1981_Intersil_Data_Book 1981 Intersil Data Book

User Manual: 1981_Intersil_Data_Book

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D~DIb

ABOUT OUR COVER

We, at Intersil, believe in using the wisdom of the past
to help turn today's ideals into tomorrow's realities. This
policy is reflected in our advertising posters, each of
which shows one of history's great thinkers.
A copy of one or all of the posters is yours for the asking.
See the back of this Product Guide tor otter details.

~mDmlm~~~IDmmDIIIIIIIIIIIIIIII

Intersil reserves the right to make changes in the
circuitry or specifications contained herein at
any time without notice.
Intersil assumes no responsibility forthe use of
any circuits described herein and makes no
representations that th~y are free from patent
. infringement.
Intersil, Inc.
10710 N. Tantau Avenue
Cupertino, California 95014
U.S.A.
Tel: (408) 996-5000
TWX: 910-338-0171 (INTRSLINT CPIO)
Printed In U.S.A. © Copyright 1981, Intersil, Inc., All Rights Reserved.

A·1

PROMs; pin-for-pin replacements, but with better
delivery time and better prices. HMOS process
provides high reliability and cost effectiveness.
Available ROMs include:
Access times are 60 ns
82HM137 (1 K x 4)
82HM141 (512 x 8) for the 137 and 141, 70 ns
82HM181 (11< x 8)
for the 181 and 185, and
80 ns for the 191.
82HM185 (2K x 4)
82HM191 (2K x 8)
o 'ICM7240/50/60 CMOS Prcigrammable Timer/
Counters-A family of RC oscillatorsitimersl
counters with selectable output counts from RC to
255 RC. High frequency operation to 13 MHz.
. Timing may be programmed from microseconds to
days, and counting modes can be straight binary
.'
or decimal.
o ICL7126 Micropower 3V2-Digit AID Converter-·
A CMOS chip which includes all active devices
needed for direct LCD interface, including seven
segment decoders, direct display drivers, reference
and clock. Capable of operation for as long as 9000
hours-nearly a year-on a single 9V battery.
.
High-accuracy features include auto-zero to less
than 10 p.V, zero drift of less than 1 p.V 1'C, input
bias current of 10 pA max, and rollover error of less
than one count.
o ICM7236 4V2 -Digit VF Counter-Driver-~ew low. power CMOS up-counter with static drivers for
vacuum fluorescent displays. High-performance
device includes decoders, output latches, count
Inhibit, reset and leading-zero blanking on a: single
chip. For fast counting, 15MHz is guaranteed and
25 MHz is typical. Maximum count to 19999.
Typical power consumption is 10 p.A.
o IM80C4811M80C35 CMOS Microprocessor-An 8-bit
single-chip microprocessor which is pin' and function compatible with the NMOS 8048/8035 while
offering the inherent low power dissipation and
excellent noise immunity typical of CMOS. Power
dissipation with a 6 MHz crystal (3 MHz internal
clock) is less than 55 mW. The devices also feature
a power-down mode which retains RAM data
integrity.
o ICM7235 4V2-Digit VF Display Decoder/Driver-.-A single-chip interface between microprocessors
and non-multiplexed 7-segment v~cuum fluorescent
displays. Available with multiplexed BCD input for
digital logic interface, or with high-speed p.P interface, and in hexadecimal (0-9, A-F) or Code B
.
.(0-9, d~!lh, E, H, L, P, blank) outputs. The CMOS
device features display blanking, static discharge
protection,' brightness control and low power
consumption.
Intersil's full range of quality integrated circuits and
discrete devices' is available through a world-wide
network of stocking distributors. Field sales offices are
located in all major market areas of the United States
and Canada to provide a high level of product support.
A complete listing of these distributors, Sales Representatives and Company Sales. Offices is included at
the end of this publication.

Intersil is ranked among the.ten largest independent
manufacturers of semiconductors in the United States.
The presen~ Intersil is the result of a 1976 merger
between Intersil, Inc., a major supplier of semiconductor. devices, and Advanced Memory Systems (AMS),
a leadmg source of add-on and add-in memories for
computers and computer-related equipment. This
strength was further augmented in 1979 by the
acquisition of Datel SystElms, inc., a company widely
known for superior data acquisition products and
. systems.
'
Intersil employs over 4000 people in its three operating divisions (Semiconductor, Memory Systems and
Datel-Intersil) and carries out product develcipment
and manufacturing activities at plants in Cupertino,
Santa Clara and Sunnyvale, California; Mansfield,
Mas,sachusetts; Bombay, India; and Singapore. The
.
company produces analog and digital integrated
,circuits, using CMOS/LSI, MOS/LSI, low-power CMOS,'
and bipolar LSI·technologies. Applications and markets
include data acquisition and processing, industrial ' ..
process control, portable and fixed instrumentation,
RF and telecommunications, data conversion, and
.
horological equipment.
Intersil's Systems Division is a major manufacturer
of add-on memories for upgrading IBMs 370, 360 and' .
303XX series of computer mainframes, j:lnd to date has
shipped and installed more than five billion bytes of
semiconductor memory. The group also manufactures
a line of standard and custom microsystems .and .
memory expansion boards for numerous micro and
minicomputer applications.
Significant new semiconductor products introduced
.
in 1980 include: .
o IVN6000K Series Vertical Power' FETs-A prcipri~
etary double-diffusion planar process yields vertical
pow~r MOS FETs with breakdown voltage ratings
as hIgh as 450V. Unique geometry of the IVN6000
series provides for low ON resistance and high'
~urrent density. Devices can switch in 10 ns, ten
tImes faster than other DMOS power transistors
, on the market.
o ICL7660 Voltage Converter-A unique CMOS chip
w~iCh converts pcisitive voltage to negative 'voltage
wIth 99.9% accuracy (RL = 55D). Power conversion
efficiency is 98% and lOUT is greater than 40 rnA.
Solves the problem of providing a second power
supply, and can be cascaded or paralleled for
greater negative voltages or more current.
o ICL7650 Ultra-Stable Op Amp-Very nearly the
"universal" op amp, in terms of error-free operation, low power consumption, DC stability and
input offset voltage. Long-term drift with .temperature is only 0.01 p.Vl'C over the full telT)perature
ra~ge. DC input bias current is only 10 pA, and
gam, CMRR and PSRR are extremely high-ih
excess . of 130 dB. High slew rate is 2.5V 1p.s. Gainbandwidth product is 2 MHz. Needs no trimming
potentiometer to. maintain stability. Phase error is
less than 10'.
o 82HM Series High-Speed ROMs-An attractive
alternative tothe hard-to-get bipolar 82S series
A·2

m

GENERAL INFORMATION
Introduction _ _ _ _ _ _ _ _---:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A-2
How to Use This Publication
A-4
A-5
8ase Number Index
Functional Index
A-8
IC Alternate Source Index
A-10
Discrete Alternate Source Index
A-14

D DISCRETES _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~1-1

fd VERTICAL POWER MOSFETs - - - - - - - - - - - - - - - - - - '-1
BJ ANALOG SWITCHES AND MULTIPLEXERS _ _ _ _ _ _---,--_ _•. _ _ _ _ 3-1

II DATA ACQUISITION _ _ _ _ _ _ _ _~_ _ _-,----_ _ _ _ _ _ _ 4-1

II
ill

BI

II

mLINEAR _ _ _ _ _ _ _ _ _ _--------------~

~

m

[iJ

i

II

TIMERS, COUNTERS, AND DISPLAY DRIVERS _ _ _ _ _ _ _ _ _ _ _ _ 6-1

CONSUMER CIRCUITS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 7-1

~DIGITAL _ _ _~_ _._ _ _ _ _~------------8~ ~

IS] APPENDIX

~------------------- 8-2

Package Dimensions _ _ _ _ _ _
High Reliability Processing
Application Note Summary
Chip Ordering Information _
Intersil Part Numbering System
Sales Offices, Distributors and Representatives

8-11
8-19
8-21
8-27
8-29

A·3

rp
L:I

a
&

BASE NUMBER INDEX
If only the basic part number is k,nown, use the Base
Number Index, as a locator aid. The Base Number
Index is organized in alpha-numeric sequence, with
prefix letters appearing in bold type. Devices are
arranged in this index according to the numeric value
of the first digit on the left, then the value of the
second digit, then the third, and so on. For example,
device number ICM7218 precedes ICL741. No
package/temperature/pin number suffixes are included,
but may be obtained from the specific product data
sheet.
FUNCTIONAL INDEX
This is an'index of Intersil device types categorized by
product grouping and function. The first major subsection, DISCRETES, is further subdivided rnto categories for JFETs, MOSFETs, and special function
devices. VMOS, the next major subsection, is arranged
according to device characteristics for rDSrONj. All
remaining major subsections (ANALOG SWLTCHES/
MULTIPLEXERS, DATJI. ACQUISITION, LINEAR,
TIMERS/COUNTERS, CONSUMER CIRCUITS, MEMORIES, MICROPROCESSORS/PERIPHERALS and
DEVELOPMENT SYSTEMS) are organized alphabetically by function within easy grouping. The Functional
Index appears in its entirety in the front matter section
of this publication, and an appropriate sub-index
appears at the beginning of each major product
"
subsection.

CROSS-REFERENCE GUIDES
Two cross-reference guides are provided, including
one for discrete devices and one for integrated circuits.
The discrete device cross reference indicates
whether Intersil can provide the industry-standard
type, or an Intersil-preferred part instead.
The IC alternate source cross-reference lists competitive manufacturer device types for which Intersi/
makes pin-for-pin replacements. In the left-hand
column, the competitive device part number is organized alphabetically by manufacturer. The Intersil pinfor-pin replacement appears in the right-hand column.
SELECTOR GUIDES
Selector guide tables appear at the front of each
major product category'subsection, and provide a
quick reference of key parameters for the devices
contained in that section.
DEVICE FUNCTION/PACKAGE CODES
Diagrams whi.ch provide decoding information for
device prefix and suffix codes are provided as rear
matter material, as are package dimensions.
DIE SELECTION CRITERIA
Many of Intersil's sl?miconductor products are available
in die form. This section contains general information
on criteria for transistor and integrated circuit die
selection, including physical parameters, packaging
for shipment, assembly, testing, and purchase options.
HIGH-RELIABILITY PROCESSING
Defines Intersil's commitment to 100 percent com.
pliance with MIL-STD-883, MIL-STD-750, MIL-M-38510
and MIL-S-19500 specifications. Also outlines Intersi/'s
programs for quality conformance, quality testing and
limited use qualification, and includes a glossary of
military/aerospace Hi-Rei terms.

NOTE:
In this publication, PRELIMINARY
is used to indicate that at the
time of printing the device was
not fully characterized. ADVANCE
INFORMATION means that the
device is in the pre.production
stages.

A·4

•••••••••••••I.

mmmm.~mlmmm.Dm~~m
TYPE #

PAGE

TYPE #

0042
0801
0802
0803
0804

5-6
4-9
4-9
4-9
4-9

o

10KM
100
100
100
101ALN

TYPE #

PAGE

PAGE

TYPE #

129
129
129
129
130

3-35
3-31
3-29
1-20
3-29

OG
OGM
IH
OG
OG

185
185
185
186
187

3-41
3-45
3-50
3-41
3-41

HA
_ HA
HA
HA
HA

2-3
1-11
1-13
5-11
5-75

IT 130

1-21
3-29
1-21
3-29
1-21

OGM
IH
3N
OG
DGM

187
187
188
188
188

3-45
3-50
1-31
3-41
3-45

HA
HA
HA
HA

10
IT
LM
LM

1-11
1-13
5-15
5-17
1-14

DG 133

U 1897
U 1898

3-50
1-31
3-41
1-50 .
1-50

LM 105

5-23
1-14
1-14
5-27
5-75

U 1899
190
190
190
190

LH
AOC
AOC
AOC
AOC
VN
10
IT
LM
ICL

101
101
101A
102
J 105

J 106
J 107
LM 107
ICL 108ALN

108
110
110
111
J 111

OG

G
IT

G

G 131
IT 131
G 132
IT 132
G 1330
OG 134
G 1340
G 1350

1-22
3-29
1-22
1-22
1-22

3N
DG
OGM
IH

139
139
140
140
141

3-37
5-41
3-31
1-24
3-31

3N
DG
OGM
IH
VCR

IT 136

G 1360
IT 137
IT 138
IT 139

2507
2510
2512
2515
2517

5-104
5-99
5-99
5-99
5-104

2520
2522
2525
2527
U 257

5-99
5-99
5-99
5-104
1-36

HA
HA
HA
2N
HA

2600
2602
2605
2607
2607

5-106
5-106
5-,106
1-51
5-107

1-50
1-31
3-41
3-45
3-50

2N
2N
HA
HA
HA

2608
2609
2620
2622
2625

1-51
1-51
5-106
5-106
5-106

191
191
191
191
2N

1-31
3-41
3-45
3-50
1-9

HA
VCR
VN
LM
LM

2627
3P
30AB
300
301A

5-109
1-9
2-5
5-11
5-15

IH 188
3N 189
OG 189

3-31
3-29
3-31
3-29
3-29

5-32
4-4
5-19
3-6
1-13

DG
LM
OG
IT
OG
OG
ICM
OG
OG
OG

142
1424
143
144
145

3-37
7-5
3-37
3-37
3-37

OG 200
IH 200

OG 112

4-4
5-33
7-4
3-9
3-6

U 200
OG 201
IH 201

3-55
3-59
1-32
3-61
3-65

J 112
0 113
J 113
LO 114
LM 114

1-13
3-9
1-13
4-4
1-16

OG
OG
DG
OG
DG

146
151
152
153
154

3-37
3-31
3-31
3-31
3-31

J 201
U 201
IH 202
J 202
U 202

1-33
1-32
3-65
1-33
1-32

G 115

3-13
3-15
3-18
1-17
3-18

3N
DG
OG
3N
OG

161
161
162
163
163

1-25
3-37
3-37
1-26

J 203
J 204

3-15
3-18
3-18
. 3-9
3-21

3N
OG
3N
3N
3N

164
164
165
166
170

1-26
3-37
1-27
1-27
1-28

LH 2111

1700
171
172
173
J 174

J 175

LM
LO
LM
OG

LO 111
LM 111
ICM 1115

0 112

DG 116

G 116
M 116
G 117
DG 118

G 118
G 119
0 120
OG 120
IT 120

o

121
OG 121
IT 121
IT 122

o

123

OG 123

G 123
IT 124
LM 124
D 125
DG 125

G 125
DG 126

G 126
IT 126

G 127
IT 127

G 128
IT 128

1-18 ,
3-9
3-21
1-18
1-18
3-25
3-15
3-13
1-19
5-36

PAGE

ICL 301ALN
LM 302

U 304
LM 305
U 305
U 306

5-75
5-19
1-37
5-23
1-37

LM 308

1-37
5-27
5-75
1-38
5-32

1-33
1-33
5-91
5-93
5-f,l5

U 308
J 309
U 309
J 310
LM 310

1-39
1-38
1-39
1-38
5-19

2114
M 2114L
2147
M 2147

5-97
8-5
8-9
8-13
8-16

LM
LM
LM
VN

1-48
1-28
1-29
1-29
1-30

2148
M 2148
LH 230lA
LH 2308
U 231

8-20
8-24
5-91
5-93
1-35

VN
2N
2N
2N
2N

35AK
3684
3685
3686
3687

2-7 1-52
1-52
1-52
1-52

LH 2310
LH 2311

DG 180

1-30
1-49
1-30
1-30
3-41

U 232
U 233
U 234

5-95
5-97
1-35
1-35
1-35

2N
2N
2N
2N
2N

3810
3811
3821
38223823

1-53
1-53
1-55
1-55
1-56

U 235
2500
25L02
2502
2502

1-35
5-99
4-11
4-11
5-99

2N3824
2N 3921
2N 3922
2N 3954
2N 3955

1-57
1-58
1-58
1-59
1-59

25L03
2503
25L04
2504
2505

4-11
4-11
4-11
4-11
5-99

2N
2N
2N
2N
2N

3956
3957
3958
3970
3971

1-59
1-59
1-59
1-60
1-60

IT
3N
3N
3N

IT 1750

J 176
J 177

LH 2,101A
LH 2108
LH 2110

3~37

3-25
3-15
3-29
3-31
3-29

OG
DGM
IH
OG
OGM

181
181
181
182
182

3-41
3-45
3-50
3-41
3-45

HA
AM
AM
HA

1-20
3-29
1-20
3-29
1-20

IH
OG
OG
DGM
IH

182
183
184
184
184

3-50
3-41
3-41
3-45
3-50

AM
AM
AM
AM
HA

A-5

LM 307
ICL 308LN

J 308

U 310
311
324
339
35AB

1-39
5-33
5-78
5-41
2-5

m

Il

BAsE NUMBER INDEX
TYPE#·

PAGE

TYPE #

TYPE #

PAGE

PAGE

TYPE #

PAGE

2N
2N
2N
VCR
VN

3972
3993
3994
4N
40AF

1-60
1-61
1-61
1-9
2-9

DG 445A
DG'446A
MM 450
MM 451
DG 451A

3-77
3-77
3-81
3-81
3-73

IH
IH
IH
IH
IH

5025
5026
5027
5028
5029

3-96
3-96
3-96
3-96
3-96

2N
2N
2N
2N
2N

5397
5398
5432
5433
5434

1-79
1-79
1-80
1-80
1-80

IH
U
U
MK
U

401
401
402
4027
403

3-68
1-41
1-41
8-212
1-41

MM
DG
DG
DG
MM

452
452A
453A
454A
455

3-81
3-73
3-73
3-73
3-81

AD
IT
IH
IH
IH

503
503
5030
5031
5032

5-49
1-45
3-96
3-96
3-96

2N
2N
2N
2N
2N

5452
5453
5454
5457
5458

1-81
1-81
1-81
1-82.
1-82

U
2N
2N
U
U

404
4044
4045
405
406

1-41
1-62
1-62
1-41·
1-41

VN
DG
DG
DG
DG

46AF
461A
462A
463A
464A

2-11
3-77
3-77
3-77
3-77

IH
IH
IH
IH
IH

5034
5035
5036
5037
5038

3-96
3-96
3-96
3-96
3-96

2N
2N
2N
2N
2N

5459
5460
5461
5462
5463

1-82
1-83
1-83
1-83
1-83

2N
ITE
2N'
ITE
2N

4091
4091
4092
4092
4093

1-64
1-64
1-64
1-64
1-64

2N
2N
2N
2N
2N

4856
4857
4858
4859
4860

1-72
.1-72
1-72 .
1-72
1-72

IT
IH
IH
IH
IH

504
5040
5041
5042
5043

1-45
3-103
3-103
3-103
3-103

2N
2N
2N
2N
2N

5464
5465
5484
5485
5486

1-83
1-83
1-84
. 1-84
1-84

ITE
U
2N
U
2N

4093
410
4100
411
4117

1-64
1-42
1-62
1-42
1-65

2N
2N
2N
2N
2N

4861
4867
4868
4869
4878

1-72
1-73
1-73
1-62

IH
IH
IH
IH
IH

5044
5045
5046
5047
5048

3-103.
3-103
3-103
3-103
3-103

MM
MM
2N
2N
2N

550
551
5515
5516
5517

3-81
3-81
1-85
l-85
1-85

2N
2N
U
U
U

4118
4119
412
421
422.

1-65
1-65
1-42
1-43
1-43

2N
. 2N
VCR
IT
IVN

4879
4880
5P
500
5000AN

1-62
1-62
1-9
1-45
2-13

IH
IT
IH
IH
IH

5049
505
5050
5051
5052

3-103
1-45
3"103
3-103
. 3-111

2N
2N
MM
2N
2N

5518
5519
552
5520
5521

1-85
1-85
3-81
1-85
1-85

2N
2N
2N
2N
2N

4220
4221
4222
4223
4224

1-66
1-66
1-66
1-67
1-67

IVN
IVN
IVN
IVN
IH

5000AZ
5000B
50005
5000T
5001

2.21
2-15
2-17
2-19
3-83

IH
IH
IH
IH
IH

5053
5101
5108
5110
5111

3-111
5-113
3-118
5-115
5-115

2N
2N
2N
MM
NE

5522
5523
5524
555
555

1-85
1-85
1-85
3-81
6-3

U
U
U
LM
DG

423
424
425
4250
426A

1-43
1-43
1-43
5-111
3-73

IVN
IVN
IVN
IVN
IH

5001A
5001B
50015
500n
5002

2-13
2-15
2-17
2-19 .
3-83

IH
IH
2N
IH
2N

5112
5113
5114
5114
5115

5-115
5-115
5-115
1-75
1-75

SE
NE
SE
2N
2N

555
556
556
5564
5565

6-3
6-7
. 6-7
1-87
1-87

U
DG
DG
2N
2N

426
429A
433A
4338
4339

1-43
3-73
3-73
1-68
1-68

IH
IH
IH
IH
IH

5003
5004
5005
5006
5007

3-85
3-85
3-87
3-87
3-87

IH
2N
2N
2N
2N

5115
5116
5117
5118
5119

5-115
1-75
1-77
1-77
1-77

2N
1M
1M
1M
1M

5566
5600
5603
5.604
5610

1-87
8-39
8-42
8-48
8-39

DG
2N
2N
2N
DG

434A
4340
4341
4351
439A

3-73
1-68
1-68
1-69
3-77

IH
IT
IH
IH
IH

5009
501
5010
5011
5012

3-91
1-45
3-91
3-91
3-91

IH.5140
IH 5141
IH 5142
IH 5143
IH 5144

3-127
3-127
3-127
3-127
3-127

1M
1M
2N
2N
2N

5623
5624
5638
5639
5640

8-42
8-48
1-88
1-88
1-88

2N
ITE
2N
ITE
2N

4391
4391
4392
4392
4393

1-70
1-70
1-70
1-70
1-70

IH
IH
IH
IH
IH

5013
5014
5015
5016
5017

3-91
3-91
3-91
3-91
3-91

AD
2N
2N
2N
2N

590
5902
5903
5904
5905

5-55
1-89
1-89
1-89
1-89'

ITE
DG
U
DG
U

4393
440A
440
441A
441

1-70
3-73
1-44
3-73
1-44

3-127
1-78
1-78
1-78
1-78
3-55

2N
IH
2N
IH
IT

5018
5018
5019
5019
502

1-74
3-91
1-74
. 3-91
1-45

2N
2N
2N
2N
2N

5906
5907
5909
5911

1-89
1-89
1-89
1-89
1-90

2N
ITE
DG
DG
DG

4416
4416
442A
443A
444A

1-71
1-71
3-77
3-77
3-77

IH
IH
IH
IH
IH

5020
5021
5022
5023
5024

3-91'
3-91
3-91
3-91
3-91

5911
5912
5912
6000K
6100

1-90
1-90
1-90
2-31
8-55

1~73

A-6

IH
2N
. 2N
2N
2N
IH

5145
5196
5197
5198
5199
5200

1M
IVN
IVN
IVN
IH
IVN

5200
5200H
5200K
5200T'
5201
5201C

IVN
IVN
IVN
IH
SU

5201H
5201K
520n
5208
536

8-28
2-23
2-25
2-27
3-61
. 2-29
2-23
2-25
2-27
3-135
5-52

IT
2N
IT
IVN
1M

590S'

BASE NUMBER INDEX
TYPE #

PAGE

TYPE #

PAGE

TYPE #

8~77

7045A
7049A
7050
7051
7101

7-15
7-4
7-24
7-4
4-96

ICM
ICM
ICM
ICM
ICM

7242
7245
7250
7260
7270

6-134
7-56
6-123
6-123
7-2

ICL
ICL
ICL
ICL
ICL

8018A
8019A
8020A
8021
8022

4-88
4·88
4-88
5·187
5·187

PAGE

TYPE #

PAGE

1M
1M
1M
IH
IH

6101
6102
6103
6108
6116

8-97
8-120
3-143
3-149

ICM
ICM
ICM
ICM
ICL

IH
IH
IH
1M
1M

6201
6208
6216
6312
6316

3-155
3-159
3-165
8-132
8-139

ICL
ICL
ICL
ICL
ICL

71C03
7104
7106
7107
7109

4-104
4-118
4-17
4-17
4-26

ICM
ICM
ICM
ICM
/LA

7271
7272
7273
7307
733

7·60
7-66
7·2
7-4
5·63

ICL
ICL
ICL
ICL
ICL

8023
8038
8043
8048
8049

5·187
5-190
5·198
5·205
5-205

1M
1M
2N
2N
2N

6402
6403
6483
6484
6485

8-144
8-144
1-91
1-91
1-91

ICL
ICL
ICL
ICL
1M

7116
7117
7126
7135
7141

4-42
4-42
4-50
4-58
8-219

1M
1M
/LA
/LA
AD

7332
7364
740
741
741K

8·227
8·230
5·66
5-70
5·74

ICL
ICL
ICL
ICL
ICL

8052
8053
8063
8068
8069

4·104
4-135
5·213
4·104
5-221

IMF
1M
1M
1M
1M

6485
6504
65X08
6512
6514

1-93
8-152
8-157
8-163
8-169

1M
ICM
ICM
ICM
ICM

7141M
7201
7206
7207
7207A

8-223
6-9
7-28
6-11
6-11

ICL
ICL
/LA
AD
AD

741HS
741LN
748
7520
7521

5·72
5·75
5·78
4·68
4·68

1M 82C43
82HM137
82HM141
82HM181
82HM185

8-233
8-237
8-240
8-243
8-247

1M
1M
1M
VN
VN

65X18
65X51
65X61
66AF
66AK

8-157
8-174
8-174
2-11
2-7

ICM
ICM
ICM
ICM
ICM

7208
7209
7210
7211
7212

6-15
6-22
7-2
6-25
6-25

AD
AD
AD
AD
AD

7523
7530
7531
7533
7541

4-74
4-68
4-68
4-78
4-82

ICL
ICL
MFE
ICH

82HM191
8211
8212
823
8500

8·251
5·223
5·223
1·47
5·233

1M
1M
IVN
2N
IVN

6653
6654
6660
6660
6661

8-180
8-180
2-37
2-39
2-37

ICM
ICM
ICM
ICM
, ICM

7213
7214A
7215
7216
7217

6-35
7-2
7-36
6-40
6e55

ICM
ICM
ICL
ICL
ICL

7555
7556
7600
7601
7605

6·140
6-140
5·121
5·121
5·130

ICH
ICH
ICH
ICH
VN

8510
8515
8520
8530
88AF

5·239
5·247
5·239
5·239
2·11

2N
VN
VN
VN

6661
67AB
67AF
67AK
6801

2-39
2-5
2-9
2-7
8-187

ICM
ICM
ICM
ICM
ICM

7218
7220A
7220FA
7220MA
7220MFA

6-67
7-2
7-2
7-2
7-2

ICL
ICL
ICL
ICL
ICL

7606
7611
7612
7613
7614

5-130
5-140
5·140
5-140
5·140

VN
VN
VN
VN
VN

89AB
89AF
90AB
98AK
99AK

2-5
2-9
2-5
2-7
2-7

6901
6910
6912
6914
6915

8-191
8-192
8-196
8-197
8-198

ICM
ICM
ICM
ICM
ICM

7223
7223A
7223VF
7224
7225

7-42
7-3
7-48
6-76
6-76

ICL
ICL
ICL
ICL
ICL

7615
7621
7622
7631
7632

5·140
5-140
5·140
5·140
5·140

6920
6941
6942
6950
6970-IFDOS

8-200
8-201
8-201
8-205
8-211

ICM
ICM
/LA
ICM
ICM

7226
7227
723
7231
7232

6·83
6·55
5·57
6·94
6·94

ICL
ICL
ICL
ICL
/LA

7641
7642
7650
7660
777

5·140
5-140
5-155
5·161
5-85

7N
7027
7038A
7038B/D/E/G
7045

1-9
8-212
7-4
7-11
7-15

ICM
ICM
ICM
ICM
ICM

7233
7234
7235
7236
7240

6-94
6-94
6-112
6-118
6-123

ICL
ICL
ICL
ICL
ICL

8001
8007
8008
8013
8017

5·167
5-171
5-172
5·176
5·183

VCR
1M
ICM
ICM
ICM

A·7

a

•••••••••••••••••

m~~SDD~~ml.D~~mm
EDiSCRETES

2N3921/22
2N3954-58
2N5196-99
2N5452-54
2N5515-24
2N5902-9

JFET Single
Switches
N-Channel
J105-7
J111-13
U200-2
U1897-99
2N3970-72
2N4091-93
ITE4091-93
2N4391-93
ITE4391:93
2N4856-61
2N5432-34
2N5638-40
P-Channel

IT100/1
J174-77

2N3993/4
2N5018/19
2N5114-16

Page
1-14
1-15
1-32
1-50
1-60
1-64
1-64
1-70
1-70
1-72
1-80
1-88
1-13
1-30
1-61
1-74
1-75

JFET Dual Switches
N-Channel
2N5564-66

1-87

JFET Single
Amplifiers
N-Channel
J201-4
J308-10
U308-10
2N3684-87

2N3821/22
2N3823
2N3824
2N4117-19
2N4220-22

2N4223/24
2N4338-41
2N4416
ITE4416
2N4867-69

2N5397/98
2N5457-59
2N5484-86
P-Channel
U304-6
2N2607-9
2N5460-65

1-33
1-38
1-39
1-52
1-55
1-56
1-57
1-65
1-66
1-67
1-68
1-71
1-71
1-73
1-79
1-82
1-84
1-37
1-51
1-83

JFET Dual
Amplifiers .
N-Channel
U231-35
U257
U401-6
U421-26

U440/41
IT500-5

2N5911/12
IT5911/12
2N6483-85
IMF6485

BVOSS < 100V,
rOS(on) < 0.50

1-58
1-59
1-78
1-81
1-85
1-89
1-90
1-90
1-91
1-93

BVoss < 100V,
rOS(on) < 50

MOSFET Switchesl
Amplifiers
N-Channel
M116

3N170/71
IT1750
2N4351 .
P-Channel
3N161

3N163/64
3N172/73
IT1700
MFE823
Dual P-Channel
3Ni65/66
3N188-91

1-17
1-28
1-49
1-69
1-25
1-26
1-29
1-48
1-47
1-27
1-31

IT126/27
IT140

2N4044/45
2N4100
2N48Z8-80
PNP Devices
1T130-32
IT136-39

2N3810/11
2N5117-19

1-16
1-18
1-19
1-20
1-24
1-62
1-62
1-62

1-35
1-36
1-41
1-43
1-44
1-45

Special Function

Analog Switches
with Drivers

High Speed Dual Diodes
10100/1
1-11
Voltage Controlled
Resistors
VCR2-7
1-9

OG111/112
OG116/118/123/125
OG120/121

IVN6000KN Series

OG126A Family
OG139A Family
OG180 Family
OGM181 Family
IH181 Family
·OG200
IH200
OG201
IH201/202
IH401
IH5001/2
IH5003/4

IH5005/6/7
2-31

IH5009-24
A-8

TTL or CMOS to
Higher Levels
IH6201

AID Converters
3-118
3-135
3-143
3-149
3-159
3-165

0129

BVoss> 350V,
rOS(on) < 50

Digital Translatorl
Analog Driver

Multiplexers

0112/1131120/121
0123/125

VERTICAL POWER
MOSFETS

3-1:
G116-19
3-1~
G125-32,
3-2~
G 1330/40/50/60
3-8;
MM450/550,
MM451/551,
M M452/552/M M455/555

DATA
ACQUISITION

Analog Switch
Drivers

1-21
1-22
1-53
1-77

3-113-12i
3-51
3-6i

Analog Switches
without Drivers

ANALOG
SWITCH ES AN D
MULTIPLEXERS

IH5108
IH5208
IH6108.
IH6116
IH6208
IH6216

3-9(

3-10~

G115/123
2-3
2-5
2-7
2-9
2-11
2-13
2-15
2-17
2-19
2-21
2-37
2-39

VN10KM
VN30AB Series
VN35AK Series
VN40AF Series
VN46AF Series
IVN5000/1AN Series
IVN5000/1 BN Series
IVN5000/1SN Series
IVN5000/HN Series
IVN5001AZ Series
IVN6660/61 Series
2N6660/61 Series

Bipolar Dual
Amplifiers
NPN Devices
LM114
IT120-22
IT124

2-23
2-25
2-27
2-29

IVN5200/1 H N Series
IVN5200/1KN Series
IVN5200/HN Series
IVN5201CN Series

IH5025-38
IH5040-51
IH5052/3
IH5140-45
IH5200
IH5201

3-151

L0110/111/114
4-·
4-2(
ICL7109
4-5(
ICL7126
4-51
ICL7135
ICL8052/3
4-131
ICL8068/8052A/7104 4-111

D/A Converters
AOC0801-4
3-9
3-25
3-35

A07520/21/30/31
A07523
A07533
A07541

4-!
4-61
4-7'
4-71
4-8:

DVM Circuits
3-6
3-16
3-22
3-31
3-37
3-41
3-45
3-50
3-55
3-59
3-61
3-65
3-68
3'83
3-85
3-87
3-91

ICL7106/7
ICL7116/17
ICL8052/7101
ICL8052/71C03
ICL8068/71C03

4-1~

4-4:
4-9!
4-10·
4-10·

Successive
Approximation
Registers
AM25(L)02/3/4

4-1

D/A Current \
Switches
ICL8018/19/20

4-81

INEAR

mplifiers

river Amplifier for
)werTransistors
Page
;L8063
5·213
river Amplifier for
I:tuators, Motors
;H8510/20/30
5·239
;H8515
5·247
strumentation,
Dmmutatlng Auto·Zero
U605/6
5·130
)g·Antiiog
:L8048/49
5·205
perational,
l10pper Stabilized
;L7650 '
5·155
perational,
Dmmutatlng Auto·Zero
U600/1
5·121
peration'al, FET Input
-i0042
5·6
D503
5·49
J/NE§36
5·52
,740
5·66
;L8007
5·171
;L8043
5·198
;H8500
5·233
perational, General
upose
111101/301
5·15
111107/307
5·27
111108/308
5·32
111124/324
5·38
,741
5·70
,
U41HS
5·72
D741K
5·74
:L741LN
5·75
,748
5·78
,777 '
5·85
-12101/2301
5·91
-12108/2308
5·93 '
15101
5·113
:L8008
5·174
peratlonal, High
Ipedance
~2600Family
5·106
~2607/27
5·109
perational, High Speed
~2500 Family
5·99
~2507/17/27
5·104
:L8017
5·183,
peratlonal, Low Power
1114250
5·111
:L76XX Series
5·140
:L8021·23
5·187
deo
,733
5·63

omparators
~al

-12111/2311

5·97

Followers
LM102/302
LMll0/310
LH2110/2310
Low Power
iCL8001
Precision
LMlll/311
Quad
LM139/339
Sample and Hold
IH5110·15
Temperature Sensor
AD590
Voltage Reference
ICL8069
ICL8211/12
Voltage Regulators
LM100/300
LM105/305
p,A723 '

Oscillator/Clock
Generator

5·19
5·19
5·95

ICM7209
ICM7213

5·167
5·33

Low Battery
Indicator

5·41

,ICM7201

CONSUMER
CIRCUITS

5·55
5·221
5·223

Watches

5·11
5·23
5·57

ICM1424C/MC
ICM7245
ICM7271
ICM7272

ICM7038
ICM7050
ICM7223 '
ICM7223VF

ICM7045
ICM7045A
ICM7215

ICM7206
6·3
6·7
6·123
6·134
6·140
6·140

6·15
6·40
6·55
6·76
6·83
6·118

Counter Timebase
ICM7207(A

Display

6·11

Driver~

ICM7211/12
ICM7218
' ICM7231·34
ICM7235

6·25
6·67
6·94
6·112

IM6100
6801 Sampler Kit

7·15
7·15
7·36

IM6101
IM6102
IM6103 ,
IM6402/3
82C43

Touch Tone
Encoders

Timers

8·132
8·139
8·180
8·180
8·200
8·28
8·39
8·~2

8·48
8·53

8·55
8·187

Peripherals
8·77
8·97
' 8·120
8·144
8·233

Development
Systems
7·28

DIGITAL
Memory
NMOS Static RAMs
' 2114
8·5
M2114L
8·9
2147
8·13
M2147
8·16
2148
8·20
8·24,
M2148
,7141
8·219
7141M
8·223
CMOS Static RAMs
IM6504
8·152
IM65X08
8·157
IM6512
8·163
IM6514
8·169
8.157
IM65X18
IM65X51
8·174
8·174
IM65X61
NMOS Dynamic RAM
IM7027/4027
8·212

A·9

8·230
8·237
8·240
8·243
8·247
8·251"

Microprocessor
7·11
7·24
7·42
7·48

Stopwatches

TIMERS,
COUNTERS AND
DISPLAY DRIVERS

Counters

7·5
7·56
7·60
7·66

Clocks

Multiplier
ICL8013
5·176
Voltage Converter
ICL7660
5·161
Waveform Generator
ICL8038
5·190

ICM7208
ICM7216
ICM7217/27
ICM7224/25
ICM7226
ICM7236

6·9

5·115

Special Function

NE/SE555
NE/SE556
ICM7240/50/60
ICM7242
ICM7555
ICM7556

6·22
6·35

~227r1

NMOS ROMs
IM7332
IM7364
82HM137
82HM141
82HM181
82HM185
82HM191
CMOS ROMs
IM6312
IM6316
CMOS EPROMs
IM6653
IM6654
6920 EPROM
Programmer
Bipolar PROMs
IM5200FPLA
IM5600/10
IM5603/23
IM5604/24
Bipolar PROM
Programming
Specifications

Intercept Jr.
8·205
8·192
Intercept II
Intercept CPU with Dual
Serial 1/0
8·196
Double Density
Flexible Disc
Controller
8·197
Concept·48
8·201
4Kx12 CMOS
Memory Module
8·191
32Kx 12 RAM
Board
8·198
6970 Disc Operating
,System
8·211

AMD
AM2502
AM2503
AM2054
LF155
LFl56
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2301
LH2311
LM10l
LM102
LM105
LM107
LM108
LMll0
LMlll
LM124
LM201
LM202
LM205
LM207
LM208
LM210
LM211
LM224
LM301
LM302
LM305
LM307
LM308
LM310
LM311
LM324
NE555 ,
NE556
723
7'\1 .
741
748

Interilll
AM2502
AM2503
AM2504
LFl55
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2301
LH2311
AD10l
LM102
LM1D5
LM107
LM108
LMll0
LMlll
LM124
AD201
LM202
LM205
LM207
LM208
LM210 .
LM211
LM224
.AD301.
LM302
LM305
LM307
LM308
LM310
LM311
LM324
NE555
NE556
LM723
j£A733
ICL741
LM748

AMI

Intersll

S6508
S6518

IM65X08
·IM65X18

AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN·
AD7521LD
AD7521LN
AD7521SD
AD7521TD
AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD'
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
'AD7533TD
AD7533UD
AD7541AD
.AD7541BD
AD7541JN
AD7541KN
AD7541SD
AD7541TD

AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD
AD7521TD
AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN
. AD7541KN
AD7541SD
AD7541TD

Analog Devices

Interall

Datel

Intersll

AD10l
AD108
AD201
AD208
AD301
AD308
AD503
AD590
AD741
AD7506/COM/CHIPS
AD7506/MILJCHIPS
AD7506JD
AD7506JD/883B
AD7506JN
AD7506KD
AD7506KD/883B
AD7506KN
AD7506SD
AD7506SD/883B
AD7506TD
AD7506TD/883B
AD7507/COM/CHIPS
AD7507/MILJCHIPS
AD7507JD
AD7507JD/883B
AD7507JN
AD7507KD
AD7507KD/883B
AD7507KN
AD7507SD
AD7507SD/883B
AD7507TD
AD7507TD/883B
AD7520JD
AD7520JN
AD7520KD

AD101
LM108
AD201
LM208
AD301
LM308
AD503
AD590
AD741
IH6116C/D
IH6116M/D
IH61.16CJI
IH6116CJI/883B
IH6116CPI
IH6116CJI
IH6116CJI/883B
IH6116CPI
IH6116MJI
IH6116MJI/883B
IH6116MJI
IH6116MJI1883B
IH6216C/D
IH6216M/D
IH6216CJI
IH6216CJI/883B
IH6216CPI
IH6216CJI
IH6216CJ1/883B
IH6216CPI
IH6216MJI
IH6216MJI/883B
IH6216MJI
IH6216MJI/883B
AD7520JD
AD7520JN
AD7520KD

AM5402

HA2505
HA2525

EMM/sEMI

Intersll

2114

2114

Exar

Intersll

XR2240
XR4741
XR555
XR556
XR8038
XRL555
XRL556

ICL7240
LMl48
NE555
NE556
ICLB038
ICL7555
ICL7556

Fairchild

Intersll

j£AF155
pAF156
j£AF157
j£AF255
j£AF256
pA257
j£AF355
j£AF356
j£AF357
j£Al0l
j£Al02
j£Al05
pAl 07
j£Al08
j£All0
pAll1
j£A124
j£A201

LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
AD10l
LM102
LM105
LM107
LM108
LMll0
LMlll
LM124
AD201

A-10

j£A202
p.A205
j£A207
,..A208
p.A210
j£A211
pA224
j£A301
j£A302

::t~~

j£A308
j£A310
j£A311
"A324
j£A3302·
j£A555
j£A556
j£A723
j£A733
pA740
j£A741
j£A748

~777
4721

LM202
LM205
LM207
LM208
LM210
LM211
LM224
AD301
LM302
LM305
LM307
LM308
LM310
LM311
LM324
MC3302
NE555
NE556
LM723

t0
t0

733
M740
741
M748

~777
M65X51

F4736
M4027
93417
93427
93436
93446

IM65X08
MK4027
IM5603
IM5623
IM5604
IM5624

Fujitsu

Intersll

MBM4044
MB7051
MB7052
MB7053
MB7056
MB7057
MB7058
MB8114
MB8227
MB8401
MB8411
. Harris
HA2500
HA2502
HA2505
HA2507
HA251 0
HA2512
HA2515
HA2517
HA2520
HA2522
HA2525
HA2527
HA2600
HA2602
HA2605
HA2607
HA2620
HA2622
HA2625
HA2627
HA2720
HD6402
HID-0506-6
Hll-0506-2
Hll-0506-5
HI1-0506-6
HI3-0506-5
HID-0507-6
Hll-0507-2
Hll-0507-5
Hll-0507-8
HI3-0507-5
HID-02OD-6
Hll-020D-2
Hll-0200-4
Hll-020D-5
Hll-0200-8

IM7141
IM5610
IM5623
'IM5624
IM5600
IM5603
IM5604
IM2114
MK4027
IM65X08
IM65X16
Intersll
HA2500
HA2502
HA2505
HA2507
HA251 0
HA2512
HA2515
HA2517
HA2520
HA2522
HA2525
HA2527
HA2600
HA2602
'HA2605
HA2607
HA2620
HA2622
HA2625
HA2627
ICL8021
IM6402
IH6116C/D
IH6116MJI
IH6116CJI
IH6116MJI/883B
IH6116CPI
IH6216C/D
IH6216MJI
IH6216CJI
IH6216MJI/883B
IH6216CPI
IH200BID
DG200B/D
IH200AK
DG200AK
IH200BK
DG200BK
IH200BK
DG200BK
IH200AKl883B
DG200AKl833B

Ie Alternate Source Index (continued)
continued
HI2-0200-2

HI3-0201-5
H10-5040-6
HI1-5040-2
HI1-5040-5
HI1-5040-8
H10-5041-6
HI1-5041-2
HI1-5041-5
HI1-5041-8
HI0-5042-6
HI1-5042-2
HI1-5042-5
HI1-5042-8
HI0-5043-6
HI1-5043-2
HI1-5043-5
HI1-5043-8
HI0-5044-6
HI1-5044-2
HI1-5044-5
HI1-5044-8
HI0-5045-6
HI1-5045-2
HI1-5045-5
HI1-5045-8
HI0-5046-6
HI1-5046-2
HI1-5046-5
HI1-5046-8
HI0-5047-6
HI1-5047-2
HI1-5047-5
HI1-5047-8
HI0-5048-6
Hll·5048-2
HI1-5048-5
HI1-5048-8
H10-5049-6
HI1-5049-2
HI1-5049-5
HI1-5049-8
HI0-5050-6
H11-5050-2
H11-5050-5
H11-5050-8
H10-5051-6
HI1-5051-2
HI1-5051-5
HI1-5051-8
HM6100
HM6101
HM6102
HM6103
HM6312
HM6508
HM6518
HM6551
HM6561
HM7603
HM7610
HM7611
HM7620
HM7621

IH200AA
DG200AA
IH200BA
DG200BA
IH200BA
DG200BA
IH200AN883B
DG200AN883B
DG200CJ
IH201C/D
DG201B/D
IH201MJE
DG201AK
IH201CJE
DG201BK
IH201CJE
DG201BK
IH201 MJE/883B
DG20 1AK/883B
DG201CJ
IH5040C/D
IH5040MJE
IH5040CPE
IH5040MJE/883B
IH5041C/D
IH5041MJE
IH5041CPE
IH5041MJE/883B
IH5042C/D
IH5042MJE
IH5042CPE
IH5042MJEl883B
IH5043C/D
IH5043MJE
IH5043CPE
IH5043MJE/883B
IH044C/D
IH5044MJE
IH5044CPE
IH5044MJEL883B
IH5045C/D
IH5045MJE
IH5045CPE
IH5045MJE/883B
IH5046C/D
IH5046MJE
IH5046CPE
IH5046MJEl883B
IH5047C/D
IH5047MJE
IH5047CPE
IH5047MJE/883B
IH5048C/D
IH5048MJE
IH5048CJE,CPC
IH5048MJEl883B
IH5049C/D
IH5049MJE
IH5049CJE,CPE
IH5049MJE/883B
IH5050C/D
IH5050MJE
IH5050CJE,CPE
IH5050MJE/883B
IH5051C/D
IH5051MJE
IH5051 CJE,CPE
IH5051 MJE/883B
IM6100
IM6101
IM6102
IM6103
IM6312
IM65X08
IM65X18
IM65X51
IM65X61
IM5610
IM5603
IM5623
IM5604
IM5624

Intel

Intersli

2104A

IM7027
MK4027
2114
IM7141
IM5604'
IM5605
IM5624
IM80C49
IM87C41

HI2-0200-4
HI2-0200-5
HI2-0200-8
HI3-0200-5
HI0-0201-6
Hll-0201-2
Hll-0201-4
Hll-0201-5
HI1-0201-8

2114
2141
3602
3604
3622
8049
8741

Maruman

Intersli

MIC2114

2114

MlcroPower
Systems

Intersli

MP7520JD
MP7520JN
MP7520KD
MP7520KN
MP7520LD
MP7520LN
MP7520SD
MP7520TD
MP7520UD
MP7521JD
MP7521JN
MP7521KD
MP7521KN
MP7521LD
MP7521LN
MP7521SD
MP7521TD
MP7521UD
MP7523JN
MP7523KN
MP7523LN
MP7530JD
MP7530JN
MP7530KD
MP7530KN
MP7530LD
MP7530LN
MP7531JD
MP7531JN
MP7531KD
MP7531KN
MP7531LD
MP7531LN
MP7533AD
MP7533BD
MP7533CD
MP7533JN
MP7533KN
MP7533LN
MP7533SD
MP7533TD
MP7533UD
MP7621AD
MP7621BD
MP7621JN
MP7621KN
MP7621SD
MP7621TD

AD7520JD
AD7520JN
AD7520KD
, AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD
AD7521TD
AD7521UD
AD7523JN
AD7523KN
AD7523LN
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
.AD7531JD
AD7531JN
AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN
AD7541LN
AD7541SD
AD7541TD

MMI

Intersli

5300-1
5301-1
5305-1
5306-1
5330-1
5331-1
6300-1
6301-1
6305-1
6306-1
6330-1
6331-1

IM5603
IM5623
IM5604
IM5624
IM5600
IM5610
IM5603
IM5623
IM5604
IM5624
IM5600
IM5610

Mostek

Intersli

MK4027

IM7027
MK4027

Motorola

Intersli

LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LM10l
LM105
LM107
LM110
LM111
LM124
LM201
LM205
LM207
LM208

LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
AD10l
LM105
LM107
LMll0
LMlll
LM124
AD201
LM205
LM207
LM208

A-11

LM210
LM211
LM224
LM301
LM305
LM307
LM308
LM310
LM311
LM324
MCM2114
MC1723
MC1741
MC1748
MC3302
National
Semiconductor
AD7520JD (DAC1022LCD)
AD7520JN (DAC1022LCN)
AD7520KN (DACl 021 LCD!
_ AD7520KN (DAC1021 LCN
AD7520LD (DAC1020LCD)
AD7520LN (DAC1020LCN)
AD7520SK (DAC1022LD!
AD7520TD (DACl 021 LD
AD7520UD ~ACl 020LD
AD7521JD ( AC1222LC 6 )
AD7521JN (DAC1222LCN)
AD7521KD lDAC1221 LCD!
AD7521KN DAC1221 LCN
AD7521 LD lDAC1220LCD
AD7521 LN DAC1220LCN)
AD7521 SO (DAC1222LD)
AD7521TD (DAC1221 LD)
AD7521UD ~AC1220LD6
AD7530JD ( AC1022LC )
AD7530JN (DAC1022LCN)
AD7530KD (DAC1021 LCD)
AD7530KN (DAC1 021 LCNI
AD7530LD (DAC1020LCD
AD7530LN (DAC1020LCN)
AD7531JD (DAC1222LCD)
AD7531JN (DAC1222LCN)
AD7531KD (DAC1221 LCD)
AD7531KN (DAC1221 LCN)
AD7531 LD (DAC1220LCD!
AD7531 LN (DAC1220LCN
AD7533AD (DAC1022LCD)
AD7533BD (DAC1021 LCD!
AD7533CD (DAC1020LCD
AD7533JN (DAC1022LCN)
AD7533KN (DAC1021 LCN)
AD7533LN (DAC1020LCN)
AD7533SD (DAC1022LDI
AD7533TD (DACl 021 LD
AD7533UD (DAC1020LD)
AH0126CD
AH0126D
AH0126D/883
AH0129CD
AH0129D
AH0129D/883
AH0133CD
AH0133D
AH0133D/883
AHOl34CD
AHOl34D
AHOl34D/883
AH0139CD
AH0139D
AH0139D/883
AH0140CD
AH0140D
AH0140D/883
AH0141CD
AH0141D
AH0141D/883
AH0142CD
AH0142D
AH0142D/883
AH0143CD
AH0143D
AH0143D/883
AHOl44CD
AHOl44D
AHOl44D/883
AD0145CD
AH0145D
AH0145D/883
AH0146CD
AH0146D
AH0146D/883
AH0151CD

LM210
LM211
LM224
AD301
LM305
LM307
LM308
LM310
LM311
LM324
2114
LM723
ICL741
LM748
MC3302

Intersli
AD7520JD
AD7520KD
AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD
AD7521TD
AD7521UD
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD
AD7533UD
DG126BK
DG126AK
DG 126AK/883B
DG129BK
DG129AK
DG129AK/883B
DG133BK
DG133AK
DG 133AK/883B
DGl34BK
DG134AK
DG 134AK/883B
DG139BK
DG139AK
DG139AK/883B
DG140BK
DG140AK
DG 140AK/883B
DG141BK
DG141AK
DG141AK/883B
DG142BK
DG142AK
DG 142AK/883B
DG143BK
DG143AK
DG 143AK/883B
DGl44BK
DGl44AK
DG 144AK/883B
DG145BK
DG145AK
DG 145AK/883B
DG146BK
DG146AK
DG 146AK/883B
DG151BK

m

a

Ie Alternate Source Index (continued)
continued

AH0151D
AH0151D/BB3
AH0152CD
AH0152D
AH0152D/BB3
AH0153CD
AH0153D
AH0153D/BB3
AHOl54CD
AHOl54D
AH0154D/BB3
AH0161CD
AH0161D
AH0161 D/883
AH0162CD
AH0162D
AH0162D/BB3B
AH0163CD
AH0163D
AH0163D/B83
AH0164CD
AH0164D
AH0164D/B83
AH5009CN
AH5010CN
AH5011CN
AH5012CN
AN5013CN
AH5014CN
AH5015CN
AH5016CN
AM9709CN
AM97C09CN
AM9710CN
AM97Cl0CN
AM9711CN
AM97CllCN
AM9712CN
AM97C12CN
DM54S1B8
DM54S287
DM54S288
DM54S387
·DM74S188
DM74S2B7
DM74S288
DM74S387
LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LFl1201D
LFl1201D/883
LFl1202D
LF11202D/883
LFl150BD
LFllS08D/883
LFl1509D
LFl1509D/883
LH0042
LH2101
LH210B
LH2110
LH2111
LH2301
LH230B
LH2310
LH2311
LM100
LM10l
LM102
LM105
LM107
LM10B
LMll0
LMlll
L~124
L 200
LM201
LM202
LM205
LM207
LM20B
LM210

DG151AK
DG151AKlBB3B
DG152BK
DG152AK
DG 152AKlBB3B
DG153BK
DG153AK
DG153AKl883B
DG154BK
DG154AK
DG154AKlBB3B
DG161BK
DG161AK
DG161AKlBB3B
DG162BK
DG162AK
DG162AKlBB3B
DG163BK
DG163AK
DG 163AKl883B
DGl64BK
DGl64AK
DG 164AKl8B3B
IH5009CPD
IH5010CPD
IH5011CPE
IB5012CPE
IH5013CPD
IH5014CPD
IH5015CPE
IH5016CPE
IH5009CPD
IH5009CPD
IH5010CPD
IH5010CPD
IH5011CPE
IH5011CPE
IH5012CPE
IH5012CPE
IM5600
IM5623
IM5610
IM5603
IM5600
IM5623
IM5610
IM5603
LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
IH201MJE
DG201AK
IH201 MJE/883B
DG201AKl883B
IH202MJE
DG202AK
IH202MJE/B83B
DG202A1B83B
IH6108MJE
IH6108MJE/883B
IH6208MJE
IH6208MJ E/883B
LH0042
LH2101
LH2108
I LH2110
LH2111
LH2301
LH2308
LH231 0
LH2311
LM100
AD10l
LM102
LM105
LM107
LM108
LMll0
LMlll
LM124
LM200
AD201
.LM202
LM205
LM207
LM20B
LM210

LM211
LM224
LM2902
LM300
LM301
LM302
LM305
LM307
LM30B
LM310
LM311
LM4250
LM555
LM556
LM723
LM733
LM740
LM741
LM742
MC3302
MM2114
MM450
MM451
MM452
MM455
MM5257
MM550
MM551
MM552
MM555
MM74C920
MM74C929
MM74C930

LM211
LM224
LM2902
LM300
AD301
LM302
LM305
LM307
LM30S'
LM310
LM311
LM4250
NE555
NE556
LM723
p.A733
LM740
LM741
LM74B
MC3302
2114
MM450
MM451
MM452
MM455
IM7141
MM550
MM551
MM552
MM555
IM65X51
IM65X08
IM65X18

NEC
p.PB403
p.PD2114
p.PD6508

Intersl!
IM5603
2114
IM65XOB

Plessey

Intersl!

SC748

LM748

PMI

Intersl!

LF155
LF1.56
LF157
LF255
LF256
LF257
LM308
LF355
LF356
LF357
. ICL741

PM155
PM156
PM157
PM255
PM256
PM257
PM308
PM355
PM356
PM357
SSS741
Raytheon

Intersl!

LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2101
LH2301
LH2311
LM10l
LM105
LM107
LM10B
LM124
LM201
LM205
LM207
LM20B
LM211
LM224
LM2902
LM301
LM305
LM307
LM30B
LM311
LM324
RC555
RC556
RC723
RC733
RC741·
RC748
RM723

LF155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2101
LH2301
LH2311
AD101
LM105
LM107
LM10B
LM124
AD201
LM205
LM207
LM20B
LM211
LM224
LM2902
AD301
LM305
LM307
LM30B
LM311
LM324
NE555
NES56
LM723
icYlll
LM74B
LM723

.A-12

RM741
. RM74B
RV3302

ICL741
LM74B
MC3302

RCA

Intersl!

CA10l
CAl 07
CAlll
CA124
CA201
CA207
CA20B
CA211
CA224
CA301
CA307
CA30B
CA311
CA324
CA555
CA723
CA741
CA74B
CDP1854

AD10l
LM107
LMlll
LM124
AD201
LM207
LM20B
LM211
LM224
AD301
LM307
LM30B
LM311
LM324
NE555
LM723
ICL741
LM748
IM6402

Signetics

Intersl!.

p.A723
p.A733
1'740
p.A741
~748
F155
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2101
LH2108
LH2301
LH2308
LH2311
LM101
LM107
LM111
LM124
LM201
LM207
LM224
LM2902
LM301
LM307
LM308
LM324
MC3302
NE555
NE556
B049
B2S123
82S126
82S129
82S130
82S131
82S23

LM723
p.A733
LM740

Silicon General

p.A777
SG10l
SG105
SG107
SG10B
SG110
SGlll
SG124
SG201
SG205
SG207
SG208
SG210
SG211
SG224
SG301
SG305
SG307
SG308
SG311
SG324
SG3302
SG4250
SG555

A741
tLF155
M748
LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LH2101
LH21 08
LH2301
LH2308
LH2311
AD10l
LM107
LMlll
LM124
AD201
LM207
LM224
LM2902
AD301
LM307
LM30B
LM324
MC3302
NE555
NE556
IM80C49
IM5610
IM5603
IM5623
IM5604
IM5624
IM5600
Intersl!

p.A777
AD10l
LM105
LM107
LM10B
LMll0
LMlll
LM124
AD201
LM205
LM207
. LM20B
LM210
LM211
LM224
AD301
- LM305
LM307
LM30B
LM311
LM324
MC3302
LM4250
NE555

Ie Alternate Source Index (continued)
DG182BA

continued
SG556
SG723 .
SG733
SG741
SG748

NE556
LM723
p.A733
ICL741
LM748

SlIIconlx

Intersll

DGM111AL
DGMlllAP
DGM111BP
DG123AL
DG123AP
DG123BP
DG125AL
DG125AP
DG125BP
DG126AL
DG126AP
DG126BP
DG129AL
DG129AP
DG129BP
DGl33AL
DG133AP
DG133BP
DGl34AL
DGl34AP
DGl34BP
DG139AL
DG139AP
DG139BP
DGl40AL
DG140AP
DG140BP
DG141AL
DG141AP
DG141BP
DG142AL
DG142AP
DG142BP
DG143AL
DG143AP
DGl43BP
DGl44AL
DGl44AP
DGl44BP
DG145AL
DG145AP
DG145BP
DG146AL
DG146AP
DG146BP'
DG151AL
DG151AP
DG151BP
DG152AL
DG152AP
DG152BP
DGl53AL
DGl53AP
DGl53BP
DGl54AL
DGl54AP
DGl54BP
DG161AL
DG161AP
DG161BP
DG162AL
DG162AP
DG162BP
DGl63AL
DG163AP
DG163BP
DGl64AL
DGl64AP
DGl64BP
DG180M
DG180AL
DG180AP
DG180BA
DG180BP
.DG181M
DG181AL
DG181AP
DG181BA
DG181BP
DG182M

DGlllAL
DG111AK
DGlllBK
DG123AL
DG123AK
DG123BK
DG125AL
DG125AK
DG125BK
DG126AL
DG126AK
DG126BK
DG129AL
DG129AK
DG129BK
DG133AL
DG133AK
DG133BK
DGl34AL
DGl34AK
DGl34BK
DG139AL
DG139AK
DG139BK
DG140AL
DG140AK
DG140BK
DG141AL
DG141AK
DG141BK
DG142AL
DG142AK
DG142BK
DGl43AL
DG143AK
DG143BK
DGl44AL
DGl44AK
DGl44BK
DG145AL
DG145AK
DG145BK
DGl46AL
DG146AK
DG146BK
DG151AL
DG151AK
DG151BK
DG152AL
DG152AK
DG152BK
DGl53AL
DG153AK
DG153BK
DGl54AL
DG154AK
DGl54BK
DG161AL
DG161AK
DG161BK
DG162AL
DG162AK
DG162BK
DG163AL
DG163AK
DG163BK
DGl64AL
DGl64AK
DGl64BK
DG180M
DG780AL
DG180AK
DG180BA
DG180BK
DG181M
DG181AL
DG181AK
DG181BA
DG181BK
DG182M
DGM182M
DG182AL
DGM182AL
DG182AK
DGM182AK

D'G182AL
DG182AP

I

DG182BP.
DGl83AL
DG183AP
DG183BP
DGl84AL
DGl84AP
DGl84BP
DG185AL
DG185AP
DG185BP
DG186M
DG186AL
DG186AP
DG186BA
DG186BP
DG187M
DG187AL
DG187AP.
DG187BA
DG187BP
DG188M
DGl88AL
DGl88AP
DGl88BA
DGl88BP
DG189AL
DG189AP
DG189BP
DG190AL
DGl90AP
DGl90BP
DG191AL
DG191AP
DG191BP
DG200M
DG200AL
DG200AP
DG200BA
DG200BP
DG200CJ
DG201AP
DG201BP
DG201CJ
DG506AR
DG506BR
DG506CJ
DG507AR
DG507BR
DG507CJ
DG508AP
. DG508BP
DG508CJ
DG509AP
DG509BP
DG509CJ
D123AL
D123AP
Dl23BP
D125AL
D125AP
D125BP
Dl29AL
Dl29AP
D129BP
G115AP
G115BP
Gl16AL
Gl16AP
Gl16BP
Gl17AL
Gl18AL
Gl18AP
Gl19AL

DG182BA
DGM182BA
DG182BK
DGM182BK
DG183AL
DGl83AK
DG183BK
DGl84AL
DG184AK
DG184BK
DG185AL
DGM185AL
DG185AK
DGM185AK
DG185BK
DGMl85BK
DG186M
DG186AL
DG186AK
DG186BA
DG186BK
DG187M
DG187AL
DG187AK
DG187BA
DG187BK .
DG188M
DGM188M
8G188AL
Gl88AK
DG188BA
DGMl88BA
DG188BK
DG189AL
DG189AK
DG189BK
DGl90AL
DGl90AK
DGl90BK
DG191AL
DGM191AL
DG191AK
DGM191AK
DG191BKDGM191BK
IH200M
DG200M
IH200AL
DG200AL
IH200AK
DG200AK
IH200BA
DG200BA
IH200BK
DG200BK
DG200CJ
IH201MJE
DG201AK
IH201CJE
DG201BK
DG201CJ
IH6116MJI
IH6116CJI
IH6116CPI
IH6216MJI
IH6216CJI
. IH6216CPI
IH6108MJE
IH6108CJE
IH6108CPE
IH6208MJE
IH6208CJE
IH6208CPE
D123AL
D123AK
D123BK
D123BJ
D125AL
D125AK
D125BK
D125BJ
D129AL
D129AK
D129BK
Gl15AK
G115BJ
Gl15BK
Gl16AL
Gl16AK
G116BK
Gl16BJ
Gl17AL
G118AL
Gl18AK
Gl19AL

A-13

G123AL
G123AP
LDll0
LDlll
LD114
SI452
SI455
SI552
SI555

G123AL
G123AK
LDll0
LDlll
LDl14
MM452
MM455
MM552
MM555

Synertek

Intersll

SY21'14

2114

TI

In1erall

p.A723
p.A733
1'741
p.A748

LM723
p.A733

~m

LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
LM10l
LM105
LM107
LMlll
LM124
LM201
LM224
LM2902
LM301
LM305
LM307
LM311
LM324
NE555
NE556
SN54S188
SN54S288
SN54S387
SN74S188
SN74S288
SN74S387
TL182CL
TL182CN
TL1821L
TL1821N
TL182ML
TL185CJ
TL185CN
TL1851J
TL1851N
TL185MJ
TL188CL
TLl88CN
TLl88IL
TL188IN
TLl88ML
TL191CJ
TL191CN
TL1911J
TL1911N
TL191MJ
TMS4027
TMS4044
TMS4045

r

A741
M748

~777
F155

LF156
LF157
LF255
LF256
LF257
LF355
LF356
LF357
AD10l
LM105
LM107
LMlll
LM124
AD201
LM224
LM2902
AD301
LM305
LM307
LM311
LM324
NE555
NE556
IM5600
IM5610
IM5603
DGM182BA
IM5610
IM5603
DGM182BA
DGM182CJ
DGM182BA
DGM182CJ
DGM182M
IH5045CJE
IH5045CPE
IH5045CJE
IH5045CPE
IH5045MJE
IH5042CTW
IH5042CPE
IH5042CTW
.IH5042CPE
IH5042MTW
IH5043CJE
IH5043CPE
IH5043CJE
IH5043CPE
IH5043MJE
IM7027
MK4027
IM7141
2114 -

m

INDUSTRY
STANDARD

NEAREST
INnRSlL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INnRSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INnRSIL
EQUIVALENT

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

2N5270
2N5268
IT132
IT132
ITl32

2N3814
2N3815
2N3816
2N3816A
2N3817

IT132
IT132
IT130
IT\30A
IT130

IT132
IT137
ITl38
IT139
ITl37

2N3817A
2N3819
2N3820
2N3821
2N3821JAN

ITl30A
2N5484
2N2608
2N3821
2N3821JAN

2N3821JANTX
2N3821JTXV
2N3822
2N3823

2N3367

ITl38
IT139
2N4340
2N4338
2N4338

2N3823JAN

2N3821JANTX
2N3821JTXV
2N3822
2N3823
2N3823JAN

2N3368
2N3369
2N3370
2N3376
2N3378

2N4341
2N4339
2N4338
2N2608
2N2608

2N3823JANTX
2N3823JANTXV
2N3824
2N3907
2N3908

2N3823JANIX
2N3823JANTXV
2N3824
ITl20
ITl20

IT139
IT139·
2N2607
2N2607
2N2607

2N3380
2N3382
2N3384
2N3386
2N3409

2N2609
2N3994
2N3993
2N5114
IT122

2N3909
2N3909A
2N3921
2N3922
2N3949

2N2609
2N2609
2N3921
2N3922
IT132

2N2844
2N2903 \
2N2903A
2N2910
2N2913

2N2607
IT122
ITl20
IT122
IT122

2N3410
2N3411
2N3423
2N3424
2N3425

IT122
IT122
IT122
IT122
IT122

2N3950
2N3954
2N3954A
2N3955

IT132
2N3954
2N3954A
2N3955
2N3955A

2N4391
2N3823
2N4338

2N2914
2N2915
2N2915A

2N3436
2N3437
2N3438

2N4341
2N4340
2N4338

2N3452

2N4220

2N2916A

2N3453

2N4338

2N3956
2N3957
2N3966
2N3967
2N3967A

2N3956
2N3957
2N4416

2N4340
2N4341

ITl20
IT120
ITl20
IT120
ITl20

2000M
2001M
2005
200U
2015 .

2N3823
2N3823
2N4392
2N3824
2N4391

2N2917
2N2918
2N2919
2N2919A
2N2920

ITl22
ITl22
ITl20
ITl20
2N2920

2N3454
2N3455
2N3456
2N3457
2N3458

2N4338
2N4340
2N4338
2N4338
2N4341

2N3968
2N3968A
2N3969
2N3969A
2N3970

2N3685
2N3685
2N3686
2N3686
2N3970

2025
2035
2045
2078A
2079A

2N4392
2N3821
2N3821
2N3955
2N3955

2N2920A
2N2936
2N2937
2N2912
2N2973

2N2920
ITl20
ITl20 .
IT122
ITl22

2N3459
2N3460
2N3513
2N3514
2N3515

2N4339
2N4338
IT122
IT122
IT122

2N3971
2N3972
2N3993
2N3993A
2N3994

2N3971
2N3972
2N3993
2N3993
2N3994

2080A
2081A
2093M
2094M
2095M

2N3955A
2N3955A
2N3687
2N3686
2N3686

2N2974
2N2975
2N2976
2N2977
2N2978

ITl20
IT120
ITl20
ITl20
IT120

2N3516
2N3517
2N3521
2N3522
2N3574

ITl22
IT122
IT122
IT122
2N2607

2N3994A
2N4009
2N4010
2N4011
2N4015

2N3994
IT132
IT132
IT132
1T139

2098A
2099A
210U
2130U
2132U

2N3954
2N3955A
2N4416
2N5452
2N3955

2N2979
2N2980
2N2981
2N2982
2N3043

ITl20
IT121
1T122
IT122
IT121

2N3575
2N3578
2N3587
2N3608
2N3680

2N2607
2N2608
1Tl22
3N172
1T120

2N4016
2N4017
2N4018
2N4019
2N4020

1T137
IT139
ITl39
IT139
IT139

2134U
2136U
2138U
2139U
2147U

2N395'6
2N3957
2N3958
2N3958
2N3958

2N3044
2N3045
2N3046
2N3047
2N3048

ITl22
IT122
ITl21
ITl22
IT122

2N3684
2N3684A
2N3685
2N3685A
2N3686

2N3684
2N3684
2N3685
2N3685
2N3686

2N4021
2N4022
2N4023
2N4024
2N4025

IT139
1T139
IT137
1T137
IT137

2148U
2149U
2315
2325
2335

2N3958
2N3958
2N3954
2N3955
2N3956

2N3049
2N3050
2N3051
2N3052
2N3059

IT139
ITl39
IT139 .
IT129
IT139

2N3686A
2N3687
2N3687A
2N3726
2N3721

2N3686
2N3687
2N3687
ITl31
IT130

2N4026
2N4038
2N4039 .
2N4065
2N4066

3N163
2N4351
2N4351
3N163
3N166

2345
2355
241U
250U
251U

2N3957·
2N3958
2N4869
2N4091
2N4392

2N3066
2N3067
2N3068
2N3069
2N3070

2N4340
2N4338
2N4338
2N4341
2N4339

2N3728
2N3129
2N3800
2N3801
2N3802

IT122
IT121
IT132
IT132
IT132

2N4061
2N4082
2N4083
2N4084
2N4085

3N166
2N3954
2N3955
2N3954
2N3955

2N2060
2N2060A
2N20608
2N2223
2N2223A

ITl20
IT121
IT121
IT122
1Tl21

2N3071
2N3084
2N3085
2N3086
2N3087

2N4338
2N4339
2N4339
2N4339
2N4339

2N3803
2N3804
2N3804A
2N3805
2N3805A

IT132
IT130
1T130A
IT130
IT130A

2N4091
2N4091A
2N4091JAN
2N4091JANTX
2N4091JANtXV

2N4091
2N4091
2N4091JAN
2N4091JANTX
2N4091JANTXV

2N2386
2N2386A
2N2453
2N2453A
2N2480

2N2608
2N2608
IT122
IT121
IT122

2N3088
2N3088A
2N3089
2N3089A
2N3113

2N4339
2N4339
2N4339
2N4339
2N2607

2N3806
2N3807
2N3808
2N3809
2N3810

1T122
IT122
1T122
IT122
2N3810

2N4092
2N4092A
2N4092JAN
2N4092JANTX
2N4092JANTXV

2N4092
2N4092
2N4092JAN
2N4092JANTX
2N4092JANTXV

2N2480'
2N2491
2N2498
2N2499
2N2500

IT121
2N2608
2N2608
2N2609
2N2608

2N3277
2N3278
2N3328
2N3329
2N3330

2N2606
2N2607
2N5265
2N5267
2N5268

2N3810A
2N3811
2N3811A
2N3812
2N3813

2N3810A
2N3811
2N3811A
IT132
IT132

2N409-3
2N4093A
2N4093JAN
2N4093JANTX
2N4093JANTXV

2N4093
2N4093
2N4093JAN
2N4093JANTX
2N4093JANTXV

1005
100U
102M
1025
103M

2N5458
2N3684
2N5686
2N5457
2N5457

2N2606
2N2607
2N2608
2N2609
2N2609JAN

2N2607
2N2607
2N2608
2N2609
2N2609JAN

1035
104M
105M
105U
106M

2N5459
2N5458
2N5459
2N4340
2N5485

2N2639
2N2640
2N2641
2N2642
2N2643

ITl20
IT122
IT122
ITl20
IT122

. 2N3336
2N3347
2N3348
2N3349
2N3350

107M
1I0U
120U
125U
1277A·

2N5485
2N3685
2N3686
2N4339
2N3822

2N2644
2N2652
2N2652A
2N2720
2N2721

IT122
IT120
ITl20
ITl20
IT122

2N3351
2N3352
2N3365
2N3366

1278'
1279A
1280A
1281A
1282A

2N3821
2N3821
2N4224
2N3822
2N4341

2N2722
2N2802
2N2803
2N2804
2N2805

IT120
ITl39
IT139
IT139
IT139

1283A
1284A
1285A
1286A
130U

2N4340
2N4222
2N3821
2N4220
2N3687

2N2806
2N2807
2N2841
2N2842
2N2843

1325A
135U
14T
155U
1714A

2N4222
2N4339
2N4224
2N4416
2N4340·

1825
1835
1975
1985
1995

I
I
I

I

2N2916

2N3331
2N3332
2N3333
2N3334
2N3335

A·14

2N3;95SA

2N4221

2N4221

..

CONSULT FACTORY

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

IND\ISTRY
STANDARD

NEAAESI'
INTERSIL
EQUIVALENT
IT12l

2N4100
2N4117
2N4117A
2N4118
2N4118A

2N4100
2N4117
2N4117A
2N4118
2N4118A

2N4979
2N5018
2N5019
2N5020
2N5021

2N4859
2N5018
2N5019
2N2843
2N2607

2N5471
2N5472
2N5473
2N5474
2N5475

2N5265
2N5265
2N5265
2N5265
2N5265

2N6448
2N6451
2N6452
2N6453
2N6454

U310
U310
U310
U310

2N4119
2N4119A
2N4120
2N4139

2N4119
2N4119A
3N163
2N3822

2N4220

2N4220

2N5033
2N5045
2N5046
2N5047
2N5078

2N5460
2N5453
2N5454
2N5454
2N5397

2N5476
2N5484
2N5485
2N5486
2N5515

2N5266
2N5484
2N5485
2N5486
2N5515

2N6483
2N6484
2N6485
2N6502
2N6503

2N6483
2N6484
2N6485
IT122
IT122

2N4220A
2N4221
2N4221A
2N4222
2N4222A

2N4220
2N4221
2N4221
2N4222
2N4222

2N5090
2N5103
2N5104
2N5105
2N5114

ITl22
2N4416
2N4416
2N4416
2N5114

2N5516
2N5517
2N5518
2N5519
2N5520

2N5516
2N5517
2N5518
2N5519
2N5520

2N6550
2N6568
2N6656
2N6657
2N6658

2N4868A
2N5432
IVN6657
2N6657
2N6658

2N4223
2N4224
2N4267
2N4268
2N4302

2N4223
2N4224
3N163
3N16l
2N4302

2N5114JAN
2NS1l4JANTX
2N5114JANTXV
2N5115
2N5115JAN

2N5114JAN
2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN

2N5521
2N5522
2N5523
2N5524
2N5645

2N5521
2N5522
2N5523
2N5524
2N3954

2N6659
2N6660
2N666l
25C294
25Jll

IVN6658
2N6660
2N666l
IT122
2N2607

2N4303
2N4304
2N4338
2N4339
2N4340

2N5459
2N5458
2N4338
2N4339
2N4340

2N5115JANTX
2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX

2N5115JANTX
2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX

2N5546
2N5547
2N5549
2N5555
2N5556

2N3955A
2N3955
2N4093
J310
2N3685

25J12
25J13
25J15
25J16
25J47

2N2607
2N5270
2N2607
2N2607

2N4341
2N4342
2N4343
2N4351
2N4352

2N4341
2N5461
2N5462

2N5116JANTXV
2N5117
2N5118

2N5557
2N5558
2N5561
2N5562
2N5563

2N3684
2N3684
U401
U402
U404

25J48
25J49
25J50
2SJ78
25J79

2N4353
2N4360
2N4381
2N4382
2N4391
2N4392
2N4393

2N4392
2N4393

2N4416
2N4416A
2N4417

2N4416

..

..
.......

2N4351

2N5119

3N163

2N5120

2N5116JANTXV
2N5117
2N5118
2N5119
IT131

3N172
2N5460
2N2609
2N5115
2N4391

2N5121
2N5122
2N5123
2N5124
2N5125

ITl32
IT132
ITl31
ITl32
IT132

2N5564
2N5565
2N5566
2N5592
2N5593

2N5564
2N5565
2N5566
2N3822
2N3822

25J80
25Kll
25K12
25K13
25K132

2N4416A
2N4416

2N5158
2N5159
2N6163
2N5196
2N5197

2N5434
2N5433
2N3822
2N5196
2N5197

2N5594
2N5638
2N5639
2N5640
2N5647

2N3822
2N5638
2N5639
2N5640
2N4U7A

25K133
25K134
25K135
25K15
25K17

2N4446
2N4447
2N4448
2N4856

2N5432
2N5434
2N5432
2N5434
2N4856

2N5198
2N5199
2N5245
2N5246
2N5247

2N5198
2N5199
ITE4416
2N5484
2N5486

2N5648
2N5649
2N5653
2N5654
2N5668

2N4117A
2N4117A
2N5638
2N5639
2N5484

25K178
2SK179
25K18
25K180
25K19

2N3821

2N4856A
2N48S6JAN
2N4856JANTX
2N4856JANTXV
2N4857

2N4856
2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857

2N5248
2N5254
2N5255
2N5256
2N5257

2N5486
IT132
IT132
IT130
2N5457

2N5669
2N5670

25K23
25K30

2N5459
2N5458

2N5794
2N5795

2N5485
2N5486
IT129
ITl29
IT139

2N4857A
2N4857JAN
2N4857 JANTX
2N4857JANTXV
2N4858

2N4857
2N4857JAN
2N485 7 JANTX
2N4857JANTXV
2N4858

2N5258
2N5259
2N5265
2N5266
2N5267

2N5458
2N5459
2N2607
2N2607
2N2608

2N5796
2N5797
2N5798
2N5799
2N5800

IT139
2N2608
2N2608
2N2608
2N2608

2SK37
2SK41
25K42
,2SK43
2SK44

2N5484
2N5459
2N3822
ITE4092
ITE4416

2N4858A
2N4858JAN
2N4858JANTX
2N4858JANTXV
2N4859

2N4858
2N4858JAN
2N4858JANTX
2N4858JANTXV
2N4B59

2N5268
2N5269
2N5270
2N5277
2N5278

2N2608
2N2609
2N2609
2N4341
2N4341

2N5801
2N5802
2N5803
2N5B43
2N5844

2N4393
2N4393
2N4392
ITl30
IT130

2SK46
2SK48
25K49
25K50
2SK54

2N5459
2N3821
2N5484
ITE4416
2N3822

2N4859A
2N4859JAN
2N4859JANTX
2N4860
2N4B60A

2N4859
2N4B56JAN
2N4856JANTX
2N4860
2N4860

2N5358
2N5359
2N5360
2N5361
2N5362

2N4220
2N4220
2N4221
2N4221
2N4222

2N5902
2N5903
2N5904
2N5905
2N5906

2N5902
2N5903
2N5904
2N5905
2N5906

25K55
25K56
25K61
25K65
25K66

2N3822
2N5459
2N5397
J201
2N3821

2N4860JAN
2N4860JANTX
2N4861
2N4861A
2N4B61JAN

2N4857JAN
'2N485 7 JANTX
2N4861
2N4B61
2N4B5BJAN

2N5363
2N5364
2"5391
2N5392
2N5393

2N4222
2N4222
2N4867A
2N4B6BA
2N4869A

2N5907
2N5908
2N5909
2N5911
2N5912

2N5907.
2N5908
2N5909
2N5911
2N5912

25K68
2SK72
3G5
3N145
3N146

2N3822
2N5196
2N3821
3N163
3"163

2N4B61JANTX
2N4867
2N4867A
2N4868
2N4868A

2N4B5BJANTX
2N4867
2N4867A
2N4868
2N4868A

2N5394
2N5395
2N5396
2N5397
2N5398

2N4B69A
2N4869A
2N4869A
2N5397
2N5398

2N5949
2N5950
2N5951
2N5952
2N5953

2N5486
2N5486
2N5486
2N5484
2N5484

3N147
3N148
3N149
3N150
3N151

3N189
3N189
3N161
3N163
3N190

2N4869
2N4869A
2N4878
2N4879
2N4880

2N4869
2N4869A
2N4878
2N4879
2N4880

2N5432
2N5433
2N5434
2N5452
2N5453

2N5432
2N5433
2N5434
2N5452
2N5453

2N6085
2N6086
2N6087
2.N6088
2N6089

IT122
IT122
IT121
ITl21
IT122

3N155
3N155A
3N156
3N156A
3N157

3N163
3N163
3N163
3"163
3N163

2N4937
2N4938
2N4939
2N4940
2N4941

ITl31
ITI32
IT132
IT132
IT131

2N5454
2N5457
2N5458
2N5459
2N5460

2N5454
2N5457
2N5458
2N5459
2N5460

2N6090
2N6091
2N6092
2N6441
2N6442

IT121
IT121
IT121
IT122
IT122

3N157A
3N158
3N158A
3N160
3N161

3N163
3N163
3N163
3N16l
3N161

2N4942
2N4955
2N4956
2N4977
2N4978

IT132
IT122
IT122
2N5433
2N5433

2N5461
2N5462
2N5463
2N5464
2N5465

2N5461
2N5462
2N5463
2N5464
2N5465

2N6443
2N6444
2N6445
2N6446
2N6447

ITl22
IT122
IT121
IT121
IT121

3N163
3N164
3N165
3N166
3N167

3N163
3N164
3N165
3N166
3N16l

2N4445

2N5793

A·15

..
..

2N5457
2N5457
2N5457

..

....
2N4868
2N5484

....
..

ITE4416

2SK32

2N3822

25K33
25K34

2N5397
2N3822

..

CONSULT FACTORY

"
~',

INDUS1lIY
STANDARD

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAl!EST
INTUSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

3NI68
3NI69
3N170
3NI71
3N172

3NI61
3NI70
3NI70
3NI71
3NI72

A0838,
A0839
A0840
AOB41
A0842

2N3956
2N3957
2N5520
2N5521
2N5523

BFX36
8FX70
BFX71
BFX72
BFX78

IT131
IT122
IT122
IT122
2N5397

CM646
CM650
CM651
CM652

2N4092
2N4091
2N5432
2N5433
2N5432

3N173
3N174
3N175
3N176
3NI77

3NI73
3NI63
3NI70
3NI70
3NI71

BC264 ,
BC264A
BC264B
BC264C
BC2640

2N545B
2N5457
2N545B
2N545B
2N441'6

BFXB2
BFXB3
BFX99
BFY20
BFYBI

2N5019
2N5019
ITI20A
ITI22
IT122

CM653
CM697
CMBOO
CMB56
CMB60

2N5433
2N5433
2N5433
' 2N5433
2N4B6BA

3N17B
3N179
3NIBO
3N181,
3NI82

3NI72
3NI72
3NI72
3NI6I
3NI6I

BCYB7
BCYBB
BCYB9
B0512
B0522

IT121
IT122
IT122
IVN500lBNE

BFYB2
BFYB3
BFYB4
BFY85
BFY86

ITI22
ITI22
IT122
IT122
IT122

CMX740
CP640
CP643
CP650
CP651

2N5432
2N4091
-2N5434
2N5432
2N5433

3NI83
3NI88
3NIB9
3NI90
3NI91

3NI61
3NI8B
3NI89
3NI90
3NI91

BF244
BF244A
BF244B
BF244C
BF245

2N54B6
2N5484
2N5485
2N54B6 ' ,
2N54B6

BFY91
BFY92
BN209
BSV22
BSV78

IT122
ITI22
IT122
2N4416
2N4B56A

CP652
CP653
01101
01102
01103

2N5433
2N5433
2N3821
2N3821
2N433B

3N207,
3N208
3SK22
3SK23
3SK28

3N!90
3NIBB
2N5486
2N5397
2N5397

BF245A
BF245B
BF245C
BF246
BF246A

2N4416
2N4416
2N4416
2N5485
2N5639

8SV79
BSV80
'BSX82
C21
C2306

2N4857A

2N4B5BA
2N3B22
2N3B21
2N5196

01177
01178
01179
OIlBO
OIlBI

2N3821
2N3B21
2N4338
2N3B22
2N433B

42T
4360TP
5033TP
588U
58T

2N4392
2N5462 '
2N5460
2N4416
2N5457

BF246B
BF246C
'BF247
BF247A
BF247B

. 2N563B
2N563B
2N4091
2N4091
2N4091

C38'
C413N
C610
C6II
C612

2N433B
2N5434
2N4392
2N4221
2N4221

01182
0llB3
01.184,
0llB5
01201

2N4338
2N4341
2N4340
2N4339
2N4224

59T
703U
704U
705U
707U

2N4416
2N4220
2N4220
2N4224
2N4860

BF247C
BF256
BF256A
BF256B
BF256C

2N4091
2N5484
2N5484
2N4416
2N4416

C613
C614
C615
C620
C621

2N4221
2N4220
2N4221
2N4220
2N4220

01202
.01203
01301
01302
01303

2N3B21
2N4220
2N4222
2N4220
2N4220

714U
734EU
734U
751U
752U

2N3B22
2N4416
2N5516
2N4340
2N4340,

BF320
BF346
BF347
BF348
BF800

2N5461
ITE4392
J201
J310
2N4867

C622
C623
C624
C625
C650

2N4220
2N4220
2N4220
2N4220
2N4220

01420
01421
01422
02T2218
02T2218A

2N4B6B
2N3822
2N4869
ITI29
IT129

753U
754U
755U
756U
AI90

2N4341
2N4340
2N4341
2N4340
ITE4416

BF801
BF802
BF804
BF805
BF806

2N4B67
2N43JB
2N4338
2N4869
2N4869 '

C651
C652
C653
C6690
C6691

2N4220
2N4220
2N4220
2N4341
2N4341

02T2219
02T2219A
02T2904
02T2904A
02T2905

ITl29
ITI29
ITl39
ITl39
ITl39

AI!l1
AI92
AI93
AI94
A195

ITE4416
2N4416
2N5484
2N5484
2N5484

BF808
BF810
BF811
BF815'
8F816

2N4868
2N4858
2N4858
2N4858

C6692
C673
C674
C680

02T2905A
02T918
OAI02
OA402

ITl39
ITl29
2N5196
2N5196

2N4858

C680A

2N4339
2N4341
2N4341
2N4338
2N4338

DN3066A

2N3821

AI96
AI97
AI98
AI99
A5T3821

ITE4416
ITE4391
ITE4392
ITE4393
2N5484

BF817
BF818
BFQIO
BFQII
BFQI2'

2N4858
2N4858
U401
U401
U402

C681
C681A
C682
C682A
C683

2N4338
2N4338
2N4339
2N4339
2N4339

ON3067A
ON3068A
ON3069A
ON3070A
ON3071A

2N4338
' 2N4338
2N3822
2N3821
2N4338

A5T3822
A5T3823
A5T3824·
A5T5460
A5T5461

2N5484
2N4416
2N4341
2N5460
2N5461

' BFQI3
BFQI4'
BFQI5
BFQI6
8FS21'

U403
U404
U405
U406
2N5199

C683A
C684
C684A
C685

2N4339
2N4220
2N4220
2N4220

ON3365A
ON3365B
, ON3366A
ON3366B

2N4220

C685A

2N4220

ON3367A

2N3687

A5T5462
A03954
A03954A
A03955
A03956

2N5462
2N3954
2N3954A
2N3955
2N3956

BFS21A
BFS67
BFS67P
BFS68
BFS68P

2N5199
2N3821
2N5459
2N3823
2N4416

C80
C81
C84
C85
C91

2N4338
2N433B
2N4338
2N4338
2N4858

\ ON33678

ON3368A
ON3368B
ON3369A
ON3369B

2N4091
2N4341
2N4221
2N4339
2N4220

A03958
A05905
A05906
A05907
A0590B

2N3958
2N5905
2N5906

2N3821
2N3822
2N3823
2N3821
2N4856

C92
C93
C94
C94E
C95

2N4091
2N4393
2N468

ON3370A
ON3370B
ON3436A

2N433B
2N4338
2N4341

2N5457

ON34368

2N4222

2N5908

BFS70
BFS71
BFS72
BFS73
BFS74

2N5457

ON3437A

2N4340

A05909
ADBIO
AD811
AD812
A0813

2N5909
2N4B7B
2N4878
2N4878
2N4878

BFS75
BFS76
BFS77
BFS78
BFS79

2N4857
2N4858
2N4859
2N4860
2N4861

C95E
C96E
C97E
C98E
CC4445

2N5459
2N5484
2N3822
2N3822
2N5432

ON3437B
DN3438A
DN3438B
ON3458A
DN3458B

2N4220
2N4338
2N4339
2N4341
2N4222

IT124
ITl24
ITl20A
IT140
,ITl32

BFS80
BFTlO
BFTII
8FWIO
BFWII

2N4416A
2N5397
2N5019
2N3823
2N3822

CC4446
CC697
CF2386

DN3459A
ON3459B
ON3460A

2N4339
2N4220
2N4338
2N4220
2N4338

DNX2
ONX3
DNX4
ONX5
ONX6

AD814
AD815
A0816
A0818
AD820

!

NEAREST
INTUSIL
EQUIVALENT

.

2N5907

,

,

CM647

CFM13026

2N5434
2N4856
2N5458
2N3824
2N4858

AD821
AD822
AD830
AD831
A0832

IT 130A
ITl30A
2N5520
2N5521
2N5522 '

BFW12
BFW13
BFW39
BFW39A
BFW54

2N4416
2N4867
ITI29
IT12Q
2N3822

CM600
CM601
CM602
CM603
CM640

2N4092
2N4091
2N4091
2N4091
2N4093

AD833
A0833A
A0835
A0836
A0837

2N5523
2N5524

BFW55
BFW56
BFW61.
BFXII
BFX15

2N3822
2N4860
2N4224
IT132
IT122

CM641
CM642
CM643
CM644
CM645

2N4092

DNX9

2N4092
2N4092

OU4339
OU4340

2N3954

2N3955
2N3955

CF24

2N4093
2N4093

ON34608

DNX1

ONX7
ONX8

,

2N4091
2N3686
2N4091

,

2N4338
2N4338

mm

2N4338
2N4~16

2N4416
2N4339
2N5397
2N5398

-

··CONSULT FACTORY'

A-16

O~OI1.
INDUSTRY
STANDARD
EIOO
EIOI
EI02
EI03
EI05

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

2N5458

FE5459

2N5459

lliF132

FE5484

2N5484

FES485

IAFI33
IAFl50
IAFI51
IAFI52

J204

JI05

FF400

JlG6

FM!lOO

2N3954A

JI07
Jl05
Jl06

FMI100A

2N5906
2N5906
2N3954
2N5906

IAFI53
IAF300
IAF301
IAF305
IAF306

FMl104A

2N3955
2N5908
2N3957
2N5909

FMII05

2N3954A

IAF330
IAF331
IAF332
IAF333
IAF350

FMllOSA

IT500
2N3954A
IT500
2N3954
IT500

IAF351
IAF352
IAF353
IAF530
IAF531

2N3955

IAF532
IAF533
IAF730

FE54B6

EIII
ElllA
Ell2
Ell2A
EI13

Jill
Jill
Jll2
Jll2
J113

El13A

J113
J204

JI74
Jl75

FMII06
FMII06A
FMII07

EI75
EI76

JlQ7

FMtlOlA
FMll02
FMII02A

FMll03
FMll03A
FMll04

J176

FMI107A

FMIIOB
FMIIOBA

E203
E204

J177
J201
J202
J203
J204

FMII09
FMI109A
FM111D

E210

2N5397

FM1110A

2N5397
2N5397

FMIlll
FMIlllA
FMl1l2

2N5908
2N3957
2N5909
2N5196

EI77
E201
E202

E211
E212
E230
E231

INDUSTRY
STANDARD

2N5485
2NS486
2N54S7

-2NS4S7
2N5459

EI06
EI07
EI08
El09
EIIO

E114
E174

2N4867
2N4868

IT502
2N3957
IT503
2N3955

IAF731

IAF732
IAF733
ITIOO
ITlOI
ITI08

NEAREST
INTERSIL
EQUIVALENT

....
....
..
......
....
....
....
..
....

....
..
..
......
..
..

ITIOO
ITIOI
ITI08

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

ITC3806
ITC3807
ITC3808
ITC3809
ITC3810

IT132
ITI32
ITI32
ITI32
ITI30

ITC3811
ITC4017
ITC4018
ITC4019
ITC4Q20

IT130.
ITl39
IT139
ITl39
IT139

ITC4021
ITC4022
ITC4023
ITC4024
ITC4025

IT139
ITl39
ITI37
ITt37
ITI37

ITE2453
ITE2639
ITE2.640
ITE2641
ITE2642

ITl20
ITl20
ITI22
IT122
ITl20

ITE2643
ITE2644
ITE2720
ITE2721
ITE2722

IT122
IT122
ITI20
ITl22
IT120

ITE2903
ITE2913
ITE2914
ITE2915

IT122
ITI22
IT122
ITl20

ITI09

ITI09

ITE2916

IT120

IT1tO

ITI21

ITIIO
ITlll
ITI20
ITl20A
ITl21

ITE2917
. ITE2918
ITE2919
ITE2920
ITE2936

ITI22
ITI22
ITI20
ITl20
IT120

2N3955A
2N3955
2N3955A

ITI22
IT124
IT124A
IT124B
ITI25

ITI22
IT124
IT124A
ITI248
ITl25

ITE2937
ITE2972
ITE2973
ITE2974
ITE2975

ITl20
IT122
IT122
IT120
ITl20

FM1211
FM3954
FM3954A
FM3955
FM3955A

IT5911
2N3954
2N3954A
2N3955
2N3955A

IT126
IT127
ITl28
ITl29
ITI30

IT126
ITI27
ITI28
ITI29
IT130

ITE2976
ITE2977
ITE2978
ITE2979
ITE3066

IT120
IT120
IT120
IT120
2N3685

IT5911
IT5911
2N5454
2N3956
2N3957

FM3956
FM3957
FM3958
FP4339
FP4340

2N3956
2N3957
IT5911
2N4339
2N4340

ITI30A
ITI31
ITI32
IT136
ITI37

ITI30A
ITl31
IT!32
IT136
ITl37

ITE3067
ITE3068
ITE3347
ITE3348
ITE3349

2N3686
2N3687
IT137
IT13B
ITI39

E420
E421
E430
E431
ESM25

IT5911
IT5912
J3091X21
J310lX21
U401

FT0654A
FT06548
FT0654C
FTOG540
FT3820

2N5486
2N5486
2N4221·
2N4221
2N5460

ITI3B
ITI39
IT140
ITI700
IT1701

IT138
ITI39
IT140
ITI700
3N172

ITE3350
ITE3351
ITE36BO
ITE3BOO
ITE3802

IT137
ITl38
IT120
ITI32
IT132

ESM25A
ESM4091
ESM4092
ESM4093
E$M4302

U401
2N4091
2N4092
2N4093
2N5457

FT3820
FT3909
FT703
FT704
FVN2

2N5019
2N5019
3N161
3N163
VN67AK

IT1702
ITl 750
IT2700
IT2701
IT400

3NI63
ITI750
3N165
3NI65
2N4392

ITE3804
ITE3806
ITE3807
ITE3808
ITE3809

IT130
IT132
IT132
ITl32
ITl32

ESM4303
ESM4304
ESM4445
ESM4446
ESM4447

2N5459
2N5458
2N5432
2N5434
2N5432

FVP2
GET5457
·GET5458
GET5459
HA7807

2N5457
2N5458
2N5459
ITl32

IT404
IT500
IT500P
IT501
IT50lP

IT404
IT500
IT500
IT501
IT501

ITE3810
ITE3811
ITE3907
ITE3908
lTE4017

ITI30
IT130
ITl20
ITl20
ITI39

ESM4448
FE0654A
FE0654B
FE1DD
FE1DOA

2N5434
2N4386
2N5485
2N3821
2N3821

HA 7809
HOIG1030
HEPB01
HEPBD2
HEP803

ITl32
3N163
2N3B22 .
2N5484
2N5019

IT502.
IT502P
IT503
IT503P
IT504

IT502
IT502
IT503
IT503
IT504

ITE4018
ITE4019
ITE4020
lTE4021
ITE4022

IT139
IT139
IT139
ITI39
IT139

FEl02
FE102A
FE104
FE104A
FEI600

2N4119
2N4119
2N4118
2N4118
2N4092

HEPFOO21
HEPFI035
HEPF2Q04
HEPF2005
10100

2N5484
J176
2N5484
2N5459
IDIOO

IT5911
IT5911
IT5912
ITC2972
ITC2973

IT5911
IT5911
IT5912
ITI22
ITl22

ITE4023
ITE4024
ITE4025
ITE4091
ITE4092

IT137
IT137
IT137
ITE4D91
ITE4092

FE200
FE202
FE204
FE300
FE302

2N3821
2N3B21
2N3821
2N3B22
2N3821

10101
IMF3954
IMF3954A
IMF3955
IMF3955A

10101
2N3954
2N3954A
2N3955
2N3955A

ITC2974
ITC2975
ITC2976
ITC2977
ITC2978

ITl20
IT120
ITl20
IT!20
ITl20

ITE4093
ITE4117
ITE4118
ITE4119
ITE4338

ITE4093
2N411 7
2N411B
2N4119
2N4338

FE304
FE3819
FE4302
FE4303
FE4304

2N3821
2N5484
2N5457
2N5459
2N5458

IMF3956
IMF3957
IMF3958
IMF5911
1MF5912

2N3956
2N3957
2N3958
IMF5911
1MF5912

ITC2979
ITC3347
ITC3348
ITC3349
ITC3350

1T120
ITI37
ITl38
IT139
ITI37

ITE4339
ITE4340
ITE4341
ITE4391
1TE4392

2N4339'
2N4340
2N4341
1TE4391
ITE4392

FE5245
FE5246
FE5247
FE5457
FE5458

2N4416
2N5484
2N5486
2N5457
2N5458

IMF6485
IAF100
IAFI01
IAFI30
1RF131

IMF6485

ITC3351
ITC3352
ITC3800
ITC3802
ITC3804

ITI38
ITl39
ITI32
ITl32
ITI30

ITE4393
ITE4416
ITE4867
IrE4868
ITE4869

ITE4393
ITE4416
2N4867
2N4868
2N4869

FM1200

2N39S4

2N4869
J270
J271

FM1201
FM!202

E300
E304

2N5397

FM1204

2NS486

FMl205

2N3954
2N3954
2N3955A
2N3955
2N3954

E305

2NS484
J30B

FMI206

2N3954

FM1207

2N3954

J309
J310
J310

FMl20B
FM1209'
FM1210

E312
E400
E401
E402
E410

2N5397
2N3955
2N'3955
2N3957
2N3955

E411
E412
E413
E414
E415

E232
E270
E271

E308
E309
E310
E311

I

NEAREST
INTERSIL
EQUIVALENT

FMl203

..

....
....

ITIll
ITl20
IT120A

,

A·17

,

*.

CONSULT FACTORY

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
, STANDARD

NEAREST
INTERSIL
EQUIVALENT

IVN5000ANO
IVN5000ANE
IVN5000ANF
IVN50008NO
IVN5000BNE

IVN5000ANO
IVN5000ANE
IVN5000ANF
IVN5000BNO
IVN5000BNO

J203
J203-18
J204
J204-18
J210

J203
J203
J204
J204
2N5397

IVN5000BNF
IVN5000SNO
IVN5000SNE
IVN5000SNF
IVN500lANO

IVN5000BNF
IVN5000SNO
IVN5000SNE
IVN5000SNF
IVN500lANO

J211
J212
J230
J231
J232

IVN500lANE
IVN500lANF
IVN500lBNO
IVN500lBNE
IVN500lBNF

IVN500lANE
IVN500lANF
IVN500lBNO
IVN500lBNE
IVN500lBNF

IVN500lSNO
IVN500lSNE
IVN500lSNF,
IVN5200HNO
IVN5200HNE
IVN5200HNF

INDUSTRY
STANDARD
KE38'23

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

KE3971
KE3972
KE4091

2N3823
ITE4391
ITE4392
ITE4393
ITE4091

LS5359
LS5360
' L55361
LS5362
LS5363

2N5397
2N5397
2N4867
2N4868
2N4B69

KE4092
KE4093
KE4220
KE4221
KE4222

ITE4092
ITE4093
2N5457
2N5459
2N5459

LS5364
LS5391
LS5392
LS5393
LS5394

J203
2N4867A

J270
J270-18
J271
J271-18
J300

J270
J270
J271
J271
2N5397

KE4223
KE4391
KE4392
KE4393
KE4416

J204
ITE4391
ITE4392
ITE4393
ITE4416

LS5395
LS5396
LS5457
LS545B
LS5459

2N4869A

IVN500lSNO
IVN500lSNE
IVN500lSNF
IVN5200HNO
IVN5200HNE

J304
J305
J308
J309
J310

2N5486
2N5484
J308
J309
J310

KE4856
KE4857
KE4858
KE4859
KE4860

ITE4391
ITE4392
ITE4393
ITE439 I
ITE4392

LS5484
LS5485
LS5486
LS5556
LS5557

2N5484
2N5485
2N5486
2N3685
2N3684

IVN5200KNO
IVN5200KNE
IVN5200KNF
IVN5200TNO

IVN5200HNF
IVN5200KNO
IVN5200KNE
IVN5200KNF
IVN5200TNO

J315
J316
J317
J3970
J~971

' 2N5397
U309
U310
ITE4391
ITE4392

KE4861
KE510
KE5103
KE5104
KE5105

ITE4393
ITE4393'
J204
ITE4416
ITE4416

LS5558
LS5638
LS5639
LS5640
MI03

2N3684
2N5638
2N5639
2N5640
3NI61

IVN5200TNE
IVN5200TNF
IVN520lCNO
IVN520lCNE
IVN520lCNF

IVN5200TNE
IVN5200TNF
IVN520lCNO
IVN520lCNE
IVN520lCNF

J3972
J401
J402
J403
J404

ITE4393
IT501
IT502
IT503
IT503

KE511
KH5196
KH5197
KH5198
KH5199

ITE4392
2N5196
2N5197
2N5198
2N5199

MI04
MI06
MI07
MI08
M113

3NI61
3NI66
3NI89
3NI91
3NI61

IVN520lHNO
IVN520lHNE
IVN520lHNF
IVN520lKNO
IVN520lKNE

IVN520lHNO
IVN520lHNE
IVN520lHNF
IVN520lKNO
' IVN520lKNE

J405
J406
J4091
J4092
J4093

IT504
IT505
ITE4091
ITE4092
ITE4093

LOF603
LOF604
LOF605
LM114
LM114A

2N4221
2N4221
2N4221
ITl20
ITl20A

MI14
M116
M117
M119
MI63

3NI61
M116
2N4351
3NI61
3NI63

IVN520lKNF
IVN520lTND
IVN520lTNE
, IVN520lTNF
IVN6657

IVN520lKNF
IVN520lTND
IVN520lTNE
IVN520lTNF
IVN6657

J410
J411
J412
J420
J421

IT502
IT503
IT503
IT5911
IT5912

LM114AH
' LM114H
LM115
LM115A
LM115AH

ITI20A
ITl20
ITl20
ITl20A
ITl20A

MI64
M511
M511A
M517
MA7807

3NI64
3NI72
3NI72
3NI63
IT) 32

IVN6658
IVN6660
IVN6661
JIOO
JIOI

IVN6658
IVN6660
IVN6661
2N5458
2N4338

J4220
J4221
J4222
J4223
J4224

J204
J202
J203
J202
J202

LM115H
LMI94
LM394
LS3069
LS3070

ITl20
ITl20A
ITI20A
2N5458
2N5458

MA7809
MAT-OIAH
MAT-OIFH
,MAT-OIGH
MAT-OIH

ITl32
ITI40
ITl40
ITl40
ITl40

JI02
JI03
JI05
JI05-18
Jl06

2N5457
2N5459
JI05
JI05
JI06

J430
J4302
J4303
J4304
J431

J309(X2)
2N4302
2N5459
2N5458
J310(X2)

LS3071
LS3458
LS3459
LS3460
LS3684

2N5458
J204
J204
J204

ITI22

2N3684

M01120
M01120F
M01121
MD1122
M01123

, Jl06-18
Jl07
Jl07-18
JI08
JI08-18

JI06
JI07
JI07
JI05
JI05

J433
J4338
J4339
J4391
J4392

2N5457
2N5457
2N5457
ITE4391
ITE4392

LS3685
LS3686
LS3687
LS3819
LS3821

2N3685
2N3686
2N3687
2N5484
2N5457

M01129
MD1129F
M01130
M01130F
M02218

ITl29

JI09
JI09-18
J110
J110-18
J111

JI06
JI06
JI07
JI07
J111

J4393
J4416
J4856
J4857

LS3822
LS3823
LS3921
LS3922
LS3966

2N5458
2N5458
2N3921
2N3922
ITE4416

M02218A
M02218AF
M02218F
M02219
M02219A

ITI29

J4858

ITE4393
ITE4416
nE4856
ITE4857
ITE4858

Jl11-18
Jl11A
Jl11A-18
J112
J112-18

J111
Jll1
J111
J112
J112

J4859
J4860
J4861
J4867
J4867A

nE4859
ITE4860
nE4861
2N4867
2N4867A

LS3967
LS3968
LS3969
LS4220'
LS4221

ITE4416
ITE4416
ITE4416
J204
J202

M02219AF
M02219F
M02369
M02369A
M02369AF

J112A
J112A-18
J113
J113-18.
JIl3A

J112
J112
J113
JIl3
JIl3

J4867RR
J4868
J4868A
J4868RR
J4869

2N4867
2N4868
2N4868A
2N4868
2N4869

LS4222
LS4223
LS4224
LS4338
LS4339

J203
J202
J202
2N5457
2N5457

M023698
M023698F
M02369F
M02904
MD2904A

J113A-18
J114
J1401
J1402
J1403

J113
2N5555
IT501
IT502
IT503

J4869A
J4869RR
J5103
J5104
J5105

2N4869A
2N4869
2N5484
2N5485
2N5486 '

LS4340
LS4341
LS4391
LS4392
LS4393

2N5457
2N5458
ITE439 I
ITE4392
ITE4393

M02904AF
M02904F
M02905
M02905A
MD29D5AF

ITl39
ITI39

J1404
JI405
JI406
J174
J174-'18

IT503
IT504
IT505
JI74
JI74

J5163
K114-18
K210-18
K21l-18
K212-18

2N5486
2N5555
2N5397
2N5397
2N5397

LS4416
LS4856
LS4857
LS4858
LS4859

ITE4416
ITE4091
ITE4092
ITE4093
ITE4091

MD2905F
M02974
M02975
M02978
M02979

ITl20
ITl20
IT120
ITl20

J175
J175-18
JI76
J176-18
J177'

JI75
JI75
JI76
JI76
JI77

K300-18
K304-18
K305-18
K308-18
K309-18

2N5397
2N5486
2N5484
J308
J309

LS4860
LS4861
LS5103
LS5104
LS5105

ITE4092
ITE4093
2N5484
2N5485
2N5486

M03008
MD3250
MD3250A
M03250AF
MD3250F

ITl20
ITl32
ITl31

JI77-18
J201
J201-18
J202
J202-18

JI77
J201
,J201
J202
J202

K310-18
KE3684
KE3685
KE3686
KE3687

J310
2N3684
2N3685
2N3686
2N3687

LS5245
LS5246
LS5247
LS5248
LS5358

ITE4416
2N5484
2N5486
2N5486
J204

MD3251
M03251A

ITI32
ITl31

M03251F
MD3409

ITl29

KE3970

J2.04
J202
J202
J203
J203

2N486BA

2N4869A
2N4869A
2N4869A
2N5457
2N5458
2N5459

UD3251AF

..

ITl22
ITI22

IT139

ITl39'
ITl29

....
....
..
..
....

ITI29
ITI29

ITI29
ITI29
ITI22
ITI39
ITl39

..

..

..

•• CONSULT FACTORV

A·18

INDUSTRY
STANDARD
M03410

1.403467
MD3467F
MD3725
MD3725F

NEAREST
INTERSIL
EQUIVALENT
ITI29
IT139

..

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

....

INDUSTRY
STANDARD

MEF5563
MEM511
MEMSllA
MEM511C
MEMS17

U403
3N172
3N172
3N172

MHQ6100

3NI72

MMF2

MEMS17A
MEMSl7B
MEMS17C

MMF3
MMF4,
MMF5
MMF6

2N5198
2N3922
2N5199

MEM550
MEM550C

3N172
3N172
3N172
3NI89
3N189

MMT3823

2N3823

MPQ6700
MPQ918
MQII20
MQII29
MQ2218

MHQ610QA

MKIO
MMFI

2N4416

MPQ6100A

MPQ6501
MPQ6502
,MPQ6600
MPQ6600A

NEAREST
. INTERSIL
EQUIVALENT

....
....

MD3762
MD3762F
M04957
M05000
MOSOODA

IT139

M050008

ITI32
IT129
IT139

MEM550F

3NI89

MEM551
MEM55lC

3NI89

IT122

MEM556
MEM556C

3N172
3N172

MP301
MP302
MP303
MP310
MP311

IT1248
ITI25
ITI248
2N4045
2N4045

MQ2218A
MQ2219
MQ2219A
MQ2369
MQ2484

ITI22
IT132
IT132

MEM560
MEM560C
MEM561
MEM561C

3NI61
3NI61
3NI63
3NI63
2N4351

MP312
MP318
MP350
MP351
MP352

2N4044
ITI20A
ITI32

IT130
ITI30

MQ2904
MQ2905
MQ3251
MQ3467
MQ3725

..
....
....
..
......
....
....
....
..

ITl32

MEM562C

MP358

MEM563

2N43S!
2N4351

MEM563C
MEM711
MEM712

2N4351
M116
M116

MP3954
MP3954A
MP3955
MP3956

ITl30A
2N3954
2N3954A
2N3955
2N3956

M03762
MQ3798
MQ3799
MQ3799A
MQ70DI

..

MEM712A
MEM713
MEM806
MEM806A
MEM807

MII6
3N170
3NI63
3NI63
3N172

MP3957
MP39S8
MP5905
MP5906
MP5907

2N3957
2N3958
2N5905
2N5906
2NS907

MQ7003
MQ7004
MQ7007
MQ930
1.40982

MEM807A
MEM814
MEM816
MEM817
MEM823

3N172
3NI61
3NI72
3N172
MFE823

MP5908
MP5909
MP5911
MP5912
MP804

2N5908
2N5909
2N5911
2N5912
2N5520

MTFIOI
MTFI02
MTFl03
MTF104
N05700

2N5484
2N5484
2N5457
2N5459
ITI20A

MEM954
MEM954A
MEM9548
MEM955
MEM9S5A

3N188
3N188
3NI88
3N190
3,N190

MP830
MP831
MP832
MP833
MP835

2N5520
2N5521
2N5522
2N5523
2N3954

N05701
N05702
NOF9401
NDF9402
NOF9403

ITl20A
ITl20
IT500
IT501
IT502

3N190
2N4092
2N4338
2N4858
2N4416

MP836
MP837
MP838
MP839
MP841

2N3955
2N3955
2N3956
2N3957
2N5521

NOF9404
NOF9405
NDF9406
NDF9407
NOF940B

IT503
ITS04
IT500
IT501
IT502

M07000
M07D01
M0700lF
M07002
MD7D02A
MD70028
M07003
MQ7003A
MD7003AF

M070038
MD7003F
M07004
MD7004F
M070C7

..

ITI29

..

IT132
ITI32
IT132

..

IT122

..
..
..

IT129
ITI29

M07007A
1.4070078
MD7007BF
M07007F
M07DS

ITI29
IT129

MD708A
MD708AF
MD7088
MD708BF
M070BF

ITl29

MOB001
M08002
M08003
1.40918
M0918A

ITl20
ITl20
IT122

....
..
....

ITl29

IT129

....
....
..

MEM562

3N190

2NS197
2N3921

2N3955A

....
....
......
..
..

M0918AF
1.409188
M0918F
M0918F
M0982

IT139

MEM9S5B
MF510
MF803
MF818
MFE2000

MD982F
1.40984
MEFI03
MEF104
MEF3069

ITI39
2N5457
2N54S9
2N4341

MFE2001
MFE2004
MFE200S
MFE2D06
MFE2007

2N441S
2N4093
2N4092
2N4091
2N4860

MP842
MPF 102
MPF 103
MPF 104
MPFI05

2N5523
2N5486
2NS457
2N545S
2N5459

NOF9409
NDF9410
NF3819
NF4302
NF4303

IT503
IT504
2NS484
2N5457
2N5459

MEF3070
MEF3458
MEF3459
MEF3460
MEF3684

2N4339
2N4341
2N4339
2N4338
2N3684

MFE2008
MFE2009
MFE2010
MFE2011·
MFE2012

2N4859
2N4859
2N4859
2N5433
2N5434

MPF 106
MPFI07
MPF 108
MPF 109
MPFl11

2N5485
2N5486
2N5486
2N5484
2N5458

NF4304
NF4445
NF4446
NF4447
NF4448

2N5458
2N5432
2N5433
2N5433
2N5433

MEF3685
MEF3686
MEF3687
MEF3821
MEF3822

2N3685
2N36B6
2N3687
2N3821
2N3822

MFE2012
MFE2093
MFE2094
MFE2095
MFE2133

2N5433
2N4338
2N4339
2N4340
2N4860

MPF 112
MPF1Sl
.MPF208
MPF209
MPF256

2N5458
2N5398
2N3821
2N3821
ITE4416

NF500
NF501
NF506
NF5101
NF5102

2N4224
2N4224
2N4416
2N4867
2N4867

MEF3823
MEF3954
MEF3955
MEF3956
MEF3957

2N3823
2N3954
2N3955
2N3956
2N3957

MFE2912
MFE3002
MFE3003
MFE3020
MFE3021

2N5433
3NI70
3N164
3N166
3NI66

MPF4391
MPF4392
MPF4393
MPFB20
MPF970

ITE4391
ITE4392
ITE4393
J310
JI75

NF5103
NF511
NF5163
NF520
NF521

2N4867
2N4860
2N4341
2N3684
2N3685

MEF3958
MEF4223
MEF4224
MEF4391
MEF4392

2N3958
2N4223
2N4224
ITE4391
ITE4392

MFE4007
MFE4008
MFE4009
MFE4010
MFE4011

2N3686
2N3686
2N368S
2N2608
2N2608

MPF971
MPQIOOO
MPQI050
MPQ2221
MPQ2222

J175

NF522
NF523
NF530
NF531
NF532

2N3686
2N3865
2N4341
2N4339
2N4341

MEF4393
MEF4416
MEF4856
MEF4857
MEF4858

ITE4393
ITE4416
2N4856
2N4857
2N4858

MFE4012
MFE5000
MFE823
MH02221
MH02222

MFE823

..
....

MPQ2369
MPQ2483
MPQ2484
MPQ2606
MPQ2607

NF533
NF5457
NF5458
NF5459
NF5484

2N4339
2N5457
2N5458
2N5459
2N5484

MEF4859
MEF4860
MEF4861
MEF5103
MEF5104

2N4859
2N4860
2N4861
ITE4416
ITE4416

MHQ2369
MHQ2483
MHQ2484
MHQ2906
MH02907

NF5485
NF548S
NF5555
NF5638
NF5639

2N5485
2N5486
2N5484
2N5638
2N5639

MEF5105
MEF5245
MEF5246
MEF5247
MEF5248

ITE4416
ITE4416
2N5484
2N5486
2N5486

MHQ3467
MHQ3546
MHQ3798
MHQ3799
MHQ4001A

NF5640
NF5653
NF5654
NF580
NF581

2N5640
2N4860
2N4861
2N5432
2N5432

MEF5284
MEF5285
MEF5286
MEF5561
MEF5562

2N5484
2N5485
2N5486
U401
U402

MHQ4002A
MHQ4013
MHQ4014
MHQ6001
MHQ6002

NF582
NF583
NF584
NF585
NF6451

2N5433
2N5434
. 2N5433
2N4859
U310

..
..

2N2609

....
....
..
....
..
....

......
....

MPQ33,o3
MPQ3467
MPQ3546
MPQ3725
MPQ3725A
MPQ3762
MPQ3798
MPQ3799
MPQ3904
MPQ3906

MPQ4003
MPQ40Q4
MPQ6001
MPQ6002
MPQ6100

A·19

..

......

......
....
....
....
..

....
....
..

....
....
..

..

CONSULT FACTORY

5
D~DIL

,

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

INDUSTRY
STANDARD

S75V21
575V22
SA2253
SA2254
SA2255

ITi22
ITl22
ITl22

SU207B
5U2079
SU20BO
SU20BO
5U20BI

SA2644

IT120

5U2081

U404

SA2648
SA2710
SA2711
SA2712

ITl20
ITl20
ITl20
ITl21

SU2098
SU2098A

S75VOI
S75V02

U310
2N4220
2N4220

S75V03
575Vll
S75V12

NKTB01l3

2N3B21
2N4339
2N4339
2N4339

-

2N4339

NKTB0215

2N4339
2N4339

NKTB0216
NKTB0421

NEAREST '
INTERSIL
EQUIVALENT

SU2076
SU2077
SU2077

U310
U310

NF6454
NKT80111
NKTB01l2

NKTB02!2
NKTB02!3
NKTB0214

INDUSTRY
STANDARD

....
..

NF6452
NF6453

NKT80211

NEAREST
INTERSIL
EQUIVALENT

IVN5000BNF

....

INDUSTRY
STANDARD

2N3954
2N3954
2N3954

SU2075
5U2076

T0520

'NEAREST
INTERSIL
EQUIVALENT

T0522
T0523
T0524

IT139
ITl39
ITl39
ITl39
IT139

T0525
T0526
T0527
T052B
T05432

IT132
IT132
IT13!
IT13!
2N5432

2N5197

T05433
T05434

2NS433
2N5434

2N5197
2N5196

T0550
T05902

2N5197

T05902A

ITl29
2NS902
2N5902

T052'1

2N3955
2N3954
2N3955

2N3955
U404
U404 \

U404

NKTB0422
NKTB0423

2N4220
2N4220
2N4220

NKT80424

2N4220
2N5484

ITl21
ITl22
ITl20
ITl20
ITl21

SU2099A
SU2365
SU2365A
SU2366
SU2366A

2N5197
2N3954

TD59D3A

2N5903
2N5903

2N4338
2N433B
2N433B

SA2713
SA2714
SA2715
SA2716
SA2717

T05903

NPCI08
NPC211N
NPC212N
NPC213N

2N3954

T05904

2N5904

2N3955
2N3955

TD5904A

T05905

2N5904
2N5905

NPC214N

2N4339

SA271S

IT122

5·U2367

NPC215N
NPC216N
NP05564
NP05565

2N4339
2N4339
2N5564
2N5565

SA2719
SA2720
SA2721
5A2722

ITl20
ITl21
IT122
ITl20

SU2367A
SU2368
SU2368A
SU2369

2N3955
2N3955

NPOS566
NPOB302
NP08303
NVOI09NI

2N5566
2N3954
2N3955
2N3956
VN99AJ

SA2723
SA2724
SA2726
SA2727
SA2738

ITl21
ITl22
ITl22
ITl22
IT120A

SU2369A
SU2410
SU2411
SU2412
SU2652

QT3
PIOO4
PIOO5
PI027
PI02B

2N4338

2N5116
2N5115
2N5267
2N5270

SA2739
SOFIOOI
SOFIOO2
SOFIOO3
SOF500

ITl20
2N5432
2N5433
2N5520

SU2652M
SU2653
SU2653M
SU2654
SU2654M

2N5520
2N5520
2N5520
2N5520
2N5520

SU2655
SU2655M
SU2656
, SU2656M
SX3Bl9

U402
U402
U404
U404
2N5484
2N260B
ITl29
ITl29
ITl29
IT129

T1542
TIS5B
TIS59
TIS6B
TIS69

2N4393

NP08301

I

2N5434

SU2098B
SU2099

PI029
PI069E
PIOB6E
PI087E
Pl1l7E

2N5270

2N2609
2N5115
2N5516
2N5640

SOF501
SOF502
SOF503
SOF504
SOF505

PlllSE
Pl1l9E
PF510
PF5101
PF5102

2N5641
2N5640
2N5115
2N4867

SOF506
SOF507
SOFS08
SOF509
SOF510

2N5520
2N5520
2N5520
2N5520
2N3954

SX3B20
TOIOO

SOF512
SOF513
SOF514
SOF66l'

2N3954
2N3954
2N3954
ITl22

T0201
T0202
T02219
T0224

2N4867

TD5905A

T05906
TDS906A

2N3956
2N3956
2N3957

T05907
T05907A

,2N3957
2N5907
2N590B
2N5909

T05908
TD5908A

T05909
TD5909A

T0591!

U401

TD5911A

U401
U401
U401
U401
U401

T0101

TOI02
T0200

T05912
TD5912A

T0700
TO 70 I
I

T0709
T0710

2N5905
2N5906
2N5906
2N5907
2N5907
2N5908
2N590B
2N5909
2N5909
IT59!1
IT5911
IT5912
IT5912
ITl22
ITl22

T0711
T0713

!Tl22
ITl22
IT122
ITl22

T1514

2N4340

TIS25
TIS26
TIS27
T1534
TIS41

,2N3955
2N54B6
2N4859

2N3954
2N3954

PF5103

2N4867

PF511

2N5114

Pl1091
PLlO92

2N3B23
2N3823

PLlO93

2N3823

SDF662

1T122

T0225

ITl29
ITl29
ITl29
ITl22
1T122

PLlO94
PN3684
PN3685
PN3686
PN3687

2N3823
2N3684

SOF663
SES3Bl9

2N36B5
2N3666
2N3687

ITl22
2N5484
2N4338

2N39S6
2N4391

TI$74

2N4392

2N4338

TIS75
TIS8B

2N4393

2N4339

ITl22
ITl22
ITl22
ITl22
ITl21

TIS70
TIS73

SFT602
SFT603

T0226
T0227
T022B
T0229
T0230

PN4Q91

ITE4091
ITE4092
ITE4093
J204
J202

SFT604
SL30lAT
SL30lBT
SL30lCT
SL30lET

2N4339
ITl29
ITl29
ITl29
ITl29

T0231
T0232
T0233
T0234
T0235

ITl21
ITln
ITl22

TISBBA
TIXS33
TIXS35

2N4392
2N4857

TIXS36
TIXS41

2N4391

ITl22

J203
J204
J202
2N5461
2N5460

SL360C
SL362C
SU2000
SU2020
SU2021

ITl29
ITl29
2N4340
2N3954
2N3954

T0236
T0237
T023B
T0239
T0240

ITl22
ITl22
ITl22
ITl22
ITl21

' TIXS42
TIXS59
TIXS7B
TIXS79
TN4117

2N5639

ITE4391
ITE4392
ITE4416

SU2022
SU2023
SU2024

.2N3954
2N3954
2N3954

T0241
T0242
T0243

SU2Q25

2N3954

SU2026

2N3954

T0244
T0245

ITl21
ITl20A
ITl20A
ITl29
ITl29

H14117A
TN411B
TN411BA

2N4856
2N4B57

SU2027
SU2028
SU2028
SU2029
SU2029

2N3954
2N3954
2N3954
2NS197
2N3954

T0246
T0247
T024B
T0250
T02905

ITl29
ITl29
ITl29
ITl20A
I1139

TN4338

2N3955
2N3954

T0400
T0401

2N5198

T0402

1T139

VN99AK

SU2030
SU2030
SU2031
SU2031
SU2032

2N3954
2N3954

T0500
T0501

..

SU2032
SU2033
SU2033
SU2034
SU2034

2N3954
2N3954
2N3954
2N3955
2N3954

T0502
T0509
TOSIO
T0511
T0512

SU2035
SU2035

2N3955
2N3954

T0513
T0514

SU2074

2N3954

T0511

SU2074
SU2075

2N3954
2N3954

T0518
T0519

PN4092
PN4093

PN4220
PN4221
PN4222
PN4223

PN4224
PN4342

PN4360
PN4391
PN4392
PN4416
PN4856
PN4857

PN485B
PN4859

2N4858

PN4860

2N4860
2N4B61
2N5460

2N4859

PN4861
PN5033
PTCl51
PTCIS2

2N5484
2N5485

PV210

VN35AK

PV211
PV212
Q2T2222
Q2T2905
Q2T3244
Q2T3725
S55VOI
S55V02
S55Vll
S55V12

S55V21
S55V22

VN67AK

-

..
......
......
..

..

$FT601

A·20

ITl22

2N3955A

2N4416

2N4~16

2N4859
2N5459

2N4341
2N4341
2N4117

TN4119

TN4119A

2N4U1A
2N4118
2N4118A
2N4119
2N4119A

2N433B
2N4339

TN4339

TN5277

2N4340
2N4341
2N4341

TN4340
TN4341
TN5278

2N4341

TP5114
TP5115

2N5114

ITl39
ITl39

TP5116

UIIO

2N5116
2N26,08

ITl39
ITl32
IT132
ITl32
ITl32

UIII
U1l2
U1l3
U1l4
U1l77

2N260B
2N2608
2N2608
2N2608
2N4220

ITl32
IT132
IT132
ITl32
ITl32

U1l78
U1l79
UllBQ

2N3821
2N3821
2N4221
2N4220
2N3821

ITl39
ITl39

f

2N54B4
2N54B6
2N3955A

U1l81
U1l82

2N5115

..

CONSULT FACTORY

D~OIL
INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

....
......
......

U1277
U1278
UI279
U1280
U1281

2N3684
2N3685
2N3686
2N3684
2N3822

U301
U3010
U3011
U3012
U304

2N5115
2N4341
2N4340
2N4338
U304

UC714E
UC734
UC734E
UC751
UC752

2N4341
2N4416
2N4416
2N4340
2N4340

VN130BN2
VN1308N3
VN13Q8N6
VN130BND
VN1309N2

i..J1282
UI283
U1284
UI285
U1286

2N4341
2N4340
2N4341
2N4220
2N4341

U305
U306
U308
U309
U310

U305
U306
U308
U309
U310

UC753
UC754
UC755
UC756
UC805

2N4341
2N4340
2N4341
2N4340

VNI309N3
VN1309N6
VN1309ND

VNIA

2~5270

VN18

VN67AJ

U1287
U1321

U311
U312
U314
U315
U316

U310
2N5397
2N5555
2N5397
U309

ueB07

2N5115
2N5270
2N260B
2N2608
2N2608

VN2

VN67AK

VN2A

VN89AB

U1322
U1323
U1324

2N4092
2N4860
2N3822
2N3822
2N3687

VN28
VN3
VN3QAA

VN67AK

U1325
U133
UI420
U1421
U1422

2N3686
2N260B
2N3821
2N3822
2N3822

U317
U320
U321
U322
U328

U310
2NS433
2N5434
2N5433

2N2609
2N5397
2N5397
1T126
2N4869

VN3QAB

UXC2910
veR10N

VN30AB
VN35AJ
VN35AK
VN35AA
VN35AB

U146
U147
UI48
U149
U168

2N2606
2N2608
2N2608
2N2609
2N2609

U329
U330
U331
U350
U401

....

VNAllN
2N3958
2N3958
2N4341
VCR2N

VN35AJ
VN35AK
VN35JA
VN3A
VN3B

VN35AJ
VN35AK

U401

VCAllN
VCAI2N
VCR13N
VCA20N
VCR2N

U1714
U1715
U182
U183
U1837E

2N4340
2N4340
2N4857
2N3824
2N5486

U402
U403
U404
U405
U406

U402
U403
U404
U405
U406

VCR3P
VCR4N
VCASP
VCR6P
VCR7N

VCR2P
VCR4N
VCR5P
VCR6P
VCR7N

VN4
VN40AF
VN45JA
VN46AF
VN4A

1VN5000BNE
VN40AF

U184
UI897E
U1898E
U I 899E
U197

2NS397
Ul-897
UI898
U1899
2N4338

U410
U4ll
U412
U421
U422

2N3955
2N3956
2N3958
U421
U422

VF28
VF8ll
VF815
,VFW40
VFW40A

2N4392
2N4858
2N4858
1T122
1T120

VN48
VN5
VN5A
VN5B
VN64GA

1VN5000BND

U198
UI99
U1994t
U200
U201

2N4340
2N4341
2N4416
2N4861
2N4860

U423
U424
U425
U426
U430

U423
U424
U425
U426
J3091X2)

VMP1
VMPll
VMP12
VMP2
VMP21

IVN6657
IVN6657
1VN6658
1VN6660
1VN6660

VN66AF
VN66AJ
VN66AK
VN67AA
VN67AB

VN66AF
VN66'AJ
VN66AK
VN67AA
VN67AB

U202
U2047E
U221
U222
U231

2N4859
2N4416
2N4391
2N4391
U231

U431 U440
U441
UCIOO
UCllO

J3101X2)
U440
U441
2N3684
2N3685

VMP22
VMP4
VNOI04Nl
VNOI04N2
VNOI04N3

VN67 AJ
VN67AK
1VN5000AND

VN67AF
VN67AJ
VN67AK
VN84GA
VN86t1F

VN67AF
VN67AJ
VN67AK

U232
U233
U234
U235
U240

U232
U233
U234
U235
2N5432

UCI15
UC120
UCI30
UCI55
UC1700

2N4340
2N3686
2N3687
2N4416
3N163

VNOI04N5
VNOI04ND
VNOI06Nl
VN0106N2
VNOI06N3

VN67AJ
VN67AK
1VN5000ANE

VN88AF
VN89AA
VN89AB
VN89AF
VN90AA

VNB8AF
VN89AA
VN89AB
VN89AF
VN90AA

U241
U242
U243
U244
U248

2N5433
2N5432
2N5433
2N5433
2N5902

UC1764
UC20
UC200
UC201
UC21

3N163
2N3686
2N3824
2N3824
2N3687

VNOl06N5
VNOI06N6
VNOI06ND
VNOI08Nl
VNOI08N2

VN99AJ
VN99AK

VN90AB,
VN98AJ
VN9BAK '
VN99AJ
VN99AK

VN90AB
VN98AJ
VN98AK
VN99AJ
VN99AK

U248A
U249
U249A
U250
U250A

2N5906
2N5903
2NS907
2N5904
2N5908

UC210
UC2130
UC2132
UC2134
UC2136

2N441G
2N5452
2NS4S3
2N5454
2N5454

VNOIOBN3
VN0108N5
VNOIOBN6
VNOI08ND
VNOI09N2

U251
U251A
U252
U253
U254

2N5905
2N5909
1T5911
1T5912
2N4859

UC2138
UC2139
UC2147
UC2148

2N5454
2N39S8
2N3958
2N3958
2N3958

VNOI09N3
VNOI09N5
VNOI09NO
VNI
VNf014N6

U255
U256
U257
U257/TO-71
U266

2N4860
2N4861
U257
U257/TO-71

2N3822
2N4869
2N4869
,2N4091
2N4392

VNI0KM
VN1204Nl
VN1204N2
VN1204N5
VN1204NO

IVN5000ANE
1VN5200KNO
1VN5200TND
!VN5201CND

2N~856

UC220
UC240
UC241
UC250
UC251

VPOI06N2
VP0106N3
VPOI06N5
VPOI06N6
VPOI06ND

U273
U273A
U274
U274A
U275

2N4118A
2N4118A
2N4119A
2N4119A
2N4119A

UC2766
UC300
UC310
UC320
UC330

3NI66
2N2608
2N2607
2N2607
2N2607

VN1206Nl
VN1206N2
VN1206N5
VN1206ND
VN1208Nl

1VN5200KNE
1VN5200TNE
IVN5201CNE

VPOI08NI
VPOID8N2
VP0108N3
VP0108N5
VPOI08N6

U275A
U280
U281
U282
U283

2N4119A
2N5452
2N5453
2N5453
2N5453

UC340
UC40
UC400
UC401
UC41

2N2607
2N2608
2N5270
2N5116
2N2608

VN 1208N2
VN1208N5
VN120BND
VN1209Nl
VN 1209N2

1VN5200TNF
1VN5201CNF

U284
U285
U290
U291
U295

2N5454
2N5454
2N5432
2N5434
2N5432

UC410
UC420
UC450
UC451
UC588

2N5268
2N5267
2N5114
2N5116
2N4416

VN1209NS
VN1209ND
VN1304N2
VN1304N3
VN 1304N6

1VN5201CNF

U296
U300
U3000
U3001
U3002

2N5434
2N5114
2N4341
2N4339
2N4338

UC703
UC704
UC1()S
UC707
UC714

2N4220
2N4220
2N4224
2N4860
2N3822

VN1304ND
VN1306N2
VN1306N3
VN1306N6
VN1306ND

UC21~9

UC814
UC851
UC853
UC854
UC855
UTI 00

UTI01

..
....

I

VN33AK

VN35AA
VN35AB

..
....
....
..
....
..
....
..

IVN5000ANE
VN30AA

VN33AJ

IVN6661

1VN5000ANF

VN89AA

"

..

1VN5000ANF
1VN5000AND

..

VN46AF
1VN5000BNF

....
....

..

1VN5000VNF

VN99AK

VND
VNDA
VNDB
VPOI04N1
VP0104N2

..

VPOI04N3
VPOI04N5
VPOI04N6
VPOI04ND
VPOI06N1

VN67AJ

..

..

1VN5200KNF

..

1VN5200KNF
IVN5200TNF

..

......
......
....

VPOI08ND
VPOI09Nl
VPOI09N2
VP0109N3
VP0109NS
VPOI09N6
VPOI09ND
VPI
VP1A
VPIB
VP2
VP2A
VP2B
VP3
VP3A

....
....
..

......
....
....
....
..
......
....
......
....

....
....
..
....
....
..

"CONSULT FACTORY

A·21

D~DIL
IHDUS1'RY
STANDARD

NEAREST
IIfTEIISIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
IIITERSIL
EQUIVALENT

INIIUS1'RY
STAIIDAIID

NEAREST
IIITERSIL
EQUIVALENT

IIIDUS11IY
STAIDARD

NEAREST
IIITERSIL
EQUIVALENT

..
......
..
....
....
..

VP3B
VP4
VP4A
VP4B
VP5
VP5A
VP5B
VPD
VPDA
VPDB
W245A
W245B
W245C
W300
W300A

ITE4416
ITE4416
ITE4416
2N5398
2N5397

W3008
W300C
W300D
'WK5457
WK5458

2N5397
2N5397
2N5398
2N5457
2N5458

WK5'459
ZDT40
ZDT41
ZDT42
ZDT44

2N5459
ITl29
ITl29
ITl29
ITl29

ZDT45

ITl29

-

,
~

...
A·22

CONSULT FACTORV

~

':,

',','

"

''';_::'':;'::~~O

JFET Single Switches
N-Channel
J105-7
J111-13
U200-2
U1897-99
2N3970-72
2N4091-93
ITE4091-93
2N4391-93
ITE4391-93
2N4856-61
2N5432-34
2N5638-40
P-Channel
1T100/1
J174-77
2N3993/4
2N5018/19
2N5114-16

Page
1-14
1-15
1-32
1-50
1-60
1-64
1-64
1-70
1-70
1-72
1-80
1-88

2N4416
ITE4416
2N4867-69

2N5397/98
2N5457-59
2N5484-86
P-Charlnel
U304-6
2N2607-9
2N5460-65

1-71
1-71
1-73
1-79
1-82
1-84

P-Channel
3N161

3N163/64
3N172/73
IT1700
MFE823
Dual P-Channel

1,37 3N165/66
1-51 3N188-91
1-83

JFET Dual
Amplifiers

N-Channel
U231-35
1-35
1-13
U257
1-36
1-30
U401-6
1-41
1-61
U421-26
1-43
1-74
U440/41
1-44
1-75
IT500-5
1-45
2N3921/22
1-58
JFEr Dual Switches 2N3954-58
1-59
2N5196-99
1-78
N-Channel
2N5452-54
1-81
2N5564-66
1-87
2N5515-24
1-85
2N5902-9
1-89
JFET Single
2N5911/12
1-90
Amplifiers
IT5911/12
1-90
2N6483-85
1-91
N-Channel
. IMF6485
1-93
J201-4
1-33
J308-10
1-38
MOSFET Switches/
U308-10
1-39
Amplifiers
2N3684-87
1-52
2N3821/22
1-55
N-Channel
2N3823
1-56
1-17
M116
2N3824
1-57
3N170171
1-28
2N4117-19
1-65
1T1750
1-49
2N4220-22
1-66
2N4351
1-69
2N4223/24
1-67
2N4338-41
1-68

1-25
1-26
1-29
1-48
1-47
1-27
1-31

Bipolar Dual
Amplifiers
NPN Dev;ices
LM114
IT120-22
IT124
IT126/27
IT140
2N4044/45
2N4100
2N4878-80
PNP Devices
IT130-32
IT136-39
2N3810/11
2N5117-19

Special Function
High Speed Dual Diodes
1D100/1
1-11
Voltage Controlled
Resistors
VeR2-7

Y~

••••••••I•••••••••••

~DmsmmDmm

Switches - Junction FET
Ordering Inlormation
Prelerred
Part
Package
Number

rDS (on)
max
II

Vp
min/max
V

BV GSS
min
V

IGSS
max
pA

10 (off)
max
pA

loss
min/max
rnA

N·channel: Generally requires driver circuit to translate the popular logic leyels to voltages required to divide tne JFET.
-40
250
50
-4.0 -10.0
TO·18
30
2N3970
25
-40
250
-5.0
-2.0
2N3971
TO·18
60
5
-40
250
-3.0
100
-0.5
2N3972
TO·18
-40
30
-200
200
-5.0
-10.0
30
2N4091
TO·18
-40
200
15
-200
-7.0
-2.0
2N4092
TO·18
50
8
-40
200
-200
-5.0
-1.0
2N4093
TO·18
80
100
50
-10.0
-100
-40
TO·18
30
-4.0
2N4391
-40
100
25
-100
-2.0
-5.0
2N4392
TO·18
60
-40
100
5
-100
-3.0
100
-0.5
2N4393
TO·18
-40
250
50
-10.0
-250
-4.0
2N4856
TO·18
25
-40
250
20
-250
-6.0
-2.0
2N4857
TO·18
40
-40
250
8
-250
-4.0
-0.8
2N4858
TO·18
60
50
-250
-30
250
-4.0
-10.0
2N4859
TO·18
25
-30
250
20
-6.0
-250
-2.0
2N4860
TO·18
40
-30
250
8
-250
-4.0
-0.8
2N4861
TO·18
60

D

150
75
30

150
75
30
100
80
100
80

CRSS
max
pF

max
pF

50
90
180
65
95

25
25
25
16
16

6.0
6.0
6.0
5.0
5.0

140
55
75
100
34

16
14
14
14
~8

5.0
3.5
3.5
3.5
6.0

·60
120
34
60
120

18
18
18
18
18

6.0
6.0
8.0
8.0
8.0

tap
max
ns

CiSS

-10.0
-9.0
-4.0
-12.0
-8.0

-200
-200
-200
-I nA
-I nA

-25
-25
-25
-30
-30

200
200
200
InA
InA

150
100
30
50
,25

41
41
41
24
54

30
30
30
10
10

15.0
15.0
15.0
4.0
4.0

-5.0
-2.0
-1.0
-4.0

-6.0
-10.0
-10.0
-10.0
-10.0

-I nA
-200
-200
-200
-100

-30
-40
-40
-40
-40

InA
200
200
200
100

5
30
15
8
50

63
65
95
140
55

10
16
16
16
14

4.0
5.0
5.0
5.0
3.5

100
30
3
6
8

-2.0
-0.5
-4.5
-2.0
-0.5

-10.0
-10.0
-10.0
-6.0
-4.5

-100
-100
-3 nA
-3 nA
-3 nA

-40
-40
-25
-25
-25

100
100
3 nA
3 nA
3 nA

25
5
500
200
100

75
100
20
20
20

14
14

3.5
3.5

TO·92
TO·92
TO·92

30
50
100

-3.0
-1.0
-0.5

-10.0
-5.0
-3.0

InA
InA
InA

35
35
35

InA
InA
InA

20
5
2

2N3993
2N3994
2N5114
2N5115
2N5116

TO·72
TO·72
TO·18
TO·18
TO·18

150
300
75
100
150

4.0
1.0
5.0
3.0
1.0

9.5
5.5
10.0
6.0
4.0

1.2 nA
1.2 nA
500
500
500

25
25
30
30
30

1.2 nA
1.2 nA
500
500
500

-10
- 2
-30 -90
-15 -60
- 5 -25

16
16
25
25
25

4.5
4.5
7.0
7.0
7.0

IT100
ITIOI
JI74
JI75
JI76

TO·18
TO·18
TO·92
TO·92
TO·92

75
60
85
125
250

2.0
4.0
5.0
3.0
1.0

4.5
10.0
10.0
6.0
4.0

200
200
InA
InA
InA

35
35
30
30
30

100
100
-I nA
-I nA
-I nA

-10
-20
-20 -100
- 7 -60
- 2 -25

35
35

12.0
12.0

J177
J270
J271
PI086
PI087

TO·92
TO·92
TO·92
TO·92
TO·92

300

0.8
0.5
1.5

2.25
2.0
4.5
10.0
5.0

InA
200
200
2 nA
2 nA

30
30
30
30
30

-I nA

~1.5 -20
.- 2 -15
- 6 -50
-10.0
- 5.0 -

20
20
45
45

5.0
5.0
10
10

2N5432
2N5433
2N5434
2N5638
2N5639

TO·52
TO·52
TO·52
TO·92
TO·92

5
7
10
30
60

2N5640
ITE4091
ITE4092
ITE4093
ITE4391

TO·92
TO·92
TO·92
TO·92
TO·92

100
30
50
80
60

ITE4392
ITE4393
JI05
JI06
JI07

TO·92
.10·92
TO·92
TO·92
TO·92

JIll
JI12
JI13

-4.0
-3.0
,-1.0

150
75
30

P:channel:

75
150

1-2

-10 nA
-10 nA

37
68
102

15
25

Switches and Amplifiers Ordering Inlormalion
Preferred
Part
Package
Number
P-Channel

~nhancement:

3N161
3N163
3N164
3N172
3N173
1T1700

VGS

MOSFET

(TH)

BV GSS
min
V

VGS(Off)

minImax
V

IGSS
max
pA

loss
max
pA

G,s
min

ros (on)
max

~mho

II

IQ Ion)
min
mA

Gen. used where max isolation between signal source and logic drive required: sw. ··On" resistance varies with signal amplitude.

lO-72
TO-72
lO-72
TO-72
TO-72
lO-72

-1.5
-2.0
-2.0
-2.0
-2.0
0.2

-25
-40
-30
-40
-30
-40

-5.0
-5.0
-5.0
-5.0
-5.0
-5.0

-10 nA
-200
400
-400
-10 nA
200

-100.0
-10.0
10.0
-10.0
-500.0
10.0

3500.0
2000.0
1.0
1500.0

-40·
- 5
- 3
- 5
- 5
2

250
300
250
350
400

2.0

-120 Diode Protected
- 30
- 30
- ~O Diode Protected
- 0

I

N-Channel Enhancement: Can switch positive signals directly from TTL logic: gen. requires driver or translator circuit to switch bipolar Signals.
2N4351
2N170
2N171
1T1750
M116

TO-72
TO-72
TO-72
TO-72
TO-72

1.0
1.0
1.5
0.5
1.0

5.0
2.0
3.0
3.0
5.0

10 nA
10 nA
10 nA
10 nA

25
25
25
25
30

1000.0
1000.0
1000.0
30.0

10.0
10.0
10.0
10.0
100.0

3
-10
10
10

300
200
200
50
100

100
Diode Protected

Amplifiers-N-Channel Junction FET
Ordering Informalion
Preferred
Part
Number
Package

g,s
min
~ mho

Vp
minImax
V

IDss
minImax
mA

IGSS
max
pA

BV GSS
min
V

05.0
-3.5
-2.0
-1.2

-100
-100
-tOO
-100
-100

-6.0

en
max

CISS

erss

max
pF

max
pF

nvl \ Hz

-50
-50
-50
-50
-50

1.2
t.2
1.2
1.2
3.0

140 @ 100 Hz
140@ 100 Hz
140@ 100 Hz
140@ 100 Hz
200 @ 10 Hz

-50
-30
-50
-40
-40

3.0
2.0
2.0
1.5
1.5

200 @ 10 Hz

2N3684
2N3685
2N3686
2N3687
2N3821

TO-72
TO-72
TO-72
TO-72
TO-72

2000
1500
1000
500
1500

2.5
1.0
0.4
0.1
0.5

7.5
3.0
1.2
0.5
2.5

-2.0
-1.0
-0.6
-0.3
-4.0

2N3822
2N3823
2N3824
2N4117
2N4117A

TO-72
TO-72
TO-72
TO-72
TO-72

3000
3500

2.0
4.0

10.0
20.0

-8.0

70
70

0.03
0.03

0.09
0.09

-0.6
-0.6

-1.8
-1.8

-100
-500
-100
-10
-1

2N4118
2N4118A
2N4119
2N4119A
2N4220

TO-72
TO-72
TO-72
TO-72
TO-72

80
80
100
100
1000

0.08
0.08
0.2
0.2
0.5

0.24
0.24
0.6
0.6
3.0

-1.0
-1.0
-2.0
-2.0

-3.0
-3.0
-6.0
-6.0
-4.0

-10
-1
-10
-1
-100

-40
-40
-40
-40
-30

1.5
1.5
1.5
1.5
2.0

2N4221
2N4222
2N4223
2N4224
2N4338

TO-72
TO-72
TO-72
TO-72
TO-18

2000
2500
3000
2000
600

2.0
5.0
3.0
2.0
0.2

6.0
15.0
18.0
20.0
0.6

-6.0
-8.0
-0.8
-1.0

-100
-100
-250
-150
-100

-30
-30
-30
-30
-50

2.0
2.0
2.0
2.0
3.0

2N4339
2N4340
2N4341
2N4416
2N4867

TO-18
TO-18
lO-18
TO-72
TO-72

800
1300
2000
4500
700

0.5
1.2
3.0
5.0
0.4

1.5
3.6
9.0
15.0
1.2

-0.6
-1.0
-2.0

-100
-100
-100
-100
-250

-50
-50
-50
-30
-40

7
7
7
4
25

3.0
3.0
3.0
2.0
5.0

65@ 1 kHz
65 @ 1 kHz
65 @ 1 kHz

-0.7

-1.8
-3.0
-6.0
-6.0
-2.0

2N4867A
2N4868
2N4868A
2N4869
2N4869A

TO-72
-[0-72
TO-72
lO-72
lO-72

700
1000
1000
1300
1300

0.1
1.0
1.0
2.5
2.5

1.2
3.0
3.0
7.5
7.5

-0.7
-1.0
-1.0
-1.8
-1.8

-2.0 .
-3.0
-3.0
-5.0
-5.0

-250
-250
-250
-250
-250

-40
-40
-40
-40
-40

25
25
25
25
25

5.0
5.0
0.0
5.0
5.0

5@ 1 kHz
10@1 kHz
5@ 1 kHz
10@ 1 kHz
5@ 1 kHz

2N5397
2N5398
2N5457
2N5458
2N5459

lO-72
TO-72
TO-92
TO-92
TO-92

600_0
5000
1000
1500
2000

10.0
5.0
1.0
2.0
4.0

30.0
40.0
5.0
9.0
16.0

-1.0
-1.6
-0.5
-1.0
-2.0

-6.0
-01
-6.0
-7.0
-8.0

-100
-100
1 nA
1 nA
-1 nA

-25
-25
25
25
-25

1.2
1.3
3.0
3.0
3.0

3 dB@450MHz

-0.1
-0.1
-0.3

-B.O

5
5.5
7
7
7

(

1·3

65@ 1 kHz

10@1 kHz

3 dB@450MHz
3 dB @ 450 MHz
3dB@450MHz

N-Channel Junction FET continued

Amplifiers -

D

2N5484
2N5485
2N5486
ITE4416·
J201

TO·92
TO·92
TO·92
TO·92
T0-92

3000
3500
4000
4500
500

1.0
4.0
8.0
5.0
0.2

5.0
10.0
20.0
15.0
1.0

-0.3
-0.5
-2.0

J202
J203
J204
J308
J309

TO·92
TO·92
TO·92
TO·92
TO·92

1000
1500
1500
8000
10,000

0.9
4.0
1.2
12.0
12.0

4.5
20
typ
60.0
30.0

-0.8
-2,0
-0.5
-1.0
-1.0

J310
U308
U309
U310

TO·92
TO·52
TO·52
TO·52

8000
10,000
10,000
10.000

24.0
12.0
12.0
24.0

60.0
60.0
30.0
60.0

-2.0
-1.0
-1.0
-2.5

Amplifiers -

-0.3

-0.3
-4.0
-6.0
-6.0
-1.5

-1 nA
-1 nA
-1 nA
-100
'-100

-25
-25
-30
-30
-40

5
5
5
4
4

1.0
1.0
1.0
2.0
1.0

120@1 kHz
120@lkHz
120@1 kHz

-4.0
-10.0
-2.0

-100
-100
-100
-1 nA
cl nA

-40
-40
.-25
-25
-25

4
4
4

1.0
1.0
1.0

5@1 kHz
5@1 kHz
10@1 kHz
10@100Hz
10@100Hz

-1 nA
-150
-150
-150

-25
-25
-25
-25

IGSS
max
nA

BV 30 V
• Cr = 0.75 pF (typical)

TO-71

D

TO·78

GENERAL DESCRIPTION
The 10100 and 10101 are monolithic dual diodes intended
for use in applications requiring extremely low leakage
currents. Applications include interstage coupling with
reverse isolation, signal clipping and clamping and protec·
tion of ultra low leakage FET differential dual and operational amplifiers.

ABSOLUTE MAXIMUM RATINGS
(@ 25°C unless otherwise noted)

Maximum Temperatures
Storage Temperature
-65°C to +200°C
+200°C
Operating Junction Temperature
Lead Temperature (soldering, 10 sec. time limit) +300°C
Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating
Maximum Voltages & Currents
V R Reverse Voltage

• These leads are not to be tied together nor
connected to the circuit in any way.

CHIP
TOPOGRAPHY

300mW
1.7 mWfC

1f -7f T,~e~;'!i) ~.~:

30V

V D1D2 Diode to Diode Voltage

±50 V

IF Forward Current

20mA

.

019.1' IJ.

~L

".

ANODE #1

I R Reverse Current

100pA

2

ANODE #2

TYP. 2 PLACES .003Q DIAMETER

0040

•

6

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
PARAMETER

MIN.

VF

Forward Voltage Drop

0.8

BV R

Reverse E!reakdown Voltage

30

IR

Reverse Leakage Current

IIR -I R I
1
2

Differential Leakage Current

Cr

Total Reverse Capacitance.

10100, 10101
TYP.
MAX.

1.1

0.1
2.0

0.75
1-11

UNITS

TEST CONDITIONS

V

IF = 10mA

V

IR = 1 .uA

10
10
3

pA
pA
nA
pA

VR =
VR =
VR =
VR =

1

pF

V R =10V,f=lMHz

1 V, T A = 25°C
10 V, T A = 25°C
10 V, T A = 125°C
10 V

ID100, ID101
TYPICAL CHARACTERISTICS OF 10100/10101

CAPACITANCE

REVERSE CURRENT·VOLTAGE

D

12

1.0

11

0.9

10
~

Eo

0.8
LL
C-

9

0.7

8

.E'

0.6

7
6

4
3

./'"

2

... ""
o

V

./"

,./

r--

r---

0.4

./

0.3
0.2

/"
10

-

VOLTAGE

0.5

/

5

o

"- r--

VS.

0.1
15

25

20

5

30

10

FORWARD CURRENT·VOLTAGE

r---.:=
~~~~~~!'!'~~~~T~~

100 rnA ~:

100nA

~~L-L-~l-~~J-J--L-L-L-L~

o

0.1 D.2 0.3 0.4 0.5 0.6 0.70.8 0.91.01.1 1.2 1.3 1.4

1·12

15

20

25

30

IT100, IT101
P-Channel JFET
FEATURES

PIN
CONFIGURATION

• Interfaces Directly with T2L Logic Elements so that
No Extra Driver Stage is Required.
• rOS(on) < 750 for 5V Logic Drive

TO·18

II

• IO(off) < 100 pA

GENERAL DESCRIPTION
This P-channel JFET has been designed to directly interface
with T2L logic, thus eliminating the need for costly drivers,
in analog gate circuitry. Bipolar inputs of ±15 V can be
switched_ The FET is OFF for hi level inputs (+5 V or
+15 V) and ON for low level inputs {< 0_5 V for IT100 <
1.5 V for IT10l.

o

CHIP
TOPOGRAPHY

ABSOLUTE MAXIMUM RATINGS

5514

@25°C (unless otherwise noted)
MaximulTl Temperatures
Storage Temperature
Operating Junction Temperature
Lead Temperature (Soldering,
10 sec time limit)

5

Gte

_65° C to +200° C
+200°C

Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating
Maximum Voltages & Current
V GS Gate to Source Voltage
V GD Gate to Drain Voltage
IG
Gate Current

FULL RADIUS
(DRAIN)
0019

+300°C

.0015

300 mW
1.7 mWtC

~1~---.~~~b - - - - - 1
NOTE: SUBSTRATE IS GATE

35V
35V
50 mA

ORDERING INFORMATION
TO·18

WAFER

DICE

1T100
IT101

IT100/W
IT101/W

IT100/D
IT10l/D

ELECTRIC CHARACTERISTICS @ 25°C (unless otherwise noted)
CHARACTERISTIC
IDSS

Max' Drain Current

Vp

Pinch Off Voltage

BVGSS

Gate-Source Breakdown Voltage

IGSS

Gate Leakage Current

MIN
-10
2

IT100
MAX

-

1T101
MIN
MAX
-20

4.5

35

4

10

35
200

-8

UNIT
mA
V
V

200

-8

pA

gfs

Transconductance

gos

Output Conductance

-1

-1

ID{off)

Drain (OFF) Leakage

-100

-100

pA

rOS(on)

Drain-Source "ON" Resistance

75

60

n

Ciss

Input Capacity

35

35

pF

Crss

Reverse Transfer Capacity

12

12

pF

1-13

mmho
mmho

TEST CONDITIONS
VGS

= 0, VDS =-15 V

= 1 nA, VDS =-15 V
= 1 !lA, VDS = 0
VGS = 20 V, VDS = 0
VGS = 0, VDS =-15 V
VGS = 0, VDS =-15 V
VDS = 10 V, VGS =-15 V
VGS = O. VDS =-0.1 V
VDG =-20 V. VGS = 0
VDG =-10 V, IS = 0
ID

IG

Ji05·Ji07
N·ChanneIJFET

D~DIb

PIN
CONFIGURATION

D

TO·92
FEATURES
• Low

roS(on)

(30 MAX J1 05)

APPLICATIONS
·Analog Switches, Choppers, Commutators
S

D

G

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage ......... -25V
Gate Cu rrent. .......................... 50mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27mW/DC) ................... 360mW
Operating Temperature Range ...... -55 to 135·C
Storage Temperature Range ........ -55 to 150·C
Lead T-rmperature Range
.
(1/16"from case for 10 seconds) .......... 300·C

ORDERING INFORMATION
J105·
J106
J107

TO-92 only
. TO-92 only
TO-92 only

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25 °Cunless otherwise noted
Jl06

Jl05
PARAMETER

MIN

TYP

MAX

MIN

TYP

-3

Jl07
MAX

MIN

TYP

-3

MAX

U~IT

-3

nA

TEST CONDITIONS

S

IGSS

Gate·Reverse Current (Note 1)

T

VGS(off)

Gate-Source Cutoff Voltage

-4.5

A

BVGSS

Gate-Source Breakdown Voltage

-25

25

25

T

lOSS

Drain Saturation Current (Note 2)

500

200

100

I

10(6tt)

Drain Cutoff Current (Note 1)

3

3

3

nA

VOS;' 5V. VGS = - fOV

C

rOS(on)

Drain source ON Aesistance

3

6

8

.0

V OS50.1V, VGS _OV

Cdg(off)

Drain Gate OFF Capacitance

35

35

35

Csg(off) .

Sou ree Gate OFF Capacitance

35

35

35

Drain Gate plus Source Gate

160

160

160

0

y

-10

-6· -0.5

-2

-4.5

N

VOS =5V, 10 _1 "A
V
~mA

VOS'=OV, IG-

1 "A

VOS=15V, VGS=OV

VOS = OV. VGS = -10V

t=l MHz

pF

Cdg(on)

+

VDS =OV, VGS = -15V

VOS =VGS=OV

ON Capacitance

A
M
I
C

Csg(on)
td(on)

Turn On Delay Time

15

15

15

tr

Rise Time

20

20

20

td(ott)

Turn Off Delay Time

15

15

15

tf

Fall Time

20

20

20

-

NOTES: 1. Approximately doubles for every 10'C increase in TA.
2. Pulse test duration =300 /LS; duty cycles3%.
1-14

ns

Swjtching ·Time Test Conditions
J105 J106 JfO?
1.5V
1.5V
1.5V
VOO
VGS(Off)
-12V
-?V -5V
50!!
50!!
50!!
RL

J111·J113
N·ChanneIJFET
APPLICATIONS

PIN
CONFIGURATION

• Analog Switches
• Choppers
• Commutators

CHIP
TOPOGRAPHY

50018

TO·92

FEATURES

~

• Low Cost
• Automated Insertion Package
• Low Inse~tion Loss
rDS(on) < 30n (J111)
• .No Offset or Error Voltage Generated by Closed
Switch
.
Purely Resistive
High Isolation Resistance from Driver,
• Fast Switching
.
tD(on)
tr = 13 ns Typical
• Short Sample and Hold Aperture Time
Cgd(off) < 5 pF
Cgs(off) < 5 pF

D

S

G

,1

001)& FUll RADIUS
·OOI7S.IDRAINI
"-"'-

00II r-0072 iNOTE

SUBSTRATE IS GATE

I~I

~·I-:I

L

,~"~

I-..lli.-I
g"

OOlS

0026

ISOURCE]

+

ORDERING INFORMATION

. ABSOLUTE MAXIMUM RATINGS(@ 25°C)

-TO·92
J111

WAFER

DICE

J1111W

J112
J113

J112/W
J113/W

J111/D
J112/D
J1131D

Gate-Drain or Gate-Source Voltage ••........•...•...•.. -35V
Gate Current ......•. ; ..•••.•••....•...•.....•..••..•. 50 mA
Total Device Dissipation (TLEAO = 25°C) ••...•....... 625 mW
Power Derating (to +135°C) .••......••.•.•..•.... 5.68 mW/oC
Storage Temperature Range.•...•...••...•... -55°C to +135°C
Operating Temperature Range ..........•.... -55° C to +135° C
Lead Temperature (1/16" from case for 10 seconds) ... +300° C

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
J111
J113
J112
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
Gate Reverse Current (Note 1)
1
1
1 nA
-J.S IGSS
3
10
1
0.5
3
2 T VGS(off) Gate Source Cutoff Voltage
5
V
SA BVGSS Gate Source Breakdown Voltage 35
35
35
Drain Saturation Current (Note 2) 20
-iT loss
2
rnA
5
51 10(011)
Drain Cutoff Current (Note 1)
1
1
1 nA
30
100 n
6C rOS(on) Drain Source ON Resistance
50
5
5
5
~D Cdg(off) Drain Gate OFF Capacitance
5
5
5
8 Y Csg(olf) Source Gate OFF Capacitance
pF
9N Cdg(on) Drain Gate Plus Source Gate
28
28
28
- A Cst(on) ON Capacitance
10M \dlon)
Turn On Delay Time
7
7
7
111 tr
Rise Time
6
6
6
12C td(olf)
Turn Off Delay Time
20
20
20
ns
Fall Time
15
15
15
13
tf

..

NOTES:
1. Approximately doubles for every 1Q°C increase in TA.·
2. Pulse Test duration 300"s; duty cycle oS 3%.

1-15

Vos
Vos
Vos
Vos
Vos
Vos

-

TEST CONDITIONS
OV, VGS - -15V
5V, 10 - 1"A
OV, IG - -1"A
15V, VGS - ov
5V, VGS - -10V
0.1V, VGS - OV

VOS = OV, VGS = -10V
. f=1 MHz

Vos - VGS - 0

Switching Time Test Conditions
J111
J112 J113
10V
10V
10V
Voo
-7V
-5V
VGS(Off) -12V
800n 1,600n 3,200n
RL

I

LM114/H, LM114A'/AH
Dual NPN Monolithic
Transistor
GENERAL DESCRIPTION

FEATURES

_These devices contain a pair of junction· isolated NPN transis·
tors fabricated on a single silicon substrate. This monolithic
, structure makes possible extremely tight parameter matching
at low cost. Further, advanced processing techniques yield
exceptiona.IIY high current gains at low coil ector currents,
virtual elimination of "popcorn noise," low leakages and
improved long·term stability.
'

•
•
•
•
•
•

O

Low offset voltage - 0.5mV maximum
Low drift - 2/l V C maximum from ~55° C to +125" C
High current gain - 500 minimum at 10/lA
Tight beta match - 10% maximum
High breakdown voltage - to 60V
Matching guaranteed over a OV to 45V collector· base voltage range
CMRR> 100dB

r

•

Although designed primarily for high breakdown voltage and
exceptional DC characteristics, these transistors have surpris·
ingly good high·frequency performance. The gain·bandwidth
product is 300M Hz with 1 mA collector current and 5V col·
lector·base voltage and 22MHz with 10/lAcoliector current.
Collector·base capacitance is only"" 100pF at 5V.

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·71
TO·78

4003

:~~~ :g~;~
II

-r-;C;;;O;:;LL~EC;'T~OR~=1;:l:• •=iiitl-":'-7"-=
ISOLATION
COLLECTOR

ABSOLUTE MAXIMUM RATINGS

&nQ

:i2 TVP. 2 PLACES

:g:~ II

1

.0270

Collector· Base Voltage (BVCBO) . . . . . . . . . . '. . . . . . . 45V
Collector· Emitter Voltage (BVCER) . . . . . . . . . . . . . . . . 45V
Collector· Collector Voltage . . . . . . . . . . . . . . . . . . . . . . 45V
Emitter·Base Voltage (BVEBO) . . . . . . . . . . . . . . . . . . . 6V
Collector Current. . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Total Power Dissipation (Note 1) . . . . . . . . . . . . . . . . .0.8W
Operating Junction Temperature . . . . . . . . . . _55°C to +15d'C
Storage Temperature. ' . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10 sec) .. '.' . . . . . . . . . +300°C

ELECTRICAL CHARACTERISTICS (Note

t.

CONDITIONS

Offset Voltage

1~A '" Ic '" 1OO~

Offset Current

Ic =
Ic =

Bias Current

Ie

.0040

TVP. 2 PLACES .0030

DIAMETER

ORDERING INFORMATION
, TO·71
LM114
LM114A

,

TO·78

WAFER

10~
1~A

UNITS

0.5

2.0

mV

2.0
0.5

10

nA
nA

20

40

nA
mV

3.0

1~

DICE

LM114/W LM114/D
LM114H
LM114AH

MAXIMUM LIMITS
LM114, H
LM114A, AH

=10~

Ic =

DIAMETER

EMITTER.;r2
EMITTER =1

2)

PARAMETER

:=:

BASE =2 TVP. 2 PLACES

-l.--B-'-SE-,-,-~HL-""...J :~~

nA

Offset Voltage Change

OV '" Vee'" VMAX. Ie = '10~

0.2

1.S

Offset Current Change

OV '" Vee'" VMAX. Ic = 10~A
-55"C", TA '" + 125"C,
Ic = 10~

1.0

4.0

nA

2.0

10

IlVI"C

12

50

nA

60

1S0

nA

Offset Voltage Drift
Offset Current

-SS~C '" TA '" +12S",

Ie =

,

10~

Bias Current

-5S"C '" TA " + 12S"C,
Ic = 10~

Coliector·Base Leakage Current

Vce = VMAX
TA = +2S"C
TA = +12~"C

10
10

50

SO

pA
nA

Coliector·Emltter Leakage
CUrrent

Vce = VMAX. Vee = OV
TA = +25"C
TA = +12S"C

SO
50

200
,200

pA
nA

Coliector·Coliector Leakage
Current

Vec = VMAX
TA = +2S"C
TA= +125"C

100
100

300
300

pA
nA

Note 1: The maximum dissipation given is for a +2S" C case temperature. For operation under other conditions, the device must be derated based on a '
+150o C maximum junction ten:lperatu're and a thermal resistance of +70°C/W junction to case of +230°CIW junction to ambient.
Note 2: These specifications apply for TA = +25°C arid OV .. Vce .. VMAX, unless otherwise specified'. For the LM114 and LM114A. VMAX =
30V.
1·16

M116
Diode Protected
N-ChannelEnhancement
Mode MOS FET
GENERAL,DESCRIPTION
•
•

DEVICE
SCHEMATIC

PIN
CONFIGURATION

Low IGSS
Integrated Zener Clamp Protects the Gate

1

~:

10-72

ABSOLUTE MAXIMUM RATINGS (25°C)
Drain-to-Source Voltage
Gate-to-Drain Voltage.
Drain Currenr
Gate Zener Current
Storage Temperature
Operating Junction Temperature
Total Device Dissipation (Derate
2.25 mWfC to 125°C)

30V
30V
50 niA
±0_1 rnA
-65 to 150°C
-55 to 125°C

4

C

G

S

CHIP
TOPOGRAPHY
1003-Z

D

225mW

NOTE: SUBSTRATE
IS HODY,

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
rDS(onl .

Drain Source ON Resistance

VGS(th)
BVOSS
BVSOS
BVGBS
IS(OFF)
IGSS
Cgs or
Cgd
Cdb

Gate Threshold Voltage
Drain-Source Breakdown Voltage
Source-Drain Breakdown Voltage
Gate·Body Breakdown Voltage
Drain Cutoff Current
Source Cutoll Current
Gate-Body Leakage
Gate·Source or
Gate·Orain Capacitance
Drain-Body Capacitance

Ciss

Input Capacitance

10(QFF)

MIN

1
30
30
30

1-17

Ml16
MAX
100
200
5

UNITS

n

60
10
10
100

V
V
V
V
nA
nA
pA

2.5

pF

7

pF

10

pF

TEST- CONDITIONS
VGS - 20 V, 10 - 100 IlA, VBS - 0
VGS = 10 V, 10 = 100llA, VBS = 0
VGS = VOS, 10 = 10llA, VBS = 0
10 = 1 IlA, VGS= VBS =0
IS = 1 IlA, VGf) = VBD = 0
IG = lOIlA, VSB = VOB = 0
VOS = 20 V, VGS = VBS = a
VSO = 20 V, VGO = VBO = 0
VGS = 20 V, VOS = VBS = 0
VGB = VOB = VSB = 0, I = 1. MHz
Body Guarded
VGB - 0, VOB - 10 V, I - 1 MHz
VGB - 0, VOB - 10 V, VBS - 0
1=1 MHz

o

IT120·IT122
Dual Monolithic
NPN Transistor
FEATURES
•
•

High hFE at Low Current
Low Output Capacitance

•

IBl - IB2

PIN
CONFIGURATION

> 200 @ 10 pA
< 2.0 pf

< 2.5 nA

Tight V BE Tracking

< 3.0 pV t

TO·71
TO·78

C

ABSOLUTE MAXIMUM RATINGS (Note 1)
25° C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Power Dissipation

@

.
_65°C to +200°C
+200°C

TO·78

ONE SIDE
Total Dissipation at 25°C 0.4 Watt

Case Temperature
Derating Factor

Maxirpum
V CBO
V CEO
V EBO
VCCO
IC

2.3mWtC

CHIP
TOPOGRAPHY

TO·71

BOTH SlOES ONE SlOE BOTH SIDES
0.75 Watt

0.3 Watt

0.5 Watt

4.:pnW/oC

1.7mW/oC

4.3mWtC

Voltage & Current for Each Transistor
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector to Collector Voltage
Collector Current

4003

-f-;:;;;-;-;~;;;-;;ji:i;;;II;;::;;:i----,soLAT'ON
,0045 x ~
COLLECTOR #1
COLLECTOR
.0035 ,0035

45 V
45 V
7.0 V
60 V
50mA

.0230

#2 TYP. 2 PLACES

.0270

.0045 .0045
.0035 II .0035

1

BASE ::-2 TYP. 2 PLACES

:~~g

-'----.-AS-.-.-,-'7yL-.......- '

DIAMETER

~~~:;~~A~~S :~~~g

EMITTER #1

DIAMETER

ORDERING. INFORMATION
TO·78
)H20
IT121
IT122

WAFER

TO·71
IT120·T071
IT121·T071
IT122·T071

IT120/W
IT121/W
IT122/W

DICE
IT120/D
IT121/D
IT122/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

1T120A
MIN MAX

IT120
MIN MAX

1T121
MIN MAX

1T122
MIN MAX

UNIT

TEST CONDITIONS

hFE

DC Current Gain

200

200

80

80

hFE
hFE(-55°C)

DC Current Gain
DC Current Gain

225

225

100

100

IC = 1.0 rnA, VCE = 5.0 V

75

75

30

30

IC-l0MA, VCE -5.0V

Vol~age

IC= 10MA, VCE =5.0V

VBE(ON)

Emitter-Base On

0.7

0.7

0.7

0.7

V

I C = 10 MA, V CE = 5.0 V

VCE(SAT)

Collector Saturation Voltage

0.5

0.5

0.5

0.5

V

IC - 0.5 rnA; IB - 0.05 rnA

1.0

ICBO

Collector Cutoff Current

1.0

'1.0

1.0

nA

IE=O,VCB=45V

ICBO(+150°C)

Collector Cutoff Current

10

10.

10

10

IE - 0, VCB - 45 V

lEBO

Emitter Cutoff Current

1.0

1.0

1.0

1.0

MA
nA

COB

Output Capa«::itance

2.0

2.0

2.0

2.0

pF

IE = 0, VCB = 5.0 V

CTE

Emitter Transition Capacitance

2.5

2.5

2.5

2.5

pF

IC=O, VEB=0.5 V

CC1' C2

Collector to Collector Capacitance

4.0

4.0

4.0

4.0

pF

VCC - 0

IC1' C2
VCEOISUST)

Collector to Collector Leakage Current

10

10

10

10

nA

VCC=±60V

Collector to Emitter Sustaining Voltage

GBW

Current Gain
Bandwidth Product

IVBE1-VBE21

Base Emitter Voltage Differential

IIB1-IB21

Base Current Differential

1"(VBE1-VBE2)1

Base-Emitter Voltage Differential
Change with Temperature

45

45

45

45

V

10
220

10
220

7
180

7
180

MHz
MHz

1

2

3

5

mV

2.5

5

25

25

nA

3

5

10

20

MVtC

NOTES: (1) These ratings are limiting values above which the serviceability of any semicondUctor device may be impaired.
(2) The lowest of two '"'~~c: readings is taken as hFE1 for purp()~es of this ratio.

1·18

IC - 0, VEB - 5.0 V

IC - 1.0 rnA, I B - 0
IC -lOMA, VCE - 5V
IC= 1 rnA, VCE = 5V
IC = 10 MA, VCE = 5.0 V
IC - 10 MA, VCE = 5.0 V
TA - _55°C to +125°C
Ie = 10llA, VCE ~ 5.0 V

IT124
Super.Beta Dual
Monolithic NPN Trans.istor
FEATURES
•
•
•
•

CHIP
TOPOGRAPHY
4003

PIN
qONFIGURATION

Very High Gain - hFE 2:: 1500 @ 1 and 10JLA
Low Output Capacitance - Cabo :5 0.8 pF
Tight VBE Matching - IVBE1 - VBE2 1-2 mV TYP.
High fT - 100 MHz
.

TO·7S

.J.-:::;:.:;:;;;;~~"

ABSOLUTE MAXIMUM RATINGS (Note 1)
@ 25°C (unless otherwise noted)

:~~~~ :g~:
II

-r-;:C;;;oL7.LE;:CT;';;O;R-;;;,,~.r:;:l---"";'ISOLATION
COLLECTOR
.0230

#2 TYP. 2 PLACES

.0270

:~:~ x :~~~

1

Maximum Temperatures
Storage Temperature .............. ~5° C to +200° C
Operating Junction Temperature ............. +200°C
Le;:td Temperature (soldering, 10 second
time limit) .................................. +2S0~C
Maximum PowerDissipation·
ONE SIDE·BOTH SIDES
Device Dissipation @ Free Air 400 mW
750 mW
Linear Derating Factor ....... 2.3 mW/oC 4.3 mW/oC
Maximum Voltage and Cur~ent for Each Transistor
VCBO Collector to Base Voltage .................. 2V
VCEO Collector to Emitter Voltage ................ 2V
VEBO Emitter to Base Voltage (Note 2) ............ 7V
Vcca Collector to Collector Voltage ... ,........ 100V.
Ic
Collector Current ....................... 10mA

BASE =2 TVP. 2 PLACES

--1...----1,£--1---\--'

:~:~

DIAMETER

. BASE :Jl

EMITTER .lt1

EMITTER;=-2 .0040
TYP. 2 PLACES .0030
DIAMETER

c,

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL·

CHARACTERISTICS

MIN

'NF

DC Current Gain
DC Current Gain
DC Current Gain
Emitter-Base "ON" Voltage
Collector Saturation Voltage
Collector Cutoff Current·
Collector Cutoff Current
Emitter Cutoff Current
Output Capacitance
Emitter Transition Capacitance
Collec'tor to Collector Capacitance
Collector to Collector Leakage Current
Current Gain Bandwidth Product
. Current Gain Bandwidth Product
Narrow Band Noise Figure·

BVCBO
BVEBO
VCEo(SUST)

Collector-Base Breakdown Voltage
. Emitter-Base Breakdown Voltage
Collector-Emitter Sustaining Voltage

hFE
hFE
hFE(-55°C)
VBE(ON)
VCE(SAT)
ICBO
ICBO(+150°C)
lEBO
COBO
CTE
CC1C2
IC1C2

fr
fr

MAX

UNITS

1500
1500
SOO
0.7
0.5
100
100
100
.0.8
1.0
0.8
250
10
100
3

V
V
pA
nA
pA
pF
pF
pF
pA
MHz
MHz
dB

V
V
V

2
7
2

CONDITIONS

Ic = 1!,A, VCE = 1V
Ic - 10!,A, VCE - 1V
Ic - 10!,A, VCE - 1V
Ic - 10!,A, VCE - 1V
Ic = 1mA, IB - 0.1mA
IE - 0, VCB - 1V
IE = 0, VCB = 1V
Ic - 0, VEB - 5V
IE - 0, VCB - 1V
Ic - 0, VEB - 0.5V
Vcc =0
Vcc = ±50V
Ic - 10!,A, VCE - 1V
Ic - 100!,A, VCE - 1V
Ie - 10!,A. VCE - 3V,
f = 1 KHz, RG = 10 Kohms,
BW = 200 Hz
Ie = 10!,A, IE - 0
IE = 10!,A, Ic = 0
Ie - 1mA, IB - 0

MATCHING CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL

IVBE1-VBE21
I(VBE,-VBE2)I/o C
IIB1-IB21

CHARACTERISTICS

Base Emitter Voltage Differential
Base En:!.itter Voltag'e Differential
Change with Temperature
Base Current Differehtial

TYP

MAX

UNITS

2
5

5
15

mV
!'V/oC

.S

nA

CONDITIONS

Ie = 10!,A, VCE = 1V
Ie = 10!,A, VCE = 1V
T = -55°C to +125°C
Te - 10!,A, VCE - 1V

NOTES:
1. These ratings are limiting values above which·the serviceability of any semiconductor device-may be impaired.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter .current must never exceed 1DI'Amps.

1·19

II

IT126·IT129
Dual Monolithic NPN
Transistor
FEATURES
• High Gain at Low Current VCE = 5V

hFE

PIN
·CONFIGURATION

230 at 10mA,

2:

TO·71
TO·78

• Low Output Capacitance - Cobo :S 3 pF
Tight IB Match - IB1.2 < .25 p.A at 1 mA,
VCE
5V
Tight VBE Tracking - l:>(VBE1 - VBE2) :S 3/LV/oC
-55°C to +125°C
.

0:

=

• Dielectrlcally Isolated matched pairs for
differential amplifiers

ABSOI,..UTE MAXIMUM RATINGS
@

2SoC (unless otherwise noted)

Maximum Temp~ratures
Storage Temperature
Operating Junction Temperature

CHIP
TOPOGRAPHY
4001

-6SoC to +200°C
+200°C
T078

T071
Maximum Power Dissipation
Total Dissipation at 25°C
Case Temperature
Derating Factor

ONE SIDE

BOTH SIDES

ONE SIDE BOTH SIDES

EMITTER

~~~ It :~~~
TYP. 2 PLACES

0.3 Watt
1.7 mwfc

0)5 Watt
4.3 mwfc

0.4 Watt
2.3 mwfc

0.5 Watt
2.9 mwfc

BASE .0030 .0030
\ .0040 It .0040
TYP, 2 PLACES

COLLECTOR

EMITTER

Maximum Voltage and Current for Each Transistor
V CBO Collector to Base Voltage
VCEO

Collector to Emitter Voltage..

VEBO

Emitter to Base Voltage (Note 2)

V CCO

Collector to Collector Voltage

IC

Collector Current

IT126,7
60V

60V
7V
70V
100mA

IT128
55V

1T129
45V

.0035

BASE

TYP. 2 PLACES

45V

55V
7V

7V

70V

70V
100mA

100mA

,0034

.0045 It .0044

ORDERING
INFORMATION
I
T078

TO·71

WAFER

DICE

IT126

IT126-T071

IT127
IT128

1T127-T071
IT128-T071

IT126/W
IT127/W

IT126/D
IT127/D

IT129

IT129-T071

IT128/W
IT128/W

1T128/D

IT128/D

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
PARAMETER

IT127

1T126
MIN

MAX

MIN

800

200

IT129

1T128

MAX

MIN

800

150

UNITS

CONDITIONS

MIN

800

100

IC = 1 .0 mA, V CE = 5V

70

100

IC = 10 l'A, VCE = 5V

hFE

DC Current Gain

150

.hFE

DC Current' Gain

200

hFE

DC Current Gain

230

230

170

115

IC=10mA,VCE=5V

hFE

DC Current Gain

100

100

75

·50

IC = 50 mA, VCE = 5V

hFE(-55°C)

DC Current Gain

75

75

60

40

VBE(on)

Emitter·Base On Voltage·

VCE(sat)

Collector Saturation Voltage

150

MAX

MAX

.9

.9

1.0

1.0

.9,
1.0

IC = 1 mA, VCE = 5V

.9

V

ic = 10 mA, VCE = 5V

1.0

V

IC = 50 mA, VCE = 5V

.3

.3

.3

.3

V

IC= 10mA,IB= 1 mA

1.0

1.0

1.0

1.0

V

IC = 50 mA,lB = 5 mA

ICBO

Collector Cutoff Current

0.1

0.1

0.1

0.1

nA

IE = 0, VCB = 45V. 30V

ICBO(+150'C)

Collector Cutoff Current

0.1

0.1

0.1

0.1

I'A

IE = 0, VCB = 45V. 30V

lEBO

Emitter Cutoff Current

0.1

0.1

0.1

0.1

nA

IC = 0, VEB = 5V

Cobo

Output Capacitance

3

3

3

3

pF

IE =0; VCB = 20V

1·20

I

O~OIL

IT130·IT132.
Dual Monolithic PNP
Transistor

FEATURES

PIN
CONFIGURATIONS

• High hFE at Low Current> 200 @ 10,..A
• Low Output Capacitance < 2.0 pF
• IS1·IS2

TO·71
TO·78

< 2.5 nA

• Tight VSE Tracking

II

< 3.0,..V/oC

ABSOLUTE MAXIMUM RATINGS (Note 1)
@

25°C (unless otherwise noted)

Maximum Temperatures
Storage Temperature
Operating Junction Temperature

_65°C to +200°C
+200°C

Maximum Power Dissipation
To·78
ONE SIDE
Total Dissipation at 25°C 0.4 Watt
Case Temperature
Derating Factor
2.3mwfc

TO·71

BOTH SIDES ONE SIDE BOTH SIDES
0.75 Watt

0.3 Watt

0,5 Watt

4.3mWrC

T.7mWrC

2.9mWrC

CHIP
TOPOGRAPHY
4503

Maximum Voltage & Current for Each Transistor
VCBO' Collector to Base Voltage
VCEO Collector to Emitter Voltage
V EBO Emitter to Base Voltage
V ceo Collector to Collector Voltage
IC
Collector Current

.0045 x .0045
-I-;';;-;-;:;::;;;;;-;~~liir:-=i----ISOLATION
COLLECTOR #1
COLLECTOR
.0035 .0035

45V
45 V
7.0 V
60V
50mA

.0230

#2 TYP. 2 PLACES

:gg~~ x :~o;:

.0270

!

BASE #2 TYP. 2 PLACES

-.,-''>'-'>'---'r-'

--'----BA-S-'

:g~g

DIAMETER

i~;~J~~A~is :~~~

EMrITER #1

OIAMETER

ORDERING INFORMATION

ELECTR.ICAL CHARACTERISTICS

(25°C

TO·79

TO·71

WAFER

DICE

IT130A
IT130
IT131
IT132

1T130A·T071
IT130·T071
1T131·T071
IT132·T071

IT130A/W
IT130/W
IT131/W

IT130A/D

IT132/W

IT130/0
IT131/0
IT132/0

unless otherwise noted)

PARAMETER

1T130A
MIN MAX

1T130
MIN MAX

1T131
MIN MAX

1T132
MIN MAX

UNIT

TEST CONDITIONS

hFE

DC Current Gain

200

200

80

80

IC = 10 /lA. liCE = 5.0 V
IC = 1.0 rnA, VCE = 5.0 V

hff_

DC Current Gain

225

225

100

100

hFE(-55°CI

DC Current Gain

75

75

30

30

VBE(ONI

Emitter-Base On Voltage

VCE(SATI

Collector Saturation Voltage

0.5

0.5

0.5

ICBO
ICBO(+150°CI

Collector Cutoff Current

-1.0

-1.0

-1.0

Collector Cutoff Current

-10

-10

-10

lEBO

Emitter Cutoff Current

-1.0

-1.0

Cob
Cte

Output Capacitance

2.0

Emitter Transition Capacitance

CC1- C2
IC -C2
VCEO(SUSTI

Collector to Collector Capacitance

V

Ic = 10 /lA, VCE " 5.0 V
IC = 10/lA, VCE = 5.0 V

0.5

V

IC = 0.5 rnA, IB = 0.05 rnA

-1.0

nA

IE = 0, VCB = 45 V

-10

~A

IE = 0, VCB - 45 V

-1.0

-1.0

nA

IC = 0, VEB

2.0

2.0

210

pF

IE = 0, VCB = 5.0 V

2.5

2.5

2.5

2.5

pF

IC = 0, VEB = 0.5 V

4.0

4.0

4.0

4.0

pF

VCC-O

10

10

10

10

nA

VCC = ±60 V

0.7

Collector to Collector leakage Current

0.7

0.7

0.7

Collector to Emitter Sustaining Voltage

-45

-45

-45

-45

GBW

Current GainBandwidth Product

5
110

5
110

4
90

4
90

IVBE1-VBE21

Base Emitter Voltage Differential

IIB1-IB21

Base Current Differential

Id(VBE1-VBE211

Base·Emitter Voltage Differential
Change with Temperature

V
MHz
MHz

1

2

3

5

mV

2.5

5

25

25

nA

3

5

10

20

/lVfC

NOTES. (1) These ratings are limiting values above whIch the servIceabIlity of any semIconductor deVIce may be Impaired.
(2) The lowest of two hFE readings is taken as hFE1 for -purposes of this ratio.

1-21

=

5.0 V

---

IC - 1.0 rnA, I B = 0
IC - 10 /lA, VCE = 5 V
-IC ='1 rnA, VCE = 5 V
IC = 10 /lA, VCE = 5.0 V
IC - 10/lA, VCE - 5.0 V
TA = ~55'C to +1-25°<:
IC=IOI'A, V CE -5.oli

IT136·IT139
Dual Monolithic .PNP
Transistor
FEATURES
•

1 ..
•

PIN
CONFIGURATION

High Gain at Low Current - h FE;;' 200 @ 1mA
Low Output Capacitance - Cabo

< 3 pF

TO·71
TO·78

Tight IB Match - IB1 _ 2 < .25 f.lA@ 1 mA - 5V
Tight VBE Tracking - ~(VBE1 - VBE2) <,3 f.lV fc
-55°C to + 125°C'
Dielectrically !Ji0lated matched pairs for differential amplifiers.

ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
M<\ximum Temperatures
Storage Temperature
Operating Junction Temperature

_65°C to +200°C
+200°C

El

Maximum Power Dissipation
T071
T078
ONE SIDE BOTH SIDES ONE SIDE BOTH SIDES
Total Dissipation @ 25'C
Case Teinperature
0.3 Watt
0.5 Watt
0.4 Watt
0.75 Watt
Derating Factor
1.7mW/'C 2.9mW/'C
2.3mWI'C 4.3mWI'C

81

CHIP
TOPQGRAPHY
'~~;: Il :~~~:

EMITTER

Maximum Voltage and Current for Each Transistor
IT136,7
VCBa
Collector to Base Voltage
60V
VCEa
Collector to Emitter Voltage
60V
V EBa
Emitter.to Base Voltage
7V
Collector to Collector Voltage
70V
Vcca
100mA
9oll~ctor Current
IC

TYP. 2 PLACES

IT138
55V
55V
7V
70V
100mA

IT139
45V
45V
7V
70V
100mA

BASE .0030
.0040
COLLECTOR

EMITTER

0035

BASE

It

,0030
,0040

TYP,2 PLACES

.0034

0'045)( .0044
TYP, 2 PLACES

4501

ORDERING INFORMATION

1-22

,TO·78

TO·71

WAFER

DICE

IT136

IT136-T071

IT136/W

IT136/D

IT137

IT137-T071

IT137/W

IT137/D

IT138

IT138-T071

IT138/W.

IT138/D

IT139

IT139-T071

IT139/W

IT139/D

IT136 - IT139

D~OIL

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
1T136
PARAMETER

MIN

1T137

MAX

MIN

IT139

IT138

MAX

MIN

MAX

MIN
70

100

150

U"!ITS

MAX

CONQITIONS

hFE

DC Current Gain

150

hFE

DC Current Gain

150

800

150

hFE

DC Current Gain

125

230

125

80

50

IC = 10 rnA, VCE = 5V

hFE

DC Current Gain

65

60

40

25

IC = 50 rnA, VCE = 5V

hFE(-55°C)

DC Current Gain

75

75

60

40

VBE(on)

Emitter - Base On V,)ltage

800

100

IC = lallA, VCE = 5V

70

800

800

IC = 1.0 rnA, VCE = 5V

IC = 1 rnA, VCE = 5V

.9

.9

.9

.9

V

1.0

1.0

1.0

1.0

V

IC = 50 rnA, VCE = 5V

.3

.3

.3

.. 3

V

IC=l mAIB=.l rnA

IC=10mA,VCE=5V

VCE(sat)

Collector Saturation Voltage

.6

.6

.6

V

IC= 10mA,IB= 1 rnA

ICBO

Collector Cutoff Current

0.1

0.1

0.1

0.1

nA

IE = 0, VCB = 45V, 30V

ICBO(+150oC)

Collector Cutoff Current

).1

0.1

0.1

0.1

IIA

IE = 0, VCB = 45V, 30V

lEBO

Emitter Cutoff Cu;rem

0.1

0.1

0.1

0.1

nA

IC = 0, VEB = 5V

Cabo

Output Capacitance

3

3

3

3

pF

IE = 0, VCB = 20V

.6.

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

PARAMETERS
BVC t C2

Collector to Collector Breakdown
Voltage

VCEO(sust)

Collector to Emitter Sustaining
V~ltage

BVCBO

Collector Base Breakdown Voltage

BVEBO

Emitter Base Breakdown Voltage

IT136
MIN

IT138

1T137

MAX

MIN . MAX

MIN

MAX

IT139
MIN

MAX

UNITS

CONDITIONS

100

100

100

100

V

IC =±lI1A

60

60

55

45

V

Ie = 1 rnA, IB = a

60

60

55

45

V

IC = 10 IIA, IE = a

7

7

7

7

V

IE= lO IlA,le=O

MATCHING CHARACTERISTICS @25°C (unless otherwise noted)

PARAMETERS
IVeE t - VeE 2 '
1il.(VBE t - VBE 2 )lfC

1T136
MIN

MAX

1T138

"11137
MIN

MAX

MIN

MAX

1T139
MIN

MAX

UNITS

'. Base Emitter Voltage Differential

1

2

3

5

mV

IC = 1 rna, VCE = 5V

Base Emitter Voltage Diffe"rential

3

5

10

20

IIvte

Ie = 1 rnA, VCE = 5V

2.5

5

10

20

nA

IC = lallA, VCE = 5V

.25

.5

1.0

2.0

IIA

IC = 1 rnA, VCE = 5V

TA = _55°C to +125°C

Change with Temperature
.IB, - IB2'

CONDITIONS

Base Current Differential

1·23

II

IT140
Dual Matched NPN
Transistor
FEATURES
• Excellent Conformance
• Tight VBE Match < 1.0mV

D

• Tight VBE'Tracking

PIN
CONFIGURATION
TO·71

< 3.0 p.V/oC

ABSOLUTE ",AXIMUM RATINGS (Noto 1)

. @ 25·C (unless otherwise noted)

Maximum Temperature.s
Storage Temperature
Operating Junction Temperature
Maximum Power Dissipation

-65·Cto +200·C
+200·C

TO·71
ONE SIDE
BOTH SIDES

CHIP
TOPOGRAPHY

Total Dissipation at 25.·C
0.5 Watt
Case Temperature
0.3 Watt
Derating Factor
1.7mW/·C
4.3mW/·C
Maximum Voltage & Current for Each Transistor
VCBO Collector to Base Voltage
20V
20V
VCEO Collector to Emitter Voltage
.7.0V
VEBO Emitter to Base Voltage
45V
VCCO Collector to Collector,Voltage
Ic'
Collector Current
.
50mA

4003S

-r-;;C; ;OL:;:;LE;; CT;; O; R-;;:=,;:!:iiI'r=-i----ISOLATION
.0045 .0045
. COLLECTOR
.0035 .0035
x

.0230

::2 TYP. 2 PLACES

.0270

:~~;~ II :~~~

J_

\

BASE =2 TYP. 2 PLACES

-L--BA-SE-_--,-yLf-:-"r-J

:~::

DIAMETER

~~~~~~~A~~S :=~

EMITTER =1

DIAMETER

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
DC Current Gain
hFE
DC Current Gain
hFE
DC Current Gain
hFE
hFE( -55·C)
DC Current Gain
VBE(ON)
Emitter·Base On Voltage
VeE (SAT)
Collector Saturatiori Voltage
Collector Cutoff Current
leBO
leBO( + 150·C) Collector Cutoff Current
Emitter Cutoff Current
lEBO
Output Capacitance
COB
Emitter Transition Capacitance
CTE
Collector to Collector Capacitance
Cel. e2
Gollectqr to Collector Leakage Current
le1' e2
Collector to Emitter Sustaining Voltage
VeEo(SlJST)
Current Gain
Bandwidth .Product
fT'
VBE1-VBE2
IB1-IB2

Base Emitter Voltage Differential
Base Current Differential
Base-Emitter Voltage Differential

~(VBE1-VB2)

Change with Temperature

hFE1- hFE2

MIN
200
100 .
250
30

0.7 '
0.3
200
1.0
400
2.0
2.5
4.0
10

UNIT

V
V
nA
f.'A
nA
pF
pF

2.5

pF
riA
V
MHz
MHz
mV
nA

3

f.'V/·C

20
400
. 1

Current Gain Match

5%

Emitter Resistance

1.5

hFE2
re

MAX

TEST CONDITIONS
= 10mA, VeE = 5V
- 10p.A, VCE - 5.0V
= 1.0mA; VCE = 5.0V
= 10f.'A, VeE = 5.0V
- 10p.A, VCE - S.OV
- O.SmA, IB - O.OSmA
= 0, VeB = 45V
- 0, VeB = 45V
= 0, VEB = 5.0V
= 0, VeB = 5.0V
= 0, VEB.= 0.5V

Vee
Vec
Ic Ic =
IC =
Ie =

=. 0
= ±60V
1.0mA, IB - 0
10f.'A, VeE = 5V
1mA, VeE = 5V
10f.'A, VeE = 5.0V

Ie == 10f.'A, VeE = 5.0V
TA = -55·C!0 +125·C
Ie = 10f.'A, VeE = 5.0V
Ie = 10f.'A, VeE = 5V I

{}

NOTES. (1) These ratings are limiting values above which the serviceability of anY,semlconductor device may be impaired.
(2) The lowest of two hFE ~eadlngs is taken as hFE1 for purposes of this ratio.

1-24

Ic
Ic
Ic
Ie
Ie
Ie
IE
IE
Ic
IE
Ie

Ie = 100f.'A to 1mA., VeE - 5V

3N181
Diode ProtectedP·Channel
Enhancement Mode MOS FET
GENERAL DESCRIPTION

PIN
CONFIGURATION

DIODE·PROTECTED ENHANCEMENT·TYPE
MET AL·OXI DE·SEM ICONDUCTOR TRANSISTOR

10-72

For applications requiring very high input impedance, such
as series and shunt choppers, multiplexers, and commutators.

II

FEATURES
• Channel Cut Off with Zero Gate Voltage
• Square-Law Transfer Characteristic Reduces' Distortion
•

Independent Substrate Connection Provides Flexibility
in Biasing

•

Internally Connected Diode Protects Gate from Damage
due to Overvoltage
.

C

G S

0

CHIP
TOPOGRAPHY

1503·Z

(2 per package)

DESCRIPTION
These devices are designed for applications requiring very
high input impedance, such as choppers, commutators, and
logic switches. Each device is protected from excessive
input voltage bya shunting diode connected from the gate
to the substrate. This eliminates the need" for most precautionary handling procedures associated with unprotected
MaS devices.
NOTE

SUBSTRATE
tSBODY

ORDERING INFORMATION
TO·72

WAFER

DICE

3N161

3N1611W

3N161/D

ELECTRICAL CHARACTERISTICS (25°C free-air temperature unless otherwise noted)
PARAMETER
IGSSF

Forward Gate-Terminal Current

BVGSS

Forward Gate-Source Breakdown Voltage

lOSS

Zero-Gate-Voltage Orain Current

VGS(th)
VGS

Gate-Source Threshold Voltage
Gate-So,urce Voltage

IO(on)

On·State Drain Current

IYfsl
IYosl
Ciss
. Crss

Small-Signal Common·Source
Forward Transfer Admittance
Small-Signal Common·Source
Output Admittance

MIN

TYP

MAX
-0.1
-1

-25
-10
-10

UNIT
nA
nA

VGS = -25 V, VDS = 0
VGS - -25 V;VOS - 0,

V

IG -0.1 rnA, VOS = 0,

nA
I1A

VDS=-15V,VGS=0
VDS = -25 V, VGS = 0

-1.5

-5

V

-4.5
-40

-8

V

-120

rnA

3500

6500

I1mho

250

I1mho

10

pF

4

pF

TEST CONDITIONS
TA - 100 C

VOS = -15 V, 10 = 10 I1A

VOS=-15V,lo=-8mA
VDS = -15 V, VGS = -15 V

f = 1 kHz
VOS=-15V,lo=-8mA

Common-Source Short-Circuit
Input Capacitance
Common·Source Short-Circuit
Reverse Transfer Capacitance

f =1 MHz

1-25

3N163,3N164

O~UIb

P-Channel Enhancement
Mode MOS'FET

FEATURES

D

•

Very High Input Impedance

•

High Gate Breakdown

•

Fast Svyitching

•

Low Capacitance

PIN
CONFIGURATION

(@

25°C

3N163

±30V
±125V

-40V
-40V
-40V

-30V
-30V
-30V

ID

Drain to Source Voltage
Source to Drain Voltage
Drain to Gille Voltage
Drain Current

Po

Power 0 issipation

VDSS
V SDS

V oGa

Derating Factor

Operating Junction Temperature
. Storage Temperature
Lead Temperature 1/16" from
Case for 10 sec max

TJ
T sto

Tc

---~_I

,3N164

i40V
±125V

V GSS (l)

1----- ~

~mbient unless noted)

Static Gate to Source Voltage
Transmit Gate to Source Voltage

V GSS

1503·Z

TO·72

MAXIMUM RATINGS

CHIP
TOPOGRAPHY

-50 rnA -50 rnA
375mW
3.0mWtC
-55 to + 150°C

-65

to

c

NOTE: SUBSTRATE
IS BODY

o

G

ORDERING INFORMATION
WAFER
TO·72
DICE

+200°C'

+265°C

3N163
3N164

(11Cevlces must nOt be tested at '125V more than once or for
longer In an 300 ms

3N163/D
3N164/D

3N163/W

3N164/W

NOTE: See handling precautions on 3N170 data sheet.

ELE.CTRICAL CHARACTER ISTICS

(@ 25°C and V BS ~ 0 unless noted)
3N164

3N163
MIN

MAX

MIN

MAX

UNITS

Gate Reverse Leakage Current

pA

Gate Forward Current

pA

Gate Forward Current@ 125"C

TEST CONDITIONS

pA

BVI?SS

Drain-Source Breakdown Voltage

-40

. -30

v

10'" -lO,uA, V GS ::- 0

BV SDS

Source Drain Breakdown Voltage

-40

-30

v

IS

VGS(thl

:=

-lO.uA, V GO '" 0, V aB

-2.0

-5.0

v

-5.0

-2.0

-5.0

v

Vas

-6.5

-3.0

-6.5

v

Vas - - 15V, 10

pA

Vos - -15V, V GS - 0

Threshold Voltag~

-2.0

-5.0

Threshold Voltage

-2.0

Gate Source Voltage

-3.0

'oss

Zero Gate Voltage Drain Current

200

400

=:

Isos

Source Drain Current

400

800

pA

VSD

~

15V, V GS

Drain-Source on Resistance

250

300

ohms

V GS

=:

-20V,

'.D(onl

On Drain Current

-5.0
@

1 kHz

2000

-30.0
,4000

-3.0
1000 ,

250

-30.0

0

=

-15V, 10";0 -10pA

r ds(on}

Forward Transcondu"ctance

:=

:=

'"

'0""

0.5 mA

'Vos "" 0
-10DpA

Vas:= -15V, V GS - -lOV

mA

4000

/-lmhos

Vas

250

prnhos

Vos=-15V,ID=-10mA

=

-15V, 10:= -10 mA

Yos

Output Admittance@ 1 kHz

C,~

Input Capacitance - Output Shorted

2.5

. 2.5

pF

Vos

=

-15V, 10'" -lOrnA, f

Reverse Transfer Capacitance

0.7

0.7

pF

Vos

=

-15V, 10

Output Capacitance Input Shorted

3.0

3.0

pF

Vas'" :"'5V, 10 '" -10 mA, f '" 1 MHz

SWITCHING CHARACTERISTICS
t,

(@

=

25°C and V BS ~ 0)

Turn-On Delay Time

12

12

V OD

Rise Time

24

24

IOlonl = 10 rnA

Turn-Off Time

50

50

SWITCHING TIME CIRCUIT

=-

-15V

SWITCHING WAVEFORM

v ..
10",

10·',

90".

1·26

1 MHz

-lOrnA, f =- 1 MHz

3N165,3N166
Dual P-Channel
Enhancement Mode
MOS FET

FEATURES
•

Very High Input Impedance'

•

High Gate Breakdown

•

Low Capacitance

PIN
CONFIGURATION

1)
T stg

TL

_

'--'W'--' II

c
C

G,

~.K

8

4

, CHIP
2506C TOPOGRAPHY

t·

0290
.0330

~

Ij:::'§..ooo·

.0025
0035

0,

G,

t

J

0

±40V
Static Gate to Source Voltage.
Transient Gate to Source Voltage
±125V
Drain to Source V'oltage
-40V
Source to Drain Voltage
-40V
Gate to Gate
±80V
Anv Lead to Case
±40V
Drain Current
50mA
Power Dissipation (each side)
300mW
(both sides)
525 mW
Total Derating Factor
4.2 mWtC
Operating Junction Temperature '-55 to +150°C
Storage Temperature
-65 to +200°C
Lead Temperature' 1/16" from
+300°C
Case for 10 sec max

7

I

TO·99

MAXIMUM RATINGS (@ 25°C ambient unless noted)
VGSS
VGSS1'I
Voss
VGOS
VGG
VG
10
Po

DEVICE
SCHEMATIC

.

NOTE'
SUBS! RA TE

.

Sio

~

GATE 2

GATE'

2

SID 2

s/O

~

1

mo

___
SOl

.

t

.0190

I

BODY

JN190/3N191 ONl y

ORDERING INFORMATION
TO·99
3N165
3N166

(1 )Devices must not be tested at ± 125V more than once or for
longer than 300 ms.

WAFER
3N165/W
3N166/W

DICE
3N165/D
3N1661D

NOTE: See handling precautions on 3N170 data sheet.

ELECTRICAL CHARACTERISTICS (@ 25°C and VBS = 0 unless noted)
MIN ,MAX UNITS
10
-10
-25
-200
-400
-30
-5
-5
300
3000
300
3.0
0.7
3.0
1200

pA
pA
pA
pA
pA
.mA
V
V
ohms
ILmhos
I'mhos
pF
pF
pF
I'mhos

MIN

MAX

UNITS

0.90

1.0
100

mV

b.VGS1.2 Gate Source Threshold Voltage
Differential Change with Temperature

8

mV

b.VGSl-2 Gate-Source Threshold Voltage
Differential Change with Temperature

10

mV

Gate Reverse Leakage Current
IGSS
Gate Forward Leakage Current
IG(I)
Gate Forward Leakage Current ( + 125:C)
IG(I)
Drain to Source Leakage Current
IDSS
Source to Drain Leakage Current
ISDS
On Drain Current
ID(on)
VGS(th) Gate Source Threshold Voltage
VGS(th) . Gate Source Threshold Voltage
Drain Source On Resistance
rls(on)
Forward Transconductance
9ls
Output Admittance
gas
Input Capacitance
Ciss
Crss
Reverse Transfer Capacitance
Output Capacitance Input Shorted
Coss
RE(YIs) Real Part Forward Transconductance

MATCHING CHARACTERISTICS

-5
-2
-2
1500

TEST CONDITIONS

= 40V
= -40V
= -40V

VGS
VGS
VGS
VDS
VSD
VDS
VDS
VDS
VGS
VDS
VDS
VDS
VDS
VDS
VDS

=
=

VDS
VDS

= -15V, ID = -1500!LA, f = 1KHz
= -15V, ID = -5OOILA

-

-20V

= -20, VDB = 0
= -15V, VGS = -10V
- -15V, ID
- VGS, ID 20V, ID
- -15V, ID
- -15V, ID
-15V,ID
- -15V, ID
-15V,lo
-15V, 10

=-

=

-

-lOILA
- lOILA
- -lOOILA
- -lOrnA, f - 1kHz
- -lOrnA, f - 1kHz
-10mA,f
lMHz
- -lOrnA, f - lMHz
-10mA,f
lMHz
-lOrnA; f 100M Hz

=

=

=
=

=
=

3N165

YIS1 /YIs2 Forward Transconductance Ratio
VGSl-2 Gate-Source Threshold Voltage
Differential

1-27

TEST CONDITIONS

= -' 15V, ID = - 500!LA
= - 55°C to + 25 °C
VOS = -15V, ID = - 500ILA
T = +25'C to +125°C
VDS
T

3N170,3N171
N·ChannelEnhancement
Mode MOS FET
FEATURES

II

PIN
CONFIGURATION

• Low Switching Voltages-VGS(th) " 3.0 V
• Fast Switching Times-t, " 10 ns
• Low Drain-Source Resistance rds(on) = 200{J
(Max)

10-72

• Low Reverse Transfer Capacitance Crss = 1.3pF
(Max)

ft- Ml
J

3. Do not insert or remove devices from circuits with
the power on as transient voltages may cause permanant damage to the devices.

~

.0025 X ,Q9~

VALUE
25
±35
±35
30
300

SYMBOL

c

25'C

VDS
VDG
VGS
ID
PD

UNIT

1.7

Power Dissipation@Te """' 2SoC
Derate above 25° C
Operating Junction Temperature

PD

Storage Temperature Range

T5t9

TJ

800
4.56
175
--65 to +200

V
V'
V
mA
mW
mWi'C
mW
mWi'C

'c

'c

ORDERING INFORMATION
TO·72

CHIP
TOPOGRAPHY

1. To avoid the build-up of static charge, the leads of
the devices should remain shorted together with a
metal ring except when being tested or used.
2. Avoid unnecessary handling. Pick up devices by
the case Instead of the leads.

G C

RATING
Drain-Sou.rce Vo1tage
Drain-Gate Voltage
Gate-Source Voltage
Drain Current
Power Dissipation @ TA

Derate above 2S"C

HANDLING PRECAUTIONS
MOS field-effect transistors have extremely high input resistance. They can be damaged by the accumulation of excess static charge. Avoid possible
damage to the device while wiring, testing, or in actual operation, by following the procedures outlined
below:

MAXIMUM RATiNGS (TA = 25'C unless oth"w;se noted)

WAFER
3N170/w
3N170/w

3N170
3N171

DICE
3N170/0
3N170/0

.1g2.Q

.OO~OOT~"'OO~ :':~"
'0035
l
:gg!g
.0140
.ot80

xgg~~

.

S

X .0039

".:';:"

D .0030 X .0028
.0040 .0038

ELECTRICAL CHARACTERISTICS (25·C unless otherwise noted)
PARAMETER

MIN

MAX

UNITS

Substrate connected to source
rEST CONDITIONS

OFF CHARACTERISTICS
V(BR)DSS
IGSS
lOSS

Drain-Source Breakdown Voltage

25

V
10

Gate Leakage Current

100

pA

10= 10pA, VGS=O
VGS = -'35 V, VDS =,0
VGS; -35 V, Vbs= 0, TA = 125°C

10

nA

VOS = 10 V, VGS =0

1.0

pA

VDS=10V,VGS;O,TA=125°C

1.0

2.0

V

VOS= 10 V,ID = 10pA

1.5

3.0
mA

VGS = 10 V, VDS = 10 V

2,0

V

ID=10mA,VGs=10V

200

0

VGS = 10 V, ID ; 0, f = 1.0 kHz

Zero-Gate-Voltage Drain Current

ON CHARACTERISTICS
VGS(th)
ID(on)

Gate-Source Threshold Voltage
"ON" Drain Current

10

Drain-Source "ON" Voltage
VDS(on)
SMALL SIGNAL CHARACTERISTICS
rds(on)

Drain-Source Resistance

IYfs I

Forward Transfer

Admittan~e

·1000

3N170
3N171

pmhos

VDS= 10 V, ID.; 2.0 mA,
f = 1.0 kHz

Crss

Reverse Transfer Capacitance

1.3

pF

VDS = 0, VGS = 0, f = 1.0 MHz

Cis;;

Input Capacitance

5_0

pF

VDS= 10 V, VGS =0, f = 1.0 MHz

5.0

pF

VD(SUB) ; 10 V, f = 1.0 MHz

Drain-Substrate Capacitance
Cd(sub)
SWITCHING CHARACTERISTICS
td(on)

Turn-On Delay Time

3.0

ns

tr

Rise Time

10

ns

td(off)

Turn-Off Delay Time

. 3.0

ns

tf

Fall Time

15

ns

1-28

VOD = 10 V, ID(on) '" 10 mA,
VGS(on) = 10 V, VGS(off) ; 0,
RG = 50 0

3N172,3N173
Diode Protected
P-Channel Enhancement
Mode MOS FET

FEATURES
•

High Input Impedance

•

Diode Protected Gate

DEVICE

PIN
CONFIGURATION

SCH~MATIC

II

TO·72

MAXIMUM RATINGS (@ 25°C ambient unless noted)

VGSS
Voss
Vsos
VoGa
10

IGIII
IGlrl
Po
TJ
Tstg

h

Gate to Source Voltage
Drain to Source Voltage
Source to Drain Voltage
Drain to Gate Voltage
Drain' Current
Gate Forward Current
Gate Reverse Current
Power Dissipation
Derating Factor
Operating Junction Temperature
Storage Temperature
Lead Temperature 1/16" from
Case for 10 sec max

tp::

3Nl72
3N173
-40V
-30V
-40V
-30V
-40V
-30V
-'-40V
-30V
-50mA -50 rnA
10llA
10llA
1.0mA 1.0 rnA
375mW
3.0mWfC
-55 to +150°C
-65 to +200°C
+256°C

4

CHIP
TOPOGRAPHY

1503 Z

~X0029

.0035

.0039

NOTE: SUBSTRATE

, IS BODY,

ORDERING INFORMATION
, DICE
WAFER
TO·72
3N172
3N173

3N172/W
3N173/W

3N172/D
3N173/D

ELECTRICAL CHARACTERISTICS (@ 25°C and V BS ; 0 unless noted)
3N173

3Nl72

PARAMETER
MIN

UNITS

MAX

MIN

-SOO

-200

TEST CONDITIONS

MAX
pA

VGS = -20V

IlA

VGS = -20V

IGSS

Gate Reverse Current

IGSS

Gate Reverse Current (+ 12SoC)

BVGSS

Gate Breakdown Voltage

-40

,BVoss

Drain·Source Breakdown Voltage

-40

BVsos

Source-Drain Breakdown Voltage

-40

VGSI"'I

Threshold Voltage

-2.0

-S.O

-2.0

-S.O

V

V~s = VGs. 10 = -101lA

VGSI ""

Threshold Voltage

-2.0

-S.O

-2.0

-S.O

V

Vos = -lSV. 10 = -101lA

VGS

Gate Source Voltage

-3.0

-6.S

-2.S

V

Vos = -lSV. 10 = -soo IlA

loss

Zero Gate Voltage Drain Current

-0.4

-10

nA

Vos = -lSV

150S

Zero Gate Voltage Source Current

-0.4

-10

nA

Vso = -lSV. Voa ='0.'

rds(on)

Drain Source On Resistance

3S0

ohms

10lthi

On Drain Current

-30

rnA

-1,0

-0,5
-12S

-30
-30

-30

1"-29

-5.0

'V

lo=-10IlA

V

,10 = ~101lA

V

-30

2S0
-S.O

-12S

-6.S

Is '= -10IlA. Voa = 0

VGS = -20V. 10 = -100 IlA
' VDs = -lSV. VGS = -10V

J174.J177
P·Channel' JFET

;.

APPLICATIONS

II

PIN
CONFIGURATION

• Analog Switches
• Choppers
• Commutators"

CHIP
TOPOGRAPHY
55088

TO·92

FEATURES
• Low Insertion Loss
r ds (on)< 85Il (J174)
• No Offset or Error.Voltages Generated by Closed
Switch,
.
'.
,
Purely Resistive
.
High Isolation Res.istance from Driver
• Short Sample and Hold Ap,rture Time
Csg(off) < 5.5 pF
Cdg(off) < 5:5, pF
• Fast Switching
.
.'
td(o~) + t~ = 7 ns Typical

NOTE. SUBSTRATE IS GATE

D

G

S

ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

(~5°C)

Gate-Drain or G~te-Source Voltage (Note 1) ....•.............•...........•. 30V
:Gate Curr~rit' ............................................................ 50 mA
Total.Device Dissipation (25°C Free-Air Temperature) .•.......•..•.•... 350 mW
Power Derating (to +125° C) .,...................................... 3.5 mW/O C
Storage Temperature Range ................. : .................... -55 to +125°C
Operating Temperature Range ................................... -55 to +125°C
Lead Temperature (1/16" from case for ~O seconds) ...•..••........•..... 300°C

ELECTRICAL CHARACTERISTICS,

TEST CONDITioNS: 25~ C unless6therWi~e noted
J174
1

~
S
CsT
T
'4A
f-;;T
5 I
C

'"6
7

fa

J175

J176

J177

PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
TEST CONDITIONS
Gate Reverse Current
1
1
1
1
nA VOS - O. VGS - 20V
IGSS
(NQte2)
4
5
0.8
2.25
10
3
6
1
Vos --15V.10--10nA
YGS(off) Gate-Source Cutoff
Voltage
V
30
30
Vos - 0, IG - 1/LA
BVGSS Gate-Source Breakdown .30
30
Voltage
Saturation Drai~ Current 20
100
7
--£0
2
25 1.5
20 rnA Vos - . 15V. VGS- 0
loss
(Note 3) .
Drain
Cutoff
Current
-1
-1
-1
-1
10(off)
nA VOS - -15V. VGS - 10V
(Note 2)
(I
125
250
rOS(on) Drain-Source ON
85
300
VGS - 0, Vos - - 5000 J.lmho from de to 100 MHz

•

Matched V GS' gfs and gos

D

CHIP
TOPOGRAPHY

PIN
CONFIGURATION

6022

TO·99

L

@ 25°C (unless otherwise noted)

.0220
'0260

---.J

-I

~

G .0037
1 .0027

-.-----:-

ABSOLUTE MAXIMUM RATINGS

I

,0190
,0230

.

°2
G2

0

.0027

.0037 .0031
I .0027 x .0027

~

Gate-Drain or Gate-Source Voltage
-25 V
Gate Current
50mA
Device Dissipation (Each Side), T A = 85°C
(Derate 3.85 mWfC)
250mW
Total Device Dissipation, T A = 85°C
(Derate 7.7 mWfCI
500mW
Storage Temperature Range
_65°C to +150o C

.0031

JC

ITVP. 2 PLACES)

',-

(TVP. 2 PLACES)

51

:~~~; x :~~~~
(TYP. 2 PLACES)

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (2SoC unless otherwise noted)
MIN

PARAMETER
IGSS

Gate Reverse Current

BVGSS
VGS(off)
lOSS
9fs
9fs
gos
90ss
Ciss
Crss

Gate·Source Breakdown Voltage
Gate·Source Cutoff Voltage
SaturatiOn Orain Current (Note 1)
Common·Source Forward Transconductance
Common-Source Forward Transconductance
Common·Source Output Conductance
Common·Source Output Conductance
Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance

e;;
10SSl
IOSS2
IVGS1-VGS21

2hl

9fs2
Igosl-gos21

-25
-1
5
5000
5000

Equivalent Input. Noise Voltage

MAX
-100
-250
-5
40
10,000
10,000
150
150
5
1.2
30

UNIT
pA
nA
V
rnA
}lmho

pF

TEST CONDITIONS
VGS~15V,VDS=0

IG

~

-1 }lA, VOS

~

150°C

0

VOs~10V,io~lnA

VOS-l0V,VGS-0
VOS-l0V,10-5mA
VOG~10V,10~5mA

VOS

~

10 V,IO

~

5 rnA

VOG~10V,10~5mA

nV

f - 1 kHz
f~ 100 MHz
f = 1 kHz
f-l00MHz
f = 1 MHz
f ~ 10 kHz

JH7"

~

Orain Current Ratio at Zero Gate Voltage (Note 1)

0.85

Oifferential Gate-Source Voltage
Transconductance Ratio

0.85

Oifferential Output Conductance

NOTE:
1. Pulse test required, pulse width = 300 J1s, duty cycle

1-36

mV

1
20

< 30%.

VOS~10V.VGS~0

1
100

VOG = 10 V, 10 = 5 rnA
/1 mho

f

~

1 kHz

U304·U306

P·ChanneIJFET
APPLICATIONS

PIN
CONFIGURATION

• Analog Switches
• Commutators
• Choppers

TO·18

Q

1-rt

FEATURES
• ON Resistance <85 ohms ( U304)
• ID(off) <500 pA
• Switches directly from T2L Logic (U306)

~
D

ABSOLUTE MAXIMUM RATINGS (25°C)

D

s

G,C

,

CHIP
TOPOGRAPHY

Reverse Gate-Drain or Gate-Source Voltage (Note 1) ... 30V
Gate Current ...................... :.............. SO mA
Total Device Dissipation, Free-Air
(Derate 2.8 mW/· C) ............................ 3S0 mW
Storage Temperature Range ....••.......•. --£S to +1S0·C
Lead Temperature
(1/1S" from case for SO seconds) •..•...•......... 300·C

-

55088

.019(.483)

--

'II
.0231.5841

-

s.ggl~

. '~.

.018(.451)

:~~::~~:I D'.
x

0031(0939)

.oo27f0685/

x

;:,,::;

-

,

.

NOTE' SUBSTRATE IS GATE

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS

10·18

WAFER

DICE

U304
U30S
U30S

U304/W
U30S/W
U30S/W

U304/D
U30SJD
U306/D

TEST CONDITIONS: 2S· C unless otherwise noted.
Characteristic

,..l

lass

~
~
4

U304
Min Max
500

U305
Min Max
500

1.0

1.0

Gate-Source Breakdown Voltaae
Gate-Source Cutoff Voltage

VOS(on)

Drain-Source ON Voltage

loss

.Saturation Drain Current (Note 2)

10(011)

Drain Cutoff Current

ros(on)
rds(on)
Cis.

Static Drain-Source ON Resistance
Drain-Source ON Resistance Common-Source Input Capacitance

-1.0
85
85
27

-1.0
110
110
27

12

C rss

Common-Source Reverse Transfer
Capacitance

7

7

13 S

id(on)

Turn-ON Delay Time

20

25

~
~
16

t,
idioll)
tl

Rise Time
Turn-OFF Delay Time
Fall Time

15
10
25

25
15
40

rsf7
r-

~
9
10

!:;to
I-y

I
T
C
H

30
5

10

30
3

6

1.0
30
1

150·C

/J A
la - 1 /JA, Vos - 0
Vos - -15V, 10 - -1/JA

4
V

N

f-- W

Test Conditions
Vas = 20V, Vos = 0

Gate Reverse Current

BVass
Vas(oll)

I-S
T
5 A
T
I
C

U306
Min Max Unit
500 pA

-1.3
-30

-90
-500

-0.8
-15

-60
-500

Vas = 0, 10 = -15mA(U30.4),
10 = -7mA (U305),
10 = -3mA (U306)
-25 rnA Vos - -15V, Vas - 0
-500 oA Vos = -15V, Vas = 12V (U304),
Vas = 7V (U305),
-1.0 /JA Vas = 5V (U306)
f150°C
Vas - OV, 10 - ':'1 rnA
175
0
f - l kHz
175
0
Vas - OV, 10 - 0
27
Vos - 15V, Vas -.0
I vos 'o,vas T2V1U304J 1=1 MHz
pF
Vas = 7V (U305),
7
Vas = 5V (U306)
U304
U305
U306
25
-10V
-6V
-6V
Voo
7V
5V
35
Vas(oll) 12V
7430
18000
20
5800
IRL
0
0
60
Vas(on) 0
-15mA -7mA -3mA
10(on)
-0.6

-5

NOTES:
1. Due to symmetrical geometry these units may be operated with source and drain leads interchanged.
2. Pulse test pulsewidth = 300/Js, duty cycle ::;3%.

1·37

U~UIb

J308~J310

N·Channel Silicon J;FET
APPLICATIONS

PIN
CONFIGURATION

• VHF/UHF Amplifiers
• Oscillators
• Mixers

CHIP
TOPOGRAPHY

TO·92

g:

FEATURES

Industry Standard Part In Low Cost Plastic Package
High Power G.ain
11 dB Typical at 450 MHz
Common-Gate
.
• Low Noise - 2.7 dB Typical at 450 MHz
• Wide Dynamic Range Greater than 100 dB
• Easily Matches to 75 n Input

5021

D

G

NOTE' SUBSTRATE
IS GATE

S

ABSOLUTE MAXIMUM RATINGS (25°C)
ORDERING INFORMATION

Drain-Gate Voltage ................................. 25V
Source-Gate Voltage ................................ 25V
Forward Gate Current ............................ 10 mA
Total Device Dissipation (TLEAD = 25°C) ........ 625 mW
Derate above 25°C .......•................ 5.68 mW/oC
Storage Temperature Range ............... -55 to +150°C
Operating Junction Temperature Range .... -55 to +135°C

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS· 25°C unless otherwise noted
J308
1

'2s

PARAMETERS
BVGSS Gate-Source Breakdown
Voltage
Gate Reverse .Current
IGSS

'3"T
f---4A VGSlolf)
T
'5"1 loss
r.,-C
6
VGSII)
7

gb

f-s

gos

0
9 Y gig
N
WA gog
M
111 Cgd
C
12 Cgs

13

en

14

RelVfsl

15

RelVlgl

'16H
I

Re(ViS)

r,y

Re(vos)

F
'16R Gpg
E
NF
Gpg

r,g-O
C20
~

NF

Gate-SQurce Cutotl
Voltage
Saturation Drain
Current INote 11
Gate-Source Forward
Voltage
Common-Source Forward
Transconductance
Common-Source
Output Conductance
Common-Gate Forward
Transconductance
Common Gate-Clutput
Conductance
Gate-Drain
Capacitance
Gate-Source
Capacitance
Equivalent Short-Circuit
Input Noise Voltage
Common-Source Forward
Transconductance
Common-Gate Input
Conductance
Common-Source Input
Conductance
Common-Source Output
Conductance
Common-Gate Power
Gain at Noise Match
Noise Figure
Common-Gate Power
Gain at Noise Match
Noise Figure

NOTE: 1. Pulse test PW 300 1'5, duty cycle

MIN
25

TYP

-1.0

1.0
1.0
-6.5

12

60

MIN
-25

TYP

MAX

MIN
25

TYP

MAX

1.0

1.0
1.0
-6.5

"A
V

15V,
VGS
T - +125°C
Vos ~ 0
Vos - 10V. 10 - 1nA

12

30

24

60

mA

VOS

1.0

V

1.0
20,000 8,000

200

10V, VGS

0

VOS - 0, IG - 1 mA

18,000
200

200

13,000

13,000

12,000

150

150

150

pmhos

1.8

2.5

1.8

2.5

1.B

2.5

4.3

5.0

4.3

5.0

4.3

5.0

10

nA

TEST CONDITIONS
11'A, VOS - 0

IG -

2.0

20,000 10,000

10

UNIT
V

1.0
1.0
-4.0

1.0
8,000

J310

J309
MAX

10

pF
nV

JHz
12

12

12

14

14

14

0.4

0.4

0.4

0.15

0.15

0.15

16

16

16

1.5
11

1.5
11

1.5
11

2.1

2.7

2.7

Vos ~ 10V,
10 ~ 10mA

Vos
VGS

~
~

0,
-10V

Vos 10V,
10 ~ 10 mA

f ~ 1 kHz

f~

1 MHz

f

~

100 Hz

f

~

105 MHz

mmho
Vos ~ 10V,
10 ~ 10mA

dB
f ~ 450 MHz

:s 3%.

1-38

U308·U310

N·ChanneIJFET
FEATURES
•

•

•
•

is relatively flat out to 1000MHz. Applications for these
devices in military, commercial and consumer communica·
tions equipment include low noise, high gain R F amplifiers,
low noise mixers with c:onversion gain, and low noise, ultra
stable RF oscillators.

High Power Gain
15dB Typical at 100MHz, Co~mon Gate
10dB Typical at 450MHz, Common Gate
Low Singl~ Sideband Noise Figure
1.5dB Typical at 100MHz, Common Gate
3.2dB Typical at 450MHz, Common Gate
Wide Dynamic Range - Greater than 100dB
Offered in Wide Variety of Packages for Most Any
Circuit Configuration.

II

GENERAL DESCRIPTION
This family of N·channel Junction FETs are designed and
characterized for VHF and UHF applications requiring high
gain and low noise figure. The forward transconductance

PIN
CONFIGURATIONS

TO 52

CHIP
TOPOGRAPHY

TO·92

5021

NOTE: suaSTRATE

IS GATE

S

0

G

ORDERING INFORMATION
TO·52
U308
U309
U310

TO·92"

WAFER

DICE

U308/W
U309/W
U310/W

U308/D
U3091D
U310/D

• See J308·310 data sheet for TO·92 package.

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate·Drain or Gate·Source Voltage
Gate'Current
Total Power Dissipation
Power Derating (to maximum operating temperature)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (1/16" from case for 10 sec)

TO·52

TO-92

.-25V
20mA
500mW
4.0mWtC
-65 to 150°C
-65 to 200°C
300°C

-25V
10mA
300mW
3.0mWtC
"":55 to +125°C
'-55 to +125°C
300°C

1-39

U308·U310
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
U30a

CHARACTER ISTIC
MIN

IGSS

D

BV GSS
V

TYP

U309
MAX MIN

TYP

U310
MAX MIN

TYP

UNIT

-150

-150

-150

pA

V GS =-15V

-150

-150

-150

nA

VGS= 0

Gate Reverse Current

Gate-Source Breakdown
Voltage

Gate-Source Cutoff
GS(off) Voltage
Saturation Drain Current

lOSS

(Note 1)

VGS(f)

Gate-Source Forward
Voltage

gfg

Common-Gate Forward
Transconductance (Note 1)

TEST CONDITIONS

MAX

-25

-25

-25

T = 125°C

IG = -1 !lA, VOS = 0
V

-1.0

-6_0

-1.0

-4.0

-2.5

-6.0

12

60

12

30

24

60

mA

VOS=10V,VGS=0

1.0

V

IG = 10mA, VOS= 0

1.0

10

20

1.0

10

20

10

18

VOS = 10 V, 10 = 1 nA

mmho
VOS= 10 V,
10=10mA

Common-Gate Output
gogs

Conductance

Cgd

Drain~Gate

Cgs

Gate Source Capacitance

en

Equivalent Short Circuit
Input Noise Voltage

10

gig

Conimon·Gate Forward
Transconductance

12
11

gogs.

Common·Gate Output
Conductance

Capacitance

150

150

150

2.5

2.5

2.5

5.0

5.0

5.0

VGS= -10V,
pF
8

10

10

12
11

-

f = 1 kHz

!lmho

VOS= 10V

l!Y

VOS = 10 V,

¥Hz

10=10mA

1= 1. MHz

1= 100 Hz

1=100MHz
, - 450 MHz

12
11
mmho

Gpg'

Common·Gate Power
Gain

NF

Noise Figure

0.18·
0.7

0.18
0.7

0.18
0.7

15
10

15
10

15
10

1.5
3.2

1.5
3.2

1.5
3.2

VOS=10V,
10 = 10 mA

1= 100 MHz
1=450MHz
1= 100MHz
1=450MHz

dB

NOTE: Pulse test duration = 2 ms.

1-40

1= 100 MHz
1= 450 MHz

U401-U406
Monolithic Dual N-Channel
JFET
FEATURES
• Minimum System Error and Calibration - SmV
Offset Maximum (U401), 9SdB Minimum CMRR
(U401-04)
• Low Drift with Temperature - 10jlVfOC Maximum
(401,02)
• Operates from Low Power Supply Voltages VGS(off) <2.SV
• Simplifies Amplifier Design - Output Impedance
>SOOKfl

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·71

6017

~

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage

.................

Forward Gate Current .•••••••••.••••••••••••••••• 10

52 °2
G,

50V

G,

U
0,

I---

II

023! 002---1

iI!!
~~'
OlD

I

G,

'1' "

SOURCE
DRAIN

3.6 Mil

GAT!

J.3Mll

:;

J.3MIL

5,

rnA

Device DiSSipation (each side)

@ TA

= 85°C derate 2.6 mW/oC

••••••••••••.• 300 mW

ORDERING INFORMATION

Total Device Dissipation

@ TA

= 85°C (derate 5

mW/oC) ••••••••••••••• 500 mW

l

Storage Temperature Range •••••••••••••••• -65 to 200°C

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25° unless otherwise
Characteristic
1

~

IGSS

'3

S
T
~ 'A
T
I
f-- C

VGSloffl

~B

IG
BVG'-G2

'5
~

VGS(on)

loss

9

gt,

Iw

9o,

S1
~

f-;3
f-:;4

Gate-Source Breakdown
Voltage
Gate Reverse Current
INote 11
Gate-Source Cutoff
Voltage
Gate-Source
Voltage lonl
Saturation Drain Current
INote 21

BVG5S

D
Y
N
A
M
I
C

15
16 M
_A
17 T
C
I-;sH
I
N
G

gt,
go,
Ciss
Crss

eN
CMRR
IVGS1-VGS21 .
~IVGs1-VGs21
~T

<

Gate Current INote 1I
Gate-Gate Breakdown
Voltage
Common-Source Forward
Transconductance (Note 2)
Common-Source Output
Conductance
Common-Source Forward
Transconductance
Common-Source Output
Conductance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance
Equivalent Short-Circuit
Input Noise Voltage
Common-Mode Rejection
Ratio INote 31
Differential Gate-Source
Voltage
Gate-Source Voltage Differentiar Drift INote 41

I

TO·71
U40X

J

I

WAFER
U40X/W

U402
U403
U404
U405
U406
Min Max Min Max Min Max Min Max Min Max Min Max
-50
-50
-50
-50
-50
-50
25
2.5

25
.5

2.5

.5

10.0 0.5

-15
10

-15
10
±50

2.5

-.5

2.5

10.0 0.5
15
10

J

DICE
U40X/D

I

-.5

2.5

-25
.5

-2.3

Unit
V
pA

2.5
2.3

Test Conditions

VOS - O. VGS- 30V
Vos

V

15V, 10

1 nA
200~A

VOG

15V, 10

10.0 0.5

10.0

rnA

VOS

10V, VGS

-15
10

-15
10

-15
10

J)A

VOG - 15V,
10 = 200~A
Vos 0, VGS

±50

±50

nA
V

,

VOS - O. IG - -l~A

10.0 0.5

±50

±50

-25

2.3

2.3

10.0 0.5

±50

-25

25

2.3

2.3
0.5

I

noted.

U401

5

1

0

TA - 125°C
O,IG ±l~A

2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
20

20

20

20

20

1000 1600 1000 1600 1000 1600 1000 1600 1000 1600 1000 1600
2.0

2.0

2.0

2.0

2.0

VOS= 10V,
VGS = 0

20

1=1 kHz

2.0

B.O

B.O

B.O

8.0

B.O

8.0

3.0

3.0

3.0

3.0

3.0

3.0

20

20

20

20

20

20

VOG = 15V,
10 = 200~A
pF
nV

95

95

95

90

dB

VOG

5

10

10

15

20

40

mV

10

10

25

25

40

80

~V/oC

~~

1=1 MHz
Vos 15V,
1= 10 Hz
VGS = 0
VOG - 10 to 20V, 10 - 200~A

JHZ
95

1=1 kHz

.u mho

10V, 10

VOG 10V,
10 = 200~A

200~A

TA -55°C,
TB=+25°C,
ID = 200~A
Tc = +125°C

V

1. Approximately doubles for every 10° C increase in TA. 2. Pulse test duration = 3001'5, duty cycle:5 3%. 3. CMRR = 20 I0910[ Ll.IVG~1-~~S21]
= 10V. 4. Measured at end points, TA, TB and Tc.

Ll.VDD

1-41

U410· U412
Monolithic Dual
N·Channel JFET

APPLICATIONS

FEATURES

1.

FET Input Amplifiers

• Minimum System Error and Calibration

PIN
CONFIGURATION
TO·71

10 mV Offset Maximum (U410)
70 dB Minimum CMRR (U410)

• Low and Medium Frequency
Amplifiers

10 /LVI 'C Maximum (U410)

• Precision Instrumentation
Amplifiers

Ol3 !,OOI

1:

Low Output Conductance

I

(, ~
III

<;(jlll~

Cf

[)Hfll"
(01\11

ABSOLUTE MAXIMUM RATINGS (25°)

s>'

Gate-To-Gate Voltage . ....... ; •....................... ± 40 V
Gate-Drain or Gaie-Source Voltage . .................. 50 - 40 V
Gate Current ......................................... 50 mA
Total Package DisSipation (25.'C Free-Air) ................ 375 mW
Power Derating ........................ '.... '....... 3.0 mW/'C
Storage Temperature Range. , ................. -65 to + 150'C
Lead Temperature
(1/16" from case for 10 seconds) ......................... 300 'C

G,

G,

---l

E~'

:!: 00;>

• Simplifies Amplifier Design

, • Comparators

t-.

6017

e=

• Low Drift with Temperature

• Impedance Converters

CHIP
TOPOGRAPHY

'1. (,

~'Il

I , ;1

~'Il

I. '(

~'Il

~ s,
0,

ORDERING INFORMATION
WAFER
U410/W
U411/W
U412/W

TO·71
U410
U411
U412

DICE
U4101D
U4111D
U4121D

ELECTRICAL CHARACTERISTICS (25 'C unless otherwise noted)'
U410
Characteristic

Min

TYP

Gate Reverse
IGSS

S
T

Gate-Source Breakdown

BVGSS

I

lOSS

C

IG
VGS

Voltage
Saturation Drain Current
(Noie 2)
Gate Current (Note 1)
Gate·Source Voltage
Common-Source Forward

gts

D

Transconductance

y
N

gos

A
M

Ciss

C
M
A
T
C
H

Crss
en

I

-1.0

-3.5

Capacitance
Common-Source Reverse
Transfer CapaCitance

-40
0.5

5.0

-0.2
1,000
600

Min

TYP

-200

I;
-1.0

-3.5

-1.0

Unit

Test Conditions

pA

VOS=O,VGS= -30V

Max
-200
-3.5

VOS=20V, 10=1 nA

-40

0.5

5.0

VOS = 0 V, IG = - 1 "A

0.5

5.0

-200
-3.0 -0.2
4,000 1,000

-200
-3.0 -0.2
4,000 1,000

-200

pA

-3.0
4,000

V

1,200
20
5

1,200
20
5

1,200

600

600

20
5

4.5

4.5

4.5

1.2

1.2

1.2

rnA'

.

VOS = 20 V, VGS = OV
VOG=20V,10=200"A
VOS = 20 V, VGS = 0 V

"mho

pF

I Differential Gate·Source

LlVGs,-VGS2IGate.Source
6T
Differential Drift (Note 3)
Common-Mode Rejection
G
CMRR
Ratio (Note 4)

U412
Max

-40

Equivalent Short·Circuit
Input Noise Voltage

VGS,-VGS2 Voltage.

TYP

V

Common·Source Output
Conductance
Common-Source Input

I

Min

-200

(Note 1)

Gate·Source Cutoff
VGS(off)
Voltage

A
T

U411
Max

50

50

50

10

20

40

mV

10

25

80

"V/'C

VOG = 20 V, 10 = 200 "A
VOS=20V,VGS=OV
VOG'- 20 V, 10 - 200 "A

f= 1 KHz

VOS = 20 V, VGS = OV

t =1 MHz

VOS = 20 V, 10 = 200 "A

f = 100 Hz

VOG = 20 V, 10 = 200 "A
VOG = 20 V, 10 = 200 "A

I
N,

80

80

70

dB

TA = 25'C toTB= 85'C
VOO =10VtoVOO = 20V
10 = 200 "A

Note 1: Approximately doubles for every 10'C increase in TA·
[
LWOD
]
Note 2: Pulse test duration = 300 /Lsec; duty cycle,;; 3%.
Note 4: CMRR = 2010910 61VGSI.VGS2 1
Note 3: Measured at end points, T A and Te.

1-42

6VDD = 10 V.

U421'·U426
,Monolitic Dual
N·ChanneIJFET
APPLICATIONS,
• Very High Input Impedance
Differential Amplifiers
• Electrometers
• Impedance Converters

PIN
CONFIGURATION

CHIP
TOPOGRAPHY
6034

TO·99

FEATURES
• High Input Impedance
IG = 0.1 pA Maximum (U421-3)
• High Gain gls = 140 !Lmho
10 = 30 !LA (U421-3)
• Low Power Supply Operation
VGS(off) = 2V Maximum (U421-3)
• Minimum System Error and Calibration
10 mV Maximum Offset
90 dB Minimum CMRR (U421, U424)

ABSOLUTE MAXIMUM RATINGS (25°C)

ORDERING INFORMATION

Gate-to-Gate Voltage ............................ ±40V
Gate-Drain or Gate-Source Voltage .'.•.......••..., -40V
Gate Current ...••.•.•.....•.••.•. '......•....•... 10 rnA
Device Dissipation (Each Side), TA = 25°C
, (Derate 3.2 mW/oC to 150°C) ..•.............. 400 mW
Total Device Dissipation, TA = 25°C
(Derate 6.0 mW/oC to 150°C) .•..•• : ••....•... 750 mW
Storage Temperature Range ..•....•...... --65 to +150°C

TO·99
U421
U422
U423
U424
U425
U426

ELECTRICAL CHARACTERISTICS

DICE
U4211D
U422/D
U423/D
U424/D
U425/D
U4261D

WAFER
U421/W
U422/W
U423/W
U424/W
U425/W
U426/W

TEST CONDITIONS: 25°C unless'otherwise noted
U421-3
Min Typ Max
-40 oW
BVGSS Gate-Source Breakdown Voltage
+40
BVG1G2 Gate-Gate Breakdown Voltage
0,2
Gate Reverse Cu rrent (Note 1)
IGSS
O.S
0,1
Gate Operating Current (Note 1)
IG
-100
-2.0
VGS(oH) Gate-Source Cutoll Voltage
-

GENERAL DESCRIPTION
A low noise, low leakage FET that employs a cascode
structure to accomplish very low IG at high voltage levels,
while giving high transconductance and very high common
!'(lode rejection ratio.
.

> 120 dB

5 pA @ 50VDG

• Low Miller Capacitance (Crss)
• Low

90S

> .025 I'mhos

'

G1

~

@-2
Gz

.,

M~IMUM RATINGS
(@ 2S'C unless otherwise noted)

ABSOLUTE

Sz

PIN
CONFIGURATION
10·71
low profile

Maximum Temperatures
Storage Temperature ............ -6S'C to
Operating Temperature. • . . . • . . • • . . . . . . . ..
Lead Temperature (soldering, 10 sec time limit).

+ 1S0'C
+ 1S0'C
+ 3OO'C

Maximum Power Dissipation
Device Dissipation @ 8S'C Free Air Temperature
One Side . ~ ......... : . . . . . . • . . . . . . . • • . •. 250 mW
Both Sides ................. . . . . . . . . . . .. 500 mW
Linear Derating

CHIP
TOPOGRAPHY

One Side ......... : ...............••. 3.8S mW/'C
Both Sides ....••........•...........

7.7 mW"C

S028

BODY -..:r:r.;-;;~;;;;;;-]
.003 DIA.

Maximum Voltages & Currents
Vos Drain to Source Voltage .......•..•...••...• 60V

SOURCE 1
.033 x.OO3 •

GATE 1
.003 x .003

VGS Gate to Source Voltage; . . . . . . . . . . . . . . . . . .. 60V

GATE 2
.003 x.OO3

VGO Gate to Drain Voltage ......... ' ....../ .•... 60V
VG1 G2 Gate to Gate Voltage ..........•.• ; . . . . .. 60V
IG Gate Current .......... ." •....... : ....... ;. SO mA
",,','

DRAIN 1
.003 x.OO3

DRAIN 2
.003 x.OO3
SOURCE 2
.003 x.OO3

~

ORDERING INFORMATION

NOTE: Due, to the non·symmetrical structure of these devices. the
drain and source ARE NOT intercha,ngeable.

1-4S

TO·78
ITSOO
ITS01
ITS02
ITS03
ITS04
ITSOS
\

WAFER
ITSOO/W
ITS01/W
ITS02/W
ITS03/W
ITS04/W
ITS05/W

DICE
IT500/D
ITS01/D
ITS02/D
ITS03/D
ITS04/D
ITSOS/D

I

IT500 ·IT505
ELECTRICAL CHARACTERISTICS
Symbol

(@25°C

unless otherwise specified)

Characteristics

Min

IGSS

Gate Reverse Current

BVGSS

Gate·Source Breakdown Voltage

-50

<

VGS (off)

Gate·Source Cutoff Voltage

-0.7

CI)

VGS

Gate·Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain Current (Note 1)

u

f=

I-

II
u
~

z<
>0

mA

1000

4000

700

1600

gas

Conductance

Cglg2

Gate to Gate Capacitance

C iss

Common·Source Input
Capacitan.ce

C rss

Common-Source Reverse
Transfer Capacitance (Note 3)

0.5

NF

Spot Noise Figure

0.5

-en

Equivalent Input Noise Voltage

Characteristics

VOG = 5011, 10 = 200 IlA
125°C
VOS = 20V, VGS = 0

VOG = 20V, 10 = 200 IlA
Ilmho

0.025

V G1 = V G2 :=10V

pF

7

f = 1 MHz
pF
VOS = 20V, VGS = 0
f- 100Hz,
RG = 10 Mn

dB

f = 10 Hz
f = 1 kHz

IlV

0.035
0.010

VHZ

Test Conditions

Unit
nA

VOG = 20V,
10 = 200 pA

-

VOS = 20V, VGS

Differential Gate

gl51
gl52

6 VGS1,VGS2

---6T

10

1

0.95

1

0.95

1

0.95 0.90

Transconductance

0.97

1

0.97

1

0.95

1

0.95

Cor;nmon Mode

CMRR "

5

0.95

Differential Gate·
Source Voltage
Gate·Source Dif·
ferential Voltage
Change with
Temp. (Note 2)

VGSfVGS2

5

Saturation Drain
Current Ratio
(Note 1)
Ratio (Note 1)

 2000 jJ.mhos

PIN
CONFIGURATION

ABSPLUTE MAXIMUM RATINGS INate 1)
@

25 C (unless otherwise noted)

CHIP
TOPOGRAPHY
1503

TO·72

Maximum Temperatures

Storage Temperature
Operating Junction Temperature
Lead Temperature (soldering,
10 second time limit)

":6S"C to '~200°C
_55°C to +150°C

Maximum Power Dissipation
Total Dissipation at 2SoC
. Ambient ~emperature
"
Linear Derating Factor at 25 C
Ambient Temperature
Total Dissipation at 2S o C
Case Temperature
Linear Derating Factor at 25° C
Case Temperature

0.375 W

3mwtc
1.25W

10

Maximum Voltages and Current
VOSS Drain to Source and Body Voltage
V SDS Source to Drain and Body Voltage
VGSS Transient Gate to Source Voltage
(Note 2)
V GSS Gate to Sour~(! Voltage
ID(on) Drain, Current

mwtc

ORDERING INFORMATION

-40 V
-40 V
±125 V
-40 V
50mA

ELECTRICALCHARACTERISTICS(@ 25"C unless otherwise noted)
UNITS

TEST CONDITIONS

BVDSS

Drain to Source Breakdown Voltage

-40

V

VGS - 0,10 - -10 /lA

-40

V

VGS = 0,10 = -10 /lA
(See Note 2)

PARAMETER

MIN

MAX

BVSOS

Source to Orain Breakdown Voltage

IGSS

Gate Leakage Current

lOSS
lOSS (150°C)

Drain to SourGe Leakage Current

200

pA

VGS = 0, VDS = -20 V

Orain to Source Leakage CLirrent

0.4

VGS = 0, VOS = -20 V

ISOS
ISOS (150°C)

Source to Orain Leakage Current

400

/lA
pA

Source to Orain Leakage Current

OB

VGS = 0, VOS= -20 V

VGS(th)

Gate Threshold Voltage

/lA
V

-2

-5

VGS = 0, VOS = -20 V
VGS = VDS, ID = -10 /lA

ELECTRICAL CHARACTERISTICS (@25°C unless otherwise noted)
PARAMETER
ros (on)
IDS (on)

MIN

Static Orain to Source "on" Resistance
. Orain to Sour'ce "on" Current

TYP

MAX

UNITS

400

ohms
mA

4000

/lmhos

5

pF

VOS = -15 V,ID = ~10 mA
f = 1 MHz
VOG=-15V,ID~0

2
2000

9fs

Forward Transconductance
Common Source

Ciss

Small Signal, Short Circuit, Common
Source, Input Capacitance

Crss

Small Signal, Short Circuit, Common
Source, Reverse Transfer Capacitance'

1.2

pF

Coss

Small Signal,Short Circuit, Common
Source, Output Capacitance

3.5

pF

en

Equivalent I nput Noise Voltage
..

TEST CONDITIONS
VGS - -10 V, VDS- 0
VGS=-10V, VOS=-15V
VOS;" -15 V, 10 ~ -10 mA
f = 1 kHz

f = 1 MHz

150
.

nV/y'Hz

VOS = ~15 V, 10
f = 1 MHz

~

-:10 mA

VOS=-15V, 10=-1 mA
f = 100 Hz; BW = 1 Hz

.

NOTE: 1. These ratings are limiting values above which the serviceability of any semiconductor device may.be Impaired .
2. Actual gate current is immeasurable. Package suppliers are .required to guarantee a package leakage of < 10 pA. External package
leakage is the dominant mode which is sensitive to both transient and storage environment,.which cannot be guaranteed.

IT1750
N·Channel Enhancement
Mode MOS FET
FEATURES
•

PIN
CONFIGURATION

Low On· Resistance - 50n

•

Low Capacitance - 1.7 pF

•

High Gain - 3,000 fJmhos

•

High Gate Breakdown Voltage - ±125V

•

Low Threshold Voltage - 3 V

TO·72

I

ABSOLUTE MAXIMUM RATINGS (Note 1)
@

25°C (unless otherwise noted)

Maximum Tempe'ratures
Operating Junction Temperature
Maximum Power Dissipation
Total Dissipation at 25° C Ambient Temp.
Linear Derating Factor at 25° C
Ambient Temp.

3mwtC

Maximum Voltages and Current
VOSS Drain to Source and Body Voltage
V GSS Transient Gate to Source Voltage
ID(on) Drain Curr~nt

25 V
±125 V
100 mA

375mW

CHIP
TOPOGRAPHY
1003
.~~~ x %~~

f- -

0260 -

----![

f;ill:
NOTE: SUBSTRATE
IS BODY

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS
VGS(TH)
lOSS
IGSS
BVOSS
rDS(on)
10(on)

(T A ~ 25°C, Body connected to Source unless otherwise noted)

PARAMETER
Gate to Source Threshold Voltage
Orain Leakage Current
Gate Leakage Current (Note 2)
Orain Breakdown Voltage
Orain To Source on Resistance
Orain Current

MIN
0.50

TVP
1.5
0.1

MAX
3.0
10

UNITS
V
nA

25
50

50

V
ohms
mA

25
10

= 10MA, VGS ~

VBS ~ 0
20 V, VBS =0
VOS ~ VGS ~ 10 V, VBS ~ 0
VOS~ 10V, 10~ 10 mA,
I ~ 1 KHz, VBS ~ 0
10

VGS~

Vis

Forward Transadmittance

Ciss

Total Gate I nput Capacitance

5.0

6.0

pF

10 = 10 mA, VOS ~ 10 V,
1= 1 [v1Hz, VBS ~ 0

Cdg

Gate to Orain Capacitance

1.3

1.6

pF

VOG ~ 10 V, VBS ~ 0

Note: 1.

2.

Mmhos

TEST CONDITIONS
VOS ~ VGS, 10 - 10 pA; VBS - 0
VOS ~ 10 V, VGS ~ VBS ~ 0
(See Note 2)

3,000

These ratings are limiting values above which the serviceability of any semiconductor device may be impaired:
Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of < 10pA.
External package leakage is the dominant mode which is sensitive to both transient and storage environment, 'which
cannot be guaranteed.

1-49

U1897·U1899

N·ChanneIJFET
FEATURES

D

PIN
CONFIGURATION

• Low insertion Loss
rOS(on)< 30n (U1897)
• No Error or Offset Voltage Generated
by Closed Switch

CHIP
TOPOGRAPHY

TO·92

5001B

9

APPLICATIONS
Analog, Switches, Choppers, Communicators

.OOI351.03427} FUll RADIUS

'"' 'C'1' ' '

I:~_,"'n

-I-J·,
l
1 ~

ABSOLUTE MAXIMUM RATINGS (25°)

.OO72j.182i~

NOTE: SUBSTRATE IS GATE

1

""sa..

Gate-Drain or Gate-Source Voltage .......... - 40V
Forward Gate Current ...................... 10mA
Total Continuous Device Dissipation
at (or Below) T A = 25°C
(Derate 3.5mW/oC to 125°C) .............. 350mW
Storage Temperature Range ....... - 55 to + 125°C
Operating Temperature Range ..... - 55 to + 125°C
Lead Temperature
(1/16" from case for 10 seconds ............,300°C

]"'"

1-

s

~~

0

T

IGSS
IDGO
ISGO

A

ID(oll)

Drain Cutoff Current

VGS(Off)

Gate-Source Cutoff Voltage '
::;aturahon uram vurrent
(Note 1)

S

I

TO·92
U1897
U1898
U1899

WAFER
U1897/W
U1898/W
U1899/W

DICE
U18971D
U18981D
U18991D

D

Y

VDS(on)

Drain-Source ON Voltage

0.2

0.2

0.2

V

VGS =0, ID=6.6mA (U1897)
ID=4,OmA (U1898)
ID=2.5mA (U1899)

rDS(on)

Static Drain-Source ON
Resistance
Drain-Gate Capacitance
Source·Gate Capacitance
Common-Source Input
Capacitance

30

50

80

I)

ID-lmA, VGS=O

5
5
16

5
5
16

5
5
16

Common-Source Reverse
Transler Capacitance
Turn ON Delay Time
Rise Time

3.5

3.5

3.5

15
10

15
20

20
40

CDG
CSG
CISS
Crss

N
A
M

td(on)
tr

C
toft

VDG _,20V, IS-O
VSG-20V, 10=0
pF

1=1 MHz
VDS=20V, VGS=O

I

I

.003&(.0853)

.oo35(.o~:ci:R~~6<·06601

U1897
U1898
U1899
TEST CONDITIONS
MIN MAX MIN MAX MIN MAX, UNIT
-40
-40
-40
IG= -lpA, VDS=O
40
40
V
IG= 1pA,IS-0
49
40
40
40
IG- -lpA, ID-O
-400
-400
-400
VGS--:-20V, VDS-O
200
200
200
VDG-20V,IS-0
200
200
200 pA VSG-20V,ID=0
~uu
' ~uu
~uu
VDS-20V, VGS--12V (U1897)
10
10
10 nA VGS = -:8V (U1898)
VGS= -6V (U1899) TA=85·C
-5.0 -10 ~2.0 -7.0 -1.0 -5.0
V
VDS = 20V, ID - 1 na
30
15
8.0
rnA VDS=20V, VGS-O

T

C I'DSS

I

,

DI8C.457)-

G

TEST CONDITIONS: 25°C unless otherwise noted

BVGSS
BVDGO
BVSGO

.()0451,IH31

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS

PARAMETERS
Gate·Source Breakdown Voltage
Drain-Gate Breakdown Voltage
Source·Gate Breakdown Voltage
Gate Reverse Current
Drain-Gatll Leakage Current
Source-Gate Leakage Current

'"

Turn OFF Time

Switching Time Test Conditions
ns

U1897
VDD

60

40

80

VGS(on)
VGS(Off)
RL
'D(on)

NOTE: 1. Pulse test pulsewidth =300/,5; duty cycle<3%

1·50

';3V
0
-12V'
4301)
6.6mA

U1898
3V

a
-8V
700!l
4mA

U1899
3V
0
-6V
11001)
2.5mA

2N2607-2N2609
2N2609 JAN
P-Channel JFET
APPLICATIONS
•

PIN
CONFIGURATION

Low-level Choppers

5010

• Data Switches
TO-1S

o

ABSOLUTE MAXIMUM RATINGS

Sill

(unless otherwise noted)
0025

Maximum Voltages & Current
V DG Drain to Gate Voltage
VSG Source to Gate Voltage
IG Gate Current

0025

0035)( 0035

Maximum Temperatures
_65°C to +200°C
Storage Temperature
'Operating Junction Temperature
+175°C
Lead Temperature (Soldering, 10 sec_ )
+260°C
Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating

(for 2N2607, 8)

012\

• Commutators

@ 25°C

:
;
11

CHIP
TOPOGRAPHY

FULL R

T

I~
IIL!J

all
015

~ '"004~
0050

~
NOTE

SUBSTRATf
IS GA TE

all

5503B

300mW
2_0mWtC'

30V
30V
50mA

ORDERING INFORMATION
TO-1S
2N2607
2N260S
2N2609
2N2609 JAN

WAFER

DICE
2N26071D
2N260S/W
2N260SID
2N2609/W
2N26091D
2N2609 JAN/W 2N2609 JANID
2N2607/W

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
2N2607
Characteristic

Min

V GS = 30 V, V DS = 0
IGSS

BV GDS
Vp

V GS = 5 V, V DS = 0, T A = 150 C
0

Gate·Drain Breakdown

Voltage
Gate-Source Pinch·Off
Drain Current at Zero Gate

DSS

Voltage

gis'

Small·Slgnal Common·Source
Forward Transconductance

Giss

. Gate·Source Input Capacitance

1G = 1 tJA, V DS = 0

Max

Min

Max

Min

Max

Unit

3

10

30

nA

3

10

30

!1A

Noise Figure

30

V DS = -5 V, ID = -1

tJA

1

30
4

1

4

-0.30 -1.50 -0.90 -4.50

V DS = - 5 V, V GS = 0, I = 1 kHz

330

V DS =-5V,V GS =IV,
1=140kHz

V GS = 0,

1000
10

R~

= 10 MD

R

=

V

30

V DS = -5 V, VGS'= 0

V DS = -5 V,
NF

2N2609

Gate·Source Cutoff Current

Voltage
I

2N260S

Test Conditions

1

4

-2

-10

V
rnA
}Jrnho

2500
17

30

3

3

pF

3
dB

1= 1 kHz

1-51

G

lMD

II

2N3684·2N3687
N·Channel JFET
FEATURES

PIN
CONFIGURATION

O.

• C GSS < 1.2 pF
Exceptionally high figure of merit

•

TO·72

Radiation Immunity

• Symmetrical devices for low-level choppers, data
switches, multiplexers and low noise amplifiers

•

Extremely low noise and capacitance

•

High input impedance

•

Zero offset

•

High reliability silicon epitaxial planar construction

D

CHIP
TOPOGRAPHY

ABSOLUTE MAXIMUM RATINGS
@

25°C (unless otherwise noted)

5010

Maximum Temperatures'
Storage Temperature
Operating Junction Temperature
Lead Temperature (Soldering,
10 sec time limit)

0(2)

_65°C to +200°C
+200°C

:~mFULLR

5111

, T
m
IIl!J
.-L
I~

.

011,

015

Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating

.0025 X .0025

~ '004~

.00350035

300mW
1.7 mW/C

.0056

•

NOTE. SUBSTRATE

IS GATE .
.011

:015

Maximum Voltages & Current
V GS Gate to Source Voltage
V GD Gate to Drain Voltage
Gate Current
IG

-50V
-50 V
50mA

ORDERING INFORMATION
TO·72

WAFER

DICE

2N3684
2N3685
2N3686
2N3687

2N3684/W
2N3685/W
2N3686/W
2N3687/W

2N3684/D
2N3685/D
2N3686/D
2N3687/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
PARAMETER
BVGSS Gate to Source Breakdown Voltage
Vp
Pinch·Ofl Voltage
Total Gate Leakage Current
IGSS
Total.Gate Leakage Current (150 C)
IGSS
Saturation Current, Drain-ta-Source
lOSS
Forward Transadr:nittance
. IYfsl
C iss
Gos
Crss

Common Source Input Capacitance
(Output Shorted)
Small Signal, Common Source Output Conductance (input shorted)
Small Signal, Common Source Short

Circuit Reverse Transfer Capacitance
'OS(on) On Resistance
NF
Noise Figure (Spot)

2N3684
MIN
MAX

2N3685
MIN
MAX

2N3686
MIN
MAX

2N3687
MIN
MAX

-50
2.0

-50
1.0

-50
0.6

-50
0.3

2.5
2000

5.0
-0.1
-0.5
7.5
3000

1.0
1500

3.5
-0.1
-0.5
3.0
2500

4.0

4.0

50

0.4
1000

2.0
-0.1
-0.5
1.2
2000

0.1
500

1.2
-0.1
-0.5
0.5
1500

UNITS

TEST CONDITIONS

V
V
nA
IJA
mA

VOS=OV, IG -1.0IJA
VOS = 20 V, 10 = O,OOlIJA
VGS - -30 V, VOS - 0
VGS -JOV, VOS-O@150°C
VGS - 0 V, VOS - 20 V
VOS - 20 V, VGS - 0 V
f = 1 kHz
VOS - 20 V, VGS = 0,
1= 1 kHz
VOS=20V,VGS-0,
f = 1 kHz
VOS = 20 V, VGS - 0,
f = 1 kHz
VDS - 0, VGS - 0
f - 100 Hz, RG - 10 Mn
NBW = 6 Hz, VOS = 10 V

.umhos

4.0

4.0

pF

25

10

5

Ilmhos

1.2

1.2

1.2

1.2

pF

600
0.5

800
0.5

1200
0.5

2400
0.5

Ohms
dB

1-52

U~Ulb

2N381 O/A,2N38111 A
Monolithic Dual Matched
PNP Transistor

ABSOLUTE MAXIMUM RATINGS
Maximum Temperatures
Storage Temperature .....•.•..•....•.......•...•..•..•..•............ -65°C to +200°C
Operating Temperature ...............•.....•...•............................... 200° C
Lead Temperature (10 seconds) ..............•...•.........•.•................... 230°C
Maximum Power Dissipation
Total Dissipation at .........................•..•...............
One Side Both Sides
25°C Ambient Temperature ................•.•.................
500 mW
600 mW
Linear Derating Factor .....•.............•.........•.•.•....... 2.9 mW/oC 3.4 mW/oC
Maximum Voltage and Current (One side)
VEBO Emitter to Base Voltage ...............................•................... -:5.0V
VCBO Collector to Base Voltage ........••..................•................•... -60V
VCEO Collector to Emitter Voltage .......•.....•.• :.............................. -60V
Ic
DC Collector Current ..•............•...•.....•.' .' ....•.. , ....•. , ..... , ... 50 mA

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS:
SYMBOL

25°C Ambient Temperature unless otherwise noted
CHARACTERISTIC

ICBO

Collector Cutoll Current

lEBO
BVEBO
BVCBO
BVCEO

Emitter Cutoff Current
Emitter to Base Breakdown Voltage
Collector to Base Breakdown Voltage
Collector to Emitter Breakdown
Voltage
DC Current Gain

hFE

VBE(ON)
VCE(sal)
VBE(sal)
hFE1
hFE2
IVBE1-VBE21
I u(VBE1-VSE2) I

Cob
Cib
Ihfel
hie
hre
hoe
hfe
RE(hie)
NF

2N3810
MIN. MAX.
10
10
20
-5,0
-60
-60
100
150
150
150
125
75

Base to Emitter "On" Voltage
Collector to Emitter Saturation
Voltage
Base to Emitter Saturation Voltage
DC Current Gain Ratio

0.9

Base to Emitter Voltage
Differential
Base to Emitter Voltage
Dillerential Gradient

Output Capacitance
Input Capacitance
Magnitude 01 Common Emitter
Small Signal Current Gain
Input Impedance
Reverse Voltage Feedback Ratio
Output Conductance
Small Signal Current Gain
Real Part 01 Common Emitter
Small Signal Input Impedance
Noise Figure

2N3811
MIN. MAX.

1.0
1,0
3.0
5.0
150
3.0

10
10
20
-5.0
-60
-60

450
450
450

-0.7
-0.2
-0,25
-0.7
-0.8,
1.0

225
300
300
300
250
150

0.9

UNITS
nA
f.LA
nA
V
-V-V-

900
900
900

-0.7
-0.2
-0,25
-0.7
-0.8
1.0

,V
-V
-V-V-V-

5.0
-3.0
1.0

5,0
-3,0
1.0

mV
mV

-0.8

-0,8

mV

4.0
8.0

4,0
8,0

PF

5,0
30
25
60
600
30

1.0
1,0
10
5.0
300
10

5,0
40
25
60
900
40

mV

pF

, kfl
x 10-4
f.Lmho
kfl

1,5

dB

2.5

1,5

-dB

7.0

4,0.

-dB-

3.5

2.5

dB

3,0

1·53

TEST CONDITIONS
VCB - -50V, Ic - 0
VCB - -50V, IE - 0, TA - 150°C
VEB --4,OV
Ic - 0, 'E - lOf.LA
IE - 0, Ic - lOf.LA
Ic -10 mA
Ic - 10 f.LA, VCE - -5.0V
Ic - lOOf.LA, VCE - 5,OV
Ic - 500f.LA, VCE - 5,OV
Ic - 1,0 mA, VCE - -5,OV
Ic - 10 mA, VCE - 5,OV
Ic - lOOf.LA, VCE - -5.0V, TA- 55°C
Ic - lOOf.LA, VCE - -5.0V
Ic - lOOf.LA, IB - lOf.LA
Ic -1,0 mA, IB - 100f.LA
Ic - l00f.LA, IB - lOf.LA
Ic - 1.0 mA, IB - lOOf.LA
VCE - -5.0V, Ic - 0,1 mA
VCE - -5,OV, Ic - lOf.LA to 10 mA
VCE - -5.0V, Ic - lOOf.LA
VCE - -5.0V, Ic - 0.1 mA
TA - 25°C to 125°C
VCE - -5.0V, Ic - 0,1 mA
TA - -55°C to +25°C
VCB - -5.0V, 'E - 0, I - 100 kHz
VEB - 0.5V, Ic - 0, I - 100 kHz
Ic - 500f.LA, VCE - -5,OV, f - 30 MHz
Ic- 1.0 mA, VCE - -5.0V, I -100 MHz
VCE- 10V, Ic -1.0 mA, 1- 1.0 kHz
VCE - -10V, Ic -1.0 mA, I - 1,0 kHz
VCE- 10V, Ic - 1,0 mA, I - 1,0 kHz
10V,lc 1.0mA,1 1.0 kHz
VCE
VCE- 10V, Ic - 1.0 mA, I - 1,0 kHz
Ic - lOOf.LA, VCE - 10V, I - 1.0 kHz,
PBW = 200 Hz, RG = 3,0 kfl
Ic - lOOf.LA, VCE - -10V, f - 10 kHz,
PBW = 2.0 kHz, RG = 3.0 kfl
Ic - l00f.LA, VCE - - 10V, I - 100 Hz,
PBW = 20 Hz, RG = 3.0 kfl
Ic - lOOf.LA, VCE - 10V, RG - 3.0 kfl
3,0 dB down at 10 Hz and 10 kHz'
PBW = 15,7 kHz

o

2N38101A, 2N38111A
PIN
CONFIGURATION

CHIP
TOPOGRAPHY

ORDERING INFORMATION

TO·78

4503

TO·78

-r~:;-;;::;;;;;~:l:i.-;-=::;;:i----ISOLATION
.0045 x .0045
COLLECTOR ~1
COLLECTOR
,0035 .0035
.0230

=2 TYP. 2 PLACES

.0270

::,~" :=~

1

D

2N3810
2N3810A
2N3811
2N3811A

WAFER

DICE

2N3810/W
2N3810AIW
2N3811IW,
2N3811AJW

2N3810/D
2N3810A/D
2N38111D
2N3811A/D

BASE =2 TYP. 2 PLACES

--'------.,..+--'~ :~~~ DIAMET~R
BASE =1

~~~~:~~A~~S :~:~

EMITTER =1

OIAMETER

ELECTRICAL CONDITIONS
TEST CONDITIONS: 25°C Ambient Temperature unless otherwise noted
SYMBOL
ICBO

Collector Cutoll Current

lEBO
BVEBO
BVCBO

Emitter Cutoff Current
Emitter, to Base Breakdown Voltage
Collector to Base Breakdown
Voltage
Collector to Emitter ~reakdown
Voltage
DC Current Gain

BVCEO
hFE

VBE(ON)
VCE(sat)
VBE(sat)
hFE1
hFE2

Base to Emitter Voltage Dillerential

Id(VBE1-VBE2)1

Base to ,Emitter Vpltage
Differential Gradient

hie
hre
hoe
h'e
RE(hie)
NF

~O

-60

~O

~O

V

100
150
150
150
125
75

--DC Current Gain Ratio

0.95
0.85

Output Capacitance
Input Capacitance
Magnitude of Common Emitter
Small Signal Current Gain
Input Impedance
Reverse Voltage Feedback Ratio Output Conductance
Small Signal Current Gain
Real Part 01 Common Emitter
Small Signal Input Impedance
Noise Figure

2N3811A
MIN. MAX.

UNITS
nA
p.AnA
V
V

Base to Emitter "On",Voltage
Collector to Emitter Saturation
Voltage
Base to Emitter Saturation Voltage

I VBE1-VBE2 I

Cob
Cib
Ihlel

2N3810A
MIN. MAX.
10
10
20
5.0

CHARACTER'ISTIC

1.0
1.0
3.0
5.0
150
3.0

450
450
450

-0.7
-0.2
-0.25
-0.7
-0.8
1.0
1.0

10
10
20
-5.0

225
300
900
300
900
900300
250 _
150
-0.7
-0.2
-0.25
-0.7
-0.8
0.95
1.0
0.85
1.0

-5.0
1.5
-0.5 '

'-5.0
-1.5
-0.5

-0.4

-0.4

4,0
8.0

4.0
8.0

5.0
30
25

60
600
30

1.0
1.0
10
5.0
300
10

5.0
40
25
60
900
40

"

,

.

TEST CONDITIONS
VCB - -50V, Ic - 0
VCB - -50V, IE - 0, TA -150 D C
VEB --4.0V
Ic - 0, IE - 10p.,t\,
IE - 0, Ic - 10p.A
Ic -10 mA

Ic - 10p.A, VCE - -5.0V
Ic - 100pA, VCE - 5.0V
Ic - 500!,A, VCE - -5.0V
Ic - 1.0 mA, VCE - '5.0V
Ic - 10 mA, VCE - -5.0V
Ic - 100ILA, VCE - -5.0V, TA - -55 D C'
V
Ic - 100p.A, VCE - -5.0V
V
Ic - 100p.A, IB - 10p.A
V
Ic - 1.0 mA, IB - 100p.A
V
Ic - 100p.A, IB - 10 p.A
V
Ic - 1.0 mA, IB - 100p.A
VCE - -5.0V, Ic - 0,1 mA
VCE - -5.0V, Ic - 0.1 mA,
TA - -55D C to +125D C
mV
VCE - -5.0V, Ie - 10p.A to 10 mA
mV
VCE - -5.0V, Ic - 100p.A
mV
VCE - -5.0V, Ic - 0.1 mA
TA - 25D C to 125D C
mV
VCE - -5.0V, Ic -0.1 mA
TA- 55 D C to +25 D C
- pF
VCB - -5.0V, IE - 0, 1 - 100 kHz
pF'
VEB - 0.5V, Ic - 0, 1 - 100 kHz
Ic 500p.A, VCE- 5.0V, 1 30mHz
Ic - 1.0 mA, VCE - 5.0V, 1 - 100 MHz
kO
VCE - 10V, Ic -1.0 mA, 1 - 1.0 kHz
x 10-4 VCE - 10V, Ic -1.0 mA, 1 - 1.0 kHz
p.mho ,VCE - 10V,Ic 1.0 mA, 1 1.0 kHz
VCE - 10V, Ic -1.0 mA, 1 - 1.0 kHz
kO
VCE- 10V,Ic 1.0mA,1 1.0 kHz

3.0

1.5

dB

2.5

1.5

dB

7.0

4.0

dB

3.5

2.5

dB

lOV,1 1.0 kHz,
Ic 100p.A, VCE
PBW 200 Hz RG 3.0 kO
Ic - 10p.A; VCE - -10V, 1 - 10 kHz,
PBW 2.0 kHz, RG 3.0 kO
Ic - 100p.A, VCE - -10V, 1 - 100 Hz.
PBW 20 Hz, RG 3.0 kO
Ic 100p.A, VCE
10V,RG 3.0kO,
3 dB down at 10 Hz and 10 kHz
PBW 15.7 kHz

=

=

=

=

=
=

1·54

=

/

D~DIL

.2N3821, 2N3822

N·ChanneIJFET
FEATURES

PIN
CON FIG U RATION

• Low Capacitance
• Up to 6500 ",mho Transconductance

@

o

TO·72

o
9r-r(

ABSOLUTE MAXIMUM RATINGS
25° C (unless otherwise noted)

Maximum Temperatures
_65°C to +200°C
Storage Temperature
+200°C
Operating Junction Temperature
Lead Temperature (Soldering,
10 sec time limit)
+260°C
Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
300mW
Linear Derating
1.7 mWfC
Maximum Voltages & Current
V GS Gate to Source Voltage
V GD Gate to Drain Voltage
IG Gate Current

c

~s

CHIP
TOPOGRAPHY

-50 V
-50 V
10mA

50038

ORDERING INFORMATION

TO·72

WAFER

DICE

2N3821
2N3822

2N3821/W
2N3822/W

2N3821/D
2N3822/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
IGSS

Gate Reverse Current

BVGSS
VGS(olf)

Gate·Source Breakdown Voltage
Gate·Source Cutoff Voltage

VGS

Gate·Source Voltage

lOSS

Saturation Drain Current

gls
IVlsl

Common·So~rce Forward

Transconductance (Note 1 )
Common-Source Forward

Transadmittance
Common-Source Output

gos

Conductance INote 1)
Common-Source Input

2N3821
MIN
MAX

2N3822
MIN
MAX

-0.1
-0.1

-0.1
-0.1

-50

-6

0.5
0.5

2.5

-1
2

-4
10

1500

4500

3000

6500

3000

1500

fJ.A
V
rnA

TEST CONDITIONS
VGS"-30V.VOS"0

10

20

6

Crss

3,

3

NF

Noise Figur.e

5

5

e;;

Equivalent Input Noise Voltage

200

200

1=1 kHz
1= 100 MHz
VOS.=15V,VGS=0

pF

NOTE: 1. These parameters are measured during a 2 msec interval 100 msec after doC power is applied,

1·55

I
I 150'C

IG-- 1 fJ. A ,VOS-0
VOS - 15 V, 10 - 0.5 nA
VOS 15 V,IO 50fJ.A
VOS - 15 V, ID - 200 VA
VOS" 15 V, VGS - 0 (Note 3)

fJ. mho

6

Capacitance

nA

-50
-4
-2

Common-Source Reverse Transfer
Capacitance

Ciss

UNIT

dB
~

y'RZ

1=1 kHz

1=1 MHz

VOS - 15 V, VGS - 0,
Rqen = 1 meg, BW = 5 Hz
VOS= 15V,VGS"O,BW=5Hz

1= 10 Hz

2N3823
N.Channel JFET

0-

FOR VHF AMPLIFIER OSCILLATOR
MIXER APPLICATIONS

CHIP
TOPOGRAPHY

PIN
CONFIGURATION

Noise Figure < 2.5 dB at 100 MHz
- Low Capacitance
- Transconductance up to 6500 /-Lmho

TO·72

\

ABSOLUTE MAXIMUM RATINGS (25°C)

ORDERING INFORMATION

Gate-Source Voltage .............................. -30V
Gate-Drain Voltage ............................... -30V
Gate Current .................................... 10 mA
Total Device Dissipation at (or below) 25°C
Free-Air Temperature ....................... 300 mW
Storage Temperature Range .............. -u5 to +200°C
Lead Temperature 1/16" From Case to 10 Sec ..... 300°C

ELECTRICAL CHARACTERISTICS (25°C)
CHARACTERISTIC
IGSS
BVGSS
VGS(off)
VGS
IDSS
gls
IVlsl
gas
giss
goss
Ciss
Crss
NF

Gate Reverse Current
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage'
Gate-Source Voltage
Saturation Drain Current
Common-Source Forward
Transconductance
Common-Source Forward
Transadmittance
Common-Source Output
Transcond uctance
Common-Source Input
Conductance
Common-Source Output
Conductance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance
' Noise Figure

MIN

MAX
--{l.5
--{l.5

UNIT
nA
p.A

-30
-1.0
4
3,500

-8
-7.5
20
6,500

V
mA

TEST CONDITIONS
VGS

= -20V, Vos = 0

p.mho

800

150°C

IG - 1 p.A, VOS - 0
VOS = 15V, ID - 0.5 nA
VDS = 15V, ID = 400 /-LA
VDS = 15V, VGS = 0 (Note 3)

3,200
35

I

VOS

f

= 1 kHz (Note 1)

f

= 100 MHz

f

= 1 kHz (Note 1)

f

= 200 MHz

f

= 1 MHz

f

= 100 MHz

= 15V, VGS = 0

200
6
pF

2
2.5

dB

VDS = 15V, VGS
RG = 1 k!1

NOTE 1: These parameters are measured dunng a 2 msec mterval100 msec after d-c power

1·56

IS

=0

applied.

I

2N3824
N·Channel

JFET
FOR HIGH SPEED COMMUTATORS
AND CHOPPERS
• rds < 250 oh-ms
• 10(off)

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·72

50038

< 0.1 nA

ABSOLUTE MAXIMUM- RATINGS (25°C)
Gate-Source Voltage ......•...............•.......... -50V
Gate-Drain Voltage ..•......••............•...•..••.. -50V
Gate Current : ....••...•..•......................... 10 mA
Total Device Dissipation at (or below) 25°C
Free-Air Temperature. . . . . • . . . . . . . . . . . . . .• . . . . . .• 300 mW , -Storage Temperature Range ..•...•.......•.. ---£5 to +200° C
Lead Temperature (1/16" from case for 10 seconds) ... 300°C

ORDERING INFORMATION

-'_ ELECTRICAL CHARACTERISTICS
_rEST CONDITIONS: 25° C unless otherwise noted
MIN

CHARACTERISTIC
IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

10(off)

Drain Cutoff Current

rds(on)

Drain-Source ON Resistance

MAX
-0.1

UNIT

-0.1

JJ.A
V

-50'

TEST CONDITIONS

nA
VGS
IG

= -30V, VOS = 0

0.1

nA

, 0.1 '

p.A

250

n

VGS - OV, 10

Vos

= 15V, VGS = -BV
=0

Ciss

Common-Source Input Capacitance

6

pF

VOS - 15V, VGS - 0

Crss

Common-Source Reverse Transfer Capacitance

3

pF

VGS - -BV, VOS - 0

1·57

150°C

= 1 p.A, VOS = 0
150°C
f - 1 kHz
f

= 1 MHz

o

D~DIL

2N3'921, 2N3922
Dual Monolithic
N·ChanneIJFET

D.

MATCHED FET PAIRS FOR
DIFFERENTIAL AMPLlFIERS

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·71

6017

IG < 250 pA (25 nA at 100°C)
• goss < 20 J.lmhos (ID = 700 J.lA) ,
• Matched VGS, l:;.VGS, and gls

SOURCf
ORAIN
CAT(

ABSOLUTE MAXIMUM RATINGS (25°C)

J.6Mll
J • J Mil
J. JMll

ORDERING INFORMATION

Gate-Drain or Gate-Source Voltage ., ,', , , , , , , , , , , , , , , . , , , " -50V
Gate Current ",. ,', , , , , , , , , . , , , , , , , , , , , , , , , , , , ; , , . , , , , , , . 50 mA
Total Device Dissipation (Derate 1.7 mW/oC to 200°C) '" 300mW
Storage Temperature Range " . , " " " , .. ,";""; --65 to +200°C

' DICE

WAFER

TO·71
2N3921 •
2N3922

2N39211W
2N3922/W

2N3921/D
2N3922/D

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
CHARACTERISTIC
IGSS
BVoGO
VGS(oll)
VGS

MIN

Gate Reverse Current
Drain-Gate Breakdown Voltage
Gate-Source Cutoff Voltage
Gate-Source Voltage

-0.2

Gate Operating Current

loss
gls
gos
Ciss
Crss ,
gls
goss

Saturation Drain Current (Note 1)
1·
Common-Source Forward Transconductance (Note 1) 1500
Common-Source Output Conductance
Common-Source Input CapaCitance
Common-Source Reverse Transfer Capacitance
Common-Source FOl'V'ard Transconductance
1500
Common-Source Output Conductance'

NF

Spot Noise Figure

IVGS1-VGS21
AIVGS1-VGS21
AT
gls1/gls2'

Transconductance Ratio,

UNIT
nA
p.A

50

IG

CHARACTERISTIC
Differential Gate-Source Voltage
Gate-Source Differential Voltage
Change with Temperature

MAX
1
-1
-3
-2.7
-250
-25
10
7500
35
18

6
20
2

2N3921
MIN
MAX
5

V
pA
nA
mA

VGS = -30V, VOS = 0 100°C
10 - 1 p.A, Is - 0
VOS - 10V, 10 - 1 nA
Vos - 10V, 10'= 100p.A
VOG = 10V, 10 = 700p.A 1000C,
VOS - 10V, VGS - 0

p.mho
VOS

== 10V, VGS = 0

p.mho
dB

VOG = 10V, 10';' 700 p.A f = 1 kHz
Vos == 10V, VGS = 0

UNIT
mV

.25

p.V/oC

1.0

,NOTE: 1. Pulse test duratIOn - 2 ms.

1·58

0.95

1.0

-

f - 1 kHz,
RG = 1 meg

TEST CONDITIONS
VOG

= 10V,

10 =700 p.A

0.95

f = 1 kHz

pF

2N3922
MIN
MAX
5,

10

TEST CONDITIONS

TA - O°C
ts= 100o'C
f

= 1 kHz

2N3954·2N3958
Monolithic Dual
N·ChanneIJFET
GENERAL DESCRIPTION
Matched FET pairs for differential amplifiers. This family
of general purpose FETs is characterized for low and
medium frequency ,differential ampl ifiers requiring low
offset voltage, drift, noise, and capacitance.

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

6017

FEATURES

< SmV

•

Drift

< S /lvtc

•

Offset Voltage

•

Low Capacitance - C iss = 4 pF Max

r------023±.Q02--j

020

• Spot Noise Figure;; 0.5 dB Max

GI

t!

(

ABSOLUTE MAXIMUM RATINGS
@

J.6Mll
JlIJMll
J.JMll

ORDERING INFORMATION

25° C (unless otherwise noted)
Any Case-To-Lead Voltage
Gate-Drain or Gate-Source Voltage

±100 V
-50 V
±100 V

Gate-To·Gate Voltage

Gate Current

S,~D'

50 rnA

G, U

Gt

Total Device Dissipation 8S"C (Each Side)
2S0 mW
Case Temperature
(Both Sides)
SOO mW
Power Derating (Each Side)
2.86 mWtC
(Both Sides)
4.3 mWtC

Storage Temperature Range
Lead Temperature
(1/16" from c~se for 10 seconds)

I

SOURCE
ORAIN
GATE

• Superior Tracking Ability

• Low Output Conductance - 90S = 35 J..I.mho Max

I

'F~
T ',:a== ::

TO·71

D,

s,

-6SoC to +12SoC

10·71

WAFER

2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958

2N3954/W
2N3954A/W
2N3955/W
2N3955A/W
2N3956/W
2N3957/W
2N3958/W

DICE
2N3954/D
2N3954A/D
2N3955/D
2N3955A/D
2N3956/D
2N3957/D
2N3958/D

300"C

ELECTRICAL CHARACTERISTICS 125"C unlessoth.,w;se noted)
PARAMETER

2N3955'
2N3955A
2N3956
2N3957
2N3958
2N3954
2N3954A
UNIT
TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
pA VGS
30 V,
-100
100
100
100
-100
100
100
-500
-500
nA VDS ~ 0
TA-125C
-500
-500
-500
-500
-soo

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown
Voltage

-50

VGSloff)

Gate·Source Cutoff
Voltage

-1.0

-50
-4.5

c1.0

-50
-4.5

-1.0

-50
-4.5

-1.0

-50
-4.5

-1.0

-50
-4.5

-1.0

VDS ~ 0
IG ~ I"A

-50
-4.5

-·1.0

V

VGSlf)

Gate·Source Forward
Voltage

VGS

Gate-Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain
Current

~fs

Common·Source Forward 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000
Transconductance
1000
1000
1000
1000
1000
1000
1000

'os

Common·Source Output
Conductance

Ciss·
Crss

-0.5

-4.2
-4.0

-0.5

-50
-250
0.5

5.0

2.0

2.0

2.0

-4.2
-4.0

-0.5

-50
-250
0.5

5.0

-4.2
-4.0

2.0

-OA

5.0

-0.5

-50
-250

-50
-250
0.5

-4.2
-4.0

2.0

0.5

5.0

-4.2
-4.0

2.0

-0.5

-50
-250
0.5

5.0

-4.2
-4.0

-0.5

-50
-250
0.5

5.0

0.5

-4.2
-4.0
pA
nA

5.0

rnA

35

35

35

35

35

Common·Source Input
Capacitance

4.0

4.0

4.0

4.0

4.0

4.0

4.0

Common Source Reverse
Transfer Capacitance

1.2

1.2

1.2

1.2

L2

1.2

1.2

Drain-Gate Capacitance

NF

Common-Source Spot
Noise Figure

IIG1-IG2)

Differential Gate
Current

IOSS1i1OSS2

Drain Saturation Current
Ratio

IVGS1-VGS21

Differential Gate-Source
Voltage



, oo;>s

NOTE SUBSTRATE IS GATE

ABSOLUTE MAXIMUM RATINGS
Reverse Gate·Draln or Gate·Source Voltage
(Note 1) ............................. 30 V
Gate Current ......................... 50 rnA
Total Device Dissipation, Free·Air
(DE1rate 3 mW/·C) . ................. 500 mW
Storage Temperature Range .... - 65 to + 200·C
Lead Temperature
(1/16" from case for 60 seconds) ......... 300·C

G

s

ORDERING INFORMATION
WAFER
2N5018/W
2N5019/W

TO·18
2N5018
2N5019

DICE
2N5018ID
2N5019ID

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N5018

2N5019

Characteristic

S
T
A
T

BVGSS

Gate·Source Breakdown Voltage

IGSS

Gate Reverse Current

10(off)

Drain Cutoff Current

lOGO
BGS(off)
lOSS
VOS(on)
rOS(on)
rds(on)
Ciss

N
A

C rss

M
I

C

Min

Max

30
2

V

-10

2
-10

nA

-10

-10

~A

-2

-2

nA

-3

-3

~A

10

5

V

Gate·Source Cutoff Voltage
Saturation Drain Current
, Orain·Source ON Voltage

IG ; 1 ~A, VOS ; 0
VGS; 15 V, VOS ; 0
VOS = -15 V, VGS - 12 V (2N5018)
150'C

VGS = 7 V (2N5019)
VOG ; -15 V, IS ; 0

Drain Reverse Current

~10

-5
-0.5

mA
-0.5

150'C
VOS= -15V,10; -1~A
VOS; -20V, VGS; 0

V

VGS-O,IO- -6mA(2N5018),
10; -3mA(2N5019)

.

Static Orain·Source ON
Resistance
Drain-Source.ON Resistance
Common·Source Input

D
y

Max

30

I

C

Test Conditions

Unit
Min·

CapaCitance
Common-·Source Reverse

75

150

{J

10; -1 mA, VGS; 0

75

. 150

Il

10=O,VGS;0

45

45

VVOS = -15 V, VGS = 0
t = 1 MHz

pF
10

10

VOS = 0, VGS = 12 V (2N5018),
VGS ; 7 V (2N5019)

Transfer Capacitance

td(on)

Turn·ON Delay Time

15

15

tr

Rise Time

20

75

tdlot!)
tf

Turn·Off Delay Time

15

25

Fall Time

50

100

NOTE 1: Due to symmetrical geometry
these units may be operated
with source and drain leads
interchanged,

f = 1 kHz

VOO; -6V,VGS(on);0

ns

2N5018
2N5019

RL
VGS(off) 10(on)
J2V -6mA 9100
tv -3mA 1.8K Il

INPUT PULSE
RISE TIME < 1 ns
FALL TIME < 1 ns
PULSE WIDTH 100 ns
REPLETION RATE 1 MHz

SAMPLING
SCOPE

1·74

SAMPLING SCOPE
RISE TIME 0.4 ns
INPUT RESISTANCE 10 M[l
INPUT CAPACITANCE 1.5 pF

2N5114·2N5116 JAN,JTX
P·Channel JFET

FEATURES

PIN
CONFIGURATION

• ON Resistance < 75 ohms (2N5114)
• ID(off) < 500 pA
• Switches directly from T2L Lpgic (2N5116)

II

TO·18

,GENERAL DESCRIPTION
Ideal for inverting switching or "Virtual Gnd" switching
into inverting input of Op. Amp. No driver is required and
±10 VAC signals can be handled using only +5V logic (T2L
or CMOS).

o

CHIP
TOPOGRAPliY

ABSOLUTE MAXIMUM RATINGS

~

550S8

@25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Lead Temperature (Soldering,
10 sec time limit)

G,C

,0190

----j

'" ,'~.11iijll~':::·:;

_65°C to +200°C
+200°C

0140

M80

,0037 x ~ 0
.0027
,0025

NOTE: SUBSTRATE IS GATE

Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating

ORDERING INFORMATION

500 mW
3.0 mW/oC

Maximum Voltages & Current
VGS Gate to Source Voltage
VGD Gate to Drain Voltage
IG
Gate Current

30 V
30 V
50 mA

T01S·

WAFER

DICE

2N5114
2N5115
2N5116

2N5114/W
2N5115/W
2N5116/W

2N5114/D
2N5115/D
2N5116/D

"add JAN, JTX to basic part number to specify these devices
(To 18 package only)

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)

-

CHARACTERISTIC

BVGSS

Gate-Source Breakdown Voltage

IGSS

Gate Reverse Current,

IDIOFF)

Drain Cutoff Current

Vp

Gate-Source Pinch-Off Voltage

IDSS

Drain Current at Zero Gate Voltage

VGSSF

Forward Gate-Source Voltage

VDSION)

Drain-Source, ON Voltage

rDS(on)

Static Drain-Source ON Resistance
Small-Signal Drain-Source ON
Resistance
IJan TX only
Common-Source Input
Capacitance
IJan TX only

rds(on)
Ciss
C rss

Common-Source Reverse
Transfer Capacitance

2N5114
MIN
30

MAX

2N5115
MIN
30

MAX

2N5116
MIN
30

MAX

UNIT

500
1.0

500
1.0

500
1.0

V
pA
/lA

-500
-1.0

-500
-1.0

-500
-1.0

pA
/lA

5

10

3

6

1

4

V

-30

-90

-15

-60

-5

-25

rnA

TEST CONDITIONS
IG = 1 /lA, VDS = 0
VGS=20V,VDS=0

2N5114 - 12 V
25'C
VDS = -15 V, VGS= 2N5115 = 7V
2N5116= 5V
VDS = -15 V, ID = -1 nA
2N5114 - -18 V
= 2N5115 = -15 V
VGS = 0, VDS
2N5116 = -15 V
Pulse Test Duration- 2 ms

15Qo'C

-1

-1

-1

V

IG=-l rnA,VDS=O

-1.3

-0.8

-0.6

V

VGS = 0, ID

75
75
75
25
25

100
100
100
25
25

150
150
175
25
27

pF
pF

VDS=-15V,VGS=0,f= 1 MHz

7

7

7

pF

VDS = 0, VGS

n
n
n

2N5114 - -15 rnA
=2N5115=- 7 rnA
2N5116=- 3mA
VGS-O,ID--lmA
VGS = 0" ID = 0, f = 1 kHz

f = 1 MHz

1-75

25 C

lW'C

2N5114 -12 V
= 2N5115 = 7V
2N5116, 5V

O~OlL

2N5114·16, JAN JTX

SWITCHING CHARACTERISTICS (@ 25°C unless otherwise noted)
CHARACTERISTIC
td
tr
toff
tf

D

2N5114

2N5115

2N5116

MAX

MAX
10
20

MAX
12
30
19
50

Turn·ON Delay Time
Rise Time
Turn·OFF Delay Time
Fall Time

6
10

6

8

15

30

TEST CONDITIONS
Voo

2N5115

2N5116

-10V

-6V

-6V

20V

12V

BV

RL

43011

91011

2 KI1

RG

10011

22011

39011

-15mA

-7mA

-3mA

-12V

-7V

-5V

IO(ON)
VIN

Js-f
:§t~~' ' '1"

O.1"F

90%

V,N

.-. I,

04-

90%

_ 6V

10%

10%

~~~~JI~EEs~si~~CE

4.0

4.0

3.0

3.0

~
>

=

Vos
O.1V
VGS = 0

1\

'.0
0 .•
0 .•
0.7
0 .•
O.S

30

'0

100

7.5K<'

S
,.2K

SAMPLING SCOPE

UNIT

~ VCD

l~M

-=-r
>

:e-

_I,

10.0
•.0
•.0
7.0
•.0

2.0

.>

510

Vos(ON)

OUTPUT

~
>"

JAN TX
2N55115
MAX
10
20

INPUT

2N5114
VGG

JAN TX
2N5116
MAX
25
6
35
10
8
29
6
(not JAN TX specified)

JAN TX
2N5114
MAX

. 4.0

L
/vos

Vos = 20V
VGS = 0

>"

VGS "" 0

20

j

3.0

€

= 20V

2.0

(pulsed)

(pulsed)

,/
'.0
0 .•
0 .•
0.7
0 .•
0.5

300

1.000

1

3

10

100

30

'.0
0 .•
0 .•
0.7
0 .•
O.S
1,000

3,000

loss (mA)

rOS(ON) (ohms)

10,000

30,000

100,000

Ors (p.v)

JAN TX and JAN TX V Processing
PRODUCTION

1. Raw Material
2. Factory Processing

-T----T---

+

PRE-CAP VISUAL
INSPECTION FOR
JAN TXV LOTS

+

I NSPECTION LOTS
FORMED AFTER
FINAL ASSEMBLY
OPERATION
(SEALING)

--

LOTS PROPOSED
FOR
TX OR TXV
TYPES

TXV PROCESSING REQUIRES
VISUAL INSPECTION BEFORE
FINAL ASSEMBLY; PLEASE
CONSULT THE FACTORY FOR
ORDERING INFORMATION.

I
100% POWER BURN-IN
1. Measurement of specified

100% PROCESS CONDITIONING

L........-

1.
2.
3.
4.

High·temp. storage
Temp_.Cycling (thermal shock)
Acceleration (centrifugal)
Hermetic·seal test(s)

r-

parameters
2. Burn·in
3. Measurement of spepified
parameter to determine
delta(L)
4. Lot evaluation

r--

INSPECTION
TO VERI FY
GROUP
GROUP
GROUP

TESTS
LTPD
A
B
C

r--

REVIEW OF
GROUPS A, B, C
DATA FOR
ACCEPT OR REJ ECT

~.

I

PREPARATION
FOR
DELIVERY

1·76

2N5117·2N5119
Dual Monolithic PNP
Transi'stor
ABSOLUTE MAXIMUM RATINGS (25°C unless otherwise noted) (Note 1)
Dissipation at 25°C Case Temperature
Each side (Note 1)
Both sides
Derating Factor
Each side
Both sides
Voltage
Collector to Base
Collector to Emitter
Emitter to Base (Note 2)
Collector to Collector
Collector Current
Storage Temperature
Lead Temperature for 10 Seconds

PIN
CONFIGURATION
TO·7S

O,4W
O,75W

2,3mW/'C
4,3mW/'C

CHIP
TOPOGRAPHY

45V
45V
7,OV
100V

c,

4503

:g:~x:=~

-T~CO;;:l~LE~C:;;TO~R;-:-;",~• •i=iii3----"'''':''ISOlATION
COLLECTOR
a?~

=2 TYP. 2 PLACES

:~It:~~
!'
-'-_____ "...+--'\-.J
0270

10mA
-65 to +200'C
+300'C

BASE =2 TYP, 2 PLACES

'::~ OIA~ETER

BASE =1

EMITTER =2
0040
TYP. 2 PLACES. 0030
DIAMETER

EMITTER :;;1

ORDERING INFORMATION
TO·78

WAFER

DICE

2N5117
2N5118
2N5119

2N5117/W
2N5118/W
2N5119/W

2N5117/D
2N5118/D
2N5119/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N5117
2N5118
MIN
MAX

PARAMETER

2N5119
MIN

TEST CONDITIONS

UNIT

MAX

hFE

DC Current Gain
DC Current Gain

hFE

DC Current Gain (_55°C)

ICBO

Collector Cutoff Current

0.1

Q.l

nA

IE-O,VCB=30V

ICBO

Collector Cutoff Current (l50°C)

O.l

0.1

p.A

IE=O,VCB=30V

lEBO
IC1-C2
GBW

Emitter Cutoff Current

0.1

0.1

nA

IC = 0, VEB = 5.Q V

Coliector·Collector Leakage
Current Gain Bandwith Product
Output Capacitance

5.0

5.0

pA

VCC= 100V

0.8

0.8

MHz
pF

1.0

1.0

pF

IC = 0, VEB - 0.5 V

0.8

0.8

pF

Vec= 0
IC = 1.0 rnA, IB = 0

4.0

dB

IC-l0p.A, VCE =5.0V
BW = 200Hz'

hFE

Cob
C te
VCEO(,ustl
NF

Narrow Band Noise Figure

V(BR)CBO

Collector Base Breakdown Voltage.
Emitter Base Breakdown Voltage

V(BR)EBO

IC = 10 p.A, VCE = 5.0 V

50

IC = 500 p.A, VCE - 5.0 V

30

20

300

100

Emitter Transition Capacitance
Collector-Collector Capacitance
Collector-Emitter Sustaining Voltage

CC1,C2

50

100

100

IC = 10 p.A, VCE = 5.0 V

100

45

45
4.0

V

IC = 500 p.A, VeE = 10 V
IE = 0, VCB = 5.0 V

45

45

V

IC= 10p.A,IE=0

7.0

7.0

V

IE= 10p.A,IC-0

I'

= 1 KHz, RG = 10 K!"!

MATCHING CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
hFE1/hFE2
VBE1-VBE2

DC Current Gain Ratio
(Note 3)
Base·Emitter Voltage
Differential
Base Current Differential

2N5117
MIN MAX
0.9

2N5118
MIN MAX

2N5119
MIN MAX

0.85

1.0

0.8

IC = 10 "A to 500 p.A, VCE = 5 V
IC = 10 p.A, VCE = 5.0 V

1.0
mV

3.0
5.0

5.0

TEST CONDITIONS .

UNIT

1.0

IC = 10 p.A to 500 p.A, VCE = 5 V
Ie = 10 p.A, VCE =5.0 V

=5.0 V

10.0

15

40

nA

.:I.(VBE1-VBE2)

Base Voltage Differential
Change with Temperature

3.0

5.0

10

p.V/oC

IC = 10 p.A, VCE = 5.0 V

TA = _55°C to+125°C

.:I.(l Bl-IB2)

Base·Current Differential
Change with Temperature

0.3

0.5

1.0

nAtC

IC = 10 p.A, VCE = 5.0 V

TA = _55°C to +125°C

IB1-IB2

IC = IOp.A, VCE

1. Ma)umum ratings are limiting values above which devices may be damaged. These ratings give a maximum Junction temperature of 200 C.
2. The reverse base·lo·emitter voltage must never exceed 7.0 volts and the reverse base·to.emitter current must never exceed Hi IlA.
3. Lower of two hFE readings is defined as hFE1'

1·77

III

D

2N5196·2N5199
Monolithic Dual
N·ChanneIJFET
ABSOLUTE MAXIMUM RATINGS (Note 1)
@

25°C (unless otherwise noted)

Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Lead Temperature (Soldering,'
10 sec. time limit)

PIN
CONFI~URATION

-65°C to +200°C
+150°C'

6017

TO·71

f-,--.023 ±.a02

I

.020 G,

52

I::
3
3
3

SOURCE

~

S2~
01

O2

U

'---I

~"
T

~

Maximum Power Dissipation
Device Dissipation @ 85°C Free Air Temperature
One Side
•
250 mW
Both Sides
, 500 mW
Linear Derating
One Side
2.56mwfc
Both Sides
4.3mWfC
Maximum Voltages & Currents.
VGS Gate to Source Voltage
V GD Gate to Drain Voltage
IG 'Gate Current

-

CHIP
TOPOGRAPHY

DRAIN
GATE

It
It

It

6MIL
3 Mil
3 MIL

S1

D1

ORDERING INFORMATION
TO;71
2N5196
2N5197
2N5198
2N5199

-50 V
-50 V
50mA

WAFER

DICE

2N5196/W
2N5197/W
2N5198/W
2N5199/W

2N5196/D
2N5197/D

2N5198/D
2N5199/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
MIN

PARAMETER

MAX
-25
":50

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

-0.7

-4

VGS

Gate-Source Voltage

-0.2

-3.B

V

VOS = 20 V, 10 = 1 nA

-15

pA

VOG = 20V,IO = 200J1A

-15

nA

0.7

7

mA

lOSS
gl.

Saturation Drain Current (Note 1)
Common-Source Forward Transconductance (Note 1)

1000

4000

gl.

Common-Source Forward Tran.conductance (Note 1)

700

1500

go.

Common-Source Output Conductance

go.

Common-Source Output Co"nductance

Ciss

Common-Source Input Capacitance

6

Common-Source Reverse Transfer Capacitance'

2

NF

Spot Noi.e Figure

en

Equivalent Input Noi.eVoltage

IIGHG21

Differential Gate Current

I DSS 11 I DSS2

Saturation Drain Current ,Ratio
(Note 1)

0.95

gl.1/ 91.2

Transconductance Ratio
(Note 1)

0.97

IVGS1-VGS21

Differential Gate-Source Voltage

llIVGS1-V GS21
llT

Gate-Source Differential Voltage
Change with Temperature
(Note 2)

Igo.l-go.21

Differential Output Conductance

NOTE:

MAX

MAX

5

MIN

1

0.95

1

0.97

1

0.95

1

0.95

VDS=20V,VGS=0
VDG = 20 V,ID = 200J1A
VDS=20V,VGS=0

dB

VDS=20V,VGS=0

J1
2N5199

MAX

MIN

1

0.95

1

0.95

1 = 100 Hz,
RG=10MU
1= 1 kHz

..;HZ
MAX

UNIT

TEST CONDITIONS

5

nA

VDG =20V,
ID = 200J1A

1

-

VDS = 20 V, VGS =0 V

1

-

'5

10

15

mV

5

10

20

40
J1vtc

5

10

20

40

1

1

1

1

1·78

1 = 1 kHz

1 = 1 MHz

5

1. Pulse test required, pulsewldth = 300 IJS, duty cycle" 3%.
2. Measured at end points, TA and TB.

I

pF

5

5

"

VDG = 20V,ID = 200J1A

0.020
20
2N519B

2N5197
MIN

I 150°C

I 125°C

J1mho

0.5

2N5196

-I

VDS=20V,VGS=0

50
4

Cr••

MIN

TEST CONDITIONS
VGS = -30 V. VOS = 0
IG=-IJ1A.VOS=O

Gate Operating Current

,

nA

-50

IG

PARAMETER

UNIT
pA

J1mho

125°C

'I = 1 kHz

VDG=20V,
ID = 200J1A

TA = 25°C
TB = 125'C .
TA = _55°C
TB = 25°C
1 ~ 1 kHz

2N5397,2N5398
N·Channel JFET
FEATURES
•

Gps

= 10 dB Typical (Common Gate) at 450 MHz

• NF = 3.5 dB Typical'at 450 MHz

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·72

5011

• Crss = 1 pF Typical

~'~!~--l.

I

G

o

300°C
300mW
1.7 mW/C

Maximum Voltages & Current
VGS Gate to Source Voltage
VGD Gate to Drain Voltage
IG
Gate Current

PARAMETER

BVGSS
VGS(off)
lOSS
VGS(f)

Gate·Source Breakdown Voltage
Gate·Source Cutoff Voltage

gfs
goss

Saturation Drain Current

-25 V
-25 V
10 mA

Common-Source Forward

Ciss

Common·Source Input Capacitance

9iss

Common·Source Input
Conductance

Gps
NF
Note 1:

-25
-1.0
10
6000

Pulse test duration

MIN

MAX

MAX
-0.1
-0.1

-25

- La
5

-6.0
40
1

5500

10,000

-6.0
30
1
10,000
200

1.3
5.0

nA

J1A
V
mA
V

J1.mho

,

pF

3000

400
500

J1mho

9000
5000

WAFER
2N5397/W
2N5398/W

DICE
2N5397/D
2N53981D

TEST CONDITIONS
V GS

= -

15 V, V DS =

a

VOS = 0, IG - -1 J1A
V DS - 10 V, ID - 1 nA
VOS - 10 V, VOS VOS - 0, IG - 1 mA
VOS - 10V, 10 - 10 mA
VOS=10V,VGS=0
VOS - 10 V, 10 - ·10 mA
VOS = 10V, Vr,e; =
VOS -10 V, 10 - 10 mA
Voe; = 10V, Vr,e; =0
VOG = 10 V, (0 = 10 rnA
VOS= 10V,Vr,c;=0
VOG - 10 V, 10 - 10 mA
VOG = 10 V, VGS=O
VDG - 10 V, ID = 10 mA
VOS =10 V, VGS =
VOG = 10 V, 10 = 10 mA
VOS = 10 V, VGS =

I

= 2m.
1·79

I
150 C

a

f = 1 kHz

a

10,000

dB

f = 1 MHz

a

15
3,5

00305

a

5.5

5500

0025

UNIT

400

2000

5 O,!~ x ,_!!Q40~

~s

1.2

Common-Source Output

Conductance
Common-:,Source Forward
Transconductance (Note 1)
Common-Source Power Gain
(neutralized)
Common·Source, Spot Noise
Figure (neutralized)

c

TO·72
2N5397
2N5398

-0.1
-0.1

Transconductance (Note 1)
Common·Source Output
Conductance

Common-Source Reverse Transfer
Capacitance

9fs

MIN

Gate·Source Forward Voltage

Crss

goss

0032

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
,
2N5398
2N5397
Gate Reverse Current

0025

~
-65°C to +200°C
+200°C

Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Li near Derati ng

IGSS

SUBSTRATflSGATE

,O.!.QQ
.
0140

25°C (unless otherwise noted)

Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Lead Temperature (Soldering,
10 sec·time limit)

NOTE

T~DOO"XOO"

ABSOLUTE MAXIMUM RATINGS
@

I'

0170

VaG = 10 V, 10 = H) mA

f = 450 MHz

II

2N5432·2N5434
N·ChanneIJFET
FEATURES
• r ds (on) < 5 ohms
• Excellent Switching Low Cutoff Current -

ton < 4 ns
toff < 6 ns
ID(off) < 200 pA

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO 52

5018
0036
X :0026

r
.0250

0290

I

ABSOLUTE MAXIMUM RATINGS
@25°C (unless otherwise noted)

L~

Maximum Temperatures
Storage Temperature
+200°C
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec time limit) +260°C
Maximum Power Dissipation
Device Dissipation @ Free Air Temperature
Linear Derating

SUBSTRATE IS GATE

003§ X 003~

S

0025

0025

ORDERING INFORMATION
300mW
2.3 rilW/oC

Maximum Voltages & Current
V GS Gate to Source Voltage
V GD Gate to Drain Voltage
Gate Current
IG
ID
Drain Current

-25 V '-25 V
100mA
400mA

TO·52

WAFER

DICE

2N5432
2N5433
2N5434

2N5432/W
2N5433/W
2N5434/W

2N5432/D
2N5433/D
2N5434/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
2N5432
MIN
MAX
-200
-200
-25
200
200
-4
-10

CHARACTERISTIC
IGSS

Gate Reverse Current

BVGSS

Gate Source Breakdown Voltage

10(~1f)

Drain Cutoff Current

VGSloifi

Gate-Source Cutoff Voltage
Saturation Drain Current
(Note 11
Static Drain-Source ON Resistance
Drain-Source ON Voltage

lOSS
rOS(onl
VOS(on)
rds(on)
Ciss
Crss

td
tr
toft
tl

150
2

Drain-Source ON Resistance
Common-Source Input Capacitance
Common-Source Reverse Transfer
Capacitance
Turn-ON Oelay Time

Rise Time
Turn-OFF Oelay Time
Fall Time

2N5433
MAX
-200
-200
-25
200
200
-9
-3

MIN

100

2N5434
MAX
-200
-200
-25
200
200
-4
-1

MIN

30

5
50.
5
30

7
70
7
30 '

15

15

15

4
1
6
30

4

4

1

1

10
100
10
30

6

6

30

30

UNIT
pA
nA
V
pA
nA
V

son

S

RISE TIME 025 ns
FALL TIME 0 75
PULSE WIDTH 200 ns
PULSE RATE 550 pps

1·80

150'C

IG - -lilA. VOS - 0
VOS=5V,VGS=-10V

150'C

VOS=5V,10=3nA

rnA

VOS = 15 V, V GS = 0

VGS=O,IO=O

1-1 kHz

pF

VOS=0,VGS=-10V

1=1 MHz

ns

VOO-l.5V,
VGS(on) = 0,
VGS(oft) = -12 V,
10(onl = 10 mA

VDD

RG

VGS=-15V.VOS=0

ohm
mV
ohm

NOTE: 1. Pulse test required pulsewldth 300 J.1s, duty cycle";;; 3%.

V'N ~RLvov::~~g~:~:~UT PULSE

TEST CONDITIONS

SAMPLING SCOPE
RISE TIME 0.4 ns
INPUT RESISTANCE 10M
INPUT CAPACITANCE 1.5 pF

VGS = 0, 10 = 10 rnA

2N5452-2N5454
Monolithic Dual
N-Cha'nnel JFET

FEATURES
• Offset Voltage 5 mV
• Drift 51lVfC
• Low Capacitance
• Low Output Conductance - 1 Ilmho Max

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO·71

6017

GENERAL DESCRIPTION
Matched FET pairs for differential amplifiers. This family
of general purpose FETs is characterized for .Iow and
medium freCJuency differenti~1 amplifier appl ications
requiring. low drift and low offset voltage.

ABSOLUTE MAXIMUM RATINGS
@

SOURCE
ORAIN
GATE

25° C (unless otherwise noted)

Maximum Temperatures
-65°C to +200°C
Storage Temperature
+150°C
Operating .Junction Temperature
Lead Temperature (Soldering,
10 se.c. time limit)
+300°C
Maximum Power Dissipation
Device Dissipation @ 85°C Free Air Temperature
One Side
250 mW
Both Sides
500 mW
Linear Derating
One Side
2.86mWtC
Both Sides
4.3 mWfC
Maximum Voltages & Currents
-50 V
VGS Gate to Source Voltage
-50 V
V GO Gate to Drain Voltage

3 ~ 6 Mil
3. JMll
J.JMll

ORDERING INFORMATION
TO·71
2N5452
2N5453
2N5454

DICE
2N5452/D
2N5453/D
2N5454/D

WAFER
2N5452/W
2N5453/W
2N5454/W

ELECTRICAL CHARACTERISTICS (25°C unle .. otherwi.e noted)
PARAMETER
IGSS'
BVGSS
VGS(off)
VGS
VGS(t)
lOSS
9fs
90.

Ciss
Crss
Cd90
en

NF
IOSSl/10SS2
IVGS1-VGS21·

2N5452
MIN
MAX
-100
-200

Gat!! Reverse Current
Gate-Source Breakdown
Voltage
Gate-Source Cutoff Voltage

Gate-Source Voltage
Gate-Source, Forward Voltage
Saturation Drain Current

Common-Source Forward

Transconductance
Common-Source Output

-50
-1
-0.2
0.5
1000
1000

Conductance
Common-Source Input

Capacitance
Transfer Capacitance
Drain-Gate Capacitance
Equivalent Short Circuit
Input Noise Voltage
Common-Source Spot
Noise FiQure

-1
-0.2
0.5
1000
1000

UNITS

-100.
-200

pA
nA

-4.5
-q.<
2
5.0
3000

V

-50
-4.5
-q.<
2
5.0
3000

-1
-u.<
0.5
1000
1000

TEST CONDITIONS
VGS = -30 V, VOS = 0

I
ITA-150C

VOS=O,IG=-l/JA

3.0
1.0

3.0
1.0

3.0
1.0'

4.0

4.0

4.0

1.2

1.2

1.2

1.5

1.5

1.5

20

20

20

0.5
0.95

Voltage

Gate-Source Voltage
AIVGS1-V GS21 Differential Change with
Temperature
Transconductance Ratio
9f.l/9fs2
UI erentla uutput
190.1-90.21
Conductance

-100
-200
-50

-4.5
-4.2
2
5.0
3000

2N5454
MIN
MAX

mA
.umho

VOS 20V,IO-l nA
VOS=2UV,0 'bU/JA
VOS=O,IG=lmA
VOS = 20 V, VGS • U
'VOS=20V, VGS=O
VOS·= 20 V, 10

200/JA

f 1 kHz
f - 100 MHz
f= 1 kHz

VOS = 20 V, VGS = 0

Common-Source Reverse

Drain Saturation Current Ratio
Differential Gate-Source

2N5453
MIN
MAX

0.97

1.0

0.5
0.95

1.0

0.5
0.95

10.0

15.0

0.4
0.5'

0.8
1.0

2.0
2.5

1.0
0.25

0.97

1.0
0.25

1-81

0.95

VOG =:10 V, IS = 0
nV

y'R'Z
dB

1.0

5.0

f= 1 MHz

pF

VOS=20V,VGS=0
VOS 20 V, VGS = 0
RG= 10Mn
VOS=20V,VGS-0

mV
VOS= 20 V, 10 = 200/JA

f = 1 kHz
f = 100 Hz

T = 25°C to _55°C
T=25 Cto+125 C

1.0
0.25

pmhos

f = 1 kHz

II

2N5457·2N5459
N·Channel JFET
ABSOLUTE MAXIMUM RATINGS
(25°C unless otherwise no!ed)

PIN
CONFIGURATION

VDG

Drain-Source Voltage ........................... 25V
Drain-Gate Voltage .-............................ 25V

VGS(r)

Reverse Gate-Source Voltage ............. _. . . . . .. 25V

VDS

D:~D

CHIP
TOPOGRAPHY

TO·92

5010
0(2)

~
,

Gate Current ................................. 10mA
Sill

Total Device Dissipation @TA = 25°C .......... 310mW

~~~~x ~~~

Derate above 25°C ....................... 2.82mW/oC
Storage Temperature Range ........... - 65 to

Wl'r'~

~ '"oo.~
"1'i05o

Operating Junction Temperature ................ 135°C

+ 150°C

::::~FUC,"

T

~

'NOTE· SUBSTRA, H
tSCATE

']15

o

S

G

ORDERING INFORMATION
TO-92
2N5457
2N5458
2N5459

WAFER
2N5457/W
2N5458/W
2N5459/W

DICE
2N5457ID
2N5458ID
2N5459/D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
PARAMETER
OFF CHARACTERISTICS
' Gate-Source Breakdown Voltage
BVGSS
IGSS

Gate Reverse Current

VGS(olf)

Gate·Source Cutoll Voltage

VGS

Gate·Source Voltage

MIN

TYP

-25

-60
.05

-0,5
-1.0
-2.0

MAX

UNITS
V

TEST CONDITIONS
IG=-10"A.VDS=0
VGS= -15 V, VDS - 0
VGS = -15 V, VDS = 0, TA = 100°C

-1.0
-200

nA

-6.0
-7.0
-8.0

V

VDS=15V,ID=10nA

V

VDS-15 V, 10 - 100"A
VDS = 15 V, 10 = 200"A
VOS = 15 V, 10 = 400"A

mA

VOS=15V,VGS=0

2N5457
2N5458
2N5459

"mho

VDS = 15 V, VGS = 0,1= 1 kHz

2N5457
2N5458
2N5459

"mho
pF
pF

VOS = 15 V, VGS = 0, 1=1 kHz
VOS-15V, VGS-O,I-l MHz
VOS 15 V, VGS 0, I 1 MHz

2.5
3.5
4.5

2N5457
2N5458
2N5459
2N5457
2N5458
2N5459

ON CHARACTERISTICS
lOSS

Zero·Gate·Voltage Orain
Current

1.0
2.0
4.0

3.0
6.0
9.0

5.0
9.0
16

1000
1500
2000

3000
4000
4500
10
4.5
1.5

5000
5500
6000
50
7.0
3.0

OYNAMIC CHARACTERISTICS
IVlsl

Forward Transler Admittance

IVosl
Ciss
Crss

Output Admittance
I nput Capacitance
Reverse Transfer Capacitance

1-82

2N5460· 2N5465
P·Channel JFET
PIN
CON FIG URATION
TO:92

II
o

G

CHIP
TOPOGRAPHY

MAXIMUM RATINGS
SYMBOL

RATING
Drain-Gate Voltage
Reverse Gate-Source Voltage
Forward Gate Current
Total Device Dissipation @ T A = 25°C
Derate above 25° C
Storage Temperature Range
Operating Junction Temperature Range

ELECTRICAL CHARACTERISTICS

VDG
VGS(r)
IGIIl

2N5460
2N5461
2N5462
40
40

2N5463
2N5464
2N5465
60
60

10
310
2.82
-65 to +150
-65 to +135

PD
Tsto
TJ

UNITS
Vdc
Vdc
mAdc
mW
mWfC
°c
C

ORDERING INFORMATION

TO·92

WAFER

DICE

2N5460
2N5461
2N5462
2N5463
2N5464
2N5465

2N5460/W
2N5461/W
2N5462/W
2N5463/W
2N5464/W
2N5465/W

2N54601D
2N5461/D
2N5462/D
2N5463/D
2N5464/D
2N5465/D

,

(25°C unless otherwise notedl

PARAMETER
V(BRIGSS

Gate-Source Breakdown Voltage

VGS(offl

Gate-Source Culoff Voltage

IGSS

Gate Reverse Current

MIN

TYP

40
60
0.75
1.0
1.8

MAX

6.0
7.5
9.0
5.0
5.0
1.0
1.0

UNITS

TEST CONDITIONS
~

Vde

IG

Vde

VOS

na
na
pAde

na

10 pAde. VOS

~

15 Vde. 10

VGS ~ 20
VGS ~ 30
VGS ~ 20
VGS ~ 30

Vde,
Vde,
Vde,
Vde,

~

~

0

1.0 pAde

VOS ~ 0
VOS ~ 0
VOS = 0, T A = 100'C
VOS ~ O. TA ~ 100'C

2N5460.
2N5463.
2N5460,
2N5461,
2N5462.
2N5460,
2N5463,
2N5460,
2N5463',

2N5461.
2N5464.
2N5463
2N5464
2N5465
2N5461,
2N5464,
2N5461,
2N5464,

2N5460,
2N5461,
2N5462,
2N5460,
2N5461,
2N5462,

2N5463
2N5464
2N5465
2N5463
2N5464
2N5465

2N5462
2N5465

2N5462
2N5465
2N5462
2N5465

ON CHARACTERISTICS
lOSS

. VGS

Zero-Gate Voltage Drain Current

Gate-Source Voltage

1.0
2.0
4.0
0.5
0.8
1.5

5.0
9.0
16
4.0
4.5
6.0

1000
1500
2000
5.0
1.0
1.0

4000
5000
6000
75
7
2.0
2.5

60

115

mAde

VOS

~

15 Vde, VGS

VOS
VOS
VOS

~

Vde

~

15 Vde, 10 - 0.1 mAde
15 Vde, 10 ~ 0.2 mAde
15 Vde, 10 = 0.4 mAde

,umhos

VOS

~

15 Vde. VGS

pmhos
pF
pF
dB
nVI

VOS VOS VOS Vns -

~

~

0

SMALL-SIGNAL CHARACTERISTICS

Qls

Forward Transadmittance

90S

Output Admittance
Input Capacitance

Ciss
C rss
NF

en

Reverse Transfer Capacitance
Common-Source Noise FiQure

Equivalent Short-Circuit Input
Noise Voltage

v'HZ

1·83

VOS

~

15 Vde,
15 Vde,
15 Vde,
15 Vde,

~

O. f = 1.0 kHz

2N5460, 2N5463
2N5461, 2N5464
2N5462, 2N5465

VGS - 0, f - 1.0 kHz
VGS - 0, f - 1.0 MHz
VGS 0, f 1.0 MHz
Vr.s - 0, Rr. -1.0 Megohm, f -100 Hz, BW - 1.0 Hz

15 Vde, VGS

~

0, f

~

100 Hz. BW

~

1.0 Hz

2N5484·2N5486
N·ChanneIJFET
FEATURES

PIN
CONFIGURATION

• Specified for 400 MHz Operation

TO-92

• Can Be Used as a Low Capacitance Switch

II

•

Economy Packaging

•

C rss

q

< 1.0 pF

t-

ABSOLUTE MAXIMUM RATINGS
Drain-Gate Voltage
Source Gate Voltage
Drain Current
Forward Gate Current
Total Device Dissipation @ 25°C
Derate above 25° C
Operating Junction Temperature Range
Storage Temperature Range

o

25 V
25 V
30mA
10mA
310 mW
2_82 mwtC
_65°C to +150°C
-65°C to +1 50°C

S

G

CHIP
TOPOGRAPHY
~6~;

I

5000
FULL R \

T \. ~j D"~~S'~ T

E_OO35X..!!.!!li
0025
0025

'Oi3

~"62~
"'iiii66

NOTE

SUBSTRATE
IS GATE

'"

ill

ORDERING INFORMATION
TO-92
2N5484
2N5485
2N5486

WAFER
2N5484/W
2N5485/W
2N5486/W

DICE
2N54841D
2N54851D
2N54861D

ELECTRICAL CHARACTERISTICS (25·C unless otherwise noted)
PARAMETER
IGSS

Gate Reverse Current

BVGSS
VGS(olfl
lOSS

Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current
Common-Source Forward
Transconductance

91s

Re(vosl
Rt:!(Yis)

Coss
NF

2N5486
MIN
MAX

-1.0
200

-1.0
200

-1.0
-200

-25
-0.3
1.0
3000

<

Common-Source Forward
Transconductance

-3.0
5.0

-25
-0.5
4.0

6000

3500

50

Conductance

Re(yfs)

Crss

2N5485
MIN
MAX

Common-Source Output

/ 90S

Ciss'

2N5484
MIN
MAX

I

-4.0
10

-25
-2.0
8.0

-6.0
20

7000

4000

8000

V
mA

VGS = -20 V, VDS = 0

3000

- +100·C

75
3500

,umhos

100

100

1000

1000

5.0

5.0

5.0

1.0

1.0

1.0

VOS = 15 V, VGS = O·

100

2.0

2.0

2.0

2.5
3.0

2.5

2.5

4.0

4.0

25
18
10

T

IG - -1 "A, VDS - 0
VOS 15V,IO 10 nA
VOS 15 V, VGS = U INote
f'" 1 kHz

60

75

Noise Figure

' Common-Source Power Gain

nA

TEST CONDITIONS

2500

Common-Source Output
Conductance
Common-Source Input
Conductance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance
Common-Source Output
Capacitance

.16
Gps

UNiTS

30
20

18
10

1-84

30
20

pF

f'" 1 MHz

VOS - 15 V, VGS - 0, AG = 1 Mil
VOS - 15 V, Ib- 1 mA, AG -. 1 kll
VOS
dB

f-l00MHz
f - 400 MHz
f - 100 MHz
f - 400 MHz
f-l00MHz
f - 400 MHz

= 15 V,

10 - 4 mA, RG - 1 kll

VOS-15V,IO-l mA
VOS

15 V,IO

4 mA

f

1 kHz

f 100 MHz
f -400 MHz
f

100 MHz

1= 400 MHz

,

2N5515·2N5524
Monolithic Dual
N·Channel

JFET
ABSOLUTE MAXIMUM RATINGS (Note 1)
PIN
CONFIGURATION

@25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Maximum Power Dissipation
Device Dissipation
@ Free Air Temperature
Linear Derating

II

TO-71

ONE SIDE
250mW
85°C

BOTH SIDES
500mW
B5°C

3.85 mWfC

7.7 mWfC

Maximum Voltages & Current
-40 V
-40 V
50 rnA

V GS Gate to Source Voltage
VGD Gate to Drain Voltage
IG Gate Current

CHIP
TOPOGRAPHY
(2N5520-24)
D,

~--i
G']'
'I
It

"FEATURES
• Tight Temperature Tracking':'" I:!. VGS < 5 p.V

tc

.025

I

6017

,

r--01J:!:,001~
5, .0035."""
.0025 X .0070
TYP. 2 PLACES

.0037,.003'
-:[G2 .1);)27
0027
TVP. 2 PLACES
02 0035 x·OO35

==w

E~s'

'Ts,~:;

~~2 p~~~~s

$2

sounCI 3. r,MIl
DRAIN

GAH

• High Common Mode-Rejection - CMRR < 100 db
•

•

~

• Tight MatchingVGS <5 mV
IG < 10 nA@ 125°C
!Its <3%
g~ss < .1 p.mho

(2N5515-19)

.

6019

ORDERIN'G INFORMATION

LowNoise-.e n <15nV/YHz@10Hz

TO-72
2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
2N5525

Nl5

WAFER

DICE

2N5515/W
2N5516/W
2N5517/W
2N5518/W
2N5519/W
2N5520/W
2N5521/W
2N5522/W
2N5523/W
2N5524/W
2N5525/W

2N55151D
2N55161D
2N55171D
2N55181D
2N5519/D
2N5520/D
2N55211D
2N5522/D
2N55231D
2N5524/D
2N5525/d

J,:UIH

2N5515 thru 2N5524
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
MIN

PARAMETER
(+ 25 C)
Gate Reverse Current
(+·15o. o C)
Gate-Source Breakdown Voltage
Gate-Source Pinch-Off Voltage
Orain Current at Zero Gate Voltage (Note 2)
Common-Source Forward Transconductance
(Note 2)
Common-Source Output Conductance
Common-Source Reverse Transfer
Capacitance
Common-Source Input Capacitance
2N5515-19
2N552o.-24
Equivalent Input Noise Voltage
2N5515-24
(+ 25 C)
Gate Current
(+125°C)
Gate Source Voltage
Common-Source Forward Transconductance
(Note 2)
Common-Source Output Conductance

IGSS
BVGSS
Vp
\
. lOSS
9fs

D

goss
Crss
Ciss
,

en
IG
VGS
9fs
goss'

-40.
-0..7
0..5 .

MAX
-250.
-250.
-4
7.5

UNITS
pA
nA ,
V
V
rnA

TEST CONDITIONS
VGS= -30. V, VOS=o.
IG = 1 }J.A, VOS = 0.
VOS 'ZUV,IO ,iiil\
VOS - 20. V, VGS - 0.

400.0.

}J.mho

VOS=2o.V,VGS=o.

f = 1 kHz

10.

}J.mho

VOS- 20. V, VGS-o.

f - 1 kHz

5

pF

VOS= 20. V, VGS=o.

f = 1 MHz

pF
nV/y!!z
nV/y'Hz

nV/$z

VOS-2o.V,VGS-o.
VOG - 20. V, 10 - 2o.o.}J.A
VOG = 20. V, 10 = 2o.o.}J.A
VOG = 20. V, 10 = 2o.o.}J.A

f 1 Mffz
f - 10. Hz
f = 10. Hz
f = 1 kHz

-0..2

25
30.
15
10.
-10.0.
-10.0.
-3.8

50.0.

100.0.

}J.mho·

VOG = 20V, 10 = 2o.o.}J.A

1

}J.mho

VOG - 20. V, 10 - 2o.o.}J.A

100.0.

!

pA
nA
V

VOG = 20. V, 10 = 2o.o.}J.A
VOG = 20. V, 10 = 2o.o.}J.A
f = 1 kHz

MATCHI~G CHARACTERISTICS (2SoC unless otherwise noted)
PARAMETER
IOSSI
IOSS2
IIGl -IG21
91,1
9fs2

Drain Current Ratio at

2N5515,20
MIN
MAX
0.95
1

2N5516,21
MIN
MAX
0.95
1

2N5517,22
MIN
MAX
0.95
1

2N5518,23
MIN
MAX
0.95
1

2N5519,24
MIN
MAX
0.90
1

Differential Gate CUrrent

10

1+125°C)
0.97

1

10
0.97

1

10
0.95 .

1

0.95

10
,1

10
0.90

.l>IVGSl - VGS21
.l>T

Differential Output
Conductance

Differential ~ate·Source
Voltage
Gate-Source Voltage Differential Drift ITA = +2SoC to

+125°C)
Gate-Source Voltage DifferITA = +25 to

.l>IVGSl - VGS21 entia I Drift
.l>T
·_55°C)
;

CMRR

Common Mode Rejection
Ratio (Note 3)

nA

VOG = 20 V, 10 = 200~A

-

VOG = 20 V.IO = 200~""
1=1 KHz
VOG-20V.10 200~A
1= 1 KHz

1

INote 2)

IVGSI -VGS21

TEST CONOITIONS
VOS = 20 V. VGS = 0

Zero Gate Voltage (Note 2)

Transconductance Ratio

./905S1 - 905521

UNIT

0.1

0.1

0.1

0.1

0.1

5

5

10

15'

15

~V

VOG = 20 V.IO = 200~A

5·

10

20

40

80

~vfc

VOG = 20 V.IO = 200~A

5

10

20

40

80

~vfc

VOG = 20 V.IO = 200~A

100

100

90

NOTES:
1. The'se ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
.
•
2. Pulse duration of 28mS used during test.

3. CMRR = 20L0910VOO/IVGSl - VGS21.I.I>VOO = 10V) .

1-86

~mho

dB

VOO = 10 to 20 V. 10 = 200~A

D~DlL

2N5564·2N5566
DualN~ChannelJFET

FEATURES
• Specified Matching Characteristics
!' High Gain. 7500/Lmho Minimum
• Low "ON" Resistance - 100{) Maximum

PIN.
CONFIGURATION

CHIP
TOPOGRAPHY

TO-71

6033

II

ABSOLUTE MAXIMUM RATINGS
(25°C unless otherwise noted)
. Gate-Gate Voltage ........... _......... _......... " ± 80V
Gate-Drain or Gate~Source Voltage. . . . . . . . . . . . . . .. - 40V
Gate Current. ..................................... 50mA
Device Dissipation (Each Side), T A 25'C
(Derate 2.2 mWI 'C) .......................... 325mW
Total Device Dissipation, T A 25'C
(Derate 3.3 mW/·C) ...................... _... 650mW
Storage Temperature Range ........ " - 65'C to + 200'C
Lead Temperature
(1116'.' from case for 10 secondsi .............. 300'C

=

=

'.

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25° C unless otherwise noted
. ,PARAMETERS

SYMBOL
IGSS

WAFER
2N5564/W
2N5564/W
2N5566/W

TO-71
2N5564
2N5565
. 2N5566
CONDITIONS

Gate-Reverse Current

DICE
2N55641D
2N5565/D
2N55661D
MIN.

VGS= -20V, VDS=O
150"C

S
T
A
T
I
C

BVGSS

Gate·Source Breakdown Voltage

IG = -1j 100 dB
Low Offset
/:; I VGS1 - VGS21<5mV

•

Tight Tracking
VGS1 - VGS2 !//:;T<5/lV;oC

en

< 10 nV/~ at 10 Hz
PIN
CONFIGURATION

/:; I

CHIP
TOPOGRAPHY

I

6019

TO·71
0,

G'~'};r

ABSOLUTE MAXIMUM RATINGS (Note 1)

039"--j

[--= •iii
i I ======-...L

(@ 25° C unless otherwise noted)

Maximum Temperatures
_65°C to +150°C
Storage Temperature
+150°C
Operating Junction Temperature
Lead Temperature (soldering, 10 sec, time limit) +300°C

151

1

I

-I-

I

025

0035

G2

ORDERING INFORMATION
TO·71
2N6483
2N6484
2N6485

±50 V

VG 1 G2 Gate to Gate Voltage

50mA

IG Gate Current

ELECTRICAL CHARACTERISTICS
SYMBOL

(@

WAFER
2N6483/W
'2N6484/W
2N6485/W

DICE
2N6483ID
2N6484ID
2N6485ID

25°C unless otherwise specified)

CHARACTERISTICS

MIN.

'GSS

Gate Reverse Current

BV GSS

Gate·Source Breakdown Voltage

50

Vp

Gate Source Pinch-Off Voltage

0.7

'OSS

Drain Current at Zero Gate Voltage

9"

Common-Source Forward Transconductance

9055
Ciss
Crss

Common·Source Reverse Transfer Capacitance

MAX.

UNIT·

200

pA

VGS" ~30V, VOS-'O. TA

200

nA

VGS" -30V,VOS"'O,TA" 1150C

·4.0

TEST CONOITIONS

V

'G"

V

VOS

20V,IO=1I1A

0.5

7.5

1000

4000

,umho

VOS'" 20 V, VGS = 0, f -= 1 KHz (Note 2)

Common-Source Output Conductance

10

pmho

V OS "20V,VGS"O,I" 1 KH,

Common Source InllUI Capacitance

20

pF

Vos = 20 V" VGS " 0, I " 1 MH,

3.5

pF

V OS "20V,VGS"O,I= 1 MH,

100

pA

100

nA

V GO - 20V,I0 200 "A, TA = t25··C
VOG = 20 V, '0 = 200 "A, T A - I 150·'C

0.2

3.B

V

500

1500

pmtlo

VOG" 20 V, '0

=

200"A,1

pmho

VOG

0

200"A

nV/"fFfi
nV/..;Ffi

VOS

0

VOS

0

IG

Gate Current

V GS

Gate-Source Voltage

91,

Common·Source Forward Transconductance

90,

Common Source Output Conductance

en

Equivalent Input Noise Voltage

10

1·91

mA

125 C

=-

I"A.VOS"O
0

VOS" 20 V, VGS" 0 INote 21

0

VOG = 20V,I O - 200"A

0

20 V,IO

=

1 KHl !Note 2)

20V, '0 = 200 "A, I - 10 H,
20V,I 0

0

o(m

T~!S 2 PL~~~S

52

-50 V

0027

TYP 2 PLACES

D20035x0035

-50 V

VGD Gate to Drain Voltage

0025 X 0070

2 PcACES
0037 X 0037

Maximum Power Dissipation
Device Dissipation @ 85°C Free Air Temperature
One Side
250 mW
Both Sides
500mW
Linear Derating
3,85mwfc
O~e Side
7,7 mWfC
Both Sides
Maximum Voltages & Currents
VGS Gate to Source Voltage

'"

0080

200"A,I- 1 KH,

2N6483 - 2N6485
MATCHING CHARACTERISTICS (@2SoCunlessotherwise noted)

D

SYMBOL

2N6483

CHARACTERISTIC

I DSS1
I DSS2

Drain Current Ratio at Zero
Gate Voltage

gfsl

UNIT

MIN.

MAX.

MIN.

MAX.

0.95

1

0.95

1

0.95

1

-

10

nA

1

-

10

10

Transconductance Ratio

ggs2

2N6485

MAX.

"Differential Gate Current

IIGI -IG21

2N6484

MIN.

0.97

1

0.97

1

0.95

CONDITIONS
V DS =20V,V GS =0
INote 21
VOG.= 20 V, 10 = 200 MA
TA = +125°e
VOG = 20 V, 10 = 200 MA,
f = 1 KHz INote 21

0.1

0.1

0.1

Mmho

VOG = 20 V, ID = 200 MA,
f = 1 KHz

5

10

15

mV

V DG = 20V, 10= 200MA

tial Drift

5

10

25

pvre V DG = 20V, ID= 200MA
TA = +25°e to +125°e

Ll. 1V GS1 - V GS2 1 Gate-Source Voltage Differential Drift
Ll.T

5

10

25

pV/oe

Differential Output

I gas 1 - gos21

Conductance

1V GS1 - V GS2 1

Oifferential Gate-Source
Voltage

Ll.1 V GS1 - VGS21
Ll.T

Gate-Source Voltage Differen-

Common Mode Rejection

eMRR
NOTES:

100

Ratio

90

100

dB

VOG = 20V, ID ~ 200MA
T A = -55°e to + 25°e
V DO =10t020V,
10 = 200 pA INote 31

1. These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
2. Pulse duration of 2 ms used during test.
3_ CMRR = 20Log lO Ll.V DD/Ll.IV GSI - V GS21, ILl.V DD = 10 Vl, not included in JEDEC registration

TYPICAL OPERATING CHARACTERISTICS
en vs. FREQUENCY

en vs. FREQUENCY
100

100

I
:i!

-t

, :i

'"~
.c

10

_~il

II

'0 = 200/J.A

.t

I

i

VOS"'20V

'"=s
.-

~?Ll'15V&2V
~~V~S'20V

I

".,J +

_.

.c

--

10

ID-2~iJ.~

::-- ~

r--

-~

:::f:::::

'0 ; 4OO .u A

I
I

1
10

100

lK

10K

1
10

lOOK

100

frequency (Hz)

15

80

~

If I-

J

r---

40

-

20

.....

10
8.0
8.0

-T

./

lOSS

.......-

2.0 4 - 4 0 0 •

1.0

"

/ I

E
u

12
11
10

./

.....

.,/"

10

I

15

20

25

o

30

VOG IVI

Ci~

o

2

-

4 6

C'"

-

8 10 12 14 16 18 20 22 24 26 28 30

VOSIVI

1-92

I-

'0' 200JA I-

/'

.¥200.A
o

-

.....

13

n

60

4.0

lOOK

TYPICAL CAPACITANCE vs. VDS

GATE CURRENT vs. VDG

~

10K
frequency (Hz)

'100

~

lK

IMF6485
Low Noise Dual Monolithic
N·ChanneIJFET

O~OIb

FEATURES

• en

<

GENERAL DESCRIPTION
This N-Channel Junction F ET is characterized for ultra'
low noise applications requiring tightly contrplled and specified noise parameters at 10 Hz and 1000 Hz. Tight matching specifications make this device ideal as the input
stage for low frequency differential instrumentation amplifiers.

10nV/.vRZ@ 10Hz

• CMRR>90dB
• /:, IV GS1 =V GS2

I< 25 mV

• /:, IV GS1 =V GS2 1<40J,lV/°C.
ABSOLUTE MAXIMUM RATINGS(Note 1)
(@ 25°C unless otherwise noted)

.------~

PIN
CONFIGURATION

Maximum Temperatures
Storage Temperature
_65°C to +150°C
Operating Junction Temperature
+150o C
Lead Temperature (soldering, 10sec. time limit! +300°C

TO·71

D,
G,

039

-----i
-

Iii, 'I.~:-l

~80

003S

"'Zf'~!t S,

0025 X 0010
TYP 2 PLACES

~~

025

-J.

x

:i;x

D2

±50V
50mA

ELECTRICAL CHARACTERISTICS

ORDERING INFORMATION

(@

25°C unless otherwise specified)

CHARACTERISTICS

MIN.

MAX.

UNIT

-200

pA

V GS = -30 V, VOS = 0, TA = +25"C

-200

nA

VGS= -30 V, VOS=O, TA =·.+150'·C

V

IG

VOS=20V,10= 1 nA

TEST CONDITIONS

IGSS

Gate Reverse Current

BV GSS

Gate-Source Bre,akdown Voltage

-50

Vp

Gate·Source Pinch·Off Voltage

-0.7

-4.0

V

lOSS

Drain Current at Zero Gate Voltage

0.5

7.5

rnA

gfs

Common-Source Forward Transconductance

1000

4000

~rnho

VOS = 20 V, VGS = 0, f = 1 KHz (Note 21

9055

Common-Source Output Conductance

10

J,lmho

VOS = 20V, V GS = 0, f = 1 KHz

C iss

Common-Source Input Capacitance

20

pF

V OS=20V, V GS =0, f = 1 MHz

Crss

Common:Source

3.5

pF

VOS=20V,VGS=O,f= 1 MHz

100

pA

VGO = 20 V,IO = 200~A. T A ~ +25·C

100

nA

VOG'= 20 V,IO = 200~A, TA ~ +150·C

0.2

-3.8

V

VOG = 20V,I D = 200~A

500

1500

IJmho

VOG = 20 V, 10 = 200 ~A, f = 1 KHz INote 21

1·

p.mho

VOG = 20 V,IO = 200~A

Transfer Capacitance

IG

Gate Current

V GS

Gate·Source Voltage

9fs

Common·Source Forward Transconductance

90s

Common·Source Output Conductance

,
en

~i;

ryp 2 PLACES

-50 V

IG Gate Current

~everse

~i~

G2 TYP 2 PLACES

S2

-50 V

VGD Gate to Drain Voltage
VG1- G2 Gate to Gate Voltage

SYMBOL

't--

6019

I /:-it

Maximum Power Dissipation
Device Dissipation @ 85 0 C Free Air Temperature
One Side
250 mW
Both Sides
500 mW
Linear Derating
One Side
3.85mwfc
7.7 mW/oC
Both Sides
Maximum Voltages & Currents
VGS Gate to Source Voltage

CHIP
TOP.OGRAPHY

EqUivalent Input Noise Voltage

1-93

= -1

~A. VOS = 0

VOS = 20 V, VGS = 0 (Note 21

15

nV/,j"Rl

Vos = 20 V, 10 = 200~A, f = 10 Hz

10

nV/y'RZ

Vos = 20 V, 10 = 200~A, f ~ 1 KHz

,

II

IMF6485
MATCHING CHARACTERISTICS
SYMBOL

(@ 25°

C unless otherwise noted)

CHARACTERISTIC
Orain Cu~rent Ratio at Zero Gate Voltage

IOSS1

MIN.

MAX.

UNIT

0.95

1

-

10

nA

CONDITIONS
VOS = 20 V. V GS = 0 (Note 21

IOSS2
Oifferential Gate Current

I IG1 - IG2 I

VOG = 20 V, 10 = 200 J.lA
T A = +125° C

II

Transconductance Ratio

gfs1

0.95

-

1

-

V OG =' ,20 V, 10 = 200 J.lA,
f = 1 KHz (Note 2)

ggs2
I gos1 - gos2 I

Oifferential Output Conductance

0,1

J.lmho

VOG = 20 V, 10 =200 ,J.lA,
f = 1 KHz

I V GS1 - V GS2 1

Oifferential Gate-Source Voltage

25

61V GS1 - V GS2 1

Gate-Source Voltage, Oifferential Odft

40

VOG = 20 ~. 10 = 200 J.lA

mV

= 200

J.lvt C VCG = 20 V. 10

J.lA

T A = +25° C to +125° C

6T
61V GS1 -V GS2 1

Gate-Source, Voltage Oifferential Orift

40

J.lvt C VOG = 20 V. 10 = 200 J.lA
T A = _550 C to +250 C

6T

Common Mode Rejection. Ratio

CMRR

90

dB

VOO = 10 to 20 V.
10 = 200 J.lA (Note 3)

NOTES:

1. These ratings are limiting values above which the serviceability of any individual semiconductor device may be ,mpaired.
2. Pulse duration of 2 ms used during test.
3. CMRR = 20L0910

~

I

,.'"e

:s,.e

IO-l00PA

:- pVOS= 15V

10

::::;: t::,..
f-

10:: 200/-1

,;::: S;:

-I-Vos- 20 V' •

~

,.....

10

100

10K

lK

1
10

lOOK

~oo

/

",-

10
8,0
6,0

/'

'GSS

,./

~

12

"U;,

10

E

Vi e--

20

-r

c;:.

13

40

4,0

11

9
10" 2 ~IA

./

10

Cns ,;

r-I-I-

~OO/-1A

o

-

./

2,0 _'O=400pA /

1,0

IHII

15
1.

60

~

lOOK

10K

TYPICAL CAPACITANCE vs. VDS

GATE CURRENT vs. VDG
100
80

lK

frequency

frequency (Hzl

«

'0:: 400 J.lA

VOS"'25V

1

.!;

I

10

1
15

20

25

o

30

I
o

2

4 6

8 10 12 14 16 18 20 22 24 26 28 30
VOSIVI

1-94

;,

...

-:"-:

Verlical Power . . .. . . . .

... .. ···"OSFETi*:~E:'}1
..
•,

< SO

IVN6000KN Series

rOS(on)
Page
2-31

BVOSS < 100V,
r05(on) < 0.50
/'

.

.
".~ •• , .

:

.

..

<..

~

,

BVoss < 100V,

BVoss>3S0V,
rOS(on)

.

.,. N . . . . . " ••••• ·~ . , • •

IVN5200/1HN Series 2-23
IVN5200/1 KN Series 2-25
IVN5200/1TN Series . 2-27
2-29
IVN5201CN Series

< SO

VN10KM
VN30AB Series
VN35AK Series
VN40AF Series
VN46AF Series
IVN5000/1AN Series
IVN5000/1 BN Series
IVN5000/1SN Series
IVN5000/1TN Series
IVN5001AZ Series
IvN6660/61 Series
2N6660/61 Series

2-3
2-5
2-7
2-9
2-11
2-13
2-15
2-17
2-19
2-21
2-37
2-39

,~

,

.

..

c::::::::I,

SELECTOR GUIDE N·CHANNEL ENHANCEMENT MODE VERTICAL POWER MOS,BVoSS<100V

rOS(on)

10(on)

VGS(lh)

OHMS

AMPS

VOLTS

MAX

~

MAX

Po
WATTS

BVoss -

Tc~25·C

MIN

35V MIN
ZENER

DRAIN·SOURCE BREAKDOWN VOLTAGE

40V MIN

NON·ZENER

ZENER

60V MIN

80VMIN

90V MIN

STEADY

PEAK

MIN

0.5

5,0

12

0,8

2,0

50

IVN5200KND

IVN5200KNE

IVN5200KNF

0,5

5,0

12

0,8

3,6

50

IVN5201KND

IVN5201KNE

IVN5201KNF

0,5

4,0

10

0,8

2,0

12,5

IVN5200TND

IVN5200TNE

IVN5200TNF

0,5

4,0

10

0,8

3,6

12.5

IVN5201TND

IVN5201TNE

IVN5201TNF

2,5

1.2
1,2

3,0

0,8

2,0

6,25

IVN5000TND

IVN5000TNE

IVN5000TNF

IVN5000TNG

2,5

3,0

0,8

-

6,25

IVN5001TND

IVN5001TNE

IVN5001TNF

IVN5001TNG

3,0

1,2

3,0

. 0.8

2.0

6.25

3,5

1,2

3,0

0,8

2,0

VN35AK
VN35AB

NON·ZENER

NON·ZENER

IVN6660

3,5

1.2

3,0

0,8

-

6.25
6,25

4,0

1,2

3,0

0,8

2,0

6,25

4.5

1.2

3.0

0.8

2.0

6.25

4.5

1.2

3.0

0.8

6.25

5,0

1.2

3.0

0.8

-

2.5

0.9

O.S
0,8

2.0
3,6

3.13
3,13

IVN5000SND

6.25

ZENER

ZENER

NON·ZENER

ZENER

PACKAGE

NON·ZENER
TO·3

TO·39

VN66AK
VN67AK

VN67AB
IVN6661

VN98AK
VN99AK

VN89AB
VN30AB

VN90AB

2,5

0,9

3.0
3,0

IVN5001SND

IVN5001SNE

IVN5001SNF

0.5

5.0

12

0.8

2.0

30

IVN5200HND

IVN5200HNE

IVN5200HNF

0.5

5.0

12

0,8

3,6

30

IVN5201HND

IVN5201HNE

IVN5201HNF

IVN5000SNE

IVN5000SNF

TO·52

TO·66

I\)

3.0

1.7

3,0

0,8

-

12

3,5

1.7

3,0

0,8

-

12

4,0

1.7
1,7

3,0

0,8

-

12

4,5

3,0

0,8

-

12

5,0

1.7

3.0

0,8

-

VN46AF

VN66AF
VN67AF
VNS8AF

TO·202
(PLASTIC)

VNS9AF

12

VN40AF

2,5

1.7

2.0

12

IVN5000BND

IVN5000BNE

IVN5000BNF

1.7

3.0
3,0

O.S

2,5

O,S

3,6

12

IVN5001BND

IVN5001BNE

IVN5001BNF

0,5

5,0

12

O,S

3,6

30

IVN5201CND

IVN5201CNE

IVN5201CNF

2,5

0.7

2,0

0,8

2,0

2,0

IVN5000AND

IVN5000ANE

IVN5000ANF

2,5

0,7

2,0

0.8

3,6

2.0

IVN5001AND

IVN5001ANE

IVN5001ANF

-

0.5

1,0

0.3

2.5

1.0

VN10KM .

3.0

0.5

2.0

0.8

3.6

2.0

IVN5001AZE

RoS(on)
OHMS

VGS(lhl
VOLTS

1000n)
AMPS

MAX

STEADY

3.0

2.25

I

PEAK

MIN

7.5

2.0

I

Po
WATTS

..

TO·220
(PLASTiC)

TO·237
(PLASTiC)

IVN5001AZF

BVoss

Tc~25·C

MAX

MIN

350V

5.0

36

IVN6000KNR
--- :.---------

I

I

400V
IVN6000KNS

I

I

450V
IVN6000KNT

.c::::::::I

F

VN10KM
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• Directly drives inductive loads

• LED and lamp drivers

• High speed, high peak current switching

• TTL and CMOS to high current interface

• Inherent current sharing capability when paralleled

• High speed switches

• Directly interfaces to CMOS, DTL, TTL logic

• Line drivers

• Simple, straight-forward DC biasing

• Relay drivers
• Transformer drivers

• Inherent protection from thermal runaway

II

,--------,
(OUTLINE DWG. TO-237)

SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS

DRAIN

~----,

(T A = 25° C unless otherwise noted)
Drain-source Voltage ........................... 60V
Drain-gate Voltage ............................. 60V
Continuous Drain Current (see note 1) ......... 0.5A
Peak Drain Current (see note 2) ............... 1.0V
Gate-source Forward Voltage ............ " .... +15V
Gate-source Reverse Voltage '" ............ ; .. 0.3V
Continuous Device Dissipation at (or below)
25°C Case Temperature ..................... 1.0W
Linear Derating Factor. . . . . . . . . . . . . . . . . . .. 8mW/oC
Operating Junction
Temperature Range ................ -40 to +150°C
Storage Temperature Range .......... -40 to+150°C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C

*
I
I

I

I
I

GATE

(see note 3)

I

_J
SOURCE

Body Internally connected to source
Drain common to tab

S

CHIP TOPOGRAPHY

Note 1. Tc ; 25°C; controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Maximum pulse width 80!,sec, maximum duty cycle 1.0%.
Note 3. The Drain·source diode is an integral part of the MOSFET
structure.

2-3

/

G

D

VN10KM

O~OIb

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

BVDSS

Drain-Source Breakdown

60

VGS(lh)

Gate Threshold Voltage

0.3

f-2

f--

S

3

T
A
T
I
C

f-4

f-5

f-6

Min

Typ

Unit

Max

Test Conditions

= OV,

= 100 /J-A

V

- VGS

2.5

V

VDS

= VGS,ID = 1 mA

ID

IGSS

Gate-Body Leakage

10

nA

VGS

= 10V, VDS = 0

IDSS

Zero Gate Voltage
Drain Current

10

/J- A

VDS

= 40V,

A

VDS

ID(on)

ON-State Drain Current
VDS
V

VGS

= 10V, ID = 0.5A

mmho

VDS

= 15V, ID = 0.5A

pF

VDS

= 25V, f = 1 MHz

Note 2

0.25
0.50

f--

VGS

=0

= 25V,

VGS

= 5V

= 25V,

VGS - 10V
Note 1

7

8
f-9
f--

D
y
N

10

A
M

f-11

f--

I

12

C

f-13

2.~

VDS(on)

Drain-SolJrce ON Voltage

Qts

Forward Transconductance

Ciss

Input Capacitance

48

Coss -

Output Capacitance

16

Crss

Feedback Capacitance

2

tON

Turn-ON Time

5

tOFF

Turn-OFF Time

!j

100

200

Note 2
See Switching Times Test
Circuit, page 2-42

ns

NOTES: 1. Pulse lesl -80 ,"s pulse. 1% duly cycle.
2. Sample Test.

THERMAL RESPONSE

DC SAFE OPERATING REGION
Tc = 25°C
0

D -0.5

D=J2

-

-F

V

D;:.t!-

V

500.,.g:j

5msec

"

~
I

r-

ffi
a:

100·',,<;11

~,

1.0

....

l' 10psec

DC

a:

"

"z
;;:

D=~r-

1

'p lmsec

~

V

O. 1

a:

.ru
~I I

~rN5000AND
"
IVN5001AND

Ri

VN5O o'OANE
IV"I5QO.II\1\1.~
IVN5000ANF

a

E
0.0 ,

IVN5001ANF

1.0
10
100
VDS DRAIN - SOURCE VOL TAGE IVOL TS)

'2-

DUTY CYCLE, 0 = 11/t2

0.0 1
0.01

0.1

10
t1 - TIME

~IIII

100

(m~ecl

POWER DISSIPATION
DERATING
1000

2.4r---,.,--,---,--,--..,

E

~ 2.0t--....t--t--t--t---I

T
~

1.6

~
~

1.2 r-~--~---r--~~

aa:

0.8/--t--'--t-"<-+--t---I

2~ o.4F=R2:"'f'---k---t---I

Note: For other 5000 family characteristic curves, see page 2-41.
2-4

~ o~....,.~....,.~~~~~~
-0
200
T~ TEMPERATURE-rCI

VN30AB, VN35AB, VN67AB,
VN89AB, VN90AB
n-Channel Enhancement-mode
Vertical Power MOSFET
FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTl.. logi.~

• CMOS and TTL to high current interface

• Sim"le DC biasing
• Extended safe ope~ating area

• Line drivers
• Logic buffers
.• Pulse amplifiers

• Inherently temperature stable

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(,1'A = 25° C unless otherwise noted)

DRAIN

Drain-source Voltage
VN30AB, VN35AB ...' ........................ 35V
VN67AB .................................... 60V
VNB9AB ..................................... BOV
VN90AB ................ ;.:................. 90V
Drain-gate Voltage
VN30AB, VN35AB ........................... 35V
VN67 AB ....... : ................... , ........ 60V
VNB9AB ......................... : .......... BOV
VN90AB ..................................... 90V
Continuous Drain Current (see 'lote 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2.0mA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .......... : ....... 100mA
Gate-source Forward (Zener) Voltage .......... +15V
Gate-source Reverse (Zener) Voltage .......... -0.3V
Thermal Resistance, Junction to Case ....... 20°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature .................... 6.25W
Linear Derating Factor .................... 50mW/oC
Operating Junction
Temperature Range ...... , ......... -55 to '+150°C
Storage Temperature Range .......... -55 to +150°C
Lead Temperature
(1116 in. from case for 10 sec) ............. +30aoC
Note 1; Tc = 25°C; controlled by typical
power dissipation.

(OUTLINE DWG. TO-39)

.

J~~om"
I
I

iI

I
_J

GATE 0 - - - _ - - '

SOURCE
GATE

Body Internally connected to source.
Drain common to case.

CHIP TOPOGRAPHY

rDSlon) and maximum

Note 2. Pulse width BOllsec, duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

2-5

SOURCE

VN30A~VN35AB,VN67AB,VN89AB,VN90AB

O~OIb

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
VN30AB

CHARACTERISTIC

~2

-:a

...:. S

T
A
T
I
C

4

5

MIN

BVoss

Drain Source Breakdown

35

VGS{th)

Gate Threshold Voltage

0.8

lass

Gale-Body Leakage

6

10(01\)

7

9"

Forward Transconductance

"8

Clss

Input Capacitance (Note 2)

-

C~,

-

11..c
~

(Note 1)

TYP

0.01

VN90AB

MAX

MIN

80

0.8

1.2

0.5

0.8

0.01

MAX

90
0.8

1.2

0.01

0.5

TYP

0.5

V

1.2
0.01

0.5

.A

TEST CONDITIONS

10
10

=10.uA, VGS =0
=1.0mA. Vos = VGS

Vas - 10V, Vos = 0

=0

10

10

Vos = 25V, Vas

6.0

4.5

5.1

5.1

6.0

VGS = 5V, 10 - 300mA

2.2

2.5

2.2

,

2.0

1.0

3.5

2.2

2.0

250

1.0

250

2.2

4.5

2.0

1.0

250

5.0

2.0
250

50

50

50

50

10

10

10

10

10

40

. 40

40

40

40

n

Vas = 10V, 10

A

Vos

mn

.vos

=1.0A

=25V. VGS = 10V
25V.lo

O.SA

50

ton

Turn-ON Time (Note 2)

4

10

4

10

4

10

4

10

4

10

tolf

Turn-OFF Time (Note 2)

4

10

4

10

4

10

4

10

4

10

Note 1. Pulse Test -

UNIT

10

250

Capacitance (NOt6 2)

TYP

10

1.0

Capacitance (Note 2)

MIN

10

2.0

Reverse Transfer

VN89AB

MAX

60

5.0

Common Source Output
Coss

MIN

1.2

0.5

2.2
1.0

VN67AB

MAX

35

Drain-Source ON-State
Resistance (Note 1)

TYP

0.8

0.01

ON-State Drain Current

MIN

1.2

Drain Current

ROs(on)

VN35AB

MAX

Zero Gate Voltage

loss

-

D
Y
9 N
A
M
10 I

TYP

pF

VGS = 0, Vos

= 24V.

1= 1.0MHz

ns

BO,us, 1% duty cycle.

Note 2. Sample Test.

THERMAL RESPONSE
0- 0.5

((I

-'o IIIL
0.2

I-'"

/'

-=0.01

0.01

0=0.1--" ,.....
0=0

"'"

,/

III

-

-

JLJ

./

~I'2-I
TuTIlr' ~ =(j2
0.1

10

1000

100

t1 - TIME (msec)

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

DC SAFE OPERATING REGION
Tc = 25°C
10

9.0

Vi
II-

"~z
0

6.0

~

4.5

0

3.0

iii

I

7.5

-----

I

~

+80

:;

;;:

0::

0

Z

0.1

~

+120

+160

T - TEMPERATURE (OC)

+200

I

VN30AB, VN35AB

:s

>

VN67AB

I

.9

=

0.0

'"

llli VN~9A~
1

1111111
10

\;'"

"""

"

0.8

VN90AB
100

VOS - DRAIN TO SOURCE VOLTAGE (VOLTS)

2-6

0.9

,.

....

1.1

'""

u
Z

o

+40

"-

::>

0::

o
o

51
N

0::
0::

1.5 ,-;--FREE AIIR " "

20a"c/W

1.2
"-

ffi

INFINITE HEAT SINK

[\.20°C/W

~
_

500 ~s~50 J.l ~ 00 f.lS 10 ~s

DC

I-

0::

~

~!:"5

~
.",
:;

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

·40 ·20 0 20 40 60 80100120140
TEMPERATURE _

°c

VN35AK, VN66AK, VN67AK,
VN98AK, VN99AK
n-Channel Enhancement-mode
Vertical Power MOSFET
FEATURES

APPLICATIONS

• High speed, high current switching

• High current analog switches

• High gain-bandwidth product

• RF power amplifiers

• Inherently temperature stable

• Laser diode pulsers

• Extended safe operating area

• Line drivers

• Simple DC biasing

• Logic buffers

• Requires almost zero current drive

• Pulse amplifiers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A = 25° C unless otherwise noted)
Drain-source Voltage
VN35AK .................................... 35V
VN66AK, VN67 AK .......................... 60V
VN98AK, VN99AK ........................... 90V
Drain-gate Voltage
VN35AK .................................... 35V
VN66AK, VN67 AK ........................... 60V
VN98AK. VN99AK ........................... 90V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) .............. : 3.0A
Gate-source Forward Voltage .................. +30V
Gate-source Reverse Voltage .................. -30V
Thermal Resistance, Junction to Case ....... 20°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature .................... 6.25W
Linear Derating Factor .................... 50mW;oC
Operating Junction'
Temperature Range ................ -55 to +150°C
Storage Temperature Range .......... -55 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C
Note 1. Tc '= 25°C; controlled by typical
power dissipation.

Body Internally connected to source.
Drain common to case.

CHIP TOPOGRAPHY

rDSlon) and maximum

Note 2. Pulse width 80llsec, duty cycle 1.0%.
Note 3. The Drain·source diode is an integral part of the MQSFET
structure.

2·7

(OUTLINE DWG. TO-39)

O~OIb

YN35AK, YN66AK, YN67AK,·YN98AK, YN99AK
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

,

MIN

r-1

VGS('h)

Drain-Source Breakdown
Gate-Threshold Voltage

IGSS

Gate-Body Leakage

loss

Zero Gate Voltage
Drain Current

BVoss

~
~
~

S
T
6 A
T
f-= I
~ C

TYP

MAX

0.5

2.0
100

35
0.8

10(on)

Vbs(on)

11
12
13

gt.

r;:;

D
V
15 N
r-- A
M
I
18 C

l-

~

r1l

Ciss

Coss
Crss

ton
toff

0.8

SOO
10

2.0
100
SOO
10

SOO

SOO

O.S

100

ON-State Drain Current
VN66AK

1.0

2.0

Drain-Source
Saturation Voltage

VN98AK
VN3SAK
VN67AK
VN99AK
Forward Transconductance
Input Capacitance
Common Source Output
Capacitance
Reverse Transfer Capacitance

VN98AK
VN99AK
MIN TVP MAX

60

r2

~9
~

VN66AK
VN67AK
MIN TVP MAX

VN35AK

CHARACTERISTIC

1.0
2.2
170

2.S

Nole 1, Pulse test - 80l's pulse, 1°/q duty cycle.

170

-

3.0

4.0

3.S

t.2
2.2

4.S
SO

2S0

I'A

SOO
100
2.0
1.1
2.2

170

40

SO

40

50

2S0
40

38

45

3S

40

32

40

7

10

6

10

10

3
3

8
8

3
3

8
8

S
3
3

Vos" VGS, 10 = lmA
VGS = ISV, Vos = 0
VGS = ISV, Vos = 0, TA = 12S'C INote 21
Vos = Max. Rating, VGS = 0
Vos = 0.8 Max. Rating, VGS = 0, TA = 12S'C
(Note 2)
Vos = 2SV, VGS = 0
Vos = 2SV, VGS = 10V
VGS - SV, 10 = 0.3A

nA

SOO
10

nA
A

= 10V, 10 = t .OA
(Note 1)
= SV, 10 = 0.3A
= tOV, 10 = 1.0A
= 24V, 10 = O.SA, f - 1KHz

mil

VGS
VGS
VGS
VOS

pF

VGS = 0, Vos

V

8
8

TEST CONDITIONS

VGS = 0, 10 - 10uA

V

2.0
100

O.S

1.0

1.1.
2.2

2S0

Turn ON Time
Turn OFF Time

100
2.0
1.0
2.2

1.0

90
0.8

UNIT

= 24V, f = lMHz

(Note 2)

ns

Note 2. Sample test.

THERMAL RESPONSE
o

... ..,,0

0.5

c.--

1111
11111

o:W
wN

0=0.2

"':;
.....
...Wo"

---

i--'

_f-

>~

o=o·vf--'

20:

2,

V;2

~;;:

o. 1

"'0
w,,-"
>w

i=o
02
w ..

JLj.

0-0

...

~

~'"
Wv;

_f-

,,~II

IW

:co:

,!-

DUTY CYCLE, 0

I IIIIIII

0.01

t,/t 2

I(
1000

100

10

0.1

0.D1

=:

t, - TIME (msecl

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

POWER DISSIPATION vs CASE 'DC SAFE .OPERATING REGION
OR AMBIENT TEMPERATURE
Tc = 25°C

i

9.0

2

6.

a

i=
~

10

I
I

7.5

0 .........

~

~
....
150:

INFINITE HEAT SINK

4. 5

~
o

0:

~

0
+40

+80

~

+120

T - TEMPERATURE

+160

ee)

faN

~

'~"
0:

r=

.P

1--0.0 1

-

"

VN66AK. VN67AK

V1N9~~~: VN9~A~
10

+200
Vo•

>~

VN35AK

: ,

100

ORAIN·TO·SOURCE VOLTAGE (VOLTS)

2·8

Lo-'

1. 1

Lo-'
~

1

Lo-'
I,;;;"

I

(

o. 1

I

1. 5 \--- FREE JR " ' "
20B'CIW

1.2

,"'...

f--

"oz

"{

~

C 3. 0

250lJ,s 100jJs 1Op'

'--=-f-11

a:

I"-20'CIW

~f:El,rry$,

0.9

o. B
-40 -20 0 20 40 60· 80100120140
TEMPERATURE _

°c

VN40AF, VN67AF, VN89AF

D~D~

n-ChanneIEnhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC· biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature' stable
• Reliable, low cost plastic package

• DC motor controllers

• Pulse amplifiers,

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A =,25° C unless otherwise noted)
Drain-source Voltage
VN40AF ..................................... 40V
VN67AF ..................................... 60V
VN89AF ..................................... 80V
Drain-gate Voltage
VN40AF ..................................... 40V
VN67AF ..................................... 60V
VN89AF ..................................... 80\1
Continuous Drain Current (see note 1) ......... 1,7A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2,OmA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .................. 100mA
Gate-source Forward (Zener) Voltage ........ " +15V
Gate~source Reverse (Zener) Voltage .......... -0,3V
Thermal Resistance, Junction to Case .... : . 10.4°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature ...................... 12W
Linear Derating Factor .................... 96mW/oC
Operating Junction
Temperature Range ................ -40 to +150°C
Storage Temperature Range .......... -40 to +150°C
Lead Temperature .
(1/16 in. from case for 10 sec) ............. +300°C

(OUTLINE DWG. TO-202)

DRAIN

rl----l

I

(see note 3)

i

I
I
I

GATE

_J
SOURCE

0, TAB

Body internally connected to source.
Drain common to tab.

CHIP TOPOGRAPHY

Note 1. Tc = 25°C; controlled by typical rDS(on) and maximum
power dissipation.
Note 2. Pulse width 80l'sec, duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure. '

2-9

VN40A~VN67A~VN89AF

n~nl!..

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CHARACTERISTIC

r-J.
r43

'4
--::-

~S

MIN

BVoss

Drain-Source Breakdown

VGS(.h)

Gate-Threshold Voltage

IGSS

Gate-Body Leakage

loss

Zero Gate Voltage
Drain Current

VN40AF
TYP MAX

40
40
0.6

7 T

8'

I

9'

10(on)

ON-State Drain Current

11

VOS(on)

prain-Source Saturation
Voltage

~

1.0

13
14

15

16
17

D

gm
·elss

Y Crss

N

A

18 M
19 cI
20
21

Coss

td(on)
tr
td(off)
tf

. Forward Transconductance
Input Capacitance
Reverse Transfer capacitance
Common-Source Output
Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall· Time

MIN

1.2
0.01

100
2
0.3
1.0
1.0
2.2
250

VN89AF
TYP MAX

TEST CONDITIONS

SO

O.S

1.2
0.01

10
100
10

100
2
0.3
1.0
1.0
2.2
250

1.0
2.0
5.0

mU

VGS = 0, 10 = 1O"A
VGS = 0, 10 - 2.5mA
Vos = VGS, 10 = lmA
VGS = 10V, Vos = 0
VGS = 10V, Vos = 0, TA = 125°C (Note 2)
VOS' = Max. Rating, VGS = 0
Vos = O.S Max. Rating, VGS = 0, TA = 125°C
(Note 2)
VOS = 25V, VGS = 0
VOS = 25V, VGS = 10V
VGS = 5V, 10 = O.lA
VGS = 5V 10 = 0.3A
(Note 1)
VGS = 10V, 10 = 0.5A
;
VGS = 10V, 10 = 1.0A
VOS = 24V, 10 = 0.5A, f - 1KHz

O.S
10
100

pF

VGS = 0, VOS = 25V, f = 1.0 MHz

V
1.2
0.01

10

10
100
10

100

100

1.0
1.7
3.5

100
2
0.4
1.4
,1.3
2.2
250

50

50

50

5
5
5
5

2
2
2
2

V

4.5
50
10

2
2
2
2

I

1.9

50
10

5
5
5
5

"A

nA
A

50
10

2
2
2
2

UNIT

60

lob

C

1ii

VN67AF
TYP MAX

60
60

6 T

--"-A

MIN

(Note 2)

5
5
5
5

ns

Note 1. Pulse test - 80l's pulse. 1% duty cycle.
Note 2. Sample test.

THERMAL RESPONSE
1

~

0=05

;....-::;;..-

III

IJ~IJ

//

./

1J!!f-I;'

1
0=

fLJ

~.~',I'.

OUTY CYCLE. 0 =
0.0 1
0.01

11111111
10

0.1

I I
1000

100

t, - TIME (ms~)

POWER DISSIPATION vs
CASE TEMPERATURE

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

DC SAFE OPERATING REGION
Tc = 25°C

8

'.2
5

•
9

fo
"

::;

INFINITE HEAT SINK

i\...

,0.4'C/w

"-

6

3 r-FREE AIR
104°CIW

0

lilN

"-

0.'

-".

+80 +120 +160 +200
T _ TEMPERATURE (DC)

+40

mE.

O.O',L..o-L...l...l.J..LlJJ•.Lo-L...l....L..IJJ..ILI.oo
VDS '" DRAIN-SOURCE VOLTAGE (VOLTS)

,

...

/

'"

~

:;;
0:

0

".

Z

I

l!l 0.9
>

".

.,

O.B
-40 -20

a

20 40 60 80100 120140

TEMPERATURE -

2-10

'c

VN46AF, VN66AF, VN88AF
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing'

• Line drivers

• , Extended safe operating area

Logic buffers

• Inherently temperature stable

• Pulse amplifiers

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Drain-source Voltage
VN46AF ....................................... 40V
VN66AF ..................................... 60V
VN88AF ..................................... 80V
Drain-gate Voltage
VN46AF ..................................... 40V
VN66AF ..................................... 60V
VN88AF ..................................... 80V
Continuous Drain Current (see note 1) ......... 1.7A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2.0mA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .................. 100mA
Gate-source Forward (Zener) Voltage .......... +15V
Gate-source Reverse (Zener) Voltage .......... -0.3V
Thermal Resistance, Junction to Case ..... . 10AoC/W
Continuous Device Dissipation at (or below)
25°C Case Temperature ...................... 12W
Linear Derating Factor .................... 96mW/oC
Operating Junction
Temperature Range ................ -40 to +150°C
Storage Temperature Range .......... -40 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C

GATE

D, TAB

CHIP TOPOGRAPHY

Note 1. Tc = 25°C; 'controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Pulse width 80l'sec, duty cycle 1.0%.
Note 3. The Drain·source diode is an integral part of the MOSFET
structure.

2·11

(OUTLINE DWG. TO·202)

VN46AF,VN66A~VN88AF

·O~OIL

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CHARACTERISTIC

~

r1r2
r-i

~
~
7

'a
~
~
i-=

T
A
T
I

C

~

D

17

N
A

21

Drain-Source Breakdown

VGSlth)

Gale-Threshold Voltage

IGSS

G~le-Body

loss

Zero Gale Vollage
Drain Current

ID(on)

ON-Slale Drain Currenl

Leakage

10
100
10

gl,

Forward Transconductance

Inpul Capacilance

M
I
C

100
2
0.3
1.0
1.0
2.2
250

1.0

Coss

150

1.5
3.0
150

Capacitance

Id(onl

Turn-ON Delay Time

"

Rise Time

2
2
2
2

Turn-OFF Delay Time
Fall Time

Id(off)
II

Note 1, Pulse tesl -

1.7
0.01

80,"s pulse, 1% duty cycle.

MIN

80
80
0.8
10
100
10

VN88AF
TYP MAX

100
2
0.3
1.0
1.0
2.2
250

1.7
0.01

10
100
10

1.0
1.5
3.0
150

100
2
0.4
1.4
1.3
2.2
250

nA
A
1.7

ml1
50
10

50

50

50

5
5
5
5

2
2
2
2

V

4.0

50
10

2
2
2
2

itA

100

50
10

5
5
5
5

UNIT

V

100

1.0

Reverse Transfer Capacitance
Common-Source Output

Y erss

VN66AF
TYP MAX

100

Vollage

Giss

MIN

60
60
0.8

1.7
0.01

Drain-Source Saturation

VOS(onl

r11.
13
r1!

r;a
r,g
20
r=-

BVoss

40
40
0.8

VN46AF
TYP MAX

S

r1+

r2§.

MIN

pF

5
5
5
5

TEST CONDITIONS

VGS =0, 10 = 10ltA
VGS =0, ID =2.5mA
VOS =VGS, 10 =1mA
VGS - 10V, VOS =0
VGS =10V, VOS =0, TA =125'C (Nole2)
Vos =Max. Raling, VGS =0
VDS =0.8 Max. Rating, VGS =0, TA -125'C
(Nole 2)
VOS - 25V, VGS =0
Vos =25V, VGS =10V
VGS =5V, 10 - 0.1A
VGS =5V, ID =0.3A
(Nole 1)
VGS =10V, ID =0.5A
VGS - 10V, 10 - 1.0A
Vos - 24V, 10 - 0.5A,! - 1 KHz

Vas =0, VOS
! =1.0MHz

=25V,
(Nole 2)

ns

Note 2, Sample test.

THERMAL RESPONSE
D-O.S

;L
,,0

b'J~'4

a: W
wN

:z:::;
......

lffi'L-

"

....2a:
Wo

;;;2

2,

i'i: l! o. 1
.... 0
w'-

/1--'

V
V

-0

2:w

nJ

.... 0

02

......'"
..~~
w ..

~I,,-I

",a:

,;-

DUTY CYCLE, 0 = t,/t 2

0.01
0.01

11111111
10

0.1

II
1000

100

t, - TIME (msec)

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

DC SAFE· OPERATING REGION
Tc = 25°C

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE
1.'2

,

fa
N

.

INFINITE HEAT SINK
10.4°CNoJ

::;

0
. 0

+40

~

"
a:

'\
t--FREE AIR
~Q4·C!W

1.1

0

"'- ~

+80

+120

0.1

VN66AF
~~~'IIV~N~46~A~FII
11111111 VN~8~F

+160 +200

T _ TEMPERATURE (OC)

o.O~L..O-J......L.J...J.J.J.JCLt'0,-..l-.LL.J.J.JJlJ'00
Vos - DRAIN-SOURCE VOLTAGE (VOLTS)

,

2

~

>
CD

0.9

I--'

"" ""

""

0.8

-40 -20 0

~O

40 60 80100120140

TEMPERATURE _ °c

·2·12

IVN5000/1 AN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high peak current switching

• LED and lamp drivers

• Inherent current sharing capability when paralleled

• High gain, wide-band amplifiers

• Directly interfaces to CMOS, DTL, TTL logic

• High speed switches

• Simple, straight-forward DC biasing

• Line drivers

.• Inherent protection from thermal runaway

II

• Logic buffers
• Pulse amplifiers

• Reliable, low cost plastic package

~--------------------------------~

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

(OUTLINE DWG. TO-237)

DRAIN

J----,

(TA = 25° C unless otherwise noted)
Drain-source Voltage
IVN5000AND, IVN5001AND. : ................. 40V
IVN5000ANE, IVN5001ANE ...... , ............ 60V
IVN5000ANF, IVN5001ANF ................... 80V
Drain-gate Voltage
IVN5000AND, IVN5001 AND .............. , .... 40V
IVN5000ANE, IVN5001ANE ................... 60V
IVN5000ANF, IVN5001ANF ................... 80V
Continuous Drain Current (see note 1) ......... 0.7 A
Peak Drain Current (see note 2) ............•.. 2.0A
Gate-source Forward Voltage .................. +30V
Gate-source Reverse Voltage .................. -30V
Thermal Resistance, Junction to Case ...... 62.5°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature ..................... 2.0W
Linear Derating Factor .................... 16mW/oC
Operating Junction
Temperature Range ................ -40 to +150°C
Storage Temperature Range .......... -40 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) .............. +300°C

:PJ'--"
I
I

SOURCE

Body internally connected to source
Drain common to tab

CHIP TOPOGRAPHY

Note·1. Tc 0 25'C; controlled by typical rOS(on) and maximum·
power dissipation.
Note 2. Maximum pulse width 80l'sec. maximum duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

2-13

S

G

0

IVN5000/1 AN Series
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted), VBS = 0
IVN5000AND
IVN5001AND
MIN TYP MAX

CHARACTERISTICS
Drain-Source Breakdown
Voltage
Gate
IVN5000 Series
VGS('h) Threshold
IVN5001 Series
Voltage

1

-

BVoss

2
3

f-;j

fs

r-s

S

~

A

f--'-

IGSS

T
loss

T
9 I

~
~
~

'O(on)

C

~
~

I--

60

TEST CONDITIONS

VGS = 0, 10 = lOI'A

0.8

2.0

0.8

2.0

0.8

3.6

0.8

3.6

0.8

3.6

V
Vos = VGS, 10 = 1 mA

0.1

Drain Current
IVN5000 Series
IVN5001 Series
IVN5000AND
IVN5000ANE
I'VN5000ANF
IV
lAND
lANE
I
I
lANF

UNIT

80

2.0

10

Zero Gate Voltage

ON-State
Drain Current

IVN5000ANF
INV5001ANF
MIN TYP MAX

0.8

Gate-Body Leakage

Drain-Source
VOS(on) Saturation
Voltage

'12

40

IVN5000ANE
IVN5001ANE
MIN TYP MAX

1.0
1.0

20
1.9
1.9
1.5
2.0
1.2
1.9

0.1

10

50

50

10
500

10
500

2.5

20
1.9
1.9
1.5
2.0
1.2
1.9

2.0

2.5

2.0

1.0
1.0
2.5

0.1

10
50
10
500

'2.5

20
1.9
1.9
1.5
2.0
1.2
1.9

2.5

2.5

2.0

2.5

1.0
1.0
2.5

VGS = 15V, Vos - 0
VGS = 15V, itos - 0, TA - +125'C
Vos = Max. Rating, VGS = 0
Vos = 0.80 Max. Rating, VGS -0, TA-+125'C
VOS - 24V, VGS - 0
VOS = 24V, VGS = 10V
VOS - 24V, VGS - 12V
VGS = 5V, 10 = 0.3A
VGS = 10V, 10 = 1.0A
VGS = 7V, 10 = 0.3A
VGS - 12V, 10 = 1.0A
(Note 1)
VGS = '10V
10 = 1.0A
VGS = 1.2V

nA

I'A
nA
A

2.5

V

Static DrainSource ON

IVN5000 Series

16

Resistance

IVN5001 Series

1.9

2.5

1.9

2.5

1.9

2.5

17

Small-Signal
IVN5000 Series
Drain-Source
ON Resistance IVN5001 Series
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time

2.0

2.5

2.0

2.5

2.0

2.5

VGS ='10V

1.9

2.5

1.9

2.5

1.9

2.5

VGS = 12V

15

I-

rDS(on)

I-18

"19
"20
"21
'22
~

~

rds(on)

D
Y
N

gl.
Giss
Coss
erss
td(on)

A
M
I

C

tr
td(off)
tf

f2s

ffs

170

280
40
27
6
2
2
2
2

170
50
40
10
5
5
5
5

280
40
27

6
2
2
2
2

170
50
40
10
5
5
5
5

n

280

40
27

6
2
2
2
2

0.5A, f = 1KHz

Vos - 24V, 10

mU
50
40
10
5
5
5
5

10 = 1.0A
f = 1KHz

Vos = 24V, VGS = 0

pF

(Note 2)

f = lMHz
See Switching Times Test
Circuit, page 2-42.

ns

(Note 2)

Nole 1. Pulse test - 80l'sec, 1% duty cycle,
Nole 2. Sample test.

DC SAFE OPERATING REGION
Tc = 25°C

THERMAL RESPONSE

0
0-0.5

1
0'j3-

oy
tI

-

I

V

::>

<1

DUTY CYCLE, 0

0.0 I
10

IIIII1I

100

O. 1

a:

.ru
t, - TIME (msec)

~ l'

Cl

§

Fli

IVN5000ANO "
IVN5001ANO
VN5

00'0ANE
IV~5qO,lA~,~

E

tVN5000ANF

0.0 1
1.0

I

10",ec

DC

a:
u
2

500p.sef?=Ff

tzt°O"~

1. 0

iE
a:

o=~
V

0.1

~~~~~

~

I-

V

~tl-1
_ t2-

0.01

'P -

~

IVN5001ANF
10

100

VDS DRAIN - SOURCE VOLTAGE (VOLTS)

= t1/t2

POWER DISSIPATION
DERATING
1000

........

2.4r--~-~-~-r-

~~ 2.01--..+--+---+---+----1
T

~ 1.6

~

1.21---+---''t---+---+---j

Bi
ca: 0.81---+--+-",,-+---+---j
w

~ 0.4F=~:::-"T--*--+----I

.E O'~_~_-::-_:-::.;::,o:-::_~
o
40
160
200
Note: For other 5000 family characteristic curves, see page 2-41.
2-14

T - TEMPERATURE-(OC)

IVN5000/1 BN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

•

•

High speed, high peak current switching

Switching power supplies

•

Inherent current sharing capability when paralleled

•

DC to DC Inverters

•

Interfaces directly with
, CMOS, DTL, TTL logic

•

High gain, broad-band VHF/UHF Amplifiers

•

Simple, straight-forward DC biasing

•

Line drivers

•

Inherent protection from thermal runaway

•

Logic buffers

•

Reliable, low cost plastic package

•

Pulse amplifiers

These devices are Non-Zener equivalents of the
VN40AF Series.
Original Type No.
Zener Protected

Equlv. Type No.
Non-Zener

VN40AF
VN46AF
VN66AF
VN67AF
VN88AF
VN89AF

IVN5001BND
IVN5001BND
IVN5001BNE
IVN5001BNE
IVN5001BNF
"IVN5001 BNF

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

SOURCE

(25° C unless otherwise noted)
Drain-source Voltage
IVN5000BND, IVN5001 BND .................. 40V
IVN5000BNE, IVN5001 BNE .................. 60V
IVN5000BNF, IVN5001BNF ................... 80V
Drain-gate Voltage
IVN5000BND, IVN5001BND .................. 40V
IVN5000BNE. IVN5001 BNE ....... : .......... 60V
IVN5000BNF, IVN5001BNF ................... 80V
Continuous Drain Current (see note 1) ........ 1.7A
Peak Drain Current (see note 2) ............... ' 3.0A
Gate-source Forward Voltage ................. +30V
Gate-source Reverse Voltage ................. -30V
Thermal Resistance, Junction to Case .... 10.4° C/W
Continuous Device Dissipation at (or below)
25° C Case Temperature ..................... 12W
Linear Derating Factor ................... 96mW/o C
Operating Junction
Temperature Range ................ -40 to +150° C
Storage Temperature Range .......... -40 to +150° C
Lead Temperature
(1/16 in. from case for 10 sec) .... , ...... , +300° C

CHIP TOPOGRAPHY

Note 1. Tc ~ 25° C; controlled by typical rDS(on) and maximum
" power dissipation.
Note 2. Maximum pulse width 80"sec. maximum duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure. "

2-15

0, TAB

(OUTLINE DWG. TO·202)

IVN5000/1 ,BN Series

O~OIb

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted), Vss = 0
IVN5000BND
IVN5001BND

CHARACTERISTICS

MIN

Drain-Source Breakdown
Voltage
Gate
IVN5000 Series
VGSllhl Threshold
IVN5001 Series
Voltage

1

-

BVoss

2

f-3

~

's

rs~

s

T
A
T
fg I
f-'- C

'"a
rlQ

~
12
f-;3

~

~
~

ffs
f2s

2.0

O.B

3.6

40

ON-State
Drain Current

TYP

MIN

O.B

2.0

O.B

2.0

O.B

3.6

O.B

3.6

IVN5000 Series
IVN5001 Series
IVN5000BND
IVN5000BNE
IVN5000BNF
IVN5001BND
IVN5001BNE
IVNS001BNF

Static DrainIVNSOOO Series
Source ON
IVNSOOI Series
Resistance
Small-Signal
IVNSOOO Series
rds(on) Drain-Source
ON Re~istance IVNSOOI Series
Forward Transconductance
gf,
Input Capacitance
Ciss
. Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-ON Delay Time
tdlon}
t,
Rise Time
Turn-OFF Delay Time
Ielloff}
tf
Fall Time

1.0
1.0

TEST CONDITIONS

MAX

BO

10

0.1

10
50
10
500

50
10
500
20
1.9
1.9
1.5

TYP

UNIT

MAX

60

0.1

IVN5000BNF
IVN5001BNF

2.0
1.2
1.9

2.5
2.S

20
1.9
1.9
1.5
2.0
1.2
1.9

2.0

2.5

2.0

1.0
1.0

0.1

2.S

20
1.9
1.9
1.5
2.0
1.2
1.9

2.S

2.0

1.0
1.0
2.5

10
50
10
500

VGS

=0, '10 = 10~A

Vos

=VGS,

V

= lmA

10

VGS = 15V, Vos 0
VGS = 15V, Vos - 0, TA - +125°C
Vos - Max. Rating, VGS - 0
Vos =0.60 Max. Rating, VGS - 0, TA - +125°C
Vos - 24V, VGS - 0
Vos - 24V, VGS - 10V

nA

~A

nA

A

2.S

Vos = 24V, VGS - .12V
VGS - 5V, 10 - 0.3A
VGS - 10V, 10 = 1.0A
VGS 7V, 10 = 0.3A
VGS = 12V, 10 - 1.0A

2.S

VGS

2.5

V

0
Y
N
A
M
I
C

170

1.9

2.S

1.9

2.S

1.9

2.S

2.0

2.S

2.0

( 2.5

2.0

2.S.

VGS

1.9

2.S

1.9

2.S

1.9

2.S

VGS

2BO
40
27
6

SO
40
10

2BO
40
27
6
2
2
2
2

170
SO
40
10
S
S
S
S

170

2
2

S
S
S
S

2
2

2BO
40
27
6
2
2
2
2

VGS

il

mil
SO
40
10
S
S
S
S

Vos

10

= 12V
= 10V
= 12V
=24V,

= 1.0A

10 = 1.0A
f = 1KHz

=O.SA, f = 1KHz

10

Vos = 24V, VGS
f = lMHz

pF

(Note 1)

= 10V

rOS(on)

f--

f21

O.B

Drain Current

Vollage

17

~

1010nl

MIN

Zero Gate Voltage

VOS(on) Saturation

IS
f16

~

loss

MAX

Gate-Body Leakage

Drain-Source

'f-'-'
14

lB

IGSS

TYP

IVN5000BNE
IVN5001BNE

=0

(Note 2)

See Switching Times Test

ns

(Note 2)

Circuit, page 2-42.

Nole 1, Pulse test - BO~sec, 1% duty cycle.
Nole 2. Sample test.

THERMAL RESPONSE

wN

~~

w 0
in"

'"

~~

;21<

5~

w
u

~~se-;:+

~sec~

IVN5001SNF

10

100

VDS DRAIN - SOURCE VOLTAGE (VOLTS)

POWER DISSIPATION DERATING

t,/t2

3.6
0.0 1
0.01

~
...

1111111
0.1

10

100

1000

'~"

:2

t1 - TIME (msec)

3.0

0

2.4

;;:
iii

1.B

;::

~
i\NFINITE HEAT SINK
,40°C!W

\

0

li

~

FREE AIR \

a: 1.2

~ 0.6
I

a9 o
Note: For other 5000 family characteristic curves, see page 2-41.
2-18

p;;;;;
o

~~

40

80

120

160

200

·IVN5000/1 TN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

These devices are non-zener improved equivalents of
the following series.

• High speed, high current switching
• High gain-bandwidth product
• Inherently temperature stable

Original Type No.
Zener Protected

Original Type No.
No Zener Protection

Intersil Equivalent Type No.
Non-Zener or Preferred
Replacement

VN30AB
VN35AB

• Extended safe operating area
• Simple DC Biasing

VN35AK
VN66AK

• Requires almost zero current drive

VN67 AB
VN67 AK

APPLICATIONS

VN89AB
VN90AB

• High current analog switches

VN98AK
VN99AK

• RF power amplifiers

2N6659
2N6660
2N6661

• Laser diode pulsers
• Line drivers
• Logic buffers

IVN5001TND
IVN5001TND
IVN5000TND
IVN5000TNE
IVN5001TNE
IVN5000TNE
IVN5001TNF
IVN5001TNG
IVN5000TNG
IVN5000TNG
IVN5000TND
IVN5000TNE
IVN5000TNG

SCHEMATIC DIAGRAM

(OUTLINE DWG. TO-39)

• Pulse amplifiers

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-source Voltage
IVN5000TND, IVN500HND ..................
IVN5000TNE, IV~500HNE .....•............
IVN5000TNF, IVN500HNF ..................
IVN5000TNG, IVN500HNG ....... , .........
Drain-gate Voltage
IVN5000TND, IVN500HND ..................
IV.N5000TNE, IVN500HNE ..................
IVN5000TNF, IVN500HNF ..................
IVN5000TNG, IVN500HNG ................

40V
60V
80V
90V
40V
60V
80V
90V

SOURCE

Body internally connected to source.
Drain common to case.

Continuous Drain Current (see note 1) ........ 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Gate-source Forward Voltage ................. +30V
Gate-source Reverse Voltage ................. -30V
Thermal Resistance, Junction to Case. . . . 20° C/W
Continuous Device Dissipation at (or below)
25° C Case Temperature .................. 6.25W
Linear Derating Factor ................... 50mW/o C
Operating Junction
Temperature Range ............... -55 to +150° C
Storage Temperatu re Range ......... -55 to +150° C
Lead Temperature
(1/16 in. from case for 10 sec) ............ +300° C

CHIP TOPOGRAPHY

Note 1. Tc ~ 25' C; controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Maximum pulse width BOl'sec. maximum duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

2·19

GATE

II

IVN5000/1 TN Series
ELECTRICAL CHARACTERISTICS (TA

= 25°C unless otherwise
IVN5000TNE
IVN500HNE

CHARACTERISTICS

MIN

TYP

noted), VBS

IVN5000TNF
IVN500HNF

MAX

MIN

2.0
3.6

0.8
0.8

TYP

=0

IVNSOOOTNG
IVN500HNG

MAX

MIN

2.0
3.6

0.8
0.8

TYP

TEST CONDITIONS

MAX

STATIC
BVDSS

Drain-Source Breakdo~n
Voltage-

VGS{th)

Gate
Threshold
Voltage

IGSS

40

lVN50DO Series
IVN5001 Series

60
2.0
3.6

0.8
0.8
0.1

Gate-Body Leakage

80

0.8
0.8

10

0.1

50

10

90

0.1

50

10

VGS = 0,10 = 10 p.A

2.0
3.6
0.1

V

10

50

50

Vas = VGS, 10 = 1 rnA
VGS - 15V, VDS - 0

nA

VGS - 15V, VDS -,0,

TA = +125"C·
10

loss

Zero Gate Voltage
Drain Current

IO(on)

ON-State
Drain Current

IVN5000 Series
lVN5001 Series

Drain-Sourc.e
Saturation
Voltage

IVN5000 Series I - -

VOS(on)

10
500

500
20

raS(an)

. Static DrainSource ON
Resistance

1.0
1.0

1.9
1.9

1.0
1.0

1.5

1.0
1.0

1.9
1.9
1.5
2.0

2.5

2.5

1.9

2.5

1.2
1.9

2.5

2.0
1.9

2.5

2.0

2.5

1.9

2.5

2.0
1.9

2.5

2.5

2.0

' 2.5
2.5

2.0
1.9

2.5

1.9

2.5

IVN500 1 Series

11VNSOOO Series

20
1.9
1.9

"A
nA
A

1.5

2.5

1.9

IVN5000 Series

20
1.0
1.0

1.5
2.5

10
500

500

2.0
1.2

'2:0
1.2

IVN5001 Series

20
1.9
1.9

10

2.0
1.2
1.9

2.5

2.0
1.9

2.5

2.5

2.0

2.5

·2.0

2.5

1.9

2.5

1.9

2.5

V

2.5
2.5

II

VDS - Max. Rutmg~
Vas 0.80 Max. Rating.
VGS = 0, TA = +125°C
VDS - 24V, VGS = 0
VDS - 24V, VGS _IOV, 1 1
12V 111
24V, VGS
VDS
VGS - 5V, 10 - 0.3Alll
'VGS - 10V, ID - 1.0Alll
VGS -7V, 10 - 0.3Alll
12V,ID
1.0A'll
VGS
VGS = 10V
VGs-12V

J ID = 10A"
1
.

VGS =,10V
12V
VGS

10 = 1.0A '1,
If=IKHZ

1

DYNAMIC
Small-Signal
raS(an)

g~j~~~7s~~~~eIIVN5001

Series

CISS

Forward Transconductance
Input Capacitance

Coss

Output Capacitance

27

50
40

C rss

6

10

to(on)

Reverse Transfer Capacitance
Turn-ON Delay Time

2

5

I,

Rise Time

2

5

tD(offl

Turn-OFF Delay Time
Fall Time

2
2

5
5

gf,

If

170

280
40

170

280
40

170

280

170

mil

280

50

40

50

40

50

27 .

40

27

40

27

40

6

10

6

10

6

10

2

5

2

5

2

5

2
.2

5

2

5

2

5

5
5

2
2

5
5

2
2

5
5

2

II

I

VDs-24V,lo-O.5A, f =1 KHz 1'1

pF

VDS = 24V, VGS = 0
f ~ lMHz
(see note 2)

ns

See Switching Times Test
Circuit, page 2-42
(see note 2)

Note 1. Pulse test - 80llsec, 1% duty cycle.
Note 2. Sample test.
'

THERMAL RESPONSE

DC SAFE,OPERATING REGION
TC = 25° C

IVN50DOTND
IYNS001TND

IVN5000TNE
IYN5001TNE
IVN5000TNF
IVN5001TNF

IVN5000TNG

IVN500HNG

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

,
t, -

TIME

5

{msec~

z
9

6

' \ INFINITE HEAT SINK
10,4'Ctw

'\,

3 -FREE AI 1=1

_'04°C/W
0

Note: For other 5000 family characteristic curves, see page 2-41.
2-20

~

1'-

-+40
+80
+120
+160
T - TEMPERATURE ('C)

+200

D~OIb

IVN5001 AZ Series
n-Channel Enhancement-mode
Vertical Power MOSFET

APPLICATIONS

FEATURES
,. High speed, high peak current switching

• LED and lamp drivers
wide~band

• Inherent current sharing capability when paralleled

• High gain,

• Directly interfaces to CMOS, DTL, TTL logic

• High speed switches

• Simple, straight-forward DC biasing,

• Line drivers

• Inherent protection from thermal runaway

• Logic buffers
• Pulse amplifiers

• Reliable, low cost plastic package

amplifiers

81'

..---~
(OUTLINE DWG. TQ-237)
SCHEMATIC DIAGRAM
DRAIN

ABSOLUTE MAXIMUM RATINGS

~-~~-,

(TA = 25° C unless otherwise noted)
Drain-source Voltage
IVNS001 AZE ................................ 60V
IVN5001 AZF ................................ BOV
Drain-gate Voltage
IVN5001 AZE ................................ 60V
IVN5001 AZF .................... " . ; . . . . . . ... BOV
Continuous Drain Current (see note 1) ......... O.SA
Peak Drain Current (see note 2) ......... : ..... 2.0A
Gate-source Forward Voltage .... ; ............. +15V
Gate-source Reverse'Voltage ................. "-0.3V
Thermal Resistance, JUllction to Case ...... 62.5°C/W
Continuous Device Dissipation at (or below)
25°C' Case Temperature ..................... 2.0W
Linear Derating' Factor .................... 16mW/oC
Operating Junction
Temperature Range ................ -40 to +150°C
Storage Temperature Range .......... -40 to +150°9
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C

I

I
I

,

(see note 3)
I

GATE

_J
SOURCE

Body internally connected to source
Drain common to tab

CHIP TOPOGRAPHY

Note 1. Te'= 25°C; controlied by typical rOS(on) and maximum
~ower dissipation.
Note 2. Maximum pulse width 80!,sec, maximum duty cycle 1.0%:
Note 3. The Drain·source diode is an integral part of the MOSFET
structure.

2·21

S

G

0

IVN5001 AZ Series
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted), Vas
IVNS001 AZF

IVNS001 AZE
CHARACTERISTICS
1

~

I-s
f--s

r--r

r--s
t-g

VGSllh)

Drain-Source Breakdown Voltage
Gate Threshold Voltage

IGSS

Gate-Body Leakage

loss

Zero Gate Voltage
Drain Current

BVoSS

~

f--T

S
T
A
T
I
C

10 on

ITo
r-11

rOSlon)

12

rds(on)

14
1"5
16
17
1&

WTo

0

gls

Y
N
A
M

Giss

I
C

TYP

MAX

MIN

60
2.5
100

0.8
0.1

TYP

Coss

erss
tdlon)
t,
Idloff)
II

ON-State Drain Current
Drain-Source
Saturation Voltage
Static Drain-Source

1.0

ON Resistance
Small-Signal Drain-Source
ON Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time

170

1.9
1.2
1.9
1.9
1.9
280
40
27
6

MAX

TEST CONDITIONS

UNIT
VGS

80
0.8

500

2.5
100
500

10
500

10
500

0.1

20

VOSIO~)

13

MIN

=0

20
1.0
3.0

3.0

3.0

1.9

3.0

3.0

1.9

3.0

280
40
27

50
40

6

10

170

JLA
nA

1.9
1.2
1.9

50
40
10

V
nA

5
5
5

2
2
2

5
5
5

2

5

2

5

0, 10

~

10JLA

1mA
VOS
VGs.lo
0
VGS
15V. VOS
VGS - 15V, VOS - 0, TA - +125°C
Max. Rating, VGS
0
VOS
VOS - 0.80 Max. Rating, VGS ~ 0, TA

~

+125°C

VOS - 24V, VGS - 0
12
24V, VGS
VOS
VGS ~ 7V, 10 ~ 0.3A

A

2
2
2

~

II

(Note 1)

VGS - 12V, 10 - 1.0A
VGS ~ 12V, 10 ~ 1.0A

n

VGS ~ 12V, 10 "' 1.0A, f ~ 1KHz
~

24V, 10

~

0.5A, f

~

mU

VOS

pF

VOS ~ 24V, VGS
f ~ 1MHz

ns

See Switching Times Test
Circuit, page 2-42

~

1KHz

0

(Note 2)

(Nole2)

NOTES: 1. Pulse test -60 /J.s pulse, 1% duly cycle.
2. Sample Test.

DC SAFE OPERATING REGION
Tc = 25°C

THERMAL RESPONSE

10

~
:E
!!.

0-0.5

-

--

....+:='-

..-

0"::'y

/'

0.62

I
I-

tp 1msec
5msec

1('- l'10.,ec

1.0

~

500p,ec=ff
100·'""it

DC

a:
a:

::>
(,)

z

V

JU
~I

""
0.1 '§§l:VN5000AND
IVN500'AND

a:
0

~:VN500'OANE

E

---l:VN500'OAN'F

"

D·t-

--j~VN5001ANE

IVN5001ANF
0.0 1
10
100
1.0
VDS DRAIN - SOURCE VOLTAGE IVOLTS)

\

12-

DUTY CYCLE, 0 '" t1/t2

0.0 1
0.01

POWER DISSIPATION
DERATING

I1I1111
10

0.1

100

1000

t1 - TIME (msec)

~

i

2.4r--'\"""-"T'""--'---'---'
2.01-....,rt---+--i--l---~

T

~, 1,6

~

1.21---+--'\---1--+---1

iii

oa: O.B I---+---t--'<:-I--f---t
w

~ 0.4F=~""""'+'--Ir-f---t
~

Note: .For other 5000 family characteristic curves, see page 2-41.
2-22

0

0~--~--~--~~~~~2~00·

IVN5200/1 HN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Inherent current sharing capability when paralleled

• DC to DC inverters

• Directly interfaces to CMOS, DTL, TTL logic

• Logic buffers

• Simple, straight-forward DC biasing

• Line drivers

• Extended safe operating area

• Motor controllers

• Inherently temperature stable

• Power amplifiers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(OUTLINE DWG. TO-66)

(T A = 25° C unless otherwise noted)

Drain-source. Voltage
IVN5200HND, IVN5201 HND .................. 40V
IVN5200HNE, IVN5201 HNE ............. , ..... 60V
IVN5200HNF, IVN5201HNF ................... BOV
Drain-gate Voltage
IVN5200HND, IVN52Q1 HND .: ................ 40V
IVN5200HNE, IVN5201HNE ................... 60V
IVN5200HNF, IVN5201HNF ................... BOV
Continuous Drain Current ..................... -5.0A
Peak Drain Current (see note 1) ................ 12A
Gate-source Forward Voltage .................. +30V
Gate-source Reverse Voltage .................. -30V
Thermal Resistance, Junction to Case ...... 4.17°C/W·
Continuous Device Dissipation at (or below)
25°C Case Temperature ...................... 30W
Linear Derating Factor ................... 240mW/oC
Operating Junction
Temperature Range ................ -55 to +150°C
Storage Temperature Range .......... -55 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C

SOURCE

Body internally connected to source.
Drain common to case.

CHIP TOPOGRAPHY

mB f+lImB

-I'

Note 1. Maximum pulse width 80ltsec, maximum duty cycle 1.0%
SQURCE

Note 2. The Drain·source diode is an integral part of the MOSFET
structure.

GATE

2-23

IVN520011 HN Series
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted) , Vss
IVN5200HND
IVN5201HND
MIN TYP MAX

CHARACTERISTICS

1

BVoss

-2
-

VGS(th)
3

-;;5
'"'6

IGSS
T

loss

10(on)

C

16

17

-

rds(on)

18

'19~
N

~A

~M
i7231

~C

.

ON-State

Drain Current

Static Drain'roS(on) Source ON

15

-

~

Drain Current

UNIT

TEST CONDITIONS

VGS = 0, 10 = 1OOl'A

80

IVN5200 Series

0.8

2.0

0.8

2.0

0.8

2.0

IVN5201 Series

0.8

3.6,

0.8

3.6

0.8

3.6

Vos = VGS, ID = SmA
0.2

20

0.2

100
100
5.0

Zero Gate Voltage

Drain-Source

14
...:..c..

'2s

60

=0

IVN5200HNF
INV5201HNF
MIN TYP MAX

V

Gate-Body Leakage

VDS(on) Saturation
Voltage

13

'2o

40

S

7 A
'"'6
9 TI

1"0
..."
12

Drain-Source Breakdown
Voltage
Gate
Threshold
Voltage

IVN5200HNE
IVN5201HNE
MIN TYP MAX

.'
IVN5200 Series

5.0
5.0

IV
IV
OHNE
IV
OHNF
1HND
IV
INV5 1HNE
IVN5201HNF

IVN5200 Series

100
10
10
1.5
1.9

2.5

1.2
1.8

2.5

0.2

20

5.0
5.0

100
10

20

nA

1.9
1.2
1.8

2.5

VGS = 10V

100
100

I'A
rnA
nA

5.0
100
5.0
5.0

10
1.5

' 10
10
1.5

2,5

1.9
1.2
1.8

2.5

VGS = 12V, VDS = 0
VGS = 12V, VDS - 0, TA - +125'C
VDS = Max. Rating, VGS = 0
VDS - 0.80 Max. Rating, VGS - 0, TA = +125'C
VDS - 24V, VGS = 0
VDS = 24V, VGS = 10V
VDS = 24V, VGS = 12V
VGS - .5V, ID = 2.0A
VGS - 10V, 10 = 5.0A
VGS = 7V, ID - 2.0A
(Note 1)
VGS = 12V, ID = 5.0A

100
100
5.0

A

2.5

V

0.38

0.50

0.38

0.50

0.38

0.50

0.36

0.50

0.36

0.50

0.36

0.50

10 = 5.0A
VGS = 12V

Resistance

IVN5201 Series

Small-Signal
Drain-Source

IVN5200 Series

0.38

0.50

0.38

0.50

0.38

0.50

VGS = 10V

10 = 5.0A

ON Resistance

IVN5201 Series

0.36

0.50

0.36

0.50

0.36

0.50

VGS = 12V

f = 1KHz

1.8
210
160
45
4
4
4

250
200
60
20
20

gf,

Forward Transconductance

Ciss
Coss

Input Capacitance
Output Capacitance

Crss

Reverse Transfer Capacitance

td(on)
tr
td(off)
tf

Turn-ON DelJlY Time
Rise Time
Turn-OFF Delay Time
Fall Time

1.0

1.8
210
160
45
4
4
.4
4

1.0
250
200
60
20
20
20
20

1.8
210
160
45
4
4
4
4

1.0
250
200
60
20
20
20
20

4

n

mho

20
20

VDS = 24V, ID = 5.0A, f = 1KHz

pF

VOS = 24V, VGS = 0
f = 1MHz

ns

See Switching Times Test
Circuit, page 2-44.

10

~

(Note 2)

4.0A
(Note 2)

Note 1. Pulse test - 80l'sec, 1% duty cycle.
Note 2. Sample test.

I
THERMAL RESPONSE

;.--:
'~ilUImRml

POWER DISSIPATION vs
CASE TEMPERATURE

~DO.5

\ INFI~ITE HJAT SINiK

V

' \ 4.17'CIW

-

1\

\

1,\
+40

+80

+120

+160

+200

Tc - CASE TEMPERATURE I'CI

DC SAFE OPERATING REGION
Tc = 25°C

lOO E~""'F'EEm!E~3~I!l!ll
;: 10 --+-1"
~

t, - TIME (msec)

==;;500~se'c:t=tt::tt

::::::::.!msec
tp - 5msec

:::E:

100,usec

~
cc
cc

c--)-t- D

~

r--IVN5200HND

::>

~~I~V~N5~2~01~H~NijD'~~111

.~« 1.0 F:~~~~~~~~~
t--~VN5200HNF

_0

1.0

0.'

Note: For other 5200 family characteristic curves, see page 2-43.

2-24

10

IVN520'HNF

100

Vos - DRAIN-SOURCE VOLTAGE (VOLTS)

IVN5200/1 KN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

~PPLICATIONS

• High speed, high current switching

• Switching power supplies

• Inherent current sharing capability when paralleled

• DC to DC inverters

.• Extremely low drive currents

• CMOS and TTL to high current logic

• Simple, straight-forward DC biasing

• High current line drivers

• Extended safe operating area

• Motor controllers.

• Inherently temperature stable

• Power amplifiers

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)
Drain-source Voltage
IVN5200KND, IVN5201 KND ... , , ..... , .... , . , , 40V
IVN5200KNE, IVN5201 KNE ..... , ............. 60V
IVN5200KNF, IVN5201 KNF .............. " ... 80V
Drain-gate Voltage
IVN5200KND, IVN5201 KND .................. , 40V
IVN5200KNE, IVNS201KNE ................... 60V
IVN5200KNF, IVN5201 KNF ,." ..... ,', ... , ... 80V
Continuous Drain Current ..... , ....... , ... , , ,. 5.0A
Peak Drain Current (see note 1) , ...... , ... ,., .. 12A
Gate-source Forward Voltage ...... , .... , ..... , +30V
Gate-source Reverse Voltage. , ... , ....... , .. , . -30V
Thermal Resistance, Junction to Case .. , .... 2,5°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature. , , . , ... , . , , ....... , .. 50W
Linear Derating Factor .. , ,' .. , , ..... " , .. . 400mW/oC
Operkting Junction
. .
Temperature Range ..... ,. , ....... , -55 to +150°C
Storage Temperature Range ... " ..... -55 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) , ...... , ..... +300°C

(OUTLINE DWG. TO-3)

DRAIN

~

J~~~~o""'

"". llJ
SOURCE

. Body internally connected to source
Drain common to case

CHIP TOPOGRAPHY

Note 1. Maximum pulse width BOl-'sec, maximum duty cycle 1.0%
Note 2. The Drain-source diode is an integral part of the MOSFET
structure.

2-25

SOURCE~
GATE~

3 DRAIN

IVN5200/1 KN Series

D~DIL

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted);
IVN5200KND
IVN5201KND
MIN TYP MAX

CHARACTERISTICS

1

-2
-3

~

BVoss

VGSI'hl

Drain-Source Breakdown
Voltage
Gate
IVN5200 Series
Threshold
IVN5201 Series
Voltage

'-;:-

IGSS

Gate-Body Leakage

7 A
raT
rgl
r-;-oC

loss

Zero Gate Voltage
Drain Current

1010nl

ON-State
Drain Current

~S
~T

"IT
~
~

VOS(on)

~

I15

I-

ros{on)

16

17

I-

~D
~Y

20 N
21A
22M
-EI
C

rds(on)

gf.
Ciss

Coss
Crss

2'4

ldIon I
t,

26

tdloffl
tf

2s

Drain-So,uree
Saturation
Voltage
Static DrainSource ON
Resistance
Small-Signal
Drain-Source
ON Resistance

40

60

VBS =

0

IVN5200KNF
INV5201KNF
MIN TYP MAX

UNIT

SO

TEST CONDITIONS

VGS • 0, 10' 100l'A

O,S

2.0.

O.S

2.0

0.8

2.0

O.S

3.6

0.8

3.6

O.S

3.6

V
VOS • VGS, 10 • 5mA

0.2

IVN5200 Series
IVN5201 Series
IVN5200KND
IVN5200KNE
IVN5200KNF
IVN5201KND
INV5201KNE
IVN5201KNF

IVN5200KNE
IVN5201KNE
MIN TYP MAX

5.0
5.0

100
10
10
,1.5
1.9
1.2
1.S

20
100
100
5.0

0.2 '

2.5

100
10
10
1.5
1.9
1.2
1.8

5.0
5.0
2.5

20
100
100
5.0

0.2

5.0
5.0

2.5

nA

VGs' 12V, Vos - 0
VGS • 12V, VOS • 0, TA • +125'C

2.5

VOS • Max. Rating, VGS • 0
VOS - 0.80 Max. Rating, VGS' 0, TA' +125'C
VOS - 24V, VGS - 0
VOS • 24V, VGS • 10V
VOS • 24V, VGS • 12V
VGS • 5V, 10 • 2.0A
VGs' 10V, 10 • 5.0A
VGS - 7V, 10 - 2.0A
(Note 1)
VGS - 12V, 10 • 5.0A
VGs'10V

100
10
10
1.5
1.9
1.2
1.8

2.5

20
100
100
5.0

I'A
mA
nA
A

2.5

V

IVN5200 Series
IVN5201 Series

0.3S

0.50

0.38

0.50

0.38

0.50

0.36

0.50

0.36

0.50

0.36

0.50

IVN5200 Series
IVN5201 Series

0.3S

0.50

0.38

0.50

0.38

0.50

VGs'10V

0.36

0.50

0.36

0.50

0.36

0.50

VGS' 12V .

1.S
210
160
45
4
4

250
200
60
20

Forward Transconductance

1.0

Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Ti me '
Rise Time
Turn-OFF Delay Time
Fall Time

1.8
210
160
45
4
4
4
4

1.0
250
200
60
20
20
20
20

4
4

1.0

20
20
20

1.8
210
160
45
4
4
4
4

250
200
60
20
20
20
20

10' 5.0A
VGs' 12V

n

10' 5.0A
f'lKHz

mho

Vos - 24V, 10 • 5.0A, f - 1 KHz

pF

VOS' 24V, VGS' 0, f· lMHz

(Note 2)

ns

10 = 4.0A
See Switching Times Test
Circuit, page 2-44.

(Note 2)

Note 1, Pulse test - SOl'sec, 1% duty cycle.
Note 2. Sample test.

POWER DISSIPATION vs
CASE TEMPERATURE

i

THERMAL RESPONSE

'~m6l1t1mgJ
~DO.5

V

"o

~
iii

60

50
40

\
-

~iNITE

JEATS,lK2.5°CIW

30

~

C

ffi

20

~I

10

0..0,

\

'\

0

o

+40

+80

+120

+160

+200

Tc - CASE TEMPERATURE 1°C}

DC SAFE OPERATING REGION
Tc = 25°C

t, -

TIME {msec)

O."L-1....LllW,u:o~.~~::.LUJJ,~OO

Note: For other 5200 family characteristic curves, see page 2-43.

2-26

Vos - DRAIN·SOURCE VOLTAGE IVOLTS}

IVN5200/1 TN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• High ef,iciency switching power supplies

• Inherent current sharing capability when paralleled

• Off-line switching regulators

• Directly interfaces to CMOS, DTL, TTL logic

• High speed, high current switches

• Simple, straight-forward DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature stable
• Low ON resistance in small

• High peak current pulse amplifiers
• DC motor controllers

packag~

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Drain-source Voltage
IVN5200TND, IVN5201TND ................... 40V
IVN5200TNE, IVN5201TNE ................... 60V
IVN5200TNF, IVN5201TNF .................... 80V
Drain-gate Voltage
IVN5200TND, IVN5201TND ................... 40V
IVN5200TNE, IVN5201TNE ................... 60V
IVN5200TNF, IVN5201TNF .................... 80V
Continuous Drain Current (see note 1) ......... 4.0A
Peak Drain Current (see note 2) ................ 10A
Gate-source Forward Voltage .................. +30V
Gate-source Reverse Voltage .................. -30V
Thermal Resistance, Junction to Case ....... 10°C/W
Continuous Device Dissipation at (or below)
,25°C Case Temperature .................... 12,5W
Linear Derating Factor .................. . 100mW/oC
Operating Junction
.
Temperature Range ................ -55 to +150°C
Storage Temperature Range .......... -55 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) ........ , .... +300°C

(OUTLINE DWG. TO-39)

DRAIN

~
om

J,"".:""'

'J

ilJ
SOURCE

GATE

Body Internally connected to source
Drain common to case

CHIP TOPOGRAPHY

Note 1. Tc = 25'C; controlled by typical rDS(on)' and maximum
power dissipation.

II

-19 mil 1__

Note 2. Pulse width 80llsec. duty cycle 1,0%,
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

SOURCE

2-27

m.1

IVN5200/1 TN Series

O~OIb

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted),
IVN5200TND
IVN5201TND
MIN TYP MAX

CHARACTERISTICS

Drain-Source Breakdown
BVoss
Voltage
Gate
IVN5200 Series
VGSlthl Threshold
IVN5201
Series
Voltage

1

-2
'3

4'

'5
16 TS
r-t
I-- A
~

T
I
C

9

To~

IGSS

Gate-Body Leakage

loss

Zero Gate Voltage
Drain Current

IO(on)

ON-State
Drain Current

Drain-Source
VOS(on l Saturation
Voltage

~

~

'14
'-'-'15

r16

fOS(onl

17

r18

"19
'20

12,~

~
~
~

rds(on)

D
Y
N
A
M
I
C

gf,
Ciss
Coss
C rss
td(on)

tr
td(off)

'2s

tf

40

VGS = 0, 10 =

2.0

0.8

2.0·

0.8

3.6

0.8

3'.6

0.8

3.6

5.0
5.0

IIV
I T NTNE
D
IV
TNF
IVN5201TND
INV5201TNE
IVN5201TNF

20
100
100
5.0

100
10
10'
1.5
1.9
1.2
1.8

0.2

20
100
100

0.2

5.0

0.38

0.50

0.38

0.50

0.38

0.50

0.36

0.50

0.36

0.50

0.36

0.50

0.38

0.50

0.38

0.50

0.38

0.50

VGS = 10V

0.36

0.50

0.36

0.50

0.36

0.50

VGS = 12V

1.8
210
160
45

250
200
60

5.0
2.5

2.5

2.5

2.5

1.2
1'.8

2.5

5.0
5.0

I--

i'i~ o.

1-"
WL

1f::::::F=

:JJl

V

VGS - 7V, 10 = 2.0A
VGS = 12V, 10" 5.0A

1.0

1.8
210
160
45
4
4
4
4

1.0
250
200
60
20
20
20
20

4
4
4
4

1.0

1.8
210
160
45

20
20
20
20

4
4
'4
4

VGS = 10V

250
200
60
20
20
20
20

VGS = 12V

n

mho

Vos = 24V, 10 = 5.0A, f = 1KHz

pF

Vos = 24V, VGS = 0, f = 1MHz

(Note 2)'

ns

10 ~ 4.0A
See Switching Times Test
Circuit, page 2-44.

(Note 2)

15.0

i!!

~ 12.5

~

\ tNFtNiTE HEA~ StNK
10.0 t - - ~ ,10'C/W
t-

~

P

Z

o

~

7.5

iii

vI-'

i5

fU

1-"

"z
W«
"-I"-",

Wu;

ffi

5.0

~

2.5

1

"a:

.t-

10

100

\

FREE AIR 104°CIW

--r--

1000

+80

lOa

~~~::c

'"

i
.§

tp-

100~sec

lOt/sec

~c

.L

10

a:
a:

:l

"
Z

lIers

• Simple, straight-forward DC biasing

• Power amplifiers

• Extended safe operating ar,ea

• RF amplifiers

• Inherently temperature stabl,e

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A = 25° C unless otherwise noted)

DRAIN

Drain-source Voltage'
IVN6000KNR ......... , ....... ,........... 350V
IVN6000KNS .. :.......................... 400V
IVN6000KNT '............................. 450V
Drain-gilte Voltage,
IVN6000KNR ~ ............................ 350V
IVN6000KNS .......' .................. '" . .. 400V
"iVN6000KNT ............................. 450V
Continuous Drain Current. . . . . . . . . . . . . . . . . .. 2.SA
Peak Drain Current (see note 1) ............... 7.SA
Gate-source Voltage..................... ± 30V
Thermal Resistance, Junction to Case ..... 3.0OC/W
Continuous Device Dissipation at (or below)
2SOCCaseTemperature ................. 41.7W
Linear Derating Factor ................ 333mW/OC
Operating Junction
Temperature Range ................ -55 to +150°C
Storage' Temperature Range .......... -55 to +150°C
Lead Temperature
(1/16 in, from case for 10 sec) ............. +300°C
Body-drain Diode ,Continuous Forward Current .... 3A
Body"drain DJode,Peak Forward Current ......... 10A

. . J,,:,
~ l,,·,j
.

GATE

I'''''
.L

,

'

00,"

'I

~2

SOURCE

GATE

',1

SOURCE

CHIP TOPOGRAPHY

-I9mil!+-

'ITImi'

SOURCE

Note 2. The Drain-source diode is an integral part of the MOSFET
structure.

GATE

2·31

'.

\S}
3 DRAIN

Body internally connected to source.
Drain common to case.

Note 1. 'Maximum pulse width 80/Lsec, maximum duty cycle 1.0%

,-p-

IVN6000 KN Series
ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified
LIMITS
PARAMETER
Drain-Source
Breakdown Voltage
IVN6000KNR

TEST CONDITIONS

SYMBOL
BVos

V GS =OV
10 = 100llA

MIN.

TYP.

MAX,

UNIT

350

IVN6000KNS

400

IVN6000KNT

450

V

Gate-Threshold Voltage

VGS(th)

Vos = VGS, 10 = 10 mA

Gate-Body Leakage Current

IGSS

VGS = 30 V

10

10.0

nA

Zero Gate Voltage
Drai n Current

loss

Vos= Maximum Rating, VGS = OV
TJ = 125°C

0.2

2

rnA

3.0

0

ON Drain Current l11

10(on)

Vos = 25V, VGS = 15V

Static-Drai n Source
ON Resistance l11

rOS(on)

VGS = 15V, 10 = 1A

Forward Transconductance l11

gls

Vos = 200V, 10 = 1.5A

Input Capacitance

Ciss

Output Capacitance

Coss

Reverse Transfer Capacitance

Crss

Rise Time

tr

Fall Time

tl

Drain-Source Voltage Rate of Rise

dV/dt

1.5

5

5

7
2.5

0.8

A

mho

1.0
220

300

22

30

6

10

Vos = 200V, 10 =1.0A,
VGS = 15V, Rgen = 60

5

10

5

10

Vos ,; 400V, VGS = 0

100'

Vos = 100V, f = 1.0 MHz, V GS = OV

pF
ns
ns
V/ns

Note: 1. Pulse Test: 80"s, 1'10 duty cycle.

BODY-DRAIN DIODE CHARACTERISTICS
LIMITS
TYP.

MAX.

Forward Voltage Drop

VI

Peak Forward Current = 2A

0.95

1.1

Reverse Recovery Time

trr

itwd(pk) - Irev(pk) Recovery to 50%

100

ns

Recovered Charge

Orr

TJ -

200

nC

PARAMETER

TEST CONDITIONS·

SYMBOL

150~ C,

Note: In the following curves, Vi3s is defined as the
gate-source voltage minus the threshold voltage.

VGS = VGS - Vlh

I,
2-32

Ilwd(pk) - 2A

MIN.

UNIT
V

U~UIL

IVN6000 KN Series
OUTPUT
10

CHA~ACTERISTICS

TRANSFER CHARACTERISTICS
12

·Vbs ""1011'

LV

I
I
V

1

.IVGS =
sv

Vos

c

1/

,

200V

10

Ii'

f/

I

I

/

*Vi;s'"
6V

f,

/
*~

/

4V

J

VGS =
2V

100

200

300

400

a-2

500

./

,. ~
-1

0

1

2

-

3

4

5

6

7

S

9

TRANSCONDUCTANCE CHARACTERISTIC,

TRANSCONDUCTANCE CHARACTERISTIC

Vos c200V

VOS" 200V

..-

~

/

V
1/

1

/
I

10

vos·-VOLTS

VDS - VOLTS

/'

~

V ....
./

,..

",

/

/

V

1/
J

o

o

o-2

10

V
-1

0

1

2

3

4

5

6

7

S

9

10

VGs*-VOLTS

10 -AMPS

OUTPUT CONDUCTANCE

DRAIN-SOURCE LEAKAGE CURRENT

loo0~-------.---------r.-------,

1000

vJs = 3JOV
VGS =0

100 I:--------+~<-----+------_;

I

100

/

'1

V

I

]
101:---~~-+--------+--------_;

'/

10

1
-40

V

/
-20

V
20

40

60

~O

100

TEMPERATURE -"C;

lo,-mA

2-33

V

120

140

IVN6000 KN Series )
BODY-DRAIN DIODE FORWARD
VOLTAGE CHARACTERISTIC

CAPACITANCE VI. DRAIN-SOURCE VOLTAGE

II

1

1000

'a
I
w

"

I
I
IL

VGS = 0

cgs

2

~

100

U

~

1

"

II

10

J

V

Cgd

V
00

.1

.2

.3

.4

Vos- VOLTS

.5

.6

.7

.9

.8

1.0 1.1

1.2

VSD -VOLTS

DRAIN-SOURCE BREAKDOWN VOLTAGE
VARIATION WITH TEMPERATURE

THRESHOLD VOLTAGE VS. TEMPERATURE
ID "" 1mA

1. 4

1.2

I,
Q

·w
N
:::;

1. 2

~

" ."

~

1.0

I

. >'G

cw

N

~
a:

II

V

1

8

>'f!.
a:I

" "-

......
6

0.9

V

V

I

"-

;'

... v

1. 1

:::;

NLOPE • -6.7 mV/'C

a:

II

,

V

o. 8

"I\.
-60

-40

-20

20

40

60

80

100

120

140

-40

-20

20

TJ _cC

18

V~s. 2~V
Vos =0

J

/

/
1
-40

V

I

100

0

-20

0

60

/

80

100

120

140

GATE DYNAMIC CHARACTERISTICS

GATE LEAKAGE CURRENT
1000

40

TEMPERATURE - "C

V~oy' ~0D.

10 a1A

16

50V

V

2jV

r;

4

J1

680 PFj
2

v

VJ
v
L L

0
8

63O'IpF

LL .L

6

V

375V

VJ

4

//

/

V

2

/212 pF
0

20

40

60

80

100

120

2

140

o

10

ClG -

TEMPERATURE - 'c

2-34 .

12

14

nano COULOMBS

16

18

20

IVN6000 KN Series
ON RESISTANCE vs.
JUNCTION TEMPERATURE

LARGE SIGNAL TRANSFER CHARACTERISTICS
2.0

10

)77

10'" lA

1.8

/

:::;

"
a"
z
0:

VOS=

20V

,

1.0

~

.8

e

VOS'"

J,. r-

.6

/

I .......

10

12

14

16

18

.2

20

-60

60

80

100

120

140

16

18

100

'0 =llA

v+ 25 'e
~

I

Z

40

ON RESISTANCE vs. VGs·
AS A FUN~TION OF 10

~

Q

20

-20

TJ - °c

_40,le

/"

-40

VOLTS

ON RESISTANCE VS. VGs·
AS A FUNCTION OF TEMPERATURE

L

V

"

.4

Vos'"
2V

W;,; -

+125°

'/

V

5V

~ r00

100

~-

VGS '" 4V

~

1.2

;;;

Vos=
10V

V
1

1.4

iilN

I. v
If

~

1.6

Vos50V

./

VGs*=10~

I

~

10

........

lj =+125°C .

l'-r-

l,

"-i'-

1

-2

10

12

14

rio =5A

"-

J5'e

Ilj = _400C

10-

\ ~I\, i

10 =3A

16

1
-2

18

rT

J

'0 = 1AJ

1
. 10

VGS"'-VOLTS

VGS" - VOLTS

·VGS = VGS - Vth

2-35

12

14

IVN6000 KN Series
SAFE OPERATING AREA
OPERATION IN THIS REGION IS

10.--;~_L_IM_I_TE_O_B_V_'~D~SI~DNr)______________~
SINGLE PULSE

Te • 25'C
'TJ MAX"" 150D C.,

Ro,e = 3.5' C/W I

I
I
I
I
I
I

en

ffi
ffi

..!l!,
E

.5
.4

.3
.2

Vos - VOLTS

POWER DISSIPATION vs. TEMPERATURE DERATING

TRANSIENT THERMAL IMPEDANCE

40

..

"-

NORMALIZED FOR R/JJc=3.5~CIW

S
N

:::;
"
a:

o

~

-s

N

1. 0

D. 8

o. 6
o. 4
0.2

o

0.1

0= 1.0

- t/f?

I--'/:::;;;

0-.75

'\

0

~

'0=.5
O=.~

-

~

'\

I'.
l\.

10

Vo=o

1.0

"

'I\.

-

10

100

40

1000

tp-ms

2·36

80

120

160

IVN6660-1
n-Channel Enhancement-mode
Vertical 'Power MOSFET
REPLACEMENTS FOR 2N6660-1

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers
• ' Pulse amplifiers

Inherently temperature stable
• Typical ton and tolf < 5ns

• High frequency linear amplifiers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(TA =:' 25°C unless otherwise noted)
Drain-source Voltage
.
IVN6660 ..................................... 60V
IVN6661 ..................................... 90V
Drain-gate Voltage
IVN6660 ...... ,' .............................. 60V
IVN6661 , ...... ,... . . . . . . . . . . . . . . . . . . . . . . . . .. 90V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2.0mA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .................. 100mA
Gate-source Forward (Zerier) Voltage ... , ...... +15V
Gate-source Reverse (Zener) Voltage .......... -O.3V
Thermal Resistance, Junction to Case ....... 20°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature .................... 6.25W
Linear Derating Factor ............ , ...... . 50mW/oC
Operating Junction
Temperature Range ................ -55 to +150°C
Storage Temperature Range .......... -55 to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) : ............ +300°C

(OUTLINE DWG. TO-39)

GATE

S'OURCE

Body Internally connected to source.
,Drain common to case.

CHIP TOPOGRAPHY

Note '1. Tc = 25°C; controlled by typical rOSlon) and maximum
power dissipation.
Note 2. Pulse width 80l'sec, duty cycle 1.0%.
Note 3: The Drain-source diode is an integral part of the MOSFET
structure.
.

2-37

GATE

IVN6660-1

U~UI!.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
IVN6660

CHARACTERISTIC

MIN

~
2

BVoss

Drain Source Breakdown

~

VGS(,hl

Gate Threshold Voltage

IGSS

Gate-Body Leakage

I--=-

r--1-

~

~
7

f'---=--

~
9

f-To''11
f-i2
'13
f--"'-

T
A
T
I
C

10(onl

ONCState Drain Current

Vos(onl

Drain-Source Saturation Voltage

Cds

Static Drain-Source ON-State
Resistance
Small-Signal Drain-Source
ON-State Resistance
Forward Transconductance
Input Capacitance
. Drain-Source Capacitance

C rss

Reverse Transfer Capacitance

td(onl

t,

Turn-ON Delay Time
Rise Time

td(offl
tf

Turn-OFF Delay Time
Fall Time

rds{on)

~
r=-

gfs
D
Y
N
A
M
I
C

Clss

~
24

100
2
0.3
1.0
0.9

1.0

MIN

TYP

MAX

90
90
0.8

2.0
100

O.S

Zero Gate Voltage Drain Current

lS

r-w
'21

60
60
0.8

loss

rOS(en)

7

IVN6661
MAX

S

14

f--J6
f-;?
f-1iJ

TYP

UNIT

TEST CONDITIONS
VGS = 0, 10 = lOI'A
VGS - 0, 10 = 2.SmA
Vos - VGS, 10 - lmA
VGS - lSV, VOS = a
VGS = lSV, Vos = 0: TA = 12S'Cj(Note 2)
VOS = Max. Rating, VGS = a
VOS - 0.80 Max. Rating, VGS =0, TA-12S'C
(Note 2)
VOS - 25V, VGS - a
Vos - 25V, VGS - 10V
VGS = SV, 10 = 0.1 A
VGS = SV, 10 = 0.3 A
VGS - 10V, 10 - O.SA
VGS = 10V, 10 = 1.0 A
(Note 1)
VGS = 10V, 10 = 1.0 A

V
2.0
100

O.S

sao

sao

10

10

sao

500

2.2

3.0

100
2
0.4
1.1
1.3
2.2

2.2

3.0

2.2

4.0

2.2

3.0

2.2

4.0

1.0
1.5

nA

J-"
>-:;;

r-

V

0=0.;.-"'-

wO°

2,

;;2
~

1<

o. 1

>-<.>

we..
~w

>-<.>
<.>2

w"

fU

0-0

~>-

p:l

_r-

~'"
w;;

Iw
~o:

I

'Z-

,,to

E
0rmHli . 0 =(jZ
0.0 1
0.01

0.1

10

100

1000

tl ....:. TIME (msec)

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

DC SAFE OPERATING REGION
Tc = 25°C
10

9.0

g
"

~.
2

0

~

I

5

6.0 ---"
4.5

150:

Ci 3.0

;;'
0:

o

51N

"o
0:

1

0.1

IS

0_

1

l'\...

+40
+80
+120 +160
T - TEMPERATURE ('C)

'" '"
",lll

E
+200

i'"

1

2

2

>

'"

0.9

"'"

~

Z

0

"

1.1

:::i
:;;

<.>
2

W

208'CIW

1.2

...
...

::>

0:

2

~f

I

0:

'{

;: 1.5 r--FREE A!R" "

00" .250 /.Is:.l00 /.IS 10

DC

>-

INFINITE HEAT SINK

\...20'CIW

iii

.0

~~!"s

f:;;

7.5

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

".,

0.8

~>

O.ot
1

10

100

VD• - DRAIN-TO-SOURCE VOLTAGE (VOLTS)

2-38

-40 -20 0 20 40 60 80100120140
TEMPERATURE _

°c

O~OlL

2N6660-1
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature stable

• Pulse amplifiers

• Typical ton and toft < 5ns

• High frequency linear amplifiers

ABSOLUTE MAXIMUM RATINGS

SCHEMATICJ)IAGRAM

(TA = 25°C unless otherwise noted)
Drain-source Voltage
IVN6660 ... : .. ; ..... : .. '...................... 60V
IVN6661 .... : .................................. 90V
Drain-gate Voltage
IVN6660 ..................................... 60V
IVN6661 ...................................... 90V
Continuous Drain Current (see note 1) .... , .... 2.0A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2.0mA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .................. 100mA
Gate-source Forward (Zener) Voltage .......... +15V
Gate-source Reverse (Zener) Voltage .......... -0.3V
Continuous Device Dissipation at (or below)
25°C Case Temperature .... , ............... S.33W
Linear Derating Factor .................... 67mW/oC
Operating Junction
Temperatljre Range ................ "-55 to +150°C
Storage Temperature Range .......... -55 to +150°C
. Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C

(OUTLINE DWG. TO-39)

GATE

Body internally connected to source.
Drain common to case.

CHIP TOPOGRAPHY

r
I

Nole 1. Tc = 25°C; controlled by typical rOS(on), and maximum
power disSipation.
.
Nole 2. Pulse width BOllsec. duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

2-39

GATE

2N6660-1·

O~O[l,'

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
IVN6660

CHARACTERISTIC
1

MIN

~

BVoss

Drain Source Breakdown

-T

-t-

VGSI'h)

Gate Threshold Voltage

~

IGSS

Gate-Body Leakage

TYP

IVN6661
MAX

60
60
0.8

2.0
100

I
l
-"-- s
T
A

loss

Zero Gate Voltage Drain Current

Il
g-

T
I
C

10(onJ

ON-State Drain Current

VOSlon)

Drain-Source Sflturation Voltage

W
:-iT
'12

~
r--

fDSlon I

15

rdslonl

r-;s
f-;r
r-;-a

1-;9

!--fafT,-

'22
c-=-

100
2
0.3
1.0
0.9

1.0

Static Drain-Source ON-State

14

gls
Ciss

D
Y
N
A

M
I
C

~
24

Resistance
Small-Signal Drain-Source

0.8

2.0
100

0.5

500
10

500
10

500

500
100

La

2.2

3.0

2.2

4.0

2.2

3.0

2.2

4.0

1.5

nA

MA
nA
A

3.0

1.6
4.0

V

TEST CONDITIONS
VGS = 0, 10 = lOMA
VGS = 0, 10 - 2.5mA
Vos - VGS, 10 - lmA
VGS - 15V, Vos - a
VGS - 15V, VOS = 0, TA = 125°C (Note 2)
VOS - Max. Rating, VGS - a
Vos c 0.80 Max. Rating, VGS = 0, TA -125°C
(Note 2)
VOS - 25V, VGS - a
I
Vos - 25V, VGS - 10V
VGS - 5V, 10 0.1 A
VGS - 5V, 10 = 0.3 A
VGS = 1OV, 10 - 0.5A
VGS - 10V, 10 - 1.0 A
(Note 1)
VGS = 1OV, 10 = 1.0 A

11

ON-State Resistance

170

Forward Transconductance

250

Crss

Reverse Transfer Capacitance

tdlen)

Turn-ON Delay Time
Rise Time

2

Turn-OFF Delay Time
Fall Time

It

UNIT

V

2.2

CdS

tdlofll

MAX

2
0.4
1.1
1.3
2.2

Input Capacitance
Drain-Source Capacitance

t,

TYP

90
90
0.5

7

MIN

170

250

'50 )--.

50
40
10

Note 1. Pulse test - 80l'sec pulse, 1% duty cycle.

VGS=10V,IO=1.0Ajl=
mil

40
10
35

2

35
5
5

2
2

5
5

2
2

5
5

2
2

5
5

pF

Vos = 24V, 10 - 0.5

A1 1KHz

VGS = 0, Vos = 25V, f = 1.0MHz
VGS - 0, VOS = 24V, f = 1.0MHz
VGS - 0, VOS - 0, f -1.0MHz

(Note 2)

ns

Note 2, Sample test.

THERMAL RESPONSE
.1

0-0.5

.

t:;::::

....

-' Lilli

I--'"

0=0.2_ ....

1/

o=o.~r-

t-"
.1

fU
~tl-1 . I

/'

0=0

1--1-

- t2-

DUTY CYCLE, 0 "" t,/t 2

0.0 1

0.01

Jlillill JJ

10

0.1

1000

100

. t, - TIME (msec)

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

DC SAFE OPERATING REGION
Tc = 25°C
10

9.0

~
I-

"z

~

7.5

;;
0

;.:

...

1.2

·filN

...

OC

f:i

"
::;

a:
a:

4.5

""oa:

::J

u

3.0

~

~

1.5

"

a:

O. 1

>'&
0_

I

"''''
"'~
l~

0.0 1
0

+40
+80
+120 +160
T - TEMPERATURE 1°C)

+200

1

10

100

Vos - ORAIN·TO·SOURCE VOLTAGE (VOLTS)

2-40

'"

0.9

"

fo"'"

1

I

E

0

1.1

~

z

Z

0

~

00 p.s .250 p.s::100 p.s 10

Ti

I-

6.0

;:

iii

~~~s

"'

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

"

"

O.B
... 40 -20 0

20 40 60 80 100 120140

TEMPERATURE _

°c

5000 Family Typical Performance Curves
(25°C. unless otherwise stated)

SATURATION CHARACTERIST!CS

OUTPUT CHARACTERISTICS
, iii 2.4
0..
:;:

5

--

'2.0

PULSE TEST -BOp Sec,
1% DliTY CYCLE
'-

I

~
w

1.S

7V

O.B

:9

~ 1.6

-

-

/V

:5

// V

5V r4V t-3V
0
o
10
20
30
40
50
VDS DRAIN-SOURCE VOLTAGE - (VOLTS)

Z

Q

E

w

'

u

a

1.2

~~
::l«

o

V
/.

0.4

Z
o

C

0

1.2

~?:. 0.8

a:

o
Z

v

o

/

~,~
ZO

a: O.B

o
z

1.S

ww

/

I

5V
4V t-3V
1.0
2.0
3.0
4.0
5.0
VDS DRAIN-SOURCE VOLTAGE - (VOLTS)

z
00

I
V

~

o

~
a:

2.0
4.0
S.O
B.O
10.0
VGS GATE.sOURCE VOLTAGE - (VOLTS)

0.4

CAPACITANCE vs
DRAIN-SOURCE VOLTAGE

u:
.e-

BO

i

w

u

z

«

SO

I-

U

«
0..
«
u

40
20

Vos =24V
VGS = 0 '
f= 1 MHz

r- r-

1.0

1
I

\-- -

w
u

~

~

V

VVGS=5V

~Srol
o
-40

+40
+80 +120 +lS0
T - TEMPERATURE - ('C) ,

VDS,24V
f= 1KHz
PULSE TEST 801' Sec.,
./
1% DUTY CYCLE

V

~
I-

~\

1 \\

U

5

~

I"'-

1\
\

I"
o

VGS=5~

~

~V

V
/v.

OUTPUT CONDUCTANCE
vs DRAIN CURRENT

120

t-100 t--

~

VGS=10V

ilia:

/

z

':iii
o

..-

~

I-

a:
a:

0

~
I"":

SV r-

«

\-PULSE TEST-BOp Sec.,
5 2.0 r-l%
DUTY CYCLE
I
1.S

c--

7V t--

' / / f-""
;..-

2.0

z

VDS=2~V

iii

0.4

L..- f- -8V

NORMALIZED DRAINSOURCE ON RESISTANCE
vs TEMPERATURE

iii 2.4
0..

O.B

z

o

_9V

/1-'

z

TRANSF:ER CHARACTERISTIC
:;:

V

a:

::l
'f 1.2

SV t--

o 0.4

VGS=
_10V-'

~

~

z

Z
o

_PULSE TEST-80IlSec,
I 2.0 _'1% DUTY CYCLE

BV -

z

o

±9V

a 1.2
~

~ 2.4

!

10V_

a:
a:

O~OIl.

--

0.1

z
o
U

C;'L

I::l
0..

I

5o
J

Coss

:-~

C,"

o
10
20
30
40
50
VDS DRAIN-SOURCE VOLTAGE - (VOLTS)

2-41

./

.01
0.01
0.1
1.0
ID(ON) ON DRAIN-CURRENT - (AMPS)

O~OlL

5000 Family Typical Performance Curves
(25°C. unless otherwise stated)
DRAIN-SOURCE ON
RESISTANCE vs
GATE-SOURCE VOLTAGE

u;
:;;
:t:

Q
I

~

~
en
w

\

VDS= O.w

VDS= lbv
PULSE TEST -200jlSoc.,

::::l

is

(.)

w

Co)

mi"

300

Z

;i

z

<{

~ 400

::::l

a

200

~

11

10

100

100

Z

J

200

f-

a
~
;;:
a:
ou.

7

o

o

0.2

0.4

0.6

0.8

1.0

/

100

If

../

0

0
2.0
4.0
6.0
.0 10.0
,;; VGS GATE-SOURCE VOLTAGE - (VOLTS)

1.2

ID(ON) ON DRAIN CURRENT - (AMPS)

VGS GATE-SOURCE VOL TAGE-(VOLTS)

1/

en

;i

f-



...

~

:;;

0.9

~

'"

T'"

0.8

~O%

-40 -20 0

20 40 60 80100120140

TEMPERATURE _ °C

SWITCHING TIME TEST CIRCUIT
+24V
+24V

o

10KO

3 msec

15V

H r
n

OV..J

OSCILLOSCOPE
TEKTRONIX 7904
OR EOUIVALENT

LJ
KI
2200

2-42

5200 Family Typical Performance Curves
(25°C. unless otherwise stated)
OUTPUT CHARACTERISTICS
_
~

9.0

......

~

7.5

~

6.0

.12

I

Cii 9.0
::;:
~ 7.5

«

~

2

1.5

1

]
_0

l
I

I

4.5

o

3.0

«a:

5~

I

3.0

u
2

1

C
.£

3V
1

0

o

10

20

30

40

50

°

60

w

~

7.5

I1%

~ 6.0

~UTY

4.5

g;

3.0

«

~

::l::;:

"10

~

.s,
w

\

300

2

~
U 225

«
0«
u

~
-'=

I-

\\.

=
-

=

..sw

r-

2

/

fv'=5V
GS

0

+40

+80 +120 +160

10

VOS =24V
f - 1kHz
PULSE TEST

80jlsec

=1% DUTY CYCLE

::l

o
2

c.

o

I '" I-

.......
l - I-

"- .......

-fo",--

0-

I::l

IcJ_

r- ,......

10

20

30

40

50

i.-"

U
I::l

o

1
~B

o

o

100

E

u

\

75

,b

10~

T -TEMPERATURE (OC)

~
U

"-

150

6.0

OUTPUT CONDUCTANCE
vs DRAIN CURRENT

~

1

u

\

0.4
-80 -40

a:

450
Vos = 24V
VGS = 0
f = 1 MHz

5.0

GS

.B

CAPACITANCE vs
DRAIN-SOURCE VOLTAGE

375

4.0

~ =10V
I

1

2
4
6
8
10
12
o
VGS - GATE-SOURCE VOLTAGE (VOLTS)

u

VGS = 5~

0.8

o

/
./'

u.

3.0

t ~

Oa:

«a: -

\

2.0

1.6

22

0

1.0

wN

II

1.5

C

_

o

. ~ ~ 1.2

II

.£
_0

0

20
Ow

2

1

y

3V

vGS -

iii

I

o

....

Iii

a:

~

~

«

CYCL

::l

1.5

2.0

2

/

80Jlsec

2

u

/

Vos - 10V
PULSE TEST

5V

4~

/J /

NORMALIZED DRAINSOURCE ON RESISTANCE
vs TEMPERATURE

TRANSFER CHARACTERISTIC

I

6~
-I·
I

VDS - DRAIN·SOURCE'VOLTAGE (VOLTS)

Vos - DRAIN·SOURCE VOLTAGE (VOLTS)

_ 9.0
~

I

./'

l- I/'
'tI

a

I

'/

/

2

4V

'1

~ 1-7V

/

6.0

::l

6~

~ 4.5

o

2
w
a:
a:

I

.... ~ VGS=

,;'

I-

I

a:

PULSE TEST BO!",c. 1% DUTY CYCL~

0-

7~

::l

g;

SATURATION CHARACTERISTICS

VGS - BV

PULSE TEST BO!,sec. 1% DUTY CYCLE

O~OIL

60

VDS - DRAIN·SOURCE VOLTAGE (VOLTS)

0.1
0.1

10

10(onl - ON DRAIN CURRENT (AMPS)

2-43

5200 Family Typical Performance Curves
(25°C. 'unless otherwise stated)
DRAIN-SOURCE ON
RESISTANCE vs
GATE-SOURCE VOLTAGE

TRANSCONDUCTANCEvs
DRAIN CURRENT

TRANSCONDUCTANCE vs
GATE-SOURCE VOLTAGE

,g

10

g
w
~ 2.0

w_
tJ'"
a:::;:
::J::t:

~2

1.6

8

1:2

a
.' z

I!!!

'"
«

lS~

a

a:
~

10 '" S.DA, PU LSE TEST
80 Jjsec - 1% DUTY CYCLE

0.01

1

. 10

100

V GS - GATE·SOURCE VOLTAGE (VOLTS)

a

~

8 1.2

Il

VDS =10V.

1

I
.:;;

o
o

..i.
1/

z

I

PULSE TEST

II
0.4

a:

!/

g 1.6

IL

~ 0.8

L"

~

./

Z

mJ~"'
.

g

~~

2.4

w
~ 2.0

l,..- ~

~

1\

O~Oll.

200IL'.c
1% DUTY'CYCLE

4

6

8

PULSE TEST

a

200IL'ec

~. 0.4

;s:
a:

'10

'rr1% DUTY CYCLE rI -.l-.l-.l
VDS = 10V

'1-

ll-

I I I I
2

J.
IL

~a: 0.8

r-

~

12

I
~

10 (0"1- ON .DRAIN CURRENT (AMPS)

1./

0

1/

0
2
4
6
8
10
12
V GS - GATE SOURCE VOLTAGE (VOLTS)

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

SWITCHING TIME TEST WAVEFORMS
-PULSE WIDTH1.2
90%
INPUT

OUTPUT

j-

90%

.

10%

r~"1--.

aw

N

10%

:::;

90%

10-""
~

~

a:
0

~

z

V-10%

10%~

1.1

«

.~.mp

td

L

~

'"c

>
III

0.9

~

O.B
·40 ·20 0

20 40 60 80100120140

TEMPERATURE - °C

SWITCHING TIME TEST CIRCUIT
+10V
+24V

COAXIAL CABLE
Zo = 12.511

211

10Kl1

;J;

.01ILFd

...--0-......,.

3msec

H

r-1 r.
OV.J
L..J

15V

OSCILLOSCOPE
TEKTRONIX 7904
OR EOUIVALENT
KI

220n

MERCURY REED
RELAY

2·44

"

';',:

:~

"

.

Analog'·SwilcI11J8
andMulliplei.Si,.:"
,

,

Multiplexers
Page

IH5108
IH5208
IH6108
IH6116
IH6208
IH6216

3-118
3-135
3-143
3-149
3.159
3-165

Analog Switch
Drivers
0112/113/120/121
0123/125
, 0129

3-9
3-25
3-35

Analog Switches
with Drivers
DG111/112
DG116/118/123/125 '
DG120/121
DG126A Family
DG139A Family
DG180 Family
DGM181 Family
IH181 Family
DG200
IH200
DG201

3-6
3-16
3-22
3-31
3-37
3-41
3-45
3-50
3-55
3-59
3-61

."',,

'. ,,; h ,:",. ,.

~ •. ~,.:;,., >

',....

.:'

" :. "

'.' :•• ".: .: :.M.··.

IH201/202
IH401
IH5001/2
IH5003/4
IH5005/6/7
IH5009-24
IH5025-38
IH5040-51
IH5052/3 '
IH5140-45
IH5200
IH5201

• ."

3-65
3-68
3-83
3-85
3-87
3-91
3-96
3-103
3-111
3:127
3-55
3-61

Analog Switches
without Drivers
G115/123
3-13
G116-19
3-19
G125-32,
3-29
G1330/40/50/60
MM450/550,
3-81
MM451/551,
M M452/552/M M455/555

Digital Translatorl
Ana'iog Driver
TTL or CMOS to
Higher Levels

IH6201

3-155

<

' : ::;:t.:~;'{~'~~":·>Y:':'

,....

'"

.~:.

".' &l
',Y"

). " . ' •

~;;;.;,.:.j.,;'~'J;/'" '<,:~
"'/",:,:,'.,~ ;, "
,

','

;

..

:-:',.:'

',:-'

'?'

,: ... ,

. :"",::':

..

".

.

A N A L '0 G

T'IP,LEXERS

S WIT C

Analog Switches with Driver
Type

No. of
Channell

SPST

SPST

SPST

SPST

4.

Inlerlll .
Device
No.
IH5001
IH5002
IH5021
IH5022
IH5023
IH5024
IH5037
IH5038
IH5040
IH5140
OGlll
OG112
OGI33A
OGI34A
OG141A
OG151A
OG152A
OG180
OG181
OG182
OGM182
OG433A
OG434A
OG441A
0G451A
OG452A
IH181
IH182
OG200
IH200
IH5003
IH5004
IH5005
IH5006
IH5007
IH5017
IH5018
IH5019
IH5020
IH5033
IH5034
IH5035
IH5036
IH5041
IH5048
IH5141
IH5013
IH5014
IH5015
IH5016
IH5029
.IH5030
IH5031
IH5032
OG116
OG118
OG201
IH201
IH202
IH5009
IH5010
IH5011
IH5011

Switch
Technology
N·JFET

N~JFET

P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
CMOS
CMOS
PMOS FET
PMOS FET
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
CMOS
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
Vara FET
Vara FET
CMOS
CMOS
N·JFET
N·JFET
N·JFET
N·JFET
N·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·JFET
CMOS
CMOS
CMOS
P·JFET
P·JFET
P·JFET
p·JFET
P·JFET
P·JFET
P·JFET
P·JFET
P·MOSFET
P·MOSFET
CMOS
CMOS
CMOS
P·JFET
P·JFET
P·JFET
P·JFET

rOS{onl

11

maxI!)
30
50
100
150
100
150
100
150
75
50
450
450
30
80
10
15
50
10
30
75
75
35
80
15
20
100
30
75
70
75
' 30
50
10
30
80
100
150
100
150
100
150
100
150
75
35
50
100
150
100
150
100
150
100
150
450
450
75
75
75
100
150
100
150

101011)

Ion
nA
1'1
max
max
5.0 0.5
5.0 0.5
0.2 0,5
0.2 0.5.
0.2 0.5
0.2 0.5
0.5 0.2
0.5 0,2
1.0 0.5
0.1
0.1
-1.0 0.3
-1.0 ·0.3
1.0 0.3
1.0 0.3
10.0 0.5
10.0 0.5
2.0 0.3
10.0 0.3
1.0 0.15
1.0 0.25
0.1
0.25
5.0 0.5
S.O 0.5
15.0 0.75
15.0 0.75
5.0 0.5
0.1
0.25
0.1
0.25
1.0 0.7
1.0 1.0
1.0 0.3
1.0 0.3
10.00 1.0
1.0 0.5
1.0 0.5
0.2 0.5
0.2 0.5
0.2 .0.5
0.2 0.5
0.5 0.2
0.5 0.2
0.5 0.2
0.5 0.2
1.0 0.5
1.0 0.25
0.1
0.1
0.2 0.5
0.2 0.5
0.2 0.5
0.2 0.5
0.5 0.2
0.5 0.2
0.5 0.2
0.5 0.2
-4.0 0.3
-4.0 0.3
1.0 0.5
1.0 0.5
1.0 0.5
0.2 0.5
0.2 0.5
0.2 0.5
0.2 0.5

loff

logic Inpul
Input
Typ(2)
hi
hi

1'8

max
1.0
1.0
0,5
0.5
0.5
0,5
0.2
0.2
0.25
0.075
1.0
1.0
0.8
0.8
1.25
1.25
0.1i
0.25
0.13
0.13
0.13
1.0
1.0
1.25
1.25
1.0
0.13
0.13
0.5
0.5
0.8
0.8
2.5
1.0
1.0
0.5
0.5
0.5
0.5
0.2
0.2
0.2
0.2
0.25
0.15
0.075
0.5
0.5
0.5
0.5
0.2
0.2
0.2
0.2
1.0
1.0
.0.25
0.25
0.25
0.5
0.5
0.5
0.5

3·2

Logic Lavel
OTl, TTL, RTl
OTL. TTL. RTl
TTL High level
TTL . low level
TTL High level
TTL low level
TTL Hilih level
TTL High level
OTl, TTL, RTl, CMOS, PMOS
TTL, CMOS
OTl, TTL, RTl
OTl,. TTL, RTl
OTl, TTL, RTl
OTl. TTL, RTl
OTl. TTL, RTl'
OTL. TTL, RTl
OTl, TTL, RTl
OTl, TTL, RTl \
OTl, TT~, RTl
OTl, TTL, RTl
OTl, TTL. RTl
OTl, TTL, RTl
OTl, TTL. RTl
OTl, TTL. RTl
OTl, TTL, RTl
OTl, TTL, RTl
OTl, TTL. RTl, CMOS, TTL High
OTl, TTL, RTl, CMOS, TTL High
OTl, TTL, RTl, CMOS, TTL High
OTl, TTL, RTl, CMOS, TTL High
OTl, TTL. RTl
OTl, TTL RTl
OTl, TTL, RTl
OTl, TTL, 1m
OTl, TTL, ATl
TTL: High level
TTL, low level
TTL, High' level
TTL. low level
TTL, High level
TTL, High level
TTL, High level
. TTL, High level
OTl, TTL, ATl, CMOS, PMOS
OTl, TTL, RTl, CMOS, PMOS
TTL, CMOS
TTL, High level
TTL, low level
TTL, High level
TTL. low level
TTL, High level
TTL. High Level
TTL, High level
TTL, High level
OTl, TTL, ATl
OTl, TTL, ATl
OTl. TTL, RTl, CMOS
OTl, TTL, ATl, CMOS
OTl, TTL. ATl, CMOS
TTL, High level
TTL, low level
TTL, High level
TTL, low level

Power
Consumption
mW
78
78

10
10
10
10
10
10

hi
hi
10

hi
hi
hi
hi
hi
hi
10
10
10
10

hi
hi
hi
hi
hi
level
level
level
level

10'
10
10
10

hi
hi
hi
hi
hi

.035
.035
163
152
68
68
68
72
72
120
120
120
:035
78
78
78
82
82
.350
.350
3.0
.350
78
78
78
78
78

10
10
10
10
10
10
10
10

hi
hi
hi

.035
.035
.035

10
10
10
10
10
10
10
10

hi
10
10
10

hi
10
10
10
10

133 '
133
.350
.350
.350

Analog Switches with Driver continued
rOS(on)

"

Type

SPST

SPST

SPOT

SPOT

OPST

OPST

OPST

OPOT

4PST

No. 01
Channels

Device
No.

Switch
Technology

II

max(l)

10(011)
nA
max

ton

toft

~s

~s

Logic Input
Logic Level

·Input
Typ(2)

Power
Consumption

mW

IH5025
IH5026
IH5027
IH5028
IH5052
IH5053

P·JFET
P·JFET
P·JFET
P·JFET
CMOS
CMOS

100
150
100
150
75
75

0.5
0.5
0.5
0.5
1.0
1.0

max
0.2
0.2
0.2
0.2
0.5
0.5

max
0.2
0.2
0.2
0.2
0.25
0.25

TTL
TTL
TTL
TTL
OTL.
OTL,

High
High
High
High
TTL,
TTL,

Level
Level
Level
Level
RTL, CMOS, PMOS
RTL, CMOS, PMOS

10
10
10
10
10
hi

OG123
OG125
OG143A
OG144A
OG146A

P·MOSFET
P·MOSFET
N·JFET
N·JFET
N-JFET

450
450
80
30
10

-4.0
-4.0
1.0
1.0
10.0

0.3
0.3
0.4
0.4
0.5

OG161A
OG162A
OG186
OG187

N·JFET
N·JFET
N·JFET
N·JFET

15
50
10
30

10.0
2.0
10.0
1.0

0.5
0.4
0.3
0.15

1.0
1.0
0.8
0.8
1.25
1.25
0.8
0.25
0.13

OTL,
OTL,
OTL,
OTL,
OTL.
OTL,
OTL,
OTL,
OTL,

TTL,
TTL,
TTL,
TTL,
TTL,
TTL,
TTL,
TTL,
TTL,

hi
10
(3)
(3)
(3)
(3)
(3)
(3)
(3)

90
90
73
73

OG188
OGM188
OG443A
OG444A
OG446A

N·JFET
CMOS
N-JFET
N-JFET
N·JFET

1.0
0.1
5.0
5.0
15.0

0.25
0.25
0.5
0.5
0.75

0.13
0.13
1.0
1.0
1.25

OTL,
OTL,
OTL,
OTL,
OTL,

TTL,
TTL,
TTL,
TTL,
TTL,

(3)
(3)
(3)
(3)
(3)

73
.035
78
78
78

OG461A
OG462A
IH187
IH188
IH5042
IH5050
IH5142

N·JFET
N·JFET
Vara FET
Vara FET
CMOS
CMOS
CMOS

75
75
80
35
.15
20
100
30
75
75
35
50

RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL
RTL

15.0
5.0
0.1
0.1
1.0
1.0
0.1

0.75
0.5
0.25
0.25
0.05
0.25
0.175

OTL,
OTL,
OTL,
OTL,
OTL,
OTL,
TTL,

TTL, RTL
TTL, RTL
TTL, RTL,
TTL, RTL,
TTL, RTL
TTL, RTL
CMOS

(3)
(3)
(3)
(3)
(3)
(3)
(3)

83
83
.350
.350
.035
.035
.035

OG189
OG190
OG191
OGM191
IH5043
IH5051
IH190
IH191
IH5143

N·JFET
N·JFET
N·JFET
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

10
30
75
75
75

10.0
1.0
1.0
0.1
1.0
1.0
0.1
0.1
0.1

0.3
0.15
0.25
0.25
0.5
0.25
0.25
0.25
0.175

1.25
1.0
0.13
0.13
0.025
0.15
0.125
0.25
0.13
0.13
0.13
0.25
0.15
0.13
0.13
0.125

OTL,
OTL,
OTL,
OTL,
OTL,
OTL,
TTL,
TTL,
TTL,

TTL, RTL
TTL, RTL
TTL, RTL
TTL, RTL
TTL, RTL, PMOS, CMOS
TTL, RTL, PMOS, CMOS
CMOS, PMOS, TTL High Level
CMOS, PMOS: TTL High Level
CMOS

(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)

120
120
120
.035
.035
.035
.350
.350
.035

IH5044
IH5144

1.0
0.1
1.0
1.0
10.0
10.0
2.0

hi
hi

.035
.035

0.3
0.3
0.5
0.5
0.3

0.25 OTL, TTL, RTL, CMOS, PMOS
0..125 TTL, CMOS
OTL, TTL, RTL
0.8
OTL, TTL, RTL
0.8
1.25 OTL, TTL, RTL
1.25 OTL, TTL, RTL
0.8
OTL, TTL, RTL

hi
hi
hi
hi
hi

OG183
OG184
OG185
OGM185
OG426A

N-JFET
N·JFET
N·JFET
CMOS
N·JFET

75
50
80
30
10
15
50
10
30
75
75
80

0.5
0.175

OG126A
OG129A
OG140A
OG153A
OG154A

CMOS
CMOS
N-JFET
N·JFET
N·JFET
N·JFET
N-JFET

10.0
1.0
1.0
0.1
50

0.3
0.15
0.25
0.25
0.5

0.25
0.13
0.13
0.13
1.0

OTL,
OTL,
OTL,
OTL,
OTL,

TTL,
TTL,
TTL,
TTL,
TTL,

OG429A
OG440A
OG453A
OG454A
IH184
IH185
IH5045
IH5049
IH5145

N·JFET
N-JFET
N·JFET
N·JFET
Vara FET
Vara FET
CMOS
CMOS
CMOS

35
15
20
100
30
75
75
35
50

5.0
15.0
15.0
5.0
0.1
0.1
1.0
1.0
0.1

0.5
0.75
0.75
0.5
0.25
0.25
0.5
0.25
0.175

1.0
1.25
1.25
1.0
0.13
0.13
0.25
0.15
0.125

OTL,
OTL,
OTL,
OTL,
OTL,
OTL,
OTL,
OTL,
TTL,

TTL, RTL
TTL, RTL
TTL, RTL
TTL, RTL
TTL, RTL,
TTL, RTL,
TTL, RTL,
TTL, RTL,
CMOS

hi
hi
hi
hi
hi
hi
hi
hi
hi
hi
hi
hi
hi
hi

68
68
68
72
72
84
84
84
.035
78

OG120
OG121

P·MOS FET
P·MOS FET
N-JFET
N·JFET
N·JFET
N·JFET
N-JFET

450
450

-3.0
-3.0

0.3
0.3

2.0
2.0

OTL, TTL, RTL
OTL, TTL, RTL

hi
10

164
164

30
80
10
15
50

1.0
1.0
10.0
10.0
2.0

0.8
0.8
1.25
1.25
0.8

OTL,
OTL,
OTL,
OTL,
OTL,

TTL,
TTL,
TTL,
TTL,
TTL,

(3)

35
80
15
20
100
75
75

5.0
5.0
15.0
15.0
5.0
1.0

1.0
1.0
1.25
1.25
1.0
0.25
0.25

O:rL,
OTL,
OTL,
OTL,
OTL,
OTL,

TTL, RTL
TTL, RTL
TTLQ, RTL
TTL, RTL
TTL, RTL
TTL, RTL CMOS, PMOS

(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)

84
84
84
90
90

N-JFET
N·JFET
N·JFET
N·JFET
N-JFET
CMOS
CMOS

0.4
0.4
0.5
0.5
0.4
0.5
0.5
0.75
0.75
0.5
0.5
0.5

OTL, TTL, RTL CMOS, PMOS

hi

OG139A
OG142A
OG145A
OG163A
OG164A
OG439A
OG442A
OG445A
OG463A
OG464A
IH5046
IH5047

35
30
75
50

1.0

3·3

CMOS,
CMOS,
PMOS,
PMOS,

PMOS, TTL High Level
PMOS, TTL High Level
CMOS
CMOS

RTL
RTL
RTL
RTL
RTL

CMOS,
CMOS,
PMOS,
PMOS,

PMOS
PMOS
CMOS
CMOS

RTL
RTL
RTL
RTL
RTL

(3)

.350
.350
133
133
84
84
84

78
78
83
83
.350
.350
.035
.035
.035

78
78
78
83
83
.035
.035

g

Multiplexers
Type

Faull
Protected

No. 01
Channels
1 of 8
1 of 16
2 of 8
2 of 16
1 of 8
2 of 8

Device
No.
IH6108
IH6116
IH6208
IH6216
IH5108
IH5208

10(offl
nA
max
0.1
0.2
0.1
0.2
0.1
0.1

rOS(on)

Swllch
Technology
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

II

max(l)
300
600
300
600
700
700

Ion
/,s
max
1.5
1.5
1.5
1.5
1.5
1.5

logic Inpul

toff

Inpul
Typ(2)
hi
hi
hi
hi
hi
hi

/,8

max
1.0
1.0
1.0
1.0
1.0
1.0

.0Tl, TTL,
OTl, TTL,
DTl, TTL,
OTL. TTL,
OTl, TTL,
OTl, .TTL,

logic Level
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

ATl,
ATl,
RTl,
RTl.
RTl.
RTl,

Power
Consumpllon
mW $I
4.5
4.5
4.5
4.5
4.5
4.5

Multi-Channel FET Switches
Eleclrical Characterislics @ +25'C-Military Temperalure Devices
ohms
max(4)
200
200
100
500
250

G'127
G-128
G-129
G-130
G-131

Switch
Technology
P-MOS
P-MOS
P-MOS
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET

90
45
500
250
90

90
45
500
250
90

ID(Offl
na
max
0.2
20.0
2.0
0.05
0.05
0.1
0.1
0.05
0.05
0.1

G-132
G-1330
G-1340
G-1350
G-1360

N-JFET
N-JFET
N-JFET
N-JFET
N-JFET

45
20
10
20
10

45
20
10
20
10

MM-451
MM-452
MM-551
MM-552
G-116

P-MOS
P-MOS
P-MOS
P-MOS
P-MOS

200
200
200
200
100

Oiff

G-117
G-115
G-118
G-123
MM-450

SPST

MM-550
G-119

P-MOS
P-MOS
P-MOS
P-MO'S
P-MOS
P-MOS
P-MOS

Type
SPST

11

No. 01
Channels

SPST

SPST
SPST

Device
No.
MM-455
MM-555
G-124
G-125
G-126

rOS(on)

ohms
max(l)
600
600
450
500
250

ton
ns

logic Input

toft

ns

max·

max·

50
50
100
30
30

50
50
100
50
50

30
30
30
30
30

0.1
0.5
0.5
0.5
0.5

600
600
600
600
450

.100
100
100
125
200

450
450
450
500
600

200
100

600
450

logic level
P-MOS
P-MOS
P-MOS
- 5V PMOS
-10V PMOS

Type
10
10
hi
hi
hi

50
50
50
50
50

- 5V
-10V
- 5V
-10V
- 5V

PMOS
PMOS
PMOS
PMOS
PMOS

hi
hi
. hi
hi
hi

30
30
30
30
30

50
50
50
50
50

hi
hi
hi
hi
hi

0.2
0.2
20.0
20.0
- 2.5

50
50
50
50
100

50
50
50
50
100

- 0.5
-10.0
- 3.0
-10.0
0.2
20.0
-1.5

100
100
100
100
50

100
100
100
100
50
50
100

-10V PMOS
- 5V PMOS
-10V PMOS
- 5V PMOS
-10V PMOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS
P-MOS

10
10
10
10
10
10
10
10
10
10

P-MOS
P-MOS

10
10

50
100

'These limes are dependent on the driver used.

Drivers for FET Switches
Electrical Characteristics @ +25'C-Military Temperature Devices
Vour
No. of Channels

4
6

Device
No.
0112
0113
0120
0121
IH6201
0129
0123
0125

Posilive

Valls
+9.9
+9.9
+9.9
+9.9
+14.0
Vsupply
Vsupply
Vsupply

Negallve
Volls
-19.2
-19.2
-19.2
-19.2
-14.0
-19.3
-19.7
-19.7

Ion
ns
max·
250
250
250
250
200
250
250
250

Notes:
1. Switch Resistance under worst case analog voltage .
. 2. Positive logic LO CO") or HI ("1") voltage at driver input necessary to turn
3. Logic "0" or "1" can be arbitrarily assigned for double-throw switches.
4. Switch resistance under best case analog voltage.

toff

ns
max
1500
1500
600
600
300
1000
600
600

switch on.

3-4

lo
/'A (max)
1.0
1.0
1.0
1.0
1.0
200
1.0
1.0

lin

HI
rnA (max)
1.5
1.0
1.5
1.0
1.0
0.25pA
1.0pA
1.5pA

logic Inpul
Level
TTL
TTL
TTL
TTL
TTL
TTLiOTl
TTLiOTl
TTL

Power
Consumption
(mW)
103
76
220
193
.350
55
20
50

VARAFET
Type

n
max

Vp
V
max

IH401
IH401A

30
50

7.5
5.0

rOS(on)

Lowest Quiescent .Current

I
IH5040 Family and
IH5140 Family
IH200 Family
Monolithic CMOS
.Monolithic CMOS driver driver gate
gate conbination
conbination.
Features
1. Very low quiescent
current resulting in
very low power
consumption.
2. Low cost.
3. Good speed with
moderate rOS(on)
and leakage,
4. Over voltage protection to ±25V.
5. Can switch up to
±13V signals with
±15V supplies.

Notes
1. TTL, DTL, CMOS and
PMOS compatible.
2. 5048 through 5053
and the IH200
family are 2-chip
hybrid devices with
35n rOSl on) max
@25"C.
3.5040 through 5047
have 75n rOSl on) max
@25"C.
5040
5041,5048
5042,5050
5043,5051
5044
5045,5049
5046
5047
5052,5053
200
201,202

SPST
Dual SPST
SPOT
Dual SPOT
DPST
Qual DPST
DPDT
4PST
Quad SPST
Dual SPST
Quad SPST

15 (oft)

loss
rnA
min

ton
ns
max

Vailalog

ns
max

Package
4 FETS/Pkg

Vp _ p
min

Vmject

pA
max
200
200

45min
35min

50
50

150
150

16 Pin Dip
16 Pin Dip

15
20

10
10

Highest Speed

Lowest rOS lon )

I

I

IHI81 Family
CMOS driver and
Varafet gate.

tOft

06180 Family
Bipolar/MOS drive
with N-JFET gate.

Features
1. High speed switch.
2. Low quiescent
current resulting
in low power
consumption.
3. Low leakage
resulting in low
error term.
4. Lower cost than the
comparable speed
DG180 Family.
5. Can switch signals
almost to the
supply rails.

Features
Features
1. Low charge
1. Low r OSlon)
injection.
2. As fast as the
IH5140 Family.
2. Almost as fast as
3.
Moderate leakage.
5140 and DG180
Families.
3. Very low quiescent
current resulting
in low power
consumption.
4. Ultra low leakage.

Notes
1. TTL and CMOS
compatible.
2. Pin compatible
with the more
popular members
of the DG180 .
family.

Notes
1. TTL, HTL, CMOS
and PMOS
compatible.
2. Pin for pin compatible with
DG180 Family.

5140
5141
5142
5143
5144
5145

SPST
Dual SPST
SPOT
Dual SPOT
DPST
Dual DPST

IH181,182 Dual SPST
IH184,185 Dual DPST
IH187, 188 SPOT
JH190, 191 Dual SPOT

0G12B,OGI2BA
Family and IH5001
Family
Bipolar driver with
N-JFET gate.

For switches whose
outputs go into the
input of an OP Amp.
5009 Family
VIRTUAL GROUND
SWITCH

For switching
positive signals only:
5025 Family
POSITIVE SIGNAL
SWITCH

Features
Output of switch must Can' switch positve
1. Low rOSl on )
go into the virtual
signals only unless
2. Only switch with
ground paint of an
a translator driver
true chip enable
Op Amp (unless
is used.
pin.
signal is <0.7V).
3. Low cost.
Features
Features
4. Moderate leakage 1. Very low quiescent 1. Very low quiescent
& quiescent curcurrent.
current.
rent speCifications. 2. Does not need
2..Does not need
driver: can be
driver: can be
driven directly by
driven directly by
TTL.
TTL.
3. Low cost.
3. Low cost.

Notos
Notes
Notes
1. DTL, TTL, RTL
1. "A" selection
1. All switches in
devices have
compatible
5009 family are
2. DG180, 183, 185
higher speeds.
SPST.
and 189 have 10n 2. DG426/ A family is 2. Odd numbered
a slightly downmax on resistance
devices are driven
graded version of
by TTL open
but have higher
collector logic.
leakage than others the DG126/A
in the family.
series. See spec
3. Even numbered
3. DG181, 184, 187
tables for comdevices are driven
parison.
by TTL low level
and 190 have 30n
logic.
max rDS(on).
DG133, 134, Dual
4. Commonly used for
4. DG182, 185, 188
and 191 have
141,151, SPST
signals going into
152
the inverting input
75n max rOSl on)
DG180, Dual SPST
DG126, 129, Dual
of Op-Amps.
181,182
140,153, DPST
5009,5010 quad.
DG183 Dual DPST
154
DG143,144,Dilt.
compensated
184,185
DG186, SPOT
146,161, Input
5011,5012 quad,
uncompensated
187,188
162 SPOT
DG139,142, Dilt,
5013,5014 triple,
DG189, Dual SPOT
190;191
145, 163, Input
compensated
5015,5016 triple,
164 DPDT
IH5001, SPST
uncompensated
5002
5017,5018 dual,
IH5003, Dual
compensated
5004,5005, SPST
5019,5020 dual,
5006,5007 '
uncompensated
5021,5022 single,
compensated
5023,5024 single,
uncompensated

3-5

Vp _ p
max

Notes
1. All switches in
5025 family are
SPST.
2. All devices can be
driven by TTL open
collector logic. All
devices can be
driven by low level
TTL logic if input
signal is less
than IV.
3. Commonly used for
signals going into
the non-inverting
input of Op-Amps.
Odd numbered
. devices have lOOn
max fOS(on). @
25"C.
5. Even numbered
devices have 150
max fOS{on). @
25°C
5025,5026 quad,
common drain
5027,5028 quad
5029,5030 triple,
common drain
5031,5032 triple
5033,5034, dual,
common drain
5035,5036 dual
5037,5038 single

O~OlL

DG111/112
2~Channel ~Drivers with
MOS·FET Switches
(Military Series - 55 0 C to +-125 0 C)

,FEATURES

GENERAL DESCRIPTION

• Each Channel Completely Isolated

This driver·switch series provides two completely isolated
switches per package. The collector~supply (Vee) may be
operated at different voltages for each switch. Two driver
input configurations are available for inverting and non·
inverting applications. For ,minimum propagation delay as
well as optimum speed and power, a terminal is supplied for
biasing the constant-current MOS-FET pull-up.

• 20V p.p Swi,tching Capability'
• Zener Diode Protected Gates
• MOS·FET Current·Source Pull·Up

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
DGlll

DGl12

<>-t-----<>"";

,
0----+-<>'",

O-t---:---~...,.-;

o----j-O'<.

..
,

<>-t-----...J
0..
0..

DGlll
DGl12

CONDITIONS

IINIOFF)

0..

z

MAX LIMIT

PARAMETER
(NOTE)

IOION)

Is = ":'100 /1A

Vo=-10V

1000

nA

Vo = 10V, Is = 0

-1000

nA

Vs = 10V, Vo= 10V

I SIOFF )

-1

-1000

nA

Vo = 10V, Vs = -10V

mA

One Channel ON

/1A

All Channels OFF

-6

ICCIOFF)

10

s:a

ILIOFF)

10

IRIOFF)

-15

IEEIOFF)

-20

tON

300

t!}

C/l

Vo = 0

1

DG112

DGl12

liN = lm A
Vo = 10V

-1

3

~I-

125

IOIOFF)

ICCION)

1--

V

250

DG111

DGll1

VIN = O.4V

O.B

600

3

~C/l
u:;:;

VIN = 0.5V

/1A

450

-0.5

:r:UJ

mA

200

ILION)

DGl12

-0.7
100

200

IRION)

DG111

V IN =4.1V

450

IEEION)

0..

/1A

n
n
n

DG111

UJ

20

100

a:

:J

UNITS

100

DGl12

C/l

125°C

,

.
ns
See Switching Times

tOFF

1

/1s

NOTE: (OFF) and ION) subscripts refer to the conduction state of the MOS·FET switch.

3·7

O~OI!,

DG111/112
TYPICAL CHARACTERISTICS
SWITCHING TIMES vs

TEMPERATURE
lK

1100

15- -lmA

~R
~
, Q 100 r-e-

Vr:;

V+ = 10V
= -20V
VP, = -20V

125'25°- V

Bf-

550

liN vs VIN
(OG1121

(OGlll,OGI121

ros vs Vo OR Vs

-

ro--t-t- ;...

]

900

"'~

700

j::

'"~

1.8

VEN -0
V- = -20V
V+ = 10V
GoUT = 30pF
P = -20V
tOFF

500

;;
S
~

V'

300

100

10
-10

'10

--50

III'!,

u

>-

irz

,.

tON~

25

)

V
\ 0.2

125

rr

I

z

1/

0.4

0.6

O.B

'V IN -INPUT VOLTAGE IV}

TEMPERATURE (DC)

Vo OR Vs IVI

1/1'1

0,6

0,2

o

,~

I

-55"C

:i'::>

~

~

1~;:gN

>-

/
./

T

VEN =0
V- = -20V

1.4

APPLICATION TIPS
The recommended resistor values for interfacing with RTL, DTL, and T2 L Logic is shown in figs. 1 and 2 .
• sv

-10%

RTL
DTL937,94B.

949,961,963

RTL
OTL931,9Jl,937
948,949.961,963

DTL9JO,936,945,

946,962.931
DTl 930, 936.
945,946,962

+5V!10%

TTL 54f74
TTL 9000 SEAlES

SUHl

TTl 54114
TTL 9000 SERIES
SUHL

Figure 2. DG112 Interface

Figure 1. DG111 ,Interface

Enable Control
The VEN and VINH terminals can be used as a strobe or an enable control. The requirements for sinking 'current at V EN or
sourcing current at VINH are: ILION) x no. of channels used, for DG111, and IR(QN) x no. of channels used, for the DG 112.
The voltage at V 1NH must be greater than VIN for VIN < 4V. VINH must be at least +4V for V 1N > 4V.

SWITCHING TIMES
DGlll,

+45V

V"
t,'.DIlls

oJ!....

I,' 01"s

~-,,--oOUTPUT
30"

"

DG112
OUTPUT

DGl12

'24V

OG11!
OUTPUT

O~o-~'~6~K__~4-~~

s,

+--......

-oOUTPUT

2K

3-8

JOpF

O~O[b

D112/113/120/121
2·Channel FET Switch Drivers
(Military Series - 55 ° C to' +
.
125°C)

FEATURES

GENERAL DESCRIPTION

• Two separate channels

This series contains 2 separate channels each with J. F ET
collector 'pull-up, in one package. Two switching speeds are
provided for speed-power ratio selection.

• J·FET Collector Pu)l·up
• Interfaces 5V Logic
• Two switching speeds to choose frol"D

at

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
.--------------'-------r---~-----,

v- ,

v'

ORDERING INFORMATION

Dl13'

L:
A

v'

12

K

IN
OUT

Package
, K - 14-Pin CERDIP
L - 14·Pin Flat Pack
'%" x %"
.
P - 14-Pin Ceramic DIP (Special Order Only)
Temperature Range
A - -SSoC to +,12SoC
B - _20°C to +8SoC
C - O°C to +70°C

' - - - - - - - - - ' - - Device Chip Type

3·9

10

IN
OUT

VR

V-

R.I

O~OIL

D112/113/120/121
Pos. Supply to Emitter (V+ - V-I . . . . . . . . . . . . . .. 33V
Output to Emitter (VOUT .,. V"'") . . . . . . . . . . . . . . . 33V
Logic Supply to Emitter (VL - V-I .... . . . . . . . .. 30V
Ref. to Emitter (VR - V-I . . . . . . . . . . . . . . . . . . . 31V
Input to Ref. (VIN - VR) . . . . . . . . . . . . . . . . . . . . .2V
Ref. to Input (VR - VIN) . . . . . . . . . . . . . . . . . . . .. 6V
Logic Supply to Input (VL - VIN) . . . . . . . . . : . . .. ±6V
Current (any pin) . . . . . . . . . . . . . . . . . . . . . . . . 30m A

Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Operating Temperature ...... . . . . .. _55°C to +125°C
Dissipation (Note) . . . . . . . . . . . . . . . . . . . . . . 750mW
LeadTemperature (soldering, 10 sec.) . . . . . . . . . . 300°C
NOTE: Dissipation rating assumes device is mounted with all leads

welded or soldered to printed cirCUIt board in ambient
temperature below +70 C. For higher temperatures, derate
10 mwr C.

Stresses above thpse listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS (per channel)
Test conditions unless otherwise specified are as follows: V- = -20V, V+
and power supply measurements based. on specified input conditions.
PARAMETER
(NOTE)
NO
~ N

I-

::>

00

Co

~

M~

N

~

00
NM
~

~

00
I-

::>

o~

I-

00

Co

::>
0

NN

...J
...J

0

VINION)
IINIOFF)

1.0

1.0

leSSIOFF)

-2.2

-1.8

-1.8

leSSIOFF)

-0.6

-0.4

-0.4

MIN

leSSIOFF)

-7.5

-S.7

-S.1

MAX

leSSIOFF)

-3.2

-3.0

-2.0

MIN

Co

mA

V OUT = -20V
VEE = -20V

MIN

V

lOUT = -10pA

MIN

V

lOUT = I mA

MAX

mA

2.0

ICCION)

1.8

IEEION)

3.8

~

0

MAX

9.8

0.5

0

liN = 1 mA
VIN = O.4V

-19.0

IRION)

:s:

V
·pA

9;9

Co
Co

UJ

100

-19.2

7.7

M

0.8

9.9

IEEION)

::>

1.2

-19.2

>
...J
Vl

V IN =4.1V

1.0

2.0

a:

VIN =O.4V

pA

1.3

5.7

0

mA
MAX

1.5

20

CONDITION

UNITS

1.0

·ICCION)

~

= 0, VL = 4.5V, VR = O. Output

MAXIMIN

1.5

ILION)

0
N

12S·C

1.0

ILION)

N

2S·C

IINIOFF)

VOUTION)

lOUT

LIMIT
-SS·C

IINION)

VOUTIOFF)

«

= +10V,

ICCION)

1.8

IEEION)

2.8

IRIONI

0.5

One channel
ON

~

N

0
...J
...J

«
l?
Z

-Vl

J:UJ

u;;;:

-

NM
~

00

1--

0NN

Vl

00

~I-

ICCION)

5.7

IEEION)

6.7

I LiOFF )

250

I RIOFF )

150

ICCIOF F)

50

IEEIOFF)

250

;

MAX

All channels
OFF

tOFF

1.5

tON

0.25

tOFF

0.60

tON

0.25

NOTE:

pA

(OFF) and fON) subscripts refer, to

MAX

(See Switching

ps

Times)
"

~he

3-10

conduction state of the driver.

D112/113/120/121
TYPICAL PERFORMANCE CURVES

OUTPUT RISE TIME VS
TEMPERATURE ANO LOAO
CAPACITANCE (0112,0113)
10

j
w
:;;
.1

..

0.5

i<

....
"....

"
0

:'V+= +101/
V =-20V _
;eCl = l00pF
VL = 4.5V ---,
~VR =0
,t.Cl =50pF

.~

C~ = 2d pF:

~

0.5

Cl = 10 pF

I!:~

0.21-

-

'.

~

w
en

OUTPUT RISE'TIME V5
TEMPERATURE ANO LO.
CAPACITANCE (0,120, 012,

_

I

0.2

5

-50 -25

0

25

50

= -:iov +--+--+-1-;

VL =-4.5V
VR = 0

~=t::t:~~~~:j

"
Oo.,~~§~~

I

75

V-

~
~ ~~~~~~~~~~

I I

0,1

V+ = +10V

~

0.05 E
-50 -25

100 125

SWITCHING. TIMES
VS TEMPERATURE
. 1100

i

900

:e~

700

~

r--r--,---,......~-V-:-+-=-,-0V--,

f-+-+---1f--+-

V- = -20V

f-+-+--f--+I-+-+--,-j-+-

VL = 4,5V
,VR = 0
,
CL = 10pF :

100 125

j'ci

I

I - ~rO'IDI2;- f'-ooo..

I:::::: ~D,112, 0113,.
"

~
o

0.1
75

25

-;;0

125

-25

TEMPERATURE ('CI

0

25

50

RSAT VS
, TEMPERATURE

u

~
I-'
..:

/.

103

/

1.3

..

L

1,2

.L~

c

w

N

:::;

./

10>

..:

:;;

~

1.0

a:

.2

0

z

./

10

100 125

1.4

VOUT'= V+ = +10V'

~

75

T6MPERATURE ('C)

'0UT(OFF) VS
TEMPERATURE
10<

"

75

V+=+-'0V'
1= ~
'. .'1,- = VOUT = -20V

~

Q

~O

I-

:;:

1

25

10SS(OFF) VS
TEMPERATURE
10

1-+-+--,-j-+-+-+--1~

z

0

T~MPERATURE

TEMPERATURE ('C)

.9

,...

,/

./

~

~

a:

.7
-50 -25

I

25

45

65

85

lOS

.8

125

0

25

50

75 100 125

TEMPERATURE I'C)

TEMPERATURE ('C)

3-11

O~OR.

D112/113/120/121
APPLICATION TIPS
The recommended resistors for interfacing with RTL, DTL, and T2 L Logic is shown in figures 1 and 2 ..

RTL

RTL

DTL931,9l2.937
948,949.961,963

Oll 931. 948,
949,961,963

t5V!10%

DTl930, 936,

DTL 930, 936. 945.

945. 946, 9G2

946.962,931

'

+SVtl0""

TTL 54174
TTl. 9000 SERIES

TTL 54174
TTL 9000SERtES

SOHL

SUML

Figure 1. 0112and0120
Interface

Figure 2. 0113and0121
Interface

Enable Control

as

The V R and V L pins can be used
a STROBE or an ENABLE control. The requirements for the enable driver are as
follows: I L (ON) X no. of channels used for the D1 12 & D1 20 and IR (ON) X no. of channels used for the D113 & D1 21:
The voltage at V L must be greater than the voltage at V IN by at least +4 V.

SWITCHING TIMES

0112,0120 .
V"
I,

~

<50",
< 50",

45V~

ov

ovI

0113

tv. r

0113,0121

0121

0112
0120

Circu it Diagrams

3-12

op

,

G115/G123
4 and 6·Channel MOS FET
Switches Industrial Series
- 20°C to + 85°C
FEATURES

GENERAL DESCRIPTION

• Integrated MOS-FET Constant-Current Sources for Active Driver-Collector Pull-up

These switches may be connected directly to the INTERSIL
switch -driver D123 series without the need of any interfacing
components, and are internally protected by a Zener diode
integrated on the silicon chip. A MOS-FET used as a current
source provides an active pull-up for faster switching capability. The active pull-up FET can be disabled without sacrificing the Zener protection of the gates.

• Integrated Zener Diode Protection for Both Positive and
Negative Spike Protection
• P-Channel Enhancement-Type Switches

SCHEMATICS AND PIN CONFIGURATIONS (Outline Dwgs DD, FD-2, JD, PD)
Gl15

G123

16

14

'-----t-,---+----f--r-<>0.

~--+----+----+----+----~-.~o

9

'--+---,...--00,

5,<>------------------------------'

5,

-+-----1--<,.-,

5, '0-'

13

0-______________+-+-<>16 0

'2

5,o-f---+--<>"l
12

5. c>-if----+---+-~--,

14

5, ~~~.... 0------------1>--\-00.
0 - - - -.....

II

0----------+

5, <>-~---+--+----t-+--OO

5.'0.°-+----i--t--+--o1

5,o-~---'---+--+---t----+-<>"1

ORDERING INFORMATION
Gl15

L=
A

K

Package
J - 14-Pin Plastic DIP
K - 14-Pin CERDIP
L - 14-Pin Flat Package
P - 14-Pin Ceramic DIP (Special Order Only)

,

Temperature Range
A - Military (-55'C to +125'C)
B - Industrial (-20'C to +85'C)
C - Commercial (O'C to +70'CI

L-_____________

Device Chip Type

NOTE: Plastic package available in commercial and industrial temperature ranges only.

3-13

O~OIb

0115/123
ABSOLUTE MAXIMUM RATINGS (25°C)
Source Current (Is) • . . . . . . . . . . . . . . . . . . . .. 100mA
Drain Current (I D) . . . . . . . . . . . . . . . . . .'. . .. 100mA
Gate Current (lG) . . . . . . . . . . . . . . . . . . . . . . . . • 5mA
Pull-up Control Current (lp) . . . . . • . . . . . . . . . . . 100JlA
Body to Source (VB - Vs) ...... : ...... -2V to +25V

Body to Drain (VB - VD ) . . . . . . . . . . . . .. -2V to +25V
Body to Gate (VB - VG) . . . . . . . . . . . . . . . . . . . +35V
Body to Pull-up (VB - Vp) . . . . . . . . . . . . . . . . .. +35V
Power Dissipation (derate 1OmW/"C above 70°C .. 750mW
Lead Temper~ture (soldering, 10 sec.) ......... : 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS (per channel unless noted)
LIMITS
PARAMETER

25°C

-20°C

Gl15

CONDITIONS

Max

n

V BO ~ 0, V GO = -30V
lis =
V BO = +10V, V GO =.,.20V 11 mA
Vso - +20V, V GO - ,.10V

10(OFFI

-10

-500

Max

nA

VOs = -20V, Vss = V GS = V ps = 0

IS(OFFI

-5

-100

Max

nA

Vso = -20V, Vso = V GO = Vpo =0

IGSS

-5

-100

Max

nA

V GS = -20V, Vos = V SB = V ps = 0

IGIONI

-0.8
-2.4

Min
Max

rnA

V Ge = -30V, V ps = -30V, Vos

V GSlthl

-2
-6

-2
-6

-2
-6

Min
Max

V

Is = -10pA,V OG = 0,
Ves = Vps = 0

=0

BVoss

-25

-25

-25

Min

V

10 = -10 pA, V GS = VBS = V ps = 0

BVsos

-25

-25

-25

Min

V

Is = -10pA, V GO = V BO = Vpo = 0

BV GSS

-35
-90

-35
-90

-35
-90

Min
Max

V
V

IG = -10pA, V OB =V SB

BV PBs

-35
-90

-35
-90

-35
-90

Min
Max

V
V

Ip = -1OpA, V OB = V SB = V GB = 0

Typ
Typ

pF
pF

18 (TYP)

Typ

pF

9 (TYP)

Typ

pF

f

3.5(TYP)

Typ

pF

V SB = -5V, V OB =0, V GB = Vps = 0
f = 1 MHz

3(TYP)
O.4(TYP)

CDB

G123

-

CSB

Both

UNITS

150
300
600

CGS , CGO
Cos
--:-

MINI
MAX

125
250
500

125
250
500

rOSIONI

G115
and
G123

85°C

-

= V PB

=0

V Ge =O,V SB =O,V OB =O,Vps=O
f = 1 mHz, Body Guarded

V OB = -5V, Vse
= 1 MHz

=

V GS = Vps = 0

TYPICAL CHARACTERISTICS
u.
a. laO
Vas

"'uz

't;;"

iii

15

10 3

"'

--

"'
U
II:

101

Z

;;:
o

II:
I

.f1

....'"

U

v Ga

0

~

'"

illa::

Is - laO pA
TA ::: 25 C

.

-15

-10

-5

Vos-GATE·SOURCE VOLTAGE (VI

f-10 2

~~~

"I

"'
U
II:

al

;;:

I - - 1-+85"C
I - - I- +25"C..:::p.,,,, 111

Z

0.
Z

103

1;;

>o

p-

I
"'
U

50

u

20
G115

II:

0.
I

rJ
-20

""

z

10

-30 -25

V SB

"'
u

10

II:

5v>

=ov

-

::>

~

~
z

;;:

9

10

-30

-25

-20 -15

-10

-5

Voo - DRAIN·BODY VOLTAGE IVI

3-14·

10::- loop.A-

Vas ::- 0

II:

~

>

10

-30 -25

-20

-15

-10

-5

VosGATESOURCE VOLTAGE IVI

U~UlL

DG116/118/123/125
4 and 5·Channel Driver·MOS·PET
Switch Combinations
(Military Series -55°C to +125°C)

FEATURES

GENERAL DESCRIPTION

• Available With and Without Programmable Constant
Current pull-up
• Zener Protection on All Gates
• P-Channel Enhancement-Type MOS-FET
Switches
• Each Switch Summed to One Common Point

This series includes devices with four and five channel
switching capability_ Each channel is composed of a driver
and a MOS-FET switch_ Two driver versions are supplied
for inverting and noninverting applications_ A MOS-FET,
used as a current source provides an active pull-up for faster
switching_
An external biasing connection is brought out for biasing
the current source for optimization of speed and power.

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
DG116
(One Channel)

DG118
(One Channel)

DG123
(One Channel)

DG125
(One Channel)

I.

,

, ..
, ..

I

I

I

I

I

I

I

I

I

I

I
I

I
I
I
I
I
I
I
I

I

I
I
I
I

_J

:

___ J

I

:I

I

I

!

I
I
I

I

I

I

_____ JI

I
I
I I
I I
_J
I
I
___ JI

I

I

:

L=
A

DGl16,DG123

Y,N

VL

Condo

L
H

L
L
H
H

L
L
H
H

L
H

OFF
ON
OFF
OFF

L=OV.H=+V

3-15

Switch

VR

L

' - - - - - -_ _ _ Device Chip Type

DGl18,DG125

Y,N

H

I

I
I

I
I
I
I
I

I
I
I
I
I

I

_______ JI

TRUTH TABLE

Temperature Range
A - Military (-SSOC to+12S0C)
B - Industrial (_20° C to +8SoC)

I

_____ J

I

K

Package
K - 14-pin CERDIP
L - 14-pin Flat Package
P - 14-Pin Ceramic DIP (Special Order Only)

I

:I I
I

I
-..:. ______ 1

ORDERING INFORMATION

I
I

I

I
I

DGl16

I
I

I
I
I

L
H

DO 116/118/123/125

O~O!l

ABSOLUTE MAXIMUM RATINGS
Collector to Emitter (V+ - V-) . . . . . . . . . . .. . . .. 33V
Collector to Pull·up (V+ - Vp) . . . . . . . . . . . . . . . . 33V
Drain to Emitter (VD - V-) . . . . . . . .. . . . . . . . .. 32V
Source to Emitter (Vs - V-) . . . .. . . . . . . . . . . . .. 32V
Drain to Source (VD - Vs) . . . . . . . . . . . . . . . . . . . 28VSource to Drain (Vs - VD) . . . . . . . . . . . . . . . . . .. 28V
Logic to Emitter (VL - V-) . . . . . . . . . . . . . . . . . . 33V
Reference to Emitter (VR - V-) . . . . . . . . . . . . . . . 31V
Reference to Input (VR - VIN) . . . . . . . . . . . . . . . . . 6V
Logic to Input (VL - VIN) . . . . . . . . . . . . . . . . . '.. ±6V

Input to Emitter (VIN - V-) . . . . . . . . . . .. . . . . .. 33V
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . 30m A
Storage Temperature. . . . . . . . . . . . .. _65°C to +150°C
Operating Temp'erature ... . . . . . . . .. -55°C to +125°C
Dissipati.on (Note) . . . . . . . . . . . . . . . . . . . . . . 750mW
Lead Temperature (soldering, 10 sec.) . . . . . . . . . . 300°C
NOTE: Dissipation rating, assumes device is mounted with all. leads
welded or soldered to printed circuit board in ambient

temperature of 70°C. Derate 10mWfC for higher ambient
temperature.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections ofthe specifications is not implied. Exposure to absolute maximum rating, conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS
Test conditions unless specified otherwise are as follows: VL = 4.5V, VR
test conditions used for output and power supply specifications.

PARAMETER
(NOTE)

I-

:::l

DGl16
DG123

a.
Z

-

DGl18
DG125

-55°C
1

1

V'NION)

1.3

1.0

I'NIOFF)

1

1

I'NION)

-0.7

-0.7

a..

I-

0

All
circuits

>-l
a..
a..

:::l
(f)

cr:

UJ

$
0
a..

All
circuits

= -20V, and P = -20V.

UNITS

100

IJ.A

V ,N

V

liN

0.8
20

IJ.A

-0.7

mA

200

200

250

450

450

600

4

4000

nA

IOIOFF)

-4

-4000

nA

ISIOFF)

-1

-1000

ICCION)

3

mA

ILION)

3

mA

IRION)

-0.5

mA

IEEION)

-6

mA

ICCIOFF)

10

IJ.A

. ILIOFF)'

10

IJ.A

IR(OFF)

-15

IJ.A

IEE(OFF)

-20

IJ..A

IOION)

100

Input ON and OfF'

CONDITIONS

+125°C

n
n
n

rOSION)

:::l

+25°C

I'NIOFF)

I-

All
circuits

V-

MAX LIMITS

100

:::l

= 0,

125

nA

,

= O.4V
= 1 mA
V ,N = 4.1V
V ,N = 0.5V

= 10V, Is =-lmA
Va = O. Is = -1001J.A
Vo = -lOV,l s = -lOOIJ. A
Vo = 10V, I Slall ) = 0
VSlall) = 10V, Vo = -lOV
Vo = 10V, Vs = -lOV
VD

,

One Channel (ON)

All Channels (OF F)

(.:J

-zJ:UJ

(f)

U:2

1--

~I-

(f)

All
.circuits

tION)

0.3

IJ.s

tIOFF)

1

IJ.s

See Switching Times

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the MOS·FET switch for the given test condition.

3·16

DO 116/118/123/125
TYPICAL CHARACTERISTICS
SWITCHING TIME,S vs
TEMPERATURE

liN vs VIN
(DGl16.DG123)
1.8

~
~

VR = 0
V- = -20V

1100

I I

1.4

I-

l~;:gH

w

_55°C

z

a:
a:

::;)

I-

::;)

0..

z

.~

I

I

u

0.6

]: 900
V>

'h",
II

I

-;

/

z

0.2

V
o

0.2

0.4

0.6

/

~ 700

v+

= 10V

/
tOFF

OUTPUT
30pF

DG118,125

s,
OUTPUT

3·17

+10

O~OlL

G116 - G119
5 and 6·ChanneIMOS-FET Switches
Military Series -55°C to +125°C
GENERAL DESCRIPTION

FEATURES

These switches may be connected directly to the INTERSIL
switch-driver D123 series without need of any interfacing
components. These MOS-FET switches are internally protected by a Zener diode integrated on the silicon chip. A
MOS-FET used as a current source provides an active pullup for faster switching. The active pull-up FET can be disabled without sacrificing the Zener protection of the gates.

• P-Channel Enhancement-typeMOS-FET Switches
• Zener Protection on All Gates
• With and Without Constant Current Source Pull-up

BJ------LOGIC DIAGRAMS (Outline DwgsPD, JD, FD-2, DD)

Gl17

Gl16

"

"~"----------~ ~----+------r----~~

,,0.-----------------'

'----r---+~

,O'-----------------------~I'----~~

,~.------------------------------~
Gl19

Gl18

,~'----+----+-~ L-1------~

.'~'----~--~-+-----+~
"~·----~ll'----~----_+------~--

,'~'.-----------"

ORDERING INFORMATION
G116

J

M

~

Lp"~~14.Pi"PI.";ODIP
,

' .
,

..

K - 14·Pin CERDIP

L-14-Pin Flat Package

Te;~r:~:::

:::eetic

DIP (Special Order Only)

A - Military (_55°C to +12SC C)
B - Industrial I_20°C to +85°C)

Device Chip Tvpe

3-18

G116-G119

O~OIl,

ABSOLUTE MAXIMUM RATINGS (25°C)
Source Current (Is)
Drain Current (lD)
Control Gate Current IG
PUll-Up Gate Current Ip
Body Voltage (Va) to Any Terminal
Power Dissipation (Note)
Storage Temperature

100 mA
100mA
SmA
100 !lA
-2 to +30V
7S0mW
-SSoC to +lS0°C

Operating Temperature
Lead Temperature (soldering, 10 sec.)

-SO°C to +12SoC
300°C

NOTE: Dissipation rating assumes device is mounted with all leads
,

welded or soldered to printed circuit board in ambient tem-

perature- below +70°C. For higher temperatures, derate
10 mwtC.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL CHARACTERISTICS (per channel unless noted)
References to pull-up gate P do not apply to Gl18.

LIMITS
PARAMETER

rDSIONI
(Note 1)

G116M Series
2SOC
12SOC
12S
250
600

100
200
4S0

Gl16C Series
2SOC
12SOC

MINI
MAX

UNITS

12S
250
600

Max

n

Max

nA

V SD = -20V. V BD = V GD = V PD = 0

Max

nA

Vas = -20V
VBD-VGD-VPD-O

nA

ISIOFFI

-O.S

-SOO

-1

-2S00
-3000
-1500

-S

IDIOFFI

-2.S
-3.0
-1.5
-0.5

-500

-1

Max

-6~

CONDITIONS

V BD
V BD
V BD

= 0,

V GD = -30V, V PB = 0
+10V, V GO -20V,V PB
+20V, V GD -10V, V PB

Is =
0
0

Gl16
Gl18
Gl19

-3
V G1B to V GSB = O. V G6B = -30V
V DB = -20V, V SB = V PB = 0

= Vps

BV DSS

-30

-30

Min

ID = -10 !lA. V GS = V BS

BV sDs

-30

-30

Min

Is = -10IlA. V GD = V BD = V PD =0

BV GBS

-30
-90

-30
-90

Min
Max

BV PBS

-30
-90

-30
-90

Min
Max

Ip = -10 !lA. V GB = V SB = V DS = 0

-2

-6

-2
-6

Min
Max

Is = -10 !lA. VDS = -10V. V SB = 0

IGIONI
(Note 2)

-0.5
-2

-0.3
-2.5

Min
Max

mA

V GB

IGSS

-0.5

VGDlthl

V

=0

= :'30V. V PB

= -30V. V SB = V DB = 0

= -20V. VDS = V BS = V ps = 0
= O. V BS = O. or V BD = 0
Body Guarded. f = 1 mHz
V PB = V GB = V DB = O. V SB = -SV. f = 1 ';;Hz

-1

Max

nA

V GB

3

3

Max

pF

V PB

CSD

0.4

0.4

Max

pF

CSB

3.5

3.S

Max

pF

C DB

Gl17

IG = -10 !lA. V PB = V SB = V DB = 0

CGD or CGS

-500

-lmA

18
18
10

18
.18
10

Max

pF

V PB
V DS

20

20

Max

pF

V G6B = -30V. V PB = V SB = 0
V G1B to V GSB = O. V DB = -SV.
f = 1 mHz

=V GB = V SB = 0
= -SV. f = 1 mHz

Gl16
G118
G119
Gl17

NOTE 1: For the G 117 this is the resistance from each, of the source terminals (5 terminals) and the one drain terminal to the internal junc-

tion of the output MOS·FETs.

.

NOTE 2': Not applicable to Gl18,

3-19

O~Oll

0116-0119
TYPICAL ~HARACTERISTICS

-.

VO II - DRAIN·BODY VOLTAGE (V)

~

1

-30

-25 -20

;:'00
u

,~ ~~~~~~~i:j .....
~ E
§
z

g

-'0

o.

.= 1 MHz

'00
.0

50

)-

c

~

~'O'elllmm
~

c

I ,0L--L__L--L__L--L~
-30 -25

-20

-15 -10

-5

Vos - GATE·SOURCE VOLTAGE (V)

~w

'0

Z

~

,

V OII

-30

-2. -20

-,.

u

,

-VGI-O

-10

-.

0

E 10'

:2

Vos· -10V
Ves -0

,0-'

C

10-2

~

z

J

~

'0'"

Is" l00,.A
TA ·2S·C

C

'0"

~

-30

-20

-'0

-0'

Vas - GATE-SOURCE VOLTAGE IV)

VSI - SOURCE-BODY VOLTAGE IV)

,0'

:>

1;l

c

I

*
~

z

I

'0'

w

:;( 10'"

;;:
c

..in
z

~
U

)-

,

Vas -OV

w

u

.. 10-'
Ii!
. ..
ffi

~

u

Z

SINGLE SOURCE,
ALL TYPES

:>

J

20

/

VSII "VGI--O

'0

~

5l,

i

u

;!
20

.

,

Co

w

U

~ ~'O'

~

-,.

e

'0
-30 -2. -20

-I.

-10

-S

VGs-GATE·SOURCE VOLTAGE (VI

APPLICATION TIPS
Description of Analog Switch

Single Channel

;-

: SOURCE

o

DRAIN

G- Terminal - This is the control terminal of the switch; the voltage at this terminal determines the conduction state of
02.To insure conduction of 02 when voltages between ±10V are switched, the gate voltage (VG) should be
at least 10V more negative than the most negative voltage ,to be switched (-10V). Therefore. V G should go
. to -20V. To insure turn·off VG should not be less than the most positive voltage to be switched. +10V. For
convenience the same potential as the body could be used.
a·Terminal - This terminal is connected to the body (substrate) of the chip and must be maintained at a voltage that is
equal to or greater than the most positive voltage to be switched. This is to insure that the drain·to·body or
.
'
the source·to·body jl!nctions do not become forward biased.
P·Terminal -

The potential. with respect to the body. at this terminal determines the gate·to·source voltage of 0, w.hich
determines the amount of drain current available for driver·collector pull·up. Shorting terminal P to a
prevents 0, and 0 3 from conducting. but still allows the body·to·drain junction of 0, to act as a forward
biased diode for positive gate voltages. and to act as a Zener diode for negative 'voltages which exceed
avoss (-30 to -90V) for protecting the gate of O2 ,'

D.Termina,1 - The. common point of the MOS·FET switches (summing point).
S ·Terminal - This is the normallY'open terminal of the MOS·FET switch and is normally used as the input.

APPLICATIONS
5·Channel Multiplexer With Series Switch

3·Channei Differential Multiplexer

~:C ""'+-+--+--<1
0-------------+
........------+>1

"..

0.:::..1--1---'

aTO -tOV

L

'------TOCONTR0f.LOGIC _ _ _ _- '

'------TOCON'tAQl LOGIC - - - - - '

3·20

U~UlL

DG 120/DG 121
3·Channel Drivers with
Differential Switc'hes
Military Series - 55 0 C to + 125 0 C

FEATURES

GENERAL DESCRIPTION

• 3-Channel With Normally-Off
MOS·FET Switches in One Package
• ,ll.rDS(oN)Matched to Better Than

30n.

This series is composed of three channels in one package,
Each channel is compos.ed of two matched MOS-FET
switches for differential input requirements. Two driver
configurations are available for inverting and noninverting
applications. A. MOS-FET used as a current source provides
an active pull-up load for faster switching.

SCHEMATIC AND LOGIC DIAGRAM (Outline Dwgs DD, FD-2, JD)
DG 121

DG 120 (One Channel)

L='

ORDERING INFORMATION
DG120

A

(One Channel)

TRUTH TABLE

K

Package
K-14·Pin CERDIP
.
L-14-Pin Flat Package
P-14-Pin Ceramic DIP (Special Order Only)
Temperature Range
A - Military (-5S0C to +12S0C)
B - Industrial I_20°C to +85°C)

L -_ _ _ _---,.

DG120

L

Device Chip Type

3-21'

DG121

V'N

VR

V'N

VL

L
H
L
H

L

L

L

L

L
H
H

H
L
H

= OV.

H
H

H

= +V

Switch
Condo
OFF
ON
OFF
OFF

U~UR.

DG120/121
ABSOLUTE MAXIMUM RATINGS
Collector to Emitter (V+ - V-I . . . . . . . . . . . . . . ..
Collector to Pull·Up (V+ - Vp) . . . . . . . . . . • . . . . .
Drain to Emitter (VD - V-I ..... . . . . . . . . . . . ..
Source to Emitter (Vs - V-I . . . . . . . . . . . . . . . . ..
Drain to Source (VD - Vs) . . . . . . . . . . . . . . . . . . .
Source to Drain (VS - VD ) . • . . . . . . . . . . . . ' ..... '
Logic Emitter (VL - V-I . . . . . . . . . . . . . . . . . • ..
Ref. to Emitter (VR - V-I . . . . . . . . . . . . . . . . . . .
Ref. to Input (VR - ViN) ...... '. . . .. . . . . . . . ..
Logic to Input (VL - VIN') .. . . . . . . . . . . . . . . . ..

33V
33V
32V
32V
28V
28V
33V
31V
+6V
±6V

Current (Any Terminal) . . . . . . . . . . . . . . . . '.•.. 30m A
Storage Temperature . . . . . . . . . • . . . . _65°C to +150oC
Operating Temperature . . . . . . . . . • . . _55°C to +125°C
Dissipation (Note) . . • • . • . . . . . . . . . . . . . . . . 750mW
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . 300°C
NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature of 70°C. Derate 10mWfC for higher ambient
temperature.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device: These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability ..

ELECTRICAL CHARACTERISTICS
Test conditions unless otherwise specified are as follows: VR = 0, VL = 4.5V, V+ = 10V, V- = -20V. Input ON and OFF
test conditions are used for output and power supply specifications.
'

PARAMETER
(NOTE 1)

)-

DG120

VINION)

:J
a.

z

-

IIN(oFF)

DG121

MAX LIMIT
-5SoC
1
1.3

+2SoC

10

tIN(ON)

-0.7

-0.7

J.l.A

0.8

1.0

10

CONDITIONS

UNiTS

100
..

.1

IINIOFF)

rOSION)

+12SoC

V IN = OAV

V

liN =,1 mA

20

J.l.A

V IN ='4.1V

' -0.7

mA

V IN = O.SV

100

100

125

51

Vo = 10V

200

200

250

51

Vo = 0

450

450

600

51

Vo = -10V

51

Vo = -10V, Is = -lOOJ.l.A

nA

'VSlalll = lOV, Vo = -lOV

Is = -lmA

)-

:J
a.
)-

Both

:J
0

~rOSION)

30

(Note 2)

\

3

3000

-3

-3000

IsioFFI,

-1

-1000

IRIONI

-0.5

,I OION )
IOIOFF)
DG120

>-

DG121

...J

a.'
a.
:J
tJ)

cr;,

uu

$:

Both

ILION)

3

,leeloNI

3

IEEION)

-6

leel~FF)
ILIOFF)

0

a.

Vo = 10V, Is = 0
Vo = 10V, Vs = -10V

mA

One Channel ON

J.l.A

All Channels OFF

10

,

10

IR(OFF)

-15

IEE(OFF)

-20

tON

300

ns

2

p's

J

Cl
~tJ)

~uu

u:2
)--

See Switching Times

Both

-)-

$:

en

tOFF

NOTE 1: (OFF) and (ON) subscripts refer to th~ conduction state of the MOS·FET switch.
NOTE 2: ArDS(ON) is the resistance difference between differ~ntial switches.

3·22

,

O~O!L

DG120/121
SWITCHING TIMES

DG120

+IDV

+2.4V

orL

16K

V"
t, < 0.1 j.lS
t, < 0.1 "s
-2OV

OV

OUTPUT

2K

JOpF

OGI20
OUTPUT

DG121

OV

'"
t4.5V

oIL

OG121
OUTPUT

'"

OUTPUT

-20V

2K

30pF

APPLICATION TIPS
The recommended resistor values for interfacing RTL, DTL, and T2 L Logic are shown in Figures 1 and 2.

RTL
OTL 937, 946.

RTL

949,961,963

DlL 931, 932, 937
948,949,961,963

OTl 930, 936, 945.
946.962,931
01 L 930, 936
945, 946, 962

-sv

~

10'\

TTL

54/74
TTL 9000 SERIES

TTL 54/74
TTL 9000 SERIES
$UHL

5UHL

Enable Control
The VR and VL terminals can be used as a strobe or an enable control. The requirements for sinking current at VR or
sourcing current at VL are: I L(ON) x No. of channels used, for DG 121 and IR(ON) x No. of channels used, for DG120. The
voltage at VL must be greater than VIN for VIN < 4V. VL must be at least -f'4V for VIN > !IV.

3-23

D~DIl.

.···DG120/121
APPLICATIONS

.-

DG120

7·

.:!!!..es
R"

'0

III

. L ~OUN~-LO;; J
OFFseT VOL T AGE~

3-Channel Differential Multiplexer

TYPICAL CHARACTERISTICS

'OS vs Vo

0'

lK

Is -lmA
125°_ V+ 10V

~ ~~-ssol
-....;
'-'/r:;

E
.c

e

SWITCHING TIMES vs
TEMPERATURE
.

Vs

100

25°- V":" = -20V

. . . r--..--

1400

~

1200

;;; 1000
w
::;;

;:: BOO

Vo -+10V
V+= +10V
V-=-20V
VL • SV •. VR

~UI = 30 P

'"~ 60Q RL, =2k,.........
u
,ien .400

0

!:

200 I-:-I-:-

10
-10

o·
V D OR Vs (VI

liN vs VIN
(OGI20)
1.8

=0 C

/'

"7 ~tOFF -

/

.. -50 -25

VR
V-

1.4

I

=0
= -20V

12S·C~
2SoC I
_55°C I '~

I-

zw

I-:-

a:
a:
:>
u

I

I-

~ 0.6

,
z.

0

TEMPERATURE (OCI

3-24

7
J

.0.2
25 50 75 100 125

101

I

z

tDN

o
+10

<
.5

I7L. . 17
o

0.2

0.4

0.6

0'.8

V ,N -INPUT VOLTAGE (VI

D123/D125
a-Channel FETSwitch Drivers
Military Series - 55 0 C to + 125 0 C

FEATURES

GENERAL DESCRIPTION

• Provides DC level shifting between low-level
Logic and MOS-FET or J-FET switches

The 0123 and 0125 monolithic bi-polar drivers convert
low-level positive signals (0 & +5V) to the high level positive
and negative voltages necessary to drive F ET switches_ One
.lead can be used to provide an enabling capabilitv_

• External Collector Pull-ups required
• Direct interface with G116, G117, G119, G115,
and G123 MOS-FET switches

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
0123

0125

.
'-

.

(IIIAIIUIV.I

ORDERING INFORMATION
D123

.

A

~

LpaCkage
.
K - 14-Pin CERDIP
L - 14-Pin Flat Pack
P - 14-Pin Hermetic DII:' (Special Order Only)
Temperature Range
A - Military (-55°C to +125°C)
B - Industrial (_20°C to +8S0 C)

1..--'--_ _--..,.._ _ Device Chip Type

3-25 .

D123/125
ABSOLUTE MAXIMUM RATINGS
Input-to-Emitter Voltage (V IN - VEE)
Output-to-Emitter Voltage (Vo - VEE)
Logic Supply-to-Emitter Voltage (V L - VEE)
Input-to-Reference Voltage (V IN - VR)
Input-to-Logic Supply Voltage (V IN - V L )
Reference-to-Emitter Voltage (V R - VEE)
Maximum Dissipation (Note)
Current (any pin)

33V
33V
27V
2V
+6V
31V
750mW
30mA

-65°C to +150°C
_55°C to +125°C
300°C

Storage Ternperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)

NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature of 70° C. Derate 10 mWf C for higher ambient
temperature.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS
Test conditions unless otherwise specified are as follows: VEE = -20V, V L = 4.5V;I OUT = 0, V R = O. Output and power
supply measurements based on specified input conditions.

MAX LIMIT
PARAMETER
M
N
~

f:J

a

-z

It}
N

c..

25°C

liN (OFF)

1

1

VIN(ON)

1.3

1

IIN(oFF)

1

1

IIN(ON)

1.5

1.5
0.1

CONDITIONS

125°C

UNITS

100

/lA

V IN = O.4V

V

IIN=1mA

0.8

/lA

V IN =4.1V

mA

V IN = 0.5V

10

/lA

V OUT = +10V

20

~

a
f:J

c..

f:J

C)

1.2

~
It}M
NN

IOUT(OFF)

0.1

VOUT(ON)

-19.7

-19.7

-19.5

V

lOUT = 1 mA

00

VOUT(ON)

-19.2

-19.2

-19.0

V

lOUT = 4 mA

I R(ON)(1)

0.5

0.5

0.5

I R(OFF) (2)

1

1

150

/lA

I EE (ON)(1)

1

1

1

mA

I EE (OFF)(2)

2

2

200

/lA

I L (oN)(1)

2

2

M
N

>..J

mA

~

a

c..
c..

:J
CJ)

cr:
l.U

5:

It}
N

0

c..

I L (OFF)(2)

1

1

I EE (ON)11)

2

2

I EE (OFF) (2)

2

2

1.9

ioo

rnA
/lA

lOUT = a for
ON measurements.
,
V OUT = +1OV for
OFF measurements.

~

a

c.:I

M
N

:Cl.U

a

~CJ)

U2

f--f-

5:
CJ)

_55°C

~

o(l
It}
N
~

a

NOTES: 11)
(2)
13)
14)
15)

1.9
200

mA
/lA

t(on)

250

ns

lOUT = 1 mA COUT (3) = 10 pF

t(oft) (4)

800

ns

(See Switching Times)

tlon )

250

ns

lOUT = 4 mA COUT (3) = 10 pF

600

ns

(See Switching Times)

t(oft) (5)

One channel ON, 5 channels OFF.
All channels OFF.
Add 30 ns per pF for 1 mA and add 8 ns per pF for 4 mA for additional capacitive loading.
For Dual-In-Line package add 120 ns to tloft).
For Dual·ln-Line package add 30 ns to tloft).

3-26

O~OIL

D123/125
SWITCHING TIMES
0123

v,.

IDU .lm"/4 ...... '

Dm
Vo".

'o"I

"V

n

1.< IOn,
I, =

/

1.2
1.1
1.0

I

L

700

CJ

Vee"" -20V

~
:x: 500

v+"" 10V

>-

VR =0

I

f--


./

too

800

1.8

z

:>

........
600

toll (delay)

I I
400

25

75

125

-75

$
>-

fii

a:

125'C

'">-

25°C

a:


I}

l/
o

;t
.5

0.4

,
r

0.2

/

z

75

10'
liN· 1 rnA (0123)
V,N • 0.5V (0125)
VR = a
V L ·4.5V
Vee = -20V Vee = lOV

< 0.3

II

I

25

IOUT(OFFI VS
TEMPERATURE
0123 AND 0125

r

55°C

-25

TEMPERATURE 1°C)

0.6
_VA ·0
Vee = -20V

0

2
z

"""-V

VSAT VS TEMPERATURE
0123 AND 0125

;t

lOUT =

i""-- .........

$

TEMPERATURE 1°C)

liN jPEAt------+-<>0.
s,
s.

"

t===:J::"
3
t===:J::
. t===:J::"
,

o.

G.

G,

S,

"

G,

GIO

8

~

0

" s.

G,

6, 63 6. 65
G,
G,
G,

GIO

5
G.O

"

3

G,a

S,

,

~D'

G.

S.

S.

s. o-t---+-~f--+4!

b.

G,

b,
G.

ELECTRICAL CHARACTERISTICS per channel (25°C unless otherwise noted)
TEST CONDITIONS

CHARACTERISTIC

~

~

25°C
125°C

-0.1
-0.1

-0.1
-0.1

G127
G131

G12B.
G132

G1330
G1350

G1340
G1360

-0.2
-0.2

-0.2
-0.2

-5.0
-5.0

-5.0
-5.0

Gate Reverse Current

V GS

BV Gss

Gate-Source Break·
down Voltage

IG~-l/-lA.Vos~O

Vp

Gate·Source Pinch·
Off Voltage

Vos

IOIOFF)

Drain Cutoff Current

Vos - 10V
V GS ~ -lOV

25°C
125°C

0.05
0.05

0.05
0.05

0.1
0.1

0.1
0.1

0.5
0.5

'SIOFFJ

Source Cutoff Current

Vso ~ 10V
VGo.= -lOV

25°C
125°C

0.05
0.05

0.05
0.05

0.1
0.1

0.1
0.1

0.5
.0.5

loss

Drain Current at Zero
Gate Voltage

Vos = lOV. Vi:;s = 0
(Pulsed)

0.5

2

5

10

15

ros

Drain-Source ON
Resistance

V GS = O. 10 = O. f

500

250

90

45

COG + CSG

Gate·Source plus Gate·
Drain ON Capacitance

V GS ~O. Vos =0. f~ 1 ~Hz

10

10

40

COG

Drain·Gate OFF
Capacitance

2

2

2

2

CSG

Source·Gate OFF

Capacitance

10V. 10

~

O.

G126
G130

IGSS

~

-20V. Vos

G125
G129

0.1 /-lA

~

1 kHz

UNIT

LIMIT

nA
uA

Max

-40

-40

-40

-40

-30

-30

V

Min

-5

-10

-5

-10

-5

-10

V

Max

0.5
0.5

nA
/-lA

Max

0.5
0.5

nA
/-lA

Max

30

rnA

Min

20

10

n

Max

40

300

300

pF

Max

7

7

16

16

pF

Max

7

7

16

16

pF

Max

V GS = -10V. Vos = O.
f = 1 MHz

3-29

0125 - 0132, 01330/40/50/60
ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION

Gate·Drain or Gate·Source Voltage
Gate Current
Total Device Dissipation Free Air (Note)
Storage Temperature Range
()perating Temperature
Lead Temperature (Soldering, 10 sec)

-40V
50 mA
500 mW
-65 to +150°C
-65 to +150°C
300°C

K

A

G125

lp~~kag:

:U
.
·

NOTE: Dissipation rating assumes device· is mounted with all leads
welded· or soldered to printed circuit' board in ambient
temperature below 75°C. For higher temperatures, derate

.

.
.

the device at the rate of 6.7 mwtC.

..

.
K - 14·Pin CERDIP
L - 14·Pin Flat Pack
.
P - 14·Pin Ceramic DIP
(Special Order Only)

Temperature Range

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to abso·
lute maximum rating conditions for extended periods may
affect device reliability.

IJ

TYPICAL

A - Military -55°C to +125°C
B - Industrial -20°C to +85°C
'--...,---'----- Device Chip Type

NOTE: Ceramic DIP available for military temperature
range only.

CHARACTERISTIC~
...z~ -10
w

a:
a:
::>
u

G1330, GI34~~
G1350, G136

V

-1

, 2.0

~~~~~: ~~~~,

~

V

w

en

a:

N

,1.6

!;t

1.4

~

1.2

:J

1.0

~

0.6

V GS
10

-

=a

0

f = 1 kHz

V

N

~

w
a:
w _-0.1

G125, G126,G129, G130

/ V

~ 0.8
a:

\t

k

--0.01

VG, -20V
Ves - 0

V

.~

W

~.

100

TEMPERATURE

V

l.--'

0.2

o

lW

1~

V

~ 0.4

CJ

"

1.8

-75

-25

lOCI

75

25

TEMPERATURE

125'

lOCI

APPLICATION
4·Channei Commutator Circuit

>-.....-U'

V.....J.IV

VII "_lOY

OUT

OFF MODEL

OFF MODEL
5pF

hfIOGI40,'4'1

IpF

5pF IDG151. 1531

-m·~

~~:T···'"r ± '~F·=-

ON MODEL

ON MODEL

-=-

":'

1.0 pi'

':'

"n

':"

':'

":'

'n'

.

sou""'~ .....

_M3~_'

I·"Y. " .

. I··'~-r·" .'
·3·33

D~DIl.·

DG12el1291133113411401
. 1411151115211531154
TYPICAL CHARACTERISTICS (per channel)
DG151, 152,153, 154

DG126, 129, 133, 134,140,141

VIlli THRESHOLD
vs TEMPERATURE

VIN THRESHOLD
TEMPERATURE

VI

2

,

VR =0
V+~+12V
ON V-=:-12V

~~

~

1

~~

...J

0

%

-

OFF

V R =0
. V+=+15V

2

0

...oz:

ON

V-=-12V

OFF

-..

III

%

1-'
I:::l

...!
,
z

:>

o

-75

25

-25

76

o

125

-75

-25

TEMPERATURE C·CI

rDSCONI
VI TEMPERATURE
CNormalized to 25°C Valuel

2

100
OG152,154

I-V+:" +12V
_V-.=·-18V

o

-75

[...oi .....
".

E
.c

,g
Z

-25

25

1000-

10

OG151,OG163

~
E

"

I;i;

,.

';t

.....

..... 10'

i--'"

125

75

rDSCONI
vs TEMPERATURE

VIN =2.5V
r-VR = 0 .

1

25

TEMPERATURE C·CI

-

I

75

125

-75

-25

'TEMPERATURE C·CI

25

75

125

TEMPERATURE C·CI

ALL CIRCUITS
ON SUPPLY CURRENT
"'.TEMPERATURE

2.6
;(

!

2,2

1000 _ _

r- l - I
r- I - I:x:.

...oz:

~

100

oz:
:::l
u

1.4

>
1.0
...J

......

:::l

III

0.6

0

0,;2

r- -

- -

121~NI

1

I-

~~m

~ !;;il!!~!~1
!2

1.:ON1

-"T

z

.E

OG152,
154

OG125,I29,
133,134

10

0.1

-75 -60 -25 0

25 60· 75 100 125

TEMPERATURE (·CI

10
;(

I-

z 1.8

OFF SUPPLY CURRENT
vs TEMPERATURE

'O(OFFI VS TEMPERATURE

.

25

45

65

85

105

TEMPERATURE C·CI

3-34

125

...oz:

I I I

Z

I I I

Y

I

oz:

:::l
U

>
...J

...... . 0,1
:::l

III

U.
U.

0

V

0.01
25

45

65'

85. 105

TEMPERATURE I·CI

125

D129
4·Channel MOS FET Switch
Driver with Decode

FEATURES

GENERAL DESCRIPTION
The D129 is a 4'Chanmil driver with binary decode inpu't_ It
has been designed to provide the DC level-shifting required
to interface low-level logic outputs (0.7 to 2_2V) to fieldeffect transistor inputs (up to 50V peak-to-peak). For a 5V
input logic supply. the V- terminal can be set at any voltage between -5V and -30V_ The output transistor is capable of sinking 1 OmA and will stand-off up to 50V above V - I I
in the off-state_
'

• Quad Three-Input Gates Decode Binary Counter to Four
Lines

•

Inputs Compatible with Low Power TTL and DTL.
IF = 200J,lA Max

The ON state of the driver is controlled by a logic "1"
(open) on all three input logic lines. while the OFF state of
the driver is achieved by pulling anyone of the three inputs
to a logic "0" (ground).

• Output Current Sinking Capability10mA

•

External Pull-Up Elements Required

The 4-channel driver is internally connected such that each
one can be controlled independently or decoded frorri a
binary counter_

• Compatible with G 115 and G 123 Series Multichannel
MOS FET Switches which include Current-Limiter PullUp FETs

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DO, FD-2, JD)
v'

v'

"
IN,

13

OUT 1

36K

IN2
12
IN3
IN.
IN5

11

INPUTS
QUl Z

va

OUT 3

1N6
1~

OUT 4

IN7

(EACH DRIVER)
GND

V-

ORDERING INFORMATION
D129

A

K

l=
'.

PaCkage
\
K - 14-pin CERDIP
L - 14-pin Flat Pak
.
P - 14-pin Ceramic DIP (Special Order Only)

Temperature Range
A - _55°C to +125°C
B - _20°C to +85°C
L.._ _ _ _ _ _ _ Device Chip Type

3-35

.

O~OIL

D129
ABSOLUTE MAXIMUM. RATINGS
<

•

'

'

"

•

;

Note: Dissipation rating assumes device mounted with all leads welded

Vo - V- ..... : ....... : . . . . . . . . . . . : ...... 50V
GND -V- , ..........................' ... 33V
V+ - GND .; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V'
VIN - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . " ±6V
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . 30mA
Storage Temperature. . . . . . . . . . . . . .. _65°C to +150°C
0perating Temperature ...... . . . . . .. -55°C to +125°C
Power Dissipation (note) .... : . . . . . . . . . . • . . . 750mW
Lead Temperature (Soldering, 10sec) . . . . . . . . '... '. 300°C

iii

ElECTA ICAl CHARACTERISTICS To" ooodl'oo.
PARAMETER
VaL
a
U VaL
T laH
I
*
I INH
N
IINL *
T'
I ton
M
E toff

00'".

or soldered to pc board in ambient temperature of 70 0 e. Derate 10mW/oe
for higher ambient

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

"'h".l~

",,,,;ft,d V- • -20V,

MAX LIMITS

I

1.0 = 10mA

1.0= 1mA 1 VIN = 2.2V, v+ = 4.5V

.output Current, High

Va= 10V, V IN = 0.7V
V IN- 5V Input Under Test,

Turn-aN Time

VIN

"19.8 -19.8 -19.75
0,1

0.1

20

0.25

0.25

5

V

,.

10

0.2

0.2

1

1

5

-250

-225

-?OO

f.l.A

= 0, V+ =5.5V

S lEE
U
P
P IL

Negative Supply Current
Logic Supply Current

V-

~

lEE

Negative Supply Current

V+= 5.5V

IL

Logic Supply Current

-250

-200

-160

0.25

0.3

1.0

1.5

-2

One Channel "aN"

= -20V

f.l.s

- 2.25

-25

All VIN = 0,

-10

All Channels ".oFF"

0.75

.

.,~={
OV

1

SWITCHING TIME AND TEST CIRCUIT
+10V

tf'" lOOns

3.

=--

IN~J-I>+-+---<> OUT

'-20V

tr = lOOns
t pw = 1#$

f=100KHz

r

."

ton

t-tOff

+10V----~

OUT

ov _ _ _ _ _-'.1

-20V _--'-_ _ _-.:..:17.:..:V*.:;90%::::--_ _ _ _---I

3-36

mA

3.3

3

* Per gate Input

+5V •

f.l.A

All ather Inputs

See Switching Time Test Circuit

Turn-aFF Ti~e

UNIT

25°C 125°C -20°C 25°C 85°(,:
-19.25 ~19.25 -19
-19.3 -19.3 -19

.output Voltage, Low

Input Current,
Input Voltage Low

01291

_o5°C

.output Voltage, Low

V IN = 0

v+· 5V

D129M

CONDITIONS

Input l,;urrent
Input Voltage High

termperatures~

f.l.A
mA

U~U[l

DG139, DG142 - DG146,
DG161 - DG164.
Drivers with, Differentially Driven
N.O. and' N.C. FET Switches

FEATURES

GENERAL DESCRIPTION

• Each channel complete-interfaces with mOst integrated logic

Each ,package contains a monolithic driver with differential
input and 2 or 4 discrete FET switches. The driver may be
treated as a special purpose differential amplifier which
controls the conduction state of the FET switches. The
differential output of the driver sets the switches in opposition, one pair open and the other pair closed. All switches
may be opened by applying a positive control signal to the
V R terminal.

• Low OFF power dissipation, 1 m'W
• Switches analog signals up to 20 volts peak-to-peak
• Low rOS(ON), 10 ohms max on DG145andDG146

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, jD)
DPDT

SPDT

OG139(rOS(ONI = 30m
OG142(rOS(ONI = 80m
OG145(rOS(ONI = 10m
OG163(rOS(ONI = 150)
OG164(rOS(ONI = som

OG143(rOS(oN) = 80m
OG144(rOS(ON) = 30m
OG146(rOS(ONI = 10m
OG161 (rOS(ON) = 15m
OG162(rOS(ON) = 50m

\1

v'

0....1------o,_.--\-....7sw,
....

IN, ~--+---'

14
1
<>-t------0'j'~-+ 5 SWJ

~1------~'--\-~3

sw,

O""I----:----O-('--\--<> sw,
v12

v- 12

ORDERING INFORMATION
DG139

'
L=
A

K

L-_ _ _ _ _ _ _ _ _ _

3-37

Package
K - 14-pin CERDIP
L - 14-pin Flat Pack
P - 14-pin Cerarr1ic DIP (Special.order .o~IY)
Temperature Range
A - Military _55°C to +12So C
B - Industrial _20°C to +8So C
Device Type

/

DG139, DG142 -

DG146, DG161 -

DG164

,.

ABSOLUTE MAXIMUM.RATINGS
V+ - V- . . . . . . . . 36V
Vs - V30V
V+ - Vs
30V
Vs . - VD
. ±22V
v R -V- . . . . . . . . 21V
Power Dissipation (Note)
Current (any terminal)

V+ v+ VIN1
VIN1
VIN2

VR .
17V
VIN1 or VIN2 . 14V
±6V
- VIN2
±6V
- VR .
±6V
- VR .
750mW
. . . 30mA

Storage Temperature
. . . . . . ,.
Operating Temperature . . . . . . . . .
Lead Temperature (soldering, 10 sec)

-65 to +150°C
-55 to +125°C
300°C

NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in amb·ient
'temperature below 70° C. For higher temperature, derate at
rate of 10 mwtC.

Stresses above those listed under~·Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS
Applied voltages for all tests: DG139, DG142, DG143, DG144, DG145, DG146 (V+ = 12V, V-= -18V, VR = 0,
VIN2 =2.5V) and DG161, DG162, DG163, DG164 (V+ = 15V, V- = -15V, VR = 0, VIN2 =2.5V).lnputtestcondition
that guarantees FET switch ON or OFF as specified is used for output specifications.

SYMBOL
(NQTE)

V,NIONI

N

TYPE

Input Volt. On

VINIOFFI

Input Volt.-Otf

IVg -V131

Differential Voltage

TEST CONDITIONS

25'

1250

2.9 min

2.5 mm

2.0 min

Volts

At Pm 9 and 13 See Figure 1 and 2. Pg. 4

0.6

Volt!.

At Pin 9 and 13 See Figure ,. and 2. Pg. 4

Volts

See Note '. Pg. 4

I."

60

60

"A

V '''-i 1

3 OV

60

60

"A

V,,,,]

20V

Input leakage Current

Drain·Source On Resinanee

w
C
H

o
U

'O(ONI .. ISION •

Drive Leakage Current

'SIOHI

Source Leakage Current

IOIOFFI

Drain Leakage Current

T

IOIONI + 'SIONI

Drive Leak. Current

P

ISIOFFI

Source Leakage Current

U
T

'OIOFFI

Drain Leakage Current

IOIONI + 'StON.

Drive Leakage Current

'StOFF)

Source Leakage Current

IOIOFF'

Drain LAhti' Current

IOIONI

+ 'SIONI

..-'SIOHI

p

o

w

u
p

01

01

"A

V'''-il

2 OV

01

01

"A

V'''-i]

3 OV

OGl42
OG143

80

80

150

..

OG139
OG144

30

30

.60

"

VO" 10V, IS '" -lmA

OGI45
OG146

10

10

20

~l

OGI61
OG163

15

15

30

~1

OG162
OGI64

50

50

100

U

100

nA

Vo · V,

100

nA

V, . lOY. Vo

100

nA

Vo . lOV. Vs '. -lOV

OG139
DG142
OG143
OG144
OG145
OG146

OG161
OG163

-lOV
-IOV

100

nA

Vo

Vs~-10V

1O

1000

nA

V,

lOV. Va

-IOV

10

1000

nA

Vo · 10V. Vs

-lOV

500

nA

Vo - Vs . -7.5V

10

1000

nA

V,

10

1000

nA

Vo ·7 SV, VS . -7.SV

500

nA

Vo " Vs ' -7.SV

200

nA

V, - 7.SV. Vo ' -7.SV

200

nA

Vo : 7 5V. Vs - -7.5V

OGI62
DG164

IOIOFFI

Drain Leak"" Curr.. nt

I'IONI

Positive Power Supply
Drain Current

40

mA

'lION)

NegatIVe Power SupplV
Drain Current

-20

mA

''''(ONI

Reference Power Supply
Drain Current

-2.0

mA

1'(OfF)

POSitive Power Supply
Leakage Current

25

~A

'210fF)

Negative Power Supply
Leakage Current

-25

"A

'AIOFfl

Reference Power Supply
Leakage Current

-25

.A

y

VO'" lOY, IS'" -lmA

Vo · 7 5V, 's ' 1 mA

Drive Leak. Current
Source Leakage Current

O.Smm

120

IIN2(OFF)

rOSIONI

1.0
0.5 min

120

Input Current

IIN2(ONI

'INHOFFI

UNITS

_55'

0.5 min
All ClrCll,lts

IINHONI

U

ABSOLUTE MAX. LIMIT
CHARACTERISTIC

7 SV. Vo ' -7.SV

V IN • ·3V

V IN1 ·2V

p..11 Circuits

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

3-38

V IN1

~

V IN ] ,

a.sv

DG139, DG142 -

O~OIL

DG146, DG161- DG164

ELECTRICAL CHARACTERISTICS PER CHANNEL (cont.)
ABSOLUTE MAX. LIMIT

SYMBOL
INOTE)

CHARACTERISTIC

UNITS

TYPE
_55°C

toN

DG139,OG142
OG143,DG144
DG162.DG164

Turn·On Time

26'
0,8

"'
0,7

0,4

"'

OG162.0G164
OG139.0G142
OG143,DG144
DG162,DG164

S

toFF

Turn-Off Time

N
G

1,6

OG139. QG142
OG143.0G144

"'

0,8

1,2

"'
"'

0,8

,"'

DG162,DG164

C
H
I

OG145. DG146

toN

1.0

OG161,OGI63

Turn·On Time

DG14S. QG146

Turn-Off Time

l

0,5

OGiSt,oG163

toFF

DG14S.0G146
DG'161.DG163

2,5

OGI45,OG146
DG161,OG163

1.25

PON

E

P OFF

ON Dnver Power

See Below

See B\!IOW

"'
"'

1,8

,

p

0
W

See Below

OG139.0G142
DG143.DG144

W
I
T

TEST CONDITIONS

1250

See Below

175

mW

Both Inputs VI!'.!

I

mW

Both Inputs V 1N ~ t.OV

All CirCUits

OFF Driver

power

R

NOTE: (tiFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test,

SWITCHING TIMES (25°C)
DG139, 142,143,144,145,146

"

DG161, 162, 163, 164
v,~,

v.~.

t. ~

I) 1~.

1.' 0

t~.

.'

I." 0

I~.

aI

v,~,

t, .:: 0 1 ~I
t, < I~.

°

I. "0 I ~I
t, ... Olu'

SWI802
OUTPUT

SW II!o 2
OUTPUT

v.' ·IOV

~~~"t~
V. '15V

S..... 31!o'

v. 'IOV

SWJ&'
OUTPUT
V.' J5V

SW380~

SW3&4

SW1&2

OUTPUT

OUTPUT

OUTPUT

V.··IOV

V•• IOV

V.' ·15V

OUTPUT

V.' ·15V

-.

ov

y+ :·12Y

v+·

Y-'-18Y

OFF MODEL

l~C

y-. -15Y

OFF MODEL
5pf
IlpF

~

"I' IOGI61. 1611
11"F 10THERSI

"'~::f "l~" f·'.':'~' ' "
1 0,,1'

ON MODEL

ON MODEL

'O""".~"'"

' 'L4"'"' .
3·39

'

2.SV

DG139, DG142 -

DG 146, DG161 -

n~nlb

DG164

FIGURE 1

FIGURE 2

"'OLUTE VOLTAGE

VOLTAGE AT PIN 13

LEVELS FOR SWITCHING
WITHONE SIDE OPEN AND
OTHER SIDE SWITCHED AT

NECESSARY TO SWITCH
WHEN 81AS AT PIN 9 IS

.2.flV AT 25"C

2SoC

a

4
V'N (Pin 13)

V IN (Pins9 or 13)

NOTE1: An example of Absolute Minimum Oifferential Voltage. iV, - V I ,i. is when V,
.

ON and the V I ' side of the switch is OFF at 25°C. Converseiy. when V,
the V I' side of the switch is ON at 25°C ..

= 2V and

= 3V
V

13

and V I , = 2.5V. the V, side of the switch is
= 2.5V. the V, side of the switch is OFF and

TYPICAL CHARACTERISTICS (per channel)
OG139.142. 144. 145. 146
VIN1THRESHOLO

vs TEMPERATURE

IOIOFFI vs TEMPERATURE

'OS(ON) vs TEMPERATURE
1000

100

""

.;!W 1 &2ARE ON_

~

ijh ij/: ~
~h ij/,
(£h ij/,
ij/

~

rh

. . f1T

[5W 1& 'AfEO'F"

z

:>

.

OG142.143

.J...-

10

:..... U"/,

--

100

~

L..-

DGtt.t-

~~

~

V

10
DG145.146

~E

8

DG145.146

0

:§

EXCEPT
DG145.146

=

"

a
-75 -50 -25

a

1

25 50

75 100 125

-75 -50 -25

TEMPERATURE (C)

0.1

a

25

50 75 100 125

25

45

65

85

105

125

TEMPERATURE I'CI

OG161. 162.163.164
VIN1 THRESHOLD

vs TEMPERATURE

ROSION) vs TEMPERATURE
100

,;!~
""Vh
V./.'
~
~

~~

t'h Vh

.....

z

to
z

[51'0 1&

:>

~

!AIEO~

""

r/h 0:;
r/h Yh i"h
V'h Vh i"h

"'~f1T
a
-75 -50 -25

a

DG162.164

1 ~ 2ARE ()N_

""

~

75 100 125

TEMPERATURE I'C)

...;;

;;,;;;.
.£
i

o

100

./

~

;;:
L..- I -

10

DG161.163

~

1
25 50

IS(OFF) vs TEMPERATURE

1000

-75 -50 -25

a

::

F

S

DG161.163

V

10
0

ji

.....

DG162.164

0.1
25

50

75 100 125

TEMPERATURE I'CI

3·40

25

45

65

85

105

TEMPERATURE ('C)

125

DG180·191
High·Speed Driver With
Junction FET Switches

FEATURES

GENERAL DESCRIPTION

• Constant ON-resistance for signals to ±10V (DG182,
185, 188, 191), to ±7.5V (all devices)
• ±15V power supplies
• _<2nA leakage from signal channel in both ON and
OFF states
• TTL, DTL,RTL direct drive compatibility• lon, toff <150ns, break-before-make action
• Cross-talk and open switch isolation >50dB at
10MHz (750 load)

The DG180 thru DG191 series of analog gates consists of2
or 4 N-channel junction-type field-effect transistors (J-FET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8 to 2V) to control the ONOFF state of each switch. The driver is designed to provide a
turn-off speed which is faster than turn-on speed, so that
break-before-make action is achieved when switching from
one channel· to another. In the ON state, each switch
conducts current equaily well in both directions. In the OFF
condition, the switches will block voltages up to 20V peak-topeak. Switch-OFF input-output feedthrough is >50dB down
at 10M Hz, because of the low output impedance of the FETgate driving circuit.

SCHEMATIC DIAGRAM (Typical Channel)
ONE AND TWO CHANNEL SPDT AND SPST
CIRCUIT CONFIGURATION

TWO CHANNEL DPST CIRCUIT CONFIGURATION

v+

VL

v+

VL

IN

IN

S
D

S
D

II

II

GND

v-

DG186/187/188 SHOWN

GND

~~_-,--.6---4----l

DG183/184/185 SHOWN

y-

ORDERING INFORMATION
PART
NUMBER
DG180
DG181
DG182
DG183
DG184
DG185
DG186 .
DG187
DG188
DG189
DG190
DG191

DG

rDS(on)

TYPE
DualSPST
Dua-I SPST
DualSPST
Dual DPST
Dual DPST
Dual DPST
SPDT
SPDT
SPDT
Dual SPDT
Dual SPDT
Dual SPDT

181

x

Y

L

(MAX)
10
30
75
10
30
75
10
30
75
10
30
75

PACKAGE
A· lO·PIN METAL CAN
L - 14·PIN FLAT PACK
P . CERAMIC DIP (Special Order Only)
K· CERDIP

L -_ _ _ _ TEMPERATURE

A - MILITARY -55°C TO +125°C
B - INDUSTRIAL -20°C TO +85°C
L -_ _ _ _ _ _ DEVICE TYPE

L------'-----DRIVER

3-41

3

o~o[!,

00180·191
MAXIMUM RATINGS
V+·V- .............. 36V
. V+·'vo ....... , .... , .. 33V
Vo·V- ... '" ... : .......33V
Vo·Vs ............. ±22V
VL·V- ............... 36V
Lead Temperature (Soldering,

Current (S or D) See Note 3 ..................... 200mA •
Storage Temperature ................ -65"Cto +150"C
Operating Temperature .............. -55"Cto +125"C
Power Dissipation' ................ 450 (TW), 750 (FLAT),
825(DIP)mW

VL·VIN ················8V
VL·GND .............. BV
VlwGND .............. 8V
GND·V- ............. 27V
GND·VIN ............... 2V
10 sec) ........... 300°C

'Device mounted with all leads welded or soldered to PC board.
Derate 6mW/'C (TW); 10mW/'C (FLAT); llmW/'C (DIP) above
75·C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not.
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V+= +15V, V- = -15V, VL =5V, Unless Noted)
PARAMETER

DEVICE
OG181. 182. 184. 185
187, 188;,190, 191
IOG180, 183, 186, 1891

-5S·C

S

B SERIES
-20'C . +2S·C
5

+8S·C
100

.
UNITS
nA
V-

1010111

10(on)

+

IS(on)

1151

130m

1
1101

100
110001

5
1151

100
13001

nA

Vs ~ 7.5V, Va
V,N ~ "OFF"

OG182, 185, 188,191

1

100

5

100

nA

Vs ~ 10V, Vo
V,N ~ "OFF"

OG181, 182, 184, 185
187, 188, 190, 191
lOG 18'0, 183, 186, 1891

1

100

5

100

1101

OG181, 184,'187, 190
IOG180, 183, 186, 1891

1
1101

OG182, 185, 188, 191

1

OG180, 181, 183, 184
186, 187, 189, 190

Ion
0
y
N
A
M
I
C

toft '

1-

S
U

P
P
L
Y

110001
100

5

100

nA

Vs'~ 10V, Va
V'N", "OFF"

-2

-200

-10

-200

nA

Va

~

10

20

300

-250

~

"ON"

nA

Va

~ Vs'~

V,N

~

10

20

~A

V,N = 5V

ns

See switching time test circuit

150

300

'1011 Switches

250

300

3011 and 7511 Switches

130

150

9 typical 121 typicall
6 typical 117 typicall
14 typical 117 typicall
Typically >50dB at 10MHz ISee Note 21

pF

-10V, V,N

~

"ON"

OV

Vs = -5V, 10 = 0, f = 1MHz
Va - +5V, Is - 0, f - 1MHz
Va Vs 0, f - 1MHz
75!l, CL 3pF
RL

1.5

0.1

0.1

0.8

0.8

-5.0

-5.0

-4.0

~.O

-3.0

-3.0

OG180, 181,182, 183,
184, 185, 189, 190, 191

4.5

4.5

Il

OG186 187 188

3.2

3.2

IGNO

ALL

-2.0

-2.0

1.5

1.5

1+

OG180, 181, 182, 189,
190,191

Il

-7.5V, V,N

~A

250

OG183, 184, 185

3.0

3.0

OG186 187 188

0.8

0.8

OG180, 181, 182, 189,
190,191

-5.0

-5.0

OG183, 184, 185

-5.5
-3.0

-5.5
-3.0

OG180, 181, 182, 183,
184, 185, 189, 190, 191

4.5

4.5

OG186, 187, 188

3.2
-2.0

3.2

OG186, 187, 188

~

-10V

-200

OG186, 187, 188

1-

Vs

~

~

7250

3011 Switches

1.5

~

-10

7511 Switches

OG180, 181, 182, 189,
.190,191
OG183, 184, 185

10V

-250
350
180

OG186, 187, 188

~

"OFF"

Vs - 7.5V, Va - -7:5V
V,N ~ "OFF"

1011 Switches

OG181, 182, 184, 185,
187, 188, 190,191
Co on) + eS(on) IOG180, 183, 186, 1891
OFF Isolation
OG180, 181, 182, 189
190,191
1+
OG183, 184, 185

-20V, VIN

nA

ALL

-250

V-

100
13001

-250

CSlofll
COlo1I1

-1PV, V+

13001

-200

IINH

Vo~

-10V

5
1151

-2

ALL

10V,

~

-7.5V

1151

,110001
100

-250

IINl

Vs~

~

nA

OG182, 185, 188, 191
I
N

= -20V, VIN = "9FF"

110001

W
I
T
C
H

TEST CONDITIONS
(Nole'11
Vs -10V, Vo - -10V, V+ -10V

1101

OG181, 184, 187, 190
IOG180, 183,186,1891

ISloff)

A SERIES
+2S'C
+12S'C·
1
100

V,N = 5V

rnA

V,N = OV

\

IGNO

ALL

~2.0

Note 1: See SWitching State Diagrams for VIN " ON " and VIN " OFF " Test Conditions.
Note 2: Off Isolation typically >55d8 at lMHz for DG180, 183. 186, 189.
Note 3: Saturation Drain Current forDG180, 183, 186, 1890nly, typically300mA (2msec Pulse Duration). Maximum Current on all other devices
(any terminal! 30mA.

3·42

DG180·191
ELECTRICAL CHARACTERISTICS (CONT'D)
MAXIMUM RESISTANCES (rOS(ON) MAX)

DEVICE
NUMBER
DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG191

MILITARY TEMPERATURE
-55°C
+25°C
+125°C
10
10
20
30
30
60
75
75
100
10
10
20
30
30
60
75
75
150
10
10
20
30
30
60
75
75
150
10
10
20
30
30
60
75
75
150

INDUSTRIAL
TEMPERATURE
-20°C
+25°C
+85°C
15
15
25
50
50
75
100
100
150
15
15
25
50
50
75
100
100
150
15
15
25
50
50
75
100
100
150
15
15
25
50
50
50
100
100
150

CONDITIONS (Note 1)
V+ = 15V, V- = -15V, VL = 5V

UNITS

n
n
n
n
n
n
n
n
n
n
n
n

Vo =-7.5V
Vo =-7.5V
Vo =-10V
Vo =-7.5V
Vo = -7.5V
Vo = -10V
Vo =-7.5V
Vo = -7.5V
Vo ;-10V
Vo =-7.5V
Vo = -7.5V
Vo =-10V

Is =-10mA
VIN = "ON"

APPLICATION HINT (for design only): Normally the minimum signal handling capability of the DG180 through DG191 family is 20V peak.to·m
peak for the 751l switches and 15V peak·to·peak for the 101l and 301l switches (refer 10 and Is tests above). For other Analog Signals, the
following guidelines can be used: proper switch turn·off requires that V- sVANALOG(peak) -Vp where Vp = 7.5V for the 101l and 301l switches
and Vp =5.0V for 751l switches e.g., -10V minimum (-peak) analog signal and a 751l switch (Vp=5V), requires that V-s-10V
-5V= -15V.
.

SWITCHING TIME TEST CIRCUIT

switching time test circuit. Vo is the steady state output with
switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.

Switch output waveform shown for Vs = constant with logic
input waveform as shown. Note that Vs may be + or - as per

LOGIC INPUT FOR "OFF" TO "ON" CONDITION (OG180/181/182 SHOWN)
LOGIC 3V
INPUT
tr <10ns
tf <10ns

SWITCH
OUTPUT

1.SV

1.....- - - -....... 1

A-+-~~--~--ova

SWITCH Vs --In;~];::::::::::::+=:::;,INPUT
0.9 Va
SWITCH
OUTPUT

too

Va

= Vs RL + ~~S(ON)

'":"

DUAL SPST

DUAL DPST

SPDT

DUAL SPOT

DG180/f81/182

DG183/184/185

DG186/187/188

DG189/190/191

TEST CONDITIONS
DG180/181/182
VIN "ON" = 0.8V
VIN "OFF" = 2.0V

TEST CONDITIONS

I

VIN
VIN
VIN
VIN

All Channels
All Channels

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

TEST CONDITIONS
DG186/187/188
Channel
"ON" = 2.0V
Channel
"ON" = O.BV
Channel
"OFF" = 2.0V
Channel
"OFF" = 0.8V

1
2
2
1

SWITCH STATES ARE
FOR lOGIC "1" INPUT = 2.0V

3-43

VIN
VIN
VIN
VIN

TEST CONDITIONS
DG189/190/191
"ON" = 2.0V Channels
"ON" = O.BV Channels
"OFF" = 2.0V Channels
"OFF" = O.BV Channels

1&
3&
3&
1&

SWITCH STATES ARE
FOR lOGIC "1" INPUT = 2.0V

2
4
4
2

O~OIL
DG180·191
PIN CONFIGURATIONS AND SWITCHING STATE DIAGRAM (See previous page for logic input)
DUAL SPST (DG180, 181, 182)
Metal Can Package

Flat Package

CERDlp·

(OUTLINE DWG FD·2)

(OUTLINE DWG JD)

YL

(OUTLINE DWG TO·100)

DUAL DPST (DG183, 184, 185)
CERDlp·

Flat Package

5,C===;:::;;J

14

r;:===::J 5
3

03

Y+

(OUTLINE DWG JE)

(OUTLINE DWG FD·2)

SPOT (DG186, 187, 188)
Metal Can Package

CERDlp·

Flat Package
NO

C::=====;::;J

14

r:;:===:::1 NC
NC

NC

NC
YL

v-

v+

(OUTLINE DWG FD·2)

(OUTLINE DWG TO·100)

(OUTLINE DWG JD)

DUAL SPD! (DG189, 190, 191)
CERDlp·

Flat Package

" 53
r;:===::J
03

v-

Y+

(OUTLINE DWG FD·2)

·Slde bralze ceramic package available"
as special order only. Consult factory.

3·44

(OUTLINE DWG JE)

DGM181·191
High-Speed
CMOS Analog $witch••

FEATURES

GENERAL DESCRIPTION

• Pin and Function Replacement for DG181 Family
• Meets or exceeds all DG181 family specifications
with monolithic reliabillity
• low power consumption
• 1nA leakage from signal channel. In both ON and
OFF states
.
• TTL, DTl, RTl direct drive capability
• to", toff < 150ns, break·before·make action
• Crosstalk and open load switch Isolation > SOdB at
.. 10MHz (750 load)

The DGM181 family of CMOS monolithic switches utilizes
Intersil's latch-free junction isolated processing to combine
the speed of the hybrid DG181 family with the reliability and
low power conslimption of a monolithic CMOS construction. These devices, therefore, are an ideal replacement for
the DG181 family.
The DGM181 family has a high state threshold of 2.4V;
devices which have a threshold of 2.0V (the DG181 specification) can be selected and are avaliable as the DGMS
series - see ordering Information.
.
Both series meet or exceed all other specifications of the
DG181 family.
No quiescent power is dissipated in either the ON or OFF
state of the switch. Maximum power supply current is 10pA
from any supply, and typical quiescent currents are in the
10nA range. OFF leakages are guaranteed to be iess than
200pA at 25 ·C.
.

SCHEMATIC DIAGRAM. (Typical Chan",el)

v. OF DGM182
ORDERING INFORMATION
TYPE
DualSPST

Dual DPST

SPOT

Dual SPOT

STANDARD
PART.
NUMBER
DGM181BX
DGM182AX
DGM182BX
DGM184BX
DGM185AX
DGM185BX
DGM187BX
DGM188AX
DGM188BX
DGM190BX
DGM191AX
DGM191BX

SELECTED
PART
NUMBER
DGMS181BX
DGMS182AX
DGMS182BX
DGMS184BX
DGMS185AX
DGMS185BX
DGMS187BX
DGMS188AX
DGMS188BX
DGMS190BX
DGMS191AX
DGMS191BX

DGM
rOS(on)

MAX
AT 25°C
50
50
75

S

181

A

A

L~,

A· 1IJ.PIN METAL CAN
L· 14-PIN FLAT PACK
K • CERAMIC DIP
J. EPOXY DIP

50
50

L -_ _

75
50
50
75
50
50
75

L -_ _ _ _.

TEMPERATURE RANGE
A· MILITARY -SS'C TO +12S'C
B • INDUSTRIAL -20'C TO +85'C
DEVICE TYPE

1..-_ _ _ _ _ _ _ OPTION

CMOS ANALOG DRIVER

3-45

8J

.

O~O[l,

DGM181·191
. MAXIMUM RATINGS
v+-v- .......... 36V
v+-Vo •.•.....•.•• 33V
Vo-V - ..•.••...•.. 33V
Vo-Vs ........... ±22V

VL-VIN .•.....•.•.•
VL-VGNO •.••.••••••
VIN-VGNO •.•...•...
GND-V- ..........

Storage Temperature. . . . . • . . • • . . . .. - 65·C to + 150·C
Operating Temperature. . . . . . . • . . . .• - 55·C to + 125·C
Power Dissipation' ......... ; ••••• 450 (TW), 750 (FLAT),
.
825 (DIP) mW

30V
·20V
20V
27V

VL -v - .••..•...... 36V
GND-VIN ••••....• .- 20V
"Device mounted with all leads welded or soldered to PC board.
Current (Any Terminal) •...••••...••••..•.•....• 30mA
Derate 6mW'oC (lW); 10mW'oC (FLAT]; 11mW'oC (DIP) above 75°C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V+
PARAMETER
lS(ofn·
S

-SsoC

A SERIES
+2SoC
+12SoC

OGM182, 185, 188, 191

W

I
T
C
H

DEVICE
OGM181, 184, 187, 190

= +15V, v- = -15V, VL=5V, unless noted)

0.2

-20°C

B SERIES
+2SoC
2.0

+8SoC
100

0.5

50

2.0

100

0.5

50

5.0
2.0
10
10
180
300
150

106
50
20
20

50

DGM181, 184, 187, 190

10(01n

OGMJ82, 185, 188, 191

0.2

50

"

OGM181,
OGM182,
ALL
ALL
OGM181,
OGM182.

1000n) + l6(on)
I
N
D
y
N
A
M
I
C

IINL
IINH
Ion

184, 187, 190
185, 188, 191

0.5
1.0
1.0

184, 187,'190
185, 188, 191

ALL
loff .
OGM181, 182, 184, 185,
Cs(oln
187, 188, 190. 191
CO(ofn
CO(on) + CS(on)
OFF Isolation
1+
ALL
I
ALL
S
ALL
IL
U
ALL
IGND
P
P
1+
ALL
L
I
ALL
Y
ALL
IL
ALL
IGNO
NOTE 1. See Switching State Diagrams for VIN " ON " and

50
20
20

250
130

10
10
10
10
10
10
10
10
VIN

5pF typical
6pF typical
11pF typical
Typically >50dB al 10MHz
100
100
100
100
100
100
100
100
" OFF " Test Conditions.

..

TEST CONDITIONS
UNITS
(Nole 1)
nA
Vs=7.5V, Vo= -7.5V
VIN="OFF"
nA
Vs-10V, Vo- -10V
VIN = "OFF"
nA
Vs = 7.5V, Vo = -7.5V
VIN="OFF"
nA
Vs=10V, Vo= -10V
VIN="OFF"
nA
vo=vs= -7.5V. VIN="ON"
nA
Vo-Vs- -10V, VIN - "ON"
p.A.
VIN=OV
p.A.
VIN=5V
ns

pF

100
100
100
100
100
100
100
100

See switching time test circuit
Vs= -5V,lo=O, f=1MHz
Vo- +5V,ls=O, f-1MHz
Vo-Vs-O, f-1MHz
RL-750,CL-3pF
VIN=5V

p.A.

VIN=OV

ELECTRICAL CHARACTERISTICS
MAXIMUM RESISTANCES (rOS(ON) MAX)

DEVICE
NUMBER
DGM1!l1
DGM182
DGM184
DGM185
DGM187
DGM188
DGM190
OGM191

MILITARY TEMPERATURE
+2SoC
55°C
+ 125°C

INDUSTRIAL
TEMPERATURE
+2SoC
20°C
+8S o C

50
50

50

75

50

50

75

50

50

75

50

50

75

50

50
75
50
75
. 50

75
50
75

75
50
75

75
50
75

75
100
75
100
75
100
75
100

UNITS

, 11

11
11
11
11
11
11
11

CONDITIONS (Note 1)
V+ =1SV, V- = -1SV, VL=SV
VO=
VO=
Vo=
Vo=
Vo=
VO=
VO=
Vo=

-7.5V
-10V
-7.5V
-10V
-7.5V
-10V
-7.5V
-10V

Is= -10mA
VIN="ON"

APPLICATION COMMENT: The charge Injection in these switches is of opposite polarity to that of the standard OG180 family, but con·
siderably smliller.
3·46

~

DGM181·191

O~OIL

PIN CONFIGURATIONS & SWITCHING STATE DIAGRAM
DUAL SPST (DGM181, 182)
Metal Can Package

Flat Package (FD-2)

5'C::::::::=====~

Dual-In-Line Package
14

c.======::J 5,

NC

VL

NC
NC

V+

(OUTLINE DWG TO-100)

SWITCH STATES ARE FOR LOGIC "1" INPUT

o

(OUTLINE DWGS DO, PO)

DUAL DPST (DGM184, 185)
Flat Package

Dual-In-Line Package

.G=======::::J

53

I::::======~

OND

0,

5,

V+

VL

c:::=====::::::J

(OUTLINE DWG FD-2)

SWITCH STATES ARE FOR LOGIC "1" INPUT

i (OUTLINE DWGS DE, PEl

SPDT (DGM187, 188)
Flat Package (FD-2)

Metal Can Package

NC c::======~

VL

Dual-In-Line Package
14

r:;:====~

NC

NC

NC

IN

NC

y+

YL

(OUTLINE DWG TO-100)

c:::======::::r

I::::======~

OND

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL SPDT (DGM190, 191)
Flat Package

5, C::::::::======:;::;;:J-

Dual-In-Line Package
14

53
03

0

0,

0,

5,
IN1

y-

y+

YL

c:::=======:J

(OUTLINE DWG FD-2)

OND

SWITCH STATES ARE FOR LOGIC "1" INPUT

3-47

(OUTLINE DWGS DE, PEl

O~OIl.

DGM181·191
SWITCHING TIME TEST CIRCUIT

=

Switch output waveform shown for Vs constant with logic.
Input waveform as sh?\I\In. Note that Vs may be + or - as per

. switching time test clrc·ult. Va Is the steady state output with
switch on. Feedthrough via gate capacitance may Jesuit In
spikes ~t leading and trailing edge of output .waveform.

. LOGIC INPUT FOR "OFF" TO "ON" CONDITION (DG180/181/182 SHOWN)
LOGIC
INPUT
tr<10ns
tf<10ns

3V

SWITCH
INPUT

Vs

SWITCH
OUTPUT

0

0.9Vo
I

TEST CQNDITIONS

0.1VO
ton

TEST CONDITIONS

toff

TEST CONDITIONS
DGM187/188
V1N "ON" = 2.4V+
V1N "ON"=O.8V
V1N"OFF" = 2.4V+
V1N"OFF" = O.8V

t

FOR SELECTED DEVICES, LO(3IC

"i" INPUT

= 2.0V

3·48

Channel 1
Channer2'
Channel 2.
Channel 1

TEST CONDITIONS
DGM190/191
V1N"ON" = 2.4V+· Channels 1 & 2
VIN"ON'~=O.8V
Channels 3 & 4
V1N"OFF" = 2.4V+ Channels 3 & 4
V1N"OFF" = O.BV Channels 1 & 2

D~D!b

DGM181·191
CHIP TOPOGRAPHIES

CONSULT
FACTORY

DGM188

DGM181/182
{l1x53

DGM191
91x76

DGM185
91x76

NOTE: BACKSIDE OF CHIP IS COMMON TO V+.

3-49

IH181 Series
Low.-Power, High Level
.
Analog Gates

current) from the TTL logic output, element; ,thus the
effective fanout, if one were to drive only solid ,state
switches, approaches millions.

FEATURES
, • Switches 20 Vpp Signals
• Quiescent Current Less than 100 JlA
• Overvoltage Protection to ±25V
• Break-Before-Make Switching toft, 130ns Max, ton
250ns Max.
T2 L, HTL, CMOS, PMOS Compatible
Low rOS (ON) '- 30n
Constr'uction includes CMOS high level driver circuitry
combined with unique "VARAFET" switches.

The 'family of analog gates is guaranteed' to be, "breakbefore-make" switching; The "off" time is faster than the
"on" time. Typical turn-off times are 80 ns and typical
turn-on ti mes are 200 ns.

SCHEMATIC DIAGRAM
(Typical Channel)

GENERAL DESCRIPTION
, The INTERSIL IH181/191 serjes is a low power version of
the standard DG181/191 series. They meet or exceed the
standardDG181/191 series specifications with the following
exceptions:
1.) VINH = 2.4 vol~s minimum.
2.) Break-before-m.ake switching requires ton to' be'250
ns m~ximum.
See also IH5040, IH5140 series.

The actual switching element is a unique new Intersil
design, called the Varafet. The Varafet is a monolithic '
combin~tion of a' varactor J-Fet diode driving a conventional J-Fet. Strobing the solid state switch is accomplished'
by the TTL levels of a "1" being 2.4V or greater; a "0" is
0.8V or lower. The translator input circuitry will draw
virtually no source or sinking current (typical pa of input

MAXIMUM ON RESISTANCES - rDS(ON) MAX'
(V+ = 15V, V- = -15V, VL =5V, IS = 10mA, VINL = O.BV, VINH = 2.4V)
DEVICE NUMBER
Dual SP$T
OualOPST
SPOT
Dual SPOT

IH 181
IH182,
IH 184
.IH 185'
IH 187
IH 188
IH 190
IH 191

MILITARY TEMPERATURE
25·C
125·C
-55"C
30
30
60
75
75
100
30
30
60
150
75
75
30
30
60
75
75
150
30
30
60
,75
75
150

3-50

INDUSTRIAL TEMPERATURE
25·C,
-20·C
a5"c
75
50
50
150
100
100'
75
50
50
100
100
150
50
75
50
100
150
100
5075
50
150
100
100

UNITS

CONDITIONS

n
n
n
n
n
n
n
n

Vo =-7.5V
Vo = -10V
VD =-7.5V
VO=-10V
Vo =-7.5V
VO=-10V
Vo = -7.5V
Vo =-10V

·D~DIl.

IH181 Family
Current (Any Terminal)
Storage Temperature
Operating Temperature
Power Dissipation'

ABSOLUTE MAXIMUM RATINGS,
V+-VV+-VD
VD-VVD-VS
VL-V-

36V
33V
33V
±22V
36V

BV
BV
BV

VL- VIN
VL- GND
VIN - GND
GND - VVR - VIN

30mA
_65°C to 150°C
_55°C to 125°C
450mW

"Device mounted with all leads welded or soldered to PC
board. Derate 6 mW/"C above 75°C

36V
2V

Stresses above those listed under Absolute Maximum Ratings may Cause permanent d~mage to the device. These are stress
ratings only, and functional operation of the device 'It these or any other conditions above those indicated in the operational·
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
.
device reliability.

ELECTRICAL CHARACTERISTICS - IH181 THROUGH IH191
(V+ = 15 V , V- = -15 V VL = 5 V , Unless Notedl

.

PARAMETER

MAX LIMITS INote 1)
DEVICE

Note II)
SWITCH

ISIOFF)

_55°C +2S oC +125°C _20°C +2SoC +8SoC

ALL

1

100

5

100

nA

IH 181
IH 187

IH 184
IH 190

1.

100

5

100

nA

IH 182
IH 188

IH 185
IH 191

1

100

5

100

nA

1

100

5 .100

ALL

TEST CONDITIONS
Vs = 10V, Vo = -10V, V+ = 10V
V- = -20V, VIN = 2.4V
Vs = 7.5V, Vo = -7.5V
V IN ·= 2.4V
Vs - 10\1, Vo = -10V
V IN = 2.4V

nA'

Vs = 10V, Vo = -10V, V+ = 10V
V- = -20V, VIN = 2.4V

IH 181
·IH 187

IH 184
IH 190

1

100

5

100

nA

Vs = 7.5V Vo = -7.5V
V IN = 2.4V

IH 182
IH 188

IH 185
IH 191

1

100

5

100

nA

Vs = 10V Vo = -10V·
V IN =2.4V

IH 181
IH 187

IH 184
IH 190

-2

-200

-10

-200

nA

V O =V S =-7.5V V IN =0.8V

IH 182
10 ION) + IS ION) IH 188
IN IINL
ALL

IH 185
IH 191

·2

-200

-10

-200

nA

VO=VS=-10V VIN=O.BV

1

,.

1

1

1

1

jJA

1

1

1

1

1

1

jJA

V IN =OV
V IN = 5V

IDIOFF)

IINH
DYNAMIC
ton

ALL
ALL

250
130

toll

ALL

Csloffl

;

CD loll)

ALL

COlon) + Cs Ion)
Ofl Isolation
1+

100

1-

100

GROUND

300
150

ns
"S=-5V,I O =0,1=IMHZ

6 typical

pi

VS=-5V,IO-0,I=lMHZ

14 typical

pi

Vo=V!';=O l=lMHZ

pi

RL = lOOn, CL = 3pl

jJA

10

100

100

10

100

100

jJA

100

jJA

100

jJA

10

1+

100

10

100

100

jJA

1-

100

10

100

100

jJA

.,

;

See switching time
test circuit

pi

10
ALL

ns

9 typical

Typ> 50 dB at .10 MHZ

IL

!

UNITS.

IL

10

100

jJA

GROUND

10

100

jJA

Both V IN = OV

BothV IN =5V

APPLICATION HINT (for design only): The minimum signal handling capability of the IH181 through IH191 family is 20V peak to peak for the.7S0 switches and
'15V peak to peak for the 30n switches (refer 10 and IS tests above. Proper switch turn off requires that V- <: VANALOG (-peak) - Vp where Vp .. 7.SV for
30n, swi,tches and Vp" S.OV for 750 swi~ches i.e., A -10V minimum (-peak) analog signal and a"75n switch IVp < 5Vl. requires that V- " -10V -5V "" -15V.

3-51

O~DIL

IH181 Family
SWITCHING TIME TEST CIRCUIT

Switch' output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be .j. or - as per
switching time test circuit.' Vo is tile steady state output with switch on. Feedthrough via gate capacitance may result in spikes
at leading and trailing edge of output waveform.

i f\

lOme"O'

lOGIC

2.4V

-

:~.p~1",-1.2vr=l~===1/~==
O~

II' Ian.

"

IKU

s~~~~7 -- ~~I ~

SW'ITCH 09Vo

~

\

"'-+=dI~F===;=d"lo==

!?UTPUl DIVel:,

0_,

Vo

LOGIC COMPATIBILITY

3

'R~I""I.I~\II<"

ov

1~1.'IIIS,

GND

_1',,"'_

'.',_'

Vs

R~ • :~SIONI

means that one is operating along the zero load current, or
zero 'source current line for the TTL output voltage' vs.
Iload or Isource current. Thus the maximum output ,is
obtained from the TTL gate. Figures 1 and 2 show the
, expected (typical) output of a TIL gate vs. load and source
currents and plotted as a function of temperature and
power supply. '

The IH 181/191 family can be used with almost any logic
family. It has been designed to directly interface with the
popular TTL, HTL, and CMOS families. The fact that the
solid state switch input current approaches zero (specification has 1 IlA maximum for either high or low input states)
50r---~---r---'r---~---r---T----r---,

Vee "'"sov

40
g
"

-t-----if--t-V,N . 0,4V -+--if---i

,3D

j;
0

> 20

'0

o

12

i

'6

ILOAD AND

20

24

2.

20

4,'

32

'as- mA

t

32

2'

ILOAD AND lOS' mA

IH181 FAMIL V
LOAD LINE

IH181 FAMILY
'LOAD LINE

FIGURE 1. CIRCUIT ANALYSIS AND CHARACTERISTICS
OF SERIES 54n4

FIGURE 2.

,r-------.. . -----.,

•!":IV ,

115V

I

r----~----"

.. -

1

I
"

lK~! TO
20K1!

REXT'N {_,'_O.

I

I

I
I

,
1

I
1

1
1
1

I
I

I
1
1

,

'I

'lSVOR

1
1

v'"

~~!T.:.~A.!E__

-

-I

=___-:..J

lOGIC
INPUT

JJv.
.t.

FIGURE 4. FOR INTERFACING WITH HTL OPEN
COLLECTOR LOGIC

FIGURE 3. FOR INTERFACING WITH
TTL 1:0GIC

Note:
When using HTL or CMOS logic, you will note that a Zener
diode has 'been added between the VL supply ("!ormally
plus 5V) and the V+ supply (normally plus 15V). This
zener is not critical and, in fact, any value between 2V and
10V will work fine. No biasing resistor is needed to
establish a curre';t through the zener'. In cases where the
TTL logic level may, go below 2.~V,a pull-up resistor
should be added between the TTL output and the plus 5V
power supply.

FIGURE 5. FOR USE WITH CMOS LOGIC

3-52

IH181 Family

D~DI!,

THEORY OF OPERATION

the "0" state makes no difference; the quiescem current .remains leakage OT FET in the off condition.
'

Voltage Translator or Driver Circuit

The currents previously discussed are dc currents and ,the
obvious result is that' the circuit' power consumption is
going to ~e low. For example, with plus and minus 15V
power supplies, the specified maximum power consumption
is 3 mW.' The typical power consumption will be 30 nW.
When strobing from a particular duty cycle square wave, ac
currents will be drawn and the magnitude o~ these is
dependent upon the _duty cycle and the pulse repetition
rate. Figure 8 shows, typical ac current draw as a function
of pulse repetition rate.

The translator part of the IH181 family takes the low level
strobe input and 'converts'it to plus and minus'15V swing.
These voltage swings are necessary to drive the output
Varafets so' they can switch the maximum analog input
signal. As shown in Figures 6 and 7, this translation is
performed without drawing any power supply quiescent
current. Typical quiescent current is only the ID(off)
leakage of the fet - this is usually in the less than 1 nA,
range. Whether the input strobe logic is in the "1" state or

V+ .15V

V· .,5V

,....,

lOGIC IN

..,

T2LLEVELi±=-~ ~

~IOOO
OFF

2.

2'

~

II:

iil

.
I

V

100

'"o
IN

t--t__+0:..:c.1+15VI

J

+--4_ _-+=O:..!...I-l5V1

10

VV

ffi

~

5
£'

1

/

V
V

ffi

...z
§

V

/
10

100

lk

"Ole

lOOk

LOGIC FREOUENCY@llO%DUTY CYCLE 1Hz!

, FIGURE 8.

POWER S.lIPPLY QUIESCENT
CURRENT VS. LOGIC
FREQUENCY RATE

FROM DRIVER

v-

-15V

~

ORAIN

V--15V
SOURCE

FIGURE 6. DRIVER STATES WITH
T2L ;"" INPUT

FIGURE 7. DRIVER STATES WITH'
T2L',:O" INPUT

FIGURE 9. ,OUTPUT VARAFET

Notice that the polarity of the driver diode is such that it
forms a back-to-back diqde combination with the sourceto-gate or drain-to-gate junctions of theFET. This makes it
impossible to forward bias a source-to-gate junction during
switching. The driver diode is a voltage variable capacitor
whose C (capacity) vs. V (voltage across diode) plot is
much greater than the C vs. V plot for either the,
source-to-gate or drain-to-gate FET junctions. In fact, the
criteria for proper operation of the varafet is that the
integral of the diode's C vs. V plot is at least equal to the
sum of the C vs. V plots for the source-to·gate and
drain-to-gate FET junctions. The integral of C vs. V is
charge O. C = ON and 0 = C XV. Thus the varafet is really
a charge transfer device.

THEORY OF OPERATION (CONTINUED)
Output J-Fet or Varafet
,.

The output J-Fet is, of course, the actual solid state switch.
The translator circuit is ,merely a means to interface the low
level' TTL strobing logic into higher levels to drive the' '
output Fet. 'The varafet is a monolithicially constructed
combination of a' varactor diode in series with the gate of
an til-channel J-fet. The' driver diode (varactcir diode) is
needed to prevent'forward biasing the output Fet durin'g
norm~1 switching aJ>plicatio~s. Figure 9 shows a schematic'
of the complete varafet.
'
3-53

O~OIb

IH181 Family
SWITCHING STATE DIAGRAMS
DUAL SPST

Flat Package

Metal Can Package

IH181/IH182

"

"
D,

'"

Dual-In-Line Package"

"
D,

D,

'.,

'.,
v,

v,
ORDER NUMBERS:
SWITCH STATES ARE
FOR LOGIC "1" INPUT

"

"

ORDER NUMBERS:

ORDER NUMBERS:

IH181MTW

OR

IH181CTW

IH181MFD

OR

IH181CFD

IH181MID

OR'

IH181CJD

IH182MTW

OR

IH182CTW

IH182MFD

OR

IH182CFD

IH182MJD

OR

IH182CJD

(OUTLINE DWG To-l00)

(OUTLINE DWG JD)

(OUTLINE DWG FD-2)
Flat Package

Dual-ln·Line Package*

·DUAL DPST
IHl84f1Hl85

ORDER NUMBERS:

ORDER NUMBERS:
IH184MFD

OR

IH184CFD

IH184MJE

OR

IH184CJE

IH185MFD

OR

IH185CFD

IH185MJE

OR

IH1B5CJE

(OUTLINE DWG JE)

(OUTLINE DWG FD-2)
Flat Package

Metal Can Package

SPOT

Dual-In-Line Package"

IHl87f1H188

D,

s,

ORDER NUMBERS:

ORDER NUMBERS:

ORDER NUMBERS:

IH187MTW

OR

IH187CTW

IH187MFD

OR

IH187CFD

IH187MJD

OR

IH187CJD

IH188MTW

OR

IH188CTW

IH188MFD

OR

IH188CFD

IH188MJD

OR

IH188CJD

(OUTLINE DWG TO-l00)

(OUTLINE DWG JD)

(OUTLINE DWG FD-2)

Flat Package

DUAL SPOT

Dual-In-Line Package"

IH190/IH191

0,
o'c:::IJ-......,..,
" c:::::IJ--l--'

0,

"

'.,

",

ORDER NUMBERS:
OR

IH190CFD

IH190MJE

OR

IH190CJE

IH191MFD

OR

IH191CFD

IH191MJE

OR

IH191CJE'

(OUTLINE DWG FD-2)
"Side

br~ise

ceramic packages special order only_ Consult factory_

ORDER NUMBERS:

IH190MFD

3-54

(OUTLINE DWG JE)

O~OlL

DG200/lH5200
CMOS Dual SPST
Analog Switch••

FEATURES

GENERAL DESCRIPTION

e Switches Greater Than 28Vpp Signals With ± 15V
Supplies
e Quiescent Current Less Than 100~
eBreak-Before-Make Switching toll 100nsec, ton
500nsec Typical
e T2L, DTL, CMOS, PMOS Compatible
e Non-Latching With Supply Tum-Off
e Complete Monolithic Construction
e Industry Standard (DG200) .
e Improved Performance Version (IH5200)

The DG200/lH5200 solid state analog gates are designed using an Improved, high voltage CMOS monolithic technology.
They provide ease-of-use and performance advantages not
previously available from .solld state switches. Destructive
latch-up of solid state analog gates has been eliminated by
INTERSIL's CMOS technology.

SCHEMATIC DIAGRAM (Yz DG200/1H5200)

Key performance advantages of these devices are TIL compatibility, low-power operation (quiescent current less than
100pA), and guaranteed Break-Before-Makeswltching.
The DG200 is completely spec and pin-out compatible with
the industry standard device, while the IH5200 offers
significantly enhanced specifications with respect to ON
and OFF leakage currents, switching times, and supply current.
.

PIN CONFIGURATIONS
CERDIP " EPOXY
DUAL-IN-LINE PACKAGE

METAL CAN PACKAGE

v+ (SUBSTRATE AND CASE)

NC

v+
(SUBSTRATE)

11 HC
D,
TOPYIEW

$,

. (OUTLINE DWG TO·100)
(OUTLINE DWGS JD, PD)

ORDERING INFORMATION
INDUSTRY IMPROVED
STANDARD
SPEC
PART
DEVICE

DG200AA
DG200AK'
DG200AL
DG200BA
DG200BK
DG200BL
DG200CJ

PACKAGE

TEMPERATURE
RANGE

IH5200MlW 1Q..Pin
-55 to
Metal Can
IH5200MJD 14-Pin CERDIP -55 to
IH5200MFD 4-Pin Flat Pak -55 ,to
IH5200llW 1Q..Pln
-25 to
Metal Can
IH5200IJD 14-PlnCERDIP ...:25 to
IH5200IFD 4-Pin Flat Pak -25 to
IH5200CPD 14-Pin. .
Epoxy DIP

: 14

IN, S~$...JF5I='N'
He

+125·C

He

GND

+125·C
+125·C
+85·C

12

+85·C
+85·C

Ys~BSTRATE)
r.j/C·

NC

SWITCH STATES ARE FOR LOGIC

"1." INPUT (POSITIVE LOGIC)

0 to +70·C

(OUTLINE DWG FD-2)

3-55

BJ
.

DG200/lH5200
ABSOLUTE MAXIMUM RATINGS
Current (Any Terminal) . . .. . . . . . . . . . . . . . . . . . .. > 30mA

v+-v- ..................................... <33V
<30V

Storage Temperature .............. -65·C to +150·C

<30V

Operating Temperature ............. -55·Cio +125·C

Vo-Vs ................... ',' . . . . . . . . . . . . . .. < ± 22V

Power Dissipation .......................... 450mW

VIN-GND ... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. <20V

(All Leads Soldered to a P.C. Board.) Derate 6mW/'C Above 75 ·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanentdamage to the d!lvlce. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the speciflca· .
tlons Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DG200
ELECTRICAL CHARACTERISTICS (@25·C, v+ = +15V, v- = -15V)
MIN./MAX. LIMITS

PER CHANNEL

MILITARY

SYMBOL

CHARACTERISTIC

-55'C

liNION)

Input Logic Current

liNIOFF)

Input Logic Current

1
1

rOSlon)

Drain·Source On
Resistance

70

Channel·to·Channel
ROS(on) Match
Min. Analog Signal
Handling Capability

~

rOSlon)
VANALOG

+25'C
1

COMMERCIAUINDUSTRIAL
+125'C O/-25'C .+25·C +70'C/+85'C
1
1
1
1

TEST
UNITS CONDITIONS
p.A

VIN=O.8V

1

1

1

p.A

70

1
100

80

80

100

0

25

25

25

30

30

30

0

VIN =2.4V
•
Is=1mA,
VANALOG = ±10V
Is (EachChannel)=1mA

±14

±14

±14

±14

±14

±14

V

Is-10mA

1

,

1010FF)

Switch OFF Leakage
Current

2

2

100

5

5

100

nA

VANALOG = -14V to
+14V

ISIOFF)

2

2

100

5

5

100

nA

VANALOG = -14V to
+14V

2

2

200

10

10

200

nA

Vo= Vs = -14V to
+14V

ton

SWitch OFF Leakage
Current
Switch ON Leakage
Current
Switch "ON" Time

iOfl

1010N)
+ISION)

1.0

1.0

p's

RL -1 kO, VANALOG
= -10V to +10V
See Fig. A

Switch "OFF" Time

0.5

0.5

p's

RL=1kO, VANALOG
= -10V to +10V
See Fig. A

QIINJ.)
OIRR

Charge Injection

15
54

20
50

mV

See Fig. B

dB

f=1MHz, RL= 1000,
CLs5pF
See Fig. C

IVl

+ Power Supply
Quiescent Current

1000

1000

2000

1000

1000

2000

p.A

VIN =OV or
VIN=5V

IV2

- Power Supply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

1000

1000

2000

'. 1000

1000

2000

p.A

CCRR

Min. Off Isolation
Rejection Ratio

·50

54

3·56

dB

One Channel Off

I

DG200/lH5200
TEST CIRCUITS
Figure B

Figure A

ANAl)OG j~':UT

INPUT

.

3Y

I

(N0?D--l>-_
LOGIC INPUT

1- .

Your

10pF

510

Dyn
~~~~ o--Q--t>- L

DYn o--Q--t>- LOGIC

r

ANAL09 INPUT

h

3Y

Figure C

10,OOOpF

1kH

~YOUT

"::"

Your

I

-=

1'000

IH5200
ELECTRICAL CHARACTERISTICS (@25°C, V +
PER CHANNEL

MILITARY

SYMBOL

CHARACTERISTIC

-55°C

I'NION)
I'NIOFF)
rOS(on)

Input Logic Current
Input Logic Current

1
1
70

rOS(on)

Channel-to·Channel
ROS(on) Match

VANALOG

+125°C O/-25'C
1
1
1
1

+25'C
1
1

+70'C/+85'C
1
1

TEST
UNITS CONDITIONS
p.A
p.A

Y,N =0.8V
Y,N =2.4V

°
°

Is=1mA,
VANALOG = ±10V
Is (Each Channel)=1mA
Is=10mA

70

100

80

80

100

25

25

25

30

30

30

Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current

±14

±14

±14.

±14

±14

±14

V

0.2

0.2

50

1

1

50

nA

VANALOG = -14V to
+14V

lS(oFF)

Switch OFF Leakage
Current

0.2

0.2

50

1

1

50

nA

VANALOG = -14V to
+14V

IOION)
+I SION )

Switch ON Leakage
Current

0.5

0.5

100

1

1

100

nA

Vo=Vs= -14Vto
+14V

ton

Switch "ON" Time

0.7

0.8

p.s

RL = 1kO, VANALOG
= -10V to +10V
See Fig. A

toff

Switch "OFF" Time

0.25

0.4

p.S

O(INJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio

5
54

10

mV

RL = 1kO, VANALOG
= -10V to +10V
See Fig. A
See Fig. B

50

dB

f=1MHz, RL=1000,
CL,,5pF
See Fig. C

IVl

+ Power Supply
Quiescent Current
- Power Supply
Quiescent Current

Y,N =OV or
V,N=5V

IOIOFF)

IV2
CCRR

Drain·Source On
Resistance

+25°C
1
1

= +15V, V - -.= -15V, VREF open)

MINJMAX. LIMITS
COMMERCIAUINDUSTRIAL

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

250

200

150

300

250

200

p.A

10

10

100

10

10

100

p.A

50

54

3-57

dB

One Channel Off

DG2001lH5200
TYPICAL CHARACTERISTICS
va VD and Power
Supply Voltage

I'DS(on) va VD

and
Temperature -

.! (

100

U1

-!i~ 1

1a1ec

10

Ii .m~m.
0

5

~

A-V+.+~IY'V• - v+ ••

10

_:.:

-1' -10 -5

fDS(on)

DI lOOt+t=IA:~Dm;ttl:l

Y-·-IIV

IIIYi+.i+i'lVl

•

CHIP TOPOGRAPHY

10

i.

§:o

-15 -10 -I

11

~-DlWNVOLTAGE(VOI.lIII

__ 11V
tIV, V-. -1IV

c - y+ •• tOV, Y-.-1V¥
D_Y+a."'.Y- __1Y

0

•

~-

ID(CIII) va Temperature·

0

5

,.

15

DRAIN VOLTAIIE CVOLlIII

15(011) or 1D(0I1)
va Temperature·
31

.§il

IIi'"

~I

~.

~~

0.1

eo

......

:!lit

~

..

15 '86

D,

5,

105- 125

NOTE: Backside of chip of commo~ to V+.

T - TEMPERATURE ('C)

APPLICATIOt-.!S

The Function of VREF
Application Hints

YIN
VV+
VREF
Logic Input
Positive Negative Reference
Voltage
Pin
Supply Supply
VINH MIni
Voltage Voltage Connection
VINL Max
(V)
(V)
(V)
+15·

-15

+12

-12

+10

-10

+8'

-8

'Operatlon below ±8V

Vsor
VD
Analog
Voltage
Range

(V)

(V)

. 2.4/0.8

-15 to +15

Open or
1.4V

2.410.8

-12 to +12

1.4V

2.4/0.8

-10 to +10

1.4V

2.4/0.8

-8 to +8

' Open

VREF is an internal connection which allows the user to
establish the logic threshold voltage at which the switch
changes state. The actual threshold voltage Is equal to the
voltage on the VREF pin; VREF Is internally connected for a
1.4V threshold at V+ = +15V. For other· thresholds and/or
supply voltages, VREF may be connected to a voltage source
or resistive divider whose output voltage Is equal to the
desired threshold. The internal impedance of VREF Is 21kO
±30%.·
Additionally, to adjust VREF, a single pullup resistor can be
used from the VREF pin to a positive 'supply voltage to shunt
the upper Internal divider resistor. The equation below
shows the calculation of the shunt resistor for the desired
logic threshold voltage - this calculation Is based on
nominal Internal resistor values, Which are ± 30% In absolute magnitude. The adjusted trip point voltage (VREF)
should be limited to an upper level of 5V to avoid Input logiC
switching transition hysteresis.

Is not recommended.

Logic Inputs
Logic input circuitry protects.the input MOS gate from transients. A series MOS device shuts off when VIN exceeds the
positive power supply; negative transients are clamped to
ground by a diode clamp.

R1 xR2

(~-1).
Vtr

R1-R2

(~-1)
-Vtr

RSHUNT=

Calculation of RsHUNT

The input voltage characteristics have a current spike oc-.
currlng at the tranSition voltage when the logic goes from
VINH to VINL. If a series resistor Is used for additional static
protection It should be limited to less than 4.7kO to ensure
switching with worst case current spikes.

Where

R1 a220kO:

nominal values,

R2a23kO

±30% run-to-run

Example: for V+ = 15V, VTRIP=5V,uslng nominal R1, R2
calculation RSHUNT = 58kO.

3-58

IH200
CMOS Analog Gate
FEATURES

GENERAL DESCRIPTION

• Switches Greater Than20Vpp Signals With ±15V
Supplies
• Quiescent Current Less Than 10~A
• Overvoltage Protection to ±25V
• Bi'eak·Before·Make Switching: IoFF 200 nsec, ioN
400nsec Typical
• T2L, DTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• Complete Monolithic' Construction

ORDERING
'H2OO

The IH200 solid state analog gate Is designed using an
improved, high voltage CMOS monolithic technology. This
improved CMOS technology provides input overvoltage
capability to ± 25 volts without damage to the de.vice, and
destructive latch·up of solid state analog gates has been
eliminated. Early CMOS gates were destroyed when power
supplies were removed With an Input signal present. The
INTERSIL CMOS technology has eliminated this serious
systems problem.
.

IH2~0

INFORMATIO~

Tt

c·.·.

Key performance advantages of the
are TTL compatibility and ultra low-power operation. The quiescent currt:!nt
requirement is less than 101'A. Also designed into the IH200
is guaranteed Break-Before-Make switching. This is
logically accomplished by extending the tON time (400 nsec
TYP.l such that it exceeds tOFF time (200 nsec TYP.l. This.
insures that an ON channel will be turned OFF before an OFF
channel can turn ON. This eliminates the need for external
logic required to avoid channel to channel shorting during
switching.

.PKkage .A='OoPlnTO·'OO
K• 14·Pln CERDIP
L.. ,4-Pln Flat Pack
P 14.f11n Ceramic DIP

=

TemperllUI.Aange
A=MIUlary -55'C TO +,25'C
B=lndual,ll' -20"CTO +85'C

L -_ _ _ _ _ _ _ _ DevicaType

'H200

C

DE

T

,

DE=,ft.Pln Ceramic DIP
tSpeclal Order Only)

PIN CONFIGURATIONS

JE", I&Pin CEROIP

Tamp'fatuI,Range
M_Mllltary
C=CommlllclaIO'Cto .70·C
Device Typa

•

5'1>-+---0"1

Ne

FUNCTIONAL DIAGRAM

y+
12 (SUBSTRATE)

TOP VIEW

OUTLINE DWGS
DD, JD

OUTLINE DWGS
. DE, JE

SWITCH STATES ARE FOR LOGIC
"1" INPUT (POSITIVE LOGIC)

,.

{

'''' =~;;;i;a...Jf~5i= 'N,

Ne

Ne

~~8STRATE)

GND
NC

YL

S2

S,

02

01

v-

Nle

OUTLINE DWG

FD-2

3·59

v + '(SUBSTRATE AND CASE)

OUTLINE DWG .
TO-100

t:I

mI

IH200
ABSOLUTE MAXIMUM RATINGS
V+-V- ..................................... <33V
V+-Vo ....... , ..............•........•.... :. <30V
Vo-V- ....... ; .•............................ <30V
Vo-Vs ......................••.....•......... <±22V
VL-V- .........•............................ < 33V.
VL-VIN ............ ; ...........•....•..•..... <30V
VL-GND .......... ~' .......................... <20V
VIN-GND •......•............................. <:20V

Current (Any Terminal) .........•...... ' ........ <30mA
storage Temperature ... : ........... -65'Cto +150'C
Operating Temperature ... : ......... -55'Cto + 125'C
Power Dissipation .. . . . . . . . . . . . . . . . . . . . . . . . .. 450mW
(All Leads Soldered to a P.C. Board)
Derate 6mW"C Above 70'C
Lead Temperature (Soldering, 10 sec) .... : ..... :.' 300'C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect·
device reliability.

ELECTRICAL CHARACTERISTICS(@25~C, v+ = +15V, V- = -15V, VL= +5V)
'.

PER CHANNEL
SYMBOL CHARACTERISTIC
liN(ON)
liN (OFF)
rOS(ON)

Input Logic Current
Input Logic Current
Drain-Source On
Resistance

rOS(ON)

. Channel to Channel
Ros(ON) Match
VANALOG Min. Analog Signal
Handling Capability
Switch OFF Leakage
IO(OFF)
Current
IO(ON) .
Switch On·Leakage
Current
+IS(ON)
Switch "ON" Time
tON

-5S oC
1
1
75

MIN.!MAX. LIMITS
.MILITARY
COMMERCIAL
+2S oC +12SoC
1
1
1
1
75
100

0

+2S~C

1
1
80

1
1
80

+70°C
1
1
100

25

25

30

30

30

0

±11

±11

±11.

±10

±10

±10

V

1

1

100

5

5

250

nA

2

2

200

10

10

250

+ Power Supply
Quiescent. Current
-Power Supply
Quiescent Current

10

10

100

10

10

100

10

10

100

10

.10

100

p.A.

V+=+15V,V-=
-15 V, VL= +5 V

+5 V Supply
Quiescent Current
Gnd Supply
Quiescent Current
Min. Channel to
..
Channel Cross
Coupling Rejection
.Ratio

10

10

100

10

10

100

p.A

Switch Duty Cycle
<10%

10

10

100.

10

10

100

p.A

1.0

1.0

0.5

0.5

Q(INJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio

15
54

20
50

ILVO
IGND
CCRR

VIN = 0.8 V
VIN = 2.4 V
Is -1mA.
VANALOG = -10 V to
±10 V
Is (Each Channell
= 1 mA
Is -10mA

VANALOG = -10 V to .
+10 V
nA' Vo = Vs = -10 V.to
+10 V
p's
RL ~ 1 kO. VANALOG
~ -10 V to +1.0 V
See Fig. A
p's
RL =.1 kO. VANALOG
.. = -10 V to +10 V
See Fig. A·
mV . See Fig. B
dB
f = 1 MHz,.RL =
1000, CL"S5pF
See Fig. C
p.A

Switch "OFF" Time

I-a

p.A
p.A
0

25

tOFF

I+a

TEST
UNITS CONDITIONS

54

50

"

3-60

dB

One Channel Off

DG201/1H5201
Quad SPST
CMOS Analog Switches

GENERAL DESCRIPTION

FEATURES
• Switches Greater Than 28Vp-p Signals With ± 15V
Supplies
• Quiescent Current Less Than 100~
• Break-Before-Make Switching toff = 100nsec, ton =
Typically 500nsec
• TTL, OTL, CMOS, PMOS Compatible
• Non-Latching With Sl!pply Tum-Off
• Complete Monolithic Construction
• Industry Standard (OG201) ,
• Improved Performance Version IH5201 .

The DG201/1H5201 solid-state analog gates are designed using an Improved, high-voltage CMOS monolithic technology.
They provide ease-of-use and performance advantages not
previously available from solid-state switches_ Destructive
latch-up of solid-state analog gates has been eliminated by
INTERSIL's CMOS tech,nology_
Key performance advantages of these devices are TIL compatibility, low-power operation (quiescent current less than
100pA), and guaranteed break-before-make switching_
The DG201 Is completely spec and pin-out. compatible witli
the Industry standard device, while the IH5201 offers
significantly enhanced speCifications with respect to ON
and OFF leakage currents, switching times, and supply current.

CHIP TOPOGRAPHY

SCHEMATIC DIAGRAM (1/4 DG201/1H5201)

IN3

VREF

v+

IN4

D4

""¥'--"

v-

-.::==~'=

NOTE: BacksIde of chip

DUAL-IN-LINE PACKAGE
IMPROVED
SPEC
DEVICE

DG201AK
DG201BK

IH5201MJE
IH52011JE

DG201CJ

IH5201CPE

PACKAGE
16-Pin CERDIP
16-Pin CERDIP
16-Pin
.Plastic DIP

to V + .

PIN CONFIGURATIONS (Outline dwgs JE, PEl

ORDERING INFORMATION

INDUSTRY
STANDARD
PART

c~mmon

TEMPERATURE
RANGE
-55·C to +125·C
-20·C to +85·C
O·C to +70·C

SWITCH OPEN FOR LOGIC "1" INPUT

3-61

r&l

D~DfL

DG20111H5201
ABSOLUTE MAXIMUM RATINGS
v+-v- ....................................
,v+-Vo .....................................
vo-v- ......................................
Vo-Vs .................................... <
VREF-V- ............................. '......
VREF-VIN ....................................
VREF-GND .................... ; .............
VIN-GND ......... ~ . . . . . . . . . . . . . . . . . . . . . . . . ..

<33V
<30Y
<30V
± 22V
<33V
<30V
<20V
<20V

Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . ..
, Storage Temperature .............. -65'C to
Operating Temperature ............. -55'Cto
Power Dissipation ........... : .. ,...........
Derate 6mW/'C Above 70'C

< 30mA
+150'C
+125'C
450mW

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the speclflca·
tions Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DG201
ELECTRICAL CHARACTERISTICS (@25'C, v+ ,,; +15V, V- = -15V)
PER CHANNEL
SYMBOL

CHARACTERISTIC

hNION)
hNIOFF)
rOS(ON)

lD(oN)
+IS(ON)

Input Logic Current
Input Logic Current
Draln·Source On
Resistance
Channel to Channel
roS(oN) Match
Analog Signal
Handling Capability
Switch OFF Leakage
Current
SWitch OFF Leakage
Current
SWitch On Leakage
Current
"

ton

MINJMAX. LIMITS
COMMERCIAL
MILITARY
-SS'C
+2S"C +12S'C
O'C
+2S"C
+70'C
1
1
1
1
1
1
1
1
1
1
1
• 1
80
100
80
125
100 ,
125

UNITS

"A
"A

°
°

TEST
CONDITIONS
VIN=0.8V
VIN=2.4V
Is=lmA,
VANALOG = ± 10V
Is (Each Channel) =lmA

25

25

25

30

30

30

±14

±14

±14

±14

±14

±14

V

Is-IOmA

1

1

100

5

5

100

nA

VANALOG = -14V to
+14V

1

1

100

5

5

100

nA

2

2

200

5

5

200

nA

VANALOG = -14V to
+14V
Vo=Vs= ±14V

Switch "ON" Time

1.0

I

toff

SWitch "OFF" Time

QIINJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection' Ratio

54

Ii!

+Power Supply
Quiescent Current
- Power Supply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

rOS(ON)
VANALOG
lD(oFF;)
ISIOFF) ,

10
CCRR

1.0

1'5

RL -,1 kO, VANALOG
= -10V to +10V
See Fig. A

0.5

0.5

I'S,

15

20
50

RL = 1kO, VANALOG
= -10V to +10V
See Fig. A
See Fig. B
f=IMH7, RL= 1000,
CLs5pF
See Fig. C

mV
dB

2000

1000

2000

:2000

1000

2000

"A

2000

1000

2000

2000

1000

2000

"A

54

50

3-62

dB

VIN =OVor 5V

One Channel Off

DG20111H5201
TEST CIRCUITS
Figure A

Figure B

ANALJOG

l:':UT

ANALOG INPUT

ov.fL~-r~~~~ --~
1

r

h

3V

ovJ1. ~ J -=
LOGIC

INPUT

Your

'OpF

VPp@'MC

51H

LOGIC INPUT

-=

(NO~_

b

VOUT

'=

VOUT

1'001\

'O.OOOpF

'0"

m

Figure C

iH5201
ELECTRICAL CHARACTERISTICS (@25°C, v+

=+15V, v- =-15V)

MIN./MAX. LIMITS

PER CHANNEL

MILITARY

COMMERCIAL
+ 25'·C
+70·C

SYMBOL

CHARACTERISTIC

-55·C

+25·C

+125·C

O·C

I'N(ON)
hN(OFF)
rOS(ON)

Input logic Current
Input Logic Cu(rent

1

1

1

1

75

1
'100

1

Drain-Source On
Resistance

1
75,

1
1

1

1

100

100

1
125

rOS(ON)

Channel to Channel
roS(oN) Match
Analog Signal
Handling Capability

25

25

25

30

30

30

±14

±14

±14"

±14

±14

0.2

0.2

50

1

0.5

0.5

' 100

1

VANALOG
lD(oFF)/
lS(oFF)
1D(0N)
, +IS(ON)
ton

Switch OFF Leakage
Cumint
'
Switch ON- Leakage
, Current
Switch "ON" Time

toff

Switch '~OFF" Time

Cl(INJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio

Ii!

+ Power Supply
Quiescent Curreht
- Power Supply
Quiescent Current

Ie
CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

0.5

UNITS

TEST
CONDITIONS

p.A
p.A

V(N=0.8V

Il
Il

Is=1mA,
VANALOG = ±10V'
Is (Each Channel)=1mA

±14

V

Is=10mA

1

50

nA

VANALOG = -14V to
.+14V

1

100

nA

Vo=Vs- ±14V

'"s

RL=1kll, VANALOG
= -10V to, +10V
See Fig. A
RL =1 kll, VANALOG
, = -10V to ,-f10V
See Fig. A

0.75

VIN=2.4V

i

0.25

0.3

fLS

5
54

10
50

mV

See Fig. B

dB

f=1MHz, RL=1001l,
CLs5pF '
See Fig. C
V,N=OV to 5V

1000

750

600

1500

1000

1000

p.A

10

10

100

20

20

200

p.A

54

50'

3-63

dB

One Channel Off

DG20111H5201
TYPICAL CHARACTERISTICS
V+=+15V
V-1=-15V
125'C

P.

25' C

po

-55'C

po

0

5

10

A
+tSV, v- =-tSV
+t2V, v- -t2V
+tOV, v- -tOV
+8V, v- = -8V

r-A-V+
B - v+
C-V+
r- 0 - V+

=
=

r-

-t5 -10 -5

15

0

5

10

15

Vo - DRAIN VOLTAGE (VOLTS)

Vo - DRAIN YOLTAGE (VOLTS)

<
.s

""-

C
B

o

o

-15 -10 - 5

~

100

10.lIm!e

...JI-

V

wz
zw
za:
«a:

a5
r

~

c;2
§~
...J

I-"

".

O.l~lnlll

oz·0.01

L...J--1--'--L.-L...1......L-,i--.L....J

25

45

65

85

105

125

45

T - TEMPERATURE ('C)

APPLICATIONS·

85

105

125

The Function of VREF
Application Hints

VIN
V+
VREF
Logic Input
Positive Negative Reference
Voltage
Supply Supply
Pin
VINH Mini
Voltage Voltage Connection
VINL Max
(V)
(V)
(V)
(V)

v-

Vs or
VD
Analog
Voltage
Range
(V)

-15

Open

2.4/0.8

-15to+15

+12

-12

Open or
1.4V

2.4/0.8

-1210 +12

+10

-10

1.4V

2.410.8

-1010+10

+8*

-8

1.4V

2.4/0.8

-810 +8

+15

65

T - TEMPERATURE ('C)

. VREF is an internal connection which allows the user to
establish the logic threshold voltage at which the· switch
changes state. The actual threshold voltage is equal to the
voltage on the VREF pin; VREF Is internally connected for a
1.4V threshold.at VT = +15V. For other thresholds andlor
supply voltages, VREF may be connected to a voltage source
or resistive divider whose output voltage is equal to the
desired threshold. The internal impedance of VREF is 21kO
±30%.
Additionally, to adjust VREF, a single pullup resistor can be
used from the VREF pin to a positive supply voltage to shunt
the upper internal divider resistor. The equation below
shows the calculatlo'n of the shunt resistor for the desired
logic threshold voltage - this calculation is based on<'
nominal internal resistor values, which are ± 30% in absolute magnitude. The adjusted trip point voltage (VREF)
should be limited to an upper level of 5V to avoid input logic
switching transition hysteresis.

*Operatlon below ±8V is not recommended.

Logic Inputs
Logic input circuitry protects the input MaS gate from transients. A,series MaS device shuts off when VIN exceeds the
positive ,power supply; negative transients are clamped t6
ground by a diode clamp.

RSHUNT=

The !nput voltage characteristics have a current spike
occurring at the transition voltage when the logic goes from
VINH to VINL. If a series resistor is used for additional static
protection it should be limited to less than 4.7kO to ensure
switching with worst case current spikes.

Where

V+
)
R1 x R2 ( ·---1
Vtr
R1-R2

(~-1)
Vir

Calculation of RSHUNT
R1 =220kO:

nominal values,

R2 =23kO

±30% run-to-run

Example: for V+ =15V, VTRIP=5V, using nominal R1, R2
calculation RSHUNT = 58kO.

3-64

IH201 /IH202
CMOS Analog Gate
FEATURES

CMOS technology provides input overvoltage capability to
±25 volts without damage to the device and the destruc·
tive latch·up of solid state analog gates has been
eliminated. Early CMOS gates were destroyed when power
supplies were removed with an input signal present. The
INTERSll CMOS technology has eliminated this serious
systems problem.

• Switches Greater Than 20Vp.p Signals With
±15V Supplies
• Quiescent Current less Than 10~
• Overvoltage Protection to ±25V
• Break·Before·Make Switching tOFF 200nsec,
tON 400nsec Typical
• Pl, OTl, OMOS, PMOS Compatible
• Non·latchlng With Supply Turn·Off
• IH201 Four Normally Closed Switches
.• IH202 Four Normally Open Switches
• low leakage Typical < 100pA.

Key performance of the IH201 are TTL compatibility and
ultra low·power operation. The quiescent current require·
ment is less than 10pA. Also designed into the IH201/2 is
guaranteed Break·Before·Make switching. This is logically
accomplished by extending the tON time (400nsec Typical)
such that it exceeds tOFF time (200nsec Typical). This in·
sures that an ON channel will be turned OFF before an
OFF channel can turn ON. This eliminates the need for ex·
ternal logic required to avoid channel·to·channel shorting
during switching.

GENERAL DESCRIPTION
The IH201/2 Solid State Analog Gate is designed using an·
improved, high voltage CMOS technology. This improved

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

(SUB!;tTAATE)

.ORDER NUMBERS:
IH201MDE OR IH201CDE
SWITCH STATES ARE
FOR LOGIC "1" INPUT

ORDER NUMBERS:
IH202MDE OR IH202CDE

ORDERING INFORMATION

IH201

1
M

JE

T.

,
PACKAGE

DE = 16·PIN CERAMIC DIP (Special
JE = 16·PIN CERDIP

TEMPERATURE RANGE
M = MILITARY _55°C TO +125°C
C=COMMERCIAL O°C TO +70°C
'--------DEVICE CHIP TYPE

3·65

Order Only)

If]

Il

D~DIl.

IH201/1H202
MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS /

V+-V- .....................................
V+-Vo ......................................
Vo-V- .................. .'. . . . . . . . . . . . . . . . . ..
Vo-Vs ......... ,. . . . . . . . . ... . . . . . . . . . . . . . . .. <
VL-V- .................. , ...................
VL -Y'N ......................................
VL -GND ....................................
V'N-GND ....................... '.........'. . ..

Current (Any Terminal) ....................... <30mA
Storage Temperature .............. -65·C to +150·C
Operating Temperature .. , ......... -55·C to+125·C
Power Dissipation ..................., ....... 450mW
(All Leads Soldered to a P.C. Board)
Derate 6mW/·C Above 70·C
Lead Temperature (SQldering, 10 sec) ........... 300·C

<33V
<30V
<30V
± 22V
<33V
<30V
<20V
<20V

Stresses above those listed under Absolute Maximum' Ratings may cause permanent damage to the device, These are stress ratings only, and functional
spe~ifications is not Implied. Exposure to absolute maximum rating conditions for e,xtended periods may affect device reliability.
'

operation of the device at these or, any other conditions above ,t.hose indicated in the operational sections of the

ELECTRICAL CHARACTERISTICS (@25·C, V + = +15V, V- = -15V, VL= +5V.)
PER CHANNEL
SYMBOL CHARACTERISTIC
Input Logic Current
IiN(ON)
IiN(OFF)

Input Logic Current

rOS(ON)

Drain-Source On
Resistance

rOS(ON)

IO(ON)
+IS(ON)
tON

Channel to Cl'1annel
Ros(ON) Match
Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current '
Switch On Leakage
Current
Switch "ON" Time

tOFF

Q(INJ.)
OIRR

VANALOG
IO(OFF)

1+0
I-a

Iva
IGNO
CCRR

MIN;/MAX. LIMITS
COMMERCIAL
MILITARY
0
+25°C HO°C
-55°C +25°C +125°C
1
1
1
1
1
1

TEST
UNITS' CONDITIONS
VIN = O.B V (fH201),
p.A
VIN = 2.4V (fH202)
p.A
VIN = 2.4 V (fH201),
VIN = O.BV (fH202)
Is = lmA,
VANALOG = ±10 V

1

1

1

1

1

1

100

100

200

150

150

200

25

25

25

30

30

30

°

±11

±11

±11

±10

±10

±10

V

1

1

200

2

2

250

nA

2

2

200

2

2

250

nA

°

1.0

1.0

p's

Switch "OFF" Time

0.5

0.5

p's

Charge Injection
Min. Off Isolation
Rejection Ratio

15
54

20
50

mV
dB

+ Power Supply
Quiescent Current
-Power Su'pply
Quiescent Current

20

20

100

30

30

20

20

100

30

30

+5 V Supply
QuieSCent Current
Gnd Supply
Quiescent Currerit
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

20

20

100

30

20

20

100

20

54

VANALOG = -;-10 V to
+10 V
Vo = Vs = -10 V to
+10 V
RL -1 kO,VANALOG
=-10 V to +10 V
See Fig. A
RL = 1 kO, VANALOG
= -10 V to +10 V
See Fig. A
See Fig. B
f = 1 MHz, RL =
1000, CL $5pF
See Fig. C

100

p.A

100

p.A

V+= +15 V, V-=
-15 V, VL = +5V

30

100

p.A

Switch Duty Cycle
<10%

20

100

p.A

50

3·66

Is (Each Channell
= 1 mA
Is = 10 rnA

.,.

dB

One Channel Off

D~OIl.

IH201/IH202
TEST CIRCUITS

ANAL)OG :::UT

F-

ANALOG INPUT

3V

ovIL

ovIL
~~~ o-Q-I>- hVOUT
~F

.

-

3V

t=~ r'~

111kn

..

m

Filiure A

2VPP @1MC

51U

LOGIC INPUT

':"":'

(NO~_

':"

l=VOUT
1,000,

.

.

Flllure C

3-67

.

10,OOOpF

Flllure B

J

O~OIb

IH401 /IH401 A
VARAFET Switch
/

FEATURES
• rDS(on)

its capacity is a strong function of the voltage across it. The
driver diode is electrically in series, with the gate of the Nchannel FET and simulates a back-to-back diode' structure;
this structure is needed to prevent forward biasing the sourceto-gate or drain-to-gate junctions of the F ET when used in
switching applications.
'

=25 ohms Typical (IH401)

• lD(off) of 10pA Typical
• Switching Times of 25ns for ton and, 75ns ,
for toft (RL= 1kO)
• Built-In Overvoltage 'Protection to Plus or
Minus 25V
,

Previous applications of Junction FETs required the addition
of diodes, in series with the gate, and then perhaps a gate-tosource referral resistor or a capacitor in parallel with the diode;
there,fore, at least 3 components were ~equired to perform the
switch function. The IH401 does this same job in one component (with a great deal better performance characteristics).

• Charge InJectlono. 3mV Typical hito O.01I'F
, 'Capacllor

III·
81

It-

Chis <1pF Typical
Can 8e Used for Hybrid cons~ructlon

'Like a standard FET, to practically perform a solid state switch
function a translator should be added to drive the diode. This
translator takes ·the T2L levels and con~erts them'to voltages
required to drive the diode/FET system (typically a OV to
-15V translation and a 3V to +15V shift). With ±15V power
supplies, the IH401 will typically switch 18 p _p at any frequency from DC to 20M Hz, with less than 30 ohms rOSlon) .
The IH401A will typically switch 22V p_p with less than 50
ohms rOSlon) .

GENERAL DESCRIPTION
The IH401 is made up of 4 monolithically constructed combinations of a varactor type diode and an N-channel Junction
FET. The FET itself is very similar to the popular 2N4391.
and the driver diode is a specially designed diode, such that

, TOPOGRAPHY

SCHEMATIC/PIN CONFIGURATION
(Outline Dwg JE)
,

1--.----26 ± 2 m i ' - - -....--l1
DRIVE

1

.0037 x ,0037
.0027 .0027

.0035 x .0037
.0025 .0027'

.0035 x .0037
.0025 .0027

ORDERING INFORMATION
CERDIP Package: IH401JE
IH401AJE

3-68

IH401/1H401 A
ABSOLUTE MAXIMUM RATINGS
. V· to v- ..................................... " 35V
V· ........................................... 35V
v- ........................................... 35V
V· to VIN ............... '..........•.......... " 40V

Operating Temperature ......... -55·C to + 125·C
Storage Temperature ........... -65·C to + 150·C
Lead Temperature (Soldering 10 sec) ......... 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above ihose Indicated In the operational sections of the speclflca·
tions is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS AT 25°C (unless otherwise specified)
SYMBOL

CHARACTERISTIC

IH401

CONDITIONS

MIN

rOS(on)

Switch "on" Resistance

vORIVE -15V, VORAINID = 10mA

Vp

Pinch·Off Voltage

10

Switch "off" Current or

TYP

MAX

7.5V

UNIT

20

30

n

6

7.5

V

VORIVE = -15V, VSOURCE = -7.5V,
VORAIN = +7.5V

10

200

' pa

I D(of!)

Switch "off" Leakage at
125°C

Same as Above

0.25

50

na

ISloff)

Switch "off" Current

VORIVE - -15V, VORAIN - -7.5V,
VSOURCE = +7.5V

10

200

pa

IS(off)

Switch "off" Leakage at
125'C

Sar:ne as Above

0.3

50

na

10(on) +
lSI on)

Switch Leakage when
Turned "on"

Vo = Vs = -7.5V,
VORIVE = +15V

0.02

2

na

Vanalog

AC Input Voltage Range
without Distortion

See Figure B

Vinject

Charge Injection Amplitude

See Figure C

10(ofl)

"off" Leakage

Diode Reverse Breakdown
Voltage. This Correlates to

BVdiode

Overvoltage Protection

Gate to Source or Gate to
Drain Reverse Breakdown
Voltage

BVGSS

Maximum Current Switch

1 nA, VOS

10V

4

15

18

V p.p

3

10

mV p . p

Vo = Vs = -V, 10RIVE = 1 /JA;
VORIVE = OV

-30

-45

V

VORIVE = -V, Vo = Vs = OV,
10RIVE = 1 /JA

30

41

V

VORlVE = 15V, liS = OV,
Vo = +10V

45

70

mA

lOSS

can Deliver (Pulsed)

ton

Switch "on" time (Note 1)

See Figure A

25

50

ns

toff

Switch "off" time (Note 1)

See Figure A

75

150

ns

NOTE 1:

Driving waveform must be >100ns rise and fall time.

SIGNAL
±5V

.15V

,

o v - - -__H----~
' - - - - - STROBE INPUT

10%

r-1

L-

-15v--l

+ 1 5 V - - - - . \ - - -........ 90%
-15V----'

_-';::.5V~_ _ _~

'5V

_

90%

STROBE

INPUT

1 ' - - - - +5V SIGNAL

,,,,

-5V SIGNAL

90%

FIGURE A

+15V

oVLI

~ '1

""Ie-~-+t~

-

Vour -

-15V

1.
FIGURE B

3·69

FIGURE C

C"'O.OlpF

IH401/1H401 A
ADDED NOTE:
The IH401A lends itself very well to hybrid construction i.e.; chip
requirement.

ELECTRICAL CHARACTERISTICS AT 25°C (unless otherwise specified)
SYMBOL

CHARACTERISTIC

IH401A

CONDITIONS

UNIT

TYP

MAX

35

50

4

5

V

VDRIVE - -15V, VSOURCE = -10V,
VDRAIN = +10V

10

200

pa

IDloff)

Switch "off" Leakage at
125°C

Same as Above

0.25

50

na

ISloff)

Switch "off" Current

VDRIVE
VSOURCE

10

200

pa

ISloff)

Switch "off" Leakage at
125°C

Same as Above

0.3

50

na

IDlon) +
ISlon)

Turned "on"

VD = Vs = -10V,
VDRIVE = +15V

0.02

2

na

Vanalog

without Distortion

22

Vp.p

3

10

mV p. p

rDSlon)
Vp

Switch "on" Resistance

Pinch·Off Voltage
Switch "off" Current or

IDloff)

"off" Leakage

Switch Leakage when

AC Input Voltage Range

VDRIVE 15V, VDRAIN = -10V,
ID = lOrnA
ID 1 nA,VDS=10V

=

15V, VDRAIN
+10V

20

Charge Injection Amplitude

See Figure C

BVdiode

Diode Reverse Breakdown
Voltage. This Correlates to
Overvoltage Protection

VD = Vs = -V, IDRIVE
VDRIVE = OV

Gate to Source or Gate to
Drain Reverse Breakdown

Voltage
Maximum Current Switch

3

-10V,

See Figure B

Vinject

BVGSS

MIN

=

1 J.LA,

n

-30

-45

V

VDRIVE = -V, VD =VS = OV,
IDRIVE = 1 J.LA

30

41

V

35

55

mA

IDSS

can Deliver. (Pulsed)

VDRIVE = 15V, Vs = OV,
VD = +10V

ton

Switch "on" time INote 1)

See FigureA

25

50

ns

toff

Switch "off" time INote 1)

See Figure A

75

150

ns

NOTE: Driving waveform must be >100ns rise and fall time.

APPLICATIONS
IH401 FAMILY
Although this simple PNP circuit represents a minimum of
components, it requires open collector TTL input and
tloff) IS limited by the collector load resistor (approximately
1.5/ls for lOkrl). I mproved switching speed can be obtained
by increasing the complexity of the translator stage.

In general, the IH401 family can be used in any application
formally using a JFET /isolation diode combination (2N439l
or similar). Like .standard FET circuits, the I H401 requires
a translator for normal analog switch function. The translator is used to boost the TTL input signals to the ±15V
analog supply levels which allow the I H401 to handle ±7.5V
analog signals (or IH401A to handle ±10V analog signals).
A typical simple PNP translator is shown in Figure 1.
-15V

A translator which overcomes the problems of the simple
PNP stage is the Intersil IH6201.· This translator driving an
IH40l varafet produces the following typical features:

ANALOG
SIGNALS

ton time of approx. 200ns } br~ak before make

IN

toff time of approx. SOns
+15V

ovJL

sWitch

TTL compatible strobing levels of

'2.4V

o.4v

SL

ID(on) + IS(on) typically 20pA up to ±10V analog
signals

IOkSl

FROM TTL
OPEN COLLECTOR
LOGIC

ID(off) or IS(off) typically 20pA
+15V

Quiescent current drain of approx. 100nA in either
"on" or "off" case

FIGURE 1
3·70

IH401/1H401 A
APPLICATIONS (Cont.)

*The IH6201 is a dual translator (two independent translators per package) constructed from monolithic CMOS technology.
The schematic of one-half IH6201, driving one-fourth of an IH401, is shown in Figure 2_

v+

I---~I
2.4V

O.4VJL

o.

T~~o"SR1-:;STROBE
INPUT

I

L

I
I
I
I
I
~A~A~E:'..J

+15V

8 "'-1 5v

GND

fJ=+ 15V

-IL
I
I
I
I

I
I

I

I

Ls-1SV

-15V

NOTE: Each translator output has
a e and "0 output. 8 is just the
inverse of 8, i.e., (0 output is
1800 out of phase with respect
to e outputl.

TRANSLATOR

FIGURE 2

A very useful feature of this system is that one-half of an IH6201 and one-half of an IH401 can combine to make a SPDT
switch, or an IH6201 plus an IH401 can make a dual SPDT analog switch. (See 111.)

I. DUAL SPST ANALOG SWITCH

+3V

D V J i - r 2 L2

NOTE: Either switch is turned on when strobe input goes high.

3·71

IH401/1H401 A
APPLICATIONS (Cont.)
II. DPDT ANALOG SWITCH

+3V

ovS'L

T2l1

11---------'-----III. DUAL SPOT

1lmi----:':-II------of·-f-!-<>sw,

0'-'1---0") ----+-+...

SW,

= Bom
= 35m
= 15m
= 20m
= 100m

v+
11

IN

12
'VA (ENABLE)

V-

-8E=~~~p.:sw,

~

SW J

.,...,
~===:::r==+~t:SW,
sw.
IN

10

v.

(ENABLE)
10

v.

12

v-

VAIENABLE}

I ENABLE)

ORDERING INFORMATION
DG426

A

Tt

'''M"

.

L - 14-Pin Flatpak
P,- 14-Pin Ceramic DIP (Special Order Only)
K - 14-Pin CERDIP
Commercial Temperature 'Range
,
(O'C to +70 'C)

'--_ _ _ _ _ _ Optlon
'--_ _ _ _ _ _ _ _ Devlce Type Number

3-73

II

D04261A Family
ABSOLUTE MAXIMUM RATINGS

Storage Temperature
. . . . . . . . . . -65 to +150°C
Operating Temperature .••••.•.••.• -65 to +150°C
Lead Temperature (soldering, 10 sec:) •..• :... 300°C

Analog Signal Voltage (VA - v- or v+ - VA)
28V
Total Supply Voltage (V+ - V-I ...... . . .
32V
~os. Supply Voltag'e to Hef. Voltage (V+ - VR)
18V
Ref. Voltage to Neg. Supply Voltage (VR - V-I
21V
Power Dissipation (Note) .
750 mW
Current (any terminal) . . . . . . . . . . . . . . . 30 mA

NOTE; Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature below 70°C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the speclflca·
tions Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
.

.

.

BJ

)

ELECTRICAL CHARACTERISTICS PER CHANNEL
Applied voltages for all. tests: DG426, DG429, DG433, DG434, DG440, DG44l, (V+,;, +12V, V- = -18V, VR = 0) and DG451,
DG452, DG453, DG454 (V+ = +15V, V- = -15V, VR = 0). Input test condition which guarantees FET switch ON and OFF as
specified is used for output and power supply specifications.
.
' .
SVMBOL
(NOTE)
I
N
P
U
T

ABSOLUTE MAX. LIMIT
CHARACTERISTIC

V,NIONI

Input Voltage-On

V,NIOFFI

Input Voltage-Off

I(NION)

Input Current

I!NIOFFI

Input Leakage Current

'DSION.

TYPE

All Circuits

Drain-Source On Resistance

5

+ ISIONI

'OION)

Source Leakage Current

IDIOFFI

Drain Leakage Current

0
U
T
P
U
T

Drive Leakage Current

ISCOFF)

+ 'SIONI

IOtONI

25·

70·

2.9 min

2.5 min

2.0mi"

1.4

W
I
T
C
H

UNITS
'00 '

1.0

0.8

Valts

V,=-12V

Volts

V,=-12V

150

100

100

pA

V 1N = 2.5V

4

4

10

pA

V tN

DG426/A
DG434/A

80

80

130

n

DG429/A
DG433/A

35

35

50

n

DG440/A
DG441/A

15

15

25

n

DG451/A
DG453/A

20

20

3D

n

DG452/A
DG454/A

100

100

140

n

Vo =aV,l s = 1 mA

DG426/A
DG429/A
DG433/A
DG434/A

Drive Leakage Current
DG440/A
DG441/A

5

160

nA

Vo-Vs=-BV

5

160

nA

Vs =8V.Vo =-8V

5

160

nA

Vo = BV. Vs = -8V

S

160

nA

Vo -Vs -:"'SV

Source Leakage Current

15

500

nA

Vs = 8V.Vo - -8V

Drain Leakage Current

15

500

nA

Vo - 8V. Vs = -8V

Drive Leakage Current

5

100

nA

Vo - Vs - -5.5V

15

300

nA

Vs • S.5V. Vo - -S.5V

+ ISION )

DG4S1/A
DG453/A

IS(OFF)

Source leakage Current

IDIOFFI

Drain Leakage Current

15

300

nA

Vo = 5.SV. Vs = -S.5V

Drive Leakage Current

S

100

nA

Vo

5

100

nA

Vs - 5.5V. Vo = -5.5V

100··

nA

Vo - 5.5V. Vs = -5.5V

+ ISIONI

DG452/A
DG454/A

Source leakage Current

II)(OFFI

Drain leakage Current

5

P

I HONI

Positive Power Supply
Drain Current

3.5

mA

0
W

1210NI

Negative Power Supply
Drain Current

-2.0

mA

IRION)

Reference Power Supply
Drain Current

-1.5

mA

25

pA

-2S

pA

-25

pA

S
'HOFF)

Positive Power Supply
leakage Current

1210FFJ

Negative Power Supply
leakage Current

'RIOFFI

Reference Power Supply
leakage Current

p

I

Vo = 5.5V. Is = 1 mA

ISIOFFI

P
L
Y

O.8V

ISIOFFI

1010NI

U

==

IOIDFFI
1010N)

E
R

TEST CONDITIONS

Vs = -S.SV

One Driver ON. VIN '" 2,5V

All Circuits

,

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test,

3-74

Both Drivers OFF, V1N = O.SV

O~OIb

DG4261A Family
ELECTRiCAL CHARACTERISTICS PER CHANNEL (cont.)
ABSOLUTE MAX. LIMIT
SYMBOL
(NOTE)

o·

Turn-On Time

toN

S

W
I
T
C
H

Turn-Off Time

toFF

I

N
G

Turn-On Time

toN

DG426. DG429
DG433. DG434
DG452. DG454

25·

\
toFF

70·

1.0

~s

See Below

DG426A. DG429A
DG433A. DG434A
DG452A. DG454A

0.5

DG426. DG429 .
DG433. DG434
DG452. DG454

2.0

DG426A. DG429A
DG433A. DG434A
DG452A. DG454A

i.o

DG440. DG441
DG451. DG453

1.5

0.7

~s

~S

See Below

1.3

~S

~S

See Below

DG440A. DG441A
DG45IA. DG453A

Turn-Off Time'

TEST CONDITIONS

UNITS

TYPE

CHARACTERISTIC

.75

DG440. DG441
[)G451. DG453

2.5

DG440A. DG441 A
DG451 A. DG453A

1.25

1.3

fS

~S

See Below
1.8

~S

p

0

ON Drive Power

PON

W
E
R

175

mW

Both Inputs Y'N = 2.5V

1

mW

Both Inputs Y'N '" 1.0V

All Circuits
OFF Driver Power

P OFF

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

SWITCHING TIMES (at 25°C)
DG4511A. 452/A. 453/A. 454/A

DG426/A. 429/A. 433/A. 434fA.
440/A.441/A
PWV~;".
1,

<0.1...

t,

<0 I".

'.

311 .. -_ _ _ _"

PW-s".

2.S11

1. <0,' ""

t,

...
:l:

!;;

:l

...~

1,1--+-----t--r---j

z

;>

o

-25

50

75

o

-25

TEMPERATURE lOCI

25

50

75

TEMPERATURE lOCI

'OS{ON) vs TEMPERATURE

(No~malized to 2SoC Value)

'O{OFF) vs TEMPERATURE

100

t:-

!===OGI52/A,154/A

tJ

~-

--

f?

o

W

N

,..,..V

:::;
«
:;;
a:

o

,.

z

~

~

V

OGI51/A,153/A....,

.E

-25

02550

75

o

-25

TEMPERATURE lOCI

25

50

75

TEMPERATURE lOCI

ALL CIRCUITS

ON SUPPLY CURRENT
vs TEMPERATURE

2.6

';i

g
\;;

2.2

-

~ 1.8

a:

::>

tJ

OFF SUPPLY CURRENT
vs TEMPERATURE

"DS{ON) vs TEMPERATURE

- --

10

1000

';i

.:;

IIIONI

~ 1.0
w

100

a:
a:

::>

10

tJ

>.

12101\11

::. 1.4

!l:

_ OG4521 A, 4541 A

!l:

::>
~ 1.0

o
.6
-25

-

~

0.1

-'

V!

.01

u.

a

IAIONI

!---

o

OG426/A, 429/A, 433/A, 434/A

0,1

25

50

TEMPERATURE lOCI

75

25

50
TEMPERATURE lOCI

3-76

r-

.001

15

25

50
TEMPERATURE lOCI

75

DG439/A, DG442/A - DG446/A,
DG461/A - DG4641A
Drivers with Differentially Driven
N.O. and N.C. 'FET Switches

FEATURES

GENERAL DESCRIPTION

•

Each package contains a monolithic driver with differential
input and 2 or 4 discrete F ET switches. The driver may be
treated as a special purpose differential amplifier which
controls the cond~ction state of the F ET switches. The
differential output of the driver sets the switches in opposition, one pair open and the other pair closed. All switches
may be opened by applying a positive control signal to the
V R terminal.

Each channel complete-interfaces with most integrated logic

•

Low OFF power dissipation,-1mW

•

Switches analog signals up to 16 volts peak-to-peak

•

Low rDS(ON), 15 ohms max on DG445/A and DG446/A

•

Switching times improved 100%-"A" circuits

SCHEMATIC & LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)

SPDT
DG443fA(rDS(ON)
DG444fA(rDS(ON)
DG446fA(rDS(ON)
DG46lfA(rDS(ON)
DG462fA(rDS(ON)

v'

DPDT

"

=
=
=
=

.

son)
35n)
l5n)
20n)
= lOOn)

DG439fA(rDS(ON)
DG442fA(rDS(ON)
DG445fA(rDS(ON)
DG463fA(rDS(ON)
DG464fA(rDS(ON)
I

= 35n)
= Son)
= l5n)
= 20n)
= lOOn)
sw.
3
2
-0

v

,"

10

v.

IN, ~_-+-'-J

v12

v12

ORDERING INFORMATION
DG439

A

L
C

L

L -_ _ _ _ _
L -_ _ _ _ _ _ _

Package

L-14 Pin Flatpak
P-14 Ceramic DIP (Special Order Only)
K-14 Pin CERDIP

Commercial Temperature Range
(O'C to +70 'C)
Option'
Device Type Numbet

D.

S.

Il

DG439/A Family
ABSOLUTE MAXIMUM RATINGS

,Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operailon of the device at these or
any other 'conditions above those Indicated In the operational
sections of the specifications is not Implied. Exposure to
absolute maximum rating conditions' for extended periods may
affect device reliability.

v+-v-:
32V
V+-VR.
16V
Vs - V28V
v+ - VIN1 or VIN2.
.14V
v+ - Vs
28V
VIN1 - VIN2 ..... ±5V
Vs -VD
... ±21V
VIN1 - VR .
±5V
VR - V. . .. 20V
VIN2 - VR .
±5V
Power Clissipation (Note)
.. 750 mW
Current (any terminal)
. . . 30 rnA
Operating Temperature ..... : ....... -55 to +1256 C
Lead Temperature (soldering, 10 sec) ...••..• 300°C
NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature below 70·e. For higher temperature, derate at
rate of 10 mwtC.

ELECTRICAL CHARACTERISTICS

'."

.

'.

Applied voltages for all. tests: DG439/A, DG442/A, DG443/A, DG444/A, DG445/A, DG446/A, (V+ = 12V, V- = -18V,
VR = 0, VIN2 = 2.5V) and DG461A, DG462/A, DG463/A, DG464/A (V+ = 15V, V- =-15V, VR =0, VIN2 = 2.5V), Input
test condition that guarantees FET switch ON or OFF as specified is used for output specfficati6ns,
SYMBOL
(NOTE)
VINIONI

I
N
p
U
T

ABSOLUTE MAX. LlMI~
CHARACTERISTIC

Input Voltage-On

VINIO''''

Input Volt....-Off

IV. - V131

Differentiall

I'N1I0NI

Vol~

TEST CONOITIONS

25"

us"

2.9 min

2.5 min

2.0 min

Vol1~

AI Pm 9 and 13 See Figure 1 and 2. Pg. 4

0.8

Volls

At Pin 9 and 13 See FllP-lre 1 and 2. Pg. 4

0.5 min

Volts

See Note I, Pg. 4

1.4
AIIC,rculu,

Input Currenl

IIN210NI

"NHOFF)

UNITS

-55"

TYPE

0.5 min

1.0

0.5 min

150

100

100

"A

V illil

150

100

100

"A

10

"A

V''''2 - 2.0V
VINl - 2.0V

10

"A

V. fII2 ·'3.0V

Inpul Leakage Currenl

IIN210FF)

OG442/A

80

80

130

II

OG439/A
DG444/A

35

35

50

!I

DG445/A
OG446/A

25

II

OG443/A

15

15

S
W

OG4611A
OG463/A

20

~O

I
T

OG462/A
OG464/A

100

100

rDSION.

C

H

0
U
T

IDIONI

+ ~SIONI

Source Leakage Current

1010FFI

Dr.in L........ Current

1010NI

+ 'SIONI

ISIOFFI

U
T

1010FF.
1010NI

+ ISIONI

1010FFJ

Dr.in L. . . . . Current

P

!I

II

160

nA

160

nA

Vs "'BV. Vo --BV

160

nA

VO "BY. Vs=-BV

I?

160

nA

Vo"'Vs"-BV

500

nA

Vs "BV. Vo·-BV

DG4611A
OG463/A

Vo = BV. Vs "'-BV

Vo"'Vs"-BV

15

500

nA

5

100

nA

Vo - Vs '" -5.SV

15

300

nA

Vs .. 5.5V. Vo

15

300

nA

Vo" 5.5V. Vs" -5.SV
Vo "- Vs .. -S.SV

Drive L_k8g1 Current
OG462/A
DG464/A

100

nA

100

nA

100

. nA

1010FFI

Dr.in LINk... Current

'1I0NI

Positive Pow.er SUpply
Drain Currenl

3.5

mA

'210NI

Negalive Power Supply
Drain Current

-2.0

mA

IAIONI

Reference Power Supply
Drain Current

-1.5

mA

11I0F F1

Positive Power Supply
Leakage Current

25

"A

1210FFI

Negalive Power SUpply
Leakage Current

-25

"A

'.HOFFI

Reference Power Supply
Leakage Current

-25

"A

y

,1 mA

30

Source Leakage Current

R

~

' 140

'SIOFFI

0
W

U

DG44S/A
OG448/A

Drive Leakage Current
Source Leakage !=urrenl

+ ISIONI

OG439/A
OG442/A
OG443/A
DG444/A

Dr.in L........ Current

'SIOFFI

V~ , IOV. Is

Vo " 7.5V. Is " 1 mA

Drive Leek. Current
Source Leakage Currenl

1010NI

E

Drive Leak.ge Current

ISIOFFI

p

P

Dr.in·Source qn R.aistanct

3.0V

z

-S.SV

Vo • 5.SV. Vs '" -5.5V
Vo'" 5.SV.

Vs == -S.5V

V INI = 3V
V IN , = 2V

AIIC,rcuiu.

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

3·78

VIN , "V IN2

~

O.BV

O~OIL

D0439/A Family
ELECTRICAL CHARACTERISTICS PER CHANNEL (cont.)
SYMBOL
INOTEI

~BSOLUTE

CHARACTERISTIC

MAX. LIMIT

-6SoC
OG439.0G442
DG443.0G444

25'

125'

1.0

"'

OG462. DG464
toN

Turn-OnTime
DG439A.DG442A
DG443A.OG444A
DG462A.OG464A

TEST CONOITIQNS

UNITS

TYPE

0.1

0.5

Sl!e Below

"'

OG439,DG442

OG443,DG444
OG462. DG464

S

W

toFF

Turn-Off Time

1
T

C

OG445,DG446

H

1
N

DG439A.OG442A
DG443A, DG444A
OG462A. DG464A
OG461,OG463

toN

"'

1.0

1.3

"'

1.3

"'
"'
"'

1.5

OG445A.DG446A
OG461 A. DG463A

OG445,OG446
OG461.DG463

Turn-OffTime

DG445A.DG446A
OG461 A. OG463A

.15
2.5

1.8

1.25

P

0

PON

ON Driver Power

POFF

OFF Driver Power

W
E
R

See Below

"'

Turn-On Time

G

toFF

2.0

See B,low

See Below

175

mW

Both Inputs VIt" ' 215V

1

mW

Both Inputs V'N

All Circuits

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

SWITCHING TIMES (25°C)
OG439/A, 442/A, 443/A, 444/A, 445/A, 446/A

OG461/A, 462/A, 463/ A, 464/ A
\/,.,

II, .. ,

< 1).1

~I

1. <0.'

~I

t,

t,<01_
to .

0

EO~

'SW 1& !AI

1

V//. 0
0
0

. . fiT

1000
OG4421A.443/A

10

r"4 ~

......

-

.....1

100

I--

DG439/A.444/A

1-1-+DG445/A.446/A

DG445/A.446IA ~ § 3

§ §

1

........

10

A

0

.§

EXCEPT
OG4451A.4461A

r-,

o
-75 -50 -25

0

25 50

75 100 125

1
-75 -50 -25

TEMPERATURE (oCI

0,1
0

25 50 75 100 125

25

45

65

85

105

125

TEMPERATURE 1°C)

TEMPERATURE lOCI

DG461/A, 462/A, 463/A, 464/A
VINI THRESHOLD
vs TEMPERATURE

1000

~

"'«:

......

i

to

·sw

z

:>

OG462/A. 464/A..;;:

.sW 1 &2AREON_

~

,,/. 0

~.fi ~
~ ~7h ~.fi ~

10

1& IAF'EO

~

····fiT

.

IS(OFF) vs TEMPERATURE

ROS(ON) vs TEMPERATURE

100

,-

,-

100

-

ifh if.!

r"4 ~
....,

==

~

OG461/A,463/A

DG461/A.463/A

........

10

e

.E

.-

..

o

-75 -50 -25

0

25 50

75 100 125

TEMPERATURE lOCI

1
-75 -50 -25 0

0G462/A, 464/A

0.1
25 50

75 100 125

TEMPERATURE lOCI

3·80

25

45

65

85

105

TEMPERATURE (OCI

125

MM450/MM550, .MM451/MM551
MM452/MM552, MM455/MM555
MOS·FET Switches

FEATURES

GENERAL DESCRIPTION

•
•

The MM450, and MM550 series each contain p channel
MOS enhancement mode transistors. These devices are
useful in airborne and ground support systems requiring
multiplexing, analog transmission, and numerous signal·
routing applications. The use of low threshold transistors
(VTH = 2 volts) permits operations with large analog input
swings (±10 volts) at low gate voltages (-20 volts).

Large Analog Input-±10V
Low S,upply Voltage- VBULK = +lOV
VGG = -20V
• Typical ON Resistance-V IN = -10V, l50n
VIN = +10V, 75n
• Low Leakage Current-200 pA.@ 25°C
• Input Gate Protection

Each gate input is protected from static charge build-up by
the incorporation of zener diode protective devices con. nected between the gate input and device bulk.

CONNECTION DIAGRAMS
MM450. MM550 Dual

MM451, MM551 Four
Channel Switch

Differential Switch .

MM452, MM552 Four MDS

MM455, MM555 Three MOS

Transistor Package

Transistor Package

"

,,"-+----+__ ;

~_-+_O

,,0-'+--+--i--c'O

,,~o--_-'-'

"0-0_ _ _- - '

---------'Tl

o-l

OUTLINE DWG
TO-100

OUTLINE DWG
TO·l00

OUTLINE DWGS

OUTLINE DWG

JE;FD.-2

TO-lOa

ORDERING INFORMATION

MM

1T
50.

F

,..,~~ ,-'' ;" ".~..

J - 16 Pin CERDIP
H - 10 Pin Metal Can
Device Type

'--_ _ _ _ _ _ Temperature Range
4 - (_55° C to +125° C)
5 - (DOC to 70°C)
'--_ _ _ _ _ _ _ _ Analog Switch

3-81

!:II
i:I

MM450/550, Mr.,451/551, MM452/552, MM45~/555
A.BSOLUTE MAXIMUM RATINGS INote 1)

O~OIL

MM550, MM551, MM552, MM555
Storage Temperature
Lead Tempertature (soldering, 10 sec.)

Gate Voltage (V GG )
+14.5V to -30V
Bulk Voltage'(V euLK )
+14V
Analog Input'IV'IN )
+14V to -20V
Power Dissipatio.n
200mW
Operating Temperature
MM450, MM451, MM452, MM455 -55°C to +125°C

o°C to. 70°C
-65°C to +150°C
300°C

NOTE 1: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board ih ambient'
temperature below 70°C, For higher temperature, derate
at rate of 10 mW/oC for FO package and 6.5 mWrC for
TW package.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated In the operational sections of th'e speclflca·
tlons is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (per channel unless noted)
,
SYMBOL

CHARACTERISTICS

Analog Input Voltage

All

VGS(Thl

Threshold Voltage

All

rOS(ON)

prain-Source On Resistance

All

I GBS

Gate Leakage Current

All

IstoFF)

Drain Leakage Current

Source Leakage Current

Source-Bo,dy Capacitance,

tsB

\

Gate-Body Capacitance

CGB

TYPICAL PERFORMANCE
rOSlon)

YS

8So

1.5

Min
Max
600

200

200

MM450.
MM452.
MM550.
MM552.

MM451
MM455
MM551
MM555

0.2

40

VGS

0,4

40

V

VOG=O
10= jOllA

n

Max

n·

VIN ='-IOV 10= I rnA
VB = 10V
VIN = +10V VGS = -20V

100

Max

nA

VGS = -25V. Vas = Vos = 0

200

Max

nA

Max

nA

Max

nA

Max

nA

pF
pF
pF
pF
pF

Max

Max

Max

100

20

400

100

All

10

MM450. II!IM5S0

14

MM451. MM551

24

MM452. MM552

11

MM455. MM555

11

MM450. MM550

13

MM451. MM551

8

MM452. MM552

9

MM455. MM555

9

pF
pF
pF
pF

All

5

pF

rOSlon) vs VGS

rOSlon)
100,000

V as ,"·,0V
V IN = OV
10 '" 1 mA

TA '" 8SoC

1000

V OB ='-25V
V Ga = VSB == 0

Vs• = -25V
VOB=VGB=O

-

Max
Max
Max
Max

VOB=VGB=VSB=O
t = 1 MHz

Max
Max
Max

z

0

'.
100

Vas'" .tOV
VII'; '" -tOv
to -1 rnA'

1
TA = 85°C
TA. = 2SoC
rT A " _55°C

Z
0

~

.::-~

1000

DRAIN CUR,RENT vs GATE
TO SOURCE VOLTAGE

VGS

S

T A "'-55"c

~

YS

10,000

T A =25°C

'.~1fft1

Max

.

V

CURVE~

10,000

100 • • • •

MAx

3.0
600

CONDITIONS

MIN

12~

Max

5

MM451
MM455
MM551
MM555

Gate-Source Capacitance

CGS

70°

±10

MM450.
MM452.
MM550.
MM552.

Drain-Body Capacitance

COB

UNITS
2So

VIN

IO(OFF)

LIMITS

TYPE

-

").;

>-

"~ 60 H-t-++++-H:'L~
~ 4.0 H-t-++++-HH---l
::>

:

~

-4

-8

-12

-16

-20

100 ~~~~~~~~-"
-16
-17
-18
-19
-20
VGSIV\

VaslV)

3-82

2.0

H-t-++++IL*+-H

O ...........................LJLl-'--'--'
o -1.0 -2.0 -3.0 -4.0 -5,0
VGS - GATE TO SOURCE VOLTAGE {V)

IH500 1/1H5002
i·Channel Driver with
SPST FET Switch
AND Gate Available
GENERAL DESCRIPTION

FEATURES
•
•
•
•
•

Gate Lead Available for Nulling Charge Injection Voltage
Channel Complete-Interfaces With Most Integrated Logic
Low OFF Power Dissipation, -1 mW
LoWrDS(on), 30n Max on IH5001
Switches Analog Signals up to 16 Volts Peak-to-Peak

These switching circuits contain one channel in one package, the channel consisting of a driver circuit controlling a
SPST junction FET switch. The driver interfaces DTL, TTL,
'or RTL logic signals for multiplexing, commutating, and'
DiA converter applications, which permits logic design directly with the switch function. Logic "1" at the input
turns the FET switch ON, and logic "0" turns it OFF. The
gate lead of the FET has been brought out to enable the
application of a referral resistor for nulling offset voltage
due to charge injection.

SCHEMATIC & LOGIC DIAGRAM (Outline Dwg PAl

IH5001 (rOS(on) = 30n)
IH5002 (rOS{on) = 50n.)
v+
2

G

6

S05~----------~-r---r~7D
1N

0--+---;-,
4

v,

1

~ENABle)

3

V,
tENABLE)

v-

ORDERING INFORMATION

IH5001

C

PA

T -1=-,~

a-Pin Plastic DIP

CommercIal Temperature Range
,(0 to +70°C)
Device Type

3-83

3

v-

r&J

O~OI!:.

IH500 111H5002
ABSOLUTE MAXIMUM RATINGS
. Arialog Signal Voltage (VA - V- or V± VA)
Total Supply Voltage (V+ - V-I
Pos. Supply Voltage to Ref. Voltage (V+ - VR)
Ref. Voltage to Neg. Supply Voltage (VR - V-I
Power Dissipation (Note)
,Current (Any Terminal)

Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)

28V
32V

-65 to +150°C
Oto +70°C
300°C

18V
21V

. NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature below 70· C.

500mW
30mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated in the operational sections of the specifications is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Applied voltages for all tests: V+ = +12V, V- = -18V. Input test condition which guarantees FETswltch ON or OFF as
specified Is used lor output and power supply specifications.
SYMBOL
. (NOTE)
I
N
p

u
T

s

VINIONI

Input Voltage,ON

VINIOFFI

Input Voltage-OFF

IINIONI

Input Current

IINIOFFI

I nput Leakage Current
Drain-Source ON
Resistance

VOSIONI

w
I

0
U
T

T
C
H
I

p

IOIONI+ISIONI

Drive Leakage Current

T

ISIOFFI

Source Leakage Current

IOIOFFI

Drain Leakage Current

u

N
G

1+
p

1-

0

w
E
R

p
p
L
y

~,

TYPE

V- = -12V
V- = -12V

100

'I1A

VIN - 2.5V
VIN - 0.8V

4

4

10

I1A

30

50

IH5002

50

50

85

n
n

Vo = 8V. Is = 1 mA

5

160

nA

Vo =VS =-8V

5

160

nA

Vs = 8V, Vo = -8V

5

160

nA

Vo - 8V, Vs = ·8V

Both
Circuits

Positive Power Supply

Drain Current
Negative Power Supply

Drain .Current

3.5

mA

-2.0

mA

-1.5

mA

25

I1A
I1A

Reference Power Supply Drain Current

I+LK

Positive Power Supply
Leakage Current

I- LK

Negative Power Supply
Leakage Current

-25

IRLK

Reference Power Supply Leakage Current

-25

ton

Turn-On Time

Both
Circuits

Driver ON, V IN = 2.5V

Driver OFF, VIN = 0.8V

I1A
~

0.5

Both
Circuits

Turn-Off Time
ON Driver Power

R

POFF

OFF Driver Power

Both
Circuits

VGSSF

Gate Source
Forward Voltage

Both
Circuits

T

100

Volts
Volts

0.8

30

PON

F
E

1.0

TEST CONDITIONS

IH5001

toff

,

UNITS

2.9 min 2.5 min 2.0 min
1.4
Both
Circuits 150

0

w

ABSOLUTE MAX LIMIT
70°
25°
0°

IREF

s

u

CHARACTERISTIC

1.0

0.7

I1s

1.3

See Below

I1S

175

mW

VIN = 2.5V

1

mW

VIN = 1.0V

Volts

1.5

IG = 1.0mA, VOS =0

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

SWITCHING TIMES (at 25°C)

V,.

V.· t8V

PW- 6~f
" C to +125"C)
I - Industrial (-20"C to +8S"C)

Device Type

NOTE:

MiII~ary

temperature range not available In plastic package,

v'

,
0-+--------_., "-+-0"',

0--+-----"]

Y.
l'ItAIUI

"

v-

3-85

"---!--+-osw,

'D~OIL

IH5003/5004
ABSOLUTE MAXIMUM ,RATINGS

NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient tem·
perature below 70·C. For hi!lher temperature. derate at
, ~ate of lPrryWI"C.,

Analog Signal Voltage (VA - V- or V+ - VA)
30V
Tota,l Supply Voltage (V+ - V""')
,
36V
25V
·i>os~ Supply Voltage to Ref. Voltage (V+ - VR)
. Ref. Voltage to Neg. Supply Voltage (VR .,. V-I
22V
, Powe~ DisSipati'~n (Note)
'. '
'
750mW
Current (Any Terminal):
30mA
-65 to +150°C
Storage Temperature
-55 to +125°C
Operating Temperature
300°C
Lead Temperature (Soldering, 10 sec)

Stresses above those listed under" Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional op"E!ration of the device at these or
any other· conditions above those indicated in the operational
sections of the specifications is riot implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

ELECTRICAL CHARACTERISTICS
Applied Voltages for all tests: V+ = +PV, V- = -18V, GND = O. Input test condition which guarantees FET switch ON o'r
OFF as specified is used for output and power supply specifications..
~

. SYMBOL
(NOTEI

"

u
T

s

Input Voltage·ON
Input Voltage.OF:F

Both

Circuits 120

IINIONI

Input' Current
Input Leakage Current

rOSIONI

Drain·Source ON
Resistance

10 lCiNI+ ISIONI

Drive

G

ISIOFFI

Source

1.4

0.1

Current

IREF

Reference Power Sup·
ply Drain Current

I+LK

Positive Power Supply
Leakage Curre~t ,.'

I-LK

Negative Power Supply
Leakage Current

IRLK

ply Li!lIkage Current

tan

Turn·ON Time

toff

Turn·OFF Time

a

PON '

ON Driver Power

E

POFF

OFF Driver Power

R
5

u
~

p

L
y

p

w
R

F

Gate Source

VGSlfl

E
T

Forward Voltage

IlA

VIN = 2.5V

2

IlA

VIN = O.BV

n
n

50

B5

Both
Circuits

Both

Circ~its

Reference Power Sup-

,.
w
.,
c

60

50

Drain Current

E

0.1

IH5004

Drain Current

1-

V- = -12V
V-'= -12V

50

Negative Power Supply

w

Volts

30

Positive Powe'r Supply

1+

60

Both
Circuits

lOa

nA

I

100

nA

.VS = 10V, Vo = -IOV

I

lOa

nA'

Vo

Vo = Vs = -IOV .

3

mA

-I.B

mA

-1.4

mA

25

IlA

-25

IlA

-25

IlA

0.3

0.5

IlS

0.8

1.2

IlS

= )OV, Vs = -II]V

One Driver ON, VIN

See Bel 0)" .
Both Inputs VIN

mW , Both Inputs VIN

1.5

=2.5V

Both Drivers OFF·
VIN = O.BV

'mW

I

Both
Circuits

Vo = IOV,. I~ = I, niA

2

175

Both
Circuits

TEST CONDITIONS

Volts

0.6

30

Current

~eakage

1.0,

IH5003

Drain Leakage Current

1010FFI.' .

p
0

L~akage

'UNITS

2.9 min 2.5 min 2.0 min

IINIOFFI

~ ~

I

ABSOLUTE MAX LIMIT
25·
-55·
125·

VINIOFFI

'8
Z ¥.

TYPE

VINIONI

N

p

CHARACTERISTIC

Volts

= 2.5
= IV

IG = 1.0mA. Vos

=a

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

.,2V

SWITCHING TIMES (at 25°C)
OWV;",_
1"<0.1,,,
10<01""

.
ou,""
.

tlOV'

,..1----,

~.•v

v .. °10'1

ou,""

. v ..

,.

<_lOY

ON MODEL

OFF MODEL

-'"IT'''''
,....."1". . . '
·M..... '
"='

.' ....... .

"='

.•

sou.c._~ ~.

...'~ ....

"='

.

3·86

,

" : , " .

OUT

IH5005 -'IH5007
2·Channel Drivers with
FEATURES
.. Gate Lead Available for Nulling Charge Injection Voltage
SPST FETSwitches
• Expansion Capability Available
• Each Channel Complete-Interfaces With Most Integrated
Gate Available AND
Logic
• Low OFF power dissipation, 1 mW
• Low rOS(ON), 10n Max on IH5005
directly with the switch function. Logic .. ,. .. at the input
turns the FET switch ON, and Logic "0" turns it OFF. The
gate lead of the F ETs has been brought out to enable the
application of a referral resistor for nulling offset voltage
due to charge injection. Driver points are brought out to
provide for the addition of external FETs for expansion
capability.'
.

GENERAL DESCRIPTION
These switching circuits contain two channels in one package, each channel consisting of a driver circuit controlling
a SPST junction FET switch. The driver interfaces DJL,
TTL, or RTL logic signals for multiplexing, commutating,
and 'O/A converter applications, which permits logic design

PIN CONFIGURATIONS

ID

Gl

DRIVER
81

IN3

1

DRIVER

2.

51
D1

V+

N/C

5 '

VREF(ENABLE)

I.

G1
IN3
V-

13
12
11
10

3

N/C
S3
03
DRIVER

v+
VREF(ENABLE)
IN1
G3

9

IN,

7

8

G3

DRIVER

OUTLINE DWG
FD-2

OUTLINE DWG
DD, PD, JD

ORDERING INFORMATION

SCHEMATIC AND LOGIC DIAGRAMS

lHS005

IH5005 (rOS(on) = 10n)
IH5006 (rOS(on) =30n)
I H5007 (rOS(on) = 80n)

L
M

FD

P"k''''

-

DO - 14·Pin Ceramic DIP (Special Order Only)
FD - 14-Pin Flat Pack

PD - 14-Pin Plastic
JD - 14·Pin CERDIP
Temperature Range

v'

M = Military (_55°C to +12SoCI
I = Industrial (_20°C JO +8S oCI
C = Commercial laoc to +70 C)
Q

' - - - - - - Device Type

NOTE: Military temperature range not available
in plastic package.

v'

,

0-+----------<'1 ....-t-<>'w.
6-+------<,,! ....----7--1-<> ..,

"

IENABltl

3-B7

IH5005 -

IH5007

ABSOLUTE MAXIMUM RATINGS

NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient tem-

Analog Signal Voltage (VA - V- or V+ - VA)
30V
Total Supply Voltage (V+ - V-I
,
36V
Pos.Supply Voltage to Ref. Voltage (V+ - VR )
25V
Ref. Voltage to Neg. Supply Voltage (VR - V-I
22V
Power Dissipation (Note)
750mW
Current (Any Terminal)
30mA
Storage Temperature
-65°C to +150°C
-65°C to +12SoC
Operating Temperature
300°C
Lead Temperature (soldering, 10sec.)

perature below 70°C. For higher temperature, derate at
rate of 10 mwtC.

Stre.sses above' those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposu're to absolute maximum rating conditions for extended periods may
affect device reliability.

ELECTRICAL CHARACTERISTICS
Applied Voltages for all tests V+ = +12V, V- '= -18V, VR = O. Input test.condition which guarantees FET switch ON or
OFF as specified is used for output and power supply specifications.
SYMBOL
(NOTE)

CHARACTERISTIC

VINIONI

Input Voltage-ON

f:::l

VINIOFFI

Input Voltage-OFF

~

IINION)

Input Current

IIN(OFFI

Input Leakage Current

Q.

rOSIONI

Drain-Source On Resistance

f:::l

I!::::l
0

J:

u

f-

3:

til

'OIONI + 'SION)

Drive Leakage Current

ISIOFFI

Source Leakage Current

IOIOFFI

Drain Leakage Current

::>

w

;;:

,..A

80

80

150

!1

IHS006

30

30

50

!1

IHSOOS

10

10

20

!1

2

100

nA

Vo=Vs=~10V

1

100

nA

Vs

1

100

nA

Vo

iHS006
IHS007

1+

3

mA

1-

Negative Power Supply
Drain Current

-1.8

rnA

IREF

Drain Current

-1.4

rnA

I+ LK

Positive Power Supply
Leakage Current

25

,..A

I-LK

Negative Power Supply
Leakage Current

-25

,..A

IRLK

Reference Power Supply
Leakage Current

-2S

,..A

IHSOOS

Reference Power Supply

Va = 10V, Is = 1 mA

= IOV, Vo = -10V
= 10V. Vs = -lOY
Vo = Vs = -10V
Vs = IOV. Vo = -lOY
Vo = 10V, Vs =-10V

One Driver ON, Y,N

=2.5V

All Circuits

3:til

toft

Turn·OFF Time

a:

w

PON

ON Driver Power

0

POFF

IH5005
IHS006
IH5007

1.0

1.5

2.S

3.7

0.5

0.8

1.0

1.5

Both Drivers OFF, V IN

=0.8V

,...
,..S
,..S
,..S

See Page 3

=2.5

17S

mW

Both Inputs Y,N

1

mW

Both Inputs Y,N = 1.0

All Circuits

f-

X

Y,N = O.BV

2

IH5007

nA

Turn-ON Time·

<:

Y,N = 2.SV

Positive Power Supply
Drain Current

ton

Q.

,..A

nA

J:

0
Z

V- = -12V

60

1000

f-

w

0.1

Volts

10

Turn-OF F Time

u.

0.1

60

V-=-12V

Volts

0.6

Drain Leakage Current

IOIOFFI

Turn·ON Time

Q.

120

TEST CONDITIONS

2.Umin

nA

ton

;;:

All Circuits

1.0

UNITS

100

toff

u

1.4

125°

1000

0

~

2.9 min 2.5 min

Drive Leakage Current

Source Leakage Current

Q.

(.')

25°

2

+ 'SION)

til

a:

-5So

10

IOIONI
IS(OFF)

>-..J
Q.
Q.

ABSOLUTE MAX. LIMIT

TYPE

OF F Driver Power
Gate Source Forward

VGSSF

Voltage

Vp.f'

at Expansion

All Circuits

1.S

= 1.0mA,Vos =0

Volts

IG

Volts

VIN=~

+3V

Peak·Peak Voltage
All Circuits

30

Outputs

V+=+18V, V-o;-18V,'

w

RL" 100

NOTE: IOFF} and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

3-88

IH5005 -

IH5007

SWITCHING TIMES

(at 2SoC)

OFF MODEL

',.

pw. 51"
t. ":0.' 1"
I, <0 I~. 0 ...

OUTPUT

v.'

IOV

OUTPUT
V. -·IOV

"ON MODEL

TYPICAL CHARACTERISTICS

(per channel)
rDS(ON) vs .
TEMPERATURE
(Normalized to 25°C Value)

V IN THRESHOLD
vs TEMPERATURE
2

=0

VR

~ ~~
OFF

1

v+= +12V
V- = -12V

;;;

t- ~~N.==02.5V

r2

I- V~ = +12V

N

V = -18V

o

-F

W

N
~

""

......
./

1

oz

......

...... V

:;

a:

./

V

.
I

z

o

->

o

-75

-25

25

75

o

-75

125

-25

25

ON SUPPLY CURRENT
vs TEMPERATURE

.sti'i5
a:
a:

:J

10

f- I -

:+
.....-

f-l-

I
I-

f-,- I -

2.2
1.8

r--

1
tZ

w
a:
a:
:J
u

1.4

u

~

:J

'"0z

1.0
0:6
0.2

125

OFF SUPPLY CURRENT
vs TEMPERATURE

ID(OFF) vs TEMPERATURE

2.6

;;

75

TEMPERATURE lOCI

TEMPERATURE rCI

f- I -

>-

~:J

IREF

I--r

".

0.1

'"u.u.
0

J

-75 -50 -25 0

0.1
25 50

75 100 125

TEMPERATl!RE lOCI

/

0.01
25

45

65

85

105

TEMPERATURE lOCI

3-89

125

25

45

65

85

105

TEMPERATURE lOCI

125

IH5005 -

500.7

O~OIL

APPLICATION
Expansion Capability IH5005

Gl340
V 1N3

D1\
~

5,_

I

0,

I

5,_

I

I
53

IN3600

~GI

04

I
I

l

I

I

,

I
I

I

I

VIN

03

I

I

54 _

VIN2

G,

G3

G4

IN;Wo

lOOK
lOOK

~

lOOK·

IN3600

!

,~

lOOK

IN3600
~

~

G,

1

1.r

+lSVlll

4

8

I HSOOS
S

6
~

2

+3V
OV

+3V
OV

Lf

5W,

I

3

I

I
I
13

I

;...._J

IN

5W3

I
I
I
I

I

I

JL

I
I

9
IN

ENABLE)

Fo-t>-----J
10

--:

7

-lSJ12

V 1NB

Gl340

5,

~

-

~
I
I

S3

54

-

/0
I

I

I

I

I

:

IN36oo.

0,

.i

~

....

3-90

G4

lOOK
lOOK

'N3600
IN3600

I
G3

lOOK
...

V 1N7

V 1N6
VIN
(

04
I

I
I
G,

'N3600

~

03

I

I

~G,

0,

l·ooK

IH5009 - IH5024
Virtual Ground
Analog Switches
FEATURES

GENERAL DESCRIPTION

• Switches Analog Signals up to 20 Volts Peak·to·
Peak
• Each Channel Complete - Interfaces with Most
Integrated Logic

The IH5009 series of analog switches were designed to fill
the need for an easy·to·use, inexpensive switch for both in·
dustrial and military applications. Although low cost is a
primary design·objective, performance and versatility have
not been sacrificed.

• Switching Speeds Less than 0.5JLs

Each package contains up to four channels of analog
gating and is designed to eliminate the need for an exter·
. nal driver. The odd numbered devices are designed to be
driven directly from T2L open collector" logic (15 volts)
while the even numbered devices·are driven directly from
low level T2L logic (5 volts). Each channel simulates a
SPDT switch. SPST switch action is obtained by leaving
the diode cathode unconnected; for SPDT action, the
cathode should be grounded (OV). The parts are intended
for high performance multiplexing and commutating
usage. A logic "0" turns the channel ON and a logic "1"
turns the channel OFF.

• ID(OFF) less than 500pA Typical at 70 DC
• Effective rds(ON) - 5n to son
• Commercial and Military Temperature Range
Operation

PIN CONNECTIONS
IH5009 (rOS(ON)S 1000) (OUTLINE)
IH5010 (rOS(ON) S 1500) ot.~g,SJO
14 PIN DIP

0-+----.--'-0,..-1

"-~-+---I--<>"

IH5011 (rOS(ON) S 1000) (OUTLINE)
IH5012 (rOSION) S 1500) \of.~~,SJE
16 PIN DIP

• o-i---,--;-o' "-------+-"'"

2

IH5015 (rOS(ON)S 1000) (OUTLINE)
IH5016 (rOS(ON) S 1500) of.~~,SJE
16 PIN DIP

o--I----t------'-:

1

10

,o-I-~-...j.if

IH5019 (rOS(ON)S 1000)
IH5020 (rOs(oN)s1500)
8 PIN DIP

-t-

~1£J_--+-1;: :.it'--~

nA....-.l·
1

,
[14]

IH5021 (rOS(ON)s1000) (OUTLINE)
OWGS
IH5022 (rOs(oN)s1500)
8 PIN DIP
DO, PA, JD

c'

2

,
115]

IH5023 (rOS(ON) S 1000) (OUTLINE)
IH5024 (rOSION)s1500)
g~~~
8 PIN DIP

::§ TI
(Note: Numbers in brackets refer to CERDIP packages.)

3·91

OWGS
( .OUTLINE)
~O, PE, JE

15

IH5017 (rOS(ON)S 1000) (OUTLINE)
IH5018 (rOS(ON) S 1500) ot.~~,SJO
8 PIN DIP

is

IH5013 (rOs(oN)s1000)
IH5014 (rOs(oN)s1500)
14 PIN DIP

( OUTLINE)
DWGS
DE, PA, JE

--'---11 ;.~

r&J

O~OI!.

IH5009- IH5024

Operating Temperature
5009C Series ............ :' .. .. .. .. .. .. ... O·C to + 70·C
·5009M,Serles ................... :.. - 55·C to + 125·C
Lead Temperature (Soldering, 10sec) ............. 300·C

ABSOLUTE MAXIMUM RATINGS
Positive Analog Signal Voltage .......... , , " . :, , , . " 30V
Negative Analog Slgr:Jal Voltage, , , . ,', , , , , , . , " , " -15V
Diode Current ..... , , , , ...... , , , , , , , , , , , .. , , • , , . , " 10mA
Power Dissipation (Not~). , , , , , , , , , , , , , , , , , , , , , " 500mW
Storage Temperature .: .............. -65·Cto +150·C
Lead Temperature (Soldering, 10 sec) ",.,.'".,'" 300·C

NOTE: Dissipation raling assumes device is mounled with all leads welded
or solde/ed 10 prlnled circuit board In ambienl lemperalure below
75'C. For higher lemperalure, derale al rale 01 5mW/'C.
.

Stresses above those listed under Absolute Maximum' Ratings may cause permanent damage to the device, These are
stress ratings only, and functional operation of the device at these or any other conditions above those Indicated In the
operational sections of the specifications Is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect devlce·rellability.
.

ELECTRICAL CHARACTERISTICS. (per channel)
SPECIFICATION LIMIT
SYMBOL

CHAAACTERlsnc

(Nolel)

TYPE

TEST
CONDITIONS

-SS'C (MI
O'C (C)

(NOlo 2)

MINIMAX

(Nolo 4).

All

"N(ON) .

Input Curtent-ON

"N(OFF)

Input Current-OFF

5V Logic Okts
15V Logic Ckts

+ 12S'C (M)
+10'C (C)

2S'C
• TYP.

.MINIMAX

UNITS

MINIMAX

V,N=OV,ID=2mA

0.1

.01

0.1

100

,.A'

VIN= +4.SVi VA= ±10V

0.2

.0'

0.1

10

nA

..0'

0.2 .

10

'nA

"N(OFF)

,Input. Current·OFF

V'N= +11V, VA= ±10V

0.2

V'NON)

Channel Control Voltage-ON

5V Logic Ckts

See Figure 5, Note 3

.0.5

0.5

0.5

V

V'N(ON)

Channel Control Voltage"()N

15V logic Okts

See Figure 6, Note 3

' 1.5

1.5

1.5

V

V'N(OFF)

Channel Control Voltage-OFF

5V logic ekl.

See Figura 5, Note 3

4.5'

4.5

4.5

V

VI"'IOFF)

Channel Control Voltage·OFF

15V logic Okls

See Figure 8, Note 3

11.0

11.0

11.0

V

IDIOFF)

Leakage Current-OFF

5V Logic Ckl.

ID(OFF)

Lee.kage Current'()FF

15V Logic Ckls

ID(ON)

Leakage Current.()N

5V Logic Ckts

VIN= +4.5V. VA= :t:10V

0.2

.02

0.2

10

nA

VIN =

0.2

.02

0.2

10

nA

1.0

0.30

1.0

1000(M)
200 (C)

nA

0.5

500(MI
100101

nA

+ l1V, VA = :t 10V

V,N=OV,IS=lmA .

IDlON)

L~akage

Current'()N

15V ~oglc Ckts

V,N'=OV,IS=lmA

0.5

IIliON)

Leaka:ge Current·ON

5V Logic Ckls

V,N=OV,ls=2mA

1.0

1.0

10

pA

'-DiON)

Leakage Current.()N

15V Logic Ckl.

Y,N =OV, IS =2mA

2.0

2.0

1000

nA

'DS(ON)

Drain·Source ON·Resistance

'DS(ON)

Drain..source ON· Resistance

5V LOgIC,.Ckts
15V- Logic Ckts

ID = 2mA, Y,N = 0.5V
ID=2mA, VIN='.5V

150
100

0.10

90

150.

3851MI
2401C)
250(M)
160 (C)

60

100
500
500

'(on) 1
I(om

Turn'()N Time

All

See Flgur•• 3 & 4

150

Turn·OFF Time

All

see Flgurel 3

a. 4

300

CT

Cross Talk

0

ns
ns
dB

120

f=100Hz

.AII

0

NOTE 1: (OFF) and (ON) subscript notation relers 10 Ihe ~onductlon slale 01 Ihe FET swllch lor Ihe given lest.
N.OTE2: ReIer lO.Flgure 2 lor!leflnilion 01 lerms.
NOTE 3:

,

v'N(Q,.j and V'NlefF) are leal condltlo.ns guaranleed .by Ih. I.sls 01 respectively

rOS(ONI and 'DlOFF)'

NOTE 4: "5V LOgic CKTS" applies to even·numbered devices.
"15V LOIllc C;KTS" .applles 10 odd-numbered dOYlce•.

.

ORDERING INFORMATION

It
IH50XX

-M

DE
LPACKAGE
.

CHANNELS

LOGIC'
LEVEL

IH5009

4

+15

JD,DD,PD'

IH5010

4

+ 5

JD,DD,PD

IH5011

4

+15

JE,DE,PE

IH5012

4

+ 5

JE,DE,PE

IH5013

3

+15

JD,DD,PD

IH5014

3

+ 5

JD,DD,PD

IH5015

3

+15

JE,.DE,PE

IH5016

3

+ 5

JE,DE,PE

IH5017

2

+15

JD,OO,PA

IH5018

2

+ 5

JD,DD,PA

IH5019

2

+15

JE,DE,PA

IH5020

2

+ 5

JE,DE,PA

.IH5021

1

+15

JD,DD,PA.

IH5022

1

+ 5

JD,DD,PA

IH5023

1

+15

JE,DE,PA

IH5024

1

+' 5

JE,DE,PA

BASIC
PART NUMBER

~ ~~ =_ 1!~:~ ~~~i:g g:~
PE
DD
DE
JD
JE

-

III-PIN PLASTIC DIP
14-PIN CERAMIC DIP (Special Orde' Only)
III-PIN CERAMIC DIP (Special Order Only)
14·PIN CERDIP
16·PIN CERDIP

TEMPERATURE RANGE
M = MILITARY (-55"C 10 +125'C)
C =COMMERCIAL (O"C 10 +10"C)
BASIC PART NUMBER

3·92

NOTE: Mil-Temperature range (_55°C to
ceramic packages only.

PACKAGES

+ 125"C) available

IH5009 -

IH5024

TYPICAL ELECTRICAL CHARACTERISTICS (per channel)

~
z

o
~

10k

a

100

IOION) VS. TEMPERATURE

~ 'l~i's!OI'mAiiili!
i
~

I

a~

IO(OFFI VS. TEMPERATURE

.'~ lOOk

1000

t§ ~A. ~~~~!

~

'°0.5

9

Is

I

I

~~-

1.0
1.5
2.0
2.5
Is - SOUACE CURRENT (mAl

(1)

+5V, ; .,5V

f-

lk

~

100

I

~.

10

25
75
TEMPERATURE I'CI

E

o

~
~O.8
a: 0.6

""

~ -90
;: -80
~' -70

V

V

101\

l -I -

o

'00

10 kn

o

ROSION)

~

5

.JB

I',

~ -100

i-i-

75

OF FREQUENCY

-110

.

1.0

50

CROSSTALK AS A FUNCTION

-120

~12

~

25

T~MPERATURE I'C)

-130

v

~

V

100

CROSSTALK MEASUREMENT CIRCUIT

ROS(ONI VS. TEMPERATURE
(NORMALIZED TO 25 C VALUEI

u 1.4

~

-=-

w

~

~

F==

~

'OK

"~

~

~

D(OF!_~

'~~
J 1=

I"

"

-60

-- .::::::",

-50
-40
-30

25

50

75

100

10

TEMPERATURE ( C)

100

lK

10K

lOOK

1M

.. sv (5010 ETC)
"15V (5009 ETC)

FREQUENCY 1Hz)

DEVICE SCHEMATICS AND PIN CONNECTIONS
FOUR CHANNEL
, ,
IH5009 (rOSION) ,,10011)
IH5010 (rOSION) " 1501l)
14 PIN DIP

THREE CHANNEL

'IH5011 (ros ION),,1001l)
IH5012 (rOS(ON) ,,15011)
16 PIN DIP

IH5013 (rOSION) ,,1001l)
IH5014 (rOS ION),,1501l)
14 PIN DIP

IH5015 (r OSloN),,1001l)
IH5016 (rOSloN),,1501l)
16 PIN DIP

IT
.
TY-:
,R

3~'

t. 6,

,

6~'

15 L
"~9

'1:2 bl0

IT

SINGLE CHANNEL

TWO CHANNEL
IH5017 (rOSION ) "',1001l)
IH5018 (rOS(ON),,1501l)
8 PIN DIP

IH5019 (rOSIO N ) ,,1001l)
IH5020 (rOSION) ,,15011)
8 PIN DIP

3.-u---o'
t. 62
s.-u---o'
t5

IH5021 (rOSIO N) ,,10011)
IH502:! (rOS(ON) " 1501l)
8 PIN DIP

IH5023 (rOS(ON) ,,1001!)
I H5024 (rOS(ON) '" 15011)
8 PIN DIP

'~.

31T'

3

L

3-93

,

5

2

IH5009 -

IH5024

THEORY OF OPERATION
The ,signals seen at the drain of a junction FET type
ana]og switch can be arbitrarily divided into two
categories; those wliich are less than ± 200mV, and
those which are greater than ± 200mV. The former
cat'egory includes all those circuits where switching
is performed at the virtual ground pOint of an op-amp,
and it is primarily towards these applications that
the IH5009 family of circuits is directed.
By limiting the analog signal at the switching pOintto ± 200mV, no external driver is required and the
need for additional power supplies is eliminated.
Devices are av,ailable with both commori drains and
with uncommitted drains.

Clearly, the gain err,or caused by the switch'is dependent on the match between the FETs ratherthan the
absolute value of the FET on:resistance. For the
standard product, all the FETs in a given package are
guaranteed to match within 50!!. Selections dciwn to
511 are available however. Contact factory for details.
Since the absolute va'lue of rOS(ON) is guaranteed only
to be less than'10011 or 15011, a substantial improvement in gain accuracy can be obtained by using.the
comp~nsatingFET. ,

DEFINITION OF TERMS

Those devices which feature common drains have
another FET in addition to the-channel switches. This
FET, which has gate and source connected such that
VGS = 0, is intended to compensate ,for the onresistance of the switch. When placed in series with
.the feedback resistor (Figure 1) the g~in is given by

R,

, 10k!l + rOS(ON) (comperisator)
GAIN

10k!! + ros (switch)

.Figure 2.

NOISE IMMUNITY
The advantage of SPOT switching is high noise immunity when the series elements is OFF. For example,
if a ± 10V analog input is being switched by T2l open
collector logic. the series switch is OFF when the
logic. level is at + 15 volts. At this time .. the diode conducts and holds the source at approximately + 0.7
vol.ts with an AC impedance to ground of 25 ohms.
Thus random noise superimposed on the + 10 volt.
,analog input will n'ot falsely trigger the FET since the
noise voltage will be shunted to ground.
.
When switching a negative voltage. the input further
increases the OFF voltage beyond pinch·off. so there
is no danger of the FET turning on.

Figure 1.' Use of Compensation FET

SWITCHING CHARACTERISTICS
VA ":!;10V

,

+5V

~K
S:','

OV~

G

VIN

I.\N
PW"SIIJ
t r <0.1,us
t,c;'DpF)

"

,

0

V,.

~ 5V

PW'" 51011
t,--~-<>

YOUT

2 10Kn

6 100 Kn:

ANALOG
INPUTS

9

1 Mn

,
1

,

L ___ _

1

~

'

____ ___

7

B

-..GAIN SELECT

~

14

CHARACTERISTICS GAIN

=-~:UT :; RFB
.

":;"

NOTE: Additional apPlication~ in(ormation is given in Applicatlori B~lIetins A003 "Understanding and Applying the Analog
Switch" and A004 "The 5009 Series of Low Cost Analog Switches". See also September '79 Issue of Product.Engineerlng
"Analog Switching" by Paresh Malliar:

3·95

IH5Q25 - IH5038
Positive Signal
Analo~ Switches,
FEATURES

GENERAL DESCRIPTION

•

The IH5025 series of analog switches was designed to fill
the need for an easy-to·use, Inexpensive switch for both in·
dustrial and military applications. AlthOugh low cost Is a
primary design obJective, performance ~nd versatility haVe
not been sacrificed.

Switches up to + 20V into High Impedance
Loads (i.e. Non·lnverting Input of Operational
Amp.)

•
•

IO(OFF)<50pA

•

rOS(ON)< 1500

•

Driven from TTL Open Collector Log,ic

Each package contains up to four channels of analog
gating and is designed to eliminate the need for an exter·
nal driver.

rOS(ON) Match < 500 Channel to Channel
Switching Speeds < 100"s

The entire family Is designed to be driven from TTL open
collector logic (15V), but can be driven from 5V logic if
signal input is less than lV. Alternatively, 20V swltchln,g Is
readily obtainable If TTL supply voltage Is + 25V. Normally,
only positive signals can be switched; however, up to
± 10V can be .handled by the addition of a PNP stage
(Figure 11) or by'capacitor isolation (Figure 10). Each channel is a SPST switch. A logic "0" turns the channel ON and
.
a logic "1" turns the channel OFF.

PIN CONNECTIONS
IH5025 (roS(oN)s1000)
IH5026 (roS(oN)s1500)
14 PIN DIP

IH5027 (rOS(ON) S 1000)
IH5028 (rOS(ON) S 1500)
16 PIN DIP

IH5031 (rOs(oN)s1000)
IH5032 (rOS(ON) S 1.500)
16 PIN'DIP

IH5029 (rOS(ON) S 1000)
IH5030 (rOS(ON)s1500)
14 PIN DIP

3,

11

(2)2

6(12)

(3)3

IH5037 (roS(oN)s1000)
IH5038 (roS(oN)s1500)
8 PIN DIP

IH5035 (rOs(oN)s1000)
IH5036 (rOS(ON) S 1500)
8 PIN DIP

IH5033 (rOS(ON)S 1000)
IH5034 (roS(oN)s1500)
8 PIN DIP.

(3)3

7(15)

·f
3(3)

(2)2

4(4)

"'-_";"'~f- 14.0V

II
II

II

tOFF

tON

+15V

rn

,

I ..
1.
~
OV
I
II

1 Kn

-::-

FET "ON" FOR VIN

FEr

+1.0V~
.

ov..rl·

Figure 1

Figure 2
+5V

vou;OSCOPE

-: - . . J

PROBE (lOX)
10.000 of

lOOn

'.

. VOUT

TO SCOPE PROBE
(lOX)

~

+ ~~(:,"V

+15V

OVn.

1 Kn

10Vpp

•

@

+15V

fn: 1 KC

Figure 4

Figure 3

3·98

II

IH5025 -

O~OIb

IH5038

DEVICE SCHEMATICS

THREE CHANNEL

FOUR CHANNEL
IH5025 (TOSION)" 100!l)
IH5026 (TOSION)" 150!l)
14 PIN DIP

IH5027 (TOSION)" 100!l)
IH5028 (rOSION),,150!l)
16 PIN DIP

'n'
,

11

5

"n"

13

12

4

'if'
'if"
7

11

IH5029 (TOS(ON)" 100!l)
IH5030 (TOS(ON),,150!l)
14 PIN DIP

14

10

12

15

13

10

4(4)

5(11)

IH5035 (TOSION)" 100!l)
IH5036 (TOS(ON),,150!l)
8 PIN DIP

""n"
(2)2

4(4)

""'if'"'
6(12)

8(14)

'n'

'if'
'if"
2

4

7

5

10

12

SINGLE CHANNEL

TWO CHANNEL
IH5033 (TOSION)" 100!l)
IH5034 (ToSION)"i50[!)
8 PIN DIP

IH5031 (TOS(ON)" 100!l)
.IH5032 (TOS(ON)" 150!l)
16 PIN DIP

7(15)

5(13)

Numbers In parentheses Indicate CERAMIC PACKAGE LAYOUT

3-99

IH5037 (TOSION),,100!l)
IH5038 (TOSION),,150[!)
8 PIN DIP

'~n'"
3(3)

1(1)

Iti5025 -

O~OIl.

IH5038

TH-EORY OF. OPERATION
The IH5025 series differs from the IH5009 series In that
they maybe driven by floating outputs. This family Is
generally used when operating I;,tothe-non-Invertlng Input
of an operational amplifier, while the IH5009 series is used
in operations where the output feetls into the Inverting (virtual ground) input.
The IH5025 model is a basis charge area switching device,
in that proper gating action depends upon the capacity vs.
voltage relationship for the diode Junctions. This C vs. V,
when integratec;l, produces total charge Q. It Is Q total which
is switched between the series diode and the gate to
source and gate to drain junctions. The charge area (C vs. V)
for the diode has been chosen to be a minimum of four (4)
times the area of the gate to_source junction, thl!l! providing
adequate saf~ty margins to insure proper switching action.

Il

If normal logical voltage levels of ground to + 15V (open
collector TTL) ar.e used, only signals which are between OV
and +·10V can be switched. The pinch-off range of the
P·Channel FET has been selected between 2,OV and 3.9V;
thus with + 15V at the logical input, and a + 10V signal In·

LOGIC INTERFACE CIRCUITS

put, 1.1V of margin exists for turn·off. When the IH5025Is
used with 5V TTL logiC, a maximum of + tv can be switched.
The gate of eachFET has been brought out so that a
"referral resistor" can be placed between gate and source.
This Is used to minimize charge Injection effects. The connection is shown below:
\

FROM
TTL OUTPUT

For Switching levels> + 10V, the + 15V power supply must
be Increased so that there is a minimum of 5Vof difference
between supply and. signal. For example, to switch + 15V
level, + 20V TTL supply Is required. Up to + 20V levels can
be gated.
.

.

.

When operating with TTL logic it is necessary to use pull-up resistors as shown hi Figures 6 and 7. This ensures the
necessary positive voltages for proper gating action.

r- -- -------,

r--- - - -,

+5V

+15V

I·

I
I

r
I
I

I

I

I

I
I

L!~T~ G~T~

LOGIC
INPUT

I

IVINI

I

I

I
I
I
_ _ _ _ ..J

-

I

_":" I

____ ...J.

I!!!~.!:.G~E

-=

Figure 8. Interfacing with +15V
Open Collector LogiC

Figure 5. Interfacing with +5V Logic

3-100

IH5025 .:.:... IH5038
APPLICATIONS
r - - - -

-----..,+25V
SIGNAL

I
I

I
I

I

INPUT
OVTQ+20V

REXT
I(2Kn

ITO
110Knl

I
I
I

"+3V

.OV.r"l..

+15V

I

I

OVn.

I
I

~O'!..T~~~_::. _ _

-_J

'+15V

OV.n..

Figure 8. Sample and Hold Switch

Figure 7. Multiplexer from
Positive Output
Transducers

Figure 9. Switching up to +20V
Signals with T2L Logic

r---------'+15V
I
I
I
I

I

I"XT
illKO

I

ITO

I
I
I

I'OKOI

.,.,SHIFT.: 1.0 @110Hz

I
I
I

+3V

ov..r-L

+15V

¢SHIFT~O.16 @1100Hz

lJov

'\

I

I
I
ILl5~,..T!k~!S. _____
-= .JI

+3V

+3V

ov ~L---:.:.o:.:v---c;:::J'--,
m.~~___ Jj;u~OGIC
TTL

+15V

OUTPUT

-~ll-1f1IHtI/1f1If/liU-----~8rl"tftlf1"r11~Ir__-~~v OP,AMP,

IfvVv ,

,

V'IV \fv

-sv OUTPUT

NOTE: TO SWITCH t'OVAC (lOVppl: (1) INCREASE :!:5VSUPPLY TO +10V.
(21 INCREASE TTL SUPPLY FROM +,5V TO +25V.

Figure 10. Switching Bipolar Signals with T2L Logic

3-101

UP TO +20V

VOUT .I""]!V

IH5025 -

O~OIL

IH5038

APPLICATIONS (Cent.)

r -- - -----,

RlOAD

+1SV

·+3V

I
I

+3V

T2L
INPUT

OV~~~;UT

I
I
I

OV

JL

GATE
STROBE
2N2907
TYPE OR
2N3638

I
I

ov.JL

+15V~. OUTPUT
T2L

10 Kn

+15V

GATE.

. . STAOBE

-15V

lOV

.

11

ADVANTAGES OVER FIGURE' NO. 10 METHOD
A. DC LEVELS OF UP TO ,lOV CAN BE SWITCHED, AS WELL AS
AC SIGNALS UP TO 100 KC; NO. 10 METHOD SWITCHES ONLY'
AC RANGE OF 10 Hz TO 10 kHz.
B CKT IS NOW BREAK BEFORE MAKE

.

.

~
-lOV

Your
.

DISADVANTAGES;
A. PNP CKT DRAWS 3 rnA, WHEN ON; THUS ADDS 3 rnA X 30V 90 mW
POWER OISS.
B. tON TIME WILL BE CONSIOERABL Y SLOWED DOWN FROM lOa ns
(BEFORE IN FIGURE NO. 10) TO 1 • 21's NOW.

=

Figure 11: Switching Bipolar Signals with T2L Logic (Alternate Method)

--------------------------------------------------------------------~--~------------------------~------~---ETC.

A.
MSB

-=

13
10K

2N3638

TYPE

'3V
5K

OV

T2llNPUT
+15V

T2L
OUTPUT

r------i·,5V

'3V
OV.JL
T2L
INPUT

I

I

I

I

I
I

I
'I

I

I

I

I

I

I LOGIC

-lOV

LADDER
VOL rAGE

jlNPUT

I (VIN)
I
~V....!.T~A~

I
I

-=- _ .:.. -.J

I
1__
l22v..!..T "-E.A:!!..

Figure 12. Using the IH502B as a. Dual SPOT to Drive

-=- _ -=-.J

Ladder Networks for Bipolar Switching (up to ± 10V)

i.e.

o

A
FROM CONTROL
LOGIC

CHANNEL B. C. D. INPUTS - +15V;
CHANNEL A INPUT OV
SIGNAL OUTPUT -

Rf + AA X SIGNAL INPUT

AA
NOTE:
,
WHEN SWITCHING IT) OR H StGNAllNPUTS,A SCHEME
SIMILAR TO FIGURES 10 OR 11 SHOULD BE USED.

Figure 13. Gain Co~trol with High Input Impedance

3-102

IH5040·IH5051 Family
. High Level CMOS
Analog Gates
GENERAL DESCRIPTION.

FEATURES
• -Switches Greater Than 20Vpp Signals With ±]5V Supplies
• Quiescent Current Less Than 1·I.lA
• Overvoltage Protection to ±25V
• Break-Before-Make Switching toff 200 nsec, to~ 300 nsec
Typical
• T2 L, DTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• Low ~DS(on) ::- 35Q
•
•

New DPDT & 4PST Configurations
Complete Monolithic Construction
IH5040 through IH5047

FUNCTIONAL

D~AGRAM
v'

The IH5040 family of solid state analog gates are designed
using an improved, high voltage CMOS monolithic technology. These devices provide ease-of-use and performance advantages not previously available from solid state
switches. This improved CMOS technology provides input
overvoltage capability to ±25 volts without damage to the
deVice, and destructive latch-up of solid state analog gates
has been eliminated. Early CMOS gates were destroyed when
power supplies were removed with an input signal present.
The. IH5040 CMOS technology has eliminated this serious
systems problem.
Key performance advantages of the 5040 series are TTL
compatibility and ultra low-power operation. The quies. cent current requirement is less than 11.lA. Also designed
into the 5040 is guaranteed Break-Before-Make switching,
which is accomplished by extending the ton time (300 nsec
TYP.) sO that it exceeds toft time (200 nsec TYP.). This
.insures that an ON channel will be turned OFF before an
OFF channel can turn ON. This eliminates the need for external logic required to avoid channel to channel shorting
during switching.
Many of the 5040 series improve upon and are pin-for-pin
and electrical replacements for other solid state switches.

FUNCTIONAL .DESCRIPTION

7

v-

FIGURE 1. TYPICAL DRIVER, GATE -IH5042

INTERSIL
PART NO.
IHS040
IHS041
IHS042
IHS043
IHS044
IHS04S
IHS046
IHS047
IHS048 Dual
. IHS049 Dual
IHSOSO
IHS051 Dual

TYPE
SPST
Dual SPST
SPOT
Dual ~PDT
DPST
Dual .OPST
DPDT
4PST
SPST
DPST
SPOT
SPOT

rOS(on)
7S11
7S11
7S11
7S11
7S11
7S11
7S11
7S11
3S11
3S11
3S11
3S11

PIN/FUNCTIONAL
EQUIVALENT
(Note 1)

DG 188AA/BA
DG 191 AP/BP
DG 18SAP/BP

DG 184AP/BP
DG 187AA/BA
DG 190AP/BP

ORDERING-INFORMATION
IH5040 M

NOTE 1. See Switching State diagrams for applicable package
equivalency.

JE
Package

[

Pin and functional equivalent monolithic versions of the DG181,
DG182, OG187 and OG188 are available.· See data sheet for
this and also IH181 to IH19l ..

DE - 16·Pin Ceramic DIP (Special Order Only)
FE - 16·Pin Flatpak
JE - 16·Pin CEROIP
.

.

PE - 16-Pin Plastic DIP

.

TW- TO-99 Metal Cen (lH?04112.IH5044.
IH5048. IH5050 Onlv)

Temperature Range
.

M _ Military _55°C to +12SoC
C - Commercial oOe to +70°C
Basic Part Number

3-103

IH5040·IH5051 Family

.D~I!:,

ABSOLUTE MAXIMUM RATINGS
Curre'nt (Any Terminal) ..... .

. <30mA

Storage Temperlj.ture ..

-66°C to +150°C

Operating Temperature

_55°C to +125°C

Power Dissipation ... ' ...

V+-V-,

<33V

V+-VD

<30V

VD-V-

<30V
<±22V

VD-VS
VL-V-

....... 450mW

(All Leads Soldered, to a P.C. Board) ,
o'erate 6mW/oC Above 70°C

VL-VIN

<33V
<30V

<20V
VL-GND
. Lead Temperature (Soldering, 10 sec) .
VIN-GND
<20V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These, are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in,the operational
sections of the specifications is not implied. ,Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
'
'

EL,ECTRICAL CHARACTERISTICS

Ii]

(@25°C, v+'= +15 V, V- = -15 V,VL = +5 V)
MIN./MAX. LIMITS

~ER CHANNEL '

MILITARY
CHARACTERISTIC

·56'C

"NION)

Input 'Logic C~rrent

1

"NIOFF)

Input Logic Current

rOS(on)

Drain-SouTce On

SYMBOL

75135)

+25°C

75135)

COMMERCIAL
+125"C

150160)

+25"C

80145)

80145)

+70"C

130145)

UNITS

VIN .. 2.4 V Note 1

"A'

YIN" o.~ V Note ,

1I

Resist 8 l"!ce

25115)

VANALOG

Min. AnalogSignal
Handling Capability

'OIOFF)

Switch OFF

25115)

25115)

30115)

:tll1:tl01

tl1(tl0)

t"1~10)

itO(:ttO)

1111

1111

loofiDOl

515)

5151

2(2)

2121

200{2001

10(101

lOIlO}

, 30115)

30115)

1I

(lH5048thru IH50511

+lOhtO)

V

IS" 10 rnA OH5048 thru IH50511

'S lEach Channell "' 1 mA,

Leaka9~

tl0(!10)

. 100(100)

nA

1001200)

nA

Current
'OION)
+ISION)

ton
toff

Switch On Leakage

AL" 1 kH, VANALOG'" -10 V
to110 V See Fig. A

Switch "OFF" 1:ime

250(150)

250(150)

15110)

20 (lOI.

A L ;; 1 kU. VANALOG'" -10 V
to +10 V See FIg, A
IIH5048 thru IH50511
See Fig. 8
{lH5048 thru IH5~511
f'" 1 MHZ",R L .. lOOH. C L ,.; 5 pF
See Fig. C
..

OIRR

Min. Off Isolation
Aejectibn Ratio

IGND
CCRR

IS -10 V to + 10 V
IlH5048 thru IH50511

50013001

Charge Injection

)-LQ

VO" Vs

500(250)

QIINJ,)

)-0

V ANALOG c. -10 V to +10 V
(lH5048thru IH5051'

Current
Swi tch "QN" Time

,

,1+0

(IHS048 Thru IHS0511IS;; lmA.
V ANALOG "'·10 V to +10 V

Channel to Channel
ROSION) Match

4rOS(ONI

TEST CONDITIONS

"A

54
I'

+ Power. Supply

Ouiescllnt Current
- Power Supply
Quiescent Current
+5 V SupplV
Quiescent Current
Gnd Supplv
Quiescent Current

dB

10

10

10

100

"A

10

10

10

100

"A

10

10

10

100

"A

10

10

10

100

"A

54

Min. Channel to
Channel Cross

mV

50

50

dB

·V+ '" +15 V. V- =-15 V. V L " +5 V
V L = +5 V
SWItch Duty Cvcle ... 10%

One Channel Off; Any Other
Channel·Switches as per Fig. E

Coupli~g R~iection

Ratio

TEST CIRCUITS
FIG. B

FIG. A
_

n

T'L

LOGIC
INPUT

,FIG. C

ANALOG INPUT
'lOV

~)

h

,"'I>'J

n

T'L

LOGIC
INPUT

VOUT

-="n

NOTE 1: Some channels are tarned on by high "'" logic inputs and other channels are turned on by low,"ti" inputs; however O.SV to 2.4V
describes the min. range for switching properly. Refer to logic diagrams to see absolute value of logic input required to produce
"ON" or "OFF", state.

3·104

IH5040·IH5051 Family

n~nlL

TYPICAL ELECTRICAL CHARACTERISTICS (Per Channel)
100

160

1- r-

--

80

I

Monolithic
Hybrid

-

140

+12~·C
+2S·C

S

I-- I--

~

J5 CI;::;;:f-"

=ll"c

-10 -5 -2.5

a

@j:

20

15V SUPPLIES

5

7.5 -75

I - I--

10

~

,,~v

-

l-

t-= F

-10 -75

-- -----:l-~lV
-5 -2.5

0

CROSS COUPLING
REJECTION vs FREQUENCY

2.5

5

7.5

25

20r--r~~~-i~T--t~t--j

15r--r~~1--i~t--t~t--j

10~::t:::EJ:TI

10

-10 -7.5 -5 -2.5

r-----H1'
o+-D-t>---

rj:
I

'

, II

r-c...::No-l-+-+-+-+-

aol-......j~~

ill

~

I

:

I

I

I

-=-

...

VOUT

lOOn

-=-

I
40
r2L LEVELS

~~~+.-~---.~

20

..IL ~:
SNITCHED

CHANNEL

200QmVpp

ceRR '" 20lQG - - - -

Your (mVpp)

10

100

Ik

10k

lOOk.

I'\,_t-....

I

~~1J

loon

1M

FIGURE E

FREQUENCY (Hz)

OFF ISOLATION vs FREQUENCY

~ --80

E '-60

OfF STATE

9
:

40
20

DEPENDS ON PART

~

,t

j

"

i I

I OIAR "20LOG
1Hz

10Hz

100Hz

Ii<.

10k

lOOk

1M

FIGURE F

POWER SUPPLY QUIESCENT CURRENT
VS LOGIC FREQUENCY RATE
~ 1000

~
100

~

0
~

;:

'"z

10

~

~

5
.9
10

100

v----~

,

Your (mVpp!
2000mVpp

FREOUENCY (Hz)

iii

~

--v- -

F'

I'

f " ' . 1 1 , '. ,-,-

lk

10k

lOOk

LOGIC FREOUENCY@llO%DUTY CYCLE (Hz)

FIGURE G

3-105

a

2.5,

VANALOG (V)

I

OFF
CHANNEL

~

a

I

FIGURE 0

~

i

10-

VANALOG (V)

VANALOG (VI

'00

30
o

>
.§.

.... t----'

!15V

40

:;;-~'mA - - -

2.5

"bv

60

+'~5°C

+2S·C

0

80

(i

____
""- ------ --------

o _

Monolithic

1= ~HVbridl

100

o

0

I - f--

120

10- I--

60

CHARGE INJECTION vs V ANALOG
(SEE FIG. B) C L = 10,OOOpF

rDS(on) vs
POWER SUPPLY VOLTAGE

rDS(on) vs VANALOG SIGNAL

lDO!!

Your

5

7.5

10

IH5040-1115051 .Family
FOR INTERFACING WITH T2L OPEN COLLECTOR LOGIC.

j------:----, +15V
1

1
1
1
1
T2Lr-L
LOGIC

+15V

TYP. EXAMPLE FOR +ISV CASE SHOWN

FOR USE WITH CMOS LOGIC.

Jl~

,----;---;--:--,
1
1

~ND

1
•

v+

{

1
1
1

GNO

IN

15V> v+ ';;. 6V
'ov ;;. v- ;>:-15V

LOGIC INTERFACING.
'5V

IN

1
1
1

1

-I
L::::''2.L.:'~

-::-

1

-::-·1

____ -.J

f

,·5V VL

•

+

10k!!

\

3·106

•

V t15V OR +Vee [V, TERMINAlI

O~OI!:.

IH5040·IH5051 Family
THEORY OF OPERATION

A. FLOATING BODY CMOS STRUCTURE

-15V

In a conventional C·MOS structure, the body of the "n"
channel device is tied to the negative supply, thus forming
a reverse biased diode between the drain/source and the
body (Fig. J). Under certain conditions this diode can
become forward biased; for example, if the supplies areoff
(at ground) and a negative input is applied to the drain.
This can have serious consequences for two reasons. Firstly,
the. diode has no current limiting and if excessive current
flows, the circuit may be permanently damaged. Secondly,
this diode forms part of a parasitic SCR in the conventional
C·MOS structure. Forward biasing the diode causes the
SCR to turn on, giving rise to a "Iatch·up" condition.
Intersil's improved C·MOS process incorporates an addi·
tional diode in series with the' body (Fig. K) .. The 'cathode
of this diode is then tied to .V+, thus effectively floating
the body. Tne inclusion of this diode not only blocks the
excessive current path, but also prevents the SCR from
turning on.

P MATERIAL
ANALOG
SIGNAL

,----0

0-------,

INPUT

VOUT

FIGURE J

I

t15V
IV')

DI
FLOATING BODY

B. OVERVOLTAGE PROTECTION

ANALOG
SIGNAL

0------,

INPUT

The floating body construction inherently provides over·
voltage protection .. In the conventional C'MOS process, the
body of all N:channel FETs is tied to the most negative
power supply and the body of  ±15V, a forward bias condition exists between
drain and body of the MOSFET. For example, in Fig. J if
the analog signal input is more negative than -15V, the
drain to body of the N·channel FET is forward biased and
destruction of the device can result. Now by floating the
body, using diode 01, the drain to body of the MOSFET is
still forward biased, but 01 is reversed biased so no current
flows (up to the breakdown of 01 which is;;;' 40V). Thus,
negative excursions of the analog signal can go up to a
maximum of -25V. Whe'n the signal goes positive (;;;. +15V,
01 is forward biased, but now the drain to body junction
is reversed for the N·channel FET; this allows the signal to
go to a maximum of +25V with no appreciable current
flow. While the explanation above has been restricted to
N·channel devices, the same applies to P·channel FETs and
the construction is as shown in Fig. L. Fig. L describes an
output stage showing the paralleling of an Nand P channel
to linearize the rDS(ON) with signal input. The presence
o~ diodes 01 and 02 effectively floats the bodies and
provides over voltage protection to a maximum of ±25V.

...-----0

Your

FIGURE K

v+

ANALOG

51 GNA L
IN

, - - _ - 0 Your

0--'-',----,

v+

FIGURE L

3·107

IH5040·IH5051 Family

O~OI!"

APPLICATIONS
IMPROVED SAMPLE & HOLD
USING IHS043

OUTPUT

ANALOG
INPUT

+3V"

IH5043

all ..

> 5AMPL E MODE

> HOLD MODE

USING THE CMOS SWITCH TO DRIVE
AN R/2R LADDER NETWORK (2 LEGS)

..JL
T2L

LOGIC
STROBE

EXAMPLE: If -V ANALOG = -10VDC and +V ANALOG = +10VDC
then Ladder Legs are switched between !10VDC, depending upon state

..JL
r2L

of Logic Strobe.

LOGIC

STROBE

2'

DIGITALLY TUNED
LOW POWER ACTIVE FILTER
100kll

Constant gain, constant Q, variable frequency filter which

provides simultaneous Lowpass, Bandpass, and Highpass
outputs. With the component values shown, center frequency
will be 235Hz and 23.5Hz for high and low logic inputs
respectively. Q = 100, and Gain"= 100.
fn

1
= Center Frequency = - -

21TRC

3·108

IH5040·IH5051 Family

o~nlL

SWITCHING STATE DIAGRAMS
(OUTLINE DWG
FE-2)

SWITCH STATES
ARE. FOR LOGIC "1" INPUT

(OUTLINE DWGS
DE, JE, PEl

v'

VL

"

SPST
IHS040 ('OS(on) < 7S0)
I
I
I

"

I
I
I

_J

J

"

GND

v-

OND

OUALSPST
IHS041 ('OS(on) < 7S0)

v'

VL
VL

v'

s,

D,

0,

S,

,",

SI

S,

s,

0,

OND

"

GND

"

"

"

v'

LN,
LN,

LN,

'",
S,

SPOT
IHS042('OS(on) < 7S0)

"

"

I
_J

,", "

(OUTLINE DWG TO-l00)

v'

VL

(DGl88 EQUIVALENTl

v'

",

"

s,

0,

S,

D,

s,

0,

s,

0,

v'

S,

0,

5,

0,

GND
OND

(DG191 EQUIVALENT)
DUAL SPOT
IHS043 ('OS(on) < 7S0)

"

"

S,

0,
0,

s,

s,

D,

S,

OJ

LN,

'N,
'N,
S,
S,

OPST
IHS044 "OS(on) <7S0)

v'

"

v'

D,
0,

GND

"

"

"

1~2

D,
D,

v'

"

"

s,

0,

s,

0,

S,

D,

S,

D,

GND

VL

s,

'L

"
0,
0,

S,

'",
'",S2

v'

5,

0,

s,

0,

'N,
0,
D.

S.

0,

5,

0,

OND

v-

(OG18S EQUIVALENT)
DUAL OPST
IHS04S ('OS{on) <7S0)

s,

"

v-

y'''~

S,

0,
D,

S,

"

GND

3-109

v'

IH5052/IH5053
CMOS Analog Gates
FEATURES

technology provides Input overvoltage capability to ± 25
volts without damage to the device, and the destructive
latch-up of solid state analog gates has been eliminated.
Early CMOS gates were destroyed' when power supplies
'were removed with an inp!Jt signal present. The INTERSIL
CMOS technology has eliminated this serious systems
problem. Key performance advantages are TIL compatible
and ultra low-power operation. The. quiescent current requirement is less than 10~. Also designed Into the
IH5052/3 is guaranteed Break-Before-Make switching. This
is logically accomplished by extending the tON time
(400nsec TYP.) such that It exceeds tOFF time (200nsec
TYP.). This insures that an ON channel will be turned OFF
before an OFF channel can turn ON and eliminates the
need for external logic required to avoid channel to chan-IB
nel shorting during switching. The IH5052 Is designed to
have switch closure with Logic ,"0" (O.BV or less) and the
IH5053 is designed to close switches with a Logical "1"
(2.4V or more). '

• Switches Greater Than 20Vpp Signals With ±15V
Supplies
• Quiescent Current Less Than 10~
• Overvoltage Protection to ± 25V
• Break·Before·Make Switching toff 100nsec, tori
250nsec Typical
• T2L, DTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• IH5052 4 Normally Closed Switches
• IH5053 4 Normally Open Switches

GENERAL DESCRIPTION
The IH5052/3 solid state analog gates are designed using
an improved, high voltage CMOS technology. This provides
ease-of·use and performance advantages not previously
available from solid state switches. This improved CMOS

PIN CONFIGURATIONS

FUNCTIONAL DIAGRAM

OUTLINE DWGS
DE,JE
DUAL-IN-LINE PACKAGE

SWITCH STATES ARE

FOR LOGIC "1" INPUT

ORDERING INFORMATION
IH505X

C

JE

T

TL_ _ _ _ _ Package

'JE = 16-Pln CERDIP
DE = 16-Pln Ceramic .DIP (Special Order Only)

Temperature Range
M=Mllltary
C = Commercial

L - - - - - - - - - - - B a s l c Part Number

3-111

IHSOS2/IHS.OS3
MAXIMUM RATINGS

V+-V-' ..................................... <33V
V+-Vo ................................ .' ..... <30V
Vo-V- ...................................... <30V
Vo-Vs ................... '. . . . . .. . . . . . • . . . .. < ± 22V
VL-V- ................. ' ..................... <33V
VL-VIN ...................................... <30V
VL-GND ............... ' .......•............. <20V
VIN-GND ..................................... , < 20V

CurrenHAnyTerminall .....•.........•...•..•.... <30mA
Storage Temperature ..........•....••• --£5°Cto+150°C
Operating Temperature •.......••.•.... '-55° C to +125°. C
Power Dissipation ..........•..........••......• 450mW
(All Leads Soldered to a P.C. Board)
Derate 6 mW/·C Above 70·C
Lead Temperature (Soldering, 10 sec) ............. , 3oo·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions above those Indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

-ELECTRICAL CHARACTERISTICS (@25'C, V+ = +15V, v- = -15V, VL= +5V, GND=OV)
MIN;/MAX. LIMITS

PER CHANNEL

MILITARY

SYMBOL CHARACTERISTIC
ItNIONI

Input Logic Current

ItNIOFFI
rOSION)

Input Logic Current

-55'C

+25'C

1
1

1
' 1

75

Drain-Source On

COMMERCIAL
+125'C
1

0

75

1
100

25

25

±11

TEST CONDITIONS
+70'C

UNITS

1

+25'C
1

1

I'A

V,N - 2.4VIIH50531-0.SV IIH50521

1

1

1

V,N - 0.8VIIH50531-2.4V IIH5052)

80

80

100

I'A
0

25

30

30

30

0

Is (Each Channell

±11

±11

±10

±10

±10

V

Is

1

1

100

5

' 5

100

nA

VANALOG - -10V to +10V

2

2

200

10

10

100

nA

Vo - Vs - -10V to +10V

500

ns

RL 1kO. Vanal, = -10V to
+ 10V See Fig.

250

ns

RL-1kO. Vanal , = -10V to
+ 10V See Fig.,

15

20

54

.50

mV
dB

IS-1mA. Vanalog= -'10"'to
+10V

Resistance
MOS(ON)
VANALOG
IOIOFF)

Channel to Channel
ROSION) Match
Min. Analog Signal
Handling Capability
Switch OFF Leakage

=1 mA

=10mA

Current
IO(ON)
+IS(ON)

Switch On Leakage
Current

tON

Switch "ON" Time '

500
250

=

tOFF

Switch "OFF" Time

O(INJ,I
OIRR

Chiuge Injection
Min. Off Isolation

1+

+ Power Supply
Quiescent Curent

10

10

100

10

10

100

I'A

I

- Power Supply
Quiescent Current
+5V Supply
Quiescent Current

10

10

100

10

10

100

I'A

'10

10

100

10

10

1~0

pA

10

10

100

10

10

100

I'A

See Fig. B
1- 1 MHz. RL - 1000. CL " 5pF
See Fig. C

Rejection Ratio

IVL
I'GND

Gnd Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

54

=

V+ = +15 V. V- -15 V. VL= +5 V
wlthGNO
Switch Outy Cycle" 10%

dB

50

One Channel 011; Any Other
Channel Switches as per Fig. E,

TEST CIRCUITS
FIG. A

FIG.B

JOG l~uT

3Y

OYn~_

L~:;'C~h
INPUT

,

.

YOUT

1DpF

J-=

1kn

[fl

FIG.C
'ANALOG '",PUT

ANAL

.-D--o-t>--;
LOGIC
1L INPUT

10.00DpF

3-112

J

Your

YPP@1MC

T2L

i..OGIC INPUT

.

(NO~_
":'

'

-=":'

~YOUT

t

oon

510

O~OI!"

IH5052/IH5053
TYPICAL ELECTRICAL CHARACTERISTICS (Per Channell
ros(ON) VB
POWER SUPPLY VOLTAGE

ros(ON) VB VANALOG SIGNAL

CHARGE INJECTION VB VANALOG
(SEE FIG. 8) CL = 10,OOOpF

160

100

I

80

40r-+--r~--+--r~--+-~

140
120

!10~

+1JSOC

I-- I-+25°C
I--

60

:::..
o
o

20

-

80

0

-J5'C

a: 40

100

1= F-

a:

60

I

40

Is '},mA

20

r- I -

+12

I--

:t1S

I-- ~

-10 -7.5

-5

-2.5

0

2.5

5

7.5

10

VANALQG (V)

-10 -7.5

~

~

S

~

~

i

0

30
25
20
15

.

@ :!::15V SUPPLIES

o

35r-+--r~--+--r~--t-~

~

-5

-2.5

0

2.5

5

7.5

':t:J;;t~::1:J[~::t:j
10

-10 -7.5 -5

-2.5

VANALOG (V)

0

2.5

5

7.5

VANALOG (V)

FIGURE 0

r------,

CROSS COUPLING
REJECTION vs FREQUENCY

100

rn

OFF

120

CHANNEL

'I'

r-.r-.

80

.

............

"r....
T2L LEVELS

20

~

2000mVpp
R -120~OGI YOUT (mYpp)

cf 7

o
1

10

100
1k
10k
FREQUENCY (Hz)

lOOk

i-..J
!I

.i
I
I

I
I

.

YOUT

loon

L -=

I
I

60
40

_1 r"\---"'-- .
~-I..F~
-=-

n-. +o---t>--

-~I~~~

I

L-----=1J

SWITCHED
CHANNEL

5Hl
2Ypp
@1Me

loon

1M

FIGURE E

OFF ISOLATION vs FREQUENCY
-120

-100

~
it

1',

2Vpp

'\

,

@1MC

-80

-:-

'r--

;;0

5111

-:-

OFF STATE'

£

,;

-40
100H

-20
OIRR ~~ 20LOG YOUT (mVpp)
1- "j' 1 '-1- -1- 2000mYpp

1Hz

10Hz 100Hz

lk

10k

lOOk

1M

FIGURE F

FREQUENCY (Hz)

POWER SUPPLY QUIESCENT CURRENT
vs LOGIC FREQUENCY RATE

1

'000

~

..

V

:>

.

 ±15V, a forward bias condition exists between drain and
body of the MOSFET. For example, in Fig. H .ifthe analog
signal input is more negative than -15V, the drain to body of
the N-channel FET is forward biased and destruction of the
device. can result. Now by floating the body, using diode D1,
the drain to body of the MOSFET is still forward biased, but
D1 is reversed biased so no current flows (up to the
breakdown of 01 which is;::: 40Vl. Thus, negative excursions
of the analog signal can go up to a maximum of - 25V.
When the signal goes positive (;;" + 15V, D1 is forward biased, but now the drain to body junction is reversed forthe
N-channel FET; this allows the signal to go to a maximum
of + 25V with no appreciable current flow. While the explanation above has been restricted to N-channel devices,
the same applies to P-channel FETs and the construction
. is as shown in Fig.· J. Fig. J describes an output stage
showing the paralleling of an Nand P-channel to linearize
the ros(On) with signal input. The presence of diodes 01 and
02 effectively floats the bodies and provides overvoltage
protection to a maximum of ± 25V.

ANALOG
SIGNAL
INPUT

VOUT

T

RL

FIGURE I

v+
01
ANALOG
SIGNAL
IN

0-_---,

RL

v+
FIGURE J

3-114

,...--...-"V+ >5V
QV>V- > -15V

APPLICATIONS

PROGRAMMABLE GAIN NON-INVERTING AMPLIFIER WITH SELECTABLE INPUTS

VIN1
YOUT

CH,

CH,
VINJ

CH,
V,N4

CH,

9.9k
II

100kll

loon

-15V

+5V

ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY

3-116

U~DIl.

IH5052/1H5053
APPLICATIONS (Continued)
4-CHANNEL SEQUENCING MUX
DECODER

SEQUENCER
(2 BIT BINARY COUNTER)

ANALOG SWITCH
S,
YINI

J-K 0'=",,_1-+---,
MUX
SEOUENCE
RATE

RESET

0,

FLIP
FLOP

o-r--------'
J .J-K

0,

FLIP
FLOP

YIN4

KRESETQI-:;c2'+~~~~=:i=Lf"i-t-'1

0,

'------'

OUT

DUAL J-K FLIP FLOP
POSSIBILITIES
TTL - SN5473

3 INPUT NAND

POSSIBILITIES
TTL - 1 1/3 SN5410
CMOS - 1 1/3 CD4023

CMOS - C04027
ENABLE

YINJ

S,

aI-:;c2,c+--1H+-HH

0----------'

Truth Table (IH5052)

ENABLE

MUX
SEQUENCE
RATE

SEQUENCER
SWITCH STATES
(- DENOTES OFF)
OUTPUT
21
20
SW1 SW2 SW3 SW4

1

1 pulse

1

0
0
0

1

2 pulses

0

1

1

3 pulses

1

1

4 pulses

0

0

0
0

1

0
0

ON

-

-

-

ON

1

--

-

-

ON

0

ON

-

-

-

-

-

A Latching DPDT
The latch feature insures positive switching action in response to non-repetitive or erratic commands. The A1 and A2 inputs are
normally low. A HIGH input to A2 turns 81 and 82 ON, a HIGH to A1 turns 83 and 84 ON. Desirable fo"r use with limit detectors,
peak detectors, or mechanical contact 'closures.
+15V

+5V

T5V

VL
S,

Truth Table (IH5052)

A,
OUT 1

COMMAND
A,

53
QUAD 2 INPUT
NAND GATES
TTL ,- OM7400
OR OM5400
CMOS - CD4011
or DM74COO

5,

OUT 2

S.

3-117

STATE OF SWITCHES
AFTER COMMAND

A2

A1

S3 & S4

S1 & S2

0
0

0

same

same

1

off

1

0

on
off

1

1

on

INDETERMINATE

IH5108
a·Channel Fault Protected
CMOS Analog Multiplexer

GENERAL DESCRIPTION

FEATURES
• Ultra low leakage -10(011):5 100pA
-. Power supply quiescent current less than 1inA
• ± 13V analog signal range
• . No SCR latchup
• Break·before·make switching
• Pin compatible with DG508, HI508 and AD7508
• All channels OFF (IILK :5100nA) when power OFF, for
analog signals up to ± 25V
• Any channel turns OFF (IILK :5100nA) if input exceeds
supply raiis by up to ± 25V. Throughput always
< ± 14V (± 15V supplies)
• TTL and CMOS compatible binary address and
enable inputs

11

. FUNCTIONAL DIAGRAM

The IH5108 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug·in replacement for the
DG508 and similar devices, but adding fault protection to the
standard performance. A unique serial MOSFET switch en·
sures that an OFF channel will remain OFF when the input
exceeds the supply rails by up to ± 25V, even with the supply
voltage at zero. Further, an ON ,'channel will be limited to a
throughput of about 1.5V less than the supply rails, thus
affording protection to any following circuitry such as op
amps, D/A converters, etc. Cross talk onto "good" channels
is also prevented.
A binary 3·bit address code together with the ENable input
allows selection of anyone channel or none at all. These 4
inputs are all TTL compatible for easy logic interface; the
ENable input also facilitates MUX expansion and cascading .

DECODE TRUTH TABLE

S1~
s,~

S3~
S4~
S,

VOUT 0

o---o---""'C

A2

A,

Ao

X
0
0
0
0
1
1
1
-1 -

X
0
0
1
1
0
/0
1
1

X, 0
0
1
1
1
0
1
1 . 1
0
1
1
1
0
1
1
1

EN

ON SWITCH
NONE
1
2

3
'4
5
6
7
8

, A o, A A2, EN
"
Logic '11" = VAH ;o:2.4V
Logic "0" = VAL :50.8V

PIN CONFIGURATION

AO

A1

A,

(OutlinedrawingJE,PE)

EN (ENABLE INPUT)

3 LINE BINARY ADDRESS INPUTS
(101)ANDENHI
ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON

TOP,VIEW

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

PACKAGE

16 pin CERDIP

IH5108CJE

- 55·C to + 125·C
O·C to 70·C

IH5108CPE

O·C to 70·C

16 pin plastic DIP

IH5108MJE

3·118

16 pin CERDIP

O~OIL

IH5108
ABSOLUTE MAXIMUM RATINGS
VIN(A, EN)toGround ••••••••••••••••••••••• -15Vto 15V

Operating Temperature ••••••••••••••••••• - 55 to 125°C

VSorVDtoV+

StorageTemperature •.•.••....•••••••.••• - 65 to 150°C

••.•.••••••••••••.•.••••••• + 25V, -40V

VSorVDtoV- ..••••.•.•.••••.•••...•.•.• -25V, +40V

Power Dissipaton (Package)·

•••• : ••••••••••••• 1200mW

v+ toGround ••••••••••••••••••••••••••••••••••• 16V
V- toGround ••••••••••.•••••••.•••.•••••••••• -16V

• All leads soldered or welded to PC board. Derate 10mW'·C above
70·C.

Current (Any Terminal) ••••••..••••••••••••••.•••• 20mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera·
tlon of the device at these or any other conditions above those Indicated in the operational sections of the specifications is not Implied. Exposure to absolute max·
imum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS V + =15V, V -

CHARACTERISTIC

NO
MAX LIMITS
MEASURED TESTS TYP
TERMINAL
PER 2SoC
MSUFFIX
2SOC
.12SoC
O·C
TEMP
-SS.·C
S to D

rDS(on)

8
8

S

500

1000
1000

1000
1000

1500
1500

1200
1200

1200.
1200

UNIT

1800
1800

Il

Sequence each
switch on
VAL -0.8V,
VAH = 2.4V

rOS(on)max-rOS(on)min V

S = ± 10

V

rOS(on)avg.

IS(OIl)

S

10 (011)

D
D

8
8
1
1
8

0.002
0.002
0.03
0.03
0.1

0.05
0.05
0.1
0.1
0.2

50
50
100
100
100

0.1
0.1
0.2
0.2
0.4

50
50
100
100
100

8

0.1

0.2

100

0.4

100

Is with Power OFF

S

8

1

10

10

1000

50

50

5000

Is wilh

S

8

1

10

10

1000

50

50

5000

Ao, A A2,
"
or
EN

4

.01

-10

-30

nA

IEN(on) .IA(on)
. or

-10

-30

.4

.01

10

D

0.3

1

t open

D

0.2

ton (EN)

D

0.6

1.5

toll(EN)

D

0.4

1

ton-toft Break-

D

50

25

S Supply
U Current
P

I

8

30

10

I

See Figure 2

10

See Figure 3

ns

VEN = + 5V, AO' A A2 Strobed
"
VIN = ± 10V, Figure 4

V EN =0. RL = 200!l. CL = 3pF. Vs = 3 VRMS.
I =500 KHz

S
D
D toS

5
25
1

pF

I

Vsupp = OV, VIN = ± 25V,
VEN = Vo = OV, Ao, A A2 = OV or 5V
"
VIN = ±25V, Vo= ±10V

"s

---,

-15V FROM +15V FROM
DRIVER
DRIVER

Figure 5. Serles Connection of Channel Switches

Within the normal analog signal band, the inherent variation
of switch ON resistance will balance out almost as well as
the customary parallel' configuration, but as the analog
signal approaches either supply rail, even for an ON channel,
either the p- or the n-channel will become a source follower,
disconnecting the channel (Figure 6). Thus protection is
provided to any Input or output channel against overvoltage
on any (or several) input or output channels even in the
absence of multiplexer supply voltages, and applies up to the
breakdown voltage of the respective switches, drawing only
leakage currents. Figure 7 shows a more detailed schematic
of the channel switches, including the back-gate driver
devices which ensure optimum channel ON resistances and
breakdown' voltage under the various conditions.
Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use'the
logic inputs as.a sort of phantom supply; this could result in
an output up to that logic level. 10 prevent this from occurring, simply ensure that the ENable pin Is LOW any time the
multiplexer supply voltages are missing (Figure 8).
3-121

-15V

~15V

FROM
DECODER

+15V

Figure 7. Detailed Channel Switch Schematic
+15V

lDDpF

Figure 8. Protection Against Logic Input

O~OI!;.

IH5108
MAXIMUM SIGNAL HANDLING CAPABILITY
The IH510S is designed to handle signals In the± 10V range,
with a typical rOS(On) of 6000; it can successfully handle
signals up to ± 13V, however, rOS(,,") will Increase to about
1.SK. Beyond±13V the device approaches an open circuit,
and thus ± 12V Is about the practical limit, see Figure 9.

Figure 10 shows 'the input/output characteristics of an ON
channel, illustrating the Inherent limiting action ofthe series
switch connection (see Detailed Description), while Figure 11
gives the ON resistance variation with temperature;

""

fDS(onl

t

'

2Kn
1.SKn

lKn

sooo'

-VSOURce

~,_--1_--1~--l_--l--'--lL-._L-.~L-_L--'-.L..:_.L..:_.L..:_.L..:--,..L-_..L_..L_+

-14V

-12V

-10V

-8V

-6V

-4V

-2V

ov

2V

4V

6V

Figure 9. rDS(~n) vs Signal Input Voltage @ TA =

8V

10V

12V

14V

+VSOURCE

+ 25°C

+VOUT

16
14

12
'10

vour

-V'N+--+-t-t--t-+-+"""'I-+-+-+-t-t--.::>I':-+-+"""'I-+-+-+--f-l--+-+--+--if--++V,N'
-4
-6
-8
-10

-12
-14
-18

-Your
Flglire10. MUX Output Voltage vs Input Voltage
Channel 1 Shown; All Channels Similar

3-122

D~DIl.

IH5108·

300n
200n

Vsupp=

:t:15V
VIN= ±10V

loon
'-2S'C

2S'C

7S'C

12S'C

TEMPERATURE

Figure 11. Typical rDS(On) VS Temperature

USING THE IH5108 WITH SUPPLIES OTHER
THAN :!:15V
2000n
18000

The IH5108 will operate successfully with supply voltages
from, ± 5V to ± 15V; rOS(on) increases as supply voltage
decreases, see Figure 12. Leakage currents; however,
decrease with a lowering of supply voltage, and therefore the
error term product of rOS(On) and leakage current remains
reasonably constant. rOS(on) also decreases as signal levels
decrease. For high system accuracy [acceptable levels of
ros(on)l the maximum input signal should be 3V less than the
supply voltages. The logic levels will remain TTL compatible.

1600n

~
~'.~.'~

1400n
1200n
1000n

soon

+10VSIGNAL

600!!

-10VSIGNAL

400!!
200!!
:!:10V

:!:SV

:!:lSV

Figure 12. rDS(on) vs Supply Voltages

IH5108 APPLICATIONS INFORMATION
-15V

+lSV

DECODE TRUTH TABLE

EN
IHS10B

AO

---I-"

A,

---+-+-..

A2--++-H
TTLOR .
CMOS

INVERTER

'::"

Your

IH510B

A3

Ai

Al

Ao

ON SWITCH

0
0
0
0
0
0
'0
0
1
1
1
.1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816

Flgure 13. 1 0116 channel multiplexer using two I H5108s.
Overvoltage protection is maintained between all
channels, as Is break·belore·make switching.

3·123

IH5108
IH5108 APPLICATIONS INFORMATION (Cont.)

-t>o-

VL
+5V

+15V

r

TTU CMOS INVERTER

=D>-

AD

'TTUCMOS NOR GATE

IH5108
10UTOF8
MUX

A,
A.

Ao

EN

'A4

I

1
!
, ANALOG INPUTS 8

Ao

~

...

EN

I•

I' '7

~
~
AI

I

I

..I

~

KYl>l

1-.

1.

n
.~

.

S.!-.

D3

1
1
..J

IN3

IH5108
10UTOF8
MUX

1.

~ VOUT

IH5053

AD

EN

D.

r-

J.

17 ANALOG INPUTS 24

~

D,

1

IN,

ANALOG INPUTS 18

),

-A,

I

s,!."

52

IH510S
10UTOF8
MUX

EN

-

n

IH5108
1 OUT OF 8
MUX

'Ai

.....

r

~~s.--L-

1

J.

25 ANALOG INPUTS 32

"

D.

r-

J

15V

DECODE TRUTH TABLE

DECODE TRUTH TABLE

A. A3 A2 A, Au ON SWITCH

A4 Aa A2 A1 Au ON SWITCH

0
0

0
0
0
0

0
0
0
0
0
0
0
0

0
0

o
0
0
0

0

0
0
0
0
1
1
l'
1
0
0

0
0
0
1
1
1 0
1 '0
1 1
1 1
1 1
1 1

0
0
1.
1
0

0
1
1
0
0
1
1
0
0
1
1

0
1

0
1
0
1

0
1,

0
1

0
1
0
1

0
1

51
-52
53
54
55
S6
57
58
59
510
,511
512
513
514
515
516

-1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0

0
0
0

0
O'
0
0
1
1
1
1
1
1
1
1

0
0
0

0
0
1
0 1
1 0
1 0
111
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

0
1
0
1
0
1
0
1
0
1

0
1
0
1

0
1

Figure 14.1 of 32 mulllplexer using 41H5108s an'd an IH5053 as a
submultlplexer. Note that tha IH5053 Is protected
against overvoltage. by the IH5108s •. Submultlplexing
reduces output leakage and capacitance.

3-124

517
518
519
520
521 •
522
523
524
525
526
52?
528
529
530
531
532

. D~DIl.

IH5108
CHIP TOPOGRAPHY

~

EN

O.

Sa

GND
!-----O.111"

3-125

I

NOTES:

3-126

IH5140 Family
High Level CMOS
Analog Gates
FEATURES

GENERAL DESCRIPTION

•

The IH5140 Family of CMOS monolithic switches utilizes Intersil's latch-free junction isolated processing to
build the fastest switches now available. These switches
can be toggled at a rate of greater than 1 MHz with super
fast ton times (80ns typical) and faster toll times (50ns
typical), guaranteeing break before make switching.
This family of switches therefore combines the speed
of the hybrid FET DG 180 Family with the reliability and
low power consumption of a monolithic CMOS con'
struction.

•

Super fast break before make switching
ton 80ns typ, toll 50ns typ (sPST switches)
Power supply currents less than 1J.LA

• OFF leakages less than 100pA @ 25°C
guaranteed
•

Non-latching with supply turn-off .

•
•

Single monolithic CMOS chip
Plug-in replacements for IH5040 family and part of
the DG180 family to upgrade speed and leakage

•
•

Greater than1MHz toggle rate
Switches greater than 20Vp-p signals with
±15V supplies
T2L, CMOS direct compatibility

•

OFF leakages are guaranteed to be less than 100pA at
25°C. No quiescent power. is dissipated in either the ON
or the OFF state of the switch. Maximum power supply
current is lJ.LA from any supply and typical quiescent
currents are in the 10nA range which makes these
devices ideal .for portable, equipment arid military
applications.
The IH5140 Family is completely compatible with TTL
(5Vl logic, TTL open collector logic and CMOS logic
gates. It is pin compatible with Intersil's IH5040 Family
and part of the DG180/190 Family as shown in the
switching state diagrams.

ORDEAINGINFORMATION
Order
Part Number
IH5140 MJE
IH514D CJE
IH514D CPE
IH514D MFO
IH5141 MJE
IH5141 CJE
IH5141 CPE
IH5141 MFD
IH5141 CTW
IH5141 MTW
IH5142 MJE
IH5142 CJE
IH5142 CPE
IH5142 MFO
IH5142 CTW
IH5142 MTW
IH5143 MJE
IH5143 CJE
IH5143 CPE
'IH5143 MFO
IH5144 MJE
IH5144 CJE
IH5144 CPE
IH5144 MFO
IH5144 CTW
IH5144 MTW
IH5145 MJE
IH5145 CJE
'IH5145 CPE
IH5145 MFO
Note:

Function
SPST,
SPST
SPST
SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Qual SPST
SPOT
SPOT
SPOT
SPOT
SPOT'
SPOT
Dual SPOT
Dual SPOT
Dual SPOT
Dual SPOT
OPST
OPST
OPST
OPST
OPST
OPST
OualOPST
OualOPST
OualOPST
OualOPST

Package
16 Pin CEROIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00

TO-100
16
16
16
14

Pin
Pin
Pin
Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

TO-l00
TO-l00
16 Pin
16 Pin
16 Pin
14 Pin
16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack
CERDIP
CERDIP
Plastic DI P
Flat Pack

TO-IDO
TO-l0D
16
16
16
14

Pin
Pin
Pin
Pin

CERDIP
CERDIP .
Plastic DI P
Flat Pack

FUNCTIONAL DIAGRAM
Temperature
Range
-55°C to 125°C
DOC to 7DoC
DoCt07DoC
-55° C to 125° C
-55°C to 125°C
DoC to 70°C
DOC to 7DoC
-55° C to 125° C
0°Ct07DoC
_55° C to 125° C
_55° C to 125° C
DOC to 70°C
DOC to 7DoC
-55° C to 125° C
DOC to 7DoC
-55° C to 125° C
-55° C to 125° C
DOC to 70°C
DOC to 70°C
-WC to 125°C
_55° C to 125t C
DOC to 7DoC
DOC to 7DoC
-55° C to 125° C
DoG to 7DOG
-55° C to 125° C
-55°C to 125°C
DoC to 7DoC
DOC to WC
-55°C to 125°C_

V'

FIGURE 1_ Typical Driver/Gate - IH5142

1. Ceramic (side braze) devices also available; consult factory.
2. MIL lemp range parts also available with MIL-STD-883 processing.

3-127

8J

IH5140·IH5145 Family
ABSOLUTE MAXIMUM RATINGS

V"'-V-

Current (Any Terminal) ............ < 30 mA
Storage Temperature
-65°C to +150°C
Operating Temperature .... -55°C to +125°C
Power Dissipation· ...... . . . . . . . . . . .. 450 mW
(All Leads Soldered to a P.C. Board)
Derate 6 mW/oC Above 70°C
Lead Temperature (Soldering 10 sec.) .. 300°C

V~VD

VD-VVD-VS
VL-VVL-VIN
VL
VIN

<33V·
<30V
<30V
<±22V
<33V
<30V
<20V
<20V

NOTE:

Stresses above those listed under
Absolute Maximum Ratings maycause

permanent damage to the device.
These are stress ratings only, and func~
tional operation of the device at these
or any other conditions above those
indicated in theoperatiqnal sections of
the specifications'is not implied. Expo·
sure to absolute maximum rating conditions for extended periods may affect

device reliability.

ELECTRICAL CHARACTERISTICS (@ 25°C, V+ = +15V, V- = -15V, VL = +5V)
MIN.lMAX. LIMITS
PER CHANNEL
MILITARY

COMMERCIAL.

SYMBOL

CHARACTERISTIC

-55°C

+25°C

+125°C

0

+25°C

+70°C

IINH

Input Logic Current

1

1

1

1

1

1

p.A

VIN = 2.4 V Note 1

IINL

Input Logic Current

1

1

1

1

1

1

p.A

VIN = O.B V Note 1

rOS(On)

Drain-Source On
·Resistance

50

50

75

75

75

100

0

Is=-10mA
VANALOG = -10 V to +10 V

~rOS(On)

Channel to Channel
rOS(On) Match

25

25

25

30

30

30

0

Is (Each Channell = -10 mA

VANALOG

Min. Analog Signal
Handling Capability

±11

±ll

±11

±10

±10

±10

V

Is = 10 mA

10(off)+

Switch OFF Leakage

0.1

0.1

20

0.5

0.5.

20

nA

IS(off)

Current

0.1

0.1

20

0.5

0.5

20

Switch On Leakage

0.2

0.2

40

1

1

40

lo(on)+

r

UNITS TEST CONDITIONS

Vo = +10 V, Vs = -10 V
Vo = -10V, Vs = +10 V

nA

Vo = Vs = -10 V to +10 V

IS(on)

Current

ton

Switch "ON" Time

toff

Switch "OFF" Time

Q(INJ.).

Charge Injection

100

150

PC

See Fig. 4, Note 2

OIRR

Min. Off Isolation
Rejection Ratio

54

50

dB

f = 1 MHz, RL= 1000, CL :5 5 pF
See Fig. 5, Note 2

1+

+ Power Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

p.A

1-

- Power Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

p.A

V' = +15 V, V- =-15 V,
VL= +5 V

IL

+5 V Supply
QuiElscent Current

1.0

1.0

10.0

10

10

100

p.A

Switch Duty Cycle < 10%
See Fig. 6

IGNO

Gnd Supply
Quiescent Current

1.0

1.0

10.0

10

,10

100

p.A

CCRR

Min. Channel to
Channel Cross
Coupling Rejection.
Ratio

See pages 4 & 5 for switching time specifications and timing diagrams.

,

54

50

dB

One Channel Off; Any Other
Channel Switches
See Fig. 7, Note 2

Note: 1. Some channels are turned on by high (1) logic inputs and other channel.s are turned on by low (0) inputs; however O.BV to
2.4V describes the min. range for switching properly. Refer to logic diagrams to find logical value of logic Input required
to produce ON or OFF state.
2. Charge injecHon, OFF isolation, and Channel to Channel isolation are only sample tested in production.

3-128

\
I

1

U}t5140-IH5145
Family
}
100

190

:'

IH~141

S

70

so

60

60

--- -

30

+125 C

+s

+6

+2

+4

40

-

2S'C

-SS'C

20
+10

.............

Q

'--

-2

r--

I--

+S

+10

-10

~

1

i---!10V, ,SV SUPPLIL

+6

+2

+4

-2

-4

-6

-S

-10

FIGURE 3. rOS(on) vs. Power Supplies.

-120~::::::::~:::::::j---~-t-----t----,---1

+101---j---t-\---t-----,7i--

~

TA =: +25"C
IHS141 DATA

ANALOG SIGNAL VOLTAGE IVI

FIGURE 2. rOS(on) vs. Temp., @ ±15V, +5V Supplies.

~

V

.....

±15V. +5V SUlPLIES

ANALOG SIGNAL VOL TAGE IVI

"

SU~PLlES

0

20

-s

-6

-4

'"
r- r-- -

± SV, I+sv

r---.....

so

r--

40

"-

90
DdTA

~

+5

-1001-----1-----+-~~___+-----+----~

~

bI'~+--I--+--+-- ~

§
<
z

-80

><

l'

-sl--+-~~-1--_+--+-

i -10i--+--++-1---+--+--t-NOTE:

+VINJECT

>-

-60

>0

tVINJECT

~
OmV

?f~
51n

-=-

3

ffi ~c

~

12 +5V

CD .£-If-®+15V

-401-----

.V!NJECT~

0)

-V1N"JECT

,

~

-20 1---C-=-1-"F

CD

-c~

CD

-=- ---+----+-----1

SOCKET ON COPPER GROUND PLANE JIG

-10

OL-~LLUllll__L~~lli__L~~llL~_U~WL~_L~LU

-s

+10

100

. lK

ANALOG SIGNAL VOLTAGE (V)

10K

lOOK

1M

10M

FREQUENCY (Hz)

FIGURE 5, "OFF" Isolation vs. Frequency.

FIGURE 4. Charge Injection vs. Analog Signal.

2.S ,--,---r-.-r-rrn,----r-r-rT1"TTTr--r-,r-r-rTTm

2.6i--------:---+----'----+---------j
2.4i-------+-------+------'----j
2.2l---------+_

I+h-"'--'+ SUPPLY

~o

F:
CD

o

1-_--'......---___

1--:----'...,....---

-100

~

"g

r-r--j

12 +5V11 +15V

~

Il ..;;O.05mA FROM

><

~

OV

>0

STROBE INPUT

P'"

-40

-20

0
100

1000

r - PERIOD OF PULSE REPETITION RATE (us)

FIGURE 6. Power Supply Currents vs. Logic
Strobe Rate.

-60

400ns

lps to DC

100

-80

:ii

-1""""l....SL+3V

0+lOVloon

lKH - - - -

10

-120

1K

100K.

FREOUENCY (Hz)

FIGURE 7. Channel to Channel Cross Coupling
Rejection vs, Frequency.

3-129

1M

10M

IH5140-IH5145 Family
SWITCHING TIME SPECIFICATIONS
(ton. toft are maximum specifications and ton-toft is minimum specifications)

,

MILITARY
Part
Number

Symbol

IH5140-

ton
toff
ton-toff

Characteristics
Switch "ON" time
Switch "OFF" time
Break-belore-make

ton
toff
ton-toff

Switch "ON" time
Switch "OFF" time
Break-belore-make

ton
toff
ton-toll

Switch "ONUtime
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belere-make
Switch "ON" time
Switch "OFF" time
Break-belore-make

5141

IH51425143

IH51445145

ton
toll
tan-tatl
ton
toff
tan-toff
ton
toff
ton-toll
ton
toll
ton-tall
ton
toff.
ton-tall

-55°C

COMMERCIAL

+25°C

+125°C

150
125
5
175
150
5

175
125
10

250
150

200
125
10
175
125
10
200
125
10

300
150
5
250
150
5
300
150
5
250
150
5
300
150
5

ton

@-15V

"::'

~

~

12"
11.

.
T 2l
+15VI""""I,NPUT

Q

~ ---I

o

.

+10V

10pF

+10V

OV I I

I

"::'"::'

1

2

3

0

o

®

II

I

ov

.

,r-"

-:.=...t

=:.::.

VO.UTA,

lKU

I
II
I +15V I
O V " - - ' LOGIC INPUT

I~ lN91.
1+15V

IfF1

toff

r- ~ I+.i' 'i
~
'-+I

+15V

I'

-TOV

-11-ton
"

I

Your

-.J~
toft

FIGURE 8.

"IGURE 9.

ton

16 +10V

15}------,

II

90%

I I

I

.2YJL: T2L INPUT

r----'

o

+10V

+16V

I

vaUTA

I~

toft
I +10V

+15V

+15V

Units

Test
Conditions

ns

Figure 8

"ns

Figure 9

ns

Figure 8

ns

Figure 9

ns

Figure 10

ns

Figure 11

ns

Figure 8

ns

Figure 9

5

175
125
10
200
125
10

@ ~NPUT

+70°C

+25°C

100
75
10
150
..
125
10

NOTE, SWITCHING TIMES ARE MEASUREO@ 90% PTS.

@ ±10V

O°C

I

lKU

VOUTAOA B

110%
II
I I

I

II
II

I

II

FIGURE 10.

FIGURE 11.
3·130

3

-r0
., -10VL.®

INPUT

I

.. 1,

2

10pF

IH5140·IH5145 Family
TYPICAL SWITCHING WAVEFORMS

SCALE:

VERT. ~ SV/DIV.
HORIZ. ~ 100ns/DIV.

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 8)

=.

II

•

..

11

••

,

~

VA·-:-·-~OV,..

• II

a•

.
•
'a

"

·.It! , .

I

.

~

.a

,J a

TTL LOGIC

a 1111·

..

I.

..., •

' 'VAn'"" '''':'0 V , II

a

•

.

VA "'.+10V

"

I'J

, TTL'LOGIC

pj

II ,

•

VA ~~tl0 V.

.

. .II

•• • •
• .. •

VII
i( ".1I
1OV'

iII

'

'

.
'

J
,
j

• "J

.'

::=
. ::=

;TTL'lOGIC'

•

'J
II'VA~
I
• 111....Hli II'
-10V, .

_ _ _ _ _ _~1i1

.-. ....-. ••.-•
•.

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9)

•••

Iii III

'

•I

"

••••

• •-"

•

11

I

1111

II

- •-

VA ·,c=-,'ov

n ULLOuGIC

~"

. •J

+12S0C

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 10)

• ••

..
•
I

'.
II

a

I

.. a

..

l1li",1·

.. v~,:" :+',00

• ••• • a'i
a

I'

" ~
'

, TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 11)

II II

nLl
,LOGIC"
I

III..'

!!III.

•

vA:~-'-lOV

'

II Iia ~

... •

II

3·131

IH5140·IH5145 Family
APPLICATION NOTE
To maximize switching speed on the IH5140family use
TTL open collector logic (15V lJIIith a 1knor less collector resistor). This configuration will result in (SPST)
ton and toff times of 80ns and 50ns, for signals between
-10V and +10V. The SPOT and OPST switches are
approximately 30ns slower in both ton and toff with the
same drive configuration. 15V CMOS logic levels can
be used (OV to+15V), but propagation delays in the
CMOS logic will slow down the switching (typical
50ns - 100nsdelays).

ANALOG OUT

ffi

16 ANALOG IN (CHANNEL A)

2 ,

3

+5V

@-5V.

CD
o
,0
ANALOG OUT

When driving the IH5140 Family from either+5VTTLor
CMOS logic, switching times run 20ns slower than if
they were driven from +15V logic levels. Thus ton is
about 105ns, and tott 75ns for SPST switches, and 135ns
and 105ns (ton, tOff) for SPOT or OPST switches. The low
level drive can be made as fast as the high level drive if
±5V strobe levels are used instead of the usual OV-+3.0V
driv,e. Pin 13 is taken to -5V instead of the usual GND and
strobe input is taken from +5V to -5V levels as shown in
~Figure 12.

@+sv

® +1SV

,ffi

II

~

CMOS
" LLEVEL
.
INPUT
STROBE

10

®

ANALOG IN (CHANNEL BI

FIGURE 12.

I]

The typical channel of the IH5140 family consists of both
P and N-channel MOS-FETs. The N-channel MOS-FET
uses a "Body Puller" FET to drive the body to -15V(±15V
supplies) to get good breakdown voltages when the
switch is in the off state (See Fig. 13). This "Body Puller"
FET also allows the N-channel body to electrically float
when the switch is in the on state producing a fairly
constant RDS(ON) with different signal voltages; While
this "Body Puller" FET improves switch performance, it
can cause a problem when analog input signals are
present (negative signals only) and power supplies are
off. This fault condition is shown in Figure 14.'
Current will flow from-10Vanalog voltage through the
drain to body junctionof 01, then through the drain to
body junction of 03 to GNO. This means that there is
10V across two forward-biased silicon diodes and current will go to whatever value the input sig'nal source is
capable of supplying. If the analog input signal is
derived from the same supplies as the switch this fault
condition cannot occur. Turning off the supplies would
turn off the analog signal at the same time.
This fault situation can also be eliminated by placing a
diode in series with the negative supply line (pin 14) as
shown in Figure 15. Now when the power supplies are
off and a negative input signal is present this diode i"s
reverse biased and no current can flow.

±15V FROM
DRIVERS

-15V

FIGURE 13.

~

/

GND WHEN POWER
SUPPLIES ARE OFF

,"

FIGURE 14.

@INA

® T2LAIN

~---..,i
@
@+5V

@+15V

@

T2LBIN.,

®INB

FIGURE 15.

3·132

lN914
OR EOUIVALENT

~I

·15V

O~OIL

IH5140·IH5145 Family
APPLICATIONS

.-~----~~~'6~+VANAlOG
15

SL...
T2L

OUTPUT

LOGIC
STROBE

ANALOG
INPUT

SL...
2R

IH5143

2R

T2L
LOGIC

IH5143

STROBE

ETC.  SAMPLE MODe
OV .. > HOLD MODE

EXAMPLE: If -v ANALOG'" -10VDC and +V ANALOG .. ,+10VDC
then ladd~r Legs are switched between ± IOVCC, depending upon 'state
of logic Strobe.

a

FIGURE 16. Improved Sample and Hold Using IH5143

FIGURE 17. Using the CMOS Switch to Drive an R / 2 R n
Ladder Network (2 Legs)

lOOk!!

100kH

HI PASS

lkH

68k!!

R

CONSTANT GAIN. CONSTANT O. VARIABLE FREOUENCY FILTER WHICH
PROVIDES SIMUL TANEOUS LOWPASS. BANDPASS. AND HIGHPASS
OUTPUTS. WITH THE COMPONENT VALUES SHOWN. CENTER FREOUENCY
WILL BE 235Hz AND 23.5Hz FOR HIGH AND LOW LOGIC INPUTS
RESPECTIVELY. Q= 100. AND GAIN =.100.
fn = CENTER FREQUENCY

FIGURE 18. Digitally Tuned Low Power Active Filter.

3·133

1

= 2n RC

IH5140-IH5145 Family
SWITCHING STATE DIAGRAMS
FLATPACK (FD·2)

SWITCH STATES ARE FOR LOGIC "1" INPUT
FLATPACK (FD·2)

DIP (JE, PEl

TO·100

DIP (JE, PEl
VL

v'

v'

VL

" o-t----<>.,-.-t--o 0,

" o-'--,<_ _o-;'L.:\-,'-<> 0,

" o-t----"t----<>.....'+-o 0,
OUALSPST
IH5l4l (rOS(on)< 75ft)

GND

< 75ft)
DIP (JE, PEl

DIP (JE, PEl
(DG19l EQUIVALENT)

FLATPACK (FD·2)

TO·l00
(DG188 EQUIVALENT)

v'

" 0-+----<,.,->'+-0 0,

I]:

" 0-+---<>"'-',+-0 0,
0,

0,

0,

0,
0,

"

'J

"

.,

IN,
IN,

"
"

'J

0,
OJ

IN,
IN,

0,

0,
0,

,13

GND
GND

DUAL SPDT
IH5l43 (rDS(on) < 75ft)

SPOT
IH5l42 (rDS(on) < 75 ft)
FLATPACK (FD·2)

DIP (JE, PEl

" o:-t----<>"i'Lf''''' 0,

., <>"+---<>'1''+'-0 0,

0,
0,

" <>-"+----<.-r''+-'<> 0,

"
53

,

IN,

"

OPST

0,
0,

IN,

"
GND

DIP (JE, PEl
(DG185 EQUIVALENT)

FLATPACK (FD·2)

·TO·l00

0,
0,

""

IN,

"
"
DUAL OPST
" IH5l45 (rOS(on) < 75ft)

IH514~ (rOS(on)< 75ft)

3·134

0,
0,

IN,

0,
0,

IH5208
4·Channel Differential
Fault Protected
CMOS Analog Multiplexer

U~UlL

FEATURES

GENERAL DESCRIPTION

• Ultra low leakage-lo(ofl):5100pA
• Power supply quiescent current less than 1mA
• :!: 13V analog signal range
• No SCR latchup
• areak·before·m~ke switching
• TTL and CMOS compatible strobe control
• Pin compatible with H1509, DG509 and AD7509
• All channels OFF (1ILK:5100nA) when power OFF: for
analog signals up to :!: 25V
• Any channel turns OFF (1ILK:5100nA) if input exceeds
supply rails by up to :!: 25V. Throughput always
< :!: 14V (:!: 15V supplies)
• TTL and CMOS compatible binary address and
enable inputs

The IH5208 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed asa plug·in replacement forthe
DG509 and similar devices, but adding fault protection to the
standard performance. A unique serial MOSFET switch en·
sures that an OFF channel will remain OFF when the input
exceeds the supply rails by up to ± 25V, even with the supply
voltagest zero. Further, an ON channel will be limited to a
throughput of about 1.5V less than the supply rails, thus
affording protection to any following circuitry such as op
amps, D/A converters, etc. Cross talk onto "good" channels
is also prevented.

o

A binary 2·bit address code together with the ENable input
allows selection of any channel pair or none at all. These 3
inputs are all TTL compatible for easy logic interface; the
ENable input also facilitates MUX expansion and cascading.

DECODE TRUTH TABLE

FUNCTIONAL DIAGRAM

'''3L
s,.o---"

S3'~

S4a

~

Da'

S'b~

.

S4b~

Ao

X

X'

0
0
1
1

0
1
0
1

EN

ON
SWITCH
PAlfI

0
1
1
1
1

NONE
1a, 1b
2a,2b
3a,3b
4a,4b

A o, A EN
"
Logic "1" = VAH :e:2.4V
Logic "0" = VAL SO.8V

"'~gr'
S3b~

A,

PIN CONFIGURATION

(Outline drawing JE, PE)

.

I

ADDRESS DECODE
10F4

~o

b

A1

IT:r;-v-~ A,
[I
~ GND
v~ v+
s,. [I
~ S'b
All

I

I

EN

S2a

.

2 LINE BINARY STROBE INPUTS
(00) AND EN=1
ABOVE EXAMPLE SHOWS CHANNELS 1a and 1b ON

S3a

S4a

D.

IT

0

~

IEJ

~

TOPVIEW

ORDERING INFORMATION

IH5208MJE

TEMPERATURE RANGE
- 55°C to

+ 125°C

PACKAGE
16 pin CERDI P

IH5208CJE

O°C to 70°C

16 pin CERDI P

IH5208CPE

O°C to 70°C

16 pin plastic DIP

3·135

S3b

ill

Db

~ S4b

IT
IT
o

PARTN\.IMBER

S2b

[TIj

:

rg
0

IH5208
ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) toGround ....................... -15V, + 15V
VsorVotoV+ .............. : ............ + 25V, -40V
VsorVotoV- ........................... -25V, +40V
V+ toGround ................................... 16V
V - to Ground ................................. -16V
Current (Any Terminal) ........................... 20mA

Operating Temperature ................... - 55 to 125·C
Storage Temperature ..................... - 65 to 150·C
Power Dissipaton (Package)· .................. 1200mW
• All leads soldered or welded to PC board. Derate.10mW/·C above

70·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera·
tion of the device at these or any other conditions above those Indicated in the operational sections oflhespecifications is not implied. Exposure to absolute max·
Imum·ratlng conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS V + =15V,V - = -15V, VEN =2.4V, unless otherwise specified.

CHARACTERISTIC

NO
MAX LIMITS
MEASURED TESTS TYP
TERMINAL
PER 25·C
M SUFFIX
-55·C
TEMP
25·C
125·C
O·C
S to 0

'OS(on)

8

a
S MOS(on)

500

1000
1000

1000
1000

1500
1500

1200
1200

1200
1200

UNIT

1800
1800

5

-

W

700

C SUFFIX
25·C
70·C

!l

TEST CONDITIONS

%

LlrOS(On)

.1

T
C 15 (011)
H
10 (011)

S
0
0

10(on)

F Is with Powel OFF
A

U
L IS with

8
8
1
1
B

0.002
0.002
0.03
0.03
0.1

0.05
0.05
0.1
0.1
0.2

50
50
100
100
100

0.1
0.1
0.2
0.2
0.4

50
50
100
100
100

B

0.1

0.2

100

0.4

100

S

8

1

10

10

1000

50

50

SOOO

S

8

1

10

10

1000

SO

SO

SOOO

AD, A" EN

4

.01

-10

-30

-10

-30

4'

.01

10

30

10

30

1

nA

Sequence each
switch on
VAL -O.BV,
VAH = 2.4V

Vo =10V, .
Is= -1.0mA
V o - -10V
Is = -1.0mA

rOS(on)max-rOS(on)min V ;;;' ± 10V
s
rOS(on)avg .

Vs = 10V, Vo = -10V
Vs - -10V, Vo - 10V
10V
Vo-10V, VS Vo - -10V, Vs _10V

'VEN = 0

Sequence each
switch on

VS(AII) = Vo - 10V
10V

VS(AII) - Vo -

VAL = O.BV, VAH -2.4V

Vs upp ", OV, VIN = ± 2SV,
. VEN =Vo =OV, AD, A" A2 =OV or SV
nA

VIN = ± 2SV, Vo - ± 10V

,

T Overvoltage
I
N

IEN(on)IA(on)
or
IEN(oll) IA(oll)

~A

ttransition

0

0.3

topen

0

0.2

tOn(EN)

0

0.6

toll(EN)

0

0

y ton-tof' Break·

0

8

VA - 2.4V or OV
VA 7'.15V or OV
See Figure 1

See Figure 2
1.S

0.4

1

SO

2S

10

"$

See Figure 3

ns

VEN = + SV, AD, A" A2 Strobed
VIN = ± 10V, Figure 4

dB

VEN = 0, RL = 200Cl, CL = 3pF, Vs = 3 VRMS,
f=500 KHz

pF

vo-o
Vs-O,V o

N Before·Make
A Oelay Settling

~

.Time
C "OFF" Isolation

CS(off)
CO(Olt)
COS(ott)
S Supply
U Current
P

I

+

I-

0

60

S

S

0
Oto S

2S
1

v+
V

1
1

40
2

I

Vs-O

1000
1000

200
100

3-136

~A

J
0

All VA, V EN =0 or 5V

VEN -OV,
t= 140 KHz
to 1 MHz

O~OIb

IH5208
+15V
D.

3.0V
1.4V
O.BV

,,10V
- - - . --S1b(on)

VS1b

:t10V

Your

PROBE
VS4b

PROBE IMPEDANCE

-15V

Rp?:1MI1

Cp::s:30pF

,
Figure 1. I tran', Swilching Tesl
+15V

+3.0V

~- 50%

VA

L,r---..,-j-<>""1---,<> Your

SWITCH

"",,5~0::roA~_ _

OU~~:'5~~ ihr-_tO_P_'"__-_TI-"Jt:

35pF

v,HIt

-P

Figure 2. lopen (Break-Belore·Make) Switching Tesl

+15V

.

+3V

__ •• ~rno,

VEN

I---J'----,-o-~~=-__o_ 5V

~-50%

I r AND II :-;100n5

_

OV
O.IVO

.-~

tEN (on) -

__ tEN(all)

SWITCH OUTPUT

Lr---..,-j--Q--'1---'<> VOUT

VOUT

35pF

Vo

-5V

Figure 3. Ion and toll Swllching Test .

ton and loll OF LOGIC
INPUTs10ns

+3V

I I

BREAK.BEFORE
I:
MAKE DELAY ~ll ~-~

,:

J __...::;'

IIV

. VOUT
VOUT2

:Ai
BR~~~:~~=~ -H-

Figure 4. Break·Belore·Make Delay Test

3-137

INPUT

'--+lOV

~

__ :A:{\ __ ~l~~T

IH5208
DETAILED DESCRIPTION
The IH5208, like all IntersH's multiplexers, contains a set of
CMOS' switches forming the channels, ·and driver and
, decoder circuitry to control which channel turns ON, if any. In
addition, the IH5208 contains an Internal regulator which provides a fully TTL compatible ENable Input that is Identical in
operation to the Address Inpu.ts. This does away with the
special treatments, that many multiplexer enable inputs require for proper logic swings. This identical circuit treatment
of the ENable and'Address lines also helps ensure the extension of break-before-make switching to wider multiplexer
systems (see applications section).
'

B1

(a) OVERVOLTAGE WITH MUX POWER OFF

-25V
OVERVOLTAGE

SIGNAL
INPUT

I

+15V

--

-

. G

To",
J.

N·CHANNEL
MOSFET IS OFF

.".

(b) OVERVOLTAGE WITH MUX POWER ON
-15V

-25V

1

. +15V

-15V

t~f

+25VFORCED
ON COMMON
OUTPUT

'--

~~T~=~AL

OVERVOLTAG/E
,
., CIRCUITRY
N·CHANNEL MOSFET~
N·CHANNEL
TURNED
ON
'
MOSFET
IS OFF
IS
BECAUSE Vos= +10V
-15V FROM +15V FROM P.CHANNEL
DRIVERS
DRIVERS MOSFET IS OFF

~

Figure 6. Overvoltage Protection ,

-15V

COMMON
OUTPUT

'1

S

P·CHANNEL
MOSFEJ IS OFF

Another, and more Important, difference lies in the switching
channel. Previous devices have used parallel n- and
p-channel MOSFET SWitches, and while this scheme yields
reasonably good ON resistance· characteristics and allows
the switching of rall-to-rall input Signals, It also has a number
of drawbacks. The sources and drains of the switch transistors will conduct to the substrate if the Inpout goes outside the supply ralls, and even careful use of diodes cannot
avoid channel-to-output and channel-to-channel coupling in
cases of Input overrange. The IH5208 uses a novel series
arrangement of the p- and n-channel switches (Figure 5) com:
blned with the dlelectrlcally Isolated process tQ obviate these
problems.

-15V

S

N·CHANNEL M O S F E T - r / 1D
ISTURNEDON
BECAUSE Vos = + 25V

+25VFORCED
ON COMMON
. OUTPUT
LINE BY
EXTERNAL
CIRCUITRY

S 0--.4.......,

0+-4--1--00

T

. -15V FROM +15V FROM
,DRIVER
DRIVER

Figure 5.· Series Connection of Channel Switches

Within the normal analog signal band, the inherent variation
of switch ON resistance will balance out almost as well as
the. customary, parallel configuration; but as the analog
Signal approaches either supply rail, even for an ON channel,
either the p- or the n-charinel.will become a source follower,
disconnecting the channel (Figure 6). Thus protection is
prOvided to an'y input or output channel against overvoltage
on any (or several) input or output channels even in the
,absence of multiplexer supply·voltages, and applies up to the
breakdown voltage of the respective SWitches, drawing only
leakage currents. Figure 7 shows a more detailed schematic
of the channel switches;' Including the back-gate driver
devices which ensure optimum channel ON resistances and
breakdown voltage under the various conditions.
Under some 'circf,Jmstances, If the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic Inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from, occurring,simply ensure that the ENable pin is LOW any time the
multiplexer supply voltages are missing (Figure 8).
'

.

,

3-138

-15V

-15V

FROM
DECODER

+15V

Figure 7. Detailed Channel Switch Schematic
+15V

l00pF

Figure 8. Protection Against Logic I'!put

IH5208
MAXIMUM SIGNAL HANDLING

CAP~BILITY

The IH520B is designed to handle signals in the ± 10V range,
with a typical rOSl on ) of 600n; it can successfully handle
signals up to ± 13V, however, rOSlon ) will increase to about
l.BK. Beyond ± 13V the device approaches an open circuit,
and thus ± 12V is about the practical limit, see Figure 9..

Figure 10 shows the input/output characteristics of an ON
channel, illustrating the inherent limiting action of the series
switch connection (see Detailed Description), while Figure 11
gives the ON resistance variation with temperature.

rOS(on)

t
2Kil

"OFF" BEYOND
THIS VOLTAGE

1.5K!1

1K!!

Soon
- VSOUACE ....._....L_....L_....L_....L_...L._-'-_-'-_-'-_--'-_--'-_--'-_---'_---'_ _' - - _ ' - - _ +

-14V

-12V

-10V

-8V

-6V

-4V

-2V

OV

2V

4V

6V

Figure 9. rOSlon) vs Signal Input Voltage @ TA

8V

10V

12V

+ VSOURCE

14V

=- + 25°C

1

+VOUT

16

14

-

12
10

VOUT

VOUT

-+-f-l--t-+-t--l-+-+-+-f--f--';!L-+-t--II-+-+-+-f-+-++-t--Ii--'-+ +V'N

-V'N .....
-24 -22 -20-18 -16 -14 -12 -10 -6 -6 -4 -2

4

6

8

m

g

M

-4

-6
-8
-10
-12
-14
-16
-VOUT

Figure 10. MUX Output Voltage vs Input Voltage
Channel 1 Shown; All Channels Similar

3-139

•

•

~

a

M

U~OIb

IH5208
rOS(on)

10000

3000
2000

Vsupp = :!:15V
VIN = ±10V

100<>

-55°C

m
III

.

125°C
TEMPERATURE

Fi g ure.11. Typical rOS(On) YS Temperature

USING THE IH5208 WITH SUPPLIES OTHER
THAN :t15V
.
.

'DS(o'i

TA = + 25°C

20000
18000

The IH5208 will operate successfully with supply voltages
from .± 5V to ± 15V; rOS(on) increases as supply voltage
decreases, see Figure 12. Leakage currents, however,
decrease with a lowering of supply voltage, and therefore the
error term product of rOS(on) and leakage current remains
reasonably constant. rOS(on) also decreases as signal levels
decrease. For high system accuracy [acceptable levels of
, ros(on)l themaximum input signal should be 3V less than the
supply voltages; The logic thresholds will remain TTL
compatible.

16000

""u,.'=

~

14000
12000
10000

8000

.

.+ 10V SIGNAL

600n

-10V SIGNAL

I

4000
2000
~ov

~5V

:!:15V

:t10V

Figure 12. rOS(On) vs Supply Voltages

IH5208 APPLICATIONS INFORMATION
+5V

Aoo--_-~

Alo--,-+-~

+15V

-15V

+15V

VOUTa

DECODE TRUTH TABLE

IH520a

EN

TTL/CMOS
INVERTER

VOUTb

Figure 13.

:2 01 16 channel multiplexer using two IH5208s.
Overvoltage protection and break·belore·make
. sWitching are extended to alrchannels.

ON
SWITCH
PAIR

A2

Al

Ao

a
a
a
a

a
a

a

1

1

2
3

1
1
1
1

1
1

a
1

4

a
a

a

5
6

1
1

1

a
1

7

8

D~DIL

IH5208
IH5208 APPLICATIONS INFORMATION (Cont.)
+5V
TT UCMOS INVERTER

Do--

Au
A,

TTLICMOS NOR GATE
A2

IH520B
EN

J

A.

I
"-

....

S~~'b

S~.

S!b

a

S,

~

S.

q,.

I'
I

r

[ s!.

S~~5b

1

I

S2

b

I....

I~

)Q.

S.

-.:.

Sab

a
IH520B

EN

.

-/

;

~

S'~~b

+15V

S,

.-c

S.

I
I
I

IN,
IN2

a
\

IH520B

EN

I

S'~b g..

s,~ J"b

S,'..

S2

b

S'~b q.

8~~

I
I....
I
I

S.

-L.r-

-·i

DECODE TRUTH TABLE
A3 A2 A,

Ao

ON SWITCH

ON SWITCH

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

S1a
S2a
S:ia
S4a
S5a
S6a
S7a
S8a
S9a
S10a
S11a
S12a
S13a
S14a
S15a
_ S16a

S1b
S2b
S3b
S4b
S5b
S6b
S7b
Sab
S9b
S10b
S11b
S12b
S13b
S14b
S15b
S16b

0
0
0
0
1

1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

VOUTa

VOUTb

Figure 14. submuiliplexed 2 of 32 system. The two IHS043s ere
overvoltage protected by the IHS208s. submultlplexlng
reduces output capacitance and leakage currents.

D.

1-15v

~

-lrV

'--'---

J)

r!!--

nD2

+r

+f

-lrV

~

r

I
I

i

~r--

~

IN2

"7
+lrV

VOltre

J

EN

J

D,

I

IN,

a
IH520B

?

...

IH5043 I

-15V

~
~f--

-

I

+15V

+15V

Y

-15V

+115V

D,

-1
D2

-J.

1-15v

VOUTh

U~UIL

IH5208
CHIP TOPOGRAPHY

Da

0_108"

S.4b
\

S3b

S2b

v+

Slb

-------0.111"

GND

-------1

3-142

IH61 08
8 Channel CMOS
Analog 'Multiplexer
FEATURES

GENERAL DESCRIPTION

• Ultra Low Leakage - ID(Off) :::; 100pA
• rDS(on) < 400 ohms over full signal and temperature
range
• Power. supply quiescent currentless than 100llA
• ±14V analog signal range
• No SCR latchup
• Break before make switching
• Binary strobe control (3 strobe inputs control 8
channels)
• TTL and CMOS compatible strobe control
• Pin compatible with DG508, HI-508 & AD7508

The IH610B is a CMOS monolithic. one of B multiplexer. The
part is a plug-in replacement for the DG50B. Three line
binary decoding is used so that the B chann!'lls can be
controlled by 3 strobe inputs; additionally a fourth input is
provided to use as a system enable. When theenable input is
high (5V) the channels are sequenced by the 3 line strobe
inputs, and when low (OV) all channels are off. The 3 sfrobe
inputs are controlled byTTL logic or CMOS logic elements, a
"0" corresponding to any voltage greater than 2.4V. Note that
the enable input (EN) must be taken to 5V to enable the
system and less than O.BV to disable the system.

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE
A2

Al

Ao

EN

ON SWITCH

x

x

x

a

NONE
1
2

a
a
a
a

Sl~
S2~

1
1
1
1

S3~

1

a

1
1

1

a

a
a

1

a

1
1

1

"a"

VOUT

0

EN
SWITCH

1
1
1
1
1
1
1
1

Ao. A1. A2
Logic "1" = VAH 2: 2.4V
Logic
= VAL::; O.BV

S4~
S5~

a

a
a

PIN CONFIGURATION

3
4
5
6
7
B
VENH 2: 4.5V

(Outline drawings DE. PEl

56

S7~

.--- r--

AD

EN []:

58~

V-[I

0! 01 l 0! l
I

Ao

Al

II....,

s,[]:
S2 [l

o

EN (ENABLE INPUT)

.

p:ru Al

iHl GND
illJ v+
~55

53 [[

Iru 56

[f

!lID 57

54

A2

0[[

.

I1ID A,

~58

3 LINE BINARY STROBE INPUTS
(1 o 1) ANO EN@5V
ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON .

. ORDERING INFORMATION

PART NUMBER
IH610BMDE

TEMPERATURE RANGE
-55°C to +125°C

IH610BCDE

O°C to 70°C

16 pin ceramic DIP

IH610BCPE

O°C to 70°C

16 pin plastic DIP

3·143

PACKAGE
16 pin ceramic DIP

.O~OIL

IH61
08
.',
'

ABSOLUTE MAXIMUM RATINGS

Current (Analog Drain) .....•.......•..........•. 20 mA
Current (Analog Source) .......................... 20 mA
Operating Temperature .................. --55 to 125°C
Storage Temperature .................... 115 to 150·C
Power Dissipation (Package)' ............. , ... 1200 mW
'All leads soldered or welded to PC board. Derate 10 mwrc above

VIN (A, ENltoGround '..... ,. '.......... : .... -15V to 15V
Vs or VD to V~ .......... , ........................ 0, -32V
Vs or VD to:V- . ;' .... ~: ................. : .... ,'... O,32V
V+ to Ground ..................................... 16V
V- to Ground ................... .' ................ -16V
Current (Any Terminal) .......................... 30 rnA

70°C.

Stresses above those listed under Absolute Maximum Ratings may cause permanentdamageto the device. These are stress ratings only. and functional operation of
the device at these or any other conditions atiove those indicated in the operational sections of the speCifications is not implied. Exposure to absolute maximum
rating condi\ions for e~tended periods may affect device reliability.
..
,

ELECTRICAL CHARACTERISTICS v+ ~ 15V v- = -15V

VEN

= +5Vl

Ground

NO
MAX LIMITS
CHARACTERISTIC MEASURED TESTS ,TYP
TERMINAL
PER
ZS·C
M SUFFIX
CSUFFIX
TEMP
;-5S'C ZS·C 12S'C O·C
ZS·C 70·.C

a.
a

Sto 0

rOSION)

lao
150·

300
300

300
300

400
400

. 350
350

350
350

TEST CONDITIONS

I

450
450

Vo - 10V. Is -:-1 ,OmA Sequence each switch on
Vo - -10V. Is - 1.0inA I VAL VAH - 2.4V

o.av.

(\

%

arOSlon) =

W
I
T IS(OFFI
C

S

a
a

H IO(OFFI

0

1
1

IO(ONI
I IAN(ONI or IA(on)
IA(oll)
N IAN(OFFI

p
U IA

A2

T

En
0
0
0
0
0

!transition

o topen
Y

on(En)

N ff(En)
A "OFF" Isolation
M
I .Cs(oHI

a
a

0
A-~~~~

OV

Your

3SpF

Vs, =-5V

Figure 3.

ton

and

to!!

Switching Test

IH6108 APPLICATION INFORMATION

tEnable Input Strobing Levels
The enable input on the IH6108 requires a minimum of+4.5V
to trigger to the "1" state and a maximum of +0.8V to trigger
to the "0" state. If the enable input is being driven from TTL

logic, a pull-up resistor of 1k to 3kO is required from the gate
output to +5V supply. (See Figure 4)

14 +5V lKD

DM7404N
TTL LOGIC

+3V

.2l!..fL.

VOUT

Figure 4. Enable Input Strobing from TTL Logic

3-145

O~OIL

IH6108
IH6108 APPLICATION INFORMATION (CO NT.)
When the EN input is driven from CMOS logic, no pullup is necessary, see Fig. 5.

+5V

figure 5. Enable Input Strobing from CMOS Logic

The supply voltage of the CD4009 affects the switching 'speed of the IH6108; the same is true for TTL supplyvolti;lge levels. The
chart below shows the effect, on ttrans for a supply varying from +4.5V to +5.5V.

CMOS OR TTL SUPPLY VOLTAGE
+4.5V
+4.7.5V
+5.00V
+5.25V
+5.50V

TYPICAL ttrans @ 25°C
400ns
300ns
250ns
200ns
175ns

The throughput rate can therefore be maximized by using a +5V to +5.5V supply for the Enable Strobe Logic ..

The examples shown in Figures 4 and 5 deal with enable strobing when expanding to more than eight channels is required; in
these cases the EN terminal acts as a fourth binary input. If eight channels or less are being multiplexed, the EN terminal can be
directly connected to +5V logic supply to enable the IH6108 at all times.

3-146

O~OIL

IH6108
IH6108 APPLICATION INFORMATION (CO NT.)
APPLICATIONS
II. Using the IH6108 with supplies other than
±15V
The IH6108 can be used with power supplies ranging from
±6V to ±16V. The switch rOS(on) will increase as the supply
voltages decrease, however the multiplexer error term (the
product of leakage times rOS(on)) will remain'approximately
constant since leakage decreases as the supply voltages are
reduced.

voltage in order to define a binary "1" state. For the case
shown in Figure 6 the EN voltage is 11.. 3V which means that
logiC high atAOand A1 is=+8.8V(logic low continues to be=
0.8V)' In this configuration the IH6108 cannot be driven by
TTU+5V) or CMOS (+5V) logic. It can be driven by TTL open
collector logic or CMOS logiC with +12V supplies.

Caution must be taken to ensure that the enable (EN) voltage
is at least 0.7V below V+ at all times. If this is not done the
binary input strobing levels will not function properly. This
may be achieved quite simply by connecting EN (pin 2) to V+
(pin 13) via a silicon diode as shown in Figure 6. When using
. this type of configuration, a further requirement must be met
- the strobe levels at·AO and A1 must be within 2.5V of the EN

If the logic and the IH61 08 have common supplies, the EN pin
should again be connected to the supply through a silicon
diode. In this case, tying EN to the logic supply directly will
not work 'since it violates the 0.7V differential, voltage
required between V+ and EN. (See Figure 7) A 1,.F.capacitor
can be placed across the diode to minimize switching
glitches. ,

Figure S. IH6108 Connection Diagram for less than ±15V

3-147

SuPPI~

Operation.

rg

IH61 08

O~OIL

IH6108 APPLICATION INFORMATION (CONT.)

IN914 OR ANY SILICON DIODE

m

16l-.....+ - , - - - : - - - - - - - - - - - - ! : E ! ! . N

Figure 7. IH6108 Connection Diagram with Enable Input Strobing for less than ±15V Supply Operation.

III. Peak-to-Peak Signal Handling Capability
The IH6108 can handle input signals up to ±14V (actually
-15V to +14.3V because of the input protection diode) when
using ±15V suppli.es.

The electrical specifications of the IH6108 are guaranteed
for ±10V signals. but the specifications have very minor
changes for ±14V signals. The notable changes are slightly
lower rD~(on) and slightly higher leakages.

3-148

IH6116
16 Channel
'CMOS Analog Multiplexer
(One out of 16)
FEATURES

GENERAL DESCRIPTION

•
•
•
•

The IH6116 isa CMOS monolithic, one of 16 multiplexer. The
part is a plug-in replacement for the DGS06. Four line binary
decoding is used so thatthe 16 channels can be controlled
by 4 strobe inputs; additionally a fifth inputis provided to use
as a system enable. When ,the enable input.is high (SV) the
channels are sequenced by the 4 line strobe inputs, and
when low (OV), all channels 'a're off. The 4 strobe inputs are
controlled by TTL logic or CMOS logic elements with a "0"
corresponding to any voltage less than 0.8V and a "1"
corresponding to any voltage greater than 3.0V. Note thatthe
enable input (EN) must be taken to 5V to enable the system
and less than 0.8V to disllble the system.

•
•
•
•
•
•

Pin compatible with DG506, HI-506 & AD7506
Ultra Low Leakage - 10(011) :S 100pA
±11 analog signal range
rOS(on) <700 ohms over full signal and temperature
range
Break before make switching
TTL and CMOS compatible strobe control
Binary strobe control (4 strobe Inputs control 16
channels)
Two tier submultiplexing to facilitate expandabillty
Power supply quiescent current less than'100J.lA
N,o SCR latchup

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

s,~o--'
S2~o--

::::h·
'~~il
S6~

"0--

s.~·

~o-•

s,
s,,"-'o--U

S13.~o-s,,~o--

EN

x

a

a
a
a
a

a
a
1
1

a
a

1
1
1
1

1
1

a
a
a
a

a
a

a
1
a
1
a
1
a
1
a
1
a
1
a
1
a

ON SWITCH

. NONE
1
1
1
2
1
3
1
4
1
5
1
6
,1
7
1
8
1
9
1
10
,11
1
1
12
1
13
1
14
1
15
l'
16
VENH ~ 4.5V

~

PIN CONFIGURATION (Outline drawings

S16~o-TO DeCODe LOGIC
CONTROLLING BOTH
TIERS OF MUXING

9 ~.
A,

Ao'

x

1
1
1
a
1
a
'1
1
1
1
1
Logic "1" = VAH ~ a.ov
Logic "a.. = VAL:; 0:8V

--~=_~~

YOUT

35pF

35pF

-=-

~A<10on.

II < lOOns

J

\'----,-~O.8V

O.BY

V

OUT

EN
I, < lOOns
It <0 lOOns

3V

o.sv

VS1=-2V

YOUT

ov
S10N

VSl == -5V

Figure 3

Figure 2

IH6116 APPLICATIONS
I. 1 out of 32 channel multiplexer using 2 IH6116s.

-15V

+15V

EN

-=-

IH6116

51

5"

Ao
AI
A,
A3

VOUT

A4

-15V,

+15V

TTL OR
CMOS
INVERTER
"::'

IH6116
EN
*TTL Inverter must have resistor
pullup to drive EN Input.

517

53'

DECODE TRUTH TABLE

A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Al
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
81
82
83
84
85
86
87
88
89
810
511
812
813
814
815
816

DECODE TRUTH TABLE

Figure 4

3-151

A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Al
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
817
818
819
820
821
822
823
824
,825
826
827
828
829
830
831
832

D~DlL

IH6116
IH6116 APPLICATIONS
II. 1 out of 32 cha'nnel multiplexer using 2'IH6116s; using an IH5041, for submultiplexing.

+15V

-15V

EN
':'

IH6116

' VL
+5V

'V,
+15V

5,
S,

Ao
A,

I

,IN,

A2
A3

,

IN,
+15V

D,

-=

IH6116

':'

EN

VA

S32 .-

YOUT

I

-15V

5,

TTL OR
CMOS
INVERTER

D,

J

V,
-15V

S17

A4
-TTL gate must have resistor
pullup 10 +5V 10 drive "EN" Input.

A4

As

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

1
, 1
1
1
1
1
1
1

DECODE TRUTH TABLE
A2
Al
Ao
ON SWITCH
0
0
0
81
1
0
0
82
1
0
83
0
1
0
1
84
1
0
0
85
1
0
1
86
1
1
0
87
1
1
1
88
0
89
0
0
0
1
810
0
0
811
0
1
1
1
812
0
1
0
0
813
1
0
1
814
1
815
0
1
1
816
1
1

A4
1
1
1
1
1
1
1
1
1
1
1
11
1
1
1

Figure 5

3·152

As
0
0
'0
0
0
0
0
0
1
1
1
1
1
1
1
1

DECODE TRUTH TABLE
A2
Al
Ao
ON SWITCH
817
0
0
0
0
0
1
818
0
1
819
0
1
1
0
820
1
0
0
821
1
0
1
822
1
823
1
0
1
1
1
824
0
0
0
825
0
0
1
826
0
1
827
0
0
1
1
828
1
829
0
0
1
0
1
830
1
1
0
831
1
1
1
832

,

O~OIL

IH6116
IH6116 APPLICATIONS
III. 1 out of 64 multiplexer using 4 1/165 anCl IH5053 as submultiplexer.

~"
,TTLI"CMOS" INVERTER

=D-

V,
+15V

VL
+5V

TTL/CM05 NOR GATE·

1

1
Ao
At
A2

Ao

IH6116
1 OUT OF 16
MUX

ENABLE

I

~

5t_

Ot

I

11 I

I

I I A~~L~G IIN~U+51

II

I

I

116

I

'INt

.J

IN2

1

Ao
At
A2

I

Ao

......

ENABLE

-""

·L

02

52

,

I

1"iT

.

IH6116
1 OUT OF 16
M,UX

171

I

1 I

1 ~N1LdGIIN~U+51

1 1 1 132

~

IH5053

Ao

"

At
A2
A3
ENABLE

1

IH6116
1 OUT OF 16
MUX

331

I

I I I ,I ~N~LdG ~N~u+sl I I I

148

53_

IN3

~

.,

IN4

Ao
At
A2

--r')
oTTL gate must have
puIlup reslslqr 10 drive EN

ENABLE

1

I
I

IH6116
1 OUT OF 16
MUX

Ao

491

1

I I 1 ~N~L~G IIN~U~51

Figure 6

3·153

03

I
I
I

1-

54

1 1 1 164

.gA

lV2
-15V

04

IH6116
IV. GENERAL NOTE ON EXPANDABILITY OF
IH6116

Bl

The IH6116 is a two tier multiplexer, where sixteen input
channels are routed to a common output in blocks of 4. Each
block of 4 input channels is routed to one common output
channel, and thus the submultiplexed system looks like 4
blocks of 4 inputs routed to 4 different outputs with the 4
outputs tied together. Thus 20 switches are needed to handle
the 16 channels of information. The advantage of this is
lower output capacity and leakage that would be possible
using a system with all 16 channels tied to one common
output. Also the expandability into 32, 64, 128, etc. is
facilitated. Figures 4, ~S, and 6 show how the IH6116 is
expanded.
Figure 4 shows a 1 of 32 multiplexer, using 21H6116s. Since
the 6116 is itself a 2 tier MUX, the system as shown is
basically a 2 tier system. The four output channels of each
6116 are tied together sothat 8 channels are tied to the Your
common point. Since only one channel of·information is on
at a time, the common output will consist of 7 OFF channels
and 1 ON channel. Thus the output leakage will correspond
to 7 IO(offs) and 1 IO(on), or about 1.0 nA of typical leakage at
room temperature. Thruput speed will be typically 0.81's for
ton and 0.31's for tott. Thruput channel resistance will be in
the soon area.
Figure S shows the 1 of 32 MUX of Figure 4, with a third tierof
submultiplexing added to further reduce leakage and output
capacity. The IHS041 has typical ON resistances 'of son
(max. is·7So) so it only increases thruput channel resistance
from the SOO ohms of Figure 4 to aboutSSO ohms for Figure S.
NOTE:

D~DlL
Thruput channel speed is a littfe slower by about O.Sl's for
both ON and OFF time, and output leakage is about 0.2 nA.
Figure 6 shows a 1 of 64 MUX using 3 tier MUXing (similar
to Figure S). The IntersillHSOS3 is used to get the third tier of
MUXing. The VOUT pOint will' see 3 OFF channels and 1 ON
channel at anyone time, so that the typical leakages will be
about 0.4 nA. Thruput channel resistance will be in the SSO
ohm area with thruput switching speeds about 1.31's for ON
time and 0.81'5 for OFF time.
The IHSOS3 was chosen as the third tier of the MUX because
it will switch the same AC signals as the IH6116 (typically
plus and minus 1SV) and uses break before make switching.
Also power supply quiescent cur~ents are on the order of 121'A so that no excessive system power is generated. Note
that the logic of the SOS3 is such that it can be tied directly to
the enable input (as shown in the figures) with no extra logiC
being required.

V. ENABLE INPUT STROBING LEVELS
The enable input (EN) acts as an enabling ordisabling pin for
the IH6116 when used as a 16 channel MUX, however when
expanding the MUX to more than 16 phannels, the EN pin
acts as another address input. Figures 4 and S show the EN
pin used as the A4 input.
For the system to function properly the EN input (pin 18)
must go to SV ±S% for the high state andless than 0:8V for the
low state. When using TTL logic, a pull-up resistor of 1kn or
less should be used to pull the output voltage up to SV. When
using CMOS logic, the high state goes to the power supply
so no pull-up is required.

This multiplexer does not require external resistors and/or diodes to eliminate what is commonly known as a latch up or SCR action.
Because of this fact. the rOS(ON) of the switch is maintained at specified values.

3·154

IH6201
Dual CMOS Driverl
Voltage Translator

U~UlL

FEATURES
• Driven direct from TTL or CMOS logic
• Translates logic levels up to SOY levels
• Switches 20VACPP signals when used in conjunction
with Intersil IH401A Varafet (as an analog gate)
• tON :5 300nS & tOFF :5 200nS for 30V level shifts
• Quiescent supply current :5100J.la for any state (d.c.)
• Provides both normal & inverted outputs

GENERAL DESCRIPTION
The IH6201 is a CMOS, Monolithic, Dual Voltage Translator;
it takes the low level TTL or CMOS logic level and converts
them to higher levels (i.e. to ±15V swings). This translator is
typically used in making solid state switches, 'or analog
gates.

BLOCK DI.AGRAM
+5V

When used in conjunction with the Intersil IH401 family
Varafets, the combination makes a complete solid state
switch capable of switching signals up to 22Vpp and up to
20MHz in frequency. This switch is a "break-before-make"
type (i.e. toft time < ton time). The combination has typical toft
:'" 80nS and typo ton ~ 200nS for signals up to 20Vpp in
amplitude.
A TTL "1" input strobe will force the 8 driver output up to
V+ level; the 0 output will be driven down to the-V-Ievel.
When the TTL input goes to "0", the 8 output goes to V- and
if goes to v+; thus 8 and 'if are 180° out of phase with each
other. These complementary outputs can be used to create a
wide variety of functions such as SPDT and DPDT switches,
etc.; alternatively the complementary outputs can be used to
drive an Nand P channel Mosfet, to make a complete Mosfet
analog gate ..
The driver typically uses +5V and ±15V power supplies;
however a wide range of V+ and V- is possible, however
V+ > 5V is necessary for the driver to work properly.

SCHEMATIC DIAGRAM (ONE CHANNEL)

DRIVER

+5V

OUTPUT
0,

ii,-

DRIVER
OUTPUT
02

-::-

ij,
V+

4k

PIN CONFIGURATION

DRIVER

. OUTPUT

lk

+---0

LOGIC
STROBE

DRIVER
OUTPUT

ii

OUTLINE DWGS
DE, JE, PE

ORDERING INFORMATION
PART NUMBER
'IH6201CDE
'IH6201MDE
IH6201CJE
IH6201MJE
IH6201CPE
'Special Order Only

V-

TEMPERATURE RANGE
O°C to 70°C
-55°C - +125°C
O°C to 70°C
-55°C to 125°C
O°C to 70°C

3·155

y-

r&l

IH6201
ABSOLUTE MAXIMUM RATINGS
v· to V- ........................ ; ....................
V· ............................... ; ..................
V- ..................................................
v· to VIN ..... : .................................. , ....

35V
35V
35V
40V

Operating Temperature. . . . . . . . . . . . . .. - 55·C to + 125·C
Storage Temperature. . . . . . . . . . . . . . . .. - 65·C to + 150·C
Lead Temperature (Soldering 10 sec) ............... 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL SPECIFICATIONS V+

(J

or

(J

ITEM
driver output swing

= +15V, V- = -15V, VL = +sv

CONDITIONS
+3V
fig. 28
VIN=OV...r-L

VIN strobe level ("1 "I for
proper translation

(j ~ -14V

VIN strobe level ("0"1 for
proper translation

(j ~ 14V

liN input strobe current draw
(for OV - SV rangel

(J ~

()

~

14V
-14V

VIN = OV or +SV

IH6201MDE
IH6201CDE
-25°C +25°C +85°C -55°C +25~C +125°C UNITS
28
28
28
Vpp
28
28
28
3.0

3.0

3.0

2.4

2.4

2.4

VD.C.

0.4

0.4

0.4

0.8

0.8

0.8

VD.C.

1

1

1

1

1

1

,.,A

ton time

V---oV,

+ 15V

V

I

__________~~r--

-15
+15

-15V

OV

-15V
TRANSLATOR

Figure 2A
NOTE:

Each translator output has a (J and OO\.ltpul.

Figure 2B
(J

is just the inverse of

0.

A very useful feature of this system is that one-half of an IH6201 and one-half of an IH401 can combine to make a SPDTswitch,
or an IH6201plus an IH401 can make a dual SPOT analog switch. (See III.)

I. Dual SPST Analog Switch

II. DPDT Analog Switch
(

NOTE: Either switch is turned on when strobe input goes high.

3·157

rfl

IH8201
APPLlCATJONS.

CONTINUED
IV. Dual DPST

III. Dual SPDT

/

3-158"

IH6208
4·Channel Differential
CMOS Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Ultra low leakage - ID(oll) ::; 100pA
.' rDS(on) < 400 ohms over full signal and temperature
range
• Power supply quiescent current less than 100/LA
• ±14V analog signal range
•. No SCR latch up
• Break before make switching
• Binary strobe control (2 strobe inputs controls 2 out
of 8 channels).
• TTL and CMOS compatible strobe control
• Pin compatible with H1509, DG509 & AD7509

The IH620B is a monolithic 2 of B CMOS multiplexer. The part
is a plug-in replacement' for the DG509. Two line binary
decoding is used so that the B channels can be controlled in
pairs by the binary inputs; additionally a third input is
provided to use as a system enable. When the enable input is
high (5V) the channels are sequenced by.the 2 line binary
inputs, and when low (OV) all channels are off. The 2 strobe
inputs are controlled by TTL logic or CMOS logic elements
with a "0" corresponding to any voltage less'than O.BV and a
"1" corresponding to any voltage greater lhan 2.4V, Note that
the enable input (EN) must be taken to 5V to enable the
'
system, and less than Q,BV to disable the system,

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

Sl.

S2a~

Ao

EN

X

X

a
a

a

a

Al
~

S3a~

S4a~

EN SWITCH
I
I

\

1
1
I

1
1
1
1

1
0
1

ON
. SWITCH
PAIR
NONE
1a, 1b
2a, 2b
3a, 3b
4a, 4b

0,

I
I
I
I
I

Slb

Ao, Al

02

I
I

LOGIC "1"
LOGIC "0"

S2b~

VENH 2': 4,5V

>--

S3b~

PIN CONFIGURATION

S4b~

Ao

R8

o EN

~SV

At

2 LINE BINARY STROBE INPUTS
(00) AND EN ~ SV (EN ~ "1" FOR +SV, "0" FOR OV)
ABOVE EXAMPLE SHOWS CHANNELS 1. & lb ON.

(Outline drawings DE, PEl

........ ,...- ~

II • ....,

EN [3:

Ao

= VAH 2': 2.4V
= VAL:::; O,8V

Al

~

GNO

v-I]:

~

v+

Sla [!

TIl

Slb

S2a [[

~ S2b

S3a J:§:

TIl

S3b

S4a

IT

1liI

S4b

01

[i

]:I

02

"

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

IH6208MDE

--55° C to +125° C

IH6208CDE

O°C to 70°C

PACKAGE
16 pin Ceramic DII'
16 pin Ceramic DIP

IH6208CPE

O°C to 70°C

16 pin Plastic DIP

3-159

-

'D~DIL

IH6208
ABSOLUTE MAXIMUM RATINGS

Current (Analog Drain) .......................... 20 rnA
Current (Analog Source) ........................ 20 rnA
Operating Temperature ................... -55 to 125°C
Storage Temperature .................... -65 to 150°C
Power Dissipation (Package)' ................. 1200 mW
•All leads soldered or welded to PC board. Derate 10 mW/o C above

VIN (A, EN) to Ground ... ; ..................... -15V; V1
Vs or Vo to v+ ................................. 0, -32V
Vs or Vo toV- .. : ............................... 0, 32V
V+ to Ground ..................................... 16V
V- to Ground ......... , .................... ,..... -16V
Current (Any Terminal) .......................... 30 rnA

70°C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device:. These are stress ratings only, and functionaroperation of
the device at these or any other conditions above those indicated in the operational sections of the specifications is· not implied. Exposure to absolute maximum
rating condi.tions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS v+ =

15V,

v- =·-15V,

VEN = +5V1, Ground = OV, unless 'otherwise specified.

NO
CHARACTERISTIC MEASURED TESTS TYP
MAX LIMITS
TERMINAL
PER
25'C
M SUFFIX
C SUFFIX
25°C 70'C
TEMP
-5S o C 2S'C 12S'C O'C
S.to 0

rOSION)

0

IO(ON)

0

S

I IA(on)
N IAloll)
P
U IA
T

Y
N
A
M
I
C

180
150

300
300

300
300

400
400

350
350

350
350

450
450

20

S tHosION)
W
I
T IS(OFF)
C
H 10(OFF)

0

8
8

TEST CONDITIONS
UNIT

8
8
2
2
8

0.002
0.002
0.03
0.03
0.1

0.05
0.05
0.1
0.1
0.2

8

0.1

0.2

2
2

.01

10
10

.01

50
50
50
50
50
50
30
30

'0.1
0.1
0.2'
0.2
0.4
10
10

-30

-30

-10
-10

-30

OA

50
50
100
100
100
100

n

Vo = 10V, Is = -1.0 mAJSequence each switch on
Vo - -10V, Is - -1.0 mAl VAL =0.8V. VAH =2.4V

%

6ros{on') =

Vs
Vs
NA Vo
Vo

EN

ttrans

0

t open

iJ

tEN(on)

tEN(oll)
"OFF" Isolation

0
0
0

Cs(off)

S

Gdloff)

0

0.3
0.2
0.6

OA

30

+

I'

-30

-30

1
1.5
1

~s

60

dB

5
12

pF

1

o toS

Cds(off)

S Supply

-10
-10

2
1

1

40

U Current
11
2
P
P Standby
1
1
+
I'S8
L
Current
1
I-58
1
Y
NOTE ,1. See Section I Enable Input Strobing Levels.

-

rDS(on)avg.

10V Vo - -10V
-10V. Vo = 10V
10V. Vs - -10V
-10V. Vs - 10V
V~,,- Vo = 10V
Vs All) - Vo - -10V
VA - 2AV or OV
VA-15VorOV

~A

AO, A1

rDS(on)max - rOS(on)min

=
-

Vs = ±10V

VEN = 0
Sequence each switch on
VAL =0.8V, VAH =2.4V

,

VEN
VEN
See
See
See

= 5V
- 0
Fig. 1
Fig. 2
Fig. 3

All VA = a
IIStrobe Pins),

VEN = O. RL = 20011, CL = 3 pF. Vs =,3 VRMS,
f = 500 kHz
Vs = 0
Vo = a

VEN = 0, f = 140 kHz to
1 MHz

Vs = 0. Vo - 0
1000

200
100

1000

100

1000

100

1000

VEN = 5V
All VA = 0 OR 5V

~A

VEN = 0

SWITCHING INFORMATION
3.0V
1.4V
O.BV

VSlO
O.9VSlb

~

. 51.
52.
53.
S4.
51b '
52b
S3b

_ _ _--'

1-----""

VA

-=

':'

-= -= .

S4b
IH6208

EN
02
O.9VS4b
VS4b

PROBE IMPEDANCE
Rp;:: 1Mn
Cp s; 30pF

ttrans

Figure 1. Itrans Switching Test

3·160

O~OIL

IH6208
,

VA

+3.0V

~--_- __ ~D!!'____

--i.. .______
I

tA-- tft'' '

1i:O~~;J

+15V

L"T"'__-rJ~~T=::-:r:~VOUT
35pF

Figure 2. topen <8reak-8efore-Make< Switching Test

+5V

VEN.

tr &l!:5100ns·

Z

I : _____

~

I

._~!'______~
: ....- - - - - -

+15V

tEN(ofl)

DV ~----t-~--~----~~-t--~~----­

r----~

D.1Vo

__~~S~lb~----~-5V

IH6208

SWITCH OUTPUT
Your
(SEE FIG. 3)

-r__r-ifi-r----r-<>VOUT

L..,..__

35pF
D.9VO
Vo

-5V

Figure 3. ton and toll Switching Test

IH6208 APPLICATION INFORMATION

I. Enable Input Strobing Levels
The enable input on the IH6208 requires a minimum of +4.5V
to trigger it into the ·"1" state and a maximum of +0.8V to
trigger it into the "0" state. If the enable input is being driven

14 +5V

from TTL logic, a pull-up resistor of 1k to 3kO is required
from the gate output to +5V supply. (See Figure 4),

1K

DM74D4N
TTL LOGIC
+3V

~

Figure 4. Enable Input Strobing from TTL Logic

3-161

O~OIl,

IH6208
IH6208 APPLICATION INFORMATION (CO NT.)
When the EN input is driven from CMOS logic, no puliup is necessary. (See Fig. 5)
+5V·

Figure 5

The supply voltage of the CD4009 affects the switching speed of the IH6208; the same is true for TTL supply voltage levels. The
chart below shows the effect on ttrans for a supply varying from +4.5V to +5.5V.

CMOS OR TTL SUPPLY

TYPICAL ttrans @ 25° C

+4.5V
+4.75V
+5.0V
+5.25V
+5.50V

400ns
300ns
250ns
200ns
175ns

-

The·throughput rate can therefore be maximized by using a +5V to +5.5V supply for the Enable Strobe Logic.

The examples shown· in Figures 4 and 5 deal with enable strobing when expanding tei more than four differential chal)nels is
required; in these cases the EN terminal acts as a third binary input. If four channel pairs or less are being multiplexed, the EN
terminal can be directly connected to +5Vto enable the IH6208 at all times.

3-162

IH6208
IH6208 APPLICATION INFORMATION (CO NT.)
APPLICATIONS
II. Using the IH6208 with supplies other than
±15V
The IH620B can be used with power supplies ranging from
±6V to ±16V. The switch rDS(on) will increase as the supply
voltages decrease, however the multiplexer error term (the
product of leakage times roS(on» will remain approximately
constant since leakage decreases as the supply voltages are
reduced.

2.5V of the EN voltage in order to define a binary "1" state.
Forthe case shown in Figure 6the EN voltage is 11.3V, which
means that logic high at AO and A1 is = +B.BV (logic low
continues to be = O.BVL In this configuration the IH620B
cannot be driven by TTL H5V) or CMOS (+5V) logic. It can be
driven by TTL open collector logic or CMOS logic with +12V
supplies ..

Caution must be taken to ensure that the enable (EN) voltage
is at least O.7V below V+ at all times. If this is not done the
binary input strobing levels will not function prpperly. This
may be achieved quite simply by connecting EN (pin 2) to v+
(pin 14) via a silicon diode as shown in Figure 6. A further
requirement must be met when using this type of
configuration; the strobe levels at AO and A 1 must be within

If the logic and the IH620B have common supplies, the EN pin
should again be connected to the supply through a silicon
diode. In this case, tying EN to the logic supply directly will
not work since it violates the O.7V differe. ntial voltage
required between V+ and EN (See Figure 7). A 11'F capacitor
can be placed across the diode to minimize switching
glitches.
.

IN914

IH620a

I'" "'"~'"' ,,~
+12V

•

'"~'" ""'~

'''= (

A CHANNELS
COMMON DRAIN OUTPUT

= 0,

1

...._ _ _ _ _.....

9 02

= B CHANNEL DRAIN OUTPUT
(COMMON)

Figure 6. IH620B Connection Diagram for less than ±15V Supply Operation.

3-163

rf]

O~OIb

IH6208
IH6208 APPLICATION INFORMATION

IN914

I
I

I
1

..

"'-"'!~-...1

16~~~__________________________~E~N~

CD4009A

Figure 7. IH6208 Connection Diagram with Enable Input Strobing for less than ±15V Supply Operation.

III. Peak-to-Peak Signal Handling Capability
The IH6208 can handle input signals up to ±14V (actually
-15V to +14.3V because of the input protection diode) when
using ±15V supplies.

The electrical specifications of the IH6208 are guaranteed
for ±10V signals, but the specifications have very minor
changes for ±14V signals. The notable changes are slightly
lower rDS(on) and slightly higher leakages.

3-164

IH6216
a·Channel Differential
CMOS Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Pin compatible with HI507, DG507 & AD7507
• ± 11V analog signal range
• rDS(on) < 700 ohms over full signal and temperature
range
• Break before make switching
• TTL and CMOS compatible strobe control
• Binary strobe control (3 strobe inputs controls 2 out
of 16 channels).
• Two tier submultiplexing to facilitate expandability
• Power supply quiescent current less than 100/-LA
• No SCR latch up
.
• Very low leakage ID(off) :S 100pA

The IH6216 is a CMOS monolithic 2 of 16 multiplexer. The
part is a plug-in replacement for the DG507. Three line
binary decoding is used so that the 16 channels can be
controlled in pairs by the binary inputs; additionally a fourth
input is provided to use as a system enable. When theenable
input is high (5V) the channels are sequenced by the 3 line'
binary inputs, and when low (OV) all channels are off. The 3
strobe inputs are controlled by TTL logic or CMOS logic
elements with a "0" corresponding to any voltage less than
0.8V and a "1" corresponding to any voltage greater than
3.0V. Note that the enable input (EN) must be taken to 5V to
enable the system and less than 0.8V to disable the system.

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

52.0---"
".~~~
53.0---"

b:::::3Lb ·
~-

55.~

52b~~J

j

A1

X
0
0
0
0

x
0
0
1

1
1
1

5a.0---"

51b

A2

1

x

a

0

1
1
1
1
1
1
1
1

NONE
1
2
3
4
5
6
7
8

1

0
0
1
1

LOGIC "1"
LOGIC "0"

0,

53b~O---

SWITCH
PAIR

0
1
0
1
0
1

1

~
~

ON

EN

Ao

VAH > 3V VENH > 4.5V
VAL < O.BV

,

54.~O---

55b~O---

PIN CONFIGURATION

(Outline drawings 01, PI)

5•• ~O--57.~O---

~

.;~r.-r-~.

5a.~<>---

02

2

27

NC 3

TO DECODE LOGIC
CONTROLLING BOTH

5a:i
S7b 5

TIERS OF MUXING

56b 6

~~ ~
Ao

Al

25

o

EN

"21 54.
S3a
.

51.
GN1i

Ne 13

NC 14

15 A2

11

A2

3 LINE BINARY STROBE INPUTS
(000) AND EN"" 5V
ABOVE EXAMPLE SHOWS CHANNElS 1a & 1bON.

20 S2a

m
lEN
"

S2~1

'5V

57.

24 SSa
23 SSa

55:
S4b ~
a
S3b 9

v-

26 SSa

S1a

16 Ao
A1

TOP VIEW
V1 COMMON TO SUBSTRATE

,.
ORDERING INFORMATION
PART NUMBER
IH6216MDI
IH6216CDI
IH6216CPI

TEMPERATURE RANGE
-55°C to +125°C
O°C to 70°C
O°C to 70°C

3-165

PACKAGE
28 pin Ceramic DIP
28 pin Ceramic DIP
28 pin Plastic DIP

1:1
a

IH6216
ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground ............. ;.: .......... -15V, Vl
Vs or Vo to V+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0, -32V
Vs or Vo to V- .................................. 0, 32V
V+ to Ground ..................................... 16V
V- to Ground .................................... -16V
Current (Any Terminal> ........................... 30 mA
Current (Analog Drai~) ........................... 20 mA

CurrenUAnalog Source) ......................... 20 inA
Operating Temperature .................... -55t0125°C
Storage Temperature ...................... -65t0150°C
Power Dissipation (Packager .................. 1200mW
Lead Temperature (Soldering 10 sec) .............. 300·C
• All leads soldered or welded to PC board. Derate 10 mW/· C above
70°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tathe device. These are stress ratings only, and functiohal operation of
the'device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS v' = 15V. V- =-15V,
CHARACTERISTIC

MEASURED TESTS

TYP

TERMINAL

25°C

PER
TEMP

S to 0

rOSION)

VEN = +5Vl. Ground = OV, unless otherwise specified.
TEST CONDITIONS

NO

480
300

16
16

MAX LIMITS

UNIT
C SUFFIX

M SUFFIX
-55°C

25°C

125°C

O°C

25°C

70 0 e

600
600

600
600

700
700

650
650

650
650

750
750

I

Vo;:::;: 10V, Is - "-10mA Sequence each switch on

II

I
S .lrOSIONI

20

%

Vo ..l

10V. Is _. 10mA I VAL =0.8V. VAH =3V

rOS(on) ::::

W
I
T Is OFF
C
H 10 OFF)

S

0

D

1010N)

I

IAJon}or
N IA(oft)

P

Ao A,

U IA
T

A2 A3

EN

to pen
Y ton(En)

0

N tolf(En)

0
.

S

C Cd(off)

D

Cos

+

S Supply
U Current

P
P Standby
L
Y Current

-

+
-

Oto S
I'
1- .
1'58
I 58

0.1
0.1
0.1
0.1
.01
.01

0.6
.0.2
0.8
0.3
60

0

MC
I
S

om

50

0.1
0.1
0.2
0.2
0.2
0.2
10
10

50
50
100
100
100
100
30
·30

0.2
0.2
0.4
0.4
0.4
0.4
10
10

50
100
100
100
100
30
30

-10
-10
1

-30
-30

-10
-10

-30
-30

Vs
Vs
nA Vo
Vo

=
-

10V. Vo - -10V
-10V. Vo - 10V
10V. Vs - lOV
-10V. Vs - 10V

VEN

~

0'

Sequence each switch on

VS(Atl) - Vo -- 10V

=

VSIAIII Vo -- 10V
VA ~ 3.0V
VA ~ 15V

VAL =0.8V. VAH

~3V

"A

0

"OFF" Isolation

0.01

3
1

0

ttrans

o
A

16
16
2
2
16
16
3
3

rOS(on)max - rOS(on}mm
Vs = ±10V
rDS(on}avg

1.5
1

"5
dB

5
20

1
1
1
1

1
55
2
1
1

pF

VEN
VEN
See
See
See

1000
1000
1000
1000

O. Vo

~

0

i

20011. CL

VEN - O. RL
I ~ 500 kHz
Vs - 0
Vo = 0
VS

200
100
100
100

All VA

= 5V
- 0
Fig. 1
Fig. 2
Fig. 3

3 pF. Vs

VEN = 0.1
1 MHz

3 VRMS.

= 140 kHz to

0

VEN = 5V
All VA = 0 OR 3V

"A
VEN = 0

NOTE 1: See Section V. Enable Input Strobing Levels.

SWITCHING INFORMATION
3.0V

.51
52
53
S4
55
56
57

58
51b

52b
53b

54b
55b
S5b
57b

58b

.'

Rpe·
"

;*:CP
I

. . --:.'I:- ~ROBE IMPEDANCE
--

Rp;;: 1Mn

Cp::; 30pF

3-166

IH6216
OPEN
+15V

VAEF

-D

SWITCH OUTPUT
Yo

r~--------~1-~S1~'____~__

"2Y

(SEE FIG. 2)

S2b
THRU
S7b

-=-

S8b

L..,...________...,...r-g;j:---T-D
D2

YOUT

3SpF

-=-

Figure 2
OPEN
t15V

YREf

S1b
O.lYO

ALL OTHERS

A2

SWITCH OUTPUT
Yo
(SEE FIG. 3)

-5V

-=YOUT

O.9Yo
Yo
Ys

-=-

-=-

Figure 3

IH62j APPLICATIONS
I. 2 out of 32 channel multiplexer using 2 IH6216s.
+15V

-15V

I

J

Ao
A.
A2

TTL·/CM

INVERTE~5

IH6216

r--

k~----~;-~ ~~b---~-S;~

'1

EN

L~

~VOUT1

-15V

+15V

I

f--o VOUT2

\

r--

'----

IH6216

EN

1-------\ \-------\
59.

516.

59b

S16b

~

"'TTL gate must have pullup 10 drive EN

Figure 4
DECODE TRUTH TABLE'

DECODE TRUTH TABLE

A3
0
0
0
0
0
0
0
0
1
1
'1
1
1.
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0

1
1
1
1

A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
S1a
S2a
S3a
S4a
S5a
S6a
S7a
S8a
S9a
S10a
S11a
S12a
S13a
S14a
S15a
S16a

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Voun

3-167

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
S1b
S2b
S3b
S4b
S5b
S6b
S7b
S8b
S9b
S10b
S11b
S12b
S13b
S14b
S15b
S16b

VOUT2

D~DlL

IH6216
IH6216 APPLICATIONS
II. 2 out of 32 channel multiplexer using 2 IH6216s; with an IH5043 for submultiplexing.

+5V

'-15V .

1+15V

Ao o------ 1000 Mn

•

FET Input for-Zin

•

Auto-Zero Minimizes Effects of Offset, Drift and Tem·
perature

The PMOS LD110/LDl14 synchronous digital processor
combines the counting, storage and data multiplexing
functions with the random logic necessary to control the
quantized charge-balancing function of the analog processor.
Seventeen static latches store the 3% digits of BCD data as
weU as overrange, underrange and _polarity information.

• Auto-Polarity
•

Multiplexed Parallel BCD or Serial BCD OutPllt (LDl14!'

• Active High or Active Low Logic Outputs (LDl14)
• Overrange and Underrange -Signals Available for Auto·
Ranging Capability.

In the LD110, nine push-pull output buffers (capable of
driving one standard TTL load each) provide the sign, digit
strobe and multiplexed BCD data outputs, all of which are
active high. The -digit scan is an interlaced format of digits
1,3,2, and 4.

• + 512 Output Available for Phase Locked Loop Clock
.(LDl14)
•

TTL Compatible Outputs

\

In theLDl14, ten push'pull output buffers (capable of
driving one standard TTL load) provide the clock frequency +512, sign, digit strobe' and multiplexed BCD data.
Four data output format options allow the user to tailor
the BCD output to his circuit requirements.

GENERAL DESCRIPTION
The monolithic LD111 analog processor contains a bipolar
comparator, a bipolar integrating amplifier, two MOS·FET
input unity gain amplifiers, ~everal P-channel enhancement

LD111
ANALOG PROCESSOR

LD110
_DIGITAL PROCESSOR
v+

SIGN

VREF

------ -----BCD OUTPUT

DIGIT STROBES

6, B2 63 B4

,01 0203 0 4

LD114
DIGITAL PROCESSOR
PARALLEL

DIGIT

~~aIT~

iii th 82 BJ 84 PHASE D1 02 03 04

UID
OND
COMP

Mil

10
AZ FilTER

AZOUT

Mil

v-

CLOCK

OND

IN

.,·2

...·3

NC

GND

NC

SIGN
NC
DIGIT PHAse

ORDER
NUMBER
L0111CJ·PLASTIC

lDtllCp·CEAAMIC

TOP VIEW

ORDER
NUMBER

L0110CJ·PLASTIC
LD111CP·CERAMIC

TOP VIEW

4-4

ORDER
NUMBER
LDI14CR-CEAAM1C

ABSOLUTE MAXIMUM RATINGS

V1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.0V
V++- V- (LDlll) ........................• 30V
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . , ........ 6V
V+ - V- (LDll0/LDl14) ................... 20V
Voltage on any pin relative to V+ (LD114) .. 0.3V to -20V
VREF . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . V++

Operating Temperature . . . . . . . . . . . . . . . . . . 0 to 70°C
Si:orage Temperature . . . . . . . . . . . . . . . -65°C to 150°C
Power Dissipation (Package, LDll0/LDlll)*, .... 750mW
Power Dissipation (Package, LD114)* . ....... 1200mW
*Device mounted with all leads' welded or soldered to PC
Board, Derate 6.3 mW/"C above,25°C.

ELECTRICAL CHARACTERISTICS v++ = 12V, v+; 5V, V- = 5V, VREF = 8.2V, TA = 25°C.
PARAMETER

I
N
P
U"
T

0
U
T
P
U
T

SYMBOL

MIN

CONDITIONS

Clock Frequency

fiN

50% Duty Cycle

Input Bias Current

liN

TA = 25° C

4

TA = 70° C

40
40

NMR

fL =60Hz

ICL

VCLOCK in = 0,4 N

Comparator

IINL

VINL = -12 V

-

-100

Latch Inhibit

IINL

VINL= -12 V

180

·600

25

400

Format Option Inputs

IINH

VINH = VSS

VOLl

IOL= 15O fJ. A

Measure/Zero Voltage, High

VOHl

lOr! = -200fJ.A

Up/Down Logic Voltage, Low

VOL2

10L = 250fJ. A

Up/Down Logic V,oltage, High
Digits, Bits, Sign Voltage,7S12*

VOH2

10H = -200fJ.A

VOL3

10L = 1.6 mA

dB
-500
fJ.A

0,4
2,4
0,4
2,4

V
0,4

Analog Comparator Voltage

VOH3

10H = -100fJ.A

2,4

Data Bit Voltage, High

VOH4

10H = -200fJ.A

2,4
2,4

VOH5

10H = -800fJ.A

rDS(on)

V AZ(in) = -4.0 V, IS = -50 fJ.A

I

ON Resistance, Up/Down Switch

rDS(on)

IS = 1 mA

T

Up/Down Switch Temperature

C

pA

Normal Mode Rejection

Measure/Zero Voltage, Low

UNIT
kHz

Clock Input Current, Low

Digits, Sign Voltage, 7512*

W

MAX

30.7

ON Resistance, Auto Zero Switch

S

TYP

11

50

kr2

650

3000

n

TC

0.20

0.50

%/oC

2.2

3.5

-1.8

-3.0

Supply Current, LOll 0/114

1++
1A
ID

-17

-23

Supply Current, LDll0/114

1+

17,4

24

H

Coefficient

S
U
P
P
L
Y

Supply Current, LDlll

Supply Current, LDlll

Power Supply Rejection Ratio, V++ PSRRl

80

85

Power Supply Rejection Ratio, V- PSRR2

60

65

35

41

Reference Current Rejection Ratio

RREF = R2 = 100K,Q, VIN= 2V

mA

dB
nA/LSB

*7512 output applicable to LDll4 only

INPUT/OUTPUT SCHEMATICS

d

Ll?l
~
':"

't;i f--

v'

Vo

j

OUTPUT BUFFERS
(Digits, Bits, Sign,,512, MfZ, UfO)

lIN

-["1

t

-V2

[>0-'

VIN

J.

.

J.,'~
~

[>0-

v'

COMPARATOR,CLOCK,LATCH
INHIBIT INPUTS
4-5

FORMAT OPTION INPUTS
(Bit Phase, Digit Phase, Scan, Serial Bits)

DESCRIPTION OF PIN FUNCTIONS (LD110/LD114)
BIT PHASE (*LD114) - The bit outputs will be active high
(positive) logic if this pin is left open or connected to V-.
The application of V+ to this pin will give a complemented
output (negative logic).

v+ - Positive Supply Voltage. Recommended level is +5
volts ± 10%.
V- - Negative Supply Voltage. Recommended level is -12
volts ±10%.

DIGIT PHASE (*LD114) - The DigitStrobe outputs will be
of positive logic if this pin is left open or connected to V(an active pull-down is internally connected to V-). Applying V+to this pin will complement the outputs to give
negative logic. Negative logic may simplify interfacing with
Common Anode LED, Gas Discharge and Liquid Crystal
Displays.

CLOCK IN - This input accepts a TTL or MOS level clock
to drive the synchronous digital circuitry. Acceptable duty
cycles on the external clock range from 30% high, 70% low
to 70% high, 30% low for clock frequencies from 2 kHz to
75 kHz. Although any clock frequency between 2 kHz and
75 kHz may be used, clock frequencies that are integer divisions of 2048FL (FIN = 2084FL/n, n = 2,3, 4,51, FL = Line
Frequency) provide measure and zero periods that are integer multiples of the line frequency period (T zero = n/Flo
T measure = 2n/F U. Line frequency interference is minimized by the selection of one of these 50 frequencies.

B1, B2, B3, B4 - BCD Data Bit Output. B4 represents the
most significant bit and Bl the least significant bit of the
BCD output. Bit 4 of digit 4 goes high for an underrange
condition (less than 100 counts). These outputs are compati ble with 1 standard TTL load.

This input has an active pull-up to V+.
M/Z - Measure/Zero Logic Output. This 0 to 5 volt logic
output successively provides Autozero and Measurement
intervals of 2048 and 4096 clock periods respectively. This
output is compatible with CMOS logic arid directly interfaces with the LD 111 analog processor.

MUX Underrange = B4 . D4 (5% of full scale)

D1, D2, 03, D4 - Digit Strobe Outputs. D4 is the most
significant and D1 the least significant digit of the 3% digit
output. The digit strobes are each selected in turn when the
BCD data bits for that digit appear at the bit outputs.

+512 (LD1,14) - This TTL compatible output (1 standard
load) provides the necessary clock frequency division for a
phase locked loop digital clock. The line frequency rejec, tion will be held at the maximum level (>80 dB) when
locked to the line frequency.

MUX Overrange = D1 + D2 + D3 + D4 (100% of full scale,
count;;' 2000).

SCAN (*LD114) - Sequential/Interlace Digit Scan. The
digit strobe format will be an interlaced format of digits 1,
3,2 and 4 if this pin is left open or is connected to V-. This
format is useful for. display digits packaged two to an
envelope and which require an interdigit blanking period ego
(Beckman Displays). By alternating' from envelope, an
interdigit blanking period is effectively provided.

U/D - Up/Down Logic Output. This output has logic levels
of 0 to +5 volts to provide pulse-width modulation of the
reference current when used with the LDlll analog pro:
cess or. This output is CMOS compatible.
COMP - Analog Comparator Input. This input has an active
pull-up to V+ for a comparator "high" state. This pin must
be pulled down to V- for a "low" comparator state.

The application of V+ to this pin will give a sequencia I scan
of digits 1, 2, 3 and 4. This format may be more useful in
interfacing with data acquisition equipment.

An End-of-Conversion Signal can be decoded from the three
interconnecting logic lines (M/Z, U/D, Comp) using the
following CMOS logi.c.
M/Z + U/D + Comp = E.O.C.

LATCH INHIBIT (*LD114) - Connecting this pin to V2
will prevent updating of the internal static latches, thus
providing a "hold" function. Leaving this pin disconnected
will allow the latches to be updated once each sampling
period.

SIGN - Sign of Analog Input Polarity. This TTL level output is a static signal which is either 0 or V+ for a negative
or positive input polarity respectively.

4-6

DESCRIPTION OF PIN FUNCTIONS (LDll0/LDl14) Cent.
SERIAL BITS (*lD114}-Paraliel/Serial Bit Output Format.
The BCD data bits for each digit will appear simultaneously
with the digit strobe if the parallel bit option is selected.

UfD - Up/Down Logic Input. The logic signal applied to
this pin operates a SPOT switch to provide Quantized
pulses of charge to the integrator.

This format is useful for driving multiplexed displays. The,
parallel bit format is available when this pin is left open or
connected to V-.

COMP - This analog comparator output is an open collector configuration which goes to V- when "low."

The application of V+ to this pin will put all of the BCD
data bits in a serial order at the bit 4 output.

V- - Negative Supply Voltage. Recommended level is
-12V ± 10%.

Bit outputs 1, 2, and 3 contain tim~ markers to identify the
data. The most significant bit of the last digit (D4) is
identified by a marker at the bit 2 output. The least significant bit of the first Digit (Dl) is identified by a marker at
bit 3. Bit 1 shows a marker for the least significant bit of
each digit.

GI}fO - Analog Processor Ground.
REFout - This voltage output of the SPOT U/D switch,
converted to a current by resistor Rl, supplies the reference
current to the integrator.

All output format options are independent of one another
(i.e., the serial bit output can have either sequential or interlace scan, Positive or Negative logic).

INT_ IN - Integrator Summing Node.

(*For LD110, action is described for "pin left open".)

VRE'F - A stable positive reference voltage (5 to 11 V)
applied to this pin is the standard to which the input
voltage VIN is measured. Ratio measurements can be made
by applying a variable to this input (1.0 to 11 V).

DESCRIPTION OF PIN FUNCTIONS - LDlll
BU F OUT - The output of this unity gain input buffer amplifier is applied to the integrator summing node through
a scaling resistor R2. The value of this resistor is typically
10 Krl for a 200:0 mV full-scale and 100 Krl for a
2.000 V full-scale. The digital output is inversely proportional to the value of th is resistor,

INT. OUT - The output of the integrating amplifier is
made available for application to the Auto-Zero amplifier by
means of resistor R4.
AZ OUT - The output of the unity gain Auto-Zem Amplifier provides a second negative reference current to the integrator through resistor R3.

V,N
Rl
Count=-8192
VREF R2

AZ FilTER - The RC filter (R5 and CSTRG) connected to
this pin stores. DeC. voltage components to balance amplifier offset and drift components.

HI-QUALITY GND - This pin, typically connected to a
High Quality Ground point for single ended inputs CAN BE
USED AS THE INVERTING INPUT FOR 01 FFERENTIAl
SIGNALS. The digital output will be VIN - VH 1- Q. When
using this differential mode, it is important that resistor R3
equal Resistor R2 for proper operation.

AZ IN - This input is switched into the AZ filter during the
Zeroing interval.
VIN - Analog Voltage Input. The AID System digitizes the
voltage appearing at this input.

M/Z -'- Measure/Zero Logic Input. Internal level shifting
drivers operate the PMOS switches' in response to this
digital signal.

V++ - Positive Supply Voltage. The recommended level is
+12 volts ± 10%.

4-7

APPLICATIONS LDll1ILD.114

,.. ., 11-r- ,-,
'. r-

3.•

~
f - -,-,.'
'
~,b

~•

-.- f-- -'_'-_-1 I-~ __I i= _._1

OL·702

4.12

R10
510n
r~-

I'

4.12

Rll
7511

3___:~-:~~__

-

il..-....!i

9

... '

4.12

1'6 _
..----+-----'

__ 6 _..31-_-12

L

~;

~ DL·702

___ DL ·702

_ _ _ _ _ ....!.O

i3 __

~4:_,~

____

..!_,

_____ ~ J
1

R12

:l:.....----jf---'-......1 ,..

""VI/\,--<>V'N

,
r---

0:-

..----'
~~

r--

6

,...-',

••
11

,.,;

'2

17

fcIr

'6

'3
14

"

~~. Kn

n

_I

'-' '4~: f---4-'\,.1V\
=r-

R4120lm
v~

4

LOll1

131-:=:::t==tN~l

:

~~I-I---t-..",~ 'R~

7

10 -

e Q~

100Kn

II ·
9l 1~~IT~l2'F .
IL .AtEll
-j

21
2.

' r - ,.

r.

~

28
27
26
25
24
LOll"\ 23
22
~

2
3

I

R,

ft--I---

75K!1

f---:--

10K!1

~.o,.~~

'2N42~'
'5V

f~.m::

+512

! ,'2V

+12V

3'1.. Digit DVM (:1:200.0 mV)

APPLICATIONS LDll0/LDlll

.-___-'\;'"',."'nl\r-l+
Rg

AS

Q,!-"'v"v"',,'......,,''''··vp.,,·-l.
2N5139

l~
,

.
(FND·71)

(FND·70)

(FND·70J

(FND·701

RBt

-_ _--

A.o

6,
VIN

+12V

......

7416
HEX INVERTER

, 5

RIO
5.1K!!

.. :

CLOCK
OUTPUT

V~EF

4-8

"

ADcoa01-ADcoa04
a-Bit Microprocessor
Compatible AID Converters

FEATURES

GENERAL DESCRIPTION

• MCS-48 and MCS-80/85 bus compatible-no interfacing logic required
• Conversion time < 100 P.s
• Easy interface to all microprocessors
• Will operate "stand alone"
• Differential analog voltage inputs
• Bandgap voltage references
• TTL compatible inputs and outputs
• ON-chip clock generator
• OV to 5V analog voltage input range (single + 5V
supply)
• No zero adjust required,

The ADC0801 family are CMOS a-bit successive approximation AID converters which use a modified potentiometric
ladder, and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or 1/0 ports, hence no interfaCing is required.
A differential analog voltage input allows increasing the
common-mode-rejection and offsetting the analog zero input'
voltage value_ In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
The ADC0801 family is available in the industry standard 20
pin CERDIP packages_

TYPICAL APPLICATION

PIN CONFIGURATION

c-s IT~~

r<

1
2
3

\

I

~

ANY
PROCESSOR

~~
ID

'l;.1~
I~.

5
11
12
13
14
15
16
17
18

CS

vee

RD
WR

CLKR

-

INTR
DB7
DB6
DB5

CLKIN

AID

DB4
DB3
DB2'
DBl
DBO

2!!..0

tbr

19
4

10kY-

T1

~J

f·BIT RESOLUTION
V,N (+)
DIFF
OVER ANY DESiRED
V,N (_) ~ INPUTS ANALOG INPUT
8
VOLTAGE RANGE
AGND
VREF/2

~ VREF/21

DGND

~

b..

":"

RD

@:

~

WR

IT

CLK

~

INTR

II

+IN

[I

~ DB3

~ DBO (LSB)

m

DBl

~

-IN

II
~

~
~

DB5

VREF/2

Ii

~

DB6

DIGITAL GND

§

,

ADC0801

± 1/4 bit adjusted full scale

ADC0802

± 1/2 bit no adjust

ADC0803

± 1/2 bit adjusted full scale

ADC0804

± 1 bit no adjust

TEMPERATURE
RANGE

O'C to + 70'C
- 40'C to + 85'C
-55'C,to +125'C
O'C to + 70'C
- 40'C to + 85'C
- 55'C to + 125'C
O'C to + 70'C
- 40'C to + 85'C
- 55'C to + 125'C
O'C to + 70'C
- 40'C to + 85'C

4-9

PACKAGE

20
20
20
20
20
20
20
20
20
20
20

pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin

CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP

DB4

t!!l DB7 (MSB)

ORDERING INFORMATION

ERROR

DB2

ANALOG GND

TOP VIEW

PART

v+ ORVREF
CLKR

ORDER
NUMBER

ADC0801LCN
ADC0801LCD
ADC0801LD
. ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LD
ADC0804LCN
ADC0804LCD

II

D~DIL

ADC0801-ADC0804
ABSOLUTE MAXIMUM RATINGS

OPERATING RATINGS

Supply Voltage ....................•..•........ , .. 6.5V
Voltage at Any Input. ............... -0.3Vto(V+ +0:.3V)
Storage Temperature Range ........... -'- 65'C to + 150'C
Package Dissipation at TA = 25'C ................ 875 mW
Lead Temperature (Soldering, 10 seconds) .......... 300·C

Temperature-Rarige
ADC0801l02l03LD ................. ~ -55'Cto + 125'C
ADC0801/02/03/04LCD ............... -40'Cto + 85'C
ADC0801/02/03/04LCN . ................. O'C to + 70'C
SupplyVoltageRange ..•......•........ : .... 4.5Vto6.5V·

ELECTRICAL CHARACTERISTICS
Converter Specifications: V + = 5V, VREF /2 = 2.500V, TMIN :sTA:sTMAX and 1e = 640 kHz unless otherwise stated.
PARAMETER

MIN

TYP

MAX

UNIT

,TEST CONDITIONS

ADCOB01:'
Total Adjusted Error

±1/4

LSB

With Full Scale Adjust

ADCOB02:
Total Unadjusted Error

±1/2.

. LSB

Completely Unadjusted

ADCOB03:
Total Adjusted Error

±1/2

LSB

With Full Scale Adjust

±1

LSB

Completely Unadjusted

ADCOB04:
Total Unadjusted Error
VREF /2 Input Resistance

1.0

Analog Input Voltage Range

1.3

kll
V++0.05

GND-0.05

Input Resistance at Pin 9

V

DC Common·Mode Rejection

±1/16

±1/B

LSB

Over Analog Input Voltage Range

Pow.er Supply Sensitivity

±1/16

±1/B

LSB

V + = 5V ± 10% Over Aliowed
Input Voltage Range

Timing Specifications: V + = 5V and TA = 25'C unless otherwise stated.
PARAMETER
fe

Clock Frequency

tconv

Conversion Time

CR

Conversion Rate In Free-Running Mode

\

,

tW(WR)L Width of WR Input (Start Pulse Width)
tAcc

MIN

TYP

MAX

UNIT

100
100

640
640

12BO
BOO

kHz
kHz

66

73

ns

B770

ConvlS

ns

CS=OV

200

ns

CL = 100 pF (Use Bus Driver IC
for Larger Cd

125

250

ns

CL = 10 pF, RL = 10k

300 .

450

ns

5

7.5

pF

5

7.5

pF

RD to Output Data Valid)
t 1H, tOH 3-S!!te Control (Delay from Rising Edge
of RD to Hi-Z State)
tWI
CIN
.COUT

Delay from Falling Edge of WR to
Reset of INTR
Input Capacitance of Logic
. Control Inputs
3-State Output Capacitance (Data Buffers)

4-10

INTR tied to WR with
CS = OV, fe = 64? kHz

135

100

~cess Time (Delay from Failing Edge of

TEST CONDITIONS
V+ =6V,
V+ =5V

U~Ull

AM2502/3/4
AM25L02/3/4
Successive Approximation Registers

FEATURES

systems as the control and storage element in recursive
digital routines.
The registers consist of a set of master latches which act as
the control elements and change state when the input clock
is LOW, and a set of slave latches that hold the register data
and change on the input clock LOW to HIGH transition.
Externally the device acts as a special purchase serial to
parallel c'onverter which accepts data at the D input of the
register and sends the data to the appropriate slave latch to
appear at the register output and the DO output on the 2502
and 2504 when the clock goes from LOW to HIGH. There are
no restrictions on the data input; it can change state at any
time except during the set-up time just prior to the clock

• Contains all the storage and control for successive
approximation A to 0 converters.
• Provision for register extension or truncation.
• Can be operated in START-STOP or continuous
conversion mode.
• 100% reliability assurance testing in compliance
with MIL-STO-883.
• Can be used as serial-to-parallel counter or ring
counters.
• Electrically tested and optically inspected dice for
the assemblers of hybrid products.

GENERAL DESCRIPTION

transition. At the same time data enters the register bit the
next less significant bit is set to a LOW, ready for the next
iteration.
The AM25L02/L03/L04 are low power equivalents of the
AM2502/03/04.

The AM2502/3/4 are 8-bit and 12-bit TTL Successive Approximation Registers. They contain all the digital control
and storage, necessary for successive approximation
analog to digital conversion and can also be used in digital

II

...------------..,
LOGIC DIAGRAM

DO (2502, 2504)
Q6(10)

Q7(11)

D

r-----------,

I (SEE NOTE)
I Bits 5 (9) to 1

05(91-1

I

I
I

cc

00

I

L _ _ _ _ _ _ _ _ _ _ .J

NOTES
1. CELL LOGIC IS REPEATED FOR
REGISTER STAGES.
05 TO 0, 2502/3
09 TO 0, 2504
2. NUMBERS IN PARENTHESES ARE FOR 2504

PIN CONFIGURATIONS'AND LOGIC SYMBOLS
DO
(2502)

AM25(L)02/(L)03
DO (2502)
E (2503L
CC

00
0,
02
03
D
GND

1

v+
Q7
07
06 S
05

~'

DO
CC

00
0,
02
03
0,
05
06
07
07

25021
2503
8-BIT
SAR
10

0

CP

(outline dwg JE, PEl

E
(2503)

CC

AM25(L)04
34

v+

E
DO

011

CC

NC

00
0,
02
03
0,
05

011
010
09
Os
07
06 S

NC
D
GND

NC

S

D

CP

CP

5
6
2504
12-BIT 7
SAR
8
9
16
17
14
18
19
11
20
21
23
13

(outline d' 'g JG, PG)
E

4·11

CP

v+
011

E
00
0,
02
03
0,
05
06
07
Os
09
010
011
011

DO

CC
00
0,
02
03
0,
05
NC
D
GND

32 1
4
5

~

242322
21
20

AM25(L)04 ::

8
9
10>1112

17
16
13 1415

NC

011
010
09
Os
07
06
NC

5

CP

(outline dwg FG)

~

AM2502/3/4, AM25L02/3/4
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..................................................... - 1.0

MAXIMUM LOGIC
'V,L2
"LOW" OUTPUT ~.E-+':M""AX=I;:::M"'U"'M""L-=O-=G""IC::VOLTAGE...a:m
"LOW"INPUT
Vo~~ NOISE'
VOLTAGE
0.0
IMMUNITY '--_ _ _ __
DRIVING DEVICE (Low level)
DRIVEN DEVICE

!; 0.8

CURRENT INTERFACE CONDITIONS -

!I: 0.6

;: g::
~

!;

OUTPUT DRIVING
"HIGH"

V+--~------~-------T-----

o

~~-- ____ '!I~
~L'

VI~

DRIVING
DEVICE

DRIVEN
DEVICE

HIGH

INPUT LOAD
DRIVEN "HIGH"'

4·13

AM2502/3/4, AM25L02/3/4
SWITCHING TIME WAVEFORMS
KEY TO TIMING DIAGRAM
---'------1.5V

1.5V

07(11) -~-----l-

------i-.~'!/q.

------+-+~IL-----.j...U/I.'IJ

------f----'---1.5V

---------#1'1111- _____-+________..j.)~~ --1.5V
~~__

INPUTS

MUST BE
STEADY

-~~ffi~~w,,q.-----j---------t----1.5V

S'

06(10)

WAVEFORM

OUTPUTS

WILL BE
STEADY

WILL BE
MAY CHANGE CHANGING
' - FROM H TO L FROM Ii TO L

/I
•

WILL BE
MAY CHANGE CHANGING
FROM L TO H FROM L TO H

DON'T CARE; CHANGING;
ANY CHANGE STATE
PERMITTED
UNKNOWN

tpd+MAX

DO
(2502, 2504)

======:jm~======:::z~~ --.,-------'l~\,,~

(2503, 2504) _ _ _ _ _ _ _ _

E
Q7(11)

t

!Pd.(E) M A X ,
"

~

- - - - - ' - - - - - - 1 . 5 ...
;"

~\" 1I"'hr---------"--~\_
"~V'I

DEFINITION OF TERMS
SUBSCRIPT TERMS:
H -HIGH, applying to a HIGH logic level or when used with
Vee to indicate high Vee value.
I-Input.
L.,- LOW, applying to LOW logic level or when used with Vee
to indicate'low Vee value.
O-Output.

FUNCTIONAL TERMS:
Fan-Out - The logic HIGH or LOW output drive capability in
terms of Input Unit Loads.
Input Unit Load One T2L gate input load. In the HIGH state
it is equal to liH and in'the LOW state it is equal to .Ill!
CP- The clock input of ttie register.
CC - The ,conversion complete output. This outp'ut remains
HIGH during a conversion and goes LOW when a conversion
if> complete.
0- The serial data input of the register.
E- The register enable. This input is used to expand the
length of the register and when HIGH forces the 07(11)
register output HIGH and inhibits conversion. When not
used for expansion the enable is held at a LOW logic level
(Ground),
07(11)- The true output of the MSB of the register.
Q7(11)- The complement output of the MSB of the 'register.
OJ, i = 7(11) 'to 0- The outputs of the register.
S - The start input. If the start input is held LOW for at leasta
clock period the register will be reset to 07(11) LOW and all
.the remaining outputs HIGH. A start pulse that is LOW for a
shorter period of tim~can be used if it meets the set-up time
requirements of the S input.
DO - The serial data output. (The 0 input delayed one bit.)

OPERATIONAL TERMS:
IlL - Forward input load current.

4-14

~~A!~E:HOE~7~~~BLE CHANGES

Ipd-(E) MAX

________

APPLIES ONLY WHEN START-SIGNAL
1.5V APPLIED DURING PREVIOUS
CLOCK PERIOD.

IOH-Output HIGH current, forced out of output VOH test.
lot:. - Output LOW current, forced into the output in VOL test.
IIH- Reverse input load current.
Negative Current-:- Current flowing out of the device.
Positive Current- Current flowing into the device.
VIH-Minimum logic HIGH input voltage.
VIL - Maximum logic LOW input voltage.
VOH- Minimum logic HIGH output voltage with output HIGH
current 10H flowing out of output.
VOL - Maximum logic LOW output voltage with output LOW
current 10L flowing into output.
.
SWITCHING TERMS: (Measured at the 1.5V logic level.)
tpd- - The propagation delay from the clock, signal LOWHIGH transition to an output signal HIGH-LOW transition.
tpd+ - The propagation delay from the clock signal LOW- .
HIGH transition to an output signal LOW-HIGH transition.
tpd-:(E)-Thepropagation delay fror)1 the Enable signal
HIGH-LOW transition to the 07(11) output signal HiGH-LOW
transition.
'
tpd+(E)- The propagation delay from the Enable signal
LOW-HIGH transition to 07(11) output signal LOW-HIGH
transition.
ts(O)- Set-up time required for the logic level to be present
at the data input prior to the clock transition from LOW to
HIGH in order for the register to respond. The data input
should remain steady between ts max, and Is min. before the
cl~k.

ts(S,!,- Set-up time required for a LOW level to be present at
the Sinput prior to the clock transition from LOW to HIGH in
order for the register!9 be reset, or time required for a HIGH
level to be present on S before the HIGH to LOW clock transition to prevent resetting.
tpw(CP)-The minimum clock pulse width (LOW or HIGH)
required for proper register operation.

AM2502/3/4, AM25Lo2/3/4
USER NOTES FOR AID CONVERSION

AM2S(L)02/3 TRUTH TABLE
TIME
In
0
1
2

3
4
5
6
7
B

9
10

INPUTS
D S E
X L L
07 H L
06 H L
05 H L
04 H L
03 H L
02 H L
01 H L
Do H L
X H L
X X L
,X X H

1. The register-can be used with current switches which are
either active high or active low. If active low current
switches are used, the resulting digital output from the
register is active LOW. That is, a logic "1" is represented
as a low voltage level. If active high current switches are
used then the digital output is activeHIGH; a logic "1" is
represented as a high voltage level.
"
2. For a maximum digital error of ±1/2 LSB the comparator
must be biased. If active high current switches are' used,
the comparator should be biased +1/2 LSB and if the
curre'nt switch'es are active low, the comparator must be
'
biased -1/2 LSB.
3. The register, by suitable selection of resistor ladder network, can be used to perform either binary or BCD
conversion.
4: The register can ,also be used to perform 2's complement
conversion by offsetting the comparator 1/2 full range
+1/2 LSB and using the complement of the MSB Q7(11) as
the sign bit.
.
5. If the register is truncated and operated in the continuous
conversion mode a lock-up condition may occur on
power-on. This situation can be overcome by making the
START input the OR function of CC and the appropriate
register output.
'-

OUTPUTS
Do
X
X

07
X
L

07
06
05
04
03
02
01
Do
X
X

Dr
07
07
07
07
07'
07
07
07
H

06
X
H
L
06
06
06
06
06
06
06
06
NC

05
X
H
H
L
05
05
05
05
05
05
05
NC

04
X
H
H
H
L
04
04
04
04
04
04
NC

03 02
X X
H H
H H
H H
H H
L
H
03 L
03 02
03 02
03 D2
03 D2
NC NC

01
X
H
H
H
H
H
H
L

00
X
H
H
H
H
H
H
H
L

CC

X
H
H
H
H
H
H
H
H
01
01 Do L
01 Do L
NC NC NC

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
Note: Truth Table for 25(U04 is extended to include 12 outputs,

n

AM2£6lo2/3 TIMING CHART

"~~I

CLOCK

DATA
Q7

Q.

Qs

Q4

Q3 _ _---'

OUTPUTS
Q2 _ _---'

Q, - - - - - '

Qo _ _---'
CONVERSION - - - . . - - - - - - - - - - - - - - - - - - - - - - - - - ,
COMPLETE
"---..,-_..,...._
DO .J-_ _.J-_ _.J-_---I

Note: Arbitrary Conversion shown. Timing chart for AM25(U04 is extended to include 12 outputs, starling with

4-15

all.

·O~OIL

AM2502/3/4, AM2SL02/3/4
ORDERING INFORMATION
16 PIN
CERDIP
AM2502DC
AM2502DM
AM2503DC
AM2503DM
24 pin
CERDIP
AM2504C AM2504DC
AM2504M AM2504DM

PART
AM2502C
AM2502M
AM2503C
AM2503M

16 PIN
PLASTIC
DIP
AM2502PC
AM2503PC
24 pin
plastic DIP
AM2504PC

DICE
AM2502XC
AM2502XM
AM2503XC
AM2503XM
24 pin ..
Dice
Flatpak
AM2504XC
AM2504FM AM2504XM

To order "L" devices, msert "L" followmg"25"; e.g., AM25L02DM
NOTES: C-- Commercial Temperature Range (O°C to +70°CI
M - Military Temperature Range (-55°C to +125°CI

CIRCUIT DESCRIPTION

clock LOW-to-HIGH transition in order to guarantee correct
resetting. After the clock has gone HIGH resetting the
register, the S signal is removed. On the next clock LOW-toHIGH transition the data on the D input is set into the 07(11)
register bit and the 06(101 register bit is set to a LOW ready
for the next clock cycle. On the next clock LOW-to-HIGH
transition data enters the 06(101 register bit and 05(9) is set to
a LOW. This operation is repeated for each register bit in turn
until the register has been filled. When the data goes into OQ,
the CC signal goes LOW, and the register is inhibited from
further change until reset by a START signal.
To allow two's complement conversion the complementary
output of the most significant register bit is made available.
An active LOW enable input, E, on the 2503 and 2504 allows
devices to be connected together to form a longer register by
connecting the clock, D, and S inputs together and
connecting the CC output of one device to the E input of the
next less significant device. When the START signal resets the
register, the E signal goes HIGH, forcing the 07(11) bit HIGH
and inhibiting the device from accepting data until the
previous device is full and its CC goes LOW. If only one
device is used the E input should be held at a LOW logic level
(Ground!. If all the bits are not required, the register may be
truncated and conversion time saved by using a register
output going LOW rather than the CC signal to indicate the
end of conversion.

The register is reset by holding the S (Start) signal LOW
during the clock LOW-to-HIGH transition. The register
synchronously resets to the state 07(11) LOW, (Note 2) and
all the remaining register outputs HIGH. The CC
(Conversion Complete) signal is also set HIGH at this time.
The S signal should not be brought back HIGH until after the
39kll

REF IN
ANALOG IN

>--------,
>-------,

15V

16

AD7541

151413121110 9 8 7 6

OUTPUTS
FOR
CONTINUOUS
CONVERSION

CHIP TOPOGRAPHY

MSB
{TART LSB4 5 6 7 8 9 16 1718192021 23

!_S~~

_

I

S

I

loon

I
I
:470PF~
I

14

AM25L04

11 D

'-i8'::-::_ _ _ _-'1'i'3~-......;.1:_...
CC
CP
E

CP

CONVERSION

t---+--~-----+------ COMPLETE

GND

SIGNAL

D

00

0,

0, 03 04

Os

Die size 0.95" x 0.142"

MODERATE COST AID CONVERTER

4·16

ICL71 06/71 07
3Y2 Digit Single Chip
A/D Converter
GENERAL DESCRIPTION

FEATURES
.• Guaranteed zero reading for 0 volts input on all
scales.
• True polarity at zero for precise null detection.
• 1 pA typical input current.
• True differential input and reference.
• Direct display drive - no external components
required. - LCD ICL7106
- LED ICL7107
• Low noise - less than 15/-N p-p.
• On-chip clock and reference.
• Low power dissipation - typically less than 10mW.
• No additional active circuits required.
• Evaluation Kit available.

The Intersil ICL7106 and 7107 are high perfdrmance, low
power 3-1/2 digit AID converters containing all the necessary. active devices on a single CMOS I.C. Included are
seven-segment decoders, display drivers, reference, and a
clock. The 7106 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7107 will
directly drive an instrument-size light emitting diode (LEO)
display.
The 7106 and 7107 bring together an unprecedented
combination of high accuracy, versatility, and true economy.
High accuracy like. auto-zero to less than 10I'V, zero drift of
less than 1I'V/oC, input bias current of 10 pA max., and rollover error of less than one count. The versatility of true differential input and reference is useful in all systems, but gives
the designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of single power supply operation
(7106), enabling a high performance panel meter to be built
with the addition of only 7 passive <;omponents and a display.

+'N -

IN

+. R~

R,
24K!1

1MIl

ICL7107 with LED Display

ICL7106 with Liquid Crystal Display

(Outline dwgs DI,.,_JL, PL)

ORDERING INFORMATION
Temp. Range

Part

Package

7106
7106
7106
7107
7107
7107
7106 Kit
7107 Kit

40 pin ceramic DIP
O'C to +70'C
40 pin plastic DIP
O'C to +70'C
40 pin CERDIP
O'C to +70'C
40 pin CERDIP
O'C to +70'C
40 pin ceramic DIP
O'C to +70'C
40 pin plastic DIP
O'C to +70'C
Evaluation kits contain IC, display, circuit
board, passive components and hardware.
See' page 10.

Order Part 1#
ICL7106CDL
ICL7106CPL
ICL7106CJL
ICL7107CJL
ICL7107CDL
ICL7107CPL
ICL7106EV/Kit
ICL7107EV/Kit

4-17

V'

OSC1

01

OSC2

Cl

1
~ '"

05C3

Iii

B1
A1

TEST

-

Gl
El

C·REF
C-REF

02
C2

COMMON
IN HI

82

IN LO
AlZ
BUFF
.NT
V-

!:::

_

~
w

to

1

A2

F2

E2

_ { 03
~
83
~
F3
E3
(1000) AB4
POL
fMINUS)

REF HI
REF LO

g:l(~EN5)
A3

g

G3 !i.
OP/GND
(7106) (7107)

II
~

O~O[6

ICL7106/ICL7107 .
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+)
ICL7106 ..................................... 15V
ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 6V
Supply Voltage (V"')
ICL7106 ..................................... 15V
ICL7107 . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. - 9V
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) ......... V+ to VClock Input
ICL7106 ................................ Test to V+
ICL7107 ............................... Gnd to V+

Power Dissipation (ICL7106 Note 2; ICL7107 Note 1)
Ceramic Package ......................... 1000mW
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . .. 800mW.
Operating Temperature ................. O·C to + 70·C .
Storage Temperature. . . . . . . . . . . . . .. - 65·C to + 160·C
Lead Temperature (Soldering, 60 sec) ............ 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

.

Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100!,A.
Note 2: Dissipation rating assumes device Is mounted with all leads soldered to printed circuit board.

ELECTRICAL CHARACTERISTICS (Note 3)
CHARACTERISTICS

MIN
--{)OO.O

TYP

MAX

UNITS

±OOO.O

+000.0

Digital Reading

VIN = VREF
VREF = 100mV

999

999/1000

1000

Digital Reading

-VIN = +VIN = 200.0mV

-1

±.2

+1

Counts

Full scale = 200mV

-1

±.2

+1

Counts

CONDITIONS

Zero Input Reading

VIN = O.OV
Full Scale = 200.0mV

Ratiometric Reading
Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)
Linearity (Max. deviation from
best straight line fit)

or full scale = 2.000V

Common Mode Rejection Ratio
(Note 4)

VCM = ±1V, VIN = OV.
Full Scale = 200.0mV

50

IlVN

Noise (Pk-Pk value not exceeded
95% of time)

VIN = OV
Full Scale = 200.0mV

15

IlV

Leakage Current

I Input

VIN = 0

Zero Reading Drift

VIN =0
O· < TA < 70°C

Scale Factor Temperature
Coefficient

VIN = 199.0mV
0° < TA < 70°C
(Ext. Ref. Oppm/OC)

V+ Supply Current (Does not
include LED current for 7107)
V Supply Current (7107 only)

VIN =0

Analog Common Voltage (With ..
respect to Pos. Supply)

25kfl between Common &
Pos. Supply

Temp. Coeff. of Analog Common
(With respect to Pos. Supply)

25kfl between Common &
Pos. Supply
V+ to V = 9V

7106 ONLY
Pk-Pk Segment Drive Voltage,
Pk-Pk Backplane Drive Voltage
(Note 5)
7107 ONLY
Segment Sinking Current
(Except Pin 19)

1

10

pA

0.2

1

llV/oC

1

5

ppml"C

0.8

1.8

mA

0.6

1.8

mA

2.8

3.2

V

\
,

V+ = 5.0V,
Segment voltage = 3V

(Pin 19 only).

2.4

80

ppml"C

6

4

5

V

5

8.0

mA

10

16

mA

Note 3: Unless otherwise noted, specifications apply to both the 7106 and 7107 atTA = 25· C, fclock =48kHz. 7106 is tested in the circuit of Figure
1.7107 is tested in the circuit of Figure 2.
Note 4: Refer t'o "Differential Input" discussion below.
Note 5: Back plane drive is in phase with segment drive for 'off' segment, 180· out of phase for 'on' segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.
4-18

ICL71 06/ICL710.7
TEST CIRCUITS
+'N -

+'N -

Figure 1: 7106

Figure 2: 7107

DETAILED DESCRIPTION
ANALOG SECTION
Figure 3 shows the Block Diagram of the Analog Section for
the ICl 7106 and 7107. Each measurement cycle is divided

REF HI

CREF+

r-----I

I,

3.

36

into three phases. They are (1) auto-zero IA-Z). (2) signal
integrate liNT) and (3) deintegrate IDEl.
-

v+

REF LO
35

n
l1l.I

33

v+

,
I
I

10Ma

I

..... - ---~ TO DIGITAL SECTION

I
'31

INHI~~~~-,----~--~--~------~

'NT

6.2V
A/Z

'32
COMMON~~-----+----~--~--~
I

~~

I
INLO~30~~9-

LOW

____~~______________~________________~

L_________________________ ____________________________________ _

liNT

~

v-

Figure 3: Analog Section of 7106/7107

1. Auto-zero phase

o

IN lO fora fixed time. This differential voltage can be
within a wide common mode range; within one volt of
either supply. If. on the other hand. the input signal. has
no return with respect to the converter power supply. IN
lO can be tied to analog COMMON to establish the
correct common-mode voltage. At the end of this phase.
the polarity of the integrated signal is determined.

During auto-zero three things happen. First. input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second. the reference
capacitor is charged to the reference voltage. Third. a
feedback loop is closed around the system to charge the
·auto-zero capaCitor CAZ to compensate for offset
voltages in the buffer amplifier. integrator. and
comparator. Since the comparator is included in the loop.
the A-Z accuracy is limited only by the noise of the
system. In any case. the offset referred to the input is less
than 10/N.

3. De-integrate phase
The final phase is de-integrate. or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures
that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero.
The time required for the output t9 return to zero is
proportional to the input signal. Specifically the digital
reading displayed is 1000

2. Signal Integrate phase
During signal integrate. the auto-zero loop is opened. the
internal short is removed. and the internal input high and
low are connected to the external pins. The converter
then integrates the differential voltage between IN HI and

Iv¥:rl.

4·19

n~olL

ICL71 06/1CL71 07
Differential Input

these problems are of course eliminated if' an external
reference is used.

The input can accept differential voltages anywhere within
the ,common mode range of the input amplifier; or
specifically from 0.5 volts below the positive supply to 1.0
volt above the negative supply. In this range the system has a
CMRR of 86 dB typical. However. since the integrator also
swings with the common mode voltage. care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input
voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V fiJll scale swing with little loss of accuracy.
The integrator output can swing within 0.3 volts of either
supply without loss of linearity. See A032 for a discussion
of the effects of stray capacitance.

The 7106. with its negligible dissipation. suffers from none
of these problems. In either case. an external reference can
easily be added. as shown in Fig, 4.
v+

~

"

6.8kll

20kJ!
REF LO

\

710617107

7106/7107

liZ

REF HI
REF LO

ICL 8069
1.2 V
REFERENCE

COMMON

v(b)

(.)

Differential
Reference
,

II

v'

V' REF HI

Figure 4: Using an External Reference

The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference ,capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage. the reference ca, pac, itor can gain charge (,inCrease
voltage) when called up to de-integrate 'a positive signal but
lose charge (decrease voltage) when called up to deintegrate
a n!'lgative input signal. This difference in reference for (+) or
(-) input voltage will give 'a roll-over error. However. by
selecting the reference capacitor large enough in
comparison to the stray capacitance. this error can be held to
less than 0.5 count for the worst case condition. (See
Component Val,ues Selection belowl.

Analog COMMON is also used as the input low return durIng auto-zero and de-integrate. If iN LO is different from
analog COMMON, a common mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common mode voltage
from the converter. The sar:ne holds true for the reference
voltage. If reference can be conveniently referenced to
analog COMMON, it should be since this removes the common mode voltage from the reference system.

Analog COMMON

Within the IC. analog COMMON is tied to an N channel FET
that can sink 30mA or more of current to hold the voltage 2.8
volts below the positive supply (when a load is trying to pull
the common line positivel. However. there is only 1O/lA of
source current. so COMMON may easily be tied to a more
negative voltage thus over-riding the ('nternal reference.

This pin is included primarily tq set the common mode
voltage for battery operation (7106) or for any system where
the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately
2.8 volts mor~ negative than the positive'supply. This is
selected to give a minimum end-of-life battery voltage of
about 6V. However, the analog COMMON has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the zener to regulate (>7V),
the COMMON voltage will have a low voltage coefficient
1.001%1%). low output impedance (""15m. and a temperature
coefficient typically less than 80ppm/o C.

TEST

The limitations' 01 the on-chip reference should also be
recognized, however. With the 7107. the internal heating
'which results from the LED drivers can cause some
degradation in performance. Due to their higher thermlll
resistance.' plastic parts are poorer in this respect than
ceramic., The combination of reference Temperature
Coefficient (TC). internal chip dissipation, and package \
thermal resistance can increase noise nearfull scale'from 25
p.V to 80p.Vp-p. Also the linearity in going from a high
dissipation count such 'as 1000 (20 segments on) to a low
dissipation count such as 1111 (8 segments on) can sui'ier b,y
a count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because overload is a low dissipation mode. with the
three least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All
4-20

The HoST pin serves two functions. On the 71 06 it is coupled
to the internally generated digital supply through a soon
resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on the,
LCD display. Figures 5 and 6 show such an application. No
more than a 1mA load should be applied.
v+

7106

TO LCD
DECIMAL POINT

L-----o~~~;~LANE
Figure 5: Simple Inverter for Fixed Decimal Point

ICL71 06/1CL7107
DIGITAL SECTION
BPl----_-i--\

7106

Figures 7 and 8 show the digital section for the 7106 and
7107, respectively. In the 7106, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the
relative large capacitive currents when the back plane (BP)
voltage is switched. The BPfrequency is the clock frequency
divided by 800. For three readings/second this is a 60 Hz
square wave with a nominal amplitude of 5 volts. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON. In all cases neglible d-c voltage exists across the
segments.

DECIMAL
POINT
SELeCT

TEST

Figure 6: Exclusive 'OR' Gate for Decimal Point Drive

Figure 8 is the Digital Section of the 7107. It is identical to the
7106 except that the regulated supply and back plane drive
have been eliminated and the segment drive has been
increased from 2 to 8' mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is "on" for negative
analog inputs. If IN LO and IN HI are reversed, this indication
can be reversed also, if desired.

The second function is a "lamp test". When TEST is pulled
high (to v+) all segments will be turned on and the display
should read -1888. The TEST pin will sink about 10mA under
these cond itions.
.
Caution: on the 7106, in the lamp test mode, the segments
have a constant d-c voltage (no square-wave) and may burn
the LCD display if left in this mode for several minutes.

--·-rr+tt~·1---1~~·-rrt+-----~.~----,

,
,I
,,
,,
,
I

I
I

TYPICAL SEGMENT OUTPUT

I
I

I

,I
I
I
I

I

I
I

,,
I

-------~~~~~~~~~========~~~~~~~======::----ll"
I

v'

---r----+-----r----4----+-~~~~~~~--+-------~--~VV\rlDTEST

esc 1

asc 2

esc 3

Figure 7: Digital Section 7106

4·21

ICL71 06/ICL71 07

.--, ".,.
,-,

,,..

n~nlL

,.-:-,.
•
d

-------------------------------------

-----

--------i
I
I

I

I
I
I
I
I

TYPICAL SEGMENT ,OUTPUT

,I

__~~------~--.-------~----1_--_+--_r--~------------'~V· '
31

, TEST

21

I

500!l

I
DIGITAL

L----+~~~----~3~!-_-_-_-_-_--_-_-_-_-_-_-_-_-_--_~_-_~_-_-_-_--_-_-_~_-_--_~_~~$GROUNO

II

asc 1

asc 3

asc 2

Figure 8: Digital Section 7107
40kHz (2.5 readings/second) will reject both 50 and 60 Hz
(also 400 and 440 Hz>.

System Timing
Figure 9 shows the clocking arrangement used in the 7106
and 7107. Three basic clocking arrangements can.be \Jsed:

COMPONENT VALUE SELECTION
1. Integrating Resistor

1. An external oscillator connecteq to pin 40.
2. A crystal between pins 39 and 40.

Both the buffer amplifier and the integrator have a class A
output stage with 100!,A of quiescent current. They can
supply 20!,A of drive current with negligible non-linearity .
. The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 4701(0 isnear optimum and similarly a 47KO for a 200.0 mV scale.

3. An R-C oscillator using all three pins.
~

7106/7107 .

I
I

,
I
I
TO
I
COUNTER

I'

I

I

I

I
I
I

L________

'!!'__ :'3~~_

.__ ~ _______ _

I
I
I
_________ J
38
'

2. Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up
will not saturate the integrator swing (approx. 0,3 volt
from either supply>. In the 7106 or the 7107, when the
analog COMMON is used as a ~eference, a nominal ±2
volt full scale integrator swing is fine. Forthe 7107 with ±5
volt supplies and analog COMMON tied to supply ground,
a ±3,5 to ±4 volt swing is nominal. For three readings/
second (48kHz clock) nominal values for CINT are 0.22!,F
and 0.10!,F, respectively. Of course, if different oscillator
frequencies are used, these values should be changed in
inverse proportion to maintain the same output swing.

TEST (7106)

or GND (7107)

Figure 9: Clock Circuits
,The oscillator frequency is divided by four before it clocks
the decade counters, It is then further divided to form the
three convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (Q to 2000 counts) and autozero (1000 to 3000 ,counts). For signals less than full scale,
auto-zero gets the unused portion of reference deintegrate.
This makes a complete measure cycle of 4,000 (t6,OOO'clock
pulses) independent of input voltage. For three readings,(
second, an oscillator frequency of 48kHz would be used,

An additional requirement of the integrating capacitor is
it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for
this application, polypropylene capacitors give
undeteCtable errors at reasonable cost.

To achieve maximum rejection of 60 Hz pickup, the signal
integrate cycle should be a multiple of 60 Hz, Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33 % k Hz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
662f3 kHz, 50kHz, 40kHz, etc. would be suitable. Notethat

3. Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence 'on
the noise of the system. For 200 mVfull scale where noise
.4-22

ICL7106/1CL7107
is very important, a 0.471'F capacitor is recommended. On
the 2 volt scale, a 0.0471'F capacitor increases the speed
of recovery from overload and is adequate for noise on,
this scale.

4. Reference Capacitor
A 0.11'F capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent rollover error. Generally 1.0 I'F will hold the roll-over errorto
0.5 count in this i'nstance.

and weighing systems with a variable tare are examples.
This offset reading can be conveniently generated by
connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.

7. 7107 Power Supplies
The 7107 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2
cap'acitors, and an inexpensive I.C. Figure 10 shows this
~pplication. See ICL7660 data sheet for an alternative.

5. Oscillator Components
For all ranges of frequency a 100KO resistor is
recommended and the capacitor is selected from the
equation f = ~~. For 48kHz clock (3 readings/second), C
= 100pF.
-

6: Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 volt scale, Vref should equal 100.0 mVand 1.000 volt,
respectively. However, in many applications where the
A/D is connected to a transducer, there will exist a scale
_factor other than unity between the input voltage and the
digital reading .. For instance, in a weighing system, the
designer might like to have Ii full scale reading when the
voltage from the transducer is 0.682V. Instead of dividing
the input down to 200.0 mV, the designer should use the
input voltage directly and select VREF = .341V. Suitable
values for integrating resistor and capaCitor would be
120KO and 0.22I'F. This makes the system slightly
quieter and also avoids a qivider network on the input.
The 7107 with ±5V supplies can accept input signals up
to ±4V. Another advantage of this sytem occurs when a
digital reading of zero is desired for VIN ;CO. Temperature

Figure 10: Generating Negative Supply from +5v
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5 volts.
3. An external reference is used.

TYPICAL APPLICATIONS
possibilities, and serve to illustrate the exceptional versatility of these A/D converters.

The 7106 and 7107 may be used in a wide variety of
configurations. The circuits which follow show some of the

7108

To pin 1

7107

40

Set VREf'" 100.0mY

REFLO
CREF
CREF

COMMON
INHI
INLO

AlZ
BUFF

REF LO
C REF
C REF

22Kn

1Kn

i

INT

v-

G,.

C,

C,
}TO DISPLAY

0.22 F

I

ITO

A,
GJ
GND

0,
TO BACK PLANE

2.

2'

+

IN

47KIl

BUFF

G,

=.01",F

O.47/-1 F

AlZ

9Y

22KIl
1Mn

IN HI

V-

.

100.0mY

,/

+5V

pO.'"Fj

IN LO

=

INT E}====~0.~22~"F~_ _ _ _~
BP

Set VAEF=

100pF

COMMON

1Mn

A3

100Kfl

yv

:!

REF HI

q~~:u:~~+".O:!!'"~F
___~~~IN
[
0.47/-1 F
47Kn

40
~

~~~~ ~

0-------./
1Kn

To pin 1

'-" OSC.
OSC 2

DISPLAY

---------- -

-5V

,,
,

--------~

Figure 12: 7107 using the internal reference. Values shown are for
200.0 mV fUll scale,-3 readings per second. IN LO may be tied to '
either COMMC;>N for inputs floating with respect to supplies, or GND
for single ended inputs. (See discussion under Analog COMMON.)

Figure 11: 7106 using the internal reference. Values shown are for
200.0 mV full scale, 3 readings per second, floating supply voltage
(9V battery>.
4-23

O~OIL

ICL7106/1CL7107
TYPICAL APPLICATIONS (Contd.)
7107

7107

Set VREF '" 100.0mY

/

10Kn

10K!!
D-------.~AJV\,.-A.;x,'V-____1I_-o

C REF
C REF

+5V

6.8V

COMMONC}-------.

IN HI n-------+----±-,"'01c-.=-FAJV\~-----<>,N

C}--;=....~----~='---____t-_<>'N

-------<>

A~~ F~=~0~,4~7.~F~~~~=:=,~:..:.:.:""------1p-,
n __--'\/\JV4,,7K"'I'-+'
:

IN

BUFF

I~~ Ej=====~~0~'2~2.;£F~________:-:-------<>v-

I

~:

n------~~------------____1~_o~V

i

TO DISPLAY

______________ -l

Figure 13:7107 with an external band-gap reference 11.2V typel.'lN
LO is tied to COMMON, thus establishing the correct common mode
voltage. If COMMON is not shorted to GND, the input voltage may
float with respect to the power supply and COMMON acts as a preregulator for the reference. If COMMON is shorted to GND, the input
is single ended Ireferred to supply ground) and the pre-regulator is
over-ridden.
7106/7107

'-'

Figure 14: 7107 with Zener diode reference. Since low T.C. zeners
have breakdown voltages - 6.8V, diode must be placed across the
total supply 110V). As in the case of Figure 12, IN LO may be tied to
either COMMON or GND.

To pin 1

esc 1
asc 2
osc 3
TEST
REF HI
REF LO
C REF
q REF

2-

1QOKH

'~

g

cJ
AJ
OJ
BP/GND

SetYREF 100.0mY

$eIVREF'" 1.000V

/

100pF

:=:

8==:s=0.l F

100pF

REF HI

v+
2SKn

,/

24Kn
1M!1

:;: .D1/'F

+

'v

B:::J~~~:;:=;+"='----------<>'N

IN

-

.047JJF

470Kn

..A.,!
Q.22j..1F

~. I D~,SPLAY

v-

TO

21

Figure 15: 710617107: Recommended component values for 2.000V
full scale.

Figure 16: 7107 operated from single +5V supply. An external
reference mustbe used in this application, since the voltage between
V+ and V- is insufficient for correct operation of the internal
reference.

~T~o~p~ln·'----------------------~V+
7107

0----------.

14

IN HI
IN LO
AIZ
BUFF
INT

v-

40

100Kn

COMMON

0,

To pin 1

7107

40

7106

40

. To pin 1

asc 1

40
100KIl

g~g ~ 0-----\1----'
TEST
RE,F HI

100pF

Scale factor adjust

n----..,---==,.......

,//

Silicon NPN
MPS 3704 or
similar

47KJl

O.22.u F

,
i

~ TO

DISPLAY

A3

~ TO DISPLAY

0,
~ TO BACK PLANE

21
Figure 17: 7107 m~asuring ratiometric values of Quad Load Cell. The
resistor values within the bridge are determined by the desired
sensitivity.

4·24

Figure 18: 7106 used as a digital centigrade thermometer. A silicon
diode:connected transistor has a temperature coefficient of about
-2m VI' C. Calibration is achieved by placing the senSing transistor
in ice water and adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in boiling water and the
scale-factor potentiometer adjusted for 100.0 reading.

O~OIL

ICL71 06/1CL71 07
TYPICAL APPLICATIONS (Contd.)

OIRange

UtRange

or 74C10 •

CD4023

CD4077

To pin 1

Scale factor adjust

40

ascI
osc 2

(VREF '" 100mV for AC to RMS)

lOOK!!

OSC'[]--~10~OP~F~~--~

REF HI

33KIl

Figure 20: Circuit for developing Underrange and Overrangesignals
from 7107 outputs. The LM339 is required to ensure logic
compatibility with heavy display loading.
.

Figure 19: Circuit fordeveloping Underrange and Overrange signals
from 7106 outputs.

7106

LM339

or 74CI0

D------------.

Figure 21: AC to DC Converter with 7106. TEST is used as a com·
mon mode reference level to ensure compatibility with most op·
amps.

Figure 22: Display Buffering for increased drive current. Requires
four DM7407 Hex Buffers. Each buffer is capable of sinking 40 mA.

4·25

n
iii

D~DlL

ICL710912 Bit Binary
A/D Converter for
Microprocessor Interfaces
GENERAL DESCRIPTION

FEATURES

II
~

• 12 bit binary (plus polarity and overrange) dual
slope integrating analog-tp-digital converter.
• Byte-organized TTL-compatible three-state outputs
and UART handshake mode for simple parallel or
serial interfacing to microprocessor systems.
• RUN/AOLD input and STATUS output can be used
. to monitor and control conversion timing.
• True differential input and differential reference.
• Low noise - typically 1S/.N p-p.
.1pA typical input current.
• Operates at up to 30 conversions per second.
• On-chip oscillator operates with inexpensive
3.S8MHz TV crystal giving 7.5 conversions per
second for 60Hz rejection. May also be operated as
RC oscillator for other clock frequencies.
• Fabricated using MAX-CMOSTM technology
combining analog and digital functions on a single
low power LSI CMOS chip.
• All inputs fully protected against static discharge;
no special handling precautions necessary.

The ICL7109 is a high. performance, low power integrating
AID converter designed to easily interface with microprocessors.
The output data (12 bits, polarity and overrange) may be
directly accessed under control of two byte enable inputs
and a chip select input for a simple parallel bus interface. A
UART handshake mode is provided to allow the ICL7109 to
work with industry-standard UARTs in providing serial data
transmission; ideal for remote data logging al'lplications. The
RUN/HOLD input and STATUS output allow monitoring and
control of conversion timing.
The ICL7109 provides the user with the high accuracy, low
noise, low drift; versatility and economy of the dual-slope
integrating AID converter. Features like true differential
input and reference, drift of less than 1/.tV/OC, maximum
input bias current of 10pA, and typical power consumption
of 20mW make the ICL7109 an attractive per-channel
alternative to analog multiplexing for many data acquiSition
applications.

PIN CONFIGURATION AND TEST CIRCUIT:
(See Figure 1 for typical connection to a UART or Microcomputer)

TOP VIEW

GN:~

"'~

ORDER
BYTE
OUTPUTS

{

ww{

ORDER
BYTE
OUTPUTS

BYTE {
CONTROL
INPUTS

1 GND
V+40
2 STATUS
REF IN-39
3 POL
REF CAP -38
4 OR
REF CAP + 37
5 B12
REF IN+ 36
6 Bll
IN HilS
7 Bl0
IN LO 34
8 B9
COMMON 33
9 B8
INT32
ICL7109
10 B7
AZ 31
11 B6
BUF 30
12 B5
REF OUT 29
13 B4
V-28
14 B3
SEND 27
15 B2
RUN/HOLD 26
16 Bl
BUF OSC OUT 25
17 TEST
OSC SEL 24
18 LBEN
OSC OUT 23
19 HBEN
OSC IN 22
20 CE/LOAD
MODE 21

!-o+5V

~l"F
1M!!
=.Ol"F

C'NTII
II CAZ .15"F"
... 33"F

)-o~ ":~ " ' ' ' lk!!

40·Pin
40·Pin
40·Pin
40·Pin

Package
Ceramic DIP
Ceramic DIP
CERDIP
Plastic DIP

Order Number
ICL7109MDL
ICL71091DL
ICL71091JL
ICL7109CPL

4·26

24k!!

~
.I-

(OUTLINE DWGS DL, JL, PL)

Temp. Range
-55·C to +125·C
-20·C to +85·C
-20·C to +85·C
O·Cto 70·C·

REF IN +
v+

.J-- GND

~

~

Part
7109
7109
7109
7109

---0

,J-

'R'NT

ORDERING INFORMATION

'v

DIFFERENTIAL
REFERENCE
+
INPUT HIGH
INPUT LOW
GND

3.5795 MHz
TV CRYSTAL

20kll FOR 0.2V REF
200kn FOR ~.ov REF

O~O[b

ICL7109
ABSOLUTE MAXIMUM RATINGS·
Positive Supply Voltage (GND to v+) ...................................... +6.2V
Negative Supply Voltage (GND to V-) ....................................... -9V
Analog Input Voltage (Lo or Hi) (Note 1) ................................ V+ to VReference Input Voltage (Lo or Hi) (Note 1) ............................. V+ to VDigital Input Voltage
'
V+ + 0.3V
(Pins 2-27) (Note 2) ................................................. GND - 0.3V
Power Dissipation (Note 3)
Ceramic Package .............................................. 1W @ +S5°C
Plastic Package ............................................ 500mW @ +70° C
Operating Temperature
Ceramic Package (MDU ............................... -55°C::; TA::; +125°C
(lDU ................................. -25°C::; TA::; +S5°C
Plastic Package
(CPU ................................... O°C::; TA::; +70°C
Storage Temperature ............................... : .... -55°C::; TA::; +125°C
Lead Temperature (soldering, 60 sec.) ..................... : ............. +300°C
I

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress
rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TABLE I OPERATING CHARACTERISTICS
All parameters with v+ = +5V, vTest circuit as shown on page 1.

= --5V,

GND

= OV, TA = 25°C,

unless otherwise indicated.

ANALOG SECTION
PARAMETER
Zero Input Reading

SYMBOL

Ratiometric Reading
Non-Linearity (Max deviation
from best straight line fit)
Roll-over Error (difference
in reading for equal pos. and
neg. inputs near full scale)
Common Mode Rejection Ratio

CMRR

Input Common Mode Range

VCMR

Noise (p-p value not
exceeded 95% of time)
Leakage current at Input

Supply Current V+ to V
Ref Out Voltage

TYP
±OOOOa

. MAX
+OOOOa

VIN = VREF
VREF = 204.SmV
Full Scale = 409.6mV to 4.096V
Over full operating temperature
range.
Full Scale = 409.6mV to 4.096V
Over full operating temperature
range.

3777a

3777a
4000a

4000a

-1

±.2

+1

Counts

-1

±.2

+1

Counts

VCM ±1V VIN = OV
Full Scale = 409.6mV
Input Hi, Input La, Common

50
V-+1.5

UNITS
Octal
Reading
Octal I
Reading

""V/v
V+-1.0·

V

VIN = OV
Full Scale - 409.6mV

hLK

VIN = 0 All devices 25° C
ICL7109CPL O°C::; TA::; +70°C
ICL71091DC -25°C::; TA::; +S5°C
ICL7109MDL -55°C::; TA::; +125°C
VIN = OV
VIN = 40S.9mV = > 7770a
reading
Ext. Ref. 0 ppm;oC

1
20
100
2
0.2(

10
100
250
5
1

pA
pA
pA
nA
jlVloC

1

5

ppm/DC

VIN = 0, Crystal Osc.
3.5SMHz test circuit
Pins 2-21, 25, 26, 27, 29, open
Referred to V+, 25kO
between V+ and REF OUT
25kO between V+ and REF OUT

700

1500

jlA

700

1500

jlA

-2.S

-3.2

V
ppm/oC

15

jlV

1+

Isupp
VREF

Ref Out Temp. Coefficient
Input Common Mode Range

MIN
-oOOOa

en

Zero Reading Drift
Scale, Factor Temperature
Coefficient
Supply Current V+ to
GND

CONDITIONS
VIN = O.OV
Full Scale = 409.6mW

VCM

IN HI, IN LO, COMMON
4-27

-i.4

SO
V- +1.5

V+ to O.5
V+ -1.0
V- +1.0

V

U~UIb

ICL7109
DIGITAL SECTION
PARAMETER
Output High Voltage

SYMBOL
VOH

Output Low Voltage

VOL

MIN
3.5

lOUT = 1.6mA

Output Leakage Current

Pins 3-16 high impedance

Control 1/0 Pullup
Current

Pins 18, 19, 20 VOUT = V+ -3V
MODE input at GND

Control I/O Loading

HBEN Pin 19 LBEN Pin 18

Input High Voltage
Input Low Voltage

II

CONDITIONS
lOUT = 100/lA
Pins 2-16, 18, 19, 20

VIH

Pins 18-21, 26, 27
referred to GND

Vil

Pins 18-21, 26, 27
referred to GND

,

TYP
4.3

MAX

0.2

0.4

V

±.01

±1

/lA

UNITS
V

5

/lA
50

pF
V

2.5
1

V

Input Pull-up Current

Pins 26, 27 VOUT = V+ -3V

5

/lA

Input Pull-up Current

Pins 17, 24 VOUT = V+ -3V

25

/lA

Input Pull-down Current

Pin 21

VOUT = GND +3V

5

/lA

Oscillator Output
Current

High
Lo"Y

OOH
OOl

VOUT = 2.5V
VOUT - 2.5V

1
1.5

rnA
rnA

Buffered Oscillator
Output Current

High
Low

BOOH
BOOl

VOUT = 2.5V
VOUT - 2.5V

2
5

rnA
rnA

tw

MODE Input Pulse Width
No. ,.
Note 2:

Note 3:

50

ns

Input voltages may exceed the supply voltages provided the input current is limited to ±100!'A
Due to the SCR structure inherent in the process usad to fabricate these devices, connecting any digital inputs or outputs to voltages
greater than V'+ or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources
other than the same powersupply be applied to the ICl71 09 before its power supply is established, and that in multiple supply systems
the supply to the ICL7109 be activated first.
This limit refers to that of the package and will not be obtained during normal operation.

+5V- 1 v+
2 OSC CONTROL
GND-r:: 3 GND
+5V- 4 RRD
5-12
RBRI-8

-

13 PE
14 FE
150E
+5V- 16 SFD

SEiiiAL

20 RRI

SEruAi:

25 TRO

TRC40 OSC IN 17
EPE 39
CLS138 f + 5 V
CLS237
SBS 36
PI35 -GND
CRL 34 26-33
TBRI-8
TRE 24 ORR 18
DR 19
TBRL 23
TBRE 22
MR 21 I-GND

INPUT

OUTPUT

GND- 1 GND
25 BUF OSC OUT
2 STATUS

-

I!--

8

3-8
B9-BI2.POL,OR
9-16
Bl-B8 _
17 TEST
18 LBEN
21 MODE
20 CE/LOAD
27 SEND

~1"F

J

OSC IN 2 2 1 L ] 3.58 MHz
CRYSTAL

FOR lOWEST POWER CONSUMPTION,
TBR1 TBRS INPUTS SHOULD HAVE 100kU

IM6403
CMOS UART

19 HBEN

V+40 -+5V
--GND
REF IN - 39
REF CAP - 38
EXTERNAL
REF CAP + 37
REFERENCE
REF IN + 36
+
lMfl
IN HI35
v· A
+ INPUT
=.OI"F
IN LO 34
GND
COM 33
INT .1SJ..'F
INT 32
II
.. CAZ
AZ 31
".33"F
BUF 30
~../'
REF OUT 29 IR!NT 20kfl 0.2V REF
200kfl2V REF
~28 I- -5V
RUN/HOLD 26 I- +5V OR OPEN
OSC SEL 24 I-GND
OSCOUT 23

ICL7109
CMOS AID CONVERTER

PULLUP RESISTORS TO +5V

Figure 1A. Typical Connection Diagram UART Interface - To transmit latest result, send any word to UART

r='D~
+5V

1

2
XTALI
1 TO
'
4'RESET
5 SS
6 INT

GN 0 - 7 EA
8 WR
9 PSEN
11 ALE
25 PROG
5Y'+
+5V - 26 VDD
39
TL
+5V +5 V- 40 VCC

-

GN 0 - 20 GND

3
XTAL2
21-24
35-38
P20-P27
31-34
PI4-P17

+SV- 40 V+
GND- 1 GND
17 TEST

-

~IOTHER
r+s-,
I/O

26 RUN/HOi])
2 STATUS
J18 LBEr-:
19 HBEN
3-8
.,
B9-BI2,POL,OR
9-16
Bl-B8
8
20 CE/LOAD

P1330
P1229
P11 28
Pl0 27

12-19
DBD-DB7
ROl0

r';
8

REF IN 39
REF CAP -38
REF CAP + 37
REF IN + 36
IN HI35
IN LO 34
COM 33
INT32
AZ31
BUF30
REF OUT 29
Y-28
SEND 27
BUF OSC OUT 25
OSC SEL 24
OSC OUT 23
OSC IN 22
MODE 21

.01"F
.. CAZ
...33"F
I--5V

-

+ INPUT
GND
CINTII·15"F
II

.~ J
RINT 20kfl 0.2V REF.
200 kfl2Y REF.

-GND

~ 3.58 MHz

-

ICL7109
CMOS AID CONVERTER

Figure 1B: Typical Connection Diag~am Parallel Interface With MCS-48 Microcomputer

4-28

+

lMfl

:;:

I

874818048

GND
EXTERNAL
R EFERENCE

~1"F

CRYSTAL

ICL7109
TABLE 2 - Pin Assignment and Function Description
PIN
, 1
2.

STATUS

3
4
5
6
7

17.

POL
OR
B12
Bll
Bl0
B9
B8
B7
B6
B5
B4
B3
B2
Bl
TEST'

'18

LBEN

8

,

'.'

SYMBOL
GND'

9·
10
11
12
.13
14
15
'16

19

20

HBEN

CE/LOAD

DESCRIPTION
bigital GroUnd, OV, Greund return fer all
digital legic
"
Output Highdu(ing integrate anddelntegrate until data is latched ..
Output Lew when analeg. section. is in
Aute-Zero cenflguratien.
Pelarity - HI fer Positive Input.
Overrange- HI If Overranged.
Bit 12 IMest Signifi~t Bi!!...-....,.
Bit 11
All
Bit 10
three
Bit9
state
Bit 8
.output
Bit 7 HI= true'
data
Bit6
bits
Bit 5
Bit 4
Bit3
___ --C_-.:
Bit2
BiU
ILeast Significant Bitl
Input High - Nermal Operation.
Input Lew - Fercesall bit .outputs high.
Nete: Thisinput is used fer test purpeses
.only.
Lew Byte Er:table - With Mede (Pin 211 lew,
and CEi'IOAD (Pin 201 lew, taking this pin
low activates lew order byte .outputs Bl-B8.

:

22
23
24

25
26

27

- With M.ode IPin 211 high, this pinserves as
a lew byte flag .output used in handshake
mede. See Figures 7, 8, 9.
High Byte Enable - With Mede (Piii 2H1ew,
and CEiLOAD (Pin 201 lew, taking this pin
lew activates high .order byte .outputs B9B12,POL, OR.

28
29
30
31
32
33

- With Mode (Pin 211 high, this pin serves as
a high byte flag .output used in handshake
mede. See Figures 7, 8, 9..
Chip Enable Lead - With Mede(Pin 211 low,
CEILOAD serves as a master .output enable.
When high, Bl-B12, POL, OR .outputs are
disabled.

34
35
36
37
38
39
40

- With Mede (Pin 211 high, this pin serves as
a lead strobe used in handshake mede.
See. Figures 7, 8, 9.
No~:

DESCRIPTION
Input Low - Direct .output mode where
CE/LOAD IPin 201, HBEN (Pin 191 and
LBEN (Pin 181 act as inputs directly
centre.lling byte .outputs.
, Input Pulsed High - Causes immediate
entry i nte handshake mede and .output .of
data as in Figure 9.
Input High - Enables CEILOAD (Pin 201,
HBEN (Pin 191, and LBEN (Pin 181 as .outputs, handsh!ike mede will-be entered and
data .output as in Figures 7 and 8 at cenversien completien.
OSCIN
Oscillater Input
OSC OUT
Oscillater Output
OsciliaterSelect - Input high cenfigures
OSC SEL
OSC IN, OSC OUT, BUF OSC OUT as RC
.oscillator - cleck will be same phase and
duty cycle as BUF OSC OUT.
- Input lew configures OSC IN, OSC OUT
for crystal oscillator - clock frequency will
be 1/58 of frequency at BUF OSC OUT.
BUF OSC OUT Buffered OSCillator Output
RUNIHOLD
Input High - ConversiOnS centinuously
performed every 8192 cleck pulses.
Input Low - Conversion in progress completed, cenverter will stop in Aute-Zero 7
counts before integrate.
SEND
Input - Used in handshake mode to indicate
ability of an external. device to accept data.
VAnalog Negative Supply- Neminally-5V
witl1respect to GND IPin 11.
Reference Voltage Output - Nominally 2.8V
REF OUT
dewn from V+ (Pin 401.
BUFFER
Buffer Amplifier Output
AUTO-ZERO
Auto-Zero Nede - Inside foil OfCAZ
INTEGRATOR Integrator Output - Outside foil .of CINT
Analeg Common - System is Auto-Zeroed
COMMON
te.COMMON
INPUT LO
Differential Input Lew Side
INPUT HI
Differential Input High Side
Differential Reference Input Positive
REF IN +
Reference Cap'lcitor Positive
REF CAP +
REF CAPReference Capacitor Negative
Differential Reference Input Negative
REF IN.V'
Positive Supply'voltage - Nominally +5V
\'{ith respect to GNDIPin lL

PIN
SYMBOL
21
'MODE

All digital levels are pesitive true:

DETAILE,D DESCRIPTION
Analog Section
Figure 2 shows, the equivalent circuit of the Analog Section
of the IGL7109. When the RUN/ROT]) inpu.! is left open or
conr:1ected to V+, the circuit will perform conitersionsata rate
determined by the clock frequency (8192 clock periods per
cycle). Each measurement cycle is divided into three phases
as shown in Figure 3. They are (1) Auto-Zero (AZ), (2) Signal
'Integrate liNT) and (3) Deintegrate (DEI.

the buffer amplifier, integrator; and comparator. Since
the comparator is included in the loop, the AZ accuracy
,is limited only by the qoise of the system. In any case, the
offset referred tei the Input Is less than 10!'V.
2. Signal Integrate Phase
During Signal integrate ttie auto-zero loop is opened, the
internal sh9rt is removed and the internal input high and
low are connected to the external pins. The converter
then integrates the differential voltage between IN HI and
IN LO for a fixed time of 2048 clock periods. Note that
this differential voltage can be within the common mode
range of the inputs~ At t~e end of this phase, the polarity
of the integrated Signal is determined.

1. Auto-Zero Phase
During auto-zero three things happen. First, Input high
and I.ow are disconnected .from their pins and internally
. shorted to analog COMMON. Second, the reference capaCitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the autozero capacitor CAZ to compensate for offset VOltages In
4-29

O~OIL

ICL7109
RINT

r-_ _ _---il-'C:..:.R""E~F_ _ __,

,--I

REF CAP

+

REF IN

+

REF IN-

CAZ

BUFFER

AZ
------

.--_ _ _ _ _-'-.;30

31

I
I

INPUT HIGH

I
(Jr--{)(r-.,.-t----.,.---t-----i
35

1

I
I

I
1

I
I

COMMONar---+-.---~

6.2V

33

1

AZ- FROM CONTROL
INT LOGIC
DEINT (+) DIGITAL SECTION
DEINT(-)-

liNT

I

INPUTLO$-~>(r--~----------------~

134

I
1

IL

_____________________ _

~

40

v-

REF OUT

v+

Figure 2: Analog Section
POLARITY
DETECTED
INTEGRATOR
OUTPUT
.
INTERNAL CLOCK

1

I

I

1.-.

n.r 1.fUlJl....

I

I

I
I,
I

I

I

I

n

I

I

I

I

I

I
I

I--COUNTS

I.

I

I

MIN.

.

/DETECTED

FIXED

2048.1

1I

COUNTS

NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V,N

I
I

DEINT PHASE 1II---1-AZ-

~ ~

I
2048

1/
~;2

"._v:_~~1
~ 1""'1 ~

~ PHASE I--I-INT
PHASE II '. i.
1
I ,

INTERNAL LATCH I
STATUS OUTPUT

ZERO CROSSING
OCCURS
ZERO CROSSING

I

'l..I1IlIU1..r

I

.

I

I
I

I

I
I

.I'

4096 COUNTS--t

I

1

I

I

MAX
"""AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION

Figure 3: Conversion Timing (RUN/HOLD Pin High)

3. De-integrate Phase
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and
input high is connected across the previously charged
(during. auto-zero) reference capacitor. Circuitry within
the chip ensures that the capacitor will be connected
with the correct polarity to cause the integrator output to
return to zero crossing (established In Auto Zero) with a
fixed slope. Thus the time for the output to return to zero
(represented by the number of clock periods counted). is
proportional to the input signal.

positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale with some loss of accuracy. The
integrator output can swing within 0.3 volts of either supply
without loss of linearity.
.
The ICL7109 has, however, been optimized for operation
with analog common near digital ground. With power
supplies of +5V and -5V, this allows a 4V full scale integrator
swing positive or negative maximizing the performance of
the analog section.

Differential Input

Differential Reference

The input can accept differential voltages anywhere within
the common mode range of the input amplifier; or
specifically from 1.0 volts below the positive supply to 1.5
volts above the negative supply. In this range the system has
a CMRR of 86dB typical. However, since the integrator also
swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive common
mode voltage with a nearfull-scale negative differential input
voltage. The negative input signal drives the integrator

The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge ·to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to deintegrate a positive signal but
lose charge (decrease voltage) when called uptQ deintegrate
a negative input signal. This difference in reference for (+) or
H input voltage will give a roll-over error. However; by
4-30

O~OIL

ICL7109
selecting the reference capacitor large enough in
comparison to the stray capacitance, this error can be held to
less than 0.5 count for the worst case condition (see
Component Values Selection belowl.
The roll-over error from these sources is minimized by
having the reference common mode voltage near or at
analog COMMON.

Component Value Selection
For optimum performance of the analog section, care must
be taken in the selection of val ues for the integ rator capacitor
and resist9r, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
The most important consideration is that thE:! integrator
output swing (for full-scale input) be as large as possible. For
example, with ±5V supplies and COMMON connected to
GND, the nominal integrator output swing at full sc?le is ±4V.
Since the integrator output can go to 0.3V from either supply
without significantly affecting linearity, a 4V integrator
output swing allows 0.7V for variations in output swing due
to component value and oscillator tolerances. With ±5V
supplies and a common mode range of ±1V required, 'the
component values should be selected to provide ±3V
integrator output swing. Noise and. rollover errors will be
slightly worse than in the ±4V case. For larger common mode
voltage ranges, the integrator output swing must be reduced
further. This will increase both noise and rollover errors. To
improve the performance, supplies of ±6V may be used ..
1. Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100/LA of quiescent current. They supply 20jJ.A of drive curren't with negligible nori-linearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 4.096 volt full scale, 200k!l is
near optimum and similarly a 20k!l for a 409.6mV scale.
For other values of full scale voltage, RINT should be
chosen by the relation
R
INT -

full scale voltage
20/LA

2. Integrating Capacitor
The integrating capacitor CINT should be selected to give
the maximum integrator output voltage swing without
saturating the integrator (approximately 0.3 volt from
either supplyl. For the ICL7109 with ±5 volt supplies and
analog common connected to GND, a ±3.5 to ±4 volt integrator output swing is nominal. For 7~1/2 conversions per
second (61.72KHz clock frequency) as provided by the
crystal oscillator, nominal values for CINT and CAl are
0.15/LF and 0.33/LF, respectively. If different clock frequencies are used, these values should be changed to
maintain the integrator output voltage swing. In general,
the value of CINT is given by
(2048 x clock period) (20JLA)
CINT =

integrator output voltage swing

An additionai requirement of the integrating capaCitor is
that it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for
this application, polypropylene capacitors give undetectable errors at reasonable cost up to 85° C. Forthe military
temperature range, Teflon® capaCitors are recommen-

ded. While their dielectric absorption characteristics vary
somewhat from unit t9 unit, selected devices should give
less than 0.5 count of error due to dielectric absorption.
3. Aulo-Zero'Capacilor
The size of the auto-zero capacitor has some influence on
the noise of the system; a big capacitor, giving less noise.
However, it cannot be increased without limits since it, in
parallel with the integrating capacitor forms an R-C time
constant that determines the speed of recovery from overloads and more important the error that exists at the end
of an auto-zero cycle. For 409.6mv full scale where noise
is very important and the integrating resistor small, a
value of CAl twice CINT is optimum. Similarly for 4.096V
full scale where recovery is more important than noise, a
value of CAl equal to half of CINT is recommended.
For optimal rejection of stray pickup, the outer foi I of CAl
should be connected to the R-C summing i,unction and
the inner foil to pin 31. Similarly the outer foil of CINT
should be connected to pin 32 and the inner foil tothe R-C
summing junction. Teflon®, or equivalent, capacitors are
recommended above 85'C for their low leakage'
characteristics.
4. Reference CapaCitor
.
'
.
A 1/LF capaCitor gives good results in most applications.
However, where a large common mode voltage exists (i.e. ~
the reference low is not at analog common) and a 409.6mV
scale is used, a larger value is required to prevent (oil-over
error. Generally 10/LF will hold the roll-over error to 0.5
count in this instance. Again, Teflon®, or equivalent
capacitors should be used for temperatures above 85°C
for their low leaka,ge characteristics.
5. Referer:lce Voltage
'- The analog input required to generate a full scale output
of 4096 counts is VIN = 2VREF. Thus for a normalized scale,
a reference of 2.048V should be used for a 4.096V full
scale, and 204.8mV should be used for a 0.4096V full
scale. However, in many applications where the AID is
sensing the output of a transducer, there will exist a scale.
factor other than unity between the absolute output
voltage to be measured and a desired digital output. For
instance, in a weighing system, the designer might like to
have a full scale reading when the voltage from the transducer is 0.682V. Instead of dividing the input down to
409.6mV, the input voltage should be measured directly
and a reference voltage of 0.341V should be used. Suitable values for integrating resistor and capacitor are 34k
and 0.15/LF. This a.voids a divider on the input. Another
advantage of this system occurs when a zero reading is
desired for non-zero input. Temperature and weight
measurements with an offset or tare are examples. The
offset .may be introduced by connecting the voltage
output of the transducer between common and analog
high, and the offset voltage between common and analog
low, observing polarities carefully. However, in processor-based systems using the ICL7109, it may be more
efficient to perform this type of scaling ortare subtraction,
digitally using software.
.
. 6. Reference Sources
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The resolution of the ICL7109 at 12 bits is one part in 4096, or
244ppm. Thus if the reference has a temperature coefficient of 80ppmfOC (on board reference) a temperature
difference of 3° C will introduce a one-bit absolute error.

II

4-31

ICL7109
,I.;'

For thi$ reawn, it is recommended that an external highquality reference be used where the ambient temperature is
not controlled or where high-accuracy absolute measurements are being made_

converter.. W.hen the MODE pin is low or left open (this input
is provided with a pulldown resistor to ensure a low level
when the pin is left open), the converter is in its "Direct",
output mode, where the output data is directly accessible "
under the control of the chip and byte enable inputs. When '
the MODE input is pulsed high,Hie converter enters the
UAFlT handshake mode and outputs the data in two bytes,
then returns to "direct" mode. When the MODE input is left '
high, the converter will output data in the handshake mode at ' ,J.
the end of every conversion cycle. (See section entitled
"Handshake ,Mode" for further details),

The ICl7109 provides a REFerence OUTput (pin 29) which
may be used with a resistive divider to generate a suitable
reference voltage. This output will sink up tO,about 20mA
without significant variation in output voltllge, ,and is pro'
videdwith a pUIiUp bias device which sources about 10,..A.
The output voltage is nominally 2.8V below V+, and has a
temperature coefficient of ± 80ppm/·C typo When using the
onboard reference, REF OUT (Pin 29) should be connected
to REF - (pin 39), and REF + $hould be connected to the
wiper of a precision potentiometer between REF OUT and
V +. The circuit for a 204;8mV reference is shown In the test.
circuit. For a 2.048mV reference, the fixed resistor should be
removed, and a 25kO precision potentiometer between REF
OUT and V+ shoulq be used. '
Note that If, pins 29 and 39 are tied together and pins 39 and
40 accidentally shorted (e.g., during testing), the reference
. supply will sink enough current to destroy the device. This
can be avoided by placing a 1kO resistor in series with pin 39.

II

STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Signal Integrate (Phase II), and goes low
one-half clock period after new data from the conversion "
has been stored in the output latches. See Figure 3 for
details of this timing. This signal may be used as a "data ' ",
valid" flag (data never changes while STATUS Is low) to drive
interrupts, or for monitoring the staWs of the converter.
RUN/HOlP Input
When the RUN/HOLD input is high, or left open, the circuit , •
will continuously perform conversion cycles, updating the
output latches !lfter zero crossing during the Deintegrate ,"
(Phase III) portion of the conversion cycle (See Figure 3), In
this mode of operation, the conversion cycle will be
performed in 8192 clock periods, regardless afthe resulting ', .

DETAILED DESCRIPTION
Digital Selection

"

'

The digital section includes the clock oscillator and scaling
. circuit, a 12-bitbinarycounter with output latches and nlcompatible three-state output drivers, polarity, over-range,
and control logic, and UART handshake logic, as shown in
the Block Diagram, Figure4.

~~

Throughout this description, logic levels will be referred to
as "low" or "high". The actual logic levels are defined in
Table 1 "Oper!lting Characteristics". For minimum power
consumption, all inputs should swing from GND (Iowtto V+
(high). Inputs driven from TTL gates should have 3-5kO pullup resistors added for maximum noise immunity,
MODE Input
.The MODE inpulis used to control the output mode aLthe

,

,t

TEST

t

,

,

If RUN/HOLD goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred, the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate, the timespent in'
Deintegrate !lfter the zero-crossing. If· RUN/HOLD stays or
goes low; the converter will ensure minimum Auto-Zero
time, and then wait in Auto-Zero until the RUN/HOLD input,
goe~ high. The converter will begin the Integrate (Phase II) '!.. ,.'
, portion'of the next conversion (and the STaTuS output will ",,'
go high) seven clock periods after the high level is detected at'
RUN/HOLD. See Figure 5 for details.
, '

HrGH ORDER
- BYTE OUTPUTS "
"
'B B B B
POL OR 12 11 10 9

;-;1'

B
8

LOW ORDER
'BYTE,OUTPUTS,,'
B B B B B B B
76 5 4 3 2 1

17

1--_ _t-;ltji8_'(j) LiiEN
1---.....t---.1<;i9-. RUN/HOLD may
now go low terminating Deintegrate and ensuring a minimum
Auto-Zero time before stopping to wait forthe next conversion.
Alternately, RUN/HOLD can be used to minimize conversion
time by ensuring that it goes low during Deintegraie, after
zero crossing, and goes high after the hold point is reached.
The required activity on the RUN/HOLD input can be
provided by connecting it to the Buffered Oscillator Output.
In this mode the conversion time is dependent on the input
value measured. Also refer to Intersil Application Bulletin
A032 for a discussion of the effects this will have on AutoZero performance.·

HBEN
ASINPUT.u..J-I..L.J..L~

LBEN
AS INPUT J.J.J-I..L.J..L~

HIGH BYTE _____ _
DATA

DATA
----

tOAB
tOHB
tCEA
tOAC
tOHC

TYP

220

Data Hold Time
from Byte Enable
Chip Enable Width
Data
from
Data
from

Access Time
Chip Enable
Hold Time
Chip Enable

400

MAX

UNITS
ns

210

350

ns

150
260

300

ns

260

400

ns

240

400

ns

~

--.
IDHCii.I

DATA
VALID

HIGH IMPEDANCE

Figure 6: Direct Mode Output Timing

It should be noted that these control inputs are
asynchronous with respect to the converter clock - the data
may be accessed at any time. Thus it is possible to access the
data while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STATUS output will prevent this.
Data is never updated while STATUS is low.
Handshake Mode
The handshake output mode is provided as an alternative
means of interfaCing the ICL7109 to digital systems, where
the AID converter becomes active·in controlling the flow of
data instead of passively responding to chip and byte enable
inputs. This mode.is specifically designed to allow a direct
interface between the ICL7109 and industry-standard
UARTs (such as the Intersil CMOS UARTs, IM6402/3) with no
external logic required. When triggered into the handshake
mode, the ICL7109 provides all the control and flag signals
necessary to sequence the two bytes of data into the UART
and initiate their transmission in serial form. This greatly
eases the task and reduces the cost of designing remote data
acquisition stations using serial data transmission to
minimize the number of lines to the central controlling
processor.

Table 3 - Direct Mode Timing Requirements

350

-

LOW BYTE _ _ _ _ _ _ _ _ _ _ _ _ _ _ ... 1-_

Direct Mode

MIN

- - - ; .....

IOAC--

When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity
and over-range high order byte) are accessible under control
of the byte and chip enable terminals as inputs. These three
inputs are all active low, and are provided with pullup
resistors to ensure an inactive high level when left open.
When the chip enable input is low, taking a byte enable input
low will allow the outputs of that byte to become active
(three-stated on). This allows a variety of parallel data
accessing teChniques to be used, as shown in the section
entitled "Interfacing." The· timing requirement~ for these
outputs are shown in Figure 6 and Table 3.

DESCRIPTION
Byte Enable Width
Data Access Time
from Byte Enable

~

AS INPUT

If the RUN/HOLD input goes low and stays low during AutoZero (Phase D, the converter will simply stop at the end of
Auto-Zero and wait for RUN/HOLD to go high. As above,
Integrate (Phase II) begins seven clock periodsafterthe high
level is detected.

SYMBOL
tBEA

tCEA

r

CE/LOAD~.

Entry into the handshake mode is controlled by the MODE
pin. When the MODE terminal is held high, the ICL71 09 will
enter the handshake mode after new data has been stored in
the output latches at the end of every conversion performed
(See Figures 7 and 8>' The MODE terminal may also be used
to trigger entry into the handshake mode on demand. At any
time during the conversion cycle, the low to high transition of
a short pulse at the MODE input will cause immediate entry

ns

4-33

ICL7109
zeRO CROSSING

/9CCURS
INTEGRATOR
OUTPUT

INTERNAL

CLOCK

ZERO CROSSING

/DETECTED

f'.
""
-.S h--f--

.r-

INTERNAL
LATCH

----

~

----~-

II-

STATUS
OUTPUT
MODE
INPUT
MODe HIGH ACTIVATES
UART
INTERNAL
MODE NORM

CE7rnAI>, ~.

[BEN

TERMINATES

SEND

SEND

____ SENSED~

1\\

SEND
INPUT

SENSED""

~

/

I \\
\

\\
HIGH BYTE
DATA

/

-------- ------

__ .i_.

~

IN HANDSHAKE MODe
DISABLES OUTPUTS CE/LOAD, HBEN, LBEN

DATA VALID

---------

~--

------------ --- --------- --mliI""DONTCARE

L

MODE LOW, NOT

\
LOW BYTe
DATA

I,-.i~_i_

/

\

UARTMODE

DATA VALID

---~:S===
---------

_J._~_ ~·THREE.STATE WITH PULLUP

- - - - '" THREE·STATE HIGH IMPEDANCE

Figure 7: Handshake With Send Held Positive

INTE~~~~~~

I

ZeRO CROSSING
OCCURS

ZERO

C~OSSING

_ _ _~:-_-¥-,D:::ETECTED

INTERNAL
CLOCK
INTERNAL
LATCH

STATUS
OUTPUT

MODE
INPUT

---------1

---:~_-~_-~r~

INTERNAL UART
MODE ;;N;;O;;;RM"--'-_ _ _ _....,.f

~

SEND
SENSED

SEND INPUT
(UART TBRE)

CEiLOAD OUTPUT
(UARTTBRL)

--------1

HIGH BYTE

DATA

LOW BYTE
DATA

-------~ ~--

B=DONTCARE

-

DATA VALID

- - - - = THREE-STATE HIGH IMPEDANCE

Figure 8: Handshake - Typical UART Interface Timing

4-34

~----

ICL7109
byte enable as an output may be used as a byte identification flag. With SEND remaining high the converter
completes the output cycle using CE/LOAD and LBEN'while
the low order byte outputs (bits 1 through 8) are activated.
The handshake mode is terminated when both bytes are
sent.
Figure 8 shows an output sequence where the SEND input is
used to delay portions of the sequence, or handshake. to
ensure correct data transfer, This timing diagram shows Ull
relationships that occur using an industry-standard
IM6402/3 CMOS UART to interface to serial data channels.
In this interface, the SEND input to the ICL71 09 is driven by
the TBRE (Transmitter Buffer Register Empty) output of the
UART, and the CE/LOAD terminal of the ICL7109 drives the
TBRL (Transmitter Buffer Register Load) input to the UART.
The data outputs are paralleled into the eight Transmitter
Buffer Register inputs.

into the handshake mode. If this pulse occurs while new data
is being stored, the entry into handshake mode is delayed
until the data is stable. While the converter is in the handshake mode, the MODE input is ignored, and although
conversions will still' be performed, data updating will be
inhibited (See Figure 9) until the converter completes the
output cycle and clears the handshake mode.
When the converter enters the handshake mode, or when the
MODE input is high, the chip and byte enable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle (See Figures 7, 8, and 9),
In handshake mode, the SEND input is used by the converter
as an indication of the ability of the receiving device (such as
a UART) to accept data.
Figure 7 shows the sequence of the output cycle with SEND
held high. The handshake mode (internal MODE high) is
entered after the data latch pulse (since MODE remains high
the CE/LOAD, LBEN and HBEN terminals are active as
outputs). The high level at the SEND input is sensed on the
same high to low internal clock edge. On the next lowto high
internal clock edge, the CE/LOAD and the HBEN outputs
assume a low level, and the high-order byte (bits 9 through
12, POL, and OR) outputs are enabled. The CE/LOAD output
remains low for one full internal clock period only, the data
outputs remain active for 1-1/2 internal clock periods, and
, the high byte enable remains lowfortwoclock periods, Thus
the CE/LOAD output low level or low to high edge may be
used as a synchronizing signal to ensure valid data, and the

Assuming the UART Transmitter Buffer Register is empty,
the SEND input will be high when the handshake mode is
entered after new data is stored. The CE/LOAD and HBEN
terminals will go low after SEND is sensed, and the high
order byte outputs become active. When CE/LOAD goes
high at the end of one clock period, the high order byte data
is clocked into the UART Transmitter Buffer Register. The
UART TBRE output will now go low, which halts the output
cycle with the HBEN output low, and the high order byte
outputs active, When the UART has transferred the data to
the Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high, On the next ICL7109

ZERO CROSSING
OCCURS
/

_---'~_ _-+'/'--Z-ERO CROSSING QETECTED

::,::~:::~
LATCH

STATUS
OUTPUT
POSITIVE TRANSITION CAUSES
MODE ENTRY
INTO
INPUT
UART MODE

~

,

INTERNAL UART
MODE -NORM

I~~~~~/

1-_+-_1-_ _ _ ___1 _-+----'t""-',.;;.,;;.;.;,...,L..-.......,

,m$mlmmmmmll
j2.

DEINT
PHASE III

STATUS OUTPUT -'"
UNCHANGED IN
UART MODE

_-+--+---

'm.m~mmmmm:
'm~m~mmmml ~m~~
~
~
~

___

II

SENSED

AS't~~~~~ _.i __ L_.u---' --'--000{

'--_-F

L_L
HIGH~1~!

----- _____ 1------ 1'-_-,-_ _
----'-------i ""-'--+--i
"'1'

LBEN _ .i_-1 __ .v-----'

__1

>-,

'------I
LOW~!~i

------------f
. . '" DON'T CARE

J-------------{ J - - -

---

=:

THREE-STATE HIGH IMPEDANCE

_.1_ == THREE-STATE WITH PUlLUP

Figure 9: Handshake Triggered By Mode

4-35

DATA VALID

4

U~UIL

ICL7109
v+--~------~--

internal clock high to low edge, the high order byte outputs
are disabled, and one-half internal clock later, the HBEN
output returns high. At the same time, the CE/LOAD and
LBEN outputs go low, and the low order byte outputs
become active. Similarly, when the CE/LOAD returns high at
the end of one clock period, the low orderdata is clocked into
the UART Transmitter Buffer Register, and TBRE again goes
low. When TBRE returns to a high it will be sensed on the
next ICL7109 internal clock high to low edge, disabling the
data outputs. One-half internal clock later, the'handshake
mode will be cleared, and the CE/LOAD, HBEN, and LBEN
terminals return high and stay active (as long as MODE stays
high).

24

-~;c
SEL

22

23

25

osc

OSC
OUT

BUFFERED
OSC
OUT

----

IN

GND

0

----

CRYSTAL

Figure 11: Crystal Oscillator
oscillator will operate with most crystals in the 1 to 5MHz
range with no external components. Taking the OSCILLATOR
SELECT input low also inserts a fixed .758 divider circuit
between the BUFFERED OSCILLATOR OUTPUT and the
internal clock. Using an inexpensive 3.58MHz TV crystal, this
division ratio provides an integration time given by:

With the MODE input remaining high as in these examples,
the converter wili output the results of every conversion
except those completed duringa handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure9 shows a handshake
output sequence triggered by such an edge. In addition, the
SEND input is shown as being low when the converter enters
handshake mode. In this case, the whole output sequence is
controlled by the SEND input, and the sequence for the first
(high order) byte is similar to the sequence for the second
byte. This diagram also shows the output sequence taking
longer than a conversion cycle. Note that the converter still
makes conversions, with the STATUS output and
RUN/HOLD input functioning normally. The only difference
is that new data will not be latched when in handshake mode,
and is therefore lost.

T

= (2048 clock periods) X

58)
( 3.58MHz

.
= 33.18ms

This time is very close to two 60Hz periods or 33.33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
If at any time the oscillator is to be overdriven, the overdriving signal should be applied atthe OSCILLATOR INPUT,
and the OSCILLATOR OUTPUT should be left open. The
internal clock will be of the same frequency, duty cycle, and
phase as the input signal when OSCILLATOR SELECT is left
open. When OSCILLATOR SELECT is at GND, the clock will
be a factor of 58 below the input frequency.

Oscillator
The ICL7109 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated as an RC or crystal
oscillator. The OSCILLATOR SELECT input changes the
internal configuration of the oscillator to optimize it for RC
or crystal operation.

When using the ICL7109with the IM6403 UART, it is possible
to use one 3.58MHz crystal for both devices. The BUFFERED
OSCILLATOR OUTPUT of the ICL7109 maybe used to drive
the OSCILLATOR INPUT of the UART, saving the need fora
second crystal. However, the BUFFERED OSCILLATOR
OUTPUT does not have a great deal of drive, and when driving.more than one slave device, external buffering should be
used.
Test Input
When the TEST input is taken to a level halfway between V+
and GND, the counter"output latches are enabled, allowing
the counter contents to be examined anytime.

When the OSCILLATOR SELECT input is high or left open
(the input is provided with a pullup resistor), the oscillator is
configured for RC operation, and the internal clock will be
of the same frequency and phase as the signal at the
BUFFERED OSCILLATOR OUTPUT. The resistor and
capacitor should be connected as in Figure 10.. The circuit
will oscillate at a frequency given by f = .45/RC. A 100kO
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 2048 clock periods is close to an integral
multiple of the 60Hz period.

When the TEST input is connected to GND, the counter
outputs are' al.1 forced into the high state, and the internal
clock is disabled. When the input returns to the 1/2 (V+ -GND)
voltage (or to V+) and one clock is applied, all the counter
outputs will be clocked to the low state. This allows easy
testing of the counter and its outputs.

INTERFACING
24

Direct Mode
Figure 12 shows some of the combinations of chip enable
and byte enable control signals which may be used when
interfacing the ICL7109 to parallel data lines. The CE/LOAD
input may be tied low, allowing either byte to be controlled
by its own enable as in Figure 12A. Figure 128 shows a
configuration where the two byte enables are connected
together. In this configuration, the CE/LOAD serves as a
chip enable, and the HBEN andLBEN may be connected to
GND or serve as a second chip enable. The 14 data outputs
will all be enabled simultaneously. Figure 12C shows the
HBEN and LBEN as flag inputs, and CE/LOAD as a master
enable, which could be the READ strobe available from most
microprocessors.

25

-10~

BUFFERED
OSC
OUT

SEL

I

v+ 9 R OPEN L -_ _ _+_~
Jose

~

.45/RC

Figure 10: RC Oscillator
When the OSCILLATOR SELECT input is Iowa feedback device and output and input capacitors are added to the
oscillator. In this configuration, as shown in Figure 11, the
4·36

ICL7109
A.

O~OIb

GND-_._----,

B.

CHIP SELECT 1

GND

CHIP SELECT

c.

89-812
POL, OR

89-812
POL, OR
81-812
POL, OR

81-88
ANALOG
IN

81-88

ICL7109

ICL7109

ANALOG
IN

RUN/HOLD 1 - - - CONVERT

ICL7109

ANALOG
IN

RUN/HOLD 1 - - - CONVERT

RUN/HOLD "c--OC":"NC"":V=ERC"::T

CHIP s~~~c~~ - - + - - - '

CONTROL

8YTE FLAGS

Figure 12: Direct Mode Chip and Byte Enable Combinations
Figure 13 shows an approach to interfacing severallCL7109s
to a bus, ganging the HBEN and LBEN signals to several
converters together, and using the CE/LOAD inputs
(perhaps decoded from an address) to select the desired
converter.

access the data. This application also shows the RUN/HOLD
input being used to initiate conversions under software
control.
A similar interface to Motorola MC6800 or MOS Technology
MCS650X systems is shown in Figure 16. The high to low
transition of the STATUS output generates an interrupt via
the Control Register B CB1 line. Note that CB2 controls the
RUN/HOLD pin through Control Register B, allowing
software-controlled initiation of conversions in this system
also.

Some practical circuits utilizing the parallel three-state
output capabilities of the ICL7109 are shown in Figures 14
through 19. Figure 14 shows a straightforward application to
the Intel MCS-48, -80 and -85 systems via an 8255PPI, where
the ICL71 09 data outputs are active at all times. The I/O ports
of an 8155 may be used in the same way. This interface can
be used in a read-anytime mode, although a read performed
while the data latches are being updated will lead to
scrambled data. This will occur very rarely, in the proportion
of setup-skew times to conversion time. One way to
overcome this is to read the STATUS output as well, and if it
is high, read the data again after a delay of more than 1/2
converter clock period. If STATUS is now low, the second
reading is correct, and if it is still high, the first reading is
correct. Alternatively, this timing problem is completely
avoided by using a read-after-update sequence, as shown in
Figure 15. Here the high to low transition of the STATUS
output drives an interrupt to the microprocessor causing it to
CONVERTER
SELECT

Figure 17 shows an interface to the Intersil IM6100 CMOS
microprocessor family using the IM6101 PIE to control the
data transfers. Here the data is read by the microprocessor in
an 8-bit and a 6-bit word, directly from the ICL7109 to the
microprocessor data bus. Again, the high to low transition of
the STATUS output generates an interrupt leading to a
software routine controlling the two read operations. As
before, the RUN/HOLD input to the ICL7109 is shown as
being under software control.
The three-state output capability of the ICL7109 allows
direct interfacing to most miCroprocessor busses. Examples
of this are shown in Figures 1, 18 and 19. It is necessary to

CONVERTER
SELECT

CONVERTER
SELECT

8-81T 8US
GND

GND
MODE

CE/LOAD

GND
MODE

89-812
POL, OR

CE/LOAD

MODE

ICL7109

ICL7109
81-88

81-88

8

ANALOG
IN
RUN/HOLD!--- +5V

8

ANALOG
IN
RUN/HOLDr--- +5V

8YTE SELECT FLAGS

6

ICL7109
81-88

ANALOG
IN

CE!LOAD
89-812
POL, OR

89-812
POL,OR

<

Figure 13: Three-stating Several 7109's to a Small Bus
4-37

r - - - +5V

II
~

ICL7109
carefully consider the system timing in this type of interface,
to be sure that requirements for setup and hold times, and
minimum pulse widths are met. Note also the drive limitations on long b-usses. Generally this type of interface is only
favored if the memory peripheral address density is low so

that simple address decoding can be used. Interrupt.
handling can also require many additional components, and
using an interface device will usually simplify the system in
this case.

(

ADDRESS BUS

~

CONTROL BUS

j

11

·1

1

1

(

II

1

1

11

1

DATA BUS
GND

I

I

MODE

CE/LOAD
B9-B12
POL, OR

~J t} ~l

RD

6

WR

D7-DO

J

11 11 11

AO-Al

cs

PAs-PAo

j

V

--

RUN/HOLD - + 5 V
-ICL7109

8

~

Bl-BB
STATUS

IN

GND

HBEN

LBEN

j

I

B

PB7-PBo

r-SEETeX'T-

B255
(MODE 0)

BOOB, B080,
B085, 8048 ETC

PCs

,

Figure 14: Full-time Parallel Interface to MCS-4S, -SO, -S5 Microcomputer Systems

?

ADDRESS BUS

)

CONTROL BUS

~

II

I

1

1

?

-I

1

J:l
1 J

1

DATA BUS
GND

,

I

I

MODE

CE/LOAD

1J
RD

B9·B12
POL,OR

6

GND

STATUS

1

~J

AO-Al

LBEN

I

f} ~l

cs

B255
Bl-BB

--

1J

pc,

ICL7109

HBEN

D7-DD

V

--

IN

t}

PAs-PAo

RUN/HOLD

8

WR

B

1
"
sIBA

II

l~'F

8008,8080,
8085, 8048 ETC

PB7-PBo

PC4

10kll

+5V
SEE TEXT

pc,

INTRA

INTR

"

Figure 15: Full-time Parallel Interface to MCS-4S, -SO, -S5 Microcomputers With Interrupt

4':38

j

\

D~DIb

ICL7109
GND
MODE
B9-B12
PAO-5
POL, OR 1--_6_--,,/

CRB 1--llR-Oll

MC680X

ICL7109
Bl-BB

8

OR

PBO-7

MCS650X
MC6820

ANALOG
IN

STATUS 1 - - - - - j C B l
RUN/iii5i:ii i - - - - - 1 C B 2

GND - - 4 - -....- - '

ADDRESS
BUS

DATA
BUS

CONTROL
BUS

Figure 16: Full-time Parallel Interface to MC680X or MCS650X Microprocessors

f

12-BIT DATA BUS

/'>
GND

I
MODE

ICL7109
Bl-B8

ANALOG
IN

~

I-6

0

'IM6100
CMOS
~P

12

i'r-

8

SENSE 1

STATUS

I

V-

12

i'r-

IM6101
CMOS
PIE

1;----:-

j\.

~'''('' '~I ~

RUN/HOLD
LBEN

(

I
CE/LOAD
B9-B12
POL, OR

q'

/>

",/,>

HBEN

READ 1

I

I

READ 2

I

~

,..
CONTROL BUS

~7

Figure 17: ICL7109-IM6100 Interface Using IM6101 PIE

BOOB, BOBO, BOB5

ICL7109
Bl-B8

B,

1-----'
ANALOG
IN
CE/LOAD~-----'

\
·MEMRo,IOR
10' 808018228 System

GND

+5V

Figure 18: Direct Interface - ICL7109 to 8080i8085 ,

4-39

(-

O~OlL

ICL7109

B9-B12
POL; OR

Bl-B8
ANALOG
IN

MC680X
OR
MCS650X

8

HBEN~------------~

AO-A2
LBEN~------------~

A15-Al0

R/v.;, VMA
ADDRESS
BUS

DATA
BUS

CONTROL
'BUS

Figure '19: Direct iCL7109 - MC680X Bus Interface

separately, the data from every conversion (provided the
data access takes less time thana conversion) will be
sequenced in two bytes into the system.

Handshake Mode
The handshake mode allows ready interface with a wide
variety of external devices. For, instance, external latches
may be clocked by the rising edge of CE/LOAD, and the byte
enables may be used as byte identification flags or as load
enables.

If this output is made to go from low to high, the output
sequence can be obtained on demand, and the interrupt may
be used to reset the MODE bit. Note that the RUN/HOLD
input to the ICL7109 may also be driven by a bit of the 8255 so
that conversions may be obtained on command under
software control. Note that one port of the 8255 is not used,
and can service another peripheral device. The same
arrangement can also be used with the 8155.

Figure 20 shows a handshake interface to Intel microprocessors again using an 8255PPI. The handshake operation with
the 8255 is controlled by inverting its Input Buffer Full (lBF)
flag to drive the SEND input to the ICL7109, and using the
CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port used.
If the 7109 is in handshake mode and the 82551BF flag is low,
the next word will be strobed into the port. The strobe will
cause IBF to go high (SEND goes low), which will keep the
enabled byte outputs active. The PPI will generate an
interrupt which when executed will result in the data being
read. When the byte is read, the IBF will be reset low, which
causes the ICL7109 to sequence into the next byte. This
figure shows the MODE input to the ICL7109 connected to a
control line on the PPI. If this output is left high, or'tied high

Figure 21 shows a similar arrangement with the MC6800 or
MCS650X microprocessors, except that both MODE and
RUN/HOLD are tied high to save port outputs.

I I

if"

CONTROL BUS

I I
RD
B9-B12

ICL7;0~L, OR

9

Bl-B8

6

07-00

tJ

,r.I

cs

PA,-PAo

I'

8

CE/LOAD

. STBA

III I

AO-Al

.\

1-------'

IN

WR

I I

DATA BUS

PC4

8008,8080,
8085, 8048 ETC

8255
(MODE 1)

SEND~PC5
RUN/HOLD

'

PCs

MODE 1-------,----1 PC,

PC3 I----------IINTR

Figure 20: Handshake Interface - ICL7109 to MCSc48, -80, 85

4-40

~

-

-

-

-

-

-

~

~

(L-______________________________________
ADDRESS.BUS
-________________________

~

The handshake mode is particularly convenient for directly
interfacing to industry standard UARTs (such as the Intersil
IM6402/6403 or Western Digital TR1602) 'providing a
minimum component count means of serially transmitting
converted data. A typical UART connection is shown on
page 3. In this Circuit, any word received by the UART causes

1

O~OIb

ICL7109
+5V-.__-----,

CRA 1--100-011

MC6B20

ICL7109

ANALOG
IN

CE/LOAD

t----~

SEND

MC6BOO
OR
MCS650X

CA1
CA2

ADDRESS
BUS

DATA
BUS

CONTROL
BUS

Figure 21: Handshake Interface'· ICL7109 to MC6800; MCS650X

the UART DR (Data Ready) output to go high. This drives the
MODE input tO,the ICL7109 high, triggering the ICL7109 into
handshake mode. The high order byte is output to the UART
first, and when the UART has transferred the data to the
Transmitter Register, TBRE (SEND) goes high and the
second byte is output. When TBRE (SEND) goes high again,
LBEN will go high, driving the UART ORR (Data Ready Reset)
which will signal the end of the transfer of data from the
ICL7109 to the UART.

is used to select which converter will handshake with the
UART. With no external components, this scheme will allow
up to eight ICL71 09s to interface with one UART. Using a few
more components to decode the received word will allow up
to 256 converters to be accessed on one serial line.
The applications of the ICL7109 are not limited to those
shown here. The purpose of these examples is to provide a'
starting point for users to develop useful systems, and to
st)ow some of the variety 'of interfaces and uses of the
ICL7109. Many of the ideas suggested here may be used in
combination; in particular the uses of the STATUS,
RUN/HOLD, and MODE signals may be mixed.

Figure 22 shows an extension of the one converter· one
UART scheme of the Typical Connection to several
ICL7109s with one UART. In this circuit, the word received
by the UART (available at the RBR outputs when DR is high)

a

SERIAL OUTPUT
IM6403 CMOS UART

T.....
TBRL

ORR

W
?

""

11 11
8-BIT DATA BUS

I

I

MODE

e

SERIAL INPUT
TBR1-TBRB

RBR1-RBRB

TBRE

I

CE/ SEND
LOAD
B9-B12
POL, OR

. :ICL7109
B1-B8

/"'>-

~

1
MODE

r-6

CE/
LOAD

0

1

1

SEND

B9-B12
POL,OR

-

MODE

6

8

B

B1-B8

8

IN

I

I

+5V

1

(

1

CE/ SEND
LOAD
B9-B12 r-6
POL, OR
ICL7109

ICL7109

ANALOG
IN

-RUN/HOLD
- ,LBEN
-HBEN

/">

/~

8

B1-B8

0
8

IN

HBEN

-RUN/HOLD - + 5 V

--

LBEN

HBEN

I

I

I

RUN/HOLD

-LBEN

+5V

I

Figure 22: Multiplexing Converters with Mode Input

APPLICATION NOTES
A016 "Selecting AID Converters," by David Fullagar
A017 "The Integrating AID Converters," by Lee Evans
A018 "Do's and Don'ts of Applying AID ,Converters," by
Peter Bradshaw and Skip Osgood '
4-41

\

A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw
A032 "Understanding the Auto-Zero and Common Mode
Performance of the ICL7106 Family," by Peter
Bradshaw
R005 "Interfacing Data Converters & Microprocessors," by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

II

ICL7116, 7117
3% Digit Single Chip
A/D Converter with Display Hold

FEATURES

seven segment decoders, display drivers, reference, and a
clock. The 7116 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7117 will
directly drive an instrument-size light emitting diode (LED)
display.
The 7116 and 7117 have almost all of the features of the 7106
and 7107 with the addition of a HOLD Reading input. With
this input, it is possible to make measurement and then
retain the value on the display indefinitely. To make room for
this feature the reference inpwt has been referenced to
Common rather than being fully differential. These circuits
retain the accuracy, versatility, and true economy of the 7106
and 7107. High accuracy like auto-zero to less than 10J.,v,
zero drift of less than 1I1V;o C, input bias current of 10pA
maximum, and roll over error of less than one count. The
versatility of true differential input is of particular advantage
when measuring load cells, ~train gauges and other bridgetype transducers. And finally the true economy of single
power supply operation (7116), enablil)g a high performance
panel meter to be built with the addition of only seven passive
components and a display.

. • HOLD Reading Input allows indefinite display hold
• Guaranteed zero reading for 0 volts input on all
scales.
• True polarity at zero for precise null detection.
• 1 pA input current typical.
• True differential input
• Direct display drive - no external components
required. - LCD ICL7116
- LED ICL7117
• Low noise - less than 15 fJ.V pk-pk typical.
• On-chip clock and reference.
• Low power dissipation - typically less than 10mW.
• No additional active circuits required.

II

a

GENERAL DESCRIPTION
The Intersil ICL7116 and 7117 are high performance, low
power 3-1/2 digit AID converters. All the necessary active
devices are contained on a single CMOS I.C., including

TYPICAL CONNECTION DIAGRAMS
IN

IN

+ -

+ Rl
24Kn

ICL7116 with Liquid Crystal Display

Rs
1M!!

c,

ICL7117 with LED Display

ORDERING INFORMATION
en

Part
7116
7116
7116
7117
7117
7117

Temp. Range
,O'C to +70'C
O'C to +70'C
O'C to + 70'C
O'C to + 70'C
O'C to +70'C
O'C to +70'C

Package
40·Pin Ceramic DIP
40-Pin Plastic DIP
40 Pin CERDIP
40-Pin Ceramic DIP
. 40-Pin Plastic DIP
40-Pin CERDIP

Order Number
ICL7116CDL
ICL7116CPL
ICL7116CJL
ICL7117CDL
ICL7117CPL
ICL7117CJL

!::
~
-

_

~

t.

HLDR
01
C1

1

B1
A1
F1
G1

.,

I

OSC2

TEST

REF HI
V'
C'REF
C-REF

02

COMMON

B2

IN LO
A/Z
BUFF
INT
V·
G2 (TENS)

C2

~~

E2
_ ( 03
~
83

~
F3
E3
(1000) AB4
POL
(MINUS)

4-42

aSCl

asc 3

INHI

~~)g

.

G3 ~
BP/GNO
(7116)/(7117)

ICL7116/ICL7117
ABSOLUTE MAXIMUM RATINGS
ICL7116

ICL7117

Supply Voltage v+ ................................. +6V
Supply Voltage (v+ to V-) ........................... 15V
V- ................................... -9V
Analog Input Voltage (either input) (Note 1) ...... V+toVAnalog Input Voltage (either input) (Note 1) ...... V+toVReference Input Voltage (either input) .............. V+ to VReference Input Voltage (either input) ............ V+ to VClock Input .................................. Test to V+
Clock Input .................................. Gnd to V+
Power Dissipation (Note 2)
Power DisSipation (Note 2)
Ceramic Package ............................ 1000 mW
Ceramic Package .......•................. 1000mW
Plastic Package ........................... 800mW
Plastic Package .............................. 800 mW
Operating Temperature .................... 0° C to + 70°. C
Operating Temperature .................... 0° C to +70° C
Storage Temperature .................. -65° C to +160° C
Storage Temperature .................. -65° C to +160° C
Lead Temperature (Soldering, 60sec) .; ............ 300° C
Lead Temperature (Soldering, 60sec) .............. 300° C
Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±1OOI'A.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

ELECTRICAL CHARACTERISTICS (Note 3)
CHARACTERISTICS
Zero Input Reading

"

,

CONDITIONS
VIN =O.OV
Full Scale = 200.0mV

Ratiometric Reading

VIN =VREF
VREF= 100mV

Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)
Linearity (Max. deviation from
best straight line fit)
Common Mode Rejection Ratio
(Note 4)

- VIN = + VIN

=200.0mV

Full Scale = 200mV
or Full Scale = 2.000V

MIN

TYP

MAX

UNITS

-000.0

±OOO.O

999

999/1000

+000.0
1000

Digital Reading
Digital Reading

-1

±.2

+1

Counts

-1

±.2

+1

Counts

VCM= ±1V, VIN=OV,
Full Scale = 200.0mV
VIN =OV
Full Scale = 200.0mV

50

J.NIV

15

J.N

VIN=OV
VIN=O
00..---_ TO DIGITAL SECTION

I
I

'31
INHI~~~~~----r---~~~------~'
INT

6.2V

'32

COMMON~~----~----~--+-------~

INPUT

I

LOW

I

IN LOI(&='30'---4l9-------<'-----------__---t-------------------'
l ________________________
iNT
L
_

v-

~-------------------- -------- -- - - - - - - - -

Figure 3: Analog Section of 711617117

1. Auto-zero phase

and IN LO for a fixed time. This differential voltage can be
within a wide common mode range; within one volt of
either supply. If, on the other hand, the input signal has no
return with respect to the converter power supply, IN LO
can b,e tied to analog COMMON to establish the correct
common-mode voltage. At the end of this phase, the
polarity of the integrated signal is determined.

During auto-zero three, things happen. First, input high
and low are disconnected from the pins and internally_
shorted to analog COMMON. Second, the reference
capacitor is charged to the reference voltage. Third, a
feedback loop is closed around the system to charge the
auto-zero capacitor CAl to compensate for offset
voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop,
the 'A-Z accuracy 'is limited only by the noise of the
system. In any. case, the offset referred to tlie input is less
, than 10!'V.

3. De~integrate phase
The final phase is de-integrate, o'r reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures
that the capacitor will be connected with the correct·
polarity to cause the integrator output toreturn·to zero.
The time required for the output to return to zero is
proportional to the input signal. Specifically the digital
reading displayed is 1000 (~:~f I.

2. Signal Integrate phase

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low' are connected to the external pins. The converter
then integrates the differential voltage between IN HI

4-44

ICL7116/ICL7117
Differential Input
The input can accept differential voltages anywhere within
the common mode range of the input amplifier; or
specifically from 0.5 volts below the positive supply to 1.0
volt above the negative supply. In this range the system has a
CMRR of 86 dB typical. However, since the integrator also
swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worse case condition would be a large positive commonmode voltage with a near full-scale negative dif.ferential input
voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full scale swing with little loss of accuracy.
The integrator output can swing within 0.3 volts of either
supply without loss of linearity. See A032 for a discussion of
the ef.fects of stray capacitance.

Reference
The reference input must be generated as a positive voltage
with respect to COMMON. Note that current flowing in the
COMMON pins' internal resistance causes a slight shift in
the ef.fective reference voltage, disturbing ratiometric
readings at low reference inputs. If possible, do not let this
current vary.
. Analog COMMON
This· pin is included primarily to· set the common modb
voltage for battery operation (7116) or for any system where
the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately 2.8 volts more negative than the positive sup·ply. This
is selected to give a minimum end-of-life.battery voltage of
about 6V. However, the analog COMMOI'II has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the zener to regulate (> 7V),
the COMMON voltage will have a low voltage coefficient
1.001%1%1, low output impedance ("'1501, and a temperature
coefficient typically less than 80ppm/o C.

set at a fixed known voltage (power supply common for Instance). lri this application, analog COMMON should be tied
to the same point, thus removing the common·mode voltage
from the converter.
.
v+
v+

6.SkU

7116/7117
leL 8069
1.2V REFERENCE

7116/7117

COMMON

v(al

(bl

Figure 4: Using an External Reference

Within the IC, ~nalog COMMON is tied to an N channel FET
that can sink 30mA or more of current to hold the voltage 2.8
volts below the positive supply (when load is trying to pull
the common line positive), However, there is only·10p.A of
source current, so COMMON may easily be tied to a more
negative voltage thus over-riding the .internal reference.

a

TEST

II
~

The TEST pin serves two functions. On the 7116 it is coupled
to the internally generated digital supply through a 500n
resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal pOints
or any other presentation the user may want to i ncl ude on the
LCD display. Figures 5 and 6 show such an application. No
more than a 1 mA load should be applied.
v+

7116

The ·Iimitations of the on-chip reference should also be
recognized, however. With the 7117, the internal heating
which results from the LED drivers can cause some
degradation. in performance. Due to their higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature
Coefficient (TCI, internal chip dissipation, and package
thermal resistance can increase noise near full scale from 25
. p. V to 80 p. Vpk-pk. Also the linearity in going from a high
dissipation count such as 1000 (20 segments on) to a low
. dissipation count such as 1111 (8 segments on) can suffer by
a count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because .overload is a low dissipation mode, with the
three least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All
these problems are of course eliminated if an external
reference is used.

TOLCO
DECIMAL POINT

BP 21
TEST '"3'='7""L-I-_-_...J_--<>

~~c";~LANE

Figure 5: Simple Inverter for Fixec;t Decimal Point
v+

v+

BP'I----~:~D+1
D+I

I.

7116

I

DECIMAL [

POINT

SELECT

I

I

D-+-,
I

TOlCD
DECIMAL

POINTS

:D+
,

....-T""-..1

v+ =

I

I

CD4030

DP ON,
L__
GROUND = DP OFF.

I

---'
\GND

Figure 6: Exclusive 'OR' Gate for Decimal Point Drive

The 7116, with its negligible dissipation, suf.fers from none of
these problems. In either case, an external refe·rence can
easily be added, as shown in Fig. 4.

The second function is a "lamp test". When TEST is pulled to
high (to V+ I all segments will be turned on and> the display
should read - 1888. [Caution: on the 7116, in the lamp test
mode. the segments have a constant doc voltage (no squarewave) and will burn the LCD display If left in this mode for
several minutes.]

Analog COMMON is also the voltage that input low returns
to during auto;zero and de-integrate. If IN LO is different
from analog COMMON, a common mode voltage exists in
the system and is taken care of by the excellent CMRR of
the converter. However, in some applications IN LO will be
4-45

ICL7116/1CL7117
to 8 mA, typical for instrument size common anode LED
displays. Since .the 1000 output (pin 19) must sink current
from two LED segments, it has twice the drive capability or 16
mA.,
'.
In both devices the polarity indicator is ON for negative
analog inputs: This can be reversed by simply reversing IN
LO and IN HI.

DIGITAL SECTION
Figures 7 and 8 show the digital section for the 7116 and
7117, respectively. In. the 7116, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the
relative large capacitive currents when the back plane (BP)
voltage is switched, The BPfrequency is the clock frequency
.divided by 800. For three readings/second this is a 60 Hz
square wave with a nominal amplitude of 5 volts. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON. In all cases neglible d-c voltage exists across the
segments.

HOLD Reading Input
The HLDR input will prevent the latch from being updated
when this input is at a logic "HI". The chip will continue to
make A/D conversions, however, the results will not be
updated to the internal latches until this input goes low. This
input can be left open or connected to TEST (7116) or
GROUND (7117) to continuous)y update the display. This
input is CMOS compatible, and has a 70k typical resistance
to either TEST (7116) or GROUND (7117>.

Figure 8 is the Digital Section of the 7117. It is identical
except the regulated supply and back plane drive have been
eliminated and the segment drive has been increased from 2

-iii

.
SEGMENT ASSIGNMENT

[,' : ,?

j' '-:

5 :5 -: ::: 9

------------------------------------.~-·+-·--·---+i~+i+t--·+HH-t++---·H+t+t·i----::.~----,
I

I

'1

I

TYPICAL SEGMENT OUTPUT

OSC1

Figu'p 7: Digital Section 7116

4-46

ICL7116/ICL7117

,-,
,'a. ,-,

SEGMENT ASSIGNMENT

'-'.-" "_:J

~:;LI'-'--'';;O
I

:J(J

-

"J.J

.,:,.

-

., J.
d

TYPICAL SEGMENT OUTPUT

--~~------~-'-------------r---+---r--+------------WY+
37 I TEST
500

n

I

211 DIGITAL
L---_+~~+---_+3~!-_-_-_-_-_-_-_-_-_-_-_-_-_~F.l=_=_=_=~=_-_·_-_~_~_-_-_-_~~$GROUND
HlOR

osc 2

eSCl

asc 3

Figure 8: Digital Section 7117

40kHz (2.5 readings/second) will reject both 50 and 60 Hz
(also 400 and 440 Hz>.

System Timing
Figure 9 shows the clocking arrangement used in the 7116
and 7117. Three basic clocking arrangements can be used:

COMPONENT VALUE SELECTION
1. Integrating Resistor

1. An external oscillator connected to pin 40.
2. Pi. crystal between pins 39'and 40.

Both the buffer amplifier and the integrator have a class A
output stage with l,oOILA of quiescent current. They can
supply 20llAof drive current with negligible non-linearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470kn is
near optimum and similarly a 47kn for a 200.0 mV scale.

3. An R-C oscillator using all three pins.
7116/7111

I•

•

i
I
COUNTER I

I

I

TO

I

I

I

I
I
I

I

•
I,

I

L _______ _

~--------

~

II

________ J

2. Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-Up
'will not saturate the integrator swing (approx. 0.3 volt
from either supply>. In the 7116 or the 7117, when the
analog COMMON is used asa reference,a nominal ±2volt
full scale integrator swing isfine. Forthe 7117 with ±S volt
supplies and analog common tied to supply ground, a
±3.S to ±4 volt swing is nominal. For three readings/
second (48kHz clock), nominal values for CINT are 0.22
and O.lOJLF,respectively.Of course, if different osc.illator
frequencies are used, these values should be changed in
inverse proportion to maintain the same outP~t swing.

EXTERNAL
OSCILLATOR

TEST (7116)
or GND (7117)

Figure 9: Clock Circuits I
The oscillator frequency is divided by four before it clocks
'the'decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and auto'zero (1000 to 3000 counts>. For signals less than full scale,
auto-zero gets the unused portion of reference deintegrate.
This makes a complete measure cycle of 4,000 (16,OOOCIock
pulses) independent of input voltage. For three readings/
second, an oscillator frequency of 48kHz would be used.

An additional requirement of the integrating capacitor is
it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for
this application, polypropylene capacitors give
undetectable errors at reasonable cost.

To achieve maximum rejectiol'1 of 60 Hz pickup, the signal
integrate cycle shou'id be a multiple of 60 Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz; 33 % kHz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
66 2/3 kHz, 50kHz, 40kHz, etc. would be suitable. Note that

3. Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200 mVfull scale where noise
4·47

U~UIL

ICL7116/1CL7117
is very important, a 0.471'F capacitor is recommended. On
the 2 volt scale, a 0.0471'F capacitor increases the speed
of recovery from overload and is adequate for noise on
this scale.

. for VIN *0. Temperature and weighing systems with 'a
variable tare are examples. This offset reading can be
conveniently generated by connecting the voltage trans·
ducer between IN HI and COMMON and the variable (or
fixed) offset voltage between COMMON and IN La.

7. 7117 Power Supplies

4. Reference Capacitor

The 7117 is designed to work from ±5 volt supplies.
However, if a negative'supply is not available, it can be
generated from the clock output with, 2 diodes, 2
capacitors, and an inexpensive I.C. Figure 10 shows this
application. See ICL7660 data sheet for an alternative.

A 0.11'F capacitor gives good results in most applications.
If rollover errors occur a larger value, up to 1.01'F may be
required.

5. Oscillator Components
For all ranges of frequency a 100kO resistor is
recommended and the capacitor is selected from the
equation f = ~~. For 48kHz clock (3 readings/second), C
= 100pF.

6. Reference Voltage
The analog input required to generate full·scale output
(2000 counts) is: VIN 2VREF. Thus, for the 200.0 mV and
2.000 volt scale, VREF should equal 100.0 mV and 1.000
volt, respectively. However, in many applications where
the AiD is connected to a transducer, there will exist a
scale factor other than unity between the input voltage
and the digital reading. For instance, in a weighing sys·
tem, the designer might like to have a full scale reading
when the voltage from the transducer is 0.682V. Instead
of dividing the input down to 200.0mV, the designer
should use the input voltage directly and select VREF
o.341V. Suitable values for integrating resistor and
capacitor would be 120kO and 0.22I'F. This makes the
system slightly quieter and also avoids a divider network
on the input. The 7117 with ±5 volts supplies cali accept
input signals up to ±4 volts. Another advantage of this
system occurs when a digital .reading of zero is desired

=

Figure 10: Generating Negative Supply from +5v
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:

=

1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5 volts.

3. An external reference is used.

TYPICAL APPLICATIONS
The 7116 and 7117 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these A/D converters.

7116

......, osc·'

7117

4.

g.
ase3
OSC2

C REF
C REF

Set VREF

Set YREF=100.0mV

'oOPF

TEST

REF HI
v+

/

,A',

pr-

FP··'·F

1K~v-

COMMON

·f.~,i

'5V
22Kll

II

.22/-lF

::::: 9V

~

TO DISPLAY

,

S--

O.47pF

47Kn
.22J-1.F

,

iTO DISPLAY

Go

21

·5V

,,
,

- --------- ---------"

GND

TO BACK PLANE

21

IN

.D1/JF

IN LO
AlZ
BUFF
INT
VG,
C3
A:3

-

-A;':A 47Knj

i

IN HI

IN

O.47 /-lf

G,
C3
A3
G3 ~
BP

1M!!

+

::;:.01pF

v-

=100.0mV

/

TEST

1Mn

IN HI
INLO
AlZ
BUFF
INT

4•

,AA'··KOj

";:"

Figure 12: 7117 using the internal reference. Values shown are for
200.0 mV full scale, 3 readings per second. IN La may be tied to
either COMMON for inputs floating with respectto supplies, or GND
for single ended inputs. (See discussion under Analog Common.!

Figure 11 : 7116 using the internal reference. Values shown are for
200.0 mV.full scale, 3 readings per second, floating supply voltage
(9V battery).
4·48

O~OIL

ICL7116/ICL7117
711617117

'-" OSCl

7117

40

'-"

.AAA100KOj

OSC2

Set VREF = 100.DmV

-v

ose3

100pF

TEST

,A'A

v+ F I C REF

'~s~ri

-A

v+

INT
a'l=
C'F

~: 1=

C REF I=PO.,.
COMMON

+

INHI
IN La

IN

+SV

+

'V

IN

O.47J.1F
,-A

·V.Y

BUFF

INT

v-

1Mn

·::.OlpF

All

"""A470K'1L

".22pF

V-

,AA

,Kn . i'OKIIT'fsKn
...... ,.2V (ICL 8069)

C REF

-

.047pF

/

f-'-

v+

24KO

• .01~F

a~! 1=

ap/aND

,A

'MO

INHI

Set VREF =lOU.amY

100pF

TEST
REF HI

I=PO.,.F
C REF
COMMON
INLO

100Kn

asc 3

/

REF HI

40
OSC1

asc 2

47KIl

.22",F

va'l=

~I=

ITO DISPLAY

ITO DISPLAY

G:~g

El
21

21

'Figure 13: 7116/7117: Recommended component values for 2.000V
full scale.

Figure 14: 7117 operated from single +5V supply. An external
reference must be used in t,his application, since the voltage between
y+ and V- is insufficient for correct operation oi' the internal
reference .

.------9v+
7117

7116
40
'-' OSC1

40

asc 1

100Kn

OSC 2 Lt--".N'..--4
OSC3[}--~~-~
100pF
TEST

REF H I D - - - - - - - h .
V·

100Kfl

OSC2
OSC3

'V:i,V

TEST

100pF

REF HI

0----,----'

bO.,.F[

COMMON
INHI
INLO

.22",F

-------0

.22J.1F

V-

a,
C,
A3
a,
ap

>22 Kn

SIIlconNPN
~:~a~704 or

~'----~

.12OK
l'
'V

"Ill.

\ zero adjust

'V

INT

ITO DISPLAY

'V.V~

470kn

BUFF

v-

0-

1Mn

J.ODKJ!

.01J.iF=
O.047J.iF

All

47Kn

/

100KI!A ,'A

v+
CREF
CREF

Scale .actor adjust

-

":"9V

~

I TO DISPLAY
-

TO aACK PLANE

21

Figure 15: 7117 measuring ratiomlltric values of Quad Load Cell. The
,resistor values within the bridge are determined by the desired
sensitivity.

Figure 16: 7116 used as a digital centigrade thermometer. A silicon
diode-connected transistor has a temperature coefficient of about
-2mV/oC. Calibration is achieved by placing the sensing transistor
in ice water and adjusting the leroing potentiometer for a 000.0
reading. The sensor should then be placed in boiling water and the
scale-factor potentiometer adjusted for 100.0 reading.

For additional information see the following Application Bulletins:
A016
A017
A018
A019
A023
A032
A046

"Selecting AID Converters," by David 'Fullagar
"The Integrating AID Converters," by Lee Evans
"Do's and Don'ts of Applying AID Converters," by Peter Bradshaw and Skip Osgood
"4 V2·Digit Panel Meter Demonstratorllnstrumentation Boards," by Michael Dufort.
"Low Cost Digital Panel Meter Designs," by David Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common Mode Performance of the ICL7106/7/9 Family," by Peter Bradshaw
"Building a Battery-Operated Auto Ranging DVM with the ICL7106," by Larry Goff

4-49

II
~

ICL7126
Single~Chip

3 t /a-Digit
Low.-Power AID Converter

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•

The Intersil ICL7126 is a high performance, very low power
3'12 digit AID converter. All the necessary active devices are
contained on a single CMOS IC, including seven segment'
decoders, display drivers, reference, and clock. The 7126 is
designed to, interface with a liquid crystal display (LCD) and
includes a backplane drive. The supply current is 100!,A,
ideally suited for 9V battery operation.
The 7126 brings together lin unprecedented combination of
high accuracy, versatility, and true economy. High accuracy,
like auto-zero to less than 10!'V, zero drift of less than
1!'V/oC, input bias current of 10pA max., and rollover error
of less than one count. The versatility of true differential
input and reference is useful iri all systems, but gives the
designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of single power supply operation
allows a high performance panel meter to be built with the
addition of only 7 passive components and a display.
The ICL7126 can be used as a plug-in replacement for the
ICL7106 in a wide variety of applications, changing only the
passive components.

•
•
•
•
~

•
•

Guaranteed zero reading for 0 Volts input on all scales
True polarity at zero for precise null detection
1pA typical Input current
True differential input and reference
Direct LCD display drive - no external components
required
Pin compatible with the ICL7106
Low noise .....: less than 15J.!V pop
On-chlp clock and reference
Low power dissipation guaranteed less than 1mW
No additional active circuits required
Evaluation Kit available (ICL7126EV/KIT)
8,000 hours typical 9 Volt battery life

II

PIN CONFIGURATION
v'
IN

+ -

iil

!:

!!i

OSC 1
OSC2
OSC 3
TEST '
REF HI

01
Cl
Bl

1 Al

Fl

-

REFLO

G1

C+REF

ICL7126

El

C-REF

COMMON
IN HI
INLO
AlZ
BUFF'
INT

02
C2
B2
A2
F2
E2

1

_

~
"'

t:.

_{03
.

~

v-

:=!
-

C
~

F3
E3
(1000) AB4

. POL
(MINUS)

.'

1-g

G2 (TENS)

B3

G3 ~

20

1

BP

(Outline dwg DL,JL,PL)

ORDERING INFORMATION

Pari
Temp. Range
7126
O~C to +70'C
7126
O'C to +70'C
7126
O'C,to +70'C
7126 Kit

ICL71l!6wlth Liquid Crystal Display

4·50

Package
40·Pln"Ceramic DIP
40·Pin Plastic DIP
40-Pin CERDIP
Evaluation Kits
See page 8.

Order Number
ICL7126CDL
ICL7126CPL
ICL7126CJL
ICL7126EVIKIT

O~OIL

ICL7126
ABSOLUTE MAXIMUM RATINGS

Power Dissipation (Note 2)
Ceramic Package .............................. 1000mW
Plastic Package .................................. 800mW
Operating Temperature .................... O°C to +70°C,
Storage Temperature ................... -6SoC to +160°C
Lead Temperature (Soldering, 60 sec) .............. 300°C

Supply Voltage (V+ to V-) ........................... 1SV
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) .......... V+ to VClock Input. ...... ~ .......................... TEST to V+

Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100pA.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board ..
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress
rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Note 3)

TYP

MAX

UNITS

-000.0

±OOO.O

+000.0

Digital Reading

999

999/1000

1000

Digital Reading

-VIN = +VIN '" 200.0mV

-1

±.2

+1

Counts

Linearity (Max. deviation from
best straight line fit)

Full scale = 200mV
or full scale = 2.000V

-1

±.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM=±1V, VIN=OV.
Full Scale = 200.0mV

SO

}LV/v

Noise (Pk - Pk value not exceeded
9S%oftime)

VIN=OV
Full Scale = 200.0mV

1S

}LV

CHARACTERISTICS

CONDITIONS

Zero Input Reading

VIN=O.OV
Full Scale = 200.0mV

Ratiometric Reading

VIN =VREF
VREF= 100mV

Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)

MIN

1

10

pA

0.2

1

}LV/oC

1

S

ppm/DC

SO

100

}LA

2.8

3.2

V

Leakage Current @ Input

VIN=OV

Zero Reading Drift

VIN=O
0° .,---_

I

I

TO DIGITAL SECTION

'31

INHI~~~~~----~--~~-r------~
INT

'32

COMMON~~-----+--~~--~--~

INPUT
LOW

I

'30

INLO~~~9-----~~--------------~--~------~----~
~~T_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~

L___

..!:

________________________________ ____ _

Figure 3: Analog Section of 7126

1. Auto-zero phase

within a wide common mode range; within one Volt of
either supply. If, on the other hand, the input signal has
no return with respect to the converter power supply,
IN LO can be tied to analog COMMON to establish the
correct common-mode voltage. At the end of this phase,
the polarity of the integrated signal is determined.

During 'auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference
capacitor is charged to the reference voltage. Third, a
feedback loop is closed around the system to charge the
auto-zero capacitor CAZ to compensate for offset voltages
in the buffer amplifier, integrator, and comparator. Since
the comparator is included in the loop, the A-Z accuracy
is limited only by the noise of the system. In any case, the
offset referred to the input is less then 10,uV.

3. De-integrate phase
The final phase is de-integrate, or reference integrate.
Input low' is internally connected to analog COMMON
and input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures
that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero.
The time required for the output to return to zero is
proportional to the input signal. Specifically the digital
reading displayed is 1000 (~).

2. Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter
then integrates the differential voltage between IN HI and
IN LO for a fixed time. This differential voltage can be

4-52

O~OIl,

ICL7126

y+

Differential Input
,\

.

"

"~

"

The input can accept differential voltages anywhere within
the common mode rante of the input amplifier; or specifically
from 0.5 Volts below the positive supply to 1,0 Volt above the
. negative supply. In this range the system has a CMRR of '
86 db typical. However, since the integrator also swings with,
the cominon mode voltage, care must be exercised to assure
the integrator output does not saturate. A worst case condition woul,d be a large positive common-mode voltage with a
near full-scale negative differential input voltage. The
negative input signal' drives the integrator positive when
most of its swing has been used up by the positive common
mode voltage. For these critical applications the integra'tor
swing can be reduced to less than the recommended 2V full
scale swing with little loss of accuracy. The integrator output
can swing within '0.3 Volts of either supply without loss of
linearity.

~.

.,.

The reference yoltage can, be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor lOSing or gaining charge to stra'y capacity
on its nodes. If there is a large conimon mode voltage, the
reference capacitor can gain charge (increase voltage)
when called up to de~integrate
positive signal but lose
charge (decrease voltage) 'when called up to deintegrate a
negative,input signal. This difference in reference for (+) or
(-) input voltage will give a roll-over error. However, by
selecting the niference capacitor large enough in comparison
to the stray capacitance, this error can be held to less than
0.5 count for the worst case condition. (See Component
Values Sele~tion below.)

This pin, is included primarily to set the common mode'
," voltage for battery operation or for any system where the
", . input signals are floating with respect to the power'Suppiy,
The COMMON pin sets a voltage that is' approximately 2.8
Volts more negative than the' positive supply. This is selected
to give a mininium end-of~life battery )/oltage of about 6V.
'. " However, the anaiog COMMON has some of the attributes of
....
a· referem:;e Voltage. When the total supply voltage is large
enough to'cause the zerier to regulate «7'1/), the COMMON
,.
\. '. voltage wili have a low voltage coefficient (0.001%/%), low

r'.

CO)

Figure 4: Using an External Reference
output impedance ("'150), and a temperature coefficient
typically less than 80ppm/oC.

Withirithe IC, analog COMMON is tied to an N channel FET
that can sink 100llA or more of, current to hold the. voltage
2.8 Volts below the positive supply (when a load is trying to
pull the common line positive). However, there is only 11lA
of source current, so COMMON may easily be tied to a more
negative voltage thus over-riding. the internal reference .. '

Test

.-.~

COMMON

Analog COMMON Is also used as the input low return dur- .
ing auto-zero and de-integrate. If IN LO Is different from
analog COMMON, a common mode voltage exists in the
system and Is taken care of by the exceilent CMRR of the
converter; However;in some applications IN, LO will be set
ilt a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same pOint, thus removing the common mode voltage
from the converter. The same holds true for the reference
";oltage. If reference can be conveniently referenced to
analog COMMON, it should be since this removes the common mode voltage from the refer~nce sy.stem.

.'

~

REF LO

II

. Analog COMMON

'.

leL'aH9
1.2 n'EFERENCE

The limitations of the on"chip reference should also be
recognized, however. The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2 to 8° C,' typical for· instruments, can
give a scale factor error of a count or more. Also the common
1I0itage will have a poor voltage coefficient when the total'
supply voltage is less than that which will cause the zener
to'regulate (lXlry..-oh--o·5Y
C REF
B.SkO

0--------,

y+

REF LO

240Kfl

250KO

1= =:5=0.1,F

COMMON

1Mn

IN HI
IN LO

0.022 F

AlZ

1.8M

B~=~ 1=

CO;:~:~::::::::::::--~--------~;IC~-;

+

I~ ~~ D---.,..;..----,~o".1"'"F"""N\r-~-.",N

IN

:;:.01~F

-

Ol

O.33~F

'V
75011 -til047,F
yG,
Co
}TD DISPLAY
Ao
Go
BP ~TO BAC' PLANE
21

D---------~----

POLARITY

-

6.B VOLT
ZENER

7135

v+

--6--11
23

v+

'-" ICL8069
1.2V
REFERENCE

liZ
COMMON~-~--.

J,
DIGITAL
GND

(a)

CLOCK
IN

RUN/, OVER
HOLD
RANGE

UNDER
RANGE

(b)

Figure 5: Digital Section 7135

_ Figure 4: Using an External Reference

4-61

BUSY

II
~

O~OIL

ICL7135

Integrating CapaCitor
The product of integrating resistor and capacitor should be
selected to give the maximum voltage swing which ensures
that the tolerance build-up will not saturate the integrator
swing (approx. 0.3 volt from either supply). For ±5 vO,lt
supplies and analog COMMON tied to supply ground, a±3.5
to ±4 volt full scale integrator swing is fine, and 0.10jlF is
nominal. In general, the value of CINT is given by

3. BUSY (Pin 21). BUSY goes high at the beginning 01 signal
integrate and stays high until the first clock pulse after zerocrossing (or after end of measurement in the case of an overrange). The internal latches are enabled (i.e., loaded)
during the first clock pulse after busy and are latched at the
end of this clock pulse. The circuit automatically reverts to
auto-zero when not BUSY, so it may also be considered a
(ZI + AZ) Signal. A very simple means for transmitting the
data down a Single wire pair from a remote location would
be to AN D BUSY with Clock and subtract 10,001 counts from
the number of pulses received - as mentioned previously
there is one "NO-count" pulse in each reference integrate
cycle.
4. OVER-RANGE (Pin 27). This pin goes· positive when the
input signal exceeds the range (20,000) of the converter. The
output F-F is set at the end of BUSY and is reset to zero at the
beginning of Reference integrate in the next measurement
cycle.
.

CINT=

(10,000) (clock period) (20/lA)
integrator output voltage swing
A very important characteristic df the integrating capacitor is
that it has low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
l)se the capaCitor with the input tied to the reference.

5. UNDER-RANGE (Pin 28). This pin goes positive when the

II
~

[10,000 x clock period) x liNT
integrator output voltage swing

This ratiometric condition should read half scale 0.9999, and
any deviation is probably due to dielectric absorption. Poly·
propylene capacitors give undetectable errors at reasonable
cost. Polystyrene and polycarbonate capaCitors may also
be used in less critical applications.
.

reading is 9% of range or less.The output F-F is set at the end
of BUSY ·(if the new reading is 1800 or less) and is reset at the
beginning of signal integrate of the next reading.
6. POLARITY (Pin 23). This piri is positive for a positive input
signal. It is valid even for a zero reading. In other words,
+0000 means the signal is positive but less than the least
significant bit. The converter can be used as a null detector
by forcing equal frequency of (+) and H readings. The null at
this point should be less than 0.1 LSB. This output becomes
valid· at the beginning' of reference integrate and remains
correct until it is re-validated for the next measurement.

INTEGRATOR
OUTPUT
uTo-1 SIGNAL

~1~'1~~1

7: Digit Drive~ (Pins 12, 17, 18, 19 and 20). Each digit drive is
a positive going signal that lasts for 200 clock pulses.
The scan sequenee is 05 (MSO), 04, 03, 02 and 01 (LSD). All
five digits are scanned and this scan is continuous unless an
over-range occurs. Then all digit drives are blanked from the
. end Of the strobe sequence until the beginning of Reference
Integrate when 05 will start the scan again, This can give a
blinking display as a visual indication of over-range.

1b~1iJl

I INT2EoGo~~TE

REFERENCE~

COUNTS COUNTS cOUNTS MAX.
FULL MEASUREMENT CYCLE
40,002 COUNTS

BUSY

"

8. BCD (Pins 13, 14, 15 and 16). The Binary coded Decimal
bits B8, B4, B2 and B1 are positive logic signals th'at go on ,
simultaneously with the digit driver Signal.
.

----.J

'-----.. . . 1.

UNDER·RANGE ~
WHEN APPLICABLE "'~'""'"~~:-::-".,.,.~

,

I EXPA~~CgJCALE

FOR O~~~I_~!~~~~ 05
~D4
~D3

~D2

COMPONENT VALUE SELECTION

~Dl

For optimum performance of the analog section, care must
be taken.!n the selection of values forthe integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion. rate. These values must be chosen to suit the
particular application.

Ich08~~~

r- AUTO ZERO

I.
FOR o~~~I_~!~~~nD5

Integrating Resistor
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. Both the buffer ampliJier and the
integrator have a class A output stage with 100jlA of
quiescent current. They can supply 20jlA of drive Gurrent
with negligible non-linearity. Values of 5 to 40jlA give good
.results, with a nominal of 20jlA, and the exact value of
integrilting resistor may be chosen by
RINT =

'FIRST 05 OF AZ II.ND
REF INT ONE COUNT LONGER

STROBE I I I I I

.

SIGNAL INTEGRATE
,

J1~D~4________~~~____~~

full scale voltage
, 20/lA

Figure 6: Timing Diagram for Outputs
4-62

O~OIL

ICL7135

To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
'40kHz, 33V.kHz, etc. should be selected. For 50Hz rejection,
oscillator frequencies of 250kHz, 166 213kHz, 125kHz,'
100kHz, etc.' would be suitable. Note that 100kHz (2.5
,readings/second) will reject both 50 and 60Hz.
The clock used shou,ld be free from significant phase or frequency jitter. Several suitable low-cost oscillators are
shown in the Applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.

Auto-Zero and Reference Capacitor
The size of thE1 auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less' noise_
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference cap and auto-zero
cap are only Important at power-on or when the circuit Is
recovering from an overload. Thus, smaller or cheaper caps
can be used here if accurate readings are not required for
the first few seconds of recovery.
Reference Voltage
The analog Input required to generate a full-scale output is
VIN=2 VREF.
'
'
,

Zero-Crossing Flip-Flop
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by up to one count In every instance, and
if a correction were not made, the display would always be
one count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one-count delay
compensates for the delay of the zero-crossing flip-flop, and
allows the correct number to be latched into the display.
Similarly, a one-count delay at the beginning of phase 1 gives
an overload display of 0000 instead of 0001. No delay occurs
during phase 2, so that true ratiometric readings result.

The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommehded that a high quality reference be used where
high-accuracy absolute measurements are being made.
'

Rollover Resistor and Diode
A small rollover error occurs in the 7135, but this can be
easily corrected by adding a diode and resistor in series between the INTegrator OUTput and analog COMMON or
ground. The value 'shown in the schematics is optimum for
the recommended conditions, but if integrator swing or
clock frequency is modified adjustment may be needed. The
diode can be any silicon diode, such as a 1N914. These components can be eliminated if rollover error is not important,
and may be altered in value to correct other (small) sources
of rollover as needed.

EVALUATING THE ERROR SOURCES
Errors from the "ideal" cycle are caused by:
1. Capacitor droop due to leakage.
2. Capacitor voltage change due to charge "suck-out" (the
reverse of charge injection) when the switches turn off.
3. Non-jinearity of buffer and integrator.
4. High-frequency limitations of butfer, integrator and
comparator.
5. Integrating capacitor non-linearity (dielectric absorption.)
6. Charge lost by CREF in charging Cstray.
7. Charge lost by CAZ and CINT to charge Cstray.
Each of these errors is analyzed for .Its error contribution to
the converter in application notes listed on the back page,
specifically A017 and A032.

Max Clock Frequency
The maximum conversion rate of most dual-slope AID converters is limited by the frequency response of the comparator. The compilratorin this circuit follows the integrator
ramp with a 31's <;Ielay, and at a clock frequency'of 160kHz
(61's period) half of the first reference integrate clock period
is lost in delay. This means. that the meter reading will
change from 0 to 1 witli a 50l'V input, 1 to 2 with 150I'V, 2 to 3
at 250I'V, etc. This transition at mid-point is considered
desirable by most users; however, if the clock frequency is
increased appreciably above 160kHz, the instrument will
flash "1" on noise peaks even when the ,input is shorted.
'For many-dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non-linearity and noise do not Increase substantially with frequency, clock rates of 4P to
-1 MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will ~e a constant and ,can be subtracted out digitally_
The clock frequency may be extended above 160kHz without
this error, however, by using a low value resistor in series
with the Integrating capacitor. The effect of the resistor is to
,introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By
careful selection of the ratio between this resistor and the
integrating resistor (a few tens of ohms in the recommended
circuit), the comparator delay can be compensated and the
maximum clock frequency extended by approximately a factor of 3, At higher frequencies, ringing and second order
breaks will cause significant nonlinearities in the first few
counts of the instrl,lment - see Application Note A017.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices, measurement cycles as long as 10 seconds give no measurable
leakage error.

NOISE
The peak-to-peak noise ,around zero is approximatelY,151'V
(pk-to-pk value not exceeded 95% of the time). Near full
scal'e, this value increases to ap'proximately 30I'V, Much of
the noise originates in the auto-zero loop, and is proportional
to the ratio of the input signal to the reference.
ANALOG, AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of ICL7135 circuits, especially in high-sensitivity circuits. It is most important that return ,currents from digital
loads are not fed into the' analog ground line.
POWER SUPPLIES
The 7135 is designed to work from :t;.5V supplies. However,
in selected applications no negative supply is required. The
c,onditions to use a single + 5V supply are:
1. The input signal can be referenced to the center of the
'
common mode range of the converter.
2. The Signal, is less than ± 1.5 volts.
See "differential input" for a discussion of the effects this
will have on the integrator swing without loss of linearity.
4-63

O~OIb

ICL7135
TYPICAL APPLICATIONS

LED is driven from the 7 segment decoder, with a zero
reading blanked by connecting a D5 signarto RBI input of
the decoder. The 2-gatt;l clock circuit should use CMOS
gates to maintain good power supply rejection.
Figure 8 is similar except the output drives a multiplexed
common cathode LED Display with the 7-Common Emitter
Transistor Array, for the digit driver transistors, making a
lower component count possible. Both versions of the
complete circuit will give a blinking display as a visual
indication of overrange, A clock oscillator circuit using the
ICM7555 C'MOS timer is shown.

The circuits which follow show som'e of the wide variety,of
possibilities, and serve to illustrate the exceptional versatility
of this AID converter.
Figure 7 shows the complete circuitfor a 4-1/2 digit (±2.000V)
full scale) AID with LED readout using the ICL8069 as a 1.2V
temperature compensated voltage reference. It uses the
band-gap principal to achieve excellent stability and low
noise at reverse currents down to 50p.A. The circuit also
shows a typical R-C input filter. Depending on the
application, the time-constant of this filter, can be made
faster, slower, or the filter deleted completely. The 1/2 digit
+5V
6.8kll

b

ANALOG
GND

c

Bl
B2

d

B4

B8

III

SIGNAL
INPUT

lOOk

9

O.1J.1F

47k

ICL7135

C

RC NETWORK

lose
-For'lner resolution on scale factor adjust. use a 10 h.lrn pot ora small pot In series wilha

IIxed resistor.

Figure 7: 4-1/2 Digit A-D Converter with a multiplexed common anode LED display

SET

VREF = 1.07,V -5V

+5V

VREF IN

:SIGNAL
INPUT

O.1~F.r-~~,

+5V

Figure 8: Driving multiplexed common cathode LED displays

4-64

= .45/RC

O~OIl,

ICL7135
A suitable circuit for driving a plasma-type display is shown
in Fig. 9. The high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving 'BI' are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted If not needed. The 2.5k & 3k resis(ors set the
current levels in the display. A similar arrangement can be
used with Nlxie---+5V
u

22-10OpF

27 BO
'35 V-

e-

V+1
+5V

II

o~on.

ICL7135

if a negative supply is not available, it can be generated from
2 capacitors, and an inexpensive I.C. (Figure 13).

TYPICAL APPLICATIONS (Contd.)
A problem sometimes encountered with both LED & plasma'type display driving is that of clock source supply line
variations. Since the supply is shared with the display, any
variation in voltage due to the display reading may cause
clock supply voltage modulation. When in overrange the
display alternates between a blank display and the 0000
overrange indication. This shift occurs during the reference
integrate phase of conversion causing a low display reading \
just after overrange recovery. Both ofthe above circuits have
considerable current flowing in the digital supply from
drivers, etc. A clock source using Intersil's LM311 voltage
comparator in positive feedback mode (Fig~re 12) could
minimize any clock frequency shift problem.
'
The 7135 is designed to work from ±5 volt supplies. However,

.--1-'---..,-----4
16kll

INTERFACING WITH UARTS
AND MICROPROCESSORS
Figure 14 shows a very simple interface between a free'running ICL7135 and a UART. The five STROBE pulses start
the transmission of the five data words. ,The digit :5 word is
OOOOXXXX, digit 4 is 1OOOXXXX, digit 3 is 01 OOXXXX, etc.Also
the polarity is transmitted indirectly by using it to drive the,
Even. Parity Enable Pin (EPE). If EPE of the receiver is held
low, a parity flag at the receiver can be decoded as a positive
signal, no flag as'negative. A complex arrangement is shown
in Figure 15. Here the UART can instruct the AID to begin a
measurement sequence by a word on RRI. The BUSY signal
resets the Data Ready Reset (DRRI. Again STROBE starts the
+5V

+5V
1kll

56kll
ICL7660

1---.,--<> Vour = -sv
30kll'

1

10"F
' - - - _ - -......- - -.. 390pF

Figure 13: Generating Negative Supply from +5V

Figure 12: LM:,l11, Clock Source

J

SERIAL OUTPUT
TO RECEIVING UART

t

DRR

IM6402/3
EPE

TBRL

.

TBR

,

UART
IM640213

.

RRI

DR

-

TRO

r - - EPE

t

TR'O

1

TBRL

2

3

4

-

.

TBR
2

3

4

5

6

7

8

D,

D3

D2

D,

B,

B2

B,

B,

6

7

8

1Y 2Y 3Y

74C157

\

1

\

5

1A 2A 3A
N C - D5

04 03 02 01 81 82 84 8a

,-

D5

ICL7135

RUN/ii15i]) ----<> +5V

~OL

ENABLE

~.

1B 2B 3B

II I

STROBE

ICL7135
'---

....
frl
lJl
....

P 0
0 V
L E
R

U

N
D
E
R'

Au~~~grl5

BUSY

\

Figure 14: ICL7135 to UART Interface

===i.

Figure 15: Complex ICL7135 to.UART Interface

12

12

L--+~+-~-+-~--~---~READ1

B, B2 B, B':; ~

iCL7135

L E
R

'1100pf

IM6101
STROBE 1-----1 SENSE 1

• R RUN/HOLDI----'--IWRITE 1

Figure 16: IM6100 to ICL7135 Interface

4-66

,IM6100

+5V
10K

ICL7135
EN

O~O\l,.

lY

PAO

2>(

PAl

EN

lY

PAl
MC680X
OR
MCS6S0X

PA2
PA3

PA2
PA3

8255
(MODE 1)

Mc6820

03

D.

PA4
PAS
PA6
PAT

CAl

PAO

03

D.

CA2

INTERSIi.
IM80C48,
INTEL
8080
8085,
ETC.

PA4
PAS
PA6
PAT

STROBE PA6

Figure 17: ICL713? to MC6800, MCS650X Interface

Figure 183 ICL7135,to MCS-48, -80, 85 Interface

transmit sequence. A quad 2 input multiplexer is used to
superimpose polarity, over-range, and under-range onto the
Os word since in this instance it is known that B2 = B4'= B8 =

O.
For correct operation it is important that the UART clock be
fast enough that each, word is transmitted before the next
STROBE pulse arrives. ,Parity is locked into the UARTat load
time but does not change in this connection during an output
stream.

APPLICATION NOTES
A016 "Sel.ecting A/D Converters," by David Fullagar
A017 "The Integrating A/D Converters," by Lee Evans
A018 "Do's and Don'ts of Applying A/D Converters," by
Peter Bradshaw and Skip Osgood
A019 "4-1/2 Digit Panel Meter Demonstrator/Instrumentation Boards," by Michael Dufo'rt
A023 "Low Cost Digital Panel Meter. Designs,''' by David
Fullagar and Michael Dufort

4·67

Circuits to interface the ICL7135 directly with three popular
microprocessors are shown in Figures 16, 17 and 18. The
main differences in the circuits are thatthe IM6100 with its 12
bit word capability can accept polarity, over-range, under-II
range, 4 bits of BCD and 5 digits simultaneously wher(! the ~
8080/8048 and the MC6800 groups with 8 bit words need to
'
have polarity, over-range and under-range multiplexed onto
the Digit 5 word - as in the UART circuit. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.

A028 "BLiilding an Auto-Ranging DMM Usil')g the
8052A17103A AID Converter Pair," by Larry Goff
A030 "The ICL7104 - A Binary Output A/D Converter for
Microprocessors", by Peter Bradshaw
A032 "Understanding the Auto-Zero and Common Mode
Performance. of the ICL7106 Family", by Peter
Bradshaw
ROOS "Interfacing Data Converters & Microprocessors," by
Peter Bradshaw et ai, ElectroniCS, Dec. 9, 1976

AD7520/7530
AD7521/7531

D~D[b,

10 & 12 Bit Monolithic
Multiplying D/ A Converters ,
FEATURES

GENERAL DESCRIPTION

• AD7520/ AD7530: 10 Bit Resolution; 8; 9 and 10 Bit'
Linearity
,
• ~D7521/AD7531: 12 Bit Resolution; 8, 9 and 10 Bit
Linearity,
• Low Power Dissipation: 20 mW (Max)
• Low Nonlinearity Tempco: 2 PPM of FSR/o C (Max)
• Current Settling Time: 500 its to 0.05% of FSR
• Suppiy Voltage .Range: +5V to +15V
• DTL/TTLICMOS Compatible'
.. Full Input Static Protection
• 883B Processed Versions Available

The AD75201AD7530 and AD75211AD753f are monolithic,
high accuracy, low cost 10-bit ,and 12-bit resolution,
multiplying digital-to-analog converters mAC),
INTERSIL thin-film on CMOS processing gives up to 10bit accuracy with DTLlTTLlCMOS compatible operation.
Digital inputs are fully protected against static discharge
'
by diodes to ground and positive supply.
Typical applications include digital/l\nalog interfacing,
multiplication and division, programmable power
supplies, CRT character generation, digitally controlled
gain circuits, integrators and attenuators, etc.
The AD75;30 and AD7531 are identical to the AD7520 and
AD7521, respectively, with' the exception of. outpu't
leakage current ·and feedthrough specifications.

FUNCTIONAL DIAGRAM
10Kn

VAEF

SPDT
NMOS
SWITCHES

1DKU

CHIP TOPOGRAPHY
10KIl

10KO

---+.....-+-.....- - o

'---+,l.+-;--f-I.....

4-.,-.....+---+i-----+--......

IOUT2

RFEED8ACK

81T11

BIT10

(Switches'shown fqr Digital Inputs "High")
(Resistor valljes are nominal)

BITO

BIT6 BIT7 BITS

I

1------·2~4::8~"m----~,

PACKAGE IDENTIFICATION

,T 1~pac.age'
AD7520

Suffix D: Cerdlp package
Suffix N: Plastic DIP package

PIN CONFIGURATION (Outline dwgs DE, PEl
- TOP VIEW

J N

AD7520 (AD7530)

.
Nonllnearily .
L...,.----'Ganoral Type

ORDERING INFORMATION
Nonlinearity
0,2% IS· Bill

0,1% 19·Bill

0.05% 110·Bill

O'Cto+ 0

Temperature Range I
-25' C to +S5' C -55'Cto +125'C

AD7520JN
AD7530JN
AD7521JN
AD7531JN

AD7520JD •
AD7530JD
AD7521JD
AD7531JD

AD7520SD

AD7520KN
AD7530KN
AD7521KN
AD7531KN

AD7520KD
AD7530KD
AD7521KD
AD7531KD

AD7520TD

AD7520LN,
AD7530LN
,AD7521LN
AD7531LN

AD7520LD
AD7530LD
AD7521LD
AD7531LD

AD7520UD

AD7521

AD7521SD

AD'7521TD

AD7521UD

4·68

~AD7531)

D~DIl.

AD7520/7530/7521 17531

ABSOLUTE MAXIMUM RATINGS (TA = 25~ C unless otherwise noted)
Operating Temperatures
V+ ............................................. +17V
IN,KN,LNVersioris ..................•.. 0° Cto+700 C
VREF ...........••............................ ±25V
JD, KD, LDVersions •.............•..... -25°Ct085°C'
Digital Input Voltage Range .........•.... V+ to GND
SD, TO, UD Versions .: .....••.....,... -55° C to +125° C
Output Voltage Compliance ..•. '. . . . . .. -100mV to V+
Power Dissipation (package)
Storage Temperature .................. -£5° C to +150° C
up to +75°C ..... ,......................... 450 mW
derate above +75°C @ ..............•... 6 mW/oC
CAUTION: 1) The digital control inputs are zener protected; however. permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.

2) Do not apply voltages higher than VOO or less than GND potential on any terminal except VREF and R,b.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional'
operation 01 the device at these or any other conditions above those indicated in the operational sections of the specifications Is not imptled. Exposure to abo
solute maximum rating conditions for extended periods may affect device reliability,

SPECIFICATIONS (V+ = +15V, VREF= +10V, TA=25"C unless otherwise specified)
AD7520 '
(AD7530)

PARAMETER
, DC ACCURACY (Note 1)
Resolution
Nonlinearity

AD7521
(AD7531)

UNITS

12

Bits',

10
J
S
K
T
L
U

LIMIT

0.2 (8-Bitl

% of FSR

Max

0.1 (9-Bit)

% of FSR

Max

O,OS (10-Bit)

% of FSR

Max
Max

, TEST CONDITIONS

'" FIG.

S, T, U: over -5S"C to =12S"C

.

1

"'1~

-10VSVREFS = 10V

Nonlinearity Tempco
Gain Error (Note 2)

2

PPM of FSRI" C

0.3

% of FSR

Typ

Gain Error Tempco (Note 2)

10

PPM of FSR/" C

Max

Output Leakage Current
(either ,outpull

200
(3001

nA

Max

Power Supply Rejection
ACACCURACY
Output Current Settling
Time

±O.OOS

% of FSR/%

Typ

SOO

nS

Typ

To 0.05% of FSR (All digital
inputs low to high and high to
low)

6

10

mV pp

Max

VREF = 20V pp, 100kHz
(50kHz) All digital inputs low

S

5k
10k
20k

n

Min
Typ
Max

pF
pF
pF
pF

Typ
Typ
Typ
Typ

Feedthrough Error
REFERENCE INPUT
Input Resistance (Note 3)
ANALOG OUTPUT
Voltag,e Compliance
(both outputs)
Output Capacitance

Output Noise
(both outputsl
DIGITAL INPUTS
Low State Threshold
High State Threshold
Input Current'
(low to high statel
Input Coding,

-10VSVREFS +10V
Over the specified temperature
range
2

All digital inputs high.
IOUT1 at ground.

See absolute max. ratings
lOUT" 120
IOUT2 37
IOUT1 37
IOUT2 120
Equivalent to 10kn
Johnson noise

All digital'inputs high

4

All digital inputs low

4

Typ

0.8

V

Max

2.4
1

V

Min

/loA

Typ

3

Over the specified temp range

See Tables 1 & 2 on pages 4
arid S

Binary/Offset Binary

,

POWER REQUIREMENTS
Power Supply Voltage Range

1+

,

Totel Power Dissipation
,(Including the ladderl
NOTES:

+S to +lS
5
2
20

V
nA
mA

Typ
Max

mW

Typ

1. Full scale range IFSRI is l0V for unipolar and ±10V for bipolar modes.
2. Using internal feedback resistor, RFEEDBACK.
3. Ladder and feedback resistor Tempco is approximately -150ppm/"C.

4-69

All digital inputs at GND
All digital inputs high or low

AD7520/7530/7521/7531

O~OI6

TEST CIRCUITS
NOTE: The following test circuits apply for the AD7520: Similar circuits can be used for the AD7530, AD7521 and AD7531.
VREF

10 BIT
BINARY
COUNTER

•

,,
,
'BIT 10
(LSB)

loun

UNGROUNDED
SINE WAVE

AD7520

n...n.

VREF-,----..,---i---'I.A..rv---..,---+f

-=-

CLOCK

SOaK

GENERATOR
40Hz 2V pop
+10 V

13

":"

BIT 10
(LSB)

Figure 1. Nonlinearity

Figure 2. Power Supply Rejection

+11V (ADJUST FOR Your "" OV)

+15V
+15V

f

~ 1kHz

BW

QUAN
TeCH

+1.

NC

j

= 1Hz

BIT 1 (Msa)

MODEL

••"

"16

NC

lK

AD7520

1340
WAVE
ANALYZER

100 mVp-p
1MHz

-,

-=-

Figure 3. Noise

VAEF == 20 V pop 130 kHz SINE WAVE

BIT 1 (MSB)

10----1

.
15

-=-

Figure 4. Output Capacitance

+15V

-!-15V

HO V CV.:::
F_ __
RE::.

EXTRAPOLATE

14

BIT 1 (M~B)

~-------,

~~ Jl.fUl..
DIGITAL INPUT

13

":"

Your

r-:!:-",;,,~,,~

15

•

,

51: 1% SETTLING (1 mY)
81: 0.03% SETTLING
t=rise time

AD7520

,!

;';:-;iD(i:s.:~_~...:IIOUT2
~BIT
10
13

81T 10 {LSD

(LS~)

GND

Figure 5. Feedthrough Error

Figure 6. Output Current Settling Time

DEFINITION OF TERMS
GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage val!ue.

NONLINEARITY: Error contribl1ted by deviation of the
DAC transfer function from a best straight line function ..
Normally expressed as a percentage of full scale range.
For a multiplying DAC, this should hold true over the
entire VREF range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREFI. A
bipolar converter of n bits has a resolution of [2-(n-1)]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full.Scale.

FEEDTHROUGH ERROR: Error caused by capacitive
. coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from loun and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears
on loun terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.
4·70

AD7520/7530/7521/7531

D~DI6

GENERAL CIRCUIT INFORMATION
The AD7520 (AD753OJ and AD7521 (AD7531) are
monolithic, multiplying D/Aconverters. Highly stable thin
film R-2R resistor ladder network and NMOS SPOT
switches form the basis of the converter circuit, CMOS
level shifters permit low power DTLITTUCMOS
compatible operation. An external voltage or current
reference and an operational amplifier are all that is
required for most voltage output applications.

Converter errors are further reduced by using separate
metal'interconnections between the major bits and the
outputs. Use of high threshold switches reduces the offset
(leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 8l. This configuration results in DTU
TTL/CMOS compatible operation over the full military
temperature range. With the ladder SPOT switches driven
by the level shifter, each switch is binarily weighted foran
'ON resistance proportional to the respective ladder leg
current. This assures a constant voltage drop across each
switch, creating equipotential terminations for the '2R
ladder resistors and highly accurate leg currents.

A simplified equivalent circuit of the DAC is shown in
Figure 7. The NMOS SPOT switches steer the ladder leg
currents between IOUT1 and IOUT2 busses which must be
held either at ground or virtual ground potential. This
configuration maintains a constant current in each ladder
leg independent of the input code.
10Kfl

VREF

10Kn

10KU

10KH ,

v+-----~-~--~~-~~-

(15117)
20Kn

SPOT
NMOS

SWITCHES

IOUT2 (2)

'-+----++--+i-----+'----+i....----oIOUT1
I
I

b

81T2"
(5)

(1)

I

I

OTL/TTL/CMOS
INPUT

RFEEDBACK

.I

(16118)

Bin
(6)

(Switches shown for Digital Inputs "High")
Figure 7. 7520/7521 Functional Diagram

Figure 8. CMOS Switch

APPLICATIONS

2. Adjust the offset zero adjust trimpot of the output
operational amplifier for OV ±1 mV at VOUT.'
Gain Adjustment

UNIPOLAR BINARY OPERATION
The circuit configuration for operating the AD7520
(AD753OJ and AD7521 (AD7531) in unipolar mode is
shown in Figure 9. With positive and negative VREF values
the circuit is capable of 2-Quadrant multiplication. The
"Digital Input Code/Analog Output Value'" table for
unipolar mode is given in Table 1.

1. Connect all AD7520 (AD7530) or AD7521 (AD7531)
digital inputs to V + .
2. Monitor VOUT for a - VREF (1·2- n)reading. (n =10 for
AD7520 (AD7530) and n =12 for AD7521 (AD7531)).
3. To decrease VOUT, connect a 'series resistor (0 to 500
ohms) between the reference voltage and the VREF ter·
minal.
4. To increase VOUT, connect a series 'resistor (0 to 500)
ohms) in the IOUT1 amplifier feedback loop. '
TABLE 1

.+15V
VREF----,

BIT 1 (MSB)
DIGITAL
INPUT

1S

11~FR,-,=FE::::ED:::::BA=CK,--_ _.,

CODE TABLE -

i
;'

~1otLSai~1:!3
-4-:1
BIT 10 (LSB)
Figure 9.

YOUT

Unipolar Binary Operation
(2-Quadrant tvlultiplication)

ANALOG OUTPUT

1111111111

-VREF (1 -2-n)

1000000001

-VREF (1/2

1000000000

-VREF / 2
-VREF (1/2 -2-n)

0000000001

-VREF (2 -n)

NOTE:

1. Connect all digital inputs to GND.
4·71

+ 2-n)

0111111111
0000000000

Zero Offset Adjustment

UNIPOLAR BINARY OPERATION

DIGITAL INPUT

1.LSB=2-nVREF

0
2. n = 10
n = 1'2

for 7520, 7521
for 7530, 7531

AD7520/7530/7521/7531
(APPLICATIONS, Cont'd.)

Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect al'l digital inputs to "Logic 1".
3. Adjust IOUT2 amplifier offset zero adjust trimpot for OV
±1 mV at IOUT2 amplifier output.
4. Connect MSB (Bit 1) to "Logic 1" and all other bits to
"Logic 0".
5. Adjust IOUll amplifier offset zero adjust trimpot for OV
±1 mV at VOUT;"
'
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-(n-1)) volts reading. (n =
10 for AD7520 and AD7530, and n = 12 for AD7521 and
,
AD7531).
'
;3. 'To increase VOUT, connect a series resistor of up to
500n between VOUT and RIb.
4. To decrease VOUT, connect a series resistor of up to
500n betwee,n the reference voltage and the VREF
terminal. .

BIPOLAR (OFFSET BINARY) OPERATION
The circuit configuration for operating the AD7520
(AD753Q) or AD7521 (AD7531) in the bipolar mode is given
in Figure 10: Using offset binary digital input codes and,
positive and negative reference voltage values 4Quadrant multiplication can be realized. The "bigital
,Input Code/Analog Output Value" table for bipolar mode
is given in Table 2.
+15
VREF

R3

---_1--II------Jl./VIr------,
10 MEGOHM

BIT 1 (MSB)

DIGITAL

I

INPUT

:

15

"

18 RFEEDBACK

1 faun
AD7520

13

BIT 10 (LSB)

Figure 10. Bipolar Operation
•
(4-Quadant Multiplication)

II
~

TABLE 2
CODE TABLE - BIPOLAR (OFFSET BINARY) OPERATION

'A "Logic 1" input at any digital input forces the
corresponding ladder switch to steer the bit current to
IOUll bus. A "Logic 0" input forces the bit current to IOUT2
bus. For any code the'IOUT1 and IOUT2 bus currents are
pomplements of one another: The current amplifier at
IOUT2 changes the polarity of IOUT2 current and the
transconductance amplifier at IOUll output sums the two
currents. This'configuration doubles the output range but
halves the resolution of the DAC. The difference current
resulting at zero offset binary code, (MSB = "Logic 1", All
other'bits = "Logic 0"), is corrected by using an external
resistor .. (10 Megohm), from VREF to IOUT2.

DIGITAL INPUT

ANALOG OUTPUT
-VREF (1 - 2,"(n-1))

,1111111111
1000000001

-VREF (2-(n-1))

1000000000
011111111'1

0
VREF (2-(n-1))

0000000001

VREF 11 - 2-(n-1))

0000000000
NOTE:1. LSB=2-ln - 1j VAEF

POWER DAe DESIGN USING AD7520

VREF
2. n = 10 lor 7520 and 7521
n = 12 lor 7530 and 7531

30Kn
16
15

YREF (±10Y)

t--'------I3

"

+15V

-

12
11
10

1

BIT
SWITCHES'

INTERSIL
4 AD7520 13

LSB)

10KU

:!:IT~HES

YOUT

100pf

1----;

7.SKn

3DpF

-15V

Figure 1,. The Basic Power DAC

A typical po'wer DAC designed for 8 bit accuracy and 10
bit resolution is shown in Figure 1,. An INTERSIL IH8510
power amplifier (1 Amp continuous output at upto ±25 V)
is driven by the AD7520. '
A summing amplifier between the AD7520 imd the IH8510
is used to separate the g~in block containing the AD7520
on-chip resistors from the power amplifier gain stage
whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise the AD7520 can be 'directly
connected to the IH8510, by using a 25 Vreferenceforthe
DAC.
.'

An' important note on the AD7520/101A interface
concerns the connection of pin 1 of the DAC and pin 2 of
the lOlA. Since this point is the summing junction of an
amplifier with an AC gain of 50,000 or better, stray
capacitance should be minimized; otherwise instabilities
and poor noise performance will result. Note that the
output of the lOlA is fed into an inverting amplifier with a
gain of ~3, which can be easily changed to a'non-inverting
configuration. (For more information see; INTERSIL
Application Bulletin A021-Power D/f;.. Converters Using
The IH8510 by Dick WilenkenJ
,
4-72

O~DI6

AD7520/7530/7521/7531
(APPLICATIONS, C,onl'd.)
ANALOG/DIGITAL DIVISION

This is division of an analog variable (VIN) by a digital word.
With all bits off, the amplifier saturates to its bound, since
division by zero isn't defined. With the LSB (Bit-10l ON,
the gain is 1023. With all bits ON, the gain is 1 (±1 LSB):

. With the AD7520 connected in its normal. multiplying
cqnfigurationas shown in figure 15, the transfer function
is'
,
(A1
Vo = -VIN

21

+

A2
22

+ A3
23 + .. ,

An)
2ri

+15V

where the coefficients Ax assume a value of 1 for an ON bit
and 0 for an OFF bit.
By connecting the DAC in the feedback· of an operational
amplifier, as shown in Figure 12,. the transfer function
becomes

Vo

~

(

I'
16

. BIT.l (MSBI ;5

V'N

5
DIGITAL:
INPUT!
BIND (LSBI 13

VOUl

3

A1

21

Figure 12. Analog/Digital Divider

4-73

O~Olb

AD7523
8 Bit Monolithic
Multiplying D/A Converters

FEATURES
• 8,9 and 10 bit linearity
• Low gain and ,linearity Tempcos
• Full temperature range operation
• Full input static protection
.' DTLITTL/CMOS compatible
• +5 to +15 volts supply range
• Fast settling time: 100 nS
• Four quadrant multiplication
• 8838 Processed versions available

GENERAL DESCRIPTION
The Intersil AD7523 is a monolithic, low cost, high
performance, 10 bit accurate, multiplying digital-to-analog ,
converter (DAC), in a 16-pin DIP.
Intersil's thin-film resistors on CMOS cirpuitry provide 8-bit
resolution (8,9 and 1q-bit accuracy), with DTUTTUCMOS
compatible operation.
Intersil AD7523's accurate four quadrant multiplication, full
military temperature range operation, full input protection
from damage due to static discharge by clamps to V+ and
GND and very low power dissipation make it a very versatile
converter.
Low noise audio gain control, motor speed control, digitally
controlled gain and attenuators are a few of the wide number
of applications of the 7523.

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

VAEFIN

,10Kll

(15)

20Kll

10K!!' 10K!!

<»

> 20Kll3

SPDT~! l' ~h
sWIT~~~~1 ,:
l'
,,
,
~

MSB
(4)

.I

BIT2
(5)

20Kll

$

10~J..l

"

">
20K!!

~h
11

,

I'

6

3

'v
20Kll'

1

-= (3)

r"1 r"1
• . ..'

OUTl

20Kll

............ r -

~ RFEEDBACK
'~ VAEFIN
~v+

.-

OUT2 []

,

GND@
IOUT2(2)
IOUT1(l)

~
10Kll RFEEDBACK

BIT3
(6)

IT

BIT 1 (MSB)

G

BIT2

[I

AD7523

~

II
BIT 4 II
BI,T 5

NC

I!!J BIT 8 (LSB)
i!ID BIT 7

BIT 3

(16)

I!ID NC

t!J

[!

BIT 6

TOP VIEW

(Switches shown for Digital Inputs "High")

OUTLINE DRAWINGS

DE,PE

ORDERING INFORMATION

TLT

Temperature Range
Nonlinearity O°Cto+70°C -20'Cto+85'C -55°Cto +125°C
0.2%
(8 Bill
AD7523AD
AD7523SD
AD7523JN
0.1%
AD7523BD
AD7523TD
(9 Bill
AD7523KN
0.05%
(10 Bill
AD7523CD
AD7523LN
" AD7523UD

D

,

D - ll1-Pln Cerami. DIP
N - III-Pin Plaatl. DIP

Nonlinearity and Temperature Range'
J, K, L - Cammerc!.1
O'C 10. +lO'C

A,B,C - Induolrl,,1
-20'C to +85'C
S,l,U - Milito"
-55'C 10 +l25'C
L-_ _ _ _ _ _ _ _ Bo.l. POrl'Numbar

4-74

AD7523
AB~OLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)

Ceramic
up to 75° C ................................... 450mW
derates above 75° C by ....................... 6mW/o C
Operating Temperatures
IN, KN, LN Versions ..................... 0°Cto+70°C.
AD, BD, CD Versions .................. -25° C to +85° C
SO, TO, UD Versions. . . . . . . . . . . . . . .. -55° C to +125° C
Storage Temperature ................ -65°Cto+150°C
Lead Temperature (soldering, 10 seconds) ...... +300° C

v+ ................................................

+17V
V REF ............................................. ±25V
Digital I nput Voltage Range. . . . . . . . . . . . . . . . .. -0.3 to VDD
Output Voltage Compliance ................. -o~3 to VDD
Power Dissipation (package)
Plastic
up to +70° C .................................. 670mW
deratesabove+70°Cby .................... 8.3mW/oC

CAUTION: 1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages higher than VDD and lower than GND to any terminal except VREF + RFB.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those indicated in the operational'sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended'periods may affect device reliability.

SPECIFICATIONS (V +

= + 15V, VREF = + 10V unless otherwise specified)

.

TA
+25°C

TA
MIN-MAX

UNITS

LIMIT

(±1/2 LSB)

8
±0.2

8
±0.2

Bits
% of FSR

(±1/4 LSB)
(±1/8 LSB)

±0.1
±0.05

±0."1
±0.05

% of FSR
0/; of FSR

Min
Max
Max

-10V:5 VREF:5 + 10V

Max

VOUT'

% of FSR

Max

Digital inputs high.

PPM of FSRI' C
PPM of FSR/oC

Max
Max
Max

-10V VREF + 10V

Max
Max
Max

V+
14.0to15.0V
To 0.2% of FSR, RL - lOOn

PARAMETER

TEST CONDITIONS

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

Monotonicity
Gain Error (Note 2)

±1.5

Nonlinearity Tempco (Note 2 and 3)
Gain Error Tempco (Note 2 and 3)

±1.8
2
10

Output Leakage Current (either output)
AC ACCURACY (Note 3)

±50

±200

nA

Power Supply Rejection (Note 2)
Output Current Settling Time

0.02
150
±1/2

0.03
200
±1

% of FSR/%

Feedthrough Error
REFERENCE INPUT
Input Resistance (Pin 15)
Temperature Coefficient (Note 31
ANALOG OUTPUT (Note 31
Voltage Compliance (Note 4)
Output Capacitance

DIGITAL INPUTS
Low State Threshold (VINd
High State Threshold (V INH )
Input Current (per input)
Input Coding
Input Capacitance (Note 31

nS
LSB

5K
20K
-500

II

ppm/oC

Min
Max
Max

NOTES:

1.
2.
3.
4.

VOUT1 - VOUT2 - 0

=

=

20V pp, 200KHz sine wave. All
VREF
digital inputs low.
All digital inputs high. louT1 at ground.
. Both outputs.

-100mV to V+
Ma~

COUT1
COUT2

100
30

pF
pF

Max

COUT1
COUT2

30
100

pF
pF

Max
Max

0.8
2.4

V
V
p.A

Max
Min

4

pF

Max

+5 to +16

V

100

p.A

±1
Binary/Offset Binary

Max

.See maximum ratings.
All digital inputs high (VINHI
All digital inputs low (VINLI

GU9rantees DTL/TTL and CMOS (0.5
max, 14.5 mini levels
VIN - OV or +15V
See Tables 1 & 2
Accuracy is tested and guaranteed at

POWER REQUIREMENTS
Power Supply Voltage Range
1+

=YOUTZ =OV

Guaranteed

Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
Using internal feedback resistor, RFEEDBACK.
Guaranteed by design; not subject to test.
Accuracy not guaranteed unless outputs at ground potential.

4-75

V+
Max

= +15V,only.

All digital inputs low or high.

Specifications subject to
change without notice.

O~OI!.

AD7523
DIG'ITAL INPUT

APPLICATIONS
UNIPOLAR OPERATION
+lSV

±10V
VREF

Rl
2k

MSB
NOTES:
1. Rl AND R2 USED ONLY IF GAIN
ADJUSTMENT IS REQUIRED.
2. 'CRl PROTECTS AD7S23 AGAINST
NEGATIVE TRANSIENTS.
R21k

Your

Figure 1. Unipolar Binary Operation 12-Quadrant Multiplication)

ANALOG OUTPUT

LSB

11111111

-VREF

(255)
256

10000001

-VREF

C29 )

10000000

-VREF

C28)
256

01111111

-VREF

C27)
256

00000001

-VREF

00000000

-VREF

Note: 1 LSB = (2-8 ) (VREF)=

(2~6)

256

= _ VREF
2

(2~6)
C~6)' =0

(VREF)

Table 1. Unipolar Binary Code Table

BIPOLAR OPERATION
VREF

DIGITAL INPUT
MSB
LSB
lS
11~I'-R::..;FB"---_ _ _~R'v2,,,1I\,k~_ _ _ _ _- ,
DATA I MSB AD7523 OUT1
1 t'O"'U'-'T-'-2----;R'""4--;:Scc
INPlJTS I.SB
k -R""'3'"'S;;ck--.---f--t
0 - - 11
2 ......--"-.N\r1~'V\,..,
RS lOOk

!

R71M!!

R610k

CR2

NOTES:
3. RS-R7 USED TO ADJUST Vour = OV AT
1. R3/R4 MATCH 0.1% OR BETTER.
INPUT CODE 10000000.
2. Rl, R2 USED ONLY IF GAIN
4. CRl & CR2 PROTECT AD7S23 AGAINST
NEGATIVE TRANSIENTS.
ADJUSTMENT IS REQUIRED.

ANALOG OUTPUT

1'1111111

-VREF

C27)
128

10000001

-VREF

C~8)

10000000

0

01111111

+VREF

00000001

+VREF

00000000

+VREF

C~L

C27 )
128

C28)
. 128

Note: 1LSB = (2- 7 ) (VREF)'= (1 ~8) (VREF)
Table 2. Bipolar IOffset Binary) Code Table

Figure 2., Bipolar 14-Quadrantl Operation

POWER DAC DESIGN USING AD7523

0.68!!

10K!!

yOUT

-3SV

0.680

7.SKO

-lSV

Figure 3. The Basic Power DAC

A typical power DAC designed for 10 bit accuracy and 8 bit
resolution is shown in' Figure 3. INTERSIL IH8510 power
amplifier (1 Ampcontinuousoutputwith up to +25V) isdriven
by the AD7523.
,
A summing amplifier between the AD7523 and the IH8510 is
used to separate the gain block containing the AD7520 on-

chip resistors from the power amplifier gain stage whose
gain is set only by the external resistors. This approach
minimizes drift since the resistor pairs will track properly.
Otherwise AD7523 can be directly connected to the IH8510,
by using a 25 volts reference for the DAC.

4·76

O~OIl.

AD7523
APPLICATIONS (continued)
DIVIDER .(DIGIT ALLY CONTROLLED GAIN)

MODIFIED SCALE FACTOR AND OFFSET

V,N
+15V

Vour = - VIN/o
WHERE: .
-VREFD

D = BIT1 + BIT2 + ... BITH
2'
22
28

( O---Vour
Vour

=

VREF [(R,":R2) -

(R~:DR2~ WHERE:

D = BI;' 1·+ BI:22 + ••. BI:' 8
( O '':"

.OKn ~ .. .oKn

20Kfl

. loun

·vv

.oK" ;:.

1

IOUT2' '[]

.oKn

~'(3)

. SPc):~!1

r'h
~1 r' .,
SWIT~~~: I : '---lj--l-..,~-+-I-il~-~.-1-1+--T-I-+---o
I

I

I

I :

~
MSB
(4)

'I....Z.

&

BIT2
(5)

BIT3
(6)

• • ••

RFEEDBACK

(18)

AD7541

frs.
BIT "
~

, BIT 2

IT

trn

BIT3

[!

~ BIT 10

BIT 4

IT

10U12 (')

10KH

p:!l RFEEDBACK
~ VREF IN

~V+

GND[1

BIT 1 (MOB) . .

G i : , I O U T t (1)

b

0:. -

~

(LSB)

BJT 11

BIT 9

BITS[!

tTIJSIT8

BIT6 [9

IioJ BIT7

..

(Switches shown for Digital Inputs "High")
(OutUne dwg ON, PN)

ORDERING INFORMATION
T

Temperature Range
Nonllnellrlly O°C to +70°C -20°C to +Ss.°C --55°C to +125°C
0.02%
(11-bitl
AD7541JN
AD7541AD
AD7541SO
0.01%
(12-bit)
AD7541KN
AD7541BD
AD7541TD
0.01%
(12-bit)
AD7541LN
Guaranteed

Monotonic

0

. L

~
--,---

,

·PACKAGE '
D - la-PIN CER!lMIC DIP
N - la-PIN PLASTIC DIP
. NONLINEARITY AND
TEMPERATURE RANGE
J,K,L.- COMMERCIAL O'C TO +70'C
A,B -INDUSTRIAL -2D'CTO +85'C
.S,T - MILITARY -SS'C TO +12S'C

I.

BASIC PART NUMBER

'4-82

D~DIL

AD7·541
ABSOLUTE MAXIMUM RATINGS
(TA = 2S0C unless otherwise noted)
V+ ..•......••..••.......•.••...•••.•••...•..••..• +17V
VREF ........•...•.......••..•...••... ~ . . . • . . . . .• ±2SV,
Digital Input Voltage Range. . . . • . . • . • . . . . . .• . V+ to GND
Output Voltage Compliance •....••..•••.. -100mV to V+·
Power Oissipatio.n (package)
upto+7SoC ............••.•..•••..••....•..•. 4S0mW
deratesabove+7S0Cby •.......••••.....•.... 6mW/oC
CAUTION

Operating Temperatures
IN, KN, LN Versions ..................... 0° C to +70° C
AD, BD Versions ............ .'.. .. .... - 20·C to + 85·C
SO, TO Versions .•..•••..••.. "...... -5So C to +125° C
Storage Temperature ...•....•...•..• -6S0Cto+150·C

1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
.
e.lectrostatic fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages higher than Vee or less than GND potential on any terminal except VREF and RIb.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.
.

SPECIFICATIONS (V+ = +1SV, VREF= +10V, TA=2S·C unless otherwise specified)
PARAMETER
DC, ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

S
T

J
K
L

Gain Error (Note 2)
Output Leakage Current (either output)
AC ACCURACY (Note 3)
Power Supply Rejection (Note 2)
Output Current Settling Time'
Feedthrough Error

±0.02
1
1

LIMIT

Bits
% of FSR
% cif FSR
%of FSR

Min
Max
Max
Max

"'10V ::;; VREF ::;; +10V
VOUT1 = VOUT2 = OV

Milx

.,.10V::;; VREF ::;; +10V

Max

Voun = VOUT2 = 0

% of FSR
nA

I

% of FSR/%
pS
mV pp

Max
Max
Max

!}

Min
Typ
Max.

-100mV to V+
Coun
COUT2

Output NOise (both outputs)
DIGITAL INPUTS
Low State Threshold (VINLl
High State Threshold (VINH)
Input Current
Input Coding
Input Capacitance (Note 3)
POWER REQUIREMENTS
Power Supply Voltage Range
1+
Total Power Dissipation !including the
ladder)

200
60
. 60
200
Equivaleflt to 10K!}
Johnson noise

pF
pF
pF
pF

0.8

V
V
pA

2.4

±1

TEST CONDITIONS

UNITS

-.

5K
10K
20K

Cou'n
COUT2

NOTES:

12
12
±o.020
±o.024
±o.010
±o.012
±0.010
±0.012
Guaranteed Monotonic
±0.3
±o.4
±200
±50
±0.01

REFERENCE INPUT
Input Resistance
ANALOG QUTPUT
Voltage Compliance (Note 4)
Output Capacitance (Note 3)

TA
MIN-MAX

TA
+25°C

..

Max
Max
Max
Max
Typ

Max
Min
Max

Binary/Offset Binary

V+ = 14.5 to 15.5V .
'To 0.01% of FSR
VREF - 20V pp, 10 kHz. All
digital inputs low.

FIG.

1

2
6
5,

All digital inputs high.
loun at ground.
Both outputs.
See maximum ratings.
All dij;lital inputs high (VINH)

4

All digital inputs low (VINL)

4
'3

VIN - 0 orV+
See Tables 1 & 2 on pages 4 and 5.

8

pF

·Max

..

.' +5 to +16

V
mA
mW

2
20

1. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
2. Using internal feedback resistor, RFEEDBACK.
3. Guaranteed by design; not subject to test.
4. Accuracy not guaranteed unless outputs at ground potential.

4-83

Accuracy is not guaranteed
over this range
Max
Typ

All digital inputs high or low

Specifications subject to
change, without notice.

I

AD7541

·D~DIL

TEST CIRCUITS
VAEF

12 BIT
BINARY
COUNTER

UNGROUNDED

,,,
I

SINE WAVE
GENERATOR
4OHz·2V p-p .

BIT 12

+10Y

(LSB)
':'"

CLOCK

-+t

V R E F - . - - - - . - - + - - ' V I o I v - -....
(ADJUST
FOR

1 MEG

.f1.I1

5DOK

.-

VERROA

BIT 1 (MSS)

= DV.DC¢:==;r.
10K.o1%

BIT 12
(LSB)

Figure 1. Nonlinearity

. Figure 2. Power Supply Rejection

+11V (ADJUST FOR YOUT = OV)

+15Y

II

He
F = 1kHz
BW:: 1Hz
BIT 1 (MSS) 4'7

OUAN

+15,

,.
NC

18

TECH

5

MODEL
134D
WAVE
ANALYZER

100 mYp-p
1MHz

3. Noise

Figure

Figure 4. Output Capacitance

+15V

+15V

YAEF :: 20V pop 10kHz SINE WAVE

+10V··-"V:.;:RE:;..F_ _...,
EXTRAPOLATE

,=;.;....:..:=.....
BIT 1 {MSS)

17

BIT 1 (MSB) •

1811-------..,

~~n.n.n

1-:---'-"5

1.

BIT 12 (LSB) 15

::~ :,~!~t~NG

ri:
,7:---t'6:'

1&

AD1541

5

A07S4,

DIGITAL INPUT
3

Figure 5. Feedthrough Error

Figure 6. Output Current Settling Time

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed .as a percentage of full scale range. For a
, multiplyin!! DAC, this should hold true over the entire VREF
range. .
,
RESOLUTION: Value of,the LSB. For example, a unipolar
converter with n bits has a resolution of (2-n) (VREF). A bipolar
converter of n bits has a resolution of [2-(n-1)][VREF].
Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale,

GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.
FEED THROUGH ERROR: Error· caused by capacitive·

coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from IOUT1 and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 . terminal with all digital inputs LOW or on IOUT2
terminal when all .inputs are HIGH.

4-84

"0

AD7541
GENERAL CIRCUIT INFORMATION
The Intersil AD7541 is a 12 bit, monolithic, multiplying D/A
converter. Highly stable thin film R-2R resistor ladder
network and NMOS DPDT switches form the basis of the
converter circuit. CMOS level shifters provide low power
DTLlTTL/CMOS compatible operation. An external voltage
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in Figure
7. The NMOS DPDT switches steer the ladder leg currents
between IOUT1 and IOUT2 busses which must be held at
ground potential. This configuration maintains a constant
current in each ladder leg independent of the input code.
Converter errors are further eliminated by using wider metal
interconnections' between the major bits and the outputs.
Use of high threshold switches reduces the offset (leakage)
errors to a negligible level.

VREF IN

10K!)

10K!!

1DKU

Each circuit is laser-trimmed, at the wafer level, to better than'
12 bits linearity. For the first four bits of the ladder, special
trim-tabbed geometries are used to keep the body of the
resistors, carrying the majority of the output current,
undisturbed. Tl;1e resultant time stability of the . trimmed
circuits is comparable to that of untrimmed units.
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to the first
(Figure 8), This configuration results in DTLlTTLlCMOS
compatible operation over the full military temperature
range. With the ladder DPDT switches driven by the level
shifter, each switch is binarily weighted for an "ON"
resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,'
creating eqiJipotential terminations for the 2R ladder
resistors, resulting in accurate leg currents.
.

10KIl

(17)

SPOT

~oo
SWITCHES

~=~

4---+-t---+-t----+---*"1r---<>IOUT1

(1)

RFEEDBACK

(18)

(Switches shown for Digital Inputs "High")
Figure 7. AD7541 Functional Diagram

Figure 8. CMOS Switch

APPLICATIONS
General Recommendations
Static performance. of the AD7541 depends on IOUTl and
IOUT2 (pin 1 and pin 2) potentials being exactly equal to GND
(pin 3>'

Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.
The V+ (pin 18) power supply should have a low noise level'
and should not have any transients exceeding + 17 volts.'

The output amplifier should be selected to have a low input
bias current (typically less ttian 75nA), and a ·Iow. drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200J.LV).

Unused digital inputs must be connected to GND or Voo for
proper operation.
A high value resistor (:-1 MOl can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.

The .bias current compensation resistor in the amplifier's
non-inverting input qan cause a variable offset. Noninverting input should be connected to GND with a low
resistance wire.

When gain adjustment· is required, low tempco (approxi~
mately 50ppm/o C) resistors or tri m-pots shouldbe selected.
4·85

AD7541

O~OIb

APPLICATIONS, Continued
UNIPOLAR BINARY OPERATION
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 9. With positive and
negative VREF values the circuit is capable of 2-Quadrant
multiplication. The "Digital Input Code/Analog Output
Value" table for unipolar mode is given in Table 1. Schottky
diode (HP 5082-2811 or equivalent) prevents lauT1 from
negative excursions which could damage the device. This
precaution is only necessary with certain high' speed
amplifiers.

Zero Offset Adjustment
1. Connect all digital inputs to GND ..
2. Adjust the offset zero adjust trimpot of the output operational amplifier for OV ±0.5mV(max) at VOUT.
Gain Adjustment
1.. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1- 1/212) reading.
3. To increase VOUT, connect a series resistor, (0 to 500
ohms), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (0 to 500
ohms), between the reference voltage and the VREF
terminal.

+15V

Code Table -

VREF - - - - - ,

BIT 1 (MSB)

17

16

DIGITAL INPUT
111111111111
100000000001
100000000000
011111.111111 .
000000000001
000000000000

RFEE08ACK

18

DIGITAL
INPUT

:
;
Your
81T 12 (lSa) 15

3
GND

II~.

Figure 9. Unipolar Binary Operation (2-Quadrant Multiplication)

TABLE 1
Unipolar Binary Operation

ANALOG OUTPUT
-VREF (1 - 1/212)
-VREF (1/2 + 1/212)
-VREF/2
-VREF (1/2 -·.1/212)
-VREF (1/212)
0

-----,-----'-Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Set R4 to zero.
3. Connect all digital inputs to "Logic 1".
4. Adjust fOUT2 amplifier offset zero adjust trimpot for OV
±O.lmVat IOUT2 amplifier output:
5. Connect a short circuit across R2.
6. Connect all digital inputs to "Logic 0".
7. Adjusf lauT2 amplifier offset zero adjust trim pot for OV
±0.1 mV at lauTl amplifier output.
8. Remove short circuit across R2.
9. Connect MSB (Bit 1) to "Logic 1" and all other bits to
"Logic 0".
10. Adjust R4 for OV ±0.2mV at VOUT.

BIPOLAR (OFFSET BINARY) OPERATION
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 10. Using offset binary di!;lital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
"Digital Input Code/Analog Output Value" table for bipolar
mode is given in Table 2.
VREF

BIT 1

(M~B)

·,811--------,

I

I
I
I

>---<~t-VOUT

I
DIGITAL:
INPUT I

AD7541

I

Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 -' 1/211) volts reading.
3. To increase voui, connect a series resistor, (0 to 500
ohms), in the IOUTl amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (0 to 500
ohms), between the reference voltage and the VREF
terminal.

I
I
I
I

o--,I-~15
BIT 12 (LSB)

R"

500.0

~";;-...I

GND

Note: R1 and R2 should be 0.01%, low- T~R resistors.
Figure 10.. Bipolar Operation (4~Quadrant Multiplication)

A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to loun bus.
A "Logic 0" input forces the bit currentto IOUT2 bus. For any
.code the IOUTl and IOUT2 bus currents are complements of
one another. The current amplifier at IOUT2 changes the
polarity of IOUT2 current and the transconductance
amplifier at loun output sums the two currents. This configuration doubles the output range but halves the resolution
of the DAC. The difference current resulting at zero offset
binary code, (MSB = "Logic 1", All other bits = "Logic 0"), is
corrected by using an external resistive divider, from
VREF to IOUT2.

Code Table -

DIGITAL INPUT
111111111111
100000000001
100000000000
011111111111
000000000001
000000000000
4-86

TABLE 2
Bipolar (Offset Binary) Operation

ANALOG OUTPUT
-VREF (1 - 1/211)
-VREF (1/211)
0
VREF (1/211)
VREF (1 -1/211)
VREF

AD7541

,O~OIl.
+1SV

VREF +10V

17

BIT 1 (MSB)

<>:;==:1'

BIT2<>

BIT 12

5
5Y/DIV

Your

(LSB)o--!---11~5~""':~

Figure 11. General DAC Circuit with Compensation
Capacitor, Cc.

I
IJ

1\
It

L
IJ

It

It

Figure 14. AD7541 Response with: A = Intersil 2520

DYNAMIC PERFORMANCE The dynamic performance of the DAC, also depends on the
output amplifier selection. For low speed or stati~applica, tions, AC specifications of the amplifier are not very critical.
For high-speed applications slew-rate, settling-time, 'openloop gain and gain/phase-margin specifications of the
amplifier should be selected for the desired performance.

20~s/DIV

SV/DIV

II

r

1

The output impedance of the AD7541 looking into 10UT1
varies between 10k!l (RFee'dback alone) and 5kU (RFeedback in
parallel with the ladder resistance).
Similarly the output capacitance varies between' the
minimum and the maximum values depending on the input
code. These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.

Figure 12. AD7541 Response with: A = Intersil 741 HS

A capacitor in parallel with the feedback resistor provides the
necessary phase compensation to critically damp the
output.

1 s/DIY

"

5V1DIV

I
!j

1\

\

" I

I

'0

A small capacitor connected to the compensation pin of the
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.

1\

1\

Three typical circuits and the resultant waveforms are shownin Figures 11 to 14. A low-cost general purpose IIntersil
741 HS), a low-cost high-speed (Intersi! 2515) and a 'highspeed fast-settling IIntersil 2520) amplifier cover the
principal application areas.

Figure 13. AD7541 Response with: A = Intersil 2515
Cc ~ 15pF

INPUT SIGNAL'WARNING

Because otthe input protection diodes on the logic inputs, it is important that no voltage greater than 4V outside
the logic supply rails be applied to these inputs at any time, including power·up and other transients. To do so
could cause destructive SeR latch·up.'

4·87

~

ICLS01SA/S019A/S020A
Quad Current Switch for
D/ A Conversion

FEATURES

GENERAL DESCRIPTION

• TTL Compatible: LOW-0.8V
HIGH-2.0V
• 12 Bit Accuracy
• 40 nsec, Switching Speed
• Wide Power Supply Range
• Low Temperature Coefficient

The Intersil ICL8018A family are high speed precIsion
current switches for use in current summing digital-toanalog converters. They consist of four logically controlled
current switches end a reference device on a single
monolithic silicon chip. The reference transistor, combined
with precision resistors and an external source, determines
the magnitude of the currents to be summed. By weighting
the currents in proportion to the binary bit which controls
. them, the total output current will be proportional to the
binary number represented by the input logic I~vels.
The performance arid 'economy of this family make them
ideal for use in digital-to-analog converters. for industrial
process control and instrumentation systems.

APPLICATIONS:
• D/A-A/D Converters

•
•
•
•

Digital ThreshoJd Control
Programmable Voltage Source
Meter Drive
I
X-V Plotters

PIN DIAGRAM

SCHEMATIC DIAGRAM
EQUIVALENT CIRCUIT

v+
MSB
LOGIC INPUTS

r-~~--~A~--

____~

BIT 4

BIT 3

BIT2

BIT 1

5

4

3

2

2

LOGIC { BIT 2
INPUTS BIT 3

v+

::: :}TO
PRECISION
BIT 3 RESISTORS

BIT4

1

COMPENSATION {E
. TRANSISTOR C

D12

BIT4
9

6

BASE LINE

OUTLINE DWGS
JO. PO

ORDERING INFORMATION
REFERENCE
TRANSISTOR

9,

lOUT

BASE

6
EMITTER

10
\

BIT 4

11

12

13

BIT 3

BIT 2

BIT 1

40k

COMMERCIAL
TEMP RANGE
PLASTIC DIP

ICL8018AMJD
ICL8019AMJD
ICL8020AMJD

ICL8018ACPD
ICL8019ACPD
ICL8020ACPD

ICL8018AMXJD
.ICL8019AMXJD
ICL8020AMXJD

ICL8018ACXPD
ICL8019AGXPD
ICL8020ACXPD

-NOTE: Units ordered in equal quantities will be matched such
that the Vbe'S of the 8019 will be within ±10mV of the 8018 compensating transistor, and the Vbe'S ·of the 8020 will be within
±50mV. The ICL8018 - X matched sets consist of one 8018,one
8019, and one 8020. The ~019 - X contains one 8019 and one 8020,
while the 8020· X contains two 8020's, Units shipped as matched
sets will be marked with unique set number,

)

TO PRECISION RESISTORS

aOk

ACCURACY
Individual Devices
.01%
0.1%
1.0%
Matched Sets'
·,01%
0.1%
1.0%

MILITARY
TEMP RANGE
GERDIP

20k , 1 0 k

a

4·88

ICLS01SA/S019A/S020A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .............. '................................... :. . . . . . .. ±20V
Logic Input Voltage .................................................. -2V to V+
Output Voltage ............................................... VBASELINE to + 20V
VBASELINE ........................................................... V- to +5V
Storage Temperature ......................................... -65°C to +150°C
Operating Temperature ICL8018AM
ICL8019AM : .......................... -55°C to +125°C
ICL8020AM
ICL8018AC
I CL8019AC ............................... 0° C to +70° C
ICL8010AC
Lead Temperature (soldering 10sec) ..................................... 300°C
Stresses above' those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sectio(ls of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (4.5V:S V+ :S 20V, V- = -15V, TA = 25°C, V @ pin 6 = -5V)
. PARAMETER
Absolute Error
ICL8018A
ICL8019A
ICL8020A
Error Temperature Coefficient
ICL8018A
ICL8019A
ICL8020A
Switching Time To Turn On LSB
Output Current (Nominal)
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4 (LSB)
Zero Output Current
Output Voltage Range
Input COding-Complimentary Binary
(See Truth Table)
Logic Input Voltage
"a" (Switch ON)
"1" (Switch OFF)

CONDITIONS

MIN

TYP

VINHI = 5.0V
VINLO = O.OV

±2
±2
±2
40
1.0
0.5
0.25
0.125
10

~,

VIN = 5.0V
VBASELINE +1V

MAX

UNITS

±.01
±0.1
±1

%

±5
±25
±50

ppm/oC

ns
mA

50
+10

nA
V

0.8

V

-2
0.1

mA
pA

LlloUT <400nA
2.0

Logic Input Current

"a"
"1" (into device)
Power Supply Rejection
V+
V-

-1.0
0.01

VIN = OV
VIN = 5V

%N

.005
.0005

Supply Voltage Range
V"
V-

4.5
-10

Supply Current (Vsupp= ±20V)
1+
1-

5
-15

20
-20

V

7

10
3

mA

1

4-89

ICLS01SA/S019A/S020A
BASIC D/A THEORY

10.0 volts the maximum output would be

The majority of digital to analog converters contain the
elements shown in Figure 1. The heart ofthe 01A converter is
the logic controlled switching network, whose output is an ,
analog current or voltage proportional to the digital number
on the logic inputs. The magnitude of the analog output is
determined by the reference supply and the array of
precisiqn resistqrs, see fig: 2. If the switching network has a
current output, often a transconductance amplifier Is used to
prollide a voltage output.
, LOGIC INPUTS

REFERENCE

SWITCHING NETWORK

RESISTOR ARRAY

Ii

Figure 1: Elements of a DfA Converter
Nominal
Otltput
Current (mA)
1.875
1.750
1.625
1.500
1.375
1.250
1.125
1.000
0.825
0.750
0.625
0.500
0.375
0.250
0.125
0.000

.Logic·lnput
0000
000 1
001 0
00 1 1
o1 0 0
o1 0 1
o1 1 0
o 1 1· 1
1 000
100 1
10 1 0
101 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

:~~~ X 10V. Since

the numbers are extremely close for high resolution systems,
the terms are often used interchangeably.
'
The accuracy of a 01 A converter is generally taken to mean
the largest error of any output level from its nominal value.
The accuracy or. absolute error is often expressed as a
percentage of the full scale output.
Linearity relates the maximum error in terms of the deviation
from'the best straight line drawn through all the possible
output levels. Linearity is related to accuracy by the scale
factor and output offset. If the scale factor is exactly the
nominal value and offset is adjusted to zero, then accuracy
and linearity are identical. Linearity is usually specified as
being within ±1/2 LSB of the besf straight line.
Another desirable property of 01 A converter is that it be
monotonic. This simply implies that each successive output
level is greater than the preceding one. A possible worst case
condition would be when the output changes from most
significant bit (MSB) OFF, all other bits ON to the next level
which has the MSB ON and all other bits OFF, e.g., 10000 ...
to 01111.
In applications where a quad current switch drives a
transconductance amplifier (current to voltage co'nverter),
transient response is almost exclusively determined by the
output amplifier itself. Where the quad output cur~ent drive~
a resistor.to ground, switching time and settling time are
useful parameters .
Switching time is the familiar 10% to 90% rise time type of
measurement. Low capacitance scope probes must be used
to avoid masking, the high speeds that current source
switching affords. The settling time is the elapsed time
between the application of a fast input pulse and the time at
which the output voltage has settled to or approached its
final value within a specified limit of accuracy. This limit of
accuracy should be commensurate with the resolution of the
OAC to be used.
Typically, the settling time specification describes how soon
after'an input pulse the output can be relied upon as accurate
to within ±1/2 LSB of an N bit converter. Since the 8018A
family has been desiged with all the collectors of the current
switching transistors tied together, the output capacitance is
constant. The transient response is, therefore, a Simple
exponential relationship, and from this thesettling time can
be calculated and related to the measured rise time as shown
in Figure 3.

Figure 2: Truth Table

DEFINITION OF TERMS
Bit,!! of
±1/2 LSB Error
Number of
Number of
Resolution, % Fuli'Scale Time Constants Rise Times
.2 %
6.2
2.8
8
.05%
10
7.6
3.4
12.
.01%
9.2
4.2
Rise Time (10%-90%) = 2.2 RL Ceff

The resolution of a O/A converter refers to the number of
logic inputs used to control the analog output. For example,
a 01A converter using two quad current sources would be an
8 bit converter. If thre,e quads were used, a 12 bit converter
would be formed. Resolution is otten stated in terms of one
part in, e.g., 256 since the number ·of controlling bits is
related to totai number Of identifiable levels by the power of
2. The four bit quad has sixteen different'leveis (see Truth
Table) each output corresponding to a particular logic input
word.
.
,

Figure 3: Settling Time

VS.

Rise Time Resistor Load

CIRCUIT OPERATION

Note that maximum output of the quad switch is 1 + 1/2 + 1/4
+ 1/8 = 1-7/8 = 1.875 rnA. Ifthisseries of bits were continued
as 1/16 + 1/32 + 1/64 ..... 112 (n.1), the maximum output limil
, would approach 2:0 rnA. This limiting value is caHed full scale
output. The maximum output is always less than the full
scale'output by' one least significant bit, LSB. For a twelve bit
system (resolution 1 part in 4096) with a full scale output of .

An example of a practical circuit ,for the ICL8018A quad
current switch is shown in Figure 4. The circuit can be
analyzed in two sections; the first generates ve~ accurate
currents and the second causes these' currents to be
'switched according to input logic Signals. A reference
current of 125JLA is generated by a stable reference supply
and a precision resistor. An op-amp with low offset voltage

4-90

ICLS01SA/S019A/S020A
LOGIC INPUTS

, ,_ _ _ _ _ _

BIT4

i-I
I
I

v+

~A~

BIT 3

5

_ _ _ _ _ _,

BIT 2

BIT 1

3

2

I

I
VAEF

RS

L

IREF

VOUT

Q12
IN914

ATTENUATED OUTPUT
CURRENT FROM
OTHER QUADS

Rs
10
SOk

SOk

11

40k

12

20k

13

14

10k

Figure 4: Typical Circuit
and low input bias current, such as the ICL8008, is used in
conjunction with the internal reference transistor, 06, to
force the voltage on the common base line, so that the
collector current of 06 is equal to the reference current. The
emitter current of 06 will be the sum of the reference current
and a small base current causing a drop of slightly greater
than 10 volts across the 80k resistor in the emitter of 06.
Since this resistor is connected to -15V, this puts the emitter
of 06 at nearly -5V and the common base line at one VBE
more positive at -4.35V typically.
Also connected to the common base line are the switched
current source transistors 07 through 010. The emitters of
these transistors are also connected through weighted
precision resistors to -15V and their collector currents
summed at pin 8. Since all these transistors, 06 through 010,
are designed to have equal emitter-base voltages, it follows
that all the emitter resistors will have equal voltage drops
across them. It is this constant voltage and the precision
resistors at the emitter that determine the exact value of
switched output current. Theemitter resistor of 07 is equal to
that of 06, therefore, Ois collector current will be IREF or
125/lA. 08 has 40k in the ernitter so that its collector current
will be twice IREF or 250/lA. In the same way, the 20k and 10k
in the emitters of 09 and 010 contribute.5 rnA and 1 rnA to the
total collector current.
The reference transistor and four current switching
transistors are designed for equal emitter current density by
making the number of emitters proportional to the current
switched.
The remaining circuitry provides switching signals from the
logic inputs. In the switch ON mode, zener diodes Ds
through D8, connected to the emitter of each current switch
transistor 07 thru OlD, are reverse biased allowing the
transistors to operate, producing precision currents
summed in tile collectors. The transistors are turned off by

raising the voltage on the zeners high enough to turn on the
zeners and raise tile emitters of the switching transistor. This
reverse .biases the emitter base diode th'ereby shutting off
that transistor's collector current.
The analog output current can be used to drive one load
directly, (1 kfl to ground for FS = 1.875V for example) or can
be used to drive a transconductance amplifier to give larger
output voltages.

EXPANDING THE QUAD SWITCH
While there are few requirements for only 4 bit D to A
converters, the 8018A is readily expanded to 8 and 12 bits
with the addition of other quads and resistor dividers as
shown in Figure 5.
To maintain the progression of binary weighted bit currents,
the current output of the first quad drives the input of, the
transconductance amplifier directly, while a resistor divider
network divides the output current of the second quad by 16
and the. output current of the third by 256.
e.g.,ITotal= 1 x(1 +1/2+1/4+1/8)+1/16(1+1/2+1/4+1/8)
+ 11256 (1 + 1/2 + 1/4+ 1/8)=1 + 1/2+ 1/4+ 1/8+
1/1E) + 1/32 + 1/64 + 1/128 + 1/256 + 1/512 +
1/1024 + 1/2048.
Note that each current switch is operating at the same high
speed current levels so that standard 10k, 20k, 40k and 80k
resistor networks can be used. 'Another advantage of this
technique is that since the current outputs of the second and
third quad are attenuated, so are the errors they contribute.
This allows the use of less accurate switches and resistor
networks in these positions; hence, the three accuracy
grades of .01%,,0.1%, and 1% for the 8018A, 8019A and,
8020A, respectively. It should be noted that only the.
reference transistor on the most significant quad is
required to set up the voltage on the common base line
joining the three sets of switching transistors (Pin 9),
4-91

ICLS01SA/S019A/S020A
ANALOG
VOLTAGE OUT

VREF

LOGIC ,INPUTS

LIREF

II
:.I

Figure 5: Expanding the Quad Switch

the external zener will dominate the temperature
dependence of this scheme, however using a temperature
compensated zener minimizes this problem. Since 06 is
operating at' a higher current density than the other
switching transistors, the temperature matching of VBE'S is
not optimum, but should be adequate for a simple 8 or 10 bit
converter.
The 8018A series is tested for accuracy with 10V reference
voltage across the precision resistors, implying use of a 10
volt zener. Using a different external zener voltage will only
slightly degrade accuracy if the zener voltage is above 5 or 6
volts.
When using other than 10 volt reference, the effects on logic
thresholds should also be noted (see logic levels belowl. Full
scale adjustment can be made at the output amplifier.

GENERATING REFERENCE CURRENTS ZENER REFERENCE
'
As mentioned above, the 8018A switches currents
dete.r'mined by a constant voltage across the external
precision resistors in the emitter of each switch. There are
several ways of generating this constant voltage. One of the
simplest is shown in Figure 6. Here an external zener diode is
driven by the same current source line used to bias internal
Zener D11.
v+
BIT 4
BIT 3
BIT 2
BIT 1
3

2

1
012

PNP REFERENCE
Another simple reference scheme is shown in Figure 7. Here
an external PN P transistor is used to buffer a resistor divider.
In this case, the -15 volt supply is used as a reference.
Holding the V- supply constant is not too difficult since the
8018A is essentially a constant current load. In this scheme,
the internal compensation transistor is not-necessary, since
the VBE matching is provided by the emitter-base junction of
the external transistor. A small pot in series with the divider
facilitates full scale output adjustment. A capacitor from
base to collector of the external PNP will lower output
impedance and minimize tranSient effecis.

8

.--I----.-+~-+_.--t--+-+--<>IOUT
'-<~F-="'----f--O"---+-+---=:'----l+-=--++-=::":'::+-----.J-

- - -

TO
OTHER
QUADS

Q12

FULL COMPENSATION REFERENCE
13

14

For high accuracy, low drift applications, the reference
scheme of Figure 4, offers excellent performance. In this circuit, a high gain op-amp compares two currents. The first is a
reference current generated in Rs by the temperature compensated zener and the virtual ground at the non-inverting opamp input. The second is the collector current of the
reference transistor 06, provided on the quad switch. The
output of the op-amp drives the base of 06 keeping its
collector current exactly equal to the reference current.
Since the switching transistor's emitter current densities are
equal and sirice the preciSion resistors are proportional, all
of the switched collector currents will have the proper value.

10k

-15V

Figure 6: Simple Zener Reference

The zener current will be typically 1 mA per quad. The
compensation transistor 06 is connected as a diode in series'
with the external zener. T,he VSE of this transistor will
approximately match the VSE'S of the current switching
transistors, thereby forcing the external zener voltage across
each of the external resistors. The temperature coefficient of

4-92

ICLS01SA/S019A/S020A
BIT4

BIT 3
4

5

BIT 2

BIT 1

3

2

V+

1
012

--TO
OTHER
QUADS
Q12

10

14

80k

-15V

Figure 7: PNP Reference

+15V
360

2k
20k

+15V
3.9k
510

'

~~O\'UI\TI'PvU_T-..O_F_FS_E_T-'-

f

ADJUST
10M

5k
_ _-+-I

EOUT

10k
-15V

r

30PF

RlI:
14.0625k

14.0625k'

R,S
937.5

IN914

51k

'1000pF

R9
80k

80k

-15V
NOTE: ALL RESISTORS RATIO TO Rl
UNLESS OTHERWISE NOTED.

Rl
R2
R3
R4
Rs

TOLERANCE TABLE
10k
0.1% ABS

20k
40k

0.0122%
0.0244%

80k
10k

0.0488%
0.096%

RB
R7
Rs
R9
RlO
R11

20k
40k
80k
80k
10k
20k

Figure 8

4·93

0.195%
0.391%
0.781%
0.1%
0.5% ABS
RATIO TO RlO 1%

R12
R'3
R14
R,S
R1B
R17

40k
80k
lk
937.5fi
14.0625k
14.0625k

RATIO TO RlO 1%
RATIO TO RlO 1%

l%ABS

l0f0ABS
RATIO TO R15 1%
RATIOTOR'40.1%

10k

O~OIL

ICLS018A/8019A/8020A
The op-amp feedback loop using the internal reference
transistor will maintain proper currents in spite of VSE drift,
beta drift, resistor drift and changes in V-.Using this circuit,
,temperature drifts of 2 ppm/o C are typical. A discrete diode
· connected as shown will keep Q6 from saturating and
prevent latch up if V- is disconnected.
In any reference scheme, it is advisable to capacitively
decouple the common base line to minimize transient
effects. A capacitor, .001/lF to .1/lF from Pin 9 to analog
ground is usually sufficient.

MULTIPLYING DAC
The circuit of Figure 9 is also convenient to use as a one
quadrant multiplying D/A converter. In a multiplying DAC,
the analog output is proportional to the product of a digital
number and an analog signal. The digital number drives the
logic inputs, while the analog signal replaces the constant
reference voltage, and produces a current to set up the
regulating BOOB op-amp. To vary the magnitude of currents
being switched, the voltage across all the 10k, 20k, 40k and'
BOk resistors must be modulated according to the analog
input. An analog input of 0 to +10 volts and an BOk resistor at
the input to the BOOB will fulfill this requirement. .

IMPROVED ACCURACY

II
~

CALIBRATING THE 12 BIT D/A CONVERTER

As a final note on the subject of setting up reference levels, it
should be pointed out that the largest contributor of error is
the mismatch of VSE'S of the current switching transistors.
That is, if all the VSE'S were identical, then all precision
resistors would have exactly the same reference voltage
across them. A one millivolt mismatch compared'with ten
volt reference across the precision resistors wi II cause a .01 %
error. While decreasing the reference voltage will decrease
the accuracy, the voltage can be increased to achieve better
than .01% accuracies. The voltage across the emitter
resistors can be doubled or tripled with a' proportional
inc~ease in resistor values resulting in improved absolute
accuracy as well as improved temperature drift performance.
This technique has been used successfully to implement up
to 16 bit DI A converters.

1. With all logic inputs high (ones) adjust the output amplifier'
offset for zero volts out.
2. Put in the word 0000 1111 1111 (Quad 1 maximum output
Quad 2 and 3 off) and adjust full scale pot for Va of 15/16
(10V) where full scale output is to be 10 volts.
3. Put in the word 1111 00001111 and trim the Quad 2 divider
for Va of 15/256 (10Vl. This adjustment compensates for
VSE mismatches between quads although matched sets
are available (see data sheet).
4. Put in the word 1111'1111 0000 and trim the Quad 3 divider
for Vo of 15/4096 (10Vl.
5. Finally, with all bits ON (all O's) readjust the full scale
factor pot for
Va = 4095/4096 (10V)

SYSTEM INTERFACE REQUIREMENTS

PRACTICAL D/A CONVERTERS

Using the 801BA series in practical circuits requires
consideration of the following interface requirements.
Logic Levels: The B01BA is designed to be compatible with
TTL, DTL and RTL logic drive systems. The one constraint
imposed on the external voltage levels is that the emitters of
the conducting current switch transistors be in the vicinity of
-5V; this will be the same as the voltage on Pin 6 if the
reference transistor is used. When using other than -5V at
Pin 6, tl'le direct bearing on logic threshold should be
considered.
Power Supplies: One advantage of the ICLB01BA is its
tolerance of a wide range of supply voltage. The positive
supply voltage need only be large enough (greater than
+4.5V) to keep Q11 out of saturation, and the negative supply
needs to be more negative than -10V to ensure constant
current operation of Q12. The maximum supply voltage of
±20V is dictated by transistor breakdown voltages. It is often
convenient to use ±15V supplies in systems with op-amps
and other I.C.'s. These supplies tend to be better regulated
and free from high·current transients found.on supplies used
to power TTL Logic. As with any high speed circuit, attention
to layout and adequate power supply decoupling will
minimize switching effects.
Ground: High resolution D/A, e.g., 12 bits require fairly large
logic drive currents. The change from all bits ON to all bits
OFF is a' considerable change in supply current being
returned to ground. Because of this, it is usually advisable to
maintain separate ground pOints for the analog and digital
sections.
Resislors:Each quad current switch requires 'a set ,of
matched resistors scaled proportional to their binary
currents as R, 2R, 4R and BR. For a 10V resistor voltage drop
and "2 mA" full scale output current. resistor values of 10k,
20k, 40k and 80k are convenient. Other resistor values can be
used, for example, to increase total output current. The

The complete circuit for a high performance 12 bit D/A
converter is shown in Figure B. This circuit uses the "full
compensation reference" described above to set the base
line drive at the proper level, the temperature compensated
zener is stabilized using an op-amp as a regulated supply,
and the circuit provides ~ very stable, precise voltage
· reference for the D/A converter. The 16:1 and 256:1 resistor
divider values are shown for a straight binary system; for a
binary coded decimal system the dividers would be 10:1 and
100:1 -

u

LOO

I

~I

(5
::>

8
:;:

I

30

~

"9
u

u
-'

"u>-iC

10

I-

100

3000

CLOCK CAPACITOR - pF

FIGURE 2_
The 7101 has an internal clock which requires a single
capacitor between Pins 25' and 28 to operate_ Figure 2
shows the, typical capacitor value required to give the
desired frequency.
During auto-zero, the clock is internally gated-off with
Pin 28 high and Pin 25 low. When "start-reset" goes high,
starting a measurement cycle, the clock starts counting
with Pins 25 and 28 immediately changing ·phase. The
counting continues until the end of the 'measurement
. cycle, at which time the clock is returned to its auto-zero
condition.

In a typical application where visual readings are required,
three readings per second is near the optimum speed. Faster
readings make it difficult to resolve individual rea'dings,
while at slower rates the reader has to wait too long between
measurements_ In this applicatipn, 40% of the time (133mS)'
could be allocated to auto-zero and 60% (200mS) to signal
and reference integrate. Since a measurement cycle consists
of 3,000 clock pulses maximu~, this dictates' a clock
frequency of 15kHz. Also, since the dual:slope technique
of A/D conversion is not first-order dependent on clock
frequency, the '±20% variation of clock frequency from
unit-to-unit would result in no measurable error. However,
in some applications, a more precise clock frequency would
be desired. For instance, if precise rejection of 60Hz is
require·d, the signal integrate phase (1,000 counts) would
have to contain an integral number of 60Hz periods. For
these applications, an external clock can be used by deleting
the capacitor and connecting the external clock to Pin 25.
However, if the clock is run asynchronously with start/reset,
there will be one clock pulse of uncertainty in the integrate
signal time, depending on where in the clock pulse period
the start/reset went' high_ This will show up as one count
of noise for signal near full-scale: This noise or jitter can be
avoided by synchronizing the start/reset pulse to the
negative-going edge of the external clock. Pin 33, Gated
Clock Out, is a buffered output of the clock (internal or
external) that is off (low) during auto-zero and in phase
with Pin 25 during measurement.
Component·Selection
Except for the reference Voltage, none of the component
values are first order important in determining the accura<:Y
of the instrument While this is undoubtedly an advantage
of this approach, it does make the selection of nominal
component values arbitrary at best. For instance, the
reference capacitor and auto-zero capacitor are each shown
as 1.0pfd. These relatively large values are selected to give
greater immunity to PC board leakage since much smaller
capacitors are ·adequate for ·charge injection errors or
leakage errors from the 8052/7101.
The ratio of integrating resistor and capacitor is selected to
give 9-volt swing for full-scale inputs. This is a compromise
between possibly saturating the integrator (at ±14V) due
to tolerance build-up between the resistor, capacitor, and
clock and the errors a lower voltage swirg could induce
due to offsets referred to the output of the comparator.
Again, the .22pfd value for, the integrating capacitor is
selected for PC board considerations alone since the very
small leakage at the integrator input is nulled at auto-zero.
A very important characteristic of the integrating capacitor
is low dielectric absorption. A polypropylene capacitor
gave excellent results. In fact, a good test for dielectric
absorption is to use the capacitor in this circuit with the
input tied to reference. This ratiometric condition should
read 1.000 and any deviation is probably due to dielectric
aDsorption_ In this ratiometric condition, a polycarbonate
capacitor contributed an error of approximately 0.8 digit,
polystyrene about 0.3 digit, and polypropylene less than
0.05 digit. The increased T.C. of polypropylene is of no
consequence in this circuit. The dielectric absorption of the
reference capacitor and auto-zero capacitor are only impor-.
tant at power on or when the circuit is recovering'from an
overload. Thus, smaller or cheaper capacitors can be used
here if accurate readings are not requ'ired for the first few
seconds of recovery.
4-100

D~DIL

ICL805217101
The back·to·back diodes on the comparator ·output are
recommended in the 200.0mV range to reduce the noise
effects. In the normal operating mode, they offer a high
impedance and long integrating time constant to any noise
pulses charging the auto·zero capacitor. At start·up or
.recovery from an overload, their impedance is low to large
signals so the capacitor can' be charged in one auto· zero
cycle. If only the 2.000V range is used, a 100k resistor in
place of the back·to·back diodes is adequate for noise
effects.

meter reading will change from 0 to 1 with 50pV in, 1 to
2 with 150pV, 2 to 3 at 250pV, etc. This transition at mid·
point is considered desirable ·by most users. However, if
the clock frequency is increased appreciably above this,
the instrument will flash 1 on noise peaks even when the
input is shorted.
Some circuits use positive feedback or a latch to solve the
delay· problem. However, unless the comparator voltage
swing, the comparator gain, and the integrator gain are
carefully controlled, this circuit can generate anticipation
errors that greatly exceed the 3pS delay error. Also, it is
very susceptible to noisespikes. A more controlled approach
for extending the conversion rate is the use of a small
resistor in the integrator feedback loop. Th is feeds a small
pulse to the comparator to get it moving _quickly· and
partially compensate for its delay.

Maximum Clock Frequency
The maximum conversion rate of most dual·slope A/D
converters is limited by the frequency response of the
comparator. Even though the comparator in this circuit
is all NPN with an open loop gain·bandwidth product
of 300M Hz, it is no exception. The compar.ator output
follows the integrator ramp with a3pS delay'. At a clock
frequency of 160kHz (6pS period), half of the first refer·
ence integrate period is lost in delay. This means that the

The minimum clock frequency is established by leakage on
the auto·zero and reference capacitor. With most devices,
measurement cy'cles as long as 10 seconds gave no measur·
able leakage error.

APPLICATIONS
8052/7101 3Y, Digit LCD DPM/DVM
Figure 3 illustrates an application where the 8052/7101
interfaces with a Liquid Crystal Display. The CD4054 and
CD4055s are Liquid Crystal Display Drivers (4·segment and
7·segment, respectively) which provide the level shifting
(up to 30V p . p at VDD-V EE = 15V) necessary to drive the
LCD. Overrange is indicated by a special character. If
blanking of any part of the display is required on overload,

Pin 23 (7101) can be used to drive Pin 7 on those display
drivers via an inverter and level shift such as CD4009 or
74C903 or another CD4054. Display applications requiring
a plus sign rather than a blank indication for positive analog
input levels (i.e., +1.999 versus 1.999) need to invert the
"polarity" logic output level which is normally high for
positive analog input signals.

D

r---~~~~~~--~----------,

.;? TO

r-----H+H-H-r--+H--H+h---+-H+H+r+---r

-2V S; VIN S; +2V

Leakage Current at Input
Zero Reading Drift

Note
Note
Note
Note

S052171 C03(1)
S052A171 C03A(2)
MIN
TYP
MAX
MIN
TYP
MAX
-{l,OOO ±O,OOO +0,000 -{l,OOOO ±O,OOOO +0,0000

0,2

,01

LSB

Digital
Count
Error

1

0,5

20
50
5
1

30
5

30
3
0,5

10
2

pA
p.V/oC

3

15

2

5

ppm/oC

1

p.V

Tested in 3-1/2 digit (2,000 count) circuit shown in'Fig, 7, clock frequency 12kHz, Pin 2 71C03 connected to Gnd,
Tested in 4c1/2 digit (20,000 count) circuit shown in Fig 7, clock frequency 120kHz, Pin 2 71C03A open,
Tested with a low dielectric absorption integratirig capacitor. See Component 'Selection Section,
The temperature range can be extended to +70°C and beyond,as long as the auto-zero and reference capacitors are increased to
absorb the higher leakage of the 8068,

4·107

O~OI!:.

8052/71 C03' 8068/71 C03
10k
-= +15V-15V

n

C]

lOOk

90k

-INT,IN

INT,OUT

11

li"---l

INTEGRATOR

l:t

'-'

I
I

I'
II

P~!:.A~~~ D5
3
19

II

'

D4

D3

D2

Dl

24

25

26

27

, SEVEN
SEG.
DECODE

-'-'--1

LSD

. . MSD

I
I
I
I
I
-l

b:1

.. MULTIPi.'EXER

I
20 I Bl '
21 B2
22 B4
23 B8

_ _ PETAlLED DESCR;PTION'

iii

Analog Section
,.
Figure 2 shows the equivalent Circuit of the Analog Section
o both the ICL71C03/8052 and the ICL71C03/8068 in the 3
different 'phases 'of operation. If the RUN/HOLD pin is left
open or tied to V+, the system will perform conversions at a
rate 'determined by the clock frequency: 40,002 at 4·1/2 digit
and 4002 at 3·112 digit clock periods per cycle (see Figure 3
for details of conversion timirt$l)'

1. Auto·Zero Phase.1 Fig. 2A.
'During Auto·Zero, the Input of the circuit is' shorted to
ANALOG GROUND through switch 1, and switch 3 closes
a'ioop around the integrator and' comparator, the pur;
pose of whlc~ If; to charge the auto·zero capacitor until
theintegratoroufputdoes not change witl:! time. Also,
switches 1 and 2 recharge the reference capacitor to
VREF' ,

.

SW4

SW4

SW3

SW3

ICAUTO ZERO

ICAUTOZERO

Figure 2A: Phase I Auto'-Zero

Figure 2C: Phase I!I

SW4

+ Deintegrate

, SW4

.*

SW3

I

~AU!~ ZERO

Figure 28: Phase II Integrate Jnput "

CA~TO ZERO,

Figure 20: Phase III - Deintegrate

Figure 2: A~alog Section of Either ICL8052 or ICL8068 with ICL71C03

4·108

8052/71 C03 8068/7·1 C03
3. Deintegrate Phase III Fig. 2C&D.

2. Input Integrate Phase II Fig. 2B.

During the Deintegrate phase, the switch drive logic uses
the output of the polarity F/F in determining whether to
close switch 6 or 5.lf the input signal is positive, switch 6 is
closed and a voltage which is VREF more negative thi}n
during Auto·Zero is impressed on the BUFFER INPUT.
Negative'lnputs will cause ± VREF to be applied to the
BUFFER INPUT via switch 5. Thus, the reference
capacitor generates the equivalent of a (+) or (-)
reference from the single reference voltage with negligi·
ble error, The reference voltage returns the output of the
integrator to the zero·crossing point established in Phase
I. The time, or number of counts, required to do this is
proportiona: to the input voltage. Since the Deintegrate
phase can be twice as long as the Input Integrate phase,
the input voltage required to give a full scale reading
= 2V REF ·
.

During Input Integrate the auto·zero loop is opened and
the ANALOG INPUT is connected to the BUFFER INPUT
through switch 4. If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous state (Auto·Zero). Thus, the
integrator output will not change but will remain sta·
tionary during the entire Input Integrate cycle. If VIN is not
equal to zero, an unbalanced condition exists compared
to the Auto·Zero phase, and the integrator' will generate
a ramp whose' slope is p'roportional to VIN. At the end of
this phase, the sign of the ramp is latched into the polar·
ity F/F.

POLARITY
DETECTED---..

INTEGRATOR' I
OUTPUT
,I

hz

CLOCK
INTERNAL LATCH

ZERO CROSSING
OCCURS
I
~I'
ZERO CROSSING I
I -' ~
I'" ~
/DETECTED
I
.
PHASE I---l--INT PHASE I I ;
~;2 DEINT PHASE III-I-AZ~

1/

h..r ~
.nnn.h..
,..nnnn.r
~
I
I
I
I

I

I

I

I

BUSY OUTPUT I
I

I

I '

n

I

I

I

I

I

I

CROSSIN~/

NUMB.ER OF COUNTS TO ZERO
PROPORTIONAL TO

VIN

COUNTS
Phase I
Phase II
10,000
10,001
1,000
1,001

4-1/2 digit
3-1/2 digit

.'

I
I
I
I

~AFTER
ZERO CROSSING,
ANALOG SECTION WILL
, BE IN AUTOZERO
CONFIGURATION
Phase III
20,001
2,001

Figure 3: Conversion Timing

Zero-Crossing Flip Flop

The integrator output is approaching the zero-crossing point
where the count will be latched and t.he reading displayed.
For a 20,000 count instrument, the ramp is changing
approximately 0.50mV per clock pulse (10 volt max
integrator output divided by 20,000 counts!. The clock pulse
feedthrough superimposed upon this ramp would have to be
less than 100l'Vpeak to avoid causing significant errors.
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not ,recognized. Of course, the flip-flop delays the
true zero-crossing by one count in every instance, and if a
correction were not made, the display would always be one
count too high. Therefore the counter is disabled for one
clock pulse at the beginning of phase 3. This one count delay
compensates for the delay of the zero-crOSSing flip-flop, and
allows the correct number to be latched into the display.
Si~ilarly, a one count delay atthe beginning of phase 1 gives
an overload display of 0000 instead of 0001. No delay occurs
during phase 2, so that true ratiometric readings result

Fig. 4 shows the problem that the zero-crossing FIF is
designed to solve.

CLOCK
PULSE

~FEEDTHROUGH

/

Figure 4: Integrator Output Near Zero-Crossing

4·109

S052/71C03 S06S/71C03
DETAILED DESCRIPTION
Digital Section

II
~

verter. The output F·F is set at the end of BUSY and is
reset to zero at the beginning of Reference Integrate in
the next measurement cycle.
6. UNDER·RANGE (Pin 13). This pin goes positive when
the reading is 9% of range or less ..The output F·F isset
at the end of BUSY (if the new reading is 1800/180 or less)
and is reset at the beginning of Signal Integrate of the
next reading.
7. POLARITY (Pin 3). This pin is positive for a positive in·
put signal. It is valid even for a zero reading. In other
words, +0000 means the signal is positive but less t,han
the least significant bit. The converter can be used as a
null detector by forcing equal (+) and (-) readings. The
null at this point should be less than 0.1 LSB. This output
becomes valid at the beginning of Reference Integrate
and remains, correct until it is revalidated for the next
measurement.
8. Digit Drives (Pins 19, 24, 25, 26 and 27). Each digit drive
is a positive'going signal which lasts for 200/20 clock
pulses. The scan sequence is D5 (MSD), D4, D3, D2 and D1
(LSD). All five digits are scanned even when operating in
the 3· '12 digit mode, and this scan is continuous unless
an OVER·RANGE occurs. Then all Digit drives are blanked
from the end of the STROBE sequence until the begin·
ning of Reference Integrate, at which time D5 will start
the scan again. This gives a blinking display as a visual
indication of OVER·RANGE.
9. BCD (Pins 20, 21, 22 and 23). The Binary coded decimal
bits Bs, B4 , B2 and 81 are positive logic signals that go on
simultaneously with the Digit driver.

The 71C03 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
1. 4·1/213·1/2 (Pin 2). When high (or open) the internal
counter operates as a full 4·1/2 decade counter, with a
complete measurement cycle requiring 40,002 counts.
When' held low, the least significant decade is cleared
and the clock is fed directly into the next decade. A
measurement cycle now requires only 4,002 clock pulses.
All 5 digit drivers are active in either case, with each digit
lasting 200 counts with Pin 2 high (4·1/2 digit) and 20
counts for Pin 2 low (3~ 1/2 digit).
2. RUN/HOLD (Pin 4). When high (or open) the A/D will
free·run with equally spaced measurement cycles every
40,00214,002 clock pulses. If taken low, the converter will
continue the full measurement cycle that it is doing and
then hold this reading as long as Pin 4 is held low. A
short positive pulse (greater than 300ns) will now initiate
a new measurement cycle beginning with up to
10,00111,001 counts of auto zero. Of course if the pulse
occurs before the full measurement cycle (40,002/4,002
counts) is completed, it will not be recognized and the
converter will simply complete the measurement it is do·
ing. An external indication that a full measurement cycle
has been completed is that the first STROBE pulse (see
below) will occur 101/11 counts after the end of this cy·
cle. Thus, if RUNIHOLD is low and has been low for at
least 101/11 counts, the converter is holding and ready to
, start a new measurement when pulsed high.
3. STROBE (Pin 18). This is a negative·going output pulse
that aids in transferring the BCD data to exterriallatches,
UARTs or microprocessors. There are 5 negatlve'going
STROBE pulses that occur in the center of ,each of the
digit drive pulses and occur once and only once for each
measurement cycle starting 101/11 pulses after the end
of the full measurement cycle. Digit 5 (MSD) goes high at
the end of the measurement cycle and stays on for 201/21
counts. In the center of this digit pulse (to avoid race con·
ditions between changing BCD and digit drives) the first
STROBE pulse goes negative for 1/2 clock pulse width.,
Similarly, after Digit 5, Digit 4 goes high (for 200/20 clock
pulses) and 100/10 pulses later the STROBE goes '
negative for the second time. This continues throuQh
Digit 1 (LSD) when the fifth and last STROBE pulse is
sent. The digit drive will continue to scan (unless the
previous signal was over·range) but no additional
STROBE pulses will be sent until a new measurement is
available.
4. BUSY (Pin 28). BUSY goes high at the beginning of
signal integrate and stays high until the first clock pulse
after zero·crossing (or after end of measurement in the
case of an OVER·RANGE). The internal latches are en·
abled (i.e., loaded) during the first clock pulse after BUSY
and are latched at the end of this clock pulse. The circuit
automatically reverts to auto·zero when ndt BUSY so it
may also becon'sidered an A·Z signal. A very simple
means for transmitting the data down a single wire pair
from a remote location would be to AN D BUSY with clock
and subtract 10,001/1,001 counts from the number of
pulses received - as mentioned previousty there is one
"NO·count" pulse in each Reference Integrate cycle.
5. OVER·RANGE (Pin 4). This pin goes positive when the
input signal exceeds the range (20,000/2,000) of the con·
4·110

INTEGRATOR
OUTPUT

z~~g'l SI~~~L I ~~ii~~~~iJ
~c6'8~\s
c6~~~s
10.001/

10.000/

20001/2001

COUNTS 'MAX.
FULL MEASUREMENT CYCLE
40,002/4,002 COUNTS
.

BUSY

STROBE

------lI

III I I
t"AUTOZERO

FOR

r-

'--_~

SIGNAL
INTEGRA1E

o~~~.~!~~~nL:D,,-5- - - - -......- - - 1
JnL:D~4_ _ _ _~, ..._ _~
-ll~D3~_ _ _~~_ _;-_
--ll~D2~

-r__

_ _ _.~_ _

~~--~-­
Figure 5: Timing Diagram for Outputs

U~UI!"

S052/71C03 S06S/71C03
COMPONENT VALUE SELECTION
For optimum performance of the analog section, qare must
. be taken in the selection of values forthe integrator capacitor
and resistor, auto-zero capacitor, reference voltage,. and
conversion rate. These values must be chosen to suit the
. particular application.
Integrating Resistor
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current should be small compared to the output short circuit current such that thermal
effects are kept to a minimum and linearity is not affected.
Values of 5 to 40pA give good results with a nominal of
20pA. The exact value may be chosen by
.
R
- full scale voltage·
INT 20J.lA
·Note: If gain is used in the buffer amplifier then ,R
- (Buffer gain) (full scale voltage)
.INT 20!"A
Integrating Capacitor
The product of integrating resistor and capacitor is selected
to give 9 volt swing for full scale inputs. This is a compromise
between posl:\ibly saturating the integrator (at +14 volts) due
to tolerance build-up between the resistor, capacitor and
clock and the errors a lower voltage swing could induce due
to offsets referred to the output of the comparator. In
general, the value of CINT is given by
. ]
[10,000 (4-1/2 digit)
C
= 1000 (3-1/2 digit) X clock penod) X (20J.lA)
INT
Integrator output voltage swing
A very important characteristic of the integrating capacitor is
that it has low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale 1.0000, and
any deviation is probably due to dielectric, absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.
Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor' should be large enough such that
stray capacitance to ground from its nodes is negligible.
Note: When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero
capacitor. As a rule of thumb, the reference capacitor should
be approximately the gain. times the value of the/auto-zero
capacitor. The dielectric absorption of the reference cap
and auto-zero cap are only important at power-on or when
the circuit is recovering from an overload. Thus, smaller or
cheaper caps can be used here if accurate readings are not
required for the first few seconds 0.1 recovery.
Reference Voltage
The analog input required to generate a full scale output is
VIN = 2 VREF.
The stability of the reference voltage is a major factor in the'
overall absolute accuracy of the converter. For this reason, it
is recommended that an external high quality reference be
used where the ambient.temperature is not controlled or
where high-accurB;cy absolute measurements are being
made.
I 4-11-1

Buffer Gain
At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor Is stored, and subtracted
from the input voltage while adding to the reference voltage
during the next cycle. The result of this is that. the noise
voltage is effectively somewhat greater than the input noise
voltage of the buffer itself during Integration. By introducing
some voltage gain Into the buffer; the effect of the auto-zero
noise (referred to thE! input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase In buffer gain
merely increases the total offset to be handied by the autozero loop, and reduces the available- buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for dOing this with the
ICL8068/1CL7ic03 is shown in Figure 6.
to-SDK

TO ICL7tCD3

Figure 6: Adding Buffer Gain to ICL8D68

ICL8052 vs ICL8068
The ICL8052 offers significantly lower input leakage
currents than the ICL8068, and may be found preferable in
systems with high input impedances. However, the ICL8068
has substantially lower noise voltage, and is the device of
choice. for systems where noise is a limiting factor,
particularly in low sig~al level conditions.
Max Clock Frequency
The maximum conversion rate of most dual-slope AID
converters is limited by the frequency response of the'
comparator. The comparator in this circuit is no exception,
even though it is entirely NPN, with an open-loop gainbandwidth product of 300M Hz. The comparator output
follows the integrator ramp with a 3J.1s delay, and at a.clock
frequency of 160kHz (6J.1s period) half of the first reference
integrate clock period is lost in delay. This means that the
meter reading will change from Oto 1 witha50J.lVinput, 1 t02
with 150J.l V, 210'3 at 250J.l V, etc. This transition at mid~point is
considered desirable by most users. However,' if the clock
frequency is increased appreciably above 160kHz, the
instrument will flash "1" on noise peaks even when the input
is shorted.
For many dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non-linearity and noise do not
increase substantially with frequency, clock rates of up to
-1MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be a
constant and can be subtracted out digitally..
The minimum clock frequency is established by leakage on
the auto-ze~o and reference caps. With most devices,
measurement cycles as long as 10 seconds give no
measurable leakage error.

8052/71 C03 8068/71 C03
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 33-1/3kHz, etc. should be selected. For 50Hz
rejection, oscillator frequencies of 250kHz,166-2/3kHz,
125kHz, 100kHz, etc. would be suitable. Note that 100kHz
(2,5 readings/second) will reject both 50 and 60Hz.
The clock used should be free from significant phase or
frequency jitter. A simple two-gate oscillator and one based
on a CMOS 7555 timer are shown in the Applications section.
The multiplexed output means that if the display takes significant current from the logic supply, the clock should have
good PSRR.

APPLICATIONS

II
~

Specific Circuits Using the 8068/71C03 8052/71C03
Figure 7 shows the complete circuit for a ±4-1/2 digit
(±200,OtnV full scale) AID with LED readout using the
internal reference of the 8068/52, If an external reference is
used, the reference supply (pin 7) should be connected to
ground and the 300pF reference cap deleted. The circuit also
shows a typical R-C input filter. Depending on the
application, the time-constant of this filter can be made
faster, slower, or the filter dei'eted,completely. The 1/2 digit
LED ,is driven from the 7 segment decoder, with a zero
reading blanked by connecting a 05 signal to RBI input of
the decoder.
A voltage translation network is connected between the
comparator output of the 8068/52 and the auto-zero input of
the 71C03, The purpose of this network is to assure that,
(juring auto-zero, the output of the comparator is at or near
the threshold of the 71 C03 logic (+2.5V) while the auto-zero
capacitor is being charged to VREF (+1 OO,OmV for a: 200.0mV
instrument). Otherwise, even with zero volts in, some
reference integrate period would be required to drive the
comparator output to the threshold level. This would show
up as an equivalent offset error, Once the divider network
has been selected, the unit-to-unit variation should
contribute less than a tenth of a count error. A second feature

is the back-to-back diodes, used to lower the noise. In the
normal operating mode they offer a high impedance and
long integrating time constant to any noise pulses charging
the, ~uto-zero cap. At stiJ,rtup or recovery from an overload,
their impedance is low to large signals so that the cap can be
chargedup in one auto-zero cycle. The buffer gain does not
have to be set precisely at 10 since the gain is used in both the
integrate and deintegrate phase, For scale factors other than
200.00mV the gain of the buffer should be changed,to give a
±2V buffer output. For 2,OOOOV full scale this means unity
gain and for 20,OOOmV (1j.tV resolution) a gain of 100 is
necessary,' Not all 8068As can operate properly at a gain of
100 since their offset should be less than 10mV in order to
accommodate the auto-zero circuitry, However, for devices
selected with less than 10mVoffset, the noise performance is
. reasonable with apprOXimately 1,51.1V near full scale, On all
scales less than 200.00mV, the voltage translation network
should be made adjustable as an offset trim.
The auto-zero cap should be 11.1F for all scales and the
reference capacitor 'should be 11.1F times the gain of the'
buffer amplifier. At this v,alue if ttie input leakages of the
8052/8068 are equal, the droop effects will cancel giving zero
offset. This is especially important at high temperature.
Some typical component values are shown in the table
below. For 3-112 digit conversion use 12kHz clock,
V++ = +15V, V+ = 5V, V- = -15V, Clock Freq = 120kHz (4-1/2 digiti
ICLB052/B06B with
Full scale VIN
Buffer Gain (RB~~fB2)

UNITS
ICL71C03A
200
2000
mV
laO'
10
1
100
100
100
kD
RINT
0,22
0,22
0.22
CINT
IlF
1,0
1,0
·1,0
CAZ
IlF
10
10
1.0
CREF
IlF
10
100
1000
mV
VREF
Resolution (4-1/2 digit)
1
10
100
/lV
'Note comment on offset limitations above, Buffer gain' does not
improve ICLS052 noise performance adequately:
20

r-------~~----~r_------~------~r_--~+5

~~~~~150!!~
" II '-I 1-' I-I ~,~ ~ ~~~

15011
4.7k

-,- ,

I-I

I-I
_

I-I

_

_

1-'
_

NOTE: FOR
3-1/2 DIGIT
TIE PIN 2LOW

.A'A'

~

4-1/2 DIG/3-1/2

~j ~~~;~~D

DIG

BUSY ~
LSD D1 n~'7l7fJl-+++
1+------------------------------------'

-4. POLARITY

~ REFERENCE

10~ :~~: ~:: ~

26~

1i~~~~~~~~~~~~~~~~~~~~~~§~U

~: I~ ~ ,II
D2

M'SB

B4 ~ ,

rt.

8052-806~NT. OUT ~14
~rf

'15V- 1 v300pF
2 COMP OUT
II
3 REF CAP
10k
II ~ REF BYPASS
--~ GND
~10PF -- 6 REF OUT
17 REF SUPPLY

'L

1

120kHz = 3
READINGSISEC

,'"

1,OpFI=

:~ i~===~==~-,

LSB
~ ANALOG INPUT
MSD D5 U1M9----'
o-----.1P'---~H-i:k1.12 ~C·~LJOACLOKGINGNO
STROBE ~
36K<
A-Z IN 1J1IZ71---------++--h_~r·~....,1~
~ UNDERRANGE
A-Z OUT FW
CLOCK
J.1 OVERRANGE ' DIGITAL GND ~
IN
,- rh
300~~

+

10kf
o F=¥

9 RBI

71COr3_ _ _-..

+5V- '"1 v+

~~~~~L

~: r-

47k

~~gg:~~~ikHZ

0------,

~>,:.y- =
I

-":1'.'1'.',

"

1k '

_,

'0...

*For finer resolution on scale factor adjust, use a 10 turn pot or a small pol .in series with a fixed resistor.

Figure 7: S052A IS068A)/71C03A 4-1/2 Digi) A-D Converter
4-112

T

BUF IN 13

CINT

'

tiNT IN 12

-INT IN 11
100k~
- BUF IN 10
RIN~~
BUF OUT ~ ,,~
v++ ~
90k RB,

+.l..

1~V

10k_
RB2-

8052/71 C03 8068/71 C03
_ A suitable circuit for driving a plasma-type display is shown
in Fig. B. The -high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving 'BI' are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted if not needed. The 2K & 3K resistors set the
current levels in the display. A similar arrangement can be
used with 'Nixie'@ tubes.

Other Circuits for Display Applications
The popular"lCD displays can be interfaced to the OIP of the'
ICl71 C03 with suitable display drivers, such as the
ICM7211A as shown in Figure 10. A standard CMOS 4000
series LCD driver circuit is used for displaying the 1/2.'digit,
the polarity, and an 'overange' flag. A similar circuit 9an be
used with the ICM7212A lED driver and the ICM7235A
vacuum fluorescent driver with appropriate' arrangements
made for the 'extra' outputs. Of course, another full driver
circuit could be ganged to the one shown if required. This
would be useful if additional annunciators were needed.

@ Nixie is a registered trademark of Burroughs Corporation.

I

POL

I ,-, 1-' ,-, ,-,

T , '-"

,

C' ,~

9

The Figure shows the complete circuit for a 4-1/2 digit
(±2.000V) AID again using the internal reference of the

ov

B052A/B06BA.

A

Figure 11 shows a more complicated circuit for driving LCD
displays. Here the data is latched into the ICM7211 by the
Strobe signal and 'Overange' is indicated by blanking the 4
digits. A clock oscillator circuit using the ICM7555 CMOS
timer is shown. Some other suitable clock circuits are
suggested in Figs, 12 & 13. The 2-gate circuit should use
CMOS gates to maintain good power supply rejection.

GATES
ARE
7409
POL 05
8052AI
8068A

B3
71C03A

A problem sometimes encountered with the B052/6BI71C03
AID is that'of gross over-voltage applied to the input. Voltage
in excess of ±2.000 volts may cause the integrator output to
saturate. When this occurs, the integrator can no longer
source (or sink) the current required to hold the summing
junction (Pin 11) at the voltage st.ored on the auto zero
capacitor. As a result, the voltage across the integrator
capacitor decreases suffiCiently to give a false voltage
reading. This problem can also show up as large-signal
instability on overange conditions. A simple solution to this
problem is to use junction FET transistors across the
integrator capacitor to source (or sink) current into the
summing junction and prevent the integrator amplifier from
saturating, as shown in Figure 14.

B1
+5

ov

Figure 8: ICL8052-8068171 C03A Plasma Display Circuit
ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of B06B or B052/71C03A circuits, especially in high
sensitivity circuits. It is most important that return currents
from digital loads are not fed into the analog _ground line.
Both of the above circuits have considerable current flowing _
in the digital ground returns from drivers, etc. A
recommended connection sequence for the ground lines is
shown in Figure 9.

cl'tr

-

V
IN

--vvv----1
liP
FILTER
CAP

-

ICL71C03
PIN11
ANGND

1

CAZ

REf
VdLTAGE
EXTERNAL
REFERENCE
(IF USED)

BUF
-IN

+15V

VREF

ICL8052/68
PIN 5
AN GND

(IF
USED)

1 1

1>-

8068 PIN 2
COMP

Li

DIGITAL
LOGIC

1{
DIG GND
ICL71C03
PIN 15

-15V

I

BOARD
EDGEI

I

I

y-yy-~t)
~

T

DEVICE PIN

TTl

+5V SUPPLY BYPASS CAPACITOR(S)

Figure 9: Grounding Sequence

4-113

-.

SUPPLY
RETURN

II
~

D~DIL

S052/71C03 S06S/71C03

-

4·1/2 DIGIT LCD DISPLAY
+5Y

) II)

I

I

11161514125341
CD4054A

-':~b'
0 LI
n Lt
L'
11_1 Lt

28 SEGMENTS Dl·04

-BACKPLANE

78131110926
OY

t;

BUSY ~.

1 Y+

--[!

I

3-ii2

4·1/2 /

L-cr POL

D2~

R/H

D3~

33 D3

-41 COMPIN

D4iE

34 D4

B8p:

30 B3

~

29 B2

-15Y--!:! YICL71C03(A)

:L REF
RCl
l~F=r RC2

B4
B2

F;.

~

28 Bl

Bl~

.!!! INPUT

O.l~F=F.

NPUT

31 Dl . ICM7211A
32 D2

--!:i

100kll

:!1 ANALOG GND. STiffiiiE ~
AZIN

-IE UR

AZOUT

~OR

~

DIG.GND ilID-OY
CLOCK
IN
120kC = 3 READINGS/SEC

--

'

1.0~F

-15y-g:

30Okll

~

?

-15Y

OY

~

,

~
......

r

D51ill--

----@ CLOCK

36kll~

5 BP

D1J!!r

.....

,.

.

"

300.e.g~3 ICL8052(A ~
0.22~F
12

....g
~

8068(A) ~

'tl.

rIT

5kll
10kll

~

J!.r

100kll
V-

~+15Y

~

:

=10~F

'----'
tAtiALOG GND

Figure 10: Driving LCD Displays

4-114

2,3,4
6·26
'37·40 r--OPTI ONAL
CAPACITOR
ose 36
.. --+5V
22-10OpF

-or

27 BO
35 Y-

,

Y'l]
, +5Y

·S052/71C03 S06S/71C03

OIMlIlfiOI!..
')..--J=:::;:;--;-;:::;-::;:;';;::;-;:::128 SEGMENTS 01-04
1/2 C04030

02p2ID6--~~~::~c:)-t--------------l~~

ICL71 C03IA)

B4P2:2==~~~~~~~t==============j==~

B2~1

B1 2.

100kll

051.

INc>P_U_T+1--0_.1..:.~_F""'..-I__-flill1 ANALOG GNO liTiffiiiE 18t----j-----,

T300PF

OV
36kll
100kll
+lSV

300kll

";

ANALOG GNO

Figure 11: 4-1/2 Digit LCD DPM With Digit Blanking on Overrange.

~=.-,
RC NETWORK

.C

100pF

Figure 12

REF OUT '6 8
300P F=E

7

~ I~~~:I

1

,,
:5 +BUF IN 13
2[-----

REF.COMP,

TO 71C03A

Figure 14: Gross Overvoltage Protection Circuit

Figure.13: Clock Circuits
4-115

Il

D~OIL

S052/71C03 S06S/71C03
INTERFACING WITH UARTS
AND MICROPROCESSORS
Figure 15 s~ows a vel}' simple interface between freerunning 8068/8052/71C03A and a UART. The.five Strobe
pulses start the transmission of the five data words ..The digit
5 word isOOOQXXXX, digit4is 1000XXXX, digit3 is0100XXXX,
etc. Also the polarity is transmitted indirectly by using it to
- drive the' Even Parity Enable Pin (EPE). If EPE of the receiver
is held low, a parity flag at the receiver can be decoded as a
positive signal, no flag as negative. A complex arrangemenf '
is shown in Figure 16. Here the UART can instruct the AID to
begin a measurement sequence by a word on RRI: The Busy
signal resets the Data Ready Reset (DRH). Again Strobe
starts the transmit sequence. A quad 2 input multiplexer is
used to superimpose polarity, over-range; and undeHange
onto the 05 word since in this instance it is known that B2 =

.

~=~=~

For correct operation it is important that the UART clock 'be
fast enough that each word is transmitted before the next
STROBE pulse arrives. Parity is locked into the UART at load
time but does not change jn this connection during'an output
stream.

II

Circuits to interlace the 71C03(A) directly with three popular
microprocessors are shown in Figures 17, 18 and 19. The
main differences in the circuits are that IM6100 with its 12 bit
word capability can accept polarity, over-range, underrange, 4 bits of BCD and 5 digits simultaneously where the
8080/8048 and the MD6800 groups with 8 bit words need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 word - as in the UART circuits. In each case the
microprocessor can instruct -the NO when to begin a
measurement and when to hold this measurement.

APPLICATION NOTES
A016 "Selecting AID Converters," by David Fullagar
A017 "The Integrating AID Converters," by Lee Evans
A018 "Do's and Don'ts of Applying NO Converters," by
Peter Bradshaw and Skip Osgood
A019 "4-1/2 Digit Panel Meter Demonstrator/lnstrumentation Boards," by Micliael Dufort
A023 "Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort
A028 "Building an Auto-Ranging DMM Using the
8052A/7103A AID Converter Pair," by Larry Goff
ROOS- "Interfacing Data Converters & Microprocessors," by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976

SERIAL OUTPUT
TO RECEIVING UART

1

f
TRO

I
ORR,

RRI

DR
TRO

IM6402/3
TBRL

r- EPE
,-----tEPE

UART
IM640213

,

TBRL 1-'-----,

1

.

.

TBR
2, 3

4

5

6

7

8

J1Y 2Y1-'3Y

...

ENABLE

74C157 ~'
-'

lA 2A 3A

'NC

I I I

STROBE 1-_---1

0,

-

04 03 02 D1 B, 82 84 88

'-- 0,

Figure 15: Simple 71C03171C03A to UART Interface

71C03/A

o

U
V N
E 0
E
R R
STROBE
RUN/HOlli
BUSY

f---'-

12,

L--r+-r1-++-~~------~--~REAOI

B1B2 B4B8

• 71C03(A)

6

~

L E
R
R

"lOOp!

Figure 16: Complex 71C03/7103A to UART Interface

12

_

,

L

+5V

RUN/HOLO

~

P

'*
II

2B 3B

0

71C03lA
L-----1POL

mlB

IM6101

IM6100'

STROBE I-.,-----~SENSE 1
7

RUN/HOLOI-------~WRITE 1

Figure 17: IM6100 to 71 C03171 C03A Interface

4-116

'

+5v
10K

O~OI6

8052/71 C03 8068/71 C03
EN

1Y

EN

PAO

1Y

PA1

PA1
MC680X
OR
MCS650X

PA2
PA3

PA2
PA3

03
04

PA4
PAS
PA6
PA7

CA1

8080
8085,
ETC.

8255
(MODE 1)

MC6820

71C03

PAO

71C03
03
04

PA4
PAS
PA6
PA7

CA2

Figure 18: IGL71C03 to MC6800. MCS650X Interface

Figure 19: ICL71C03 to MCS-48, -80, 85 Interface

4-117

ICLS052/ICL7104.
,.
and .ICLS068/ICL71 04
161'141'12 Bit Binary AI'D
Converter Pai~ for JLProcessors
FEATURES

GENERAL DESCRIPTION

e- 16 bit binary three-state latched outputs plus

The ICl7104, combined with the ICl8052 or ICl8068, forms
a member of Intersil's high performance A/D_ converter
family. The 16-bit version, the ICl7104-16, performs the
analog switching and di.gital function for a 16-bit binary AID .
converter, with full three-state output,· UART handshake
capability, and other outputs for a wide. range 'of output
interfacing. The ICl7014-14 and ICl7104-12 are 14 and 12.bit versions. The analog section, as with all Intersil's
integrating converters, provides fully preCise Auto~Zero,
Auto-Polarity (including±O null indication), single reference
operation, very high input impedance, true input integration
over a constant period for maximum EMI rejection, fully
ratiometric operation, over-range indication, and a medium
quality built-in reference. The chip pair also offers optional
input buffer gain for high sensitivity applications, a built-in
clock oscillator, and output signals for providing an external
Auto-Zero capability in preconditioning circuitry, synchronizing external multiplexers, etc.

poiarity and overrange. Also 1;4 anci 12 bit versions.
• Ideally suited for interface
UARTs,
microprocessors, or other complex circuitry~
• Conversion on'demand or continuously.
.• Handshak~ byte-serial transmission synchronousl)f
or on demand.
• Guaranteed zero reading for zero volts input
• True polarity at zero count for precise null detection.
• Single reference voltage for true ratio metric .
operation.
• Onboard clock and reference.
• Auto-Zero; Auto-Polarity
Accuracy guaranteed to .1 count.
• All outputs TTL compatible.
• ±10V analog input range ._
• Status signal available for external sync, A/Z in
preamp, etc. .

*0

4.

PIN CONFIGURATIONS
v..

, v+:
BUFFER
(-IN)

COMP
OUT
REF
CAP

12 INTEGRATOR
(+IN)

REF
PASS

11 INTEGRATOR
(-IN)

BUFFER
OUT

REF
'OUT
REF
SUPPLY

DIG GND
STTS
_POL.
O.R.
BIT 16
BITIS
BIT 14
BIT 13
BIT 12
. BITll
BIT10
BIT9
BITS'
BIT7
BIT6
'BITS
BIT 4
BIT 3
BIT 2

. v-

DIGGND
STTS
POL
O.R.
BIT 14
BIT13
BIT 12
BITll
BIT 10
BIT9
N.C.

,

(OUTLINE DWGS DD,JD,PD)

N.C.
BITS
BIT 7
BIT 6
BIT S
BIT4
BIT3
BIT2

COMPIN
REFCAP 1
VREF
AZ

ANALOG GND
REFCAP 2
BUFIN
ANALOG liP

v+

CEii:D
12

SEN

14

·MODE
CLOCK· 2

17

f NOTE

Riii

CLOCKr.l~~~~~

18

LiiEN

-r BIT 1

""l....;.;...--",_ _

(OUTLINE DWGS DL,JL,Pl)

ORDERING INFORMATION
Part
8052
8052
8052A
8052A
8068
80SBA

Tamp. Range
O'C
O'C
O'C
O'C
O'C

to
to
to
to
to

70'C
70·C.
70'C
70'C
70'C

O°C to 70·C.

Package
14·Pln
14·Pln
14·Pln
14·Pln
14·Pln
14·Pln

Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
CERDIP
CERDIP

Order Number

Part

ICL8052CPD
ICL8052CDD
ICL8052ACPD
ICLS052ACDD
ICL8068CJD
ICL806SACJD

710412·81t
710412·81t
710412·81t
710414·81t
710414·81t
710414·81t
710416·81t
710416·81t
710416·81t

4-118

Package

Temp. Range
O'C to
O'C to
O'C to
O'C to
O'Cto
O'C to
O'C to
O.·C to
O'C to

70'C
70'C
70'C
70'C
70'C
70~C

70'C
70'C
70'C

4Q.Pln
4Q.Pln
40·Pln
40·Pln
4Q·Pln
4Q·Pln
40·Pln
40·Pln
40·Pln

CERDIP
Plastic DIP
Ceramic DIP
CERDIP
Plastic DIP
Ceramic DIP
CERDIP
Plastic DIP
Ceramic DIP

Order Number
ICL7104·12CJL
ICL7104·12CPL
ICL7104-12CDL
ICL7104·14CJL
ICL7104·14CPL
ICL7104·14CDL
ICL7104·16CJL
ICL7104-16CPL
ICL710'll.16CDL

8052/7104 8068/7104
ABSOLUTE MAXIMUM/RATINGS
Power Dissipation 1 •••••••••••••••.•••••••••..•• 500mW
Storage Temperature .................. -65°Cto+150°C

8052,8068
Supply Voltage ................................... ±18V
Differential Input Voltage(8068) ................... ±30V
(8052) .................... ±6V
Input Voltage 2 ................................... ±15V
Output Short Circuit Duration,
All Outputs3 ................••.....•..•••.. Indefinite
Operating Temperature ..................... 0°Cto+70°C
Lead Temperature (Soldering, 10 Sec,) ......' ...... 300°C

7104
V+ Supply (GND to V+) ............................ 12V
V++ to V- .......................................... 32V
Positive Supply Voltage (GND to V++) .............. 17V
Negative Supply Voltage (GND to V-) ............... ,17V
Analog Input Voltage (Pin 32-39)4 .............. V+ to VDigital Input Voltage ........................... V++0.3V
(Pins'2-3Q)5................................ GND -D.3V

Notes:
1: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambienttemperature below+700 C.
For higher temperatures, derate 10mW/oC.
.
2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
3: Short circuit may be to ground or either supply. Rating applies to +70°C ambient temperature.
4: Input voltages may exceed the supply voltages provided the input current is limited 'to ±100JoLA.
5: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latch up. Forthis reason
it is recommended that no inputs from sources not on the same power supply be applied to the ICL7104 before its power supply is
established.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress rating only and functional operation of

the devices at these or any other conditions above those indicated in

th~

operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

7104 ELECTRICAL CHARACTERISTICS (V+ = +5V, V++ = +15V, V- = -15V, Ta = 25°C)
CHARACTERISTICS

CONDITIONS

MIN

UNITS

liN
hN

Vin = +5V to OV
Vin - OV to +5V

+2
10

TYP
+7'
±0.001

MAX

CLOCK 1
COMP IN INote 11

+30
+10

Jl.A
Jl.A

Inputs
with Pulldown

MODE

liH
hL

Vin - +5V
Vin - OV

+1
10

+5
iO.Ol

+30
tl0

Jl.A
Jl.A

Inputs
with
Pullups

SEN, RIR
LBEN, MBEN,
HBEN, CElLO

liH
IlL

Vin - +5V
Vin - OV

-10
30

±0.01
5

+10
1

·Jl.A
Jl.A

Clock Input
. Comparator liP'

SYMBOL

}

INote 21

Input High Voltage

All Digital Inputs

V,H

Input Low Voltage

All Digital Inputs

V,L

Digital
Outputs
Three-Stated
On

LB EN
MB EN 116 only)
HB EN
CElLO

VOL
VOH
VOH

10L - 1.6 mA
10H - 10Jl.A
10H - -240Jl.A

INote 3)

2.0

-

V

1.5

1.0

V

.4

2.4

.27
4.5
3.5

V
V
V

-10

±.001

+10

Jl.A

-

.3
3.3.
0.5
4.5
.27
3.5

.4

V
V
V
V
V
V

2.5

-

BIT n, POL, OR
Digital
Outputs
Three-Stated Off

BIT n, POL, OR

10L

0:0 Vout:o V+

Non-Three-State
Digital
Output

STTS

VOL
VOH
VOL
VOH
VOL
VOH

10L = 3.2 mA
10H - 400Jl.A
10L - 320Jl.A
320Jl.A
10H
10L - 1.6 mA
10H - 320Jl.A

CLOCK 2
CLOCK'S 1-12, -14 ONLYI
Switch 1
Switches 2,3
Switches 4,5,6,7,8,9
Switch Leakage

Switch

Supply
Currents

+5V Supply Current
All outputs high impedance
+15V Supply Current
15V Supply Current

1++
1-

Freq. - 200 kHz
Freq. 200 kHz

Logic Supply
Positive Supply
Negative Supply

V+
V++
V

Note 5

Note
Note
Note
Note
Note

1:
2:
3:
4:
5:

1+

Freq.

DC

200

400

200

600

.3
25

1.0
200
+11.0
+16.0
-10.0

= 200 kHz

4.0
+10.0
16.0

ThiS spec applies when not In Auto-Zero phase.
Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode.
Apply only when these pins are outputs, i.e., the mode pin is high or the 7104 is in handshake mode.
Clock circuit shown in Figs. 10 and 11.
V+ must not be more positive than V++.

4-119

.4

20k
10k

ros(on)

1010ffi

-

25k
4k
2k
15

roS(en)

Clock Freq. INote 41

Supply Voltage

2.4

-

rOS(on)

Clock

R'~l.nge

2.4

11
11
11
pA
kHz
r

Jl.A
mA
Jl.A
V
V
V

8052/7104 8068/7104
8068 ELECTRICAL CHARACTERISTICS
SYMBOL
Vos

liN
CMRR

Av
SR
GBW
Isc

Input Offset Voltage
Input Current (either input) (Note 1)
Common-Mode Rejection Ratio
Non-Linear Comporient of CommonMode Rejection Ratio (Note 2)
Large Signal Voltage Gain
Slew Rate
Unity Gain Bandwidth
Output Short-Circuit Current

I Negative

Vo
Ro
TC
Vsupp
Isupp.

8068
CONDITIONS I MIN I TYP I MAX
EACH OPERATIONAL AMPLIFIER
20
65
VCM = OV
VCM - OV
175
250
VCM - +1OV
70
90

CHARACTERISTICS

I Small-signal Voltage Gain
I Positive Output Voltage Swing

AVOL
+Vo
Vo

Output Voltage Swing

(Vsupp = ±15V unless otherwise specified)

VCM = ±2V
RL - 50kD.

I
I
I

Output Voltage
Output Resistance
Temperature Coefficient
Supply Voltage Range
Supply Current Total

I

MIN

I

8068A
TYP

I
I

20
80
90

70

110

MAX

UNITS

65
150

mV
pA
dB

110
20,000

20,000

6
2
5
COMPARATOR AMPLIFIER
RL - 30kD J
I 4000
I +12 I +13
I 2.0 I 2.6
VOLTAGE REFERENCE
1.5
1.75
5
50
±10

6
2
5

10

I

I
I

I

I

+12
2.0

2.0

1.60

±16
14

±10

I
I
I

VIV
V/Jis
MHz
mA

10

I
I

+13
2.6
1.75
5
40

1.90

8

VIV
V
V

±16
14

V
ohms
ppm/oC
V
mA

MAX

UNITS

50
10

mV
pA
dB

I

8052 ELECTRICAL CHARACTERISTICS
SYMBOL
Vos

liN
CMRR

Av
SR
GBW
Isc

Note 1:

Note 2:

Input Offset Voltage
Input Current (either input) (Note 1)
Common-Mode Rejection Ratio
Non-Linear Component of CommonMode Rejection Ratio (Note 2)
Large-Signal Voltage Gain
Slew Rate
Unity Gain Bandwidth
Output Short-Circuit Current

I Negative Output Voltage

Vo
Ro
TC
Vsupp
Isupp

8052
CONDITIONS I MIN I TYP I MAX
EACH OPERATIONAL AMPLIFIER
20
50
VCM =OV
5
50
VCM - OV
70
90
VCM = ±10V

CHARACTERISTICS

I Small-signal Voltage Gain
I Positive Output Voltage Swing

AVOL
+Vo
-yo

Output Voltage
Output Resistance
Temperature Coefficient
Supply Voltage Range
Supply Current Total

Swing

(Vsupp = ±15V unless otherwise specified)

VCM =±2V
RC - 10,kD

I
I
I

I

MIN

I

I

20
2
90

\0

110

110

,

20,000

.6
1
20
COMPARATOR AMPLIFIER
RL - 30kD
I 4000
I
~ +12 I +13
I -2.0 I -2.6
VOLTAGE REFERENCE
1.5
1.75
5
50
±10
6

8052A
TYP

20,000
6
1·
20

100

I .

I

I
I

I
I

I
+12
-2.0

2.0

1.60

±16
12

±10

I
I

100

I

VIV
V
V

+13
2.6
1.75
5
40
6

VIV
V/p.s
MHz
mA

1.90

±16
12

V
ohms
ppmfOC
V
mA

The input bias currents are junction le~kage currents which approximately double for every 10' C increase inthe junction temperature, TJ. Due to limited production test time, the input bias currents aremeasured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA +OjA Pd
where OjA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
This is the onlycomponent that causes error in dual-slope converter.

4-120

8052/7104 8068/7104

O~OlL

SYSTEM ELECTRICAL CHARACTERISTICS:' 806817104
(V++

= +15V, V+ = +5V, V- = -15V

CONDITIONS

CHARACTERISTICS

Vin = O.OV
Full Scale

Zero Input Reading
Ratiometric Reading

Clock Frequency

Linearity over ± Full Scale
(errqr of reading from
best straight Iinel

8068A17104-12
MIN
TYP
MAX

8068A17104-16
MIN
TYP
MAX

-.000

±.OOO

+.000

-0.0000

±O.OOOO

+0.0000

-0.0000

7FF

800

801

1FFF

2000

2001

7FFF

0.2

1

0.5

1

-4V'; Vin ,; +4V

Differential Linearity
-4V ::; Vin :::; +4V
(difference between worse
case step of adjacent counts
and ideal step

Rollover error (Difference in
reading for equal positive &
negative voltage near full

8068A17104-14
MIN
TYP
MAX

±O.OOOO +0.0000

= 4.000V

Vin = VAel.
Full Scale = 4.000V

(1)

= 200KHz

.01

.01

0.2

-Vin == +Vin "" 4V

8000

8001

0.5

1

.01

UNITS
Hexadecimal
Reading
Hexadecimal
Reading
LSB

LSB

1

1

0.5

100

165

100

165

5

0.5

2

0.5

2

"V/'C

5

2

5

2

5

ppm/'C

1

0.5

200

265

1

2

LSB

scale)

Noise Ip·P value not
exceeded 95% of time)

Vin - OV
Full scale

Leakage Current at Input 121

Vin

Zero Reading Drift

Vin - OV
O'C'; TA'; 70'C

= 4.000V

3

= OV

Scale Factor Temperature 131 Vin - +4V
0,;TA';50'C'
Coefficient
lext. ref. 0 ppm/'CI

2

2

"V
pA

SYSTEM ELECTRICAL CHARACTERISTICS: 805217104
(V++

= +15V,

V+

= +5V, V- = -15V Clock Frequency = 200,KHz

CHARACTERISTICS
Zero Input Reading

,

Ratiometric Reading (3)

Vin = O.OV
Full Scale. = 4.000V

-.000

±.OOO

t· OOO

-0.0000

7FF

800

801

1FFF

0.2·

1

Vin

= VRef.

Noise (P-P value not
exceeded 95% of time)

-4V:$ Vin ::; +4V

-Vin '= +Vin "" 4V

Vin

Zero Reading Drift

2000

2001

0.5

1

-0.0000
7FFF

±O.OOOO +0.0000
8000

8001

0.5

1

.01

.01

0.2

\

1

0.5

.01

1

0.5

UNITS
Hexadecimal
Reading
Hexadecimal
Reading
LSB.·

LSB

1

LSB

= OV

Full scale
Leakage Current at Input 121

±O.OOOO +0.0000

8052A17104-16
MIN
TYP
MAX

= 4.000V

Differential Linearity
-4V::; Vin ::; +4V
(difference between worse
case step of adjacent counts
and ideal stepl
Rollover error (Oifferetlce in
reading for equal positive &
negative voltage near full
scale)

8052A17104-14
TYP
MAX
MIN

MIN

Full Scale
Linearity, over ± Full Scale
(error of reading from
best straight Iinel

805217104-12
TYP
MAX

CONDITIONS

= 4.000V

= OV
Vin = OV
Vin

20
50

"V
30

30

30

80

20

30

20

30

pA

1

5

0.5

2

0.5

2

p.V/'C

3

15

2

5

2

5

ppm/'C

OOSTA:570°C
Scale Factor Temperature
Coefficient

. 0,;TA';70'C
Vin' - +4V

lext. ref. 0 ppm!' CI

Note 1:
Note 2:

Note 3:

Tested with low dielectric absorption integrating capacitor.
The input bias currents are junction leakage currents which approximately double for every 10'C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. T J;" TA +OjA Pd
where OjA is the thermal resistance.irom junction to ambient. A heat sink can be used to reduce temperature rise.
The temperature range can be extended to 70' C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the
high temperature leakage of the 8068. See note 2 above.

4·121.

D~DIl.

8052/7104 8068/7104

CONVERT

OR
CONVERT
CONTROL

POL

BOS2A1
B068A

8052A1

7104

80BBA

U88

7104

;.,.
LBB

B052A1
8088A

7104
-18
CONTROL

CONTROL
CONVERT

,.--..

!

~:. or CHIP SELECT 2

OR

'---4---4--'--_

POL

80S2A1
8088A

71C!4

USB

Full 18 Bit Three State 'Output
LBBi----/

CONTROL

Various C~mbinations of Byte Disables

AC CHARACTERISTICS (V++= +15V, v+ = -f-SV, V- = -1SV)
Ice.

, CElLO
AS INPUT

FiiffiiI
AS INPUT

MBEN
AS INPUT

ilIEIiI
AS INPUT'
HIGH BYTE
DATA

~::!~t~ BYTE
LOW BYTE
ENABLE

-----------------------------:----------------------< ~:~~ }----... -'---+-~~-..:.:;:=~.1
,

,

'

--------------~--------------~------- - - - - - - = HIGH IMPEDANCE
TABLE l' Direct Mode Timing Requirements
SYMBOL
tbe.,
tdab

DESCRIPTION
XBEN Min, Pulse Width

'MIN

TYP

Data Access Time
from XBEN

UNITS

200 '

Data Hold Time
from XBEN

200

teoa

CElLO Min, Pulse Width

500

~ae

Data Access Time
from CElLO

200

~he

Data Hold Time
from CElLO

tewh

CLOCK 1 High Time

t dhb

MAX

500

209
1250

4-122

1000

ns

O~OIb

8052/7104 8068/7104
TABLE 2: Handshake Timing Requirements

NAME
. tmw
tsm
tme
tmb
teel
teeh
tebl
tcbh
tedh
tedl
tss
tebz
teez
tewh

DESCRIPTION
MODE Pulse (minimum)
MODE pin set-up time
MODE pin high to low Z CElLO high delay
MODE pin high to XBEN low Z (high) delay
CLOCK 1 high to CElLO low delay
CLOCK 1 high to CElLO high delay
CLOCK 1 high to XBEN low delay
CLOCK 1 high to XBEN high delay
CLOCK 1 high to data enabled delay
CLOCK 1 low to data disabled delay
Send ENable set-up time
CLOCK 1 high to XBEN disabled delay
CLOCK 1 high to CElLO disabled delay

MIN

TYP

CLOCK 1 High Time

1250

20
-150
200
200
700
600
900
700
1100
1100
-350
2000
2000
1000

MAX

UNITS

ns

\
..

H.

CLOCK 1 (PIN 25)

L
EITHER:

,~~--~~~--~--~~~~-----DO-N-T--CA-R-E------~~;~x~--~.r

·MODE Pilot
OR:

L_-:_:~:-~~"

INTERNAL LATCH
PULSE IF MODE "HI".

IGNORED

______

~_-II- ___________

-------------

.

UART
INTERNAL MODE

NoRM----~--~~~~

SEN
(EXTERNAL SIGNAL)

O/R,POL01-14

BITS 1·5

----~~---.,~.----+-----~----~I~;.~·--.---4r~{C:::!D~A~TA~VA~L~ID~,~S~TA~B~~t:::>~--4---~-----HANDSHAKE MODE TRIGGERED BY

-----OR---

THREE-STATE . _
-16 HAS EXTRA (MBEN) PHASE

-14, -12 BIT VERSION SHOWN

Timing Relationships In Handshake Mode

.

'

,

4-123

THREE-STATE W PULLUP .....

O~OIL

8052/7104 '8068/7104
TABLE 3:, Pin Assignment and Function Description
PIN
1

2

GND.

3

STTS

4

POL

.5

OR

6·

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

7

8

9

,

SYMBOL
V(++)

10

11

12

·13

14
15
16
17
18
19
20
21
22

23

16
14
12
15
13
11
14
12
10

BIT 13
BIT 11
BIT9
BIT 12
BIT 10
nc
BIT 11
BIT9
nc
BIT 10
nc
nc
BIT9
nc
ric
·BIT8
BIT 7·
BIT6

:-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14 .
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14·
-12

BIT 11
BIT4
BIT 3
.BIT2
Bin
LBEN

PIN

25
26
27

SYMBOL
CLOCK1
CLOCK2
MODE

28

R/H

(Most .significant bill

--.-29

SEN
\

Data Bits, Three-state
outputs. See Table 4 for
format of ENable~ and'
bytes.
HIGH = true

,

30

CElLO

31

V(+)

32
33

AN. IN
BUPIN

34
35·

REFCAP2
AN.GND.

3.6
37
38
39
40

A-Z
VREF
REFCAP1
CaMP-IN
V(-)

DESCRIPTION
Clock input. External clock or oscillator.
Clock output. Crystal or RC osCillator.
Input LO;Direct output mode where
CE/i]), RE!B'i, iii1SB\j, and LBEN act as
inputs directly controlling byte outputs.
If pulsed HI causes immediate entry into
handshake mode (see Figure 9),
If HI, enables CElLD, HBEN, MBEN, and
LBEN as outputs. Handshake mode
will be entered and data output as in
~igures 7 & 8 at conversion completion.
Run/Hold; Input HI-conversions continuously performed every 217 (-16)
. 215 (-14) or 213 (-12) clock pulses.
Input La-conversion in progress
completed, converter will stop in
Auto-Zero 7 counts before input integrate:
Send-ENable: Input controls timing'
of byte transmission in handshake
mode. HI' indicates 'send'.
Chip-Enable/LoaD. With MODE (pin 27)
. La, CE/LD serves as a master output
.emible; when HI, the bit outputs and
POL, OR are disabled. With MODE HI,
pin serves as a CoaD.strobe (-ve
going) used in handshake mode. See
Figures 7 & 8.
Positi\le Logic Supply Voltage.
.
'Nominally +5V.

ANalog INput. High side.
BUFfer INput to analog chip
(lCL8052 or ICL8068)
REFerence CAPacitor (negative side)
ANalog GrouND:' Input low side and
reference low side.
Auto-Zero node.
Voltage REFerence input (positive side)
REFerence CAPacitor (positive side)
COMParator INput from 8052/8068
Negative Supply Voltage. Nominally-15V.

--..:...----.:...

-16

HBEN

-14
-12

CLOCK3

DESCRIPTION
positive Supply· Voltage
Nominally +15V
. Digital Ground .OV, ground
return
STaTu~ output .HI during
,Integrate and Deintegrate
until data is latched .LO
when analog section is in
Auto-Zero configuration.
POLarity. Three-state output. HI for positive input.
OverRange. Thr!!e-state
output.

Least significant bit
[ow Byte ENable. If 'not in
handshake mode (see pin 27)
when La (with CE/LD, pin
30) aptivates low-order
byte outputs, BITS 1-8
When in handshake mode
(see pin 27), serves as a
loIN-byte flag output. See
. Figures 8, 9 and 10.

MBEN

HBEN

24

OPTION

.' -16

-14
-12

CElLO

LBEN

Mid Byte ENable. Activates
BITS 9-16, see LBEN (pin 22) .
High Byte ENable. Activates
BITS 9-14, POL, OR, see
LBEN (pin 22)

7104-16 POL O/R 816 815 814 813 812 811 BtD 89

88

87

86

85

84

83

82

81

7104·14
7104-12

88
SB

87. 86
87 86

85

as

84
84

83
83

82
82

81
81

POL C/R 814 813 B12 811 810 89
POL O/R
812 811 B10 89

TABLE 4: Three-State Byte Formats and ENable Pins.

High Byte ENable.
Activates POL, OR, see
LBEN (pin 22),
RC oscillator pin. Can be
used 'as clock output.

4-124

n~nlL

8052/7104 8068/7104

Fig. 1 shows the functional block diagram of the operating system. For a detailed explanation, refer to fig. 2 below.
-15V

RINT

-aUF IN

aUF OUT

CINT

5 4 3 2 1

-INT IN

~·~~v~.~~Hv~.~~H~~.~·~~~~~9'~--1

I

r-........I....l...j,...;I"""-I...I....I............l...I....."""-I-I....I.....I...t21

'NB,6bil

I .version shown;

THREE STATE OUTPUTS

I

I
I

!:r:~~:~I~:!r
In pinout here.

7104

CONTROL LOGIC

MODE
R/H

L _____ _
REF
CAP
CAP
(1) CREF (2)

Figure 1: 8052A (8068A)17104 16/14/12 Bit AID Converter Functional Block Diagram

, DETAILED DESCRIPTION
Analog Section
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL71 04/8068 in the 3
different phases of operation. If the Run/Hold'pin is left open
or tied to Vt, the system will perform conversions at a rate

deterr(lined by the clock frequency: 131,072 for -16;32,368
for - 14; and 8092 for -12 clock periods per cycle (see Figure
conversion timing!.

D

0
ZERO
CROSSING
FF

'CL

POL

CL

Figure 2A: Phase I Aut9-Zero

1, Auto-Zero Phase I Fig. 2A
During Auto-Zero, the input of the buffer is shorted to
analog ground thru switch 2, and sWitch 1 closes a loop
around the integrator and comparator. The purpose of
4·125

the loop is to charge the Auto-Zero capacitor until the
integrator output no longer changes with time. Also,
switches 4 and 9 recharge the reference capacitor to VREF.

O~OIb

8052/7104 8068/7104
AN
liP

D

Q
ZERO
CROSSING
FF
CL

POL

CL

Figure 28: Phase II Integrate Input

2. Input Integrate Phase II Fig. 28
During input integrate the Auto-Zero loop is ope'ned and
the, analog input is connected to the buffer input thru
switch 3. (The reference capacitor is still being charged to
VREF'during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous state (Auto-Zero). Thus the

integrator output will not change but will remain
stationary during the entire Input Integrate cycle. If VIN is
not equal to zero,' an unbalanced condition exists
compared to the Auto-Zero phase, and the integrator will
generate a ramp whose slope is proportional to VIN. At the
end of this phase, the sign of theramp is latched into the
polarity F/F.

D

BU621

97-=

Q

ZERO
CROSSING
FF

'

CL

~VREF

-"="+
CREF

CL

POL

+ Deintegrate

Figure 2C: Phase III

Deintegrate Phase III Fig. 2C & D
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. Ifthe input signal was positive,
switches 7 and 8 are closed and a voltage which Is VREF more
negative than during Auto~Zero is impressed on the buffer
input. Negative inputs will cause +VREF to be applied to the
buffer input via switches 6 and 9., Thus, the reference
capacitor generates the equivalent of a (+) reference or a H
reference from the single 'reference voltage with negligible

error. The reference voltage returns the output of the
integrator to the zero-crossing point established in Phase I.
The time, or number of counts, required to do this is proportional to ttie input voltage. Since the Deintegrate phase can
be twice as long as the Input integrate phase, the input
voltage required to give a full scale reading = 2VREF.
Note: Once a zero crossing is detected, the system
automatically reverts to Auto-Zero phase for the leftover
Deintegrate time (unless Run/Hold is manipulated, see Runl
Hold Input in detailed description, digital section).

D

lX,
6

9

-

Q
ZERO
CROSSING
FF

7

CL

+

CAEF

POL

Figure 20: Phase III - Deintegrate

4·126

CL

O~OI!,.

8052/7104 8068/7104
POLARITY

ZERO CROSSING
DET~ECTED
OCCURS

I'.

INTEGRATOR
OUTPUT

I

INTERNAL CLOCK

il.r

1.J4

I

1/
~

;2

I

ZERO CROSSING
<",DETECTED
I

~ PHASE I--..I-INT
PHASE II • i.
~
DEINT PHASE I I I - - - l - A i . I ,
I
~ Jl,J"lIl..f"L, N1.IlIlr 'l..I111IUl.r

I

INTERNAL LATCH

'.

I

I
I

I ' . .

I

h

I
I

I

1

I

I

I

I

I

1.1

I"

I

I

I

I

I

STATUS OUTPUT I'

I

NUMB~R

.

OF COUNTS TO ZERO CROSSING!
PROPORTIONAL TO V,N

-16
-14
-12

Phase I
32768
8192
2048

COUNTS
Phase II
32768
8192
2048

.

"'-AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION

Phase III
65536
16384
4096

Figure 3: Conversion Timing

COMPONENT'VALUE SELECTION
For optimum performance of the analog section, care must
be taken in the selection of values forthe integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular' application.
Integrating Resistor
The integrating resistor is determined by the full scaie input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current sl:lOuld be small
compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not.
·affected. Values of 5 to 40 jJ.A give good results with a
nominal of 20 jJ.A. The e~act value may be chosen by
RINT =
'Note~

full scale voltage'
20jJ.A

If gain is used in the buffer amplifier then -

RINT =

(Buffer gain)' (full scale voltage)
20jJ.A

Integrating Capacitor
The product of integrating resistor and capacitor is selected
to give 9 volt swing for full scale inputs. This is a compromise
between possibly saturating the integrator (at +14 volts) due
to tolerance build-up between the resistor, capacitor and
clock anq the errors a lower voltage swing could induce due
to offsets referred to the output. of the comparator. In
general, the value of C'NT·is give by

Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
Note: When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero
capac,itor. As a rule of thumb, the referenCe capacitor should
be approximately the gain times the value of the auto-zero
capacitor. The dh31ectric absorption of the reference cap and
auto-zero cap are only important at power-on or when the
circuit is recovering from an overload. ·Thus, smaller or
cheaper caps cari be used here if accurate readings are not
required for the first few seconds of recovery.

Reference Voltage
The analog input required to g'enerate a full scale output is
V,N = 2 VREF.
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The
resolution of the ICL7104 at 16 bits is one part in 65536, or
15.26ppm. ,Thus, if the reference has a temperature
coefficient of 50ppm/oC (on board reference) a temperature
change of 1/3°C will introduce a one-bit absolute error. For
this reason, it is recommended that an external high quality
reference be used where the ambient :temperature is not
controlled or where high-accuracy absolute'measurements
are being made.

~32768 for -16

]
(819'2 for -14 X clock pe. riod) X (20jJ.A)
C
= (2048for-12
INT
Integrator output voltage swing
.

This ratiometric condition should read half scale (100 ... 000l
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.

A very important characteristic of the integrating capacitor is
that it have low dielectric absorption .to prevent roll-over or
ratio metric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
4-127

II

O~OIb

8052/7104 8068/7104
Buffer Gain

At the end of the auto-zero interval, the instantaneous noise
voltage on the auto~zero 'capacitor is stored, and subtracts
from the input voltage while adding to the reference voltage
during the next cycle. The result is that this noise voltage
effectively is somewhat greater than the input noise voltage
of the buffer itself during integration. By introducing some
voltage gain into the buffer, the effect of the auto-zero noise
(referred to the input) can be reduced to the level of the
inherent buffer noise. This generally occurs with a buffer
gain ot' between 3 and 10. Further increase. in buffer gain
merely increases the total offset to be handled by the autozero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for dOing this with the
ICL8068/1CL7104 is shown in Figure 4. With careful layout,
the circuit shown can achieve effective input noise voltages
on the order of 1-2"V, allowing full 16-bit use with full scale
inputs of as low as 150mV. Note that at this level, thermoelectric EMFs between PC boards, IC pins, etc., due to local
temperature changes can be very troublesome. For further.
discussion, see App. Note A030.

Figure 4: Adding Buffer Gain. to ICL8D68

Table 5: Typical Component Values

V++ = +15V V+ = 5V V- = -15V Clock Freq = 200 kHz
ICL8052/8068 with
ICL7104-16
200
800
Full scale VIN
4QOO
Buffer Gain
10
1
1
100
43
200
RINT
.33
.33
.33
CINT
1.0
1.0
1.0
CAZ
10
i.o
1.0
Cret
100
400
2000
VREF
Resolution
3.1
12
61

ICL7104-14
4000
100
10
1
47
180
0.1
0.1
. 1.0
1.0
1.0
10
2000
50
6:1
244

ICL8052 vs ICL8068
The ICL8052 offers significantly lower input leakage
currents than the ICL8068, and may be found preferable in
systems with high input impedances. However, the ICL8068
has substantially lower noise voltage, and for systems where
system noise is a limiting factor, particularly in low signal
level conditions, willgive better performance.

4·128

ICL7104-12
50
4000
1
10
27
200
.022
.022
.47
.47
4.7
4.7
25
200
12
980

UNITS
mV
kD
/iF
/iF
/iF
mV
/iV

8052/7104 8068/7104

O~OIL

DETAILED DESCRIPTION

Run/Hold Input

Digital Section

When the Run/Hold input is connected to V+ Qr left open (this
input has a pullup resistor to ensure a high level when the pin
,is left open), the circuit will continuously perform conversion
cycles, updating the output latches at the end of every
Deintegrate (Phase IIIl portion of the conversion cycle (See
Figure 3), (See under "Handshake Mode" for exception.! In
this mode of operation, the conversion cycle will be,
performed in 131,072 for 7104-16, 32768 for 7104-14 and
,8192 for 7104-2 clock periods, regardless of the resulting
value,
If Run/Hold goes low at any time duringDeintegrate (Phase
IIIl after, the zero' crossing has o~curred, the circuit will
immediately terminate Deintegrate and jump to Auto-Zero.
This feature can be ,used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Hold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Hold input
goes ~igh. The converter will ,begin' the Integrate (Phase III
portion of the next conversion (and the' STaTuS output will
go high) seven clock periods after the high level is detected at
RLm/Hold. See Figure 6 for details.
USing the Run/Hold input in this manner allows an easy
"convert on demand" interface to be used. The converter
may be held at idle in Auto-Zero with Run/Hold low. When
Run/Hold goes high the conversion is started, and when the
STaTuS output goes low the new data is va.!!.d (or transferred
to the UART - see Handshake Mode!. Run/Hold may now go
low terminating Deintegrate and ensuring a minimum AutoZero time before stopping to wait for the next conversion.
Alternately, Run/Hold can be used to minimize conversion
time by ensuring that it goes low during Deintegrate, after
zero crossing, and goes high after the hold point is reachecj.
The required activity on the Run/Hold input can be provided
bY,connecting it to the CLOCK3 (-12, -14), CLOCK2 (-16)
Output. fn this mode the conversion time is dependent on the
input value measured. Also refer to Intersil Application
Bulletin A030 for a discussion of the effects this will have on
Auto-Zero performance.

The digital section includes the clock oscillator circuit, a 16,
14 or 12 bit binary counter with output latches and TTLcompatible three-state output drivers, polarity, over-range
and control logic and UART handshake 'logic,' as shown in
the Block Diagram Figure 5 (16 bit version shown),
Throughout this description, logic levels will be referred to
as "low" or "high", The actual logic levels are defined under
"ICL7104 Electrical Characteristics", For minimum power
consumption, all inputs should swing from GND (Jow) to V+
(high!. Inputs driven from TTL gates should have 3-5kO
pulliJp resistors added for maximum noise immunity ..

MODE Input
The MODE input is used to control the output mode of the
converter, When the MODE pin is connected t6 GND or left
open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter is
in its "Direct" output mode, where the output data is directly
accessible under the, control of the chip and byte enable
inputs, When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the'data in
three bytE;ls for the 71'04-16 or two bytes for the 7104-14 and
7104-12, then returns to "direct" mode, When the MODE
input is left high, the converter will output data in the
handshake mode at the end of every conversion cycle, (See
se,ction entitled "Handshake Mode"for further details!.

0'

STaTuS Output
During a conversion cycle, the STaTuS output goes high at
the beginning of Input Integrate JPhase Ill, and goes low
one-?alf clock period after new data from the conversion has
been stored in the output latches, See Figure 3 for details of
this'timing, This signal may be used as a "data valid" flag
(data never changes while STaTuS is low) to drive interrupts,
or for m'onftoring the status ol.the converter.
'

CE/LD
B8

B7

B6

B5

B4

B3

B2

Bl

7104-14
7104-12

'-_-I-l-4 HilElii

I

I

I MBEN

I (-16 only)

I

I

LATCH

I.

, CLOCK
COMPOUT
TO AZ
'
ANALOG { INT
SECTION DEINT(+)
DEINT(-)

rH-A~ND~S:-:H~A-KJ.E1-l.UUI CE/LD

OSCILLATOR
AND CLOCK
, CIRCUITRY

2i..
STaTuS

21.

LOGIC

~

1

2

3

4-129

I

I
2L. ___ J

I,

_____ _

CLOCK CLOCK CLOCK

Figure 5: Digital Section

I

MODE

SEND

~

,

O~O[b

8052/7104 8068/7104
OPTION
MIN
MAX

INTEGRATOR
OUTPUT
INTERNAL CLOCK

-

"1..['

DEINT TERMINATED
.
AT ZERO CROSSING",

-12
1785
2041

-14
-16
7161 28665
8185 32761

I

~TION~J"..

I

I

I

I

I

~ ; : :!:

1-------7

COUNTS~

---

~....n.nnn.nn..~ ~ ~
I
n

.

I

I

I

INTERNAL LATCH _ _......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~......

I

"""""!r----

STaTuS OUTPUT
RUN/HOLD INPUT

.... pINHTASE I

STATIC IN

I HOLD STATE

I - - -_ _ _

I

--------""Lr-_-_-_-_-_--_-_-_"'"1_ _ _ _ _ _ _ _ _ _ _ _

L..
i _ _ _ _ _ _ _I_ _ _ _

-1

I

Figure 6: Run/Hold Operation

II
~

If the Run/Raid input goes low and stays low c(uring Autoe
Zero (Phase D, the converter will simply stop at the end of
Auto-Zero and wait for Run/Hold to go high. As above,
Integrate (Phase III begins seven clock periods after the high
level is detected.
.

input low will allow the outputs of that byte to become active
(three-stated on!. This allows a variety of parallel data accessing techniques to be' used. The timing requirements for these
outputs are shown under AC Characteristics and Table 1.

Direct Mode
When the MODE pin is left at a low level, the data outputs[bits
1 through 8 low order byte, see table 4 for format of middle
(-16) and high order bytes]are acce.ssible undercont.rol of the
byte and chip ENable terminals as inputs. These ENable
inputs are all active low, and are provided with pullup
resistors. to ensure an inactive high level when left open.
When the chip ENable input is low, taking a byte ENable

.It should be noted that these control inputs . are
asynchronous with respect to the converter clock - the data
may be accessed at any time. Thus it is possible to access the
data while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STaTuS output will prevent this.
Data is never updated while STaTuS is low. Also note the
potential bus conflict described under "Initial Clear Circuitry".

ZERO-CROSSING

INTE~~~~~~ ---~:----k---

For -16'MBEN sequence Inserted he,re.

INTERNAL
CLOCK
INTERNAL
LATCH _ _ _ _ _ _.....
STATUS
OUTPUT

---------~

INTERNAL
MODE~~~

__

-#~

___

~

CE/LOAD

HIGH BYTE
DATA

LOW BYTE
DATA ---------~-

Mn-----------------------------------

LOW BYTE

_~DONTCARE

----

~

THREE-STATE HIGH IMPEDANCE

Figure 7: Handshake With SEN Held Positive

4-130

-~-~ TI:IREE-STATE WITH PULLUP

8052/7104 8068/71'04
Handshake Mode
The handshake output mode is provided as an alternative
"means of interfacing the ICL7104 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and-byte ENable
inputs. This mode is specifically designed to allow a direct
interface betweeri the ICL7104 and industry-standard
UARTs (such as the Intersil CMOS UARTs, IM6402/3) with no
external logic required. When triggered into the handshake
mode,-the ICL7104 provides all the control and flag Signals
necessary to sequence the three (lCL7106-16) or two
(lCL7104-14, -12) bytes of data into the UART and initiate
their transmission in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the
number of lines to the central controlling processor.
" Entry into the handshake mode will occur if either of two
conditions are fulfilled; first, if new data is latched (j.e. a
conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from lowto high, when E;!ntry
will occur immediatE;!ly (if new data is being latchE;!d, E;!ntry is
delayed to the end ofthe latch cycle). WhilE;! in thE;! handshakE;!
mode, data "latching is inhibited, and the MODE pin is
ignored. (Note that conversion cyclE;!s will continue in the
normal manner). This allows VE;!rsatile initiation of handshake
operation without danger of false data generation; if thE;!
MODE pin is hE;!ld high, E;!VE;!ry conversion (othE;!r than thOSE;! "
compiE;!ted during handshakE;! operations) will start a new

handshake operation, while if the MODE pin is pulsed high,
handshake operations can be obtained "on demand."
When the converter enters the handshake mode, or when the
MODE input is high, the chip and byte ENable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle. The Send ENable pin (SEN) (pin
29) is used as an indication. of the ability of the external
device to receive data. The condition of the line is sensed
once every clock pulse, and if it is high, the'next !,orfirst) byte
is enabled on the next rising CLOCK 1 (pin 25) clock edge,
the corresponding byte ENable line goes low, and the Chip
ENablelLoaD line (pin 30) (CElLO) goes low for one full clock
pulse only, returning high.
On the next falling CLO~K 1 clock pulse edge, if SEN remains
high, or after it goes high again, the byte output lines will be
put in the high impedance state (or three-stated off). One half
pulse later, the byte ENable pin will be cleared high, arid
(unless finished) the CElLO and the next byte ENable pin will
go low. This will continue until all three (2 in the case of 12
and 14 bit devices) bytes have been sent. The bytes are
individually put into the "low, impedance state Le.: three'stated on during most of the time thattheir byte ENable pin is
(active) low. When receipt" of the last byte has been
acknowledged by a high SEN, the handshake mode will be
cleared, re-enabling data latching from conversi"ons, and
recognizing the condition of the MODE pin again. The byte
and chip ENable will be three-stated off, if MODE is low, but
held h"igh by their (weak) pullups:These timing relationships
are illustrated in Figure 7, 8, and 9, and Table 2.

INTERNAL
CLOCK"
INTERNAL
LATCH _ _ _ _....
STATUS - - - - - - ;
OUTPUT"

MOOE------~
INPUT
MODE _ _ _ _ _ _ _~
INTERNAL

'~e~eBtl---)

SEN INPUT
(UART
TBRE) ~
CEILD OUTPUT
(UARTTBRLI

..,....------r-_t.

HIGH BYTE
DATA - - - - - -

MIDDLE

~:;.!

"----~~-

_______ _

LOW BYTE
DATA - - - - - - -

. ' = DONT CARE

- - - = THREE·STATE HIGH IMPEDANCE

Figure 8: Handshake - Typical UART Interface Timing

4-131

I

,...
•
"

D~DIL

8052/7104 8068/7104'

II
~

Figure 7 shows the sequence of the output cycle with SEN
held high. 'The handshake mode (Internal MODE high) is
entered 'after the data latch pulse (since MODE remains high
the CElLO, LBEN, MBEN and HBEN terminals are active as
outputs). The high level at the SEN input is sensed on the
same high to low'intern1l1 clock edge. On the next low to high
internal clock edge, the CE/[Ij,'and the HBEN outputs
assume a low level and the high-order byte (POL and OR; and
except for -16; Bis 9-14) outputs are enabled. The CElLO
output remains low for one full internal clock period only, the
data outputs remain active for 1-1/2 internal clock periods,
and the high byte ENable remains low for two clock periods;
Thus the CElLO o.utp,ut low level or low to high edge may be
used as 1l synchronizing signal to ensure valid data, and the
byte E/ilable as an output may, be used as a byte identification flag. With SEN remaining high the converter completes
the output cycle using CElLO, MBEN and LBEN .while the'
remaining byte outputs (see Table 4) are activated. The
handshake mode is term inated when all bytes are sent (3 for16,2 for -14, -12).
Figure 8 shows an output sequence where the SENinput is
used to delay portions of the sequence, or handshake, to
ensure correct :data transfer. This timing diagram shows the
relationships that occur using, an industry-standard
IM6402/3 CMOS UART to interface to serial data channels.
In this interface, the,SEN input to the ICL7104 is driven by
the TBRE (Transmitter Buffer Register Empty) output of the
UART, and the CE/CO terminal of the ICL7104 drives the
TBRL (Transmitter Buffer Register Load) input to the UART.

The data outputs are paralleled into' the, eight Transmitter
Buffer Register inputs,
Assuming the UART Transmitter Buf~er Register is empty,
tile SEN input will be high when the handshake mode is
entered after' new data is stored. The CE/iJ) and HBEN
terminals will go low after SEN is sensed, and the high order
byte outputs become active. When CElLO goes high aUhe,
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UARTTBRE
output will now go low, which halts the output cycle with the
RBEN output low, and the ,high order byte outputs active .. '
When the UART has transferred the data to the Transmitter
Register and cleared the Transmitter Buffer Register, the
TBRE returns high. On the next ICL7104 internal clock high
to low edge, the high order byte outputs are disabled, and
one-half internal clock later, the HBEN output returns high. '
At the same time, the CElLO and MBEN (-16) or LBEN
outputs go low, and the corresponding byte outputs become
active. Sim'ilarly, when the C'E/DJ returns high at the end of
one clock period, the enabled data is clocked into the WART
Transmitter Buffer Register, and TBRE again goes low.
When'TBRE returns to a high it .will be sensed on the next
ICL7104 internal, clock high to low edge, disabling the data
outputs. For the 16 bit,device, the sequence is repeated for
LBEN. One-half internal clock later., the handshake mode
will' be ,~cleared, and the chip and byte ENable terminals
return high and stay active (as long as ,MODE stays high).
With the MODE input remaining high as in these examples,
the converter will output the results of every conversion
ZERO CROSSING

INTERNAL
CLOCK
INTERNAL
LATCH

-----+-01 ,.-+-+---:-...,....u .........;=F.:..;::=-.&....~--+-+----:-..II---+-+--

MODE
INPUT=~=~

INTERNAL
MODE=~

__

SEN
INPUT

Rl!'EIiI'--.;..~-r-HIGH

~~! ---.,....----~ 1--.+.-1c=~~~~I~=j
MBEN ;,..,_:.... _ _

r---...,....I--I------4f---+-""'"
'-----0--+-...(

MIDDLE ~!~!

____ ':"" ___ -! I-

II =

DON7CARE

~

- - = THREE-STATE HIGH IMPEDANCE

Flgure,9: Handshake Triggered By Mode

4-132

-,"'- =

THREE-ST~TE WITH PULLUP

8052/7104 8068/7104

O~OIb

except those completed during a handshake operation. By
triggering the converter into handshake mode with a lowto ,
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure 11 shows a handshake
output sequence triggered by such an edge. In addition, the
SEN input is shown as being low when the converter enters
handshake mode. In this case, the whole output sequence is
contrplled by the SEN input, and the sequence for the first
(high order) byte is similar to tlie sequence for the other
bytes. This diagram also shows the output sequence taking
longer than a conversion cycle. Note that the converter:...still
makes conversions, with the STaTuS output and Run/Hold
input functioning normally. The only difference is that new
data will not be latched when in handshake mode, and is
therefore lost.

As a result of pin count limitations, the ICL7104-16 has only
CI!.OCK 1 and CLOCK 2 available, and cannot be used as an
RC oscillator. The internal clock will correspond to the
inverse of the signal on CLOCK 2. Figure 11,shows a crystal
. oscillator circuit, which can be used with all 7104 versions. If
an external clock is to be used, it should be applied to
CLOCK 1. The internal clock will correspond to the Signal
applied to this pin.

Initial Clear Circuitry
The internal logic of the 7104 is supplied by an internal
regulator between V++ and Digital Ground. The regulator
includes a low-voltage detector that will cl,ear various
registers. This is intended to ensure that on initial power-up"
the control'logic comes up in Auto-Zero, with the 2nd, 3rd, and
4th MSB bits cleared, and ·the "mode" FF cleared (i.e. in
"direct" mode). This, however, will also clear these registers
if the supply voltage "glitches" to a low enough value.
Additionally, if the supply voltage comes up too fast, this
clear pulse may be' too narrow for reliable clearing. In
general, this is not a problem, but if the UART internal
"MODE" FF should come up set, the byte and chip ENable
lines will become active outputs. In many systems this could
lead to buss conflicts, especially in non-handshake systems.'
In any case, SEN should be high (held high for nonhandshake systems) to ensure that the MODE FF will be
cleared as fast as possible (see Fig. 7 for timing). For these
and other reasons, adequate supply bypass is
recommended.

Oscillator
The ICL7104-14 an9 -12 are provided with a versatile three
terminal oscillator to generate the internal clock. The
oscillator may be overdriven, or may be operated as an RC or
crystal oscillator.
Figure 10 shows the oscillator configured for RC operation.
The internal clock will be of the same frequency and phase as
the voltage on the CLOCK 3 pin. The resistor and capacitor
should be connected as shown. The circuit will oscillate at a
frequency given by f = .45/RC. A 50-100kO resistor is
recommended for useful ranges of frequency_ For optimum
60Hz line rejection, the capacitor value should be chosen
such that 32768 (6), 8192 (-141, 2048 (-12) clock periods is
close to an integral multiple of the 60Hz period.

25

CLOCK
1

24

26

CLOCK

CLOCK

3

2
R

lose

~

Figure 11: Crystal Oscillator

POWER SUPPL V SEQUENCING
Because of the nature ofthe CMOS process used to fabricate
the ICL71 04, and the multiple power supplies used, there are
certain conditions of these supplies under which a disabling
and potentially damaging SCR action can occur. All of these
conditions Involve the V+ supply (nom. +5VI being more
positive than the V++.supply. If there is any possibility of this
occuring during start-up, shutdown, under transient
conditions during operation, or when inserting a PC board
into a "hot" socket, etc., a diode should b.e placed between V+
and V++ to prevent it. A germanium or Schottky rectifier
diode would be best, but in most cases a silicon rectifier
diode is adequate.

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of 8068 or 805217104 circuits, especially in 16-bit and
high sensitivity circuits. It is most important that return
currents from digital loads are not fed into the analog ground
line. A recommended connection sequence for the ground
lines is shown in Figure 12.

APPLICATIONS INFORMATION
Some applications bulletins that may be found useful are
listed here:
"Selecting AID Converters", by Dave Fullagar
"The Integrating' AID Converter", by Lee, Evans
"Do's and DonI's of Applying A/D Converters", by
Peter Bradshaw and Skip Osgood
"Building a Remote Data Logging Station", by Peter
Bradshaw
A030 "The ICL7104 - A Binary Output AID Converter for
.
Microprocessors", by Peter Bradshaw
R005 "Interfacing Data Converters & Microprocessors", by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.
A016
A017
A018
.
A025

c

.45/RC

Figure 10: RC Oscillator
Note that CLOCK 3 has the same output drive as the bit outputs.

4·133 .

II
'

~

O~OIb

8052/7104 8068/7104

~r--'VV'vV

IN

EXTERNAL
REFERENCE
(IF USED)

---1

liP
FILTER
CAP

8068 PIN 2
COMP

~/
DIGITAL
LOGIC

K

DIG GND
ICL7104
PIN2

B.OAROI
EDGE

I

>...

I .
I

~-~ARALLEL BCD OUT

TIL 306 OR 745-0009
OR EQUIVALENT

I I I I

I I I I

I I I I

I I I I

3214

3214

3214
71-1 10 -

3214
3214
7 1_1 10 1--.--7 1 1 10

1 I 9
12 15 5 14 l

91-12 15 5 14

110~r- 7 1 110~

1

9~

I

1 1
12 15 5 14

1 9l
12 15 5 14

I I I I

U

hi

U

rh

9U
12 15 5 14

.5.0V

f~~~E

[l
I
I
I I I
I I
1 1
2REA~~go---+-1-~====~=+=t~========+=t=~=======+=t==========t=r-~--~-------l

! -ollllll

~~~~~~i7~~S~~~~~I~L~-S-T-ER-_-SL-A-V-E-FiLl=P_=F~LO=P=1====~=====Q=D=1=1~1E=2= =6~= 6~5~1= .A=2='7=k=4l36~C:LE~:~:T-C-~1~: :21~ ~:~F~'5~'10~2VrB~L~:-;Y:KC
__

23456-

_~_

CD4025 - TRIPLE 3-INPUT NOR GATE
CD4073 - TRIPLE 3-INPUT AND GATE
CD4070 - QUAD EXCLUSIVE OR GATE
74C161 - 4-BIT BINARY COUNTER
74L04 - HEX INVERTER

Qc

~ 12
Q: 13
14

I'

NOTE: FOR 3-3/4 DIGIT USE 16kHz CLOCK
FREQUENCY AND DELETE TIL306 FROM MIDDLE

9
10

57

R

I
-1
IIMSB

.

0047 F
"6
1 4
4

+5V

11 6

10

I tF~8
6 51=
1m

MSB
EXTERNAL

+5.0V



12

--

'

~"'-11~~--;:=::],..--.

--;;!c/1~1~
3 10
12

I

1 14

12

IN914

6

3
1

1

..- 57 ,4 2,1-+-+-I-W1--I--J.-J

~.:
-it--- .. " --------"~~!~---------- , J:'''"'
OJ T ,

'ii

6-15V

1

+-______________-<~)(
2! U(ill-,-31!~
.......--_H+f_+_J

-15V

-~

1

-.J.1.!..!1___+-I-1

'-+-________________________________~------------------_+~1~0~~2~~~~---+4
~

9~

'--------------------------------+--------------------~~5(~~1~--~

DATA VALID

Figure 7: 4-::1/4 Digit DVM

4-143

ICLS052/S053 S052A/S053A
CLOCK FREQUENCY
120KC FOR
3 READINGS/SEC.

O~OIL

PARALLEL BCD OUT

n

LI

'9

12 15 5 14

+5.0V

9

IFREE
I RUN
I

~--

__------~----------~~--------4r~----------~~-+------~--o

SYNC

~

_

L

MSB

_____________ _
ICL8053A

15V

DATA VALID

PACKAGE DESIGNATION
1 - CD4027 - DUAL JK MASTER-SLAVE FLIP-FLOP
2 - CD4025 - TRIPLE 3-INPUT NOR GATE
3 - CD4073 - TRIPLE 3-INPUT AND GATE
4 - CD4070 - QUAD EXCLUSIVE OR GATE
5 - 74L04 - HEX INVERTER
6 - 74L74 - DUAL 'D' FLIP-FLOP
7 - 74L74 - DUAL 'D' FLIP-FLOP

NOTE: FOR 3-1/2 DIGIT USE 1/10 CLOCK FREQUENCY
AND DELETE TIL306 FROM MIDDLE.

Figure 8: 4-1/2 Digit,OVM (Parallel BCD)

4-144

ICLS052/S053 S052A/S053A

12~________________~-JV10~k~~~~~

17
, ~

100pF.:r:

r----r--Ir====t=~====:t====~i
I

14~________________I77
________~CA~R~R~Y~

10
116

9
OVERRANGE

'5,OVI

qr-

1

I
I

.

(~

't~PU,TT 111~ +
o·~rl

~'
":"

I

I
I

I

'I

t

15V

PACKAGE DESIGNATION
1 - CD4027 - DUAL JK MASTER-SLAVE FLIP-FLOP
2 - CD4025 - TRIPLE 3-INPUT NOR GATE
3 - CD4073 - TRIPLE 3-INPUT AND GATE
4 - CD4070 - QUAD EXCLUSIVE OR GATE
5 - 74L04 - HEX INVERTER
6 - 74L74 - DUAL 'D' FLIP-FLOP
7 - 74L74 - DUAL 'D' FLIP-FLOP
8 - MM74C926 - 4 DIGIT COUNTER WITH MULTIPLEXED
7-SEGMENT OUTPUT DRIVERS

DATA VALID
NOTE: FOR 3-1/2 DIGIT USE SAME 'CLOCK FREQUENCY AND DELETE LEAST
SIGNIFICANT LED.

(

Figure 9: 4-V2 Digit DVM (20,000 Count Multiplexed Display)

ICL8052 vs. ICL8068
An alternative to the 8052 is the 8068.
While the ICL8052 offers significantly lower input leakage
currents than the ICLS068, and may be found preferable in
systems with high input impedances, the ICL8068 has sub4-145

stantially lower noise voltage and will give better performance in systems where noise Is a limiting factor, such as
low signal level conditions, Specifications m.ay be found in
the ICL8068/1CL8052/1CL71C03 and ICL8068/1CL80521
ICL7104 data sheets,

NOTES:

4·146

'. i
;':

"

"

Linear
'.~.~',

......

......" ..

Amplifiers

,..'.

Driver Amplifier for
Power Transistors
Page
ICL8063
5·213
Driver Amplifier for
Actuators, Motors
ICH8510/20/30
5·239
ICH8515
5·247
Instrumentation,
Commutating Auto·Zero
ICL7605/6
5·130
Log·Antiiog
ICL8048/49
5·205
Operational,
Chopper Stabilized
ICL7650
5·155
0perational,
Commutating Auto·Zero
ICL7600/1
5·121
'Operational, FET Input
, LH0042
5·6
AD503
5·49
SU/NE536
5·52
/LA740
5·66
ICL8007
5·171
ICL8043
5·198
ICH8500
5·233
Operational, General
Purpose
LM1011301
5·15
LM107/307
5·27
LM108/308
5·32
LM124/324
5·38

~

,

.'

".

5·70
/L A741
ICL741HS
5·72
AD741K
5·74
ICL741LN
5·75
5·78
/LA748
5·85
/LA??7
LH2101/2301
5·91
LH2108/2308
5·93
IH5101
5·113
ICL8008
5·174
Operational, High
Impedance
HA2600 Family
5·106
HA2607/27
5·109
Operational, High Speed
HA2500 Family'
5·99
HA2507/17/27
5·104
ICL8017
5·183
Operational, Low Power
LM4250
5·111
ICL76XX Series
5·140
ICL8021·23
5·187
Video
/LA733
5·63

Comparators
Dual
LH2111/2311
Followers
LM102/302
LM110/310
LH2110/2310

5·97
5·19
5·19
5·95

Low Power
ICL8001
Precision
LM1111311
Quad
LM139/339
Sample and Hold
IH5110·15
T~mperature Sensor
AD590
Voltage Reference
ICL8069
ICL8211/12
Voltage Regulators
LM100/300
LM105/305
/LA723

5·167
5·33
5·41
5·115

1"

5·55
5·221
5·223
5·11
5·23
5·57

Special Function
Multiplier
ICL8013
5·176
Voltage Converter
ICL7660
5·161
Waveform Generator
ICL8038
5-'190

"

II

.........................

.D~~lm

Operational Amplifiers-General Purpose
Type
lOlA
10lALN
107
lOB
10BA
10BLN
124'

Deac.rlptlon
General Purpose, Uncompensated
Guaranteed Noise lOlA
Gen Purpose, Compensated
Low. Level, Uncompensated
Low Offset lOB
. GuaranteeH Noise lOB
Quad, Compensated

Ib
(nA)

Vos
(mV)

AVOL
(V/V), '

GBW(typ)
(MHz)

Isupp

2.0
2.0
2.0
2.0
0.5
" -'2.0
5.0

75
75
75
2.0
2.0

50,000
50,000
SO,OOO
50,000
. BO,OOO

O.B
O.B
1.0 '
1.0

3.0
3.0
3.0
0.6
0.6

2.0
300

50,000
100,000

1.0
1.0

0.6
2.0

O.B
O.B

Packages·

-55, + 125
. -55, + 125
-55, + 125
-55, + 125
-55,+ 125

J,F,T
J,F,T
T
J,F,T
J,F,T

-55, + 125
-55, + 125
0,
0,
0,
0,

+ 70
+ 70
+ 70
+ 70

v' Hz@IOHz

T
J

70 nVI

v' Hz@ 10 Hz

P,T
P,T
P,T
F,J,P,T

50 nVI

v' Hz @ 10 Hz

70 nV I

v' Hz @ 10 Hz

- Gen Purpose, Uncompensated
Guaranteed Noise 301A i
Low Bias, Compensated
Low Level, Uncompensated

7.5
7.5
7,5
7.5

2SO
2SO
2SO
7.0

1.0

3.0
3.0
3.0
O.B

30BA
30BLN
.324
741
741C

Low Offset 30B
Guaranteed noise 30B
Quad; Compensated
. Gen Purpose Compensated
Gen Purpose Compensated

0.5
7.5
7.0
5.0
6.0

7.0
7.0
SOD
'500
SOD

BO,OOO
25,000
100,000
50,000
25,000

1.0
1.0
1.0
1.0
1.0

O.B
O.B
2.0
2.B
, 2.B.

0, + 70
0, + 70
0, + 70
'-55,+ 125
0, + 70

J,T
T
J,P
T
P,T

5.0
6.0
5.0
, 6.0
0.5

SOD
SOD
500
500
50

50,000
25,000
50,000
25,000
50,000

1,0
1.0
1.0
1.0
1.0

2.B
2.B
2.B
2.B
2.B

-55,.+ 125
0, + 70
-55, + 125
0, + 70
Oto 70

J,T
'P,T
J,F,T
P,T
T

25,000
25,000
150,000
150,000.
20,000

O.B
O.B
O.B
O.B

-55 to 125
01070
-55, + 125
0;+ 70
-55, + 125

P,T
P,T
P,T
P,T
J,T

741HS
741CHS
741LN
741CLN
741K

Guaranteed Slew Rate '741
Guaranteed Slew Rate 741C .
Guaranteed Noise 741
Guaranteed Noise 74ic
High Accuracy 741

74B
74BC
mc
BOOBM

General Purpose
General Purpose, Compensated
General Purpose Comparator
General Purpose Comparator
Low bi~s Current, Compensated

1.0
1.0
0.7
0.7
5.0

BO
BO
25
25
10

to,

2.0
2.0
2.5
2.5
2.B

BOOBt
IH510r
LH2101A

Low bias current, Compensated
Ullra low noise
Dual high performance

6.0

"moo
••"~,,
LH210BA ,Dual
super .m
beta

20,000
100,000
25,000
25,000
40,000

1.0
10.0
O.B
1.0
1.0

/ 2.B
15.0
2.5
0.4
0.4 ,

-0, + 70
-55 to +125
-55 to 125
-55 to 125
-55 to 125

J,P,T

2.0
2.0
0.5

25
1,000
100
3.0
3.0

LH2301A . Dual high perfbrmance
LH230B
Dual super beta,
.
LH230BA Dual ~uper' beta

7.5
7.5
0.5

300
10
10

15,000
15,000
SO,OOO

O.B
1.0
1.0

2.5
0.4
0.4

'01070
01070
01070

D
D
D

777

Remarks
50nVI

301A
30lALN
307
30B

lIB

25,000
25,000.
25,000 .
25,000

TA
(OC)

(mA)

Slew Rate O. 7V IllS
Slew Rate 0.7V I ~S
50 nVI v' Hz @ 10 Hz
~O nV I v' Hz @ 10 Hz

·1
D
D
D

Operational Amplifiers-Low Power Programmable
Type

Description

4250
42SOC

Programmable, Uncompensated
Programmable, Compensated

B021M
B021C
B022M
B022C
B023M
B023C

Programmable, Compensated
Programmable, Compensated
Dual B021M
Dual B021C
Triple B021 M
Triple B021C

Vos
(mV)

. Ib
(nA)

5.0
5.0
S.O
3.0
6.0
3.0
S.O
3.0
6.,0

10
10
75
20
30
20
_,30
20,
30

AVOL
_ (V/V)
25,000
25,000
25,000
SO;OOO
SO,OOO
SO,OOO
SO,OOO
SO,OOO
SO,OOO

'GBW
(MHz)

Isupp
(IlA)

0.27
0.27
0.27
0.27
0.27
0.27

B.O
B.O
90
40
50
40
SO
40
SO

atlset

(IlA)
1
1
10
30
30
30 '
30
30
30

at Vs
(V)

TA ,
(OC)

'±I.S
±1.5
±1.5
'±S.O
±S.O
±S.O
±S.O
±S.O
±S.O

-5510125
0, to 70

T

-55, - 125
0, -70
-55, - 125
0, -70
-55, to 125
O,to 70

J,T
T
J,F
J,P
J
J,P,

, Packages·
T

Video Amplifiers
Type

Description

'733M : ' Gain selectable video amp:
Gain selectable video, amp.
733C

Gains (lyp)
(V/V).

Bandwidths (typ)
(MHz)

en
IlV(rms)

Output
Oflset(V)

Isupp
(mA)

400,100,10
400,100,10

40,90,120
40,90,120

,12
12

'1.5
1.5

24
24

'See package key, page 5-5.

5·2

TA
(OC)
_ -55, + 125
0, + 70

Packages·
T
T

Operational Amplifiers- FET Input
Type

Description

Vas
.-1--1--,"'"'1

INPUT

I
,I
I
I

6

~~1~

1~\PUT

REFERENCE

I
I

_ _ _ _ .J

Dl1N914

>-'VVI,--+-",.

021N914

I

____

ANALOG
OUTPUT

I-=

Cl
O.OI"F
POL VSTYRENE

PRECISION VOLTAGE COMPARATOR

ALTERNATE LOW DRIFT SAMPLE

5-8

LH0042/LH0042C
TYPICAL PERFORMANCE CHARACTERISTICS (CON'T.)
OUTPUT SWING VS SUPPLY
VOLTAGE

OUTPUT VOLTAGE SWING
VS LOAD RESISTANCE

CURRENT LIMITING
'5

40
~

RL '" 2KS1

36

~

32

~

28

~

24

"o
"~

0

"~

8

i!:

~

TA '" 25°C

/'"

28

~
~

./

26
24

~

/'

2

-

"~ '6'4
0
12

SWING - V p.P

./

"~

~

"z
~

,.

I

o
o

10

LOAD RESISTANCE (kS1)

15

20

25

30

Ol(TPUT CURRENT (±mA)

VOLTAGE FOLLOWER LARGE
.. SIGNAL RESPONSE

TRANSIENT RESPONSE

12

Vs - ±15V

'5

Vs = !15V

RL = 2K

Rl = 2K
T = 25°C

TA = 25"C

'2

-

25

SUPPLYVDtTAGE (tV)

'6

'\

r °i

~~.'~0~.2-L~0~.5~~'.~0~2~.0-L~5~.0~~'0

OUTPUT VOLTAGE SWING VS
FREQUENCY

Vs =1"5V

12S-

0

'\

'0

'8

0

VOUTPUTVOLTAGE_

6

----

20

"i!:
"

./

Vs o>:!:lSV
TA = 25"C

22

>-

l - F:::: ::--

~

1

.,"
w

,0

INPUT \

~

w

.".,

'0

[

OUTPUT

0

INPUT

>

~

>-

~

0

>
>-

-4

-5

"0

"i!:
"0

I

-8

0

,k

'Ok

lOOk

-12

1M

OUTPUT

-'0
I

'0

'OM

.200

.400

TIME (I-Is)

FREOUENCY (Hz)

FREQUENCY CHARACTERISTICS VS
AMBIENT TEMPERATURE
1.4

I

,

FREQUENCY CHARACTERISTICS VS
SUPPLY VOLTAGE
',4

I I

'.2

I
I

Vs = ±15V

'.2

I-JRIANSIE~T

TRANSIENT

~

;-- t---

'.0

T~

V

~WRAT

r---

CLOSEDLO~F

S.R·

I

BANrWliTH

0.8

0.6
-60

-20

II

20

60

~ ~NSE-

l-

,-

'.0

120
'00
80

~

r-- BjNDWrTH

I
100

'0

140

OPEN LOOP TRANSFER
CHARACTERISTICS VS FREQUENCY

'0

IlIlr

40

•

'00

Av= 100

'0

11/

2

'0

VII

lOOk

~AIN

"'"

-45

"'-

PHASE SHIFT

,

r::::- ~,

~
'Ok

3

'0

Hl
1k

5,

'M

10' .1

10

100

Vs "'±15V
TA = 25"C 45
f\ ;:. 2KU

-

'""'- "'-

'0

1IAV= 10

20

G

'0

III

60

20

'5

SUPPLY VOLTAGE (tV)

'.

tiSi·

,::::::.

~OSEDllOOP

0.8

~

OUTPUT RESISTANCE VS
FREQUENCY
'40

-

"

SLEWR~

TEMPERATURE (" Cj

160

TA = 25°C

lk

'"

10k

5-9

~

lOOk

FREaUENCY 1Hz)

FREaUENCY (Hz)

-90

-"1'

-135

~.

1M

-180

10M

.600

Vs=±lSV
RL = 2K

1

I-

r--

C = 1'001' I.800

LH0042lLH0042C
TYPICAL PERFORMANCE CHARACTERISTICS

1,000

700

./

0

~

o

500

o

~

400

is

300

ffi

200

iii

~

V

_

~
a:
"'-'

V

,V

\

,
0.0,

.\

'00
50

65

85

105

O.

125

INPUT OFFSET VOLTAGE
VS TEMPERATURE

~

i
o
>-

"~

~~
w

/

>

-500

a l- ~o
1:1

1/

lOOO

V

/

V

V

V

~

~

'00

60

INPUT SOURCE RESISTANCE

'00 r-r-mrmr-'TTTmr-rrm",--nmTnn

I'v;

= ±15V

80 H+HcHII--++++HII-+f+tRs = lOOn

~
~

/'

'2

"

z
o

~LO~~'~OO~~W,Lk-L~'~O~k-W~,WOOk

CHANGE IN INPUT OFFSET
VOLTAGE D'UE TO THERMAL
SHOCK VS TIME

1":

15 0

~

"

1l"
'-'

TA = 25"C
PREVIOUS Vos 0;;; 1 /J.V

/'
\

/'
'0

'5

TIME FROM.POWER APPLICATION (MIN)

VOLTAGE GAIN
'20

I

TAJ~

0

O~

I

0

~

0

I

0

tAPPLY

I---

I

-20

20

"-

20

SUPPLY VOLTAGE VS
SUPPLY CURRENT.

Vos""/-tV

;;;

'OM

STABILIZATION TIME OF.INPUT
OFFSET VOLTAGE FROM POWER
TURN-ON

PREVIOUS QUIESCENT

o

'M

lOOk

'Ok

'\.

I I v; = l"iv I I
100

~

tON

6o'c~1

II

~

/

SOURCE RESISTANCE (m

SUPPLY VOLTAGE (±V)

FREaUENCY (Hz)

:z:
'-'

100

//

w

"

o

w

~

'/
fo=10~

/

;;;

'-'
Z

150

Vs = ±15

'-'

ir

~

200

TA = 25°C

~w '6
>-

>-

~

20
w

'-'

TA=25°C

1\

'i

300
250

tn)

COMMON MODE INPUT VOLTAGE
VS SUPPLY VOLTAGE

60r\+H~-++++HII-+~mr-t+

~

TA '" 25°C

0,.

'40

TEMPERATURE (O_c)

25"C

125

Vs = ±15V

50

......

105

400
350

oz
>-

20

85

o

~

, -20

65

45

'-'

~

TOTAL INPUT NOISE VOLTAGE'
VS FREQUENCY

~

25

TOTAL INPUT NOISE VOLTAGE'
VS SOURCE RESISTANCE

OFFSET ERROR (WITHOUT
Vas NULL) -

1/

0' 500

,

T _ TEMPERATURE (0 C)

-

Vs = ±15V
Vas';;: 51lV AT2S'C

~ 1000

[7

,

T - TEMPERATURE (OC)

TEMPERATURE (Oe)

~

oV

~
a;

45

V

100

!:;
~

25

200

'50

'00

V

./

1,,000

V

600

z

INPUT BIAS CURRENT VS
TEMPERATURE
10,000

INPUT OFFSET CURRENT
VS TEMPERATURE

MAXIMUM POWER DISSIPATION
800

40

60

80

80
5

100

TIME FROM HEAT APPLICATION (SEC)

SUPPLY VOLTAGE (±V)

'NOISE VOLTAGE INCLUDES CONTRIBUTION FROM SOURCE RESISTANCE.

5-10

k:::::o p

--

'0

TA

=25"C

TA
'5

SUPPLY VOLTAGE (±V)

I

.

12S C
Q

20

O~OIl

LM100, LM300
Voltage Regulator

FEATURES
• Adjustable short circuit current limiting
• Output voltage adjustable from 2V to 30V
• Output currents in excess of 5A possible by adding external transistors
• One percent load and line regulation
• One percent stability over full military temperature range. Can be used as either a linear or high-efficiency switching regulator

GENERAL DESCRIPTION
The ·Intersil 100/300 monolithic integrated circuit is a
voltage regulator. It is designed for use in applications ·that
range from digital power supplies to precision regulators.

PIN CONFIGURATIONS

The output voltage is adjustable from 2V to 30V with a 1%
load and line regulation. Short circuit current limiting is
also adjustable. By adding external transistors, output currents in excess of 5A are possible.
BOOSTER
OUTPUT

"'i

The device can be used as either a linear or high·efficiency
switching regulator, and will start on any load within rating.
It responds .quicklY to both load and line transients and
features small standby power dissipation, and freedom from
oscillations with varying resistive and reactive loads.

UN~EGU~~T."~~

GROUND
REFERENCE
BYPASS

TOP VIEW

SCHEMATIC DIAGRAM

.---r--------.,------,---.,-,-

(outline dwg FB)

3UNR£GULAfED IN~UT

NOTE: Pin 4 connected to bottom of package.

"
'"
"

·201(·

"
'"

~~
REGULATED
OUTPUT

,""

+----N'r+--W'Y-t+--~--+-

B REGULATED ouTPUT

BOOSTER
OUTPUT

6

2

FEEDBACK

GROUND
TOP VIEW

.-----

~REHRENCEBYPAs.s

"'
'"

NOTE: Pin 4 connected to case.

ORDERING INFORMATION
Part number
LM100
LM300

(outline dwg TO-99)

To 99
Can

. 10-Pin
Flatpak

LM100H*
LM300H

LM100F

Dice
LM100/D
LM300/D

* Add /8838 to order if 8838 processing is desired.

5-11

D~DIl

LM 100, LM300
ABSOLUTE MAXIMUM RATINGS
LM100
Input Voltage
Input·Output Voltage Differential
Power Dissipation (Note 1)
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering: 60 sed

40V
40V
500mW
-55°C 'to +150°C
-65°C to +150°C
, 300~C

LM300
35V
30V
300mW
O°C to 70°C
_55°C to 125°C,
260°C

ELECTRICAL CHARACTERISTICS (Note 2)

PARAM,ETER

CONDITIONS

LM100
TYP

LM300
TYP

MIN

8,5

40

8.0

30

V

Output Voltage Range

2,.0

30

2.0

20

V

Output·lnput Voltage,
Differential

3.0

30

3.0

20

V

Input Voltage Range

Load Regulation (Note 3)
Line Regulation

Temperature Stability

Rsc = 0, 10
VIN
VIN

< 12 mA

-VOUT
-VOUT

<:::; 5V
5V

>

-55°C <:::; TA <:::;+125°C
O°C'<:::;TA <:::;70°C .

Feedback Sense Voltage
Output Noise Voltage

10 Hz <:::; f <:::; 10 kHz
=0
CREF = 0.1 {..IF

0.1
0.05

0.2
0.1

0,3

1-.0

,

0.005
0.002
0.1

Lo

VIN = 40V
VIN = 30V

1.0

3,0

VIN - V OUT ='30V
V IN',- V OUT = 20V

1.5

Long Term Stability

" Minimum Load Current

0.5

1.8

C"REF

Standby Current Drain

0.1

MAX

UNITS

MAX

MIN

0.1

0,5

%

0.1
0.05

0.2
0.1

%/V
%/V

0.3

2.0

%
%

1.8

V

0.005
0.Op2

%
%
,%

0.1

1.0

1.. 0

. 3.0

mA
mA

1.5

.3.0

mA
mA

3.0

NOTE 1: The maximum junction temperature of the 100 is 150"'C, while that of, the 300 is 100"'C. For operating at elevated temperatures
devices in ,the TO-5 package must be derated based on a thermal resistance of 150"C/W, junction to ambient or 45"C/W, junction
to case: For the flat package, the derating' is based on thermal resistance' of 185"C/W when mounted on a 1/16-inch-thick epoxy
glass board with ten 0.03-inch·wide, 2·ounce copper conductors. Peak dissipations to lW are allowable providing the dissipation
rating is not exceeded with the power av~raged over a five second i n t e r v a l . '
.
NOTE 2: These specifications apply for a junction temperature between -55"C and +150"C, (100) O°C and 70"C, (300) for input and output
voltages within the ranges given, and for a divider impedarce seen by the feedback terminal of 2 kIl, unless otherwise specified.
The load and line regulation speci~ications are for constant junction temperature: Temperature drift effects must be taken into
account separately when the unit is operating under co'nditions 6f high dissipation.
.
\
NOTE 3: The output currents given, as well as the load regulatiqn: can be increased by the addition of external transistors. The improvement

,factor will be roughly equal to the composite current gain of the added transistors.

5-12 '

O~OIb

LM 100, LM300
TYPICAL PERFORMANCE CHARACTERISTICS FOR 100,300*
REGULATION
CHARACTERISTICS
WITHOUT CURRENT
LIMITING
1.00t

~'.000

T,I.

~

.......

.999

T,

2~'C I-- I--

.,SOtc

.998

~ I--

~

~

o

~ 0.99

a:

I I
o

10

.~

~ ~~-

•

5

~

ffi

~

"

30

U
I-

'5
u

i

:::; 0.3

a:

:la:

0.6

a:

0.2

~

a:
0

ili

0.2
-40

40

80

~

~J~

lSi' 2arJi'"

10

.

I I
-40

40

"""

80

i"'o

...

~

10 15 20 25

"

. ".

~

I-

30 35 40 45

R, /I R2 -2. 2kn

2 3

10

50

SUPPLY VOLTAGE
REJECTION AS A FUNCTION
OF INPUT·OUTPUT VOLTAGE
DIFFERENTIAL

H-+++-+-H

0

.08

HI-·..-'P';..H-t-+++-+-H

...a:

;;

20

OUTPUT (VI

.1

~

".

10

I~CI

I-

"~

'"

:st-

In

·s

12.0

tT-

~

~-

:'-

20

13.0 1'""'1"""'T". .r-rT"7"-'-':::0~m~A""
Hc-t-t-+t-H Rse .. ton
VOUT • lOV

.~
1.0

I-

"l.-

30

120

REGULATOR DROPOUT
VOLTAGE AS A FUNCTldN
OF JUNCTION TEMPERATURE

w

t--

I-'

::1lI-

~-

OPTIMUM DIVIDER
RESISTANCE VALUES AS A
FUNCTION OF OUTPUT
VOLTAGE

z

JUNCTION TEMPERATURE

VOUT '" 2V

:'

I--=-

5

...~u

1

~,,~,

20

120

MINIMUM INPUT VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
8.0

0.4

r-+1--:'

40

'(10;>

I-

JUNCTION TEMPERATURE ("el

0
~

I'

,,,,

G

I-

""~

...">
0

I
I

40

I-

0.4

l-

"

"'

0.8

OUTPUT CURRENT (mAl

SHORT CI RCUIT CURRENT
AS A FUNCTION OF
JUNCTION TEMPERATURE

<

§

a:
u

i!:

0.5

"~"
t!:

1\
20 25 30 35

5

OUTPUT CURRENT (mAl

CURRENT LIMIT SENSE
VOLTAGE AS A FUNCTION'
OF JUNCTION TEMPERATURE

0
~

1\

10 15

0.98
20

15

.~

I-I-H
f- ~ ',- I-' -~ $0'Il.
~
fI-'
'"
'"
';I. I-- '"n
n

LOAD CURRENT (mAl

W

"T ~

'\

R c -'00

1.0

1.0

~

i"

I

a:

.991

Rsc -100

NI-$$~,

>

...~- '

CURRENT LIMITING
CHARACTERISTICS

I

I-

~

REGULATION
CHARACTERISTICS
WITH CURRENT
LIMITING

~
z

~

.1\

.06

""~

.04

>
~

.02

0

II:

iil

6.0

40

-40

80

120

-40

JUNCTION TEMPERATURE (CCI

MINIMUM LOAD CURRENT
AS A FUNCTION OF INPUT·
OUTPUT VOLTAGE
DIFFERENTIAL

<
~

2.0

"
0
"::;g
"::;Z
u

i

1.0

0.4

o 0.3
~
~

'/

::

10

~

40

INPUT·OUTPUT VOLTAGE DIFFERENTIAL IVI

..

IOV

)C~'''''I'F

Ll" '. ,
• ~:o-~

II

-9.2 HH-+-+--f-I-I-I-t-f

5

-0.3

5

30

VOUT

g
~.

20

L

0.1

-0.4

10
VO~TAGE

INPUT·OUTPUT

20. . 40

DIFFERENTIAL tV,)

LINE TRANSIENT
RESPONSE

I-t-t-t-f-f-t Rsc = 10n
-C -0 ~t- ::~:~Om";,.A

0.2

.~ -0.1

,.I

2' 3

120

LOAD TRANSIENT
RESPONSE

I

!

ffi

a:
a:

80

JUNCTION TEMPERATURE (OCI

~

I
I

I-

40

H-t-t-f-f-I--I--t-H
I-t-t-t-f-f-I--I--t-H

~ 0.2

z

0

;:

"~
..,...
~
"
0

0.1

Rsc

CL =0

·0

I"

';..

.... ,... t.
CL

> -0.1

I-

~:>

•

I
1 "F

I

I

~o

15

-0.2

0

10
TIfI':: ("sl

* 300 Only Guaranteed 0° C :'5. T A :'5. 7rf C
5·13

20

s.

·'on

4V 1N -SV
VOUT • tOV

I
I I

TIME I"s)

D~DIL

LM100, LM300
DEFiNitiON OF TERMS
INPUT VOL TAGE RANGE: The range of DC input
voltages over which the regulator will operate within
specifications.
OUTPUT VOLTAGE RANGE: The range of regulated out·

put voltages over which the specifications,apply.

'

OUTPUT-INPUT VOLTAGE DIFFERENTIAL: The volt-

age difference, between the unregulated input voltage, and
the regulated output voltage for which the regulator will
operate within specificati~ns.
'
LINE REGULA TION: The percentage change in regulated
output voltage for a change in input voltage.
LOAD REGULA TlON: The percentage change in regulated
output voltage for a change in load from the minimum load
to ,the maximum load current specified.

CURRENT-LIMIT SENSE VOL TAGE: Tl:le voltage across
the current limit terminals required to cause the regulator
to current,limit with a short circuited output. This voltage
is used to determine the value of the external current-limit
resi,stor when external booster transistors are used.
TEMPERATURE STABILITY: The percentage change in
output voltage for a thermal variation from room temperature to either temperature extreme.
FEEDBACK SENSE VOL TAGE: The voltage, referred to

ground, on the feedback terminal of the regulator while
it is operating in ~egulation.
OUTPUT NOISE VOLTAGE: The average AC voltage at
the output with constant load and no input ripple..
STANDBY CURRENT DRAIN: That part of the operating

current of the regulator which does not contribute to the
load current.

TYPICAL APPLICATIONS

200 rnA Regulator
A~

10

~4r--------~V~

AI

AI

v.
A2

A2

----~------+--+-GAOUNO

-------+---------.....+-GROUND

• Basing diagram is Top View

t Solid Tantalum
• Baaing diagram is Top View

4A Switching Regulator

_2A Regulator With Foldback' Current Limiting
A3
0,7

r.---4r-?---W.-~----'----'--.V~T

=

28V .

Of
lN3880

01
2N3065

A2
3.1K I

AS

. elt

IUV'
"

1m

A6

UK

t Solid tan18lu'm

• Basing diagram is top view-

view .

;=:~"t.~:v~~m I. t~
*60 tums = 20 on Arnold Engineering
A930157.2 molybdenum permalloy

co,.

LM101A/301A
General Purpose
Operational Amplifier
GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

The Intersil 101A and 301A are general purpose operational
amplifiers. These high performance op amps are improved versions of the standard 1011301.

Supply Voltage 101 A
301A
Power Dissipation (Note 1)
Differential Input Voltage
I nput Voltage (Note 2)
Output Short·Circuit Duration
Operating Temperature Range 101A
301A

This general purpose op amp has many outstanding features; overload protection on the input and output, no
latch-up when the common mode range is exceeded, and
freedom from oscillations. The 101 A also features better
accuracy and lower noise in high impedance circuitry, and
low input currents. Frequency compensation is achieved
with a single 30 pF capacitor. It has advantages over inter·
nally compensated ampl ifiers in that the frequency com·
pensation can be tailored to the particular application.
For example, in low frequency circuits it can be overcom. pen sated for increased stability margin. Or the compensa,
tion can be optimized to give more than a factor of ten
improvement in high frequency performance for most
applications.
The Intersil 101A operates over a temperature range from
- 55°C to + 125°C while that of the 301 A is O°C to + 70°C.

Storage Temperature Range
Lead Temperature (Soldering, 60 sec)

±22V
±18V
500mW
±30V
±15V
Indefinite
-55°C to 125°C
DoC to 70°C
_65°C to 150°C
300°C

NOTE 1: The maximum junction temperature of the lOlA is 150°C, while
that ofthe 301 A is 1OO'C: For operating at elevated temperatures
devices in the TO~5 package must be derated based on a thermal
resistance of 150°C/W, junction to ambient or 45°CIW, junction
to case. For the flat package, the derating is based on thermal
resistance of 185'CIW when mounted on a 1116-inch-thick epoxy
glass board with ten O.03-inch-wide, 2-ourice copper conductors. Th'e thermal resistance of the dual-in-line package is
lOQoCiW, junction to ambient.

NOTE 2: For supply voltages less than'" 15V, the absolute maximum
input voltage is equal to the supply voltage.

ORDERING INFORMATION .
Part
Number
101A
301A

8 lead
TO-99

8'pin
Plastic DIP

LM101AH'
·LM301AH

LM301AN

10 lead
Flatpak

,

14 pin
CER DIP

LM101AF'

LM101AJ-14

LM301AF

LM301AJ

14 pin
Plastic DIP

Dice
LM101AID

LM301AN-14

LM301ND

• Addl883B to ordering number if 883B processing is desired.

PIN CONFIGURATIONS
TO·5

Flat Package

.

BALANCEI
CQMPEIIISATION
II\IPUT

~

(outline dwg TO-99)
NOTE: Pin 4 connected to
case,

14P;nDIP

,
i

1.

~

.

_ INPUT..

v-

8 Pin Plastic DIP

1

S

COMPENSATION
v~

OUTP\JT
'8ALANCE

(outline dwg FB)

(outline dwg PAl

NOTE: Pin 5 connected to bottom
of package.

5-15

(outline dwgs JD. PD)
NOTE: Pin 6 connected to bottom
.of package.

LM~01A/301A
ELECTRICAL CHARACTERISTICS

(~ote)'

,
PARAMETER
Input Offset Voltage
Input

Of~sefCurrent

CONDITIONS

'.

TA = 25°C, Rs ~ 50.kll
TA = 25°C

I nput Bias Current

TA = 25°C

I tlput Resistance

TA = 25°C

Supply Current

T Ii = 25°C, Vs ,,; ±20V
TA = 25°C, Vs =±15V

Large Signal Voltage
Gain
, Input Offset Voltage

MIN

,

..

101A'
TYP
0.7
1.5
30

1.5

301A.
TYP

MIN

2.0

2.0

Rs ~ 50 kll

nA

75

70

250

nA

0.5

2

25°C ~ T A ~ 125°C
. 25°C:::; T A::; 70°C
.,..55°C ~ T A ~ 25°C
'0°C~TA~25°C

0.01
0.02

,

3.0

160

25

.15

6.0

20

I nput Offset Cu rrent

Mll

3.0

3.0

3.0

mV

50

160

50

7.5

UNITS

3

1.8

TA = 25°C, Vs = ±15V
V OUT = ±10V, RL ~;2 kll

MAX

10

4
1.8

Average Temperature
Coefficient of Input
Offset Voltage

Average Temperature
Coefficient of Input
Offset Current

MAX

mA
mA

V/mV
10

mV

30

jJ.vtc

'70

nA

0.1
0.01

0.3

0.02

0.6

0.2

nAtC
nAtC
nAtC
nAtC

(

I nput Bias Current
Supply Current

T A = +125°C, Vs = ±20V

Large Signal Voltage
Gain

Vs = ±15V, V OUT ='±10V
RL ~2 kll

Output Voltage Swing

Vs = ±15V, RL = 10 kll
RL = 2 kll

±12
±10

Vs =±20V
Vs = ±15V

±15

Input Voltage Range

300

- 100
1.2

mA

2.5

V/mV

15

25
±~4

±13

nA

±12
±10

.,

±14
±13

±12

V
V
V
V

Common Mode
Rejection Ratio

Rs ~50 kll

80

96

70

90

dB

Supply Voltage
Rejection Ratio

Rs ~50kll

80

96

70

96.

dB

NOTE: For the lOlA, these specifications apply for ±5V < Vs < ±20Vand -55°C S TAs 125"C unless otherwise specified.
For the 301A, these specifications apply for ±5V s Vs s ±15V and;O"C ~ TA s 70"C, unless otherwise specified.

5-16

LM101A/301A
GUARANTEED PERFORMANCE *
INPUT VOLTAGE RANGE
20

I
I
I

~
w
z

16

0:

12

'"«,

_55°C

~

POSlTIVE

w

'«"
:;

./

8

/'

0

>

....

:>

OUTPUT SWING

< T. < 125°C

V

,/

'z"

./ ./
./

151--l--l---+~+--t.-oS1

~
....:::>
....:::>

NEGATIVE

10 ~~--+-~~~-+---;

Q.

V

o

V

Q.

~

°5

10,

10 '

20

15

15

SUPPLY VOLTAGE ltV)

SUPPLY VOLTAGE ltV!

TYPICAL PERFORMANCE *
SUPPLY CURRENT (101A1201A)
2.5

:i

.s
....z
w

2.0

~ -55°~
....--;:::. :.--

-

:>

u

r

1.0

:>

0.5

~

'"

80

iii 110

f-"'"

1.5

100

_ T.

0:
0:

T• • 125°C

INPUT CURRENT

VOLTAGE GAIN (101A1201A)
120

1

T• • 25°C

z

;;:

-

'"w

I-""

100

'"«...J
....
0

>

90

80

15

10

T• •

:s

.

20

--

~55°C

k;::::= ~

==

TA ~ 25°C

~

:>
~

T• • 12SoC

z

!'11l

T• • 125°C

30JA\

15

~

w

u

>

'"~

i"-

w

25

f-;.

iii

:s

80

;;:

60

z

'w"

'....«"

40

0

20

...J

«
o

I " { I • 3 pF

r". "-

100

10

10k

lk

10

°

II -I I

12

'"~z
'"....

:::>

....:::>

100

lk

FREQUENCY 1Hz!

• 301A only guaranteed to ± 15V, O°C ~ T A

...J

0

>

Cl',t,0pF

°

10k lOOk 1M 10M

I III
lk

lOOk

1M

5-17

10k

lOOk

.8
6
4

-

J
I

T• • 25°C
Vs=±lSV

r ~JI---+-

1\

I

°

-4

I

OUTPUT

~

-2

-6

I

INPUT,

--

I

\

-8

~
10k

FREQUENCY 1Hz!

.s. 70° c.

~

'"w
'"....«

\

1\

0

'z"

Cl • 3 pF

\

lk

,VOLTAGE FOLLOWER PULSE
RESPONSE

~

1I

'\
10

100

FREQUENCY 1Hz!

T. '25°C
Vs = ±15V

~

-

II

lOOk,

10

Q.

pF

-20

If~

'"z

LARGE SIGNAL FREQUENCY
RESPONSE

T. 3p '\.\

>

10- 25

'
:E 10-u.

T• • 25°C
Vs=±lSV

1"'-

"-

FREQUENCY 1Hz!

1

• 25°C

0:

16

r
"- ~
~~

15 100 125

"- J,Olt

«
w

OPEN LOOP FREQUENCY
RESPONSE

~

so

T

:::>

30

'120

25

W

OUTPUT CU ARENT ItrnA!

100

-25 0

-

:::>

10- 16
20

-so

w

Z

15

~

~

:;;
10

-

OFFSET

INPUT NOISE CURRENT

_ 10- 24

«
w

o

. ;-.
TEMPERATURE 1°C!

?sa::

«
:::>
o


o

10iA

8

o
10

301A

BIAS

°,,,;-,

~

T•• 25 C

'"a
z

~T. '70o~d

~

....'"
ir....

T• • 25°C

20

Q.

INPUT NOISE VOLTAGE

Vs ·!tI5V

P'\0IA
301A

10.0

40

z

0:
0:

"""i-.

.-

SUPPLY VOLTAGE ltV!

CURRENT LIMITING

-...
'\ ')

....

w

oS

....:::>

15.0

.......

60

:::>
u

f-""

5

SUPPLY VOLTAGE I±V!

"-

:i

-10
10M

°

10 20 30 40 50 60 70 80
TIME

I~s!

.

n~nlL

LM101A/301A

EQUIVALENT SCHEMATIC DIAGRAM

BALANCE

INPUTS

COMPENSATION

----+---I--Co>
---+----11:. 01
>-+"W\~OUTPUT

R7

80K

R8
L-~~~-~~-+~

___

1K

~-----~~

__

~v-

R4
250

BALANCE

TYPICAL APPLICATIONS
Standard Compensation and
Offset Balancing Circuit

Fast Voltage Follower

v,.
+

1 Ci~PF
30pF

Rl

Power Bandwidth: 15 kHz
Slew Rate: W/!,s

10M

R1
10K

R2
S.1M.

~

.....-"""'-M-- vR3

'::'

201(

Fast Summing Amplifier
C2
3pF

R2
Rl
30K

v,.-oJo.I"""--+-~
>~-VOUT

Power Bandwidth: 250 kHz
Small Signal Bandwidth : 3.5 MHz
Slew Rate: 10VI!'s

5-18

LM102/302
LM110/310
High Performance Voltage Followers

O~OIb

FEATURES

GENERAL DESCRIPTION

• Low Input Current - 7 to 30 nA Max

The LM1 02/LM302 and LM11o/LM310are monolithic high
performance voltage followers. I n buffer appl ications they
offer substantial advantages compared I!I/ith general purpose
operationaL amplifiers: input current, ·bandwidth, and 'slew
rate are all significantly improved. Applications include high
speed sample' and hold circuits, instrumentation amplifiers,
active filters, as well as general purpose buffers.

• High Slew Rate - 10 to 30 V//ls
• Wide Bandwidth - 20 MHz (LM 11 0/LM31 0)
• Internal Frequency Compensatio'1
• 'Interchangeable with 741 in Follower
Applications

For new designs the LM110/LM310 is recommended.

PIN CONFIGURATIONS
(outline dwg T0-99)

EQUIVALENT CIRCUIT

BALANCE
'ALANCE

.--I-,::-,_---=",-.4--------......----1,...v·

""

""

A2
II<.

AJ
IK

NOTE: Pin 4 connected to case
TOP 'VIEW

~:

(outline dwg FB)

INPUT I

r---,/

()UTPUT

BOOSTER

NOTE: Pin 5 connected to bottom of Package,
TQPvlEW

(outline dwg JD)

'''---t----+------rt::a''
+---800STER

'"
".

"'"

'"
""

... OCO .......... ECT'ON

ORDERING INFORMATION

4

NOTE: Pin 6 connected to boI1Dm of package

Part
number

TO-99
Can

10 pin
Flatpak

LM102

LM102H

LM102F

LM110

LM110H*

LM110P

LM110J

411302

L.M302H

LM310

LM310H

LM310F

LM310J

14 pin
CER DIP

Bpin
Plastic DIP

(outline dwg PAl

Dice
'BALANCE

LM102JD
LM1101D
LM302/D
LM310N

LM310,o

•Add/8838 to order number if 8838 processing is desired:
5·19

v'
INPUT

v-

OUTPUT
'BALANCE

D~OIl.

LM102, LM302, LM110, LM310
ABSOLUTE MAXIMUM RATINGS
Supply Vollage
Power Dissipation (Note 1 J
Inpul Vollage (N.,. 2)
OUIPUI Short Circuil Duralion (Nole 3)

Operaling Temperalure Range:

±18V
500mW
±ISV
Indefinite

-SSOC 10 +12SoC.
-2SoC 10 +8SoC
O°C 10 +70°C
-6SoC 10 +T50°C'

102, 110
202,210
302.310

Storage Temperature ftange
lead Temperalure (Soldering, 10,ec)

300°c

ELECTRICAL CHARACTERISTICS 102/202/302 (Note 4)'
PARAMETER

CONDITIONS

MIN

LM102
TVP

Oll,el Vollage

2

Average Temperature Coefficient of
Ollsel Vollage

6

-

Input Current

10'·
RL:2; 10kn

0,999

OutPut Resistance
RL :2;8kn

±10

Supply Current.

3

10

7
10'·

10"
0,9996

0,999
2,5

±13

MIN

MAX
10

3,5

5,5

S

'15

II)

10"

10"

0,9995

1,000

0,8

2,5

0,9985

5,5

Positive SupplV Rejection"

sO

60

60

Negali.e Supply Rejecli.n

70

70

70

Offsel Vollage

TMIN:n

g
w
az

"''''
~@I

co!'

w-

......
t' :--ts;::,
-Rs=lM

100

~

Ul

!::!~
-'
«
::;;
-a:

"§

Ul

I-

Rs = lOOK

...

I-

Rs- 10K-"- I;f-

w

::>

a:

«
o

z
.1

"'

-15

-55

25

65

:iw

105

TEMPERATURE ('C)

-15

10
10

100

lk

::;;

10k

lOOk 1M

VOLTAGE GAIN'

VOLTAGE GAIN

270
225

...
:I:
~

Ul

z

r

135

0,999

w

90
45

~

0,99

0

0

>
lk

lOOk

10

Ul

Vs

.~w
w

I-

::>

I-

'"

T. = 25'C

0

T.

~

-'

-55'C

1

10k

lk

-

o·

II illllli

.1

lOOk

-55

1M

~

r

'"\

\

Vs = 11SV
T. = 25'C
DISTORTION

< 5%

10

6

60

~
w

40

a:

'"I-::>

>-

-'

'"'"::>

0

0
lOOk

1M

"i"'-

FREQUENCY (Hz)

Ul

25

65

105

V

IL

.".

"",

TA

Vs = ±15V

T. = 25'C

--

125'C

-.

T. = -55'C

"",
/

V 11.. = 300n"'"

_-15

~ilin

25

o

105

65

10

40

30

20

CURRENT (mA)

SUPPLY CURRENT
6

~~--~---,--~---,

80 r.::~~::;;t--;:T
70

z
;:
u

,

Ul

::>

a;
:!!
0

"§

RSA - ;:....-

/"'"

./

POWER SUPPL Y REJECTION
90

z

-I-

:;~

TEMPERATURE ('C)

LARGE SIGNAL FREQUENCY
RESPONSE

12

-15

POSITIVE OUTPUT SWING

115V

---....

FREQUENCY (Hz)

14

.....

0
>,

V OUT = 110V

iii
a:

T.=125"C

......

15

z
«
Ii;

,::>

"~«

TEMPERATURE ('C)

U

in

-

+15V

IVs2±5~

w

SYMMETRICAL OUTPUT
SWING

II

w

U

a:

t= V s ~ 0,9999 t:::::: t::::::

10

Vs-±15V

w

!

z

FREQUENCY (Hz)

OUTPUT RESISTANCE

§
z

i

;;

t~

0.999
-55

100

«
I-

~

Gl

Rs= 10k
t= 200 Hz-

1M

FREQUENCY (Hzl

,

4

(~s)

0,99999

r-T.,."",..--r-TTTrmr-rr-m""'"rT"TT11m

180 m

"

3
TIME

FREQUENCY (Hz)

~

"«

o

10M

;; 0.9999

;;:

\

II I

-10

VOLTAGE GAIN
0.99999

Vs= ±15V
T = 25'C

-5

0

::>

0

\

0

::>

~

~

g

I-

Z

50

Q

20

-'

10

::>

~

Vs = ±15V

Vs = ±5V

w

a:
a:

30

~

~~

i": ~

>-

'"'"

-....

Ul

0
10M

-10
100

o
lk

10k

lOOk

1M

10M

FREQUENCY (Hz)

°Note that optimum stability is obtained for a source resistance of 10 kn. For source resistances lower than 10
resistance in series with the input to .ensure adequate stability margin.

5·21

-55

.. 15

25

65

105

TEMPERATURE I'C)

kn. it is advisable to put additional

o~o!!:,

LM102,LM302,LM110,LM310
INCREASING NEGATIVE
SWING UNDER' LOAD

OFFSET BALANCING
R1
1~

OUTPUT
OUTPUT

R2·

INPUT

S.1K

v·Mav be added to reduce
internal dissipation.

APPLICATIONS

INSTRUMENTATION AMPLIFIER

SAMPLE AND HOLD

Your
OUTPUT

SAMPLE/HOLD
~ 0,01 "F POLYSTYRENE.

DEFINITION OF. TERMS

OFFSET VOL TAGE: The voltage at the output of the
amplifier with the input at zero .

put voltage to the change in output current with constant
input voltage.

.OFFSET VOL TAGE TEMPER1 TURE DRIFT: The average drift rate of offset voltage for a thermal variation from',
room temperature to the indicated temperature extreme,'

OUTPUT VOL TAGE SWING: The peak output voltage
swing, referred to zero, that can be obtained without the
large-signal voltage gain falling below the minimum specified
value.

INPUT CURRENT: The current into the. input of the
amplifier with the input at zero.
INPUT RESISTANCE: The ratio of the rated output voltage swing to the change in input current required to drive
the' output from zero to this voltage.
LARGE SIGNAL VOL TAGE GAIN: The ratio of the output voltage swing to the cliange in input voltage required
to drive the' output from zero to .this voltage.

SUPPL Y CURRENT: The current required from' the power
supply to operate the amplifier. with no load, anywhere
within its linear range.
POWER SUPPL Y REJECTION: The ratio of.the change in
input offset voltage to the change in power supply voltage
producing it.
SL.EW RATE: The internally-limited rate of change in
output voltage with a large-amplitude step function applied
to the input.

OUTPUT RESISTANCE: The ratio of the change in out-

5·22

LM105, LM305
Voltage Regulator
FEATURES
• Output current in excess of lOA possible by adding external resistor
• Direct, plug-in replacement for 100/300 giving improved
regulation

• Output voltage adjustable from 4.5V to 40V (105)
• DC line regulation guaranteed at 0.03%/V
• Load regulation better than 0.1 %

GENERAL DESCRIPTION

The I ntersil 105/305 can be used as either a I inear or
switching regulator circuit with output voltages greater than
4.5V. It features fast response to both load and line transients, and freedom from oscillations with varying resistive
and reactive loads. .

The Intersil 105/305 monolithic integrated circuit is a posi·
tive voltage regulator. It ·is a direct replacement for the
100/300 with an extra gain stage added for improved
regulation. In contrast to the 100/300, the 105/305 reo
quires no minimum load current while permitting higher
vbltage operation by reducing standby current drain.

PIN CONFIGURATIONS

SCHEMATIC DIAGRAM
r-=;--;----P--..--U"IREGULAHOIN"-I'

REGULATED OUTPUT
\

CURRENT LIMIT

BOOSTER OUlPUT

2

GROUND

(outline dwg TO-99)

NOTE: Pin 4 connected to case
F I~t Package

NO CONNECTION

NO CONNECnON

' .,

10

BOOSTER OUTPUT

2

9

CURRENT LIMIT

, UNREGULATED INPUT

3

8

REGULATED OUTPUT
COMPENSATION
FEEDBACK

GROUND·

1

~

6

REFERENCE BYPASS

TOP VIEW

(outline dwg FB) .
NOTE: Pin 4 connected to bottom of package

ORDERING INFORMATION
Part
number
LM105
LM305

TO-99
Can
LM105H*
. LM305H

10 pin
Flatpak
LM105F

Dice
LM105/D
LM305/D

• Add /883B to order number if 863B processing is desired.

5·23

LM105, LM305
. ABSOLUTE MAXIMUM RATINGS
105
I

305

50V
40V
500mW
:-55°C to +150°C
-65°C to +150°C·
300°C

Input Voltage
Input-Output Voltage Differential
Power Dissipation (Note 1)
Operating Junction Temperature Range
Storage Temperature Range
'
Lead Temperature (Soldering, 60 sec)

40V
40V
500mW
O°C to 70°C
-55°C to 125°C
3CXtC·

ELECTRICAL CHARACTERISTICS (Note 2)

CONDITIONS

PARAMETER

,.
105
TVP

MIN

MAX

MIN

305
. TYP

'MAX

Input Voltage Range

8.5

50

8.0

40

Output Voltage Range

4.5

40

4.5

30

Output-Input Voltage
Differential

3.0

30

3.0

30

UNITS
V

,

V
V

<:

,Load Regulation (Note 3) 0:::; 10
12 mA
Rsc = 18n, T A = 25°C
Rsc = lOn, TA = 125°C
Rsc = 18n, TA = -55°C
Rsc = 11m, T A = 70°C
Rsc =,18n, TA '= o°c
Line Regulation

VIN -

V 1N
Temperature Sta\lility

-

V OUT
Vou:r

::;

>

0.02
0.03
0.03

5V
5V

-:55°c,:::; T A ::; +125°C
O°C::; T A ::; 70°C

Feedback Sense Voltage
Output Noise Voltage
;

10 Hz::;f::; 10kHz
CREF = 0
CREF =0.1 jJF

Long Term Stability
Standby Current Drain

Ripple Rejection

V 1N
V 1N

=50V
= 40V

CREF

0.05
0.1
0.1

0.025
0.015

0.06
0.03

0.3

1.0

0_05

0.03
0.03

0.1
0.1

0.025
0.05

0.06
0.03

%/V
%!V

0.3

1.0

%
%

1.8

1.8

0.005
0.002

0.005
0.002

0.1

1.0

0.8

2.0

'

= 10jJF, f = 120 Hz

0.02

0.003

\ 0.01

%
%
%
%
%

V

\

%
%

0.1

1.0

%

0.8

2.0

mA
mA

0.003

0.01

%!V

NOTE 1: The maximum junction, temperature of the lOS is lSOoC, while that of the 30S is 8SoC. For 'operating at elevated temperatures
devices in the TO-S package must b.e derated based on a thermal resistance of lS0°C/W, junction to ambient or 4SoC/W, junction
to case. For the flat package. the derating is based on thermal resistance of 18S°,c/W when mounted on a 1/1S-inch-thick' epoxy
glass board with ten O.03-inch-wide. 2-ounce copper conductors. Peak dissipations to 'lW are allowable providing the diSSipation
rating is not exceeded wi!h the power averaged over a five second interval.
NOTE 2: These specifications apply for a junction temperature. between -,55°C and +l!!O"C, (105) o°C and 70"C. (30S) for input and output
voltag,s within the ranges given. and for a divider impedance seen by the feedback terminal of 2 kn, unless otherwise specified.
The load and line regulation specifications are for constant junction temperature. Temperature, drift eUects must be taken into
account separately when the unit is operating under conditions of high dissipation.
NOTE 3: The output currents given. as well as the load regulation.' can be increased by the addition of external transistors: The improve,ment
factor wi II be roughly equal to the composite current gain of the added transistors .

.

5-24

LM105, LM305
TYPICAL PERFORMANCE CHARACTERISTICS FOR 105,305*
CURRENT LIMITING
CHARACTERISTICS

LOAD REGULATION

~
z
o

0

-......

:=:.:::

~

~ -0.01
o
w
to

~ -0.02

-". .

11'1~'C
:.,-~-

...J

o
>

5 -0.03
....Q.
o

J Asc =0
l--l-.

1·,J
"

-5~'~

,

I I

::>

-0.04

o

10

15

o

~

5

1 I
1 I I!

-0.06

>

....
ir
....::>
o

Tj

'

,

-0.08

o

10

0.5

....

zw

~5mA

E.
....z

0.4

a:
a:

::>
u

r-...,
........

u
a:

"r-...,

0.3

"

a~

2.6

20

z
«
....

in
w
a:

2.4

-so -25

w
u
en

U
~

10

en
0.2
-75

0

25 50 75 100 125 150

~
./ ~

V

7.0

-75 -50 -25 0

25 SO 75100 125 150

'"«
....

~
12

....

V

J

".................. - ,....'

IL • 20 rnA

...;;~

ILI= lOrnA

1-"': r--

::>
Q.

11
-75 -50 -25

25 SO· 75 100 125

TEMPERATURE ('C)

'....«"

V

...J

>

....::>
....
!)

3,5

Q.

0

3.0

2.5
-75

,. V
-so

./

V

-25 0

/

w

a:
a:

::>
<.>

V

/'

>
ID

t- V'

0

z

«
....
en
25

so

0.9

~.

~ ...

25'C

l-

....

75 100 125

10

'305 only guaranteed oOC 5 T A 570°C, VIN

20

30

40

= 40V

max, VOUT

= 30V max.
5·25

~

;;
w

o

40

so

20

-40

125'C

o

~

>

....

::>

400

-

~

..

~VIN

= 5V

Vou> -10V
Rsc = 100
IFl=20mA

.... CL -1 IlF

....

0

INL '" 1.0 rnA

Vau> - 10V

....-.!- .. ...l ...
LOAD

,

::>

.0 -400

o

'"

,

Rsc' 100

- C L =0

~
50

I

1
LlNEI

'0

w

~

I

INPUT VOLTAGE (V)

o

I
I-'~--

0.8

10

TRANSIENT RESPONSE

tz

I

TEMPERATURE ('C)

.

-

-.1 _Ll

5

1

INPUT OUTPUT VOLTAGE DIFFERENTIAL (V)

;-r'

./

1.0

Ct • f = 10p:F
f >120 Hz

~ 0.001

-J5'C

,"

r--

~ 0.002

I

1.1

Vau> = 10V
TA • 25'C

0

~ 0.005

75 100 125

-;(

E.
....
z

==

'I

.,«

STANDBY .CURRENT DRAIN

/

Cr.'

Q.
Q.

1.2

4.5

4.0

0.1

z 0.05
0
;::

TEMPERATURE' ('C)

MINIMUM OUTPUT
VOLTAGE

0

25 SO

:;
~

>

J
0

"""

20

o

-1_1

!!:

0

10

u
w 0.02
;;J
a:
w 0.01

I

Il :::SmA

~

:::::::::

SUPPLY VOLTAGE
REJECTION.

Vau> '10V _
Rsc • 100

>

Q.

w

f""

OUTPUT VOLTAGE

13

0

!!:

-so -25

R2

~

5

REGULATOR DROPOUT
VOLTAGE

w

50

2.8

JUNCTION TEMPERATURE ('C)

...J

t.,...-

6.0
-75

40

RlIR2 = 2 KU
Rl=1. 11V ouT

2.2

"'--+--+-+-I-+--+-+=t.....;)

~

w

....::>

30

2.0

Vau >' 4.5V

>

,

3.0

30

....a:

•

20

OPTIMUM DIVIDER
RESISTANCE VALUES

....

:;

t-.....

8.0

...J

10

OUTPUT CURRENT (rnA)

40

MINIMUM INPUT VOLTAGE

0

.l.

o

;(

JUNCTION TEMPERATURE ('C)

«
....'"

Rsc = 1001
....--r--tl--t-!HI-t

a:'

SHORT CIRCUIT CURRENT

a:
a:

a

g

T j = 125'C

1 = lSO'C TI 1-+-+-+-+-+--i
0.2
'I I I !

w

40

30

w

........

:E

::;

lt-

=Tt ',li 5' C

I -

0.4

LOAD CURRENT (rnA)

~t-....

Z

....

j

Q.

3.2
la

w
en
~

I
I'" T =25'C
....::> 0.6 H-t--t1rl--H
IH,-'r-,rl
....::>
o
>

20

.Ll J
1-+-+-+
11".1I-+'l-'t-V-+-i

1.0

T j • -55'C --,-;
0.8 t--t-t--'-'..1;"'-"'-'-1r-+-t---t--I

~

,W

i

~

~

o
>

0.6

w

>

.
.

-0.1

20

CURRENT LIMIT SENSE
VOLTAGE

~
o~

11= _515'C

1'-. '

1\
II

lsri,c!I \

LOAD CURRENT (rnA)

~

....

.~
w

~ ~

~
T j = 25°C----

w -0.04

'"~

Rsc • 100

-....
'"':'
'. \

~ -0.02

>
w
o

T j = 25'C

TI.

~
z
;::

o

10

~

20
TIME (Il')

~

1
30

U~UIb

LM1'05, LM305
,TYPICAL APPlICATIONS*
1~OA Regulator with Protective Diodes

10A 'Regulator with Foldback Current Limiting

...

UT._
r-_-......,-~---.,.--:f"'.,.-v.u,-:av

D"

UT....

v...
:t:-t:::---2V to ±20V. The amplifiers may· be
frequency compensated with a single external capacitor. The
LM108Aand LM308Aare high performance selections from the
108/308 amplifier family.

Input Bias Current - 2 nA max to 7 nA max
Input Offset Current - 0.2 nA max to 1 nA max
Input Offset Voltage -0.5 mV max to 7.5 mV max
t:Nos/!::.T - 5ILVrC to 30 ILvrc'
.
!::.Ios/!::.T - 2.5 pArC to 10 pArC
Pin for Pin Replacement for 101A/301A

PIN CONFIGURATIONS
DUAL·IN·LlNE PACKAGE

FREO C O M P . A 8 FREO COMP B
-IN
V+.

OUT

+IN
V-

.

. NC
INVERTING INPUT 4

(outline dwg PAl

NON.I~~~~TING

5

TOP VIEW

(outline dwg JD)

BAUCOMP

COMP

-IN

v·

+IN

OUT

V-

BAL

TOP VIEW

(outline dwg FB-1)

(outline dwg TO-99)

ORDERING INFORMATION
Part
number

T0-99
Can

8pin
MiniDIP

14 pin
CERDIP

10 pin
Flatpak

Dice

LM10BA
LM308A

LM108AH*
LM308AH

LM308AN

LM108AJ
LM308AJ

LM10BAF
LM308AF

LM108A1D
LM308A1D

LM108
LM308

LM108H*
LM308H

L~308N

LM10BJ
LM30BJ

LM1D8F
LM308F

LM108/D
LM308/D

*If 8838 processin,g is desired add 18838 to order number.
5·29

LM108/A, LM308/A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
108,I08A
3011,308A
Internal PowerDissipation (Note I)
Metal Can (TO-99
.
DIP
Differential Input Current (Note 2)
Input Voltage (Note 3)

500mW
SOOmW
±IOmA
±15V

ELECTRICAL CHARACTERISTICS (T A
PARAMETER

Indefinite
Output Short-CircuitDuration
Operating TemperatureRa!lge
-55'C to +125'C
108,l08A
O'Cto +70'C
308,308A
~65'C io + 150'C
Storage TemperatureRange
300'C
Lead Temperature (Soldering, 60 sec.)

±20V
±18V

=

25°C

unless otherwise specified)· (Note 4)
,

308

CONDITIONS
MIN

108

308A

TYP . MAX

MIN

TYP

MAX

MIN

l08A

TYP

MAX

MIN

TYP

UNITS
MAX

Input Offset Voltage

2.0

7.5

0.3

0.7

2.0

0.3

0.5

mV

Input Offset Current

0.2

1.0

0.2 _ 1.0

0.05

0.2

0.05 0.2

nA

Input Bias Current

1.5

7

1.5

0.8

2.0

0.8

2.0

nA

10

Input Resistance
Supply Current

Vs = ±20V
Vs = ±15V

Large Signal
Voltage Gain

Vs'; ±15V, V OUT = ±10V,
RL:2! 10 kl!

40

10

0.5

7

40

30

0.3
0.3
25

O.B

300

0.3
BO

30

70
0.6

Ml!

70
0.3

0.6

\.

0.8

300

50

300

80

rnA
rnA
VIm V

300

THE FOLLOWING SPECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES
Input Offset Voltage

10

,

Input Offset Current

1.5

Average Temperature'
Coefficient of Input
Offset Voltage

6.0

30

1.0

Average Temperature
Coefficient of I.nput
Offset Current

2

10

2.0

'10

Input Bias Current
Large Si9nal
Voltage Gain

Vs = ±15V, VOUT' = ±10V,
R L ;:" 10kl!

Input Voltage .Range

V~ = ±15V

0.73

3.0

1.0

mY'

1.5

0,4

0.4

nA

1.0

5.0

jJ.V/'C

0.5

2.5

pAtC

3.0

nA

5.0

3.0

10

0.5

15

2.5

3.0

10

15

60

25

40

±13.5

±13.5

±13.5

±13.5

V/mV
V

Common Mode
Rejection ,Ratio

BO

100

96

110

B5

100

96

110

dB

SuPPlY Voltage

BO

96

96

110

BO

96

96

110

dB

±13

±14

±13

±14

±13

±14

±13

±14

Rejection Ratio

Output Voltage Swing
Supply Current

Vs = ±15V, RL = 10·kl!
TA.= +125'C, Vs '= ±20V

0.15

0.4

0.15

NOTE 1: Derate Metal Can package at 6,8 mWrC for operation at ambient temperatures above 75° C and the Dual ·In-Line package at
9 mwr C for operation at ambient temperatures above 95° C.
.
NOTE 2: The-inputs are shunted with back-la-back diodes for over-voltage protection. Therefore. excessive current will flow if a differential
input voltage in exCe~s of 1V is applied between the inputs unless some limiting re~istance is used,.

NOTE 3: For supply voltages less than':t15V, the maximum input voltage is equal to the supply voltage.

NOTE 4:

Unless otherwise specified. these specifications apply for supply vottagesfrom ::!:5V to ::!:2OVforthe 108, and 108Aand
::!:5V to ±15V for the 308 and 308A.

5·30 .

.

V
0.4

rnA·

U~DI1

LM10S/A, LM30S/A
TYPICAL PERFORMANCE CURVES
INPUT CURRENTS
2.0
1.5

:it

..s

30Lo~A~IAL

'kl

1.0

108A/lOB

""a:Zw 0.5<,..

MAXIMUM DRIFT ERROR
lk

'

.......
t- .......... ,....

.......

e.>
"" 0.20

r--..

::J

~0.15

1-108
I
308

o

I::J

a:
a:
a:

--

t:

o

~

308A

~ 108/108A:

OiFS!T
1.0

-55-35-15 5 25 45· 6585105125

-55 C <

t- 308/308A:
lOOk

TEMPERATURE I"C)

r-

~ • < 125"C

O"C';:T A ';: 70"C

1M

100M

10M

-

11'

o

f-

~ I""'"

I-

~ 1.0
Z

f= IOB/I08A:

""~

I-

108A

-55"C';:

r:- 308/308A:

..J

;; 0.1
:;
lOOk

+..,;:

125°C

O·C ,;: T A';: 70·C

1M·

10M

100M

INPUT RESISTANCE In)

INPUT NOISE VOLTAGE

VOLTAGE GAIN

1000

120

I I

3681• t-3~8A

ow

INPU'T RESISTANCE (n!

POWER SUPPLY REJECTION

I

~ 10

w
~
108A

1-'

10

a:
o

..J

o

~

7

=:1.

~fo =:/

w

108A/l08

0.10

~,~I

<:J

I-

13
~'00

a: 0.25

308/308A OF FSE T

MAXIMUM OFFSET ERROR

.s'00
w
£

80

Z

0

>=
e.> 60
~
w
a: 40

a

Rs = lOOk

Z
I-

>-

..J
0..
0..

Rs= 1M

~ 100

20

Rs~ 0

40

:l

0..

~

::J

en

0
-20

10
lk

100

10k

lOOk

1M

10M

10

-

~
<:J

10

Z

3:
en

""
0""

::J
0..

~\

\

T A = 125°C
I
I:'"
TA = 70"C

TA 1=

:it 500

a;
:!! 80

~400
w

Z

~

I..J

o

it
::J

o

>

en 100

--

It

10

§

r

10'

Z

C§

101

~

10·

~." = 1000. C, = 30 pF

::J

'

10-'
100

lk

10k

10

\

8

~Z

lOOk

FREQUENCY 1Hz)

1M

Z

10M

~

3:
en
I-

C, = 3pF

::J
0..

g

~

VOLTAGE FOLLOWER
PULSE RESPONSE

1\

I-

lOUT = ±1 mA
Vs = ±lSV

'--'
10

f,

,

Av = 1,
= 3~ pF
i T A = 25"C

/

:=
glO-'

,

~

45

4

cr,i~

o
lk

6
4
1

~ -2
~ -4
o
.> -6

-

.r-- ..... ~

-- .-r r-

f-,-

\

INPUT

\

I

I i\

J
\1..'

0yTP~T

I

.-

T A = 25·C
Vs=±lSV
C, = 30 pF.

-8
-10

10k

lOOk

FREQUENCY (Hzl

5·31

1M

o

40

o

10k lOOk 1M 10M

LARGE SIGNAL.
FREQUENCY RESPONSE

Vs = ±lSV

80
TIME

120
I~s)·

:J
w

GAIN
PHASE ___:+1C, = 30 pFF.2l:
lk

135i
:!!
<:J

_~C,=I00PF

100

180 .

90

~

FREQUENCY (Hz)"

<:J

y~v, = 1000.
, C,=, (JpF

W
0..

",

SUPPLY VOLTAGE I±V)

~ 12

/

'ItI-

....v

r- r--)C' = 3 pF

10

TA = 25°C

/

"\\j f\

w
e.>

l00p~\

~,-30PF~

'-

20

15

. 16

:1.~'

"'
."'-

C,=

-20

OUTPUT CURRENT (±mAI

10"

20

o

o

CLOSED LOOP
OUTPUT IMPEDENCE

~,=~pF_

60

~ 40

~200

c!-

-~50C'I

"" ""'-

w

e.>

I I- II

0

120
100

a:
~300

TA=O"C~

::J

600

3

TAI=2~"CL

5

OPEN LOOP
FREQUENCY RESPONSE

Vs = ±15V

I-......

20

SUPPLY VOLTAGE (±V)

SUPPLY CURRENT

..

15

10

FREQUENCY 1Hz) .

OUTPUT SWING

"- ............

90
lOOk

10k

lk

.100

FREQUENCY (Hz)

15

C,=O
1= 100Hz

I

160

iE

LM10S/A, LM30S/A
GUARDING
Extra care must be taken in the assembly ot' printed circuit
boards to take full advantage of the low input currents of
the ,lOa amplifhn. Boards must be thoroughly cleaned with'
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or
silicone, rubber to prevent. contamination.,
Even with properly cleaned and coated boaros, leakage
currents, may cause trouble at 125°C, particularly, since the
input pins are adjacent to pins that are at supply potentials.
This leakage can be significantly reduced by using guarding
to lower the' voltage difference between the inputs and
adjacent metal runs. Input guarding of the a-lead TO-99

package isaccom'plished by using a 10-1eadpin circle, with
the leads of the device formed so that the holes adjacent
to the inputs'are empty when it is inserted in the board. The
guard,' which is a conductive ring surrounding the inputs,
is connected to a low impedance point that is at approximately the ,same voltage at the inputs. leakage currents
.from high-voltage pins are' then absorbed by the guard.
The pin configuration of the dual in-line package is designed
to facilitate guarding, since the pins adjacent to the inputs
are not used (this is different from the standard 741 and
lOlA pin configuration}.

FREOUENCY COMPENSATION CIRCUITS
ALTERNATE CIRCUIT: IMPROVES REJECTION OF
POWER SUPpLY NOISE BY A FACTOR OF TEN.

STANDARD CIRCUIT

",

",

OUTPUT

OUTPUT
NON

INve~~~~~ o-..JY"\,i\3~--1

C.~CO(l!~)

c,

Co'" JOpf

5-32

LM111, LM311
Precision Voltage Comparators

D~OIL

FEATURES

GENERAL DESCRIPTION

e
•
•
•
•
•

The LM 111 Series comparators are designed for precision
applications where the input and·output characteristics of
710 and 106 high speed comparators are not adequate for
low level signal detection and high level output drive capability. They ar.e design-ed to operate from supplies up to
±18V and single supplies down to +5V. The output is
capable of driving TTL, RTL, DTL as well as MaS and
lamps or relays_ I nput offset voltage balancing and TTL
strobe capability are provided. Outputs can be wire OWed.

Differential I nput Voltage Range- ±30V
Input Common Mode Voltage Range - ±14V
Operating Power Supplies +5V to ±18V
I nput Offset Cu rrent - 20 nA max
Input Offset Voltage - 3 mV max·
Output Flexibility - 35V; 50 mA;
T2L Compatible
• Strobed Output & I nput Offset Adjustable

. Switching speeds to TTL logic levels are typically 250 ns.

PIN CONFIGURATIONS
METAL CAN

FLAT PACKAGE

OVAL-iN· LiNE

v'
v'
OUTPUT GROUND

2

:: ::

NC
BALANCE,
STROBE

11

BALANCE

(outline dwg FB)

NOTE. Pin 4, connected to case

NOTE

-

,.

Pm,6 connected to bottom 01 package
TOP VIEW

(outline dwg TO-99)

(outline dwg JD)

ORDERING INFORMATION
TO-9S
Can

10 pin
Flatpak

14 pin
CER DIP

LM111

LM111H*

LM111F

LM111J'

LM311

LM311H·

LM311F

LM311J

8 pin
Plastic DIP

LM31fN

• Add 18838 to order number if 8838 processing is desired.

5-33

STROBE
BALANCE

V-

B BALANCEI
STROBE

7

TOP VIEW

Part
number

:~:UT

(outline dwg PAl

Pin 5 connected 10 bottom of package
TOP VIEW

v'

8

10 NC

BALANCE
NOTE

GRO~:Z

14 pin
Plastic DIP

Dice

LM311N-14

LM111/D
LM311/D

O~OIl

LM111, LM311
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage
Output to Negative Supply Voltage

36V
LM Ill,
LM311

Ground to Negative Supply Voltage
Differential I nput Voltage
Input Voltage (Note 1)
Power Dissipation (Note 2)
Output Short Circuit Duration
Operating Temperature Range LMlll·
LM311
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

SOV
40V
30V
±30V
'±15V

SOOmW.
10 sec

-55°C to +125°C
O°C to +70oC

-65°C to +150°C'
joo°C

ELECTRICAL CHARACTERISTICS (Note 3)
PARAMETER
In'put Offset Voltage (NoteA)

LM311

LM111

CONDITIONS

MIN

T A = 25°C, Rs ~ 50k

,

TYP

MAX

0.7

3.0

~.O

MIN

TYP

MAX

2.0

7.5

UNI.TS
mV
nA'

Input Offset Current (Note 4)

TA = 25°C

I nput Bias Current

TA = 25°C

60

Voltage Gain

TA = 25°C

200

200

V/mV

Response Time (Note 5)

TA = 25°C

200

200

ns

Saturation Voltage

TA = 25°C

Y,N

6.0
.100

0.75

TA = 25°C

Output Leakage Current

T A = 25°C

0.75

0.2

4)

nA

10

mV

70

nA

300

nA

4.0

.

20
150

Input Voltage Rang'e
Saturation Voltage'

50

0.2

Rs~ 50k

Input Bias Current

mA

10

Y,N ~ 10 mV, V OUT = 35V

Input Offset Current (Note 4)

±14

±14

V+~ 4.5V,Vc = 0

..
0:23

0.4

0.1

0.5

V'N~-10mV,lsINK~8mA

~ 5 mV, VOU~. =

0.23

TA = 25°C

·5.1

6.0

5.1

7.5

Negative Supply Current

TA = 25°C

4.1

5.0

4.1

5.0

35V

V

0.4

Output Leakage Cu~rent
(Note 6)
Positive Su pply Current

Y,N

V

I

,

;

V'N~-6mV,lsINK~8mA

V

1.5

3.0'

3.0

Y'N ~ 5 mV, V OUT = 35V

Input Offset Voltage (Note

nA

1.5

< -.10 mv, lOUT = 50 mA

Strobe on Current

50
250

\

Y'N ~ -5 mV, lOUT =' 50 mA

..

10·
100

IlA

,

mA
mA

.NOTE 1: This rating applies for ± 15V supplies. The positive input voltage limit is 30Vabove the negative supply. The negative input voltage limit is equal to the
negative supply voltage or 30V below the positive supply, whichever is less.
NOTE 2: Th~ maximum junction temperatu~e ofthe 111 is 150"C, while that of the 3,., is 85°C. For operating at elevated temperatures, devices in the TO-5
package must be derated based on a thermal resistance of 150"CMI. junction to ambient, or 45°CMI. junction to case. For the flat package, the derating is based
on a thermal resistance of 185°CMI. when mounted on a 111S-inch-thick epoxy glass board with ten, 0.03,inch-wide, 2-ounce copper conductor. The thermal
resistance of the dual-in-line package is 100"CMI. junction to ambient.
NOte 3: These specifications apply for V. = ±16Vand over the operating temperature range, unless otherwise stated. The offset voltage, offset ament and
bias current specifications apply for.any supply voltage from a single 5V supply up to ± 15 supplies.
.
NOTE 4: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 rnA load.
Thus, these parameters define an error band and take into account the worst case effects of,voltage gain and input impedance.
NOTE 5: The response time specified (see definitions) is for a 100 mV input step with 5 mVoverdrive,
NOTE 6: This'specification applies.for Pin 1 -15V. Pin 7 ~20V.
'
5-34

LM111, LM311
TYPICAL PERFORMANCE
INPUT OFFSET
INPUT BIAS CURRENT 111

CURRENT 111

±15V

Vs

:;;

;:: 300

z

RAISED- I--

W

f-vs - ±15V

1....

~

1"-

::>

200

u

r--..

Vl

"'

..... ....... RAISED

ffi

10

(;

~ 100

~

~

-

i"" f- NORMAL........

....

NORMAL- I--

v

20 I'\.

'"'"

'"

i3'"
:::

OFFSET ERROR 11'

30

400

r--.!.

Z

o
-55 -35-15 5

-55 -35 -15 5

25 45 65 85 105 125

TEMPERATURE lOCI

TEMPERATURE lOCI

20
/

RAISED_

....

1"'-_

zW

:;: 300
::>
u
Vl

«

iii

1....

r-

-

:;;

0

NORMAL

10

20

30

40

50

(;
NORMAL

W

Vl

100

"'
....

75

:::

ir
~

10

20

30

40

50

60

70

80

"=OJ

/

- -0.5 -

i:'
~ -1,0

.,

/
t - SUPPL Y VOLTAGES_

10M

:;;;

z

o

8

25
-4

0

'4

12,16

8

/

20~V
I

~l

J. II

II'

5mV
2 :"vf,

l.

0

/

i---"

0.2

-55 -35 -15 5

.... E 100

~A =1 25°IC-

20r~

I I I

2';'V

~ ~ 50

5 mV

:;
E

, V'o'

::> '"

>
0.4

0.6

0.8

/I
/I

~~~:~e;ER \.

-1

-.5

.5

OUTPUT SATURATION
VOL TAGE

TA - 2SoC

~,0.7
W

~0.6
0.5

V

>
z 0.4

I-'

./
./

o

~0.3

Vs '= ±15V[A =/25'1_

2'" 0.2
«
V>

0.4

0.6

0.8

1/

0.1

o
0.2

\.
I '\

10
/

....
;5

-50

o

'\

OUTPUT
R, = 600n

0.8

Pt

o

0.2

20

0

= ,1k

DIFFERENTIAL INPUT VOLTAGE ImVI

v ; [ > i = VOUl
n

~ ~ -100

o

~
....
::>

sv

1\

.... W

0

30

....

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES,

~s=' ±1~V-

"= :

a
>

25 45 65 85 105125

1

vp1-=n

::>w

'"«....

40

TEMPERATURE rCI

/

5V

RL

V- = 40V

W

- -

0.4

:;;;

50

Vs = 30V
TA=2SoC- f- NORMAL OUTPUT

50

.J

g -1.5
:;;;

-8

~

-

'W

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES

>

1M

TRANSFER FUNCTION

/

I--~EFIER~EDITO

DIFFERENTIAL INPUT VOLTAGE IVI

o

lOOk

INPUT RESISTANCE Inl

COMMON MODE LIMITS

V-

-:;

10k

a

w

TEMPERATURE I'CI

:;

-16 -12

>

Vos/71IYOS + Rs10s

.J

60

'"~ \125
u

TYPICAL

z

80

~2oo

175

,I

«

INPUT CHARACTERISTICS

150

/

,

10

~
z

225

~

t-MAXIM~M

....

TEMPERATURE lOCI

t5

25"C

TA

....

~

70

10M

1M

OFFSET ERROR 311

>

~

60

lOOk

INPUT RESISTANCE I.(J)

a

o
o

Rslos

IIII
10k

....W

....

.

~ 100

t-+-Imtttlt-+vOS~IVOS+
0.1

>

:;'

,-

u.

....

RAISED

i"- t-

:;'

>
:;
a

'":;«

u 10

200

:;;

«

W

/

......

....

.J

E 100

~S=±15

........

'"'"
::>
t;;

::>

'"

."

~

W

INPUT OFFSET CURRENT 311

INPUT BIAS CURRENT 31 1
500
Vs'" ±15V
~
:. 400 ~t---:.

25 45 65 85 105125

~

o

10

'20

30

40

OUTPUT CURRENT ImAI

5·35

50

~M1_11,

LM311

TYPICAL PER FORMANCE (Cont)
RESPONSE TIME FOR VARIOUSINPUT OVERDRIVES
'

RESPONSE TIME FOR,VARIOUS
INPUT OVERDRIVES

OUTPUT LiMITING
CHARACTERISTICS
140

;;;

15
10

~~

5

1--

20 ",V

IL

0 2 ",',
-5

.~ ~

'? B

~" 2' '_

v" -

V

;;; -15

, 'I

\l

5;;:'-

_

VO
",-

> -10

E

-

v'

L

5 ",V

, '-

,~ = 1'15~-,
IS,

-50

"''''
~ ~ -100

I

o-'
>

jA

~25'E~

0

.4
TIME

10

1-;;:'::0",

5

1':..:
::01-

0
-5

06
>

,VSI= '115V
Ty2rC

t-J s =

,

a: 40

U

ffi

6

>-

0

I

0
20

25

30

......
...... "'"

UT

III

~Vs- '15V
I-OUTPUT V OUT =

;: 10. 8

paSITIVE SUPPLY ~UTPUT LOW

~

(tl 1j

::0

1

LEAKAGE CURRENTS I I 1/21 I

la'
;(

......

I

I

-55 -35 -15 5,

SUPPL Y VOLTAGE IVI

-~

r-

1 1-:-l - I-

l

IS

10,
OUTPUT VaLTAGE IVI

POSITIVE AND ~
NEGATIVE SUPPLY -'.~

~

""-

""-

SHORTCIRCUIT t--CU'RRENT t---

a: 20
0

;15~

.......

-

......

/

I-

III

8

a:
a:
OJ
u

w

15

60

u

.-L-

L

,\.
~ ./

SUPPLY CURRENT

a:
a: 3
::>
u'
~ 2

10

-H-

100

a:
~ '80
u

0

j

0

ffi

. POW ER----:
DISSIPA TlO~

J:

I I

>

I-

m

r-l-

120

I-

:;

o-'

4

III

.5

I-

~

\

;;; -IS
I- .5 100
::Ow
a.. <.!J 50
~ ~ 0

11(:

1\

0,7

TA = 25 C

;(

TIME Ipsi

oS

::>

_

Cl.

l~sl

;( 5

z

V'~w'

!l..

2mV

, 10

I-

'~

~~

\
20~~ 1\
\
5mV

-10

SUPPLY CURRENT

/

V'

IS

:;

I

25 45 65 85105125

TEMPERATURE I'CI

soy

~

z

w

a:
a:

a10.
..:
'"~ 10"

r

./

9

w

~PUTV'N

0

w
-'

10 '

15V

, ......
25

45

65

85

105

125

HMPERATURE I CI

LEAKAGE CURRENTS 31,1
'I=V S'-'15V

5

VOL TAGE GAIN: The ratio of the change in autput
voltage ta the change in voltage between th~ input ter'minals,
producing it.
.

t-0~TPUT V OUT " ' /

I-

~ 10- 9

a:
a:

::>

RESPONSE TIME: The interval between the application
, of an input step function and the time when the output
, crosses the logic threshold voltage. The input step drives
the comparator from .some initial, saturilti!d input voltage
to an. input level just barely in excess of that ~equired ta
bring the output from saturation to tlie logic threshold
voltage. This excess is 'referred to as the voltage overdrive.

,U

w

~

'"~

10- 1 O~ =INPUT V,. ='15~

-'

10"

,~"
~

--

~

g

~

TEMPERATUR~

~

~

M

lOCI

SA TURA TION VOL TAGE: The low output 'voltage level
with the input drive equal to or greater. than a specified
value.

DEFINITION OF TERMS
INPUT OFFSET VeJL TAGE: The voltage between the
input terminals required to make the autput voltage greater
than or less than specified voltages. . ,

STROBE ON CURRENT: The current that must be drawn
out of the strobe termi(lal to disable the comparator.

INPUT OFFSET CURRENT: The difference between the'
two input currents for which· the outp_ut will be driven'
higher than or lower than specified .voltages.

OUTPUT LEAKAGE CURRENT: The current into the
output terminal with a specified output voltage relative
to the ground pin and the input drive equal to or greater
than a givel1 value.

INPUT BIAS CUR·RENT:. The average of the
currents.,

t~o

input

·INPUT VOL TAGE RANGE:. The range of voltage on the
input terminals (common mode) aver whiCh the offset
specifications apply.

SUPPL Y CURRENT:, The current required from the, posi·
tive or negative supply to operate the c;omparator with no
output load. The power will .vary with input voltage, but is
specified as a m~xil'1lum for the entire range of input voltage
conditions ..
5·36

LM111,LM311
TYPICAL APPLICATIONS

TTL COMPATIBLE OUTPUT SWING

HIGH LEVEL TTL COMPATIBLE
OUTPUT SWING

MOS LOGIC COMPATIBLE
OUTPUT SWING

.,5V
'5V
.5V
1K

YOU!

VUUl

-lOY

OBTAINING ± 15 VOLT OUTPUT SWI NG

DRIVING GROUND·REFERRED LOAD

USING CLAMP DIODES TO
IMPROVE RESPONSE

v'

+15V

FROM
LADOE R4~-------4
INVERTING I P'

NETWORK
7

02

V OU1

TTL
OUTPUT

01
LAMP

15V

'------+---ANALOG INPUT

'INPUT POLARITY REVERSED WHEN USING PIN 1 AS OUTPUT

OFFSET BALANCING

. STROBING

INCREASING INPUT STAGE SLEW RATE'

:B=

R2
3K

V·

. •. 5
2
'.

6

.

8- 7

3

'IN'CREASES TYPICAL COMMON
MODE SLEW FROM 7.0V/!'s TO 18V/!'s

5-37

~
a

D~DlL

LM124/324
Low Power Quad Operational Amplifiers

FEATURES

GENERAL DESCRIPTION

• Internally frequency compensated for unity gain

The LM124 series cOnsists of four independent, high
gain, internally frequency compensated operational
amplifiers which were designed specifically to operate
from a single power supply over a wide range of voltages.
.operation from split power supplies is also possible and
the low power supply current drain is independent of the
magnitude of the power supply voltage.

• Large DC voltage gain

100dB

• Wide bandwidth (unity gain)
(temperature compensated)

1MHz

• Wide power supply range:
Single supply
or dual supplies

3V to 30V
±1.SV to ±1SV

,

Application areas include transducer amplifiers, dc
gain blocks and all the conventional op amp circuits
which now can b'e more easily implemented in single
power supply systems. For example, the LM124 series
can be directly operated off of the standard +5V power
supply voltage which is used in digital systems and will
easily provide the required interface electronics without ~equiring the additional ±15V power supplies.
,
In the linear mode the input common-mode voltage
range includes ground, and the output voltage can also
swing to ground, even though operated from only a
single power supply'voltage.

• Very low supply current drain (800/-LA) - essentially
independent of supply voltage (1mW/op amp at
+SV)
4SnA

• Low input biasing current
(temperature compensated)

2mV
SnA

• Low input offset
and offset current

• Input common-mode voltage range includes ground

13:

Differential input voltage range equal to the power
supply voltage
Large output voltage swing

OV to V+ - 1.SV

The unity gain cross frequency is temperature compensated, as is the input bias current..

SCHEMATIC DIAGRAM (Each Amplifier)

PIN CONFIGURATION (outline dwgs JO, PO)
OUT.

-;IN.

+IN.

v-

+IN3

-IN3

OUT~

OUT,

-IN,

+IN,

V·

+IN~

-IN2

·OUT2

CHIP CONFIGURATION

ORDERING INFORMATION
Part
Number
LM124
LM324

Dice

14 Pin
CERDIP

14 Pin
Plastic Dip

LM124/D
LM324/D

LM124J'
LM324.i

LM324 N-14

Temper~ture

Range
- 55'C to + 125'C
O'C to +70'C

~
• Add /8838 to order number if 8838 processing is desired,

OUT,

,

OUT,
CHIP DIMENSION 56 x 61 MILS

5·38

n~OlL

LM1241324
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, v'
Differential Input Voltage
Input Voltage
Power Dissipation (Note 1)
Plastic
CERDIP
Output Short-Circuit to GND (One Amplifier) (Note 2)
V' ,;15 and T, = 25'C

Input Current (V," < -0.3 VoJ, (Note 3)

32Vor ±16V
, 32V
-0.3V to +32V

50 mA

Operating Temperature Range
LM324
LM124
Storage Temperature Range

570 mW
900 mW
Continuous

O'C to +70'C
- 55'C to + 125'C
-65'C to +150'C
300'C

Lead Temperature (Soldering, 10 seconds)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V+ =+5,QV, Note 4)
PARAMETER
Input Offset Voltage
Input Bias Current
(Note 6)
Input Offset Current
Input Common-Mode
Voltage Range (Note 7)

Supply Current

Large Signal Voltage
Gain
Output Voltage Swing
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Amplifier-to-Amplifier
Coupling (Note 8)
Output Current
Source

Sink

Short Circuit to Ground
Short Circuit to V+
Input Offset Voltage
Input Offset Voltage
Drift
Input Offset Current
Input Offset Current
Drift
Input Bias Current
Input Common-Mode
Voltage Range (Note 7)
. Large Signal Voltage
Gain

CONDITIONS

MIN

T, = 25'C, (Note 5)
IIN!+)

or

IINH TA

=

IIN(+} -IINH' TA -

LM124
TYP

MAX

MIN

LM324
TYP

MAX

UNITS

±2

±5

±2

±7

25°C

45

150

45

250

nA

25°C

±3

±30

±5

±50

nA

0

V' = 30V, T, = 25'C
R, - x Vee = 30V, (LM2902 Vee - 26C)
R, = x On All Op Amps
Over Full Temperature Range
T, = 25'C
V+ =15V (For Large Va Swing)
R, '" 2kn, T, = 25'C
R, - i!kn, T, - 25'C (LM2902 R, '" 10kn)

V'-1.5
1.5
0.7

0
1.5
0.7

3
1.2

mV

V+-'1.5

V

3
1.2

mA
mA
rnA

50

100

25
V+-l.5

0

100

V/mV
V+~1.5

0

V

DC, T, = 25'C

70

85

65

70

dB

DC, T, = 25'C

65

100

65

100

dB

-120

dB

f - 1kHz to 20kHz, T, - 25'C
(Input Referred)

-120

VIN + = 1V. V1N _ = av,
V- = 15V, T, = 25'C

20

40

20

40

mA

V1N _ = 1V, VIN = av,
V' = 15V, T, = 25'C

10

20

10

20

mA

V1N _

12

50

12

50

/LA

=

1V, VUH

=

OV,

T, = 25'C, Va = 200mV
T, = 25'C, (Note 2)

40
20

(Note 5)
Rs = on

60
40
±7

40
20

7

7
±100

IIN!+) -I'N(-l

IIN(+)

or

40

IINH

0

V+ - +15V (For Large Va Swing)
RL 2': 2kn

25

500

40
0

mV

nA
pArC

10

V+-2

mA

/LVrC
±150

10

V+ = 30V

60
40
±9

500

nA

V'-2

V

15

V/mV

Output Voltage Swing
Va"
Va'
Output Current
Source
Sink
Differential Input
Voltage

V' =30V, R, = 2kn
R, '" 10kn
V, = 5V, R, ,; 10kn

26
27

V" = +IV, V,,_ = OV, V' = 15V
V" = +1V, V IN + = OV, V+ = 15V

10
5

(Note 7)

28
5

26
27
20

20
8

10
5
V'

5-39

28
5

20

20
8

V
V
mV
mA
mA

V'

V

O~OlL

LM124/324

Note 1: For operating at high temperatures, the-LM324 must be derated based on a + 125'C maximum junction temperature and a thermal resistance of
175'Crw which applies for the device soldered in a printed circuit boardioperating in a still air ambient. The LM124 can be derated based on a + 150'C
maximum junction temperature_ The dissipation is the total of all four amplifiers-use external resistors, where possible, to,allow the amplifier to
'
saturate or to reduce the powe~ which is dissipated in the integrated circuit.
,Note 2: Intersll's LM124 series is protected against shorts to eitherV+ or V-_ No more than one output at a time should be shorted_ At V,upp > 15V, continuous
shorts can exceed the power dissipation ratings and cause eventual destruction,
'
Note 3: This input current will only exist when the voltage at any of the input leads is driven negative_ It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps, In addition to this diode action, there is also lateral NPN parsitic
transistor action on the IC chip_ This transistor action can cause the output voltages of the op amps to go to the V+ voltage level (or to ground for a
large overdrive) for the ti,me duration that an input is driven negative, This is not destructive and normal output states will re-establish when the input
voltage,which was negative again returns to a value greater than -O,3V.
,Note ,4: These speCifications apply for V, =+SV and -SS'C s T. s +12S'C for the LM124, and 0'9 sT. s + 70'C for the LM324.
Note 5: Vo '" 1.4V, R, =00 with V+ from SV to 30V, and over the full input common-mode range (OV to V+ =1.5V),
Note 6: The direction of the input current is out olthe IC due to the PNP input stage. This current is essentially constant, independent of the state ofthe output
so no loading change-,exists on the input lines.
Note 7: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than Q,3V. The upper end of the
common-mode voltage range is V+ -1 ,5V, but either or both inputs can go to +32V without damage.

.

Note 8: Due to proximity of external components, insure that coupling is not originating via stray capacitance between these external parts. This typically
can be detected as this type of capacitive coupling increases at higher frequencies •

TYPICAL PERFORMANCE CHARACTERISTIC$

,15

INPUT VOLTAGE RANGE

INPUT CURRENT
90

80

C
w

1

"" 10

~

~

a...

...>

i2

-

60

-40

o

,-

v+", 15V

-

I

20

_trJ

10

OPEN LOOP
FREQUENCY RESPONSE

I- " - -

;;
II:

...CZ

w
II:
II:

2

25

"

~

~~A=OOCTO+~ ~

~

ill

I I

-55 -15 J

15
v+ OR V- - POWER SUPPLY VOL rAGE (IV)

,- - - '

r- -V+::+5V

o

10

--

1
z
:0

~ 30

~

v -ov

I I I

- r- ~l+~+3Jv I~_-

70

~ 50

0

SUPPLY CURRENT

I J10

I

65

105.

_0

a

TA

--55'C20 \

30

V+ - SUPPL V VDL TAGE IV I

COMMON'MOOE
REJECTION RATIO

VOLTAGE FOLLOWER
PULSE RESPONSE
4

Rt. -' 2.0k
3
2

1f0

...: 0;;-

3

z"
-"

2

/

1\ v· =

/

15

V

\
','

"- w,

I ...

z""'
:>-g

f - FREQUENCY (Hz)

f - FREQUENCY (Hz)

VOLTAGE FOLLOWER PULSE
RESPONSE (SMALL SIGNA!,)

OUTPUT CHARACTERISTICS
CURRENT SOURCING

500r-'-~======-~-r-,

"~.

450

~~
....
""'>

w

"~

o
>

400

~

350

...:0

ge
~S

t--tt--+-!-+-+-It-+----j

a ~"
~

~~

:0

o
I

.0

250 0':-~'-'::--3~,-''-:-::-7-'-::7~8
t -TIME (/-Is)

1f-

10

20

t-

40

30

TIME ($ls)

OUTPUT CHARACTERISTICS'
CURIiIENT SINKING

;~V'/2~
5
4

~
'":

'":

.

INDEPENDENT OF
2

~Hf1I+_2~f-'c+-l I-+

H-f-lllffIilrf-'A+-II

v+

1111..,11--"HfI*"HfI

111111111111111
0.001 0,01

0.1

10

100

10+ - OUTPUT SINK CURf\ENT (mA I

5-40

0'111111"'~'

0,01

~--=TA'--=-_-+2_5'_C~. J.-I IJ.J I

L.L.ICI&o.'--U.u......
LJ....

0.001

0.01

0.1

1

10

100

10+ - OUTPUT SOURCE CURRENT (mA I

LM139/339
Voltage Comparators

FEATURES

GENERAL DESCRIPTION

• Wide single supply voltage range or dual supplies

The lM139 series consists of four independent precision
voltage comparators with an offset voltage specification
as low as 2 mV max for all four comparators. These were
designed specifically to operate from a single power supply over a wide range of voltages. Operation from split
power supplies is also possible and the low power supply
current drain is independent of the magnitude of the
power supply voltage. These comparators also have a
unique characteristic in that the input common-mode
voltage range includes ground, even though operated
from a single power supply voltage.

• Very low supply current drain (0.8 mA)independent of supply voltage (2 mW/comparator
at+5 V)
• low input biasing current
• low input offset current
and offset voltage
•
•
•
•

25 nA
±5 nA
±3 mV
Input common-mode voltage range includes gnd
Differential input voltage range equal to the power
supply voltage·
low output
250 mV at 4 rnA
saturation voltage
Output voltage compatible with TTL, DTl, ECl,
MOS and CMO~ logic systems

Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and time
delay generators; wide range VCO; MOS clock timers;
multivibrators and high voltage digital logic gates. The
lM139 series was designed to directly interface with TTL
and CMOS. When operated from both plus and minus
power supplies, they will directly interface with MOS logic
-where the low power drain of the LM339 is a distinct _
advantage over standard comparators.

mil

SCHEMATIC DIAGRAM

PIN CONFIGURATION

.

OUT2

OUT)

OUT,

OUT,

V'
-IN,

V-

+IN4

+INI

-IN,

-IN2

+IN 3

+IN2

-IN J

+INPUT

(oulline dwgs JO, PO)

OUTPUT

OUT2

OUTJ

OUT,

OUT,
V-

V'
-IN,

ORDERING INFORMATION
Part
Number

Temperature
Range

Dice

14 pin
CCR OIP

LM139
LM339

- 55°C to + 125°C
QOC to +7Q'C

LM139/0
LM339/D

LM139J'
LM339J

+IN4

+INI

-IN,

14 pin
Plastic

14 pin
Flatpak

-IN 2

+ IN 3

LM139F
LM339F

+IN2

. LM339N

, Add 18838 to order number if 8838 processing is desired.

5-41

-IN J

(oullirie dwg FO·l)

D~DIL

LM139/339
ABSOLUTE MAXIMUM RATINGS

NOTE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure, These are
stress ratings only and functional operation of the devices at
these or' any other conditions above those indicated in the
operation sections of this specification is not implied,
Exposure to absolute maximum rating conditions for
extended periods may cause device failures,

Supply Voltage, V+
Differential Input Voltage
36 V or ±18 V
Input Voltage
36 V
Power Dissipation (Note 1)
-0,3 V to +36 V
Molded DIP
S70 mW
Cavity DIP
900 mW
Flat Pack
800 mW
Output Short-Circuit to GND, (Note 2),
Continuous
Input Current (VIN < -0,3 V), (Note 3)
SO mA
Operating Temperature Range
LM339
O'C to +70'C
LM139,
-SS'C to + 12S'C
Storage Temperature Range
-6S'C to + 1S0'C
Lead Temperature (Soldering, 10 seconds)
300'C

ELECTRICAL CHARACTERISTICS (V+ = 5 V, Note 4) ,
PARAMETER

LM139

CONDITIONS

Input Offset Voltage

TA = 2S'C, (Note 9)

Input Bias Current

I'NI+) or I'NH with Output in
Linear Range, TA = 25'C, (Note 5)

Input Offset Current

I'NI+) -I'NH' TA = 25'C

Input Common-Mode Voltage
Range

TA = 25'C, (Note 6)

Supply Current

RL =
RL =

Voltage Gain

00

00,

MIN.

MAX.

±2,0

±5,0

25

100

±3.0
0

on all Comparators, TA = 2S'C
V+ = 30V, TA = 25'C

O.B

mV

±25

nA

V+-1,5

V

2.0

mA
rnA
V/mV

200

V'N = TIL Logic Swing, VREF =
1.4V, VRL := SV, RL = 5,1 k 0,
TA = 2S'C

300

ns

1,3

/-'S

16

mA

Response Time

VRL = 5 V, RL = 5,1 k 0,
TA =, 25'C, (Note 7)

Output Sink Current

V1NC- J ~ 1V; V1N1 +) = 0,
Vo '" 1,S V, TA = 25'C

Saturation Voltage

V'NH ", 1V, V'N'+) = 0,
IS'NK ,,; 4 mA,' TA = 25'C

250

Output Leakage Current

I/'NI+) ", 1V, V'NH = 0,
Vo,= 5 V, TA = 25'C

0,1

Input Offset VOltage

(Note 9)

Input Offset Current

'INC+) -

Input Bias Current

UNITS

nA

RL ", 15 kO, V+ = 15V (To
Support Large Vo Swing), TA = 2S'C

Large Signal Response Time

TYP.

6,0

IIN(-J

I'NI+) or I'NH' with Output in
Linear Range

Input Common-Mode Voltage
Range

0

' 500

mV
nA

9,0

mV

±100

nA

300

nA

V+-2,0

V

Saturation Voltage

V'NI_) ", 1V, V'NI+) = 0,
IS'NK ,,;'4 mA

' 700

mV

Output Leakage C)lrrent

V'NI+) "" 1V, V'NI_) ~ 0,
Vo = 30 V

1,0

/-,A

Keep all V'N'S'" 0 V (or V-,
if used), (Note 8)

36

V

Differential Input Voltage

,

5-42

D~DIb

L'M139/339
ELECTRICAL CHARACTERISTICS (CON'T) (V+ = 5 V
PARAMETER

,

LM339

CONDITIONS

Input Offset Vottage

T. = 25°C, (Note 9)

Input Bias Current

I'NI+' or I'NI-' with Outp'ut in
Linear Range, T. = 25°C, (Note 5)

MIN.

UNITS

TYP.

MAX.

±2.0

±5.0

mV

25

250

nA

Input Offset Current

I'NI+' -I'NH' TA = 25°C

Input Common-Mode Voltage
Range

T. = 25°C, (Note 6)

Supply Current

RL = co on all Comparators, TA '= 25°C
RL "; CO, V+ = 30V, TA = '25°C

0.8

Voltage Gain

RL ", 15 kn, V+ = 15V (To
Support Large Vo Swing), T. = 25°C

200

V/mV

300

ns

1.3

,...s

16

mA

Large Signal Response Time

±5.0
0

, V'N = TTL Logic Swing, VREF =
1.4V, VRL = 5V, RL = 5.1 k n,
TA = 25°C

Response Time

VRL .= 5 V, RL = 5.1 k n,
TA = 25°C, (Noie 7)

Output Sink Current

V'NH '" 1V, V'NI+I. = 0,
Vo" 1.5 V, TA = 25°C

Saturation Voltage

V1N1 - J ;:;::: 1V,

V1N(+1 = 0,
IS'NK .. 4 mA, TA = 25°C

250

Output Leakage Current

V'NI+' '" 1V, V'NH'= 0,
Vo = 5 V, TA = 25°C

0.1

Input Offset Voltage

(Note 9)

Input Offset Current

IINI+I -

Input Bias Current

6.0

±50

nA

V+-1.5

V

2.0

mA
mA

500

nA
9.0

IINI-I

I'NI+' or I'NI-' with Output in
Linear Range

Input Common-Mode Voltage
Ranqe

0

mV

mV

±150

nA

400

nA

V+-2.0

V

Saturation Voltage

V'NH '" 1V, V'NI+l = 0,
IS'NK" 4 mA

700

mV

Output Leakage Current

V'NI+' '" 1V, V'NH = 0,
,
Vo = 30 V

1.0

,...A

Differential Input Voltage

Keep all V'NS '" 0 V (or V-,
if used), (Note 8)

36

V

.

Note:
1. For operating at high temperatures, the LM339 must be derated based on a 12SoC maximum junction temperature and a thermal resistance
of 17SoC/W which applies forthe device solderedin II printed circuit board, operating in a still air ambient. The LM139 must be derated based.
on a 1S0°C maxitnum junction temperature. The low bias dissipation and the "ON-OFF" characteristic of the outputs keeps the chip
dissipation very small (Po s 100 mW), provided the output transistors are allowed to saturate.
..
2. Short circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately
20 mA independent of the magnitude of V+.
.
. '
3. This input current will only exist When the voltage afany of the input leads is driven negative. It is due to the collector-base junction of the
input PNP transistors becoming forward biased and thereby acting' as input diode clamps. In addition to this diode action, there is also
lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+
voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal
output states will reestablish when the input voltage, which was -negative; again returns to a value greater than -0.3V.
4. These specifications apply for V+.= SVand -SsoC s T•. s +125°C, for the LM139. The LM339 temperature specifications are limited to
O°C s TA S + 70°C.
,
S. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state
of the output so no loading change exists on the reference or input lines.
6. The input com'mon-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of
, the common-mode voltage range is'V+ -1.SV, but either or both inputs can go to +30V without damage.
7. The response time specified is for a 100 mV input step with S mV overdrive signals 300 ns can be obtained, see typical performance
characteristics section.
"
,
8. Positive excursions ot input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than -O.3V (or 0.3V below the
magnitude of the negative power supply, if used).
9. At output switch point,"Vo = 1.4V, Rs = on with V+ from SV; and over the full input common-mode range (OV to V+ -1.SV).
10. For input signals that exceed V+, onlytheoverdriven comparator is affected. With a SV supplyV'N should be limited to 2SV max, and a limiting'
resistor should be used on all inputs that might exceed the positive supply.

5-43

LM-139/339
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT CURRENT

SUPPLY CURRENT
1.0

<
.§
I-

2

w

,.

0.6

7

a:
a:

::>

">....
~

In

0.4
,

-'

,.

~

-

".t!!". ~+25°C

I-

-

2

40

::>

TA ""+70"C

2

;!!

_z

20

30

= +125"C

t.1

I I "
10

r-- T

20

I

o

40

'\

1

\

"

~~

I

4,0

_I
20 m::..

>?
~>o

3,0

I-

2.0

0

1.0

::>

.--J

100mV

.,v

I

~

I-

:!!

II

4.0

~>

2.0

-

1,0

II I..

100

Of- I-T

1,0

,1.5

-t5V

~.=
.

=2606_

t

i-

0.5

I,
II

2DmV

-\- =1 25°b
IA 1

o

100

II

0

I I I

-100

;!!

10

5~V

3.0

vour

1 1 1
-50

1.0

INPUT OVER~RIVE = 100 mV

""-

5.0

w'

~.... >
gE

0,1

, SUPPLYVDLTAGE

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES-POSITIVE TRANSITION

r"l?" =
~

'"" TA =+25°C'

t:%..,.

0.00 1
0,01

40

5.0 mV = INPUT OVERDRIVE

1

'2V

I-

6.0

5.0

V

~V

0,01

00C

30

IA

~ V TA =-WC

SUPPLY VOLTAGE (V)

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES-NEGATIVE TRANSITION
6.0

7

20

10

10 - O\JTPUT SINK CURRENT (mA)

w'

TA - +25.oC ,A

o

0.1

~
~

I-

TA =+125"C- I--

TA_=+125°~

o

"~

RL ",'-

o

g

TA ""DoC

I

I

1.0

~

TA = -55"'C

w

a:
a:

0.2

o

w

60

~-

I
ciUTOIF {
SATURATION

~

RIN (CM);l! 10 9 '.0

A-r-

~

10
V1N(CM)-OV

~ - T 1 =olc

0.8

OUTPUT SATURATION VOLTAGE

80

TA - _55°C";-

I

I

I I I
0.6

2.0

TIME ( ,ec)

Vour

.

T

I I I I
1.5

1.0

2.0

TIME (sec)

TYPICAL PERFORMANCE CHARACTERISTICS LM2901
INPUT CURRENT,

SUPPLY CURRENT

OUTPUT SATURATION VOLTAGE
10

80
TA '" -4Q°C

1!;;

I

60
TA

w

a:
a:

1

0 oc

TA .. +85°C ....
0.1

40

il

TA ' +25"C

"'~~~-I_ _-I

TA -+25<>C

i~

20

In_

~

--:

TA =+85°C
1

I

o

, 0

10

SUPPLY VOLTAGE (V)

20

5.0 mV = INPUT OVERDRIVE

2~m~

-

2.0

~

,I

.,v

I

INPUT OVERDRIVE = 100 mV

5.0

I

4,0

r,.~,,=

2.0

-

1.0

-50

100

o

0.5

1.0

t

1.5

o

=1 25o

l' I

I
.
III~v,.. . ~1k- r20mV

.

.

.

t

I I I
0.5

2.0

5-44

Your
•

I I I
1.0

TIME (,ec)

TIME ( sec)

r

I
II .,v

0 - r T =25"6-·
L I

+ L

~; -100

II
5mV

0

I I I,
I I I

~.... >

""-

3, 0

Vour

100mV

ui

~

100

1o, OUTPUT SINK,CURRENT (mAl

6.0

6.0

g.§

40

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES-POSITIVE TRANSITION

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES-NEGATIVE TRANSITII;>N

1.0

30

SUPPLY VOLTAGE (V) ,

1,5

2,0

LM139/339
APPLICATION HINTS

The differential input voltage may be larger than V+ without damaging the device. Protection should be provided
to ptel(ent the input voltages from' going negative more
than -0.3 V (at 25°C). An . input clamp diode can be
. used as .shown in the applications section.

The LM139/339 are high gain, wide bandwidth devices
which, like most comparators, can easily oscillate if the
output lead is inadvertently allowed to capacitively couple
to the inputs via stray capacitance. This shows up only
during the output voltag'e transition intervals as the comparator changes states. Power supply bypassing is not
required to solve this problem. Standar.d PC board layout
is helpful as it reduces stray input-output coupling. ReI ducing the input resistors to < 10 k n reduces the feedback signal levels and finally, adding even a small amount
(1 to 10 mY) of positive feedback (hysteresis) causes such,
a rapid transition that oscillations due to stray feedback
are not possible. Simply socketing the IC and attaching
resistors to the pins will cause iriput-output oscillations
during the small transition intervals unless hysteresis is
used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required.
All pins of any unused comparators should be grounded.

The output of the LM139 series is the uncommitted collector of ~ grounded-emitter NPN output transistor. Many
collectors can be tied together to provide an output
OR'ing function. An output P!JII-up resistor can be con- .
nected to any available power supply voltage within the
permitted supply voltage range and there is no restriction
on this voltage due to the magnitude of. the voltage which
is appli~d to the V+ terminal of the LM139A package. The
output can also be used as a simple SPST switch to
ground (when a pull-up resistor is not used). The amount
of current wbich the output device can sink is limited by
the drive avail.able (which is independent of V+) and the
f3 of this device. When the maximum current limit is reached (approximately 16 mAl, the output transistor will come
out of saturation and the output voltage will rise very
rapidly. The output saturation voltage is limited by the
approximately 60 n rsat of the output transistor. The low
offset voltage of the output transistor (1 mY) allows the
output to clamP essentially to ground level for small load
currents.
.

The bias network of the LM139 series establishes a drain
current which is independent of the magnitude of the
power supply voltage over the range of from 2 V to
30 v.

It is usually unnecessary to use a bypass capacitor across
the power supply line.

TYPICAL APPLICATIONS (V+ =15 V) .
. +5.0V .

V.

BASIC COMPARATOR

DRIVING CMOS

DRIVING TTL

+O.075V

lOOk

lOOk

AD-I\N......,
lOOk

8 D-'NI.....---<......--l

v;:r

lOOk

::r

CD-I\N~

··0····1··

lOOk

CD-I\N~

"0" "1"

AND GATE

OR GATE

5·45

LM139/,,39
TYPIC"AL APPLICATIONS (CON'T) (V+ = 1.5 V)
V+

+ '

ol
.
'0
'----1

100pF

10k

1M

,.+V,N"II-....--+----i

lOOk

PW

15k
51k

-v+

:, ms..::r-E. o
,to t,

BI·STABLE MULTIVIBRATOR
ONE·SHOT MULTIVIBRATOR

10M

560k

:'=r-

15k

lOOk'

"0"

, .+V'N 0-"",,.,,..+---+--\

-fE.1",

+4V

40

lOOk

",.:::n=
~
t,

A
02

Vo

3k

"I"

01

to

o '

lOOk
10k

':"

VOUT =A+B+C+O

,B

C
0
240k
62k

-=

ONE·SHOT NlULTIVIBRATOR WITH INPUT LOCK OUT

10k

15k

lOOk

LARGE FAN·IN AND GATE

v'

3,Ok
10M

10k

Vo'

~=r
0

V3

'3

3.0k
51k

Ve,

10M

.10k

~y

V2

INPUT GATI NG SIGNAL

o

'2

3,Ok

v+ ----------,- ... __

51k

10M

10k

\

v,

-'--

51k

'ANDing' THE OUTPUTS

TIME DELAY GENERATOR

5·46

'.

LM13,9/339
TYPICAL APPLICATIONS (V+ = 5.0 V)

+VREF

0----;
10k

4.3k

Rl
1M

Dl
lN914

R2
lOOk

D2
lN914

15k

NON·INVERTING COMPARATOR
WITH HYSTERESIS

lOOk

~+nr

BOpF

P

f= 100kHz

Vo

1M

V+
1M

+V,N o------l

3k

1M

lOOk

'FOR LARGE RATIOS OF Rl/R2.
Dl CAN BE OMITTED.

1M

v+o-"W_H
1M

SQUAREWAVE OSCILLATOR

PULSE GENERATOR
1M

INVERTING COMPARATOR
WITH HYSTERESIS

V+

V+

>-+~oQVo

STROBE

INPUT

·OR LOGIC GATE WITHOUT.
PULL·UP RESISTOR

COMPARING INPUT VOLTAGES
OF OPPOSITE PQLARITY .

BASIC COMPARATOR

OUTPUT STROBING

V·
TOOk
• lOOk

500 pF

3.0k
5.1k

+Vc
FREQUENCY
CONTROL
VOLTAGE
INPUT

3.01<

10

>-"''''-0

O.l,u.F

OUTP

OUTPUT

20k
20k

~------------------~~

SDk

v+/2
V+=+30V
+25OmV ,.;;; Vc " +5OV
700 Hz" to" 100 kHz

TWO·DEC::ADE HIGH·FREQUENCY VCO

5·47

LM139/339
TYPICAL APPLICATIONS (CON'T) (V+

=

5 VJ
v·

v· {12VI

200k·

2.0k
100k

10k

1.0k
";"

.

AV:: 100

LOW FREQUENCY OP AMP
200k

C'RYSTAL
f= 100kHz

v'
CRYSTAL CONTROLLED OSCILLATOR

LIMIT COMPARATOR

v·
RS
10k

MAGNETIC
PICKUP

3.0k

R2

[

-

--

R'N

II

.R2
lk

20M

LOW FREQUENCY OP AMP
WITH OFFSET ADJUST

AV'" 100

lk

'

10k

v·
LOW FREQUENCY OP AMP
(Vo = OV FOR VIN = OV)

TRANSDUCER' AMPLIFIER

20M
10k

ZERO CROSSING DETECTOR
(SINGLE POWER SUPPLY)

v·

SPLlT·SUPPLY APPLICATIONS (V+ =+15 V and V-';' -15 V)
v·

2k

51k
51k

3.9k

2.4k

2.4k

10k

8.2k

2k

ZERO CROSSING DETECTOR

v·
5.1k

V,N
50pF

6.8k
V-

vCOMPARATOR WITH A NEGATIVE REFERENCE

MOS CLOCK DRIVER

5'48

AD503
High Accuracy
Low Offset Op Amp

FEATURES

range' operation; the ADS03S for operation from -SsoC
to +12SoC.

• Low IBIAS: 15pA MAX
• Low Drift: 25/-LVoC MAX

It provides performance comparable to modular FET op
amps, but because of its monolithic construction,
however, its cost is significantly below that of modules,
and becomes even lower .in large quantities.

GENERAL DESCRIPTION
The ADS03 is an IC FET input op amp which provides
the user with input currents of a few pA, high overall
performance, low cost, and accurately specified, predictable operation. The device achieves maximum bias
currents as low as SpA, minimum gain of 7S,OOO, CMRR
of BOdS, and a minimum slew rate of 3V//-Ls. Itis free from
latch-up and is short circuit protected, and no external
compensation is required, as the internal 6dS/octave
rolloff provides stability in closed loop applications.

The ADS03 is especially designed for applications involving the measurement of low level currents or small
voltages from high impedance sources, in which bias
current can be a primary source of error. Input bias
current contributes to error in two ways: (1) in cljrrent
measuring configurations, the bias current limits the
resolution of a current signal; (2) the bias current produces a voltage offset which is proportional to the value
of input resistance (in the case of an inverting configuration) or source impedance (when the noninverting
"buffer" connection is used). The ADS03, therefore, is of
use where small currents are to be measured or where
relatively low voltage drift is necessary despite large
values of source resistance.

The ADS03 is suggested for all general purpose FET
input amplifier requirements where low cost is of prime
importance.
The circuits are supplied in the TO-99 package; the
ADS03J, K are specified for 0 to +70°C temperature

ORDERIN,G INFORMATION

1
AD503

~

PIN CONFIGURATION

GUARD PIN

J

H

L
L

Package

H - 10-99 metal can

Electrical option
INVERTING

See Specification Table, next page.

INPUT

Basic Part number

vOFFSET NULL

0-..1?¥.F0~..
5

OFFSET

~v(outline dwg TO·99)

S-49

~ULL

II

·AD503
SPECIFICATIONS (Typical @+2SoC and :!:1SVdc, unless otherwise noted)
, PARAMETER
OPEN LOOP GAIN1
VOUT = :!:10V, RL ~ 2kn
I
TA = min to max
OUTPUT CHARACTERISTICS
Voltage @ RL = 2kn, T A = min to max
Voltage@RL=10kn, TA=mintomax
Load Capacitance 2
Shorl Circuit Current
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time, Unity Gain (to 0.1%)
INPUT OFSET VOLTAGE3
vs Temperature, TA = min to J11ax
vs Supply,.TA = minto max
INPUT BIAS CURRENT
Either Input4
INPUT IMP.EDANCE
Differential
, Common Mode
INPUT NOISE
Voltage, 0.1 Hz to 10Hz
SHz to SOkHz
f = 1kHz,(spot noise)
INPUT VOLTAGE RANGE
DifferentialS
'Common Mode, TA = min to· max
Common Mode Rejection,VIN = ±10V
POWER SUPPLY
Rated Performance
Operating
Quiescent Current
TEMPERATURE
Operating, Rated Performance
Storage

AD503J

AD503S

AD51i3K

20,000· min (SO,OOO typ)
1S,OOO min

SO,OOO inin (120,000 typ)
40,000 min

..

:!:10V min (:!:13V typ)
:!:12V min (:!:14V typ)
750pF.
25mA

··
·
,
·,

1.0MHz
100kHz
3.0VlI'5 mih (6.0Vllls typ)

,

10IlS

...

-

2S,OOO min

···
·
·

·,
,
."

SOmV max (20mV typ)
20mV max (BmV typ)
751lV/oC max (30p.V/oC typ) 2Sp.VloC max (10p.V/oC typ) SOp.voC max (20p.V/oC typ)
400p.VIV max (200p.VIV typ) 200p.VIV max (100p.VIV typ) "
1SpA max (SpA typ)

10pA max (2.5pA typ)

,

1011 nll2pF
1012 nll2pF
1Sp.V (p-p)
5.0p.V (rms)
30.0nVl.JHz

,

:!:3.0V
:!:10V min (±12V typ)
70dB min (90dB typ)

·
·,
,

±1SV
±(5 to 1B)V
7mA max (3mA typ)

,

·
··
"

·

-65°C to +1S0°C

~

,

,

o to +70°C

,
,

,
BOdB'min (90dB typ)

..

..
·,

"

,
±(S to 22)V

,

-5SoC to +12SoC

,

Nole 1. Open Loop-Gain is specified with Vos both nulled 'and' unnulled.
Nole 2. A conservative design would not exceed 500pF of load capacitance,
Nole 3. Input offset voltage 'specifications are guaral)leed after 5 minutes of 'operatfon at TA = +25 QC.
Note 4. Bias current specifications are guaranteed after 5 minutes of operation at TA = +25o C. For higher· temperatures, the current doubles
every 10°C.
. .
..
Nole 5. See comments in rnput Considerations section.
'Specifications same as for AD503J.
"Specifications same as for AD503K. .
. Specifications subject to change without notice.

APPLICATIONS CONSIDERATI()NS
Bias Current
Most IC FE;T op amp manufacturers specify maximum
bias currents as the value immediately after turn-on.
Since FET bias currents double every 10°0 and since
most FET op amps have case temperature increases.of
15°C to 20°C above ambient, initial "maximum" readings
.5-50

may be only '.4 of the true warmed up value. Furthermore,most IC FET op amp manufa9turers specify Ib as the
average of both input currents, sometimes resulting in
twice the "maximum" bias current appearing at the
input being used. The total result is that ax the expected
bias 'current may 'appear at either input terminal in a
warmed up operating unit.

AD503·

D~DIL.

The A0503 specifies maximum bias currents at either
input after warmup, thus giving the user the values
he expected.

Note that the use of the model 209 heat sink reduces
warmed up bias current by 60% to 1.0pA in the A0503'K.
Both of these techniques may be used together for obtaining lower bias currents. Remember that loading the
output can also affect the power dissipation.

Improving Bias Current Beyond Guaranteed Values

100

Bias currents can be substantially reduced by decreas":
ing the junction temperature of the device. One technique
to accomplish this is to reduce the operating supply
voltage. This procedure will decrease the power dissipation of the device, which'will in turn result in a lower'
junction temperature and lower bias currents. The supply
voltage effect on bias current is shown in Figure 1.
1,0

j

0.9

..,!Il.l

0.8

~
w

)

.~ ~
u

~

'/

•
.;

~ .~o

0.6
O.5

'"

0,4

:;
:;
a:

1/

v

/

25

0.7

N

1

L
If

./

/"

z

0,3

50

70

AMBIENT TEMPERATURE TA _0,(:
Vs'" 1: 15V

/

o

v
V

V

Figure 3. Input Bias Current vs Temperature

V

-

0, 2

Input Considerations
The common mode input char!icteristic is shown in
Figure 4. Note that positive common 'mode inputs up to
+13.5 Volts and negative common mode inputs to -Vs
are permissible, without incurring excessive bias currents. To prevent possible- damage to the unit, do not
exceed VCM =Vs.

15

10
SUPPLY VOLTAGE -iVS - VOLTS

Figure 1. Normalized Bias Current vs SupplV, Voltage

Operation of the AD503K at ±5V reduces the warmed up
bias current by 70%. to a typical value of 0.75pA.

100 ,--r-,-..,-"'T'""'T""""T"""T---r--,-,.-r-,--..,--,-......

A second technique is the use of a suitable. heat sink.
Wakefield Engineering Series 200 heat sinks were selected to demonstrate this effect. The characteristic bias
current vs case temperature above ambient is shown in
Figure 2. Bias current has been normalized with unity
representing the 25°<: free air reading.

1
I

!E 10
I-

iiia:
a:

'"en
U

S

CD

...

1,0

~

!!;
0.9

.!II;'

}.041

O.s

'/ \
~051--= ~

7

h071'--;:;

./

0,1
-16

o

10

'/
./

15

20

-4

12

Figure 4. Input Bias Current vs Common Mode Voltage

WAKEFIELD MODEL
'NUMBERS
_

Like most other FET inp'ut'op amps, the AD503 displays
a degraded bias current specification wben operated
at moderate differential input voltages. It m'aintains its
specified bias current up to a differential input voltage
of ±3V typically. Above ±3V, the bias current wiUincrease to approximately 400ILA. This is not a failure
mode. Above ±10V differential input voltage, the bias
current will increase 100ILAIVdlff (in vcilts), and other
parameters may suffer degradation.

/(2T-

0,2

-s

COMMON MODE INPUT VOLTAGE - VOLTS

~

.0,3

-12

25

30

CASE TEMPERATURE ABOVE 25'C - 'c Vs ,15V

Figure 2. Normalized Bias Current vs Case Temperature

5·51

II

536
FET Input
Operational Amplifier
FEATURES

DESCRIPTION

• SpA input bias current
• hlput and output protection

The 536 is a special purpose high performance operational amplifier utilizing a FET input stage for extremely
high input impedance and low input current.

• Offset null capability
., Internally compensated

The device features internal compensation, standard pinout, wide differential and common mode input voltage
ranges, high slew rate and high output drive capability.

• 6V!/-LseC slew rate
• Standard pinout
., 1MHz unity gain bandwidth

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .............................. ±22V
Differential Input Voltage Range ............... ±30V
Common Mode Input Voltage Range ......... , .. ±Vs
Power Dissipation' ......................... 500mW
Operating Temperature flange
SU536 ... - 55°C to + 85 °C
NE536 ..... O°C to + 70°C
Storage Temperature Range ......... -65° to +150°C
Lead Temperature (Solder, 60 sec) ............ 300°C
Output Short Circuit Duration 2 •••••••••••••• indefinite

PIN CONFIGURATION
NC

Notes:
1. Rating applies for case temperature to + 25'C; derate linearly at
6.5mWrC for ambient temperatures above 75°C.
2. Short circuit may be to ground or either supply. Rating applies to
+125°C case temperature or + 75°C ambient temperature.

ORDERING INFORMATION

V'

(outline d\l!fg

TEMPERATURE
RANGE

TO-99)

DICE

TO·99 CAN

O·C to + 70°C
NE536/D
- 55°C to + 85 °C SU536/D

DC ELECTRICAL CHARACTERISTICS

TA = 25°C, Vsupp ±15V unless otherwise specified.'

PARAMETER
Vos
aVos/ aT

TEST CONDITIONS

Offset Voltage
Drift

NE536T
SU536T

MIN;

NES36
TYP.

Rs ~ 10kfl
Over Temp., Rs ~ 10kfl

30
30

Rs = 0 fl, Over Temp.

30

los

Of(set Current

5

IBIAS

Input Current>

30

VCM

Common Mode Voltage Range

CMRR

Common Mode Rejection Ratio

RIN

Input Resistance

VOUT

Output Voltage Swing

Icc

Supply Current

PSRR

Supply Voltage Rejection Ratio

AVOL

Large Signal Voltage Gain

Vsupp

Power Supply Range

--

Rs

~

10kfl, VIN = ±10V

RL'" 2kfl, Over Temp.
RL ~ 10k fl, Over Temp.
~

10kfl, ±6

~

5-52

/LVrC
pA
100

pA
V

64

80

dB

100

Mfl

±10
±12

±11
±13

V
V

6.0

8.0

100

300 -

50
25
±6

, Notes:
1. Input current typically doubles every 10°C.

mV
mV

±11

Vs ±15

Vo = ±10V, RL 2kfl
Vo = ±10V, RL '" 2kfl, Over Temp.

90

UNIT

±10

VOUT = OV
Rs

MAX.

±18

mA

/LVN
'11m V
V/mV
V

536
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, ±6V ~ Vs ~ ±20V unless otherwise specified. 2
SU536

Vos

PARAMETER

TEST CONDITIONS

Offset Voltage 2

Rs ~ 10k!1
Over Temp. Range, RS :s; 10kO
Rs

AVos/AT Drift
los

Offset Current

IBIAS

Input Current',2

~

MIN.

10k!1

TYP.

MAX.

7.5
7.5

20
30

20

VCM

Common Mode Voltage Range

CMRR

Common Mode Rejection Ratio

RIN

Input Resistance

VOUT

Output Voltage Swing 2

1+

Supply Current

PSRR

Supply Voltage Rejection Ratio

AVOL
Vsupp

Power Supply Range

~
~

Vsupp = ±15V
Rs

~

10k!1, VIN = :!:10V

RL ~ 2k!1, Vsupp = ±15V
"RL ~ 10k!1, Vsupp = ±15V
VOUT

= OV,
Rs

:!:11

V

70

80

dB

100

M!1

:!:10
:!:12

:!:12
:!:13

V
V

10k!1

Vsupp = ±15V, Vo = ±10V, RL

Large Signal Voltage Gain 2

~

4.5

5,5

rnA

50

150

/LVN
V/mV

,

:!:20

V

50

2k!1

pA
pA

:!:10

Vsupp = ±20V
~

30
3000

5
250

2k
10k

mV
mV
/LVrC
pA

5
Over Temp. Range, RL
Over Temp. Range, RL

UNIT

:!:6

Notes:
1. Input current typically doubles every 10°C.
2. Operating temperature range is - 55°C to + B5°C.

AC ELECTRICAL CHARACTERISTICS
T A = 25°C unless otherwise specified.'·2
SYMBOL

PARAMETER

COIFF

Differential Capacitance

en

Input Noise Voltage

TEST CONDITIONS

MIN.

TYP.

O,1Hz-100kHz

Zo

Output Impedance

GBW

Unity Gain Frequency
Full Power Bandwidth

Vsupp = ±15V
Vsupp = ±15V

SR

Slew Rate, Inverter
Slew Rate, Follower

Vsupp = ±15V, A =-tV
Vsupp = ±15V,A = +1V

"

MAX.

pF

20

I'Vrms

100

!1

1
100

MHz
KHz

6
6

VII'S
VII'S

Notes:
I, Temperature range is - 55 '" TA
2. ± 6V :5 Vsupp ± 20V

'"

B5°C

v'

TEST CIRCUITS

v'
VOLTAGE FOLLOWER CIRCUIT

OFFSET NULL CIRCUIT

5-53

UNIT

6

536

U~UIl

TYPICAL PERFORMANCE CHARACTERISTICS
LARGE SIGNAL VOLTAGE FOLLOWER
PULSE RESPONSE

J

TA = 25°C. Cl .. l00pF

I I I

+5

~

40

I I I

II.

+'0

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY

eo

CL

I

::l

:=::l
0

=100pF

'6

1\
\

'2

II

-'0
o

2

4

6· 8

-r---

\

20

TA "" 2S"C

I

-5

Rl '" 2Kfl

24

RL =2Kn

>

VSUPP = ±15V

32

28

VSUpp '" :!:15V

0

36

\

o

10 12 14 16 18

,

\

'K

'00

'OK

TIME -,usee

lOOK

,M

'OM

FREQUENCY - Hz

OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE

OPEN LOOP PHASE RESPONSE AS A
FUNCTION OF FREQUENCY
0

I

J

+2 0

II

POSITIVE SWING

~

o>

+1 5

+'

~

......

0

"z
~

S
~

-10
.-1 5

Rl = 2Krl

.......

a:

4

6

B 10 12

'\.

_8 0

I

~ -100

NEGATIVE SWING

I
I

\

-6 0

iilo

J

a:

l""-h.. I

-20

'\

m -40

I

-5

o

-20

TA '" 2S"C

"..

...

+5

0

1-'11

1\

-120

-'4 0

II
I I

-'6 0
-'8 0

14 16 18 20

10

100

SUPPL V VOLTAGE -'tV

OPEN LOOP VOLTAGE GAIN AS A
. FUNCTION OF FREQUENCY
'00

>
>

'\.

.E
I

z
<1

"
w

"~

40

>

20

I

\

100

o

50

~

I\.

\

0

I::l

I'\.
10

100

lK

10K lOOK

110

RL '2KI1 'OOpF _

"'- =

I

Vsupp =

t15V

1

1M

o

10M

I

,100
TA = 2SoC

~

. 90

z

~

0

w

~-

0

g

0

Ij

\

0,

10M

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

'T!.LI-

I

~

I\.

lOOK 1M

I I

I

'50

'\.

60

r r-.....

200

'\.

ao

10K

VOLTAGE FOLLOWER
TRANSIENT RESPONSE

-

\.

lK

FREQUENCY - Hz

RL '= 2Kn

I

0

,1

.2

3

A

5

.7

~

0
4 2

S

~

4

6

8

10

12 14 16 18 20 22

FREOUENCY - Hz

TIME IN iJS

SUPPLY VOLTAGE - ±V

INPUT VOLTAGE NOISE AS A
FUNCTION OF FREQUENCY

INPUT CURRENTS AS A FUNCTION
OF AMBIENT TEMPERATURE

OUTPUT SHORT-CIRCUIT CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE;

10000,---,--,---,---,

25

'OK
VS=±15V

~

"E

~

I

'K

I
w

L

""
::;

A

o
>
w

'"z
is

'0

~~.<:
"'="O---:,,!,OO,---"'KC---,'-='OKo---:',,,,OOK
FREQUENCY - Hz

,

-20

/r

,/

+20

./

./

~NPUT OFFSET

C,RREjT-

V
+40

+60

TEMPERATURE -'C

5-54

+80

22

a:

2'

"eo
:;
"Ua:

20

ilia:

+100

l;;
0

ili

Vsupp:= ±15V

23

eo

::l

INPUT BIAS CURREN'y

24

,.

'8
'7
'6

'5-20

i'....

-

,.....

,

+20

+40

TEMPERATURE - ¢C

+60

_+80

AD590
, Two-TerminallC
Temperature Transducer
FEATURES
•
•
•
•
•
•
•
•

electrical temperature sensors are currently employed. The
inherent low cost of a monolithic integrated circuit combined
with the elimination of support circuitry makes the AD590 an
attractive alternative for many temperature measurement
situations. Linearization circuitry, precision voltage amplifiers, resistance-measuring circuitry and cold junction compensation are not needed in applying the AD590. In the
simplest application, a resistor, a power source and any
voltmeter can be used to measure temperature.

Linear current output: 1 pAJ°K
Wide range: - 55°C to +150°C
Two-terminal device: Voltage in/current out
Laser trimmed to :t O.5°C calibration accuracy
(AD590M)
Excellent linearity: :t O.5°C over full range (AD590M)
Wide power supply range: + 4V to + 30V
Sensor isolation from case
Lowcost
.

In addition to temperature measurement, applications include temperature compens,ation or correction of discrete
components, and biasing proportional to absolute temperature. The AD590 is available in chip form making it suitable
for hybrid circuits and fast temperature measurements in
'protected environments.

GENERAL DESCRIPTION
The AD590 is a two-terminal Integrated circuit temperature
transducer which produces an output current proportional to
absolute temperature. The device acts as a high impedance
constant current regulator, passing 1 /lA/OK for supply voltages between + 4V and + 30V. Laser trimming of the chip's
thin film resistors is used to calibrate the device to 298.2 /lA
output at 298.2°K (+ 25°C).

The AD590 is particularly useful in remote sensing applications. The device is insensitive to voltage drops over long
lines due to its high impedance current output. Any wellinsulated twisted pair is sufficient for operation hundreds of
feet from the receiving circuitry. The output characteristics
also make the AD590 easy to multiplex: the current can be
sWitC. hed by a CMOS m. ultiplexer orthesupply voltage can be ~
swit~hed by a logic ga!e output.
"

The.AD590 should be used in any temperature sensing application between - 55°C and + 150°C in which conventi.onal

SCHEMATIC DIAGRAM

PIN CONFIGURATIONS

+

+---.--...,

.

.

1 Ul 1
L.

OJ OJ

CASE

+
(Outline Drawing TO-52)

ORDERING INFORMATION
NON-LINEARITY
(OC)

TO-52
PACKAGE

±3.0
± 1.5

AD590lH
AD590JH

±O.B
±O.4

AD590KH
AD590LH

±O.3

AD590MH

5-55

CERAMIC
PACKAGE

AD590lF
AD590JF
AD590KF
AD590LF
AD590MF

(Outline Drawing DH)

O~OIb

AD590
ABSOLI,JTE MAXIMUM RATINGS
(TA = + 25°C unless otherWise noted)

ForwardVoltage(V+ toV-) .. : .................. +44V
Reverse Voltage (V + to V -) ..................... - 20V
BreakdownVoltage(CasetoV+ orV-) ........... ±200V

SPECIFICATIONS (Typical values at TA =
CHARACTERISTICS

+ 25°C, V +

Rated Performance Temperature Range .. - 55·C to + 150·C
Storage Temperature Range ............ - 65°C to + 175°C
Lead Temperature (Soldering,10 sec) ............. + 300°C

= 5V unless otherwise noted)

AD5901

AD590J

AD590K

AD590L

AD590M

UNITS

298.2

298.2

298.2

298.2

298.2

~A

1.0

1.0

1.0

1.0

1.0

~A/oK

Output
Nominal Output Current
@ + 25°C (298.2~K)

Nominal Temperature
Coefficient

± 10.0 max

± 5.0 max

± 2.5 max

±1.0 max

±0.5 max'

°C

±20.0 max

±10.0 max

±5.5 max

±3.0 max

±1.7 max

°C

± 5.8 max

±3.0 max

±2.0 max

±1.6 max

±1.0 max

'C

Non-Linearity

±3.0 max

±1.5 max

±0.8 max

±0.4 max

Repeatability (Note 2)

± 0.1 max

± 0.1 max

± 0.1 max

± 0.1 max

±0.1 max

'C

. Long Term Drift (Note 3)

± 0.1 max

±0.1 max

.±0.1max

±0.1 max

±0.1 max

'C/month

Calibration Error
@ + 25°C. (Notes)

Absolute Error
( - 55°C to + 150°C)
Without External
Calibration Adjustmeni
With External Calibration
Adjustment

Current NOise

40

±0.3 max

'C

40

40

40

40

PA/..jHz

0.5
0.2

0.5
0.2

0.5

~AIV

0.2

~AIV

0.1

0.1

0.1

~AIV

Power Supply Rejection
+4

298.2

a:
a:

...'-'
::>

...::>
0..

0

218

/

V

,------0+5V

V

v
AD590

1kn

218°K 298.2°K 423°K
(- 55'C) ( +25'C) ( +150'C)

Typical Connection

TEMPERATURE .

5-56

V

)J-A723
Voltage Regulator

FEATURES

GENERAL DESCRIPTION

• 150 mA output current without external pass
transistor
• Output currents in excess of 10A possible by
adding external transistors
• Input voltage 40V max
• Output voltage adjustable from 2V to 37V
• Can be used as either a linear or a switching
regulator.

The 723, is a voltage regulator designed primarily for series
regulator, applications. By itself, it will supply output currents up to 120 mA, but external transistors can be added to
provide any desired load 'current. The circuit features
extremely low standby current drain, and provision is made
for either linear or foldback current limiting.
The 723 is also useful in a wide range of other applications such as a shunt regulator, a current regulator, or a
temperature-controller.
The 723C is identical to the 723M except that the 723C has
its performance guaranteed over a O°C to 70°C temperature
range, instead of -55°C to +125°C.

BLOCK DIAGRAM

. FREQUENCY
COMPENSATION

7

Vc

TEMPERATURE
COMPENSATED
ZENER
SERIES PASS
TRANSISTOR
VOUT
{
CURRENT
LIMITER

·Pin numbers refer to metal can package.

~
V-

Vz

CURRENT
SENSE

ORDERING INFORMATION

PIN CONFIGURATIONS·

NC

Part
Number

,

/LA723C
/LA723M

TO-99
Can

14 Pin
CERDIP

14 Pin
Plastic DIP

/LA723HC /LA723DC /LA723PC
/LA723HM* /LA723DM*

/LA723C/D
/LA723M/D

NC
FREQUENCY
COMPENSATION'

CURRENT LIMIT

Dice

v+
Vc

CURRENT SENSE

INVERTING INPUT
NON-INVERTING

* Add OB to order number if 883B processing is desired.

INPUT

VOUT

VREF

Vz

V-

NC

(outline dwgs JD, PD)

CURRENT
LIMIT

INVERTING

~V+

INPUT

0

NON-INVERTING 3

-I

INPUT
I

.

VREF 4

_~(,!)

Vc

VOUT

V-

TOP VIEW
NOTE: Pin 5 connected to case.

(outline dwg TO-100)
5·57

fJ. A723
ABSOLUTE MAXIMUM RATINGS
.. Pulse. Voltage from V+ to V- (50 ms) ........................................ 50V
Continuous Voltage from V+ to V- ....................................... :. 40V
Input-Output Voltage Differential .......................................... 40V
Maximum Amplifier Input Voltage .IEither Input) ............................ 7.5V
Maximum Amplifier Input Voltage (Differential) ........................... : ....5V
Current from Vz ....................... '. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. :25 mA
Currentfroin VREF '" ................ : .................................... 15 mA
Internal Power Dissipation Metal Can (Note 1) .......... , ............... 800 mW
.
.
Cavity DIP (Note 1) ......................... 900 mW
Molded DIP (Note 1) ........................ 660 mW
Operating Temperature Range /-LA723
......................... -55°C to +125°C
.
.
/-LA723C
........................... O°C to +70°C
. Storage Temperature Range Metal Can ........................ --£5°C to +150°C
.
...
.
DiP ....................... ·, ...... -55°C to +125°C
Lead Temperature (Soldering, 10 sec) ....................... ; ............ 300°C
Stresses abov~ those listed under Absolute·Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of th~ device
at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may. affect device reliability.

ELECTRICAL CHARACTERISTICS (Note 2)
PARAMETER
Line Regulation

Load Regulation

Ripple J;lejection
Average Temperature
CCoefficient of Output Voltage
Short Circuit Current Limit'
Reference Voltage
Output Noise Voltage
Long Term Stability
Standby Current Drain
Input Voltage Range
Output Voltage Range.
Input-Output Voltage Differential

CONDITIONS

MIN

VIN = 12V to VIN = 15V
-55°C < TA < +125°C
O°C,::; TA::; +70°C
VIN-12V to VIN = 40V
IL - 1 mA to IL '- 50 mA
-55°C < TA < +125°C
O°C < TA < == +70°C
f = 50 Hz to 10 kHz, CREF = 0
f - 50 Hz to 10 kHz, CREF - 51'F.
:-55°C < TA < +125°C
O°C::; TA::; +70°C
Rsc - 10.0, VOUT - 0

.. /-LA723
TYP MAX
0.1
.01
0.3
.02
.03

MIN

0.2
0.15
0.6

/-LA723C
TYP MAX
.01

0.1

0.1
.03

0.3
0.5
0.2

UNITS

% VOUT

0.6
74
86
.002

6.95
BW - 100 Hz to 10 kHz, CREF - 0
BW -100 Hz to 10kHz, CREF =51'F
IL -.0, VIN - 30V
9.5
2.0
3.0

65
7.15
20
2.5
0.1
1.3

74
86

dB

.015

7.35

3.5
40
37
38

6.80

9.5
2.0
3.0

.003
65
7.15
20
2.5
0.1
1.3

.015
7.50

%!OC
mA
V
I'Vrms

4.0
40
37
38

Vo!1000 hrs
mA
V

Nole 1: See derating curves for maximum power rating above 25°C.
.
Nole 2: Unless otherwise specified, TA = 25°C, W~ = V+ =Vc =,12V, V- = 0, VOUT = 5V, IL = 1 mA, Rsc = 0, C,= 100 pF, CREF=Oand divider
Note
Nole
Nole
Nole
Nole

3:
4:

5:
6:
7:

impedance as seen by error amplifiers 10 Kfl connected as shown in Figure 1:Line and Idad regulatio.n specifications are given forthe
condition of constant chip temperature. Temperature drifts must.be taken .into account separately for high dissipation conditions.
L, is 40 turns of No. 20 enameled copper wire wound on Ferroxcube P36/22-3B7 pot core or equivalent with 0.009 in. air gap.
Figures in parentheses may be used if Rl/R2 divider is placed ·on opposite input of error amp.
.
Replace Rl/R2 in figures with divider shown in Figure 13.
.
V+ must be connected to a +3V or greater supply.
.
For metal can applications where Vz is required, an external 6.2 volt zener diode should be connected in series with VOUT.

5·58

O~OIL·

tlA723
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD REGULATION
CHARACTERISTICS WITH
CURRENT LIMITING·'
0.05

LOAD REGULATION
CHARACTERISTICS WITH
CURRENT LIMITING

,-.-----,,..-,-'--'-r--.,..-.--I.--I,---,

0.1

VOUT· +5V, VIN" +12V
RSC "10n

r---c

1 1

.....

....

!:i

::l

~-0.05

~

.;p.

~

-0. 1

"

~ -0.15

::l

~~

-0.3

-0.25

-0.4

,

15

25

20.

30

20

OUTPUT CURRENT ImAI

1.2

~

~~~~ ~O~~' VIN - +12V

-'~

1--.

~

,

::l

,~
~

~

~

0:

0.8
0.6

I

r' TA",-55'C.

0.4 I-

0.: ~f=t~

-t

I--+----l

60

80

I--="-j;;;-=-+~i-+--t---:-""""~I---I 80

z

;;

w

-50

\1
I-'

I
II

0

V

0

2.0

~

r-

.---: I-- t-

TA"125;~~

T~" 1~5,L.L
I

0.8

O.6
O. 4
VOUT" VREF
ILj 0 I

I

20

30

40

50

I'NPUT VOLTAGE IVI

OUTPUTIMPEDANCEVS
.FREQUENCY

-

'-'

-< z

35

It
-OUTPUTVOLTAGE/'

-2.0 ~

I-

~

>

,-

0

25

8.0

0

co

'm"

-4.0

15

10

-6.0
45 .

!

S

~

0

4,0

"
-'
0

.

I::l
I::l

!
.1.0

.~

C

w

£

~o w"
:1c

. VOUT=+5V

VIN"+12V
.RSC = 0
TA"25'C
' IL"50mA

1

0

I

TA" 25'C
RSC=O
-4.0
-5

I

10

LOAD CURRENT

;;
.W

IL= 1 mA

0

~
c

>
oS

...
~

~TPUTVOLTAGE-

VIN = +12V
-2.0 VOUT= +5V

::l

..-

1.0

50
100
150
JUNCTION TEMPERf\TURE I'CI

12

<
0

>

I::l

1.2

LOAD TRANSIENT. RESPONSE
4.0

II\..

0

J"

\

2.0

w

""
~~
-<0

I-""

1.4

0

INPUT VOLTAGE

~

! ·1.

TAc-55'C'-,-

1.6

O. 2

100

6.0

0

!:a~ E
:::!;:

3':1
+-+--+""'I----l 40 ~ In .

LINE TRANSIENT RESPONSE

4.0

. IL=lmAtoIL""50mA

2.0

nO:
i~

OUTPUT CURRENT ImAI

.

~~~! ~ +SV I--t---t-_l+-_·-I--.J".+--jl-l

STANDBY CURRENT DRAIN VS
INPUT VOLTAGE

-++-+.l--.-1--+---1
i

40

~O'~--

VIN - VOUT IYI

120 ·~ffi

r-:::-'=I--l---1

..::

20

>
oS

100

---:--

TA" 125'C='i---H------,-+---'--l

_._"-

f--+-+--t---i-+--t--'l"-..t----j
TA"'25°C

80
40
60
OUTPUT CURRENT ImAI

j.--"1

-0.2 '-'-'-'---"---'----''-----~-''--~..........
-5
15
25
. 35
45

TA"25'C::r-t.t---~I----l

f--

H-'

-0.1

."Io.:--;-----I~+-+-+--t---j 160

'~'-f-

. "I

t---

0:

LINE'

1.8

1.0 I-----~-~+~----j

w

TA='-55'C-

r-~----.,...-'T--'---r-r---1 200

'-"---r---r-~---------,,,,.,..,'
1

-I"

·co
w

CURRENT LIMITING
CHARACTERISTICS VS
JUNCTION TEMPERATURE

CURRENT LIMITING
CHARACTERISTICS

......

::l

~
~.

1

TI\

'j

0
j:

:\.

'\ \ I I I

i

0.1

z

\ \ :"..

1 Tl"lJ5'c
10

,

'\~I

~r-t-

-0.2

~

0

>
;p.

TA" 25'C-\

&l
0:

&l
0:

i

0.2

::l

;

z
o

:J

....

!

!
5 -0.2 U-~.

I
~ -0.1

o

LOAD & LINE REGULATION VS
INPUT~OUTPUT VOLTAGE
DIFFERENTIAL

-4.0

0

-8.0
-5

\
\'

r

-10 ~ ~
o !!!
z

f-'

-20 ~.

VIN=+12V

VOUT"+5V
IL",40mA
TA=25'C
RSC" 0

\.
15

5-59'

25

35

I::l

~

,Iii

0.1

::l

0

-30

45

.01
100

lK

10K
lOOK
FREOUENCY IHzl

1M

ll~DIl,

J.LA723
MAXIMUM POWER RATINGS
p.A723
POWER DISSIPATION VS
AMBIENT TEMPERATURE
1000
DIP

900

700

500

f

-

;"S ~I-

1----:'

+-t-t-- "~
.,'!

-1---

I

800
700

~

-

400
300

900

1\

TO-5
~\
1-_-1--__

600

~

!

1000

I I
I

800

p.A723C
POWER DISSIPATION VS
AMBIENT TEMPERATURE

~

--

!

f
--

100

400
300

TJ MAX' 150'C
_
RTH • 160' C/W (TO-51
RTH' 140' C/W (OIPI

200

600
500

200
100

NO HEATSINK

o
,55

-25

0

25

50

75

100

125

150

-55

-25

TA AMBIENT TEMPE.RATURE ('CI

iii

0

25

50

75

100

125

150

T A AMBIENT TEMPERATURE ( CI

,

TABLE I: RESISTOR VALUES (kIll FOR STANDARD OUTPUT VOLTAGE
POSITIVE
OUTPUT APPLICABLE
VOLTAGE . FIGURES
(Note 4)
+3.0
1,5,6,9,
12 (4)
+3.6
1,5,6,9,
12 (4)
1,5,6,9,
+5.0
12 (4)
1,5,6,9,
+6.0
12 (4)
2,4, (5, 6,
+9.0
12,9)
2,4, (5,6,
+12
9,12)
2,4, (5, 6,
+15
9,12)
2,4, (5, 6,
+28
9,12)
+45
7
+75
7

FIXED
OUTPUT
±5%
R1
R2
4.12 3.01

OUTPUT
NEGATIVE
FIXED
ADJUSTABLE- . OUTPUT APPLICABLE
OUTPUT
±10% (Note 5)
VOLTAGE
FIGURES
±5%
R1
P1
R2
R1
R2
1.8
0.5
1.2
102
3.57
+100
7

5% OUTPUT
ADJUSTABLE
±10%
R1
P1
R2
2.2
10
91

3.57

3.65

1.5

0.5

1.5

+250

2.15

4.99

.75

0.5

2.2

1.15

6.04

0.5

0.5

1.87

7.15

.75

4.87

7.15

7.87

7

3.57

255

2.2

10

240

--6 (Note 6)

3, (10)

3.57

2.43

1.2

0.5

.. 75

2.7

--9

3, 10

3.48

5.36

1.2

0.5

2.0

1.0

2.7

-12

3, 10

3.57

8.45

1.2

0.5

3.3

2.0

1.0

3.0

-15

3, 10

3.65

11.5

1.2

0.5

4.3

7.15

3.3

1.0

3.0

28

3, 10

3.57

24.3

1.2

0.5

10

21.0

7.15

5.6

1.0

2.0

-45

8_

3.57

41.2

2.2

10

33

3.57
3.57

48.7
78.7

2.2
2.2

10
10

39
68

-100
-'-250

3.57
3.57

97.6
249

2.2
2.2

10
10

91
240

8
/8

TABLE II: FORMULAE FOR INTERMEDIATE OUTPUT VOLTAGES
Outputs from +2 to +7 yolts
(Figures 1, 5, Q, 9, 12, (4))

Outputs from +4 to +250 yolts
(Figure 7)

Current Limiting

VOUT =[VREF X Rl ~ R2] .

VOUT = [VRiF X R2;1 Rl]; R3 = R4

ILiMIT = VSENSE
Rse

Outputs from +7 to +37 volts ,
(Figures 2, 4, (5, 6, 9, 12) )

Outputs from --6. to -250 Yolts
(Figures 3, 8, 10)

Foldback Current Limiting
_ [VOUTR3 + VSENSE (R3 + R4)]
IKNEE Rse R4
Rse R4
I
' - [VSENSE X R3 + R4 ]
SHORT eKT Rse ' ~

r

R1+ R2]
VOUT = VREF X ~

, VOUT = [VREF X Rl + R2} R3 = R4
2
R1
'

5-60

O~OIl.

IlA723
TYPICAL APPLICATIONS

TYPICAL PERFORMANCE

Regulated Ouput Voltage

NOTE: R3",;,-w2

TYPICAL PERFORMANCE
Regulated Ouput Voltage
15V
Line Regulation (.l VIN :II lV)
1.5mV
Load Regulation (j, IL .. 50 mAl
4.SmV

SV

Line Regulation (.l VIN .. lV)
Load Regulation (~I L = 50 rnA)

O.5mV

1.5mV

f~r minimum temperature drift.

NOTE:. R3 =

R~~R~2 for minimum temperature drift.

R3 may be eliminated for minimum component count.

FIGURE 2:
Basic High Voltage Regulator
(VOUT = 7 to 37 Volts)

FIGURE 1:
Basic Low Voltage Regulator
(VOUT = 2 to 7 Volts)

VAEF

VOUT

Vz

~~~~c

CL

cs

TYPICAL PERFORMANCE

Regulated Ouput Voltage

-lSV

line Regulation (J. VIN = lV)

lmV
2mV

Load Regulation (.lIL "" 100 mAl

TYPICAL PERFORMANCE
Regulated Ouput Voltage
.. +15V
line Regulation (.1 VIN = 3V)
1.5 mV
Load Regulation (.lIL = 1A)
15 mV

FIGURE 4:
Positive Voltage Regulator'
(External NPN Pass Transistor)

FIGURE 3:
Negative Voltage Regulator

VIN

V+

RSC
30

V+

VREF

VOUT

t - -.....'VII'v...._~~~~~~TEO

R:i

VREF

2.7K

~~~k

CS
N.I.
R2

R4
S.6K

CL

RSC

INV.I-+--....~

~~~~~~TEO

'-:-:-r--rn~,

TYPICAL PERFORMANCE
Regulated Output Voltage
+5V
Line Regulation I..\VIN = lV)
0.5 mV
Load Regulation It\ I L '" lAI
5 mV

TYPICAL PERFORMANCE

Regulated Output Voltage
Line Regulation (.l VIN = 3V)
Load Regulation (.ll L = 10 rnA)

Short Circuit Current

FIGURE 5:
Positive Voltage Regulator
(External PNP Pass Transistor)

+SV
O.5mV
lmV

20mA

FIGURE 6:
Foldback Current Limiting

5-61

D~DIl.

J.LA723
TYPICAL' APPLICATIONS (CON'T.)

VRE'F

VIN

RSIOK

V+
VOUT

RS
In

L_'-'t~::=~::::==::I_~_REGULATED
OUTPUT

OUTPUT
L~::~::::::~::::::::::j-~~_REGUlATED
TYPICAL PERFORMANCE
Regulated Output Voltage .
+50V
Line Regulation (.6. VIN 20)1)
15mV
Load Regulation (J.IL .. 50 rnA)
20mV

TYPICAL PERFORMANCE
Regulated Output Voltage
-l00V
Line Regulation (ol VIN = 20V)
30 mV
Load Regulation (.11 L .. 100 mAl "20 mV

FIGURE 7:
Positive Floating Regulator

FIGURES:
Negative Floating Regulator

=

.

VIN
VIN·

V+

II ~,1mH'

.----jVREF

I-~""~t-i'ow,--..._

RI

01
IN2071

Cl .
'0.1

~5~~J:TED

~F

R31K

RI

TYPICAL PERFORMANCE
Regulated Output Voltage

TYPICAL PERFORMANCE
-15V
Regulated Output Voltage
8mV
6mV

+5V

, Line Regulation (olVIN = 20V,
. Load -Regulation (.lI.L II: 2AI

10mV

Line Regulation (J. VIN = 3OV,
LOad Regulation (.1.1 L .. 2Al

BOrnV'

FIGURE 10:
Negative Switching Regulatpr

FIGURE 9:
Positive Switching Regulator

VIN

" VIN
V+
VREF

RI

, REGULATED
OUTPUT

VOUT

~~~k

VREF'
CL

R2

~~~CL

INV.

V-

cs
R4
1-"2"K,,,,-o

=

=

NOTE: Cur~ limit tnmsmor maY be

used for shutdown if current
limiting II not NqUired.

N:1.

~P~~

R3
100

Vz

Rl

CS

N.I,

VOUT

1

RI

INV.
Pl-

TYPICAL PERFORMANCE
Regulated Ouput Voltage
+sv
Line RegUlation (& VIN = 3V)
O.5mV

TYPICAL PERFORMANCE'
+5V
Regulated Ouput Voltage
O.5mV
Line Regulation (6 VIN = 3V)
1.5mV
Load Regul~ion {4fL .. 50 mAl

Load Regulation {& IL'" 50 mAl

FIGURE 12:
Shunt Regulator

FIGURE 11:
Remote Shutdown Regulator with
Current Limiting

5-62

1.5mV

FIGURE 13:
Output Voltage
Adjust (See Note 5) .

... A733
Differential Video Amplifier
Linear Integrated Circuits
FEATURES
•
•

GENERAL DESCRIPTION
The 733 is a monolithic two-stage Differential Input,
Differential Output Video Amplifier. Internal series-shunt
feedback is used to obtain wide bandwidth, low phase
distortion, and excellent gain stability. Emitter follower
outputs enable the device to drive capacitive loads and all
stages are current-source biased to obtain high power
supply and common mode rejection ratios_ It offers fixed
gains of 10, 100 or 400 without external components, and
adjustable gains from 10 to 400 by the use of a single
external resistor, No external frequency compensation
components are required .for any gain option. The device is
particularly useful in magnetic tape or disc file systems
using phase or N RZ encoding and in high speed thin film or
. plated wire memories.

120. MHz Bandwidth
250 k[2 Input Resistance

• Selectable Gains of 10, 100, and 400
•

No Frequency Compensation Required

ABSOLUTE MAXIMUM RATINGS

±s

V
±5 V
±6 V
10mA

Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Output Current
Internal Power Dissipation
Metal Can
Flatpak
DIP
Operating Temperature Range
Military
Commercial

500 mW
570 mW
670 mW

CHIP TOPOGRAPHY
3

- 55°C to +125°C
0° C to + 70° C

G29

2

1

GAIN SELECT

INPUT 2

INPUT'

/

Storage Temperature· Range
- 65°C to + 150° C
Lead Temperature (Soldering, 60 second time limit) 300°C
GAIN

10
G'A

GAIN SELECT

..

4----;..~!~k~
~:..Jlk
~Fr
91 r l!:Jl

SEL~!:~

- ~'A

GAIN SELECT

,n·:A~:
r
--

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions above those indicated in the opsrational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

OUTPUT

~

OUTPUT 1

CHIP DIMENSION 43 x 45 MILS

EQUIVALENT CIRCUIT

PIN CONFIGURATIONS

lO·LEAD METAL CAN
(TOP VIEW)
RU

~~--~~~~--~--~
II\iPUT \

...... r--~OLJTPUT 1

I"JPUT 2

OUTPUT 2

ORDERING INFORMATION
Temp Range
GAl'\!

Note:

Commercial

SEl~CT

Pin 5 connected to case,

Military

(outline dwg TO-l00)

5-63

Package

Order
Number

Dice
TO-99
Dice
TO-99

/J-A733C/D
/J-A733HC
/J-733M/D·
/J-733HM

400~

;

pA733
733M ELECTRICAL CHARACTERI'STICS (TA
PARAMETER (see definitions!

= 25°C.

Vs

= ±6.0 V unless otherwise specified)

CONDITIONS

MIN.

TYP.

MAX ..

UNITS

Differential Voltage Gain
Gain 1 (Note 1)

300

400

500

Gain 2 (Note 2)

90

100

110

Gain 3 (Note 3)

9.0

10

11

Bandwidth

RS" son

Gain 1

40

MHz

Gain 2

90

MHz

Gain 3

120

MHz

Aisetime

RS - son, VOUT= 1 V p.p

Gain 1

10.5

Gain 2

4.5

Gain 3

2.5

Propagation. Delay

ns
10

ns
ns

RS = 50n, VOUT = 1 V p .p

Gain 1

7.5

Gain 2.

6.0

Gain 3

3.6

ns

4.0

kn

30

kl1

ns
10

ns

Input Resistance
Gain 1
Gain 2

20

Gain 3

kn

250

Input Capacitance

Gain 2

2.0

'pF

Input Offset Current

0.4

3.0

Input Bias Current

9.0

20

Input Noise Voltage

RS = 50n, BW = 1 kHz to 10 MHz

Input Voltage Range

IJA
IJA
I1Vrrns

12
±1.0

V

Common Mode Rejection Ratio

Gain 2

V CM=±lV,f";;100kHz

Gain 2

V CM =±lV,f=5MHz

Supply Voltage

Rejectio~

60

B6

dB

60

dB

70

dB

Ratio

D.vS

Gain 2

= ±0.5 V

50

Output Offset Voltage
Gain 1
Gain 2 and Gain 3

0.6

1.5

V

0.35

1.0

V

3.4

Output Common Mode Voltage

2.4

2.9

Output Voltage Swing

3.0

4.0

V
V p _p

Output Sink Current

2.5

3.6

rnA

Output Resistance

20

Power Supply Current

18
0

n
24

rnA

0

The following specifications apply for -55 C :S;;;;TA ~ +125 C

Differential Voltage Gain

Gain 1 (Note 1)

200

600

Gain 2 (Note 2)

80

120

Gain 3 (Note 3)

8.0

12

Input Resistance

kll

8.0

Gain 2
Input Offset Current
Input Bias Cu rrent

Input Voltage Range

5.0

I1A

40

IJA
V

±1.0·

Common Mode Rejection Ratio

50

dB

Supply Voltage Rejection Ratio

50

dB

Output Offset Voltage
Gain 1

1.5

V

Gain 2 and Gain 3

1.2

V

Output Swing

2.5

Output Sink Current

2.2

V p .p
rnA
27

_Positive Supply Current

Notes: 1. Pins GIA and GIB connected together.
2. Pins G2A and G2B connected together.
3 Gain select pins left open.

5·64

rnA

pA733
733C ELECTRICAL CHARACTERISTICS (TA = 25°C, Vs = ±6.0 V unless otherwise specified)
CONOITIONS

PARAM ETER (see definitions)

MIN.

TYP.

MAX.

UNITS

Differential Voltage Gain

Gain 1 (Note 1)

250

400

600

Gain 2 (Note 2)

BO

100

120

Gain 3 (Note 3)

B.O

10

12

Bandwidth

-

RS - 50fl.

Gain 1

40

MHz

Gain 2

90

MHz

Gain 3

120

MHz

Risetime

RS = 50n, VOUT = 1 Vp.p

Gain 1

10.5

Gain 2

4.5

Gain 3

2.5

Propagation Delay

ns'
12

ns
ns

RS = 50fl., VOUT.= 1 Vp.p

Gain 1

7.5

Gain 2

6.0

Gain 3

3.6

ns

4.0

kfl.

30

kfl.

ns
10

ns

Input Resistance

Gain 1
Gain 2

10

Gain 3
Input Capacitance

Gain 2·

250

kfl.

2.0

pF

Input Offset Current

0.4

5.0

/lA

Input Bias Current

9.0

30

/lA

Input Noise Voltage

RS

= 50n, BW

= 1 kHz to 10 MHz

12

/lV rms
V

±'1.0

Input Voltage Range
Common Mode Rejection Ratio

Gain 2

VCM = ±'1 V, f<;;100'kHz

Gain 2

V CM = ±'1 V, f = 5 MHz

60

86

dB

60

dB

70

dB

Supply Voltage Rejection Ratio

Gain 2

50

:::"VS = ±'0.5 V

Output Offset Voltage
Gain 1
Gain 2 and Gain 3

0.6

1.5

0.35

1.5

V

3.4

V

Output Common Mode Voltage

2.4

2.9

Output Voltage Swing

3.0

4.0

Output Sink Current

2.5

3.6

Output Resistance

20

Power Supply Current

lB

V

V p .p
rnA
fI.

2¢

rnA

The following specifications apply for OoC ~ TA ~ ±70oC
Differential Voltage Gain

Gain 1 (Nole 1)

250

600

Gain 2 (Note 2)

BO

120

Gain 3 (Note 3)

B.O

12

B.O

Input Resistance-Gain 2

kfl.
6.0

Input Offset Current

40

Input Bias Current

V

±'1.0

Input Voltage Range

JJA
JJA

Comm.on Mode Rejection Ratio

Gain 2

VCM= ±'1 V,f<;;l00kHz

50

:::"VS = ±'0.5 V

50

dB

Supply Voltage Rejection Ratio
Gain 2

dB
1.5

Output Offset Voltage (All Gain)
Output Voltage Swing

2.8

Output Sink Current

2.5

rnA
27

Power Supply Current

Notes: 1. Pins G1A and G1B connected together.
2. Pins G2A and G2B connected together,
3. Gain select pins left open.

5-65.

V
V p .p
rnA

IJA740
FET.lnput
Operational Amplifier
FEATURES
•
•
•
•
•
•

High input impedance ... 1 MQ
No frequency compensation required
Short·circuit protection
Offset voltage null capahil,ity
Large common·mode and differential voltage ranges
No latch up

GENERAL DESCRIPTION
The' 740 is a high perfor,mance1monolithic FET -Input
Operational Amplifier epitaxial process, It is intended for
a wide range of analog applications where very high input
impedance is required and features very low input offset
current and very low input bias current. High slew rate,
high common mode voltage range and absence of '.'Iatch up"
make the 740 ideal for use as a voltage follower. The high
gain and wide range of operating voltages provide superior
performance in active filters, integrators, summing amplifiers, sample and holds, transducer amplifiers, and other
general feedback applications. The 740 is short circuit
protected and has the same pin configuration as the 741
operational amplifier. No external components for frequency compensation are required as the internal 6 dB/
octave roll-off insures stability in closed loop applications.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±22V
Internal Power Dissipation (Note 1)
500mW
Differential Input Voltage
±30V
Input Voltage (Note 2)
±15V
Voltage between Offset Null and V+
±0.5V
Storage Temperature Range
-65°C to +150°C
Operating Temperature Range
Military (740)
_55°C to +125°C
,Commercial (740C)
O°C to +70°C
Lead Temperature (Soldering, 60 seconds)
300°C
Output Short-Circuit Duration (Note 3)
Indefinite

m

PIN CONFIGURATIONS
(outline dwg TO-99)

ORDERING INFORMATION
Temperature Range

Package_

Commercial

Dice

j.LA740CID

Military

Dice

JLA740M/D

Commercial

TO-99
Can
TO-99
Can

j.LA740HC

Military

NC

Order number

JL740HM

NOTE:

EQUIVA,LENT CIRCUIJ

5-66

Pin 4 Connected to Case.

U~UIL

JlA740
740M

ELECTRICAL CHARACTERISTICS (VS = ±15V, TC = 25°C unless otherwise
CONDITIONS

PARAMETER

specifi~d)

MIN.

TYP.

MAX.

UNITS

10

20

mV

Input Offset Current (Note 4)

40

150

pA

Input Current (either input) (Note 4)

100

200

Input Offset Voltage

RS'; 100kn

Input. Resistance

pA
Mn

1

Large Signal Voltage Gain

50,000

RL" 2kn, VOUT = ±10V

1

Output Resistance -

75

n

Output Short·Circuit Current

20

mA

Common Mode Rejection Ratio

dB-

80

64

Supply Voltage Rejection Ratio

70

300

jlV/V
mA

Supply Current

4.2

5.2

Power Consumption

126

156

Slew Rate

6.0

Unity Gai~ Bandwidth

3.0

MHz

110

ns

-'

Risetime

Transient Response
(Unity Gain)

mW
V!jlS

CL'; 100pF, RL = 2kn, VIN = 100mV
Overshoot

20

10

%

The following specifications apply for TC = -55°C to +85°C:
±12

±10

Input Voltage Range
Large Signal Voltage Gain

V

25,000

Output Voltage Swi~g
Input Offset Voltage
Input Offset Current

RL ;;'10kn

±12

±14

V

RL;;' 2kn

±10

±13

V

15
30

30

pA

TA=+85°C

185

- pA

TA=-55°C

Inp~t Current (either input)

mV

RS'; 100kn
TA=-55°C

TA = +85°C_

2.5

200

pA

4.0

nA

,
VOLTAGE OFFSET
NULL CIRCUIT

.~
.
3V
2

TRANSIENT RESPONSE
TEST CIRCUIT

VOUT

~>-

'.r'

5

6

,

5·67 -

740

6

CL:

D·,

-::

,.A740
740C
ELECTRICAL CHARAC-r:ERISTICS (VS = ±l~V, TC = 25°C unless otherwise specified)
P.o.RAMETER

CONDITIONs

MIN

TYP

MAX

UNITS
mV

30

'110

Input Offset Current (Note 41 '

60

300

pA

Input, Current (either input) (Note '4)

0.1

2.0

nA

Input Ofiset'Voltage

RS'; 100Hl'

Input Resistance

MS'!,

1

Large Signal Voft"ge Gain'

20,000

RL" 2kS'!, VOUT = .,0V

Output Resistance

1
75

S'!

Output Shori:Circuit Current

20

,mA

Supply Current

4.2

S.O

mA

Power. Consumption

126

' 240

mW

Slew Rate

6.0

VII's

Unity Gain Bandwidth

1.0

MHz

Transient Response
(Unity Gain)

Risetime

,

300
CL ';100pF,RL =2kS'!, VIN = 100mV

, ns

,

Overshoot

10

%

The following specifications apply for O°C .; TA .; +70°C:
Input Voltage

Rang~

Comm,on Mode Rejection Ratio

.,0

,,'12

V

,55

SO

dB

Supply Voltage Rejection "Ratio

70

Large Signal Voltage Gain
Output Voltage Swing

jJVIV

RL;;' 10kS'!

±12

±14

RL" 2kS'!

±10

±13

V

30

mV

Input Offset Voltage
Input Offset Current

60

Input Curren't (either input)

1.1

NOTE 1:
NOTE '2:
NOTE 3:
NOTE 4:

500

500,000
V

pA
10

Rating applies for ,ambient temperature to +70 'C; derate linearly at 6.3mWf C for ambient temperatures above +70° C.
For supply voltages les,s than ±15V, the absolute maximum input voltage is equal to tlie supply voltage.
~
Short circuit may be to gro\lnd or either supply. Rating applies to +125°C case temperature or +75°C ambient temperature,
Typically doubles for every 10°C increase in ambient temperature.
0

5·68

nA

t1A740
TYPICAL PERFORMANCE CURVES FOR 740 AND 740C

INPUT BIAS CURRENT AS ~
FUNCTION OF AMBIENT
TEMPERATURE

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF FREQUENCY

4. a

J.

5

10 7

Vs ~ '15V
TA

~

10 6

25 C

'2 3. a

. 10 5

"-

~ 2. 5

a _
~ 2.

104

a

1. 5

10J

~

1. a

iD
~

o. 5

;"

a

~

10

---

-1. a
-75

-50

-25

0

25

'"

10 2

/

-0. 5

Vs" !15V
TA =25"C

"-

1

50

75

100

10

100

'" ""

lk, 10k

""

lOOk

i"

1M

10M

T A - AMBIENT TEMPERATURE - "C

f - FREOUENCY - Hz

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY

INPUT NOISE VOLTAGE AS.A
FUNCTION OF FREQUENCY

40
VS=:15V

6

,

>
,

28

~

24

<3

2a

~

16

!;
o

12

>

T A'" 25°C

1\
\

a

100

1k

10k

lOOk

1M

f - FREQUENCY - Hz

I - FREQUENCY - Hz

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

OPEN LOOP PHASE RESPONSE
AS A FUNCTION OF FREQUENCY
a

10
Vs

=

'15V

Vs = '15V

T A " 25"C

f-2

1-

-6
-8
-10

-4 5 ;\

\

r"

\

-~JTPUT
.-'

-4
I-~

TA "25'C

,

INPUT

-90

\

-\.1-

-135

I
I

-18a

TIME - #$

10

100

lk

10k

lOOk

f _ FREQUENCY - Hz

5-69

1M

10M

741
Operational Amplifier

GENERAL DESCRIPTION
The 741 and 741C are general purpose operational amplifiers which feature improved performance over industry
standards like the LM709. They are direct, plug-in replace"
ments for the 709C, LM201, MC1439 and 748 in most
applications.
The offset voltage and offset current are guaranteed over
the entire common mode range. The amplifiers also offer

many features which make their application nearly foolproof: oyerload protection on the input and output, no
latch-up when the common 'mode range is exceeded, as
well as freedom from oscillations.
The 741C is identical to the 74iexcept that the 741C has
its performance guaranteed over a O°C to 70°C tempera'
ture range, instead of-55°C to 125°C.

PIN CONFIGURATIONS

METAL CAN

a PIN MINI DIP

(outline dwg TO-99)

(outline dwg PAl

NC

NC

OFFSET NU!.-L
,INVERTING INPUT

INVERTING INPUT

2

NON·INVERTING INPUT

2.~7

3-V'l- 6

V+

OUTPUT
OFFSET NULL

V'

TOP VIEW

. NOTE: PIN 4 CONNECTED TO BOTTOM OF PACKAGE

NOTE: PIN 4 CONNECTED TO CASE
I

:

14 PIN DIP
(outline dwg, JD, PD)

•

10 PIN FLATPACK
(outline dwg FB)
NC

,.

NC

NC

NC

NC

13

NC

OFFseT NULL

NC

OfFSET NULL

3~12
4
11

NC

v+ '

IN~ERTING INPUT--'--I,....

INVERT IN

OUTPUT

NON·INVERTING INPUT--.----.,.:..oV'

NON·INVERT IN

OFFSET NULL

5

+

,

V-

OFFSET NULL

NC

a·PIN
MINIDIP

14 PIN
PLASTIC

14 PIN
CERDIP

10PIN
FLATPACK

LM741CN

LM741CN·14

LM741J
LM741CJ

LM741CJ

I'A741PC

I'A741DM
f.!A741DC

I'A741FM

LM741
LM741C

LM741H
LM741CH

I'A741
IlA741C

I'A741HM,
I'A741HC

I'A741TC

AD741
AD741C

AD741H
AD741CH

AD741CN

ICL741
ICL741C

ICL741MTY
ICL741CTY

ICL741CPA

(

ICL741CPD

5-70

v'
OUT

NC

ORDERING INFORMATION
TO-99
CAN

10

ICL741MJD
ICL741CJD

ICL741MFB

741

D~DIb

ABSOLUTE MAXIMUM RATINGS
Supply Voltage 741
741C
Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration
Operating Temperature Range 741
741C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

±22V
±18V
500 mW
±30V
±15V
, Indefinite
-55°C to 125°C
O~C to 70°C
~65°C to 150°C
300°C

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

ELECTRICAL CHARACTERISTICS (Note 3)
PARAMETER

741

CONDITIONS

MIN.

TYP.

741C
MAX.

MIN.

TYP.

MAX.

UNITS

Input Offset Voltage

TA = 25°C, Rs < 10 kO

1.0

5.0

1.0

6.0

mV

Input Offset Current

TA = 25°C

30

200

30

200

nA

Input Bias Current

TA = 25°C

200

500

200

Input Resistance

TA = 25°C

0,3

Supply Current

TA = 25°C, Vs =, ±15V

Large Signal Voltage Gain

TA = 25°C, Vs = ±15V
VOUT = ±10V,RL > 2 kO

Input Offset Voltage

Rs < 10 kO

1.0
1.7

50

1.0

0.3
2.8

)60

.500

1.7
25

nA
MO

2.8

160

rnA
v/mV

6.0

7.5

Input Offse1 Current

500

300

nA

Input Bias Current

1.5

0.8

f1,A

mV

Large Signal Voltage Gain

Vs = ±15V, VOUT = ±10V
RL> 2 kO

25

Output Voltage Swing

Vs = ±15V, RL = 10 kO
RL = 2kO

±12
±10

Input Voltage Range

Vs =±15V

±12

Common Mode
Rejection Ratio

Rs < 10 kO

70

90

70

90

dB

Supply Voltage
Rejection Ratio

Rs < 10 kO

77

96

77

96

dB

15
±14
±13

V/mV
±14
±13

±12
±10
±12

\/
V
V

Note 1: The maximum junction temperature of the 741 if 150 0 C, while that of the 741C is10Qo C. For operating at elevated temperatures, devices in'the TO~5
package must be derated based on a thermal r,esistance of 150°C/W, junction to case.
,'
'
Note 2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
I
Note 3: These specifications apply for Vs = ±15V and -55°C:::; TAk::::; 125 0 C, unless otherwise specified. With the 741C, ho"."'ever. all specifications are limited
to O'C'; TA'; 70'C and Vs = ±15V.
7 V

EaUIVALENT SCHEMATIC

R.
25

6 OUTPUT
RIO

50

5·71

.

ICL741HS
High Speed 741
Operational Amplifier
FEATURES
•
•
•
•

• Large Common-Mode Input Range
• Guaranteed Drift Characteristics

Pin For Pin and Electrically Equivalent to tlA741
Guaranteed Slew Rate - O.7V/J.lsMin.
Low Cost
Short Circuit Protection

• No Latch Up
• Internal Frequency Compensation

ABSOLUTE MAXIMUM RATINGS

GENERAL DESCRIPTION

Supply Voltage
±18V
Power Dissipation (Note 1)
500mW
Differential Input Voltage
±30V
'Input Voltage (Note 2)
±15V
Operating Temperature Range
O°C to +70°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature (Soldering at 60 sec.)
300°C
Output Short-Circuit Duration (Note 3)
. Indefinite

The 741HS .high slew rate version of the 741 general
purpose operational' amplifier is intended for applications
where' slew rate. performance greater than 0.3V /f,lsec is
'required. Typical applications are oscillators, active filters,
sample .and hold and other large signal applications. This
device has a guaranteed minimum slew rate' of 0.7V/f,lsec
and is identical and equivalent to the standard 741 operational amplifier. It will fill the application void between the
741 and 101 A type amplifiers (slew rate = 0.3V /f,lsec) and
the more costly high·speed amplifiers (slew rate = 30V /f,lsec).

NOTE 1: The maximum junction temperature of the 741 HS is
150°C, while that of the 741CHS is 100°C. For operating
at elevated temperatures devices in the TO-S·package must
be derated based on a thermal resistance of lS0° C/W,
junction to ambient or 4SoCfW, junction to case. For the
flat package, the derating is based on thermal resistance
of 18So C/W when mounted on a 1 f16-inch-thick epoxy
glass board with ten 0.03·inch-wide, 2-ounce copper conductors. The thermal resistance of the dual~in~line package
is 100° C/W, junction to ambient.
NOTE 2: For supply voltages less than ±lSV, the absolute maximum input voltage is equal to the supply voltage.
T A = 2So C unless otherwise speCified.
NOTE
3:
Short
circuit may be to ground or either supply.
/
.
.

HIGH-SPEED 741 OPERATIONAL AMPLIFIER

741HS

741 STD
5/lS/em

--to-

Stresses above those listed under Absolute Maximum
Ratings may cause permanent Ida mage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ORDERING INFORMATION
8 Pin
Plastic DIP

14 Pin
CERDIP

TO-99
Can

ICL741CHSPA

ICL741MHSJD

ICL741CHSTY
ICL741MHSTY

PIN CONFIGURATIONS
NOTE: AVAILABLE
IN COMMERCIAL
TEMP RANGE ONLY

NOTE: AVAILABLE
IN MILITARY
TEMP RANGE ONLY

NC

Ne

OUTPUT

INVERTING
INPUT
OUTPUT

INPUT

,OUTPUT

v-

BALANCE

v(oulline dwg PAl

(oulline dwg JD)

5·72

(oulline dwg TO·99)

ICL741HS
ELECTRICAL CHARACTERISTICS
CONDITIONS

PARAMETER

MIN

741MHS
TYP

MAX

6.0

1.0

5.0

mV
nA

741CHS
TYP

MAX

2

MIN

Input Offset yoltage

T A = 25° C, RS $ 50 kn

Input Offset Current

TA =25°C

20

200

20

200

Input Bias Current

TA=25°C

200

500

200

500

Input Resistance

TA = 25°C

Supply Current

T A = 25° C, V S = ± 15V

0.3

1.7

TA=25°C,VS=~15V

Large Signal Voltage Gain

2.0

25

VOUT = ±10V, RL ::: 2kn

0.3

160

50

RS:O; 50kn

Slew Rate

VOUT = ±10V, RL::: 2kn
CL = 50pF

Input Offset Current

TA = 25°C

0.7

Large Signal Voltage Gain

Vs = ±15V, VOUT = ±1.0V
RL::: 2kn

Output Voltage Swing

Vs = ±15V,

15
±12
±10

RL = 10kn
RL = 2kn

0.7

mA
V/mV

6

1.0

Input Bias Current

2.8

160

7.5

Inpui Offset Voltage

nA
Mn

1.0

l.r

2.8

UNITS

1.0

mV
V/lJsec

300

500

nA

0.8

1.5

IJA

,

V/mV

25
±12
±10

±14
±13

±14
±13

V
V

Input Voltage Range

Vs = t15V

±12

Common Mode Rejection Ratio

RS:O; 50kn

70

90

70

90

dB

Supply Voltage Rejection Ratio

RS:O; 50kn

77

96

77

96

dB

m~,""

DEFINITION OF TERMS
INPUT OFFSET VOL TAGE: That voltage which must be
applied between the input terminals through two equal
resistances to obtain zero output voltage.

V

±12

~"bmu'"
w
'"0z

lk

10k

lOOk

10

~

"--"

0.1

,...

_"'MAX

i;'i

'"'"::>

u

w

TYP

.1---

'"0

.~

"-

100

lk

10k

FREQUENCY (Hz)

~

0-01
10

TOOk

~
p"-:
'"~
MAX
---.TYP

w

0'"
z

0.01
10

0.1

u

TYP

z.

0.01

. lOOk

~

W

10

. MAX

~

CJ

10

..J

w

~

1.
w

TYP

CJ

,...

i;'i

tOB/30B INPUT REFERRED
VOLTAGE NOISE
100

lk

100

10k

. lOOk·

10

ORDERING INFORMATION
PART
NUMBER

TYPE

PACKAGE

TEMPERATURE
RANGE

ORDER
NUMBER

741·LN
·741C·LN
74HN

MIL
COM
MIL

TO:99
TO·99
14 Lead DIP

-5SoC to +12SDC
. oDe to + 700e
_55°C to + 125°C

ICL74TLNTY
ICL741CLNTY
ICL741LNJD

741C·LN
74HN
101A·LN

CQM
MIL
MIL

8 Lead DIP
FLATl'ACK
TO·99

ctCto"+ 700 e
. -5SoC to +12SoC
-5SoC to +12SoC

ICL74tCLNPA
ICL741LNFB
ICL101ALNTY

301A·LN
101A·LN
301A·LN

COM
Mil
COM

TO·99
14 Lead DIP
.8 Lead DIP

-5SoC

100 e

ICL301ALNTY
ICL101ALNJD
ICL301ALNPA

101A·LN
108·LN
308·LN

MIL
MIL
COM

FLAT PACK
TO·99
TO·99

_5S o c to +12SoC
-5SoC to +12SoC
oDe to + 70De

ICL10tALNFB
ICL108LNTY
ICL308LNTY

oDe to +

5-76

70°C

to +12SoC

o°c to +

100

lk

10k

FREQUENCY (Hz)

FREQUENCY (Hz)

lOOk

ICL741LN, ICL741CLN, ICL101ALN, ICL301ALN, ICL108LN, ICL308LN
NOISE IN OPERATIONAL AMPLIFIERS
VOL TAGE NOISE: The noise due to the equivalent input
voltage generator is measured using the circuit shown in
Figure 1. It is expressed in nV/$z.
CURRENT NOISE: The noise due to the equivalent input
current generator is measured using the circuit in Figure 2.
It is expressed in pA/y'HZ. Popcorn noise cannot be effec·
tively screened using this test due to its erratic nature and
very low frequency.

FIGURE ,.

POPCORN NOISE: Popcorn noise, sometimes referred to
as burst noise, is a low frequency noise phenomenon in
which the output 'of the amplifier appears to jump errati·
cally between two or more stable states. It is most noticeable when operating at high source impedances and is
expressed as a transition amplitude, in J1V, for a given
source resistance. The test circuit of Figure 3 is used.
The noise of an amplifier may be expressed in terms of an
input referred voltage generator (en) and an input referred
current generator (in), see Figure 4. The total noise of an
amplifier in a typical application contains contributions
from both these generators, together with a contribution
from the source resistance. The total mean square noise
for a bandwidth of 1 Hz is given by:

FIGURE 2.

o
FIGURE 3.

II

111. A2

.'~

(1 )

Since both en and in are frequency dependent, the total
mean square noise for a given bandwidth L'lf ; f 2 :" f, is
given by:
e2 T

;ff2

2

e2 n df + R 2 sJ f
f,
f,

i2 n df + 4kTRs L'lf

FIGURE 4.

(2)

With most amplifiers, the voltage noise term dominates for
low source impedances. The current noise term is dominant
at higher source .impedances.
To specify operational amplifier noise performance one of
two methods is used. One is to specify the total input
referred noise for a given bandwidth and source imped·
. ance. This is defi ned as eT from equation 1 above. 'The test
circuit in Figure 5 is used. The typical broadband noise of
the 741 and 101A type amplifier is shown in Figure 5.
The second method is to guarantee specific values of en
and in (in equation 2) at various frequencies. A Noise
. Analyzer is used for th is measurement (F igure 3). The
values of en and in (for L'lf =' 1 Hz) are measured at 10Hz,
100 Hz, 1 kHz, 10 kHz and 100 kHz. The recorded values
may be plotted graphically, as shown on page 1. The noise
information obtained from these measurements is considerably more general than that obtained from the first method,
since the noise for any source impedance and bandwidth
may be calculated from equation 2. (Graphical integration
can determine the area under each curve.)

FIGURE 5.

741/101A BROADBAND
NOISE FOA VARIOUS
BANDWIDTHS

100

10

I 1111

=

-

10-100 kHz
10-10 kHz

10-1 kHz

0.1
100

1k

10k

SOURCE RESISTANCE

FIGURE 6.

5·77

lOOk

n

ILA748
Operational A~plifier
ABSOLUTE MAXIMUM RATINGS

FEATURES

Supply Voltage ............................. ±22 V
.
Internal Power Dissipation (Note 1)
Metal Can .............................. 500 mW
DIP ......................... ·.......... 670 mW
Mini DIP ............................... 310 mW
Differential Input Voltage .................... ±30 V
Input Voltage (Note 2) ....................... ±15 V .
Storage Temperature Range '
Metal Can, DiP ................... -65°C to +150°C
Mini DIP .................... ~. -55°C to +125°C
Operating Temperature Range
. Military (748) ............. ; .. ~55°C to +125°C
Commercial (748C) , ............. , O°C to + 70°C
Lead Temperature (Soldering, 60 Seconds)
,
Metal Can~....... . . • . . ••••••• . . . . . . . •• . •• • . .• 300°C
Molded DIPs ....••.................. ; ..... 260°C
Output Short Circuit Duration '(Note 3) ... :.. Indefinite

• Short-circuit protection
• Offset voltage null capability
• Large, common-mode and differential voltage
ranges
• Low power consumption
• No latch up

GENERAL

B

DE~CRIPTION

The 748 is a High Performance Monolithic Operation~1
Amplifier and is intended for a high wide range of analog
applications where tailoring of frequency characteristics is
desirable. High common mode voltage range and absence of latch-up make the 748 ideal fo-' use as a voltage.
follower. The high gain and wide range of operating voltages provide superior perfo~mance in integrator, summing amplifier, and general feedback applications. The
748 is short-circuit protected and has the same pin configuration as the popular 741 operational amplifier. Unity.
gain frequency compensation is achieved by means of a .
. single 30 pF capacitor. For superior performance, see
,777 data sheet.

NOTES:

.

.

1'. Rating applies to ambient temperatures up to 70·C. Above 70°C
ambient derate linearly at 6.3 mW/o C for metal can, 8.3 mW/~C for
the DIP and 5.6 mW/oC for the mini DIP.
2. For supply voltages less than ±15V, absolute maximum input"
voltage is equal}o the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies to
+125·C case temperature 'or.+75·C ambient temperature.

PIN CONFIGURATIONS
a·LEAD MINI DIP
OFFSET

FREQ.

NULL

COMP

·IN
+IN
v-

8-LEAD METAL CAN

(outlin" dwg PAl

(outline dwg TO-99)

v+

OUT
OFFSET
NULL

vNOTE: Pin 4 connected to case

ORDERING INFORMATION
Part
Number

Temperature
Range

1LA748C

O"C to +7O"C

p.A748M
p.A748HM

}TOP VIEW)

5·78

-55'C to +125"C

Package

Order
Number

Dice

p.A748C/D

TO·99 can
8 pin minidip
Dice
TO-99 can

1LA748HC
p.A74BTC
"A748M/D·
p.A748HM

D~DIL

ILA748
.748 ELECTRICAL CHARACTERISTICS (Vs

= ±1S V, T A = 25·C, Cc = 30 pF unless otherwise specified)
TYPo

MAX.

UNITS

1.0

5.0

mV

Input Offset Current

20

200

nA

Input Bias Current

80

500

. PARAMETERS (see definitions)
Input Offset Voltage

CONDITIONS

MIN •

Rs .;;10 kfl

Input Resistance

0.3

Input Capacitance

2.0

pF

±15

mV

150,000

V/V

. Offset Voltage ~djustment Range
RL;;.2 kn~ VOUT.= ±10 V

Large·Signal Voltage Gain

50,000

nA
Mfl

2.0

Output Resistance

75

fl

Output Short-Circuit Current

25

rnA

Supply Current.

1.9

2.8

rnA

Power Consumption

60

85

mW

Transient Response
(Voltage Follower,
Gain of 1) .

VIN = 20 mV, Cc = 30 pF, RL = 2 kfl, CL .;;100 pF
Rise Time
Overshoot

Slew Rate,
(Voltage Follower, Gain of 1)
Transient Response
(Voltage Follower,
Gain of 10)

.'

RL;;.2kfl

VIN = 20 mV, Cc = 3.5 pF, RL = 2,kfl, CL .;;100 pF

Rise Time

/LS

5.0

%

0.5:

V//Ls

,0.2

..

Overshoot
Slew Rate
(Voltage Follower, Gain of 10)

0.3

RL ;;.2 kfl, Cc = 3.5 pF

5.0

/Ls
%

5.5

V//Ls

The following specifications apply for -55°C.;; TA';; +125°C:
Input Offset Voltage
Input Offset Current
Input Bias Current

Rs.;; 10 kfl

1.0

6.0

mV

TA = +125°C

10

200

nA

TA = -55°C

50

500

nA

TA = +125°C

0.03

0.5

/LA

0.3

1.5

/LA
V

150

/LV/V
V/V

TA = -55°C

Input Voltage Range
Common Mode Rejection Ratio

Rs .;;10 kfl

Supply Voltage Rejection Ratio

As .;;10 kfl

Large Signal Voltage Gain

Supply Current
Power Consumption

VOLTAG~

OFFSET NULL CIRCUIT

v.

±13

70

90
30

RL;;.2 kfl, VOUT';' ±10 V

Output Voltage Swing

±12

dB

25,000

RL ;;.10 kfl

±12

±14

RL;;.2kfl

±10

±13

V
V

TA = +125°C

1.5

2.5

TA = -55°C

2.0

3.3

rnA

TA = +125°C

45

75

mW

TA = -55°C

60

100

mW

-20V

GAIN TEST CIRCUIT

y.-

+2DV

rnA

AVO = yiN x 10 3 = 10 x 10 3
VOUT ('

VOUT

1 kO

·50n

DIGITAL
. YOL TMETERI 0.47 j.&F

1""

SUGGESTED

VIN

D.C. INPUT
(:t10VI

50kO
0.01%
5.1MO

VOUT

FOR VIN SPECIFIED

50kO

500
0.1%

......J\,f\~--oV--.

2kO

500
0,1%

25kO

TOLERANCE OF

ALTERNATE

+16V

5-79

All UNMARKED
RESISTORS IS t%

~

p;A748

D~DIl.

748C ELECTRICAL CHARACTERISTICS (Vs
PARAMETEI:tS
Input Offset Voltage
Input Offset Current' ,

= ±15 V, TA =25°C, Cc = 30 pF unless otherwise specified)

CONDITIONS

MIN.

Rs ,,;;10 kfl

Input Bias Current
Input Resistance

0.3

Input Capacitance
Offset Voltage Adjustment Range
Large Signal Voltage Gain
Output Resistance
Output Short-Circuit Current

RL;;;;2 kfl, VOUT

= ±10 V

20,000

20
80
2.0

200.
500

VIN

Rise Time

RL;;.2 kfl

VIN

= 20 mY, Cc = ~.5 pF,

IL

= 2 kfl, CL ,,;;100 pF

Overshoot
Slew Rate
(Voltage 'Follower, Gain of 10)

Rt;;.2 kfl, Cc

The following specifications apply for O°C ,,;; TA ,,;;
Rs,,;; 10 kfl
Input Offset Voltage

= 3.5 pF

mA
mW

ILf/
%

0.5

V/ILS

0.2
5.0

ILS
%

5.5

V/ILS

+ 70°C:

Input Voltage Range

Output Voltage Swing

mA
2.8
85

0.3
5.0

InpurOffset Current
Input Bias Current
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large Signal Voltage Gain

V/v
fl'

= 20.mV, Cc = 30 pF, RL = 2 kfl, CL ,,;;100 pF

Rise Time

Slew Rate
(Voltage Follower, Gain of 1)

UNITS
mV
nA.
nA
Mfl
pF
mV

150,000
75
25
1.9
60

Overshoot

Transient Response
(Voltage Follower,
Gain of 10)

MAX.
6.0

2.0
±15

Supply Current
Power Consumption
Transient Response
(Voltage Follower,
Gain of 1)

TYP.
2.0

,

Rs,,;; 10l

60

u

40

;:

!i01

ffi
;:

~

I
1

20

/'
./

V

4

/

2

j
I

15

8
0.1

20

;}
0.2

0.5

1.0

5.0

2.0

10

LOAD RESISTANCE - kU

748C FREQUENCY
CHARACTERISTICS AS A
FUNCTION OF
AMBIENT TEMPERATURE

748 FREQUENCY
CHARACTERISTICS AS A
FUNCTION OF
AMBIENT TEMPERATURE

FREQUENCY.CHARACTERISTICS
AS A FUNCTION OF .
SUPPLY VOLTAGE
1.4

I

r--.. ~~ SLE~RA~E
P p- ~ I I

.......
1.0

0.8

1.10

.q'l'0~0~

l/Of~
I I I

/

0.6-60

-20

20

Vs

Vs = ±1SV '

lI~
~~€
S\'Y,~

1.2

INPUT NOISE VOLTAGE
AS A FUNCTION OF
FREQUENCY

/

6

SUPPLY VOLTAGE _ ±V

SUPPLY VOLTAGE -± V

V

0

V
10

15V
25'C

A

.1/

E
1

~

20

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

TA = 25°C

0

15

10

SUPPLY VOL lAGE - 'V

120

Z

05

SUPPLY VOLTAGE - ! V

POWER CONSUMPTION
AS A FUNCTION OF
SUPPLY VOLTAGE

100

2

8

SUPPLY VOL rAGE - :tV'

;:

/

Z

0

20

/

4

~

o

/
/

o

85
80

".-

/

6

w

/'

8

TA = 25"C

14

60

TEMPERATURE _.

F-

100

L
b
~e,'¥1

+15V

,;0

~'"

1.05

...........

w

3

">w

>
;:

g

1.00

~q..~

I

~Dol~d-

0.95

0.90 0

140

SLEW RATe

~~1'

-::::: V

c

INPUT NOISE CURRENT
AS A FUNCTION OF
FREQUENCY

=

.~'1-0"'0,I~

10

20

30,40

50

60

70

TEMPERATURE -"C

!.

BROAD BAND NOISE FOR
VARIOUS BANDWIDTHS
lOa

1

Vs = t15V
TA ':' 25°C

f-

ii:

~
~

10.~0~klJ,

10

[;]

to· 10kHz ==

a:

,

lQ.lkH

'*'"
a:

w

--

=
/'

15
z
~

~
FREQUENCY - Hz

FREQUENCY - Hz

5-82

.1

100

lk

10k

SOURCE RESISTANCE - 52'

tOOk

JLA748
TYPICAL PERFORMANCE CURVES FOR 748 AND 748C
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
.
FREQUENCY
Vs ,. t15V
TA' '" +25"C

'0o -=::- f-I
Z

;;

g

''-,

"

60
AL -= 2kfJ:

"
~

!'-" ~

80

w

0-

"c '30F

~
~"'.......

'-","

-20

~

102

24

r'\

"c • 30pF

-21 0

10 7

10

102

-10 3

u1'

105

lQ4

'

., i

i

, til

\i

I

,

10k

1k

I

1\ Cc • 30F
I

:~lJ j
. iN..
'1111'-

II

o

,

TA '" 25°C
RL ;:. 10kU

\e.;. 300F

: 1"

:! .
':1
10 7

Vs ":15V

,

,M

100k

10M

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
GAIN/COMPENSATION OPTIONS

FREQUENCY RESPONSE
FOR VARIOUS
CLOSED LOOP GAINS

COMPENSATION CAPACITANCE
AS A FUNCTION OF
CLOSED LOOP VOLTAGE GAIN

'20

r-,--,---,---,---,--,---.

'20

,00

I-',,<--,,,,-+-+-

100

80

50
Vs = ,~15V

I-'--t---"t-'

\

z

~

>U

'"~

~

Cc "20F

u

'~OpF

"'"

1

10

100

lk

10k

lOOk

I

'\
I'"
r~

0

>=

'p\

"c '50F

5.0

z

"c'30~~
"c

10

Vs '" ~15V
TA '" 25°C
RL ,. 2krt

1\

20

u

Co • 10F

~-20

~

2.0

~

'.0

1--- 20%

NO OVERSHobr
~L< 100pFl
¥

1--- _.,

'''-

OVERSHOOT

fli

I

I

f": ~

0

u

1M

U o

10M

w

w •

--=: =:::::::",

w w ro

u

FREQUENCY - Hz

fREOuENCY • Hz

CLOSED LOOP VOLTAGE GAIN - dB

INPUT RESISTANCE AND
INPUT CAPACITANCE AS A
FUNCTION OF FREQUENCY

OUTPUT RESISTANCE
AS A FUNCTION OF
FREQUENCY

COMMON MODE REJECTION
RATIO AS A FUNCTION OF
FREQUENCY

'OM

Vs ,.

~15V

!g

TA = 25"C

I
0

~
~

,

0

:l
to
illa:

600

Vs '" !15V
TA '" 25"C

A'N

1M

,

00

III

c:

500

, iii
I I

I
w

u

z

400

u
~

300

,.0 u>-~

~lOOk

iC

!::

10k

0.1
1M

lOOk

FREOUENCY - Hz

VOLTAGE FOLLOWER
TRANSIENT RESPONSE
(GAIN OF1)

0

II

,

o

100

a:
w

100

1k

70

~

, ".

200

!::

100

80

~

1k

10k

II - ~
lOOk

,M

TA '" 25'C
CL '" 30pF

\.

50

\.

40
30

z

20

">'

'0

0

ct-

""

60

0

.>'

Yf

Vs - ·15V

90

>=

z

,i,

I

'00

a:
0

:0

C LN -

'Ok

I
w

80

;;
w

r-----t--t--t-"i..

~
~

TA = 25"C
RL = 10kn

I

40

I
~

'6

\.

II

I

I

FREQUENCY - Hz

"

~

32

-180

,-\

106

-

II

FREaUENCY - Hz

60 I-'--t---+-~

~

105

TA =+25"C
Rs=50U

fREQUENCY - Hz'

«

"w

10 4

10 3

- -

-'50

\

'1,

Vs '" : 1SV

-90
-110

,

Al '" 2kB

·l~~.,~

Cc "'30p~_

20

10

\

-6o
AL = 2kn

... ....

_

~~ <;; =3pf

-3 o

~

4

1

..-........

Rs '" son
I--

0

z

40

0

12 0

'i!

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY

OPEN LOOP PHASE RESPONSE
AS A FUNCTION OF
FREQUENCY

'\

0

"

10

100

lk

10k

1M

lOOk

FREQUENCY - Hz

FREQUENCY - Hz

TRANSIENT RESPONSE
TEST CIRCUIT

VOLTAGE FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE

10M

28
24
20
90%

~
I

>::>

i':
::>
o

16

'2

I
I

,

I

'0%;"
f--i RISE ITIME

'---

Vs '" .t15V
TA '" 25"C
RL = 2kU

L' --

'.0

1.5,

2.0

"7;0=
Co' 30F

C l '" 100pF

.5

I

I

. -'0 "-'-..L-1.--L-L-I...--'---LI-"-J

o

2.5

TIME-f,lS

10

20 30 40 50 60 70 80 90
TIME.-j.lS

5-83

D~DI!"

'JLA748
TYPICAL PERFORMANCE CURVES
FEED FORWARD COMPENSATION

LARGE SIGNAL FEED FORWARD
TRANSIENT RESPONSE

10ka

'0
7.5

TA .. 25°C

>

I
~

5.0

~
!;
I!:

10kn

V,N

O---'V'I'v---.........- - - - I

.... -.

Vs '" t15V
Cl '" 10pF

r

II

2.5

I\

13

>-.....- -....,...--0 VOUT
~2.50

1.0

2.0

3.0

4.0

5.0

6.0

RESPONSE TIME-lIS

150 pF

TYPICAL APPLICATIONS
PULSE WIDTH MODULATOR

·~~~-~~~-e-----+-,s-V--_'-SV---JV~--~
~

.~

_~

'OO~

...----+---0 VOUT
R3
10kn

c,
O.47 P

FI
0,
6.2V

RS

100n

°2

fc

< fn < funity

gain

6.2V

PRACTICAL DIFFERENTIATOR

CIRCUIT FOR OPERATING THE 748
WITHOUT A NEGATIVE SUPPLY

+20V
+15V

'-15V.

>---.....- - - 0

VOUT

Your
30 pF

t

5-84

j.tA777
Precision Operational Amp. ifier

FEATURES

GENERAL DESCRIPTION

• Low offset voltage and offset current

The p.A777 is a monolithic Precision Operational
Amplifier. It is an excellent choice when performance .
versus cost trade-offs are possible between super beta
or FET input operational amplifiers and low cost general purpose operational amplifiers. Low offset and
bias currents fmprove system accuracy when used in
applications such as long term integrators, sample and
hold circuits and high source impedance summing
amplifiers. Even though the input bias current is extremely low, the p.A777 maintains full ±30V differential
voltage range. High common mode input voltage
range, latch-up protection, short circuit protection and
simple frequency compensation make the device versatile and easily used.

• Low offset voltage and current.drilt
• Low input bias current
• Low input noise voltage
• Large common mode and differential voltage ranges

ABSOLUTE MAXIMUM RATINGS
.Supply Voltage
Internal Power Dissipation (Note 1)
Metal Can
Differential Input Voltage
Input Voltage (Note 2)
-65°C to
Storage Temperature Range
O°C
Operating Temperature Range (HC)
(HM)-55°Cto
Lead Temperature (Soldering, 10s)
Output Short Circuit Duration (Note 3)

±22V

500mW
±30V
±15V
+150oC
to 70°C
+125°C
300°C
260°C
Indefinite

PIN CONFIGURATION
8-LEAD METAL CAN
(TOP VIEW)

Note 1: Rating applies to ambient temperatures up to 70°C. Above
70°C ambient derate linearly at 6.3mW/oC for Metal Can,
8.3mW/oC for the DIP, and 5.6mW/oC for the Mini DIP.
Nole 2. For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.

>--~OUT

Nole 3. Short Circuit may be to ground or either supply. Rating
applies to +125°C case temperature or +75°C ambient
temperature fOr!sET ::; 30!,A.

v(outline dwg TO·991

ORDERING INFORMATION
Dice
! O.B
l;;

~-+-+--t~-+-+-__1

~ 0.6 f-,--+-+--t--+-+-__1

~OA~-+~+--t--+-+-__1

"

~ 0.2 ~-+-+--t--+-+-__1
O~~_~~_~_~_J

5

.

.10
.15
SUPPLY VOLTAGE - tV

20

o

I 30

~ 0.5

1'\

I-

a: 25
<>

".

I-

20

0.2

20
40
60
80
. TEMPERATURE _ °C

100

8Or-r-r-,-,-,-,----r-,-,--,
~~HHHH-VS = t15V
RL =~
~ 70~HHHH-t~~~__1
~,_+_+_+_+4-4-1-1-+-4

60

r-......

80

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

> 28

Vs - ±15V

I

TA = 25"C

'"

~ 24

/

ill

50 I--iH--+-+-+r----P*
.......
-t-+-l

~ 40~~HHH-t-t-t-+__1
~

30L-L-~~~~~~~_J

-20

20

60

TEMPERATURE _

100

(Ie

140

5

~ 16

~

12

:li..

8

/
0.1 0.2
0.5 1.0 2.0
5.0
LOAD RESISTANCE - kll.

•

Vs = ±15V

i"

5 :::-

'" "

r-- ~

~ <:::- in2
1

c:;

o

iIi

10

INPUT NOISE VOLTAGE
AND CURRENT AS A
FUNCTION OF FREQUENCY

a:
~

100

(Ie

~ 20

<>
a:

-60

60

I-

:;;

~

40

TEMPERATURE _

;:

t:

20

Q

POWER CONSUMPTION AS
A FUNCTION OF AMBIENT
TEMPERATURE

~

l - I-

f- .......

1.0

0.1

35

15a:

§

OFFSET

OUTPUT SHORT-CIRCUIT
ClIRRENT AS A FUNCTION
OF AMBIENT
TEMPERATURE

E

:3a:
z

20

INPUT OFFSET CURRENT
AS A FUNCTION OF
SUPPLY VOLTAGE

I-

~

Ii; 2.0

"

r-0.1

10
15
SUPPLY VOLTAGE - tV

10

I

-

5

I

§1

BIAS

!l

1

'ii

r-Vs =±15V

I-

w 5.0

~

w

INPUT RESISTANCE AS .
A FUNCTION OF
AMBIENT TEMPERATURE

<>

a

a:

20

30

~ 10
a:

I

10
15
SUPPLY VOLTAGE - tV

5

Vs" ±15V

!;;

//

8

/

/

~. 0

20

10
15
SUPPLY VOLTAGE - tV

500
~ 100

20

Ii:

/

,

V

o
o 4
:;;
z 2

INPUT CURRENT AS
A FUNCTION OF
AMBIENT TEMPERATURE

~
TA "'2S"C

'/

5

20

POWER CONSUMPTION AS
A FUNCTION OF SUPPLY
VOLTAGE
~ 50

'/

16

.,;-

-/
/

~ 10
!:; 8
o
~ 6

V

"o

~

!:;

'a:~" 12

L

~ 24

O°C~TA <1 70oC

w 14

./

I-

~ 100

g

O"C 40

TA = 25°C
RL = 2kll

!g

INPUT COMMON MODE
VOLTAGE RANGE AS A
FUNCTION OF SUPPLY"
VOLTAGE

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE

15

10
-60

Vs -±lSV
TA, = 25°C
-20
20
60
100
TEMPERATURE _ °C

140

100
lk
10k
FREQUENCY - Hz

5-87

10-26
lOOk

pA777

·U~UIb

TYPICAL PERFORMAN.CE CURVES

OPEN LOOP VOLTAGE GAIN
As A FUNCTION OF
FREQUENCY

OPEN LOOP PHASE
RESPONSE AS A
FUNCTION OF FREQUENCY

120
Vs '" ±15V

"""""

100

fg 80

z
~

~~

RL ""2kn'

w

~ 4O-C c =30pF

5

20

>

,""

I"

60

T A =+25°C

-30

Rs ·50n

m -60

RL .'2kn I----

!

~

". "'"

Q..

\

-150

120

II

C( 60
w
'" 40

'w"
"!:i'g" 20
-20

'"

ce = 2pF

-20

100M

10

'"
:;;

R'N

1M

~

~W

1

C'N

5 lOOk
10k

., I
.j

lk
100

t-.
J~OUT

1

, I

10

z
c

0

§

"""'-

Ce = 30pF

"\

0

0:

0

g

30

.:;;
Vs '" ±15V

TA " 25°C

10k
lOOk
lk
FREQUENCY· Hz

100

a0

w

III

1

~

1M

VOLTAGE FOLLOWER
TRANSIENT RESPONSE
(GAIN OF 1)

z
c

~

\C;e = 3pF

1\
Cc =30pF

·1111 I
o IIII I
lk

10k

lOOk

1M

10M

FREQUENCY· Hz

..

COMpENSATION
CAPACITANCE AS A
FUNCTION OF .CLOSED
LOOP. VOLTAGE GAIN
50

Vs '" ±16V

.TA '" 25°C
·R L = 2kn

w
\\
" 20

~

~. ~

5.0

z
c

~

i

'I. '\

10

.

, NO OV RSHboT
IC L " 100pF!

1"-.. 1-..
2.0

20%OVERSH~ :::::::: .....,
,

~ 1.0
:;;
ICL ~20~F!

80.5

o

=
"""'"

10 20 30 40 50 60 70
CLOSED LOOP VOLTAGE GAIN· dB

INPUT OFFSET VOLTAGE
DRIFT AS A FUNCTION
OFTIME

>

:" 100

Vs" t15V
TA = 25°C

LJ ·50

II I

0:

"

100 lk 10k lOOk 1M 10M
FREQUENCY· Hz

COMMON MODE REJECTION
RATIO AS A FUNCTION OF .
FREQUENCY

~ laO
c 90
>=

I

10M

~

1
1

8

~, ~

.1

FFiEQUENCY. Hz

INPUT RESISTANCE,
OUTPUT RESISTANCE,
AND INPUT CAPACITANCE
AS A FUNCTION OF FREQUENCY

~~; ~~;

ce =3Pf)~
Ce ·3bpF ce =5pFI ~

~ 20
g

1

V, • ±15V

1
ce l'pF

80

z

~

u.

l

100

'"~

16

...

10 102 10' 104 10' 10. 10'
FREQUENCY· Hz

120

z


r"\

-120

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
GAIN/COMPENSATION OPTIONS

Vs = ±16V

TA = 25"C
RL ·100kn

ii
~

Ce ·30pF

-210
1

~ 40

'" 32

!:
I-

-IBO

102 10' 104 10' 10. 107
FREQUENCY· Hz

10

-90

c

'\

-20
1

jL~~

W

ffi

Vs = ±15V

Ce. ==2kn
3pF -!A =+25°C
RS =50n

.0:

Cc = 3pF

r\

0

f\fL
~

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUEN.CY

w

~
!:;'
c
>

Iii

~

60

u.

o

"\

I-

~

.'\

0

V; • '±20V:
TA • 125°C

80

TREND LINE

40

V-

;!;

:!:

20 If

w

0

'"

.~
10

100 lk 10k lOOk 1M 10M
FREQUENCY·. Hz

TRANSIENT RESPONSE
TEST CIRCUIT

:

0

i5 . 0

200

400
600
TIME·HRS.

BOO

1000

VOLTAGE FOLLOWER
LARGE SIGNAL
.
PULSE RESPONSE

2B
24

>

20

90%

~ 16

I

I-

~ 12
B

-

I

5

-

~r-

V'N

Vs = ±1S,(
TA = 25°C

- C e ·30pF
0 - RISE1TlME _RL = 2kn
C '" l00pF
L

.0

.5

1.0 1.5
TIME· "5

2.0

-10L....J.-':--:':c--,L--'L-'-I'-:-::'I~-,J.
o

2.5·

10 20 30 40 50 60 70 BO 90
TIME·,I.Is

5-88

JlA777
TYPICAL PERFORMANCE CURVES
STABILIZATION TIME'OF INPUT OFF-SET
VOLTAGE FROM POWER TURN-ON

THERMAL RESPONSE OF INPUT OFFSET VOLTAGE
TO STEP CHANGE OF CASE TEMPERATURE
~!4'-~C

§

e~

300

...

H--'-iHj:::j::::ji=+::j:::j:::j

"fA = 2SoC

Vs; +15V

~

b~

200

:Ow

....

H---'-t.f+-+-I-t-HH-+--I

0 ..

t...-I-

~ ~ -1 0
z

7.5 CL = 10~FH-+++-H-+-I
TA = 25'CH-t-++-H-t--l

~

5.0 H-I--+++-+-H-I--Ir-H

~

...~ 2.5 H-tlI-t+-I-+-:H-+-I1+-l
\
:0

o

0

H-t-t-+-I-t--IH-+-t--H

-2.5 L..1....L...l...:-'-:-Ll....L...l...:-'-:-L..1...J

a

1.0

2.0

3.0

4,0

RESPONSE TIME

5,0

6.0

jJS

VOLTAGE OFFSET
NULL CIRCUIT

GAIN TEST CIRCUIT

DC INPUT
1;10~ FOR Vs = ;15V)
TOLERANCE OF ALL
UNMARKED RESISTORS
IS1%
10Mn

5.1Mn
25kn

SUGGESTED

ALTERNATE

5·89

p.A777
TYPICAL APPLICATIONS
BIAS COMPENSATED LONG TIME INTEGRATOR

SAMPLE AND HOLD

R ' " r r : ; ' V+

20kU

R4

V+

2.2M.Q
INPUT

R2

IN457

c,
>--6._-<> OUTPUT

30pF

*ADJUST R3 FOR MINIMUM INTEGRATOR DRIFT

CAPACITANCE MULTIPLIER

AMPLIFIER FOR CAPACITANCE TRANSDUCERS

10Mn

R,

C

. 'l

=

R;

C,

Vos + los Rl

=

--R-,--

lkf! Rs = R3

LOW FREQUENCY CUTOFF A, X C1

BILATERAL CURRENT SOURCE

HIGH SLEW RATE POWER AMPLIFIER
r---r<>+15V

INPUT

INPUT

INSTRUMENTATION AMPLIFIER WITH
HIGH COMMON MODE REJECTION

!100V COMMON MODE RANGE
INSTRUMENTATION AMPLIFIER

~::=:: ~ forbestCMRR
R7

A4

R3 = R4

R, = Ae '" lOR 3

R,

Gain =

As"

5·90

LH2101A/LH2301A
Dual High Performance
OpAmp
FEATURES
• Low offset voltage
• Low offset current
• Guaranteed drift characteristics
• Offsets guaranteed over entire common mode and
supply voltage ranges
• Slew rate of,1 OV/ MS

.GENERAL DESCRIPTION
The LH21 01 A series of dual operational amplifiers consist of
two LM101A type op amps in a single hermetic package.
Featuring all the same performance characteristics of the
single, these duals offer in addition closer thermal tracking,
lower weight, and reduced insertion cost.
The LH2101A is specified for operation over the -55°C to
+125°C military temperature range, while the LH2301A is
specified for operation over the 0° C to +70° C temperature
range.

PIN CONFIGURATION

CONNECTION DIAGRAM
.-------,.;.0 v+

OUT,

...-_ _ _...;1"'40 BALANCE.

INV
INPut

,..-_ _..:.20()

r __':;;,60

A

g~~~~~SATION

NIC

OUTPUT

BAL,

'----~ BAL/COMPENSATION

NON-INV
INPUT

-INa

+----..-!:o()VINV
INPU!

+INa

,..---"-0 BALANCE

12

o----j

10

OUTPUT
COMPENSATION

BAl/COMP.

OUTPUT

OUTCOMP.

eAL/COMPENSATION

v;

'----.:..ov+

ORDER NUMBER LH2101AD, LH2301AD
AUXILIARY CIRCUITS
ALTERNATE
BALANCING CIRCUIT

INVERTING AMPLIFIER
WITH BALANCING CIRCUIT

SINGLE POLE COMPENSATION

R1
-VIN

16,8
OUTPUT

VOUT

14,7

R3
+VIN

C,

R1
10M

30pF .

C,
30 pF

R2
5.1M .

tMav ~e zero or equal to parallel combination
of R 1 and R2 for minimum offset.

FEEDFORWARD COMPENSATION

TWO POLE COMPENSATION

R,

R1

-VIN

--"lM-+-!
16,8

VOUT

C,

~

R,es

Fij+1f2

Cs= 30 pF

16,8

C1' C2
,

21ff~

VOUT

C2;:
R2
fo""3MHz

R4
10K

C2"".10C,

5-91

U~UIL

LH2101A/LH2301A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ........................ '..................... : .... ; . . .. • .. ±22V
Power Dissipation (Note 1) ............................................ 500 mW
Differential Input Voltage ., ~ . . • • . . • . . . . . . . • . . • . • • . . • • • • • . • . . • . . . • • . • . • • • •• ±30V
Input Voltage (Note 2) •••...••..•.•....••.•..•....•••.•.••..••..•.•.•••..•. :f:15V
Output Short-Circuit Duration ....•••......••...•....• : ...... , .•••... Continuous
Operating Temperature RangeLH2101A .•.••......•••.••...•..•. -55°C to 125°C
. LH2301A ................. , ... ; ...... O°C to 70°C
Storage Temperature Range .................................... -65°C.to 150°C
Lead Temperature (Soldering, 10 sec) .................................. ~: 300°C

ELECTRICAL CHARACTERISTICS Each side (Note 3)
LIMITS
PARAMETER
Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Supply Current
Large Signal Voltage Gain

Input Offset Voltage
Average Temperature
.Coefficient of Input
Offset Voltage
Input Offset Current
Average Temperature
Coefficient of Input
Offset Current
Input Bias Current
Supply Current
Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode
Rejection Ratio
Supply Voltage
Rejection Ratio

. UNITS

LH2101A
2.0
10
75
.1.5
3.0
50

LH2301A
7.5
50
250
0.5
3.0
25

MflMin
rnA Max
VlmV Min

3.0

10

mVMax

15

30.

p.VloC Max

20
0.1
0.2

70
0.3
0.6

nA Max

100
2.5
25

300

±12
+10
±15

±12
±10
±12

Rs:550kfl

80

70

Rs:5 50 kfl

80

70

CONDITIONS
TA - 25°C, Rs < 50kfl
TA- 25°C
TA - 25°C
TA - 25°C
TA - 25°C, Vs - ±20V
TA - 25°C, Vs - ±15V
Vour= +10V, RL> 2kfl
Rs:550kfl

25°C:5 TA:5 125°C
-55°C:5 TA:5 25°C

TA - +125°e, Vs - ±20V
Vs - ±15V, Vout - ±10V
RL>2kfl
Vs - ±15V, RL - 10 kfl
RL - 2 kfl,
,Vs - ±20V

15

mVMax
nA Max

nA/oe Max
nAMax
rnA Max
VlmV Min

VMin

dB Min

Note 1: The maximum junction temperature of the LH2101A is 150°C, and the thermal resistance is 100·CIW, juriction to ambient.
Note 2: For supply voltages less than ±15V, the absolute maximum input. voltage is equal to the supply voltage.
Note 3: These specifications apply for ±5V ::s; Vs ::s; ±20Vand --55°C ::s; TA ::s; 125°C, unless otherwise specified. For the LH2301A these
specifications apply for O°C::S; TA::S; 700 q, ±5V and ::s; Vs ::s; ±15V. Supply current and input voltage range are specified as Vs = ±15V for the
LH2301A. C, = 30 pF unless otherwise specified.

5·92

LH21 08/2308

U~UIb

Dual Super Beta
OpAmp
FEATURES

GENERAL DESCRIPTION

• Low offset current - 50 pA
• Low offset voltage - 0.7 mV
• Low offset voltage - LH2108A: 0.3 mV
LH2108:
0.7 mV
• Wide input voltage range - ±15V
• Wide operating supply range - ±3V to ±20V

The LH2108A1LH2308A and LH2108/LH2308 series of dual
operational amplifiers consist oftwo LM108A or LM108 type
op amps in a single hermetic package. Featuring all the same
performance characteristics of the single device, these duals
also offer closer thermal tracking, lower weight, and reduced
insertion cost.
The LH2108A1LH2108 is specified for operation over the
-55° C to +125° C military temperature range, and the
LH2308A1LH2308 is specified for operation from 0° C to
+70°C.
PIN CONFIGURATION

CONNECTION DIAGRAM
V+
14
INV
INPUT

BALANCE
OUTPUT
COMPENSATION

2
16

v~

OUT,

OUTPUT
OUT CaMP,

3

NON-INV"
INPUT

6

INV
INPUT

10

8
NON-INV
INPUT

11

13

9

BAL/COMP,

BAL,

-IN ...

,-INa

+IN...

+IN.

V-

7

12

N/C

BAL/COMPENSATION

BALANCE
OUTPUT
COMPENSATION
OUTPUT
BAL/COMPENSATION

v-

SAL/CaMP,

SAL,

OUT CaMP,

OUTo

v~

V+
(outline dwg DE)

ORDER NUMBER LH2108AD,
LH2408AD, LH2108D,
OR LH2408D

AUXILIARY CIRCUITS
ALTERNATE*
FREQUENCY COMPENSATION

STANDARD
COMPENSATION CIRCUIT
R2

C2

R2

-VIN JVV'v~-----'lN'I("_...,

-V I N'-"IN'Ir-_----.Jw\r---,

VOUT

cp"!!l£lL
- R1+R2
Co = 30 pF
CI

FEEDFORWARD
COMPENSATION

VOUT

VOUT,

* Improves rejection
of power supply

1

noise by a factor
of ten.

C1
150 pF

5-93

C2 = 2,1 0 R2
10 = 3 MHz

LH21 08/2308
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................•...................•......... ±20V' ,
Power Dissipation (Note 1) ............................................ 500 mIN
Differential Input Current (Note 2) ............................ ',' . . . . . . .. ±10mA
Input Voltage (Note 3) ...... , ............................................ .-. ±15V
Output Short Circuit Duration ...................................... Continuous
Oper?ting Temperature Range
LH210BA/LH210B ......................................... -55°C to +125°C
LH230BAlLH240B ...... ; ................. ;................... 0° C to +70° C
Storage Temperature Range ... " ............................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................................... 300°C

ELECTRICAL CHARACTERISTICS Each side (Note 4)
LIMITS
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Supply Current
Large Signal Voltage Gain

Input Offset Voltage
Average Temperature Coefficient
o(lnput Offset Voltage
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
Supply Current
, Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Supply Current
Large Signal Voltage Gain,

Input Offset Voltage
Average Temperature Coefficient
of Input Offset Voltage,
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
Supply Current
,Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio-

CONDITIONS
TA - 25°C
TA - 25°C
TA-25°C
TA -25°C
TA - 25°C
TA - 25°C Vs - ±15V
VOUT = ±10V, RL;:::: 10 kO

TA-+125°C
Vs - ±15V, VOUT -,±10V
RL;:::: 10 kO
Vs - ±15V, RL - 10 kO
Vs ±15V

CONDITIONS.
TA = 25°C
TA - 25°C
TA - 25°C
TA - 25°C
TA - 25°C
TA - 25°C Vs - ±15V
VOUT = ±10V, RL;:::: 10 kO

LH2108
2.0
0.2
2.0
30
0.6
50

LH2308
7.5
1.0
7.0
10
O.B
25

'MO Min
mA Max
V/mV Min

3.0
15

10
30

mV Max
/lVrC Max

0.4
2.5

1.5
10

nA Max
pAloC Max

3.0
0.4
25

10

nA Max
mA Max
V/mV Min

±13
±13,5
B5
BO

±13
±14
BO
BO

"

15

LIMITS
LH2108A
LH2308A
0.5
0.5
0,2
1.0
2.0
7.0
30
10
0,6
O.B
BO
BO

1.0
5

UNITS
mV Max·

nA Max

V Min
dB Min

UNITS
mV Max

nA Max
MO Min
mA Max
V/mV Min

0.73
5

/lV/oC Max

mV Max

0.4
2.5

1.5
10

nA Max
pA/oC Max

3.0
0.4
40

10
60

nA Max
mA Max
V/mV Min

±13
±13.5
96
96

±13
±14
96
96

,

TA - +125°C
Vs - ±15V,VOUT - ±10V
RL> 10 kO
Vs - ±15V, RL - 10 kO
Vs = ±15V

-

, V Min
dl? Min

Note 1: The maximum junction temperature olthe LH2108/A is 1500 C, and that olthe LH2308/A is 85° C. The thermal resistance olthe packages
is 100° CIW, junction to ambient.
,.Note 2: The inputs are shunted witli back-to-back diodes for overvoltage protection, Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some limiting resistance is used,
Note 3: For supply voltages less than ±15V. the absolute maximum input voltage is equal to the supply voltage.
Note 4: These specifications apply for ±5V,;; Vs';; ±20V and -55° C';; TA';; 1250 C, unless otherwise specified, and the LH2308A1LH2308 for ±5V';;
VS ,;; 15V and 00 C ,;; T A ,;; 70 0 C. ,

5-94

D~DIb

LH2110/LH2310
Dual Voltage
Follower

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•

The LH2110 series of dual voltage followers consist of two
LM110 type followers in a single hermetic package:Featuring all the same performance characteristics of the single,
these duals offer in addition closer thermal tracking, lower
weight, and r!lduced insertion cost.
The LH2110 is 'specified for operation over the -55·C to
+125·C military temperature range; .and the LH2310 is
specified for operation from o·e to +70·C.

Low input current - 1 nA
High input resistance - 10 MO
High slew rate - 30v/P.s
Wide bandwidth- 20 MHz
Wide operating supply range - ±5V to ±18V
Output short circuit protected.

PIN CONFIGURATION

CONNECTION DIAGRAM

1

2
3
'rJ

4 ---I
INPUT 0-..:..

v+

:JSTER

8

INPUT 0'0'.1..:..2- - - - - I

5
9

BAL.

NC

BAL.

NC

BOOST~

IN.

v-

BOOST.

10
11-

OUT.

UTPUT

13
b

v+A

}BALANCE

} BALANCE

IN.

V·-

BAL.

NC

·BAL.

v+

OUT.

OUTPUT
BOOSTER

•

(outline dwg DE)

V+

ORDER NUMBER LH2110D or LH2310D

AUXILIARY CIRCUITS
INCREASING NEGATIVE
SWING UNDER LOAD

OFFSET

INPUT

BAL~NCING

CIRCI)IT

.....-4---v+

16,8
>-~~OUTPUT

'>--_OUPUT

16,8
INPUT

Rl> 100

v-

'May be added to reduce
internal dissipation

'5-95

II

LH2110/LH2310
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..................................•.....•................. ±18V
Power Dissipation (Note 1) ....................................•....... 500 mW
lriput Voltage (Note 2) ................................•.......••...•...... ±15V
Output Short Circuit Duration (Note 3) .....•.......•..•.......•..... Continuous
Operating Temperature RangeLH2110 .......................... -55°C to 125°C
LH2310 .............•............... O°C to 70°C
Storage Temperature Range ..............................•..... -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...............•.................... 300°C

ELEC.TRICAL CHARACTERISTICS Each side (Note 4)
PARAMETER
Input Offset Voltage
Input Bias Current
Input Resistance
Input Capacitance
Large Signal Voltage Gain
Output Resistance
Supply Current (Each Amplifier)
Input Offset Voltage
Offset Voltage
Temperature Drift
Input Bias Current
Large Signal Voltage Gain
Output Voltage Swing (Note 5)
Supply Current (Each Amplifier)
Supply Voltage Rejection Ratio

CONDITIONS
TA = 25°C
TA - 25°C
TA - 25°C
TA - 25°C, Vs - ±15V
VOUT = +10V, RL = 8 kn
TA - 25°C
TA - 25°C
-55°C < TA < 85°C
TA - 125°C
Vs - ±15V, VOUT - ±10V
RL = 10 kn
Vs - ±15V, RL 10 kn
TA - 125°C
±5V:S; Vs :s; ±18V

LH2110
4.0
3.0
10M
1.5
.999

LIMITS
LH2310
7.5
7.0
10M
1.5
.999
2.5
5.5
10
10

UNITS
mV Max
nA Max
n Min
pF Typ
V/v Min

n Max
mA Max
mV Max

2.5
5.5
6.0
6
12
10
.999

10
.999

nA Max
V/v Min

±10
4.0
70

±10
70

V Min
_ mA Max
dB Min

-

/lV/DC Typ

Note 1: The maximum junction temperature of the LH2110 is 150°C, while that of the LH2310 is 85°C. The thermal resistance olthe package is
100°C/W. junction to ambient.
Note 2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
Note 3: Continuous short circuit is allowed for case temperatures to 125° C'and ambienttemperaturesto 70° C. It is necessary to insert a resistor
greater than 2 Kn in series with the inut when the amplifier is driven from low impedance sources to prevent damage when the outpu(is shorted.
Note 4: These specifications apply for ±5V ::; Vs::; ±18V and -55° C::; T A::; 125° C, unless otherwise specified, and for the LH231 0, all temperature
specifications are limited to O°C::; TA::; 70°C.
Ndte 5: Increased output swing under load can be obtained by connecting an. external resistor between the booster and V- terminals.

5·96

LH2111,LH2311
Dual Voltage
Comparator
FEATURES
•
•
•
•
•

GENERAL DESCRIPTION

Wide operating range - ±15V to a single +~V
Low input currents - 6 nA
High sensitivity - 10 I.N
Wide differential input range - ±30V
High output drive - 50V.50 rnA

The LH2111 series of dual voltage comparators consist of
two LM111 type comparators in a single hermetic package.
Featuring all the same performance characteristics of the
single, these duals offer in addition closer thermal tracking,
lower weight, and reduced insertion cost.
The LH2111 is specified for operation over the -55° C to
+125°C military temperature range, and the LH2311 is
specified for operation from O°C to 70°C.

AUXILIARY CIRCUITS
OFFSET BALANCING

STROBING

INCREASING INPUT
STAGE CURRENT·

V+

TTL
STROBE

"Increases typical common
mode slew from 7.0flJ.s to l8V/ps.

V-

DRIVING GROUNDREFERRED LOAD

USING CLAMP DIODES
TO IMPROVE RESPONSES

COMPARATOR AND
SOLENOID DRIVER
0,
IN4QOl

.----_v+

_-.--I4..._ -__ ~~TPUT

FROM
LAOOER-t--.,....-=1
NETWORK

INPUTS"

v-

'---~-4- ANALOG INPUT

i

STROBING OFF BOTH INPUT·
AND OUTPUT STAGES

TTL INTERFACE WITH HIGH LEVEL LOGIC

FROM D/A NETWORK

R,

r----.---_-

240K
INPUT" -J\M~r-_p--j::-:-:l

V+ '" 5V

R5

'K
;:1...
'5::.:.:<
.8........_ TO TTL lOGIC

ANALOG

·Values shown are for a 0 to 30V
!ogic swing and a 15V threshold.

INPUT

-;- May be added to control speed

and reduce susceptibility to noise
spikes.

TTL
STROBE

"'Typical input current is
50 pA with. inputs strobed off.

5-97

LH2111,LH2311
CONNECTION DIAGRAM

BAL/STROBE
A
BALA

NC

VB+

ORDER NUMBER LH2111D
OR LH2311D

v~

BAL B

B.
BAL/biROBE .

ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage ....................................................•. 36V
Output to Negative Supply Voltage (VOUT - V-) ............................. SOV
Ground to Negative Supply Voltage (GND - V-) ............................. 30V
Differential Inpl,lt Voltage ., ............................................... ±30V
Input Voltage (Note 1) ........ , ....... :,' .... ,............................. ±1SV
Power Dissipation (Note 2) ............................................ SOO mW
Output Short Circuit Duration .....• -. ..... ; . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 10 sec
Operating temperature Range LH2111 .......................... -5SoC to 12SoC
LH2311 .................... ;.: ...... 0°Ct070°C
Storage Temperature Range .................................... -6SoC to 1S0°C
Lead Temperature (Soldering, 10 sec) ; ................................... 300°C

ELECTRICAL CHARACTERISTICS Each side (Note 3) .
LIMITS

I

PARAMETER
Input Offset Voltage (Note 4)
Input Offset Current (Note 4)
Input Bias Current
Voltage Gain
Response Time (Note 5)
Saturation Voltage
Strobe On Current
Output Leakage Current
Input Offset Voltage (Note 4)
Input Offset Current (Note 4)
Input Bias Current
Input Voltage Range
Saturation Voltage
~

Positive Supply Current
Negative Supply Current

CONDITIONS
TA = 2SoC, Rs S SOk
TA - 2SoC
c
TA - 2SoC
TA = 25°C
TA = 2SoC
Y,N :5-5mV, lOUT = SOmA
TA = 25°C
TA - 25°C
VIN 2: 5mV, VOUT '" _35V
TA = 25°C
Rs:5 50k

V+ 2: 4.5V, V -0
VIN :5 -5mV, ISINK :5 8 mA
TA - 25°C
TA = 25°C

LH2111
3.0
10
100
200
200
1.5

LH2311
7.S
SO
2S0
200
200
1.5

UNITS
mV Max

3.0
10

3.0
SO

mA Typ
nA Max

4.0
20
150
±14
0.4

10
70
300
±14
0.4

mVMax

6.0
5.0

7.S
5.0

nA Max
V/mV Typ

_ns Typ
V Max

nA Max
V Typ
V Max

mA Max

Note: This rating applies for ±15V supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is
, equal to the 'legative supply voltage or 30V below the positive supply, whichever is less. . Note 2: The maximum junction temperature is 150°C_ The thermal resistance of the dual-in-line package is 100°CIW, junction to ambient.
Note 3:These specifications apply for Vs = ±15V and ~5° C::; TA::; 125° C forthe LH2111, and 0° C::;TA::; 70° C for the LH2311 , unless otherwise
stated. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single5V supply up to ±15V
supplies_ For the LH2311,-VIN '" ±10V.
Note 4: The offset voltages and offset currents given are-the maximum valueS required to drive the output within a volt of either supply with a 1
mA load. Thus, these parameters define an error band _and take -into account the worst case effects of voltage gain and input impedance.
Note 5: The response time specified is for a 100 mV input step with 5 mV overdrive.
-

5·98

HA 2500/02/05/10/12/15/20/22/25
.High Slew Rate
Operational Amplifiers
FEATURES

GENERAL DESCRIPTION
The 2500 series of high slew rate operational amplifiers are
monolithic integrated circuits fabricated using dielectric isolation' and thin film resistors. These internally compensated
amplifiers feature excellent input parameters, high gain and
wide bandwidth. They are "ideally suited f()r DIA and AID
converter circuits, pulse amplifiers and high frequency buffer
amplifiers.

.• Slew Rate - Up to 120 V/p.s
• Settling Time - 200 ns to 0.1 %
• Bias Current -100 nA
• Gain Bandwidth Product - 30 MHz
• Internal Frequency Compensation
• Radiation Harde.ned

2500 through 2515 are compensated for uhity gain. 2520
through' 2525 are intended for closed loop gains of 3 or greater, and feature increased slew rates and gain-bandwidth
products.

• Meets MIL-STD-883

PIN CONFIGURATIONS

VOLTAGE OFFSET NULL CIRCUIT

)

BANDWIDTH CONTROL

OUT

v-

v-

(TOP VIEW)

. (outline dwg TO-99)

·ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

HA2500

_55°e to +125°e

HA2502

_55°e to +125°e

HA2505

oOe to +75°e

HA251 0

-55°e to +125°e

HA2512

_55°e to +125°e

HA2515

oOe to +75Oe

HA2520

.-550 e to +125°e

HA2522'

_55°e to +125°e

HA2525

oOe to +75°e

PACKAGE
TYPE
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO-99
Flat Pack
TO~99

Flat Pack

ORDER
NUMBER
HA2-2500-2
HA9-2500-2
HA2-2502-2
HA9-2502-2
HA2-2505-5
HA9-2505-5
HA2-2510-2
HA9-2510-2
HA2-2512-2
HA9-2512-2
HA2-2515-5
HA9-2515-5
HA2-2520-2
HA9-2520-2
HA2-2522-2
HA9-2522-2
HA2-2525-5
HA9-2525-5

•
•
•
,;

•
•
•
•

•
"
•
•

(outline dwg FD)

'883 processing is available for these devices.
Order -8 instead of -2.

5-99

OmtfiOlL

HA2500/2502/2505
ABSOLUTE MAXIMUM RATINaS
, Supply Voltage . . . . . ' .. :
. • . • . .
Input Voltage (Note'l) ',' , • . . .
Differential Input Voltage . . . . .
Peak Output Current . . . . • . . • . . • . .
Internal Power Dissipation (Note 2) . . • . .
Lead Temperature (Soldering, 60 sec)
Storage Temperature Range
. .
Operating Temperature Range . • . • • . . • .

ELECTRICAL CHARACTERISTICS

. • . .
. .. , . . . .
±20V
· . • . . . . . . . . . . . . . • . . . • . • .
±ISV
· . • . • . • . . . . . . . . . •. . . • . • .
±ISV
. . • . • • . • . . . . . . . . . . . . . . • . ±SOmA
· . . . . . • . . . . . • . . . • • . . • . • • . . . . 300mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
• • • . • . • .. .. • . . . . . . . . . . . -6SoC to +IS0oC
. . . . • . • . .
. .. -SSoC to +12SoC (2S00, 2502)
OoC to + 7SoC (2S05)

(TA = 25°C, Vs = ±15V unless otherwise specified)

2500
PARAMETER

CONDITIONS

,Input Offset Voltage

MIN

TYP

Large Signal Voltage Gain

RL= 2kRVO=±10V
AV>lO

Full Power Bandwidth

RL = 2kn. CL = 50pF, VO= 20Vp·p

Overshoot INotes 3A)

RL='2kn, CL = 50pF

Slew Rate INote 3)

RL = 2kn. Ct. =50pF, VO= ±5V

Settling Time Ito 0.1%

RL = 2kn. CI-= 50pF. VO= ±5V

TYP'

MIN

MAX

8

4

8

2S

20

50

20

50

25

10
. SO

20k

30k

350

,

, RL = 2kn. CL = 50pF

2505
MAX

4
20

50

20

15k

25k.

15k

'12

Rise Time INotes 3A)

TYP

5

Input Offset Current

Gain Bandwidth

MIN

, 2

RS ";;;10 kn

Input Resistance

2502
MAX

±25

12

500'

300

500

300

V/V

12

MHz
kHz

500

50

25

50

25

50

25

40

25

50

25

50

±20

330

±30

±20

330

nA

25k

25
±30

mV
Mn

50

,

UNITS

ns
%

±30

VIIJS

330

ns

of Final Value) INote 3)
±10

VO= ±10V

Output Current

Supply Current

±10
4

±10
4

6

mA

6

4

6

mA

THE FOLLOWING SPECIFICATIONS APPLY FOR' OPERATING TEMPERATURE RANGE'
Input Offset Voltage

,

I nput Offset Current

I nput Bias Current

Offset Voltage Average Drift

RS";;;lO kn

NOTE,1:
NOTE 2:
NOTE 3:
NOTE 4:

mV
nA

200

125

250

_55°,C to +25O C

200

400

250

500

nA
nA

+25°Cto +75°C

125

250

nA

OoC to +25°C

250

500

nA

RS";;;lO kn
80

VCM = ±5V·

20

20

0.1

0.1

90

±10

Supply Voltage Rejection Ratio t;.V = ±5V
Output Voltage Swing

10
100

100

Common Mode Range

, Large Signal Voltage Gain

10
100

+25°C to +125°C

Offset Current Average Drift
Common Mode Hejection Ratio'

8
50

80

RL = 2kn. VD= ±10V

7.Sk

RL= 2kn

±10

74

90

74

±12

±10

74

20

p.vfc

0.1

nAfC

90

dB

90

dB

±12

'V

±10'

±10
90

.

90

74

±12

±10

V

10k

Sk

V/V

For supply voltages less than ±1SV, the absolute maximum input voltage is equal to the supply voltage.
Derate TO~86 at 4.S mW/oC above 84°C; derate TO-99 at 6.6 mW/oC above 10SoC.
AV = 1.
Va = 400 mV p •p .

TRANSIENT
RESPONSE
IO

Full Power Bandwidth

RL = 2kn. CL = 50pF. VO= 20Vp-p

Rise Time (Notes 3,4)

RL= 2kn, CL= 50pF

25

50

25

50

25

50

Overshoot (Notes 3,41

RL = 2kn. CL= 50pF

25

40

25

' 50

25

50

Slew Rate (Note 3)

RL= 2kn. CL = 50pF. VO= ±5V

Settling Time (to 0.1%

RL= 2kn, CL= 50pF. VO~ ±5V

12
750

12

1000

±50

600

±40

±e5

1000

600

±40

±eo
250

250

1000

kHz
ns
%

±eo

V/J1S

250

ns

of Final Value) (Note 3)

Output Current

±10

Vo = ±101i

Supply Current

±10

±10
4

4

6

mA
4

6

6

THE FOLLOWING SPECIFICATIONS APPLY FOR OPERATING TEMPERATURE RANGE
Input Offset Voltage

RS";;10kn

I nput Offset Current
I nput Bias Current

Offset Voltage Average Drift

mV
nA

200

125

250

-55°C to +25°C

200

400

250

500

nA
nA

+25°C to +75°C

125

250

oOe

250

500

to +25°C
20

RS";;10kn

30

0.1
80

90

±10

Common Mode Range

Supply ,Voltage Rejection Ratio Av = ±5V

80

Large Signal Voltage Gain

RL=2kn. Vo = ±10V

7.5k

Output Voltage Swing

RL = 2kn

±10

0:1
74

90

74

±12

±10

nA

30

Ilvte

0.1

nAte

90

dB

90

dB

±10

±10
90

74

nA

90

74

±12

±10

V

5k

5k

VIV
±12

For supply voltages less than ± 15V. the absolute maximum input vol(age is equal to the supply voltage.
De.rate T0-86 at 4.5 mW/oe above 84 0 e; derate T0-99 at 6.6 mW/oe above 10Soe.
AV = 1.
Vo = 400 mVp=p.

TRANSIENT
RESPONSE
10

Full Power Bandwidth

RL = 2 k!G, CL= 50pF,VO = 20Vp·p

Rise Time (Notes 3.4)

RL= 2k!G, CL= 50pF

Overshoot (Notes 3.4) ,

R L= 2 k!G, CL= 50pF

Slew Rate (Note 3)

R L= 2 k!G, CL= 50pF, VO= ±5V

Settling Time (to 0.1%

R L= 2k!G, CL= 50pF, VO= ±5V -

2522
MAX

MIN

TYP

MAX. UNITS

5

10

5

10

10

25

20

50

20

50

10k

15k

40
7.5k

30

±100

MIN

8

100

100
15k

,

15

50

25

40

1200
,
;±gO

±120
200

1600

nA

100

7.5k

15k

V/V

30

MHz

1200

M!G

1600

kHz

15

50

15

50

25

50

25

50

;±gO

±120

mV

40

30

2000

,

2525
MAX

4

50

1500

TYP

200

ns

%

±120

VIps

200

ns

of Final Value) (Note 3)

Output Current

±10

VO= ±10V

Supply Current

±10
4

±10
4

6

mA
4

6

6

mA

THE FOLLOWING SPECIFICATIONS APPLY FOR OPERATING TEMPERATURE RANGE
Input Offset Voltage

RS';;;lO k!G

Input Offset Current

Input Bias Current

Offset Voltage Average Drift

14

mV

100

nA

100

200

125

250

nA

_55°C to +25°C

200

400

250

500

nA

+25°C to +75°C

125

250

nA

OoC to +25°C

250

500

"nA

RS ';;;10 k!G

80

Common Mode Rejection Aati'o VCM = ±5V

20

30

30

flVtC

0.1

0.1

0.1

nAtC

90

dB

90

dB

90

±10

Common Mode Range

Supply Voltage Rejection Ratio t;.V = ±5V

80

Large Signal Voltage Gain

RL = 2 k!G, VO= ±lOV

7.5k

Output Voltage Swing

RL = 2 k!G

±10

1:
2:
3:
4:

14
100

+25°C to +125°C

Offset Current Average Drift

NOTE
NOTE
NOTE
NOTE

11
50

74

90

±10
90

74

±12

±10

±io
90

74

±12

±10

5k

200~V
INPUT

J

L

OV

,.

INPUT

J

,90%-----,----

1

10%-- , . :

-!

9~0%---,-----

OUTPUT:

.

[RISE TIME

L

-1.S7V

'600mv~,'
--~- - - , - - OUTPUT,

SLEW RATE
AND
TRANSIENT RESPONSE

SLEW RATE
67V

-5V

:

r---r- -- --- --:

~V

____L ___t_________ ".,

10%--~

~! SL~~/:~TE

I,

1:

'

I

NOTE: Measured on both positive and negative transitions.

5-102

V

5k

For supply voltage less than ± 15V, the absolute maximum input 'Voltage Is equal to the supply voltage.
Derate T0,.86 at 4.5 mW/oC above 84°C; derate TO-99 at 6.6 mW/oC above 1 05°0~
AV = 3.
Va =600 mV p _p .

TRANSIENT
RESPONSE

74

V/V
±12

V

SUGGESTED OFFSET
ZERO ADJUST
AND BANDWIDTH
CONTROL HOOK-UP

HA2500102/05/10/12/15/20/22/25
SCHEMATIC. DIAGRAM,

OFFSET

R5
t.2K

Qt

Q2

Q3

Rt
4K

R6
200

R9
200

R7
t.BK

RtO
t.BK

RB
t.2K

v+
Rtt
2K

BW

CONTROL
INPUT+
R26

INPUT-

v-

OFFSET

5·103

HA2507/2517/2527
High Slew Rate
Operational Amplifier Series
DESCRIPTION

FEATURES
HA2507 HA2517 HA2527
• High Slew Rate

30

60

120

V/p.s

• Fast Settling

330

250

200

ns

• Wide Power
Bandwidth

0.5

1.0

1.6

MHz

• High Gain
Bandwidth

12

12

20

MHz

• High Input
Impedance

50

100

100

Mfl

HA2507/2517/2527.operational amplifiers are a series of
high-performance, epoxy-packaged monolithic IC's designed to deliver excellent slew rate, bandwidth and
settling time specifications. Typical slew rate specifications for HA2507, HA2517 and HA2527 are 30V/1L sec,
60V/1L sec and 120V/lLsec respectively. Corresponding
settling times (:lOV step to 0.1 %) are 330ns, 250ns and
200ns for HA2507, HA2517 and HA2527 respectively.·
Bandwidths ra[lge from 12MHz to 20MHz .. HA2507/
2517/2527 are internally compensated; HA2507 and
HA2517 are stable for closed loop gains (Av) greater than
or equal to unity. HA2527 is stable for Av >3.
This series of op amps affords an economical means of
designing high performance equipment for ind.ustrial and
commercial use. Their slew rate and settling time performance makes them ideally suited for high speed 0/ A,
A/D and pulse amplificatioll designs. The wide bandwidth
offered by these devices also makes them valuable components in RF and video applications. HA2507/2517/2527
also deliver offset current, bias current and offset voltage
specifications compatible with the requirements of accurate signal conditioning systems.

ORDERING INFORMATION

HA3-2507-5
HA3-2517-5
HA3-2527-5

8 pin minidip
/

SCHEMATIC

~

01

R6
200

RS 1.2K

R'
200 RS 1.2K

OFFSET

V+

R7
02

Rl
.K

r--~,.. 03

';j~04

r-

R2
2K

~

C

CONTROL

k::

03B
029

BANDWIDTH

CONTROL

o~

v+

033

OUT

v-

OFFSET ADJ,

(o~t1ine dwg PAl

~

032

030

~

R25

R26

J02:
}

"'" .L<027

F;;31

R23
3K

':039
::t-

c-

~~

016
R13
30

~014

OUTPUT

~

015

Rl'
30
0;-;-

01B~

r-t::

Rl.
6.3K

019

025

Y026

R2~

Cl'

",,030

a~ 022

02.
021

3K

R1B
1.48

R17
1.48

Rl.
1.48

::!
R15
740

R22

INPUT- o
OFFSET

'VALUES OF Cl. C2. R25 AND R26 VARY DEPENDING ON DEVICE TYPE.

5-104

R12 1.1K

~

C2'

F-

~36

011

010

Q4~

""
k035

+IN

t--

037

INPUT+

-IN

OB

R4
11.13K

OFFSET ADJ,

07

960

R11
2K

1.BK

"'.

B.W.

PIN CONFIGURATION

RIO

1.8K

v-

D~DIL

HA2507/ 2517/2527
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals ......... 40.0V
Differential Input Voltage .................... ±15.0V
Peak Output Current .. . . . . . . . . . . . . . . . . . . . . . .. 50mA
Internal Power Dissipation.. . . . . . . . . . . . . . . . .. 300mW
Operating Temperature Range. HA-2507/HA-2517/HA-2527 ..... DOC:;:; TA :;:;+75°C
Storage Temperature Range .. - 65° ,;; T A :;:; + 15Doc

NOTE:

Stresse~ above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
, stress ratings only and fundional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

ELECTRICAL CHARACTERISTICS V+=+15V D.C., V-=-15V D.C.
HA·2507
O°C to + 75°C
LIMITS
PARAMETER

TEMP.

MIN.

HA-2527
O°Cto +75°C

HA-2517
O°Cto +75°C
LIMITS

TYP.

MAX.

5

MIN.

LIMITS

TYP.

MAX.

MIN.

TYP.

10
14

5

10
14

5

MAX. UNITS

INPUT CHARACTERISTICS
Offset Voltage

,

+25°C
Full

Offset Voltage Average Drift

mV
mV
/LV/oC

Full

25

Bias Current

+25°C
Full

125

250
500

125

250
500

125

250
500

nA
nA

Offset Current

+25°C
Full

20

50
100

20

50
100

20

50
100

nA
nA

Input Resistance

. +25°C

Common Mode Range

20

30

10
14

40

50

30

100

40

100

Mil

Full

±10.0

+25°C
Full

15K
10K

25K

7.5K
5K

15K

7.5K
5K

15K

Full

74

90

74

90

74

90

dB

20

MHz

±10.0

±10.0

V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 1, 4)
Common Mode Rejection Ratio (Note 2)
Gain Bandwidth Product (Note 3)

+25°C

12

12

V/V
V/V

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 1)

Full

±10.0 ±12.0 .

±10.0 ±12.0

±10.0 ±12.0

V

Output Current (Note 4)

+25°C

±10

±20

±10

±20

±10

±20

mA

Full Power Bandwidth (Note 4)

+25°C

220

500

450

1000

750

1600

kHz

TRANSIENT RESPONSE
Rise Times (Notes 1,5,6 & 8)

+25°C

25

50

25

50

25

50

Overshoot (Notes 1, 5, 7 & 8)

+25°C

25

50

25

50

25

50

Slew Rate (Notes 1, 4, 5 & 8)

+25°C

Settling Time to 0.1 % (Notes 1, 4, 5 & 8)

+25°C

±15

±30

±30

0.33

±60

±60

0.25

ns
%

±120

V//LS

0.20

/LS

POWER SUPPLY CHARACTERISTICS
;

Supply Current
Power Supply Rejection Ratio (Note 9)

+25°C
Full

4
74

90

Notes:
1. RL = 2K
2. VCM = + 5.0V
3. Av> 10
4. Vo = + 10.0V
5. CL = 50pF
6. Vo = + 400mV for HA-25(}7 and HA-2517; Vo = + 200mV for HA-2527
7. Vo =+ 600mV
'
8. For HA-2507 and HA-2517, Av = l; For HA-2527, Av = 3
9. 6. V ='+ 5.0V

5-105

6

4
74

90

6

4
74

90

6

mA
dB

.HA2600, HA2605, HA2622,.
HA2602,HA2620,HA2625.
High Impedance Operational Amplifiers
FEATURES

GE,:NERAL DESCRIPTION

•
•
•
•
•
•
•

The 2600 series of high impedance operatioriai amplifiers
are monolithic integrated circuits f~bricated using dielectric
isolation. These internally compensated amplifiers feature
excellent input parameters, low input bias and wide bandwidth. They are ideally suited for general purpose 'use in
instrumentation and signal processing applications.

Input Impedance - 500Mn
Offset Current - 1 nA
Bias Current - 1nA
Gain Bandwidth Product - 100MHz
High Gain - 150K
Output Short Circuit Protection
Meets MI L-STD-883

2600 through 2605 are compensated for unity gain. 2620
through 2625 are intended for closed loop gains of 5 or·
greater and feature increased slew rated and gain-bandwidth
products.

PIN. CONFIGURATIONS, TOP VIEWS
(outline dwg TO-99)

(outline dwg FB)

(outline dwg JD)

BANDWIDTH CONTROL

NC

NC

BANDWIDTH

OFFSET ADJUST

v'
IN'

OUTPUT

v-

OFFSET ADJt..;ST

Pin 4 Connected to case

ORDERING INFORMATION

PART
NUMBER

TEMPERATURE
RANGE

HA2600

-55°C to +125°C

HA2602

-55°C to +125°C

HA2605

O°C to +75°C

I

HA2620

-55°C to +125°C .

HA2622

-55°C to +125°C

HA2625 '-

OOC to +75 OC

PACKAGE
TYPE

ORDER
NUMBER

TO-99
. TO-91 'Flat Pack
1.4 Pin CerDIP
TO-99
TO-91 .Flat PacK
14 Pin CerDIP
TO-99
TO-91 Flat Pack
14 Pin CerDIP
TO-99
TO-91 Flat Pack
14 Pin CerDIP
TO-99
TO-91 Flat Pack
14 Pin CerDIP
TO-99
TO-91 Flat Pack
14 Pin CerDIP

HA2-2600-2 *
HA9-2600-2 *
HAl-2600-2 *
HA2-2602-2 *
HA9-2602-2 *
HA 1-2602-2 *
HA2-2605-5 .
HA9-2605-5
HAl-2605-5
HA2-2620-2 *
HA9-2620-2 *
, HA 1-2620-2 *
HA2-2622-2 *
HA9-2622-2 *
HA 1-2622-2 *
HA2-2625-5
HA9-2625-5
HAl-2625-5

*8838 processing is available for these devices_ Order -8 instead of -2_
5-106

HA2600,.HA2605, HA2622, HA2602, HA2620, HA2625
ABSOLUTE MAXIMUM RATINGS

Supply Voltage
Input Voltage (Note 1)
Differential lriput Voltage
Peak Output Current
Internal Power Dissipation (.Note 2)
Lead Temperature (Soldering,
60
sec.)
.
.
Storage Temperature Range
Operating Temperature Range

±22.5V
±15V
±12V
Full Short Circuit Protection
300inW
+300 oC
'-65°C to +150 o C
-5SoC to +125°C (2600, 2602)
.0oC to + 75°C (2605)

EI.,ECTRICAL CHARACTERISTICS (TA =,25°C, Vs = ± 15V, unless otherwise specified)
PARAMETER

2600

CONDITIONS

Input Offset Voltage

MIN

TYP

RS " 10k!!

I

Input Resistance
Large Signal Voltage Gain

RL = 2k!!. Vo = QOV

Unity Gain Banc!width

Va < 90mV

Full Power Bandwidth

RL = 2k!!. CL = 50pF. Vo = 20Vp . p

Rise Time (Note 3)

RL = 2k!!, CL = 100pF

Overshoot (Note 4)

RL = 2k!!, CL = 100pF

Slew Rate

RL = 2k!!, CL = 100pF, Vo = '5V

Setting Time

RL=2k!!,CL= 100pF.VO= '5V.

TYP

2605
MAX

MIN

TYP

MAX

UNITS

4

3

5

3

5

1

10

5

25

5

25

nA

10

5

25

5

25

nA

1
500 .

100

-

MIN

0.5

Input Offset Current
Input Bias Current

2602
MAX

lOOK

150K

50

75

40

300

40

300

Mn

SOK

150K

SOK

150K

V/V

12

MHz

50

75

50

75

12

'.
4

12

KHz

30

60

30

60

30

60

25

40

25

'50

25

50

7

mV

4

1.5

4

7
1.5

ns
%

7

V/~s

1.5

ns

(to • ~OmV of Fin.a! Value)
Output Current

Vo =

,10\1

,15

,22

Supply Current

3

,10
3.7

,18
3

±10

±lS
3

4

rnA
4

mA

THE FOLLOWING SPECIFICATIONS APPLY FOR OPERATING TEMPERATURE RANGE
Input Offset yo~tage

RS" 10k!!

Input Offset Current
,

I "put" Bias Current

Offset Voltage Average Drift

RS" 10k!!

Common Mode Rejection Ratio

VCM = '5V

2

6

7

7

mV

5

30

60

40

nA

10

30

60

.40

80

I

100

,11

Common Mode .Range

Supply Voltage Rejection Ratio

Vs

,~V

Large Signal Voltage Gain

RL = 2k!!, Vo = .,OV

70k

Output Voltage Swing

RL = 2kl!

'10

To' 15V

74

100

74

,11

80

90

74

±10

100

dB

90

dB

V

'11
74

90

70k

60k
"2

,10

.12

V/V
.12

NOTE 1: .For supply
is equal to the supply voltage.
. . voltages less than ±15V, the absolute maximum input voltage
. ),
NOTE 2: Derate TO'91 at 4.5 mWf'C ·above 84°C; derate TO'99 at 6.6 mW/oC above 105°C.
NOTIj:3: Vo = 400 mV p_p
NOTE 4: Vo = 800 mV p_p
,

TRANSIENT
RESPONSE

INPUT

.

J

SLEW RATE AND
SETTLING TIME.

L

~~.£YER~.£~~
_____ _

90'.==-I
- '
OUTPUT

10'.

---I

L

----.

OUT

100pF

I
I
j.....: RISE TIME

I I

NOTE:

SUGGESTED
OFFSET
ZERO ADJUST
HOOK-UP

SLEW RATE AND
TRANSIENT
RESPONSE

\

MEASUREO ON BOTH POSITIVE AND NEGATIVE TRANSITIONS.

5-107

nA
~V/'C

5

.y

V

HA2600,HA2605,HA2622,HA2602,HA2620,HA2625
ABSOLUTE MAXIMUM RATINGS

Supply Voltage
, Input Voltage. (Note 1)
, Differential Input Voltage
Peak Output Current
-Internal Power Dissipation (Note 2)
Lead Temperature (Soldering, 60 sec.)
Storage Temperature Range
Operating Temperature Range

±22.5V
±15V
±12V
Full Short Circuit Protection
300mW
300°C
-65°C to +150 o C
-55°C to +125°C (2620, 2622)
OOC to +75°C (2625)

ELECTRICAL CHARACTERISTICS (TA = 25°C, Vs =± 15V, unless otherwise specified)
PARAMETER

2620

CONDITIONS

Input Offset Voltage (Note 3)

MIN

RS .;; 10k!!

Input Offset Current

I

Input Bias Current

-

Input Resistance

=±10V, CL =50pF
RL = 2k!!, CL = 50pF
RL = 2kSl, CL = 50pF,Va =20V p • p
RL = 2kn, CL = 50pF
RL = 2kn, CL = 50pF, Va = '5,OV
Va = ±1OV
RL~

Large Signal Voltage Gain
Gain Bandwidth fNotes4 and 5)

Full Power Bandwjdth
Rise Time (Note 6)

Slew 'Rate (Nota 6)

Output Current

2k!!, Va

4

3

5

15

5

25

15

5

25

I

. Large Signal Voltage Gain
Output Voltage Swing'

= ±9V To J15V
RL = 2kn, Va = ±10V,-CL = 50pF
RL = 2k!l, CL = 50pF '

i

3

5

5

25

nA

5

25

nA

I

MAX

mV

40

300

40

300

MSl

SOK

150K

80K

150K

VIII

100

MHz

400

600

320

600

320

600

i25

,35

±15

±22

80
80

VSupply

TVI'

500

100

±20

±35

'10

±18

45

3

3,7

6
5

35

-10

35

60

100

3

74

100

74

90

90

60k
±10

±12

17
±20

±35

±10

±18

4

3

KHz

ns

45

VI~s

mA
4

mA

7

7

mV

60

40

~A

40

nA

74

100

d8

90

dB

±11

±11

70k
±10

17

45"

±11

Supply Voltage Rejection Ratio

UNITS

I

150K

17

=±5V

MIN

65

Input Bias Current
VCM

2625
MAX

1

100

'Common Mode Range

TVP

,lOOK

,

Common Mode Rejection Ratio

MIN

0,5

RS';; 10kSl

Input Offset Current

NOTE
NOTE
NOTE
NOTE
NOTE
NOTE'

MAX

1

Supply Current

Input Offset Voltage

2622

TVP

V

74
70k

t12

V/V

±10

±12

V

1: For supply voltages less than ±15V, the absolute maximum input· voltage is equal to the supply voltage,
2: Derate TO-91 at 4.5 mWf.C above 84°C; de'rate TO-99at 6.6 mWfC above 105°C,
3.: May be externally adjusted to zero.
4: Vo < 90mV_
5: 40d8 gain.
6: AV '= '5.0V,

TRANSIENT
RESPONSE

'SLEW RATE AND
TRANSIENT RESPONSE

SLEW RATE

SUGGESTED OFFSET
-ZE;RO ADJUST AND
BANDWIDTH
CONTRQL HOOK-UP
+v

100mv~/
'.
'.

INPUT

,ov

.

INPUT'

.

-w _ ,

500mv~--'.
-

90"'('
---'-OUTPUT
:.
10""
__
I,

I
•

NOTE:

.

IN

+5V~_____
_ __

90%----OUTPUT

~RISE TIME

I

1V~
.

..

-5V

-

-

5011

I.lV

OUT

.:._-1-_1._

10% _ _

I

1 SLEW RATE

: ~.lT..,

,I

•

BANDWIDTH

.lv/.n

lCONTROL

MEASURED O,N BOTH POSITIVE AND NEGATIVE TRANSITIONS •

. 5-108

U~Ull

HA2607/2627
Wide Band Operational
Amplifier Series

FEATURES
• Wide gain-bandwidth

DESCRIPTION
HA-2607 HA-2627
12
100
MHz
7

35

V/J.ls

75

600

KHz

• High slew rate
• Wide power bandwidth
• High.gain

150KV/V

• High input impedance

500Mn

HA-2607/2627 bipolar operational amplifiers are high performance, epoxy-packaged monolithic IC's designed to
deliver outstanding wideband AC performance. HA-2607
has a specified bandwidth of 12MHz while HA-2627 has
a typical gain-bandwidth of 100MHz!* HA-2607 and
HA-2627 also offer correspondingly high slew rates of
7V/p, Sec and 35V/p, Sec respectively. These dynamic
characteristics, coupled with 150,OOOV/V open-loop gain
enables HA-2607/2627 to perform high-gain amplification
of very fast, wideband signals.
'
The HA-2607 and HA-2627 op amps afford an economical means of designing high performance equipment for
industrial and commercial use. These amplifiers are
. ideally suited to pulse amplification designs as well as
high frequency (e.g. RF, video) applications. The frequency response of both amplifiers can be tailored to
exact.design requirements by means of an external bandwidth control capacitor.
* HA-2607 /2627 are internally compensated-HA-2607 is ~
stable for Av;;' 1,-HA-2627 is stable for Av;;' 5.
•

• Output short circuit
protection '
ORDERING INFORMATION

8 pin minidip
8 pin mini dip

HA3-2607·5
HA3-2627-5

PIN CONFIGURATI()N
OFFSET ADJ.

SCHEMATIC
BANDWIDTH
CONTROL

OF FS-=.T

BANDWIDTH
CONTROL

4.1~~~

Rl
lK

v+

+IN

OUT

~

a3

v-

a4

OFFSET ADJ,

afi=

R4

1.56K

1.S6K

'C3

L,

al

-IN

R3

16pF

~,

IN PUT+

(o!o

as

o.

028

01' ...~
R7
13'
'---

O~

I

a41
~42

032

a60

i~"

a59

1

0-

a3l

rr

rK°

al.~"

 TA > +25°C
+25°C> TA > +85°C
+25°C > TA > +125°C
Low Bias
Band Width
0.1 to 10Hz
Med Bias
Rs';; lk!!
High Bias
Low Bias
Band Width
0.1 to 10Hz
Med Bias
Rs < lk!!
.High Bias
f -10Hz
Band Width 1Hz

VOS/Time

enp-p
en10

f -10Hz
,

in 10

0.2
0.005
0.01
0.05

Band Width 1Hz

DIF VIN
Low Bias
Med Bias
High Bias
Any Bias Setting
Any Bias Setting
Any Bias Setting,
(Includes charge injection currents)
Any Bias Setting,
(Includes charge injection currents)

CMRR
PSRR

to

-4.2
-4.0
-3.5

Maximum Output Voltage
Swing

VauT

Rl-1M!!
Rl = lOOk!!

±4.8

SR

Unity Gain Band Width

GBW

Unity
Gain
ICL7600
ICL7600
Test Circuit 2

V
V/p,s
V/p,s
V/p,s
MHz
MHz
MHz
MHz
MHz
MHz
pA
V

V'-l.4
V-+0.3

V
V
pA

V'+0.3

V

V'-l.4

V
Hz
Hz
rnA
rnA
rnA
V
V

Med Bias Setting
High Bias Setting
V' -8.0V';; VOR';; V'+0.3V

V-+l.4
V--o.3

VORH·

Internal oscillator division ratio 32

V'-o.3

VORL
!cOM

Internal oscillator division ratio 2
DR Connected to V'
DR Connected to GND
High Bias Setting
Medium Bias Setting
Low Bias Setting
High Bias Setting
Medium or Low Bias Setting

±30

V'-8
160
2560
7
1.7
0.6

Case - 0 pF

5-123

y

GND
V-

VSM
VSl
lOR

V'-V·

dB
dB
dB
V
V
V
V

V'+0.3

V--0.3 ,;; VSIAS';; V' +0.3 volt
Low Bias Setting

Operating Supply Voltage
Range

+4.2
+4.0
+3.5

V'-o.3

ISlAS
VSH

,

V

1.8
0.5
0.2
1.2
0.3
0.12
1.8
0.4
0.2
±30V+

BIAS Terminal Input Current
BIAS Voltage to Define
Current Modes

Is

V'+0.3

-4.5

GBW

DR (Division Ratio)
Input Current
DR Voltage to define
oscillator division
ratio
Nominal Commutation
Frequency
Supply Current

pAly'Hz

+4.4

Extrapolated Unity
Gain Band Width

ICL7601

0.1

nA

105
105
100
±4.9

Large Signal Slew Rate

700

p,V
p,V
p,V
nV/vHz

1.5

Rl - lOOk!!

90
90
80

p.V
p.V
p,V

0.150

Av

Positive Swing
Negative Swing
High Bias Setting
Med Bias Setting
Low Bias Setting
High Bias Setting
Med Bias Setting
Low Bias Setting
High Bias Setting
Med Bias Setting
Low Bias Setting

p.V/year
p.V/oC
p.V/oC
p.V/oC

3

Voltage Gain

Rl = lOkI!

0.1
0.1
0.15

±5

88
110
0.300

INIS

Low Bias
Med Bias
High Bias

±20

UNIT
p.V
p.V
p.V
p.V

V
V
V
dB
dB
nA

Common Mode Rejection Ratio
Power Supply Rejection Ratio
Non Inverting Input
Bias Current
Inverting Input Bias
Current

he

MAX

0.8
0.8
1.0
4.0
4.0
5.0

V--o.3

CMVR

VALUE
TYP
±2
±2
±7

5
4

15
5
1.5
16
16

ICL7600/ICL7601

U~UR.

TEST CIRCUITS
oy+

11~14l_-...:...--o-..:o y+ .

t-----,.o--

oGND

oGND
Y,N-.....- - - - - i

Your

lk

*
-=

o'Y+

Y_

OOY_

-----y+---------:i: Coso

YINo-.....- - - - - I

-----v+--------~ Coso

lk

-=

Your

oy+

Y-

'o~

lMll

T.est Circuit 1: Voltage Gain = 1000

. Test Circuit 2:.Unity Voltage Gain

ov+

y+

r;-'14l--~
N/C
Y,No-.....- - - - - i

oGND

-----v+---------~

. 10k

VOUT

ov+

"!:'

Y-

OOy_

0}

,------;<>,OY-

150k
INPUT o--'\IV\,....-'VV'II.....'V'oI'lr..---t

Coso

NULL
. OFFSET
Your

laOk

20k

Test Circuit 3: Voltage Gain = 10

m
•

Test Circuit 4: DC to 10Hz Unity Gain Low Pass Filter

TYPICAL CHARACTERISTics
INPUT OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
COMMUTATION FREQUENCY
(Cl. C2 =1/,F)

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGES .

INPUT OFFSET VOLTAGE AS A
FUN~TION OF AMBIENT TEMPERATURE

y-. NEGATIYE POWER SUPPLY YOLTAGE·-Y
-7.5

..

>

+10

~ +8

"~+6

TEJ~ CI~CUITll
C, =C2 = l~F
100M = 160 Hz

w
~

g

I-

t:;+4

I
/

~

~ +2

~O
~

:-4.0
-3.0

. OFFSET YOLTAGE

-- ,..-- --

:>

i

-i'\,]

-

o

:>

o

10
100M'

~
,
\\,

~6ISE ~

I~OLV·GIE

17.5

+-14-+±1::---I15.0 ~

g

/

1

-I-'

t--HI-t1Fr;/;-;;+';;~;---;f--+lttF-l12.5

l!l

10.0

Ii!

/

___ 5

z
a;

LOW
BIAS

t:::: ' /
l~~a

-7

z

~-4

~II.
i

It -3

~.

I-

~-2

ii!i
~-1

o

./MED BIAS 2.5 ::
.,;

100
10k
lk
COMMUTATION FREQUENCY .. Hz

.,. "

o

5.~ ~

:>

o

c
;;;

2

5-124

3~~
w

Tl

"o~-5

10.0~

Iv.: t:,.-i;&jI

100
lk
10k
COMMUTATION FREQUENCY· Hz

= 251c
. Av = 1000
Rs $lkO
C,. C2 = 1.0~F
IY+I =.IV-I
100M = 160 Hz

~-6
w

12.5[5

7.5

~OOM'

>

W·

HIGH BIAS

"~~-L~~~~~~~O

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE AS A
FUNCTION OF SUPPLY VO,LTAGE
(V+cV-)

.>

I~Ar-

!;
<

+2.5 . +3.5
+4.5
+5.5
+6.5
+7.5
y+. POSITIYE POWER SUPPLY YOLTAGE· Y

20.0 ~
HIGH
w
. TlfS- 17.5~
~
MED
15.0g

.

-20 . ."rnr-,=""--==:--r-,,rrrr-, 20.0 ~

2

N~lt~ YO.,.o:GE
-:---

o

TA - 25"C
Av=1000
Rs $lkll
I', C,. C2 = ~¥
11+=+5
, \ V-=-5Yj

OFFSET \
VOLTAft;;

~

~

Z

';' -1.0

INPUT 'OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
COP/IMUTATION FREQUENCY
.
(C. C2 = O.1/'F)
f--

~

-2.5

1

II.

-4
-50 -25
0
'25
50
75 100 125
- TA • AMBIENT TEMPERATURE· ·C

,

-35

.1-

~

-20

-45

m
0-2.0

./

'" -2

-5.5

TA =25·C
Av = 1000
Rs $lkO
.C,. C2 = 1.0~F
IY+ ~ Y-I = 10 VOLTS
100M = 160 Hz

!j

g

-11.5

"
.. - ---

30"

~

25g

J
)1 20 6z
w

15~

i

...

10~

5

4
6
8
ro n M
IY+'Y-I • SUPPLY YOLTAGE • Y ,

o
I-

d

.
I NOISE YOLTAGE
16°

.~

ICL7600/ICL7601
INPUT CURRENT AS A FUNCTION
OF COMMUTATION FREQUENCY

'il. -500
Ou>

~ffi-400

II

>=0:-350
0:0:
~I-

5~-250
~ ;:;-200

\ /

i~-150

~

II

-50

1

>+4

I
I
I

"z
00:

1-0

~6 0
5~-1

/
II

~~ -2
6~
>w -3

1/

0:

E

............

..........

a>

v+·v- = 10 VOLTS
NO LOAD
NO INPUT

0:

4

zw

::l

0.
0.
::l

-- -

u>

MED BIAS

o

-50

""-

LO BIAS

lk

...0:

\.
.......

-

lose - 5.2 kHz I
Fo, Cose - 0 pF

o

~

::! 100

--

W

+30

"~

+10

w

.0

AZ

>

-=--=-

w

......~ -t-3.0

Z-10

5 +1.0
0.

"- +0.3100

\

\

~
~ -20

\

c

::l

I-

~-30

1
10
100
1000
Cose • OSCILLATOR CAPACITANCE· pF

\
2

3 45
10
20304050
I - FREQUENCY - Hz

TOTAL E,QUIVALENT INPUT OFFSET
VOLTAGE AS A FUNCTION OF
SOURCE IMPEDANCE - -INPUT

/
-

0: ·100
0:
0:
~ -30

o

~

I

...J

o

H+t-+-+

-10

>

I-

m-3.0 hl+t++-t+-t+-t--H+i--1--1+++-t
...o...

V

o

II
r-T~=125ld

~---40

1/

I-

0

::;;


TOTAL EQUIVALENT INPUT OFFSET
VOLTAGE AS A FUNCTION OF
SOURCE IMPEDANCE - +INPUT

"-

.c

" ,

/
MED BIAS

FREQUENCY RESPONSE OF THE 10 Hz LOW
PASS FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 4).

."

u>

-25
0
25
50
75
100 125
TA' AMBIENT TEMPERATURE 'C

~+100

o

lOOk

u

-

U 4

• 2
!!!

lk
10k
RL • LOAD RESISTANCE

0:

...J

::l

~

~

ow

-

TA = 25°C
NO LOAD- r NO INPUT

0:

u>

TA = 25'C
5 < IV+-V I < 10 VOLTS=

u

..........

Z
W
0:

IZ

V

......HI BIAS

w
a:

TA = 25'C
I-IV+,V-I = 10V
RL CONNECTED TO GND_

10k

>

I-

,,'

E

::l

-5
100

:t

HIBLAS

" +1 /'

10
100
1000
leOM' COMMUTATION FREQUENCY· Hz

f.--

~

W~+3

:-- 4sINJ~TING
INPUT CURRENT

I--"

o

I

/

/

.0:

.§?~-100

I

I

INiB NON INVERTING
INPUT CURRENT

~G-300

+5

~

TA = 25'C
IV+'rll= :01VOLTIS

0: • -450

MAXIMUM OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT LOAD RESISTANCE

5 -1.0 HfH++*t+-1I'-+1-j-j-j'-l#f-'-l

0.

/

Z
- -0.3· LJ..LJ...L..L.J..LJ.lL.L..lU..L..L.ll.L..L....J

lk
lOOk
10k
1M
RSl INPUT SERIES RESISTANCE· n

100

5-125

lk
10k
lOOk
1M
RS2 INPUT SERIES RESISTANCE· n

100

O~OIL

ICL7600/ICL7601
DETAILED DESCRIPTION
CAZ Operational Amplifier Operation
The CAZ operational amplifier functions on principles which
are very different from those encountered in conventional op
amp types. An important advantage of the lCL7600/lCL7601
devices is the ability to self-compensate for internal error
voltages, whether. they are steady-state, related to temperature or supply voltage, or variable in nature over a long
term.
Operation of the ICL7!l00/1CL7601 CAZ operational
amplifier is demonstrated in Figur-e 1. The basic amplifier
configuration represented by the large triangles has one. more
input than does a regular op amp--the AZ, or auto-zero input.
The voltage at theAZ input is that to which ear;;h of the
internal op amps will be auto-zeroed. In Mode A, op amp #2 is
connected into a unity gain mode through on-chip analog
switches, and charges the external capacitor C2 to a voltage
equal to the DC offset voltage of that amplifier and the
instantaneous low frequeney noise voltage. A short time
later, the analog switches reconnect the on-Chip op amps in
the configuration shown in Mode 8. In this mode, op amp #2
has capacitor C2 (which was charged to a voltage equal to its
offset and noise voltage) connected in series. to its noninverting (+) input and nulls out the input offset and noise
voltage of the amplifier. While one of the op amps is processing
the input signal, the other is placed in the auto-zero mode and
charges its capacitor to a voltage equal to its equivalent DC and'

+INPUT
AZ

=__

low-frequency error voltage. The internal op amps are recon~
nected at a rate designated as the commutation frequency,
fCOM.
The CAZ amp concept offers a number of other advantages
to the designer, as compared to standard bipolar or FETinput op amps:
• Effective input offset voltages can be made between
1000x and 10,OOOx less withouttrimming.
• Long-term drift phenomena are compensated for and
dramatically reduced.
• Temperature effects are compensated for over a wide
range. Reductions can be as high as 100 times or higher.
• Supply voltage sensitivity is reduced.
The on-chip op amps are connected internally to the external
input and output terminals via CMOS analog switches,as
shown in Figure 2. The analog switch structure shown in
Figure 2 is arranged so that at any time three switches are'
open and three switches are conducting. Each analog switch
includes a P-channel transistor in parallel with an N-channel
transistor.
.

---,,..-7.=O.::;UTPUT

v-r_ _ _ _---'~OU=.TPUT

-INPUT

Figure 1: Diagramatic representation olthe 2 half cycl~s of operation of the CAZ OP AMP .

.

c,--~--------~------~

c, ---+--+-----..,
OUTPUT

+INPUT

--t---'

AZ

RF
(100kfi)

-INPUT------~----~

I~:UTATION
I
~

C[

~ '-FliEQUENCY) .

CL

Figure 2: Schematic of a~alog switches connecting each internal OP AMP to the external inputs and output.

5-126

ICL7600/lCL7601
APPLICATIONS
The ICL7600/lCL7601 CAZ op amp is ideal for use as a frontend preamplifier for dual-slope AID converters which
require high sensitivity for single-ended input sources such
as thermocouples.
A typical high-sensitivity AID converter system is shown in
Figure 3. The system uses an IntersillCL710912-bit monolithic AID binary converter, and is intended for direct interface with microprocessors. Both the ICL7600/lCL7601 and
the ICL71 09 use power supply voltages of±5V, and the entire
system consumes typically 2.5 mA of current.
The input signal is applied through a low-pass filter (150 Hz)
to the CAZ op amp, which is connected in a non-inverting
gain configuration of either 10 or 100. The internal oscillator
of the CAZ amp is allowed to run free at about 5,200 Hz, .
resulting in a commutation frequency of 160 Hz, with the DR
, terminal connected to V+ . The error-storage capacitors Cl
and C2 are each 1 p.F value, and provide a good
compromise between the minimum equivalent input offset
volta~e and the, lowest value of low-frequency noise.
The output signal is then passed through a low-pass filter
(1 MHand 0.1 p.F), with a bandwidth of 1.5 Hz. This results'in
an equivalent DC offset voltage of 1 to 2 p.V, and a peak-topeak noise voltage of 1.7 p.V, referred to the input olthe CAZ
amp. The output from the low-pass filt~r feeds directly into
the input of the ICL7109.

In a system such as that shown in Figure 3 there is a degree of
flexibility possible in aSSigning various gains to the ICL76001
ICL7601 pre-amplifier, and to various sensitivities ,for the
ICL~109. For optimum performance, the CAZ op amp must
amplify the input signal so that the equivalent 15p.V input
noise voltage of tl)e AID converter is masked. This implies a
gain of at least 10 for the CAZ op amp preamplifier.
On the other hand, if the gain olthe CAZ op amp is increased
too much, its output swing will be limited by the ±5V
supplies. This condition imposes a maximum gain of 200 to
produce an output of ±o..000005 times 4,096 times 200,or
;!:4.096V, .for a 5p. V per count sensitivity. Use of an ICL7600 is
recommended for low gains (<;201 and the ICL7601 for gains
of more than 20.
'
The'values of the integrating resistor and the reference
voltage must be chosen to suit the overall sensitivity of the
system. F.or example, in a system requiring a sensitivity of
5p.V per coiJnt, use a CAZ amp in a gain configuration of 50
(with ICL7601L Thus for a full scale count of 4096 (12 bits),
the input voltage to the'ICL7109would be 51' V times 50 times'
4096 or 1.024 volts. Since the ratio of input to reference is 2:1,
the value of the reference voltage becomes 0.512 and a 50k!}
integrating resistor is recommended. A system s'uch as that
shown in Figure 3 will allow a resolutionof 1°C for low
sensitivity platinumlrhodium junctions. ,For 0.1°C resolution, 'use high sensitivity thermocouples having copperl
constantan junctio·ns.

, 40
39t-----::o...
38
37
36
351----''---'----'
341-------,

1 GND
ICL7600/lCL7601

INPUT
10k

1
2
3
4
5
6
7

C,
C,
+IN
AZ
-IN
C2
C2

DR
NIC
OSC
v+
OUT
BIAS
v-

14
13
12
11
10
9

a

4
5
6
7

v+

'1Mll
9
DIGITAL
1/0

-5V ':'

990kll (190kll)
USE ICL7601 FOR GAIN OF >20
USE ICL7600 FOR GAIN OF 520

,

ICL1109

~O

11
12
13
14
15
16
17
18
19
20

29
'28
27
26
25
241----::1..
23
22
21

Figure 3: AID system with 5/lV'resolution using an ICL7600llCL7601 CAZ ~ME' Ilreamplifier
and an ICL7109 dual slope AID converter.
.
"

The low-pass filter between the output of the CAZ op amp
and the input of the ICL7109 AID converter can be used to
improve the signal-to-noise ratio of the system by reducing
bandwidth. A 10 Hz filter will result in an equivalent peak-to- _
peak noise voltage figure of 41' V. If the bandwidth is reduced

5-127

to 1.5 Hz, the peak-to-peak noise voltage wil,l be reduced to
about 1.7 I'V, a reduction by a factorofthree. The penalty for
this reduction will be a longer system response time; however
in most cases this will not be a major consideration, because
of the large thermal inertia of many thermocouple probes. :

n~olL

ICL7600/ICL7601
SOME HELPFUL HINTS
Testing the
Amplifier

ICL7600/lCL7601

CAZ

Operational

A simple and relatively accurate means of testing the CAZop
amp is to use a Tektronix 'rype 577 curve tracer, with the CAZ
op amp inserted in a special 14-lead socket which plugs into
a Tektronix 178, and which contains two soldered-in autozero capacitors of 1 /IF each. This simple and convenient
tester will provide most of the information needed for lowfrequency parameters. The test setup will allow resolution of
input offset voltages to about 10 /lV.
For greater accuracy, it is suggested that a breadboard be
built which minimizes thermoelectric effects and which
includes an output low-pass filter of the type shown in Test
Circuit #4. The output from the CAZ amp can be connected
to a dual-slope AID converter as shown in Figure 3. The lowfrequency noise can then be displayed on a storage scope or
on a strip chart recorder.

Bias Control

IB

The on-chip op amps consume over 90%' of the power
required for the ICL7600/1CL7601. Three externallyprogrammable bias levels are provided. These levels are set
by connecting the BIAS terminal t6 V+, GND or V-, for LOW,
MED or HIGH BIAS levels, respectively. The difference
between each bias setting is approximately a factor of three,
,which allows a 9:1 ratio between supply current and the bias
setting. The reason for this current programmability is to
provide the user Y'lith a choice of device power dissipation
levels, slew rate values (the higher the slew rate the better the
recovery from commutation spikes), and offset errors due to
chip "v9'tage drop" and thermoelectric ,effects (the higher
the power dissipation the higher the input offset error). In
most cases, the medium (MED BIAS) setting will be the best
'
choice.

Output Loading (Resistive)
With a 10 kfl load the output swing can .cover nearly the
entire supply voltage range, and the device can be used with
loads as low as 2k!1. However, with loads of less than 50 k!l,
the on-chip op amps become transconductance amplifiers,
since their output impedances are about 50 k!l each. Thus
the open-loop gain is 20 dB less with a 2 k!l load than it would
be with a 20 kn load. For high gain configurations requiring
high accuracy, output loads of 100 k!l or more are
suggested.
Another consideration which must not be overlooked is the
additional power dissipation of the chip which results from a
large output swing into a low value load. This added variable
can affect the initial input offset voltages under certain
cond itions.

Output Loading (Capacitive)
In many applications, it is desirable to include a low-pass
filter at the output to reduce high-frequency noise outside
the signal passband of interest. With conventional op amps,'
the obvious solution would be to place a capacitor across the
external feedback resistor to provide the low pass filter.
However, with the CAZ OP amp, this is not feasible because
of the nature of commutation voltage spikes. The voltage
spikes show a low impedance characteristic in the direction
of the auto-zero voltage, and a high impedance on the
recovery edge, as shown in Figure 4. It can be seen that the
effect of a large load capacitor is to produce an area error in
the output waveform, and hence an effective gain error. The
output low pass filter must be a high impedance type to avoid
output voltage area errors. For example, a 1.5 Hz filter should
use a 100 k!l resistor and a 1.0 /IF capacitor, or a 1.0 MIl
resistor and an 0.1/lF capacitor. This effect also causes
problems with integrator circuits.

Oscillator and Digital Considerations
The oscillator has been designed to run. free at about 5.2 kHz
when t~e OSC terminal is open-circuited. If the full divider
network is used, this will result in 11 commutation frequency
of about 160 Hz nominal. The commutation frequency is the
frequency at which the on-chip op amps are switched
between the signal processing and the auto-zero modes. A
160 Hz commutation frequency represents approximately
the optimum frequency. at which the input offset voltage
is .close to minimum, where the low-frequency noise is
acceptable, and where errors derived from noise spikes will
be low. Other commutation frequencies may proVide
optimization of other parameters, but always to the
detriment of major characteristics.
The oscillator is of a high impedance type, so that a load of
only a few picofarads on fhe OSC terminal will cause a
significant shift in frequency. It is therefore recommended
that if the desired frequency of the oscillation is 5.2kHz, the
terminal should be left unattached and open. In other
instances, it may be desirable to lock the oscillator to a clock
or to run it at another frequency. The ICL7600/lCL7601
provides two degrees of flexibility. First, the DR (division
ratio) terminal permits the user to choose between dividing
the oscillator by 32 (DR terminal to V+ ) or by 2 (DR terminal to
GND), to obtain the commutation frequency. Second, the
oscillator may have its frequency lowered by the addition of
an external capacitor connected between the OSC terminal
and V+, or system ground terminals. For situations which
require the commutation frequency to be locked onto a
master clock, the OSC terminal can be driven from TTL logic

Ai'

OUTPUT

INPUT
AC

GNO

RSOUACE

WAVEFORMS

OUTPUT
VOLTAGE

Figure 4: Effect of a load capacitor on outpui voltage waveforms.

5-128

r

ICL7600/lCL7601
(with resistive pull-up) or from CMOS logic, provi'ded that the
V+ supply (with respectto ground) is +SV (±1 0%) and the logic
driver also operates from a similar supply voltage. This is
because the logic section -- including the oscillator ~­
operates from an internal -SV supply referenced to V+
generated on-chip, and is not accessible externally.

amps are typically in the 10 pF range, and since it is desirable
to reduce the effective input offset voltage about 10,000
times, the offset voltage auto-zero capacitors C1 and C2 must
be at le~st 10,000 x 10 pF, or 0.11-'F each.
'

Thermoelectric Effects

VOLTAG'i;NO

,

OUTPUT

The ultimate limitations to ultra-high-precision DC
amplifiers are thermoelectric, Peltier or, thermocouple
effects in junctions consisting of various metals, alloys,
silicon, etc. Unless all junctions' are at precisely the same
temperature, small thermoelectric voltages will be produced,
generally about 0.1 J!.V/oC. However, these voltages can be
several tens of microvolts per °C for certain "thermocouple
materials:
In order to realize the extremely low offset voltages which the
CAl op amp can provide, it is essential to take precautions to '
avoid temperature gradients, All components should be
enclosed to eliminate air movement across device surfaces.
In addition, the supply volt~ges and power dissipation
should be kept to a minimum. Use the medium bias mode as
well as a high impedance load, and keep well away from heat
dissipated by surrounding equipment.

Component Selection
The two required auto-zero capacitors, C1 and C2, should
each be of 1.0 I-'F value. These are large values for nonelectrolytic capacitors, but since the voltages impressed on
them do not change significantly, problems of dielectric
absorption arid the like are not important.
Excellent results have been obtained in operation at
commercial temperature ranges using several ofthesmallersize and more economical capacitors, since the absolute
values of the capacitors is not critical. Even polarized
electrolytic capacitors rated at 1.0I-'F/SOV, though not
recommended, have been used with success.

Com mutating Voltage Transient Effects
While in most respects the CAZ op amp behaves like a
conventional op amp, its principal applications will be in very
low level, low-frequency preamplifiers limited to DC through
100 Hz. This is because of the finite switching transients
which occur in the input and output terminals due to commutation effects'., These transients have a frequency spectrum
beginning at the commutation frequency, and include all of
tlie higher harmonics. If the commutation frequency is
higher than·the highest in-band frequency, these transients
can be effectively blanked with a low-pass filter.
The input commutation transients arise when each of the onchip op amps experiences a shift in voltage equal to the input
offset voltage about (S-10mV) which occurs during the
transition to the signal processing mode from the autozero mode, Since, the input capacitances of the on-Chip op

r Wvt

:T .rw
A1A

WflYvvw
.lu ~lA

I1vw

3mS- - - l

'~AA"V'

~ \w

Ww 'vr~n

TIME-

Figure 5: Output waveform from Test Circuit 1.
The charge 'Which is injected into the op amp when it is
switched into the signal-processing mode produces a
rapidly-decaying voltage spike at the input, in addition to an
equivalent DC bias current averaged over a full cycle. This
bias current is directly proportional to the commutation
frequency, and in most'instances will greatly exceed the
inherent leakage currents of the input analog switches,
which are typically, about 1,0 pA at ambient temperature of
2SoC.
The output waveform of Test Circuit#1 (with no input) is
shown in Figure S. Note that the equivalent noise voltage
shown is amplified 1000 times, and that because of the finite
slew rate of the on-Chip op amps the 7 mV input transients
are ill!! amplified by ,1000.
The output transient voltage effects (as distinct from the
input effects which are propagated through the on-Chip op
amps) will occur if there is a difference in the output voltage
of the internal op amps between the auto-zerc;> modes and the
signal-processing modes. The output stage of the on-chip
op amp must slew from its auto-zero output voltage to the
desired Signal-processing output voltage. This is shown in
Figure 6, where the system is auto-zeroed to ground.
The duration of the output transients is greatly affected by
the gain configuration and the bias setting, since these two
parameters have an effect on system slew rate. At low gains
and high bias settings, the output transi,ent durations are
very short. For this reason there are two versions.of the CAl
op amp, the ICL7600 which is compensated for unity gain
and which can be used for gain configurations up to 20, and
the ICL7601, which is uncompensated and recommel1ded
for operation in gain configurations greater than 20. Thus,
when a signal is being processed in a high gain configuration, the effective output signal error is greater for the
, ICL7600 than it is for the ICL7601.

Non-Amplifier Applications
In principle, this is One of the few "chopper-stabilized" type
amplifiers that could be used as a':comparator; the transient
effects on the output will normally require careful
synchronism of output strobes with o.scillator drive. '

OUTPUT

Your

TIME-

Figure 6: Simple CAZ OP AMP circuit and the output voltage waveform.
5-129

II

ICL7605/1CL7606,
Commutating Auto-Zero (CAZ)
Instrumentation Amplifier

. FEATURES

lit

GENERAL DESCRIPTION

• Exceptionally low input offset voltage - 2p.V
• Low long term input offset voltage drift 0.2/J.v/year .
• Low input offset voltage temperature drift ...:..
0.05p.VloC
• Wide common mode input voltage range- 0.3V
above supply rail
• High common mode rejection ratio - 100 dB
• Operates at supply voltages as low as ±2V
• Short circuit protection oli outputs for ±5V
operation
• Static-protected inputs - no special handling
required
• Fabricated using proprietary MAXCMOS'· process
technology
• Compensated (ICL7605)or uncompensated
(ICL7606) versions

The ICL7605/1CL7606 commutating auto-zero (CAZ) instrumentation amplifiers are designed to replace most ofioday's
hybrid or' monolithic instrumentation amplifiers, for low
frequency applications from DC to 10 Hz. This is made
possible by the unique construction of this new Intersil
device, which takes an entirely new design approach to low
frequency amplifiers.
Unlike conventional amplifier deSigns, which employ three
op amps and require ultra-high accuracy in resistor tracking ,
and matching, the CAZ instrumentation amplifier requires
no trimming except for gain. The key features of the CAZ
principle involve automatic cOrTipensation for long term drift
phenomena and temperature effects, and a flying capacitor
input.
The ICL7605/1CL7606 is a monolithic CMOS chip which
consists of two analog sections - a unity gain differential to
single-ended voltage converter and a CAZ op amp. The first
. section senses ihe differential input and applies it to the CAZ
amp section. This section consists of an operational
amplifier circuit which continuously corrects itself for input
voltage errors, such as input offset voltage, temperature
. effects, and long term drift.
The ICL7605/1CL76D6 is intended for low-frequency
operation in applications such as strain gauges, which
require voltage gains from 1 to .1000 and bandwidths from
DC to 10Hz. Since the CAZ amp automatically corrects itself
for internal errors, the only periodic adjustment required is
that of gain, which is established by two external resistors.
The no-adjustment feature, combined with extremely low
offset and temperature coefficient figures, makes the. CAZ
instrumentation amplifier very desirable for operation in
severe environments (temperature, humidity, toxicity,
radiation, etc.> where equipment service is difficult.

SYMBOL
C3

v+

. +DIFF IN
-DIFF IN
OUTPUT

,AZ
-INPUT

PIN CONFIGURATION

AZ ~
. -INPUT ~

ORDERING INFORMATION

I

--

Order parts by the following part numbers: I

,

Compensated

. IN
Q-DIFF

.1 ...,

18

2

17 g

+DIFF IN

C4
316~C3
C4
4
15 C3
C2 ~ 5 .
14 c,
. C2 ~ 6
. 13 g'Cl
v- 7
12 DR
BIAS ~ 8
.11 g osc
OUTPUTe 9
10 v+

P

P

,

ICL7605CJN
ICL76051JN
ICL7605MJN

-

UncomPensated
ICL7606CJN
ICL760SiJN
ICL7606MJN

Package
CERDIP
CERDIP
CERDIP

Temperature
Range
O°C.to +70°C
'-25°C to +85°C
--55°C to +125°C

Order dice by the following part numbers: '
ICL7605/D
ICL7606/D

(outl(ne dwg IN)

\

5·130

ICL7605 I ICL7606

O~OIb

ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (sum of both positive and
negative supply voltages v+ to V-) ........... 18 Volts
DR Input Voltage •............. (V+ +0.3) to (V+ -8) Volts
Input Voltage (C1, C2, C3, C4 +DIFF IN,
-DIFF IN, -INPUT, BIAS, OSC)
(Note 1) ................... (V+ +0.3) to (V- -0.3) Volts
Differential Input Voltage (+DIFF IN to -DIFF IN)
,
(Note 2) ........ :......... +(V+ +0.3) to (V- -,Q.3) Volts
Duration of Output Short Circuit (Note 3) ..... Unlimited

Continuous Total Power Dissipation (at or below 25°C
free-air temperature) (Note 4) .•...•.•.......• 500 mW
Operating Temperature Range:
ICL7605/ICL7606CJN.................... 0 to +70°C
ICL7605/1CL76061JN ................. -25°C to +85°C
ICL760511CL7606MJN ....... , ...... -55°C to +125°C
Storage Temperature Range .......... .,..55°C to +150°C
Lead Temperature (soldering 60 seconds) ........ 300° C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any othe(conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Due to the SCR structure inhe~ent in all CMOS devices, exceeding these limits may cause destructive latchup. For this reason, it is
recommended thaI no inputs from sources operating on a separate power supply be applied to the 7605/6 before its own power supply is
established, and that when using multiple supplies, the supply for the 7605/6 should be turned on first.
Note 2: No restrictions are placed on the differential input voltages on either the+DIFF IN or-DIFF IN inputs so long as these voltages do not
exceed the power supply voltages by more than 0.3V,
.
,
Note 3: The outputs may be shorted to ground IGNDl or to either supply IV+ or V-l. Temperatures and/or supply voltages must be limited to
insure that the dissipation ratin'gs are not exceeded.
Note 4: For operation above 25°C free-air temperature, derate 4mW/o C from 500 mW above 25° C.

BLOCK DIAGRAM

r't

I

BIAS

~

+

OP

C3

DIFFERENTIAL
TO SINGLE
ENDED VOLTAGE
CONVERTER
ANALOG
SWITCH
SECTION

+DIFF IN
-DIFF IN

CAZ
OP
AMP
INPUT
AZ ANALOG
SWITCH
SECTION

71

RF'
'V

.~2

~

o~

.~

--

f----<> OUTPUT

1;

rcj I

AZ
-INPUT

OSC

I

CAZ
OP
AMP
OUTPUT
ANALOG
SWITCH
SECTION

I

RC
OSCILLATOR

+2 OR +32
:
DiviDER NETWORK

DiR
(DIVISION RATIO)

~

rl

~

LEVEL
TRANSLATORS

+2

t

Y

l

LEVEL
TRANSLATORS

5-131

r

STABILIZED
POWER
SUPPLY

II

L

ICL760S/ICL7606
OPERATING CHARACTERISTICS
Test Conditions: V+ = +5 volts. V-= -5 volts. TA =+25 0 C. DR pin connected to v+ (feoM''' 160Hz. feoM1 '" 80Hz).
C1 =C2=C3=C4 = 1p.F. Test Circuit 1 unless otherwise specified.

PARAMETER
Input Offset Voltage
!

SYMBOL

Average Input Offset
Voltage Temperature
Coefficient
Long Term Input
Offset Voltage Stability
Common Mode Input Range
Common Mode Rejection Ratio

tNoslIH

Vos

I1Vos/l1t
CMVR
CMRR

CONDITIONS
Rs $ 1k!!
Low Bias Setting
Med Bias Setting
Hgh Bias Setting
MIL version over temp.
Med Bias Setting
Low·or Med Bias Settings-55°C > TA;' +25°C
+25°C> TA > +85°C
+25°C > TA > +125°C
Low or Med Bias Settings

MIN

0.01
0.01
0.05
0.5
5.3

Cosc - O. DR connected to V • C3 - C4 - 1/lF
Cosc=1j.1F.DR connected to GND. C3 = C4 'f 1/tF
Cosc=1/lF.DR connected to GND. C3 = C4 = 10/lF

Power Supply Rejection Ratio
-INPUT Bias Current

PSRR
-ISlAS

Equivalent Input Noise
Voltage peak-to-peak

enp-p

Equivalent Input·
Noise Voltage
Voltage Gain

en

Av

;Any bias setting. fc 160Hz
. (Includes charge injection currentsl
low Bias Mode
Band Width
Med Bias Mode
0.1 to 10Hz
High Bias Mode
Band Width
0.1 to 1.0Hz
All Bias Modes /
:
Low Bias Selling
RL '\ 100k!!
Med Bias Selling
High Bias Selling
RL - 1M!!
RL = 100k!!
RL = 10k!!
Positive Swing
Neqative Swing
C3 - C4 -1/lF
All Bias Modes

-'

Band Width of Input
Voltage Translator
Nominal Commutation
Frequency
Nominal Input Converter
Commutation Frequency
Bias Voltage to define
Current Modes
Bias (Pin 81 Input Current
Division Ratio Input
Current
DR Voltage to define
Oscillator division ratio
Effective Impedance of
Voltage Translator
Analog Switches
~uPPIY Current

Operating Supply
Voltage Range

±VO

GBW

DR
DR
DR
DR

Connected
Connected
Connected
Connected

fCOM

Cosc - OpF

fCOM1

Cosc - OpF

VSA
VSM
VSL
ISlAS
lOR

Low Bias Selling
Med Bias Setting
High Bias Selling

VORH
VORL

Internal oscillator division ratio 32.
Internal oscillator division ratio 2

to
to
to
to

90
90
80

V+-V-

±5
+20'
0.1
0.1 ..
0.15

,
+5.3

dB
dB
dB
nA

1.5

./lV
/lV
/lV
/lV

1.7
105
105
100
±4.9
±4.8

160
2560
80
1280
V+
GND

v-·

V"+p.3
V+-1.4
V-+0.3

±30
_ ±30

V' -8..0$ VOR $ V' +0.3 volt
V'-o.3
V+-8

V'+0.3
\1+-1.4
30

High Bias Selling
Med Bias Setting
Low Bias Setting
High Bias Setting
Med or Low Bias Setting

5-132

7
1.7
0.6
5
.4

/lV/DC
/lV/DC
/lV/Year

100
104
110
0.15

-4.5

V -0.3
V-+1.4
V--o.3

/lV
/lV
/lV
/lV
'/lV/oO

V
dB

10
V
GND
V
GND

UNIT

94

+4.4

RAS
Isupp

MAX'

4.0
4.0
5.0

...

Maximum Output
Voltage Swing

VALUE
TYP
±2
±2
±7

dB
dB
dB
V
V
- V
V
Hz
Hz
Hz
Hz
Hz
V
V
V
pA
pA
V
V
k!!

15
5
1.5
10
10

mA
rnA
rnA
V
V

O~OIb

ICL760S/ICL7606
INPUT OFFSET VOLTAGE AND.
PK·TO-PK NOISE VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGES

INPUT OFFSET VOLTAGE AS A
FUNCTION OF AMBIENT TEMPERATURE

>

+10

NEGATIVE POWER SUPPLY VOLTAGE
-7.5
1>.5
-5.5
-4.5
-3.5
-2.5
>
TA = 25'C
"Av = 1000
w
Rs'; lkll
20
~ -4.0
el, C2 = 1.0j.lF
IV+ - V-I = 10 VOLTS
o
IcOM = 160 Hz
>
I- -3.0
15
OFFSET VOLTAGE _
w

TEJT CI~CUITll
C, = C, = l"F
fCOM = 160 Hz

"~ +8

!!>

..:

~ +6

g
I-

w

+4

m

u..

~ +2

/

I-

~
~

0

I

~

~

-4
-50

z

-25
25
50
75 100 125
TA - AMBIENT TEMPERATURE - 'c

VO_rGE;;:
r---, r-' N~lrE,
- ---

=

>

w

-7

Av

0

~

2.5!:

OL-~-U~L-~~_L-~~L-..J

100

lk

10.0

~

7.5

J:

i:!~-5I-'-'...,..,i::'M"""k-'\;f-bI"h~±:-'::':+=--I 5.0

0

2.5

0

,

~-3

IcOM -

o

",

- ;;-OiSEV;L~AGE

~-1

o

J
/V

105

6

~m 100

0'"

25g ::;;1
w ZO
0>= 95
20
::;;..:
z ::;;a:
OZ
15~ 00 90
N

!:0

o

INPUT CURRENT AS A FUNCTION
OF COMMUTATION FREQUENCY

MAXIMUM OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT LOAD RESISTANCE

Om

-r -1

!!>S!: -400

II

zw

>=a: -350

a: a:
~~-300
~I­

~~-250

\ /
7

~~-150
.a:

.m~ -100

~ -50
.10

V

I--"

I
I

I

INiB NON INVERTING
INPUT CURRENT

Z--200
'!!>

I

1/

+ T.A : 25'C
IV
11 01VOLTS

I--"'"

I

If

I

/

II
IJ

/

~INJiRTING

INPUT CURRENT

100
1000
fCOM - COMMUTATION FREQUENCY - Hz

+5

14

5

W~+3
!!>z

~5+2

oa:

>"+1

~~

~

0

TA = 25'C
f---IV+-V-I = 10V
RL 'CONNECTED TO GND_

5~ -1
Oz

:-~ -2

g~a: -3
-4

7

1.0
10.0
C3, C. - VOLTAGE CONVERTER
CAPACITOR VALUES -"F

~

~ 6

l/

/

/

-

8

./

1-0

V

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

f-"

>+4

.;...r--

/

1/

0.1

16

fc=40Hz

. / "'fc = 160 Hz
.~
./
. . . --;:r= ~rio Hz

/

/

8n

./

L

/

I§

a:w
a:-,
::;;w
0 oa: 85

8
10
12
SUPPLY VOLTAGE

2

~

5
J:

J.t-

TA - +25 0
V--V- = 10V
C, = C, = l"F

10~

1.--"""

1k
COMMUTATION FREQUENCY - Hz

COMMON MODE REJECTION RATIO
AS·A FUNCTION OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED
VOLTAGE CONVERTER
CAPACITORS

...~

-

~

10k

~-500

N

0
10k

fCOM - COMMUTATION FREQUENCY· Hz

a: ' -450

o

1---4

~tJ~:s:F:~to~t;"ttstI17.5
Il.
~
:I!
~-2

10

m

30!!>

Cl, C, = 1.0"F
IV+I = IV-I
fCOM = 160 Hz

w
'~ff

-5 f---Hf-H-f--ChI-H-+-+-+++--l5.0 ~
~
0

Il.

>

12.5 w

,;.

= 1000

Rs :::;:lkU

100 Z

UJ

.~o

w 0

5z Iii>

35~

Tl = 25!C

~

Sl '1>
~ ...~
15.0 gW' ;!-5
17.5

f---Hf-H-T':f--+-1-H~+-*+++--l12.5!!! g

tu -10
tt

0

INPUT OFFSET VOLTAGE AND
PK-TO-PK NOISE AS A FUNCTION
OF SUPPLY VOLTAGE (V+-V-)

-20 ,-.."rn---=--=""---""TTrr-r-, 20.0 ';

o~
>

~ -15

,+2.5
+3.5
+4.5
+5.5
+6.5
+7.5
- POSITIVE POWER SUPPLY VOLTAGE

INPUT OFFSET VOLTAGE AND
PK-TO-PK NOISE VOLTAGE AS A
FUNCTION OF COMMUTATION
FREQUENCY (Cl, C2.= O.lI'F)

~..: -15

15.0 ~

J:
~ Il.

-;- -1.0

.

I-'HI BIAS

V

TA = 25'C
NO LOAD- I NO INPUT

~ 5
a:

:::>

04

~

:l::

"

-5
100

3
:::>
, 2

m

!!!

I '~
lk
10k
RL - LOAD RESISTANCE

5-133

100k

III
..:

~ !!>

g

20.0 ~
17.5

5

:::>

"-

-20 r-",,,,,""---o--......,..,.,..,,.-..,--,-,rrr..,--,

10 ~ 0

Il.

>

~

w ~
Sl w

~ ~-10~~~~~~rr~t.'~

u...
0-2.0
I-

/

"' -2

/

V

INPUT OFFSET VOLTAGE AND
PK-TO-PK NOISE VOLTAGE AS A
FUNCTION OF COMMUTATION
FREQUENCY (Cl, C2 = 11'F)

o

2

--

./
MED BIAS
LO BIAS

I

4
6
8
10
12
14
16
IV+-V-I - SUPPLY VOLTAGE - VOLTS

~
I-

ICL760S/ICL7606
SUPPLY CUR.RENT AS A
FUNCTION OF TEMP.ERATURE

~

~

H'~'AS.

~

,

~

t-.....

...
i5

5

:;)

4

II:
II:

•

CJ

>

~

'Il.

10k
TA = 25'C'
5 < ly+·V-' < 10 VOLT,S::

."

1""'00.
lose ~ 5.2 kHz ,:
For Cose - 0 pF

~

y+.y- = 10 VOLTS
NO LOAD
-I-NO INPUT

3

-

:;)

'"

OSCILLATOR FREQUENCY AS A FUNCTION
, OF EXTERNAL CAP~CITIVE LOADING

2

--

MED BIAS
LO BIAS

.0

I\.

--

t-

r--

10

-50 -25
0
25
50
75 100 125
TA • AMBIENT TEMPERATURE 'c

1
10
100
1000
Cose • OSCILLATOR CAPACITANCE· pF

, I

. FREQUENCY RESPONSE'OF THE 10 Hz LOW
PASS FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 2).

AMPLITUDE RESPONSE OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED VOLTAGE CONVERTER

.."

'\

J

~

w

'"z -10

TA - +25'C
(Y··V-) = 5 VOLTS
C, = C2 =,C. = c,'= lpF

.~

~ -20

w

J '\I~E:=B~::Hz
i

g-ao

~

... -40

!::
Il.

~

I

I -50
~

I 'ALIASING

-60

'\

FI9r

I,R E
10
' 100
1,000
I - FREQUENCY - Hz

1

,------1, AZ -DIFF IN , •.

,-----1. -IN +DIFFIN 17
4C,

C.,.
C.,.

5C2

'C114

.c,

C".
7V~
DR12
• BIAS
OSC"
• OUTPUT y. ,.

0

II

,

r-,JA~I25ld

~-10
~

:3

::;-20

Wt '\

I

....

"w

~

o
~
~-30

'\

1.1
\

~

~

~-40

'\
10,000'

1\
2

,

3 4 5
10
20 304050
I· FREQUENCY· Hz

100

GND OR YOLTAGE
BETWEEN
(V, +0.3) AND '
(Y- -iI.3) VOLT
lpF

• C2

+5Y

~.A/\r1'---OUTPUT

1M

lK

Vour

YOLTAGE GAIN = 1000

TESi CIRCUIT 1: USE TO MEASURE:
V
a) INPUT OFFSET VOLTAGE ( 10qooUT)
b) INPUT EaUIV NOISE VOLTAGE
c) SUPPLY CURRENT
d), CMRR
e) PSRR

TEST CIRCUIT 2: DC to 10Hz (1Hz) Unity Gain Low Pass Filter

5-134

ICL760S/ICL7606

O~OI!"

DETAILED DESCRIPTION
CAZ Instrumentation Amp Overview

CAZ Op Amp Section

The CAZ instrumentation amplifier operates on principles
which are very different from those ofthe conventional three
op amp designs, which must .use ultra-precise trimmed
resistor networks in order to achieve acceptable accuracy.
An important advantage of the ICL760S/ICL7606 CAZ instrumentation amp is the provision for self-compensation for
internal error voltages, whether they are derived from
steady-state conditions, temperature, supply voltage fluctuations, or are variable over a long term.
The CAZ instrumentation amplifier is constructed with
monolithic CMOS technology, and consists of three distinct
sections, two analog and one digital. The two analog
sections - a differential.to single-ended voltage converter,
and a CAZ op amp - have on-chip analog switches to
steer the input signal. The analog switches are driven from a
self-contained digital section which consists ·of an RGoscillator, a programmable divider, and associated voltage
translators. A functional layout of the ICL7605/1CL7606is
shown in Figure 1.

Operation of the CAZ amp section of the ICL7605/1CL7606
instrumentation amplifier is best illustrated by referring to
Figure 2. The basic amplifier configuration, represented by
the large triangles, has one more inputthan does a regular op
amp - the AZ,.or auto-zero terminal. The voltage onthe AZ
input is that level at which each ofthe internal op amps will be
auto-zeroed. In Mode A, op amp #2 Is connected in a unity
gain mode through on-chip analog switches. It chiuges
external capacitor C2 to a voltage equal to the DC input offset
voltage of the amplifier plus the instantaneous lowfrequency noise voltage. A short time later, the analog
switches reconnect the on-chip op amps to the configuration
shown in Mode B. In this mode, op amp #2 has capacitor C2
(which is charged to a voltage equal to the offset and noise
voltage of op amp #2) connected in series to its non-inverting
(+) input in such a manner as'to null out the input offset and
noise voltages of the amplifier. While one of the on-chip op
amps is processing the input signal, the second op amp is in
an auto-zero mode, charging a capacitor to a voltage equal
to its equivalent DC and low frequency error voltage. The onchip amplifiers are connected and reconnected at a rate
designated as the commutation frequency (feoM), so that at
all til)1es one or the other of the· on-chip op amps is
processi'ng the input Signal, while the voltages on capacitors
Cl and C2 are being updated to compensate for variables
such as low frequency noise voltage and input offset voltage
changes due tote~perature, drift or supply voltages effects.

-l

+DIFFIN , DIFFERENTIAL
TO SINGLE
I
ENDED "
I
VOLTAGE
-DIFF IN I
CONVERTER

I

I OUTPUT

Figure 1: Simplified Block Diagram

The ICL7605/1CL7606 have approximately constant equivalent input' noise voltage, CMRR, PSRR, input'offset voltage
and drift values independent of the gain configuration. By
comparison, hybrid-type modules which use the traditional '
three op amp co'nfi'guration have relatively ,poor
performance at low gain (1 to 10m with improved
performance above a gain of 100.
The only major limitation of the ICL760S/ICL7606 is its lowfrequency operation (10 to 20 Hz maximuml. However in
many applications speed . is not the most important
parameter.

Compared to the standard bipolar or FET input op amps, the
CAZ' amp scheme demonstrates a number of important
advantages:
• Effective input offset voltages can be reduced from 1000
to 10,000 times without trimming.
• Long-term offset voltage drift phenomena can be
compensated and dramatically reduced.
• Thermal effects can be compensated for over wide
, operating temperature range. Reductions can be as much as
100 times or beUer.
• Supply voltage sensitivity is reduced.
CMOS processing is ideally suited to implement the CAZ
amp structure. The digital section is easily fabricated, and

~_ _ _ _~~O~UTPUT

a

v-r_ _ _......;.--.::~O~UTPUT

Figure 2: Diagrammatic representation of, the 2 half cycles of operation of the CAZ OP AMP.

5-135

t;I

1:1

D~DI!..

ICL760S/ICL7606

C,---t--------~--------i

CL

OUTPUT

"INPUT

~

INPUT
FROMFIG4

.

AZ
~INPUT

RF
(100kll)

e['

------,------'

.

(COMMUTATION
FREQUENCY)

CL

.

Figure 3: Schematic of analog.~witches connecting each internal OP AMP to its inputs and output.

.. the transmission gates (analog switches) which connect the'
on-chip op amps can be constructed for minimum charge
injection and the widest operating voltage range. The analog
section, which includes the on-chip op amps, contributes
performance figures which are similar to bipolar or FET input
designs. CMOS structure provides the CAZ amp with openloop gains of greater than 100 dB, typical input offset
vol~ages of ±5 mV, al\d ultra-low leakage currents;typically 1
pA.
.

·
m

.

DIFFERENTIAL-TO-SINGLE-ENDED
UNITY GAIN VOLTAGE CONVERTER
An idealized schematic of a voltage converter block is shown
in Figure 4. The mode of operation is quite Simple, involving
two capacitors and eight switches. The switches are
arranged so that four are open and four are closed. The four
conducting switches connect one of the capacitors across
the differential input, and the other from a ground or
reference voltage to the input of the CAZ instrumentation
amp. The output signal of this configuration is shown in
Figure 5, where the voltage steps equal the differential
voltage (VA-VB) at commutation times a, b, c, etc. The output
waveform thus represents all informaUon contained in the
input Signal from DC up to the commutation frequency,
commutation and noise voltages are added. Sampling theory
states that to preserve the integrity of theiinformation to be
processed, at least two samples must be taken within a
period (1If) of the highest frequency of the signal being

.

The CMOS transmission gates connect the on-chip op amp;
to· external input and output terminals, as shown in Figure 3.
Here, one op amp and its associated analog switches are
required to connect !!ach on-chip op amp, so that at anytime
three switches are open and three switches are closed. Each
analog switch consists of a P-channel transistor in parallel
with anN-channel transistor.

, 5,

'ls,
+DIFF IN
S3

r-

..

C3

(S4
INPUT OF AMPLIFIER
c.

GND OR REFERENcE VOLTAGE
S5

'ISs
-DIFF IN
S,

----<

MODE
S,
52
S3
54
S5
A
CLOSED OPEN CLOSED OPEN CLOSED
B
OPEN CLOSED OPEN CLOSED OPEN'
The frequency at which mode. A & B are cycled I.
known a. the INPUT COMMUTATION FREQUENCY

(Ss
Figure 4: Schematic of the differential to single ended voltage converter

5-136

S,
CLOSED
OPEN

ICL7605 I ICL7606
~~~~------t---~-t------+-~~~---o

1---1.
___~REFERENCE
I

OUTPUT
VOLTAGE

GND OR

VOLTAGE

INPUT COMMUTATION
PERIOD (1/fcOM')

Figure 5: Input to Output Voltage waveforms from the differential to
single ended voltage converter. For additional information, see
frequency characteristics in Amplitude Response of the Input
Differential to single ended voltage converter graph on page 5.

sampled. Consequently this scheme preserves information
up to the commutation frequency. Above the commutation
frequency, the input signal is transferred to a lower
frequency. This phenomenon is known as aliasing. Although
the output responds above the commutation frequency, the
frequencies of the output response.s have been aliased down
to frequencies below the commutation frequency.
The voltage converter is fabricated with CMOS· analog
switches, which contain a parallel combination of P-channel
and N-channel transistors. The switches have finite ON
impedances of 30kO, plus parasitic capacitances to the
substrate. Because of the charge injection effects which
appear at both the switches and the output of the voltage
converter, the values of capacitors Co and Co must be about
1/LF to preserve signal translation accuracies to (l.01%. The
1/LF capacitors, coupled with the 30kO equivalent
impedance of the switches, produce a low-pass filter
response from the voltage converter which is approximately
3 dB at 10 Hz.

APPLICATIONS
USING THE ICL7605/1CL7606 TO BUILD A DIGITAL READOUT TORQUE WRENCH
A typical application for the ICL7605/ICL7606 is in a strain
gauge system, such as the digital readout torque wrench
circuit shown in Figure 6. In this application, the CAZ instrumentation amplifier is used as a preamplifier, taking the
differential voltage of the bridge and converting this voltage
to a single-ended voltage reference to ground. The signal is
then amplified by the CAZ instrumentation amplifier and
applied to the input of a 3-1/2 digit dual-slope AID converter
chip for LCD panel meter display. The AID converter device
used in this instance is the IntersillCL7106.
In the digital readout torque wrench circuit, the reference
voltage for the ICL71 06 is derived from the stimulus applied
to the strain gauge, to utilize the ratiometric capabilities of
the AID. In order to set the full-scale reading, it is required

that, given a certain strain gauge bridge with a defined
pressure voltage sensitivity, a value of gain for the ICL7605/
ICL7606 instrumentation CAZ amp be selected along with an
app. ropriate value for the reference voltage. The gain should
be set so that at full scale the output will swing about 0.5V.
The reference voltage required is about one-half 'the
maximum output swing, or appr~ximately 0.25V.
In this type of system, only one adjustment is required. Either
the amplifier gain or the reference voltage must be varied for
full-scale adjustment. Total current consumption of all'circuitry, less the current through the strain gauge bridge, is
typically2 mAo The accuracy is limited only by resistor ratios
and rhe transducer.

OSC 140

1 AZ -DIFF IN 1B
,-----I2-IN +DlFF IN"
3C4

:g;

C316

ICL7606

6 C2

g:::

,.

C113

7 v'
DR12
• BIAS
OSC11
9 OUTPUT
V'"

11
12

13
14
15
16

10kll

1MIl
R,

Av

~

"1B
Rl + R2
--R-,-

~

101 TIMES

20

5-137

V·

v-

IN H131

IN L03.
AZ29 .47"F
BUFF 2B
.22"F
INT"

v'

V-26
25

ICL7106

24

19

23
22

2.

21

LCD DISPLAY

Figure 6: 3-1/2 Digit Digital Readout Torque Wrench

100k

OSC 239
OSC 338
'TEST 3'
REF Hf36
REF L03S
C REF3'
C REF3'
COMM3'

'}

47kll
.".

II

18

O~OIl,

ICL760S/ICL7606
Outp~t

SOME HELPFUL HINTS
Testing the ICL760S/ICL7606

CAZ Instrumentation Amplifier
Test Circuits #1 and #2 provide convenient means of
measuring most of the important electrical parameters of the
CAZ instrumentation amp. The output signal can be viewed
on an oscilloscope after being fed through a low-pass filter. It
is recommended that for most applications, al0w~pass filter
of about 1.0 to 1.S Hz be used to reduce the peak-to-peak
noise to about the same level as the input offset voltage.
The output low-pass filter must be of a high-input impedance
type-(not simply a capacitor across the feedback resistor R2)
at about 100k!1 and 1.0ILF so that the output dynamic loading
on the CAZ instrumentation is about 100k!1.

Bias Control
The on-chip op amps consume over 90% of the power
required by thelCL760S/ICL7606 instrumentation op amp.
For this reason, the internal op amps have externallyprogrammable bias levels. The.se levels are set by
connecting the BIAS terminal to either V+, GND, or V- for
LOW, MED or HIGH BIAS levels, respectively. The difference
between each bias setting is about a factor of 3, allowing a 9:1
ratio of power supply versus bias setting. This current
programmability provides the user with r:i choice of device
power dissipation levels, slew rates (the higher the slew rate,
the better the recovery from commutation spikes), and offset
errors due to "IR" voltage drops. and thermoelectric effects
(the higher the power dissipation, the higher the input offset
error). In most cases, the medium bias (MED BIAS) setting
will be found to be the best choice.

Output Loading (Resistive)
With a 10k!1 load, the output voltage swing can vary across·
nearly the entire supply voltage range, and the device can be
used with loads as low as 2k!1.
However, with loads of less than SOk!1, the on-Chip op amps
will begin to exhibit the characteristics of transconductance
amplifiers, since their respective output impedances are
nearly SOk!1 each. Thus the open-loop gain is 20 dB less with
a 2k!1 load than it would be with a 20k!1 load. Therefore, for
high gain configurations requiring high accuracy, an output
load of 100k!1 or more is suggested.
There is another consideration in applying the CAZ instrumentation op amps which must not be overlooked, and that
is the additional power dissipation of the chip which will
result from a large output voltage swing into a low resistance
load. This added power dissipation can affect the initial input
offset voltages under certain conditions.

Loading (Capacitive)

In many applications, it is desirable to include a low-pass
filter at the output of the CAZ instrumentation op amp to
reduce high-frequency noise outside the desired signal
passband. An obvious solution when using a conventional
op amp would be to place a capacitor across the external
feedback resistor and thus produce a low-pass filter.
However, with the CAZ op amp concept this is not possible
because of the nature of the commutation spikes. These
voltage spikes exhibit a low-impedance characteristic in the
direction of the auto-zero voltage and a high-impedance·
characteristic on the recovery edge, as shown in Figure 7. It
can b·e seen that the effect of a large load capacitor produces
an area error in the output waveform, and hence an effective
gain error. The output low-pass filter must be of a highimpedance type to avoid these area errors. Forexample, a 1.S
Hz filter will require a 100k!1 resistor and a 1.0JLF capacitor,
or a 1 M!1 resistor and an 0.1ILF capacitor.

Oscillator and Digital Circuitry Considerations
The oscillator has been desigried to run free at about S.2 kHz
when the asc terminal' is open circuit. If the full divider
network is used, this will result in a nominal commutation
frequency of approximately 160 Hz. The commutation
frequency is that frequency at which the on-Chip op amps are
switched between the signal processing and the auto-zero
modes. A 160 Hz commutation frequency represents the
best compromise between input offset voltage arid low
frequency noise. ather commutation frequencies may provide
optimization of some parameters,:but always at the expense
of others.
The oscillator has a very high output impedance, sothat a
load of only a few picofarads on the asc terminal will cause
. a significant shift in frequency. It is therefore recommended·
that if the natural oscillator frequency~is desired (S.2 kHz) the
,terminal remains open circuit. In other instance.s, it may be
desirable to synchronize the oscillator with an external clock
,source. or to run it at another frequency, The ICL760S1
ICL7606CAZ amp provides two degrees of flexibility in this
respect. First. the DR (division ratio) terminal allows a choice
of either dividing the oscillator by 32 (DR terminal to V+) or by
2 (DR terminal to GND) to obtain the commutation
frequency. Second, the oscillator may have its frequency
lowered by the addition of an external capacitor connected
between the asc terminal and the V+ or system GND
terminals. For situations which require thatthe commutation
frequency be synchronized with a master clock, (Figure 8)
the asc terminal may be driven from TTL logic (with
resistive pull-up) or by CMaS logic,provided that the V+
supply (with respect to ground) is +SV (±10%) and the logic
driver also operates from a similar voltage supply. The

f\f\

INPUT
AC
WAVEFORMS

GND

RSOURCE

OUTPUT
VOLTAGE

Figure 7: Effect of a load capacitor on output voltage waveforms.
5·138

O~OIL

ICL7605 I ICL7606,
, - - - - - 1 1 AZ

-DiFF IN 18
+DIFF IN 17

3 C4
4 C4
5 C2

C316
- C315
C,14

.-----1, -IN
6 C2
7

v-

'BIAS
9

C,13

TTL
OR
CMOS
LOGIC

DR12

OSClll---~I--c(

OUTPUT

V'" 10

22kn

USE RL FOR TTL LOGIC
(NOT NEEDED FOR CMOS)

Figure 8: ICL7605 being clocked from external logic into the
oscillator terminal.

reason for this. requirement is that the. logic section
(including the oscillator) operates from an internal
-5V supply, referenced to V+ supply, which is not accessible
externally.

Thermoelectric Effects
The ultimate limitations to ultra-high-sensitivity DC
amplifiers are due to thermoelectric, Peltier, or thermocouple effects in electrical junctions consisting of
various metals (alloys, silicon, etc.) Unless all junctions are at
precisely the same temperature, small thermoelectric
voltages will be produced, generally about 0.1IlV/oC.
However, these voltages can be several tens of microvolts
per ° C for certain thermocouple materials.
In order to realize the extremely low offset voltages which the
CAZ op amp can produce, it is necessary to take precautions
to avoid temperature g·radients. All components should be
enclosed to eliminate air movement across device surfaces.
In addition, the supply voltages and power dissipation
should be keptto a minimum by use of the MED BIAS setting.
Employ a high impedance load and keep well away from
equipment which dissipates heat.

Component Selection
The four capacitors (Cl thru C4) should each beabout 1.0IlF.
These are relatively large values for non-electrolytic
capacitors, but'since the voltages stored on them change
significantly, problems of dielectric absorption, charge
bleed-off and the like are as significant as they would be for
integrating dual-slope AID converter applications. Polypropylene are the best for C3 and'C4, though Mylar may be
adequate for Cl and C2.
Excellent results have been obtained for commercial
temperature ranges using several of the less-expensive,
smaller-size capacitors, since the absolute values of the
capacitors are not critical. Even polarized electrolytic
capacitors rated at 1.01lF and 50V have been used successfully at room temperature, although no recommendations
are made concerning the use of such capacitors.

Commutation Voltage Transient Effects
. Although in most respects the CAZ instrumentation
amplifier resembles a conventional op amp, its principal
applications will be in very low level, low-frequency preamplifiers limited to DC through 10 Hz. The is' due to the
finite switching transients which occur at both the input and

5·139

output terminals because of commutation effects. These
transients have a frequency spectrum' beginning at the
commutation frequency, and including all of .the higher
harmonics of the commutation frequency. Assuming that the
commutation frequency is higher than the highest in-band
frequency, then the commutation transients can be filtered
out with a low-pass filter.
The input commutation transients arise when each of the onchip op amps experiences a shift in voltage which is equal to
. the input offset voltages (about 5-10mV), usually occurring
during the transition between the signal processing mode.
and the auto-zero mode. Since the input capacitances of the
on-chip op amps are typically in th'e 10 pF range, and since it
is desirable to reduce the effective input offset voltage about
10,000 times, the offset voltage auto-zero capacitors Cl and
C2 must have values of at least 10,000 x 10 pF, orO.1IlFeach.
The charge that is injected into the input of each op amp
when being 'switched into the' signal processing mode
produces a rapidly-decaying voltage spike at the input, plus
an equivalent DC input bias current averaged over a full
cycle. This bias current is di rectly proportional to the
commutation frequency, and in most instances will greatly
exceed the inherent leakage currents of the input analog
switches, which are typically 1.0 pA at an ambient
temperature of 25° C.
The output waveform in Test Circuit #1 (with no inputsignall
is shown in Figure 9. Note that the equivalent noise voltage is
amplified 1000 times, and that due to the slew rate of the o n - I
chip op amps, t~e input transients of approximately7 mVare
not amplified by 1000.

j

! - - s m s - - - ! /gg'~~~i~ril~kI~s~~%~~E ENDED
OUTPUT
VOLTAGE
'

GND

T~

III

III

2r/,~lNNlt'If!v'v.,aiNhWN¥ ,wAWtI,\\,ly
1I

3mS-i" CAZ OP·AMP
'I
TRANSIENTS

TIME-

Figure 9: Output waveform from Test Circuit 1.

Layout Considerations
Care should be exercised in positioning components on the
PC board, particularly the capacitors Cl, C2, C3 and C4, all of
which must be shielded from the OSC terminal. Also,
parasitic PC board leakage capacitances associated with
these four capacitors should be kept as low as possible to
minimize charge injection effects.

ICL761 XI
762X/763X/764X
Low PowerMAXCMOSTM
Operational Amplifiers
'FEATURES
•
•
•
•
•
•
•
•
•

APPLICATIONS

Wide operating voltage range ±0.5V to ±sv
Single Ni-cad battery operation
High input impedance - 1012 0
Programmable power consumption - as low
as 10JLW
Input current lower than BIFETs ~ typ 1pA
Available as singles, duals, triples, andquads
Output voltage swing ranges to within millivolts of
V- to V+
'
Low power replacement for many standard op amps
Compensated and uncompensated versions

• Portable instruments
• Meter amplifiers
• Telephone headsets
• Me~ical instruments
• Hearing aid/microphone • High impedance buffers
amplifiers
A number of special options are available. They include:
• Single, dual, triple, and quad configurations
• Internally compensated and uncompensated
versions
• Inputs protected to ±200V (ICL7613/15)
• Input common mode voltage range greater than
supply rails (ICL7612)
Note: See page 2 for table of options.

,SCHEMATIC

®

OFFSET

10

SETTING
STAGE

OUTPUT
STAGE

I

I

"
+

>-------1

· .. 0

+INPUT

INPUT

STAGE
I

6.3V

P9

.

----- ...." ----

v-

Cc=~~~F0

v'
D

-INPUT

TABLE OF JUMPERS

ICl-7611
ICL·7612
ICL·7613
ICL-7614
ICL-7615

ICl·7621
ICl-7622
ICL·7631

lel·76l2
ICL·7641
ICL·7642

B, F, H
B,
S,
C,
C,
C,

F, H
F, H
0, E
D, E
E

C, E
B, F, H
B, F, H
C, G
A, E

o'--Hl~--0

2

2'" "'0
",2
2",
WW ~c..

'"

c..

ICL76XX

M

N

::;;
I

0

u

0

Q~ >o~
...Jw Wu ...Jw
u
...JI- I-w ...JI-w
 Xo=>
w8 uc.. wu~
2

'"

>
::;;

u

MINI PLASTIC CERAMIC
DIP(1!
DIP DIP(1]

U

U

U

0",

°0
,...
+

N

'b
,...

+

+

+

0

S

S

S

S

w
IX
w

U

U

U

U

U

0

w

2

°0

'1n

'"

'b

'b
,...

°0

U

'b
,...
+

S
ou
0

u
0",

N

:;S

Y

'"'"

DIE

u
'b
,...
+

S
u
'b

0 P

~

Vos SELECTION
A=2mV
B=5mV
C = 10mV
0= 15mV
E = 20mV

SINGLE

DUAL

DUAL
747 PINOUT

TEMP. RANGE
C = O°C TO 70°C
M = _55°C TO +125°C

':t

~

High IQ
QUAD
LowlQ

7612 ACTV AM TV ACPA
BCTV BMTV BCPA
VJ DCTV - - DCPA

DCID

ACT V AM TV ACPA
BCTV BMTV BCPA
DCTV
DCPA

--

DCID

7622

ACPD
BCPD
DePD

ACJD AMJD
BCJD BMJD
DCJD - - DCID

(31
7631 7632

BCPE
CCPE
ECPE

BCJE BMJE
CCJE CMJE
ECJE - - ECID

BCPD
CCPD
ECPD

BCJD BMJD
CCJD CMJD
ECPD - - ECID

BCPD
CCPD
ECPD

BCJD BCJD
CCJD CCJD
ECJD - - EC/D

rr

Nip Nip
QUAD

PACKAGE CODE
TV - TO·99, 8 PIN
PA - PLASTIC 8 PIN MINIDIP
PO - 14 PIN PLASTIC
PE - 16 PIN PLASTIC
JD - 14 PIN CERDIP
JE - 16 PIN CERDIP

7615

VIP VIM VIP
7621

1458 PINOUT

TRifLE

7611 7614 7613

7641

PF
PfL
7642

NOTES: 1. Dual~ and quads are available in 14 pin DIP packages, triples in 16 pin only.

2. Ordering code must consist of basic device and order suffix, e.g., ICL7611BCPA.
3. ICL7632 is not compensatable. Recommended for use in high gain circuits only.

5·141

u
'1n

~
+

S
U
0",

'"

ICL761X/762X/763X/764X
PIN CONFIGURATIONS
DEVICE
ICL7611XCPA
ICL7611XCTV
ICL7611XMTV
ICL7612XCPA
ICL7612XCTV
ICL7,612XMTV
ICL7613XCPA
ICL7613XCTV
ICL7613XMTV

DESCRIPTION
I nternal compensation, pl"s
offset null capability
'and external 10 control_

PIN ASSIGNMENTS
TO-99 (TOP V lEW)
(outline dwg TO-99)

8 PIN DIP (TOP VIEW)
(outline dwg PAl

IQ SET

OFFSET

I Q SET

-IN

OUT

+IN

OFI',SET

v*Pin 7 connected to case_

ICL7614XCPA
ICL7614XCTV
ICL7614XMTV
ICL7615XCPA
ICL7615XCTV
ICL7615XMTV

,Fixed 10 (100I'A), external
compensation, and offset
null capability_

TO~99 (TOP VIEW)
(outline dwg TO-99)

8 PIN DIP (TOP VIEW)
(outline dwg PAl

COMP
COMP

OfFSET
-IN

v+

+IN

OUT

v-

OFFSET

v* Pin 7 connected to case.

ICL7621XCPA
ICL7621XCTV
ICL7621XMTV

Dual op amps with Internal
compensation; 10 fixed
at 100l'A
'

TO-99 (TOP VIEW)
(outline dwg TO-99)

8 PIN DIP'I"TOP VIEW)
(outline dwg PAl

v+

v+ OUT. ,-IN. +IN.

Pin compatible with
Texas I nst_ TL082
Motorola MC1458
Raytheon RC4558

OUT. -IN., +IN.v-

v* Pin 8 Connected tei case.
ICL7622XCPD

Dual op amps with Internai
compensation and offset
null capability; 10 fixed
at 100,.A

14 P.IN 'DIP (TOP VIEW,)
(outline dwgs JD, PO)
OFFSET. v+ OUT.

Pin compatible with
Texas Inst_ TL083
Fairchild ,.A'J47

N/C

OUT.

14

Note: Pins 9 and 13 are internally conneCted_

5-142

v+ OFFSET.

ICL761X/762X/763X/764X
PIN CONFIGURATIONS (Cont.)
DEVICE
ICL7631XCPE
ICL7632XCPE

DESCRIPTION

PIN ASSIGNMENTS
16 PIN DIP (TOP VIEW)
(outline dwgs JE, PE) ,

Triple op amps with internal
. compensation (lCL7631) and
no compensation (lCL76321.

lOA

SET

Adjustable I Q

Ice

v+

OUT...

+INa

-INa

-IN"

+IN A

OUTa

V+

SET

16

Same pin configuration as
ICL8023.

•
NC

lac

-INc

+IN c

SET

Note: Pins 5 and 15 are internally connected.

ICL7641XCPD
ICL7642XCPD

14 PIN DIP (TOP VI EW)
(outline dwg JD, PD)

Quad op amps with internal

comp,ensation.
QUTo

IQ fixed at 1inA (lCL7641)
I Q fixed at 10IlA (lCL 7642)

-INo

+INo

v-

+INc

-INc

OUTe

-iNA

+IN"

V+

+IN a

-INa

OUTa

14

Pin compatible with
Texas I nstr. TL084
National LM324
Harris HA4741

"
OUTA

GENERAL INFORMATION
STATIC PROTECTION
All devices are static protected by the use of input
diodes. However, stro(1g static fields should be
avoided, as it is possible for the strong fields to cause
degraded diode junction characteristics, which may
result in increased input leakage currents.
LATCHUP AVOIDANCE
Junction-isolated CMOS circuits employ configurations which produce a parasitic 4-layer (p-n-p-n)
structure. The 4-layer structure has characteristics
similar to an SCR, and under certain circumstances
may be triggered into a low impedance state resulting
in excessive supply current. To avoid this condition, no
voltage greater than 0.3\,1 beyond the supply rails may
be applied to any pin. (An exception to this rule
concerns the inputs of the ICL7613 and ICL7615,
which are.protected to ±200V.) In general, the op amp
supplies must be established simultaneously with, or
before any input signals are applied. If this is not
possible, the drive circuits must limit input current flow
to 2 mA to prevent latchup.
.
CHOOSING THE PROPER 10
Each device in the ICL76XX family has a similar 10
set-up scheme, which allows the amplifier to be set to
nominal quiescent currents of 10 !LA, 100 !LA or 1 mA.
5·143

These current settings change only very slightly over
the entire supply voltage range. The ICL7611/12/13
and ICL7631/32 have.an external 10 control terminal,
permitting user selection of each ampfifiers' quiescent
current. (The ICL7614/15, 7621/22, and 7641142 have
fixed 10 settings - refer to selector guide for details.)
To set the ra of programmable versions, connect the 10
terminal as follows:
10 = 10!LA - 10 pin to V+
10 = 100!LA -10 pin to ground. If this is not possible,
any voltage from V+ -0.8 to V- +0.8 can be used.
10 = 1mA - 10 pin to V-

NOTE: The negative output current available is a function of the quiescent current setting. For maximum p-p
output voltage swings into low impedance loads, 10 of
1 mA should be selected.
•
OUTPUT STAGE AND LOAD
DRIVING CONSIElERATIONS
Each amplifiers' quiescent current flows primarily in
the output stage. This is approximately 70% of the 10
settings. This allows output swings ·to almost the
supply rails for output loads of 1M, 100K, .and 10K,
using the output stage in a highly linear class A mode,
In this mode, crossover distortion is avoided and the
voltage gain is maximized, However, the output stage
can also be operated in Class AB, which can supply

ICL761X/762X/763X/764X
higher output currents. (See graphs, under Typical
Operating Characteristics). During the transition from
Class A to Class B operation, the output transfer
characteristic .is non-linear and the voltag'e gain
decreases,

A spedial feature of the output stage' is' that it
approximates a transconductance amplifier,and its
gain is directly proportional to load impedance.
Approximately the same open loop gains are obtained
at ea~h of thela settings if corresponding loads of 10K,
100K, and 1M are used.
INPUT OFFSET NULLING
For those models provided with OFFSET :NUlLiNG
pins, nulling may be achieved by connecting a 25K pot
between the OFFSET terminals with the wiper
connected to V+. At quiescent currents of 1 mA and
tOO p.A, the nulling range provided is adequate for all
, Ves selections; however with la = 10p.A, nulling may
not be possible with higher values of Vas.

,

5

FREQUENCY COMPENSATION,'
The ICl7611/12/13, 7621/22, 7631, 7641/42 are
internally compensated, and are stable for closed loop
gains as low as unity for capacitive loads LIP to 100pF.
The ICl7614 and 15 are externally compensated by
connecting a capacitor between the COMP and OUT
pins. A 39pF capacitor is required for unity gain compensation; for greater than unity gain applications,
increased bandwidth and slew rate can be obtained by
reducing the value, of the compensating capacitor. ,
Since the gm of the first stage'is proportional to.ffQ,
greatest compensation is required when 10 = 1 mA. The
ICl7632 is not compensated internally, nor'can it be
. compensated externally. The device is stable when
used as follows:
.
10 of 1 mA for gains;::: 20
10 of 100 p.A for gains;::: 10

la of 10 p.A for gains;::: 5

HIGH VOLTAGE INPUT PROTECTION
The ICl7613 and 7615 include on-chip thin film
resistors and clamping diodes which allow voltages of
up to ±200 to be applied to either input for an indefinite
time without device failure. These devices will be
useful where high common mode voltages, differential '
mode voltages, or high transients may be experienced,
Such conditions may be found when interfacing
separate systems with separate supplies. Unity gain
stability is somewhat degraded with capacitive loads
because of the high value of input resistors.
EXTENDED COMMON MODE INPUT RANGE
The ICL7612 incorporates additional processing
which allows the input CMVR to exceed each power
supply,rail by 0.1 volt for applications where Vsupp;:::
±1.5V. For those applications where VSUpp:S; ±1.5V,
the input CMVR isJimited in the positive direction, but
may exceed'the n'egative supply rail by 0.1 volt in the
negative direction (e.g., for VSUPP = ±0.5V, the input
CMVR would be +0.1 vO,lts to -0.6 volts).
OPERATION AT Vsupp

= ±0.5 VOLTS

. Operation at Vsupp = ±0.5V is guaranteed at 10 = 10p.A
only. This applies to these devices with selectable la,
'and those devices are set internally to 10 = 10p.A (I.e.,
ICl7611, 7612, 7613, 7631, 7632, 7642).
Output swings tq within a few millivolts of the supply
rails are achievable for RL;::: 1 Megn. Guaranteed input
CMVR'is ±0.1V minimum and typically+O.4V to -0:2 at
Vsupp = ±0.5V. For applications where greater
common mode range is desirable, refer to description,
of ICl7612 above.
'
The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout,
construction, board cleanliness, and supply filtering to
,avoid hum and noise pickup.

ABSOLUTE MAXIMUM RATINGSl11
Total Supply Voltage iJ+ to v- ......... : ...... :... 18V
Input Voltage .............. : ....... 'V++0.3 to v- -0.3V
Input Voltage ICL7613/15 Only .... V++200 to v- -200V
Differential Input Voltage l21 :..
±/iV+ +0.31 - (V- -0.3)]V
Differential'lnput Voltage l21
'
ICL7613/15 Only .. :'...... ± /iV++2001 - (V- - 200)jV
Duration of Output Short Circuitl 31 ••• • • • • • • •• Unlimited
Continuous Power Dissipation @ 25°C
Above 25°,C
derate as follows:
2~W/oC
TO-99
250mW
2mW/oC
8 Lead Minidip
250mW
3mW/oC
14 Lead Plastic
375mW
500mW
4mW/"C
14 Lead Cerdip
16 Lead Plastic
375mW 3mWI"C
4mW/o,C
16 Lead Cerdip
500mW
Storage Temperature Range, ......... . "55°C to +150°C

Operating Temperature Range
MSeries ....... : ................... -55°C to +125°C
C,Series ................•........... ~. O°C to +70°C
L~ad Temperature (Solderin~, 10 sec)' ....•. : .... 300°C
Notes:
1, Stresses above those listed under Absolute Maximum

Ratings may cause permanent damage to the device. rhese
are stress ratings only, and functional operation ofthe device
at these or any other conditions above those indicated in
the operational sections' of the specifications is not implied.
Exposure to absolute maximum rating conditions' for
extended periods may ~ffect device reliabilitY.
2. Long term offsetvoltage stability will be degraded if large
input differential voltages are applied for long periods of
time.
3. The outputs may be shorted to ground or to either, supply.
for Vsupp:510V. Care must be taken to insure that the dissipation rating is not exceeded.
'

5·144
,

.

ICL761X/762X
ELECTRICAL CHARACTERISTICS

Vsupp = ±5.0V, TA = 25°C, unless otherwise specified
76XXA

PARAMETER

SYMBOL

Input Offset Voltage

Vos

Temperature Coefficient of Vos

t,vos/t1T

Input Offset Current

los

Input Bias Current

IBiAS

Common Mode Voltage Range
(Except ICL7612)

VCMR

Extended Common Mode Voltage
Range (ICL7612 Only)

VCMR

CONDITIONS
Rs~100K!l, TA=25°C
TMIN~TA~TMAX

10

TA=25°C
t1TA=CI 21
t1TA=MI21.

0.5

TA=25°C
t1TA=C
t1TA=M

1.0

Large Signal Voltage Gain

AYOL

Unity Gain Bandwidth

Gew

Input Resistance

RIN

Common Mode Rejection Ratio

CMRR

15
20

15
30
300
800

0.5

50
400
4000

1.0 .

p.V/oC

25
30
300
800

0.5

50
400
4000

1.0

mV

30
300
800

pA

50
400
4000

pA

±4.4
±4.2
±3.7

±4.4
±4.2
±3.7

V

10=10uA

+5.3
+5.3
-5.1
+5.3
-4.5

+5.3
+5.3
-5.1
+5.3
-4.5

+5.3
+5.3
-5.1
+5.3
-4.5

V

RL=100K!l, TA=25°C
t1TA=C, t1TA=M,
10=100p.A

±4.9
±4.8
±4.6

±4.9
±4.8
±4.6

±4.9
±4.8
±4.6

RL=10K!l, TA=25°C
t1TA=C, t1TA=M,
10=1 mA,
Vo=±4.0V, RL=1M!l
10=10p.AI1J, TA=25°C
t1TA=C
t1TA=M

±4.5
±4.3
+4.0

±4.5
±4.3
+4.0

±4.5
±4.3
+4.0

V

86
80
74

104

80
75
68

104

80
75
68

104

Vo=±4.0V, RL =100k!l
10=100p.A, TA=25°C
t1TA=C
t1TA=M

86
80
74

102

80
75'
68

102

80
75
68

102

Vo=±4.0V, RL=10k!l
10=1mAI1J, TA=25°C
t1TA=C
t1TA=M

90
85
77

98

80
75
68

98

80
75
68

98

10=10p.AI1J
10=100p.A
10=1mAI1t

0.044
0.48
1.4

0.044
0.48
1.4

1012
R~100KO. 10=10p.AI11
R~100KO,

PSRR

5
7

±4.4
±4.2
±3.7

Rs~100K!l,

Power Supply Rejection Ratio

76XXD

10=10p.AI11
10=100p.A
10=1mA111

10=1OOuA

Vour

2
3

R~100K!l

10=1mA
Output Voltage Swing

76XXB

MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

10=100p.A
10=1mA111

Rs~100KO, 10=10p.AI11
Rs~100KO,

Rs~100K!l,

10=100p.A
10=1mA111

1012

dB

0.044
0.48
1.4

MHz

1012

0

76
76
66

96
91
87

70
70
60

96
91
87

70
70
60

96
91
87

dB

80
80
70

.94
86
77

80
.80
70

94
86
77

80
80
70

94
86
77

dB

Input Referred Noise Voltage

en

. Rs=1000, f=1 KHz

100

100

100

nV!(Hz

Input Referred Noise Current

in

Rs=1000, f=1 KHz

0.Q1

0.Q1

0.Q1

pAYHz'

Supply Current
(Per Amplifier)

Isupp

No Signal, No Load
10=10p.AI1)
10=100p.A
10=1mA[11

0.01
0.1
1.0

Channel Separation

V01/V02

Slew Rate [31

SR

Rise Time 13[

Overshoot Factor [3[

Note: 1. ICL7611, 7612, 7613 only.

tr

0.02
0.25
2.5

0.Q1
0.1
1.0

0.02
0.25
2.5

0.01
0.1
1.0

0.02
0.25
2.5

'mA

AYOL=100

120

120

120

dB

AYOL=1, CL=100pF,
. VIN = 8Vp- p
10=10p.A[11, RL=1M!l
10=100p.A, RL=100K!l
10=1mAI1I, RL=10KO

0.016
0.16
1.6

0.016
0.16
1.6

0.016
0.16
1.6

V/p.s

VIN-50mV, CL-100pF
10=10p.AI11, RL=1M!l
10=100p.A. RL=100K!l
'lo=1mAI 11, RL=10KO

20
2
0.9

20
2
0.9

20

P.s

0.9

VIN=50mV, CL=100pF
10=10p.AI1I, RL=1MO
10=100p.A, RL=100K!l
10=1mA[1[, RL=10K!l

5
10
40

5
10
40

5
10
40

2. C = Commercial Temperature Range: 0° C to +70° C
M = Military Temperature Range: _55° C to +125° C

5·145

2

%

3. ICL7614/15;39pF from pin 6 to pin 8.

ICL761 X/762X
ELECTRiCAL CHARACTERISTICS Vsupp = ±O.5V, 10 = 10",A,

TA = 25°C, unless otherwise specified.
Specs apply' t6 ICL7611!7612!7613 only.

.

76XXA
PARAMETER

SYMBOL

Input Offset Voltage

Vos

CONDITIONS

MIN.

TYP.

Rs~100KO,TA~25°C

AVos/AT

Input Offset Current

los

'.
Input Bias Current

IBIAS

"

MIN

TYP.'

2
3

TMINgA~TMAx

Temperature Coefficient of Vos

76XXB
MAX.

Rs~100KO

10

TA=25°C
ATA=C
ATA=M

0.5

TA=25°C
ATA=C
ATA=M

1.0

MAX

'UNITS

5
7

mV
fJV/o C

15
30
300
600

0.5

50
500
4000

1.0

30
300
800

pA

50
500
4000

pA

Common Mode Voltage Range
(Except ICL7612)

VCMR

±0.1

±0.1

V

Extended Common Mode Voltage
Range (ICL76120nly)

VCMR

+0.1.
to
-0.6

+0.1
to
-0.6

V

Output Voltage Swing

Your

Large'Slgnal Voltage Gain

AVOL

RL=1MO, TA=25°C
ATA=C
ATA=M

±0.49
±0.48
±0.41

±0.49
±0.46
±0.41

V

Vo=±O.1V, RL=1MO
TA=25°C
ATA=C,
IlTA=M

90
80
70

90
60
70

dB
MHz

Unity Gain Bandwidth

GBW

0.044

0.044

Input Resistance

RIN

1012

1012

0

Common Mode Rejection Ratio

CMRR

80

60

dB

Power Supply ReJection. Ratio

PSRR

Input Referred Noise Voltage

en

RS5100KO
Rs~100KO

80

80

dB

Rs=1000. f=1 KHz

100

100

nV1Hz'

Input Referred Noise Current

in

Rs-1000, f-1KHz

0.01

Supply Current
(Per Amplifier)

Isupp

No Signal. No Load

6

Slew Rate

SR

AVOL=1. CL=100pF.
VIN=0.2Vp-p
RL=1MO

0.016

0.Q16

V/fJS

Rise Time

tr

VIN=50mV. CL=100pF
RL=1MO

20

20

fJS

VIN=50mV, CL=100pF
RL=1MO

5

5

%

Overshoot Factor

0.Q1
15

6

Note: C = Commercial Temperature Range(O°C to +70° C); M = Military Temperature Flange (-55°C to +125°C).

5-146

pA1Hz'
15

fJA

763X/764X
ELECTRICAL CHARACTERISTICS

.

Vsupp= +5
- OV TA =25°C unless otherwise specified

SYMBOL

Input Offset Voltage

Vos.

Temperature Coefficient of Vos

AVos/AT

Input Offset Current

los

Input Bias Current

Common Mode Voltage Range

Output Voltage Swing

Large Signal Voltage Gain

ISlAS

VeMA

VOUT

AVOL

Unity Gain Bandwidth.

Gsw

Input Resistance

RIN

Common Mode Rejection Ratio

CMRR

Power Supply Rejection Ratio

PSRR

CONDITIONS

MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

RsS100KO, TA=25°C
TMINSTASTMAX

10
15

5
7

Rs"'100KO

15

TA=25°C
ATA=C
ATA=M

0.5

TA=25°C
ATA=C
ATA=M

1.0

lo=10p.Alll
la=100p.A I31
la=lmAl21

76XXE

76XXC

76XXB
PARAMETER

20
25

20
30
300
800

0.5

50
500
4000

1.0

30
30
300
800

0.5

50
500
4000

1.0

±4.4
±4.2
±3.7

±4.4
±4.2
±3.7

±4.4
±4.2
±3.7

RL=100KO, TA=25°C
ATA=C, ATA=M,
lo=100p.A

±4.9
±4.8
±4.5

±4.9
±4.8
±4.5

±4.9
±4.8
±4.5

RL=10KO, TA=25°C
ATA=C, ATA=M,
lo=lmA

±4.5
±4.3
±4.0

±4.5
±4.3
+4.0

±4.5
±4.3
+4.0

Vo=±4.0V, RL=lMOPI
la=10p.AI 1 I, TA=25°C
ATA=C
ATA=M
VO=±4.0V, RL=100k0131
la=100p.A, TA=25°C
ATA=OC
ATA=M
Vo=±4.0V, RL=10k0 121
la=1mAlll, TA=25°C
ATA=C
ATA=M

80
75
68

104

80
75
68

104

86
80
74

102

80
75
68

102

80
75
68

102

86
80
74

98

80
75
68

98

80
75
68

98

0.044
0.48
1.4

1012
Rs"'100KO, la=10p.AI11
RsSl00KO, la=100!'A
RsSl00KO,la=lmAI 2 1
RsSl00KO,la=10!,AI 11
RsSl00KO, la=100!,A
RsSl00KO, la=lmAl21

1012

pA

50
500
4000

pA

V

104

0.044
0.48
1.4

p.VfOC
30
300
800

V

86
80
74

la=10p.AI11
la=100p.AI3 1
la=lmAl21

mV

dB

0.044
0,48
1.4

MHz

1012

0

76
76
66

96
91
87

70
70
60

96
91
87

70
70
60

96
91
87

dB

80
80
70

94
86

80
80
70

94
86

80
80
70

94
86
77

dB

77

77

Input Referred Noise Voltage

en

Rs=1000, f=l KHz

100

100

100

nV!fHz.

Input Referred Noise Current

in

Rs=1000, f=lKHz

0.01

0.01

0.D1

pA!fHz

Supply Current
I Per Amplifier}

Isupp

No Signal, No Load
la=10!,AI11
la=100p.A
la=lmAl21

0.D1
0.1
1.0

0.01 0.022
0.1 0.25
1.0
2.5

0.01 0.022
0.1 0.25
1.0
2.5

mA

Channel Separation

V01IVo2

Slew Rate l41

SR

Rise Time l41

Overshoot Factor 14Y

tr

0.022
0.25
2.5

AVOL=100

120

120

120

dB

AVOL=l, CL=100pF,
VIN =8Vp-p
la=10p.AI1I, RL=lMO
la=100p.A, RL=100KO
la=lmAlll, RL=10KOI 21

0.Q16
0.16
1,6

0.Q16
0,16
1.6

0.016
0.16
1.6

V/!'s

VIN=50mV, CL=100PI"
la=10p.Alll, RL=lMO
la=100!,A. RL=100KO
la=lmAI21, RL=10Kfl

20
2
0.9

20
2
0,9

20
2
0,9

!,s

VIN=50mV, CL=100pF
la=10!,AI 11, RL=lMfl
la=100!,A, RL=100Kfl
la=lmAI21, RL=10Kfl

5
10
40

5
10
40

5
10
40

Note: 1. Does not apply to 7641,
2. Does not apply to 7642,
C = Commercial Temperature Range:O°C to +70°C
M = Military Temperature Range: -55°C to +125°C
3. ICL7631/32 only.
4. Does not apply to 7632,

5·147

%

763X/764X
ELECTRICAL CHARACTERISTICS

Vsupp = ±O.5V, IQ = 10j.!-

--; ~ ~ la=10"A

/

100

AL'" lQOKn

10' 100"A _

-

0

"

105

~~

10

ffi

1

~

VOUT ;:: 8 VOLTS

1
-75

-50

-25

0

+25

I

+50

102

=
-

100
I
0

10

",I, rnA

95

"cc
'"

90

0

;:

~

cc
w

"

"

~

0

85

~10

80

=

--

"""

75

..........

>
>

&
"

-

r-

........

........

70

-50

-25

o

+25 +50

lOll

r-95

;:

~

r - __ _
- -100lmA

90

cc
w 85
c

90'

:E

135'

:E
:E
0
u

~

..........
..........

0

~

",

'\~

10K

lOOK

z 80

I

w

1M

75
70

-75

-50

~
~

-25

'"az

14

,

12

~
~

200

......

+75 +100 +125

FREE·AIR TEMPERATURE -'C

'w~"

vs~P;;= "

~

f-,5V

>

a
w

..,

\

\
~

100
0
10

100

I

i""

r-_

1K

FREQUENCY - Hz

5·149

10K

.
o

100

TA = +2S"C

I

1
lK

•

I"~....
10K

:

1\

1-2"~ t-=-........

vsupp :;; t2V

~
lOOK

°c

---'a =10pA
\
, .... " 10 =100pA
,, '\

l,\

I-

i'-

+75 +100 +125

-'a=lmA

I- t8V

1\

\

+50

"\

\

.<::Vsupp

10
300

+25

PEAK-TO-PEAK OUTPUT VOLTAGE
AS A FUNCTION OF FREQUENCY

400

I-

0

FREE·AIR TEMPERATURE _

16

,

r-....

0

TA '" +25~C
3V ... Vsupp ..;,; 16V

500 1\

rNA

r--~~=10~ ..........

0

45'

180~

lK

+125

Vsupp '" 10V

I 100

0'

I
10

+100

105

rnA

'\ ~'\

+75

!ll

33pF FOR

"ccz

I'\. ~

.... 50

COMMON MODE REJECTION
RATIO AS A FUNCTION
OF FREE-AIR TEMPERATURE

w

V)

65
-75

=:

EQUIVALENT INPUT NOISE VOLTAGE
AS A FUNCTION OF FREQUENCY

o
>

I"- r---...

1O"A

=+25°C

10"'"

+25

FREE.AIR TEMPERATURE _oC

TA

lo::r 10~A'

1
0.1

~ 600

-

-25

FREQUENCY - Hz

Vsupp '" lOV

r- r-

;:

0.1
-50

+100 +125

;:

.1I0ilmAII

'c

POWER SUPPLY REJECTION
RATIO AS A FUNCTION OF
FREE-AIR TEMPERATURE

!ll

./

0

10

+75 +100 +125

FREE·AIR TEMPERATURE -

/

1.0

°c

Cc

10~"A

PHASE SHIFT ' ....

1

+75

ICL7614/15

'\. ~
""'~,, ~

103

VSUpp "" 10 VOL TS

0

10 =
~......,

10'

I

-'

;:

-

RL = 10K>!
'0'" lrnA

>

+50

v,ur = 16~

100

I

~

:;:;

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AND PHASE SHIFT
AS A FUNCTION OF FREQUENCY

1

~

"w
"~"

+25

L

I-

F.REE-AIR TEMPERATURE _

1000

>

-

-25

10

"'"iD

~

1
-50

16

"u

r-- I--

10

V)

/

ffi

-lo,,'0pA

"

100

cc
cc

1

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AS-A FUNCTION
OF FREE-AIR TEMPERATURE

'"

0-

I-

102

SUPPL Y VOLTAGE - VOL TS

;;

"I

I
-10'" 100/-IA

"u>

v' 0
V- "-5VOLTS

f--

I-

w
cc
cc

~5 VO~TS

~

v1-v- '= lOvbLTS
NO LOAD
-NO SIGNAL

-

-lo=lmA

Z

..,.o

1000

I

1

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE

'\

~\

•....... ~

lOOK

FREQUENCY - Hz

"-

1M

10M

O~OIb

ICL761X/762X/763X/764X
TYPICAL'PERFORMANCE CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE AS A
FUNCTION OF FREQUENCY
>

.16

'"

~>

14

1=

10

I
w

~

-I

12

""\ t\'

;:\

\ l'\

'"

~"

TA - -!We

i\r\

"

10K

11

12

~

10

121---4---+--~--1-

o
>
~

I
w

"

1M

10M

0

V

/

v

V

V

0.0 1

ffi

D. 1

"

"in'"

I'..

:::>

~

o

1.0

14

o

SUPPLY VOLTAGE - VOLTS

8
Vsupp'" lOV

>
I

Rl
Cl

'" lOKS!

TA

'" +25 C

>

'"'~"
0

1\

/

I-

:::>

1=

"'"

I-

~

-2
INPUT

-4

:::>

1=
:::>

10

"'"

/OUTPUT

.~

. INPUT
-4

-6

20

40

60

TIME-ps

5·150

80

10

100

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE
Vsupp - lOV
RL = lMn
Cl = 100pF

10 - 10pA

>
w

:::>

/OUTPUT

1=
:::>
Cl
Cl

r\

\

INPUT

-2

I-

"

100

~

~

120

-4
-6

200

= +2S"C

'\

/

0

>

I-

"«

TA

I

~-'

\

-2

~

12

1.0

I

\\

0

I-

I-

LOAD RESISTANCE - Kn

.- 100pF
'" +25~C

~

-6

16

= 100KQ

Rl

0

~

14

Vsupp '" ,1OV

I

>

-~

:::>'

.0
Cl

I~ = 106"A

~A'

I-

\

!oUTPUT

12

c..

.0

l-

/

=

- VOLTS

w

'~"

w

>

VOL~AGE

I

'" 100pF

=25°C

1/

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE
10" 1 rnA

v~ -V-,. 10 VOLTS

TA

V

10

SUPPLY

°c

10 "'lmA

10 -lmA.::

10

16

+50 +75 +100 +125

16

-

.....
"-

~

+25

MAXIMUM PEAK-TO-PEAK OUTPUT
VOL -rAGE AS A FUNCTION OF
LOAD RESISTANCE

10 -100J,lA

""

o

-25

!zw
:::>
u

12

-50

FREE.AIR TEMPERATURE _

10 "'lOIlA

I-

10

-75

.~'

~

'E"I

:::>

0

~

IQ'" lmA

o

"

MAXIMUM OUTPUT
SINK CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

40

~
0

r-.....

Vsupp '" 10 VOLTS

:::>

~"

MAXIMUM OUTPUT/SOURCE
CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

,/

.........

RL" 2Kn

'"

SUPPLY VOLTAGE - VOLTS

/

=10Kn

~

FREQUENCY.:.... Hz

0

1

RL

~

1\

lOOK

V

r-.....

o

t'-..:: t--...

0

Rl = lOOKn

-

1=
:::>

1--1---\---+

10

TA = +25~C

TA = +125,,,...-'11\

o

>

'"
;:\

:::>

"

16

I--

'0 clmA

5

~

= lOV

Vsupp

MAXIMUM PEAK-TO-PEAK
VOLTAGE AS A FUNCTION OF
. FREE-AIR TEMPERATURE

MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGE

400

600

TIME-,us

800

I\.

1000 1200

D~DIl

ICL761 X/762X
APPLICATIONS
Note that in no case is la shown. The value of la must
be chosen by the designer with regard to frequency
· response and power dissipation.

PRECISE TRIANGLE/SQUARE WAVE GENERATOR
Since the output range swings exactly from rail to rail,
frequency and duty cycle are virtually independent of
power supply variations.

SIMPLE FOLLOWER*

..fLfl..'
V,~-----I"""

>-----..--_----

1M

VOUT

RL" 10k
OUTYCYCLE
680kll
WAVEFORM GENERATOR

AVERAGING AC TO DC CONVERTER FOR A/D
CONVERTERS SUCH AS ICL7106, 7107,7109, 7116,
7117.
LEVEL DETECTOR"

1M

"By using the ICL7612 in these applications,. the cir· cuits will follow rail to rail inputs.

.05.F 10k

20k

2.2M

>-l MI'........,----'\IV'v----,

TO
SUCCEEDINq
INPUT
STAGE

V'N
+5

V'N

+5

>---+-----1
l00k~-?--I

' - - - + 1 - VOL

>---....---- VOUT
TO CMOS OR
LPTTL LOGIC

COMMON

1M

PHOTOCURRENTINTEGRATOR
· Low leakage currents allow. integration times up to
several hours.

MEDICAL INSTRUMENT PREAMp
Note that AVOL = 25; single Ni-cad battery operation.
Input current (from sensors connected to patient)
limited to < Sp.A ufJder fault conditions.
·IM
lOOk. 1%

I.F
+

500k.1%

lOOk

INPUT

VOUT

50k

VOUT

1M. 1%

1\
V+

-=

lOOk
lOOk. 1%
IM

5·151

1M. 1%
V-

II

ICL761X/762X/763X/764X
FIFTH ORDER CHEBYSHEV MULTIPLE FEEDBACK LOW PASS FILTER
The low bias currents perm'it high resistance and low
capacitance vaiues to be used to achieve low
frequency cutoff, fc = 10Hz. AVOL = 4. Passband ripple
= 0.1 dB.
.
O.2pF
O.2pF

•

I~
30k

. 1601<
.~

1
r--

~

O.2pF

680k

·look

1

51k

-

360k

INPUT

i

O.lpF

I

.

O.2pF

~
1M

O.I"F

L_-I~_.J

I

360k

OUTPUT

I

L_-I~_.J

1M

"Note that small capacitors (25-50pF) may be needed for stability in some cases.

III
111:1

SECOND ORDER BIQUAD BANDPASS FILTER
Note that 10 on each amplifier may be different.
AVOL= 10. Q = '00. f 0 = 100Hz.
.

Vos NULL CIRCUIT

O.I"F

16k

16k

>-----IIOUT

V,N

O.I"F
1.6M

160k

1601<

>,---+-VOUT

BURN-IN AND LIFE TEST CIRCUIT

-

. UNITY GAIN FREQUENCY COMPENSATION

"

+8V

>---t-_--.--VOUT

1.5k
V,N>----I

"I_ l00pF

..". RL = lOOk
10k FOR
FOR1010• =lrnA
l00,.A
1M FOR 10 • lo,.A

-FOR ICL7614/15
NOTES:
1. FOR DEVICES WITH EXTERNAL COMPENSATION.
USE 33pF.
2. FOR DEVICES WITH PROGRAMMABLE STANDBY
CURRENT. CONNECT la PIN TO V- (10 trnA .
MODE).

=

5·152

ICL761X/762X/763X/764X
CHIP TOPOGRAPHY

BIAS/CaMP

OFFSET

-INPUT

761X -

.076 IN.
(1.93 MM)
OUT.

V+

"I

---r

OFFSET.

OFFSET,

.077 IN.
(1.95 MM)

-IN.

OFFSET.

OFFSET.

762X

5-153

ICL761 X/762X/763X1764X
CHIP TOPOGRAPHY (Cont.)

1-4------- (2.13
.OS4IN. --------t.....1
MM)

+IN.

OUT.

-IN •

.079 IN.
(2.00 MM)

lac SET
la. SET

OUTc
-INc +INc

v~

763X
.OSO IN.
MM} - - - - - - - i - . J

Jo+-~----(2.03

-INc OUTc OUT. -IN.,
'+INc

+IN •.

.OS6IN.
(2.1SMM)

. v-

-IND

764X

5-154

ICL7650
CHOPPER STABILIZED·
OPERATIONAL AMPLIFIER
FEATURES

The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages
in a nulling amplifier that sp~nds alternate c.lock
phases nulling itself and the main amplifier. Two external capacitors are required to store the correcting
potentials on the two amplifier nulling inputs. These
are the only external components necessary.
The clock oscillator and all of the other control circuitry is entirely self-contained. However, the 14-pin
version includes a provision for the use. of an external
clock if required for a particular application. In addition, the ICL7650 is internally compensated for unity
gain operation.
.

• Extremely low input offset voltage - 1 p. V over
temperature range
• Low long term and temperature drift of input
offset voltage
.
• Low D.C. input bias current -10pA
• Extremely high gain, CMRR and PSRR min 120dB
• High slew rate - 2.5V/p.S
• Wide bandwidth - 2MHz GBW product
• Internally compensated for unity gain operation
• Very low intermodulation effects (phase shift
<10°)
• Clamp circuit to avoid overload recovery .
problems, allow comparator use
• Extremely low chopping spikes at input and
output

ORDERING If:.IFORMATIPN

GENERAL DESCRIPTION
The ICL7650 'chopper stabilized amplifi~r is a high performance device designed to be used in a wide variety
of applications. This amplifier offers exceptionally low
offset voltage and input bias parameters combined
with excellent bandwidth and speed characteristics.
Intersil's unique approach to chopper stabilized amplifier design, using Intersil's well established CMOS
process', yields a versatile precision component which
can replace more expensive hybrid or modular parts,
while out-performing them and other monolithic
devices~

TEMP RANGE

PACKAGE

ORDER #

O°C to 70°C'

14pin plastic

ICL7650CPD

-20°C to B5°C

14pin CERDIP

ICL76501JD

O°C to 70°C

Bpin TO-99

ICL7650CTY

- 20°C to B5°C .

. Bpin TO-99

ICL76501TY

-55°C to 125°C

14pin CERDIP

-55°C to 125°C

Bpin TO-99

FIG. 1 BLOCK DIAGRAM

PIN CONFIGURATION

~
esc

.

.

INT/EXT

INT/EXT
EXT ClK IN
ClK

EXTCLK!N
NC (GUARD)

ClK OUT

ourOUTPUT·

A

INPUTS

OUTPUT CLAMP

8

>------+---------<> OUTPUT
(outline dwg JO, PO)

A

8

(outline dwg TO·99)

5-155

ICL7650
ABSOLUTE MAXIMUM RATINGS
Cont. Total Power Dissipn (TA =2S°C)
CERDIP Package ....................... 500 mW
Plastic Package ..... , .................. 375 mW
TO-99 ............................... , ... 250 mW

Total Supply Voltage (V+ to V-) ........... 18 Volts
Input Voltage .............V+ +0.3 to V- -0.3 Volts
except EXT CLOCK IN: ... V+ +0.3 to V+ -6.0 Volts
Storage Temp. Range ............. -55°C to 150°C
Operating Temp. Range ..... , ...... -20°C to 85°C
(C series ........................... O°C to + 70°C)
Lead Temperature (Soldering, 10 sec) ....... 300°C
Voltage on control pins ...............' ... V+ to VDuration of Output short ckt ............. Indefinite
Current into any pin ......................... 1OmA
-while operating ......................... 100 /LA

Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS: Test Conditions: V+ = +5V, V- = -5V, TA =25°C, Test Ckt
(unless otherwise specified)
PARAMETER
Input Offset Voltage

Average Temp. Coefficient
of Input Offset Voltage
Input Bias Current
(doubles every 10'C)

TEST CONDITIONS

Vos

T.=25'C
over operating temp.
range (note 1)

±0.7
±1.0

tNos/IlT

over operating temp.
range (note 1)

0.01

T.=25'C
O'C-+--- OUTPUT

CLOCK
The ICl7650 has an internal oscillator giving a chopping frequency of 200 Hz, available at the CLOCK OUT
pin on the 14 pin devices. Provision has also been
made for the use of an external clock'in these parts.
The INT/EXT pin has an internal pull-up and may be left
open for normal operation, but to utilize an external
clock this pin must be tied to Y- to disable the internal
clock. The external clock signal may then be applied to
the EXT. CLOCK IN pin. At low frequencies the duty
cycle of th,e extern,al clock is not critical, since an internal divide-by-two provides the desired 50% switching
duty cycle. However, since the capacitors are charged
only when EXT ClK IN is HIGH, a 50-80% positive duty
cycle is favored for frequencies above 500Hz to ensure
that any transients have time to settle before the capacitors are turned OFF. The external clock should
swing between Y+ and GROUND for power supplies up
to ±6Y, and between Y+ and Y+ - 6Y for higher supply
voltages. Note that a signal of about 400Hz will be
present at the EXT ClK IN pin with INT/EXT high or
open. This is the internal clock signal before the divider.
In those applications where a strobe signal is available,
an alternate approach to avoid capacitor misbalancing
during overload can be used. If a STROBE signal is
connected to EXT ClK IN during' the time that the
unknown signal is applied to the amplifier, neither capacitor will be charged as long as STROBE is low.
Since the leakage at the capacitor pins is quite low at
room temperature, the typical amplifier will drift less
than 10/LY/sec, and relatively long measurements can
be made with little change in offset.

DETAILED DESCRIPTION
AMPLIFIER
The block diagram shows the major elements of the
ICl7650. There are two amplifiers, the main amplifier,
and the nulling amplifier. Both have offset null capability. The main amplifier is connected full time from the
input to the output, while the nulling amplifier, under
the control of the chopping frequency oscillator and
clock circuit, alternately nulls itself and the main
amplifier. The nulling connections, which are MOSFET
back gates, are inherently high impedance, and two
external capacitors provide the required storage of the
nulling potentials, and the necessary nulling loop time
constants. The nulling arrangement operates over the
full common mode and power supply ranges, and is
also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL '
Careful balancing of the input switches, and the inherent balance of the input circuit minimizes chopper
frequency charge injection at the input terminals, and
also the feedforward-type injection into the compensation capacitor, which is the main cause of outp~t
spikes in this type of 'circuit.
Previous chopper-stabilized amplifiers have suffered
from intermodulation effects between the chopper
frequency and input signals. These arise because the
finite AC gain of the amplifier necessitates a small AC
signal at the input.This is seen by the zeroing circuit as
an error signal, and is chopped and fed back, thus
injecting sum and difference frequencies and causing
disturbances to the gain and phase vs. frequency characteristics near the chopping frequency. These effects
are substantially reduced in the ICl7650 by feeding the
nulling Circuit with a dynamic current, corresponding
to the compensation capacitor current, in such a way
as to cancel that portion of the input signal due to finite
AC gain. Since that is the major error contribution to
the ICl7650, the intermodulation and gain/phase disturbances are held to very low values, and can generally be ignored.
The null-storage capacitors should be connected to
the CEXTA and CEXTB pins, with a common connection to

BRIEF APPLICATION NOTES
COMPONENT SELECTION
The two required capaciters, CEXTA and CEXTS have optimum values depending on the clock or chopping
frequency. For the preset internal clock, the correct
value is 0.1/LF, and-to maintain the same relationship
between the chopping frequency and the nulling time
constant this value should be scaled approximately in
proportion. A high quality film type capacitor such as
mylar is preferred, although a ceramic or other lower
grade capacitor may prove suitable in many
applications.
5·157

m

ICL7650
PIN COMPATIBILITY

limitations on the replacement of other op. amps by the
ICL7650 are the supply voltage (±BV max.) and the
output drive capability (1 Ok!l load for full swing). Even
these limitations can be overcome using a simple
booster circuit, as shown in Fig. 4, to enable the full
output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of
the ICL7650.
Fig. 5 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in
using a chopper stabilized amplifier,in this application
are avoided, since the clamp circuit forces the inverting input to follow the input signal. The threshold input
must tolerate the output clamp current - VIt:~/R without
disturbing other portions of the system.
Normal logarithmic amplifiers are limited in dynamic
range in the voltage input mode by their input offset
voltage. The built-in temperature compensation and
convenience features of the ICLB04B can be expanded
to a voltage input dynamic range of close to 6 decades
by using the ICL7650 to offset-null theICLB04B, as
shown in Fig. 6. The same concept can also be used
with such devices as the HA2500 or HA2600 families of
op amps, to add very low offset voltage capability to
their very high slew rates and bandwidths. Note that
these circuits will also havetheir DC gains, CMRR, and
P8RR enhanced.
Mixing the ICL7650 with circuits operating at ±15V
supplies requires the provision of a lower voltage. Although this can be met fairly easily,a highly efficient
voltage divider can be built using the ICL7660 voltage
converter circuit 'backwards'. A suitable connection is
shown in Fig. 7.

The basic pinout of the B-pin device corresponds,
where possible to that of tHe industry standard B-pin
devices, the LM741 , LM10l, etc. The null storing external capacitors are connected to pins 1 and B, usually
used for offset null, compensation capacito.rs, or not
connected. The output clamp pin (5) is similarly used.
In the case of the OP-05 and OP-07 devices, the replacement of the offset null pot, connected between
pins land Band V+, by two capacitors from those pins
to V- will provide easy compatibility. As forthe LM10B,
replacement of the compensation capacitor between
pins 1 and B by the two capacitors to V- is all that is
necessary. The same operation, with the removal Of
. any connection to pin 5, will suffice for the LMl 01,
ILA74B, and similar parts.
The 14-pin device pinoutcorresponds most closely to
that of the LM10B device, owing to the provision of
"NC" pins for guarding between the input and all other
pins. Since this device does not use any of the extra
pins, and has no provision for offset-nulling, but requires a compensation capacitor, some changes will
be required. in layout to convert to the I.CL7650.

Ii
.

TYPICAL APPLICATIONS
Clearly the applications of the ICL7650 will mirror
those of other op. amps: Thus, anywhere that the performance of a circuit can b. e significantly improve.d by a
reduction of input offset voltage and bias current, the
ICL7650 is the logical choice. Basic non-inverting and,
inverting amplifier circuits are shown in Figs. 2 and 3.
Both circuits can use the output clamping circuit to
enhance the overload recovery·performance. The only

INPUT

>----'---1
>----1r-~OUTPUT

INPUT>----"I~---J

e>-.....-_OUTPUT

R,
R,

(R,IJR2)-1Mn
FOR FULL CLAMP EffECT'

R,

A, + IR1/IRv '" 1Mn
FOR fULL CLAMP EFFeCT

0.11-'F

FIG. 2 NON INVERTING AMPLIFIER WITH
(OPTIONAL) CLAMP
.

FIG. 3 INVERTING AMPLIFIER WITH (OPTIONAL)
CLAMP

+7.SV

v,., >-___-1

OUT

10k

FIG. 4 USING 741 TO BOOST OUTPUT DRIVE
CAPABILITY

FIG. 5 LOW OFFSET COMPARATOR

5·158

·ICL7650
STATIC PROTECTION

same temperature, thermoelectric voltages typically
around 0.1jLVrC, but up to tens of jLVrC for some
materials, will be generated. In order to realize the
extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special
precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially that caused by power-dissipating
elements in the system. Low thermo-electric coefficient connections should be used where possible and
power supply voltages and power dissipation should
be kept to a minimum. High impedance loads are
preferable, and good separation from surrounding
heat-dissipating elements is advisable.

All device pins are static protected by the use of input
diodes. However strong static fields and discharges
should be avoided, as they can cause degraded diode
junction characteristics, which may result in increased
input leakage currents.

LATCH-UP AVOIDANCE
Junction-isolated CMOS circuits inherentli include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCR. Under certain circumstances this junction may be triggered into a lowimpedance state, resulting in excessive supply current.
To avoid this condition, no voltage greater than 0.3V
beyond the supply rails should be applied to any pin. In
general, the amplifier supplies must be established
either at the same time or before any input signals are
applied. If this is not possible, the drive circuits must
limit input current flow to unqer 1rnA to avoid latchup, .
even under fault conditions.

GUARDING
Extra care must be taken in the assembly of printed
circuit boards to take full advantage of the low input
currents of the ICL7650. Boards must be thoroughly
cleaned with TCE or alcohol and blown dry with compressed aiL After cleaning, the boards should be
coated with epoxy or silicone rubber to prevent
contamination.
Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the
input pin.s are adjacent to pins.th~t .are at supply poten- ~
tials. ThiS leakage can be Significantly reduced by
using guarding to lower the voltage difference between the inputs and adjacent metal runs. Input guarding of the 8-lead TO-99 package is accomplished by
using a 10-lead pin circle, with the leads of the device
formed so that the holes adjacent to the inputs are
empty when it is inserted in the board. The guard,
which is a conductive ring surrounding the inputs, is
connected to a low impedance point that is at approx- '
imately the same voltage at the inputs. Leakage currents from high-voltage pins are then absorbed by the
guard.
The pin configuration of the dual in-line package is
designed to facilitate guarding, since the pins adjacent
to the inputs are not used (this is different from the
standard 741 and 101A pin configuration, but corresponds to that of the LM108).

OUTPUT STAGE/LOAD DRIVING
The output circuit is a high-impedance stage (approximately 18kfl), and therefore, with loads less than this
the chopper amplifier behaves in some ways like a
transconductance amplifier whose open loop gain is
proportional to load resistance. For example the open
loop gain will be 17 dB lower with a 1kfl load than with
a 10kfl load. If the amplifier is used strictly for DC, this
lower gain is of little consequence, since the DC gain is
typically greater than 120dB even with a 1kfl load.
However, for wideband applications, the best frequency response will be achieved with a load resistor
of 10k or higher. This will result in a smooth 6dBI
octave response from 0.1 Hz to 2MHz, with phase shifts
of less than 10° in the transition region where the main
amplifier takes over from the null amplifier.

THERMO-ELECTRIC EFFECTS
The ultimate limitations to ultra-high precIsion DC
amplifiers are the thermo-electric or Peltier effects
arising in thermo-couple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the

CONNECTION OF INPUT GUARDS

INP1Jl

~"'
·"""."'···''''''~'··''''''

N.
"'"'
,

~

~1.

.

AI'

.

' .

-=-' '..'UT

-;

NOTE

R~\R;2

IojUST U LOW ',,"PEO""CE

'USE TO COM'ENSATE fO~ lAr.GE ~OURCE R(SIStANCES

INVERTING AMPLIFIER

F))LLOWER

NON-INVERTING AMPLIFIER

5-159

ICL7650
TYPICAL APPLICATIONS (Contd.)

I

Ro

I

L_J,.,•.,._J

A, OUTPUT

(LOWT.C.)

10ktl

FIG.7 SPLITTING +15V WITH ICL7660.
SAME FOR -15V. >95% EFF.

FIG. 6 ICL8048 OFFSET NULLED BY ICL7650

5·160

ICL7660
Monolithic MAXCMOS®
Voltage Converter

FEATURES

GENERAL DESCRIPTION

• Simple Conversion of +5V Logic Supply to ±5V

~-~

The Intersil ICL7660 is a monolithic MAXCMOS6.5V.
Contained on chip are a series DC power supply regulator,
RC oscillator; voltage level translator, four output power
MOS switches, and a unique logic element which senses the
most negative voltage in the device and ensures that the
output N-channel switches are not forward biased. This
assures latch-up free operation.

.

• Simple Voltage Multiplication (VOUT = (-) nVIN)
• 99.9% Typical Open Circuii Voltage Conversion
Efficiency
• 98% Tvpical Power Efficiency
• Wide Operating Voltage Range 1.SV to 10.0V
• Easy to use - Requires only 2 External NonCritical Passive Components

APPLICATIONS
•
•
•
•

On Board Negative Supply for up to 64 Dynamic RAMs.
Localized wProcessor (8080 type) Negative Supplies
Inexpensive Negative Supplies
Data Acquisition Systems

PIN CONFIGURATIONS

The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0 volts.
This frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overd.riven by an external clock.
.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5 to +10.0 volts),
the LV pin is left floating to prevent device latchup.

(outline dwg

PAl ,

Typical applications for the ICL7660 will be, data acquisition
and microprocessor based systems where there is a +5 volt
supply available for the digital functions and an additional-5
volt supply is required for the analog functions. The ICL7660
is also ideally suited for providing low current, -5V body bias
supply for dynamic RAMs.

(outline dW9 TO-99)

ORDERING INFORMATION
PART NUMBER

ICL7660CTY
ICL7660CPA
ICL7660MTY
ICL7660/D

TEMP. RANGE

PACKAGE

-20° to +70°C
-20° to +70°C
-55° to +125° C

TO-99
8 PIN MINI DIP
TO-99
DICE

BLOCK DIAGRAM
r-------------~------------~r_------r_------------------_ov+

,------------------QCAP+

VOUT

OSC

LV

=

=

5-161

Ii

ICL7660

U~UIl,

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................•.•................... : ............. 10.5V
Oscillator Input ,voltage (Note 1) .. " ..... ; ....... - 5.5V
- 3.5V
\
Output Short Duration (VSUPPL Y :::;5.5V) ......•...................... Continuous
Power Dissipation (Note 2)
,
ICL7660CTY ......................................................... 500mW
ICL7660CPA . .,. .............•............... , .......•......•......... 300mW
ICL7660MTY ........ ; .•... '...•...........'. ..• ,' ...................... 500mW
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the spe,cifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
PARAMETER
SYMBOL
1+
Supply Current
V+H1
Supply Voltage Range
(Ox out of circuit)
V+L1
Supply Voltage Range
(Ox out ofcircuitl
V+H2
Supply Voltage Range
(Ox in circuit)
V+L2
Supply Voltage Range
(Ox in circuit)

v+ = 5V, TA = 25°C, Case = 0, Test Circuit Figure 1 (unless otherWise spe~ified)

- Lo

LIMITS
TYP. MAX.
170
500
3.0
6.5
3.0
5.0
1.5
3.5

- Hi

3.0

10.0

V

MIN:::;TA:::; MAX, RL = 10k!l, LV= No Connection

- Lo

1.5

3.5

V

MIN:::; TA:::; MAX, RL = 10k!l, LV = Ground

100
120
150
300

!l
!l
!l
!l

400

!l

lOUT = 20mA, TA = 25° C
lOUT = 20mA, -20°C:::; TA:::; +70°C
lOUT = 20mA, -55°C < TA < +125°C
V+ = 2V, lOUT = 3mA, LV = Ground,
-20°C:::; TA:::; +70°C
V+ = 2V, IOUT=3mA, LV=Ground,-55°C:::;TA:::;
+125°C, Ox in circuit

MIN.
- Hi

55

Output Source Resistance

ROUT

fose
PEf
VOUT Ef
Zose

Oscillator Frequency
Power Efficiency
Voltage Conversion Efficiency
Oscillator Impedance

95
97

10
98
99.9
1.0
100

UNIT
p.A
V
V
V

TEST CONDITIONS
RL -.,
O°C:::; TA:::; 70°C; RL = 10k!l, LV= No Connection
-55°C:::; TA:::; 125°C, RL = 10k!l, LV = Ground
MIN:::; TA:::; MAX, RL = 10k!l, LV = Ground

kHz
%,

RL = 5k!l
RL =,.,

%
M!l
k!l

V+ = 2 Volts
V+ = 5 Volts

Notes: '1. Connecting any terminal to voltages greater than V+ or less than GROUND may cause de'structive latchup. It is recommended that no
inputs from sources operating from external supplies be applied prior to "power up" of the ICL7660.
2.Derate linearly ab~ve SO°C by S.SmW/oC.

TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

;

-iA=;25,t
=
V'

w
~
~
o
>

1

II

0

-4

Z
0

80

~

z

0
0

..,80

Q.

//

50

'\

,/

30

20
II:
.~ 10 /
0

90
80

7f'o....

iii
II:
w 40
>

/

. ; ' . , SLOPE 550
-5
o 10 20 30,40 50 60 70
LOAD CURRENT IL(mA)

r- .......

(3
ii: 70
u.
w 60

I:

2

-3

zw

;

...
...~:;) -1-2
o

> 90
0

!

+5V

SUPPLY CURRENT & POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT
100
~100

/

50
30

20

30

= +25'C- 2~
= +5V
10

11-

40

50

LOAD CURRENT IL (rnA)

5·162

o

60,

~
o

...

"+

:;)

~

TA ~+2J,C
V+=2V

~\

\

w +1

''""
m

40 Z-i

fose ?::: 1KHz

TA
V+

""
!:C'
C

1\

+2

.,c

60 ,0

\

/

V

10

70

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

>

\
0

\

I

)

:;)

I!:

l../

0_1

-2

.....
o

~

1

i<"""""

2

~

3

"'S"rPE1150f
4

5

6

LOAD CURRENT IL (mA)

7,

8

ICL7660
SUPPLY CURRENT POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT
l100
~ 9D

r-r-....

~ 80

~

$
Z

7 o -TA=+25°C
6 0 y+ = +2.0Y

o

50

ffi

40

iii

20.0
.........

1--""

/

~

'"/bI

a:

10

a..

0

u

n

"

8.0 ~.

§:

12

a:

1\,

z~

'"0

10K

'\
y+ =+5Y

if

"1'0..

~

i'-

§: 350

iA !25ob'-

~
!i;

III

!S
o

.......

150

'" 100

5

~

~,

50

o

10

o

234567
SUPPLY YOLTAGE (y+)

T-+25°Y

I

lOUT = 1 mA

~ 96
94

'is

~Z

88

IJ

84

o

a:

~
a..

lOUT = 15mA

90

.

"-

I

w 92

,

_IY+=5Y
0° +25 0 +50 0 +75°.+100°+125°
TEMPERATURE (OC)

m0 f;7~ YW t:0

I%~ ~!'Y-\

VU

.

TA~

[~
~~

6.0
5.0
4.

86

·V~
....
Y+=+2Y

OPERATING VOLTAGE ASA
FUNCTION OF TEMPERATURE
1.0
0.0
9.0 ~

....

(3

it

--

I- ..-

-50 Q -250

POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSC. FREQUENCY
98

V

200

~

o

10K

100
1000
Case (pI)

250

iii

100

rr

2

10 YIII+
10
1.0

10~T = 1'mA

~ 300

;)

t

'"o

5Y

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

w
a:
w
u
a:

l100

y+

(3

0 +25 +50 +75 +100 +125
TEMPERATURE-(OC)

~

o

~ 100

..........

6
-50 -25

1'1

S

gj 1000

5l
5

1\

;)

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE

w
u

~

1K

w

u

9.0

10K

S

10

~
=
8

t

OmA
1.5
3.0
4.5
6.0
7.5
LOAD CURRENT IL (mA)

14

u.

4.0~

2.0

~

S
a:
o

6.03'

L

o

g

". 16

10.0 ~

/

.=.'N

-;; 18

£

::l,...

14.0

i/

~ 3D
o
u 20

~

16.0 ~
12.0 -<

V-

'N' 20

~

18.0

~

FREQUENCY OF OSCILLATION
AS A FUNCTION OF
EXTERNAL OSC. CAPACITANCE

UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF
T,EMPERATURE

"gDI

•

YO

:~~rQUT 0;

~
-

?

82
80
100

1

+'+5Y
1K
OSC. FREQUENCY lose (Hz)

I
-H5

10K

!5

0 +25 +50 +75 HOD +125
TEMPERATURE (OC)
y.+

=r

------,

I
I
I

I
I

-

I
I

·Cos.£l
-::J:"

Ox

,d~.. -,, -=

RL

0.075 Inch
(2.1 mm)

~YOUT
LV

NOTES: 1. For large value of Cose (>1000pF) the values of C1
and C2 should be increased to 1OOIlF.
2. Ox is required for supply voltages greater than 6.5V
@ --55°· ::; TA ::; +70°C; refer to performance curves
for additional information.
Figure 1: ICL7660 Test Circuit

C,-

~------~(2~.:1~~~----~----~
Figure .2: Chip Topography

5·163

·D~DIl.

ICL7660
CIRCUIT .DESCRIPTION
The ICL7660 contains all the necessary circuitry to complete
a voltage doubler, with the exception of 2 external capacitors
which may beinexPE1nsive .10~F polarized electrolytic
capacitors. The mode of operation of the device may be best
understood by considering Figure 3, which shows an
idealized voltage doubler. Capacitor C1 is charged to a
voltage, V+, for the half cycle .when switches S1 and Sa are
closed. (Note: Switches S2 and 54 are open during this !lalf
cycle,) During the second half cycle of operation, switches
S2 and 54 are 'dosed; with S1 and S3 open, thereby shifting
capacitor C1 negatively' by V+ volts., Charge is then
transferred from C1 to C2 such that the voltage on C2 is
exactly V~, assuming ideal switches and no load on C2. The
ICL7660 approaches this ideal situation more closely than
.
existing non-mechanical circuits. .
In the ICL7660, the 4 switches in Figure 3 are MOS .power
switches; S1 is a P-channel device and S2, S3 & S4 are Nchannel devices. The main difficulty with this approach is .

that in integrating the switches, the substrates of ,S3 & S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under.output
short circuit conditions (VOUT = V+), the output voltage mU!lt
be sensed and the substrate bias' adjusted accordingly.
Failure. to accomplish this would result in high power losses
and probable device latch up.
This problem is eliminated in the ICL7660 by a logic network
which senses the output voltage (VOUT) together with the
level translators and switches the substrates or S3 & S4 to the
correct level to maintain necessary reverse bias.
The voltage regulator portion oUhe ICL7660 is an integral
part of the anti-latchup circuitry, .however it's' inherent
voltage drop can degrade operation at low Voltages.
Therefore, to improve low voltage operation the "LV" pin
should be connected to GROUND, disabling the regulator.
For supply voltages greater than 3.5 volts the LV terminal
must be left open to insure latch up proof operation, and
prevent device damage.
v+

.

OSCILLATOR
AND

SWITCH
LOGIC

L-________~~~------~--------~--+----OGND

Figure 3: Idealized Voltage Doubler·

. THEORETICAL POWER EFFICIENCY' ..
CONSIDERATIONS
In tlieory a voltage multiplier can approach 100% efficiency if
certain conditions are met:
'
A The drive cirquitry consumes minimal power
B The output switches have extremely low ON resistance
'
and virtually no o f f s e t . ,
C The impedances of the pump and reservoir yapacitQrs
are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage multiplication if large values of C1 and 'C2 'are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF .cHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
E = 1/2C1 (V1 2 - V22)
Where V1 and V2 are the voltages on C1 !:luring the pump and
transfer cycles. If the impedances of Cl and C2 are relatively
high at the pump frequency (refer to Fig. 3) compared to the
value of RL" there will' be a, substantial difference in the
voltages V1 and V2. Therefore it is not oniy desirable to make
C2 as large as possibla to eliminate output voltage ripple, but
also to employ a correspondingly large value for C1 in order
to achieve maximum efficiency of operation.

DO'S ANDD9N'T$
1 Do not exceed maximum supply voltages.
2 Do not cQnnect LV terminal to GROUND for supply
voltages greater than 3.5 volts.

3 Do not short ,circuit the output to V+ supply for supply
voltages &bove 5.5 volts for extended periods, however,
transient conditiol)s including startup are okay.
,4 When using polarized capacitors, the + terminal of Cll,
must be connected to pin 2 of the ICL7660 and the +
terminal of C2 mustbe connected to GROUND.
5' Add diode Ox as shown in Fig. 1 for hi-voltage, elevated
temperature applications.
'

CONSIDERATIONS FOR HI VOLTAGE &
ELEVATED TEMPERATURE

will.

The ICL7660
operate efficiently over its specified
temperature range with only 2 external passive components
(storage & pump capacitors), provided the operating supply
voltage does not exceed 6.5 volts at +70° C and 5.0 volts at
+125°C. Exceeding these maximums at the temperatures
indicated may result in destructive latch-up of the ICL7660.
(Ref: Graph "Operating Voltage Vs. Temperature")
Operation at supply voltages of up to 10.0 volts over the full
temperature range without danger, of ,latch-up can be '
achieved bY adding a general purpose diode in series with
the ICL7660 output, as shown by "Ox" in the circuit
diagrams. The effect of this diode on overall circuit performance is the reduction of output voltage by one diode
drop (approximately 0.6 volts),
,
5·164

O~OI6

ICL7660
TYPICAL APPLICATIONS '
1. Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 for generation of negative supply voltages, Figure 4
shows typical connections to provide a negative supply
where a positive supply is available, A similar scheme maybe
employed for supply voltages anywhere in the operating
range of +1,5V to +10,0 volts, keeping in mind that pin 6 (LV)
is tied to the supply negative (GNO) only for supply voltages
below 3.5 volts, and that diode Ox must 'be included for
proper operation at higher voltages andlorelevated
temperatures,

The output characteristics of the circuit in Figure 4are those
of a nearly ideal voltage source in series with 70 ohms. Thus
for a load current of-10mA and a supply voltage of +5 volts,
the output voltage will be -4.3 volts. The dynamic output
impedance due to the capacitor impedances is 1/wC where

giving

1

wa

21T fosc x 10-5

= 3 ohms

for C ,= 10ILF and fosc = 5kHz (1/2 of oscillator frequency)
'NOTE: 1. Vour =-nV+ FOR
1.SV S V+:5 6,5V
2. Your = -n(V+ -VFOX)
FOR 6,5 S V+ S 10.0V
>---l"--~o

Vour'

i10~F

Figure 4: Simple Negative Converter

2. Paralleling Devices

its own pump capacitor, C1, The resultant output resistance
would be approximately

Any number of ICL7660 voltage convertors l'(1ay be
paralleled to reduce output resistance. The reservoir
capacitor, C2, serves all devices while each device requires

ROUT (of ICL7660l
n (number of devices)

ROUT =

RL

Figure 5: Paralleling Devices

3. Cascading Devices

defined by:

The ICL7660 may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage, however,
due to the finite efficiency of each device, the practical limit
is 10 devices for light loads, The output voltage is

VOUT = -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the.weighted sum of the individuallCL7660
Rour val ues.

V+

Dx

r*-,

. 9---t---o Vour'

L __

..J.1. .•.

'NOTE: 1; Your = -nV+ FOR =
1,5V S V+ S 6.5V
2. Your = -n (v+-VFOX) FOR
6,5V S v+ S 10.0V
Figure 6: Cascading Devices for Increased Output Voltage

5-165

r

:E10~F .

O~OIb

ICL7660
4. Changing the ICL7660 Oscillator Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved byoverdriving the oscillator from an external
clock, as shown in Figure 7. In order to prevent possible
device latch up, a 1k!l resistor must be used in series with the
clock output. In the situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k!l pullup resistor to V+ supply is required. Note
that the pump frequency with external clocking, as with
internal clocking, will be 1/2 'of the clock frequency. Output
transitions occur on the positive-going edge of the clock.

ICL7660 at low load levels by lowering the bscillator frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, Cos e , as shown in
Figure 8. However: lowering the oscillator frequency will
cause an undes(rable increase in the impedance ofthe pump
(C,) and reservoir (C 2) capacitors; thi's is overcome by in.creasing ,the values of C, and C2 by the same factor that the
frequency has been reduced. For 'example, the addition of a
100pF capacitor between pin 7 (as c) and V+ will lower the
oscillator frequency to 1kHz from its nominal frequency of
10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and C2 (from 10~F to

It is also possible to increase the conversion efficiency of the

100~F).

v+

v+

v+

Case

1k

>---r---o Vour'

----rr---ovour

- ~~

i10~F

J;

Figure 7: External Clocking

m

l:1li

Figure 8: Lowering Oscillator Frequency

6. Combined

5. Positive Voltage Multiplication

Negative Voltage Conversion and
Positive Supply Multiplication
Figure 10 combines the functions shown in Figures4 and 9 to
provide negative voltage conversion and positive voltage
multiplication simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts from an
existing +5 volt supply. In this instance~apacitors C1 and C3
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir respectivelyforthe multiplied
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device:

The ICL7660 may be employed to achieve positive voltage
multiplication using the circuit shown in Figure 9. In this
application, the pump inverter switches of the ICL7660 are
used to charge C1 to a voltage level of V+ - VF (where V+ is the
supply voltage and VF is the forward voltage clrop of diode
01). On the transfer cycle, the voltage on C1 plus the supply
voltage (V+) is applied through diode 02 to capacitor C2. The
voltage thus created on C2 becomes (2V+) - (2VF) ortwice the
supply voltage minus the combined forward voltage drops of
diodes 01 and 02.
The source impedance of the output (Vour) will depend on
the output current, but for v+ = 5 volts and an output 'Current
of 10mA it will be approximately 60 ohms.

v+

v+

:FC3
0,

':' Vour = (2V+)(Yeo, )-(VFD')

NOTE:
0, & 0, CAN BE ANY
SUITABLE DIODE

Figure 9: ~ositive Voltage Multiplier

Figure 10: Combined Negative Converter and Positive Multiplier

5-166

ICL8001

Precision Comparator

ABSOLUTE MAXIMUM RATINGS

FEATURES
•
•
•
•
•

Low Input Current ~ 250 nA
Low Power Consumption 30 mW
Large Input Voltage Range> ±10V
Low Offset Voltage Drift 3
Output Swing Compatible with Bipolar Lpgic

i1vtc

GENERAL DESCRIPTION
The Intersil BOOl integrated circuit is a monolithic voltage comparator featuring low input currents, low power
consumption, and 250 ns response time. A versatile output
stage enables the designer to control the output voltage
swing. The use of thin film resistors ensures excellent long
term stability and the device is particularly suitable for
low power space and airborne applications.

±lBV
±lBV
±15V
500mW
15 mA
_65°C to +150°C

Supply Voltage
Input Voltage (Note 2)
Differential Input Voltage
Internal Power Dissipation (Note 1)
Peak Output Current
Storage Temperature Range
Operating Temperature Range
(B001C)
(B001M)
Lead Temperature (Soldering,60 sec)

O°C to +70°C
_55°C to +125°C
300°C

EQUIVALENT CIRCUIT

SCHEMATIC DIAGRAM

10Kn
~-_'-:'Q OUTPUT

NON-INVERTING
INPUT

9V

INVERTING
INPUT

O~T

v-

GNO

NULL

PIN CONFIGURATION
NON-INVERTING
INPUT

vTOP VIEW

(outline dwg TO-100)
NOTE: Pin 5 connected to case_

11

ORDERING INFORMATION
8001

C

TZ

L

;~"::";." '0'
Temperature Range:
C - Commercial (O°C to +70G e)

•

M - Military t-55"C to +12So C)
Device Chip Type

NOTES and Additional Electrical Characteristics on Page 5-168.

5-167

O~OIL

ICL8001
ELECTRICAL CHARACTERISTICS

(v++ = 15V, v+ = 5V, V- = ,..15V unless otherwise specified)

CONOITIONS

PARAMETER

MIN

B001M
TYP

MAX

B001C
TYP

MIN

MAX

UNITS
\

The following specifications apply for
TA = +25°C:
Rs ~ 10 Hl.

Input Offset Voltage

0.5

Input Offset Current

1.0

3.0

5.0

2

20

10

50

Input Bias Current

40

100

50

250

Input Resistance

10

Power Consumption

VOUT

= 2.5V

30

Input Offset Voltage

Rs

~

10 kil

30

4.0
2.0

Input Offset Current

'7

Average Temperature Coefficient
of Input Offset Current

35

Input Bias Current
Common Mode Rejection Ratio

60

100

15

30
100

35
300
±12

V

70

90

70

90

dB

300
±15

15,000

= +15V

At 2 mA Sink Current

nA

±10

±15
V+

nA

±12
300

Negative Output Level

mV
I1V/'C

±10

Differential Input Voltage Range
Positive Output Level Max (Note 3)

mW

pAtC

Supply Voltage Rejection Ratio
Voltage Gain

nA
Mil

6.0
3.0

20

250

Range

nA

.

\

Average Temperature Coefficient
of Input Offset Voltage

V~ltage

60

,

The following specifications apply for
-55°C::;;TA ::;;+125°C (BOO1M)
O°C::;; TA ::;; +70°C (B001C)

Input

10

mV

7.0

60,000

60,000

7.0

9.0
200

Response Time (Note 4)

15,000
500

250

250

V
V/V

9.0
200

I1V/v

V
400

mV
ns

NOTE 1: Rating applies for ambient temperatures to +70°C.
NOTE 2: For s,upply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
NO~E 3: Positive output level can be adjusted below 9V by changing V+. See circuit.
NOTE 4: The response time specified is for a 100 mV input step with 5 mV overdrive.
NOTE 5: Input bias current is independent of V-.

CIRCUIT NOTES:

vVOLTAGE OFFSET
NULL CIRCUIT

OUTPUT LEVEL COMPATIBLE
WITH TTL, DTL, ETC,

NOTE: As with all high gain comparators, care must be taken to avoid feedback between output and input. Where possible, hysteresis
should be used to provide a small deadband.

5·168

ICL8001
TYPICAL PERFORMANCE CURVES

INPUT BIAS CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENT
AS A FUNCTION OF
V++ (NOTE 5)

100
90

;;

1 80 1'\

. ~ 70

w
::: 60

a so

b-.

I-

~ 20

.s

80

I- 40

70

W
II:
II:

z

::> 30

60

::>

SO

Ul

40

OJ

30

..:

I-

::>

0-

20

?:

10

-

--

u

I-

w

!--

rf

+20

+60

+100
TEMPERATURE (OC)

=> 10

+140

o
5

6

7

8

-60

9 10 11 12 13 14 15

COMMON MOOE RANGE
AS A FUNCTION OF
SUPPLY VOLTAGE

~
w

+SV

V-=-ISV

'~"

o

t

~

60

g

15
u
a:

40

~

o0-

-r- - - r- ri-

w

20

0-

A

z

-20

+20

+60

+100

~

ou

/'

+140

7

-SSOC_

8

.if

I,

w

I'

'"

--

+2SOC

::>
0-

I-

::>
0

-~

c--+12SOC

-100

0

~

I-w

+40

INPUT VOLTAGE (V)

+100

15

13

>

-lolv,t-+
-5 mV, -2 mV

11

::>..J
00

~

~ +100

~~

~~

>

-11
J,{.;..-

~;:

I-

o

I I
-20 mV

=>",

I- ~ +100

0
- ~ -100

11

9

5

'>E

"

-40

k"

RESPONSE TIME FOR
VARIOUS INPUT
OVERORIVES

'.~

o

1i
o

v

v

V·

~\

,L -A

I

'/

15

1+2 mV
',+5 mV - - - +20mV-+10 mV .........

'~

>

I-

5

10

/

--'

0

13

en
2

RESPONSE TIME FOR
VARIOUS INPUT
OVERORIVES

I I

I

I I I
I I I
I I I I
11

- -

I I

..:
I- 6

9

>

i=

SUPPLY VOLTAGE (V)

VOLTAGE TRANSFER
CHARACTERISTICS

~

I
I
I

/'

~

TEMPERATURE (OC),

io

W

' / :...;JEGATiVE LIMIT-

o

"/

-60

\E 13
~
S 11
S
o

POSITIVE LIMIT

9

o

+140

~

,

~

;-

+100

POSITIVE OUTPUT SWING
AS A FUNCTION OF V+

11

W

Ul

+60

15

13

II:

::>

+20

TEMPERATURE 1°C)

15

.sz 80

-20

POSITIVE SUPPLY V*

V .... ;: +15V

v" ;::

r-.... r--...

?:

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

~

.......

1-'

0
-20

20

u..

0

0-

o
-60

SO

I-

u

10

;;

.s
W
II:
II:

-

r-

~ 40
OJ 30

?:

100
90

z

I"

INPUT OFFSET CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE

o

0
- ~ -100
200

400
TiME (ns)

5-169

600

800

o

>

o

200

400
TIME (ns)

600

800

•

ICL8001
CIRCUIT AND APPLICATION NOTES

INPUT

>-i>--o OUTPUT
OUTPUT

A 1 • As for minimum
Vas and d~ift.

SIMPLE VOLTAGE LEVEL DETECTOR

COMPARATOR WITH HYSTERESIS

+5V ,

SET U:''J,~o-----1

OUTPUT

INPUT

SET L~r::I~o----I

J>-+-oOQ

CONNECTION TO PROVIDE LOGICAL OR OF
TWO COMPARATOR OUTPUTS

USE OF EXTERNAL NAND GATES TO PROVIDE
OUTPUT STORAGE

BUFFER

ANALOG
INPUT

A TO D CONVERTER

WINDOW DETECTOR

5·170

ICLa007
FET Input
Operational Amplifier

O~OlL

GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

The Intersi! 8007 integrated circuit is a low input current
FET input operational amplifier. The 8007A is selected for
1 pA max input current.

Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Operating Temperature Range
8007M,8007AM
8007C,8007AC
Lead Temperature (Soldering, 10 sec.)
Output Short-Circuit Duration (Note 3)

The devices are designed for use in very high input imped·
ance applications. Because of their high slew rate, high
common mode voltage ra·nge and absence of "Iatch-up",
they are ideal for use as a voltage follower.

±18V
500mW
±30V
±15V
-65"C to +1!;O°C
-55°C to +125°C
O°C to +70°C
300°C
Indefinite

NOTES:
1. Rating applies for case temperatures to 125°C; derate linearly at
6.5 mW/oC for ambient temperatures above +75°C.

The Intersi! 8007 and 8007A are short circuit protected.
They require no external components for frequency compensation because the internal 6 dB/roil-off insures stability
in closed loop applications. A unique bootstrap circuit
insures unusually good common mode rejection for an FET
input amp and prevents large input currents as seen in some
amplifiers at high common mode voltage.

2. For supply voltages less than ± 15V, the absolute maximum input.
voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies

to +125°C case temperature or +7SoC ambient temperature.

,
TRANSIENT RESPONSE
TEST CIRCUIT

EQUIVALENT CIRCUIT
r-~--------~--~--~~----~-ov'

,--________~~---- v ...

OUTPUT

v.

~--4---4-------~~--~--+-----~-ov-

PIN CONFIGURATION (outline dwg TO-99)

ORDERING INFORMATION

NC

Part
Number

vITQPVIEWI

IClBOO7C
ICL8007AC
ICL8007M
ICL8007AM

Temperature
Range
O°C to +70"C
-55°C to +125°C

dice

To-99
Can

ICL8007C/D
ICL8007AC/D
ICL8007M/D
ICL8007AM/D

ICL8007CTV
ICLBOO7ACTV
ICL8007MTV
ICLBOO7AMTV'

,

• Add 1883B to order number if 883B processing is desired.

NOTE: Pin 4 connected to case

5-171

ICL8007
ELECTRICAL CHARACTERISTICS (V s = ±15V unless otherwise specified)
fl007M
MIN

B007AM & B007AC

8007C

CONDITIONS

CHARACTERisTICS

TYP

MAX

10

20

MIN

TYP

MAx

20

50

MIN

TYP

MAX

15

30

UNITS

The following specifications apply for TA = 25"C:
Rs~l00kll

Input·Off.et Vciltage
Input Offset Current

0.5

Input Current (either input)

2.0

0.5
20

3.0

Input Capacitance

2.0
.R L ~ 2 kll, V OUT = ±10V

Large Signal Voltage Gain

0.5

106

10"

Input Resistance

50

4.0

106

2.0

50,000

pA
Mil
pF

2.0

20,000

mV
pA

0.2

V/v

20,000

Output Resistance

75

75

75

n

Output Short-Circuit Current

25

25

25

mA

Supply Current

3.4

Power Co.nsumption
Slew Rate

.

102

3.4
102

6.0

3.4

180

6.0

6.0

1.0

1.0

Unity Gain Bandwidth
Transient Response (Unity Gain)

5.2
156

102
2,5

6.0
180

mA
mW

6:0

V/jls

1.0

MHz

CL~100pF,RL=2kll

Risetime
Overshoot

300

300

300

ns

10

10

10

%

The following specifications apply for O"C $. TA $. +70"C (S007C and BOO7ACJ. -55"C $. TA $. +12S'C 18007M and 8007AM):

Input Voltage Range

±10

±12

±10

±12

±10

±12

V

70

90

70

90

86

95

dB

Common Mode Rejection Ratio
Supply Voltage Rejection Ratio

70

Large Signal Voltage Gain·

300

70

25,000
RL~10kn

Output Voltage Swing

,

RL~2kn

Input Current (either input)

600

70

±14

±12

±14

±12

±14

tl0

±13

±1O

±13

±10

±13

2.0

V
V

1.0
50

Average Temperature Coefficient
of Input Offset Voltage

nA
pA

30

75

jlV/v
V/v

±12

TA = +125°C
TA=+70°C

200

15,000 .

15,000

75

50

jlvtc

TYPICAL PERFORMANCE CURVES
OPEN LOOP
VOLTAGE GAIN
10·
10'

z

10'

w

10'

"'"
'"....«

10'

>

10

-'
0

-

~sup~ = ±~5V
T.

~

1

t

10

VOL TAGE FOLLOWER LARGESIGNAL PULSE RESPONSE

=+25°C

""""100

lk

w

4

0

a

'....-'«"
>

....
12....

-4

::>
0

T.

I I

l-

\

INPUT

'"3:

=25°C

10M'

~s~;P ~±W~
TA =t25"C
RL = 10kn

32

Vl

YI I
I OU~P~T
1/

12....
::>

24

'«"
w

16

"'"
':"

8

~

a

1\

0

\

-- 0

40

....

"-

-8

\

10k lOOk 1M

FREQUENCY IHzl

~

~
z

I I VSUPP = t15V

8

OUTPUT VOLTAGE SWING AS
A FUNCTION OF FREQUENCY

1 2

3

4

5

TIME I"sl

5-172

6

7

8

9

Ik

10k

lOOk

1M

FREQUENCY IHzl

10M

ICL8007

OUTPUT SWING AS A FUNCTION
OF SUPPL Y VOLTAGE

INPUT CURRENT AS A
FUNCTION OF TEMPERATURE

TRANSIENT RESPONSE

20

28

T. =25"C
AL = 2 kn

24

>

....E.
...~:>

20

~

90%

16

II
Vs=!15V
.y..- AISE TIME TAL. --= 25°C
2 kH
CL = l00pF
I

0

o

.5

1.0

1.5

2.0

/ (t

10

/

V

0

/
./

2.5

40

TIME 1.,1

60

80

100

120

o

140

V

NEGATIVE SWING

15

10

5

20

SUPPLY VOLTAGE I!VI

TEMPEAATUAE lOCI

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE

V

/

0..

/

10%
0

...~:>
...:>

/

y-.

POSITIVE SWING /

z

I
I

12

/

15

CJ

INPUT VOLTAGE RANGE AS
A FUNCTION OF SUPPLY VO~TAGE

QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF SUPPLY

VOLTAG~

20

w

~

CJ

z
«

Z

a:
w

;t

'"
0..

1 .

~

>
lOS

CJ

......
0
...:>>
«

0
0

...
Z

W
0..

0

15
POSITIVE / .

10

15

20

<
..s

V

:>

/ V

&:

iil

10

15'

20

",,1000

10'

§
>

zw

I';:

I-

a:
a:
:>
u

~

-

>

.!O

I- !----

3

w

'"0z

10'

w

,.-.

...

>

0

10'

1"-'

'"0Z
-15

25

65

TEMPERATURE lOCI

105

10

100

ik

...a::>

..

~

L
10k

FREQUENCYIHzI

For additional information, see Applicatio'n Bulletin A005.

5·173

w
u.
w

Rs= 50n

llt

o
-55

a:
a:

As' 1 Mn

w

'"

r- BANDWIDTH
r- = 10 Hz TO 100 kHz i./

w 10.0

«

......
>

0..
0..

:>.

100

a

CJ

I-

20

WIDE BAND NOISE AS A FU~CTlON
OF SOURCE RESISTANCE

Vs = :!"15V

5

15·

10

5

SUPPLY VOLTAGE ItVI

INPUT VOLTAGE NOISE AS
A FUNCTION 'OF FREQUENCY

6

~~

...>

SUPPLY VOLTAGE I!VI

QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF TEMPERATURE

4

-~

u

k'"

SUPPLY VOLTAGE I!VI

..s<
...

4

a:
a:

/. VNEGATIVE

0

T. = 25'C

!zw

/V

10

~.

o

/.~

lOOk

~

----

.

L

I"

.\"

1.0

=

BANDWIDTH
= 0.1 Hz TO I_1HZ::
0.1
100

lk

10k

lOOk

1M

10M 100M

SOURCE RESISTANCE 1m

ICL8008
Low Input Current
Operational Amplifier

U~U[b

FEATURES

GENERAL DESCRIPTION

•
•
•
'.
•
•

The 8008 is.a high performance monolithic operational.
amplifier with very low input currents. It is intended for
a wide range of analog applications. High common mode'
voltage orange and absence of "latch-up" tendencies make.
the 8008 ideal for use as a voltage follower. The high gain
and wide range of operating voltages provide superior per·
formance in integrator, summing amplifier. and general
feedback applications. The 8008 is short.,.circuit protected;
has the same pin configuration'as the popular 741 operational amplifier. and, requires no external components for
frequency compensation. The internal 6 dB/octave roll-off
insures stability in closed loop applications.

Low Input Current
No Frequency Compensation Required
Offset Voltage Null Capability·
Large Common-Mode and Differential Voltage Ranges
Low Power Consumption
No Latch uP.

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS
±18V
Supply Voltage
SOOmW
Internal Power Dissipation (Note 1) ,
Differential Input Voltage
±30V
Input Voltage (Note 2) .
±1SV
Voltage between Offset Null and V±O.SV
-6SoC to +lS0°C
Storage Temperature Range
Operating Temperature Range ,
-SSoC to +12SoC
8008M
O°C to +70°C
8008C
300°C
Lead Temperature (Soldering. 60 sec.)
Output Short';'Circuit Duration (Note 3)
Indefinite

PIN' CONFIGURATIONS
Plastic DIP

o':~~:O~
I~"UT

INI'U"

V

•

. (outline dwg TO"99)
NOTE: Pin 4 CONNECTED TO CASE

V'

•

••

OUTPUT

~~~!n

}'DPYIEWI

NOTE 1: Rating applies for case. temperatures to J 25" C; derate
linearly at 6.5· mwtC for ambient temperatures above
+75"C.
NOTE 2: For supply voltages less than ±15V. the absolute maximum input voltage is equal to the supply voltage.
NOTE 3: Short circuit maY be to ground or either supply. Rating
applies to +125°C case temperature or +75°C ambient
.
temperature.

(outline dwg PAl

,ORDERING INFORMATION
ICLaoas

M

TV

l

Package:
.
.
TV-TO-99 metal can
.
PA-S Pin Plastic DIP (Available
only at Commercial Temperature
Range) ·ID Dice
Temperature Range:
M-Military -55°C to +125°C
C -Commercial OOC to + 700C
Device Type

5·174

ICL8008
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

(V s = ±15V unless otherwise specified)
8068M

8008C

r M:-:-1N:-:--""':;::OT:::Y':;'P'---:M-:-A-:-X:-:-f--:-M':':I-:-N"'-"::"::'T::':Y::':P'---M-A-:-i
X UN ITS

CONDITIONS

The following specifications apply for T A = 2SD C:

Input Offset Volta'ge
Input Offset Current
Input Bias Current
Input Resistance
Input Capacitance
Offset Voltage Adjustment Range
Large-Signal Voltage Gain
Output Resistance
Output Short-Circuit Current
Supply Current
Power Consumption
Transient Response (unity gain)
Risetime
Overshoot
, Slew Rate (un,itv gain)

Rs~10krl.

1,0
1.0
2
25
5
1.5
±15
20,000 200,000
75
25
1.7
50

RL ~ 2 krl., VOUT = ±10V

VIN = 20 mY, RL = 2 krl.,
CL ~ 100 pF

mV
nA
nA
Mri.
pF
mV
V!V

rI.
2.8
85

0.3
5.0
0.5

mA
mA
mW
/JS
%

V//Js

oC IB008MI:

1.5

6

1.5

' 7

Rs~ 10 krl.

7.5

15
30

Il)put Bias Current

50

Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large Signal V~ltage Gain
Output Voltage Swing

6.0
20
25

-< TA -< +70°C IBOOBCI, _55°C -< TA -< +12S

Rs~ 10krl.

Input Offset Voltage
Input Offset Voltage Average
Temperature Coefficient
Input Offset Current

2.8
85

1.0
2.0
5
5
25
1.5
±15
20,000 200,000
75
25
1.7
50

0.3
5.0
0.5

RL ~ 2 krl.

The following 'specifications apply for DoC

5
5
10

±10
70

±12
90
30

Rs ~ 10 krl.
Rs~ 10 krl.
RL:?: 2 krl., VOUT = ±10V 15,000
±12
RL:?: 10 krl.
±10
RL:?: 2krl.

±12
70

±13
90
30

150
15,000
±12
±10

±14
±13

mV

30

/Jvtc
nA

50

nA

150

±14
±13

V
dB
/JV!V
V!V
V
V

TYPICAL PERFORMANCE CURVES
OPEN l.OOP VOl.TAGE
GAIN AS A FUNCTION
OF SUPPl. Y VOl.TAGE

OPEN l.OOP VOl.TAGE
GAIN AS A FUNCTION
OF FREQUENCY

10"
lOS

z 10'


-

~

10,,1
10

100

z


""

[\

lk 10k lOOk 1M 10M

FREQUENCY 1Hz)

24

;;

Cl

~

_f.-

20

I--t---i--+--i--+--t
1--I--1'P'-+--i---+--t
90%

16 ~~~/~~~"'-~~

~ 12 1---++,1+--+--1-+--1
581---++-1+-+--1-+--1

lOS

I-

~

10

T.=25'C=
5 x lOS

w

.",

-'

0

I
,~
Vs = .15V_
T. = 25°C

"'- ~

TRANSIENT RESPONSE
28 r-~--~--~-,---r--'

10"

5 x 10'

o

,

4

o
10'
10

15

20

SUPPLY VOLTAGE ltV)

CIRCUIT NOTES:
TRANSIENT RESPONSE
TEST CI RCUIT

VOl.TAGE OFFSET
NUl.l. CIRCUIT

v"

5·175

Vs= '15V

10%

"r- RISE TIME TR~:- 25'C
2 kll.
CL

o

,5

1,0
TIME I~sl

1.5

•

100 pF

2,0

2.5

ICLS013
Four Quadrant Analog Multiplier
/

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•

The ICL8013 is a four quadrant analog multiplier whose
output is proportional to the algebraic product of two input·
signals. Feedback around an internal op-amp provides level
shifting and can be used to generate division and square root
functions. A simple arrangement of potentiometers may be
used to trim gain accuracy, offset voltage and feedthrough
performance. The high accuracy, wide bandwidth, and
increased versatility of the ICL8013 makes it ideal for all
multiplier applications in' control and instrumentation
systems. Applications include RMS measuring equipment,
frequency doublers, balanced modulators and
demodulators, function generators, and systems process
controls.

Accuracy of ±O.5% ("A" version)
Full ±10V I/O voltage range
1 MHz bandwidth
Uses .standard ±15V supplies
Built ip op amp provides level shifting, division and
square root functions.

1iJ,----;.-_ _ _ _ _-...
BLOCK DIAGRAM (MULTIPLIER)

ZIN

X,N

Xos

VOLTAGE TO CURRENT
CONVERTER AND
SIGNAL COMPRESSION

OUTPUT

Yos

ZIN

PIN CONFIGURATION

ORDERING INFORMATION
TEMPERATURE MULTIPLICATION ORDER PART
NUMBER
TYPE
RANGE
ERROR
ICL8013AM -55°C to +125°C
ICL8013AM TZ
ICL8013BM -55°C to +125°C
±1%
ICL8013BM TZ
ICL8013CM -55°C to +125°C
±2%
MAX' ICL8013CM TZ
ICL8013AC TZ
ICL8013AC
O°C to +70°C
±.5%
±1%
ICL8013BC TZ
ICL8013BC
O°C to +70°C
±2%
ICL8013CC TZ
ICL8013CC O°C to +70°C

Yos

±'"}

ICL8013C/O

O°C to +70°C

±2% TYP

ICL8013C/O

V·
TOP VIEW

(outline dwg TO·l00)

5·176

O~OIb

ICLS013
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................. ±18V
Power Dissipation (Note 1) .................... 500 mW

Input Voltages (X, Y, Z, Xo, Yo, Zo) .........•.... VsuPP
Lead Temperature (soldering, 10 sec) ..... , ...... 300 0 e
Storage Temperature Range ........... -65°e to +150 o e

NOTE 1: 'Derate at 6.8 mW/oC for operation at ambient temperature abov.e 75°C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificatiqns is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Unless otherwise specified TA = 25°e VsuPP = +15V
Gain and Offset Potentiometers Externally Trimmed)
PARAMETER

Multiplier Function
Multiplication Error'

CONDITIONS

MIN

ICL8013A
TVP MAX
XY

10
-10< X < 10
-10ECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES
Multiplication
-10 < X < 10,
1.5
2
-10

'
Q.

TA

0

10M

.J

25'C
RBw = 20 kG
R,=5kG

24

16

'"~

12

at-

8

'"

4

Q.

0

Q.

..:

w

iii
:2

z

~

'~"

a

>

Q.

a

a..J

Z
W

Q.

a
100

FREOUENCY IMHzI

-5.0

~~

.3

80
70
60
50
40
30
20
10

o

[{

~
....

~III

IIII

IIII
lOOk

1M

-20
-10
0
-.
:x:
10
»
VI
m
20
VI
30
!
."
40
-l
50
C60
70
80
90

.

Row=20k~ ~

10k

\
INPUT

.1

.2

10M

FREOUENCY 1Hz)

.3

.4

.5

(~.)

FREQUENCY CHARACTERISTICS AS A FUNCTiON OF
TEMPERATURE

IA

1111

j

-10

\.

TIME

~11I=ti_~1
BW
'II

~

1\

I
'I
o

.5

".4

I~s)

IIII I

90

1\

I

-7.5

AESPONSE

..:

-

0

dPE~LOOPFREQUENCY

w

10

.2

TIME

•

r

2.5

-10

o

100M

t-

::J

;=

\

INPUT

20

a

t-

::J

TA • 25'C
Raw' 20 kG

OUTPUT

5.0

~

5 -2.5

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY

28

10
7.5

\

FREOUENCY 1Hz)

32

UNITY GAIN LARGE
SIGNAL PULSE RESPONSE

1

10

1000

100

CLOSED LOOP GAIN

Q.

a

r"

I

VI

10

1

OUTPUT

I
Row' 20kll

u

75 100 125

TA·= 25'C
Row = 20 kll

60

Row.lnll

a..J

~
z

50

UNITY GAIN TRANSIENT
RESPONSE

40
20

25

70
Raw

60

a

100

TEMPERATURE I'CI

80

..J

>

lk

o c....JL.U..l.WIIL-L.U..LLUI......I..ioj.l.ll...£

3,0
0

FREQUENCY RESPONSE
FOR VARIOUS CLOSED
LOOP GAINS

w

a:
:;

:;

TEMPERATURE I'CI

'"

~

"..

'"

-75 -50 -25

';;:

£ 10k

::J

20

z

.....~

u

o

iii
:2

lOOk.a. .

6,0

120

1

OPTIMUM VALUE OF'Raw
AS A FUNCTION OF CLOSED
LOOP GAIN (SEE FIG. 1)

1

100M

1.6
1.4

UNITY GAIN
Row' 20 kG

I-+--+-I-+--r-'-r---r--!

w
:::>
..J



w

>
;:

0

..:
..J

w 0.8

a:

0.6
0.4 '--'---'--"'---'--'---'--'--'
-75 -SO, -25 0 25 50, 75 100 125
TEMPERATURE I'C)

·S017C only guaranteed for 0° C ::: T A :::;: + 70° C

DEFINITION OF TERMS
Input Offset Voltage:

Voltage which must ,be applied to
input terminal to obtain zero output vqltage.

Input Current: Current into input terminal when at ground
potential.

Unity Gain Bandwidth: The frequency at which the small
signal gain is 3 dB below its low frequency value.
Transient Response:' The 10% to 90% closed loop stepfunction response of the amplifier under small signal
conditions_

Large Signal Voltage Gain: The ratio of maximum output
swing with load to the required change in input drive
voltage.
Settling Time: The elapsed time between the application
of a fast input pulse and the time at which the output has
Slew Rate: The maximum rate of change of output voltage
settled to its final value within a specified limit of accuracy_
in response to a large amplitude input pulse_
5-185

·D~DIL

ICL 8017
APPLICATIONS INFORMATION
Figure 1. Inverting·Voltage Amplifier

v'
R.

lIJF~

R. w

GAIN

~s

R,

IX
lOX
l00X

10m
10kO

10m
l00kn

20kn
an

Ikn

lOOkn

shon

Raw

BAND·
WIDTH

10MHz
-6MHz
800kHz

SLEW
RATE

1loV/I/o'
100V/IJ.!
5OV/p,s

y-

~OTE: If no' bandwidth control resistor (Rew) is connected between pins 3 and 4, the amplifier is unconditionally stable for
normal feedback configurations. Some Impro"eme~t· in frequency performance can be realized by setting Raw = 20 kSl;

the amplifi!r will still be uncondition~lIy stable. However, for optimum frequency response, Raw should be selected from
the" curve on page 3, based on the closed loop gain of the circu it. Additional control of the bandwidth/stability trade~off is
possible by bypassing Rt ~ith a low value capacitor. It is not necessary to alter t,he value of C" C2 or C3'
'

Figure 2. Current Summing A";pllfler
y'

0,1% SETTLING TIME· l.,sec
,onr. SETTLING TIME· 3.,sec

,.Fl

y-

NOTE: The analog output current of the 8018 Series 0/ A current switches can be converted to voltage using the 8017 as shown. Input
compensation of approximately 10 kO and 30 pF helps improve sattllng time.

Figure 4. Isolation of Capacitive L,.oads

F ig,ure 3. Settling Time Measurement
'OK

10K

PUL~~ Ooo.............' ..
OK......_-1

15pF

.":)-......- 0 ••
'OK

v,. Ooo-W......--4-l
Sin
SK
L.OW CAPACIT ANCE
SCOPE PROBE

\

F0771

NOTE: Excess ph.se shift caused by h.avy capacitive
loading (above 200 to 300 pF)' can cause stability
problems. By providing the amplifl.r with a minimum·r.al load Impedance (510). these difficulties can be overcome. Note that at high out-'
put currents. maximum voltage swing will be
reduced.

N,OTE: Settling time is measured by creating .. dummy
summing junction lind observing the error voltage
waveform on' a sCope. The J'unctlon Is clamped
with high speed diod.s to avoid overdrlvlng the
scope preamp.

5-186

ICL8021-ICL8023
Low Power
, Operational Amplifiers

FEATURES
•
•
•
•
•
•
•

!:Nos = 3 mV max (adjustable to zero).
±lV to ±18V Pqwer Supply Operation.
Power Consumption - 20 p.W @ ± lV.
Input Bias Current - 30 nA max.
Internal Compensation.
Pin-For-Pin Compatible With 741.
Short Circuit Protected.

GENERAL DESCRIPTION
The Intersil8021 integrated circuit is a low power operational
amplifier specifically designed for applications requiring very
low standby power consumption over a wide range of supply
voltages. The electrical characteristics of the 8021 can be tail, ored to a particular application by adjusting an external resistor, RsET, which controls the quiescel1t current. This is advan, tageous because IQ can be made independent of the supply
voltages; it can be setto an extremely lowvaluewhere power
is critical, or to a larger value for high slew rate or wideband
applications.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Il)put Voltage (Note 1)
Common Made Input Voltage (Note 1)
Output Short Circu it Duration
Power Dissipation (Note 2)
Operating Temperature Range
8021M
8021C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

±18V
±15V
±15V
Indefinite
300mW

Other features of the 8021, incl,ude low input current that re"
mains constant with temperature, low noise. high inpl,lt impedance, internal compensation and pin-for-pin compatibility with the 741.
'

- 55·C to + 125·C
O"C to +70·C
-65·C to +150·C
+300"C

The Intersil8022 (8023) consists of two (three) low power operational amplifiers in a single 14-pin DIP. Each amplifier is
,identical to an 8021 low power op amp, and has separate connections for adjusting itS electrical characteristiCs by means
of an external resistor, RSET ' which controls the quiescent current of that amplifier.

NOTE 1: For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.
NOTE 2: Rating applies for case temperatures to +125·C; derate
linearly at 5.6 mW/·C for ambient temperatures above
+ 95·C. :

SCHEMATIC DIAGRAM

11:1

PIN CONFIGURATIONS

'BALO'
JfAil'•.
"

~N

2

"IN

•

V-

•

v-

,'loSET
7
V",

'

,
•

OUT

BAL'

(outline dwg PAl

(outline dwg TO-99)
NOTE: Pin 4 connected to case:

VOLTAGE OFFSET !\lULL CIRCUIT
(outline dwg JO, PO)

"

ORDERING INFORMATION
1CLI021

-r

Baale
Pan Number
8021-5lngle
8022-DU81
802~Trlple

1
C

TV

"'LP~~O-99 Metal Can
PA-8 pin Mlnidlp

8021 ~nly

~g::~: ~:~ ~~'::DIP

8022 only

~~ :~ ~:~ ~=!PDIP

-8023 only

(outline dwg JE. PEj

, Temperature,
C- Commercl81- O'C to 7O'C
M- Military -56"C to +125'C

5·187

!I;I

ICL8021-ICL8023
ELECTRICAL CHARACTER1STICS (V s = ±6V, IQ = 30 }.lA, unless otherwise specified.)
CHARACTERISTICS

8021C

8021M

CONDITIONS

MIN

TYP

MAX

MIN

MAX'

TYP

UNITS

The following specifications apply for T A = 25°C:

Input Offset Voltage

Rs ::;100kSl

\

2

Input Offset Current

3

.5

Input Bias Current

5

Input Resistance
Input Voltage Range

Vs = ±15V

Common Mode Rejection Ratio

Rs ::;10krl

2
.7

7.5
7

20

6

mV

10

nA

30

nA

3

10

3

10

M.I1

±12

±13

±12

±13

V

70

80

70

80

dB

/

Supply Voltage RejectionRatio

Rs ::;10kn

Output Resistance

Open Loop

Output Voltage SWJng

RL ~ 20 kSl, Vs = ,±15V
RL ~ 10 kn, Vs = ±15V

150

30

30

2
±12
±11

Output Short·Circuit Current

±14
±13

±12
±11

±13

Power Consumption

V OUT =0'
\

Unity Gain Bandwidth

R L = 20 kn, V IN = 20 mV

Transient Response (Unity
Gain)
Risetime
Overshoot

V
V
mA

360

0.16

600

}.lW

V/}.ls

0.16

kHz

270

270

}.lVIV
kn

±14
±13
±13

480

360

Slew Rate'.(Unity Gain)

150

2

RL = 20 kn, V IN = 20 mV
1.3
,10

1.3
10

}.lS

%

The following specifications apply for 0 C < TA < +70 C (S021C) -55 C < +125' C (S021M)

I nput Offset Voltage

Rs ::;10kn

I nput Offset Current
Input Bias Current

2,0

4,0

2.0

1.0

5

1.5

15

10

Av~rage

Temperature
Coefficient of Input
Offset Voltage

R s ::;10kn

Average Temperature
Coefficient
Input
Offset Current

of

7.5
15

15

50

mV
nA
nA

5

5

}.lV;"C

1.7

0,8

pAtC
,

Large Signal Voltage Gain

RL = 10kn

Output Voltage Swing

RL ~ 10 kn

50

200

50

200

V/mV

±10

±13

±10

±13

V

QUIESCENT CURRENT ADJUSTMENT

QUIESCENT CURRENT
SETTING RESISTOR
IPIN 8 TOV-)

QUIESCENT CURRENT
SETTING RESISTOR
IPIN8TOV-)
v,
~

10j,lA

3O.A

tOOuA

!T 5

15M!l

470kH

150 k!2

,

3

33 MH

11 MH

330 kl!

100k!l

,

6

75MH

21MU

-750kn

220 kH

JOO.A
I'j . lOjJA
10

• 9

13MH

4Mn

13MU

35QkH

!

12

18Mn

56MH

15 Mil

510 k!!

!

15

22 Mil

7.5MH

22 MU

620kU

M!~

1(j-3~
lu - l00jJA

1 M!~

\

100

,

1

~!~

0

,,

6

8

10 - 300 jJA

111111
10 12 14

SUPPLY VOLTAGE (-VI

5-188

16

18

O~OIb

ICL8021-ICL8023

TYPICAL PERFORMANCE CURVES* (T A; +25°C, VS; ±6V, IQ ; 30 !lA, unless otherwise specified.)

am_

INPUT BIAS CURRENT
VS QUI ESCENT CURRENT
100

1
~

z

~

~

i3

100

1
~

50

~

0

10

DIFFERENTIAL INPUT
IMPEDANCE VS
QUIESCENT CURRENT

INPUT BIAS CURRENT VS
AMBI ENT TEMPERATURE

U

~

«

~
~

~

~

~

r-r-

~

0.l

r-r-

i~

r-

10" lOJ.lA

0

10

30

100

300

60

100

140

TEMPERATUAE ( CI

~

100

30

"

300

QUIESCENT CURRENT 'liA)

PHASE MARGI N VS
QUI~SCENT CURRENT

FREQUENCY RESPONSE
VS QUI ESCENT CURRENT

.5;EB

§"'IIII

10

~

I I I
-20 0 20

aUIESCENT CURRENT I"AI

SLEW RATE VS
QUIESCENT CURRENT

,r----··1-4+1·~II_-_I_-crI-I_HHH

r

Z

1
-60

1

1: fJmlf1c~:-l=1m

~

Ia', 3'

10

~

=

r-

10'" l00j.lA

AL ":WkI!

r

~

500

r

o
~ 300

~

";::

200

z
~

/'

~

°'00
~

<

~

V

~

V

90

-I-

75
60

./
45

30

100

~
30

100

300

10

aUIESCENT CURRENT ("AI

OPEN·LOOP FREQUENCY
RESPONSE

~

z

-

120

"

~-R,

- 50 kll

80

R,

-5k~!-

S

20,

~

15

10

~-++t~1-+-~-+-t~

~-+HI-~1-+-~-+-t~

10

lk

:=

/'

~

10
Rl

~

20 kH

'===

L

~

~

00

> 60

~

~
0
>

50

;:::

40

"ii'
z

~

0

'3

!6

!10

SUPPLY vOLTAGE (VI

r

~

10 =30",A:j"

50

5·189

,

~

r---..

i3

10"'A~

100

........... 10 " 100",A

~

ill.

FREQUENCY 1Hz)

300

?

"100"'A~

"ii'

10" 30",A

..!a " lQ",A

z

1IIIIll
IlllilL
10

100

EQUIVALENT INPUT'NOISE
CURRENT VS FREQUENCY

1111111
I-+-

30

QUIESCENT CURRENT ("AI

20
10

I I

10

10

Ittf

30

~

'1

V, "6V

~

16

f

Vs - '15V

1

10 =

~

"'"

10

RISE TIME

EQUIVALENT INPUT NOISE
VOLTAGE VS FREQUENCY

~

~
~

~

TIME I"sec)

OUTPUT VOLTAGE SWING
VS SUPPLY VOLTAGE

~

3

;;


(J

:>

10

~

5
5

10

15

20

25

SUPPLY VOLTAGE

1.03

>
~ 1.02

"'
...C 1.00

:>
fil1.0 1

:>
fil 1.01

-

~

T1T

~~ V

en

1.03

>
~1.02

a:

~ ~ rx~25'C

>

..J
.Q.
Q.

~V

/

"'

a: 15
a:

II

30

~0'99

::;

N

t

30V
-:-20V
l'OV

.....

-

;;;

~

~

.rtov

a:

00.98

00.98

z

::
. 5

"'~0.99

::;

a:

z

"'
a:
...C 1.0Or-

10

15

20

25

SUPPLY VOLTAGE

5·192

30

~~

,
-SO -25 0 25

75

TEMPERATURE' C

125

O~O!L

ICLS038
THEORY OF OPERATION (see block diagram,
first page)
An external capacitor C is charged and discharged by two
current sources. Current source #2 is switched on and off by
a flip-flop, while current source #1 is on continuously.
Assuming that the flip-flop is in a state such that current
source #2 is off, and the capacitor is charged with a current I,
the voltage across the capacitor rises linearily with time.
When this voltage reaches the level of comparator #1 (set at
2/3 of the supply voltage), the flip-flop is triggered, changes
states, and releases current source #2. This current source
normally carries a current 21, thus the capacitor is
discharged with a net-current I and the voltage across it
drops linearly with time. When it has reached the level of
comparator #2 (set at 1/3 of the supply voltage), the flip-flop
is triggered into its original state and the cycle starts again.

Four waveforms are readily obtainable from this basic
generator circuit. With the current sources set at I and 21
respectively, the charge and discharge times are equal. Thus
a triangle waveform is created across the capacitor and the
flip-flop-produces a square-wave. Both waveforms are fed to
buffer stages and are available at pins 3 and 9.
The levels of the current sources can, however, be selected
over a wide range with two external resistors. Therefore, with
the two currents set at values different from I and 21, an
asymmetrical sawtooth appears at terminal 3 and pulses with
a duty cycle from less than 1% to greater than 99% are
available at terminal 9.
The sine-wave is created by feeding the triangle-wave into a
non-linear network (sine-converter). This network provides a
decreasing shunt-impedance as the potential of the triangle
moves toward the tWb extremes.

Performance of the Square-Wave Output
200

114

RISE TIME
I

150
-)-

I

w
CJ

~

;!:
o

... 1.5

25~~ fP"'-5S 6C
125\C~~

~~
..c1:"&7

I
I

FALL TIME

50
- ) - 25°C

o
o

-I

~f.J

2

TT

V

>
~

1

~
a:
1=

0.5

25°C
125°C

I~ e:::

;}j

o i.IIII iI'f'

125°C

, 6

o

10

2

~ VV

~~
;.... ~J;.5.C

I' '1

10

4

LOAD CURRENT-rnA

LOAD RESISTANcE-kn

Performance of Triangle-Wave Output

~

1.0

r1.,r;ie!==J:;;~~~~

g

....

>

!;

~ 0.8

H-t-t-+-+-+-Nnhi-+-l

o

w
N

:::;

'"

z

1.0

c

/

::t

0.8

:Iia:

0.7

:::;.

·z 0.6
0 2

4 6 8 10 12 14 16 18 20
LOAD CURRENT-rnA

I

0.1

o

:I:

15

I

r

1.1

L.g
o

:>

o
~

~
...
o

~ 0.9

10

w 1.2

10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY

0.01
10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY

Performance of Sine-Wave Output
w 1.1

~
g
!;

~

~

a:

o
z

II

10

1.0

5o
c

12

"' f\

~

o

.~
~

o.g

!!!

c

8

6

~

4

'I. ADJ~~

~

o

10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY

rJ

U~A IJ,lST D

ED

~ 1-1-

10Hz 100Hz lkHz,10kHzl00kHzlMHz
FREQUENCY

5-193

O~OIl,

ICLS038

v
~
"'-.
1"'-V

v "-

"r"\1"'-V V
-

1"-V

""1"-V

V !'\

' /r\
,
\/

..... ,/"

' /r\

..V

\ ......... "

~

'\

,,/~

'/

r\

'V

~

Square-Wave Duty Cycle - 50%

......

.,.... /

"

~

Square-Wave Duty Cycle - 80%
Phase Relationship of Waveforms

WAVEFORM TIMING

With two separate timing resistors, the frequency is given by

The symmetry of all waveforms can be adjusted with the
external timing resistors, Two possible ways to accomplish
this are shown in Figure 1. Best results are obtained by
keeping the timing resistors RA and Rsseparate (a). RA
controls the rising portion of the triangle and sine-wave and
the 1 state of the square-wave.
The magnitude of the triangle-waveform is set at 113 Vsupp;
therefOre the ri~ing portion of the triang. Ie is,

m

f

=_1_' = -::-_--:__--=_--,t1

+ t2

f=

5

5

Rs

RA

(b)

(a)

v+

(e)

r--------.--~~v+

6

,JUl..

ICL8038

11
C

r--------.--~~v+

Rs

RS

10

(for Figure 1a)

Neither time nor frequency are dependent on supply voltage,
even though none of the voltages are regulated inside the
integrated circuit. This is due to the fact that both currents
and thresholds are direct, linear functions of the supply
voltage and thus their effects cancel.
To minimize sine-wave distortion the 82kO resistor between
pins 11 and 12 is best made variable. With this arrangement
distortion of less than 1% is achievable. To reduce this even
further, two potentiometers can be connected as shown in
Figure 2; this configuration allows a typical reduction of
sine-wave distortion close to 0.5%. '

=.£ X RARsC
3 2 RA - Rs ,

Thus a 50% duty cycle is achieved when RA = Rs.
If the duty.cycle is to be varied over a small range about50%
only, the connection shown in Figure 1b is slightly more
convenient If no adjustment of the duty cycle is desired,
terminals 4 and 5 can be shorted together, as shown in Figure
1c. This connection; however, causes an inherently larger
variation of the duty-cycle, frequency, etc. '

RA

~.~

f = 0.15
RC

The falling portion of the triangle and sine-wave and the 0
state, of the square-wave is:
'CX1/3V+

Rs
)
2 RA-Rs

If a Single timing resistor is used (Figure 1c only), the
frequency is

-"3

1. X Vsupp _ ~ X VsuPP

3

or, if RA = Rs = R

t _CXV _CX1/3XV+XRA - 5 R
C
1I
-,
1/5XV+
AX

t = CXV =
2
I

.§. RA C ( 1 +

12 2

Vv
'\IV

RL

6

4

ICL8038

10

9

3

12 2

11

)'111
Vv
'VtJ.

J1JL

Vv
10

c

82k
V-orGNO

11
C

'------"-----4__-----cy- or GND

Figure 1: Possible Connections for the External Timing Resistors,

5-194

12 2

'V\,

82k
V-orGND

ICLS038
FREQUENCY MODULATION AND SWEEPING

v+

RB

The frequency of the waveform generator is a direct function
of the DC voltage at terminal 8 (measured from V+). By
altering this voltage, frequency modulation is performed.
For small deviations (e.g. ±10%) the modulating signal can be
applied directly to pin 8, merely providing DC decoupling
with a capaCitor as shown in Figure 3a. ' An external resistor
between pins 7 and 8 is not necessary, but it can be used to
increase input impedance from about 8k!1 (pins 7 and 8
connected together), to about (R + 8k!1l.
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply
voltage and pin" 8 (Figure 30f. In this way the entire bias"for
the current sources is created by the modulating signal, and
a very large (e.g. 1000:1) sweep range is created (f = 0 at
Vsweep = 0), Care must be taken, however, to regulate the
supply voltage; in this configuration the charge current is no
longer a function of the supply voltage (yet the trigger
thresholds still are) and thus the frequency becomes
dependent on the supply voltage. The potential on Pin 8 may
be swept down from V+ by (1/3 Vsupp - 2V).

RL

nn
ICL8038

'\tv

10k

100kn
'------------t-- 5mA), transistor betas and saturation voltages will
contribute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of 10,uA to
1mA. If pins 7 and 8 are shorted together, the magnitude of
the charging current due to RA can be calculated from:

RB

7

<

4

RL

6

9

nn

12

2

f\JV

ICL8038

8

T
FM
10

11

81k

C

V-orGND

A similar calculation holds. for Rs.
The capaCitor value should be chosen at the upper end of its
possible range.

(b)

v+
swJEEP
VOLTAGE

WAVEFORM OUT LEVEL CONTROL AND
POWER SUPPLIES

RA

4

The waveform generator can be operated either from a single
power-supply (10 to 30 Volts) or a dual power-supply (±5 to
±15 Volts). With a single power-supply the average levels of
the triangle and sine-wave are at exactly one-half of the
supply voltage, while the square-wave alternates between V+
and ground. A split power supply has the advantage that all
waveforms move symmetrically about ground.
The square-wave output is not committed. A load resistor
can be connected to a different power-supply, as long as the
applied voltage remains within the breakdown capability of
the waveform generator (30V). In this way, the square-wave"
output can be made TTL compatible (load resistor
connected to +5 Volts) while the waveform generator itself is
powered from a much higher voltage.

?

~RB
5

RL

6

ICL8038

>-8

10

::c

11

12

gc...+-o

n.rL

3

:-----0.

2

f---o

81k

V-orGND

Figure 3: Connections for Frequency Modulation (a) and Sweep (b)

5-195

18

ICLS038

O~DI!:.
r-------~------------------~~--~+15V

APPLICATIONS

v+'
RB

15k

RB
9

7

6

4

2 AMPLITUDE

IN914

ICLB038

8

10.

11

2

IN914
1+1~"""H--<>

11

Lr. +15V (+10V)

-15V

C.

•

~---------------+-----------+~--~v-

Figure 4: Sine Wave Output Buffer Amplifiers.
The sine wave output has a relatively high output impedance
(1kO Typ). The circuit of Figure 4·provldes buffering, gain and
amplitude adjustment. A simple op amp follower could also be
used.

STROBE

lOOk
OFF

C

ON

-1~V (-10V)

Figure 5: Strobe-Tone Burst Generator.
With a dual supply voltage the external capacitor on Pin 10 can be
shorted to ground to halHhe 8038 oscillation. Figure 5 shows a
FET switch, diode ANDed with an Input strobe signal to allow the
output to always start on the same slope.
.
+10v

"l'IN457
DUTY
CYCLE
lk
:

~.l~F

• 4.7k

4.7k-

;> 15k

~

,-5

4

6

9~

.IU1.

10k
FREQUENCY

,

10
20k

'----

ICLB038

8

:> ~15M~ ~

11

12

3~

21--::--2

"'"

$"~ISTORTI

• f'.0047~F

~ lOOk

ON
.
-10 V

Figure 6: Variable Audio Oscillator, 20Hz to 20kHz.
To obtain a 1000;1 Sweep Range on the 8038 the voltage across external resistors RA and RB must decrease to nearly zero. This requires that the
highest voltage on control Pin 8 exceed the voltage at'the top of RA and Rs by a·few hundred millivolts.
The Circuit of Figure 6 achieves this by· using a diode to lowerthe effective supply voltage on the 8038. The large resistor on pin 5' helps reduce
duty cycle variations with sweep.
HIGH
FREQUENCY
SYMMETRY

lN753A
(6.2V)

10kn

4.7kn -

lkn

100kn

lMn

4
lkn

5

LOW
FREQUENCY
SYMMETRY

6

SINE·WAVE
OUTPUT

ICLB038

">-+_""~+---I8

FUNCTION GENERATOR

./'\,.,

3

2~--~~+~--+------+~--~
11

10

12

50~F

.1SV

10kn
. OFFSET

100kn
3,900pF

SINE-WAVE
DISTORTION

L-----~-----4~--~~------------+-------------~~~5V

Figure 7: Linear Voltage Controlled Oscillator
The linearity of input sweep voltage versus output frequency can be significantly improved by using an op.amp as shown in Figure 7.

5·196

O~OIL

ICLS038
USE IN PHASE-LOCKED LOOPS

Second, the DC output level olthe amplifier must be made compatible to the DC level'required atthe FM input of the waveform
generator (pin 8,0.8 X V+l. The simplest solution here is to providea voltage divider to V+ (R1, R2asshown) iftheamplifierhasa
lower output level, or to ground if its level is higher. The divider
can be made part of the low-pass filter.
This application not only provides for a free-running
frequency with very low temperature drift, but it also has the
. unique feature of producing a large reconstituted sinewave
signal with a frequency identical to that at the input.
For further information, see Intersil Application Bulletin
A013, "Everything You Always Want~to Know About The
'8038."

Its high frequency stability makes the ICL8038 an ideal
building block for a phase-locked loop. In this application
the remaining functional blocks, the phase-detector and the
amplifier, can be formed by a number of available IC's (e,g.
MC 4344, NE 562, HA 2800, HA- 2820),
In order to match these building blocks to each other, two
steps must be taken, First, two different supply voltages are
used and the square wave output is returned to the supply of
the phase detector. This assures that the VCO input voltage
will not exceed the capabilities of tM phase detector. If a
smaller VCO signal is required, a simple resistive voltage
. divider is connected between pin 9 of the waveform
generator and' the VCO input of the phase-detector.

v++

I

<

~. gy~TL~ ~
~ FREQUENCY;':
ADJUST

R1

4

FMBIAS
0----

v+

<;-

INPUT

0----

PHASE DETECTOR

I---

AMPLIFIER

DEMODULATED
FM

I

R2

FM
SWEEP
INPUT

'VVV
-I~
'----y--.:.J

LOW-PASS
FILTER

f---o

Vv
SINE WAVE
OUT

ICLB03B

s'
10

*

11
TIMING
CA!'.

Figure 8: Waveform Generator Used as Stable veo in a Phase-Locked Loop

5-197

TRIANGLE
OUT

6
3

SQUARE
WAVE
OUT 9

>

VCO
IN

5

7

21--0

'\IV

11--0

SINE WAVE
ADJ.

12

~ SINE

;,:

WAVE
ADJ.

ICL,8043
Dual Fet Input OpAmp

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•

The ICL8043 contains two FET input op amps, each'similar in
performance to the ICL8007, The inputs and outputs are fully
short circuit protected, ,and no latch~up problems exist.
Offset nulling is accomplished by using a single pot (for each
amplifier> connecte~ to the positive supply . voltage, The
devices have exceilent common mode rejection,

Very low Input current - 1pA
High slew rate - 6V/p.s
Internal frequency compensation
Low power dissipation - 135mW typ
Monolithic construction

EQUIVALENT CIRCUIT (One Side)

OFFSET VOLTAGE NULL CIRCUIT

--

INPUT
OFFSET NULL

v+

7

~-+--o OUTPUT

INPUT

10

PIN CONFIGURATION

ORDERING INFORMATION

TYPE

ORDER.
' PART NUMBER

8D43M

ICL8043MJE

8D43C

ICL8D4~CPE

8D43C

ICL8043CJE

PACKAGE

16 PIN DIP,(TOP VIEW)

TEMPERATURE
RANGE

--55·C to 125·C
Ceramic
16 Pin DIP
Plastic
D·C to 70·C
16 Pin DIP'
D·C to 7D·C
Ceramic
16 phI DIP
(oulline dwgs JE. PEl

5·198

ICLS043

O~OIb

ABSOLUTE MAXIMUM RATINGS
Sl)pply Voltage ••••••••••.•.•••..•.•••••••.•••••••••••••••••••••••••••••• ±18V
Internal Power Dissipation (Note 1) ..................................... 500mW
Differential Input Voltage .................................... .-.'............ ±30V
Input Voltage (Note, 2) .................................................... ±15V
Voltage between Offset Null and V+ ••••••••••••••••••••••••••••••••••••••• ±0.5V
Storage Temperature Range .................................... --u5,oC to +150°C
Operating Temperature Range
8043M •••••••••••••••••••••••••.••••••••••••••••.•.••...••.. --55°6 to +125°C
8043C .. : ...................................................... O°C to +70°C
Lead Temperature (Soldering, 60 sec,) •••.•.•••••.•...••••...•.•••.•••••• 300° C
. Output Short-Circuit Duration ........................................ Indefinite

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
'
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTES:
1. Rating applies for case temperatures to 125°C; derate linearly at 9mW/oC for ambient temperatures abol(e +95°C.
2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.

ELECTRICAL CHARACTERISTICS

(Vsupp = ±15V unless otherwise specified)

I

SYMBOL
CHARACTERISTICS
CONDITIONS
I MIN.
The following specifications apply forTA = 25°C:
, Rs < 100kO
Input Offset Voltage
Vos
Input Offset Current
los
.Input Current (either input)
liN
Input Resistance
RIN
Input CapaCitance
CIN
Av
Large Signal Voltage GaIn
RL > 2kO, Vau! =±10V 50,000
Output Resistance
Ro
, Isc
Output ,Short-Circuit Current
Isupp
Supply Current (Totall
,
Pd
Power Consumption
SR
Slew Rate
GBW
Unity Gain E\andwidth
t,
Transient Response (Unity Gain) CL < 100pF, RL = 2kO
Risetlme
Overshoot

I

8043M
TYP.
10
0.5
2.01
106
2.0

I

I

MAlt

I

MIN.

20

I

'8043C,
TYP.
20
0.5
3.0
106
2.0

20

I

I

MAX.
50
50

20,000
75
25
4.5
135
6.0
1.0

'75
25
4.5
135
6.0
1.0

6
180

300
10

6.8
204

I

UNITS
mV
pA
pA
MO
pF
VN
0
mA
mA
mW
VI,.s
MHz

300
10

ns
%

±12

V
dB

The following speCifications apply 'for 0° C < TA < +70° C (8043C), -55° C < TA < +125° C (8043M):
dVIN
CMRR
PSRR
Av
±Vo

Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing

Vos
liN

Input Offset Voltage
Input Current (either input)

dVos/dT

Average Temperature Coefficient
of Input Offset Voltage

±10
70

±12
70

25,000
±12
±10

RL> 10kO
RL>2kO
TA=+125°C
TA ,;,+70°C

±10
70

90

±14
±13
15
2.0

300

70
15,000
±12
±10

30
15

90'

±14
±13
30
50 •

75
5·199

600

,.VN

60

VN
V
V
mV
nA
pA
,.VloC

175
75

ICLS043
TYPICAL PERFORMANCE CURVES
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY
106
100

f'.

Z 104

C

~

103

"i:!

102

!i!

10

I

,

~

..J

~ 40

I,

Vsupp = ±15V !-TA=+25"C

""
""

~

32

!;

24

~

~

~~~p~ = I±~~V
+25"C
RL'= 10kn

-

24r-~---r--~--+_~r_~

20r-~90=%~~~---+--~~

~ 16r-~_irr--~--+_--r_~

~,12r-~-~/~~---+--~~

5

8 -1~
4

I
0

.5

1.0
1.5
TIME (ps)

2.0

10k

100k

1M

0123456789
TIME (ps)

2.5

OUTPUT SWING AS A FUNCTION
OF SUPPLY VOLTAGE
20

fQ

TAI= 25 C
TL = 2kp

@)

~

103

0-

0::l

20

Z

r--

40

60' 80
100 120
TEMPERATURE ("C)

o

140

v.~

15

<

.s

/ /
/,/
!!l 10 - -POSITV
/NEGATIVE- 5
0.
>
l//
!; 5
...~
/

104 L........L..---J__.l.......L......l.__.l........L.--I
o
±5
±10
±15
±20

zW

!zw

4

!S

3

>~

2

U

...

±10

--

±15

o
z
, rJ 10.0

w

!i!W

102

105

i'

z

1 Mn

Rs

::l

100

1k

.Y

i---'"

K

100k

100

.......

"'"

BANDWIDTH
- 0.1 Hz TO 1 kHz

w 1.0

II:
'0-

~ 0.1

10k

FREQUENCY (Hz)

5·200

~~~~~~ci~oo kHz V

~

Rs -son

I
10

OF SOURCE RESISTANCE

UJ

103

~

±20

±15

WIDEBAND'~OISE AS AFUNCTION

>
.;:; 100
w.

IIII
TEMPERATURE ("C)

±10

SUPPLY VOLTAGE

r

o
65

±5

±20

¥

<.:s.

oz

25

f..-"

1000

UJ

-15

3

::l
UJ

INPUT VOLTAGE NOISE AS
A FUNCTION OF F~EQUENCY

= ±15V

iil
~5

...>-...
..J

"04



-

. ,0.

8
, 0

4

"i:!

1\

~

100" 1k 10k 100k 1M 10M

~!U:';;.~15V _

~
w

.. 16

-i

VOLTAGE FOLLOWER LARGESIGNAL PULSE RESPONSE

Til =

o

\

10

OUTPUT VOLTAGE SWING AS
A FUNCTION OF FREQUENCY

,1k

10k

I

I

100k

1M

I
10M 100M

SOURCE RESISTANCE (n)

O~OIb

ICLS043
CHANNEL SEPARATION

Channel separation or crosstalk is measured using the circuit of Figure 1. One amplifier is driven so that its output swings±10V;
the signal amplitude seen in the other amplifier (referred to the input) is then measured. Typical performance is shown in Figure
2.
Channel Separation = 20 log (VOUT(A))
VIN(B)

CHANNEL SEPARATION

11 0

"
\

100
RL

iii"

~

90

-

z

0

~
a:

«0.

"'

0

R

!'\

=2k

Ih=12r c
=10k
RL

i\
~

70

til

60

~

50

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 1

Figure 2

Following this nulling operation, A1 is used as a normal
amplifier while the voltage necessary to zero its offset
voltage is stored on the integ rator comprised of A2 and C,.

APPLICATIONS
Applications for any dual amplifier fall into two categories.
There are those which use the two-in-one package concept
simply to save circuit-board space and cost, but more
interesting are those circuits where the two sides of the dual
are used to complement one another in a subsystem
application. The circuits which follow have been selected on
this basis.

The advantage of this circuit is that it allows chopper
amplifier performance to be achieved at one-tenth the cost.
The only limitation is that during the offset nulling mode, A1
is disconnected from the input. However, in most data
acquisition systems, many inputs are scanned sequentially.
It is fairly simple to synchronize the offset nulling operation
so that it does not occur when that particular amplifier is
being "looked at". For the component values shown in Figure
3, and assuming a total leakage of 50pA at the inverting input
of A2, the offset voltage referred to the input of A1 will drift
away from zero at only 40MV/sec. Thus, the offset nulling
information stored on C, can be "refreshed" relatively
infrequently. The measured offset voltage of A, during the
amplification mode was 11MV; offset voltage drift with
temperature was less than 0.1MV/oC.

AUTOMATIC OFFSET SUPPRESSION
CIRCUIT
The circuit shown in Figure 3 uses one amplifier (A1) as a
normal gain stage, while the other (A2) forms part of an offset
voltage zeroing loop. There are two modes of operation
which occur sequentially; first, an offset null correction
mode during which the offset voltage of A1 is nulled out.

+5V

130k!!
1k!!

C,
SW3*

16

LOGIC
INPUT

_10k!!

/

/

4/__________~~__________~/

•

*SW" SW2, & SW3 ARE ALL PART OF A SINGLE IH5043 CMOS ANALOG
SWITCH CONNECTED AS SHOWN
IN FIGURE 38

/

Figure 3A.

5·201

Flgure-3B.

+15V

1:1

O~OIL

ICLS043
STAIRCASE

~ENERATOR

The circuit shown in Figure 4 is a high input impedance
version of the so-called "diode pump" or staircase generator.
Note that charge transfer takes place at the negative-going
edge of the input-signal.
. The most common application for staircase generators is in
low cost counters. 'By resetting the capacitor when the
output reaches a predetermined level, the circuit may be
made to count reliably up to a maximum of about 10. A '
straightforward circuit using a LM311 for the level detector,
and a CMOS analog gate to discharge the capacitor, is
shown in Figure 5. An important property of this type of

counter is the ease with which the count can be changed; it is
only necessary to change the voltage at which the
comparator trips. A low cost A-D converter can also be
designed using the same principle since the digital count
between reset periods is directly proportional to the analog
voltage used as a reference for the comparator.
A considerable amount of hysteresis is used in the,
comparator shown in Figure 5. This ensures that the
capacitor is completely discharged during the reset period.
In a more sophisticated circuit, a dual comparator "window
detector" could be used, the lower trip point set close to
ground to assure complete discharge. The upper trip point
could then be adjusted independently to determinethepulse
'count.

r-, r

fJ

r. ~

-- - -

10100

~

LOW LEAKAGE
DIODE PAIR

~

- ,......r

;.....J

VOUT
}

- - - - HORIZONTAL

~

(2v/DIV)

VIN
}

(5v/DIV)

50mS/DIV

Figure 4

IH5042

1kfl

~

100kfl

--- -- ---

"r'

1/
--

.;.r

--- ro--

~

/

10kfl

Your VAEF

Figure 5

5-202

VOUT

.,-A

/'

}

(5V/DIV)

VI~
--- ~- ~-- ---- } (5v/DIV)

HORIZONTAL

10100
LOW LEAKAGE
DIODE PAIR

~

~

~

200mS/DIV

U~UIL

ICLB043
SAMPLE & HOLD CIRCUIT
Two important properties of the 8043 are used to advantage
in this circuit. The low input bias currents give rise to slow
output decay rates ("droop") in the hold mode, while the high·
slew rate (6V1p.S) improves the. tracking speed and the
response time of the circuit. See Figure 6. . .
The ability of the circuit to track fast moving inputs is shown.
in Figure 7A. The upper waveform is the input (10Vldiv), the
lower waveform the output (5V1div). The logic input i.s high.

Actual sample and hold waveforms are shown in Figure 78.
The center waveform is the analog input, a ramp moving at
about 67V1ms, the lower waveform is the logic input to the
sample & hold; a logic "1" initiates the sample mode. The
upper waveform is the output, displaced by about 1 scope
division (2V) from the input to avoid slJperimposing traces.
The hold mode, during which the output remains constant, is
clearly visible. At the beginning of a sample pe~iod, the
output takes about 8p.sec to catch up with the input, after
which it tracks until the next hold period.

+15V
-15V

10
OUTPUT

16

ANALOG
INPUT

51n
-15V

4

13

5

12 +5V

-15V

I

10,000 pF
POLYSTYRENE

o

LOGIC IN~UT

11 +15V

10

+3V = > SAMPLE MODE
OV = ? HOLD MODE

IH5043

Figure 6

""

~

I

It.

r
1\

r

\

............

t\

1"-- ~

..........

L\r.

'!o..

~ ......

~

TOP: INPUT (10VlDIV) .
BOTTOM: OUTPUT (5V1DIV)
HORIZONTAL: 10~./DIV

TOP: 2V1DIV
CENTER: 2V1DIV
BOTTOM: 10V/DIV
HORIZONTAL: 10~S/DIV

Figure 7A

Figure 78

5.-203

............

i'"' i"oo.

D~DIl,

ICLS043
INSTRUMENTATION AMPLIFIER
A dual FET input operational amplifier is an attractive
component around which to build an instrumentation
amplifier because of the high input resistance. The circuit
shown in Figure 8 uses the popular triple op-amp approach.
The output amplifier is a High Speed 741 (741 HS, slew rate
gu'aranteed ?0.7VIp.s) so as to utilize the high slew rate ofthe
8043 to the, maximum extent. Input resistance of the circuit
(either input, regardless of gain configuration) is in excess of
1012 ohms.
'-

Common mode rejection is largely determined by the
matching between R4 and Rs, and Rs and R7. In applications
where offset nulling is required, a single potentiometer can
be connected as shown in Figure 9.

For the component values shown, the overall amplifier gain
is 200 (front end gain = 2Rl + R2. back end gain, = Rs/R4l.
R2

For more information on FET input operational amplifiers,
seelntersil Application Bulletin A005 "The 8007: A High
Performance FET-input Operational Amplifier."

~.5k

Another popular circuit is given in Figure 10. In this case the
gain is 1 + Rl/R2, and the CMRR determined by the match
between Rland R4, R2 and R3.

Ib

Figure ,8

Figure 9

CHIP TOPOGRAPHY
A,

"

I"

,087"

----,...--)o~1
16

r

ALL RESISTORS .1'10

,087"

( )

Figure 10

6

5-204

,

ICL8048, ICL8049
Monolithic Log Amplifier
Monolithic Antilog Amplifier
FEATURES·
• 1/2% Full Scale Accuracy
• Temperature Compensated O°C to 70°C
• Scale Factor 1V /Oecade, Adjustable
• 120dB Dynamic Current Range (8048)
• GOdB Dynamic Voltage Range (8048 & 8049)
• Dual FET-Input Op-Amps

GENERAL DESCRIPTION
The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is
nominally designed to provide 1 volt of output for each
decade change of input. For increased flexibility, the scale
factor, reference current and offset voltage are externally
adjustable.
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
l-'t9lt change at the input.

PIN CONFIGURATION
(outline dwgs DE, PEl

8048 SCHEMATIC DIAGRAM
VREF >--'\NV-O jlR£f
16

Your
10

GNO

GROUND

1

NO CONNECTION

3

Al OFFSET NULL

4

8048

0--+--'-1

At OUTPUT

7

NO CONNECTION

8

15
GAIN
At OUTPUT

8049 SCHEMATIC DIAGRAM

A2 INPUT

14

t,IQUT
16
GA1~,

GAIN
Al OFFSET NULL

4

13

A2 OFFSET NULL

Al OFFSET '\lUll

5

12

A7 OFFSET NULL

9

NO CONNECTION

10

Your

15
GROUND

Al INPUT,

Al OUTPUT

5·205

Al OUTPUT

7

NO CONNECTION

8

ICL8048
MAXIMUM RATINGS
Supply Voltage
lin (Input Current)
Iref (Reference Current)
Voltag~ between Offset Null and V+
Power Dissipation

±18V
2'mA
2mA
±O.S V
7S0mW

Operating Temperature Range
Output Short Circuit Duration
Storage Temperature.Range·
Lead Temperature (Soldering, 60 sec.)

O°Cto +70°C
Indefinite
. -6SoC to +12SoC
300°C

ELECTRICAL CHARACTERISTIC (Note 1)
8048BC
PARAMETER

CONDITION

MIN.

TYP.

8048CC
MIN.

MAX.

TYP.

MAX.

UNITS.

Dynamic Range
lin (InA-ImA)

Vi~ (10mV-l0V)

RIN = 10kn

Error, %.of Full Scale

TA =.25°C, liN = 1 nA to 1 mA

Error, % of Full Scale

TA=' O°C to +70°C,

120

120

60

60
.20
..60

dB
dB

0.5

.25

1.0

%

1.25

.80

2.5

%

liN = lnAto lmA
Error, Absolute Value

12

30

14

60

mV

TA = O°C to +70°C,
,liN = lnAto lmA

36

75

50

150

mV

Temperature Coefficient of VOUT

liN = 1 nA to 1 mA

0.8

Power Supply Rejection Ratio

Referred to Output

2.5

Offset Voltage (AI & A2)

Before Nulling

15

Wideband Noise

At Output, for liN '= IOOIiA

250

Output Volta'ge Swing

RL = 10kf!

±12

±14

RL =2kf!

±10

±13

TA = 25°,C, liN = InAto lmA

Error, Absolute Value

,

Power Consumptioh

150

Supply Current

5

mV/oC
mV/V

0.8
2.5
25

,

±12

15
250
±14 .

±10

±13

200,
. 6.7

50

mV
IIV(RMS
V

"

V

150

200

mW

5

6.7

mA

NOTE 1: Unless otherwise noted, specifications apply for Vs = ± 15V, T A = 25°C, IREF = 1 mA, scale factor adjusted for IV/decade.

TRANSFER FUNCTION
FOR CURRENT INPUTS

SMALL SIGNAL BANDWIDTH
AS A FUNCTION OF INPUT
CURRENT

TRANSFER FUNCTION FOR
VOLTAGE INPUTS
tOOk

'REF" IrnA

.~

'N

=
:r

00

i0

w

z

~
o
>

0-

~:>

10k

;:;

Ik

V

..I

"
Z

-2

'"

in

:::

-4

o

~~,-:,:::-o-,o"""=-,o""'=-,o"-=-,-lO-'=-'O"-=-,-'0"'"':--'10

INPUT VOLTAGE

MAXIMUM ERROR VOLTAGE
ATTHE OUTPUT AS A
FUNCTION OF INPUT CURRENT

MAXIMUM ERROR VOLTAGE
AT THE OUTPUT AS A
FUNCTION OF INPUT VOLTAGE

200

I I

175

8048 CC 10°C to ?O"C)

'50

I I

'25

100

ae (O~C to 70"C)
8048 cc (25~CJ

, 75

108 10 7

I

106,

105

434

10.4

INPUT CURRENT (AMPS)

IRS' 10kill

o
10mV

II
lOOmV

IV

INPUT VOLTAGE

5·206

10-3

lOV

= 10910 e
ilVOUT--v,;;-

.~%

100

"
"
I

0.1

B048 BC 125'C}

10-3

10-5

VOLTAGE GAIN'" .o.V,N

r-.;

8048 BC IO°C to locei

25

10-7

1000

50

8048 BC 125"CI

I

"-

10-9 .

8048 cc 12S"CI .

50
25

R'N "10kU

8048 cc IO"C to 70"e)

150

V

SMALL SIGNAL VOLTAGE GAIN
AS A FUNCTION OF INPUT
VOLTAGE FOR RS = 10 kf!

10

8048

75

1/

\,

V

INPUT CURRENT lAMPS}

125

I I

'00

10 9

--'10
10-11

J

INPUT CURRENT (AMPS)

o

100

ill"

-6

J

.01
1mV

10mV

l00nlV

INPUT VOLTAGE

"
IV

10V

U~UIb

ICL8049
MAXIMUM RATINGS

±lBV
±15V
2mA
±0.5V
750mW
O°C to +70°C
Indefinite
. -65°C to +150°C
300°C

Supply Voltage
Vin (Input Voltage)
Iref (Reference Current)
Voltage between Offset Null and V+
Power Dissipation
Operating Temperature Range
Output Short Circuit Duration·
Storage TerilPerature Range
Lead Temperature (Soldering, 60 sec.)

ELECTRICAL CHARACTERISTIC (Note 1)
MIN.

CONDITION

PARAMETER
Dynamic Range (VOUT)

VOUT = 10mV tei 10V

Error, Absolute Value

TA = 25°C, OV;O;VIN;O;3V
T A = ODC to +70DC,

Error, Absolute Value

B049BC
TYP. MAX.

MIN.

60

8049CC
TYP. MAX.

UNITS
dB.

60!
3

10

5

25

20

75

30

150

,

mV
mV

OV;O;VIN;O;3V
Temperature Coefficient, Referred to VI N

VIN = 3V

Power Supply Rejection Ratio

Referred to Input, for

0.38

0.55

mV/DC

2.0

2.0

p.VIV

VIN = OV
Offset Voltage (AI & A2)

Before Nulling

15

Wideband Noise

Referred to I nput, for

26

Out·put Voltage Swing

RL = 10kll

±12

±14

±12

RL = 2kll

±10

±13

±10

15

25

50

26

mV
p.V(RMS)

I

VIN = OV

Power Consu mption

±14
±13 .

V
V

150

200

150

200

mW

5

6.7

5

6.7

mA

Supply Current

NOTE 1: Unless otherwise noted, specifications apply for Vs = ±15V, TA.= 25 DC, IREF = lmA, scale factor adjusted for 1 decade (out) per
volt lin!.
.
MAXIMUM ERROR VOLTAGE
REFERRED TO THE INPUT AS A
FUNCTION OF VIN

TRANSFER FUNCTION
(VOUT AS A FUNCTION OF VIN)
10

10

\
r-- r-- \\\~-

hR~F imA
0

I

-

r-- r-- \~~~~~ \'

\\

,~\~

ea
,1Q~

\1

:;?~?~\

0.1

,'-

."

~

\\ \\
\\ \

.01

.001
-4

-3

-2

-1

0

+1

+2

cor:1":C>.Jf::J':.,o.,'{FJ

,;'" 'tlS049CC

\
+3

I
+4

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

SMALL SIGNAL BANDWIDTH
AS A FUNCTION OF
INPUT VOLTAGE
10M

F'RE~

1M

lOOk

0

SMALL SIGNAL VOLTAGE GAIN
AS A FUNCTION OF
INPUT VOLTAGE
-100

lml

rlREF""mA

-23

-10

"

~

. f--

/

"- r-....

, -1

"-0.1

10k

1k

(2~)

8049 Be (25°C)

-0.01

o
INPUT VOLTAGE (V)

"

"r-....

o
INPUT VOLTAGE (V)

5·207

ICL80~8, ICL8049
THEORY OF OPERATION

value of 15.9kn at 25°C, and its temperature coefficient is
carefully designed to provide the necessary compensation.
Resistor R2 is external and should be a low T.C. type; it
should have a nominal value of lkn to provide 1 volt/
decade, and must have an adjustment range of ±2Q% to
allow for production variations in the absolute value of R 1.

The 8048 relies for its operation on the well-known exponential relatiQnship between the' collector current and the
base-emitter voltage of a transistor:
,IC= Is[e9VSEAT -lJ

(1)

For base-,emitter voltagl1s greater than 100mV; Eq. (1)
becomes
qVSE/ .
(2)
IC=ISe
/kT
From Eq_ (2), it can Be' shown that for' two identical
transistors operating at different collector currents, the
VSE difference (6VSE) is given by:
6VSE = -2_303 x kqT log

10

[IcljrC2J

OFFSET AND SCALE FACTOR ADJUSTMENT,
A log amp, unlike an op-amp, Cannot be offset adjusted by
simp'ly grounding the input. This is because the log of zero
approaches minus infinity; reducing the input current to
,zero starves 01 of collector current and open the feedback
loop around Al. Instead, it is necessary to zero the offset
voltage of ,A 1 and A2 separately, and then to adjust the
scale factor. Referring to Fig. 1, this is done as follows:
1) Temporarily connect a 10kn resistor (RO) between
pins :2 and 7. With no input voltage, adjust R4 until
the output of Al (pin 7) is zero. Remove RO.
Note that for a current input, this adjustment is not
necessary since the offset voltage of Al does not
cause any error for current-source inputs.

(3)

Referring to Fig_ 1, it is clear that the potential at the
collector of 02 is equal to the 6VSE between 01 and 02.
The output voltage is 6VSE multiplied by the gain of A2:
VOUT =

5

'The

-2_30~(R~2+ R2)(kD log 10 [IIN(IREFJ (4)

expressio~

2.303 x kqT has a numerical value of 59mV

at 25°C; thus in order to generate 1 volt/decade. at the
OUtput, the ratio (Rl + R211R2 is chosen to be 16.9_ For
this scale' factor to hold constant as a function of temperature, the (R 1 + R211R2 term must have a l/T characteristic
to compensate for kT /q.
.
In the 8048 this is achieved by making R 1 a thin film
resistor, deposited on the monol1thic chip, It has a nominal

,

2) Set liN = IREF = lmA. AdJust R5 such that the
output of A2 (pin 10) is zero.

3) Set liN = lilA, IREF =lmA. Adjust R2 for
VOUT = 3 volts (for a 1 volt/decade scale factor)
or 6 volts (for a, 2 volt/decade scale factor),.
Step #3 determines the scale factor. Se~ting liN = lilA
. optimizes the ,scale factor adjustment over a fairly wide
dynamic range, from 1rnA to 1 nA. Clearly, if the 8048 is to
be .used for inputs which only span the range lOOIlA to
lmA, it would be better to set liN ,= 100llA in Step #3.'
Similarly, adju~tment for other scale factors would require
different II Nand VOUT v,alues.

FIGURE 1. 8048 OFFSET AND SCALE FACTOR ADJUSTMENT

5-208

ICL8048, ICL8049
THEORY OF OPERATION

For voltage references equation 7 becomes

The 8049 relies on the same logarithmic properties of the
transistor as the 8048. The input voltage forces a specific
t.VBE between 01 and 02 (Fig. 2). This VBE difference
is converted into a difference of collector currents by the
transistor pair. The equation governing the behavior of the
transistor pair is derived from (2) on Page 3 and is as follows:
IC1/ =
[qt.VBE/ ]
/11,
exp
/kT
C2

r-=!!.L

VOUT = VREF x ROUT exp
x q VIN ]
RREF
UR1 + R2· kT

OFFSET AND SCALE FACTOR ADJUSTMENT
As with the log amplifier, the antilog amplifier· requires
three adjustments. The first step is to null out the offset
voltage of A2. This is accomplished by reverse biasing the
base·emitter of 02. A2 then operates as a unity gain buffer
with a grounded input. The second step forces VIN = 0;
the output is adjusted for VOUT = 10V. This step essen·
tially "anchors" one point on the transfer function. The
third step applies a specific input and adjusts the output to
the correct voltage. Th is sets the scale factor. Referring to
Fig. 2, the exact procedure for 1 decade/volt is as follows:

(5)

When numerical values for q/kT are put into this equation,
it is found that a t.VBE of 59mV (at 25°C) is required to
change the collector current ratio by a factor of ten. But
for ease of application, it is desirable that a 1 volt change
at the input generate a tenfold change at the output. The
required input attenuation is achieved by the network com·
prising R1 and R2. In order that scale factors other than
one decade per volt may be selected, R2 is external to the
chip. It should have a value of 1kn, adjustable ±20%, for
one decade per volt. R1 is a thin film resistor deposited on
the monolithic chip; its temperature characteristics are
chosen to compensate the temperature dependence of
equation 5, as explained on Page 3.

1) Connect ·the input (pin #16) to +15V.
This
reverse biases the base·emitter of 02. Adjust R7
for VOUT = OV. Disconnect the input from +15V.
Adjust R4 for
2) Connect the input to Ground.
VOUT = 10V. Disconnect the input from Ground.
3) Connect the input to a precise 2V supply and adjust
. R2 for VOUT= 100mV.

The overall transfer function is as follows:
IOUT/
[-R2
qVINl
/IREF= exp ~R1 + R2) x

(6)

kTJ

The procedure outlined above optimizes the performance
over a 3 decade range at the output (i. e., VOUT from ~
10mV to 10V). For a more limited range of output
voltages, for example 1V to 10V, it would be better to
use a precise 1 volt supply and adjust for VOUT = 1V.
For other scale· factors and/or starting points,· different
values for R2 and RREF will be needed, but the same basic
procedure applies.

Substituting VOUT = lOUT x ROUT gives:

r

-R2
qVINl
VOUT = ROUT IREF exp liR1 + R2) x

k"TJ

(7)

VREF
(+15V)

R3

15kn

VINO'-----,

R6
lOOkn

R5
15U1.

(8)

680.0.

ROUT

(lOW
T.e.)

10kn

lkn
VOUT

V+

8049
FIGURE 2

5·209

O~OIb

ICL8048, ICL8049
APPLICATIONS INFORMATION
Frequency Compensation

Scale Factor Adjustment
The scale factor adjustment procedures outlined on Page 3
(8048) and Page 5 (8049) are primarily directed towards
setting up 1 volt (LWOUT) per decade (b.IIN or b.VIN) for
the log amp, or one decade (b.VOUT) per volt (b.VIN) for
the antilog amp.
This corresponds to K = 1 in the respective transfer func·
tions:
Log Amp: VOUT=-K log

1O['I~REF]

Although the op-ampsin both the 8048 and the 8049 ,are
compensated for unity gain, some additiona I frequency
compensation is required. This is because the log transistors
in the feedback loop add to the loop gain. In the 8048,
150 pF should be connected between Pins 2 and 7 (Fig. 1).
In the 8049, 200 pF between Pins 3 and 7 is recommended
(Fig. 2).

(9)

Error Analysis

yi<

Antilog Amp: VOUT=ROUTIREF lO- Vlf

(10)

By adjusting R2 (Fig. 1 and Fig. 2) the scale factor "K" in
equation '9 and 10 can be varied. The effect of changing K
is shown graphically in Fig. 3 for the log amp, and Fig. 4,
for the antilog amp. The nominal value of R2 required to
give a specific value of K can be determined from equation
11. It should be remembered that Rl has a ±20% tolElrance
in absolute value, so that allowance shall be made for ad·
justing the nominal value of R2 by ±20%.
941
R2 = (K-.059)

(11 )

n

EFFECT OF VARYING "K" ON
THE LOG AMPLIFIER
12

in
~

1,,\

10

0

~
w

"'- .........

-

'"

'~"

0

>

."
..........

~

>:::>

i':
:::>

,0

JAEF=lmA

Performing a meaningful error analysis of a circuit con-,
taining log and antilog amplifiers is more complex tllan
dealing with a similar circuit involving only op-amps. In
this data sheet every effort has been made to simplify the
analysis task, without in any way compromising the validity,
of the resultant numbers.
The key difference in making error calculations in log/
antilog amps, compared with op-amps, is that the gain of
the former is a function of the input signal level. Thus, it
is necessary; when referring errors from output to input, or
vice versa, to check the input voitage'level, then determine
the gain of the circuit by referring to the graphs given on
Pages 2 and 4.
The various error terms in the log amplifier, the 8048, are
referred to the output (RTO) of the device. The error
terms in -the antilog amplifier, the 8049, are referred !o
the input (RTI) of the device. The errors are expressed in
this -way because in'the majority of systems a number of
log amps interface with an antilog amp, as shown in Fig. 5.

~

~I"

~ r:::: ~

ERROR DUE TO A (ATO)
"X mV

-2
10-10 10-9 10-8 10-7 10-6 10-5 10-4 ',,10- 3

INPUT CURRENT (AMPS)
OUTPUT

FIGURE 3

EF FECT OF VARYING "K" ON
THE ANTILOG AMPLIFIER
10

~

IREF'" lmA
ROUT" lOkn

---

,\ 1'-

~

"\ i\

w

'"'"
C;

0

'\

"-

>

>-

:::>

i':
:::>

,1

r---- ~j ~~ ~

F= ~~~-

0

,01

o

,

~-

FIGURE 5

--

- - I---

'\;:;- r----

,--

~

\

"

'\

It is very straightforward to estimate the system error at
node (A) by taking the square root of the sum,of-the
squares of the errors of 'each contributing block.
"

, INPUT VOLTAGE IV)

Total Error

FIGURE 4

5-210

=vix2 +

y2 + z2

at (A)

ICL8048, ICL8049
or negative IREF to either circuit will cause malfunction,
and if maintained for long periods, would lead to device
degradation. Some protection can be provided by placing a diode between pin 7 and ground.

If .required, this error can be referred to the system output
,through the voltage gain of the antilog circuit, using the
voltage gain plot on Page 4.
.
The numerical values of x, y, and z in the above equation
are obtained from the maximum error voltage plots given
on Pages 2 and 4. For example, with the 8048BC, the
maximum error at the output is 30mV at 25°C. This
means that the measured output will be within 30mV of
the theoretical transfer function, provided the unit has
been adjusted per the procedures on Page 3. Fig. 6 iIIus·
trates this point.
To determine the maximum error. over the operating temperature range, the 0 to 70° C absolute error values given
in the table of electrical characteristics should be used. For
intermediate temperatures, assume.a linear increase in· the
error between the 25°C value and the 70°C value.

SETTING UP THE REFERENCE CURRENT
In both the 8048 and the 8049 the input current reference
pin (lREF) is not a true virtual ground. For the 8048, a
fraction of the output voltage is seen on Pin 16 (Fig. 1).
This does not constitute an appreciable error provided
VREF is much greater than this Voltage. A 10V or 15V .
reference satisfies this condition. For the 8049, a fraction
of the input voltage appears on Pin 3 (Fig. 2). placing a
similar restraint on the value.of VREF.
. Alternatively, IR EF can be provided from a true current
source. One method of implementing such a current source
is shown in Fig. 7.

LOG OF RATIO CIRCUIT, DIVISION

For the antilog amplifier, the only difference is that. the
error refers to the input,.i. e., the horizontal axis. It will
be noticed that the maximum error voltage of the 8049,
over the temperature range, is strongly dependent on the
input voltage. This is because the output amplifier, A2,
has an offset voltage drift which is directly transmitted to
the output_ When.this error is referr.ed to the input, it must
be divided by the voltage gain, which is input voltage
dependent. At VIN = 3V, for example, errors at the
output are multiplied by 1/.023 (= 43.5) when referred
to the input.

The 8048 may be used to generate the log of a ratio by
modulating the IREF input. The. transfer function remains
the same, as defined by equation 9: .

It is important to note thatboth the 8048 and the'8049
require positive values of IREF' and the input (8048) or
output (8049) currents (or voltages) respectively must
also be positive. Application of negative liN to the 8048

To avoid the problems caused by the I REF input not b,eing
a true virtual ground (discussed in the previous section). the
circuit of Fig. 7 is again recommended if the I REF input
is to be modulated.

(9)

VOUT = -K 10910 [II%EFJ

Clearly it is possible to perform division using just one
8048, followed by an 8049. For multiplication, it is
generally necessary to use two log amps, summing their
outputs into an a[ltilog amp.

TRANSFER FUNCTION FOR
CURRENT INPUTS

+lSV

R,

2N2219

10kO
-8L-~~

__~~__~~~

10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3

INPUT CURRENT lAMPS)

Actual output will lie
within shaded area for
8048 BC at 25°C

lREF
PIN 16 ON 8048)
( TO
TO PIN 3 ON 8049

FIGURE 7

FIGURE 6

5-211

&l

ICL8048, ICL8049
DEFINITION OF TERMS
In the definitions which follow, it will be noted that the
various error terms are referred to ~he output. of the log

amp, and to the input of the antilog amp. the reason for
this is explained on Page 6.

DYNAMIC RANGE The dynamic range of the 8048 refers

TEMPERATURE COEFFICIENT OFVOUT OR VIN.' For
the 8048 the temperature cot;lfficient refers to the drift
with temperature of VOUT for a constant input current.

to the range of input voltages or currents over which the
device is guaranteed to operate. For the 8049 the dynamic
range refers to the range of output voltages over which the
device isgiJaranteed to operate.
The absolute error is a
measure of the deviation from the theoretical transferfunc·
tion, after performing the offset and scale factor adjustments as outlined on Pages 3 (8048) or 5 (8049). It is
expressed in mV and referred to the linear axis of the
transfer function plot. Thus, in the case of the 8048, it is
a measure of the deviation from the theoretical output
voltage for a given input current or voltage. For the 8049
it is a measure of the deviation from the theoretical input
voltage required to generate a specific output voltage.

Fo'r the 8049 it is the temperature drift of the input voltage
required to hold constant value of VOUT.

a

ERROR, ABSOLUTE VALUE

The absolute error specification is guaranteed over the
dynamic range.
ERROR, % OF FULL SCALE The error as a percentage of

'full scale can be obtained from the following relationship:
100 x Error, absolute value
Error, %of Full Scale = - - - - - ' - - - - - Full Scale Output Voltage

The ratio of the
voltage change in the linear axis of the transfer function
(VOUT for the 8048, VIN for the 8049) to the change
in the .supply voltage, assuming that the log axis is held
constant.

POWER SUPPL Y REJECTION RA TlO

WIDEBAND NOISE For the 8048, this isthe ~oise occur-

ring at the output under the specified conditions. In the
case of the 8049, the noise is referred to the input".
SCALE FACTOR For the log amp, the scale factor (KHs
the voltage change at the output for a decade (i. e. 10:1')

change at the input. For the antilog amp, the scale factor
is the voltage change required at the input to cause a one
decade change at the output. See equations 9 and 10.

ORDERING INFORMATION

TYPE
8048
8048
8048
8048
8049
8049
8049
8049

BC
BC
CC
CC
BC
BC
CC
CC

PACKAGE
16 Pin Ceramic DIP
16 Pin Plastic DIP
16 Pin Ceramic DIP
16 Pin Plastic DIP
16 Pin Ceramic DIP
16 Pin Plastic DIP
16 Pin Ceramic DIP
16 Pin Plastic DIP

'MAX_ ABSOLUTE
ERROR (2S0,C)

TEMPERATURE RANGE
O°C to
O°C to
O°C to
O°C to
O~C to
O°C to
O°C to
O°C to

30mV
30mV
60mV
60mV
10mV
10mV
25mV
25mV

5-212

+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C

ORDER PART NUMBER
ICL 8048 BC DE
ICL 8048 BC PE'
ICL8048CCDE
ICL 8048 CC PE
ICL 8049 BC DE
ICL 8049 BC PE
ICL 8049 CC DE
ICL 8049 Cc PE

ICLS063
Power Transistor Drive.r-Amplifier

FEATURES:

Designed to operate with all varieties of operational
amplifiers and other functions, two external power
transistors of any construction technique, and 8 to 10
passive components, the ICL8063 is ideal for use in such
applications as linear and rotary actuator drivers, stepper
motor drivers, servo motor drivers, power supplies, power
DACs and electronically controlled orifices. .

• Converts ±12V Outputs from 'Op Amps and other
linear functions to ±30V levels
• When used in conjunction with general-purpose
op amps and external complementary power
transistors, system can deliver> SO Watts to
external loads
• Has built-in Safe Area Protection and short-circuit
protection
• Produces 2SmA quiesgent current in power amp
configuration while delivering ±2 Amps output
current
• Has built in ±13V Regulators to power op amps or
, other external functions
SOOkO input impedance with RBIAS = 1MH

The ICL8063 takes the output levels (typically ±11V) from an
op amp and boosts them to ±30V to drive power transistors,
(e.g. 2N3055 (NPN) and 2N3789 (PNP)). The-outputs from the
ICL8063 supply up.to 1OOmA to the base leads of the external
power .transistors.
This amplifier-driver contains internal positive and negative
regulators, to drive an op amp or numerous other functions;
thus, only ±30V supplies are needed for a complete power
amp.

GENERAL DESCRIPTION

The ICL8063 provides built-in power supplies and will
operate from inputs generated by most of the op amps in use
today-regardless of technology-as well as many other
linear functions, such as timers, comparators and waveform
generators. And it will drive almost all power transistors with
breakdown voltages up to 70 volts.
\

The ICL8063 is a unique monolithic power transistor driver
and amplifier that allows construction of minimum chip
power amplifier systems, complete with built in safe
operating area circuitry, short circuit protection and voltage
regulators. It is primarily intended for complementary
symmetrical outputs.

SCHEMATIC DIAGRAM

PIN CONFIGURATION

-VREG. OUT

1

12 GNO

FREQ. COMPo CAPAC.

5

PNP BASE DRIVE OUTPUT

.6

11

-RSHORT CKT. PROT.

7

10 CURRENT COMpo. CAPAC.

OUTPUT

8

9

NPN BASE DRIVE OUTPUT
+RSHORT CKT. PROT.

(outline dwg JE, PEl

O.RDERING INFORMATION
ICL8063MJE
ICL8063CJE

- CERDIP, -55°C TO 125°C

ICL8063CPE

- PLASTIC DIP, O°C,TO 70°C.

- CERDIP, O°C TO +70°C

5·213

5

ICL8063
ABSOLUTE MAXIMUM RATINGS @ TA = 25°C
Supply Voltage .•............. ,.......................................... ±35V
Power Dissipation ......................•...................• '.......... 500mW
Input Voltage (Note.1) .•..•........................................... ,... ±30V:'
Operating Temperature Range .................... ICL8063MJE -55°C to +125°C
ICL8063CPE O°C to 70°C
ICL8063CJE O°C to 70°C
Storage Temperature Range .................................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec) ........................... : ......... 300°C
Regulator Output Currents ............................................... 10 mA
Nole 1:

For supply voltages less than ±3'OV the absolute maximum input voltage is equal to the supply voltage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other condilions above those indicated in the operational se"ctions of the specifications is not
implied. Exposure to absolute. maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS.(@25°C; Vsupp = ±30V)
MINIMAX LIMITS
SYMBOL

TEST CONDITIONS

CHARACTERISTIC

ICLB063C

ICLB063M
-55°C

+25°C +125°C

DOC

+25°C

UNITS
t7DoC

Vos

Max. Offset Voltage

See Figure 1

150

SO

50

150

75

75

mV

10H

Min. Positive Drive .
Current

See Figure 2

50

50

50

40

40

40

mA

loa

Max. Positive Output
Quiescent" Current

See Figure 3

500

250

250

600

300

300

p.A

10L

Min. Negative Drive
Current

See Figure 2

25

25

25

20

20

20

mA

10L

Max. Negative Output
Quiescent Current

See Figure 4

500

250

250

600

300

300

p.A

V.REG

Regulator OU,tput Voltages
Range

See Figure 5

±13,7
±1.2V

±13.7
±1.0V

±13.7
±1.5V

±13.7
±1.0V

±13.7
±1.0V

±13.7
:!:1.0V

V

ZIN

A.C. Input Impedance

See Figure 6

400

400

400

400

400

400

kll

VsuPP

Power Supply Range

10

Power Supply
Quiescent Currents

Av

Range of Voltage Gain

VOUT(MINI

V

±5 to ±35V
10

6

6

12

7

7

mA

See Figure 7
VIN = 8Vp-p

6±2

6±2

6±2

6±2

6±2

6±2

VIV

Minimum Output Swing

See Figure 7; Increase
VIN until VOUT flattens

±27

±27

±27

±27

±27

'±27

V

liN

Input Bias Current

See Figure 8

100

100

100

100

100

100

IJ.A

IREG

Regulator Output Current

(See Note 21

10

10

7

10

10

7

mA

Nole 2:

Care should be taken to 'ensure that maximum power dissipation

IS

not exceeded.

RSIAS

1Mn

.-__.--'-_-0 Your"" 6 (Yes)
:. Vas:=

V~UT

'-

V,N

,.,,"'
'...,
'.

I

I

"

10'

POWER AMP OF FIG. 9

Your "'-1

lOOk

1M

AOPEl\IlOOP = 101· X Your
Vo

'.

10M

Figure 12: Bode Plot of Open Loop Gain of Above Schematic

,.

10kn

+30V

0.6

0.5
O.4fl
@5W

§: 0.4

g

a: 0.3

0.2

/

0.1

O.02!l
10

100

,.

./

ROUT

10k

=:

EI~~~:UT X D.l!1

Em

lOOk

L -__

~~l~OO~O~.F~_VO~U_'~OV·lvn~rv

f-(Hz)
ROUT

Figure 13: Typical Performance of ROUT vs. Frequency of

2. Designing A Simple Function Generator

Pow~r

Amplifier System

Capacitor working voltages should be greater than 50V DC
and ali resistors should be 1/2W, unless otherwise indicated.
The interconnecting leads from the 741 pins 2 and 3 to their
respective resistors should be kept short, less than 2 inches if
possible; longer leads may result in oscillation.
Full output swing is possible to about 5KHz; after that the
output begins to taper offdue to the slew rate of the 741, until
at 20KHz the outpulswing will be about 20V pp (±10Vl. This
problem can be remedied by simply using an op amp with a
higher slew rate, such as the LF156.

USing a variation of the fundamental power amplifier
building block described in the previous section, the
ICL8063 dm be implemented in the design of a simple, low
cost function generator (Figure 14l. It will supply sine waves,
triangular waves and square waves from 2 hertz to 20
kilohertz. This complete test instrument can be plugged into
a standard 110VAC line for power. VOUT will be up to ±25V
(50V p-p) across loads as small as 10 ohms (about 2.5 amps
maximum output currentl.
5·217

n~ol!"

ICL8083
.
R,'
1GOk

~

Va

R710k

2N3Oss DN HEAT SINK

Q,'.-----...,

.

CI.4fi
5W

'

ICL8038

R,.
R11

8

10

.All

11

5W

....
1GOk

,

SYMMETRY ADJUST

Co

1000pF

1,..F COYER RGE 2 - 20Hz

0.1,..F COVER AGE 20 - 200Hz:
O.o1,..F COVER AGE ZOO - 2kHz
0.001"F COVER RGE 2kHz·- 20kHz

•TRANSFORMER
IS TRIAD RUB

1

+
e,~

*,@50 WVDe
10.ooo,..F-

Flgure14: power Function Generator

3. Building .. CQnstant Current Motor Drive Circuit

2N3.55

The constant current motor drive configuration shown in
Figure 15 is an extremely simple circuit to construct using
the ICL8063. This minimum device circuit can be used to
drive DC motors where there is some'likelihood of stalling or
lock up; if the motor locks, the current drive remains
constant and the system does not destroyitse!f. Using this
approach two 6V batteries are sufficient for' decent
performance. A 10 volt input will produce one amp of output
current to drive the motor, and if the motor, is, stalled, lOUT
remains, 'at 1 amp~

0.4n
,@5W

....
-r--r--r__i-.-r-r.-'Vvv
.. +
IloUT
...,.
0.40
@5W

For example, suppose it's necessary tei' drive a 24V DC motor
with 1 amp of drive current. First make Vsupp at least 6 volts
more than the motor being driven (in this case 30 volts). Next
select RBIAS according to Vsupp from the data sheet, which
indicates RalAs = 1MO. Then choose Rl, R2, and Ra for
optimum sensitivity. That means making Aa = 10 to minimize
the voltage drop acrossAa (the drop will be 1'amp x 1 ohm or '
1 volt). If,l amp/volt sensitivity is desirable let A2= Al = 10kO
to minimize feedback current error. Then a ±lV input voltage.
will produce a ±1 amp current through the motor.
Capacitors should be at least 50 voltswork'ing voltage and all
resistors 1/2W,except for those valued at 0.4 ohms, and Ra.
Power across Ra = I x V = 1 amp x 1 volt = 1 watt, so at least a 2 '
watt value should be used .. Use large heat sinks for the
2N3055 and 2N3791 power transistors. A Delta NC-641 or the
equivalent is appropriate. Use a thermal compound When
mounting the transistor to the heat sink. (See Intersil
ICH8510 data sheet),

R,
NOW ~ ." (-) R2/R, x
~IN

..!..
Ra

Figure 15: Constant Current Motor Drive

4. Building 'A Low Cost 8 ohm per channel HI-fi
Amplifier.
'
For about $20 per channel, it's possible to build a high fidelity
amplifier using the ICL8063 to drive 8 ohm speakers. A
channel is defined here as all amplification between
turntable or tape output and power out. (Figure HI)
The input 741 sfage Is "a preamplifier with A.I.A.A.
equalization for records. Following the first 741 stage is a
10kO control pot, whose wiper arm feeds 'into the power
amplifier stage consisting 'of a second 741, the ICL8063 and

5·218,

O~OIb

ICL8063
the power transistors. To achieve good listening results,
selection of proper resistance values in the power amplifier
stage is important. Best listening is to be found at a gain
value of 6 [(5kfi + 1kfi/1 kfi = 6)]. 3 is a practical minimum,
since the first stage 741 preamp puts out only ±10 volt
maximum signals, and if maximum power is necessary this
value must be multiplied by 3 to get ±30 volt levels at the
output of the power amp stage.
Each channel delivers about 56 volts p-p across an 8 ohm
speaker and this converts to 50 watts RMS power. This is
derived as follows:
Vrms 2
56V p-p
Power = 8 ohms' Vrms = ~ = 20V, 20V2 = 400V2

4002

:. Power = - - - = 50 watts RMS Power.
8 ohms
Distortion will be < 0.1% up to about 100Hz, and then it
increases as the frequency increases, reaching about 1% at
20kHz.
The ganged switch at the input is for either disc playing or
FM, either from an 'FM tuner or a tape amplifier. Assuming
DC coupling on the outputs, there is no need for a DC
reference to ground (resistor) for FM position. To clear the
signal in the FM position, place a 51 kfiresistor to ground as ,
shown in Figure 16 (from FM input position to ground),

200kn

Skn

30kO

O.40@5W

FM>-.--------<>.,.

SO SPEAKER

+

10.000~F

- J.@SOWVDC

Figure 16: Hi Fi Amplifier
r--~-4~-~-~--~----,-o13
+30V

+16

f----

---~

1,

RL::; '"

+12
R,=10n

,

\\

CC=O~\

51 z+8

\\

oll>

100-------4

~\~

"
+4

Cc~\o~~~~

R,

.\
~~

\'

-2

i

/

100

,.

10'

100k

1M

f-(Hz)

OUT vs. Frequency For Typical Circuit Shown
Figure 17: Typical Performance Curve of Ev

IN

5-219

O~OlL/

ICL8063

r----. __~---.----._--~~------~~13
+30V.

SOOk

.......

400k

::

\

300k

~

z

N

200k

\

lOOk x VA

RL

liN"" - - - - YIN - VA

\

100k

100Hz

V,N

1kHz

\

10kHz
100kHz
I-(Hz)

1M

10M

..

iii

Figure 18: Typical Performance Curve of Input Impedance Versus Frequency for Typical Circuit Shown

CHIP TOPOGRAPHY

68

Nole: Intersil offers a hybrid power amplifiersimilartothat
shown in fig. 9. See ICH8510/8520/8530 data sheet for
details.

5-220

ICLS069 Series
Low Voltage Reference

FEATURES

GENERAL DESCRIPTION

• Temperature Coefficient guaranteed to 10 ppm/o C
max.
• Low Bias Current ... 50J.LA min
• Low Dynamic Impedance
• Low Reverse Voltage
• Low Cost

The ICL8069 is a 1.2V temperature compensated voltage
reference. It uses the band-gap principle to achieve excellent
stability and low noise at reverse currents down to 50!,A.
Applications include analog-to-digital converters, digital-toanalog converters, threshold detectors, and voltage
regulators. Its low power consumption makes it especially
suitable for battery operated equipment.

TYPICAL CONNECTION DIAGRAMS
-_----_-+sv
+ 15V
2.2kH

ICLaOS9

---_---,sv

v+

15kll
10kll

ICL7107
ICLaOS9

1k!l

REF HI

10kll

, -ol
[vour
~See

~---t COMMON

- - - t REF LO

L -.....

Nole 1

I
I

.!
la) Simple Reference 11.2 volts or less)

Ib) Buffered 10V Reference using a
single supply.

ORDERING INFORMATION
MAX. TEMPERATURE
COEFFICIENT OF VREF
.005 %/oC
.005 %/oC
.01 %;oC
.01 %/oC

MAX. TEMPERATURE
COEFFICIE~T OF VREF
.001%/oC
.0025 %/oC
.005 %/oC
.005 %/oC
.01 %/"C
.01 %/oC

TEMP RANGE
-55°C to +125°C
O°C to +70°C
-55° C to +125° C
O°C to +70°C

Ic) Double regulated .100mV reference
for ICL7107 one-chip DPM circuit.

PIN CONFIGURATION
. TO-92
ORDER PART #
ICL8069CCA
ICL8069DCA

TEMP RANGE

TO-52
ORDER PART #

O°C to +70°C
O°C to +70°C
-55°C to +125°C
O°Cto +70°C
-55°C to +125°C
O°C to +70°C

ICLB069ACO
ICL8069BCQ
ICL8069CMQ
ICL8069CCQ
ICL8069DMQ
ICL8069DCQ

(outline dwg TO·92)

NOTE: ICLB069DC and IC18069DM are also available as dice. Order
ICLS069DC/D and ICLB069DM/D

5-221

ICLS069 Series
ABSOLUTE MAXIMUM RATINGS
Reverse Voltage ......... .- ................... See Note 2
Forward Current ............................... '.•. 10mA
Reverse Cu'rrent .................................. 10mA
Power Dissipation, . Limited by max forward/reverse current
Storage Temperature ................... -65° C to +200° C
Operating Temperature
ICL8069C ....•.. ; ...................... 0°Cto+70°C
,ICL8069M .........•..•............. -55°Cto+125°C
LeadTemperature(Soldering,10Sec) ...•......... 300°C

ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

(@ 25°C unless otherwise ,noted)

CONDITIONS

TYP

MIN

UNITS

MAX
I

Reverse breakdown
Voltage

IR

Reverse breakdown
Voltage change

50llA ::; IR ::; 5mA

= 50llA
= 500llA
IF = 500llA

,7

Reverse dynamic Impedance

= 500llA

1,20

1.23

IR
IR

Forward Voltage Drop
RMS Noise Voltage

\

10Hz::; f ::;10kHz
IR = 500pA

1.25

V

15

20

mV

1
1

2
2

n

1

V

5

IlV

!

Breakdown voltage
Temperature coefficient:
ICL8069A
ICL8069B
ICL8069C
ICL8069D

m

I,· 500,A

'

T A = operating
temperature range
(Note 3)

;

Reverse/Current Range.

-

.001
.Q025
.005
.01 ,

%/oC

5

rnA

.050

TYPICAL PERFORMANCE CHARACTERISTICS
REVERSE VOLTAGE AS A
FUNCTION, OF CURRENT

VOLTAGE CHANGE AS A
FUNCTION OF REVERSE CURRENT

'4
~

lOrnA

o
~

;!

5>

...

I-

z

.

lmA

~

w
a:
a:

"~

-55°C /

//

4

~~25OC.

....,25"C

0

I~ I", SOO~A

1.240

8

...ir '

"o

1.245

12

;;; 10

"::!z

REVERSE VOLTAGE AS
A FUNCTION OF TEMPERATURE

~
100.. A
~EYERSE

100},lA

a:
w

i:;

/,;"""

a:

/'

lmA

10mA

1.235

0

1.230

..

1.225

...>
"...

:::::;::::

"

./

.2

.4

.6

.8

1.0

REVERSE VOLTAGE (V)

'r"""

i-"""

0

+'17 t4rY ~F

CURRENT

w

"!:;<

,

1.220
1.215
1.2

1.4

-50

-25

0

+25

+50

+75 +100 +125

TEMPERATURE (Oe)

,

Notes:
1) The diode should not be operated with shunt capacitances between 200pF and O.22/lF, as it may oscillate at some currents. Ifcircuit strays in
excess of 200pF are anticipated, a 4.7/l'F shunt capacitor will ensure stability under all operating conditions.
2) In normal u,se, the reverse voltage cannot exceed the reference, voltage. However when plugging units into a powered-up test fixture, an
instantaneous voltage equal to the compliance of the test circuit will be seen. This should not exceed 20V.
3) For the military part, measurements are made at 25° e, -55° e, and +125° e. The unit is then classified as a function of the worst case T.e, from
25° e to -55° e, or 25° e to +125° e.

5·222

'ICL8211., ICL8212,
Programmable Voltage Reference

FEATURES

GENERAL DESCRIPTION

• High accuracy voltage sensing and generation:
internal reference 1.15 volts typical
• Low sensitivity to supply voltage and temperature
variations
• Wide s!Jpply voltage range: Typ. 1.8 to 30 volts
• Essentially constant supply current over full supply
voltage range
• Easy to set hysteresis v.oltage range
• Defined output current limit - ICL8211
High output current capability - ICL8212 .

The Intersil ICL8211/12 are micropower bipolar monolithic
integrated circuits intended primarily for precise voltage
detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of
output buffer/drivers.
Specifically, the ICL8211 provides a 7mA current limited
output sink when the voltage applied 'to the 'THRESHOLD'
terminal is less than 1.15 volts (the internal reference), The
ICL8212 requiresa voltage in excess of 1.15 volts to switch its
output on (no current limit). Both devices have a low current
output (HYSTERESIS) which is switched' on for input
voltages in excess of 1.15V. The HYSTERESIS output may be
used to provide positive and noise free output switching
using a simple feedback network.
Applications include:
1. Low voltage sensor/indicator
2. High voltage sensor/indicator
3. Non volatile out-of-voltage range sensor/indicator
4. Programmable voltage reference or zener diode
5. Series or shunt power supply regulator
6. Fixed value constant current source

SCHEMATIC DIAGRAM

PIN CONFIGURATION
. HYSTERESIS

8

VOLTAGE REFERENCE COMPARATOR OUTPUT BUFFERS

'.-_ _-~..-..,:."_'",:v~---<~~_ _.f.'r_-.-_A_ _.,.'_ _~8 V+
RS
4.Skil

+-__.:..o2 HYST

L.._ _

4

GROUND
(outline dwg PAl

(outline dwg TO-99)

ORDERING INFORMATION
Part Number
ICL8211CPA
ICL8211CTY
ICL8211MTY
ICL8212CPA
ICL8212CTY
ICL8212MTY
ICL8211D
ICL8212D

Temperature Range

o to +70°C
o to HO°C
-55° to +125°C
o to 70°C
o to 70°C
-55 to +125°C
Dice only
. Dice only

,THRESHOLD

Package
8 lead Mini DIP
TO-99 Can
TO-99 Can
8 lead Mini DIP
TO-99 Can
TO-99 Can

x

<~ R6

~ 100k!l
x

x

,x

x
- - - - ICL8211 oplion
x x x x ICL8212 opllon

5-223

ICL8211/ICL8212

,n~nlb

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ....•.........•................•........'....... -0.5 to +30 volts
Output Voltage ............................................... -0.5 to +30' volts
Hysteresis Voltage ........................................ , ... +O.S to -10 volts
Threshold Input Voltage .............. " +30 to -5 volts with respect to GROUND
and +0 to ,-30 volts with respect to V+
Current into Any Terminal ........................ ,...................... ±30mA
Power Dissipation (Note 1 & 2) ......................................... 300mW
Operating Temperature Range' ICL8211M/12M ... , .. ; .......... -5SoC to +125°C
Operating Temperature Range ICL8211C/12C ....................... 0 to +70°C
Storage Temperature Range ................................... --usoC to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Rating applies for case temperatures to 125°C to ICL8211MTY/12MTY products. Derate linearly at -10mW/oC for ambient
temperatures above 1000 e.
NOTE 2: Derate linearly above 50°C by -10mW/oC for ICL8211C/12C products. The threshold input voltage may exceed +7 volts for short
periods of time. However for continuous operation this voltage must be maintained at a value less than 7 volts.

TYPICAL OPERATING CHARACTERISTICS (v+
PARAMETER
Supply Current

SYMBOL
,+

Threshold Trip Voltage

VTH

Threshold Voltage Disparity
Between Output & Hysteresis
Output
Guaranteed Operating Supply
Voltage Range

VTHP

Typical Operating Supply
Voltage Range

Vsupp

Threshold Voltage
Temperature Coefficient
Variation of Threshold Voltage
with Supply Voltage
Threshold Input Current
Output Leakage Current

Output Saturation'Vpltage
Max Available Output Current

Hysteresis Leakage Current

Vsupp

= 5V, TA = 25°C unless otherwise specified)

CONDITIONS
2.0 < V+ < 30 ,
VT = 1.3V
VT = 0.9V
'lOUT = 4mA V+
V+
VOUT = 2V
V+

= 5V
= 2V
= 30V

AVTH/AV+
ITH
10lK

VSAT
10H

IlHYS

Hysteresis Sat Voltage

VHYS

(max)

Max Available Hysteresis Current

IHYS

(max)

TYP

MAX

MIN

10
50
0.98
0.98
1.00

22
140
1.15
1.145
1.165
-8.. 0

40
250
1.19
1.19
1.20

50
'10
1.00
1.00
1.05

30
30
30
30
30
30

2.0
2.2
2.8
1.8
1.4
2.5

lOUT = 4 rnA VOUT= 2V
IHYST = 7p.A VHYST = 3V
+25°C
-55°C to +125°C
+25°C
+125°C
-55°C
lOUT = 4mA
VOUT = 2V
A V+ = 10% atV+ ~5V
VTH = 1.i5V
VTH = 1.00V
VOUT = 30V
VOUT = 30V
VOUT = 5V
. VOUT = 5V

110
20
1.15
1.145
1.165
-{).5

250
40
1.19
1.19
1.20

p.A
p.A
V
V
V
mV

' 30
30
30
30
30
30
+200

1.0

1.0

mV

250

100
5

250
10

VTH '" 1.0V
VTH = 1.3V
VTH = 1.0V
VTH'= ,l.3V

10
1

= 4inA

0.17

1
0.4

7.0

12

0.17
4

15
0.1
-{).1
-15

UNITS

+200

100
5

VTH = 1.0V
VTH = 1.3V
(Note 3 & 4) VTH = 1.0V
VTH = 1.3V
VOUT = 5V
-55°C oS TA oS 125°C VTH = 1.0V
V+ = 10V VTH = ~:OV
VHYST =VIHYST - -7p.A VTH - 1.3V
measured with respect to V+
VTH'= 1.3V
IO~JT

ICL8212
TYP
MAX

V
V
V
V
V
V
ppmi"C

2.0
2.2
2.8
1.8
1.4
2.5

o to +70°C

AVTH/AT

'~L8211

MIN

-21

15
12

-15

0.1

rnA
rnA
p.A

-{).2

V

35

-{).1

-{).2

0.4
rnA

-21

nA
nA
p.A
p.A
p.A
p.A
V
V

p.A

NOTE 3: The maximum output current of the ICL8211 is limited by design to 15ma under any operating conditions. The output voltage maybe
sustained at any voltage up to +30 as long as the maximum power dissipation of the device is not exceeded.
NOTE 4: The maximum output current of the ICL8212 is not defined, and systems using the ICL8212 must therefore ensure that the output
curre~t does not exceed 30ma and that the maximum power dissipation of the device is not exceeded.

S-224

O~OIL

ICL821 'U / UCL8212
TYPICAL OPERATING CHARACTERISTICS

HYSTERESIS
OUTPUT SATURATION CURRENT
AS A FUNCTION OF TEMPERATURE

THRESHOLD INPUT CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

~

10,000
TA 25·C
V· 10V
1,000

I- H~L8Jll

Characteristics
common to both
the ICL8211 and
the ICL8212

~r IcL821~- i -

0

V· = 5V
VTH'= 1.2V

!Z-5
w
a:
0:
:>-10

VHYS

= 4.~~ J.5V 11th

I

respect to V' supply)

u

I-

:>-20
0.

50-25

100
I/

!II

~-30

a:

r--

ICLrll

w

I

I

ICj212

t--

li;

10
0.0 1.1 1.151.2 2.0 3.0 6.0 8.010.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALEj

~

-40 -20

0 +20 +40 +60 +80
TEMPERATURE ·C

Characteristics ICL8211
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE
150

150

1125

~VTH = 0 . 9 v i ±
TA=~5·C

I-

~ 100
a:

I I
f
.

.a 75

, 100

IZ

~ 75

a:
:>

>~ 50

ICLf211

0.
0.

I

.§.

ICL~211

!Z 8
w
a:
a:
:>

u

5
0.

4

l-

S2

. TA=25·C
v' = 5V'
VA = 0.5V
VHYS = v' - 0.25V

kl

I I
HYSTERESIS

OU+P~ ~ ~yUT
I
I
J

-h

_8~V

~ 7
a:

V
a
II:

-5~

'0:

a

o
>

-15 ~

I-

:l
-20 0
!II

iii

-25~

-55 -25

+5 +35 +65 +95 +125
TEMPERATURE ·C

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF SUPPLY VOLTAGE

9 1.14

C) 1.17

~~~~--r-~~~~

~

1---t--~7"'r--t--~~

o....

o

:I:

!II
W

II:

OUTPUT",

......
......

vv
./

./ J'.HYS
OUTPU';--

IriL~il1.lJ.l'

1.13

>-

-55 '-25 +5 +35 +65. +95 +125
TEMPERATURE ·C

:I:

OUTPUT CURRENT A$ A
FUNCTION OF OUTPUT VOLTAGE

9

I--

w

.J.IL~.clttt-+-tttH

~~L~;l~ -lHtt-.....-p.4-tt1H

a:
:>

1111

0L-~~~V~T~H_~~.1~52~V~~~

5-225

0

!Z -5

w
~

-10

:>

l-

S ~1J/:j;#f~I'=4-Ilf;II±t1tH
1.0
10.0
OUTPUT VOLTAGE

1

I--

I-

~

100.0

2 3 45
10 20304050100
SUPPLY VOLTAGE

HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF .
HYSTERESIS OUTPUT VOLTAGE

~ -20

~ 3~ffl++~_V_TrHt=Hlr·l~47_V-rtt1;
0.1

1

u -15

. VTH -1.0V

II:

u

-55 -25 +5 +35 +65 +95 +125
TEMPERATURE ·C

Jl

~1.16

I I II

I' ?rA, VHYS = (V' -2) V

j!:1.14

j!: 1.13

I-

V' =5V
VTH = 1.1V
Va = 1.0V

~~a~ va! 1V

w

~

-"""""K

r-IH,s

~1.15
!II
w
,0:

I--

ICLJ211

1-101=

w

-30~

~ 6

o

.....1"""--t--+--t

25 ~-t--±

1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

~ 1.15

I-

a:

-10

I-

:>

IV-

1.18

I-

I-

~

12~~n-T-~~-r-r~n

.§.

751---+--~--r--+---r~

'5

I-

OUTPUT SATURATION CURRENT AS
A FUNCTION OF TEMPERATURE

r--

~

!II

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF TEMPERATURE

1.12 1.13 1.14 1.15 1.16 1.17 1.18
THRESHOLD VOLTAGE

.

~

0.

0.0

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE

.:. 100

u 50 ~-t~-r~~-+--~~

25

30

10
20
SUPPLY VOLTAGE

!.

:>

!II

'VTH = 1.3V

12

, I~L82Jl-

~

:>

cu 10

I

TA=25·C
V'= 5V
\ OUTPUTS OPEN
CIRCUIT

u 50

25

!II

r- r-.

.!.

OUTPUTS OPEN CIRCUIT

0:

'5

1125

SUPPLY CURRENT AS A FUNCTION
OF TEMPERATURE

S -25
~

~

-40

VI

TITlI

If·

~81,,1

J
ICL8211
TA = 25·C

r,

-30

10iJ LJ
~~lll

ffi -35
t;

rTI l j14fr

~ -10.00

-1.00
-0.10
-0.10
HYSTERESIS OUTPUT VOLTAGE

ICL8211/ICL8212
TYPICAL OPERATING CHARACTERISTICS
Characteristics ICL8212

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

150

TA=2~OC I

I

150

I

':;125

<,125 I-OUTP~T~ OrEN fIRCUIT-

.:;

!zw

" VTH

100

a:

§ 75

r- -

o

.~

a.
a.

50

1.3V

I ICLr12
I I
-

.

I

~ 100

.
i--

zw

~ 75 i-- ICJ212

r-

:l

.0

~ 50

I,vTH - o.~v

~ 25

g;
til

I I
o

10,
20
SUPPLY VOLTAGE

TA - 25°C
I
I
I
v' = 5V
OUTPUTi OPEN CIVT"':::

<'

150

V· =5V
<'
.:; 125 r-- OUTPUTS OrEN CIRCUIT

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE

1

B

::i
til

o

Li

!zw

20

.-55 -25

§ 15 J--+JJ.-I-

c..J

~ 10t--t.r~~~9===~~
I!:

:J:

o

5

5

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF SUPPLY VOLTAGE

a:

-25

1.14

301

~~

z
0 0 .4

~~

11

10 §

v

~

~ 0.2

~

~

~

0

~

+5 +35 +65 +95 +125 ~
TEMPERATUREoC
0

I

'

o

ICJ21!

11

lvf~'liiv
1J..111

VTH -1.153V

!,;II

0.1

k~~lnJv
i I

v

~

~

-55 -25

TA=25°C
V' =5V

0

~ 0.3
~ 0.1
5 0

40

1.0
10.0 30.0 100.0
OUTPUT VOLTAGE

CIRCUIT DESCRIPTION
The ICL8211 and ICL82.12 use standard linear bipolar
integrated circuit technology with high value thin film
resistors which define extremely low value currents.
Components 01 thru 010 and R1, R2 and R3 set up an
accurate voltage reference of 1.15 volts. This reference
voltage is close to the value ofthe bandgap voltage for silicon
and is highly stable with respect to both temperature and

r;;oTH OUTPriE
TA

= 25

Q

C

~~~~~~ES1
I

I

lOUT = 4mB, VOUT = 1V
.. _
IHYS = -7MA, VHYS = (V' - 2) V
1.13
.1
2 345 10 20304050 100
SUPPLY VOLTAGE

+5 +35 +65 +95 +125
TEMPERATURE °c

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

~05.
g

§! 1.15
ffi
~1.14

~

~0.6

/

L

9

o

OUTPUT SATURATION VOLTAGE
AND CURRENT AS A
FUNCTION OF. TEMPERATURE

Icl8~1~

.g~ 1.16

:31.15 J--t---I7"Y---,-+-f--i

1--1-1-+---1--

+5 +35 +65 +95 +125
TEMPERATURE °c

~ 1.17

~1.16

J--+I-if-

a:

I

, .,

V

1.18
w

I

vL=ot- r -

50

a.
~ 25

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF TEMPERATURE

1 25 J--+I--I---A"-+--f---1-5

" VTH = \.3V t-ICJ212

~ 75

0.0 1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD' VOLTAGE- VTH
(IRREGULAR SCALE)

30

r"'""

~ 100

zw

I

~

25

SUPPLY CURRENT AS A FUNCTioN
OF TEMPERATURE

HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF
HYSTERESIS OUTPUT VOLTAGE

<'
.:;
~

z

0

.....

-5

~-10

a:

B-15

~-20

.....

LitT I

~531

VT = 1.153V

U

~-25 ~ ~1.~8V

o

!!!-30
til

.,.

J.(j

I
V

n

821

1i

l-

TA = 25°.C

. ~-35
w
t; -40
> -10.00
-1.00. -0.10
-0.01
:J:
HYSTERESIS OUTPUT .VOLTAGE

Ii'jill

supply voltage. The deviation from .the bandgap voltage is
necessary due to the negative temperature coeific,ient of the
~hin film resistors (-5000ppm per °Cl.
Components 02 thru 09 and R2 make up a constant current
'source; 02 and 03 are identical and form a current mirror. 08
has 7 times the emitter area of 09, and due to the current
mirror, the collector currents of 08 and 09 are forced to be
equal and it can be shown thatthe collector current in 08 and
5-226

O~OIb

ICL8211/ICL8212
1. GENERAL INFORMATION-

09 is
Ie (08 or 09! = _1_ X
R2

THRESHOLD INPUT CONSIDERATIONS

ll. in 7

Although any voltage between ---5Vand v+ may be applied to
the THRESHOLD terminal, it is recommended that the
THRESHOLD voltage does not exceed about +6 volts since
above that voltage the threshold input current increases
sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.

q

or approximately 1J.LA at 25°C
Where k = Boltzman's constant
q = charge on an electron
and T = absolute temperature in oK

,INPUT
VOLTAGE
(RECOMMENDED RANGE -5 TO
+5 VOLTS)

Transistors Os, 06, and 07 assure that the VeE of 03,04, and
09 remain constant' with supply voltage variations. This
ensures a constant current supply free from variations.

VTH

(If MUST
EQUAL OR
EXCEED 1.8
VOLTS)

o---+--uJ

The base current of 01 provid~s sufficient start up current for
the constant current source; there being tv!o stable states for
this type of circuit - either ON as defined above, or OFF if no
start up current is Provided. ,Leakage current in the
transistors is not sufficient in itself to ,guarantee reliable
startup.

RLl

Vo

t--------+-....,--<> VHYST

t02

04 is matched to 03 and 02; 010 i~ matched to 09. Thus the Ie
and VBE of 010 are identical to that of 09 or 08. To generate·
the bandgap voltage, it is necessary to sum a voltage equal to
, the base emitter voltage of 09 to a voltage proportional to the
difference of the base emitter voltages of two transistors 08
and 09 operating at two current densities.

"'"' "w

. VTHO

nV."-

II~

.

H ,ft.no_1
C\

r ,V

,VOLTAGE,

C\

v' - r-l

Thus 1.15 = VBE (09 or 010) +

which provides

R3
R2

--l

R3 X kT in 7

1'i2

0:

q

rI
rl1..CL8211/12 AND
L--.J L.....:........ ~UTPUT.

-l}-----{J--lfl
I I
I ICL8211 ONLY

V.
OV

-

OUTPUT
ICL8212 ONLY

= 12 (approxJ
Figure 1: Voltage Level Detection

The total supply current consumed by the voltage reference
section is approximately 6J.LA at room temperature. A voltage
at the THRESHOLD input is compared tothe reference 1.15
volts by the comparator consisting of transistors 011 thru
017. The outputs from the comparator are limited ·to two
dioCie drops less than V+ or approximately 1.1 volts. Thusthe
base current into the hysteresis output transistor is limited to
about 500nA and the collector current of 019 to 100J.LA.
In the case of the ICL8211, 021 is proportioned to have 70
times the emitter area of 020 thereby limiting the output
current to approximaely 7mA, whereas for the ICL8212
,almost all the collector current of 019 is available for base
drive to 021, resulting in a maximum available collector
current oflhe order of 30mA. It is advisable to externally limit
, this currenlto 25mA or less.

The outputs ~hange states with an input THRESHOLD
voltage of approximately 1.1'5 volts. Input and output
waveforms are shown in Figure 1 for a simple 1.15 volt level
, dt;!tector.
The HYSTERESIS output is a low current output and is
intended primarily for -input threshold voltage hysteresis
applications. If this output is used for other applications it is
suggested that output currents be limited to 10J.LA or less.
The regular OUTPUT's from either the ICL8211 or ICL8212
may be used to drive most of the common logic families such
as TTL or C-MOS using a single pullup resistor. There is a
guaranteed TTL fanout of 2 for the ICL8211 and 4 for the
ICL8212..

v·

VTH

APPLICATIONS
The ICL8211 and ICL8212 are similar in many respects,
especially with regard' to the' setup of the input trip
conditions and hysteresis circuitry. The following
discussion"describes both devices, and where differences
occur they are clearly notlld.
.

Figure 2: Output Logic Interface '

5-227

ICL8211/ICL8212
A principal application .of the ICL8211 is voltage level.
detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive sUPPlY without a series current
limiting resistor.
.
On the other hand the ICL8212 is intend~d for applications
such as programmable" zener references, and. voltage
regulators where output currents well in excess 7mA are
desirable. Therefore, the output of the ICL8212 is not current
limited, and if the output is used to drive an LED, a $eries
current limiting resistor must be used.

INPUT
VOLTAGE

of

a) Range of input voltage greater than +1.15 volts.
Input voltage to change the output'states·
= (R1 + R2)
X 1.15 volts

In most applications an input resistor divider network may be
used to generate the 1.15V required for VTH. For high
accuracy, cLirrents as large as 50~A may be used, however
. for those applications where current limiting may be
desirable, (such 'as when .operating from a battery) currents
as low as 6p.A may be considered without a great loss of
accuracy. 6~A represents a practical minimum, since it is
about this level where the device's own input current
becomes a· significant percentage of that flowing in the
divider network.

MAY BE ANY STABLE VOLTAGE
REFERENCE GREATER
VREF (_I THAN 1.15 VOLTS

INPUT

b) Range of input voltage less than +1.15 volts.
Input voltage to change the output states
(R1 + R2) X 1.15
R2 VREF
R1

v-~~------------~

~

Figure 4: Input Resistor Network Setup Procedures

For supply voltage level detection applications the input
resistor network is connected across·the·supply terminals as
shown.in Figure 5.

Figure 3: Input Resistor Network Considerations

Case 1. High accuracy required, current in resistor network
unimportant Set I =50~A forVTH 7' 1.15 volts:. R1 '20k ohms.

INPUT VOLTAGE
OR SUPPLY VOI;TAGE

Case. 2. Good accuracy required, current in resistor network
important Set I = 7.5~A for VrH = 1.15 volts :. R1150.k ohms.

~----------~vo

Figure 5: Combined Input and Supply Voltages

, Conditions for correct operation of OUTPUT (terminal #4l.
1. ICL8211
.
1.8V::;V+::;30V
2. ICL8212
0::; V+::;30V

SETUP PROCEDURES FOR VOLTAGE
LEVEL DETECTION

Case

Case 1. Simple voltage detection - no hysteresis
Unless an input voltage of approximately 1.15 volts is to be
detected, resistor networks will be used to divide or multiply
the unknown voltage to be sensed. Figure 4 shows
procedures on how to set up resistor networks to detect
. INPUT VOLTAGES of any magnitude and polarity.
.

2.

Use of the HYSTERESIS function

. The disadvantage of the simple detection circuits is that
there is a small but finite input range where the o!Jtputs are
neither totally 'ON' nor totally 'OFF'. The principle behind
hysteresis.is to provide positive feedback to the inpLit trip
P9int such that there is a voltage difference between the
input voltage necessary to turn the outputs ON and OFF.

5-228

ICL8211/1CL8212
The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry, however,
is' not limited to applications requiring better noise
performance but may be expanded into highly complex
systems with multiple voltage level detection and memory
applications - refer to specific applications section.
There are two simple methods to apply hysteresis to a circuit
for use in supply voltage level detection. These are shown in
Figure 6.
r-------------~~v·

"

R:l

Circuit (a) requires that the full current flowing in the resistor
network be sourced by the HYSTERESIS output whereas for
circuit (b) the current to be sourced by the HYSTERESIS
output will be a function of the ratio of the two trip points and
their values. For low values of hysteresis circuit (b) is to be
preferred due to the offset voltage of the hysteresis output
, transistor,
A third way to obtain hysteresis (ICL8211 only) is to connect
a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external resistance
between the THRESHOLD and GROUND when the
OUTPUT is switched on.
3~ PRACTICAL APPLICATIONS

a), Low Voltage Battery Indicator

'--------i---oVO
150kll

a) Low trip voltage' ,
VTRl = [ :.
.R, ...

Vrn r--1S0k
ou,

t~~I1~

t

0:
W

.Z

R, - S~F~

I
ill

.JJ.il

0.1
1.0
,10
100
SUPPLY CURRENT ~ I (mal

Figure 12: Programmable Zener or Voltage Refert:lnce

I

The ICL8212' may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using
a resistor network connected to the THRESHOLD terminal
toprogram, the. zener voltag~ (V zener =
(R1 + R2) X 1.15 volts) .

!v2lv3

S\,PPLY VOLTAGE

SUPPLY VOLTAGE

SUPPLY VOLTAGE

Figure 10: Output States of the ICL8211 and ICL8212 .!Is a
.Function of the Supply Voltage

R1
Referring to Figure 9, the.ICL8212 is used to detect a voltage,
V2, which is the upper yoltage limit to the operating voltage
range. The ICL8211 detects the lower voltage limit of the
operating voltage range, Vl. Hysteresis is used with the
ICL8211 so that the qutput can be stable in either state over
the operating voltage range Vl to V2 by making V3 -the upper .
trip point of the ICL8211 much higher in voltage than V2.
The output of the ICL8212 is used to force the output ofthe
'ICL8211 into the ON state above V2. Thus t~ere is no value of

Since there is 110 internal compensation in the ICL8212 it is
'necessary to use. a large capacitor across the output to
prevent oscillation.
Zener voltages from 2 to 30 volts may be programmed and
typical impedance values between 300l'A and 25mA' will
range from 4 to 70. The knee is sharper and occurs at a
significantly lower current than other similar devices
available.

5-230

O~O[b

ICL8211/ICL8212
v.'o--...--------------..----,

f) Precision Voltage Regulators .
V'~----------------~--

___

r-----R3

I

L·l\v"\,/,,,-

v'o--,--------,-.,---,
Vour

=

R2;' R1 X 1.15 VQLTS

r-----R3

Figure 13: Simple Voltage Regulator

,

L_,\..A,/'\,...

The ICL8212 may be used asthe controller for a highly stable
series voltage regulator. The output voltage is simply
programmed, using a resistor divider network R1 and R2.
Two capacitors C1 and C2 are required to ensure .stability
since the ICL8212 is uncompensated internally.
This regulator may be used with lower input voltages than
most other commercially available regulators and also
consumes less power for a given output control current than
any commercial regulator. Applications would therefore·
include battery operated equipment especially those
operating at low voltages.
High supply voltage dump circuit
In many circuit applications it is desirable to remove the
power supply in the case of high voltage overload. For
circuits' consuming less than 5mA this may be achievedusing an ICL8211 driving the load directly. For higher load
currents it is necessary to use an external pnp transistor or
darlington pair driven by the output of the ICL8211. Resistors
R1 and R2 set up the disconnect voltage and R3 provides
optional voltage hysteresis if so desired.
f)

CIRCUIT
BEING
PRQTECTED

v-

Figure 14: High Voltage Dump Circuits
g) Frequency limit detectors
Simple frequency limit detectors providing a GO/NO-GO
output for use with varying amplitude input signals may be
conveniently implemented with the ICL8211/12. ·In the
application shown, the first ICL8212 is used as a zero
croSSing detector. The output circuit conSisting of R3, R4 and
C2 results in a slow output positive ramp, The negative range
is much faster than the positive range. R5 and R6 provide
hysteresiS so· that under all circumstances the second
·ICL8212 is turned on for sufficient time to discharge C3. The
time constant of R7 C3 is much greater than R4 C2.
Depending upon the desired output polarities for low and
high input frequencies, either an ICL82110ran ICL8212 may
be used as the output driver.
.

II

v'~-,--------~-.----------~~------~-.

C,

Rs

INPUT o-jl+~-ill

L-------------r-~-oOUTPUT

TIME CONSTANT R3 C2 <{ R4 C2 ,; R7 C3
VARY R1 FOR QPTlo.N ZERO CRQSSING DETECTION
VARY R4 TO. SET DETECTION FREQUENCY

---j INDETERMINATE
BELQW to

INPUT --~~-------->'r-------+-OFF

w

!;t

...

1.15V --J.olH---='-'-'==="l;.....i = A

(/)~

"'0>

it~

...

1.15V
B

~

g

--+-H--------++-f--

-

QN

r-

~
(

to

Figure 15: Frequency Limit Detector
5-231

--

ON

ill

!;t

"'01
.cn(;
"'0>
::> ....

-

o,.()

I
I
I

FREQUENCY-

...
::>
OFF 0.

O~OIL

ICL8211/ICL8212

For ,further applications, see A027 "Po,wer Supply Design
using the ICL8211 and ICL8212" by D. Watson.

This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output wil'l switch at the input frequency.
h) Switch bounce filter
Single pole single throw (SPST) switches are less costly and
more available than :single polect'ouble throw (SPOT)
switches. SPST switches range from push button and slide
types to calculator keyboards. A major problem with the use
of switches is the, mechanical. bounce of the elctrical
contacts on closure. Contact bounce times can range from a
fraction of a millisecond to several tens of milliseconds
depending upon the switch type. During this contact bounce
time,the switch may make and break contact several times.
The circuit shown in Fi'gure 16 provides a rapid charge up of
Cl to close to the positive supply voltage (V+) on a switch
closure and a corresponding slow discharge of' (;1 on a
switch break. By proportioning the time constant of R1 C1 to
approxim'ately the manufacturer's bounce time the output as
terminal #4 of the ICL8211/12 will be a single transition of
state per desired switch closure.

CUSTOM OPTIONS
The ICL8211/12 have been designed with more 6n chip
components than are used, in anticipation of more dedicated
high volume system usage. The trigger voltage and
hysteresis resistor network is integrated on chip but not
connected. Consult the 'faqtory for more information on
clistom options.

CHIP TOPOGRAPHY

GROUND

r-_-------._.--ov.
,AL

~ 0.038 _ _--I

SWITCH OUTPU OUTPUT
ICL
1 I L8212
HI
LO
LO
HI

1-

CLOSED
OPEN

(0.965)

,DIE IS PASSIVATED WITH A DEPOSITED OXIDE. BONDING
PAD OXIDE'WINDOWS A~E 3.6 x 3.6 MILS SQUARE.

~~--------_r~-OVo

Figure 16: Switch Bounce Filter

j) : Low voltage power disconnector
There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
,below a certain value. As an example, the National LM199
I precision
reference has an on chip heater which,
malfunctions with supply voltages below 9 volts causing an
excessive device temperature. The ICL8212 may be used to
detect a power supply voltage of 9 volts and turn the power
supply off to the LM199 heater section below that voltage .
.-----------~~----_--~----~v·

LM199

Figure 17: Low Voltage Power Supply Disconnect

5·232

ICH8500/A
Ultra Low Bias Current
Operational Amplifier
FEATURES

GENERAL DESCRIPTION

• Input diode protection
• Input bias current less than 0.01 pA at all
operating temperatures
• No frequency compensation required
• Offset voltage null capability
• Short circuit protection
• Low power ~onsumption

ThelCM8500 and ICH8500A are hybrid circuits
designed for ultra low input bias current operational
amplifier applications. They are ideally suited for
analog and electrometer applications where high input
resistance and low input current are of prime
importance.

APPLICATIONS
•
•
•
•
•
•
•

Femto Ammeter
Electrometers
Long time integrators
Flame detectors
pH meter
Proximity detector
Sample and Hold Circuits

SCHEMATIC DIAGRAM
v'

Functionally, they are pin for pin identical to the
popular 741 monolithic amplifier. These amplifiers are
unconditionarly stable and the input offset voltage can
be adjusted to zero with an external20k potentiometer.
The input bias current for the inverting and noninverting inputs is 0.1 pA maximum for the ICH8500,
and 0.01 pA maximum for the ICH8500A and are
constant over the operating temperature range of
-25 0 C to +85 0 C.
'
Pin 8 is co'nnected to the case. This permits the
. designer to operate the case at any desired potential,
the key to achieving the ultra low input currents
associ a, ted with these t,wo amplifiers. Forcing the case
to the same potential as the inputs eliminates current
flow between the case and the input pins, and leakage
currents that may have otherwise existed between any
of the other pins and the inputs are intercepted by the
case.

ORDERING INFORMATION
ICH

8500A

TV

LPACKAGE

~

,

'

TV=TO-99 metal can
OEVICE TYPE
INTERSI L HYBRID
CIRCUIT

NON·INVERTING
INPUT

lOOpF

OFFSET
NULL

12K

PIN CONFIGURATION
1K

CASE
(GUARD)

1K

OFFSET
NULL

12K

5-233

(outline dwg TO-99l

18

ICH8500/A
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute. maximum rating conditions for
extended periods may cause device failures.

Supply Voltage 0000 .... 00.... 00000.. 0' 0" 00 ±18V
Internal PoWer Dissipation l1 ] 000000000000.0 500 mW
Differential Voltage 000000........ 0.. 000000o. ±Oo5V
Storage Temperature 000:00 .. 0000 -65°C to +150°C
Operating Temperature 0000000000 -25°C to +85°C
Lead Temperature (Soldering lOsec) 00000 o· 300°C
Output Short Circuit Duration 0000000000 Indefinite
Note: 1. Rating applies for ambient temperature to +70· C.

ELECTRICAL CHARACTERISTICS (TA

= 25°C

unless otherwise specified, Vsupp

CHARACTERISTICS
Input Leakage Current
(Inverting and Non-Inverting)

SYMBOL

Input Offset Voltage
Change in Input Offset
Voltage Over Temperature

,

Common Mode Voltage Range .
Large Signal Voltage Gain

MAX

MIN

TYP

0.1

. TEST
CONDITIONS

MAX UNITS
0.Q1

pA
. mV

Case at same
potential as .inputs

Vos

50

50

±Vos

±50

±50

mV

20kO Potentiometer

·±5.0
±500

mV
mV
dB

.+25 to +85°C
-25 to +25°C
±5 volts common
mode voltage

!!.Vos//H

Common Mode Rejection Ratio

Feedback Capacitance
Long Term Input Offset
Voltage Stability

TYPo

!iLK

Offset Voltage Adjustment Range

Output Voltage Swing

MIN

= ±15V)

ICH8500A

ICH8500

CMRR

60

75

60

75

±Vo

±11

±11

V

CMVR

±10

±10

V

AVOL

20,000

105

20,000

Cfb

0.1

!!.Vos/!!.t

±3.0

RL

~

10kO

-

105
0.1

±3.0

pF

Casfl guarded

mV

At 25°C

Slew Rate

SR
CIN

0.5
.0.7

0.5

Input Capacitance

0.7

V/p.s
pF

Input Capacitance

'CIN

1.5

1.5

pF

RL

~

,

2kO

Case guarded
Gase grounded

CIRCUIT NOTE,S
VOLTAGE OFFSET
NULL CIRCUIT

LOW LEVEL CURRENT MEASURING CIRClIlT

VOLTAGE FOLLOWER

">=+-;-o OUTPUT

Vo" 1 VOlT/pA
." 1012,IIN

NOTE: Adiust input offset voltage to OmV ±1 mV before '!leasuring leakage.

5·234

'U~UIL

ICH8500/A
TYPICAL PERFORMANCE CURVES

OPEN LOOP VOLTAGE
GAIN VS. FREQUENCY
..1

"'-

i!

+10

J,
~~
.~'~

w

'"z

"'-

~

'"

.
1

100

lk

COMMON MODE REJECTION
RATIO VS. SUPPLY VOLTAGE

+15

1

Vsupp· t15V
TA" +25"C

10

10-

INPUT VOLTAGE RANGE
vs. SUPPLY VOLTAGE

+5

w

'«"

~

'"
0

>

'"

10k

-5

r-.~IVI: LfMrr

f-

lOOk

~

;:;

-10

+25'C

~ ::::::V
~'r'O~oC
~~.

2.0

r::::

1.5

......-:

li
>
~w

~

,~

'""

u

~

:t

~

'>"
0

1.0

'"5z

0.5

12

13

14

15

16

POWER CONSUMPTION
VS. SUPPLY VOLTAGE
60

"
~SI: \001

"

400

50

.§:

\

z

0

40

"Olz

30

u

20

t

300

200

11

SUPPLY VOLTAGE (±V)

\.

k::

0

\

'"
~

2

100

iiff
.'~

"\~

~

10

V--

~c

.+~

~
I-- , - ' -

,~

~

o

8

10

8

15' 16

INPUT REFERRED
NOISE VOLTAGE

3.0

f-

14

SUPPLY VOLTAGE (tV)

±QUIESCENT SUPPLY
CURRENT VS. SUPPLY VOLTAGE

;C
.§:

11

10

"

12

13

14

SUPPLY VOLTAGE (±V)

15

16

o

10

10.0

lk
FREQUENCY (Hz)

5-235

10k

lOOk

o

8

10

11

12

13

14

SUPPLY VOLTAGE (tV)

15

16

ICH8500/A
APPLICATIONS
The Pico Ammeter
A very sensitive pico ammeter' can be constructed with
the ICHa50D. The basic circuit (illustrated in Figure 1)·
employs the amplifier in the inverting or current
summing mode.
Care must be taken to eliminate any stray currents
from flowing into the current summing node. This can
be accomplished by forcing all poihts surrounding the
input to the same potential as the input. I ri this case the
potential of the input is at virtual ground, or OV,
therefore, the case of the device is grounded to
intercept any stray leakage currents that may
otherwise exist between the ±15V input terminals and
the inverting input summing junctions. Feedback
capacitance' should be kept to a minimum in order to
maximize the response time of the circuit to step
function input currents. The time constant of the

circuit is approximately the product of the feedback
capacitance Cfb times the feedback resistor Rfb. For
instance, the time constant of the circuit in Figure 1 is 1
sec if Cfb = 1 pF. Thus, it takes approximately 5 sec (5
.time constants) for the circuit to stabilize to within 1% .
of its final output voltage after a step function of input
current has been applied. Cfb of less than 0.2 to 0.3 pF
can be achieved with proper circuit layout. A practical
pico ammeter circuit is illustrated in Figure 2.
The internal. diodes CR1 and CR2 together with
external resistor R1 protect the input stage of the
amplifier from voltage transien~s. The two' diodes
contribute no error currents, since under normal
operating conditions there is no voltage across them ..
'Feedback capacitance is the capacitance between the output and
the inverting input terminal of the amplifier.

Cfb

R1b",012n

CURRENT

.......;::--------~-_ OUTPUT

SOURCE

Vo "-lIN Rtb
'" -1 VOLT/pA

CUAAENT/
SUMMING

NODE

. Figure 1. Basic Pico Ammeter Circuit

+15V

INPUT

-

Af
1M"

.......----co-----i

>--~---'V'"","----'---

....""""--~-O------+----- OUTPUT

Vo = -liN )( 10 12 n

"N

=-1 VOlT/pA
CAl

INTERNAL
DIODES

20krl
. 4

-15V

Flgurp. 2. Pico Ammeter Circuit

5·236

ICH8500/A
Sample and Hold Circuit (Figure 3)

As an example, suppose the leakage current due to all
sou'rces flowing into the current summing node of the
sample and hold circuit is 1DOpA. The rate of change of
the voltage across the 0.01 J.lF storage capacitor is then
10mV/sec. In contrast, if an operational amplifier
which exhibited an input bias current of 1 nA were
employed, the rate of change of the voltage across
CSTO would be 0,1 V)sec. An error build up such as this
could not be tolerated in most applications.

The basic principle of this circuit is to rapidly charge a
capacitor CSTO to a voltage equal to an input signal.
The input signal is then electrically disconnected from
the capacitor with the charge 'Still remaining on CSTO.
Since CSTO is in the negative feedback loop of the
operational amplifier, the output voltage of the
amplifier is equal to the voltage across the capacitor.
Ideally, the voltage across CSTO will remain constant,
thus the output of the amplifier will also be constant,
however, the voltage across CSTO will decay at a rate
proportional to the current being injected or taken out
of the current summing node of the amplifier. This
current can come from four sources: leakage
resistance of CSTO, leakage current due to the solid
state switch SW2, currents"due to high resistance paths
on the circuit fixture, and most important, bias current
of the operational amplifier. If the ICH8500A operational amplifier is employed, this bias current is almost
non-existant «0.01 pA). Note that the voltages on the
source, drain and gate of switch SW2 are zero or near
zero when the circuit is in the hold mode. Careful construction will eliminate stray resistance paths and
capacitor resistance can be eliminated if a quality
capacitor is selected. The net result is a quality sample
and hold circuit.
"

Wave forms illustrating the operation of the sample and
hold circuit are shown in Figure 4.

The Gated Integrator

The circuit in Figure 3 can double as an integrator. In
this application the input voltage is applied to the.
integrator input terminal. The time constant of the
circuit is the product of R1 and CSTO. Because of the
low leakage current associated with the ICH8500 and
ICH8500A, very large values of R1 (Up to 1012 ohms)
can be employed; this permits the use of small values of
integrating capacitor (CSTO) in applications that
require long time delays. Waveforms for the integrator
circuit are illustrated in Figure 5.

, Rib CAN BE REDUCED TO 10K
IF CIRCUIT IS EMPLOYED AS
AN INTEGRATOR

RIb
l00kSl
0.01%
INPUT TERMINAL
IF CIRCUIT

CHARGE

STORAGE
CAPACITOR

IS EMPLOYED
AS AN INTEGRATOR
Y,N ='OTO flOV

CSTO
O.01J.1F

/

SW2
1T1700

INPUT TERMINAL
IF CIRCUIT

lOOkn

0.D1%

IS EMPLOYED

.......;:----00----

AS A SAMPLE AND

HOLD CIRCUIT
Y'N =OTO :!:.10V

B

IT1700

+15V
10pF

V2

lSkn
-15V

V3
10kSl

CNULL ~ lpF

'Mil

-15V

-=

V,
SAMPLE

IT1700

PULSE OR
CAPACITOR
DISCHARGE
PULSE

1kll

t--------------'---'

ADJUST CNULL TO ELIMINATE
ANY OUTPUT OFFSET VOLTAGE
DUE TO CHARGE INJECTION
FROM SW2
. I

15kfl

-=

-15V

Figure 3. Sample and Hold Circuit or Integrator Circuit

5·237

OUTPUT

ICH8500/A
WAVEFORMS

.1

Y,N

+5~

--.J

SAMPLE PULSE

.1

+5V
V,N

T1ME_

bl

V, "5V~
'

+15V

bl

V,

-15V

-15V

0---,
V2

dl

I

V3

II

-15V

,I

STATE OF

dl

V3

+15V

-15V

II

CLOSEDli

II
'

~--:-OPEN-­

SWI

STATES~i

II~SED

I

'OPEN

"

TIME_

~
...
'---~

,jl\l
--J
II

,I

STATE OF

SWI

CLOSED II
, ~ ,

I-CLOSEO--I

.

,I

-15V

+15V~1
:
'

SAMPLE PULSE

Dli

,I

i\

i '----',

~15V

--.J

'

',LII

II CLOSED
OPEN~fl~==---

I--CLOSED--i

STATE OF
SW2

,OPEN

OPEN

""'-SAMPLE WINDOW

INPUT TO +16V - - - - - - - - " " ' \ \ .
S&H
0 _______
"'
_ _ _;..._ __

g)

INTE~~:6~~

I

I,~

~SAMPLE

WINDOW

0 -------------

INPUT -lOY

OUTPUT

hi

0 , - - - - , - - ,- - - - - - - - - -

OP.AMP,

,

-

+6V

o

Figure 4. Sample and Hold Circuit Waveforms

= ______ _

_L.._ _ _

Figure 5. Gated Integrator Waveforms

5-238

ICH851 0/8520/8530
Power Amplifier I
Motor & Actuator Driver
KEY FEATURES:

DESCRIPTION:

• Capable of delivering 2.7 amps @ 24-28V d.c.
operation (30V supplies)
• Protected against inductive kick back with internal
power limiting
• Programmable current limiting (short circuit protection)
• Package is electrically isolated (allowing easy heat
sinking)
• DC gain 100dB
• 20m A typical standy quiescent current
.. Popular 8 pin TO-3 package
• Internal frequency compensation
• Can drive up to 0.1 horsepower motors.

SCHEMATIC DIAGRAM

The ICH8510/8520/8530 is a family of hybrid power
amplifiers that have been specifically designed to drive linear
and rotary actuators, electronic valves, push-pull solenoids,
and DC & AC motors.
There are three models available for up to ±30V power supply
operation, 2.7 amps @24voltoutputlevels, 2 amps @24V,and1
amp @24V. All amplifiers are protected against shorts to ground
by the addition of 2 external protection resistors.
The design uses a conventional 741 operational amplifier,
a special monolithic driverchip(BL8063), NPN & PNP power
transistors, and internal frequency compensating capacitors. The chips are mounted on a beryllium oxide
substrat.e for optimum heat transfer to the metal package;
this substrate provides electrical isolation between
amplifiers and metal package.
The I.C. power driver chip has built-in regulators to drive the
. 741 @ typically ±13v supply voltages.

v+

-=

6

~---+-----oVOUT

5

H---t-'V\f\r......-oRSC-

v

ORDERING INFORMATION

PIN CONFIGURATION (OUTLINE

ICH8510MKA

. I

I~ P':';.'2: 'oo",o.o~"
.

(TOPYIEW)

Temperature Range
M=Military -55°C to +125'C
'. I = Industrial -20'C to +85'C
Basic Part Number
8510=1A output
8520 =2A output
8530 =2.7 A output

5-239

DWG. KA)

ICH851 0/8520/8530
ABSOLUTE MAXIMUM RATINGS

@TA=25"'C

Supply Voltage ........................................... , .............. ±32V
Power Dissipation, Safe Operating Area ............................. See Curves
Differential Input Voltage ................................................. ±30V
,Input Voltage ........... , ............................ ; ........... ±15V (Note 1)
Peak Output Current ....................................... See Curves (Note 2)
Output Shori Circuit Duration (to ground) ................... Continuous (Note 2)
Operating Temperature Range M ............................ ,. -55°C - +125°C
I .............................. -20°C - +85°C
Storage Temperature Range .... , .............................. -B5°C to +150°C
Lead Temperature (Soldering, 10 seconds) ....... : ....................... 300°C
Max Case Temperature .............. ; ................. : ................. 150°C
Note 1: Rating applies to supply voltages of ±15V. For lower supply voltages, VINMAX = Vsupp.
Note 2: Rating applies as long as package dissipation is not t\xceeded for heat sink attached. (See Figure 8.1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL SPECIFICATIONS, TA =

+25°C. VSUPP = ±30V (unless otherwise stated)
ICH85101

DESCRIPTION

SYMBOL

CONDITIONS

Inpul Ollsel Voltage
Change with

.lVosl.lPd

Mid. on Wakefield
403 Heat Sink

Inpul Ollsel Vollage

Vas

Rs' 10 kl!
Pd .' tW

Input Bias Current

IBIAS

Rs' 10 kl!
Pd· . lW

MIN.

ICH85201

ICH8510M

MAX.

MIN,

MAX.

4

MIN.

ICH8520M

MAX.

MIN.

MIN.

ICH8530M

MAX

2

4

2

ICH85301

MAX.

MIN.

4

MAX.

UNITS

2

mVIW

Power Dissipation
-6

-3

+6

+3

500

. -6

250

+6

-3

500

+3

-s

250

-3

+6
500

+3

mV

250

nA

Input Offset Current

los

Rs' 10 kl!
Pd .' lW

Large Signal
Voltage Gain
Input Voltage Range

AVOL

Rl -2011
Va ·213 VsuPP

Common Mode
Rejection Ratio

CMRR

Rs

10 kl!

70

70

70

70

70

70

dB

Power Supply

PSRR

Rs

10 kl!

77

77

77

77

77

77

dB

Stew Rate

SR

Cl 3 pF. Av - 1
lOll
Rl
Va . 213 VsuPP

0.5

0.5

0.5

0.5

0.5

0.5

VI'S

Output Voltage Swing

VOMAX

Rl ·2011
Av - 10

~25V

~25V

~2SV

~2SV

(Rl ~3D!!)
+2SV

(Rl "3D!!)
+2SV

V

Output Current (3)

IMAX

811
Rl
Av - 10

2.7

2.7

2.0

2.0

1.0

1.0

A

Power Supply

10

Rl
V'N - OV

200
100

-10

VeMR

100

100

-10

+10

+10

100

200
100

100
-10

+10

-10

100

200
100

+10

-10

-10

+10

nA
dB

100
+10

V

Rejection Ratio

Quiescent Current

Note 3: See Figure #9.if Power Supplies are less than

~

Inpul Offsel Vollage

vas

Pd· lW

Input Bias Current

IBIAS

Pd· lW

Input Offset Current

los

Large Signal
Voltage Gain

AVOL

Output Voltage Swing

VOMAX

Rl

Thermal Resistance

RlljA

Without
Heat Sink

Junction to Ambient

Thermal Resistance
Junction to Case
Thermal Resistance
Supply Vollage Range

Rl - 2011
~Vo ,,,2/3 Vsupp
2011. Av " 10

-10

RIIJA

Vsupp

+10

100

mAo

~24

TA

=

--wc.

-9

~18

~10

+10

-9

=

+9

MV

-20CC. to +85°C.(I)
+9

-10

+10

-9

750

1500

750

1500

750

nA

500

200

500

200

500

200

nA

90
.

90

40

90

90'

V

~24

40

40

40

40

dB

90

~24

~24

=24

=24
40

MId. on Wakefield
403 Heat Sink

- +9

to +125 c C.(M) or TA

1500
90

RflJC

Junction to Ambient

125

100

125

30V,

ELECTRICAL SPECIFICATIONS (continued)

0

100

125

2.5

2.5

2.5

2.5

2.5

2.5

(Typ.)
4.0

(Typ.)
4.0

(Typ-1
4.0

(Typ.)
4.0

(Typ.)
4.0

(Typ.)
4.0

~30

=18

=30

5-240

=18

=30

~18

~30

~18

=30

=18

~30

"CIW
-CIW

.

°CIW
V

o~o[!:.

ICH8510/8520/8530
How To Set The Externally Programmable,
Current, Limiting Resistors:
The maximum output current is set by the addition of two
external resistors, R~c and Rgc. Because of the current
power limiting circuitry, the maximum output current is
,available only when Vo is close to ,either power supply. As
Vo moves away from Vsupp, the maximum output current
decreases in proportion to output voltage. The curve below
shows maximum output current versus output voltage.

v

Inductive Load
(Note catch diode)

Capacitive Load
lOUT (Amp.)

VStJpp .. :!:30Y
Tc -=25"C
Roo ",OAI1,5W

3

,Vo

Thus the limiting circuitry protects the load and avoids
needless damage to the driver during abnormal conditions.
For any 24-28VDC motor/actuator, the Rsc resistors must be
calculated to get proper power delivered to the motor (up to a
maximum of 2.7A) and Vsupp set at ±30V. For lower supply and/
or output voltages, the maximum output current will follow graphs
of Figures 1 and 5.

'Vo
YOU1MAX

NOTE ON AMPLIFIER P~WER DISSIPATION
The steady state power dissipation limit is given by
P _

TJ(MAX) - TA

o - RHJC + RHCH + ROHA
where
TJ =
TA=
RHJC=

}---~VOUT

Rge

Figure 1: Maximum Output Current for Given Rsc

In general, for a given Vo, Isc limit, and case temperature·
Tc. Rse;: can be calculated from the equation below for Vo
positive, lOUT positive.
Rsc = (20.6Vo)" +680-2.2 (Tc-25°C)
ISC(LIMIT)
"For Vo negative, replace this term ~ith 10.3 (Vo-1.2)
For example. for 10

= 1.5A @ Vo
A

sc

= 25V and T c

= 25°C,

= 1195 = 0.797
1500

Therefore for this application, Rsc = .820 (closest standard
value)
When 0.820 is used, Isc @ Vo = OV will be reduced
to abou,t lA.' Except for small changes in the' u±VO(max)
Limit" area, the effects of changing Rsc on the lOUT vs VOUT
characteristics can be determined by merely changing the
lOUT scale on Fig. 1 to'correspond to the new value. Changes
in Tc move the limit curve bodily up and down.
This internal power limiting circuitry however does not at all
restrict the normal use of the driver. For any normal load, the
static load line will be similar to that sholl)ln in Figure 1.
Clearly,' as Vo decreases, the 10 requirement falls also,
more steeply than the 10 available. For reactive loads, the
dynamic load lines are more complex. Two typical operating
point loci are sketched here:
5·241

Maximum junction temperature
Ambient temperature
Thermal resistance from transistor junction to
case of package
RHCH=
Thermal resistance from case to heat sink
RHHA=
Thermal resistance from heat sink to ambient air
And since
200°C for silicon transistors
2.0C/WATT for a steel bottom TO-3 package with
die attachment to beryllia substrate to header
.045°CIW for 1 mil thickness of Wakefield type 120
thermal joint compound
.09°CIW for 2 mil thickness of type 120
.13°CIW for 3 mil thickness of type 120
.17°CIW for 4 mil thickness for type 120
.21°C/W for 5 mil thickness of type 120
.24°C/W for 6 mil thickness of type 120
The choice of heat sink that a user selects depends
upon the amount of room available to mount the
heat sink. A sample calculation follows: by
choosing a Wakefield 403 heat sink, with free air,
natural convection (no fan!. ROHA '" 2.0°CIW.
Using 4 mil joint compound,
200~C-TA

Po =

2.0° + 0.17" + 2.0

200°C-TA,
4.17°C/W

200"C -25°C = 42W
,4.17°C/W
and @ TA = 125°C,
200"C -125°C' = l8W
4.17"C/W
From Fig. 2 the worst case steady state power dissipation for an
IH8520 (Rse = 0.620) is about 30W and 18W respectively. Thus
this heat sink is adequatE!.

[I

ICH851 0/8520/8530
TYPICAL PERFORMANCE CURVES

For ICH 8520, multiply

10Ul by 0.67
Rsc O.SII

ICH 8530

10Ul

3.0A

TeASE 125°C

For ICH 8510, multiply
lOUT by 0.33

Rse

1.2n

Source Current

only Is shown.
Sink Current
is Idenlical with
Reversed Scales.
Derate Linearly
Between Curves
with Temp.

·30

·25

-20

-15

-10

10

-5

15

20

'25

30V Your

-30 -25

Figure 2: Safe Operating Area; lOUT vs VOUT

VS

-20

-15

-10

-5

10

15

20

2S

Tc

10K

Volfset(mv)

1S

10

}---~"""-+VOUT

10

15

20

25

30

Pkg. Power Diss. (W)
"Set switch on Vln to gel desired Power Oiss., then
switch to Gnd, 10 read offset (Vour '" 11 x Vottset)

Figure 3: Input Offset Voltage vs F'0wer Dissipation
Input Ir:rtpedance (Mn)

RI

30r-R_'__O_(~U_n;~IY_G~'~in~)__________,

20t-R_'__S_KJ_'______________

RI 10Kn
1 0 t - - - - - - - - - - - - -_____
RI

lOOKn

10Hz:

100Hz

1 KHz

10KHz

Freq.

Figure 4: Input Impedance vs Gain vs Frequency
Oulescent current from·
either +Vcc or -Vee (rna)

10K

80

60

40

"'~provided the de.vice has
adequate heat sink. A curve of power dissipation vs Va
under short circuit conditions is given in Figure 12. The
limiting circuit is more closely dependent on case
tel1')perature than (output transistor) junction
temperatures. Although these operating conditions are
unlikely to be attained in actual use. they do represent the
limiting case a heat sink must cope with .. For fully safe
design. the anticipated range of Va values that could
occur. (steady state. including faults) should be examined
for the highest power dissipation. and the device provided
with a heat sink .that will keep the junction temperature
below 200 0 C and the case temperature below 150 0 C with
the worst case ambient temperature expected.

Source direction shown
Pdiss
For sink, reverse Your searle. _ _ _ _ _-40-W-_..¥' TA·- 2S"C

. RI
Av

RI+Ri
RI

.,

.",.-'

............

--

.

,.,... _.-.

Transients only

...........

Figure 10:
Non-Inverting Amplifier

Figure 11:
Inverting Amplifier

2SV

20V

20
10

./."
-VOUT 30V

30

15V

10V

SV

5V

10V

15V

20V

Figure 12: Power Dissipation under Short Circuit Conditions

TYPICAL APPLICATIONS
II. Obtaining Up To 5 Amps Output Currerit Capability By
Paralleling Amplifiers

I. Actuator Driving Circuit (24-28 VDC rated)

10K

·9K

,.

-30Y

01

Actuator

/Plston
Actuator

V'N

~~~~~or)

Your

lK

Figure 13: Power Amp Driving Actuator

Figure 14: Paralleling Power Amps for Increased Current
Capability

The gain of the circuit is set to +10. so a VIN = +2.4V will
produce a +24V output (and deliver up to 2.7 amps output
current). To reverse the piston travel. invert VIN to -2.4Vand
VaUT will go to -24V. Diodes D1 and D2 absorb the inductive
kick of the motor during transients (turn-on or turn-off); their
breakdown should exceed GOV.

This paralleling procedure can be repeated to get any desired
output current. However. care must be taken to provide sufficient load to avoid the amplifiers pulling against each other.
5·244

ICH851 0/8520/8530
III. Driving A 48VDC Motor

OK
+30Y

Overellrren' P,otei::tlo~
. Circuit

--------1

A YIN - +2.4Y

I
I

will deliver output
0148Y
acro •• m·olor

I
I

J

I
I
I
I

lK

I
I
I
L _ _ _ _ _ _ _ _ _ _ .JI
-For currenl protection R1 '" D,7V

Ima.

+30V

Figure 15: Power Amp Driving 48 VDC Motor

m

2. Simply vary the DC driving voltage to valve. Most valves
obtain full'opening as an inverse of applied voltage, i.e.,
valves open 100% in five seconds at 24VDC and in 10
seconds at 12VDC.
A circuit to perform the second method is shown belo\\(;
the advantage of this is that digit switches can precisely
set driving voltage to 0.2% accuracy (8-bit DAC), thereby
controlling the rate at which the valve opens.
,

IV. Precise Rate Control of an Electronic Valve
There are two methods to get very fine control of the opening
of an orifice driven by an electronic valve.
1. Keep the voltage constant, i.e., 24VDC or 12VDC,
and vary the time the voltage is applied, i.e., if it
takes five seconds to completely open an orifice
at 24VDC, .then applying 24V for only 2V2 seconds
opens it only 50%.

10K

~15V

+5V rei
·15V

11. 1,1~
0

ele~lronic

d;9"

valve

.w;""..

Figure 16: Digitally Controlled Electronic Value

V. The circuit presented in Fig. 16 is also an excellent way to

build a preCision variable power supply using a BCD coded
DAC with BCD Thumbwheel switches.

get a precise power supply voltage; in fact, it is possible to
4K

'15V

-30Y . +35V
unregulated input

I

#01 bits depends
upon desi~,ed accuracy

20
1
1
0
0

.......--<

~"r"',

,-sv ref.

1

digit switches

4K + lK)
Your = !:5Y ( ~

J<

,

-30Y--3SY unregulated input

.

digital It set by ~ws. and ~an deliver up 10 3 amps.

21
1
1
1
1
0
0

22
1
1
0
0
0
0

23
1
1
1
1

0
0

24
1
1
1
1
0
0

25
1
1
0
0
0
0

26
1
1
0
0
0
0

27
1

0
0

o BIT
1
0
1
0
1
0

Vout
+25VDC
-25VDC
+15VDC
-15VDC
+0.098VDC
-0.098VDC

Etc.

-

Figure 17: Digitally Programmable Power Supply
5·245

The power supply can be set to :!:O.1VDC.

ICH851 0/8520/8530
VI.

processor (local) or C.P.U. program the D/ A converter.
Then total, pre-programmable, electronic control of an
actuator, electronic valve, motor, etc., is obtained. This
would be used in conjunction with a transducer/multiplex
system for electronic monitoring and control of any electromechanical function.

There is great power available in the sub-systems shown in
IV alld V; there the D/ A converter is shown being set
manually (via digit switches) to get a precise analog output
(binary # x full scale voltage), then the driver amplifier
multiplies this voltage to produce the final output voltage. It
seems obvious that the next logical step is to let a micro-

ELECTRONIC CONTROL SYSTEM:

MUX = INTERSIL IH5060 (1/16) or IH5070 (2/16)
. S/H (SAMPLE & HOLD) = INTERSIL IH5111
D/A CONVERTER = INTERSIL 7520 or INTERSIL 7105
POWER AMP = IH8510 (1 AMP) or IH8520 (2 AMP) or
IH8530 12.7AMPI
AID CONVERTER = ICL8052/71 03 or ICL8052/7104
}l COMPUTER = IM6100 family:
TO AID STROBE eNTRl.

HEATER OR MOTOR
OR SOME POWER
CONVERTER

Ii!

TO O/A CONVERTER

HEAT SINK INFORMATION
Heat sinks are available from Intersil. Order part number 290305 1$10.00 ea.) with a RHHA =1.3° C/watt. A convenient

mating connector is also available. Order part number 290306 ($4.50 ea.l.

NOTE: This product contains Beryllia. If used in an application where the package integrity may be breached and the internal parts crushed or
machined. avoid inhalation of the dust..
.

5-246

leH8SiS
Power Amplifier
Motor & Actuator Driver
KEY FEATURES:

DESCRIPTION:

• Delivers up to 1.5 amps @ +12VDC (±15VDC
supplies)
.
, • Protected against inductive kick back by internal
power limiting .
• Programmable current limiting (short circuit
protection)
• Package is electrically isolated (allowing easy heat
'
sinking)'
. • DC gain> 100dB
• Popular 8 pin TO-3 package
• Internal frequency compensation
• Can drive up ,to 0.033 horsepower motors
• Pin equivalent to ICH8510/20/30 family

The ICH8515 is a hybrid power amplifier specifically
designed 'to ilrive linear and rotary actuators, electronic
valves, push-pull solenoids, and DC &. AC motors.
The design uses a conventional 741 operational amplifier, a
special monolithic driver chip (BL8063), NPN & PNP power
transistors, and an internal frequency compensating
capacitor. The chips are mounted on a beryllium oxide
substrate, for optimum heat transfer to the metal package;
this substrate provides electrical isolation between
the amplifier and the metal package.
The 8515 has special SOA ·(safe operating area) Circuitry
which allows it to withstand a direct short to ground or to
either supply indefinitely. It has been designed to operate
with ±12 or ±15VDC supplies and will deliver typically 1.5
to1.8A@13Voutusing +15V supplies.
Internal frequency compensation provides stability, down to
unity gain (either inverting or noninverting) even when using
inductive loads.

SCHEMATIC DIAGRAM

v'

7

H---.JINIr-"""RSC'

-=

6

+----+--=--:---<>YOUT
5

1--..--+'INIr-~RSC·

I

.

Y·

PIN CONFIGURATION (OUTLINE DWG. KA)

ORDERING INFORMATION

(TOP VIEW)

DEVICE

TEMPERATURE

OUTPUT

ICH8515MKA
ICH85151KA

-55°C to +125°C
~20°Cto + 85°C

1.5A
1.25A
Y-

5-247

Rsc

leMeSiS

O~DR.

ABSOLUTE MAXIMUM RATINGS @TA'=2SoC
Supply V.oltage ..••..••.••••.•••••..•••...••.•..••.••••.••••••••••..••••. ±18V
Power Dissipation, Safe Operating Area •.••..•.•••.••.••••••••••• ,.. See Curves
Differential Input Voltage ••••••••.•• , .......... " .... ~ ................... ", ±30V
Input Voltage .................................................... ±1SV (Note 1)
Peak Output Current ...................' .................... See Curves (Note 2)
Output Short Circuit Duration (to ground) ....••....•...•.' ... Continuous (Note 2)
Operating Temperature Range M ••• __ ..••.•••...•.......•..•.. -5SoC - +12SoC '
( ....•. " .•.•..,.................. -20°C - +8SoC
Storage Temperature Range ................................... ~SoC to +1S0°C
Lead Temperature (Soldering, 10 seconds) .•••••••••••••••.•••.•.•••••••. 300°C
Max Case Temperature .• : .•, •. : ..................... ',' .'•••• '.......... :...• '1S0°C
Note 1: Rating applies to supply voltages of ±15V. For lower supply voltages; VINMAX = Vsupp.
Note 2: Rating applies as long as package dissipation is not exceeded for heat sink attached.
Stresses above those listed under Absolute Maximum Ratings may cause permanent'damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated i~ the operational sectioris of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
." '

OPERATING ,CHARACTERISTICS TA

\

= +2SOC. Vsupp = ±1SV (unless otherwise stated)

,

ICH85151

PARAMETER

SYMBOL

TEST CONDITIONS

Input Offset Voltage
Change with
Power Dissipation

L\Vos/L\Pd

Mtd. on Wakefield
403 Heat Sink

Input Offset Voltage

Vos

Rs'" 10kO, Pd < 1W

Input Bias Current

ISlAS

Rs'" 10kO, Pd < 1W

Input Offset Current

los

Rs'" 10kO, Pd < 1W

Large Signal Voltage Gain

AVOL

RL = 100,
Vo > '2/3 Vsupp

MIN.

TYP.

ICH8515M
MAX.

MIN.

TYP.

'MAX.

UNITS

2

mV/W

4

I

\

-6

1

6

-3

0.7

SOO.
200
100

,--

-,10

3

mV

2S0 'nA
100
100

nA
dB

Input Voltage Range

VCMR'

Common Mode
Rejection Ratio

CMRR

Rs

= 10kO

70

70

dB

Power Supply
Rejection Ratio'

PSRR

Rs

= 10kO

77

77

dB

Slew Rate

SR

O.S

O.S

V/p.s

Output Voltage Swing

VOMAX

RL

±12

Output Current

IMAX

RL

±1.25

Power Supply
Quiescent Current

IQ

CL = 30pF, Av = 1,
,RL = 100
Vo '" 2/3 Vsupp

= 100, Av = 10
= SO, Av = 10
RL = ex:, VIN = OV

OPERATING CHARACTERISTICS (continued)TA
Input Offset Voltage

Vos

Input Bias Current

ISlAS

.

+10

+10

±12
1.4
80

±1.S'

-10

+10

70

los

Large Signal Voltage Gain

AVOL

RL = 100,
L\ Vo = 2/3 Vsupp

Output Voltage Swing

VOMAX

RL

-9

, +9

Thermal Resistance
Junction to Ambient

R9JA

Without Heat Sink

Thermal-flesistance
Juriction to Case

R9JC

Thermal ,Resistance
Junction to Ambient

R9JA

Supply Voltage Range

Vsupp

90

±10

±10

mV
nA
dB

.'

V

40

40

oeM

3.0

3.0

°C/W

4.S
±1'1

5·248

200

90

Mtd, on Wakefield
403 Heat Sink

mA

7S0' nA

500

= 100, Av = 10

A
100

-20°C. to +8S0C. (I)

1500

Input Offset Current

V

V
1.8

12S

= -Ssoc. to +12soC.(M) orTA =

Pd<1W
' Pd<1W

-10

4.S
±17

±11

°C/W
±17

V

,

leH8SiS
How To Set The Externally Programmable,
Current limiting Resistors:

The maximum output current is set by the addition of two
external resistors, A se and A se. Because of the current
power limiting circuitry, the maximum output current is
available only when Va is close to either power supply. As
Vo moves away from Vsupp, the maximum output current
decreases in proportion to output voltage. The curve below
shows maximum output current versus output voltage.
Rse

~

0.62!! .5W

lOUT

Te ~ 25'C

Inductive Load
(Note catch diode)

Capacitive Load

Thus the limiting circuitry protects the load and avoids
needless damage to the driver during abnormal conditions.
For any 12VDC motor/actuator, the Ase resistors must be
calculated to get proper power delivered to the motor (up to a
maximum of 1.5 amps) and Vsupp set at ±15V. For lower
supply and/or output voltages, the maximum output current
will follow graphs of Figures 1 and 9.

Vsupp::: ±15V

-15V
,VOUT

MAX

NOTE ON AMPLIFIER POWER DISSIPATION
The steady state power diSSipation limit is given by

p _

TJ(MAX) - TA

o - AeJc + RecH + AeHA
where
TJ =
TA=
AeJc=

) - - - - - . Vour
Rge

Figure 1: Maximum Output Current for Given Rsc

In general, for a given Va, Ise limit, and case temperature
Te, Ase can be calculated from the equation below for Vo
positive, lOUT positive.
Asc = (20.6Vo)* +680-2.2(Tc- 25°C)
Isc (limit) in mA
* For Vo negative, replace this term with·1 0.3 (Vo-1.2)
For example, for 10 = 1.5A @ Va =12V and Tc = 25° C,
Asc = (20.6)(12) +680 = 927.2 = .618
1500
1500
Therefore for this application, Asc = .62!l (closest standard
value)

Ii

Maximum junction temperature
Ambient temperature
Thermal resistance from tra.nsistor junction to
.
case of package
ROCH= . Thermal resistance from case to heat sink
ReHA=
Thermal resistance from heat sink to ambient air
And since
150°C for silicor) transistors
TJ =
ReJc '"
2.0CIWATT for a steel bottom TO-3 package with
die attachment to beryllia substrate to header
RecH=
.045°CIW for 1 mil thickness of Wakefield type 120
thermal joint compound
.09°CIW for 2 mil thickness of type 120
.13°CIW for 3 mil thickness of type 120
.17°CIW for 4 mil thickness for type 120
.21°CIW for 5 mil thickness of type 120
.24°ClWfor 6 mil thickness of type 120
ReHA=
The choice of heat sink that a user selects depends
upon the amount of room available to mount the
heat sink. A sample calculation follows: by
choosihg a Wakefield 403 heat sink, with free air,
natural convection (no fan>. ReHA '" 2.0°CIW.
Using 4 mil joint compound,
PD =

When 0.62!l is used, Isc @ Va = OV will be reduced
to about 1A. Except for small changes in the. "±VO(max)
Limit" area, the effects of changing Ase on the lOUT vs VOUT
characteristics can be determinE1d by merely changing the
lOUT scale on Fig. 1 to correspond to the new value. Changes
in Te move the limit curve bodily up and down.
This internal power limiting circuitry however does not at all
restrict the normal use of the driver. For any normal load, the
static load line will be similar to that shown in Figure 1.
Clearly, as Va decreases, the 10 requirement falls also
more steeply than the 10 available; For reactive loads, the
dynamic load lines are more complex. Two typical operating
point loci are sketched here:
5-249

150°C-TA
2.0° + 0.17° + 2.0

150°C-TA
4.17"C/W

or@TA = 25°C,
150°C -25°C
4.17°C/W

30W

and @ TA = 125°C,
150°C -125'C
4.17"C/W

6W

From Fig. 2 the worst case steady state power dissipation for
the IH8515 (Asc = 0.62m is about 15W and 11W respectively.
Thus this heat sink is adequate.

ICH8515
Rsc

=

TC~

RSC

O.62fl

Tc

25"C

~

=

0.620

10

125"C

VSUpp = ::!:1SV

VSUpp = :!:1SV

1.5A

0.5

-15

-10

+5

-5

+10

+15

Vo

-15

Figure 2: lOUT

VS.

-10

-5

o

+5V

+10V

+15V

VOUT

TYPICAL PERFORMANCE CURVES
10k

VolIl.t(rny)

15

10
} - - - - . . -........ VOUT

1011

10

15

20

25

30 Pkg. Power Diss. (W)

*Set switch on Vln to get desired Power Diss., then
swltoh to Gnd. to read offset (VOUT =:= 11 x Voffset)

Figure 3: Input Offset Voltage vs Power Dissipation
Inpul Impedance (Mil)

Rf

30t-_R_f=
__
0~(U~n~l~tY~G=a=in~)__________,

Rf = SkI!

20r-----~--

________~

10t-R_f_=_1~0~k~I!~___________

Rf = 100kll

10Hz

100Hz

1kHz

10kHz

Freq.

Figure 4: Input Impedance vs Gainvs Frequency

Quiescent current from ..

either V+ or V- (ma)

60

50.
1k

40

o
5
·they

10

ar~ approX: equal

15
Power Supply Voltages

Figure 5: Quiescent CU,rrent vs Power Supply Voltage

5-250

O~OIL

leH8SiS
Your 'pow.er band width Your 2: ±67% Vee

RI

100kHz

10kHz
lk

1kHz

}--~""",""~VOUT

Vln@1

lOU

10

-=

100 Closed loop gain

Gain = Rl7k:lkll

Figure 6: Large Signal· Power Band Width

CL ,; 1000pF lor
Adequate Stability

Closed loop Gain

100

+:::;--::=,--_.......

RI

CL +5000pF

RI = 99kll
CL +100pF

10~R~I-=~9~k!~I------~~\

lk

RI = Oil

10Hz

Vin@1

100Hz 1kHz 10kHz 100kHz

treq(Hz)

Figure 7: Small Signal Frequency Response

Max. Output Current (Amps) @ Your :::: ±12V, Vsupp :::: ±15V

1.5A

1.0A

~2{j(31V1
-.~

0.5A

. 12!\

0.5A

OA ---+---t--+----t--+--~t__-_+__ VSU??
±5V
±10V
±15

OA~-+--+-~---r--~-+--+-~r-~

-25

+25

~

+50 +75 +100 +125
Ca.e Temp. (Te) (OC)

-l;5

Figure 8: Maximum Output Current vs. Case Temperature

Figure 9: Maximum Output Current vs. \lsupp

5·251

O~OIb

ICH8515
TYPICAL APPLICATIONS
I. CONSTANT VOLTAGE DRIVE FOR D.C. MOTORS
Here VouTfVlN = 4, and if VIN =, -3V, VOUT = +12V, and vice
versa for VIN = +3V. Diodes Dl,·D2 should be lN4001types;
these absorb the inductive kickbacks of the motor. The 2000pF
Miller capacitor is used to prevent system oscillation, by
providing gain rolloff @.approx. 20kHz (-3dB). •

II. CONSTANT CURRENT DRIVE FOR D.C. MOTORS
Rt

r-----i

I
V,N

r-------]
L

I

O.C. MOTOR

R

I

I

L ______ l

V,N
-15V

5

I

1

.

RL ' assuming RI ». RL.

This circuit allows precisely set motor drive current with op.
amp. feedback accuracy. If RN = RF = lkn, and RL = lon,
I
.
then _L_ = -0.1 Amps/Volt, andi! RL = 1!1 (use 4W or more)
V~
.
and RF = RIN = lkn, ...!h..=-1 x 1 = 1 Amp. Thus if VIN = 1.5V,
VIN
Volt
1.5 amps will flow thru the motor. Since one side of the
motor will have a 1.5V drop (with respect to GND), the Vo point
will go to 13.5V and develop 12V acr?ss motor.

+15V

I 12V

R

-15V

IL
RI
VIN = - RIN •

I

L

HEAT SINK INFORMATION.

.

Heat sinks are available from.lntersi!. Order part number 290305 ($10.00 eaJ with aRRHA = 1.3°C/watl. A convenient

mating connector is also available .. Order part number 29·
0306 ($4.50 eaJ.
.

NOTE: This product contains Beryllia. If used in an application where the package integrity may be breached and the internal parts crushed or
machined, avoid inhalation 01 the dust.

5·252

..>.,'. : .'"
", , ' . ' ,

, ~

\. ~

".,~:

.,.::...::".'

Zr~~;:

.~.:

··:~·t'

.'

.•. ;.\.

,}I~i:m.r.'

.'
... :

... , .

:",~'

'... .. .. ,

;Dounte'r's'"" ,: .,

.,.!~;.·;fjq~'l:Ii'l'~V;.•·Drl~~'~~~~,i~~:. .
=.::-:.¥.....:.~>:~';~:'",,'

.....',

- ,"'

,'~ .:.....~: ';.. y.... :>....;..~~,;....~,,-"":~:y . . :...:.,.,....

','

Display Drivers

Timers
NE/SE555
NE/SE556
ICM7240/50/60
!CM7242
ICM7555
ICM7556

Page
6-3
6-7
6-123
6-134
6-140
6-140

Counters
ICM7208
ICM7216
ICM72J7127
ICM7224/25
ICM7226
ICM7236

6-15
6-40
6-55
6-76
6-83
6-118

ICM7211/12
ICM7218
ICM7231-34
ICM7235

6-25
6·67
6-94 .
6-112

Oscillator/Clock'
Generator
ICM7209
ICM7213

'.

,,;:

'

": ....

i '.

6-22
6-35

Low Battery
Indicator
ICM7201

6-9

.Counter Timebase
'""': :'

ICM7207/A

6-11

~ounters,

Timers and Display Drivers
Output
Crystat fr~quency
Seconds: 1,31 MHz Seven-digit common-cathode LED drive,
Minutes: 2.18 MHz
Displays up to 240.000 seconds, 2,400
'Hours: 3.64 MHz'
minutes, 24-hours.

Part Number
ICM7045A

Circuit Description

Package',

Complete industrial stopwatch precision decade
timer to count seconds, minutes or hours by
selection of suitable oscillator. frequencies.

28-Pin DIP

ICM7201
ICM7206

Low battery voltage indicator
Touch-tone encoder; requires single contact per key.

TO-72

Not applicable

16-Pin DIP

3.~7954

ICM7206A

Touch-tone encoder; requires one contact per key
with common line connected to + supply,

16-Pin DIP

MHz
3,57954 MHz

Lights LED at voltage below 2.9V.
2-of-8 sine wave for tone dialing
2-of-8 sine wave for tone dialing

\

ICM7206B'

Touch-tone encoder; requires 2 contacts per key
with common line connected to'~egative supply;
oscillator ,enabled when key is ~ressed.

16-Pin DIP

3,57954 MHz

2-of-8 sine wave for tone dialing

ICM7206C

Touch-tone'encoder requires single contact per
key; osciltator enabled only when ,key' is
depressed,
,
Frequency counter timebase.

16-Pin DIP

2.57954 MHz

2-oi-8 sine wave for tone dialing

7-digit unit counter. With addition of 7207 the
circuit becomes a complete timer-frequency
counter.
High-frequency clock-generator for 5-volt systems'

28-1'in DIP

ICM7207
ICM7202A
ICM7208

ICM7209
ICM7211
ICM7212
ICM7213
ICM7216
. .lCM7226

DJ

14-Pin DIP
lHin DIP

8-Pin DIP
40-Pin DIP (plastic)

'Four-digit display decoder drivers; ICM7211 is
LCD; ICM7212 is LED; Non-multiplexed for low
noise, BCD input, decoded display drive output,

,6,5536 MHz
5.2488 MHz

0.Ql, 0.1, or I-second cOUht window plus
stor~, reset and MUX.
LED display, drive

to'10MHz

Crystal frequency, plus

8 divider stage

Four-digit. seven-segment direct display
drive; LED or LCD

I

Oscillator and f~equency divider
Eight-digit universal counter measures frequency,
period, frequency ratio. time interval. units;
on-board time base,

lHin DIP (plastic)

to 10 MHz

lpps, lppm, 10 Hz, composite

28-Pin DIP
40-Pin DIP
(Cerdip or plastiC)

lor 10 MHz

Eight-digit-common anode or common
'cathode direct LED'drive; BCD output

ICM7217
ICM7227

F9ur-digit CMOS up/down counter; presettable
start/count and compare register; fQr hardwired or microprocessor control applications;
cascadable,

28-Pin Cerdip
,or plastic

Four-digii, seven-segment common anode
or common cathode direct LED display
drive; equal. zero, carry/borrow

ICM7218A1D '
ICM7218E

LED display driver system with 8x8 memory;
numeric or dot (t of 64) decoding;
microprocessor compatible.
4'h-digit high speed counter/decoder/driver;
25 MHz typ; ICM7224 is LCD, ICM7225 is LED;
.direct display drive, cascadable.

'28-Pin DIP
40-Pin DIP,
(Cerdip or plastic)
40-Pin DIP
(plastic)

Eight-digit, seven-segment plus decimal
' point; common cathode or common
anode
.4'i,-digit seven-segment direct display
driver; LED or LCD '

ICM7224
ICM7225
ICM7231

8-digit CMOS multiplexed LCD driver...
Parallel input.

40-Pin DIP (plastic)

Eight-digit. seven-segment pius two flags
per digit
.

ICM7232

10'/,-digit CMOS multiplexed LCD driver,
Serial input.
'

40-Pin DIP (plastic)

ICM7233

4-C)laracter CMOS multiplexed LCD driver.
Parallel alphanumeric (6-bit ASCII) input.

40-Pin DIP (plastic)

10V,-digit. seven-segment' plus two flags
per digit
Four-character, 16-segment plus colon

ICM7234

5-character CMOS multiplexed LCD driver.
Serial alphanumeric (6-bit ASCII) input.

40-Pin' DIP (p!asiiC)

, Five-character, 16-segment 'plus colon

ICM72~5/A

4-digit CMOS decoder/driver for direct drive
vacuum fluorescent displays, BCD input.

40-Pin DIP (plastic)

Four-digit, seven-segment. vacuum
fluorescent display drive; either HEX
orCODE B

ICM7235M / Af,I

Same as above but microproces,sor compatible.

ICM7236

4'I1-digit high speed ,CMOScounter/decoder/driver
for vacuum fluorescent displays; 25MHz typo
counting Speed.

40-Pin DIP (plastic)

4'h-digit. seven-segment: vacuum
fluorescent display drive

ICM7236A '

'Same as above but counting to 15959.

40-Pin DIP (plastic)

4'h-digit. seven-segment. vacuum
fluorescent display drive

ICM7240
rCM7250
, ICM7260

Programmable CMOS counter/timers using
external AC time base. Programmable from
!'s to years.

,

ICM7242

Fixed CMOS counter/timer .. Uses external AC
time base; sequence timing from!,s to minutes.

8-Pin DIP

ICM7243

a-character multiplexed LED display driver with
alphanumeric (6-bit ASCII) input.

40-Pin Cerdip

Single or dual 'CMOS version of lndust;y-standard
555 timer: aO,!,A typo supply current: 500 kHz
guaranteed: 2-18V power supply.

8-Pin DIP
lHin DIP

.UCM7555
ICM7556

External

Timed output

External

Timed output

16-Pin DIP

6·2

Eight-character, 14/16-segment common
cathode alphanumeric LED display drive

555
Precision Timer

FEATURES
•
•
•
•
•
•

GENERAL DESCRIPTION

Timing from microseconds through hours
Operates in both astable and monostable modes
Adjustable duty cycle
High current output can source or sink 200mA
Output can drive TTL
.
Temperature stability of 0.005%/° C

APPLICATIONS
•
•
•
•
.•
•
•

Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Missing Pulse Detector

TheNE/SE 555 monolithic timing circuit is a highly stable
controller capable of producing accurate time delays, or
. oscillation. Additional terminals are provided for triggering
or resetting if desired. In the time delay mode of operation,
the time is precisely controlled by one external resistor and
capacitor. For stable operation as an oscillator, the free running frequency and the duty cyCle ,are both accurately
controlled with two external resistors and one capacitor; the
circuit may be triggered and reset on falling waveforms, and
the output structure can source or sink large currents or
drive TTL circuits.
.

PIN CONFIGURATIONS

BLOCK DIAGRAM

(OUTLINE DRAWING JD)

CONTROL
VOLTAGE

GND
NC
TRIGGER

DISCHARGE
NC

OUTPUT
NC

THRESHOLD

RESET

NC
CONTROL
VOLTAGE

NC

(OUTLINE DRAWING PAl

G R O U N D O B v+
TRIGGER
2
7
DISCHARGE
OUTPUT

3

6

THRESHOLD

,RESET

4

5

eg~i~g~

ORDERING INFORMATION
NE555/D

QOC to +7QoC

Dice

NE555F

14 pin CERDIP

NE555N

8 pin plastic DIP

NE555T

TO-99 can

SE555/D

-55° C to +125° C

(OUTLINE DRAWING TO-99)
V+

Dice

SE555F'

14 pin CERDIP

SE555T'

TO-99 can.

TRIGGER

'Add /8838 to order number if 8838 processing is desired.

6·3

2

6

THRESHOLD

til

555
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................. : ............•........................... +18V
Power Dissipation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 600mW
Operating Temperature Range,
NE555 ........ : ......,....................,...................... O°C to +70°C
SE555 ..•...................................... : ....... ',' ... -55~ C to +125° C
Storage Temperature Range ..•................................ -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) .............................. +300°C

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS; TA = 25°C, V+= +5V to +15 unless otherwise specified.
PARAMETER
Supply Voltage
Supply Current

TEST CONDITIONS

Timing Error
Initial Accuracy
Drift with Temperature "
Drift with Supply Voltage
, Threshold Voltage'
Trigger Voltage ,
Trigger' Current
Reset Voltage
Reset Current
Threshold Current
Control Voltage Level

MIN
4.5

V+- 5V RL - '"
V+-15VRL-'"
Low Stllte, Note 1
RA, Rs - 1kfl to 100kfl
C = 0.1~F Note,2

V+-15V
V+ - 5V.

3
10

4.8
1.45
0.4

,

Output Voltage Drop (low)

,

Note 3,
V+= 15V
V+=5V
V+= 15V
ISINK = 10mA
ISINK - 50mA
ISINK - 100mA
ISINK = 200mA
V+=5V
ISINK - 8mA
ISINK - 5mA

SE555
TYP

9.6
2.9

,MAX
18
5
12

0.5
30
0.005
2/3
5
1.67
0.5
0.7
0.1
0.1
10
3.33

2
100
0.02

0.1
0.4
2.0
2.5

0.15
0.5
2.2

0.1

0.25

MIN
4.5

NE555
TYP
3
10

5.2
1.9
1.0

' 0.4

.25
10.4
3.8

9.0
2.6

1
50
0.01
2/3 ,
5
1.67
0.5
0.7
0.1
0.1
10
3.33
0.1
0.4
2.0
2.5

MAX
16
6
15

UNITS
V
mA

%
ppm/DC
%IVolt
X Vcc

V
~A

1.0

V
mA

.25
11
4

~A

.25
'.75
2.5
V

.25

.35

Output Voltage Drop (high)

>

ISOURCE = 200mA
V+-15V
ISOURCE - 100mA
V+-15V
V~+= 5V

12.5

13.0
3.0

Rise Time of Output
Fall Time of o.utput

13.3
3.3
100
100

-

12.5

12.75
2.75

13.3'
3.3
100
100

NOTE 1: Supply Current when output high typically 1mA less.
NOtE 2: Tested at V+,,;, 5V and V+ = 15V.
I
NOtE 3: This will determine the maximum value of RA + R'B for 15V operation. The maximum total R = 20 MO.

6·4

nsec

555
TYPICAL CHARACTERISTICS
MINIMUM PULSE WIDTH
REQUIRED FOR TRIGGERING
~ 150

"I

10.0

«

~+-+---t--+--I-t-t-+----l

125

E 8.0

J:

f-

e

~
w

III
..J

::iE
Z

~

.

Z

w 6.0
a:
a:

75

:::l

4.0

U

50

>..J

:::l

~

~25~C

I

f-

100

:::l

c..

~

~

~

Al ~

f - -1-~515°C
~ 1.6 F=- +25"C
ell.4

~

>I 1.2

~C

25
- 00

10

30

20

f-'"

-

+125°C

:::l

00.8

./

I 0.6

III

0.2

o

-

>

"> 0.4

40

V

LI

f-,1.0

:::l 2.0

5V";;; V+ ,.;;; 15V

I

o

5.0
10.0
15.0
SUPPLY VOLTAGE· VOLTS

1.0

2.0

5.0 10

20

II
50 100

ISOURCE -rnA

LOW OUTPUT VOLTAGE

LOW OUTPUT VOLTAGE

LOW OUTPUT VOLTAGE

.vs. OUTPUT SINK CURRENT

vs. OUTPUT SINK CURRENT

vs. OUTPUT SINK CURRENT

10

10
--

,

o~L v
'"'
1' /fl0(.) 0(.)
.,.~

1.0

g

~ 1.0
I

j.

I

It--'''

, 50.1

o

+25°C
+125°C#

f-

:::l

~ 0.1

-4

~
+125
°c

..J

I A

g
g 0.1

>

J

-55°C

~ 1.0
I
f-

'"'-55°C

>

V+ = 15V _

=t=-55°C~
+25°Ci

..J

g

-

10

V+ = 10V

V+- 5V_

:;

112~od~ ~

2.0
1.8

~

11.
11.

LOWEST VOLTAGE LEVEL OF
TRIGGER PULSE - % V+

III

HIGH OUTPUT VOLTAGE
vS.OUTPUT
SOURCE CURRENT

SUPPLY CURRENT
vs. SUPPLY VOLTAGE

+25°C~

+125°C

~

--

~- 55°C

P"

.01
1.0

2.0

5.0

10

20

50

.01
1.0

100

2.0

ISINK - rnA

50

100

i=

\

ujl.005

\

e

\

fill.000
N

0.995

---- --

--

~
..J
~

::iE

w
w

>-

1.005
1.000

- r-- r-

N

~ 0.995

g;

Z

-r-

0.990

o

5
10
15
20
SUPPLY VOLTAGE - VOLTS

:3w

Z 150~~~~~~+-~-+~

o

~
«
11.

100

(!l

a:

11.

0.985

200 ~-+----t--+-I-:7~'+--+---l

c

o

Z

0.985

PROPAGATION DELAY
vs. VOLTAGE LEVEL
OF TRIGGER PULSE
~ 250~-+----t--+-~-+--~-+---l

1.010

::iE

g; 0.990

100

5!

c

c

10

u 300r-~-r~--~~~~~

1.015

w
::iE

1.010

I
ISINK - rnA

DELAY TIME
vs. TEMPERATURE

1.015

~

~

20

I

::iE

i=

10

ISINK -rnA

DELAY TIME vs.
SUPPLY VOLTAGE
w

5.0

.01
1.0

-50 -25 0 +25 +50 +75 +100+125
TEMPERATURE _ °c

6-5

O~~~~--~~~~~

o

10
20
30
40
LOWEST VOLTAGE LEVEL OF
TRIGGER PULSE - % V+

555
. APPLICATION INFORMATION
TIME DELAY

MONOSTABLE OPERATION

vs. RA, Rs AND C
V+

RA
u.

RESET
TRIGGER
INPUT

U

::t

---

I
w

CJ

8

4
2

2

«
lo-

7

U
6

'-----0---; 3

CJ

5

. OUTPUT

«
0..
«

JC
CONTROL
VOLTAGE
01 J.lF

I·

10
J.ls

of

In this mode
operation, th~ timer functions as a one-shot.
Initially the external capacitor (G) is held discharged by a
transistor inside the timer. Upon application of a negative
trigger pulse to pin 2, a flip-flop is set which releases the
short circuit across the external capacitor and drives the

100
J.lS

10 100
ms ms
TIME DELAY

ms

10

.s

output high. The voltage across the capacitor increases
exponentially with the time constant TRAG. When the voltage
across the capacitor equals 2/3 V+, the comparator resets the
flip-flop, which in turn discharges the capacitor rapidly and
drives the output to its low state.

ASTABLE OPERATION

FREE RUNNING FREQUENCY
vs. RA, Rs AND C
V+

RL

u.

RA

::t

I

CJ
2

8

«
t-

7

om",

U

0.1

«
0..

RB

3

I'
,
_ 1

",----ji"'<---f"<--P..--+--i+-f

w

4

OUTPUT

10

I

5 0.01

6

2

I

1

I

10

C

100

FREE RUNNING FREQUENCY - Hz

the charge and discharge times, and therefore the frequency
are independent of the supply voltage.

The circuit can also be connected to trigger itself and free run
as a multivibrator. The external capacitor charges through
RA and Rs and discharges through Rs only .. Thus the duty
cycle may be precisely set by the ratio of these two resistors:
In this mode of operation, the capacitor charges and discharges between 1/3 V+ and 2/3 V+.As in the triggered mode,

. .
b f 1
Th e f requency 0 f OSCI'11;
atlon IS given y: =

t _ (RA1.46
+ 2Rs) G

6·6

D~DIb

.556
Dual Precision Timer

FEATURES

GENERAL DESCRIPTION

• Timing from microseconds to hours
• Operates in both astable and monostable
time delay modes
• High output current
• Adjustable duty cycle
• TTL compatible
• Temperature stability of 0.005%/ ° C

The NE/SE556 Dual 555 Monolithic timing circuit is a highly
stable controller capable of producing accurate time delays
or oscillation. Timing is provided by an external resistor and
capacitor for each timing function; the two timers operate
independently of each other sharing only V+ and ground. The
circuits may be triggered and rellet on falling waveforms. The
output structures will sink or source 150mA.

APPLICATIONS
•
•
•
•
•
•
•
•
•
•
.'
•
•
•

Precision Timing
Sequential Timing
Pulse Shaping
Pulse Generator
Missing Pulse Detector
Tone Burst Generator
Pulse Width Moduli)tion
Time Delay Generator
Frequency Division
Industrial Controls
Pulse Position Modulation
Appliance Timing
Traffic Light Control
Touch Tone Encoder

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................... +18V
Power Dissipation" ......................... .' .... 800mW
Operating Temperature Range NE556 ..... O°C to +70°C
SE556 .. -55°C to +125°C
Storage Temperature Range ............ -65° C to +150° C
Lead Temperature (Soldering, 60 sec) ............ +300° C
'Derate linearly at 6.5mV/oC above ambient temperature of 75°C.

m

r--------~----.,W
BLOCK DIAGRAM

PIN CONFIGURATION
DISCHARGE

v+

THRESHOLD
DISC,HARGE

, - - - - - - - - 1 DISCHARGE
THRESHOLD

THRESHOLD
CONTROL

VO~Tts~~ 1'--1_--,

CONTROL
VOLTAGE
RESET
OUTPUT

CONTROL

,..--+-i ~~~:¢GE

THRESHOLD
CONTROL
VOLTAGE
RESET
OUTPUT

GROUND

TRiGGER

(OUTLINE DRAWINGS JO, PO)

OUTPUT Hf---'

'---H OUTPUT

ORDERING INFORMATION
NE556/D DOC to +7DoC
NE556F
NE556N
SE556/D -55°C to+125°C
SE556F"

GROUND L-_______________- ,_ _- '

Dice
14 pin CERDIP
14 pin plastic DIP
Dice
14pin CERDIP

"Add 18838 to order number if 8838 processing is
desired.

6·7

D~DIb

556
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: TA = 25° C. V+ = +5V to +15 unless otherwise specified.
SE556
PARAMETER
TEST CONDITIONS
MIN
TYP
4.5
Supply Voltage
3
V+,... 5V RL -.,
Supply Current
10
(each device)
V+= 15V RL =.,
Low State. Note 1
Timing Error (Monostable)
RA = 2Kn to 100Kn
0.5
C =0.1JiF Note 2
Initial Accuracy
30
Drift with Temperature
0.05
Drift with Supply
Voltage
Timing Error (Astable)
RA.Rs - 2KH to 100KH
Initial Accuracy
1.5
C = 0.1JiF Note 2
90
Drift with Temperature
Drift with Supply
0.15
Voltage
2/3
Threshold Voltage
Note 3
30
Threshold Current
V+= 15V
4.8
5
Trigger Voltage
V,+= 5V
1.45
1.67
Trigger Gurrent
0.5
0.4
0.1'
Reset Voltage
Reset Current
0.1
Control Voltage Level
V+= 15V
9.6
10
3.33
2.9
V =5V
Output Voltage (low)
V+= 15V
0.1
ISINK = 10mA
0.4
ISINK = 50mA
2.0
ISINK - 100mA
2.5
ISINK - 200mA
V.+=5V
0.1
ISINK = 8mA
Is INK - 5mA
Output Voltage (high)
12.5
ISOURCE = 200mA
V+= 15V
-ISOURCE = 100mA
V+= 15V
13.0
13.3
3.0
3.3
V+='5V
Rise Time of Output
100
Fall Time of. Output
100
Discharge Leakage Current
20
Matching Characteristics
.(Note 4)
0.05
Initial Timing Accuracy
Timing Drift with
Temperature
±10
Drift with Supply
0.1
Voltage

MAX
,18
5
11

MIN
4.5

NE556
TYP
3
10

1.5
100
0.2

MAX
16
6
14

1.0

0.4

10.4
3.8

9.0
2.6

0.15
0.5
2.25

ppm;oC

2.25
150

%
ppm/oC

0.3

%N

%

%N

30
5
1.67
0.5
0.7
0.1
10
3.33

100

0.1
0.4
2.0·
2.5

.25
.75
2.75

V
nA
V

1.0

JiA
V
mA

11
4

,

0.25
.25

V

.35

12.5

100

13,3
3.3
100
100
20

100

nA

0.1

0.1

0.2

%

12.75
2.75

ns

ppm/oC

±10
0.2

0.2

0.5

NOTES: 1. Supply current when output is high is typically 1.0mA less.
2. Tested at V+ = 5V and V-: = 15V.
3. This will determine the maximum value of RA +'Ra for 15V operation. The maximum total R = 20 Mf}.
4 ... Matching characteristics refer to the difference between performance characteristics of each timer section.

6-8

mA

0.75
50
0.1

2/3

100
5.2
1.9

UNITS
V

%N

ICM7201
Low Battery Voltage
Indicator
FEATURES

DESCRIPTION

• Accurate voltage indication: 2.9 V ::; V th ::; 3.3 V

The ICM7201 is designed for use in battery operated
systems which require an indication when the battery
stack has depleted to a fixed voltage. The LED will light
at voltages below 2.9 volts; at voltages above 2.9 volts
the LED may be lit by connecting the TEST terminal to
GROUND .

• Simple to use: requires only an additional LED lamp
for complete system
'. Low power consumption: 4.5 mW at V+ = 3.6 V
• Good noise rejection - 0.2 V of hysteresis for device
threshold voltage

The ICM7201 has hysteresis designed into its
threshold voltage trigger point so that the LED will not
flicker with supply voltage noise and will not be turned
on gradually at the trigger voltage. Under all normal
circumstances the LED will either be fully on or
fully off.

SCHEMATIC ICM7201

PIN CONFIGURATION

(OUTLINE DRAWING TO-72)

v'

R,

g-

R,

T3
R,

T,

OUTPUT

R7

GROUND
(CASE)

R3

OUT

T,

R~

TEST

R5

CHIP TOPOGRAPHY

GROUND

ORDERING INFORMATION
ICM7201

c
I

DR

.
,

Package
(DR = TO·72)

'Temperatur~ ,Range
Industrial-20°C to +85°C

' - - - - - - - - - - TYPE
Order D,evices By Following Part Number - ICM72011DR
Order Dice By Following Part Number -ICM7201/0

6·9

.D~OIL

ICM7201
ABSOLUTE MAXIMUM RATINGS
Power Dissipation ....................... 100 mW
Maximum Supply Voltage .................... 5.5V
Maximum Output Current[lJ ............... 100 rnA
Operating Temperature .......... -20°C to +85°C
Storage Temperature .... : ...... -55°C to +125°C
.

.

I

TYPICAL OPERATING CHARACTERISTICS TA = 25°C, Test Circuit unless otherwise stated

PARAMETERS

SYMBOL
1+

Supply Current
Trigger

Voltag~

CONDITIONS

MIN

LED off, V+= +3.6 V
2.9

VTRIG

TYP

MAX

UNITS

1.2

2

rnA

3.1

3.3

V

Temperature Coefficient of
Trigger Voltage

LlVTRIG/LlT

Hysteresis Voltage

Vth

0.2

V

LED Current at
Trigger Voltage

ILED

VF of LED approx. 1.7 V
V+= 3.1 V

15

rnA

Test Current

ITEST

V+=3.6 V

0.5

mV/oC

-12

1.5

rnA

Note:
1. At high supply voll!iges (approaching 5 volts) it is necessary to include a cu~rent limiting resistor in serieswith the LED to limit the output
current to 100 mA maximum.
.

TEST CIRCUIT

TYPICAL OPERATING CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

·V

TA

~

25 C

1\
Ni-Cd a-CELL DISCHARGE

o
o

3.1V

BATTERY

V

.-/"

/1'

'~f-I

V

HYSTE~ES1S VOL TfGE

VOL TAGE
SUPPl Y VOL TAGE Vs

DISCHARGE T l M E -

--~

'OPTIONS
The ICM7201 can be supplied with maximum supply voltage options up to 15 volts and threshold voltage ranges
starting from 1.8 volts. For further information contact the
factory.

6·10

ICM7207/A
CMOS Oscillator
Controller
FEATURES

DESCRIPTION

• Stable HF oscillator
• Low power dissipation :0; 5mW with 5 volt supply
• Counter chain has outputs at "'" 212 and .;. 2" or
"'" (2" x 10); n = 17 for 7207, and 20 for 7207A
• Low impedance output drivers ~100 ohms
• Count windows of 20/200ms (7207 with 6.5536MHz
crystal) or 0.1/1 sec. (7207A with 5.24288MHz
crystal)

The ICM7207/A consist of a highstability oscillator and frequency divider providing 4 control outputs suitable for
frequency counter timebases. Specifically. when used as a
frequency counter timebase in conjunction with the
ICM7208 frequency counter. the four outputs provide the
gating signals for the count window. store function. reset
function and multiplex frequency reference. Additionally.
the duration of the count window may be changed by a factor
of 10 to provide a 2 decade range .counting system.
The normal operating voltage of the ICM7207/A is 5 volts at
which the typical dissipation is less than 2mW using an oscillator frequency of 6.5536MHz (5.24288MHz).

APPLICATIONS
•
•
•
•

In the 7207/A the GATING output; RESET. and the
MULTIPLEX .output provide both pull up and pull down.
eliminating the need for 3 external resistors; although.
~g must be provided if interfacing with T2L is required.
RESET occurs 3911-'s after STORE. eliminating an.y potential
problems of overlap between STORE and RESETwhliln using
the ICM7208;

System timebases
Oscilloscope calibration generators
Marker generator strobes
Frequency counter controllers

BLOCK DIAGRAM
...
@-

r

•

OSCIN'

I

RF

l

.;.2 12

I
I

I

/

5
OSCOUT

';J

--- •

J

....

j "

~

l

-:f"

l'

".:~,

CON~

~

-1:»

'<.

OUTPUT

-j)o- -(~

t
-

t----.

(

~l

GATING OUTPUT

'Y ~

""~Yl

~l

'<.,J:

STORE

RESET 14

4

PIN' CONFIGURATION

ORDERING INFORMATION
~~ A

~

+10

,

MULTIPLEX

-=

I

t2S
(+zSl

I

~,~""
•

(OUTLINEORAWING PO)

N/CC~PRST

PO

.

STOC

2

N/CC

3

GROUNDC

4

OSCOUTC

5

PD·14 PIN PLASTIC DIP

13 PGATINGOUT
12 PMUXOUT
ICM7207

TEMPERATURE RANGE
_20°C to +85°C
ELECTRICAL OPTION

(AlII P

RANGE CONTROL

10 p V '

~sCINC

6

9 PN/C

N/CC

7

8 PN/C

TYPE
ORDER DEVICES BY FOLLOWING PART NUMBER
ORDER DICE BY FOLLOWING PART NUMBER

ICM7207 I PO, ICM7207AIPD
ICM7207/D. ICM7207A/D

6·11

ICM7207/A

D~OlL

ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings refer to values
which if exceeded may permanently
change or destroy tlie device. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device,. These are stress ratings
only, and functional operation of the device
. at these or any other conditions above
those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Supply Voltage ' .....................................•.................. 6.0V
Input Voltages ..•..................•..... Equal to or less than supply voltage
Output Voltages ........ Not more positive than +6V with respect to,GROUND
Output Currents ....................................................... 2SmA
Power Dissipation @ 2SoC Note 1 .........................•......... 200mW
Operating Temperature Range .•••.• ; .•.••.......•.••••.•••••. -20°C to +8SoC
Storage Temperature Range .....•........................•. -SsoC to+12SoC
NOTE 1: Derate by 2mW/oC above 25°C,

TYPICAL OPERATlNG CHARACTERISTICS

TEST CONDITIONS: fosc = 6.5536MHz(7207). 5.24288MHz(7207A). V+ '" SV. TA '" 2SoC, test circuit unless otherwise
specified.

SYMBOL,

PARAMETER
Operating Voltage Range
Supply Current
Output on Resistances

V+
1+

Output Leakage Currents
(Output Resistance
Terminals 12.13.14)

IOlK
(ROUT)

Input Pulldown Current
Input Noise Immunity
Oscillator Frequency Range
Oscillator Stability
Oscillator Feedback
Resistance

Ip'd

rds(On}

CONDITIONS

MIN.

-20°C to +8S°C.
All outputs open circuit
Output current - SmA
All outputs
All outputs (STORE only)
Output current - 50pA. 7207 A
only
Terminal 11 connected to V+

4

MAX.

260
50

5.5
1000
120

V
pA
n

50
33K

pA

50

200

0.2

10
1.0

p.A
% supply voltage
MHz
'ppmN

25
2

Note 2
CIN = COUT - 22pF
Quartz crystal open circuit
Note 3

fosc
fSTAB
r'osc

TYP.

UNIT

n

3

Mn

.

, .'
JilOTE 2: Dynamic dividers are used m the mltlal
stages of the divider cham. These dividers have a lower frequency of operation
,

6

,

,

determined by transistor sizes, threshold voltages ahd leakage currents.
NOTE 3: The feedback resistor has a non-linear value determined by the oscillator instantaneous input and output voltage
voltages and the supply voltage.

SUPPLY CURRENT AS A FUNCTION
OF OSCILLATOR FREQUENCY
300

~-.

200

OUTPUT SATURATION RESISTANCr;:S
AS A FUNCTION OF SUPPLY VOLTAGE
w

TA'25 0 C
Medium Quality Quartz Crystals

"

2

~

..-1/'

l..-~"/'
12MHz

... "\..

~

i=~

;20

"~

r3.3

B

50

"10
OSCILLATOR FREQUENCY MHz

I

I

---

!

!

~ : - - . !OUTPUT 2 _ _
0 .............
~TPUTI.GATING OUT
a
MUX OUiPUT

~...

g~NU! ;2!~F--+-+---t--J

,1 25oc I

RL" KI1

a

"

2
Ou>

...

TA

a

10

~

...
COUT;; 10pF
\
CIN"" 10pF
~ 150
,,\
6.5 MHz
a::
" C O U T = 10pF
100 -J
MHz elN "" 10pF
~
COUT = 22pF
8:
2 MHz elN;; 22pF

.!.

Z

120

u

v+ =5V
250

.

I

a

"o

I

a

12

3

I

4
5
SUPPLY VOLTAGE

SUPPLY CURRENT AS A FUNCTION
'
OF.SUPPLY VOLTAGE

OSCILLATOR STABILITY AS A FUNCTION
.
OF SUPPLY VOLTAGE

600
TA= 2SOC I
500 fOSC = 6.5 MHz

I

COUT= 22pF
CIN" 22pF I

"...

I

i

::t 400

i

~
a: 300

""u

i

~ 200

~

(f,I

100

a

6-12

/
V
3

,/

i,

/i
I

!

i

I
4
5
SUPPLY VOLTAGE

V

O~OIb

ICM7207/A
OUTPUT TIMING WAVEFORMS 7207/A

Crystal Frequency = 6.553S/5.24288MHz

_1_ or 625J.iS (1128k

~I
MULTIPLEX OUTPUT

.

OR 7811ls)

H,

~----nn----JLfL
14

·1
(100 OR.ll0000(Oms).
i-----~____~

20 or 200 ms

. r------""""I

GATING OUTPUT

STORE

~

.

Lr----·

;---Lj

t--+ 312J.1s (391/Js)
RESET

•U----·}--/----fi----r----ut--+

312J.ls (391ps)

provides a 50~/o duty cycle signal whose period depends upon
whether the RANGE CONTROL terminal is connected to V+ or
GROUND (open circuit) ..

Referring to the test circuit, the crystal oscillator frequency is
divided by 212 to provide both the multiplex frequency and
generate the output pulse widths. The GATING OUTPUT

'For ICM7207 A this pulse is delayed 391).1s.

TEST CIRCUIT
CRYSTAL PARAMETERS
CIN '" COUT

)CM7207

=22pf
.

f '" 6.5536MHz
R, = 40n

c,

=15mpF

Co = 3.5 pF

ICM7207A
f = 5.24288MHz
Rs < 7sn
Co = 4pF
eM'" 12mpF
CL

= 12pF

10k

Of---.------I
+

S\'VITCHES 5,. 52, 53, 54 OPEN CIRCUIT FOR SUPPLY CURRENT MEASUREMENT.
SWITCH S5 OPEN CIRCUIT FOR SLOW GATING PERIOD.

t SWITCHES 52. Sa. 54 and SOk RESISTORS ARE NOT NEEDED WHEN USING, THE ICM7,207A.

6·13 '

D~OIL

ICM7207/A
APPLICATION NOTES
OSCILLATOR CONSIDERATIONS
The oscillator consists of a CMOS inverter with a non-linear
resistor connected between the input and output terminals
to provide biasing. Oscillator stabilities of approximately 0.1
ppm per 0.1 volt change are achievable at a supply voltage of
5 volts, using low cost crystals. The crystal specifications are
shown in the TEST CIRCU'IT.
It is recommended that the crystal load capacitance (CLl be
no 'greater than 15pF for a crystal having a series resistance
equal to or less than 750, otherwise the output amplitude of
the oscillator may be too low to drive the divider reliably. '
If a very high quality oscillator is desired, it is recommended
that a quartz c[ystal be used having a tight tuning tolerance
±10 ppm, a low series resistance (less than 25m, a low
motional capacitance of 5mpF and a load capacitance of
20pF. The fixed capaCitor CIN should be 39pF and ,the
oscillator tuning capacitor should range between approximately 8 and 60pF.
Use of a high quality crystal will result in typical oscillator
stabilities of 0.05 ppm per 0.1 volt ch,ange of supply voltage.

FREQUENCY LIMITATIONS
,The ICM7207/A uses -dynamic frequency counters in the
initial divider sections. Dynamic frequency counters are faster and consume less power than static dividers but suffer
from the disadvantage that there is a minimum operating
frequency at a given supply voltage. ,

FL----"--

0;063"
(1.6mml

I~~'
0.059"

~--:----·1.5mml----~1

Chip may be die attached. using conventional
bon~ing

SUPPLY' 4
VOLTAGE 3
WINDOW 2

10KHz

100KHz
1MHz
FREQUENCY

10MHz

For example, if instead of 6.5MHz, a 1MHz oscillator is
required, it is recommended that the supply voltage be
reduced to between 2 and 2.5 volts. This may be realized by
using a series resistor in series with the 5V positive supply
line plus a decoupling capacitor. The quartz crystal
parameters, etc., will, determine the value of this resistor.
NOTE: Except for the output open drain n-channel transistors no other terminal is permitted to exceed the supply
voltage limits.

A complete frequency counter using the ICM7207/A together
with the ICM720B Frequency Counter is described in the
ICM720B data sheet.
'

GATING MUX RANGE'V+

eutectic or epoxy procedures. Wire

5

PRACTICAL FREQUENCY COUNTER

CHIP TOPOGRAPHY

_1

6

may be

either aluminum ultrasonic or gold compression.

6·14

,ICM7208
CMOS 7

U~UlL

Decade Counter
FEATURES
•
•
•
•

DESCRIPTION

Low operating power dissipation < 10mW
Low quiescent power dissipation < SmW
Counts and displays 7 decades
Wide operating supply voltage range
,

2V

-s.

V+

-s. 6V

,

• Drives directly 7 decade multiplexed common
cathode LED display
• Internal store capability
• Internal inhibit to counter input
• Test speedup point
• All terminals protected against static discharge

The ICM7208 is a fully integrated seven decade counterdecoder-driver' and is manufactured using Intersil's low
voltage metal gate C-MOS process.
Specifically the ICM7208 provides the following on chip
functions: a 7 decade qounter, multiplexer, 7 segment
decoder, digit & segment driver, plus additional logic for
display blanking, reset, input inhibit, and display on/off.
For unit counter applications the only additional
components are a 7 digit common cathode display, 3
, resistors and a capacitorto generate the multiplex frequency
reference, and the control switches,
The ICM7208 is intended to operate over a supply voltage of
2 to 6 volts as a me'dium speed counter, or over a more
restricted voltage range for high frequency FlPplications,
As a frequency counter it is recommended that the ICM7208
be used in conjunction with the ICM7207 Oscillator
Controller,which provides a stable HF oscillator, and output
signal gating,

ORDERING INFORMATION
ORDER
PART NUMBER

TEMPERATURE
RANGE

PIN CONFIGURATION

(OUTLINE DRAWING PI)

28 LEAD
PACKAGE

ICM7208IPI
PLASTIC
-20°C to +85°C
ORDER DICE BY FOLLOWING PART NUMBER:
.ICM7208D

SEG a
TEST 2

,

SEG f
GROUND

4

TEST 3

7

SEG, b

DISPLAY ENABLE

9

MUX 3

STORE

CHIP TOPOGRAPHY
TEST 1

0,

SEG.g

MUX, #2
MUX. #1

SEG.c
RST

SEG b

COUNT ENABLE

MUX, #3

,RESET
COUNT ENABLE'
COUNT IN

Chip may be die attached using conventional
eutectic or epoxy procedures. Wire bonding rylay be
either aluminum ultrasonic or gold compression.

6·15

SEG 9

COUNTER INPUT

ICM7208
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) ................................................ 1 W
Supply voltage (Note 2) ..................................................... 6V
Output digit drive current (Note 3) ...................................... 150mA
Output segment drive'current ........................................... 30 mA
Input voltage range (any input terminal) (Note 2) ... Not to exceed the supply voltage
Operating temperature range ................................... -20°C to +85°C
Storage temperature range .................................... -55°C to +125°C
. Lead temperature (soldering, 10 seconds) ................................ 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure-to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL OPERATION CHARACTERISTICS
TEST CONDITIONS:(V+ = 5V, TA = 25°C, TEST CIRCUIT, display off, unless otherwise specified)
PARAMETER

SYMBOL

CONDITIONS

Quiescent Current

10

All controls plus terminal 19 connected to

Quiescent Current

10

All control inputs plus terminal 19 connected

MIN

TYP

MAX

30

100

70

150

UNITS

V+ . No multiplex oscillator
to V+ except STORE which is connected
/lA

to GROUND
Operating Supply

.1+

All inputs connected to V+ , RC multiplexer

1+

fin = 2MHz

Supply Voltage' Range

V+

fin :S 2MHz

Digit Driver On Resistance

rDIG

Digit Driver Leakage

IDIG

Operating Supply

210

500

osc operating fin < 25KHz

Current

700

Current

Current
Segment Driver

3.5
4

5.5

V

12

(}

500

/lA

I

40

rSEG

(}

On Resistance
Segment Driver

500

ISLK

/lA

Leakage Current
Pullup Resistance of RESET
or STORE Inputs

Rp

COUNTER INPUT Resistance

RIN

COUNTER INPUT Hysteresis
Voltage

VHIN

100

400
k(}
100

Terminal 12 either at V+ or GROUND
25

50

mV

NOTE 1: This value of power dissipation refers to that of the package and will not be obtained under norinal operating conditions.
NOTE 2: The supply voltage must be applied before or althe same time as any input voltage. This poses no problems with a single power supply
. system. If a multiple power supply system is used, it is mandatory that the supply for the ICM7208 is switched on before the other
supplies otherwise the device may be permanently damaged.
.
,
NOTE 3: The output digit drive current must be limited to 150mA or less under steady state conditions'.IShort term transients up to 250mAwili
not damage the device,.) Therefore, depending upon the LED display and the supply voltage to be used it may be necessary to include
additional segment series resistors to limit the digit currents,

6·16

ICM7208
TYPICAL PERFORMANCE CHARACTERISTICS
SEGMENT OUTPUT CURRENT AS A FUNCTION,
OF SUPPLY VOLTAGE

MAXIMUM COUNTER INPUT FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE

30.0
N

==
~
>
CJ

zw

~

6.0

5.0

/

I::I

...

~

4.0

/

W

II:
II:

~

3.0

CJ

...

2.0

o

1.0

2.0

15.0

/

I::I

0

I-

10.0

.iii
Cl
==

w

V

'=="

20.0

I::I

5.0

til

3.0

4.0

5.0

6.0

..,.V
1.0

0

'"

::I

::I

1
(

200

100

,/

/
",

V

Tllli5 0

'"

"IZ
W

II:
,II:

400

300

::I

CJ

/

.......>
...

iil •

a
c

-d

r--e

,-'
,--g

200

100

I II

MUX INPUT

.~

Tiil

~_.0_0l_C_O_UN_~_·~_~_'_NP_U_T_O~_~_E_Q_UE_N_~_~_'_'N_M_H_Z_1_0
....

1::1

B BBBB
2

4

3

I

6

I

I

5.0Y

/' FUNCTION
GENERATOR,

DISPLAY

.=I:..

y+o

~

~100k ~
-

9
10

STORE
COUNT ENABLE
INHIBIT
RESET
lOOk

6·17

7 -COMMON CATHODE

280
27

261-25
24
5
6 .lCM7208 23
22
21

y+

y+

,

SDk

20
19

11
12
13

18
17r-16

14

15t---

___

B

1:3

5

1.
2
3
4

'-:!:-

J
H~ H!

I II

1.Jk~l,1 EX~EJJ~~

ed c
1

~

1.6kHz RC MUX OSC

Q
u_

b

d

.

_ _ _ _ _,_o_ _ _1_,.o_ _S_2 P_P_LY_3.·_:0;;..L_T_A4_GO_E_5_.0
__
6._0_ _ _ _ _ _ _ _ _ _ _

TEST CIRCUIT

6.0

500

/

150

50

My

5.0

600

TAJ50 C
"N = 25kHz
RC oscillator 1.5kHz

til

t

4.0

300

>
....

......

3.0

SUPPLY CURRENT AS A FUNCTION
OF COUNTER INPUT FREQUENCY

W

CJ

I

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

250

II:
II:

/

SUPPLY YOLTAGE

I

"IZ

I

I

2.0

SUPPLY YOLTAGE

/~

I

LED FORWARD YOLTAGE
DROP@ 15 mAo 1.8Y
5 SEGMENTS LIT

::I

/

::I
==

;c
==

25.0

E
I-

aw

IL

'z"

7.0

::I
II:

TA=l~oc I

TA =125oC

:J:

50k
II

.01~F

M UX
R. C.
0 SCILLATOR
(APPROX. 1.5kHz)

DJ

ICM7208
TEST PROCEDURES

CONTROL INPUT DEFINITIONS

The ICM7208 is provided with three input terminals 7, 23, 27
which may be used to accelerate testing: The least two sig~
nificant decade counters may be tested by applying an input
to the 'COUNTER INPUT' terminal 12. 'TEST POINT'
terminal 23 provides an input which bypasses the 2 least
significant decade counters and permits an injection of a
signal into the third decade counter. Similarly terminals 7
and 27 permit rapid counter advancing at two points further
along the string of decade ·counters.

INPUT
TERMINAL VOLTAGE
V+
9
1. DISPLAY
Ground
11
V
2. STORE

Ground

3. ENABLE

13

V+

4., RESET

14

Ground
V
Ground

FUNCTION
Display On
Display Off
Counter
Information
Latched
Counter
Information
Transferring
Input to Counter
Blocked
.Normal Operation
Normal Operation
Counters Reset

COUNTER INPUT DEFINITION
The internal counters of the ICM7208 index on the negative
edge of the'input signal at terminal #12.

BLOCK DIAGRAM
16I-"VV\r------.

TEST POINT 1

TEST INPUT 2

TEST INPUT 3

OSC3

R

R

CL
+10

+10

STORE

SEG.I

[I]

9~~~~-------~
DISPLAY
ON/OFF

DIG. 1 . DIG.2

DIG.3

6·18

DIG.4

v+

m

GROUND

DIG.S

DIG.6

DIG.7

ICM7208
APPLICATION NOTES

It is recommended that the display multiplex rate be within
the range of 50Hz to 200Hz, which corresponds to 400Hz to
1600Hz for the multiplex frequency input.

1. Format of Signal to be Counted
The noise immunity of the COUNTER INPUT Terminal is ap~
proximately 1/3 the supply voltage. Consequently, the input
signal should be. at least 50% of the supply in peak to peak
amplitude .and preferably equal to the supply. NOTE: The
amplitude of the input signal should not exceed the supply;
otherwise, damage may be done to the circuit.
The optimum 'input signal is a 50% duty cycle square wave.
equal in amplitude to the supply. However, as long as the rate
of change of voltage is not less than approximately
10-4V/1'sec at 50% of the power supply voltage, the input
waveshape can be sinusoidal, triangular, etc.
When driving the input of the ICM720B from TTL, a 1k-5k
ohm pull-up resistor to the positive supply must be used to
increase peak to peak input signal amplitude.

4. Unit Counter
The unit counter updates the display for each negative
transition of the input signal. The information on the display
will count, after reset, from 00 to 9,999,999 and then reset to
0000000 and begin to count up again. To blank leading zeros,
actuate reset at the beginning of a counf. Leading zero
blanking affects two digits at a time,
For battery operated systems the display may be switched
off to conserve power.
An external generator may be used to provide the multiplex.
frequency input. This signal, applied to terminal 19
(terminals 16 and 20 open circuit)" should be approximately
equal to the supply voltage, and should be a square wave for
minimum of power dissipation.

2. Display Considerations
Any common cathode multiplexable LED display may be
used. However, ifthe peak digit currerit exceed 150 mA for
any prolonged time, it is recommended that resistors be
included in series with the segment outputs to limit digit
current to 150mA.
.
The ICM720B is specified with 500l'A of possible digit
leakage current. With certain new LED displays that are
extremely efficient at low currents, it may be necessary to
include resistors between the cathode outputs and the
positive supply to bleed off this leakage current.

For stand alone systems, two inverters are provided so tMta
simple but stable RC oscillator may be built using only 2
resistors and a capacitor.

3. Display Multiplex Rate,

The input switch is shown to be a single pole double throw
s'witch (SPOT). A single pole single throw'switch (SPST)
could also be used (with a pullup resistor), however, antibounce. circuitry must be included in series with the counter
input. In order to avoid contact bounce problems due to the
SPOT switch the ICM720B contains an input latch on chip.

Figure 1 shows the schematic of an e'xtremely simple unit
counter that can be used for remote traffic counting, to name
one application. The power cell stack should consist of 3 or 4
nickel cadmium rechargeable cells (nominal 3.6 or 4.B volts),
If 4 x 1.5 volt cells are used it is recommended that a diode be
placed in series with the stack t6 guarantee that the supply
voltage does not exceed 6 volts.

The ICM720B has approximately 0.51's overlap between
output drive signals.'Therefore, if the multiplex rate is very
fast, digit ghosting will occur. The ghosting determines the
upper limit for the multiplex frequency. At very low multiplex
rates flicker becomes vis.ible.
a
b

c
,----d

r--e
,-f
r--c-9

1::/ 1-/ l-/ l-' l-I'
1::-:/ 0
1=' 1=/ I~
7

6

S

4

I

Bb

3

2

I

L

1 -COMMON CATHODE

2J
2
27
263
4
25
5
24
6 ICM7208 23
V+o- 7
22
21
- 8
100k
20
9
10
19
11
18
t - 100k
12
16
13
0.01~F
14
15r-1 •

+S.OV

T

DISPLAY

V+~~
100k

-

_I

INPUT
PROCESSING

rHr-

I
I

!t-::-

N.O.

°oRV+

-

-

-:::c-

RESET

Figure 1: Schematic Unit Counter
6-19

v+

v+

m
•

,

ICM7208

s.

Frequency Counter
this information is stored, the counters are cleared and are
ready to start a new count when the counter input is e.nabled.
Using a 6.5536mHz quartz crystal and the ICM7207 driving
the ICM7208, two ranges of counting may be obtained, using
either 0.01 sec or 0.1 sec counter enable windows.

The ICM7208 may be used as a frequency counter when
used with an external frequency reference and gating logic.
This can be achieved using the ICM7207 Oscillator Controller (Figure 2), The ICM7207 uses a. crystal controlled
oscillator to provide the store and reset pulses together with·
the counting window. Figure 3 shows the recommended
input gating waveforms to the ICM7208. At the end. of a
counting period (50% duty cycle). the counter input is
inhibited. The counter information is then transferred and
storeq in latches, and can be displayed. Immediately after

b

•
c

,...-----d

-

ab

--:-9

1

2

3

-:1:-.

r---

v+o

lk

_D!SPLAY

f.l

~

lOOk

ICM
7207

~

8-40p

0
~

F

MH~

7

8

22P-;--

10Mn

T

~

.,:,

r---

50k

h

j

v~ ±

GATING W~NDOW
SELECT

50k

i

i

::::: 5.0V

l:i14

L

l-

ed C

..-----1

The ICM7207 provides the multiplex frequency reference of
1.6kHz.

aa Baaa

19

r---e

Previous comments on leading zero blanking, etc., apply as
per the unit counter.

-

!,
~RESET

I'

1 •
2
3
4
5
6 ICM7208
0-7
v+- 8
9
10
11
12
13
14

+0.47~F

i

2J
27
2625
24
23

7 -COMMON CATHODE

v+

v+

22
21
20 1918-

1716 15 r---

v+

~

INPUT
,~
PROCESSING

INPUT

CRYSTA L PARAMETERS
CL = 12pF
CM = 15mpF
Rs =55n
Co= 3pF

Figure 2: Frequency Counter

Note: For a 1 sec count window which allows all 7 digits to be used with a resolution of 1Hz, the ICM7207 can be replaced with the ICM7207 A.
Circuit details are given on the 7207A data sheet.
.

6-20

D~DIl.

ICM7208

I

1:1
COUNT ENABLE INPUT

STOiiE INPUT

'iiEsET INPUT

COUNTER INPUT

I~V+-5.0V

I--COUNTER INPUT-I - - - - - - - - O V
ENABLED (COUNTING WINDOW)

lJ

:J L~S::E~G:::M:::EN:::T:-:D:-:A:-::T:-:A­
-U-

PULSE WIDTH NOT
CR'ITICAL > 50~S.c.

LATCHED

COUNTER RESET

EXTERNAL FREQUENCY TO BE MEASURED

Figure 3: Frequency Counter Input Waveforms

6. Period Counter
For this application, as opposed to the frequency counter,
the gating and the input signal to be measured are reversed
to the frequency counter. The input period is multiplied by
two to produce a single polarity signal (50% duty cycle) equal
to the input period, which is used to gate into the counter the
freql,lency reference (1MHz in this easel. Figure 5 shows a

COUNT ENABLE INPUT

block schematic of the input waveform generator. The 1MHz
frequency reference' is generated by the ICM7209 Clock
Generator using an SMHz oscillator frequency and internally
dividing this frequency by S. Alternatively, a 1MHz signal
could be applied directly to COUNTER INI"UT. Waveforms
.
are shown in Figure 4.

~~TERNAL FI'IEQUENCYI

STORE GENERATED. BY THE POSITIVE
EDGE OF THE ENABLE INPUT

STciiiE INPUT

"iiEsET INPUT

=U=RESET

INPUT IS = 1MHz

COUNTER INPUT

Figure 4: Period Counter Input Waveforms

INPUT

---------f

1---....------ EtiAaLi INPUT
t----- iiEsET INPUT'
' - - - - - - - - - - - - STORE INPUT
1 MHz

1----'------ COUNTER INPUT

Figure 5: Period Counter Input

6-21

Generato~

ICM7209
CMOS CI,ock Generator

FEATURES

GENERAL DESCRIPTION

• High frequency operation - 10MHz guaranteed
• Easy to use oscillator - requires only a quartz
crystal and two capacitors
• Bipolar,MOS and CMOS compatibility
• High output drive capability - 5 x TTL fanout with
10ns rise and fall times
• Low power - 50mW at 10MHz
• Choice of two output frequencies - osc., and osc.
+8 frequencies
• Disable control for both outputs
• Wide industrial temperatu're range - ,-20° C to
+85°C
• All inputs fully protected - circuits may be handled
without any special precautions

The Inl!~rsil ICM7209 is a versatile CMOS clock generator
capable of driving a number of 5 volt systems with a variety of
input requirernents. When used to drive up to 5 TTL gates, the
typical rise and fall times are 10ns.
The ICM7209 consists of an oscillator, a buffered output
equal to,the oscillator frequency and a second buffered
output having an output frequency onE;l-eighth that of the
oscillator. .The guaranteed maximum oscillator frequency is
10MHz, Connecting the DISABLE terminal to the negative
supply forces the +8 output into the '0' state and the output 1
into the '1' state,

SCHEMATIC D'IAGRAM'

CHIP TOPOGRAPHY
+8

2

Dl

Of

DYNAMIC
DIVIDE BY 8

OSCIN

8,:,
1, '

6

OSC OUT

OUT-+8'

3
53MILS
(1.35 mnil

DIsABLE
'ZENER VOLTAGE IS TYPICALLY 6.3 VOLTS

PADS 4.2 x 4.2 MILS2

(.107 mm x .107 mml

ORDERING INFORMATION

ICM7209

L=
I

,

Chip may be die attached using conventional
enteric or epoxy procedures. Wire bonding may be
either Aluminum ultrasonic or Gold compression.

PIN ,CONFIGURATION

(OUTLINE DRAWING PAl

PA

.

Package

"

(See Outime Dr,~wlOg)

Temperature Range·
(Industrial:
, -20 to +85' CI

' - - - - - - - - - - TYPE

TOP VIEW
Order DeVices by FollowlIlg Part Number
Or~er

leMl209 I PA.'

Dice by Following Part Number - ICM1209 0

Pin 1, is desi,9naled by eilher a dot or a notch,

6·22

ICM7209

O~OIb

ABSOLUTE MAXIMUM RATINGS
Power Dissipation (25° C) ............................................... 300mW
Supply Voltage .................... '......................................... 6 V
Output Voltages .................................. Equal to or less than supply
Input Vo.ltages ............. '....................... Equal to or less than supply
Storage Temp ................................................. -55°C to +125°C
Operating Temp. Range ......................................... -20°C to +85°C
Lead Temp. (Soldering, 10 seconds) .............. : ...................... 300°C
NOTE: Stresses above those listed under Absolute Maximum Ratings may c'ause permanent damage
,tothedevice. These are stress ratings only, and function'al operation of the device atthese or any
other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

TYPICAL OPERATING CHARACTERISTICS
TEST CONDITIONS: V+

= 5V ±10%, test circuit, fose = 10MHz, TA = 25°C unless otherwise specified.

PARAMETER
Supply Current

SYMBOL
1+

Disable Input Capacitance
Disable Input Leakage
Output Low State

CD
IiLK
VOL

Output High State,

VOH

Output Rise Time (Note 3)

tr

Output Fall Time (Note 3)

tf

Minimum OSC Frequency
for 78 Output
Output 78 duty cycle

fose

CONDITIONS
Note 1
No Load
Either '1' or
Either OUT
simulated 5
Either OUT
simulated 5
Either OUT
simulated 5
Either OUT
simulated 5
Note 2

'0' state
1 or OUT 78
x TTL loads
1 or OUT 78
x TTL loads
1 or OUT 78
x TTL loads
1 or OUT 78
x TTL loads

MIN

TYP.
11

MAX
20

UNITS
mA

5
±10

/LA

pF

0.4
4.0

4.9
10

25

10

25

2

Any operating frequency
7:9
Low state: High state
NOTE 1: The power dissipation IS a function of the oscillator frequency (1st ORDER EFFECT see curvel but IS also effected to a small extent by
the oscillator tank components,
NOTE 2: The +8 circuitry uses a dynamic scheme. As with any dynamic system, information or data is stored on very small nodal capacitances
instead of latches (static systemsl and there is a lower cutoff frequency of operation. Dynamic dividers are used in the ICM7209 to
significantly improve high frequency performan'ce and to decrease power consumption.
NOTE 3: Rise and fall times are defined between the output levels of 0.5 and 2.4 volts.

TEST CIRCUIT

CRYSTAL PARAMETERS:
CM= 5mpF
RS = 15 ohms
Co =3pF
f= ~ MHz

+5V

O.01!LF

~r---llt---....
r--~_

r--_ _---'"_ _---'"~OISABLE
OSC OUT V+
OUT 1

,400Q

__l

ICM 7209
OSC IN

6-23

v-'

_--<>--_-~I-~ SIMULATED

5x TTL LOADS

OUT 78

·D~DI6

ICM7209
TYPICAL'OPERATING CHARACTERISTICS

SUPPLY CURRENT
AS A FUNCTION OF
OSCILLATOR FREQUENCY
-

15
TA=25°C

cc

SIM~LAT~D 5JTTL

~

LOADS AT
OUTPUT 1

.!i 10
z
w
a:
a:

a
>

5

'-I

8::

iiJ

o

(

4

5

\\

II

TA= 25°C
LOAD =
5xTTL
LOADS
TA= 25°C
fOSC=
10MHz

/
V

....V

1MHz
10MHz
FREQUENCY

w 4
Cl,

~

-I

g

100MHz

V

(I)

\.
20

40

60

80

3

~

~ 2

8::
;)

~ ~..t~~~~~AiLED

100KHz

TYPICAL OUT 1
RISE AND FALL TIMES
5

/

SUPPLY VOLTAGE RANGE
FOR CORRECT OPERATION OF
+8 COUNTER AS A FUNCTION OF
OSCILLATOR FREQUENCY

100

TIME Ins)

1

o

/

if I

/

~LYVOLTAGE

LOCI FOR CORRECT
OPERATION

10KHz 100MHz 1 MHz 10MHZ ,100MH,z
OSCILLATOR FREQUENCY

Rise and fall times of OUT +8
are similar to th'ose of OUT 1.

[i]
--------------------~----------~------~---------------------------------

APPLICATION NOTES
OSCILLATOR CONSIDERATIONS
The oscillator consists of a C-MOS inverter with a non-linear
resistor connected between the oscillator input and output
to provide D.C. biasing. Using commercially obtainable
quartz crystals the oscillator will operate from low frequencies 110KHz) to 10MHz.
The oscillator' circuit consumes about ,SOOI'A of current
using a 10MHzcrystai with a Svoltsupply.and is designed to
operate with a high impedance tank circuit. It is therefore
necessary that the quartz crystal be specified with a load
capacitance ICLI of 10pF instead 'of the standard 30pF. To
maximize the stability ofthe oscillator as a function of supply
voltage and temperature. the motional capacitance of the
crystal should be low ISmpF or lessl. Using a fixed input,
capacitor of 18pF and a variable capacitor ,of nominal vaiue
of 18pF on the output will result in oscillator stabilities of
typically 1ppm per volt change in supply voltage. '

dividers). The dynamic divider has advantages in high speed
operation and low power but suffers from limited low
frequency operation. This results in a window of operation
for any oscillator frequency (see graph under TYPICAL
OPERATING CHARACtERISTICS).

OUTPUT DRIVERS
The output drivers consist of C-MOS inverters having active
pullups and pulldowns. Thus the outputs can be used to
directly drive TTL gates. other C-MOS gates operating with a
S vOlt supply. pr TTL compatible MOS gates.
The guaranteed fanout is S TTL loads although typical
fanout capability is at least 10 ,TTL loads with slightly
increased output rise and fall times.

COMMENTS ON THE DEVICE
POWER CONSUMPTION
At low frequencies the principal' component of the Rower
consumption is the oscillator. At high oscillator frequencies
the major portion of the power is consumed by the output
drivers. thus by disabling the outputs (activating the
DISABLE INPUT) the device power consumption can be
dramatically reduced.

THE +8 OUTPUT
A dynamic divider is used to divide the oscillator frequency
by 8. Dynamic dividers use small nodal capacitances to store
voltage levels instead of latches (which' are used in static

6·24

O~OlL

ICM7211 (LCD)
ICM7212 ',(LED)
Four Digit CMOS
Display DecoderI Drivers

ICM7211 (LCD) FEATURES

DESCRIPTION

• Four digit non-multiplexed 7 segment LCD display
oututs with backplane driver
• Complete onboard RC oscillator to generate backplane frequency.
• Backplane input/output allows simple synchronization of slave-device segment outputs to a master
backplane signal.' '
• ICM7211 devices provide separate digit select
Inputs to accept multiplexed BCD Input (Pinout and,
functionally compatible with Sillconlx DF411).
• ICM7211M devices provide data and digit select
code Input latch~s controlled by chip select inputs
to provide a direct high ,speed processor Interface.
• ICM7211 decodes binary to hexadecimal;
ICM7211A decodes binary to Code B (0-9, dash,
E, H, L, P, blank)

The ICM7211 (LCD)'and ICM7212 (LED) devices constitute a
family of non-multiplexed four-digit seven-segment CMOS
display decoder-drivers;
The ICM7211 devices are configured to drive conventional
LCD displays by providing a complete RC oscillator, dil.dder
chain, backplane, driver, and 28 segment outputs. These
outputs provide the zero d.c. component signals necessary
for long display life.
The ICM7212 devices are configured to drive com'monanode LED displays, providing 28 current-controlled low
leakage open-drain n~channel outputs. These devices
provide a BRIGHTNESS input, II!/hich may be used at normal
logic levels as a display, enable, or with a potentiometer as a
continuous display brightness control.
Both the LCD and LED devices are available with two input
configurations. The basic devices provide four data-bit
inputs and four digit select inputs. This configuration is
suitable for interfacing with multiplexed BCI;), or binary
output devices, such as the ICM7217, ICM7226 and ICL7103.
The microprocessor interface (suffix M) devices provide data'
input latches and digit select code latches under control of
high-speed chip select inputs. These devices simplify the
task of implementing a cost-effective alphanumeric 7-segment display for microprocessor systems, without requiring
extensive ROM or CPU time for decoding and display
updating. .
The standard devices will provide two different decoder configu~ations. The basic device will decode the four bit binary
input into a seven-segment alphanumeric hexa-decimal
output. The "A" versions will provide the same output code
as the ICM7218 "Code B", i.e., 0-9, dash, E, H, L, P, blank.
Either device will correctly decode true BCD to seven
segment decimal outputs.'
Devices in the ICM7211/7212 family are packaged in a
standard 40 pin plastic dual-in~line package and all inputs
are fully protected against static discharge. '

ICM7212 (LED) FEATURES
• 28 current-limited segment outputs provide 4-dlglt
non-multiplexed direct LED drive at > SmA per
segment.
• Brightness Input allows direct control of LED
segment current with a single potentiometer. Canfunction digitally as a display enable.
• ICM7212M and ICM7212A devices provide s~me
input configuration and output decoding options as
the ICM7211.
'

PIN CONFIGJ.lRATIONS

(OUTLINE DRAWING PL)

(OUTLINE DRAWING PL) ,

6·25

m

ICM7211/ICM7212
ABSOLUTE MAXIMUM RATIN'GS '
Power Dissipation (Note 1) .••.••••••••••••••••••.•..••. ; ••••••.. 0.5 W@70°C
Supply Voltage ..••.•.••.••••••••....• '. . • • • . . • • . • • . • • • • • • • • • . • • • • • • • . • . . •. 6.5V
Input'Voltage (Any
,
Terminal) (Note 2)' •..••••.••••..•.••..••.••.••:. . • • . • •• V+ +O.3V, GROUND -o.3V
Operating'Temperature Range •.• , •..•...••.• , •••••.•.• ; •••• , .. , :"'20°C to+85°C
Storage Temperature Range ................................... -55°C to +125°C
Leai:! Temperature (Soldering 10 sec,) ..•••••••••••.••••••••.••..•••••.•.. 300°C
,Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
, the device. These ,are stress ratings only, and funCtional 'operation of the device at these or any
other conditions above, those indicated in the operational s~tions of the specifications Is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
NOTE 1: Thls,limlt refers to that of the package and will not be realized during normal operation.
filOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any terminal to
voltages greater than V+ or'less than GROUND may Cause destructive device latch up.
, For this reason, it is recommended that no inputs from exter"al sources not operating on
, the same power supply be applied to the device before its supply Is established, and that
in multiple supply systems, the supply to the ICM721111CM7212, tie turned on first.

TABLE I: OPERATING CHARACTERISTICS
TEST CONDITIONS: All parameters measured with V+ = 5V
,ICM7211 CHARACTERISTICS (LCD)
PARAMETER
Operating supply Voltage Range
,Operating Current '
Oscillator Input Current
Segment Rise/Fall Time
Backplane Rise/Fall Time
Oscillator Frequency
Backplane Frequency

SYMBOL
Vsupp
lop
loser
trfs
trfb
fose
, fbp'

CONDITIONS,

MIN
3

Test circuit, Display blank
Pin 36
CL - 200pF
CL = SOOOpF
Pin 36 Floating
Pin 36 Floating

,

TYP
5
10
±2
0.5
1.5
16
125

'MAX'
6'

UNIT
V

50
±10

p.A

TYP

MAX

UNIT

6
50

V
p.A

+1

mA
p.A
mA

MAX

UNIT

p's
kHz
Hz

ICM7212 CHARACTERISTICS (COMMON ANODE LED) ,
MIN

SYMBOL CONDITIONS'

PARAMETER
Operating Supply Voltage Range
Operating Current
Display Off
Operating Current
Segment Leakage Current
Segment On Current

Vsupp
lop
loP'
ISLK
ISEG

4

:

Pin 5 (~rightn!3ss),
Pins 27-34 - GROUND
Pin 5at V , Display all 8's
Segment Off
18egment On, Vo - +3V

'

5
10 \

'

200
+0.01
5

8

INPUT CHARACTERISTICS, '
' SYMBOL CONDITIONS
PARAMETER
Logical "1" input voltage ,
VIH
Logical "0" input voltage
VIL
Pins 27-34
Input leakage current
IILK
.
Input capacitance
Pins ,27"34
CIN
Measured at Pin 5 with ,Pin 36 at GND
BP/Brightness input leakage
IBPLK
BP/Brightness, input capacitance
All Devices
CBPI
AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION
Refer to Timing Diagrams
Digit Select Active Pulse Width
tsa
Data Setup Time
tds
Data Hold Time
tdh
Inter-Digit Select Time
tids
AC CHARACTERISTICS - MICROPROCESSOR INTERFACE
Chip Select Active Pulse Width
tcsa other chip select either held active, or
both driven together
Data Setup Time
tds
Data Hold Time
tdh
Inter-Chip Select Time
tics
"

MIN'

±.01
5
±.01
200

,

-

~

6-26

TYP

3

' 1

V

1
±1
:

±1

p.A
pF
p.A
pF
P.s

500
200
2

ns
P.s

200
100
10
2

ns
0
P.s

ICM7211/ICM7212
TYPICAL CHARACTERISTICS
ICM7211 OPERATING SUPPLY CURRENT
AS A FUNCTION OF SUPPLY VOLTAGE

ICM7211 BACKPLANE FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE

30

180

LCD D~~I.CES, TEST CIRCUIT
25 -DISPLAY BLANK
PIN 36 OP~N

I

.Y

'
j/

120

I V/
15

TA-25°C~

10

/ 1.0

Case - 0

/

/

ITA -1- 2O'C')I

~ 90

~

./

V

,"

. / /case"" 22pF

./

60

(PIN 36 OPEN)_

'/

/

V
,

:l!

/ ~V
, ~ Y' ~TA

./

"

=70°C

,~

,;'

150

20

i.

oLc~s

LJo
r-TA '" 25c C

30

?'

Case

o

4

1

--

220pF

4
v+ Volts

V+ Volts

ICM7212 LED SEGMENT CURRENT
AS A FUNCTION OF OUTPUT VOLTAGE
15

- J-- -

I-PILAL+
TA = 25°C

/

.

::;!' 6V-1

-

/

10

V

E

l
II
o

./

/V
1/1/
'/

/'

.......

V+-5V

l- fy+=

4V

'I

o
Vo Volts

ICM7212 LED SEGMENT CURRENT
AS A FUNCTION OF
BRIGHTNESS CONTRO~ VOLTAGE
12

SEIGME~T OLTPJTAT1+3V I

TA

=

ICM7212 OPERATING POWER (LED DISPLAY)
AS A FUNCTION OF SUPPLY VOLTAGE
1800

/

25 C C

10

1500

/

I

I

,

I

/

TA=25°C

V.

1200

/

/
/

6

1

I

/
/
o

V

/

900

1/

600

, ...

/
o

LE~ OE~ICE~

DISPLAY ALL EIGHTS
LED FORWARD VOLTAGE DROP
VFLED = 1.7V
PIN 5 AT V+

./

"

V

300

,
5

3
VPIN 5 Volts

. V+ Volts

6·27

I

ICM7211/ICM7212
BLOCK DIAGRAMS
ICM7211 (A)
0'

SEGMENT OUTPUTS

03

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

OATAJ~~~§H~~3
1===

INPUTS

oIGITI~~~~====~===:L

SELECT
INPUTS

____~

BACK·

OSCILLATOR
16KHz

+128

FREE-

PLANE

DRIVER

RUNNING

OSCILLATOR

ENABLE

INPUT

ICM7212 (A)
0'

03

02

01

SeGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

BRI!3HTNESS

.6-28

ICM7211/ICM7212
ICM7211(A)M
04

03

D.

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

DATA
INPUTS

2-81T
DIGIT SELECT

CODE INPUT

CHIP SELECT 1
CHIP SELECT 2

OSCILLATOR
16KHz

+128

FREE·

BACKPLANE

DRIVER

RUNNING

OSCILLATOR
INPUT

ICM7212(A)M
04

03

D.

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

BRIGHTNESS

DATA
INPUTS

2-81T
DIGIT SELECT
CODE INPUT

CHIP SELECT 1

CHIP SELECT.

6-29

ICM7211/ICM7212
INPUT DEFINITIONS
In this table. V+ and GROUND are considered to be normal operating input logic levels. Actual input low and high levels are
specified in Table 1. For lowest power consumption. input signals should swing over the full supply ..
INPUT
BO

B1
B2
B3
OSC
(LCD Devices Only)

TERMINAL CONDITION
V+ = Logical One
27
GND = Logical Zero
V+ = Logical One
GND = Logical Zero
28
V+ - Logical One ,
GND = Logical Zero
29
V+ = Logical One
30
GND = Logical Zero
36
Floating or with
external capacitor
GROUND

FUNCTION
Ones (Least Significant)
Twos
Fours
Eights (Most significant)
Oscillator input
Disables BP output devices. allowing segments to be synced to an
external signal input at the BP terminal (Pin 5)

ICM7211/1CM7212
MULTIPLEXED-BINARY INPUT CONFIGURATION
INPUT
TERMINAL CONDITION
D1
31
02 .
V+ = Active
32
GND = Inactive
03
33
04
34
ICM7211 M/ICM7212M
MICROPROCESSOR INTERFACE INPUT
INPUT DESCRIPTION
TERMINAL
31 •
DS1 Digit Select
Code Bit 1 (LSB)
D$2 Digit Select
32
C.ode bit 2 (MSB)
CS1
CS2

Chip Select 1
Chip Select 2

33
34

Data Input Bits

FUNCTION
01 (Least significant) Digit Select
.02 Digit Select
03 Digit Select
04 (Most significant) Digit Select

CONFIGURATION
CONDITION
V+ = Logical One
GND = Logical Zero

V = Inactive
GND'= Active

FUNCTION
DS1 & DS2 serve as a two bit Digit Select Code Input
DS2. DS1 = 00 selects 04
DS2. DS1 = 01 selects 03
DS2. DS1 = 10 selects 02
DS2. DS1 = 11 selects 01
When both CS1 and CS2 are taken low. the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select. the data is decoded
and written into the output latches.

TEST CIRCUIT
+

5V

-

, IIII t-'-------,

-';~M~2~:):~~
5 BP
EACH SEGMENT
TO BACKPLANE
WITH 200pF
CAPACITOR

,QSC 36
GND 35

DIGIT/CHIP
SELECT
INPUT

l~;

32
31

DATAl 28~~

V+(MICROPROCESSOR)
VERSIONS

GND(MULTIPLEXEO\
\VERSIONS
J

INPUTS

27

20

u--~

J

__ __ -,-___ J
~

6-30

v"

ICM7211/ICM7212
DIGIT SELECT

,
OSCILLATOR
FREQUENCY

----.,1

DN_t

BACKPLANE

INPUT/OUTPUT

DIGIT SELECT
DN

O~OIL

.n.r 'UlIlI1f
1JU1.f
II

----~I

1-64 CYCLES

OfFSEGMENTS----~1
ON SECMENTS

Figure 1: Multiplexed Input Timing Diagram

1IlJ1Jlf
-I

128 CYCLES

.

t

'

IL - - -

64 CYCLES-'+j

' L-

S

'----_......IrDisplay Waveforms

large capacitive loads with short (1-2",s) rise and fall time~,
The maximum frequency for a backplane signal should be
about 125Hz, although this may be too fast for optimum
display response at lower display temperatures, depending
on the display used,
'
The onboard oscillator is designed to free run at approximately 16KHz at microampere power levels. The oscillator
frequency is divided by 128 to provide the backplane
frequency, which will be approximately 125Hz with the
oscillator free-running; the oscillatOr frequency may be
reduced by connecting an external capacitortotheOSC·illator
terminal.
'

CS1
(CS2)

CS2
(CS1)
DATA AND
DIGIT SELECT
CODe·

l1li

= DON'T CARE

Figure 2: Microprocessor Interface Input Timing Diagram

The oscillator may also be overdriven if desired, although
care must be taken to ensure that the backplane driver is not
disabled during the negative portion of the overdriving signal
(which could cause a d.c. component to the displayl. This
can be done by driving the OSCillator Input between the
positive supply and a level out· of the range where the
backplane disable is sensed ( about one fifth of the supply
voltage above GROUND). Another technique for overdriving
the oscillator (with a signal swinging the full supply) is to
skew the duty cycle of the overdrivirig signal such that the
negative portion has a duration shorter than about one
microsecond. The backplane disable sensing circuit will not
respond to signals of this duration.

DESCRIPTION OF OPERATION
LCD DEVICES
The LCD devices in the family (lCM7211.,7211A, 7211M,
7211 AM) provide outputs suitable for driving conventional
four~digit by seven-segment LCD,displays, including 28
individual segment drivers, backplane' driver, and a selfcontained oscillator and divider chain "to,,,generate the
backplane frequency,
The segment and backplane drivers each consist 01a CMOS
inverter, with the n- and p-channel devices ratioed to provide
identical on resistances, and thus equal rise and fall times,
This eliminates any dc component, which could arise from
differing rise and fall times, and ensures maximum display
life,
The backplane output devices can be disabled by
connecting the OSCillator input (pin 36) to GROUND. This
allows the 28 segment outputs to be synchronized directly to
a signal input at the BP terminal (pin 51. In this manner,
several slave devices may be cascaded to the backplane
output of one master device, .or the backplane may be
derived· from an external source. This allows the use of
displays with characters in multiples of four and a single
backplane. A slave device represents a load of approximately
200pF (comparable to one additional segment>, thus the
limitation of the number of devices that can be slaved to
,one master device backplane driver is the additional load
represented by the larger backplane of displays of more than
four digits; and the effect of that load on the backplane rise
and fall times. A good rule of thumb to observe in order to
minimize power consumption is to keep the rise and fall
times less than about 5 microseconds. The backplane output
driver should handle the backplane to a display of 16 one,half-inch characters (rise and fall times not exceeding 5",s. ie,
3 slave devices. and the display backplane driven by a fourth
master device). It is recommended that· if more than .four
devices are to be slaved together, that the backplane signal
be derived externally and all the ICM1211 devices be slaved
to it: This external signal should be capable of driving very

LED DEVICES
The LED devices in the family (lCM7212, 7212A, 7212M,
7212AM) provide outputsjsuitable for directly driving fourdigit by seven-segment common-anode LED displays,
including 28 individual segment drivers, each consisting of a
low-leakage, current-controlled, open-drainn-channel
transistor.
The drain current of these transistors can be controlled by
varying the voltage at the BRIGHTNESS input (pin 51. The
voltage at this pin is transferred to the gates of the output
devices for "on" segments, and thus directly modulates the
transistor's "on" resistance. A brightness control can be
easily implemented with a Single potentiometer controlling
the voltage at pin 5, connected as in Fig (31. The
potentiometer should be a high value (100KO to 1MO) to
minimize 12R power consumption, which can be significant
when the display is off.
The BRIGHTNESS input may also be operated digitally as a
display enable; when high, the display is fully on, and low
fully off. The display brightness may also be controlled by
varying the duty cycle of a signal swinging between the two
voltages at the Brightness input
Note that the LED devices have two connections for
GROUND; both of these pins should be connected, The
6·31

[8
•

ICM7211/ICM7212
double connection is necessary to, minimize effects of bond
wire resistancewith the large total display currents possible.
When operating LEO devices at higher temperatures and/or
higher supply voltages, the device power dissipation may
need to be reduced to prevent excessive chip temperatures.
The maximum power dissipation is 1 watt at 25°C, derated
linearly above 35°C to 500mW at 70°C (-15mW/oC above
35° C)' Power dissipation for the device is given by:
P '= (V+"VFLED) (ISEG) (nSEG)
where VFLED is the LEO forward voltage drop, ISEG is
segment current, and nSEG is the' number of "on" segments.
It is recommended that if the device is to be operated at
elevated temperatures the segment current be limited by use
of the Srightness input to keep power dissipation within the
limits described above. ,

A select code of 00 writes into 04, SC2 = 0, SC1 =' 1 writes
into 03,SC2 = 1, SC1 = 0 writes into 02, and 11 w~ites into
01. The timing relationships for inputting data are shown in
. Fig (2), and the chip select pulse widths and data setup and
hold times are specified in Table 1.

BINARY
B3 B2 B1 BIl

a
a
a
a
a
a
a
a

- - - t _ - - V+(LED ANODES)
100kfl-1M!l

_

=:!~HTNESS

a a
a' a
a
a
a
a
. 1

Figure 3: Brightness control

INPUT CONFIGURATIONS AND OUTPUT CODES

D]
•

The standard devices in the ICM7211/12 family accept a
four-bit true binary (je, positive level = logical one) input at
pins 27 thru 30, least significant bit at pin 27 ascending to the
most significant bit at pin 30. The ICM7211, ICM7211 M,
ICM7212, and ICM7212M devices decode ,this binary input
into a seven-segment alphanumeric hexadecimal output,
while the ICM7211A, ICM7211AM, ICM7212A, and
ICM7212AM decode the binary input into the same sevensegment output as in the ICM7218 "Code S", ie 0-9, dash, E,
H, L, p, blank. These codes are shown explicitly in Table 2.
Either decoder option will correct~y decode true SCDto a
seven-segment decimal output.
'
,
These devices are actually mask-programmable to provide
any 16 combinations of the seven segment outputs decoded
from the four input bits. For larger quantity orders, (10K pcs.
minimum) custom decoder options can be arranged.
Contact the factory for details.
The ICM7211, ICM7211A, ICM7212, and ICM7212A devices
are designed to accept multiplexed binary or BCD input.
These devices provide four separate digit lines (least
significant digit at pin 31 ascending to most significant digit
at pin 34), each of which when taken to a positive I,evel
decodes and stores in the output latches of its respective
digit the character corresponding to the data at the input
port, pins 27 through 30. More than one digit select may be
activated simultaneously (which will write the same
character into all selected digits), although the timing
requirements 'shown in Fig (1) and Table 1 for data setup,
hold, and inter-digit select times must be met. to ensure
,
correct output. '

a

HEXADECIMAL
ICM7211(M)
ICM7212(M)

CODE B
ICM7211A(M)
ICM7212A(M)

L'
"

'-'".,

,

,
j
'-:'
-'
"

a
a
a

1

1

1

a
a
a
a

a
a

a

1

a

1

1

a
a

a

1

1

a

,-:'
:::;

.'

'.',
,-

'-:
.:

:]

,.-'
I:;
-,,
c·
'-'
'j

,.
,,

(J

c'

'-'0

.'

J

,:J

"

c

,.b

'.
:-1,

,-,

,-

,.':'
':,.

,:]
J

,.

(BLANK)

Table 2: Output Codes

SEGMENT ASSIGNMENT

APPLICATIONS
1. Ganged ICM7211's Driving 8-Digit LCD Display.
04

The ICM7211M, ICM7211AM, ICM7212M, and ICM7212AM
devices are intended to accept data from a data bus under
processor control.
In these devices, the four data input bits and the two-bit digit
select code (OSl pin 31, OS2 pin 32) are written into input
buffer latches when both chip select inputs (CS1'pin 33, CS2
pin 34) are taken low. On the riSing edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the
contents of the digit select code latches.

03

02

BCD/BINARY_~_LWW-+--'======fIIH""--'
DATA

DIGIT
SELECTS

6·32

1 9!~-~~
05

~~

_ _ _ _ _ _ _ _ _ _ _ _ _ _, - - - - '

ICM7211/ICM7212
2. 4 1/2 Digit LCD DPM with Digit Blanking on Overrange.

4 112 DIGIT LCD DISPLAY

-I5V

~/BBBB
1 '

*4030

~
~

......

+5V

BUSY

~

D1

L..a

POL

D2

-[!

Rlii

D3~

CaMP IN

D4·

.:1

:::r

REF

1PF=~

RC1

100kn

~

O.1pF9=_

:TI

~
--@

ICL71C03A

B2

~

RC2

B1

iii'

INPUT

D5

iE

CLOCK

A2IN

~OR

-

A20UT

lID-~ov

ICM7211A

33 D3

I

f--L..'

CD4071 1

2,3,4
11-26
37-40

3404

-

OPTIONAL
CAPACITOR

29 B2

I
I

~mII
I.

GMI

J-

+5V
1/4 CD4030

V+1~.
+sv

__

'-----~

36kn

>~

rj ICL8D52A

.00pF II

. -g

>

-15V

ICL8D68A

~

rr

~

300kn

14

+5V

GNO...... V+@-

~

1

':!

~5.n

b

"~

"

---1

j

Ill--

vt;Ok
ADJUSTT o fe = 120kHZ

3DOpF

ov

100k{l

~

~+15V

+15V: ANALOG POSITIVE VOLTAGE
+ "SV:' DIGITAL POSITIVE VDLTAGE (v+)
ov: DIGITAL GROUND VOLTAGE
-15V: ANALOG NEGATIVE VOLTAGE

~
>100n

-E RESET

10~~

..fA J

T

II

.2li;F

~10pF

=

..t ANALOG GND'

NOTE: See also ICLS0521S06SIICL71 C03 Data Sheet for a similar
circuit with fewer features.

6~33

+5V

2780
35 GROUND

OV.

I

111.OpF

......

t---

26B1

'- +5V

-- t.

-1:
22-1 OOpF

OSC36

2 ICM7555
• OUT
~

-15V-g

I--

30 B3

1

hL,..)

iT'

DIG.GND

UR

31 D1

32D2

I

iTiiOiE 1i'
-;'.

ANALOGGND

~L

1

~

B8

BACKPLANE

SBP

r;---cli4iiii1

~

~
·B4
~

-15V--{! -15V

INPUT

~

41/2/3Tt2

1--

I

2B SE~MENTS D1-04

ICM7211/ICM.7212
3. 8048/8748/1M87C48 Microprocessor Interface.
8·DIGIT
LCD DISPLAY

BB B B BBB

v+ +5V

h~

4.

26

2.

vee VDDVSS

~~

~~
-=~

2 XTALl

3 XTAL2

r~-'"
=
~ 35

1/0

_ 36 OSC

-1-

{r

~,

SEGMENTS 6·26
DATA
37·40

BP 5

nTa-~~D3~1 D3~2 C3~1 C3~2

BIICM7211M
LOW ORDER DIGITS

{r

~,

5 BP
6-26 SEGMENTS
OATA 37-40

y+ 1 ,3S
OSC36

80-83
OS1 DS2 CS1 CS2
'27Ys"'2"9'"30" 31 32 33 34

y+~

4 RESET

iNT

l

PSi N

P~~G ~ RJ>

I

I

I

-

PBa 32

33
3'
3S
36
37
38
PB739

8355/8755
ROM/EPROM
WITH 1/0
EXPANDER

11 ALE

8355/8755 NOT NECESSARY
TO ICr-,7211 INTERFACE

7

3

-=

I

I

NC

NC

-'-

LCD
DISPLAY

LED
DISPLAY

ICM72111PL
'ICM7211A IPL
ICM7211M IPL
ICM7211AM IPL
ICM72121PL
ICM7212A IPL
ICM7212M IPL
ICM7212AM IPL

OUTPUT CODE
HEXADECIMAL
CODE B
HEXADECIMAL
CODE B
HEXADECIMIo\L
CODE B
HEXADECIMAL
CODE B

INPUT CONFIGURATIONS
MULTIPLEXED 4-BIT
MICROPROCESSOR INTERFACE
MULTIPLEXED 4-BIT
MICROPROCESSOR INTERFACE

TABLE 3: Option Matrix and Ordering Information

6·34

2.

2'
26
27
28
29
3.
PA731

810R
10lQW

\

~

•

VDDVSS
PAD 24

12 ADO
13AD1
14 AD2
15 AD3
16 AD4
17 ADS
18 ADS
19 AD7

900

ORDER PART NUMBER

vee

Ne- 1 PROG

DBa 12
13
14
lS
16
17
18
DB719

1 T.

A1~E

22 A9
23 Al0
2eE
4 RESET

36
37
P2738 rliO

39T1

4.

21 AS

IM80C48 P2• 21
7 EA
8048
22
8748
~:
I'COMPUTER 3.

6

Y++5V

:::r:;:.

33
P1734

'Ne- S 55

~PUT{

Pl. 27
28
29
3.
31
32

ICM7211M
HIGH ORDER DIGITS

6

DICE
ICM7211/D
ICM7211A/O
ICM7211M/O
ICM7211AM/O
ICM7212/0
ICM7212A10
ICM7212M1O
ICM7212AM/O

ICM7213

One Second/One Minute
Precision Clock and
Reference Generator

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•

The ICM7213 is a fully integrated micropower oscillator and
frequency divider with four buffered outputs suitable for
interfacing with most logic families. The power supply may
be either a two battery stack INi-cad, alkaline, etc.> or a
regular power supply greater than 2 volts. Depending upon
the state of the WIDTH, INHIBIT, and TEST inputs, using a.
4.194304 MHz crystal will produce a variety of output
frequencies including 2048 Hz, 1024 Hz, 34.~33 Hz, 16 Hz, 1
Hz, and 1/60 Hz (plus composites!.
The ICM7213 utilizes a very high speed low power metal gate
C-MOS technology which uses 6.4 volt zeners between the
drains and sources of each transistor and also across the
supply terminals. Consequentiy, the ICM7213 is limited toa6
volt maximum supply voltage, although a simple dropping
network can be used to extend the supply voltage range well
above 6 volts (see Figure 2!.

.•
•
•
•

Guaranteed 2 volts operation
Very low current consumption: Typ. 100MA @ 3V
All outputs TTL compatible
On chip oscillator feedback resistor
Oscillator requires only 3 external components:
fixed capacitor, trim capacitor, and a quartz crystal
Output inhibit function
4 simultaneous outputs: one pulse/sec, one pulse/
min, 16Hz and composite 1024 + 16 + 2Hz outputs
Test speed-up provides other frequency outputs
Input static. protection - no special handling
required

BLOCK DIAGRAM
(4,194,304Hz)

(a,192Hz)

'1024Hz)

(16Hz)

(64Hz)

(4Hz)

OSCOUT~

ORDERING INFORMATION
ICM7213

PIN CONFIGURATION

L=
I

(OUTLINE DRAWING PD)

.PO

Package
PO = 14 Pin Plastic
. . Temperature Range
-20°C to +85°C
L -_ _ _ _ _ _ _ Type
.

WIDTH

OUT4

OUT3

OUT2

INHIBIT
GROUND
OSC OUT

Order Devices by Following Part Number
ICM72131PD
Order Dice by Following Part Number
ICM7213D

6-35

OUT 1
TEST

v+

OSCIN

N/C

N/C

N/C

ICM7213
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .•.....•••••.....•..•..•.•..•.•.••....•.••...••...•......•. 6.0V
Output Current (Any output) ••.••..••.••..•...............••.••.••.•...... 20mA
All Input and Oscillator Voltages (Note 1) ...•..••..••.•• Equal to but not greater
than the supply voltage
All Output Voltages (Note 1) .••...•.•.•...••...•.•..•.•.••...••..•. 0:5 Vo :5 +6
Operating Temperature Range.................................. -20°C to +85°C
Storage Temperature' Range .•......•..•..•....••.....••....... -40°C to +125°C
Power Dissipation (Note 2) .•••.•..•.•.•..•............•...••.••.•....•.. 200mW
Lead Temperature (Soldering 10 sec.! .................................... 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device afthese or any
other conditions above those Indicated In the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
NOTE 1: The ICM7213 like most C-MOSdevices, mayenteradestruCtive latchup mode if an input
or output voltage is applied in excess of those defined and there is no supply current
limiting.
NOTE 2: Derate linearly power rating of 200mW at 25°C to 50mW at 70°C.

OPERATING CHARACTERISTICS
TEST CONDITIONS: V+ = 3.0V, fose = 4.194304 MHz, Test Circuit, TA = 25°C unless otherwise specified
PARAMETER
Supply Current
Guaranteed Operating Supply

Voltage Range
Typical Operating Supply
Voltage Range
Output Leakage Current
Output Sat. Resistance
Inhibit Input Current
Test Point Inpllt Current
Width Ihput Current
Oscillator gm
Oscillator Frequency Range (Note 3)
Oscillator Stability
Oscillator Start Time

SYMBOL
1+

CONDITIONS

MIN

TYP

MAX

UNITS

100

140

p.A

VOP

-20°C < TA < 85°C

2

4

Vor>

-20°C < TA < 85°C

1.4

5

IOlK
ROUT

Ii

Any output, IOlK = 2.5mA
Inhibit terminal connected to V+

ITP

Test pOint terminal connected
to V+

Iw

Width terminal connected to V+
V+ =2V

gm
fose

120

10
200

10
10

40
40

10

40

Any output, VOUT = 6 Volts

2V < V+ < 4V

Is

V+ = 3.0 lIolts
V+ = 2.0 volts

p.A

n
p.A

umho

100
1

fSTAB

V

10
1.0
0.1
0.2

MHz
ppm
sec

NOTE 3: The ICM7213 uses dynamic dividers for high frequency division. As with any dynamic system, information is stored on very
small nodal capacitances instead of latches (static systeml, therefore there is a lower frequency of operation. Dynamic dividers
are used to improve the high frequency performance while at the same time significantly decreasing power consumption. At
low supply voltages, operation at less than lMHz is. possible. See application notes.

·6·36

ICM7213
SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE
130
~120

::t

I

1- 110

zw

VS~pp;3V

~100

>
..J
t

1 25~-r--~-b~+-~~

::t.

1 250

I

C

9
z

!z

200

I-

I\.

I

"- i'-..

:l
tJ 90

/
r-- f-""""

a100r--r~~~--t--t~

a..

0

o

0.1' 0.2 0.3 0.4 0.5 0.6
OUTPUT SATURATION
VOLTAGE (ANY OUTPUT)

OSCILLATOR STABILITY AS A
FUNCTION OF SUPPLY VOLTAGE

~
~

+1.5

~

:>w

+1.0

:>w

oZ

C

C

~ E +0.5

> +1

z..

tJ E

ilj Ii: 0 r--t:?C""'=-t---b-Lf----l

0

:lO~

w!!:

~$-1

a: ..... -0.5

:5

o

L-....L.__.l...--1..__.l--1..---l

OSCILLATOR STABILITY
AS A FUNCTION
OF DEVICE·TEMPERATURE

::

5f-#-*--~-r--+-~~

I:l

2.0
3.0
4.0
5.0
SUPPLY VOLTAGE v+ - V-

0 +20 +40 +60 +80
TEMPERATURE _.oC

~I

"'E

~

,'REFERENCE
COUNTER

MAIN COUNTER

1i
"00

Frequency (fA)

Input A

100 Hz (Oscillator
-1- 105 or 104)
Input A

Period (tA)

Oscillator

Ratio (fAlfs)

Input A

Input B

Time Interval
(A- B)

Osce(Time
Interval FF)

Time Interval FF

Unit Counter
(Count A)

Input

Osc. Freq.
(fose)

Oscillator

~

V+ -VOUT (VOLTS)·

+

100 Hz (Oscillator
105 or 104)

-1-

m
•

'

FIGURE 4. ICM7216A & C TyplcallOIGvs. V - Vour•
4.5V :5 V+:5 6.0V

Not Applicable

EXTernal DECimal Point Input -When the external decimal
point is selected this input is active. Any o(the digits, except
D7, can be'connected to this pOint. D7 s~ould not be used since
it will override the overflow output and leading zeros will
remain unblanked after the decimal point. This input is availa.
ble on the ICM7216C and D only.

HOLD Input :.-. When the HOLD Input is at v+, any measurement in progress is stopped, the main counter is reset and the
chip is held ready to initiate a new mfilasurement. The latches
which hold the main counter data are not updated so the last
completemeasurementis displayed. When HOLD is changed to GND a new measurement is initiated.
VOUT (VOLTS)

RESET Input -,- Tile RESET Inpui is the same as an inverted
HOLD Input, except the latthes for the Main, Counter are
enabled, resulting inan output of all zeros, and the pin has a
pull-up.

80

r-----,-:---:------,----,---::->l

DISPLAY CONSIDERATIONS
The display is multiplexed at a 500 Hz rate with a digit time of
244 I'sec. An interdigit blanking time of 6 I'sec is used to
prevent ghosting between digits. The decimal point and leading zero blanking assume right hand decimal point displays,
and zeros following the decimal point will not be blanked. Also,
the leading zero blanking will be disabled, .when the Main
Counter overflows. Overflow is indicated by the decimal point
on digit 7 turning on.
'
The ICM7216A and C are deSigned to drive common anode
LED displays at peak current of 25mA/seg~ent, using
displays with VF = 1.B V at 25mA. The average DC current will
be over 3mA under these coriditions. The ICM7216B and D
are designed to drive common cathode displays at peak
current of 15mA/segment using displays with VF,= 1.8V at
15mA. Resistors can be added in series with the segment
drivers to ,limit the display current in very efficient displays, if

VOUT (VOLTS)

FIGURE 5. ICM7216A & C'TypicaiiSEG
6·48

VS;

Your '

D~DIl.

ICM7216
200,......------,------,--,.----,

-20"C

/

/

/

ACCURACY

/

In a Universal Counter crystal drift and quantization errors
cause errors. In Frequency, Period and Time Interval modes,
a signal, derived from the oscillator is used in either the
Reference Counter or Main Counter. Therefore, in, these
modes an error in the oscillator frequency will cause an
identical error in the measurement. For instance, an
oscillator temperature coefficient of 20ppm/oC will cause a
meallurement error of 20ppm/oC.

1
!:

!2

.!'

(a)

Vour IVOL TS)

200,......----r----~~---_,

,In addition, there is a quantization error inherent in any
digital measurement of ±1 count. Clearly this error is reduced
by displaying more digits. In the Frequency mode the
maximum accuracy is obtained with high frequency inputs
and in Period mode maximum accuracy is'obtained with .Iow
frequency inputs. As can be seen in Figure 8, the least'
accuracy will be obtained at 10 KHz. In Time Interval
measurements there can be an error of 1 count per interval.
As a result there is the same inherent accuracy in all ranges
as shown in Figure 9. In Frequency RatiO measurement can'
be more accurately obtained by averaging over more cycles
of INPUT B as shown in Figure 10.

50r---D~-~-~-~r_-----~

(b)

Vour IVOLTS)

FIGURE 6. ICM7216B & D TyplcallOIGIT vs. YOUT
30,......----,r-------,----.,

FREOUENCY

1Hz I

FIGURE 8. Maximum Accuracy of Frequency and Period
Measurements Due to Limitations of
Quantization Errors

20

,

~
o

a;

'"ffi
'"

ICM7216B

o

ICM7216A
I-

:J

~

:J

o

0:
ci
EXT OSC INPUT
OSC INPUT

EXT OSC INPUT
OSC INPUT

05

OSC OUTPUT

==,....,,--

SEG B

osc OUTPUT

06

SEGC
SEG F

07 '
RANGE INPUT
EXT D.P. INPUT

HOLD INPUT

RI\NGE INPUT
EXT D.P. INPUT

HOLD INPUT

, INPUTA

INPUT A
RESET INPUT

,CONTROL INPUT
MEASUREMENT iN
PROGRESS

i'iEsET INPUT

CONTROL INPUT
MEASUREMENT IN

SEG F

D7

PROGRESS

06

SEGC

I-W

~f:3

:::len

o

(!l« I 0
ffif3 >f:3en

en",

co

ffi-

en

0:
ci

ICM7216D

ICM7216C

6-54

ICM7217 Series
ICM7227 Series
4 Digit CMOS
Up/Down Counter/
Display Driver
FEATURES

figurations available. Digit and segment drivers are provided
to directly drive displays of up to .8" character height
(common anode) at a 25% duty cycle. The frequency of the
onboard multiplex oscillator may be controlled with a single
capacitor, or the oscillator may be allowed to free run.
Leading zeroes can be blanked. The data appearing at the 7
segment and BCD outputs is latched; the content of the
counter is transferred into the latches under external control
by mears of the Store pin.

• Four decade, presettable up-down counter with
parallel zero detect
• Settable register with contents continuously
compared to counter
• Directly drives multiplexed 7 segment common
anode or common cathode LED displays
• On-board multiplex scan oscillator
• Schmitt trigger on count input
• TTL compatible BCD I/O port, carry/borrow, equal,
and zero outputs
• Display blank control for lower power operation;
quiescent power dissipation < SmW
• All terminals fully protected against static discharge
• Single SV supply operation

The ICM7217/7227 (common anode) and ICM7217 A17227 A
(common cathode) versions are decade counters, providing a
maximum count of 9999, while the ICM7217B, 7227B
(common anode) and ICM7217C17227C (common cathode)
are intended for timing purposes, providing a maximum
count of 5959.
These circuits provide 3 main outputs; a CARRY/BORROW
output, which allows for direct cascading of counters, a
ZERO output, which indicates when the count is zero, and an
EQUAL output, which indicates when the count is equal to
the value contained in the register. Data is multiplexed to and
from the device by means of a tri-sta.te BCD I/O port. The
CARRY/BORROW, EQUAL, ZERO outputs, and the BCD
port will each drive one standard TTL load.
To permit operation in noisy environments and to prevent
multiple triggering with slowly changing inputs, the count
input is provided with a Schmitt trigger.
Input frequency is guaranteed to 2 MHz, although the device
will typically run with fin as high as 5 MHz. Counting and
comparing (EQUAL output I will typically run 750 kHz maximum.

DESCRIPTION
The ICM7217 and ICM7227 are four digit, presettable up/
down counters, each witt) an onboard presettable register
continuously compared to the counter. The ICM7217
versions are .intended for use in hardwired applications
where thumbwheel switches 'are used for loading data, and
simple SPOT switches are used for chip control. The
ICM7227 versions are for use in processor-based systems,
where presetting and control functions are performed under
processor control.
These circuits provide multiplexed 7 segment LED display
outputs, with common anode or common cathode con-

PIN CONFIGURATIONS

(OUTLINE DRAWINGS JI, PI)

COUNT INPUT

S'fORE

COMMON ANODE

COMMON CATHODE

19 GROUND
jjj

D2
il3
D4

6-55

Dl
•

ICM7217/7227
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (common anode/Cerdip) .......................•. 1 W } Note 1
Power'Dlsslpatlon (common cathode/Plastic) ...........•....•.... 0.5 W
Supply Voltage V+ -V- ....................................................... 6V
Input voltage (any terminal> ............... , ..•.. V+ +0.3V,Ground -o.3V - Note 2
Operating temperature range................................... -20°C to +85°C
Storage temperature range ...................... ; ............. -55° C to +125° C
Absolute maximum ratings define stress limitations 'which if exceeded may permanently damage the device. For continuous operation'these
devices must be operated under the conditions defined under "Operating Characteristics."
'

OPERATING CHARACTERISTICS

TA = 25°C Test Circuit Display Diode Drop 1 7V unless otherwise specified
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Supply current
IMIN,
Display Off, LC, DC, UP/DN,
(7217)
(Lowest power mode)
ST, RS, BCD I/O Floating or at V+ (Note 3)
350
500
fJ.A
Supply current
Display off (Note 3)
1t:.IIN,
300
500
fJ.A
(7227)
(Lowest power mode)
Supply current
lop
Comm0n Anode, Display On, all "8's" ,
175
200
mA
OPERATING
Common Cathode, Display On, all "8's"
85
100
mA
V+
Supply Voltage
4.5
V
5
5.5
Digit Driver output
Common anode, VOUT = V+ -2.2V
175
200
IDIG
mA
current
peak
Segment driver
-25
-40
Common anode, VOUT = +1.3V
ISEG
mA
output current
,
peak
Digit Driver
-75
-100
Common cathode, VOUT = +1.3V
IDIG
mA
output current
peak
Segment Driver
Common cathode VOUT = V+ -2V
10
ISEG
12.5
mA
output current
peak
Ip
ST, RS, UP/DN input
VOUT = V+ -2V (See Note 3)
5
25
J1.A
pullup current
3 level input impedance
100
ZIN
kf1
BCD 110 input,
ICM7217 common anode (Note 4)
VSIH
1.3
V
high voltage
ICM7217 common cathode (Note 4)
4.1
V
ICM7227 with 50pF effective load
3
V
BCD I/O input
ICM7217 common anode (Note 4)
VSIL
0.8
V
low voltage
3,7
ICM7217 common cathode (Note 4)
V
V,
ICM7227 with 50pF effective load
1.5
BCD I/O input
Ispu
ICM7217 common anode Y,N = V+ -2V (Note 3)
5
25
J1.A
pullup current
BCD 110 input
ICM7217 common cathode Y,N = +1.3V (Note 3)
5
25
ISPD
fJ. A
pulldown current
BCD 110, Carry/borrow
VOH = V+ -1.5V
100
ISOH
J1.A
zero, equal outputs
output high current
-2
BCD I/O, Carry/borrow
VOL = +O.4V
mA
ISOL
zero, equal outputs
output low current
Count input frequency
V+ = 5V ± 10%, -20°C 
10
KHz
fds
oscillator frequency
DC
Operating Temperature
-20
Industrial temperature range
,TA
85
Range
NOTE 1 These limits refer to the package and will not be obtained during normal operation.
NOTE 2 Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than V+ or less than V- may cause desrructive device latch up, Forthis reason it is recommended that the power supply to the device be
'established before any inputs are applied and that in multiple systems the supply to the ICM7217/7227 be turned on first.
NOTE 3 In the ICM7217 the Up/Down, Store, Reset and the BCD I/O as inputs have pull up devices which consume power when connected to
the negative supply. When all these terminals are connected to the negative supply, with the display off, the device will consume
typically 750 !J,A The ICM7227 devices do not have these pullups and thus are not subject to this condition.
NOTE-4 fhese voltages are adjusted to allow the use of thumbwheel switches for the ICM7217 versions, Note that a positive level is taken as a
logic zero for ICM7217 common-cathode versions only,

v+

= 5V +10%
-

.

6-56

ICM7217/7227
TEST CIRCUITS

Common-Anode
Display

.

f~'b'-'
1-' L'
'-'1
r.,.
C' C]
D.

l03

f dB-

e-

b-

g-

01

J02

f
b
humbwheel

Switches

Carry _

~
g:;g!:~~BBBB

rero -

BC
BC
BC D 1102's
BC D 1101's

1
2

EqUal-3

D. 03 02 01

•
•
•
5

7
Count Inpul- 8

2'
27
2.
2S
2.
ICM7217 23
ICM72178 22
21
2.

5Y

y+ln
~l
-:r

;

'T IT!

==

I

28
27

Control

2.
2S

18
17
16
15

~~

LC 14
Scan

I~

~18Y

,.

Up/Down 10
LR 11
\

~

-l N,O. '

ICM7227A

2'
231-

Count Input

ICM7227C

21
22
20

c"'o:;;n:;:,,:;;~t:;;:"'o;;;~anaR":"'~d:i'.---...114

~

t-:j:::j:p===:jJ

4 Bit
Data Bus

~E:lE=:;=t~~

Display Control

"1718
~:

(from proceslo,r)

..L

Figure 1
Figure 1 shows the ICM7217 in thecommon-anode version' and the ICM7227 in the common-cathode version,

RESET ----1--'"-1
ZERO ----+---1

UP/ON ----+--1

COUNT----~-I

",
",2',
1',

1 - - - - - - - SCAN

MUXED L.R. 4

MUX, VO

1 - - - - - - - LOAD COUNTER

[2~~~~~~Jr-__I-::============±~=M=U=X=E=O=L=C=':'~
1-----r-----~------~-_CO~U~TP,PU"'T~M~UU:X~.t.________~
CONTROL
LOGIC
AND DISPLAY

04 030201

Figure 2: ICM7217 Functional Block Diagram

6-57

DISPLAY
CONTROL
LOAD REGISTER

ICM7217/7227

"'-----~- , ----

SCAN

INTERNAL
OUTPUT

"'""----.,;..----

.......
~,-

....

.......

....

asc.

INTERNAL

r:. ______________________________ __________
l~~

l

~

!?!.-J

EXTERNAL
(COMMON
ANODE)

DIGIT

~I'

I

;;;D3;,----------r-...,l4H

INTERDIGIT BLANK

02

o.--,~

STRO.BES

__________________ ______________________
~

~I

L

Figure 3: Multiplex Timing

COMMON ANODE DISPLAY
TO 04 STROBE

COMMON CATHODE DISPLAY

TOD1 STROBE

TO 04 STROBE

TO 01 STROBE

IN914 OR
EQUIVALENT

,,-8_-r1_~1/

I

TO BCD INPUTS OF 7217, 72178

TO BCD INPUTS OF !217A, 7217C

Figure 4: Thumbwheel switch/diode connections

'cws-t--'rcs-

CWS
INPUT

r----'Df-

I

Of

INPUT

:--'cos_

;+-tcDH

'---J

I-

~

'\

'\

t

ST

SC1,SC2 LATCHES REseT
.. {

UfO

REGISTER WRITE CYCLE (Sel,Se2 "" 1,1)

SCI

~ fiLL.:

SC2

~ ~,

BCD I/O

(COUNTER WRITE CYCLE IS S'IMILAR: Sel, SC2 = 1, 0)

tlDH

Xi77ll7ll7i,

X;

'IX

~ b7ii

.{.SCI

DATA OUTPUT CYCLE (Sel,Se2 "" 0,1)

SC2

~~

BCCIIO
OUTPUT

tODA-

~

f-

-

I
-

j---tODH

="DON'T"CARE

*: CONTROL WORD INPUTS

Figure 5: ICM7227 I/O Timing (See Table 2)

6·58

-

ICM7217/7227
CONTROL INPUT DEFINITIONS ICM7217
INPUT
Store (ST)

TERMINAL
9

Up/Down (U/D)

10

Reset (RST)

14

Load Counter
LC/I/O OFF

12

Load Register
LR/OFF

11

Display Control
(DC)

VOLTAGE
V+ (or floating)
Ground
V+ (or floating) ,
Ground
V+ (or floating)
Ground
Unconnected
V+
Ground
Unconnected
V+
Ground

FUNCTION
Output latches not updated
Output latches updated
Counter counts up
Counter counts down
Normal Operation
Counter Reset
Normal operation
Counter loaded with BCD data
BCD port ,forced to Hi Z condition
Normal operation
' Register loaded with BCD data
Display drivers disabled; BCD port
forced to Hi Z condition, mpx counter
reset to 04; mpx oscillator inhibited

Unconnected,
V+

23 Common Anode
20 Common Cathode

Ground

Normal operation
Segment drivers disabled
Leading zero blanking inhibited

CONTROL INPUT DEFINITIONS ICM7227
INilUT
Data Transfer (DT)

Control
Word
Port
"
"
"

TERMINAL
13

Store (ST)

VOLTAGE
V+
Ground

V+ (During CWS Pulse) Output latches' updated
Output latches not updated
Ground

9

Up/Down (U/D)

V+ (During CWS Pulse) Counter counts up
Counter counts down
Ground
V+ = 1
SC1, SC2
00 Change store and
Ground
up/down latches. No data
transfer. 01 Output latch
data active
10 Counter to be preset
11 Register'to be preset

10

,
Select Code Bit 1 (SC1)
Select Code'Bit 2 (SC2)

11
12

Control Word Strobe (CWS)

14

Display Control (DC)

FUNCTION
Normal Operation
Causes transfer of data
as directed by select code

23 Common Anode
20 Common Cathode

V+
Ground

Normal operation
Causes control word to be
written into control latches

Unconnected
V+
Ground

Normal operation
Display drivers disabled
Leading zero blanking
inhibited
'

DESCRIPTION OF OPERATION
outputs source >60}.LA.
The digit and segment drivers provide a decoded 7segment
display system, capable of directly driving common anode
LED displays at typical peak currents of 40mA/seg., This
corresponds to average currents of 10mA/seg at a 25%
multiplex duty cycle. For the common cathode versions,
peak segment currents are 12.SmA, corresponding to
average segment currents of3.1mA. The OISPLAYpin controls the display output using three level logic. The pin is
self-biased to a voltage approximately 1/2 IV' I; this corresponds to normal operation. When thispin is connected to V+,
the segments are inhibited, and when connected to V-, the
leading zero blanking feature is inhibited. For normal
operation (display on with leading zero blanking) the pin may
be left open. The display may be controlled with a 3 position
SPOT switch; see fig. 1.

OUTPUTS
The CARRY/BORROW output is a positive goirig pulse
occurring typically SOOns after the positive going edge of the
COUNT INPUT. It occurs when the counter is clocked from
9999 to 0000 when counting up and from 0000 to 9999 when
counting down. This output allows direct cascading of
counters.
The EQUAL output assumes a negative level when the contents of the counter and register are equal.
The ZERO output assumes a negative level when the content
of the counter is 0000.
The CARRY/BORROW, EQUAL and ZERO outputs will drive
. a single TTL load over the full range of supply voltage. and
ambient temperature; for a logic zero, these outputs will sink
2mA @O.4V IOn resistance 200 ohms I, and for a logic one, the
6-59

U~UI!:.

ICM7217/7227
The BCD I/O port provides a means of transferring data to
and from the device. The ICM7217 versions multiplex data
into the counter or register via thumbwheel switches,
depending on inputs to the LOAD COUNTER or LOAD REGISTER pins; in the ICM7227 versions, input/output control
and timing must be provided externally. When functioning as
outputs, the BCD I/O pins will drive one standard TTL load.
Common anode versions have internal pull down resistors
and common cathode versions have internal pull up resistors
on the four BCD I/O lines.
The onboard multiplex scan oscillator has a nominal freerunning frequency of 10kHz. This may be reduced by the
addition of a single capacitor between the SCAN pin and the
positive supply, or the oscillator may be directly overdriven
to about 20kHz. Capacitor values and corresponding
nominai oscillator frequencies, digit repetition rates, and
loading times (for ICM7217 versions) are shown in Table 1,
below.
The internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse occurring at the
oscillator frequency. This pulse clocks the four-state
counter which provides the four multiplex phases. The short
pulse width is used to delay the digit driver outputs, thereby
providing inter-digit blanking which prevents ghosting. The
digits are scanned from MSD (D4) to LSD (D1). See Fig. 3 for
the display digit multiplex timing.
Table 1
Digit'
Nominal
Scan Cycle
Oscillator
Repetition
Scan
Time
Frequency
Date
Capacitor
400,us
10kHz
None
2.5kHz'
20pF
1.2kHz
800,us
5kHz
250Hz
4ms
90pF
1kHz

•

CONTROL'OF ICM7217

•

The counter is incremented by the riSing edge of the count
input signal when UP/DOWN is high. It is decremented when
UP/DOWN is low. A Schmitt trigger on the COUNT INPUT
provides hysteresis to prevent double triggering on slow rising edges and permits operation in noisy environments.

'

The STORE pin controls the internal latches and consequeritly the Signals appearing at the 7-segment and BCD
outputs. Bringing'the STORE pin low transfers the contents
of the counter into the latches.
The counter is asynehronously reset to 0000 by bringing the
RST pin low. The count input is inhibited during reset and
load counter operations. The STO, RST and UP/DOWN pins
are provided with pullup resistors of approximately 75 k!l.
The BCD I/O pins. the LOAD COUNTER ILCI, and LOAD
REGISTER (LR J pins combine to provide presetting and
compare functions. LC and LR are three-level inputs, being
self-biased at approximately 1/2 V+for normal operation. With
both LC and LR open, and thumbwheel switches (if used I set
to "zero" (open), the BCD 1/0 pins provide a multiplexed
BCD 'output of the latch contents, scanned from MSD
to LSD by the display multiplex. In this mode of operation,
the BCD pins will drive one TTL load. When either or both of
the LC or LR pins is connected to V+, the TTL driver devices
are turned off and the BCD pins become high-impedance
inputs. When LC is 'connected to V+, the count input is
inhibited and the levels at the BCD pins are multiplexed into
the counter. When LR is connected to V+, the levels at the
BCD pins are multiplexed into the register without disturbing
the counter. When both are connected to V+, the count is

6·60

inhibited and both register and counter are presettable.
When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pinsgo to the high impedance state, and the
segment and digit drivers are turned off. This allows the
display to' be used for other purposes and minimizes power
consumption. In this display off condition, the circuit will
continue to count, and the CARRY/BORROW, EQUAL,
ZERO, UP/DOWN, RESET and STORE functions operate as
normal. When LC is connected,to ground, the BCD I/O pins
are forced to the high i'mpedance state without disturbing the
counter or register. See "Control Input Definitions" (pg. 51 for
a catalog'ing of the pins that function as three-state selfbiased inputs and their respective operations.
Note that the ICM7217 and 7217B have been designed to
drive common anode displays. The BCD inputs are active
high, as are the BCD outputs.
The ICM7217A and 7217C are used to drive common
cathode displays, and the BCD inputs are active low. BCD
outputs are active high.

NOTES ON THUMBWHEEL SWITCHES
MULTIPLEXING

8.

The thumbwheel switches used with these circuits (both
common anode and common cathode) are TRUE BCD
coded; i.e. all switches open corresponds to 0000.
, Since the thumbwheel switches are connected in parallel,
diodes must be provided to prevent crosstalk between digits;
See fig. 4.
In order to maintain reasonable noise margins, these diodes
should be specified with low forward voltage drops (lN914l.
During load counter and load register operations" the
multiplex oscillator is disconnected from the SCAN input and
is allowed to free-run. In all other conditions, the oscillator
may be directly overdriven, however the internal oscillator
signal will be of the same duty cycle and phase as the overdriving Signal, and the digits are blanked during the time the
external signal is at a positive level. To insure proper leading
zero blanking, the blanking time should not be less than about
2,us, and by varying the duty cycle, the display brightness may
be altered. Overdriving the oscillator at less than 200Hz may
cause display flickering. See fig. 6 for brightness control
circuits.
These circuits are variable-duty-cycle os.cillators suitable for
overdriving the multiplex oscillator at the SCAN input of an
ICM7217. The inverters should be CMOS CD4000 series, and
the diodes may be any, inexpensive device such as IN914.
When either the LOAD COUNTER (Pin 12/ or LOAD REGISTER (Pin 11, is taken high; the chip executes a sequence of
operations that reads the thumbwheel switches. These inputs
are edge-triggered. and pulsing them high for 500 ns at room
temperature will initiate a full thumbwheel switch scan and
data entry cycle.
When the circuit recognizes that a load, input is high, the
multiplex oscillator and counter are reset (to D41. The internal oscillator is then disconnected from the SCAN pin and
the preset circuitry is enabled. The oscillator starts and runs
with a frequency determined by its internal capacitor, (which
may vary from chip to chipl. When the chip finishes a full 4
digit multiplex cycle (loading each digit from D4 to D3 to D2
to D1 in turn I, it again samples the LOAD REGISTER and
LOAD COUNTER inputs. If either or both is still high, it
repeats the load cycle, if both are floating or low, the oscillator is reconnected to the SCAN pin and the chip returns to
normal operation. Total load time is digit "on" time multiplied
by 4.

ICM7217/7227
caus,e trouble. A simple circuit which provides a reliable
power-up reset and a fast rise time on the RESET input is
shown below.
'

When using the digit outputs as strobes into the thumbwheel
switches, the switched BCD data is inputted and
automatically synchronized to the appropriate digit When
using the digit outputs to gate external logic, it must be
remembered that input data must be valid atthe trailing edge
of the digit output
'
The preset circuitry is used to perform the reset operation by
forcing the BCD input lines to zero, and "presetting" all four
decades of counter in parallel. This affects register loading; if
LOAD REGISTER is activated when the RESET input is low,
the register will be set to zero, since the input lines are forced
'.
to zero.
When using the circuit as a programmable divider (+ by N
with equal outputs) a short time delay (about 11's) is needed
on the EQUAL output to allow the RESET input to establish a
valid duration reset pulse.

33>

--~--~-.-----v+

N.O.-!

iiESET INPUT
ICM7217

SKfl

- - - - -....+,.-----y-

CONTROL OF 7227 VERSIONS
The 7227 series has been designed to permit microprocessor
control of the inputs. BCD inputs and outputs are active high.

rI

47pF

EQUALo----A.IV\~---'-------__OCi RESET

When the circuit is configured to reload the counter or register with a new value from the BCD line's (upon reaching
EQUAL), loading time will be digit "on" time multiplied by
four. If this load time is longer than one period of the input
count, a count.can be lost. Since the circuit will retain data in
the register, the register need only be updated when a new
value is-to be entered. RESET will not clear the register.

SCAN INPUT
ICM7217

SCAN INPUT
ICM7217

1MU

y+ = SV

3Kn

In the IM7227 versions,the STORE, UP/DOWN, SC1 and SC2
(select code bits 1 and 2) pins form a four-bit control word
input. A negative-going pulse on the CWS (control word
strobe) pin writes the data on these pins into four internal
control latches, and resets the multiplex counter in preparation for sequencing a data transfer operation. The select
code 00 is reserved for changing ti1e state of the Store and/or
Up/Down latches without initiating a data transfer. Writing a
one into the Store latch sets the latch and causes the data in
the counter to be transferred into the output latches, while
writing a zero resets the latches causi!1g them to retain data
and not be updated. Similarly, writing a one into the
up/BOWri latch causes the counter to count up and writing a
zero causes the counter to count down. The state of the Store
and Up/Down latches may also be changed with a nonzero
select-code.
Writing a nonzero select code initiates a data transfer
operation. Writing select code of 01 (SC1, SC2) indicates that
the data in the output latches will be active and enables the
BCD I/O port to output the data. Writing a select code of 11
indicates that the register will be preset"a'nd a 10 indicates
that the counter will be preset.
When a nonzero' select code is read, the clock of the fourstate multiplex counter is switched to the DT (DATA TRANSFER) pin .. Negative-going pulses at this pin then sequence a
digit-by-digit data transfer, either outputting data or presetting the counter or register as determined by the select,code.
The output drivers of the BCD I/O port will be enabled only
while DT is low during a data transfer initiated with 01 select
code.
The sequence of digits will be 04-03-02-01, Le. when outputting, the data from 04 will be valid during the first DT
pulse, then 03 will be valid during the second pulse, etc.
When presetting, the data for 04 must be valid atthe positivegoing transition (trailing edge) of the first 5T pulse, the data
for 03 must be valid during the second DT pulse; etc.
At the end of a data, transfer operation, on the positive going
transition of the fourth OT pulse, the SC1. and SC2 control
latches will automatically reset, terminating the data transfer
and reconnecting the multiplex counter clock to the
oscillator. In the ICM7227 versions, the multiplex oscillator is
always free-running, except during a data transfer operation
when it is disabled.
Fig. 5 shows the timing of data transfers initiated with a 11
select code (writing into the register) and a 01 select code
(reading out of the ou'tput latches!. Typical times during
which data must be valid at the control word and BCD I/O
ports are indicated in Table 2.

a

SCAN INPUT
ICM7217

y-= OV

Figure 6: Brightness Circuits

OUTPUT AND INPUT RESTRICTIONS
The CARRY/BORROW output is not valid during load coun'
ter and reset operations.
T,he EQUAL output is not valid during load counter or load
'
register operations.
The ZERO output is not valid during a load 'counter
operation.
,
"
, The RESET input'may be susceptible to noise if its input rise
time (counting out of reset) is greater than about 500l's. This
will present no problems when this input is driven by active
devices (Le., TTL or CMOS logic) bilt in hardwired systems
adding virtually any capacitance to the RESET input can

6-61

[i
•

ICM7217/7227
2. UNIT COUNTER WITH BCD OUTPUT (Figure 7)

Table 2
SYMBOL DEFINITION TIME NS SYMBOL
CONTROL
275
tcdh
lews
WORD
STROBE
WIDTH
INTERNAL
2-3,,5
tics
tids
CONTROL
SETUP
tidh
300
DATA
tat
'TRANSFER
tada
PULSE
WIDTH
CONTROL
300
tadh
leds
DATA
SETUP

DEFINITION TIME N~
CONTROL
300
DATA HOLD

INPUT'
DATA
SETUP
INPUT
DATA HOLD
OUTPUT
DATA
ACCESS
OUTPUT
DATA
HOLD

300

The simplest application of the ICM7217 is a 4 digit unit
counter. All that is required is an ICM7217, apowerf;upply
and a 4 digit display. Add a momentary switch for reset, an
SPOT centercoff switch to blank the display or view leading
zeroes, and one more SPOT switch for up/down control.
Using an ICM7217A and a common-cathode calculator-type
display, results in the least expensive digital counter/display
system available.

300
'CARRY

ZERO

300

COMMON~CATHODE'

300

COUNT INPUT 8

__

_

_

I...J LI LI C)
,I..,JUUO

4
BCD {
OUTPUT·

LED DISPLAY

ICM
7217A

'4I-D-,.c.,SP-LA~Y-----=--....-1

Figure 9: 8 Digit Up/Down Counter

.

.

the register can be set with the stop point and the EQUAL
,outp~t used to stop the recorder either on fast forward, play
or rewind.
To make the recorder stop before the tape comes free of the
reel on rewind, a leader should be used. Resetting the
counter at the starting point of the tape, a few feet from the
end of the leader, allows the ZERO output to be used to stop
th'e recorder on rewind, leaving the leader on the reel.

5. TAPE RECORDER POSITION INDICATOR/
CONTROLLER (Figure 10)
This circuit shows an application which uses the up/down
counting feature of the ICM7217 to keep track of tape
position. This circuit is representative of the many
applications of up/down counting in monitoring dimensional positio·n. For example, an ICM7227 as a peripheral to a
processor can monitor the position of a lathe bed or
digitizing head, transfer the data to the processor, drive
interrupts to the processor using the EQUAL or ZERO 'outputs, and serve as a numerical display for the processor ..

The 1Mll resistor and .0047 f.lF capacitor on the COUNT
INPUT provide a time constant of about 5ms to debouncethe
reel switch. The Schmitt trigger on the COUNT INPUT of the
ICM7217 squares up the signal before applying it to the
counter. This technique may be used to debounce switchclosure inputs in other applications.

In the tape recorder application, the LOAD REGISTER,
EQUAL and ZERO outputs are used to control the reco·rder.
To make the recorder stop at a particular point ·on the tape,

LOGIC TO GENERATE
RECORDER CONTROL
SIGNALS

COMMON-CATHODE
.
LED DISPLAY

)

REEL SWITCH'
CLOSED ONCEJREV

~~~~~====~~
4 DIGITS
RESET

Figure 10: Recorder Indicator

6·63

~

1.1

U~UIl.

ICM7217/7227
6. PRECISION FREQUENCY COUNTER/
TACHOMETER (Figure 11)

6.5536 MHz crystal I, giving a 0.01 second gating with Pin 11
connected to V+, and a 0.1 second gating with Pin 11 open.
To implement a four digit tachometer,the ICM7207A with
one second gating should be used. To get the display to read
directly in RPM, the rotational frequency of the object to be
measured must be multiplied by 60. This can be done electronically using a phase-locked loop, or mechanically. by
using a disc rotating with the object with the appropriate
number of holes drilled around its edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1
second gating, and multiply the rotational frequency by 600.

This circuit is a simple implementation of a four digit
frequency counter, using an ICM7207A to provide the one
second gating window and the STORE and RESET signals. In
this configuration, the display reads hertz directly. With Pin 11
of the ICM7027A connected to V+,the gating time will. be 0.1
second; this will display tens of hertz as the least significant
digit. For shorter gating times, an ICM7207 may be used (with a

--_+----~--------~---.--------~--------_+--V+=5V

22pF

10kn
BCD OUT

~-_.

5
6

ICM

5
6
T

• 7207A
CRYSTAL
t == 5.24288 MHZ'
Rs < 750

25-28

•

ICM
10

2•

7217·

COUNT 8

".

15-19
21,22

STORE

CD4001

RESET 14

20

"::"

INPUT

Figure 11: Precision Frequency Counter (-lMHz Maximum)

til
•

7. INEXPENSIVE FREQUENCY COUNTER/
TACHOMETER (Figure 12)

300-500J.Ls. The positive waveform time is given by twp = 0.693
IRA + RS-I C while the negative waveform is given bytwn =0.693
RBC. The system is calibrated by using a 5M!1 potentiometer
for RA as a "coarse" control and a 1k potentiometer for RB as a
"fine" control. CD40106S's are used as a monostable multivibrator arid reset time delay.

This circuit uses the low power ICM7555 (CMOS 5551 to generate the gating, STORE and RESET signals. To provide the
gating signal: the time.r is configured as an astable multivlbrator, using RA, Rs and C to provide an output that is positive for
approximately one second and negative for approximately

INVERTERS: C0401068
NANOS: CD40118

COUNT INPUT 0 - - - - - - - - - - - - - '

___-i1--300·'--tl:.==:;-:"~S~EC===.:.::::jl

....Jr--'

! - o '. . . , . . . -_ _

1-+50~S

S'fORE --~-iU

.

...-------__1, ___

,'-----'

------,U

~
,~,

,~.
r--~~------------~'~

L--.~""-----:---

'L-_----'r:--'

Figure 12: Inexpensive Frequency Counter
6·64

ICM7217/7227
v+ == 5V-r-~'-----:::;======+;:::;v+= sv

8. LCD DISPLAY INTERFACE (Figure 13)

The low-power operation of the ICM7217 makes an LCD
interface desirable. The IntersillCM7211 4 digit BCD to LCD
display driver easily interfaces to the ICM7217. Total system
power consumption is less than 5mW.

03 33
02 32
01 31
DB3

~~

002 28
DBl

4"'.""·.-_-V+...,2.
5 4'9
6 2'.

L.._ _...!D~B:::J0r2'_.7

- D.C. 23

1's

20

ICM7217
IJI
COUNT:

01 26

~~ ~~
~~~~~14L__-.JD~.¥2",-5_ _....J

STORE 10

Figure 13: LCD Display Interface
In the area of "intelligent" instrumentation, the ICM7227 can
serve as a high speed (up to 750kHz) counter/comparator.
This is the element .often used for converting time,
frequency, and positional and occurence data into digital
form. For example, an ICM7207A can be used with two
ICM7227's to provide an 8 digit, 2MHz frequency counter.
Since the ICM7207A gating output has a 50% duty cycle,
there is 1 second forthe processorto respond to an interrupt,
generated by the negative going edge of this signal while it
inhibits the count. The processor can respond to the
interrupt using ROM based subroutines, to store the data,
reset the counter, and read the data into main memory. To
add simultaneous period display, the processor inverts the
data and an ICM7218 Universal Display Driver stores and
displays it. Capacitance can be measured by counting the
frequency of an oscillator,' thereby allowing the measurement of fluid levels, proximity detectors, etc.
Future Application Notes,'and Bulletins will address the
ICM7227 more fully, and users are welcome to submit any
circuits or unique uses for review and possible publication in
application information.

9. MICROPROCESSOR INTERFACE-ICM7227
(Figure 14)
This circuit shows the hardware necessary to interface the
ICM7227 to an IntersillM6100 CMOS microprocessor. Using
an IM6101 Parallel Interface Element (PIE) allows the
addition of one or more ICM7227 devices as generalized
peripherals to any IM6100 system, using a minimum of
external components.
A similar configuration may be used with the MC6800 using
the corresponding PIE, while an 8223 can be used to
interface 8080 based systems.
The ICM7227 can perform many "accessory" functions that
are inefficient or impossible forthe processor to perform. For
simple systems, the ICM7227 can provide a cost-effective
display latch/decoder/driver. By adding a timebase such' as
an ICM7213, and using an ICM7227C or 0, an inexpensive
real-time clock/display, directly accessible by the processor,
can be constructed.

rD~
/

DXO-11

/12

LXMAR
DEVSEL

INTGNT
IM6100
MP

v+

XTC

~<

\
C1
C2
SKP
INTREQ

.

~

1-1
12
a:..JI-U
ctWZI::::i:

ALE ~ PRDG WR

r'

I"

125

1'.

RD

18

Wli
.

8

1
Figure 6: 8 Digit Microprocessor Display

6·74

ICM7218 SERIES
16 DIGIT MICROPROCESSOR DISPLAY
APPLICATION
Both ICM7218's are addressed simultaneously with a 3 bit
word, DA2-DAO.
.
.

Decimal point information (from the processor, P26-P27) is
supplied to the .1CM7218 on bus lines ID7 to both devices.

Display data from the MCS-48 1/0 bus (DB7-DBO) is
transferred to both ICM7218 (ID3-IDO) sim).Jltaneously,
4 bits + 4 bits on WRITE enable.

Choice of decoding is available in either Hexadecimal or
Code-B format by hardwiring or decoding to a Three Level
format on Pin 9 of the ICM7218.

Display digits from both ICM7218's are interleaved to allow
adjacent pairs of digits to be loaded sequentially on a single 8
bit data bus, ie DO D1, D2 D3, D4 D5, etc ..

Multiplexing is asynchronous with respect to the microprocessor and is completely performed by the ICM7218;

, , '-' , , , , , ,, , ,, '-' '-' '-'
L' '-' '-' '-'
'-'. '-'. L'. '-'. '-'. , '. L'. , '. '-'. '-'. '-'. '-'. L'. '-'. '-1'.
I

8

,~,

/ I.

016

DIS

01.

013

012

010

011

GND!:

a

VDD

II

Vss

•

XTAL1

-=

f-l

D.

03

02

01

v-I

v+,.

8

DIGITS

[#:

I.

8

28

SEGMENTS

f-'--

DIGITS

I----

SEGMENTS

r--f----

p!-

P2D
P21
P22
P23
P2'
P2S
P2.
P27

RESET

EA

NC---l55

INPUT

OS

Vss

~

8048 •
7

06

28

VDD

t-¥.t-¥!--

PID
Pl1
P12 ~
30
P13
PI.
PIS 32
P16
P17

...ILI.3 XTAL2
II

II

07

ONDI:

+5v 11I.

2

II

08

8

+S~hrl
,402620
Vee

DO

21
22
23

~
3S

~
37
38

12
DBD
13
OBI
14
082
IS
DB3
16
DB.

TO

2! Tl

DBS
DB.
DB7

:-! iNT
ALE PSEN PROG WR

1"

I~

125

\,0

~
10

DAD

ICM7218C/D

~~

7

7 107 (DEC. PT.).

~D7

ICM7218C/D

(DEC: PT.)

12
11 100
101
102
~
---1i 19 3

~~

100
13 101
14

S
6 DAD
10 DAI
DA2

:g~

"

~

rl}~

v+~ :THREE

v+---1.

L'EVEl

Viii

RO

1~

r

THREE

LEVEL

-

WR
8

Figure 7: 16 Digit Display

NO DECODE APPLICATION
The ICM7218 can be used as a microprocessor based LED
status panel driver. The microprocessor selected controlword would include "No Decode" and "Data Coming". The
computer then outputs word oriented "Ones" and "Zeroes"
to indicate on-off states. This data is read into the ICM7218
which in turn directly drives appropriate discrete LEDs. LED
indicators can be red or green (8 "segments" x, 8 digits = 64
dots + 2 per red or green = 32 channels). With red, yellow and
green, 21 channels can be accommodated.
6-75

Additional ICM7218's may be bussed and addressed (see
Figures 6 and 7) to expand the status panel capacity. Note per
figure 4 that after the ICM7218A/B has beEln read in its data (8
WRITE pulses),.it ignores additional information on the data
lines. A new control word must be received before the next
write sequence can be accommodated. Consequently, by
address decoding and WRITE pulse enabling, numerous
ICM7218's can be bussed together to allow a large number of
indicator channels.

U~UIL

ICM7224 (LCD)
ICM7225' (LED)
4112 Digit Count.r/
Decoder/Drivers ,
GENERAL DESCRIPTION

FEATURES

The ICM7224 and ICM7225 devices constitute a family of
high-performance CMOS 4 1/2-digit counters, including
decoders, output latches, display drivers, count inhibit,
leading zero blanking, and reset circuitry.
The counter section provides direct static counting, guaranteed from DC to 15 MHz, using a 5V ±10% supply over the
operating temperature range. At normal ambient temperatures, the devices will typically count up' to 25 MHz. The
count input is provided with a Schmitt trigger to allow
operation In noisy environments and correct counting with
slowly changing inputs. These devices also provide count
inhibit, store and reset circuitry, which allow a direct interface with the ICM7207/A to implement a low cost, low power
frequency counter with a minimum component count.
These devices also incorporate several features int~nded to
simplify cascading four-digit blocks. The carry output allows
the counter to be cascaded, while the leading zero blanking
input and output allows correct leading zero blanking
between four-decade blocks. The backplane driver of the
LCD devices may be disabled, allowing the segments to be'
, slaved to another backplane signal, necessary when using .
an eight or twelve digit, single backplane display. In LED
systems, the brightness input to several ICM7225 devices
may be ganged to one potentiometer.
The ICM7224/1CM7225 family are packaged in a standard,
40-pin dual-in-line plastic package.

• High frequency counting - guaranteed 15MHz,
typically 25MHz at 5V
.,
• Low power operation - less than 100~W quiescent
• Store and Reset Inputs permit operation as
frequency or period counter
• True count inhibit disables first counter stage
,. Carry output for cascading four-digit blocks
• Schmitt-trigger on the count Input allows operation
in noisy environments or with sloWly changing
Inputs
.~
.
• Leading zero blanking Input and output for correct
leading zero blanking with cascaded devices
• LCD devices provide complete onboard oscillator
and divider chain to generate backplane frequency,
pr backplane driver may be disabled allowing
,
segments to be slaved to a master backplane signal
, • LED devices provide Brightness input which can
function digitally as a display enable or with a single
potentiometer as a continuous display brightness
control

Dl
•

r-----~---r---....;...,-.----.

TYPICAL APPLICATION (UNIT COU,NTER) -

PIN CONFIGURATION
(OUTliNE DRAWING PL)

COUNT 32

COUNT IN

COUNT INHIBIT 31 J---~PO;;AUc;;;S-:;-E~
LZO 30
(CLOSED)

LZI 29...-__ --""'LZ=B~
CARRY 28
. INHIBIT
(CLOSED)

--I::~;

'--=2.-=S=EG""M"'EN""T""S

L-_--'-'lH.=.A=LF-=-D:.;,:'G::.'T:"""-I37!40

(CM7225

ORDERING INFORMATION

LCD
DISPLAY
LED
DISPLAY

ORDER PART NUMBER
ICM72241PL
ICM7224A .IPL
ICM72251PL
ICM7225A IPL

COUNT OPTION
19999
15959 .
19999
·15959

6-76

ICM7224/ICM7225
ABSOLUTE. MAXIMUM RATINGS
Power Dissipation (Note 1) ........................................ 0.5 W@ 70°C
Supply Voltage (V+) ..•..•.• '. • . • • . • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • . . . •. 6.5V
Input Voltage (Any
(
Terminail (Note 2) ............................................... V+ +0.3V, -D.3V
Operating Temperature Range .................................... -20° C to +85° C
Storage Temperature Range ........................... ; ......... -55° C to. +125° C
Stresses abave thase listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress riltings only, and functional aperatian of the device at these or any
ather conditions above those indicated in the operational sections of the specifications is not
. implied. Exposure to absolute maximum rating conditians for extended periods may affect device
reliability.
'
NOTE 1: This limit refers' to that of the package and will not be abtained during normal operation.
NOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any terminal to
voltages greater than V+ or less than GROUND may cause destru'ctive device latch up.
For this reason, it is recommended that no inputs from sources operating on a different
power supply be applied to the device before its supply is established, and that in
multiple supply systems, the 'supply to the ICM7224/1CM7225 be turned on first.
OPERATIN~CHARACTERISTICS' TABLE 2
(All Parameters measured with V+ = 5V 'unless otherwise indicated)

ICM7224 CHARACTERISTICS
PARAMETER
Operating current
Operating supply voltage rarige
Oscillator input current
Segment rise/fall time .'
Backplane rise/fall time
Oscillator frequency
Backplane frequency

SYMBOL. CONDITIONS
Test circuit, Display blank
lop'
V+
losci
trls
trfb
fose
fbp

Pin 36
Cload - 200pF
Cload - 5000pF
Pin 36 Floating
Pin~ 36 Floating

MIN· .TYP
10
3
5
±2
0.5
1.5
.16
125

MAX
50
6
±10

MIN

TYP
10

MAX
, 50

UNITS
p.A

"

5
200
±0.01
8
16

6

V
rnA
p.A

UNITS
JJ.A
V
JJ.A
p's
KHz
Hz

ICM7225 CHARACTERISTICS
PARAMETER
Operating current display aff

SYMBOL
lopo

CONDITIONS
Pin 5 (Brightness) at GROUND
Pins 29 31-34 at V+

V+

Operating supply voltage range
Operating current

lop

Pin 5 at V+, Display 18888

Segment leakag.e current
Segment on current
Half digit on. current

ISLK
ISEG
IH

Segment Off
Segment On, Vout = + 3V
Half digit pn, Vout. = + 3V

5
10

±1

mA

FAMILY CHARACTERISTICS
PARAMETER
Input
Pullup Currents
Input High Voltage
. Input Low Voltage
Count Input Threshold
Count Input Hysteresis
Output High'
Current
Output Low
Current

SYMBOL
Ip
VIH
VIL
VCT
VCH
IOH

IOL

Caunt Frequency

fcount

Store, Reset Minimum Pulse Width

tS,tA

CONDITIONS
Pins 29, 31, 33, 34
Vout = V+- 3V
Pins 29, 31, 33, 34
Pins 29, 31, 33, 34

-

MIN

TYP
10

MAX

3
1

2.
Carry Pin 28
Leading Zero Out Pin 30
vout = V+ -3V
Carry Pin 28
Leading Zero Out Pin ·30
Vout = +3V
4.5V < V+ < 6V

350

,0.5
500

350

500

0

DC-25

3

6·77

UNITS
p.A

V

p.A

15

MHz
p's

"

ICM7224/ICM7225
TYPICAL CHARACTERISTICS
7225 LED SEGMENT CURRENT
AS A FUNCTION OF OUTPUT VOLTAGE

7224 OPERATING SUPPLY CURRENT
AS A FUNCTION OF SUPPLY VOLTAGE

15

30

. L~~~~ICES. TEST CIRCUIT

PIN 36 O~EN

~

I

ITA" 1-2O

W

~

15

o

TA=25°C~

~

/

8: 10

/. ~

:::I

In

~

W

II:
II:

I

:::I

o

-h

!2
~

5

-- :

12

~~

,

I

I

I

I

I

I II

1~I~Ld_~E~
5

BP
ICM7224
LOW ORDER DIGITS
MASTER BACKPLANE

co

LZllZQ CEC,NTRs iTGNDOSC
27 28 2930 31 32 3334 35 36'

21

I II

I I, III

III

1.\1

,

F-::t

9rHDI-<..-- 6
Be:~,
-7
COUT = C'N , ICM7207A

40

IIII~

~~Jf,,~ CZLE~~~[~~~~g 'f
10k!!

I

SEGMENTS 15

20 '

ICM7224

21

II

I

BACKPLANE,

' SEGMENTS

BP

CD LZI LZQ

r{'

6

4
SEGMENTS

SEGMENTS

4 SEGMENTS

I

.

-::b-

1"-.
'.

_~WITCH -OPEN 1 SEC GATING

1/4 CD4069C

SWITCH CLOSED 0.1 SEC GATING

CRYSTAL- CIN

J
40

I

22pF
INPUT
SIGNAL
CONDITIONING
(PRESCALER

COUT:: 22pF

10 ::: 5.24258 MHz
Rs' < 75n
Cs ::: O.015pF .
Cp = 3.5pF

LEVEL SHIFTING)

"

6-82

f--,--SIGNALINPUT

II

ICM7226A/B

10MHz Universal Counter System
ICM7226A Drives Common
Anode LED's
ICM7226B Drives Common
Cathode ,LED's
FEATURES'

GENERAL DESCRIPTION

• CMOS design for very low power
• Output drivers directly drive both digits and
segments of large 8 digit LED displays. Both
common anode and common cathode versions are
available
• Measures frequencies from DC to 10 MHz; periods
from 0.5J,Ls to 10s
,. Stable high frequency oscillator uses either 1MHz or
10MHz crystal
• Control signals available for gating of prescalers
and prescaier display logic
• Multiplexed BCD outputs

The ICM7226 is a fully integrated Universal Counter and LED
display driver. It combines a high frequency oscillator, a
decade timebase counter, an 8 decade data counter and
latches, a 7 segment decoder, digit mUltiplexer, and segment
and digit drivers which can directly drive large LED displays.
The counter inputs accept a maximum frequency of 10MHz
in FREQUENCY and UNIT COUNTER modes and 2MHz in
the other modes. Both inputs are digital inputs. In many
applications, amplification and level shifting will be required
to obtain proper digital signals for these inputs.
The ICM7226 can function as a frequency counter, period
counter, frequency ratio (fA/fs) counter, time interval couriter
or a totalizing counter, The devices requireeithera 10MHz or
lMHz crystal timebase, or if desired an external timebase
can also be used. For PERIOD and TIME INTERVAL, the
10MHz timebase gives a O:ll'sec resolution. In PERIOD
AVERAGE and TIME INTERVAL AVERAGE, the resolution
can be in the nanosecond range. In the FREQUENCY mode,
the user can select accumulation time of 10ms, lOOms, ls
and lOs, With a lOs accumulation time, the frequency can be
displayed to a resolution of 0.1 Hz. There is a 0.2s interval
between measurements in all ranges. Control signals are
provided to enable gating and storing of prescalerdata.

APPLICATIONS
•
•
•
•
•

Frequency Counter
Period Counter
Unit Counter
Frequency Ratio Counter
Time Interval Counter

Leading zero blanking has been incorporatea with
frequency display in kHz and time in I'S. The display is
multiplexed at a 500Hz rate with a 12,5% duty cycle for each
digit. The ICM7226A is designed for common anode display
with typical peak segment currents of 25m A, and 'the
ICM7226B is designed for common cathode displays with
typical segment currents of 12mA. In the DISPLAY OFF
mode, both digit drivers & segment drivers are turned off,
allowing the display to be used for other functions.

PIN CONFIGURATION
CONTROL IN
BIN
MEAS IN PROGRESS
FUNCTION.
STORE
BCD 4
BCD 8 7

CONTROL IN ' •
BIN ,2
MEAS IN PROGRESS I J
FUNCTION :'
STORE 5

01 8
03 9
02 '"
04 11
GROUND ,,05 --13
06 "
07 15
25 Vi08 16
2<, 06
BCD 2 ~17
" 07
BCD 1 18
2208
RST IN 19
2~ RANGE
EX DP IN 20
"'-----'
.FOR MAXIMUM FREQUENCY
- " _ _';""....r
(OUTLINE DRAWING DL)

STABILITY, CONNECT TO V· OR GROUND

A IN
HOLD
BUFF OSC OUT
NC*
J6 OSC OUT
J5 OSC IN
34 NC*
OJ EXT OST IN
J2 RST OUT
J1 EXT RANG
JO DP OUT
29 SEG 9
261 SEG e
27' SEG a
26 SEG d
40

J9
J8
37

(OUTLINE DRAWING PL)

ORDERING INFORMATION
DISPLAY

DEVICE

Common Anode

ICM7226A

Common Cathode ICM7226B

PACKAGE ORDER NUMBER
ICM7226A IDL
Ceramic
Plastic

NOTE: An evaluation kit is available for these devices -

6·83

ICM7226B IPL
order ICM7226/1EV/KIT,

m
•

ICM7226A/B
ABSOLUTE MAXIMUM. RATINGS
Maximum Supply Voltage •.•••..••...•.......••.•..••••.....•.••.•.••••... 6.5V
Maximum Digit Output Current •.•.•.•••.•••..•.....•.••.•.•••• '. • . • • • • •. 400mA
Maximum Segment Output Current ....................................... 60mA
-Voltage on any Input or Output Terminal ....•.•..•...••. Not to exceed V+ or GND
.
by more than +0.3 volts
Maximum Power Dissipation at .••.•.•...••..................•. 1.0W (lCM7226A)
70°C (Note 1) ............................................. ~. 0.5W (lCM7226B)
Maximum Operating Temperature Range .. : •.................... -20°C to +85°C
Maximum Storage Temperature Range .......................... ~55°C to +125°C
Lead Temperature (soldering. 10 seconds) ................................ 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only. and functional' operation of the device at these or any
other conditions above those indicated In the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
'
. -NOTE: Destructive latchup may occur if input signals are applied before the power supply is
established or if inputs or outputs are forced to voltages exceeding V' or ground by O.3V.

ELECTRICAL CHARAC'FERISTICS
TEST CONDITIONS: V'= 5.0V. Test Circuit. TA= 25°C. unless otherwise specified.
PARAMETER
Operating Supply
Current
Supply Voltage Range

Maximum Guaranteed
Frequency
Input A. Pin 40

Maximum Frequency
Input B. Pin 2

SYMBOL CONDITION
Display Off
lop
Unused inputs to GROUND
, Vsupp
-20°C < TA < 85°C
Input A. Input B
Frequency at fMAX
fA(max)

fS(max)
I

Minimum Separation
Input A to Input B
Time Interval Function
Maximum osc. freq. and ext. osc.
freq. (minimum ext. osc. freq')

fose

Oscillator Transconductance

gm

Multiplex Frequency
Time Between Measurements

fmux

Minimum Input Rate of Charge

dVin/dt

-20°C < TA < 85°C
4.75V< V+ < 6.0V Figure 1
Function = Frequency.
Ratio. Unit Counter
Function = Period. Time Interval
-20°C < TA < 85°C
4.75V < V+ < 6.0V
Figure 2
-20°C < TA < 85°C
4.75V < V+ < 6.0V
Figure 3
-20°C-< TA < 85°C·
4.75V < V+ < 6.0V

Inputs A. B

6-84

TYP

MAX

UNITS

2

5

mA

6.0

V

4.75

10
2.5

14

MHz

2.5

250

ns

,

(0.1)

10

MHz
j.ts

500
200

Hz
ms

2000

V+ = 4.75V
TA = +85°C
lose = 10 MHz
fose - 10 MHz

MIN

I

25

15

mV/JJs

n~nll

ICM7226A/B
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: V+ = 5.0V, test circuit, TA = 25°C, unless otherwise specified.
PARAMETER
SYMBOL CONDITION
INPUT VOLTAGES
PINS 2,19,33,39,40
-20°C < TA < +70°C
input low voltage
VIL
input high voltage
VIH
hLK
, PIN 2, 39, 40 INPUT LEAKAGE, A, B
PIN 33
-20°C < TA < 70°C
input low voltage
VIL
input high voltage
VIH
Input resistance to V+
VIN = V+ -1.0V.
PINS 19,33
RIN
Input resistanct) to GROUND
PIN 31
VIN=+1.0V
RIN
Output .Current
PINS 3,5,6,7,17,18,32,38
VOL=+O.4V
IOL
PINS 5,6,7,17,18,32
IOH
VOH-+O.4V
PINS'3,38
I()H
VOH - V+ -o.8V

MIN

TYP

MAX

1.0

V
3.5
20

-

UNITS

0.8

~A

V
2.0

100

400

50

100

kO

p.A

400
100
265

p.A

ICM7226A
PINS 22,23,24,26,27,28,29,30
DIGIT DRIVER
high output current
low output current
SEGMENT DRIVER
PINS 8,9,10,11,13,14,15,16
low output current·
high output current
MULTIPLEX INPUTS
PINS 1,4,20,21
input low voltage
input high voltage
input resistance to GROUND

IOH
IOL

Vo = V+-2.0V
Vo - +1.0V

150

180
-0.3

mA

JOl

Vo = +1.5V
Vo - V+ :"1.0V

25

35
100

mA
p.A

IOH

0.8

VIL
VIH
RIN

VIN =+1.0V

IOL
IOH

Vo = +1.0V
Vo - V+ 2.5V

IOH
IL

Vo = V+-2.0V
VO- GROUND

2.0
50

V

100

kO

50

75
100

mA
p.A

10

15

ICM7226B
DIGIT DRIVER
PINS 8,9,10,11,13,14,15,16
low output current
high output current
SEGMENT DRIVER
PINS 22,23,24,26,27,28,29,30
high output current
leakage current
MULTIPLEX INPUTS
PINS 1,4,20,21
'input low voltage
input high voltage
input resistance to V·

VIL
VIH
RIN

10

V+ -2.0
VIN - V' -1.0V

V -0.8
200

360

mA
p.A

V
k!l

EVALUATION KIT
An evaluation kit is available for the ICM7226, It includes a" the components necessary to assemble and evaluate a
universal frequency/period counter based on the ICM7226. With the help of this kit. an engineer or technician can
have the ICM7226 "up-and-running" in less than an hour. Specifically. the kit contains an ICM7226AIDL. a 10MHz
quartz crystal. eight each 7-segment .3" leds. PC board. resistors. capacitors. diodes. switches and IC socket.
Order # ICM7226i\EV/KIT.

6·85

Il•

ICM7226A/B
TIME INTERVAL MEASUREMENT

This can easily be accomplished with the following circuit,
Figure3b:

The ICM7226 can be used to accurately measure the time
interval between two events. With a 10MHz timebase crystal,
the time between the two events can be as long as ten
seconds. Accurate resolution in time interval measurement
is 100ns.

SIGNAL A

SIGNAL 8

The feature operates with Channel A going low at the start of
the event to be measured, followed by Channel B going low
at, the end of the event.

'NPUT A:"::

50

w:",:

v'

r.

N.D.

v'

~ IpR'MEI

150K

0" "10n'ec
lN914

100K

Figure 1: Waveform for Guaranteed Minimum FAMAX Function =
Frequency Ratio, Unit Counter.

,Fr~quency,

=J_

250n,

INPUT A

OR
INPUT B

4.SV - - - -.....~

.

O.SV

Type

={

CD40498 Inverting Buffer
CD4070B Exclusive-OR

-

Figure 3b: Priming Circuit, Signal A & B High orLow

d

___ 250 ns

Ir = If '" 10ns

Figure 2: Waveform for Guaranteed Minimum fBMAX and fAMAX for
Function = Period and Time Interval.

Following the priming procedure (when in single event or 1
cycle range input) the device is ready to measure one (only)
event.

When in the time interval mode and measuring a single event,
the ICM7226 must first be "primed" prior to measuring the
event of interest. This is done by first generating a negative
going edge on Channel A, followed by a negative going edge
on Channel B to start the measurement interval. The inputs
are then primed ready for the measurement. Positive going
edges on A and B, before or after the priming, will be needed
to restore the original condition.

When timing repetitive Signals, it is not necessary to "prime"
the ICM7226, as it is done automatically the first time the
input signal changes states:
During any time interval measurement cycle, the ICM7226
requires 200ms following B going low to update the internal
logic. A new measurement cycle will not take place until
completion of this internal update time.

•

STORE

--+-i
FUNCTION:
TIME INTERVAL

30 TO 40ms

L _I

40ms

~
~ 19~~g~~~ms--~-I---PAIM.ING --_-+-_____ MEASUR~MENT INTERVAL ---'-----.,I-UPDATE-

I

MEASUREMENT
IN PROGRESS

INPUT A

INPUTS
2500s MIN.
MEASURED
INTERVAL
(FIRST)

NOTE: IF RANGE IS SET TO l·EVENT, FIRST AND L'AST MEASURED INT'ERVAl WILL COINCIDE.

Figure 3a: Waveforms in Time Interval Mode.

6·86

I
---l

I--

MEASURED

INTERVAL
{LA<:T\

ICM7226A/B

r- DECODE~I-.....,8'f---t O~:~~:S 1-------------------....:;<>1:......,0 g~G~~UTS (8)

EXT

asc

INPUT

asc INPUT
asc OUTPUT

o-------i

~~S~~~CT
~
"--

In

B~~~E~C~

r--

-

I

1
60
r ..

_.--J

HZ

COUNTER

I

EXT

--t-+--+-'
"----t_+__1-__1~+---,~-::---+--i-

~-r--_-_-_-_-_-_-_-_-_-_-_--l--l-_-_-_

6

T

r-INPUT

'-Hf----+-j--t---t-H---t---''f----''-/

.~

---lEN

MAIN

L.

AESE~I

INPUT A o_--.-HCONTROl ~-III1I1----_r-tJC~l~~C,~O!..U,N;TrER._._O,FJI-t--+--+--1-~

O--rHH

RANGE INPUT

L~ ::L~~~ L ~
RESET LOGIC r-nL..lL,202G!.5IC:....III-====-----O RANGE INPUT
STORE &

~INPUTo_--r_r_-----+_+_--------~

INPUT B

C~~:~~ll--_ _-O
,--

.,.104 OR -;-10 5

,----------~~--.-----~

L-

RANGE

r"------------+tl REF~~O~NCE

1'1' l' I' 1'1'1'1'

LOGIC

CONTROL

LOGIC

CONTROL

1-----0

INPUT

D.P.
EXT. D.P.

lOGIC I-----------~ INPUT

-

r-.

,

-

DECODER
& lZB
LOGIC

,----!,- __

~

SEG

DRIVERS

8 L-O
1_--'7

SEGMENT
OUTPUTS (S)

. FN

FUN~:~~~o-------~C~::~~LI-~--r-_----r----r-------------------1----1-~

~6

4

'--'---------c,t-~

4

>---"f--o

'-________~t-...">------o

BCD
OUTPUTS (4)

RESET
OUTPUT

MEAS IN
PAOG 0------ ~-~
~
OUTPUT
---- - _ _ _ _ _ _+_---1

' -_ _ _ _ _ _ _ _ _ ~

STO~
~OUTPUT

HOLD INPUT O>------~---------Figure 4: Block Diagram

CONTROL INPUT

y+

eo

S.OV

DIODES: IN914

10kJl

STORE OUTPUT
BCD C OUTPUT
BCD 0 OUTPUT
dp

8

ICM7226A

CRYSTAL SPECS. =
Fa 10.00 MHz
Co 22pF
Rs·
3511

"

33

"

"

f
,

6: DENOTES
,
BUS WITH
6 CONDUCTORS

"

LED OVERFLOW INDICATOR CONNECTIONS;
OVERFLOW WILL BE INDICATED ON THE
DECIMAL POINT OUTPUT OF DIGIT 7

24

ICM7226A
ICM7226B

LED OVERFLOW
INDICATOR-

Figure 5: Test Circuit

6·87

d.p.

0,

0,

d.p.

ICM7226A/B
Display Off - To enable the DisplayOff mode it is necessary
to tie 04 to the controlinput and have the HOLD input at V+.
The chip will remain in the Display Off mode until HOLD is
switched low. While in the Display Off mode, the segment
and digit driver outputs are open. During Display Off, the
oscillator continues to run, with a typical supply current of
1.5mA with a 10MHz crystal, and no measurements are
made. In addition, signals applied to the multiplexed inputs
have no ·effect. A new measurement is initiated when the
HOLD input goes low.

APPLICATION NOTES
GENERAL
INPUTS A & B
The signal to be measured is applied to Input A in Frequency,
Period, Unit Counter, Frequency Ratio and Time Interval
modes. The other input signal to be measured is applied to
Input B in Frequency Ratio and Time Interval. fA should be
higher than Is during Frequency Ratio.
Both inputs are digital inputs with a typical' switching
,threshold of 2.0V at V+ =5.0V. Foroptimum performance, the
peak to peak input signal should be at leas~ 50% of the supply
voltage and centered about the switching voltage. When
these inputs afebeing driven from TTL logic, it is desirable to
use a pullup resistor. The circuit counts high to low transitions at both inputs.
Note: The amplitude of the input should not exceed the s~pply by
more than 0.3V otherwise, the circuit may be damaged.
.

1 MHz Select - The 1MHz select mode allows use of a 1MHz

crystal with the same digit multiplex rate and time between
measurements as a 10MHz crystal. The internal decimal
point is also shifted one digit to the right in Period and Time
Interval, since the least significant digit will be in 11'.5 increments rather than 0.1I's.
External Oscillator Enable - in this mode, the external
oscillator input is used, rather than the on chip oscillator, for
the Timebase and Main Counter inputs in Period and Time
interval modes.' The on chip oscillator will continue to
function when the external oscillator is selected, but have no
effect on circuit operation: The external oscillator input
frequency must be greater than 100kHz or the chip v~till reset
itself and enable the on chip oscillator. Connect external
oscillator to both OSC IN (pin 35) and EXT OSC IN (pin 331.

MULTIPLEXED INPUTS
The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the
appropriate digit driver output to the inputs. The iriput
function, range and control inputs must be. stable during the
last half of each digit output, ,(typically 125}lsec). The
multiplex inputs are active high for the. common anode
ICM7226A, and active low for. the common cathode
ICM7226B.

Ii]
•

External Decimal Point Enable - When external decimal
point is enabled, a decimal pOint will be displayed whenever
the digit driver connected to the external decimal point is
active. Leading Zero Blanking will be disabled for all digits
following the decimal pOint.

Noise on the multiplex inputs can cause improper operation.
This is particularly true' when the unit counter mode of
operation is selected, since changes in voltage on the digit
drivers can be capacitively coupled through the LED diodes
to the multiplex inputs. For maximum noise immunity, a 10k
resistor should be placed in series with the multiplex inputs
as shown in the application notes,
Table 1 shows the functions selected by each digit for these
inputs.
TABLE 1
FUNCTION INPUT
PIN 4

RANGE INPUT
PIN 21

PIN 31
CONTROL INPUT
PJN 1

EXTERNAL DECIMAL
POINT INPUT. PIN 20

Test Mode - This is a special mode used only in high speed
production testing, and serves no other purpose.

RANGE INPUT
The range (nput selects whether the measurement is made
for 1,10,100, or 1000 counts of the reference counter, or if the
external range input determines the measurement time. In all
functional modes except Unit Counter, achange in the range
input will stop the measurement in progress, without updating the display, and initiate a new measurement. This prevents an erroneous first reading after the Range Input is
changed.

FUNCTION
DIGIT
D,
Frequency
Period
DB
Frequency Ratio
D2
Time Interval
D5
Unit Counter
D4
Oscillator Frequency
D3
,01 Sec/1 Cycle
D,
.1 Sec/10 Cycles
D2
1 Sec/100 Cycles
D3
10 Sec/1 k Cycles
D4
Enable External Range
D5
Input
Blank Display
D4&Hold
Display Test
DB
1MHz Select
D2
External Osciilator Enable
D,
External Decimal Point
Enable
D3
Test
D5
Decimal Point is Output for Same Digit
That is Connected to This Input

FUNCTION INPUT
Six functions can be selected. They are: Frequency, Period,
Time Interval, Unit Counter, Frequency--Ratio and Oscillator
Frequency:
These functions select which signal iscounted into the main
counter and which Signal is counted by the reference
counter, as shown in Table 2. In Time Interval, a flip flop is
set first by a 1-+0,transition at INPUT A and then reset bya 1-+0
transition at INPUT B. The oscillator is gated into the Main
Counter during thetime the flip flop is set. A change in the
FUNCTION input will stop the measurement in progress
without updating the display and then initiate a new
measurement. This prevents an erroneous first reading after
the FUNCTION Input is changed. If the main counter
overflows, an overflow indication is output on the decimal
output during 08.
'

CONTROL INPUTS
Display Test - All segments are enabled continuously, giving
a display of all 8's with decimal points, The display will be
blanked if Display Off is selected at the same time.
6-88

ICM7226A/B
TABLE 2
DESCRiPTION .
Frequency (fA)

MAIN COUNTER
Inpul-A

Period (IA)
Ratill (fAlfe)
Time Interval (A-B)
Unit Counter(Count A
Osc. Freq. (fosc)

Oscillator
Input A
Osc ON Gate
Input A
Oscillator

REFERENCE
COUNTER
100Hz (Oscillator +
lOS or 1()4)
l~utA

Input B
Osc OFF Gate
Not Applicable
100Hz (Osc : 105 or
1()4)

EXTERNAL DECIMAL P~INT INPUT
When the EXTernal Decimal Point is selected, this input is
active. Any of the digits, except Os, can be connected tothis
pOint. Dashould not be used since it will override the overflow
output and leading zeros will remain unblanked after the
, d~cimal point.
HOLD Input ,- Except in the unit counter mode, when the
HOLD Input is at V+, any measurement in progress is
stopped. the main counter is reset and the chIp is held ready
to initiate a new measurement. The latches which hold the
main counter data are not updated, so th(!! last complete
',measurement is displayed. In unit counter mode when
HOLD I nput is atV+, the counter is not stopped or reset, butthe
display is frozen at that in'stantaneous value. When HOLD
goes low the count continues from the new value in the
counter.
RESET Input - The RESET Input also enables the main
counter latches, res!Jlting in an all 'zero output.
EXTernai RAN~E ,,'Iput - The EXTernal RAN.GE Input is used
to select other ranges than those provided on the chip.
Figure 4 shows the relation!!hip between MEASurement IN
PROGRESS and EXTernal RANGE Input.
REFERENCE
COUNTER
CLOCK

EXT RANGE

INPUT

Figure 4: External Range Input to End of Measurement in Progress.
MEASUREMENT IN PROGRESS. STORE AND R~SET OU,tputs - These outputs are provided to enable display of '
prescaler digits. Figure S .shows the relationship between
these signals during the time between measurements. All
,three outputs can drive a low power Schottky TTL load. The
MEASUREMENT IN PROGRESS Output can directly drive
one ECL load, if the ECL device is powered from tlie same
power supply as the ICM7226.

1_-·
1

f1.E::Mat~:~T

STORE '
iiESffijij'j'

p

190 to 200m,

1.....____

U
I

~60ms
,

of

TABLE 3 Truth Table ,BCD Outputs
NUMBER
0
1
2
3
4
5
6

7
B
9

BCDS
PINT
0
0
0
0
0
0,
0
0
1
1

BCD 4
PIN,6
0
0
0
0
1
1
1
1

BCD 2
PIN 17
0
0
1

.

BCD,1
PIN 1'&
0
1
0

1

1

0
0

0
1
0
1

0

1
1
0

0

0

0

'1

BUFFered OSCillator OUTput - The BUFFered OSCillator
OUTput has been' provided to enable use of the on chip
oscillator signal without loading the, oscillator itself. This
output will drive one. low ,power Schottky TTL load. Care
should be taken to minimize capacitive loading on this pin.

DISPLAY CONSIDERATIONS

a.

The display is multiplexed at a SOOHz rate. with digit time of
244~s, and an interdigit blanking time of 6~s, to pr~vent
ghosting between digits. The dec,imal point and leading zero
blanking have been implemented for right hand decimal
point displays; zeros following the decimal point will not be
blanked. Leading zero blanking will also be disabled if the,
Main Counter overflows. The internal decimal point control
displays frequlilncy in kHz and time in ).ls.
The ICM7226A is designed to drive common anode LED
displays at a peak current of 25mA/segment, using displays
with VF = 1.SV at 2SmA. The average DC current will be
greater than 3mA urider these conditions. The ICM7226B.is '
designed to drive common cathode displays at a peak current
of 1SmA/segment, using displays with VF = 1.BV at 1SmA.
Resistors can be added in series with the segment drivers to
limit the display current, if required. Figures 6, 7, Band 9
show the digit and segment currents as Ii function of output
voltage for common anode and common cathode drivers.

300,..---,...---,-'"'7.1"'1

------:-1

l--+40m. ,

3~to4Om.

going (lCM7226B - Common Cathode) digit drivers lag the
BCD data by 2 to 6 microseconds; the leading edge the
digit drive Signal is used to externally latch the BCD data.
Each BCD output will drive one low power Schottky TTL load
and when interfacing low power Schottky TTL latches, it is
necessary to use 1kn pull down resistors on the TTL inputs
for optimum results. The display is multiplexed from MSD to
LSD. Leading zero blanking has no effect on the BCD
outputs.

200

I---t-----H~--j

100

1------1-ffl'-t----;

U .....,..----~40m.

Figure 5: RES€T OUT. STORE, and MEASUREMENT IN
PROGRESS Outputs Between Measurements.
BCD 0lltputs - The BCD representation of each digit output
is available at the BCD outputs; see Table 3 for Truth Table.
The positive going (lCM7226A - Common Anode) or negative
,
~9

1
2
V, - Vo (VO~TS)

Figure 6: ICM7226A Typical IDIG vs. V+-Vo
4.5 :5 V+ :5 6.0V

I
•

ICM7226A/B
8or-----,-----~~~0'~C~,,~

V· = 5.5Y

In addition, there is a quantization error inherent in any
digital measurement of ±1 count. Clearly this error is
reduced, by displaying more digits. In the Frequency Mode,
maximum accuracy is obtained with high frequency inputs,
and in Period Mode maximum accuracy is obtained with low
frequency inputs. As can be seen in 'Figure 10, the least
accuracy will be obtained at 10kHz. In Time Interval
measurements there is a maximum error of 1 count per
interval. As a result there is the same inherent accuracy in all
ranges, as shown in Figure 11. in Frequency Ratio
measurement more accuracy can be obtained by averaging
over more cycles of Input B as shown in Figure 12.

y

\..40~----~~~+_----~

20~~~+-----+_----~

o

L -_ _

~-'-

_ _ _ __'__ _ _ _....

o
VO(VOLTS)

"

Vo (VOLTS)

(b)

(a)

Figure 7: ICM7226A Typical ISEG vs. Vo
200 ,..-----,------,--..---.

~
150

r-'k-"k--'k-"l.c-l--f----c,lL-,ol
2

;;
~100~----~~--4-----~
.§

~ (3

"u:

4

)

PERIOD
MEASUREMENT
rose. 10MHz

103 CYCLES

1-t-++7IC~~!(d~-j

~ ~ : 1-+-+-.I"~qjAIP'k-'~ :::~:.:c )

FREQUENCY

o
50~-,~+_----+-----~

:OC;~~:ES
102 CYCLES.

~~ 3

1-:----t-,......,""''I-_''''''-1

~ 100 1----t-j.,7~w.j-----;--~
.§

*
~

200 r-----,-------,----,----,

1 SEC

50~~~+_----4-----~

MEASUREMENT

IL--'L....L.--I3 - COMMON HIGH WITH RESPECT TO SEGMENT.

1

~ l'

o

-10
COM 2 ACTIVE DURING

~2

rill

1

20

30

-r-

11 11
11 11

cpi, 92. t:i - COMMON LOW WIT,H' RESPECT TO SEGMENT.
COM 1 ACTIVE DURING 91 AND

~_ - -

. PEAK VOLTAGE
FOR 90% CONTRAST
h-+-l.oNI

10

40

50

AND 92'

COM 3 ACtiVE DURING 93 AND 93'

AMBIENT TEMPERATURE ("CI

Figure 6. Temperature Dependence of LC Threshold
Figure 4. Voltage Waveforms on Segment g (Vg)

TEMPERATURE EFFECTS AND
TEMPERATURE COMPENSATION
The performance of the IC material is affected by'
temperature in two ways. The response time Of the.
display to changes in applied RMS voltage gets longer
as the display temperature drops. At very low
temperatur~s (-20 DC) some displays may take several
seconds to change to a new character after the new
information appears at the outputs. However, for most
applications above ODC this will not be a problem with
available multiple~ed LCP materials, and for lowtemperature applications, high-speed liquid crystal
materials are available. One high temperature effect to
consider deals with plastic materials used to make the
polarizer. Some polarizers become soft at high
temperatures and permanently lose their' polarizing
ability, thereby seriously degrading display contrast.
Some displays also use sealing materials unsuitable
for high temperature use. Thus, when specifying displays the following must be kept in mind: liquid crystal
material, polarizer, and seal materials.

A more important effect of temperature is !he variation.
of threshold. Voltage. For typical liquid crystal materials
suitable for multiplexing, the peak voltage has a temper1 ature coefficient of -7 to -14 mV/DC. This means that as
temperature rises, the threshold voltage goes down.
Assuming a fixed value for Vp, when the threshold voltage drops below Vp/3 OFF segments begin to. be vis. ible. Figure 6 shows the temperature dependence ot
peak voltage for the same liquid crystal material ()f
Figure 5.
For ap'plications where the display temperature does
not vary widely, Vp may be set at a fixed voltage chosen
to make the RMS OFF voltage, Vp/3, just below the
threshold voltage at the highest temperature expected.
This will prevent OFF segments turning ON at high
temperature (this at the cost of reduced contrast for ON
segments at low temperatures).

D~DI1.\

ICM7231 132/33/34
DISPLAY VOLTAGE AND
TEMPERATURE COMPENSATION
Thes~ circuits allow control of the display peak voltage
by bringing the bottom of the voltage divider resistor
string out at pin 2. The, simplest means for generating a
display voltage suitable to a particular display is to connect a potentiometer from pin2 to GND as shown in
Figure 7. '

OPEN

ZOOkn ~-'----i 2 Vo,sp

36r-----=-=L
leM
7231-,
7234

A potentiometer with a maximum value of 200 kO should
give sufficient range of adjustment to suit most displays.
This' method for generating display voltage should be
u$ed only in applications where the temperature ot the
chip and qisplay won't vary more than ±5° C (±9,O F), as
the, resistors on the chip have a positive temperature
coefficient (this will·tend to increase the display peak
voltage with an increase in temperature). The display
voltage also depends on the power supply voltage, and
this will requirirtighter tolerances for wider temperature
ranges. Figure 8 shows another meth9d bf setting up a
display vbltage using five silicon,diodes in series. These
diodes, 1N914 or eqUivalent, will each have a forward
drop ·of approximately 0.65V, with approximately 20p.A
flowing through them at room temperature: Thus, 5
diodes wiil give 3.25V, suitable for a 3V display using
materials as shciwn in Figures 5 arid 6. For higher voltage
.displays, more diodes may be added. This circuit has
. the' additional advantage of reasonable' temperature
compensation,.as each diode has a negative temperature
coefficient cif -2 mV;oC; five in series gives -10 mVloC,
.
not far.from optim(Jm for the material described..

6
,

4 0 . . . - - - +5

Figure 7

V+

2 VOISP

40

+5

36

-=

leM
72317234

The disadvantage of the diodes in series is that only
integral multiples o.f the diode voltage can be aChieve, d.
The· diode voltage multiplier circuit shown in Figure 9
allows fine-tuning the display voltage by means of the
potentiometer; it likewise provides temperature compensatioA ·sin.ce· the temperature coefficient of the
transistor base-emitter junction (about -2. mVlOC) is
also r:nultiplied.
..

Figure 8

The transistor used in the circuit of Figure 9 must have
a beta.of at least 100 with a collector cur.rent of 1O·~A.
The inexpensive 2N2222 shown in the figure. il'1 a
su'i'table device, but any transistor with high beta at low
purrent will function prOPerly..
For battery operation, where the display voltage is
generally the same as the battery voltage (usually 34.5V), the ,chip may be operated at the display'voltage,
with VOISP connected to, GND.
'
,
The inputs of the chip are designed such that they may
be driven above V+ without damaging the chip. This
allQws, for example, th'echip and display to operate at a
regulated 3V, and a microprocessor driving its inputs
to operate with a less well controlled 5V supply. The
inputs should not be driven more than 6.5V above
GND under any circumstances.
,

V+

2 Vo,sp

2Dkn
POTENTIOMETER

leM
72317234

4Dkn

Figure '9

6-100

40

'+5

ICM7231/32/33/34
DESCRIPTION OF OPERATION
PARALLEL INPUT OF DATA
AND ADDRESS ICM7231, ICM7233
The parallel input structure ef the ICM7231 and
ICM7233 devices is erganizeej to. allew simple, direct
interfacing to. all micreprecessers, see bleck diagrams
Figures 10 and 11. In the ICM7231, address and data
bits are written into. the input latches o.n the rising edge
ef the chip select input. In the ICM7233, the two. chip
selects are equivalent; when beth are lew, the latches
are transparent and the data is latched en the rising
edge ef either chip select.

08

X Y Z

01
X Y Z

06
X y'Z

05
X Y

Z

The rising edge ef the chip select ,also. triggers an enchip pulse which enables ,the !lddress deceder and
latches the, deceded data into. tl'le addressed digit
eutputs. The timing requirements fer the parallel input
devices are shewn in Figure 12, with the values' fer
setup, held, and pulse width times shewn in AC Characteristics en page 3. Nete that then~ is a minimum
tiiTle between chip select pulses;,this is to. allew sufficient time fer the en-chip enable pulse to. decay, and
ensures that new data deesn't appear at the deceder
inputs befere the deceded data is written to. ,the
eutputs. '

04

03

02

X Y Z

X Y Z

X Y Z

01
X Y

Z
V·

SEGMENT
LINE
DRIVERS
3WIDE

OUTPUT
, LATCHES
9WIOE

VH

g~~~l~,

VL

VOLTAGE
LEVEL
GENERATOR

VOl...
t-t-t-----PIN 2 (INPUT)

COM'
COM 2

COM 3

I

'

DATA INPUTS

Figure 10. ICM7231 Block Diagram

6·101

ICM7231 132/33/34

04,

UVWXYZ

03

02

01

UVWXYZ

UVWXYZ

UVWXYZ

V·

OUTPUT

VH

LATCHES
18 wIDe

ON CHIP
DISPLAY
VOLTAGE

LEVEL

•

GENERATOR

18

18

~H_-<..V:.;D:::IS::..P PIN 2 (INPUT)
18

DATA

COM 1

DECODER

COMMON

, LINE

COM 2

DRIVER
COM 3

I

.1~,CS2!

ADDRESS
INPUTS

CHIP SELECT
INPUTS

. Figure 11. ICM7233 Block Diagram

CS2
INPUT

\---------'------l
---

/-

.,

S)~----------------~·

CS1
INPUT

DATA
ADDRESS

INPUT

DO NOT CARE

PARALLEL INPUT TIMING ICM7233
(ICM7231 HAS ONLY ONE CHIP SELECT. IT APPEARS AT PIN

1.1

Figure 12. ParaUeJlnpul Timing

6-102

ICM7231 132/33/34
Input signal, and when the'correct number of bits has
been shifted into the shift register (8 in the ICM7232, 9
in the ICM7234), the DATA ACCEPTEDOLJtput goes
low. Following this, a low-going pulse at the WRITE
input will trigger the chip tb decode the data and store
it in the output latches of the addressed digit. After the
data is latched at the outputs, the shift register and the
control logic are reset, returning the DATA ACCEPTED Output high. After this occurs, a pulse· at the
WRITE input will not change the outputs, but will reset
the control logic and shift register, assuring that each
data bit will be entered into the correct position in the
shift register depending on subsequent DATA CLOCK
inputs.

SERIAL INPUT OF DATA AND
ADDRESS ICM7232, ICM7234
The ICM7232 and I,CM7234 trade six pins used as data
inputs on the ICM7231 and ICM7233 for six more segment lines" allowing two more 9-segment digits
(ICM7232) or one more 18-segment character (ICM7234).
This is done at the cost of ease in interfacing, and
requires that data and address information be entered
serially. Refer to block diagrams, Figures ,13 and 14
and timing diagrams, Figures 15,16, and 17. The interface consists of four pins: DATA Input, DATA CLOCK
Input, WRITE Input and DATA ACCEPTED Output.
The data present at the DATA Input is clocked into a
shift register on the rising edge of the DATA CLOCK

010

X Y Z

09
X Y

08
Z

X

06

07

Y Z

X Y

05

04

03

02

01

Z

ON CHIP

VH

OUTPUT
LATCHES
9WIDE

VL '

DISPLAY
VOLTAGE
LEVEL
GENERATOR

H-f-+--,VD:::;IS,,-P PIN 2 (INPUT)

COM 1
COMMON

LINE
DRIVERS

COM 2

COM3

~

/

SHIFT REGISTER

SHIFTS RIGHT TO LEFT
ON RISING EDGE OF DATA CLOCK

DATA

DATA

INPUT CLOCK
, INPUT

WRITE

INPUT

DAT,A

ACCEPTED
OUTPUT

Figure 13. ICM7232 Block Diagram

6·103

ICM7231/32/33/34
The shift register and control logic will also be reset if
too many data clock input edges are received; this also
prevents incorrect data from being decoded. In the
ICM7232, the eleventh clock resets the shift register
and control logic, while in the ICM7234 it is the tenth.
The recommen_ded procedure for entering data is
shown in the serial input timing diagram, Figure 15.
First, When DATA ACCEPTED is high, send a WRTfE
pulse. This resets the shift register and control logic
and initializes the chip for the data input sequence.
Next clock in the appropriate number of correct data
and address bits. The DATA ACCEPiED Output may
be monitored if desired, to determine when the chip is
read to output the decoded data. When the correct
number of bits has been entered, and the DATA
ACCEPTED Output is low, a pulse at WRITE will cause
the data to be decoded and stored in the outputs ofthe
addressed digit. The shift register and control logic are
reset, causing DATA ACCEPTED to return high, and
leaving the chip ready to accept data for the next digit.

D5
UVWXYZ

D4
UVWXYZ

D3
UVWXYZ

Note that for the ICM7232 the eleventh clock resets the
shift register and control logic, but. the DATA
ACCEPTED Output goes low after the eighth clock.
This alloWs the user to abbreviate the data to eight bits,
which will write the correct character to the 7-segment
display, but will leave the annunicators off, as shown in
Figure 16.
If only AN2 is to be turned on, nine bits are clocked in; if
AN1 is to be turned on, all ten bits are used.
'In the ICM7234, nine bits are always reguired; the
control logic is similar,but allows only a WRITE (DATA
ACCEPTED, Low) with nine bits entered in the shift
register, as shown in Figure 17.
The DATA ACCEPTED Output will drive one lowpower Schottky TTL input, and has equal current drive
capability pulling high or low.
Note that ,in the serial input devices,it is possible to
address digits which don't exist. Tables 2 and 5 show
that when an incorrect address is applied together with
a WRITE pulse, none of the outputs will be changed;

D2
UVWXYZ

Dl
UVWXYZ

SEGMENT
LINE
DRIVER
6WIDE

v+

OUTPUT

VH

LATCHES

18 WIDE

D]

18

18

ON CHIP
DISPLAY
VOLTAGE
LEVEL
GENERATOR

VL

VOISP

PIN 2 (INPUT) ,

18

DATA
DECODER

CHARACTER
ADDRESS
DECODER

COM 1

EN

COMMON
LINE
DRIVERS

COM 2
COM 3

~
/
SHIFT REGISTER

'
SHIFTS RIGHT TO LEFT'
ON RISING EDGE OF DATA CLOCK

DATA
INPUT

DATA WRiTE DATA
CLOCK INPUT ACCEPTED
INPUT'
OUTPUT

, Figure 14. ICM7234 Block Diagram

6·104

IC.,.7231 132/33/34

D~DI!:.
ELEVENTH CLOCK
WITH NO Wiii'fl PULSE
RESETS SR + LOGIC

DATA
CLOCK
INPUT
(PER ~IT
OF DATAl

DATA
INPUT

.DATA
ACCEPTED
OUTPUT

WRITE
INPUT.

,..,~ ••• ~ ••••

AND STORES'
DATA, RESETS SHIFT
REGISTER AND LOGIC
WHEN DATA ACCEPTED
IS LOW

RESETS SHIFT REGISTER
AND INPUT CONTROL
LOGIC WHEN OATA
ACCEPTED HIGH

Figure 15. ICM7232 One Digit Input'Timing Diagram, Writing Both Annunicators

ICM7232 WRITE ORDER

DATA
CLOCK
INPUT

OATA
INPUT

~':';:";:':';:";:':';';~~~~Io:l.:.;:,,;:.:.;,;'i:it~~:.t

DATA
ACCEPTED
OUTPUT

.---1
WI!lTE
INPUT

RESETS SHIFT REGISTER
AND CONTROL LOGIC
WHEN OATA ACCEPTED
.ISHIGH

~DONOTCARE

Figure 16. ICM7232 InputTiming Diagram, Leaving Both Annunciators OFF

6-105

D~DIb

ICM7231/,32/33/34

TENTH CLOCK.
WITH NO Wi!lTE
PULSE RESETS
SRAND LOGIC
DATA
CLOCK
INPUT

\

'--

DATA
INPUT

DATA
ACCEPTED
OUTPUT

. --I

-II-,twn
twp I---

------------------------~
LJ.~~--.
RESETS SHIFT REGISTER

WRITE --\;
INPUT
,

I ~~~f~~ci~~T~~~~~I::H

'I

_DONOTCARE

WRITE ORDER

Figure 17.· ICM7234 Orie Character Input Timing Diagram

I]
•

DISPLAY FONTS AND OUTPUT CODES
The standard versions of the ICM7231 and ICM7232
chips are programmed to drive a 7-segment display
plus two annunciators per digit.

decimal point) on COM3 (AN1 i (see Figure .19). The
"C" d~vices provide only a "Code 8" output for the
7-segments.

The "A" and "8" suffix chips place both annunciato, rs
on COM3. The display connections for one 'digit ofthis
display !Ire shown in Figure 18. The "A" devices decode
the input data· into a hexadecimal 7-seQment output,
while the "8" devices supply Code 8. outputs (see
Table 1).
The "C" devicE!5 place the left hand annunciator on
COM1 (AN2) and the right hand annunciator (usually a

See Table 3· for annunicator input controls. The
ICM7233 and ICM7234 are supplied in an "A" version
only. The layout for a single charac~r is shown in
Figure 20 with output decoding shown in Table 4.
The data decoder is mask program'mable. For larger
quantity orders (10,000 and up) custom decoder
programs can be arranged. Contact the factory for
details.

X

y,

z
COM1~~r--.------'---~-----

x

Y

z
COM 2

.~

SEGM ENT LI NE CONNECTIONS

:i,~

..

COM3----~--~------~-­

SEGMENT LINE CONNECTIONS

COMMON LINE CONNECTIONS

LH ANNUNCIATOR ON COMMON #1 (TOPI (AN 2)
RH ANNUNCIATOR ON COMMON #3 (BOTTOM) (AN I)
. "C"'SU~FIX DEVICES

COMMON LINE CONNECTIONS

lilliI.

+

'ANNUNCIATORSCAN BE: IllQf] •
1:;.. -.ARROWS
THAT POINT TO INFORMATION PRINTEO AROUND THE DISPLAY
OPENING. ETC,. WHATEVER THE DESIG,~ER CHOOSES TO INCORPORATE·
IN THE LIOUID CRYSTAL DISPLAY.

BOTH ANNUNCIATORS
ON COMMON #3
(AT BOTTOM OF CHARACTER)
("A" AND "B" SUFFIX VERSIONS)

r

FIgure 18. ICM7231 and ICM7232 Display Fonts
(':A" and "B" Suffix Versions)

Figure 19, ICM7231 and ICM7232 Display Fonts
("C" Suffix VerSions)

6·106

ICM7231 132/33/34
U

v wx

z·

Y

Table 2

COM1--~---r-r--.--r--

DISPLAY
OUTPUT

CqDE INPUT
ICM
7232
ONLY
COM 2

COM3-----L----~----­

20.

A2

Al

AD

D

D

D

D

01

D

D

D

1

02

D

D

1

D

03

D

D

1

I

04

D

1

D

D

05

D

1

D

1

06

D

1

1

Q.

07

D

1

1

1

08

1

D

D

D

09

1

D

D'

1

DID

1

D

1

D

NONE

1

D

1

1

NONE
NONE

COMMON LINE CONNECTIONS

SEGMENT LINE CONNECnONS

Figure

DIGIT
SELECTED

A3

ICM7233 and ICM7234 Display Font
(18-Segment Alphanumeric)

Table 1
CODE
INPUT

DISPLAY
. OUTPUT

BD BD BD BD
3
2
1
D

HEX

CODE
B

,_,

D

D

D

D

n

n

D

D

D

1

I
I

I
I

D

D

1

D

D

D

1

1

I:'-, e-,
:1

1

D

D

I-I

:1

D
D

1

D

1

D

1

1

D

I_I

1

1

1,

D

D

D

1:1

1

D

D_

1

1

D

1

D

1

D

I

1
D

,-,,-,:' 1=',b
,-, :-1e
,
cl ,,-e F'
,-,-

D

1

I

D

I

I

I

I

D

1

1

I

1

D

D

1

D

1

NONE

I

1

1

D

NONE

1

1

I

1

NONE

ADDRESS DECODING (lCM7231/32)

Table 3

E.-, 0:0-,
,

1

,.

1

1

I-I
II:1 ":,-

D

I

I

CODE
INPUT

I

n

n
0:0

AN AN
1
2

D

D

:=1

D

1

.1-.

1

D

I

1

BLANK

BINARY DATA
DECODING
(lCM7231/32)

DISPLAY OUTPUT
ICM7231C
ICM7231 AlB
ICM7232C
ICM7232 AlB
LH
BOTH
ANNUNCIATORS ANNUNCIATOR
COM 1
ON COM 3
RH
ANNUNCIATOR
COM 3

,-,
n

'I::

H

'1-'

CI.

ANNUNCIATOR
DECODING

6·107

,-,CIF:

Cr,

ICM7231/32/33/34
Table 5

Table 4
'CODE INPUT

DISPLAY OUTPUT
CODE
INPUT

05.04
03 02

01

DO

0.0

0.1

[E

p

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

'0

0

0

1

0

1

0

1

1

0

0

1

1

'1

1,

0

0

0

0

0

1

1

R, Q
B R
C 5
IJ T
E U
F V

0

1

0

1

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

1.0

1.1

ICM
7234
ONLY

0
I

I

A2

~
:E :3
9; Y
% S
Jj 5

DIGIT
SELECTED

,
Al

AO

0

0

0

01

0

0

1

02

0

1

0

03

0

1

1

04

1

0

0

05

1

O.

1

NONE

1

1

0

NOt>lE

1

1

1

NONE

II

hi I 1
H X  9
J Z
I-< [ +
L
L \ /
M J :>
N )'I
0 ~ / ?

[j

*

ADDRESS
DECODING
(lCM7233/34)

/

DATA DECODING
6 - BIT ASCIl-1S SEGMENT
(lCM7233/34)

APPLICATIONS
Figures 21 and 22 show typical applications for the
ICM7231-34 family..
'

v'

VD~L

1v'Vee

A

26 40
Pl0 27
20Vss
I
20SCI

--l120P~

I

II

6MHzD

~120P-;

30SC2

--l~
v'-

P 17 34
P20 21
22
4 RESET
23
24
35
7 EA
36
P2637
P 27 38
6'SS

DBO 12

~

{-=

1 TO

INPUTS

39T1

600

C}

§
~

r-

1

I/O PORT

v'
GND
I/O PORT 2

TEMPE RATURE
COMPE NSATION

27

27

1=.

F-

/).

40

v'

3-29

VOISP

ICM7233A
36GND
DO - - - - - - 0 5 AOAl CS2CSl
30 ---------35 37 38 39 1

2

3-29

2

v'- 40 v'
GND

36GNO

VOISP

ICM7233A

00--,------05 AOA1CS2CS1
30 - - - - - - - - 35 37 38 39 1

I

1

1

I

I

~
i

201<11
VOISP

ADJ.

n

40k

TO
EXT ERNAL
MEM ORY AND
OTH ER PERIPHERALS

}"w

I
BUS:
I
I
OB719

,11925108
ALEI p J N 1 1 :
8048
IM80C48
IM87C48
MICROCOMPUTER

2N2222

PROG
DIGIT ADDRESS IS MERGED WITH DATA AND. OUTPUT TO DISPLAY AS IF WRITING TO EXTERNAL RAM

Figure 21.' 8048/1M80C48 Microcomputer with 8 Character 16 Segment Full ASCII Triplex LiqL!id Crystal Display

6-108

ICM7231 132/33/34

I! ~
..L

-

~
1.21

...r::-- 39 EXTAL

27

Vee 35

ICM7233AIPL

ir'
v'

~6A;:OADD CS2 CS1

40 RESET

311-3537.38 39

-

2 HALT

-

7BA

. DATA

BUS
26·33

6
D'.Di

U

,

21-28
PORT

RJIii VMA
34
5

I

I

6
D'.Di

A,

~15PLAV

29 V::'

ADDRESS

WITH RAM

4

-

2
AD.
AI

ICM7233AIPL

1
A3

6
D'.Dt

2

AD.

r-1

A,

A,

ICM7233AIPL

D'.Dt:~·
AI

2

D'ATA
-

STORAGE ENABLE

'OTHER I/O

8

7

~lfA g~~~ F}CONTROL

r-}

.

20E f;IQ 19
6 CSO
1 8 F . COUNTER/TIMER
7 RJIii CTG 17

ru

36 Vss

IRQ

I J.

MC6846

.

ROM . I/O TIMER

Figure 22. MC6802 Microprocessor with 16 Character 16 Segment Full ASCII Liquid Crystal Display

D6

D7

D6

D5

D4

D3

D2

Dl

COM 1
COM 2
COM 3

ICM7231AFIBF
;rOPVIEW

Figure 23. "Forward" Pin Orientation and Display Connections.

6·109

f40. n

1
A5

-

}TOOT HER
PARTS OF
SV5TE M

I 2·5. 16. JO..33. 36·40 ~4LSOO

16

MC6602
MI CROPROCESSOR

TIm

ICM7233AIPL

ADJ.
2DkO

8

ADD 9-20

BUS 22·25
E37

-

1
A,

2

AD.

v'
2N2222

27

:..

2

DISPLAY VOISP

GND

27

VOISP

I

4OV" 3-29

v'

27

38 XTAL

3MR
I~
-=- v' 10kn_ 6NMI

=3'=3

T r-J __
..L
L_ ~III -,I e

TEMPERATUR'e
COMPENSATION

58·
RE 36

D4MHz

~

E:_F~_CJ..LL_
T I

I
8
Vee

V"
V·

IT
\II

V'

ICM723~/32/33/34
ISELECT I

D
,,;I.

09

DB

~

I FORWARD !

8

07

1 D
L.
D.

06

05

D4

03

02

01

B. B. Ia·a
D B'B
. I . c.
. .
6.

b.

b.

ISTOP I

(WAIT!

(][]

COM 1
COM 2
COM 3

-::::- ......
:::: ....... ::: ......... : : ........ .......

ICM7232CR

, ' ..... ' ..... ' , ...... ,
':' ........................
........

,.........

,,' ,

"'"

TOPVIEW

"

"

PCB TRACES UNDER PACKAGE.

Figure 24. "Reverse"Pin Orientation and Display Connections.

CHARACTER
4

CHARACTER
3

CHARACTER

2 '

CHARACTER
1 '

z
y

x

ICM7233AFIO

W

v
" U

Z
Y

xwv

LCD

U

DIE MOUNTS UNDER LCD

TOP VIEW (BOTH DIE AND LCD)

Figure 25. "Forward" Die Pad Orientation and Typical Triplex Alphanumeric Display Connections.

6·110

"Q

!il><-<-<
N

N

N

........ "

-"

->0

r:

....

N

~.
•

~WWWNNN--""

2V

COM 3

N

2U

(;

3Z

CoM2

3V
3X

CoMl
VDISP

i:

~

c.:.
Co>

3W

.

3V

~

i:::2~]_
'11t~~...:rl?{,;;r,;;r,;;r,;;r~;
___
--.~- =?':~~~1

~

::

,J:Io'~

< c:

CI

CI

C

C

0

....

N

W

·c
~

>< -<

"

CoM3

CSt

'.....

5X

VDISP

6Z

;.
:.;
C;
S
.

6V

V·?

6)!

A2

-

n

c

Q

•

;~

AO

~

=

=>

>

=

m

CEll

....

N

CI

....

N

%

"-

__,

~

N

""'"
~

~
~

W

AI

;:;

M

~
"

GND

U1

=

--,

-<

COM 2
COM 1

N

~

:'~ij ~
....

5Z
5V

Co> ,
...

___

N o N

-

Al

:; "i~ ~~",£",j;'-*-<:':lI1i::;"~J;.~~.I:~

-< N

£

_V·
':'
. I:~ 'II

N ><

~

•

""a

_

~

4Z

>< -<

n

2

~
o
-t

s

=

N<><-«

~~~::::c: ,.,'

5Z

3Z

D

~1

(;

3X

VDlSP

i:

3W

~"

3V

DATA CLOCK
INPUT
V'

~

. '"

N

•

COM 3
CoM2
COM 1

~
"

" ....

~

(;

6Z (lOX)'

DATA CLOCK INPUT"

i:

6V (tDV)'
"
6X (10Z)'

v+

~.
~

" "
WRITE INPUT

3U

WRITE INPUT

7Z (9X)'

DATA INPUT

4Z

DATA INPUT

7V (9V)*

DATA ACCEPTED

DATA "ACCEPTED

7X (9Z)*

4V

-

4X

OUTPUT

OUTPUT

GND

~

GND
oP!.&:ao.c:.U1U1U1U1U1U1

:E <

C:.N

-<

><

== <

;.

~

c:

R
CEll

ml

:D

-

~ ~

~

~

~.

c:; = c;
Cii'ca-'::::i'::::i':::i~,::;!
2:$ .:S
2$ .:S ~'~ :! ~
****.*--.*

a

.. ..

1=
.

(1JD

=
F

"

.

ICM1235
Four Digit
Non-Multiplexed Vacuum
Fluorescent Displ..V
Decoder-Drivers
FEATURES'

DESCRIPTION

• 28 high voltage segment drivers provide four
. 7·segment digl~s
.

The IcM7235 family· of display driver circuits provides the
user with a single chip interface between digital logic or
microprocessors to non-multiplexed 7-segment vacuum
fluorescent displays;

• Multiplexed BCD Input (7235)
• High speed processor inttnface (7235M)
• 7.s~gment hex (0·9, A·F) or Code·B (0,9, dash, E,
H, L, P, blank) output versions available
• Display blanking input
• All devices fabricated using high density
MAX·C~OStl1) LSl'technology for v~ry low·power,
high·performance operation .
• All inputs fully protected against static discharge

PIN CONFIGURATIONS'

The chips provide 28 high voltage open drain P-channel
transistor outputs organized as four 7-segment digits.
The devices are available with two Input configurations. The
basic devices provide four data-bit inputs and four digit
.. select inputs. This configuration is suitable for interfacing
with multiplexed BCD .or binary output devices, such as
the Intersil ICM7217, ICM7226 and ICL7103. The
microprocessor interface devices (suffix M) provide data
input latches and digit select code latches under control of
high-speed chip select inputs. These devices simplify the
task' of implementing a cost-effective alphanumeric
7-segment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and
display updating.
'

(OUTLINE DRAWINGPL)

The sta:ndard devices available will provide two different
decoder configurations. The basic device will decode the
four bit binary input into a seven-segment alphanumeric
hexadecimal output (0.9, A-F); The "A" versions provide-the
same output code as the ICM7218 Code "B" (0-9, dash, E, H,
L, P, blank). Either device will correctly decode true BCD to.
seven-segment decimal outputs.
.
All devices In the 'ICM7235 family are packagep in a stan·
dard 40-pin plastic dual-in-line package.
Table 1, the option matrix and ordering information, shows
the four standard devices of the ICM7235 family and their
markings, which serve as part numbers for ordering purposes.

40 D1
39 C1
38 81
37 A1
3& Ground
35

leM
7235MI35AM -

:-1I
y+

:
~~ ~:

CHIP

S~LEcT INPUTS

DIGIT SELECT CODE BITS

TABLE 1: OPTION MATRIX AND ORDERING .INFORMATION
83 14

Order Part Number

Cl 15
03 16

ICM72351PL

"17

03 18
F3 19
A420
-.._ _ _r

6-112

,

OutP~t Code
. Hexadecimal

Input Configuration
Multiplexed 4-8it

ICM7235A IPL

Code 8

Multiplexed 4·8it

ICM7235M IPL

Hexadecimal

M.lcroprocessor Interface

ICM7235AM IPL

Code B

Microprocessor Interface

to

ICM7235
ABSOLUTE MAXIMUM RATtNGS
Power Dissipation (Note 1) ......•....... 0.5 W @ + 70·C
Supply'Voltage (V+ -Ground) . . . . . . . . . . . . . . . . .. 6.5 Volts
Input Vo"itage (Note 2) .......... V+ +0.3V, Ground -0.3V
Output Voltage (Note 3) ......... : ... ,,', ...... , V+ -35V
Operating Temperature Range. . . . . . . . .
-20°C to +85°C
Storage Temperature Range .......... -55·Cto +125·C

Absolute maximum ratings define stress limitations
which, If exceeded, may permanently damage the device.
These are not continuous' duty ratings. For continuous
operation these devices must be operated under the condl·
tions defined under "Operating Characteristics."

TABLE 2: OPERAT,NG CHARACTERISTICS
. All parameters measured with V+ = 5V, T A = 25°C

PARAMETER

SYMBOL

Operating Supply Voltage Range

CONDITIONS

VsuPP
1+

Supply Current

1+,

Supply Current
Segment OFF Output Voltage

VSEG

Segment OFF Leakage Current
Segment ON Current

MIN,

TYP

MAX

UNIT

4

5

6

V

50

p.A

100

mA

10

p.A

Measured V+ to Ground
Test circuit; display blank or OFF

t 10

Measured V+to Display
ISLK = 10,..A

ILS

VSEG=V+ -30V

ISEG

VSEG=V+ -2V

SYMBOL

CONDITIONS

V

30

-

0.1
1.5

2.5

MIN

TYP

mA

INPUT CHARACTERISTICS
PARAMETER
logical "1" Input Voltage

VIH

Referred to Ground

Logical "0" Input Voltage

VIL

Referred to Ground'

IILK
CIN

Pins 27-34

,

input Leakage· Current
Input Capacitance
ON/OFF Input Leakage
I

Pins 27·34

UNIT
V

±0.1

1.5

V

±1

p.A

5

IILK(ON/OFF) All Devices
CIN/ON/OFF All Devices

ON/OFF Input Capacitance

MAX

3

±0.1
200

pF
±1

p.A
pF.

AC CHARACTERISTICS - MULTIPLEXERD INPUT CONFIGURATION
Digit Select Active Pulse Width

tsa

Data Setup Time
Data Hold Time
Inter-Digit Select Time

AC CHARACTERISTICS -

Refer to Timing Diagrams

tds

1
500 .

ns

tdh

200

ns

2

P.s

200

ns

tids
MICROPROCESSOR INTERFACE

Chip Select Active Pulse Width

tcsa

Other chip select either held active,
or both driven together

Data Setup Time

tdsm

100

Data Hold Time

tdhm

10

Inter-Chip Select Time

tics

2

p.S

ns
0,

ns
p.S

..

NOTE.1: This limit refers to that of the package and will not be realized during normal.operation.
NOTE 2: Due to the SCR structure Inherent in the CMOS process used to fabricate these devices, connecting any input terminal to a
voltage in excess of v+ 'or ground may cause destructive device latch-up. For this reason, it is reco~mended that inputs from ex·
ternal sources operating on a different power supply be applied only after the device's own power supply has been established,
and that on rnultlple supply systems th.e·supply to the ICM7235 be turned on first.
NOTE 3: This value refers te;> the display outputs only,

6-113

D~DIb

ICM7235
INPUT DEFINITIONS

In this table, V+ and ground are considered to be normal operating input logic levels. Actual input low and high levels are
specified in Tat;>le 2. For lowest power consumption, input signals should swing over.the full supply.
INPUT

TERMINAL

CONDITION

FUNCTION

BO

27

V+ = Logical One
Ones (Least Significant)
Ground = Logical Zero

B1

28

V+ = Logical One
Twos
Ground= Logical Zero

B2

29

V+ = Logical One
Fours
Ground = Logical Zero

B3

30

V = Logical One
Eights (Most Si'gnificant)
Ground = Logical Zero

ON/OFF

5

V+ = OFF:,
Ground =ON

+

Data Input Bits

.

Display ON/OFF Input

ICM7235,ICM7235A
MULTIPLEXED BINARY INPUT CONFIGURATION
INPUT

TERMINAL

01

31

02

32

03

33

04

34

....

CONDITION

FUNCTION
01 (Least Significant) Digit Select
02 Digit Select

V+ = Active
Ground = Inactive

03 Digit Select
04 (Most Significant) Digit Select

ICM7235M, ICM7235AM
MICROPROCESSOR INTERFAcE INPUT CONFIGURATION
INPUT

DESCRIPTION

DS1

Digit Select
Code Bit 1 (LSB)

31

DS2

Digit Select
Code Bit 2 (MSB)

32

CS1

Chip Select 1

33

CS2

Chip Select 2

34

TERMINAL

CONDITION

FUNCTION.

V+= Logical One
Ground = Logical
Zero

Dsi & DS1 serve as a two·bit Digit Select Code Input
DS2, DS1 = 00 selects 04
DS2, DS1 =01 selects 03
DS2, DS1 =10 selects 02
DS2, DS1 = 11 selects 01

,

When both CS1 and CS2 are taken to ground, the data at
the Data and Digit Select code inputs are written into the
input latches. On the rising edge of either Chip Select, the_
data is decoded and written into the output latches.

V+ = Inactive
Ground = Active

v

ICM 7235 TYPICAL DC VACUUM FL.UORESCENT DISPLAY CONNECTION
OPEN·DRAIN HIGH·VOLTAGE P·CHANNEL TRANSISTOR OUTPUTS

10·30V
TYP
DEPENDING

f::---'\\'~~~~~~~~~~~~~~r==r==r-l

~"'-"'----""':.l---'-I'

+-=-

+

4·6V

ON
DISPLAY

-=-'

1,35
V-

\

ICM7235 •

/

' - - - GROUND

36

["1
"'1"'1

.

.

IG.

abc

,d

,-

e
I...-

III
DEPENDING ON
DISPLAY

3120 Central Expressway
Santa Clara, CA 95051
Tel.. (408) 241·8222
Model FIP 4F8S

6·114

~ ~GRID

2

L..e

~-

DIRECTLY HEATED
VFILAMENT CATHODE
,GLASS ENVELOPE

DC FILAMENT
DISPLAY .

:~:2_5~

1'. NEC Electron, Inc.

:.....

g

I ./,

- 1- - - - - - - - - - - - - -

IF'
VACUUM FLUORESCENT DISPLAYS (4 DIGIT):

f

PHOSPHOR:COATED
ANODES

F-'

"

ICM7235
ICM7235135A

04

03

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

DISPLAV

ON/Off

OATA
INPUTS

DIGIT
SELECT
INPUTS

ICM7235M135AM

0'

SEGMENT OUTPUTS

03
SEGMENT OUTPUTS

02
SEGMENT OUTPUTS

01
SEGMENT OUTPUTS

DISPLAY

ONIOFF

DATA

INPUTS

2-81T
DIGIT SELECT
CODE INPUT

CHIP SELECT 1
CHIP SELECT 2

6-115

ICM7235
setup, hold, and inter-digit select times must be
met to ensure correct output.
The ICM7235M and AM devices are intended to
accept data from a data bus under processor
control.
In these devices, the four data input bits and the
2-bit digit select code (DS1 pin 31, DS2 pin 32)
are written into input buffer latches when both
chip select inputs (CS1 pin 33, CS2 pin 34) are
taken to ground. On the rising edge of either chip
select input, the content of the data input latches
is decoded and stored in the output latches of
the digit selected by the contents of the select
code latches. A select code of 00 writes into 04,
01 writes into 03, 10 writes intoD2 and 11 writes
into 01. The timing relationships for inputting
data are shown in Figure 3; and the chip select
pulse widths and data setup and hold times are
specified in Table 2.

CIRCUIT DESCRIPTION
Each device in the ICM7235 family provides
signals for directly driving the anode terminals
of a four-digit, 7-segment non-multiplexed vacuum
fluorescent display. The outputs are taken from
the drains of high-voltage, low-leakage P-channel .
FETs, each capable of withstanding >-,35V with
respect to' V+. In addition, the inclusion of an
ON/OFF input allows the user to disable all segments by connecting pin 5 to V+; this same input may also be used as a brightness control by
applying a Signal swinging between V+ and
ground and varying its duty cycle.
The ICM7235 may also be used to drive nonmultiplexed common cathode LED displays by
connecting each segment output to its corresponding display input, and tying the common
cathode to ground. Using a power supply of 5V
and an LED with a forward drop of 1.7V results in
an "ON" segment current of about 3m A, enough
to provide sufficient brightness for displays of
up to 0.3" character height.
Note that these devices have two V+ terminals;
each should be connected to the positive supply
voltage. This double connection is necessary to
minimize the effects of bond wire resistance,
which could be a problem due to the high
display currents.
'

TEST CIRCUIT
5V

v+

SEGMENTS OFF

V

36

Ground = SEGMENTS ON

Dl
•

V' 35

Input Configurations and Output Codes
The standard devices in the ICM7235 family accept a four-bit true binary (i.e., positive level =
logical one) input at pins 27 through 30, least
significant bit at pin 27 ascending to the most
significant bit at pin 30. The ICM7235 and
ICM7235M decode this binary, input into a 7segment alphanumeric hexadecimal output,
while the ICM7235A and ICM7235AM decode the
binary input into the same 7-segment output as
the ICM7218 "Code B," i.e., 0-9, dash, E, H, L, P,
blank. These codes are shown explicitly in Table 3.
Either decoder option will correctly decode true
BCD to a 7-segment decimal output.
These devices are actually mask-programmable
to provide any 16 combinations of the 7-segment
outputs decoded from the four input bits. For
larger quantity orders, (10K pcs. minimum)
custom decoder options can be arranged. Contact your Intersil Sales Office for details.
The ICM7235 and ICM7235A devices are intended
to accept multiplexed binary or BCD output.
These devices provide four separate digit lines
(least Significant digit at pin 31 ascending to
most significant digit at pin 34), each of which
when taken to a positive level decodes and
stores in the output latches of its respective
digit the character corresponding to the data at
the input port, pins 27 through 30. More than one
digit select may be activated simultaneously
(whiCh will write the same character into all
selected digits), although the timing requirements shown in Figure 2 and Table 2 for data

34

V' MICROPROCESSOR
VERSIONS

DIGIT/CHIP { 33
SELECT
INPUTS

32

Ground MULTIPLEXED VERSIONS

31

DATA
INPUTS

f 3.
29

V'

1 28
\27

20

21

TYPICAL OUTPUT CHARACTERISTICS
- 10

-12

-

-

-

-

J'
.1,

~r

I//J

v+

-r

V. '(J
4V

v. 1"4,5V

~

-

v~ ~

-:Fr
6-116

,/

~

l -I - f~
,b----- f- "/

rl-i-

....V J
1/

V

3' lOUT

rnA

~~DlL

IC.M7235
Table 3 Output Codes
, DIGIT SELECT
DN_l

BINARY
83 82 81 80

plGIT SELECT
ON

Figure 2. Multiplexed Input Timing Diagram

cs.
(CS2)

0
0

0
0

0
0

0

0

1

0
1

0

0

0

0
0

0
1

0

1

1

1

.1

0

0

0

0

0
1

0

CS2
(CS')

0

0
0

DATA AND
DIGIT SELECT
CODE

im

0
0

1

= DON'T CARE

0

SEGMENT ASSIGNME;NT
\

6-117

"
L.'

'J

,?

,?
;:;
-',
'-'
S
,,;:;
,,

",

::

'-',-I
::;
,,::;

-,,
S
J

1

1
0
1
0

Figure 3. Microprocessor Interface Input Timing Diagram

CODEB
ICM7235A
ICM7235AM

O:J

0
0

HEXADECIMAL
ICM7235
ICM7235M

.::;

"
,-b
'-,

",
,

,::;

'-'0
J

E
:;
,

,-

,'-,::;

,-

(BLANK)

0

':,- -

ICM7236
41/2 Digit Counter
With Vacuum Fluorescent
Static Display Drivers
FEATURES

DESCR,IPTION

• High frequency counting - guaranteed 15MHz,
typically 25MHz at 5V

The ICM7236 anq ICM7236A devices are high-performance
CMOS 4% digit counters, Including decoders, output
latches, count inhibit, reset, and leading zero blanking circuitry, and twenty-nine high-voltage open drain P-channel
transistor outputs suitable' for directly driving non-mUlti:
plexed (static) vacuum fluorescent displays.

• Low power op,eratlon - less than 100"W
quiescent
• Direct 4Vz digit seven-segment display drive for
non-multiplexed vacuum fluorescent displays
• Store and Reset inputs permit operation as ,
frequency or period counter
.
• True count inhibit disables first counter stage
• Carry output for cascading four-digit blocks '
• Schmitt-trigger on count inp",t allows operation
In ~olsy environments or with slnwly changing
inputs
• Leading zero blanking Input and output for cor- '
~ect I~ading zero blanklrtg with cascaded devices

The ICM7236 is a decade counter, providing a maximum
count of 19999, while the ICM7236A is intended for timing
purposes, providing a maximum count of 15959.
The counter section of the two devices in the ICM7236 family
provides direct static counting from DC to 15MHz guar. an teed (with a 5V ± 10% suppiy) over the operatilJg temperature range. At normal room temperatures, the device will
typically count up to 25M Hz. The count input is provided
with a Schm,ltt trigger to allow operation in noisy environments and correct counting with slowly changing inputs. These devices also provide count inhibit, store and
reset circuitry which allows a direct interface with the
ICM7207 devices to implement a low cost, Idw power frequency counter with a minimum component count
These ,devices also, incorporate features intended to
simplify cascading in four-digit blocks.' The carry output
allows the counter to be cascaded, while the leading zero
blanking input and output allow correct leading zero blankIng between four-decade, blocks.

All inputs fully protected against static discharge
- no special handling precautions ,necessary
Devices fabricated using MAXCMos'm process
for high-performance, low power operation

PIN

CONFI~IJRATION

, The ICM7236 and, ICM7236A a-re packaged in a standard
40-pil) dual-in-line plastic package. :

(OUTLINE DRAWING PL)

01
C1
81

A1
Gr.ound

v+
Store (STO)
.'
Reset (RST) ,
Count Input (COUNT)
Count Enable (CEN)
leading Zero Output (LZO)
Leading Zero Input (LZI)
Carry Output (CRy)
112 Digit

F4 '

TABLE

G4
E4

ORDER PART NUMBER

04
A4 20

21

1: ORDERING INFORMATION

C4
84

6-118

COUNT OPTION

ICM72361PL

19999

ICM7236AIPL

15959

ICM7236
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) ............ " 0.5 W @ + 70·C
Supply Voltage (V+) ..... ',' ..................... 6.5 V
DisplayVoltage(Note3) .,., .......... ,........ V+ -35V
Operating Temperature Range. . . . . . . . .
-20·C to +85·C
Storage Temperature Range ..... '. . . .. -55·C to + 125·C

Absolute maximum ratings define stress limitations
which, if exceeded, may permanently damage the device. '
These are not continuous duty ratings. For continuous
operation these devices must be operated under the condl·
tions defined under "Operating Characteristics."

TABLE 2: OPERATING CHARACTERISTICS
(All parameters measured with V+ =5V unless otherwise indicated.)

PARAMETER

SYMBOL

Operating Supply Voltage Range
Operating Current

TVP

MAX

3

5

6

V

Test circuit, Display blank

10

50

p.A

IOLK'
Ip

Output OFF, V = V+ -30V

0.1

V1H
V1L

Pins 29, 31, 33, 34

lop

, Display Voltage

VOls P

Display Output Leakage
Input Pullup Currents
Input High Voltage
Input 'Low Voltage
Count Input Threshold
Count Input Hysteresis

Vm
VCH

Output High Current

10H

Output Low Current

IQL

Count Frequency

fcoun!

Store, Reset Minimum Pulse Width

ts, tw

NOTE" Th'. 11m", ,,',"

CONDITIONS
V+

MIN

Vsupp

Pins 29, 31, 33, 34

V=V+ -3V

V

10

p.A

PA

10

V

Pins 29, 31, 33,34

2

Carry Pin 28~ leading zero out Pin 30
VOUT= +3V.
4.5V
NOTE 2: Due to ttle SCR structure Inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages
greater than V+ or less than ground may cause destructive device latch·up. For this reason, it Is recommended that no inputs
,
from external sources not operating on the same power supply be applied to the device before its supply is established, and that
in multiple supply systems, the supply to the IQM7236/7236A be turned on first.
NOTE 3: This limit refers to the display output terminals only.

DESCRIPTION OF OPERATION
All of the chips in the ICM7236 family provide twenty·nine
outputs suitable for directly driving the anode terminals of
4 V. digit seven-segment non·multiplexed (statiC) vacuum·
fluorescent displays. Each display output is the drain of a
high·voltage low-leakage P-channel transistor, capable 'of
withstanding typically greater than -35 volts with respect
to V+. 'The output characteristics are shown graphically
under "Typical Characteristics."
'
These chips also provide a dislay ON/OFF input which may
be used to disable all the segment outputs and thus blank
the display. This input may also be used to control the
display brightness by varying the duty cycle of a signal at
the Input swinging between V+ and ground.

NOTE that these circuits have two terminals for V+; both of
these pins should be connected to the power supply positive
terminal. The double connection is necessary to minimize effects of bond wire resistance with the large total 'display
currents possible.
These chips may also be, used to directly drive' nonmultiplexed common-cathode LED displays, where each
, segment of the display is driven by one ICM7236 output, and
, the common cathode is connected to ground. With a 5V
power supply and a 1.7V LED di0ge forward voltage drop,.
the current in an "ON" segment will be typically 3mA. This
should provide sufficient brightness in displays up'to about
0.3" character height.

6-119

ICM7236
TEST CIRCUIT

, TYPICAL OUTPUT CHARACTERJSTICS

-

-

12

,.

-

-

•
J•

-

-

II

~r

~
Y+",:4V

.~
V· I=4.&V

~

~~~

-

Ground

mA

r/ll

D

~

~

..

..
.);1"
26

20

,,'
~,

V

V

,/
V' ".

..... ~TA=20·C

., ~~=;];.C
~V

,

""

..,.. --

TA=70·C

./ / , "
~

.

,.

.

SUPPLY VOLTAQE

SUPPLY CURRENT AS A FUNCTION OF
COUNT FREQUENCY
10mA

,
Ic~-h';' I

I

I-V'=6V

~~~~~CUlT

'I)

1mA

II
I) ,

100""

,
.... 1--"
10kIU

100kHz

1MHz

33
32

31
3D

29

CARRY

28

SEGMENT ASSI~NIVIENT

ICM7238

r-SINE WAVE INPUT
SWINGING FULL SUPPLY

~

ResET
COUNT

6

4S

~

34

LZI

MAXIMUM COUNT F~EQUENCY (TYPICAL)
AS A FUNCTION OF SUPPLY VOLTAGE·

's

as

. STORE

izo

20

.. .

38

V'

COUNT INH

•

1/

I-- P""

Y+ SEGMENTS OFF
Ground SEGMENTS ON

2

3 lOUT

'(jJ

V j

V~ l- I-"

~tr

r

....y".A~

.....

f-:'"

1111

ICM72381A

1

10MHz .

100MHI

"COUNT

6-120

21

D~DIb

ICM7236
COUNTER SECTION
The devices in the ICM7236 family implement a four-digit
ripple-carry resetable counter, including a Schmitt trigger on
the COUNT input and a CaRrY output. Also included is an
extra D-type flip-flop, clocked by the carry signal and
outputting to the half-digit segment driver, which can be used
as either a true half-digit or as an overflow indicator. The
counter will index on the negative-going edge of the signal at
the COUNT input, and the CaRrY output will provide a
negative-going edge following the count which indexes the
counter from 9999 (or 5959) to 10000. Once the half-digit flipflop has been clocked, it can only be reset (with the rest ofthe
counter) by a negative level at the ReSet terminal, pin 33.
However, the four decades will continue to count in a normal
fashion after the half-digit is set, and subsequent CaRrY
outputs will not be affected.
A negative level, at the COUNT ENABLE disables the first
divide-by-two in the counter chain without affecting its clock.
This provides a true count inhibitwhich is not sensitive to the
state of the count input, preventing false counts which can
result from using a normal logic gate forcing the state of the
clock to prevent coun,ting.
Each decade drives directly into a four-to-seven decoder
which derives the seven-segment output code. Each decoder
output' corresponds to the one-segment terminal of the
device. The output data is latched at the driver; when the

STOre pin is at a negative level, these latches are updated, and
when the S1'O pin is left open or at a poistive level, the latches
hold their contents.
The decoders also include zero detect and blanking logic to
provide leading zero blanking. When the Leading Zero I nput is
floating, or at a positive level, this circuitry is enabled and the
device will blank leading zeroes. When the Leading Zero Input
is at a negative level, or the half-digit is set, leading zero
blanking is inhibited, and zeroes in the four digits will be
displayed. The Leading Zero Output is provided to allow
cascaded devices to blank leading zeroes correctly. This
output will assume a positive level only when all fourdigitsare
blanked, which can only occur when the Leading Zero Input is
at a positive level and the half-digit is not set.
For example, on an eight-decade counter with overflow using ,
two ICM7236 devices, the Leading Zero Output of the highorder digit device would be connected to the Leading Zero
Input of the low~order digit device. This will assure correct
leading zero blanking for all eight digits.
The STO, ReSeT, COUNT ENABLE, and Leading Zero Inputs
are provided with pullup devices, so that they may beleftopen
when a positive level is desired. The CaRrY and Leading Zero
Outputs are suitable for interfacing to CMOS logic in general,
and are specifically designed to allow cascading of ICM7236
devices in four-digit blocks.

CONTROL INPUT DEFINITIONS
In this table, V+and ground areconsideredto be normal operating input logic levels. Actual input low and high levels are specified in
Table 2. For lowest power consumption, input signals should swing over the full supply.
INPUT

TERMINAL

VOLTAGE

FUNCTION

Leading Zero Input (LZI)

29

V+ or Floating
Ground

Leading Zero Blanking Enabled
Leading Zeroes Displayed

Count Enable (CEN)

31

V+ or Floating
Ground

Counter Enabled
Counter Disabled

Reset (RST)

--

33

V+ or Floating
Ground

Inactive
Counter Reset to 0000

Store (STO)

34

Output Latches Not Updated
Output Latches Updated

Display ON/OFF

5

V+ or Floating
Ground
V+
Ground

6·121

Display Outputs Disabled
Display Outputs Enabled

ICM7236·
BLOCK DIAGRAM

D1
SEGMENT OUTPUTS

lZD

D2

D3

D4

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

_-------1

1/2

DIGIT

OUTPUT

..----t--

lZI

COU:J - - ' - - - - - - 1
COUNT IN

CRV

DISPLAY

O'A/OFF

TYPICAL DC VACUUM FLUORESCENT DISPLAY CONNECTION

.

OPEN·ORAIN HIGH·VOLTAGE P·CHANNEL TRANSISTOR OUTPUTS

\

.,
10·30V

TVP
DEPENDING

.J-

4.6~ :J-

ON

\

1.35
V·

DISPLAY

ICM7236

'--

GROUND

36

~G'.'d.,.L

[_~ _____________L<~
l

,

VACUUM FLUORESCENT DISPLAYS (41/2 DIGIT):
1. NEC Electron, Inc.
3120 Central Expressway
Santa Clara, CA 95051
Tel. (408) 241·8222
Model FIP 5F8S

F

,II
~'I _
1.S-2.5VTYP
DEPENDING ON DISPLAY

PHOSPHOR·COATED
ANODES

GRID
DIRECT·HEATED
FILAMENT/CATHODE
GLASS ENVELOPE

ICM7240/50/60
CMOS Programmable
Timers/Counters'
FEATURES

voltage ranges, higher operating frequencies, lower
component counts and a wider range of timing
components. They are intended to simplify the
selection of various time delays orfrequencyoutputs
from a fixed RC oscillator circuit

• Replaces 8240/50/60, 2240 in most applications
• Timing from microseconds to days
• May be used as fixed or programmable counter
• Programmable with staridard thumbwheel switches
• Select output count from
1RC to 255RC (ICM7240)
1 RC to 99RC (ICM7250)
1RC to 59RC (ICM7260)
• Monostable or astable operation
• Low supply current: 115J.LA@ 5 volts
• Wide supply voltage range: 2-16 volts
• Cascadeable

GENERAL DESCRIPTION
The ICM7240/50/60 is a family of CMOS Timer/Counter
circuits intended to replace Intersil's ICL,8240/50/60
and the ,2240 in most applications. Together with the
IGM7555/56 (CMOS versions ofthe SE/NE 555/6), they
provide a complete line of RC oscillators/timers/
counters offering lower supply currents, wider supply

.ORDERING INFORMATION

Each device consists of a counter section, control circuitry,and an RC oscillator requiring an external resistor and
capacitor. For counter/divider applications, the oscillator
may be inhibited and an input clock applied to the TB
terminal. The ICM7240 is intended for straight binary
counting ortiming, whereas the ICM7250 is optimized for
decimal counting or timing. The ICM7260 is specifically
designed for time, delays in seconds, minutes and hours.
All three devices use open drain output transistors, thereby allowing wire AND-ing. Manual programming is easily
accomplished by the use of standard thumbwheel
switches or hardwired connections. The ICM7240/50/60
are packaged in 16 pin CERDIP packages,
Applications include programmable timing, long delay
generation, cascade able Counters, programmable
counters, low frequency oscillators, and sequence
timing .

PIN CONFIGURATION

(OUTLINE DRAWING JE)

"

,

ICM7240,7250, 7260
PART
NUMBER
ICM7240IJE

TEMPERATURE
RANGE
-20° C to +85° C

PACKAGE

., !

7250/60

16 Lead CERDIP

ICM7250IJE

-20°C to +85°C

16 Lead CERDIP

ICM7260IJE '

-20° C to +85° C

16 Lead CERDIP

ICM7240/D

Dice Only

ICM7250/D

Dice Only

ICM7260/D

Dice Only'

10's

1

,
7240
----;-[ r;--'-"7s' p v'
2[

4

4 [3

8

8[4

l6[ 5

12

~o.

32[ 6

11 pTRIGGER

64 [

10

1'"
40

80'

2

7

128[ 8

*7260 OPEN CIRCUIT

6-123

'

~:y N/C (7240)
....... CARRY OUT (7250/60)
. 14
\B I/O'

2

15

P
P
P

13pRC

MOD
RESE,T

9 ~GND

ICM7240/S0/60
ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device'. These
are stress rating~ only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum, rating conditions for
extended periods may affect device reliability.

Supply Voltage .... ,: ......................... 18V
Input "o/tage I1J
Terminals10,11,12,13,14 ..... ,.; ..... GND-0.3Vto
V++0.3V
Maximum continuous output
current (each output) ...................... 50 mA
Power Dissipation 12J ••••••••••••••••••••••• 200 mW
Operating Temperature Range ...... -2{)°C to +85°C
Storage Temperature Range ...... -55°C to +125°C
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting
any terminal to voltages greater thanV+ or Jess than GROUND may
cause destructive device latchup. For this reason, it is recommended
that no inputs from external sources not operating' on the same
supply be applied to .the device before its supply is established, and
that in multiple' supply systems, the supply to the ICM7240/S0/S0 be
turned on first.
2. Derate at -2 mW/oC above 2S~C.

BLOCK DIAGRAM
ICM7240/50/60

MOD < > - - - - - - . , - - - ,

q

RC 1~3-------

SO

">
g:

'"

40

TA '" +7S"C

"...

rt/

60
20

TA '+25°C

.1.-:.1--

:/

I I'
/1 . /

./

L-I-"""

__

/

140
120

,I

-I

160

:>

~

L .....I-""'"

200
~
.:, lS0
I-

/

1

TA"'·20°C

220

V
J

1

1

1

1

1

1

-

RESET MODE

o .I
o

I.

1

!J

10

12

14

16

SUPPLY VOLTAGE (VI

·TIMING CAPACITOR, C (.Ff

TIMEBASE FREE RUNNING FREQUENCY
AS ~A FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH
AS A FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300
_ 1200

E.

TA '" +25°C

1100

~ 1000

~

900
800
70 0
600
500

w

~
~

0:

~

~

v+"16V
.~-

400
300

I-

\ \,1

\.

-,...

200
10o V+=2V
1
0

TIME Bil-SE FReQUENCY.(Hzl

r--

V+=5V

f'...

1
3

S

4.

9

10 .

TRIGGER AMPLlTU'DE (VOLTSI

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE'
AS A FUNCTION OF TEMPERATURE

MINIMUM RESET PULSE WIDTH
ASA FUNCTION OF RESET AMPLITUDE
, .1500

+10.0

~.

1400
1300
1200

i'

ffi

0:

I

/

J=2~

+6, 0

~

+4.0

1;

+2.0

0.0
a , -2.0

5l

-

-4. 0

N

,

\~

.....; ~

ff:

"

R
10kn
lMn
lkn
100kn
10kn

\

·W

+ .l,'16V

r-...

~

iii

1

t<
\

TA =+25°C

+S.O

c

'V+-5V.

b

500
1400
300
200
100
0

o

TA = 2S"C

j.1100
1000
900
3E SO0
~ 700
~ 600

t;

Z

~, -6. 0 - -----"

~ ,.....

......

"

0:

~ ~~

7

9

~"

-S.O
-.10,0
2

10

.....

.....
~, " ~-:: ':-..

10

12

14' 16

SUPPLY VOLTAGE (VI

RESET AMPLITUDE (VOLTSI

6-126

~,

....,~

Z

6

---

100kfl .OlIlF - -

:;;

o

C

.. 001.F--..,.-100pF - - .1.uF
.OOWF---.01.F ~- •••.

lS

20

ICM7240/S0/60
TYPICAL PERFORMANCE CHARACTERISTICS
NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF SUPPLY VOLTAGE
+5

~

z

+3

o
>
u

+1

~

ffi

:::>

S
FE
iil
N

::;

«
~
o

z

R.lOJn~
_

+2

,0

1
-2
3

100M

I
I

+4

o
;::
::!

MAXIMUM DIVIDER FREQUENCY
VB. SUPPLY VOLTAGE*

10M

", ".

·C.O.l"~""

--

-- ~

~C =O.1J.1F

If

1M

+25~C

~

I

I

lOOK

~ ~ ~g~~~~R~~~~~~~ g~~~E-;;TIONS
f:='CIRCUIT FUNCTIONING AS

5V, If'" 15V

-4

f-

I

5

-25

TA '"

RC CONNECTED ::
TO GROUND I
- I--

+25

+50

10K

o

+75

TEMPERATURE ('CI

2

4

6

8

10

12

14

16

18

20

SUPPLY VOLTAGE (VI

OUTPUT SATURATION CURRENT AS A
FUNCTION OF OUTPUT SATURATION VOLTAGE

DISCHARGE OUTPUT CURRENT AS A FUNCTION
OF DISCHARGE OUTPUT VOLTAGE

1....
ffirr

rr
:::>
u

'"
'rr"
«

z

;;;
w

:I:

~

is
0'1'-1-L--'-..L-LLLOLll.l:--l..-i-..l..J...lJ..W.--'-'--J....L..LlWl0·

10

DISCHARGE SATURATION VOLTAGE IV)

OUTPUT SATURATION VOLTAGE IV)

DESCRIPTION OF PIN FUNCTIONS
COUNTER OUTPUTS (pINS 1 THROUGH 8)
Each binary counter output is a buffered "open-drain"
type. At reset condition, all the counter outputs are at a
high, or non-conducting state. After a trigger inp'ut or
when using the internal timebase, the outputs change
state (see timing diagram, .Figure 1). If an external
clock input is used, the trigger input must overlap at
least the first falling edge of the clock. The counter
outputs can be used individually, or can be connected
together in a wired-AND configuration, as described in
the Programming section.

RESET AND TRIGGER INPUTS (PINS 10 AND 11)
The circuits are reset or triggered by positive going
control pulses applied to pins 10 and 11, and once
triggered they ignore additional trigger inputs until
either the timing cycle is completed or a reset signal is
applied. If Doth reset and trigger are applied simultaneously trigger overrides reset. Minimum input pulse
widths are shown in the typical performance characteristics. Note that all devices feature power ON reset.

GROUND (PIN 9)

The period t of the time base oscillator can be modulated by applying a DC voltage to this terminal. The
time base oscillator can be synchronized to an external
clock by applying a sync pulse to pin 12.

MODULATION AND SYNC INPUT (PIN 12)

This is the return or most negative supply pin. It should
have a very low impedance as the capacitor discharge
and other switched currents could create transients.

6-127

ICM7240/S0/60
TIMEBASE INPUTIOUTPUT PIN (TERMINAL 14)
While this pin can be used as either a time base input or
output terminal, it should only be used as an input
terminal if terminal 13 (I~C) is connected to GND.
If the counter is to be externally driven, care should be
taken to ensure that fall times are fast (see Operating
Limits section).
Under no conditions is Ii 300pF capacitor 'on this terminal useful and should be removed if a 7240/50/60 is
used to replace an 8240/50/60 or 2240. '
CARRY OUTPUT (TERMINAL 15,ICM7250/60 ONLY)
This pin will go HI for the last 10 counts of a 59 or 99
count, and can be used to drive another 7250 or 7260
counter stage while still using all the counter outputs
of the first. Thus, by cascading several 7250's a large
BCD countdown can be achieved. '
The basic timing diagrams for the ICM7240/50/60 are
shown in Figure 1. Assuming that the device is in the
RESET mode, which 'occurs on powerup or after a
positive signal on the RESET1ermirial(if TRIGGER is
low), a positive edge on the trigger input signal will
initiate normal operation. The discharge' transi~tor
turns on, discharging the timing capacitor C,and all
the flip-flops in the counter chain change states.
Note that for straight binary counting the outputs are
symmetrical; that is, a 50% duty cycle HI-LO. This is
not the case when using BCD counting. See Figure.3.

Ii] Jl

L

TRIGGER INPUT
ITERMINAL 11)

-

.~__________

•

-'"I-rl""Ir-T-rl""1r-T--r"""T""'""1I"""I-Ir--_ TIMEBASE
OUTPUT
ITEBMINAL 14) )
-

-I

2.

+2 OUTPUT ITERMINAL 2)

I-• +4 OUTPUT ITERMINAL 3)

1--4.--1
-,~_ _....

J,

1.

8.

r

!-_ _ _...

+8 OUTPUT ITERMINAL 4)

1

.~~

;128.---J

+1280UTPUT
ITERMINAL 8; 7240 ONLY)

Figure 1. Timing Diagram for ICM7240/50/60

CIRCUIT DESCRIPTION
The timing cycle is initiated by applying a positivegoing trigger pulse to pin 11. This pulse enables the
counter section, sets all counter outputs to the LOW or
ON state, and starts the time base oscillator. Then,
external C is charged through external R from 20% to
70% ofV+, generating a timing waveform with period t,
equal to 1RC. A short negative clock ortime base pulse
occurs during ~he capacitor discharge portion of the
waveform. These clock pulses are counted by the
binary counter of the 7240 or by two cascaded Binary
Coded Decimal (BCD) Counters in the 7250/60. The
timing cycle terminater when a positive-going reset

pulse is applied to pin 10. When the circuit is at reset,
both the time base and the counter sections are disabled and all the counter outputs are at a HIGH or OFF
state. The carrry-out is also HIGH.
In mosttiming applications, one or more of the counter.'
outputs are connected back to the reset terminal; the
circuit will start timing when a trigger is applied and
will automatically reset itself to complete the timing
cycle when a programmed count is compieted. If none
of the counter outputs are connected back tothe reset
terminal (switch Sl open), the circuit operates in its
astable, or free-running mode, after initial triggering.

PROGRAMMING CAPABILITY
the counter outputs,pins 1 through 8, are open-drain
N-channel FETs, and can be shorted together to a
common pull-up resistor to form a "wired-AND" connection. The combined output will be LOW as long as
anyone of the outputs is low. Each output is capable of
sinking =5 mAo In this manner, the time delays associated with each counter output can be summed by
simply shorting them together to a common output.
For example, if only pin 6 is connected to the output
and the rest left open, the total duration of the timing
cycle (monostable mode) to would be 32t for a 7240
and 20t for a 7250/60. Similarly, if pins 1, 5, and 6 were
shorted to the output bus,the total time delay would be
to = (1 + 16 + 32)t for the 7240 or (1 + 10+ 20)t for the
7250/60. Thus, by selecting the number of counter
terminals connected to the output bus" the timing
c;:ycle can be programmed from: '
11:::; to:::; 255t (7240)
11 :::; to:::; 99t (7250)
11:::; to:::; 59t (7260)
Note that for the 7250 and 7260, invalid count states
(BCD values;:: 10) will not be recognized and the counter will not stop.
The 7240i50/60 can be configured to initiate a controlled timing cycle upon power up, and also reset
internally; see figure 2. Applications for this could
include lawn watering sprinkler timing, pump operation, etc.

BINARY OR DECIMAL PATTERN GENERATION
In astable operation, as shown in Figure 2, the output
of the 7240/50 appears as a complex pulse pattern. The
waveform' of the output pulse train car) be determined
directly from the' timing diagram of Figure 1, which
shows the phase relatiOns between the counter outputs. Figure 3 shows some of these complex pulse
patterns . .The pulse. pattern repeats itself at a rate
eqlJal to the period of the highest counter bit connected to the common output bus. The minimum pulse
width contained in the pulse train is determined by the
lowest counter bit connected to the output.

THUMBWHEEL SWITCHES
While the ICM7240 is frequently hard wJred for a particular function, the ICM7250 and ICM7260 can easily
be programmed using thumbwheel ·switches. 'Standard BCDthumbwheel switches have one common and
four inputs (1,2,4 and 8) which are connected according to the binary equivalent to the digits 0 through 9.

,I 6"-128

ICM7240/S0/60

DIM1fIfiDI!:.
NOTES ON THE COUNTER SECTION

For a single ICM7250 two such switches would select a
time of 1RC to 99RC. Cascading two ICM7250's(using
the carry out gate) wo·uld expand selection to 9999RC.
For a ICM7260, there are standard BCD thumbwheel
switches tor the 0 through 5 digit (twelve position 0 to 5
repeated).

Used as a straight binary counter (19M7240), as a +1 00
(ICM7250), or +60 (ICM7260) all devices are significantly faster than their bipolar equivalents. However,
when using these devices as programmable counters
the maximum frequency of operation is reduced by
more than an order of magnitude. For any division ratio
other- than 256 (fCM7240), 100. (ICM7250), or 60
(ICM7260) the maximum input fr,equ4:lncy must be
limited to apprpximately 100 KHz or less' (with V+equal
to +5 volts). The reason for this is two-fold:

v'
10K

C

50 F

~
":'

r,v+

t...

GND

".-r JL

~ ~

TRIGGER

..

RESET~5K
-'-

':"

.-:'.

OUrpUT

v'lI
GN.:':j f-~

S,
PROGRAMMING BY SOLDER CONNECTIONS
OR THUMBWHEEL SWITCHES
• FOR POWER UP TRIGGERING 1t';'=l85ms) USE CIRCUIT SHOWN
AND OMIT EXTERNAL PULSE.

Figure 2. Generalized Circuit for Timing Applications (Switch Sl
open for astable operation. closed for monostable
operation)

A

2 PIN PATTERNS

a. Since Ripple counters are used, there is ·a
propagation delay between each individual +2
counter (8 counters forthe lCM7240/S0 and 7 forthe
ICM7260). Outputs from the individual +2 counters
are AND'ed together to provide the output signal
and the Reset/Trigger signal.
b. There must be a delay of the positive going output to
the Reset terminal, (pin 10) and the Triggerterminal
(pin 11 ).. The Reset signal must therefore be
generated first, and from this signal another signal
is obtained through a delay network. The trigger
overrides Reset.
..
The delay between Trigger and Reset is generated by
the signal RC network consisting of the 56kO resistor
and the 330pF capacitor.
The delay caused by the counter Ripple delays can be
as long as 2~s (5 v91t supply), and the delay between
Reset and Trigger should be at least 2 ~s. The sum of
these two delays cannot be greater than one-half of the
input clock period for reliable operation. See Figure 4
and 5.
.

.

..1ULJL.fUL Jlll.flJL-.Jl.f

.-l ~ 3. L

.--l ~ ~8'~7.-J
PINS 1 & 4 SHORTED

PINS 1 & 2 SHORTED. - RC
B

3 PIN PATTERNS

v'
10K"

j.-----21.---,----+I

CLOSE
TO INHIBIT
INTERNAL
TIMEBA5E

, PINS 1. 3. & 5 SHORTED

C

4 PIN PATTERNS

.-~~

"So NOT
USED ON
ICM7260

~ ~5~ ~21'~ t5~ ~ ~85'3.

3:

3i

L----~-----~--~OU~UT

PINS 1. 3. 5. & 7 SHORTED

Figure 3~ Pulse Patterns Obtained by Shorting
Various Counter Outputs

Figure 4. Programming.the Counter Section of the ICM7240/50/60

6·129

[I
•

ICM7240/S0/60

OFF

, :,
ON
,OFF
ON

,1...._ _....J

PIN 2

L-_ _ _- - I

. OFF
PIN 3

!-I_ _ _ _ _

!

OUTP~:r (~ESETJ

.

.

n

n

~.I!-i---'-~------- ~,- - - - I

\

Figure 5.

I

f\.

TRI~GER ~

..,
Wavefo'r~s for

I

·ON

1

,)

. '~L-,-

Programmfng the
,

--i~

RESET TO TRIGGER . .
RC DELA': .

Counte~ Section for a Division

.•

.
RESET TO TRIGGER
RC DELAV

Ratio of 7 IS1, S2, S3 Closed)
'

.

.

APpLIGATIONS

I]
.

GENERAL CONSIDERATIONS
Shorting the RC terminal or output terminals to v+ may·
exceed dissipation ratingsand/or maximum DC current limits (especially at high supply voltages). .'

~

10~ding

ICM7240

There is limit of 50pF maximum
on the TB I/O·
terminal if the timebase is being used to drive the
counter section. If higher value loading is used,the
counter sections may miscount.
.

ICM7240 ,

• TRIGGERING CAN BE
OBTAINED FROM A
PREVIOUS STAGE, A
LIMIT SWITCH, OPERATOR SWITCH, ETC.

For greatest accuracy, use timing component values
shown, in the graph under Typical Performance Characteristics. For highest frequency operation it will b~
desirable to use very low yalues for the capacitor;
-accuracy wilf decrease for oscillator frequencies in
excess of 200 KHz.

ICM7240

When driving the coLinter section from an external
. clock, ~he optimum drive waveform is a square wave
with an amplitude equal to supply voltage. If the clock
is a very slow ramp triangular, sine wave, etc., it will be
necessary to "s'quare up" the waveform (rise/fall time ~
1,",s); this can be done by using two CMOS inverters in
series, operating from the same' supply voltage as the
ICM 7240/50/60.

ICM7240

ICM7240

By cascadingdev.ices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages,
numerous sequential, control variations can be obtain'ed. Typical applications include injection molding
machine controllers, phonograph record production
machines, automatic sequencers (no metal contacts
or moving parts), ~illing ma'chine controllers, process
timers, ~utomatic lubrication systems,etc.

S~

t. 1
WAIT
5 SEC.

By selection of Rand C;; , a widevariety/of sequence
timing can be realized. A typical flow chart for a
.
machine tool controller could be as follows:

ENABLE
10 SEC,

WAIT
5 SEC.

. Figure 6,

6·130

t-

COUNT
TO 185

It~
ENABLE
5 SEC.

ICM7240/S0/60
CMOS PRECISION PROGRAMMABLE 0-99
SECONDS/MINUTES LABORATORY TIMER

The ICM7250 is well suited as a laboratory timerto alert
personnel of the expiration of a preselected interval of
time:
When connected as shown, the timer can accurately
measure preselected time intervals of 0-99 seconds or
0-99 minutes. A 5 volt buzzer alerts the operator when
the preselected time interval is over.

The time base is first selected ,with S1 (seconds or
minutes), then units 0-99 are selected on the two
thumbwheel switches S4 and S5. Finally, switch S2 is
depressed to start the timer. Simultaneously the quartz
crystal controlled divider circuits are reset, the
ICM7250 is triggered and counting begins. The
ICM7250 .counts until the pre-programmed value is
reached, whereupon it is reset, pin 10 of the CD4082B
is enabled and the buzzer is turned on. Pressing S3
tu rns the buzzer off.

The circuit operates as· follows:

v+
_ _ _.:.;16,-,-.::.81.....=-='---.

20Mrl

r-_~_~

= +5 VOLTS DC

v+

QUARTZ XTAL = 32,768 Hz

_ _ _ _~11r
330Kfl

14

10

CD4060B

v+

CD40248

4Hz

RESET

27pF

12

1'/2 CD4082B

1 PULSE/MIN

START

v+

-LS2
C>---ltage

VOTS

ISOURCE = 1 mA
ISINK

= 3.2

RC = Ground

VMOD

V+ = 5V

VRST

3.5

V
0.6

V

25

/-LA
V

3.5

= 15V

V

11.0

V+ = 5V

1.6

2,0

V

V+ = 15V

3.5

4.5

V

V+ = 5V

1.3

2,0

V

V+ = 15V

2.7

4.0

50

kfl

1

MHz

Trigger/Reset Input Resistors

RTRIG;
RRST

(pull Downs)

Max Count Toggle Rate

It

V+ = 2V }
,
V+ = 5V
Counter/Divider Mode

,

/-LA

4.2
0.25

mA

ITSLK

V+

Reset Input Voltage

V

Operating, R = 1 Mn. C = 0.1/-LF

(Independent 01 RC Components)

VTRIG'

UNITS

Operating. R =10Kfl,
C = 0.1/-LF
"
,

.~f/~T

, Trigger Input Voltage

16
125

RC Oscillator Frequency
Temperature Drift

Mod Voltage Level

MAX

Reset

Timing Accuracy

Time Base Output
Leakage Current

TYP

2

2

V+ = 15V

V

6

MHz

13

MHz

50% Duty Cycle Input with Peak to
Peak Voltages Equal to V+ and GND
Output Saturation Voltage
Output Sourcing
, Current 7242

VSAT

All Outputs except TB Output
V+ = 5V, lOUT = 3,2 mA

0,22

ISOURCE

V+ = 5V
Terminals 2 & 3, VOUT = 1V

300

MIN Timing Capacitor

Ct

Timing Resistor Range

Rt

0.4

V
/-LA
pF

10·
V+ S 5,5V

100

22M

fl

V+ S 16V

300

22M

fl

TEST CIRCUIT

L--{j,~"'---;]b----OTIMEBASE INPUT/OUTPUT
+2' IRC+21 OUTPUT <>----I[]
+2' IRC ~2561 OUTPUT <>----I[]

Jl..

Jl..

• TIMEBASE PERIOD"" 1.0RC;
1 SEC. = lMQ x lJlF

NOTE: OUTPUTSi-2 1 AND+2 8 ARE INVERTEASANDHAVE
ACTIVE PULLUPS,

6-135

D~DR.

ICM7242
TYPICAL PERFORMANCE CHARACTERISTICS

. RECOMMENDED RANGE
OF TIMING COMPONENT VALUES
FOR ACCURATE TIMING

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
260

j

240
. 220

"<
.=,

lS0

....... '" 1

ztw

160

....... 1-"""

'"::>'"
"...
>-

.~

/

140

./

120

/ / V
1/. /

100
SO

(//

60

'V

40
20
'0

V-

I ..Y

200

100M r--,--,---,--...--.---,----.--,

/

1

TA"-20°C

10M

~

V

1

L-+-

:r

e

1M

..eill

100k

a:

TA' +25°C

",'

1..-1- i""'"
TA = +75°C

a:

1

1

"

z

10k

1

1

:E

1

1

t=

1k

RESET MODE

o

I I

1

10 . 12

14

100'-::--:':-:--:l--'---'-''--,-L_~-:::'~

16

100pF .001

SUPPLY VOLTAGE (V)

TIMING EAPACITOR. C (.F)

DIMENSIONS IN INCHES AND "1ILlIMETERS

MINIMUM TRIGGER PULSE WIDTH
ASA FUNCTION OF TRIGGER AMPLITUDE

TIMEBASE FREE RUNNING FREQUENCY
AS A FUNCTION OF RAND C

1500
1400
1300

TA ""+25°C

'" 1200
.5 1100

~ 1000

III'

c

ii:

w
~

.ffi

::>

""a:
t-

900
SOD
7pO

600
v+ = 16V
500
400
'" =5V
300
\ 1\,,1
200
100 V+"'2V
1
o 1
o 1 2 3· 4 6 6

".......

-,...

TIME BASE FREQUENCY (Hz)

I

i!Z

1

TA =26"C

SDO

1/

~
~C

~w

a

/J'2V

c

500

+6.0
+4.0
+2.0
0.0

~ -2.0
c· -4.0

.=16V

400

TA ""+25°C

+S.O
R
lOkSl
lMSl
lkSl

C

v+ -5V

900

1\

\~

f==.-; ~
..... ~~

~

.-6.0

r:z::

-B.O

2

.3

.4

~

6

7

8

9

10

-10.0
2

~::?~F

8

~

......

:~

"-

~, " ~~ ,~

10

12

14

SUPPLY VOLTAGE (V)

RESET AMPLITUDE (VOLTS)

6-136

_

/

:::;:.

~"
4

::-:.-: _

l00kSl ,01.F - -

:;;

......

!'....

C

,001.F--,--- -

~~~~Sl :~~~~F::-_-_-=

"'" "

w
N

o

.0

9· 10

+10.0

1500
1400
1300
1200
1100
"1000

300
200
100

S

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF SUPPLY VOLtAGE

MINIMUM RESET PULSE WIDTH, .
AS A FUNCTION OF RESET AMPLITUDE

700
600

7

TRIGGER AMPLITUDE (VOLTS)

','
~

16

18

20

ICM7242
TYPICAL PERFORMANCE CHARACTERISTICS
NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF TEMPERATURE

MAXIMUM DIVIDER FREQUENCY'
vs. SUPPLY VOLTAGE
100M

+5

~

z
a

~

~
c

>u

+4
+3

--:;.L

R = lOJn
C= 0.1"':- ......--

+2

+1

~

::>

fil

-1

c

-2

3

-3

e:
w

"a~

-4

Z

-5

V

--

~

~~
C = O.l,uF

";;>-

10M

~

u

~

2ff

=>-~

TA =+25 C

_

Q

RC CONNECTED
TO GROUND
_
1M

II

ffi'

C

;;
C
X
5V<

lOOK

":;;

v+ < 15V

10K

+25

-25

+50

o

+75

TEMPERATURE (OC)

2

4

6

8

10

12

14

16

18

20

SUPPLY VOLTAGE (VI

DISCHARGE OUTPUT CURRENT AS A FUNCTION
OF DISCHARGE OUTPUT VOLTAGE

OUTPUT SATURATION CURRENT AS A
FUNCTION OF OUTPUT SATURATION VOLTAGE

~

~

E

E

I-

i-

~

0:
0:

::>
u

~

0:
0:

::>

z
a

u

"0;Z

~

I

0:

:r+---t-

W

to

0:

"

",.

::>

~

I-

I

l;l

,I

c

~

I-

::>

TA =+25"C

'1

o

10

10

DISCHARGE SATURATION VOLTAGE (V)

APPLICATIONS
.GENERAL CONSIDERATIONS
Shorting the RC terminal or output terminals to V+ may
exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).
OPERATING LIMITS
There is a limitation of 50pF maximum loading on the
TB I/O terminal if the timebase is being used to drive
the counter section. If higher value loading is used, the
counter sections may miscount.
.
For greatest accuracy, use timing component values
shown in the graph under typical performance characteristics. For highest frequency operation it will be
desirable to use very low values for the capacitor;
accuracy will decrease for oscillator frequencies in
excess of 200 KHz.
When driving the counter section from an external
clock, the optimum drive waveform is a square wave
with an amplitude equal to supply voltage. If the clock

OUTPUT SATURATION VOLTAGE (vi

is a very slow ramp triangular, sine wave, etc., it will be
necessary to "square up" the waveform; this can be
done by using two CMOS inverters in series, operating
from the same supply voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose'
principal applications will be very low frequency oscillators and long range timers; it makes a much better
low frequency oscillator/timer than a 555 or1CM7555,
because of the on-chip 8-bit counter. Also, devices can
be cascaded to produce extremely low frequency
signals..
.
Because outputs will not be AND'd, output inverters
are used instead of open drain N-channel transistors,
and the external resistors used for the 2242 will not be
required for the ICM7242. The ICM7242 will, however,
plug into a socket for the 2242 having these resistors.
The timing diagram for thelCM7242 is shown in Figure
1. Assuming that the device is in the RESET mode,
which occurs on powerup or after a positive signal on
the RESETterminal (ifTRIGGER is low), a positive edge
6-137

D~DlL

ICM7242
on the trigger input signal will initiate normal operation.
The discharge transistor turns on, discharging the
, timing capacitor C, and all the flip-flops in the counter
chain change states. Thus, the outputs on terminals 2
and 3 change from high to low states:After 128 negative
timebase edges, the +28 output returns to the high state.

Jl

- - - - - -_ _~___

-

"""T1-r1-rI..."Ir-II--rI"""TI-rI-.rl...,Ir-IIr-"', _

"""TI

R

OUTPUT_"'---{::J

TRIGGER INPUT
(TERMINAL 6)

J~~~~:~~~~TPUT
TRIGGER

~..._ _--:=

TERMINAL 6

-I

-

IIIIIII fflll_'

+2 OUTPUT (TERMINAL 2)
TB OUTPUT

'128/256 OUTPUT

TERMINALS

~UTPUT ~1'TER~'NAL3

(TERMINAL 3) (ASTABLE
. OR "FREE RUN" MOD~'-

, + 1281256 OUTPUT
(TERMINAL 3) (MONOSTABLE
OR. "ONE SHOT" MODE)

Figure 4. Monostable Operation

,COMPARING THE ICM7242 WITH THE 2242

Figure 1. Timing Diagrams of Output Waveforms for the ICM7242.
(Compare with Figure 5)

ICM7242

, To use the 8-bit counter without the timebase, terminal,7
(TB I/O) should be connected to, ground and the
outputs taken from terminals 2 and 3.

c.

d.

Jl11It

- ? 314(11")

fiN

• flN12

I

- " 114(11")

e.
f.

-n

OUTPUTS'{ _ _

"~:

g.

Figure 2. Using !he ICM7242 as a Ripple Counter (Divider)

h.

The ICM7242 may be used for a very low frequency
square wave reference. For this application the timing
components are more convenient than those that would
be required by a 555 timer. For. very low frequencies,
devices may be cascaded (see Figure 3).

2242

2-16V
4-15V
Operating Voltage
Commercial Temp.
-20· C to +75· C O· C to +75· C
Range
Supply Cu~rent
V+ = 5V '
7 mA Max.
0.7 mA Max.
Pullup Resistors
'TB Output
Yes
No
+2 Output
No
Yes
, +256 Output '
No
Yes
a.5 MHz
Toggle Rate
3.0 MHz
Resistor to Inhibit
No,
Yes
Oscillator
Resistor in Series
with Reset for '
Monostable Operation
No
Yes
Capacitor TB
Terminal for
No
Sometimes
HF Operation

a.
·b.

By selection 6f Rand C , a wide variety of sequence
timing can be realized. A typical flow chart for a machine
tool controller could be as follows:'
ICM 7242

~t
\

Figure 3., Low Frequency Reference (Oscillator)

WAIT
5 SEC.

ICM

7~42

~

I t I
ENABLE

WAIT

COUNT

10 SEC.

5 SEC.

T01S5

ENABLE
5 SEC.

Figure 5.

For monostable operation the +28 output is connected
to the RESET terminal. A positive edge on TRIGGER .
initiates the cycle (NOTE: TRIGGER overri~es RESET).
The ICM7242 'is superior in all respects to the 2242 '
except for initial accuracy and oscillator stability. This is
primarily due to the factthat high value p-resistors have
been used on the ICM7242 to provide the comparator
timing points.
"

)

By cascading devices, use of low cost CMOS ANDI OR
, gates.and appropriate RC delays between stages, numerous sequential control variations ca'n be obtained.
Typical applications include injection molding machine
controllers, phonograph record production machines,
automatic sequencers (no metal ,contacts or moving
parts), milling machine controllers, process timers, autoatic lubrication systems, etc.

6·138

ICM7242
SEQUENCE TIMING
• Process Control
• Machine Automation

• Electro-pneumatic Drivers
• Multi-operation (Serial or Par.allel controlling)

SEQUENCE TIMER:
v+

v+

v+
R

33K,

'50K

-=

100PF~

PUSHS, TO START SEOUENCE:

---j

TRIGGER

~ MUST BE SHORTER THAN "ON time,"

.

Jl

~

______________________________
•

I---- 12BRC -----l

;..1------------------.,....-------

OUTPUTA'\

,[
OUTPUTB'

128RC---~·I~-_-~--..:---

I.

------'I

'I

l---I[

1--128RC

---+---~----_+------~----~
OUTPUTe"

1

1

.

--I

r-~~-----

,~I1----:-'28RC~

~o" ---t-~-______t'"-l_~.-_f

OUTPUT 0*

..

Figure 6. '

CHIP TOPOGRAPHY (.068" x .069")
RC
TRIG

RESET
GROUND

+1281256
OUT

.1281256
OUT

6·139

SELECT RC VALUES TO
OESIREO"ON timo"
FOR EACH ICM7242

U~Ull

ICM7555/7556
C'MOS
General Purpose Timers

FEATURES

GENERAL DESCRIPTION

• Exact equivalent In mQst cases for SE/NE555/
556 or the 355.
• Low Supply Current 80~A Typ. (ICM7555)
160~A Typ. (ICM7556)
• Extremely low trigger, threshold and reset
currents - 20pA Typical
• High speed operation - 500 .kHz guaranteed
• Wide operation supply voltage range guaranteed
.
2 to 18 volts
• Normal Reset function ~ No crowbarrlng of
supply during output transition.
• Can be used with higher Impedance timing elements
than regular 555/6 for longer RC time constants.
• Timing from microseconds through hours
• Operates I.... both astable and .monostable modes
• Adjustable duty cycle
• High output source/sink driver can drive
TTL/CMOS
• Typical temperature stability of 0.005% per ° C at
25°C
• Outpuis have very low offsets, HI and LO

The ICM7555/6 are CMOS RC timers providing significantly
improved performance over the standard SElNE555/6 and 355
timers, while at the same .time being direct replacements for
those devices in most applications. Improved parameters'
include low supply current, wide operating' supply voltage
range, low THRESHOLD, TRIGGER andRESE'f currel)ts, no
crowbarring of the supply current during output transitions,
higher frequency performance and no requirement to decouple CONTROL VOLTAGE for stable operation.
Specifically, the ICM7555/6 are stable controllers capable of
producing accurate time delays or frequencies. The ICM7556
is a dual ICM7555, with the two timers operating independently of each other, sharing only V+ and GND. In the one
shot mode, the pulse width of each circuit is precisely con- '
trolled by one ext.ernal resistor' and capacitor. For astable
operation as an oscillator, the free running frequ~ricy and the
duty cycle are both accurately controlled by two external.
resistors and one capacitor. Unlike the regular bipolar 555/6
devices, the CONTROL VOL TAG~ terminal need riot be
decoupled with a capacitor. The circuits are triggered and
reset on falll ng (negative) waveforms, and the output inverter
can source or sink currents large enough to drive TTL loads,
or provide minimal offsets todrive"CMOS loads;

Dlr------:--~~---...,------,
APPLICATIONS

PIN CONFIGURATIONS .(Top View)

• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Generation
•. Pulse Width Modulation
.. Pulse Position Modulation
• Missing Pulse Detector
(OUTLINE DRAWING TO-99)

PRDERING INFORMATION
iEsiT

4

1...-_---1

7

'DISCHARGE

6

THRESHOLD

5

~g~f:3~

(OUTLINE DRAWING PA)
ORDER.
PART NUMBER

TEMPERATURE'
RANGE

ICM7SljSIPA
ICM75551TY
ICM7555MTY
ICM75561PD
ICM7556MJD

-2010+8SoC
-20 to +85°C
-55 to +125°C
. -20 to +8So C
.-S5 to +125°C

ICM7555/D
ICM75S6/D

PACKAGE
DISCHARGE
THRESHOLD'

8 Lead MiniDlp
TO-99 Can
TO-99 Can
14 Lead Plastic DIP'
14 Lead CERDIP

2

CONTROL
VOW!!!

12 THRESHOLD

4

11

OUTPUT

5
8

10

'iiiGGii

DICE
DICE

.

RES5T

~g~j:3~
iiiiiT

(OUTLINE DRAWING JD, PO)

6-140

,UIM1J1fiUI!:.

ICM7555/ICM7556
ABSOLUTE MAXIMU!'II RATINGS (NOTE 1)

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device, These
are stress ratings only. and functional op,eration olthe device
at these or any other conditions above those indicated in the
operational sections of the'speciiications is hot implied,
Exposure to absolute 'maximum rating conditions ,for
extended periods may affect device reliability.

Supply Voltage ...•..••....•......•........... +18 Volts
Input Voltage Trigger ~
, '
Threshold ••..• :5 V+ + 0.3V ,to;::: V- - 0.3V
Reset
'
Output Current Control Voltage ...............•.. 100mA
Power Dissipation l21 ICM7556 .••.........•...• 300mW
ICM7555 ................. 200mW
Operating Temperature Range 121
ICM75551PA ....•..•....-20°C to +85°C
ICM75551TY ....••..••..-20° C to +85° C
ICM75561PD .•...•.... : .-20° C to +85° C
ICM7555MTY ......... -55°Cto+125°C
ICM7556MJD ......... :55°C to+125°C
Storage Temperature ..•..•....•......• -65°Cto+150°C
Lead Temperature (Soldering 60 Seconds) ••.•.... +300° C

OPERATING CHARACTERISTICS (TA = 25°C, V+= +2 to +15 Volts.unless other specified)

..

PARAMETER

VALUE
TEST CONDITIONS

SYMBOL

MIN

TYP

MAX

UNITS

18
16

V
V

Supply Voltage

V+

-20~C oS TA oS +70° C
-55°C oS TA oS +125°C

Supply Currentl 3!

1+

ICM7555

V+= 2V
, V+= 18V

60
120

200
300

JJA
JJA

ICM7556

V+= 2V
V+= 18V

120
240

400
600

JJA
JJA

RA, RB = 1k to 100k.
C=O,lJJF
Note 4
Note 4
'.

S\! oS V+ oS lSV
2.0
SO

5.0
200
300
60a

Timing Error
Initial 'Accuracy
Drift with Temperature

2
3

V+= SV
V+= 10V
V7= lSV

v+= SV

Drift with Supply Voltage
Threshold Voltage

VTH

Trigger Voltage

VTRIG

Trigger Current

ITRIG

V+-18V
V+= SV
V+= 2V

Threshold Current

ITH

V+-18V
V+= SV
V+= 2V

Reset Current

IRST

VRESET = Ground

Reset Voltage

VRST

V+= 18V
V+= 2V

Control Voltage Lead

Vcv

Output Voltage Drop

Vo

1.0

3.0

V+

0.63

0.66

0.67

V+

0.29

0.33

0.34

-

V+= 18V
\i+= SV
V+= 2V

V+
Output Lo

V+ -18V
V+= SV
V+= 18V
V+= SV

Rise Time of Output

tr

RL=10MO

CL= 10pF

ISINK - 3.2mA
ISINK = 3.2mA
ISOURCE = 1.0mA
ISOURCE = 1.0mA
V+=SV

Fall Time of Output

tf

RL= 10MO

CL = 10pF,

V+=SV

Guaranteed Max Osc Freq

fmax

Astable Operation

Output HI

%
ppm/oC
;

%IV
V+
V+

SO
10
1

pA
pA
pA

SO
10
1

pA
pA
pA

100
20
2

pA
pA
pA

0.4
0.4

0.7
0.7

1.0
1.0

0.62

0.66

0.67
0.4,
0.4

4.0

0.1
O.lS
17.8
4.5

V
V
V
V

3S

40

75

ns

3S

40

7S

17.25

SOO

V
V
V+

ns
kHz

NOTES:
,
"
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal toa voltage greater than V+
+0.3V or less than V- -{).3V may cause destructive latch up.
For this reasen it is recommended that no inputs from external sources not
operating from the same power supply be applied to the device before its power supply is established.
In multiplesystems, the supply of the
ICM7555/6 must be turned on first. .
2. junction temperatures should not exceed 135°C 'and the pow1r dissipation must be limited to 20mWat 125°C. Below 125°C power
dissipation may be increased to 300mW at 2SoC., Derating factor is approximately 3mW/oC (75S6) or 2mWI'C (7S5S).
'
3. The supply current value is essentially independent of the TRIGGER. THRESHOLD and RESET voltages.
4. Parameter is not 100% tested, Majority of all units meet this specification.

6-141

ICM7555/ICM7556
TYPICAL CHARACTERISTICS.
MINIMUM PULSE WIDTH
REQUIRED FOR TRIGGERING
1200

'I
I

1100
~1000

-

TA =-25°C

900

~

I

.00

i

:>

300

i

ill

,.

Y+-2V

-

200

~

300

I-

ffi

100

§

80

"

60

t
iil

a

10

V-

40
20

~

/,1-

v-=15VI-.

-

/
/

ifi
a:

~.

V- 2V

o

"iiiz

1.0

~,

.

~
o

r

/

4

1.0

-.

Z

;:
C

s:w

1.0

V

o. ,~
0.01

iY((

l-1,O
•. ~ "'0.9

~ "'0.8

.~
o

l:i
i5

:>

"'0.7
-0.6

~O.5

~ ... 0.4

a:

.... -0.3

o·

~ -0.2

,.a:~
o
z

II
1.0

oon

0.01

1.0F

.\
.\

~

V+:::: 2V

-0.1
-20

I I

+20
+40
TEMPERATURE °C

+60

0.1
1.0
DISCHARGE LOW VOLTAGE VOL

TA = 25·C

.......... .........

lnF
100pF

./
1.0

V-+=2V

1/ /
/

/

0.1
0.01

10.0

V-+=SV

5'00

400

"0z

300

".

200

I
I
TA

!J
+70 G e

/.
V

TA - +2S G C
20'C
TA

'/J

1.

o
10
20
30
40
LOWEST VOLTAGE LEVEL OF'Tii'iGGiii PULSE (Oft V+)
TIME DELAY IN THE MONOSTABLE
MODE AS A FUNCTION OF RA AND ~

I

lmF

10#L F

'Oo~


0

......... .........
.......... ......... .........

10~F

,"F

~

J'=18v!i'

C

"

100~F

V·
/ V

I--

w
a:
a:

.;:

V·=2V

~ f;;;~t ~ dRB)

lmF

Y+ ="sV.

7'" ~=5V

£

:lw

I

10mF

\\1\
\,\
~['"

"'0.1

,

FREE RUNNING FREQUENCY AS A
FUNCTION OF RA, Rsand C
100mF

'.-

,

TA - 70 0 e

S

o.

0.1

I O'I"F

-100

OUTPUT SINK CURRENT AS A .
FUNCTION OF OUTPUT VOLTAGE

a:

100.0

C =

o

I·;.

, / I-'"""

C

RA = Re :: 10kU

:--

5

:>

.00

v- 5V

V

:I:

NORMALIZED FREQUENCY STABILITY
IN THE ASTABLE MODE AS A .
FUNCTION OF TEMPERATURE

~

V-+=18V

on

10.0

./

c

III

-:

Ill.

'"
V"

o
"z
~

1.0
10.0
SUPPLY VOL TA~E (VOLTS)

-10.0m

~
o.

~

/

in

\

"a:w
":>o

/

:>.

"iiiz

V"'-18VY

w

RA = Re "" 10kl!

w
a:
a:

DISCHARGE OUTPUT CURRENT
AS A FUNCTION OF
DISCHARGE OUTPUT VOLTAGE

:>

~

,

a:

:>

V

a:

C :: lQOpF

l-

2V-

0.1
1.0
OUTPUT LOW VOLTAGE VOL

~ 10.0

RA :: As :: 10M'o

-1.0 ~

V+ SV

Z

5o

!Z

"-

f

/

/

~ 10.0

V

<
S·

\

I

v-

10.0

I\

!Z

.<

VL

TA = 25°C

-4

g

...

100

r- ~=~~-

:>

100

0

V· 2V.......

20

/

TA'I= 25°

-6

16 18

.-Vtll

o

NORMALIZED FREQUENCY STABILITY
IN THE ASTABLE MODE AS A
FUNCTION OF SUPPLY VOLTAGE

0

12 14

/

OUTPUT LOW VOLTAGE VOL

!

10

a:

~
o

0.1

8

Y+=18V

5

0.1
0.01

~

-

0

120

4D

I II

TA = 25·C

<
s
.2I- 10.0

"iiiz

i·/

~+7r·C

200
'.0

.0

6

ifi'
a:
I-

TA'" +25°C

s<

1

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
10 0

'--

....

-G.l

/ 1/

TA = 25°C'

SUPPLY VOLTAGE (VOL T~)

I

!V"'=18Y

.Y

OUTPUT VOLTAGE REFERENCED TO, Y+
-10
-01
-001

-10

I I
2

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

.21-" 10.0

240

I)

~

TA:' -20°C

I-"

,JI-"

LOWEST VOLTAGE LEVELOF iii'i'GGEii"PULSE (OlaV"')

100

- --

280
TA= -20°C

,/

I

o

320

120

~

Y+=1BV

100

180

a:

LW

I~ A
v+_sv

400

~ 140

g

I.
VIJ·

:> 400

200

,.0

::!

18

500

Z

:c

liD

700

w
~ .00

,.o.
,.

I

OUTPUT SOURCE CURRENT AS A .
FUNCTION' OF OUTPUT VOLTAGE

SUPPLY CURRENT AS A
·FUNCTION OF SUPPLY VOLTAGE

1pF 100
nl

IJ'/ . / V V
II /' . / V
1

10

#LI

#LI

100

1

10

100

/.II

ml

ml

ml

TIME DELAY

V
V
V
V
,/

10

s

D~O\!"

ICM7555/ICM7556

v·

APPLICATION NOTES
GENERAL
The ICM7555/6 devices are, in most instances, direct replacements for the NE/SE 555/6 devices. However, it is possible to
effect economies in the external component count using the
ICM7555/6. Because the bipolar 555/6 devices produce large
crowbar currents in the ,output driver, it is necessary to decouple the power supply lines with a good capacitor close to the
device. The 7555/6 devices produce no such transients. See
Figure 2.

10K

OUTPUT

0....--1----"

500
TA=25°C
400

"~
...z
'"a:

300

F!gure 3: Astable Operation

1\

MONOSTABLE OPERATION

VSEINE555

~ 200

In this mode of operation, the timer functions as a one-shot.
Initially the external capaCitor (C) is held discharged by a
transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip flop is set which
releases the short circuit across the external capaCitor and
drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t = RAC.
When the voltage across the capacitor equals 2/3 V+, the
comparator re~ets the flip flop, which in turn discharges the
capacitor rapidly and also drives the OUTPUT to its low
state. TRIGGER must return toa high state before the OUTPUT can return to a low state.

\

(J

..
>~

~ 100

I'CM7555156

U)

I

200

400
TIME -"s

600

600

Figure 2. Supply Current Transient Compared with
Standard Bipolar 555 During an Output Transition

a:

t'" O.69RC

V+

The ICM7555/6produces supply current spikes of only 2-3
mAinstead of 300-400 mA and supply decoupling is
normally not necessary. Secondly, in most instances, the
CONTROL VOLTAGE decoupling capacitors are not
required since the input impedance of the CMOS
comparators on chip are very high. Thus, for many applications 2 capacitors can be saved using an ICM7555, and 3
capacitors with an ICM7556.

RA

6 THRESHOLD'
-CONTROL
5 V21J~GE

I
I

V+:5. 18V

.J..

OPTIONAL
CAPACITOR,

--'--

I

POWER SUPPLY CONSIDERATIONS
Figure 4: Monostable Operation

Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply can be high
unless the timing components are high impedance.
Therefore, use high values for R and low values for C in
Figures 3 and4.

CONTROL VOLTAGE
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or
even inhibition of oscillation, depending on the applied
voltage. In the monostable mode, delay times can be
changed by varying the applied voltage 'to the CONTROL
VOLTAGE pin.

OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply
voltages will equal the supply voitage.At a supply voltage 'of
4.5 volts or more the ICM7555/6 will drive at least 2 standard
TTL loads.
.

RESET
The RESET terminal is designe,d to have essentially the same
trip voltage as the standard bipolar 555/6, i.e. 0,6to 0,7 volts, At
all supply voltages it represents an extremely high input impedance, The mode of operation of the RESET function is, however"much improved over the standard bipolar 555/6 in that it
controls only the internal flip flop, which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins,
This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices,

ASTABLE OPERATION
The circuit can be connected to trigger itself and free run as a
multivibrator, see Figure 3. The output swings from rail to rail,
and is a true 50% duty cycle square wave. (Trip points and
output swings are symmeirical). Less than a 1% frequency
variation is observed, over a voltage range of +5 to +15V.

_

1

f -:- 1.4 RC

6·143

O~OIL

ICM7555/ICM7556
'EQUIVALENT CIRCUIT

I

THRESHOLD

o

CONTAOL
VOLTAGE

n

.
.
OUTPUT

'1iND

BLOCK DIAGRAM
V·

8

O~TPUT
DRIVERS

rHRESHOlD
60---~+-I

""_I ....

5 0 - - - -...

~ OUTPUT

CONTROL
VOLTAGE

Dl

COMPARATOR

B

This block diagram reduces the circu'itry down to its simplest equivalent components,
Tie down unused inputs,
R = lOOk!}, ± 20% typ,

TRUTH TABLE

THRESHOLD
VOLTAGE

TRIGGER
VOLTAGE

DON'T CARE DON'T CARE
>2/31/3(V+)

1/3
o

2.5

-

DiUBLjR

-

2.0
0.0

:---..

~+-ll.55lN i""-- r-....
:---..

V+""'1.2V

.y

=t55~

V+ DOUBLER = 1.2V

0.8

1.6

2.4

OUTPUT CURRENT

'2 ",A)

1.7

VOLTAGE DOUBLER EFFICIENCY
AS A FUNCTION OF OUTPUT CURRENT

4.5

!:i

1.6

1.5

SUPPLY VOLTAGE IVOLTS)

VOLTAGE DOUBLER OUTPUT VOLTAGE
AS A FUNCTION OF OUTPUT CURRENT

~ 3.5

1.4

1.2

SUPPLY VOLTAGE IVOLTS)

g

.......

3.2

-

80

4.0

0.0

0.8

1.6

7·7

3.2

2.4

OUTPUT CURRENT

'H

I.,A)

4.0

n~olb

ICM1424C/MC

, , , .,.- .-. ,ICJ'JLt
., ., "

DISPLAY FONT NUMBERS

IC~'~O
DISPLAY CONNECTION
1

,,/ I
(
I
I K I
(.

I

(

; I

i

/'1

I

I

I

I

~

I

,

I

"

I

I

I

,)

I

161 I

I

I

l

I

L-::--------...::'J
Gl
>
....
"" ..... '"
/.........
- - --- (/ /

" I

I

) '----/(

I Fl' I

I

I

",--------7 A
Al
/~/ /

" ',',

I

I

:;I

/

I

I

I

I El I

).....----"

__~1

t/:~/

_ _

Cl I

,--'

I COL I
,
I

L ___ -'

r---'
: COL / L __ .-l

I

~~'J

NORMAL OPERATION

2SEC LATER

I

b'c'~)

RUNI

COLON:

TIME

MONTHI
DATE

FLASHING

OFF

PRESS
DISPLAY
ONCE

0)
...) oJ
( ......
SECONDS

PRESS
DISPLAY
ONCE

II-"Y'),
( IL"
TIME

DISPLAY

IX
FLASHING

ON

PRESS
SET
ONCE

Bc~)

RUN2
TIME
COLON:

ON

MONTHI
DATE
OFF

Two modes are provided for normal operation, the RUN
1 and RUN 2 mode, selectable by the userusingtheSET
switch. In either mode only the DISPLAY switch is used
to address the watch.

PRESS • (
DISPLAY
ONCE

.':)0)
...)_'
SECONDS

ALTERNATING
CONDITION
PRESS
DISPLAY
ONct'

ON

RUN2
This mode allows 'hands off' viewing-of both time and
month/date by cycling every 2 seconds between the
'TIME' mode (colon on) and 'MONTH/DATE'. Each
display stays on for 2 seconds, therefore the user can
always see the information he needs in less than 2
seconds. On the other hand this rate is slow enough to
give a non-irritating display. If the DISPLAY switch is
activated, the circuit will switch to the 'SECONDS'
mode, which will remain on until turned off by the user.
Note that in the 'SECONDS' mode RUN 1 AND 2 are
indistinguishable. To return to RUN 1 frolTi RUN 2 it is
necessary to cycle through the SET modes. Press SET 5
times.

RUN 1
The circuit is normally in the 'TIME' mode with the
colon flashing.
Upon activating the DISPLAY switch, the circuit enters
the 'MONTH/DATE' mode. The timer starts after release of the switch and2 seconds later returns to the
'TIME' mode. If the DISPLAY switch is activated again
during 'MONTH/DATE', the circuit Elnters the 'SECONDS' mode. It will stay in this mode until the
DISPLAY switch is activated again. Seconds are
displayed in the minutes position.
7·8

ICM1424C/MC
SETTING OPERATION
RUN 1

·Selected counter advances one with each push of the DISPLAY button or at a 1 Hz rate if OJ'SPLAV held down.

Setting the ICM1424C/MC is carried out in a sequential
manner. The SET input allows the user to cycle
through two run modes and four set modes.lneach set
mode the DISPLAY input is used to advance the
counter being set either by one count per push or'at a 1
Hz rate if the DISPLAY switch is held down
continuously. All set operations are independent, i.e.
the counters following the one being set are inhibited;
this allows convenient time zone adjustment without
affecting date or month.

1OOJLF low'voltage capacitor should be connected across
the battery terminals; this allows about 20 seconds for
battery replacement.

OSCILLATOR
The osci Ilator of the I CM 1424C/MC is desig ned for low
frequency operation at very low currents from a 1.3 to
1.8 volt supply. The oscillator is of the inverter type with
a non-linear feedback resistor having a maximum
resistance under startup conditions included on chip.
The nominal load capacitance of the crystal should be
less than 1SpF, typically 12pF. In specifying the crystal,
the motional capacitance, series resistance and tuning
tolerance must be compatible with the characteristics
of the circuit to insure startup and operation over a wide
voltage range under worst case conditions. On chip
oscillator capacitor"" 25pF.

DATE SET
The perpetual calendar uses 28 days for February. In a
leap year, on February 29, the watch will display March
1. To display February 29, change date to 29 fi rst, then
March to February.
HOURS SET

The following expressions can be used to arrive at a
crystal specification: Tuning range

The ICM1424C/MC is intended for use with a display
without AM/PM flags and shows an A in the minutes
units position for AM and a P for PM.

df

f

MINUTES SET
The 'MINUTES SET' mode is used for exact
synchronization of the watch as well as for setting the
minutes. If the DISPLAY switch is not activated during
'MINUTES SET', neither seconds nor minutes will be
affected and the next activation of the SET switch will
return the circuit to the RUN 1 time mode with flash'ing
colon. If the DISPLAY switch is used in the 'MINUTES
SET' mode, the minutes will advance and the seconds
counter is reset to 00 and put on hold. The user now
advances to the next minute and pushes the SET
switch once. The circuit is now in a TIME HOLD mode,
showing hours, minutes and colon (not flashing). while
the seconds are still held to 00. At the tone of the time
signal push the DISPLAY switch. This will cause the
watch to display month/date and back to time, while
the seconds will start running at the time the switch is
activated. Time setting accuracy is approximately 0.1
seconds.

APPLICATION NOTES
SYSTEM CONSIDERATIONS
The ICM1424C is designed to be mounted onthe same
side of the board substrate as the display; the
ICM1424MC is designed to be mounted on the backside of the board. The switches used for the watch
should be SPST connected to V+. The total system
power consumption is sufficiently low that it is possible
to replace the battery without loss of timekeeping. A

=

Cm
CIN COUT
2 (Co + Cli ; Cl = CIN + COUT

gm required for startup
gm = 47T 2f2 CIN COUT Rs [ 1 +
here

~~ ]

2

Rs = Series Resistance of Crystal
,.
f = Frequency of the Crystal
At = Frequency Shift from Series Resona,nce
Frequency
Co = Static Capacitance of Crystal
CIN = Input Capacitance
COUT = Output Capacitance'
Cl = Load Capacitance
Cm = Motional Capacitance of Crystal

The gm required for startup calculated should not
exceed SO% of the gm guaranteed for the device.
TEST POINT AND DISPLAY TEST
. The circuit is reset to a known state by connecting
SET, DISPLAY and TEST . to V+ .. This state is
December 1, 12:00 a.m., in the RUN 1 mode. The TEST
input, when connected to V+ causes the circuit to
speed up the seconds by 128 times, while inputs can
then be applied at a rate of up to SOO Hz. The test point
allows automatic testing of the device in a very short
, time.

7·9

ICM1424C/MC
CHIP TOPOGRAPHY

o

20

80

100
F3

80

ICM1424C

60

Bl

BOND PAD SIZE" 5)(5 MILS

119

IN

-c-t-----t-c-t--

100

80

ICM1424MC

60

40

0-+--=
BOND PAD'SIZE" 5x5 MILS

7-10

104

U~U[b

ICM7038B/D/E/G
CMOS Analog Quartz
Clock Circuit
Synchronous Motor Applications

FEATURES

GENERAL DESCRIPTION

• Single battery operation: 1.2 to 1.8 volt operation

The ICM7038 family of synchronous motor drivers is
desiQned to operate from a 1.5V battery, and performs
the functions of oscillator, frequency divider and output driver. In addition a power driver is tapped off from
the thirteenth divider for use as an alarm driver.
Specifically the 'ICM7038 family uses an inverter oscillator having all biasing components on chip. Binary
dividers permit frequency division from 4 MHz down to
64 Hz (ICM7038B). The output from the divider network
drives a bridge output circuit which provides a.50%
duty cycle AC square wave having virtually zero DC
component for driving a synchronous single phase
motor. The total output driver saturation is typically
200 ohms providing efficient operation of synchronous
motors. The alarm output will drive a transducer (piezoelectric or speaker).

• Very low power: 30J.LA typical
• High output current drive: 1 mA minimum
• Zero output bridge DC component (50% duty cycle
square wave)
• All inputs fOlly protected - no special handling
precautions required
.
• Wide temperature range: -20 0 C to +70 0 C

TABLE OF OPTIONS
The ICM7038 may be modified with alternative metal
masks to provide any number of binary divider stages
up to a·maximum of19 together with various output
options. Consult your Intersil representative or the
factory for further information. The alarm output can
be tapped off from any of the latter divider stages.
(See table for,standard options).

Part Number

Binary Dividers

Output Frequency
(50% Duty Cycle
Square Wave)

ICM7038B
ICM7038D·

16

64 Hz

17

32 Hz

ICM7038E

18

16 Hz

ICM7038G

19

8 Hz

ORDERING INFORMATION

PIN CONFIGURATION
(OUTLINE DRAWING PAl

----...r-

v+ [L •

L

~l~Bb·

I1 asc IN

L = '

v- [ [

ro

OUT 1 L..!.
OUT 2'

leM
7038 .
B/O/E/G

CI:

] ] asc OUT
-;;;
....!.J NC

.•

.

.

IP. A = 8 PIN fLASTIC DIP)
I = TEMPERATURE RANGE

:[] ~LARM OUT

INDUSTRIAL:
-20to+70°C

.
,

TOP VIEW

PACKAGE

ELECTRICAL OPTION

I

TVPE

PIN liS DESIGNATED BY EITHER A DOT OR A NorCH.
ORDER DEVICES BY FOLLOWING PART NUM8ER'ICM703BB I PA

ORDER DICE BY FOLLOWING PART NUMBERICM7038C/O

7·11

O~Oll

ICM1038B/D/E/G
TEST CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Power Dissipation Output Short eircuit[l] • 0 0 300mW
Supply Voltage 00000000 00 000 . 0 0 0 0 0 00 . 00 0 0 0 000 0 0 3V
Output Voltage[2] 000000 0 0 0 000 0 0 0 0 0 . 0 0 0 0 0 0 0 0 000. 3V
Input Voltage[2] 00 .. 0 0 0 0 0 0... 0 . 0 0 00 0 0 0 0 0 0 0 0 0.. 0 0 3V
Storage Temperature 0;' 0 0 0 0 0 0 0 0 0 0 -30 o e to +125°e
Operating Temperature 000000000000 -20 o e to +70 o e

. QUARTZ CRYSTAL PARAMETERS
f = 4,194,304 Hz

RS= 35U
Cm =10mpF
Co = 305 pF

v+

ORV-

~g~j!
NOMINAL
VALUE

NOTE: Stresses above those' listed under "Absolute Maximum
Ratings" may cause permanent device failure. These 'are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the·
operation sections of this specification is not implied.
Exposure to absolute maximum .rating conditions for
extended periods may cause device failures.

SINGLE PHASE
64 Hz
SYNCHRONOUS
MOTOR

'512 Hz
50% DUTY CYCLE
SIMULATED ALARM LOAD

NOTES:
1. This value of power dissipation refers to that of the package and will not be obtained under normal operating conditions.

2. Except for instantaneous static discharges all terminals may exceed the supply voltage (2.0V max) by ±O.S volt provided that thll
currents in these terminals are limited to 2 mA each.

TYPICAL OPERATING CHARACTERISTICS
(V+

= 105V, fosc = 4,194,304 Hz test circuit 1, TA = 25°C,
Symbol

Parameter

unless otherwise specified)

Conditions

Min.

1+

Supply Current

Guaranteed Operating Voltage Range V+

-20°C::::; to:5 70°C

Total Output Saturation Resistance

RSAT

p+n Output Transistors,
lOUT = O.SmA

Alarm Output Saturation Resistance

RAL

lOUT = 1mA

Oscillator Stability

fSTAS

1.2V < V+< 10SV
CIN = COUT = 1SpF

tstart

V+ =1.2V

Oscillator Start-Up Time

~:

v+

los\1

ALARM~
OUT
I

v+~
Ql

64Hz

OUT1

V-

3

ALL ZENER DIODES HAVE TYPICAL
BREAKDOWN VOLTAGES OF,7 VOLTS

P

,

Q2

v-

N

64Hz

7·12

p.A

1.B.

V

200

700

300

BOO

n
n
ppm

1.0

v+

512 Hz

Unit

SO

1

v+

v-

Max.

30
1.2

SCHEMATIC DIAGRAM (ICM7038B)

v+

Typo

sec

ICM7038B/D/E/G
TYPICAL OPERATING CHARACTERISTICS
ALARM OUTPUT CURRENT (SOURCE) VS.
OUTPUT SATURATION VOLTAGE

SUPPLY CURRENT VS. SUPPLY VOLTAGE
140

'CRVSTAL'PAAAMET~RS

/

PER TEST CIRCU!T PAGE 2

120
~
0

E
f-

80

illa:
a:

::>

"

.60

::>

40

/""

'"

~

V

f-

illa:
a:

::>

--

~
20

-2 ~------+-------~----~F-~+-~

!

/

>

~

V

d,N/coJr::: 10JfJOPF
:/

100

.3

o

-4 ~------+-----~~~--~~----~

"
f-

'~~ ~10PF

irf:>

o

.-6 ~-------I-::::_~--~------~----~
Voo:> 1.65V

~~

1.2

1.5

1.8

____- L______

-2

~

____

~

____

~

-1

SUPPL V VOL TAGE

ALARM OUTPUT SATURATION VOL-TAGE

OUTPUT CURRENT (SOURCE) VS.
OUTPUT SATURATION VOLTAGE

OSCILLATOR STABILITY VS. SUPPLY VOLTAGE

-1

-2

TA'" 2S"C
P·CHANNEL TRANSISTOR
lQl OR 031

CRVSTAL PARAMETERS

PER TEST CIRCUIT PAGE 2

~-----r------~--~~~~--1-4
1.2V

0

~

f-

illa:

v+ '"

a:

n

1.8V

12~------~------f-----~~----~-12

::>

"

~_-+

~

'""

III0

!!

1.0

-1

-2

_ _ _+-_1.2V

- ---

1.5

6

a:

f ""

",VOO'" 1.6SV

•

5

.........,

:>

~

"
f-

~

VOO

I'

f-

il

=

1.5V

w

"a:o

>

'\. \

~
iil

'\ \
\ 1\

'" "\

15pF/15pf
JOpF/l0pF

SUPPLY VOL TAGE

BRIDGE OUTPUT CURRENT VS.
BRIDGE OUTPUT VOLTAGE

!

V

..-/

1.3

2.0

OUTPUT SATURATION VOL TAGE

8

/"

30/10

f-

3'

___-t"SV

10PF/30~

./

:i
iii

...z

f-

::>

o

CINfCOUT =

>
f-

C
1I
1I

m

N·CHANNEl TRANSISTOR
(Q2 OR Q41

f-

~

I-:;

c
:;I
c...

!

1\\

1.0

, ,

a

. 2.0

---

1.0

-40

-20

+20

TEMPERATURE

BRIDGE OUTPUT VOL TAGE

7·13

+40
t~CI

'

-...

+60

+80

ICM7038B/D/E/G
APPLICATION NOTES
GENERAL DESCRIPTION
The ICM7038 Family has been designed primarily for
· quartz clock and timer applications using oscillator, .
frequencies between 2.0 and 10 MHz. The design
objectives were exceptional oscillator frequency
stability, very low power, wide supply voltage range
and wide temperature range. The oscillator contains all
components except the tuning components and quartz
crystal. Three outputs are provided. The two principal
outputs are intended to be used to drive a single phase
synchronous motor in a bridge configuration. As such,
because of the matching of the transistors in the two
outputs, the output DC component is extremely small.
Stepper motors may also be used by placing a
capacitor in series with the motor and using either a
single output or the bridge output.

feedback resistor is provided on chip, which has a
maximum value' at start up. Oscillator tuning should be
done at the oscillator output.
The following expressions can be used to arrive at a
crystal specification:
Tuning Range
Ilt =
f

OR

o-j

OR

Vss

C' - CINCOUT
L - CIN+COUT

gm required for startup

,gm

· Voo

Cm
2(Co +CL)

( C)2
C~

= w2 CINCOUT Rs 1 +

Rs
f
Af

= series resistance of the crystal
= frequency of the crystal
= frequency shift from series resonance
frequency
Co = static capacitance of the crystal
CIN = input capacitance
COUT = output capacitance
CL
= load capacitance
C m = motional capacitance
w
= 217"f

The resultinggm should not exceed 50 tLmhos
· Alternatively outputs 3 and 4 may be used tei drive TTL
logic directly for timer applications.
.
The alarm output is taken' from the outpLlt of the
thirteenth divider and can source 1 mA at a low
saturation voltage.

2VMAX
1·12MHz

g

The ICM7038 mey be ",ed " a ""'gh' di,lde' by
driving directly into the oscillator output (pin no. 7)
with a low impedance square wave drive; As such it
may be used over the frequency range 1 MHz to 10
MHz.
.

OSCILLATOR CONSIDERATIONS
The oscillator of the ICM7038 is designed to 9P.erate
with crystals having a load capacitance of 10 to 12 pF.
This allows nominal capacitor values of 15/15 pF or
'·20/20 pF. I ncreasing the load capacitance of the crystal
requires larger oscillator 'device sizes, which causes
the supply current to increase, Modifications to the
oscillator can be made on a custom basis. The tuning
· range can be increased by using crystals with lower
load capacitances, however, the stability may decrease
somewhat. This can be counteracted by reducing the
motional capacitance of the crystal. A non-linear

7-14

ICM7045/A
CMOS Precision
Decade Timers
FEATURES

GENERAL DESCRIPTlqN

• Total integration: includes oscillator, divider,
,
decoder driver on chip ,
• Wide operating supply range: 2.5V:::;V+ :::;4.5V
• Low operating power consumption:
0.9 mW @ 3.6V supply with display off
• High output current drive: 18 mA peak current
per segment with 12.5% duty cycle.
• Leading zero suppression: timer stopwatch
'applications
• Fractional second suppression: 24·hour clock
application
• Short duration short circuit protection on all
inputs and outputs at 3.6V supply

The ICM7045/A are fully integrated precIsion d~cade
timers fabricated using Intersil's low voltage metal gate
C·MOS technology, The oscillator, frequency divider,
multiplexer, decoder, segment and digit output buffers are
all included on·chip, The circuits are designed to interface
directly with fully multipl~xed B',digit 7·segment common
cathode LED displays. The normal supply voltage is 3.6V,
equivalent to a stack of three nickel cadmium batteries.

The ICM7045
The ICM7045 divides the oscillator frequency in sixteen
binary stages 'to a freq,uency of 100 Hz; some of these
intermediate outputs are used to generate the multiplex
waveforms at a 12.5% duty cycle/BOO Hz rate. The 100 Hz
signal is then processed in the counters and multiplexed
in the decoders.
This circuit is designed for use as a digital timer,
4·function stopwatch and 24, hour clock; the only external
'components required are the display, batteries, 6.5536
'MHz crystal, turning capaCitor and 4 switches.

ICM7045
• Versatility of applications: precision timer,
,4 mode stopwatch, 24·hour clock
• Uses 6.5536 MHz quartz crystal for high
accuracy

The ICM7045A

ICM7045/A

The main difference between the 7045 and 7045A is that
the divide by sixty counters of the 7045 'are replaced by
decade counters in the 7045A. Thus seconds, minutes or
hours may be counted in a decade fashion, depending on
the choice of osci lIator frequency.
The two other differences are: the oscillator is divided by
217 in the 7045A, and CATH B (LSD) is not used.

• ' May Be Used to Count '
-Seconds (1.310772 MHz crystal)
-Minutes (2.184533 MHz crystal)
-Hours (3.640889 MHz crystal) ,

BLOCK DIAGRAM

PIN CONFIGURATION (outline dwg 01) ,

V+

2 LINES

SEG d
SEG.

a UNES
v'

tl·

HF DIVIDER
8 LINES

28

SEG.

'

27

DIGITS 3 & 4 ADVANCE

3

26

SEG,

GROUND'

" CATH5

CATH 3

5

" CATH 6,

CATH 4

6

1 & 2 ADVANCE )
CATH 1 (MSD)

1 LINES

ZENOR DIODE HAS TYPICAL BREAK06wN VOLTAGE OF 6.5V.

ORDERIN~

INFORMATION

[. I

ICM7045

A

,

I

,

23

TEST POINT

" CATH 7
CATH 8(7045)NC(7045A)

8

21

START/STOP

9,

'0 OSC OUT

CATH 2

10

19

OSC IN

DISPLAY

11

18

SEG g
SEG b

Package

STANDARD MODE

12

1)

L.."
Pi" Pi,,,;, DIP
Temperature Range

SPLIT MODE

13

16

RESET

RALLY MODE

14

15

SEG c

DI

I

= Industrial

- 20·C to

+ 85·C

Option
Type
Order Dice by Following Part NLimber- ICM7045ID, ICM7045A/D

7·15

ICM70451A
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (1) ................................................... 1W
Supply Voltage ..................................................... + 5.5V
Input Voltage ................ Equal to, but never in excess of the supply voltages
Output Voltage .; ............ Equal to, but never in excess of the supply voltages
Digit Drive Output Current ....................................... 150mA/digit
Storage Temperatures .................................... -55·Cto +125·C
Operating Temperatures .".................. , ............... - 20·C to + 85·C
Lead Temperature (Soldering, 10 sec) .. '......................... : ...... 300·C
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
'these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 1: This value of power dissipation refers to that of the package and will not be obtained
under normal operating conditions.

TYPICAL OPERATING CHARACTERISTICS
\

'

TEST CONDITIONS: V+ =3.6V, TA =25·C Parameters listed are absolute value
PARAMETER

Supply Current

Operating Voltage
Segment Current Drive

SYMBOL

1+

V+
ISEG

Instantaneous
Average
Segment Current Drive

CONDITIONS

Display Off
7 Segments Lit
VF= 1.8V
2 Segments Lit
VF=1.8V
-20·C
0

18

I-

zw

16

CI

14

::E

w

III

'""w..."

r--

.......
~

I

I

.s
z

I

I

SEGMENTS LIT

::>

18

I-

16

0

z
w

........

:--.. .......

"-

12

7 SEGMENTS LIT.......

10

I I I I I

8
1.5

I

-

.......

CI

III

...'""w"

"-

1 700

V

I-

zw

600

a:
a:
::> 500
0

400

>-

1/

..J

300

::>

200

00-

J

III

2.5

-~

100

V

6

2.S

800

jf',
V 7 SEGMENTS LIT

10
8

TA=2S'C
DISPLAY OFF'

900

'/

J

12

w

........

1000
TA=2S'C
LED FORWARD
VOLTAGE DROP
OF 1.8V AT 15mA

14

::E

2.0

SUPPLY CURRENT
VS.
SUPPLY VOLTAGE

PEAK SEGMENT CURRENT
VS.
SUPPLY VOLTAGE

,...- f -

o

3.0

LED SEGMENT VOLTAGE DROP

3.5

4.0

4.5

5.0

2.5

3.0

3.5

-4.0

4.5

5.0

SUPPLY VOLTAGE

SUPPLY VOLTAGE

OSCILLATOR STABILITY VS. SUPPLY VOLTAGE FOR 3 DIFFERENT QUARTZ CRYSTALS (lCM7045A)
+ 12.0 r - - - - r - - , . - - - - - - - ,
E

E + 12.0 r----r--r--:T·A-=..,2"'5,..'C~---,
Q.
f = 3.64089 MHz
~ + 8.0
QUARTZ RS = 330
z
CRYSTAL Co = 4.1pF
o 40 PARAMETERS, CM = 18mpF

+ 12.0 r---,--'---:---;:---'--:II
E

Q.

!i+'
~
~~~~"~~4--=~~

Q.

~ + 8.0 1'---t--',:--""":"-'--'-"T7£...J
z
52 + 4.0 1'--......1--=.:,---'-!7"~"""'~
!¢

z
52

~

~Q

~ + 8.0 f--t--+---,..--r--'iI'---l

Q

~

~ -4.0 COUT=60pF,

·z
w

::>,

TA=25'C
t= 2.184533MHz
QUARTZ
RS = 800
CRYSTAL
C
51 F
PARAMETERS

15

•

5w - 80.

RS= 47!l
Co = 3.3pF
CM=10mpF

~ -8.0

a:

u.

+4.0

!¢

-12.0 '----'_-'-_........_...1...-_.......- 1
3.0
. 4.0
2.0
5.0
SUPPLY VOLTAGE

3.0
4.0,
SUPPLY VOLTAGE

2.0

C~~10~PF

::: -12.0

5.0

2.0

3.0
4.0
SUPPLY VOLTAGE

ICM7045
Quartz Crystal Parameters
f = 6.5536 MHz
Rs=40n
C1 =15mpF
Co =3.5pF

lC['

""

"'

Ml0

~.i '1-/'
.Ii!- I~?
/
/

M1

I0 /

.

s"

51

10THS

l00THS

q?~~
I

l~~
r;- •

~.

t--!, !

L-a

26

.r.

H,C!

25

,.
1m-

5

,'('c

~
0:
'8

DISPLAY

STANDARD

'"

~
"
'

"'
b~~
SPLIT

RALLY

~

I~

"
"
Iw
2

'10

0',

N.O. = NORMALLY OPEN
N.C. = NORMALLV CLOSED

CTUN1NG

lICM704S*J f"

9

START/STOP

[ID- W
~

--a

~

14

6.5536 MHz.

N.O.

---.L

RES~

TOP VIEW

'Shown for ICM7045. The same circuit may be used with the 7045A if a different crystal frequency is chosen.
NOTE:

Specify quartz 'crystal to have nominal frequency value
when tuned by a total parallel capacitance value of 12
pF or less.
Figure 1: Four Stopwatch Modes

7-17

5.0

ICM7045/A
3. Showing 00 in the two least significant digits. (7045';
least significant digit 7045A)
4. Turning on the display if it was previously turned off

FUNCTIONAL OPERATION
STOPWATCHITIMER OPERATION
The control' inputs used in the complete stopwatch application are: (refer to fig. 1)
START/STOP
DISPLAY

The display of just two zeros in the two least significant
digits (7045; least significant digit 7045A) gives' the
complete assurance that the stopwatch is "ready to go."

SPLIT
RALLY

RESET
STANDARD

START/STOP and DISPLAY are designed for connection to
single pole double throw switches to insure operation free
of contact bounce.

STANDARD MODE
In the STANDARD mode, after a reset has taken place,
START/STOP is activated at, time to. The clock and display
are moving simultaneously. A second activation of
START/STOP stops the clock and holds the display at time
ttotal' This completes an event. For timing a second event
there are two options. One is to /3ctivate START/STOP at
the start of the secohd event. This will momentarily reset
the counter and display so that the timing of the second
event proceeds from zero. Another activation of
START/STOP stops the counter and display at time ttotal to
end the second event. The other option, i~ to activate
RESET after the first event is over. Then the second event
proceeeds similarly to the first eve!}t. As is clear from this
description, RESET can be used at any time to reset the
stopwatch, including when a timing is in progress. The
DISPLAY input can be activated to turn the display off and
on. If the display is off when RESET is activated,it will
reset and turn on. Turning off the display for timi'1g long
events will result in a very substantial power saving.

The switch connected to RESET can be normally open
single pole single throw. STANDARD, SPLIT and RALLY
are control pOints with internal pull down resistors to
v- .T~ese are designed to be connected to a rotary
function switch which will connect no more than one of
these pOints to V+. If STANDARD (SPLIT, RALLY) is
connected to V+ the stopwatch is said to be in the
STANDARD (SPLIT, RALLY) mode. If all three are left open,
the stopwatch is in the SEQUENTiAL mode.

RESET FUNCTION
When the stopwatch is turned on, the RESET will normally
be activated. This puts the stopwatch ina ready condition
by:
1. Resetting all circuitry
2. Blanking seconds, minutes, hours

PAUSE

10 EVENT NO.1

~--I
MANUAL
RESET

START/STOP
,

•
STARTS
RESETS
COUNTER
COUNTERS,

t

BLANKS
6 MOST
SIGNIFIGANT
DIGITS

,

"0••1

HOLDS
DISPLAY

DISPLAY
FOLLOWS.
COUNTER

,

BLANKS

f

(AUTOMATICALLY)
MOMENTARILY'
RESETS COUNTERS

"010,

'

- 1----- ....
START/STOP
t
HOLDS
DISPLAY

t
t

BLANKS
DISPLAY
FOLLOWS
COUNTER

PAUSE . to
~~I

RESETS
COUNTERS

EVENT NO.2

,
STARTS
COUNTERS '

TURNS ON
DISPLAY

MANUAL
RESET

to

..

. 1 ' --I
START/STOP
START/STOP
,
t

EVENT NO.1

"0'"

-I

START/STOP
,,

START/STOP

START
COUNTER

• HOLDS
COUNTER

.--~.

to

MANUAL
RESET

START/STOP
,

t
RESETS

STARTS
COUNTER

COUt.JTERS

t

BLANKS

TURNS ON
DISPLAY

7-18

~tot.1

EVENT NO.2

• 1

•

f---o

START/STOP

t

•

HOLDS
COUNTER

0 0 0

O~OI!:.

ICM7045/A
SEQUENTIAL MODE
The sequential mode of the stopwatch is designed for timing events consisting of more than one leg (such as relays,
multilap races, etc.). After the initial rese.t the START/STOP
is activated at to to start the event. A second activation of
START/STOP at time t1 stops the display and allows t1 to
be read out, while the clock resets and starts counting
again instantaneously. At time t2 an activation 6f
START/STOP enters t2 (the time of leg 2) into the display.
This sequence can continue indefinitely. Assuming the
, total event has n legs, the total elapsed time is then equal

to the sum of the n times read out:

If it is desired to see the moving clock after a time has
been recorded, the DISPLAY switch can be activated to
release the display hold and catch up with the moving
clock. The display cannot be turneo off in the- sequential
mooe. RESET can be activated at any time to reset clock
and display.

'.f - - - - - - - - ~'"'US-E-.--I--L-EG-N-O-.'~-'f-i
MANUAL
RESET

START/STOP

STARTS
COUNTER

RESET
COUNTERS

I
BLANK
DISPLAY

__LE_Q_N_O._2~._I~~

~NO. n

START/STOP

START/STOP

HOLDS
DISPLAY

ADVANCES
AND,
HOLDS

ADVANCES
AND
HOLDS

DISPLAY

DISP~AY

I

\

DISPLAY
FOLLOWS

COUNTER
IS
UNINTERRUPTED

COUNTER

•••

START/STOP

t

t

t

'0

EVENT ---,,---------~_l

t

,

f

\

COUNTER
IS
UNINTERUPTED

COUNTER
IS
UNINTERRUPTED

ILt:o NO.n = t n -

lEG NO.2=t z -l,

LEG NO.1 =1, -10

tn+

1

SPLIT MODE
The split mode is another mode for timing multileg events.
In contrast to the sequential mode, the timing in the split
mode is cumulative. From a reset condition, the
START/STOP switch is activated at to to start the counter
and display running. A second activation at t1 stops the
display and allows t1 to be read out while counter 'continues timing. A third activation at t2 advances the display

with the total elapsed time from to to *2 showing. Finally, at
time tn the total elapsed time of the event is entered in the
display. The time of on\lleg of the event can be obtained by
subtraction. The display can be synchronized to the
cOllnter (catch-up function) at any time by activating the
display switch. To reset the timer, activate reset. The
display cannot be turned off in the SPLlT'mode.

'.f - - - - - . . , . , - - - P~~E __

!

_

LEG NO.1

I, 10

LEG NO.2

EVENT

to,

12

.

LEG NO. N

In to

,----.-~f____--~I--'----· \-'---r'---I··· ~'~I

MANUAL

START/STOP

START/STOP

STARTS
COUNTER

HOLDS
DISPLAY

START/STOP

START/STOP

ADVANCES

ADVANCES

AND
HOLDS
DISPLAY

AND
HOLDS
DISPLAY

I_

RESlET
RESETS
COUNTERS

\

I

1

DISPLAY
FOllOWS
COUNTER

BLANKS
DISPLAY

+

t

I

RESETS

COUNTERS

I
STARTS

RESETS
COUNTER

RESETS
COUNTER

I

+

COUNTER

STARTS
COUNTER

STARTS
COUNTER

RALLY MODE
The rally mode is designed for timing of events with interruptions. Consider an n leg event where the legs may be
separated by intervals which should not be timed. The rally
mode' starts with a RESET. At time to, the stopwatch is
,started by activating START/STOP. After this pOint the
RESET function is disabled to prevent accidental resets

during long timing intervals. At time t, a START/STOP
pulse stops counter and display. From here on each leg
time is added to the total by a START/STOP pulse at the
beginning of the leg and atthe end. The individual leg
times are determined by subtraction. The display can be
turned on and off with the display switch.

'.I - - - - - - - - - - - - - E V E N T - - - - - - - - - - - - - 1'.
II

II

'-:

I

START/STOP

START/STOP

START/STOP

START/STOP

C~~~~;R

C~~~~~~;S

C~~~~;R

COUNTER
CONTINUES

OISP
HOLDS

DISPLAY
FOLLOWS
. COUNTER

DISPLAY
HOLDS

~~f--L-EG-N-O-.'~I~~II---LE-G-NO-.-2-.-tl--P.,-~~.~~~
1 MANUAL

~~LE:

t

COUNTER
RESETS

t
BLANK

,START/STOP

t
CS;::;:R

tit

DISPLAY
FOLLOWS
COUNTER

t

ttl

DISP
LEGNO.1=1 1 -I O

7-19

t

,

t

DISPLAY
FOLLOWS
COUNTER

___ I LEG N~
START/STOP

t

COUNTER
HOLDS

t

DISP
HOLDS

O~OIb

ICM7045/A
CLOCK OPERATION
The control inputs used in a possible 24-hour clock configuration are (refer to fig. 2):
START/STOP
MINUTES ADVANCE
HOURS ADVANCE
RALLY
START/STOP,
MINUTES
ADVANCE
and
HOURS
ADVANCE are designed for connection to single pole
double throw switches; this assures contact bounce
elimination on the~e inputs. To avoid an additional switch
for the DISPLAY input, the RALLY input should be
connected to V+ through a 20kresistor and to V- through
a 0.01J.-------+---co

v+~------~---{Il

TOP VIEW

TOP VIEW

CLOCK CIRCUIT I
The standard clock circuit is shown and described in fig. 2.
The clock accuracy with a stable voltage supply will de·
pend mostly on the temperature and aging characteristics
of the crystal.

TIMER CIRCUIT II

The power supply can be modified to give battery standby
power.

This circuit allows cumulative timing of intervals. Each in·
terval is timed by one start and one stop pulse on the
start/stop line. Each subsequent interval timed adds to the
total line displayed. The reset switch allows the timer to be
reset to zero to start another sequence of intervals. Note
that the time between the end of one interval and, the start
of the reset is not recorded nor added to the total.

,N

V4V

>>------1...-----.. .

TO

v+

=

3.6V

1
v+ 0-------+---[

The standby circuit should be designed to provide the
specified minimum voltage to the ICM7045,

OTHER CLOCK CIRCUITS
The basic. clock circuit can be modified for various special
applications. If it is desired to turn the display on and off,
then connect the display input to an additional SPOT
switch, while omitting the capacitor/resistor combination
on theSTANDARD Input.
,
This input can then be wired direJt~ to V +. This 24-hour
clock version might be applicable to vehicles, boats, etc.
where a battery Is available to supply the display off clock
current, while the display can be turned on with the ignition. Another possible configuration would connect a
special circuit to the DISPLAY input which generates a
double pulse about 3 seconds. apart:

N.O.

t:ill-.--<"--

RESET

I
7-21

ICM7045/A

r

lOOk

-L
0---+--------1

TO DISPLAY INPUT

This means depressing the switch will turn on the clock's
display for.3 seconds. This allows design of a battery
operated "on demand" digital 24·clock.

STOPWATCH EXTERN.AL SYNC CIRCUIT
If the stopwatch is connected as shown in fig.1, a-few addi·
tional 'components will allow external synchronization of
the stopwatch in any mode:

v+

10k
ICM7045/A

2.2k

2.2k

. I

I

"--------~-~-------

I

NOTE:-

Be sure to minimize the distance between the transistor
and the ICM7045 to prevent noise from being generated
along this connection. Noise spikes absolutely. must not
exceed the supply voltages.

,

.

.

The external sync signal source must supply a positive
pulse to activate the START/STOP Input. The minimum
voltage of this pulse is about 1.2V in the circuit as shown,
but the triggering level can be changed by modifying the
input resistor ratio. The output impedance of the ex~ernal .
sync signal source should be no 'greater than 4k ohms.

TH E ICM7045A
The ICM7045A will coun~ to a total of 2399999. The next
count will show 0000000. On appliction of RESET the
display will show 0 on the least Significant digit; all other
digits will be blanked. Leading zero suppression blanking
is performed on pairs of digits. For example, 9 will show as

9, 10 will show as 010, 999 will show as 999, 1000 will
show as 01000 and so forth.
The oscillator frequency alone determines whether the
timer is to be used for second, minute or hour counting.

'SECONDS' TIMER Use a 1.31072MHz quartz crystal
DIGIT #
,1
23
OOOK Secs _ 10K Secs
1K Secs
'MINUTES'TIMER Use a 2.184533MHz quartz crystal
DIGIT #
1
2
3
1K Mins
100 Mins
10 Mins
'HOURS' TIMER Use a 3.640889MHz quartz crystal
1
2
DIGIT #
3
1.0 Hrs
Hrs
Hrs+10

4
,
100 Sees

5
10 Sees

6
Secs

7
Sec +10

4
Mins

5
Min+10

6
Min +100

7,
Min +1000

4
Hrs +'100
7·22

5
Hrs +1,000

6
7
Hrs +10,000 Hrs +190,000

ICM70451A
OSCILLATOR CONSIDERATIONS
The oscillator is a high gain complementary MOS inverter
with on-chip feedback resistors and an on-chip fixed input
capacitor of 22pF_ For the 6_5536 MHz crystal needed for
normal tiniing, it is suggested that the nominal load
capacitance be kept under 12pF to keep total loading on
the oscillator to a reasonable level. The actual trimmer
range and the nominal load capacitance needed will have
to be determined from the total stray capacitance of the
. particular circuit (including ICM7045 with package, PC
board, etc.) and the tuning tolerance of the chosen crystal.
The series resistance of the crystal should also be kept to
a low value (typically less than 50 ohms) to achieve
adequate low voltage operation ..
Oscillator t\me up can be most easily performed using a
pull-up resistor of 10k ohms on the fractional seconds
digit, using period average tune for 1.25ms (800Hz).
The oscillator of the ICM7045A is identical to that of the
ICM7045, with the exception of the crystal frequency and
load capacitance; Using similar value tuning capaCitances
with the lower frequency crystals (1.31077HHz, 2.184MHz
3.64089MHz) the stability of the oscillator is significantly
degraded. It is, therefore recommended that the tuning
cap,acitances be increased to a nominal total of 40pF at
both the oscillator input .and output. Since there is an on
chip input capaCitance of 20-22pF the additional external
input capac.itance should be approximately ;!OpF.
The ICM7045A is guaranteed to operate over the supply
voltage range of 2.5 to 4.5V using nominal input and output

tuning capacitances of 40pF and with crystals having the
following characteristics:
f = 1.310772MHz
2.184533MHz
3.64089MHz
Rss 1000 (1500 for 1.310772MHz)
.
CM -10-20mpF
Cos6pF
CL = 20pF (parallel resonance mode)

CHIP TOPOGRAPHY
CATH

1&2

ADV

7-23

li

(7045) NC(7045A)

D~DIL

ICM7050
CMOS Quartz
Clock Circuit
Bipolar Stepper Motor Applicatioris
GENERAL DESCRIPTION

FEATURES

The ICM7050 is a single battery analog quartz clock circuit
intended for use with bipolar stepper motors, and fabricated
using Intersil's low voltage metal gate C-MOS process. The
circuit consists of an oscillator, a divider chain, an output
oneshot, and output buffers. The oscillator, when using the
. specified 4.19MHz crystal and capacitors, provides excellent stability. The high frequency portion of the divider
chain consists of dynamic dividers, while the remainder are
static. The dynamic dividers provide for low power
consumption and low operating voltage, but limit low
frequency operation. The 223 divider chain is tapped at the
211 ,2 19, and 222 points to provide a complex alarm of 1Hz,
8Hz, and 2048Hz driving an output inverter. The oneshot
generates the 46.875 millisecond pulse width and the large
output inverters provide the low impedance necessary to
drive the motor. A reset inhibit function is provided so that if
the RESET occurs during an output pulse resetting wi" not
take place until the pulse is completed. RESET may also be
used as a stop for synchronization to a time signal or tester.

Single b~Hery operation
Very low current - typically 30~A at 4.19MHz
Reset or stop function, Inhibited during output
Excellent drive with extremely low output saturation
resistance: less than 100 ohms
• Complex direct drive alarm: 1 Hz + 8Hz + 2048Hz
• Output pulse width 47ms at 1 Hz rate
• Cust.omoptlons avallable*

•
•
•
•

"Two customized versions of the ICM7050 are available as standard
factory options. They are:
ITS9063 - Output pulse width is 31 ms at 1Hz rate.
ITS9064·1 - Output pulse is a 1Hz square wave.

PIN CONFIGURATION

BLOCK DIAGRAM

(OUTLINE DRAWING PAl

,

IT -v-":!IBOSCIN
v- 11 ICM7050 :TI OSC OUT
:!l ALARM
OUT1 I!
v+1.

OSC B
IN

~DYNAMIC
v

SP.!'EDUP!GATE

+26

+25

1
OSC
OUT

7

RES~:~~TOP 4

ALARM

-

6

;--

OUT
2
3

~l
V- 2

1

RESETITEST
TEST
AND
RESET
RESET
INHIBIT
LOGIC

'!r'tSN/STOP

2048

r-J:!!-

OUTPUT
CONTROL
LOGIC

+27

ORDERING INFORMATION

2171
21.

ICM7050

Q +2 Q

RESET
MEMORY
LOGIC

223

8Hz
+25

,
/

j

L

OUT2

TOP VIEW

COMPLEX
ALARM
LOGIC

1Hz

]:I

I}

I

T1

PA

T

Package
PA = B pin plastic OIP
·Temperature Range:

Industrial -20 0 C to 70 0 C
Type

Order Devices by Following Part Number -ICM7050IPA
Order Dice by Following Part Number - ICM7050/D
Order Options by Following Part Numbers ICM7050 IPA/ITS 9063
ICM7050 IPA/ITS 9064-1

I

7·24

O~OIb

ICM7050
ABSOLUTE MAXIMUM RATINGS
Power Dissipation Output Short Circuit (Note 1) ......................... 300mW
Supply Voltage ............................................................. 3V
Output Voltage (Note 2) .......... ,.......................... Equal to but never
Input Voltage (Note 2) ............................. exceeding the supply voltage
Storage Temperature .......................................... -30°C to +125°C
Operating Temperature ........................................ :"20°C to +70° C
Lead Temperature (soldering. lOs) ....................................... 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

,

NOTE 1: This value of power dissipation refers to that of the package and will not normally be obtained urider normal operating conditions.
NOTE 2: Due to the inherent SCR structure of junction isolated CMOS devices, the circuit can be put in a latchup mode if large currents are
injected into device inputs or outputs. For this reason special care should be taken in a system with multiple powersupplies to prevent
voltages being applied to inputs and/or outputs before power is applied. If only inputs are affected, latchup can also be prevented by
limiting the current into the input terminal to iess than 1mAo

ELECTRICAL CHARACTERISTICS
(V+ = 1.5V, f05c = 4.194.304Hz test circuit. TA = 25°C. unless otherwise specified)
PARAMETER
Supply Current
Operating Voltage
Total Output Saturation Resistance
Alarm Saturation Resistance

Oscillator Stability
Oscillator Start-up Time

SYMBOL
1+
V+

ROUT
RAL(on)
f5tab
totart

CONDITIONS
No Load
-20°C < TA < 70°C
IL = 3mA
P.IL=lmA
N.IL=2mA
1.2::; V+ ::; 1.6
V+ = 1.2V

MIN

TYP
30

1.2
70
400
100
1

1.0

CLOCK CIRCUIT

~--------------~--ALARM

v+~~~--~
RESET/STOP

v-

Quartz Crystal Parameters
f ~ 4,194,3D4 Hz
R5 ~ 45 ohms

C,

~

Co

~

1DmpF
4pF

MOTOR

7·25

MAX
60
1.8
100
700
400

UNITS
p.A
V

n
n
n
ppm
sec

O~OIL

ICM7050
OUTPUT WAVEFORMS
,

NORMAL OPERATION

RESET DURING OUTPUT 1 PULSE

r---fS

~

OUT l '

.

'1,.1 .

!

OUT2

U

II

I

'

R~SET ~1-1S0C-

ALARM

ALARM
RESET BETWEEN PULSES

U,...---

RESET DURING OUTPUT 2 PULSE

OUT1~S

Ii

OUT 1

I~S----------~~

OUT2

....Il'==

RESET _ _ _

'i

M, fJ-----,

L._ _l_S_0C_---J_---''--_

IMm'''OOIII

, ALARM

TYPICAL OPERATION CHARACTERISTICS
SUPPLY CURRENT va SUPPLY VOLTAGE
~

140

Cryslal paramoto~l
Por Clock Circuli page 2

120

Cln/Co~! = 10~F/~P~/

0

.

0

V

V

./'

3

Cln/C;:ou! = 10PF/:t"

E

!...
,

-1

.....-::;;...

1.2

-2

1.5
SUPPLY VOLTAGE

OUTPUT CURRENT

,,/V

3!10

30pF/l0pF

oF0

1

;! 0
J!!

15PF~ ~

~

,2

vs. SUPPLY VOLTAGE

Crys1a1 paramete'!L
Per Clock Circuli page 2

V

0./

0

OSCILLATOR STABILITY

-

I-- V

1.3

. 1.&

lJPF/15PF
30pF/l0PF

1.5

1.8

SUPPLY VOLTAGE

va OUTPUT LOAD VOLTAGE'

ALARM OUTPUT CURRENT

VB

SATURATION VOLTAGE

1.5

O~
0

..........

"'""-" "'"

~+""I.&V

........

v+= .5V

'""- K

-

+=1. V

0

o '.

~

~

'\

~
r--.,.

~

'\~

1,\ \

1.0
OUTPUT LOAD VOLTAGE

1.5

0.5

1.0

N Channel Saturation Vollage

CUSTOM OPTIONS

1.5

• Alarm frequency - Any combination of· three binary
frequencies up'to and including 2048Hz.

All Intersil analog quartz dock circuits are mask
programmable for a variety of input and' output
configurations. The ICM7050 may be customized by varying
the following. Parameters specified apply to an input
frequency of 32kHz.
• On chip oscillator capacitor· - up to 50pF at COSCI or
Cosco
'
• Output pulse width - ~rom 7~~ms to 50% of output period
• OutpU.t pulse frequency - from 0.5Hz·to 64Hz

A mask programming charge and a minimum order are
required f.or custom options. Consult factory for details.

7·26

ICM7050
APPLICATION NOTES

OSCILLATOR TUNING METHODS

When tuning the oscillator two m·ethods can be used. Th~
first method would be to monitor the outp·ut pulse at either
OUT 1 or OUT 2 with a counter set to measure the period.
The oscillator trimmer would then be adjusted for a reading
of 2.000000 secs. A second method would be to put the
device in the reset mode by pulling the reset pin to V+ and
then monitor the ALARM output with a counter set to
measiJre average period. The ALARM output is a continuous
2048Hz when in the reset mode, which gives a period of

OSCILLATOR CONSIDERATIONS
The oscillator of the ICM7050 has been designed to operate
with crystals having a load capacitance of 10 to 12pF. This
allows nominal capacitor values of 15/15pF or 20/20pF.
Increasing the load capacitance ofthecrystal requires larger
oscillator deliice sizes, which causes the supply current to
increase. Modifications to the oscillator can be made on a
custom basis~ The tuning range can be increased by using
'crystals with lower load capacitances, however the stability.
may decrease somewhat. This can be counteracted by
. reducing the motional capacitance of the crystal. A nonlinear feedback resistor having a maximum value at start
up is provided on chip. Oscillator tuning should be done at
the oscillator output.
The following expressions cao be used to arrive at a crystal
specification:·
.
Tuning Range
af =
Cm
f
2(Co + Cll

Cl =

488.2815its.

TEST MODE OPERATION

CinCout
Cin + Cout

Pulling the RESETITEST ,input to -7V switches the device
into the test mode to speedup automatic testing. When in the
test mode the output rate is increased 16 times, from 1Hz to
16Hz, with a corresponding reduction in pulse width. The
ALARM output changes to a composite waveform of 16Hz
and 128Hz. The circuit can be reset while in the test mode by
shorting the ALARM output to V-.
.

gm required for startup
gm =

ru2

CinCoutRs

(1 +

.

The trimmer capacitor used for tuning should be connected
to the oscillator output. Otherwise, if tuned at the input, the
stability will vary with tuning, and the current drain may
become excessive when the input capacitance is' much less
than the output capacitance. Refer to the 1+ vs V+ and
OSCILLATOR STABILlTYvs V+ characteristic curves on the
preceding page.
.

~) 2

Rs = series resistance of the crystal
f = frequency of the crystal
af = frequency shift from series resonance frequency
Co = static capacitance of the crystal
Cin = input capacitance
.
Cout = output capacitance
Cl = motional capacitance
ru = 27l'f
The resulting gm should not exceed 50",mhos.

ALARM CONSIDERATIONS
The ALARM output inverter is large .enough to directly drive
transducers requiring up to 2mA of current. If more current is
needed than a buffer should be used'. A slight fluctuation in
the ~upply current of 0.5",A to1.0pA will be seen; this is a
result of 2048Hz driving the relatively large gate capacitance
of the alarm output transistors.
'See Intersil Application Bulletin A031 for details.

CHIP TOPOGRAPHY
asc osc
IN.

OUT

ALARM

OUT2

.06S"

.173mm

1
I·

RESET

TEST
.076"

,I

1-----.193mm·---'--'-

7-27

ICM7206
CMOS'Touch
ToneMEncoder·

U~DlL

-3dBV into. a 900 ehm terminatien. The skew between the
high and lew groups is typically 2.5 dB witheut lew pass
filtering.
.

FEATURES
• Low cost system with minimum component count
• Fully integrated oscillator uses 3.58 MHz color TV
crystal
.
• .High current bipolar output driver
• Low output harmonic distortion
• Wide operating supply voltage range:.3 to S vO.lts
• Uses inexpensive single contact per ~ey
calculator type keyboard (ICM720S/C/D)
• Extremely low power :5 S.SmWwith a S.SV supply
• Single and dual tone capabilities
• Multiple key lockout
.
• Disable output: provides output switch function
whenever a key Is pressed
• Custom options available

The 7206 uses either a 3 x 4 er 4 x 4 single centact keybeard;
the escillater will run whenever the pewer is applied, and the
DISABLE eutput censists of a p-channel epen drain FET
.
whese seurce is connected to. Y+·.
The 7206A can also. use a 3 x'4er4x4keybeard, but requires
a double centact type with the cemmen line. tied to. y+, The
oscillater will be en whenever pewer is'applied; the DISABLE
output censists ef a p-channel epen drain FET; its' seurce is
cennected to. Y+.
The 7206B requires a 4 x 4-deuble centactkeybeard ~ith the
cemmen line tied to. Y-. The escillater will be en enly during
the time that a ROW is enabled; and the DISABLE eutput
censists ef an n-channel epen drain FET with its' seurce tied
to. Y-.
.
The ~206C uses either a 3 x 4 er4 x 4 single centact keybeard;
the escillater will be cn enly during the time that a key is
depressed. The DISABLE eutput censists cf an n-channel
e'pen drain FET with its seurce tied to. Y-"
The 7206D uses a single centact 3 x 4 er 4 x 4 keybeard. The
escillater will be on only during the' time that 'a key is
depressed. DISABLE eutput consists of a p-channel open
drain FETwith its seurce tied to. Y+.

GENERAL DESCRIPTION
The Intersil ICM7206/A1B/C/D are 2-ef-8 sine wave tene
enceders fer use in telephene dialing systems. Each circuit
c:entains Ii high.frequency·escillater, two. separate pregrammabie dividers, Ii D/A cenverter, and a high level eutput
driver.' .
The referenqe frequency is.generated frem a fully integrated
cscillater requiring enly a 3.58 MH2; coler TV crystal. This
frequency is divided by 8 and is then gated into. two. divide by
N ·ceunters (pessible divisien ratics 1 throUgh 128) which
prcvide the cerrect divisien raties fer the upper and lower
band ef frequencies. The eutputs frem these. two. divide by N
ceunters ar~ further divided by 3 to. previde the time.
seque~cing for a 4 veltage level synthesis ef each sinewave.
Beth stnewaves are added and buffered to. a high current
'cutput driver, with 'prcvisions made fcr-up to. two external
. capaciters fer lew pass filtering, if desired. Typically, the
tctal output harmenicdistcrtien is·20% with no. L.P. filtering
and it may be reduced to. typically less than 5% with filtering.
The cut~ut drive level cf the tene pairs will be apprexlmately

14pF

II
'.

OSC.IN

14pF ..

0--+--1

1----+---+-- TO +8

~--~+---+--~v-

OSC OUT <>----:----;.;------------'

ICM72060s'ciliator

PIN CONFIGURATION
VIC

1.

16

lP2 C 2
ReW1 C

15

p'v+

PeUTPUT

.ICM

1;

7206/A1B/C/D

PART
NUMBER.
ICM7206JPE
ICM7206A JPE
ICM7206B JPE
ICM7206C' JPE
. ICM7206D JPE
ICM7206/D
ICM7206A/D
·ICM7206B/D
ICM7206C/D
ICM7206D/D
)

p COl2

- ReW3 C

5

ReW4 C

6

11 ::fCOl4

DISAlilE C

7

10

8

9

v- c:

ORDERING INFORMATION
..

14.P cel 1

'3

ReW2C 4

(eUTLINEeRAwINGPEI.

12

P cel3

::J esceUT
::J esc IN

Pin 1 is deSignated either by a del er a netch.

7-28

TEMPERATURE
RANGE
-40··C to. +85· C
-40·. C to. +85· C
-40· C to. +85· C
-40·C to. +85·C
-40· C to. +85· C
_40· C to. +85· C
_40· C to. +85· C
_40· C to. +85 0 C
-40· C to. +85· C
-40· C to. +85· C

"

PACKAGE
Plastic
Plastic
Plastic
Plastic
Plastic
DICE
DICE
DICE
DICE
DICE

ICM7206 Family
ABSOLUTE MAXIMUM RATINGS (Note 1)

Output Volt. (term. 151. Not more pas. than +5V with respect to V+,
nor more neg. than -1.0 with respect to VOutput CUffent (terminal 151' ............................. 25mA
Power Dissipation ........... .'......................... 300mW
Operating Temperature Range ................. -40°C to +85°C
Storage Temperature Range .................. -55°C to +125°C

Supply Voltage (Note 21 .................................. 6.0V
Supply Current V- (terminal 81 ........................... 25mA
Supply Current V+ (terminal 161 .......................... 4dmA
Disable Output Volt. (term. 71 .. Not more pas. than V+ nor more
neg. than -6V with respect to V+
NOTE

i. Stresses above those listed under Absolute Maximum Rating's may cause permanent damage to thed~vice. These are stress ratings only.
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability,

NOTE 2. 'The ICM7206 family has a zener diode connected between V· and V- having a breakdown voltage between 6.2 and 7.0 volts. If the
currents into terminals 8 and 16 are limited to 25 and 40mA maximum respectively, the supply voltage may be increased above 6 volts
to zener voltage. With no such current limiting, the supply voltage must not exceed 6 volts.

TYPICAL OPERATING CHARACTERISTICS
TEST CONDITIONS: V+= 5.5V, Test Circuit, TA = 25°C unless otherwise specified.
PARAMETER
Supply Current
Guaranteed Operating Supply Voltage Range
I Note 3,
Peak to Peak Output Voltage
RMS Output Voltage

SYMBOL

CONDITIONS

1+

Rl disconnected

VOP

-40°C S TA S +85°C

VOUT

Skew Between High and Low Band
Output Voltages

MIN. TYP. MAX. UNITS
450 1000
3.0

C1, C2 disconnected - Low Band
0.90 1.15 1.45
Rl - 1 kll, no filtering - High Band
1.10 1.40 1.70
Rl = 1kll, fOUT = 697Hz
C2 Only
480
480
C1 to C2
Nofillering
490
Rl = 1kll, fOUT= 1633Hz
490
C1
580
C1 to C2
Nofiltering
655
Rl = 1kll, C1, C2 disconnected

Output Impedance

Zo

Total Output Harmonic Distortion

THD1

R,l = 1kll

Operating
Quiescent

dB

90
25

200

II
Kll

20

25

2.3
1.0

10
10
4.6

fose

3S,VT_V',S6V

2.0

4.5

4VS,V+-V',S6V

2.0

'7

Maximum Output Voltage Level

VOH

Minimum Output Voltage Level
Keyboard Input Pullup Resistors
I
Keyboard Input Capacitance
Guaranteed Oscillator Frequency Range
,Note4,
Guaranteed Oscillator Frequency Range
System Startup Time on Application of Power
System Startup Time on Application of Power
and Key Depressed Simultaneously
DISABLE Output Saturation Resistance
,ON STATE,
DISABLE Output Leakage
,OFF STATE,

VOL

ton

ICM7206,ICM7206A

100

See Logic Table for Input Conditions
Current = 4mA

10lK

See Logic Tabt'e for Input Conditions

Oscillator Load Capacitance

Case

Guaranteed Output Frequency Tolerance

fa

Oscillator Startup Time ICM7206B, C, 0

tstart

Measured between terminals 9 & 10,
' no supply voltage applied to circuit
_40° CST AS 85° C
Any output frequency
Crystal tolerance ±60ppm
Crystal load capacitance CL = 30pF
VT = 3V I Note 5,

NOTE 3:

150
5

%

V
Kll
pF
MHz

10

ICM7206B, ICM7206C, ICM7206D
RD

mV

3.0

RIN
CIN

THD2

V

2.5

Either Hi or Low Bands
No Low Pass Filtering
Rl = 1 kll, C1 = .0021'F I fOUT = 697Hz
C2 = 0,,02I'F
I fOUT = 1633Hz
Rl = 1kll
0.5
RL =1kll
Termi nals 3,4,5,6,11,12,13,14
35
Terminals 3.4,5,6,11,12,13,14

Total Output Harmonic Distortion

I'A

6.0

7
330

ms

700

11

10

I'A

7

pF

±0.75

%

7

ms

Operation above 6 volts must employ supply current Iimiting.'Refer to 'ABSOLUTE MAXIMUM RATINGS' and the Application Notes
for further information,
NOTE 4: The ICM7206 family uses dynamic high frequency circuitry in the initial 23 divider resulting in low power dissipation and excellent per" formance over a restricted frequenc'y range, Thus, for reliable operation with a 6 volt supply an oscillator frequency of not less than
2MHz must be used.
NOTE 5: After row input is enabled.

7·29

,ICM7206 Family

D~DIb,

TRUTH TABLE
LINE
1
2
3
4
5
6
7
8
9
10
11

ROWS (1)
ACTIVATED
0
1
1
2 or 3
2 or 3
1
4'
0
1
2 or 3
4

12
13

2 or 3 or 4
4

COlS (2) ACTIVATED
0
1
2 or 3 (incl. col #4)
1
2 or 3 (excl. col #3)
40r 3 (must excl.col #4)
1
1 or 2 or 3 or 4
0
0
0
4
2 or 3 or 4

OUTPUT
JTERMINAl #15)
Off
trow + Icol
trow
Icol
D.C. Level
Irow, 50% Duty Cycle
fcol, 50% Duty Cycle
Off
902Hz + trow
902Hz
902Hz, 50% Duty,
Cycle
D.C. Level
D.C. Level
/

I

DISABLE
(TERMINAL #7)
Off
On
On
On
On
trow, 50% Duty Cycle
fcol, 50% Duty Cycle
Off
On
On
902Hz, ,50% Duty
Cycle
Indeterminate
Indeterminate

COMMENTS
Quiescent State
Dual Tone
Single Tone
Single Tone
No Tone,
lrow Test
Icol Test
n/a"
n/a'
n/a'
n/a'
Multiple Key Lockout
Multiple Key Lockout

'n/.a - not applicable to telephone calling.
"
'
"
"
Note1: Rows are activated forthe ICM7206/C by connecting toa negativesupply voltage with respect to V+'I terminal161 at least33%ofthe value
of the supply voltage (V'-V-I. For the ICM7206A rows (and columnsl are activated by connecting t6 a positive supply voltage with
respect to V- (terminal 81 at least 33% of the value of the supply voltage (V'-V-). The rows and columns of the ICM7206B are activated
by connecting to a negative supply v o l t a g e . '
,
Note 2~ Columns ('ICM72061 are aC,tivated b'y being connected to a positive supply voltage with respect to V- lIerminal 8) at least 33% of the
value of the supply voltage (V+-V-I.

COMMENTS
All combinations 01 row and column activations are given in
the truth table. Lines 1 thru 7 and 12, 13 represent conditions'
obtainable with a matrix keyboard., Lines 8 thru 11 are given
only for completeness ,and are not pertinent to telephone
dialing:
.

A 'DC LEVEL' on terminal 15 may be, any voltage level
between approximately 1.2 and 4.3 volts with respect to V(terminal 8) for a 5.5 volt supply Voltage.
The impedance of the OUTPUT (terminal 15) is approximately 20K ohms in the OFF state. The 'DISABLE OUT-OUT' ON'
and OFF conditions are defined in the' TYPICAL
OPERATING CHARACTERISTICS.
'

Lines 6 and 7show c0nditions for generating 50% duty cycle
full amplitude signals useful for rapid testing of the row and
column frequencies on automatic test equipment. In all other
cases, output frequencies on terminal 15 are single or dual4
level synthesized sinewaves.'

SCHEMATIC DIAGRAM
_
OSC
OSCILLATOR

23
SEQUENCER

LOW BAND
N

v+ O>---)~~I--O

V-

6.4V

OSC
LP 1

DUAL
DTO A
CONVERTER

HIGH BAND
N

LP 2

OUTPUT
BUFFER
DRIVER

OUTPUT

DISABLE
LOGIC
DRIVER

DISABLE

23
SEQUENCER

CONTROL
LOGIC

4 X COLUMNS

7-30

ICM7206 Family
TEST CIRCUIT (single contact keyboard devices shown)

ROW1--~--__~---+----~----r---~-----r--~

ROW2--~--__~~-+----~----r---~-----r--

__

r-+---~r_+_+_~_.---oOUTPUT

~----~~

-5.5V
ROW3~~--__~---+----~----r---~-----r--~

ROW4--4---~~---+----~----r---~----~--~~~

COL2

COL 1.

COL3

QUARTZ CRYSTAL PARAMETERS
f
= 3,579,545 Hz
RS'';; lOOn
CM = 200 mpF
CO=4.5pF
CL = 30 pF

-5.5V

COL4

TYPICAL OPERATING CHARACTERISTICS

TOTAL HARMONIC DISTORTION
AS A FUNCTION OF LOAD
RESISTANCE

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
100

TA=~5'C

I

16r-------r------,~-----,

I

OUTPUT OPEN CIRCUIT

~

S

~

c:

!3

1.0

__ r-

u

>

~

~

;:
c:
o

II

t-

~

10~--~~~----~------~

697 Hz

Ci

Cl

~

z
o

~

:<

c:

/"

O. 1

TA = 25 C
SUPPLY VOLTAGE = 5.5V
LOAO CONNECTED BETWEEN
TERMINALS 8 AND,15

z
o

I

10


w
o
c:
o

~ -0.5

1.5

I

/

>
t-

~

/

0.75

t-

/

O)

o

0.5

,V
2

SUPPL Y VOL TAG E

V~OW
BAND

V
4

SUPPLY VOLTAGE

7:-31

,,
,,

ICM7206 Family
_
1

STANDARD TELEPHONE
KEYBOARD
---.
COL 1

COL2

COLJ

[J [J
[J [J

ROW 1

ROW2

KEY

1
2
3
4
5
6
7
8
9

COL4

8 Q
D El
c:J D

.

D· [~]
D c:J [J G

ROWJ

ROW4

I·

0
#
A
B
C

·1

FULL KEYBOARD

D

LOW BAND

HI BAND

FREQ. Hz

FREQ. Hz

697
697
,697
770
770
770
852
852
852
941
941
941
697
770
852
941

1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633

FIGURE 1: Keyboard, Frequencies

2.414.

~
L LOW BAND

L HI BAND

SIGNAL

SIGNAL

-)

NO LOW PASS FILTERING
Cl AND C2 REMOVED

APPROX. HIGH AND LOW
2.6Vp-p

~~~~~~~~IES

1". "., ,

REFERRED TO V-

FIGURE 2

Figure 2 shows individual currents of a low band and high band frequency pair
into the summing node A (see Figure 3) and the resultant voltage waveform.

DESIRED
FREQUENCY
Hz

ACTUAL
FREQUENCY
Hz

FREQUENCY
DEVIATION
%

. DIVIDE BY N
RATIO,

697
770
852
941
1209
1336
1477
1633

699.13
766.17
847.43
947.97
1215.88
1331.68
1471.85
1645.01

+0.30
--4--00UT

~~~--+-~-------oLPl

L-____~______~~--_+----------------_Cv,'+5

v+

TIME- -

~

- -

2

....

0
-5

.0

1 1 1 2 1 J

1 4 1 5 I

1

I

I

~:J

7 1 8 1

I

1

-10

2
w -15
lIVIN 13K
~20
I-

'1

«

~ -25

I-

0

-30
-35
100

\
1.
\
v+

13K

1.

21"1

"'l

002

.022pF

:J

TA=25'C

\

,

. VOUT
1K

\

V-

lK

10K

\
lOOK

FREQUENCY (Ho)
OUTPUT WAVEFORM

FIGURE 4: Frequency Attentuation

FIGURE 3: D to A Converter
and Output Buffer

Characteristics of the Output Buffer
7-33

O~OIL

ICM7206 Family
2. Latchup Considerations
Most junction isolated C-MOS integrated circuits. especially
those of moderate or high complexity, exhibit latchup phenomena whereby they can be triggered into an uncontrollable low impedance mode .between the supply terminals.
,This can be due to gross forward biasing of inputs or outputs
(with respect to th9 supplY terminals), hi,gh voltage supply
transients, or more rarely by exceptional fast rate of rise of
supPly voltages.

output going more than 1 volt negative with respect to the
negative supply V- and the circuit operates over the supply
voltage range from 3.5 volts to 15 volts on the device side of
the bridge rectifier. Transients as high as 100 volts will not
cause system failure, although the encoder will not operate
correctly under these conditions. Correct operation will
resume immediately after the transient is removed.
The output voltage of the synthesized ·sine wave is almost
directly proportional to the supply voltage (V+~V-) and will
increase with increase of supply voltage until zener ,breakdown occurs (approximately 6,3 volts between terminals 8
and 16) after which the output voltage remains constant.

The ICM7206 family is no exception, and precautions must
be taken to limit the supply current to those values shown in
the ABSOLUTE MAXIMUM RATINGS. For an example, do
not use a 6 volt very low impedance supply source in an
electrically extremely noisy e'nvironment unless a 500 ohm
current limiting resistor is included in series, with the Vterminal. For norma!' telephone encoding applications no
problems are envisioned, even with low impedance
transients of 100 volts or more, if circuitry similar to that
shown in. the next section is used,

4. Portable Tone Generator
The ICM7206A/B require a two contact key keyboard with
the common line connected to the positive supply (neg for
ICM7206B) (terminal161. A simple diode matrix may be used
with this keyboard to provide power to the system whenever
a key is depressed, 'thus negating the· need for an on/off
switch, In Figure 6 the tone generator is shown using a 9 volt
battery. However, if instead, a 6 volt battery is used, the diode
D4 is not required. It is recommended that a 470 ohm resistor
still be included in series with a negative (positive) supply to
prevent accidental triggering of laIChup.

3. Typical Application (Telephone Handset)
A typical encoder for telephone handsets is shown in Figure
5, This encoder uses a single contact per key keyboard and
prov·ides all other switching functions' electronically, The
diode connected between terminals 8 and 15 prevents the

CD 0 @

R6
S,1K.

'---'-l

@@@
(j) ® ® ,---,--,
CV @ 0

R4
1K

RS
3.3K

.----'LJ

4 X 3 MATRIX
KEYBOARO
(ONE CONTACT
PER KEY)
R2
2,7K

R3
680

R1
2.2K

NOTE: If dual contact keyboard is used, common should be left floating,
FIGURE 5: Telephone Handset Touch Tone Encoder

7-34

ICM7206 Family

COM

O~OIb

CD CD 0
0 ® CD
(2) ® ®
0 @) 0
4 X 3 KEYBOARD
2 CONTACTS
PER KEY

4.7K!' (470!! FOR
6 VOLT SUPPL YI

FIGURE 6:Portable Tone Generator

OPTIONS
(For additional information consult the factory)
a) Selecting the least expensive and most reliable keyboard
b) Selecting the. lowest cost and most available quartz
crystal
c) Minimizing the number of external components
d) Minimizing supply current drain and maximizing operating supply voltage range
.
e) Providing the smallest and least expensive circuit possible .in a 16 lead package
Options can be achieved using metal mask additions to
provide the following.
.' 1) The sequence or position of either the row or column
terminals can be interchanged i.e., row 1 terminal 3 could
become terminal 11, etc.

2) Any frequency oscillator from approximately 0.5MHz to
7MHz can be chosen. Note that the'accuracy of the output
frequencies will depend on the exact oscillator frequency.
For instance, a 1 MHz crystal could b.e used with worst
case output frequency error of 0.8%. Or, if high accuracy
is required, ±0.25%, oscillator frequencies of 5, 117,376Hz
or 2,558,688Hz could be sel.ected. ROM's are used to
program the dividers.
3) The 'DISABLE' output may be changed to an inverter or
an uncommitted d(ain n-channel transistor.
41 The oscillator may be disabled until a key is depressed .

CHIP TOPOGRAPHY

Chip Dimensions
0.060" 11 .524mm) x 0.1 01"
12.565mm)
Chip may be die attached using
_ conventional eutectic ·or epoxy

procedures. Wire bonding may
be either aluminum ultrasonic or

gold compression.

7-35

D~DIb

ICM7215
6.Digit 4·Punction
LED Stopwatch Circuit

FEATURES

GENERAL DESCRIPTION

• Four functions: I>tart/stop/reset, split, taylor, time
out
'
• Six digit display: ranges up to 59 minutes 59.99
. seconds
• High LED drive current: 13mA peak per segment at
16.7% duty cycle with 4.0 volt supply
• Requires only three low cost SPST switches without
loss of accuracy: start/stop, reset, display unlock
• Chip enable. pin tums off both segment and digit
outputs; can be used for multiple circuits driving one
display
• Low battery Indicator
• Digit blanking on seconds and minutes
• Wide operating range: 2.0 to 5.0 volts
• 1KHz multiplex, rate prevents flickering display
• Can be used easily in four different single function
stopwatches or two two-function stopwatches:
start/stop/reset with time-out, split with taylor. The
component count for a three- or four-function stopwatch will be slightly greater.
• Retrofit to ICM7205 for split and/or taylor
applications

The ICM7215 is a fully integrated six digit LED stopwatch
circuit fabricated with Intersil's low threshold metal gate
CMOS process. The circuit, interfaces directly with a six
digit/seven segment common cathode LED display. The low"
battery indicator can be connected to the decimal point
anode or to a separate LED. The only components required
for a complete stopwatch are the display, three SPST
switches, a 3.2768MHz crystal, a trimming capacitor, three
AA batteries and an on-off switch. For a two function stopwatch, or to add a display off feature, one additional slide
switch is required. The circuit divides the oscillator frequency by 215, to obtain 100Hz, which, is fed to the fractional
seconds, seconds and minutes counters, while an intermediate frequency is used to obtain the 1/6 duty cycle
1.07KHz multiplex waveforms. The blanking logic provides
leading zero blanking for seconds and minutes independently of the clock. The ICM7215 is packaged in a 24-lead
plastic DIP.

, BLOCK DIAGRAM

PIN CONFIGURATION
(OUTLINE DRAWING PG)

6 OUTPUTS

OSC OUT
LBIANODE

MULTIPLEX
GENERATOR

OSCIN

2

Seg c

MODE

seg 8

RESET

Seg e
seg <;I

10th.

DISPLAY UNLOCK

Seg g
7 OUTPUTS

seg b
Seg r

1 INPUT

S1
4 INPUTS

>-----;

TEST
START/STOP

~10UTPUT
BATT.

ORDERING !NFORMATION
Order devices by following part number ICM7215 I PG
Order dice by following part number ICM7215/D

7·36

S10

100th.

9

vCHIP ENABLE
M10
M1

ICM7215
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .........•••......•....•...•...•.....••.....••...•..••.... 5.5 V
Power Dissipation (Note 1) ' .............................................. 0.75 W
Operating Temperature ...•..•..................•.•.•••....••.. -20°C to +70°C
Storage Temperature .•..•..•...••...••... : ....••••....•....•. --55°C to +125°C
Input a'nd Output Vciltage '....... equal to but never exceeding the supply voltage
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS:
TEST CONDITIONS: TA =+25°C, stopwatch circuit, V+ =4.0V unless otherwise specified.
PARAMETER

CONDITIONS

MIN

Supply Voltage

V+

SYM

-20°C < TA < +70°C

2.0

Supply Curre'nt

1+

Display off

Segment Current

ISEG

5 segment,s lit

Peak

TYP
0.6

MAX

UNITS

5.0

V

1.5
mA

1.8 Volts across display

9.0

Average

13.2
2.2

Switch Actuation Current

Isw

Switch Actuation Current

All inputs except chip enable

20

50

Chip enable

50

200

Digit Leakage Current

IOLK

VOIG = 2.0V

50

Segment Leakage Current

ISLK

VSEG = 2.0V

100

p.A

-

Low Battery Indicator
Trigger Voltage

VLBI

LBI Output Current

ILBI

Oscillator Stability
Oscillator Transconductance

fSTAB
gm,

Oscillator Input Capacitance

Cosel

2.2

= 2.0V, VLBI = 1.6V
V+ = 2.0V to V+ = 5.0V
V+ = 2.0V
V+

2.8

V

2.0

mA

6

PPM

120
24

p.mho
30

pF

36

NOTE 1: The output devices on the ICM7215 have very low impedance characteristics, especially the digit cathode drivers, If these devices are
shorted to a low impedance power supply, the current could be as high as 300mA. This will not damage the device momentarily, but if
the short qircuit condition is not removed immediately probable device failure will occur.

STOPWATCH CIRCUIT

M1

S10

S1

10th.

100thB

t
13

t
12

t
11

t
18

17

t

v+
QUARTZ CRYSTAL
PARAMETERS
f = 3.2768MHz
RS=500'
CM'=23mpF
CO = 14pF
CL = 15pF

ROTARY SWITCH WITH
TWO DECKS, GANGED TOGETHER

1-----.S"'TAa"RT/STOP N.O.
i - - - - - - - - i RESET

N.O.

N.O. NORMALLY OPEN
_TO DISPLAY
7·37

SWITCH TRUTH TABLE
SWITCH MODE
POS.
(21)
MODE
START/STOP/RESET
1
FLOAT
SPLIT
2
v+
TAYLOR
3
VTIME·OUT
4
FLOAT

DISPLAY ,
(19)

FLOAT
UNLOCK
UNLOCK
V-.

D~DIl.

ICM7215
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VS VOLTAGE

SEGMENT CURRENT VS SUPPLY VOLTAGE·

<

_ 0.8 DISPLAY OFF

1

TA =+25°C

/

!zw 0.6
~

I\.

:::I

0.2

I/)

/.

I-

V

:IE

/'

CI
W 5

':11:

~O

4.0

5.0

/
3.0

4.0

LOW BATTERY INDICATOR (LBI)
TRIGGER VOLTAGE VS TEMPERATURE

~ 2.9

....

/

~

V

W

~
2.7

"'

CI

'"

,/

!:io

/

2.5

>
II:

~2.3

'"

.........

CI

~

3,0

2.0

5.0

SUPPLY VOLTAGE (V+)

I

TA = +25°C
COUT = 22pF

/'

,

2.0

OSC.STABILITYVSSUPPLYVOLTAGE

V

V

I\.

SUPPLY VOLTAGE (V+)

I

:;

.//

."

!zw 10
I/)

3.0

/

/

~ 15

:::I
U

0.0
2.0

I

.W

I

/

V,

I

VF(LED) = 1.8V

Z

V

II:
II:

a0.4

I

. .§. 20 TA = +25°C

4.0

iii
....

5.0

2.1
-10,0

SUPPLY VOLTAGE (V+)

10

'"

30

.........

50

TEMPERATURE (OC)

16~-----FUNCTIONAL OPERATION

START/STOP/RESET MODE

Turning on the stopwatch will bring up the reset state with
the fractional seconds displaying 00 and the other digits
blanked. This display always indicates that the stopwatch is
ready to go.
.
The display can be turned off in any mode by connecting the
chip enable input to V+.

When the mode input is floating and the display input is floating or connected to V: the circuit is in the start/stop/reset
mode.

/

(,",,-,

'-"-'

RESET

PRESS
START/STOP
ONCE

CC
,_.:; -,'U_'
CLOCK AND
DISPLAY COUNTING

DISPLAY STOPS
PRESS
START/STOP
'ONCE

The start/stop/reset mode can be used for single event
timing il) a one-button stopwatch; an additional switch clln
be used to provide an instant reset. To time another event, .
the display must be reset before the start of the event.
Seconds will be displayed after one second, minutes after

7-38

RESET
PRESS
START/STOP

ONCE

one minute. The range of the stopwatch is 59 minutes 59.99
seconds,. and if an event exceeds one hour, the number of
hours must be remembered by the user. Leading zeroes are
not blanked after one hour.

ICM7215
:rAYLOR OR SEQUENTIAL MODE
When the mode input is connected to V-, the stopwatch is in
the taylor or sequential mode~

,-,,-,
CLOCK AND
DISPLAY COUNTING

RESET

'PRESS
START/STOP
ONCE

IC ':/.J

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING
PRESS
START/STOP
ONCE

- - - - 20.47

-, I I

1-' -,,-

-''-;1',I

Cu -,

ULI

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING
PRESS
DISPLAY
UNLOCK
ONCE

PRESS
START/STOP
ONCE

sec.--,----...- - - 1 2 . 3 5 88c.-----_"------42.79 s e c . - - - -

,-,,-,

,,-,

'-' '-'

C, '0
CLOCK AND
DISPLAY COUNTING

RESET

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
START/STOP
ONCE

PRESS'
RESET

Each split time is measured from zero in the taylor mode; i.e.,
after stopping the watch, the counters reset momentarily and
start counting the next interval. The time displayed is that
elapsed since the last activation 'cif starVstop. The display is'

stationary after the first interval unless the display unlock is
used to show the running clock. Reset can be used at any
time.

SPLIT MODE
When the mode input is connected to V+ the stopwatch is in
the spJit mode.

,-,,-,

",-,,-;
,0

U,-,

1/11'-,
-"

CU

I -,

RESET

CLOCK AND
DISPLAY COUNTING

_, L

'-' '-

LAP 1
DISPLAY STOPS
LAP 2
DISPLAY STOPS
CLOCK CONTINUES COUNTING CLOCK CONTINUES COUNTING

PRESS
START/STOP
ONCE

PRESS
START/STOP
ONCE

':;:'O.J

STOP

PRESS
START/STOP
ONCE

PRESS
DISPLAY
UNLOCK
OIliCE

_ - - - 20.47 s e c . - - - _ - - - 12.35 s e c . - -____- - - - 42.79 s e c . - - - -

ue
,,-,
,_, ,0
CLOCK AND
DISPLAY COUNTING

"
'-'

,,-

,-, ,-,
'_'U

,:,.:; 0

DISPLAY STOPS
CLOCK CONTINUES COUNTING
PRESS
START/ST,OP
ONCE

RESET

PRESS
RESET

The split mode differs from the taylor in that the lap times are
cumulative in the split mode. The counters do not reset or
stop after the first start until reset is activated. Time

displayed is the cumulative time elapsed since the first !ltart
after reset. Display unlock can be used to let the display
'catch up' with the clock, and reset can be used at any time.

7-39

ICM7215
TIME OUT MODE
When the mode input is floating and the display input is tied
. to V-, the stopwatch is in~he time-out mode.

,-,,-,

,-,~

DO

:;,-, 1,,;.' -;
eLI , I

'-"- -"-'

ULI

CLOCK AND
DISPLAY STOPS
DISPLAY COUNTING
CLOCK STOPS
PRESS
PRESS
PRESS
START/STOP
START/STOP
START/STOP
ONCE
ONCE
ONCE
20.47 aec.-----o_--- TIME OUT

RESET

-----0_-- 22.32 sec.

'II'

,-,,,

uJ
,0
'L ,_,

C" -,I '0

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

L"_'

- DISPLAY STOPS
CLOCK STOPS

RESET

,

PRESS
RESET

-----~---.

be used at any time. The display unlock button is bypassed in
this mode.

In the time-out mode the clock and display alternately start
and stop with activations of the starVstop switch. Reset can

APPLICATION NOTES
LOW BArTERY INDICATOR

SWITCH CHARACTERISTICS

_

The on-chip low battery indicator is intended for use with a
small LED or the decimal points on a standard LED display.
The output is the drain of a p-channel transistor two-thirds
the size' of the, segment drivers, and'designed to provide a
trigger voltage of approximately 2.5. volts at room
temperature. Normal AA type batteries will provide many
hours of accurate timekeeping after the indicator comes on,
however the wide voltage spread between the LSI voltage )
and minimum operating voltage is req'uired to guarantee low
battery indication under worst case conditions.
•

The ICM7215 is designed for use with SPST switches
throughout. On the display, unlock and reset inputs the
characteristics of the switches are unimportant, since the
circuit responds to a logic level held for any length of time
however short. Switch bounce on these inputs does not need
to be specified. The starVstop input, however, responds to
an edge and so requires a switch with less than 15ms of
switch bounce. The bounce, protection Circuitry has been
specifically designed to let the circuit respond ,10 the, first
edge of the signal, so as to preserve the full accuracy of the
system.

_

CHIP ENABLE

'

.

.
LATCHUP CONSIDERATIONS

The chip enable, input is used to disable both segment and
digit drivers without affecting any of the functions of the
device. When the chip enable input is floating or connected
to V-, the display is enabled, and when the tied to V+ the
display is turned off. One example of the many possible uses
of this feature is driving one display from two ICM7215
devices, one in the split mode and the other in the taylor
mode. The circuit below indicates how the user can obtain
lap and cumulative readings of the same event.

'I~

_______

D_IS_P_LA
__
Y ______

TO DISPLAY

ICM7215
SPLIT

Due to the, inherent structure of junction isolated CMOS
devices, the circuit can be put in a latchup mode if large
currents are injected into device inputs or outputs. For this
reason special care should be taken in a system with multiple
power supplies to prevent voltages being applied to inpuis
and/or outputs before power is applied to the 7215. If only
inputs are affected, latch up can also be prevented by limiting
th~ current into the input terminal to less than 1mA.

~
TO DISPLAY

"1 r----~-+--!

-+-__-124

241-_ _

~_______
1~5~

ICM7215
TAYLOR

~1~5________~

v+
TAYLOR SPLIT
ALL OTHER SWITCHES COMMON TO BOTH DEVICES

7·40

ICM7215

, <

OSCILLATOR TUNING

OSCILLATOR DESIGN
, The oscillator of the ICM7215 includes all components on
'chip except the 3.2768 MHz crystal and the trimming
capacitor. The oscillator input capacitance has a nominal
value of 30pF, and the circuit is designed to work with a
crystal with a load capacitance of approximately 15pF. If the'
crystal has characteristics as shown on page 3, an 8"40pF
trimming c,apacitor will be adequate for a tuning tolerance of
,±30PPM on the crystal. If the crystal's static capacitance is
significantly, lower, a narrower trimming range may be
selected.
After dec'iding on a crystal and a nominal load capacitance,
take the worst case values of Cin, Cout 'and Rs and calculate
the gm required by:
'•

gm = w2 Cin Cout Rs
Co
Rs
Cin
Cout

{ '1

+ Co

(Cin + Cout)} 2
Cin Cout

Tuning can be accomplished by using the 10th or 100th
seconds with the device reset. The frequency onthe cathode
should be tuned to 1066.667 Hz, which is equivalent to a
period of 937.5 microseconds. Note that a frequency counter
cannot be connected directly to the oscillator because of
possible loading.

TEST POINT
The test point input is used for high speed testing of the,
device. When the input is pulsed,low, a latch is set which
speeds up counting by a factor of 32; each pulse on the test
point rapidly advances both minutes and seconds ,ina
parallel 'mode. To accurately rapid advance the signal' '
applied to the test point must be free of switch bounce. The
circuit is taken out of the test mode by using either reset or
, startlsto~

REPLACING THE ICM7205 WITH THE ICM7215

static capacitance
'series resistance
input capacitance
output capaCitance
'w
2rr x crystal frequency
The resulting gm should be less than halfthegm specified for
the device. If it is not, a lower value of crystal series
resistance and/or load capacitance should be specified.
=
=
=
=
=

The ICM7215 is designed to be compatible with circuits
using the ICM7205. If the 7205 is used only in the split mode
no changes are required. If the 7205 is used in the taylor
mode and the split taylor input (pin 21! is left open, a jumper
from pin 21 to V- must be added when converting to the 7215.
A jumper may also be needed if the 7205 is used with a split!
taylor switch. Once the jumper has been added the board
can be used with,either device.

CHIP TOPOGRAPHY

START!
STOP
MODE

V+

sege

sega

RESET

sege

DISPLAY
UNLOCK

115 mils
(2.921)

10th.

segd
'100lhs
segg

v-

segb

CHIP
ENABLE

seg!

S1
,1(11-------106
1..

mil. - - - - - .

(2.692)

PAD SIZE 5 lc 5 mils'

(0.127 x 0.127)

7·41

'

II

ICM7223
4-Digit LCD Clock
Circuit with
Snooze Alarm

U~Ull

FEATURES

GENERAL DESCRIPTION

• 3-1/2 or 4 digit ~isplay with AM/PM and alarm flags
• 12/24 hour user selectable formats
• Direct alarm drlve@3V pop, with complex (cricket)
alarm tone
• 8 minute snooze (Dice programmable from 2 to 14
- minutes In two minute increments)

The ICM7223· is a fully i I!teg rated 4-digit LCD clock
circuit with 24 hour alarm and 8 minute snooze timer.
For high accuracy and. low power consumption a
32.768. KHz quartz watch crystal is usedas the time
base, and the number of external components has .
l5een reduced to a minimum.
' .
The time keeping and alarm time counters are split
during setting; allowing hours and minutes to be set
independently, each at a 2 Hz rate. A 'time hold' mode is
entered when setting m·inutes; seconds are automatically reset to zero. The clock starts when the RUN
mode is entered, thereby permitting synchronization
of the clock to the nearest second: Seconds are not
displayed_.
The ICM7223 is fabricated using ·'ntersi"s low
threshold metal gate CMOS process for minimum cost
and long battery life.
'

• Single battery operation (1.5V)
• Low current - 6 p.A maximum
• On-chip fixed oscillator Input capacitor
• 32 kHz oscillator requires only quartz crystal and
trimming capacitor
• Voltage tripler fo-r large displays

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM72231PL

-20°C to +70°C

40 Pin Plastic DIP

ICM7223D/D

-20°C to +70°C

DICE

BLOCK DIAGRAM

PIN CONFIGURATION
(OUTLINE DRAWING PL)

osc IN

esc OUT

Vi

CAP 3 CAP 2 CAP ~

PM(+~~ +}:a~)

V;
-4.5VTO
DISPLAY
OUTPUTS
SET AND DISPLAY
1 H.

12/24

CONTROL
LOGIC

F2

AM(B11

G2

BP

E2

HRS/MINS ADV

02

RUN/SET

92

OSCIN

RUN/SET

HRS.IMIN.

12/24
OSCOlJT

~ADVANCE

D--~-==!==-~

'COLON

v'

F3

v-

ALARM OFF

AL 2

---:resr-

AL 1

AL 2
A3+03
AL 1

ALOFF/ffiT

C3

SNOOZE

B3

v-3

F4

C~P3

G4

CAP,

CAPl

BACKPL~NE

+ 26 SEGMENTS

~v+ ~

Vi

SNOOZE

l-l.5VI

7-42

04

A4

C4

B4,

PARENTHESES AND BOLD TYPE INDICATE
24 HOUR OPERATION

ICM7223
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..•••....•• -55°C to +125°C
Operating TemperaturE! •••....••• -10°C to +60°C
Power Di'ssipation l11 ••..•.••...••..•• ; .••. 100 mW
Supply Voltage l21
V+-Vl ••••••..•.• : •..•••..•...•.•..•. -: •.. 2.0V
V+-V"3 ...•..•••.•....••••....•••....•••... 5.5V
Input Voltage (Osc. In, Test,
Set, Display) ••••.•..•••••• • . • . •• V- :5 VIN :5 V+
Output Voltage (Osc. Out, 512) ..... V1':5 \tOUT:5 V+
(All Other Pins) ...••••.......•..... V'3:5 VOUT:5 V+

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the'devicesat
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

OPERATING CHARACTERISTICS
TESt CONDITIONS: V+-V-

=

=

1.55V, voltage tripler connected, TA
25°C, Test Circuit,
unless otherwise specified, voltages and currents are shown as absolute values.

PARAMETER

SYMBOL

CONDITIONS

Supply Voltage

V+

V

Supply Current

1+

Display Disconnected

Tripier Output Voltage

Vi

13 == 0.0 p.A
13 = 1.0 p.A

MIN.

= OV -10 0 0 < TA < 60°C

MAX.

4

UNITS"

1.8

Volts

6

p.A

4.2

V

4.1

= 0.2V (Both Directions)
= 0.1V (Both Directions)
Vsw = V+or Vsw = V3

Segment Drive Current

ISEG

VSAT

5

Backplane Drive Current

IBP

VSAT

20

Switch Actuation Current

Isw

Alarm Saturation Resistance

TYP.

1.2

p.A
p.A
3

5

P-CH at 1 mA

P-CH

350

500

N-CH at 0.5 mA

N-CH

1500

1800

RAL(ON)

Oscillator Stability

fSTAB

V = av, 1.20V::; V+ S; 1.55V,
COUT = 25 pF

Oscillator Input Currentl 31

IOSCI

'OSC IN' Connected to V+
'OSC OUT Open Circuit

0

2

PPM

Q.2

p.A

Oscillator Input Capacitance

CIN

20

25

Oscillator Transconductance

gm

10

15

Notes:
1. The .ICM7223 is fully short circuit protected on all inputs and
outputs. However, if by forward biasing an input or output the
device is put into a latchup condition, power dissipation must be
limited to 100 mW to prevent destruction of the device.
2. The ICM7223 is intended for use with two power supplies, one of
which is derived from an external battery v1' and the other is
generated internally by .the voltage multiplier 1\13 The common
point of the two supplies is the most positive, v+. If desired the

p.A

30

pF
p.mho

TYPICAL APPLICATION
26 LINES TO DISPLAY
TIME SET
DISPLAY OUTPUTS

OSCIN

0 - - - 0 V'
RUN = FLOAT

RUN/SET
CRYSTAL

c::::::::J

0 - - - 0 Vi
HRSADVANCE

0 - - - 0 V'

OSCOUT

HRS/MIN
ADVANCE

ICM7223

MIN ADVANCE

O---OVj

5-35pF

v'

SNOOZE
SNOOZE 1---<1'" 0 - - - 0 y+

o - - - - " i 12124 HR
FLOAT = 12HR

v+

ALOFF

=24HR

NOTE: ALL CONTROL INPUTS HAVE
INTERNAL PULLDOWNS TO V;CRYSTAL PARAMETERS:
f = 32,768 Hz
-CL=10pF
eM '" 2.5mpF
Rs = 20Kn

ALARM
TRANSDUCER
14kHzI

Ii

circuit can be supplied with an external V'S by disconnecting the
multiplier capacitors, or 113 and V1' can be tied together (for a 1.51
volt display for instance).
I
3. The integrated oscillator biasing components have a nonlinear
characteristic depending on the instantaneous values of the input
and output voltages of the oscillator 'and the supply. Under
oscillator startup conditions this component has a maximum
value.
.

1.5V

T·05~F

bv;
7.·43

ALARM OFF
0--0 V'

ICM7223
·TYPICAL PERFORMANCE CHARACTERISTICS.
SUPPLYCURREN:r VS. SUPPLY VOLTAGE

OIS~LAY IOlSC6NNEdTEO

OSCILLATOR STABILITY VS. SUPPLY VOLTAGE

i'
a.

,

,

!!o
2

/

<
.:!.
f2

w

a:
a:

::>
u

...

>

a.
a.
::>
II)

0

4.0

2.0

----

V

V

w

+1

2

0

c
>
U

V

5.0

·3.0

<

;;:

~

6.0

+2

;:

,

w

V
-"

~

::>

0·'

w

rr
rr

LL

-1

I'!<

-2

......<:;

-

~

--'

v
V

.",

V

II)

p

1.0
1.2

1.5

1.8

1.2

2.0

1.8

1.5
SUPPLY VOLTAGE (VOLTS)

SUPPLY VOLTAGE (VOLTS)

ALARM DRIVER OUTPUT CURRENT
VS. OUTPUT VOLTAGE

VOLTAGE MULTIPLIER OUTPUT VOLTAGE
VS. OUTPUT CURRENT

.. P CHANNEL OUTPUT VOLTAGE

-20

-

~
~

!r
w

[:]==t::t~::E:T5R~IP~L~ER~~~-~I.~~Vj·
4.0
1--+--I----1'--+--!--I---'+-'+--+--I

3.0

C:J==t::t~::E:~RI~PL~E~R~~~'~I~.~:j

",.

g~

!5
~
o

2.5

- 10'

~+=,1.~ ?

V+
3.5

-15

1.5

-05
~

..A
17

VI
3

=1.55~

4

a.

"".

::>
a.f-<
::> E
0... fw2

1.0

<::>

0.5

Z~.
2a:

1--+--I----1I-+--!--I-+-+-+--I

52 U

V+

V

o1/
o

·v
.0.5

1.0

=f.55V

=1.2V,
1.5

2.0

N· CHANNEL OUTPUT
VOLTAGE (VOLTS)

OUTPUT CURRENT I;' ("AI

\

NORMAL CLOCK OPERATION

RUN

1",

MODE
COLON FLASHES

AT 1 Hz RATE

In normal operation, hours and minutes are displayed
with the colon flashing at a 1 Hz rate. An AM and a PM
indicator flag is provided in the 12 hour mode, while in .
the 24 hour mode, the pads used for the AM/PM flags
are utilized to drive the segments which produce the
numeral "2" in the tens of hours digit. The alarm flag
will be on if the alarm is enabled, and off if the alarm is
not enablep; (Alarm Off input at V+).

7-44

ICM7223
TIME SETTING

~~~E

PM

C':DD~

PM

~

COLON STILL FLASHING
NO CHANGE IN DISPLAY

PM

PM

l:DDi--=-==-I 1:56

__~~~~

L __~~~~

HRSADVANCE
AT 2 Hz RATE
COLON STILL FLASHING

•

~~~(j~D~~~~tls~~~G

1:56

COUNTERS START RUNNING
COLON STARTS FLASHING

SECONDS RESET TO ZERO

TIME HOLD MODE

NOTE: When the HRS/MIN Advance input is activated
be a pause of less than one second before the
there
counters start advanciQg at a 2 Hz rate.

will

TIME SETTING
To set the time, the RUN/SET switch is placed in the
Time Set position, and the HRS/MIN advance input is
used to advance the hours or minutes. Theseconds are
reset to zero .and coun.ting is stopped whenever the
minutes are set. The clock will start when the RUN/SET
switch is put back into the RUN position, and while in
the RUN position, inputs from the HRS/MIN advance
switch are disabled to prevent accidental setting.

After 8 minutes the alarm will again sound, and will
continue for 2 minutes and stop unless ALARM OFF is
used or another Snooze cycle is activated. The Snooze
may be repeated as many times as desired.

NOTE: In die form, all the SNOOZE input pads are
available, allowing the manufacturer or user to select
snooze times from 2 to 14 minutes in 2 minute steps.
These pads are identified asSN1, SN2 and SN3. See
the, following table for the selection of Snooze times:

ALARM OPERATION

INPUT CODE (1 = V+)
SN1
SN3
SN2

The alarm comparator provides a 24 hour alarm in both
12 and 24 hour modes. When the time of day and alarm
times are equal, the alarm outputs are enabled,
providing that the ALARM OFF input is at Vi". If the
ALARM OFF input isatV+, the alarm outputs will notbe
enabled. The alarm outputs provide a push-pull, or
bridge, configuration for direct drive of a piezoelectric
transducer, and if increased drive (loudness) is
desired, a coil and external NPN transistor may be
used. The external transistor should be driven by the
ALARM 1 output. The coil DC resistance should be
1000 or greater, to limit the peak current to less than
13 mAo

SNOOZE
TIME

0

0

0

None

0

0

1

2 minutes

0

1

0

4 minutes

0

1

1

6 minutes

1

0

0

8 minutes

1

0

1

, 10 minutes

1

1

0

12 minutes

1

1

1

14 minutes

ALARM SETTING

The alarm signal is a complex waveform that generates
the Intersil Cricket sound. The alarm output will
automatically stop after one minute unless either the
ALARM OFF or the SNOOZE input is used. The alarm
transducer should be selected to provide maximum
output (loudness) at 4 kHz, that is, it should be
resonant at 4 kHz.

HRSADVANCE
AT2Hz RATE

SNOOZE OPERATION
A momentary closure of the SNOOZE switch to V+ w'lI
silence the alarm and start the snooze timer. The
Snooze input must be activated during the one minute
the alarm is soundin~ in order to start a Snooze cycle.

MIN. ADVANCE
AT 2HzAATE

The alarm time is set by switching to' Alarm Set, then
using the HRS/MIN ADVANCE input to set hours and
minutes. The alarm time is displayed only when the
RUN/SET switch is in the Alarm Set position.
7-45

ICM7223
SNOOZE OPERATION
24 HOURS
LA~ER

\

ALARM
SOUNDS

PRESS
SNOOZE
BUTTON
ONC~

-

ALARM
DISABLED

BMIN.
LATER

ALARM
SOUNDS

PRESS
SNOOZE
BUTTON
ONCE

2MIN.
LATER

_ALARM_
OFF

ALARM
DISABLED

t--

ALARM
DISABLED

NOTE: IF ALARM OFF IS LEFT AT V+ THE ALARM WILL NOT SOUND 24 HOURS LATER.

APPLICATION NOTES.
ALARM DRIVE
The ICM7223 alarm output transistors are capable of
directly driving a piezoelectric ceramic transducer at 3
volts peak-to-peak. Any transducer that' does not
require ..more than 1 mA of peak current may also be
used. The transducer should generate maximum
output at'4 kHz. If a louder sound is desired, buffering
(using an NPN transistor and 5 mho coil) or sound
enhancement techniques such as a resonant cavity or
diaphragm will be 'required. See Application Bulletin
A031 for details ..

volt supply. The oscillator is of the inverter type with a '
nonlinear feedback resistor included on chip, which
has a maximum ,reSistance under startup conditions~
The nominal load capacitance of the crystal should be
less than 15 pF; typically 12 pF. In speCifying the
crystal, the motional capacitance, series resistance
and tuning tolerance have to be compatible with the
characteristics of the circuit to insure startup and
operation over a wide voltage range under worst case
conditions.
'
The following expressions can be used to arrive at a
, crystal specification:'
.
Tuning range

TEST MODE'

7

The high speed test .mode for automatic testing is
entered by pulling the ALARM OFF/TEST Input to ~7
volts referenced to V1. In this- state the HRS/MIN
ADVANCE input will advance. the appropriat.e counters
at the rate that the input is toggled. The colon will
appear to stop flashing .as it is changing state more
rapidly than the display can respond. In the run mode
the minutes will change at a 4:27 Hz rate, as the clock
has been speeded up by a factor of 256 Hz. 'The
backplane frequency will be 512 Hz. The voltage tripler'
drive.trequencies remain thesameasin normal modes.
ALARM AND DISPLAY TEST
If the ALARM OFF and SNOOZE buttons are pushed
simultaneously, all segments of the display'will be
turned on and the alarrri will sound, while none of the
time counter contents are disturbed.

VOL TAGE MULTIPLIER
The ICM7223 voltage multiplier may be utilized only in
a tripler. configuration; only' four pins, and three
external c"apacitors are required. The connection of the
capacitors differs from that used in 'standard watch
circuit· type voltage' multi piers, therefore close
attention should be paid to substrate design to ensure
the proper connection o~ the capacitors.
OSCILLATOR
The oscillator .of the ICM7223 is designed for low
frequency operation at very low currents from a 1.55

~f

_

T -

'
Cm
C _ CIN COUT '
2 (CO + CLI; L -CIN + COUT

gm required ,for startup
. gm=. 47T2f2 CIN COUT Rs ( 1 + CO)2
CL
.

where
Rs = Series R,esistance of Crystal
f
= Frequency of the Crystal
,if
= Frequency Shift from Series Resonance
Frequency"
.
Co = Static Capacitance of Crystal
CIN = Input Capacitance
.
COUT= Output Capacitance
CL = Load Capacitance of Crystal
C m = Motional Capacitance of Crystal
The gm reqIJired for startup calculated should not
exceed 50% of the gm guaranteed for the deviCE!.
POWER UP RESET
An onchip circuit is provided that will reset all counters
and flip-flops to a known state when 'power is first
applied. The alarm and timekeeping counters will bel
reset to1 :OOam in the 12 hr. mode and 0:00 in the 24 hr.
. mode. This function is' not tested during automatic
testing, as it dO,es not affect normal circuit operation.
7·46 ,

ICM7223
DISPLAY

D·

r-------------------------~

: . (J)fM]

~~{2:

:I tre IrB f trB fff(I
1'0 fJ B fJ f e8 BB
Fl

MOTOROLA MLC406
BECKMAN
737-01
LAOCOR
LAD-DOl
HAMLIN
3411
TIMEX
Tl00l
COCKROFT CII202

B1

F2

l~.

B2

F3

~

~

I~
~
L _____________

C

0

P

0

C

1

1112222

F

G

II

A

f

G

e

E

111

0

, ,,

C

B

A

L

~

.

~
~
___________

E

0

C

B

AFGEOCBAZB

1

3

J

J

l

................

,

.

~.

COCKROFT CII201

CHIP TOPOGRAPHY
ICM7223
A3
+

120 (3.0"8)--.....,..

80 (2.0.'2)----..-

40 (1.0116)---

20 (0.508)---.d

CHIP DIMENSIONS: 116 x 147 mils (2.95 x.3.73 mm)

7-47

:

~

G

- --,•

L

B4

3

"W!jl·

NUMBERS

F4

F

"

DISPLAY FONT

B3 .

, ,,
Z

E

iI

~

,

ICM7223VF
3·1/2 Digit Vacuum
.Fluorescent Clock Circ"it·
With Snooze Timer
'and Sleep rimer
FEATURES

GE.NERAL DESCRIPTION

• 3-1/2 digit display with' AM/PM, sleep timer, and
alarm flags
.

The ICM7223VF is a fully integrated 3-1/2 digit Vacuum
Fluorescent clock circuit with 24 hour alarm, and-sleep
and snooze timers; For high accuracy and low power
consumption a 32.768 kHz quartz watch crystal is used
as the time base, while the number of external compo~
nents has been reduced to a minimum: The vacuum
fluorescent display outputs are static, or nonmultiplexed, thereby elimimiting radio frequency interference (RFI).
The time keeping and alarm time counters are split
during setting, allowing hours and minutes to be set
independently, each at a 2 Hz rate. A 'time hold' mode is
entered when setting minutes; seconds are automati. cally reset to zero. The clock starts when the RUN mode
is entered; this permits synchronization of the clock to
the nearest second. Seconds are not displayed.

• . Direct alarm drive with complex (cricket) alarm tone
plus radio enable for clock radio applications
• 8 minute repeatable programmable sno~ze
. • Programmable sleep timer
.• Wide operating voltage range -;- 4 t015 volts
• Low current -12/LA @ 12V with display off
• On-chip fixed oscillator Input capacitor
• Uses standard 32.768 kHz crystal
• Display control blanks display for auto and travel
clock applications

ORDERING INFORMATION

Pari
Number
ICM7223VFIPL
ICM7223VF/D

BLOCK.
DIAGRAM

Temperature
Range

Package

-20°C to +85°C

40 Pin F'lastlc DIP ,

• -20°C to +85°C

OSCIN

.The alarm employs a snooze timer that may be programmed from 2 to 14 minutes in two minute increments;
the sleep timer may be set from 8 to 56 minutes in 8
. minute increments. The alarm outputs consist of a complex (cricket) alarm tone to directly drive a speaker or
piezoelectric transducer and a radio enable output which
allows control of a clock radio.
The ICM7223VF is fabricated using Intersil's low
threshold metal gate CMOS process for minimum cost
and long battery life. Current drain at 12 volts is
typically 12/LA with a maximum 9f 25~ (display off).

Dice

OSCOUT

DIVIDER CHAIN

c=-"t-~rL_-~~~-~-~-~-~-:-:-~-_J~~~~c"tl-"-.j-r-SE=T-A=ND~D-ISP=L-A-y1----u
CONTROL
LOGIC

1 Hz

RUN/SET

1------,10 ~~::~E

r----l---I:J ALARM OFF
~

Hl»---io~~R~~E '
~__- r____j-i>--{JALOUT

26 SEGMENTS OPEN
DRAIN P·CH OllTPlITS

v+

(GND)

V-

(-12VI

7-48

VREG

SN3

SN2

SN1

O~OIb

ICM.7223VF
PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

(OUTLINE DRAWING PL)

B1+C1

PM

F2

AM

G2

ALARM FLAG

E2

DISPLAY CONTROL

02

HRS/MINS ADV

C2

RUN/SET

B2

VAEG

A2

OSC IN

COLON

OSCOUT

F3

V+IGNDI

,G3

v-

E3

A3+D3

§,.torage Temperature .........•... -55°C to +125°C
Operating Temperature ...••......... -20°C to +85°C
Power Dissipation)1 1 ••••••••••••••••••••••• 500 mW
Supply Voltage (V+ - V-) ............. ',' : ...... 18V
Input Voltage
(OSC IN, SN1, SN2, SN3) ....• -2V:::; VIN :::; V+ + 0.3V
(RUN/SET, HRS/MIN ADV,
AL OFF/TEST) .....• V- -0.3V:::; VIN:::; V+ + 0.3V
Output Voltage
(OSC OUT) .................... -2V:::; VOUT:::; V+
(AL OUT, RADIO ENABLE,
All Segment Drivers) .•.....•... V-:::; VOUT :::; V+

RADIO ENABLE
ALOUT

C3

ALOFF/TEST

B3

SNOOZE 3

F4

SNOOZE 2

G4

SNOOZE 1

E4

SLEEP FLAG

04

A4

C4

B4

, NOTE: Stresses 'above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only. and functional operation olthe device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure 'to absolute maximum rating conditions for
extended periods may aifecl'device reliability.

NOTE: CONSULT FACTORY IF 24 HOUR TIME
DISPLAY IS DESIRED.

OPERATING CHARACTERISTICS All testing at 25°C; All numbers stated in absolute value
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

15

V

"

Supply Voltage Range
Timekeeping Accurate
Supply Current
Supply Current Display ON (2) ,

V+

1+

Segment Output
Saturation Resistance

RSEG

Oscillator Input
Capacitance

CIN

Oscillator Stability

fSTAB

Alarm Saturation Resistanc,e

RAL(on)

Switch Actuation Current

4
Display OFF V+ - V- =12V
V+.:...V = 12V, Display
Test, NEC LD8164

12·

25

3

los = 1mA P-ch
20

p.A
mA

1000

1500

n

25

30

pF

"

Isw

5V::; VSUPPLY::; 15V
P-ch at 10mA
N-ch at 10mA

0.7

1.0

ppm

220
100

300'
150

n
n

I!SW = V+

10

30

p.A

Vsw=V

10

30

p.A

NOTES: 1. This valueD! power dissipation is that of the package and will not be obtained under normal operating co'nditions.
,
2. Chip current plus display anod~ current only; does not Include display filament or grid currents.

7·49

(

ICM7223VF
TYPICAL CLOCK RADIO APPLICATION
CRYSTAL PARAMETERS:
F'= 32,768 Hz
C, = IOpF

c" ... 2.5 mpF
RS'20kn

,-----1 OSC IN
I

CRYSTAL

RUN/SET

1--_.-1---'

A~~:'c\~

1--_-+___-'

c:::J

,---:*F---+---t OSC OUT
ICM7223VF '

5 - 30pF

+-----'-11------1

DISPLAY

VREG

O.47pF
AL.OFF

AL~~~ I---~---o~~---+
SN3

SN2

'SNI
.SLEEP

...&...

10------+
I
I

TORAOIO
'V' SUPPLY

I

...&...

.-------oG------+
IDPST PUSH BUTTON)

SNOOZEISLEEP
PROGRAMMING

SNOOZE

...&...
(SPST PUSH BUTTON)

OSCILLATOR STABILITY vs. SUPPLY VOLTAGE

SUPPLY CURRENT va. SUPPLY VOLTAGE
so

'.5

4E

,.

0

40

i

...I

B

ili

~

35

'e
8:

30
,DISPLAY OFF; ALL INPUTS FLOATING

I

25

iii

20

'5

./

V

'0

1-

-0. 5

10

12

r--

.......

14

16

18

5

20 I

.,...

I'REF'

..

-..0

./
8

-

-

~
.~

~

"
~

o. 5

.6

.4

.2

'0

SUPPLY VOLTAGE - V

SUPPLY VOLTAGE - V

ALARM DRIVER OUTPUT CURRENT
VB. OUTPUT VOLTAGE
SEGMENT DRIVER OUTPUT CURRENT
VB. DRAiN VOLTAGE

P·CHANNEl OUTPUT VOLTAGE - V

18

0

16

12

10

8

6

PJH

9

-

r-

I
-

I

I, I

P·CH VSUPrL Y - 12V

_r-"
/"

5

'T

-

-

"e

...
I

V

i

,1
o 2

ilia:

40
20

4

B

8

10

12

'4 16

18

P·CHANNEL SEGME~T OUTPUT VOLTAGE - V

40
60
60

N·CH

...... r- oy
~ ./

I/'

20

30

'2V
12 14

16

18

N· CHANNEL.OUTPUT VOLTAGE - V

7-50

".

I-- I~2V k--' ~
.3V V

-

10

~

/.~

.5V

60

a

"""- - - - ,-0-- OFF
0

HRS'
ADV!

! TIME SET
~RUN

,-0-MIN
ADV

[

~
lI

ALARM

PF

rl ~

TRANSDUCE R

QfO
CRYSTAL

'820n

NPN

'T

~II

........
.~

PM
INDIC.
6.SV':i ~-

6sn
lW
~

~~

--

~~

RADIO

r----

[AL SET

~

~

r
J I

35

30

'10FF

I
'---RADIO

6~ SNOOZE

)I AL
~ OFF

I-- I--

J

,

'

25

ON

)/'

,

21

ICM7223 VF

5,

10

15

20

L--

I

~ ~ ~~tllt~~ENT

,..'

-

~ ....

~

- r-

rr-

PM

II
G

G

R
I
D

1

~TOV+

I
F
1

A
1

F
2

A
2

B

G

2

R
I
D

,

C
0
L
0
N

F
3

A
3
D
3

B
3

F

A

B

G

4

4

4

R

DISP
CONT

I
D

NEC LD816. V.F. DISPLAY

G
F
I
L

R
I

0

G

E
1

D
1

C
1

G

2

E
2

I I

,n

BRIGHT

b

0
2

C
2

G
3

E
3

C
3

G

E

0

C

••••

R
I

0

F
I
L

I

DISPLAY BRIGHTNESS,
I

DIM

7-54

ICM7223VF
TYPICAL DISPLAY (FIP5E15S)
i

Other displays (by NEe):
FIP 5885
LD 8196
LD 8164

~
AM

PM

,t"
.
.......
f ,I.'. I., I.,.
t~, t~,

DISPLAY FONT
NUMBERS

.,C a_,,

CHIP TOPOGRAPHY

02

E2
G2
F2
B1 +C1
?

PM
AM
ALARM FLAG
OISP~ONT

HRSIMIN AOV
RUN/SET

CHIP DIMENSIONS: 116 x 147 mils (2,95 x 3,73 mm)

7-55

ICM7245
Quartz 'Analog
,WatchCircuit
FEATURES

, GENERAL DESCRIPTION

,. Very low currenf consumption: 0.4~A at
1.55 volt typical
• 32 kHz oscillator requires only quartz crystal
and trimming capacitor
'

"

• Bipolar stepper drive with low output ON resistance: '
200 ohms maximum (7245 AlB/D/E/F)
• Unipolar stepper drive with very low output ON
resist,ance: 50 ohms maximum (7245U)
• Extremely accurate: oscillator stability ,
typically 0.1 ppm'
'
• STOP function for easy time synchronization
• TEST input for highspeed testing
• Wide temperature range: -20°C to +70°C
• On'chlp fixed oscillator capacitor: 20pF ±20%

TABLE OF OPTIONS
Bipolar!
Unipolar

Pulse
Wldlh
,(ms)

Pulse
Frequency

ICM7245A

8

9,7

1Hz

ICM72458

8

7.B

1Hz

CIN

ICM7245D

8

7.B

0.1Hz
(1 pulse!
10 seconds)

COUT

Device
Number

\

l

'

ICM7245E

8

iB

JCM7245F

8

7.B

ICM7245U

U

3.9

.

The ICM7245 is a very low current,' .low voltage'
'microcircuit for use in analog watches. It consists of an
oscillator, dividers: logic and drivers necessary to
provide either bipolar or unipolar drive for minimumcomponent count watches. The oscillator is extremely
stable over wide ranges of voltage and temperature,
and thus combines high accuracy with low system,
power.Th~ ICM7245 is fabricated using Intersil's low
thresh'old metal-gate CMOS process. '
The inverter oscillator contains all components onchip except for the tuning capacitor and quartz crystal.
The binary divider consists of 15 stages, the last 5 of
which may be reset. If a reset ~stop) occurs during an
output pulse, the duration Clf the pulse is not affected.
When the reset is released, the first output occurs
approximately 1 second later. For the bipolar version,
memory reset-logic is. included to make sure the first
pulse after a "stop" occurs on the opposite'output from
the one just before the ~·stop" .
The bipolar bridge output consists of two large
inverters, normally high. The output ON resistance
the P and N channel devices in series is200n maximum
@ 1 mAo I n unipolar operation, the output is madeup of.
a single normally high inverter. The ON resistance of
the N-clj1annel de"ice.is 50n maximum @ 3 mAo

0'

PIN CONFIGURATION

' Oscilialor
Capacitor

(OUTLINE DRAWING BA)

.-------.. ,...------0.-.

, MOTOR 2

I

MOTOR 1

I

,

2

6

'. ' STOP I 4

0.OB33Hz
(1 pulse!
12 seconds)

CIN

0.051;iz
(1 pulse!
20 seconds)

CIN

1Hz

CIN

I OSCIN

'7',

ICM7245
/

3

OSCOUT

.8

1

yOUT

,5

l

TEST

I

ORDERING'INFORMATION

T
ICM7Z45 U

,

1I

BA

:~C=K:~~

FLATPACK
'-_'_ _ _ _ _ _ _ TEMP. RANGE
L ._ _ _ _ _ _ _ _ _ -20'CTO+70'C
L - l- - - - - , - -

ELECTRICAL OPTION

DEVICE TYPE'

OllDER DICE BY FOLLOWING PART NUMBER:
ICM7245AiD
"
LSELECT OPTION

7·56

'ICM7245
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections 'of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

Storage Temperature ...•....... -40°C to +125°C
Operating Temperature .•.•.. ' ..•. -20°C to +70°C
Power Dissipation (Note 1) .••.....•....•.• 25 mW
Supply Voltage (V+ - V-) •••........•.. 3.0 volts
Lead Temperature (Soldering, 10 sec) ..... 300°C
Input Voltages •••.••.•.•.

V- -0.3 < VIN < V+ +0.3

Note 1.: This value of power dissipation refers to that of the package and will not normally be obtained under !"lormal operating conditions.

TYPICAL OPERATING CHARAcTERISTICS
V+ -

V- =

1.55V, fosc = 32,768 Hz, circuit in Figure 1, TA = 25°C, unless otherwise stated.

Numbers are in absolute values.

PARAMETER

SYMBOL
1+

Supply Current

TEST CONDITIONS

MIN.

TYP.

No Load

0.4

Operating Voltage

V+- V-

O°C < TA < 50°C

1.2

Oscillator Transconductance
Oscillator Capacitance

gm

Start-up

15

Cosc

20

16

MAX. UNITS
0.8
1.8

Jl.A
V

24

Jl.mho
pF

STOP Input Current

ISTOP

0.3

Jl.A

TEST Input Current

ITEST

10

Oscillator Stability

fSTAB
1+

Jl.A
ppm

Supply Current During Stop

A(V+-V

0.1

'STOP' Connected to V +

Output Saturation Resistance P-CH .

Ro
Ro-p

Unipolar IL

Output Saturation Resistance N-CH

RO-N

Unipolar IL

Output Saturation Resistance

) =0.6V

+ P-CH)

Bipolar (N-CH.

IL

= 1 mA

= 3 mA
= 3 mA

1.0

Jl.A

200

.n
n
n

200
50

TYPICAL WATCH CIRCUIT

L
/
1

"MO'

9

5·25 pF

CRYSTAL
PARAMETERS

B

=='
D
T

f

2

7
leM
72458

3

+

-:;:-

-

STOP

4

5

Figure 1.

7·57

= 32768 Hz

CL =10 pF
CM = 2.5 mpF
Rs = 20K!1

32768 Hz
CRYSTAL

1.55V

ICM7245
WAVEFORMS
(ICM7245U)

(ICM7245B)
~I~--------~l\
MOTOR 1

U

1-1 SEC--i

Ur--~

MOTOR 2

-----I f--

r

STOP

7 .8mS

-----I

TYPICAL OPERATING CHARACTERISTICS
. SUPPLY CURRENT AS
A FUNCTION OF SUPPLY VOLTAGE
1.6

16

J

TA 250 C
RL.= 60.11
COUT = 20 pF

1.4

BRIDGE'OUTPUT CURRENT
AS A FUNCTION OF LOAD VOL TAGE

-

14

1.2

~
I-

15a:
a:

::J

~

'"

12

15a:

10

a:

r--..

v+



....

,

(".3V

3.0

DOUBLER V+

"

1.SSV

~OUB~ER J. -1. 3V
1

r

C-

I

I

0.5

1.0

1.5

./

V

2.0

2.5

./

.7-62

5
-

"\

~

--

V+=1.3V

I

II

1.0
N-CH OUTPUT VOL rAGE (VOLTS)

aUTPUTCURRENT IH (~A)

0

i
V·~'.55V

C-

./
2.5

./

.,

k:: V

V·".5~ . /

-

"~
0

I

TA =2S'C

I

4.0

~

~

1.7

1.B

1.5

SUPPLY VOLTAGE

-

'1 o

2.0

U~U!b

ICM7271
DUPLEXED 4 DIGiT LCD DISPLAY
20

19

18

17

21

ld

B~

~

@)

@

.,

lb

*
16

15

2b

31

14

13

12

11

3b

41

61

~ ~ (;] ~ [cl

2.

e e

@)

u
Ou
@@

@ @

, ., :,..., a,, a a
Ie

1

DISPLAY FONT
NUMBERS

2

2.

2,

3

4

6

5

~
3.

b1 b1 b1
4.

3,

f

C
fLu-

DUPLEXED LCD DISPLAY WAVEFORMS
V'IO.OVI_
V-(-1.5V)_

I

1~3.0VI_

, t.

8

9

LOWER SEGMENTS CONTROLLED BY BP"

10

a--,

wr ,

t",

SEGMENT A AND B WAVEFORMS

1

'(l-u 11to'

BACKPLANE

VrmsON

NOTE: UPPER SEGMENTS CONTROLLED BY BP2.

4.

a,
~ Of a :, '...f

7

wr

VH

e

@

Q~O [ffJ

0
r=J
0

D
kJ El

Cd ~

El [d

*Typical displavs include '
LADCOR
LAD·122
Fairchild
FLM·4005·01
BBC
LC1612XX
LC2013XX

to

NO,l

BACKPLANE
NO.2.

SEG. 'A' ON
SEG, 'S' OFF

._.1...,/

(V+\2_J5v+.vrmsOFF

ILf S IL

to

to

SEG. 'A' OFF
SEG. 'S' ON

to

SEG. 'A' ON
SEG. 'S' ON

'""~VO+(Y':.)2

I_O_N~SE~G-:V~O-LT-SI---f2-2---V,IV~'1-2+----2-1--~_2

_____________

"

v'

2~_=_2f2

__._I_O_FF_S_EG_._VO_L_TS_I__
j2_2_____

'ONOFF

SEG. 'A' OFF
SEG. 'S' OFF

/51231

NORMAL WATCH OPERATION
TIME
HOURS-MINUTES-DAY
TU
0

·RUN

0

•

0

0

0

DEMAND
MONTH-DATE-DAY
TU

0

.PRESS
DISP
ONCE

• :•. -: c.
.t,. '_ILI

0

•
It-.
.U-:w" :.
0

0

1.5 SEC
DELAY

COLON 3t

FLASHING

0

0

0

••

J

PRESS
DISP
ONCE

SECONDS-D~Y

TU
0

PRESS
DISP
ONCE

•

0

,

0

0

0

0

. -, -, . C C.

COLON
FLASHING

In the TIME mode, the circuit displays hours, minutes
and day, and the colon is flashing. Demand operation
is actuated by depressing the DISPLAY switch once
for month, date, and day. Seconds are displayed by

depressing the DISPLAY switch twice, and they will
remain displayed until the DISPLAY switch is depressed a third time.
7-63

_

!~

__
2_.___
' ___
=__'__
o_.__
' _______________

·ICM7271 .·•.
.

-

'

"

-

,

ALARM OPERATION
ALARM TIME.
ENTIRE
HOURS MINUTES DISPLAY FLASHING

TIME
HOURS'MINUTes

o

0

.- .. 0

0

0

o

0

0

'.

0

0

0

00.

PRESS

'0

ALARM TIME
ENABLED)

(AL~RM

0

DISPLAY

ONCE
(ENABLES
ALARM)

PRESS
DISPLAY

ONce

seT ALARM
MINUTE TENS

. seT ALARM MINUTE~

'OR

,.

\

o

PRESS

0

....

0

0

0

,. J (

SET
ONCE

PRESS

0,

,.•

DISPLAY

'i-' ..,

PRESS
SET
ONCE

-,. 'C

ONCE
FOR EACH

10MIN.INCREMENP

:.

o

0 . • ," 0

•••

L--A-L-A-RM-'''L':'AG-A-N-D-~' .:~~~g~~~) L--A-L-AR-M"";..LA'-G-A-N-D....,.......
'MIN. TENS FLASHING

HOURS'
INCREMENT-

ALARM FLAG, HAS,
AND P FLASHING

MIN. TENS FLASHING

TIME, ALARM ENABLED

,;..

• L.' •

•

(

('

*In all set modes, pressing the DISPLAY once will advance the
flashing digit by one. II held down, the digits will increment at a 1 Hz

~. ~

~&

'

.

SNOOZE OPERATION

Th~ mode switctiallows easy access to all alarm
functions. Each push of MODE: causes the circuit to
switch from Wne to.alarm or vice versa. When the watch
time eqUals .the alarm (including AM/PM for 12hr
modeHhe alarm will sound. The alarm will silence itself
after one minute,or can be silenced by pressing the
DISPLAY button. In either cas,e, the alarm will remain
armed to sound again 24 hours later. If neit~er SET nor
DISPLAY is used for 24 seconds after 'entering the
. alarm mode the circuit will return to time.

While sounding, the alarm may be silenced' for
approximately five minutes by pressing the MODE
button. This 'SNOOZE' may be repeated as often as
desired. If the. MODE button is pressed during the
'SNOOZE' time the. alarm will be silenced, for
approximately five minutes from the second depres"
sion. The display will not be affectedbyactivation of
the 'SNOOZE' operation;, depressing the DISPLAY
button will terminate the snooze cycle.

SET OPERATION

.
,-, . (a:,
'0

0

0

0

0

,C/':I 0

(

~~~~~ING/
1.5SEC.

0

0

PRESS
SET

.

"

~

0

0

0

'.~. ~

,•
0

0

0

0

0

,,
0

PRESS

DISPLAY

0

0

.

0

0

DATE

DAY

0

0

, L.f -, -,

, AND SECONDS RESET
TO ZERO

0

..

,,
0

SET DAY·

PRESS

SET
ONCE
IF MINUTES
HAVE BEEN"

TIME HOLD MODE
IF MIN. HAVE BEEN

0

HRM1N .

0

0

0

FLAS~N~IN

0

';/0

0

0

0

0

'LI-:' • \
DATE

MONTH

PRESS'

,.C-,.. . ,-a-,
i (,
0

,.-, -, ,

DAY FLASHING

PRESS
SET
ONCE

SET

SET MINUTES·

.:,.( ('

COLON NOT FLASHING

0

f LI- ~

TIME HOLD

~

0

MONJ~TE F~SHI~~TE

Al TEREO

0

,fC·-,. . r\.-, )
seT HOURS·

PRESS

SET, ,
ONCE

"

0

HR

0

ONCE,

000

AOR P

HR AND A OR P FLASHING

SET

*In all set· modes, pressing the DISPLAy' once will advance the
flashing cligit by 0l'le. II held down, the digits wUl increment at a 1 Hz
rate. '

Setting the ICM7271 is carried ..out in a sequential
manner .. The SET input allows the user to cycle
through the five set modes. All set operations are
independent, i.e. the counters following th~ one being
set are inhibited; this allows, for instance: convenient
.time zone adjustment wi.thoutaffecting day, date or
month.' The setting sequence is graphically shown
abOve, The. counters being set are flashed at a 1 Hz rate
for. easy useFidenti.fication
.
..
'

0

PRESS
SET
ONCE

IF MINUTES HAVE NOT BEEN ALTERED

10-3
MONTH

,....., -,
seT DATe-

0

MONJ~NTH'FLASHI~~TE

'.

DEMAND

\

.
,.-, - =-

SET MONTW

TIME

O.

HOURS SET
In the 12 hour mode an A or P will appear in the right
most digit to indicate AM/PM. These characters: are
blanked in the 24 hour mode.
MINUTES SET.
The MINUTES .SETmode is used for exact synchroni"
zation of the. watch as well as for setting the minutes. If'
the'DISPLAY switch is not activated during MINUTES
SET, neither seconds norminuteswi.11 be affected and
the next aqivation of the SET switch will retur(l the
circuit to norm\lltime. If DISPLAY is, used in the

'

DATE SET
The perpetual calendar uses 28days for February. Ina
leap year,on February 29, the watch will display March
t. To display February 29, change date to 29 fi rst, then
M,arch'to February_'
".
.
7-64

ICM7271
The following expressions can be used to arrive at a
crystal specification:

MINUTES SET mode the minutes will advance and the
seconds will reset to 00 and be put on hold. The user
now advances to the next minute and pushes SET
once. The circuit is now in TIME HOLD. The DISPLAY
will show hours, minutes, day, and the colon will be on
(not flashing). At the tone of the time signal; push
DISPLAY, This will cause the watch to display
month/date/day for 1.5 seconds and return to normal
(running) (time) display. Time setting accuracy is
approximately 0.1 seconds ..

Tuning range
Dof

T

Cm
= 21 Co

.C

+ CLI'

L

=

CIN COUT
CIN + COUT

gm required for startup
.

gm = 4rr 2f 2 'CIN COUT Rs (1

,2

+~~)

where
Rs
= Series Resistance of Crystal
f
= Frequency of the Crystal,
~f
= Frequency Shift from Series Resonarice
Frequency
,
Co
;= Static Capacitance of Crystal
CIN = Input Capacitance
COUT = Output Capacitance
CL
= Load Capacitance
C m = Motional Capacitance of Crystal

SET MODE TIME-OUT
If,neither SET nor DISPLAY is used for 24 seconds the
circuit will return to normal time.
'

APPLICATION NOTES
ALARM DRIVE
The ICM7271/M provides sufficient drive current for
n.ormal use with 'a 4 KHz piezoelectric transducer, provided the transducer is properly mounted. For increased drive, a 5, mH coil and an external NPN,
transistor are required. Refer to the Application Note
A03~, "ICM7220A Cbil Driven Alarm Design," for
details.

The gm required for startup calculated should not
exceed 50% of the gm guaranteed for the device.

OSCILLATOR
The oscillator of the ICM7271/M is designed 'for low
frequency operatiori from a 1.55 volt supply at.very low
currents. The oscillator is of the inverter type with a
non-linear feedback resistor which has a maximum
resistance under startup conditions included on chip.
The nominal load capacitance of the crystal should be '
less than 15 pF, typically 12 pF. In specifying the
crystal, th,e motional capacitance, series resistance
and tuning tolerance must be compatible with the
characteristics of the circuit to insure startup and
operation over a wide voltage range under worst case
conditions.

TEST POINT AND DISPLAY TEST
The circuit is resetto a known state by connecting SET,
DISPLAY,and TEST to V+. This state is Saturday
December 1,12:00 am (or 00:00), with alarm at 12:00
am (or 00:00) and disabled. When powering up the
device, it will also reset to this state. The TEST input,
when connected to V+ causes the circuit to speed up
the seconds by 512 times. The date-month carry is not
inhibited during
connecting SET and DISPLAY to V+ the circuit will
provide a DISPLAY TEST function, turning on all
segments and indicators on the display as well as
sounding the alarm.
'

PIN CONFIGURATION

SET SWITCH
C4/G4

D3!E3

"':'AL
(-)/eOl

7-65

ICM7272
4-Digit Duplexed LCD
Chronograph
Watch Circuit
GENERAL DESCRIPTION

FEATURES
• 4-dlgit duplexed display with time, day of week, dateand chrono flags

• F~II 30 minute 'chronograph: minutes, seconds, tenths.
Tenths of seconds are displayed in dynamic bargraph
• MODE button allows switching between watch and
chronograph without affecting chrono function
• 12/24 hour, month/date reversal bond option
• Display test: All segments and flags ON when DISP
and SET are pushed at the 'same time
• Power ON reset

• For NORMAL operation: (All operations begin with
RUN display - hours: minutes, day)
Press:
DISPLAY

once

To:
Display month- date day

• For SET operation:
Press:
SET

once
again
again
again
again
again

To:
Set month'
Set date'
Sefday'
Set hours'
Set minutes'
RUN or HOLD

, The ICM7272 is a fully integrated 4-digit 6-function LCD
watch circuit with a 30 minute, tenth second chrono. graph, and designed to interface with readily available
4-digit duplexed displays. The oscillator, frequency
dividers, voltage'multiplier, and segment drivers are all
incorporated on chip. The only additional c~miJonents
required for a complete watch are a 32 kHz crystal, on'e
trimming .capacitor, two multiplier capacitors, a
duplexed LCD display, three SPST switches and a f,5V
battery.
.
Chronograph operation has been optimized for short as
well as long interval timing. Tenths of seconds are displayed in a dynamic bargraph across the top of the
display, while seconds and minutes are displayed in the
A-seven segment .digits. 30 minutes is automatically
converted to 00:00.0.
The MODE button allows alternating between watch
and fchrono at any time; in the CHRONO mode, the
DISPLAY switch acts as the START/STOP/RESET. In
TIME SET mode, if no buttons are pushed for 24
seconds the circuit returns to RUN. 60 ms of switch
debounce is provided on all switch inputs.
The ICM7272 is fabricated using Intersil's I~w threshold meta,1 gate CMOS process, and is designed for
mounting on the same side of the substrate as the.
display.
.

'Selected counter advances once with each push onhe DISPLAY

_:ut~:ro~~::~:~;~:i~i~::::t~;~n.

l1li

Press:
MODE
DISPLAY
DISPLAY

once
once
again
again
hold
for

.

To:
Display minutes: seconds,fenths
Start
Stop
Start (time out function)
Reset

PIN CONFIGURATION

1,5

MODE

sec.
once

RUN

ORDERING INFORMATION

Order dice by following part number: ICM7272D .

Note: For evaluation only the ICM7272 is available. in a 40 pin
ceramic DIP with 0.1" pin-to-pin and 0.6" row-to-row spacing.
Order part number: ICM72721DL

7·66

-ICM7272
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the devIce
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating con\litions for
'extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS
Storage Temperature ........... -55°C to +125°C
Operating Temperature .......... -=20° C to +85°C
Power Dissipation l11 (Dice Only) .......... 100 mW
Supply Voltage l2 !
v+ - V- ................................. 2.0V
V+ - V2 .................................. 5.5V
Input Voltage (Osc. In, Test,
Set, Display) .... '................. V- :s VIN:::; V+
Output Voltage (Osc Out) ......
V- :SVOUT :s V+ .
(All Other Pins) ................ V2 :s VOUT :s V+

"Notes:
1.
The ICM7272 is fully short circuit protected on all inputs and outputs. However, if by biasing an input or output the device is put into
a latchup condition, power dissipation must be limited to 100 mW to prevent destruction of the device.
2.
The ICM7272. is intended fo'r use with two power supplies, one of which is derived from an external battery (V-I and the other is
generated internally by the voltage multiolier(V 2 I. The common point of the two supplies is the most positive, V+. If desired the
circuit can be supplied with an external V2 by disconnecting the multiplier capacitors.
.

OPERATING CHARACTERISTICS
TEST CONDITIONS: V+ - V- = 1.55V, Voltage Doubler Connected,
Voltages Specified in Absolute Value.
PARAMETER

TA

= 25° C,unless otherwise stated.

.

SYMBOL

CONDITIONS

= OV

MIN.

TYP.

Supply Voltage

V+

V.

Supply Current

1+

Display Disconnected

V~

IH

Segment Drive Current

ISEG

VSAT = 0.2V I Both Directions'

Backplane Drive Current

IBP

VSAT

Switch Actuation Current

Isw

Vsw

Alarm Saturation Resistance

RAL(ON)

N-ch and P-ch (Seriesl at 1 mA

Oscillator Stability

fSTAB .

V = OV, 1.3V::; Vi"::; 1.55V,
COUT = 25 pF

Oscillator Input Current[3)

losci

'OSC IN' Connected·to V+
'OSC OUT .Open Circuit

Oscillator t'nput Capacitance

CIN

20

25

Oscillator Transcol1ductance

gm

10

15

. Doubler Output Voltage

IH

-10°C < TA < 60°C

1.5

= 0.0 p.A
= 1.0 p.A
= 0.1 V
= Vi"

I

1.2
3.0

3.1

2.9

3.0

Both Directions'

MAX.

U~ITS

1.8

Volts.
).

5o

2, 5

2, 0

0,5

0

'.5 "

,13L

2,0

0

2.5

.5

'.0

'.5

, OUTPUT CURRENT (mAl

. OUTPUT CURRENT tH (j.lA!

7·68

2.0

2.5

ICM7272
DUPLEXED CHRONO WATCH DISPLAY

0000000000

uOu

@@

Q~O

0
0

c::J

~

,,

2e

DISPLAY FONT
NUMBERS

1-1

2g

. c::J

mru DDODO

IT] [1] ITJOD [ill §
10

Ou

Ou Ou

c=J

J.

COL.

J,

4e

4d·

10

,

NOTE, UPPER SEGMENTS CONTROLLED BY BP,.
LOWER SEGMENTS CONTROLLED BY BPt.

.

11

a_,

DUPLEXED LCD DISPLAY WAVEFORMS

SEGMENT A AND'S WAVEFORMS
!

v+

(O.OV)-

·V-I-1.5VI_
VH 1-3.0VI_

~

-

I Wto
BACKPLANE
NO,1

VrmsON

_

fLuJLIU SfL

to

to.

BACKPLANE
NO.2

(V+)2_~
2.[2'

-.1.,/

IONSEG, VOLTS I - 12 yIV'I'+T

to

SEG. 'A' ON
SEG. 'B' OFF

to

SEG. 'A'OFF
SEG, 'B' ON

VrmsOFF

IOFF SEG, VOLTSI

=

to

SEG. 'A' ON
SEG. 'B' ON

~JO+(,£)2
V+.
f2
2
= 212'

ON

,

SEG. 'A' OFF
SEG. 'B' OFF

OFF

~ 1 231
=,,>".'

NORMAL WATCH OPERATION (12 Hr option)
TIME
HOURS-MINUTES-DAY
TU

DEMAND
MONTH-DATE-DAY
TU

RUN

.;.·ce.

PRESS DISP ONCE

'Lj:tO
~~!~~ING t

,•

0000.00000

0000.00000

,
1.5 SEC DELAY

The circuit displays hours, minutes and day with the
colon flashing, Pressing DISPLAY switches the display

"'-'\3
,•LI

. I ;~:S~~~G

to the month, date, and day mode with the date flag on.
1,5 seconds later, the circuit returns to TIME.
'

NORMAL OPERATION (24 Hr option)
TIME
HOURS-MIN UTES-DAY
TU

ooooeooooo
RUN

:,.-•. C C.
CL~:tO
;~~~!NG

t

DEMAND
MONTH-DAtE-DAY
TU

,

,•

0000.00000

PRESS DISP ONCE

1.5 SEC DELAY

7-69

"'-3
',LI",

I~~:S~?~G

ICM7272
SET OPERATION
SET MONTH"

TIME
000.000000

, :,. c C'
IL:_'LI

(

,

~

.-.~,

'~-

:,

,

It' -, ,

ooo.oooooe

PRESS
SET
ONCE

I LI- ~ I

I

1.5SEC.

,

\ IIt-'LI.- :,-,

000.000000

MONTH

f

PRESS
DISPLAY

~

"'75

a

,0

0' 0

~,

0

1\

DATE

PRESS
SET
ONCE

,-,.
,-, V
},. '\

o

PRESS
SET
ONCE

". ~o

IF MINUTES
HAVE BEEN
ALTERED

HR~lIN. FLAS~INGMIN

TIME HOLD MODE
IF MIN. HAVE BEEN
SET

•.

SET HOURS·

000.000000

PRESS
SET
ONCE

It-'
0

ILI-:' I

SET MINUTES·

\

000.000000

COLON NOT FLASHING
AND SECONDS RESET
TO ZERO

DAY

DATE

, -, ..- n
"1 :, :,
TIME HOLD

0

, MONTH

,-, ..- ,-,

IF MINUTES HAVE NOT BEEN AL TERED

DEMAND

,

DAY FLASHING

o

PRESS
SET
ONCE

~ONJ~TE F~SHIZ~TE

MONTH
DATE
MONTH FLASHING

~~~~~INi

SET DAY·

SET DATE"

000.000000

PRESS
SET

0

0

.'0

0

0

0

0

0

HR
ADR P
HR AND A OR P FLASHING

"In all set modes, pressing the DISPLAY once will advance the flashing
digit by one. If held down, the digits will Increment at a 1 Hz rate.

MINUTES SET
The MINUTES SET mode is used for exact synchronization 'ofthe watch as well as for settingthe minutes. If the
DISPLAY switch is 'not activated during MINUTES SET.
neither seconds nor minutes will be affected and the'
next activation of the SET switch will return the circuit to
normal time. If DISPLAY is used in the MINUTES SET
mode the minutes will advance and the seconds will reset
to 00 and be put on hold. Theuser now advanc~s to the
next minute and pushes SET once. The circuit is now in
TIME HOLD. The DISPLAY will show hours, minutes,
day, and t~e col6nwill be on (not flashing). At the-time
signal tone, push DISPLAY. This will cause the watch to
display month/date/day for 1.5 seconds and return to
normal (time) display. Seconds begin counting the
moment the switch is pushed, and time setting accuracy
is approximately 0.1 seconds.

Setting the ICM7272 is carried out in a sequential
manner. The SET input allows the user to cycle through
the five set modes. All set operations are independent,
i.e. the counters following the one being set are inhibited; this allows, for instance, convenient time zone
adjustment without affecting day, date or month. The
setting sequence is graphically shown above. The counters being set are flashed at a 1 Hz rate for easy user
identification.
,
DATE SET
The perpetual calendar uses 28 days for February. In a
leap year, on February 29, the watch will display March
1. To display February 29, change,date to 29 first, then
March to February.
HOURS SET

_

In the 12 hour mode an A or P will appear in the right
most digit to indicate AM/PM. These characters are
blanked in the 24 hourmode,with minutes continuously
displayed.

SET MODE TIME-OUT
If neither SET nor DISPLAY is used for 24 seconds the
circuit will return to normal time.

_ _ CHRONOGRAPH OPERATION

CHRONOGRAPH OPERATING

RUN

CHRONOGRAPH

-, -.- .-,
.,C-:.,.

00.0000000

su

HR

PRESS
MODE
ONCE

TENTHS

.-, .-,

t-.ooooooooo

LI ~( Lo' LI

MIN

MIN

COLON OFF /

/~

.-, .-. .-..-.
LILI LILI
_

PRESS
DISP
ONCE

(J)

flASHING

....
-,c .-:,:. -.......
.-:. .-,:.
'~

SEC

"FLASHING

.-. .-,
LILI

.,LI ,

~

•

,....A

SEC

PRESS
DISPLAY
AND HOLD
FOR 1.5 SEC.

0

~

0.1 SEC.
LATER

oo.oot oooo

"='-'-C'
."--.J_•
SU

HR

PRESS
DISP
ONCE

0'0 0

.,.-, .-, U
LI L' LI'

• • • 0000000

.000000000...

MIN

~

SEC

PRESS
MODE
ONCE

FLAG
FLASHING

FLAG FLASHING

FLASHING

MIN

(J) _

~

.-, .-, -.-, .-,
LlLI-LILI

"",(J)

CHRONO FLAG ON

DISP AFTER ROLLOVER
TENTHS'

I

COLON
/FLASHING

CHRONOGRAPH OPERATING

.-, .-, LILt
LILI .'0

• • • • • .0

PRESS
MODE

FLASHING

DISPLAY STOPPED
5/10 SEC.

' DISPLAY RUNNING

MIN

PRESS
DISP

CHRONOFLAG FLASHING

DISPLAY RESET
.000000000

\

., r,

RUN

FLAG SEQUENCE @ 10Hz

.000000000

RUN

TENTHS

PRESS
MODE
ONCE

-, -.-,.-,

00.0000000

SU

.

C -LILI

HR

K(J)

MIN

ON

The MODE switch allows easy access to' all chrono
functions. Each push of MODE' causes the circuit to
switch from time to chrono or vice versa. When the
chrono time equals 29 min 59.9 sec the circuit will roll

over to 00:00. Chrono tim,e can accumulate up to 29 min
59 sec and 9/10 seconds.

7·70

ICM7272
APPLICATION NOTES

gm required for startup

ALARM DRIVE
The ICM7272 provides sufficient drive current for
normal use with a 4 KHz piezoelectric transducer, provided the transducer is. properly mounted. For increased drive, .a 5 mH coil and an external NPN
transistor are required. Refer to the Application Note
A031, "ICM7220A Coil Driven Alarm Design," ,for
details.
.

gm = 4rr2f2 CIN COUT Rs (1
where
Rs
f
Af

= Series Resistance of Crystal
= Frequency of the Crystal
= Frequency Shift from Series Resonance
Frequency
Co
= Static Capacitance of Crystal
CIN
= Input Capacitance
COUT = Output Capacitance
CL
= Load Capacitance
Cm
= Motional Capacitance of Crystal

OSCILLATOR
The oscillator of the ICM7272 is designed for low (requency operation from a 1.55 volt supply at very low
currents. The oscillator is of the inverter type with a
nonclinear feedback resistor which has a maximum
resistance under startup conditions included on chip.
The nominal load capacitance of the crystal should be
less than 15 pF, typically 12 pF. In specifying the
crystal, the motional capacitance, series resistance
and tuning tolerance must be compatible with the
characteristics of the circuit to insure startup and
operation over a wide voltage range under worst case
conditions.

The gm required for startup calculated should not
exceed 50 0(0 of the gm guaranteed for the device.
TEST POINT AND DISPLAY TEST
The circuit is reset to a known state by connecting SET,
DISPLAY, and TEST to V+. This state is Saturday
December 1, 12:00 am (or 00:00 I. with alarm at 12:00
ani (or 00:00) and disabled. When powering up the
device, it will also reset t9 this state. The TEST input,
when connected to V+ causes the circuit to speed up
the seconds by512 times.The.date-month carry is not
inhibited during date set in the test mode. By
connecting SET and DISPLAY to V+ the circuit will
provide a DISPLAY TEST function, turning on all
segments and indicators on the display as well as
sounding the alarm.'

. The following expressions can be used to arrive at a
crystal specification:
Tuning range
Af

T

+~~r

Cm · .
CIN COUT
2lCO + CLI ; CL = CIN + COUT

CHIP TOPOGRAPHY

7-71

D~DIL

NOTES:

7-72

Digital
Memory
NMOS Static RAMs Page
2114
8-5
M2114L
8-9
2147
8-13
M2147
8-16
2148
8-20
M2148
8-24
7141
8-219
7141M
8-223
CMOS Static RAMs
IM6504
8-152
IM65X08
~157
IM6512
8-163
'IM6514
8-169
IM65X18
8-157
IM65X51
8-174
IM65X61
8-174
NMOS Dynamic RAM
IM7027/4027
8-212
NMOS ROMs
8-227
IM7332
IM7364
8-230
82HM137
8-237
82HM141
8-240
82HM181
8-243
82HM185
8-247
82HM191
8-251
CMOS ROMs
IM6312
8-132
IM6316
8-139
CMOS EPROMs
8-180,
IM6653
IM6654
8-180
6920 EPROM
8-200
Programmer

Bipolar PROMs
IM5200FPLA
IM5600/10
IM5603/23
IM5604/24
Bipolar PROM
Programming
Specifications

8-28
8-39
8-42
8-48
8-53

Microprocessor
IM6100
6801 Sampler Kit

8-55
8-187

Peripherals
Itvl6101
IM6102
IM6103
IM6402/3
82C43

8-77
8-97
8-120
8-144
8-233

I

Development
Systems
Intercept Jr.
8-205
Intercept II
8-192
Intercept CPU with Dual
Serial 1/0
8-196
Double Density
Flexible Disc
Controller
8-197
Concept-48
8-201
4K x 12 CMOS
Memory Module
8-191
32Kx 12 RAM
Board
8-198
6970 Disc Operating
. System
8-211

NMOS
Static RAMs
Organlzallon
1024,x 4
2114/2114l.
2114/3/2114L-3
2114/2/2114L-2
2148
2148-3
M2148

Max Acceai Time (nBI

Icc Max(mAI

No. PlnB

Package'

Temp Wange'

~5

100170
100170
100170
140
140
180

18
18
18
18
18
18

J,P
J,P
J,P
J,P
J
J

C,M
C,M
C,M
C.
M
M

450
300
200
70
55
85

70/SO
70/50
. 70/50
160/140
180
180

18
. 18
18
18
18
18

J,P
J,P
J,P
J,P
J,P
J

C,M
C,M
C,M
C
C
M

No. Pins

Package'

Temp Range'

16
16
16
16

,J
J
J
J

No. Pins

Package'

450
. 300
200
70

55

4096 x 1
714117141L
7141-3/7141L-3
7141·2/7141L-2
2147/2147L
2147·3
M2147

Dynamic RAMs

.-:

Organlzallon ,

Max- Access Time (nsl

4096 x 1
7027-1
4027-2
4027-3
4027-4

120
ISO
200
2SO

Max(mAI

100

35
35
35
35

C
C
C
C

ROMs
Organization
1024 x 4 .
82HM137
82HM137

Bl

Max Access Time (nsl

100

Max(mAI

Temp Range'

60
80

120
130

18
18

2048 x 4
82HM185
82HM185

60
60

120
130

18
'18

J,P
J

C
,M

512 x 8
82HMli11
, 82HM141

70
90

175 '
185

24
24

J,P
J

C

1024 x 8
82HM181
82HM181

70
90

175
185

24
24

J,P
J

C
M

2048 x 8
82HM191
82HM191

80
100

175
185

24
24

J,P
J

C
M

4096 x 8
IM7332

300

80

24

J,P

C

8192 x'8
IM7364

350

ISO

24

J,P

C

, . 'package and Temperature Key
F-Flatpack
J-Ceramic Dualln·Line
P-Plastic Dual 'In-Line
D-Ceramic Side Braized (Not

C-Commercial, O'C to +70'C
I-Industrial, -40'C to +85'C
M...:.Military, -55'C·to +125'C
Recommended for High Volume)

8-2

J,P •
J

C
:M

M

CMOS
Static RAMS
Organization
64 x 12
IM6512
IM6512A
1024 x 1 .
IM65X08
IM65X08A
IM65X18
IM65X18A
4096x1'
IM6504
256 x 4
IM65X51
IM65X51A
IM65X61
IM65X61A
1024 x 4
IM6514

Max Access
Time (nsl

Vee·

460
150

5
10

250
200
250
200

5
10
5
10 .

IV)

300

·5

300
235
300
235

5
10
5
10

Icc Max (mAl
Operating·

2
10
2
10

2
10
2
10

300

Icc Max (~AI
Standby

No. Pins

100
500

18
18

10
500
10
500

16
16
18
18

J,F,P
J,F,P
J,F,P
J,F,P

C,I,M
I,M
C,I,M
I,M

50

18

J,P

C,I,M

10
500
10
500

18
22
18
22

J,P
J,P
J,P
J,P

C,I,M
I,M
C,I,M
I,M

50

18

J,P

C,I,M

Package" .

Temp Range

J,F
. J,F

C,I;M
I,M

ROMS
Max Access
Time (nsl

Vee
IV)

Icc Max (mAl
Operating

Icc Max (~AI
Standby

No. Pins

1024 x 12
IM6312-1
IM6312A

510
250

5
10.

1.8
2

100
500

18
18

J,F
J,F

I,M
I,M

2048 x 8
IM6316

550

20

200

18

J

10M

Organization

Package"

Temp Range

EPRO.Ms
Max Access
Time (nsl

Vee
IV)

Icc Max (mAl
Operating

Icc Max (PAl
Standby

No. Pins

1024 x 4
IM6653
IM6653A

550
300

5
10

6
12

140
140

24
24

I,M
I,M

512 x 8
IM6654
IM6654A

550
300

5
10

6
12

140
140

24
24

I,M
I,M

Organization

Package"

Temp Range

Bipolar PROMS
Organization
(

FPLA
IM5200
32 x 8
IM5600
IM5610
256 x 4
. IM5603A
IM5623
512 x 4
IM5604
IM5624

Max Access Time
(nsl

Icc Max (mAl

100

No. Pins

Output
Type

24

DC

Package"

Temp
C

65
65

100
100

16
16

OC
TS

J,F,P
J,F,P

C,M
C,M

70
70

130
130

16
16

·OC
TS

J,F,P
J,F,P

C,M
C,M

80
80

140
'140

16
16

OC
TS

. J,F,P
J,F,P.

C,M
C,M

"See package and temperature key, p 8-2

8-3

[8

..

'..

MICROPROCESSOR·
IM61.DD Microprocessor Family
IM6l0D
IM61Dl
IM6102
·IM6103

.-

CMOS Microprocessor
CMOS Programmable Interface Ele.menl (PIE)·
CMOS Memory Extension/OMAllnterval Timer/Controller (MEDIC)
CMOS 20 bit Parallel Input-Output Port (PIO)

UAHTS
IM640211M6403
Development Supporl
6801
- IM6100 CMOS Family Sampler
6950
- Intercept Junior Tutorial System
6910
- Intercept II Microcomputer Prototype Development Sy.stem
6940
- Intercept III Microcomputer Prototyping Development ·System
6.975,
- Intercept D~al Floppy Disk driile
IM8048 Peripheral
Development S~pport
6942·

- Concept 48-Single Board Development Tool

SYSTEMS
LSI-8
. 6920

- LSI Based PDP8® Computer System - see 6912, 6914, 6915 .
- CMOS EPROM Programmer

'D~Dlb

2114
4096 Bit (1 024x 4)
NMOS Static RAM

FEATURES
• Cycle Time Equal to Access Time• Completely Static· No Clock Required
• Common Data Input and Output
• TTL Compatible Inputs and Outputs
• 883A Class B Processing Available
• Single + 5 Volt Power Supply
• Pin Compatible with industry standard 2114
- • Maximum Access Time:
.
·200 ns (- 2)
·300 ns (- 3)

, DESCRIPTION
The 2114 is a 4096·bit static Random Access Memory
organized 1024 words x 4 bits. The storage cells and decode
and control circuitry are completely static, therefore no
clocks or refresh operations are required. Memory access
occurs within the specified access time after all address in·
puts are stable. A Chip Select input is provided for simple
memory array expansion.
The 2114 is pin and performance compatible with the
industry standard 2114 series,and the device is assembled
in a standard 18·pin DIP for maximum system packing den·
sity.

• Maximum Power Dissipation:
- 370 mW (2114L)
- 525 mW (2114)

BLOCK DIAGRAM
A3
A4
As

PIN CONFIGURATION,

LOGIC SYMBOL
vi S vee

-vee

•

As
A7

As

_GND
MEMORY ARRAY
64 ROWS
64 COLUMNS

•

- As

1/0,

Vee

As

A7

A4

As

A3

A9

Ao

1/0,

A,

1/02

A2

1/0 3

i/0 2

5

1/0 3

. GND

1/0 4

1/04

Vi

Ao
A,
A2
A3
A.
As
As
A1
As
A9

2114
1/03

-->----------1ra-

(outline dwgs IN,PN)

GND

t----

PIN NAMES,
Ao-A9

5
w

w

ADDRESS INPUTS
DATA INPUT/OUTPUT
WRITE ENABLE
CHIP SELECT

ORDERING INFORMATION

POWER
370mW
525mW

200ns
D2114L2,

ACCESS TIME
. 300n5
D2114L3

450n5
D2114L

PACKAGE
CERDIP

P2114L2

P2114L3

P2114L

PLASTIC

D2114-2

D2114·3

D2114

CERDIP.

1"2114·2

P2114·3

P2114

PLASTIC

8-5

O~OI!"

2114
ABSOLUTE MAXIMUM RATINGS
Operating Temperature ..................... ; ....\ ... '....•...... O·C to + 70·C
Storage Temperature ................................... '........ -uS·C to +1S0·C
Voltage on Any Pin .to Ground ............... ; ..................... -O.SV to +7V
,Power Dissipation
...............: .. : ..............
: ...•....................
'1W
,
.
'
NOTE: Stresses above those listed under 'Abs6rute Maximuln Ratings may cause permanent.
damage to thedevice, These are stress ratings only. and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the
specifications is not implied, Exposure to absolute maximum rating conditions for
extended periods may affect device reliability, '

DC CHARACTERISTICS'
TEST CONDITIONS: Vcc= +SV±5%, TA=O·C,to + 70·C
2114L
PARAMETER

SYMBOL

Input Load Current
Output Leakage Current

'INlD
IOlK

TEST CONDITIONS

MIN

VIN = OV to 5.25V
S = 2.4V,
= O.4VtoV cc
'YIN = 5.25V
1110 =OmA, TA = + 25·C,
VIN - +5.25V

MAX

2114
MAX

UNITS

10
10

MIN

10
10

p.A'

65

90

70

100

VI/O

Power Supply Current,

ICC2 '

Power Supply Current

19C1

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

Vil
VIH

rnA

11/0 = Om A, TA = O'C

..

Vol.
VOH

-0.5
2.0

"
IOl - 3.2mA
IOH = -1mA

,

2.4

0.8
Vcc
0.4
Vcc

-0.5
2.0
2.4

0.8
Vcc
0.4

V

Vcc

, CAPACITANCE
PARAMETER
Input/Output Capacitance. '
·Input Capacitance

SYMBOL

TEST CONDITIONS
VI/a = bv
VIN - ov

CliO

CIN

MAX
S
S

UNITS
pF

DEVICE OPERATION
When Wis high, the data input buffers are inhibited to pre·
vent erroneous c;lata from getting into the array. ,As long as
Wremains high, the data stored cannot be changed ,by the .
addresses Chip Select, or data 1/0 voltage levels andlhli· '
Ing transitions. The block diagram also shows data'
storage cannot be changed by W, the addresses, or the In· .
• put data as long as S Is high. Either S or W by itself, or in
conjunction with the other, can prevent the extraneous
wrltl~g du~ to signal transitions;

8·6

A read occurs, during t,he overlap of

5 low and W high.

Data within the array can only be changed during a Write
time, defined as the overlap of § low and W.low. To prevent
the loss of data, the addresses, must to prop.erly establish·
ed during the entire Write time plus t wr .

O~OIb

2114
AC CHARACTERISTICS
TEST CONDITIONS: Vee = + 5V ± 5%, TA = O°C to + 70°C·

tr = tf = 10ns, VIL = 0.8V, VIH = 2.0V, Output Load = 1 TTL Gate and 100pF
Input and Output Timing Reference Level = 1.5V

READ CYCLE
2114·2
PARAMETER

SYMBOL

Read Cycle Time

tre

2114·3

2114

2114L2
MIN
M~X

2114L3
MAX
MIN

21114L
MIN
MAX

200

300

450

,

Access Time

taa

200

- 300

S to Output Valid

teo

70

100

S to Output Active

tex

20

Output Three-State from Deselect

tOld
t aha

0

Output Hold from Address Change

WRITE CYCLE

450
100
20

20
. 50

80

0

50

UNITS

ns

100

0
50

50

.
2114·2

2114·3

2114

2114L2

2114L
MIN
MAX

Write Cycle Time

twe

200

2114L3
MIN
MAX
300 .

Write Time

tw

120

150

Write Release Time

twr

0

0

Output Three-Stateirom Write

talw

0

Data to Write Time Overlap

tdw

120

PARAMETER

SYMBOL

MIN

MAX

60

0

,

200
0
80

0

150

200
0

Data Hold from Write Time

tdh

0

0

Address Setup. Time

taw

0

0

0

S Select Pulse Width

tew

,120

150

200

100

TIMING DIAGRAMS
READ CYCLE

WRITE CYCLE
A

DOUT--------------------~~~--~rr---

DIN------~~---1
Note: W is high for a READ cycle.

8·7

UNITS

450

ns

2114
2114 BIT MAP DIAGRAM

Vee
AaArAsAsA4A3
r - - - - - r - - -..... 63 r - - - - - r - - -.....

110,"

15-015-0

o

15-015-0

GROUND

8·8

'

D~DlL

M2114L
4096 Bit (1024x4)
NMOS Static RAM

FEATURES

DESCRIPTION

•
•
•
•
•
•
•

The M2114L is a 4096-bit static Random Access
Memory organized 1024 words x 4 bits. The storage
cells and decode and control circuitry are completely
static therefore, no clocks or refresh operations ar~
required. Memory access occurs within the specified
access time after all address inputs are stable. A Chip
Select input is provided for simple memory array
expansion.
.

Cycle Time Equal to Access Time
Completely Static-No Clock Required
Common Data Input and Output
TTL Compatible Inputs and Outputs
883A Class B Processing Available
Single + 5 Volt Power Supply
Maximum Access Time:
- 200 ns (-2)
-300ns (-3)
• .Maximum Power Dissipation: -495mW
• Pin Compatible with Intel M2114
• Military Temperature Operation:
-55°C to +125°C

. BLOCK DIAGRAM

The M2114L is pin and functionally compatible with
the Intel M2114 series, and operations at 90mA over a
5V ± 10% range. The worst-case access time is 450ns
with speeds of 300 ns ( - 3) and 200ns ( - 2) available.
The device is assembled in a standard 18-pin DIP for
.
maximum system packing density.

PIN CONFIGURATION

LOGIC SYMBOL

iii S

vee

A3---I~'

A4 - - - - I

---r::::n
A8 ---r::::n
A5

•

MEMORY ARRAY
64 ROWS
64 COLUMNS

Vee

Ao

A7

A1
A2

A8

Aa

A7 ----f:>1

A3

A9

A8----I~'

Ao

1/0 1

A1

1/0 2

A8

1/°3

AT

1/°4

As

Vi

A9

1/°1--......
1/0 2 ---++-I-r>~
1/0 3 -..-1-1+1

A4
A5

M2114L

1/°4--++1-1+1

(outline dwg IN)

PIN NAMES

s
Vi

Ao-A9

ADDRESS INPUTS
DATA INPUT/OUTPUT
WRITE ENABLE
CHIP SELECT

ORDERING INFORMATION
PART NUMBER

ACCESS TIME

PACKAGE

MD2114L2

200n5

CERDIP

MD2114L3

300n5

CERDIP

MD2114L

450n5

CERDIP

8-9

O~OIb

M2114L
ABSOLUTE MAXIMUM RATINGS
Operating Temperature ...................................... - 55°C to + 125°C
Storage Temperature ...•..................................... -65°C to +150°C
Voltage on Any Pin to Ground ..................................... --{).5V to +7V
Power Dissipation' ................................................'. ........ 1W
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only. and functional operation of the device
. 'at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliapility.

DC CHARACTERISTICS
TEST CONDITIONS: TA = -55°Cto +125°C, Vee = +5V±10%
PARAMETER
Input Load Current

TEST CONDITIONS

SYMBOL

IINlD

Output Leakage Current
Power Supply Current

II0lK

I

ICC1

UNIT!?,

MAX

MIN

10

. VIN = OV to 5.5V
S = 2.4V,.

10

VI/a = O.4Vto VCC
VIN = 5.5V,

65

I'A

11/0 :: OmA, TA = +25°C
Power Supply Current
Input Low Voltage

Vil

-0.5

0.8

Input High Voltage

VIH

2.0

VCC
0.4

VI

VCC

Output Low Volt?-ge
Output High Voltage

J

IOl = 3.2mA
10H = - 2OOI'A

Val
VOH

rnA

90

VIN = 5.5V,
11/0 = OmA, TA = -55'C

ICC2

V

CAPACITANCE
. PARAMETER

SYMBOL

TEST CONDITIONS

UNITS

MAX -

Input/Output Capacitance

CliO

Vila - OV

5

Input Capacitance

CIN

VIN = OV

5

pF

DEVICE OPERATION
When

iN is high, the data input buffers are inhibited to

A read occurs during the overlap of

pre~terroneous

data from getting into the array. As long
as W remains high, the data stored cannot be changed by
the addresses, Chip Select, or data I/O voltage levels and
timing transitions. The block d~ram also shows data
storace cannot be changed by W, the addresses, or the
input-data as long as S is high: Either Sor W by itself,
or in conjuction with the other, can prevent the extraneous
writing due to signal transitions.

S

low and

W high.

Data within the array can only be changed during a Write
time, defined as the overlap of S low and INlow. To
prevent the loss of data, the addresses must be properly
established during the entire Write iime plus t wr .

8·10

M2114L
AC CHARACTERISTICS
TEST CONDITIONS: TA = -55°C to +125°C, Vcc= +5V±10%
tr = tf = 10ns, VIL = 0.8V, VIH = 2.0V, Output Load
Input and Output Timing Reference Level ~ 1.5V

= 1 TTL Gate and

100pF

READ CYCLE
PARAMETER

SYMBOL

M2114L2
MIN
MAX

M2114L3
MIN
MAX

M2114L
MIN
MAX

200

300

450

Read Cycle Time

trc

Access Time

taa

200

300

S to Output Valid

tco

70

100

S to Output Active

tex

Output Three-State from Deselect

told

0

Output Hold from Address Change

toha

50

20

20
60

0

UNITS

450
100

ns

20
80

0

100

I

50

50

WRITE CYCLE
M2114L2
"MAX
MIN

M2114L3
MIN
MAX

M2114L
MIN
MAX

twe
tw

200

300

450

120

150

200

twr

0

0

Output Three-State from Write

tolw

0

Data to Write Time Overlap

tdw

120

Data Hold from Write Time
Address Setup Time

tdh
taw

S Select Pulse Width

tew

PARAMETER

SYMBOL

Write Cycle Time
Write Time
Write Release Time

I

60

0

UNITS

0
80

0

150

200
0

0

0

0

0

0

120

150

200

100

TIMING DIAGRAMS
READ CYCLE (1)

WRITE CYCLE

----trc - - -

ADDRES!E

lao

*___ADDRES~~--"--~~~~~~I-W-C----~--~~

_._-----=--

'!

Vi

loha
DOUT--------------------~~~--~~----

DIN

Nole:

1. IN is high for a READ cycle.

8-11

------~r_---.,..----,_

ns

O~OI!,

M2114L
2114 BIT MAP DIAGRAM
Vee

AeA7AeAsA4A3
~----~----~63 r-----Y-----~

1/03

15-015-0

o

15-015-0·

AgA2A1Ao
GROUND

8-12

2147
.4096 Bit· (4096 X 1).
HMOS Static RAM
GENERAL DESCRIPTION

FEATURES
• High speed - 55ns maximum acc'ess time
• Automatic low-power standby - 550mW (2147L)
• Completely static - no clock required
• Single + 5V supply
• TTL compatible inputs and outputs
• Three-state output
• HMOS Process technology
• Industry standard 2147. pin compatible

The Intersil 2147 is a low power, high-speed 4096-bit 'static
RAM organized 4096 words by 1 bit. It is an advanced
version of the industrY standard 2147, fabricated using Intersil's HMOS single-layer poly selective-oxidation process. Innovative design techniques result in minimum cell
area and optimum circuit performance.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
.
An automatic low-power standby mode is controlled by
chip select (8); less than one cycle time after S goes high,
power dissipation drops from a maximum of 160mA to
20mA (2147).
The basic device operates over the 5V ± 10% range with a
worst-case access time of 70ns. A "- 3" device is
available with a worst-case access time of 55ns.
The Intersil 2147 is supplied in an 18-pin package with
industry standard pin configuration.

BLOCK DIAGRAM

PIN CONFIGURATION.LOGIC SYMBOL
W

AO
AO
Al

Al
A2

A2
A3
A4
AS

64 x 64
MEMORY ARRAY

A3

Q

A4

GND

AS

5 vcc

AO
Al

VCC
A6
A7
AS
A9

A2
A3
A4
AS
A6
A7
AS
A9

Al0
All
D

5

D

2147
Q

Al0
All
D----------~1:>1

(outline dwg IN)

Q

GND

~P=I~N~N~'A~M~E~S~--~=A=0-~A=11~=A=D=D=R=ES=S=I=N=P=UT=S~~

5 - -......01

D
Q

W---4--I
W

DATA INPUT
DATA OUTPUT
CHIP SELECT
WRITE ENABLE

ORDERING INFORMATION
PART NO.
02147-3
02147L
02147

ACCESS TIME
55ns
70ns
70ns

ACTIVE CURRENT
180mA
140mA
160mA

\

STANDBY CURRENT
30mA
10mA
20mA

8-13

PACKAGE
18 Pin CEROIP
18 Pin GEROIP
18 Pin CEROIP

TEMP. RANGE
OOG to +70 D G
OOG to +70°C
OOG to +70 o G

[iJ

O~OIL

2147
ABSOLUTE MAXIMUM RATINGS1
SYMBOL

DESCRIPTION

MIN

MAX

UNITS

NOTES

VIN
los
tSTORE
tSIAS
PD

Voltage on any Pin Relative to GND
D.C. Output Current
Storage Temperature
Ambient Temperature Under Bias
Power Dissipation

-1.5

+1
20
+150
+85
1

V
mA
'C
'C
W

2

/

-65
-10

NOTES:
'1. Stresses greater than ,those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of
the device at these or any other conditions exceeding those indicated in the opera'tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
2. This device contains,internal circuitry to Protect against damage due to static charge. Conventional precautions should be observed,
.
however, during storage, handling, and use to 'avoid exposure to excessive voltages.
ELECTRICAL PARAMETERS
SYMBOL
VIH
Vil
VOH
VOL
III
IOlK
lOS

SYMBOL
ICCOP1
ICCOP2
ICCSS
ICCPON

vee = sv ±

DESCRIPTION
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOVY Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current

DESCRIPTION
Operating Supply Current ,
Operating Supply Current
Standby Supply Curreot
Peak Power-On Supply Curren

10%, TA

MIN
2.0
-1.0
2.4

= ooe to +'70oe, unless otherwise noted

MAX

MAXIMUM VALUES
2147
2147·3
2147l
170
135
150
140
160
180
10
20
30
70
30
50

NOTES:
1. VCC ~ 5.5V, S = VIL, 10 = 0
2. TA = 25'C
3. TA = O°C
4. VCC = 4.5 to 5.5V, § = VIH
TIMING PARAMETERS

V
V
V
p.A
p.A
mA

0.4
10
SO
200

-200

VCC = SV.±10%, TA =

DESCRIPTION

twp

Write- Recovery Time

acs1
tacs2

toh
tlz
thz

. tou
pd
.twc

Icw
law
-t as

I- tdw
Idh
Iwz
tow

VOUT

~ 1V/lls.

t wr -

trc

VCC - S.SV, GND :5 VIN :5 VCC
VCC = S.SV, S
VIH, GND :5 VO :5 4.SV

=
= GND to VCC

,

5. VCC = GND to 4.5V, S = lower of VCC or VIH min. Apullup resistor on S is required diJring power-on in order to keep the device
deselected; otherwise ICCPON approaches ICCOP. VCC 'slew

READ CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Hold from·Address Change
Chip SelE!ction to Output Enabled
Chip Deselection to Output Disabled
Chip Selection to Power Up Time
Chip Deselection to Power DownTime
WRITE CYCLE
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set~p Time
Write Pulse Width

taa

IOH - +4.0mA
IOL - SmA

UNITS NOTES
mA
1, 2
2, 3
mA
mA
4
mA
5

ooe to +70 oe,

JEDEC
SYMBOL

TEST CONDITONS

UNITS
V

6.0
O.S

Data Valid to End of Write
Data Hold Time
Write Enabled to Output Disabled
Output Active from End of Write

SYMBOL

unless otherwise noted1, 4

2147
MIN

2147-3
MAX

70
TAVQV
TSLQV
TSLQV
TAXQX
TSLQX
TSHQZ

.

MIN

. NOTES:
1. Ir = t f = 10ns. Input and output timing reference level = 1.5V.
2. Device deselected for 55ns or more prior to selection.
3. Device deselected for a finite time less than 55ns prior to selection.

UNITS

NOTES

55
70
70
80

5
10
0
0

40

55
55
65
5
10
0
0

70
55
55.
0
40
15
30
10
0
0

35

55
45
45
0
35
10
25
10
0
0

2
3

40
.30

30

TSLWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH.
TWHDX
TWLQZ
TWHQX

. MAX

ns

30

4. Operating temperature range is guaranteed with transverse ai'r
flow exceeding 400 linear feet per minute.

2147
TIMING DIAGRAMS
Read Cycle (Address)

,
-'
'-

ADDRESSES
(AD-All)

)K

ADDRESSES VALID

. taa
_toh
DATA OUT
(0)

/

"-

PREVIOUS DATA OUT VALID

DATA OUT VALID

'-

I

,Notes: 1. Device is continuously selected, S = VIL.
2. Write Enable is high for read cycle, Vii = VIN.

'Read Cycle (Chip Select)

CHIP SELECT
(ll")

~

-

'"

,

. tacs
HIGH

DATA OUT
(0)

=t
z

-tpu

./

!
I.

-'
'-

DATA OUT VALID

E

- .-

"

./

HIGH
Z

j-tpd

--- - - - -

ICCOP
VCC CURRENT
ICCSB _ _ _ _

~.

Note: Address is valid prior to or coincident with

S transition

low,

Write Cycle (W Controlled)
twc

----------------+-\

ADDRESSES
(AD-All)

CHIP SELECT

. (5)

WRITE ENABLE
(W)

DATA IN
(D)'

HIGH

DATA OUT
(0)

z

8-15

r:III
~-

n~ulb

M2i47
,4096 Bit (4096 x,i)
HMOS 'Static RAM

FEATURES
• High ,speed - 85ns maximum acc,ess time
• Automatic low·power standby"':'" '30mA maximum
• Full military temperature range
• 883A Class B processing available
• Completely static - no clock required
• Single + 5V supply
• ,TTL compatible inputs and outputs
• Three·state outputs
• HMOS process technology
.. Intel M2147 compatible

GENERAL DESCRIPTION
'The Intersil M2147 isa high·speed 4096·bit static RAM
organized 4096 words by1 bit, fabricated with Intersil's
HMOS single-layer poly selective-oxidation process, Innovative design techniques result in minimum cell area
and optimum circuit performance,
"
'
,
'Inputs ,and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
, structures.
An automatic low-power standby mode is controlled by
chip select (8); I,ess than one cycle time after S goes high,
power dissipation, drops from a maximum of 180mA to
30mA.
The device operates over the full military temperature
range ( - 55°C 'to + 125°C) at 5V ±10% with a worst-case
access time of'85ris, arid is supplied In an 18-pin package
with industry standard pin configuration,

BLOCK DIAGRAM
AO
Al
A2

64 x 64
MEMORY ARRAY

PIN CONFIGURATION

A3

LOGIC SYMBOL
Vi

A4

s vce

AS

a

0

s

IIi1

AO
Al,
A2
A3

vcc

A4

A9

AS

A10
All
0

A6
A7'
AS

a
Vi
GND

5

AO
Al
A2
A3
A4

0

AS
A6
A7
AS

a

A9

A10
All

Vi

(outline dwg IN) ,
PIN,NAMES

-=

TRUTH TABLE,

AO-A11
-D

ADDRESS INPUTS
DATA INPUT
DATA OUTPUT
CHIP SELECT
WRITE ENABLE

Q

S
W

,

S

Vi

MODE: '

OUTPUT

~CC

H

X

Not 'Selected

"High Z

Standby

L

L

Write

High Z

Active

L

H

Read

Dour

Active

ORDERING INFORMATION
-

PART NO.
MD2147

"

, ACTIVE CURRENT

TEMP. RANGE

180mA

8-16

'O~OIb

M2147
ABSOLUTE MAXIMUM RATINGS
Voltage on any Pin Relative to GND . '......................... -1.5 to +7 Volts
D.C. Output Current ..•.... : ........... " ............................ 20m A '
Storage Temperature ...........•................ : .......... -65 to +150°C
Ambient Temperature Under Bias ............................ -65 to +135°C
Power Dissipation .•.................................................. 1W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational. sections of the spec;:ifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC CHARACTERISTICS
SYMBOL
VIH
Vil
III
VOH
VOL

10lK
leeOPl
leeOP2
leesB
leepON
los

1 vce = 5V ±10%. TA = -5oo e to +125°e unless otherwise noted

DESCRIPTION
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output HIGH Voltage
Output LOW Voltage
Output Leakage Current
Operating Supply Current
Operating Supply Current
Standby Supply Current
Peak Power·On Supply Current
Output Short Circuit Current

0.01

SYMBOL
trc
taa
tacS'l
ta~s2

toh
tlz
thz ,
tpu
tpd
twc
Icw,
taw
tas
twp
twr
tdw
tdh
twz
tow.

MAX
6.0
0.8
10

2.4
0.45
50
160
180
30
70
200

0.1
120
15
35
-200

NOTES:
1. Typical values are measured at VCC.= 5.0V. TA = 25°C and
are not guaranteed.
2. VCC = 5.5V, GND ~ VIN ~ VCC
3. 10H = -1.0mA
4. 10L = 5mA
5. VCC = 5.5V. § = VIH, GND ~ VO ~ 4.5V
6. VCC = 5.5V. § = VIL. 10 = 0

AC CHARACTERISTICS

M2147
TYP

MIN
2.0
-0.3

7.
8.
9.
10.

UNITS
V
V

NOTES

ILA
V
V

2
3
4
5
6, 7
6, 8
9
10

ILA
rnA
rnA
rnA
rnA
rnA

TA= 25°C
TA=-55°C
VCC = 4.5 to 5.5V, § = VIH
VCC = GND to 4.5V, S = lower of VCC or VIH min. A pullup
resistor on § is required during power-on in orderto keep the
device deselected; otherwise ICCPON approaches ICCOP.
VCC slew rate ':0: WIlLS.

vee = 5V ±10%, TA = -55°e to +125°e, unless otherwise noted

DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output Enabled
Chip Deselection to Output Disabled
Chip Selection to Power Up Time
Chip Deselection to Power Down Time
WRITE CYCLE
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output Disabled
Output Active from End of Write

JEDEC
SYMBOL

M2147
MIN

MAX

UNITS

TEST CONDITIONS

85
TAVQV
TSLQV
TSLQV
TAXQX
TSLQX
TSHQZ

85
85
100
5
10
0
0

Note 2
Note 3

40
30
ns

TSLWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TWHDX
TWLQZ
TWHQX

85
70
70
0
55
15
35
10
0
0

50

NOTES:
1. tr = t f = 10ns. Input andoutputtiming reference level = 1.5V. AC test conditions on page 8·19.
2. Device deselected for 55ns or more prior to selection.
3. Device deselected for a finite time less than 55ns prior to selection.
8·17

M21'47
TIMIN.G DIAGRAMS
Read Cycle (Address)

ADDRESSES

ADDRESSES VALID.

IAG-A11)

DATA OUT
(0)

DATA OUT VALID

Notes: 1. Device is continuously selected,S = VIL.
2. Write Enable is high for read cycle, iN = VIH.

ReadCycle (Chip Select)

CHIP SELECT

(S)

DATA OUT
(0)

DATA OUT VALID

VCC CURRENT
ICCSB _...,..._______"

Note: Address is valid prior to or coincident with

5 trahsition low.

Write Cycle (WControlled)

ADDRESSES.
IAG-A11)

,

ADDRESSES VALID

CHIP SELECT

(s)

WRITE ENABLE
(w)

DATA IN
(D)

HIGH

DATA OUT
(0)

z
8·18

U~UIL

M2147
Vee

Dour

0-----,-----1
300n

- 30pF (INCLUDES SCOPE AND JIG)

OUTPUT LOAD

AC TEST CONDITIONS
Input Pulse Levels ................................................ GND to 3.SV
Input Rise and Fall Times ........................................ Ir = tj= 101-'5
Input and-~utput Timing Reference Level .................................. 1.SV

-\

8·19

2148
4096 Bit (1024 X 4)
'HMOS,Static RAM
GENERAL DESCRIPTION

FEATURES
•
•
•
•
•
•
•
•

High speed - 55ns maximum access time (2148-3)
Automatic'low-power standby - 165mW maximum
Completely static - no clock required
Single +5V supply
TTL compatible inputs and outputs
Three-state outputs
HMOS Technology
Pin compatible with industry standard 2114 and
2148 devices

BLOCK DIAGRAM
A3 "
A4
AS

MEMORY ARRAY
64 ROWS
64COLUMN$

A6

The Intersil 2148 is a high speed ,4096 bit static RAM organized 1024 words by 4 bits. It is a single-layer poly HMOS
version of the industry standard 2114, and pin'compatible
with both the 2114 and 2148. 'Innovative design techniques
result in minimum cell area and optimum circuit performance.
Inputs and three-state outputs a~e TTL ~ompatible arid allow
for direct interface with common system bus structures.
An automatic low-power standby mode is controlled by chip
select S;,less than one cycle time after Sgoes high, operating
'current drops from a maximum of 140 rnA to a standby
current of 30 rnA.
The basic device operates over the 5V ±10% range with a
worst-case access time of 70ns. A "-3" device is available
with a worst-case access time of 55n9,
The Intersil 2148 is supplied in an 18-pin package with
'industry standard pin configuration.

PIN CONFIGURATION

LOGIC SYMBOL

A7,
A6

...

A8

Vcc S
AD
Al
A2
A3
A4
AS
A6
A7
A8
A9

COLUMN 110
CIRCUIT

1/01

1/02
1/03
1/04

Vi

2148

1/01
1/02
1/03,
1/0.

':' GND

(outlinedwg IN)

TRUTH TABLE
W--1L-.I

PIN NAMES
PIN NAMES

Address Inputs
Data InpuVOutput
Chip Select
Write Enable

Ao-A9
1/0,-1/04

S
W

s

w

H

X

L
L

H

L

'MODE
Not Selected
Write
Read,

1/0
High-Z
DIN'
DOUT

POWER
Standby
Active
Active

ORDERING INFORMATION
PART NO.
02148
D2148~3

ACTIVE CURRENT
140mA

STANDBY CURRENT

PACKAGE

TEMP. RANGE

70n8

30mA

18 pin CERDip

O·C to +70·C

55n8

140mA

30mA

18 pin CERDIP

O·Ctc +70·C

ACCESS TIME

8-20

n~nlb

2148
ABSOLUTE MAXIMUM RATINGS

Voltage on any Pin Relative to GND1 ......................................... -1.5 to +7V
D.C. Output Current ............................................................. 20mA
Storage Temperature ...... : .............................................. -'65 to +150°C
Ambient Temperature Under Bias ......... : ................................. -10 to +85°C
Power Dissipation ................ .'................................................. 1.2W
Stresses above those listed under Absolute Maximum Ratings may cause permanentdamageto'the devi~e. These are stress ratings only. and functional operation of
the device at these or any other conditions above those Indicated In the o'perational sections of the specifications Is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
NOTES:
1. This device contain~ internal circuitry to protect against damage due to static charge. Conventional' precautions should be observed,
however, during storage, handling, and use to avoid exposure to excessive voltages .

. ELECTRICAL PARAMETERS
SYMBOL
VIH
Vil
VOH
VOL
hlK
10lK
los

Vcc = 5V ±10%, TA =

DESCRIPTION
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current

SYMBOL
ICCOP1
ICCOP2
ICCSB
ICCPON

oae to+70ae, unless otherwise noted

MIN
2.0
-1.0
2.4.

MAX
6.0
0.8
0.4
10
5q
150

150

t re .
Is.
Issel
Isse2
toh
tlz
thz
tpu
tpd
two
tow
taw
tas
twp
twr
tdw
tdh
twz
tow

,
NOTES
1,2
1,3
4
5

UNITS
mA
mA
mA
mA

-

NOTES:
1. Vcc = S.5V. S = VIL. 10 = limA
2. TA = 25°C
3. TA = O'C

SYMBOL

10H --2.0mA
IOl-8mA
Vcc - 5.5V, GND :5 VIN :5 Vee
S - VIH, Vee - 5.5V, GND :5 Vo :5 4.5V
Your - GND to Vee

MAXIMUM VALUES
2148;3
2148
135
135
140
140
30
30
50
50

DESCRIPTION
Operating Supply CLlrrent
Operating Supply Current
Standby Supply Current
Peak Power-On Supply Current

TIMING PARAMETERS

NOTES

UNITS
V
V
V
V
p.A
p.A
mA

4. Vcc = 4.5 to 5.5V. S = VIH
5. Vcc=GNDto 4.5V. S= 10werofVcc orVIHmln.ApuliupresistoronSls
required during power-on in ordertokeepthedevicedeselected;otherwise ICCPON approaches Iccop. Vcc slew" lV1p.s.
Vcc

= 5V ±10%, TA = oae to +70ae Unless otherwise noted, 1,4

DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output Enabled.
Chip Deselection to Output Disabled
Chip Selection to Power Up Time
Chip Deselection to Power Down Time
WRITE CYCLE
Write Cycle Time
Chip Selection to End of Write
Address Valid· to End of Write
Address Setup Time
, Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output Disabled
Output Active from End of Write

JEDEC
SYMBOL

2148-3
MIN

2148

MAX

MIN

55
55

65
5
15
0
0

25

5
15
0
0

55
50
50
0

40
5
25
5
0
5

NOTES

25

70
70
80

2
3

25

5
5

30

30

TSLWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TWHDX
TWLQZ
TWHQX

UNITS

70

55
TAVQV
TSLQV
TSLQV
TAXQX
TSLqX
TSHQZ

MAX

70
65
65
0
50
5
25
5
0
5

,

ns

.-

25

5

NOTES:
1. tr = lf = 10ns. Input and output timing reference level = 1.SV. VIL = OV. VIH = 3.0V.
2. Device deselected for 55ns or more prior to selection.
• 3. Device deselected for less than 55ns prior to selection. For deselect time of Ons prior to seJect. read cycle (address' applies.
4. Operating temperatu~ range Is guaranteed with transverse air flow exceeding 400 linear feet per minute.
6. tlz and thz are measured from 1.5V level of 5 to ± 5O'lmV from high Impedance voltage of load circuit. tlz and thz are sampled and not 100% tested.
CAPACITANCE TA = 25°C, f = 1.0mHz
SYMBOL
PARAMETER
MAX
Input Capacitance
5
Output Capacitance

7

Note: Capacitance sampled and not 100% tested.
8-21

2148

O~OI!,

TIMING DIAGRAMS

ADDRESSES
(AG-A9)

DATA OUT
(110,-1/04)

Read Cycle (Address)

_ _ _ _ _ _ _ _J

_ _ _ _ _ _ _ _ _ _ _ _ _ _' "

Notes: 1. Device is continuousiy selected., S = VIL.
- 2. Write enable is high for read cycle, iii = VIH.

_Read Cycle (Chip Select)

D~T:,_?t~~

Icc

____

..;.;H;.;;;IGH;.;.;Z;;....._+-_ _ _~

OP--.:.-----___-,--- ~- ----hr-.----'-------------t-.---"'"""'\.

S8-----------'

Notes:
)
.
_
1. Address is valid prior to or coincident with S transition low..
2. Write enable is high for read cycle, iii =·VIH.

Write Cycle(W Controlled)
ADDRESSES
(AO-A9) _\;......_ _ _ _ _~

ADDRESS VALID

DATA IN

In.-.
I:iiI

DATA OUT

Write Cycle

(5 Controlled)

ADDRESS

DATA IN

.OATAOUT

Note: Outpuis remain high-Z if

S, iii go high simultaneously.
8-22

2148
TEST LOADS

+5V

+5V

510fl

51011

Dour --.--~4
330fl

Dour -~----:--1
330n

30pF
.
(INCLUDING SCOPE AND JIG)

AC PARAMETER LOAD CIRCUIT

5pF

liz, 1hz LOAD CIRCUIT

8·23

M2148
4096 Bit (1024 X 4)
HMOS Static RAM

D~DIL

FEATURES
• High speed - 85nsmaxlmum access time
• .Automatic low-power standby- .165mW maximum
• Completely static - no clock required
• Single + 5V supply
• TTL compatible inputs and outputs
• Three-state outputs
• HMOS Technology
• Pin compatible with Industry standard 2114M and
M2148 devices
BLOCK DIAGRAM
A3

GENERAL DESCRIPTION
The Intersil M2148 is a highcspeed 4096:bit static RAM
organized
1024 words by 4 bits. It is a single-layer poly
HMOS version of the industry standard 2114 and pin compatible with both the 2114M and .M2148.lnnovative design'
techniques result in miriimum cell area and optimum .
circuit performance.
.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
.
An automatic low-power standby mode is controlled by
chip select S; less than one cycle time after S goes high,
operating current drops from a maximum of 180 rnA to a
standby current of 30 mA.
The device operates over the 5V ± 10% range with a worstcase access time of 85ns and is supplied in an 18-pin
packag,e with industry standard pin configuration.

A4
AS

M~MORY

ARRAY
64 ROWS
64 COLUMNS

A6

PIN CONFIGURATION

LOGIC SYMBOL

A7

Vce 5

....

AS

AO
Al
A2
A3
A4
AS
A6
A7
AS

1/0,

1/02

M2148

1/03
1/04

Vi

M2148

1/0,
1/0,
1/03
1/04

A9

= GND

W -'-,L-.I

PIN NAMES
.!

S
H
L
L

PIN NAMES
Address Inputs
Data Input/Output
Chip Select
Write Enable

Ao-A9
1/01-1/04'

§
W

W

x
L

H

MODE
Not Selected
Write
Read

1/0
High-Z
DIN
DouT

. POWER
Standby
Active
Active

ORDERING INFORMATION
ACCESS TIME

85ns

ACTIVE CURRENT
180mA

STANDBY CURRENT
30mA

8-24

PACKAGE
18 pin CERDIP

TEMP. RANGE
-55· to +125·C

M2148
ABSOLUTE MAXIMUM RATINGS
Voltage on any Pin Relative to GND1 ......................................... -1.5 to +7V
D.C. Output Current ............................................................. 20rnA
Storage Temperature ..................................................... -65 to +150°C
Ambient Temperature Under Bias ......... : ................................ - 65 to +135°C
Power Dissipation .........................................•........................ 1.2W
Stresses above those listed under Absolute Maximum Ratings maycause permanent damage to the device. These are stress ratings only. and functional operation of
the device at these orany other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

NOTES:
1. This device contains internal circuitry to protect against damage due to static charge. Conventional precautions should be observed,
however, during storage. handling, and use to avoid exposure to excessive voltages.

ELECTRICAL PARAMETERS
SYMBOL
VIH
VIL
VOH
VOL
hLK
10lK
los

Vee

= 5V -+ 10% , TA = - 55°C to

DESCRIPTION
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current

-200

MAX
6.0
0.8

tre
t.a
tascl
tasc2

toh
tlz
thz
tpu
'tpd
!we
tew
taw
tas
twp
twr
tdw
tdh
twz
tow

IOH - -1.0mA
IOL - 5.0.mA
Vee - 5.5V, GND < VIN < Vee
S - VIH, Vee - 5.5V, GND '" Vo '" 4.5V
VOUT - GND to Vee

UNITS

NOTES

160
180
30
70

rnA
rnA
rnA
rnA

1,2
1,3
4
5

4. Vce = 4.5 to 5.5V. S = V'H
5. Vce = GND to 4.5V. S = lower of Vce or V'H min. A pulfup resistor on Sis

NOTES:
1. Vcc = 5.5V. S = V'L. 10 ,; OmA
2. TA = 25°C
3. TA=-55°C

SYMBOL

NOTES

MAXIMUM VALUES
M2148

Operating Supply Current
Operating Supply Current
Standby Supply Current
Peak Power· On Supply Current

TIMING PARAMETERS

+ 125°C, unless otherwise noted

UNITS
V
V
'V
V
p.A
p.A
mA

0.45
10
50
200

DESCRIPTION·

SYMBOL
ICCOP1
ICCOP2
ICCSB
ICCPON

MIN
2.0
-1.0
2.4

required during power-on in orderto keep the device deselected; otherwise IcepON approaches leeop. Vee slew ~ 1V/lls.

Vee

5V ± 10%,

TA

DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output Enabled
Chip Deselection to Output Disabled
Chip Selection to Power Up Time

- 55·C

t.o + 125°C

JEDEC
SYMBOL

Unless otherwise noted, 1, 4

M2148
MAX

MIN

NOTES

85
TAVOV
TSLOV
TSLOV
TAXOX
TSLOX
TSHOZ

5
10
0
0

85
85
100

2
3

40

5
5

30

Chip Deselsction to Power Down Time

WRITE CYCLE
Write Cycle Till)e
Chip Selection to End of Write
Address Valid to End of Write'
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output Disabled
Output Active from End of Write

UNITS

TSLWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TWHDX
TWLOZ
TWHOZ

85
70
70
0
55
.15
35
10
0
10

ns

-

50

5

NOTES:
1. tr= 11'= 10ns. Input and output timing reference level = 1.5V. V'L =OV. V'H = 3.0V.
2. Device deselected for 55ns or more prior to selection.
3. Device deselected for less than 55ns prior to selection. For deselect time of Ons prior to select, read cycle (address) applies.
4. Operating temperature range is guaranteed with transverse air flow 'exceeding 400 linear feet per minute.

5. tli and thz are measured from 1.5V level of S to ± 500mV from high impedance.voltage of load circuit. tlZ and thz are sampled and not 100% tested.

Input Capacitance
Output Capacitance

N~te:

8·25

Capacitance sampled and not 100% tested.

U~UIL

. M2148
TIMING DIAGRAMS

Read Cycle (Address) .

ADDRESSES
(AD-AS) _ _ _ _ _ _ _ _ _-'

=======J~~~~~~~~~5~========:--...,....-----

DATA
OUT
(1/0,-1/04) _ _- ' -_ _ _ _ _ _ _ _ _-'
Notes: 1. Device is.·.continuously selected, S = VIL.
2. Write enable is high for read cycle, Iii =' VIH.

Read Cycle (Chip Select)

z

ICC

S8----------'

Notes:
1. Address is valid prior to or coincident with § transition low.
. 2. Write enable Is high for read cycle, Iii = VIH ..
"0

.

_

Write Cycle (W Controlled)
ADDRESSES
(AO-A9)

ADDRESS VALID
------~

DATA IN

Write Cycle (5' Controlled)

ADDRESS

DATA IN

DATA OUT
Note: Outputs remain high-Z if

S. Iii go high simultaneously.
8-26

M2148
TEST LOADS·

+5V

+5V
510n

DOuT-__+--~

33011

DOUT-__+---.

30pF

33011

5pF

(INCLUDING SCOPE AND JIG)

AC PARAMETER LOAD CIRCUIT

liz. 1hz LOAD CIRCUIT

8·27

IM5200
Field Programmable
Logic Array
(FPLA)
GENERAL DESCRIPTION

FEATURES
•
•
•
•
•
•
•
•
•

Avalanche Induced Migration (AIM) Programmability
48 Product Terms, 14 Inputs, 8 Outputs
Output Active Level - High or Low
Product Term Expandability
Edit Flexibility
DTLlTTL Compatible Inputs and Outputs
tpd - typically 65 ns
5 Volt ± 5% Power Supply
Passive Pullup Outputs

APPLICATIONS
•
•
•
•
•

Random Combinatorial Logic
Code Conversion
Microprogramming
Look-up Tables
Control of Sequential Circuits,
Counters, Registers, RAMs, etc.
• Character Gen.erators
• \Decoders or E~coders

LOGIC DIAGRAM

The IM5200, field programmable logic array (FPLA),
is useful in a wide variety of logic applications. The device
has 14 inputs and 8 outputs. The FPLA may have up to 48
product terms. Each product term may haye up to 14
variables and each one of the outputs provides a sum of the
product terms. The FPLA is functionally equivalent ,to a
collection of AND gates which may'be OR'ed at any of its
outputs. Since some functions are more easily represented
in their inverted form, the output level is also programmable to either a high or low active level. The IM5200 is
provided with passive pullup outputs. This output configuration is useful for product term expansion by wire-ANDing
the outputs of different IM5200's.

PIN CONFIGURATION (outline dwg JG)

'a
"

'2

'3
's"
'6

'7

'.

'.

INPUT
BUFFERS

ElEMENTS
(28 x 4BJ
OUTPUT ACTIVE
LEVEL ARRAY
8 PROGRAMMABLE
elEMENTS
(8 x 11

''a

'"'12

m
'13

TOP

view

SUMMING ARRAY
384 PROGRAMMABLE

OUTPUT

ELEMENTS
(8 x 48)

BUFFERS

ORDERING INFORMATION
MEMORY CIRCUIT MARKING AND PRODUCT
CODE EXPLANATION
1M

'
LS

5200

C

JG

~paCkage
.

'
JG = Cerdip 24 Pin Dip
Temperature Range C = O·C to +70·C
Device TYPe
.

'-~-------Intersil

8-28

Memory

IM5200
MAXIMUM RATINGS
-0.5Vto + 7V
-1.5V to + 5.5V
- 0.5V to + 5.5V
- 65 °e to 150 0 e
OOeto +70 0 e

Supply Voltage Rating
Input Voltage
Output Voltage (Operating)
Storage Temperature
Operating Temperature

ELECTRICAL CHARACTERISTICS
SYMBOL

5.0V +5%, TA

Vee

PARAMETERS

MIN

ooe to 70°C

TYP,

MAX

-0.63

-1.0

mA

VIL = OAV

40

pA

VIH=4.5V

IlL

low level input current

IIH

High level input current

V IL

Input low threshold voltage

V IH

Input high threshold voltage

Vc

Input clamp voltage

BV in

I nput breakdown voltage

5.5

V OH

Output high voltage

204

ICEX

Output leakage current

ISC

Output short circuit current

VOL

Output low voltage

ICC

Power Supply Current

Cin

Input capacitance

5

Cout

Output capacitance

tpd

Input to output switching
delay
(t+_, t++, t_+, t __ )

5

0.8
2.0

UNITS

CONDITIONS

V
V

-.9

:"1.5

V

liN = -10 mA

6.5,

V

liN = 1.0mA

3.25

V

!OH = -2501lA

,

<1

50.

IlA

VO= 5.5V

-1.1

-1.7

mA

VO=OV

V

IOL=12mA

mA

Inputs"either open
or at ground (see
note 3).

10

pF

Yin = 2.0V, VCC = OV

7

12

pF

Vo = 2.0V, VCC = OV

65

100

ns

See switching
test circuit

-0.7

-

0.3

0045

135

20

-

NOTE 1: Conditions for all typical values are V CC = 5V. T A = 25° C.
NOTE 2:Conditions ior all maximum and minimum specifications are the worst case for the comp~ete range of V CC and T~.
NOTE 3: Power consumption will increase after programming. The increase will be typically 0.75 rnA per product term proQ!ammed.

SWITCHING DELAY
TEST CIRCUIT

SWITCHING WAVEFORMS

vcc

R'

300n

CL

J'O"

R2
600n

FREQ'" lMHz
DUTY CYCLE,. 50%
AMPLITUDE = OV to 3V
tR '" tF = 5 ns

ALL MEASUREMENTS MADE AT l.5V LEVELS

8·29

'IM5200
PRODUCT DESCRIPTION
AVALANCHE INDUCED MIGRATION TECHNOLOGY
The AIM element is a minimum size, open base, NPN
transistor. The emitter is contacted by an aluminum
"column" line and the collector is common with the
collectors of other elements and the "row" driver collector.
A conventional gold doped TTL process is used t~ fabricate
the AIM element and all other ,transistors, diodes and
resistors on the chip. The programming technique is to
force a high current through the element from emitter"to
collector, This forces the emitter·base jLinctionbeyond
normal avalanche and into a second breakdown mode, In
the second breakdown, the current constricts to a narrow
high temperature filament. Aluminum then migrates down
the filament to the emitter·base·junction and causes a short
of that junction. The drop in power dissipation, as soon as
the emitter·base short is achieved, causes a ,decrease in
temperature. Since temperature is a driving force in the
programming action, further advance of migrating alumi·
num is inhibited after programming is achieved, The action
is thus self·limiting, The AIM programming technique
assures superior reliability since the element junction where'
the programming action occurs is inherently hermetic.
GENERAL DESCRIPTION
The IM5200 Field Programmable Logic Array (FPLA)
is a logic element designed to produce a sum of
product terms, which may be programmed by the user, at
each of eight outputs. The basic operating circuit is
comprised of 56 input inverters, which generate the'true
and complement of the 14 inputs, 48 twenty-eight input
AND gates, 8 forty-eight input NOR gates and 3 arrays of
AIM programmable elements. Additional circuitry is dedicated to the functions of programming and testing before
programming. All outputs have 4K resistor pull-Ups which

permit wire-ANDing. Inputs are DTL and TTL designs with
2 VB E operating thresholds.
.
Product Term Array
The Product Term Array, consisting of a 48,x 28 'element
AND array, allows the desired true or complement inputs
to be connected by programming to the 48 AND gates
which form the product terms. Only the input variables
included in the product terms are programmed. New
variables may always be added to a previously programmed
product-term until all 14 variables have been used,
Summing Array
A 48 x 8 element OR array allows any combination of as
many as 48 product terms to be 'logically summed (OR'ed)
at each output by programming.
Output Active Level Array
The Output Active Level Array consists of eight elements,
one per output, which provide'for changing the active level
of any output from LOW to HIGH. Active LOW is the
necessary, active state when expanding product terms by the
parallel connections of two (2) or more IM5200s. The
programmable active HIGH feature may be used to advantage in nonexpanded applications to save inverters andlor
product terms when system considerations so req ui reo
LOGIC OPERATION
The operating logic and AI M programmable,element arrays
are shown in Figure 1. In logic equation form each output
can be expressed in the SUM OF PRODUCTS form.
Fi or

Fi = logical sum of any user programmed combination of 48 available prod,uct terms (PTj )
where PTj = any user programmed combination of the true or cO,mplement of the 14
available inputs (lk).

8EFORE

PROGRAMMING

AFTER
PROGRAMMING

'"

NOTES
1. Programming Logic and
, Preprogramming Test Logic
is not shown.

2.

Active Level Inversion Elements
(8 total)

"
Figure 1. FPLA Operating logic.
8-30

IM5200
Some examples of possible SUM·OF·PRODUCT·TERMS
functions and individual PRODUCT TERMS are:

3. Checking the accuracy of programming circuitry
decoding

SUM OF PRODUCT TERMS

4. Checking the integrity of programming p'aths under
programming conditions

Fl = PT 3 +PT 28 + PT 39 + PT47
F3 = PT 1 + PT33

+ PT39

+ PT45 + PT46 + PT47

F7 = PT2
PRODUCT TERMS
PT 3 = 10 T2 T8 T13
PT46 = 1116 19 111 T12 113
PT 2 = 14
A . product term is not .necessarily a minterm since a'
minterm contains all input variables. The unprogrammed
inputs of a product term that is not a minterm are "don't
care". For example, the product term 11 13113 will activate
any output to which it is programmed whenever the 11
input is HIGH, 13 is HIGH, and 113 is LOW, regardless of
the logic state of the other inputs. A minterm expansion of
11 13 T13 would produce 211 miniterms which means there
are 211 out of 214 possible combinations o.t all 14 input
variables that will activate arw output to which the product
term is programmed.
Any minterm condition applied to the IM5200 inputs will
select (1) no product terms, (2).one product term, or (3)
more than one product term.

This test capability assures high programming yield and
data sheet electrical performance after programming of
parts.

PRODUCT TERM MINIMIZATION TECHNIQUES
Standard two (2) level multi·output minimization tech·
niques (e.g. Quine·McCluskey algorithm) can be used to
realize a minimal sum of product terms. In certain cases,
the number of product terms can be further reduced by
sharing product terms and by inverting the output active
level. These techniques are important in cases iNhere the
initial specification indicates a need .tor more than 48
product terms.
APPLICATION OF BOOLEAN REDUCTION
REALIZE:

Fl =1211 1 0 + 12 11 1 0 ;: 12 11 10
Applying the distributive law, product terms
12 11 10 and 12 11 To can be expressed as
12 11 (10 + To). By the law of complement,
10 + To = 1 and the entire expression is
reduced to:
Fl =1211 TO+ 1211

PRODUCT TERM SHARING
Fl =

T211 TO

+

'12 11 TO

F2 =

T211 TO +

12 Tl 10

In the case of no product term selection all the outputs will
be in the inactive state (opposite to the levels specified in
the ACTIVELEVEL DATA for each output).

REALIZE:

When only one product term is selected, the outputs
assume the active levels specified by the SUMMING DATA
TRUTH TABLE entry for the selected product term. The
outputs not specified as active will assume the inactive state
(opposite state to that specified in the ACTIVE LEVEL
DATA).

Since T2 11 10 is common to both F 1 and F 2 , it may be
shared so that only three product terms, rather than four,
are required.

To determine the output status for a case of multiple
product term selection, first all of the product. terms
selected must be identified. Each output state can then be
determined by examining the SUMMING DATA for all of
the multi ply selected product terms.

To achieve a reduction in product terms, in
this case, Fl can be realized in its comple·
ment form using DeMorgan's Theorems. The
true form required a HIGH active level and 4
product, terms. The complement form' reo
quires a LOW active level and 3 product
terms;

If any of the product terms has an active level specified for
the output, the output will assume the active state as
specified by the' ACTIVE LEVEL DATA. If none of the
product terms have an active level specified for the output,
the outputs will assume the inactive state (opposite state to
that specified bY,the ACTIVE LEVEL DATA.
TESTING
. Some circuitry is built into the IM5200 for test purposes
only. On an unprogrammed part it allows for:
1. Testing the output in the LOW state
2. Sampling the switching delay time through a max·
imum delay path

ACTIVE LEVEL INVERSION
REALIZE:

Fl =12 Tl TO + 1211 10 + 1211 10 + 1211

F1 ·=12 11 10 + 1211 10 + 1211 10
EDIT FLEXIBILITY,
PRODUCT TERM DEACTIVATION
The true or the complement of any input may be
connected to the AN D gates by programming. However, if
both the true and the complement of any variable are
programmed in a product term, that product term willnever be selected since Ii' Ii = O. This feature may be used
to deactivate. permanently any previously programmed
product ter.m.
8·31

IM5200
ADDITION OF NEW INPUT VARIABLES
TO EXISTING PRODUCT TERMS

3_ Four outputs, FO, F 1, F2, and F3 corresponding to
pins 13, 14, 15, and 16, respectively, for the routing
of current into one of four sectors of the arrays_

In the AIM technology only the active inputs a~e pregrammed. Unprogrammed inputs are "don't care." Therefore, additional input variables can be added to the "old"
product terms at any time_ For example,
Old Product Term
1011 '4 (12,1 3 ,1 5 '"

4. Nine inputs, 14 , 15 , 16 , 17 , 18 , 110 , 111 , 112 , and 113
corresponding to pins 2, 3, 4, ~, 6, 8, 9,10, and 11,
respectively, to select a unique element within a
sector_

113 = don't care)

Adding input variable 12 (true or'complement) to the product term would yield:
New Product Term
,1011 12 '4 (13' 15 ••• 113 = don't care) ,
EXPANDING A SUM OF PRODUCT TERMS
BY ADDING NEW PRODUCT TERMS
New product terms may be added to the sum of product
terms at any output by programming the AI M element that
connects the product term AN D gate to the output thereby
enabling activation of the output when the product term is
activated. The product term may be one already used in
another output sum of product terms or it may be one that
has not previously been used.
CHANGING AN OUTPUT ACTIVE LEVEL
FROM LOW TO HIGH
Any outputs that are' active LOW can be changed to active .
HIGH by programming the corresponding AIM element in
the OUTPUT ACTIVE LEVEL ARRAY_

Inputs 11 and 12 , corresponding to pins 22 and 23, are used
to enable testing of propagation delay, programming
circuitry decoding and output low level characteristics
before programming.
Programming current pulses are forced into the output pin,
corresponding to a particular ,sector, and routed to the
element selected for programming. The elements are sensed
a~ a reduced current level after each programming pulse to
determine if programming has occurred.
After all necessary elements are programmed, the array is
reverified by scanning the array and resensing all elements
directly. Finally, a logical verification is conducted forcing
all 214 input states and checking the eight outputs for the
correct logic levels.
EFFECTS OF PROGRAMMING (P)
OR NOT PROGRAMMING (NP)
AN ElEMEN~ IN EACH OF THE
THREE ARRAYS

PROGRAMMING
Output Active Level Array

GENERAL
Recommended Programmer is DATA I/O model 10.

ALi

EFFECT ON AN Ol,lTPUT

NP

Output active level will be a LOW for all product
,
terms programmed to the output_

P

Output active level will be a HIGH for all product
terms programmed to the output.

Programming an IM5200 requires:
1. Two input pins, 10 and 19 corresponding to pins 21
and 7, respectively, to be. forced to a voltage above
normal TTL operating levels to establish the programming mode.
2. One input pin, 13 corresponding to pin '1, to be
switched between a high level and ground to select
between the Summing Array (OR Array) or the
Product Term Array (AND Array). respectively_'

OUTPUT PIN

SECTOR

LOCATION

. Product Term,Array
Ik

Ik

EFFECT ON A PRODUCT TERM

NP

NP

The logic state of the input cannot effect the
product term. It is a "don't care" input.

NP

P

Low input becomes an active variable in the
product term.
,

FO

13

1

0 -

Fl'

14

2

16 -

Product Terms;
AND/OR Arrays

P

NP

High input becomes an active variable in the
product term_

F2

15

3

32 - 47 Product Terms;
AND/OR Arrays

P

P

F3

16

4

Output Active Level Array

Disables th'e product term, preventing the
product term from ever activating any output.

15 Product Terms; .
AND/OR Arrays
31

8-32

IM5200
Summing Array
PT j
NP

FOR PROGRAMMING
DATA FORMATS
I
EFFECT ON AN OUTPUT

Output is isolated from the product term unless

pr~grammed. Therefore, activation of the pro-

Intersil Inc. can program the IM5200 from data inputs
consisting of a truth table, or paper tape. Format specifics
follow. If TWX data inputting is used, TWX 910-338-0171.
If mailing data input. mail to:

duct term can not affect the output.
P

INTERSIL, INCORPORATED
ATTEN: ORDER ENTRY
10710 N. Tantau Avenue
Cupertino, CA 95014

Activation of the product term will force the output to its active level.

FORMAT INFORMATION SUMMARY
HAND ENTRY 1N
TRUTH TABLE FORM

Heading
Information

Start of Data

Enter at top of the form
as.indicated

Not required

TWX-RCVDAS
HARD COpy OR
P~PER TAPE

Enter as per example

Enter as per example

preceding sta~ of
data (STX). The

preceding the start of
data (STXI. The

asterisk '*) cnar·
acter may not be
used in any heading
information

asterisk (.. ) character may not be
used in any heading
information

'STX (Control B)

STX (Control B)

Active Level Data Not required
Identifier

Active Level Data H::> High active level
Entry
L '" Low active level
Product Term
Number

PAPER
TAPE

"A

"A

H - High active level
L '" Low active level

H '" High active level
L '" Low active level

"P

"P

Not required

Identifier

Product Term
Number Entry

Pr~printed

Product Term
Input Data
Identifier

Not required

Product Term
Input Data
Entry

'" Active high input H '" Active high input H:: Active high input
'" Active low input L '" Active low input L:: Active low input
BLANK'" Don't care input - '" Don't care input - '" Don't care input

Summing Data
Identifier

Not required

Summing Data
Entry

A

Eild of Data

Not requrred

Deactivating a
Product Term

Enter 0 as any input
entry for a product term
to be deactivated

Enter 0 as any input Enter D as any input
entry for a product
entry for a product
term to be deactivated term to be deactivated

Spacing. Carriage
Returns. Li ne
Feeds

Not applicable

As needed to give an
easily readable
appearance in
teletype printed
form
See TWX description for recornmended format

Rubouts

'" Product term
is summed by
this output
BLANK'" Product term
is not summed
by this output

Not applicable

MSD - Decimal 04
LSD ;: Decimal O-g
"I

"F

MSD '" Decimal 0-4
LSD = Decimal O-g
"I

"F

A '" Product term is
summed by this
output
- == Product term is
not summed by
this output

A :: Product term is
summed by this
output
- :;: Product term is
not summed by
this output

ETX (Control C) ,

ETX (Control C)

May be used to
correct errors

Not required unless
examination by
printout on a teletype is desirable .
See Paper Tape
description for
recommended
format
May be used to
correct errors

TRUTH TABLES

assure th"at it will remain as a part of the purchase order
which is entered.

Truth tables can be submitted to Intersil Inc. by mail or by
TWX (91q-338-01711. A"truth table format for mailing is
presented as a part of this da"ta sheet. Additional copies of.
this format are available upon request. The customer should
complete all heading information on the format in order to

When entering a truth table by TWX, the following format
is recommended "so that the data is compatible with the
paper tape format. The TWX can, therEifore, be received in
punched paper tape form for direct processing by a
programmer equipped with a paper !ape reader input.
8·33

G]

IM5200
TWX FORMAT

,
. A HEN ORDER ENTRY

PO NUMBEh 7-706574
B ILL TO BRADY Ei.ECThONI CS INC
1074 SIXTH ST
SYhAGUSE NY 13206
SHIP TP BRADY ELECThONI CS INC
7 6LI EAST CAhL 10N
. SYMCUSE NY 13206

TELE.(315) 463':5870
TWX 910-377-6402
B UY Eh HANK HEN ON E

SHIP AIR EXPhESS
ITEM 01 PIN 706475- 00 1

TRUTH TAPLE f-/N

12 FCS

DEl. I VERY ASAP

7064,75-001

STARTOF DATA

r-

:s

10

III

c

, !

o

-55 -25

+125

.....,..

I

III
III

/'

C

III
II:

30

VCC=5V
TA=2So

20

A~DTd

V

U

./
len DELAY

lE

/vCC=5~_

III

:Ii

i=
>-

T1= 2~
/
I
,
/
V
I
1/ ADD TO ACCESS DELAY laa

L

10

:s
III

c

o

20 60 100 140 180 220 260.300

~

~

V

V
V

V
~

...-

~

ADD TO
.
ACCESS DELAY I••

20 60 100 140 180 220 260 300
LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

8-45

+75
+

125

m

iii

c

,/ADDTOIen ","DELAY
.
.

0 +25

TEMPERATURE (OC)

IM5623 DELAY
INCREASE WITH LOAD
CAPACITANCE

I

C

"VCC'; 4.5V-i-VCC = 5.0V :-V /~CC=5.5V

30
E '20

TEMPERATURE (0C)

(0C)

'40

III
III

-' --

.
40

~

~

Oldl~'l'

O.6k

10

iM56D3 DELAY
INCREASE WITH LOAD
CAPACITANCE

....s

':f}

10pFI

:Ii. 50

I-- ~

-55 -25

+125

....s

O.6k

VCC = 5.SV

o

70
60

0,31<

v~~

80

VCC=4.5~_

10

I I

o

60

:Ii

+125

IM5623 CHIP.ENABLE
TO OUTPUT DISABLE TIME
DELAY (1015) VS
TEMPERATURE

~-len'l'

:J)PF

+75

TEMPERATURE (OC)

90

III

III

VCC=5.5V

10

-55":'250 +25

+125

O.3k

70

= 4.5V
. VCC=5.0V_
VCC=5.5V

10

V~~

80

.~ •

~VCC

/ V

E 20

90

v

..-

~

30

IM5623 CHIP ENABLE TO
OUTPUT ACCESS DELAY
(lEN) VS TEMPERATURE

~pFfF~

60
50

...
III

IdlB

k·

~ Sk. !-3k·' .
-'

TEMPERATURE (OC)

IM5623 ADDRESS TO
OUTPUT ACCESS DELAY
(IAA) VS TI;:MPERATURE

90

+75

0 :25

10 PF,tdIS

50

III
C
III

••

~dlSl

60

:Ii

'i=

20~~~~~~
101+

TEMPERATURE (OC)

....s

.s

'0 U--.L_L..--'----'---'_.l.-....

-55 -25

0,31<

70

III

50~~r-=r~~rH~F--!---1

o

80

.

3 3k-f---If---!---1

~ 30 k/--I-+-:-lf--±:-'-'ii"--r--t

10

,

ten'"

:Ii

i=

90

80,V~~I

£-sl

3JPFien

s:~
w

VCC=4.SV
VCC= S.OV

VCC:=

80

IM5603 CHIP I;:NABLE TO
OUTPUT DISABLE TIME
DELAY (1015) its
TEMPERATURE

D~DIl

IM5603/IM5623
TYPICAL DC CHARACTERISTICS

,

<
.§.

IM5603 OUTPUT LOW CURRENT (loL)
VS OUTPUT LOW VOLTAGE (VoL)
50
40

a:
a:

35
30

:J
U

;::
0

...J

I-

:J
II.

I-

:J

0

'1-

z

w

a:
a:

·a
l:

o

o

w

II

a:
a:

:J
U

;::

L

III.

10

:J

5

o...J

/

o

100

200

Vee = 5V
.TA=25D e
300

400

30
25'
20
15

:J

/

50
45
40
,35

" I-

o

/

/
/

/

o

500

o

~

a

I-

:J

300

400

500

IM5623 OUTPUT HIGH CURRENT (IOH)
, VS OUTPUT HIGH VOLTAGE (VOH)

-0.5
-1.0
-1.5
'-2.0

Vee =4.5V
Vee = 5.0V
Vee = 5.5V r-.,X.

<
.§.

t---..I II
/'

//"'>
/'/ /'
/ //

V/ /
1'/

-20

l:

CL

-

•

-4.5

u

:J

:i:

TA=25D e
ENABLED AND_
ADDRESSING
A PROGRAMMED BIT

-4.0 r--

z
w
a:
.a:

0
-5
-10
-15

I-

I

i

I

2

3

4

I-

;-25
'-30

:J

-35'

I-

-40
-45

II.

:J

0

+0.2
0.0
Vee- 4.5V _

fit

:"1.2
-1.4
-1

o

1 '.

,+0.2
<
.§.
I-

zw

-0.2

:J

-0.6
-0.8

J

a: -0.4
a:

U
I-

:J
II.

~'

I
'2

5

.

0.0

·f
'~l

I

If

4

. IM5603 OR IM5623 ADDRESS INPUT
CURRENT lis INPUT VOL TAGE

~ 17
h "2< Vee = 5.0V
11/ " Vee=5.5V~

~ . -1.0

3

OUTPUT HIGH VOLTAGE (V)

~

-0:2
-0.4
-0.6
-0.8

2

0

5

IM5603 OR IM5623 CHIP ENABLE INPUT
, CURRENT VS INPUT VOLTAGE

in

200

IM5603 OUTPUT HIGH CURRENT (IOH)
VS OUTPUT HIGH VOLTAGE'(VOH)

,OUTPUT HIGH VOLTAGE (V)

<

100

OUTPUT LOW VOLTAGE (mV)

o

'~

Vee':'5V
TA= 25D e

;'

OUTPUT LOW VOLTAGE (mv)

-3.0
-3.5

:J

/

15
10
5

~
II.

Z

.20

...,2.5

:J

I-

25

!2,
I-

<
.§.

45

I-

z.
w

IM5623 OUTPUT LOW CURRENT (IOL)
VS OUTPUT LOW VOLTAGE (VoL)

,

-1

3

INPUT VOLTAGE (V)

!":- ~
11/ ,""""

Vee - 4.5V
Vee = 5.0VVee = 5.5V-

0)

2

,

-1.0
-1.2

/J
~ "1/

I

INPUT VOLtAGE (V)

8·46

3

IM5603/IM5623
OUTPUT STAGE SCHEMATICS
IM5623

IM5603

loon

1.3k
8 INPUT
I\IIUL TIPLEXER

8 INPUT
MULTIPLEXER
+--~---.--c' OUTPUT

OUTPUT

lk

=

=

8·47

IM5604/IM5624
. 2048 Bit B.ipolar
Programmable Read
·Only Memory
FEATURES

GENERAL DESCRIPTION
The Intersil IM5604 and IM5624 are high speed, electrically
programmable, fully decoded, bipolar 2048 bit read only
memories organized as 512 wo·rds by 4 bits. On-chip address
decoding, chip enable inputs and uncomitted collector or
three~state outputs proviae for simplified memory expansio_n
and use in bus organized systems.
.
Unprogrammed AIM elements are sensed as ZERO's or low.
logic levels at the outputs. Programming with a commercially
available programmer irreversibly converts selected elements
in the array so that they are sensed as ONE's or high logic
. levels.
The following companies make programmers approved by
Intersil:
'
1. Data I/O Corp., P.O. Box 1603, Bellevue, Wash. 98009
2. PRO-LOG Corp., 2411 Garden Rd., Monterey, CA 93940

• US!!S Pa,ented AIM Programming Element for
- Superior Reliability
.
- High Programming Yield.
- Fast.

LIMIT
LEVEL TESTED

MIN

MAX

FORCING CONDITION

VOL

-

IOL = 20mA ± 1mA

Zero

VOH

4.5

.85
-

IOL = WOIlA ± 10llA

One

PARAMETER

PROGRAMMING CYCLE TIMING DIAGRAM
. PROGRAM
PULSE

D .

I

!

ISENSE STROBES 1 '

I

I
I
ADDRESS CHANGE

I

I

20 mA ENABLE

r--

n

180 mA
I 100 mS TIME-OUT TRIGGER

!--

ENABLE

100 mS TIME-OUT RESET

..

60/,S IF PROGRAMMING OCCURS ON THE FIRST PULSE
60/,S + 10(N-1j" IF N PULSES ARE REQUIRED BEFORE
PROGRAMMING IS l>ENSED .
IF PROGRAMMING IS NOT ACHIEVED WITHIN 100mS THE SEQUENCE
HALTS AND A FAILED TO PROGRAM INDICATION IS GIVEN

A - 20mA CURRENT SOURCE TURNED ON (VOLTAGE
OVERSHOOT MAY OCCUR)
B - VOLTAGE LEVEL IS SENSED AND COMPARED
C - 180mA CURRENT SOURCE IS TURNED ON (180 + 20 = 200mA)
D - VOLTAGE FALLS INDICATING PROGRAMMING

. 8·54

E
F
G
H
I

•

- 180mA CURRENT SOURCE IS TURNED OFF
c VOLTAGE LEVEL IS SENSED AND COMPARED
- 180mA CURRENT SOURCED IS TURNED ON
- 20mA CURRENT SOURCE IS TURNED OFF
- ADDRESS IS CHANGED

IM6100 CMOS 12 Bit
Microprocessor

FEATURES

GENERAL DESCRIPTION

• Silicon Gate Complementary MOS
• Fully Static - 0 to 5.7 MHz
'. Single Power Supply
IM6100 Vcc = 5 volts
IM6100A Vcc = 10 volts
• Crystal Controlled On Chip Timing
• PDP®-8/e, Instruction Set Compatible
• Lov{Power Dissipation
,< 10mW@ 3.3'MHz @ 5 volts
• TTL Compatible at 5 volts
• Excellent Noise Immunity
• Direct Memory Access (DMA)
• Interrupt

®

PDp·S is a registered trademark of Digital Electronics Corp.

The IM6100 is a fixed word length, single word instruction,
parallel transfer microprocessor using 12-bit, two's complement arithmetic which recognizes the instruction set of
Digital Equipment Corporation's PDP-8/e minicomputer,
The internal circuitry is completely static and designed to
operate at any speed between DC and the maximum
operating frequency. Two pins are available to allow for an
external crystal, thereby eliminating the need for clock
generators and level translators. The crystal can be removed
and the processor clocked by an external clock generator,
The device design is optimized to minimize the number of
external components required for interfacing with standard
memory and peripheral devices,
.
The IM6100 family includes IM6101 (Programmable Inter~
-facing Element), IM6102 (Memory ExtensioniDMA Controller/Interval Timer), IM6103 (Parallel Input-Output Port),
IM6512 (64 x 12 RAM), IM6312 (1k x 12 ROM), and IM6402/03
(UART), all featuring ultra low power-high noise immunity
CMOS characteristics. The entire family is supported by the
.6910 Intercept II Microcomputer Development System.

PIN CONFIGURATION (outline dwg DL,.PL)
Vee

DATAF

RUN

INTGNT

DMAGNT

CPSEL

DMAREO

MEMSEL '
IFETCH

CPREO

SKP

RUN/HLT

C2
CT

RESET
INTREO

co

XTA

i'i'ESE'f

rM.~~ITt--~¥-~~

SWSEL

LXMAR

DEVSEL

WAIT

osc

BLOCK DIAGRAM

XTB

LINK

XTC

DX11
DX10

OUT

OSCIN

INTREQ

OSC IN
OSC OUT

GND

DXO

DX9

DX1

Dxe

DX2

DX7

DX3

DX6

DX4

DX5

XTA,XTB. XTC
OMAGNT. RUN

INTGNT.OATAF
IFETCH

Figure 1: Functional Block Diagram

ORDERING INFORMATION
ORDER CODE'

PLASTIC PKG,
CERAMIC PKG,
MILITARY TEMP,
MILITARY TEMP,
WITH 8838

IM61 00-1

IM6100A

IM6100

IM6100-11PL IM610D-AIPL
IM610D-IPL
IM6100-11DL IM61OD-AIDL
IM6100-IDL
IM6100-1MDL IM6100-AMDL IM6100-IDL
IM6100-1~DL/ IM6100-AMDU
8838

883B

8·55

O~OIb

IM6100
. IM6100 '
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6100 .................... -45°C to +85°C
Storage Temperature ................. -65°C to +150°C
Operating VOlt9ge ..................... +4.0V to +11.0V
Supply Voltage ................................ +12.0V
Voltage On Any Input or
Output Pin ....................... -D.3V to Vee +O.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for.
'extended periods may cause device failures,

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee
SYMBOL

= 5.0V ±10%, TA = -40°C to +85°C

1

VIH

PARAMETER
Input Voltage High

2

VIL

Input Voltage Low

3
4

Input Leakage

5

IlL'
VOH
VOL

6
7

IOlK
' Icc

8

Icc

9

CIN
Co

10

Output Voltage High
Output Voltage Low

CONDITIONS

MIN
Vee-2.0

GND:5 VIN < Vee
10H =-D.2mA

-1.0

Power Supply Current-Standby
Power Supply Current-Dynamic

pF

Figure 2 and 22)

= 5.0V ±10%, CL = 50pF, TA -40°C to t85°C, Ie = 2.5MHz

3

Ilxmar
tas
tah
lend

Address Setup Time: DX-LXMAR I~)
Address Hold Time: LXMAR I~)-DX .

PARAMETER

MIN

Data Output Enable Time: DEVSEL

TYP

MAX

UNITS

2.5

MHz
ns

800

LXMAR Pulse Widlh
"-

335

ns

120

ns
575

ns
. ns

175

I~)-DX

lal
ten
Iwp

Access Time from LXMAR

650

ns

Output Enable Time IMEM, CP, DEVSEU

400

ns

Pulse Widlh IMEMSEL, CPSEU

320

ns

Iwpd

Pulse Width IDEVSEU
Data Setup Time IDX- t MEMSEL/CPSEU
Data Hold Time It MEMSEL/CPSEL-DX)

320
240
175

ns
ns

Data Setup Time IDX-t DEVSEU

275

·ns

Data Hold Time It DEVSEL-DXI

175

tds
tdh
Idsd
tdhd
tsl

ns

Logic Delay 10 MEM/DEV/CP/SWSEL

75

440

ns
ns

Logic Delay 10 LX MAR, XT A, XTB, XTC

65

380
475

ns
ns

19

txt
1st
Irs
Irh

20

Irhp

21

Iws

22

twh

Hold Time for Wait

18

mA
pF

Major State Time

16

~A

1.8

/-lA

10.0

ts

17,

V.

1.0
800

8.0

2

14
15

0.45
-1.0

.Output Capacitance

Operating Frequency

11
12
13

/-lA
V

8.0

SYMBOL
fop

9
10

V

1.0

. 7.0

1

6
7

0.8
2.4

GND $. VOUT $. Vee
VIN - GND or Vee
fe = 2.5MHz

UNITS
V

Input Capacitance

A.C. CHARACTERISTICS' ISee

5
8

MAX

10L = 2.0mA

Output Leakage

TEST CONDITIONS: Vee

4

TYP

Logic Delay to DATAF,RUN, DMAGNT, INTGNT, LINK, IFETCH
Set up Time for CP/INT/DMAREQ

0

ns
ns

RUN-HALT Pulse Width

300
110

Set up Time for Wait

100

ns

35

ns

Hold Time for CP/INT/DMAREQ, RESET, RUN-HALT

Note: For capacitance greatf than 50pF, the AC paramete . will have a delay factor of 0.5ns/pF.

8·56

ns

O~OIb

IM6100
IM6100A
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Industrial IM6100AI ................. '. -40° C to +85° C
Storage Temperature .... :........... -65° C tei +150° C
Operating Voltage ..................... +4.0V to +11.0V
Sup'ply Voltage ................................ +12.0V
Voltage On Any Input or
Output Pin ....................... --{).3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to ,absolute maximum rating conditions for
,extended periods may cause device failures.

D.C. CHARACTERISTICS.
TEST CONDITIONS: Vee
SYMBOL
1
2
3
4
5
6
7
8
9
10

VIH
VIL
ilL
VOH
. VOL
IOlK
Icc

Icc
CIN
Co

= 10V ±5%, TA = -40°C to +85°C

PARAMETER
Input Voltage High
Input Voltage Low
Input Leakage
Output Voltage High
Output Voltage Low
Output Leakage
Power Supply Current-Standby'
Power Supply Current-Dynamic
Input Capacitance
Output Capacitance

'CONDITIONS

MIN
70% Vee

GND :s VIN :s Vee
IOH - O.OmA
IOL = O.OmA
GND:S VOUT :s Vee
VIN = GND or Vee
fe =5.71MHz

-1.0

TYP

MAX
20% Vee
1.0

Vee -0.01
GND +0.01
1.0
900
4.0
8.0
10.0

-1.0

.
7.0
8.0

UNITS
V
V
!J.A
V
V
!J.A
!J.A
mA
pF
pF

A.C. CHARACTERISTICS (Ref: Figures 2 and g6)
= 10V ±5%, CL = 50pF, TA = -40°C t9 +85°C, Ie = 5.71MHz

TEST COND'ITIONS: Vee

1
2
3
4
5
8
6
7
9
10·
11
12
13
14
15
16
17
18
19
20
21
22

SYMBOL
fop
ts
tlxmar
tas
tah
tend
tal
ten
twp
twpd
tds
tdh
tdsd
tdhd
tsl
txt
tst
trs
trh
trhp
tws
twh

PARAMETER
Operating Frequency
Major State Time
LXMAR Pulse Width
Address Setup Time: OX-LX MAR (+1
Address Hold Time: LXMAR UI-DX
Data Output Enable Time: DEVSEL (+I-DX
Access Time from LXMAR
Output Enable Time (MEM, CP, DEVSELI
Pulse Width (MEMSEL, CPSELI
Pulse Width IDEVSELI
,
Data Setup Time (DX- t MEMSEL/CPSELI
Data Hold Time ( t MEMSELlCPSEL-DXI
Data Setup Time (DX- t DEVSELI
Data Hold Time ( t DEVSEL-DXI
Logic Delay to MEM/DEV/CP/SWSEL
Logic Delay to LXMAR, XTA, XTB, XTC
Logic Delay to DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH
Set up Time for CP/INT/DMAREO .
Hold Time for CP/INT/DMAREO, RESET, RUN-HALT
RUN-HALT Pulse Width
Set up Time for Wait
Hold Time for Wait

MIN

MAX
5.71

350
150
55
60
250
295
185
140
140
1.15
60
110
60
35
35

180
155
190

0
125
45
45
15

Note: For capacitance greater than 50pF, the AC parameters will have a delay factor of 0.5ns/pF.

8·57

TYP

UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

IM6100
IM6100~M

(Military)

ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6100AM ............... -55°C to +125°C
Storage Temperature ................ --B5° C to +150° C
Operating Voltage ......... ~'.; ......... +4.0V to +11.0V
Supply Voltage ........ ': .... ................... +12.0V
Voltage On Any Input or
Output Pin ....................... --{).3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of thedevices at
these or any other conditions above those indicated in the
operation sedions of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

D.C. CHARACTERISTICS.
TEST CONDITIONS: Vee ~ 10V ±5%, TA = -55°C to +125°C
SYMBOL

1
2
3
4
5
6
7
8
9
10

VIH
VIL
IlL
VOH
VOL
IOlK
Icc
Icc
CIN
Co

PARAMETER
Input Voltage High
Input Voltage Low'
Input Leakage
Output Voltage High
Output Voltage Low
Output Leakage
Power Supply Current-Standby
Power Supply Current-Dynamic
Input Capacitance
Output Capacitance

A.C. CHARACTERISTICS

IRef.: Figures 2and 221

TEST CONDITIONS: Vee = 10V

± 5%,

1
2
3
4
5
8
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SYMBOL
. lop

ts
t'xmar
las
lah
lend
lal
len
Iwp
twpd
Ids
Idh
Idsd
Idhd
lsi
txt
1st
Irs
trh
Irhp
Iws
Iwh

CONDITIONS

MIN

. TYP

MAX

70% Vee
GND :5 VIN < Vee
10H =O.OmA
10L = O.OmA
GND :5 VOUT :5 Vee
VIN = GND or Vee
fe = 5.0MHz

20% Vee
1.0

-1.0
Vee -{).01

GND +0.01
1.0
900
4.0
8.0
10.0

-1.0

7.0
8.0

UNITS
V

V
/lA
V
V
/lA
u.A
mA
pF
pF

Cl = 50pF, TA = -55°C to +125°C, .Ie = 5.0MHz
PARAMETER

MIN

Operating Frequency

TYP

MAX

UNITS

5.0

MHz
ns
ns
ns
ns
ns
ns

400
170
70
70

Major State Time
. LXMAR Pulse Width
Addtess Setup Time: DX-LMAR Ul
Address Hold Time: LXMAR I~l-DX
Data Output Enable Time: DEVSEL I*l-DX
Access Time from LXMAR
Oulput Enable Time IMEM, CP, DEVSELl
Pulse Width IMEMSEL, CPSELl
Pulse Width IDEVSELl
Data Setup Time IDX- , MEMSEL/CPSELl

290
340 '
220
160
160
140
70
140

Data Hold Time I' MEMSELlCPSEL-DXI
Data Setup Time IDX-' DEVSELl
Data Hold Time I , DEVSEL-DXI
Logic Delay to MEM/DEV/CP/SWSEL \
Logic Delay to LXMAR, XTA, XTB, XTC
Logic Delay to DATAF, RUN, DMAGNT, INTGNT,' LINK, IFETCH
Set up Time for CP/INT/DMAREQ
Hold Time for CP/INTIDMAREQ, RESET, RUN-HALT
RUN-HALT Pulse Width
Set up Time for Wait
Hold Time for Wait

70
35
·35

Note: For capacitance 0' greater than ?OpF, the AC parameters will have a delay factor of O.5ns/pF,

8-58

ns
ns
. ns
210
170
210

0
140
50
50
20

ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

O~OI!"

IM6100
IM6100-1
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6100-11 ..... ,............. -40°C to +85°G
Storage Temperature ................ --65°C to -t.150°C
Operating Voltage ..................... +4.0V to +11.0V
Supply· Voltage ................................ +12.0V
Voltage On Any Input or
Output Pin ....................... --().3V to Vee_+0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functiomll operation olthe devices at
these or any other conditions above those indicated in the
'operation sections of this specification is not, implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.
.'

D.C. CHARACTERISTICS
TEST-CONDITIONS: Vee = 5.0V ±10%, TA = -40°C to +85°C
SYMBOL
1·
2
3
4
5

VIH
VIL

ill
VOH
VOL
IOlK
Icc
Icc
CIN
Co

6
7
8

9
10

PARAMETER
Input Voltage High
Input Voltage Low
Input Leakage
Output Voltage High
Output Voltage Low
Output Leakage
Power Supply Current-Standby
Power Supply Current-Dynamic
Input Capacitance
Output Capacitance

A.C. CHARACTERISTICS

CONDITIONS

MIN
Vee -2.0

GND S VIN :;; Vee

-1.0

10H - -o.2mA
10L 2.0mA .

2.4

GND < VOUT < Vee
VIN GND or Vee
fe 3.33MHz

-1.0

TYP

MAX

UNITS
V
V
",A

O.B
1.0

"1/,

=

0.45
1.0
800
2.0
B.O
10.0

=
=

7.0
B.O

V
",A
",A
mA
pF
pF

IRef. Fig. 2 and 22)

TEST CONDITIONS: Vee = 5.0V ± 10%, Cl = 50pF, TA = -40°C to +B5°C, fe =3.33MHz

1
2
3
4
5
8
6
7

9

SYMBOL
fop
ts
tl xmar
las
tah
tend
·tal
ten
t wp '

10
11
12
13
14
15
16

twpd
tds
tdh

17.

1st

1B
19
20
21
22

Irs
Irh
lrhp
Iws

Idsd
Idhd
lsi
Ixt

twh"

MIN

PARAMETER
Operating Frequency
Major State Time
LXMAR Pulse Width
Address Setup Time: DX-LXMAR I~)
Address Hold Time: LXMAR I~)-DX
Data O\Jtput Enable Time: DEVSEL I~)-DX
Access Time from LXMAR

MAX
3.33

600
260
B5
125
470
520
300

Output Enable Tilne IMEM, CP, DEVSEU
Pulse Width IMEMSEL, CPSEU

235

Pulse Width IDEVSEU
Data Setup Time IDX-t MEMSEUCPSEU '
Data Hold Time It MEMSEUCPSEL-DX)
Data Setup Time IDX-t DEVSEU
Data Hold Tim'e It DEVSEL-DXI
Logic Delay to MEM/DEV/CP/SWSEL
Logic.Delay 10 LXMAR, XTA, xi's, XTC
'Logic Delay to DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH
. Set up Time for CP/INT/DMAREO
Hold Time forCP/INT/DMAREO, RESET, RUN-HALT
RUN-HALT Pulse Width
Set up Time for Wait
Hold Time fo'r Wait

235
135
125
225
1'25
75·
65

a
200
BO
100
20

Note: For capacitance greater than 50pF, the AC parameters will have

TYP

a delay factor of 0.5ns/pF.

8-59

3BO
270
340

-

UNITS
MHz
ns
ns
ns
ns
ns
ns
·ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

O~OIL

IM61 00
IM61 00-1 M (Military)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6100-1M ... : ........... -55°C to +125°C
Storage Temperature ................ --65° C to +150° C
Operating Voltage " ... " . " ..... " " .. +4.0V to +11.0V
Supply Voltage . " " ... " . " , , •...• ,,' .... , ... " +12.0V
Voltage On Any Input or
Output Pin .............. , ........ -o.3V to Vee +0.3V

NOTE: Stresses above those listed under· "Absolute Maximum
Ratings" may cause permanent device' failure. These are
.stress ratings only and functional operation of the devices at
'these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
. extended periods may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5V
SYMBOL
1
2
3
4
5
6
7
8
'9

VIH
Vil
ill
VOH
VOL
IOlK
lec
lec
CIN
Co

10

± 10%, TA =

-55°C to +125°C

PARAMETER
Input Voltage High
Input Voltage Low
Input LeakaQe
Output Voltage High
Output Voltage Low
Output Leakage
Power.Supply Current-Stan'dby
Power Supply Current-Dynamic
Input Capacitance
Output Capacitance

A.C. CHARACTERISTICS

(Ref. Fig. 2 and 221

± 10%, CL =

05
8
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SYMBOL
fop
Is
tl xmar
tas
tah
lend
lal
len
Iwp.
·twpd
tds
tdh
tdsd
Idhd
tsl
txt
tst
trs
trh
Irhp
tiNS
twh

o~

MIN
Vee -2.0

GND < VIN < Vee
10H =-Q.2mA
IOl 2.0mA
GND < Your < Vee
VIN = GND or Vee
.fe 2.5MHz

-1 ..0
2.4

TYP

MAX
0.8
1.0

=

TEST CONDITIONS: Vee = 5.0V

1
2
3
4

CONDITIONS

0.45
1.0
800
2.0
8.0
10.0

-1.0

=

7.0
8.0

UNITS
V
V
JJ.A
V
V
f).A
~A

mA
pF

of

50pF, TA = -55°C to +125°C, Ie = 2.5MHz

PARAMETER
Operati.ng Frequency
Major State Time
LXMAR Pulse W.idth
Address Setup Time: DX-LXMAR (II
Address Hold Time: LXMAR (II-OX
Data Output Enable Time: DEVSEL (II-OX
Access Time from LXMAR
Output Enable Time (MEM, CPo DEVSELI
Pulse Width (MEMSEL, CPSELI
Pulse Width (DEVSELI
Data Setup Time (DX- +MEMSEL/CPSELI
Data Hold Time ( +MEMSEL/CPSEL-DXI
Data Setup Time (DX- + DEVSELI
Data Hold Time ( +DEVSEL-DXI
LOQic Delay to MEM/DEV/CP/SWSEL
Logic Delay to LXMAR, XTA, XTB, XTC
Logic Delay to DATAF, RUN, DMAGNT, INTGNT, LINK, IFETCH
Set up Time for CPIINT/DMAREO
Hold Time for CPIINT/DMAREO, RESET, RUN-HALT
RUN-HALT Pulse Width
Set up Time for Wait
Hold Time for Wait

MIN

MAX
2.5

800
355
200
175
655
745
470
330
330
250
170
350
170
75
65

UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

420
300
375

0
220
90
110
20

Note: For capacitance of greater than 50pF, the AC parameters all have delay' factor of 0.5ns/pF.
8·60

TYP

ns
ns
ns
ns
ns
ns
ns
ns

O~OIb

IM61 00
GNO

+5V

r----~==~::1===r=====~~~~~~~~===t112~---MULTIPLEXER

OXo - OX11

--..,

I

I

LlNK:----:--t--~~~~J

--~

-- -.-:i r-±--l

~:::~-----i ~
!--orI

I

I

t

------l

os~sg~~----~-+--,

I
I

,------t....fPLA OUTPUT LATCHi--.J
I
i
I

XTA, XTB, XTC

I~T~~~~bA~~~~--~-1-1
IFETCH

...._...,._ _...
LXMAR
OEVSEL
SWSEL
MEMSEL
CPSEL

WAIT------~----~

Figure 1: Functional Block Diagram

FUNCTIONAL PIN DESCRIPTIONS
PIN
1
2

SYMBOL
Vee
RUN

3

DMAGNT

4

DMAREQ

5

CPREQ

6

RUf'J/HLT

'7
8
9
10
11

RESET
INTREQ
XTA
LXMAR
WAIT

12

XTB

13

XTC

14

OSC OUT

15

OSCIN

16

DXo

17

DX1

DESCRIPTION
Supply voltage.
The signal indicates the runstate of the CPU
and may be used to power down the external
circuitry
Direct Memory Access Gr'!nt-DX lines are
th r.ee-state.
Direct Memory Access Request-DMA is
granted at the end of the current instruction.
Upon DMA grant, the CPU suspends
program execution until the DMAREQ line is
released.
Control Panel Request-a dedicated interrupt which bypasses the normal device interrupt request structure.
Pulsing the Aun/Halt line causes the CPU to
alternately run and halt by changing the state
of the internal RUN/HL T flip flop.
Clears the AC and loads 77778 into the PC.
CPU is halted.
Peripheral device interrupt request.
External coded minor cycle timing-signifies
input transfers to the IM6100.
The Load External Memory Address
Register is used to store memory and
peripheral addresses externally.
Indicates that peripherals or external
memory is not ready to transfer data. The
CPU state gets extended as long as WAIT.is
active. The CPU is in the lowest power state
with clocks running.
External coded minor cycle timing-signifies
output transfers from the IM6100.
External coded minor cycle timing-used in
conjunction with the Select Lines to specify
read or write operations.
Crystal input to generate the internal timing
(also external clock input),
See Pin 14-0SC OUT (also external clock
ground)
DataX-multiplexed data in, data out and
address lines.
See Pin 16-DXo.

8-61

PIN

SYMBOL

18
19
20
21
22
23
24
25
26
27
28
29
30
31

DX2
DX3
DX4
DX5
DX6
DX7
DX8
DXg
GND
DXlO
DX11
LINK
DEVSEL
SWSEL

32

Co

33
34
35

Cl

36
37
38

IFETCH
MEMSEL'
CPSEL

39
40

INTGNT
DATAF

C2
SKP

DESCRIPTION
See Pin 16-DXo..
See Pin 16-DXo.
See Pin 16-DXo.
See Pin 16-DXo.
See Pin 16-DXo.
See Pin 16-DXo.
See Pin 16-DXo.
See Pin 16-DXo.
Ground
See Pin 16-,DXo.
See Pin 16-DXo.
Indicates state of link flip flop.
Device Select for 1/0 transfers.
Switch Register Select for the OR THE
SWITCH REGISTER INSTRUCTION (OSR).
OSR is a Group 2 Operate Instruction which
reads a 12 bit external switch register and
OR's it with the contents of the AC.
Control line inputs from the peripheral
device during an 1/0 transfer (Table VI),
See Pin 32-CO.
See Pin 32-CO.
Skips the next sequential instruction if active
during an 1/0 instruction.
Instruction Fetch Cycle
Memory Select for memory transfers.
The Control Panel Memory Select becomes
. active, instead of the MEMSEL, for control
panel routines. Signal may be used to
distinguish between control panel and main
memories.
Peripheral device Interrupt Grant.
Data Field pin indicates the execute phase of
indirectly addressed AND, TAD, ISZ and
DCA instructions so that the data, transfers
are controlled by the Data Field, DF, and not
the Instruction Field, IF, if Extended Memory
Control hardware is used to extend the
addressing space from 4K to 32K words.

O~OIL

IM61 00
MEMORY ORGANIZATION

PAGE 378
PAGE 36
PAGE 358

FIELD 7

<

FIELD 6
FIELD 5

The IM6100 has a basic addressing capacity of 4096 12-bit
words which may be extended by Extended Memory Control
hardware to 32K. The memory system is organized in 4096
word blocks, called MEMORY FIELDS. The first 4096 words
of memory are in Field 0; if a full32K of memory is installed,
. the uppermost Memory Field will be numbered 7. In any
given Memory Field every location has a unique 4 digit octal
(12 bit binary) address,bOOOa to 7777a (000010 to 409510).
Each Memory Field is subdivided into 32 PAGES of 128
words each. Memory Pages are numbered sequentially from
Page OOa, containing addresses 0000-0177a, to Page 37a,
containing addresses 7600a-7777a. The first 5 bits of a 12-bit
MEMORY ADDRESS denote the PAGE NUMBER and the
low order 7 bits specify the PAGE ADDRESS of the memory
location within the given Page.

PAGE 0
PAGEOh
PAGE 068
PAGE 058
PA E 048

FIELD 4

r+

. FIELD 3
FIELD 2

I

FIELD 0

LaC 1778
LaC 1768
LaC 1758'

>

>LaC 0108 >
r+

PAGE 03a

FIELD 1

PAGE 028
PAGE 018
PAGE 008

I}-

32K MEMORY
(108 FIELDS) '-

777..18

}-

01778

1 MEMORY FIELD 0000,
(408 PAGES)

LaC 0078
LaC 0068
LaC 0058
LaC. 0048
LOC 0038'
LaC 0028
LaC 0018
LaC 0008
1 MEMORY PAGE
(2008 LOCATIONS)

MEMORY ADDRESS
12-BIT OCTAL MEMORY !, of the EA are logically ANO'cd with tho contents of tho AC and the result is stored in AC

AND I PA

1

15

LOGICAL AND INDIRECT IPA '" 0010-00178)

AND PAIX

1

16

0

10

LOGICAL AND AUTOINDEX IPAIX
o erallon" IPA)~PA) + 1: IAC1-IAC, A !lPAII
BINARY ADD DIRECT

TAD EA

18

TAD I PA
TAD I PAIX
ISZ EA

28

Operation: (AC)-IACI" ([PAil

'

= 0010-00178)

OpHation IACI~AC) + lEA)
Dcscrlphon: Contents of the EA are ADO'ed with ttle contents of the AC and the result IS stored
complements the LINK. If AC is initially cleared. this Instruction acts as LOAD trom Memory

_1

15

BINARY ADD INDIRECT IPA '" 0010-0017a)

1

16

0-

16

BINARY ADD AUTOINDEX IPAIX = 0010-00178)
Operation IPAI_IPA) + 1. lAC) ---1ACI + UPAI.I
INCREMENT AND SKIP IF ZERO DIRECT

In

ttle AG. carry out

Operation lAG) -tAC) + IIPAll

Operation: IEAI-tEA1+l, if1EAI =00005, PC-PC+l
Description; Contents of the EA are incremented by , and restored. If the r2sult is
skipped.

zero. the next sequential

instruction is

ISZ I PA

1

21

INCREMENT AND SKIP IF ZERO INDIRECT IPA '" 0010-0017a)

ISZ I PAIX

1

22

0

11

INCREMENT AND SKIP IF ZERO AUTOINDEX IPAIX = 0010-00178)
Operation ',PA)~PAI +1· (IPA)) -, ~l. Skip
microinstructions which have a 0 in'bits 5; 6, 7, or 8 may not
be microprogrilmmed with skip microihstructions which
have a 1 in those same bits.
.

6

7

10

11

LOGICAL SEQUENCES:
1 (BIT 8 IS ZERO)-SMA OR SZA OR SNL
(BIT 8 IS ONE) -SPA AND SNA AND SZL
2
-CLA
'3
.,....OSR, HLT

Figure 6: Group 2 Microinstruction Format·

Ta~le

IV: Group 2 Operate Microinstructions

NU~BER

OCTAL
CODE

LOGICAL
SEQUENCE

OF
STATES

7400
7402

1
3.

10
10

7404

·3

15

7410
7420

1
1

10
10

SZL

7430

1

10

SKIP ON ZERO LINK-The content of Lissampled, ;he~extsequentlal :nstruction is skipped If Lcontalnsa
O. If the L contain's a 1, the next instruction is executed,
"
,I

SZA

7440

1

10

SKI P ON ZERO ACCUMULATO R-The content of theAC issampled; thenextsequential instruction is
skipped if the AC has all bits which are 0, If any bit in the AC is a 1. the next instruction is executed.
'

SNA

7450

1

10

SZA SNL
SNA SZL
SMA

7460
7470
7500

1
1
1

10
10
10

SPA

7510

1

10

SMASNL
SPA SZL
SMA SZA

7520
7530
7540

1
1
1

10
10
10

SPASNA

7550

1

10

SMASZA
SNL'
SPASNA
SZL
CLA
LAS

7560

MNEMONIC
NOP
HLT
OSR
. SKP
SNL

'.

.

SZA CLA
SNA CLA
SMACLA
SPA CLA

1

10

7570

1

10

7600
7604

2
1,3

10
15'

7640
7650

1,2
1,2
1,2
12

10
10
10
10

7700

7710

/

OPERATION
NO OPERATION-see Group' MICROINSTRUCTIONS

-

~ferL~:;~~~~r~~ sig~sp~~,~J ;~~~~~~o;eO~Jh:f~~~r~~~~~chlne cycle. If HLT is, combined with others in OPR 2, the
OR WITH" SWITCH REG ISTER-The content of the Switch Register if OR'ed with the content of the AC
and the result is stored In the AC. The OSR INSTRUCTION TIMING is shown in Figure 7. The IM6100 sequences the
OSA instruction through a 2-cycle execute phase referred to as CPR 2A and CPR 2B .
SKIP-The'conlent of the PC is incremented by 1, to skip the next sequential instructi'on .

SKIP ON NON-ZERO LINK-The content of L is sampled, the next sequential instruction is skipped if L
contains a 1, If L contains a O. the next instruction is executed.
' ,

SKIP ON NON-ZERO ACCUMULATOR-The conten' of the AC Is sampled; the next sequenUal

instructIOn IS skipped if the AC has any bits which are not O. If every bit in the AC is 0, the next instruction is executed,

SKIP ON ZERO ACCUMULATOR, OR SKIP ON NON-ZERO LINK, CiA. BOTH
SKIP ON NON-ZERO ACCUMULATOR AND SKIP ON ZERO LINK
SKIP ON'MINUS ACCUMULATOR--'-If 'he'con'ent of AC 10J contaIns a '. IndlcaUn~ thai the AC

contains a negative two's complement number, the next sequential instruction isskipped.lfAC(OI contalns.aO, the next
Instruction Is executed.

SKIP ON POSITIVE ACCUMULATOR'-The con'enlS of AC 10J are sampled. If AC 10J conlalns aO.

indicating that the AC contains a poSitiVe IWO'scomplement number, thenextsequential instruction is skipped. If AC(Ol
contains a I, the next instruction is executed,
'
\.

SKIP ON MINUS ACCl:JMULATOR OR SKIP ON NON-ZERO LINK OR BOTH
SKIP ON POSITIVE ACCUMULATOR AND SKIP ON ZERO LINK
SKIP ON MINUS ACCUMULATOR OR SKIP ON ZERO ACCUMULATOR OR
BOTH
SKIP ON POSITIVE ACCUMULATOR AND SKIP ON NON-ZERO
ACCUMULATOR
.
SKIP
MINUS'ACCUMULATOR OR SKIP ON ZERO ACCUMULATOR OR
SKIP ON NbN-ZERO LINK OR AL~
SKIP ON POSITIVE ACCUMULATOR AND SKIP ON NON-ZERO
. ACCUMULATOR AND SKIP oN ZERO LINK
CLEAR ACCUMUtATOR,-The AC Is loaded with bInary O·s.
LOAD ACCUMULATOR WITH SWITCH REGISTER-Thecon'en'oftheAClsloadedwlththe

em

content of the SA, bit for bit. This is equivalent to a microprogrammed combination 01 CLA and OSR.

SKIP
SKIP
SKIP
SKIP

ON
ON
ON
ON

ZERO ACCUMULATOR THEN CLEAR ACCUMULATOR
NON-ZERO ACCUMULATOR THEN CLEAR ACCUMULATOR
MINUS ACCUMULATOR THEN CLEAR ACCUMULATOR
POSITIVE ACCUMULATOR THEN CLEAR ACCUMULATOR

8-67

IM6100

O~OIL.

INSTRUCTION SET (CONTINUED)
STATES

I

I

I
LXMAR

I

~
I

:I

I

I

~
I .
I

II

..

I

I

I

I

IL-J

i

. i··

. I

I

. J

Dxloo~~
o ®
0
o

INSTRUCTION ADDRESS

® INSTRUCTION- CPU 0

SWITCH REGISTER,- CPU DATA

Figure 7: OSR Instruction Timing

GROUP 3 MICROINSTRUCTIONS
tion.lf more than one of the bits is set, the instruction is a
microprogrammed combination of group 3 microinstructions following the logical sequence listed in Figure 8. All
unused bits are "don't care".

Figure 8 shows the instruction forrhat of group 3 microinstructions which requires bits 3 and 11 to contain a 1. Bits 4, 5
or 7 may beset to indicate a specific group 3 microinstruc-

10
:

1

I

1

: CLA,: MilA

11

I

"DON'T CARE

LOGICAL SEQUENCES:
1-CLA
2-MQA,MQL
3-ALL OTHERS

Figure

8: Group 3 Microinstruction Format

Table V: Group 3 Operate Microinstructions

OCTAL
CODE

LOGICAL
SEQUENCE

NUMBER
OF
. STATES

NOP
MOL

7401
7.421

3
2

10
10

MOA

7501

2

10

MNEMONIC

-

SWP

7521

3

10

CLA
CAM

7601
. 7621

1
3

10
10

ACL

,

7701

3

10

CLA SWP

7721

3

10

OPERATION
: NO OPERATION-see Group 1 Microinstructions
MQ REGISTER LOAD-The content of the AC IS loaded

i,nto the MO,'the AC IS cleared and the onginal

content of the MQ IS lost.

MQ REGISTER INTO ACCUMULATOR-The ~onlenl of IheMO "OR edwith the content oftheAC

and the resul~ is load~d Into the AG. The, onglnal content 0,' the AC is lost but the original content of the MQ isrelained
This Instruc\JOn provides the.programmer With an InclUSive OR operation

SWAP ACCUMULATORAN D MO REG ISTER-The content of the AC and MO "e tnte SAMPLE REQUEST LINES

(!i) DON'T CARE DEV WRITE

C6l INSTRUCTION ADDRESS

Figure 13: Interrupt Enable FF ON liON)

CONTROL PANEL INTERRYPT TRANSFER
The IM6100 supports a memory space completely separate
from main memory; called control panel memory. Therefore,
the IM61 00 control panel and other supervisory functions are
implemented in software. This implementation need not use
any part of the main memory or change the processor state.
This is an important feature, since the final version of the
system may not have a control panel and the system
designer would like to use the entire cap'acity of the main
memory for the specific system application.
The control panel communicates with the IM6100 with the
Control Panel Request, CPREQ, line. The CPREQ is functionally similar to the INTREQ with some important.
differences. The CPREQ is granted even when the machine
is in the HALT state; the IM6100 is temporarily putin the RUN

state forthe duration ofthe panel routine. The IM61 00 reverts
to its original processor state after the panel routine has been
executed.
The CPR EO does not affect the interrupt enable system, and
the processor IOTtnstruction, ION is redefined and IOF is
ignored while 'the IM6100 is in the Control Panel Mode. Once
a CPREQ is granted, the IM6100 "Viii not recognize any
DMAREQ or INTREQ until CPREQ has been fully serviced.
When a CPREQ is granted, the PC is stored in location OOOOs
of the Panel Memory and the IM6100 resumes operation at
location 77778. The Panel Memory would be organized with
RAM',s in the lower pages and PROM's in the higher pages.
The control panel service routine would be stored in the
higher pages in the nonvolatile PROM's, starting at 77778. '

EXECUTE

CPINT

.

IFETCH

STATES

CPREQ
INTERNAL
CNTRL FF
IFETCH
LXMAR

1-__..L...=-====~===='"'='"'='"'~"""=""""""""""""""1

1

I

.

j
I

,~

~------tI3------o-t

STATES

Figure 24: Write Transfer Wail Circuil

Xtb

Figure 24 shows a logic implementation to wait during
WRITE's only.
The rising edge of MEMSEL (or CPSEL or DEVSEU during
READ clocks in a zero 'on the WAIT line. XTB, after a delay,
releases the WAIT line. Every WRITE pulse is preceded by a
READ pulse, and if no write operation is performed in a cycle,
the T6 state is not entered and the WAIT line is not sampled.
For x units of delay, the following conditions must be mel:

Xtc

WAIT:::::::::E~:::::::::::::::E~::=
Figure 22: Wait Line Sampling Timing
t - > - - - - - 112

MEMSEL
DEVSEL
XTA
.. D!':!.Y-,
~

-----i

--

txl(min) + 1131min) - Iwh

111--------l~

2: X

~ and
2

Figure 23: Memory And Input Transfer Wait Circuit
The circuit shown in Figure 23 will. make the IM6100 wait
during main memory and device input (READ) transfers.
MEMSEL or DEVSEL, being 10'11', will assert WAIT low. When.
XTA becomes active high, the WAIT line is asserted high
after a delay. The wait duration is.controlled by the delay in
the XTA-WAIT path IILl).
.
The following conditions must be satisfied to obtain x units
of delay during READ's:
.

m
•
•

ts!(max) + tI2(max) + tws < Is

Ixt(max) + tI3(max) + tws < (x + 1) ~
2
In the circuit shown in Figure 2S, the WAIT signal is normally
asserted low and it is released by XTA during READ's and
XTB during WRITE's. Note that WAIT is active for all data
transfers. Since XTA and XTB have identical timing relative
to the WAIT sample point, the constraints to be satisfied are
as follows:

Ixt(mln) + tI4(min) - twh

2:

x ~ and
2

Ixl(mln) + tI1(min) - Iwh

2: X

~

txt(max) + 114(max) + Iws < (x + 1) ts

2

"2

Ixl(max) + 111(ma;) + Iws < (x + 1) ~
2

t - > - - - - - 114 ----~

For example, for an IM61001 device operating at4MHz, S.OV
and 2So C, the constraints to be met to obtain 1 unit of delay
12S0nsec) are as follows:
112(max) < Is - tsl(max) - Iws
< SOD - 300 - 30
< 170nsec

Fig~re

8·76

25: Data Transfer Wail Circuil

'IM6101
Programmable Interface'
Element (PIE)
FEATURES

GENERAL DESCRIPTION

• Compatible with IM6100 Microprocessor

The IM6101 is a Programmable Interface Element (PIE)
device designed for interfacing various peripheral
chips such as UART's, FIFO's, Keyboard Scanner's to
IM6100 Microprocessor. In this way, the IM6101
eliminates the need for additional external logic
between 6100 !-,P and its peripherals,

• Four Separate SENSE Input Lines to Sense the
Status of Peripheral Devices
• Four Programmable OPERATE Control Line,s for
READ/WRITE on Peripheral Devices
• FOLir General Purpose FLAGS each of which
is Programmable

The IM6101 provides the control signals to peripheral
devices for READING or WRITING on the OX bus by
activating the WRITE CNTRL and READ CNTRL lines
with lOT (Input Output Transfer) instructions.

• Chained Vectored Priority Interrupt Structure
Possible
o Low Power: Less than 1 mW @ 5V

Each IM6101 can sample 4 status lines from peripheral'
devices. It can also generate interrupt requests to the
!-,P if the corresponding individual interrupt enable bits
in th.e PIE are enabled and the respective status lines
become active.

• TTL Compatible at +5V

FUNCTIONAL BLOCK DIAGRAM

The four FLAG lines may beset or reset under program
control to send control information to the peripheral
devices or to send binary data:

OX IO.11)

LXMAR
OEVSEL

TO
IM6100

[

~

INTGNT

SEL (3.1i}ADDRESSING

ADDRESS

AND

CONTROL LOGIC

PRIN} ~~~~~~~6N

XTC

TOANO
FROM

C1
C2

POUT

OTHER PIE'S

INT/SKP

PIN CONFIGURATION (outline dwg DL, PL)

)
TO PERIPHERAL DEVICES

POUT

FIGURE 1.
WRITE 1
READ 1

ORDERING INFORMATION

C2
Ci
FLAG"

ORDER. CODE
PLASTIC PKG.
CERAMIC PKG.
MILITARY TEMP,
MILITARY TEMP.
WITH 6636

IM61!l1·l
IM6l0l·lIPL
IM6l0l·lIDL
IM6l0HMDL
IM6l0l·l
MDU6636

IM61!l1A
IM6l!l1·AIPL
IM6l0l·AIDL
IM6l0l·AMDL
IM6l0l·AMDU
6636

IM61!l1
IM610HPL
IM6l0l-lDL

FLAG 4
XTC

-

DEVSEL

OX"

-

OXg

ox.
OX7.

8·77

EiJ

IM6101
IM6101
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Industrial IM61011 .............. -40 0 G to +85°C
Storage Temperature ............ -65° C to 150° C
. Operating Voltage ..... : ............. 4.0V to 7.0V
Supply Voltage ................. :......... +8.0V
Voltage On Any Input or
Output Pin ........... :...... -0.3V to Vee +0.3V

NOTE: Stresses above those listed, under "Absolute Maximum
Ratings" may cause permanent·device failure. These are
stress ratings only and functional operation of the devices at'
these or any other conditions above those indicated in the
operation sections of this specification is not implied,
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.
.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5V
SYMBOL

± 10%,

PARAMETER

CONDITIONS

1 V,H

Input Voltage High

2 V,L

,Input Voltage Low

3

TA = -40°C to +85°C

Input Leakage

ilL

GND$V,N$Vee

-1.0
2.4

4 VOH

Output Voltage High

IOH = -0.2mA

5

VOL

Output Voltage Low

IOL = 2.0mA

6

IOlK

Output leakage

GND$Vour$Vee

7

ICCSS

Power Supply

Current~Standby

MIN

TYP

MAX

Vee-2.0

V
0.8

V

1.0

IJA

0.45

V

V

-1.0
1.0

Vee = 5V ± 10%

UNITS

1.0

IJA

100

IJA

8 'ICOOp

Power Supply Current'-:Dynamic

500

IJA

9 C,N

Input Capacitance

7.0

8.0

pF

Output Capacitance

8,0

10.0

pF

TYP

MAX

10 Co

Vee=5V±10%
f=250 kHz

A.C. CHARACTERISTICS
,TEST CONDITIONS: Vee
SYMBOL

= 5V ± 10%, TA = -40°C to +85°C,

PARAMETER

1

tdr

Delay from DJ::VSEL to READ

2

tdw

Delay from DEV8El to WRITE

Cl

= 50pF
MIN
100

UNITS

375

ns

375

ns

3

tdf

Delay from DEVSEl to FLAG

475

ns

4

tde

Delay from DEVSEL to C1, C2

560

ns

5

tdi

Delay from DEVSEL to SKP/INT

560

ns

6

tda

Delay fromOEVSEl to DX

560

ns

7
8
9
10
11

LXMAR Pulse Width

300

ns

tas

Address Setup Time

100

ns

tah

Address Hold Time

150

ns

tds

Data Setup Time

90

ns

tdh

Data Hold Time

150

ns

, t'xmar

Note: See Figure 2 for an A.C: Timing Diagram,

8-78

IM6101
IM6101A
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6101A .............. -40°C to +85°C
Storage Temperature ............ -65°C to 150°C
Operating Voltage .................. 4.0V to 11.0V
Supply Voltage ........................... +12.0V
Voltage On Any Input or
Output Pin· .. .. . . . . . . . . . . . ... -0.3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratil')gs only and functional operation of the devices at
these or any other conditi'ons above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditioos for
extended periods may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 10V ±5%,TA= -40°C to +85°0
SYMBOL

PARAMETER

1

VIH

Input Voltage High

2

ViL

Input Voltage Low

,CONDITIONS

3 IlL

Input Leakage

GNDSVINSVee

4

VOH

Output Voltage High

IOH= OrilA

5

VOL

Output Voltage Low

10L = OmA

6

IOLK

Output Leakage

GNDSVouTSVee

7

ICCSS

Power Supply Current-Standby

Vec=10V±5%

8

ICCOp

Power Supply Current-Dynamic

Vee=10V±5%
f=571 kHz

9

CIN

10 Co

,MIN

TYP

MAX

UNITS

20% Vee

V

1.0

p.A

V

70% Vee

-1.0
Vee-O.Q1

V
GND+0.01

V

1.0

p.A

1.0

500

p.A

2.0

rnA

Input Capacitance

7.0

8.0

pF

Output Capacitance

8.0

10.0

pF

TYP

MAX

-1.0

A.C. CHARACTERISTICS
TEST CONDITIONS: Vcc = 10V ±5%, TA = -40°C to +85°C, CL = 50pF
SYMBOL

PARAMETER

1

tdr,

Delay from DEVSEL to READ

2

tdw

Delay from DEV8EL to WRITE

3

tdf

4

tde

5
6

MIN

UNITS

150

ns

150

ns

Delay fro,m DEVSEL to FLAG

'200

ns

Delay from DEVSEL to C1, C2

215

ns

tdi

Delay from DEVSEL to SKP/INT

215

ns'

tda

Delay from DEVSEL to,DX

215

ns

50

7

tlxmar

LXMAR Pulse Width

120

ns

8

tas

Address Setup Time

40

ns

9

tah

Address Hold Time

10

tds

Data Setup Time

11

tdh

Data Hold Time

.

Note: See Figure 2 for an A.C. Timing Diagram,

8·79

50

ns

65

ns

50

ns

,

IM6101
IM6101AM
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Military IM6101AM ............. -55°C to +125°C
Storage Temperature ............ -65°C to 150°C
Operating Voltage .................. 4.0V to 11.0V
Supply Voltage ........ ; .................. +12.0V
Voltage On Any Input or
Output Pin .................. -O.3V to Vcc +O.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those in'dicated in' the
operation sections ·of this specification is not implied.
Exposure to absolute maximum· rating, conditions for
extende,d periods may cause devi<::e failures:,

D.C. CHARACTERISTICS
TEST CONDITIONS: Vcc = 10V +
- 5% , TA = -55°C to +125°C
SYMBOL

PARAMETER

CONDITIONS

1 VIH

Input Voltage High

2

Input Voltage Low'

VIL

MIN

TYP

MAX

UNITS

20% Vee

V

1.0

p.A

V

70% Vee

,

3

ilL

Input Leakage

GND:SVIN:SVee

4

VOH

Output Voltage High

10H = OmA

5

VOL

Output Voltage Low

10L = OmA

6

IOLK

Output Leakage

GND:SVouTS:Vee

-1.0
Vee-0.01 .

V
GND+0.01

V

1.0,

p.A

,1.0

500

p.A

-1.0

7

ICeSB

Power Su'pply Current-Standby

Vee=10V±5%

8

Iccop

Power Supply Current-Dynamic

Vee=10V±5%
f=571 kHz

2.0

rnA

9

CIN

Input Capacitance

7.0

8.0

pF

Output Capacitance,

8.0

10.0

pF

TYP

MAX

UNITS

165

ns

165

ns

10 Co

A.C. CHARACTERISTICS
TEST CONDITIONS: Vcc =10V
~YMBOL

± 5%,

TA = -55°C to +125°C, CL = 50pF

PARAMETER

MIN

1.

tdr

Delay from DEVSEL to READ

2

Idw

Delay from DEVSEL to WRITE

3

tdf

Delay from DEVSEL to FLAG

220

ns

4

tdc

Delay from DEVSEL to C1, C2

240

ns

5

Idi

Delay from DEVSEL to SKP/INT

240

ns

tda

Delay from DEVSEL to DX

240

ns

Ilxmar

LXMAR Pulse Width

135
45

ns

6
7

50

,

ns

las

Address Setup Time

9

tah

Address HO,ld Time

55

ns

10

tds

Data Setup Time

70

ns

Idh

Data Hold Time

55

ns

8

11

Note: See Figure 2 for an A.C. Timing Diagram.

8-80

IM6101
IM6101-11
ABSOLUTE MAXI,MUM RATINGS
Operating Temperature
IndustriallM6101-11 ............
Storage Temperature .••••..••.•.

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

-40°C to +B5°C
-65° C to 150° C

Operating Voltage ...•...•.•.•..••..• 4.0V to 7.0V
Supply Voltage. . • • . . • • . • . . . . • • • . . . . . . . . . .. +B.OV
Voltage On Any Input or
Output Pin ..•...•.....•.•.•. -0.3V to Vee +0.3V

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5V ± 10%, TA = -40°C to +B5°C
SYMBOL

PARAMETER

CONDITIONS

MIN

1 VIH

Input Voltage High

2 Vil

Input Voltage Low

3

Input Leakage

GND:5VIN:5Vee

-1.0
2.4

ill

TYP

MAX

UNITS

0.8

V

1.0

p.A

Vee-2.0

4 VOH

Output Voltage High

10H = -0.2mA

5 VOL

Output Voltage Low

IOL = 2.0mA

6 IOLK

Output Leakage

GND:5Vour:5Vee

7

V

V

-1.0

V

1.0

p.A

100

p.A

ICCSS

Power Supply Current-Standby

Vee = 5V ± 10%

8 lecop

Power Supply Current-Dynamic

Vee=5V±10%
f=330 kHz

500

p.A

9

Input Capacitance

7.0

8.0

pF

Output Capacitance

8.0

10.0

pF

TYP

MAX

CIN

10 Co

1.0

0.45

A.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5V ± 10%, TA = -40°C to +B5°C, CL = 50pF
SYMBOL

PARAMETER

1

tdr

Delay from DEVSEL to READ

2

tdW

Delay from DEVSEL to WRITE

3

MIN
100

UNITS

300

ns

300

ns

tdf

Delay from DEVSEL to FLAG

375

ns

4

tdc

Delay from DEVSEL to Cl, C2

460

ns

5

tdi

Delay from DEVSEL to SKP/INT

460

ns

460

ns

6

tda

Delay from DEVSEL to OX

7

tlxmar

LXMAR Pulse Width

240

ns

8

tas

Address Setup Time

80.

ns

9

tah

Address Hold Time

125

ns

10

tds

Data Setup Time

80

ns

11

tdh

Data Hold Time

100

ns

Note: see Figure 2 for an A.C. Timing Diagram.

8·81

IM6101
IMS101-1M
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Military IM610HM •......•.... -55°C to +125°C
Storage Temperature ......•..•.. -65° C to 150° C
Operating Voltage •........•........• 4.0V to l.OV
Supply Voltage ......... :................. +8.0V·
Voltage On Any Input or
.
Output Pin ...•....•......... -0.3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent 'device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied,
Exposure to absolute niaximum rating conditions for
extended periods may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5V +
- 10% , TA = -55°C to +125°C '

SYMBOL

PARAMETER

1 VIH

Input Voltage High

2 VIL

Input Voltage Lo,w

CONDITIONS

MIN

TYP

UNITS

q.8
1,0

V

V

3 IlL

Input Leakage

GND5:VIN5:Vee

-1.0

4 VOH

Output Voltage High

10H = -0.2mA

2.4

5 VOL

Output Voltage Low'

10L = 2.0mA

6

IOlK
7 'ecss
8 leeop

Output leakage

GND5:VoUT5:Vee

Power Supply Current-Standby

Vee = 5V ± 10%

Power Supply Current-Dynamic

Vec=5V±10%
f=330 kHz

9 CIN

Input Capacitance

7.0

Output Capacitance

10 Co

MAX

Vee-2.0

/loA
V

0.45

V

1.0

/loA

100

/loA

500
8.0

/loA
pF

8.0

10.0

pF

TYP

MAX

UNITS

330

ns

330

ns

-1.0
1.0

A.C. CHARACTERISTICS
TEST CONDITIONS: Vee =5V ± 10%, TA = -55°C to +125°C, Cl = 50pF

SYMBOL

MIN

PARAMETER

tdr

Delay from DEVSEL to READ

taw'

Delay from DEVSEL to WRITE

taf

Delay from DEVSEL to FLAG

415

ns

4

tdc

Delay from DEVSEL to C1, C2

510

. ns

5

tdl.

Delay from DEVSEL to SKP/INT

510

ns

6

tda

Delay from DEVSEL to OX

510

ns

7

tlxmar

LXMAR Pulse Width

265

ns

8

tas

Add,ress Setup Time

90

ns

9

tah

Address Hold Time

140

ns

10

tds
tOH

Data Setup Time

80

ns

Data Hold Time

110

ns

1
2
3

11

100

Note: See Figure 2 for an AC. Timing Diagram.

8·82

IM6101
IM610t FUNCTIONAL DESCRIPTION
Pin
Number

Symbol

Input!
Output

Description

1

Vee

+5 volts

2

INTGNT

A high level on INTERRUPT
GRANT Inhibits recognition of
new interrupt requests and allows the priority chain time to
uniquely specify a PIE.

3

PRIN

A high level ON PRIORITY IN
and an interrupt request will
select a PIE for vectored interrupt.

4

SENSE 4

The SENSE input is controlled
by the SL (sense level) and SP
(sense polarityl bits of control
register B. A high SL level will
cause the SKIP flip flop to be set
by a level while a low SL level
ca'uses sense and interrupt flip
flops to be set by an edge. A high
SP level will cause the sense flip
flop to set by a positive going
edge or high level. A high IE
(interrupt enable) level generates an interrupt request whenever the INT flip flop is set (by an
edge).

5

SENSE 3

See pin 4 - SENSE 4

6

SENSE 2

See pin 4 - SENSE 4

7

SENSE 1

See pin 4 - SENSE 4

8

SEL 3

Matching SELECT(3-71 inputs
with PIE addressing on DX(3-71
during IOTA selects a PIE for
programmed input output transfers.

9

SEL 4

See pin 8 - SEL 3

10

LXMAR

A positive pulse on LOAD EXTERNAL ADDRESS REGISTER
loads address and control data
from DX(3-11) into the address
register.

11

SEL 5

See Pin 8 -

12

SEL 6.

See Pin 8 - SEL 3

13

XTC

The XTC input is a timing signal
produced by the microprocessor. When XTC is high a low
going pulse on DEVSEL initiates
a "read" operation. When XTC is
low, a low going pulse on
DEVSEL initiates a "write" operation.

14

SEL 7

I

15

DX 0

I/O

Pin
Number

Symbol

Input!
Output

24
25

DX 9
DX 10

I/O
I/O

See Pin 15 - DX 0
See Pin 15 - DX 0

26

DX 11

I/O

See Pin 15 -

27

GND

28

DEVSEL

29

FLAG 4

o

The FLAG outputs reflect the
data stored in control register A.
Flags (1-41 can be set or reset by
changing data in CRA via a WRA
(write control register AI command. FLAG1 and FLAG3 can be
controlled directly by PIE commands
SFLAG1,
CFLAG1,
SFLAG3 and CFLAG3.

30

FLAG 3
FLAG 2

32

FLAG 1

33

C1

o
o
o
o

See Pin 29 -

31

I/O

See Pin 15 -

DX 0

See Pin 15 -

DX 0

18

DX 3

I/O

See Pin 15 - DX 0

19

DX 4

I/O

See Pin 15 -

DX 0

20

DX 5

I/O'

See Pin 15 -

DX 0

21

DX 6

I/O

SeePin15-DXO

22

DX 7

I/O

See Pin 15 -

DX 0

23

DX 8

I/O

See Pin 15 -

DX 0

8-83

The PIE decodes address, control and priority information and
asserts outputs C1 and C2 during the IOTA cycle to control the
type of data transfer. These outputs are open drain for bussing
and require pullup resistors to
Vee.

C2

o
o

See Pin 33 -

READ1

36

WRITE1

o

Outputs WRITE1 arid WRITE2
are used to gate data from the
IM6100 DX bus into peripheral
devices. Data does not pass
through the PIE.

\

38

I/O

FLAG 4

34

Data transfers between the microprocesso-r and PIE take place
via these input/output pins.

DX 2

FLAG 4

See Pin 29 -

35

37

DX 1

FLAG 4

See Pin 29 -

C1 (LI, C2(LI- vectored interrupt
C1(LI, C2(HI - READ1: READ3
or RRA commands
C1(HI, C2(HI - all other instructions

See Pin 8 - SEL 3

17

DX 0

The DEVSEL input is a timing
signal produced by the microprocessor during lOT instructions. It is used by the PIE to
generate timing for controlling
PIE registers and "read" and
"write" .operations.

SEL 3

16

Description

READ2
WRITE2

39

SKP/INT

40

POUT

o
o
o

o

C1

Outputs READ1 and READ2 are
used to gate data from p!3ripheral devices onto the DX bus
for input to the IM6100. Note the
data does not pass through the
PIE.

See Pin 35 -

READ1

See Pin 36 - WRITE1
The PIE asserts this line low to
generate interrupt requests and
to signal the IM6100 when sense
flip flops 'are set during SKIP
instructions. This output is open
drain.
A high level on priority out indicates no higher priority PIE
interrupt requests are outstand-'
ing. This output is tied to the
PRIN input of the next lower
priority PIE in the chain.

IM6101
TIMING DIAGRAM
alon!L.wi~ecoded

Timing for a typical lOT transfer is shown in Figure 2.
During the IFETCH cycle, the processor obtains from
memory an lOT instruction of the form 6XXX. During
the IOTA the processor places that instruction back on
the OX lines@ and pulses LXMAR transferring
address and control information for the lOT transfer to
all peripheral 'devices. A low going pulse on DEVSEL
while XTC is high @)is used by the addressed PIE

control information to generate
C1, C2, SKP and controls, for data transfers to the
processor. Control outputs READ1 and READ2 are
used'to gate peripheral data to the OX lines during this
time. A low going pulse on DEVSEL while XTC is
low @ is used to generate WRITE1 and WRITE2
controls. These signals ,are used to clock processor
accumulator data into peripheral devices.

----~-----'----IOT I N S T R U C T I O N - - - - - - - - - - - ' - - - - - - + !

XTC

...I

\~

__~I

\~

____~I

\~

______~r--

n'LXMAR
LXMAR . - - / \_ _ _ _ _ _ _

MEMSEL

"---J

~~----------,------..,-----~~

~;
-II
'A DOH

'7?77TTm"!777',.,.,AS

DX(O·11)

~

0 ~%I@{~@ffA@J2?M1W01,a

0)

IDA

DEVSEL

IDR--j

7.-I:ii1-!oH

r- ~

~

t'::=.!DR

i -~

READ (NEGATIVE POLARITYI

1- ,'DW

'\

WRITE

V

WRITE
IOF-

l-

CFlAG

SFLAG

IDF--t.:=} _____________________________

m

FLAG (VIA WCRA COMMAND)

----------------------------- I:' ~~;,---------.1
101-

SifIii'iNT

INTERRUPT DATA

C;,a

INTERRUPT DATA

SKIP
IDC~

~'IDC

----

OX data, CO; el, C2'and
SKP are read by the IM6100
on the rising edge of T3

Sense FF's are sampled
when LXMAR is high
by the PIE

FIGURE 2. IM6101 PIE Timing Diagram.

All PIE timing is generated from IM6100 signals
LXMAR, DEVSEL, and XTC. No additional timing
signals, clocks, or one shots are required. Propagation
delays, pulse width, data setup and hold times are
specified for direct interfacing with the IM6100.
8·84

Interrupts are sampled by
the IM6l0C on the rising
edge of T2 of execution
cycle

IM6101
PIE ADDRESS AND INSTRUCTIONS
The 5 address bits (3-7) are compared with the
select inputs SEL3, SEL4, SEL5, SEL6, SEL7 to address
1 of 31 possible P.IE's. Address zero is reserved for
lOT's internal to the IM61 00. The four control bits are
decoded to select one of 16 instructions. Note also that
the lOT instructions 66XX are reserved for the Parallel
Input/Output Port (P10 - IM6103).

The IM61QO communicates with the PIE and with
peripherals through the PIE via lOT commands.
During the IOTA cycle (See Figure 1) an instruction of
the form 6XXX is loaded into all PIE instruction
registers. The bits are interpreted as shown below.

9

,.DDRESS

10

11

CONTROL

FIGURE 3. PIE Inslructlon Format.

CONTROL MNEMONICS
0000

READ1

1000

READ2

0001

WRITE1

1001
0010
0011
1010
1011

WRITE2
SKIP1
SKIP2
SKIP3
SKIP4

0100

RCRA

0101
1101
1100

WCRA
WCRB
WVR

0110

SFLAG1

1110
0111
1111
(S007)8

SFLAG3
CFLAG1
CFLAG3
CAF

DESCRIPTION
The READ instructions generate a pulse on the appropriate read outputs. This signal
is used by th,e peripheral device to gate data onto the OX bus to be "OR'ed" with the
IMS100 accumulator data.
The WRITE instructions generate a pulse on the appropriate write output. This signal
is used by peripherals to load the IMS100 accumulator data on the OX lines into
peripheral data registers.
The SKIP instructions test the state of the sense flip flops.lfthe input conditions have
set the sense flip flop, the PIE will assert the SKP/INT output causing the IMS100 to
skip the next program instruction. The sense flip flop is then cleared. If the sense flip
flop is not set, the PIE does not assert the SKP/INT output and the IMS100 will.execute
the next instruction.
The Read con@1 Register A instruction gates the contents of eRA onto the OX lines
during time 4 to be "OR" transferred to the IMS100 AC. (See Figure 2)
The Write Cqntrol Register A, Write Control RegisterB and Write Vector Register
of IOTA into
instructions transfer IMS100 AC data on the OX lines during time
.the appropriate register. (See Figure 2) Bits 10,11 of the VR;5, 7 of CRA; 8-11 of CRB
are don't care bits for these instructions.
The SET FLAG instructions set the bits FL 1 and FL3 in control register A to a high
level. PIE outputs FLAG1 and FLAG3 follow the data stored in bits FL1 and FL3 of
CRA.
The CLEAR FLAG instructions clear the bits FL 1 and FL3 in control register A to a low
level.
IMS100 internal.lOT instruction CLEAR ALL FLAGS clears the interrupt requests by
clearing the sense flip flops. It has no effect on control register output flags FL 1, FL2,
FL3, FL4. To clear these output flags, bits 0-3 of CRA must be cleared using WCRA
with bits. 0-3 of AC cleared.

®

-

PRIORITY FOR VECTORED INTERRUPT
A hardware priority network uniquely selects a PI E to
provide a vectored address. The first lOT command of
any type, after the I M61 00 signal INTERRUPT GRANT
goes high, resets the line INTGNT to a low level. The
signal INTGNT is used to freeze the priority network
and enable vector generation. Within a given PIE, the
internal priority is int~rrogated during every LXMAR.

The highest priority PIE has PRIN tied to Vee. The
lowest priority PIE is the last one on the chain. The
vector address generated by the PI E consists of 10 bits
from the vector register and two bits that indicate the
sense input within the highest priority PIE that
generated the interrupt.
8;85

IM6101
A. Daisy-chaining of several
PIE chips"

1 " 2
B, Interrupt Vector
,Register Format.

!

4

9,

INTERRUPT VECTOR

10 11
SPRI: Sense Priority

SPRI

SPRI Conditions·

00
01
10
11

SENSE1
SENSE2 and not SENSE1
SENSE3 and not ISENSE2 orSENSE11
SENSE4 and not ISENSE3 or SENSE2 or SENSE11

'AUSense Input Imes are enabled for mterrupts,
FIGURE 4. IM6101 Priority for Vectored Interrupt.

I/O CONTROL LINES (C1 AND C2)
, the type of inputcoutput transfer is..,£on,trolled by the
selected PI E by activating the C1, C2 lines as shown
below. These outputs are open drain,
'

C1 C2
H
L

L

H DEV/PIE - AC Write
H AC - AC + DEVIPIE "OR" Read'
L PC - VECTOR ADDRESS Vectored Interrupt

INTERRUPT/SKIP (INT/SKP)
If the SENSE flip flop is set, the INT/SKP line is driven
low to cause the IM6100 to skip the next instruction.
This output is open drain.

Interrupt and skip information are time multiplexed on
the same lines. Since the IM6100 samples skip and
interrupt data at separate times (see Figure 1) there is
no degradation' in system performance. The PIE
samPle, s the se, nse flip flO,PS and generates an interru p
,t
request for enabled bits on the rising edge of LXMAR.
Interrupt requests are asserted by driving the INT(SKP
line low. During IOTA of SKIP instructions the
'INT/SKP, reflects the SENSE flip flop data,

m
•

,

CONTROL REGISTER A (CRA)
The CRA can be read and written by the IM6100 via
the'RCRA and WCRA commands. The format and
meaning of control bits are shown below.

10 11
!FL4I'FL3IFL21 FL11wP21 . IWP11 . IIE411E311E211E1!
o

9

• Don't care for WCRA, 0 for RCRA

FIGURE

li. Format for Control Register A.

FL(1-4)

IE(1-4)

Data on FLAG outputs corresponds to data in FL (1-4);
Changing the FL bits in CRA changes the corresponding FLAG output.

A high level on
interrupts.

WP(1,2)
A high level onWRITE POLARITY bits causes positive
pulses at the WRITE outputs (see Figure 1>'
8·86

INTERRUPT ENABLE enables

IM6101
CONTROL REGISTER B

. For the Interrupt flip flop to be set, the corresponding
interrupt enable bit must be set to 'one'. If the sense
input is programmed to be edge sensitive, the flip flop
is set when the edge occurs. If it was initially
programmed to be level sensitive and then the mo'de is
changed to be edge sensitive, the flip flop will be set if
the polarity of sense input line corresponds to its SP
bit.

The CRe can be written by the IM6100 via the WCRB
instruction. It has no read back capability. The format
and meaning of control bits are shown below. Bits 8-11
are don't care bits.

o

1

4

5

7

ISL41 SL31 SL21 SL11SP41SP31 SP21SP11

All conditions that set the Interrupt flip flop also set the
associated Skip flip flop. In addition, the Skip flip flop is
set when the 'Polarity of the sense input corresponds to
its SP bit in the level sensitive mode.
The Skip flip flop is cleared at IOTA READ time by
executing a CAF (6007) instruction or a SKIP
instruction on the associated sense input that actually
skips. In the level sensitive mode, whenever the
polarity of sense input does not correspond to its SP
bit, the sense FF is cleared.'
.

FIGURE 6. Format lor Control Register B.

SL{1-4)
A high level on the SENSE LEVEL bits causes
the'SENSE inputs to be level sensitive. A low level on
the SL bits causes the SENSE inputs to be edge
sensitive. The INT FFs are set only if a sense line is set
. up to be edge sensitive.

The Interrupt flip flop is cleared whenever the sense
flip flop is cleared. In addition, it is cleared if the
associated sense logic actually creates a vector, the
interrupt enable bit is cleared to a 'zero' or the sense
input is programmed to be level sensitive. Detailed
operation of resetting Interrupt and Skip flop flops are
as shown in Figure 7.

SP(1-4)
A high level on the SENSE POLARITY bits causes the
SKIP flip flop to be set by a high level or positive going
edge. A low level causes the SKI P flip flop to be set by a
low level. or negative going edge.

PERIPHERAL INTERFACE LINES
SENSE(1-4)
The IM6101 has two latches associated with each
sense input - a SKIP flip flop and an INTERRUPT flip
flop.

a

0

0

INT

F/F

"'~ENAC TIVE EDGE
'" 1 WHEN ACT tVE
LEVEL IS TR UE

SL

c

r- c

0:

INTREQ"" L WHEN ACTIVE EDGE OCCURS

0:

SKP = L WHEN ACTIVE EDGE

A

Y

~

s
a

'- 0

0

SKIP

F/F.

-c

-C

A

lXMAR

RESET
SKP FF tL)

RESET SKP FFI'" CA F + SKP ON i + (SL '" 1) (ACTIVE LEVEL IS FALSE)
RESET

RESET INT FFi "" CAF + SKp· ON i + ISL "" 1) + VECTOR ON i

tNT FF ILl

Figure 7. IM6101 SKIP Flip Flop and INTERRUPT Flip Flop Input Diagram.

8·87

IM6101
APPLICATIONS
INTRODUCTION
generated the request. Each'one of these locations must
contain a Jump instruction pointing to the specific service
routine for the corresponding sense input. The 36.6;'5
interrupt acknowledge time at 3.3 MHz consists of 171'5
(max) to recognize an interrupt request, 3.61's to grant an
interrupt request, 10l's to execute theVECT for vectoring
and 6.01'S10 execute a Jump instruction to a specific
service r.outine.

The IM6101, Programmable Interface. Element (PIE), .
provides a universal means of interfacing industry
standard LSI devices and peripheral equipment
controllers to the IM6100 Microprocessor.
The IM6100 configures each PIE for a specific interface.
during system initialization by programming the control
registers within the PI.E for write enable polarities, sense
polarities, sense edges or levels, flag values and interrupt
enables .. On power-up, the registers will contain random
bit patterns.
'
The data transfer between the IM6100 and the peripheral'
devices does not take place through the PIE. The programmable Interface Element provides the steering
Signals for data transfers. This approach was chosen
since all the standard LSI. elements such as Keyboard
chips, UA~Ts, FIFOs,etc. have internal storage latches
and they require only control signals to take data from the
bus or to put data on the bus. If some user defined
peripheral interfaces do not have these built-in storage
elements, discrete CMOS or low power Schottky latches,
or flip-flops, must be provided to store the data from the
IM6100 until the peripheral device is ready to accept it and
to latch data from the peripheral devices until the IM6100
asks for it.

Proper vectoring requires the following
conditions:
1. The IM6100 must be enabl.ed for interrupts with the
ION command.
2. The INTGNT output of the IM6100 must be connected
to the INTGNT of all the PIEs and the PRIN oi the PIE
with the highest priority must be connected to VCC·
and its PROUT should be connected to the PRIN of the
PIE with the next highest priority and so on.
3. The IE bit of the sense line that is expected to generate
the interrupt must be set to 1.
4. The sense line must be 'programmed to be edge
sensitive. If a sense line is programmed to be level
sensitive, it will not generate an INTREQ nor will it
generate a vector.
5. The vector register of the PIE must be initialized with
the proper vector. Note that the two least significant
bits are generated by the PIE itself.

INTERRUPT PROCESSING WITH PIE'S
The PIEs provide for a vectored priority interrupt scheme.
Up to 31 PIEs may be chained to obtain 124 interrupt lines.
The microprocessor will recognize, identify and start
serVicing the highest priority interrupt request within
36.61'5 at 3.3MHz.
The INTREQ lines from all PIEs are wire-ANDed together.
A PIE generates an interrupt request, if anyone of its four
sense lines, which are interrupt enabled, become active
by driving the INTREQ line to the IM6100 low. If no higher
priority requests are outstanding (RE,5ET, CPREQ, HL T
or DMAREQ), the IM6100 will grantthe request at the end
of the current instruction. The content of the Program
Counter is deposited in location OOOOa of the memory and
the program fetches the next instruction from location
0001a. The retur'l address is hence available in location
OOOOa. This address must be saved in a sbftware stack if
nested interrupts are allowed.

6. The C1 and C2 lines cif all the PIEs must be wired
together with the C1 and C2 of the IM6100 and pull up
resistors must be provided on·these lines since the PIE
C1 and C2 outputs are open drain. TheSKP/INT line of
the PIE must be wired with the INTand SKP lines of the
IM6100. If the PIE OX lines are buffered, the external
bus must be enabled onto the PIE OX with the XTB.
being active high and the PIE OX bus must be enabled
onto the external bus when the C1 line of a PIE is active
low {during RCRA, READ1, READ2 or vectorJ.

m
•
•

7. The vector address will be generated with the first lOT
of any kind after the INTGNT.
.
8. Note also that a successful skip on a sense line will
reset an interrupt request by the sense line, if any. One
should not thus turn on the interrupt system after a
successful skip on a sense line expecting that the
sense line that was just tested will generate a request.

The IM6100 activates the INTGNT signal high when an
INTREQ is acknowledged. The INTGNT is reset by exe,cuting any lOT instruction. Thel PIEs use the INTGNT
signal to freeze the priority network and to uniquely
specify the PIE with the highest priority interrupt request.
The PIE with the highest priority request sends a unique
vector address to the'IM6100 when the processor
executes the first·IOT instruction after the INTGNT. The
I nterrupt II Prototyping System uses the lOT instruction
VECT(6047) for Vectoring.

SKIP HANDLING WITH PIE'S
Each PIE provides for four SENSE lines. The active state
of the SENSE inputs can be programmed to be a low level,
high level, positive edge or negative edge. There is a
SENSE FF in the PIE associated with each SENSE line.
This FF is set when the SENSE line is "active".
The state .of the SENSE FF can be tested by the SKP
comman;;ts, When the IM6100 executes a SKIP instruction, it will skip .the next sequential instruction if
the SENSE FFi is set. If the skip is successful, the FF will
be cleared.

The 12-bit vector address generated by the PIE consists of
10 high order bits from the vector register, defined by the'
user during system initialization, and two' low order bits
which indicate the sense input that generated. the
interrupt. Therefor.e, if the instruction in location 0001a is
VECT-6047a, the processor will branch to 1 of 4 locations,
depending on which of the sense lines within
PIE

If the sense line was set up to be edge sensitive, it can,
therefore,be tested for the 'set' state only once. If the FFis
set by a level, it will be cleared by the successful skip and.
then, set immediately by the active level.

a

8,88

IM6101
PIE INSTRUCTiON FORMAT

If the SENSE FF was set by an edge, and the respective IE
bit is enabled, the PIE will generate an INTREQ to the
I M61 00. Provided the priority conditions are met, the PI E
will supply the vector address to the IM6100 when it
executes the first lOT instruction of any kind, after the
INTREQ has been granted. If the vector address is
generated by FFi, one may still skip once on sense line i.
It should be noted that if priority vectoring is inhibited by
grounding PRIN, an INTREQ will be cleared only if a
SKIPi instruction is executed to test the FFi that generated
the request. Note also that an INTREQ will not be
generated if the sense line was set up to be level sensitive..
In certain instances, one may be interested in restoring
the set state of a SENSE FF after it has been successfully
tested and cleared and if the SENSE line has been
programmed to be edge sensitive. For example, assume
that SENSEi is programmed to be positive edge sensitive
(SL 1 = 0, SP1 = 11. The transition from a 0 to 1 occurred;
SENSE FF1 is set; SENSEi is at a 1 level. SKIP1
instruction will clear SENSE FF1. TheSENSE FF1 can be
set, under program control, by .creating an internal edge.
This is accomplished, in this specific instance, by
programm'ing SP1 to a 0 and then back to a 1. Since SP1 is
inCRB and it cannot be read from the PIE, the CRB
constant must be stored in User memory, for example,
location KCRB.
CLA
TAD KCRB
AND K7740
WCRB
TAD K0020
WCRB
KCRB, CRB
K7740, 7740
K0020, 0020

The IM6100 communicates with the PIEs using the InputOutput Transfer (lOTI instructions. The first three bits, 02, are always set to 68 (1101 to specify an lOT instruction,
The standard PDP-8/E'" convention is to set the next '6
bits, 3-8, to specify 1 of 64110 devices and then to control
the operation of the selected 1/0 device by using bits 9-11.
However, the PDPc8/E interfaces are not standardized
since a specific pattern of bits 9-11 could specify
completely different operations in different I/O devices.
For example, the pattern 000 in bits 9-11 could mean a
.read operation for Interface A, a write operation for
Interface B,a skip instruction .for Interface C and so on
since'the operation for any lOT instruction depends
entirely upon the circuitry designed into the 1/0 device
interface.
The lOT instruction format for the PIE is different from
that used by PDP-8/E'" interfaces. The first three bits are,
as usual, set to 68 to indicate an lOT instruction. The next 5
bits, 3-7, specify 1 of 31 PIEs.and then the operation of the
selected PIE is controlled by bits 8-11 in 16 uniquely
specified ways. For example, the specific pattern 0000 in
bits'8-11 means exactly the same operation for all PIEs,
namely activate READ1 line.
Of the 32 possible combinations of bits 3-7, the pattern
00000 is reserved for internal Processor lOT instructions
and hence not available as a PIE address.
Recommended address aSSignments for the IM6101-PIE
(Programmable Interface Elementl are as follows:
Internal lOT (600X) 'and DEC HS RDR (601X)
000 00
000 01
DEC HS PUNCH (602X) and DEC TTY
Keyboard (603XI
DEC ·TTY PRINTER (604X)
000 10
INTERCEPT PIE-UART Serial Interface
000 11
INTERCEPT PIE-UART PRINTER Interface,
001 00
IM6102-MEDIC REAL TIME CLOCK
001 01
001 10
Reserved for Intercept Option - 1
001 11
Reserved for Intercept Option - 2
010 00
IM6102-MED19 EMC/DMA
010 01
IM6102-MEDIC EMC/DMA
IM6102-MEDIC EMC/DMA
010 10
IM6102-MEDIC EMC/DMA
010 11
011 00
IM6103-P10
011 01
IN6103-P10
011 10
IN6103-P10
IN6103-P10
011 11:
100 00
USER
USER
100 01
100 10
USER
100 11
USER
101 00
USER
101 01
USER
101 10
USER
101 11
USER
110 00
USER
110 01
USER
110 10
USER
110 11 ,USER
Reserved for Intercept Option - 5
111 00
Reserved for Intercept Option - 4
111 01
Intercept FLOPPY DISK System' (675X)
11.1 10
111 11
Reserved for Intercept Option - 3

IGet CRB constant
ISP1 = 0
IWrite CRB to clear SP1
/SP1 = 1
IWrite CRB to set SP1
ICRB constant

Software systems employing Skip's on a Sense input while
allowing the same input to create an Interrupt should pay
attention to the fact that the Skip and Interrupt flip flops
are synchronized by LXMAR from the IM6100. Since there
is no LXMAR during 10TB of an 1/0 instruction, the
following can occur. Assume that the following two
instruction sequence is used:
SKIP SENSEX
JMP .-1

[8

ISENSE F/F SET?
INO: WAIT FOR !T

Where SENSEX is also Interupt enabled.
Now, assume that the appropriate 'Edge' occurs during
the fetch state of the Skip instruction. The Edge causes
both flip flops to be set and the LXMAR produced at IOTA
time creates an Interrupt request. 'The Skip instruction
execution causes a Skip and clears the Skip flop flop.
However, the Interrupt flip flop will not reflect thefactthat
the Skip flip flop has been cleared until after the next
LXMAR ·occurs. So, the Interrupt request remains active
during 10TB time since the 10TB cycle does not have a
LXMAR. The IM6100 honorS the Interrupt request since
the next LXMAR doesn't oc'cur until after the lOT is
finished. The Interrupt servicing routine will not Skip
. again if it tries to find the device that created the Interrupt.
Note that the proper Vector Address will still be generated.

8-89

IM6101
DEFINITION

PARAMETER

Minimum Peripheral device write data hold time w.r.t. leading edge of WRITE

+ tow (MIN) (IM610i) - toso (IM6100)
tOHO (IM6100) + twpo (IM6100) - tow (MAX) (IM6101)

Maximum Peripheral device read data enable time

tENO (IM6100) - tOR (IM6101)

Minimum Peripheral device write data setup time w.r.t. leading edge of WRITE

twpo (IM6100)

processor. The IM6403 makes provisions for a crystal
oscillator and internal divider chain to specify the data
transfer rate. In the IM6402 the data transfer rate is
controlled by an external timing source, for example, a
Baud· Generator.
A functional block diagram of the PIElUART/IM6100
interface is shown below. The UART;"s configured, in this
specific example, to interface with an ASR-33 Teletype
which hasa data format that consists of 11 bits - a start
bi~, 8 data bits and 2 stop bits. The UART is clocked at 16X
the data rate. For the 10 character per second ASR-33, the
UART clock frequency' would be 1.76 KHz.
An 8-bit· data word from the IM6100 Accumulator is
loaded into. the Transmitt.er .Buffer Register via inputs
TBR8-TBR1 when the Transmit Buffer Register Load
(TBRLl signal makes a zero to one transition. A high level
on Transmit Buffer Register Empty (TBRE) indicates that
the buffer is ready to accept a new character for transmission. The microprocessor checks .the status of TBRE
via SENSE;2 before it transmits a new character to the
UART by pulsing WRITE1. The start bit, data bits and stop
bits appear serially at the Transmit Register Output (TRO).
A serial data stream on the Receiver Register Input (RRIl is
clocked into the Receive Buffer·Register. A high level on
Data Received (DR) indicates that a character has been
received. The contents of Receiver Buffer Register appear
on the outputs RBR8-RBR1 when a low level is applied to
Receiver Register Disable (RRD) input. The RBR outputs
are tristated when RRD is high. A low level on Data
Received Reset (ORR) clears the DR flag. RRD and DRR

TIMING REQUIREMENTS "ON PERIPHERAL
DEVICES
The timing required on peripheral devices is affected by
the combined delays of the IM6100.and IM6101 devices.
The table above describes the peripheral device timing'
requirements with respectto the data givell forthe IM6100
and IM6101 AC characteristics ..
The values at any operating frequency, temperature
and/or power supply voltage can be evaluated by
substituting the calculated values for the IM6100 and·
IM6101 parameters in the defining expressions.

ASYNCHRONOUS SERIAL INTERFACE
WITH PIE AND UART
The, IM6402/03 Universal Asynchronous Receiverl
Transmitter i~ a general, purpose programmable serial
device for interfacing an asynchronous serial data
channel. to a parallel synchronous data channel. The
receiver converts a serial word with start, data, parity and
stop bits to a parallel data word and checks 'for parity,
framing and data overrun errors. The transmitter section
converts a parallel data word intoa serial word with start,
data, parity" and stop bits. The data word iength may be 5,
6, 7 or.8 bits. Parity may be odd or even. Parity checking
and generation can be inhibited. The number of stop bits
may be 1 or 2 or 1 1/2 when·transmittirig a 5 bit code.
The IM6402/03 can be used in a wide· variety of
applications "includirig interfacing modems, Teletype'·
and remote data acquisition systems tothe IM6100 micro-

PIE/UART/IM6100 INTERFACE

r1flRYSTAL.

J

,
,DX(O)

,

DX(11)
IM6100

lXMAR

OEVSEl ~
INTGNT
XTC

Cl
C2
SKP
INTREQ

~~ r

co Fvcc

"-

cc

II
..~ "" .;;:"
JS::
wz ...
~ -''''u

SELECT CODE:

SEl3 = a
SEL4 "".;
SELS "-' 1
SEL6"""1
SEL7 == 0

DX(4)~

~N'"
uuz

~
t=:

> ...
~~

,

ox (0)

8::
~

PIE
IM6101

JS::

WRITE

~
~

OX (11)

OX (l1)e

X-

READ1
WRITE 1

SENse',-r

TBR (8) RBR (8)
UART'

IM6402'
TBR(l)

"

RBR (1)

i--' ox (4)

~

I:i:
F::: ox

RRD

TBRl
DR
TBRE
RRI

~ .t

TRO

~

-----------

110 BAUO SERIAL PORT

8·90

(11)

ORR
PI =:-1
CLS1 == CLS2 = 1
SOS "" 1
RRC == TRC ~ 1.76 KHz
'CRYSTAL :S 2.5 MHz

No Parity
8 Data Blls
2 Stop BUs

110 Baud Rate

IM6101
IM6100 data bus (OX) to receive and transmit characters.

may be tied tog~ther to clear DR as the register data is
- being read. The microprocessor monitors the status of the
DR flag via SENSE1 to see if a new character has been
received before it reads the information stored in the
buffer register by pulsing READ1 low.
The UART interface uses only the low order 8 bits of the

The NAND gate is used to load the UMiT with the leading
edge of the WRITE pulse since the IM6100 data is valid
only with respect to the leading edge at higher operating
frequencies.

. PIE CONTROL REGISTER ASSIGNMENTS FOR IM6402 UARTINTERFACE:

o

,

2

3'

4

5

6

7

8

WP1 = 0
IE2 = 1 IE1 ,;" 1

'0"

9

CRAI~'____~_'~I_'__'__W_p_'_'~I___'__I_E2__
IE~'1
0'2345

CRB~I'_____
SL_2_S_L~'I_____s_P_2_S_p'~1
SL? = 0; SP2 = 1
SL 1 = 0; SP1 '= 1

Active low WRITE1 (TBRU
Interrupt enable for· SENSE2 (TBRE)
Interrupt enable for SENSE1 (DR)
If vectored inter'rupts are used
(PIN = 1 or is part of ~ priority
chain) the Interrupt Vector Register
must be loaded with the desired
vector address ..
SENSE2 (TBRE) active on 0 to 1 transition
SENSE1 (DR) active on 0 to 1 transition

PIE ADDRESS AND CONTROL ASSIGNMENTS:

,

0

2

I, ,

3

o 10

, ,5 ,
4

lOT

I, ,
1

'. ,

OCTAL
CODE

EXTERNAL COMMANDS
6

7

9

'0

o10 0

8

0

, , ,

6340

Activate RRD low to transfer Receiver Register
contents onto the OX lines and clear the Data
Received Flag.

6341

Activate TBRL low to transfer data from the OX
lines to the Transmit Buffer.Register.

6342

Skip the next instruction if the internal SENSE
FF1 was set by a positive transition on. Data \
Received (DR) and then clear SENSE FF1.

6343

Skip the next instruction if the internal SENSE
FF2 was set by a positive transition on Transmit
Buffer Register Empty (TBRE) and then clear
Sense FF2.

READ'

Address

o10

"o 1

o10

0

0

,

1

WRITE'

o

I , , , oI
0

0

, oI

0

SKIP'

I' ,
.

o10

, , ,

o

1 0

, ,I

0

SKIP2

OCTAL
CODE

INTERNAL COMMANDS

, 2
5
"
I' lOT, o 1 , , , o I ,RCRA o I
I ' , o I , , , o I , ., I
3

0

6

4

0

7

B

0

9

DESCRIPTIQN

DESCRIPTION

'0
0

6344

'OR' transfer Control Register A to the. AC.

0

6345

Transfer AC to Control Register A

6355

Transfer AC to Control Register B

15354

Transfer AC (0-9) to Vector Register (0-9)

Address

0

0

WCRA

,

o10

I, ,

oro

1'

, , , o I' , , I
WCRB
, , , o I' , o I
0

0

WVR

,

-'

8·91

1116101
PIE Address and Control Assignments:
,

'

OCTAL
CODE

EXTERNAL COMMANDS

I

0,

1

2

3

4

5

6

7

8

9

1

1

o

11

0

1

0

o

1 0

0

Addre!~

lOT

10 11
1

o

1

6502'

Skip and clear if SENSE1 is low - used to detect
the status of the receive line,

o

I

6506

Set FLAG1 to put the transmit line high ("MARK")

1

I

6507,

Clear FLAG1
("SPACE")

o

I

6516

Set FLAG3 to enable the paper tape reader

SKIP1

',: '
11

Ii

' 1

o'

1,1 ' 0 1

DESCRIPTION'

0

I

0

1

1

SFLAG1
"

,I

1

,1

0 11 ' 0

'1,

0

o

I

0

1

1

CFLAG1'

I

1

o

1

11

0

1

0

o

11

J

1

1

SFLAG3
,

1

1

o

1

I' 1

0

0

1

o I,

1

to put the transmit line 19 w

1

1 '1 1

'

.

Clear F~AG3 to disab,le the paper tapEl reader

6517

CFLAG3

"

OCTAr
CODE

INTERNAL COMMANDS

I

0

1

"~

3

4

5

1

1

o

11

0

,1: , '0'

lOT

,

I

1

1

6

7

8

01 0

I

1"

0

1

0

1p 11

1 ' 0' '0
RCRA

Address

o

9

o

I

0

1

DESCRIPTION

0

I

6504

'OR' transfer Control Register A to AC

6505

Transfer AC to Control Register A

"

1

1

y,'CRA

/

,

I

1

1

o

11

'0

00

1

I

1

1

0

1

I

6515

I

6514

Transfer i.C to Control
Register B
,

.

"

WCRB
(

11

,1

01 1

0

l.O"

o[1 ,,1

0

0

WVR

8-92,

Transfer AC V ± 10%, CL = 50pF,TA = -55°C b+125°C'
SYMBOL' PARAMETER
1
2

VIH
VIL

3

ilL
VOH

4
5
6
7
8
9
10

VOL
IOLK
Icc
Icc
CIN
Co

CONDiTIONS

Input Voltage High
Input Voltage Low

MIN

UNITS

MAX

Input Leakagel11

Power Supply Current-Standby
Power Supply Current-Dynamic
Input Capacitancel11

GND:5VIN:5Vee

-1.0

IOH - OmA
.IqL = OmA

2.4

GND:5Vour:5Vee
VIN-GND or Vee
. fe = 2.5MHz

-1.0

V
V

0.8
1.0

-

. 'Output Voltage Highl21
Output Voltage Low
Output Leakage

I1A
V

0.45

V
p.A

1.0
800

p.A
mA
pF
pF

2.0
8.0
10.0'

7.0
8.0

Output Capacitancel11

NOTE: 1. Except pins 15, 29. 31

TVP

Vee -2,0

2. Except pins 32. 33, 34.

A.C. CHARACTERISTICS
TE.ST CONDITIONS: Vce = 5.0V_± .10%, TA = ~55°C to'+125°C, fc = 2.5MHz·
SYMBOL

PARAMETER

MIN'

1

Ilin

LXMAR Pulse Width IN

300

ns

2

lals

3
4

lalh
Iden
Icen
IdlS

Address Setup Time IN: OX-LXMAR \II
Address Hold Time IN: LXMAR(lI-OX
Data Output Enable Time: DEVSEL( I I-OX

80
120

ns
ns

5
6
7
8
'9·
10

Idlh
trst
Isld

Id~lx

11 tdem
12 ,Imdr
13 Imdw.
14 Imdwr
15

lid

16 Idrat
17 :Idxas
18 Idxah
19 Idren
20 ·trup .
21

Idwat

22

Idwen
Imws

23

24· Idms'
25 tdmh
26 Iwup

TYP

MAX

400
400

..

Controls. Output Enable Time: o'EVSELi I I-lines CO,Cl,C2,S/1
Data Input Setup Time: DX-DEVSELI! I
RESET Input Pulse Width
SKP/INTX to SKP/INT Propafjation EJelay

ns
ns
ns

100
100

Data Input Hold Time: DEVSEL,! I-DX

UNITS

ns

500
130

ns
ns·

DMA Control Signals Delay:-XTC-XTC';
MEMSEL-MEMSEL ',. LXMAR-LXMAR'

130

,ns

Enable/Disable Time from DMAGNT to EMA Lines

100

ns
ns

MEMSEL' Pulse Width READ

750
950
550

MEMSEL' Pulse Width WRITE
MEMSEL'" Pulse Width WRITE/REFSH
LXMAR' Pulse Wiqth.
DMA READ Access Time: LXMAR', I I-UP"I '
DX & EMA Address Setup Time .'V'{rt LXMAR'I I I
DX & EMA Address Hold Time Wrt LXMAR', I,

-

.

DMA READ Enable Time: ME;MSEL' ,I I-UP,II
UP Pulse Width,DMA READ
DMA WRITE Access Tir1']e: LXMAH'iI,-MEMSEL'!l1
DMA WRITE Enable Time: UP iI,-MEMSEL'!I;
MEMSEL' Setup Time DMA WRITE MEMSEL'!II-LXMAH'iII
Dt,.1AEN Setup Time Wrt XTA 'll
. DMAEN Hold Time Wrt XTA.' ! I
UP Pulse Width DMA WRITE

ns
ns

350

ns

750

,

120
175
550
350
750

./
I

ns
ns
ns
ns
ns
ns

550
100
100
100
750

8-102

ns

ns

..

ns.•
ns
ns

'IM6102
ARCHITECTURE
The IM6102 is composed of three distinct functions:
a). A OMA port that uses the bus during the second half of
a cycle t6 rea<:J, write, or refresh memory. The OMA port
logic i'ncludes a word cou n't register WC, a current address
register CA, an extended current address register ECA,
and a OMA status register.
b) An extended memory address controller that augments
the 12·bit addresses generated by the IM6100 microprocessor by s~pplying a 3-bit address field that may be
decoded to select one of eight 4096 word memory fields.
The. memory extension controller logic consists of an
, instructiqn field register IF, a data field register OF, an
instruction buffer register I B, and a save field register SF.
c) A realtime c;:lock whose mode and time base rate may be
programmed by the u~er. The clock logic includes a clock
enable register CE, a clock buffer register CB,a clock
counter register CC, and a time base multiplexer.
A block diagram of the IM6102 is shown in.Figure 1.
The IM6102 registers are s~mmarized as follows:
~.

Simultaneous DMA Channel (Figure 3)

CURRENT ADDRESS (CA) REGISTER
This register is a 12-bit presettable binary counter. At
the beginning of a SOMA tr3nsfer, th'e current address
must be set to the first location to be_accessed. The
content of. the CA register is incremented by 1 after a

SDMA transfer, and the incremented value is used as the
address of the memory location with which the' next
transfer will be performed.
EXTENDED CURRENT ADDRESS (ECA) REGISTER'
This is, a 3-bit presettable binary counter and if the carry
enable bit' of the OMA status register is set, the 12-bit
CA register and the :3 ECA bits are treated as one 15-bit.
register with the ECA bits most significant. If memory
field 7 (all 3 bits at logic one) is selected, the ECA cannot
increment, but will wrap around in fi,eld 7 and an F7
error (F7E) will occur. The Interrupt Enable bit IE in
SR11 must be set to enable F7E interrupts. If enabled the
F7E will request an interrupt. If the carry enable bit CE
in SR9 is not se.t, the .ECA is not incremented-when CA
goes from 7777 8 to 00008.
WORD COUNT (WC) REGISTER
(

A 12-bit pnisettable binary counter is used as a word
counter. At the beginning of a SOMA transfer, the two's
complement of the number' of 12-bit words to be transferred must be loaded into the WC. If enabled this will
initiate .the SOMA operation. The WC register is incremented by 1 after a SOMA transfer. If this value becomes
zero, word count overflow has occur~ed and if the IE bit
in SR 11 is set, interrupts are enabled and an interrupt is
requested. Unless instructed to be in the continuous run
mode, a WC overflow inhibits further transfers. The WOF
is set when the MSB of the WC register makes a "1" to
"0" transition.

DX

'2

LXMAR"
MSEL*

XTC·

IM6100

DMA

UP

OMAEN

PROUT

0

:i
'01

"" '"~
"
..!!l"&i

EMA(O·2t

VECTOR
INTERRUPT

EMA

INT/SKPX

IN

CSC (4MHz) elK

DUT

vee
GND

FIGURE 1: IM6102 MEMORY EXTENSION/DMA/INTERVAL TIMER CONTROLLER (MEDIC)

ED

IM6102
Symbol

Input!
Output

11

LXMAR'

o

LXMAR
IMS102

EMAO

12

XTC'

o

XTG. generated by the IM6102

SKP/INT

13

XTC

I'

CPU external minor cycle timing signal

14

CLOCK

I

Oscillator, OUT pulses from
CPU for timing the IM6102
DMA transfers.

I

Multiplexed SKP/INT line from
lower priority devices

Pin
Number

Pi'lOiJT
INTGNT
EMA2
EMA1

C;
UP

c;-

XTA

eo
osc OUT

lXMAR

15

DEVSEL

LXMAR*
XTC'

OSCIN

XTC

DX11

CLOCK

DX10

Qescriptlon
generated

16

DXO

110

Most significant bit of the
12-l>it multiplexed address and'
data 1/0 bus

SKP!INTX

GND

_ OXO

OX9

17

DX1

1/0

See pin 16-DXO

OX1

DXS

18

DX2

1/0

See pin 16-DXO

19

DX3

OX2

OX7

DX3

OX6

DX4

DX5

Input!
Output

20

Description

1

Vee

Supply voltage

2

DMAEN

Enable the IM6102 DMA channel to transfer data

3

DMAGNT

4

I

Direct memory access grant
from CPU

I

Memory select for read or write
'
from CPU

5

IFETCH

I

CPU flag indicating instruction
fetch cycle

6

MEMSEL'

o

Memory select generated by
the IM6102

I

7

UP

o

User pulse (read -or write}

9

XTA

I

CPU external minor cyci'e timing signal

10

LXMAR

I

A falling edge of LXMAR pulse
from CPU will load external
memory address register

DX4

See pin 16-DXO

1/0

See pin 16-DXO

21

DX5

1/0

See pin 16-DXO

22

DXS

'1/0,

See pin 1S-DXO

23

DX7

1/0

See pin 16-DXO

24

DX8

110

See pin 1S-DXO

25

DX9-

1/0

See pin 16-DXO

26

GND

1/0

Power Supply

27

DX10

1/0

See pin 16-DXO

28

DX11

1/0

29

OSCIN

I

Crystal input for timer oscillator

30

DEVSEL

I

Device select for read or write
from CPU

31

.OSC OUT

0

See pin 29

32

Co

0

Control lines to CPU determining type of peripheral data
transfer

l

See pin 16-DXO

c,
C2

0

See pin 32-Co

34

0

See pin 32-Co

35

SKP/INT

0

Multiplexed SKP/INT input to
the CPU

36

EMAO

0

Extended memory address
field [most significant bit}

37

EMAl

0

Extended
field

memory

address

38

EMA2

0

Extended
field

memory

address

33

Asynchronous reset will clear
Instruction'Field to Os, disable
all interrupts, initialize DMA
port to READ/REFRESH, initialize timer to "stop", "divide
by 212 mode" and "enable
divide counters"

8

1/0
(

IM6102 FUNCTIONAL PIN DESCRIPTION
Pin
Number Symbol

by the

39

INTGNT

I

CPU interrupt grant

40

PROUT

0

Priority out for vectored interrupt

NOTE: AIIDX lines are bidirectional with three-state outputs: Pinso, 8, 11,12,35,40 have active pullups; pins 32, 33: 34 have open drain
outputs; pin 15 has a resistive input pull up; all inputs are protected with resistors and clamp diodes __

8·104

IM6102
XTA
XTe
lXMAR

DX(O·11)

EMA(~21 --~~--~~--~--~~-4----~----~~~~-+----------~-----------

XTC·

DMA

UP

READ
MEMORY - DMA PORT

f---------------,

XTC"

DMA
WRITE

DMA PORT - MEMORY ~------------_,

FIGURE 2: MEDIC TIMING FOR DCA I

DMA Status Register
This register consists of 5 control bits and 2 flag bits for the SDMA feature. For a description refer to the register bit
assignments.

INTERRUPT VECTOR REGISTER
VRO·VR10
VR11",CQ'i!

SKOF

EMA

WORDCQUNT

weo-we1l

CURRENT ADDRESS

CAD· CAl'
RFSR

ILeAR

r,-I

R~~t

__ _

ACCUMULATOR

I

~-------------------------~

FIGURE 3: SOMA REGISTERS

OPERATION

normal processor bus usage. In other words, no memory
cycles are.. "stolen" from the processor; but the DMA
address and data are transferred on the bus during periods
that the DX bus is inactive.

The IM61 02 SDMA channel augments the throughput of the
IM6100 during DMA operations by transferring data be·
tween memory and peripheral devices simultaneously with
8-105

IM6102

\

.

TABLE 1 SUMMARY OF IM6102 INSTRUCTIONS

I:)

MNEMONIC

OCTAL
CODE

I/O CONTROL LINES
CO
Cl
C2

, OPERATION

GTF
RTF
COF
CIF.
COF, CIF
ROF
RIF
RIB
RMF
LlF

60.04
60.05
62Nl
62N2
62N3
6214
6224
6234
6244
6254

.0
1
1
1
1
1
1
1
·1
1

.0
1
1
1
1
.0
.0
.0
1
1

1
1
1
1
1
1
1
1
1
1

(j) Get flags,

CLZE

613.0

1

1

1

CLSK
FLOE

6131
6.132

1
1

1
1

1
1

CLAB

6133

1

1

1

CLEN
ClSA
CLBA
CLCA

6134
6135
6136
6137

0
.0
.0
.0

0
.0
.0

1
1
1
1

Clear Clock Enable Register if ~orrespondirig ACbit is'set
,
AC not changed
Skip on Clock Overflow Interrupt condition
Set Clock Enable Register if corresponding AC bit is set
AC not changed
AC .... Clock Buffer; Clock Buffer -> Clock Counter;
AC not changed
. Clock Enable Register .... AC
COF .... AC(.o). Clear COF Status bit
Clock Buffer .... AC
Clock Counter .... Clock Buffer; Clock Buffer -> AC

LCAR
RCAR
LWCR

62.05
6215
6225

.0
.0
0

1
.0
1

1
1
1

LEAR'
REAR
LFSR
RFSR

62N6
6235
6245
6255

1
1
.0
1

.1
.0
1
.0

1
1
1
1

SKOF
WRVR

6265
6275

1
.0

1
1

1.
1

CAF

6.007

1

1

1

,

0

INT I NH FF .... AC(3). SF (.0·5) .... AC(6·11)
(6) Return flags, AC(6·8) .... IB, AC(9·11) .... OF
Change Oata Field, N .... OF
Change IF, N .... IB •
Combination of ~OF, CIF
Read OF, OF + AC(6·8) .... AC(6·8)
Read IF, IF + AC(6·8) 4AC(6·8)
Read Save Field, SF + AC(6·11) .... AC(6·11)
Restore Mem. Field"SF(.o·2) .... IB, SF(3·5) .... OF
Loaq IF, IB .... IF

AC .... Current Address Register, .0 .... AC
Current Address Register .... AC
AC .... Word Count Register, Start OMA;.o .... AC; clears word
count overflow (WOF)
N .... Extended Current Address Register (ECA)
Read ECA, ECA + AC(6·8) -> AC(6·8)
AC (7 ·11 ) .... Status Register, .0 -> AC
OMA Status Register + AC(5·11) .....AC(5·11); clears Field 7
Wraparound error (F7E)
Skip on Word Count Overflow
AC(.o·l.o) -> Vector Register, ..o"" AC
@Clear all flags (F7E, W.oF, COF) Clear clock Enable
register, clock buffer c

NOTES:
1. The internal flags of the IM6100 are defined as follows: LINK -+ AC (0), INTREQ -+ AC (2) and INTERRUPT ENABLE I'F .... AC (4).
2. W\1en RTF is executed, the LINK is restored from AC (0) and the Inte"upt System is enabled after the 'next sequential ipstruction is executed.
The Interrupt Inhi!:>it FF is set preventing interrupts until the next JMP, JMS or LI F instruction is executed.
3. A hardware RESET clears F7E, WOF, 1.1.FF and COF. The I F and DF are cleared to OS. The DMA status register is cleared. (Read; refresh; .
disable F7E and WOF interrupts; no carry from CAO to ECA2). The clock Enable register is cleared (Disable COF interrupt; disable clock buffer
to clock counter transfer on COF; disablecounter). Counter/buffer is cleared •

. 8·1.06

IM6102
TABLE

2" SUMMARY OF IM6102 REGISTER' BIT ASSIGNMENTS

Current Address
Extended Current Address
Word Count
OMA Status (1 ) .
Interrupt Vector (2)
RIF Instruction (3)
RTF. CI F Instruction
GTF. RIB Instruction
CDF. RDF Instruction
RTF I nst,uction
Clock Enable (5)
Clock Buffer
:
Clock Overflow (6)

(1)

OXO

OX1

OX2

OX3

OX4

OX5

OX6

OX7

CAO

CAl - CA2

CA3.

CA4

CA5

WCO

WC1' WC2

WC3

WC4

VRO

VRl

VR3

VR4

WC5
SR5
VR5

CA6
ECAO
WC6
SR6
VR6
IFO
IBO
SFO
DFO

CA7
CAB
ECAl ECA2
WC7 WCB
SR7
SRB
VR7 VRB
IF2
IFl
IBl
IB2
SFl
SF2
DFl
DF2

CB6

EN7
CB7

VR2

IIFF(4)

END
CBO
COF

CBl

EN2
CB2

EN3
CB3

EN4
CB4

EN5
CB5

OX8

CBB

OX9

OX10 OX11

CA9

CA10 CAll

WCg
SR9
VR9

WC10 WCll
SR10 SRll
VR10 VRll

SF3

SF4

SF5 .

DFO

D.Fl

DF2

-CB9

CB10 CBll

DMA STATUS
SR5 Set if Field 7 wraparound carry er·ror F7E; cleared by CAF. RFSR (at.l0TA - XTCtime). RESET} ~~~~
SR6 Set if DMA Word Counter Overflow
WOF; cleared by CAF. lWCR. RESET
BITS
SR7 Mode Bit
Cleared by RESET (REFRESH MODE)
SRB Mode Bit 8 See below
SR9 Carry enable from CAO-ll to ECA2 if set - CE
SR10 DMA Write if set
SRllEnable F7E or WOF interrupt if set - IE
VRO -VR10 loaded from AC. VRll is equivalent to COF
IF Instruction Field;'cleared to 08 by RESET AND INTGNT
IIFF - Interrupt Inhibit Flip-Flop; set whenever IB IF; (CIF. CDF/CIF. RMF. RTF) clear~d by RESET
and I B .... I F transfer
END -' Enable Clock Overflow (COF) interrupt; cleared (interrupt disable) by RESET. CAF
EN2 - When set causes clock buffer to be transferred to clock counter on COF.
Counter runs at selected rate; COF remains set until cleared with ClSA .
.When cleared to O. counter runs at selected rate. overflow occurs every
212 counts and COF remains set.EN2 is cleared by RESET, CAF
EN3, EN4, EN5 - Select interval between pulses: Cleared to OOOby RESET.(c6unter disabled). CAF See'below.
EN7 - Inhibits clock prescaler when set. Cleared by RESET. CAF
COF - Clock Overflow status bit; cleared by CAF, RESET and elSA; complement provides lSB of interrupt vector.

7} ;

(2)
(3)
(4)
(5)

(6)

'*

SR 7, B 00
01
10

11

Refresh mode; WC is frozen, no UP, DMAEN don't care
Normal ~ode; DMAEN(H) freezes WC, CA and no
UP if WC has not overflowed; stop if WC overflows
Burst mode; DMAEN '(H) .freezes WC, CA and no
UP if WC has not overflowed; reverts to refresh
mode if WC overflows.
Stops'SDMA

EN 3,4,5
000
001
010
011
100
101
110
111

with

2 MHz clock
STOP
STOP
20 ms interval
2 ms interval
200 !lS interval
20 !ls i nter.val
2!ls interval
STOP

NOTES:
1, Bits SR 7 and 8 do 'not change when the DMA controlier stops or. reverts to refresh mode as a result of we overflow.
2 .. The "overflow" status is defined as set whe~,the most significant bit of a 'counter makes a "1" to '~O" 'transition.

8-107

IM6102
TABLE 3 SDMA INSTRUCTIONS
OCTAL
CODE

MNEMONIC

OPERATION

LCAR

6205 8

LOAD CURRENT ADDRESS REGISTER (CA) The contents of the AC replace
the contents of the CA and the AC is cleared. DMA sequencing is stopped.

RCAR

6215 8

LWCR

6225 8

READ CURRENT ADDRESS REGISTER
Description: Contents of CA transferred to AC.
LOAD WORD COUNT REGISTER (WC)
Description: Contents of AC are transferred to the WOR D COUNT REGISTE R,
the AC is cleared WORD COUNT OVERFLOW (WOF) is cleared and DMA
operation started.
LOAD IMMEDIATE TOEXTENDED CURRENT ADDRESS REGISTER (ECA)
Descriptiqn: Field N of the lOT instruction is transferred to the Extended current
address register.

LEAR

-

62N68

REAR

6235 8

LFSR

6245 8

RFSR

6255 8

SKOF

62658

WRVR

6275 8

CAF

6007 8

READ EXTENDED CA
Description: Extended current address register contents OR'd into bits 6,7,8,
of AC.
LOAD DMA FLAGS and STATUS REGISTER
Description: AC bits 7·11 are transferred to the DMA STATUS REGISTE R
and the AC is cleared.
' READ DMA FLAGS and STATUS REGISTER
Description: DMA Flags and Status Register bits are OR transferred into AC bits
5·11 and Field 7 wraparound error (F7E) is cleared.
SKIP ON OVERFLOW INTERRUPT
Description: The PC is incremented 'by 1 if a word count register overflow interrupt
condition is present causingnext instruCtion to be skipped.
WRITE VECTOR REGISTER
Description: AC bits 0·10 are transferred to the Vector Register and the AC is cleared.
CLEAR ALL FLAGS-clears F7E and WOF (and also COF), Clock enable and clock
buffer. The' DMA process is initiated if the status register is not set to the "stop" mode.

TABLE 4 DMA FLAGS AND STATUS REGISTER BIT
ASSIGNMENTS

DMA MODES
SR7 = SRa = 0 REFRESH MODE

0

If]
•

1

2

3

4

5

6

7

a

9

10

11

F7E

WOF

SR7

SRa

CE

R/W

IE

This is the mode to which the 6102 reverts on RESET.
The word count register clock input is disabled, the user
pulse (DMA data strobe) is suppressed and the DMAEN
input is ignored. However, provided valid DMA transfer
conditions are met in a particular memory cycle, the
DMA sequencer will be started, appropriate timing signals
will be generated and the current address register will be
clocked. Thus DMA read accesses will be performed con·
tinually with an essentially free·running current address
register, Read accesses will refresh dynamic memory. No
WOF is possible but an F7 E is possible if bit SR9 is set,
enabling a carry from the current address register to the
extended current address register.

where" - don't care for write and zero for read.
F7E
Fiela 7 wrap around carry error; cleared by
CAF, RFSR and RESET
WOF

Logic one indicates word counter overflow;
clear by CAF, LWCR and RESET

CE

Carry enable from CA(O·ll) to ECA; cleared
by RESET

R/W

Logic one indicates DMA write (Port to Mem·
ory transfer). Cleared (DMA Read) by RESET
Enable interrupt when WC overflows or Field 7
error occurs; cleared by RESET

IE
SR7,8

00
01

10

11

Refresh mode; WC is frozen, no UP,
OMAEN is don't care
Normal mode; OMAEN(H) freezes WC
CA and no UP if WC has not overflowed;
stop if WC overflows
Burst mode; OMAEN(H) freezes WC, CA
and no UP if WC has not overflowed;
refresh condition if WC overflows
Stops DMA

SR7 = 0; SRa = 1 NORMAL MODE
This mode is used for normal SOMA operations with
static memory. The following instruction sequence can
be used:
CLA
TAD CA
LCAR

8-108

/Clear AC
IGet starting address
/Load into current address register and,
clear AC

IM6102
TADSR
LFSR
TADWC
LWCR '

IGet DMA status Register Constant
IChange status (from refresh to normal
for example)
IGet two's complement of block length,
ILoad word count register a'nd start
DMA TRANSFERS

addressing.space of the system from 4K to 32K words. To
perform this functio.n, the EXT.ENDED MEMOHY· CONTROLLER maintains a 3-bit extended address which is de·
coded by the [llemory modules to select 1 of.S memory
fields each contajning 4096 words of storage. These 4K
fields start with FIELD 0 and progress to FIELD 7 when
32K of memory. is used. All software communication. with
the controller is via programmed lOT instructions for which
a summary is included in Table 1.

Note that LWCR will start the sequencer so it should be
the last instruction, in the initialization sequence. The
ECA register and vector register could also have been
initialized in this sequence.

Figure 4 shows t';;'o 3-bit field registers: the'lnstrudon
Field, which acts as an extension to the Instruction and
directly obtained operand adciress~s and the Data Fieid,
which augments indirectly obtained ope;and addresses. The
program can, therefore, use one'field for i.nstructions and
address pointers and another field for data. The selection
between Instruction and Data Fields is signalled by the
DATAF signal generated by the IM6100. A di5cussi~n of
the various registers Tollows.

The SDMA sequencer samples DMAEN on the rising
edge of every XTA and latches the condition of the
enable line. If·DMAEN is 'low, the sequencer is enabled,
external timing signals XTC*, MSEL *, UP, LXMAR*
are generated, the WC and CA registers are clocked.
If DMAEN is high, at XTA (t) time, the signal, is
sampled and latched and if the WC lias not overflowed,
the WC and CA registers are frozen, UP is suppressed.
If the WaF condition comes up, the SDMA operation
stops, regardless of DMAEN level.

EXTENDED MEMORY ADDRESS (0·2) .

The. DMAEN and UP signals provide a simple interlocked
handshaking method for transferring data one or more.
cliaracters at a ti,me (entire blocks) concurrently with
proceswr. operations on the bus. Of course, at all times,
independent of DMAEN, the SDMA sequencer can proceed only if other bus usage conditions for DMAoperations are met (not IOTA, IAUTOI, DCA, JMS, IJMS,
ISZ, DMAGNT, or access of location XOOOOS).
NOTE:

i'--c===::-:-:O:o:-::-'i-Oa REiSET.

'-,==='-l-'-=---,-'NT

lNT

N8

AMF

IAUTOI is an indirect cycle of any autoindexed instruction; IJMS is indirect cycle of JMS. An autoindexed .JMP

instruction may not be executed when the. DMA mode is
active.

'FIGURE'~: EMA REG'ISTERS

SR7 = 1; SRS = 0 BURST MODE

INSTRUCTION FIELD REGISTER (IF)

This mode is the same as the normal mode except when
the word count register overflows. When this happens,the
SDMA sequencer will set the WaF flag and revert to the
refresh mqde (ignoring DMAEN. freezing WC and suppressing UP). This mode is used when SDMA operations
and dynamic memory refresh must be c~nc~rrently performed. The system designer must control the block
lengths to be transferred, the refresh interval, and
memory system design according to the application and
performance desired;

The IFis a 3·bit r~gister that serves as an extension of
the Program Counter (PC). The IF, however, is not
incremented when the PC goes' from 77778 to -OOOOa.
The contents of the I F determine the field from which
all instructions are taken. Operands for all directly
addressed memory reference instructions also come from
the Instruction Field. The indirect pointerforall indirectIy addressed memory reference instructions reside in th~
Instruction Field. The IF is cleared to Os and the IM610d
Program Counter is set to 7777S by RESET.

SR7 = 1; SRS = 1 STOP MODE
. DATA FIELD REGISTER (OF)

In this mode, no SDMA operations will take place.
Naturally, cycle stealing DMAis still, possible, and indeed
may be used in any of the modes but the designer must
be avyare that cycle stealing may adversely affect dynamic
memory refresh' intervals. l..wCR and LFSR may be
executed in either order to change mode and start
DMA.

Th.e DF is a 3-bit register whiCh determines the memory
field from which operands are fetched in indirectly
addressed AND, TAD, ISZ or DCA instructions. However,
the branch address for indirectly addressed JMS or
JMP instructions is obtained from the Instruction Field.
The Data Field register may be modified under program

" B. Extended Memory Address Control

control. The DFis set to 0Si on reset.

Figure 4 shows the EMA registers in more detail along with
the register transfers caused by various instructions. The
EMA function of the IM6102 is program compatible with
the DEC PDP·S/E KMS-E Memory Extension option. The
purpose of the EMA function is to extend the effective

INSTRUCTION BUFFER

REGIST~R (lB)

The I B is a 3-bit 'registe~ which ~erves as an input buffer
for ,the Instruction Field (IF) register. All programmed
modifications of the IF register are made through the I B
S-109

[I'
•
_.

D~D[!"

IM8102
register. The transfer 'from IB'to IF takes 'plac~ at the
beginning of'theexecute phase of., the "next" JMP
"or JMS instqJction or immediately ,lipon execution of,
Pd~----------------~

CHANNELS

G,----f.>~~--------------~

, t:J

r'------~~----~,

E----~~~--------------------~

87654·32

*The "positions" of these "switches" are specified by the ROM programming
tape (segment A).

Figure 2

Frames

RAM SELECT PROGRAMMING (Frames 10-14)
Most memory systems contain both RAM and ROM. The
designer of such a system must insure that accesses to RAM
memory space do not enable the ROMs and vice versa. The
IM6312 ROM decodes address information on DXO and DX1 .
to provide a unique 1024 word address srace dedicated to
itself. It also provides a RAM Select (F) output which 'may be
used to enable an address space dedicated to RAM. The
states of DXO-DX3 which activate I' are programmed by
frames 10-13 respectively. Frame 14 determines whether I' is
considered active when high (frame 14 = H) or active when
low (frame 14 = L').
Frames 10-13 may be T (true I, V (don't care), or F (false I. For
example, if frames 10-13 are FTFV respectively, I' will be
active when address information on DXO and DX2 is F (lOW)
and DX1 is T (high I. DX3 may be either T or F, since it is
programmed V ("don't care") (see Table 31. Thus, in this
8·137

j

•

••
••
••••••
• •
•• • •
••

}

Location Setting Command to 04108
(Channel 7 punched in first frame)

}

Data Word = 74408 stored in
address 0410s

}

Data Word = 62108 stored
in address 04118

Figure 3
A data word consists of two frames with channels 8 and 7
unpunched. The two groups of six holes remaining are then
concatenated to form a 12-bit binary number (punched = H,
unpunched = LI. The most significant six bits are punched
first (channels 6-1 with 8 and 7 unpunchedl, followed by the
least significant bits. The MSB of the 12-bit data word is
channel 6 of the first frame; the LSB is channel 1 of the
second frame. Figure 3 shows examples of two data words,
74408 and 62108.

O~UIb
CHECKSUM

COMPATIBLE ASSEMBLER PROGRAMS

A two frame checksum precedes the leader/trailer at the end
of se'gn;rent B, It is the modulo 4096 sum of all frames in
s'egment B following the'initial lE'lader/trailer and preceding
the final leader/trailer (except the two frames that represent
the checksum itself), For purposes of checksum computation, each frame is to be considered an 8-bit binary word. The
12-bit result is punched out in two sequential frames, with
channels 8 and 7 unpunched. The most significant six bits are
punched first, followed by the least significant six bits as with
the data word format Any frame with channel7 or 8 punched
(e,g. leader or location setting command) is not included in
the checksum computation. For' additional BIN format
information, refer to "PDP®-8 Family Commonly Used Utility
Routines".

,PAL III, FOPAL III, MACRO-8, PAL 8, and IFDOS PAL are
assembler programs for the IM6100 microprocessor which
prepare a papertape conforming to the specifications for the
second tape segment The header must in any case be
produced manually. '
The input to a PAL assembler is ASCII source code, More
information and PAL assemblers are available from Intersil.
The firstframe-pairin a segment B produced by PAL III is a
location setting command to address 02008. This is ignored if
another origin setting follows immediately afterwards.
Some PAL assemblers produce a checksum with 13 bits (Le.,
channel 7 of the first frame of the checksum may be
punched). If channel 7 is punched, it is ignored.

®Registered trademark of Digital Equipment Corp.

A MINIMAL MICROPROCESSOR SYSTEM (64 OR 128 WORDS OF RAM)
,
.1

DXO-ll

i

L~r-

IM6100

r-E
GrG
IM6312 DXll r-l-DXO
r-tt-tROM D~~~ t-It-r-- DXl
DX8 f-tr-t- DX2
DX7 1-1t-r-- DX3
DX6 1-1'-r-- DX4
DX5 t-t- t- GND

L~-cs
......
r.,r ,....
,....

c- STR

r-- rrrt-- rt-

ADR
DXO
pXl
DX2
DX3
, ' - I- DX4
r- GND

,....
-

LXMAR
MSEL

,

Vee
MSEL' rIM6512 DXll r-tRAM DX10 r-tDX9 r-tDX8 r-IDX7 r-tDX6 r-tDX5 r-t-

I

yXCl~

r-

I
I

t-

rr
~

I
I
I

i

XTC t-

Vee
Lr-

-:--

STR
, MSEL rADR IM6512 DXll r-rg~~ RAM D~~~ r-tr-IDX2
DX8 r - r
DX7 t - r
DX3
DX6 t-r-DX4
GND
DX5 r-r--

(DELETE FOR
64 WORDS OF

I RAM)

8-138

~t-

U~U[l

IM63t8
18,384 Bit (2048x8)
CMOS ROM
common system bus structures. On-chip address registers
and two mask programmable Chip-selects simplify system
Interfacing requirements.

FEATURES
•
•
•
•
•
•
•
•

Low standby power: 11 mW maximum
High speed: 550ns maximum
On-chip address registers
TTl compatible inputs and three-state outputs
Completely static and asynchronous
Single 5V supply
Intel 2316E and Mostek MK34000 pin compatible
.Two mask programmable chip selects (active level
latched/unlatched)
• Outputs mask programmable (latched/unlatched)
• 8838 Processing available
• Military temperature range available
(-55°Cto +125°C)

The IM6316 operates over a 4.5V to 5.5V range, with an access time of 550ns and' standby current of 200 p.A
guaranteed over the industrial temperature range.

FUNCTIONAL DESCRIPTION
The falling edge of chip enable (E) latches addresses in
the on-chip register and initiates a read cycle. Address and
chip selects to be latched must be present a setup time
(TAVEL) prior to, and a hold time (TElAX) following the
failing edge of E. After an access time, valid data will be
available.
.
Optional latched outputs are active when S1 and S2 (or latched S1 and S2) are active. For unlatched outputs, E must;
also be low to ehable.
;.:.

GENERAL DESCRIPTION
The IM6316 is a 16,384-bit static silicon-gate CMOS read'only'memory (ROM) organized 2048 words by 8 bits. In all
static states, this device exhibits the microwatt power
dissipation typical of CMOS. Inputs and three-state outputs are TTl. compatible and allow for direct interface with ..

LOGICAL BLOCK DIAGRAM

aD Q1

02

Q3

04

QS

Optionallatches.for S1 and S2 are level sensitive. When E
is high, latched S1 and S2 thus perform as if they were not
latched.

PIN CONFIGURATION

Q6

LOGIC SYMBOL

07

51 52

E Vee

E-~----I
AO
AI
A2

AIO

A.

AB
A7
A6
AS
A4
A3
A2
AI
AO

O.
01

A3
A4

IM6316

04

A6

OS

A7
AB
16,384 BIT

-"'_.J"""-....-rr

06
07

A9

CELL ARRAY

02
03

AS

, A10

GND

-=-

·X = DON'T CARE

(outline dwgJG, PG)

.
'.j •.,~ • .

ORDERING INFORMATION

PIN NAMES

PART NUMBER

PACKAGE

TEMP. RANGE

IM6316IPG

24 PIN PLASTIC

-40·C to +85·C

IM6316IJG

24 PIN 9ERDIP

-40·C to +85·C

IM6316MJG

24 PIN CERDIP

-55·C to +125·C

8-139

AO-A1O

ADDRESS INPUTS

00-07

DATA OUTPUTS

E

ADDR .. S'fROBE/CHIP ENABLE .

S1,S2

CHIP SELECTS

m

IM6316

"n~nlL

. ABSOLUTE MAXIMUM, RATINGS
".SupplyVoltage ....•..................................... : ... _............ +8,OV
Input or Output Voltage Applied ....... ,............... GND -,.

7 .

~

MA7·MAO·

04·01

TPA

·f

CLOCK

A10·A8

Q3·Qj

a.r

S1
IM8316
2k x8
CMOS ROM

4042AQUAD
CLOCKED
"D"LATCH,

-,

M1m '
"

"

TPB
BUS7·BUSO

• ...

r
FIG.

A7·AO·

"

POLARITY

-L

CPD1802
CMOS "p

~

~."
'V",'

S'2

'.

E

-

Q7·QO

~

DATA BUS

f. 2K x 8 CMOS ROM

MEMORY FOR CP01802 CMOS MICROPROCESSOR .

~

ADDRESS/DATA BUS
~

PORT2 ,

v.11

DB7·DBO P27·P20

·n~

..

A10·AO

'P23

'

1

..

:

8048

.

-

S2
IM6316
2k x 8
CMOS ROM,

~P

.

..
..

,

Q7·QO

S'i

,

E"

ALE

~

FIG. 2. 2 k x 8 CMOS ROM MEMORY FOR 8048 or 8035 MICROCOMPUTERS

8·142

~

IM6316

L

ADDRESSIDATA BUS

r-

ADDRESS BUS

·U'-7

'.711

ADO·AD7 A15·A8

,

80851
NSC800

. Al0·AO

RD

Sl

101M

S2

~p

IM6316
2K x 8
CMOS ROM

E

ALE

FIG. 3. 2 k x 8 CMOS ROM MEMORY FOR 8085/NSC 800 MICROPROCESSORS

L

~

ADDRESS BUS

,

•

7

Al0·AO

51

RD

,
Z80A

S2

~p

MREQ

IM6316
2K x 8
CMOS ROM

E

.

07·00

1

,

07·00

").

f""

J

'---)

FIG. 4. 2 k x 8 CMOS ROM MEMORY FOR Z80A MICROPROCESSOR DATA BUS

8·143

~

O~OIb

IM6402/1M6403
Univ_rsal Asynchronous
.. Receiver T,.nsmiHer
(UART)

FEATURES·

GENERAL DESCRIPT.ION.

... Low Power -

Less Than 10~~ ~vp. lit 2MHz

• Operation Up to 4MH~ Clock (IM6402A)
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation

..

.

• Compatible. with Industry Standard UART's
IIM6402)
•

The d~ta word length can be 5, 6, 7 or 8 bits. Parity may be odd
or even, and parity checking and generation can be inhibited.
The stop bits may be one or two (or one and one-half when
t·ransmitting 5 bit code). Serial data format is shown in
Figure,6.

On-Chip O$ciJIator with External Crystal
(IM6403) .
.

• Operating VoltageIM6402-1/03-1: 5V
IM6402A/03A: 4-11V
IM6402/03: 5V

PIN CONfiGURATION

(outline dwg DL, PL)

Vee

EPE
elSl
SBS

RBRe

TABLE 1

RBA7

CRL

~BR6

TBRS
TaR7 .
TaR6

RBR3
RBR2
RBRl

PIN IM6402 IM6403 w/XTAL
Divide Control
N/C
17
RRC
XTAL

T8R5
T8R4
T8R3

PE
FE.

TBR2
TBRl

·19 Tri-State
22· Trj·State

40

TRC

IMIr403 w/EXT CLOCK

Always Active
Always Active

XT~L

GND

ORDER CODE
PLASTIC PKG
CERAMIC PKG
MILITARY TEMP.
MILITARY TEMP.
WITH B83B

TeRE*
MR

RRI

The IM6402 differs from the IM6403.in the use offive device
·pins as indicated in Table 1 and Figure 1.

ORDERING ·INFORMATION

TBRl

ORR

The IM6402 and IM6403 can be useq in a wide range of
applications including modems, printers, peripherals and
rE!mote data acquisition systems. CMOS/LSI technology
·permits clock frequencies up to 4.0MHz (250K Baud), an
impro~ement of 10 to 1 over previous PMOS UART designs.
Power requirements, by comparison, are reduced from
670mW to 10mW. Status logic increases flexibility and
. simplifies the user interfac·e.

Divide Control

f:xter~al Clock Input

-Always Active
Always Active

TRO
TRE
'*OR

The IM6402 and IM6403·· are CMOS/LSI UART's for
interfacing computers or microprocessors to asynchronous
serial data channels. The rec~ive~ converts serial start, data,
parity .and stop bits to parallel· data verifying proper code
transmission, parity, and stop bits. The transmitter converts
parallel data into., serial form and automatically adds start,
parity, and stop bits:

IM6402·11OII-l
IM6402.11fl3.1IPL
IM64o;l·1103.1IDL
IM6402·1/0Il-1MDL
IMfl40201103,1 .
MDUB83B

·IM6402A103A
IM6402JOII-AIPL
IM6402J03.AIDL
. IM6402I03,AMDL
IMIj402/0Il-AMDU
B83B

FUNCTIONAL BLOC.K DiAGRAM
. TRE
TBRE

*

IM8402tD3
1t,l6402ID3·IPL
.IM6402ID3IDL

--:--:---,

TBRl (LSB) .

-+----.,

~~~~~~~~

.

I
I

'----r-....... I

I

MULTIPLEXER

I
TRO

CLSl
C;LS2

.

CRL
MR

SBS

CONTROL
REGISTER

EPE
PI
RRI

RRC

MULTIPLEXER
RECEIVER REGISTER

* QR

RECEIVER BUFFER REGISTER

* These outputs lire three lt~e (lM6402) or always active (IM6403)
8-144

IM6402/IM6403
I M6402l1M6403
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IM6402/03 . . . . . . . . ... . . . . . . . . . . . . • . • . -40°C to +85°C
Storage Temperature ................... -65°C to 150°C
Operating Voltage ......................... 4.0V to 7.0V
Supply Voltage .................................. ~ +8.0V
Voltage On Any Input or Output Pin .. -0.3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolu.te Maximum
Ratings" may cause perman~nt device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections ofthis specification is not implied. Exposure
to absolute m~ximum rating conditions for extended periods
may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee
SYMBOL

= 5.0 ± 10%, TA = -40°C to +85°C
PARAMETER

MIN

CONDITIONS

1

VIH

Input Voltage High

2.

VIL

Input Voltage Low

3

IlL

4

VOH'

Output Voltage High

IOH - -0.2mA

5

VOL

Output Voltage Low

IOL =1.6mA

6

IOLK

Output Leakage

GND';;VOUT';;VCC

7

ICC

Power Supply Current StandbY

8

ICC

Power Supply Current IM6402 Dynamic

fc

fcrystal

TYP

MAX

. Input Leakage!']

-5.0

GND';;VIN';;VCC

=

0.8

V

5.0

/lA
V

2.4
-5.0
'1.0

VIWGND or Vec

UNITS
V

VCC-2.0

500 KHz

0.45

V

5.0

/lA

800

/lA

1.2

mA

g

IcC

Power Supply Current IM6403 Dynamic

3.7

mA

10

CIN

I nput Capacitance]']

7.0

8.0

pF

11

Co

Output Capacitance!']

8.0

10.0

pF

'TYP

. MAX

UNITS

1.0

MHz

2.46

MHz

=

2.46MHz

-

NOTE 1: Except IM6403 XTAL mput pms !I.e. pms 17 and 40).
NOTE 2, VCC - 5V. TA = 25°C.

A.C; CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0V ± 10%, CL = 50pF, TA = -40°C to +85°C
SYMBOL

PARAMETER

CONDITIONS

1

fc

Clock Frequency IM6402

2

fcrystal

Crystal Frequency IM6403

3

Ip~

Pulse Widths CRL. ORR. TBRL

4

Imr

Pulse Width MR

See Timing Diagrams

5

Ids

·Input Data Sat"p Time

(Figures 2.3,4)

6

tdh

I nput Data Hold Time

7

len

Output Enable Time·

RRC

TRC

MIN
D.C.

-

225

50

ns

600

200

ns

75

20

ns

90

40
80

\

PIN17 -

ns

RECEIVER REGISTER
16XCLOCK

I

RECEIVER REGISTER
'6X CLOCK

ns
190

I

J

PIN 40

TRANSMITTER REGISTER,'
16XCLOCK
I

TRANSMITTER REGISTER
'6XCLOCK

I'
NIC

'OR

I

PIN 2

NIC

I

PIN 19

IM6402

~

PIN 22

OR--~~---~--}

I

\.

IM6403

TBRE-~~~---~--

I

-

BUFFERS ARE
ALWAYS ACTIVE

PIN 22

BUFFERS ARE 3·STATE \
WHEN SFD" HIGH
\
\
\

PIN 16

SFO

PIN 2

-..:..::'-=1f----------------.-J
PIN 19

I

\

TBRE

OIVIOE CONTROL
L' DIVIDE B¥ 2048
H' OIl/IDE BY 16

,

I

,

I

PIN 16

SFo----j-------

FIGURE 1. Functional Difference Between IM6402and IM6403 UART (6403 has

On~ehlp

4111 Stage Divider)

as baud rate generators. For example. a color TV. crystal at
3.579545MHz results in a baud rate of 109.2Hz for an easy
teletype interface (Figure 10). A 9600 baud interface may be
implemented using a·2.4576MHzcrystal with the divider setto
divide by 16.

Tlie IM6403 differs from the IM6402· on three Inputs (RRC.
TRC. pin 2) as shown in Figure 1. Two outputs (TBRE. DR) are
not. three-state as on the IM6402. but are always active. The
on-eh!1,l divider and oscillator allow an inexpensive crystal to
be used as a timing source rather than additional circuitry such
8-145

D~DIb

,IM6402/IM6403
I M6402A11M6403A
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
IndustriallM6402AI/03AI .•.••...•... -40°C to +85°C '
Military IM6402AM/03AM ..••.••• ;. -55°C to +125°C
Storage Temperature .•....•........•... -65°C to 150°C
Operating Voltage ••.•...•••••. '••.••• : .• : • ' 4,OV to 11 .OV
Supply Voltage .............................. " +12.0V
Voltage On Any Input or Output Pin •. ,-O.3V to Vee +O.3V

NOTE: Stresses above those listed under "Absolute Maximum
,
Ratings" may cause' permanent device failure. These' are
stress ratings only and functional operation of the devices at
these or any other conditions above those, indicated in the
operation sections of this specification is not implied. Exposure
',to absolute maximum rating conditions for extended periods
, may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 4.0V to 11 .OV, T'A = Industrial or Military
PARAMETER

SYMBOL
1

VIH

Input Voltage High

2

VIL

Input Voltage Low

CONDITIONS'

- I nput 'Leakage! 1]

3

IlL

4'

VOH

Output Voltage High

5

VOL

Output Voltage Low

IOL = OmA

6

IOLK

Output Le,akage

GND<;VOUT<;VCC

7

ICC

Power Supply Current Standby

VIN=GND or VCC

8

ICC

,Power Supply Current IM6402A Dynamic

'fc'=4MHz

Power Supply Current IM6403A Dynamic

fcryslal = 3.58MHz

9

ICC

10

CIN

11

Co

TYp2

MIN

MAX

UNITS

,20% VCC

V

1\0

/LA

V

70% VCC
,

-1.0

GND<;VIN<;VCC
,IOH =OmA

"

V

VCC-O.D1
GND+O.Ol
1.0

'-1.0
5.0

' Input Capacitance!l]
Output Capacitance! 1]

V
/LA

500

/LA

9.0

mA

13.0

mA

, 7.0 '

8.0

pF

8.0

10.0

pF

TVP2

MAXi

UNITS

4.0

MHz

6.0

MHz

NOTE 1: Except IM6403 XTAL input pins Ii.e. pins 17 and 40).
NOTE 2: VCC=5V. TA = 25°C.

A.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 1O.OV ± 5%, CL = 50pF, TA :: Industrial or Military
SYMBOL

'CONDITIONS

PARAMETER

fc

Clock Frequency IM6402A

2

fcrystal '

Crystal Frequency IM6403A

3

tpw

Pulse Widths CRL, DRR, TBRL

4

tm'r

Pulse Width-MR

5

tds

Input Dat.a Setup Time

6

tdh

I nput Data Hold Time

7

ten

' Output Enable Time

MIN
D.C.

1

See Timing Diagrams
' (Figures 2,3.4)

-

100

40

ns

400

200

ns

40

0

ns

30

30
40

ns
70

ns

TIMING DIAGRAMS
CLS1. CLS2. SBS. PI, EPE

-.----,j

SFD OR RRD

STATUS OR
RBRl· RBRB

, FIGURE 2. 'Data Input Cycle

. FIGURE 3. Control Register Load Cycle

8-146

VALID
DATA

FIGURE 4. Status Flag Enable Time
or Data Output Enable Time

U~UIb

IM6402/IM6403
IM6402-1/IM6403-1
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Industrial IM6402-1 1/03-1 I ..••.. :.... -40°C to +85°C
Military IM6402-1 M/03-1 M .......... -55°C to +125°C
Storage Temperature ................... -65°C to+150oC
Operating Voltage ......................... 4.0V to 7.0V
Supply Voltage .....•.........• , 'f ............... +8.0V
Voltage On Any Input or Output Pin .. -O.3V to Vee +O.3V

NOTE: stresses above those listed under· "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections ofth is specification is not implied. Exposure
to absolute maximum rating conditions for extended periodsmay cause device failures.

D·.C. CHARACTERISTICS
TEST CONDITIONS: Vee
SYMBOL

= 5'.0 ± 10%, TA = Industrial.or Military
PARAMETER

CONDITIONS

1

VIH

Input Voltage High

2

VIL

I nput Voltage Low

3

IlL

Input Leakagel!]

GNDO<;VINO<;VCC

4

VOH

Output Voltage High

IOH=·0.2mA

5

VOL

Output Voltage Low

IOL = 2.0mA

6

IOLK

Output Leakage

GNDO<;VOUTO<;VCC

7

ICC

Power Supply Current Standby

VIN=GND or VCC

8

ICC

.Power Supply Current IM6402 Dynamic

fc = 2MHz
fcrystal

MIN

Typ2

MAX

UNITS
V

VCC-2.0
-1.0

0.8

V

1.0

p.A
V

2.4
-1.0
1.0

= 3.58MHz

0.45

V

1.0

p.A

100

p.A

1.9.

mA

9

ICC

Power Supply Current IM6403 Dynamic

5.5

mAo

10

CIN

Input Capacitanc.el!]

7.0

8.0

pF

11

Co

Output Capacitance!1]

8.0

10.0

pF

Typ2

MAX

UNITS

2.0

MHz

3.58

MHz

NOTE 1: Except IM6403 XTAL input pins (i..e. pins 17 and 40).
NOTE 2: VCC = 5V, TA, = 25°C.

A.C. CHARACTERISTICS

TEST CONDITIONS: Vee = 5.0V ± 10%, Cl = 50pF, TA = !ndustrial or Military
SYMBOL

PARAMETER

1

fe

Clock Frequency IM6402

2

fcrystal

Crystal Frequency ·IM6403

3

Ipw

Pulse Widths eRl, DRR,.TBRl

4

Imr

Pulse Width MR

5

Ids

I nput Data Setup Time

6

Idh

Input Data Hold Time

7

len

Output Enable Tfme

CONDITIONS

MIN
D.C.
150

50

ns

See Timing Diagrams

400

200

ns

(Figures 2,3,4)

50

20

ns

60

40
80

8-147

ns
160

ns

U~UIb

IM6402/IM6403

IM6403 FUNCTIONAL PIN DEFINITION
EPE

(Continued)

GND

RRD

CLS2

RBR8

SSS

RBR7

PI

RBR6

CRL

PIN

RBR5
RBR4

TOfU

RBA3

TBR6

RBR2

TaRS

RBRl

TBR4

SYMBOL

DESCRIPTION

14

FE

A high level on FRAMING .ERROR indicates the first stop bit was invalid. FE will
stay active until the next valid character's
stop bit is received.

15

OE

A high level on OVERRUN ERROR indicates the data received flag was not
cleared before the last character was
transferred to the receiver buffer register.
The Error is reset at the next character's
~ bit if ORR has been performed (i.e ..
ORR: active low). .

16

SFD

A high level on STATUS FLAGS DISABLE
forces the outputs PE, FE, OE, DR:TBRE'
toa high impeda"nce state. See Block
Diagram and Figure 4.
.

PE

FE

TBR2

OE

TBRl

SFD

TRO
TRE
TSRl

• DR

TBRE *

RRI

MR
"DIFFERS BETWEEN IM6402 AND IM6403.

FIGURE 5. Pin Configuration

*IM6402 only.

IM6403 FUNCTIONAL PIN DEFINITION
PIN
1
2

SYMBOL
VCC

DESCRIPTION

17

IM6402-RRC The.RECEIVER REGISTER CLOCK is 16X
·IM6403-XTAl the receiver data rate.
or EXT ClK IN

18

.A low level on DATA RECEiVED RESET
clears the data received output (DR), to a
low level.

Positive Power Supply

IM6402·N/C
No Connection
IM6403-Control Divide Control
High: 24 (16) Divider
low: 211 (2048) Divider

3

GND

Ground

4

RflD

A high level on RECEIVER REGISTER
DISABLE forces the 'receiver' holding
register outputs RBR1-RBR8 toa high impedance state.
The contents of the RECEIVER BUFFER
REGISTER appear on these three-state
outputs. Word formats less than 8 characters are right justified to RBR1.

5

RBR8

6

RBR7

See Pin 5 -

RBR8

7

RBR6

See Pin 5 -

RBR8

8

RBR5

See Pin 5 -

RBR8

9

RBR4

See Pin 5 -

RBR8

10

RBR3

See Pin 5 -

RBR8

11

RBR2

See Pin 5 .,.. RBR8

12

RBR1

See Pin 5 -

13

PE

19

DR

A high level on DATA RECEIVED indicates
a character has been received·and·transferred to. the receiver buffer register.

20

RRI

Serial data on RECEIVER REGISTER
INPUT is clocked il)to the receiver
register.

21

MR

A high level on MASTER RESET (MR)
clears PE, FE, OE, DR, TRE and sets TBRE,
TRO high. less than 18 clocks after MR
goes low, TRE returns high. MR does not
clear the receiver buffer register, and is
required after power-up.

22

TBRE

A high level on TRANSMITTER BUFFER
REGISTER EMPTY indicates the transmitter buffer register has transferred its
data tQ the transmitter register and is
ready for new data.

23

A low level on TRANSMITTER BUFFER
REGISTER lOAD transfers data from inputs TBR1-TBR8 into ihe transmitter
buffer register. A low to high transition
on TBRl requests data transfer to the
transmitter register. If the transmitter
register is busy, transfer is automatically
delayed so that the two characters are
transmitted end to en·d. See Figure 2.

RBR8

A high level on PARITY ERROR indicates
that the received parity does not match
parity programmed by control bits. The
output is active until parity matches on a
succeeding character. When parity ,is
inhibited, this output is low.

8-148

24

TRE

A high level on TRANSMITTER REGISTER
EMPTY indicate,S completed transmission
of a character including stop,bits.

25

TRO

Character data, start data and stop bits
appear serially at the TRANSMITTER
REGISTER OUTPUT.

.IM6402/1M6403
IM6403 FUNCTIONAL PIN DEFINITION

IM6403 FUNCTIONAL PIN DEFINITION

(Continued)

(Continued)

PIN

SYMBOL

DESCRIPTION

26

TBRl

• Chara'cter data is loaded into the TRANSMITTER BUFFER REGISTER via· inputs
TBR 1-TBR8. For character formats less
than 8-bits, the TBR8, 7, and 6 Inputs are
ignored corresponding to the programmed word length.

27

TBR2

See Pin 26 - TBRl

28

TBR3

See Pin 26 - TBRl

29

TBR4

See Pin 26 -:- TBRl

30

TBR5

See Pin 26 - TBRl

31

TBR6

See Pin 26 - TBRl

32

TBR7

See Pin 26 - TBRl

. 33

T8R8

See Pin 26 - TBRl

34

CRL

A high level on CONTROL REGISTER
LOAD loads the control register. See
Figure 3.

-

PIN

SYMBOL

DESCRIPTION

35

PI"

A·high level on PARITY INHI81T inhibits
parity generation, parity checking and
forces PE output low.

36

SBS"

A high level on STOP BIT SELECT selects
1.5 stopbitsfora 5 character format and 2
stop bits for other lengths.

37

.CLS2"

These inputs program the CHARACTER
LENGTH SELECTED. (CLSl lowCLS210w
5-bits)(CLSl high CLS21!lw6-bits)(CLSl
low CLS2 high 7-bits) (CLSl high CLS2
high 8·bits)

38

CLS1"

See Pin 37 -

39

EPE"

When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parity. A low level selects odd parity.

40

IM6402-TRC
IM6403-XTAL
or GND

The TRANSMITTER REGISTER CLOCK is
16X the transmit data rate.

CLS2

·See Table 2 (Control Word Function)

TABLE 2. Control Word function
CLS2
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H

H
H

H
H
H

CONTROL WORD
CLS1
PI
EPE
L
L
L
L
L
L
L
L
H
L
L
H
H
X
L.
L
X
H
H
L
L
H
L
L
H
H.
L
H
L
H
H
H
X
H
H
X
L
L
L
L
L
L
L
L
H
·L.
L
H
l
Ii
x
L
H
X
H
L
L
H
L
L
H
H
L
H
L
H
X
H
H
X
H
H

I

SBS
L
H
L
H
L

I-!
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

Ii

x = Don't Care
8·149

. DATA BITS'

5
.5
5
5
5
5
6

6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8

PARITY BIT

STOP BIT(S)

ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED

1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2

D~D[!:'

IM6402/IM6403
TRANSMITTER OPERATION

BEGINNING OF FIRST STOP BlT~ 1--7 1/2 CLOCK CYCLES

The transmitter section accepts parallel data, formats it and
transmits it in' serial form (Figure 6) on the TROutput
terminal.

::;\1

5-a DATA BITS

I

DATA

I I
I

RBR1-B,O E,.PE

~J

ORR

1,1112 OR 2 STOP BITS

~
...L.ILS--..L.."I-L.-.J.........J...---l.l.,.-L-...L.lM--l.SBI~\I

I

DR

LtL
~PARITY

IL-.

I

RRI

FE

----

*IF ENABLED
A

FIGURE 6. Serial Data Format

1--112 CLOCK
CYCLE

FIGURE 8. Receiver Timing (Not to Scale)

Transmitter timing is shown in Figure 7. @ Data is loaded into
the transmitter buffer register from the inputs TBRl through
TBR8 by a logic low on the TBRload input. Valid data must be
present at least tDS prior to and tDH following the rising edge of
TBRL. If words less than 8 bit~ are used, onl.y the least
significant bits are used. The character is .right justified into'
the least significant bit, TBR1. ® T.he rising edge of TBRl
clears TBREmpty. 0 to 1 clock cycles later, data is transferred to
the transmitter register, TREmpty is cleared and transmission
starts. TBREmpty is reset to a logic high. Output data is clocked
by TRClock, which is 16 times the data rate.©A second pulse
on TBRload loads data 'into the transmitter buffer registe'r.
Data transfer to the' transmitter register is delayed until
transmission of the current character is complete,@Data is
automatically transferred to the transmitter register and
transmission of that character begins.

START BIT DETECTION
The receiver uses a 16X clock for timing (see Figure 9.) The
start bit @ could have occurred as much as one clock cycle
before it was detected, as indicated by the shaded portion. The
center of the start bit is defined as clock count 7V2, If. the
receiver clock is a symmetrical square wave, the center of the
start bit will be located within ±1 /2 clock cycle, ±1 /32 bit or
±3.125%, The receiver begins searching forthe next start bit at
. the center of the first stop bit.
CLOCK

COUNT 7 1/2

RRI !NPUT ~

I.

START

I.

" " - - - DEFINED
CENTER OF
START BIT

71/2 CLOCK CYCLES------!
B 1/2 CLOCK CYCLES.......---.j

FIGURE 9. Start Bit Timing

TYPICAL APPLICATION

TBRE

TRE

TRO

A

C

o

END OF
LAST

STOP BIT

Ii]

FIGURE 7. Transmitter Timing (Not to Scale)

. RECEIVER OPERATION
Data is received in serial form at the RI input. When no data is
being received, RI input must remain high, The data is clocked
by the RRClock, which is 16 times the data rate, Receiver
timing is shown in Figure 8,

® During
the first stop bit, data is transferred from the receiver register
to the RBRegister. If the word is less than 8 bits, the unused
f!1ost significant bits will be a logic low. The output character is
right justified to the least significant bit RBR1. A logic high on
OError indicates an overrun which occurs when DReady has
not been cleared before the present character was tranSferred
to the RBRegister. A logic high on PError indicates a parity
error. © 112 clock cycle later, DReady issetto a logic high and
FError is evaluated. A logic high on FError indicates an invalid
stop bit was received, The receiver will not begin searching for
the next start bit until a stop bit is received.

@ A low level on DRReset clears the DReady line,

Microprocessor systems, which are inherently parallel in
nature, often require an asynchronous serial interface, This
. function can be performed easily with the IM6402/03 UART.
Figure 10 shows how the IM6403 can be interfaced to an
IM6100 microcomputer system with the aid of an IM6101
Programmable Interface Element (PIE), The PIE interprets
Input/Output transfer (lOT) instructions from the processor
and generates read and write pulses to the UART. The SENSE
lines on the PIE are also employed to allow the processor to
detect UART status. In particular, the processor must know
when the Receive Buffer Register has accumulated a
cha'racter (DR active), and when the Transmit Buffer Register
can accept another character to be transmitted.
, In this example the characters to be received or transmitted
will be eight bits long (ClS 1 and 2: both HIGH) and transmitted
with no parity (PI:HIGH) and two stop bits (SBS:HIGH), Since
these control bits will· not be changed during operation,
Control Register load (CRl) can be tied high. Remember, since
the IM6402/03 is a CMOS device, all unused inputs should be
committed:
The baud rate at which the transmitter and receiver will
operate is determined by the external crystal and DIVIDE
CONTROL pin onthe IM6403, The internal divider can besetto
reduce the crystal frequency byeither 16 (PIN 2:HIGH) or 2048
(PIN 2:l0W) times. The frequency out of the internal divider
should be 16 times the desired baud rate. To generate 110
baud, this example will use a 3,579545MHz color TV crystal
8·150

IM6402/1M6403
and DIVIDE CONTROL set low. The IM6402 may use different
receive (RRC) and transmit (TRC) clock rates, but requires an
external ,clock gen~rator.

stable on the bus" and to hold TBRL high until the UART
actually transfers the data to it's internal buffer.lfTBRL were
allowed to return loW before TSRE went high, the intended
output data would be overwritten, since the TBR 'is a
transparent latch.

To ensure consistent and correct operation, the IM6402/03
must be reset after power-up. The Master Reset (MR) pin is
active high, and can be driven reliably from a Schmitt trigger
inverter and R-C delay. In this example, the IM6100 is reset
through still another inverter. The Schmitt trigger between the
processor and R-C network is needed to assure that a slow
rising capacitor voltage does not re-trigger RESET. A long reset
pulse after power-up (-1 OOms) is required by the processor to
assure that the on-board crystal oscillator has sufficient time
to start.

Although not shown in this example, the error flags (PE, FE,
OE) could be read by the processor, using the other READ line
from the PIE. Since an IM6403is used, TBRE and DR are not
affected by the STATUS FLAGS DISABLE pin, thus, the three
error flags can be tied to the data b\ls and gated by connecting
SFD to READ2.
I! parity is not inhibited, a parity errorwill cause the PE pin to go
high until the next valid character is received.

The IM6402 supports the processor's bi-directional data bus
quite easily by tying the TBR and RBR buses together. A reaCt
command from the processor will enable the RECEIVER
BUFFER REGISTER onto the bus by using the RECEIVER
REGISTER DISABLE (RRD) pin. A write command from the
processor clocks data from the bus into the TRANSMITTER
BUFFER REGISTER using TBRL. Figure 10 shows a NAND gate
driving TBRL from the WRITE2 pin on the PIE. Thisgate is used
to generate a rising edge to TBRL at the point where data is

A framing error is generated when an expected stop bit is'not
received. FE will stay high after 'the error until the next
complete character's stop bit is received.
The overrun error flag i,s set if a received character is
transferred to the RECEIVER' BUFFER REGISTER when the
previous character has not been read. The OE pin will stay high
until the next received stop bifafter a DRR is performed.

r---------------------------~~------------------~~~t_--~--~~t_--~_\~~+w

D~'DX,,~==================~;=========================~-;==~==~============3
12

IM610D!
~ICROPROCESSOR

IM6101

PIE
INTGNT I--------------IINTGNT
LXMAR

LXMAA

DEVsEL

DEVsEL

~~----------~--~

XTC

SENSE,l

XTC

Cl

Cl

C2

SKP

I----------------j

WRlrE2~--~--~~

C2

SENSE 2

SKP/INT

'iiEADz

I-----....-------'--j

iiiiT
FIGURE 10. 110 Baud Serial.lnterface for IM6100 System

"

8·151

DmtfiDIl

IM6504
'4096 Bit (4096 X 1)
CMOS Static RAM

FEATURES
• Low Standby Power-275p.W maxim'um
• Low Operating Power-38.5mW/MHz maximum
• High Speed-300ns Maximum Access Time
• TTL Compatible Inputs and Outputs
• Three State Outputs
,/' • Data Retention to Vcc = 2V
• On·Chip Address Register
• Military and Industrial Temperature Ranges
. • Harris 6504/Mostek 4104 Compatible

GENERAL DESCRIPTION
The IM6504is a high speed; low power CMOS Static RAM
, organized 4096 words by 1 bit. Input· and three state outputs are TIL compatible anct.allow for direct interface with
common system bus structures. An on-chip address
register simplifies system iriterfacing requirements_
This device is fully compatible with the Harris HM6504, but
is fabricated, with Intersil's selective oxidation, ionplanted, self aligned silicon gate CMOS proce'ss, called
SELOX C, to achieve h'igher reliability and performance •
The standard part operates from 4.5 to 5.5 volts with an access time of 300ns and standby supply current of 50pA
guaranteed over operating temperature range. ,"
Minimum standby qurrent is drawn when chip select line E
is held at either Vccor GND. Data rentention is
guaranteed to a Vec of 2.0V.'
'

BLOCK DIAGRAM

PIN NAMES
AD-Al1
D
Q

AD-

A'

A4

A.

E

A,D

A,1

W

ADDRESS INPUTS
DATA INPUT
DATA OUTPUT
ADDR. STROBE/CHIP ENABLE
WRITE ENABLE

PIN
CONFIGURATIONS

LOGIC SYMBOL
E Vi vee

Vee
A.

011

A4

010

o.
A.
.A2 A3 AS

A6 A7

AS

AD
Al
A2
A"
A4
AS

0

IM8504

A6

07

A7

O.

AS
A9

a

A'D
A11

(outline dwg IN)

ORDERING INFORMATION
PART NO.
IM65041JN
IM6504 MJN
IM6504 CJN

PACKAGE
18 PIN CERDIP
18 PIN CERDIP
18 PIN CERDIP

8-152

TEMP_RANGE
-40·C to +85·C
- 55·C to + 125·C
O'C to +70'C

':" GND

O~OIl"

IM6504
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Vce) ....... ,......................................... + 8V
Input or Output Voltage Applied ................ ,: . . . .. GND - 0.3V to Vcc + 0.3V
Storage Temperature Range ....... : ............ ~ . . . . . . . . . . .. - 65· to + 150·C
Operating Range
Temperature
Industrial ............................................ - 40·C to + 85·C
Military ............................................. -55·C to +125~C.
Voltage,
,
65041.M .......................... ,; ..... : .. '........•.. '......... 4.5·5.5V
NOTE:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
,
damage to the device. Functional operation of the device at these or any other conditions
exceeding those Indicated in the operational sections of this SPecification is not implied.
Exposure to absolute maximum rating conditions for extended periods 'may affect device
reliability.

DC CHARACTERISTICS

.

TEST CONDITIONS:

-

Vcc = 5 OV + 10% TA = Operating Temperature Range,
PARAMETER

SYMBOL

CONDITIONS

TYP.

MAX.

UNIT

VCC-2.O
-0.3

VCC +0.3
0.8

V

-1.0
2.4

1.0

MIN.

-

Logical "1"lnput Voltage

VIH

Logical "0" Input Voltage

Vil

Input Leakage Current
Logical "1" Output Voltage

IllK
VOH

GND s VIN s Vcc
IOH = -1.0mA

Logical "0" Output Voltage'

VOL

IOl = 2.0mA

Output Leakage Current

IOlK

GND s VOUT s Vcc

Iccss

VIN = Vcc
Vcc =3.0V = E1

0.1
0.01

50
25

Iccop

f ~ 1MHz. VIN = VCC
or GND, 10 = 0

5.0

7.0
2.0
7.0
10.0

Standby Supply Current

,
Operating Supply Current
Data Retention Voltage
Input Capacitance
Output Capacitance

/lA "
V

'oA'
-1.0

1.0
/lA
rnA

VOR
5.0
6.0

CIN
COUT

V
pF

Note: Capacitance values guaranteed but not 100% tested.

AC CHARACTERISTICsCD
TEST CONDITIONS:

-

.

Vcc = 5 OV + 10% TA = Operating Temperature Range

LIMITS
PARAMETER

SYMBOL

MIN.

Access Time From EO
'rELaV
Output Disable From E
TEHaZ
E Pulse Width (Pos)
TEHEL
E Pulse Width (Neg)
TELEH
Address Setup
TAVEL
Address Hold
TElAX
Write Enable Pulse Width
TWLWH
Data Setup
TDVWL
Data Hold
TWLDX
Write Enable Read Setup
TWHEL
Write Enable Pulse, Setup
TWLEH
Early Write Pulse Setup
TWLEL
Early Write Pulse Hold
TELWH
'Early Write Data Setup
TDVEL
Early Write Data Hold
TELDX
Data Valid to Write
TaVWL
Read or Write Cycle Time
TELEL,
, ,
I.) AC Test Conditions: Input nse and fall times are 20 ns; Output load

MAX.

UNIT

300
100
120 "
300
20
50
80
0
ns
80
0
200
0
80
0
80
0
420
. .
IS 1 TTL load and 50 pf. All timing measurements are taken at 'Iz Vee .

8·153

D~DI!..

IM8504
ABSOLUTE MAXIMUM RATINGS

Supply Voltages (Vee) . : .. ,.' ........•... ; ••....•....••..••.. '.• : . ~ .•. : ... + SV
Input or Output Voltage Applied .: .•...•.........•...• 'GND - 0.3V to Vee + 0.3V
, Storage Temperature Range .....................•...••...... - 65· to, -+ 150·C
Operating Range'
"
'
Temperature .......•.....•..... , •••...........•......... : .. O~C to + 70·C
Voltage ..................................... ~' •.............. .4.75V to 5.25V
NOTE: Stresses g'reater than those listed under "Absolute Maximum Ratings" may cause per·
manent damage to the device. Functional operation of the device at, these ,or any other
conditions exceeding those Indicated In the operat!onal sections of this. specification Is
not lmplied. Ekposure 'to' absolute maximum rating condltlQns for,extended periods of
, time may affect device reliability.
.
..
'.
',
.

DC CHARACTERISTics'
TEST CONDITIONS:,
Vee = 5.0V± 5%, TA = ,Operating Temperature Range
SYMBOL

PARAMETER

,MAX.

TYP.

MIN.

CONDITIONS

UNIT

,
Logical "1"lnput Voltage
logical "0" Input Voltage '
Input leakage Current
lqgical "1" Output Voltage
logical' "0" Output Voltage'
Output leakage Current
Standby Supply Current
Ope,ratlngSupply Current
..

Input Capacitance
C;>utput Capacitance

VIH
VIL
IlL
VOH
VOL
IOLl(

GND :s VIN :s Vec
-0.4ri1A
IOH
' ".IOL ;"1.6mA
GND :s VIN :s Vec
Itcss
VII'~ == Vcc'
'f
1MHz, VIN
Vce,'
ICCOp
orGND,lO
0,

=

=

=

Vce+ 0.3
O.S
+.10.0

Vee-2.0'
-0.3
-10.0
2.4

,
100

0.4
+10.0
500

5.0
5.0
6.0

7,0
7.0'
10.0 "

-10.0

=

V

pA

,

V

',fAA

..

mA

CIN
GoUT

pF

Note: Capacitance values guaranteed but not 100% tested.

AC CHARACTERISTICSG)
TEST CONDITIONS: , "
,
,',',
Vec = 5.0V± 5%,TA = Operating Temperature Range

..
SYMBOL

PARAMETER
,

,

-

LIMITS
UNIT

MAX•

'

Access Time From E
Output Disable From E
E Pulse Width (Pos)
E Pulse Width.(Neg)
Address Setup
Address Hold
Write Enable Pulse Width
Data SetuD
Data Ho'id
Write Enable Read Setu'p
Write Enable Pulse Setup
, Early Write Pulse Setup
Early Write Pulse Hold'
Early Write Data Setup
Early Write Data Hold
Data Valid 10 Write
Read or Write Cycle Time

'TElQV
TEHQZ
TEHEL
TElEH
TAVEL
TELAX'
nyLWH
TDVWL
'TWLDX
TWHEL,
TWLEH'
TWlEL'
TELWH'
TDVEL'
TELDX
'TQVWL
TELEL

350
100
"

..

1.) AC Test Conditions: Input rise and fall times "are 20 ns; Output load Is

-: "

.

MIN.

, ",'

.""

.. ,

150.
350,
20
50
100
30 :,
100
0
250
0
100 '
30,
100
0
500:

t

, 8.154'

"
.-

.

'ns

.
,

"

,

TTL load and'50 pF. All tlmihg measurements are taken at V2 Vcc,.

','

"

,

..

IM6504
READ CYCLE

TIMING

The failing edge 6f chip enable (E) latches addresses in the
, on-chip register and initiates a read cycle (T 0). Addresses
to be latched must be present one setup time (TAVEL) prior
to and one hold time (TELAX) following the falling edge-of E.
During time T 1 the outputs become valid from the high Z
state. There Is no period of active, but invalid, data ·6n the
bus; Write enable ('iN) must remain high until after time.
T = 2. The read cycle is terminated when E goes high,
disabling the output buffers. '

=

=

t

t

t

REFERET~~~ --_+,--k-----:-,.,...-.---!:2~;---+-

FUNCTION TABLE • READ
TIME
REF

INPUTS

-1
0

1
2
3.
4

W

E
H
~
L'

X
H
.H·
H
X
H

f
H .

~

OUTPUT
Q
Z
Z
V
V
V
Z

~
X
V
X
X
X,

V

EARLY WRITE CYCLE

NOTES
MEMORY INACTIVE
CYCLE BEGINS, ADDRESSES LATCHED
OUTPUT VALID
READ COMPLETE'
MEMORY INACTIVE (SAME AS -1) .
CYCLE ENDS, NEXT CYCLE BEGINS (SAMES AS 0)

TIMING

The falling edge ofE latches addresses ·in the on-Chip
register and initiates an early write cycle. Address, Vii and 0
inputs must be present fortheapproilriate setup and hold
times prior to and following the falling edge of 'E. The 'early
write operation is complete at T = 2, after one minimum
'negative E pulse width (TELEH).
.
'During the early write cycle, output data line Q remains in a
.
. high Impedance state.

-1

tt

t

2

4

3

FUNCTION TABLE· EARLY WRITE
·TIME
REF

. -1
0

1
2
3
4

E
H
~

L

W
X
L
X

y-

X

H

X
L

~

I

INPUTS
A
"
X
V
.X
X
X
V

Q
Z
Z
Z.
Z
Z
Z

D
X,
V
.X
X
X
V

8-155

NOTES
MEMORY INACTIVE
CYCLE BEGINS, ADDRESSES LATCHED
WRITE IN PROGRESS
WRITE COMPLETE
CYCLE ENDS, MEMORY INACTIVE (SAME AS -1)
NEXT CYCLE BEGINS (SAME AS 0)

IMeso.,

Q----------~z~,~------~

TIME.~-+t----:t~-+-t_____-!-t_ _--!:-t--,---+-t,+t_'-+t~

,

REFERENCE

-1

READ ~ MODIFY -

0

1'

, 2

FUNCTION TABLE • READY-MODIFY-WRITE
,
-1
0
1
2
3
4
5
6.

INPUTS

E

"

W

A

H
~
L
L
L

X
H
H
~

X

f

X
,X

H

"""\a..

4

5

6,

WRITE CYCLE

A read - modify - write cycle may be performed If the v.(rlte
portion of the cycle Is controlled by' W, 'and 'E' remains low'
throughout. Data is read normally, with Til held high, address, Inputs latched at ,T =:= 0 andQ ,data, out valid at
T = 1_ A data out valid to write time (TQVWL) must be
observed before W Is brought low to begin the write portion ,
of the cycle.
'

TIME
REF_

3

f
H

POWER DOWN SEQUENCE

D
X
X
X
V

V
X
X
X
X "
X
V

Input Data must be valid a setup time prior to (TDVWL) and a
hold time following (TWLDX) the failing edge of W. At titTle
T 3 W Is returned high, and at T 4 E, is, returned high to,
complete the cycle. The output Q Is disabled by E and goes
to fA high Impedance state an output disable time (TEHQZ)
after E Is returned high (T' = 5).

=

OUTPUT
Q

NOTES,
MEMORY INACTIVE
CYCLE BEGINS ADDRESSES LATCHED
OUTPUT VALID READIMODIFY TIME
- WRITE BEGINS, DATA LATCHED
WRITE IN PROGRESS
WRITE COMPLETE
MEMORY INACTIVE (SAME AS -1)
CYCLE ENDS, NEXT 9YCLE BEGINS (SAME AS 0)

Z
Z
V

-

y'
V

X
X
X
X

=

V
' ,

Z
Z

POWER DOWN SEQUENCE

=

The power down sequence begins at T 0 with E held at a
logic high level 'and all addresseS, D and W established at
valid logic levels. Chip enable E must be high one minimum
positive pulse width (TEHEL) before power-down. At T 1
power supply Vcc may ,be decreased to minimum VCCDR. As
,VCC Is decreased, E must remain within data retention high
logic level threshold limits (VIHDR), andWand Ao-A9, must
remain within VIHDR or VIL limits. Failure
remain within
these limits may cause data loss or,SCR latch-up.

=

to

The same conditions must be met,' in reverse"when returnIng to normal power (T = 2,3).
"

D.

w.

't

t' f

Gl

4.SV'

(%' YCCDR (a.~ z: YCCDR 2: 2.0¥)
5°C to +150°C
Operating Ranges
Temperature
Industrial .................................................. -40°C to +85°C
Military ................................................... -55°C to +125°C
Voltage
IM65X08-1/X18-1 .............................................. 4.5V to 5.5V

DC CHARACTERISTICS
TEST CONDITIONS: Vee =5.0V ±100/0, TA = Operating Temperature Range
PARAMETER

SYMBOL

Logical "1" Input Voltage

VIH

Logical "0" Input Voltage

Vil

Input Leakage

IllK
VOH

CONDITIONS

MIN

-1.0

GND :5 VIN :5 Vee

Logical "0" Output Voltage

Val
Val

Output Leakage

10lK

GND :5 Va :5 Vee

leesB

= Vee
Vee = 3V = E
f = 1MHz, VIN = Vee or GND,
10 = 0

VOH

MAX

UNITS

V

0.8

=0
= -- >- >-

OXO

OX11 -<

IM6512
RAM OX10

vee -

MSEL

STR

OX11

AOR

, -l -

.:.....

ox,

0)(9 -<

OX2

ox.

OX3

OX7 -<

-."

ox.

.-

GNO

ox. .,ox. -

'-

~

vee

MSEL

STR

ox. l - Iox. l - I-

>-'-:- OX2

CS

-

-<

I- oxo
I- OX1

IM6512
RAM OX10

.

OX9.

ox.

f-'

OX2

I-

.DX3

. L.-

ox.

OX6

GNO

ox.

-

-

-

' DX7 - \

-

LXMAR

MSEL
XTe

:--

FIGURE 3. A Typical Microprocessor System

-Typical Microproces$Or System (Figure 3)

ADR

In the· example shown, the.IM6312 RSEL (RAM Select)
output is programmed to go low for addresses '0-255.
jM6512 with ADR = "0" will respond to address~s 0-63
(and 128-191); IM6512 with AD R = "1" will respond to
addresses 64-127 (and 192-255).

ADR should be either tied to logic "0" (GND) or logic "1"
(Vcc).1:he data on this. pin is compared internally with
address data on DX5. If the two match, the chip will
respond to MSEL and CS, otherwise the IM6512 OX line.s
remain high impedance al)d data is unchanged. As a result,
two IM6512 memories can be used with the -IM6100 and
IM6312 without additional components.

ADR
L
I!.
L
H
H
H

t

MSEL@
STR1
L
H

H
L
H
H

X
X
L
H

DX5*
L

FUNCTION
WRITE
READ-MODIFY-WRITE,
READ ONLY
. NO OP~ (HI-Z)
NO OP. (HI-Z)
WRITE
READ-MODIFY-WRITE,
READ ONLY

X = DON'T CARE
I
Nota "1: Addresses are latched on chip by the fallir,g
edge of STR·

FIGURE 4. IM6512 Truth Table

8-168

IM6514
4096 Bit (1K X 4)
CMOS Static RAM
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
.•
•
•

The IM6514 is a high speed,low power CMOS Static RAM
organized 1024 words by 4 bits. Input and three state outputs are TTL compatible and allow for direct interface with
common system bus structures. An on-chip address
register simplifies system inter~acing requirements.

Low Standby Power-275 p.W maximum
Low Operating Power-38.5 mW/MHz maximum
High Speed-300 ns Maximum Access Time
TTL Compatible Inputs and Outputs
.
Three State Outputs Data Retention to Vcc = 2V
On·Chip Address Register
Military and Industrial Temperature Ranges
Harris HM6514 Compatible

This device is fully compatibte with the Harris HM6514, but
is fabricated with Intersil's selective oxidation, ionplanted, self aligned silicon gate CMOS process, called
SELOX C, to achieve higher reliability and performance.
The standard part operates from 4.5 to 5.5 volts with an access time of 300ns arid standby supply current of 50ILA
guaranteed over operating temperature range.

BLOCK DIAGRAM
A9 .
A8
A7

'64 It 64
MEMORY

GATED
ROW

AS
AS

Minimum standby current is.drawn when chip select line E
is held" at Vee and all address, data and control lines are
held at either Vee or GND. Data retention is guaranteed
to a Vee of 2.0V.

CEll

DECODER

ARRAY

. A4~-'-_,.---I

PIN CONFIGURATIONS
010 0
\

010 1

VCC

A6

GATED
COLUMN
DECODER
AND
DATA 110

AS

0lQ2

2

AS

A3

A9

12

E
GND

11
10

W

IM6514
6

13

A7
AS
A9

A3
AO
Al
A2

A2

A1

Vee

A6
AS

A4

0100
0/0,
0 /0 2
E
0 /0 3 GND

AO

0103

A7

A4

0100
0/0,
0102
010 3
W

(outline dwg FN)

E

(outline dwgs IN, PN)

LOGIC SYMBOL

E W VCC
AO-A9

0/00-3
E
W

ADDRESS INPUTS
DATA INPUTS, 0 OUTPUTS
CHIP ENABLE
WRITE ENABLE

AO
Ai

0100

A2
A3

ORDERING INFORMATION

A4

IM6514

010,

A5

PART NO.

IM65141JN
IM65141PN
IM6514MJN
IM6514MFN
IM6514CJN

PACKAGE

18-PIN
18-PIN
18-PIN
18-PIN
18-PIN

CERDIP
PLASTIC
CERDIP
FLATPACK
CERDIP

0/0 2

A6

TEMP. RANGE
-40·C to +85·C
- 40·C to + 85 ·C
-55·C to +125·C
- 55·C to + 125 ·C
O·C to + 70·C

A7
AS

0/0 3

A9

GND

--

8-169

D~DIL

IM6514
ABSOLUTE MAXIMUM RATINGS

Supply Voltage (Vee) ...............•...............•..........•....... + BV
Input or Output Voltage Applied ...................•.. GND - 0.3V to Vee + 0.3V
Storage Temperature Range ................................. - 65· to + 150·C
Operating Range
Temperature
Industrial............................................. -40~C to +B5·C
'Military ........................ : .................... -55·C to + 125·C
Voltage
,
6514 I,M' ........ , .............. ' ............................4.5V to + 5.5V
NOTE:Stresses above those listed under "Absolute Maximum Ratlngs"'may cause permanent
damage to the device. Functional operation of the device at these or any other conditions
exceeding those Indicated in the operational sections of this specification Is not Implied.
Exposure to absolute maximum rating conditions for extended periods oHime may affect
device reliability.

DC CHARACTERISTICS
TEST CONDITIONS:

Vee

PARAMETER

= 5.0V±

10,%,TA

' SYMBOL

= Operating Temperature Range
MIN.

CONDITIONS

TYP.

MAX.

UNIT

Logical "1"lnput Voltage

VIH

Vee-2.O

Logical "0" Input Voltage

~0.3

Vee +0.3
O.B

V

Vil

Input Leakage Current

1.0

JlA

IllK
VOH,

GNDs VIN s Vee

-1.0

Logical "1" Output Voltage
Logical "0" Output Voltage

= -1.0mA

2.4

VOL

IOl = 2.0mA

IOH

Output Leaklilge Current

IOlK

GND s VOUT s Vee

Standby Supply Current

leeSB

VIN
Vee

Operating Supply Current

leeop

Data Retention Voltage
Input CapaCitance
Output Capacitance

V

0.4
1.0

-1.0

= Vee
= 3.0V = E1
f = 1MHz, VIN = Vee
or GND, 10 = 0

0.1
0.01

50
25

5.0

7.0
2.0
7.0
10.0

!lA
mA'

VDR
CIN
COUT

5.0
6.0

V
pF

NOTE: CapaCitance values guaranteed but not 100% tested.

OPERATING CHARACTERISTICS'

Ii]

AC CHARACTERISTICS1
TEST CONDITIONS' Vee == 5.0V± 10%, TA
PARAMETER

= Operating Temperature Range.
MIN.

SYMBOL

Access Time From E
TELaV
Output Disable From E
TEHaZ
Write Enable Output Disable
TWLaZ
E Pulse Width (Pos)
TEHEL
E Pulse Width (Neg)
TELEH
Address Setup
TAVEL
Address Hold
TELAX
Write Enable Pulse Width
TWLWH
Data Setup
TDVWH
Data Hold
TWHDZ
Write Enable Read Setup
TWHEL
Write Enable Pulse Hold
TELWH
Write Enable Pulse Setup
TWLEH
write Data Delay
TWLDV
Data Valid to Write
TaVWL
Read or Write Cycle Time
TELEL
..
1.) Ae Test eondltlons:.lnput rise and fall times are 20 ns; Output load

/

MAX.

UNIT

.300
100
100

120
300
0
50
.,
ns
300
200
0
0
300
300
100
0
420
. .
IS 1 TIL load and 50 pf. All tlmlOg measurements are taken at 'I. Vee .

B·170

D~OIL

IM6514CABSOLUTE MAXIMUM RATINGS
Supply Voltages (Vce)· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 8V
Input or Output Voltage Applied ...................... GND - 0.3V toVcc + 0.3V
Storage Temperature Range .................................. - 65· to + 150·C
Operating Range
.
,
Temperature ....................... ." ....................... '" O·C to + 70·C
Voltage .........'.......................................... 4.75V to 5.25V
NOTE: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other
conditions exceeding those indicated.in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0V ± 5%, TA = Operating Temperature Range

,

PARAMETER

SYMBOL

CONDITIONS

Logical "1" Input Voltage

V1H

Logical "0" Input Voltage

VIL

Input Leakage Current
Logical "1" Output Voltage

IllK
V0H

GNDsVINsVee
IOH= -0.4mA

Logical. "0" Output Voltage

VOL

IOL=1.!imA

Output Leakage Current

IOlK

GNDsVINSVee

Standby Supply Current

leess

VIN=Vee

Operating Supply Current

leeop

f = 1MHz, VIN =V cc
or GND, 10 '=0

Input Capacitance

CIN
COUT

Output Capacitance

MAX

UNITS

Vee- 2.O
-;-0.3

Vee +0.3
0.8

V

-10.0

+10.0

·/LA

MIN

TYP

2.4

V
0.4

-10.0

+10.0
500

100

/LA
rnA

5.0 .

7.0

5.0

7.0

6.0

10.0

pF

NOTE: Capacitance values guaranteed but not 100% tested .

.

.

.AC CHARACTERISTICS
TEST-CONDITIONS: vcc = 5..0V ± 5%, CL = 50pF, TA = Operating Temperature Range
PARAMETER
. Access Time from E .
OlJtput Disable from E
Write Enable Output Disable
E Pulse Width (Pos)
E Pulse Width (Neg)
Address Setup
Address Hold
Write Enable Pulse Width
Data Setup.
Data Hold
Write Enable Read Setup
Write Enable Pulse Hold
. Write Enable Pulse Setup
Write Data Delay
Data Valid to Write
Read or Write Cycle Time

SYMBOL
TELOV
TEHOZ
TWLOZ
TEHEL
TELEH
TAVEL
TELAX
TWLWH
TDVWH
TWHDZ
TWHEL
TELWH
TWLEH
TWLDV
TOVWL
TELEl

. MAX
350
100
100

MIN

150
350
20
50
350
250
0
0
350
300·
100
0
500

.,

UNITS

-ns

1.) AC Test Conditions: Input rise and fall times are 20 ns; Output load is 1 TIL load and 50 pf. All timing measurements are taken at V. Vee.
8-171

.

O~OlL

IM8514
READ CYCLE

READ CYCLE TIII!IING

The falling edge of chip enable (E) latches addresses In the
on-chip reglstElr and initiates a read 6ycle (T = 0). Addresses
to be latched must be present one setup time (TAVEL) prior
to and one hold time (TELAX) following the failing edge of E.
During time T = 1 the outputs become valid frorn the high Z '
s_tate. There is no period of active, but invalid, ,data on the
bus. Write enable (W) must remain high until after time
T = 2. The read cycle is terminated when E goes high,
disabling the output buffers. '

E
,A

FUNCTION TABLE • READ_
TIME
REF

INPUTS
E
H

-1

0
1

A
X

'\.:.

H

L

H

V
,X

H

H

~

..r

?
3
4

OUTPUT

W
X

NOTES

Q
-Z

MEMORY INACTIVE

Z

CYCLE BEGINS, ADDRESSES LATCHED
OUTPUT VALID

X

V
V

X

X

V

MEMORY INACTIVE (SAME AS • 1)

H

V

Z

CYCLE ENDS, NEXT CYCLE

READ COMPLETE

BEGINS (SAME AS 0)

WRITE CYCLE

WRITE CYCLE T,IMING

The falling edge of, E latches addresses in the ori-chlp
register and initiates a write cycle (T = 0). Write begins whenW goes low (T 1) and ends when W or E goes high (T 2).
Data to be written must be valid one setup time be (ore
(TDVWH) the rising edge of W or-E, but not before one data
delay time (TWLDV) after the falling edge of W (T = 1).

=

[iJ
:

=

~rite

At
cycle termination (T = 3), data liries become high Z
one hold time (TWH DZ) after the rising edge of W or one hold
time (TEHDZ)after1he rising edge of E. The next write cycle
'
, begins at T = 4.

REFERET~~~ --'_-'-!-...:.,..Ll----'----'---'---,..J!'-,FUNCTION TABLE • WRITE;
TIME
REF

E

-1

H

INPUTS
'~

0
'1,

2
3
4

,

W
X

A
X

DQ
Z

NOTES

"

MEMORY INACTIVE

X

V

Z

CYCLE,BEGINS, ADDRESSES LATCHED

L

""\L

X

Z

WRITE IN PROGRESS

L

f

X

V

X

Z

WRITE COMPLETE
CYCLE ENDS, OUTPUTS HIGH Z ",

V

Z

NEXT CYCLE BEGINS

H

'""\c...

H
X

8·172

O~OI!..

IM6514
READ-MODIFY-WRITE CYCLE TIMIr.,tG

t

TIME

t

t

t

t

t t

t

REFERENCE~--~-_71------~O~--------~1~------~--~2~----~------~3~------~4~~5----~6~--

READ -

MODIFY -

WRITE CYCLE

A read - modify - write cycle may be performed if the write
portion of the cycle is controlled by Wand E remains low
throughout. Data is read normally, with W held high, addresses latched at T = 0 and data out v,alid at T = 1_ A data
out valid to write time (TQVWL) must be observed before W
is brought low to begin the write cycle. One write output
disable time (TWLQZ) after W is low, the data lines return to

"

a high-Z statE;! and new data to be written Into the address
may placed on the data bus. Data to be written must be valid
one setup time before (TDVWH) and one hold time after
(TWHDZ) the rising edge of W (T = 3). The output buffers are
latched to a high-Z state by the rising edge of W, so that
when input data.is removed the bus remains high-Z until the
'
next cycle.

FUNCTION TABLE· READY-MODIFY-WRITE
TIME
REF.
1

W
X
H
H

H

0

"'""\a...

1

L
L
L

"'""\a...
J

...F

X

H

X
H

2
3
4
5
6

OUTPUT

INPUTS

E

~

A
X

0

Q

X

V
X
X
X
X
X
V

X

Z
Z
V
Z
Z
Z

X
X
V
X
X
X

Z;
Z

POWER DOWN SEQUENCE

NQTES
MEMORY INACTIVE
CYCLE BEGINS, ADDRESSES LATCHED
OUTPUT VALID, READ/MODIFY TIME
WRITE BEGINS, OUTPUT HIGH Z
WRITE IN PROGRESS
WRITE COMPLETE
MEMORY INACTIVE (SAME AS -1)
CYCLE ENDS, NEXT CYCLE BEGINS (SAME
AS 0)

POWER DOWN TIMING

=

The power qown sequence begins at T 0 with E held at a
logic high level and all addresses, W, established at valid
logic levels. Chip enable E must be high one minimum
positive pulse width (TEHEL) before power-down. At T 1
power supply Vee may be decreased to minimumVeeDR. As
Vee is decreased, E must remain within data retention high
logic level threshold limits (VIHDR), and Wand AO-Ag, must
remain within VIHDR or VIL limits. Failure to remain within
these limits may cause data loss or SCR latch-up.

=

The same conditions must be met, in reverse, when returning to normal power (t 2,3).

=

w.
TIME REF -----'--:!---~------------~----!:_---

ill
®
@

VceDn (5.5V '" VCCDR ",.2.0V)
VIH (Vee + 0.3V '" VIH ., Vee
VIL (0.8 '" VIL ,,'GND-0:3V)

®

~IHDR (Vee +

o
8-173

4.5V

~ 2.0V)

0.3V" VIHDR '" Vee -2.0V '" 2.0V)

D~Dlb

IM65X51/1M65 X 61
1024 (256x4) Bit
High Spet!'d CMOS RAM

FEATURES
• Low Standby Power: 55!J.W Maximum
• Low Operating Power: 10mW/MHz Maximum
• High Speed Operation
• High Noise Immunity
• Data Retention to VCC = 2.0V
• TTL Compatible Inputs and Outputs
• Three State Outputs
• High Output Drive: 2 TTL Loads
• On-Chip Address Registers
'
• Completely Static and Synchronous
• Operating Voltage Range 4.5V t010.5V (A version)
• Military and Industrial Temperature Ranges

GENERAL DESCRIPTION
,

'

The IM65X51 and IM65X61 are high speed, low power CMOS '
static RAMs organized 256 words by 4 bits. Inputs and
outputs are TTL compatible and allow for direct interface
with common system bus architectures. On-Chip address
registers simplify system interfacing requirements.
These, devices are fully compatible with the industry
standard 6551/61 CMOS 256x~ RAMs but are fabricated in
Selox C, a ,high density CMOS process which utilizes
selective oxidation to achieve high reliability and
performance.
The standard parts operate from 4.5 to 5.5 volts, with access
times of 300 ns and ,standby supply currents of 1OJ.La
guaranteed over operating temperature range. Access times
of 220 ns are offered in "-1" versions, and 4.5 to 10.5 volt
operating ranges are available in "A" versions.
Minimum standby current is drawn when E is held at Vee and
all address, data and control lines are held at either Vee or
GND, Data retention is guaranteed to a Vee of 2.0V.

BLOCK DIAGRAM

PIN
CONFIGURATION
I

I
OUT_I

DATA IN-+----...J......----I_____

PUT :'
I
I

IM65X51

I

---'

A3

Vee

Az

A4

A,

iN
5,

AO
A6

Ei
E2

A7

004

GNO

01 4
003

AS
"1" HIGH-z
OUTPUT

DI,
00,

01 3
oOz

OIZ
TOP VIEW

(outline dwg Jr::, PF) ,
IM65X61

I
I

---'

S,
S2'

E,

"'" HIGH-z
OUTPUT

'NO.'
IM65X51

II, "'UsTRIAL
sTO
HI SPEED
'5V
5V
IJF
-1IJF
IPF
-1 IPF
-1IJN
IJN
IPN
-1IPN

Cerdi JF
Plastic PF
IM65X61' Cerdi IN
PlastiC PN
Flatpak
*11 8838 ro'cessin is desired add 1883B to order number.

Vec

Az

A4

A,

iN

Ao

51

AS

1/0 4

A6

ORDERING INFORMATION
COMMERCIAL
sTO
5V
CJF
CPF
CJN
CPN

A3

sTO
10V
AIJF
AIPF
AIJN
AIPN

MILITARY·
sTD
HI SPEED
5V
5V
MJF
-1 MJF

sTO
10V
AMJF

MJN

AMJN

MFN

8-174

-1 MJN

AMFN

A7

I/Oz

GNO

,110,

S2

Ei
TOP VIEW

(outline dwg JN, PN)
Pin 1 is deSignated by
a dot or a ·notch.

IM65X51/IM65X61
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................................................ t8.0V.
Input or Output Voltage Supplied ........................ GND -q.3V to Vee +0.3V
Storage Temperature Range .................................... -65° C to +150° C
. Operating Range
Temperature
Industrial .................................................. ~40°C to -t-85°C
Military ........................................ ·........... -55°C to +125°C
Voltage
IM65X511X61 I,M
........................................... 4.5V to 5.5V

DC CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0V ±10%, TA = Operating Temperature Range
PARAMETER

SYMBOL

CONDITIONS

Logical "1" Input Voltage

VIH

Logi-al "0" Input Voltage

VIL

Logical "1" Output Voltage

VOH1

Logical "0" Output Voltage

VOL1

10L = 3.2mA

Output Leakage

10LK

GND:SVo:SVee

Standby Supply Current

leess

VIN = Vee

~t Leakage

TYP

MAX

UNITS

V

0.8

ilL
I

leeop

-1.0

GND:"VIN:SVee
10H = -{l.4mA

Vee
Operating Supply Current

MIN

Vee-2.0

I'A
V

0.45
-1.0

= 3V = E1

f = 1 MHz, VIN

or GND, 10 =

1.0

2.(
1.0
1

10

0.1

10

= Vee

I'A

2

mA

a

Input Capacitance

CIN

5.0

7.0

Output Capacitance

Co

6.0

10.0

pF

AC CHARACTERISTICS
TEST CONDITIONS: Vee

= 5.0V ±10%,

PARAMETER

CL

= 50pF, TA = Operating Temperature

Range

IM65X51/X61 I,M
MIN
MAX

SYMBOL

Access -rime From E 1
Output Enable Time

TE1LQV
. TSLQV

Output Disable Time .

TSHQZ

E1 Pulse Width (Positive)

TE1HE1l!

100

E1 Pulse Width (Negative)
W Pulse Width (Negative)

TE1LE1H
TWLWH

300
300

Address Setup Time

TAVE1L

0

Address Hold Time

TE1LAX

60

Data Seiup Time

TDVE1H

Data Hold Time

TE1HDX

150
0

UNITS

300
150
150

8-175

ns

IM65X51-1/IM65X61·1
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................................................ +8.0V
Input or Output Voltage Applied •..................... ~ GND -o.3V to Vcc' +0.3V
Storage Temperature Range ........ ; ............................ : -65°Cto +150°C
Operating Range
Temperature
Industrial ............................................... , ... -40°C to +85°C
Military ................................................... -55°C to +125°C .
Voltage
IM65X51-1/X61-11, "1M ......................................... 4.5V to 5.5V

DC CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0V ±10%, TA ~ Operating Temperature Range
PARAMETER

SYMBOL

Logical "1" Input Voltage

VIH

Volt~ge

VIL

Logical"O" Input

MIN

MAX

UNITS

V

0.8

Input Leakage

IlL

GND:5VIN:5VCC

-1.0

VOH1

.2.4

Logical "0" Output Voltage

VOL1

= -o.4mA
IOL = 3.2mA

Output Leakage

IOLK

GND:5Vo:5Vcc

-1.0

Standby Supply Current

leess
leeop

TYP

Vce-2.0

Logical "1" Output Voltage

Operating Supply Current

E:J

CONDITIONS

loA

1.0

fJ.A

V

0.45
1.0

= Vee
Vee = 3V = E1
f = 1 MHz. VIN = Vcc
or GND, 10 = 0

_VIN

1

10

0.1

10

fJ.A

2
"

mA

,

Input Capacitance

CIN

5.0

7.0.

Output Capacitance

Co

6.0

10.0

pF

AC CHARACTERISTICS
TEST CONDITIONS, Vee

= 5.0V ±1O%, C, = 50pF, TA =O""U"

T,mpe","" R""
1N\65X51-1/X61-11. -1M

PARAMETER

SYMBOL

MIN.

Access Time From E
Output Enable Time

TE1LQV

MAX
220

TSLQV

130

Output Disable Time

TSHQZ

E1 Pulse Width (Positive)

TE1HEL

100

E1 'Pulse Width (Negative)

220

W Pulse Width (Negative)

TE1LEH
TWLWH

Address Setup Time

TAVE1L

Address Hold Time

TE1LAX

0
60

Data Setup Time

TDVE1H

100

Data Hold Time

TE1HDX

0

UNITS

130

220

8-.176

,
ns

IM65X51 A/IM65X61 A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...................................•................ : ..... +12.0V
Input or Output Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . .. GND -o.3V to VCC +0.3V
Storage Temperature Range ..................................... -£5° C to +'150° C
Operating Range
Temperature
Industrial., ................................................ -40°C to +85°C
Military ........................•.......................•.. -55°C to +125°C
Voltage
IM65X51A, IM65X61A .........................................· 4.5V to 10.5V

DC CHARACTERISTICS
TEST CONDITIONS: Vee

= 4.5V to 10.5V, TA = Operating Temperature Range

,

PARAMETER

SYMBOL

Logical "1" Input Voltage

VIH

Logical "0" Input Voltage

Vil

CONDITIONS

MIN

TYP

MAX

lriput Leakage

III

GND~VIN~Vee

VOH

lOUT = 0

Logical "0" Output Voltage

VOL

lOUT - 0

Output Leakage

10lK

GND~Vo~Vee

leess

VIN = Vee

5.0

500

Vee = 3.0V = El

0.1

50

Operating Supply Current

-1.0

1.0

CIN
Co

V

GND +0.01

\

-1.0

1.0

10

or GND, 10 = 0
Input Capacitance

J1.A

Vee -0,01

f = 1 MHz, VIN = Vee

leeop

Output Capacitance

V

0.8

Logical"1" Output Voltage

Standby' Supply Current

UNITS

70% Vee

I

5.0

7.0

6.0

10.0

J1.A
rnA

-

pF

AC CHARACTERISTICS
TEST CONDITIONS: Vee = 10V ± 5%, Cl = 50pF, TA = Operating Temperature Range

PARAMETER
Acc'ess Time From El .
Output Enable Time
Output Disable Time
El Pulse Width (Positive)
El Pulse Width (Negative)
W Pulse Width (Negative)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time ,',

IM65X51A1X61A I,M
MIN
MAX
235
120
120
80
145
160
35
80
80
40

SYMBOL
TE1LQV
TSLQV
TSHQV
TE1HE1L
TE1LE1H
TWLWH
TAVE1L
TEl LAX
TDVE1H
TE1HDX

.

8·177 .

\

UNITS

ns

,

IM65X51 C/IM65X61 C
.ABSOLUTE MAXIMUM RATINGS'
Supply Voltage ...........................................•....... ... . . . .. 8;OV:
Input or Output Voltage Applied ., ...... 1•••••••••••••••••• GND'-O.3VtoVCC+0.3V
'Storage Temperature Range ..................................... -65°Cto+150°C
Operating Range
'
,
Temperature
Commercial, .. '...,............................................. O°C to 75°C
Voltage
IM65X51/X61C ........... , ...... : .............. :'............ 4.75V to 5.25V

DC CHARACTERISTICS
. TEST CONDITIONS:, Vee = 5,OV ± 5%, TA = Operating Temperature Range
PARAMETER

SYMBOL

Logical "1" Input Voltage

VIH

Logical :'0" Input Voltage

VIL

CONDITIONS

Input Leakage

IlL

GND:5VIN:5Vee

VOHl
Vall

IOH = -D.2mA
10L = 1.6mA

Output Leakage

10LK

GND:5Vo:5Vce

Standby Supply Current

Icess

VIN

Operating Supply Current

lecop

Ouiput Capacitance

-1,0 '

UNITS

MAX

V

1.0

/-LA

2.4 '
0.45
-1.0

= Vee

I

,v

1.0
10

f = 1 MHz, ViN = Vee

orGND, 10
·,Input Capacitance

TYP

0.8

Logical "1" Output Voltage
Logical "0" Output Voltage

,MIN,

Vee-2,0

100

/-LA,

4,0

mA

:= 0

CIN

5.0

7.0

Co

6,0

10.0

pF

AC CHARACTERISTICS
TEST CONDITIONS: Vee ~ 5.0V ± 5%, CL =50pF, TA = Operating Temperature Range

PARAMETER
Access Time From El
Output Enable Time
, Output Disable Time
El Pulse Width (Positive) .
El Pulse Width (Negative)
W Pulse Width ,(Negative)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time

SYMBOL
TE,LOV
TSLOV
TSHOZ
TE1HE1L
TE1LE1H
TWLWH
TAVE1L
TEl LAX
TDVE1H
TE1HDX

MIN

150
350
350
20
70
170
0

8-178

I M65X51 C/X61 C
MAX
350
180
180

1\

UNITS

ns '

IM65X!51/IM65X61
READ MODE OPERATION

D~DIL
READ CYCLE TIMING

In a typical READ operation the address
lines are latched by the falling edge' of
strobe in'put E1. If the chip has been selected. i.e.81 and 52 (65X51 only) are low •. data
becomes valid an access time (TE1 LQV)
after the falling edge of E1. Data is latched
into output registers by rising El and remains valid until the next cycle or' until a
chip select (SI or S2) is returned high.
Address and E2 information is edge triggered and must be valid a setup time
(TAVE1U before and a hold time (TE1LAX)
after the falling edge of E1, "
. 81. 52 and Ware' level sensitive and may
occur after E1 transitions without affecting
access time.

1HE1

E1LE1H

E1
AO-Ag
E2*

s,. 82"
Q

W

t

t

TIME
REFERENCE

-1

t

t

2

0

t

t

3

4

FUNCTION TABLE. READ
TIME REF.
1
0
1
2
3
4

E1
H
'"'L-

L
L
~

H

A
X
V
X
X
X
X

INPUTS
E2'
X
L
X
X
X
X

OUTPUTS

S

W

Q

H
X
L
L
L
H

X

Z
Z
X
V
V
Z.

H
H
H
H
H

'65X51 only

WRITE MODE OPERATION

' NOTES
'Memory Inactive, output high Z.
Addresses and E2 latched, output still high Z.
Output enabled and active.
OutQut valid.
Output latched and valid, memory inactive.
Output high Z. Ready for next cycle.
"65X61 only

WRITE CYCLE TIMING

For a WRITE operation addresses and E2
are latched by El as in a READ o'peration.
Data is written when strobe tE:l), chip
selects (81. 82) and write (Iii) are low.
WRITE operation ends when one of these
lines returns high, Minimum write pulse
requirements are specified for E1 as
TE1LE1H and for 81.82. W as TWLWH.
Data must be valid a setup time (TDVE1H)
before and a hold time (TE1HDX) afterthe
. rising edge of E1.
Note: Transitions on strobe line El when
addresses are at indeterminate levels
such as the transition to power down or
standby mode may cause change of
address or loss of data. When in either
mode care' must be taken to maintain El
at Vec level:

t

TIME

t

t

REFERENCE--------_~1------~O--------~~--------~2---------'~3-

FUNCTION TABLE. WRITE
TIME REF.
1
0
1
2
3

E1
H
'L
L
L
H

A
X
V
X

X
X

INPUTS
E2'
S
X
H
L
H
X
'L
X
L
X
H

OUTPUTS

W
X
X
'L

-..rH

Q

0
X

Z
Z
Z
Z
Z

X

X
V
X

'65X51 only
8-179

NOTES
Memory Inactive. Outputs high Z.
Addresses and E2 latched.
Write operation begins.
Write operation ends.
Outputs high Z. Ready for next cycle.
"65X61 only

IM6653/1M6654
409.6 Bit CMOS
UV ErasablePRO,M
GENERAL DESCRIPTION

FEATURES,
• Orga!1lzatlon - IM6653: 1024)( 4
IM6654: 512 x ~
• Low Power - 770p.W Maximum Staridby
• High Speed
- 300ns 10V Access Time for IM6653154 ~I
- 45.0ns 5V Access Time for IM6653154·11
• Single + 5Vsupply operation
.
• UV erasable
• $ynchronous operation for'low power
dissipation
• Three·state outputs and chip select for easy
system expansion
. .
• Full -55°C to +125°C MIL range'devices'IM6653/54 M, IM6653A164A M

The Intersll IM6653 and IM6654 are fully decoded 4096 bit
CMOS electrically programmable ROMs (EPROMs)
fabricated with' Intersil's ,advanced CMOS processing
technology. In all static states these devices exhibit the
microwatt power dissipation typical of CMOS. Inputs and
three-state outputs are TIL compatible 'and allow for direct
interface with common system bus structures. On-chip address registers and chip select functions simplify system .
interfacing requirements.
The IM6653 and IM6654 are specifically designed for program development applications where rapid. turn-around
for program changes is required. The devices may be erased by exposing their transparent lids to ultra-violet light,
and then re-programmed.

BLOCK DIAGRAM

PIN CONFIGURATION
(outline dwg JGIW)
PROGRAM

V'"f

As

W
0

0

E1

U

W

'0

><

64 x 64
ARRAY

A4

At
S

A3

E1

As
Dl

a::

A1

•••
•
•••
D40R
D8

I~

a.

I~

0

-

t

A2

VDO

A1

PROGRAM

Q3
Q3
Q2
Q2
Q1

S

Vce
As
E2

S

ORDERING INFORMATION

E1

VDD
24 PIN
PACKAGE
CERDIP
JG
(FRIT SEAL)

SELECTlONfTEMPERATURE RANGE
INDUSTRIAL
MILITARY
STD 5V HI SPEED 5V STD 10V STD 5V STD 10V
IJG
-11 JG
AIJG
MJG
AMJG

PROGRAM

Q1

Qs
Qs
Q4

Q3

8-180

O~OIL

IM665311M6654
ABSOLUTE MAXIMUM RATINGS
Supply Voltages

, ~~~ ';'·v ~~ ...... : ...... : .... : : : .... : : :.: : . : : . : :: : : . : : : ........ : : : . : : . : : : : : : : . : :.. : ::~~
Input or Output Voltage Supplied ...................... GND - 0.3V to Voo + 0.3V
Storage Temperature Range ............................... - 65·C to + 150·C
Operating Range
Temperature
Industrial ............................................ .:.. 40·C to + 85·C
Military ....................... : ..................... -55·C to + 125·C
Voltage
6653/54 I, -11 ................................................ 4.5 - 5.5
6653/54 M .................................................... 4.5 - 5.5
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifica· .
tions is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vee = Voo = 5V ± 10%, TA = Operating Temperature Range
IM6653/541, ·11,M
PARAMETER
Logical "1" Input Voltage

SYMBOL

CONDITIONS

MIN

VIH

E1,S
Address Pins

Voo-2.0

VIH
Logical "0" Input Voltage
Input Leakage
. Logical "1" Output Voltage

MAX

2.7

V

Vil

0.8

II

GND~VIN~VOO

-1.0

VoH2
VOH1

IOUT=O
IOH= -0.2mA

Vee- 0.01
2.4

VOl2
VOL1

IOUT=O
IOl=2.0mA

Output Leakage

(OlK'

GND~Vo~Vee

Standby Supply Current

looss

VIN =Voo
VIN=VOO
f=1 MHz

100

Note 1

7.0

Note 1

10.0

Logical "1" Output Voltage
Logical "0" Output Voltage
Logical "0" Output Voltage

Icc
Operating Supply Current
Input Capacitance
Output Capacitance

looop
CI

UNITS

Co

1.0

/LA

GND+0.01

V

0.45
-1.0

1.0
/LA

40
mA

6

pF

Note 1: These parameters guaranteed but not 100% tested.

AC -CHARACTERISTICS
TEST CONDITIONS: Vee = Voo = 5V ± 10%, Cl = 50pf, TA = Operating Temperature Range
IM6653/54·11
PARAMETER

SYMBOL

MIN

MAX

IM6653/54I
MIN

MAX

IIM6653/54 M
M!N

600

110

140

150

110

140

450

Output Enable Time

TSLOV

Output Disable Time

TE 1HOZ

E1 Pulse Width (Positive)

TE1HE1L

130

150

150

E1 Pulse Width (Negative)

TE1LE1H

450

550

600

TAVE1 L
TE 1LAX

0

0

Address Hold Time

80.

100

100

Chip Enable Setup Time (6654)

TE2 VE1L

0

0

0

Chip Enable Hold Time (6654)

TE1LE2X

80

100

100

8·181

UNITS

150

0

Address Setup Time

MAX

550

TE1LOV

Access Time From E1

ns .

O~OIl

IM6653A/IM6654A
ABSOLUTE MAXIMUM RATINGS
Supply Voltages '
voo ....................................................... '............. + 11,OV
Vcc= voo .................................... ; ................ '... .' ..... +11.0V
Input or Output Voltage Supplied" ................•.......GND - 0.3V to Voo + 0.3V
Storage Temperature Range .................................... - 65'C to + 150'C
Operating Range
Temperature
Industrial .....................•....... '..................... - 40'C to 85 ~C
Military, ...............................'..•.... , ........ , ... -55'C to + 125'C
Voltage ,
6653/54 AI, AM ......... , ......... , ............•..... , ............ 4.5 to 10.5V

*

NOTE: Stresses ,above those listed under Absolute Maximum Ratings m,ay cause permanent
damage to the deVice. These are stress ratings only, and functional operation of the device at
these or any other conditions above those Indicated in the operational sections of the speclfica·
'tions,is not Implied, Exposure to absolute maximum rating conditions for extended periods
'
may affect ,device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vcc=Voo=4.5V to 10.5V, TA = Operational Temperature Rarige

, PARAMETER
Logical "1" Input Voltage'
Logical "O"lnput Voltage
Input Leakage
Logical '~1" Output Voltage
Logical "0" Output Voltage
Output Leakage
Standby Supply Current
Operating Supply Current
Input Capacitance
Output Capacitance

m
.•

SYMBOL
VIH
VIH
Vil

CONDITIONS
El ,S
Address Pins

II
VOH
VOL
10lK
IOOSB
Icc
looop
CI
Co

GND:sVIN :SVoo
10ur=0
10UT=0
GND:sVo:sVcc
VIN=VOO
VIN=VOO
f=1 MHz
Note 1
Note 1

IM6653/54AI, AM
' MAX
MIN

UNITS

Voo-2.0
Voo-2.0

V
0.8
1.0

-1.0

pA

Vcc- 0.01
-1.0

.

V

GND+0.01
1.0
100
40
12
7.0
10.0

,;.A
mA
pF
"

Note 1: Thesep,aramet~rs guaranteed but not 100% tested .

,

'

'

AC CHARACTERISTICS
TEST CONDITIONS:v
cc = Voo = 10V ± 50/0, Cl = 50pf, TA = Operating Temperature Range
,
IM6653/54 AI
PARAMETER
Access Time From El
Output Enable Tim~
Output Disable Time
El Pulse Width (Positive)
El Pulse Width (Negative) ,
Address Setup Time
, Address Hold Time
Chip Enable Setup Time (6654)
Chip Enable Hold Time (6654)

SYMBOL
TE 1LOV
TSLOV
'TE 1HOZ
TE1HE1L
TE1LE1H
TAVEiL
TE 1LAX
TE2VE 1L
TE 1LE2X

MIN

125
300
0
60
0
60
8-182

MAX
300
60
" 60

IM6653/54 AM
MIN

125
350
0
60
0
60

MAX
,350
70
70

UNITS

ns

IM665311M6654
PIN ASSIGNMENTS
PIN

ACTIVE
LEVEL

SYMBOL
AO·A7,Aa

1·8,23
9·11,13·17

-

00.0 7
0 0.03

12
18
19
20
21
22

~

Data Out lines, 6654

-

Data Out lines, 6653

GND

-

Program

-

V DD
El
S

,
24

,

DESCRIPTION

Address Li nes

Programming pulse input
Chip V+ supply, normally tied to Vee

L

Strobe line, latches both address lines and, for 6654, Chip enable E2

L

Chip select line, must be low for valid data out

Ag

-

Additional address line for 6653

E2

L

Chip enable line, latched by Chip enable El on 6654

-

Output buffer

Vee

+ V Supply

READ MODE OPERATION

READ CYCLE TIMING

In a typical READ operation address lines and chip enable
E2 "are latched by the falling edge of <;hip ena,ble El (T = 0).
Valid data appears at the outputs one access time (TELOV)
later, provided level·sensitive chip select line S is low
(T = 3). Data remains valid until either El or S returns to a
high level (T = 4). Outputs are then forced to a high·Z state.
Address lines and E2 must be valid one setup time before
(TAVEL), and one hold time after (TELAX), the fallingedge
of El starting the read cycle. Before becoming valid, 0 out·
put lines become active (T = 2). The 0 output lines return to
a high·Z state one output disable time (TEl HOZ) after any'
rising edge on E1 or S.
The program line remains high throughout the READ cycle.
Chip enable line El must remain high one minimum
positrve pulse width (TEHEL) before the next cycle can
begin.
*As IM66S3 only. E2 IM6654 only-

FUNCTION TABLE
TIME

INPUTS.

REF

E1 .

-1
0
1
2
3
4
5

H

NOTES

OUTPUTS

E2"

S

X

X

A
X

~

L

X

L

X

X

L

X

L

-F

X
X

H

X

Q

,

ZI

DEVICE INACTIVE

V

Z

CYCLE BEGINS; ADDRESSES, E2 LATCHED"

X

Z

INTERNAL OPERATIONS ONLY

L

X

A

L

X

V

OUTPUTS ACTIVE UNDER CONTROL OF E1, S
OUTPUTS VALID AFTER ACCESS TIME

L
X

X

V

READ COMPLETE

X

Z

CYCLE ENDS (SAME AS ·1)

8·183

m
~

O~OIh

IM665311M6654
READ AND PROGRAM CYCLES
E,
ADDRESS.

PROGRAM - - -

OV

t

VPROG

-40V

------------'--+

s--~------~~--------~I

\~__----~--__-

1----'-,,---- R E A O - - - - , - - _ . I _ _ _ _ PROGRAM _ _ _.I_._ _ _ _ READ _ _ __

DC CHARACTERISTICS FOR PROGRAMMING OPERATION
TEST CONDITIONS: Vee =Voo=5V:b5%, TA=25°C
PARAMETER

SYMBOL

Program Pin Load Current

IpROG

Programming Pulse Amp,litude

VPROG

Vee Current

Icc

Voo Current
Address Input High Voltage

V 1HA

CONDITIONS

MIN
38

100

Address Input Low Voltage

VILA
V1H
V1L

Data. Input High Voltage
Data Input Low Voltage

TYP

MAX

UNITS

80

100

mA

40

42

0.1

5

40

100

V
mA

Voo"':2.0·
0.8

,

V

Voo-2.0

I)

0.8

/

AC CHARACTERISTICS FOR PROGRAMMING OPERATION
TEST CONDITIONS: Vee =V oo =5V:b5%, h=25°
PARAMETER
Program Pulse Width
P~ogram

SYMBOL
TPLPH

CONDITIONS

MIN

trise = tlall = 51's

18

TYP
20

MAX
22

UNITS
ms

75%

Pulse Duty Cycle

Data Setup Time

TDVPL

9

Data Hold Time

TPHDX

9

Strobe Pulse Width

TE,HE,L .

Address Setup Time

TAVE,L

Address Hold Time

TE,LE,X

Access Time

TE,LQV

I's

150
0

ns

100
.1000

PROGRAM MODE OPERATlqN
Initially, all 4096 bits of the EPROM are in the logic one
(output high) state. Selective programming of proper bit
locations to "O"s is performed electrically.
In the PROGRAM mode for all EPROMs, Vee and Voo .are
tied together to a + 5V operating supply. High IO'gie leveis
at all ofthe appropriate chip inputs and outputs must be
set at Voo7"2V minimum. Low logic levels must be set at
GND + .8V maximum. Addressing of the desired location in
PROGRAM mode is done as in the READ mode. Address
and data lines are set at the desired logic levels, and .PROGRAM and chip select (5,> pins are set high. Th~ address is

latched by the downward edge on the strobe line (E,). During valid DATA IN time, the PROGRAM pin is pulsed from
Voo to -40Y.. This' pulse initiates the programming of the
device to the levels set on the data outputs. Duty cycle
limltat!ons are specified from ¢hip heat ,di5siRation Go'n~
siderations. PULSE RISE AND FALL TIMES MUST NOT BE .
FASTER THAN 51's.
Intelligent programmer equipment with successive
READ/PROGRAMIVERIFY sequences,such as the Intersi!
6920 CMOS EPROM programmer, is recommended.
8-184

O~OIL

IM665311M6654
PROG~AMMING

SYSTEM CHARACTERISTICS

1. During programming the power supply should be
capable of limiting peak instantaneous current to
100mA.

ERASING PROCEDURE

2. The programming pin is driven from VDD to - 40 volts
(± 2V) by pulses of 20 milliseconds duration. These
pulses should be applied in the seque(lce shown in the
flow chart. Pulse rise and fall times of 10 microseconds
are recommended. Note that any individual location
may be programmed at any time.

The IM6653/54 are erased by exposure to high intensity
short·wave ultraviolet light at a wavelength of 2537 A. The
recommended integrated dose (Le.,UV intensity x ex·
posure time) ,is.10W sec/cm2. The lamps should be used
without short·wave filters, and the IM6653/54 to be erased
should be placed about one inch away from the lamp
tubes. For best results it is recommended that the device
remain inactive for 5 minutes after erasure, before
reprogramming.

, 3. Addresses and data should be presented tethe device
within the recommended setup/hold time and highllow
logic level margins. Both "A" (10V) and non "A"
EPROMs are programmed at Vee, VDD of 5\j ±5%.

The erasing effect of UV light is cummulative. Care should
be taken to protect EPROMs from exposure to direct
sunlight or florescent lamps radiating UV 'light in the
2000A to 4000A range.

4. Programming is to be done at room temperature.

PROGRAMMING FLOW CHART

8·185

O~OIL

IM665311M6654
IM6653 CMOS EPROMS AS EXTERNAL PROGRAM MEMORY WITH THE IM80C35

Vee Voo Vss

20pF

?

~05Cl
20pF

, PlolM-'

Pll~

WlJ

,P13
P14

I~
·-~05C2

iTo"

rat

P15~

P16

fTa

P17~

P20r.2~1==========l A:
A

P21 h22

i¥.

P22
P23f#

P24~

IM80C35

Vee Voo ~ GND

Vee Voo;' GND

I---~---_i~

~

~

i:

I~==l0o
r
0,

P25~
P26~
P27~

g

~~-----7iA.

~0

r---~ 0 0

-0,

, - - 02
r--- 03

-

r--

O2
03

IM6653
DBO

~~

DB2
DB3
DB4
DB5
DB6
DB7

14
15
16
17
18"
19

DBll-7''-------~-I-I__l

ALE .

IM6653

IK x 4

AD
A,
A2

\----HH-t--I

EPROM

IK

~

x4

EPROM

I----I++-I__i A,

~---H-,+I--I A2

A3

I----I++-I__i A3
I----~+-I__i A.

A,

As

1----~+-I__iAs

~-------4-r~~
I - - - - - - - _ i A,

A.

A,

~I

IM6653 CMOS EPROMS AS PRO_GRAM ,MEMORY WITH THE IM6100
+5

GND

+5

th
Vee

Vee

rm

,.------,.. 03

+5

m Dp~:

f25.
=r
\

~
-;::::=

GND

t t

IM65x61

256 x 4
RAM

~

Ao

Vi E 8,

03
IM65x61
256 x 4
RAM

A.

IM65x61
256 x '4
RAM

Vi E 5,

~

Vi E '81

I
GND

+5

IM6100

Vee voo;g GNQ
00
0

,

- l=-

DXo

OX,

03

"i:'l>"

A.

IM6653
1K

,1
i:
m

'"
" ...

+5

t-n

m~

05C OUT

i:

GND 52

00

XTC

05CIN

l>

"'=

03
As

Vee

r;=

Vee GND

...x

GND 52

00

GND

lh

!h

GND 52'

00
As

+5

GND

"'=

AD

Q3

~
i:

AD.

IM6653
1K x 4
EPROM

x4

,
'-

+5 GND

D~DDV:S5'

J

E, S

I I

~

Vee VD'D~ GND
Oog

EPROM

DX11

GND

Ao

E, 5

I I

t

VCCVDD~

-=00
03
~

Gr

GND

g

,

"i:
l>

IM6653
1K

x4

EPROM

Ao

E1 IS

I

I
,

5'r-

-02
CD4515B
5TR
52
GND_ 03
GND- 04 INH 515

In

I

} ADDITIONAL MEMORY ENABLE

I
8-186

6801'
CMOS- MicrocQmputer
,Family Sampler Kit
6960 - Sampler PC Board
,

FEATURES
• Provides fast and simple exposure to the IM6100
, Microcomputer Family
_
• Very Inexpensive'
• Interfaces to any ASCII RS-232 or20mA terminal
• Includes OOT monitor In ROM
- Includes tape punch and load routines in ROM
• All CMOS components
• Executes POP@-8/E instruction set
• Sampler PC board available - easy to
useandi"expensive

In addition; a printed circuit board is available to simplify
construction of the Sampler system (part number 6960),
The Sampler board is laid out so thai it may interface with
both RS-232C and 20mA c'urrent loop, The user may
enhance the capability of the Sampler system with the addition of sixteen optional SSI packages, 'assorted switches, and LEOs (optional parts not included), The added
capabilities include:
•
•
•
•
•
•

Address/Bus Display
Status Display
Single Instruction Step
Single Cycle Step
12-Bit Input Port
12-Bit Output Port

Any of these options can easily be added when desired;
but are not required for operation.

GENERAL DESCRIPTION
The 6801 Cfv!OS Microcomputer Family Sampler Kit is
a complete set of LSI components necessary to build a'
general purpose microcomputer. The heart of the
Sampler Kit is the IM6100 Microprocessor, The IM6100
Microprocessor exequtes the Pop-alE instruction set
The Sampler Kit also includes the OOT (Octal
Oeb~gging Tec~nique) monitor ROM (1K x 12), three
RAM s (each With 256 x 4 bits to form 256 x 12 bit
words), the Programmable Interface Element (IM6101)
and a.'UART (IM6403), A significant cost savings is
realized through purchase of the Sampler Kit over the
single quantity purchase price of all, the included
components,
'

The Sampler system, when teamed with any ASCII
terminal, gives the user an easy to understa'nd, yet powerful IM6100 Microcomputer system, The ODT Monitor program provides the control necessary to display and alter
memory contents, start execution at a particular address,
set a breakpoint, manipulate the registers, or search
memory for a value. If the terminal has tape punch/read
capability, built-in routines allow loading and saving of
programs.
'
OJ

PDP-8 is a reglstered,trademark of Digital Equipment Corp,

BLOCK DIAGRAM

rD~
IM6312 CMOS
lKX12ROM

IM6100
CMOS
_P

A
~

IM6S61 CMOS
2S6X4 RAM

t
t

-

IM6101 CMOS
PIE

t

1
IM6403CMOS
UART-

,8-187

"V

~-

,~

6801
0;::;8000000000rx

xxxxxxxxxxxx>< ....

O - " . ) W ... ()1cn .... O;l-:lO:::~~

I
4

vee

16

[)~lARE(j

17

CPREO

18

INTREQ
11 WAIT

19
20
21

32 CO

"

34 C2

23
24

26 GND
7 RESET

25
27

"g- "
~~

10
13

6 HUN!

"

fiLT

30
35
33

DXO
DXI
DX]
DX3
DX4
DXS
DX6
DX7
DX,
OX9

;;;
DXI
OX2
DX3
DX4
DXS
DX6
DX7
DX,
DX9
DXlO

DX10

OXl1

OXll

LXMAR

STR
OEH
DEL

XTe
MEMSEl

::

RSEL

DEVSF.L
SKP
el

~

A

N
~
~-

s;

9Sl

N
~
,N

o "

vee

~

,,-

~

,,-

0

- > a
z
~

S

I vee
9 SEl4
11SEL5

15
16

12 SEl6
INTGNT

2

,

PRIN

3

,

SENSE4

17
18

19
20
21

"

SEL3
14 SE17
27 GND

?3
24
25

26

DXll

10

lXMAR
XTe

13

;:

§~

28
39
:l:J

~

'8:

~

lJ'1Cl'>
~

~

m~

i"~

:D

AD
AI
A2
A3
A4
AS

m
m

A
~

-

N

~

A7
STR
RNI
e52

DEVSEL
SKP/INT
CI

w
a

~
~

~~

TaRl

8

ReRG
TBRG
RaR5
TBA5
RBR4
TBR4
RBR3
TBRJ

AAI
vee
CAL

PI

36 SBS
37 ClS2

38 CL$l

;;;
w

;;
W
;;

TBR2

AS
,A6
A7
STR
R/W

a;

ABRI

CS2

<5

ABA2

39 EPE
GND
16 SFO
2 SHE

3

MR
~

~-

0

TBRS
ABA7

"

"

~~

A6

RaR8

20
I
34
35

e51
vee
GND

~

~o

0

~

110 3
If04

~

~E~~
"

~

1/0 2

~

~

mmm

222

lID,

DXO
DXI
DX2
OX3
DX'
DXS
DX6
DX7
DX,
DX9
DXlO

ru
m

e51
vee
GND

i~

~

w

TBfl.1

g

a~ 0
x
o "

Z

~

mm~'AO

;;..

0;

vee

A2

OJ

GND

A3
A4

I/0,
H+H-t-I++--AS

~

:~::::
1/°4

STR
-R/W
e52

System Hookup Diagram
8-188

CSI

Al

D~DIb

6801
ODT MONITOR COMMANDS
ODT commands consist of a control character or an
. octal number followed by a control character. The,
commands may be typed in any time the terminal is idle
and are executed as soan as the contro.l character is
. typed.
.
BINARY LOAD COMMAND
L - Load fram the tape reader
Typing an L will load binary tape from a reade'r. The
checksum will be printed out an t/1e terminal fallowing
the end af theJaad. Printed aut checksum should be
0000 for a proper load.
EXAMINE/MODIFY COMMANDS
/ (slash) - Opens a location
Typing an octal number nnnn followed by a slash
causes the lacatian whase address is nnnn to be
opened. When a location' is apened, its cantent is
printed aut as an octal number. Typing a slash not
preceded by a number causes the mast recently
opened location to be reopened.
(carriage return) - Clases a location
Wl;len a locatian is open, typing an actal number, nnnn,
follawed by a carriage return causes the contents af
the locatian to be changed to the number nnnn and
closes the location. Typing a carriage return not
preceded by a number causes the locatian to be closeC\
without madifying its cantents.
(line feed) - Clases and opens next
When a lacatianis open, typing a line feed causes the
location to be closed and the next memary location
(that with an address ane higher than the current
locatian) to be opened. The address of the new
location will be typed out, followed by a slash, followed
by the contents of the new location. Typing an octal
number, nnnn, before typing the line feed causes the
contents of the old location to be changed to nnnn.
- (back arrow) - Closes location and opens indirect
reference
When a location is open, typing a back arrow causes
the location to be closed. The contents of the location
are then treated as an indirect reference. That is, the
content of the old location is' taken as an address, and
the new location is opened. If while a location is open,
an octal number, nnnn, is typed followed by a back
arrow, the content of the open location is changed to
nnnn and proceeds as above.
t (up arrow) - Closes location and opens memory
reference
This command behaves identically to the back arrow
command except that the contents of the location are
treated as a memory reference instruction, and it is the
location referenced by that instruction that is opened.
The location opened is that immediately referenced by
the instruction. If the instruction is indirect (bit 3 is set.
to 1 ), then typing the up arrow only opens the location
containing the pointer to the operand of the
instruction. To open the effective location referred to
by an indirect instruction, type an up arrow (memory
reference) followed by a back arrow (indirection) ..

PROGRAM CONTROL AND BREAKPOINT
COMMANDS
G - Go to
Typing an octal number, nnnn, followed by a G causes
OoT to begin executing the program stored in
memory, starting. at location nnnn ..
B -Breakpoint
Typing an octal number, nnnn, followed by a B causes
. ODT to set a breakpoint at location nnnn. Typing a B
without preceding it by a number cal,lses the current
breakpoint to be cleared.
C - Continue
After a breakpoint causes control to return to ODT
from a us'er program, typing C causes the program to
resume execution where it left off.
A - Examine/modify accumulator, link, MQ
Three consecutive ODTRAM locations are reserved
for storing the contents of the AC, link and MQ
registers when a breakpoint occurs. When execution
of the user's program resumes (via the G or C
command), the contents of these registers are restored
from these locations. Typing A causes the first of these
locations, containing the contents of the AG, to be
opened.
'
WORD SEARCH COMMANDS
M - Open search mask, lower bound, upper bound
The mask, lower bound and upper bound for ward
searches are kept in that order in three consecutive
reserved ODT locations. The. first of these locations,
the mask, can be opened by typing M.
W - Word search command
Typing an octal number, nnnn, followed by a W causes
a word sea(ch to occur. The sea~ch proceeds as
follows: The number, nnnn, that was typed is masked
and remembered as the quantity which is being
searched for. (The operation of masking is to take the
bitwise boolean AND of the given word with the
contents of· the mask word.) Then each location'li]
beginning with the location whose address is stored in •
the lower bound word, is masked and compareq with •
the quantity being searched for. If the two are equal,
then the address of the word, followed by a slash and
.. the (unmasked) contents of the word are printed out.
Then the next lacation is examined and so on until (and
including) the location whose address is stored in the
upper bound word is reached. The word search
command does not change the c·ontents of any word in
. the user's programs.
TAPE PUNCHING COMMANDS
The following commands can be used to punch out
paper tapes that can be read in by the BIN loader.
T - Punch leader/trailer
Typing a T will cause about four inches of leader/trailer
tape (tape punched with 200 octal) to be punched. The
T command also causes the accumulated checksum to.
be set to zero (cleared).

8-189

6801
P - Punch tape
Typing an octal number, nnnn, followed by a semicolon (;) followed by a second octal number, mmmm,
followed by a P; causes atape corresponding to the
contents of the block of memory beginning at location,
nnnn and ending at location,mmmm to be punched.No
checksllmis punched at the end of the block so that
several blocks can be punched together with one
inclusive checksum.
E-

Punch checksum and trailer

301/7440.l..E
302/5300 IF
, 30317400 7402CR

L7402

CR
A1764 OlF
0050/0001 OCR

Typing an E will cause the accumulated checksum to
be punched, followed by about four inches of
leader/trailer tape. The checksum is also reset to zero
(cleared).
'

302B
300G
0302 (0001

SAMPLER ODT EXAMPLE
Say that the simple program
300
301
302
303

7001
7440
5300
7402

0302 (7776
303B

START, lAC
SZA
JMP START
I:iLT

Q
0303 (0000

is stored in memory. Then the following might be the
result of a session with ODT, (Note: The underlined
portion is typed by the user, and the remainder is typed
by the computeJ. The symbol CR stands for carriage
return,and IF stands for line feed.)
,

6960 -

LIST THE PROGRAM IN OCTAL'
IF MEANS - sti0W NEXT
lOCATION
"

30017001 LF

,AOOOOlF
0050/0001 CR

LOCATION 303 IS WRONGCHANGE AND VERIFY
ACCUMULATOR, CONTAINS
GARBAGE, MAKE IT ZERO
SAME-FOR l,INK

SET BREAKPOINT AT JMP START
EXECUTE PROGRAM (GO)
BREAKPOINT OCCURS;
ACCUMULATOR HAS BEEN
INCREMENTED
CONTINUE PAST BREAKPOINT
1 + 7774 TIMES
'BREAKPOINT OCCURS; AC=7776
RESET BREAKPOINT TO HLT
INSTRUCTION
" CONTINl)E
PROGRAM STOPS WHEN AC
REACHES 0 AGAIN
, EXAMINE AC AND LINK
LINK HAS BEEN CHANGED BY
OVERFLOW
. CLEAR ALL BREAKPOIN;["S

SAMPLER PC BOARD LAYOUT'
ADDRESS/BUS

RS-232-C,
CONNECTOR
SINGLE'
INSTRUCTION
STEP

8-190 '

D~DlL

6901
4K x 12 CMOS Memory Module
with BaHery Back-up
.

.

fEATURES
• Rechargeable battery back-up
• Data Retention of up to 80 days
• Low power
• Compact size
• Low cost
• Switch selectable field addressing· .

GENERAL DESCRIPTION
.The 6901 CMOS memory module provides the Intercept
System with 4096 twelve-bit words of battery-backed-up
memory. The module retains ,its data when system power is
off;· an on-board rechargeable NiCad battery insures and
'Uninterrupted power supply to the CMOS RAMs for up to 80
days. When system power is on, the NiCad batteries are
recharged for future use. Up to eight 6901 modules may be
installed in a system by setting on-board switches so each
module responds to a unique memory field.

SPECIFICATIONS
PHYSICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS
DC Power
Requirements:

150mA at +5V typical,
500mA maximum

1.155"

ENVIRONMENTAL CHARACTERISTICS

-1

Operating
Temperature Range:
Operating
Humidity Range:

P.C. Card

3.690"
I

_l

.-J

O°C to 50°C
10% to 90% 1no condensation)

ORDERING INFORMATION

-8.000,,----'--1

1-·

Order No.
I

8-191

Module:

6901-M4KX12

Documentation:

6998 Lsi-8
User's Manu.al

8910
Intercept D
Microcomputer
Development System

··.O~OlL

- Up to 8 Simultaneous Breakpoints
- Highly Interactive Debugging Facilities
• Two High Speed Serial 110 Ports with Multiple Baud .
Rates (14 Different Baud Rates)
- User Selectable
-RS232C Standard on Both 110 Ports
.
- Elthtlr Port May be Strapped for 20mA Current Loop
• Compact Size (21.5cm x 51.4cmx 47.8cm)
• Extensive Hardware Options
- Memory Modules
- Wlrewrap Module
- Extender Module
- Teletype Relay Module
- Dual Floppy Disk System

FEATURES:
• Low Cost
• POwerful PDP®·8/ecompatible processor
• Compact size
•
• Modular design
• 4K CMOS memory
• Bus supports easy.1I0expansion
• Resi~entflrmware monitor/debugger
• Large available software base
• Low power
• Supports Interrupt and DMA operations
• Real Time Clock
HARDWARE FEATURES:
• 4K Words of Resident Memory (RAM)for Program and
Data Storage
• Expandable to 32K Words of Memory
• Resident Control Panel Memory (2K Words ROM and
256 Words RAM)
- Transparent to User Programs
- Floppy Disk Operating System Bootstrap

.'

n.·

8·192

Intercept D
Primary Port

GENERAL DESCRIPTION
Intercept II is a general purpose microcomputer
development system for Intersil's IM6100
Microprocessor components. It consists of two PC
boards, a Central Processor Module Board, and a
Memory Module Board. The Central Processor
Module Board includes the IM6100 CPU, resident
memory (2K words ROM and 256 words RAM) for firmware storage, memory extension capability and two
channels of serial 110 ports. The Memory Module
Board includes 4K words (4K x 12) of CMOS RAM for
the user's PROGRAM/DATA storage.
All of the system control features, such asan extended
memory control (for memory expansion up to 32K
words); a real time clock, and DMA control functions
are resident in the system. The resident firmware
eliminates the need for the hardware control panel.
The Intercept II has a compact enclosure size of
21.5cm x 51.4cm x 47.8cm (HxWxD), and it allows a
total of twelve PC boards in the system. Because two
cards come with the system, the user may add up to
ten additional cards to Intercpt II.
Standardized board sizes and uniform bus definitions
ensure compatibility with previous Intercept designs.
Intersil offers hardware and software support including 4K memory modules, floppy disk hardware,
Intercept Floppy Disk Operating System, Parallel 110
'Module, etc.
-

Baud Rates: 50/75/110/134.5/150/200/300/6001
1200/1800/2400/4800/9600/19200
Any of these 14 different baud rates is switch
selectable.
Code Fomiat: 10 level code
Parity: None
Secondary Port
Same as Primary Port except: Baud Rate is console
controlled or software programmable (50/75/1101
·134.5/150/200/300/600/1200/1800/2400/48001
9600138400. )
Includes four RS232C supervisory signals (two
inputs and two outputs)

Interrupt
Single level, maskable, prioritized, vectored or
polled.

Direct Memory Access
Standard IM6102 DMA, bus control implemented
on CPU module - transfer rate user controlled
(direct or user cO!'trolled block DMA) - typically
greater than 2MHz. .

Real Time Clock
4MHz DEC compatible

HARDWARE SPECIFICATIONS

Physical Characteristics

Word Size

Dimensions: (HxWxD) 21.5cm x 51.4cm x 47.8cm

Host Processor: Intersil IM6100
Data: 12-bits
, Instruction: 12 or 24-bits

Weight:

15.9KG

Electrical Characteristics
Memory Size
DC Power
Supply

Main Memory
RAM: 4K expandable to 32K (CMOS with battery
backup standard)

+5V

± 5%

+12V ± 5%
-12V ± 5%

Control Panel Memory (2K words x 12)
RAM: 256 words (resident on CPU - monitor
uses 128 words)
,
ROM: 2K (resident on CPU - used by
monitor)

Power Supply
Current

BasIc
System Current
RequIrements (Typ.)

6A

.8 A

1.0A
1.0A

.1 A

.1A

AC Power Requirements
Frequency:
Voltage:
Power:

System Clock

50 or 60 Hz
115 or 230V AC
175W max.

Crystal Controlled: 3.3MHz typical

Environmental Characteristics

Serial I/O Interfaces

Operating Temperature: 0° C to 50° C

(RS232C is standard on both 1/0 ports; either port
may be strapped for 20m A current loop operation)

Humidity: 10% to 90% (no condensation)
8-193

I

._

InterceptD
Equipment Supplied (Basic System)

Features

• 6912

Central Processor Module

• High Speed Resident Operation

• 6901

4K CMOS RAM Module

• Highly Interactive Debugging Facilities
• Completely Transparent to User Programs

• Finished Cabinet with Power/Supplies, Card Cage
and Fan
• Intercept User's Manual
• ,Two RS232C and One 20m A Current Loop Cable

SOFTWARE OPTIONS

• AC Power Line Cord

Compatible with OS18 Operating System Licensed
from Digital. Equipment Corp. Including:
• System Utilities PIP, DIRECT, FOTP, BUILD

Hardware Options

• Editors Edit, TECO

6901- M4K x 12
4K Nonvolatile CMOS Memory Module,

• Assemblers PAL 8, SABR, MACREL, RALF.

6905 - WIRE WRAP
Wirewrap Module for User Interfaces to Intercept

• High Level Languages FOCAL, FORTRAN II,
FORTRAN IV BASIC

6906 - EXTEND
Extender Module

6909 - RELAY

-

Teletype Paper Tape Reader Remote Control Module

6914 -

IFDC

,

Single Board Floppy Disk Controller

6915 -

.. File System Controls Floppy Disk Input/Output
Operation

M32K x 12

• Keyboard Monitor for Communication Between
User and IFDOS

32K NMOS Dynamic RAM Board

6917 -

Parallel .110

• Text Editor Creates and Modifies ASCII Text at the
Terminal

REMDAC Compatible 8 bit Parallel 1/0

6970 -

IFDOS Dual Floppy Disk Unit

Dual Floppy Disk System with Single Board Interface
to Intercept Bus.

SOFTWARE/FIRMWARE SPECIFICATIONS
Resident Control Panel Firmware Monitor

11.
,

Capabilities

•

Intercept Floppy Disk Operating System (IFDOS) ,

Accumulator, Link, pro, gram Counter, Instruction/
Data Fie}ds, MO, Switch Register-examine/modify

• PAL Assembler translates IM6100 assembly lan,guage to machine language in one or two passes.
About 400 symbols pan be created in standard
system of 4K word memory. 1024 more symbols can
be created with each 4K additional RAM with
maximum symbol limit of up to 4095 symbols.
.' Numerous Switch Options and Pseudo-operations
for Assembly and Listing Control

• Control Panel and Main Memory-examine/modify
• Single Instruction, BreC\kpoint, Snapshot arld Trace,
debugging and modify
• IFDOS and OS/8 Operating
System Bootstraps
• Memory Bit Pattern/Word Search
• Binary Paper Tape Input/Output Commands
(Loader/Punch)
• DEC PDP-8/E ® Console Terminal,HL T, OSR
Emulation
• Up to 8 Simultaneous Breakpoints

• Numerous Utility Programs for File, Manipulation
and Disk Dumping 'and Copying
• Disk Diagnostic Programs

,

• Supplied withlFDOSin a Standard Floppy Diskette
and Listing
• Required Hardware: '
. - Intercept System
- ASCII Terminal
- 6970-IFDOS Dual Floppy Disk Unit

8-194

Intercept

n

n~nlL
• Multitude of Programs avaihible through Digital
Equipment Corporation User's Society, Including:
- Utilities
- Languages
- Applications

6981 - FOPAL III
PAL III Fortran Cross Assembler
• Written in Standard Fortran IV

• Card Deck Based
• Can Use with Any Fortran Compiler and a Card
Reader (such as 029 Reader)

., Registered trade mark of Digital Equipment Corp.

6982 - FOCAL@8
(Order No. 6982-IS-LFOCA) - See Note 1
• Interactive Algebraic Language
• Extensive Math. Functions
• Easy to Learn High Level Language
• Needs only 4K Words of RAM
• Paper Tape Based

Note:
1. This is redistributed Digital Eq'uipment Corporation Software.
It is copyrighted and non-licensed Digital Equipment Corporation
software, which means that it cannot be copied although it may
be distributed to third parties. Digital Equipment Corporation
assumes no responsibility for any software distributed by Intersil,
Inc. nor for the performance of any of Intersil's products.

FLEXIBLE DISK
SUBSYSTEM OR UP TO
FOUR USER DISK DRIVES

enD
PRINTER

INTERCEPT SYSTEM BLOCK DIAGRAM

8-195

6912
CPU with PuaJSeriall/O
:,,' .

HARDWARE FEATURES ";.
•
•
•
•
•
•
•
•
•

Powerful P'DP®-8/e Instruction s~t
Two' Independent selj~1 ports (RS-232 or 20mA current loop)
14 selectable baud rates. /';
.
Resident memory ext~nsion controller'
Real-time clock:'"''
Auto-.start veCtor· option
Single compact boa~d
Lowpower
'
Reliable

FIRMWARE FEATURES
• Resident debugger
• Memory/register examination/inpdificatlon
'. Up to 8 breakpoints
• Slngl~.lnlitructlon In RAM or ROM
• Single.instruction trace In RAM or ROM
• Snapshot mode
• Operating system bootstrap
• Memory search/search and replace
• Paper tape loadlpunch
•. Effective address calculation for memory reference
.Instructlons

. GENERAL DESCRIPTION

'. '.

. .

.

The 6912CPU module is a'powerful;compact central processor
for the Intercept OEM Mic.rocomputer System: The procesl!or
executes the powerful PDP®-8/8 iristruction set; and addresses up t6 3K twelve bit words of memory. Two indepen- .
dent serial ports on board may be used for RS-232 or 20 mA
current loop operation and each po~ may operate at oneof14
rates between 50 and 19,200 baud. The primary port emulates
the PDP®-B/e terminal interface. Other hardware features

. include a crystal-controlled,programmable real-time ciock
and an auto-start vector option.
Resident firmware includes a concise, 'powerful debugger featuring high-speed operation, highly interactive structure, and
complete transparency to user programs. The firmware is
located in control panel memory so no user memory space is
used.
. ' .
®PDP~8

is a register~d tradem.ark of Digital EqLiipment Corp.

SPECIFICATIONS
PHYSICAL CHARACTERISTICS:

L

,.;-:-_____--,

1.155"

.P.C. Card

0.400.........

ENVIRONMENTAL CHARACTERISTICS

1

Operating
.
Temperature Range:
Operating .
Humidity Range:

10% to 90% (no condensation I

6.000"

"1-.-----0.000
- ___~----'J
. -.-----1·1

ORDERING INFORMATION
Order No.

,

ELECTRICAL CHAR~CTERISTICS
DC Power
Requirements:

O°C to 50°C

400mA(typ.) at +5V 1.2A max.
2mA (typ.) at +12V 4mA max.
2mA(typ.) at '-12V 4mA max:
8·196

Module:

6912 Intercept CPU

Ri.bbon Cable Serial I/O Assembly:

6925 Serial I/O Assy

Document~tion:

6998 LSlcB
User's Manual

O~OIL

69141FDC
Double. Density DMA
Floppy Disk Controller

FEATURES
• Single or double density
• Up to a industry standard flexible disk drives
• Single or double sided

,

• Industry standard or non"standard forma,s
for custom appllcatl~ns
.
• Automatic address verllication
• Automatic CRC on address and data
• Variable stepping rates
• DMA transfer of data in

a-bit or 12-bit modes

• Capability to lormat diskettes
• Full diagnostics

GENERAL DESCRIPTION
The Intercept floppy disk controller board provides inexpensive, reliable, compact mass storllge for the I ntercept system.
It uses a single bus slot and controls uptoeightdiskettedrives
with a maximum SUb-system capacity of 10 megabytes. Many
types of drives can beused, including single or dou ble"density
and single or double-sided. Data integrity is ensured by
employing address verification and cyclic redundancy
checking (CRC). Data transfer rate is maximized by using
direct memory access.

Because the 6914 uses an advanced LSI controller, the user has
great flexibility in choosing the drive and/or format best suited
to the application. Stepping rates, sector sizes, and sector positions can be varied to increase - both data capacity and
throughput.
For users:wishing pre.packaged disk drive SUb-systems, Intersil
offers the 6975 Dual.'Floppy Disk Drives, consisting of two
enclosed drives with power supply, cables, and documentation.

SPECIFICATIONS
ELECTRICAL CHARACTERISTiCS

PHYSICAL CHARACTERISTICS

_I____ ,...-_ _ _ _ _ _-,

DC Power
. Requirements
. Voltage:

-1

Current

-1 '

'L
0.400" _____

P.C. Card

I

1.3A nominal, 2.2A max.
10mA nominal, 35mA max.

r:tIII
1:1

ENVIRONMENTAL CHARACTERISTICS

6.000"

Operating.
Temperature Range:
OPElrating
Humidity Range:

J
I

L . . . . . - -_ _ _ _

+5V ± .25V
+12V ± .6V

1--8.000,,---1

10% to 90% (no condensation)

ORDERIIIIG
INFORMATION
/

-,-.
Order No.

Module:

6914-IFDC

Flexible Disk Drive Cable:

6926IFDCCABLEASSY

Dual Flexible Disk Drives:

6975-IFDD

Documentation:

6998 LSI-.8·
User's Manl,l'll

"

.!

8·197

32K X

6915
12 RAM Board

FEATURES
• 32K x 12.full ,memory co":,plement for the Intercept System
• Many options for custom applications
.', Low power
.,' Small parts count for reliability
• CompaCt sl,ze

,GENERAL DESCRIPTIO!\!
The 6915 memory module provide,S 32K twelve-bit words of
memory forthelnterceptsystem, using NMOS dynamipRAMs
for, low cost and small parts count. All necessary refresh
circuitry is resident on the module.
The module has a host of options for custom application flexibility, These include selective 4K field disable for mixed memory
(e.g., dynamic and battery-backed) sysiems, ,RAM inhibit for
shadowing ROM over RAM, and.paritystorage for off-board
error checking. .
'

SPECIFICATIONS
PHYSICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS
DC Power
'Requirements:

~

'r~-----'l

L-_~_P_.c_._c_a_rd .....Il
.-J I----I~ 8,000"--,------/'\
'[

CPU
Crystal Frequency:

'560niA (typ., at +5V, 1.2A max.
160mA (typ. 'at +12V, 840A max.
10mA (typ.) at-12V, 12A max.
3.3 MHz maxirri~m

ENVIRONMENTAL CHARACTERISTICS
Operating
Temperature Range:
Operating
,
Humidity Range:

___

O·C to 50·C
10% to 90% (no condensatiOn)

---'..-'

ORDERING INFORMATION

I

Order No.'
r--'-------t---,--; ,
Moduie:
69i5-M32KXi2
,Documentation:

8-198

6998 LSI-8.
User's Manual

ADDITION~L MODULES

6917 - REMDAC Compatible S-bit Parallel 110

6905 - Wirewrap-Universal Wirewrap Module (Left)
6906 - Extend-Card Extender Module (Right)

,
6912-CPU,6901-M4kx 12, 6915 M32k x 12,
6914-IFDC

Intercept II Card Cage without Powerl:!upply.

8·199

..

'~'

D~DIL

6920
CMOS
EPROM
,
, Programmer

FEATURES,

,DESCRIPTION

• Programs Intersll's IM6653f54 CMOS EPROM
• Software ,controlled for ease of expandability
• IM6100 microprocessor based
- 16K bit buffer memory
• Serial data commJnication
- 20 mA current loop
- RS232C
- 110 to 9600 selectable baud rate
• Three operating modes
- Master with CRT terminal or Teletype®
-' Slave. with development system
- Stand-alone for duplicating EPROMS
• Self contained Of A controlled power supplies
• Check sum error detection

lntersil's 6920 CMOS EPROM programmer is a multimode cost effective instrument used to program
Intersil's IM6653/54 family of CMOS EPROMs.
The 6920 is microprocessor controlled, allowing the
programmer to operate as a stand-alone unit, for
duplicating EPROMs; a master, for operation with CRT
terminals or Teletype®; or a slave, for operation with a
software development system or minicomputer.
Serial data communication is used for all command
and data transfers'with a 20 mA current loop and an
RS232C interface provided. Check sum error detection
is employed for data validation.

®Teletype is a registered trademark of Teletype Corp .

•

~?;;:;::;;0'
,:,;-;::::::':"

11111111

••••••••

8·200

6941/42 CONCEPT-48
8048 Tutorial UnitDevelop ...ent Tool
• Executes 8048 Code
• Compact Single Board Design Fits Into 3-Ring Binder
• Operated by Standard 9 Volt Battery or calculator
type wall-mount power supply
• Tactile Feedback Keypad
• 7 Character LCD Display
• 44-Pln Edge Connector for System Expansion
• 3 MHz Execution of User Program
• Optional I/O Expansion with IM82C43
• 2K ROM-based Monitor includes Load, Run, Debug,
Modify, and Save Commands
• Single Step Operation
• 8 Breakpoints - User Selectable
• 6941 CONCEPT-48 Tutorial Unit: Includes 256 Bytes
. of External Program Memory and 64 Bytes oflnternal
Data Memory
.
·6942 CONCEPT-48 Development rool: Includ,es 2K
Bytes of External Program Memory, 64 Bytes oflnternal and 256 Bytes of External Data Memory, on b!)ard
negative voltage converter, and RS-232/TTY Serial
Interface with Selectable Baud Rates of 50thru 19200
• Detailed User's Manual
GENERAL DESCRIPTION

The CONCEPT-48 is a versatile single board system
designed to. execute and debug software written for'
tlie 8048 single-chip microcomputer family. Object
code may be down-loaded from a development
BLOCK DIAGRAM
PORT1

ADR
BUS

DATA
BUS

RS-232/20 mA

512 TO 2K BYTES
PROGRAM MEMORY

256 BYTES
DA.TAMEMORY

28 KEY
KEYBOARD

8-201

system via the serial interface or entered in hex via the
28-position keypad. A 7-digit LCD display provides
information about current operations' and input
commands.
Programs are executed ·at 3. MHz .using an 8035 with
external memory. Valuable debugging tools include 8
breakpoints and the ability to Single step. Debugging is
further enhanced by the ability to examine and/or
modify registers, ports, flags, or counter. These
capabilities also simplify user exploration of the
8048 family architecture.
The CONCEPT -48 provides expansion capabilities via
a 44-pin edge connector. The unbuffered signals give
software access to all of Port I, TO, TI, and the
timer/counter, as well as the keypad, the LCD display,
and the optional UART. All 8048 signals except the
crystal inputs, SS, EA, and P24-P27 are available.
The CONCEPT-48 is available in two configurat,ions.
The 6941 CONCEPT -48 Tutorial version is primarily for
learning the use ofthe8048architectureand instruction
set. The battery operation and notebook card size make
it ideal for classroom use. The 6942 CONCEPT-48
Development Tool~version inclucies a serial interface,
expanded program merrtory(2K), and expanded data
memory (256), and is intended primarily for use as a
limited. product development tool. It may be used stand
alone, or with any deyelopment system which can
assemble 8048 program code ..

694"1/42CONCEPT-48

BREAK,FORCE
ADDRESS DECODE/SAVE
MONITOR LOGIC

PROGRAMMABLE BAUD RATE .
RS·232C SERIAL. I/O

8035 PROCESSOR

ICL7660
NEGATIVE
VOLTAGE
CONVERTER

IM65X61
EXTERNAL·
USER
PROGRAM ..
MEMORY

9 VOLT
POWER
SUPPLY

ICM7211
LCD DISPLAY
DRIVER·

LCD
DISPLAY

B ·.
•

IM65X61
EXTERNAL
DATA MEMORY

. KEYBOARD, PCAND
ACC SAVE LOGIC

KEYPAD

\

\
8·202

O~OIb

6941/42 CONCEPT·48
KEYPAD DESCRIPTION
The keypad monitor firmware of the CONCEPT-48
resides in a ROM and operates the keypad, display and,
peripheral functions of the system.
The keypad consists of two portions: The 16-key
portion is doubly-labeled with the hexadecimal
numbers 0-9, A-F, and a function abbre\(iationabove.
The 12-key portion is labeled with a single function.
Keys take effect on the u'pstroke' or release, except
MON, BOOT, UO, TO, T1 and CANCEL which are all
actuated during the key press.
'COMMAND SUMMARY
GROUP

KEY
BOOT
MON

2

RBO
RB1
XMEM
PORT
XPORT
BKPT
DUMP
. LIST

4
__________

5

6

/

Addr EXAM
,AddrEXAM
Reg # EXAM
Reg # EXAM
i\ddr EXAM
, Port # EXAM
Port # EXAM
Bkpt# EXAM
ST. Addr EXAM
End Addr CLOSE'
St. Addr EXAM
End Addr CLOSE

Reset and initialize System
Exit program execution

Program memory access
Data memory access
Register bank 0 access
Register bank 1 access
External data mem'ory access
Port access
External'port access
Breakpoint access (CCC is cl,ear) ,
Dump programs in hex format
Dump programs in list format

ACC
PSW
PC
TCNT

Accumulator access
Program status word access
Program counter access
Timer/counter access

GO
STEP

Enter program 'ex'ecution
Single instruction execution

USER RST
USER INT

UO

User reset
User interrupt
Test pin 0
Test pin 1
User key signal

LOAD

Program load from serial port

~--~----F-L-A-G-S----------------~---------------F-la-g-W--O-rd-a-c-c_e_s~s_____________________

TO
T1

7

DESCRIPTION

Aborts command input
Ends command parameter input
Delimits and extends command input

CANCEL
CLOSE
EXAM
PMEM
DMEM

3

PARAMETERS

8-203

m
~

8941/42 CONCEPT~48,
The keys have been divided into seven logical groups:
1. T~rminate execution,' return to MONITOR.
Other function keys may now be used. '
2. Command entry modifier.
Used to delimit, or otherwise control input:,
3. Address Display and Modify.
These keys access portions of the system (e.g.,
memory spaces) that are composed of multiple
elements. These elements are accessed individually,
or in groups, using individual addresses, or address,
ranges.
4. Single Element Display ant! Modify.
These keys are used to access portionsofthesystem
that are normally defined as single elements.
5. Enter pser Program Execution.
"
Execution will be stopped,by reaChing a breakpoint,
receiving a BREAK character from the serial port,
actuating MON or "BOOT. STEP stops after every
instruction.
6. Direct,lnputs to Processor During User Prog;am
Execution.'
.
These keys allow the user to input signals to the
microprocessor -during real time execution of a
program. Some ofthese are disabled during monitor
execution, and others are just not used by the
monitor. None have any effect during monitor
'
execution.
7. Load Program Memory from Serial Port.
This function key loads a program, or portion of a
program, into the user program memory from the
serial port. The program'must be in Hex format.
- Incidentally, the serial port on CONCEPT-48 can,be
configured for 14 baud rates. An ,ICL7660 voltage
converter chip generates the negative voltage
required, for RS-232 frOIn the 9-volt supply. An
IM6402 UART handles the data communication.
The use.of the keys is facilitated somewhat by prompts
from the liguid crystal display. The LCD display is a
seven segment, eight-character type and is driven by
two ICM7211 M devices. The leftmost position on the
. : ) dl.ploy has been pmvlded a cu.tom set of ch,,_m Column Address Strobe.

100

BO
10,000

40

0

. 250

ns

3

165

ns

3

60

ns

120

120

200

10.0QO 250

100

135

165

100'

135
25

165
65 . 35

0

0

ns
ns

150

20

10.000

50

0

'nb

Row Address Hold Time

13

'.se .

14

'eah

Column Address Set-up .Time
Column Address Hold Time

45

45·

1-5

'ilr

ColLimn Address Hold Time Referenced to RAS

95

ns
10.000

ns
ns
ns

85

20

20

25

35

ns

0

-10

-10

-10

ns

55

75

ns

95

120

160

ns

-10

ns

16

'e.c

Chip Select Set-up Time

-10'

-10

-10

17

'eh

Chip Select Hold"Time

45

45

55

18

'ehr

Ch ip Select Hold Time Referenced to RAS

95

95

120

,

75

ns

160

ns

19

~

Transition Time (Rise and Falll

3

20

'res :

.Read Command Set-up .Time

6

0

0

0

ns

21'

t",h

Read Command Hold Time.

0

0

0

0

ns
ns

' 35

3

35

3

50

3

50

4
I

ns

22

'weh

Write Command' Hold .Time

45

45

55

75.

23

'wer.

Write Command Ho'id Time Referenced to RAS

95

95

120

160

ns

24

'wp

Write Command Pulse Width

45

45

55

75

ns

25

'rwl

Write Command to Row Strobe. Lead Time

50

50

70

85

ns'

26

'ewl.

Write Command to Column Strobe Lead Time

50

50

70

85

ns

27

'cr.

D~ta

0

0

0.

0

ns

7

28

'crh

Data in Hold Time

45

45

55

75

ns

7

29

'dhr

Data in Hold Time Referenc~d to RAS

95

120

160

ns

30

'erp

Column to Row Strobe Precharge Time

95
'0 .

0.

'0

0

ns

31

'ep

Column Pre.charge Time

60

60

80

110

ns

32

t".h

Refresh Period

33

'we.

Write Command Set-up Time

in .Set-up Time

2

2

2

ms

0

0

0

0

ns

6

CAS to WRITE Delay

60

60

80

90

ns,

6

110

110

145

175

ns

6

10·

10

10

10

ns

34

......

35

'rwd

RAS to WRITE Delay

36

"'011

Data Out Hold Time

NOTES 1:
2:
3:
4:
5:
6:

2.

"

~ = 5 ns unless otherwise noted.
·'re. > 'ra. + .... + 2 II
to limit' power dissipation.
Load = 2 TTL + 100 pF.
if tred is greater than trod (maxi access time is controllei:::l by ieee.
Vlhe (min). VIIi (min) and VII (max) are reference levels.
'we. , .iewd and ....d are n01 restrictive parameters, they are electrical characteristics only as follows:
a. lewd +1, .:; lewd minimum outPUt latch contains data written into'current address.•
b. 'ewd" lewd (max) + ~ and
'rwd (max) + I, the data output latch contains data read from the current address.'·
c. If ICWd does not meet the above, data output state is indeterminate. '

'rwd ..

7: Referenced to latest of CAS or Wf7IITE.
.
8: Any 8 cycles that perform refresh are required after power is applied.

8-216

, IM7027/MK4027
TYPICAL DEVICE CHARACTERISTICS
TYPICAL ADDRESS DATA INPUT LEVELS VS. VDD

TYPICAL DATA OI,lTPUT LEVELVS. VDD
VOH

VIN

2.0

~o
...
~ 1.5
...
~
...z

-

,~

:'--,'

,-

-- ---

1.0

7

8

---

,

'

f--

f--

W

~M~N)

9

~

~

.-

V
/"

iii

I--:'

~...

~ 3.5
w

-- -_...-- ---------

...

vlL (MAX)

...~

/'

"

\

~

10

11

12

,,100
20

13

14

15

Voo

7

-

II:
II:

--:--- 10

-

=-r--1003
(RAS Only Cycle) -

-- -r-

25°C

alII: 100
II:

B 90
W"

!(

~ 80

.gj

::)"
,II)

70

50°C ,

TA

75°C

TYPICAL tCAC ACCESS TIME VS. VDD
Voo

IBB

t-

1002
(Standby ICC with
output disable)

OPERATING TEMPERATURE

TYPICAL IBB CURRENT VS. OPERATING TEMPERATURE'

~

Voo

-

r--

I

TA
25°C
50°C
75°C
OPERATING TEMPERATURE

i 110

16

9

100

1001
(Operating Cycle) '---

W

j

/

12, 13
14
10 ,11
Voo SUpp(.,y VOLTAGE (VOLTS)

,8

-

!2 15
U

/"

.-

TYPICAL 100 CURRENT VS. OPERATING TEMPERATURE

.

::)

V

VOH

03.0

TYPICAL 100 CURRENTVS. OPERATING TEMPERATURE

ct

!

I

.~

Voo SUPPLY VOLTAGE (VOLTS)

.§.

I

!

4.0

VIH~IN)

~

!

TA = 25°C

15

~

~

CONDITlaNS
VOO= 13.2v
Va'S =4.5v

"-

iii
~ 14

~'
> 13

...
.......

"

~ 12
II:

,~

;11

5!

~,

25°C'
50°C
75°C
OPERATiNG'TEMPERATURE

'OOC\

75°C

\ .\
\"" '\. ~'

~~
~~ ~

10

30

8·217

25°C

~ i'--

,-

40

50

60
tCAC (ns)

70

---

80

tCAC

IM7027/MK4027
,TYPICAL DEVICE ,CHARACTERISTICS (Contin~ed)
TYPICAL IDD CURRENT. VS. CYCLE TIME

TYPICAL leae VS. lrel

... lrel

.s.
i!
-eo
,III

~5°C1'

:IE, .,

c.

g 15r---~r-----~~--+-----4-----4-----~

!ZIII
II:
II:

DoC

i=70

\
\ \

CI

.:3
;;:eo
ID

=

i50

u.

j10 I------t-----t-----+---t---='t---~

\

l-

II).

~40

i

I-

z

300 .

350

=

:IE

550

400

.....

. srr MAp

30,

40

8

~YCLE TIME ~ns)

"

\

\

'"

'-----

"- '-....

030

250:

'25°C,

50

eo

"'- "

~,

eo

70

tcaJns)

MAXIMUM STRESS VOLTAGES

:The memory cells are divided into 2 groups each organi'zed.as
64 rows, by 32 columns, The column addresses run in pure
binaryJorder for Y5 Y4 Y3 Y2 Y1 YO, where Y5 is niost
significant, The row addresses run in binary order for X5 X4
X3 X2 X1 Xo except for X1 and Xo which run 1,0,2,3 and
repeat, The folded bit line approach requires that data be
be stored eitl1er true or .false 'depending on the row selected,
If Xo .is at logic "0", data 'is stored true, If Xo is at logic "1"i
data is stored false,

It is of interest to k~ow worst case stress voltages for power
supply failure and/orturn·on conditions. The 7027 can tolerate
combinations of Vaa, VOO that operate within the curves of
the figure shown below.

Voo
-6.18

":.5,16
-,5,15

ROW

--

X5X4X3X2X1XO

_.------.

,1

~

~

5
4
-21,0

~~~~~~~~~~~~~~~~VBB
-21, -,5

58
59
61
60 .

,CAPACITANCE

62 .

~63

0, .. , ....... , ... , .... , .31

,-,5, +,5

TEST CONDITIONS:
32 ",., .. " .. ·, .. ",,63

VIN = OV, f = 1 MHz (NOTE 1) "
PARAMETER

SYMBOL

TYP

COLUMN Y5Y4Y3Y2Y,YQ

MA,X

UNIT

5

Ao -

A5
Input Capacitance, ~, CAS

2

5

7

5

7

WRiTE
,3

Co

Output, Capacitance, DOUT

NOTE 1: These parameters are characterized and
. periodically sampled but not 100% tested,

8-218

pF

U~Ulb

IM7i4i
4096 Bit ( 4096 xi )
NMOS Static RAM

FEATURES

DESCRIPTION

. •
•
•
•
•
•
•
•

Cycle Time Equal to Access Time
Completely Static - No Clock Required
Separate Data Input and Output
.
TTL Compatible Inputs and Outputs
883A Class B Processing Available
Single +5 Volt Power Supply
High Density 18 Pin Package
Maximum Access Time:
-200ns (-2)
-300ns (-3)
• Maximum Power Dissipation:
-256mW (L)
- 370mW (Standard)

The IM7141 is a 4096-bit static Random Access Memory
device organized 4096 words X 1. bit. The storage cells and
decode and control circuitry are completely static; no
clocks or refresh operations are required. Memory access
occurs within the specified access time after all address
inputs are stable. A Chip Select input is provided for simple
memory array expansion.
The 7141 is assembled in a standard 18 pin DIP for maximum
system packing density.

BLOCK DIAGRAM

•

PIN CONFIGURATION

MEMORY ARRAY
64 ROWS BY
64 COLUMNS

DOUT

Ao

Vce

Al

Aa

A2

A7

.A:3

As

AI.

As

As

Al0

DOUT

All

Vi

DIN

5

GND·

LOGIC SYMBOL
Vi 5 vee
Ao
Al
A2

A:3
AI.
As
A6
A7

IM1.141

As.
A9
Al0
All
DiN

(outline dwgs IN, PN)

GND

PIN NAMES
Ao-All'
DIN
DOUT
W
S

ADDRESS INPUTS
DATA INPUT
DATA OUTPUT
WRITE ENABLE
CHIP SELECT

ORDERING INFORMATION
ACCESS TIME

POWER
265mW
370mW

200n5

300n5

IM7141 L2CJN
IM7141L2CPN
IM7141-2CJN
IM7141-2CPN

IM7141 L3CJN
IM7141 L3CPN
IM7141-3CJN
IM7141-3CPN

8-219

.PACKAGE

450n5
IM7141LCJN
IM7141LCPN
IM7141CJN
IM7141CPN

DOUT

CERDIP
PLASTIC
. CERDIP
PLASTIC

m

.IM7141

O~OIL

ABSOLUTE MAXIMUM RATINGS
Operating Temperature .................................... : .... O°C to +70°C
Storage Temperature.; ................................. , ..... --65°C to +150°C
Voltage on any Pin to Ground ........................... , ......... -{).5V to +7V
Power Dissipation .. . . . . . . • . . . • . . • • • . • • . • . • • . . • . . . • . . . . . . . • • . • • . . • . • . . • . • .• 1W
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions. above those indicated in the operational sections of the
Specifications is not. implied. Exposure to absolute maximum rating conditions for
exfended periods may affect device reliability.

DC CHARACTERISTics
TEST CONDITIONS: TA = O°C to +70°C, Vee = + 5 V ± 50/0
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

7141L
MAX

7141
MIN

MAX

Input Load Current
(All Inputs)

IINLD

VIN = 0 to 5.25V

10

10

Output Leakage Current

IOlK

S =2.4V,

10

10

Power Supply Current

lee2

VIN=5.25.
TA=O·C Output Open

45

65

Power Supply Current

lee1

VIN=5.25V,
TA=O·C Output Open

50

70

In. At Low Voltage
Input High Voltage
Output Low Voltiige
Output High Voltage

Vil
VIH
VOL
VOH

UNITS

p.A

Vilo = .0.4V to Vee

I:J

-0.5
2.0
IOl= 3.2mA
IOH ='-200p.A

2.4

0.8

-D.5

0.8

Vee
0.4

2.0

Vee
0.4

Vee

2.4

Vee

rnA

V

CAPACITANCE
PARAMETER

InpuVOutput Capacitance
Input Capacitance

SYMBOL

CliO'
CIN

TEST CONDITIONS

MAX

UNIT

VIIO = OV
VIN = OV

5
5

pF

NOTE: These parameters are periodically sampled, not iOO% tested.

DEVICE OPERATION
When W is high, the data input buffers are inhibited to pre·
vent erroneous data from getting into the array. As long as
W remains high, the data stored cannot be changed by the
addresses, Chip select, or data I/O voltage levels and timing
t!'ans!t!cns~, The block dlagram'also shows data s~orage cannot be changed by W, the, addresses, orthe input data as
long as S is high. Either S or Wby Itself, or in conjunction

with the other, can prevent the extraneous writing due to
Signal transitions.
A READ occurs during the overlap of'S" low and W high. Data
within the array can only be changed during a Write time,
aeiined as the overiap of S loW and W low. To prevent the
loss of data, the addresses must be properly establiShed
during the entire Write time plus t wr.

8·220

IM7141
AC CHARACTERISTICS
TEST CONDITIONS:TA= ODC to+70 DC, Vee = +5V±5%
tr = tf = 10ns, VIL = 0.8V, VIH = 2.0V, Output Load = 1 TTL Gate and lOOpF
Input and output timing reference .Ievel

= 1.5V

READ CYCLE
PARAMETER

SYMBOL

Read Cycle

tre

tn

Access Time

7141L2,7141-2 . 7141L3; 7141-3
MIN
MAX
MIN
MAX
200

teo

S to Output Active

tex

0

Output 3 state from Deselect.

tOld
t oha

10

Output Hold from Address Change

60

0
10

100
0

0

0

450

·300
100

7Q

UNIT~

450

300
200

S to Output Valid

7141L, 7141
MIN
MAX

80

0

ns

100

10

WRIT,E CYCLE·
PARAMETER

SYMBOL

7141L2,7141-2
MIN
MAX

7141L3,7141-3
MAX
MIN

' 7141L,7141
MAX·
MIN

Write Time Cycle

twe

200

300

450

Write Time

tw

120

150

200

Write Release Time

twr'

0

0

Output 3 State from Write

tolW

P

Data ·to Write Time Overlap

tdw

150

200

Data Hold from Write 'Time

tdh
taw
tew

120
,15

15

15

0

0
150

200

Address setup Time
S Select Pulse Width '

60

120

0

0
80

0

100

0

TIMING DIAGRAMS
READ CYCLE

·.ADDRESS

WRITE CYCLE

~rI~----~--~-----r-J~--~

DOUT--__________________

~

DIN

Note: 1.W is high for a READ cycle.

8·221

UNITS

-----------~Yee

Al

--.oGND

A2

A3

•

MEMORY ARRAY
64 ROWS BY
64 COLUMNS

Iv.
As

Ao

Yee

Al

As

A2

A7 '

A3

As

Iv.

As

As

Ala

DOUT

A11

Vi
DOUT

W

DIN

5

GND

DIN

Aa
Al
A2

A3
Iv.
As
As
A7

-

GND

PIN NAMES
Ao-All
DIN
DOUT

W
S

ADDRESS INPUTS
DATA INPUT
DATA OUTPUT
WRITE ENABLE
CHIP SELECT

)

ORDERING INFORMAtiON
PART NUMBER
IM7141·2MJN
. IM7141-.3MJN
IM7141MJN

ACCESS TIME
200ns
300ns
450ns

8·223

DOUT

As
A9
Ala
All
DIN

(outline dwg IN)

5

. IM7141M

PACKAGE
CERDIP
CERDIP
CERDIP .

Eil

IM7141M

O~OIL

ABSOLUTEIVIAXIMUM RATINGS
Operating Temperature ...................................... -50°C to +125°C
Storage Temperature ; ...•................................... , ---e5° C to +150° C
Voltage on any Pin to Ground ... : .......•......................... -o.5V to +7V
"Power Dissipation ........................... ;............................. 1W
NOTE: Stresses above those listed under Absolute Maximum Ratings m.ay cause permanent
damage to the device. These are stress ratings only. and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
'
'

DC CHARACTERISTICS
TEST CONDITIONS: TA=-55°Cto +125°C,Vcc= +5V,±10%
PARAMETER
Input Load Current'

SYMBOL

TEST CONDITIONS

MAX

MIN

IINLD

VIN = OV to 5.5V "

10

10LK

S = 204V,

10

VI/O = O.4V to Vcc
VIN = 5.5V, Output Open
TA =25·C

65

(All Inputs)
Output Leakage Current

I:)

Power Supply Current

ICCl

Power Supply Current

ICC2

Input Low Voltage
Input High Voltage
Output Low Voltage

VIL
VIH
VOL

Output High Voltage

VOH

90

VIN = 5.5V! Output Open '
TA = -,55·C.
-0.5
2,.0

,

IOL = 3.2mA
IOH = -200p.A

UNITS

p.A

rnA

0.8
V

Vcc
004

2.4

VCC

CAPACITANCE
PARAMETER
Input/Output Capacitance

Input Capacitance

SYMBOL

TEST CONDITIONS

MAX

= OV
VIN = OV

5

VIIO

CliO
CIN

5

UNIT

pF

NOTE: These parameters are periodically sampled. not 100% tested:

DEVICE OPERATION
When W is high, the data input bufiers are inhibited to
prevent erroneous data from getting into the array. As long
as W remains high the data stored cannot be changed by
the addresses, Chip Select, or data input voltage levels
and timing transitions. The block diagram also shows data
storage cannot be changed by 'w the addresses, or the
input data as long as S "is high. Either, S or W by itself,

or ,in conjunction with the other, can prevent extraneous
writing due to signal1ransitions.
A RJ:AD occurs during the overlap of S low and W high.

D3ta 'vvlthii1.the ai'jay can only be changed during a Write

, , time, defined as the overlap of S low and W low. To pre·
vent the loss data, the addresses must be properly'
established during the entire Write time plus tWR'

8-224

IM714fM

O~OIL

AC CHARACTERISTICS
TEST CONDITIONS: TA = -55°C to+125°C, Vee = =5V ±10%
tr = tf = 10ns, VIL = 0.8V, VIH = 2.0V, Output Load = 1 TTL Gate and 100pF
Input and output timing reference level = 1.5V

·READ CYCLE
PARAMETER
Read Cycle
.Access Time

SYMBOL
tre
taa

IM7141-2M
MAX
MIN

IM7141-3M
MIN
MAX

IM7141M
MIN
MAX

200

300

450

S to Output Valid

teo

S to Output Active

tex

0

Output 3 State from Deselect

totd
toha

10

Output Hold ·from Address Change

0

200

300

70

100
0

60

0

450
100
0

80

10

UNITS

0

ns

100

10

WRITE CYCLE
PARAMETER
Write Time Cycle
Write Time
Write Release Time
Output 3 State from Write
Data to Write Time Overlap
Data Hold from Write Time
Address Setup Time
S Select Pulse Width

IM7141-2M'
MIN
MAX

IM7141-3M
MAX
MIN

IM7141M
MIN
MAX

tw.e
.tw

200

300

450

120

150

200

twr
t otw

0
0

0

tdw
tdh

120

150

15

15

200
. 15

taw
tew

0

0
150

200

SYMBOL

60

0

120

0
80

0

0

TIMING DIAGRAMS
READ CYCLE

WRITE CYCLE

S

s
toha

Vi

DOUT

DIN

Note: 1. Wis high for a READ cycle.

8·225

UNITS

100

ns

·O~OlL

IM7141M
7141 BIT MAP DIAGRAM
Vee

A7A13AoA1A2.A3

r----r-----,

63 ....----....--......

~~~"='~~ 0
15"--015-0
15-015-0

GROUND

/
8-226

IM7332
32,768 BIT
(4096 X 8) HMOS ROM
FEATURES
,.•
•
•
•
•
•
•

GENERAL DESCRIPTION

High Speed - 300ns Maximum access time
Completely static", no clock required
Single + 5V supply
.
Fully TTL Compatible
Two programmable Chip Selects
Three-state outputs
Industry stamdard 24 lead pinout

The IM7332 is a 32,768 bit read-only memory (ROM)
. organized 4096 words,by 8 bits, The device is fabricated using Intersil's HMOS technology to minimize cell area and optimize circuit performance.
Inputs and three-state outputs are FrL compatible and
allow for direct interfacing to common bus structures. Two
chip select inputs which are programmable to either active
high or active low, facilitate ease of memory expansion.
The IM7332 operates over SV ±S% at 4SmA with an access
time of 300ns,

LOGICAL BLOCK DIAGRAM

PIN
CONFIGURATION

LOGIC SYMBOL

A3
5,/5, 52/52

A4

vcc

A5
128 x 256

ROW
DECODER

A6

vcc

A7

MEMORY

ARRAY

AO

. A6

A8

A1

AS

A9

A2

AS

A4

A9

52/52
5,/5,

A3

A3
A2
A1

A10
A11

AO

Q7

A7

AO ---~----<
A1

--------<

A2 ----~"5I
A10

-------1

A11

-------1

A4
AS
A6

QO

Q6

A7
. A8,

Q1

QS

A9

Q2

Q4

A10

GND

Q3

A11

QO
Q1
Q2
IM7332

Q3
Q4
QS
Q6
Q7

GND.

(outline. dwgsJG, PG)

07

06

05

04

03

02

01

00

ORDERING INFORMATION
PART NUMBER·
IM7332CPG
IM7332 CJG

PACKAGE
24 Pin PLASTIC
24 Pin CERDIP

PIN NAMES
TEMP; RANGE
O·C to
O·C to

+ 70·C
+ 70·C

.
.
. '
.
NOTE: Plastic package not yet available - pending qualification

AO -

A11

00 - 07
S1 /S1, S2/S2

ADDRESS INPUTS
DATA OUTPUTS
PROGRAMMABLE CHIP SELECTS

m

o~on.

IM7332
ABSOLUTE MAXIMUII!! RATINGS
'Supply Voltage ................................................... + 7.011
Voltage on Any Pin Relative toGND . . . . . .. . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
Commercial Operating Jemperature Range ..................... O°C to + 70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to + 150°C
Power Dissipation ..................... : .............................. ' 1W

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. These are stress ratings only and'functlonal operation of the device at these
or any other conditions above those Indlcat(ld In the operational sections of the specifications Is
not Implied. Exposure to absolute maximum, rating conditions for extended periods may affect
device reliability.

TEST CONDITIONS:Vcc = 5V± 5%, TA = O°C to

DESCRIPTION
Input High Voltage

SYMBOL

Input Low Voltage

VIH
Vil

Input Leakage Current

IILK

+ 70°C'

TEST CONDITIONS

MIN.
2.0
-0.5

Output Low Voltage

Val

Output Leakage Current

IOlK

Operating Supply Current

IcC

= OV to 5.25V
=-100JLA
S1/81 = S2/82 = 2.0V10.8V
lOUT = t6mA
S1/81 = S2/82 = 2.0V/0.8V
VOUT = OV to 5.25V
S1/81 = S2/82 = 0.8V/2.0V
TA = O°C, D,ata Out Open
VIN = 5.25V, S1/81 = S2/82 =

Input Capacitance ,

CIN

Vcc

Output Capacitance

COUT

VCC

VIN

, -10

LIMITS
TYP.

MAX.

UNIT

Vcc
0.8

V

10

/LA

lOUT

Output High Voltage

VOH

2.0V/0.8V

= 5.0V, VIN = 2.0V
= 5.0V, VOUT = 2.0V

NOTE: 1. Typical values are measured at Vee = 5.0V and TA = +25'C.
2. Capacitance values are, sampled, not 100% tested.

8-228

2.4
V
0.4
-10

10

,.A

45

mA

7
10

pF

O~OIl,

IM7332
AC CHARACTERISTICS'
DESCRIPTION

, SYMBOL

JEDEC SYMBOL

'taa

TAVQV

. Address Access Time
Chip Select to Low Impedance

TSVQX
TSVQV '.

Chip Select Delay

tlz
teo

Chip Deselect Delay

tdf

. TSXQZ

Output Hold Time

toh

TAXQX

TYP

MIN

MAX

UNIT

300
20
100

ns

100
20

READ CYCLE TIMING

~________~VA_L_ID________-J~~

aD - a7

_ _ _ _ _ _ _ _ _ __ _

------------~

Vee

AC TEST CONDITIONS
2.SKO

Vee: .....................' ................ SV±S%
TA ' ...... , .... , ...... , , .............. , O·C to 70·C
Input rise and fall times .......... "

20ns (10% to 90%)

Input and output reference level .. , ........ ".' .... 1.SV

DOUT

0--.----.

I-

100PF (INCLUDES SCOPE AND
, JIG CAPACITANCE)
.

OUTPUT LOAD CIRCUIT

8·229

IM7364
65,536 BIT
"(8192 x 8) HMOS ROM
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•

The IM7364 is a 65,536 bit read-only memory (ROM)
organized 8192 words by 8 bits. The device ,Is fabricated using Intersil's HMOS technology to minimize cell area and
.
optimize circuit performance.

High Speed - 350ns Maximum access time
Completely static -. no clock required
Single + 5V supply " '
Fully TTL Compatible
Two Programmable Chip Select
Three-state outputs
Industry standard 24 lead pinout

Inputs and three-state outputs are TIL compatible and
allow for direct Interfacing to common bus structures. A
chip select input, which is programmable to either active
high or a~tive low, facilitates ease of memory expansion.
The IM7364 operates over 5V±5% at 60mA with an,access time of 350ns.

LOGICAL BLOCK DIAGRAM

LOGIC SYMBOL

PIN
CONFIGURATION

A3
A4
AS
A6
A7

sill

256 X 256
MEMORY
ARRAY

ROW
DECODER

AB
A9
A12

A7
A6

VCC
AB

AO
A'j

AS
A4
A3
A2
Al

A9
A12
SIS
Al0
All
Q7
Q6
QS
Q4
Q3

A2
A3
A4
AS

Ao------i

m

Ql

Al-·-----i
COLUMN
DECODER

A2------i

AlO

:

A6
A7
AB
A9
Al0
All
A12

VCC

'",7364

QO
Ql
Q2
Q3
Q4
Q5
Q6
Q7

GND

All------i
rcc~~~~

(outline dwgs JG, PG)

SIS

Q7

Q6

QS

Q4

Q3

Q2

Ql

QO

ORDERING INFORMATION
PART NUMBER

IM7364CPG

PACKAGE

24 Pin PLASTIC
24 Pin CERDiP

PIN NAMES

Ao -

TEMP. RANGE

O·C to + 70 De

I

NOTE: Plastic package not yet available - pending qualitication,

8-230

QO -Q7

ADDRESS INPUTS
DATA OUTPUTS

SIS

• • • _..:::;, ,,.,, ...... ,~ ........ ' - Vl11r

A12

PQnf:=:CA .... a.AADI c ,...Wln ..;;J~Lr::\.I1
C"f":"'1 r-_T

O~OIL

IM736.4
ABSOLUTE MAXIMUM RATINGS

Supply Voltage ................•.................................. + 7.0V
Voltage on Any Pin Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
Commerc.ial Operating Temperature Range .• : ... , . . . . . . . . . . . . .. 0 ·c, to + 70'C
Storage Temperature ..................................... -55'Cto +150'C
Power Dissipation ....... ',' ........ , .................•. ., ...... '.' . " .' ....1W
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause perma·
nent damage to the device.. These are stress ratings only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
the specifications Is not implied. Exposure fo absolute maximum rating conditions for extend·
ed periods may affect device reliability.

DC CHARACTERISTICS
TESTCONQITIONS: Vee = 5V± 5%,TA = O'Cto + 70'C

DESCJIIPTIO~

Input High Voltage
Input Low Voltage
Input Leakage Current

SYMBOL
VIH
VIL
IILK

Output High Voltage

VOH

Output Low Voltage

VOL

Output Leakage Current

IOLK

.'

.

,Operating Supply'Current
Input qapacitance
Output Capacitance

Icc
CIN
Cout

TEST CONDITIONS

MIN..

VIN = OV to 5.25V

2.0
-0.5
-10

lOUT = -100,..A
SIS = 2.0V/0.BV
lOUT = 1.SmA
SIS = 2.0V/0.BV
VOUT = OV to 5.25V
SIS = 0.8V 12.0V
TA = 0 ·c, Data Out Open
VIN = 5.25V, SIS = 2.0V/0.8V
VCC = 5.0V, VIN = 2.0V
Vcc ·=5.0V, VOUT = 2.0V

=

NOTE: 1. Typical values are measured at Vee
5.0V and TA
2. Capacitance values are sampled, not 100% tested.

.....

.
. ......... .

:

= +25'C.

",

8-231

LIMITS
TYP.

MAX.
Vcc
O.B
10

2.4

UNIT

V
p.A

V
0.4

-10

10

p.A

SO
7
10

mA
pF

O~OIL

IM7384
AC CHARACTERISTICS

DESCRIPTION
Address Access Time
Chip Select to Low Impedance
Chip Select Delay
Chip Deselect Delay
Output H91d Time

SYMBOL

JEDEC SYMBOL

taa

TAVQV
TSVQX
TSVQV
TSXQZ
TAXQX

tlz
tco
tdf
toh

MIN

MAX

TYP

UNIT

350
20
12'0
120

ns

20

READ CYCLE TIMING

~_________~~L_ID________~1<~

____________

~

--------~--------~

Qo -

E:J

Q7 --------~-------------~

AC TeST CONDITIONS

Vee

Vee ........................................ 5V±5%
TA ......... '. , .•.............. '. . . . . . . .. O·C to 70·C
Input rise and fall times ............ 20ns (10% to 90%)
"Input and output reference level ................ " 1.5V

2.SKO
DOUT

0----.------.

I-=-

100PF (INCLUDES SCOPE
AND JIG
CAPAC!TANCE)

OUTPUT LOAD CIRCUIT

8·232

IM82C43
CMOS Input/Output
Expander

U~UlL

FEATURES

DESCRIPTION

• 8048/41 compatible I/O expander
• CMOS pin-for-pin replacement for standard
NMOS 8243

The I ntersill M82C43 is a CMOS input/output expander
equivalent to the NMOS 8243. It is designed to provide
I/O expansion for the 8048, and 8041 single-.chip
microcomputers.
The 24-pin IM82C43 provides four 4~bit bidirectional
I/O ports; 8048/41 instruptions implement accumulator/l M82C43 porttransfers, as well as log ical AN D/OR
operations. P20-P23 on the8048/41 s~rves asa4-bitbus
for transfer of control and data to the IM82C43.

• Low power dissipation - typically 25""W active
• Extended temperature range: -40 0 C to +85 0 C
• Four 4-bit I/O ports in 24-pin DIP
• Logical ANDIOR directly to ports
• High output drive
• High noise immunity -

typically 33%

• Single +5V supply

PIN CONFIGURATION

LOGICAL BLOCK DIAGRAM

(OUTLINE DRAWING JG, PG)

PORT 4

P50

PORT 5

PORT 2

MUX

Vee

P40

P51

P41

P52

P42

P53

P43

P60

CS

P61

PROG

P62

P23

P63

1'22

P73

P21

P72

P20
GND

P70

PORT6

ORDERING INFORMATION

PORT 7

8-233

E8

IM82C43
NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratingsonly, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affec, device reliability.

ABSOLUTE MAXIMUM RATINGS
Operating Temperature ........... -40° C to +85° C
Storage Temperature ...... ; .... -65°C to +150°C
, Voltage on Any Pin
With Respect to Ground .. Ground -0.5 toVee +0.5
Power Dissipation .............. , . . . . . . . . . . .. 1 W

D.C. AND OPERATING CHARACTERISTICS
TA

= O°C to 70°C, Vee = 5V ±10%
PARAMETER

SYMBOL

MIN.,

CONDITIONS

,

Input Low Voltage

VIL

Input High Voltage

VIH

Output Low Voltage Ports 4-7

VOL

Output High Voltage Ports 4-7

VOH

Input Leakage Ports 4-7, Port 2, CS, PROG
Output Low Voltage Port 2

IiLK
VOL

Supply Current

Icc

WRITE mode,
All outputs open,
tk =700ns

Output Voltage Port ::1

VOH

Sum of all 10L from 16 Outputs

10L

10H = 100ilA
10mA Eaeh Pin

SYMBOL

TYP.

• -0.5
Vec-2.O
;

= 30mA
10H = 240llA
Vin = Vec to OV
10L = 0.6 mA
10L

MAX.

UNITS

0.8

V

Vee+0.5

V

0040

V

1.0

IlA

2.8

V

-1.0
1

0.1

V

!;.O

mA

2.8

mA
160

A.C. CHARAC,TERISTICS
TA

= O°C to

70°C, Vee

= 5V

±10%
CONDITIONS

MIN.

Code Valid Before PROG

tA

80 pF Load

,100

Code Valid After PROG

ts

20 pF Load

60

ns

Data Valid Before PROG

tc

80 pF Load

140

, ns

PARAMETER

Data Valid After PROG

to

20 pF Load

20

Floating After PROG

tH

20 pF Load

0

PROG Negative Pulse Width

tK

CS Valid Beforel After PROG

tos
tpo

TYP.

MAX.

UNITS
ns

ns
150

400

ns
ns

"

Ports 4-7 Valid After PROG
Ports 4-7 Valid BeforelAfter PROG

tLP1

Port 2 Valid After PROG

'tACC

1:1 FUNCTIONALp~IN

50
100 pF Load
0
80 pF Load

In

Number

Function

PROG

7

Clock Input. The falling edge of PROG . ,
indicates valid address and control
. information on P20-P23, while the
rising edge indicates valid data on P20P23,
'
'

es

6

Chip select input. When HIGH, it dis-..
abies PROG. thus inhibiting change in
'
.
ciutput or internal status.

P20-P23

8-1 i

Four ,bit bidireCtional port ,carrying
address and control bits on 'the falling,
edge of PROG and 1/0, data on the
"
rising edge of PRO,G, " ,

2-5
1,21-23
17-20
13-16

Four bit bidirectional 110 ports. May be ..
configured for input, ,tri-state output
(READ mode) or latched output. Data
on pins P20-23 may be directly written,
or ANDed or ORed with previous data.

,GND

12

Circuil ground potential

Vee'

24

+5 vol' supply.

ns
ns

500

ns

FUNCTIONAL DESCRIPTION

DESCRIPTION

.Designator

P40-P43
P50-P53
P60-P63
.. P70-P73

ns
400

The IM82C43 ,has four 4-bit I/O' ports, which are
addressed as Ports 4 thru7 by the processor, The
following operations may be performed on these ports:
• Transfer acc,umulator to port (write)
• Transfer pmt to accumulator (read)
• AND ,accumUlator to port
• OR accumulator te> port
All communication between the microcomputer and
the 82C430ccurs,over Port 2 (P20-P23) with timing
provided, bY an 'output pulse on the PROG pin of the
processor: Each. data transfer consists of two 4-bit
.'
.. ,'"
nibbles:
• The first contains the' port address and command
to the 82C43.This data is present on Port 2 during
'the high-to-Iow transition of' PROG and. is
encoded as shown in the table on page 8~235.
'
• The second contains the, four bits of data
. associated w'ith the instruction, The low-to-high
" transition of PROG indicates the presen~e of data.

8-234

'
.
"
,
'
"

IM82C43
Port Address And Command Format
P23

P22

INSTRUCTION
CODE

P21

P20

0
0
1
1

0
1
0
1

Read
Write
ORlD
ANlD

0
0
1
1

0
1
0
1

ADDRESS
CODE
Port
Port
Port
Port

4
5
6
7

mode change from write to read should be ignored; all
following reads are valid. This is to allow the external
driver on the port to settle after the first read instruction .
removes the low impedance drive from thE:! 82C43 output. A read of any port will leave that port in a high
impedance state.

I/O Expansion

Write Modes
The device has ttiree write modes. MOVD P,A directly
writes new data into the selected port with old ,data
being lost; ORlD P,A ORs the new data with the old
data andwrites it to the port; and ANlD P,A ANDs new
data with old data and writes it to the port.

The use of a single 82C43 with an 80C48 or 8021 is
shown .in figure 1. If more ports are required, more
82C43s can be added as shown in figure 2. Here, the
upper nibble of port 2 is used to select one of the
82C43s. Two lines could have been decoded but that
would require additional hardware.,Assuming that the
leftmost 82C43 chip select is connected to P24, the
instructions to select and de-select would be:

After the designated operation is performed, the data
is latched and directed to the port. The old data
remains latched until the new data is written.

MOV A, #OEFH
OUTl P2, A

P24= 0
Enable, 82C43

MOV A, #OFFH
OUTl P2, A

Disable All
Send It

Read Mode
The device has one read mode. The command and port
address are latched from port 2 on the high-to-Iow
transition of the PROG pin. As soon as the read
operation and port address are decoded, the
designated port output buffers are disabled and the
input buffers enabled. The read operation is terminated by the low-to-high transition of the PROG pin.
. The port selected is switched to. the high impedance
state while port 2 is returned to the input mode.
Normally a port will be in an output mode (write) or
input mode (read). The first read of a port, following a

Power On Initialization
Initial application of power to the device forces ports 4,
5,6, and 7 to the high impedance state and port 2 to the
input mode. The PROG pin may be either high or low
when power is applied. The first high-to-Iow transition
of PROG causes the device to exit the power-on mode.
, The power-on sequence is initiated if Vee drops below
one volt.

WAVEFORMS

PROG

PORT2

P{)RT 2

PORTS 4·7

PREVIOUS OUTPUT VALID

_

PORTS 4·7

tiP'

INPUT VALID

te,

8-235

IM82C43
OUTPUT EXPANDER TIMING

TYPICAL APPLICATIONS.

BITS 3,2

EXPANDER INTERFACE

PROG

~cs

P20·P23

P4
PROG

4

I/O

4

I/O

P6

4

I/O

P7

4--

.~

---<

OO}
READ
01
WRITE

I

X

AD~RESS (4·BITS)

)

10

OR

11

AND

BITS 1,0

OO}
10
01

DATA (4·BITS)

PORT
~DDRESS

.11

PROG
P5

,8021

OR
8048

"

82C43

P20·P23

4

DATA IN

P2

>

I/O

Note:
,
,
The 82C43 does not have the same quasi-bidirectional port structure
as P1/P2 of the 80C48. When a "1" is written to P4-7 olthe 82C43it is '
a "hard 1" (low impedance to +SV) which cannot be pulled low by an
external device. All 4 bits of any port can be switched from output
mode to, input mode by executing a dummy read which leaves the
port in a high impedance (no pullup or pulldown) state.

Figure 1

USING MULTIPLE 82C43s
P27

BUS

PORT 1

8048
PORT2
PROG~----------------~----------------~----------------~------------------J

Figure 2

'.

/

8-236

G.ENERAL DESCRIPTION

FEATURES
•
,.
•
•
•
•
•
•
•
•

The 82HM137 Is a high speed 4096 bit read-only memory
(RQM) organized 1024 words by .4 bits_ ThE! device is
fabricated using Intersll's SELOX _HMOS technology, a
single-layer polysilicon; selective-oxidation arsenic diffu- .
sion process, to minimize memory cell area and optimize
circuit performance.

High speed.-70ns maximum. access time
Low Power 630mW (82HM137C)
Completely statl.c ....; no clock 'required
Single + 5V supply
Fully TTL compatible
Two Chip Select Inputs
Three-state outputs
883B processing available
Mil temp operation (- 55°C to + 125°C) available
Pinout and functionally compatible· to Industry
standard Bipolar PROMS, using only 75%
the power

The 82HM137 is an exact pinout and function replacement
, for industry standard 1024 x 4 Bipolar PROMs.
Inputs and t!lree-state outputs are TIL compatible and
allow for direct Interfacing to common bus structures. Two
chip select Inputs allow for ease of memory expansion.
The. standard 82HM137 operates over 5V ±5% at 120mA
with an access time of 70ns

LOGICAL BLOCK DIAGRAM.

PI,N CONFIGURATION

A4~

A6C~PVCC

As~

ASC 2
17 pA7
A4C 3
16 pA6
15 pA6
A3C 4
82HM137
AOC S
14 pao

A6,--t:L=

64 X64

ROW

A7~ DECODER ~

MEMORY
ARRAy

A6~
A9~

-

,.

'5

Al

~

A2

::>

A:J

~

Ii={)S2

COLUMN
DECODER.

-

.'

Ao·A9
QO·Q3
81,82

ADDRESS INPUTS
. DATA OUTPUTS
CHIP SELECTS

ORDERING INFORMATION
TEMP.~NGE

PART NUMBER

PACKAGE

82HM137CPN

18. PIN PLASTIC

O·C to + 75·C

82HM137CJN

18 PIN CERDIP

O·C to + 75·C

82HM137MJN/883B

18 PIN CEROIP

NOTE: Plastic package not yet available
-·pending qualification

-

":55·C to +125·C

02
12
11 pa3

,

,

10

9

I:l 52

LOGIC SYMBOL

~t

.tsy'tsy'L?~

Ao"":'

Do

Al-

02

01

PROM REPLACEMENT
GUIDE
SUPPLIER
AMD
FAIRCHILD
HARRIS.
MMI
MOTOROLA
NATIONAL
RAYTHEON"
SIGNETICS
TI

8-237

I:l

(outline dwgs IN, PN)

DATA OUTPUT

. 03

PIN NAMES

13 pa1

A2C 7
SIC 8

GN~C

I

Ao

A1C 6

PART NUMBER
AM27S33
93453
HM7643
6353
MCM7643
74S573
29641
82S137
TBP24S41

Vce

I

A2A:J-

-Qo

A4.,.-

!-,-Ql

As-

82HM1~7

A6-

!-'-Q2
!-,-Q3

A7- .

A6Ag

~

-

GND

D~DIl.

82HM137
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .•..........•.....'..................................... + 7V
Voltage On Any Pin Relative to GND '............. ; ...... : ....... ,' - 0.5V to + 7.0V
Commercial Operating Temperature Range ........ .'.............
O' to + 75'C
Military Operating Temperature Range ..•.................... -55'C to 4- ,125'C
Storage Temperature ...•...•.. :.......................... - 65'0 to + 150'C
Power Dissipation .....................•....................• '.......•.. 1W
NOT E: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are, stress ratings only, and functional operation of the device at these or any
other conditions above those Indicated In the operational sections of this specification Is not implied. Exposure to absoiute maxlrTllim rating conditioils for extended periods of time may affect
"
device 'reliability.
'

"'"

DC CHARACTERISTICS
TEST CONDITIONS: 82HM137C: VCC = ,5.0V± 5%,TA =
82HM137M: Vcc
5.0V ± 10%, TA

=

DESCRIPTION

SYMBOL

Input High Voltage

VIH

Input Low Voltage

Vil

,

o· to

+75'C
+ 125·C ' '

= - 55,·C to

82HM137C
MIN TYP, MAX

TEST CONDITIONS

2.0

Input Leakage Current

IllK

VIN = OV to 5.25V

-20

VOH

lOUT = -2mA

2.4

Output Low Voltage.

VOL

51 = 52 = ~85V
lOUT = 1SmA

81
Output Leakage Current

10lK
leeOP1
leeOP2

-1.0
·-20

20

0.45

= 52 = 0..85

VOUT ,= OV to 5.25V
VIN - 5.25V
VIN,= 5.5V

,40

-40

..

51:= 52 '", 0.85V

..

'p.A

V

p.A

,mA

.,

Input Capacitance

CIN

Vee = 5.0V, VIN = 2.0V

5

5

COUl:

Vee = 5.0V, Vour = 2.0V

8

-8

+25·C

"

8-238

0.5

130

Output Capacitance

"i

.

SO

-60

TA = -55°C

NOTES:L Typical values ,are measured at Vee = 5.0V and fA
2. Capacitance values are sampled, no~ 100% tested.

V

120

Data Out Open
,11/0.'= OmA

,

UNITS

,.

'

TA = O·C
Operating Supply Current

Vee
0.8

2.4

.'

S1 = ,S2 =, 2.0V
Operating Supply Current

82HM137M
TYP MAX

2.0

Vee
'0.85
' 20,

-1.0

Output High Voltage

MIN

I

pF

82HM137·
AC CHARACTERISTICS

DESCRIPTION
Address Access Time
Chip Enable Access Time

tce

JEDEC
SYMBOL
TAVQV
TSVQV

tcd

TSXQZ

SYMBOL
taa

Output Disable Time

82HM137C
TYP
MAX
60
7.'0
30
40

82HM137M
TVP
MAX
80
70

40'

30

30

40

30

40

UNITS
./

ns

NOTE: Superior speed selection is available

Vcc

AC TEST CONDITIONS

27011
(INCLUDES SCOPE AND

82HM137C: Vee = 5.0V± 5%, TA = O· to +75·C
82HM137M: Vee = 5.0V ±10%, TA = -55·C to +125·C
Input pulse levels '- O.OV and 3.0V
Input rise and fali times - 5ns (10% to 90%)
Timing reference level - 1.5V - Inputs and outputs

DOUT 0

-

........- -.... JIG CAPACITANCE)

60011

30pF

I

OUTPUT LOAD CIRCUIT

READ CYCLE TIMING

f_',..------~~-.
,____. .,. ___VA_LI_D_._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,.-~ i:I

AO.A9 _ _ _ _....

INVALID "
HIGH

Z

VALID

I

..

-

taa

/

tee --....

~

"

'/

•

8-239

\J HIGH

VALID

1.-

'

INVALID

ted

~

Z

,

8~2HM141

D~DIL

4096 Bit
(512 x 8) HMOS ROM
GENERAL OESCRIPTION

FEATURES
•
•
•
•
•
•
•
•
•

The 82HM141 is a high speed 4,096 bit read-only memory
(ROM) organized 512 words by 8 bits. The device is
fabricated using Intersil's SELOX HMOS technology, a
single-layer polysilicon, selective-oxidation arsenic diffusion process, to minimize memory .cell area and optimize
circuit .performance.
The 82HM141 is an exact pinout and functional replacement for Industry standard 512 x 8 Bipolar PROMs.
Inputs and three-state' outputs are .TIL compatible and
allow for direct interfacing to common bus structures.
Four chip select Inputs allow for "ease of memory expansion.
The standard 82HM141 operates over 5V ± 5% at 175mA
with an access time of 70ns.
!

High speed-70ns maximum access time
Completely static - no clock required
Single + 5V supply .
Fully TTL compatible
Four chip select inputs
Three-state outputs
883B processing available
Mil temp operation ( - 55·C to + 125 ·C) available
Pinout and functionally compatible to industry·
standard Bipolar PROMs

PIN CONFIGURATION

LOGICAL !=lLOCK DIAGRAM

A7

Vee
As
NIC

A6
As
A4

51

A3

52

A2
A1

53

A7
A8

Ao

Q7

Qo

Q6

AS
A6

64 x 64
MEMORY
ARRAY

ROW
DECODER

Ao
A1

COLUMN
DECODER

A2

If]

54

Q1

Qs

Q2
GND

Q4

§1
52
53
.54

51525354 Vee

Vec~

AD

GND~

Q7 Q6

PIN NAMES
Ao-As

Q3

(outline dwgs JO, PO)
LOGIC SYMBOL

ADDRESS INPUTS

A1

PROM REPLACEMENT
GUIDE

Qo

A2

Q1

A3

PART NUMBER

A4
As

Q2 .

00-07

DATA OUTPUTS

SUPPLIER

S1, S2, S3, S4

CHIP SELECTS

AMD

AM27S31

FAIRCHILD

93448

A6

Q4

HARRIS

HM7641

A7

Qs

INTEL

3624

A8

MMI

ORDERING INFORMATION
PACKAGE
TEMP. RANGE
24 Pin PLASTIC O·C to + 75·C
24 Pin CERDiP O'C io + 75'C
82HM141 MJG/883B 24 Pin CERDIP -55·C 10+ 125°C

PART NUMBER
82HM141 CPG

NOTE: Plastic package not yet available
. pending qualification

I~I""\IIVI"I"'\L

6341
""7""''''''''''
0(0""'::10

RAYTHEON

29625

SIGNETICS

82S141

TI

TBP28S45

J\,.IATIr"\fl.IA'

8·240

82HM141

Q3

Q6
Q7

~.
--

. GND

82HM141~

AC CHARACTERISTICS·
JEDEC
DESCRIPTION
Address Access Time
. Chip Enable Access Time

SYMBOL·

SYMBOL

Output Disable Time

taa

TAVaV

tee

TSVaV
TSXaZ

ted

, 82HM141M

82HM141C
MAX

TYP

TYP

70
40 .

MAX

UNITS

90
50

ns

,

\

50

40

NOTE: Superior speed sel.ection· is ·available

AC TEST CONDITIONS
Vee

470n

82HM141C: Vee=5V±5%, TA=O°C to +75°C
82HM141M: Vee = 5V±10%,TA = -55°C to +125°C
Input pulse levels· O.OV ani:! 3.0V
Input rise and fall times· 5ns (10% to 90%)
Timing reference level·· 1.5V· Inputs and outputs

(INCLUDES SCOPE AND
Dour 0----.---4 JIG CAPACITANCE)

I

30PF

OUTPUT LOAD CIRCUIT

READ CYCLE TIMING

~

Ao-Aa

VALID
'I

INVALID

VALID

"-

'\

INVAliD

..

HIGH
Z

/.

..

-

taa

\i HIGH

VALID
tee

.,........

.

8·241

1-

ted

-J

z

82HM141
ABSOLUTE MAXIMUM RATINGS .
Supply Voltage .... , ...... , ........... , ................................... +7.0V
Voltage On Any Pin Relative to GNO •. : ....... : .............•.... -{).sv to +7.0V·
Commercial Operating Temperature Range .•..................•.. 0° C to +7SoC
Military Operating Temperature Range ...•..•.•..•...... , ...... -SsoC to +12So·C
Storage Temperature ......... ; ....................•.......... -6SoC to +1S0°C
Power O,issipation ..•........................... , ... '.' ...............•....... , 1~
: NOTE: Stresses above those listed under Absolute Maximum Rating.s may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure. to absolute maximum rating conditions for
extended periods may affect device reliability.

\

DC CHARACTERISTICS
TEST CONDITIONS: 82HM141C: Vcc=SV.±S%,TA=·O·C to + 7S·C·
82HM141M: Vcc ... SV±10%, TA = -55·Ctc +12S·C
82HM141M

82HM14tC
DESC~IPTION

. Input High Voltage
Input Low Voltage
Input Leakage Current

SYMBOL

TEST CONDITIONS

V IH
VIL

Output High Voltage

IILK
VOH

Output Low Voltage

VOL

MIN TYP MAX MIN TYP MAX

2.0
-1.0
VIN = OV to 5.2SV

-20

lour= -2niA

2.4

Vcc 2.0
0.85 -1.0
20 :"'20

UNITS

Vcc
0;80

V

20

pA

0.5

V

60

.pA

185

mA

5

pF

2.4

51 = 52 = 0.85V, S3 = S4 = 2.0V

.Output Leakage Current
Operating Supply Current·
Operating Supply Current

·IOLK
ICCOP1
lecoP2

0.4S

-

IOUT=9.6mA
51 =52 =0.85V,-S3=S4 =2.0V
VOUT=OV to S.25V
81 =52 =O.85V, S3';'S4=2.0V
VIN=5.?SV
TA=O·C
VIN =S.SV
TA = -55·C

Oat,a Out Open

-40

40

-60

1-~5

IlIo=OmA
51 = 52 = 0.85V
S3=S4=2.0V

Input Capacitance

CIN

Vce =5.0V, VIN

=2.0V

Output Capacitance

COUT

Vee =S.OV, VOUT = 2:0V

NOTES: 1. Typical values are measured at Vee = 5.0V and TA = + 25·C
.
2: Capacitance values are sampled, not 100% tested.

8·242

5
8

-

'.

8

D~Dlb

(1024
.,

~

GENERAL DESCRIPTION

FEATURES
•
•
•
•
•
•
•
•
•

X

82HM181
,8192 Bit
8) HMOS ROM

High ~peed- 70ns maximum access time
Completely static - no clock required
Single + 5V supply
F.ully TTL compatible
Four chip select inputs
Three-state outputs
883B proce~sing available
Mil temp operation ( - 55°0 to +125°C) available
Pinout and functionally compatible to industry
standard Bipolar PROMs .

The 82HM181 Is a high speed 8,192 bit read·only memory
(ROM) organized 1024 words by 8 bits. The device is
fabricated using Intersil's SELOX HMOS technology, a
single-layer polysilicon, selective·oxidation arsenic diffusion process, to minimize memory cell area and optimize
circuit performance.
The 82HM181 IS an exact pinout and functional replace- .
ment for industry standard 1k x 8 Bipolar PROMs.
Inputs and three·state outputs are TTL compatible and
allow for direct interfacing to common bus structures.
Four chip select inputs allow for ease of memory expansion.
, .
The standard 82HM181 'operates over 5V ± 5% at 175mA
with an access time of 70ns.

LOGICAL BLOCK DIAGRAM
A7

vcc·

A6

As

As

ROW
DECODER

PIN NAMES
Ao-Ag

-

00-07
Sl, S2, S3, S4

ADDRESS INPUTS
DATA OUTPUTS
CHIP SELECTS

ORDERING INFORMATION
PART NUMBER

PACKAGE'
TEMP. RANGE·
82HM181 CPG
24 Pin PLASTIC Q·C 10 + 75·C
82HM181 CJG
24 Pin CERDIP' Q·C 10 + 75·C
82HM181 MJG/883B 24PinCERDIP -55·Clo+125·C

NOTE: Plastic package not yet available
. pending qualification

64 X 128
MEMORY
ARRAY

PROM REPLACEMENT
GUIDE
SUPPLER
AMD
FAIRCHILD
HARRIS
INTEL
MMI NATIONAL
RAYTHEON
SiGNETICS
TI

8·243

PART NUMBER
AM27S181
9~451

HM7681
3628
63S881
87S181
29631
82S181
TBP28S86

A4

81

A3

82

A2

53

A1

54

Ao
Qo

Q7
Q6

Q1

Qs

Q2
GND

Q4
Q3

O~OIl.

82HM181
AC CHARACTERISTICS

JEDEC
DESCRIPTION
Address Access Time

SYMBOL

Chip Enable Access Time
Output Disable Time

taa

SYMBOL
TAVQV

tee

TSVQV

ted

TSXQZ.

82HM181C

82HM181M
,MAX

UNITS

40

90
50

ns

40

50

MAX

TYP

TYP

70

NOTE: Superior speed selection is available

Ac T.EST CONDITIONS
Vcc

47011

82HM181C: Vee=5V±5%, TA=O°C to + 75°C
82HM181M: Vee = 5V±10%, TA = -55°C to +125°C
Input pulse levels - O.OV and 3.0V
Input rise and fall times - 5ns (10% to 90%)
Timing reference level - 1.5V . Inputs and outputs

(INCLUDES SCOPE AND
DouT 0 - - - - . - - 4 JIG CAPACITANCE)

1kll

I

30pF

OUTPUT LOAD CIRCUIT

I:]

READ CYCLE TIMING

Ao·A9

INVALID

1

VALID

J

HIGH

·z

VALID

I
I-

- -

t aa

tee

.

II

!'

8-244

K

INVALID

.\1

VALID

1-

ted

·~I

HIGH

z

82HM181
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ....................................... ; ................. '. +7.0V
Voltage' On Any Pin Relative to GND .•..•.................•.•.... -{).5V to +7.0V
Commercial Operating Temperature Range •..............•...•... O°C to +75°C
Military Operating Temperature Range .............•........... -55°q to +125°C
Storage Temperature .•...•...•...•..•.••..................... --£5° C to +150°C
Power D.issipation ....•..............•....•..............•................. 1W
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation ofthe device
at these or any other conditions above those indicated in the operational sections ofthis'
'specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DC CHARACTERISTICS
TESt CONDITIONS: 82HM181C: Vee=5V±5%, TA=O°C to +75°C
.

.82HM181M:' Vee = 5V± 10%, TA = -55°C to

+ 125°C'
82HM181C

DESCRIPTION

SYMBOL

TEST CONDITIONS

. Input High Voltage

VIH

2.0

Input Low Voltage

VIL

-1.0

Input Leakage Current

IILK
VOH

Output High Voltage
Output Low Voltage

. VOL

Output Leakage Current

'I OLK

VIN= OV to 5.25V

-20

louT= -2mA
51 = 52 = 0.85V, S3 = S4 = 2.0V

2.4

Vee 2.0
0.85 "':1.0
20 -20

-40

V

20

p.A

40

0.5
-60

leeoP1

Operating...Supply Current

leeoP2

Input Capacitance

CIN
COUT

Output Capacitance

"IN=5.25V·
TA=O°C

.Data Out Open

V,

60

p.A

185

mA

pF

51 = 82 = 0.85V; 83 = 8 4 = 2~OV
Operating Supply Current

UNITS

Vce
0.80

2.4
0.45

lOUT = 9.6mA
51 = 52 = 0.85V, S3 = S4 = 2.0V
VOUT=OV to 5.25V

82HM181M

MIN TYP MAX MIN TYP MAX

175

Il/o=OmA

vIN=5.5V
51 = 52 = 0.85V
TA = ':"55°C 8 3 := S4 = 2.0V
Vee = 5.0V, VIN 2.0V

5

5

Vee = 5.0V, VouT=2.0V

8

8

:=

NOTES: 1. Typicai values are measured at Vce= 5.0V and TA = +25°C
2. Capacitance values are sampled, not 100% tested.

8-245

82HM185
8192 BIT
(2048 x'4) HMOS ROM
FEATURES

GENERAL DESCRIPTION

• High speed -:- 70ns maximum access time
• Low Power 630mW (82HM185C):
.•: Completely static - no clock required
• Single + 5V supply
• Fully TTL compatible
• Chip Select input
• Three".state outputs
• 883B processing available
• Mil temp operation (- 55°C to + 125°G) available
• Pinout and functionally compatible to industry
standard Bipolar PROMS, using only 75%
the power·

The 82HM.185 is a high speed 8192 bit read-only memory
(ROM) organizetl 2048. words by 4 bits, The device is
fabricated using lritersil's SELOX HMOS technology, a
single-layer polysllicon, selective-oxidation arsenic diffusion
process, to minimize memory celi area and optimize circuit
performance.
,
The 82HM185 is an exact pinout and function replacement
for industry standard 2048 x 4 Bipolar PROMs. Inputs and .three-state outputs are TTL compatible and allow
for direct interfacing to common bus structures. A chip select
input allows for" ease of memory expansion.
The standard 82HM185 operates over 5V ± 5% at 120mA
with an access time of 70ns.

LOGICAL BLOCK DIAGRAM

PIN CONFIGURATION
vcc
A7·
A4

128 X 64
MEMORY
ARRAY

ROW
DECODER
.

.

A8

A3

A9·

AO

QO

A1

Q1

. A9

Q2.
03

S

.(outllne dwgs IN, PN)"

LOGIC SYMBOL
Vee·

PIN NAMES
.ADDRESS INPUTS
DATA OUTPUTS
CHIP SELECT

Ao-A10

s

82HM185

ORDERING INFORMATION

Io"uu,i>""".,

PART NUMBER

... 41I1Yllu"",,,,rl'l

I .0 n,., n, • .,.T'" I TE~~,.: ~A~:~" r
PACKAGE

I ... r .. '1 rLl"\o.111V

82HM1.85CJN

18 PIN. CERDIP

82HMl85N!JN/883B

~8

PIN CERDIP

U

' " LV

'T Ii.) '-'

+ 75°C.
- 55·C to + 125·C
O·C to

NOTE: Plastic package not yet available
. pending qualification

GND

8-246

D~DIL

82HM185
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................. :....................................... + 7V
Voltage On Any Pin Relative to GND .•........•.•••........•.•. .:.. O.5V to + 7.0V
Commercial Operating Temperature Range .................••...
O· to + 75·C
Military Operating Temperature Range ........... --:............ - 55·C to + 125·C
. Storage Temperature ............•.........••.•...•......•. -65·C to +150·C
Power Dissipation .......................... : . . . . . . . . ... . . . . . . . . . . . . . . • .. 1W
NOT E: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: 82HM185C: VCC = 5.0V± 5%, TA = O· to +75·C
8~HM185M: VCC
5.0V ±10%, TA
-55·C to +125·C

=

=

82HM185
DESCRIPTION

SYMBOL

. Input High Voltage

VIH

Input Low Voltage

VIL

TEST CONDITIONS

MIN

TYP

2.0
-1.0 .

Input Leakage Current

IILK

VIN = OV to S.2SV

-20

Output High Voltage

VOH

lOUT = -2mA

2.4

Output Low Voltage

VOL

Output Leakage Current

IOlK

S=

82H",,185

MAX

MIN

MAX

UNITS

Vee

2.0

Vee

V

0.8S

-1.0

0.8

20

-20

20.

p.A

O.S

V

60

p.A

TYP

2.4

0.8SV

lOUT = 16mA

0.4S

S = 0.8SV
VOUT = OV to 5.2SV

S=
Operating Supply Current

Operating Supply Current

leeOP1

leeoP2

-40

40

-60

2.0V

VIN = S.2SV

Data Out Open

Til" = O·C

11/.0

= OmA

VIN = S.SV

S=

0.85V

120

130·

Input Capacitance .

CIN

Vee = S.OV, VIN = 2.0V

5

5

Output Capacitance

COUT

yee = S.O, VOUT = 2.0V

8

8

HOT.ES:

p.A

..

TA = -5SoC

1.

Typical values are measured at Vec = S.OV and TA = +2SoC
2. CapaCitance values are sampled, not 100% tested.

8-247

pF

·O~OI!..

82HM185
AC CHARACTERISTICS

SYMBOL

jEDEC
SYMBOL

taa

TAVQV

60

70

Chip Enable Access Time

tce

TSVQV

30

Oufput Disable Time

tcd

TSXaZ

30

DESCRIPTION
Address Access Time

82HM185C
MAX
TYP

82HM185M
TYP
MAX
70

90

40

30

SO·

40

30

SO

UNITS
ns

NOTE: Superior speed selection is available

AC TEST CONDITIONS

Vcc

2700
(INCLUDES SCOPE AND
-_._---1
JIG CAPACITANCE)
0
Dour

=
=

82HM18SC: Vee = SV± S%, TA
0 DC to + 7S% DC
82HM18SM: Vee
SV ±10%, TA
-SS~Cto +12S DC
Input pulse levels - O.OV and 3.0V .
Input rise and fall times - Sns (10% to 90%)
Timing reference level - 1.SV - Inputs and outputs.

=

\

6000

I

30pF

.

OUTPUT LOAD CIRCUIT

r.t READ CYCLE TIMING
II1I:.I AO.A10----~>f~---~----V-A-LI-D----------~--------.
S

QO·Q3

K

INVALID
HIGH
Z

'"

-

taa

VALID
i/

tce.

(

INVALID

VALID

\J

1-

----.
~

8-248

~d

~

HIGH

z

82HM191
16,384 Bit
8) HMOS ROM
GENERAL DESCRIPTION

FEATURES
•
•
•
•
•
•
•
•
•

High speed· 80ns maximum access time
Completely static - no clock required
SlnSille +5V supply
Fully TTL compatible
Three chip select Inputs
Three-state outputs
8838 processing available
Mil temp operation (- 55'C to + 125 'C) available
Pinout and functionally compatible to industry
standard Bipolar PROMs

The82HM191 is a high speed 16,384 bit read-only memory
(ROM) organized 2048 words by 8 bits. The device is
fabricated using Intersil's SELOX HMOS technology, a
single-layer polysilicon, selective-oxidation arsenic diffusion process, to minimize memory cell area and optimize
circuit performance.
The 82HM191 Is an exact pinout and fUnct.ional replacement for industry standard 2048 x 8 Bipolar PROMs.
Inputs and three-state outputs are TTL compatible and
allow for' direct Interfacing to common bus structures.
Three chip select Inputs allow for ease of memorY. expansion;
The standard 82HM191 operates over 5V±5% at 175mA
with an access time of 80ns.

PIN CONFIGURATION

LOGICAL BLOCK DIAGRAM

As
As

A7

ROW'
DECODER

128 X 128

MEMORY
ARRAY

. As

·As
AlO

M==iL--=-J
. COLUMN
DECODER

A2

A3

A7

Vee

As

As

As

A9

A4

AlO

A3

51

A2

82

A,

83

AtJ.

07

00

06

0,

05

02

04

GND

03

(outline dwgs JG, PG)

[I

LOGIC SYMBOL
51

82, 83 Vee

AI;:j

Al

PIN NAMES
Ao-A1O

(ADDRESS INPUTS

IlROM REPL.ACEMENT
GUIDE

SUPPLIER
DATA OUTPUTS
00-07
AMD
Sl, S2, Sa
CHIP SELECTS
FAIRCHILD
HARRIS
ORDERING INFORMATION
INTEL
PART NUMBER
PACKAGE
TEMP. RANGE
MMI
82HM191CPG
24 Pin PLASTIC O·C to + 75·C
NATIONAL
82HM191CJG
24 Pin CERDIPO·C to + 75·C
82HM191MJG/8838 24 Pin CERDIP -55·C to+ 125·C . RAYTHEON
SIGNETICS
NOTE: PlastiC package not yet available·
• pending qualification
TI
8-249

PART,; NUMBER
AM27S191
93511
HM76161
3636
63S1681
87S191
29681
82S191
TBP28S166

00

A2

01

.k
A4

As

02
82HM191

03
04

As

05

. A7

06

As

07

As
AlO

-

GND

O~OIL

82HM191
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................... I +7.0V
Voltage On Any Pin Relative to GND ............................. -Q,5V to +7.0V
Commercial Operating Temperature Range ....................... O°C to +75°C
Military Operating Temperature Range ......................... -55°C to +125°C
Storag!l Temperature ....................................... ;. -65°C to +150°C
Power Dissipation ......................................................... 1W
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure' to absolute maximum rating cOlJditions for
extended periods may affect device reliability.

DC CHARACTERisTICS
TEST CONDITIONS: 82HM191C: Vee=5V±5%, TA=O°C to +75°C
82HM191M:

Vce =5V±10%, TA =-55°C to + 125°C
82HM191C

DESCRIPTION

Input High Voltage
Input Low Voltage
Input Leakage Current

SYMBOL,

TEST CONDITIONS

VIH
VIL

2.0
VIN = OV to 5.25V

-20

lOUT = -2mA
81 = .85V, S2 = S3 = 2.0V

2.4

IILK
VOH

Output Low Voltage

VOL

IOUT=9.6mA
8 1 = .85V, S2 = S3 = 2.0V

Output Leakage Current

IOLK

Vout= OV to 5.25V
, 8 1= 2.0V, S2 = S3 = .85V

Operating Supply Current

leeoP1

VIN =5.25V
,TA=O°,c

20

0.45

, -40

Data Out Open

leeoP2

vIN=5.5V
TA = -55°C

Input Capacitance

CIN
COUT

Vee = 5.0V, VIN=2.0V

-20

UNITS

Vee
0.80

V

20

p.A

0.5

V

60

p.A

185

rnA

2.4

40
100

IlIo=OmA
8 1 =.85V··

Operating Supply Current

Output Capacitance

Vee 2.0
0.85 -1.0

-1.0

Output High Voltage

82HM191M

MIN TYP MAX MIN TYP MAX

-60

175
100

S2 = S3 =2.0V

Vee = 5.0V, VOUT = 2.0V

NOTES: 1. Typic~1 values are measured at Vee= 5.0VandT A = +25°C
2. Capacitance values are sampled, not 100% tested.

8·250

-

5
8

5
8

pF

O~OIb

82HM191
AC CHARACTERISTICS
JEDEC
DESCRIPTION

SYMBOL

SYMBOL

82HM191C

82HM191M

TYP

MAX

TYP

MAX

Address Access Time

taa

TAVQV

50

80

.50

100

Chip Enable Access Time

tee

TSVQV

20

40

20

50

ted

TSXQZ

20

40

20

50

Output Disable Time

UNITS
ns

NOTE: Superior speed selection is available

AC TEST CONDITIONS
Vee

4700

82HM191C: Vee=5V±5%, TA=O°Cto +75°C
82HM191M: Vee = 5V±10%, TA = -55°C to +125°C
Input pulse levels - O.OV and 3.0V
Input rise and fall times - 5ns (10% to 90%)
Timing reference le~el - 1.5V - Inputs and outputs

(INCLUDES SCOPE AND
DOUT o----t-~__t JIG CAPACITANCE)

1kO

I

30PF

OUTPUT LOAD CIRCUIT

READ CYCLE TIMING
VALID
'I

INVALID

VALID

1\

HIGH
Z

""

- --

taa

tce

1/

~

8·251

\1/

INVALID

VALID

\i

1-

ted

~

HIGH

z

,

U~OIL

NOTES:

8-252

·.Apptmdix .•

.. .,._ ... _.... _.~... .' . . . .' ... :' .:";~.dPiJLj;~:"."'.:2;.D4·:;,"

pa:~

Package Dimensions
High Reliability Processing
Application Note Summary
Chip Ordering Info.rmation·
Intersil Part Numbering System'
Sales Offices, Distributors, and Representatives
.. '

8-11
8-19
8-21

,.'."

[,::;';

8-27' :
8-29
.....

~'.~""'"

\t??<.

~

.".

'.~

~,~~

IN EIS

I

I

•

All diinensions given in inches and (millimeters).

0.209-0.21'
(5.300-5.583t

0.875
(22.225)

0.450-0.250
(11.43-6.35)

~

(~!:) MAX I

~

I·

CJ?043~ ~l.;

L,

~"(f.Oi2-ij:iii) (7.925)

SEAtiNG
PLANE,

0.178-0.181
(4.521-4.851)

1.197 1.117
(..AD< '0.886) '.

.SEATING

t

.

(4.175-~334)

p+ilQfl .

.dOor

::~~ IL

MIN

0.188-0.:210

t=="1

MAX

0.500

(12:7Oj.

0.018-0.018 ......
IO~8-0.483)

MI~

,

O.440~O.420

~RMAX
(13.335)

BO~OMVIEW

TQ·3

TO·18

. , ~(::::::.:)~
1·18.001-8.509}
0.315-0.335 'I

I,
'-.---TQ

.

0.240-0.260

(8.008-8.504,
I

•

L-

1

0.178-0.191
(4.5.,-4.85",

.

SEATING
PLANE

0.045

(~':: ~ ~ ~
~-11-

0.&00

(12.70)
MIN

(0.408:-0.483)

0190':"'0.210 .

(4B28-5.334)

TO·52

TO·39

J

0.209":"0.219

- - - - - (5.308-5.563t
1
0.188-0.191
.
~

0.050
(1.27O)MAX ""'l

_

.

...

::-I+--, ---

O.osd-O~

~EA~~::~::"-II

'u-

..
-'=
T· .'

0.360 MIN
(9.144,

(1.270-1.105) 0.G28-0.034~ .
jO.711-Q.884,
0.958-0.962
(24.333 24A35,

0.100-Uifl

(4.1.6-5.334,

•

0.:':-

(0.7~

MAX ,
0.016-0.019
, (0,406-0...".

0.142-0.152
(3.607-3.881)

B·2

f(4.775_5.33,"

"

~nm . '
U-'-r-

~I_

\0.500
(12.70)
MIN

PACKAGE OUTLINES

All dimensions given In inches and (millimeters).

R
.a::iij['D 0)~-

0.209-0.219
(5.309-5.563)

0.178-0.191

.

I~:~:'
MAX
0.018-0.019
(O.408-G.483)

TO~71

jla 0 o.
~

TO·72

(8.890-9.398)

I

~.

0.17S-0.185
(4.445-4.699)

·I~
(8.001-8.509)

'DIA

nI
W
000

~I~DIA

(4.181-4.899)i,

--L.:::::=
t Lt
Q.D40

_

SEAnNG

PLANE

0.500

0.500
MIN

(1UO,

_

LOW PROFILE

. I'

0.188-0.210

LEADS FIT INTO

('E~~ ~ ~~

0.016-0.019

D~A~ci"a:~':~)

0.!.4

--,.--~.

(15.088)

, (~:~::~:~:~ -..1

-II-,~::!::~:::,

+

-.1- \..- (0.143-1.397)
0.045-0.055

~R~

t:ttll

12.15.-2.413,

.

0.045-0.055
1(1.143-1.3.7)

~~~~I~
MIN

_

o.029-0.CJ45
(0.737-1.143)
0.028-0.034-

0.175-0.205
(4.45-5.21,

0.003-0.013 R

(0.078-0.330)

'

(o'711-\l.884~
45~

__

TO·92

TO·78
0.315-0.335
(8.001-8.509)
.
0.165-0.185 -'
14.,.,-4....'

_~_

+ • ____

.. j

----

L,

--JI

t.

)
..

.

+-=

J!&!!..

/~~ ~ nn
.018-.018 DIA
UU U UU '.483-.408)

(1.016)
MAX

0.018-0.01.
• (0.408 0.483)

TO·100

TO·99

B-3

.r'65

114.6;.-0.,."

T--

__INSULATOR

(o.889)~~
~ ~~
MAX

(8.509-7.747)

.040;"~018~

~

..

0.500 ~
(1i.7Oi
MIN

I

~.DIA
.

.J. .
ii"2YoOi M1N

~

PA.CKAGE OUTLINES

All dimensions given in inches and (millimeters).

_(:'13::,:,00~°:O) - - -

I~ (~:~:~=~::~~)

0.110:"'0.120 ~

(,~:~:~_~;~::~94_3'048)" -

(~:!:~=~:;~~) --1-(1~ ~:~=~O~~:7)

0.128-0.132
(3.251-3.353)

i

RE~--.

(

j

10.795)

O.09S-0~05

(t~~J) ~~-J
I

0.250
(6.350)
MAX

__

2 PLACES

O.500~

..(12.70-14.275) . -•

t_.____

+

0.045-0.060
(1.143-1.524)--

I

I ,__ (0,'.3'7,,0:,0.',','0,)

I

I

(2.413-2.667)_1 ::0.095-0.105-'
0026
,(2.413""",,:2.667)
I
(0:660) REF NOTE 2 - , , - _
----;--1 1-

0.019-0.026
(0.483-0.660)

(~:~:~=~:~!~)--

(~:~~;=~:!~;) __ i --

. TO·202

0.205-0.195

.

.

0.080-0.115

I

(2.032-2.921)~

....

_

....

~ 0.002

T

(4.445-4.699)

-t

'1"'--'

000--L
0.594

(15.088)

DIA HOLE (TYP) 0.045-0 055

II

"~._r.:'~

T

:I 0.175-0.185
I

(470-445)

0.017

1°·105-0.095
(2.67-2.41)

0.270
..-.0'26f[ I
-(6-.'6--j~6-.60-):,

0.406-0.483)

I

0012-0.025
(0.305-0.635)....

TO·220

I (5.21-4.95) I

~75
LE:g1~~I~ ~~:O\

1

0.020-0.035
(0.508-0.889)

1

-i~~'

~

t

0.230-0.270
(5.842-6.858)

70

.------.-

CHAMBER

0.060
(1.524)
REF

O.405-0,4~5
(H).2S7

{14.224_,5.87.51

X '5

Tr

___

0.S60-0~

0.065-0.075
(1.651-1.905 __

~

(4.,,45-4.699)

I .-(~.~:~:~:~:~

(2.~!iO+3.0~)

1.21
(30.734)

. 0.285-0.315
(1.237-8.001)

1_ 0.175-0,185

]

0.100-0.120

0.500 MIN
(12.69)

0.'05 +_0.0:'

I !t

(2.66.+ 0.000)
-0.300

~LI-·.....L1-4-""';'--"""'i5"'~OO"")-_--·--~1
, ...-

_ _ _ i5~o38~

- '

(0.143-1.397) --I .:...t- 1_ 0.045-0.055
(~:~:::.,~;~~:)R~'
'.
. (0.'43~!·:~~.055
r (1.143-1.397)

.

~j~;)
MIN

i:

',,iT

1
1

0.175-0.205
(4.45-5,21)

0.003-0.0'3
(0.076-0.330) R
-

2 LEAD CERAMIC (DH)

TO·237

0.140 :'. o.dOs

(3,55! 0.15)

r

~·3~.; gg~~l

r

0,050

l-j:----G2j"~-""'l==i

-

(1.27

!

[]

0.002

~ 0,05)

3:]-:~1

LJ

L

~ 0.407MAX
(10'3381.1~

0.015 '" 0,002
{O,38! 0,051

0.115

!
*
. ~=====~=}ol
r
- ~~.O~~
~
~:g~J
~.~
0.210

t

0,005

(5.33

!

0.15)

~

M. :".ffi

~. r~!~

,

!1.:'D

!

(5.081

~:~~~~l

0.200 (5.08)

to.006f 0.001

.

O.320~ 0,280 ( 7 . 1 1 2 1 -

0.070 (1,778)

0.125 (3.175)

0.110(2.794)
_I
0.090 (2.2861 - I

U,076)

.

1_
II
r---:-:-, II

g:g~~ :~:~:: --i -

,

:

! ,~.~~, .
~:~~ :~:~:li-I

THIS DRAWING NOT TO SCALE,

8 LEAD CERAMIC (DA)

8 LEAD FLATPACK (SA)

8·4

0,015

(0.381)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.770

(1i.5&j
0.344-0.364 ~

-i-:.cJ......*

~II
0.... -0.500

(12.19-12.7)

-

~~O.OB5-0.100

SEATING PLANE

(1.02) TVP-\j.,-

(2.16-2.54)

O.16G-O.176 RAD
(4.22,",,::4.47)

8 LEAD TO-3 CAN (KA)

8 LEAD CERDIP (JA)

.380± .010

DME'

0.310: 0.005
(7.874± 0.127)

~C1.661)

I
~ ~~:t±O~:So:.
~~'
,,-J.--"=T="-A-

(9.652:tO. 2541 1

.

--:--rT
.110(2.794)---1
•090 !fim
1

~

trf

LJ ' ~
.

!--i
L
, ,===.:1=='1

0.325 ± 0.025
(8.255 :I: 0.635)

LD.DOS (0,152)

'

=(.594)
,014 (.358)

D.126MIN
(3. 175)

.070 (1.778)
.030 T.762f

.

D.D1S
0.008 (0,203)

O.240~

==i===[~'

§'§D§.2§2D;::::(5.:::5"::"::)

, 0.004 {Q.iij2j

8 LE~D PLASTIC (PA)

0,070 (1,77")=:1
0.040

IT.iiffi

,10 LEAD FLATPACK (FB)

[c::::]]
~:~: :~::~ll

~

O'110 (18.034) MAX

~:~: ~

~br;:;:;::;:::;:J;jJ;;t~~-.

-r-

. 0.110 12.194)

.'

I

D.09ii f2.2i6j--

14 LEAD FLATPACK (FD-1)

14 LEAD CERAMIC (DD)

8-5

0.040(1.016)
0.020 (0.5081

PACKAGE OUTLINES

All dimensions given in Inches and (millimeters).

14 LEAD FLATPACK (FD)

n

O.265~

r

0.250 (0. 635 1,

0,055 (0.1391
0.045 (0.114)

'~$$~::~i$~==,,====:;.T '.
L

.

~!!J!1!!(0.4571

""'=~~~==~t

0.0101D.254i

====c::3!1;i
"

Lo.007

~~

0.0'5 (0.38"

(~.'7 1

!

~

Lo.07D(0.,981

0.004 (0.1011

0.065 (0.165)

O."O~

0.090 (2.2861

14 LEAD FLATPACK (FD-2)

14 LEAD CERDIP (JD)

[I:::::]]

.1:::::]::3'
.
f'
1
~
.2'5(5.45'1

.

.770 (19.658) MAX

.000J.1,illI

,

.0151:

.160 MAX .

,

".

~~L"f"
r..I l 'JI'
.
! i,

.110~

',OBO (2.286)

~

.060~

.046 (1.143)

B-

(4r'"

'

.

.008

.~~

~!: ~

r

.400 (10?1aSW
.330 (8. 2

.0151.3810)

16 LEAD CERAMIC (DE)

14 L.EAD PLASTIC (PO)

0.380 (9.852)
0.300 T7.62f

"
L~·;::;;:;;~;I"h~~

g~~.~

"50~~'0'5(0'38'IL
(0.20321

.'00 (2:540!

~.

O'810 120.574) MAX

O.O'9~

"==""==fli'-~Ii===,,;Jif.Ol5 (0.38"
---'1
I

•

---

==l

t

0.400 MAX

'.

,

(.0.• 61

~

0.055 (1.3971
0.280'(7.1121 0.045 (1.143J
(6:illJ,3
0.040 ~
dID.OZOIO.50S)

Ir---rrns
I

L.
1 ~:~~ i~:~~i;

1

g:~ i~~~i; -.J f

16 LEAD FLATPAC,K (FE-1)

16 LEAD FLATPACK (FE-2)

B.·6

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

16

[; ~ ~ ~~ ~ ~ ~ ~~ ;:;~;~~;

0.695 L.6531
0.705 iW,907)

.

:

0.790120.0661

D.BOo '["'3201
• 1

I. . ~::~~ :~~:~;~:~-I---

.

. L-I

0.200 MAX

HHH~~'
,
,

.

,-

~ (~~I

.235 (5.969)
.215'(5.4611

MA,X

r - 0 ' . ' O 123.1141

~I

.160 MAX

t~! l! ~ 'L 'jL

0.110
0.090 12.286).

f

L-.

~ '0151.3~lIL

.100 {2.5'4Oj

.023 (.584)
,015 r.Jiff1

.

.330

t

=~
= I..1.1ZID.
0.0,30 (0.762)

l

JL

O.115~

0.06011.5241

_

fB.J82l

.

J

0.200 ~
0.125 (3.175)

I

~

[~~~~~~~j

.
(0.127

t

T'5411}--~~~===~~~.
~.050 TVP~O'315

(1.270)

0.002

0.950

O.050~

\ . - 0.900 (22.860)'

MAX~

0.060 (1.5241~
(B.D01,
:!" 0.050

I~4.130 ± 1.27 1 -

0.015 (0.381)

-L

-r

0.025
--.lI (0.6351 REF

.
~~I~
-+0.200 15.081

-! f-- ,~r.:,

,---~=€~~=3F-~~~

,

0.110 ~ 0,07011.778)
0,090 (2.286) 0.030 (0.762)

0.023 ~
Q.015 (0.381)

18 LEA~ CERDIP (IN)

1!1 LEAD FLATPACK (FN)

B·7

.

r

; . ~~
~

18 LEAD CERAMIC (DN)

rt

I

0.060
0.008 10.2031
0.02510.6351'1
'I

PIN ONE INDICATOR

0.005

10.2031

~:~~~ :~::~~:

r=MAIX

0)023 (0.584)
0.014 (0.3561

16 LEAD PLASTIC (PE)

0.415

•

0.400 (10.16)
0.330 (8382)
.

0.20015:081

~T~==rn~ITfUr t
¥¥¥¥ ¥¥¥¥~t

.008 [i1i3)

.400 (10.16)

,060 ~
.045 (1.143)

.110 (2.7941
.090 (2.286)

I

0.015

0.008

(0.381)

MAX~

[[==JJ

.!

~5r f-~
_____,__._--iI ___14-c·1t-64_1_ ~

~ (4.064)

0.023 (O.5!!1.1
0.015 t1[3811

I

16 LEAD CERDIP (JE)

'.. [::::::j1 :~!~~] 'F
.710119.5581

I

.

O.07q 0.7781
0.030 (0.7621

0.090,(2.2861

16 LEAD (.6 x .7) CERAMIC (IE)

~

.

-~:~~

.

I I..

(s.oao)

,,
,
h,~;~r-I

I ;'

0.100 (2.54) .
TYP. ------J

I

"'''r'

I

L

I
0.780119.812) MAX-----,

,

WWWW: .,.,<=, ~
==1
~L
.,.J L .J~'~' J' 'L"·,

0,060 (1.524)

0.965 (24.51..1}
0.975 {24.7651

I

~

8

"
lO

0.32018.,28I

I

• ~
0.320 ~
0.290 (7.366)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

22 LEAD CERAMIC (OF)

18 LEAD PLASTIC (PN)

1 r'
C".--~.
~ -- ~ J' g:;~g=r
:~:~~i:LnnnrErmnruI
.
0.060
0.015

.

1.10 (27.94) MAX

0.180 (4.572)

Jf n
L Jl

IT] VI ~I V .

t-----"0.200 (5.08)

0.'25 13.1751
.

I

I

~

0.110 12.794)
0.09012.2S6i

0.07011.778)
0.030/0.762)

'

q

l~

0.O'510.~

t

"

tI

:mnfJ--rIL1751~445I-r.O'5 ~I\+-I

I

~
0.110

~I

r--

I r-

--

0.030

MAX

0115

ii.524!

-

0.023 ~
0.014 (O.3SS)

0300 (762)

J

~

'(5.08)

0.125 (3.175)
0.060 ~
0.025 (0.635)

r1_

~

-

1.47011,.938)
.410 (1,q.414)

I
I

L
1-

.023 1.5842}
,015 (.3810)

.075 (1.905)

o

7p501~';;;51)MINl

'

O.OOB 10.203)

_

0.280 J.L.!..gJ
0.245 (S.223)

li,

-0'0'51-0'3811

--r

0019 (0483)

n,

L
~

:

--I,
l

0.620 /15.748)
0.590 (14.986) -

10015 TD.381J

MAX

Dco~~t

.

.

°IIO~jj7lffi"5I"1i
~V VVV' ~ VVV~ ~
-If.-I ;.

u.lieu

Q..l~ (9 652)

0.200 (5,-oS)

I
10.76211~ ~' +

f 0081020321

22 LEAD PLASTIC (PF)

'

0.070(1.7781---1

&2Q

.110 (2.794)
]9Q /2-:286l

[ . ],r- '[:~~::;:!:J
"

_

I

!

MAX

I

_I 1__

.100 (2.540)

O.440(11.176}

~1.290 (32:~61 MAX=-=!

. __

ffinr
,

II

.160HJlM}

22 LEAD CERDIP (JF)

,

I

5lJlJTIl= =m=rm=r1r lr=---i

L05;0I'2.954IJ

,0.023/0.584)
0.Q15 (0,381)

~~I:~~~I_'

1;o183B~11

F'20013::IMAX-=--=1

I 0.008 i0203l I

I

l

C":]

0.4'01'0.4'.41
0.390 (9.906)

Lo.oos (0.152)
0.003 (0.07S)

,

I

00551'3971J
0.045 TT.143}

~;

i.£:..~)~.

0.090
0.045 (l.143)

J.

"

LO.040 (1.016)
0.010 (0.254)

24 LEAD FLATPACK (F,G)
8-8

0"36019144)

j

I

24 LEAD CERAMIC (DG)

f

0430 (10922)

PACKAGE OUTLINES

[ : : ] ..
I O.lBO

I

--' LJ

g:g~fT~
:~:tI2.~:~!
1

290

"1.

'
DQJ

All dimensions given in inches and (millimeters).

I.:
0.140

661

1 :. ; ;
MAX
ww

-=::~,1-

~

.

g:;~g g~::~~:-I

II'!I

O.~OO illID ! !1_. ~ __ ----,

g:g~~~5rm'
j
--

1.290 132.7661 MAX'--' LJ

l

.,.....-r-

I I

I.

II II

O.200~

J::

I

~
.110 (2.7941

.

.090 i2.286)

L

II

'550~l

.520 (13,208)

1- - - 0.050.0.010

.
-AJL~~=+iL'015
3Bl
. .008 (0.02032)
10.

.100n:54il1

.023 1.58421
.015 {:'38"1'O1

lj

r-

0.060 1524)

(37.465)

MAXI

.

0.110
0.090 (2.286j

0.060 (1.524)
0.046 r;:;43i

0.023 (0.58421
0.015 (0.3810)

1400 0014 .•1355 •

-

-

-I

0.OB5.0.009

±:

Ii 361 ~L2.'6' 0.231

0.610

:!:.

0.010

(15.49 ± 0.25)

~~.~~: g:'3~

~:.!:: g:g~f

~;~:~ TYP

TYP

28 LEAD CERAMIC (DI)

[::J.

.600 115.2401

.570('f4.4ji)

r
~
~~J~~WWL=tJL _2+
"360

r~=l

134.5441 MAX

L .J

iI iI

~

~

:~~g ::~'~~~:l

.175

r-~.240 131.4961 MAX1

I~::~I

J~
:~~

..680117.2721~I

.!1Q t?:1M}
.090 12.286)

28 LEAD CERDIP (JI)

.060 (1.524)
.045 [i":'1'43)

.~ ~

,015 (.3810)

28 LEAD PLASTIC (PI-1)

8-9

.00B(O:2032)

.610 115.4941

0.680 117.2721

0.610 (15.494)

~

. L::.: ~:ii: J

' b '

.610115.494)

··"lrvWfm---L-II'
---'
"----'
1
I
P= J L J~ JL, g.g~~I~1
g:~~g ~ {2.79~

0.630 {t6.D021

115.DOf 0.251

"~~ffiff~;·
~~J!
~L

24 LEAD PLASTIC (PG)

~-I

0.700 117.780'_

.

0.590' 0.010

.680(17.2721

1-1,·475

0.023 (0.584)
0.015 ID.3Bfi

_ _

. ~ (4.064)

II
I

,-

~

·
--u~
[JD

MAX~ li~1

.060 ~
.045(1.143)

I

24. LEAD CERDIP WI;rH WINDOW (JG/W)

r
~::~±t
. II

I

.

,

...570
~~
(14,478)

==

.

'.

0.OOB(0.203)

_ _ ----,

0.110 ~ 0.070 (.Lll!!I
0.090 12.2861 0.030 (a.7621

24 LEAD CERDIP (JG)

.060 11.5241 Fl.24O i31.4961

I

:0.015 ~

I .

1_

0.12513.1751----1

0.700117.780'_

.

~:~~g :g::~:-.

..

1

. '.

0.630 (16.002)

[ _OJ

I~~~~I

O.625~

0.590 114'9B61]

1
_ w w ±13'556

~

\!I

0.023 ~
0.015(0.381) _

-

0.180

O.Ot5~~ ....·

0.110 12.7941 0.070 ~
0.090 12.286) 0.030 (0.762)

__

1

0.a08 (0,2031

0.12513.1751----1

0.280 :!:. 0.003
17.112:!: 0.076)

PACKAGE OUTLINES

All dimensions given In inches and (millimeters).

~I

L:~' ~~~f 1'360(35'544)MAX'~

MAX

~~J::~Jltt
:~qh
~

r l f--

:~~:

..

2.040 (51.816) MAX

.

O.060~·

~"~-~-~m~
JI
~ ! !

0.160

r-I

0.100 (2.640)
"

Tilt--I

:!:

.

0.060 (1.524)
0.045 (1.143)

0.090 (2.2861

650 (13.970l
0.620 (13.208)

0.023 (0.5842)
0.016(0.38101

l

(g:~~)

0,008 (0.2032)

.

~::~ :~~::~::

I

i

.

[IT
. g--m-'=r~
±

0.010

I

I

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2.4OO:!: 0 024

I

0.085

±

O.6'1~~(2.'6±

0.009

0.23)

.4ffiffif::rr~~
I
I
I
.. '--1
L0.176
(4.461

i

I

I •

.

--l~.

0.010 +0.002
-0.001 .

(0.25~:g~'1

~

I

--l~ --l~ ~?;:~!,,,±oO~;~I~

~~.: ~ ~:~~

~o°.l: : g::~

..

I.

TVP.·

-M!!II' -

~

(~:g~)I
MIN.

± 0.002 10.0511

c::]
F
2.040(51.820,=1

,

(~:~:I'

r~'U"'1

r1~ TYP

TVP

48 LEAD CERAMIC (OM)
8-10

.

$MAX

JL~L .

! !~

~

0.060 (1.524)

0.Q181.2:§Zl TYP.

,0.020 (.51)

0.020 (0.508),

.

~.

0.160
(4.064)

~0'012~:jTVP'
.

MIN.
0.100

(2.540)

40 LEAD PLASTIC (PL)

.;

(1.27.0.251 r - ( 6 0 . 9 6 .

0.165
0.050 (4.191)
11.2701 MAX.

f1m::?m

~"Il,\+

L . J'
I

':"-l'

~

O.110·~

(tfx)' ro.
Ii,

'":1

40 LEAD CERAMIC (DL)

40 LEAD CERDIP (JL)

0.050

0.060 (1.270)
'jjjj"fQ lif.254}

0.570 {14.4781

I'

-+11--I

SQUARE

1=~:-~-:~~

:~~~~

F . =i
.

1-

0.050 [f.27oj

28 LEAD PL:ASTIC (PI-2)

J

O.loo~

.L- (1~~:) ~

,

.Q&!Q. (5.080)

~~i16.4941--j

~~

MAX

I

ern

r:~~~l

.175 (4.445)

2.020 (51.308)

0.001 (0.025)
.
0.660

11~~'
•

.

IDlm.mmIDlmIlDDa..................
100% INTEGRATED CIRCUIT PROCESSING

100% DISCRETE DEVICE PROCESSING

Intersil is committed to build and process integrated circuits for the Military/High-Rei market segments in conformance· with MIL-STD-883 and MIL-M-38510. Any
customer· drawing which specifies testing as set forth in
these documents will be .automatically processed to the
latest revisions of MIL-STD-883 and MIL-M-38510, unless specific requests are made to the contrary.

Intersil also offers several OPL-approved discrete products
carrying the JANTX .designation, which are screened and
qualified to the latest revisions of MI L-STD-750 and MILS-19500.

\

MIL...:STD-883B SCREENING AND QUALITY
CONFORMANCE PROGRAMS, METHODS 5004
AND 5005
The following flow chart details screening activities as carried out by Intersil for Class S, Band C requirements .

. Wafer Lot Acceptance Method
5007 (SEM only)

Traceability to Wafer RUQ

Traceability to Production Lot

.Traceability to Production Lot

Internal Visual Method 2010.
Condition A

Internal Visual" Method 2010.
Condition B

Internal Visual* Method 2010.
Condition B

Stabilization Bake 24 hours min.
Method 100B, Condition C •

Stabilization Bake 24 hours min.
. Method 100B. Condition C

Stabilization Bake 24 hours min.
.
Method 100B. Condition C

Temperature Cy"cling Method 1010,
Condition C

Temperature Cycling Method 1010.
Condition C

T'emperature Cycling Meth'od 10tO.
Condition C

Constant Acceleration Yl Orientation Method 2001, Condition E

Constant Acceleration Y1 Orienta·
tion Method 2001. Condo E (Min.)

Constant Acceleration V1 Orienta·
tion Method 2001. Condo E (Min.)

Seal Hermeticity F'ine & Gross

Seal Hermeticity Fine & Gross
Leak Method 1014

Seal Hermeticity Fine & Gross
Leak Method 1014

Leak Method 1014 (Opt.)

Particle Impact Noise Detection
Method 2020. A or B

Serialization
Pre-Burn-In Electrical Test
per Spec.

Pre·Burn·ln Electrical Test.
when specified

Burn-in Test 240 hours @ 12SoC
Min. Method 1015

Burn·in Test 160 hours @ 125°C
Min. Method 1015

Post Burn-in Electrical Test
per Spec.
Rev,rrse Bias Burn-in. 72 hours

@

150 C Min .• Method 1015, A

Post Burn:jn Electrical Test .
per Spec.
Seal Hermeticity Fine & Gross
Leak Method 1014

5~~!~~~C&iS~i~~~~:@2~PC.aJ.
Static@25°C Min, & Max, Temps.
Radiographic. 2 Views. may be any
sequence after Serialization
Method 2012
Quality Conformance Testing.
Method 5005
External Visual Method 2009

External Visual Method 2009

*Method 2017. Hybrid

8-11

External Visual Method 2009

HIGH RELIABILITY PROCESSING

QUALITY CONFORMANCE INSPECTION,
CLASSES BAND C
The following diagram presents quality conformance inspection methods for Classes Band C as performed at Intersil.

GROUP A

.1

I

I
GROUP B

I

I

l
-,

I

I

Subgroup 1
Electrical
Reject
(2)

Subgroup 3
Electrical
Reject
(3)'

I
Subgroup 5
Electrical
Reject
(4)

I

I
I

I
I

I
I
I
I

I·

GROUpe

I
Subgroup 1

I

I

Electrical
Good
(77)

I

GROUP 0

I
I

I

I

Subgroup 2
Electrical
Good
(25)

Subgroup 1
Electrical
Reject
(25)

I

Subgroup 3
Destruct

Subgroup 5
Electrical
Reject
(25)

(25)

J
SubgroUp 2
Electrical
Reject

Subgroup 4
Electrical
Reject

(4)

(1)

Subgroup 2
Electrical
Reject
(25)

Subgroup 6
Electrical
Reject
(3)""

Subgroup 4
Destruct
(25)

*Sample must have had temp/time exposure speCified for burn-in.
L TPD of 15 applies to number of leads inspected except that in
no case shall less than 3 devices be used.
**Required only when a pa'ckage contains a dessicant.

NOTES:
Group A and 8 inspections are required on individual inspec·
tlon lots as a condition for acceptance for delive.ry.

4. Group D (package related tests) shall be performed periodically
at 6 month intervals.

2. Samples shall be randomly selected from the assembled inspection lot in accordance with appendix B of MIL-M·38510. Speci-

5: Where end point measurements are required but no parameters
have been' identified, the critical final electrical parameters specified for 100% screening shall be used as end point measurements.

L

tEl

fied screen requirements of method 5004 are not required to have
been ,completed for Intersil's standard generic data program, but
will be performed when required by customer drawing. Where
use of electrical rejects is permitted, and unless otherwise specified, they need not have been subjected to the temperature/time
exposure of burn·in ..

6. Subgroups within a group may be performed in any order but in-

dividual tests within a subgroup shall be performed in the sequence indicated.

Group C (chip-related test) shall be performed periodically at 3
month intervals.

8-12

HIGH RELIABILITY PROCESSING

QUALITY CONFORMANCE

LIMITED USAGE QUALIFICATION

The following steps are carried out when quality conformance testing is performed on a lot from which samples
are taken.

A customer may elect to take advantage of a "Limited
Usage" qualification per M I L~M-3B51 0, in order to reduce
the number of samples required. The following conditions
must be met for eligibility for the "Limited Usage" qualification:

QUALITY CONFORMANCE - CLASSES 8 & C

Group A
(Electrical
Acceptance)
Group.B
(Package
Related)

Group C
(Die Related)

Group 0
(Package
Related)

1. A maximum quantity of 500 microcircuits is included

STANDARD
SAMPLE
SIZE

ALLOWABLE
REJECTS

TIME.
ALLOWANCE

45

0

3-5
days

0

1 week

14
Electrical
Rejects
102 Good
Electrical
(Note 1)

1 from
Subgroup 1
1 from
Subgroup 2

8-10
weeks

50 Good
Electrical
(Note 2)
75.Electrical
Rejects

1 from each
of
5 Subgroups

4 weeks

in a single order.
2. A maximum quantity of 2000 microcircuits is included
in a given equipment-acquisition contract or program.
3. A maximum quantity of 2000 microcircuits is to be procured during a 12-month period for a given circuit type
and vendor.
Microcircuits which qualify for limited usage cannot be assigned a JAN part number. Variable data will be taken only
when specified in a customer drawing.
LIMITED USAGE QUALIFICATION- CLASS 8(1)

NOTE 2: Destructive tests:
Moisture resistance. Sllbgroup 3 sample size

25 units

Variable-frequency vibration. Subgroup 4 sample size.

25 units

Total Destroyed

50 units

QUALIFICATION TESTING
When qualification testing is' required, it will be equivalent
to quality conformance testing, with the exception that
Group A must be read and recorded on all applicable subgroups for the number of electrically-good units which will
be required for samples for Groups C and D.

TIME
ALLOWANCE

45

0

5 days

Group B
(Package
Related)

14
Electrical
Rejects

0

Group C
(Die Related,
Non-Destructive)

10 Good
Electrical
Parts

0

25
(15 Good,
10. Electrical
Rejects)

0

Group 0
(Package
Related,
Destructive)

ALLOWABLE
REJECTS

TIME
ALLOWAN.CE

Group A
(Electrical
Acceptance)

184
(Read &
Record)

5

5 days

Group B
(Package
Related)

14
Electrical
Rejects

0

1 week

Group C
(Die Related)

102
Good
Electrical
(Note 1)

1 from
Subgroup 1
1 from
Subgroup 2

10-12
weeks

50 Good
Electrical
(Note 2)
75 Electrical
Rejects

rtrom each
of
5 Subgroups

4 weeks

1 week

8-10
weeks·

4 weeks

(1) Mil-M-38510, Paragraph 4.4.4; MIL-STD-883, Method 5005.

QUALIFICATION TESTING - GROUPS 8 & C

Group 0
(Package
Related)

ALLOWABLE
REJECTS

Group A
(Electrical
Acceptance)

NOTE 1: Non-destructive, shippable samples (102 units).

STANDARD
SAMPLE
SIZE

SAMPLE
SIZE'

NOTE 1: Shippable samples.
NOTE 2: 50 destroyed samllles, subgroups 3 and 4.

8·13

HIGH RELIABILITY PROCESSING

GLOSSARY OF MILITARY/AEROSPACE HIGHREL DEFINITIONS/TERMINOLOGY·

DESC- Defense Electronic Supply Center, located in Dayton, Ohio. The command includes two major subgroups,
with functions as follows:
DE~C-ECS - .This group performs specification engineering work.. After the original specifications are created at RADC, DESC-ECS implements and monitors
the specifications. DESC-ECS is the industry!s main
interface on existing specifications.

ACCELERATEDBURN-IN":' Same as "8urn-ln", except
that testing is carried out at an increased temperature (nominally 150 C) for reduced dwell time. Accelerated testing
is not permissible for Class S devices.
0

DESC-EQM - The group which supervises supplier certifications and qualifications per MI L-M-38510. The group
to which the industry submits applications when desiring
to have devices qualified (QPL'd) on an existing JAN
slash. sheet. DESC-EQM surveys supplier facilities and
grants line certification as various r~quirements are met.
Also reviews manufacturer's qualification test data and
issues JAN QPL's accordingly.

ATTRIBUTES DATA - Go-No-Go data. Strictly pass/
fail and number of rejects recorded. A typical requirement
for post bu rn-in electrical tests on Class 8 devices.
BASELINE - Technique used to define manufacturing and
test processes at time of order placement. 8aselining usually
involves development of a Program Plan and an Acceptance
Test Plan which include flow charts, specification identification/revisi6n letters, QA procedures, and actual specimens
of certain important specifications. During subsequent
manufacture and testing of parts, it is not permissible to
make revisions or changes to any of the identified specifications, unless prior notification and possible customer approval occurs. Ot~er terminology associated with baselining include "Critical Process Changes", "Minor Process
Changes'~, and "Major Process Changes".
BURN-IN - A screening operation. Devices are subjected
to high temperature (typically 1250 C) and normal power/
operation for 160 hours (Class 8 devices) or 240 hours
(Class S devices).

DESC-EQT - Same as EQM, except handles transistors
per MIL-S-19500.
DESC LINE CERTIFICATION - The document which approves a supplier's facilities as an appropdate site to manufacture JAN parts.
[)IE SHEAR TESTS - A sample test. Mounted chips are
exercised to destruction. Degree of die adherence to lead
frame is observed. Corrective action taken if required ..
DPA - Destructive Physical Analysis. Finished products
are opened and analyzed, in accordance with customer or
MI L Spec criteria.
GENERIC DATA - Data pertaining to a device family; not
necessarily the specific part number ordered by the customer,but representative of parts in the family. Group 8,
C and D generic data is frequently requested in lieu of the
performance of special qual tests on a given order.

CLASS S, BAND C INTEGRATED CIRCUITS - These
classes set forth the screening, sampling and document control requirements for IC testing. Terminology is defined
in MI L-M-38510 and in Test Methods 5004 and 5005 of
MIL-M-38510. Classes,S, 8 and C are sometimes referred
to as "Levels S, 8 and C." The Classes cover:
CLASS S '7 For space and satell ite programs .. , ncludes
Condition A Precap, SEM, 240 hour burn-in, PIND test
and elaborate qualification and quality conformance
. testing. Normally requires extensive data, documentation, and program planning. Formerly referred to as
Class A. Class S devices are quite expensive.

GROUP A - Sample electrical tests which are performed
on each lot. Group A is defined in Test Method 5005 for
integrated circuits and in MI L-S-19500 for diodes and
tratisistors .
GROUP B - A collection of package-related environmental
and "wear-and-tear" tests. Defined in Test Method 5005
for integrated circuits. For Class S screening, additional life
tests are required, and are performed on every lot per MILM-38510 .. For diodes and transistors, Group 8 consists of
both environmental and life tests, as defined in MIl:S-19500.

CLASS B - For manned flight, and includes most frequently-procured military integrated circuits. Used for
all but highest reliability requirements. Class 8 uses
burn-in, pre-cap visual, etc.
CLASS C - For ground support equipment. Contains
only environmental screening requirements with pre-cap
visual. No burn-in required.
In all classes, LTPD (Lot Tolerance Percent Defective) is
the sampling plan measurement criteria.

GROUP C - For Class 8 and C integrated circuits, only
Group C includes life testing and temperature cycling/constant acceleration die-related sample tests. Defined in Test
Method 5005 and performed every three months per M I LM-38510. .

CORRECTIVE ACTION - Those actions which a given
supplier (or user) agrees to perform so that a detected problem does not reoccur.

GROUP D - A collection of additional environmental
package-related sample tests as defined in Test Method
5005. Performed every six months per MIL-M-38510. For
classes S, 8, & C.
.
8-14

.HIGH RELIABILITY PROCESSING
JAN - "Joint Army Navy", a registered trademark of the·
U.S. Government. The JAN marking denotes a device which
is in full compliance to MIL-M-38510 or MIL-S-19500.

NON-STANDARD PARTS APPROVAL - Approval by the
government (frequently RADC) of non-JAN parts, typically on source control drawings, for use in a military system or program. This approval is essentially a waiver which
permits non-JAN 38510 Pe done under a gaseous
nitrogen ambient atmosphere to preven~ oxidization. If a
eutectic die attach is used, it is recommended that a 98%
gold/2% silicon preform be used at' a die attach temperature between 385°C and 435°C. If an epoxy die attach is
used, the epoxy cure temperature should' not exceed 150°C.
If hermetic packages are used, epoxy die attach should be
carried out with caution so that there will be no "outgassing"
o~ the epoxy.

CHANGES

Intersil reserves the right
manufacturing processes
these improvements may
they will.not affect dice
maximum die sizes.

in improve device geometries and
without prior notice. Although
result in slight geometry changes,
electrical limits, pad" layouts, or

USER RESPONSIBILITY
BONDING

Written notification of any non-conformance by Intersil of
Intersil's dice specifications must be made within 75 days of
the shipment date ofthe die to the user. Intersil assumes no
responsibility for the dice after 75 days or after further user
processing such as, but not iimited to, chip mounting or wire
bonding.

Thermocompression gold ball or aluminum ultrasonic bonding may be used. The wire should be 99.99% pure gold ahd
the aluminum wire should be 99% aluminum/l% silicon.
In either case, it is recommended that 1.0 mil wire be used
for normal power circuits.

B-26

LINEAR:

Examples of Intersil Part Numbers
BASIC

ELECTRICAL
TEMP
OPTION

ICH8500

A

ICL8038

C

PIN

T

V

C

P

0

ICL8038CC PO

M

0

E

IH5040MDE

C

IH5040

ICL 8038
PKG

C CPO

fC
~

ICH8500ACTV

ON ALL INTERSIL IC PART NUMBERS. THE LAST THREE
LETTERS ARE TEMPERATURE, PACKAGE, AND PIN
NUMBER, RESPECTIVELY.

Number of Pins
Package
Temperature Range:
M - -55°C to +125°C
I - -20°C to + 85°C
C O°C to + 70°C
Electrical Option

'--------Device Chip Type
' - - - - - - - - - Intersil Linear Circuit

HYBRIDS:
TEMPERATURE:

C
M

PACKAGE:

-

Commercial
Industrial
Military

B
D
E
F
, I

-'J -'
K L P Q T DR -

NUMBER OF PINS: A
B
C
D
E
N
P
F
G

-8
10
12
14
16
- 18
- 20
- 22
- 24
. - 28

-

V W
Y Z

- - -L=t
'
Package:

Plastic Flaipak (minipak)
Ceramic Dual-In-Line
Small TO-8 Type
Ceramic Flatpak
16 Pin Dip (0.6 X 0.7) Lead Space
Cerdip Dual-In-Line
8 Lead TO-3 Metal Can
Leadless, Ceramic
Epoxy Dual-In-Line
2 Lead Metal Can
TO-5 Type
TO-72 with No.4 Lead
Connected to Case

J K L
M

DG 126 A L

L -_ _ _ _ _ _

A - Metal Ca~
L - Flat pack
P - Ceramic
Temperature Range:
A - -55°C to +125°C
B - ' -20°C to + 85°C
C 0° C to + 70° C
Device Chip Type

' - - - - - - - - : - - - Device Family
DG - Drivers
D

-c-

G -

Drivers

Multi-channel FET

IH 5043 B M 1= 0

--E-E~

Number of Pins
Package
Temperature Range:
'
M - -55°C to +125°C
C O°C to + 70°C
Electrical Option
' - - - - - - - - Device Chip Type
' - - - - - - - - - Intersil Hybrid/Analog Gate

, WATCH AND CLOCK:
ICM 7045 A I P I

--, -t ~
L...=

32
36
40
48

Number of Pins

Package
Temperature Range:
M - -55°C to +125°C
I - -20°C to + 70°C
C OUC to + 70°C
~---- Electrical Option
' - - - - - - - Device Chip Type
' - - - - - - - - - Intersil Watch and Clock Circuit

8, 0.230 in. Pin Circle
10, 0.230 in. Pin Circle
8. Pin 4
Connected to Case
10, Pin 5
Connected to Case
B-27

PART NUMBERS AND ORDER INFORMATION

-EtC

B!POLAR MEMORY:

MOSMEMORY:

1M 5 6 00 C J E

1M 7 114 L

L~paCkage

C J N

t~
II

Number of Pins
Package'
Temperature Range
M - -55'G to +125'C
I - -4D'C to ~ 85'C
C D'G to + 75'C
' - - - - - Speed Selection
' - - - - - - - Power Selection.
L -_ _ _ _ _ _ Device Chip Type
L-_ _ _ _ _ _ _ MOS Process.

Number of Pins
'

Temperature
'
M - -55'C to +125'C
C D'C to + 75'C
.
Specific Chip Type
' - - - - - - - ' - General Type
2 - Field Programmable Logic Array (FPLA)
6 - Programmable Read Only Memory (PROM)
' - - - - - - - - B i p o l a r Process
' - - - - - - - - - I n t e r s i l Memory Circuit

2

L - - - - - - - - - I n t e r s i l Memory

C/MOS MEMORY:

-----:--illt
1M 6 5 OB A -1 M D E

t
L

'----L-_ _ _ _
'-----'-------

L-_ _ _ _ _ _

.Number of Pins
Package
Temperature
M --,- -55'C to +125'C
I - ~4D'C to + 85'C
C D'C to + 75'C
Improved Speed, Reduced Current (optional)
Operating Voltage (optional)
Specific Chip Type
General Type
1 - Processi ng Elements
3 - Read Only Memories (ROM)
4 - Interface EI!jments
5 - Random Access Memories (RAM)
6 - Programmable Read Only Memory (PROM)
C/MOS Process
'

L-_ _ _ _,--_ _ Intersil Memory Circuit

VERTICAL POWER MOSFET PART NUMBERING
(PROPRIETARY PARTS)
I V N 52 00

Ii]

tg
X

Y

BREAKDOWN
VOLTAGE
A 20
B ' 30
C 35
D 40
E 60
F 80
G 90
H 100
J
125
K 150
L' 175
M 200
N 225
P 250
Q
300
R 350
S 400
T 450
U 500

Z

""',"0",
Voltage
Z if Zener
N if None
Package C~de
Selection
Basic Type
Nor P
Intersil
VMOS

' PACKAGE CODES
TO-237 (92+)
A
TO-202
B
TO-220
C
DICE
D
TO-66
H
TO-3
K
TO-52
S
T
TO-39

FOR INDIVIDUAL PART AVAILABILITY, PLEASE REFER TO
A CURRENT INTERSIL PRICE LlSTOR CONTACT YOUR
NEA,F!~_~~_~T~~~L_~~L~~_9.f_F_IC_E~ _______. __________ --- ______________________________________ --------.------ ------------------------

B·28

BJllIlIBJIllIlDtflllllllillllillilllBJlilllilliDllIBJllmllilDmplilDlill!lilli1l1
INTERSIL INTERNATIONAL OFFICES
DOMESTIC
HEADQUARTERS

NORTHERN EUROPEAN
HEADQUARTERS

CENTRAL EUROPEAN
HEADQUARTERS

Intersil, Inc.
10710 N. Tantau Avenue
Cupertino, CA 95014
Tel: (408) 996·5000
TWX: 910·338·0171
(INTRSLINT CPTO)

Intersil Datel (UK) Ltd.
Snamprogetti House
Basing View
Basingstoke
Hants, RG21 2YS
England
Tel: (0256) 57361
TLX:858041INTRSLG

Intersil GmbH
Bavariaring 8
8000 Miienchen 2
West Germany
Tel: 89/539271
TLX: 5215736 INSLD

SOUTHERN EUROPEAN
HEADQUARTERS

FAR EAST
HEADQUARTERS

Intersil, Inc..
Bureau de Liaison ,
217, Bureaux de la Colline
Bat. D (2" Etage)
92213 Saint-Cloud Cedex
France
Tel: (1)"602.58.98
TLX: DATELEM 204280F

Intersil, Inc.
c/o S.S.1. Far East, Ltd.
Suite 201, Austin Centre
21 Austin Av~nue
Tsimshatsui Kowloon, Hong Kong
Tel: 3-672112-3
TLX: 86496 SSI HX

INTERSIL SALES OFFICES
CALIFORNIA

ILLINOIS

OHIO

1272 Forgewood Avenue
Sunnyvale, California 94086
Tel: (408) 744-0618
TWX: 910-339-9260

201 Ogden Avenue, Suite #230
Hinsdale, Illinois 60521
Tel: (312) 986-5303
TWX: 910-651-0859

228 Byers Road
Miamisburg, Ohio 45342
Tel: (513) 866-7328
TWX: ,81 0-473-2981

MASSACHUSETTS

TEXAS

400 Oceangate Suite' #1102
Long Beach, CA 90802
Tel: (213) 436-9261
, TWX: 916-341-6829

COLORADO
5 Parker Place, Suite #351
2600 S. Parker Road
Aurora, Colorado 80014
'
-Tel: (303) 750-7004
TWX: 910:320-2982

2 Militia Drive, Suite,12
.
Lexington, Massachusetts 02173
Tel: (617) 861-6220
TWX: 710-326-0887

MINNESOTA
6550 York Avenue, South, Suite #307
Minneapolis, Minnesota 55435
Tel: (612) 925-1844
TWX: 910-576-2780

FLOR!DA
Hollywood 95 Office Park
2700 N. 29th'Avenue
, Building #2, Suite #204
Hollywood, Florida 33020
Tel: (305) 920-2442
TWX: 510-954-9819

NEW JERSEY
560 Sylvan Avenue
Englewood Cliffs, New Jersey 07632
, Tel: (201) 567-5585
TWX: 710-991-9730

8-29

10300 N. Central Expwy.
Suite 225:llI
Dallas, TX 75231
Tel: (214) 369-6916
, TWX: 910-860-5482

CANADA
338 Queen Street East, Suite #208
Brampton, Ontario L6V 1C4
Tel: (416) 457-1014
• TWX: 610-492-2691

DOMESTI"C'SALES REPRESENTAT:IVES
ALABAMA

IOWA

NEW YORK

TENNESSEE

K & E Associates, Inc.
Suite #122
3313 Memorial Parkway SE
HIJntsville, AL 35801
Tel: (205) 883-9720
TLX: 50-4421

Dy-Tronix, Inc.
Suile #202
23 Twixt Town Rd. NE
Cedar Rapids, IA 52402
Tel: (319) 377-8275

Ossman Component Sales Corp.
280 Metro Park
Rochester, NY 14623
Tel: (716) 424-4460
TWX: 510-253-7685

~o~t; ~s~oclates

Ossman Component Sales Corp.
154 PlckE!rard Bldg.
Syracuse, NY 13211
Tel: (315) 455-6611
TWX: 710-541-1522

MARYLAND
ARIZONA
Shetler-Kahn
2017 N. 7th St.
Phoenix, AZ 85006
Tel: (602) 257-9015
TWX: 910-951-0659

New 'Era Sales, Inc.
,Empire Towers-Suite #407
7300 Ritchie Highway
Glen Burnie, MD 21061
Tel: (301) 768-6666
TWX: 710-861-0520

CALIFORNIA

MASSACHUSETTS

ADDEM S:D.
7380 Clairemont Mesa Blvd.
S'uite 106
San Diego, CA 92111
Tel: (714) 268-8448

COM-SALE
235 Bear Hill Road
Waltham, MA 02154
Tel: (617) 890:0011

NORTH CAROLINA
K & E Associates
Route 2 Box 54
Garner, NC 27529
Tel: (919) 772-8454

OHIO
Glesting & Associates
3274 Donneybrook Lane
Cincinnati, OH 45239
Tel: (513) 521-8800
TLX: 21-4283
TWX: 216-26'1-1311

MICHIGAN
CONNECTICUT
COM-SALE
633 Williams Road'
Wallingford, CT 06492
Tel: (203) 269-7964

FLORIDA
EIR, Inc.
701 E. Semoran Blvd.
Suite 112
Altamonte Springs, FL 32701
Tel: (305) 830-9600
TWX: 810-853-9213

,ILLINOIS
D. Dolin Sales Co.
6232 N. Pulaski Rd.
"Chicago,IL'60646
Tel: (312) 286-6200
TWX: 910-221-5018

INDIANA

IE]

Giesting & Associates
5654 Wendzel Dr.
Coloma, MI 49038
Tel: (616) 468-4200

Giesting & Associates
5512 Autumn Hills Dr.
Westbrook Village
Dayton; OH 45426
Tel:'(513) 293-4044

Giesting & Associates
149 Mary Alexander Ct:
Northville, MI 48167
Tel: (313) 348-3811

Giesting & Associates
570 South State Circle
Galion, OH 44833
Tel: (419) 468-3737

MISSOURI
Dy-Tronix, Inc.
11190 Natural Bridge
Bridgeton, MO 63044
Tel: (314) 731-5799
TWX: 910-762-0651

OREGON
LD Electronics
P.O. Box 626
Beaverton, OR 97005
Tel: (503) ~49-8556
(503) 649-6177
TWX: 910-467-8713 .

Dy-Tronix, Inc.
13700 East 42nd .Terrace
Independence, MO 64055
Tel: (816) 373-6600

PENNSYLVANIA

,NEW HAMPSHIRE

Delesa Sales
Executive Office Park
2118 Inwood Dr., Suite #117
Ft. Wayne, IN 46805
T!JI: (219) 483-9537
TWX: 810·332-1407

COM-SALE
102 Maple St.
Manchester, NH 03103
Tel: (603) 668-1440 '

Comtek Inc.
821 Bethlehem Pike
Erdenheim, PA 19118
Tel: (215) 233-0532

NEW MEXICO

SOUTH CAROLINA

Delesa Sales
10026 E. 21 st St.
Indianapolis, IN 46229
Tel: (317) 894-3778

Shefler-Kahn
10200 Menaul NE
Albuquerque, NM 87112
Tal: (505) 296-0749

K & E Associates
4808 St. Andrews Office Park
Suite 10
Columbia, SC 29210
Tel: (803) 798-7574

8-30

Box 33A
Jqneboro, TN 37659
Tel: (615) 753-2921

TEXAS
Nova' Marketing
11700 Southwest Freeway
Suite #200
Houston, TX 77031
Tel: (713) 933-2636
TWX: 910-880-4053
Nova Marketing
5728 LBJ Freeway
Suite #400
Dallas, TX' 75240
Tel: (214) 385-9669

UTAH
Sage Sales
3524 South 1100 East.
Salt Lake City, UT 84106
Tel: (801) 467-5451
TWX: 910-925-5153

WASHINGTON
LD Electronics
East 12607 Guthrie Dr.
Spokane, WA 99216
Tel: (509) 455-0189
LD Electronics
14506 NE 169th St.
P.O. Box 663
Woodenville, WA 98072
Tel: (206) 485-7312

WISCONSIN
D. Dolin Sales Co.
131 W. Layton Ave.
Milwaukee, WI 53207
Tel: (414) 482-1111
TWX: 910-262-1139

CANADA
Lenbrook Industries Ltd.
1145 Bellamy Rd.
Scarborough, Ontario
Canada M1H lH5
Tel: (416) 438-4610
TLX: 065-25485
Lenbrook Industries Ltd.
6896 Jarry St. East
" St. Leonard, Quebec
'Canada HlP 3Cl
Tel:,(514) 323-3242

INTERSIL FRANCHISED DIS.TRIBUTORS
ARIZONA

COLORADO

GEORGIA

Kierulff Electronics
4134 E. Wood SI.
Phoenix, AZ 85040
Tel: (602) 243:4101

Bell Industries
Century Electronics Div.
8155 W. 48th Ave.
Wheatridge, CO 80033
Tel: (303) 424-1985
TWX: 910·938·0393

Arrow Electronics
2979 Pacific Dr.
Norcross, GA 30071
Tel: (404) 449·8252
TWX: 810·757·4213

Western Microtechnology Sales
, Building Hl05
7740 East Redfield Road
Scottsdale, AZ 85260
Tel: (602) 948·4240
Wyle Distribution Group
8155 N. 24th Ave.
Phoenix, AZ 85021
Tel: (602) 249·2232

CALIFORNIA
Anthem Electronics, Inc.
4125 Sorrento Valley Blvd.
Suite A
San Diego, CA 92121
Tef: (714) 279·5200
Anthem Electronics, Inc.
1020 Stewart Dr.
Sunnyvale, CA 94086
Tel: (408) 738-1111
TWX: 910·339·9312 ,
Arrow Electronics
521 Weddell Drive
Sunnyvale, CA 94086
Tel: (408) 745·6600
. Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
Tel: (213) 725·0325
TWX: 910·580·3106
Kierulff Electronics
3969 East Bayshore Rd.
Palo Alto, CA 94303
Tel: (415) 968·6292
Kierulff Electronics
14101 Franklin Ave.
Tustin, CA 92680
Tel: (714) 731·5711
Schweber Electronics
17811 Gillette Ave.
Irvine, CA 92714
Tel: (714) 556·3880
TWX: 910·595-1720,
Wyle Distribution Group
3000 Bowers Ave.
Santa Clara, CA 95052
Tel: (408) 727·2500
TWX: 910·338·0541
910-338·0296
Wyle Distribution Group'
124 Maryland SI.
EI Segundo, CA 90245
Tel: (213) 322·8100
TWX: 910-348·7111
Wyle Disiribution Group
17872 Cowan Ave.
Irvine, CA 92714
. Tel: (714) 64 H600

Schweber Electronics
303 Research Dr.
Norcross, GA 30092
Tel: (404) 449·9170

Klerluff Electronics
10890 E. 47th 'Ave.
Denver, CO 80239
Tel: (303) 371·6500

ILLINOIS

Wyle Distribution Group
451 E. 124th Ave.
Thornton, CO 80241
(303) 457·9953
TWX: 910·936·0770

Arrow Electronics
492 Lunt Ave.
. Schaumburg, IL 60193
Tel: (312) 893-9420
TWX: 910-291-3544

CONNECTICUT

Kierulff Electronics
1530 Landmeier Rd.
Elk'Grove Village, IL 60007
Tel: (312) 640·0200

Arrow Electronics
12 Beaumont. Rd.
Wallingford, CT 06492
Tel: (203) 265-7741
TWX: 710·465·0780

Newark Electronics
500 North Pulaski Road
Chicago, IL 60007
Tel: (312) 638·4411

Schweber Electronics
F.inance Drive
Commerce Industrial Park
Danbury, CT 06810
Tel: (203) 792·3500
TWX: 710·456·9405

Schweber Electronics
1275 Brummel Ave.
Elk Grove Village, IL 60007
Tel: (312) 364·3750
TWX: 910·222-3453

FLORIDA
Arrow Electronics
1001 NW 62nd SI.
Suite H402
FI. Lauderdale, FL 33309
Tel: (305) 776-7790
TWX: 510·955-945"

INDIANA
Advent Electronics, Inc.
8446 Moller Rd.
Indianopolis, IN 46268
Tel: (317) 297·4910
TWX: 810·341·3228

Arrow Electronics
115 Palm Bay Road NW
Building 200-Sulte 10
Palm Bay, FL 32905
Tel: (305) 725·1480
TWX: 510·959·6337

IOWA
Advent Electronics
682 58th Avenue Court S.W.
Cedar Rapids, IA 52404/
,
Tel: (319) 363·0221
TWX: 910·525·1337

Diplomat Electronics Inc.
2120 Calumet SI.
Clearwatrer, FL 33515
Tel: (813) 443·4514
TWX: 810·866-0436

Schweber Electronics
5720 N. Park Place,N.E.
Cedar Rapids, IA 52402
(319) 373·1417

Diplomat Electronics Inc.'
6890 NW 20th Ave.
Ft. Lauderdale, FL 33309
Tel: (305) 971-7160

MARYLAND (co~tinued)
Schweber Electronics,
9218 Gaither Rd.
' Gaithersburg, MD 20760
Tel: (301) 840·5900
TWX: 710-828·9749

MASSACHUSETTS
Arrow Electronics
96D Commerce Way
Wobum, MA 01801
Tel: (617) 933·8130
Klerulff Electronics'
13 Fortune Dr. '
Billerica, MA 01821
Tel: (617) 667·8331
TWX: 710·390-1449
Schweber Electronics
25 Wiggins Ave.
Bedford, MA 01730
Tel: (617) 275·5100

MICHIGAN
Arrow Electronics
3801 Varsity Dr.
Ann Arbor, MI 48104
. Tel: (313) 971·8220
TWX: 810·223·6020
Schweber Electronics
33540 Schoolcraft
Livonia, MI 48150
Tel: (313) 525·8100

MINNESOTA
Arrow Electronics
5230 W. 73rd SI.
Edina, MN 55435
Tel: (612) 830-1800
TWX: 910·576-3125
Kierulff Electronics
5280 West 7th 51.
Edina, MN 55435
Tel: (612) 835-4388
Schweber Electronics
7422 Washington Avenue South
Eden Prairie, MN 55343
rei: (612) 941-5280

MISSOURI
KANSAS

Diplomat Elecironics Inc.
50 Woodlake Drive West
Suite,H3 Building A
Palm Bay, FL 32905,
Tel: (305) 725·4520

Component Specialties Inc.
8369 Nieman Road
Lenexa, KS 66214
Tel: (913) 492-3555

Schweber Electronics
2830 N. 28th Terrace
Hollywood, FL 33020
Tel: (305) 927·0511 ,
TWX: 510·954·0304

MARYLAND
Arrow ElectroniCS
480l Benson Ave.
Baltimore, MD 21227
Tel: (301) 247-5200
TWX: 710-236-9005
Diplomat'Electronics Inc.
9150 Rumsey Road
Suite HA6
Columbia, MD 21045
Tel: (301) 995-1226

Wyle Distribution Group
9525 Chesapeake Dr.
San Diego, CA 92123
Tel: (714) 565·9171
TWX: 910-335·1590

8-31

LCOMP
2550 Harley Dr,
Maryland }-Ieights, MO 63043
Tel: (314) 291-6200
TWX: 910-7~2-0632
' LCOMP
2211 River Front Dr.
Kansas City, MO 64120
Tel: (816) 221-2400
TWX: 910·771·3148

N'EW HAMPSHIRE
Arrow Electronics
One Perimeter Rd.
Manchester, NH 03103
. Tel: (603) 668-6968

IiJ

NEW JERSEY

NEW YORK (continue~)

PENNSYLVANIA

WISCONSIN

Arrow Electronics
Pleasant Valley Ave.
Moorestown, NJ 0.80.57
Tel: (60.9)235·190.0.
TWX: 710.-897-0829

.Harvey Ele'ctronlcs
P.O; Box 120.8
Binghamton, NY'139D2
Tel: (60.7) 748·8211,
TWX: 510.·252·0.893

Arrow Electronics
650. Seco Rd.
Monroeville, PA 15146
Tel: (412) 856·70.0.0.

Arrow Electronics
430. W. Rawson Ave.
Oak Creek, WI 53154'
Tel: (414) 754·660.0.
TWX: 910.·262·1193

Arrow Electronics
285 Midland Ave.
Saddle Brook, NJ 0.7662
Tel: (20.1) 797·580.0.
TWX: 710.·988·220.6

Harvey Electronics
840. Fairport Park
Fairport, NY 14450.
Tel: (716)'
TWX: 510.·253·70.0.1

Diplomat Electronics Inc.
490. South Riverview Dr.
Totowa, NJ 0.7512
Tel:.(2D1) 785-1830. .
Panda Electronics Inc.
370. Union Boulevard
Totowa, NJ 0.7512
Tel: (20.1) 595·10.11
Schweber Electronics
18 Madison
Fairfield, NJ 0.70.06
Tel: (20.1) 227·7990.

NEW MEXICO
Alliance Electronics
110.30. Cochiti S.E.
Albuquerque, NM 87~23
Tel: (505) 292·3360.
Arrow Electronics
246D'Alamo Avenue, S.E.
Albuquerque, NM 8710.6
Tel: (50.5) 243·4566
Bell Industries
Century Electronics Dlv.
11728 Linn, NE
A,lbuquerque, NM 87123
Tel: (50.5) 292·270.0.
TWX: 910.·989·0.625

NEW YORK
Arrow Electronics
90.0. Broad Hollow Rd.
Farmingdale, NY 11735
Tel: (516) 694·6800
, TWX: 510.·224·6494
Arrow Electronics
20. Oser Ave.
Hauppauge, NY 11787
Tel: (516) 231-1000

1]
•
•

Arrow Electronics
770.5 Maltlage Drive
Liverpool, NY 130.88
Tel: (31"5) 652·10.0.0.

Arrow Electronics
30.0.0. South Winton Rd
'Rochester, NY 14623
Tel: (716) 275·0.30.0.
Components Plus
40. Oser Ave.
Hauppauge, NY 11787
Tel: (516) 231·920.0.
TWX: 510.·227·9869

•

Schweber Electronics .
10.1 Rock. Rd.
Horsham, PA 190.44.
Tel: (215) 441·0.60.0.

Kierulfl Electronics
2212 E. Moreland Ave.
Waukesha, WI 63186
Tel: (414) 784·8160.

TEXAS

Schweber Electronics
Jericho Turnpike
. Westbury, NY 11590.
Tel: (516) 334·7474
Twx: 510.·222·3660.

Arrow Electronics
13715 Gamma Rd.
Dallas, TX 75234
Tel: (214) 386·750.0.'
Arrow Electronics
10.70.0. Corporate Dr.
Stafford, TX 77477
Tel: (713) 491·410.0.

Schweber Electronics
2 Townllne Circle
Rochester, NY .14623
Tel: (716) 424·2222

Component SpeCialties Inc.
8222 Jamestown Dr. Suite #115
Austin, TX 78757
Tel: (512) 837·8922

Summit Distributors Inc.
916 Main SI.
Buffalo, NY 1420.2
Tel: (716) 884·3450.
TWX: 710.·522·1692

Compone'nt Specialties Inc.
10.90.7 Shady Trail
Suite #10.1'
Dallas, TX 75220.
Tel: (214) 357·6511 •

NORTH CAROLINA
Arrow Electronics
938 Burke SI.
Winston·Salem, NC 2710.2
Tel: (919) 725·8711 .

Component Specialties Inc.
8181 Commerce Park Dr.
Suite #70.0.
Houston, TX 770.36
Tel: (713) 771-7237

RESCO/Raielgh
RI. 8 Box 116~B
Highway 70. West
Raleigh, NC 27612
Tel: (919) 781·570.0.
TWX: 510.·928·0.590.

Schweber Electronics
14177 Proton St.
Dallas, TX 75234
Tel: (214) 661·50.10.
TWX: 910.·860.·5493

OHIO

, Schwe'ber Electronics
7420. Harwiri Dr.'
Houston, TX 770.36
Tel: (713) 784·360.0.
TWX: 910.·881·110.9

Arrow Electronics
P.O. Box 37856
Cincinnati, OH 45222~
Tel:, (513) 761·5432
TWX: 810.·461·2670.

UTAH

Arrow Electronics
7620. McEwen Road
Centerville, Ohio 45459
Tel: (513) 435·5563
TWX: 810.·459·1611

Bell Industries
. Century ELectronics Div.
3639 West 2150. South
Salt Lake.CitY,UT 84120.
Tel: (80.1) 972·6969
TWX: 910.·925·5698

Arrow Electronics
6238 Cochran
Solon, OH 44139
Tel: (216) 248·3990.

Diplomat ELectronics
.
30.0.7 S. West Temple, Suite #C
Salt Lake City, UT 84115
Tel: (80.1) 486·4134

Schweber Electronics
23880. Commerce Park Rd.
Beachwood, OH 44122
Tel: (216) 464,2970.
TWX: 810.·427·944.1

Kierulff Electronics
2121 S. 360.0. West
Salt Lake City, UT 841.1.9
Tel: (80.1) 973·6913 ..

OKLAHOMA
WASHINGTON

. Component Specialties Inc.
7920. E 4Dth SI. .
, Tulsa, OK 74145
Tel: (918) 664·2820.

. Kierulff Electronics
. 10.0.5 Andover Park East
Tukwila, WA 981.88
Tel: (20.6) 575·4420.

OREGON

CANADA
Cardinal Electronics
10.630. 172 St.
Edmonton, Alberta
Canada T5J 2P4
Tel:'(4D3) 483-6266
CESCO'
40.50. Jean Talon St. W
Montreal, Quebec
Canada H4P 1W1
Tel: (514)735·5511
TWX: 610.·421·330.2
CESCO
24 Martin Ross Ave.
Downsview, Ontario
Canada M3J 2K9
Tel: (416) 661·0.20.0.
CESCO
24 Martin Ross Ave.
Downview, Ontario
Canada M3J 2K9
Tel.: (41,6) 661·0.220.
RAE. Ind. Elect. Ltd.
3455 Gardner Ct.
Burnaby, British Columbia
Canada V5C 4J7
. Tel: (60.4) 291·8866
TWX: 610.·929·30.65
TLX: 0.4·356533
Zentronics Ltd.
. 1355 Meyerside Dr.
Mississauga, Ontario
Canada L5T 1C9
Tel: (416) 676·90.0.0.
TLX: 0.6·983657
Zentronics Ltd.
48DA Dutton Dr.
Waterloo, Ontario
Canada N2L 4C6
Tel: (5.19) 884·570.0.
Zentronics Ltd.
50.10. Pare St.
Montreal, Quebec
Canada H4P 1P3
Tel: (514) 735·5361
TLX: 0.5·827535
Zentronics' Ltd.
'141 Catherine St.
Ottawa, Ontario
Canada K2P 1C3
Tel: (613) 238·6411
TLX: 0.53·3636
Zentronics Ltd.
590. Berry St~eet
Winnipeg, Manitoba
Canada R3H OS1
Tel: (20.4) 775·8661

Wyle Distribution Group
1750. 132nd Ave., NE
.
.
Bellevue, WA 980.0.5
Parrot! Electronics
80.58 S.W. Nimbus Dr.
Tel: (20.6) 453.830.0._._____
' _ _ _._____. __ .. _. ____ ._____ _
B~a.Yerto!l,-9!'19!()()~---·---·----TWX;:9fD:-443:2526
_
- - - - . - - - . - - - - - - . - -..- - - - ·'el: (50.3) 641·3355
.
.
TWX: 910.·467-8720.

8·32
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