1981_Intersil_Power_MOS 1981 Intersil Power MOS

User Manual: 1981_Intersil_Power_MOS

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"Never confuse
motion with
action."
Benjamin
Franklin,
··1706-1790

U~Ulb
N·Channel Power MOS FETs

TO·3

BREAKDOWN

TO·220

TO·39

TO·52

TO·237

IVN6300SNS/T/U
0.1A, 7Sll

IVN6300ANS/T IU
0.1A, 7Sll

IVN6300SNM/P
0.12A,2S0

IVN6300ANM/P
0.12A,2S0

800V,
700V

IVN6200KNW/X
2.SA,60

IVN6200CNW/X
2.SA,60

SOOV,
4S0V,
400V

IVN6200KNS/T/U
SA,1.S0

IVN6200CNS/T/U
SA,1.S0

IVN6000TNS/T/U
1A,40

IVN6000KNS/T IU
2A,40

IVN6000CNS/TIU
1.7SA,40

IVN6100TNS/T/U
O.3A,1S0

2S0V,
200V

IVN6200KNM/P
10A,0.SO

IVN6200CNM/P
10A, O.Sll

100V,
BOV,
60V

IVN6200KNE/F/H
10A,0.2S0

IVN6200CNE/F/H
10A, 0.2Sll

IVNS200TNE/F/H
4A,0.SO

IVNSOOOSNE/F/H
0.9A,2.Sll

IVNSOOOANE/F/H
0.7A,2.S0

IVNS200KNE/F/H
SA,O.Sll

IVNS201CNE/F/H
SA,O.SO

IVNSOOOTNE/F/H
1.2A, 2.Sll

IVN6300SNE/F/H
0.2SA,7.S0

IVN6300ANE/F/H
0.2SA,7.S0

2nd Source Products

90V
to
3SV

Non·Zener
TO·39

Zener
TO·39

Zener
TO·202

Zener
TO·237

Zener
Quad

VN3S·99AK

VN30·90AB

VN40·89AF

VN10KM

VQ1000CJ

2N6660·1

ABOUT OUR COVER
We, at Intersil, believe in using the wisdom of the past to help
turn today's ideals into tomorrow's realities. This policy is
reflected in our advertising posters, each of which shows one
of history's great thinkers.
A copy of one or all of the posters is yours for the asking. See
the back of this brochure for other details.

Intersil reserves the right to make changes in the
circuitry or specifications contained herein at
any time without notice.
Intersil assumes no responsibility for the use of
any circuits described herein and makes no
representations that they are free from patent
infringement.

Intersil, Inc.
10710 N. Tantau Avenue
Cupertino, California 95014
U.S.A.
Tel: (408) 996-5000
TWX: 910-338-0171 (INTRSLINT CPTO)
Printed in U.S.A. © Copyright 1981, Intersil, Inc., All Rights Reserved.

TABLE OF CONTENTS
Technology Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Part Numbering System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1750 Optional Hi-Rei Process Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOS Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power MOS Data Sheets:
IVN5000 AN Series ............. " 9
IVN5000SN Series ............... 9
IVN5000 TN Series. . . . . . . . . . . . . .. 9
IVN5001 AN Series. . . . . . . . . . . . . .. 9
IVN5001 SN Series. . . . . . . . . . . . . .. 9
IVN5001 TN Series. . . . . . . . . . . . . .. 9
IVN5200 HN Series ............... 11
IVN5200 KN Series ............... 11
IVN5200 TN Series ............... 11
IVN5201 CN Series ............... 13
IVN5201 HN Series ............... 11
IVN5201 KN Series ............... 11
IVN5201 TN Series ............... 11
IVN6000 CN Series ............... 15
IVN6000 KN Series ............... 17
IVN6000 TN Series ............... 15
IVN6100 TN Series ............... 19
IVN6200 CN Series ............... 20
IVN6200 KN Series ............... 20
IVN6300 AN Series ............... 22
IVN6300 SN Series ............... 22

2N6660* ................ 24
2N6661 * ................ 24
VN10 KM* ............... 26
VN30AB" ............... 27
VN35AB" ............... 27
VN35AK" ............... 29
VN40AF" ............... 31
VN46AF" ............... 33
VN66AF" ............... 33
VN66AK* ............... 29
VN67 AB" ............... 27
VN67 AF" ............... 31
VN67 AK" ............... 29
VN88AF' ............... 33
VN89AB" ............... 27
VN89AF* ............... 31
VN90AB" ............... 27
VN98AK* ............... 29
VN99AK* ............... 29
VQ1000 CJ * ............. 35

Power MOS Geometries ....................................................................... , 36
Typical Performance Curves:
5000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5200 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

37
40
43
47

Application Notes:
A033
A034
A035
A036
A037

The Power MOSFET, A Breakthrough in Power Device Technology ....................... , 49
The Design of Switchmode Converters Above 100 kHz .. ',' .............. '................. 63
SwitchmodeConverterTopologies- Make Them Work for You ........................... 79
Using the Power MOSFET as a Switch ................................................ 111
High Performance Off-Line Switch Mode Power Supply .................................. 141

Intersil Sales Offices, Representatives, Distributors ................................................ 147
* Second Source Siliconix Devices

D~Dlb
Technology Description
Conventional VMOS devices begin to exhibit a high failure rate when operating at
voltages greater than 150V, and the groove spacing required to allow such voltages
makes the die size impractical. To alleviate these problems, Intersil has developed a
vertical DMOS (double diffused MOS) process which is capable of handling voltages
up to BOOV. This structure, shown below, begins with an n- epi layer grown on an n+
substrate. Regions of p- are then diffused, and inside these, regions of n+. A silicongate is embedded in Si02 and the source and gate metallization are then added to
complete the device. The current flow is at first vertical and then horizontal, with the
drain on the n+ substrate. The result is a structure which features both low ON
resistance and low gate resistance.

N+ SUBSTRATE

CURRENT FLOW
DRAIN
SOURCE

Vertical DMOS Structure

NOTE: Several different geometries have been developed, each to suit a particular requirement. The
number in the lower right hand corner of the box containing the schematic, etc., refers to the
specific geometry used for that device. See the geometry section in the back of the book.

O~OlL
Intersil Part Numbering System
In addition to a wide assortment of second-source Power MOSFET devices, Intersil
also manufactures products numbered according to the following system.
With the exception of parts in die and wafer form, part numbers are available as
contained in the current Intersil OEM price list. Contact the nearest Intersil Sales
Office or authorized representative for price and availability information on dice
and wafers.

6200
-r-

Breakdown Voltage
Z if Zener
N if Non-Zener

' - - - - - - - - Package Code
' - - - - - - - - - - Geometry Number
L...-_ _ _ _ _ _ _ _ _ _ _

1-.-_ _ _ _ _ _ _ _ _ _ _ _

BREAKDOWN VOLTAGE
A
B
C
D
E
F
G
H

J
K
L
M

20
30
35
40
60
80
90
100
125
150
175
200

N
P
Q

R
S
T
U
V
W

X
Y
Z

Nor P Channel
Intersi! Power MOSFET
PACKAGE CODES

225
250
300
350
400
450
500
600
700
800
900
1000

TO-237 (92+)
TO-202
TO-220
DICE
TO-66
TO-3
TO-52
TO-39
WAFER

A
B
C
D
H
K
S
T
W

Second-Source Part Numbers
Refer to current Intersil price list for available VN series part numbers.
Contact the l'Iearest Intersil Sales Office or authorized representative for price and
availability information on second-source dice and wafers.

/750 Optional Hi-Rei
Process Flow

U~UlL

PRESEAL VISUAL
M2072

I
STABILIZATION BAKE
M1032 (24 HRS. @150°C)

I
TEMPERATURE CYCLE
M1051 (20 CYCLES ·65°C TO 200°)

I
CONSTANT ACCELERATION
M2006 (20KG'S, Y1 AXIS)

I
FINE LEAK
M1071 (COND. H)

I
GROSS LEAK
M1071 (COND. C1)

I
100% ELECTRICAL
DC @ 25°C

I
BURN·IN HTRB
M1039 (168 HRS. @ 150°C)

I
100% ELECTRICAL
DC @25°C

I
•
•
•
•

QA LOT ACCEPTANCE
LTPD=5
VIS/MECH M1071
LTPD=5
DC @ 25°C
DC @ 125°C
LTPD= 10
DC @ -55°C
LTPD= 10

I
DATA PREP
• C OF C WITH SHIPMENT
4

O~OlL

POWER MOS CROSS-REFERENCE GUIDE
INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

2N4881
2N4882
2N4883
2N4884
2N4885

IVN6100TNS
IVN6100TNS
IVN6100TNS
IVN6100TNS
IVN6100TNS

IRF332
IRF333
IRF350
IRF351
IRF352

IVN6200KNS
IVN6200KNS
IVN6400KNS
IVN6400KNS
IVN6400KNS

IRF730
IRF731
IRF732
IRF733
IRF820

IVN6200CNS
IVN6200CNS
IVN6200CNS
IVN6200CNS
IVN6000CNU

2N4886
2N6656
2N6657
2N6658
2N6659

IVN6100TNS
IVN5200KNO
IVN5200KNE
IVN5200KNF
2N6660

IRF353
IRF420
IRF421
IRF422
IRF423

IVN6400KNS
IVN6000KNU
IVN6000KNT
IVN6000KNU
IVN6000KNT

IRF821
IRF822
IRF823
IRF830
IRF831

IVN6000CNT
IVN6000CNU
IVN6000CNT
IVN6200CNU
IVN6200CNT

2N6660
2N6661
90512
90522
9S170

2N6660
2N6661

IVN6200KNU
IVN6200KNT
IVN6200KNU
IVN6200KNT
IVN6400KNU

IRF832
IRF833
IRF9130
IRF9131
IRF9132

IVN6200CNU
IVN6200CNT

VN66AF
IVN5000ANO

IRF430
IRF431
IRF432
IRF433
IRF450

9S250
HPWR6501
HPWR6502
HPWR6503
HPWR6504

IVN6400KNT
IVN6400KNS
IVN6200KNT
IVN6200KNS

IRF451
IRF452
IRF453
IRF510
IRF511

IVN6400KNT
IVN6400KNU
IVN6400KNT
IVN5201CNH
IVN5201CNE

IRF9133
IRF9520
IRF9521
IRF9522
IRF9523

IRF120
IRF121
IRF122
IRF123
IRF130

IVN6200KNH
IVN6200KNE
IVN5201KNH
IVN5201KNE
IVN6200KNE

IRF512
IRF513
IRF520
IRF521
IRF522

IVN5201CNH
IVN5201CNE
IVN6200CNH
IVN6200CNE
IVN5200CNH

IRF9530
IRF9531
IRF9532
IRF9533
IVN5000ANO

IRF131
IRF132
IRF133
IRF150
IRF151

IVN6200KNH
IVN6200KNE
IVN6200KNM

IRF523
IRF530
IRF531
IRF532
IRF533

IVN5200CNE
IVN6200CNH
IVN6200CNE
IVN6200CNH
IVN6200CNE

IVN5000ANE
IVN5000ANF
IVN5000ANH
IVN50009NO
IVN50009NE

IVN6100CNM
IVN6100CNM
IVN6100CNM
IVN6100CNM
IVN6200CNM

IVN50009NF
IVN5000SNO
IVN5000SNE
iVN5000SNF
IVN5000SNH

IVN5000SNO
IVN5000SNE
IVN5000SNF
IVN5000SNH

..
..

....
....

..
..
....

....
..
......
..

IVN5000ANO
IVN5000ANE
IVN5000ANF
IVN5000ANH

....
..

IRF152
IRF153
IRF220
IRF221
IRF222

IVN6200KNM
IVN6200KNM
IVN6200KNM

IRF610
IRF611
IRF612
IRF613
IRF620

IRF223
IRF230
IRF231
IRF232
IRF233

IVN6200KNM
IVN6200KNM
IVN6200KNM
IVN6200KNM
IVN6200KNM

IRF621
IRF622
IRF623
IRF630
IRF631

IVN6200CNM
IVN6200CNM
IVN6200CNM
IVN6200CNM
IVN6200CNM

IVN5000TNO
IVN5000TNE
IVN5000TNF
IVN5000TNH
IVN5001ANO

IVN5000TNO
IVN5000TNE
IVN5000TNF
IVN5000TNH
IVN5000ANO

IRF250
IRF251
IRF252
IRF253
IRF320

IVN6400KNM
IVN6400KNM
IVN6400KNM
IVN6400KNM
IVN6000KNS

IRF632
IRF633
IRF710
IRF711
IRF712

IVN6200CNM
IVN6200CNM
IVN6000CNS
IVN6000CNS
IVN6000CNS

IVN5001ANE
IVN5001ANF
IVN5001ANH
IVN50019NO
IVN50019NE

IVN5001ANE
IVN5001ANF
IVN5001ANH

IRF321
IRF322
IRF323
IRF330
IRF331

IVN6000KNS
IVN6000KNS
IVN6000KNS
IVN6200KNS
IVN6200KNS

IRF713
IRF720
IRF721
IRF722
IRF723

IVN6000CNS
IVN6000CNS
IVN6000CNS
IVN6000CNS
IVN6000CNS

IVN50019NF
IVN5001SNO
IVN5001SNE
IVN5001SNF
IVN5001SNH

··Consult factory

....
..

IVN5001SNO
IVN5001SNE
IVN5001SNF
IVN5001SNH

U~U[l
INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

IVN500HNO
IVN500HNE
IVN500HNF
IVN500HNH
IVN5200HNO

IVN6200KNE
IVN6200KNF
IVN6200KNH
IVN6200KNM
IVN6200KNP

S02050B
S0220H
VN0104N2
VN0104N3
VN0104N5

VN66AK
IVN5000TNE
IVN5000TNO
IVN5000ANO
VN46AF

IVN5200HNE
IVN5200HNF
IVN5200HNH
IVN5200KNO
IVN5200KNE

IVN6200KNS
IVN6200KNT
IVN6200KNU
IVN6200KNW
IVN6200KNX

VN0106N2
VN0106N3
VN0106N5
VN0106N6
VN0108N2

VN67AK
IVN5000ANE
VN66AF
VQ1000CJ
VN99AK

IVN5200KNF
IVN5200KNH
IVN5200TNO
IVN5200TNE
IVN5200TNF

IVN6300ANE
IVN6300ANF
IVN6300ANH
IVN6300ANM
IVN6300ANP

VN0108N3
VN0108N5
VN0108N6
VN0109N2
VN0109N3

IVN5000ANF
VN88AF

IVN5200TNH
IVN5201CNO
IVN5201CNE
IVN5201CNF
IVN5201CNH

IVN6300ANS
IVN6300ANT
IVN6300ANU
IVN6300SNE
IVN6300SNF

VN0109N5
VN0204N1
VN0204N2
VN0204N5
VN0206N1

IVN5200KNO
IVN5000TNO
IVN5200CNO
IVN5200KNE

IVN5201HNO
IVN5201HNE
IVN5201HNF
IVN5201HNH
IVN5201KNO

IVN6300SNH
IVN6300SNM
IVN6300SNP
IVN6300SNS
IVN6300SNT

VN0206N2
VN0206N5
VN0208N1
VN0208N2
VN0208N5

IVN5000TNE
IVN5200CNE
IVN5200KNF
IVN5000TNF
IVN5200CNF

IVN5201KNE
IVN5201KNF
IVN5201KNH
IVN520HNO
IVN520HNE

IVN6300SNU
IVN6660
IVN6661
MTM1224
MTM1225

IVN6300SNU
IVN6660
IVN6661
IVN6200KNE
IVN6200KNH

VN0209N1
VN0209N2
VN0209N5
VN0330N1
VN0330N2

IVN5200KNH
IVN5000TNH
IVN5200CNH
IVN6000KNR
IVN6000TNS

IVN520HNF
IVN520HNH
IVN6000CNS
IVN6000CNT
IVN6000CNU

IVN520HNF
IVN520HNH
IVN6200CNS
IVN6000CNT
IVN6000CNU

MTM474
MTM475
MTM564
MTM565
MTP1224

IVN6200KNT
IVN6200KNU
IVN6200KNS
IVN6200KNS
IVN6200CNE

VN0330N5
VN0335N1
VN0335N2
VN0335N5
VN0340N1

IVN6000CNS
IVN6000KNR
IVN6000TNS
IVN6000CNS
IVN6000KNS

IVN6000KNR
IVN6000KNS
IVN6000KNT
IVN6000KNU
IVN6000TNS

MTP1225
MTP474
MTP475
MTP564
MTP565

IVN6200CNH
IVN6200CNT
IVN6200CNU
IVN6200CNS
IVN6200CNS

VN0340N2
VN0340N5
VN0345N1
VN0345N2
VN0345N5

IVN6000TNS
IVN6000CNS
IVN6000KNT
IVN6000TNT
IVN6000CNT

IVN6000TNT
IVN6000TNU
IVN6100TNS
IVN6100TNT
IVN6100TNU

PV210
PV211
PV212
S75V02
S75V03

VN35AK
VN67AK
VN99AK
VN88AF

VN0430N1
VN0435N1
VN0440N1
VN0445N1
VN10KE

IVN6200KNS
IVN6200KNS
IVN6200KNS
IVN6200KNT
IVN6300SNE

IVN6200CNE
IVN6200CNF
IVN6200CNH
IVN6200CNM
IVN6200CNP

S01002KO
S01011KO
S01012KO
S01021KO
S0110000

IVN6200KNT
IVN6200KNS
IVN6200KNS
IVN6200KNS
IVN6100TNT

VN10KM
VN1204N1
VN1204N2
VN1204N5
VN1206N1

VN10KM
IVN5200KNO
IVN5200TNO
IVN5201CNO
IVN5200KNE

IVN6200CNS
IVN6200CNT
IVN6200CNU
IVN6200CNW
IVN6200CNX

S01100HO
S0110100
S01101 HO
S0120000
S0120100

IVN6100TNT
IVN6100TNS
IVN6100TNS
IVN6300TNT
IVN6300TNS

VN1206N2
VN1206N5
VN1208N1
VN1208N2
VN1208N5

IVN5200TNE
IVN5201CNE
IVN5200KNF
IVN5200TNF
IVN5201CNF

"Consult factory

IVN5000TNH

O~OlL
INDUSTRY
STANDARD

NEAREST
INTERSIL
EQUIVALENT

VN1209N1
VN1209N2
VN1209N5
VN1304N2
VN1304N3

NEAREST
INDUSTRY
INTERSIL
STANDARD EQUIVALENT

INDUSTRY
STANDARD

IVN5200KNH
IVN5200TNH
IVN5201CNH
IVN5000TND
IVN5000AND

VN98AK
VN99AK
VP0104N1
VP0104N2
VP0104N3

VP0209N1
VP0209N2
VP0209N6
VP1204N1
VP1204N2

VN1304N6
VN1306N2
VN1306N3
VN1306N6
VN1308N2

V01000CJ
IVN5000TNE
IVN5000AND
V01000CJ
IVN5000TNE

VP0104N5
VP0104N6
VP0106N1
VP0106N2
VP0106N3

VN1308N3
VN1308N6
VN1309N2
VN1309N3
VN1309N6

IVN5000ANE

..
....

VP0106N5
VP0106N6
VP0108N1
VP0108N2
VP0108N3

VN30AB
VN33AK
VN3500A
VN3501A
VN35AB

VN30AB
VN35AK
IVN6200KNS
IVN6200KNS
VN35AB

VP0108N5
VP0108N6
VP0109N1
VP0109N2
VP0109N3

VN35AK
VN4000A
VN4001A
VN40AF
VN46AF

VN35AK
IVN6200KNS
IVN6200KNS
VN40AF
VN46AF

VP0109N5
VP0109N6
VP0204N1
VP0204N2
VP0204N5

VN64GA
VN66AF
VN66AK
VN67AB
VN67AF

IVN6200KNE
VN66AF
VN66AK
VN67AB
VN67AF

VP0204N6
VP0206N1
VP0206N2
VP0206N5
VP0206N6

VN67AK
VN88AF
VN89AB
VN89AF
VN90AB

VP0208N1
VP0208N2
VP0208N5
VP0208N6
VP0208N6

IVN5000TNH

"Consult factory

VN98AK
VN99AK

....
..

......
....
....
....
..
....
....
..
....

....

IVP5200CNE

....

IVP5200CNE

....
....

IVP5200CNH

VP1204N5
VP1206N1
VP1206N2
VP1206N5
VP1208N1
VP1208N2
VP1208N5
VP1209N1
VP1209N2
VP1209N5
VP1304N2
VP1304N6
VP1306N2
VP1306N6
VP1308N3
VP1308N6
VP1309N6
V01000CJ

NEAREST
INTERSIL
EQUIVALENT

....
......

....

IVP5200CNE

..
..
....

IVP5200CNE

IVP5200CNF

IVP5200CNH

....

....
..
....
V01000CJ

U~UIb

FEATURES

IVN5000/1 AN Series
IVN5000/1 SN Series
IVN5000/1 TN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

• High speed, high peak current switching

APPLICATIONS

• Inherent current sharing capability when paralleled

• LED and lamp drivers

• Directly interfaces to CMOS, DTL, TTL logic

• High gain, wide-band amplifiers

• Simple, straight-forward DC biasing

• High speed switches

• Inherent protection from thermal runaway

• Line drivers

• Reliable, low cost plastic package

• Logic buffers

ABSOLUTE MAXIMUM RATINGS

• Pulse amplifiers

(TA = 25°C unless otherwise noted)
Drain-source Voltage
D devices .............................. 40V
E devices ............................... 60V
F devices ............................... BOV
H devices ............................. 100V
Drain-gate Voltage
D devices ........... . . . . . . . . . . . . . . . . . .. 40V
E devices ............................... 60V
F devices ............................... BOV
H devices ............................. 100V
Continuous Drain Current (see note 1)
AN devices ............................ 0.7A
SN devices ............................. 0.9A
TN devices ............................. 1.2A
Peak Drain Current (see note 2)
AN devices ............................ 2.0A
SN, TN devices ......................... 3.0A
Gate-source Forward Voltage .............. +30V
Gate-source Reverse Voltage .............. +30V
Thermal Resistance, Junction to Case
AN devices ........................ 62.5·C/W
SN devices .......................... 40·C/W
TN devices .......................... 20·C/W
Continous Device Dissipation at (or below)
25·C Case Temperature
AN devices ............................ 2.0W
SN devices ........................... 3.13W
TN devices ........................... 6.25W
Linear Derating Factor
AN device ......................... 16mW/·C
SN devices ........................ 25mW/·C
TN devices ........................ 50mW/·C
Operating Junction
Temperature Range .......... -55·C to + 150·C
Storage Temperature Range ..... -55·C to +150·C
Lead Temperature
(1/16 in. from case for 10 sec) .......... + 300·C

SCHEMATIC DIAGRAM

AN Series (TO·237)

AN
devices
GATE
o---~

SOURCE

SN Series (TO·52)
TN Series (TO·39)

GATE

SOURCE

ORDERING INFORMATION

IVN5000 S N

~B'''kgO:~~".g,
E = 60V
F
BOV
H = 100V
No zener

Note 1. Tc 0 25°C; controlled by typical rOS(on) and maximum
power dissipation.

Package
A = TO-237
S = TO-52
' - - - - - - - T = TO·39

Note 2. Maximum pulse width 80!,sec. maximum duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

5000

IVN5000/1 AN Series

O~OIL

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted), Vas
CHARACTERISTICS

Drain-Source
Breakdown
Voltage

Gate
VaS(th) Threshold
Voltage
lass

Devices
E Devices
F Devices
H Oevices
IVNSOOO Series

0.8

2.0

IVNS001 Series

0.8

3.6
10

TEST CONDITIONS

Vas = 0,1 0 = 10pA

Vos=Vas,lo=tmA

Gale·Body Leakage

Vas - 1SV, Vos = 0
nA

Vas = tSV, Vos = 0, TA = + t2S'C

Vos - Max. Rating, Vas - 0

Zero Gale Voltage
Drain Current
ON·Slate

MAX
V

S
T
A
loss
T

UNIT

MIN
40
60
80
100

BVoss

IVN5000
IVN5001
TYP

SOO
IVNSOOO Series

1.0

1.9

Vos = 0.80 Max. Raling, Vas = 0, TA = +12S'C
Vos = 24V, Vos = 10V

10(on)
Drain Current

IVNSOOI Series

Drain·Source
VOS(on) Saluralion
Voltage

IVNSOOO Series

1.0

1.9
2.0

Vas = 24V, Vas = 12V
Vas = 10V, 10 - 1.0A

2.S
V

IVNSOOI Series

1.9

2.S

IVNSOOO Series

2.0

2.S

IVNSOOI Series

1.9

2.S

IVNSOOO Series

2.0

2.5

VGS = 10V

IVNSOOI Series

1.9

2.S

Vas = 12V

Vas - 12V, 10 - I.OA
(Nolel)

Stalic Drain·
rOS(on) Source ON
Resistance
rds(on)

Small·Signal
Drain-Source
ON Resislance

Vas = 10V
10= I.OA

gls
D
Y C iss

Inpul Capacitance

Forward Transconductance

170

280
40

N Coss

Oulpul Capacilance

Reverse Transfer Capacitance

Turn·ON Delay Time

Rise Time

td(Off)

Turn·OFF De)ay Time

Fall Time

5
5

mmho
pF

Vas = 12V
10= 1.0A
1= 1KHz

Vos - 24V, 10 - 0.5A, 1- 1KHz
VOS = 24V, Vas = 0
(Note2)

M Crss
I

C td(onl
I,

1= IMHz
See Swithching Times Test
(Note2)

Note 1. Pulse tesl - 80psec. 1% duty cycle.
Note 2. Sample test.

Note: For other 5000 family characteristic curves, see page

Circuit

IVN5200/1 HN Series
IVN5200/1 KN Series
IVN5200/1 TN Series
n-Channel Enhancement-mode
Vertical Power MOSFETs
FEATURES

APPLICATIONS

• High speed, high current switching

• High efficiency switching power supplies

• Inherent current sharing capability when paralleled

• Off-line switching regulators

• Directly interfaces to CMOS, DTL, TTL logic

• High speed, high current switches

• Simple, straight-forward DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature stable

• High peak current pulse amplifiers

• Low ON resistance in small package

• DC motor controllers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A = 25° C unless otherwise noted)

TN SERIES (TO-39)

DRAIN

Drain-source Voltage
o devices .................................... 40V
E devices ..................................... 60V
F devices ..................................... BOV
H devices ................................... 100V
Drain-gate Voltage
o devices ..................................... 40V
E devices ..................................... 60V
F devices ..................................... BOV
H devices ................................... 100V
Continuous Drain Current (see note 1)
HN, KN devices ............................... S.OA
TN devices ................................... 4.0A
Peak Drain Current (see note 2)
HN, KN devices ............................... 12A
TN devices .................................. 10.0A
Gate-source Forward Voltage .................... + 30V
Gate-source Reverse Voltage .................... - 30V
Thermal Resistance, Junction to Case
HN devices .............................. 4.17°C/W
KN devices ............................... 2.S °C/W
TN devices ................................ 10°C/W
Continuous Device Dissipation at (or below)
2SoC Case Temperature
HN devices .................................. 30W
KN devices .................................. SOW
TN devices ................................. 12.SW
Linear Derating Factor
HN devices ............................. 240mW/oC
KN devices ............................. 400mW/oC
TN devices ............................. 100mW/oC
Operating Junction
Temperature Range ............... -SsoC to + 1S0°C
Storage Temperature Range .......... -SsoC to + 1S0°C
Lead Temperature
(1/16 in. from ca&e for 10 sec) ................ +300°C

(see note 3)

I-- -,I
GATE
o~~~--'

l*
SOURCE

KN SERIES (TO-3)

HN SERIES (TO-66)

SOURCE~2
GATE

T0-88

DRAIN

GATE

SOURC~
GATE~

3 DRAIN

IVN5201

~
Basic

Note 1. TC = 25 ·C; controlled by typical rOS(on) and maximum
power dissipation.

pari
number

Note 2. Pulse width 80l'sec, duty cycle 1.0%.

11 L_M~" ~,,~.
0=

40V

E = aov
F = SOV
H = 100V
No zener
Package

Note 3. The Drain-source diode is an itegral part of the MOSFE1
structure.

H = TO-66
K = TO-3

T = T0-39

5200

IVN5200/1 KN Series
HN Series
TN Series
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted),
CHARACTERISTICS
Drain-Source
BVOSS Breakdown
Voltage
Gate

o devices

t: eVlces
F devices
H devices

MIN TYP
40

MAX

UNIT

-~-

VBS

TEST CONDITIONS

VGS = 0, 10 = 100~A

80
100

IVN5200 Series

0_8

2_0

IVN5201 Series

0_8

3_6

VGS(th) Threshold

VOS = VGS, 10 = 5mA

Voltage
0_2
IGSS

VGS = 12V, VOS = 0
nA

Zero Gate Voltage
loss

Gate-Body Leakage

Drain Current
ON-State

100
'100

VGS = 12V, VOS = 0, TA = + 125°C
VOS - Max. Rating, VGS = 0

5.0

VOS = 0.80 Max. Rating, VGS = 0, TA =

IVN5200 Series

5.0

IVN5201 Series
IVN5200 Series

5.0

10
1.9

2.5

IVN5201 Series

1.8

2.5

IVN5200 Series

0.38

0.50

IVN5201 Series

0.36

0.50

10(on)
Drain Current
Drain-Source
VOS(on) Saturation
Voltage
Static Draln-

VOS = 24V, VGS = 12V
VGS - 10V, 10 - 5.0A
V

'{as - 12V, I.D. - 5.0A

(Note 1)

VGS = 10V

rOS(on) Source ON
Resistance
Small-Signal

+ 125°C

VOS = 24V,V GS = 10V

10 = 5.0A
Il

VGS = 12V

IVN5200 Series

0.38

0.50

VGS = 10V

rds(on) Drain-Source
ON Resistance IVN5201 Series
Forward Transconductance
gfs
Input Capacitance
C iss
Coss Output Capacitance
Reverse Transfer Capacitance
C,ss
td(on) Turn-ON Delay Time

0.36
1.0 1.8
210
160
45
4

0.50
mno

VGS = 12V f = 1KHz
VOS - 24V, 10 - 5.0A, f - 1KHz

VOS = 24V, VGS = 0, f = 1MHz

250
200

10 = 5.0A

(Note 2)

60
20
10'= 4.0A

Rise Time

tdlof!)
tf

Turn-OFF Delay Time
Fall Time

4
4

20
20

See Switching Times Test
Circuit

Note 1. Pulse test - 80"sec, 1% duty cycle.
Note 2- Sample test.

(Note 2)

U~UIb

IVN5201 CN Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Deflection coil drivers

• Inherent current sharing capability when paralleled

• Off-line switching regulators

• Directly interfaces to CMOS, DTL, TTL logic

• Power amplifiers

• Simple, straight-forward DC biasing

• DC to DC inverters

• Extended safe operating area

• Motor controllers

• Reliable, low cost plastic package

• High current line drivers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(10-220)

(Til. = 25°C unless otherwise noted)
Drain-source Voltage
IVN5201CND ........................... 40V
IVN5201CNE ............................ 60V
IVN5201CNF ............................ 80V
IVN5201CNH .......................... 100V
Drain-gate Voltage
IVN5201CND ........................... 40V
IVN5201CNE ............................ 60V
IVN5201CNF ............................ 80V
IVN5201CNH .......................... 100V
Continuous Drain Current (see note 1) ........ 5.0A
Peak Drain Current (see note 2) .............. 12A
Gate-source Forward Voltage .............. +30V
Gate-source Reverse Voltage .............. -30V
Thermal Resistance, Junction to Case ... 4.17·C/W
Continuous Device Dissipation at (or below)
25·C Case Temperature .................. 30W
Linear Derating Factor ............... 240mW/·C
Operating Junction
Temperature Range ......... -55·C to +150·C
Storage Temperature Range .... -55·Cto +150·C
Lead Temperature
(1/16 in. from case for 10 sec) .......... + 300·C

GATE

0----'

SOURCE

5200

Note 1. Tc 25°C; controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Maximum pulse width 80msec, maximum duty cycle 1.0%.
Note 3. The Drain·source diode Is an integral par of teh MOSFET
structure.

IVN5201 eN Series
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted),
IVN5201CND
MIN TYP MAX

CHARACTERISTICS
o devices
E devices
Fdevices
H devices

BVoss Drain-Source
Breakdown
Voltage
VGSCthl Gate Threshold Voltage
S
T
A
T
I
C

60
80
100

V GS

1000n)

Gate·Body Leakage

nA
100
100

5.0

Drain Current
ON·State Drain Current
Draln·Source

5.0

VoS(on) Saturation Voltage

VOS = VGS, 10
5mA
VGS - 12V, VOS - 0

= 12V, VOS = 0, TA = +125"C
= Max. Rating, VGS = 0
VOS = 0.80 Max. Rating, VGS = 0, TA = + 125"C

VGS
VOS

VOS

V
1.8

2.5

VGS

0.36

0.50

VGS

0.36

0.50

Static Drain-Source
roS(on)
rda(On)

D gfs
y Clss
N Coss
A Crss
M td(on)
1
C t,

ON Resistance
Small·Slgnal Draln-Source
ON Resistance
1.0
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn·ON Delay Time
Rise Time

td(Ofl)

Turn·OFF De)ay Time

Fall Time

= 0, 10 = 100mA
=

3.6

0.8

Zero Gate Voltage
loss

TEST CONDITIONS

V
0.2

IGSS

UNIT

= 24V, V GS = 12V
= 12V, 10 = 5.0A
= 12V, 10 = 5.0A

(Note 1)

n
1.8
210
160
45
4

250
200
60

= 12V, 10 = 5.0A f = 1KHz
VOS = 24V, 10 = 5.0A, f = 1KHz
VGS

mho

= 24V, VGS = 0, f = lMHz

VOS

See Switching Times Test

20
10

= 4.0A

Circuit,

Note 1. Pulse test - 80"sec, 1% duty cycle.
Nole 2. Sample test.

(Note 2)

IVN6000 CN Series
IVN6000 TN Series
500V n-Channel
Enhancement-mode
Vertical Power MOSFETs
FEATURES
• High speed, high current switching
• Inherent current sharing capability when paralleled

APPLICATIONS
• Switching power supplies

• Directly interfaces to CMOS logic

• Motor controllers

• Extended safe operating area

• Power amplifiers

• Inherently temperature stable

• RF amplifiers

• DC to DC inverters

ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwise noted)
Drain-source Voltage
IVN6000 CNS, TNS ...................... 400V
IVN6000 CNT, TNT ...................... 450V
IVN6000 CNU, TNU ...................... 500V
Drain-gate Voltage
IVN6000 CNS, TNS ...................... 400V
IVN6000 CNT, TNT ...................... 450V
IVN6000 CNU, TNU ...................... 500V
Continuous Drain Current
IVN6000 CNS, CNT ........................ 2A
IVN6000 CNU .......................... 1.75A
IVN6000 TNS, TNT ....................... 1.0A
IVN6000 TNU ............................ 0.9A
Peak Drain Current (see note)
CN devices ............................... 6A
TN devices ............................... 3A
Gate-source Voltage ...................... ± 30V
Thermal Resistance, Junction to Case
CN devices ......................... 4.17°CIW
TN devices ........................... 10°CIW
Continuous Device Dissipation at (or below)
25°C Case Temperature, CN devices ........ 30W
TN devices ............................ 12.5W
Linear Derating Factor
CN devices ........................ 240mW/oC
TN devices ........................ 100mW/oC
Operating Junction
Temperature Range .......... -55°Cto + 150°C
Storage Temperature Range .... - 55°C to + 150°C
Lead Temperature
(1/16" in. from case for 10 sec) .......... + 300°C
Reverse Diode Continuous Forward Current
CN devices ............................... 2A
TN devices ............................... 1A
Reverse Diode Peak Forward Current
CN devices ............................... 6A
TN devices ............................... 3A

SCHEMATIC DIAGRAM
DRAIN

CN Series (TO·220)

SOURCE

Body internally connected to source.
Drain common to case.

ORDERING INFORMATION

TN Series (TO-39)

IVN6000 eNS

1r-B-'''''''~'
= 400V
= 450\1

s
T

= 500V
No Zener

Package
C
T

= TO-220

= TO-39

'------Basic part number

GATE

SOURCE

6000

Note: Maximum pulse width 80 "sec, maximum duty cycle 1.0%

D~DIL

IVN6000 eN Series

LIMITS
PARAMETER
Drain-Source
Breakdown Voltage
IVN6000 CNS, TNS

SYMBOL
BVDSS

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

VGS = OV
10 = 100 !LA
400

IVN6000 CNT, TNT

4S0

IVN6000 CNU, TNU
Gate-Threshold Voltage
Gate-Body Leakage Current

SOO
VGS(th)
IGSS

Zero Gate Voltage
Drain Current

loss

ON Drain Current[1]

10(on)

Static-Drain Source
ON Resistance[1]
IVN6000 CNS, CNT

rOS(on)

Vos = VGS, 10 = 10mA
VGS = 30V
VOS = Maximum Rating, VGS = OV
TJ = 12SoC
IeN devices
Vos = SOV, VGS = 1SV
ITN devices

V
S

2
10

100

0.2

3.S

VGS = 1SV, 10 = 1A

4.0

IVN6000CNU
Forward Transconductance[1]

gfs

Input Capacitance

Ciss

Output Capacitance
Reverse Transfer Capacitance

Coss
Crss

Rise Time

Fall Time
Slew Rate

tf
SR

Vos = 200V, 10 = 1.SA

0.8

mho

0.9
220

300

Vos = 100V,f= 1.0MHz,

VGS = OV
Vos = 200V, 10 = 1.0A,

VGS = 1SV, Raen = 6n
VGS = OV, Vos = 300V

ns
V/ns

UNIT

100

Note: 1. Pulse Test: 80fLS, 1% duty cycle

REVERSE DIODE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

Forward Voltage Drop

Forward Current = 2A

0.9S

1.2

Reverse Recovery Time

trr

Ifwd(pk) = Irev(pk) Recovery to SO%

100

Recovered Charge

Orr

TJ = 1S0°C, Ifwd(pk) = 2A

200

U~UlL

IVN6000 KN Series
500V n-Channel
Enhancement-mode
Vertical Power MOS FETs

FEATURES

APPLICATIONS

High speed, high current switching

Switching power supplies

Inherent current sharing capability when paralleled

DC to DC inverters

Directly interfaces to CMOS logic

Motor controllers

Simple, straight-forward DC biasing

Power amplifiers

Extended safe operating area

RF amplifiers

Inherently temperature stable

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A = 25° C unless otherwise noted)
Drain-source Voltage
IVN6000KNR _.......................... 350V
IVN6000KNS ........................... 400V
IVN6000KNT .......... _................. 450V
IVN6000KNU ........................... 500V
Drain-gate Voltage
IVN6000KNR ........................... 350V
IVN6000KNS ........................... 400V
IVN6000KNT ............................ 450V
IVN6000KNU ........................... 500V
Continuous Drain Current (see note 1) ..... _... 2.5A
KNU only ............................... 2.0A
Peak Drain Current (see note 2) ............... 7.5A
Gate-source Voltage ...................... ±30V
Thermal Resistance Junction to Case ..... . 3.0·C/W
Continuous Device Dissipation at (or below)
25·C Case Temperature ................. 41.7W
Linear Derating Factor ................ 333mW/·C
Operating Junction
Temperature Range .......... -55·C to + 150·C
Storage Temperature Range ..... -55°C to + 150·C
Lead Temperature
(1/16 in. from case for 10 sec) ........... +300·C
Body-drain Diode Continuous Forward Current ... 3A
Body-drain Diode Peak Forward Current ........ 10A

(TO·3)

SOURCE

6000

Note 1. Tc = 25 'C; cuntrolied by typical rOSlon) and maximum
power dissipation.
Note 2. Maximum pulse width 80sec, maximum duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

O~OIb

IVN6000 KN Series
ELECTRICAL CHARACTERISTICS TA

= 25°C, unless otherwise specified
LIMITS

PARAMETER
Drain-Source
Breakdown Voltage
IVN6000KNR
IVN6000KNS

SYMBOL

TEST CONDITIONS

MIN.

VGS =OV
10 = 100"A
BVoss

400

450
500
VGS(th)
IGSS

Vos = VGS, 10 = 10 mA

Zero Gate Voltage
Drain Current

loss

VOS = Maximum Rating, VGS = OV
TJ = 125°C

ON Drain Current!'!

10(on)

Vos = 25V, VGS = 15V

Gate-Threshold Voltage

UNIT

350

IVN6000KNT
IVN6000KNU
Gate-Body Leakage Current

TYP. MAX.

Static-Drain Source
ON Resistance!'!

rOS(on)

Forward Transconductance!'!

gls

Input Capacitance

Ciss

Output Capacitance

Coss

Reverse Transfer Capacitance

Cros

VGS

VGS
VoS

1.5

= 30 V

KNU

Rise Time

tr
tl

Vos = 200V, 10 = 1.0A,
VGS = 15V, Rgen = 60

Slew Rate

VOS

0.2

6
2.5
3.5
1.0

3.0
4.0

220

300

0.8

Vos = 100V, f = 1.0 MHz, V GS = OV

Fall Time

100

= 15V, 10 = 1A
= 200V, 10 = 1.5A

5
10

= 400V, VGS = 0

A
0
mho

100

pF
ns
ns
V/ns

Note: 1. Pulse Test: 80"s, 1% duty cycle.

BODY-DRAIN DIODE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP. MAX.

Peak Forward Current = 2A

0.95

Reverse Recovery Time

trr

Ifwd(pk) - Irev(pk) Recovery to 50%

100

Recovered Charge

Orr

T J = 150° C, liwd(pk) - 2A

200

1.1

UNIT

Forward Voltage Drop

IVN6100 TN Series
500V n-Channel
Enhancement-mode
Vertical Power MOS FETs
FEATURES

APPLICATIONS

•
•
•
•
•
•

High breakdown voltage
Very low input capacitance
Extremely fast switching
Low OFF leakage
Direct interface with CMOS, TTL logic
Extended safe operating area

ABSOLUTE MAXIMUM RATINGS

Telecommunications
High voltage signal processing
Logic interfaces
Display drivers
Electrostatic printers
Pulse generators

SCHEMATIC DIAGRAM

Drain-source Breakdown Voltage
TNS
TNT _ _ _ _ _ _ _ _ _ _
TNU _ _ _ _ _ _ _ • • •

TO·39

_400V
_450V
• 500V

Continuous Drain Current •
• 0.3A
Peak Drain Current • • _ •
• • 3A
Gate-Source Voltage • • •
± 30V
Thermal Resistance, Junction to Case • • • • • • 20'C/W
Continuous Device Dissipation (25'C Case Temp) 6.25W
Linear Derating Factor • • • • • • • • • • • 50mW/oC

SOURCE

GATE

SOURCE

6100

ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Drain-source breakdown voltage
BVoss

MIN_

TEST CONDITIONS
VGS

= OV, 10 = 1OOl'A

TNS

400

TNT

450

TNU

500

TYP.

MAX_

UNIT

Static ON Resistance
10

= 5A, VGS = 15V

rOS(on)
Gate-Threshold Voltage

VGS(th)

Forward Transconductance
ON Drain Current

gls
lo(on)

Zero Gate Voltage Drain Current
Rise Time

Ir
II

Fall Time

Slew Rate

=
=
=
=
VOS = 25V, VGS = 15V
VOS = VGS = 0, TJ = 125°C

VOS
VGS, 10
SmA
10
1A VOS
200V

Vos

1
250
1

5
300
0.1

= 200V, 10 = 1.0A

VGS = 15V, Roen = 60
VOS
350V

10
10

100

V/ns

Input Capacitance

Ciss

t = 1.0MHz

Outpul Capacitance
Reverse Transfer Capacitance

Coss

Vos = 100V
VGS = OV

15
13

Crss

V
mmho
A

D~DIL

IVN6200 eN Series
IVN6200 KN Series
n-Channel Enhancement-mode
Vertical Power MOSFETs

FEATURES

APPLICATIONS

•
•
•
•
•
•

•
•
•
•
•

High speed, high current switching
Inherent current sharing capability when paralled
Directly Interfaces to CMOS logic
Simple, stralght·forward DC biasing
Extended safe operating area
Inherently temperature stable

ABSOLUTE MAXIMUM RATINGS
= 25°C unless otherwise noted)

Switching power supplies
DC to DC Inverters
Motor controllers
Power amplifiers
RF amplifiers

SCHEMATIC DIAGRAM

(TA

DRAIN

Drain-source and Drain-gate Voltage
E devices __ ................................... 60V
F devices ..................................... 80V
H devices ................................... 100V
M devices ................................... 200V
P devices .................................... 2S0V
S devices ................................... .400V
T devices .................................... 4S0V
U devices ................................... SOOV
W devices ................................... 700V
X devices .................................... 800V
Continuous Drain Current (see note 1)
E, F, H, M, Pdevices ........................... 10A
S, T, U devices ................................. SA
W devices ..................................... 3A
X devices .................................... 2.SA
Peak Drain Current (see note 2)
E, F, H, M, P devices ........................... 20A
S, T, U devices ............................... 1SmA
W, X devices ................................. 7.SA
Gate-source Voltage ........................... ±30V
Thermal Resistance, J unction to Case ......... 1.2S 'C/W
Continuous Device Dissipation at (or below)
2S'C Case Temperature ....................... 100W
Linear Derating Factor ..................... 800mW/'C
Operating Junction
Temperature Range ............... -SS'C to + 1S0'C
Storage Temperature ................ -SS'C to + 1S0'C
Lead Temperature
(1/16 in. from case for 10 sec) ................ +300'C
Bod~-Drain Diode Continuous Forward Current
E, F, H, M, P devices ......................... 10A
S, T, U devices ............................... SA
W, X devices ................................. 3A
Body-Drain Diode Peak Forward Current
E, F, H, M, P devices ......................... 20A
S, T, U devices .............................. 1SA
W, X devices ............................... 7.SA

KN SERIES (TO·3)

J.':"~

.~-',J ~:::fj,.",,"
SOURCE

CN SERIES (TO·220)

f1'

S D. G
TAB

ORDERING INFORMATION
IVN6200

Note 1. Tc = 25'C; controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Maximum pulse width 80l'sec, maximum duty cycle 1.0%.
Note 3. The Drain·source diode is an integral part of the MOSFET
structure.

"-l"'C-~r~a~~~wn ~o~a~~OV
= 80V

T = 450V

H = 100V
M = 200V

U = 500V
W = 700V

P = 250V X = 800V

No Zener

paCk~g: TO·220
K

= TO·3

Basic Part Number

6200

IVN6200 eN Series
KN Series

D~D[l

OPERATING CHARACTERISTICS
LIMITS
PARAMETER

Drain Source
Breakdown Vollage

Gale Threshold Vollage

SYMBOL

TEST CONDITIONS

BVoss

Vos = VGS
10 = 10mA

VGS(th)

MIN.

E devices
F devices
H devices
M devices
P devices
S devices
T devices
U devices
W devices
X devices

800

E,F,H devices
all olhers

0.8
2

TYP.

lOSS

ON Drain Currenl(t)

lo(on)

500

700
2.5

Vos - maximum rating,

(M,P,S,T,U devices)
Vos= 100V
VOS -1001,1 W devices
X devices

10
3.0
2.5
0.2
0.5
1.5

M,P devices
5, T. U devices

rOS(on)

10 = 2.5A VOS = 50V (E,F,H devices)
Vos = 100V (M,P devices)
VOS = 200V (S,T,U,W,X
devices)

grs

600

(all others)
E, F, H devices
M,P devices
S, T, U devices

100
60
60

W,Xdevices

E,F,H devices
M,P devices
S,T,U,W,X
devices

40
30

Vos - 100V
(M,P devices)
VOS = 350V
(S,T,U devices)
Vos =,600V
rw,X devices)
Yos ~ (jOy
E,F,H Cev,ces
Vos = 100V M, P devices
VGS = 0 VGS = 350V S,T,U devices
Vos = 600V

W,X devices

10 ", 1A, VGS = 15V,
Rgen = 60, VOS = 50V (E,F,H devices)

mho

1.5

VOS - 100V

Reverse Transfer Capacilance

Fall Time

(E,F,H devices
only)

1-0_U-'IP_u_I_C_a:..pa;..c_lt_a_n_ce'-_ _ _-+_-'-c"'os"'s'-- - -

VOS = 50V
Inpul Capacilance

Slew Rale

rnA

W devices
X devices

Rise Time

Vos = 25V
VOS= 15V

Forward Transconduclance 1

250
VGs=OV,TJ = +125"C
(E,F,H devices)

Sialic Drain·Source
ON Resislance(1(

UNIT

250
400
450

Gale-Body Leakage Currenl
Zero Gale Voltage
Drain Currenl

MAX.

60
60
100
200

20
20
25
50

Vlns

100
. ----+---'''--+-----\
100

Body-Drain Diode Characteristics
Irwd(pk) = 2A
Forward Vollage Drop

E,F,H devices

0.9

M,P devices
S,T,U,W,X
devices

0.95
1.0

Reverse Recovery Time

Irwd(pk) = l,ev(pk)Recovery 10 50%

Recovered Charge

TJ = 15O"C,l rwd (pk) = 2A

(1) Pulse Test, 6O~s, 1 % duly cycle.

200
400

ns
nC

IVN6300AN Series
IVN6300 SN Series
n-Channel Enhancement-mode
Vertical Power MOS FETs
FEATURES

APPLICATIONS

•
•
•
•
•
•

High breakdown voltage
Very low input capacitance
Extremely fast switching
Low OFF leakage
Direct interface with CMOS, TTL logic
Extended safe operating area

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)

Telecommunications
High voltage Signal processing
Logic interfaces
Display drivers
Electrostatic printers
Pulse generators

SCHEMATIC DIAGRAM
SN SERIES (10·52)

Drain-source and Drain-gate voltage
E devices ______ ............................... 60V
F devices .................. '................... 80V
H devices ................................... 100V
M devices ................................... 200V
P devices .................................... 250V
S devices .................................... 400V
T devices .................................... 450V
U devices ................................... 500V
Continuous Drain Current (see note 1)
E, F, H devices ............................. 250mA
M, Pdevices ............................... 120mA
S, T, U devices .............................. 100mA
Peak Drain Current (see note 2)
E, F, H devices ............................. 700mA
M, P devices ............................... 350mA
S, T, U devices .............................. 300mA
Gate-source Voltage ........................... ±30V
Thermal Resistance, Junction to Case ......... 83.3·C/W
Continuous Device Dissipation at (25 ·C) ........... 1.5W
Linear Derating Factor ...................... 12mW/·C
Operating Junction
Temperature Range ............... - 55·C to + 150·C
Lead Temperature
(1/16 in. from case for 10 sec) ................ +300·C

ORAl"

I(888 note 3)

I
GATE

~-j

~t
_J

0----'

SOURCE

ORDERING INFORMATION

AN SERIES
(T0·237)

Note 1. Tc = 25·C; controlled by typical rOS(on) and maximum
power dissipation.
Note 2. Maximum pulse width SO"sec, maximum duty cycle 1.0%.
Note 3. The Drain-source diode Is an Integral part of the MOSFET
structure.

IVN8300

D.TA.

L
N

Breakdown
E=60V
F = SOV
H = 100V

Voltage
P=250V
5 = 400V
T = 450V

M = 200V U = 500V

No Zener
Package
A = TO-237
5 = TO-52
Basic Part Number

6300

IVN6300 AN Series
SN Series

O~OlL

OPERATING CHARACTERISTICS
PARAMETER

SYMBOL

Drain Source
Breakdown Voltage

TEST CONDITIONS
E devices
F devices
H devices
M devices
P devices

VGs=OV
BVOSS

10 = lO"A

S devices
T devices
U devices

Gate Threshold Voltage

VGSlth)

VGs=Vos.lo= 1mA

Gate·Body Leakage Current

IGSS

V GS = 30V

ON Drain Current

1010n)

VOS = 50V
VOS = 10V

MIN.

LIMITS
TYP.

0.2
M,P devices

700
350

S,T,U devices

300

rOS(on)

Forward Transconductance

gfs

Input Capacitance

C iss

VOS - 50V
los = 0.1A

f = 1MHz
Output Capacitance

Reverse Transfer Capacitance

Rise Time

Coss
C rss

VGS = OV

80
Vos = 35V (E,F,H devices)
Vos = 50V (M,P devices)
Vos = 100V (S,T,U devices)

VOS
VOS
VOS
VGS

=
=
=
=

50V (E,F,H devices)
100V (M,P devices)
200V (S,T,U devices)
15V, Rgen = 60

Fall Time

V GS = 15V, Rgen = 60

Slew Rate

80% rated Voss

mmho

100
20

10
100

7.5
25
75

M,P devices
S, T, U devices

VGs= 10V
lo=0.1A

3
50

E,F,H device
Static Draln·Source
ON Resistance

UNIT

1
E,F,H devices

MAX.

60
60
100
200
250
400
450
500

Vlns

2N666011
n-Channel
Enhancement-mode
Vertical Power MOSFET
FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly Interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature stable

• Pulse amplifiers

• 1\'pical ton and Ioff < 5ns

• High frequency linear amplifiers

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-source Voltage
2N6660 ................................. 60V
2N6661 ................................. 90V
Drain-gate Voltage
2N6660 ................................. 60V
2N6661 ................................. 90V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current .......... 2.0mA
Peak-gate Forward Current ................ 100mA
Peak-gate Reverse Current ................ 10QmA
Gate-source Forward (Zener) Voltage .......... 15V
Gate-so~rce Reverse Voltage ................ 0.3V
Thermal Resistance, Junction to Case ..... . 20·C/W
Continuous Device Dissipation at (or below)
25'C Case Temperature ................... 6.25W
Linear Derating Factor ................ . 50mW/·C
Operating Junction
Temperature Range ......... - 55'C to + 150'C
Storage Temperature Range .... - 55'C to + 150'C
Lead Temperature
(1/16 in. from case for 10 sec) ........... + 300'C

SCHEMATIC DIAGRAM

T0-39

DRAIN

J_~see

note 3)

+
I
I

.-'
GATE 0---.-....1

SOURCE

Body internally connected to source.
Drain common to case.

GATE

SOURCE

5000Z

Note 1. Tc = 25°C; comrolled by typical rDS(on) and maximum
power dissipation.
Note 2. Pulse width 80"sec. duty cycle 1.0%.
Note 3. The Drain·source diode is an integral part of the MOSFET
structure.
.

D~DIb

2N8880-1
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

""R~'" ."'~ "'"~

BVoss Drain-source
Breakdown
VOII,ge'

l\'cLS(J"L~ Thre'h

Forward Transconductance

D
Y

Ciss

Input Capacitance (Note 2)

C",

1.0

Common Source Output

0.8
0.5

MIN

TYP

VN90AB

MAX

80
0.8

1.2
0.01

0.5

MIN

TYP

MAX

90
1.2
0.01

0.8
0.5

0.01

0.5

6.0

4.5

5.1

6.0

5.0

2.2
1.0

2.5

2.0

2.2
1.0

3.5
1.0

2.0
250

250

2.2

4.5

2.0

2.2
1.0

250

5.0

Turn-ON Time (Note 2)

toff

Turn-OFF Time (Note 2)

Note 1. Pulse Test - 801lo<;, 1% duty cycle.

Ion

Note 2. Sample Test.

mmho

TEST CONDITIONS
10 ::: 10J,lA, VGS ::: 0
10::: 1.0mA, Vos ::: VGS

Vas::: lOV, Vos - 0
Ves ::: 25V, VGS ::: 0

2.0

".A

250

UNIT

1.2

Capacitance (Note 2)

VN89AB

MAX

2.0

Capacitance (Note 2)

TYP

250

Reverse Transfer

MIN

60
1.2

Drain Current
Resistance (Note 1)

VN67AB

MAX

Zero Gate Voltage

ON-State Drain Current

CO"

VN35AB

MAX

1.2

Drain-Source ON-State

10(on)

A
M
I
C

VN3DAB
MIN

VGS - 5V. 10 = 300mA
VGS - 10V, 10::: 1.0A

Vos::: 25V, VGS ::: 10V
Ves - 25V, 10 - O.SA

VGS ::: 0, Vos ::: 24V.
f = 1.0MHz

D~D(b

VN35AK Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• High current analog switches

• High gain-bandwidth product

• RF power amplifiers

• Inherently temperature stable

• Laser diode pulsers

• Extended safe operating area

• Line drivers

• Simple DC biasing

• Logic buffers

• Requires almost zero current drive

• Pulse amplifiers

I.::

ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwille noted)

SCHEMATIC DIAGRAM

Drain-source Voltage
VN35AK .................................... 35V
VN66AK, VN67 AK .......................... 60V
VN98AK, VN99AK ........................... 90V
Drain-gate Voltage
VN35AK .................................... 35V
VN66AK, VN67AK ........................... 60V
VN98AK. VN99AK ........................... 90V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Gate-source Forward Voltage .................. +30V
Gate-source Reverse Voltage .................. -30V
Thermal Resistance, Junction to Case ....... 20°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature .................... 6.25W
Linear Derating Factor ................... . 50mW/oC
Operating Junction
Temperature Range ............ -55·C to +150·C
Storage Temperature Range ...... -55·C to +150·C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C
Note 1. Tc = 25°C; controlled by typical
power dissipation.

(T0-39)

SOURCE

5000

rDS(on) and maximum

Note 2. Pulse width 80l'sec. duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

VN35AK, VN66AK, VN67AK, VN98AK, VN99AK
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

MIN
BVoss

Drain-Source Breakdown

VGsI'h}

Gate-Threshold Voltage

0.8

IGSS

Gate-Body leakage

loss

Zero Gate Voltage
Drain Current

TYP

MAX

MIN

0.8

0.5

2.0
100

lolon}

VDS(on)

gfs

Y
N
A

Giss
Coss

erss

ton

toff

ON-State Drain Current
VN66AK
VN98AK
VN3SAK
VN67AK
VN99AK
Forward Transconductance

170

Turn ON Time
Turn OFF Time

Note 1. Pulse test - 80l's pulse, 1% duty cycle.

MIN

0.8

0.5

2.0
100

VN99AK
TYP MAX

90
0.5

2.0
100
500
10

500

2.0

1.0
2.2

Input Cape itance
Common ~ )uree Output
Capacitance
Reverse Transfer Capacitance

MAX

500
10

1.0

Drain-Source

Saturation Voltage

TYP

50Q
10

100
1.0

VN96AK

5
T
T

VN66AK
VN67AK

VN35AK

CHARACTERISTIC

1.1
2.2

2.S

250

100
2.0
1.0
2.2

170

100
1.0

2.~

4.0

3.S

1.2
2.2

4.5

250
40

3
3

8
8

3
3

8
8

3
3

8
8

Note 2. Sample test.

170

V
nA

nA
A

2.0
1.1

3.0

250

UNIT

TEST CONDITIONS
VGS = 0 10 = 10"A
Vos = VGS, 10 = 1mA
VGS = 15V, Vos = 0
VGS - 1SV, VOS - 0, TA = 125'C Note 2
Vos = Max. Rating, VGS = 0
VOS - 0.8 Max. Rating, VGS - 0, TA -125'C
(Note 2)
Vos = 25V, VGS = 0
Vos = 25V, VGS = 10V
VGS ,. 5V, 10 - 0.3A
VGS = 10V, 10 - 1.0A
VGS - 5V, 10 - 0.3A

VGS - 10V, 10 - 1.0A
VOS = 24V, 10 =O.SA, f

VGS

(Note 1)

1 KHz

=0, VOS =24V, f = 1MHz

(Note 2)

O~O[b

VN40AF Series
n-Channel Enhancement-mode
Vertical Power MOSFET

FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

'. Current sharing capability when paralleled

• DC to DC inverters

• Directly interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing

• Line drivers

• Extended safe operating area

• Logic buffers

• Inherently temperature stable

• Pulse amplifiers

• Reliable, low cost plastic package

• DC motor controllers

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC DIAGRAM

(T A = 25° C unless otherwise noted)
Drain-source Voltage
VN40AF ..................................... 40V
VN67AF ..................................... 60V
VN89AF ..................................... 80V
Drain-gate Voltage
VN40AF ..................................... 40V
VN67AF ..................................... 60V
VN89AF ..................................... 80V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current ............ 2.0mA
Peak-gate Forward Current .................. 100mA
Peak-gate Reverse Current .................. 100mA
Gate-source Forward (Zener) Voltage .......... +15V
Gate-source Reverse Voltage ................ -0.3V
Thermal Resistance, Junction to Case ..... . 10.4°C/W
Continuous Device Dissipation at (or below)
25°C Case Temperature .................... " 12W
Linear Derating Factor .................... 96mW/oC
Operating Junction
Temperature Range ............. -40'C to +150°C
Storage Temperature Range ....... -40'C to +150°C
Lead Temperature
(1/16 in. from case for 10 sec) ............. +300°C
Note 1. Tc c 25'C: controlled by typical
power dissipation.
Note 2. Pulse width

80~sec.

TO-202

DRAIN

~_~ee

note 3)

*
I
I

GATE

D, TAB
SOURCE

5000Z

rDS(on) and maximum

duty cycle 1.0°.0.

Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

D~O[l

VN40A~VN67A~VN89AF
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CHARACTERISTIC

S
T
A
T

BVoss

Drain-Source Breakdown

VGS('hl

Gate-Threshold Voltage

IGSS

Gate-Body Leakage

loss

Zero Gate Voltage
Drain Current

MIN
40
40
0.6

VOS{onl

ON-State Drain Current

Drain-Source Saturation

Forward Transconductance

Ciss

Input Capac ... ance

D
Y

C'SS

Reverse Transfer Capacitance

Co..

M td(on 1
I
t,
C
td(off)

1.0

Voltage

MIN

VN67AF
TYP MAX

eo
eo
1.2
0.01

0.8
10
100
10

Common-Source Output
Capacitance
Turn-ON Delay Time

Rise Time
Turn-OFF Delay Time
Fall Time

100
2
0.3
1.0
1.0
2.2
250

2
2
2
2

5.0

VN89AF
TYP MAX

1.2
0.01

0.8
10
100

1.2
0.01

10
100

1.0
2.0

MIN

80
80

100

C
1010ni

VN40AF
TYP MAX

100
2
0.3
1.0
1.0
2.2

100

1.0

1.7
3.5

250

10
100
10

100
2
0.4
1.4
1.3
2.2
250

1.9
4.5

50
10

5
5
5
5

2
2
2
2

Note 1. Pulse test - 80"s pulse, 1% duly cycle.
Note 2. Sample test.

5
5
5

2
2
2
2

UNIT

VGS

=0, Vos = 25V, f =1.0 MHz
(Note 2)

TEST CONDITIONS

VGS =0, 10 = lC!!<.A ,.
V
VGS =0, 10 =2.5mA
VOS =VGS, 10 =lmA
VGS = 10V, VOS =0
VGS = 10V, VOS =0, TA = 125°C (Note 2)
p.A
VOS =Max. Rating, VGS =0
Vos =0.8 Max. Rating, VGS 0, TA -125°C
I (Note 2)
nA
VOS - 25V, VGS =0
A
Vos =25V, VGS - 10V
VGS =5V, 10 =O.IA
VGS =5V, 10 =0.3A
V
(Note 1)
VGS = 10V, 10 =O.5A
VGS = 10V, 10 = 1.0A
mmho VOS - 24V, 10 =0.5A, f - 1KHz

VN46AF Series
n-Channel Enhancement-mode
Vertical Power MOSFET
FEATURES

APPLICATIONS

• High speed, high current switching

• Switching power supplies

• Current sharing capability when paralleled

• DC to DC inverters

• Directly Interface to CMOS, DTL, TTL logic

• CMOS and TTL to high current interface

• Simple DC biasing
• Extended safe operating area

• Line drivers

• Inherently temperature stable

• Pulse amplifiers

• Logic buffers

ABSOLUTE MAXIMUM RATINGS
(TA

SCHEMATIC DIAGRAM

= 25° C unless otherwise noted)

(TO-202)

DRAIN

Drain-source Voltage
VN46AF ................................ 40V
VN66AF ................................ 60V
VN88AF ................................ 80V
Drain-gate Voltage
VN46AF ................................ 40V
VN66AF ................................ 60V
VN88AF ................................ 80V
Continuous Drain Current (see note 1) ......... 1.2A
Peak Drain Current (see note 2) ............... 3.0A
Continuous Forward Gate Current .......... 2.0mA
Peak-gate Forward Current ................ 100mA
Peak-gate Reverse Current ................ 100mA
Gate-source Forward (Zener) Voltage ........ + 15V
Gate-source Reverse (Zener) Voltage ........ -0.3V
Thermal Resistance, Junction to Case .... 10.4 ·CIW
Continuous Device Dissipation at (or below)
25·C Case Temperature ................... 12W
Linear Derating Factor ................. 96mW/·C
Operating Junction
Temperature Range .......... -40·C to + 150·C
Storage Temperature Range ..... -40·C to + 150·C
Lead Temperature
(1/16 in. from case for 10 sec) ........... +300·C

(see note 3)
GATE

SOURCE

D. TAB

5000Z

Nole 1. Tc : 25°C; controlled by typical 'DS(on) and maximum
power dissipation.
Nole 2. Pulse width 80I'5ec. duty cycle 1.0%.
Note 3. The Drain-source diode is an integral part of the MOSFET
structure.

U~U[b

VN46A~VN66A~VN88AF
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CHARACTERISTIC

BVoss

DrainwSource Breakdown

VGS('h)

Gate-Threshold Voltage

IGSS

Gate-Body Leakage

MIN
40
40
0.8

VN46AF
TYP MAX

loss

1.7
0.01

Zero Gate Voltage

lo(on)

VOS(on)

D
A

Ciss

Input Capacitance
Reverse Transfer Capacitance
Common-Source Output
Caoacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time

M Id(on)
I

Drain-Source Saturation

Forward Transconductance

Co..
tr
td off)
tf

1.0

Voltage

gf.

Y Crss

ON-State Drain Current

0.8
10
100
10

1.7
0.01

100

Drain Current

VN66AF
TYP MAX

60
60

S
T
A
T

MIN

150

Nole 1. Pulse test - 80l's pulse, 1% duty cycle.

100
2
0.3
1.0
1.0
2.2
250

MIN
80
80
0.8

10
100
10

VN88AF
TYP MAX

1.0

2
0.3
1.0
1.0
2.2

1.7
0.01

1.5
3.0
150

1.5
3.0

250

10
100
10
100

1.0

150

100
2
0.4
1.4
1.3
2.2
250

1.7
4.0

50
10

'50
10

50
10

2
2
2

5
5

2
2

5
5

Nole 2. Sample test.

TEST CONDITIONS

VGS = 0, 10 = 10MA
VGS - 0, 10 = 2.5mA
Vos = VGS, 10 = lmA
Vas - 10V, Vos - 0
VGS = 10V, Vos - 0; TA - 125°C (Note 2)
Vos - Max. Rating, VGS = 0
I'A
Vos =0.8 Max. Rating, VGS =0, TA =125°C
(Note 2)
nA
Vos - 25V VGS =0
A
Vos - ~V, VGS = 10V
Vas - 5V, 10 = O.lA
Vas = 5V, 10 = 0.3A
V
(Note 1)
VGS = 10V, 10 =0.5A
VGS = 10V, 10 = 1.0A
mmho Vos = 24V, 10 - 0.5A.f - 1KHz
V

100
100

UNIT

2
2
2
2

5
5
5

VGS = 0, Vos
f = 1.0MHz

= 25V,
(Nole2)

VQ1000 CJ
Quad n-Channel
Enhancement-mode
Vertical Power MOSFET

D~D[b

APPLICATIONS
• LED and lamp drivers
• TTL and CMOS to high current interface
• High speed switches
• Line drivers
• Relay drivers
• Transformer drivers

FEATURES
• Directly drives inductive loads
• High speed, high peak current switching
• Inherent current sharing capability when paralleled
• Directly interfaces to CMOS, DTL, TTL logic
• Simple, straight-forward DC biasing
• Inherent protection from thermal runaway

ABSOLUTE MAXIMUM RATINGS
25°C unless otherwise noted)
(TA

PIN CONFIGURATION

14 Pin Plastic Dip

Drain-Source Voltage ....................... 60V
Drain-Gate Voltage ......................... 60V
Continuous Drain Current (per device) ......... 0.3A
Peak Drain Current (per device) ............... 1.0A
Gate-Source Forward Voltage ............ " + 15V
Gate-Source Reverse Voltage ................ 0.3V
Reverse Diode Continuous Current ........... 0.3A
Reverse Diode Peak Current ................. 1.0A
Temperature
(Operating and Storage) ....... -40'C to +150'C
Lead Temperature (Soldering, 10 sec) ...... +300'C

MIN

BVDSS

Drain·Source Breakdown

VGS(lh)

Gale Threshold Voltage

0.8

IGSS

Gale-Body Leakage

loss

Zero Gale Voltage
Drain r.llrrAn'

TYP

I
L,U
Dl

l-1,

I
l,!JL,UWUJWllJ
Fll

100
100

nA
~A

TEST CONDITIONS

,
I

= OV, ID = 100,.A
= VGS = VOS, 10 = 1 rnA
VGS = 10, VOS = 0
VOS = 40V, VGS = 0
VGS

Vos
A
VOS
VGS

1.5

= 25V, VGS = 5V
= 25V, VGS = 10V
= 5V, 10 = 0.2OA

(Nole 1)

V
mmho

VOS

= 10V, 10 = 0.3A
= 15V, 10 = 0.5A

Vos

= 25, I = 1 MHz

1.65
100

Ciss

Inpul Capacilance

Coss
C ros

Oulpul Capacilance

Feedback Capacllance

Ion

Turn·ON Time

loll

Turn·OFF Time

VGS

(Nole 1)

= 0.3A, RL = 2311
Rs = 5011
IF = IR = lA

230
Reverse Diode

= O.lA
(Nole 2)

I"
165

IF
I"

NOTES:

VGS

VOS(on) Drain·Source ON Voltage

Reverse Recovery Time

TOP VIEW

UNIT

ON·Slale Drain Currenl

Forward Transconduclance

MAX

0.5

g,.

6300

0.20
10(on)

Q~J I

I ~~4

ELECTRICAL CHARACTERISTICS
CHARACTERISTIC

1171 r,ilr;il 1111 ~r.ir.i

1. Pulse lesl - 80~s pulse, 1 % duly cycle.
2. Sample lest.

= IR = 0.3A
= 0.03A

D~Dll

Power MOS Geometries

-j9mill-

--Ia

SOURCElf

milj.-

souRcEllmii
\amllj
GATE

62 mll-

5200
6000

5000

6100

-I
SOURCE

lImn

6200

6300
36

mil

5000 Family Typical Performance Curves
(25°C unless otherwise stated)
DRAIN-SOURCE ON
RESISTANCE vs
GATE-SOURCE VOLTAGE

~
:J:

b400
:l
e

illz

~ 100

«
;;:

is 300
~

100
10
VGS GATE-SOURCE VOL TAGE-(VOL TS)

~ 100

0.2

0.4

0.6

0.8

1.0

1.2

IO(ON) ON DRAIN CURRENT - (AMPS)

7--

o 1/
o

i--

~ 200

....

c±=
:

f-- !i-

~ 200

«
b 400

....

:;;:
o

-I-

300

VOS= 10V
PULSE TEST-200" Sec.,
1% DUTY CYCLE

500

ji!

I
W

Vos = 0.1V

u
a:

600

VOS= lbv
PULSE TEST-200~Sec.,
~ 500 1% DUTY CYCLE

in 100
w
a:

.sE 600

TRANSCONDUCTANCE vs
GATE-SOURCE VOLTAGE

S
J:

w 500

TRANSCONDUCTANCEvs
DRAIN CURRENT

6.0
.0 10.0
0
2.0
4.0
VGS GATE-SOURCE VOLTAGE - (VOLTS)

BREAKDOWN
VOLTAGE VARIATION
WITH TEMPERATURE

SWITCHING TIME TEST WAVEFORMS

~"'''' .'' ' ::::1

1.2

J~'p

e
w

90%

::;

50%

INPUT

OUTPUT

10%

J:~J

0.1

IVN5000ANO ""-

~ VN5001AND
VNsOOoANE

0.8~-+--+-~+---+---I

II:

2~ O.4F=+~.!dl!-*-+----J

== ~:=~~:~
IVl'jsqo,ll\l'j~

~ OL-~_~_~~~~

0.01
100
1.0
Vos DRAIN - SOURCE VOLTAGE IVOLTSI

120
180
T-TEMPERATURE-lOCI

200

O~O[l

5200 Family lYpical Performance Curves
(25°C unless otherwise stated)
DRAIN-SOURCE ON
RESISTANCE vs
GATE-SOURCE VOLTAGE
10

TRANSCONDUCTANCE vs
DRAIN CURRENT

S 24
1
.

~ 2.0

:,...-

go 1.6
z
o

TRANSCONDUCTANCEvs
GATE-SOURCE VOLTAGE

~ 2.0

o
z

0.8

10 • 5.0A. PULSE TEST
80 psec - 1% DUTY CYCLE

0.01

100

V GS - GATE·SOURCE VOLTAGE (VOLTS)

0.4

s:I
.;;

Vos= 10V
PULSE TEST

I
I

200Msec

Vos= 10V
PULSE TEST

I-

~ 0.4

ON DRAIN CURRENT (AMPS)

'O(on) -

J
IL

a: 0.8

1% DUTY CYCLE

~LLl

8 1.2
'"~

'(3

.......-=

10%~

I-'

1.1

0.9

i.-'"

0.8
-40 -20 0 20 40 60 80100120 140
TEMPERATURE - ·C

SWITCHING TIME TEST CIRCUIT
+10V
+24V

COAXIAL CABLE
Zo = 12.50

10KO
KI

-e===~H----q.....L..

011

3 msec

15V

H
n

OV.J

r
L.J

2200

MERCURY REED
RELAY

OSCILLOSCOPE
TEKTRONIX 7904
OR EQUIVALENT

5200 Family Typical Performance Curves
(25°C unless otherwise stated)
OUTPUT CHARACTERISTICS
_

9.0

PULSE TEST 80llSec, 1% DUTY CYCLE

VGS - 8V

I-

71V

6.0

3.0

1.5

]
_0

;;:

7.5

fi!

;;:

li! ~

]
~

6
8
10
12
VGS - GATE·SOURCE VOLTAGE (VOLTS)

~
~
o~
I

,\
\
\.\

1..c

.sw

fi!~

+40

+80 +120 +160

100

Ves ~24V
f= 1kHz

~ PULSE TEST
SOpsec
10 1::::1% DUTY CYCLE

::l
Q

~"'-

r--.

o
o

OUTPUT CONDUCTANCE
vs DRAIN CURRENT

225
150

2~V

VOS =
VGS =0
f= 1 MHz

0.4
-80-40

T - TEMPERATURE (OC)

CAPACITANCE vs
DRAIN-SOURCE VOLTAGE
450

'P.'_
V
- 10V

]

V GS = 5V.

;;:- 0.8

1.5

~ 300

1.2

~g;

3.0

l10~ ~
~ ~S=5V

20
Ow

1.6

:::>:;;

"i"

V GS

1
1/

4.5

_ 375

....

2.0

1il

1% DUTY CYCL

~ 6.0

~ /'

80llSec

..F

NORMALIZED DRAINSOURCE ON RESISTANCE
vs TEMPERATURE

I I

PULSE TEST

'{/

o 1.0 2.0 3.0 4.0 5.0 6.0
V DS - DRAIN·SOURCE VOLTAGE (VOLTS)

Ves = 10V

I-

6~
VI"

in 9.0

1.5

VGS=
81
V

.....

3.0

]

/- r/

TRANSFER CHARACTERISTIC

4.5

..... 1---'

-I- r- 7V

o 10 20 30 40 50 60
VDS - DRAIN·SOURCE VOLTAGE (VOLTS)

a: 6.0
a:
::l
o

7.5

2
w

51V

PULSE TEST 80llSec, 1% DUTY CYCL~

I-

T
T

4.5

;;:

9.0

If
:;;
S

I
Jv

::l

:;;

S 7.5 1

SATURATION CHARACTERISTICS

r- r- 1-<:...,_

I-

CJ-

I
.} 0.1
0.1

VDS - DRAIN·SOURCE VOLTAGE (VOLTS)

10(on) - ON DRAIN CURRENT (AMPS)

U~UIL

5200 Family lYpical Performance Curves
(25°C unless otherwise stated)

THERMAL RESPONSE
I

I-- I- "'0-0.6
I-

I-- 1-_lol.IU

r-- r)--

~t::

t:?

101JJ.\

~ JJl

I--'

JLJ
1-',_1 I
- t2--+-

rnrmroi"1"

0.0I
0.01

0.1

1000

100

t1 - TIME (msec)

POWER DISSIPATION vs CASE
OR AMBIENT TEMPERATURE

DC SAFE OPERATING REGION
Tc = 25°C

15.0

S
lOY

II/

'-::

12.5
~
~ 10.0 f---

III

~
IVN5200T

~~~~1~
O.

7.5

5.0

2.5

I~~;'~;TNI

1.0

"'R:,1TE

.p
10

100
Vos - DRAIN·SOURCE VOLTAGE (VOLTSI

HEA~ SINK

,aDeM

~E AIR 104DCIW

-r-- .'\.

+40
+80 +120 +160 +200
T - TEMPERATURE ('C)

U~Ull

6000 Family Typical Performance Curves
(25°C unless otherwise stated)

TRANSFER CHARACTERISTICS

OUTPUT CHARACTERISTICS
'0

VGS

-toy

;:, /
fl3

II:
LU

::;;.

...:
I

6
5

!VGS '=

Vos '" 200V

rJ)

II:

VGS'"
6V

Ivoso

VOS -

300

400

0.2

500

.... ~

200

'00

...:
I

a.
::;;

V~s -

VOLTS

TRANSCONDUCTANCE CHARACTERISTIC

VD~ o2oclv

Vos "200V

..-

I ..,../
rJ)

::;;
LU

k-" ~

.c:

'0
10 -

-1

V~s -

AMPS

OUTPUT CONDUCTANCE

DRAIN-SOURCE LEAKAGE CURRENT

,ooo~------~-------,.------,

'000

V~s <3JoV
VGS =0

'00

.c:

I.,

-40

-20

/v
20

TEMPERATURE -

NOTE: V~s = VGS - VGS('h)

E=.

10 -

VOLTS

100

·C

120

140

6000 Family Typical Performance Curves D~DIl
(25°C unless otherwise stated)
BODY-DRAIN DIODE FORWARD
VOLTAGE CHARACTERISTIC

CAPACITANCE vs. DRAIN-SOURCE VOLTAGE

i
U.

1000

Cg,

()

«
l-

:::;;

100

C3
«
no

.2'

()

en
w
a:
w
no

VGS "'0

Cd,

..... /

1
.1

VDS -

1000

100

Cgd

VSD -

VOLTS

1.0

1.1

1.2

VOLTS

DRAIN-SOURCE BREAKDOWN VOLTAGE
VARIATION WITH TEMPERATURE

THRESHOLD VOLTAGE VS. TEMPERATURE
10 =lmA

I.'
0

:::;

1.2

«
:::;;
a:
0

//
/ ,/

'L
/

/212 pF

-2
0

1630 lpF

I.V /

-}6

37SV

/ Ii

II
-20

140

vJry;
sov ~v7!o'

/
-40

120

·C

GATE DYNAMIC CHARACTERISTICS

GATE LEAKAGE CURRENT
1000

100

TEMPERATURE -

100

120

140

QG -

·C

NOTE: V~s = Vos - VOS(th)

nano COULOMBS

6000 Family Typical Performance Curves D~DIL
(25°C unless otherwise stated)
SAFE OPERATING AREA

III
W

a:
w

0..

::;

«
I

" " ' ...
,, , ",, ...l'O/JS

'i'm,

" ' , ' , II
, , 'I1'0m,

.1
10

'.I'OOjJS

',',

DC
20

30 40 50

'100ms

100

Vos -

1000

VOLTS

POWER DISSIPATION VI. TEMPERATURE DERATING

TRANSIENT THERMAL IMPEDANCE

!
6

NORMALIZED FOR ROJc"'3.5°CIW

::i

«
::;
a:

0
~

N'"

1.0

-:/.::;;i ~

0-.75
0.8

00."
0.2

0.1

0-.5
0.6

~
3:'
I

0-1.0

0..

.z;.. --'l

III
30

I'\.

'\.

"- i\.

/0.0

1.0

100

tp -

NOTE: V~s = VGS -

1000

VGS{th)

SWITCHING TIME TEST CIRCUIT
+200V
30V

20011

COAXIAL CABLE

10Kn

= 12.Sn

3 msee

lSV

OV.J

OSCILLOSCOPE
TEKTRONIX 7904
OR EaUIVALENT

LJ
KI
MERCURY REEO
RELAY

120

160

6000 Family Typical Performance Curves D~DIb
(25°C unless otherwise stated)
ON RESISTANCE VI.
JUNCTION TEMPERATURE

LARGE SIGNAL TRANSFER CHARACTERISTICS
2.0

10'" lA

1.8

VOS""

13
II:
W

D..

I.'

c(
~

1.2

1.0

II:

Vos=
20V

Vos=
SV

VOS'"

~ I-'"

Vos'"
10V

V
1

1.6

SOV

I.......

Vas -

-60

-20

100

120

140

ON RESISTANCE VS. VGs·
AS A FUNCTION OF 10
100

-40

TJ -'C

'o·1 1A

_40

+12SO

j...--+2S·C

c::

.,/

VOLTS

ON RESISTANCE VS. VGs·
AS A FUNCTION OF TEMPERATURE

~.VGS=4V

2V
4

100

VGs",10~.

r-....

~ .......... ,...,
1
-2

=VGS -

'T, •

-kn
14

\ \... k

'" -3A

r"'=SA

l,.+L

Vas -

NOTE: Vas

TJ =+l25"C

'" -O.SA-"
16

1
-2

1 I
2

'" -IA....I

I
6

Vas -

VOLTS

VGS(th)

VOLTS

PACKAGE OUTLINES All dimensions given in inches and (millimeters).

0.350-0.370
---(8.890-9.398)1

0.875
(22.225)

0.450-0.250

0'240~lq
I

1~1~6.35)

0.135 MAX
(3.429)

(6.096-8.604)

-.-

rl ~I~
t

~ ~ ~ II~

0.500
(12.70)

....

...

0.190-0.210
(4.826-5.334)

n- ,-tt- /

0.225-0.205

(5.715-5.207)

0.016-0.019 . .
(0.406 0.483)

MIN

I
I

SEATING

1.. PLANE

0.045

•!

0.875-0.855
(17.145-16.637)

0.440···0.420
(11.178-10.888)

0.043-0.038+ 0.312 MIN
----rt(1.092
0.965) (7.925)
1.197-1.177
t
(30.404-29.8.6)

SEATING
PLANE

0.315-0.335
,. (8.001 8.509)·

(4.089-3.835)

0.525 R MAX
(13.335)

BOTTOM VIEW

TO·3

TO·39

0.209-0.219
- (5.309-5.583)

0.178-0.191
(4.521-4.851)

SEATING PLANED_I

0.142-0.159
(3.807,-4.039)

0.820
(15.748)

III

0.470-0.500

TITJ
000

0.050 MAX
(1.270)
'''1.

(~:~:)
MAX

0.018-0.019 .... __
(0.408 0.483)

0.250-0.340

MAX

(11.938-~2.700)F (6.350
'
~r----'

0.050-0.~ I _::
(1.270-1.905) 0.028-0.034

0.500
(12.70)

8.836)

~ ___t_
..

x==

0.380 MIN

.. ~

(0.711-0.884)
0.958-0.982 _.::••1 - -_ _•
(24.333-24.435)

(9.144)

0.570-0.590
(14.478-14.988)
0.145
(3.883)
0.142-0.152
{3.807-3.881)

0.350 R
(8.890)

TO·52

TO·66

PACKAGE OUTLINES All dimensions given in inches and (millimeters).

0.240-0.260
(6.096-8.604)

J -1
i

0.480-0.520
(12.192-13.208)
1.21
(30.734)
REF - - -...'---...J.....,
0.285-0.315
~;;--T.;;'"
(7.237-8.001)

0.025
(0.635)
RAD

~(::~::::)

0.030-0.OS5
(0.762 1.397)

L,7'

0.230-0.270
(5.842-8.859)

2 PLACES

0.060
(1.524)
REF

0.405-0.425
(10.287-10.795)

t
I
I

---!.J11
_I 1_

~[I
I
L

0.095-0.105
0.170-0.190
(2.413 2.887)
~.095-0.1OS-(4.318 4.828)
0.028
I
(2.413-2.887) _ _ _ 0.019-0.028
(0.880) REF NOTE 2 _ /4(0.493-0.660)

(~:~::~:!~ -

0.020-0.035
(0.508-0.889)
0.090-0.110
(2.286 2.794)'"

TO·202

rI -.

0.205-0.195
1..<5.21-4.95)

LEADS FIT INTO
0.018-0.019
0.406 0.483)
DIA HOLE (TYP)

I:::::: :9

~105-0.095
~ (2.67-2.41)

0.185-0.175
(4.70-4.45)
•

I 0.175-0.185

-,,~~='"-~1

-t
000

1(4.445-4.899)

0.584

-r-I

(1.143 1.397)

(4.45

.235 (5.969)
.215 (5.4911
.160 MAX

~ L~l~Jl

0.045-0.055

r
=:~~~
I-t0.135
(3.43)'
•
MIN
0.175-0.205

'310~l

.280 (7.112)

'''L~

(15.088)

0.045-0.055
(0.143 1.397) -I

0.080-0.115
(2.032 2.921)-

TO·220

0.270-0.280 . :
(6.86 8.80).
I

0.D12-0.025
(0.305-0.635)

0.003-0.013
(0.076-0.330) R

1'P,L

.110~

.060~

.023~

.090 (2.286)

.045 (1.143)

.015 (.3810)

:J L

.015(0
(0.381)
.160 ~
008
2032)
.100 (2.5401'
.

5.21)

PO (14·PIN PLASTIC)

TO·237
48

.400 (10.160)
.330 (8.3821

D~DIb

A033
The Power MOSFET,
A Breakthrough in
Power Device Technology
by Rudy Severns
essentially two back-to-back PN diodes and no conduction
occurs. If, however, the gate is made positive with respect to
the source, the electrostatic field draws electrons near the
surface of the P region. This inverts that region to N material,
and a channel is formed, allowing conduction between
source and drain. Note that the MOSFET is a majority carrier
device which acts like a voltage controlled resistor during
conduction. The result is an extremely fast switch with no
storage time effects. There are, however, a number of
drawbacks for high power use which, for practical purposes,
eliminate this structure from consideration for high power
use:

Recent advances in the technology offabricating MOSFET's
have enabled manufacturers to break free of the power limitations of the early devices. While the power MOSFET is a
relative newcomer to the power switch field, it promises
exciting performance advantages over the more conventional bipolar transistor. By providing much higher switching
speeds (a few nanoseconds is typical), high input impedance
with low drive requirements, simplified multi-device operation, and greatly improved safe operating area for power
switching applications, the power MOSFET will replace the
bipolar transistor in many applications, and provide new
circuit opportunities that do not exist with bipolar technologies. Several different types of power MOSFET's are
already available, and the immediate future promises many
more devices with steadily increasing performance.

1. The length of the channel is controlled by the mask
spacing of the N+ regions. Due to the limits of accuracy of
photomask technology, it is necessary to have relatively
wide spacing. This produces long channel lengths which
increase the ON resistance for a given area of silicon.
2. The source, gate and drain conductors are all on the same
surface. This metall ization takes up a major portion of the
die area, further increasing the ON resistance.
3. This structure has large inherent capacitances. for its
current capability, especially gate to drain. This reduces
the gain bandwidth and increases the drive power in
repetitive pulse applications.

This applications note is intended to provide the design
engineer with a basic understanding of how power
MOSFET's work, the structures presently in use, the
electrical characteristics of the devices and some guidance
on application.

STRUCTURES
At the present time, there are a host of different and often
confusing names for power FET devices, such as VMOS,
VFET, HEXFET®, TMOS, DMOS, ZMOS, etc. In actuality
there are only three basic structures: vertical junction FET's,
V-groove MOSFET's and vertical DMOS FET's.

VMOS
Most of the deficiencies in the planar MOSFET's can be
overcome by going to a structure that allows the current to
flow vertically, and in which the channel length is controlled
by diffusion processes rather than mask spacing. The VMOS
structure shown in Figure 2a is a particularly good solution.
A VMOS device fabrication process starts with an N+ substrate with an N-epi layer. A P region is diffused in and then an
N+ layer is diffused within the P region. Up to this point the
process is very similar to that for a double diffused NPN
transistor (Figure 2b), but, rather than applying the base and
emitter metal, a V groove is anisotropically etched in the
surface of the device, a silicon oxide insulating layer is
grown, and finally, source and gate metal is deposited. Note
that the source metal overlaps the P and N+ regions so that
the base and emitter of the NPN transistor are connected
together.

Planar MOSFET
Figure 1 is a cross section of a conventional planar Nchannel enhancement mode MOSFET. Fabrication of this
device begins with a P substrate into which N+ regions are
diffused. Si02 is then grown and etched for the aluminum
which is deposited to form the source, gate and drain
connections. If no bias is applied to the gate, this device is

SOURCE

GATE

DRAIN

By applying a positive potential between the gate and
source, the P region close to the gate can be electrostatically
inverted to N type material, and a conducting channel
formed. Thus the source and gate connections are on the
upper surface while the drain is on the bottom, and current
flow is essentially vertical. In addition, the channel lengths
are controlled by the diffusion processes and can be made
quite short. This structure allows very efficient utilization of
the silicon, and high power MOSFET's can be fabricated.

Figure 1. The Cross Section of a Conventional MOSFET

O~OIL

A033
SOURCE

GATE

POL YCRYSTALLINE
SILICON/PHOSPHORUS

SOURCE

Si02

N+ SUBSTRATE

N+SUBSTRATE

DRAIN

Figure 3. Flat-Bottomed Groove Silicon Gate VMOS

Figure 2A. Conventional Metal Gate VMOS Structure
With Sharp "V" Groove

BASE

doped with phosphorus. Phosphorus doped poly~silicon is
an effective ion migration barrier but it is not a particularly
good conductor, having a resistance about 3000 times that of
aluminum. In a large device, this could lead to a slow turn-on
time due to the gate resistance. To alleviate this problem, a
layer of aluminum is applied over the silicon-gate to provide
high conductivity. Another benefit of the silicon-gate
process is increased manufacturing yield which lowers the
device cost. This is the standard Intersil process for VMOS
devices.

EMITTER

N+ SUBSTRATE

Vertical DMOS
COLLECTOR

While the modified VMOS process is very effective for voltages under 150V, high field problems still exist, and the
groove spacing requirements increase the die area. A vertical DMOS (double-diffused MOS) process has been developed to alleviate these problems. This structure is shown in
Figure 4. The process begins as before (for an N-channel
device) with an N- epi layer grown on an N+ substrate.
Regions of P- are then diffused, and inside these, regions of

Figure 28. Typical Double Diffused NPN Transistor

However, this basic structure has some drawbacks. The
sharp bottom of the V groove produces a strong field concentration between the 'gate and drain, and there is also a tendency for the gate oxide layer to thin down around the tip of
the V. The result is limited high voltage capability dueto gate
oxide breakdown even though the gate does not see the full
drain-source voltage. The use of an aluminum gate can
cause long term reliability problems due to ion migration
(principally sodium) through the gate oxide which leads to
variations in the device threshold voltage. A channel is
formed on each side of the V groove, and if the groove does
not penetrate well past the P region into the epi layer, it is
possible to experience excessive current densities which
may cause current injected avalanche breakdown in high
power devices.

GATE

N+ SUBSTRATE

UMOS
Most of the VMOS problems can be relieved by using a flat
bottomed groove with a combined silicon and aluminum
gate structure as shown in Figure 3. The process is very
similar to VMOS except that the etching is halted while the
bottom of the groove is relatively wide. A layer of oxide is
grown and overlaid with a layer of polycrystalline silicon

CURRENT FLOW
DRAIN
SOURCE

Figure 4. Vertical DMOS Structure

U~UIL

A033

N+. A silicon-gate is imbedded in Si02 and the source and
gate metallization are then added to complete the device.
The current flow is at first vertical and then horizontal, with
the drain on the N+ substrate.

The SONY Corporation manufactures a device called a
VFET,1 2 1which bears no relationship to the VMOS device,
and is in fact, a vertical depletion mode junction FET. The
structure, shown in Figure 6, produces a device with asquare
law transfer characteristic, while the output characteristic
(Figure 7) is very much like a low IJ. triode. The disadvantages
are relatively low stage gain, substantial gate current if the
gate is driven positive, and the relatively high gate resistance
and input capacitance which tend to reduce the gain bandwidth product.

This basic process has a number of different names, OMOS,
TMOS, ZMOS, HEXFET®, etc. The processes are basically
the same; the primary differences being in the geometry of
the P and N regions and the interconnections. The HEXFET®,
for example, uses hexagonal P regions, which allow a very
low ON resistance by maximizing the channel perimeter.
Unfortunately, as presently implemented, the silicon-gate
. structure has a very high series resistance which increases
the switching time quite significantly. Intersil uses an alternate geometry that retains the low ON resistance but
reduces the gate resistance.

SOURCE

GATE

Other Geometries
A variety of other geometries are in use to produce power
MOSFET's and junction FET's.
Figure 5 shows a MOSFET structure developed by Hitachi. 11 I
The gate structure overlays the checkerboard of Nand P
regions to form the channels, and the N regions connect to
the N+ substrate so that the drain is on the back side of the
die. To date. devices using this structure display a rather
restricted Gain Bandwidth product of 0.6 to 1.5 MHz and a
relatively high rOS(on) for a given die area. The primary
application for these devices is audio amplifiers.

DRAIN

Figure 6. VFET Structure

I I
I II 1/

GATE
SOURCE

I
l

•I I

)

Sl02

I
10

N
N

I / I

IV.

I /

/11

P epl

rJ / J

N+ SUBSTRATE

V
V
./

CURRENT FLOW

" V-

~
i;

./
",

i.,...oo' io""'"

VDS

DRAIN

Figure 7. VFET Output Charactistics

Figure SA.

BASIC LIMITATIONS

0B10
888

rOS(on) Versus Breakdown Voltage
As the breakdown voltage of a MOSFET (or a bipolar) is
increased, the ON resistance, for a given die area and
process, will increase exponentially by a factor of 2.3 to 2.7.
[I.e., rOS(on) 01 k (BVOS)2.3-2.'j For example, if the breakdown voltage of a 1n, 100V device is increased to 200V, the
die area must increase by five times to maintain the same ON
resistance. The reason for this is twofold: first, the resistivity
of the epi layer must be increased to raise the avalanche
breakdown voltage. Second, the thickness of the epi layer
must be increased to assure that the depletion region
remains totally within the epi layer. Typically, in a 400V
device, the epi resistivity will be 1500 to 2000 times greater
than the N+ substrate, so that at high voltages the ON resistance is dominated by the epi layer. The net result is that in
either a MOSFET or a bipolar device, when the breakdown

,,~

Q~P
GATE

GATE

Figure 58.

A033
\

voltage (for a given die areal is increased, the power
handling capability is reduced. Conversely, if the same
power capability is needed, then a larger die area is required.

9.0

Die Area Versus Yield/Cost

iii

The ON resistance of a power FET is proportional to the die
area. If a large die area is used to reduce the ON resistance,
the number of dice per wafer will decrease; additional dice
are lost due to inherent wafer defects and the increased
scrap zone around the wafer center and periphery. The yield
(YI can be represented by a variety of equations, all of them
exponentially decreasing in some manner. A typical equation is:

:E
~

II.

LINEAR SATURATION
REGION IREGION

...

1% DUTY CYCLE
VGS-8V

7.S

I-

6O~sec,

PULSE TEST

1/
I

6.0

II:
II:

:l
(J

z
:;;:

4.5

3.0

.!?

Y= k (n)(1-eAD )2

6V i--

II:
C

1.5

'I
~

where A is the die area, D is the defect density, n is the
number of process steps and k is a factor that varies inversely
with n, usually exponentially. The result is a rapid decrease
in yield as the die area is increased. For small devices «.050"
x .050") the yield is usually very high and the die cost low, but
as the die dimensions begin to exceed .100" x .100" the yield
drops and the cost per die increases rapidly. Many power
FET's are larger than those dimensions, so for example, a
one ohm 450 volt device may cost four to six times as much
as a 2.5 ohm device with the same breakdown rating.

0.0 0

3V
50

VDS - DRAIN SOURCE VOL TAGE (VOLTS)

Figure 8. Output Characteristics IVN5200

9.0

iii
II.

P-Channel Devices

The discussion so far, has dealt with N-channel devices,
however P-channel devices can just as easily be built simply
by interchanging the Nand P regions. In fact, some manufacturers use the same mask set to produce both Nand
P-channel devices by changing the starting material and the
process. There is, however, a very basic difference between
Nand P-channel devices. In the N-channel device, the
majority carriers are electrons but in the P-channel, the
majority carriers are holes. Holes have a mobility about half
that of electrons, so when the same mask set is used to
produce both Nand P-channel devices, the P-channel ON
resistance will be approximately twice that of the N-channel.
If, for complementary symmetry, equal rDS(on) is needed in
both devices, the P-channel will have to have abouttwice the
area. The larger structure will also have more capacitance,
so the devices will not be symmetrical in this respect, and in
large devices the cost of the P-channel device will be higher.

I-

PULSE TEST 6O~sec,
1% DUYCiCLj

rDS/

7.5

...
Z

rDS = j,V/j,1
6.0

:;;:

1I 'b"

j,1

4.5

II:
C

3.0

1.5

i-i--

~v
I

I5V

~
I

~ V'

I~ ~

I
0

F'(./ I

II:
II:

"
)

;~-

·~v- 2

VDS - DRAIN SOURCE VOLTAGE (VOLTS)

Figure 9. Output Characteristics IVN5200

signal drain-source resistance Irds(on) 1is the slope of the
transfer characteristic.

LINEAR CHARACTERISTICS

As VDS is increased, the carriers reach their maximum drift
velocity, and the device enters the saturation region where
the output impedance is high (the curves are relatively flat)
and the equal spacing between VGS curves indicates constant gm. In this region, the transfer function is linear.

Output Characteristics
The output characteristics for an IVN5200 are shown in Figures 8 and 9, where the drain current (lD) is shown as a
function of drain-source voltage (VDS I with the gate-source
voltage (VGS I as a parameter. Two distinct regions of operation are apparent, the linear region and the saturated region.
Be careful, these terms do not have the same meaning as
they do for bipolar devices. In fact, they are almost exactly
opposite! In the linear region (VDS "'0-5VI the voltage across
the channel is not sufficient for the carriers to reach their
maximum drift velocity. In this region, the FET operates as a
square law device; the static drain-source resistance
IrDSlonll is equal to VDS/ID at each point and the small

The output conductance (gos) as a function of drain current
and temperature is shown in Figure 10. Note that gos is relatively independent of temperature.

Transfer Characteristics
The transfer characteristic, taken in the saturation region, is
shown in Figure 11. The threshold voltage IVGS(th) 1 is
defined as the gate voltage atwhich the device begins to turn
on. The threshold voltage can be found by extending the

O~OlL'

A033
3.8

3.6

IJA ~ _40lc

3.4

.......
TA = 25°C~ .......
TA = sooC~
TA 100°C;;:

~si

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3.0

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~ 2.8
£ 2.6

3.2

.........

2.4

S/;;;~

2.2
2.0
1.8
1.6

1.4
-so

D V/
~
o. 1

0.1

9.0
7.5

~
~

VOS=1OV
PULSE TEST

BO"sec

DEVICE
HEATING

2.4
2.2

6.0

a:
a:

:;)
()

4.5

2.0

3.0

1.4

-...

.!a

1.5

100

~=-~OC
'If
~A- 2rC

TA - slJ°c
TA-1OO°C

I'
rJ

0.6

f/J

1.0

0.4

VGS - GATE SOURCE VOL TAGE (VOLTS)

0.2
0.0

Figure 11. Transfer Characteristic
linear portion of the transconductance curve (Figure 14) to
zero. As a practical matter however. because of the inconvenience of this measurement. manufacturers define VGSlth I as
the gate voltage at which some small current. usually 1 to 10
mAo depending on the device size. begins to flow. and this
value for VGSlthl is usually somewhat higher than the
extrapolated intercept. The threshold voltage is a function of
temperature; figure 12 shows this relationship for two different IVN5200·s. The temperature coefficient is 6 mV/oC.
Note that although the two devices have different threshold
voltages. the temperature coefficients are nearly identical.
This is typical within device types. and extremely helpful
when paralleling multiple devices. For switching applications. the variation of VGSI th. with temperature is not very
significant. but linear applications may require the bias point
to be stabilized by using a source resistance or other
negative feedback scheme.

5 6

8 9 10 11 12

10 (A)

Figure 13. IVN5200 gmvs. 10

The rOSIONI of a MOSFET is made up oftwo components.
the channel ON resistance and the bulk resistance of the
device. In low voltage devices «100VI rOSIONI is primarily
limited by the channel resistance. but in higher voltage devices. the minimum value of rOSIONI is dominated increasingly by the resistance of the epi layer. The channel resistance is controlled by the degree of gate enhancement. as
shown in Figure 15.lt can be seen that the ON resistance can
be reduced by increasing VGS to about 15 volts. However. a
point of diminishing returns. sets in. so that little is gained by
going above 15 volts. It is also important not to approach the

I
I
I
I

Ih '/

1.2
0.8

1/ /.. ~I"'"
/[& v J..-'"

1.6

1.8

C
0
.l..
c

........ 1'-0.

The small signal forward transconductance (9fs) curves are
given in Figures 13 and 14. As shown in Figure 13. fora given
VOS the transconductance increases with lOS until a point is
reached where the transconductance is constant. This is
characteristic of short channel MaS devices.

1% DUTY CYCLE

25
TAIOC)

i"--

Figure 12. IVN5200 VGS rthl vs. TA

10 (A)

...

-25

.......

r---

Figure 10. IVN5200 90S vs. 10

'iii

;--.... ;--....

A033
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2.2

2.0

1.4

1.0

0.0

0.8
4

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a: 0.9

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10 11 12

-50

VV
.... ~ .......VGS=5V

1.0

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2 f3

1.1

;'-1

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0.6

1.2

!:i!

//i '/

0.8

0.2

~",

1.2

/
vGs=1ovl

-,
/. '/ /' H
TA-100°C
/'
!II I":

1.6

0.4

1.3

"'/I--'" ~=50IoC

1.8

2
E
'"

-40°C

TA =25°C

-25

+25

+50

+75

+100

vGS(V)

TA(°C)

Figure 14. IVN5200 9m vs. VGS
Figure 16. IVN5200 ROS(on) vs. TA

Input Characteristics
The MOSFET, like the bipolar, displays significant input,
output and transfer capacitances that vary with voltage. The
gate structure has capacitance to both the source (C gs ) and
the drain (Cgd)' The inherent NPN transistor in the structure
has a reverse biased PN junction, the base-collector junction, that adds capacitance between the drain and source
(Cds). These capacitances are shown in Figure 17. The data
sheet does not state these capacitances directly; rather the
data sheet gives Ciss, C rss and Coss, as shown in Figure 18.
Ciss is the parallel combination of Cgd and Cgs , Cos s is the
parallel combination of Cds and Cgd, and C rss is the same as
Cgd·

TA 100°C
TA
50°C
""""":TA= 25°C
-TA=-40°C

o
10

100

VGS (V)

Figure 15. IVN5200 ROS(on) vs. VGS
gate breakdown voltage in the quest for low rOS(ON). For
higher VGS(th) devices, the curve will be displaced to the
right but the shape remains essentially the same. Figure 16
shows the effect of temperature on rOS(ON) at different
values of VGS. Note that the temperature coefficient of
rOS(ON) is positive. This positive temperature coefficient is
a major reason for the improved safe operating area and ease
of device paralleling. The value of this coefficient varies
between +0.2 and +0.7%; this is caused by the competing
effects of the positive TC of the silicon versus the negative
TC of VGS(th). As shown by the curve for VGS = 5V, when
VGS is close to VGS(th), the threshold effects predominate,
and as the VGS is increased the TC begins to take on the
characteristics of the silicon. This example shows a low
voltage (80V) device; in high voltage devices, ros is dominated more by the bulk resistance and the TC is more nearly
linear, with typical values of +0.6 to +0.7%.

Figure 17.
As in any junction diode, the reverse biased capacitance
decreases as the voltage is increased, so that Cos s has a
much lower and nearly constant value above 10V than near
zero. Ciss and C rss are also reduced as VOS is increased.
Because of the insulated gate structure, the input current
(IGSS) is normally very small, on the order of a few pica
amperes at 25°C. This is made up of the leakage current
through the gate structure, surface leakage current between

A033
450

\
\

375

u::-

S: 300
w
225

150

~
I

\l\

A major advantage of power MOSFET's is the very fast
switching speeds of which they are capable. If one were able
to charge the gate capacitance instantaneously, the switching time would be essentially the time it takes for the carriers
to travel from the source to the drain. In present devices, this
is about 50 to 200 picoseconds. Actual production devices
can be switched in less than one nanosecond if a suitable
pulse source is used to drive the gate. This can be done with a
mercury wetted relay and a transmission line pulse source.
For switching times longer than 5 to 10 ns, the turn-on time is
limited primarily by the drive source resistance and the input
capacitance (Figure 20a). As the switching times are reduced, the effect of parasitic inductances in the package and
generator connections become important, (Figure 20b) so
that it is difficult to turn on a TO-3 case device in much less
than 2 - 3 ns.

VGS=O

U
Z

Switching Characteristics

C,,,,!_

.........

r- t- r-c

C ',-

VDS - DRAIN SOURCE VOLTAGE (VOLTS)

Figure 18, Capacitance vs. Drain-Source Voltage
Zg

CIN Ir>10ns
10000

1000

<
S:

100

til
til

CIN Ir<10ns

10
1/

./
Figure 20.
0.1

0.01
-50

-25

+25

+50

+75

The MOSFET switching times change very little with temperature, as opposed to bipolars. The idealized switching waveforms shown in Figure 22, presume the use of a specific
test circuit like that shown in Figure 21. The actual transition
times seen by the user may be greater or less than those
shown on the data sheet, depending on the drive available.
The delay at turn-on is due to the length of time it takes for
the gate voltage to rise to VGS(th). where the device begins
to conduct. In most switching applications, sufficient gate
drive will be supplied to obtain the minimum rOS(ON); this
corresponds to the area in Figure 15 where ros changes
relatively slowly with VGS. The result is a turn-off time delay
where VGS has to drop significantly before ros begins to rise.

+100

TA(OC)

Figure 19. IVN5200 IGSS vs. TA
the package terminals, etc. Like any leakage current, IGSS
will increase exponentially with temperature; a typical characteristic curve is shown in Figure 19.
Occasionally, especially when an aluminum gate structure is
used, the gate oxide can be contaminated with sodium ions.
This produces a net positive gate charge, even when the gate
and source are shorted, and results in a reduced threshold
voltage. Unfortunately this is an uncontrolled process, and
leads to random VGS(th) variations over life. Use of the
silicon gate structure greatly reduces the possibility of
sodium contamination.

The actual switching time test waveforms for a typical
IVN5200 switching 60V at 8A are shown in Figure 23. The
positive drain voltage spike at turn-on is due to the coupling
of the drive pulse to the output by e rss during the turn-on
delay time. A similar negative pulse can occur during the
turn-off delay time.

A033
HOV
+24V
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10K!!

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Zo = 12.511

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3msec

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r
L.J

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OSCILLOSCOPE
TEKTRONIX 7904
OR EQUIVALENT

KI
MERCURY REED
RELAY

Figure 21. Switching Time Test Circuit IVN5200

..--PULSE WIDTH-

90%
50"10

INPUT

OUTPUT

10%

J~i~-

1\
1

90%

10%

J-~tdl10%

VDS
10V/dlv

VD~ =~ov
RDL = 7Il

1
\

1
I

......
10%

o
t

= 5ns/d,v

Figure 23. IVN5200

Figure 22. Switching Time Test Waveforms

Input Capacitance
The actual gate input capacitance is highly non-linear, so
that switching time and drive power calculations based on
the average input capacity and the source resistance tend to
be rather inaccurate. A better approach is to look at the gate
charge as a function of VGS. If the gate is driven from a
current source (Figure 24), and the current integrated to give
the charge, the curves in Figure 25 are obtained. For simplicity, the curves for VOO = 60V are reproduced in Figure 26.

If the effective value of CIN in eacl1 of these regions is
calculated from the slope of VGS, then: CIN(1)= 260 pF,
CIN(2) = 2900 pF, and CIN(3) = 400 pF. CIN(1) and CIN(3)
correspond to Ciss in each region. The value of Ciss is
different in Regions 1 and 3 because the bias conditions
within the device are different in each region. In Region 2,
CIN(2) "'Ciss -AvCrss, where Av =/WOS/.1.VGS, AvC rss is
the Miller capacity.

If one looks at VGS as a function of charge, it is clear that
three distinct regions exist and the dynamic input capacitance has a different value in each region. Region 1 corresponds to VGS between zero and threshold, where the device
is essentially off. The linearity of the voltage rise indicates
that the capacitance is constant. In Region 2, the rate of rise
of VGS is sharply reduced, indicating a large increase in
capacitance. This corresponds to the region whereVos is
falling and the Miller capacity appears at the input. In Region
3, the slope of VGS is again increased, although not quite
equal to that of Region 1, and is relatively linear. This corresponds to the region where the device is on and VOS is no
longer changing, so that the Miller effect is absent.

The energy (W) required to turn the device ON is:
W = 1/2 (.1.VG) (.1.QG) watt-seconds
If the gate is driven from a resistive source, ON and OFF
repetitively, at a rate fo then the drive power required is:

Oriving an IVN5200 to a VGS of 10V with fo = 100 kHz, the
drive power required is 7.5 mW. This is a vast improvement
over a comparable bipolar device.

O~OIL

A033
Safe Operating Area

:Fl

To achieve satisfactory service life from any power semiconductor. the circuit designer must assure that the device is
operated within the voltage. current and thermal capabilities
inherent in the particular device. To assist the designer. the
manufacturer provides a table of maximum ratings. a safe
operating area curve (SaARI and a thermal impedance
curve.

-=- VDD

IVN5200

A typical absolute maximum ratings table is reproduced in
Table I. While the information in the table is useful. it is not
sufficient by itself for a power device. To adequately define
safe operating conditions it is necessary to use the SOAR
curve. like that reproduced in Figure 27. For a power
MOSFET. the SOAR curvewill have three boundary regions.
Region 1 is defined by the breakdown voltage capability of

SLt
Figure 24.

Table I. Absolute Maximum Ratings
125·C unless otherwise noted I
RDL

Drain-source Voltage
IVN5200TND. IVN5201TND . • . . • . . . . • • . . . . . . .• 40V
IVN5200TNE. IVN5201TNE • • • . . . • • • . • . . • • • . •• 60V
IVN5200TNF.IVN5201TNF .•.....•.•......... 80V
Drain-gate Voltage
IVN5200TND. IVN5201TND . . . . . . • . . . . . • . . . . .. 40V
IVN5200TNE. IVN5201TNE . • . . . • • . . • . . . • • . . .. 60V
IVN5200TNF. IVN5201TNF ...•....•....••••.. 80V
Continuous Drain Current Isee note 1I . . • . . . . . . .. 4.0A
Peak Drain Current Isee note 2\ ••...••..•.••.•.• lOA
Gate-source Forward Voltage. . . . . • . . • • . . • . . . .. +30V
Gate-source Reverse Voltage . . • • . . • • • . . • • • • . •• -30V
Thermal Resistance. Junction to Case .••..••.. 10·C/w
Continuous Device Dissipation at lor below I
25·C Case Temperature •..••.• , . ••. . ••• ••• 12.5W
Linear Derating Factor. . • . . . . . . • • • • . • • •• 100mW/·C
Operating Junction
Temperature Range .......••....••. -55 to +150·C
Storage Temperature Range •.••..••••.. -55 to +150·C
Lead Temperature
11/16 in. from case for 10 secl . • • • . • • . . • • • •. +300·C

= 62!!
12

10 til

<:
0,...

....

!!!
6

4
2

1250

2500

3750

5000

6250

7500

QG (PICOCOULOMBS)

Figure 25. IVN5200 Dynamic Input Characteristics

Nole 1. TC = 25·C; controlled by typical ROSIONI and maximum
power dissipation.

Nole 2. Pulse width BOpsec. duty cycle 1.0%.
60

1\
\

100
10

:Ii

V
I...- ./

1500

"- .......
3000

til

II:
II:

0
7500

9000

Region 2

I Ii

REGI?N3,

Region 3

....

-'"

~Edlb N2

.... .L

....

1.0
i:JVN5200TND
IVN520lTND
IVN5200TNE
IVN5201TNE
IVN5200TNF
IVN520lTNF
0.1
1.0

l....r-I~~---Region 1

4500
6000
QG(pC)

5mse~ ~

rIp =
10

:::l
U

:cII:

o
o

/'~

:!.

II.

!/VGS

.1-

~lms;,c

iii

8
I\VDS

l00psec

r - - 5OOl'sec

r-"

10
VDS - DRAIN-SOURCE VOLTAGE (VOLTS)

Figure 26. IVN5200 VDS & VGS vs. OG

Figure 27. SOAR

REGION 1
100

A033
lead to secondary breakdown in MOSFET's. For a given field
gradient within the semiconductor there is a maximum
current density threshold above which self-sustaining avalanche breakdown can occur. This is a basic limitation on the
current handling capability of a power device. In present
MOSFET's the internal current densities are limited by
design. so that the junction temperature thermal limit is
reached well before any current injected avalanching is
present. Both of these breakdown modes lie well outside of
the published SOAR curves. and neither is of direct interest
to the device user. Oue to the absence of thermally induced
second breakdown. the SOAR for a MOSFET is greatly
expanded over that of a comparable bipolar.

the device. Region 2 is defined by the thermal capability of
the device. Normally a maximum junction temperature of
150·C is specified. so that in Region 2 the power dissipation
is limited to a peak junction temperature of 150·C. This
results in Region 2 being defined by a family of curves that
allow higher peak power for shorter pulse widths. Region 3 is
defined by the current capability of the device. The current
capability of a given device may be limited by the bond wire
diameter. the area of the bonding pad on the die. or by the
metallization on the die surface. Whereas the breakdown
voltage and junction temperature limitations can be readily
determined by direct measurement. the current limitations
are empirically derived from life testing. The maximum current is limited to a value which has been found to give an
acceptable service life. In a bipolar transistor. the rapidly
decreasing hFE at high currents effectively discourages operation in excess of the current ratings. In a MOSFET. however. the gain is not reduced at high currents. and there may
be a temptation. in fast pulse applications where a high
drain-source voltage may be acceptable. to operate with very
short high current pulses in excess of the ratings. Even if the
device dissipation is very low. this is inadvisable for two
reasons. First. the reliability or service life of the device is
undefined and likely to be shortened. and second. if the
current density in the device is increased sufficiently. it is
possible to reach the level where current injected avalanche
breakdown occurs. possibly destroying the device.

The normal manufacturers' SOAR curve is for a case temperature of 25·C and either OC or a single pulse. In the real
world. of case temperatures above 25·C and repetitive
pulses. the designer must modify the standard SOAR curves
for his particular application. This can be done by using the
transient thermal impedance Zithl curves which should be
made available by the manufacturer. 3.4

dVos/dt Limitations
The inherent bipolar transistor within the MOSFETstructure
can impose a limit on the rate of rise of VOS. Figure 28 is an
equivalent circuit where the parasitic bipolar transistor is
shown in parallel with the MOSFET. Even though the emitter
N+ and base P regions are connected at the surface of the die by
the source metallization. there is still asignificant base emitter
resistance I RBE I due to the bulk resistance of the Nand P
regions. In addition. the collector-base junction has capacitance ICob I. When VOS makes a positive transition. a current
will flow through Cob; I =Cob IdVOS/dtl. As VOS rises more
rapidly. more current flows through Cob until a pOint is
reached where the voltage across RBE is sufficient to turn on
the transistor. QI. This undesirable turn-on or switchback of
the parasitic NPN transistor interferes with the normal circuit
operation and can destroy the device. The threshold for
switchback varies widely from one device type and manufacturer to another. Maximum dVOS/dt information is not yet
a standard entry on the data sheets so the user will have to
either consult with the manufacturer or test the devices
himself. The IVN5000 and 5200 series parts will accept at
least 20V/nsec. The dVOS/dt rating of a device can be
improved by designing the die layout to minimize the base

For a bipolar transistor the SOAR curves will have a fourth
boundary. This region is defined by the thermally induced
second breakdown characteristic. In a bipolar device. there
are several ways to induce secondary breakdown. The first is
thermal. where the negative temperature coefficient of the
conduction resistance causes localized hot spots to be
formed. When the temperature of a hot spot is sufficiently
high. it's impedance is drastically reduced. funneling the
collector current through a small area and usually
destroying the device. Another mechanism for inducing
secondary breakdown is via avalanche breakdown. If the
collector voltage is raised to the breakdown point of the
collector-base junction and a significant current allowed to
flow. the device will go into secondary breakdown. It has
been widely advertised that MOSFET's do not exhibit secondary breakdown. This is not true. It is generally accepted that
at normal junction temperatures. the thermally induced
secondary breakdown phenomena so prevalent in bipolar
devices is not present in MOSFET's. however the avalanche
induced secondary breakdown is. This is not surprising; as
shown in the earlier discussion the MOSFET structure has
within it an NPN transistor. and the voltage limit on that
device is the base-collector junction breakdown voltage. The
current level at which primary breakdown becomes secondary breakdown. is a function of the base emitter resistance.
the temperature and the hFE of the bipolar device. In a
MOSFET. the base and emitter are shorted right on the die.
and for reasons of improving the dVOS/dt characteristic. the
resistance is made as low as possible. In addition. the hFE of
the MOSFET parasitic bipolar is much lower than a typical
bipolar device. The result is that the current level at which
primary breakdown becomes secondary breakdown is much
higher in a MOSFET than it is in a comparable bipolar transistor. The device ratings are selected so that the maximum
VOS is well below the actual breakdown point in the
production devices. Current injected avalanche breakdown.
present in bipolars during reversed bias operation. can also

,!.~ oj

Cob

RBe

s
Figure 28. Parasitic Bipolar Switchback Equivalent Circuit

A033

U~UIL
emitter resistance, and by controlling the P region doping to
produce a bipolar with low hFE. As in any bipolar transistor,
the hFE of the parasitic NPN is a function of temperature and
the dVDS/dt snapback threshold will decrease at high
temperatures.

the current. In the future, it is reasonable to expect that low
voltage, low rDS(ON) devices will be designed specifically
for this service, which will make possible the efficient generation of large amounts of 2V or 5V power.

Use of the Internal Diode
For values of VDS risetime below the threshold of switchback, the internal NPN transistor is inactive, and acts simply
as a bipolar with the base shorted to the emitter. The equivalent circuit could be redrawn, as shown in Figure 29, with a
diode in parallel with an ideal MOSFET. If VDS is reversed,
this diode will conduct and may be used in switching circuits
as a rectifier or inductive energy clamp. The forward current
and breakdown voltage ratings of this diode are equal to the
current and volt&ge ratings of the parent MOSFET. The reverse recovery time trr of this diode can be excellent; the
IVN500 and 5200 series devices have a typical trr of 60 to 70
ns. There are several reasons for the good recovery time of
this diode. First, the MOSFET fabrication process produces
essentially lightly doped epitaxial diodes with sharply defined doping gradients. Second, the P region is often formed
by ion implanting, a process that causes dislocations in the
crystal structure. These dislocations can act as recombination centers for the junction stored charge, thereby reducing
the recovery time. The diode recovery time is senstitive to the
process used and can vary widely from one manufacturer to
another. Since trr is not, at present, a data sheet entry, the
user is advised to contact the manufacturer for values.

Internal Zener Protection
Th(l first VMOS devices to appear on the market included an
on-chip zener diode from gate to source to prevent gate
breakdown due to static charging. This was formed by diffusing in an additional NPN transistor (Figure 30), with the
zener action accomplished by the reverse breakdown of the
base-emitter junction. The zener formed in this manner has a
number of drawbacks. First, the power dissipation is very
limited, 2 mA DC being typical, and second, if the gate is
pulled negative to -0.6Vor more, the NPN transistor will turn
ON and draw current from the drain circuit. This may destroy
the transistor. The result is poor reliability in many applications. Experience has shown that the gate structure of a
power MOSFET is much more rugged than the gate structure
in MOS IC devices, and given reasonable care in packaging,
handling and installation there is no need for this zener in
most applications.
D

The FET itself may be used as a synchronous rectifier. Once
the channel has been formed by making VGS positive,
current will flow through the device in either direction with
equal facility. For synchronous rectifier operation, VGS is
zero during the period when the drain is positive with respect
to the source; when VDS reverses, the gate is enabled and
current flows through the device in the reverse direction. The
forward drop is proportional to rDS(ON) and the current
flowing; when the threshold of the parallel diode is reached
the current will bypass the FET chan nel and the rectifier will
act like a normal PN junction diode.

s
Figure 30. Parasitic NPN Transistor with Internal Zener

Multiple Device Operation
The positive temperature coefficient of rDS(ON) is of great
assistance when MOSFET's are paralleled. It is possible, in
DC applications, to parallel devices without any matching,
and those devices that initially draw the most current will
heat up and shift the current to other devices to more equally
distribute the current. This is exactly the opposite of the
scenario for bipolar devices. While the paralleling of unmatched devices will work, it is a poor idea because in DC
applications a higher than necessary dissipation may occur
and in switching applications it is possible for one device to
turn on or off, before or after the other devices and have to
accept the full load current. This may force the device to
function outside of its safe operating area.

.J
s
Figure 29.

It is recommended that the user parallel devices which have
been matched for VGS(th) to within 5 to 10% accuracy. This
will assure that the turn-on and turn-off delays due to the
gate voltage rise and fall times, relative to VGS(th), are nearly
equal. rDS(ON) will also be matched, so that excessive differential heating is not required. Some additional improvement in rDS(ON) matching may be achieved by providing a
higher VGS drive so that all of the parallel devices run attheir
minimum rDS(ON) value.

For currents below the 0.6V diode threshold, the FETacts as
an ultra high speed, high voltage, low capacity rectifier with
no minimum offset voltage. This type of operation has been
used for a power rectifier at 15 MHz. Presently available
MOSFET's can be used in this manner, with the only drawback being the relatively high rDS(ON) values Which restrict

I·
I

A033
sink is better if the heat input is distributed in several sources
rather than in one. While the arguments for using a single
large bipolar device instead of multiple smaller devices are
well founded, it does not necessarily follow that the same
technique should be imitated in power MOSFET devices,
especially in the light of the rapid cost increase of the larger
die. The tradeoff may well be multiple small devices with low
die and package and moderate heat sink costs, versus single
devices with high die, package and heat sink costs. Just
where the cost crossover point between single and multiple
devices will be is yet to be determined, especially since the
very high prices for the present larger MOSFET chips is
certain to be reduced substantially. In any case, the user
should be aware ofthis tradeoff which is quite different from
bipolars, and not unnecessarily perpetuate the bias against
parallel bipolars into the application of power MOSFET's.

It should be kept in mind that many MOSFET devices have
gain bandwidths over 500 MHz. It is entirely possible for
these devices to oscillate at very high frequencies, especially
if multiple parallel devices are used. This is often an unsuspected cause of device failure. If the circuit designer is using
a low bandwidth oscilliscope during breadboard development, it is possible not to be aware of the self oscillation
therefore, use of an oscilliscope with a bandwidth of at least
200 MHz is recommended. The tendency towards oscillation
can be greatly reduced by inserting ferrite beads or low value
(50 - 100 ohm) resistors in series with the gate leads as shown
in Figure 31.
For fast pulse applications, it is not sufficient to just match
the devices. The circuit must also be reasonably symmetrical
so that identical drive voltages are applied to each gate. At
high speeds the inductive, as well as resistive, effects must
be considered. If, for example, the parasitic inductance in the
drain lead of Q1 ismuch smaller than that in the drain lead of
QN, when the devices are first turned ON most of the load
current will initially flow through Q1, even if the gate drives
and threshold voltages are identical.

Similar considerations apply if devices are to be operated in
series. It is particularly important that all devices in the same
series string come ON simultaneously, otherwise one device
may take all of the voltage momentarily. The devices should
be well matched for VGS(th) and careful attention given to
producing simultaneous gate drive. In those applications
where the maximum possible voltage capability is desired, it
may be necessary to match the rDS(ON)NGS characteristic
to assure equal voltage distribution during switching transitions. This is a much more complex procedure than VGS(th)
matching, and should be considered only as a last resort.
Analogous to the parasitic inductance in parallel operation is
the effect of circuit parasitiC capacitance in series operation.
If differential drain-source capacitances (either in the device
or in the circuit layout) exist in the series string, the transient
voltages may not be shared equally.

Variations in the stray gate circuit capacity and the device
input capacity can also cause uneven turn-on in fast pulse
applications. The effect of this can be reduced by equalizing
the stray capacity and minimizing the intergate impedances.
For applications requiring switching times below 5 to 10 ns.,
it may be necessary to match the device capacitances.
It should be kept in mind that most of the complications to
paralleling mentioned above generally apply only for very
fast pulses. Most applications will use transition times well
above 10 nsec, where simple threshold voltage matching is
all that is required. This is quite different from bipolar
transistors, where paralleling more than two devices can
become quite complex and expensive. Due to the practical
difficulties of paralleling large numbers of individual bipolars, (and SCR's also), the trend has been to develop ever
larger single devices. As the die size increases, a pOint is
reached where either the thermal capabilities or the available
mounting areas in the low cost packages are exceeded so
that an expensive package is required. The heat sink will now
see a concentrated thermal input through the relatively small
package to heat sink contact area. The efficiency of a heat

RADIATION EFFECTS
The effects of nuclear radiation on power MOSFET's is beginning to receive a good deal of attention, although very
little information has been published to date. Mr. John Buck,
a radiation effects specialist with Litton Guidance and
Control Systems, has provided the following information:

" ... When used in military systems with a nuclear hardening
speCification, VMOS and bipolar power devices have differ-

LP1

01
GATE
DRIVE

_~----4--

- - - - - - - -~------i(

Figure 31. Parallel Devices

A033
ent susceptibilities to the neutron and total dose radiation
environments. VMOS devices are almost immune to neutron
damage because they are majority carrier devices. Bipolar
power devices. on the other hand, suffer considerable gain
degradation in even moderate neutron environments. VMOS
devices, however, are more adversely affected by the total
dose (gamma) environment than are bipolar devices.

trons with (the) resulting decreaseoftrapped positive charges.
Annealing will take place at room temperature, and the rate _
of annealing will increase at higher temperatures due to
increased hole de-trapping.
"Derbenwichj51 has studied the combined effects of total
dose damage and annealing. His method involves measuring
gate threshold voltage shift versus total dose to determine a
linear damage region for the device. Then another set of the
same device type is irradiated to a dose level within the linear
damage region and then allowed to anneal at room temperature under fixed bias for several weeks or Ibnger. A transient
annealing function is then determined for the device_ His
theory then states that the convolution of dose rate versus
time with the transient annealing function predicts the net
shift in gate threshold voltage when annealing is occuring
simultaneously. This model provides a means for calculating
MOS damage in low dose rate long term environments where
annealing is a significant factor_ A typical long term ionizing
radiation environment is a satellite space application where
the system may be irradiated and anneal simultaneously for
a five year mission."

"Total dose damage to MOS devices occurs as a result of
(the) trapped charge in the gate oxide layer. Charge is
created when gamma particles collide with (atoms) in the
oxide layer causing formation of electron - hole pairs. The
electrons are more mobile than the holes, and are (more)
easily swept from the oxide layer. The holes, on the other
hand, tend to drift toward trapping sites where positively
charged hole layers are formed_ This positive charge remains in the oxide layer and causes the gate threshold
voltage olthe device to decrease. Total dose damage to MOS
devices is measured as a shift in gate threshold voltage.
Drain leakage current also increases with total dose as a
result of the gate charge buildup.
"Two other factors are important in discussing total dose
damage effects in MOS devices. One is the amount of gate
bias applied during irradiation and the other is the effect of
annealing. The more positive (the) gate bias applied during
irradiation the greater the total dose damage. This is because
the holes will migrateto trapping sites closer to the sensitive
Si-Si02 interface.

Test Results
"Figure 32 shows that total dose damage to IVN5000 parts is
linear to about 5000 rads (Si) for bias voltages of 0, 2.5V and
5V. The horizontal error bars are dosimetry error estimates.
Vertical bars are standard deviations based on a sample of
five parts tested. Preliminary tests at higher bias voltages
indicated device failures at much lower dose levels. Device

"Annealing, on the other hand, is a curing effect since the
process of annealing is the recombination of holes with elec-

2.4

2.0 ~

JU
YTJ:tt

-~v11JJl~)lt
~

I-

""t-

1.6

II'

IT.

IJ:

OV
YT - 4814 RAD (Si)

r- ""t-

c ~ 2:042
r-!.~ -0.0783

1:1;_1

I.I.·.L

C ~ 1.099
A ~ -0.0131

0.8

0.4

1 hr.
0.0
100

1 ~ay

I +I
101

102

1 week

1 month

111+

I 1+1 I

104
TIME (MINUTES)

Figure 32. VMOS LlNAC Annealing Curves

105

A033
failure on these tests was due to leakage currents approaching or exceeding the drain currents at which the DC gate
voltage measurements were made (SOOI'A). Pulse testing at
higher currents may have allowed gate voltage measurements to be made at slightly higher dose levels.

3.00

"Figure33 shows the results of the annealing measurements
made forOV and 2.SV biased parts after LlNAC irradiations to
4814 rad (Si) and 4283 rad (Si) respectively. It can be seen
from Figure 33 that these total dose irradiations are within
the linear damage regions for the device."

r------,.------,-------.-----r------,------,
.y = 106 RAD(Si)/SEC
MEASUREMENT WITHIN 10 MINUTES AFTER EXPOSURE

2.S0~----------t-----------+_----------~----------~-----------r----------_1

VG =S.OV

2.00~-----_+~-------_+----------~------~~+_------_i~~--------_i

1CI 1.50~----------~----------+_--------~~--~==5f~~----------~----------_l
1.00~----------t---------~~~~~----+_--------~~~~~-----r----------~

O.SO ~------~7'f'-7~-----:::;*-=:.--'-------+-----------t-----------r-----------j

DOSE - RAD (51)

Figure 33. VMOS LlNAC Test Results

(2) H. Suwa and A. Ishitani, "Vertical Field Effect Transistor
and It's Application to High Fidelity Audio Amplifiers,"
Proceedings of the Audio Engineering Society Convention, May 13-16, 1975.

ACKNOWLEDGEMENT
The author would like to thank B. Rosenthal, N. Zommer, and
B. Wier for their assistance in preparing the discussion on
structures and B. Smithson who did the characteristics
curves.

(3) "SOAR-The Basis for Reliable Power Circuit Design,"
Phillips Application Note No. 68, 30 April 1975.

BIBLIOGRAPHY

(4) R. Severns, "Tips On Using MOSFET's in Switching
Regulators," Intersil Application Note No. AO-36.

(1) M. Nagata, "Power Handling Capability of MOSFET,"
Proceedings of the 8th International Conference on
Solid State Devices, Tokyo 1976 and Japanese Journal
of Applied Physics, Volume 16 (1977) Supplement 16.

[S) G. F. Derbenwick and H. H. Sander, "C-MOS Hardening
Predictions for Low-Dose-Rate Environments," IEEE
Transactions on Nuclear Science, NS-24, No.6,
December 1977.

D~DIb

A034
Switchmode Converters
Above 100 kHz
by Rudy Severns

With the introduction of power MOS switches, and the
general improvement in other components, it is now possible
to design switchmode converters with switching rates in the
range of 100 kHz to 5 MHz, and from both off-line and low
voltage DC bases.

used at 200 kHz, the performance can be a good deal less
than optimum.
As shown in Figure 1, the converter can be viewed as having
primary and secondary topologies connected by a transformer. Because of the difficulties of deSigning the power
transformer at 200 kHz, each of the three circuit elements
must be considered in relation to the other two. For example,
the incorrect selection of primary switch or output rectifier
connection may make the transformer impractical at 200
kHz.

Unfortunately, a 200 kHz switchmode converter is a bit more
t'lar just a higher frequency version of the conventional 20
kHz converter. While the circuits and components used are
similar, there are a host of significant differents which alter
the design.

HOW HIGH IN FREQUENCY?
PRrMARY

Early in the design process, a decision must be made on the
switching frequency. Most performance parameters (cost,
volume, bandwidth, efficiency, etc.) change rather slowly
with increasing frequency, so there is relatively little to be
gained by going up by a factor of two or three. If significant
improvements are to be achieved, the switching frequency
must be increased enough to not only reduce the size of the
mag netic com ponents, but also to enable the use of alternate
components and materials which provide lower cost,
improved performance or both. Real changes do not appear
until the switching frequency has been increased by an order
of magnitude or more.

SECONDARY

UII(]J
Figure 1.

For primary topologies, the deSigner must chose between
switch mode (modified square waves) or resonant converters.
If switchmode is desired, then the choice is between voltagefed, current-fed with non-overlapping switch conduction, or
current-fed with overlapping switch conduction. Table I is a
comparison, pro and con for these options.

The choice of operating frequency is influenced by the
converter specification, the choice of switch (bipolar or
MOSFET) and the power level. For offline switchers using
bipolar switches, the optimum frequency would be about 200
kHz. From low voltage DC sources, the switching frequencies
using bipolar devices can be increased to 300 to 600 kHz. If
power MOSFET switches are used, the switching frequencies
may be increased to the megahertz range, and there is
increasing evidence that this may be desirable, for low power
at least. As the power level goes below 100 watts, less and
less is gained from operating arounp 200 kHz, the reason
being that the components don't really get much smaller or
cheaper. If real improvements are to be made at low power,
new designs should operate in the low MHz region using air
core magnetics and MOSFET switches. Fortunately, the
lower the power level the easier it is to go up in frequency. As
the output power is increased above 1KW, when using
bipolar switches it will be necessary to reduce the switching
frequency towards 100 kHz because the available large
devices are somewhat slower. As large power MOSFET's
become available, higher frequency operation will be
possible.

A variety of resonant circuits are available [1,2,3.4) to the
designer but, except for the work by. Miller, these circuits
have not yet been widely used at high frequencies. Thus, it is
difficult to comment on their use from direct experience.
From a theoretical point of view, however, the resonant
converters should work very well indeed, and if it is possible
to operate the current-fed switch mode circuits in the resonant
mode by adding a resonating capacitor, then a large number
of new resonant converter topologies will be available to the
designer. It is also possible that some of the series and
parallel commutated SCR inverter circuits can be used as
high frequency resonant converters, with power MOSFETs
instead of SCRs as switches. The use of resonant converters,
at high frequencies, deserves a good deal more attention
than is being given at present.
Examples of good and poor choices for high frequency
circuit topologies are shown in Figures 2 and 3. Figure 2 is a
current-fed circuit; [5) Figure 3 is the common voltage-fed
bridge quasi-squarewave converter. A comparison of the
two circuits is given in Table II. In general, the current-fed
family of converters is more suitable for high frequency
switch mode converters.

CIRCUIT TOPOLOGY
Having chosen a switching frequency, the next step is to
select circuit topology. While the common 20 kHz converter
topologies (parallel, half-bridge, full bridge, etc.) can be

D~DlL

A034
Table I. Regulator Topology Tradeoffs
PRO

CON

Voltage Fed Converter
1. Wide Variety of Circuits
2. Good Output Regulation at Heavy Loads
3. Circuit Well Understool

Current Fed Converter
1. Wide Variety of Circuits
2. No Current Spikes
3. Storage Time Overlap OK
4. Good Multiple-Output Regulation at All Loads
Resonant Converter
1. Low SWitching Transition Stresses
2. Low Capacitive Loss
3. Low EMI

1.
2.
3.
4.
5.
6.

Current Spikes can be severe
Switch Overlap is Fatal
Capacitive Losses Poor at Low Powers
Poor Output Regulation at Light Loads
Poor EMI Characteristics
High Switch Transition Stress

1.
2.
3.
4.

Voltage Spikes
Capacitive Losses Poor at Low Power
Moderate EMI Characteristics
Moderate Switch Transition Stress

1.
2.
3.
4.

Resonating Capacitors a Problem
Q Multiplication Increases Currents or Voltages
Fixed Frequency Operation Presents Problems
Circuits Tend to be More Complex

Table II. Circuit Comparisons

Figure 2
1. Even with fast recovery diodes. the reverse .recovery
time of the output rectifiers. is a significant portion of
the operating cycle. D1 will be in forward conduction
while D2 is still recovering. This places a short circuit
across the secondary which is reflected into the primary.
Because this circuit is current-fed. the only effect is to
slightly increase the energy stored in L 1 preventing
current spiking in the switches.

Figure 3
1. During the rectifier reverse recovery time. a current
spike is reflected into the primary switches. At 200 kHz.
the transformer leakage inductance is made quite small
by design. so there is very little impedance to limit the
current spike. If Schottky barrier diodes are used. the
large diode capacitance will also cause primary current
spikes.

2. Using the full wave rectifier shown. the output rectifier
reverse voltage will be twice the output voltage plus
one diode drop (not including noise). irrespective of
the line voltage. so that hot carrier diodes can be used
at voltages above 5 volts.

2. For a given output voltage. the diode reverse voltage is
relatively high. As an example. with a 5 volt output and
a 2:1 line excursion. the rectifier reverse voltage varies
from 11.7 to 22.8 volts. If the switch storage time
reduces the maximum ON time to prevent overlap. the
reverse voltage is even higher. The higher reverse
voltage also increases the dVidt that the rectifier is
subjected to.

3. At high frequencies. there is a greater tendency towards
primary volt-second asymmetry. especially if bipolar
switches are used. This can cause core saturation
current spikes in voltage fed topologies. I n this circuit.
spiking is prevented by L 1. and core saturation is
relatively harmless. Current spikes due to reflected
capacity and switch overlap. are also suppressed.

3. There is no protection from core saturation. switch
overlap or reflected winding capacitance current spikes.
In the case of bipolar switches. the need to prevent
overlap due to storage time. allowing for manufacturing
and temperature variations. can significantly reduce
the pulse width dynamic range. Core saturation can be
reduced by inserting a series capacitor in the primary.
but this capaCitor must be carefully selected to prevent
core saturation during fast line or load slewing.

4. Because a single choke is common to all outputs. cross
regulation between the outputs for varying loads is
relatively good.

4. Separate chokes are required on each output. and for
good regulation each choke must remain in continuous
conduction. There is no compensation for the choke
resistive regulation effects. The net result is that at
200 kHz. the cross regulation of multiple outputs is poor.

5. Diodes D3 and D4 do not see a reverse potential at the
end of their conduction cycle. so the reverse recovery
time of these devices is not critical.

O~OIL

A034

!I
I

pw~

f-oPWM

en
D1

f--o PWM

PWM

50%

Figure 2.

Figure 3. Quasi-Squarewave Converter

1
pwM1

Half-Bridge

Boost Regulator/Half-Bridge
Low Line, PT = 9.1W
High Line, PT = 6.5W
Tj
= 63°C

Low Line, PT = 35.BW
High Line, PT = 12.9W
Tj
(A)

(B)

Figure 4.

plane zero which is difficult to compensate for with single
loop feedback. By using multiple AC and OC loops, this
problem can be overcome.

Not only the switching frequency, but the choice of switch
can affect the choice of topology. For example, if power
MOSFETs are used as switches, the topology selected can
have a profound effect on the conduction losses. A simple
example is shown in Figure 4. Figure 4(a) is a normal halfbridge quasi-squarewave converter, while 4(b) is an unmodulated half-brdige preceeded by a boost regulator.
Given the conditions in Table III, the power losses for (b) are
much lower than (a). Because the cost of power MOSFETs is
a strong function of 1/ros' the three devices used in (b) may
be much cheaper than the two devices in (a). While this is a
fairly simple example, the boost derived family of converters
generally provides lower MOSFET conduction losses than
buck derived current-fed converters. Figure S(a) and (b)
shows two examples of boost derived current-fed converters,
one using overlapping conduction and the other a secondary
shunt switch. There are many other possible circuits[6j that
may be used. Unfortunately, the boost family of converters
has disadvantages also:

2. The output ripple current in a boost converter is discontinuous (the input current is continuous) so that the

Table III. Power MOS
Topology Conduction Loss Comparison
Assumptions
1.
2.
3.
4.
S.
6.
7.
8.
9.

1. The control loop transfer function contains a right half-

= 200W
= 80% Without Switch Losses
Vbc
200V to 37SV
TA
= SO°C
ros
= 2.S!l at 2SoC
Filter Inductor is Large
BVOSS = 4S0V to SOOV
OJA
= 4°CIW (TO-3 Case and Heat Sink)
ros Temperature Coefficient is 0.6%/oC
1)

D~DIl.

A034

-=-

in (b) should be used because it will give much better cross
regulation. A major cause of poor cross regulation is the
leakage inductance between the secondary windings, proportionally somewhat worse at high frequencies. The
autotransformer minimizes the leakage inductance, as well
as providing some resistive compensation for load variations.

50%
} DUTY
CYCLE

OVER-{
LAPPING
CONDUCTION
PWM

In the case of a high voltage output, the designer is faced
with the choice of multiple windings or voltage multipliers
(Figure 7). It can be very difficult to build a satisfactory
transformer for connection (a) due to the need for stacked
insulated windings. Because the insulation spacing is related
to the voltage and not to the operating frequency, good
primary-to-secondary coupling and uniform predictable
winding voltages are very difficult to achieve at 200 kHz. The
voltage multiplier makes the transformer design easier, but
requires a large number of capacitors. Fortunately at 200
kHz, these capacitors can be quite small. The diode shunt
capacity is the most serious limitation for high frequency
multipliers, but for small multiplication ratios (3 to 5) and
reasonable power levels (>10W) this does not seem to be a
serious problem. Present experience indicates that for
voltages over 1KV, the use of multipliers should be
considered, if only for the sake of the sanity of your
magnetics deSigner. The reflected capacitance from the high
voltage secondary will be quite large, especially if a multiplier
is used. Even allowing forthe increased leakage inductance,
the primary switch currents are usually unacceptable in
voltage-fed topologies; some form of current-fed topology
will give much better performance. The voltage multiplier
will see wide low amplitude current pulses rather than short
duration high amplitude current spikes, and this will reduce
the losses and improve the output regulation.

Figure 5.

output ripple current is large. As yet, low voltage «50V)
high current film capacitors are not available, so some
penalty in volume is paid for low voltage outputs.
3. In those converters using overlapping conduction in the
primary, a large voltage spike can be generated due to the
interruption in the primary by secondary leakage inductance current. When the shunt switch is in the secondary,
this spiking is greatly reduced.
The output winding/rectifier topology must also be carefully
selected with an eye to transformer limitations and primary
topology requirements. Figure 6 shows two rectifier connections for multiple outputs. In (a), separate windings are used,
and in (b), an autotransformer connection is used. If DC
isolation between outputs is not required, then the connection

I:
I :
I

•

li!~o
(A) MULTIPLE WINDINGS

(8) VOLTAGE MULTIPLIERS

Figure 7. HV Rectifier Schemes

FEEDBACK LOOP CONSIDERATIONS
Increasing the switching frequency from 20 to 200 kHz
provides a similar increase in the feedback loop gain crossover frequency. Given the proper type of control loop and
compensation, a gain cross-over of 20 to 100 kHz is possible,
comparable to the usual series regulator. While it is possible
for the designer to put in a Single low frequency pole with
gain cross-over at 1 to 2 kHz and have performance equal to a
20 kHz switcher, most designers will opt for higher bandwidth.
As with the input and output topologies, the feedback
scheme must be carefully considered. Table IV is a

Figure 6.

O~OIb

A034
Table IV. Fixed Frequency Control Options
1. Single DC Loop 2. DC Loop and Switch Peak Current Control
3. DC Loop and Choke Voltage Sensing
4. Feed Forward
PRO

CON

Single DC Loop
1. Well Understood
2. Simple Control Circuits
3. For 20 kHz Equivalent Performance a Single Low
Frequency Pole May be Used

1. Moving Capacitor ESR Zero Uncompensated
2. Variable Load Capacity is Uncompensated
3. Load Capacity May be Much Larger than IC Filter
Requirements
4. Two-Pole Rolloff with Peaking
5. Boost Converters have Right Half-Plane Zero
6. Gain Crossover Limited to 10-15% of fo
7. No Inherent Current Limiting

DC Loop and Switch Peak Current
1. Inherent Overcurrent Protection
2. Inherent Soft Start Capability
3. Higher Gain Crossover Frequency
4. Single Pole Rolloff
5. Inherent Current Sharing for Parallel Modules

1.
2.
3.
4.

DC Loop and Inductor Voltage Sense
1. Higher Gain Crossover Frequency
2. Right Half-Plane Zero Compensation
3. Compensation for Variable Load Capacitance
4. Moving ESR Zero Compensation
5. Single Pole Rolloff

More Complex Control Circuit
Requires Switch Current Sensor
No Compensation for Moving ESR Zero
No Compensation for Varying Load Capacity

1. Complex Control Circuit
2. Choke Voltage Sensor Required
3. No Inherent Current Limiting

Feed Forward
1. Very Simple in DC Loop Systems
2. Compensates for Loop Gain Variation with Duty Cycle
3. Improves Line Transient Response

1. Difficult to Apply to Multiloop Systems
2. Not Adequate as Regulation Loop by Itself

Some other control loop gremlins which appear at high
frequencies are:

comparison of the more common fixed frequency control
schemes.

1. The circuit stray capacitance is proportionately larger at
200 kHz, so there is an increased likelihood of subharmonic instabilities due to capacitive feed-through at
the ripple frequency. Careful layout and good bypassing
are the best means to combat this problem.

A number of control problems may be encountered at high
frequencies. AT 20 kHz, the. output filter capacitor is usually
selected for low ESR, with capacitance a secondary
consideration. Usually the filter capacitor is large, compared
to the load capacitance. However at 200 kHz, the film
capacitors used have an ESR two orders of magnitude
smaller, so the filter capacitor will now be much smaller and
the load capacity may very well be larger than the filter
capacitor. The load capacitance may also be undefined or
variable. This can make it very difficult to stabilize the
feedback loop. If power modules are to be paralleled, each
loop sees the capacity of the other modules, which may also
be a variable. When a boost-derived topology is used, there is
a right half-plane zero in the control transfer function.

2. In some types of pulse width controller circuits, the time
delay in the digital elements (especailly if CMOS is used)
may become large enough to cause significant phase
shift due to transport delay. As a rough guide, the delay
times though the controller should be kept below 5% of
the half-period, or about 100 nsec in a 200 kHz convertp.r.

COMPONENTS AT HIGH FREQUENCIES
Operation with switching rates above 100 kHz requires a
fresh look at component selection. As in the case of the
circuit topology, each of the circuit components must be
evaluated for performance, taking into account component
parasitic effects which are often ignored at 20 kHz.

These effects cannot easily be compensated for in the simple
DC control loop. Much better performance can be obtained if
a combination of AC and DC loops are used. [7,8,9] The use
of multiple loop control schemes is highly recommended
above 100 kHz.

A034
Switches

Baker Clamp (Figure 10) is perhaps the simplest and most
common way to accomplish this. It provides a marked
reduction in storage time, but does not really improve the
transition times in fast low voltage devices. In a high voltage
device, where a good deal of charge is stored in the collecter
region during saturated operation, the use of a clamp will
reduce the turn-off transition time. It should be kept in mind
that there is a limit to the useful turn-off beyond which there
is no further improvement. Excessive negative base drive
during reversed bias operation causes current crowding in
the emitter region, which in turn lowers the threshold at
which secondary breakdown will occur. The designer should
provide sufficient drive to obtain good performance, but no
more.

The designer has the choice of using either bipolar or
MOSFET devices; some ofthe tradeoffs are given in Table V.
As MOSFETs become less expensive and more diverse in
ratings, there is little question that power MOSFETs will be
the switch to use above 100 kHz, but at present, bipolars
must be considered for some applications with suitable
circuit arrangements to compensate for performance
limitations.
Fast switching times in bipolars can be achieved by first
selecting fast devices and then driving them correctly. The
switching time test circuits used by bipolar manufacturers
often do not drive the device ON or OFF hard enough, so that
the publicized switching times are often not truly indicative
of the devices' capabilities. The gain bandwidth, ft, when
given, is a much more reliable indicator of usefulness at high
frequencies. Generally, the designer should select devices
with an ft of 10 mHz or more, and then test the devices in the
actual circuit. Figure8shows an idealized base current drive
waveform. At turn-on, large, fast-rising current pulse is
applied. When the device is fully ON, the turn-on pulse is
removed and sufficient base drive, in proportion to Ic if
possible, is provided to keep the switch in or near saturation.
At turn-off, a fast rising negative current pulse is applied to
minimize the storage time. A large turn-off pulse will also
produce a rapid fall time in low voltage devices and very fast
high voltage devices using interdigated structures. It has
been shown,l15] however, that for many high voltage
transistors, a large turn-off pulse, while reducing the storage
time, may extend the turn-off current tail, significantly
increasing the switching loss. For devices rated at 400 volts
and higher, it may be desirable to use a more gradually
decreasing base drive and exchange increased storage time
for reduced switching losses. During the OFF time, the base
of the transitor should be clamped to the emitter through a
low impedance; this will minimize false turn-on due to noise
and capacitive coupled currents induced by high dV/dt in
other parts of the circuit. These requirements are really not
difficult to meet and a wide variety of circuits are possible. (10]
Figure 9 shows several possibilities using the DS0026 clock
driver as a basis. This IC will source and sink 1A in<20 nsec,
and provides an excellent interface between the logic and
the switch drive. The IC may be used barefoot, as in (a) and
(c) orwith power MOSFETs, as in (b). To reduce the storage
time, some form of antisaturation circuit can be employed to
prevent the collector voltage from gOing below the base. The

As the base is driven harder, some devices (especially high
voltage transistors) will display a region of quasi-saturation
at turn-on, as shown in Figure 11. Low voltage devices, and
those using an interdigitated structure display this effect to a
lesser extent. Unfortunately, the data sheet is seldom of
much help in determining the presence of this problem and
the designer may be forced to test a number of different
types of devices in his circuit to find out which are suitable
and which are not. In a similar manner, quasi-saturation and
a current tail can occur at turn-off,l11] and again, the only
way at present to detect these effects is by testing. Table VI is
a short summary of bipolar performance limits.

TURN'()N PULSE

Ie
~F

O~L---------+-r--------------

___________ TURN·OFF PULSE

Figure 8. Ideal Bipolar Base Drive

Table V. MOSFET Versus Bipolar Tradeoffs
MOSFET

BIPOLAR

1. FET switches are much faster-10 to 20 nsec switching
times can be readily achieved.
2. No storage time effect.

1. Transition times of 50 to 200 nsec at best, with careful
base drive design.
2. Storage times of 500 to 1500 nseccommon. This can be
reduced to 150 to 300 nssec with antisaturation circuits.
3. Base drive requirements relatively high, especially with
base overdrive for fast switching.
4. At present bipolars, even fast ones, are lower in cost.

3. Very low drive power required.
4. MOSFETs are more expensive at present, but should
be much cheaper in the future.
5. There is limited selection of MOSFET power devices.

5. A very wide variety of high speed and high power
devices are available.

A034
+12V

+ 12V

r-----100 ns, much too
slow for 200 kHz switches.
5. Excessive minimum dead time. The typical minimum
dead time is 500 ns. At 200 kHz this is 20% of the half
period and is a serious reduction in the available dynamic
range.
The most satisfactory of the present IC's are the new Silicon
General SG1526 and the Ferranti ZN1066.

A034
+24

~~----t-~~~~SENSE

Figure 30. High Frequency PWM Circuit

wires or using the pc board traces as transmission lines.
Another useful approach, shown in Figure 32, uses a small
ceramic capaCitor to reduce the area of a high dl/dt loop.
This is simply an example of RF bypassing.

3. Slew rate limiting. At high frequencies the designer must
pay attention to the power bandwidth or slew rate of the
op-amp, and be certain that the op-amp has the capability
to drive the compensation capacitors and whatever other
load is on the output of the op-amp.

The final layout will probably look quite different from the 20
kHz norm but there is no reason that it need be exotic or any
more expensive. In fact, due to the additional care used, it
may very well be less expensive.

Since comparator transitions of less than 100 ns are needed,
most comparator IC's are eliminated; the LM111 A is about as
slow a comparator as is useful. Remember that the comparator switching speed is affected by the dV/dt of the input
ramp, and the maximum practical ramp amplitude should be
used to maximize dV/dt.

Table VIII. Circuit Layout Tips
1. Identify the Hi dlldt Paths and Minimize their impedance
2. Minimize the Area of Current Loops

CIRCUIT LAYOUT

3. Use Twisted Leads for Transformer Connections

Having selected the circuit topology and the components,
the designer is faced with putting it all together in a workable
layout. At 20 kHz much latitude is permitted, and even the
worst rats nest will work. This is not the case at 200 kHz. A
200 kHz switcher has frequency components beyond 100
mHz and has much more in common with a wideband RF
amplifier than a 20 kHz switcher. A careless layout may very
well not work at all. The key is "THINK RF" during the layout.
A collection of useful layout tips are given in Table VIII.
Figure 31 gives a good idea of how much inductance is
introduced by the interconnection leads, and how this
inductance can be reduced by either twisting the connecting

4. Arrange Transformer Lead Breakouts to Minimize Inter
Connection Inductance
5. Bypass Hi dl/dt Loops with Ceramic CapaCitors
6. Use Star or Ring Connections for Parallel Components
7. Use Goundplane Construction
8. Beware of Inductive Device Cases
PARASITIC INDUCTANCE

(A)
6" LENGTH OF #22

6" LENGTH x 1/2" RIBBON

II
10
II
I'
II
10
10

LARGE FILM
CAPACITOR

PARASITIC INDUCTANCE

J
\,

(A)

(B)

T J}-l\, l~~'=o,
CERAMIC

(C)

(D)

Figure 31. Inductance of Wire Loops

Figure 32. HF Bypassing

A034
CONCLUSION
Having gone through this exercise of selecting new topologies, components and layouts, one wonders if it's really
worthwhile. Is the volume and weight reduced, is there any
cost reduction, and can we do better in the immediate
future?

'.~

tions where the line dropout requirement is very small and
conduction cooling is provided, the size reduction can be
dramatic.
The answer to the cost question is a definite maybe. There
really have not been enough commercial switchers designed
at these frequencies to know the relative value to the
arguments in Table X, but if the cost of the MOSFETs and fast
diodes can be reduced, the high frequency converters
should I:le cheaper to build.

Some of the pro and con arguments for these questions are
summarized in Tables IX, X, and XI. The amount of volume
reduction realized is very much a function of power output.
From zero to 20 watts little is gained by going to high
frequencies; from 20 to 100 watts the volume may be reduced
by a factor of 1.5, and above 100 watts a factor of 3 or more
may be obtainable. The actual size reduction achieved
depends strongly on the power supply specifications. If, for
example, a line voltage dropout of 50 or 100 ms must be
accommodated, the size of the DC energy storage capacitors
is so great that the operating frequency of the converter is
relatively unimportant. On the other hand, in those applica-

A final note of caution: Most designers find that their first
effort at 200 kHz usually isn't much smaller than what they
could built at 20 kHz! Don't be discouraged. It takes time to
appreciate the differences and to exploit the possibilities of
high frequencies. Usually by the second or third effort the
performance advantages talked about here will begin to
appear.

Table IX. Size/Volume Reduction Tradeoffs
PRO

CON

1. Transformers Smaller
2. RFI Filters Much Smaller
3. Capacitors Smaller

1.
2.
3.
4.

Heat Sinks No Smaller
Semiconductor Packages No Smaller
Auxiliary Circuits No Smaller
Line Holdup Capacitors Only Slightly Smaller

Table X. Cost Tradeolls
PRO
1.
2.
3.
4.

CON

Magnetics Cheaper
EMI Filters Cheaper
Filter Capacitors Cheaper
Power MOSFETs will be Competitive in Cost with Low
Frequency Bipolar

1. Junction Diodes More Expensive
2. HF Bipolar Switches More Expensive
3. Shielding for RFI Required

J
Table XI. Expected Future Improvements
1.
2.
3.
4.
5.

High Current, Low Voltage Film Capacitors
Lower Cost Low trr Diodes
More Practical Transformer Designs
A Good 300 KHz Modulator IC
Wide Variety of Low Cost Power MOSFETs

A034
in Constant-Frequency Current-Programmed Mode",
Proceedings of IEEE Power Electronics Specialists
Conference, June 1979-

BIBLIOGRAPHY
[ 1] E. Buchanan and E. Miller, "Resonant Switching Power
Conversion Technique", IEEE PESC Record, June
1975.

[ 9] A. Capel, "Charge Controlled Conversion Principle in
DC/DC Regulators Combines Dynamic Performance
and High Output Power", Proceedings of IEEE Power
Electronics Specialists Conference, June 1979.

[ 2] E. J. Miller, "Resonant Switching Power Conversion",
IEEE PESC Record, June 1976.
[ 3] R. Severns, "High Voltage Supplies", Proceedings 24th
Power Sources Symposium, May 1970, pages 148-152.

[10] R. Severns, "An Improved and Simplified Proportional
Base Drive Circuit", Proceedings of Powercon 6, May
1979.

[ 4] J. Biess, L. Inouge and J. Shank, "High Voltage Series
Resonant Inverter Ion Engine Screen Supply", IEEE
Power Electronics Specialist Conference, June 1974.

[11] B. Roehr, "Significance of Inductive Switching Specifications", Solid State Power Conversion, July/August
1979, pages 33-36.

[ 5] R. Severns, "A New Current-Fed Converter Topology",
IEEE Power Electronics Specialist Conference, June
1979, Figure 11b.

[12] R. Severns, "High Frequency Switching Regulator
Techniques", IEEE Power Electronics Specialist
Conference Record, June 1978.

[ 6] R. Severns, "General Techniques for Designing New
Types of Switching Regulators", Proceedings of the
European Power Conversion Conference, September
1979.

[13] R. Severns, "The Design of High Efficiency Off-Line
Converters Above 100kHz", Powercon 5 Conference
Record, May 1978.

[ 7] Y. Yu, J. J. Biess, A. D. Schoenfeld, V. R. Lalli, "The
Application of Standardized Control and Interface
Circuits to Three DC to DC Power Converters", IEEE
Power Electronics Specialists Conference, Record,
June 1973, pages 237-248.

[14] S. Feng, T. Wilson and W. Sander, "Very High Frequency
DC-to-DC Conversion and Regulation in the Low
Megahertz Range", IEEE PSCS Record, June 1971.
[15] W. Hetterscheid, "Base Circuit Design for High Voltage
Switching Transistors in Power Converters", Mulliard
Technical Communications#124, October 1974, pages
157-169.

[ 8] S. Hsu, A. Brown, L. Rensink and R. Middlebrook,
"Modeling and Analysis of Switching DC-DC Converters

D~D[b

A035
Switchmode
Converter Topologies Make Them Work for You!
by Rudy Severns
e. The power supply industry is becoming increasingly
competitive. Manufacturers using a poorly optimized
"one circuit for all applications" approach are going to be
pushed out of the marketplace by more aggressive and
versatile competitors.

INTRODUCTION
Recent years have seen a tremendous expansion in the sales
volume and variety of applications for switching regulators.
Surprisingly, if one looks at the circuit arrangements most
frequently used, only a few different types are represented.
The parallel, half-bridge and full bridge quasi-squarewave
circuits and the single ended flyback and feedforward converters represent about 95% of what is available in the marketplace today: A bit of research quickly reveals that there are
many other circuit topologies, both switchmode (modified
squarewaves) and resonant, that are available and which may
be superior to the popular circuits in particular applications.

f. Requirements on the control of EMI are becoming much
more restrictive; the choice of topology can be used to
minimize EMI.
g. It occasionally happens that an individual or organization
will create, a circuit variation that gives a real or imagined
competitive advantage for a particular application. The
normal course is to immediately patent the circuit to deny
its use to a competitor. While the competitor cannot use
the original circuit, he may very well be able to apply the
manipulative techniques shown herein to the circuit to
produce a different and perhaps even better circuit. Conversely, the circuit originator could better protect himself
by manipulating his circuit and extending the patent to all
possible variations.

This application note is intended to provide the switching
power supply designer with a broad view of the switchmode
converter topology options available and to demonstrate
synthesis techniques that should enable the designer to
invent new topologies which may better suit his particular
design problem.

Why We Need New Topologies
Where Do Circuit Topologies Come From?

There are several reasons for considering new or nonstandard circuits:

There are many sources of switchmode converter topologies. The first and most obvious place to look is standard
industry practice. The next source is the published literature
in the field; an extensive bibliography is included atthe end of
this application note. A third rich source is the patent and
patent disclosure files. A search of the patent files can be
tedious, but every so often a really useful circuit or circuit
variation will be found.

a. Increasingly, switchers are operating at higher switching
frequencies to reduce size and weight. It is now completely practical to operate above 200KHz, and while the
more popular circuits will work at these frequencies, they
are by no means optimum. It has been shown 1 that some
not so common topologies have very definite advantages
at high frequencies.
b. Power MOSFETs are rapidly becoming a reality for
switch mode converters. The distribution between switching and conduction losses in a MOSFET is quite different
from those of a bipolar, and the choice of circuit topology
can have a profound effect on the total power loss. Many
of the standard circuits are less than optimum when used
with MOSFET switches.

The next step is to employ synthesis techniques to generate
circuits that do not presently exist. A variety of synthesis
procedures exists, and the discussion of these procedures is
the main thrust of this application note:
By far, the most important source for new circuits is the
deSigner's intuition. The synthesis procedures described
herein have not evolved to the pOint that the designer can
define the desired circuit performance and then follow a
specified synthesis procedure that will lead directly to the
desired solution; and while very useful, 'the present range of
synthesis techniques are still rather clumsy tools that the
designer must guide, using his intuition to reach the desired
goal.

c. The switching power supply designer is limited by the
capabilities of the components available to him. Because
Qf the efforts of component manufacturers, the performance limits change continuously, but progress is slow
and the designer will always be faced with component
limitations. Because the electrical stresses on the individual components vary widely with the topology, the choice
of topology can be used as a tool to get around some of
the limitations in components, and the larger the number
of circuit variations available to the deSigner, the greater
the likelihood that an acceptable solution will be found.

CRITERIA FOR COMPARING CONVERTER
TOPOLOGIES
As will be demonstrated shortly, the literature, patent search
and synthesis efforts produce a large and bewildering array
of circuit topologies. The number of circuits is so large that
there is no way to deal with all of them on a one-at-a-time
basis. What is needed is some orderly means to compare
circuits quickly, to enable the designer to choose the best
circuit for his application. There are several possibilities for
simplifying the comparison process:

d. As switchers find a wider range of usage, more and more
special applications that require optimization of a variety
of different performance parameters appear. To cope with
these applications, the designer needs a wide variety of
circuits to choose from so that really effective designs can
be created.

A035
Converter Topologies Organized Into Families

1. The circuits can be organized into families sharing common characteristics.

It appears that all of the known switching regulators can be
synthesized from combinations of three circuit elements:
The boost regulator, the buck regulator and some form of DC
transformer, as shown in Figure 1. Examples to support this
contention will be given in following sections. This observation suggests a family delineation that derives from the basic
elements from which a particular converter can be assembled.
Figure 2 is a converter family tree that begins with the buck
and boost converters as the most basic elements. As will be
shown shortly, the buck and boost converters are electrical
duals of each other. The DC transformer is not treated as a
starting element but is used as a circuit element to produce
permutations of the basic buck and boost regulators.

2. The figures of merit for different topologies can be compared. The stress on the various circuit components varies
widely from one topology to another. For each topology
and component, a normalized component stress figure of
merit can be developed that relates the individual component stress to the input and output voltages and currents.
3. Figures of merit relating the amount of inductive and
capacitive energy storage required for a given power level
can be derived. These figures of merit are very useful for
weight and volume trade-off studies.
4. The feedback loop and transient characteristics are an
important practical consideration for comparing topologies. The presence of a right half-plane zero in the boost
family of converters is an example of a potential stabilization problem.

The buck derived family shares the common characteristics
of discontinuous input current, continuous output current,
duty cycle, D = Vt/V j , non-moving poles in the transfer function and an internal bus voltage Vb lower than Vj. The boost
derived family shares the common characteristics of continuous input current, discontinuous output current, a right
half-plane zero and moving left half-plane poles in the
transfer function, and an internal bus voltage higher than the
input voltage. The family of converters made up of combinations of buck and boost converters is not so neatly characterized, because of the diversity of its members, but there are
localized generalizations that can be made. Wherever possible, the common name for the particular converter is given.
Since many of the entries in Figure 2 are not generally known,
or do not have specific names, each entry is referred to the
figure number in the following sections where the circuit is
first developed.

5. The component count can be a very important figure of
merit, especially for powers below 100W. In converters
operating below 100W, the component stress is not usually high enough that multiple components or especially
high performance components are needed and the primary objective is usually low cost. As the power level goes
above 1OOW however, it becomes increasingly desirable to
use topologies that reduce component stress levels even if
the component count is higher. The point is that the component count is a very useful figure of merit, but it can be
misleading as the power level is increased.
6. The response of the circuit to component nonidealities is a
useful point of comparison. For example, the switch conduction overlap caused by transistor storage time can be
either harmless or catastrophic, depending on the
topology.

REGULATORS

(A)

m·

DC TRANSFORMERS

I
II(A)

I
I
---------+--------PARALLEL

BOOST REGULATOR

(8)

BUCK REGULATOR

I
I
I(8)
I
I
I
Figure 1

•a

rlll[Lff

S'J----f=l.J
r lS.
5,: fS4
......ll---J.

BRIDGE

OUT

'"
DUALITY

T
SINGLE ENDED
XFMR

FEED FORWARD
«3)

BRIDGE
XFMR

QUASI-SQUARE
HALF-BRIDGE

(XI
~

CURRENT FED
HALF-BRIDGE
(S3)

MULTI-WIND
CHOKE
(59,60)

CUALKIN/HAMILTON
(31B)

32A

32B

33A

33B

COMBINATIONS

BRIDGE
XFMR

OVERLAPPING
«OA)

IBM
(260)

T
HUNTER

SEVERNS
(28C, 90)

(27C)

I I

SECONDARY
SHORT
(37A)

TAPPED
XFMR
(64, 74A, 76)

(37, BiC, 38A
caD,39C)

TAPPED XFMR
(61A, 63B, 78, 800)

FLY SACK

Figure 2

CUK
(53A)

(53B, CaD)

(51B)

SECONDARY
SHORT
(40B)

SECONDARY
SHORT
(84B)

TAPPED CHOKE
(67,75)

TAPPED XFMR
(61 B, 63A, 79
80A, BaC)

TAPPED CHOKE
(66B, 81, 82)

BUCK-BOOST
(5:!.... =Q:

(10)

:!....ID
-D'= Q:
Vg
0'

(11)

Ig Ig
Vg
D
when duty ratio D is referred to homologous point A in Figure
S. However, with respect to pOint 8 ... the DC voltage gain
becomes:
'

"Comparison of the waveforms in Figure 9 shows that the
nonpulsating input and output voltage waveforms of the
buck-boost current converter have been mapped, by the
duality transformation, into the very desirable nonpulsating
input and output currents of the Cuk voltage converter. In
addition to the inductive energy transfer of the buck-boost
converter, there corresponds a dual capacitive energy transfer of the Cuk converter, since ... inductance in the buckboost converter and capaCitors in the Cuk converter are the
only energy transferring devices.
"In fact, it is this duality of (the) energy transferring mechanism which has prompted the search for the complete duality
of (the) switching converter topologies, and subsequently ...
to the establishment of duality as a general concept for a wide
class of switching converters.

fill}

(B)

(C)

(D) Cuk Voltage
Converter

Figure 8: Duality between the Buck-Boost and the Cuk Converters

Figure 9: Comparison of Buck-Boost and Cuk Converters

A035
"This also becomes an important distinguishing feature of
buck-boost converter types which are based on inductive
energy transfer only, and the new Cuk converters which are
primarily based on capacitive energy transfer but ... not
limited to that ... since some of their extensions (such as
coupled-inductor Cuk converter and single inductor Cuk
converter) possess an additional inductive energy transfer."

1. All switches are replaced by diodes phased to conduct
current in the opposite direction from the original switch.
2. All diodes are replaced with switches phased to conduct
current in the opposite direction.
3. If the duty cycle of the original switches is D, then the new
switch duty cycle is D' = i-D.
4. If, for given D, the input voltage is Vi and the output
voltage is V2, the original source is replaced by a load with
a potential of Vi and the original load is replaced by a
source with a potential of V2.
5. For a given D, an original load RL and output capacitance
C, the inverse output load and capacitance is:

Bilaterallnversion**
The duality transformations just discussed can sometimes be
difficult to apply in circuits containing transformers, because
there is no electrical dual of mutual coupling. Although not as
general as the Cuk method, a simpler duality transformation
procedure exists which does not have this problem. It has
been demonstrated 5 • 6, 7 that the common boost and buck
regulators can be made to transfer power from output to
input, as well as from input to output (Le., bilaterally) by the
simple expedient of shunting each switch with a diode and
each diode with a switch. An example of this is shown in
Figure 10, for a boost regulator where Q1 is shunted by D2
and D1 is shunted by Q2. The load is replaced by a source
equal to V2; the requirement that V2 > Vi is retained. Switch
Q2 is ON when Q1 is OFF. This means that if Q1 operates with
a duty cycle of D, then Q2 has a duty cycle of D' = i-D. The
direction of power flow is now a function of D. The procedure
can be carried one step further, as shown in Figure 1DC; Q1
and D1 are removed from the circuit and source Vi is
replaced by a load with a potential of Vi across it.
The circuit in Figure 10C is simply a buck regulator. Again
one sees the duality between the buck and boost regulators.
The rules for bilateral inversion are as follows:

R'L = RL(~~t

c' = c

(~~)2

6. For particular D, Vi, V2 and output power, the value of
Lcritical is unchanged.
The diodes and switches referred to in rules 1 and 2 are only
those directly involved in the power conversion process, not
those acting as snubbers or other control function.
This inversion process is general, and can be applied to a
wide variety of more complex converters. This provides a tool
by which new circuits can be derived from known circuits. An
example of this procedure for a more complex cicuit is given
in Figure 11; the circuit in 11A is a well known voltage-fed
configuration (sometimes referred to as a quasi-square wave
converter); Figure 11 B is the circuit after bilateral inversion is
applied. This circuit is a form of a symmetrical transformer
coupled boost regulator, in which the switches conduct
simultaneously for part ofthe cycle. A switch timing diagram
for circuits A and B is shown in Figure 12.

~~2

(A)

~
02

(8)

+
V1

RL'

Je.

Figure 11

(C)

Overlapping Conduction
The use of overlapping switch conduction is not seen very
often in present converters, because in many circuits the
results are catastrophic. However, in some converters, overlap is not only harmless but can be useful as shown by the
example in Figure 12.

Figure 10

"Portions of this section were originally published in the proceedings of the
European Power Conversion Conference, 1979. 10

A035
to this particular topology but can be used with many other
circuits. Figure 16 shows an example where a well known
current-fed converter can be made to operate as either a
buck, boost or buck-boost converter simply by altering the
switch sequence. If a large capacitor is connected from input
to output and the switches sequenced for buck-boost operation, the circuit will act as a single inductor Cuk converter.

In many (usually only current-fed) circuits, overlappng and
non-overlapping operation may be combined to enhance the
circuit's operation. Figures 13, 14and 15show an example of
such a circuit.
Non-overlapping, Mode A (Figure 14), operation prevails for
Vi?' Vb' During STATE I, energy is drawn from the source and
then delivered to the load and stored in L. In STATE II, S1
opens and the energy stored in L is delivered to the load.
During Mode A, the input current is discontinuous and the
load current is continuous.
Ove'rlapping, Mode B (Figure 15), operation prevails for Vi::;
Vb' During STATE I, energy is drawn from Viand stored only in
L. During STATE" the energy stored in L is discharged Into
the load. In this mode the input current is continuous and the
output current is discontinuous.
By controlling the switches appropriately, it is possible to
design a converter that is a boost regulator at low line voltages and buck regulator at high line.
The foregoing example shows how the basic nature of the
converter can be altered, by changing the switch sequence
without changing the topology. This technique is not limited

I-

«
Z

t: *.........,

off
on

C
Z

;::

::J

PWM

off
on

I-

'"0

Interchange of Switch Connections
Figure 17 shows four common rectifier connections. It is well
known that anyone of them can be used on the transformer
output, simply by altering the transformer secondary turns
and the diode current and voltage ratings. If bilateral inversion is applied to each of the rectifier connections, the result
is the switch connections in Figure 17(E-H).
Note that there are a large number of rectifier connections
used in practice, but relatively few switch connections. The
bilateral inversion principle can be applied to these rectifier
connections to generate new switch connections.

off
on

off

T/2

TIME

Figure 13

Figure 12

81 PWM

~;.

,-.....t-..,............,r--.... +
Vo

(A) STATE I

(A)

PWM

STAT~

I
81

L-.4--+--+-----,-{1

L-~-+---+-_---";;-ll ~;.
04

(8) STATE"

Figure 15

Figure 14

A035
SYNTHESIS USING OC TRANSFORMERS AND
BUCK OR BOOST REGULATORS

The circuit in Figure 17C is a voltage doubler. Another form
of doubler is shown in Figure 18A. If this connection is
inverted, the switch connection in Figure 188 which results is
an alternative to the popular half bridge. This variation is
rarely seen in practice but should be useful.
The next step up in this process is to invert a voltage quadrupler, as shown in Figure 19. In the case of the inverted
doubler, the switches see the line voltage and twice the line
current. For the inverted quadrupler, the switches see onehalf the line voltage and four times the line current. This
connection would be useful for very high voltage busses. The
circuit divides the line voltage across the switches naturally,
without the need for complex device matching or voltage
sharing networks.

A wide variety of converter topologies can be synthesized by
using a combination of a boost or buck regulator and some
form of DC transformer. Tile DC transformer can take a wide
variety of forms, two of which are shown in Figure 20. The
function of this circuit element is to provide voltage and
current level transformation, either up or down, within the
regulator. For the purposes of this discussion, the switches,
transformers and diodes are assumed to be ideal.

The Buck Derived Family of Converters
Asastarting point let us begin by combining the buck regulator with a parallel connected DC transformer. The buck regulator circuit will be progressively opened at points A through

11[fl] fSJ

(A)

(8)

Mode A, Buck Regulator
S3 = PWM, 81 and $2 = 50% conduction

Figure 18

Mode S, Boost Regulator
83 = always ON, $, and $2 = overlapping PWM
Model C, Buck-Boost Regulator
STATE I.
82, 83 ON
STATE II, $2 ON, 5, and S3 OFF

$,.

(A)

II'I

II~-t-_ _t - - - - j

Figure 16
INVERSION

~!!(E)
:f¥l"

(8)

'len tOO
II"

"II .

-=-

"q;u I~

I
I-=-

(8)

II
II

I: (F)
II
"

Figure 19
DC TRANSFORMERS

: I (G)
II

I
I

PARALLEL

I'~ i~
"
I

(0)

I-=-

I
I

" (H)

BRIDGE

I
Figure 17

Figure 20

O~O!L

A035
E, and the DC transformer inserted as shown in Figure 21.
When this is done, the group of circuits in Figure 22 is generated. Figure 22A is simply a pre-regulator DC-DC converter,
22B is a current-fed DC-DC converter, and 22C and Dare
essentially identical because the diodes are not needed for
the circuit operation. Here is a new circuit apparently, but as
will be shown shortly it simplifies into one well known. Figure
22E is a DC-DC converter driving a post-regulator. Circuits
22A and E are dead ends, but 22B and C can be modified to
1 PWM 1

1=1

(A)

~~--~

-=. 1

1
1

(8)

:=@IIB=

Figure 23

50%

Figure 21

110=0

50010

(A)
(A)

'B,mIICHTD
[)

(8)

PWM

(C)

&
(0)

(E)

c$I03?n

(C)

Figure 24

Figure 22

form a variety of circuits. 53 in 22C is really redundant, its
function can be performed by 51 and 52. This results in the
circuit in Figure 23A, which is the common parallel quasisquarewave converter. If a bridge rather than a parallel DC
transformer had been used, the bridge form (Figure 23B) of
the quasi-squarewave converter would have resulted. Figure
23 can be modified in a wide variety of ways; Figures 24 and

25 show some variations using saturable reactors for fixed
frequency (Figure 24) and variable frequency (Figure 25). A
host of other variations is possible.
The circuit in Figure 21 B also provides a wide variety of
variations, beginning as shown in Figure 26. One starts with
A, and then in B, 53 is shifted to the negative lead of the

O~OIL

A035

causes a large current spike to be drawn through 53. In the
circuit in Figure 26D, the current in diodes D1 and D2 is
com mutated by opening their respective series switches, so
that when the voltage is reversed across the diode only a very
small current spike is present. For high voltage sources the
circuit in Figure 26D is very useful, because 83 and 54 see no
more than the line voltage and 81 and 82 see only twice the
reflected voltage, Vb, which can be made low. For low voltage
sources the circuits in Figure 26 are at a disadvantage, however, since there are two switches in series during part of the
switching cycle which reduces the efficiency. The circuit can
be modified as shown in Figure 27. As before, 81 and 82
conduct alternately, each with 50% duty cycle, and 53 and 84
are modulated. In this circuit the current only flows through
one switch at a time, because D1 is reverse biased while 83 is
ON; the same applies to 02 and 84 on the other half cycle.
The penalty for increased efficiency is that now 83 and 84 will
see the line voltage plus twice Vb.

(A)l~5o%nI18=n
~.rPJ

(C)cSll~

s,
Figure 25

source. In C the connection between 81 and 82 is broken and
84 and 02 added. The result is Figure 26D, which is another
current-fed converter. Despite the additional diode and
switch, this circuit has some advantages; the PWM switches
are referenced to the ground node, the input power is now
shared by two transistors instead of one, 100% duty cycle in A
corresponds to 50% duty cycle in B. The current in D1, Figure
26A, is com mutated by reversing the voltage across the devices. In real devices with finite reverse recovery times, this

50%

(A)

(A)
PWM

50%

r- -

- -..,

.IIS=U

(8)

L _ _ _ _ ...J

PWM
S.

(8)

Figure 27

The circuit in Figure 27C can be modified as shown in Figure
28, by using a dual winding choke. This circuit can be further
modified, as shown in Figure 29, by connecting one choke
winding and the inner switches and diodes to the output. In
making this modification, 81,82 and 02 are no longer necessary; This results in Figure 29C, which is a two switch
current-fed converter with the properties of a buck regulator
with DC isolation and arbitrary output voltage.
Instead of separate windings on the choke, a tapped winding
may be used to produce the variations in Figure 30.
If, in the beginning, a bridge connected DC transformer had
been used instead of one which was parallel connected,
slightly different circuits would have resulted. For example,

50%
50%
Figure 26

A035
PWM
S,

liEF

(A)

BOOST ONLY n:51

liEF

~B)

(8)

BOOST ONLY n;;, 1

~8B
PWM

Figure 28

Figure 30

PWM
S,

(A)

r------...,

__-c-_~I__

(B)

~:II8P

(8)

I
L _______
L ______________

50%

11e=u

Figure 31

By a process of simple manipulation, and combining a buck
regulator With a DC transformer, a family of converter circuits
has been derived which are all clearly related and, despite
differences in the circuit connection, have in common the
properties of the buck regulator. Most of the circuits derived
in this section are relatively well known, but in the next section the process will be repeated for the boost regulator; and
this will result in a number of circuits that have not been seen
before.

(C)

Figure 29

instead of the circuit in Figure 31A, one would have the
variation in Figure 31 B. This circuit can now be modified, as
was done in Figures 26 and 27, to produce the variations in
Figure 32. Using a bridge connection, Figure 29 becomes
Figure 33A, which is a current-fed bridge inverter. With a bit
more manipulation, the circuit in Figure 33B can be derived.

The Boost Derived Family of Converters
An entire family of converters with boost properties can be
generated by combining a boost regulator with a DC transformer. As before, the DC transformer will be sequentially

A035

(A)

(8)

l~~ffD

(A)

[1j:

rr:~
1 -F1:II8TI

(8)

5;
I
I

.:Blla='~
Figure 34
50llfD

(A)

Figure 32

50%

=R1

(8)

(A)

(~)H~

s,
5,

v.
v.

50%

11s±n
0,

50%

II~

(D)

11MlJ]

(8)

50%

Figure 33

(E)

inserted into the regulator (Figure 34). The results of this
combination are shown in Figure 35. A is a boost preregulator followed by a DC-DC converter. In Band C, the
diode D1 serves no function, and can be omitted to form a
new circuit. This is a current-fed converter, modulated by
periodically shunting the primary. In D, the control element is
shifted tei the secondary, and the modulation is accomplished by shorting the secondary, again we have a new
circuit. The circuit in E is simply a DC-DC converter with a
boost post-regulator.

.-------------o-+-~I C¥?'~ ¥ ~
50%

Figure 35
50%

(A)

~:liP
50%

The function of 53 in Figure 36A can be performed by 51 and
52 if 51 and 52 are allowed to have an overlapping conduction interval. This is another way to derive the circuit in Figure
11B.
The circuit in Figure 35D is a usable converter, but it suffers
from the disadvantage of having the output current pass
through two diodes in series. An alternate and more efficient
connection is shown in Figure 37B, where the load current
flows through only one diode. The ultimate is reached in
Figure 37C, where D1, D2 and 53 are moved to a separate

Figure 36

D~DI!:.

A035

winding, which can be proportioned to provide the optimum
voltage and current for 83 independent of the output voltage.
This is a particularly interesting circuit that allows isolation
between source,load and control loop. The power chopping
is done on the primary, but the control is in the secondary,
eliminating the need for isolation within the control loop.
Like the buck family, these circuits also have many variations, as shown in Figures 38 and 39 for saturable reactor
control, and Figure 40, for bridges.

'A)r:k3II~
(8)

(A)

eGJ
50'10

,e)

(0)

Q)~ gll8TI

Figure 37

(A)

(0)

r: GJ~Ef=D
~~PWM
r: .QJ~Ef=D

(C)

Figure 39

(A)

'D)L98TI

(8)

ITJ
PWM

Figure 40

Figure 38

A035
Single Ended Converters

not really useful, but as will be shown shortly, a minor modification will make it most useful. Both circuits lack one
important ingredient, a means for resetting the core. The
family of feed forward converters is quite large, but the differences within the family are related to the means by which
the core is reset. The basic energy transfer is identical, even
though the circuits may look very different.

For many applications, low component count is of paramount importance; the family of single ended converters is
usually preferred for simplicity. By using a boost or buck
regulator combined with a single ended DC transformer, as
shown in Figures 41 and 42, if the parallel or bridge DC
transformers are divided in half, the result is single ended DC
transformers. If these transformers are combined with a
buck regulator in manner such as the quasi-squarewave
converter, the feed forward converter is the result, as shown
in Figure43. Figure43B looks a bit strange, and inthisform is

The designer has two choices (Figure 44); he may select a
core which has a low Br and which will self discharge or he
may select a very square core with little energy storage and
then reset the core externally.
In the case of self-resetting, the energy may be dissipated in
the primary or secondary (Figure 45), or recovered in the
primary or secondary, as shown in Figures 46 and 47.

(A)

(8)

Figure 41

(B)

--+f+---H

(B)

Figure 44

Figure 42

(A)

OIItTJ1

(A)

(B)

~IJ'
U' II~

(B)

Figure 45

Figure 43

A035
(A'

cfjlltrn

(A)

(8)

(C)

D'
r::c:n
T
OJ
~

OII(8)n

(C)

[iIIP31

Figure 46

Figure 49

(A)

Figure 41

Where a square loop core is used. external current reset can
be provided as shown in Figure 48. The current supplied by a
DC source as in A. or better yet. derived from the output
choke. as in B. These types of current reset do not define the
winding voltage during reset. A variety of voltage clamps for
current reset can be used as shown in Figure 49.
(8)

(C)

(8'DIIP:Jl
Figure 50

Figure 48

A035
The quasi-squarewave converter is not the only member of
the symmetrical converter family that has a single ended
equivalent. As shown in Figure 50B, the Weinberg circuit
(Figure 29C) is another which can be single ended. Again, the
core reset means is omitted, and the designer is free to select
the reset scheme and core of his choice. Figure 50C is one
possible example.
Single ended versions of symmetrical boost converters can
also be derived, as shown in Figure 51 where A is converted to
B. To maintain current continuity in the choke, the duty cycle
of S1 is now the complement of 53.

(A)

(8)

:0=0==0=

OUT

(A)
Figure 52

Figure 51

(A)

N:O

(B)

[T){]]

Limitations On This Procedure
It has been demonstrated that inserting a DC transformer
into a buck or boost converter can produce a wide variety of
useful topologies. The procedure does not, however, work
for all regulators and all DC transformers.

(e)

For example, if a parallel connected DC transformer is
inserted into a Cuk converter, most of the combinations will
not work. This is because the Cuk converter requires a bidirectional flow of current to function, and the usual switch in
the primary, rectifier in secondary DC transformer connection does not permit this. The designer must be on the lookout for this problem. For some circuits the single ended DC
transformer does not provide for continuous current flow in
the inductor, so that such variations don't work.
Even with these restrictions a huge number of circuits can
still be developed.

(0)

tl~

~~
Figure 53

SYNTHESIS USING COMBINATIONS OF
CONVERTERS
A very powerful technique forderiving new circuits is to treat
buck and boost regulators and the DC transformers as two
port networks, and then combine these networks in various
arrangements.
A few of the many possibilities are shown in Figure 52. Beginning with A, similar or dissimilar converters can be cascaded. An outstanding example of this process is the Cuk
converter (Figure 53A) which was initially derived by cascading a boost followed by a buck regulator. This topology has
several important variations, as shown in Figure 53B, C and D.

The Cuk converter has the unusual property of zero input or
output ripple in the coupled inductor case. By an additional
circuit permutation, it is possible to have zero current ripple
on both the input and the output. Figure 54 shows one way to
accomplish this. A is the basic circuit. In B, C is divided and
an inductance L is added. In C, the three inductors are
coupled. Zero input and output ripple is achieved by adjusting the mutual coupling between the windings or by using
trimming inductors. 37 Figure 55 shows some other variations
to achieve the same goal.

O~OIL

A035
(A)

r----<>'o

r~TJ

(A)

II~

f !

(8)

r!fTTJ:

(8)

(A)

Figure 54
Ll

(A)
(8)

~llL2~

l L:1J

(8)

fr:r
L2

(e)

I
•

(C)

Figure 57

(Figure 57B). If duality is applied to these two circuits, the
arrangements in Figure 57C and 0 are obtained.
Identical converters can also be cascaded with useful results.
An example of this is given in Figure 58. The input to output
voltage transfer ratio is:

Figure 55

It can be shown that the common buck-boost regulator (Figure 56A) circuit may be derived from a cascaded connection
of a buck followed by a boost regulator. By the simple expedient of using a multiple winding choke, the popular flyback
converter is derived.
A cascade connection of a boost and a buck-boost is shown
in Figure 57A. This can be transformer isolated in the same
way as the flyback, by making L2 a multiple winding choke

..YJ = (o)n

Vo
This circuit connection can be very useful when large transformation ratios are desired. Using a single buck stage for a
large transformation ratio results in very narrow, high amplitude current pulses which restrict the power handling capability of the switching device. This is a very real limitation in
off-Une converters. By cascading two or more converters. a

A035

O~O[b
The concept of tapping the inductor may be extended to the
use of multiple windings. It has been shown that the multiple
wound inductor can be used in place of multiple inductors, as
shown in Figure 61, with a significant savings in size and
weight.
A circuit using a two winding choke can also be used to
reduce the size of a filter capacitor as shown in Figure 62.
Figure 58

larger duty cycle is used which reduces the current amplitude. For example, a converter using a single stage operating
with a duty cycle of 0.1 would have a duty cycle of 0.32 if
changed to two stages, a three to one reduction in peak
current! A second benefit is that 82 would see only 32% ofthe
input line voltage, and could be a less expensive device than
81.
Paralleling of converters (Figure 528) is another very useful
way of increasing the power capability. 8y altering the switch
drive phasing between the converters, the output ripple frequency can be increased and the amplitude decreased.
Cascading and paralleling are not the only possibilities. An
example (Figure 52C) of connecting the inputs of two converters in parallel with their outputs in series is shown in Figure
59A. This is a combination of a DC-DC converter and a
flyback converter. If bilateral inversion is applied to A, then
the circuit in 8 results; another way to derive the circuit in
Figure 29C.
The possible combinations are endless and really limited
only by the designer's imagination and persistance.

(e)

1 I

(D)

T J II ~
'j

1 I

I
J

1°
T J

(E)

(F)

1::

1°
T J
Figure 60

Figure 59

limitations to the Procedure
Not all of the possible four terminal combinations yield working circuits, and general rules as to what will or will not work
have not yet been derived. The designer must, for the present, use a cut and try approach.

Figure 61

SYNTHESIS USING TRANSFORMER AND
INDUCTOR TAPPING

II r--.*-~~-"'UJ..r--....,
II
II
II

A very simple way to modify known circuits in useful ways
employs tapping of the inductor and/or transformer.

ll~---+---~--"
I:

II
II ............'1-....1

Inductor Tapping
One of the simplest modifications is to tap the inductor to
alter the component voltage or current stress, as shown in
Figure 60.

Figure 62

A035
Transformer Tapping
The transformer may be tapped to provide'very useful circuit
variations. Figures 63 and 65 show some examples. The
quasi-squarewave circuit has an output voltage waveform
(before the filter) like that shown in Figure 64A. This waveform has a very high harmonic content which must be dealt
with by the filter. If the quasi-squarewave circuit is modified
to have a tapped primary with two additional switches, as
shown in Figure 63A, the output waveform can be made to
look like that shown in Figure 648, with the difference
between V1 and V2 determined by the tapping ratios. This
waveform can have a much lower harmonic content, which
allows the size of the filter to be reduced. Similarly, the input
current will also have a lower RMS value, which is of great
assistance in reducing EMI. These circuits and some ofthose
in the following section allow the designer to trade circuit
complexity for reduced EMI. The disadvantage of these circuits (in addition to the extra switches) is thatthere is now an
upper as well as a lower limit on the line voltage that can be
accommodated, for a given tapping ratio. For applications
where there is not a large line voltage excursion, the reduction in filter size may be very worthwhile. Figure 638 is a dual
of 63A.
(A)

Figure 65A is a boost derived circuit using the same principle
(S1 and S2 do not overlap); Figure 658 is the dual of this
circuit. The bridge versions of these circuits are shown in
Figures 66 and 67. This process can be extended by adding
2n additional switches so that the voltage and current ripples
approach a sinusoid.

(8)

~~-fl__~

~;.

(8)

Figure 65

~I~

50%

Figure 63

(A)
Figure 86

:b 0 D
(8)

50%

Figure 67

Figure 64: Converter Output Voltage Waveform

100

U~UlL

A035
Combined Choke and Transformer Tapping

SUMMARY

Tapping of both the choke and the transformer can be combined in one converter. An example ofthis is shown in Figure
68A, along with its dual, 68B. By tapping the choke, the
output current becomes continuous and the input discontinuous. Figure 69 shows the bridge version of Figure 68A.
By tapping the inductor and transformer in the circuit in
Figure 70A, the circuit in 70B is generated. This circuit has
the advantage of reducing the current in 01 and 02, increasing the circuit efficiency while retaining the continuous output current and current-fed converter nature. This particular
combination of tapping does not have the upper limit on
input voltage.

A wide range of ideas and techniques, many of which are
new, have been presented herein. So much has been presented that the reader may find it difficult to see the forest as
opposed to the individual trees.
The key ideas that have been presented are:
1. The present popular circuits represent only a small portion of switch mode converter possibilities. The popular
circuits are not the only, or even the best, solutions.
2. The designer is not restricted to using the present known
converter circuits but can, by modifying the known circuits and synthesizing new ones, derive new circuits to
better solve his problem.

(A)

3. All of the converter topologies we presently know can be
derived from combinations of very simple elements; the
buck and boost regulators and some form of DC transformer.
4. Converter topologies can be grouped into families with
similar characteristics. One way to perform this grouping is to define the family members on the basis of the
basic circuit elements from which the individual circuits
are derived.

(B)

5. General duality theory can be applied to switch mode
converters to provide both insight into circuit relationships and a synthesis tool.
6. A special case of duality, bilateral inversion, leads
directly to the use of overlapping and non-overlapping
conduction and combinations thereof to alter circuit
operation.

Figure 68

7. Bilateral inversion also leads to using rectifier connections as switch connections. This can be extended to
multiplier and possibly multiphase connections.

50%

50"10

PWM

8. Quantitative figures of merit based on component stress
and energy storage, and qualitative circuit considerations can be used to compare circuits. Comparisons of
large numbers of circuits, in fact, require the use of some
orderly process .

..%

9. There are several techniques for modifying known circuits or generating new circuits: duality, bilateral inversion, combinations of boost or buck regulators with DC
transformers, combinations of more complex converters, transformer and inductor tapping and, of course,
combinations of all these techniques.

50%

Figure 69
PWM

(A)

115aIEP

10. The designer is free to choose many of the circuit properties, for example: the regulation function may be performed in either the primary, the secondary or in an
isolated winding. The control loop transfer function can
be altered to either add or remove moving poles and right
half-plane zeros. The high current ripple can be moved
from the primary to the secondary or vice versa. Both
primary and secondary ripple can be reduced at the
expense of input voltage range or circuit complexity. By
altering the switch conduction modes, the input voltage
range can be greatly extended.

PWM

(8)

Figure 70

101

A035
APPENDIX I
Effect of Waveform on RMS Value
In a switch mode converter, the current waveforms through
the inductors, transformer windings, rectifiers and switches
will appear, as shown in Figure 72, ranging from a triangle to
a rectangle depending on the value ofthe averaging inductor
and the load. For the capacitors, the waveforms will be similar, except that there can be no DC component, as shown in
Figure 73. The RMS and average values of the waveform are
given in the figures.
It can be shown that:
K == ~ =f(L/Lcl
(1)
Ib
where, L = inductance of the averaging choke
Lc = is the critical inductance for a particular input
voltage and load power.
As L is increased, K goes from 0 (triangle) to 1 (rectangle).
Substituting K = I all b, forthe continuous choke current case:
21aV9

K2+ K + 1

3 (K + 1)2

Irms= - -

General Case
IRMS

-= {

0 ['82

la~b

+ Ib2 _

~(Ia

+ Ib)2] }

D=y
Special Cases

(2)

1)0

=1
= Ib 'I:~2~a

IRMS

2) I.

= Ib
=

IRMS

../15-':::-02

3) I, = 0

~
= Ib-VT
- 4

IRMS

11 c1
•

Figure 73: RMS Value of AC Component of Trapazoidal Waveform

For constant lavgand D, the normalized (I rms= 1 for K = 1) I rms
is as shown in Figure 74. This curve shows that, for triangular
waveforms, the 12R losses are 32% higher than for rectangular waveforms. It is also apparent that for I all b > 0.6, the

General Case

IAVG

= 0 (IB ; Ib)

IRMS"'"

[~( la 2

lalb

1.16

Ib 2 )] %

1.14

1.12

Special Cases
1) 0

IAVG = 18 ;
1

RMS

(18 2

1.10

lb.-

lalb
3

1.08

+ Ib2 ) Y,

\\
\
\.

1.06

2) la = Ib

IAVO = laD
1.04

IRMS = 18 Vi)

""i'.. r--..

3) I, = 0
'AVG

1.02

IRMS = ' b f f
~

K" 1..'lb

Figure 74

Figure 72: Average and RMS Values for Trapazoidal Waveform

102

A035
additional losses incurred by having L <0:: is only 2%, so from
a practical point of view L need only be about twice Le.
Increasing the value of Iallb increases the switch turn-on
losses but decreases the turn-off losses. Since the turn-off
losses usually dominate, increasing Iallb reduces the total
switch loss also.

(A)

For the case of discontinuous inductor current (L < Lcl, la/l b
= 0 and is no longer relevant, since the waveforms are now

triangles. For a given lav9 the RMS current is:
I

,ms

= 21av9

(3)

I/3D

A plot of equation (3) is given in Figure 75, where lav9 is
constant and I ,ms is normalized for D = 1. Obviously triangular current waveforms with high peak currents and low duty
cycles are to be avoided if low losses are desired.

For the case where: I a = I b:
I,ms=

lav9

the curve in Figure 75 also applies. It is important to realize
that for a given input voltage, current and transformation
ratio, there can be a difference in duty cycle which allows one
circuit to have lower losses due to the lower value of I,ms.

(8)

50%

IRMS (N)V1r

I. WI '" Conatant

50%

\
1\

Figure 76

" I'--r- r--

The circuits shown in Figures 63 through 69 have a number of
additional variations. When the input voltage range is 2:1 or
less, one switch may be eliminated as shown in Figures 76
and 77; the switch connections can also be varied as shown in

r--

50%
~

DUTY CYCLE

Figure 75: Variation of RMS Current with Duty Cycle.

APPENDIX II
Despite the huge number of circuits presented in the main
portion of this application note, there are still many more that
could be shown. To provide the reader with as full a picture as
possible, some additional circuits are presented here with
limited comment.

Figure 77

103

A035

O~OIL

(8)

Figure 80

(A)

~
_

Figure 78

50%

~fl
PWM

....

(8)

....
.....

;

,....

...
Figure 81

Figure 79

Figure 85 shows a variation on the quasi-squarewave halfbridge that is occasionally seen. The bridge version is also
possible. The major disadvantage of this circuit is that the
inductor must operate in the discontinuous mode. Two more
useful variations of this circuit are shown in Figure 86. In A,
51 and 52 use nonoverlapping conduction, and in B, the PWM
switch is in the secondary. Bridge versions of both these circuits can be built, with and without dual chokes.

Figures 78 and 79. Some of the duals of this family of converters are given in Figures 80 and 81 and there are also multiple
winding versions of these circuits as shown in Figures 82
and 83.
Multiple transformer windings can also be used to reference
all the switches to one node, as shown in Figure 84. The extra
transformer winding may be cheaper than separate basel
gate drive isolation transformers, however, there will be some
voltage spiking due to leakage inductances between the
primary windings.

The circuit in Figure 87 is a variation of that previously given
in Figure 51 B. In this variation, T1 is designed to store energy
while L 1 is discharging through the transformer into the load
(51 open, 52 closed). While energy is being stored in L 1 (51
closed, S2 open), the transformer discharges into the load. If

104

A035
PWM

(A)

+
(8)

sJr
PWM

Figure 84

(0)

iEll~

Figure 85

(Al

s,
PWM

Figure 82

(~eu

(~5:IH
Figure 83

Figure 86

105

Figure 89A shows a circuit in which two converters have
parallel inputs and series outputs. All the switches operate
with 50% duty cycle, and modulation is accomplished by

(8)

---.,.---'
D

(~::I"--------"'~

I·D

Figure 87

the inductances of L1 and T1 are proportioned correctly, the
output current waveform shown in B will result. This has a
much lower RMS value than the original circuit and can be
made arbitrarily small by increasing the inductance value.
This is potentially another low EMI converter circuit.
There are many other combinations of converters. In Figure
88, a buck regulator with continuous inductor current and
pulse width modulation is combined with a buck-boost regulator having discontinuous inductor current and variable frequency. The two are combined with PWM and variable frequency control loops to produce a converter with a single
switch and two independently regulated outputs.

(A)

(8)

Figure 89

varying the phase between the two converters. This can be
done with n such converters to synthesize an output waveform. The circuits in Figures 24A and B can be built with one
magnetic element instead oftwo, if a dual core transformer is
used as shown in Figure 90.
The circuit previously shown in Figure 27C has some duals as
shown in Figure 91B and C.
The circuit in Figure 28C can be reconnected to be similar to
that of Figure 26D as shown in Figure 92.
A variation using a tapped choke is shown in Figure 93A. This
circuit is interesting in that some of the energy stored in the
inductor is returned to the source ratherthan to the load. The
circuit has the unusual property that at certain duty cycles
more power is pumped back into the source than is delivered
to the load, and the sign of the feedback loop inverts! Possibly, this is an example of a pole moving into the right half
plane. The circuit will also work whether or not the switches
have overlapping conduction. If this circuit is inverted (B),
the boost version which results also displays similar bizarre
behavior.

'fTIl
CO}

(e)

Vo '

Vo'

Figure 88

Figure 90

106

A035
(A)

(B)

f?3

(B)

t~J

Figure 93

A few of the circuits previously shown (Figures 30e, 46A, 47,
49A, 50, 86 and 94) also return energy to the source, and it is
conceivable that all these circuits can display this type of
instability. In some cases, this can be prevented by limiting
the stored energy, but not always.

Figure 94

(A)
Figure 91

PWM

S2L

50%

(B)

~II

~"
03

liEF

PWM

Figure 95

S~
PWM

ACKNOWLEDGEMENT
!S4
50%

The author would like to express his appreciation to Dr.
Siobodan Cuk for allowing the reprinting of a portion of his
PESe '79 paper and to Ed Bloom of Litton Guidance and
Control and Trey Burns of Digital Equipment Corporation for
reviewing and commenting on the manuscript.

Figure 92

107

A035
BIBLIOGRAPHY

14. B. F. Farber, A. D. Schoenfeld and P. A. Thollot, "Power
Processing System for a 200W Communication Satellite Transmitter," International Conference on Satellite
Communication Systems Technology, 7-10 April 1975.
15. B. Farber, D. Goldin and F. Gourash, "A High Power
TWT Power Processing System," IEEE Power Electronics Specialists Conference Record, June 1974.

This bibliography is organized in a rather different manner
than is usual. I n addition to the normal source reference that
appears as the text proceeds, there is a listing of references
by figure numbers. Foreach figure where the author is aware
of a prior source or reference, these references are given.
Those figures for which no reference is given are, to the best
of the author's knowledge, his original creations or are circuits in common use whose original source is obscure.
1. R. Severns, "The Design of Switch mode Converters
Above 100kHz," Intersil Application Note No. AO-34,
January 1980.
2. S. Cuk, "General Topological Properties of Switching
Structures," IEEE Power Electronics Specialists Conference Record, June 1979.
3. C. Desoer and E. Kuh, "Basic Circuit Theory," McGraw
Hill,1969.
4. Balabanian and Bickart, "Electrical Network Theory,"
John Wiley & Sons, 1969.
5. G. Cardwell and W. Neel, "Bilateral Power Conditioner," IEEE Power Electronics Specialists Conference Record, June 1973, Pages 214-221.
6. H. Matsuo and K. Harada, "New DC-DC Converters
with an Energy Storage Reactor," IEEE Transactions on
Magnetics, Vol. MAG-13, No.5, September 1977, Pages
1211-1213.
7. R. D. Middlebrook, S. Cuk and W. Behen, "A New Battery Charger/Discharger Converter," IEEE Power Electronics Specialists Conference Record, June 1978.

Figure 26D
16. H. Higuchi and L. Trubell, "Regulating Electric Power
Circuit Arrangement," U.S. Patent No. 4,025,863, 24
May 1977.

Figure 27C
17. I. Hunter and W. Fitzgerald, "Regulated Direct Current
Supply Circuit with Energy Return Path," U.S. Patent
No. 3,432,737,11 March 1969.
18. A. de la Lastra, "Power Converter for Converting an
Unregulated DC Input into a Regulated Output Voltage," U.S. Patent No. 3,388,311,11 June 1968, Figure 1.

Figure 29C
19. A. H. Weinberg, "A Boost Regulator with a New Energy
Transfer Principle," Proceedings of the Spacecraft
Power Conversion Electronics Seminar, September
1974, ESRO Publication SP-l03.
20. J. Biess, D. Cronin and W. Dudley, "Power Processing
Module for Military Digital Equipment Power Subsystem," IEEE Power Electronics Specialists Conference
Record, June 1977.

REFERENCES BY FIGURE NUMBER

Figure 30C
21. B. Israelsen, J. Martin, C. Reeve and V. Scown, "A 2.5KV
High-Reliability TWT Power Supply: Design Techniques
for High Efficiency and Low Ripple," IEEE Power Electronics Specialists Conference Record, June 1977.

Figure 11B
8. P. W. Clark, "Converter Regulation by Controlled Conduction Overlap," U.S. Patent No. 3,938,024, 10 February 1976.
9. R. Severns, "A New Current-Fed Converter Topology,"
IEEE Power Electronics Specialists Conference Proceedings, June 1979, Figure 5.
10. R. Severns, "Techniques for Designing New Types of
SWitching Regulators," European Power Conversion
Conference Record, September 1979, Figure 4.

Figure 31B
22. E. T. Calkin and B. Hamilton, "A Conceptually New
Approach for Regulated DC-to-DC Converters Employing Transistor Switches and Pulse Width Control,"
IEEE Industry Applications Society Annual Meeting
Record, 1972, pages 485-494
23. J. Millman, "Designing High Performance Power Converters for an Airborne Radar TWT Transmitter," Solid
State Power Conversion, November/December 1978,
pages 60-65.
24. E. T. Calkin, B. H. Hamilton, and F. C. La Porta, "Regulated DC-to-DC Converter with Regulated Current
Source Driving a Nonregulated Inverter," U.S. Patent
No. 3,737,755 issued June 5,1973.

Figure 13
9. Ibid .. . Figure 1.
10. Ibid ... Figure 5.

Figure 24C
11. A. Levy, "The Use of Magnetic Amplifier Pulse Width
Modulators in High Frequency DC-DC Converters,"
Power Electronics Specialists Conference Record,
June 1976.
12. A. Levy, "Simplifying Pulse-Width-Modulation with Mag
Amps," Solid State Power Conversion, August 1975.

Figure 39A
25. W. T. Porter, "Frequency Modulated Switching Regulator," IEEE PESC Record, June 1979.

Figure 26A

Figures 46A and 47

13. D. Cronin, B. Farber, H. Gehm and D. Goldin, "Multiple
High Voltage Output DC-to-DC Power Converter," U.S.
Patent No. 4,034,280, 5 July 1977.

26. K. VanVelthooven and H. Koppe, "Low Cost Forward
Converters Ease Switching Supply Design," Electronics February 2, 1978, pages 119-123.

108

A035
Figure 57A

Figure 48
27. M. Lilienstein and R. Miller, "The Biased Transformer
DC-to-DC Converter," IEEE Power Electronics Specialists Cunference, June 1976, pages 190-199.

43. Private correspondence R. D. Middlebrook to R. Severns, September 10, 1979.

Figure 57B

Figure 49B

44. R. P Massey and E. C. Snyder, "High Voltage SingleEnded DC-DC Converter," IEEE Power Electronics Specialists Conference, 1977 Record, pp. 156-159.

28. U.S. Patent No. 3,935,526, 27 January 1976.

Figure 53
29. Siobodan Cuk, "Modelling, Analysis, and Design of
Switching Converters," PhD Thesis, California Institute
of Technology, November 1976. Also, NASA Report
CR-13514.

Figures 57C and D
2. Ibid ... Figure 12.

30. R. D. Middlebrook and S. Cuk, "A New Optimum
Topology Switching DC-to-DC Converter," IEEE
Power Electronics Specialists Conference Record,
June 1977.

Figure 58
45. H. Matsuo and K. Harada, "The Cascade Connection of
Switching Regulators," IEEE Transactions on Industry
Applications, Vol. IA-12, No.2, March/April 1976,
pp.192-198.

31. Siobodan Cuk and R. D. Middlebrook, "DC-to-DC
Switching Converter," U.S. Patent Application No.
S.N837,532 filed September 28,1977. Also filed in foreign countries.
32. S. Cuk and R. D. Middlebrook, "Coupled-Inductor and
Other Extensions of a New Optimum Topology Switching DC-to-DC Converter," IEEE Industry Applications
Society Meeting Record, October 1977.
33. Siobodan Cuk and Robert W. Erickson, "A Conceptually New High-Frequency Switched-Mode Amplifier
Technique Eliminates Current Ripple," Proc. Fifth National Solid-State Power Conversion Conference
(powercon 5), pages G3.1-G3.22, May 1978.

Figure 61
46. A. Lloyd, "Choking Up on LC Filters," Electronics, August 21, 1967, pp. 93-97.
47. H. Matsuo and K. Harada, "New Energy-Storage
DC-DC Converter with Multiple Outputs," Solid State
Power Conversion, November/December 1978, pages
54-56.

Figure 62
48. S. Feng, W. Sander and T. Wilson, "Small-Capacitance
Nondissipative Ripple Filters for DC Supplies," IEEE
Transactions on Magnetics, Vol. MAG.-6, No.1, March
1970, pages 137-142.

34. R. D. Middlebrook and S. Cuk, "Isolation and Multiple
Output Extensions of a New Optimum Topology Switching DC-to-DC Converter," IEEE Power Electronics
Specialists Conference Record, June 1978.
35. S. Cuk, "Discontinuous Inductor Current Mode in the
Optimum Topology Switching Converter," IEEE Power
Electronics Specialists Conference Record, June 1978.
36. S. Cuk, "Switching DC-to-DC Converter with Zero
Input or Output Current Ripple," IEEE Industry Applications Society Annual Meeting Record, October 1978.
37. G. E. Bloom and A. Eris, "Practical Design Considerations of a Multi-Output Cuk Converter," IEEE Power
Electronics Specialists Conference, 1979 Record.
38. Siobodan Cuk and R. D. Middlebrook, "DC-to-DC
Converter Having Reduced Ripple without Need for
Adjustments," U.S. Patent Application, June 15,1979.
39. Siobodan Cuk, "DC-to-DC Switching Converter with
Zero Input and Output Current Ripple and Integrated
Magnetics Circuits," U.S. Patent Application, March 30,
1979.
40. Siobodan Cuk, "Discontinuous Inductor Current Mode
in the Optimum Topology Switching Converter," IEEE
Power Electronics Specialists Conference, 1978 Record, pages 105-123 (IEEE Publication 78CH1337-5
AES).
41. E. Landsman, "A Unifying Derivation of Switching
Regulator Topologies," IEEE Power Electronics Specialists Conference Record, June 1979.

Figure 63A
49. T. J. Maresca, "Regulated DC-to-DC Converter," IEEE
Transactions on Magnetics, March 1970.

Figure 68A
50. R. Hayner, T. Phelps and J. Collins, "The Venable Converter: A New Approach to Power Processing," IEEE
1976 Power Electronics Specialists Conference Record,
pages 92-103.
51. A. Rostad, C. McCown and D. Lawrence, "Application
of the Venable Converter to a Series of Satellite TWT
Power Processors," IEEE 1976 Power Electronics Specialists Conference Record, pages 104-111.

Figure 70B
9. Ibid ... Figure 14.

Figure 82A
52. E. Hnatek, "Design of Solid State Power Supplies," Van
Nostrand Reinhold Co., 1971, page 205.

Figure 84
9. Ibid ... Figure 15.

Figures 54 and 55
Figure 85

42. Private communication E. D. Bloom to R. Severns,
1/17/80.

18. Ibid .. . Figure 3.

109

A035

D~DIL

Figure 86A
53. L. Gemi!t, "Switching Regulator Using Low Voltage

Figure 94
57. J. La Duca and R. Massey, "Improved Single Ended
Regulated DC/DC Converter Circuit," IEEE Power
Electronics Specialists Conference Record, June 1975,
pages 177-187.

Diodes," U.S. Patent No. 3,624,483, 30 November 1971
(Figure 86A is a transistor version of this circuit.)
54. U.S. Patent#4,121,281 in October 1978.

MISCELLANEOUS REFERENCES

Figure88C

58. C. VanVelthooven, "Properties of DC-to-DC Converters
for Switched Mode Power Supplies," N. V. Phillips
Application Note No. 472, Eindhoven, 18 March 1975.
59. S. Lindena, "The Current-Fed Inverter," 20th Annual
Proceedings of the Power Sources Conference, Atlantic City, New Jersey, May 1966, pages A-23 to A-26.
60. J. Joyce and J. Kress, "PowerTransistorSwitching with
a Controlled Regenerative Current Mode Transformer,"
IEEE Power Electronics Specialists Conference Record,
June, 1977.
61. A. Pressman, "Switching and Linear Power Supply,
Power Converter Design," Hayden Book Company,
1977.

55. M. Kohno and K. Kuwabara, "Single Ended DC-lo-DC
Converter with Two Individually Controlled Outputs,"
IEEE International Telecommunications Energy Conference Record, November 1979, pages 191-198.

Figure 90
56. F. Kadri, "Pulsewidth Modulation Derived through Control of Flux Distribution in a Dual-Core Transformer,"
Proceeding of the 1971 INTERMAG Conference, Denver, Colorado, April 13-16, 1971.

Figure 92
9. Ibid .. . Figure 12.

110

D~D[l

A036
Using the Power
MOSFET as a Switch
by Rud), Severns
Most MOSFETs use a form of silicon gate structure where
the gate and the connection to the gate is made with doped
silicon. The SiP material, while very useful in the structure,
has a resistivity about 3,000 times greater than aluminum,
and in some devices creates a substantial resistance in
series with the gate.

MOSFET STRUCTURES
A variety of structures for implementing a power MOSFET
have been proposed and fabricated. Of these, only two
structures, the flat-bottomed V-groove and the vertical
DMOS (double-diffused MOS) structures, are currently
available as viable power switches. A cross-section view of
a V·groove device is shown in Figure 1. Fabrication of an
n-channel device begins with an N- epitaxial layer grown
on an N+ substrate. P and N regions are then diffused in, a
flat bottomed groove is anisotropically etched into the surface, and then an insulated gate structure is deposited. The
source metalization is connected to both the Nand P diffused regions, thereby effectively shorting the base and
emitter of the parasitic NPN transistor. The user should,
however, keep in mind the presence of this parasitic NPN
transistor, which in some circumstances will participate in
the circuit operation. This will be treated in later sections.

Capacitance exists within the structure from the gate to the
source, Cgs, the gate to the drain, Cgd , and from the drain to
the source, Cds. Cds is essentially the capacitance of the
base-emitter junction (Cob) of the parasitic transistor and
has the voltage-dependent characteristic typical of a PN
junction. Cgs is relatively independent of voltage but the Cgd
characteristic is very similar to Cds.
The parasitic transistor also contributes capacitances. Cob
is equal to Cds, since the same structure is involved. In addi·
tion, the base-emitter junction displays a typical diode junction characteristic.

DMOS devices are very similar to V-groove (or VMOS)
devices except that no groove is used and the gate structure
is planar (Figure 2). Manufacturers have given the DMOS
devices a variety of names, such as HEXFET, TMOS, XMOS,
ZMOS, etc. These are all basically the same structure, with
variations in th~ shape of the P diffusions and the cell interconnections.

P-channel MOSFETs are very similar to N-channel except
that the Nand P regions are interchanged. In P-channel
devices the 01" resistance for a given die area will be approximately twice that of a comparable N-channel device.
The reason for this is that in the N-channel device the majority carriers are electrons but in the P·channel device the
majority carriers are holes which have lower mobility. If
the area of the P-channel device is increased to produce an
equal rOS(ON) then the capacitance of the P-channel device
will be higher and the device cost will also be greater. For
this reason N-channel devices are usually preferred for
power switches as long as the external circuits do not
become overly complex to accommodate the N-channel
device.

Inherent in the MOSFET structure are voltage variable
capacitances and resistances. The ON resistance is the
sum of the epitaxial region resistance, the channel
resistance, which is modulated by the gate-source voltage,
and the lead and connection resistances. In addition there
Is a small but definitely non·zero resistance, rBE, between
the base and emitter of the parasitic transistor due to the
bulk resistance of the structure.

DRAIN

Figure 2. Vertical (OM OS) MOSFET

Figure 1. V·Groove MOSFET

111

A036

O~OI!,

SWITCHING CHARACTERISTICS

limit the switching speeds and no amount of drive wizardry
will significantly improve things beyond a certain point.

One of the major advantages of the MOSFET is its ability to
switch very fast. Figure 3 shows a turn-on transition for an
IVN6000 switching 350 volts in 5 nanoseconds! Most of the
presently available power MOSFETs are capable of switching in a few nanoseconds if properly driven_ Except for
switching times of ten nanoseconds or less, the transition
times are almost completely determined by the circuit in
which the device is used. This is quite different from a
bipolar junction transistor, where the physics of the device

Capacitive Characteristics
For switching times down to about 10ns a MOSFET, from a
drive point of view, is essentially a capacitor made up of
C gs , C gd and Cds as shown in Figure 4. A small signal
measurement of these capacitances as a function of drainsource voltage, VDS, for a typical device, is given in Figure 5.
C gs varies little with voltage, remaining about 210pF. Cds
and C gd however are strong functions of voltage; C gd is
400pF at 0 volts but decreases to 5pF at 350V, and Cds also

s
Figure 3. IVN6000 Turn-On

Figure 4. Capacitive Equivalent Circuit

1000

i"'-..

IVN6000
........

VGS=O

I'....

-.:::: ~f'o.
100

eg.
........

...

0
Z

..............

............

C3
10

1"--- .......
........

i'--

I'--..... ...........
Cds........
.........
...........

'Cgd

0.1

10
Vos-VOLTS
Figure 5. Capacitance Variation with Drain-Source Voltage

112

100

1000

A036

O~OIb

has a large variation. The small signal capacitance is interesting to a linear designer, but when the device is used as
a switch the designer needs to know the large signal
behavior. A much better way to present the data is shown in
Figure 6 where the gate charge is plotted as a funtion of the
gate-to-source voltage, VGS, with the supply voltage, Voo, as
a parameter and the drain current. 10 • as a constant to represent the usual inductive load. Figure 7 shows a simplified
version of the test circuit.

(1)

where:
(2)

Combining (1) and (2):

In the example shown in Figure 6, Cm is about 70nF. This
large value occurs because of the current source in the
drain lead; i.e., RL is very large. When a lower impedance
load is used in the drain. Cm will be much smaller and the
slope of the OGIVGS curves will be greater. The amount of
charge required to charge Cgd is, however, a function of Vos
and not RL or gm. so that dOG for the Region II will increase
with Vos. displacing the curves to the right as shown. For a
given Voo. OG will not vary Significantly with RL. Cgd does
vary slightly with variations in 10 and this would alter dOG
with differing RL values. but the effect is so small as to be of
no practical interest in switching applications.

The curves in Figure 6 display three distinct operating
regions. Region I is where VGS is below the threshold
voltage, Vth • so that the device is cut off and the
capacitance Is dominated by Cgs. For this device the small
signal Cgs = 210pF, which is consistent with the Region I
slope. Region II occurs as the device is turning on and
represents the Miller capacitance, defined by:

~oo=I50V

/~~
I, I200V
v

16 t - - loJ1A
I
IVN6000
14

Voo=

Irl
VI
jV /

680pF

g
I

4
2

-2

/ /

Lop~-

V
.=. VDD

~rpF
024

(3)

Cm '" gm RLCgd

I
I
I
I

n w

III
Qa -

NANO COULOMB

Figure 6. Gate Oynamic Characteristics

Figure 7. Simplified Test Circuit

VO~~:~~ _ _ _1_0_%~

10%

Figure 8. Switching Waveform

113

U~UIl"

A036
Region III represents operation with the device fully ON and
Vos near zero. Note that the capacitance in Region III is
essentially the sum of GgS and Ggd at low voltages, or about
650pF.

The total switching time, t s, is defined as:

This set of curves can be used directly by the designer to
determine both the switching time for a given drive impedance and the drive power. The drive power, Pd, for a
resistive drive source and a switching frequency of fa is

If ts is plotted as a function of the gate drive voltage for constant source resistance, curves like those shown in Figure
10 will be obtained. Thus, the deSigner is faced with a tradeoff. If large VGS is used then tdr and tr will be short and
rOS(ON) will be a minimum. Unfortunately, ~f becomes large,
and ts increases as does the drive power. If a small value of
VGS is used then tdr and rOS(ON) increase rapidly. If both low
rOS(ON) and minimum ts are required then a value of VGS that
gives a satisfactory value of rOS(ON) must be used, and a sufficiently low value of Rs must then be selected to give the
desired ts.

(6)

The effective input capacitance, Gin, for a given VGS, is
aQG
Gin = - aVGS

(5)

The idealized switching waveforms are shown in Figure 8. A
good approximationl1] for the switching times can be obtained from a piecewise linear approximation and a simple
RG model (Figure 9) using the appropriate values for Gin in
Regions I, II, or III. The turn·on delay, tdr, represents the time
required to charge Gin to VGS Vth , at which point the device
begins to conduct. A similar delay time, tdh exists at turn-off
where VGS must fall to the pOint where there is a significant
Increase in rOS(ON) before any change In the output Is
observed. The rise and fall times correspond to the times required to charge and discharge the Miller capacitance.

~--~'M~------<>-----o+

RS+RG

Vas

Figure 9. Simple RC Model

R••

1.=IcIr+lr +IcH+I,

Rs2

Vth

VGS_

Figure 10. Total Switching Time as a Function of Gate Drive and Source Resistance

114

O~OIL

A036

This voltage subtracts from VGS during the turn·on as shown
in Figure 13A, restricting the gate enhancement. This effect
can greatly increase the switching power loss because of
the delayed fall of VDS during turn·on. The problem can be
minimized by separating the drive and load current loops
right up to the device case as shown in Figure 138. A TO·3
package will have an Ls of 1 to 10nH depending on the bond·
ing wire size and the number of bond wires. Except for very
high·speed or high·current applications this is not usually a
problem, but even a small length of common external wiring
can greatly increase the effective Ls and create a problem.

High·Speed Limitations
For very fast switching times « 10ns) the simple RC model
of Figure 9 is no longer adequate. The gate resistance, RG,
and the package inductances, Ls, La, and LD, must be in·
cluded, especially in large devices as shown in Figure 11. It
is the parasitic inductances and gate resistances that limit
the achievable switching speeds. For an IVN6000 device the
minimum turn·on time is about 4ns.

lOAD

lS+WIRING

s
Figura 11. Equivalent Circuit Including Package Inductance and
Gate Resistance

(A)

It has been shownl2] that inductance which is common to
both the load and drive circuit, such as the source lead in·
ductance or the wiring inductance, can produce a turn·on
plateau in VDS like that shown in Figure 12. The voltage, VSl,
across the common inductance, Ls, is:

VSl = Ls (diD
dt

diG)
dt

(7)

.J......................·,~I'A·A 'ftJll. ....... .............
Vas
5V/dl.

10
SAldl.

VDS

1Jr"

(B)

V
Figure 13

V"'·
The drain·source capacitance, Cds, can cause asymmetrical
transition time between turn·on and turn·off even if the gate
drive is perfectly symmetrical. At turn·on Cds is discharged
through rOS(ON) and the time constant is very short. At turn· .
off however the rate of voltage rise on Cds is determined by
the load, not by the switch. For a clamped Inductive load
with a large 10 at turn-off, Cds will be charged quickly and
there will be little difference between the gate and drain
switching times, but if a resistive load is present the voltage
across Cds will have an exponential characteristiC, with the
load resistance determining the RC time constant. Even
though the channel is turned off quickly Vos may change
slowly.

10~T~I.~.+-..-..-...+-..-...-l.-...\-\::.-*'...--...+-..-...-1.-..-...+
..-...-..1-..-...-1..

100nsJdi.
(Courtesy Duke UniverSity, Center for

Solid·State Power Conditioning and Control)

Figura 12. Turn·On

Vos

Plateau Due to Ls

115

A036

D~DIL

As shown In Figure 14, Cgd can cause pulse distortion during turn-on. During the Interval when VGS < Vth (tdr) the
device is essentially a capacitor comprised of Cgd + Cg.,
and the positive edge of VGS is coupled to the output producing the initial positive pulse shown. A similar negative
pulse can occur during the turn-off delay time.

60V

r-r-lv+
O.

lpF

1PF

___

120
VOUT

i-CD4011-'"
I

IVN5200

15
16

,
I

,9
I
I
I

112

---

5
10
15
15
15

113

ns
liGATES Id'
I,
1
280 2250
1
80 370
1
44
176
96
2
30
4
24
60

Figure 14. Turn·On Overshoot Due to Cgd and td,

(AI

Drive Circuits
An Ideal gate drive circuit for a MOSFET should provide a
current waveform like that in Figure 15. At turn-on a fast risIng current pulse is applied with an amplitude sufficient for
the desired rise time. When the desired value of VGS is
reached, IG is reduced to the small value required to maintain VGs, A typical MOSFET will have a gate current of less

+60Y

+5V~--~R-l---1~~.::.:.
7406

Y+

Id,

15
15
30
30

3900
75O!l
75O!l
1.5K

40
40
40
66

ns
I,
td'
200
72
340
70
150 70
290 64

I,
120
110
116
100

r-+---------~~r------------(S)

TURN·ON

+15Y

+60Y

of-..L..----------+--f-------------

TURN·OFF
(C)

Figure 15. Ideal Gate Drive Waveforms

Figure 16. CMOS and TTL MOSFET Gate Drive Circuits

116

Ido
75
170
170
80
50

480
360
265
148

A036

O~OI1.

than 1nA but there may be other shunt elements (transformer magnetizing current, for example) In the gate circuit
that require steady-state current. At turn-off a negative
pulse is applied until VGS is zero. As will be demonstrated
shortly in the dVDS/dt discussion, it is imperative that during
the off time the gate-to-source impedance be as small as
possible.

+15V

+20V

(A)

JO.l

l00pF

A close approximation to the ideal waveforms can be
achieved with a variety of circuits. The simplest drive
scheme is to use either CMOS or TIL buffers or gates as
shown In Figure 16. These drive schemes are very attractive
because of their Simplicity, but the switching times are
relatively slow due to the buffer output limitations. If greater
speed Is needed some form of low impedance bidirectional
driver is needed; several such circuits are given in Figures
17 and 18. The OS0026 (Figure 178) driver is particularly
useful. This IC was deSigned as a NMOS clock driver to
drive capacitive loads. There are two buffers in each
package, each capable of sourcing or sinking 1_5 amperes
with a switching time of 20ns. The OS0026 can be driven
from TIL or CMOS logic. If the output from the OS0026 is
not adequate, the output can be buffered with MOSFETs as
shown in Figure 18A to provide much higher currents with
no loss of speed. Figure 188 shows another driver that does
not use a 080026. If the two separate power supplies required in Figures 18A and 188 are not available, then the
bootstrap versions in Figure 18C and 180 can be used.

+20V

+10V

6.8"F

(B)

6.8:Ff y

.01

IVN5200
10V

O>--""f-~I

..Jr IVN~

5
=:_IV_N_

v+
+20V
(C)

10V

11..

IVN5200

(A)

+20V
+

1 6.8"F

(D)

DS
0026

"
(B)

Figure 18. BI-Dlrectlonal Gate Drive Circuits

Figure 17. BI-Dlreclional MOSFET Gate Drive Circuits

117

A036

D~DI1,

In applications which use a very large MOSFET or a group of
MOSFETs in parallel, the input capacitance may be very
large and it can be difficult to charge quickly. Figure 19
shows a circuit which works very well with large-capacitance loads. When the input to the driver is zero, 0, is held
in conduction by Yo of the OS0026. 02 is clamped off by 0,.
When a positive input occurs, 0, is turned off and a current

pulse is applied to the gate of 02 by the other half of the
OS0026 through T,. After about 20ns, T1 saturates and 02 is
held on by its own Cga and the bootstrap circuit made up of
C1, 0 1 and R1. For pulses less than 50iLS the bootstrap circuit may not be needed as the input capacitance of 02
discharges very slowly. At the end of the positive input
pulse, 01 turns on shutting off 02.

V+

Y
~-t---,

2 - 1000PFj
1 - O.01/LF PARALLEL
4 - O.1/L F
IVN5200
1000pF
C1

100pF

SL
PWM Q - -......-'VV'Ir-.
1K
5Vo-p

T1 -

is three turns 30 bililar on a ferrite bead.

PERFORMANCE SUMMARY

ns
ZL
511 & 1oo0pF
4700pF
511
511
100' RG223/U
Terminated in
5111

v+ +

20
20
20

15
15
15

Id'
22.5
22.5
23
22

I,
7
15
11
18

Id'
15
16
14
14

I,
7
15.5
4.5
4

20.5'

13'

6.5

·Measured at mput to cable.

Figure 19. Very High Speed Driver

118

O~OIL

A036

Figure 20. Again the bootstrap portion of the circuit may not
be needed when the switching frequency is above 10kHz.

The power driver circuit in Figure 19 can be modified to provide a direct coupled drive for a buck regulator as shown in
1N914

1000pF

..n.
PWM

INPUT

V.
DSOO28

"'T1 Is three tums blfllar wound on a ferrite bead.

Figure 20. Gate Drive Scheme lor MOSFET Buck Regulator

It Is possible to use inductive energy storage schemes to
drive MOSFETs; two possibilities are given in Figure 21.
Energy is stored in L1 during the OFF time of Q2 and then
discharged into the gate of Q2 during conduction. The major

(A)

disadvantage of these drive schemes is that the discharge
current through the zener clamps must be maintained during the entire ON time of Q2' This may greatly increase the
drive power required.

(8)

PWM

Figure 21. MOSFET Drive Circuits Using Stored Energy

Many applications require transformer isolation between
the switches and the driver circuitry; Figure 22A shows a
very simple means to accomplish this. Unfortunately this
simple circuit has a major problem_ As shown in Figure 228,
the transformer winding volt-seconds product must average
zero. This means that the gate enhancement voltage will
vary with duty cycle, being greater at low duty cycles. If a

wide range of duty cycles must be accommodated the
switch will be over-driven at low duty cycles and underdriven at high duty cycles. As was shown earlier, this can
lead to large variations In the total switching time. However,
for those applications where only a moderate variation in
duty cycle is required this simple circuit can work very well.

+
(8)

vas

1--1
I
I
I

I
'-

Figure 22. Transformer Coupled MOSFET Drive Cirult

119

O~OIL

A036

In the drive switching times. The value of Cl is determined
by the magnetizing current of Tl . Cl should be large
enough that the voltage rise across it, due to the magnetizing current during Yo cycle, is small compared to Vs.

There are transformer-coupled drive circuits where VGS does
not vary with duty cycle. A circuit that can be used in symmetrical converters Is shown in Figure 23A. In the initial
state 8 3 and 8 4 are closed and 8 1 and 8 2 are open. The
voltage across Tl is zero and 01 and 02 are off. 8 4 is then
opened and 8 2 closed, applying a voltage, Vs, to the primary
of Tl with the dot positive. VGS for 01 is positive and for 02
negative, turning on 0 1. At the end of the conduction interval of 0 1, 82 is opened, 8 4 is closed, and the circuit reverts to
the initial state with 0 1 and 02 off. 8 3 is then opened and 8 1
closed, so that Vs is applied to the primary of T1 with the dot
negative. This turns on 02 and holds 0 1 off. At the end of the
conduction interval of 02, 8 1 is opened and 8 3 closed and
the circuit reverts to the initial state. The transformer sees
only a symmetrical AC waveform and VGS is fixed by Vs and
the turns ratio of Tl independent of duty cycle.

A practical implementation of the circuit In Figure 23A is
given in Figure 238. The switching function Is provided by a
pair of 080026 clock driver ICs driven at TIL levels from a
push-pull pulse width modulator. For low-power applications only a Single 080026 may be needed (there are two
drivers in each package), while for high-power applications
the 08oo26's may not be able to supply sufficient drive current by themselves.
The 080026's can be replaced by a pair of drivers like those
in Figure 19 to supply almost unlimited drive power by proper
selection of the output devices. For bridge converter circuits,
two more Isolated windings can be added to Tl .

Cl is added to the circuit to prevent a DC component from
appearing across the primary of Tl due to lack of symmetry

(A)

1
t---llll----'-,
Cl

(B)

l00pF
PHASE 1

I.F

DS
0026

6
5

1.~

+20V
l00pF

.rL

!I
DS
0026

iIIl

I,
il
I,

8
2

PHASE 2

I'"

6
5

I.F

Flgur. 23. Symmelrlcal Transformer Coupled Drive Circuli

120

O~OIb

A036

There are many other possible variations of both primary
and secondary arrangements, and a few of these are summarized in Figure 25.

Figure 24A shows a transformer coupled circuit that will
provide constant VGS In asymmetrical converters. This cir·
cuit is a variation of the feed-forward converter. At the
beginning of the positive input pulse, 01 turns on driving 02
into conduction. At the end of the input pulse, 01 turns off.
The voltages across the transformer windings reverse, shut·
ting off O2, and the energy stored in the core is discharged
through D1 into the source. While very simple, the circuit
has two drawbacks. First, the energy stored in the core is a
function of the duty cycle. The turn-off current for 02 is the
magnetizing current for T1, which is a function of duty cycle.
The second problem occurs if the current in D1 goes to zero
during the off time of 02. This leaves the gate connected to
winding Na, which may well have sufficient impedance to
cause dVosldt triggering problems. By adding OP1, as
shown in Figure 24B, from gate to source of 02, these problems can be overcome. At turn-off, 03 is driven on by the
energy in T1 clamping the gate of 02' Even after all the
energy in T1 is discharged, 03 still presents a relatively low
impedance at the gate of 02'

There is a basic limitation to the maximum duty cycle of
single-transformer drive circuits. Over the period of one cy·
cle the winding volt-second product must average zero. During the switch ON time the winding voltage is determined by
the required enhancement voltage, VGs. During the OFF
time VGS is limited by the breakdown voltage, BVGs, of the
gate. The maximum duty cycle is:
BVGS
DMAx = BVGS + VGS

(8)

Exactly the same problem exists in a bipolar junction transistor. However, when using a BJT, it is possible to use a
diode in series with the emitter to arbitrarily increase BV BER
at the expense of increased voltage drop during conduction.
This trick does not work with MOSFETs, since the leakage
current of the diode will be much larger than the leakage of
the MOSFET gate and all the reverse voltage still appears
across the gate.
Another disadvantage of single-transformer circuits is that
the transformer must be able to support VGS during the en·
tire ON time of the switch. Given the typical enhancement
voltage of 10 to 20 volts this makes the transformer relative·
Iy large.

(A)

PRIMARIES
(AI

.fl

(BI

(<:I

r~'O---......----t~u

11---1

TL---~(_~
Figure 25. Primaries
Secondaries on next page

figure 24

121

D~DlL

A036
SECONDARIES
(D)

turns it off. Despite the relative complexity, the circuit has
several advantages. T1 and T2 can be designed to have very
low leakage inductance, which makes fast transitions in 0 4
possible. There is no inherent limitation on duty cycle, and
04 may be kept on continuously by periodically pulsing 0 1
to replenish the charge in the gate of 0 4 , The main disadvantage of this circuit, other than its complexity, is the high
gate impedance during the off period, determined by R1. To
prevent VGS from sagging significantly during the ON
period, R1 must be relatively large. If this drive scheme is
used in a circuit that subjects 0 4 to a positive drain-source
voltage transition during the off period, 0 4 may be triggered
into conduction.

(E)

(G)

Figure 26. Pulsed Gate Orive Circuit

CON DUCTION CHARACTERISTICS

Figure 25. Secondaries

One means to get around these limitations is to use some
form of pulse drivel41where the switch Input capacitance is
charged at turn-on and holds VGS positive until a negative
pulse discharges it at turn-off. Such a circuit is shown in
Figure 26. At the beginning of the cycle, a short pulse is applied to the gate of 0 1, which in turn injects a current pulse
into the gate of 0 4 turning it on. 04 remains on due to the
stored charge in the gate until a turn-off pulse is applied to
02' This turns on 03, which discharges the gate of 04 and

In addition to the switching characteristics, the ON state
conduction characteristics are of primary concern to the
designer. For practical purposes the MOSFET can be
regarded as a voltage (VGs) controlled resistance. The ON
resistance of the MOSFET is made up of two components:
the voltage-controlled channel resistance arid the fixed
resistance due to the drain epitaxial region, the source area
bulk resistance, the die surface metalization and the
package bond wires. In a low-voltage « 100V) device the
channel resistance is usually larger than the fixed
resistances. In a high-voltage device, however, the ON
resistance is dominated by the resistance of the epitaxial
drain region when the device is fully enhanced. Figure 27
shows the variation of rOS(ON) with VGS (VGS = VGS - Vth) and
10 for a 450V two-ampere MOSFET (IVN6000 KNT). Note that
rOS(ON) increases with 10' The change in rOS(ON) is very abrupt
as VGS is increased.

122

A038

O~OIL
1A 3A 0.5A

IO=O.5A

100
1.4

IVN6000

,,,,-

'"'"

c 1.2
w

...!::!
C

'"I 10

:IE

5A,
3A
lA
0.5A

!?
I\,

1.0

lo=~mA

€

III

"OPE= -6.7mV/oC- t---

0.8

IVN6000

'" "i'..

0.6

'['-...

-2

6
8
10 12
VGS - VOLTS

-60° _40° -20 0 0°

20° 40° 60° 80° 100 0 120° 140°
Tj _ °C

*Vas=Vas - V'h

Figure 29. Varialion of Threshold Voltage with Temperalure

Figure 27. Varialion of rON with VGS and 10

rDS(ON) is also a function of temperature, as shown in Figure
28. For VGs>3 volts, the normal region for power switch
operation, the temperature coefficient is positive. This is
one of the major advantages of the MOSFET over the
bipolar, and accounts for the absence of lateral thermal instability induced second breakdown and the ease with
which multiple devices may be paralleled. Below VGS = 3V,
rDS(ON) begins to display a negative temperature coefficient.
This is due to the temperature coefficient of Vth as shown in
Figure 29. For this particular device the temperature coefficient of Vth is about -6.7 mV/oC. For VGS values near Vth ,
, rDS(ON) is dominated by the channel resistance, which in
turn is a strong function of Vth • For switching applications,

this region is normally traversed very quickly during turn-on
or turn-off and the negative temperature coefficient region
is not a problem. Figures 30 and 31 show the normalized'
value of rDS(ON) as a function of temperature for a highvoltage (Figure 30) and a low-voltage (Figure 31) MOSFET. In
the high-voltage device the temperature coefficient of
rDS(ON) is 0.7 to 0.9%loC. Because of the relatively greater
contribution of the channel resistance to rDS(ON) in the low. voltage device, the variation of Vlh with temperature reduces
the temperature coefficient of rDS(ON) to 0.2 to 0.5%l oC. A
very rapid means for determining the maximum value of ID
for a given VDS and VGS is to use the curves given in Figure
32.

2.0

100
TI=
+ 125°C

IVN6000 r--

VGL15~ ~

1.8

lo=lA t---

lo=lA
1.6
IVN6000

"--- +25°C

c 1.4

40°C

~ 1.2

I 10
z
!?

~ 1.0

I 0.8
~

-2

0.6

Vas=4V

,/'

........

i/'"
1/

0.4
0.2
6
8
10 12
vas -VOLTS

_600_400_20° 0

20° 40° 60° SOO 100° 120° 140°
TI- °c

Figure 30. Variation of ON Resistance with Temperature
for High·Voltage Power MaS

Figure 28. Variation of rON with Temperature

123

A036

O~OIL

1.3 -

---

IVN5200

----

can be represented by a variety of equations, all of them exponentially decreasing in some manner. A typical equation
is:

Vos= 10Vj
1.2

~
;;!1.1
:IE

II:

V = k(n) (1_eAD)2

1 1.0 ---

0.9 ---0.8 --

-/ -

--:;::: P=""
--

~S=5V~ ~ --1----

where A is the die area, D is the defect density, n is the
number of process steps and k is a factor that varies inversely with n, usually exponentially. The result is a rapid
decrease in yield as the die area Is increased. For small
devices « 0.050" x 0.050") the yield is usually very high and
the die cost low, but as the die dimensions begin to exceed
0.100" x 0.100" the yield drops and the cost per die increases rapidly. Many power FETs are larger than those
dimensions. For example, a one-ohm 450-volt die may cost
four to six times as much as a 2.5-ohm die with the same
breakdown rating.

----+--

/ I -

/ 10V

-50

-25

+25

+50

+75

+100

TA _·C

For small dice « 100 mil) the package cost is greater than
the die cost and so the final device cost is relatively constant but as the die cost exceeds the package cost the total
device cost becomes exponential with die area. This is
shown qualitatively in Figure 33.

Figure 31. ON Resistance Variation with Temperature for Low-Voltage
Power MOS

The rDS(ON) given in the data sheets is usually for a junction
temperature of 25·C and the deSigner must calculate the
actual value of rDS(ON) for the particular application. The
actual rDS(ON) is:

For a given structure and voltage rating, the ON resistance
of a MOSFET is an inverse function of the die area. If half
the ON resistance is desired the die area must be doubled.
For a given structure and die area, rOS(ON) increases very
rapidly with breakdown voltage. The relationship is:
rDS(ON) ex BVDS2.5-2.7

(10)

,,/

rDS(ON) = rDS(ON)(1

a T 25·C
100) r

(11)

(9)

where rDS(ON) is the resistance for Tj = 25·C at the design ID
and VGS and a is the averaged temperature coefficient of
the ON resistance at the design Tj •

The result is that a high·voltage, 10w·rDS(ON) device requires
a large die.

10
9

IVN 6000
8

f3
II:

VDS=50~

/
V

:IE 5

;,V-

I 4

t
o

I-"

COST

VDS~2OV

DIE COST =
PACKAGE COST

VOSi 1OV

..-

Vos=5V

L...?

---------

DIE AREA-

V~-2V

8
10 12 14
Vas-VOLTS

Figure 33. Die Area versus Device Cost

Figure 32. Large Signal Transfer Characteristic

avos Variation with Temperature
The breakdown voltage (BVDS) for a MOSFET is a function of
temperature as shown in Figure 34. At high temperatures
BVDs is above the data sheet values, but at low temperatures it can be significantly lower. For those applications
where the switch is exposed to a low temperature soak and

The cost of a MOSFET is a strong function of the die area. If
a large die area is used to reduce the ON resistance, the
number of dice per wafer will decrease; additional dice are
lost due to inherent wafer defects and the increased scrap
zone around the wafer center and periphery. The yield (V)

124

A036

O~OIL

then turned ON, this should be taken into account even
though most devices supplied by the manufacturer will have
breakdowns well above the data sheet values.

A portion of the drive power, PT, is dissipated in the internal
gate resistance, RG, and the remainder is dissipated in the
drive circuit resistance, Rs. (If resonant charging is used
most of the gate drive power may be recovered in the driver.)
The gate dissipation, PG, is:

Note that the MOSFET is not unique in displaying a lower
breakdown voltage at lower temperature. BJTs also show
this effect.

PG=PT (

RG~Rs)

(16)

RG is typically in the range 011 to 10 ohm. Except in very
high frequency switching applications (> 100kHz) the drive
power is insignificant compared to the other losses and is
usually ignored.
Even when VGS = 0, some current, loss, will flow from drain
to source. As shown in Figure 35, loss is very small at room
temperature but increases exponentially as the Tj is in·
creased. The power loss due to leakage is:

1.2
,VNb

1.1
./

;;!
1

PL = Vos loss (1-0)

0.9

In those applications where the MOSFET sees a substantially constant Vos the power dissipation decreases with increasing Tj because of the positive temperature'coefficient
of rOS(ON), but this is not the typical switching application.
More often the drain load is effectively a current source. In
this mode of operation the power dissipation Increases as Tj
increases, providing a positive feedback mechanism that
further increases Tj • Usually, however, for junction temperatures below 150°C, the gain coefficient of the positive feed·
back is less than one, so that a stable equilibrium point is
reached. At higher temperatures (>150°C) it is possible to
have no stable equilibrium point and the device can go into
thermal runaway.

0.8
-40·

+160·

O·

Figure 34. Breakdown Voltage Variation with Temperature

POWER LOSS AND JUNCTION TEMPERATURE
CALCULATION

1000

In a practical design situation the designer needs to know
the total power dissipat:on and the junction temperature.
The total power dissipation, Pd , Is the sum of the switch
loss, Ps, the conduction loss, Pc, some fraction of the gate
drive power, PG, and the leakage loss, PL, due to loss during
the off time of the switch. The conduction loss is:

Vos (t) 10 (t) dt

IVN6000
I

VDs=350V
VGS=O

100

2
2
IX T-25·C
Pc = ID(RMS) RoN = ID(RMS) roS(oN)(1 + 100) J
(12)
The switching loss depends on the switching time and the
nature of the drain load. The power loss due to a switching
transition is:

Ps = fs

(17)

where Vos is the drain source voltage during the OFF time,
loss is at the highest expected Tj , and 0 is the switch duty
cycle. Since initially Tj is known only approximately, the
value for PL is only approximate. Normally, however, PL is
only a small part of the total loss so that the error is not
usually significant.

./V

::I!

~
z

'=== t---

L
10

ee-

(13)

where fs is the switching frequency and T is the sum of the
voltage and current transition times. Normally an exact
solution Is not required and the following approximations
are usually adequate:
VOSMAX·loMAX )
ris
for a resistive load, Ps = (
6

(14)

VOSMAX·loMAX )
Tfs
and for an inductive load, Ps = (
2

(15)

1
-40 -20

/
0

40
60
80 100
TEMPERATURE - oc

120

140

Figure 35. Oraln·Source Leakage Current versus Temperature

125

I
I
I

I
"

D~DI!:.

A036
To determine the junction temperature the following equations must be solved:
2
Cl T,-25°C
Po = ID(RMS) rOS(ON) (1 + 100> '
+ Ps + PL

(18)

T, = TA + Rth(J.A) Po

(19)

Although equation (18) is transcendental and an exact
analytical solution is not possible, a variety of solution
methods are still possible. A most practical solution has
been suggested by Gyma, Hyde and Schwartz[4) using a
quadratic approximation for equation (12) which gives an
answer accurate to a few percent. Equation (18) now takes
the form:

General Case
IAVG = 0 Ca; Ib )
IRMS =

(1.2 + 1.lb + Ib2

)f'

<1=

Special cases

If equations (19) and (20) are combined:
A Tf+ B Ti +C=O

1) 0=1

(21)

IAVG=~

where:

A = a2 Rth(j.A)I~RMS) rOS(ON)

(22)

B = al RthO-A)lb(RMS) rOS(ON) - 1

(23)

C = TA + Rth(j.A) (Ps + Pd + 80 Rth(j.A) )~RMA) rOS(ON)

(24)

_(la2+lalb+lb2)V.
RMS3

2) la=lb
IAVG=la O
IRMS = la,JIJ
3) 1.=0

IAVG=I~

The following values for the coefficients 80, al and a2 have
been suggested:[4)

IRMS=lbA"

ao = 0.8650, al = 4.443, and a2 = 3.822 x 10 - 5
From equation (18):

Tj=

-B-v'BC 4AC
2A

Figura 36. Average and RMS Values for Trapezoidal Waveforms
(25)

It has been shown[4) that the lesser of the two possible solutions is the correct choice. If the solution for Tj is complex
the operating conditions being considered will produce thermal runaway. If a more accurate solution for Tj is required
then some form of iterative solution using a computer can
be used.

It can be shown that:

K..

1; =f(L/Lcl

(26)

where, L = inductance of the averaging choke
Lc = is the critical inductance for a particular input
voltage and load power

Once the junction temperature has been determined then
the total power dissipation can be calculated using equation (19).

As L is increased, K goes from 0 (triangle) to 1 (rectangle).
Substituting K = lallb for the continuous choke current case:
I

Minimizing 'D(RMS)
The dominant term in the power loss Is normally Pc. The
designer can minimize the amplitude of 10(RMS) for a given
power level by an appropriate choice of topology and by
controlling the current waveshape.

_IAVG - /K2+K+1
RMS-V 3 (K+ 1)2

(27)

For constant IAVG and D, the normalized (!RMS = 1 for K = 1)
IRMS is as shown in Figure 38. This curve shows the 12R
losses for triangular waveforms are 32% higher than for rectangular waveforms. It is also apparent that for lallb> 0.6, the
additional losses incurred by having L< 00 is only 2%, so
from a practical point of view L need only be about twice Lc.
Increasing the value of lallb Increases the switch turn-on
losses but decreases the turn-off losses. Since the turn-off
losses usually dominate, increasing lallb reduces the
switching loss also.

In a switch mode converter, the current waveforms through
the inductors, transformer windings, rectifiers and switches
will appear as shown in Figure 36, ranging from a triangle to
a rectangle depending on the value of the averaging inductor and the load. For the capacitors, the waveforms will be
similar, except that there will be no DC component (see
Figure 37). The RMS and average values of the waveform are
given in the figures.

126

A036

O~OIL
For the case where:
la= Ib:
IAVG
lAMS =

.JO

(29)

the curve in Figure 39 also applies.

1
= ,D
=CONSTANT

Special Cases

IRMS (N)

1) 0=1

IAVG

IRMS=~
1.=lb

IRMS=I.~
Q

3) 1.=0

IRMS=lb ~Q2
"3-4

II:

II>

Figure 37. AMS Value of AC Component of Trapezoidal Waveforms

:IE

----

_. --

- -+-

.....

_. -

---

11
il

- - t---. - -

-_.

...

...........

r-- r--

1.1 6

-- c--

1.1

4 \
1.12

---

r----

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

DUTY CYCLE

~ 1.1 0

Figure

~ 1.08

o
z

39.

Variation of AMS Current

with

Duty Cycle for Triangular

or Rectangular Current Waveforms

'\.

11>1.06

:IE

-1.04

"'"'-

1.02

C-

---r--M

K=la/lb

Figure

38.

Variation of 'RMS with Trapezoidal Current Aatio

For the case of discontinuous inductor. current (L < Lc),
la1lb 0 and is no longer relevant since the waveforms are
now triangular. For a given IAVG the RMS current is:

lAMS =

IAVG

.J3D

The topology selected can have a profound effect on the
conduction losses. A simple example is shown in Figure 40.
Figure 40A is a normal half-bridge quasi-squarewave converter, while 40B is an unmodulated half-bridge preceded by
a boost regulator. Given the conditions in Table I, the power
losses for (B) are much lower than (A). Because the cost of
power MOSFETs is a strong function of 1/rDS, the three
devices used in (B) may be much cheaper than the two
devices in (A). While this is a fairly simple example, the
boost derived family of converters generally provides lower
MOSFET conduction losses than the buck derived converters. Figures 41A and 41 B show two examples of boost
derived converters, one using overlapping conduction and
the other a secondary shunt switch. There are many other
possible. circuits that may be used. Unfortunately, the boost
family of converters has disadvantages also:
1. The control loop transfer function contains a right halfplane zero which is difficult to compensate for with
single-loop feedback. By using multiple AC and DC
loops, this problem can be overcome.

(28)

A plot of equation (28) is given in Figure 39, where IAVG is
constant and lAMS is normalized for D = 1. Obviously
triangular current waveforms with high peak currents and
low duty cycles are to be avoided if low losses are desired.

2. The output ripple current in a boost converter is discon·
tinuous (the input current is continuous) so that the output ripple current is large.

127

A036

D~DIL

Boost Regulator/Half-Bridge
Low Line, PT = 9.1W
High Line, PT = 6.5W

Half-Bridge
= 35.BW
High Line, PT = 12.9W
Low Line, PT

(S)

(A)

Figure 40. Topology Trade·Off

Table I. Power MOS Topology Conduction Loss Comparison Assumptions

1. Po

=200W

2. "

= BO% Without Switch Losses

= 200V to 375V
4. TA
=50·C
5. ros
= 2.50 at 25·C
6. Filter Inductor is Large
7. BVoss = 450V to 500V
B. OJ A
4 ·CIW (T0-3 Case and Heak Sink)
9. ros Temperature Coefficient Is 0.6%I·C
3. VOC

OVER·t~

LAPPING
CONDUCTION -l

PWM :I

~~~~~~; r...,

50%
DUTY
CYCLE
(B)

Figure 41. Boost Derived Power Converters

128

O~OlL

A036

When compared to bipolar transistors, the MOSFET conduction losses for a given die area are always greater; the
transistor's drive power and switching losses are greater
than the MOSFET's. Figure 42 shows a comparison between
transistors and MOSFETs of the total switch loss as a function of the switching frequency. The value of the crossover
frequency, fo, Is a matter of some debate but lies in the
region of 10 to 30kHz for devices of similar die area.

3. In those converters using overlapping conduction in the
primary, a large voltage spike can be generated due to
the interruption in the primary to secondary leakage in·
ductance current. When the shunt switch is in the secondary, this spiking is greatly reduced.
Despite these drawbacks the significantly lower power
losses of the boost family of converters make them very attractive for converters using MOSFET switches.

§
II:

MOSFETI----------:;;;;01--

BIPOLAR

1--------

FREQUENCY_
Figure 42. Comparison of BJT and MOSFET Losses
Note: F0 = 10 1030kHz

rapidly decreasing hFE at high currents effectively discourages operation in excess of the current ratings. In a MOSFET, however, the gain is not reduced at high currents, and
there may be a temptation, in fast pulse applications where
a high drain-source voltage drop may be acceptable, to
operate with very short high current pulses in excess of the
ratings. Even if the device dissipation is very low, this is inadvisable for two reasons. First, the reliabilty or service life
of the device is undefined and likely to be shortened, and second, if the current density in the device is increased sufficiently, it is possible to reach the level where current injected avalanche breakdown occurs, possibly destroying
the device.
For a bipolar transistor the SOAR curves will have a fourth
boundary. This region is defined by the thermally-induced
second breakdown characteristic. In a bipolar device there
are several ways to Induce secondary breakdown. The first
Is thermal, where the negative temperature coefficient of
VeE causes localized hot spots to be formed. When the
temperature of a hot spot is sufficiently high, its impedance
Is drastically reduced, funneling the collector current
through a small area, usually destroying the device. Another
mechanism for inducing secondary breakdown is via
avalanche breakdown. If the collector voltage Is raised to
the breakdown point of the collector-base junction and a
significant current allowed to flow, the device will go Into
secondary breakdown. It has been widely advertised that
MOSFETs do not exhibit secondary breakdown. This is not
true. It is generally accepted that at normal junction temperatures, the thermally-induced secondary breakdown phenomenon so prevalent in bipolar devices is not present in

SAFE OPERATING AREA
To achieve satisfactory service life from any power
semiconductor, the circuit designer must assure that the
device is operated within the voltage, current and thermal
capabilities inherent in the particular device. To assist the
designer, the manufacturer provides a table of maximum
ratings, a safe operating area curve (SOAR) and a transient
thermal impedance curve.
A typical absolute maximum ratings table is reproduced In
Table II. While the information In the table is useful, it is not
sufficient by Itself for a power device. To adequately define
safe operating conditions it is necessary to use the SOAR
curve, like that reproduced In Figure 43. For a power
MOSFET, the SOAR curve will have three boundary regions.
Region I is defined by the breakdown voltage capability of
the device. Region II Is defined by the thermal capability of
the device. Normally a maximum junction temperature of
150·C is specified, so that in Region II the power dissipation
is limited by a peak junction temperature of 150·C. This
results in Region II being defined by a family of curves that
allows higher peak power for shorter pulse widths.

Region III Is defined by the current capability of the device.
The current capability of a given device may be limited by
the bond wire diameter, the area of the bonding pad on the
die, or by the metalization on the die surface. Whereas the
breakdown voltage and junction temperature limitations
can be readily determined by direct measurement, the current limitations are empirically derived from life testing. The
maximum current is limited to a value which has been found
to give an acceptable service life. In a bipolar transistor, the

129

A036

D~DIl.

100
100,.. / 10,..

500,..
Iii'
II.

1m.
r--tp=5m\I\
I

1 10

z
REGION'" DC "I
~
IVN5200TND
Q
1.0 IVN5201TND
I
E
IVN5200TNE
IVN5201TNE

device. In a MOSFET, the base and emitter are shorted right
on the die, and for reasons of improving the dVDsldt
characteristic, the resistance is made as low as possible. In
addition, the hFE of the MOSFET parasitic bipolar is much
lower than a typical bipolar device. The result Is that the current level at which primary breakdown becomes secondary
breakdown is much higher in a MOSFET than It Is in a comparable bipolar transistor. The device ratings are selected
so that the maximum Vos is well below the actual
breakdown pOint in production devices.

"
r-....

---

REGION II

,
,

.;
17', ::.~

IVN5200TNF
IVN5201TNF
0.1
1.0
10
VDS - DRAIN·SOURCE VOLTAGE (VOLTS)

Current-injected avalanche breakdown, present in bipolafs
during reversed bias operation, can also lead to secondary
breakdown in the presently available types of MOSFETs.
For a given field gradient within the semiconductor there is
a maximum current density threshold above which self-sustaining avalanche breakdown can occur. This is a basic limitation on the current-handling capability of a power device.
In present MOSFETs the internal current densities are
limited by design, so that the junction temperature thermal
limit is reached well before any current·injected avalanching
is present. Both of these breakdown modes lie well outside
of the published SOAR curves and neither Is of direct interest to the device user. Due to the absence of thermallyinduced second breakdown, the SOAR for a MOSFET is
greatly expanded over that of a comparable bipolar.

REGION I
100

Figura 43. Typical SOAR Curves

Table II. Absolute Maximum Ratings (25°C unless otherwise noted)
Drain-source Voltage
IVN5200TND, IVN5201TND ................ 40V
IVN5200TNE, IVN5201TNE ................ 60V
IVN5200TNF, IVN5201TNF ................ 80V
Drain-gate Voltage
IVN5200TND, IVN5201TND ................ 40V
IVN5200TNE, IVN5201TNE ................ 60V
IVN5200TNF, IVN5201TNF ................ 80V
Continuous Drain Current (see note 1) ......... 4.0A
Peak Drain Current (see note 2) . . . . . . . . . . . . . .. 10A
Gate-source Forward Voltage. . . . . . . . . . . . .. + 30V
Gate-source Reverse Voltage . . . . . . . . . . . . .. - 30V
Thermal Resistance, Junction to Case ..... 10·CIW
Continuous Device Dissipation at (or below)
25·C Case Temperature ................ 12.5W
Linear Derating Factor .............. " 100mW/·C
Operating Junction
Temperature Range ......... -55·C to + 150·C
Storage Temperature Range .... -55·C to + 150·C
Lead Temperature
(1/16 in. from case for 10 sec.) . .. . . . . ... + 300·C

The normal manufacturers' SOAR curve is given for a case
temperature of 25·C and either DC or a single pulse. In the
real world of case temperatures above 25·C and repetitive
pulses, the designer must modify the standard SOAR curves
for his particular application. This can be done by using the
transient thermal impedance Z(th) curves which are generally
mllde available by the manufacturer.[7]

dVidt LIMITATIONS AND MOSFET POWER
SWITCHES
Most designers are well aware of the dV/dt limitations of
SCRs which, if exceeded, can cause these devices to turn
on in the absence of a normal trigger pulse. However, it is
not generally appreciated that a similar, and In some cases
equally detrimental, phenomenon can appear in both
bipolar transistors and MOSFET power switches.

Note 1. Tc=25°C; controlled by typical RDS(ONI and maximum
power dissipation.
Note 2. Pulse width SO,.., duty cycle 1.0%.

Waveforms Responsible for Spurious Tum-On
Turn-on due to dV/dt can occur in any power circuit that subjects the power switch to a positive dV/dt during the normal
operating cycle. A very common circuit application where
this occurs regularly is the pulse width modulated switching
regulator. An example of a half-bridge circuit is shown in
Figure 44 along with the collector (or drain) voltage and current waveforms in Figure 45. The normal operating conditions are shown in Figure 45A. 0 1 turns on at to and off at t1'
02 turns on at t2 and off at t3 where a negative current spike
flows through 0 1 and D1 due to the transformer leakage inductance. Normally most, but not all, of the reverse current
at t3 will flow through 0 1, From Figure 45A it is evident that

MOSFETs; the avalanche-induced secondary breakdown,
however, Is. This is not surprising; as shown in the earlier
discussion, the MOSFET structure has within it an NPN
transistor, and the voltage limit on the device is the basecollector jUllction breakdown voltage. The breakdown
voltage is equivalent to BVCEX in a bipolar.
The current level at which primary breakdown becomes
secondary breakdown is a function of the base emitter
resistance, the temperature and the hFE of the bipolar

130

D~DIL

A036
0, 15 subjected to a positive dV/dt during the operating cycle when the switch is in one of two states: at t" 0, has
been conducting in the forward direction and at t2, 0, is
quiescent.

Mechanisms Responsible for Spurious Tum-On
Figure 46 shows equivalent circuits in which the effect of
Cob, Cie and RBE for the transistor and Cgd, Cgs and Rgs for
the MOSFET are taken into account and separated from the
basic device.

In some applications, such as resonant inverters, motor
drivers or synthesized sine wave inverters, waveforms
similar to those in Figure 45B can occur. The significant
feature of this mode of operation 15 the reverse conduction
of 0, and D, just prior to the application of a positive dV/dt
on the collector. This is a third state in which the device may
see a positive collector transition. Any or all of these states
can occur in a very wide variety of power switching applications.

If a positive voltage ramp, Vos, is applied to the drain of the
MOSFET a current, I" will flow through the Cgd, Cgs and Rgs
resulting in a positive value of Vgs. If I, is large enough V9S
will exceed the threshold voltage, Vth , of the MOSFET and it
will turn on until V9S drops below Vth . An identical effect is
present in the bipolar device which will turn on if VBE exceeds 0.6 to 0.7 volts.
The amplitude of I, Is determined by the values for the
capacitors, input resistances, E, and t,.
The values for the capacitors depend on the type of device
(bipolar or MOSFET), the design of the device, Vos and the
state of conduction immediately prior to the application of
the ramp. The Input resistances (Rgs and RBE) are in part inherent In the devices and partly determined by the external
circuit impedance. The threshold voltages (Vth or VBE) are
temperature variable and in the case of the MOSFET, Vth is a
device design variable. Transistor hFE also varies with
temperture. E, and t, are of course determined by the external circuit.

PWM:J II
-=- Vs

Despite this apparent complexity, analytical solutions for
Vgs or VBE during the ramp can be derived which are of practical use.

pwM:=J11

General Model
For the purposes of calculating the voltage at the gate or
base, the equivalent circuit shown in Figure 47 can be used
with the appropriatl:l component values. The ramp function
is provided by the combination of a positive unit ramp starting at t = 0 and a negative unit ramp at t = t,_ The slope of
the ramp, dV/dt, is:

Figure 44. Typical SWitching Regulator Circuit

dV
dt

(30)

= t1

The output voltage, Eo(S), can be shown to be:
VCE

Vs
Vs

EOVBE. As long as
the user keeps the source impedance low during positive
drain transitions the maximum dV/dt is determined by the
bipolar. Too high a gate impedance can, however, lower the
dV/dt rating by allowing the MOSFET to turn on.

How to Determine the Appropriate Values for C1 and C2
As has been already mentioned, the values for C1 and C2 depend on the type of device selected and the design of the
specific device. Once a specific device has been selected,
the values for C1 and C2 will be dependent on the potentials
applied to the device. The typical capacitance values for a
high-voltage MOSFET were shown in Figure 5. While Cgs is
relatively constant with variations in Vos, Cgd Is obviously
not. It is possible to substitute the value of Cgs for C2 and a
relatively simple analytical expression for Cgd , for C1 into
equation (36) to determine epK but this would be somewhat
clumsy. A simpler solution would be to determine an
average value for C1 from Figure 5 for the peak voltage the
device will see.

DRAIN

A bipolar device in the quiescent state will display a
capacitance characteristic very similar to that shown for the
MOSFET. However, when either the base-emitter or basecollector junctions are forward-biased and conducting, the
capacitance values are drastically changed. When the
bipolar is conducting in the forward direction the baseemitter junction is forward-biased and displays a very large
value of diffusion capacitance. This means that C2 is large
and the dV/dt capability is greatly increased_ If on the other
hand the device is conducting in the reverse direction then
the collector base junction is forward-biased and C1 is much
larger. This greatly decreases the dV/dt capability of the
device. Even if a diode is shunted across the bipolar (0 1 or
02) some small current will still be available to forward bias
the base-collector junction.

Figure 49. MOSFET Model Including Parasitic BJT

The three operating states defined earlier determine the
choice of values for C1 and C2. Of the three conditions the
reverse conduction mode is by far the worst and has the
lowest dV/dt threshold. For the quiescent state for bipolars
and MOSFETs, and the forward conducting state of the
MOSFET, the amplitude of the current pulse due to dV/dt
triggering is usually not damaging except in very fast circuits. In the forward conducting state in a bipolar, C2 is so
large that given the limits on bipolar switching speeds dV/dt
triggering is not a problem. However, in the case where
reverse conduction has occurred, the resulting pulse in a
circuit like that in Figure 44 can destroy both devices. As a
practical matter, it is difficult to measure the diffusion
capacitances so the designer must test the desired device
under actual circuit conductions for dV/dt capability.

Another unpleasant possibility in a MOSFET is that if the
parasitic NPN is turned on it may experience second
breakdown due to thermal instability.
Temperature Effects
The threshold for dV/dt triggering will decrease with temperature for several reasons. Vth in a MOSFET has a negative
temperature coefficient of about 6mV/oC. Similarly, VBE in a
bipolar has a negative temperature coefficient of about
2mV/oC. Typically for a bipolar VBE = 0.7 and for a MOSFET
Vth = 2.0 to 5.0V. The temperature coefficient for the bipolar
is a larger percentage of the threshold voltage than in the
MOSFET so that the degradation of dV/dt due to
temperature-induced threshold shift is more pronounced in
the bipolar.

The Parasitic Bipolar in MOSFETs

The internal portion of Rg in the MOSFET is primarily due to
the gate connection material. In some structures, particularly VMOS, the gate connections are made with aluminum
which produces a very low Rg that does not vary greatly with
temperature. OMOS devices on the other hand use poly silicon gate structures which have a higher Rg with a temperature coefficient of about 0.6 to 0.7%/oC. In the parasitiC
bipolar, RBE will have a temperature coefficient of 0.6 to
0.7%/ oC. In a bipolar switch most of RBE will be in the external circuit and will probably not vary significantly with
temperature.

The present power MOSFET devices all have a parasitic
bipolar transistor as an inherent part of the structure. The
equivalent circuit for an N-channel device is given in Figure
49. For a P-channel device the parasitic transistor would be
a PNP. The base and emitter connections of the parasitic
transistor are connected together at the surface of the die
to minimize the value of RBE but there is still some
resistance in the bulk of the semiconductor material. The
value for RBE will vary depending on the size of the die and
the voltage rating but is generally 20 or less. In devices of
similar design and voltage rating, Cob increases with die
size at the same rate ·as RBE decreases so that 71 remains
essentially constant. Cob is essentially equal to Cds' As the
voltage rating is increased, Cob decreases more rapidly than
RBE increases so that 71 is smaller in higher voltage versions
of the same design.

The ON resistance of the MOSFET has a positive temperature coefficient while the bipolar has a negative temperature coefficient. The result is that at higher temperatures
the MOSFET ON resistance will tend to decrease the amplitude of the current pulse due to dV/dt and the bipolar will
tend to increase the current pulse.

133

A036

D~DIL

The gain of the MOSFET Is not greatly affected by temperature but the hFE of both the parasitic transistor and the
bipolar switch does increase with temperature. This means
that if the bipolar is turned ON more current will flow at
higher temperatures.

~PWM

The duration of the current pulse caused by dV/dt triggering
depends on the length of time eo is above Vth and In the
case of a transistor, the storage time is added to this. The
storage time will increase with temperature.

r-o PWM

If the dV/dt capability of the switch is not adequate due to
reverse conduction, a low Vf or Schottky diode may be
added in series with the drain as shown in Figure 50 and a
separate external diode connected across the combination
(D2)'
Figure 51. Quasi·Squarewave Bridge Converter

As shown in Figure 52, the forward voltage drop (Vf) characteristic is typical for a junction diode. Because of the large
die areas normally used in a power MOSFET, Vf is quite low.

:a
...w

I
I
II

II:

:!l!
I

Figure 50. Method for Eliminating Reverse Conduction

V
00

0.1

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Vso - VOLTS

USING THE INTERNAL DIODE
Figure 52. IVN6000 Diode Forward Voltage Characteristic

The parasitic transistor can be used as a rectifier or clamp
diode in switching regulator circuits. For example (Figure
51), the clamp diode usually added in a bipolar bridge inverter comes for free in the MOSFET. The internal diode has
the same breakdown voltage and current ratings as the
MOSFET itself, because it uses the same silicon, metalization, bond wires and package. The reverse recovery time (t,,)
for the diode can be excellent. In the IVN5000 and 5200
series devices, t" = 60ns and in the IVN6000 t" = lOOns.
There are several reasons for the' high speed. First, the
structure is an epitaxial diode with sharply·defined diffusions. Second, the doping of the p-region is done using an
ion implant machine. The ion implant process produces
dislocations in the crystal structure which can act as
recombination centers to reduce the recovery time. Not all
manufacturers use ion implant techniques, and there may
well be a wide variation in t" for similar devices from different manufacturers or from the same manufacturer at different times when there has been a process change.

A MOSFET may be used as a bidirectional switch or as a
synchronous rectifier. Referring to Figure 53, when the gate
is made sufficiently positive with respect to the source, the
MOSFET becomes essentially a resistor in which the cur·
rent may flow in either direction, source to drain or drain to
source. As long as the voltage drop across rDS(ON) is below
0.6 volts, the parasitic diode will not conduct appreciably
and the FET can be used as a bidirectional power switch
with zero offset voltage. If synchronous rectifier operation is
desired, the gate-source voltage is zero when the drain·
source voltage is positive, thereby blocking the flow of cur·
rent. When the drain-source voltage reverses, the gate is
driven positive and current flows from source to drain. The

134

A036

O~OIL

user now has a majority carrier rectifier with no storage time
and a switching time equal to that of the FET (usually a few
ns). The voltage breakdown rating is, of course, equal to that
of the FET. If the voltage drop across the FET exceeds the
threshold of the parasitic diode, the current is bypassed
around the FET and VI assumes the characteristic of the
diode.

It is recommended that the user parallel devices which have
been matched for Vth to within 5%. This will assure that the
turn-on and turn-off delays due to the gate voltage rise and
fall times, relative to Vth , are nearly equal. The values for
rOS(ON) will also be very close, so that excessive differential
heating is not encountered. Some additional improvement
in rOS(ON) matching may be achieved by providing higher VGS
so that all of the parallel devices run at their minimum
rOS(ON) value.

The designer must keep in mind the dV/dt limitations of the
internal diode.

It should be kept in mind that many MOSFET devices have
gain bandwidth products over 500MHz. It is entirely possible
for these devices to oscillate at very high frequencies,
especially if multiple parallel devices are used. This is often
an unsuspected cause of device failure. If the circuit
designer is using a low-bandwidth oscilloscope during
breadboard development, it is possible to be unaware of the
self OSCillation, and therefore the use of an oscilloscope
with a bandwidth of at least 200MHz is recommended. The
tendency towards oscillation can be greatly reduced by inserting ferrite beads or low-value (50-1000) resistors in
series with the gate leads, as shown in Figure 54.

Go---1
s

(A) NORMAL SYMBOL
FOR N·CHANNEL

(B) DIODE EMPHASIZED

For fast pulse applications, it is not sufficient to merely
match the devices. The circuit must also be reasonably symmetrical so that identical drive voltages are applied to each
gate. At high speeds the inductive as well as resistive
effects must be considered. If, for example, the parasitic in·
ductance in the drain lead of 0 1 is much smaller than that in
the drain lead of ON, when the devices are first turned ON
most of the load current will initially flow through 0 1, even if
the gate drives and threshold voltages are identical.

Figura 53. Diode in MOSFET Structure

MULTIPLE DEVICE OPERATION
The positive temperature coefficient of rOS(ON) Is of great
assistance when MOSFETs are paralleled. It is possible, in
DC applications, to parallel devices without any matching,
and those devices that initially draw the most current will
heat up and shift the current to other devices to more equally
distribute the current. This is exactly the opposite of the
scenario for bipolar devices. While the paralleling of un·
matched devices will work, it is a poor idea because a
higher than necessary dissipation may occur, and in switching applications it is possible for one device to turn on or off
before or after the others, and to have to accept the full load
current. This may force the device to function outside of its
safe operating area.

Variations in the stray gate circuit capacitance and the
device input capacitance can also cause uneven turn-on in
fast pulse applications. The effect of this can be reduced by
equalizing the stray capacitance and minimizing the intergate impedances. For applications requiring switching
times below 10ns, it may be necessary to match the device
capacitances.

RS
GATE
DRIVE

--~--------~------------------+---------+--

Figure 54. Parallel Devices

135

D~DIl.

A036
It should be kept In mind that most of the complications In
paralleling mentioned above apply only for very fast pulses.
Most applications will use transition times well above 10ns,
where simple threshold voltage matching is all that is reo
quired. This Is quite different from bipolar devices where
paralleling more than two devices can become quite complex and expensive. Due to the practical difficulties of
paralleling large numbers of Individual bipolars, (and SCRs
also), the trend has been to develop ever larger Single
devices. As the die size Increases, a point Is reached where
either the thermal capabilities or the available mounting
areas of the low-cost packages are exceeded so that a more
expensive package is required. In addition the heat sink will
now see a concentrated thermal input through the relatively
small package to heat sink contact area. The efficiency of a
heat sink Is better If the heat Input is distributed in several
sources rather than in one.

[

80PO.85
]1.43
Tj-Ta-P ROCH

rOS(ON)ea •AT

(39)

(40)

(Note: Equation 40 is equivalent to Equation 12.)

Calculations:
One O.OS·Ohm device:
P = (O.OS) (252)e(0.005) (110) = S4.2W

OJ -

hs =

While the arguments for using a Single large bipolar device
Instead of multiple smaller devices are well founded, it does
not necessarily follow that the same technique should be
imitated in power MOSFET devices, especially in the light of
the rapid cost Increase of the larger die. The tradeoff may
well be multiple devices with low die and package and
moderate heat sink costs, versus single devices with high
die, package and heat sink costs. Just where the cost
crossover point between single and multiple devices is has
yet to be determined, especially since the very high prices
for the present larger MOSFETs are certain to be reduced
substantially.

Rruc + ROCH = 0.83 + 0.4 = 1.23 °CIW
. 2.
[ 80(S4.2)0.85 Jl.43
110-S4.2(1.23)
=308 In

Because the heat input is concentrated, the heat sink will be
less efficient by 10 to 30% than calculated. For a 20% loss
in efficiency:
Al =370 in 2

Four O.2·0hm devices:
P=S4.2W
- 1.S+0.4 -0 48°CIW
ROCH4
-.

The following design example illustrates the thermal
arguments for paralleling devices.

A2 =

[

8O(S4.2)0.85 ] 1.43
. 2
110 _ S4.2(0.48)
= 120 In

Statement of the Problem:
Using the AHAM #4501 heat sink extrusion (A';" 28 in2/in) the
heat sink length, L, and volume, V, are:

Solve for the heat sink area, volume, and cost and the combined heat sink and device cost. Compare one O.OS·ohm
device to four 0.2-ohm devices.

L1 =13.2in
Vl =64 in 3

L2 =4.3in
V2=21 in 3
V1IV2=3.1!

Operating Conditions:

A 72" section of this heat sink costs about $80, so:

10
Ta
Tjmax
Altitude
Cooling
ROCH

C1 =$14.67
C2 =$ 4.78
Total Costs: One O.OS-ohm device = $76.87
Four O.2-ohm devices = $32.78

=2SA RMS
=40°C
= 150 °C
= Sea level
= Still air convection COOling
= 0.4 °CIW (this is the case to heat sink thermal
impedance due to mounting surface irregularities, etc., for a TO-3 case)

There is a better than 2:1 cost and 3:1 volume advantage to
using the multiple devices.
The O.OS·ohm device prices can be expected to come down
substantially but so will the price of the 0.2-ohm devices, so
it is very likely that four 0.2-ohm devices will continue to be
cheaper than one O.OS-ohm device. There will be some additional assembly charge to mount four devices versus one
device but that should not materially affect the comparison.

Device Characteristics:
O_OS-OHM DEVICE

O_2-0HM DEVICE

TO-3 Case
Rruc = 0.83 °CIW
rOS(ON) = O.OSO

TO-3 Case
R9JC = 1.S °CIW
rOS(ON) = 0.200 @ 2S °C

a=O.S%/OC

Cost = $62.20

Cost =$7.00

If this were a military application, then the junction temperature would be limited to 10SoC and the ambient would be
+SO°C or higher. Recalculating the heat sink areas for
+SO°C ambient and Tj'~10SoC:
Al =15031n 2
A2 = 227 in2
Al/A2 = 6.62!

For this problem the device power diSSipation, P, and heat
sink area, A, can be shown (see appendix) to be:

136

A036

O~OIL

I
1

6y no means does the design example imply that multiple
devices are always superior to a single device. The tradeoff
will depend on device costs and cooling provisions, and the
tradeoff will take the general form shown in Figure 55. In
some situations the additional volume of the multiple
packages may be a problem. In most cases, however, this
should not be a concern. It can also be argued that the in·
creased number of devices reduces the reliability. The
counter argument to this is that multiple devices can be run
cooler due to the improved thermal efficiency and the net
reliability Is actually increased.

Series' Operation MOSFETs
MOSFETs can be connected in series for high·voltage
operation. It is particularly important that all devices in the
same series string come ON Simultaneously, otherwise one
device may take all of the voltage momentarily. The devices
should be well matched for Vth and careful attention given
to producing simultaneous gate drive. In those applications
where the maximum possible voltage capability is desired,
it may be necessary to match the rOS(ON)/VGS characteristic
to assure equal voltage distribution during switching transitions. This is a much more complex procedure than Vth
matching, and should be considered only as a last resort. It
is probably preferable to use some form of snubber network
to equalize the voltage distribution during switching. Analogous to the parasitic inductance in parallel operation is the
effect of circuit parasitic capacitance in series operation. If
differential drain-source capacitances (either in the device
or in the circuit layout) exist in the series string, the transient voltages may not be shared equally.

COSTIVOLUM

Combinations of Bipolar Transistors and MOSFETs

3 DEVICESif.---------/--"-7f----2 DEVICES;f-------""?t':......1 DEVICE,f-------

MOSFETs can be combined with transistors in a variety of
useful ways. The most obvious combination is to use
medium-power MOSFETs to drive high-power bipolars; the
MOSFET is an excellent buffer between TIL or CMOS logic
and large bipolar devices.
Two base drive possibilities are given in Figure 56. In (6) R1
and R2 are selected independently to provide the appropriate values for IB1 and IB2 . If negative bias for 03 is
desired, the source of 02 and the ground pin of the OS0026
may be referenced to a negative potential. Figure 57 shows
a proportionaJ[5] base drive circuit.

POWER_

Figure 55. Cost versus Power Dissipation

V+

(8)

(A)

V+

U
LOAD

~~
r--L----,
I

r
R1
01
IVN5200

..n

I
I

I
I
I
I

182

IVN5200
02

I
I

L--r-__
I

DS0026

Figure 56. Bipolar Base Drive Using MOSFET

137

r.::

I::
11
ii:
il,

il
if.

i'
!

A036

O~OIL
v+

DSoo26

Figure 57. Proportional Base Drive Circuit

In addition to using MOSFETs to drive bipolar transistors,
the two types of devices may be combined into a compound
device. Some of the possibilities are shown in Figure 58. The
Darlington connection (58A and 588) using a MOSFET for
the driver will display essentially infinite beta. The cascade
connection shown in Figures 58C, 59 and 60 is a means to
obtain fast switching from a large high-voltage bipolar by inserting a low-voltagfl, 10w-rOS(ON) MOSFET in the emitter.
Another Interesting possibility is to parallel a MOSFET and
a larger bipolar transistor. The MOSFET and the transistor

are driven on simultaneously but due to the relatively slow
turn-on of the bipolar all of the current flows initially through
the MOSFET. When the bipolar is fully on (approximately
11's) nearly all of the current flows through it. The bipolar
has a much lower voltage drop than the MOSFET. At turn-off
the drive is removed from the transistor first, and approximately 1 to 3JLS later, the MOSFET is turned off. The staggered turn-off should be relatively easy to implement in the
drive logic. This combination displays the fast switching
time of the MOSFET along with the low VCE of the transistor.

(A)

(B)

r------111

DARLINGTON

(C)

BIAS

0--.--1::.

CASCO DE

(D)

PARALLEL

Figure 58. BJT/MOSFET Combinations

138

O~OIL

A036
+80V

5FFIO

r--"--~--4-- Vo
5FFIO

If
ts

tr -

--'VV\,,--------f---1

84ns
90ns
ns

3x1VN5200

lOll

VIN
(FROM
BI.DIRECTIONAL
DRIVER)

4.7K

Figure 59. Cascode BJT/MOSFET Clrcuil

(A)

(B)
+250V
0.010.47.F
LOAD

! 5A

300V

2N6582

BU407

lOT # 28
lOOpF
IVN5200

JL
2.2K

03
2x1VN5200

l00pF

Figure 60. Proporlionally Driven Cascode BJT/MOSFET

139

O~OIl,

A036
BIBLIOGRAPHY

4. D. Gyma, J. Hyde and D. Schwartz, "The Power MOSFET
as a Switch, from a Circuit Designer's Perspective," Pro·
ceedings of Powercon 7,March 1980, pp. D1·D16.

1. R. Erickson, B. Behen, R. D. Middlebrook and S. Cuk,
"Characterization and Implementation of Power
MOSFETs in Switching Converters," Proceedings of
Powercon 7, March 1980, pp. D1 to D17.

5. R. Severns, "A New Improved and Simplified Proportional
Base Drive Circuit," Proceedings of Powercon 6, May
1979.

2. H. Owen, T. Sloan, B. Rimer and T. Wilson, "Switching In·
terval Modeling in Very High Frequency, High Power
MOSFET Converters," Proceedings of Powercon 7,
March 1980, pp. G1·G13.

6. R. Severns, "Switch mode Converter Topologies - Make
Them Work for You!," Intersil Application Note AO·35,
February 1980.

3. Dr. R. Redl, Technical University of Budapest, Private
Communication, 9 April 1980.

7. "SOAR - The Basis for Reliable Power Circuit Design,"
Phillips Application Note ##68, 30 April 1975:

140

D~D[b

A037
High Performance Off-Line
Switch Mode Power Supply
by Rudy Severns
The surface topology of the IVN6000KNT has been designed
for maximum breakdown voltage and drain cllrrent while
minimizing capacitance and switching time for a given chip
size.
Power MOS FETs offer significant performance/cost advantages over bipolar power transistors in many applications. A
comparison of devices is shown in Table 1.

INTRODUCTION
Within the next year, the Switch Mode PowerSupply (SMPS)
market is expected to grow from 30% to well over 50% of the
power supply business. Users are demanding low cost and
high reliability in a smaller, lighter package, and recent
advances in the development of high voltage power FETs are
having a significant impact on the design of SMPS's. The
IVN6000KNT has several unique characteristics ideal for
SMPS applications Clever utilization of these qualities results
in substantial system gains over traditional bipolar designs.

Safe Operallng Area Rating (SOAR)
The Safe Operating Area curve forthe IVN6000KNT is shown
in Figure 2.

450 VOLT VERTICAL POWER MOS FET
Fabrication
The IVN6000 family is fabricated in Intersil's new vertical
DMOS process. "Self-aligned" processing (with fewer
masking operations and no critical etching) eliminates
many of the manufacturing and reliability problems which
plagued the prior art. A cross section of the vertical DMOS
structure is shown in Figure 1.

OPERATION IN THIS REGION IS
10 c---f~L:::IM:::'.:..;TE::D-=B:::V.::'D::.S:::IO~N)_ _ _ _ _ _----.

....-,---1'",
~

.l
<',

I' "

GATE

SINGLE PULSE
Tc = 2SoC
'TJ MAX = 150G e,
ROJC = 3.5' c/W I

''"
"
"

"" ""
"", , ' '

I
I
I

..
.5

N+ SUBSTRATE

Vos - VOLTS

CURRENT FLOW
DRAIN

Figure 2. Safe Operating Area (SOM

Figure 1. Vertical DMOS Structure

Table 1.
POWER FET

1.
2.
3.
4.
5.
6.
7.

BIPOLAR

Advllntages
Wide Safe Operating Area (SOA)
Very High Current Gain
Very Fast Switching
"Free" Reverse Diode
No Thermal Runaway
Drive Simplicity
Inherent Current-sharing when paralleled

Advantages
1. Low Saturation Voltage
2. Availability

Disadvantages
1. Static Sensitivity
2. Comparatively High Conduction Losses

Disadvantages
1. Device Storage Time - Losses, Frequency
Limitations
2. Base Drive Complexity and Power Dissipation
3. Current Hogging when Paralleled
4. Thermal Runaway
5. SOA Limitations

141

A037
18

vl~ ~v?D'

10 -lA
16
14

680P,/
12

~
0

200~

50V

375V

'/ Ii

1
I

II V630 l
/ I /

Vj
/ /

1
l

/
I

i/212PF

-2

V
o

1.0 1.1

1.2

Vso - VOLTS

QG - nano COULOMBS

Figure 3. Gate Drive Dynamic Characteristics

Figure 4. Diode Forward Voltage Characteristics

During the brief transition when the power MOSFET
switches, instantaneous peaks of 450 volts at 7.5 amps
(3375 watts) can be tolerated. Typical worst case SMPS
conditions are well below these limits, thus insuring a wide
operating margin.

2.0
ID

~ lA

1.8

Vas "",10~

1.6

MOSFET Switching Properties
Power FETs are voltage controlled devices (as opposed to
bipolar transistors which are current controlled). Since
the input is capacitive, gate charge determines the drainsource enhancement.
Figure 3 shows the IVN6000KNT drive characteristics in
nano Coulombs.

fil
N

1.4

,.<

1.2

::;

'"0Z

1.0

a
e

.8
.6

VGs = 4V

/V'

I .......

Since the charge
0= Ig ts where

Ig = Gate Current

ts = O/Ig

then

= Switching Time

-60

The switching time is dictatad almost entirely by the applied gate current since there is no minority carrier storage
time.
Switching a 1 A load to 375 Volts in 100 nanoseconds
requires only 100 milliamperes of gate drive. This feature
makes possible the use of extremely simple and reliable
drive circuits, as well as operation far in excess of the
traditional 20 kHz switching frequency.
Integral Reverse Diode
Inherent in the power MOSFET is a fast recovery epitaxial
diode with very acceptable low forward drop. This "free"
reverse diode serves an important role in many SMPS
topologies. During the time interval in which the power
MOSFET is off, the reverse diode provides a path for
inductor current. Bipolar designs require the addition of
an "extra" discrete fast-recovery diode. The IVN6000KNT
integral reverse diode is fast and also exhibits low loss.
The diode forward drop characteristics are shown in
Figure 4.
Under typical operation, a forward drop of < 1.0 Volt is
common.

-40

-20

100

120

140

Figure 5. ON Resistance vs. Junction Temperature
(Vtls

= VGS -

VGS(th))

Paralleling MOSFETs
The IVN6000KNT can be paralleled without fear of current
hogging or thermal runaway. This is significant in that it
allows the designer to scale up/down designs by merely
paralleling devices. The device has a positive temperature
coefficient for rOS(on). See Figure 5.
The device conduction losses are
Pc = VoS2 /rDS(on) where VDS = Drain-source on voltage
rDS(on) = Drain-source on resistance

Given the situation in which two paralleled devices have
different rOS(on) values, the device with lower ON resistance will dissipate the most power. Junction heating
increases rOS(on) and reduces its power dissipation, and
this negative-feedback insures stable operation between
paralleled devices.

142

A037
DESIGN NOTES
The complete 5V/50 Amp off-line (100/220 VAC) SMPS
using power MOSFETs is shown in Figure 6. The system
specifications are as follows:
SPECIFICATIONS:
Input
Characteristics:
DC Output
Ratings:
Output Ripple
and Noise:
Overload
Protection:
Over Voltage
Protection:
Temperature
Rating:
Cooling:
Thermal
Protection:

115/220 + 10%-20% VAC, 47-63 Hz
5V at 50A
50 mVpp Maximum
Fold-back type with automatic
recovery
Set at 5.6V
Operating O°C to +40°C at full-rated
power
Convection
Internal thermostat shutdown for
over temperature

Remote
Sensing:
AC Under
Voltage Inhibit:

Inhibits operation below 90/180
volts AC input

Slow Turn-On
Circuitry:

In-rush current limiting thermistor,
slow-start pulse width modulation

Available to provide compensation
for line losses.

Power Mesh
The converter configuration chosen for this application
was the half bridge. As illustrated in App. Note A034,
other topologies may result in lower conduction losses,
however, the half bridge has several advantages. A prime
consideration is that maximum voltage seen across the
FETs cannot exceed the rail voltage. For 110/220 VAC line
this represents a peak of 360 VDC. However, to insure
sufficient guard banding to accommodate line/rail spikes
and low temperature BVoss de-rating, the IVN6000KNT
-450 volt power FET is recommended. The half bridge is
also advantageous in terms of the transformer design. A
smaller core, without primary center-tap, and a favorable
turns ratio are derived.

Other key factors in selecting this topology were:
1. Well-understood and easy-to-stabilize feedback loop.
2. Relatively low RFI.
3. Circuit simplicity - single transformer driver, utilization of the FET integral reverse rectifier.
An operating frequency of 60 kHz (per switch) was
chosen. This is a compromise in that only modest improvements in size, weight, bandwidth, etc., are derived as a
direct result. The major improvements are achieved
through circuit simplification. The criterion for selecting
this frequency was the availability of components; i.e.,
diodes, capacitors, integrated circuits, etc.

+19V

-=
2k

2k
2N3702

10K

16
1k

200n

OUTPUT

5V/50A

* T,. T2 -

r--"'-'~I----1"-----<>H

see TeXT

.... KEYSTONE RL 7605-6 24-73-89

Figure 6. Power MOSFET SMPS

143

A037
The output is straightforward, 'consisting of a full wave
center-top configuration and LC filter. 75HQ Schottky
rectifiers are used to reduce rectifier dissipation. Worst
case losses for the Schottky diodes is 35 watts.
The half bridge consists of two pairs of IVN6000KNTs.
Paralleling limits the conduction losses to a maximum of
six watts/FET or 24 watts total. Each device sees less than
1.25A RMS and 2A peak, well within the rated 2.25A RMS
and 7.5A peak.
The power transformer consists of a single primary and
center tapped secondary, with a turns ratio of 15:1 :1. To
achieve high efficiency it is important to keep the magnetizing and leakage losses low. It can be shown that a
magnetizing current 1m = O.4A results in a worst case
increased dissipation of 3W (total). This being acceptable,
the minimum magnetizing inductance Lm becomes:

Lm=~

Lm - 4.5mH

Losses due to leakage inductance must also be minimized
since:
PLK

= LLK

X F

Paying close attention to the magnetic design, LLK as low
as 4.5 I'H can be achieved. This results in a maximum
leakage loss PLK - 3.7 watts. The RC snubber network
absorbs most of this energy. Core and copper losses
account for about 2.5 watts. A ferrite, toroidal core was
chosen with filar windings; this structure tends to reduce
leakage inductance and RFI.
FET Driver
Of first order is the switching losses. The energy dissipated during the switching interval is:
Ws= I t Vos(tl1o(tldt

The switching losses can then be expressed as:
Ps = fs [ WS(on)

+ WS(Off)]

Assuming constant current and linear voltage ramps, the
expression for the switching losses becomes:
PS-fSXVOS X 10 Xts

A more exact expression for switching losses can be
derived, however the contri bution of losses due to switching is small in comparison to other system losses.
Acceptableswitching losses are obtained when the switching time is 40ns; i.e., Ps = 0.75 watt/device. The gate drive
current required to achieve a ts of 40ns is

This is derived with the OS0056, high speed, monolithic
dual clock driver, which provides up to 1.5A at 20 volts
output drive. Drive transformer T 1 is tri-filar wound 1:1:1
with a magnetizing inductance Lm - 7mH and leakage
inductance LLK - 0.7 I'H. Minimization of LLK is essential.
It can be shown that LLK dominates in the calculation of
switching time where:

,~
VOT

ts~
and

VOT = VORIVER - VTH 10 or ts - 37 ns.

This drive configuration has several advantages; Foremost is the condition that both outputs can never be on
simultaneously. (Such a condition could be destructive to
the FETs.) Furthermore, when power is removed, both
outputs drop to zero rapidly, preventing any voltage
spikes or asymmetrical charging. The circuit operates
Class-C, consuming power only when an output is high.
These functions are concisely achieved with a total of 10
components.
Switching Regulator Subsystem
Many of the basic characteristics of the power supply are
controlled by the regulator subsystem. The circuit shown
in Figure 6 uses an SG1525A integrated circult to provide
output regulation via duty cycle variation of the drive
signal to the OS0056's. The SG1525A provides the
required reference voltage on pin 16, the operating
frequency of the system is controlled by the oscillator
components on pins 5 and 7, and the circuit provides an
automatic slow-start function through the capacitor on
pin 8. Overvoltage protection is achieved by allowing the
2N3702 to activate the shutdown circuitry at pin 10.
Frequency compensation is controlled by the components between pins 1 and 9, which set the medium frequency
dynamic performance of the supply and also the loop
stability. The LM339 and associated resistors provide
short circuit current limiting with fold-back. (Note that the
SG1525, which can be used in the same circuit, has a
slightly different pin out.)
More complicated control functions can be realized by
replacing the LM339 with devices such as the SG1542
through SG1544. Somewhat improved dynamic response
can be achieved by using the TL494 in place of the
SG1525A, and incorporating feed-forward compensation.
This device also includes a current limiting circuit,
obviating the need for the LM339, as shown in Figure 11.
Input Circuitry
The input circuitry is standard. A thermistor limits the
in-rush current, and a shorting clip allows the option of
110 VAC or220VAC; a 3-terminal pass regulator provides
power for the controller and driver; a 2-transistor, resistor
network coupled to the LM317 provides "under voltage"
protection. The auxiliary supply is regulated to 19 volts.

19 =

SYSTEM PERFORMANCE
where

Og -

10 nano Ceu lembs/device

or
Ig - 0.25A/device

Figure 7 is an oscillograph depicting the power transformer voltage and current waveforms. Figure 8 displays
the voltage waveforms in the half bridge. The actual FET
gate-source and drain-source waveforms are expanded in
Figure 9. Current limiting is the fold-back type. The resulting output characteristics are illustrated in Figure 10.

144

A037

160
V01AGE

160

,.~
100
2.0

100

~ 1.0

50 t-CURRENT

VOLTAGE

f-..... V-

/V
V

2.0

1.5

/cURRENT

-50

-100

-1,0

VOLTAGE - 5OV/div
CURRENT - 1A/div
TIME BASE - 2 j.tsec/div

-160

-2.0

lJ'

0.5

VOLTAGE-50V/div

TIME BASE - 20nsac/div
20..

Figure 78. Voltage/Current Waveforms Across T2. 25A Load.

Figure 7b. Voltage/Current Waveforms Expanded. 25A Loac;L

160
100

150

100

Il.......

5OV/div

-100

-nL

/ORAIN -SOURCE VOLTAGE_

"'-

I I

50v/d;,

GATE - SOURCE

10V/dlv

VOLTAG~
...........

10ns

+19V--'\M,----....:=t=::..:.::........

/
/
20

100

---

Figure 9. FET Switching Waveforms (5V125A Load)

f--

rIME BAsk -10nsec/div

Figure 8. Half Bridge Waveforms (5V12SA Load)

V--

-20

/" ~

~IME BASE - ....,/d;,
GATE DRIVE wAveJoRM
20Vldiv

-:7

OUTPUT -1/2 BRIDGE

-0

CURRENT - O.6A/div

120

PERCENT-RATED OUTPUT (CURRENT)

Figure 11. Alternative Control Circuit

Figure 10. Current Fold-Back Characteristics

145

A037
The complete SMPS has a total of about 90 circuit elements,
compared to a typical bipolar design which has 140. Calculated MTBF was 3.7 years, versus 2.9 for the bipolar.
Current MOSFET prices tend to somewhat offset the cost
savings derived by circuit simplification, but with the
anticipated future price reductions substantial savings
can be realized.

achieve significant system advantages including lower
cost, high reliability, reduced size and weight. and excellent electrical performance. The performance trade-offs
are listed in Table 2.

ACKNOWLEDGEMENTS
The author would like to thank Rudy Severns for his
numerous inputs; Brian Smithson, BruceHunter, and Janis
Jenkins for laboratory work; and Peter Bradshaw. Larry
Goff, and Dave Fullagar for general support.

A clean mechanical layout is the key for stable operation;
printed circuit boards should be double sided and groundplane construction should be used. Using the circuit of
Figure 6 in a far from optimized configuration, a power
supply measuring 6" x 9" x 3-1/2" and weighing a mere
41b. 4 oz. was fabricated, see Figure 12.

OTHER APPLICATIONS BULLETINS
A034, ''The Design of Switchmode Converters Above
100kHz," by R. Severns.
A035, "Switchmode Converter Topologies - Make Them
Work for You," by R. Severns.

SUMMARY
Recent advances in power MOSFET technology are
having an impact on switching powersupply design. Bipolar transistors have been replaced by power MOS FETs to

Figure 12. 250 Watt FET SMPS

COMPARISON: FET vs. Bipolar SMPS

Table 2.

FET

BIPOLAR

Advantages

1. Proven technology and long track record

1. Significantly reduced circuit complexity
and component count
2. Improved reliability
3. Simplified manufacturing and test
4. Low cost
5. Straightforward family expansion
6. Reduced size and weight
Disadvantages
1. No track record
2. Potential RFI problems

1.
2.
3.
4.
5.

146

Disadvantages
Poor relative reliability
High circuit complexity
High manufacturing cost
Limited design flexibility
Larger weight/volume

A038
Power MOSFETs
for Analog
Circuit Design

Ulb

U
(
.,

Bruce D. Rosenthal

INTRODUCTION

DEVICE BEHAVIOR

Although the power MOSFET has received widespread
attention for its merits in switching applications, these same
devices offer many advantages to the linear designer as well.
Table 1 summarizes the advantages of power MOSFETs over
bipolar transistors in linear applications, which include
amplifiers (audio, servo, R.F.), oscillators and voltage and
current regulators. This note is intended to familiarize
designers with the power MOSFET as a linear circuit element
and present a few design examples.

The ideal MOS device has two fundamental regions of
operation. The equations below define these regions, which
are shown graphically in Figure 1. Refer to Table 2 for the
meanings of symbols used below. Equation (1) is valid in the
linear region, Where V'GS > Vos. Equation (2) defines the
satUration region where V'GS < Vos.
10 = K' (2V'GSVOS -V20S)

(1)
(2)

Table 1. FETs vs Bipolar for Linear Use
POWER FETs

BIPOLAR TRANSISTORS

Advantages

1.
2.
3.
4.
5.
6.

1. Low Cost
2. Well Understood
3. Good Availability

Wide Safe Operating Area (SOAR)
High "ft " and Breakdown Voltage
Very High Current Gain
Drive Simplicity
Linear Transfer Characteristics
High Output Impedance

Disadvantages
1.
2.
3.
4.
5.

Disadvantages
1. Static Sensitivity
2. Limited Design Experience

Low IT
SOAR Limitations
Base Drive Complexity
Loop Stability Problems
Non-linear Transfer Characteristics

Table 2.
Symbol

Name/Definition

VGS

Gate-Source Voltage

VTH

Threshold Voltage

LINEAR
REGION

V'GS

Enhancement Voltage (VGS -

Vos

Drain-Source Voltage

Drain Current

,
I

SATURATION
REGION

,
I

VTH)

~'---------VG'3

A Constant Related to the Device Geometry

gl.

Transconductance

Useful High Frequency Limit (Limited by
Parasitic Gate Resistance and Capacitance and
Package Inductance)

go.

Output Conductance =

Output Resistance =

..,.;-----------VG.2
1~&------------VGS1
vo.

Figure 1.

~VDS

1
gas

C g•

Parasitic Gate to Source Capacitance

Cgd

Parasitic Gate to Drain Capacitance

Cd.

Parasitic Drain to Source Capacitance

Based on these fundamental equations, other key relationships
can be derived. The transconductance (gl.) can be described
by the following equations.
Qt.

Qf. =

2K' V'GS

(3)

2v'K'iD

(4)

(408) 996-5000 TWX: 910-338-0171
lot 8

A038

U~OI.L
TRANSFER CHARACTERISTICS

GATE

10 t--

V
1/

IVN6000
VD = 200V

lL
/

/
/

CURRENT FLOW
DRAIN

Figure 2. Vertical DMOS Structure

Figure 2 is a cross section of a typical power MOSFET with a
simplified equivalent circuit shown in Figure 3.

0
·2

Beginning with the input, rg is the series gate resistance. In the
device design, rg is determined by the process used; (metal
gate or poly gate) and by surface topology. The internal
capacitances are highly voltage dependent, except for egs as
shown in Figure 4.

.... j.;"
-1

234

V'GS- VOLTS

FIgure 5. Drain Current vs. Gate-Source Voltage

TRANSCONDUCTANCE CHARACTERISTIC

Best high frequency performance is obtained under conditions where substantial drain-source and drain-gate bias is
applied.

IVN6000
VDS = 200V

Drain-source current flow is determined by:
(5) .

IDS = Qls v'GS

,.,. i-"'"

Referring to equations (2), (3), and (4) for the saturation
region, we can predict the drain-source output behavior.
Typica( output characteristics for the IVN6000KNT are shown
in Figures 5, 6, and 7.
GATE

.rg

V
.....V

DRAIN

cg•

Cg•

It'

o-2

-1

V'GS SOURCE

VOLTS

FIgure 6. Transconductance vs. (.;ate-Source Voltage

FIgure 3. Equivalent Circuit

CAPACITANCE VS, DRAIN·SOURCE VOLTAGE

TRANSCONDUCTANCE CHARACTERISTIC

IVN6000
VDS = 200V

IVN6000
VGS=O

...

1000

= 1MHz

CI.

r.l

V
1/

100

I--' I-'

'.L,-'-..............""-.........u..w.u~IO:--'.......='-"I"::OO,......................:':!,000
V DS - VOLTS

FIgure 4. Device Capacitances

2018

ID-AMPS

FIgure 7. Transconductance vs. Drain Current

A038
OUTPUT CONDUCTANCE
Vs

IVN6000
VDS ~ 200V

....-----+-----<: OUTPUT

(
,g
E
"-

INPUT 0---1~-+--~

C,N

Figure 10. Feedback Bias Configuration

Again, R1 and R2 can be made very large because of the
MOSFETs input impedance. In this example:
lo-mA

In linear applications the gain factor (1') is very important. This
is defined in equation (6) by:
p,=gfsro

whe,e:

(A, + A2)

Fogure 8. Output Conductance YS. Drain Current

(6)

'0 = llgos

Like gIs, ro is a function of drain current (ID) as shown in Figure
8.
The internal reverse diode (DR) is a fast recovery (100nsec
typ.) silicon diode. The forward conduction behavior is similar
to standard PN junction diodes.

ID = A3 - vT

(8)

A2 A3

Normally, R1 and R2 are chosen to set up a current.
In biasing MOSFETs for linear operation, the designer must be
aware of the fact that (as with bipolar devices) thermal runaway
is possible because of the negative temperature coefficient of
the threshold voltage VTH. The resulting change in drain
current for increased junction temperature with fixed gate bias
is shown in Figure ". This effect is most pronounced at low
current. Stable biasing can be achieved with feedback, most
simply by adding a source resistor as in Figure 9. Thermal
transducers such as the Intersil AD590 or conventional
thermistor can also be used.

BIASING

CURRENT REGULATORS

Biasing power MOS devices for linear use involves many of the
same practices employed with bipolars with one exception: the
gate current required to establish equilibrium is practically
zero. Two rudimentary configurations are shown in Figures 9
and 10.

The current regulator is a fundamental building-block to many
circuits and systems. The power MOSFET is particularly well
suited for this application, for several reasons including:

In Figure 9, resistors R1 and R2 can be extremely large since no
D.C. current flows. R4 is used to stabilize the electrical and
thermal operating points. The quiescent drain current is
approximated by:
Vs R2

~ (~

1. Extended SOA, permitting a wide VII curve.
2. Minimal gate drive requirement, thus eliminating the need
for multiple Darlington drivers.
3. High frequency response and easy loop stabilization.
4. High output impedance.

)
-VTH

FIXED BIAS
DRAIN CURRENT vs. TEMPERATURE

(7)

In applications where a source resistor cannot be used, the
circuit in Figure 10 can be applied.
Vs

--~--.=.....---.,.---

lyJJ

IVN6000

YGs~2V

«
OUTPUT

INPUTo--j

1--4-----' I

I
E!

C,N

cs
.0 1
~

i-" I-'"
~

I-'" f..-

YGsL

I-"' I-"'f.-""

TEMPERATURE -

Figure 9. Simple Bias Configuration

YGsL

00
0

Figure ". Drain Current

3 of 8

A038
10

"\..

\""-

THERMAL LIMIT
REGION

,,-/

Vg-=-

•,

......
IVN6200KNT
2N6543,

./
Figure 13. Simple Current Regulator

!:::==SECOND BREAKDOWN
f---LIMIT REGION

200

I
I

0.01

100

160
1000

DRAIN-SOURCE/COLLECTOR - EMITTER
VOLTAGE (VOLTS)

lBV

16V

14V

Figure 12. MOSFETs have Extended Safe Operating Area (SOA)
Vg -12V

A comparison of SOAs is made in Figure 12 between the
IVN6200KNT MOSFET' and an equivalent bipolar device
(2N6543). At low voltages the devices are similar, however
above 50 volts second breakdown severely limits the usefullness of the bipolar transistor. For linear applications where
the transistor must simultaneously support large amounts of
voltage and current, the MOSFET is the device of choice.
Figure 13 shows a power MOSFET in a very simple and useful
current regulator circuit. As a first approximation:

IO~ Vg-VTH

(9)

0
Vg

10V

0
V -4V
0

100

200

300

400

:'i

OUTPUT VOLTAGE (VOLTS)

Figure 14. Output Characteristics of Figure 13

In order to make equation (9) exact, the gate enhancement
voltage must be taken into account. This may be found from
equation (2) and leads to:
Vg = VTH
= VTH

+ V'GS + (lORS)
+

1101

.JiD + IORS
K

Equation (10) gives the exact relation between drain current
and gate voltage. However, in most cases where enhancement
is fairly low, equation (9) is more useful.
The source resistor Rs provides gate bias feedback which
greatly improves the output impedance of this regulator. An
increase in the drain voltage acts to increase ID and this
increases the voltage across Rs; this lowers the enhancement
voltage and tends to reduce ID, counteracting the increase,
The complete expression for output impedance is:

'0 = RS + 'oIl + RS 9fs)

,., RS

'0 ilfs

Figure 15a. Linear Current Regulator

Ill)

Figure 14 shows the curve-tracer characteristics of the circuit
of figure 13 for different values of Vg and with Rs = 100 ohms.
Note the flat characteristics out to 400V.
Even higher values of output impedance can be obtained by
increasing the loop-gain back to the gate. Figure 15a shows
the general form of a linear current regulator using a Power
FET as the controlling device. In Figure 15b, the small signal
model is inserted into the circuit in order to calculate output
impedance (notice that this model ignores DC operating point
considerations).

Yas

Analysis of 15b shows that:

'0 = '0 + RS + 9fs '0 RS 11 + A)

(12)

(b)

" QfsRS'oA

Figure 15b. Small Signal Model

4018

500

O~OIb

A038
It is desirable to keep the sense resistor (Rs) low, since power
dissipation there is undesirable. This, however, requires that
the loop gain (A) must be increased in order to improve output
impedance.

(

A virtually ideal current regulator can be realized by teaming
up a Power FET with a low-offset operational amplifier, as
shown in Figure 18.
+12

The circuit in Figure 16 achieves sufficient gain with the
addition of only one resistor and transistor. The voltage
reference is the base-€mitter voltage of the transistor, and the
current 10 is given by
VBE

OUTPUT

113)

10=%

and the voltage gain from source to gate is given by

ICLB069

A=-

114)

where r. is the effective emitter resistance, so that the output
impedance is given by:
(RL)
Ro'" RS ro 9t. -

(15)

(re)

Figure 18. "Ideal" Current Regulator

VOLTAGE REGULATORS
In voltage regulators, as in current regulators, the low drive
requirements and extended safe operating area make the
Power MOSFET an ideal choice as the regulating device. The
same properties which allow the MOSFET to switch at high
frequencies give it an excellent transient response time in linear regulator applications.
The most basic configuration (shown in Figure 19) references
the gate directly to a zener or other voltage standard. The
output voltage will be:
Vo

(16)

Vz - VT-_
9t.

As seen from this equation, the effective source impedance is
Figure 16. Current Regulator with Loop Gain

The circuit of Figure 16 suffers from the drawback of needing
an external voltage supply. It is possible to get around this, at
some cost in performance, by tying the gate voltage supply
into the drain as shown in Figure 17. Notice that the zener
pullup resistor R2 appears across the drain-source terminals,
limiting the maximum output impedance. An additional
drawback is that the Circuit does not come into regulation until
the zener turns on, which occurs when the drain-source
voltage is around 50V. However, the two-terminal nature of the
circuit makes it useful in situations where external supplies are
not available.

1
9t.

Load regulation (ignoring Vz variations) will be 1+ 9t. RL

VOUT

r--t---J>o.,'VIr-~(+)

1Mll

vz= 10V
Figure 19. Basic Voltage Regulator

Using low threshold devices will keep the minimum inpuV
output differential voltage low.

(-)

Figure 17. Two-Terminal Current Regulator

Once again, the performance will be dramatically increased by
increasing the loop gain. As with the circuit of Figure 15a, both
load and line regulation will be improved bya factor of the loop
gain (A).
5 of 8

A038
Figure 20 shows such a circuit. Here the feedback gain is equal
to 2fjR5 (13 is the current gain of Q2, Q3). Replacing R5 with a
constant current diode would result in further improvement.
Note that all the currents, except for the actual power flow, are
very small owing to the very small drive requirements of the
Power FET. The absence of second breakdown in the FET
simplifies design considerations.
V2 (R, + R2)

zation problems, excellent high frequency response, fewer
components, and lower cost than competitive bipolar designs.
A rudimentary MOSFET amplifier is shown in Figure 22. FET
Q, and resistor R, form a common source amplifier. The gain
for this stage A, = gIs, R,. Replacing R, with a constant current
source will increase the gain significantly. Q2 and R2 form a
low impedance source follower. The gain for

vo =----

1If. R2
A2 = - - I +9f. R2

IVN5200KND

~-~---4r----~--'

and the output impedance Ro

= R2/1

+ Qf. R2

The combination of stages A, and A2 provides both high gain
and low output impedance; The high input impedance of stage
A2 provides little or no loading to stage Q,. The output current
sinking capability can be increased with "active pull-down", as
shown in Figure 23; Transistor Q2 is driven in opposite phase to
Q2. In this configuration, the loop gain

V,IN

VOUT

R,
AOL=A, eA2"'-·
R2

------~------~--------.------(+)

Figure 20. High Performance Regulator

A quick and compact regulator can be made quite simply with
a low power integrated voltage regulator and a Power
MOSFET, as shown in Figure 21. The circuit shown can
provide up to 5A and 25V. Higher voltages can be obtained by
floating the regulator. The FET can be driven directly from the
regulator, eliminating the intermediate drive stages required
by high current bipolar devices. The addition of the external
FET will improve the load and line regulation of the regulator
by a factor of glsRL. Other parameters of the regulator are
unchanged.

OUTPUT
INPUTJ
(-)

Nearly every aspect of linear voltage regulators can be
improved or simplified by using Power MOSFETs in the
output. Increased efficiency, faster transient response and
extended operating range are among the benefits derived. In
most cases, it is possible to double current capability by simply
putting two matched-threshold devices in parallel without any
additional balancing modifications.

Common· Source

Amplifier

Figure 22. Linear Amplification

IVN5200KND
(+)

~-~----,

(-)
Source· Follower
Amplifier

----~---~---~--- (+)

(+)

R,
VOUT

fdbk

OUTPUT

R2
(-)~----~~----~--o (-)

INPUTJ
(-)

Figure 21. Ie-Controlled Regulator

MOSFET AMPLIFIERS
The Power MOSFET offers unique advantages when applied
to amplifier design. An immediate benefit results from the low
drive requirement. Large voltage and power gains can be
realized with few amplifier stages, resulting in minimal stabili60! 8

Common· Source

(-)
Source· Follower

Amplifier

Figure 23. Linear Amplification

A038
-~---------'--(+I

(
I

I
I
I
I
I

-.J

OUTPUT

N
(QUASI·PI

(-I
R1

~~----4---~------~-(-1

• Complementary, But Not Totally

(a)

Symmetrical Because of Differences
Between Devices

Figures 24a and b. Complementary vs. Quasi·Complementary Output

More sophisticated output forms are also possible. For
example, a complementary and quasi-complementary output
are compared in Figure 24. These circuit forms can operate
cJass AB or B. In Figure 24a the classical full complementary
OlJtput is implemented. Although a limited number of
Pchannel MOSFETs are now available, matching P and N type
devices for gm and capacitance is not possible due to
fundamental differences between Nand P type silicon, and
using identical devices in quasi-complementary output stages
provides the best output symmetry. In Figure 24b, a
quasicomplementary output is shown using identical output
devices. The cost of the additional components required is
offset by the higher cost of P-channel devices. The operation
of the quasi-P device is shown diagramatically in Figure 25.
An amplifier, referenced to the source, is connected with its
non-inverting input fed back to the drain of an N-channel FET.
The amplifier's inverting input becomes the effective gate and
the source becomes the effective drain. This compound
transistor operates as follows: Application of a negative VGS
(effectively) generates a positive VGS (true) on NMOS FET.
This forces the source (true) to pull up as would the drain of a
P-channel device. Circuit operation is very predictable. The
effective transconductance and threshold voltage are simply:
gts( el = A 9fs

SOURCE

DRAIN
P·CHANNEL
SOURCE (EFFECTIVE)

(171

and

DRAIN (EFFECTIVE)

(181

By matching an N-channel power FET and high gain op amp,
extremely high gm(e) and low VTH(e) can be derived.

QUASI· P·CHANNEL

Figure 25. Quasl·Complementary Power MOS

7 018

D~DIL

A038
Several differential quasi-complementary output configurations are possible. Two examples are shown in Figures 26a and
26b.
These forms can be directly driven from a low power
differential amplifier stage. The circuit of Figure 26a offers
excellent common mode rejection (CMR), however, the gate
enhancement is limited to approximately 2VTH. This should
not be a problem when using high threshold devices, but if
desired this restriction can also be overcome by using the
circuit of Figure 26b. Note that this circuit, however, is sensitive
to common-mode signals.

ACKNOWLEDGEMENTS
The author would like to thank B. Hunter, T. Grant, J. Meador,
J. Zis, N. Zommer and A. Berger for their contributions.

- - -....-----0+ +

- ....- - -...---0 + +
,-----0(+)

(-)o---+--r

.------0(+)

(- )0---+--1:'
INV5200

INV5200

(+)

OUTPUT

INV5200

- _ - - - - -_ _----0(-)

--------_----0(-)

(0) CURRENT FEED CONFIGURATION

(b) RESISTOR DRIVEN CONFIGURATION

Figures 26a and b. Differential-Complementary Output Configurations

U~OIl

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201 Ogden Avenue, Suite #230
Hinsdale, illinois 60521
Tel: (312) 986-5303
TWX: 910-651-0859

10300 N_ Central Expwy_
Suite 225;nI
Dallas, TX 75231
Tel: (214) 369-6916
TWX: 910-860-5482

CANADA
338 Queen Street East, Suite #208
Brampton, Ontario L6V 1C4
Tel: (416) 457-1014
TWX: 610-492-2691

INTERSIL INTERNATIONAL SALES OFFICES
INTERNATIONAL
MARKETING
HEADQUARTERS
Intersillnc.
10710 N. Tantau Avenue
Cupertino, California 95014
U.S.A.
Tel: (408) 996-5000

TWX: 910-338-0533 (lNTRSLINT ePTO)

NORTHERN & EUROPEAN
HEADQUARTERS

SOUTHERN EUROPEAN
HEADQUARTERS

CENTRAL EUROPEAN
HEADQUARTERS

FAR EAST HDQTRS_
(EXCEPT JAPAN)

Intersi! Datel (UK) Ltd.
9th Floor
Snamprogetti House
Basing View
Basingstoke, Hants, RG21 2YS
England

Intersillnc.

Intersil GmbH
8000 Munchen 2

Intersillnc.
cIa S.S.I. Far East Ltd.

Tel: 0256·57361
TLX: 858041 INTRSL G

Bureau de Liaison
217, Bureaux de la Colllne

:;~1g ~~n~~P~~d Cedex
France

l~:(H:~~C~:204280F

BavariarinQ 8
West Germany
Tel: 891539271
TLX: 5215736 INSL 0

Suite 201, Austin Centre
21 Austin Avenue
T81m 5ha Tsui, Kowloon

~~~t:~£1~2-3

TLX: 86496 S51 HX

INTERSIL FRANCHISED DISTRIBUTORS
ARIZONA

CALIFORNIA (continued)

GEORGIA

MARYLAND (continued)

Components Plus

7500 E. Buterus Dr.
Suite T
Scottsdale, AZ 85260
Tel: (602) 991·6510

Wyle Distribution Group
9525 Chesapeake Dr.
Sen Diego, CA 92123
Tel: (714) 565·9171
TWX: 910·335·1590

Arrow Electronics
2979 Pacific Dr.
Norcross, GA 30071
Tel: (404) 449·8252
TWX: 810·757·4213

Diplomat Electronics Inc.
9150 Rumsey Road
Suite #A6
Columbia, MD 21045
Tel: (301) 995-1226

Kierulff Electronics

COLORADO

$chweber Electronics
303 Research Drive

Bell Industries

Norcross, GA 30092
Tel: (404) 449·9170

9218 Gaither Rd.
Gaithersburg, MD 20780
Tel: (301) 840-5900
TWX: 710-828·9749

ILLINOIS

MASSACHUSETTS

Arrow Electronics

Arrow Electronics
960 Commerce Way
Woburn, MA 01801
Tel: (617) 933-8130

4134 E. Wood St.
Phoenix, AZ 85040
Tel: (602) 243-4101
Kierulff Electronics

1806 W. Grant Rd.
Suite #102
Tucson, AZ 85707
Tel: (602) 624·9986
TWX: 910·952·1119
Western Microtechnology Sales

Bullding'#105
7740 East Redfield Road
Scottsdale, AZ 85260
Tel: (602) 948·4240
Wyle Distribution Group
8155 N. 24th Ave.
Phoenix, AZ 85021
Tel: (602) 249·2232

Century Electronics Div.

8155 W. 48th Ave.
Wheat ridge, CO 80033
Tel: (303) 424·1985
TWX: 910·938-0393

Kierluff Electronics
10890 E. 47th Ave.
Denver, CO 80239
Tel: (303) 371·6500
Wyle Distribution Group

451 E. 124th Ave.
Thornton, CO 80241
Tel: (303) 457·9953
TWX: 910·936·0770

CONNECTICUT

492 Lunt Ave.
Schaumburg, IL 80193
Tel: (312) 893·9420
TWX: 910-291·3544
Kierulff Electronics
1530 Landmeier Rd.
Elk Grove Village, IL 60007
Tel: (312) 640-0200

Newark Electronics
500 North Pulaski Road
Chicago, IL 60007
Tel: (312) 638-4411

Arrow Electronics

CALIFORNIA
Anthem Electronics, Inc.

4125 Sorrento Valley Blvd.
Suite A

San Diego, CA 92121
Tel: (714) 279·5200
Anthem Electronics, Inc.
174 Component Orive.

San Jose, CA 95131
Tel: (408) 946·8000
TWX: 910·339·9312
Arrow Electronics

521 Weddell Drive
Sunnyvale, CA 94086
Tel: (408) 745·6600
TWX: 910·339·9371
Arrow Electronics

9511 Ridgehaven Ct.
San Diego, CA 92123
Tel: (714) 565·4800
Klerulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
Tel: (213) 725·0325
TWX: 910·580·3106

Kierulff Electronics
3969 East Bayshore Rd.
Palo Alto, CA 94303
Tel: (415) 968·6292
Kierulff Electronics

14101 Franklin Ave.
Tustin, CA 92680
Tel: (714) 731·5711

Schweber Electronics
17811 Gillette Ave.
I rvl ne, CA 92714
Tel: (714) 556·3880
TWX: 910·595·1720
Wyle Distribution Group
3000 Bowers Ave.
Santa Clara, CA 95052
Tel: (408) 727·2500
TWX: 910·338·0541
910·338·0296
Wyle Distribution Group
124 Maryland St.
EI Segundo, CA 90245
Tel: (213) 322·8100
TWX: 910·348·7111
Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714
Tel: (714) 641·1600

12 Beaumont Rd.
Wallingford, CT 06492
Tel: (203) 265·7741
TWX: 710·465·0780
Scnweber Electronics

Schweber Electronics
1275 Brummel Ave.
Elk Grove Village, IL 80007
Tel: (312) 364·3750
TWX: 910·222·3453

Danbury, CT 06810
Tel: (203) 792·3500
TWX: 710·456·9405

INDIANA

FLORIDA

Advent Electronics, Inc.
8446 Moller Rd.
Indlanopolis, IN 46268
Tel: (317) 297·4910
TWX: 810-341-3228

Arrow Electronics

1001 NW 62nd St.
Suite #402
Ft. Lauderdale, FL 33309
Tel: (305) 776·7790
TWX: 510·955·9456
Components Plus

2718 Rand Road
Indianopolis, IN 46241
Tel: (317) 243·9353

IOWA

Arrow Electronics

Advent ElectroniCS
682 58th Avenue Court S.W.
Gadar Rapids, IA 52404
Tel: (319) 383-0221
TWX: 910·525·1337

50 Woodlake Dr. West
Bldg. B
Palm Bay, FL 32905
Tel: (305) 725·1480
TWX: 510·959·6337

5720 N. Park Place N.E.
Cedar Rapids, IA 52402
Tel: (319) 373·1417

6990 Lake Ellenor Dr.
Orlando, FL 32809
Tel: (305) 851·7550

Diplomat Electronics Inc.

115 Palm Bay Road NW
Building 200·Suite 10
Palm Bay, FL 32905
Tel: (305) 725·1480
TWX: 510·959-6337
Diplomat Electronics Inc.
2120 Calumet St.
Clearwatrer, FL 33515
Tel: (813) 443·4514
TWX: 810-866·0438

Diplomat Electronics Inc.
6890 NW 20th Ave.
Ft. Lauderdale, FL 33309
Tel: (305) 971·7160
Diplomat Electronics Inc.
50 Woodlake Drive West
Suite #3 Building A
Palm Bay, FL 32905
Tel: (305) 725·4520

Schweber Electronics
2630 N. 28th Terrace
Hollywood, FL 33020
Tel: (305) 927·0511
TWX: 510·954·0304

Components Plus
14 Burr Ave.
Framingham, MA 01701
Tel: (617) 237·2503
Klerulff Electronics
13 Fortune Dr.
Billerica, MA 01821
Tel: (617) 667-8331
TWX: 710-390-1449
Schweber Electronics
25 Wiggins Ave.
Bedford, MA 01730
Tel: (617) 275-5100

MICHIGAN

Finance Drive
Commerce Industrial Park

Schweber Electronics

KANSAS

Arrow Electronics
3801 Varsity Dr.
Ann Arbor, MI 48104
Tel: (313) 971-8220
TWX: 810-223-6020
Schweber Electronics
33540 Schoolcraft
Livonia, MI 48150
Tel: (313) 525-8100

MINNESOTA
Arrow Electronics
5230 W. 73rd St.
Edina, MN 55435
Tel: (612) 830-1800
TWX: 910-576·3125
Kierulff Electronics
5280 West 7th St.
Edina, MN 55435
Tel: (612) 635·4388
Schweber Electronics
7422 Washington Avenue South
Eden Prairie, MN 55343
Tel: (612) 941·5260

Components Plus

8501 W. 63rd SI.
Merriam, KS 66202
Tel: (913) 236·8555
Component Specialties Inc.
8369 Nieman Road
Lenexa, KS 66214
Tel: (913) 492·3555

MARYLAND
Arrow Electronics
4801 Benson Ave.
Baltimore, MD 21227
Tel: (301) 247·5200
TWX: 710·236-9005
Components Plus

4805 Benson Ave.
Baltimore, MD 21227
Tel: (301) 247·3620

MISSOURI
Arrow Electronics
2380 Schuetz Rd.
SI. Louis, MO 63141
Tel: (314) 567·6888
LCOMP
2550 Harley Dr.
Maryland Heights, MO 63043
Tel: (314) 291·6200
TWX: 910·762·0632
LCOMP
2211 River Front Dr.
Kansas City, MO 64120
Tel: (816) 221·2400
TWX: 910·771·3148

NEW HAMPSHIRE

NEW YORK (continued)

PENNSYLVANIA

WISCONSIN

Arrow Electronics
One Perimeter Rd.
Manchester, NH 03103
Tel: (603) 868·6968

Harvey Electronics
P.O. Box 1208
Binghamton, NY 13002
Tel: (607) 748-8211
TWX: 510-252·089.1

Arrow Elsctronics
650 Seco Rd.
Monroeville, PA 15146
Tel: (412) 856·7000

Arrow Electronics
430 W. Rawson Ave.
Oak Creek, WI 53154
Tel: (414) 754·6600
TWX: 910·262·1193

NEW JERSEY

Harvey Electronics
840 Fairport Park
Fairport, NY 14450
Tel: (716)
TWX: 510-253-7001

Arrow Electronics
Pleasant Valley Ave.
Moorestown, NJ 08057
Tel: (609) 235-1000
TWX: 710-897·0829
Arrow Electronics
265 Midland Ave.
Saddle Brook, NJ 07662
Tel: (201) 797·5800
TWX: 710·988·2208
Diplomat Electronics Inc.
400 South Riverview Or.
Totowa, NJ 07512
Tel: (201) 785·1830
SChweher Electronics
18 Madison
Fairfield, NJ 07006
Tel: (201) 227·7990

NEW MEXICO
Alliance Electronics
11030 COchiti S.E.
Albuquerque, NM 87123
Tel: (505) 292·3360
Arrow Electronics
2460 Alamo Avenue, S.E.
Albuquerque, NM 87108
Tel: (505) 243·4566
Bell Industries
Century Electronics Div.
11728 Linn, NE
Albuq~erque, NM 87123
Tel: (50S) 292·2700
TWX: 910-989·0625

NEW YORK

Schweber ElectroniCS
Jericho Turnpike
Westbury, NY 11590
Tel: (516) 334-7474
TWX: 510-222·3660
Schweber Electronics
4 Townline Circle
Rochester, NY 14623
Tel: (716) 424·2222
Summit Distributors Inc.
916 Main St_
Buffalo, "Y 14202
Tel: (716) 884·3450
TWX: 710·522·1692

NORTH CAROLINA
Arrow Electronics
938 Burke SI.
Winston-Salem, NC 27102
Tel: (919) 725·8711
RESCO/Raleigh
RI. 8 Box 116·B
Highway 70 West
Raleigh, NC 27612
Tel: (919) 781·5700
TWX: 510·928·0590

OHIO
Arrow Electronics
7620 McEwen Road
Centerville, Ohio 45459
Tel: (513) 435-5563
TWX: 810-459-1611

Arrow electronics
900 Broad Hollow Rd.
Farmingdale, NY 11735
Tel: (516) 694·6800
TWX: 510·224·6494

Arrow Electronics
6238 Cochran
Solon, OH 44139
Tel: (216) 248-3900

Arrow Electronics
20 Oser Ave_
Hauppauge, NY 11787
Tel: (516) 231·1000

Schweber Electronics
23880 Commerce Park Rd.
Beachwood, OH 44122
Tel: (216) 464·2970
TWX: 810·427·9441

Arrow Electronics
7705 Maltlage Drive
Liverpool, NY 13066
Tel: (315) 652·1000

OKLAHOMA

Arrow Electronics
3000 South Winton Rd
Rochester, NY 14623
Tel: (716) 275·0300
Components PltJs
40 Oser Ave.
Hauppauge, NY 11787
Tel: (516) 231·9200
TWX: 510·227·9889

Component Specialties Inc.
7920 E 40th SI.
Tulsa, OK 74145
Tel: (918) 664·2820

OREGON
Kierulff Electronics
14273 N.W. Science Park Or.
Portland, OR 97229
Tel: (503) 641·9150
TWX: 910-467·8753
Parrott Electronics
8058 S.W. Nimbus Or.
Beaverton, OR 97005
Tel: (503) 641·3355
TWX: 910·467·8720

Schweber Electronics
101 Rock Rd.
Horsham, PA 10044
Tel: (215) 441·0600

T'=XAS
Arrow Electronics
13715 Gamma Rd.
Dallas, TX 75234
Tel: (214) 366-7500
Arrow Electronics
10700 Corporate Or.
Stallord, TX 77477
Tel: (713) 491·4100
Components Plus
13777 North Central Exp.
Dallas, TX 75243
Tel: (214) 783·6060
Component Specialties Inc.
8222 Jamestown Dr. Suile #115
Austin, TX 78757
Tel: (512) 837·8922
Component Specialties Inc.
10907 Shady Trail
Suite #101
Dallas, TX 75220
Tel: (214) 357·6511
Component Specialties Inc.
8181 Commerce Park Dr.
Suite #700
Houston, TX 77036
Tel. (713) 771·7237
Schweber Electronics
14177 Proton SI.
Dallas, TX 75234
Tel: (214) 661-5010
TWX: 910·860·5493
Schweber Electronics
10625 Richmond Ave.
Suite #106
Houston, TX 77042
Tel: (713) 784·3600
TWX: 910·881·1109

Kierulff Electronics
2212 E. Moreland Ave.
Waukesha, WI 63186
Tel: (414) 784-8160
Schweber Electronics
150 S. Sunnysfope Road
Suite 120
Brookfield. WI 53005
Tel: (414) 784-9020

CANADA
Cardinal Electronics
10630172 St.
Edmonton, Alberta
Canada T5J 2P4
Tel: (403) 483-6266
CESCO
4050 Jean Talon SI. W
Montreal, Quebec
Canada H4P 1Wl
Tel: (514) 735·5511
TWX: 610·421·3302
CESCO
24 Martin Ross Ave.
Downsview, Ontario
Canada M3J 2K9
Tel: (416) 661·0200
CESCO Elec. Ltd.
98 Rue Vallier O.
Quebec City. Quebec
Canada Gl K 6W8
Tel: (418) 524-4641
RAE. Ind. Elecl. Ltd.
3455 Gardner CI.
Burnaby, British Columbia
Canada V5C 4J1
Tel: (604) 291·8866
TWX: 610·929·3065
TLX: 04·356533
RAE. Ind. Elec. Ltd.
11680 HOth SI.
Edmonton. Alberta
Canada T5S 1J7
Tel: (403) 451-4001

UTAH
Bell Industries
Century ELectronics Div.
3639 West 2150 South
Salt Lake City, UT 84120
Tel: (801) 972·6969
TWX: 910·925-5698

Diplomat ELectronics
3007 S. West Temple, Suite #C
Salt Lake City, UT 84115
Tel: (801) 486·4134
Kierulff Electronics
2121 S. 3600 West
Salt Lake City, UT 84119
Tel: (801) 973·6913

WASHINGTON
Kierulff ElectroniCS
1005 Andover Park East
Tukwila. WA 98188
Tel: (206) 575·4420
Wyle Distribution Group
1750 132nd Ave., NE
Bellevue, WA 98005
Tel: (206) 453·8300
TWX: 910·443·2526

Zentronics Ltd.
1355 Meyerside Or.
Mississauga, Ontario
Canada L5T 1C9
Tel: (416) 676·9000
TLX: 06·983657
Zentronics Ltd.
480A Dutton Or.
Waterloo, Ontario
Canada N2L 4C6
Tel: (519) 884·5700
Zentronics Ltd.
5010 Pare SI.
Montreal, Quebec
Canada H4P 1P3
Tel: (514) 735·5361
TLX: 05·827535
Zentronics Ltd.
141 Catherine SI.
Ottawa, Ontario
Canada K2P 1C3
Tel: (613) 238·6411
TLX: 053-3636
Zentronics Ltd.
590 Berry Street
Winnipeg, Manitoba
Canada R3H OSI
Tel: (204) 775·8661

DOMESTIC SALES REPRESENTATIVES
ALABAMA

IOWA

NEW MEXICO

TENNESSEE

K & E Associates, Inc.
Suite #122
3313 Memorial Parkway SE
Huntsville, AL 35801
Tel: (205) 883-9720
TLX: 50-4421

Dy-Tronix, Inc.
Suite #201
23 Twixt Town Rd. NE
Cedar Rapids, IA 52402
Tel: (319) 377-8275

Shefler-Kahn
10200 Menaul NE
Albuquerque, NM 87112
Tel: (505) 296-0749

K &. E Associates
Route 1
Box 33A
Jonesboro, TN 37659
Tel: (615) 753-2921

NEW YORK
LOUISIANA

ARIZONA
Shetler-Kahn
2017 N. 7th SI.
Phoenix, AZ 85006
Tel: (602) 257-9015
TWX: 910-951-0659

CALIFORNIA
ADDEM S.D.
7380 Clairemont Mesa Blvd.
Suite 106
San Diego, CA 92111
Tel: (714) 268-8448

Nova Marketing, Inc.
651 Laurel Street
Baton Rouge LA 70802
Tel: (504) 383-3197

MARYLAND
New Era Sales, Inc.
Empire Towers-Suite #407
7310 Ritchie Highway
Glen Burnie, MD 21061
Tel: (301) 768-6666
TWX: 710-861-0520

MASSACHUSETTS
CONNECTICUT
COM·SALE
633 Williams Road
Wallingford, CT 06492
Tel: (203) 269-7964

COM-SALE
235 Bear Hill Road
Waltham, MA 02154
Tel: (617) 890-0011

MICHIGAN
FLORIDA
EIR, Inc.
701 E. Semoran Blvd.
Suite 112
Altamonte Springs, FL 32701
Tel: (305) 830-9600
TWX: 810-853-9213

Giesting & Associates
5654 Wendzel Dr.
Coloma, MI 49038
Tel: (616) 468-4200
Giesting & Associates
149 Mary Alexander CI.
Northville, MI 48167
Tel: (313) 348-3811

ILLINOIS
D. Dolin Sales CO.
6232 N. Pulaski Rd.
Chicago, IL 60646
Tel: (312) 286-6200
TWX: 910·221-5018

GEORGIA
K & E Associates
6682-F Peachtree
Industrial Blvd.
Doraville, GA 30360
Tel: (404) 488-7025

INDIANA
Delesa Sales
Executive Office Park
2118 Inwood Dr., Suite #117
FI. Wayne, IN 46805
Tel: (219) 483-9537
TWX: 810-332-1407
Delesa Sales
10026 E. 21 st SI.
Indianapolis, IN 46229
Tel: (317) 894-3778

MISSOURI
Dy-Tronix, Inc.
11190 Natural Bridge
Bridgeton, MO 63044
Tel: (314) 731-5799
TWX: 910-762-0651
Dy-Tronix, Inc.
13700 East 42nd Terrace
Independence, MO 64055
Tel: (816) 373-6600

Ossman Component Sales Corp.
280 Metro Park
Rochester, NY 14623
Tel: (716) 424-4480
TWX: 510-253-7685
Ossman Component Sales Corp.
154 Pickerard Bldg.
Syracuse, NY 13211
Tel: (315) 455-8611
TWX: 710-541-1522

NORTH CAROLINA
K & E Associates
Route 2 Box 54
Garner; NC 27529
Tel: (919) 772-8454

OHIO
Giesting & Associates
3274 Donneybrook Lane
Cincinnati, OH 45239
Tel: (513) 521-8800
TLX: 21-4283
Giesting & Associates
5512 Autumn Hills Dr.
Westbrook Village
Dayton, OH 45426
Tel: (513) 293-4044
Giesting & Associates
570 South State Circle
Galion, OH 44833
Tel: (419) 468·3737

OREGON
LD Electronics
P.O. Box 626
Beaverton; OR 97005
Tel: (503) 649-8556
(503) 649-6177
TWX: 910-467-8713

PENNSYLVANIA
NEW HAMPSHIRE
COM-SALE
102 Maple SI.
Manchester, NH 03103
Tel: (603) 668-1440

Comtek Inc.
821 Bethlehem Pike
Erdenheim, PA 19118
Tel: (215) 233-0532

SOUTH CAROLINA
K & E Associates
4808 SI. Andrews Office Park
Suite 10
Columbia, SC 29210
Tel: (803) 798·7574

TEXAS
Nova Marketing
11700 Southwest Freeway
Suite #200
Houston, TX 77031
Tel: (713) 933-2626
TWX: 910-880-4053
Nova Marketing
5728 LBJ Freeway
Suite #400
Dallas, TX 75240
Tel: (214) 385-9669

UTAH
Sage Sales
3524 South 1100 East
Salt Lake City, UT 84106
Tel: (801) 485-5111
TWX: 910-925-5153

WASHINGTON
LD Electronics
East 12607 Guthrie Dr.
Spokane, WA 99216
Tel: (509) 455-0189
LD Electronics
14506 NE 169th SI.
P.O. Box 663
Woodenville, WA 96072
Tel: (206) 485-7312

WISCONSIN
D. Dolin Sales Co.
131 W. Layton Ave.
Milwaukee, WI 53207
Tel: (414) 482-1111
TWX: 910-262-1139

CANADA
Lenbrook Industries Ltd.
1145 Bellamy Rd.
Scarborough, Ontario
Canada Ml H 1H5
Tel: (416) 438-4610
TLX: 065-25485
Lenbrook Industries Ltd.
6896 Jarry SI. East
St. Leonard, Quebec
Canada HlP 3Cl
Tel: (514) 323-3242

111111_DI~llmll~111111111
As a natural extension of our communications program, we
have created handsome color poster renditions of each of
the historical figures and quotations used in our campaign.
Each poster is approximately 18" x 24", and is eminently
suitable for framing.

To order your favorite, simply write us on your company letterhead and request the poster or posters which strike your
fancy. There is no charge. This is our "thank you" for thinking of Intersil when you think of leading-edge technology.
INTERSIL
Marketing Services MS-38
10710 N Tantau Avenue
Cupertino, CA 95014

D~DIb

CORPORATE HEADQUARTERS'
10710 N. Tanlau Avenue
Cupertino, CA 95014
Tel: (408) 996-5000
TWX: 910-338-0171

Printed In U.S.A.

NORTHERN AND EUROPEAN
HEADQUARTERS
9th Floor
Snamprogetti House
Basing View
Basingstoke RG21 2YS
Hants, England
Tel: (0256) 57361
TLX: 8580411NTRSL G

SOUTHERN EUROPEAN
HEAOQUARTERS
Bureau de Liaison
217, Bureaux de la Colline,
BAT. D (2 e Etage)
92213 Saint-Cloud Cedex
France
Tel: (1) 602.58.98
TLX: DATELEM 204280F

CENTRAL EUROPEAN
HEADQUARTERS
Bavariaring 8
Concordiahaus
8000 MUnchen 2
West Germany
Tel: 89/539271
TLX: 5215736 INSLD

FAR EAST HEADQUARTERS
(EXCEPT JAPAN)
cIa S.S.I. Far East LId.
Suite 201, Austin Centre
21 Austin Avenue
Tsim Sha Tsui Kowloon
Hong Kong
Tel: 3-672112-3
TLX: 86496 SSI HX

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1981_Intersil_Power_MOS 1981 Intersil Power MOS

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