1981_MMI_PAL_Handbook_2ed 1981 MMI PAL Handbook 2ed
User Manual: 1981_MMI_PAL_Handbook_2ed
Open the PDF directly: View PDF 
.
Page Count: 680
| Download | |
| Open PDF In Browser | View PDF |
' 51
HAl
HMSI
""'l
PROGRAMMABLE ARRAY lOGIC
$12.00
~S I
HAL
H MSI
PAL
PROG RA MM A BLE A RR AY LOG IC
PAL
~SI
HAL
HMSI
PAL
PROGRAMMAB LE ARRAY LOGIC
PAL
1S1
HAL
HMSI
PAL
PROGRAMMABLE ARRAY LOGIC
PAL
. 51
'51
HAL
HAL
HM51
HM51
PAL
PAL
PROGRAMMABLE ARRAY LOGIC
PROGRAMMABLE ARRAY LOGIC
PAL
PAL
PROGRAMMABLE ARRAY LOGIC
PAL
lSI
HAL
lSI
151
HAL
•
HMSI
HMSI
PAL
PAL
PROGRAMMABLE ARRAY LOGIC
PAL
HAL • HMSI • PAL • PROGRAMMABLE ARRAY LOGIC • PAL
20-Pin PAL Logic Symbols
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16C1
PAL10L8
PAL12L6
PAL14L4
PAL16L2
PAL16L8
PAL16R4
PAL16X4
PAL16A4
PAL16R8
PAL16R6
PAL®
PROGRAMMABLE ARRAY LOGIC
HANDBOOK
SECOND EDITION
PAL Introduction
II
Authors: John Birkner & Vincent Coli
Video Controller by Ehud Gordon
Monolithic I!t!n
Memories LnJn.U
© CopyriIJht 1981 Moriolittiic Memories, Inc.
•
1165 Arques Avenue
•
Sunnyvale, CA 9~086-9960
•
408-739-'3535
•
910-339-9220
PAL Introduction
Acknowledgements
The following employees of Monolithic Memories made contributions to this 2nd edition of the PAL APPLICATION
HANDBOOK. Specific technical contributions are sJted. on line
two of the PAL DESIGN SPECIFICATION.
Product Planning and Applications
Department
Ehud Gordon, Applications Engineer
Saeed Kazmi, PAL Product Marketing Engineer
Nadia Sachs, Senior Applications Engineer
Shlomo Waser, Manager, Product Planning and Applications
Sales
Bernard Brafman, District Sales Manager (Northern California)
Harry Hughes, Field Applications Engineer (Northern Europe)
Dick Jones, District Sales Manager (Illinois)
Vincent Leclerc, Field Applications Engineer (Southern Europe)
Brad Mitchell, Field Applications Engineer (South East)
WillyVoldan, Field Applications Engineer (Central Europe)
Mike Volpigno, Field Applications Engineer (East Coast)
To
th~seindividuals we
extend our gratitude,
The Authors
John Birkner, Monolithic Memories Fellow
Vincent Coli, Applications Engineer
. ....
PAL Introduction
Table of Contents
PAL INTRODUCTION ...............................
1-2
PAL FAMILY
Family Portrait ......................... " ................
Logic Diagrams
. ..........
PAL 1OH8 . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL 12H6 ..............................................
PAL14H4 ..............................................
PAL 16H2 ..............................................
PAL 16C1 , .............................................
PAL20C1 ..............................................
PAL 10L8 ..............................................
PAL 12L6 ..............................................
PAL 14L4 ..............................................
PAL 16L2 ..............................................
PAL12L10 .............................................
PAL 14L8 ..............................................
PAL 16L6 ..............................................
PAL18L4 ..............................................
PAL20L2 •. . .
. ............................•......
PAL 16L8 ..............................................
PAL20L 10 ............ , ................................
PAL 16R8 ..............................................
PAL 16R6 ...................... , .......................
PAL 16R4 ..............................................
PAL20X10 .............................................
PAL20X8 ..............................................
PAL20X4 ...................................' ...........
PAL 16X4 .............. " ..............................
PAL16A4 ...................................... , .......
2-2
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-1.5
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
4-Bit Counter with 2 Input Mux ..........................
Octal Counter ...........................................
Octal Up/Down Counter .................................
10-Bit Counter ..........................................
4-Bit Up/Down Counter with Shift Register and Comparator.
4-Bit Flash Gray A/D Converter ..........................
4-Bit Gray 0/A Converter ................ : ...............
8-Bit 0/ A Converter .....................................
Octal Comparator .......................................
Between Limits Comparator ..............................
Memory Mapped Printer .................................
Craps Game ............................................
Traffic Signal Controiler .................................
32-Bit CRC (Cyclical Redundancy Checking) Error Detection.
8-Bit Error Detection and Correction .....................
4-169
4-177
4-185
4-193
4-201
4-209
4-217
4-225
4-233
4-239
4-251
4-261
4-285
4-301
4-329
VIDEO CONTROLLER
Introduction to Video Section ............... , .............
Implementing a Video Controiler Using
Programmable Array Logic .............................
Video Controiler Schematic ...............................
Video Controiler PC Board Artwork ............ , ..........
Dot Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CHAR/CURS Generator ...................................
SCAN/LINE Generator ....................................
LlNES/SCROL Generator .................................
Composite Video/Baud Rate Generator ...................
UART Shift Register and Control Key Detect. .............
UART Control ............................................
RAM Control .............................................
5-2
5-3
5-12
5-14
5-17
5-25
5-33
5-43
5-51
5-59
5-67
5-77
PAL DESIGN CONCEPTS
PAL Concepts ............................................
PALASM Flow Chart (Main Program) ......................
PALASM Flow Chart (Simulator) ..........................
PALASM 20 Source Code ................................ ·.
PALASM 24 Source Code ................................
Basic PALASM Source Code .............................
3-2
3-7
3-8
3-10
3-34
3-58
PAL APPLICATIONS
Basic Gates .............................................. 4-3
Basic Clocked Flip-Flops ................................. 4-9
Memory Mapped I/O .........•........................... 4-17
Memory Interlace Logic for 6800 Microprocessor Bus ..... 4-23
Video Logic .............................................. 4-31
Binary to BCD Converter ................................. 4-37
Deglitcher ............ , .. , ............................... 4-47
Electronic Dice Game .................................... 4-53
9-Bit Register ............................................ 4-63
Multifunction Octal Register .............................. 4-69
8-Bit I/O Priority Interrupt Encoder with Registers ........ 4-77
BC D/Hex Cou nter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-83
64k Dynamic RAM Refresh Controiler .................... 4-91
State Counter for Multiplier/Divider.. .. . .. . . .. . . . .. . . ... 4-99
ALU/ Accumulator ....................................... 4-107
Stepper Motor Controiler ................................ 4-113
Shaft Encoder ........................................... 4-123
Quad 4:1 Mux ........................................... 4-129
Dual 8:1 Mux •........................................... 4-137
16:1 Mux ..................•............................. 4-145
. ............ 4-153
Octal Shift Register.....................
4-Bit Shift Register/Comparator .......................... 4-161
ARTICLE REPRINTS
Single-Chip Controiler Increases Microprocessor Throughput6-2
FPLA Arbiter Concept Adapts to Application Needs ....... 6-9
Programmable Array Logic Leads to
Flexible Application of 8-Bit Wide Memories ............. 6-16
PAL: Quick Turnaround Alternative to Gate Arrays ........ 6-18
High Speed/Low Case Fuse Link Arrays
Compete with TTL 74S/LS .............................. 6-27
PALs: Programmable Logic Functions
Help Minimize Hardware ........................... 6-32
Gate Arrays Logjam Test Engineering ..................... 6-38
High Level Language for Programmable Array Logic ...... 6-40
PAL/HAUHMSI. SPECIFICATIONS
PAL Series 20 ................................ " ..........
PAL Series 24 ............................................
HAL Series 20 ............. : ..............................
HAL Series 24. , ......................................... ,
Octal Counter SN54/74LS461 .............................
Octal Shift Register SN54/74LS498 ........................
Multifunction Octal Register SN54/74LS380 ...............
10-Bit Counter SN54174LS491 ............................
16:1 Mux SN54174LS450 ..................................
Dual 8:1 Mux SN54/74LS451 ..............................
Quad 4:1 Mux SN54/74LS453 ............................ ,
HMSI Appendix ................•.........................
7-2
7-10
7-18
7-42
7-60
7-62
7-64
7-66
7-68
7-70
7-72
7-74
REPRESENTATiVES/DiSTRIBUTORS .............
8-1
D
PAL Introduction
The PALTM Concept
Monolithic Memories' family of PAL devices gives designers a powerful tool with unique capabilities for use in
new and existing logic deSigns. The PAL saves time and
money by solving many of the system partitioning and
interface problems brought about by increases in
semiconductor device technology.
Rapid advances in large scale integration technology
have led to larger and larger standard logic functions;
single I.C.s now perform functions that formerly required
complete circuit cards. While LSI offers many advantages, advances have been made· at the expense of
deVice flexibility. Most LSI devices still require large
numbers of SSI/MSI devices for interfacing with user
systems. Designers are still forced to turn to random
logic for many applications.
The designer is confronted with another problem when a
low to medium complexity product is designed. Often the
function is well defined and could derive significant benefits from fabrication as an integrated circuit. However,
the design cycle for a custom circuit is long and the costs
can be very high. This makes the risk significant enough
to deter most users. The technology to support maximum
flexibility combined with fast turn around on custom logic
has simply not been available. Monolithic Memories
offers the programmable solution.
The PAL family offers a fresh approach to using fuse
programmable logic. PALs are a conceptually unified
group of devices which combine programmable flexibility with high speed and an extensive selection of interface options. PALs can lower. inventory, cut design
cycles and provide high complexity with maximum
flexibility. These features, combined with lower package count and high reliability, truly make the PAL a
circuit designer's best friend.
PAL'· is a trademark of Monolithic Memories.
PAL Introduction
The PAL-Teaching Old PROMs
New Tricks
array. Since the sum of products form can express any Boolean
transfer function, the PAL's uses are only limited by the number
of terms available in the AND - OR arrays. PALs come in different sizes to allow for effective logic optimization.
Figure 1 shows the basic PAL structure for a two input, one output
logic segment. The general logic equation for this segment is
Output
\
=
(ll+fl)(ll +f2)(l2+ f3)(1 2+f4) +
(1 1+15)(11+16)(12+17) (l2+ f 8)
where the "f" terms represent the state of the fusible links in the
PAL's AND array. An unblown link represents a logic 1. Thus,
fuse blown, f = 0
fuse intact, f = 1
An unprogrammed PAL has all fuses intact.
D
OUTPUT
MMI developed the modern PROM and introduced many of the
architectures and techniques now regarded as industry
standards. As the world's largest PROM manufacturer, MMI has
the proven technology and high volume production capability
required to manufacture and support the PAL.
The PAL is an extension of the fusible link technology pioneered
by Monolithic Memories for use in bi-polar PROMs. The fusible
link PROM first gave the digital systems designer the power to
"write on silicon." In a few seconds he was able to transform a
blank PROM from a general purpose device into one containing
a custom algorithm, microprogram, or Boolean transfer function.
This opened up new horizons for the use of PROMs in computer
control stores, character generators, data storage tables and
many other applications. The wide acceptance of this
technology is clearly demonstrated by today's multi-million
dollar PROM market.
'I
.!
The key to the PROM's success is that it allows the designer to
quickly and easily customize the chip to fit his unique
requirements. The PAL extends this programmable flexibility by
utilizing proven fusible link technology to implement logic
functions. Using PALs the designer can quickly and effectively
implement custom logic varying in complexity from random
gates to complex arithmetic functions.
ANDs and ORs
The PAL Implements the familiar sum of products logic by using
a programmable AND array whose output terms feed a fixed OR
Figure 1
PAL Notation
Logic equations, while convenient for small functions, rapidly
become cumbersome in large systems. To reduce possible
confusion, complex logic networks are generally defined by logic
diagrams and truth tables. Figure 2 shows the logic convention
adopted to keep PAL logic easy to understand and use. In the
figure, an "x" represents an intact fuse used to perform the logic
AND function. (Note: the input terms on the common line with
the x's are not connected together.) The logic symbology shown
in Figure 2 has been informally adopted by integrated circuit
manufacturers because it clearly establishes a one-to-one
correspondence between the chip layout and the logic diagram.
It also allows the logic diagram and truth table to be combined
into a compact and easy to read form, thereby serving as a
convenient shorthand for PALs. The two input- one output example from Figure 1 redrawn using the new logic convention is
shown in Figure 3.
1·5
PAL Introduction
--Hf-o-
used to store computer programs and data. In these applications the fixed input is a computer memory address; the
output is the contents of that memory location.
ABC
)--A.B.C
A •B . C
PROM
Figure 2
16 Words X4 Bits
"OR" ARRAY
(PROGRAMMABLE)
~
~
~
7
~
7
V V IV V
r--'\
F<
F<
OUTPUT
b='
Figure 3
As a simple PAL example, consider the implementation of the
transfer function:
F'\
~
The normal combinatorial logic diagram for this function is
shown in figure 4, with the PAL logic equivalent shown in figure 5.
f=<
!:='
Figure 4
" AND " ARRAY
(FIXED)
Figure 6
Figure 5
Using this logic convention it is now possible to compare the
PAL structure to the structure of the more familiar PROM and
PLA. The basic logic structure of a PROM consists of a fixed
AND array whose outputs feed a programmable OR array
(figure 6). PROMs are low-cost. easy to program, and available
in a variety of sizes and organizations. They are most commonly
The basic logic structure of the PLA consists of a programmable
AND array whose outputs feed a programmable OR array
(Figure 7). Since the designer has complete control over all inputs and outputs, the PLA provides the ultimate flexibility for implementing logic functions. They are used in a wide variety of
applications. However, this generality makes PLAs expensive,
. quite formidable to understand, and costly to program (they
require special programmers).
The basic logic structure of the PAL, as mentioned earlier,
consists ola programmable AND array whose outputs feed a
fixed OR array (Figure 8). The PAL combines much of the
flexibility of the PLA with the low cost and easy programmabiiity
of the PROM. Table 1 summarizes the characteristics of the
PROM, PLA, and PAL logic families.
PAL Introduction
PAL
4 In.4 Out.16 Products
FPLA
4 In.4 Out.16 Products
"OR" ARRAY
(FIXED)
"OR" ARRAY
(PR OGR A MM A BlE)
~
7
~
7
~
IV IV IV
~
--
7
~
~
~
~
~
V
~
--
7
IV !vA
r---.
k
b<
=<
b<
~
P<
F=<
P=<
F=<
P=<
P<
~.
P<
P<
P<
P<
P<
~
1......./
..
AND" ARRAY
(PROGRAMMABLE)
AND " ARRAY
(PROGRAMMABLE)
Figure 8
Figure 7
AND
I
i
PROM
FPLA
FPGA
FPLS
PAL
Fixed
Prog
Prog
Prog
Prog
OR
OUTPUT OPTIONS
Prog
Prog
None
Prog
Fixed
TS,OC
TS, OC, Fusible Polarity
TS, OC, Fusible Polarity
TS, Registered Feedback, I/O
TS, Registered Feedback, I/O
Table 1
!I
:1
D
\;", PAL Introduction
PAL Input/Output/Function Chart
TpD
PROGRAMMABLE FEEDBACK OUTPUT
PART
INPUT OUTPUT
NUMBER
I/O'S
REGISTER POLARITY
FUNCTIONS
10L
ICC
ns, mA mA,
TYP
TYP
PAL10H8
10
8
AND-OR AND-OR Gate Array
25
8
55
PAL12H6
12
6
AND-OR AND-OR Gate Array
25
8
55
PAL14H4
14
4
AND-OR AND-OR Gate Array
25
8
5.5
PAL16H2
16
2
25
8
55
PAL16C1
16
2
25
8
55
PAL20C1
20
2
AND-OR AND-OR Gate Array
BOTH 1 AND-OR Gate Array
BOTH 1 AND-OR Gate Array
25
8
60
PAL10L8
10
8
AND-NOR AND-OR Invert Gate Array
25
8
55
PAL12L6
12
6
AND-NOR AND-OR Invert Gate Array
25
8
55
PAL14L4
14
4
AND-NOR AND-OR Invert Gate Array
25
8
55
PAL16L2
16
2
AND-NOR AND-OR Invert Gate Array
25
8
55
PAL12L10
12
10
AND-NOR AND-OR Invert Gate Array
25
8
60
PAL14L8
14
8
AND-NOR AND-OR Invert Gate Array
25
8
60
PAL 16L6
16
6
AND-NOR AND-OR Invert Gate Array
25
8
60
PAL18L4
18
4
AND-NOR AND-OR Invert Gate Array
25
8
60
PAL20L2
PAL 16L8
20
2
AND-NOR AND-OR Invert Gate Array
25
8
60
10
2
6
AND-NOR AND-OR Invert Gate Array
25
24
120
PAL20L10
12
2
8
PAL 16R8
8
8
PAL16R6
8
6
PAL16R4
8
4
PAL20X10
10
10
PAL20X8
10
8
PAL20X4
10
PAL16X4
8
PAL16A4
8
AND-NOR AND-OR Invert Gate Array
35
24
90
8
AND-NOR AND-OR Invert Array w/Reg's
25
24
120
2
6
AND-NOR AND-OR Invert Array w/Reg's
25
24
120
4
4
AND-NOR AND-OR Invert Array w/Reg's
25
24
120
10
AND-NOR AND-OR-XOR Invert w/Reg's
35
24
120
2
8
AND-NOR AND-OR-XOR Invert w/Reg's
35
24
120
4
6
4
AND-NOR AND-OR-XOR Invert w/Reg's
35
24
120
4
4
4
AND-NOR AND-OR-XOR Invert w/Reg's
25
24
160
4
4
4
AND-NOR AND-CARRY-OR-XOR Invert w/Reg's
25
24
170
1 Simultaneous AND-OR and AND-NOR outputs
Table 2
PALs For Every Task
spectrum of logic functions at reduced cost and lower package
count. This allows the designer to select the PAL that best fits
his application. PALs come in the following basic configurations:
The members of the PAL family and their characteristics
are summarized in Table 2. They are designed to cover the
Gate Arrays
output configurations available (figure 9). This wide variety of
input/output formats allows the PAL to replace many different
sized blocks of combinatorial logic with single packages.
PAL gate arrays are available in sizes from 12x10 (12 inputterms,
10 output terms) to 20x2, with both active high and active low
INPUTS AND OUTPUTS
...
")0
po
I I I
I
I I
I
I
,,
Figure 9
,
I
I
I
,
'"
,/'
PAL Introduction
Programmable I/O
A feature of the high-end members of the PAL family is
programmable input/output. This allows the product terms to
directly control the outputs of the PAL (Figure 10). One product
term is used to enable the three-state buffer, which in turn gates
the summation term to the output pin. The output is also fed
back into the PAL array as an input. Thus the PAL drives the I/O
pin when the three-state gate is enabled; the I/O pin is an input
to the PAL array when the three-state gate is disabled. This
feature can be used to allocate available pins for I/O functions or
to provide bi-directional output pins for operations such as
shifting and rotating serial data.
INPUTS, FEEDBACK AND I/O
.
..
>--
b-d
I/O
.... t----
~
....
Figure 10
II
Registered Outputs with Feedback
Another feature of the high end memberS of the PAL family is
registered data outputs with registered feedback. Each product
term is stored into a Ootype output flip-flop on the rising edge of
the system clock (Figure 11). The Q output of the flip-flop can
then be gated to the output pin by enabling the active low threestate buffer.
.
,
In addition to being available for transmission, the Q output is
fed back into the PAL array as an input term. Thisfeed!>'acl(
allows the PAL to "remember" the, previoOs state, and it can'
aiter its function based upon that state. This allows the deSigner
to configure the PAL as a state sequencer which can be
programmed to execute such elementary functions as count up,
count down, skip, shift, and branch. These functions can be
executed by the, registered PAL at tates of up to 20 MHz.
,
INPUTS, Fi!:EDBACKANO, I/O
CLOCK
r--
"\
...
DC
D lilt-----
.....
~
rt.!~ .
'"
Figure 11
XOAPALs
These PALs feature an',exclusive OR function. The sum of
products is segmented into two sums which are then exclusive
ORed (XOR) at the input of the Ootype flip-flop (Figure 12). All
of the features of the Registered PAls are included in the XOR
PALs. The XOR 'function proVides an easy implementation of
the HOLD operation uSed in counters and other state sequencers.
INPUTS, FEEDBACK AND I/O
,~I1IIIIIIIII1IIIIIIIII!lmlllllllll ~.
Figure 12
PAL Introduction
Arithmetic Gated Feedback
The arithmetic functions (add, subtract, greater than, and. less
than) are implemented by addition of gated feedback to the
features of the XOR PALs. The XOR llt the input of the D-type
flip-flop allows carrys from previous operations to be XORed
with two variable sums generated by the PAL array. The flip-flop
Q output isfed back to be gated with input terms A (Figure 13).
This gated feedback provides anyone of the 16 possible Boolean
combinations which are mapped in the Karnaugh map (Figure
15). Figure 14 shows how the PAL array can be programmed to
perform these 16 operations. These features provide for versatile
operations on two variables and facilitate the P!lrallel generation
of carrys necessary for fast .arithmetic operations.
INPUTS, FEEDBACK AND 1/0
0C
CLOCK
=
B
~
I
)D -:!~ ~
Dar--
~
Figure 13
A,--~~----~--~~----.
B--~~--~~----~--~
}----,-- 1+ Ii
}------A
} - - - - - ' - A+ B
q-
t:, x~
x~
'q
't:,x
x~
~
}------'-B
-x
xx
x-
I+B
A
A+B
}------A·B
}------A:+:B
}------A+B
-x
A+B
A:+:B
A'B
B
xx
A
A'B
0
A'B
x-
A+B
B
A'B
A:·:B
}------A
}----A.B
}----o
}------A.B
}-----,--A:.: B
)------A·ii
}----lJ
}-----,.,..,--...,.. A+ lJ
A+B
(IB)
A+B
(AB)
I+s'
(AB)
I+B
(AB)
Figure 14
Figure 15
PAL Introduction
It should now be clear that the PAL family can replace most
Small-Scale Integrated Logic (SSI) logic in use today, thereby
lowering product cost and giving the designer even greater
flexibility in implementing logic functions.
PAL Programming
PALs can be programmed in most standard PROM programmers with the' addition of a PAL personality card. The PAL
appears to the programmer as a PROM. During programming
half of the PAL outputs are selected for programming while
the other outputs and the inputs are used for addressing. The
outputs are then switched to program the other locations.
Verification uses the same procedure with the programming
lines held in a low state.
PALASM (PAL Assembler)
PALASM is the software used to define, simulate, build, and test
PALs, PALASM accepts the PAL Design Specification as an
input file. It verifies the design against an optional function table
and generates the fuse plot which is used to program the PALs.
PAlASM is available upon request in many source code media
and isdoctlmented in the PAL Design Concepts section.
HMSI (HAL Medium Scale Integration)
The HMSI family is derived from the PAL using HAUechnology.
These devices perform predetermined functions which are not
available in the existing TTL family, Because they are produced
in volume, the user receives the benefit of volume pricing. HMSI
PAL designs are given in the Applications section with their
745 number in line 2 of the PAL Design Specification,
PAL Technology
PALs are manufactured using the proven TTL Schottky bipolar
Ti-W fuse process to make fusible-link PROMs, An NPN
emitter follower array forms the programmable AND array. PNP
inputs provide high-impedance inputs (0,25 mA max) to the array, All outputs are standard TTL drivers with internal active
pull-up transistors, Typical PAL propagation delay time is 25 ns,
and all PALs are packaged in space saving 20-pin and 24-pin
SKINNYDIP'",
HALs (Hard Array Logic)
The HAL family is the mask programmed version of a PAL. The
,HALis to a PAL just as a ROM is to a PROM. A standard wafer is
fabricated to the 6th mask, Then a custom metal mask is used to
fabricate Aluminum links for a HAL instead of the progral]1mable
Ti-W fuse array used in a PAL.
The HAL is a cost-effective solution for large quantities and is
unique in that it is a gate array with a programmable prototype.
PAL Data Security
The circuitry useo for programming
and logic verification can
be used at anytime to determine the logic pattern stored in the
PAL array, For security, the PAL has a "last fuse" which can
be blown to disable the verificatiOn logic, This provides a significant deterrent to potential copiers, and it can be used to
effectively protect proprietary designs,
D'
PAL Introduction
vee
+5V
RoLL
...&..0-<
IrD
~W
-LJ
~~rr
J
-
~
~W
J
.'
>--
-----
Q3
~
.011'.1 2N4402
~h
::
2K
20K
20K
2K
":"
12011
Y4-
£
M
I
29011
,..
1'4
IA
M
12011
1'1
IA
r;;w
-
.011'1
Q2
~W
~
~~
X
12011
~
1'4
Q4
L.....-
J
,4.:..J
~J
o
.~
Q5
~
1
r-U
r;;w
~
~
p
1
pOs t - -
r..-
--Q6
120n
r;;-;W
~
Or
L.....-
~
'--
1
pQa
L..-
Figure 16
120n
1'4
29011
-.l
1
r
r;Oa~
.~
M
~
r*
M
1'4
12011
PAL Introduction
PAL Part Numbers
The PAL part number is unique in that the part number code
also defines the part's logic operation. The PAL parts code
system is shown in Figure 17. For example, a PAL 14L4CN
would be a 14 input term, 4 output term, active-low PAL with a
commercial temperature range packaged in a 20-pin plastic dip.
, - - - - - - - - - - - HARD ARRAY LOGIC FAMILY
, - - - - - - - - - NUMBER OF ARRAY INPUTS
; - - - - - - - - OUTPUT TYPE
L = ACTIVE LOW
H = ACTIVE HIGH
R = REGISTERED
C = COMPLEMENTARY
X = EXCLUSIVE-OR REGISTERED
A = ARITHMETIC REGISTERED
. . . - - - - - - - NUMBER OF OUTPUTS
TEMPERATURE RANGE
C= OCTO+75C
M = -55C TO +125C
(CASE TEMPERATURE)
r-------
.P. .'.
; - - - - - - PACKAGE
N = PLASTIC DIP
J = CERAMIC DIP
F= FLAT PACK
883B = MIL-STD-8S3,
O.PT.IONAL
HI-REL PROCE. SSING
METHOD 5004 & 5005 LEVEL B
S83C= MIL-STD-S83,
METHOD 5004 & 5005 LEVEL C
B = MIL-STD-883,
METHOD 5004 EQUIVALENT
PAL
14 L4
CJ 8838
C
~~~~~~~:~ EQUIVALENT
high-volume consumer product: an electronic dice game. This
type of product will be produced in extremely high volume, so it
is essential that every possible production cost be minimized.
The electronic dice game is simply constructed using a free
running oscillator whose output is used to drive two asynchronous modulo six counters. When the user "rolls" the dice
(presses a button), the current state of the counters is decoded and latched into a display resembling the pattern seen on
an ordinary pair of dice.
A conventional logic diagram for the dice game is shown in
Figure 16. (A detailed logic derivation is shown in the PAL
applications section of this handbook). It is implemented using
standard TTL, SSI and MSI parts, with a totall.C. count of eight:
six quad gate packages and two quad D-Iatches. Looks like a
nice, clean logic design, right? Wrong!!
PAL Goes to the Casino
A brief examination of Figure 16 reveals two basic facts: first, the
circuit contains mostly simple, combinatorial logic, and second,
it uses a clocked state transition sequence. Remembering that
the PAL family contains ample provision for these features, the
PAL catalog is consulted. The PAL16R8 has all the required
functions, and the entire logic content of the circuit can be
programmed into a single PAL shown in Figure 19.
Figure 17
PAL Logic Symbols
The logic symbols for each of the individual PAL device:; gives a
concise functional description of that PAL's logic function. This
symbol makes a convenient reference when selecting the PAL
that best fits a specific application. Figure 18 shows the logic
symbol for a PAL 10H8 gate array.
In this example, the PAL effected an eight to onepackage count
reduction and a Significant cost savings. This is typical of the
power and cost effective performance that the PAL family brings
to logic design.
ROLL
VCC
+5V
.J...
r---_--.--~
2K
o------~-~
120(1
Figure 18
A PAL Example
As an example of how the PAL enables the designer to reduce
costs and simplify logic design, consider the design of a simple;
Figure 19
1·13
D
PAL Introduction
Advantages of Using PALs
Design Flexibility
The PAL offers the systems logic designer a whole new world of
options. Until now, the decision on logic system implementation
was usually between SSI/MSI logic functions on one hand and
microprocessors on the other.. In many cases the function
required is too awkward to implement the first way and too
simple to justify the second. Now the PAL offers the designer
high functional density, high speed, and low cost. Even better,
PALs come in a variety of sizes and functions, thereby further
increasing the designer's options.
The PAL has a unique place in the world of logic design. Not
only does it offer many advantages over conventional logic, it
also provides many features not found anywhere else. The PAL
family:
Space Efficiency
• Programmable replacement for conventional TTL logic.
• Reduces IC inventories substantially and simplifies their
control.
• Reduces chip count by at least 4 to 1.
• Expedites and simplifies prototyping and board layout.
• Saves space with 2()..pin and 24-pin Skinny DIP packages.
• High speed: 25ns typical propagation delay.
• Programmed on standard PROM programmers.
• Programmable three-state outputs.
• Special feature eliminates possibility of copying by
competitors.
All of these features combine together to lower product development costs and increase product cost effectiveness. The
bottom line is that PALs save money.
Direct Logic Replacement
By allowing designers to replace many simple logic functions
with single packages, the PAL allows more compact P.C. board
layouts. The PAL's space saving 20 pin "skinny dip" helps to
further reduce board area while simplifying board layout and
fabrication. This means that many multi-card systems can now
be reduced to one or two cards, and that can make the difference between a profitable success or an expensive disaster.
Smaller Invel1tory
In both new and existing designs the PAL can be used to
replace various logic functions. This allows the designer to
optimize a circuit in many ways never before possible. The PAL
is particularly effective when used to provide interfaces required
by many LSI functions. PAL flexibility combined with LSI function density makes a powerful team.
1·14
The PAL family can be used to
replace up to 90% of the
conventional TTL family with
just 25 parts. This considerably
lowers both shelving and inventory cataloging requirements. Even better, small
custom modifications to the
standard functions are easy
for PAL users; not so easy for
standard TTL users.
PAL Introduction
Secure Data
High Speed
The PAL family runs faster or equal to the best of bipolar logic
circuits. This makes the PAL the ideal choice for most logical
operations or control sequence which requires a medium
complexity lind high speed. Also. in many microcomputer
systems. the PAL can be, used to handle high speed data
interfaces that are not feasible for the microprocessor alone.
This can be Llsed to significantly extend the capabilities of the
low-cost. low-speed' NMOS microprocessors into areas formerly
'
requiring high-cost bipolar microprocessors.
Easy Programming
The members of the PAL family can be quickly and easily
programmed using standard PROM programmers. This allows
designers to use PALs with a minimum investmE;lnt in special
equipment. Many types of programmable 'logic. such as the
FPLA. require an expensive, dedicated programmer.
The PAL verification logic can be completely disabled by
blowing out a special "last link." This prevents the unauthorized
copying of valuable data,. and makes the PAL perfect'fo'r use in
any applioation. where df' integrity m~st be carefully guarded.
Summary
The 25 member PAL family, of logic d~vices offers logic designers new options in the implementation of sequential and
combinatorial logic designs. The family is fast. compact.
flexible. and easy to use in both new and existing deSigns. It
promises to, reduce costs ,inmost areas of design and
production with a corresponding increase ii1 product profitability.
A Great Performer !
D
PAL Introduction
PAL16R6
~he~
COnnection !
uf{- "
nPl>-"
ru~
~PI>t-J
fUlr"
U~"
I.
. PAL16R61-C>gic Diagram
PAL16R6 Logic Symbols
~SOUfICE
MID ....-oGRAMMAII E
ClRCUn'RY
IIRSCIlLLANEOUS
AND TESnNG
CIRCUITRY
PAL16R6 Metalization
2·1
PAL Family
)
FAIVlILV
~5 ~ - COunt@tn!
2-2
T
PAL Family
PAL Logic Symbols
PAL10H8
PAL12H6
Active
High
PALs
OCTAL 10 INPUT
AND-OR GATE ARRAY
HEX 12 INPUT
AND-OR GATE ARRAY
PAL14H4
PAL16H2
QUAD 14 INPUT
AND-OR GATE ARRAY
DUAL
INPUT
AN.D-OR GATE ARRAY
16
2·3
PAL Family
PAL Logic Symbols
PALs With Complementary Output
PAL20C1
PAL16C1
16 INPUT
AND·OR AND·OR·INVERT GATE ARRAY
20 INPUT
AND-QR AND·OR·INVERT GATE ARRAY
Active Low PALs
PAL10L8
OCTAl: 10 INPUT
AND·OR·INVERT GATE ARRAY
2·4
PAL12L6
HEX 12 INPUT
AND·OR·INVERT GATE ARRAY
PAL14L4
PAL16L2
QUAD 14 INPUT
AND-QR·INVERT GATE ARRAY
DUAL 16-INPUT
AND·OR·INVERT GATE ARRAY
PAL Family
PAL Logic Symbols
More Active Low PALs
PAL12L10
PAL14L8
PAL16L6
DECA 12 INPUT
AND-OR-INVERT GATE ARRAY
OCTAL 14 INPUT
AND-OR-INVERT GATE ARRAY
HEX 16 INPUT
AND-OR.JNVERT GATE ARRAY
PAL18L4
PAL20L2
{
QUAD 18 INPUT
AND-DR-INVERT GATE ARRAY
y
DUAL 20 INPUT
AND-DR-INVERT GATE ARRAY
2·5
PAL Family
PAL Logic Symbols
PALs With Feedback
PAL20L10
PAL16L8
DECA 20 INPUT
AND-OR-INVERT GATE ARRAY
OCTAL 16 INPUT
AND-OR-INVERT GATE ARRAY
PALs With Registered Outputs
2-6
PAL16R8
PAL16R6
OCTAL 16 INPUT REGISTERED
AND-oR GATE ARRAY
HEX 16 INPUT REGISTERED
AND-OR GATE ARRAY
.PAL16R4
QUAD 16 INPUT REGISTERED
AND-QR GATE ARRAY
PAL Family
PAL Logic Symbols
PALs With Exclusive OR
PAL20X4
PAL20X8
PAL20X10
DECA 20 INPUT REGISTERED
AND-OR-XOR GATE ARRAY
OCTAL 20 INPUT REGISTERED
AND-OR-XOR GATE ARRAy
QUA!, 20 INPUT REGISTERED
AND-OR-XOR GATE ARRAY
PALs With Arithmetic Gated Feedback
PAL16X4
PAL16A4
QUAD 16 INPUT REGISTERED
AND-OR-XOR GATE ARRAY
QUAD 16 INPUT REGISTERED
AND-CARRY-OR-XOR GATE ARRAY
2·7
PAL Family
Logic Diagram PAL10H8
0123
1
45
,,
INPUTS (0-31)
1213
1617
2021
2425
2829"3031
...
.
~
,
2
3
,
.......
,,
......-
19
..
....
17
16
17
4
18
~
..
...
......-
~
16
~
"
25
5
.
...
~
"
15
4D
14
33
6
.....
~
41
7
I
~
-'""'
48
49
8
...
13
~
...
12
"
57
9
....
iC
III
0123
2-8
45
II
,,
12tJ
II
1617
I
2021
2425
III
28293031
11
....
PAL Family
Logic Diagram PAL12H6
INPUTS (0-31)
1
..
2
...
012 J
...
4567
89
1213
2021
1611
24252621
28293031
~
,
"
.......
8
~
...
4
17
-<
16
17
....
18
./
11
J
19
"""....
...
....
~
'"
~
.
2.
S!-
16
25
~
CI)
~
a::
w
l-
,
....
t
;:)
c
IS
32
33
oa::
a.
~
..
6
~
••
"
1
~
14
~
...
.,.,
I
,
"
SI-
.......
13
../
..
I
8
.....
9
....
~
12
....
,
0121
4561
a9
1213
1617
2021
24252627
"""
30;
. ..
11
28293031
2·9
PAL Family
Logic Diagram PAL14H4
INPUTS (0-31)
1
1
...
...
...
0123
<1567
891011
1213
1617
20212223
24252627
28293031
~
...
3
.
,
...
.....
,
,
16
11
"
18
UJ
18
17
./
19
5
19
....
::E
a:
w
14
16
25
26
l-
~~
27
t)
:::)
Q
o
a:
Q.
-'"""'
32
33
34
35
6
-
...
~
15
./
40
'"
41
42
../
43
7
8
9
2·10
...
.
JI:: ,
...
...
....
"
13
11
~
~
11
~
0123
4567
891011
1213
1617
20212223
24252627
282931J31
PAL Family
Logic Diagram PAL16H2
INPUTS (O-31)
1
,
3
4
..
....
0123
4561
891(111
12131415
16111819
20212223
24252627
28293031
~
:JIt
_JC
19
....
..
.....
18
....
..
JC
....
17
24
25
16
17
28
U)
29
::E
3D
a::
w
lI-
5
o
"'"
16
'"'
15
31
..
32
33
:::I
C
3'
35
o
a::
Q..
36
./
37
38
39
6
7
•
9
...
.
14
~
..
~~
.......
...
12
....
...
....
....
....
:JIt
o
1 2 3
4 5 6 7
a
9 1011
12131415
16111819
20212223
24252627
11
28293031
2·11
PAL Family
Logic Diagram PAL16C1
1
2
3
•
....
INPUTS (0·31)
o
1 2 3
4 fi 6,1
8 91011
12131415
16171819
202122 23
24252627
28293031
~
...
...
~
~ ..
19
1C.
....
....
...
18
....
.....
C
17
....
24
""
17
18
19
5
..
3D
J1
16
.1
15
J1
JJ
34
J5
J6
""
"
6
...
...
....
7
....
8
....
9
..
....
"
....
13
....
....
o
2-12
....
....
1 2 3
/I
5 0 1
8 9 10"
12131415
1& 171819
20212223
24252627
28293031
12
11
PAL Family
01
~
23
456
,
Logic Diagram PAL20C1
-
INPUTS (0 39)
891011
12131415
161/1819
202'
n
23
~4
25 26 27
28293031
32 ]334 35
36]13839
+-
~
~
23
3
3::J
22
~
.....
21
~
~
-z.....
20
"'-;.>-
....
4
,
I
I
5
~l
"
J3
34
(j)
e..
1
33
I-
}-
38
::!E
a:
w
h
36
IIJ
I
....rD)--'
35
":'
39
6
»-
---
..."!It..
....
t:J
..
0
"
"
c
~
"
a:
Il.
tEt>J
44
r-
"
~
"
"
7
8
-.r1
...
7"
10
11
17
--t~
...
-<>'1
.
o
oa:
a..
J1
15
3J
34
3S
6
100.
...
~
40
"
41
"43
)
,
9
2·16
...
..
.
...
14
./
4567
1J
.....
12
~
~
II 123
....
891011
1213
1611
20212223
24252627
H
28293{\31
s::]
11
PAL Family
Logic Diagram PAL18L2
INPUTS (0-31)
1
2
3
•
...
...
(J
I 2 J
4567
891011
12131415
16171819
2DZI:t2Zl
24252621
2B293031
~
....
...
...
...
19
€
~
...
~.
18
-~
...
...
....
17
~
"
25
26
21
28
I/)
....
16
"-
15
,
l'
30
::IE
a:
w
'"
./
29
~
...
~
31
"
""
33
5
o
36
J7
If
"
39
...
6
...
7
...
8
...
9
.....
.....
13
.....
12
"'"
....
...
....
...11::
A
o
....
1 2 3
4
~
b 7
8 9 1011
12 1314 1~
161118 19
2021 2223
2425-2627
11
2829 3D 31
2-17
PAL Family
Logic Diagram PAL12L10
INPUTS (0-39)
24
2~
36373839
2829
L~
•
-tj.-L-
\
23
~
10'1)-
.,
3
~
-u-
11
-o-r
25
>
b-L
33
...r\-
--tJ--L
41
18
17
16
~
...r\-
~
"
15
2
~
12
-t::5-
13
~
0123
2.18
-
~
......
..
11
19
~
"
"
10
-
~
B=Lr
"
9
20
2
..
8
21
~.
..
7
-
~
"
6
-
2
14
5
-
22
>
"
4
-
~
......
.,
-
J ........
.'C
I
20 H
2425
2829
3233
36373839
14
13
PAL Family
Logic Diagram PAL14L8
INPUTS (11-39)
Il
1
12
1
4!1
Ii
1
8
1213
9
1611
1021
24
2~
2829
32333435
36313839
~
~
S
.,
-Q-1. ........
"
2
-
"
11
4
~
25
tn
a:
~
5
"
::;)
Q
0
...
32
I0
6
.
-Q---f'-
21
B=D
20
-R-i'
v-
19
2
a:
Q.;
~
'"':'-
40
41
7
,22
2
"
I
e.
:&
.
23
-
10
3
....
""
.
18
I~
...
=B=D
17
~
-
-Q--r"
.....
"
57
!-..-f~
..
~
""
~
...
...
C·
------ufl
•
I
l'
,
~
6
,
.,
1•
-u-=r'
."
~
,1 ~
16
1,213
1811
2011
""
2821
32 ~~ 34· ~5
36 F3']!
14
13
PAL FarnUy ,
Logic Diagram PAL16L6
INPUTS (0-39)
0'
23
4567
a
9 1011
1213
1611
2021
21293031
2425
323334 35
36313839
~
~'
3
....,...
;r;:
~
So.
.-II
-Q--L
16
IJ
-Q--l-
IB
22
21
L..J"'
"
4
23
~
,....,
"
"
20
25
'1...r"1
Z1
~~
13
6
-Q--r
19
.n.
18
--
"
~
40
41
-t5--L
~~
.
8
:-
,"so
"
R-.
-
">
:R:-I
51
"
P-lL..J",
"
59
9
17
.
16
15
~
..
,
"
10
...
14
..0,
13
~
!!..
..
l
01
Z 3
45
& 7
811DII
1213
1611
2021
2425
ZIn3031
12133435
36373139
PAL Family
Logic Diagram PAL18L4
INPUTS. (0-39)
8
0123
1611
9 1011
2021
242526'27
2B293031
32333435
36313839
~
...
~
23
~~
...
4
:e;
~~
5
oS;
22
21
24
25
~
26
Z1
6
,
"
"
...
rr,
31
,.
"
33
--
-Q-i-.
~-L"
-
41
~
"'3
-O--t""'"
...
18
~
r-
"
"
52
}-,
"
--
15
~~
...
11
17
16
~~
10
19
.....
40
7
20
I
oS;
:e;
~
14
13
...
.~
01
t
3
89,1011
121311115
16,11
2·21
PAL Family
Logic Diagram PAL20L2
INPUTS (0-39)
0113
45
Ii
7
891011
12131415
16111819
20212223
24262621
28293031
~
31333435
36313839
I
~
23
~
....
3
22
.....
4
5
A
..
20
----1~
r-o
,."
"
"
"
"
"
33
6
'h
.......
19
I-'~
~
".
.,
42
.
."
7
21
~
18
1--1-"
I-
"...
...
8
17
16
----1
'"
9
A
15
.1i.
....
10
11
:Co
o
1 23
4 !Ii
Ii
1
8 91011
12 U14·15
1& "181'
202122 U
24 2&26·27
21213031
32333435
31313139
-
14
13
PAL Family
Logic Diagram PAL i6La
INPUTS (0-31)
,
0123
4561
891011
12131415
16171819
20212223
24252627
28293031
r-J
1
1
3
4
5
2
..
•
7
1I:.t---
~
....
8
9
>-J
10
11
11
13
3
14
15
.
.1--....
"
....
23
l-
5
..
~b-J
;A
.1---....
32
:l
C
~~b-J
33
34
35
o
a::
Il.
"
...
>->-;A
...
....
....I - - ~
.
~
....
~
>--J
J=
50
51
51
53
.>
"
55
11:
...
50
61
"
63
...
.JIIO
IJ 1 2 J
4 5 6 1
8 9 1011
12131415
16171819,
20212223
2425lfi 27
13
...t---'----
""
~W
57
.,"
59
..>
"
11:.1---
:It
49
9
r-J
-
47
48
8
15
-f---1
37
38
39
40
41
42
43
44
45
7
16
31
t)
6
~
....
14
15
16
17
28
29
3D
::IE
17
11:
C/)
w
>--J
-
12
a::
18
~
....~
16
17
18
19
10
•
19
...
12
11
....
2829)031
2·23
PAL Family
Logic Diagram PAL20L10
INPUTS (0-39)
0123
·
4
5
~
1
,
9 1011
1211141.
1617 1819
20212121
24252621
282930]1
12333435
36313839
.......
,
,
,
n-l/1>
....,
,
~
.1----
··
~L~
'"
"
3
Jt.
.
"
"
"
"LJ-l>--t>
,.
.....
"
"
"
....,
t-<
~~
..r-t>
"
..... -r
6
..
20
19
~
~
"
"
OJ
7
...
"'"
~T~
18
"LJ"T-l/;)
17
...
8
~
"
t-<
"
"
"
....,
~~.
.
..J.
16
~
.......
"
"
"
11
~
21
~
32
"34
10
22
.....
"
4
23
-.:n~
15
~~
K..L
....,
14
~
.
"
"
"
"
1C.
1
U I
1
J
4
ti
6'
B i
1011
12131415
18111819
20212121
24-252811
282'93031
32)334 35
35313.39
13
PAL Family
Logic Diagram PAL 16R8
-
INPUTS (0 31)
1
0123
4567
891011
12131415
16111819
20212223
24252627
28293031
0
I
~
2
3
r---,
4
5
6
~
)
2
~~~
""
../
.....
~
...
11:
r'
•
")-'
"
q
9
10
r--"
11
13
14
r-D
~
r-
15
3
Ul
....
.A
110
~
....
01---
~
~
16
17
"
~I--
"-
19
20
~
11
21
23
4
....
...~
...
<-
~~
14
Pl
~
~
~
25
16
'\.
27
19
~
30
a:
w
l-
~
"
U)
5
....
31
~
t;
;:)
""'4
"
C
33
oa:
14
'-
35
36
Q,
~
37
Ja
39
6
....
.....
~
...
~
...
40
~
41
42
43
~
44
45
46
47
7
....
~
~
....
..
49
"
51
51
53
./
54
8
....
"
iI:
~.
"
""
61
...
...
5)
"-
j
"
61
63
9
to.
...
7
'--L~t_
....
~
0123
4567
891011
12131415
16171819
20212223
24252627
282931131
~
Pl
~
Pl
~
~
2.25
PAL Family
Logic Diagram PAL16R6
-
INPUTS (0 31)
1
0123
4!i 61
B 91011
12131415
16171819
20212223
24252627
28293031
0
>-J
1
1
3
,
4
6
19
7
,
....
.....
"".1---
L
....
8
9
10
J
to.
-~
""
11
11
13
14
D
./
"
....
~
Ot--
~~
16
17
18
19
10
-
,
.
D
./
11
1Z
Ot--
~1
13
~
~
14
"
~
16
I/)
17
28
19
30
:::IE
31
a::
IU
5
...
lI-
"'"
./
~
o
.....
32
33
34
::I
C
"
35
36
o
a::
J)
~
J8
J9
6
....
....
to.
1C.
.Jt.-
ill
~
~
~
~
40
41
42
"'"
43
44
45
./
46
41
7
.....
_«:A
48
49
50
"""\..
51
e
to..
"""
"
A
"57
~
""
60
61
61
9
.....
...
r;-;;-~
./
"
...
o1
.t----....
Z 3
4 5 6 7
8 9 1011
12131415
1617 1819
20212223
24252621
28293031
~
~l
12
~
PAL Family
L ogle Diagram PAL18A4
1
INPUTS (O-31)
....
,,
0123
4561
891011
1611'1819
12131415
20212223
"24252621
28293031
,
-
~
J
4
5
6
19
7
3
~ -
.C!~
..........
••
""
~
. ID
IJ
14
"
3
18
...
"""'"
.
2 J
4
~
•
1
8 9 10 11
17
~
"-;:J.
.....
.
~
A_
~-
G ,
19
-O-L
~D-
"
"
"
"
10
. . 90- ~~
J-L
.......-
50
9
.
~1
.....
=;:,[>q- ~
"43·
8
Q
:IC:
33
6
:IC:
12 13 '4 15
z.
15
14
13
PAL Family
Logic Diagram PAL20X8
INPUTS (0-39)
1
.
0121
..
5
61
891011
121314,S
16111819
10212223
24 ZS 16 1I
l8nlOl!
32]33435
36313839
.......
,
,
~
,
~
.,
H=L
~
...
1fllY>- "
~
V"
;;.R~D-
"
"
"
"
Ifll
Ifll
tA....
2~DIfll
-t::5--L
~
"
"
"
"
I;l
IDD:til
5
20
......
,
......
"
"
"
"
...
~D-
.,
OJ
7
.
fu
-3-~~
"
;0
"
.
19
~
~
:D]
~
ID~ ~ ~
"
"
"
"
9
.~. 2JD-:tl]
:til.
.
."
;;J.. -15
......
Q
"
10
.......
H=t
6
~
j
;:::-Q-f"?D-
""
3
23
~
i;
......
"
"
~~
"
"
~>
o
1
13
..
S
6
1
8
9 1\111
12 ll14 15
16111119
20 1122 11
24152621
2B 2' 30 31
12 J334 J5
14
~
,..,.-
36313.39
2·29
PAL Family
Logic Diagram PAL20X4
INPUTS (0-39)
1
....
--V
··,
01
23
45
Ii
1
.91011
12131415
'1111119
20212223
24252121
21293031
3233341&
36313139
~I
1
~
i:.r--'
··
~
""
3
.
::::;>-tI I
"
.
----t
~D- ~~
"
"
"
~
~
.....
~D~
"
"
19
1-<1
!4
15
~
6
...
~D-
;;.
""
.n-L
..
~
.."
.
~
~
~[>~ ~
~
"
8
21
~
"
7
22
,....,
"
11
4
23
...
li
.......
51
:g:b -t\ I
"
51
51
9
16
.t---'
.
.."
......
I-(
"
I
.
..J.
15
.....1
~.
,....,
"
"
"
"
-K-l
,J.
14
.....
1
11
a
1
2
1
..
5
II
1
I
9 1011
12111415
1& 11 '119
2021,2223
14 nZI t7
It Z, 3G 31
32 33:i4 n
3& 31313'
.A..
~
13
PAL Family
Logic Diagram PAL16X4
-
INPUTS (031)
I
() 1 2 3
4561
B 91011
12131415
16171819
20212223
24252627
28293031
~
0
I
!
~
2
3
4
I
I
;
i
1
I
6
7
to..
...
~
,
>-~
9
JO
,
II
11
I
J
•
I
I
1;
...
~
=tig}D-
J6
17
W"
=ti
M
~DM
"
;:::
19
20
21
""""1-<:::1
22
13
4
~
----11
Conventional Symbology
PAL Symbology
i2 + IT
12
LOGIC STATE
~
VCC
H L L H
PRODUCT WITH ALL FUSES
; - BLOWN REMAINS HIGH
ALWAYS
INPUT
HIGH
11
IH
11 12 + 11 12
~ PRODUCT WITH ALL FUSES
INPUT
LOW -=
12
INTACT REMAINS LOW ALWAYi
11
l
SHORTHAND NOTATION
FOR ALL FUSES INTACT .,
PAL Logic Diagram
r
'0
PRODUC
LINT
E
NUMBER
;
,
~
,
7,:
"
L
I
11
4 S 6'
'191011
.
lIlTl'l'
ACTIVE HIGH
THREE-STATE ENABLE
CLOCKt
,-..
-K.
0-
r
.
INPUT LINE NUMBER
PIN
NUMBER
III
b
12
-"
...L
23
~1
]~~'"
=~D~~"
~-
o SUM OF PRODUC·
IS EaUAT ED AT THESE NODE
(BEFORE THE BUBBLE)
Q
UTPUT
'--coo NTROL
PAL Concepts
PALASM Flow Chart
(Main Program)
START
(
)
'-----r--l0L-________~R=EA~D~PA~L~P~A~R~T~N~O~&~T~IT~L=E--------~
20
READ PIN LIST AND STORE IN SYMBOL TABLE, ISYM
25
READ NEXT SYMBOL
NO
28
YES
PRODUCT GROUP = MATCH (OUTPUT SYMBOL)
NO
OR
(
YES
MATCH
NO
SET FUSES (MATCH) AND SAVE SYMBOL FOR PLOT
YES
*
64
NO
70
68
NO
+
YES
OR
74
(
OR
YES
NO
TweEK FUSES FOR NON-EXISTENT FUSE PATTERN
ECHO .INPUT PAL DESIGN SPECIFICATION
PRINT PINOUT
PERFORM FUNCTION TABLE SIMULATION
PRINT ENTIRE FUSE PLOT
PRINT BRIEF FUSE PLOT
OMIT PHANTOM FUSES AND UNUSED PRODUCT LINES
GENERATE HEX OR BINARY PROGRAMMING
FORMATt
C,_____
~
S_T_O_P_____
tA SPECIAL DATA 1/0 FORMAT IS PROVIDED FOR SERIES 24 PALs.
OPTIONAL
(MUST ENTER
APPROPRIATE
OPERATION CODE)
PALASM 24 Source Code
PALASM Flow Chart (Simulator)
READ NEXT
PIN NAME
LBUF = FALSE
IF INVERTED
READ FUNCTION TABLE
PIN LIST. STORE IN
ISYM1. LPHAS1 = FALSE
IF INVERTED
IPROD = L
READ LOGIC EQUATION
READ NEXT
PIN NAME
LBUF = FALSE
IF INVERTED
ISTATT (IOUTP) = H
.i:*-----{B
L-----------------~C
PALASM 24 ,Source Code
FUNCTION TABLE
VECTOR ERROR
EXPECT = H
ACTUAL = L
FUNCTION TABLE
VECTOR ERROR
EXPECT = L
ACTUAL = H
FUNCTION TABLE
VECTOR ERROR
EXPECT OUTPUT ENABLE
ACTUAL = Z
FUNCTION TABLE
VECTOR ERROR
EXPECT = Z
ACTUAL = L OR H
CH NGE ORDER ro- CXN1'INOE ••• ":A$
620 PRINT"" :PRINr"
THIS PROGRAM CAN BE RIJN IN EITHER THE"
630 PRINT"mtPlLED OR IN'l.'ERPREn'ED MJDES. THE CNLY DIFFERENCE"
640 PRINT"SIIXJLD BE THE SPEED OF OPERATICN." :PRl:Nr""
650 PRINT:PRINT"FINE PRINl':"
660 .PRINT"THIS PROGRAM IS DISTRIBUl'ED CN AN --AS IS -- BASIS."
670 PRINT"IT WAS TRANSLATED FIOI! A FORl'RAN IV PROGRAM"
6S0 PRINT"AND EVERY EFFORl' WAS TAKEN TO INSURE ITS AO:lJAACY."
690 PRINT"lD'JE.VER, THE USER SHOOLD ALSO VERIFY ITS AO:lJAACY"
700 PRINT"AND mtPIETENESS. ":PRINT"" : PRINT" "
710 PRINT:INPUr"PRESS TO BEX;IN PROGRAM ••• ":A$
1000 A$="":FORX%=lT016:PRINT"":NEXT:CI.EARl.000:DEFINTC,F,H,N,O,T,X,Y,Z
1010 DIME' (31, 63) :DEFSTRA,D,L,P:DIw.(15) ,P (21) ,L(50) :C=O:X$="" :A$=""
1020 x=o :PRINT"ENl'ER 1 TO CREATE PAL IESIGI SPEX:IFIC'ATICN FILE FIOI! KEYBOARD"
1030 PRINT"ENIER 2 ro RFAD EXISTING PAL IESIGI SPEX:IFICATICN FILE: " :
1040 INPU1'X:X=A8S(X):CNXGOT01060,1130
1050 GOT01000
1060 PRINT:PRINT:PRINT"ENIER IESIGt SPEX: FILENAME (FILENAME,/EJcr':D)"
1070 PRINT"ENTER "END'" (WITfDJI' ~) AFi'ER LAST LINE."
10S0 PRINT"FILENAME ? ":: LINEINPUl'A$
1090 OPEN"O",l,A$
1100 LINEINPUrA$
1110 IFA$=''END"THEN1120ELSEPRINI11,A$ :GOT01l00
1120 CLOSE:GOT01000
1130 ONERRORGOT02260
1140 PRINT:PRINT:PRINT"ENl'ER FILENAME (FILENAME,/EJcr' • PASSl'DRD: D) ro BE ":
1150 PRINT"PiSSEM3IED ?":LINEINPt11'F$
1160 X=l:OPEN"I" ,1,F$
1170 INPUTt1,A:L(X)=A:X=X+1:PRINtA
l1S0 IFECF(1)TBEN1l90ELSE1170
1190 CLOSE1:NL=X
1200~
2000
2010
2020
2030
2040
2050
2060
2070
20S0
2090
REM *** VERIFY PARI' NUMBER AND Gm' TYPE
A=L(l):TY=O
X=INSTR(A, "PAL")
***
OT$=MID$(A,X+5,1):P=MID$(A,X+6,1):P3%~(P)
PN=MID$ (A,X, 7) :P=IEFl'$ (PN,3) !IFP<>"PAL"THENGOT02090ELSEP=MID$ (PN,4,4)
IFP="10HS"0RP="10LS "'lHENl'Y=lELSEIPP=" 12H6 "ORP=" 12L6 "'l'HEN1'Y=2
IFP="14H4"0RP="14L4"'lHENl'Y=3
IFP="16H2"ORP=" 16L2"0RP= " 16C1 "THENl'Y=4ELSEIFP=" 16LS"THENl'Y=5
IFP="16R4"0RP="16R6"0RP="16R8"'lHENl'Y=6ELSEIPP="16A4"0RP="16X4"THENl'Y=7
IFTY=0'IHEN" "THENP (Y) =P (Y}+P ELSEY=Y+l
NEXT:IFY=21THEN2270ELSEIFY<21THENLC%=LC%+1:GOT02220
GCSUB7210 : PRINT II INVALID PIN LIST":END
RESUME1l30
IFP(10} <>"GID"THENPRINT"ERROR RRECl'ED ••• PIN 10 IS NCM ..~Ir·":p(10}="QID
2280 IFP (20) <>''Va::''THENPRINT''ERROR RRECl'ED ••• PIN 20 IS NOO \Ta::"II:P (20) ="Va::
II
2290
2400
2410
2420
2430
2440
2450
2460
2470
2480
2490
2500
2510
2520
2530
2540
2550
2560
2570
2580
2590
2600
2700
2710
2720
2730
2740
2750
2760
2770
2780
2790
2800
2810
2820
2830
3000
3010
3020
3025
3030
3040
3050
3060
CNERRORGOrOO : 4THENN0=8ELSENO=P3%
LC%=LC%+l:A=L(LC%) :IFLC%>NLTHEN4010
FC=O :FS=O :FR=O :AT="" :DL="} / "
CE=INSTR(A, "="} :IFCE=OTHEN2420
OU=OU+1:IFCU>NO THEN3290
AL=LEFI'$ (A,CE-1) :CT=IEN (A) :CN=CE
CN=CN-1:IFCN=OTHENGOT02500
P=MID$ (A,CN,l) :IFP=" "THEN2470ELSEIFP=":"THENFR=1:GOT02470
P=MID$(A,CN,1}:IFINSTR(DL,P}=0~P+AT:CN=CN-1:IFCN<>OTHEN2490
FORZ=12T019 :IFAT=P (Z}ORP (Z) = ("/"+AT) THEN100THENFR=1:Y=Y-100ELSEIFYOTHEN2590
IFFC=lANDINSTR(AL, ") "}=OTHENY=Y+l:CN=CE+l:OT8ENCN=CE+1:Y=Y+1:en;ua4410:GOT03050
CN=INSTR(AL," (") :CT=INSTR(AL,"} ") : IFCN=00RCT=OTHEN259 0
A=AL:CN=CN+1:CT=CT-1
IFINSTR(A, "+") <>OTHEN D'I'HENPRINT" # II ;A:END
DL=" (:) +*" :AT=""
IFCN>CI'l.'HEN:.OI'02810
P=MID$ (A,CN,l) :IFP=" "THENCN=CN+1:GOT02770
IFINSTR(DL,P}=0THENAT=AT+P:IFCN<>C1'I'HENCN=CN+1:GOT02770
GCSUB3200:GOT02760
.
Y=Y+1:A=L(LC%) :CN=CE+1:CT=IEN(A)
GCSUB4410
G0T03050
REM *** INPtJl' PRCX::ESSING FOR SIMPLE CUI'PUI'S ***
LC%=LC%+l:A=L(LC%) :IFLC%>NLTHEN4010:REM** RE..,.ENTRY POINT **
IFINSTR(A, "DESCRIPTICN"} <>OT8EN4010
IFINSTR(A, "FUNcrICN TABLE"} <>OTHEN4010
cr=LEN(A}:CN=l
IFINSTR(A,"="}<>OTHEN2430
DL=" (:)+* ":AT=""
IFCN>CTTHEN3010
3·59
Basic PALASM Source Code
3070
3080
3090
3100
3110
3120
3130
3140
3150
3160
3200
3210
3220
3230
3240
3250
3260
3270
3280
3290
3300
3310
3320
4000
4010
4020
4030
4040
4050
4060
4070
4080
4090
4100
4110
4120
4400
4410
4420
4500
4510
4520
4530
4540
4550
4560
4570
4580
4590
4600
4610
4620
4630
4640
4700
3.60
P=MID$ (A,CN,l) :IFP=" "THENCN=CN+l:00l'03060
IFP="+"ANrlI\T<>""THENY1THEN3150ELSEY1THEN3150ELSEGaSUB4410:00l'03060
IFP="*"THENGCl3UB3210:00l'03050
IFTY=7AND(P="(" CR P=":")THEN9000
IFP="(" ORP=")" ORP=":"THEN2590
AT=AT+P:CN=CN+l
IFCI'=CN-l.ANI:lM'<>""THEN0'I'HENRETURNELlANDZ<10THENX=(Z-2)*4+1:RETURN
IFZ=10ORZ=20THENX=0:RETURN
IF (TY<6ANDZ=1) OR (TY>5ANDZ=19) THENX=3:RETURN
IF(TY<6ANDZ=11)OR(TY>5ANDZ=12)THENX=31:RETURN
IFTY=lTHENX=O:RETURN
IF(TY<5ANDZ=12)OR(TY>4ANDZ=13)THENX=27:RETURN
IF(TY<5ANDZ=19)OR(TY>4ANDZ=18)THENX=7:RETURN
IFTY=2'ffiENX=O:RETURN
IF(TY<5ANDZ=13)OR(TY>4ANDZ=14)THENX=23:RETURN
IF(TY<5ANDZ=18)OR(TY>4ANDZ=17)THENX=11:RETURN
IFTY=3THENX=0:RETURN
IFZ=140R(TY>4ANDZ=15)THENX=19:RETURN
IFZ=170R(TY>4ANDZ=16)THENX=15:RETURN
X=O:RETURN
REM **** 00TPUl' TABIE FUNcrICN ****
Basic PALASM Source Code
4710
4720
4730
4740
4750
4760
4770
4780
4790
4800
4810
4820
4830
4840
4850
4860
4870
4880
5000
5010
5020
5030
5040
5050
5060
5070
5080
5090
5100
5110
5120
5130
5140
5150
5160
5170
5180
5190
5200
5210
5220
5230
5240
5250
5260
5270
5280
5290
5300
5310
5320
5330
5340
5350
6000
Y=(19-Z)*8+1:NP=0:ZO=Z
IFY>57ORY<1'lmNY=0:RE1't1RN
IFrY=1THENNP=2:RE1't1RN
IF1'Y>4'l'HEmP=8
IFFcrGHT$(PN,2)=nRB n'lmNY=Y+100:RE1't1RN
IFrY=5THENY=-Y:RE1't1RN
IF1'Y>4AND(Z=12ORZ=19)THENY=-Y:RE1't1RN
IFFcrGHT$(PN,2)=nR6"THENY=Y+lOO:RE1't1RN
IF1'Y>4AND(Z=13ORZ=18)THENY=-Y:RE1't1RN
IF1'Y> 5THENY=Y+100 :RE1't1RN
IFZ=12ORZ=19THENY=0:RE1't1RN
IFrY=2AND(Z=13ORZ=18)THENNP=4:RE1't1RN
IFrY=2THENNP=2:RErUm
IFZ=13ORZ=l8THENY=O:RErUm
IFrY=3'lHEml?=4:RErUm
IFZ=140RZ=17THENY=0:RErUm
IFRIGHT$(PN,2)=nCl nTHENY=25:NP=16:RETURN
NP=8:RmURN
REM **** VIRGIN FUSE PATl'ERN INITIALlZATICN ****
NB=0:0NTYG0T05020,5060,5160,5240,5320,532Q,5320
FORY=0T063STEP8:FORX=OT031:F(X,Y)=0:F(X,Y+1)=0:F(X,Y+2)=2:F(X,Y+3)=2
F.(X, Y+4) =2:F (X, Y+5)=2:F (X, Y+6)=2:F (X,Y+7) =2:NEXTX, Y
FORY=OTOS7STEP8:FORX=6T027STEP4:F(X,Y)=3:F(X+l,Y)=3:F(X,Y+1)=3
F(X+1,Y+1)=3:NEXTX,Y:RErUm
IF01'$=nL nTHENC=2ELSEC=3
FORY=0T063STEP56:FORX=OT031:GOSUB5340:NEXTX,Y
FORY=8TOS5STEP8 :FORX=0T031~F (X, Y) =O:F (X,Y+l) =O:F (X', Y+4) =2
F(X,Y+5)=2:F(X,Y+6)=2:F(X,Y+7)=2:NEXTX,Y
FORX=0T031:F(X,10)=0:F(X,11)=0:F(X,50)=0:F(X,51)=0:NEXTX
FORY=18T043STEP8 :F(EX=0T031:F (X, Y) =2:F (X, Y+l)=2 :NEXTX, Y
FORY=8T049STEP8:FORX=10T023STEP4:F(X,Y)=3:F(X,Y+1)=3
F(X+1,Y)=3:F(X+1,Y+1)=3:NEXTX,Y
FORY=10TOS1STEP40:FORX=10T023STEP4:F(X,Y)=3:F(X,Y+1)=3
F(X+1,Y)=3:F(X+1,Y+1)=3:NEXTX,Y:RETURN
IF01'$="L nTHENC=2ELSEC=3
FORY=0T063STEP8 :IFY=16'lmNY=48
FORX=0T031:GOSUB5340:NEXTX,Y
FORY=16T047STEP8:FORX=0T031:F(X,Y)=0:F(X,Y+l)=0:F(X,Y+2)=0
F (X,Y+3)=0:F(X,Y+4)=2:F(X,Y+5)=2:F (X,Y+6)=2:F (X,Y+7) =2 :NEXTX,Y
FORY=16T043STEP2 :FORX=14T019STEP4: IFY=20'mENY=24EI..SEIFY=28THENY=32
IFY=36THENY=40
F(X,Y)=3:F(X,Y+1)=3:F(X+l,Y)=3:F(X+l,Y+l)=3:NEXTX,Y:RETURN
IFOT$=nL"'1HENC=2ELSEC=3
FORY=0T023STEP8 :FORX=OT031:F (X,Y) =C:F (X,Y+l) =C:F(X, Y+2) =C
GOSUB5340:NEXTX,Y
IF01'$=nH"THENC=3ELSEC=2
FORY=40T063STEP8 :FORX=0T031 :GOSue5340 :NEXTX, Y
C=O
FORY=24T039STEP8 :FORX=0T031 :GOSUB5340 :NEXTX, Y
RETURN
0=0 :FORY=0T0635TEP8 :FORX=0T031 :GOSUB5340 :NEXTX, Y
RETURN
F(X,Y)=C:F(X,Y+l)=C:F(XiY+2)=C:F(X,Y+3)=C:F(X,Y+4)=C
F(X,Y+5)=C:F(X,Y+6)=C:F(X,Y+7)=C:RErUm
REM **** X-PLOT FUNCTICN ****
3·61
Basic PALASM Source Code
6010
6020
6030
6040
6050
6060
6070
60S0
6090
6100
6110
6120
6130
6140
6150
6160
6170
61S0
6190
6200
"
Al="
11
A2="
0123 4567 S901
A3="X = FUSE INTACl'
A4="0 = PHANTCM FtJSE
1111 1111 2222 2222 2233"
2345 67S9 0123 4567 S901"
(LfN,O)
-.= FUSE BliM'l
(L,N,O)
0 = PHANTCM FUSE
(H,P,l)"
(H,P,l)"
~900
PRINl'"ENl'ER FII..ENAME (FILENAME,/E}cr'.PASSVllRD:D) FOR X-PLOl' CXJl'PU1' ? "
LINEINPtJ1'X$
QPEN"O",l,X$
C=O:A(O) ="X" :A(l) ="-" :A(2) ="on :A(3) =nO":CI.S:PRINl'L (3) :PRINT""
c:NERroROOl'OO
FORX=1T04:PRINl'i1,L(X):NEXTX
PRINTt1, "n :PRINTt1,"NUMBER OF Ft5ES BliM'l =" ~NB:PRINTt1, n"
PRINl':PRINl'"NtMmR OF FUSES BliM'l =n ~NB:PRINT
PRINTt1,Al:PRINTt1,A2:PRINl'#l," "
IFC=64THENPRINTt1," ":PRINTt1,A3 :PRINTt1,A4 :Al=" " :A3=" " :A4=" " :CI..Cl3E:RETt.JRN
PRINT:PRINl'Al:PRINTA2:PRINT
FORY=0'I07:CDruB6200:~
PRINTt1," ":PRINl':PRINT"I.F.Gr\ND: n :PRINTA3 :PRINTA4
FORX=0T0800 :NEXTX:CI.S :00:006150 .
A=n ":FORX=OT03lSTEP4:A:::A+A(F(X,C) )+A(F(X+l,C) ) +A(F(X+2,C) )+A(F(X+3,C) )+n
.
6210 NEXTX:PRINTUSING"tt"~C~:PRINTA
6220 PRINl't1,USING"it n ~C~ :pRINTt1,A$ :C=C+l:RE1'URN
6900 Gl3US7210 :PRINTnINVALIDFII..ENAME n : RESUME6050
7000
REM **** HEX FUNCtION ****
7010 A(O)="0":A(l)="1":A(2)="2":A(3)="3":A(4)="4":A(5)="5 n
7020 A(6) ="6" :A(7)="7" :A(S)="S":A(9)="9" :A(10) ="A" :A(11)="B"
7030 A(12)="C" :A(13)="D" :A(14)="E":A(15)="F"
7040 ~7200
7050 PRINl'"ENl'ER FII..ENAME (FILENAME,/E}cr'.PASSVllRD:D) FOR HEX CXJl'PU1' ? "
7060 LINEINPtJ1'X$
7070 ClPEN"On,l,X$
70S0 CNERROROO1'OO
7100 PRINl':PRINl'''NtMmR OF Ft5ES B~ =n ~NB:PRINT
.
7110 PRINT:PRINl'L(3):PRINT:PRINTt1,CHR$(lS)~CHR$(07)~CHR$(07)
7120 FORX=1T04:PRINTt1,L(X):NEXTX
.
7130 PRINTt1, "" :PRINTt1, nNtMmR OF Ft5ES BtaoN =" ~NB :PRINTi1, ""
7140 PRINTt1,CHR$ (01) ~CHR$ (02) ~
7150 C--1:FCRY=OT039:C=C+1:A="":IFY=STHENY=32
7160 FORX=OT031
7170 H=(F(X,Y)AND1)+(2*(F(X,Y+S)AND1»+(4*(F(X,Y+l6)AND1»+(S*(F(X,Y+24)AND1»
71S0 PRINl'A(H)+" "~:A=A+A(H)+" ":NEXTX:PRINT:PRINTt1,A:NEXTY
7190 PRINTt1,CHR$ (20) ~CHR$ (07) :cr..cm::RETt.JRN
7200 CDruB7210:PRINT"INVALID FI~":RESUME7040
7210PRINT n*** ERROR *** ••• ":RE.'.l'URl
SOOO
REM *** BHLF AND BPNF FUNcrICNS ***
SOlO cmRmROO1'08190
S020 PRINT"ENI'ER FILENAME (FILENAME,/E}cr'.PASSVllRD:D) FOR B"~D1~DO~"F CXJ1'PUl' ? n
S030 LINEINPtJ1'X$
S040 0PEN"0",1,X$
S050 CNERRORG:7I'OO
S060 PRINl':PRINl'L(3) :PRINT:PRINTt1,CHR$ (lS) ~CHR$ (07) ~CHR$ (07)
S070 FORX=1T04:PRINTi1,L(X) :NEXTX:PRINT#l,CHR$ (01) ~CHR$ (02)
SOSO FORY=OT039:IFY=8THENY=32
S090 FORX=OT031
Basic PALASM Source Code
8100 PRINI'''B'': :PRINI'i1, "B":
8110C=24:GOSUB8170:C=16:GOSUB8170
8120 C=8:GOSUB8170:C=0:GOSUB8170
8130 PRINT"F "::PRINTi1,"F ":
8140 IFX=7 ORX=lS ORX=23 ORX=31 THENPRINT"" :PRINTi1," "
81S0 NEXTX, Y
8160 PRINT:PRINTi1,CHR$(20):CHR$(07):CLOSE:RETURN
8170 IF (F (X, Y+C)AND1) =OTHENPRINTDO: :PRINI'U,DO: :RETURN
8180 PRINI'Dl: :PRINTi1,D1::RErtJm
8190 GOSUB7210 :PRINI'"INVALID FILENAME" :RESUME8010
9000
REM *** FOR 16A4 AND 16X4 PALS ONLY ***
9010 IFY<16ORy>47THEN2590
9020 IFP=": "THENAl=MID$ (A,CN,3)EISECDI'09060
9030 IFAl=":+: "THENY=4* (!NT «Y+4) /4» :GOSUB4410 :CN=CN+3:GCYI'030S0
9040 IFAl=": *: "'l'HENGIl3UB7210 : PRINI' " " : *:" IS USED INSIIE PARENI'HFSES ONLY":END
90S0 GOSUB7210:PRINI'""":P:"" IS INVALID AS USED IN:":PRINI'''i'':A:END
9060 N8=CN:N9=INSTR(CN,A,") ") :IEN9=0'mEN90S0
9070 Al=MID$ (A,N8 ,N9-N8+l)
9080 N=VAL(RIG8T$(Al,2»:IEN<00RN>3THEN9090ELSE9100
9090 GOSUB7210:PRINI'"INVALID EXPRESSICN "., :Al: II"":END
9100 X=N*4+8
9110 NO=IEN (Al) -3 :IENO>6THEN9090
9120 CNN0CDI'09130,91S0,9170,9180,9200,92S0
9130 C=2:GOSUB9300:IFMID$(Al,2,1)="A"THENC=3ELSEC=0
9140 GOSUB9300:CDI'09290
91S0 C=1:GOSUB9300:IFMID$(Al,3,1)="A"THENC=0ELSEC=3
9160 GOSUB9300:CDI'09290
9170 AT=Al:GCYI'03260
9180 C=2:GOSUB9300:IFINSTR(Al,"+") <>DTHEN9290
9190 C=0:GOSUB9300:C=3:GOSUB9300:CDI'09290
9200 IFINSTR(Al,"+B")<>DTHENC=0:GOSUB9300:CDI'09290
9210 IFINSTR(Al, "+/") <>DTHENC=3:GOSUB9300 :CDI'0929.D
9220 C=1:GOSUB9300:C=2:GOSUB9300
9230 IFINSTR(Al, "*B") <>DTHENC=0:GOSUB9300 :CDI'09290
9240 C=3:GOSUB9300:CDI'09290
92S0 IFINSTR(Al, "+/") <>DTHENC=1:GOSUB9300 :CDI'09290
9260 IFINSTR(Al, "+:") <>OTHENC=1:GOSUB9300 :C=2:GOSUB9300:CDI'09290
927.DC=0:GOSUB9300:C=3:GOSUB9300
9280 IFINSTR(Al, "* /") <>DTHENC=1:GOSUB9300 :CDI'09290
9290 CN=CN+NO+3:GCYI'030S0
9300 F(X+c,Y)=0:NB=NB-1:RErtJm
3-63
Notes
3-84
4·1
Applications
Table of Contents
PAL Applications
Basic Gates .............................................. 4-3
Basic Clocked Flip-Flops .............. ;................... 4-9
Memory Mapped I/O .......... ,........................... 4-17
Memory Interface Logic for 6800 Microprocessor Bus ..... 4-23
Video Logic .............................................. 4"31
Binary to BCD Converter ................................. 4-37
Deglitcher ...........................•......• , ............ 4-47
Electronic Dice Game ..................................••.. 4-53
9-Bit Register ............................... , . . . . . . . . . . . .. 4-63
Multifunction Octal Register ............................... 4-69
8-Bit I/O Priority Interrupt Encoder with Registers .....•... 4-77
BCD/Hex Counter ...................'. ............ : ....... 4~83
64k Dynamic RAM Refresh Controller .. , ........... : : ..... 4-91
State Counter .for Multiplier/Divider. • . . . . . . • . . . . . . . . . . . . . .. 4-99
ALU/Accumuliltor ........................................ 4-107
Stepper Motor Controller ................. : ............... 4-113
Shaft Ehcoder .: .. .. .. .. .. .. .. .. . .. .. . .. . .. ... . . .. .. ..... 4-123
Quad 4:1 Mux ..................;........................... 4-129
Dual 8:1 Mux ............................................ 4-137
Introduction to PAL Applications
The PAL family brings a unique'flexibility to the field of. logic
design. Using PALs, designers can both replace conventional
logic in existing products and optimize the design of new
products. Previous sections discussed the PAL concept and
provided information on the advantages gained and the
techniques used when designing with PALs. This section shows
PALs at work in applications ranging from simple logic gate
replacemenUo complete system designs.
Each example is presented as a.complete PAL design. The
required logic function is described, the PAL that best solves the
16:1 Mux ................................................
Octal Shift Register ......................................
4-Bit Shift Register/Comparator ..........................
4-Bit Counter with 2 Input Mux ..........................
Octal Counter ...........................................
OctalUp/Down Counter .................................
10-Bil Counler ...........................................
4-Bil Up/Down Counter wilh Shift Register and Comparator.
4-Bil Flash Gray AID Converter ..........................
4-Bit Gray D/A Converler ................................
8-Bit D/A Converler. .. . .. .. .. .. . .. . .. . . .. . .. . .. . .. . .. ....
Octal Comparator ........................................
Between Limits Comparator ..............................
Memory Mapped Printer .................................
Craps Game .............. : ................ '.' ............
Traffic Signal: Controller .................................
32-Bit CRC (Cyclical Redundancy Checking) Error Detection.
8-Bil Error Detection and Correction .....................
4-145
4-153
4-161
4-169
4-177
4-185
4-193
4-201
4-209
4-217
4-225
4-233
4-239
4-251
4-261
4-285
4-301
4-329
problem is selected, and the actual PAL logic implementation is
shown. The. PAL ,1pgic is shown as both the PAL design
specification and the actual .PALASM output for the PAL
programmer. This makes the examples complete enough to
serve as gui~es for designers using PALs in their own systems.
The PAL is a versatile device whose applications are practically
unlimited. These applications examples, combined with the PAL
design information contained..in the rest of this book, will help
designers to get the feel of PAL design procedures. With a little
practice and study, PAL design will become a natural extension
of the normal logic design process.
Basic Gates
PAL12H6
vee
o
Basic Gates
PAL DESIGN SPECIFICATION
VINCENT COLI 06/12/81
PAL12H6
BGATES
BASIC GATES
MMI SUNNYVALE, CALIFORNIA
CDFGMNPQIGNDJKLROHEBAVCC
B = /A
E
,INVERTER
= C*D
~=O---E
,AND GATE
F=D.. ·
,OR GATE
L
o
= /I
+ /J + /K
= /M*/N
R = P*/Q
G
I~'
'.'
. L
.k
,NAND GATE
==D-
J.,R GATE
+ /P*Q
H
7EXCLUSIVE
o
'.
M~
. . ···0
N~~-'
p_---I
OR GATE
R
Q---<.......
PAL12H6
4.4
Basic Gates
FUNCTION TABLE
ABC D E F G H I JKLMNOPQR
:AB
CDE
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
FGH
IJKL
MNO
PQR
COMMENTS
-----------------------------------------------------------LH
XXX
XXXX
xxx XXX
TEST INVERTER
XXX
XXX
XXXX
xxx XXX
TEST INVERTER
HL
XXX
TEST AND GATE
XX
XXX
XXXX
xxx XXX
LLL
TEST AND GATE
xx LHL xxx XXXX xxx XXX
XXX
XXXX
xxx XXX
TEST AND GATE
XX
HLL
XX
XXX
XXXX
xxx XXX
TEST AND GATE
HHH
LLL
LHH
HLH
HHH
XXX
XXX
XXX
XXX
XXX
xxx
xxx
xxx
xxx
xxx
xxx
xxx
XXX
XXXX
XXXX
XXXX
XXXX
LLLH
LLHH
LHLH
HLLH
HHHL
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
LLH
LHL
HLL
HHL
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
LLL
LHH
HLH
HHL
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
OR GATE
OR GATE
OR GATE
OR GATE
NAND GATE
NAND GATE
NAND GATE
NAND GATE
NAND GATE
NOR GATE
NOR GATE
NOR GATE
NOR GATE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
OR
OR
OR
OR
GATE
GATE
GATE
GATE
D
-----------------------------------------------------------DESCRIPTION
THIS EXAMPLE ILLUSTRATES THE USE OF FUSIBLE LOGIC TO IMPLEMENT THE BASIC
GATES: INVERTER, AND GATE, OR GATE, NAND GATE, NOR GATE, AND EXCLUSIVE OR
GATE.
THE FUNCTION TABLE EXERCISES ALL INPUTS AND TESTS BASIC FUNCTION PERFORMANCE.
PALASM EXERCISES THE FUNCTION TABLE TO SIMULATE THE BASIC GATES.
4·5
Basic Gates
BASIC GATES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
XXXXXXXXXXXXXXXXXH01
XXXXXXXXXXXXXXXXXL11
00XXXXXXXXXXXXXXLXX1
01XXXXXXXXXXXXXXLXX1
10XXXXXXXXXXXXXXLXX1
11XXXXXXXXXXXXXXHXX1
XXOOXXXXXXXXXXXLXXX1
XX01XXXXXXXXXXXHXXX1
XX10XXXXXXXXXXXHXXX1
XX11XXXXXXXXXXXHXXX1
XXXXXXXXOXOOHXXXXXX1
XXXXXXXXOX01HXXXXXX1
XXXXXXXXOX10HXXXXXX1
XXXXXXXX1XOOHXXXXXX1
XXXXXXXX1X11LXXXXXXI
XXXXOOXXXXXXXXHXXXX1
XXXX01XXXXXXXXLXXXXI
XXXX10XXXXXXXXLXXXX1
XXXX11XXXXXXXXLXXXX1
XXXXXXOOXXXXXLXXXXX1
XXXXXX01XXXXXHXXXXXI
XXXXXX10XXXXXHXXXXXI
XXXXXX11XXXXXLXXXXXI
PASS SIMULATION
BASIC GATES
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
8
---- IA
---x --
16 X-X24
25
32
---- C*D
X---
---- F
---- G
X-
-x
-x
IM*/N
40
41
X-
-x
---x IJ
---x ---- IK
X : FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
4.6
P*/Q
IP*Q
-X-- II
48
49
50
LEGEND:
-X-X---
306
FUSE BLOWN
(H,P,l)
Basic Gates
Basic Gates
Logic Diagram PAL12H6
012 J
c
1
D
2
...
4561
89
1213
1617
1021
24252621
21293031
~
...
A
...
,
8
F
.,(
10
11
-
16
-
4
I
::r"'\.
18
B
17
E
./
...
-
""
M
5
:J-(
16
::::J
15
J3
"
J
~
14
R
.
•
.
48
./
51
8
9
.
...
13
"
"
Q
o
~
4D
41
p
H
...
...
"
N
A
J
11
G
19
~
""
....
~
~
1213
1611
"'''
24252617
L
12
K
11
J
.:
28293031
4·7
Notes
4·8
Basic Clocked Flip-Flops
PAL16R8
ClK
VCC
JKT
K
.iKe
TT
PR
TC
ClR
OT
0
DC
D
SRT
R
SRC
GNO
4·9
Basic Clocked Flip-Flops
PAL16R8
BFLIP
BASIC CLOCKED FLIP-FLOPS
MMI SUNNYVALE, CALIFORNIA
CLK J K T PR CLR D S R GND
/OC /SRC /SRT /DC /DT /TC /TT /JKC /JKT
PAL DESIGN SPECIFICATION
VINCENT COLI 07/19/81
vec
JKT : = J* /JKT* /CLR
+ /K* JKT* /CLR
+ PR
7J-K FLIP-FLOP (TRUE)
7 (JKT .. Q)
7PRESET Q
JKC : .. /J* K */PR
+ /J* /JKT* /PR
+ K* JKT*/pR
+ CLR
7J-K FLIP-FLOP (COMPLEMENT)
7 (JKC = /Q)
'1'"1'
:=
T*/'1'"1'*/CLR
+ /T* '1'"1'*/CLR
+ PR
,
7CLEAR /Q
7T FLIP-FLOE' (TRUE)
7 ('1'"1'= Q)
7P,RESET Q
TC
: = /T* /'1'"1'* /PR
+ T* '1'"1'*/PR
+ CLR
7T FLIP-FLOP (COMPLEMENT)
f (TC = /Q)
7CLEAR /Q
DT
:=
7D FLIP-FLOP (TRUE)
7PRESET Q
D*/CLR
+ PR
DC
:= /D*/PR
+ CLR
SRT : =
S*
/CLR
/R* SRT* /CLR
+ PR
+
SRC := /S* R */pR
+ /S*/SRT*/PR
+ CLR
4-10
(DT
OJ
7D FLIP..,FLOP (COMPLEMENT)
7CLEAR /Q
Q)
(DC =
/Q)
7SET-RESE'l' FLIP-FLOP (TRUE)
7 (SRT .. Q)
rPRESET Q
7SET-RESET FLIP-FLOP (COMPLEMENT)
7 (SRC = /Q)
7CLEAR /Q
Basic Clocked Flip-Flops
FUNCTION TABLE
CLK loe PR CLR J K .JKT JKC T TT TC 0 OT DC S R SRT SRC
CONTROL
C
~ LK
I
oe PR CLR
X a x
x
J-K FLIP-FLOP
IN
OUT
J K Q. IQ
x x
Z
Z
T FLIP-FLOP
IN
OUT
T
Q IQ
x
Z
Z
0 FLIP-FLOP S-R FLIP-FLOP
IN
OUT
IN
OUT
0
Q IQ.
S R Q IQ
x
Z
x
x
COMMENT
Z
x x
x
x x x x
x x x x
X. x x
x
x x x x
x x x x
x x x x
x x x x
x x x~ x
x x x x
x x xx
CLEAR
x x x
x
CLEAR
x. x x
x x x
x x x
x
x
x
TOGGLE
TOGGLE
Z
Z
aI-Z
TEST J-K FLIP-FLOP
eLL
C L L
C L L
C L L
C L L
C L L
C L L
C L a
C L L
C L L
a
L
L
L
L
L
L
L
L
L
x X L
a
L
L
L
a
L
a
L
a
a
a
a
L
a
L
a
L
L
L
a
L
L
a
L
a
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
x
x
x
x
x
x
x
x
x
x
x
x
x.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x a
L
a
a
L
a
a
L
a
L
x
x
x
x
x
x
x
x
x
x
x
·x
L
L
L
a
a
a.
L
x
aL
x
x. x
xx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
X
L
Ii
L
x x
x x
xx
x x
xx
x
x
x
x
x
TOGGLE
PRESET
TOGGLE
TEST T FLIP-FLOP
C
C
C
C
C
L
L
L
L
L
L
L
L
L
a
a
L
L
L
L
x
x
x
x
x
x
x
x
x
x
a
L
a
x
x
x
x
x
x
x
x
x
x
x x x
x
PRESET
TEST 0 FLIP-FLOP
C
C
C
C
L L
L L
L L
L L
a
C
L
L
H
L
L
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
a
a
x x x
x x x
X x x
x
x
x
CLEAR
x x x
x
PRESET
a
CLEAR
L
SET
a
aOLO
L
L
PRESET
a
a
L
L
a
x
a
L
x
x
x
)(
x
X L
,X
L
L
L
x x x
x
TEST S-R FLIP-FLOP
C L L
C L L
eLL.
C L L
C L L
a
L
L
L
L
C :to a L
C L
C L
L
L
L
L
x
x
x
x
x
x
x
x
x
x
x x x
x x x
x xx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x. x
x x
x
x
x
X
x
x
x
x
x
x
x
x
x
x
x
L
H L a
L aL
L
a
L
L
a
x X a
L
a
a
RESET
a L a L
-----------------------------------------------~-------------------------------
Basic Clocked Flip·Flops
DESCRIPTION
THIS EXAMPLE ILLUSTRATES THE USE OF FUSIBLE LOGIC TO IMPLEMENT THE BASIC
FLIP-FLOPS: J-K FLIP-FLOP, T FLIP-FLOP, D FLIP-FLOP, AND S-R FLIP-FLOP.
NEXT STATE TABLE FOR THE BASIC FLIP-FLOPS:
Q= L
Q=H
1--------------------------------------
TYPE OF
FLIP-FLOP
INPUT 1 Q+ = L 1 Q+ = H 1 Q+ = L 1 Q+ = H 1
1-----------1-------1---------1---------1---------1---------1
J-K
J
I
L
I
H
1
X
X
K
X
X
I
H
L
1-----------1-------1---------1---------1---------1---------1
L
H
H 1 L 1
1 TIT
.1 -----------1-------1---------1---------1----.:..----1---------1
DID
1
L
1
H
L
H
1-----------1-------1---------1---------1---------1-------~-I
1 SET-RESET 1
S
L
I
H
1
L
X
1
1
R
X
L
H
L
NOTE THAT A PAL16L8 MAY BE SUBSTITUTED FOR THIS DESIGN. THEN THE CLOCK INPUT
(CLK) WOULD BE GATED WITH THE DATA INPUTS TO IMPLEMENT THE BASIC FLIP-FLOPS.
THE FUNCTION TABLE EXERCISES ALL INPUTS AND TESTS BASIC FUNCTION PERFORMANCE.
PALASM EXERCISES THE FUNCTION TABLE TO SIMULATE THE BASIC CLOCKED FLIP-FLOPS.
PAL16R8
~":'--_r---Q
R
I
IMPLEMENTATION OF THE S-R FLIP-FLOP AS A DIVIDE-BV-N COUNTER
4.12
Basic Clocked Flip-Flops
BASIC CLOCKED FLIP-FLOPS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
XXXXXXXXXXIZZZZZZZZI
CXXXOIXXXXOXXXXXXLHI
COOXOOXXXXOXXXXXXLHI
COIXOOXXXXOXXXXXXLHI
CIIXOOXXXXOXXXXXXHLI
CI0XOOXXXXOXXXXXXHLI
COOXOOXXXXOXXXXXXHLI
COIXOOXXXXOXXXXXXLHI
CXXXI0XXXXOXXXXXXHLI
CIIXOOXXXXOXXXXXXLHI
CI0XOOXXXXOXXXXXXHLI
CXXXOIXXXXOXXXXLHXXI
CXXOOOXXXXOXXXXLHXXI
CXXI00XXXXOXXXXHLXXI
CXXI00XXXXOXXXXLHXXI
CXXXI0XXXXOXXXXHLXXI
CXXXOIXXXXOXXLHXXXXI
CXXXOOOXXXOXXLHXXXXI
CXXXOOIXXXOXXHLXXXXI
CXXXOOOXXXOXXLHXXXXI
CXXXI0XXXXOXXHLXXXXI
CXXXOIXXXXOLHXXXXXXI
CXXXOOXOOXOLHXXXXXXI
CXXXOOXI0XOHLXXXXXXI
CXXXOOXOIXOLHXXXXXXI
CXXXOOXOIXOLHXXXXXXI
CXXXI0XXXXOHLXXXXXXI
CXXXOOXOOXOHLXXXXXXI
CXXXOOXI0XOHLXXXXXXI
PASS SIMULATION
4-13
Basic Clocked Flip-Flops
BASIC CLOCKED FLIP-FLOPS
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
° ---x
x-x- ---- ---- ---- -x-- ---- ---- ---- J*/JKT*/CLR
-x-- ---- ------- ---- ---- /K*JKT*/CLR
~x--
1
2 ---- ---- ---8
9
10
11
x--- ---- ---- ---- ----
-x-- x--- ---- -x-- ---- ---- ----xx- ---- ---- -x-- ---- ---- ------x x--- ---- -x-- ---- ---- ------- ---- ---- ---- x--- ---- ----
16 ---- ---- x-x17 ---- ---- -x-x
18 ---- ---- ---24
25
26
-------
-------------
PR
/J*K*/PR
/J*/JKT*/PR
K*JKT*/PR
CLR
---- -x-- ---- ---- ------- -x-- ---- ---- ---x--- ---- ---- ---- ----
T*/TT*/CLR
/T*TT*/CLR
PR
-xx- -x-- ---- ---- ---- ---x--x -x-- ---- ---- ---- ------- ---- x--- ---- ---- ----
/T*/TT*/PR
T*TT*/PR
CLR
32
33
---- ------- x---
-x-- x--- ---- ------- ---- ---- ----
D*/CLR
PR
40
41 ----
---- -x----- ----
---- -x-- ---- ---x--- ---- ---- ----
/D*/PR
CLR
48
49
50
---- ------- -------
56
57
58
---- ---- -x----- ---- -x----- ---- ----
LEGEND:
--~-
-x-- ---- x--- ----x-- ---- ---x -x-x--- ---- ---- ---- ------- ---- -x-- x------ ---- -xx- ---x--- ---- ---- ----
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
686
S*/CLR
/R*SRT* /CLR
PR
/S*R*/PR
/S*/SRT*/PR
CLR
- : FUSE BLOWN
(H,P,l)
Basic Clocked Flip-Flops
Logic Diagram PAL16R8
Basic Clocked Flip-Flops
ClK
1
0123
4567
891011
12131415
1611181920212223
24252621
28293031
0
I
1
J
./
4
,
6
J
1
..... >
~~~
"'"
,
....
t.!~
~
,
9
10
r--
"'"
II
11
IJ
14
D
15
.....
K 3'"
...
o~
~1
~
16
17
"
11
4
..
r;;-";;.---
'"
19
10
T
11
13
1£:
...
....
~~
14
"
""
30
"
Z6
5
...
...
.c"""I
"
"
j
16
17
6
..
.
D
j
J1
JJ
J4
ClR
r--
"'"
19
PR
16
J9
.....
01--
~1
=Dl
40
41
"
"'"
,43
44
./
41
o
,
...
40
47
....
.
....
"'-
II
11
.../
"
14
\I
.'"
1£:
...
"
17
\8
19
60
61
61
R
9
...
...
....
0123
4,567
II" 9101)
12131415
16111819
20212223
~
~
~
o
"
~
t1l
roo--
./
~
~
48
49
50
s8
~
01--
~
~1~
24252621_ ,··Zp930"Jl
4-15
Notes
4.16
Memory Mapped I/O
PAL16L2
vee
ABF
ABE
ABO
PORT1
ABe
ABA
Memory Mapped 1/0
Memory Mapped I/O
The logic equations for the memory mapped 1/0 logic are as
follows:
Functional Description
Memory mapped 1/0 interfaces 1/0 devices to a computer by
treating the device's physical address as a memory address.
This removes the requirement for. special 1/0 decoding and
enhances the flexibility of the 1/0 system. The PAL provides a
simple and direct method for implementing memory mapped 1/0
in mini aod lTIicro computer systems.
".
PORT 0= ABO·AB1·AB2·AB3· AB4·ABS· ABS· AB7·
AB8·AB9·ABA·ABB·ABC·ABD·ABE·ABF
PORT 1
= ABO·,AB1 • AB2· AB3· AB4· ABS' ABS· AB7·
, , AB8 ~AB9 • ABA· ABB • ABC· ABO· ABE· ABF
Circuit Operation
The circuits shown in Figure 1 are typical of those found in
memory mapped 1/0 applications. The inputs to the decode
logic are the system memory address lines, AO-AF. The logic
compares the address on the memory bus with the programmed
comparison addresS. When'im address on the bus matches, the
1/0 port enable signalis'set. This enable signal can then PEl
used in conjunction with other system contror~gnalsto trans- •
fer data to and from the system data bus. OtlYer',,!lxamples' in'
this applications section cover this I/O control decoding,in mote
detail.
PAL Design
The above example shows address decoding for memory
locations 1F78 hex and 1F7~ hex. Equation terms can be
chtlrlj18d t':t~ccommodateahY labit add~e!1$.'
t',';·
II1'operatfon;the PAL enable 9titPuts~iII go hii/h whepeverone, :,
ot., the programmed addresSes' m~tches the address, on the',
I!¥stem memory' address bus"Since, the PAL:, fully' decodes, the
addfess" any two I/O address m'ay be used?
Cgnclusion "
The PAL is used to monitor the system memory addreSs bus,
, Typical micro, _ - - - - - I
ABF
ABEC>-----------~
ABE
ABDc:>_---~
ABCc:>-----------------------~
ABD
ABC
ABBc;>----------------------~
ABB
ABAc:>---------~------------~
ABA
AB9
AB8
AB9c;>-----------------------~
AB8C)~---------------------~--~
PORT9
AB7 c:-----------I
AB8~~--------------~------~
AB5
AB4~---~--------------~
AB4
AB3c;>-~--------------------~
AB3
AB2
AB1
ABO
c:-----~
AB1c:>-----------~
ABO 0_--------1
MEMORY MAPPED
10
PORT1
AB7
ABe
AB5C)~-----------__4
AB2
,,~
MEMORY MAPPED
10
Memory Mapped I/O
PAL16L2
PAL DESIGN SPECIFICATION
BIRKNER/COLI 06/29/81
MMAP
MEMORY MAPPED I/O
MMI SUNNYVALE, CALIFORNIA
ABO ABI AB2 AB3 AB4 ABS AB6 AB7 AB8 GND
AB9 ABA ABB ABC /PORTI /PORTO ABD ABE ABF vec
PORTO
PORTI
~
*
=
*
/ABO*/ABl*/AB2* AB3* AB4* ABS* AB6*/AB7
AB8* AB9* ABA *ABB* ABC*/ABD*/ABE*/ABF
: SELECT PORTO
(lF78)
ABO*/ABl*/AB2* AB3* AB4* ABS* AB6*/AB7
AB8* AB9* ABA'll ABB* ABC*/ABD*/ABE*/ABF
:SELECT PORTI
(lF79)
FUNCTION TABLE
ABF ABE ABD ABC ABB ABA AB9 AB8 AB7 AB6 ABS· AB4 AB3 AB2 ABl ABO /PORTO /PORTI
:---INPUTS AB---:FEDCBA9876S43210
LLLLHHHHLHHHHLLL
LLLHHHHLLHHHHLLL
LLLHHHHHHHHHHLLL
LLLHHHHHLHHHLLLL
LLLHHHHHLHHHHLLL
LLLHHHHHLHHHHLLH
LLLHHHHHLHHHHLHL
LLLHHHHijHHHHHLLH
LLLHHHHLLHHHHLLH
LLHRHHIJHLHHHHLLH
LLLLLLLLLLLLLLLL
HHHHHHIJIJHHHHHHHH
LHLHLHLHLHLHLHLH
HLHLHLHLHLHLHLHL
LLHHLLHHLLHHLLHH
HHLLHHLLHHLLHHLL
---OUTPUTS--/PORTO /PORTI
H
H
H
H
L
H
H
H
IJ
H
H
H
H
H
He
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
COMMENTS
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TES'l'
TEST
TEST
TEST
TEST
TEST
OF78
lE78
IFF8
IF70
IF78
IF79
IF7A
IFF9
lE79
3F79
ALL L'S
ALL H'S
ODD CHECKERBOARD
EVEN CHECKERBOARP
ODD OOUBLE CHECKERBOARD
EVEN OOUBLE CHECKERBOARD
D
DESCRIPTION
THIS PAL PROVIDES A SINGLE CHIP DECODER FOR USE IN MEMORY MAPPED I/O
OPERATIONS. EQUATION TERMS CAN BE CHANGED TO ACCOMQDATE ANY 16-BIT
ADDRESS.
THE PAL WILL MONITOR THE SYSTEM MEMORY ADDRESS BUS AND DECODE THE
SPECIFIED MEMORY ADDRESS WORD (lF78,lF79) TO PRODUCE A PORT ENABLE
PIN FOR POWro AND PORTl.
4-1.9
Memory Mapped 110
MEMORY MAPPED I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
000111101X1110BH0001
000111100X1111BH0001
000111111X1111BH0001
000011101X1111BH0001
00011110lX1111HL0001
100111101X1111LH0001
010111101X1111BH0001
100111111X1111BH0001
100111100X1111BH0001
100111101X1111BH1001
OOOOOOOOOXOOOOBH0001
111111111XII1IBHll11
lOlOl0101XOI0IBHOI01
010101010XI0I0BHI011
110011001XI00IBHI001
00l100110XOII0BHOlll
PASS SIMULATION
MEMORY MAPPED I/O
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
24
-x-x -x-x x--x x--x x-x- x-x- -xx- x-x-
32
-xx- -x-x x--x x--x x-x- x-x- -xx-
LEGEND:
x:
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN
A __ ~n
32
/AeO*/ABl*/AB2*AB3*AB4*AB5*AB6-
X-X- ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*-
FUSE BLOWN
(H,P,l)
Memory Mapped I/O
Memory Mapped I/O
ABO
AB1
AB2
AB3
1
2
3
4
.
...
012
3
Logic Diagram PAL16L2
4 S 57
891011
12131415
16171819
20212223
24252621
28293031
~
I
..
.
~
~
I
...
19
....
...
(
.,.,
26
BlK1
~
22
BlK
~
4
"
"
CB6
23
16
G
15
R
14
EN1
9
-
..
.."
I-< •
"
.....
"
"
-
.J.
....
10
~.J.
W\{L~
"
"
""
H2 !!.-...,
13
.....
II
I
1
J
4
5
6
J
•
9 U'1I
12 131415
1& 11 I I "
UtI tz 23
24 lSi6 27
i.
U JI]I
12 II ~ U
.:11 311119
H4
Notes
4·36
Binary to BCD Converter
PAU6R8
Binary to BCD Converter
Serial Binary to Parallel BCD Conversion
The purpose of this circuit is to convert a serial stream of binary
data into a parallel BCD representation as depicted by Figure 1.
+
H~..............,H.'~ ;~~ :I
'-r-L -;L1"""'TI'~' Wl Wl
TT
,,'-,
BCD1000
03
I
MSB FIRST
BCD100
BCD10
I
COMBINATIONAL
NETWORK
COUT
OJ
02
I
Do
EDGE·TRIGGERED
REGISTER
Q3
Q2
OJ Qo
I
CLOCK
I
..
BCDO
Figure 1. Conceptual Diagram of Binary to BCD Converter
Figure 3, BCD Converter Building Block.
Couleur's Technique (BIDEC)
b) BCD (present state): = 5 - 9
then BCD (next state): = 10 - 18 which are not representable in one BCD digit, and a carry out· is generated.
e.g. If BCD (present state): = 6
then BCD (next state): = 2 and COUT = 1
In this conversion technique (Ref. 1), the input binary data is
shifted left (starting with the MSB) into the BCD register. The
beauty of this method is that after each clock pulse, the BCD
output contains correct BCD representation for the "relative"
binary data shifted so far. We illustrate the last statement in
Figure 2.
c) If CIN = 1 then it is simply shifted into the LSB of the BCD
digit (the old LSB was shifted left leaving a zero in its
original position).
Thus, regardless of the BCD (present state) value, the
following is true:
Logic Design
The overall conversion problem can be segmented into four-bit
binary blocks. Each block represents one BCD digit and is
expandable by CIN and COUTo The BCD building blOCk, is
shown in Figure 3 as a state machine.
BO (next state): = CIN
Truth Table
The preceding discussion is summarized by Tables 1 and 2.
The combinational network can be designed frol:T1 a "next-state"
truth table. The truth table can be constructed by observing that
a left shift is a multiplication by 2, and a carryin adds 1 to
the LSB.
PRESENT
STATE
B3·BO
0..
5·9
10·15
In equation form:
BCD (next state): = 2* BCD (present state)
Of course, if it were binary it will be simply,
+ CIN
NEXT
STATE
n
COUT
B3·BO
0
0-8
1
0-8
DON'TCARE DON'T CARE
0
1
2
3
4
5
6
7
8
9
10·15
Table 1, General Truth Table.
However, BCD requires some corrections as will be shown
shortly. For simplicity we analyze the three relevent cases:
CONVERSION REGISTER
10'
1
I
,
64
32
16
10'
1
I
1
128
8
4
2
1
1
I
1
0
1
1
1
0
4
1
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
64
32
16
8
4
2
1
32
16
8
4
2
16
8
4
8
4
2
4
2
1
2
1
1
2
1
1
0
0
0
1
0
0
1
COUT
B3 B2 B,
So
B3 B2 B, BO
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
X
0
0
1
1
0
0
0
1
1
0
X
o
1
o
1
o
o
1
o
1
CIN
CIN
CIN
CIN
CIN
CIN
CIN
CIN
CIN
o CIN
0
0
0
0
1
1
1
1
1
X
X
X
~
RELATIVE WEIGHT BeFORE LAST SHIFT
.... RELATIVE WEIGHT BEFORE 7TH SHIFT
_
RELATIVE WEIGHT BEFORE 6TH SHIFT
.... RELATIVE WEIGHT BEFORE 5TH SHIFT
_
RELATIVE WEIGHT BEFORE 4TH SHIFT
...... RELATIVE WEIGHT BEFORE 3RD SHIFT
..... RELATIVE WEIGHT BEFORE 2ND SHIFT
..... RELATIVE WEIGHT BEFORE 1ST SHIFT
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
4
Figure 2: Tabular Representation of the Conversion Cycle.
4·38
NEXT
STATE
Table 2: Detailed Truth Table.
a) BCD (prese nt state): = 0 - 4
then BCD (next state): = 0 - 8 which are representable
in BCD form at
10'
PRESENT
STATE
0
....... BINARY INPUT
.... 1 SHIFTED IN
_
2 SHIFTED IN
..... 4 SHIFTED IN
..... 9 SHIFTED IN
...... 18 SHIFTED IN
..... 36 SHIFTED IN
_72 SHIFTED IN
' _144 SHIFTED IN
Binary to BCD Converter
B1
B3 80
B2"+-=-t-=-±:-:-t--=-=~
1
B3 BO
B2
00
vcc
ClR
CIN
ClK
00
B01
-I
BCD
B02
0
B11
BCD
B12
"'I
10
B03
B1:~ ii3. B2' BO+ B3' 80+ B2. B1' BO
B2:~ B1' BO+ B2' B1 + B3' BO
10
B13
o
o
-=
x
x
B3:
~
B2' B1 • BO+ B3' BO
COUTo = B3+ B2' BO+ B2' B1
Figure 4. Karnaugh Maps
I~ DI
PAL Implementation
100
The PAL16R8 implements two BCD digits. One of the pins is
assigned to the clear (CLR) function. The BCD conversion
register must be initialized to zero before shifting of the binary
input data is started. The eight output registers are assigned to
the two BCD digits.
l~'
1000
At this pOint, it seems that we are short of one output pin for the
COUT in expanding to more BCD digits. However, the basic
equations indicate that COUT is a function of the four preceding
BCD bits. Therefore, by inputting these four bits to the next
stage, the COUT is derived internally by the latter stage. A
similar trick is used in each chip to cascade internally.
-=
-=
Figure 5. Logic Schematic
This expansion solution implies that in the least significant BCD
stage the equation is:
(1) BO:
=
Summary
CIN
whereas in later stages the equation is:
where the C terms are driven by the corresponding B terms of a
preceding stage. However, in order to have a universal solution,
we OR the two equations. If the PAL is used as the least
significant stage C1O, Cn, C12 and C13 are grounded and
equation (1) holds. If the PAL is used as an intermediate stage,
CIN is grounded and equation (2) holds.
A similar algorithm was described in Ref. 2, where the two BCD
digits were implemented with four ICs and could be clocked at
80 ns. Here we described one chip implementation that can be
clocked at 60 ns.
References
1. "Binary to BCD Conversion Techniques" by B. MacDonald, EON Dec. 1, 1969.
2. "Special PROM Mode Effects Binary to BCD Converte"", by D.M. Brockman, ElectroniCS.
4·39
Binary to BCD Converter
PAL16R8
BBCD
BINARY TO BCD CONVERTER
MMI SUNNYVALE, CALIFORNIA
CLK /CLR CIN /C10 /C11 /C12 /C13 NC NC GND
/OC /B13 /B12 /B11 /B10 /B03 /B02 /B01 /BOO VCC
BOO :=
+
+
+
/CLR*
/CLR*
/CLR*
/CLR*
CIN
C13
C12* C10
C12* C11
PAL DESIGN SPECIFICATION
S. WASER/V. COLI 09/14/81
,CONVERT BOO (LSB)
B01 := /CLR*/B03*/B02* BOO
+ /CLR* B03*/BOO
+ /CLR* B02* B01*/BOO
,CONVERT B01
B02 := /CLR* B01* BOO
+ /CLR*/B02* B01
+ /CLR* B03*/BOO
,CONVERT B02
B03 := /CLR* B02*/B01*/B00
+ /CLR* B03* BOO
,CONVERT B03
B10 := /CLR* B03
+ /CLR* B02* BOO
+ /CLR* B02* B01
,CONVERT B10
B11 := /CLR*/B13*/B12* B10
+ /CLR* B13*/B10
+ /CLR* B12* B11*/B10
,CONVERT B11
B12 : = /CLR* B11 * B10
+ /CLR*/B12* B11
+ /CLR* B13 */B10
,CONVERT B12
B13 := /CLR* B12*/B11*/B10
+ /CLR* B13* B10
,CONVERT B13 (MSB)
4·40
Binary to BCD Converter
FUNCTION TABLE
CIN C13 C12 Cll C10
ICLR
; INPUTS
-OUTPUTS-
; CARRY
CONTROL
I
CLK
loe
B13 B12 Bll B10 B03 B02 BOl BOO
(BCD)
;C CCCC
;I 1111
;N 3210
C C I
L L 0
R KC
BBBB BBBB
1111 0000
3210 3210
COMMENTS
x xxxx
L C L
HCL
HCL
HCL
HCL
L C L
HC L
HC L
HC L
HCL
HC L
HCL
HCL
L C L
HCL
HCL
BC L
HC L
HC L
HCL
HC L
L CL
HCL
HC L
BCL
HCL
HC L
HCL
L CL
HCL
HC L
HC L
HCL
HCL
HC L
L C L
HC L
HC L
HC L
HC L
HC L
HC L
HCL
xXH
LLLL
LLLL
LLLL
LLLL
LLLH
LLLL
LLLL
LLLL
LLLL
LLLL
LLLH
LLHH
LHHL
LLLL
LLLL
LLLL
LLLL
LLLH
LLHL
LHLL
HLLH
LLLL
LLLL
LLLL
LLLL
LLLH
LLHL
LHLH
LLLL
LLLL
LLLL
LLLL
LLLH
LLHH
LHHL
LLLL
LLLL
LLLL
LLLL
LLLH
LLHL
LHLL
HLLL
ZZZZ
CLEAR (0)
SERIAL INPUT A H (1)
SERIAL INPUT A H (3)
SERIAL INPUT A L (6)
SERIAL INPUT A H (13)
CLEAR (0)
SERIAL INPUT A H (1)
SERIAL INPUT A L (2)
SERIAL INPUT A L (4)
SERIAL INPUT A L (8)
SERIAL INPUT A H (17)
SERIAL INPUT A L (34)
SERIAL INPUT A L (68)
CLEAR (0)
SERIAL INPUT A H (1)
SERIAL INPUT A L (2)
SERIAL INPUT A H (5)
SERIAL INPUT A H (11)
SERIAL INPUT A L (22)
SERIAL INPUT A H (45)
SERIAL INPUT A L (90)
CLEAR REGISTERS TO TEST
SERIAL INPUT A L (178)
SERIAL INPUT A L (360)
SERIAL INPUT A L (720)
SERIAL INPUT A L (1440)
SERIAL INPUT A L (2880)
SERIAL INPUT A L (5760)
CLEAR (0)
SERIAL INPUT A H (1)
SERIAL INPUT A B (3)
SERIAL INPUT A H (7)
SERIAL INPUT A H (15)
SERIAL INPUT A H (31)
SERIAL INPUT A H (63)
CLEAR REGISTERS TO TEST
SERIAL INPUT A H (127)
SERIAL INPUT A H (255)
SERIAL INPUT A H (511)
SERIAL INPUT A H (1023)
SERIAL INPUT A H (2047)
SERIAL INPUT A B (4097)
SERIAL INPUT A B (8196)
TEST HI-Z
------------------------------------------------------------------------------H LLLL
H LLLL
L LLLL
H LLLL
x xxxx
H LLLL
L LLLL
L LLLL
L LLLL
H LLLL
L LLLL
L LLLL
X
xxxx
H LLLL
L LLLL
H LLLL
H LLLL
L LLLL
H LLLL
L LLLL
X
xxxx
L HLLH
LLHHH
L LHHL
L LLHL
L LHLL
L HLLL
x xxxx
H
H
H
H
H
H
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
x xxxx
LLHHL
L LLHL
L LHLH
L LLLH
L LLHL
L LHLL
L HLLH
x xxxx
LLLL
LLLH
LLHH
LHHL
LLHH
LLLL
LLLH
LLHL
LHLL
HLLL
LHHH
LHLL
HLLL
LLLL
LLLH
LLHL
LHLH
LLLH
LLHL
LHLH
LLLL
LLLL
L~H
LLHH
LHHH
LHLL
HLLL
LHHH
LLLL
LLLH
LLHH
LHHH
LHLH
LLLH
LLHH
LLLL
LLLH
LLHL
LHLH
LLLL
LLLL
LLLL
LLLH
ZZZZ
D
CASCADABILITY
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
1000)
1000)
1000)
1000)
1000)
1000)
CASCADABILITY
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
(TEST BCD 100,
1000)
1000)
1000)
1000)
1000)
1000)
1000)
------------------------------------------------------------------------------4·41
Binary. to BCD Converter
DESCRIPTION
THE FUNCTION OF
INTO A PARALLEL
OUTPUT CONTAINS
DATA SHIFTED SO
THIS PAL IS TO CONVERT A SERIAL STREAM OF BINARY DATA
BCD REPRESENTATION. AFTER EACH CLOCK PULSE, THE BCD
THE CORRECT BCD REPRESENTATION FOR THE RELATIVE BINARY
FAR.
THE INPUT BINARy DATA IS SHIFTED LEFT (STARTING WITH THE MSB) INTO THE
BCD REGISTER. THIS TECHNIQUE IS KNOWN AS COULEUR I S TECHNIQUE (BIDEC).
THE COMBITORIAL NETWORK IS DESIGNED FROM THE FOLLOWING NEXT-STATE TABLE:
PRESENT
STATE
B3-BO
NEXT
STATE
B3-BO
5-9
10-15
0-8
X
COUT
1-----------------------------1
0-4
0-8
0
4·42
1
X
Binary to BCD Converter
BINARY TO BCD CONVERTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CO XxXXXXXXOHHHHHHHH1
C111111XXXOHBHHHHHL1
C111111XXXOHBHHHBLL1
C101111XXXOHBHHHLLHl
C111111XXXOHHBLHHLL1
COXXXXXXXXOHBHHHHHHl
C111111XXXOHHBHHHBL1
C101111XXXOBBHHHHLHl
C101111XXXOHHBHHLHHl
C101111XXXOHHHHLHHHl
C111111XXXOHBHLHLLL1
C101111XXXOHHLLHLHHl
C101111XXXOHLLHLHHHl
COXXXXXXXXOHHHHHHHHl
C111111XXXOHBHHHHHL1
C101111XXXOHBHHHBLHl
C1111I1XXXOHBHHHLHL1
C111111XXXOHBHLHHBL1
C101111XXXOHHLHHBLHl
C111111XXXOHLHHHLHL1
C101111XXXOLBHLHHHHl
COXXXXXXXXOHBHHHHHHl
C1OO11OXXXOBBHHHHBLl
C1OOOO1XXXOHHHHHHLL1
C101OO1XXXOHBHHHLLL1
C101011XXXOHHBLHLHHl
ClO1101XXXOHHLHLHHHl
C10111OXXXOHLHLHLLL1
COXXXXXXXXOHBHHHHHHl
C11 111 1 XXXO HHHHHHHL1
C111111XXXOHBHHHBLL1
C111111XXXOHBHHHLLL1
C111111XXXOHBHLHLHL1
C111111XXXOHHLLHHBL1
C111111XXXOHLLHHBLL1
COXXXXXXXXOHBHHHHHHl
C101OO1XXXOHHHHHHHL1
C101011XXXOHHHHHHLHl
C100101XXXOHBHHHLHL1
C100111XXXOHBHLHHHHl
C101011XXXOHHLHHHHH1
C101101XXXOHLHHBHHH1
C100110XXXOLHHHHHBL1
XXXXXXXXXXlZZZZZZZZ1
PASS SIMULATION
4·43
Binary to BCD Converter
BINARY TO BCD CONVERTER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o x--- x--x--- ---x------x-- ----
1
2
3
---- -~-- ---- ------- ---- ---- -x--x-- ---- -x- --,..--- -x-- -x-- ----
------------
-------------
/CLR*CIN
/CLR*C13
/CLR*C12*C10
/CLR*C12*Cll
8
9
10
x--x --- --x- ~-X- --~- ---- ---- ---- /CLR*/B03*/B02*BOO
x-x- ---- ---- ---x --- ---- ---- ---- jCLR*B03* /BOO
x-x- --x---x ---~ ---- ---- ---- ---- /CLR*B02*B01*/B00
16
17
18
x--x ---x - - ---- ---- ---- ---- ---x--- ---x --x- ~-- ---- ---- ---- ---x-x- ---- ---- ---x ---- ---- ---- ----
/CLR*B01*BOO
/CLR*/B02*B01
/CLR*B03*/B00
24
25
x-x- --x- ---x ---- ~--- ---- ---- ---x--x ---- ---- --x ---- ---- ---- ----
/CLR*B02*/B01*/B00
/CLR*B03*BOO
32
33
34
x- --- ---- ---x --- ---- --- ---x--x ---- ---x ---- ---- ---- ---- ----
x--- ---x ---x ---- ---- ---- ---- ----
/CLR*B03
/CLR*B02*BOO
/CLR*B02*B01
40
41
42
x--- ---- ---- ---- ---x ---- --x- --xx--- --;..- ---- ---- --.X- ---- ---- ---x
x--- ---- ---- --- --x- ---x ---x ----
/CLR*/B13*/B12*B10
/CLR*B13* /B10
/CLR*B12*B11*/B10
48
49
50
x--x--x--x-x---
/CLR*B11*B10
/CLR*/B12*B11
/CLR*B13*/B10
56
57
LEGEND:
----------------
----------------
----------------
---x
-----x--x---x
-----x------x
----
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
4·44
---x
---x
----x----
664
---------x
------x
/CLR*B12*/B11*/B10
/CLR*B13*B10
- : FUSE BLOWN
(H,P,l)
Binary to BCD Converter
Binary to BCD Converter
CLK
Logic Diagram PAL16R8
1
0123
4567
B 91011
12131415
1617181920212223
24252627
28293031
0
1
1
2
.
./
•
)
.....
~
10
J
...
"'"
11
11
13
14
15
j
A
Jt
16
17
18
4
....
~1
D
./
11
21
13
A
~
~
-
'"
19
10
C10
Q~
~~
14
r--
"'"
17
....
D
/
18
29
30
31
.c:
...
,
14
l5
36
39
A
...
....
,
40
41
41
.
Jt
43
44
45
46
4)
A
....
..
"
50
"'"
51
j
51
53
NC
8
...Jt
"
55
.....
"".....
..
57
.......
58
59
60
63
NC
~l
~
=Dl
~
U1
~
U1
:Ul~
~
D
./
61
61
9
Q '--
~
j
37
38
)
~
'"'"
31
33
6
~
110.
15
26
5
800
""
,•
CIN
~~~
""
3
4
5
Q
Q
...
C
0\2]
4561
891011
12131415
16111819
20212223
24252627
.....
......
810
813
..
2829JOJI
4·45
Noles
4-46
Deglitcher
PAL16R4
VCC
A
ZD
ZS
X
NC
D
BS
ES
GND
4';47
Deglitcher
PAL16R4
PAL DESIGN SPECIFICATION
DEGL
VINCENT LECLERC 03/03/81
DEGLITCHER
MMI FRANCE
CLK Z PRS CLR NC NC NC NC NC GND /oe ES BS NC Y X ZS ZD A VCC
/ZS := /PRS*/Z
+ CLR
/X
/Y
/PRS*/X*/Y
+ /PRS* /X ,. • /ZS
+ /pRS*
/Y*/ZS
+ CLR
:=
1CLEAR
:= /PRS*/ZS
+ CLR
IF (VCC) /BS =
:B~INNING OF SIGNAL
X + /Y +./ZS
IF (VCC) /ES = /X + Y +ZS
1END OF SIGNAL,
= /PRS*ZD*/BS*/ES
IF (VCC) /A
+/PRS*ZD
*/A
+ /pM .. * BS
*/A
* ES*/A
+ /PRS
+ 'CLR
.
IF (VCC) /ZD =
+
+
+
+
/PRS*/A* BS
/PRS*/A*ES
/pRS*/A*/ZD
/PRS*/BS*/ES*/ZD
CLR
1CL~
1Z DETECTED.
1CLEAR
FUNCTION TABLE
CLK /oe Z PRS CLR X Y ZS BS ES ZD A
1COMMENTS
--------------------------------------------------------C
C
C
C
C
C
C
C
C
C
X
L X L
L
L
L
L
H
L
L H
L H
L L
L L
L L
L X
H X
L
L
L
L
t
L
L
L
H
X
H L L L
L L, L
L L L H
L L H L
L L L H
L L H H
L H H L
L HL L
L L L L
L HH H
X Z Z Z
L
L L
L L
L L
L L
L L
H L
L L
L H
L L
L L
X X
L L
H
L H
L H
L H
HH
HL
HH
L H
HH
XX
L
CLEAR
INITIAL STATE SOO
INPUT Z·
STATE SOO TO SOl
STATE SOl TO SOO
STATE 500 TO SOl
STATE SOl TO Sll
STATE Sll TO S10
STATE S10 TO SOO
PRESET TEST
ENABLE TEST
--------------------------------------------------------DESCRIPTION
THE SYSTEM DETECTS THE BEGINNING AND THE END OF A SIGNAL WHICH IS
DISTURBED BY GLITCHES.
4·48
Deglitcher
DOOLITCBER
1
2
3
4
5
6
7
8
9
10
11
CXOIXXXXXXOLLXLLLLLI
COOOXXXXXXOLLXLLLLHI
CI00XXXXXXOLLXLLHLHI
COOOXXXXXXOLLXHLLLHI
CI00XXXXXXOLLXLLHLHI
CIOOXXXXXXOLHXHLHHHI
COOOXXXXXXOLLXHHLHLI
COOOXXXXXXOHLXLHLHHI
COOOXXXXXXOLLXLLLLHI
CXI0XXXXXXOLLXHHHHHI
XXXXXXXXXXIXXXZZZXXI
PASS SIMULATION
4·49
Deglltcher
DEGLI'l'CHER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o ---- ---- ---- ---- ---- ---- ---- ---xx- ---- ---- -------- ---x ---x
/pRS*ZD*/BS*/ES
2 ---1 -XX- ---- --- --- - - ---- ---- /PRS*ZD*/A
3 ---x -x-- ---- --- ---- ---- --x- ---- /PRS*BS*/A
4 ---x -x----- ---- ---- ---- --x- /PRS*ES*/A
5
x--- ---- --- ---- ---- ---- CLR
1 ----
8
---- ---- ---- ---- ---- --9 ---x -x---- --- ---- --x- ---- /PRS*/A*BS
10 --1 -X-- ---- ---- --- ---- ---- --X- /PRS*/A*ES
11 ---1 -X-X --- ---- ---- ---- ---- ---- /PRS*/A*/ZD
12
-x-x ---- ---- ---- ---- ---x ---x /PRS*/BS*/ES*/ZD
13
---- x--- ---- ---- ---- ---- ---- CLR
16
17
-x-- -x- ---- ---- --- ---- --- ---x-- ---- ---- ---- ---- ~---
24
25
26
27 - 32
33
48
49
50
51 --56
57
58
59
LEGEND:
-x-- ---- ---x --x ---- ---- ----x-- ---x --x .-- --- ---'- ----
-x- ---x ---- ---x - - ---- ----
/PRS*/X*/Y
/PRS*/X*/ZS
/PRS* /Y* /ZS
---- x--- ---- ---- ---- --- ----CLR
-x-- ---x - - ---- ---- ---- ---- /pRS*/ZS
---- x--- ---- ---- ---- ---- ---- CLR
-------- --x- ---- ---- ---- ------ ---- ---- ---x ---- ---- ----
X
/Y
---X ---- ---- ---- ---- ---- /ZS
---- ---- ---x --- --~- ---- ------- ---- ---- --X---- ------- --x- --- -~-- ---- ---- ---x:
FUSE
NOT
NUMBER OF FUSES BLOWN
4-50.
/PRS*/Z
CLR
BLOWN (L,N,O)
=
846
/X
y
ZS
- : FUSE BLOWN
(H,P ,1)
Deglitcher
Logic Diagram PAL16R4
Deglitcher
CLK
1
,
012 1
4567
891011
12131415
1611181920212223
24252627
2829JOJI
:>-J
1
1
J
4
Z 3
5
6
7
....
:>-J
11
14
15
....' I - - 16
17
~~
18
19
4
.....
11
21
2J
....
,
16
17
....
"
....
11
3J
"
"
35
J6
37
38
39
NC
6
~l
~x
I
18
19
3D
,
zs
~
14
25
Nt
DO-
./
"
CLR
ZD
....
11
13
...
18
....
8
J
A
c:'~
~
,
"
PRS
19
I
....
....
...
....
~
~
U]
y
40
41
42
'"
.."
,44
../
47
NC
7
....
~
....
...
..
rJ
"
""
51
54
NC
8
...
lJ
NC
as
55
....
1Il."1---
....
"57.
>=J
51
..
~
~
""
""
"
....
NC 9 ...
.....
~
012 J
45& 7
891011
121314-15
f6111819
20212223
1~Z52621
2BZ9JO]1
"
ES
~ OC
4-51
Notes
4-52
Electronic Dice Game
PAL16R8
4-.53
Electronic Dice Game
Looking at the Karnaugh Maps (Figure 3), it may be noticed that
the simplest logic equations were not generated. This was to
insure a path to a valid state from all invalid states.
Logic Design Using Standard TTL
In one die, seven LEOs make up the display (Figure 1). Notice
they can be connected such that only four lines are required to
drive them. The LEOs are turned on when the appropriate line is
driven low. Since there are four lines to be driven it is necessary
to use four Ootype flip-flops for each die. For reference the outputs of the flip-flops are labeled 01-04 and the inputs are
labeled 01-04 (Figure 2). By using the inverting output of the
Flip-Flop we catl,JJse positive logic in the design: That is, a
logical "1"'at 0 o.utput represents 'an LED being turned on.
CLOCK
01
a
1----01
51
02
VCC
Q2
03
Os
0
Q
ClK
Q
D
Q
Cl,K
Q
0
Q
ClK
Q
Q2
'3
04
D4
Q4
Figure 1
Figure 2
The present state of table 1 shows the preferred sequence in
which the LEOs should turn on. The next state shows the conditions necessary to increment when clocked. From these two
tables the Karnaugh Maps of Figure 3 were made. Using the
Karnaugh Maps the following equations are obtained;
These equations satisfy the requirements for one die. By substituting 05.oa for 01-04 and 05-0a for 01-04 we have the
following equations;
Oa= 0507+ 050a
.
..."
,
STATE
~
03
~
~
°4
°3
°2
°1
1
0
1
0
0
0
0
1
0
2
0
0
1
0
1
1
0
0
3
1
1
0
0
1
0
1
0
4
1
0
1
0
1
1
1
0
5
1
1
1
0
1
0
1
1
6
1
0
1
1
0
1
0
0
.
Table 1
4-54
.
NEXT STATE
PRESENT STATE
,-
Electronic Dice Game
~
01 KARNAUGH MAP
02 KARNAUGH MAP
04
00
01
11
10
01
-03 02
04
00
09
x
0
x
x
00
X
01
X
0
0
X
01
11
0
~
X
X
11
10
0
X
X
10
-'
0
01
~
03 KARNAUGH MAP
04 KARNAUGH MAP
03 02
04
00
01
11
10
11
10
X
00
Vx
1
X
"?--
x
x
X
01\
IZ
1
1
~
X
X
11
0
0
X
X
x
x
X
X
10
0
X
X
X
x
x
11
10
X
Note: X means Don't Care
/
D
x
Figure 3
Vee
+5V
ROLL
~W
--;=0
>-~iT
J
>-
~
~W
===r:>
J
-r
---LJ
~.
>-
~H1~
2K
~I
2N4402
~1~
20K
20K
2K
-:
02
F> 03
'--
,
[)(
'--
12011
r;;-;;;W
,
~
-'-.,....
-14-
rW.
~011
I'"
L
I
r;-;;:W
INv
29011
I'
~
IA
I~
F> 0 4
'--
~J
P
>--- F> 05 r----
"--
~J
~
~
--I> 06
12011
r;;;;J
Ln
~
~
O?
'--
.~~
.-
'--
IA
I.'"
I
12011
f\r-<
29011
IA
~W
1
Y4- ~
I'"
IA
I'"
IA
12011
~
08
"--
Figure 4
4·55
Electronic Dice Game
However, since this is a synchronous design the clocks of the
two die are common. If tlie same equations are used for both die
there will be only six different states. To 'get around this the first
die is allowed to go through each of the six states incrementing
with each clock. The second die. is inhibited from incrementing
except when the first die goes from the 6th state to the 1st state.
At this time the second die is allowed to increment one time.
Looking at the present state of table 1 it is noticed that
whenever output 01 is high, the next clock should increment the
second die. Whenever 01 is low the second die should remain
the same. From this we now write all the equations.
Applications
Rules for CRAPS
The following is a set of rules that apply whether you are playing
in Las Vegas with dice or at home with a PAL.
.
The first roll is called the come-out and you win on a 7 or 11 or
you "crap-Qut" on a 2 (snake eyes), 3 (ace caught a deuce) or 12
(box cars). If none of the above happens you will have rolled a
number between 4 and 10. Mark this number well, you will need
to roll it again to win. At this point no "crap" can hurt you, but
unless you've programmed your PAL right, a seven can. Normal
probabilities in 36 throws:
°1=01 0 2 0 3
°2=01 0 3+ 0 1 0 4
03 = 03
04 = 01 02 + 01 04
05 = 01 05 + 01
06 =
Q.j
Os 06 07
°7=01 0 7+ 0 107
Os +
6 times
6
8
5
5
5
4
4
3
3
2
2
9
4
10
06 + 01 05 07 + 01 05 08
08 =01 08 + '01 05
7 will appear
3
01 05 08
11
From these equations the logic diagram can be drawn.
(Figure 4)
2
12
Logic Design Using PALs
The design requires 8 registered outputs. Looking at the PAL
Oata Sheet we determine that a PAL16R8 best suits this
application. The equations developed above can be used here
without change. The PAL Design Specification shows the
implementation of these equations. Note that the pinout is
chosen to convenience PC board layout which is shown below.
vee
ROLL
..J...
4·56
+5V
()
Q
0
Q
Electronic Dice Game
PAL 16R8
EDG
ELECTRONIC DICE GAME
MMI SUNYVALE, CALIFORNIA
CK INIT NC NC NC NC NC NC NC GND
/OC /Q5 /Q8 /Q7 /Q6 /Q1 /Q4 /Q3 /Q2 VCC
Q1:=
+
/Q1* Q2* Q3
INIT
Q2 :=
/Q1* Q3*/INIT
/Q1* Q4*/INIT
+
Q3 :=
/Q3*/INIT
Q4:=
/Q1* Q2*/INIT
/Q1* Q4*/INIT
+
PAL DESIGN SPECIFICATION
VETTER/COLI 07/06/81
Q5 := Q1*/Q5* Q6* Q7*/INIT
+ /Q1* Q5*/INIT
Q6 :=
Q1*/Q5* Q7*/INIT
Q1*/Q5* Q8*/INIT
+ /Q1* Q6*/INIT
+
Q7:= Q1*/Q7*/INIT
+ /Q1* Q7*/INiT
Q8:=
Q1*/Q5* Q6*/INIT
Q1*/Q5* Q8*/INIT
+ /Q1* Q8*/INIT
+
4-57
ElectroniC Dice Game
FUNCTION TABLE
CK
/oe INIT
1-CONTOOLS1C /
1K oe INIT
/Q1 /Q2 /Q3 /Q4 /Q5 /Q6 /Q7 /Q8
/OUTPUTS
QQQQQQQQ
12345678
COMMENTS
NUMBER DISPLAYED
DIE 2 DIE 1
----------------------------------------------C
C
C
C
C
C
C
L
L
L
L
L
L
L
H
L
L
L
L
L
L
LHHHHHHH
HHLHHHLH
HLHHHHLH
HHLLHHLH
HLHLHHLH
HLLLHHLH
LLHLHHLH
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
C
C
C
C
C
C
L
L
L
L
L
L
C
C
C
C
C
C
INITIALIZE COUNTER
1
2
3
4
5
6
1
1
1
1
1
1
HHLHHLHH
HLHHHLHH
HHLLHLHH
HLHLHLHH
HLLLHLHH
LLHLHLHH
1
2
3
4
5
6
2
2
2
2
2
2
L
L
L
L
L
L
HHLHHHLL
HLHHHHLL
HHLLHHLL
HLHLHHLL
HLLLHHLL
LLHLHHLL
1
2
3
4
5
6
3
3
3
3
3
3
L
L
L
L
L
L
L
L
L
L
L
L
HHLHHLHL
HLHHHLHL
HHLLHLHL
HLHLHLHL
HLLLHLHL
LLHLHLHL
1
2
3
4
5
6
4
4
4
4
4
4
C L
C L
C L
C L
C L
C L
L
L
L
L
L
L
HHLHHLLL
HLHHHLLL
HHLLHLLL
HLHLHLLL
HLLLHLLL
LLHLHLLL
1
2
3
4
5
6
5
5
5
5
5
5
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
HHLHLLHL
HLHHLLHL
HHLLLLHL
HLHLLLHL
HLLLLLHL
LLHLLLHL
1
2
3
4
5
6
6
6
6
6
6
6
C H
X
ZZZZZZZZ
TEST HI-Z
-----------------------------------------------
4·58
Electronic Dice Game
DESCRIPTION
THE DUAL MODULO-SIX COUNTER INCREMENTS ON THE RISING EDGE OF THE CLOCK (CK).
THE TliREE-STATE OUTPUTS ARE HIGH-Z WHEN THE OUTPUT CONTROL LINE (jOC) IS HIGH
AND ENABLED WHEN THE OUTPUT CONTROL LINE (jOC) IS LON.
THE "INIT" LINE IS NEEDED TO INITIALIZE THE COUNTER SO THAT THE FUNCTION TABLE
SIMULATION COULD BE PERFORMED AND THE PART COULD BE TESTED AT THE TIME OF FABRICATION. THIS LINE AS WELL AS ALL OTHER UNUSED INPUTS SHOULD BE TIED TOGND.
THERE ARE 36 DIFFERENT STATES TO THE COUNT SEQUENCE. EACH STATE CORRESPONDS
TO ONE OF THE NUMBER COMBINATIONS TO BE DISPLAYED ON THE DICE.
NOTE THAT THE PINOUT IS CHOSEN TO CONVENIENCE PC BOARD LAYOUT.
ELECTRONIC DICE GAME
1 CIXXXXXXXXOHHHHLHHHI
2 COXXXXXXXXOHHLHHHLHI
3 COXXXXXXXXOHHLHHHHLI
4 COXXXXXXXXOHHLHHLLHI
5 COXXXXXXXXOHHLHHLHLI
6 COXXXXXXXXOHHLHHLLLI
7 COXXXXXXXXOHHLHLLHL1
8 COXXXXXXXXOHHHLHHLH1
9 COXXXXXXXXOHHHLHHHL1
10 COXXXXXXXXOHHHLHLLH1
11 COXXXXXXXXOHHHLHLHLI
12 COXXXXXXXXOHHHLHLLLI
13 COXXXXXXXXOHHHLLLHLI
14 COXXXXXXXXOHLLHHHLHI
15 COXXXXXXXXOHLLHHHHLI
16 COXXXXXXXXOHLLHHLLH1
17 COXXXXXXXXOHLLHHLHL1
18 COXXXXXXXXOHLLHHLLLI
19 COXXXXXXXXOHLLHLLHLI
20 COXXXXXXXXOHLHLHHLHI
21 COXXXXXXXXOHLHLHHHL1
22 COXXXXXXXXOHLHLHLLH1
23 COXXXXXXXXOHLHLHLHLI
24 COXXXXXXXXOHLHLHLLL1
25 COXXXXXXXXOHLHLLLHL1
26 COXXXXXXXXOHLLLHHLHI
27 COXXXXXXXXOHLLLHHHL1
28 COXXXXXXXXOHLLLHLLHI
29 COXXXXXXXXOHLLLHLHL1
30 COXXXXXXXXOHLLLHLLLI
31 COXXXXXXXXOHLLLLLHL1
32 COXXXXXXXXOLLHLHHLH1
33 COXXXXXXXXOLLHLHHHL1
34COXXXXXXXXOLLHLHLLH1
35 COXXXXXXXXOLLHLHLHL1
36 COXXXXXXXXOLLHLHLLL1
37 COXXXXXXXXOLLHLLLHL1
38 CXXXXXXXXXIZZZZZZZZ1
PASS SIMULATION
4-58
Electronic Dice Game
ELECTRONIC DICE GAME
11 1111 1r1l2222 2222·2233
0123 4567 8901 2345 6789 0123 4567 8901·
°l -x--x-- ---x ---- --x-"".:;-
---- /Q1*Q3*/INIT
---- /Q1*Q4*/INIT
..i. __ )( .....-)(..;.
8
-x--
--X--~-- ~.:;--~---
16
17
-x-x ---..., ..:..--- ~.:;X.;.
-x-- ---- ---x --x-
24
25
---x ---x ---- --xx---
32 -x-33 -x-34 .,.X--
-.,.-- /Q3*/INIT
---.:..
--'--
---- /Q1*Q2*/INIT
---- ---- /Q1*Q4*/INIT
/Q1*Q2*Q3
INIT
---x ---- ---x
--x---x ---- ---- ---x --x--x- ---x -------
Q1*/Q5*Q7*/INIT
Q1*/Q5*Q8*/INIT
/Q1*Q6*/INIT
-x--x--
---x ---- --x--x- ---- ---x
Q1*/Q7*/INIT
/Q1*Q7*/INIT
-x--
-~--
-x--
--x---x ---x ------x --x---x -----x- ------x ----
56 -x-.• 57 -x--
---- ---x ---x ---x ---- --x---- --x- ---- ---- ---- ---x
40
41
48
49
50
LEGEND:
x:
FUSE NOT BLOWN (L,N,O)
NUMBEk OF FUSES BLOWN =
490
-------
Q1*/Q5*Q6*/INIT
Q1*/Q5*Q8*/INIT
/Q1*Q8*/INIT
Q1*/Q5*Q6*Q7*/INIT
/Q1*Q5*/INIT
- : FUSE BLOWN
(H,P,l)
Electronic Dice Game
Logic Diagram PAL16R8
Electronic Dice Game
CLK
~
0123
4567
B 91011
12131415
16171819
20212223
24252627
2S293031
0
I
1
J
,
"""
S
6
INIT
1
.
7
... ...
~
"
•
,
9
IU
"11
IS
J
.....Jt
..
.A
16
"
1]
.
.--
"'"
19
20
11
11
"
U]
I
"
NC
.Jt
i:
I
D
...
01----
I
15
16
27
"'"
28
19
]0
S
-
....
~
~~~
14
NC
02
~
IJ
"
NC
~r-~
1I
...
...
.<
.Jt
I
Dl
~
~
~
t>
Q
]1
]]
J4
J\
36
37
"'"
./
]8
NC
, ...
]9
..
.....
...
I
I
I
40
41
"
~. ~
'3
NC
7
....Jt
"45""
./
l---~
I
I
I
I
~
I
.....
I
I
,
18
"
SO
SI
S1
oj
NC
0
...
-
S4
SS
I
.
I
I
i
I
06
I
.....
....
I
50
../
NC
9
...
61
OJ
I
I
I
I
o
1 2 3
4
~
5'
8 9 1011
12 1314 15
I
1611 18 19
l---------z1
I
2021 22 23
2425 2b 21
2B 29 30 31
08
I~·.~
S7
SS
S9
61
~
~
...
~
4·61
Notes
9·Bit Register
PAL20X10
vee
co
01
02
03
Q4
05
06
07
08
Ne
DATA
OUT
D
9-Bit Register
PAL20X10
P8125
9-BIT REGISTER
MMI SUNNYVALE, CALIFORNIA
CLK DO D1 D2 D3 D4 D5 D6 D7 D8 /LD GND
/OC NC Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO vec
/QO := /QO*/LD
+ /DO* LD
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/19/81
1HOLD QO
1LOAD DO
,\'"
/Q1 := /Ql*JLI>
+ /D1* LD
1HOLD Q1
1LOAD D1
/Q2 := /Q2*/LD
+ /D2* LD
1HOLD Q2
1LOAD D2
/Q3 := /Q3*/LD.
+ /D3* LD
1HOLD Q3
1LOAD D3
/Q4 := /Q4*/LD
+ /D4* LD
1HOLD Q4
1LOAD D4
/Q5 :=/Q5*/LD
+ /D5* LD
1HOLD Q5
1LOAD 05
/Q6 := /Q6*/LD
+ /D6* LD
1HOLD Q6
1LOAD D6
/Q7 := /Q7*/LD
+ /D7* LD
1HOLD Q7
1LOAD D7
/Q8 := /Q8*/LD
+ /D8* LD
1HOLD Q8
1LOAD D8
.. \.
,(.'
FUNCTION TABLE
/OC CLK /LD D8 D7 D6 D5 D4 D3 D2 D1 DO Q8 Q7 06 Q5 Q4 Q3 02 Q1 QO
1/ C /
10 L L
1C K D
L
L
L
L
L
L
L
L
H
C
C
C
C
C
C
C
C
X
L
H
L
H
L
H
L
H
X
4-64
DATA IN
DDDDDDDDD
876543210
LLLLLLLLL
xxxxxxxxx
HHHHHHHHH
xxxxxxxxx
LHLHLHLHL
xxxxxxxxx
HLHLHLHLH
XXXXXXXXX
xxxxxxxxx
DATA OUT
QQQQQQQQQ
876543210
COMMENT
LLLLLLLLL
LLLLLLLLL
HHHHHHHHH
HHHHHHHHH
LHLHLHLHL
LHLHLHLHL
HLHLHLHLH
HLHLHLHLH
ZZZZZZZZZ
LOAD
HOLD
LOAD
HOLD
LOAD
HOLD
LOAD
HOLD
TEST
ALL ZEROS
ALL. ZEROS
ALL ONES
ALL ONES
EVEN CHECKERBOARD
EVEN CHECKERBOARD
ODD CHECKERBOARD
ODD CHECKERBOARD
HI-Z
9·Bit Register
DESCRIPTION
THIS 9-BIT REGISTER LOADS THE DATA (DB-DO) ON THE RISING EDGE OF
THE CLOCK (CLK) IF THE LOAD LINE (/LD) IS ASSERTED (LOW ON PIN 11)
AND OTHERWISE HOLDS THE ORIGINAL VALUE.
THE 9-BIT ARCHITECTURE MAKES THIS REGISTER IDEAL FOR PARITY BUS
INTERFACING IN MICROPROGRAMMED SYSTEMS.
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED
IN OPERATIONS TABLE:
IOC
CLK
ILD
H
L
L
X
X
X
Z
C
C
H
L
X
Q
OS-DO
o
Q8-QO
o
OPERATION
HI-Z
HOLD
LOAD
D
9-BIT
REGISTER
-CLOCK
LOAD ---I~--r-r----1
OUTPUT CONTROL
a
9-BIT REGISTER
1
2
3
4
5
6
7
8
9
COOOOOOOOOOXOXLLLLLLLLLI
CXXXXXXXXXIXOXLLLL.LLLLLI
CIIIIIIIIIOXOXHHHHHHHHHI
CXXXXXXXXXIXOXHHHHHHHHHI
COIOIOIOIOOXOXLHLHLHLHLl
CXXXXXXXXXIXOXLHLHLHLHLI
CIOIOIOIOIOXOXHLHLHLHLHI
CXXXXXXXXXIXOXHLHLHLHLHI
xxxxxxXXXXXXIXZZZZZZZZZl
PASS SIMULATION
4·65
9-Bit Register
9-BIT REGISTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
0
1
x---x--
/QO*/LD
/DO*LD
x---x--
/Q1*/LD
/D1*LD
x---
-x--
/Q2*/LD
/D2*LD
x---x--
/Q3*/LD
/D3*LD
---- ---x ----
x---x--
/Q4*/LD
/D4*LD
---x
-x--
x---x--
/Q5*/LD
/D5*LD
x---x--
/Q6*/LD
/D6*LD
x---x--
/Q7*/LD
/D7*LD
---x x---x-- -x--
/Q8*/LD
/D8*LD
---x
-x--
8
9
---x
-x----x
-x--
16
17
---x
-x--
24
25
----
32
33
-x--
40
41
---x
-x--
48
49
56
57
---x
-x--
---- ----
64
65
LEGEND:
x:
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW =
4-66
684
FUSE BLOWN
(H,P,I)
9-Bit Register
Logic Diagram PAL20X10
9-Bit Register
CLK
1
-t>
II
123
4 S
& 1
191011
12131415
1&1111'9
211212223
24252621
282930]1
Jl31J435
36313'39
,
:;;::.
~~
- M~
,
2
~
DO.~
.·,
3
~~
..... -
...
~
.......-
~~
""
"
"
02
4
~-
...
~
-
~=9D
""
""
~
03 L...t~
~:::.
:R:r~D
J2
"
"
J5
04 ~~
...
~
...
"
"
16
Q6
Q7
""'-
...·
..
......
~-l:;JD
""- ~
Ie(
"
08 ~~
J
""-
--;o-~
"
""
"
·
~
Q5
....
V
50
11
PI
~ Q49
PI
"";J.
"
LO
~
Q3
....
...... .--
"
9
Q2
'It
..
07
~
~
M
~
~-9DM
IDD- Dl
-
7
05 ---I
8
Q1
@D
.... -
"
"
06
PI
~
~
"
01
QO
Ie(
J
~J
Q
,.~
._ I
2 1
•
5
•
1
" " 11
12131415
Iii IJ I"g:
20212223
24252611
U 2!llO 31
1211311
n
31
n
~.2
v
R
v
Q8
NC
•
~.
,
lflt
4-67
Notes
4.68
Multifunction Octal Register
PAl20X8
DATA
OUT
4-69
Multifunction Octal Register
PAL20X8
74LS380
MULTIFUNCTION OCTAL REGISTER
MMI SUNNYVALE, CALIFORNIA
CLK /LO DO 01 02 03 04 05 06 07 POL GNO
/OC /PR Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO /CLR vec
/QO :=
CLR
+ /CLR*/PR*/LD*/QO
:+ : /CLR*/pR* LO* POL*/oo
+ /CLR*/PR* LO*/POL* DO
/Q1 :=
CLR
+ /CLR*/PR*/LD*/Q1
:+: /CLR*/PR* LO* POL*/01
+ /CLR*/PR* LO*/POL* 01
/Q2
:=
CLR
+ /CLR*/PR*/LO*/Q2
:+ : /CLR*/PR* LO* POL*/D2
+ /CLR*/PR* LO*/POL* D2
/Q3 :=
CLR
+ /CLR*/PR*/LD*/Q3
:+: /CLR*/PR* LO* POL*/D3
+ /CLR*/PR* LD*/POL* D3
/Q4
:=
CLR
+ /CLR*/PR*/LD*/Q4
:+: /CLR*/PR* LO* POL*/04
+ /CLR*/PR* LD*/POL* 04
/Q5 :=
CLR
+ /CLR*/PR*/LO*/Q5
:+: /CLR*/PR* LD* POL*/05
+ /CLR*/PR* LO*/POL* 05
/Q6
/Q7
CLR
PAL DESIGN SPECIFICATION
BIRKNER/KAZMI/BLASCO 02/16/81
; CLEAR
; HOLD
; LOAD DO (TRUE)
;LOAD /00 (COMP)
; CLEAR
; HOLD
; LOAD 01 (TRUE)
;LOAD /01 (COMP)
; CLEAR
; HOLD
; LOAD D2 (TRUE)
;LOAD /D2 (COMP)
; CLEAR
; HOLD
; LOAD 03 (TRUE)
;LOAD /D3 (COMP)
; CLEAR
; HOLD
; LOAD 04 (TRUE)
;LOAD /04 (COMP)
; CLEAR
; HOLD
; LOAD 05 (TRUE)
;LOAD /05 (COMP)
+ /CLR*/PR*/LO*/Q6
:+: /CLR*/PR* LO* POL*/06
+ /CLR*/PR* LO*/POL* 06
; CLEAR
; HOLO
; LOAD 06 (TRUE)
;LOAD /06 (COMP)
CLR
+ /CLR*/PR*/LO*/Q7
:+ : /CLR*/PR* LO* POL*/07
+ /CLR*/PR* LO*/POL* 07
; CLEAR
; HOLD
; LOAD 07 (TRUE)
;LOAD /07 (COMP)
:=
:=
4.70
Multifunction Octal. Register
FUNCTION TABLE
07 D6 05 D4 03 02 01 DO /CLR /PR /LDPOL CLK
INPUTS
07----00
CONTROL
/CLR /PR /LD POL CLK /oe
/oe Q7 Q6 Q5
OUTPUTS
Q7----QO
Q4 Q3 Q2 Q1 QO
COMMENTS
-------~----------------------------------------------------------------------
;CLEAR AND PRESET TESTS
AAAHHHHH
L
L
L
a C L LLLLLLLL CLEAR (OVERRIDES PRESET/LOAD)
LLLLLLLL
aLL
a C L BARBARHH PRESET (OVERRIDES LOAD)
CLEAR (POL-L)
LLLLLLLL
L
L
L
L
C
L
LLLLLLLL
aHHHHHHR
aLL
L
C
L
RRRRRRRR
PRESET (POL-L)
; LOAD DATA - WALKING ZEROES (TRUE DATA)
LOAD HEX (FE)
RRRRRRRt,
a
a
Lac
L
RRRRRRR!,
LOAD HEX (FO)
RRRRRR!$
a
a
L
H
C
L
RRRRRR!$
LOAD HEX (FB)
mnnmr,HH
a
a
Lac
L
mnnmr,HH
HHRHI,mm
a
a
Lac
L
HHRHI,mm
LOAD HEX (F7)
LOAD HEX (EF)
HHHI,Hmm
a
a
Lac
L
HHHI,mmH
HHI,mnnm
H
H
L
H
C
L
HHI,mnnm
LOAD HEX (OF)
HLHBHHHH
H
H
L
H
C
L
HI,amnnm
LOAD HEX (BF)
LBmnnmH
H
H
L
H
C
L
T,RRRRRRR
LOAD HEX (7F)
RRRRRRRR
a
a
L
H
C
L
RHRRHRRR
LOAD HEX (FF)
; LOAD DATA - WALKING ONES (TRUE DATA)
LLLLLLLB
LOAD HEX (01)
LLLLLLLB
a
a
L
H
C
L
T,lJ,lJ,I,HL
LOAD HEX (02)
LLLLLLHL
a
H
L
H
C
L
T,T,T,T,T,HI,L
LOAD HEX (04 )
LLLLLHLL
a
H
L
H
C
L
LI,T,T,HI,I,T,
LOAD HEX (08 )
LLLLHLLL
a
a
Lac
L
I,T,T,HI,I,T,T,
LOAD HEX (10)
LLLHLLLL
HaL
a
C
L
T,T,BT,T,T,T,T,
LOAD HEX ( 20)
LLHLLLLL
HaL
a
C
L
T,HI,T,T,r,I,T,
LOAD HEX ( 40)
LHLLLLLL
a
a
L
H
C
L
HIJ,T,IJJ,r,
LOAD HEX (80)
HLLLLLLL
a
H
L
H
C
L
I,lJ,I,T,LLL
LOAD HEX ( 00)
LLLLLLLL
HaL
H
C
L
; LOAD DATA - WALKING ONES (COMP DATA) WITH HOLD TESTS
I,I,I,I,I,I,I.I,
HOLD
LLLLLLLL
a
H
H
L
C
L
RRRRBRRR
LOAD HEX(OO) (CaMP)
LLLLLLLL
a
aLL
C
L
LLLLLLLL
a H a a C L HHRHHHHR HOLD
LLLLLLLB
a H L L C L RRBRRRR!, LOAD HEX(Ol) (CaMP)
LLLLLLLL
H
H
a L C L RRRRRRR!. aOLD
a a L L C L RRRHHR!,l! LOAD HEX(02) (COMP)
LLLLLLHL
a H a H C L RRRRRR!.H aOLD
BmnnmHH
a a L L C L mnnmr.HH LOAD HEX(04) (CaMP)
LLLLLBLL
a a a L C L mnnmr.HH aOLD
LLLLLLLL
LLLLHLLL
a a L
HHRHI.HHH
LOAD HEX (80) (CaMP)
L
L
C
amnnmHa
a a a a C L HHRHI.mm aOLD
LLLHLLLL
a a L L C L HHHI.Hmm LOAD HEX (10) (COMP)
H
LLLLLLLL
a a L C L HHHI.Hmm HOLD
a a L
HHI,mmHH
LOAD HEX (20) (CaMP)
LLHLLLLL
L
L
C
amnnmHH
a H a a C L HHI,mnnm aOLD·
r,HI,r,r,r,LL
a a L L C L HI,mmHHH LOAD HEX(40) (COMP)
LLLLLLLL
a a a L C L HI.amnnm HOLD
HLLLLLLL
H
a L L C L I.RRBRRRR LOAD HEX (80) (CaMP)
HARAAAHH
a a a a C L I.RRRRRRR aOLD
a H L L C L RRRRRRRR LOAD HEX(OO) (COMP)
LLLLLLLL
XXXXXXXX
x x x x x a ZZZZZZZZ TEST HI-Z
-----------------------------------------------------------------------------4·71
Multifunction Octal Register
DESCRIPTION
THIS IS AN a-BIT SYNCHRONOUS REGISTER WITH PARALLEL LOAD, LOAD COMPLEMENT,
PRESET, CLEAR, AND HOLD CAPABILITIES. FOUR CONTROL INPUTS (/LD,POL,/CLR,/PR)
PROVIDE ONE OF FOUR OPERATIONS WHICH OCCUR SYNCHRONOUSLY WITH THE CLOCK (CLK).
THE LOAD OPERATION LOADS THE INPUTS (07-00) INTO THE OUTPUT REGISTER (Q7-QO),
WHEN POL=H OR LOADS THE COMPLEMENT OF THE INPUTS WHEN POL=L. THE CLEAR (/CLR)
OPERATION RESETS THE OUTPUT REGISTERS TO ALL LOWS. THE PRESET (/PR) OPERATION
PRESETS THE OUTPUT REGISTERS TO ALL HIGHS. THE HOLD OPERATION HOLDS THE
PREVIOUS VALUE REGARDLESS OF CLOCK TRANSITIONS.
CLEAR OVERRIDES PRESET, PRESET OVERRIDES LOAD, AND LOAD OVERRIDES HOLD.
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
OPERATIONS TABLE:
/OC
CLK
H
L
L
X
C
C
C
C
C
L
L
L
/CLR
X
L
H
H
H
H
/PR
X
X
L
H
H
H
/LD
POL
D7-DO
Q7-QO
OPERATION
X
X
X
X
X
X
X
D
D
Z
L
H
Q
D
/D
HI-Z
CLEAR
PRESET
HOLD
LOAD TRUE
LOAD COMP
X
L
H
L
L
X
X
H
L
----------------------~------------------------------- ---
D
POLARITY _ _ _
LOAD
PRESET
CLEAR
_CLOCK
OUTPUT CONTROL
Q
Multifunction Octal Register
MULTIFUNCTION OCTAL REGISTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
C0111111111XOOLLLLLLLL01
C0000000001XOOHBHHHBBH11
COOOOOOOOOOXOOLLLLLLLL01
C0111111110XOOBBHHHBBH11
C0011111111X01HHBBHBHL11
C0101111111X01BBHHHHLH11
C011011111lX01HHBBHLHH11
C0111011111X01HHBBLHHH11
C0111101111X01BBHLHHBB11
COll111011lX01HHLHHBBH11
C011111101lX01BLHHHHHB11
COllllll101X01LHHHHBBHll
COll111111lX01BBHHHBBH11
C010000000lX01LLLLLLLH11
C0010000001X01LLLLLLBL11
C0001000001X01LLLLLBLLll
C0000100001X01LLLLHLLL11
C0000010001X01LLLHLLLL11
C0000001001X01LLHLLLLL11
C0000000101X01LBLLLLLL11
C0000000011X01HLLLLLLL11
C0000000001X01LLLLLLLL11
C1000000000X01LLLLLLLL11
COOOOOOOOOOX01BBBBBBBB11
C1000000001X01HHBBHHHHll
C0100000000X01BBHHHHHLll
C1000000000X01BBHHHHHLll
C0010000000X01BBHBHBLH11
Clllllll111X01BBHHHHLHll
C0001000000X01BBHHHLHH11
C1000000000X01BBHHHLHH11
C0000100000X01BBHBLHBH11
Cll11111111X01HBHBLHBH11
COOOO.010000X01HBHLHHHHll
C1000000000X01BBHLHHHH11
C0000001000X01HHLHHBBH11
Cl111111111X01HHLHHBBH11
C0000000100X01BLHHHHHH11
C1000000000X01BLHHHHHBll
C0000000010X01LHHHHBBH11
Cll1111111lX01LHHHHBBH11
COOOOOOOOOOX01BBHHHBBH11
XXXXXXXXXXXX1XZZZZZZZZX1
PASS SIMULATION
4·73
Multifunction OctalA.glster
MULTIFUNCTION OCTAL REGISTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
8 ---x ---9 x-x- ---x
10 -xx- -x-11
-xx- x--
16 --x ---17 x-x- ---18 -xx- ---19 -xx- ---24 ---x
25 x-x26 -xx27 -xx32
33
3.4
35
40
41
42
43
48
49
SO
-------
---x ----xx--
---
---x ----x--
-xx-
56
57
58
59
---x ---x-x-xx-xx-
64
65
66
67
--x --x-x-xx---- ----xx-
LEGEND:
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
4_74
= 1160
CLR
/CLR*/PR*/LD*/Ql
/CLR*/PR*LD*POL*/nl
/CLR*/PR*LD*/POL*Dl
--xx-x-
CLR
/CLR*/PR*/LD*/Q2 '
/CLR*/PR*LD*POL*/n2
/CLR*/PR*LD*/POL*D2
CLR
/CLR*/PR*/LD*/Q3
x-x- /CLR*/PR*LD*POL*/n3
-xx- /CLR*/PR*LD*/POL*D3
CLR
/CLR*/PR*/LD*/Q4
x-x- /CLR*/PR*LD*POL*/n4
-xx- /CLR*/PR*LD*/POL*D4
--x-
CLR
/CLR*/PR*/LD*/Q5
/CLR*/PR*LD*POL*/n5
-xx- /CLR*/PR*LD*/POL*D5
--xx-x-
---x ---xx---
51 -xx-
--xx-x-xx-
--x-
x-- ---
--x ---- ---x-x-
-xx-
CLR
/CLR*/PR*/LD*/QO
/CLR*/PR*LD*PoL*/nO
/CLR*/PR*LD*/POL*DO
-xx-
x--- -----x ------- ---x-x- --- -----x
-xx- --- ----x--xx- --- --- ---- x----x - x-x---x ---x--xx-xx-
--xx-x-
---x ---- --x-x-x-xx---xx-
CLR
/CLR*/pR*/LD*)Q6
/CLR*/PR*LD*POL*/D6
/CLR*/PR*LD*/POL*D6
---x,--x-x- x-x-
CLR
/CLR*/PR*/LD*/Q7
/CLR*/PR*LD*POL*/n7
/CLR*/PR*LD*/POL*D7'
x-- -xx-
-
: FUSE
BLOWN
(B,P,l)
Multifunction Octal Register
Logic Diagram PAL20X 8
Multifunction Octal Register
elK
1
.....
~a123
.,
45'
1
891011
121)1415
16 t1 1819
20]1122]
14252621
2129]0]1
323134U
3611J.:H
~
=I~
2
3
~
,
~D- ~~
BL
..,
::::-
"
DO
~
~
-
~D-
"
"
"
~
4
01 ---t
"25
~D...... -
"
"
02 L
~~D-tj.-J
"
"
~
6
~
...
IDD-
."
'--'-
7
..
.
~D~
..K-L
"
05
8
.,
;0
9
~
~
02
~
~
03
~
'""J
18
~
~
17
05
RV
16
as
v
V
04
~
~D~
~ ....
07
-t5--L
"
07 ~~
it:
~
"n
"
"
11
01
.
•
,
2 l
•
S 6 I
• • 10 II
12 11 I. IS
'117'1"
20212123
2.152621
11 2! lD JI
n 11341 15
14
~
lli 31 lilt
4·75
D
Multifunction Octal Register
Application
16-Bit Register
BUS OUT ENABLE
ClK
Li5
POL
16-BIT
DATA BUS
IN
r-v-- E
~1Ic--J
~~
r----
~ 1-_ lD v ClR
.12.
DO
00
14 f--- 01
01 1---
i.!. I--- 02
02 r---
~
rs f--- 03
~
L2. f--- 04
03 r---.
04 ' - -
rs c-- 05
05 C---
f---06
06--
._;;..!.
Im-'
r- iw.
'iii f--- ~~l OC ~~ -
I,,;.;;
F-I
rw
rw
F-I
rw
rw
~
~
~
~
I--'
I;&t
~
~
~
r;;
~
100. f--JI~
I--'
~
@
~
...---....,.--
-II--=j
~
IT
r----~1---1
~
lovClR
00 -
12. t--- DO
IT f--- 01
i'::::1
~
01 - -
~
cr -
02
02 -
IE:!
8: -'---
03
03 r---
':m
~
-
04
04r---:ill
~_c
05
osr---:m
II c--- 06
061--- :ill
'iii r-- 07
071--- lsi
I,,;.;;
POlOCPR
-.
r;;
.... ~J
m
I
~ I--'
'i4'
~.
16-BIT
DATA BUS
OUT
8~Bit I/O PrioFity Inte,.rupt
Encoder With Registers·
PAL16R4
,
f'
a.Bit 1/0 Priority Encoder with Register.
PAL16R4
PAL DESIGN SPECIFICATION
8BITENC
VINCENT COLI 06/28/81
8-BIT I/O PRIORITY INTERRUPT ENCODER WITH REGISTERS
MMI SUNNYVALE, CALIFORNIA
CLK 11 12 13 14 IS 16 17 18 GND
/OC NC NC Q4 Q3 Q2 Q1 NCNC vec
/Q1
12 ~
+ /ii*/I2*/I3. 14
:~ /Il~
M
"
+/Il*/I2*/13~/I4*/I5*
16,
+ /11*/12*/13*/14*;:[5*/16*/17* 18
/Q2 :=
+
+
+
/11*/12* 13
/11*/12*/13* 14
/11*/12*/13*/14*/15*/16* 17
/11*/12*/13*/14*/15*/16*/17* 18
/Q3 :=
+
+
+
/11*/12*/13*/14* IS
/11*/12*/13*/14*/15* 16 {,1"
/11*/12*/13*/14*/15* /1 6*>-J
1
2
J
•
5
6
11 3
.. ">
1
....Jt
01
~
~
02
~
~
03
~
04
1--.---
""
D
../
22
2J
4
01--
~~~
<
24
15
26
21
J
""
JO
14
~
rJ
11
12
13
14
15
20
21
5
NC
...
16
11
18
19
13
18
...
,
"
J
NC
~.~
8
12
19
.
.
J1
1C.
...
J2
JJ
J4
J5
J6
J7
15
6
....
"
J
"
J9
1C
"
"
...
41
"'
43
.
"45
16
7
...
./
"
...
...
...
48
rJ
49
"
""
53
54
17
8
.
"
..
..
NC
...
"
""
""
r-J
..
9
13
...
57
18
lDl
6J
...
o1
.....
2 J
4 5 6 7
8 9 1011
12131415
1617 18 19
20212223
24252627
28293031
12
NC
~
4-81
Notes
BCD/Hex Counter
PAL20X8
BCD/Hex Counter
07
II
06
05
04
II
03
02
I
1111
e vG
DO
01
1
1 2 3
HP
SPLAY
01 5082
7304
1
LLL '=dJ LLL-~ LLL-~
Irr;~
1rR;~
I~~l
lIfr
LLL~
Vl~
321032100
PAl20XS
MSB
PAL20XS
COC1 C2C3COCSCS
COC1 C2 C3 Co Cs Cs
,~
IJ
PAl20XS
J
PAl20XS
COC1 C2 C3COCSCS
IJJ IJ
IJ I,Jill' IJ
~
~
,.
"
.
ClK
10
PROBE
I
+5
,HEX
PB
ClR
4-84
)
6
6k
S-BIT
TOGGLE
HEX
x5
l5B
COC1 C2C3 COCSCS
1 I~
-------
~
BCD/Hex Counter
PAL20X8
BHEX
BCD/HEX COUNTER
MMI SUNNYVALE, CALIFORNIA
CK /CLR HEX /CO /Cl /C2 /C3 /C4 /CS /C6 /CIN GND
/oe /COUTI AO Al A2 A3 BO Bl B2 B3 /COUT2 vec
IF (VCC) COUT2
= /CLR*BO*BI*B2*B3
+ /CLR* /HEX*BO*B3
/B3 := C~R
+ /CLR*/B3
:+:/CLR*CO*CI*C2*C3*C4*CS*C6*CIN*BO*Bl*B2
+ /CLR* /HEX*BO*B3
PAL DESIGN SPECIFICATION
SAEED KAZMI 04/28/81
; HEX COUNT CARRY OUT
; BCD COUNT CARRY OUT
; CLEAR
;HOLD, MSB OF STAGE 2
; INCREMENT
;CLEAR IF BCD & COuNT=9
/B2:= CLR
+ .rCLR*/B2
:+:/CLR*CO*Cl*C2*C3*C4*CS*C6*CIN*BO*BI
/Bl:= CLR
+ /CLR*/Bl
:+:/CLR* HEX*CO*Cl*C2*C3*C4*CS*C6*CIN*BO
+ /CLR* /HEX*CO*Cl*C2*C3*C4*CS*C6*CIN*BO*/B3
/BO := CLR
+ /CLR*/BO
:+:/CLR*CO*Cl*C2*C3*C4*CS*C6*CIN
/A3 := CLR
+ /CLR*/A3
:+:/CLR*CO*Cl*C2*C3*C4*CS*C6*AO*AI*A2
+ /CLR* /HEX*AO*A3
;CLEAR IF BCD & COUNT=9
; HOLD, LSB OF STAGE 2·
;HOLD, MSB OF STAGE 1
;yLEAR IF BcD &;COUNT;'9
/A2:= CLR
+ /CLR*/A2
:+:/CLR*CO*Cl*C2*C3*C4*CS*C6*AO*Al
/Al:= CLR
+ /CLR*/Al
:+:/CLR* HEX*CO*CI*C2*C3*C4*CS*C6*AO
+ /CLR* /HEX*CO*Cl*C2*C3*C4*CS*C6*AO*/A3
;CLEAR IF BCD & COUNT=9
/AO:= CLR
+ /CLR*/AO
:+:/CLR*CO*CI*C2*C3*C4*CS*C6
;HOLD, LSB OF STAGE 1
IF (VCC)COUTI = /CLR* HEX*AO*AI*A2*A3
+ /CLR*/HEX*AO*A3
;HEX COUNT, INT. r~Y
;BCD COUNT, INT. CARRY
4·85
BCD/HexCounter
FUNCTION TABLE
HEX CLR CK OC CO Cl C2 C3.C4 C5 C6
COUT2 B3 B2 Bl BO COUTI A3 A2 Al AO CIN
;HC C 0 C CC CC CCC B B B B C A A A A C
;EL K COl 2 3 4 5 6 0 3 2 1 0 0 3 2 1 0 I
;XR
U
U
N
.T
2
T
'1
COMMENT
----.---------.;..---:o-------------'"':"~_:'------------..;.------- ------------------
X H C H L L L. L L L LL L r,. L. L L L L L L L
X H C H H.H H H H H H L L L. L L L L.L L L H
H L C H H H.HH H H HL.L LL H LL LL H H
~LCHHiH~HHH~LLBLLLLHLH
HLCHHHHHHHHLLLHHLLLHHH
H L CH H H H HH H H L L H L L L L H L L H
HLCHHHHHHHHLLHLHLLH~HH
H L C H H H H H H H'H LL H H L L L H H L H
HLCHHHHHHHHLLHHHLLHHHH
HLCHHHHHHHHLHLLLLHLLLH
HLCHBHHBHHHLHLLHLHLLHH
H L C H H H H H HHH LH L H L L H L H LH
H L C H H H H H HH H L'H L H H L H L H H H
HL CHHHHHHHHLHHL L L HHL L H
H L C H H H HH H H H L H HL H L H H L HH
HLCHHHHHHHHLBHH~LHHHLH
HLCHHHHHHHHHHHHHHHHHHH
H L C H H H HH H H H L L L L L L L L L L H
L L.CH H H H H H H H L L L L H L L L.L H H
L L C H H HHHH H H~t L H ~ L L L H L H
L L C H H H HH H.H H L L L H H L L L H H H
L L C H H H H H H H H L L H LL LL H L L H
L L CH H H H H HH H'L L H L H ~ LH LH H
LtC H H H H H H H.H L L H H LL L HH L H
LLCHHHHHHHHLLHHHLLHHHH
LLCHHHHHHHHLHtL~LHLLLH
LLCHHHHHHHHHHLLHH.HLLHH
L L C H H H H H H H H LL L L 'L L L L L L H
4.AA
CLEAR
HOLD, HEX COUNT 00
'HEX COUNT 11
22
33
44
55
66
77
88
99
AA
BB
CC
DD
EE
FF
BCD COUNT 00
11
22
33
44
55
66
77
88
99
100
BCD/Hex Counter
DESCRIPTION
FOUR IDENTICALLY PROGRAMMED PALS ARE USED TO DRIVE EIGHT OF HP'S NUMERIC
AND HEX INDICATORS (5082-7340). EACH PAL CONSISTS OF TWO FOUR BIT COUNTERS.
STAGE 1 IS THE LSB AND STAGE 2 IS THE MSB. CARRYOUTOF STAGE 1 IS CALLED
INTERNAL CARRY (CooTl) AND IS FED EXTERNALLY TO STAGE 2. COUT2IS FED INTO
THE NEXT PAL. CARRYOUT AND INTERNAL CARRYSFROM THE LOWER PAL ARE CONNECTED
TO ALL OF THE HIGHER PALS TO PERFORM THE CARRY LOOK AHEAD OPERATION.
TfiESE PALS HAVE TESTABILITY BUILT INTO THEM. COUTIIS CONNECTED TO CIN :
EXTERNALLY AND CAN FORCE COUTlTO GO HIGH, THUS STAGE 2 MAY START COUNTING
AT THE SAME TIME AS STAGE 1 WHICH REDUCES THE NUMBER OF TEST VtcTORS IN THE
FUNCTION TABLE.
THIS COUNTER OPERATES AT 10 MHz AND CAN PERFORM THE FOLLOWING OPERATIONS:
CLR'
HEX
X
L
CLEAR
COUNT BCD
L ..
COUNT HEX
__________ '_____ ;.... _____ _
H
L
H
";___
OPERATION
~;..,i
BCD/HEX COUNTER
1 COXIIIIIIIIXOHLLLLLLLLHI
2 COXOOOOOOOOXOHLLLLLLLLHI
3 CllOOOOOOOOX.OHHLLLHLLLHI
4 CllOOOOOOOOXOHLHLLLHLLHl
5 CllOOOOOOOOXOHHHLLHHLLal
6CII00000000XOHLLHLLLHLHI
7 CI100000000XOHHLHLHLHLHI
8 CllOOOOOOOOXOHLHHLLHHLHl
9 CllOOOOOOOOXOHHHHLHl'UrLHI
10 CII00000000XOHLLLHLLLHHI
11 CI100000000XOHHLLHHLLHHI
12CII00000000XOHLHLHLHLHHI
13 CllOOOOOOOOXOHHHLHHHLHHl
14 CllOOOOOOOOXOHLLFiFiLLBHHI
15 CllOOOOOOOOXOHHLHHHLHHHI
16 CllOOOOOOOOXOHLHHBLHBHHI
17 CllOOOOOOOOXOLHHHHHBHHLl"
18 C11000000dOXOHLLLLLLLLBl
19 CI000000000XOHHLLLHLLLHI
20 CI000000000XOHLBLLLHLLB1
21 C1000000000XOHHBLLHBLLH1'"
22 C1000000000XOHLLHLLLBLU'
23 CI000000000XOHHLHLHLHLH1
24 CI000000000XOHLHHLLHHLHI
25 C1000000000XOHHHHLHHHLBI
26 C1000000000xOFiLLLBLLLHH1
27 ClOOOOOOOOOXOLHLLHBLLHLI
28 C1000000000XOHLLLLLLLLHl
PASS SIMULATION
<,
BCD/Hex Counter
BCO/HEX COUNTER
11 1111 1111 2222 4222 2233 3333 3333
0123
o
1
2
8
9
10
11
45678~012345.6789
0143 4567 8901 23456789
---- -.--- ----:, ---..,. ---- ---'- ---.,.' ---- ---x--- --x- --X-,--:X- --x- ---- ---- -------,.. ---x--- -XX- ---- ---:- --x- ------------ ---- ----
-x-- ---- ----.-.,..-- --.-- ---- ---- ---- --:-- ---x--- ---x -.,..--. --~- --\;".- ---- ---- ----.. ---- ---x--- ----.-:XX- -xx,... -XX--X-- -x-- -x-... -:X-- -X-x--- -xx- ---- ---- --x- ---- ---- -------
16 -x-17 x--18 x---
----: ......-- --'--' ---- ----
------x
-x--x--
-------xx-xx-
-------x--x--
/CLR* /B3
/CLR*CO*C1*C2*C3*C4*C5*/CLR*/HEX*BO*B3
/CLR*/B2
/CLIt*CO*C1*C2*C3*C4*C5*-
24
25
26
27
-x-x--x--x---
32
33
34
-x-- ---- ---- ---- ---- ---- ---- ---- ---- ---x--- ---- ---- ---- ---x ---- ---- ---- ---- ---x--- ---- -x-- -x-- -x-- -x-- -x-- -x-- -x-- -x--
CLR
/CLR*/BO
/CLR*CO*C1*C2*C3*C4*C5*-
40
41
42
43
-x----- ---- ---- ---- ------x------ ---- ---- ---x -------x-- -x-- -x-- -x-- -xx- -xx- -xx- ---x--x--- -x----- ---- --x- ---- ---- --x- ----
CLR
/CLR*/A3'
/CLR*CO*C1*C2*C3*C4*C5*/CLR*/HEX*AO*A3
48
49
50
-x----- ---- ---- ---- ---- ---- ---x--- ---- ---- ---- ---- ---- ---x ---x--- ---- -x-- -x-- -x-- -x-- -x-- -xx- -XX- ----
CLR
/CLIt*/A2
/CLR*CO*C1*C2*C3*C4*C5*,...
56
57
58
59
-x----- ---- ---- ---- ------- ---x------ ---- ---- ---x ---- ---x--- x--- -x-- -x-- -x-- -x-- -x-- -x-- -xxx--- -x-- -x-- -x-- -x-- -x-x -x-- -x-- -xx- ----
CLR
/CLR*/A1
/CLR*HEX*CO*Cl*C2*C3*C4/CLR*/HEX*CO*C1*C2*C3*C-
64
65
66
-x-x--x---
72
73
74
x--- x--x--- -x-- ----
LEGEND:
-------x--x--
CLR
---- CLR
---x ---- ---- ---------- -x-- -xx- -xx- -x-- -x-- -x-- -x-- -x-------x---x-x
/CLR,*BO*B1*B2*B3
/CLR*/HEX*BO*B3
------- CLR
---- ---- ----: ---- /CLR*/B1
-x-- -x-- -x-- -X,:,,-:,/CLIt*HEX*CO*C1*C2*C3*C4-x-- -x-- -x-- -x-- !CLIt*/HEX*CO*C1*C2*C3*C-
---- ---- ---- ---- ---- ---- ---- CLR
---- ---- ---- ---x ----x-- -x-- -x-- -x-- -x-- -x-- -x-- ------- ----
--x;.. --x- --x- --x- ---- /CLR*HEX*AO*Al.*A2*A3
--x- ---- ---- --x- ----
X : FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW = 1204
/CLIt*/AO
/CLR*CO*C1*C.2*C3*C4*C5*-
FUSE BLOWN
/CLR*/HEX*AO*A3
I
(H,P,l)
BCD/Hex Counter
BCD/HEX Counter
CK
1
Logic Diagram PAL20X8
....
..,... 0
.,
12 l
45
& J
• • 10 u
12\31415
18171'1'
Z.OZIUZl
«
%52121
H lIlD 31
3! 33 M J5
31313111
0
.
.J.
I
J
CLR ~
......
I
-'""'--
"
-O--L
~D.
~~
..•
HEX
3
.
~-9D-
."
"
co 4
~
--"
:R:J~D-
II
IS
C1
~~
"
"
-t:5--l
"
~D-
5
""'-
"
"
"
C2
....
6
..........
....
~~D
-O---l
"
7
....
~
II
"
......
SI'·
B1
~
~
....
BoD
~
t;I.
.
-
51
••
C5
~
~
21
16
!"'"
t;I.
....
~
....
IDI>t; ~
"
9
.....
16
C6 .!LL
B2
A3
A2
A1
.
,
"
B3
~
~~D
8
COUT2
t;I.
....
IDD tQ]~
.....
C4
23
'
AO
.
.....
11
""
-
.l'K J...,
"
11
..J..
....
~
o
1 Z 3
• 5 I'
• • to It
It Ill. IS
111' , . "
Z. 21
unit
ZS 21
zr
14 .,.....--
"
COUT1
13 " ' -
A-
OC
.~
"
21 H 3. 31
32 U:M 3S
li 11 31:11
Notes
64k Dynamic RAM
Refresh Controller
PAL20X4
4·91
64k Dynamic RAM Refresh Controller.
COUNT
REFEN
ROWEN
CAS
t-H--o~CK
DATA
IN
A:rAo
PAL20X4
0:r00
/CARRY
CK
A4- A7
A1l-A15
65, 536xl
RAM
ICARRY
OUT
A3-Ao
PAL20X4
0:r00
All-As •
/CARRY
IN
4.Q2
WRITE
DATA
OUT
64k Dynamic RAM Refresh Controller
PAL20X4
PAL DESIGN SPECIFICATION
DYNRAM
MIKE VOLPIGNO
07/15/81
64k DYNAMIC RAM REFRESH CONTROLLER
MMI FIELD APPLICATIONS ENGINEER NEWTON, MASSACHUSETTS
COUNT AO A1 A2 A3 A8 A9 A10 All REFEN ROWEN GND
/oe /CARRYOUT 03 02 C3 C2 C1 CO 01 00 /CARRYIN vec
/CO :=
/CO
REFEN*/ROWEN
CARRY IN
REFEN*/ROWEN
:INCR REF ADDRESS COUNTER
: SET REF COUNTER
:INCR REF COUNTER
:SET REF COUNTER
/C1
REFEN*/ROWEN
CARRYIN* .CO
REFEN*/ROWEN
:INCR REF COUNTER
:SET REF COUNTER
:INeR REF COUNTER
:SET REF COUNTER
/C2
REFEN*/ROWEN
CARRYIN* CO* C1
REFEN*/ROWEN
:INCR REF COUNTER
:SET REF COUNTER
: INCR REF COUNTER
:SET REF COUNTER
/C3
REFEN*/ROWEN
CARRYIN* CO* C1* C2
REFEN*/ROWEN
:INCR REF COUNTER
:SET REF COUNTER
:INCR REF COUNTER
:SET REF COUNTER
+
+
/AO*/REFEN* ROWEN
/A8*/REFEN*/ROWEN
/CO* REFEN* ROWEN
:SELECT LOWER ADDRESS
:SELECT UPPER ADDRESS
:SELECT REFRESH ADDRESS
+
+
/A1*/REFEN* ROWEN
/A9*/REFEN*/ROWEN
/C1* REFEN* ROWEN
:SELECT LOWER ADDRESS
:SELECT UPPER ADDRESS
:SELECT REFRESH ADDRESS
+
+
/A2* /REFEN* ROWEN
/A10*/REFEN*/ROWEN
/C2* REFEN* ROWEN
:SELECT LOWER ADDRESS
:SELECT UPPER ADDRESS
: SELECT REFRESH ADDRESS
+
+
/A3* /REFEN* ROWEN
/A11*/REFEN*/ROWEN
/C3* REFEN* ROWEN
:SEtECT LOWER ADDRESS
:SELECT UPPER ADDRESS
:SELECT REFRESH ADDRESS
+
:+:
+
/C1 :=
+
:+:
+
/C2 :=
+
:+:
+
/C3 :=
+
:+:
+
IF (veC)
IF (veC)
IF (VCC)
IF (veC)
/00
/01
/02
/03
IF (veC) CARRYOUT
=
D
CARRYIN* CO* C1* C2* C3 :CARRY OUT
4-93
64k Dynamic RAM Refresh Controller
FUNCTION
~BLE
AO Al A2 A3 A8 A9 AI0 All COUNT lac REFEN ROWEN ICARRYIN ICARRYOUT
03 02 01 00 C3 C2 Cl CO
J--DATAJAAAAAAAA
11
,32101098
--CARRIES-----CONTROLS--COU I REF ROW
NT oc EN EN
I
I
CARRY CARRY
IN
OUT
3210
CCCC
3210
HHHH
LLLL
HHHH
LLLL
HHHH
LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLH
HHHL
HHHH
XXXX
HHHH
HHHH
HHHH
HHHH
HHHH
LLLL
LLLH
LLHL
LLHH
LHLL.
LHLH
LHHL
LHHH
HLLL
HLLH
BLHL
HLHH
HHLL
HHLH
HHHL
HHHH
ZZZZ
0000
COMMENTS
---------------------.--------------------------------------------------XXXXXXXX
XXXXLLLL
XXXXHHHH
LLLLXXXX
HHHHLLLL
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
i:.
L
L
L
L
C L
C L
X H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
L
H
H
H
H
H
H
H
a
H
H
H
H
H
H
H
H
H
Ii
X
H
H
H
H
H
H
H
H
H
a
H
H
H
H
H
H
H
H
H
H
L
X
SET REF CNTR
UPPER ADDRLOW
UPPER ADDR HI
LOWER ADDR LOW
LOWER ADDR HI
INCR REFADDR
CARRY OUT
TEST HI-Z
------------------------------------------------------------------------DESCRIPTION
TWO IDENTICALLY PROGRAMMED
REFRESH CONTROL FUNCTION.
P~20X4
CAN PERFORM THE 64 k DYNAMIC RAM
EITHER COLUMN OR ROW ADDRESSES'l'O THE RAM ARE· SELECTED DEPENDING
ON ROW ENABLE (ROWEN).
AN ADDRESS COUNTER (C3-CO) IS SELECTED DURING REFRESH WHEN ROW ENABLE
(ROWEN) IS HIGH.
THESE OPERATION'S ARE EXERCISED IN THE FUNCTION TABLE AND SUMMERIZED IN
THE OPERATIONS TABLE:
jac COUNT REFEN ROWEN· 03";00
OPERATION
------~-----------~------------------------------------~--H
L
L
L
L
4·94
X
C
C
C
C
X
L
L
H
H
X
L
H
H
L
Z
AJ-AO
All-A8
C3-CO
H
HI-Z
SELECT LOW ADDR BITS
SELECT UPPER ADDRBITS
SELECT REFRESH ADDR BITS
SET REFRESH COUNTER
Mk Dynamic RAM R.f....h Controller,
64k DYNAMIC
~~
REFRESH CONTROLLER
1 CXXXXXXXX10xoassasSHsSJ1
2 CXXXXOOOOOOXOBLLHBHBLLll
3 Cixxxl11100XOBBBBBBBBBl1
4 COOOOXXXX01xom·LBBBBIJ·11
5 Cl111000001XOSHHHHHHH811
6
7
8
9
10
CXXXXXXXXl1 XOBIJ.ItLLLLLO1
CXXXXXXXXllXOBLLI·LT.BLB01
CXXXXXXXXllXOBLLLLBTStD1
CXXXXXXXXl1XOBLLLLBBBB01
CXXXXXXXXl1XOBLBT.BLLI,Ul1
11 . C:XXXXXXXXl1XOBLBLBLIILB01
12 CXXXXXXXXl1XO BTSIJIBToBTo01·
13 CXXXXXXXXl1XOBToBTiBBBBRP1
14 CXXXXXXXXllXOBBLHLLLLtDl
15 CXXXXXXXXllXOBHLBLL8LB01
16 CXXXXXXXXl1XOBBLBLHLBL01
17 CXXXXXXXXl1XOBBTSI,BBBB01
18 CXXXXXXXXl1XOBBBBBIJ,t,tD1
19 CXXXXXXXXl1XOB8BBBLBLB01
20 CXXXXXXXXllXOBHBHHHlolU.oQl
21 CXXXXXXXXllXOLBBBBBBBS01
22 XXXXXXXXXXXXlXXXZZUxpl
PASS SIMOLA,'l'ION
64k
'D~nami$ R~M.R.fre8h, Controller
64k DYNAMIC RAM REFRESH CONTROLLER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
8
9
10
-x----x
11
16
17
18
19
24
25
26
27
32
33
34
35
40
41
42
43
48
49
50
51
-x--
---x
-x--
---x
---x
---x
---x
--x---x
--x- --x- --x---- ----x----x
64
65
66
67
-x--
/A8*/R:EFEN:*/ROWEN
/CO*REFEN",ROWEN
-x-- x---x-- -x-x--- x---
/A9*/REFEN*/RgwEN
/C1*REFEN*ROWJ!lN·
x--- -x-x--- -x--
/CO
REFEN* /RmfflN.
CARRYIN
REFEN*/ROWEN
x--- -x-x--- -x--
/C1
REFEN* /ROWEN
CARRYIN*CO
REFEN* /ROWEN\
/A1*/REFEN*R~~,
/C2
CARRYIN*CO*C1
REFEN*/ROWEN
x--- -x-..,
x--- -x--
/C3
REFEN*/ROWEN
CARRYIN*CO*C1*C2
REFEN*/ROWEN
-x-- x---x-- -x-x--- x---
/A2*/REFEN*ROWEN
/A10*/REFEN*/ROWEN
/C2*REFEN*ROWEN
-x-- x---x-- -x-- -x----x
x--- x---
/A3*/REFEN*ROWEN
/A11*/REFEN:*/ROWEN
/C3*REFEN*ROWEN
-..,-x
---x
/AO*/REFEN*R~
x--- -x-x--- -x--
--x- --x-
---x
56
57
58
59
72
73
-x..- x---x-- -x-x--- x---
_·x--
---...:
-x--
~EN*/ROWEN
--- ....
---x
LEGEND:
--x- --x- --x- --xX :
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW = 1289
CARRYIN*CO*C1*C2*C3
FUSE BLOWN
(H,P,l)
.I.
64k Dynamic RAM Refresh Controller
Logic Diagram PAL20X4
64k Dynamic RAM Refresh Controller
:OUNT
1
.....
V" •
·,,
I
~
3
. i'
1
.! 1,1'
U 1114 n
1111 t i l t
lOHUll
24 UlI21
U lt10 31
n
ll:M 35
l6lJlI:tt
A2
.··
-ti:.f
11
""1...)-1"
.
.."
1-<,........
......
:tj:l
"
""
...........
~~D-
......
11
..
....
~D~
....
~
..
~-L
"
.
CARRYIN
00
01
~~ co
~
~
C1D
~
::tL~
.....
C2
17
C3
16
02
Q
.J'""\.
"
A:
50
so
9
21
~f9r>tGI] I.J......
51
A10 8
-
~-L
"
7
..J..
"
A3 5
A11
J
. . . ~D:::::::::..
"
A9
22
~~
4
-6
23
..J.
3
."
A8
..J.
.....
I
AO ~
A1
..,..
I6(L
1
~
.
......
...,
u
...L
~r-I
~
~
J
"
10
......
"
.."
.....
"
11
,II)
4'11
111111
UIlI,,'
IIUIIII
HUZlU
Mnun
lIltll3'
l233l1lS
Hl1.31
..J.
J
15
14
03
CARRYOUT
~
4·97
Notes
4-98
State Counter for
Mu Itipl ier/ Divider
State Counter for Multiplier/Divider
Transition Flow Chart Multiplier/Divider
x
/
.;. * Loop 3 times for multiplication.
**loop 6 times for fractional division,
or 7 times for integer division.
PAL16R4'
Stat. Counter Using, PAL 16R.4
for MultipU.rIDivlder
.
CLOCK-~~'"
INSffl~ I-~~'"
(lSB)
}~A~
(MSB)
INSTRUCTION
CODE
0,1,2,3
4
5
5,7
6
7
STARTING STATE
NEXT STATE
0,8,10
0,8,10
0
8, 10
0,8,10
0,8,10
4
5
1
0
1
0
FIgure 1 Transition Table Multiplier/Divider
4 .. 100
State Counter for Multiplier/Divider
PAL16R4
STCNT
S~'l'E COUNTER FOR MULTIPLIER/DIVIDER
PAL DESIGN SPECIFICATION
WILLY VOLDAN 01/27/81
MMI MUNICH GmbH
CLK IO II 12 NC NC NC NC NC GND
/oe 12 13 04 123 122 121 18 19 vec
IF(VCC) /19 =
/I2*/Il*/IO
/l2*/Il* 10
/l2* Il*/lO
/I2* Il* IO
+
+
+
IF (VCC) /18 = 121* 122* 123*/04
+ 121* 122* 123* 04
+ 121*/122* 123*/04
+ /121* 122* 123* 04
+ /121*/122* 123* 04
+ /121*/122* 123*/04
/124
:=
121* 122*/123*/04
+ 121*/122*/123*/04
+ /121*/122* 123* 04* l2* Il*/lO
+ 121* 122*/123* 04
+ /121* 122*/123* 04
+ Q1*/Q2*/Q3* 04
+ /121* 122*/123*/04
/123
:=
+
19* 18
18
*
+ /121* 122* 123* 04*
+ /121*/122* 03* 04*
+ /121*/122* Q3*/04*
+ /121*/122*/123* 04
+ /121*/122*/123*/04
+ /13
/122
:=
+
+
+
+
+
+
/121* 122* 123* 04* 12* Il*/lO
/121*/122*/123* 04
/121*/122*/123*/04
121*/122*/123*/04
/121*/122* 123* 04* 12* Il*/lO
121*/122*/123* 04
/121* 122*/123*/04
/121 :- 121* 122* 123*/04*
+ 121*122* 123* 04*
+ 121*122*123* 04*
+ 121*/122* 123*/04*
+ /121*/122* 123*/04*
+ /121* 122* 123* 04*
+
+
I2*/Il*/lO
l2*/l1* lO
I2*/Il* lO
l2*/l1* IO
l2*Il*/lO·
l2*/Il* lO
12* Il*/IO
12* Il*/IO
12* Il*/lO
12* Il*/lO
* 12*/Il*/lO
18
<;.
.
~,.
~.
,
A
/12
4~101
State Counter ·for Multiplier/Divider
IF(VCC) /13 :=
Ql* Q2*/Q3* Q4
Q2~/23* Q4
+ 21*/22*/Q3* Q4
+ /Ql* Q2*/Q3*/Q4
+ /Ql*
IF(VCC)/l2 ;- /21"" Q2* Q3* Q4""
+ /21*/Q2"" 23* Q4*
+ /Ql*/Q2* Q3*/Q4*
+ /Ql""/Q2*/Q3*/Q4
+ /Ql*/Q2* 23* Q4*
+ /Ql* 22*/Q3* Q4
+ /21* Q2*/Q3""/Q4
12*/Il* IO
12*/Il* IO
12*/Il* IO
12* Il*/IO
FUNCTION TABLE
/OC CLK IO II 12 12 13 18 19
,
,CONTROL
,/cc CLK
INST
III
012
----L
L
L
L
L
L
L
L
L
L
H
C
C
C
C
C
C
BBL
BLB
LBB
BBH
c:
BLB
LBB
BLB
C
C
C
X
XXX
BLB
XXX
xxx
0'
Q3 Q2 21
STATE
1 1 1 1
238 9
QQQQ
XX-XX
XX-X-XX X X X
X X X X
X x.x X
X X X X
LXXX
L L X X
x x XX
X H X X
X X X X
BBBB
4321
COMMENTS
BBBL
BBLL
BBBB
BBHL
BBLL
HLHL
LLBL
LHLH
BBBB
ZZZZ
DISABLED
---------------------------------------------DESCRIPTION
IN MANY SIQUENTIAL CIRCUITS IT IS DESIRABLE TO KNOW THE STATE OF THE
SYSTEM. THIS PAL16R4 APPLICATION IS AN EXAMPLE OF A STATE ,COUNTER FOR
THE MMI SEQUENTIAL MULTIPLIER/DIVIDER.
THE STATES ARE REPRESENTED BY A FOUR BIT COUNTER WHERE Ql IS THE LEAST
SIGNIFICANT BIT AND Q4 IS THE MOST SIGNIFICANT BIT.
THE NEXT-STATE OF THE COUNTER AND THE MULTIPLIER/DIVIDER IS A FUNCTION
THE PRESENT STATE AND THE INSTRUCTION LINES 12-IO. FOR EXAMPLE IF THE
MACHINE IS AT STATE 0 AND THE INSTRUCTION IS 0,,1,2 OR 3 THEN THE NEXT
STATE IS 4 (MULTIPLY INSTRUCTION), IF THE INSTRUCTION ISS (DIVIDE
INSTRUCTION), ETC.
4;'102
State Counter for Multiplier/Divider
STATE COUNTER FOR
1
2
3
4
5
6
7
MDLTIPLIE~DIVIDER
CllOXXXXXXOXXBBBBXXl
Cl01XXXXXXOXXBBBJ:.XX:l
COllXXXXXXOXXBHLLXXl
ClllXXXXXXOXXBBHllXXl
Cl01XXXXXXOXXBBBLXXl
COllXXXXXXOXXBBLLXXl
Cl01XXXXXXO:j:.XBLBtXXl
8 CXXXXXXXXXOLLLLBLXXl
9 CXXXXXXXXXOXXLBLBXXl
10 Cl01XXXXXXOxB8BBBXX1
II XXXXXXXXXXlXXZZZZlOtl.
PASS SIMULATION
STATE COONTER FOR
MDLTIPLI~DIVlI)ER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o - - --- -.-
--~
--- - - - - ---
1 -X- -x- -x- - - ---- -....: .......... --..- /12*/11*/IO
2 X--- -X-- -x-- ---- ---- ---- ---- ---- /I2*/I1*IO
3 ,..X-- x-- -X- ---- - - - - - ..--.. :..-...,- /I2*11 */10
4 x-- x-- -x- ------- - - - - -....: /12*11*10
8
9
10
1.1
12
13
14
~-
------------
- - - - - - - - ---- ~-- - - - ---- -x- -x- -x- ---x --- -:----- -x- --x---x- --x- ------_ ...- :-x- -x -x- ---x--- -...;
- - - -.,;-x --x- -x- --x- - - --- - ---I. ---I. -x---
--x- ---- --
---x ---x --x- ---x ---- ----
Q1*Q2*03*/04"
Q+*Q2*Q3*04
Ql*/Q2*Q3*/Q4
/Ql*<;12 *Q3*04 . ,
/Ql*/Q2*Q3*04
/Ql*/Q2*Q3*/04
x-- x-x- -1.- --X-"":-X - - --.Q1*Q2*Q3*/04*I2*Il*/IO
-x- x-x';'" -x.... -X"" -x- -,...- ---- Ql*Q2*Q3*04*12*/Il.*Ia
x-- x-x- .,;-x- -x... --x... ......:-. - ... Q1*Q2*Q3*04*12~Il*/IO .
19 -x- x--X~X- - x -x- --x _ .. ---- Q1*/Q2~Q3*/04'*I2*Il*/IO
20 -X- x--- X-~x ...,.~x -x- ---x - - "';"--/Q1*/Q2*Q3*/04*12*11*/IO
21-X...,. X - x-x --x- -x- - X - ' - """:-/Q1*Q2*(23*04*I2*11*/10
22 -x-- -XX- x-- ---- - - --- ---- ---- 18*t2~/Il*/IO
16 -X17 x18 -x-
23 ---- ---- ---- ---- - - - --------
---x
';>'(
/12
4-103
State Counter tor Multiplier/Divider .
STATE COUNTER FOR MULTIPLIER/DIVIDER (CONTINUED)
11 1111 1111 2222 2222 2233
0123·4567 8901 2345 6789 0123 4567 8901
24
2S
26
27
28
29
30
-x-- x--- x--x --x- --x---- -,..-- ---x ---x -x
---- - - - --~x -x -x
---- ---- --x- ---x ---x
-x- x--- x--x ---x -x---- ---- --x- ---x ---x
---- ---- ---x --x- --x
32 --x33 -x-34 x--35 x36 x--37 - 38 ---39 ----
--x-XX-x--x--x--
--x- ---- -----x- ---- ------x ---- ----x ----
-x- -----x- - ---x ----
--------x-x--x-
---- ---- - -----x- -----x- ..:...--x ---- I --x- - -
/Q1*Q2*Q3*Q4*I2*I1*/IO
/Q1*/Q2*/Q3*Q4
/Q1*/Q2*/Q3*/Q4
---- Q1*/Q2*/Q3*/Q4
-~- /Q1*/Q2*Q3*Q4*I2*I1*/IO ..
---- Q1*/Q2*/Q3*Q4
---- /Q1*Q2*/Q3*/Q4
---x-x-x
x--x
x--x
---x
------x---x
-x
-x
--x-
--1- --~I - I ---- - - Q1*Q2*'/Q3*'/Q4
---I -x - - - - Q1*/Q2*/Q3*/Q4
------ ---x ---I ---x -x
---- - - - - - - - - -
----------------
19*18
18*I2*/I1*/IO
/Q1*Q2*Q3*Q4*I2*/I1*IO
/Q1*/Q2*Q3*Q4*I2*/I1*IO
/Q1*/Q2*Q3*/Q4*I2*/I1*IO
/Q1*/Q2*/Q3*Q4
/Q1*/Q2*/Q3*/Q4
--- -----x ---- /13
40
41
42
43
44
45
46
- - ----- ---
48
49
50
51
52
-------------
56
57
58
59
60
61
62
63
---- ---- ---- ---- ---- ---- - - - ----
--x- --x
-x-- x--- x--x -x --x- --x- ---- ------- - - --x- --x- -x --x- --- -.---- ------- ---- - ----
--x -x- -x --x-
--x- --.:.x ---x --x---x --x- ---x ---x
/Q1*/Q2*Q3*Q4*I2*I1*/IO
Q1*Q2*/Q3*Q4
---- ---~ /Q1*Q2*/Q3*Q4
.;.;..------ Q1*/Q2*/Q3*Q4
---- ---- /Q1*Q2*/Q3*/Q4
---- ---- ---- - - - ---- ---- ------- --x- --x- ---x -x- ---- _-- Q1*Q2*/Q3*Q4
---- ---x --x- ---x --x- ---- ---- /Q1*Q2*/Q3*Q4
---- --x- ---x ---x -x- ---- ---- Q1*/Q2*/Q3*Q4
---- ---x --x- ---x ---x ---~ ---- /Q1*Q2*/Q3*/Q4
x--- -x-- x--x --x- --x- --x- ---- ---x--- -x-- x--x ---x --xx--- -x-- x--x --x --x---- ----
---x ---x ---x
---x --x- ---x
---x --x- ---x
-x-- x--- x--x ---x --x---- ------- ----
LEGEND:
x:
--,;,.- --'--
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN
4·104
/Q1*Q2*Q3*Q4*I2*/I1*IO
/Q1*/Q2*Q3*Q4*I2*/I1*IO
--"'-X -------- /Q1*/Q2*Q3*/Q4*I2*/I1*IO
--x--,..- ,..-"- /Q1*/Q2*/Q3*/Q4
--x- ---- ---- /Q1*/Q2*Q3*Q4*I2*Il*iIO
--x- :"~-... ---:- /Q1*Q2*/Q3*Q4
,..--x -.. .--: ---- /Q1*Q2*/Q3*/Q4
,..~x-
= 1520
- : FUSE BLOWN
(H,P,l)
State Counter for Multiplier/Divider
State Counter for Multiplier/Divider
ClK
Logic Diagram PAL16R4
I
0123
45& 7
891011
12131415
1611181920212223
24252621
28293031
0
,
~.
1
J
•
19
5
10
2
.
..
7
....
~
~I---
,,
:r--J
10
11
"
""
13
11
3
...
17
..
NC
...
D
./
~
...
"
""
""
"
j
J1
....
JJ
"
lS
j
36
J7
38
NC
6
~
39
.....
...
...
""
"
"
"
"
..
NC
7
....
""'"
./
....
...
..
:r--J
50
""
'3
54
NC
8
...
0-
E:...!~
-'"
"
"
.
18
r-~ 01
"-
""
""
27
28
5
18
.....1---
.""
12 ~
19
•
~
~
02
~
03
~
tQ] ~
04
13
13
12
12
55
....
JIO.t-51
>-t1
"
51
51
..
"
"
11
NC
..
9 ...
'--1
...
JIC..t-o, 1
.
2 3
4 5 6 7
1"011
12131415
16\1181,
20212223
24252621
21293031
~ oc
4·105
Notes
ALU/ Accumulator
PAL16A4
vee
BO 4
DATA.
IN
{
in.
,17 : : } DATA
B2
l+I''ot-ti)ool
A2
B3
.......................
A3
OUT
~
~
ALUI Accumulator
PAL16A4
ALU
ALU/ACCUMULATOR
MMI SUNNYVALE, CALIFORNIA
CLK 10 11 eo ~1 B2 B3 12 13 GND
/oe LIO /p A3 A2 Al AO /G cm vee
CARRYO.EQU
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/15/81
/I3*/I2*/I1*/IO * CIN
CARRY1 • EQU /13* /I2 */ll */10* (AO *BO)
. + It3"/I2*/ll*/IO * (AO+BQ) .CIN
CARRY2 .EQU
/I3*/I2*/I1*/IO * (Al*B1)
+ /I3*/I2*/I1*/IO * (Al+~l)*(AO*BO)
+ /I3*/t2*/I1*/IO * (Al+B1)*(AO+BO)*CIN
CARRY3 .EQU
, +
+
+
/I3*/I2*/I1*/IO'"
/I3*/I2*/ll*/IO *
/I3*/I2*/I1*/IO *
/Ij*/I2*/I1*/IO *
(A2·*B2)
(A2+B2) (Al*B1)
*
(~+~2J*(Al+:Bl) * (AO*BO)
CA2+B2)
* (A.l.+Sl)
* (AO*BO). *CIN
'
."
."
"
/AO :+
+
+
:+:
+
+
+
IIj* /12* III *IIO* (AO: * :BO)
/I3*/I2* IO*(lAO)·
II3*/12* Il*(~O)
113* 12*/I1*/IO*(BO)
II3* ;I2*/ll* IO* (lAO*,lBO)
/I3* 12* I1*/Io*/cm
/I3* 12* Il* IO*(lAl)
<[3*(/AO)
CARRYO·
+:
I.AO OR eo
, SHIFT LEFT AO
,SHIF'l!. RIGHT AO
~,BOx.o AO (LSB)
,AO PLUS BO .PLUS 1
/Al Ie /I3*/I2*/I1*/IO*(Al:*IB1)
+ /I3*/I2* IO*(/Al)
+ /I3*/I2* I1*(~1)
+ /I3* 12*/I1*/IO*(B1)
:+: /13* 12*/I1* IO*(/Al*~l)
+ /I3* 12* I1*/IO*(/AO)
+ /I3* I2* Il* IO*(lA2)
+
13*(lAl)
+
CARRY1
;Al PLUS B1
;BOLD Al
(Al AND)
,LOAD B1
( B1 )
,LOAD ~1
;Al OR B1
; SHIFT LEFT Al
; SaIFT RIGHT Al
;HOLD Al
,Al PLUS B1 PLUS 1
/A2 := /I3*/I2*/I1*/IO*(A2:*:B2)
+ /I3*/I2* IO*(/~)
+ /I3*/I2* Il*(~2)
+ /I3* 12*/I1*/IO*(82)
:+: /I3* 12*/I1* IO*(/A2*~2)
+ /I3* 12* I1*/IO*(/Al)
+ /I3* 12* I1* IO*(/A3)
+ 13*(lA2)
+
CARRY2
;A2 PLUS B2
;HOLD A2
(A2 AND)
( B2
)
;LOAD B2
;LOAD ~2
;A2 OR B2
; SHIFT LEFT A2
; SHIFT RIGHT A2
;BOLD A2
;A2. PLUS B2 PLUS 1
iAO PLUS eo
,HOLD AO
eAO AND)
(
,LO~BO
eo )
;LOAD/BO
ALUI Accumulator
/113 :=
+
+
+
:+:
+
+
+
+
/I3*/I2*/I1*/IO*(A3:*:B3)
/I3*/I2* IO*(/A3)
/I3*/I2* I1*(/83)
/I3* 12*/I1*/IO*(BJ)
/I3* 12*/I1* IO*(/A3*/83)
/I3* 12* Il*/IO*(/A2)
/I3* 12* I1* IO*/LIO
13* (/113)
CARRY3
IF(VCC)
G ..
+
+
+
/I3*/I2*/I1*/IO
/I3*/I2*/I1*/IO
/I3*/I2*/I1*/IO
/I3*/I2*/Il*/IO
*
*
*
*
IF (VCC)
P ..
+
+
+
+
+
+
/I3*/I2*/I1*/IO
/I3*/I2*/Il* IO
/I3*/I2* I1*/IO
/I3*/I2* I1* IO
/I3* 12*/Il* 10
/I3* 12* I1*/IO
/I3* 12* 11* IO
*
*
*
*
*
*
*
,113 PLUS BJ
(113 AND)
,BOLD 113
(
,LOAD B3
B3 )
,LOAD /83
,113 OR B3
, SHIP"l' LEFT 113
, SHIFT RIGHT 113
,BOLD 113 (MSB)
,113 PLUS BJ PLUS 1
(A3*BJ)
(A3+B3)*(A2*B2)
(A3+B3)*(A2+B2)*(Al*B1)
(A3+B3) * (A2+B2) * (Al+B1) * (AO*BO)
(A3+B3) * (A2+B2) * (Al+B1) * (AO+BO)
(/113) *(/A2) *(/Al) * (/AO)
(/83)*(/B2)*(/81)*(/BO)
(/113+/83) * (/A2+/82) * (/Al+/B1) * (/AO+/BO)
(/113*/83) * (/A2*/82) * (/Al*/B1) *.(JAO*/BO)
(/A2)*(/Al)*(/AO)*/CIN
/LIO*(/A3)*(/A2)*(/Al)
IF (/I3* 12* I1*/IO) /LIO • (/113)
; SHIFT LEFT OUT
IF (/I3* 12* I1* IO) /CIN" (/AO)
;SHIFT RIGHT OUT
DESCRIPTION
THE ALU ACCUMOLATOR LGADS THE A-REGISTER WITH ONE OF EIGHT OPERANDS ON
THE RISING EDGE OF THE CLOCK. G AND P OUTPUT GENERATE AND. PROpAGATE
ON THE ADD INSTRUCTION. P OUTPUTS OP .. ZERO ON INSTRUCTIONS 1,.2.3,~, 6 .7.
OPERATIONS TABLE.:
/OC CLK
13
12
Il
10
LIO
CIN 1I3-AO
OPERATION
---~----------------------------------------------------------------------~--H
X
Z
X
X
X
X
X
X
HI-Z
A =Z
L
C L L L L
X
ADD
A;=A PLUS B
L A PLUS B
L
X
H A PL B PL 1 ADD
C L L L L
A:=A PLUS B PLUS 1
C
X
L
L L L H
A
HOLD
X
A:=A
L
C
L L H L
X
LOAD
X
A:=B
B
L
C L L H H
X
X A AND B
AND
A: "'A*B
L
C L H L L
X
x /8
LOAD COMP
A:=/8
L
X
C L H L H
X
A OR B
OR
A:"A+B
L
C
X
L H H L
SHIFT LEFT
LI St.;.(A)
L
C
RI
L H H B
x SR(A)
SHIP"l' RIGHT
L
X
C
H X
A
X
X
X
BOLD
A:=A'
------------------------------------------------------------------------------
4-108
ALUI Accumulator
ALU/ACCUMUIATOR
J..1 '1111 1111 2222.' 2222 2233
0123 4567 8901 2345 6789 0123 4561 8901
o x--- x--- ---- ---- ---- ---- x--- -x-- /I3*X2*Il*10
1 - - - ---- xx-- ---- ---- --- ---- ---~/AO
8
9 -x-- -x------ ---- ---- x-xx -x-- -x~ /13*/12*/Il*/10*Al*B3
10 -x-- -x~- ---- ---- x-xx -x-~x-- -X~/13*/12*/11*/10*Al+B3*A2*B2
11 -x-- ~x-- ---- x-xx -x- --x- -x- -x-- /13*/12*/11*/10*Al+B3*A2+B2*Al~
12 -x-- -x-- x-xx ~x- ~-x- -x- -x-- ":x- /13*/12*/Il*/ttl*A3+B3*A2+B2*Al16 ..;.x-- -x-- x--x --- ---- ...---,.,x-- -x-"; /13*/12*/Il*/10*AO:*:BO
17 x--- ..;.--- xx-- ---- ---- -",,---x--x~ /13*/12*10*/AO
18. --- x--- -x-x - ... - -~-- ---_ -x..;.- -x-- /13 */12 *Il*/BO
19 -x-- -x~-x-x- ~--- -:-'-----~x-- ~x~- /I3*12*/Il*/10*BO
20 x--- -x-- xx-x ---- ---- ;;.--- x--- -X-. /13*12*/Il*10*/AO*/BO
21 -x-x x--- ---- .....;.-- --- ---~ x--..;. ~x-- /13*12*Il*/10*/C1N
22 x--- x--- --~-·xx~- --,..- -~-- x--- -x-- /I3*12*Il*10*)Al
23 --- ---.., xx-- ;..·-7---- ~-"'":~--- x-- 13*/AQ
24 -x-- -x-- --- x--x --~- ---_ -x-- -x-- /13*/12*/Il*/10*Al:*:B1
25 x--- ---- -~:-- .xx""'- ---- -,..-- '~x- -x- /13*/12*10*/Al
26 --- x-----_- -x-x - ... ---~-- -x-- -x-- /13*/12*11*181
27 -x-- -x-- ---- x-x- ---- ---- 'x- -x-- /13*12*/Il*/10*B1
28 x--- -x-- ---- xx-x -,.;.-- ----x-- -x- /13*12*/Il*10*/Al*/B1
29 -x-- x--- xx- --- ---- ---- x----x- /13*12*Il*/10*/AO
30 x--- X...-- ---- ,..--- xx- ---- x--- ~x- /13*12*11*10*/A2
31 --- ---- ---- xx- -..;-- ---- '---- ~--13*/Al
'
32-X- -x-- -"--- --~- x--x --:-- ~x- -x-- /13*/I2*/Il*/10*A2:*:B2
33 x--- ---- -------..;.xx_-.-.:.-""'·~x-- -X-./13*/12*10*/A2
34 --- x--- ---- --,.. ";x":';X-",,---X---X..,-/13*/12*1l*/B2
35-X-- -x- ---- ..;...:~- X....lC..; ---- x..;...- -x-- /I3*12*/Il*/10*B2
36 x--- -x-- --------xx-X ...... -- x-~~ -X~ /13*12*/Il*10*/A2*/B2
37 -x-- x--- ---- xx-- --,...- ;..--.., x.~- -x- /13*12*Il*/10*/Al
38 x--"'x--- ""'--- ---- ----. xx-- x--- -x-- /13*12*11*10*/Al
39. ..,----------- ----xx;.."'" ...""'-- ---- x~- '13*/A2
40 -x-- -x-- --- ---- ---,.. x~x -x-... ~x-- /13~/12*/:i:1*/1()*Al:*:B3
41X--- - .. -- ---- --;.."'- -~~.:.. xx-- -x:'- ,..x-- /13*/r2*10*/Al
...
42 ---- x--- -----:_:-- -----x~x -x..._· -X-- /13V;12*U*/B3
43 -x-- -x-.- ---~ --- - ...";'~ x-x- x--~ ,..x.,.- !13*12*/Il*/I0*B3
44 x--- -x-- ..:.---------- xx-xx~...--x-,- /13*12*/Il*10*/Al*/B3
45 ... x--x--- ---- ----:KlC-- -~--:- X-- -X-- /13*12*U*/10*/A2
.
46 x--- x--- ;..-..;.- ---- ...--,..:---- x----x-x /13*12*Il*IO*/L10
, 47 ---- ---- ---- ---- :';..;,..- xx.,..,..
,.....,"'--' .x-.,."" .13'"/Al
'.
.
" . ' :,. ' .'
,
:','..
'.
4.8 --- ---- ---- ---- '-~-- -..;.-- -~-" ---49 -x__ , -x-- -x- -x- --x- --X;-:-x__ .,.x-~ /I3'VI2~/Il*/10*Al+B3*A2+B2*Al'"
50 X--, -X-- xx- xx-- XX--lCX-- ...X:--:O ....x-- /13*/I2*/Il*10*/A3*/A2*/Al*/AO "
51 -x-x--- -x-x -x-x:-X.:.X .... x,..x-x~fX-- /I3*/12*Il*/XO*/B3*/B2*/B1~~/B0
52 x--- x----x-- -x-,..' ... x--,..x-..,-x--..,.X.....;/I3*/'12*1l*IO*/A3+/B3./A2+~*53 x-':" -x-- xx-x ,xx-x xx..:X, lCx;-:x x--,-x-- /13*I2*/Il*XO*/A3*/83*/A2*;B2*.. 54 -x-x X--- xx-xx-- xx-... ---_X-·-.
/13*12*Il*/10*/A2*/Al*/AO*/C1N'
55 x--x--- --- xx-- xx.,.;- XX~x-..,... ""'x-x /I3*12*n*10*/LIO*/A3*/A2*/Al
56 -x__ x--- ---- :----~-- :--:0-:' X--- .,.X;"'" /13*12*I1*/1P
57 ~------ ---- -----... --xx:--:o------'- fAl
LEGEND: x: FUSE NOT BLOWN (L,N,O), _: FUSE Bt.owN
(:S~P,l)
NUMBER OF FUSES BLOWN =1270
.
...x-
ALUI Accumulator
Logic Diagram PAL 16A4
ALUI Accumulator
(} 1 2 3
4
~
6'
8 9 1011
12 13 14
1~
,1) 1118 19
2(J 21 2223
24
Z~
26
n
28293031
~>c>-.-l------_----'-'19
10
2
CIN
....
...
8
9
\D
"
"')
~-+-i
_ _ _ _ _....!!'8 G
14
11
3
"
""
....
18
19
20
11
21
13
18
19
30
)1
t~
........
J1
)D-~~~
3J
)4
11
)6
3J
38
39
B2'
~
iil====I=lli. .~f)D-fi~~
~
7
B3~
............. ·lE
.1'1
',0
'"
12
8
13
9
.
.. ~
1\.'
I
\',
iJ
I
H 'I lUll
1) 111·11'\
IblllH 1'1
)O!llll3
J.1!',!IJlI
"Kil'I.lU.ll
4-111
Notes
4.112
Stepper Motor Controller
PAL16R4
vee
01A
Q3A
OOA
OOB
Q2ii
03B
4-113
D
Stepper Motor Controller
Functional Description
Stepper motors and linear actuators are used in a variety of
applications requiring precise rotational and/or linear movement. Examples are printers, floppy disc drives, mechanical
valves, etc. Stepper motors. are two-phase permanent magnet
motors which provide discrete angular movement every time the
polarity of a winding is changed. In the case of linear actuators,
the angular movement is converted to a linear movement via a
load screw. In essence, they are dc motors without brushes,
where the user provides commutation with external logic'
v'--+---<'---+---+--'
Circuit Operation
One type of drive circuit, unipolar drive, is shown in Figure 1
below. Two drive sequences are given in Tables 1A and 1B.
Angular rotation is achieved by saturating the transistor drivers
in the sequence shown in the appropriate table (full or half step).
Now, assume the circuit of Figure 1 is connected to a stepper
motor deSigned for 7.5 0 steps. By following the step sequence
of Table 1A (full step), the shaft will rotate 7.5 0 each time the
state is changed. If the sequence of Table 1B is followed, a 3.75 0
(half step) rotation will result for each change of state. For both
step sequences, the direction can be reversed by stepping
backwards through the table (step 4-3-2-1-4-etc.).
Figure 1
Table 1A
FULL STEP SEQUENCE
CLOCKWISE
ROTATION
tI
Q2
Q3
0
1
0
0
0
1
0
1
1
0
1
1
0
1
0
1
0
STEP
QO
Q1
1
1
2
1
3
0
4
1
.....
1
COUNTER·
CLOCKWISE
ROTATION
Table 18
HALF STEP SEQUENCE
CLOCKWISE
ROTATION
tI
STEP
QO
Q1
Q2
Q3
1
1
0
1
0
2
1
0
0
0
3
1
0
0
1
4
0
0
0
1
5
0
1
0
1
6
0
1
0
0
7
0
1
1
0
8
1
0
0
1
0
1
0
1
0
1
COUNTERCLOCKWISE
ROTATION
PAL Implementation
In this application, one PAL16R4 can be used to provide the
logic levels required to drive two stepper motors in the full
step mode. Due to the high current drive required (100-400
mA/phase), external inverting high current buffers would be
used (ULN 2001 or equivalent). In the design, the following
features are provided within the PAL:
4.114
• Enable/Disable inputs to enable stepping of either section. (IE
inputs).
• Select clockwise or counter-clockwise rotation.
• Set the motor to logic state step 1.
A block diagram/pinout is shown in Figure 2.
Stepper Motor Controller
MOTOR A
VCC
MOTOR A
CONTROLS
~--~+-~----VCC
MOTOR B
CONTROLS
MOTOR B
~----+-------vcc
Figure 2
A function table for each motor control section is given below.
CLOCK
E1
E2
X
X
1
X
X
1
S
X
X
f
0
0
f
0
f
0
0
FUNCTION
Hold motor in current position
Hold motor in current position
1
X
X
X
0
0
0
Step motor clockwise
0
0
1
Step motor counter-clockwise
Set outputs to step 1 levels
The full step sequence (Table 1A) can be simplified from
4 outputs to 2 outputs since 01 ~ 00 and 03 = 02. The
sequences can then be expressed as follows:
0=1
0=0
STEP
00
02
00
02
01 = 00
03 = 02
1
1
1
1
1
when S = 1:
2
3
4
1
0
0
1
00 = 1 01 = 0
0
0
0
0
when E1 = 1 or E2 = 1
0
1
1
0
00.= qO
1
1
1
1
1
01 = q1
02 = 1 03 = 0
02 = q2
03= q3
4-115
Stepper Motor Controller
The step sequences can be converted to equations by use of a
Karnaugh map.
1
0
0
Conclusion
Although this example could be used "as is" in a stepper motor
application, the programmability of PAL's could allow for any
desired modifications. Changes to the circuit might include:
1. Drive only one stepper motor, using a PAL 16R6. The other
flip-flops could be used as a programmable counter, allowing
for different speed settings.
1
2. Drive only one stepper motor, using the extra inputs and
outputs to handle other circuit functions.
1
0
1
3. Drive only one stepper motor, using a PAL 16R6. The other
flip-flops could be used as a 4-bif position counter.
0
4. The substitution of a PAL 16R8, and another inverting buffer
would allow the driving and control of four stepper motors.
--.-o
5. Re-program for half-step operation.
00 = 02 . D + 02 . D
.----..
QO
o
--.-o
02 = 00 • D + 00 . [5
Factor in E1 and E2:
OO=~·~·~·5+~·~·~·~
02 =
E1 . ~ . 00
• D +
Ei .
E2 . 00 • [5
Express the set function as an equation:
00 = E1 . E2 • S
02 =
E1 . E2 .
S
Express the hold function (when E1 or E2 = 1)
00 = qO . E1 + qO . E2
02 = q2 . E1 + q2 • E2
Combining all the above:
00 :=
E1 . E2
. S + 00 . E1 + 00 . ~ + Ei
.
E2 . 02 . [5 + E1 . E2 . 02 . D
E1 .
E2 . 00 . D + E1 . E2 . 00' ~
01 := 00
02 :=
E1 . E2
03 := 02
. S + 02 . E1 + 02 . E2 +
Stepper Motor Controller
PAL16R4
SMC
STEPPER MOTOR CONTROLLER
DEVOE COMPANY, INDIANAPOLIS, INDIANA
eLK /ElA /E2A SA DA /ElB /E2B SB DB GND
/oe /Q3B /QlB /Q2B /QOB /Q2A /QOA /Q3A /QlA
QOA : =
QOA* /ElA
+ QOA*/E2A
+
SA * ElA* E2A
E2~* DA
Q2A* ElA* E2A*/DA
+ /Q2A* ElA*
+
~ HOLD
, HOLD
~ STEP
; LOAD
.~ LOAD
PAL DESIGN SPECIFICATION
DAVE SACKETT 02/23/81
vec
IF NOT E1
IF NOT E2
1 IF SET
/Q2A IF COUNTER-CLOCKWISE
Q2A IF CLOCKWISE
IF (vee) QlA = /QOA
Q2A :.
Q2A* /ElA
+ Q2A*/E2A
+
+
SA * ElA* E2A
QOA* ElA* E2A* DA
+ /QOA* ElA* E2A*/DA
IF (vee) Q3A
QOB : =
+
+
+
+
; BoLD IF NOT E1
,BOLD IF NOT E2
. ,STEP 1 IF SET
. ; LOAD QOA IF COUNTER-CLOCKWISE
~LOAD/QOA IF CtocKWISE
= /Q2A
QOB* /ElB
QOB*/E2B
SB * ElB* E2B
/Q2B* ElB* E2B* DB
Q2B* ElB* E2B*/DB
~ BOLD
IF NOT El
IF N:OT E2
,STEP 1 IF SET
,LOAD /Q2B IF COUNTER-CLOCKWISE
;LOAD Q2B IF. CLOCKWISE
~ BOLD
IF (vee) Q1B = /QOB
Q2B .:=
Q2B*/ElB
Q2B*/E2B
SB * ElB* E2B
+ QOB* ElB* E2B* DB
+ /QOB* E1B* E2B*/DB
+
+
; HOLD
;HOLD
; STEP
; LOAD
;LOAD
IF NOT El
IF .NOT E2
1 IF SET
QOB IF COUNTER-CLOCKWISE
/QOB IF CLOCKWISE
IF (vee) Q3B = /Q2B
4·117
Stepper Motor Controller
FUNCTION TABLE
CLK
loe
iCBIP
iC
I
iL
iK
0
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
/ELA /E2A SA DA QOA QLAQ2A Q3A IElB IE2B SB DB QOB QlB Q2B Q3B
STEPPER MOTOR A
CONTROL STEP
E E S D QQQQ
1 2 A A 0123
STEPPER MOTOR B
CONTROL STEP
E E S D QQQQ
1 2 A A 0123
COMMENTS
----------------------------------------------------------------SET TO STEP 1
L L a x HLHL
L L a x HLHL
a a
L L
L L
L L
L L
L L
L L
L L
H L
La
L H
x
L
L
L
L
L
L
L
L
L
a
x
L
L
L
L
L
L
a
H
H
a
HLHL
a
L
L
L
L
L
L
L
H
L
L
HLLa
LHLH
LHHL
HLHL
HLLB
LeLa
HLLa
HLLa
HLLa
HLLa
a
L
L
L
L
L
L
L
L
H
.H
x
L
L
L
L
L
L
L
L
L
a
x
a
a
a
a
a
a
L
L
L
L
HLHL
LHHL
LHLH
HLLH
HLHL
LHHL
LHLa
LHHL
LHHL
LHHL
LHHL
HOLD
STEP
STEP
STEP
STEP
STEP
STEP
STEP
aOLD
HOLD
HOLD
A
A
A
A
A
A
A
CW, BCCW
CW, BCCW
CW, BCCW
CW, BCCW
CW, BCCW
CW, BCCW
CCW, BCW
----------------------------------------------------------------DESCRIPTION
THIS PAL16R4 PROVIDES THE LOGIC LEVELS REQUIRED TO DRIVE 'mO STEPPER MOTORS
IN THE FOLL STEP MODE.
THE FOLLOWING OPERATIONS MAY BE PERFORMED FOR EACH STEPPER MOTOR CONTROLLER
INDIVIDUALLY:
CLK
/El
IE2
S
D
OPERATION
X
C
C
C
X
L
L
L
H
L
L
L
X
H
L
L
X
X
L
H
HOLD MOTOR IN CURRENT POSITION
SET OUTPUTS TO STEP 1 LEVELS
STEP MOTOR CLOCKWISE
STEP MOTOR COUNTER-CLOCKWISE
---------------------------------------------------------X
a
x
x
X
HOLD MOTOR IN CURRENT POSITION
----------------------------------------------------------
Stepper Motor Controller
STEPPER r«>'l'OR CONTROLLER
1
2
3
4
5
6
7
8
9
10
11
12
C001X001XXOBBLLLLBB1
C11XX11XXXOBBTJ.T.T.BB1
C00000001XOHLLBBLLB1
C00000001XOLLBBBBLL1
C00000001XOLSBLLBBL1
C00000001XOBBLLLLBB1
C00000001XOBLI·BBt.t.R1
C00000001XOI,I·B1DUITJ.1
C00010000xom,x,BBtJ.1U
C10011000xom,LS'JUJ ,1I1
C01010100Xorrr.r,m,x,1I1.
C01110110xOBLLBBLLBl
PASS SIMULATION
4·11:9
'·'stepper 'Motor' ContrOller
STEPPER MOTOR CONTROLLER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
0
1
0,"
-x-
/QOA
8
9
-x-
16
17
18
19
20
x---
--x
x-- --x
-x-- -x-- x--x-- -x-x-x-x-- -x-x-x
QOA*/ElA
QOA*/E2A
SA*ElA*E2A
/Q2A*ElA*E2A*DA
Q2A*ElA*E2A*/DA
24
25
26
27
28
x---
Q2A*/ElA
Q2A*/E2A
SA*ElA*E2A
QOA*ElA*E2A*DA
/QOA*ElA*E2A*/DA
/Q2A
,',"
--x --x-----x ---x- -x-- x-x-- -x-- ---x x---x-- -x-- --x- -x--
32
33
34
35
36
x--x
--x x---x-- -x-- x---
-x-- -xxx---x-- -x-x ---- -x--
QOB*/E1B
QOB*/E2B
SB*ElB*E2B
/Q2B*ElB*E2B*DB
Q2B*ElB*E2B*/DB
40
,x--- --x ----
x-x ----x- -x-- x---x-x -x-x---xx- -x--x--
Q2B*/ElB
Q2B*/E2B
SB*E1B*E2B
QOB*ElB*E2B*DB
/QOB*E1B*E2B*/DB
--x-
/QOB
41
42
43
44
--~-
48
49
56
57
LEGEND:
-xx: FUSE OOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN.
832
/Q2B
- : FUSE BLOWN
(H,P,l)
Stepper Motor Controller
Logic Diagram PAL16R4
Stepper Motor Controller
eLK 1
,,
o
I 2 J
4 S 61
89 Hili
121J141f1
16111819
2U21 2223
24252621
28293031
~
2
J
,,
3
..
•,
.A
~
~
•,
~
""
""
"
12
3
....
~
"""
""
.
11:
"
"
"
""
~
~~~
r-o
./
28
, ...
..
22
13
24
25
26
DA
~r-~
"'"
./
21
4
18
...1---
---t.
SA
19
..'"
Q~
~1
J2
JJ
~
""
"
""
~
./
J1
6
...
...
..
'"
"
"""
""-
.
7
...
./
""
"
....
...
-'--I
..
41
r-J
to
"
""
"
54
SB
.
:r-J
"
"
51
to
....
~
~
~
~
~
13
1------
8
•
-'--I
58
DB
~
"
""
012l
4561
'91011121314151811111'
20212223
24252627
28293031
...
12
11
•• 1~1
Shaft Encoder
PAL16R4
vee
DOWN
Q1
Q3
Qi
ERROR
He
4-123
Shaft Encoder
PAL16R4
SBEN
SHAFT ENCODER
MMI MUNICa Gmba
CLK SIGNALA SIGNALS NC NC NC NC NC NC GND
/oe NC ERROR /04 /Q3 /Q2 /Q1 DOWN UP vec
IF(VCC)
PAL DESIGN SPECIFICATION
WILLY VOLDAN 03/03/81
Q1*/Q2*/SIGNALB
/up.
+ /Q1* Q2* SIGNALB
+ Q3*/04* SIGNALA
+ /Q3* O4*/SIGNALA
IF(VCC) /DOWN -
Q1*/Q2* SIGNALS
+ /Q1* Q2*/SIGNALB
+ Q3*/04*/SIGNALA
+ /Q3* 04* SIGNALA
Q1 : -SIGNALA
122 :- 121
123 :- SIGNALS
04 :- 123
IP(VCC) /ERROR • /Q1* 122 */Q3 * 04
+ /121*122* Q3*/Q4
+ Q1*/Q2*/Q3* 04
+ Q1*/Q2* 123*/04
FUNCTION TABLE
/oe
CLK SIGNALA SIGNALS ERROR 04 Q3 122 121 DOWN UP
;
;/OC
CLK
SIGNAL
A B
QQQQ
ERROR
4321
DOWN
UP
XLLa
XBBL
XBLB
XLBL
LBXB
BLXL
LBXL
B
B
L
L
L
L
B
B
B
B
L
L
L
L
X
X
B
B
COMMENTS
--------------------------------------------------------L
B L
B
L
L
L
L
t
L
L
L
L
a
C
C
C
C
C
C
C
C
C
C
x
L
B
B
B
L
L
L
a
L
B
B
B
B
B
L
L
B
B
L
a
a
L
L
B
L
B
x x
a
x
BLXB
LBBL
BLLB
zzzz
x
X
X
X
COUNT UP
COUNT UP
COUNT DOWN
COUNT DOWN
COUNT UP
COUNT UP
COUNT DOWN
COUNT DOWN
ERROR FLAG
ERROR FLAG
DISABLED
---------------------------------------------------------
Shaft Encoder
DESCRIPTION
THE PAL CONTBOLS A 4-BIT UP/DOWN COUNTER WITH THE OUTPUTS "UP" AND
"DOWN". (UP=H MEANS COUNT UP, DOWN=H MEANS COUNT DOWN)
THIS DESIGN WITH GLITCHLESS OUTPUTS WILL SERVE WELL IN ELECTRICALLY
NOISY INDUSTRIAL ENVIRONMENTS.
THE PINNING AND THE OUTPUT POLARITY ARE GIVEN AS A FIRST PROPOSAL AND
CAN BE CHANGED ACCORDING TO THE PC BOARD LAYOUT.
BLOCK DIAGRAM:
A
B
/UP
PAL16R4
/DOWN
/UP
/DOWN
4-BIT
UP/DOWN
COUNTER
SENSOR, L -_ _ _ _ _- - '
DIGIPOT
OR SIMILAR
CARRY
BORROW
SIGNALS TO ADDITIONAL
COUNTERS
SHAFT ENCODER
1
2
3
4
5
6
7
8
9
10
11
C10 XXXXXXXOXBXBBLHL1
C01XXXXXXXOxmtLLlmLl
C11XXXXXXXOXHXLHLLH1
COOXXXXXXXOXHXBLHLHl
CllXXXXXXXOXHBLXLHLl
COOXXXXXXXOXHLHXBHLl.
C01XXXXXXXOXHBLXHLHl
C10XXXXXXXOXBLHXLLHl
C01XXXXXXXOXLHLLHXXl.
ClOxxxxXXXOXLLHHLXX1
XXXXXXXXXXlXXZZZZXXl
PASS SIMULATION
4;"125
Shaft Encoder
SHAFT EN---J
1G
11
11
13
"
18
DOWN
15
SIGNAlB
3
....
..
.A
"'16
17
""
~~
of--
""
1G
11
21
D
13
NC
4
...
"
"
~D
;::::;::
-O-L
4
S
=R::!9D
5
;:::~
::{j:::t
~
....,
""
6
~
.
~D
".,
.,
04
::t):l
7
~
..
...
05
8
-Q-l
IDD
..
."
"'"
~D
56
"
06
9
~
.
00
07 ~~
~
~
... 0 3 B
~
I;J.
~
~
~
r;J.
...
·18
~
16
I'"
~
-
"
11
~
~ 02
'""'
"
"
"
~
~ 01
IDI>~ ~
.
"
"
11
.....
~D
"
"
03
llRO
3
"
"
"
"
02
J
R:!9D t;~
"
"
"
01
23
.··
"
DO
...l.
-M-,
.,.
....
.~
II
1
Z 1
4
S
6
J
. , 11111
12131415
1117" '9
201122 2J
24IS2&11
11 It 30 31
12 lJ 34-35
)6113131
.
.A..
14
04
05
06
07
RllO
13
'"
4·159
Octal Shift Register
App'ieation
16-8it Shift Register
BOS OUT ENABLE
L SB 110
{ ClK
10
11
INSTR
lS-BIT
DATA BUS
IN
IS-BIT
0 ATA BUS
OUT
1
24
r-o:~tEI
-{1
~ I r-IID'22
r:' f--IO lIRO, I-DO
OO,~
Ll
all--
:::;: f-- 01
IT f-r:"
a.!,1-c-
02
~
021--l!!i
1-0
8,
r":'
.2. f--
03 BIT 031-- ~
SHFT
~
04 REG 041-- ~
::! -
05
051--
'TI:-
~ r - OS
osl--
E
r;o f-- 07
071-- ~
110CRIlO
"-
m~lL-lEJ-
m
ti]l
,-
SHIFT 1/0
4:
----
ITr---,
,
!! --,
01
01
Is -
02'
02--~
;:;: r - 03
-
!:II-"
,
'
LlRO
00
B~T ~ h;L ,
03
SHFT,
04 REG 041--
!! I--
05
051-
os,
osl--
trn I-- 07
-
071-110CRIlO
Iii~'l
m
12
4.f8B
=1
'
PO elK TO LIRO
"
t-'
~'
tID
S
tw
~
L-14
~,
~
MSB 1/0
1
NOTE: i f MAX
'
i--S
191--
-
0,
~
joiiOiC
10
DO
"
<
I r-~
I--
r;' f-J
, ,
~
+1
SU
4·Bit
Shift Register/Comparator
PAL16R4
4·8it Shift Register/Comparator
Functional Description
The equations using AND-OR-INVERT logic are:
Frequently it is necessary to take a serial bit stream and convert
it to a parallel form for storage. It is also necessary, in some
cases, to monitor the same bit stream for certain patterns
e.g., floppy disk file headers, RS232 ASCII characters, etc.
A1, A2 '" B1, B2
= (/A1'/B1)'(/A2'/B2)
+ (lAl'/B1)'(A2*B2)
+ (Al'Bl)*(/A2*/B2)
+ (Al'Bl)'(A2'B2)
So for 3 inputs we require 8 sum of products and so on. This
Using a PAL it is possible to combine these two functions.
means that we have to cascade 2 stages in the 16R4 as there
are only 7 product terms available per output. Hence, compare
1 (COl) is:
.
Circuit DeScription
= AO*BO'Al'Bl*/CI
+ AO'BO'/Al*Bl*/CI
ICI = COMPARE IN FROM
PREVIOUS STAGE
+ lAO*/BO*Al'B1*/CI
+ lAO'/BO*/A1'/B1*/CI
The circuit shows a 16 bit !!erial/parallel convertor,with threestate outputS and a compare true output (EO). Four PAL16R4s
are ca.scaded for this design. There is also a synchronous preset
(PR) pin available. The circuit takes positive true Non-ReturnTo-Zero (NRZ) data with a central positive edge clock and
converts It into parallel data. When the A and B inputs are equal,
s negative going clock is output, with the negative (leading)
edge in the center of the output data.
Compare Output 2 (C02) is:
= A2*B2*A3'B3*/C*l and so on.
On the final stage, the clock is inverted and gated with C02.
This causes a negative going pulse to be output when the A
data center.
and B inputs arE~. equal, the leading edge being
This pulse is the EO output. For a 16 bit register, the final C02.
output can have a maximum· delay of 4x2x25j,~. = 200ns, so for
a EO pulse at data center t~e maximum clock frequency would
be 5 MHz.
.
at
PAL Impl~m.ntatlon
A PAL16R4 is used, the four flip-flops comprising the. shift
register and tlie other gates are used to compare the data and
output on appropriate pulse if the compare is true. For the shift
register the equations are:
.
But, by using a carry-Jook-ahead technique,this could be
increased to 7.2 MH;t. In practice clock frequencies of greater
than 10 MHz could be used (causing the EO pulse leading edg.e
to shift off center).
BO := /SERIN'/PR
81 := /BO'/PR
82 := IBl'/PR
e3 := la2*/PR
Conclusion
By feeding the outputs ofthe shift register into a bank of FIFOs
(67401 or similar) a practical serial communication channel can
be buffered into a microcomputer system. Using PAls the
design can be tailored. for use in different communication
systems.
The inputs are inverted because of the inverting output buffer
on each stage. To compare two inputs A and B, the boolean
equivalence operator is A '" B (or A :':8).
11-81T
DATA IN
CLOCK
SERIAL
NRI
DATA
I
CK
SERIN
J: I
C1PR~
PRES;;
Oc
4
4
4
4
{7
{;..
{;..
I
A
CLK -NC
CO2
8
B3
4
r+
CK
SERIN
CLK
CI
PR ~
t
I
A
NC
r-
CK
SERIN
CI
CO2
PR
8
I
B3
4
A
ere
r
CK
CLK i-NCr- SERIN
CO2
.
{7
CI
8
83
4
A
CLKJ
PR ~
1
4
I
11-81T DATA OUT
CO2 '-EO
8
DATA EOU
L..r
I I TCK
14--
-.j
I I
4-BIT SERIAL/PARALLEL SHIFT REGISTER/COMPARATOR WITH PRESET
2
4 .. Bit Shift Register IComparator
PAL16R4
SHFT4
4-BIT SHIFT REGISTER/COMPARATOR
MMI ENGLAND
CK CLK PR AO Al A2 A3 SERIN NC GND
/OC C02 COL B3 B2 Bl BO EQ
CI VCC
PAL DESIGN SPECIFICATION
HARRY HUGHES 02/18/81
/BO := /SERIN*/PR
;SHIFT LEFT (SERIAL IN)
/B1
/BO*/PR
;SHIFT LEFT
/B2 := /Bl*/PR
;SHIFT LEFT
/B3 := /B2*/PR
;SHIFT LEFT
:=
IF (VCC) /C01
AD* BO* Al* B1*/CI
AO* BO*/Al*/Bl*/CI
+ /AO*/BO* Al* Bl*/CI
+ /AO*/BO*/A1*/Bl*/CI
+
IF (VCC) /C02 = A2* B2* A3* B3*/COl
+ A2* B2*/A3*/B3*/COl
+ /A2*/B2* A3* B3*/COl
+ /A2*/B2*/A3*/B3*/COl
IF (veC)
/EQ = /CLK*/C02
;COMPARE AO= BO AND Al= B1
;COMPARE AO= BO AND /Al=/Bl
;COMPARE /AO=/BO AND A1= Bl
;COMPARE /AO=/BO AND /Al=/B1
;COMPARE A2= B2 AND A3= B3
;COMPARE A2= B2 AND /A3=/B3
;COMPARE /A2=/B2 AND A3= B3
lCOMPARE /A2=/B2 AND /A3=/B3
;COMPARE TRUE PULSE
FUNCTION TABLE
SERIN A3 A2 Al AO CK /oC PR CI COL C02 CLK EQ B3 B2 Bl BO
;-INPUTS;SER AAAA
lIN 3210
x xxxx
L
L
L
L
H
H
H
H
HHHL
HHLL
HLLL
LLLL
LLLH
LLHH
LHHH
HHHH
x XXXX
X XXXX
H HHHH
X xxxx
-------CONTROL------C / P C C C C E
K OC R I 01 02 LK Q
C
C
C
C
C
C
C
C
C
L
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
X
X
L
X
X
L
L
L
L
L
L
L
L
H
X
L
X
X
L
L
L
L
L
L
L
L
H
X
L
X
X
L
L
L
L
X
L
L
L
L
L L
L L
L L
L L
H X
X H
L L
X X
X
L
L
L
L
L
L
L
OUTPUTS
BBBB
3210
HHHH
HHHL
HHLL
HLLL
LLLL
r~LLH
L
LLHH
LHHH
HHHH
H
H
L
X
XXXX
HHHH
ZZZZ
xxxx
COMMENTS
PRESET
SHIFT LEFT IN A L (A=B)
SHIFT LEFT IN A L (A=B)
SHIFT LEFT IN A L (A=B)
SHIFT LEFT IN A L (A=B)
SHIFT LEFT IN A H (A=B)
SHIFT LEFT IN A H (A=B)
SHIFT LEFT IN A H (A=B)
SHIFT LEFT IN A H (A=B)
PREVIOUS STAGE COMPARE NOT TRUE
COMPARE TRUE PULSE INACTIVE
COMPARE TRUE
TEST HI-Z
4 .. 163
4.SitShift Register IComparator
DESCRIPTION
THIS 4-BIT SHIFT REGISTER/COMPARATOR ACCEPTS POSITIVE NRZ INPUT DATA ON THE
RISING EDGE OF THE CLOCK (CK) AND PRODUCES A PARALLEL OUTPUT (B) WITH A
'COMPARE TRUE PULSE' ON THE NEGATIVE EDGE OF THE CLOCK (CLK).
THE THREE-STATE OUTPUTS (B) ARE HIGH-Z WHEN THE OUTPUT CONTROL LINE (lOC) IS
HIGH AND ENABLED WHEN THE OUTPUT CONTROL LINE (/OC) IS LOW.
4.1R4
4-Bit Shift Register/Comparator
4-BIT SHIFT REGISTER/COMPARATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
CXIXXXXXXXOXXHHHHXXI
COOOII10XXOLLHHHLLOI
COOOOI10XXOLLHHLLLOI
COOOOOI0XXOLLHLLLLOI
COOOOOOOXXOLLLLLLLOI
COOI0001XXOLLLLLHLOI
COOI1001XXOLLLLHHLOI
COOI1101XXOLLLHHHLOI
COOI1111XXOLLHHHHLOI
OxxxxXXXXXOHHXXXXHl1
01XXXXXXXXOXXXXXXHXl
00011111XXOLLHHHHLOI
XXXXXXXXXXIXXZZZZXXI
PASS SIMULATION
4.165
4·Bit Shift Register/Comparator
4-BIT SHIFT
REGISTER/COMPA~TOR
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
8
9
-x--
---X·/CLK*/C02
-x--
16
-x--
24
-x-- ---x ----
32
-x--
..,.--x ----
/Bl*/PR
40
-x--
---x
/B2*/PR
48
49
50
51
52
56
57
58
59
60
LEGEND:
/BO*/PR
x-x- x-xx-x- -}(-X ----x-x x-x- ----x-x -x-x ----
---x
--,..x
---x
---x
x-xx-x-x-x
-x-x
x:
---- AO*BO*Al*Bl*/CI
---- AO*BO*/Al*/Bl*/CI
/AO */BO *Al *Bl* /CI
---- /AO*/BO*/Al*/Bl*/CI
x-x-x-x
x-x-x-x
---x
---x
---x
---x
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN
/SERIN*/PR
=
462
-------------
A2*B2*A3*B3*/COl
A2*B2*/A?*/B3*/COl
/A2*/B2*A3*B3*/COl
/A2*/B2*/A3*/B3*/COl
- : FUSE BLOWN
(H,P,l)
4-Bit Shift Register/Comparator
4-Bit Shift Register/Comparator
CK
Logic Diagram PAL16R4
1
III 2 J
4 5 6 7
891011
12131415
16111819
20212223
24252621
28293031
G
>-t1
1
2
,
J
,
5
ClK 3
.
rcl
15
~I-----
Jt
16
11
18
19
./
"
22
13
...
c:
~
24
25
26
21
A1
...
o 01--
J
29
JG
31
.....
~
~1
~
"
"
5
~~
o 0'--- .....
BO
"'"
2G
AO 4
~1
JJ
""
'"
../
J6
J7
J8
J9
....
..
...
A2 "'---I
....
"
""
""
""
41
A3
7
.
>-t1
"
55
~
B2
~
83
13
C01
12
C02
...
..
h.
.c.. I----
....
"
rJ
51
"""
""
9 ...
--.
..
B1
....
52
NC
-u~
h.
53
8
=Dl
.-o of--
"'"
../
""
""
SERIN
~
....
J2
6
EO
....
h.
..
.
18
....t - - -
~
"
PR
CI
I
8
9
IG
11
12
13
3
19
"
...
.,:1---oI
2 1
4 5 6 7
8 9 1011
12 131415
1617 1819
20212223
242S2627
28,293031
~
OC
Notes
4·Bit Counter
with 2 Input Mux
PAL16R4
AD
A
2
{ A1
DATA
IN
A2
l
A3
ao
B .
DATA
B1
IN
B2
:: ::.} DATA
OUT
I
'il:":' .LN._liS
02
1+IOl~""14 03
B3
4-169
0
4·Bit Counter with 2 Input Mux
PAL16R4
CNT4M
4-BIT COUNTER WITH 2 INPUT MUX
MMI SUNNYVALE, CALIFORNIA
eLK AO A1 A2 A3 BO B1 B2 B3 GND
/OC CO 11 Q3 Q2 Q1 QO 10 CI VCC
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/22/81
/QO := /Il*/IO*/QO
+ /Il* IO*/AO
+ Il*/IO*/BO
+ Il* IO*/CI*/QO
+ 11* 10* CI* QO
;!'IOLDQO (t,SB)
;LOAD AD
;LOAD BO
;HOLD IF NO CARRY IN
;COUNT IF CARRY IN AND QO=H
/Q1 := /Il*/IO*/Q1
+ /Il* IO*/A1
+ Il*/IO*/B1
+ 11* IO*/CI*/Q1
+ 11* IO*/QO*/Q1
+ Il* 10* CI* QO* Q1
;HOLD Q1
;LOAD A1
:LOAD B1
:HOLD IF NO CARRY IN
:HOLD IF.QO,Q;J.=L
;COUNT IF CARRY IN AND QO,Q1=H
/Q2 := /Il*/IO*/Q2
+ /Il* IO*/A2
+ Il*/IO*/B2
+ 11* IO*/CI*/Q2
+ 11* 1O*/QO*/Q2
+ 11* IO*/Q1*/Q2
+ 11* 10* CI* QO* Q1* Q2
;HOLD Q2
:LOAD A2
:LOAD B.2
:HOLD IF NO CARRY IN
;HOLD IF QO,Q2=J:.
;HOLD IFQ1,Q2=L
:COUNT IF CARRY IN AND QO,Q1,Q2=H
/Q3
:HOLD Q3 (MSB)
:LOAD A3
:LOADB3
:HOLD IF NO CARRY IN
IHOLD IF QO,Q3=L
: HOLD IF Q1,Q3=L
:HOLD IF Q2,Q3=L
:COUNT IF CARRY IN AND QO,Q1,Q2,Q3=H
:=
+
+
+
+
+
+
+
/Il*/IO*/Q3
/Il* IO*/A3
Il*/IO*/B3
Il* IO*/CI*/Q3
Il* IO*/QO*/Q3
11* IO*/Q1*/Q3
11* IO*/Q2*/Q3
11* 10* CI* QO* Q1* Q2* Q3
IF (VCC) /CO = /CI+/QO+/Q1+/Q2+/Q3
:CARRY OUT IF CARRY IN AND QO,Q1,Q2,Q3=H
B
A
CARRY OUT
CLOCK
OUTPUT CONTROL
Q
4·170
4-.Blt Counter with 2 Input Mux
FUNCTION TABLE
CLK lac Il IO A3 A2 A1 AO B3 B2 B1 BO CI co Q3 Q2 Q1 QO
~CONTROL
,CLK lac
INSTR
Il IO
AAAA
--INPUTS-BBBB
3210 3210
CARRY
CI CO
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
LLLL
LLLL
LLLH
LLLH
LLHL
LLHL
LHLL
LHLL
HLLL
HLLL
LLLL
LLLL
XXXX
XXXX
XXXX
xxxx
LHHH
XXXX
HHHH
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXx
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
X
H
X
H
X
H
H
H
H
H
H
L
H
X
OUTPUT
QQQQ
3210
COMMENTS
(HEX VALUES)
----------------------------------------------------------------------C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
H
H
H
H
L
H
L
H
L
H
L
H
H
H
L
H
H B
H H
H Ii
H H
H H
X X
HHHH
HHHH
LHHH
LHHH
HLHH
HLHH
HHLH
HHLH
HHHL
HHHL
HHHH
HHHH
LLLH
XXXX
LLHH
XXXX
XXXX
XXXX
XXXX
XXXX
HHLL
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX,
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
L
X
L
X
L
L
L
H
L
L
L
L
X
LLLL
HHHH
LLLH
LHHH
LLHL
HLHH
LHLL
HHLH
HLLL
HHHL
LLLL
HHHH
LLLH
LLHL
LLHH
LHLL
LHHH
HLLL
HHHH
LLLL
HHLL
HHLH
HHLH
HHHL
HHHH
LLLL
LLLH
LLLH
LLHL
ZZZZ
LOAD A (0)
LOAD B (F)
LOAD A (1)
LOAD B (7)
LOAD A (3)
LOAD ·B (Bl
LOAD A (4)
LOAD B (D)
LOAD A (8)
LOAD B (E)
LOAD A (0)
LOAD B (F)
LOAD B (1)
INCREMENT
LOAD B (3)
INCREMENT
LOAD A (7)
INCREMENT
LOAD A (F)
INCREMENT (ROLL OVER)
LOAD B (C)
INCREMENT (D)
HOLD (D)
INCREMENT (E)
INCREMENT (F) (CARRY OUT)
INCREMENT (0) (ROLL OVER)
INCREMENT (1)
HOLD (NO CARRY IN)
INCREMENT (2)
TEST HI-Z
-------------~---------------------------------------------------------
D
4·81t Counter with 2 Input Mux
DESCRIPTION
THE 4-BIT COUNTER LOADS A OR B FROM THE MUX, INCREMENTS, OR HOLDS
ON THE RISING EDGE OF THE CLOCK.
/oe CLK 11 10 CI A3-AO B3-BO Q3-QO
H
L
L
L
L
L
X
C
C
C
C
C
X
1.
L
H
H
H
X
L
H
L
H
H
X
X
X
X
L
H
X
X
Z
X
x
Q
A
X
X
B
A
B
X
X
x
x
Q
Q PLUS 1
OPERATION
HI-Z
HOLD
LOAD A
LOAD B
HOLD
INCREMENT
------------------------------------------------------
4·172
4-Bit Counter with 2 Input Mux
4-BIT COUNTER WITH 2 INPUT MUX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C00001111XOXOLLLL1X1
C00001111X0XlHHBHOX1
CIOOOl110XOXOLLLHIXl
CIOOOIIIOXOXILHHHOXI
COI001101XOXOLLHLIXI
COI001101XOX1HLHHOXI
C00101011X0XOLHLL1Xl
C00101011XOXIHHLHOX1
C00010111X0XOHLLL1X1
C00010111X0X1HHHLOX1
C00001111XOXOLLLL1X1
C00001111XOXIHHBHOX1
CXXXX1000XOX1LLLHOX1
CXXXXXXXXXOL1LLHL111
CXXXX1100XOX1LLHHOX1
CXXXXXXXXXOL1LHLL111
C1110XXXXXOXOLHHH1X1
CXXXXXXXXXOLIHLLL111
C1111XXXXXOXOHBBH1X1
CXXXXXXXXXOL1LLLt111
CXXXX0011XOXOHHLL1X1
CXXXXXXXXXOL1HHLHll1
CXXXXXXXXXOLOHHLH011
CXXXXXXXXXOL1HHHL111
CXXXXXXXXXOH1HHHH111
CXXXXXXXXXOL1LLLL111
CXXXXXXXXXOL1LLLH111
CXXXXXXXXXOL1LLLH101
CXXXXXXXXXOL1LLHL111
XXXXXXXXXX1XXZZZZXX1
PASS SIMULATION
4-173
4·Bit Counter with 2 Input Mux
4-BIT COUNTER WITH 2 INPUT MUX
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
16
17
18
19
20
---x ---x
-x-- --x---x
---x --x- ---x
--x- --x- --x-
24
25
26
27
28
29
---x
---x ------x ----xx---x .... _----x
-x-- --x---x --x---x
--x--x- ---x ---x
--x--x- --x- --x- --x--x-
/11*/IO*/Q1
/11*IO*/A1
11*/IO*/B1
11*IO*/CI*/Q1
11*IO*/QO*/Q1
11*IO*CI*QO*Q1
32
33
34
35
36
37
38
---x
---x ---- ---x
---- ---- ---x -----x- -x----- ---- -xx---x
---x --x---x
--x---x
--x--x- ---x
--x---x ---x
--x--x- --x- --x- --x- --x--x-
/11*/IO*/Q2
/11*IO*/A2
I1*/IO*/B2
11*IO*/CI*/Q2
11*10*/QO*/Q2
40
41
42
43
44
45
46
47
---x
---x
--x-x----x
---x --x---x
--x- ---x ------x
--x---x ---- ---x
--x---x ---x
--x- --x- --x- --x- --x- --x-
---x
---x
--x- -x---x--x--x--x--x-
/I1*/IO*/Q3
/11*!0*/A3
11*/IO*/B3
I1*IO*/CI*/Q3
11*IO*/QO*/Q3
I1*IO*/Q1*/Q3
I1*IO*/Q2*/Q3
I1*IO*C!*QO*Q1*Q2*Q3
----
/CI
/QO
/Q1
/Q2
/Q3
56
57
58
59
60
61
----
----
LEGEND:
-x--
---x
---x
X : FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
4·174
/11*/IO*/QO
/11*IO*/AO
11*/IO*/BO
11*IO*/CI*/QO
11*IO*CI*QO
11*IO*/Q~*/Q2
I1*IO*CI*QO*Q1*Q2
---- ----
---x ---- .... _-- ------x ------x
----
---x ------x -----x--x--x-
----
921
-
:
FUSE BLOWN
(H,P,l)
4-Bit Counter with 2 Input Mux
Logic Diagram PAL16R4
4-Bit Counter with 2 Input Mux
elK
1
0123
4567
B 91011
12131415
16171819
20212223
24252627
28293031
0
>-J
.
1
1
3
5
6
19
el
18
10
)
AO 3
...
...'J---
~
)-J
,
8
10
11
11
13
A1
J
.
"15
1-
~
16
17
18
19
r-~ 00
""
D
J
'"
11
22
13
A2
4
...
.c.
~
~
"
A3
5
..
15
16
17
18
19
30
.
'"
j
J1
~
1C.
~
""'I
Qj--
~1
JJ
""
35
J6
J1
80
6
..
./
38
39
Dl
t-I>
~
~
01
~
02
~
03
Pl
31
l4
~
(j
'"
""
"
""
--/
<14
47
81
7
....
....
.....
...
48
49
50
>=d
51
51
82
8
..
53
54
55
13
11
11
co
~
'I---
......
56
~
""
""
59
60
6J
83
ll11
9
...
oI
2 J
~
4 5 6 1
8 9 1011
12131415
16171819
20212223
24252627
28293031
~
4-175
Notes
4-1,76
Octal Counter
PAL20X8
DATA
OUT
4-177
D
Octal Counter
PAL20X8
74LS461
OCTAL COUNTER
MMI SUNNYVALE, CALIFORNIA
CLK 10 DO Dl D2 D3 D4 D5 D6 D7 II GND
/OC /CO Q7 Q6 Q5 Q4 03 Q2 Ql QO /CI VCC
/QO :=
+
:+:
+
/Ql
.=
+
:+:
+
/Q2 :=
+
:+:
+
/Q3 :=
+
:+:
+
/Q4
:=
+
:+:
+
/Q5 :=
+
:+:
+
/Q6
.=
+
:+:
+
/97 :=
+
:+:
+
IF (VCC)
4·178
PAL DESIGN SPECIFICATION
BIRKNER/KAZMI/BLASCO 02/10/81
/I1*/IO
1O*/QO
I1*/IO*/DO
11* 10* CI
;CLEAR LSB
; COUNT/HOLD
;LOAD DO (LSB)
; COUNT
/I1*/1O
1O*/Q1
I1*/IO*/Dl
I1* 10* CI*QO
; CLEAR
;COUN'J'/HOLD
;LOAD Dl
; COUNT
/I1*/1O
IO*/Q2
I1*/IO*/D2
11* 10* CI*QO*Ql
; CLEAR
;CQUN'r/HOLD
;LOAD D2
; COUNT
/I1*/IO
IO*/Q3
I1*/IO*jD3
11* 10* C1*QO*Ql*Q2
; CLEAR
;COUNT/HOIoD
;LOAD D3
; COUNT
/I1*/IO
IO*/Q4
I1*/IO*jD4
11* 10* CI*QO*Ql*Q2*Q3
; CLEAR
; COUNT/HOLD
;LOAD D4
; COUNT
/I1*/IO
IO*/Q5
I1*/IO*/D5
11* 10* C1*QO*Ql*Q2*Q3*Q4
; CLEAR
; COUNT/HOLD
;LOAD D5
; COUNT
/I1*/IO
IO*/Q6
I1*/IO*jD6
11* 10* CI*QO*Ql*Q2*Q3*Q4*Q5
; CLEAR
; COUNT/HOLD
;LOAD D6
; COUNT
/I1*/IO
IO*/Q7
I1*/IO*/D7
11* 10* CI*QO*Ql*Q2*Q3*Q4*Q5*Q6
;CLEAR MSB
; COUNT/HOLD
;LOAD D7 (MSB)
; COUNT
CO
= CI*QO*Ql*Q2*Q3*Q4*Q5*Q6*Q7
;CARRY OUT
Octal Counter
FUNCTION TABLE
CLK JOC II IO D7 D6 D5 D4 D3 D2 Dl DO JCI JCO Q7 Q6 Q5 Q4 Q3 Q2 91 QO
: CONTROL
:CLK JOC
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
1.
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C
L
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
INSTR
II IO
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
X
-INPUT-DDDDDDDD
76543210
LLLLLLLH
XXXXXXXX
LLLLLLHH
XXXXXXXX
LLLLLHHH
XXXXXXXX
LLLLHHHH
XXXXXXXX
LLLHHHHH
XXX XXX XX
LLHHHHHH
XXXXXXXX
LHHHHHHH
XXXXXXXX
HHHHHHHH
XXXXXXXX
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
HHHHHHHH
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXX XXX XX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
HHHHHHHL
XXXXXXXX
XXXXXXXX
LLLLLLLL
HHHHHHHH
XXXXXXXX
CARRY
JCI JCO
X
L
X
L
X
L
X
L
X
L
X
L
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
X
X
X
X
X
X
X
X
L
X
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
H
L
L
H
L
H
L
H
X
X
-OUTPUTQQQQQQQQ
76543210
COMMENTS
(HEX VALUES)
LLLLLLLH
LLLLLLHL
LLLLLLHH
LLLLLHLL
LLLLLHHH
LLLLHLLL
LLLLHHHH
LLLHLLLL
LLLHHHHH
LLHLLLLL
LLHHHHHH
LHLLLLLL
LHHHHHHH
HLLLLLLL
HHHHHHHH
LLLLLLLL
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
HHHHHHHH
LLLLLLLL
LLLLLLLH
LLLLLLHL
LLLLLLHH
LLLLLHLL
LLLLLHLH
LLLLLHHL
LLLLLHHH
LLLLHLLL
LLLLHLLH
LLLLHLHL
LLLLHLHH
LLLLHHLL
HHHHHHHL
HHHHHHHH
HHHHHHHH
HHHHHHHH
LLLLLLLL
ZZZZZZZZ
LOAD (01)
INCREMENT
LOAD (03)
INCREMENT
LOAD (07)
INCREMENT
LOAD (OF)
INCREMENT
LOAD (IF)
INCREMENT
LOAD (3F)
INCREMENT
LOAD (7F)
INCREMENT
LOAD (FF)
INCREMENT (ROLL OVER)
LOAD (FF)
LOAD (FE)
LOAD (FD)
LOAD (FB)
LOAD (F7)
LOAD (EF)
LOAD (DF)
LOAD (BF)
LOAD (7F)
LOAD (FF)
CLEAR
INCREMENT TO (01)
INCREMENT TO (02)
INCREMENT TO (03)
INCREMENT TO (04)
INCREMENT TO (05)
INCREMENT TO (06)
INCREMENT TO (07)
INCREMENT TO (08)
INCREMENT TO (09)
INCREMENT TO (OA)
INCREMENT TO (OB)
INCREMENT TO (OC)
LOAD (FE)
INCREMENT TO (FF) jCO=L
CI INHIBITS COUNT AND CO
HOLD SEL INHIBITS COUNT ONLY
INCREMENT TO (00)
TEST HI-Z
4-179
Octal Counter
DESCRIPTION
THIS IS AN 8-BIT SYNCHRONOUS COUNTER WITH PARALLEL LOAD, CLEAR, AND HOLD
CAPABILITY. THE LOAD OPERATION LOADS THE INPUTS (D7-DO) INTO THE OUTPUT
REGISTER (Q7-QO). THE CLEAR OPERATION RESETS THE OUTPUT REGISTER TO ALL LOWS.
THE HOLD OPERATION HOLDS THE PREVIOUS VALUE REGARDLESS OF CLOCK TRANSITIONS.
THE INCREMENT OPERATION ADDS ONE TO THE OUTPUT REGISTER WHEN THE CARRY-IN IS
TRUE (jCI=L), OTHERWISE THE OPERATION IS A HOLD. THE CARRY-OUT (jCO) IS TRUE
(/CO=L) WHEN THE OUTPUT REGISTER (Q7-QO) IS ALL HIGHS, OTHERWISE FALSE (/CO=H).
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
OPERATIONS TABLE:
/OC
CLK
Il
10
/CI
D7-DO
Q7-QO
OPERATION
-------------------------------------------------H
L
L
L
L
L
X
C
C
C
C
C
X
L
L
H
H
H
X
L
H
L
H
H
X
X
X
X
H
L
X
X
X
D
X
X
Z
L
Q
HI-Z
CLEAR
HOLD
LOAD
HOLD
INCREMENT
D
Q
Q PLUS 1
-------------------------------------------------TWO OR MORE OCTAL COUNTERS MAY BE CASCADED TO PROVIDE LARGER COUNTERS. THE
OPERATION CODES WERE CHOSEN SUCH THAT WHEN 11 IS HIGH, 10 MAY BE USED TO SELECT
BETWEEN LOAD AND INCREMENT AS IN A PROGRAM COUNTER (JUMP/INCREMENT). ALSO,
CARRY-OUT (/CO) AND CARRY-IN (/CI) ARE LOCATED ON PINS 14 AND 23 RESPECTIVELY,
WHICH PROVIDES FOR CONVENIENT INTERCONNECTIONS WHEN TWO OR MORE OCTAL COUNTERS
ARE CASCADED TO IMPLEMENT LARGER COUNTERS.
o
CARRY IN
CARRY OUT
CLOCK
Q
4·180
Octal Counter
OCTAL COUNTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
COIOOOOOOOIXOHLLLLLLLHXl
CIXXXXXXXXIXOHLLLLLLHLOI
COIIOOOOOOIXOHLLLLLLHHXl
CIXXXXXXXXIXOHLLLLLHLLOI
COIIIOOOOOIXOHLLLLLHHHXl
CIXXXXXXXX!XOHLLLLHLLLOI
COIIIIOOOOIXOHLLLLHHHHXl
CIXXXXXXXXIXOHLLLHLLLLOI
COIIIIIOOOIXOHLLLHHHHHXl
CIXXXXXXXXlXOHLLHLLLLLO1
COIII1I1001XOHLLHHHHHHXl
C1XXXXXXXXIXOHLHLLLLLL01
COII111110IXOHLHHHHHHHX1
CIXXXXXXXXIXOHHLLLLI,LL01
COl1llll111XOLHHHHHHHH01
C1XXxXXXXX1XOHLLLLLLLL01
COlll1ll111XOLHHHHHHHH01
COOll1l111IXOHHHHHHHHLX1
COIOl1l111IXOHHHHHHHLHXl
COIIOl11111XOHHHHHHLHHXl
COll1011111XOHHHHHLHHHXl
COIIII01111XOHHHHLHHHHX1
COlll110111XOHHHLHHHHHXl
C01IIIIIOIIXOHHLHHHHHHXl
COlll11l10IXOHLHHHHHHHXl
COll11l11l1XOLHHHHHHHH01
COXXXXXXXXOXOHLLLLLLLLXl
CIXXXXXXXXlXOHLLLLLLLHOl
CIXXXXXXXXIXOHLLLLLLHLOI
CIXXXXXXXXIXOHLLLLLLHHOI
CIXXXXXXXXIXOHLLLLLHLLOI
CIXXXXXXXXIXOHLLLLLHLHOI
CIXXXXXXXXIXOHLLLLLHHLOI
CIXXXXXXXXIXOHLLLLLHHHOI
CIXXXXXXXXIXOHLLLLHLLLOI
CIXXXXXXXXIXOHLLLLHLLHOI
CIXXXXXXXXIXOHLLLLHLHLOI
CIXXXXXXXXIXOHLLLLHLHHOI
CIXXXXXXXXIXOHLLLLHHLLOI
COOll111111XOHHHHHHHHLXl
CIXXXXXXXXIXOLHHHHHHHHOI
CIXXXXXXXXIXOHHHHHHHHHII
CIOOOOOOOOOXOLHHHHHHHHOI
Cl111111111XOHLLLLLLLLOI
XXXXXXXXXXXXIXZZZZZZZZXl
0
PASS SIMULATION
4-181
Octal Counter
OCTAL COUNTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
11
-x----- ---- ---- ---- ---- ---- ---- -x-x--- ---x ---- ---- ---- ---- ---- ---- ---x---x-- -x-x--x ---x---
/Il*/IO
IO*/OO
Il*/IO*/DO
Il*IO*CI
16
17
18
19
-x-x-----x ----x--x-- ---x--x --x-
/Il*/IO
IO*/Ql
Il*/IO*/Dl
Il*IO*CI*QO
24
25
26
27
-x-x-----x ----x--x-x--x --X"- --x-
32
33
34
35
---- ----x-x-----x ----x--x-- ---x--x --x- --x- --x-
40
41
42
43
-x-x-----x ----x-- ---- ----x-x--x --x- --x- --x- --x-
48
49
50
51
-x-x-----x
-x--x-x--x --x- --x- --x- --x- --x-
56
57
58
59
-x--x-x-----x ----x-x---x-X--x --x- --x- --x- --x- --x- --x- ---- ---- x---
/Il*/IO
IO*/Q6
Il*/IO*/D6
Il*IO*CI*QO*Ql*Q2*Q3*Q4-
64
65
66
67
---- -x--x-x-----x ----x--x-- x--x--x --x- --x- --x- --x- --x- --x- --x- ---- x---
/Il*/IO
IO*/Q7
Il*/IO*/D7
Il*IO*CI*QO*Ql*Q2*Q3*Q4-
8
9
10
72 ----
73
-x-x--x---x-x--x---x-x--x---x-x--x---x--
----
x--x---
X: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW = 1243
4·182
/Il*/IO
IO*/Q3
Il*/IO*/D3
Il*IO*CI*QO*Ql*Q2
/Il*/IO
IO*/Q4
Il*/IO*/D4
Il*IO*CI*QO*Ql*Q2*Q3
/Il*/IO
IO*/Q5
Il*/IO*/D5
Il*IO*CI*QO*Ql*Q2*Q3*Q4
---- ----
---x --x- --x- --x- --x- --x- --x- --x- --x-
LEGEND:
/Il*/IO
IO*/Q2
Il*/IO*/D2
Il*IO*CI*QO*Ql
---- CI*QO*Ql*Q2*Q3*Q4*Q5*Q6-
FUSE BLOWN
(H,P,I)
Octal Counter
Logic Diagram PAL20X8
Octal Counter
ClK
1
.,,
012
1
4561
191011
12131"5
16111819
20212123
24252621
28293031
11133415
36113839
"'"
It'J(
J
It'J(
,
I<
-
11
o
1
2 1
..
5
6
1
•
9 10 I'
12 13'415
Ii 11-1"9
202121 2l
24 252621
21293031
323334
n
>-*J
14
13
16 31 Jl19
4-183
05
07
Octal Counter
Application
16-81t Counter
BUS OUT ENABLE
COUNT ENABLE
INSTR {
ClK
10
11
IS-BIT
DATA BUS
IN
-
16-BIT
OATA BUS
0 UT
-~
K
-
rm
-rz~lr-~
~
t::::I
10.
3 -DO
CI
Qor-~
.
'::1
L.:.
141-- 01
aIr- ~
....
1::::1
.J"51-- 02
Q2r- !!!.J
8
~
.J"61-- 03 BIT Q3t-- ~
....
CNTR
":':'I
J'i I-- 04
Q4 .!!r
I.,;"
;r
I--
05
Q5
r--
....
J"'9 t-- OS
....
-fiii f -
QS r--
07
Q7r110CCO
~
"::l
...I
~
~
.../
~
...m 1L-~
~
...
r,;~
~
-lr-IIDCARRY
4:
J2~
~31--0010
;;:
t-L,;:,
--
CI
t::::I
QO-~
01
ali-.
-15 r- 02
~6 t-- 03
L:.
~
,
Q2t-
8
~
:m
~
BIT Q3t- ~
CNTR
~
04
a4
-17 t--18 r--- 05
....
1m
r- .!.!.
'~
Q5t-
-IT -
~
~
os
Q6t~Iiii
07
Q7r:- ~
~r- 110CCO
.-..
"m~ IL-~
m
12
NOTE: IMAX
4-1.84
= IpO ClK TO CO + ISU
...•
b
~.
Octal Up/Down Counter
PAL20X8
vee
Ciii
00
01
02
DATA
03
IN
DATA
OUT
05
Q7
CBo
4-185
Octal Up/Down Counter
PAL20xS
PSOOS
OCTAL UP/DOWN COUNTER
MMI SUNNYVALE, CALIFORNIA
CLK /LO DO 01 02 03 04 05 06 07 /UD GNO
/OC /CBO Q7 Q6 QS Q4 Q3 Q2 Q1 QO /CBI VCC
/QO :=
PAL DESIGN SPECIFICATION
VINC~ COLI 07/24/S1
/LO*/QO
+
LO*/OO
:+: /LO* UD* CBI
+ /LO*/UO* CSI
/Q1 :=
/LO*/Q1
+
LO*/01
:+: /LO* UD* CBI* QO
+ /LO*/UD* CBI*/QO
/Q2 :=
/LO*/Q2
+
LO*/D2
:+: /LO* UO* CBI* QO* Q1
+ /LO*/UD* CBI*/QO*/Q1
/Q3 :=
/LO*/Q3
+
LO*/03
:+: /LO* UD* CBI* QO* Q1* Q2
+ /LO*/UO* CBI*/QO*/Q1*/Q2
/Q4 :=
/LO*/Q4
+
LO*/04
:+: /LO*.UD* CBI* QO* Q1* Q2* Q3
+ /LO*/UD* CBI*/QO*/Q1*/Q2*/Q3
/QS :=
/LO*/QS
+
LO*/OS
:+: /LO* UD* CBI* QO* Q1* Q2* Q3* Q4
+ /LO*/UD* CBI*/QO*/Q1*/Q2*/Q3*/Q4
/Q6 :=
/LO*/Q6
+
LO*/D6
:+: /LO* UD* CBI* QO* Q1* Q2* Q3* Q4* QS
+ /LO*/UD* CBI*/QO*/Q1*/Q2*/Q3*/Q4*/QS
/Q7 :=
/LO*/Q7
+
LO*/D7
:+: /LD* UO* CBI* QO* Q1* Q2* Q3* Q4* QS* Q6
+ /LD*/UO* CBI*/QO*/Q1*/Q2*/Q3*/Q4*/QS*/Q6
IF(VCC) CBO =
1HOLO QO
1LOAO DO (LSB)
1INCREMENT
1DECREMENT
1HOLO Q1
1LOAD 01
1INCREMENT
1DECREMENT
1HOLD.Q2
1LOAD 02
: INCREMENT
10ECRE:MENT
1HOLO Q3,
1LOAD 03
1INCREMENT
1DECREMENT.
1HOLO Q4,
1LOAD 04
1INCREMENT
1DECREMENT
1HOLOQS
',LOAD DS
1INCREMENT
1DECREMENT
1HOLO Q6
1LOAD D6
1INCREMENT
1DECREMENT
1HOLO Q7
1LOAO 07 (MSB)
1INCREMENT
1DECREMENT
UD* CBI* QO* Q1* Q2* Q3* Q4* QS* Q6* Q7 1CARRY OUT
+ /UD* CBI*/QO*/Q1*/Q2*/Q3*/Q4*/QS*/Q6*/Q7 :BORROW OUT
4-186
Octal Up/Down Counter
FUNCTlaN TABLE
CLK IOC ILD /UD 07 06 05 04 D3 02 D1 DO ICBI ICBa 0.7 0.6 0.5 0.4 0.3 0.2 Q1 0.0
,----CaNTRaL---,CLK lac ILD IUD
C
L
L
C
L
H
C
L
H
eLL
C
L
H
C
L
H
C
L
L
C
L
H
C
L
H
C
L
L
C
L
H
C
L
H
eLL
C
L
H
C
L
H
C
L
L
C
L
H
C
C
C
C
C
C
C
L
L
L
L
L
L
L
H
L
H
H
L
L
L
C·
L
L
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
C
X
L
H
H
X
X
L
H
X
L
H
X
L
H
X
L
H
X
L
H
X
L
H
X
L
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
-INPUTSDDDDDDDD
76543210
LLLLLLLH
XXXXXXXX
XXXXXXXX
LLLLLLHH
XXXXXXXX
XXXXXXXX
LLLLLHHH
XXXXXXXX
XXXXXXXX
LLLLHHHH
XXXXXXXX
XXXXXXXX
LLLHHHHH
XXXXXXXX
XXXXXXXX
LLHHHHHH
XXXXXXXX
XXXXXXXX
LHHHHHHH
XXXXXXXX
XXX XXX XX
HHHHHHHH
LHHHHHHH
HLHHHHHH
HHLHHHHH
HHHLHHHH
HHHHLHHH
HHHHHLHH
HHHHHHLH
HHHHHHHL
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
CARR/BaRR
ICBI ICBa
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
L
L
L
L
L
L
L
H
L
X
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
L
H
H
H
H
H
x
aUT PUTS
0.0.0.0.0.0.0.0.
76543210
LLLLLLLH
LLLLLLHL
LLLLLLI,H
LLLLLLHH
LLLLLHLL
LLI,LLLHH
LLLLLHHH
LLLLHLLL
LLLLLHHH
LLLLHHHH
LLLHLLLL
LLLLHHHH
LLLHHHHH
LLHLLLLL
LLLHHHHH
LLHHHHHH
LHLLLLLL
LLHHHHHH
LHHlIHHHH
HLLLLLLL
LHHHHHHH
HHHHHHHH
LHHHHHHH
HLHHHHHH
HHLHHHHH
HHHLHHHH
HHHHLHHH
HHHHHLHH
HHlIHHHLH
HHHHHHHL
HHHHHHHH
LLLLLLLL
LLLLLLLH
LLLLLLHL
LLLLLLHL
LLLLLLHH
LLLLLLHL
LLLLLLLH
LLLLLLLL
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHHLH
HHHHHHLL
ZZZZZZZZ
caMMENTS
(HEX VALUES)
LaAD (01)
INCREMENT
DECREMENT
LaAD (03)
INCREMENT
DECREMENT
LaAD (07)
INCREMENT
DECREMENT
LaAD (OF)
INCREMENT
DECREMENT
LaAD (IF)
INCREMENT
DECREMENT
LaAD (3F)
INCREMENT
DECREMENT
LOAD (7F)
INCREMENT
DECREMENT
LOAD (FF)
LaAD (7F)
LaAD (BF)
LOAD (OF)
LaAD (EF)
LOAD (F7)
LaAD (FB)
LOAD (FD)
LaAD (FE)
INCREMENT
INCREMENT
INCREMENT
INCREMENT
HaLO
INCRF~ENT
DECREMENT
DECREMENT
DECREMENT
DECREMENT
DECREMENT
DECREMENT
HaLD
DECREMENT
TEST HI-Z
(/CBa=L)
TO.
TO.
TO.
TO.
(FF)
(00)
(01)
(02)
TO.
TO.
TO
TO.
TO
TO.
TO
(03)
(02)
(01)
(00) (/CBO=L)
(FF) (ROLL UNDER)
(FE)
(FD)
(RaLL aVER)
TO (FC)
4·187
Octal Up/Down Counter
DESCRIPTION
THIS PAL IS AN 8-BIT SYNCHRONOUS UPjDOWN .COUNTER.WITH PARALLEL LOAD AND HOLD
CAPABILITY. THREE FUNCTION SELECT INPUTS (/LD, jUD, jCBI) PROVIDE ONE OF FOUR
OPERATIONS WHICH OCCUR SYNCHRONOUSLY ON THE RISING EDGE OF THE CLOCK (CLK).
THE LOAD OPERATION LOADS THE INPUTS (D7-DO) INTO THE OUTPUT REGISTERS (Q7-QO).
THE HOLD OPERATION HOLDS THE PREVIOUS VALUE REGARDLESS OF CLOCK TRANSITIONS.
THE INCREMENT OPERATION ADDS ONE TO THE OUTPUT REGISTER WHEN CARRY-IN INPUT
IS TRUE (jCBI~L), OTHERWISE THE OPERATION IS A HOLD. THE CARRY-OUT (jCBO) IS
TRUE (/CBO=L) WHEN THE OUTPUT REGISTER (Q7-QO) IS ALL HIGHS, OTHERWISE FALSE
(jCBO~H).
THE DECREMENT OPERATION SUBTRACTS ONE FROM THE OUTPUT REGISTER
WHEN THE BORROW-IN INPUT IS TRUE (jCBI=L), OTHERWISE THE OPERATION IS A HOLD.
THE BORROW-OUT (jCBO) IS TRUE (jCBO=L) WHEN THE OUTPUT REGISTER (Q7-QO) IS ALL
LOWS, OTHERWISE FALSE (jCBO=H).
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
OPERATIONS TABLE:
JOC
CLK
JLD
JUD
H
L
L
L
L
L
X
C
C
C
C
C
X
L
H
H
H
H
X
X
L
L
H
H
JCBI
X
X
H
L
H
L
07-00
Q7-QO
X
Z
0
L
X
Q
X Q PLUS 1
X
Q
X Q MINUS 1
OPERATION
HI-Z
LOAD
HOLD
INCREMENT
HOLD
DECREMENT
THIS OCTAL COUNTER IS IMPLEMENTED WITH A SINGLE PAL20X8. CARRY/BORROW-OUT
(jCBO) AND CARRYjBORROW-IN (jCBI) ARE LOCATED ON PINS 14 AND 23 RESPECTIVELY,
WHICH PROVIDES FOR CONVENIENT INTERCONNECTIONS WHEN TWO OR MORE OCTAL UPjDOWN
COUNTERS ARE CASCADED TO IMPLEMENT LARGER COUNTERS.
o
CARRY OUT
CLOCK
OUTPUT CONTROL
Q
4·188
Octal Up/Down Counter
OCTAL UP/DOWN COUNTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
C010000000XXOXLLLLLLLHX1
C1XXXXXXXXOXOHLLLLLLHL01
C1XXXXXXXX1XOHLLLLLLLH01
C011000000XXOXLLLLLLHHX1
C1XXXXXXXXOXOHLLLLLHLL01
C1XXXXXXXX1XOHLLLLLLHH01
C011100000XXOXLLLLLHHHX1
C1XXXXXXXXOXOHLLLLHLLL01
C1XXXXXXXX1XOHLLLLLHHH01
COl1110000XXOXLLLLHHHHX1
C1XXXXXXXXOXOHLLLHLLLL01
C1XXXXXXXX1XOHLLLLHHHH01
C011111000XXOXLLLHHHHHX1
C1XXXXXXXXOXOHLLHLLLLL01
C1XXXXXXXX1XOHLLLHHHHH01
C011111100XXOXLLHHHHHHX1
C1XXXXXXXXOXOHLHLLLLLL01
C1XXXXXXXX1XOHLLHHHHHH01
C011111110XXOXLHHHHHHHX1
C1xxxxXXXXOXOHHLLLLLLL01
C1XXXXXXXX1XOHLHHHHHHH01
C011111111XXOXHHHHHHHHX1
C011111110xXOXLHHHHHHHX1
C011111101XXOXHLHHHHHHX1
C011I11011XXOXHHLHHHHHX1
C01ll101llXXQXHHHLHHHHX1
C011101111XXOXHHHHLHHHX1
C011011111XXOXHHHHHLHHX1
C010111111XXOXHHHHHHLHX1
C001111111XXOXHHHHHHHLX1
C1XXXXXXXXOXOLHHHHHHHH01
C1XXXXXXXXOXOHLLLLLLLL01
C1XXXXXXXXOXOHLLLLLLLH01
C1XXXXXXXXOXOHLLLLLLHL01
C1XXXXXXXXOXOHLLLLLLHL11
C1XXXXXXXXOXOHLLLLLLHH01
C1XXXXXXXX1XOHLLLLLLHL01
C1XXXXXXXX1XOHLLLLLLLH01
C1XXXXXXXX1XOLLLLLLLLL01
C1XXXXXXXX1XOHHHHHHHHH01
C1XXXXXXXX1XOHHHHHHHHL01
C1XXXXXXXX1XOHHHHHHHLH01
C1XXXXXXXX1XOHHHHHHHLH11
C1XXXXXXXX1XOHHHHHHHLL01
XXXXXXXXXXXX1XZZZZZZZZX1
m
PASS SIMULATION
4.189
Octal Up/Down Counter
OCTAl, UP/DOWN COUNTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
11
x--- ---x ---- ----x-- -x-- ---- ---x--x
x--x
16
17
18
19
x-----x ---- ----x--x-- ---- ---x--x --x- ---x--x ---x ----
-x----- x---
24
25
26
27
x---x-x--x --x- --xx--x ---x ---x
-------- /LO*/Q2
---- ---- LO*/D2
-x-- /LO*UO*CBI*QO*Q1
---- x--- /LO*/UO*CBI*/QO*/Ql
32
33
34
35
---- ---x
x---x--x-x--x --x- --x- --xx--x ---x ---x ---x
40
41
42
43
---- ---x-----x
-x--x-x--x --x- --x- --x- --xx--x ---x ---x ---x ---x
48
49
50
51
x---x-x--x
x--x
56
57
58
59
x------ ----x-x--x --x- --x- --x- --x- --x- --xx--x ---x ---x ---x ---x ---x ---x
x--- ---- ---- ---- ----x-- ---- ---- ---- ---x--x --x- --x- --x- --x- --x- --xx--x ---x ---x ---x ---x ---x ---x
8
9
10
64
65
66
67
72
73
74
-------
---- ---- /LO*/OO
LO*/OO
-x-- /LO*UD*CBl
x--- /LO*/UO*CBI
---x
-x--
---- ------- ----
----
----
/LO*/Q3
LO*/03
-X-- /LO*UD*CBI*QO*Ql*Q2
x--- /LO*/UO*CBI*/QO*/Ol*/Q2
-x-x---
---x
/LO*/04
LO*/04
/LO*UO*CBI*QO*Q1*Q2*Q3
/LO*/UO*CBI*/QO*/Q1*/Q2-
---- /LO*/Q5
LO*/05
-x-- /LO*UD*CBI*QO*Q1*Q2*Q3*x--- /LO*/UD*CBI*/QO*/Ql*/Q2-
---- -x--
--x- --x- --x- --x- --x---x ---x ---x ---x ---x
---x
-x--
x---
/LO*/Q6
LO*/06
/LO*UD*CBI*QO*Q1*Q2*Q3*/LO*/UO*CBI*/QO*/Ql*/Q2-
-x---x---x ---- x---
/LO*/Q7
LO*/07
/LD*UD*CBI*QO*Q1*Q2*Q3*/LO*/UO*CBI*/00*/Q1*/Q2-
-x--
---x
-x--
---- ----
---x --x- --x- --x- --x- --x- --x- --x- --x- -x----x ---x ---x ---x ---x ---x ---x ---x ---x x---
LEGEND:
/LO*/Q1
W*/Ol
/LO*UO*CBI*QO
/LO*/UO*CBI*/QO
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
= 1244
- : FUSE BLOWN
UO*CBI*QO*Q1*Q2*Q3*Q4~Q-
/UO*CBI*/OO*/Ql*/Q2*/Q3(H,P,l)
Octal Up/Down Counter
Logic Diagram PAL20X8
Octal Up/Down Counter
elK
1
G
,
1
Z
3
'S
I
J
•
"111
U 1314 15
1111111.
20212223
14 25262J
21213031
32]]3415
31313.39
.....
I
,z
MK
~
,•
""
~
::::::::::.
:R~D
-b-L
-
~
4
~9D-
"
"
"
......
-tW-
~
5
06
..
.""
~-
18
V
~
7
~~:D] ~17
~
"
"
-t:5--J-
.
.."
ID~
.
...
=:f9C>~
8
9
"
07
~
v
...
~
....
05
~
A...l!!
v
~
""J
:::::::9DB:::l
tlJ]
"
D4
~
t:rL.21
v
~??D~
.""
6
23
:::::~D
- tiIl~
"
03
J
-,--,
""
"
"
02
J
1-<1"
DO L-.
01
~-'
~
~
v
!J....
15
10
~
~
"
"
"
"
...L
hl5
051--:II:
{[ -06
06r-
Jiij ~ 07
. 071-UOOCCBO
-
E
E
~~l~'mIE
~
._-
YI
CARRY
~
!!~I
r-~
f3
o~o c't1ol- IziI
-
r-
i""""
14 r- 01
011- ~
~
1"5 r-- 02
021- ~
::
8
~
16 r- 03 BIT
031- 19
CNTR
~
f7 r- 04
041- 18
-
-
Ii -
......
05
"~-06
.liD - 07
=
1
NOTE: f MAX
-i71
06-E
i5I
071-UOOCCBO
-
~r----1
IE
05-
I'
1-~
lm:
..
CAiiRvi
BORROW
tpo ICLK TO CSO + tsu
10-Bit Counter
PAL20X10
elK
I
1 I---t>---.,
01
DATA
IN
02-7
3
08
5
iJj)
DATA
OUT
4-193
10-Blt Counter
PAL20XI0
74LS491
10-BIT COUNTER
MMI SUNNYVALE, CALIFORNIA
CLK DO 0102-7 08 09 /LD/CNT /UP SET /CIN GND
/oe Q9Q8 Q7 Q6 Q5 Q4 Q3 02 01 QO vec
/QO :=
PAL DESIGN SPECIFICATION
JOHN BIRKNER 04/01/81
/SET* LD*/DO
+ /SET*/LD*/QO
:+: /SET*/Lo* CNT* CIN* UP
+ /SET*/LD* CNT* CIN*/UP
/Q1 :=
/SET* LD*/D1
+ /SET*/LD*/Q1
:+: /SET*/LD* CNT* CIN* up* QO
+ /SET*/LD* CNT* CIN*/UP*/QO
/Q2 :=
/SET*LD*/D2-7
+ /SET*/LD*/Q2
:+.: /SET*/LD* CNT* CIN* up* QO*Q1
+ /SET:Ir/LD* CNT* CIN*/UP*/Qo*/Qi
/Q3 :=
/SE'l'* tD*/D2"'-7
+ /SET*/LD*/Q3
:+: /SET*/LD* CNT* CIN* up* QO* Q1* Q2
+ /SET*/LD* eNT* CIN* /UP* /QO* /Q1* iQ2.
/Q4 :=
/SET*LD*/D2-7
+ /SET*/LO*/Q4
:+:. /SET*/LD.* CNT* CIN* up* QO*Ql*Q2* Q3
+ /SET*/LD* CNT* eIN* /UP* /QO*/Ql */Q2* /Q3; ..
/Q5 :=
/SET* . LD* /02-7
+ /SET*/LD*/Q5
:+: /SET*/LD*·CNT* CIN* up* QO* Q1*Q2*Q3* Q4
+ /SET* /LD*·· CNT* CIN*/UP*/QO*/Q1*/Q2*/Q3*/Q4
/Q6 :=
/SET* LD*/D2-7
+ /SET*/LD*/Q6
:+: /SET*/LD* CNT* CIN* up* QO* Q1* Q2* Q3* Q4* 05
+ /SET*/LD* CNT* CIN*/UP*/QO*/Q1*/Q2*/Q3*/Q4*/Q5
/Q7 :=
/SET* LD*/D2-7
+ /SET*/LD*/Q7
:+: /SET*/LD* CNT* CIN* up* QO* Q1* Q2* Q3* Q4* Q5* Q6
+ /SET*/LD* CNT* CIN*/UP*/QO*/Q1*/Q2*/Q3*/Q4*/Q5*/Q6
/Q8 :=
/SET* LD*/D8
+ /SET*/LD*/Q8
:+; /SET*/LD* CNT* CIN* up* QO* Ql* Q2* Q3* 94* Q5* Q6* Q7
+ /SET*/LD* CNT* CIN*/UP*/QO*/Q1*/Q2*/Q3*/Q4*/Q5*/Q6*/Q7
/Q9 : =
+
:+:
+
4-194
/SET* LD* /09
/SET*/LD*/Q9
/SET*/LD* CNT* CIN* up* QO* Q1* Q2* Q3* Q4* Q5* Q6* Q7* Q8
/SET*/LD* CNT* CIN*/UP*/90*/Ql*/Q2*/Q3*/Q4*/Q5*/Q6*/Q7*/Q8
;LOAD DO
; HOLD (LSB)
; INCREMENT
; DECREMENT
; LOAD 01
; HOLD
; INCREMENT
; DECREMENT
; LOAD. 02-7
; HOLD
;INC~T
;DEcaEMENT
;LOAD 02-7
;HO~D'
; INCREMENT
;DECR,EMENT
;LOAD 02-7
;HOLD
; INCREMENT
: DECREMENT
;LOAD 02":7
; HOLD
; INCREMENT
; DECREMENT
;LOAD 02-7
; HOLD
; INCREMENT
; DECREMENT
;LOAD 02-7
; HOLD
; INCREMENT
; DECREMENT
;LOAD 08
; HOLD
; INCREMENT
; DECREMENT
; LOAD 09
;HOLD (MSB)
;INCREMENT
;DECREMENT
1 O-Bit Counter
FUNCTION TABLE
CLK 10C SET ILD ICNT ICIN Iup 09 08 02-7 01 DO 09 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
I I
;C I SIC C I -DATA IN;L 0 E L N I U DO 0 DO
;K C TOT N P 98 2-7 10
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
I,
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1.
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
X
X
X
X
H
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
L
X
L
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
X
xx x
LL
HH
LL
LL
L
H
L
L
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
LL
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
XX
LL
XX
X
H
X
XX
HH
XX
X
L
X
XX
LH
XX
X
L
X
XX
HL
XX
X
H
X
XX
HH
HH
X
H
H
xx x
xx x
xx x
xx x
xx x
xx x
XX
LL
HH
LL
LL
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
LL
XX
XX
XX
LL
XX
XX
XX
HH
XX
XX
XX
HL
XX
XX
XX
LH
XX
XX
XX
HH
HH
xx x xx
-DATA OUTQQQQQQQQQQ
9876543210
COMMENT
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLH
LLLLLLLLHL
LLLLLLLLHH
LLLLLLLHLL
LLLLLLLLHH
LLLLLLLLHL
LLLLLLLLLH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHL
HHHHHHHHLH
HHHHHHHHLL
HHHHHHHLHH
HHHHHHHLHL
HHHHHHHLLH
HHHHHHHLLL
LLLLLLLLLL
LLLLLLLLLH
LLLLLLLLLH
LLLLLLLLLL
LLHHHHHHLL
LLHHHHHHLH
LLHHHHHHLH
LLHHHHHHLL
HHLLLLLLHH
HHLLLLLHLL
HHLLLLLHLL
HHLLLLLLHH
LHLLLLLLHL
LHLLLLLLHH
LHLLLLLLHH
LHLLLLLLHL
HLHHHHHHLH
HLHHHHHHHL
HLHHHHHHHL
HLHHHHHHLH
HHHHHHHHHH
LLLLLLLLLL
ZZZZZZZZZZ
SET (SET=H)
CLEAR (D=L)
SET (D=H)
HOLD (lCNT=H)
CLEAR (D=L)
HOLD (lCNT=H)
HOLD (lCIN=H)
COUNT UP (NOTE 5 CNTRLS LOW NEAR GND)
COUNT UP
COUNT UP
COUNT UP
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN (ROLL UNDER)
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
LOAD
COUNT UP
HOLD (lCNT=H)
COUNT DOWN
LOAD
COUNT UP
HOLD (lCNT=H)
COUNT DOWN
LOAD
COUNT UP
HOW (lCNT=H)
COUNT DOWN
LOAD
COUNT UP
HOLD (lCNT=H)
COUNT DOWN
LOAD
COUNT UP
HOLD (lCNT=H)
COUNT DOWN
LOAD
COUNT UP (ROLL OVER)
TEST HI-Z
4-195
10·8it,Counter
DESCRIPTION
THE 10-BIT COUNTER CAN COUNT UP, COUNT DOWN, SET, AND LOAD 2 LSB'S (DO,DI),
2 MSB'S (D8,D9) AND 6 MIDDLE BITS (D2-7) HIGH OR LOW AS A GROUP.
SET OVERRIDES LOAD (/LD), COUNT (/CNT), AND HOLD. LOAD' OVERRIDES COUNT.
COUNT IS CONDITIONAL ON CARRY IN (/CIN), OTHERWISE IT HOLDS.
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
OPERATIONS TABLE:
/OC
CLK
SET
/LD
H
L
L
L
L
L
L
X
C
C
C
C
C
C
X
H
L
L
L
L
L
X
X
L
H
H
H
H
/CNT
/CIN
/UP
D9~DO
Q9-QO
X
X
X
H
L
L
L
X
X
X
X
H
L
L
X
X
X
X
X
L
H
X
X
D
X
X
X
X
Z
H
D
Q
Q
Q PLUS I
Q MINUS I
OPERATION
HI-Z
SET ALL HIGH
LOAD D
HOLD (/CNT... H)
HOLD (/CIN=H)
INCREMENT
DECREMENT
--------------------------------------------------------------------------
•• 11.6
1 O-Bit Counter
10-BIT COUNl'ER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
CXXXXXXXXlXXOHHHHHHHHHHl
COOOOOOXXOXXOLLLLLLLLLLI
ClllllOXXOXXOHHHHHHHHHHl
COOOOOllXOXXOHHHHHHHHHHl
COOOOOOXXOXXOLLLLLLLLLLI
CXXXXXllXOXXOLLLLLLLLLLl
CXXXXXlOXOlXOLLLLLLLLLLl
CXXXXXlOOOOXOLLLLLLLLLHl
CXXXXXlOOOOXOLLLLLLLLHLl
CXXXXX10000XOLLLLLLLLHH1
CXXXXXlOOOOXOLLLLLLLHLLl
CXXXXX10l00XOLLLLLLLLHHl
CXXXXXlOlOOXOLLLLLLLLHLl
CXXXXXl0100XOLLLLLLLLLHl
CXXXXXlOlOOXOLLLLLLLLLLl
CXXXX?{10100XOHHHHHHHHHHl
CXXXXX10100XOHHHHHHHHHLl
cxXXXXlOlOOXOHHHHHHHHLH1
CXXXXXlOlOOXOHHHHHHHHLLl
CXXXXXl0100XOHHHHHHHLHH1
CXXXXX10100XOHHHHHHHLHL1
CXXXXXl0100XOHHHHHHHLLHl
CXXXXXlOlOOXOHHHHHHHLLLl
coqooOOXXOXXOLLLLLLLLLLl
CXXXXXlOOOOXOLLLLLLLLLHl
cxxXXXllXOXXOLLLLLLLLLH1
CXXXXX10100XOLLLLLLLLLL1
COOlOOOXXOXXOLLHHHHHHLLl
CXXXXXlOOOOXOLLHHHHHHLHl
CXXXXXllXOXXOLLHHHHHHLH1
CXXXXXlOlOOXOLLHHHHHHLLl
CllOl10XXOXXOHHLLLLLLHHl
CXXXXXI0000XOHHLLLLLHLL1
CXXXXXllXOXXOHHLLLLLHLLl
CXXXXXlOlOOXOHHLLLLLLHHl
COlOlOOxxOXXOLHLLLLLLHLl
CXXXXXlOOOOXOLHLLLLLLHHl
CXXXXXllXOXXOLHLLLLLLHHl
CXXXXXlOlOOXOLHLLLLLLHLl
ClOlOlOXXOXXOHLHHHHHHLHl
CXXXXXlOOOOXOHLHHHHHHHLl
CXXXXXllXOXXOHLHHHHHHHLl
cxxxxxlPlOOXOHLHHHHHHLHl
C11lll0XXOXXOHHHHHHHHHHl
C11llll0000XOLLLLLLLLLLl
XXXXXXXXXXXXlZZZZZZZZZZl
PASS SIMULATION
4-197
10..Bit Counter
10-BIT COUNTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
o -x-- ---- ---- ---- ---- -x-1 --x --- --- --- --- x2 --- ---- ---- ---- ---- x--3 --- --- ------ ---- x--
---- ---- -x-- ----x-- -x- -x~ -x--x- x--- -x-- -x--
/SET*LD*/DO
--- --- -x-- ---- /SET*/LD*/QO
/SET*/LD*CNT*CIN*UP
/SET*/LD*CNT*CIN*/up
-x----x
------
----------
------------
-----------
-xx-x--x--
-------x--x--
-------x-x---
-x--x--x--x--
-------x--x--
/SET*LD*/Dl
/SET*/LD*/Ql
/SET*/LD*CNT*CIN*UP*QO
/SET*/LD*CNT*CIN*/UP*/QO
16 --- --17 --- ---18 --x- -x19 - .. x --x
-x----x
------
----------
-----------
-xx--x--x--
-------x-x--
-------x-x--
-x--x--x--x--
-------x--x--
/S~*LD*/D2-7
24 ---- --- -x25 --- --- ---26 -x- --x- --x27 ---x --x --x
------x
------
----------
-x- ---- ---- -x-x-- ---- ---- -xx-- -x- -x- -x-x-- -x- x- -x-
------x--x-
/SET*LD*/D2-7
/SET*/LD*/Q3
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q-
32 --- ---~ -x-- --33 --- ---- - - ---34 -x- --x- --x- -x35 -x --x --x --x
---x
------
-x-- ---x----x-- -xx-- -x-
---- -x-- ------ -x- ----x-- -x~- -x-x- -x-- -X--
/SET*LD*/D2-7
/SET*/LD*/Q4
/SET*/LD*CNT*CIN*UP*QO*/SET* /LD*CNT*CIN* /UP* /Q-
40 --- ---x-- --41 --- --- --- - - --- x-x - 42 -x- --x- --x- --x- --x- X- -x43 ---x ---x --x --x -x x-- -X--
---- -x-- ------ -X';"- - - -x- -x-- -x-x--- -x-- -X--
/SET*LD* /D2-7
/BET*/LD*/Q5
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q-
48 ---- ---- -x-- ---- ---49 --- ---- ---- ---- --50 -x- --x- --x- --x- --x51 --x --x ---x --x ---x
-x-x--x_xx-x
-------x-x---
------x--x--
/SET*LD*/D2-7
/SET*/LD*/Q6
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q-
56 --- ---- -x- ---- ---57 --- ---- --- ---- ---58 --x- --x- --x- --x- --x59 --x ---x --x --x --x
-x-- ---- --- -x-- --x-- ---- ---x -x-- --x-x- -xx- -x- -X-- -xx--x -X-X x-- -x-- -x--
/SET*LD*/D2-7
/SET*/LD*/Q7
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*C!N*/UP*/Q-
64 ---- ---- ---- -x-- ---65 --- ---- ---- --- --66 -x- --x- --x- --x- --x67 --x ---x ---x --x ---x
-xx-x-xx-x
---- --- -x- ------- ---- -x-x ---xx- -XX- -x-- -x--x-x x--x -x-- -x-
/SET*LD*/D8
/SET*/LD*/Qa
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q-
72 ---- ---- ---- ---- -x-- -x- ---- ---- -x- --73 - - --- ---- --- ---- x--- ---- ---- -x-- --x
74 --x- --x- -x- --x- --x- x-x- -xx- -xx- -XX- -x-75 --x ---x --x--x --x x-x -x-x x--x -x-x -x-LEGEND: x: FUSE NOT BLOWN (I.,N,O)
- : FUSE BLOWN
NUMBER OF FUSES BLOW = 1350
/SET*LD*/D9
/SET*/LD*/Q9
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q(B,P,1)
8 --9 --10 -x11 --x
-x-- --- ----
4-198
-----x
-x-x--
-x--x--x--x--
/SET*/LD*/Q2
/SET*/LD*CNT*CIN*UP*QO*/SET*/LD*CNT*CIN*/UP*/Q-
10.. Bit Counter
Logic Diagram PAL20X10
10-Bit Counter
CLKL..{>
0121
4561
8
9 1011
1213 U 15
16111819
20212223
24252611
1S 293031
12 11 J4 35
36313839
~C> ~~
",
2
2
DO
~
.,
~DR-l
-
'"
"
01 ~~
~
~C>
"
"
"
"
02-7 ~~
.......
5
~D...........
22
n
"
"
09
6
...
.......- "
.......
~~D--K-J
.
"
~,
"
"
LO
7
~
..
8
~
~
~
v
Pi
~ 05
02
"
04
17
V
06
07
~
9
:)t
..
~
-
~=9c>
:(j:::)
~
'"\..J
~-
~
IJ.....
15
~c
14
~~~
"
"
"
"
11
Pi
~ 03
Q
jb
"
"
"
CIN
21
01
.......
"
"
10
~
~
Bl.
""
SET
~
22
::t
"
00
I.Jv
IDD-~.
49D-PI ~
'"
UP
-
~DRt
"
"
"
"
08
"
23
,..
~
o
1
2
1
4!i
6
I
8
910 II
121314 IS
16171119
2021
n
23
24252621
28293031
n
II J4 35
~
~
36313839
4-199
08
09
0
10·BitCounter
Application
CRT Horizontal Timing and Blanking
DOT
CLOCK
74LS491
PAL16L2
t----VHBLANK
I----VBLANK
1----1 ,I---SCAN BLANK
,HO
Hl H2 H3 H4 H5 H6 H7 HB H9
v
HORIZONTAL ADDRESS
NOTE: PAL 16L2 design is application dependent.
4·200
4-Bit Up/Down Counter with
Shift Register and Comparator
PAl16X4
:.: : : }
................. 15 A2
""""14 A3
...... 0 .....
t--t?ort----t 13 Gil
DATA
OUT
m
4.Bit Up/Down Counter with Shift Register and Comparator
PAL16X4
PAL DESIGN SPECIFICATION
SCNT4C
BIRKNER/COLI 10/31/81
4-BIT UP/DOWN COUNTER WITH SHIFT REGISTER AND COMPARATOR
MMI SUNNYVALE, CALIFORNIA
CLK 10 Il BO Bl B2 B3 12 CLR GND /OC /LIO /GE A3 A2 Al AD /LE /RIO VCC
IF (/12* 11*/10) RIO
=
(AO)
;SHIFT RIGHT OUT
/AO:=
+
/I2*/Il*/IO*(/AO)*/CLR
/I2*/Il* 10* (jBO) */CLR
+ /12* Il*/IO*(/Al)*/CLR
+
12* 11*
(/AO)*/CLR
:+: I2*/Il*/IO*/RIO
+
12* 11*/10* RIO
+
12* 11* 10* RIO
+
CLR
;HOLD AD
;LOAD BO (LSB)
;SHIFT RIGHT
; HOLD (INC AND DEC)
;SHIFT LEFT
;INCREMENT IF CARRY IN
;DECREMENT IF BORROW IN
;CLEAR LSB
/Al
/12*/11*/10* (/Al) */CLR
/12*/11* IO*(/Bl)*/CLR
/12* Il*/IO* (jA2) */CLR
12* 11*
(jA1) */CLR
:+: 12*/11*/10* (/AO)
12* Il*/IO*( AD)* RIO
+
+
12* Il* IO*(jAD)* RIO
+
CLR
;HOLD Ai
;LOAD Bl
:SHIFT RIGHT
: HOLD (INC AND DEC)
;SHIFT LEFT
iINCREMENT IF CARRY IN
iDECREMENT IF BORROW IN
: CLEAR
/12*/11*/10* (/A2) */CLR
/12*/11* IO*(/B2)*/CLR
/12* Il*/IO* (jA3) */CLR
12* 11*
(jA2) */CLR
+
:+: I2*/Il*/IO* (jAl)
+
12* 11*/10*( Al)*( AO)* RIO
+
12* 11* IO*(/A1)*(/AO)* RIO
CLR
+
:HOLD A2
iLOAD B2
iSHIFT RIGHT
;HOLD (INC AND DEC)
;SHIFT LEFT
: INCREMENT IF CARRY IN
; DECRF..MENT IF BORROW IN
; CLEAR
:~
+
+
+
/A2 :=
+
+
/A3 :=
/12*/11*/10* (/A3) */CLR
/12*/11* IO*(/B3)*/CLR
/12* 11*/10* /LIO*/CLR
12* 11*
(/A3) */CLR
+
:+: I2*/Il*/IO* (jA2)
+
12* 11*/10*( A2)*( Al)*( AO)* RIO
12* 11* IO*(/A2)*(/Al)*(/AO)* RIO
+
CLR
+
+
+
IF
(
12) LIO
I2*/Il*/IO*( A3)
+ 12* 11*/10*( A3)*( A2)*( Al)*( AO)* RIO
+ 12* 11* IO*(/A3)*(/A2)*(/Al)*(/AO)* RIO
IF (VCC)
IF (VCC)
4·202
LE
iHOLD A3
iLOAD B3 (MSB)
iSHIFT RIGHT
; HOLD (INC AND DEC)
;SHIFT LEFT
; INCREMENT IF CARRY IN
iDECREMENT IF BORROW IN
;CLEAR MSB
;SHIFT LEFT OUT
;CARRY OUT
;BORROW OUT
+
+
+
+
(A3*/B3)
(A3:*:B3)*(A2*/B2)
(A3:*:B3)*(A2:*:B2)*(Al*/Bl)
(A3:*:B3)*(A2:*:B2)*(Al:*:Bl)*(AO*/BO)
(A3:*:B3)*(A2:*:B2)*(Al:*:Bl)*(AO:*:BO)
;B3
;B2
;Bl
;BO
;B
+
+
+
+
(jA3*B3)
(A3:*:B3)*(/A2*B2)
(A3:*:B3)*(A2:*:B2)*(/Al*Bl)
(A3:*:B3)*(A2:*:B2)*(Al:*:Bl)*(/AO*BO)
(A3:*:B3)*(A2:*:B2)*(Al:*:B1)*(AO:*:BO)
;B3 GT
iB2 GT
i Bl GT
iBO GT
i B EQ
GE
LT A3
LT A2
LT Ai
LT AD
EQA
A3
A2
Al
AD
A
4·Bit Up/Down Counter with Shift Register and Comparator
FUNCTION TABLE
CLK 10C CLR 12 11 10 B3 B2 B1 BO IGE lLE ILIO IRIO A3 A2 A1 AO
1
,--CONTROL-,CLK 10C CLR
INST INPUT
III BBBB
STATUS
210 3210 IGE lLE
OUTPUT
---1/0--ILIO IRIO
AAAA
3210
COMMENTS
(HEX VALUES)
------------------------------------------------------------------------------C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
C
C
L
C
L
C
C
C
C
L
L
L
L
C
C
L
L
C
C
C
L
L
L
L
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
C
C
C
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
xxx
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
LHL
LHL
LLL
LHL
LLL
LHL
LHL
HLH
LLL
HLL
HLL
HLL
HLL
HLL
LLH
HHL
HHH
LLH
HHL
HHIi
LLH
HHL
HHH
LLH
LLH
LLH
LLH
LLH
LLH
HHL
HHL
LLL
HHL
HHL
HHL
HHL
HHL
LHH
HHH
LLH
HHH
HHH
HHH
HHH
HHH
XXX
L
L
L
L
L
L
L
L
L
X
XXXX
XXXX
XXXX
LHLH
XXXX
LLHL
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
LLLH
XXXX
XXXX
LLHH
XXXX
XXXX
LHHH
XXXX
XXXX
HHHH·
LHHH
HLHH
HHLH
HHHL
bLHL·
XXXX
XXXX
HLHH
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
LLHH
XXXX
LLHL
XXXX
XXXX
XXXX
XXXX
x
x
X
L
X
L
X
X
X
X
X
X
X
X
x
x
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
x
x
X
H
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z
L
H
Z
H
Z
H
H
H
Z
L
L
L
H
L
Z
H
H
Z
H
H
Z
H
H
Z
Z
Z
Z
Z
Z
·H
H
Z
H
H
H
L
H
Z
H
Z
H
H
H
L
H
X
Z
H
H
Z
H
Z
L
H
Z
Z
H
L
L
L
L
Z
L
L
Z
L
L
Z
L
L
Z
Z
Z
Z
Z
Z
L
L
Z
L
H
L
L
L
Z
L
Z
L
H
L
L
L
X
LLLL
HLLL
LHLL
LHLL
LLHL
LLHL
LLLH
LLLL
HHHH
HHHH
HHHL
HHLH
HLHH
LHHH
HHHH
LLLH
LLHL
LLLH
LLHH
LHLL
LLHH
LHHH
HLLL·
LHHH
HHHH
LHHH
HLHH
HHLH
HHHL
HLHL
HLHH
HHLL
HHLL
HHLH
HHLH
HHHL
HHHH
LLLL
HHHH
HHHL
LLHH
LLHL
LLHL
LLLH
LLLL
HHHH
ZZZZ
CLEAR
SHIFT RIGHT IN A H
SHIFT RIGHT IN A L
COMPARE B GT A
SHIFT RIGHT INA L
COMPARE B EO A
SHIFT RIGHT IN A L
SHIFT RIGHT IN A L
SET
HOLD
SHIFT LEFT IN A L
SHIFT LEFT IN A H
SHIFT LSFT IN A H
SHIFT LEFT IN A H
SHIFT LEFT IN A H
LOAD (1)
INCREMENT
DECREMENT
LOAD ()
INCREMENT
DECREMENT
LOAD (7)
INCREMENT
DECREMENT
LOAD (F)
LOAD (7)
LOAD {Bl
LOAD (D)
LOAD (E)
LOAD (AI
INCREMENT TO {Bl
INCREMENT TO (C)
COMPAREB LT A
INCREMENT TO (D)
HOLD NO CARRY IN (/RIO=H)
INCREMENT TO {El
INCREME~ TO (F) CARRY OUT
INCREMENT TO {OIROLL.OVER
SET
DECREMENT TO (El
LOAD (3)
DECREMENT TO( 2)
COMPARE B EQ A
DECREMENT TO (1)
DECREMENT TO {O)BOROW OUT
DECREMENT TO (F) ROLL UNDR
TEST HI-Z
4.~03
4-Bit Up/Down Counter with Shift Register and Comparator
DESCRIPTION
THE 4-BIT UP/DOWN COUNTER WITH SHIFT REGISTER AND COMPARATOR WILL COUNT UP,
COUNT DOWN, SHIFT RIGHT, SHIFT LEFT, COMPARE GREATER THAN OR EQUAL TO, COMPARE
LESS THAN OR EQUAL TO, CLEAR, SET, LOAD, OR HOLD AS SPECIFIED BY THE INSTRUCTION LINES (12,11,10) AND CLEAR (CLR). ALL OPERATIONS OCCUR SYNCHRONOUSLY ON
THE RISING EDGE OF THE CLOCK (CLK) EXCEPT FOR THE COMPARISION OPERATIONS WHICH
ARE PERFORMED ASYNCHRONOUSLY AND WITH NO INSTRUCTION LINES REQUIRED.
THE COMPARISION OPERATIONS (/GE AND /LE) WILL COMPARE THE INPUT DATA (B) WITH
THE DATA IN THE REGISTERS (A) AND SUPPLY THE FOLLOWING STATUS:
! COMPARISION
/GE
/LE
!---------------------!---------------!
B IS GREATER THAN A
IS EQUAL TO A
! B IS LESS THAN A
I B
L
L
H
H
L
L
NOTE THAT BORROW, CARRY, AND SHIFT LEFT AND RIGHT INPUT/OUTPUTS SHARE THE SAME
I/O LINES (/LIO AND /RIO) AND THESE LINES ARE INVERTED (ACTIVE LOW).
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN
THE OPERATIONS TABLE BELOW:
/OC CLK
H
L
L
L
L
L
L
L
L
L
CLR
X
H
L
L
L
L
L
L
L
L
X
C
C
C
C
C
C
C
c
C
12 II 10
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
B3-BO
/GE /LE
/LIO /RIO
X
X
X
B
X
X
X
X
X
X
STATUS
X X
STATUS
X X
STATUS
X X
STATUS
X X
STATUS
STATUS
X
X
X
X
RI
Z
A3
H
COUT
SOUT
B
MSB SHIFT
I/O~
OP SELECT
LSB SHIFT I/O
2
A
X
X
X
X
AO
Z
LI
Z
CIN
BIN
A3-AO
Z
L
A
B
SR(RIO)
H
SL(LIO)
H
A PLUS 1
A MINUS 1
OPERATION
HI-Z
CLEAR
HOLD
tOAD B
SHIFT RIGHT
SET
SHIFT LEFT
SE'+
INCREMENT IF CIN
DECREMENT IF BIN
4'!"Bit Up/Down Counter with Shift Register and Comparator
4-BIT UP/DOWN COUNTER WITH SHIFT REGISTER AND COMPARATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
CXXXXXXXIXOZXLLLLXZl
COIXXXXOOXOOXHLLLXHI
COIXXXXOOxOlXLHLLXHl
COOIOIOOOXOZLLHLLHZl
COIXXXXOOXOIXLLHLXHI
COOOIOOOOXOZLLLHLLZI
COIXXXXOOXOIXLLLHXLI
COIXXXXOOXOIXLLLLXHI
CI0XXXXIOXOHXHHHHXZl
COOXXXXOOXOZXHHHHXZl
COOXXXXI0XOLXHHHLXll
COOXXXXI0XOLXHHLHXOI
COOXXXXI0XOLXHLHHXOI
COOXXXXIOXOHXLHHHXOI
COOXXXXI0XOLXHHHHXOI
CI0100000XOZXLLLHXZl
COIXXXXIOXOHXLLHLXOI
Cl1XXXXI0XOHXLLLHXOl
CIOl10000XOZXLLHHXZl
COIXXXXIOXOHXLHLLXOI
CIIXXXXIOxOHXLLHHXOl
CIOIII000XOZXLHHHXZl
COIXXXXIOxOHXHLLLXOI
Cl1XXXXlOXOHXLHHHXOl
CIOllllOOXOZXHHHHXZl
CI0111000XOZXLHHHXZl
CIOIIOIOOXOZXHLHHXZl
CIOI01100xOZXHHLHXZI
CI00l1100xOZXHHHLXzl
CIOOIOIOOXOZXHLHLXZl
COlxXXXlOXOHXHLHHXOl
COIXXXXIOXOHXHHLLXOI
COOIIOIOOXOZHHHLLLZI
COIXXXXIOXOHXHHLHXOI
COIXXXXIOXOHXHHLHXll
COIXXXXIOXOHXHHHLXOI
COIXXXXI0XOLXHHHHXOI
COIXXXXIOXORXLLLLXOI
CIIXXXXOOXOZXHHHHXZl
CIIXXXXIOXOHXHHHLXOI
CIOIIOOOOXOZXLLHHXZl
CIIXXXXI0XOHXLLHLXOI
OllOlOOlOXOHXLLHLXll
CIIXXXXIOXOHXLLLHXOI
CIIXXXXIOXOLXLLLLXOI
CIIXXXXIOXOHXHHHHXOI
XXXXXXXXXXIXXZZZZXXI
m
PASS SIMULATION
4-205
.,..ait Up/Dow,n Counter with Shift Register and· Comparator
4-5IT
COUNTER WITH SHIFT REGISTER AND COMPARATOR
.
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
UP/DOWN
0 -x-1 ---8
9
10
11
12
13
x--- -----xx
----
-xxx
---- -xxx x--x
-xxx x--x x--x
x--x x--x x--x
xx--x-x
xx-xx----"-
16
17
18
19
20
21
22
23
-x-- -x-x--- -x--x-,.. x--x---xx- -x--x-x x--x--x x---
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
xx--x-- -x-x--- -x--x-x
-x-- x--xx-xx-x---x-- -x-- xx--x-x x--- --xx ---x--x x--- xx-- ----
40
41
-x--
~--""I"
-xxx ---x--x ---x--x
x--x
x--x
-x--x--x-x--x--x--x---x--x--x-x--x--x--x---
---- ----
---------------
---------xxxx--x
---~
---- ---- ----
---- ---~--- xxxxxx- x--x
x--x x--x
x--x x--x
xxxx--x
x--x
x--x
x...,-x
-------------
-x--x--x--x--
"
x---x--x--x--x--
----------------
/I2*/Il*/IO*/AO*/CLR
/I2*/Il*IO*/BO*/CLR
/I2*Il*/IO*/Al*/CLR
I2*Il*/AO*/CLR
I2*/Il*/IO*/RIO
I2*Il*/IO*RIO
I2*Il*IO*RIO
.CLR
/I2*/Il*/IO*/Al*/CLR
/I2*/Il*IO*/Bl*/CLR
/I2*Il*/IO*/A2*/CLR
I2*Il*/Al*/CLR
I2*/Il*/IO*/AO
12*Il*/IO*AO*RIO
12*Il*IO*/AO*RIO
CLR
/I2*/Il*/IO*/A2*/CLR
/I2*/Il*IO*/52*/CLR
/I2*Il*/IO*/A3*/CLR
I2*Il*/A2*/CLR
I2*/Il*/IO*/Al
I2*Il*/IO*Al*AO*RIO
12*Il*IO*/Al*/AO*RIO
CLR
/I2*/Il*/IO*/A3*/CLR
/I2*/Il*IO*/B3*/CLR
/I2*Il*/IO*/LIO*/CLR "'"'.',.,
12*Il*/A3*/CLR
12*/Il*/IO*/A2
12*Il*/IO*A2*Al*AO*RIO
12*Il *10* /A2* /Al */AO*R~O'
CLR
"
\,-
/A3*B3
A3:*:53*/A2*B2
A3:*:B3*A2:*:B2*/Al*Bl
A3:*:B3*A2:*:B2*Al:*:Bl*/AO*BO
A3:*:B3*A2:*:B2*Al:*:Bl*AO:*:BO
12
56
---- ---- ---- -,--- x--12*/Il*/I0*A3
57 -x-~ -x----- --xx x--12*Il*/IO*A3*A2*Al*AO*R10
58 -x-x x--- --xx --xx --xx --xx x--12*Il*IO*/A3*/A2*/Al*/AO*RIO
59 x--x x--- xx-- xx-- xx-- xx-- x--(H,p,l)
LEGEND: x: FUSE NOT BLOWN (L,N,O)
- : FUSE BLOWN
NUMBER OF FUSES BLOWN = 1331
4 .. 208.
.,
---- A3*/53
---- A3:*:53*A2*/52
,.;",
A3:*:53*A2:*:52*Al*/51
A3:*:53*A2:*:52*Al:*:51*AO*/50
A3:*:53*A2:*:52*Al:*:Bl*AO:*:BO
---- ---x--xx--x-- -x--x-- -x-x--- -x--x-x ---- -x-- -x--x-- x--xx-- -x-- -x-x--xx-x--- -x--x-- -x-xx-x---x-x x--- --xx --xx
x--x--x x--- xx-- xx-x------ ---- x------ ---xx-- -x-- -x--x-- -x-- ---- ---x--- -x-- ---- ----x-x -x-- -x--x-- x--- ---- ----x-- -xxxx-- x--- -x-x--- ---- ----x-- -x-- ---- ---- xx-- ---- x--oo:x-x x--- --xx --xx --xx ---- x--x--x x--- xx-- xx-- xx--'
x------ ---x---
42
43
44
45
46
47
48
49
50
51 ---52
53
;,:
/I2*Il*/IO
---- AO
'
4-Bit Up/Down Counter with Shift Register and Comparator
4-Bit Up/Down Counter
with Shift Register and Comparator
ClK
Logic Diagram PAL16X4
I
0123
4 S 67
891011
12131415
16171819
20212223
24252621
28293031
0
I
~
~
2
3
4
5
6
10
2
...
...
,
,,
IQ
11
12
13
14
11
3
...
...
15
16
17
18
19
21
80
~24
FL~D- ~~1 ~
A1
'"""'
25
26
27
t-
28
"
30
31
~31
33
34
35
'""""
36
37
"
~
-----
40
41
42
:=::
44
45
46
47
,
fi]""
50
51
"
53
8
..
...
54
55
""
""
61
"
ClR
9
..
01---
A2
~D-U-~
A3
~
43
12
D
~
fi
~
83
~J).-
./
38
82
....--
~
;
81
AD
22
23
4
18
~D- ~~-~
~L!l
"'"
20
19
"
53
0123
4567
891011
12131415
16171819
Z0212223
24252627
2829J031
~
~
~
13
.
12
~
4-207
Notes
4.208
4·Bit Flash Gray
A/D Converter
PAL20X4
4·209
4·Bit Flash Gray A/D Converter
A/D and D/ A Converters
4-Bit Flash Gray AID Converter.
ClK
R
A6
R
A7
R
AS
R
A9
VCC
NC
AS.
R
A4
IGO
•
R
A10
R
A11
R
A12
R
A13
R
A14
R
A1S
VIN
************** **************
*
*
* *
****
****
* 1*
*24*
PAL
****
****
*
*
20x4
*>11**
****
* 2*
*23*
****
****
*
*
****
****
* 3*
*22*
****
****
*
*
****'.'
****
* 4*
*21*
****
****
*
*
****
****
>11 5*
*20*
****
****
*
****
****
* 6*
*19*
****
****
*
*
****
****
*7*
*18*
****
****
*
*
****
****
* 8*
*17*
****
****
*
*
**it*
****
* 9*
*16*
****
****
*
*
****
****
*10*
*15*
****
****
*
*
****
****
*14*
*11*
****
****
*
*
****
****
*12*
*13*
****
****
*
••
R
GNI)
IG1
4-BIT
GRAY
OUT
IG2
-/G3
R
A3
A2
R
A1'
R
IOC
*************.***.***~**********~
4-21:1
D
4-Blt Flash Gray ,AID Converter
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/29/81
PAL20X4
ADC4
4-BIT PIASH GRAY A/D CONVERTER
MMI SUNNYVALE, CALIFORNIA
CLK A6 A7 AS A9 AlO All Al2 Al3 Al4 Al5 GND
/OC Al A2 Al /G3 /G2 /Gl /GO A4 AS NC vec
IAl
GO :=
+ IA7
*
*
Al
AS
,CONVERT ANALOG TO GO (LSB)
:+: IAll* A9
+ IAl5* Al3
IA6
G1:=
*
A2
; CONVERT ANALOG TO Gl
+ IAl4* AlO
IAl2* A4
G2:=
AS
G3:.
; CONVERT ANALOG TO G2
;CONVERT ANALOG TO G3 (MSB)
FUNCTION TABLE
/OC CLK Al5 Al4 Al3 AlZ All AlO A9 AS A7 A6 AS All Al A2 Al G3 G2 Gl GO
ANALOG INPU'l'S
111111
543210987654321
GRAY
OUTPUTS
3210
C
C
C
C
C
C
C
C
C
LLLI,I,I,I,LLLI,I,I,LL
LLLLLLLLI,I,I,IJ,LH
LLLLLLLLLLLLLHH
LLLLLLI,IJ,IoI,I,HHH
LLLLLLLLLLLHHHH
LLLLLLLLLLHHHHH
LLLL
LLLH
LLHH
C
LLLLLLHHBHBBBBB
LLLLLHHHHHHHHHH
LLLJ:,HHBBHBBJffiHH
LLLttHttttBBBHBBHH
LLHHBBBBBBHHHHH
I,BBBBBBBBBBBBBH
; CONTROL
;/oe CLK
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
C
C
C
C
C
C
X
HHHHAHHHHaainma'
XXXXXXXXXXX~·.
LLHL
LHHL
LHHH
LHLH
LHLL
HHLL
HBLH
HHHH
HHHL
HLBL
HLHH
HLLH
HLLL
ZZZZ
COMMENTS
FRACTION OF VDlax
V-O
V-l/16
V-lI8
V=3/l6
V=1/4
V-S/16
V=3/8
V=7/16
V=1/2
V=9/16
V=S/8
V=1l/16
V=3/4
V=13/16
V=7/B
V=iS/16
TE~T HI-Z
-----------~----------------.---------------------------DESCRIPTION
THE 4-BIT FLASH ANAU)G-TO-DIGITAL CONVERTER CONVERTS AN ANALOG SIGNAL
INTO A 4-BIT GRAY CODE. GRAY CODE IS CHOSEN TO ELIMINATE GLITCHES AT
BINARY ROLL O~R POINTS.
THE MAXIUM SAMPLE RATE IS EQUAL TO l/tpd OF THE PAL20X4.
FEEDBACK PROPAGATION DELAY IS INTRODUCED.
A_"" "
NOTE THAT NO
4-Bit Flash Gray AID Converter
4-BIT FLASH GRAY A/D CONVERTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COOOOOOOOOOXOOOOHHHHOOX1
COOOOOOOOOOX0100BHSLOOXl
COOOOOOOOOOX0110HHLLOOXl
cooooooooooxOl11HBLHOOXl
COOOOOOOOOOXOll1BLLHlOXl
COOOOOOOOOOXOll1HLLLllXl
ClOOOOOOOOOXOlllHLHLl1Xl
Cl100000000X0111BLHHl1Xl
Cl110000000X0111tLHHl1Xl
C1111000000X0111LLHLl1Xl
C1111100000X0111LLLL11Xl
C1111110000X0111LLLHl1Xl
Cll11111000X0111LHLBlIXl
C1111111100XOll1LHLLl1Xl
Cll11111110X0111LHHLl1Xl
Cl11111111lX0111LHHBlIXl
17 XXXXXXXXXXXXlXXXZZZZXXXl
PASS SIMULATION
,
'
4-213
4-8it Flash Gray AID Converter
4-BIT FLASH GRAY A/D CONVERTER
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
24
25
26
27
-------------
----XX-------
-------------
------X------
---- --- ---- ---x ---- --x- - ---- --- - - --- ------- -x- ---- --- --- ------- ---- --- X--- ---- -X--
/A3*Al
/A7*A5
/Al1*A9
/Al5*Al3
32 -x- ---- --- ---- - - ---- ---- ---- --X- ---- /A6*A2
33 ---- ---- --- ---- X--- ---- --- ---- -X-- ---- /Al4*AlO
40 --- --- --X- - - - - - - ----
-x- --- - - ----
/Al2*A4
48 ---- --- X - ---- - - - ---- - - - - - - - ---- AS
LEGEND:
X: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
4.214
=
305
- : FUSE BLOWN
(H,P,l)
4-Bit Flash Gray A/D Converter
Logic Diagram PAL20X4
4-Bit Flash Gray A/D Converter
ClK
1
......
-V'lll
0
,
,
1
A6
~
.,
""
A7
3
""
"
"
A8 4
A9 ~
"
"
"
"
6
.
"
"
.
A11
7
1
• • 1011
12 131<1115
I. UI'"
tor, u u
N ZSH17
II J! H II
U 33)1 35
n
11 JlJI
-.
.J
-wK
23
.....
....
......
1
.J
22
...L
21
- :1
....
IA(
NC
J]
AS
A4
~
"
"
"
"
A10
45'
=~D- ~~
......
-
-~=9D- ~ ~
IDD-
~
'""J
18
~~r>~
'"....."J
17
~
....
so '
so
~
.J.t..
V
A12 ~
"
"
"
~
...
.....
51
A13
9
L..ri)l
..L
16
A3
15
A2
1'"
A1
-'1::1--
H
"
A14 1Lt~
"
""
"
A15 !!.....t~
....
IA(
-
»
J
-,rvl
.J.
-C~
,
A
;....-
13,
Notes
4-Bit Gray DI A Converter
PAL16A4
4·Bit Gray DI A Converter
**************
**************
*
* *
*
****
****
CLK * 1*
PAL
*20* VCC
****
****
*
1 6 R 4
*
****
****
' ',R
N,C *2*
...,
*19* AO
*fI**
****
*
*
****
****
2R
NC * 3*
*18* A1
****
****
*
*
****
lI',***
GO ~ 4*
*17* lab '
****
***'*
*
*
****
'11***
'G1 * 5*
*16* 181 "
4-BIT
****
*'***
GRAY
*
*
IN
****
*'1\;'*
*15,* tB2
****
**** ;
*'
*
****
****
'G3* 7*
*14* /83
****
'****
*
*
****
****
4R
NC* 8*
*13* A2
****
****
*
*
****
****
8R
/OC2 * 9*
*12* A3
****
****
*
*
****
****
GND*10*
*11* /OC1
****
****
vcc
~.,
*
*
*******************************
2N
NOTE: EACH BIT CONTRIBUTES 16 VOLTS
WHERE N = THE SUBSCRIPT OF B
4.218
ANALOG
OUT
R
Vo
4-Bit Gray. D/A Conv.erter
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/30/81
PAL16R4
DAC4
4-BIT GRAY O/A CONVERTER
MMI SUNNYVALE, CALIFORNIA
CLK NC NC GO G1 G2 G3 NC /OC2 GND
/oel A] A2 /83 /B2 /81 /80 Al All vec
BO :=
/GO* G1*' G2* G3 ,CONVERT GRAY TO
'I:
so
(LSB)
+ GO*/G1* G2* G3
+ GO* G1*/G2* G3
+ GO* Gl* G2* /G3
+ GO * /G1 * /G2 * /G3
+ /GO* Gl*/G2*/Gl
+ /GO*/G1* G2*/G3
+ /GO*/Gl*/G2* Gl
B1 :-
+
+
+
B2 :-
+
B3 :=
, CONVERT GRAY TO BI
/Gl*/G2* G3
/Gl*' G2*/G3
Gl*'/G2*/G3
Gl* G2* G3
/G2*' G3
G2*'/Gl
G3
IF (BO*OC2)
;.CONVERT GRAY TO B3 (MBB)
/AD = BO
1CONVERT
so
TO ANALOG
IF (Bl.*OC2) /Al =
81·
IF (B2*OC2) /A2 -
B2
, CONVERT B2 TO ANALOG
IF(B3*OC2) /A] =
B3
,CONVERT. 83 TO ANALOG.
4.;.219
4-8it'Qray:D/A Converter
FUNCTION TABLE
/OCl /OC2 CLK G3 G2 .Gl GO B3 B2 Bl BO A3 A2 Al AO
:---CONTROL--:/OCl /OC2 CLK
GRAY
3210
BCD
3210
ANALOG
3210
COMMENTS
FRACTION OF vmax
--------------------~-----------------------.------------1.
1.
1.
1.
L
1.
1.
1.
1.
1.
1.
1.
1.
1.
1.
L
H
X
L
L
L
L
L
L
L
L
L
L
C
C
C
C
C
C
C
C
C
C
C
1.
1.
1.
C
C
L
C
1.
C
C
X
X
t
x
H
LLLL
LLLH
LLHH
UHL
LHHL
LHHH
LHLH
LHLt
HHLL
HHLH
HHHH
HHHL
HLHL
HLHH
HLLH
HLLL
XXXX
XXXX
LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHt
LHHH
HLLL
HLLH
HtHL
HLHH
HHLL
HHLH
HHHL
HHHH
ZZZZ
XXXX
ZZZZ
ZZZL
ZZLZ
ZZLL
ZLZZ
ZLZL
ZLLZ
ZLLL
LZZZ
LZZL
LZLZ
LZLL
LLZZ
LLZL
LLLZ
1.1.1.1.
XXXX
ZZZZ
V=O
V=1/16
V=1/8
V=3/16
V=1/4
V=S/16
V=3/8
V=7/16
V=1/2
v=9/16
V=S/8
V=1l/16
V=3/4
V=13/16
V=7/8
V=lS/16
TEST HI-Z (REG)
TEST HI-Z (OC)
---------------------------------------------------------DESCRIPTION
THE 4-BIT FLASH DIGITAL-To-ANALOG CONVERTER CONvERTS A 4~BITGRAY CODE (G)
INTO A 4-BIT BINARY CODE (B), wHICH IS THEN CONVERTED INTO ANALOG OUTPUTS (A).
ANALOG .OUTPUTS (A) ARE EITHER LOW OR HI-Z WHICH ALLOWS THE CONDITIONAL
THREE-STATE OUTPUTS TO PERtORM THE OPEN COLLECTOR FUNCTION THAT IS NEEDED TO
DRIVE THE RESISTOR NETWORK.
4-Bit Gray D/ A Converter
4-BIT GRAY D/A CONVERTER
1 CXXOOOOXOXOZZHHBHZZI
2 -d
.
NC 3
5
6
7
.
~
~
.
:>-d
9
17
12
Il
3
....Jt
AO
78
A1
~~
10
NC
19
"
75
d-16
17
19
"
10
11
11
GO
4
)--
of--~
'-
D
2J
.
.
.A
Jo..
~
'"
15
26
17
28
19
30
G1
5
...
"'
./
37
.A
~
~
~~
~
~
~
~
tD1
~
31
II
J4
"
35
36
17
./
J8
G2
6
...
J9
.A
...
...
"
"
,
41
4l
44
45
G3
7
..
./
"
41
A
~
..A
"
r-J
49
50
57
"
"
53
54
NC
8
....
"
"
"
""
r-J
57
61
..
.
13
A2
A..--t-....
~
5'
9
'""
.....
-.JC::I---~
o1
1 3
4 5 6 7
.8 9 1011
12131415
161718 19
20212223
24252627
2829 J031
12
A3
~
4·223
Notes
4·224
a-Bit D/ A Converter
PAL16L8
NC
vcc
AO
01
A1
A2
A3
04
A4
05
AS
A6
A7
GNO
4·225
D
8-Bit DI A Converter
8-BIT
DIGITAL
IN
************** **************
*
*
**
****
****
PAL
*20*
NC * 1*
****
****
1 6 L8
*
*
****
****
DO * 2*
*19*
****
****
*
*
****
****
01 * 3*
*18*
****
****
*
*
****
****
*17*
02 * 4*
****
****
*
*
****
****
03 * 5*
*16*
****
****
*
*
****
****
*15*
04 * 6*
****
****
*
*
****
****
05 * 7*
*14*
****
****
*
*
****
****
06 * 8*
*13*
****
****
*
*
****
****
07 * 9*
*12*
****
****
*
*
****
****
GNO *10*
*11*
****
****
*
*
*******************************
vcc
ANALOG
OUT
VCC
AO
A1
A2
A3
A4
A5
A6
A7
R
R
2R
4R
8R
16R
32R
64R
128R
IOC
NOTE: EACH BIT CONTRIBUTES : : VOLTS
WHERE N " THE SUBSCRIPT OF O.
Vo
a-Bit D/ A Converter
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/29/S1
PAL16L8
DACS
S-BIT D/A CONVERTER
MMI SUNNYVALE, CALIFORNIA
NC DO 01 02 03 04 05 D6 07 GND
/oe A7 A6 AS A4 A3 A2 Al AO vec
IF (OO*OC)
/AD =00
1CONVERT DO
TO ANALOG
IF (D1*OC)
/Al '" 01
1CONVER'l' 01
TO ANALOG
IF (D2*OC)
/A2 '" 02
1CONVERT 02
TO ANALOG
IF (D3*OC)
/A3 '" 03
1CONVERT 03
TO ANALOG
IF (04*OC)
/A4 =04
1CONVERT 04
TO ANALOG
IF (D5*OC)
/AS '" 05
1CONVERT 05
TO ANALOG
IF (D6*OC)
/A6 "06
1CONVERT D6
TO ANALOG
IF (D7*OC)
/A7 = 07
1CONVERT 07
TO ANALOG
(LSB)
(MSB)
FUNCTION TABLE
1/ DIGITAL IN
10 00000000
1C
76543210
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
LLLLLLLL
LLLLLLLH
LLLLLLHL
LLLLLLHH
LLLLLHLL
LLLLLHBH
LLLLHLLL
LLLLHBHB
LLLHLLLL
LLI.HHRRR
LLHLLLLL
LLHHBHHH
LHLLLLLL
LBBBHHHH
HLLLLLLL
HLLLLLHH
HLLLHHHH
HI,RAAAAR
HHHHBHHH
xxxxxxxx
ANALOG OUT
AAAAAAAA
76543210
COMMENTS
FRACTION OF
ZZZZZZZZ
ZZZZZZZL
ZZZZZZLZ
ZZZZZZLL
ZZZZZLZZ
ZZZZZLLL
ZZZZLZZZ
ZZZZLLLL
ZZZLZZZZ
ZZZLLLLL
ZZLZZZZZ
ZZLLLLLL
ZLZZZZZZ
ZLLLLLLL
LZZZZZZZ
LZZZZZLL
LZZZLLLL
LZLLLLLL
LLLLLLLL
ZZZZZZZZ
V-O
"'1/256
V=1/12S
V=3/256
V=1/64
V=7/256
V=1/32
V=15/256
V=1/16
V=31/256
V=l/S
".63/256
V=1/4
".127/256
V=l/2
".129/256
".141/256
V=lS9/256
".255/256
TEST HI-Z
vmax
4-227
\
\
8';'81t DI A Converter
DESCRIPTION
THIS PAL PERFORMS THE LOGIC NEEDED TO CONVERT AN 8-BIT DIGITAL SIGNAL INTO
A 256 INCREMENT ANALOG SIGNAL.
OUTPUTS'ARE EITHER LOW OR HI-Z WHICH ALLOWS THE CONDITIONAL THREE-STATE
OUTPUTS 'TO PERFORM THE OPEN COLLECTOR FUNCTION THAT IS NEEDED TO
DRIVE THE RESISTOR NETWORK.
4·228
\-
a-Bit D/ A Converter
8-BIT O/A CONVERTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XOOOOOOOOXOZZZZZZZZI
XI0000000XOZZZZZZZL1
XOI000000XOZZZZZZLZI
XII000000XOZZZZZZLLI
XOOI00000XOZZZZZLZZI
Xll100000XOZZZZZLLLl
XOOOI0000XOZZZZLZZZI
XIIII0000XOZZZZLLLLI
XOOOOI000XOZZZLZZZZI
XIIII1000XOZZZLLLLLl
XOOOOOI00XOZZLZZZZZI
Xlll11100XOZZLLLLLLl
XOOOOOOI0XOZLZZZZZZI
Xl1111110XOZLLLLLLLl
XOOOOOOOIXOLZZZZZZZI
xll000001XOLZZZZZLLl
XlIII000IXOLZZZLLLLl
Xllll1101XOLZLLLLLLl
Xlllll11IXOLLLLLLLLl
XXXXXXXXXXlZZZZZZZZl
PASS SIMULATION
4-229
a-Bit DI A Converter
8-BIT D/A CONVERTER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
0
1
---x
x--x---
8
9
16
17
24
25
DO*OC
DO
x--
x---
x---
x--x--x--x--
D2*OC
D2
---x
D3*OC
D3
---x
x--
41
---x
D4
x---
40
D1*OC
D1
---x D4*OC
x---
32
33
---x
D5*OC
D5
48
49
x--- ---x D6*OC
56
57
x--x
LEGEND:
x--
D6
D7*OC
x--- D7
X : FUSE NOT
NUMBER OF FUSES BLOWN
BLOWN (L,N,O)
488
FUSE BLOWN
(H,P,l)
a-Bit D/ A Converter
Logic Diagram PAL16L8
a-Bit D/ A Converter
NC
11123
4567
8911J1l
12131415
16171819
2021222J
24252627
28293031
0
;=J
1
2
J
4
5
6
19
AO
18
A1
17
A2
16
A3
7
DO
~
1
....' J - ,
8
10
11
12
lJ
01
J
..
..
"
f--
15
c
~
"
4
20
21
22
2J
.
..
~
~'~
....
24
~5=J
25
26
27
28
03
5
"
...
JO
f------'
Jl
f--~
"J--
-
32
JJ
J4
J5
36
04
6
...
~
....
:N
16
17
18
02
5=t1
J7
J8
J9
....
;=J
15
A4
~
--.c'J--
...
.It
40
;=J
41
42
4J
44
45
14
A5
13
A6
12
A7
11
CH:
46
05
7
...
47
.
~
"J--
...
~
48
b-J
49
"
06
8
..
51
52
53
54
55
....
....
c'J--
.>
"
~t>1
51
58
59
60
61
62
63
07
9
.
11:
012 J
4567
891011
12131415
16171119
20212223
24252&21
28293031
....
....
Notes
Octal Comparator
PAL16C1
Octal Comparator.
PAL16C1
COMP8
OCTAL COMPARATOR
MMI SUNNYVALE ,CALIFORNIA
AD A1 A2 A3 A4 AS A6 A7 BO GND
B1 B2 B3 B4 EQ NE Bs B6 B7 vec
NE = AO*/BO
+ A1*/B1
+
A2~/B2
+ A3*/B3
+ A4*/B4
+ As*/Bs
+ A6*/B6
+ A7*/B7
FUNCTION
+ /AO* BO
+ /A1* B1
+ /A2* B2
+ /A3* B3
+ /A4* B4
+ /As* Bs
+ /A6* B6
+ /A7* B7
; COMPARE
; COMPARE
;COMPARE
; COMPARE
; COMPARE
;COMPARE
; COMPARE
;COMPARE
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/21/81
AD NE
A~ NE
A2 NE
A3 NE
A4 NE
AS NE
A6 NE
A7 NE
BO
B1
B2
B3
B4
Bs
B6
B7
T~LE
A7 A6 AS A4 A3 A2 A1 AD B7 B6 Bs B4 B3 B2B1 BO NE EO
;INPUT A INPUT B OUTPuTs
;76543210 76543210
NE EQ
COMMENTS
---------------~-----------------~~-------~-----,:,------------~BLLLLLLL LLLLLLLL
H L
A7-Jl, B7-L
LHLLLLLL LLLLLLLL
A6.H, B6-Ii
H L
LLHLLLLL LLLLLLLL
H L
As-H, Bs""L
LLLHLLLL LLLLLLLL
H L
A4-H, As-t
LLLLHLLL LLLLLLLL
H L
A3=H, B3=--L
LLLLLHLL LLLLLLLL
H L
A2=H, B2=L
LLLLLLHL LLLLLLLL
H L
A1-H, B1-L
LLLLLLLH LLLLLLLL
H L
AO-H, BO-L
LLLLLLLL HLLLLLLL
H L
A7=L, B7-H
LLLLLLLL LHLLLLLL
H L
A6=L, B6=H
LLLLLLLL LLHLLLLL
H L
As=L, Bs=H
LLLLLLLL LLLHLLLL
H L
A4=L, B4=H
LLLLLLLL LLLLHLLL
H L
A3"'L, B3=H
LLLLLLLL LLLLLHLL
H L
A2=L, B2=H
LLLLLLLL LLLLLLHL
H L
A1=L, B1=H
LLLLLLLL LLLLLLLH
H L
AO=L, BO=H
LLLLLLLL LLLLLLLL
L H
TEST ALL L'S
HHHHHHHH HHHHHHHH
L H
TEST ALL H'S
HLHLHLHL HLHLHLHL
L H
TEST EVEN CHECRERBOARD
LHLHLHLH LHLHLHLH
TEST ODD CHECRERBOARD
L H
HHLLHHLL HHLLHHLL
L H
TEST EVEN DOUBLE CHECRERBOARD
LLHHLLHH LLHHLLHH
L H
TEST ODD DOUBLE CHECRERBOARD
-------------------------------------------------------------
DESCRIPTION
THE OCTAL COMPARATOR ESTABLISHES WHEN TWO 8-BIT DATA STRINGS
(A7-AO AND B7-BO) ARE EQUIVALENT (EO"'H) OR !l>T EQUIVALENT (NE=H).
4-234
Octal Comparator
OCTAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
COMPARATOR
000000010XOOOOLH0001
000000100XOOOOLH0001
000001000XOOOOLH0001
000010000XOOOOLH0001
000100000XOOOOLH0001
001000000XOOOOLHOOOI
010000000XOOOOLH0001
100000000XOOOOLHOOOI
OOOOOOOOOXOOOOLH0011
000000000XOOOOLHOI01
000000000XOOOOLH1001
OOOOOOOOOX0001LH0001
OOOOOOOOOXOOIOLH0001
OOOOOOOOOX01DOLHOOOI
OOOOOOOOOXIOOOLH0001
OOOOOOOOlXOOOOLH0001
O()OOOOOOOXOOOOHLOOOI
111111111X1111HLll11
Ol0101010X1010HL1011
10101010lXOI01BL0101
001100110X0110HL0111
110011001X1001BLI001
PASS SIMULATION
Octal, Comparator
OCTAL COMPARATOR
11 11.11 1111 2222 2222 2233
0123 45678901 2.345 6789 0123 4567 8901
24 -x25 ---x
26 x-27 -X28
29 -~30
31
32
33
34
35
36
37
38
39
--- -...--- ,---
----" -X--AO*/BO
..._--
-.,--
~--- -'-.-
-"!"'-- X:,,:,-- /AO*SO
~-.:..
X~-
-x-
------x
-..:x--x--... ---- <---- ---x
..:x--
--x-
x-- ---x
--x· x----X- -x-
---XA1*/B1
--X- /A1-*B1
A2*/B2
/A2*B2
A3*/B3
/A3*B3
A4*/B4
/A4*B4
A5*/B5
/A5*B5
A6*/B6
/A6*B6
A7*/B7
/A7*B7
-X- --X-
--x
-x-
LEGEND:
NUMBER OF
x:
---x
--x-
FUSE
FUSES
x--x---- x---- -x-
NOT BLOWN (L,N,O)
BLOWN =
480
-
: FUSE
BLOWN
(H,P,l)
Octal Comparator
Octal Comparator
AO
1
A1
2
A2
3
A3
4
.
Logic Diagram PAL16C1
012 J
.
4!i 67
891011
12131415
16111819
20212223
24252627
28293031
~
.
..
19
87
...
18
86
....
17
85
~
~
......
h
~
....
......
Z
14
25
26
27
28
29
30
A4
5
...
"
16
1
~
15
NE
EQ
"
84
32
J3
34
35
36
31
"
39
AS
6
7
A7
8
80
9
...
~
...
....
...
~
...
..
~
h
....
..
~
o1
2 3
4
~
a
7
Bill 0 11
12 13 14 15
161118 1
e
....
2021 2223
24252627
13
12
11
82
81
28291031
4-237
B
Notes
Between Limits Comparator
PAL16X4
vee
Gi'
IT
AD
A2
A3
EO
NE
PAL16C1
rnro
1
LTlL
2
GTlU
EQ1L
3
LTDL
(ffiU 4
vee
GTDU
EQ2u 5
BTWL
Ecill
7
GT3U
8
EQ3ij 9
Ne
EQ3L
GND
4-239
D
aetween Limits Comparator
Between Limits Comparator
Logic Schematic
~a:a:$
g~~iil
--
c:l~9c:l
UPPER LIMIT
CI CI
PAL16X4
CR·OU
cc
99
\
~GTOU
:; =::;-]
~~~~,~
~~~~~--------------------------~--------.
f--g:
I,,-!B=:O~+-t_+_t_il~.~ AND
I,,-!B=,:1--+-t_+_t_il
"'~ D.
I,-=B:.=2--+-t_+_t_il
::::.~ :.,,:,
B3
:::: ARRAY
~~+-I-+-t--[~:[H"
~
~l!l
~ 3iI
~~
~ Ii;!
~~
~r- ~
g'-~~~
LO~IT
PAL16X4
.--__.m:~;;;;C~R':{~-L
1m
~
I rrNjci
~>-+-rHHHR=_=_=-;;::=c=,=,....=_~_:!J
__
~
~
\
\
~
r-
f--g:
~B4!...-+-I-+-t-~;'[H AND
, 1,-!B5=--++-H--{J::;'!J-l ::.
B8
"i SATE
\
B7
::;
[l
[!
[!
li'-1TiJ
Ii'-~
~r-~
~r- ~
III '--, I=-J l.:J, 1m
fi>oL-lTiJ
~~
ARRAY
~~
tti~
...~~~!t-LT_OL____________________.......,
:.r:. . Ii'- ~
F.il ~GT1U
~1TiJ-
\
AND
[! xu:.
[!
~.!.!!-
..!.
r-
Ii'~- 1;;1~
I--~......,...----
~~
.---_ _ _ _--:---::_ _ _ _ _ _ _ _ _ _,..,.,..,_ _- - ,
__________.,--__-,-, ________'--,
!;: I , C R · 1 L
;;
cr
~r-~
m'- l.:J,1m
,'"
'~rm',
" ~~'
F.iJ ~LT1L
,
fttIo'---IlillF=--------,~ PAL,18C1
~
jl:![!:.AND .~~
L.[lt--l,
ITo!
I~
li'-1TiJ
,Ip
I;
~ >-+-t-++----=CR""'.2""U:--'-"~- 't:! ~~ li'-1TiJ
r;'
I;
f'-.!!
r;
li'-Im
..' a. t"'~
;::
til 1;;1
~GT2U
,""
t= J
1\
1
B
U
S
~,
_~',', : : ;
r;
H-ral--{_',!J-l
B6
B9
::F
E01U
",I.!
m'--,
t""~
AND
::.
I""B.::10~+-I-:-+-+-il
r:,~ .ATE
'1,-=B.:..:11~+-I*-+--{~l[H"·AY
~~ .-----------------......1
Ii
Q ~
1;;0
Ii"'
~ 1m
E02U
~
~Im
~ ITiJ
r.. "" '--____________----'
I '-!=--+-+-+-i--{J::;'[H
r;
.;::;
~ I;;L
F.;;E01L
1=-J1'""jl!a
~.2L
~~
'i
.--------{J;:;'!J-l
;:;
AND ~
1;;1
GATE~t:;;
ARRAYfl'
1::' --
r--tw
r--Iii:
~
r----il
rnl:~'-c: r-- ~
~
r--;=:g 1& ~L
'~l -+-hI-+-,----=::-=:-:-------1
I [!:..:. ~~
I'-.!!
~ 1;;1
r;
r.. Iii:
II'
L-F-
T2L
m
AND
I'..B10
~
CR-3U
~ ,..-- Sl
'---'-~""'I:!..r;,;u
j:;,
H
B12
1'-==--+--+-i-··...,r:·!.H AND
I""B1:.::3__+--+--t-~'l!'cH :"
I--.::;B1.:.;4__+__+_t_il
I'-!::B1~5__+__+_t_i!li
;:;".AY
J ..l.'
"":Jis::e
II
II
Ii!
I!!! GT3U
~
j-I>-'-~
~
'
~~
GATE
~
E02L
~
~t- ~
[!
m'- >- ~ 1m
If-~
il-l!l
il- ~
ji'I ' - - , - - - - - - - - - - - - - - - - - - - '
. - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____'
.,
1>0";;
l!o
~"!!:-
E03U
~~ ill ':':':::'::'-{~:rJ:;1;:::£=h:~=--tiJ~
-->--',.,. J!]
@
~ LT3L
Ir-:=;,
~
j
~l L...-.tl=tl====~::!JII . I:!11
~
~~~~~~-----------------------'
AND
::.
~ ,-----------,...-------{ [! :.~~
~
~~
".AY
[l
~
•
~~1TiJ~,"
~~
.".~EQ3L
~~~~~----------------------'
g"--~~~
4.240
,,
" ,",
OUTL
"
,B'TWL
.
Between Limits Comparator
PAL16X4
BLR
BETWEEN LIMITS COMPARATOR/REGISTER
MMI SUNNYVALE, CALIFORNIA
CLK LOAD CLEAR BO Bl B2 B3 NC /OC2 GND
/OCl /NE
/EQ A3 A2 Al AO /LT /GT VCC
IF (OC2)
IF (OC2)
LT
GT
(A3"'/B3)
+ (A3:"':B3)
+ (A3:"':B3)
+ (A3: '" :B3)
(/A3"'B3)
+ (A3:"':B3)
+ (A3:"':B3)
+ (A3:"':B3)
'"
'"
'"
(A2"'/B2)
(A2: '" :B2)
(A2:"':B2)
'"
'"
'"
(/A2"'B2)
(A2: '" :B2)
(A2:"':B2)
'"
(A2:"':B2)
'"
'"
'"
'"
'"
PAL DESIGN SPECIFICATION
BIRKNER/COLI 07/12/81
(Al"'/Bl)
(Al:"':Bl)
(/Al"'Bl)
(Al:"':Bl)
(AO"'/BO)
;B3=L,
;B2=L,
;Bl=L,
;BO=L,
A3=H
A2=H
Al=H
AO=H
'"
(/AO"'BO)
;B3=H,
;B2=H,
;Bl=H,
;BO=H,
A3=L
A2=L
Al=L
AO=L
'"
(AO: '" :BO) ;COMPARE EQUAL
'"
IF (OC2)
EQ
(A3:"':B3)
IF (OC2)
NE
(A3:+:B3) + (A2: +:B2) + (Al:+:Bl) + (AO:+:BO) ;COMPARE NOT EQUAL
(Al:"':Bl)
/A3 := (/A3) "'/LOAD
+ (/B3) '" LOAD.
+ CLEAR
; HOLD REG A3
; LOAD REG A3
;CLEAR REG A3
/A2 := (/A2) "'/LOAD
+ (/B2) '" LOAD
+ CLEAR
; HOLD REG A2
; LOAD REG A2
,CLEAR REG A2
/Al := (/Al) "'/LOAD
+ (/Bl) '" LOAD
+ CLEAR
; HOLD REG Al
; LOAD REG Al
;CLEAR REG Al
/AO := (/AO) "'/LOAD
+ (/BO) '" LOAD
+ CLEAR
,HOLD REG AO
; LOAD REG AO
; CLEAR REG AO
DATA 16
BUS -r----1r----i
16-BIT
(UPPER
liMIT)
7
oun
COMPARE
lOGIC
2
CLEAR
lOAD
BTWl
ClK
4·241
Between Limits. Comparator
FUNCTION TABLE
CLK lOCI IOC2 LOAD CLEAR B3 B2 B1 BO A3 A2 Al AO LT EQ NEGT .
1CONTROL
loc
OPERATIONS
LOAD CLEAR
lCLK 1 2
C
C
X
X
X
C
L
L
L
L
L
L
X
X
L
L
X
X
C
L X
X
L L
X
L X
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X H X
X
X
X
X
X
X L L
X
L L
X L X
C L X
C
L X
X
X
X
X
L
L
L
L
L
L
L
X
H
L
L
L
X
H
L
L
L
L
X
H
L
L
L
L
C
L X
X
C
X
X
X
L
L
L
L
H
L
C
X
L
L
X
X H
L
BUS
BBBB
3210
AAAA
REG
XXX X
LLLL
LLLL
LLLH
XXXX
XXXX
LHLH
LLLL
LHLH
HHHH
XXXX
XXXX
HLHL
LHLL
HLHL
HLHH
XXXX
XXXX
HHHH
HHHL
HHHH
XXXX
XXXX
XXXX
XXXX
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LHLH
LHLH
LHLH
LHLH
LHLH
LLLL
HLHL
HLHL
HLHL
HLHL
HLHI,
LLLL
HHHH
HHHH
HHHH
HHHH
HHHH
ZZZZ
XXXX
3210
--STATUS--LT EQ NE GT
COMMENTS
(HEX VALUES)
X
X
L
L
X
X
X
H
L
L
X
X
X
H
L
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
L
H
L
X
X
X
L
H
L
X
X
X
L
H
X
X
X
X
L
H
X
X
X
H
L
H
X
X
X
H
L
H
X
X
X
H
I,
X
X
X
X
L
H
X
X
X
L
L
H
X
X
X
L
L
H
X
X
X
L
L
X
X
Z
Z
Z
Z
CLEAR REG
LOAD REG (0)
COMPARE (0 EQ 0)
COMPARE (1 GT 0)
READ REG (0)
CLEAR REG
LOAD REG (5)
.COMPARE (0 LT 5)
COMPARE (5 EQ.5)
COMPARE (F GT 5)
READ REG (5)
CLEAR REG
LOAD REG (A)
COMPARE (4 LT A)
COMPARE (A EQ A)
COMPARE (B GTA)
READ REG (A)
CLEAR REG
LOAD REG (F)
COMPARE (E LT F)
COMPARE (F EO F)
READ REG (F)
HOLD (F)
TEST HI-Z (/OC1=H)
TEST HI-Z (/OC2=H)
x x x x
DESCRIPTION
THE DEVICE CONTINUOUSLY COMPARES THE VALUE OF BUS (B3-8O) WITH THE VALUE OF
THE REGISTER (A3-AO) AND REPORTS THE STATUS ON OUTPUTS LT, EQ, NE, AND GT:
*
*
*
*
lOCI
LT
EQ
NE
GT
IOC2
H
X
L
X
X
X
X
4·242
INDICATES
INDICATES
INDICATES
INDICATES
.CLK
LOAD
THAT
THAT
THAT
THAT
B
B
B
B
IS LESS
THAN A
IS
EQUAL
TO A
IS NOT EQUAL TOA
IS GREATER THAN A
CLEAR
STATUS
LT EQ NE GT
X
H
x
X
x
x x x x
X
X
Z
X
X
X
C
C
X
L
H
L
X
C
X
L
x
L
X
L
L
L
H
L
Z
Z
Z
BUS
B3-BO
REG
A3-AO
x
Z
X
A
B
A
L
A
x
x X x X
x x x x
x x x x
x x x X
X
B
X
STATUS
B
X
OPERATION
REG HI-Z
STATUS HI-Z
READ REG
LOAD REG
HOLD
CLEAR REG
COMPARE
Between·. Llmits;Comparator
BETWEEN LIMITS COMPARATOR/REGISTER
1 CXIXXXXXXXOXXLLLLXXI
2 CI00000XXXOXXLLLLXXI
3 XOOOOOOXOXOHLLLLLBHl
4 XOOI000XOXOLBLLLLHLI
5 xOOxXXXXXXOXXLLLLXXl
6 CXIXXXXXXXOXXLLLLXXI
7 CI0I0I0XXXOXXLHLHXXI
8 XOOOOOOXOXOLHLHLHLHI
9 XOOI0I0XOXOHLLHLHHHI
10 XOOIIIIXOXOLHLBLHHLI
11 XOOXXXXXXXOXXLHLHXXI
12 CXIXXXXXXXOXXLLLLXXI
13 CI00I0IXXXOXXHLBLXXI
14 XOOOOI0XOXOLBHLHLLHI
15 XOOOI0IxOXOHLHLHLBHl
16 XOOllOIXOXOLBHLHLHLl
17 XOOXXXXXXXOXXHLHLXXI
18 CXIXXXXXXXOXXLLLLXXI
19 CI01111XXXOXXHBHHXXI
20 XOOOlllXOXOLHHHHHLHl
21XOOlll1XOXOHLBHHHHHl
22 XOOXXXXXXXOXXHBHHXXI
23 COOXXXXXXXOXXHBHHXXI
24 XXXXXXXXXXIXXZZZZXXI
25 XXXXXXXXIXXZZXXXXZZI
PASS SIMULATION
Between Limits Comparator
BE'l'WEEN LIMITS COMPARATOR/REGISTER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o
----------------
------------xxx-
---------xxxx--x
----------------
-x--------------
OC2
/A3*B3
A3:*:B3*/A2*B2
A3:*:B3*A2:*:B2*/A1*B1
A3:*:B3*A2:*:B2*A1:*:B1*/AO*BO
10
11
12
----------------
-------------xxx
------- -------xxx ------- -xxx x--x ----xxx x--x x--x ---x--x X--X x--x ----
-x--------------
OC2
A3*/B3
A3:*:B3*A2*/B2
A3:*:B3*A2:*:B2*A1*/B1
A3:*:B3*A2:*:B2*A1:*:B1*AO*/BO
16 -x-17 x--18 ----
---- xx-- ----x-x ---x--- ---- ----
---- /AO*/LOAD
---- /BO*LOAD
---- CLEAR
1 ----
2 ---3
4
8
9
------xxxx--x
x--x
---xxxx--x
x--x
x--x
24
25
26
-x-x---
---- xx----- -x-x ---x--- ---- ---- ----
---- /A1 */LOAD
---- /B1 *LOAD
---- CLEAR
32
-x-x---
---- ---- XX----- ---- ---- -X-X ----
---- /A2*/LOAD
---- /B2*LOAD
CLEAR
33
34
40
41
42
-x-x---
48
49
56
57
58
59
60
LEGEND:
x---
x---
---- xx-- ------- ---- -x-x ----
/A3*/LOAD
/B3*LOAD
---- ---- ---- ---- ---- CLEAR
---- ---- ---- ---- ---- ---- -x-- OC2
---- x--x x--x x--x X--X ---- ---- A3:*:B3*A2:*:B2*A1:*:B1*AO:*:BO
---- ------- ------- -------
x:
-xx-
-x--------
-xx-xx---- -~--xx- ---- ---- ---- ---- ----
FUSE NOT BLOWN (L, N, 0)
NUMBER OF FUSES BLOWN =
832
OC2
A3:+:B3
A2:+:B2
A1:+:B1
AO:+:BO
- : FUSE BLOWN
(H,P;l)
Between Limits Comparator
Logic Diagram PAL16X4
Between Limits ComparatorIRegister
ClK
I
o
lOAD
2
...
1 2 3
4 5 6 7
8 9 1011
12131415
16171819
20212223
24252627
28293031
....
8
9
10
11
"
13
14
15
CLEAR
3
...
....
16
17
18
"
;;;:;
2Om~§3fi§EimEmEm3~
11
21
23
BO~
t!go"
B3
7
50
51
52
53
54
NCB
..
55
56
57
58
59
"
OC2
9
.
61
51
6l
...
0123
"561
B 91011
12131415
16171819
20212223
24252621
2829JD31
4·245
Between Limits Comparator
PAL16C1
PAL DESIGN SPECIFlCA'l'ION
BLL
BIRKNER/COLI 07/12/81
BETWEEN LIMI'l'S COMPARATOR/LOGIC
MMI SUNNYVALE, CALIFORNIA
/EQ1U /L'l'lL /EQ1L /G'l'2U /EQ2U /L'l'2L /EQ2L /G'l'3U /EQ3U GND
/L'l'3L /EQ3L
NC
NC
BTWL 0U'l'L /G'l'OU /LTOL /GT1UVCC
OU'l'L .. G'l'3U
+ EQ3U
+ EQ3U
+ EQ3U
+ LT3L
+ EQ3L
+ EQ3L
+ EQ3L
7GT CR-3U
* GT2U
,EQ CR-3U, GT CR-2U
* EQ2U * GT1U
7EQ CR-3U, EQ CR-2U, GT CR-1U
* EQ2U * EQ1U * GTOU 7EQ CR-3U, EQ CR-2U, EQ CR-1U, GT CR-OU
7LT CR-3L
* LT2L
7EQ CR-3L, LT CR-2L
* EQ2L * LT1L
7EQ CR-3L, EQ CR-2L, LT CR-1L
* EQ2L * EQ1L * LTOL 7EQ CR-3L, EQ CR-2L, EQ CR-1L, LT CR-OL
FUNCTION TABLE
G'l'3U EQ3U EQ3L LT3L GT2U EQ2U EQ2L L'l'2L GT1U EQ1U EQ1L LT1L G'l'OU LTOL 0U'l'L BTWL
, COMPARATOR REGISTERS
7CR-3
7GEEL
,TQQT
7UULL
CR-2
GEEL
CR-1 CR-O
GEEL G L
TQQT TQQT T T
UULL UULL U L
0U'1'PU'l'S
0U'l'L BTWL
COMMENTS
----------------------------------------------------------------HLLL
LHLL
LHLL
LHLL
LHLL
LHLL
LHLL
LHLL
LHLL
LLBt
LLHL
LLHL
LLHL
LLHL
LLHL
LLHL
LLHL
LLLH
XXXX
HLLL
LHLL
LHLL
LHLL
LHLL
LHLL
LLHL
LLLH
HLLL
LHLL
LLHL
LLHL
LIm.
LLHL
LLHL
LLLH
xxxx
XXXX
XXXX
HLLL
LHLL
LHLL
LLHL
LLLH
XXXX
XXXX
XXXX
XXXX
BtLL
LHLL
LLHL
LLHL
LLLH
XXXX
XXXX
x
X
X X
X .X
X
X
X
X
X
X
H
H
H
L
L
L
L
L
L
L
X
L
X
I!
H L
L H
X
X
X
X
X
X
X
X
H L
L H
X
X
x
H
X
X
X
L
H
H
H
H
L
L
L
L
II
H
H
H
H
H
H
H
H
H
L
L
L
L
OUT OF LIMITS (GT3U=H)
OUT OF L~TS (G'l'2U=H)
OUT .OF LIMITS (GT1U=H)
OUT OF LIMITS (GTOU=H)
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN LIMITS
BETWEEN
LIMITS
.
.
BETWEEN LIMITS
BETWEEN LIMITS
OUT OF LIMITS (LTOL-H)
OUT OF LIMITS (LT1L=H)
OUT OF LIMITS (LT2L-H)
OU'!' OF LIMITS (LT3L=H)
----------------------------------------------------------------DESCRIPTION
THE BETWEEN LIMITS LOGIC CHECKS THE LT, EQ, AND GT STATUS PROM THE
COMPARATOR REGISTERS TO DETERMINE IF THE DATA IS BETWEEN THE t]PP]i:R,
AND LOWER LIMITS LOADED IN THE COMPARA'I'pR REGIS~. BOTH BETWEEN
LIMITS (BTWL) AND OUT OF LIMITS (OU'l'L) OUTPUTS ARE PROVIDED.
4·246
Between Limits Comparator
BETWEEN LIMITS COMPARATOR/LOGIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
XXXXXXX01XllXXLBXXX1
XXX011110X11XXLRXXX1
111101110X11XXLHXX01
011101110X11XXLH0111
011101110X11XXBL1011
110101110X11XXBLXX11
101101110X11XXBLXX11
XXX111010X11XXBLXXX1
XXXllOllOXllXXBLXXX1
XXX011111X10XXHLXXXl
XXX10111lX10XXBLXXX1
11111101lXIOXXBLXX01
011111011X10XXHLXX11
110111011X10XXBL0111
110111011X10XXLH1011
101111011X10xxLBXX11
XXXll0111X10XXLBXXX1
XXXXXXX11X01XXLBXXX1
PASS SIMULATION
4-247
Between Limits. Comparator
BETWEEN LIMITS COMPARA'l'OR/LOGIC
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
24
25
26
27
28
29
30
31
-x----------x ---- ---- -x-x ---- ---- ----
----x--x--x----- ---- ---- ---- ---- ---- ---- ---x
---- ---- ---- ---- -x-- ---- ---x ----x-- ---- ---- ---- ---- -x-- ---x ------- -x-- ---x ---- ---- -x-- ---x ------- ---- ---- ---- ---- ------- ---- -x-- ---- ---- ------- ---x ---- -x-- ---- ----
LEGEND:
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
4-248
236
GT30
EQ30*GT20
EQ30*EQ20*GT10
EQ30*EQ20*EQ10*GTOO
LT3L
EQ3L*LT2L
EQ3L*EQ2L*LT1L
EQ3L*EQ2L*EQ1L*LTOL
- : FUSE BLOWN
(B,P,l)
Between Limits Comparator
Between Limits Comparator/Logic
0123
1
2
EQ1L
GT2U
3
4
4567
891011
12131415
Logic Diagram PAL16C1
16111819
20212223
24252621
28293031
...
~
.....
19
Jt:
""
...
...
.....
.....
.....
GT1U
18
17
GTOU
Z4
15
""
"'"
5
...
3D
J1
16
.I
~
15
OUTLD
BTWL
J2
3J
34
l5
J6
37
3B
"
LT2L
EQ2L
6
7
...
...
A
--N
...
.
8
...
9
.
A
14
13
NC
NC
~
A
...
....
12
11
o
I 2 J
4 fI 8- 7
191011
U 1314 15
16171819
20212ZZJ
24252627
. LT3l
28293031
4-249
.
Notes
4-250
Memory Mapped Printer
PAL16H2
vee
Viii
RO
WRITE
A2
AS
PAL20X8
vee
07
P07
PD8
...............ro....J....
P05
P03
P02
19
Memory Mapped Printer
r----=
• t
TRS-80 EXPANSION CONN.
SYSTEM DATA BUS
AD
A15
Al4
TRS·80 EXPANSION CONN.
SYSTEM BUS
~AD
20 24 28 18
07 06 05 04
26 322230
030201 DO
~
10""
Al3
A12
A11
......
.......
A10
A9
A8
30
745387
)0-
Z.n
.
~
A7
I
I
74LS175
CKe
I.
74LS175
-r-
CK
I
+5
(
A6
20K
A5
A3
~
30
~
AAS
A2
v~
74LS123
'~
~
.,
,
Q
R = 20K
~C,=300Pf
.2:
\"),
+
P 'S
'R T
I R
N 0
T B
E
WRiTE", ,
P
A
P
E
R
B
U
S
Y
070605,04
03,0201 DO
PRINTER (37E8 HEX)
"
°TRS-80 IS A TRADEMARK OF TANDY RADIO SHACK
+5
+r-
TRS-80 EXPANSION CONN.
SYSTEM DATA BUS
Y
15
Rp
7
10
A15
A14
6
A13
3
5
9
A12
A11
4
4
A10
6
17
11
A9
7
AS
8
36
36
A7
2
;
9
11
35
AS
12
34
40
A3
,A2
13
14
RAS
17
19
WR
f
16 READ
I
24
8
1
15 WRITE
+5
5 6
7
I
9 12 13 10 11 22 21 20 19 18 17 16 15
lLf
R
>--
R
C
74LS123
+
= 20K
= 200pf
S
T
R
0
"TRS-80 IS A TRADEMARK OF TANDY RADIO SHACK
3 4
PAL20X8
~ L
f"v
23 14 2
PAL
16H2
10
,
20 24 28 18 28 32 22 30
07 D6 05 04 03 02 01 DO
1
5
AS
13
20
18.
1
TRS·80 EXPANSION CONN.
SYSTEM DATA BUS '
,
B
E
B
U
S
Y
P 07060504030201 DO
A
P
PRINTER
E
(37E8 HEX)
R
Memory Mapped Printer
PAL16H2
PAL DESIGN SPECIFICATION
MMPD
DICK JONES
07/07 /Sl
MEMORY MAPPED PRINTER DECODER
MMI FIELD APPLICATIONS ENGINEER LOMBARD, ILLINOIS
A15 A14 A13 A12 All A10 A9 AS A7 GND
A6 AS A3 A2 WRITE READ /RAS /RD /WR vec
WRITE = /A15*/A14*A13*A12*/All*A10*A9*AS*A7*A6*A5*A3*/A2*RAS*WR
READ
= /A15*/A14*A13*A12*/All*A10*A9*AS*A7*A6*A5*A3*/A2*RAS*RD
FUNCTION TABLE
A15 A14 A13 A12 All A10 A9 AS A7 A6 AS A3 A2 RAS RD WR WRITE READ
1AAAA AAAA AAA AA RRW
WR
11111 1198 765 32 ADR
15432 10
S
RE
LLBB LBBB HBB BL
LLBB LHBB HBB BL
XXXX XXXX xxx XX
XXXX XXXX XXX XX
IA
TO
E
BLH
BL
BBL
LB
LXX
LL
LL
BLL
COMMENTS
WRITE WHEN 37E8 HEX
READ WHEN 37ES HEX
RAS NOT PRESENT
NOT READ OR WRITE
DESCRIPTION
THIS IS A MEMORY DECODER FOR A PRINTER. THE PRINTER
IS MAPPED TO HEX ADDRESS 37E8. THE WRITE OR READ LINES
GO HIGH WHEN ADDRESS LINES ARE CORRECT AND A WRITE OR
READ STROBE RESPECTIVELY IS PRESENT.
THIS IS THE FIRST IC OF A 2-PAL PRINTER INTERFACE FOR
THE STANDARD CENTRONICS-TYPE PRINTER.
MEMORY MAPPED PRINTER DECODER
1
2
3
4
001101111X1110BL0101
001101111X1110LH0011
XXXXXXXXXXXXXXLL1XX1
XXXXXXXXXXXXXXLL0111
PASS SIMULATION
4 .. 253
Memory Mapped Printer
MEMORY MAPPED PRINTER DECODER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
24
-x-x x--- x--x -x-x x--x x-x- x-x- .x-x-
/A15*/Al4*Al3*Al2*/Al1*AlO*A9*-
32
-x-x x--x x--- -x-x x--x x-x- x-x- x-x-
/Al5*/Al4*Al3*Al2*/Al1*AlO*A9*-
LEGEND:
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN·
34
- : FUSE BLOWN
(H,P,l)
Memory Mapped Printer
Memory Mapped Printer Decoder
A15
A14
1
2
... :lit
...
0123
4 J 51
II 91011
12131415
Logic Diagram PAL16H2
16171819
20212223
24252627
28293031
I
...
... >.
111::
....
19
,
,
A13
A12
J
,
... :lit
...
....
...
... :lit
111::
....
18
17
14
25
26
27
28
29
"""
1.
"""
15
READ
30
A11
5
...
... :lit
J1
32
33
J4
35
36
J7
38
WRITE
3'
A10
6
A9
7
AS e
A7
9
...
...
... :lit
I.
....
...
... :lit
"
...
...
... :lit
...
....'
....
4 5 6 1
a9
1011
121314 15
161118 19
2021 22 2~
24252621
A3
....
....
" A5
....
....
11
111::
0, 1 2 3
13
A2
A6
2B 29 30 31
4·255
Memory'Mapped Printer
PAL20X8
PAL DESIGN SPECIFICATION
PDRM
DICK JONES
07/07/81
PRINTER DATA REGISTER/MUX
MMI FIELD APPLICATIONS ENGINEER LOMBAlID, ILLINOIS
WRITE D5 D4 D3 D2 D1 DO READ NC BUSY PAPER GND
/EN D6 PDO PD1 PD2 PD3 PD4 PD5 PD6 PD7 D7 vec
IF (READ) /07
- /BUSY
/PD7 := /07
/PD6
:=
:READ PRINTER STATUS -BUSY
: LOAD MSBTO PRINTER
/D6
: LOAD PRINTER
/PD5 :- /05
: LOAD PRINTER
/PD4 :- /04
: LOAD PRINTER
/PD3 := /D3
: LOAD PRINTER
/PD2 := /02
: LOAD PRINTER
/PD1
:=
/D1
/PDO :- /DO
IF (READ) /06
• /PAPER
: LOAD PRINTER
: LOAD LSB TO PRINTER
: READ PRINTER STATUS - PAPER OUT
FUNCTION TABLE
WRITE BUSY PAPER READ D7 D6 D5 D4 D3 D2 D1 DO PD7 PD6 PD5 PD4 PD3PD2 PD1 PDO
:WSPR DDDDDDDD PPPPPPPP
:RUAE 76543210 DDDDDDDD
: ISPA
76543210
:TYED
:E R
LHLH
LLHH
CXXL
CXXL
CXXL
CXXL
COMMENTS
HLXXXXXX
LHXXXXXX
ZZXXXXXX
LLLLLLLL
HLHLHLHL
HHBHHBHH
XXXXXXXX
XXXXXXXX
XXXXXXXX
LLLLLLLL
HLHLHLHL
HHH8BBHB
READ PRNTR STATUS
READ PRNTR STATUS
TEST HI-Z
LOAD DATA TO PRINTER
LOAD DATA TO PRINTER
LOAD DATA TO PRINTER
----------------------------------~-----------~--
4-256
Memory Mapped Printer
DESCRIPTION
REGISTERED DATA FRO,", THE SYSTEM BUSS IS PRESENTED TO THE PRINTER WHEN A WRITE
STROBE FROM THE DECODER IS PRESENT (DJPR1).
PRINTER STATUS DATA (P~INTER BUSY AND OUT OF PAPER) IS TRANSFERED
TO THE SYSTEM DATA BUSS WHEN A READ STROBE FROM THE DECODER IS PRESENT.
THIS IS THE SECOND IC OF THE 2-PAL PRINTER INTERFACE FOR THE
STANDARD CENTRONICS-TYPE PRINTER.
PRINTER DATA REGISTER/MUX
1
2
3
4
5
6
OXXXXXX1X10XXLXXXXXXXXHl
OXXXXXX1X01XXHXXXXXXXXLl
CXXXXXXOXXXXXZXXXXXXXXZl
COOOOOOOXXXXXOLLLLLLLLOl
C1010100XXXXXOLHLHLHLHll
CllllllOXXXXX1HHHHHBBHll
PASS SIMULATION
4 .. 257
Memory Mapped Printer
PRINTER DATA REGISTER/MUX
11 llll llll 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
----
o
1
8
x--
--x ----
---~
/BUSY
"!--- /D7
---x
16
24
READ
-x--
-x--
32
/D5
-x--
/D4
-x--
40
/D3
-x-
48
/D2
-x--
56
/Dl
-x--
64
/DO
x--
72
73
LEGEND:
/D6
x:
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW =
468
READ
-x-- /PAPER
- : FUSE BLOWN
(H,P,l)
Memory Mapped Printer
Printer Data Register/Mux
WRITE
Logic Diagram PAL20X8
1
0111
·
4
S
67
8
S lDll
1213141\
16111&19
20212223
24202621
28293031
l23Jl4H
163JlB]9
,
05
··
-Q-,9D~-
"
3
~-
:Q:r~D;;;;::.
-
-I\t',
"
03 ~
"
"
5
01 6 -
...
~D
-
"
"
.....
7
...
,.
,......
B
~
..
~D
-
"
~
"
"
~
9
..
8~
"
10
tLIl
....
20
P05
P03
~ PO
~
P01
tQJ~
POO
tl1l
....
~
,....,
"
"
"
"
11
tQ]
~
,....,.~D-
."
IAPER
~
~ P04B
..-
~~D
-
"
BUSY
~
I;J.
~D
-
"
NC
P07
~
...
.~
"
"
"
READ
~~
~2 P06
IDD--
"
"
DO
07
~
""
"
02
23
-
~
'"
D4
,....,.
~D--P I
,
,
~.~
>----t>
:J
">
o
1
2 3
4
5
6
7
' 9 ' 0 It
12 IJ 14 IS
16!1 1819
21121
n
2l
24252627
212930 JI
32 ll34
n
14
~
1& Jllll9
4·259
06
Notes
4-260
Craps Game
'r:
PAL16R4
WiN
LOsE
A
i
C
NC
NCA
NC
PAL16R6
PAL16R4
PAL16L8
vcc
vcc
is
2"
QO
46
"7
Q1
2i
NC
Q2
'is
NC
Q3
NC4S
PaS
P4s
P2S
NC
54
NC2i
P'iS
Nc1S
11
SWCiJ(
vcc
iiOIT
R
".
CK
OND
NC
Os
SWcK
NC
NC
OND
OND
Craps Game
A Game of Chance
This application note describes the use of PALs to simulate the
dice game "Craps". The design requirements were derived from
the basic rules of the game which are listed below.
1. The player throws two dice. The number will be between 2
and 12.
There are four PALs used in this design, which are:
ICI 8-State Machine and Win-Lose Decoder
IC2 36-State Machine
IC3 Dice Decoder
IC4 Store Point and 12, 17, and III Decode
2. He wins if the number is 7 or 11. He loses if the number is 2.
which is called "snake eyes".
3. Any number other than 2, 7, or 11 is the player's point.
4. Player continues to roll if a point is indicated on the first roll.
5. The player loses if he throws 7 or lIon a subsequent roll.
6. The player wins if he throws a point on a subsequent roll.
7. The player continues to roll until a win or a loss is indicated.
Not included in this application note are three more ICs. These
are a 74LS85 (Magnitude Comparitor), used to compare the
stored point to the roll of the dice on second and subsequent
rolls, and two Binary-to-Seven Segment Decoders, used to drive
the LED displays.
Craps Game
PAL16R4
ICI
8-STATE MACHINE AND WIN-LOSE DECODER
MMI FIELD APPLICATIONS ENGINEER DALLAS, TEXAS
CLK /ROLL /2 /7 /11 CP NC NC /T GND
/OC NC /NCA NC /C /B /A /LOSE /WIN VCC
PAL DESIGN SPECIFICATION
BRAD MITCHELL 04/07/81
IF (VCC) WIN
A* B*/C
;DECODE THE WIN STATE
IF (VCC) LOSE
A*/B* C
;DECODE THE LOSE STATE
A* B*/C*/ROLL
;STATE DECODES DERIVED
;FROM THE KARNAUGH MAP
;NCA IS ADDITIONAL DECODE FOR A
IF (VCC) NCA
+ A*/B* C*/ROLL
+ /A* B* C*/ROLL
A := /A* B*/C*/ROLL* 7
* T ;STATE DECODES DERIVED
+ /A* B*/C*/ROLL
* 11
* T ;FROM THE KARNAUGH MAP
+ /A* B*/C*/ROLL
* 2
* T
+ A*/B*/C*/ROLL*/7*/11
*/Cp* T
+ A*/B*/C*/ROLL* 7
* T
+ A*/B*/C*/ROLL
* 11
* T
+ A*/B*/C*/ROLL
* cp* T
+ NCA
*/ROLL
* T ;PICK ADDITIONAL DECODE LOGIC
;FROM NCA
B := /A*/B* C*/ROLL
*
+ /A* B*/C*/ROLL* 7
*
+ /A* B*/C*/ROLL
* 11
*
+ /A* B*/C
*/7*/11*/2
*
+ A*/B*/C* ROLL*/7*/11
*/CP*
+ A*/B*/C*/ROLL
* CP*
+ A* B
*/ROLL
*
+
B* C* ROLL
*
T ;STATE DECODES DERIVED
T ;FROM THE KARNAUGH MAP
T
T
T
T
T
T
C := /A* B*/C*/ROLL
* 2
+ /A* B*/C* ROLL*/7*/11*/2
+ A*/B*/C*/ROLL* 7
+ A*/B*/C*/ROLL
* 11
+ /A*/B
* ROLL
+ A
* C*/ROLL
+ /A* B* C* ROLL
T
T
T
T
T
T
T
*
*
*
*
*
*
*
4·263
Craps· Game
FUNCTION TABLE
CLK ROLL 7 11 2 CP NCA TAB C LOSE WIN
;-INPU'l'S1CR712CNT
1LO 1 PC
;XL
-OUTPOTSABC
L W
o
I
S N
E
A
1 L
COMMENTS
------------------------------------------------------------------------TEST· INITIATION AND GAME START
CBXXXXXL
CBXLXXLB
CBXXXXLB
CLXXXXLB
CLBLXXBB
CLXXXXHB
CBXXXXLH
CBXxxxLB
CLXXXXLB
CLXxBxHB
CLXXXXBB
CBXXXXLB
CBXXXXLB
CLXXXXLB
CLLL~LB
CHLLLXLB
CBXXXXLB
LLXXXXHB
CLXXXXLB
CLLLXHBB
CBXXXXLB
CHXXXXLB
CLXXXXLB
CHLLLXLB
LLXXXXHB
CLXXXXLH
CLHBXXBB
LLL
LLB
LLH
LBL
HBL
HHL
ttL
LLH
LBL
HLB
HLB
LLL
LLH
"LBL
LBL
LHB
LBB'; .
xxx
liLL
HHL
LLL
LLB
LliL
LHB
XXX
HLL
BLB
L L
L L
L L
L L
L H.
L B
L L
L L
L L
H L
H L
L L
L L
L L
L L
L L
L L
LL
L L
L B
L L
L L
L L
L L
L L
L L
B L
WIN BECAUSE A 7 WAS ROLLED
BOLD WIN WHEN NOT ROLLING
RESTART GAME
LOSE BECAUSE OF 2 ON FIRST ROLL
. BOLD LOSE WHEN NOT ROLLING
RESTART GAME
WIN BECAUSE POINT WAS MATCHED
RESTART GAME
LOSE BECAUSE 7 OR 11 WAS ROLLED ON SECOND ROLL
-------------------------------------------~----------------------------~-----DESCRIPTION
THIS PAL SERVES AS THE MAIN LOGIC UNIT. IT IS THE 8 STATE MACHINE WHICH
CO~LS WHERE WE ARE IN THE GAME.
IT ALSO DETECTS THE WIN AND LOSE STATES.
PIN IT IS USED TO INITIATE THE GAME TO STATE 000 FOR I.C. TEST EQUIPMENT.
Craps Game
8 STATE MACHINE & WIN-LOSE DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22·
23
24
25
26
27
COXXXXXX1XXXXXHHHHBI
COXXIXXXOXXXXBI.HHHHl
COXXXXXXOXXXXHLHHHHl
CIXXXXXXOXXXXBBLBBHl
CIXOIXXXOXXXXLBLLBLI
CIXXXXXXOXXXXLHLLBLI
COXXXXXXOXXXXBBHHHHl
COXXXXXXOXXXXHLBHHHl
CIXXXXXXOXXXX~HHHl
CI0XXXXXOXXXXLLHLLHl
CIXXXXXXOXXXXLLHLLHl
COXXXXXXOXXXXBBHBBHl
COXXXXXXOXXXXHLBBBHl
CIXXXXXXOXXXXBBLBBBl
CIIIIXXXOXXXXBBLHBBl
C0111XXXOXXXXHLLHBBl
COXXXXXXOXXXXHLLHBBl
01XXXXXXOXXXXLXXXBBl
CIXXXXXXOXXXXBBBLBHl
CIXl11XXOXXXXI.BLI.BLl
COXXXXXXOXXXXBBHHHHl
COXXXXXXOXXXXBI.HHBBl
CIXXXXXXOXXXXBBLBBBl
COIIIXXXOXXXXHLLHBBl
01XXXXXXOXXXXLXXXHHl
CIXXXXXXOXXXXBBBLBHl
CIXOOXXXOXXXXLLBLLBI
PASS SIMULATION
Craps Game
8-STATE MACHINE AND WIN-LOSE DECODER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
0
1
8
9
16
17
18
19
20
21
22
23
---x ---x --x-
---- A*B*/C
---x
-xxx--x----xx--- -x-- --xx--x
x--x---x-x
x-----x
x-----x
x---
--x- ---x
---x --x-x-x --x---x --xx-x- -xx--x- --x-xx- --x--x- x-x-
A*/B*C
x--x--x---
--x---x
-x-x
x--x
x-x--x---x
---x
24
25
26
27
28
29
30
31
--x-xx--xx--- x-xx--x
-x-x-----x
x-----x
-x--
-x--x--x--x--x--x--x----x -x--
/A*B*/C*/ROLL*7*T
/A*B*/C*/ROLL*ll*T
/A*B*/C*/ROLL*2*T
A*/B*/C*/ROLL*/7*/11*/CP*T
A*/B*/C*/ROLL*7*T
A*/B*/C*/ROLL*ll*T
A*/B*/C*/ROLL*CP*T
NCA*/ROLL*T
---x
-x--x--x--x--x--x--x--x--
/A*/B*C*/ROLL*T
/A*B*/C*/ROLL*7*T
/A*B*/C*/ROLL*ll*T
/A*B*/C*/7*/11*/2*T
A*/B*/C*ROLL*/7*/11*/CP*T
A*/B*/C*/ROLL*CP*T
A*B*/ROLL*T
B*C*ROLL*T
32
33
34
35
36
37
38
x--- -x-- --x- ---x --x-x-- x--- x-x- x--x --x-x-x --x- --xx--x-----x -xx- --x-x---x- --xx-----x
---x
-x---x- ---x ---x
-x--x--x--x--x--x--x--
/A*B*/C*/ROLL*2*T
/A*B*/C*ROLL*/7*/11*/2*T
A*/B*/C*/ROLL*7*T
A*/B*/C*/ROLL*l1*T
/A*/B*ROLL*T
A*C*/ROLL*T
/A*B*C*ROLL*T
48
49
50
51
x--x---
X---'
LEGEND:
---x
--x--x--x-xxx-x-
---x ---x --x---x --x- ---x
--x- ---x ---x
X : FUSE NOT BLOWN (L,N,Ol
NUMBER OF FUSES BLOWN
842
A*B*/C*/ROLL
A*/B*C*/ROLL
/A*B*C*/ROLL
FUSE BLOWN
(H,P,ll
Craps Game
Logic Diagram PAL16R4
a-State Machine and Win-Lose Decoder
ClK
1
0123
4561
891011
12131415
16171819
20212223
24252627
28293031
0
~
.
1
2
3
;
6
ROll 3
)
.
.A
~
~I----
".
,
8
~
10
11
12
13
""
3
~I----
~~
oi-'--
""
"
20
21
22
..
18
.A
"'"
16
17
18
4
19
D
~~
2J
~
c
~
~
""
r;;-;;I--
""
26
"
j
28
"
30
31
.•...
..
5
to.
~
iC.
""
I
32
33
34
l5
J6
"
./
"39
J8
CP
6
to.
~
...
'"
~
=Dl
40
41
"
""-
43
44
45
46
47
NC
7
to.
~
~
iC.
""
".
48
rJ
49
;0
"
52
53
54
NC
8
to.
"
T
.
~
~
13
NC
NCA
,,:t--....
~
~
"57
9
=Dl
~i
rJ
"
"""
"
6J
~
'I----
"'I
".
o1
2 3
4 5 6 7
8 91011
12131415
1&17 1819
20212223
24252627
28293031
12
~
NC
CraPs Oame
~-N46R6,
PAL DESIGN SPECIFICATION
, BRAD MITCBELL07 /24;8i
te2'
36 STA'l'B MACHINB
MMI FIBID APtlCATIONS BNGINBBR DALLAS, 'l'BXAS
/SWCLK
sa
He NC NC NC /T ,CK GND
/124 /Q3 /Q2 /Ql /r¥J /ROLL vec
/OC ,/SWCI: /QS
,a-s
11'(VCC) ROLL - jS
+
a*
IJ!'(VCC) SWCK - /eB:* ROLL-
QQ :- /00
+ /r¥J
,I SWITCH
'*/Q2 */Q3 */124
Q2 :- QQ:"'Ql*/Q2
/Ql* Q2
+
* Q2
+ /QQ
*/QS*T
*/QS*T
*/QS*T
"
Q3 :- QQ* Q1* Q2*/Q3
/Q2* Q3 ;
+
*Q3
+ /r;tJ
*Q3
+'
/Ql
*/Q5*T
*/QS*1t
*/QS*1
*/QS*T
124 :- QQ* Ql* Q2* Q3*/Q4*/QS*T
+
/Q3* Q4*/QS*T
* Q4*/QS*T
* Q4*/QS*'r
*Q4*/Q5*T
QQ* Ql* Q2'*Q3* Q4~/QS*T
/Ql*/Q2*/Q3*/Q4* QS
+ /r¥J* Ql*/Q2*/Q3*/Q4* QS
QS :+
CONTROLLED CLOCK
*T, DECODB DERIVED PROM KARNAUGH MAP
*/QS*T
*T
Ql :- /r¥J* Q1*/Q2*/Q3*/Q4
+ QO*/Ql*/Q2*/Q3*/Q4
*T
+ lQO* Ql
'*/QS*T
+ QO*/Ql
*/QS*T
+
/Q1
+
/Q2
+ /QQ
FLU FLOP USED AS A
IOBBOUNCB SWITCH
ROLL
Craps Game
FUNCTION TABLE
sweLK S R CK T Q5 Q4 Q3 Q2 Q1 QO ROLL SWCK
-INPUTS
,S S R C T
,W
K
--OUTPUTS-QQQQQQ
R S
5 4 3 210
0 W
,CL
L C
L K
,K
COMMENTS
----------------------------------------------------------------------------C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
x
x
x
x
x
x
xXL
xXH
xXH
xXH
xXH
xXH
Xx XH
XxXH
xxXH
Xx XH
Xx XH
xx XH
xxXH
xxXH
xxXH
xxXH
xx XH
xxXH
xxXH
xxXH
xxXH
xxXH
xxXH
xx XH
xxXH
xxXH
xxXH
xxXH
xxXH
xxXH
xxXH
Xx XH
xxXH
xxXH
Xx XH
xx XH
XxXH
HL L L
L HHL
HHL L
HHHL
HHL L
HL HL
HHL L
HHHL
L HL L
HHHL
L L L L L L
L L L L L H
L L L L HL
L L L L HH
L L L HL L
L L L HL H
L L L HHL
L L L HHH
L L HL L L
L L HL L H
L L HL HL
L L HL HH
LLHHLL
L L HHL H
LLHHHL
LLHHHH
LHLLLL
LHLLLH
L HL L HL
L HL L HH
L HL HL L
L HL HL H
L H L II H L
L HL HHH
L HHL L L
L HHL L H
L HHL HL
L HHL HH
LHHHLL
L HHHL H
LHHHHL
L HHHHH
HLLLLL
HL L L L H
HL L L HL
HL L L HH
L L L L L L
XXXXXX
XXXXXX
XXX XXX
XXXXXX
XXXXXX
XXXXXX
XXX XXX
XXXXXX
XXXXXX
XXXXXX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
L L
HL
HH
HL
HH
L L
L L
L L
HH
HL
CYCLE THRU THE TOTAL 36 STATES (STATE 0)
(STATE 1)
(STATE 2)
(STATE 3)
(STATE 4)
(STATE 5)
(STATE 6)
(STATE 7)
(STATE 8)
(STATE 9)
(STATE 10)
(STATE 11)
(STATE 12)
(STATE 13)
(STATE 14)
(STATE 15)
(STATE 16)
(STATE 17)
(STATE 18)
(STATE 19)
(STATE 20)
(STATE 21)
(STATE 22)
(STATE 23)
(STATE 24)
(STATE 25)
(STATE 26)
(STATE 27)
(STATE 28)
(STATE 29)
(STATE 30)
(STATE 31)
(STATE 32)
(STATE 33)
(STATE 34)
(STATE 35)
(STATE 0)
EXERCISING THE SET-RESET FLIP FLOP
AND THE SWITCHED CLOCK
19
4·269
Craps Game
DESCRIPTION
THIS PAL IS A 36 STATE MACHINE USED TO SIMULATE THE EXACT ROLL OF THE DICE.
THE STATE MACHINE IS SIMILAR TO THE "ELECTRONIC DICE GAME".
4.270
Craps Game
36
STATE MACHINE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
CXXXXXXIXXXXHBBHBBX1
CXXXXXXOXXXXHHHHHLX1
CXXXXXXOXXXXHHHHLHXl
CXXXXXXOXXXXHHHHLLXl
CXXXXXXOXXXXBlmIJmXl
CXXXXX~OXXXXImHLHLXl
CXXXXXXOXXXXHHHLLHXl
CXXXXXXOXXXXHHHLLLXl
CXXXXXXOXXXXHHI,HHHX1
CXXXXXXOXXXXHHLHHLXl
CXXXXXXOXXXXHHLHLHX1
CXXXXXXO XXXXHHLHLLXl
CXXXXXXOXXXXHHLLHHXl
CXXXXXXO;XXXHHLLHLXl
CXXXXXXOXXXXHHLLLHX1
CXXXXXXOXXXXHHLLLLXl
CXXXXXXOXXXXHLHHHHXl
CXXXXXXOXXXXHLHHHLXl
CXXXXXXOXXXXHLHHLHX1
CXXXXXXOXXXXHLHHLLXl
CXXXXXXOXXXX~HHXl
CXXXXXXQxxxXHLHLHLXl
CXXXXXXOXXXXHLHLLHX1
CXXXXXXOXXXX~LXl
CXXXXXXOXXXXHLLmtHx1
CXXXXXXOXXXXHLLHHLXl
CXXXXXXOXXXXHLLHLHXl
CXXXXXXOXXX~Xl
CXXXXXXOXXXXHLLLHHX1
CXXXXXXQXXXXHLLLHLn
CXXXXXXOXXXXHLLLLHXl
cxxxxxXOXXXXHLLi.LLXl
CXXXXXXOXXXXLHHHHBX1
CXXXXXXOXXXXLHHHHLXl
CXXXXXXOXXXXLHHHtHXl
CXXXXXXOXXXXLHHHLLX1
CXXXXXXOXXXXHHHHHHXl
C10XXXX10XXHXXXXXXH1
C01XXXXllXXHXXXXXXtl
CllXXXX10XXLXXXXXXLl
C11XXXX11XXHXXXXXXLl
C11XXXX10XXLXXxxxXLl
C10XXXX11XXHXXXXXXHl
Cl1XXXX10XXHXXXXXXHl
CllXXXXllXXHXXXXXXHl
C01XXXX10XXLXXXXXXLl
CllXXXXl1XXHXXXXXXLl
PASS SIMULATION
Craps Game
36 STATE MACHINE
11 1111 1111 2222 2222 2233
0123 45618901
~34S
6789, 0123 4567 8901
o ---- ---- ---- ,---... --- ..,--- ---- -----..:' ~"'-,' -..-- ---.,. ---- ---- ----
/S
2-..,-X
R*ROLL
1 - x...-
8 ---~
9 --16
17
18
19
-----------
x-- --- --- ---- ---- -----X- ---- ..-x- ~-x---x- -x-...
--x- ----....""'-- --...- ---- ..,xx-x- ---x --x... --X--";X- -x-.;.--x -X- "';-X--"'X- --X- -x--x- ---x ---- ---- ---- -xx---x --x- ---- ---- ---- -xx---x --x --X- ---- ---- -xx---- --x- ---x ---- ---- -xx-
---------:..-----------------
/QO*/Q2*/Q3*/Q4*T
/QO*/Q5*T
/QO*Ql*/Q2*/Q3*/Q4*T
QO*/Ql*/Q2*/Q3*/Q4*T
/QO*Ql*/Q5*T
QO*/Ql*/Q5*T
24 ---QO*Ql*/Q2*/Q5*T
25 --/Ql*Q2*/Q5*T
26 - - --X- ---- ---x --- ---- -XX- ---- /QO*Q2*/Q5*T
--X- - - -
-xx- ----
QO*Ql*Q2*/Q3*/Q5*T
---x ----
-XX- ----
/Ql*Q3*/Q5*T
40 --- ---x ---x --x --x --X41 -".-- --- - .. -,. ---- --x- --x
42
-""'----x
43
---- ---- --X- ---- ---x
44 --- --X- ---- ---- ---- ---x
-------------------------
--x ---x ---x
32
33
34
35
---- ---- --X--X- ---- ------- --x- ---
--x ---- -xx- --- /Q2*Q3*/Q5*T
--x --- -xx- --- /QO*Q3*/Q5*T
48
49
50
-xx-xx-..,X- ---- ----xx-xx-xx---x ---x ---x ---x ---x -xx---- --x- -x- --x- --x- ---x
--x- ---x --x- --x- --x- --x
56
57
---x ---- ---- ---- ---- ---- ----
LEGEND:
QO*Ql*Q2*Q3*/Q4*/Q5*T
/Q3*Q4*/Q5*T
/Ql*Q4*/Q5*T
/Q2*Q4*/Q5*T
/QO*Q4*/Q5*T
QO*Ql*Q2*Q3*Q4*/Q5*T
/Ql*/Q2*/Q3*/Q4*Q5
/QO*Ql*/Q2*/Q3*/Q4*Q5
---- ---- ---- ---- ---- ---- ----
x: FUSE
NOT
BLOWN (L,N,O)
NUMBER OF FUSES BLOWN = 727
-x-~ /CK*ROLL
-:
FUSE BLOWN
(H,P,l)
Craps Game
Logic Diagram PAL16R6
36-5tate Machine
SWCll(
J-h
.....
0123
4561
89101-1
12131415
16111819
20212223
24252821
28293031
0
r-J
1
2
3
4
5
•,
S
2
....
19
..,
"
c:'~
~
,
8
10
~!-~
'"
11
./
12
13
14
15
R
3
~~
"..,
....
16
11
18
19
D
./
"
22
23
4
i--
""
20
..
c:
HC "--I
0"--
~~
..
24
~
~
~
~
Dl
~
25
26
27
28
"
29
HC
5
....
30
31
....
~
32
33'-"
34
35
'I--
36
HC
6
....
~
31
38
39
....
....
,
40
,
41
42
43
....
44
'"
.'
./
41
HC
7
....
..,
..
'.
."
.""
48
"-
""
55
T
8
....
....
"
"
82
W.
c
>-J
57
51
59
80
CK
~>---
../
53
"
....
~~
0123
4561
,g 1011
121314-15
16111819
20212223
24252121
28293031
~~
~
12
SWCK
~ OC
4-273
Craps Game
PAL16L8
IC3
DICE DECODER
MMI FIELD APPLICATIONS ENGINEER DALLAS,TEXAS
NC NC /QO /Ql /Q2 /Q3 /Q4 /Q5 NC GND
NC NC /NCIS /NC2S /NC4S /lS /2S /4S /8S VCC
IF (VCC)
IS = /QO* Ql
*/Q3* Q4*/Q5
+ /QO
*/Q2*/Q3*/Q4* Q5
+ /QO* Ql* Q2*/Q3
*/Q5
+ QO*/Ql* Q2* Q3
*/Q5
+ /QO
*/Q2* Q3*/Q4*/Q5
+ QO
* Q2* Q3*/Q4*/Q5
+ NClS
IF (VCC) NClS
=
QO
*/Q2*/Q3*/Q4*/Q5
+ QO*/Ql
*/Q3*/Q4*/Q5
+ /QO
* Q2*/Q3* Q4*/Q5
+ QO*/Ql*/Q2
* Q4*/Q5
PAL DESIGN SPECIFICATION
BRAD MITCHELL 04/07/81
JTHE MINIUM LOGIC REQUIRED
JTO DECODE THE 1S BIT WAS DERIVED
JFROM THE KARNAUGH MAP
JNC1S IS USED AS ADDITIONAL DECODE
JFOR is
+ QO
*/Q2* Q3* Q4*/Q5
+ /QO* Ql* Q2
* Q4*/Q5
IF (VCC)
2S = /QO* Ql*/Q2*/Q3*/Q4* Q5
+ QO*/Ql*/Q2*/Q3*/Q4
+ QO*/Ql*/Q2
*/Q4*/Q5
+
Ql* Q2* Q3*/Q4*/Q5
* Q3*/Q4*/Q5
+ /QO* Ql
+ /QO* Ql* Q2
*/Q4*/Q5
+ NC2S
IF (VCC) NC2S
=
QO* Ql
*/Q3* Q4*/Q5
+ /QO*/Ql* Q2
* Q4*/Q5
+ /QO
* Q2* Q3* Q4*/Q5
+
/Q1
*/Q3*/Q4*/Q5
+
/Q1
* Q3* Q4*/Q5
IF (VCC)
4S
IF (VCC) NC4S
IF(VCC)
8S
JNC2S IS USED AS ADDITIONAL DECODE
JFOR2S
= QO* Q1*/Q2*/Q3*/Q4
+ /QO*/Q1* Q2*/Q3
*/Q5
t /QO* Q1* Q2* Q3
*/Q5
+
/Q1*/Q2* Q3
*/Q5
+
Ql*/Q2*/Q3
*/Q5
+ /QO
* Q3*/Q4*/Q5
+ NC4.S
JFROM KARNAUGH MAP
=
JNC4S IS USED AS ADDITIONAL DECODE
JFOR 4S
Q2* Q3* /Q4 */Q5
* Q2
*/Q4*/Q5
+
QO
=
QO* Ql*/Q2* Q3
*/Q5
/Ql*/Q2*/Q3* Q4*/Q5
Ql*/Q2* Q3* Q4*/Q5
Ql* Q2*/Q3* Q4*/Q5
/Ql* Q2* Q3* Q4*/Q5
QO
* Q2
* Q4*/Q5
/Q2*/Q3*/Q4* Q5
+
+
+
+
+
+
4-274
JFROM KARNAUGH MAP
,FROM KARNAUGH MAP
Craps Game
FUNCTION TABLE
Q5 Q4 Q3 Q2 Q1 QO NC4S NC2S NelS 8S 4S 2S lS
INPUTS
;
;Q Q Q Q Q Q
;5 4 3 2 1 0
NNN
C C C
421
S S S
. OUTPUTS
8 .. 2 1
S S S S
COMMENTS
(DICE ROLL)
-----------------------------------------------LLLLLL
LLLLLa
I. L L L a L
L L L L a a
I. L I. a L I.
LLLaI,ra
LLLaaL
LLLaHa
L L H L L L
LLaLLa
LLaLHL
LLHLaa
LLaaLL
LLHaLH
LLaaaL
LLRHaa
I. a I. L L L
LaLLLa
LaLLaL
I. a L LH a
LaLaLL
LBLHLa
LHLHHL
LaLaaH
LHHLLL
LHaLLB
LBHLaL
LHRLaH
LaHaLL
I. R H R L H
I. R B R H I.
LRHRaH
atLLLL
aLL L I. a
HLLLHL
R L I. LR a
L a L
L a a
L L I.
L L a
La L
a a a
L L L
aLL
L L L
L L L
L L L
L L L
aLL
R L L
aLL
R L L
L L L
L L a
L L L
L a I.
L a a
L L I.
L La
L H L
L HI.
L R a
L I. I.
I. L H
L a I.
L a L
I. a H
L I. L
L I. I.
L L L
I. L L
I. L L
L L a L
L L a a
La L L
L a I. a
L a a L
L a a a
L L R a
La L L
I. R L a
L a H I.
L a a a
H L I. L
L a I. I.
La L R
I. a a L
L a a a
aLL L
aLLa
La L a
I. Ba L
L a a a
aLL L
a L.L H
a L a I.
I. a a L
L B a a
a I. L L
aLL a
R L R L
a L R R
I. R R a
R I. I. L
H L L H
R L a I.
R I. a a
H a L.L
2
3
4
5
6
7
3
4
5
6
7
8
4
5
6
7
8
9
5
6
7
8
9
10
6
7
8
9
10
11
7
8
9
10
11
12
------------------------------------------------
Ell
Craps Game
DFSCRIPTION
THIS PAL DECODES THE 36 STATE MACHINE INTO A BINARY REPRESENTATION OF THE
ROLL OF THE DICE (2 THRU 12). THERE ARE 36 POSSIBLE COMBINATIONS FOR THE
TWO DICE.
THE NUMBERS ARE DECODED SO THAT THE PROPER ODDS ARE MAINTAINED
FOR THE ROLL OF EACH NUMBER.
Craps Game
DICE DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
XXllll11XXXXHLHHLHHl
XX01lll1XXXXLLHLLHH1
XXI0lll1XXXXHHHHHLBl
XXOOl111XXXXLHHLHLBl
XXl10111XXXXHLHHLLHl
XX010111XXXXLLLLLLBl
XXI00111XXXXHHHLLHHl
XXOOOll1XXXXHHLHHLHl
XX1110l1XXXXHHHLHLBl
XX0110l1XXXXHHHHLLHl
XX1010l1XXXXHHHLLLHl
XX0010l1XXXXHHHHHHLl
XX1100l1XXXXHHLHHLHl
XXOI0011XXXXHHLLHLHl
XX1000IIXXXXHHLHLLHl
XXOOOOl1XXXXHHLLLLHl
XX11110IXXXXHHHHHHLl
XX01l101XXXXLHHLHHLl
XX101101XXXXHHHLHLHl
XX001I0IXXXXHLHHLLHl
XX110I01XXXXLLHLLLHl
XX010I01XXXXHHHHHHLl
XX100I0IXXXXLHHLHHLl
XX000101XXXXHI,HHT.BL]
XX1l1001XXXXHLHHLLHl
XXOII00IXXXXLLHLLLHl
XX1010 OlXXXXHHBHHHI,l
XX00100IXXXXLHHLHHLl
XX11000IXXXXHLHHLHLl
XXOI000IXXXXHLHLLHLl
XXI0QOOIXXXXLLHLLLHl
XXOOOOOIXXXXHHHHHHLl
XX1ll110XXXXHHHLHHLl
XX01l110XXXXHHHHLHLl
XXI0l110XXXXHHHLLHLl
XXOOl110XXXXHHHHHLLl
PASS SIMULATION
4·277
Craps Game
DICE DECODER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o ---- ---- ---- ---- ---- ---- ---- ---1
2
3
4
5
6
7
----------------------
-x-- -x-x---x--x-x---x-- ----------------
---- ----
x--x--x---x--x--x-x---
-x-x---x-x---x----x---
----x--x--x--x--x-x---
x--x--x--x--x--x---x--
------~---
------------~
QO*Q1*/Q2*Q3*/Q5
/Q1*/Q2*/Q3*Q4*/Q5
Q1*/Q2*Q3*Q4*/QS
Q1*Q2*/Q3*Q4*/Q5
/Q1*Q2*Q3*Q4*/Q5
QO*Q2*Q4*/Q5
/Q2*/Q3*/Q4*Q5
8 ---- ---- ---- ---- ---- ---- ---- ----
9
10
11
12
13
14
15
---- -x-- -x-- x------ x--- x--- -x----- x--- -x-- -x----- ---- x--- x------ ---- -x-- x------ x--- ---- ------- ---- ---- ----
x--x---x--x-x---x----x
x--------------x------
---x--x--x--x--x------
----------------------
16
17
18
19
20
21
22
23
---- ---- ---- ---- ---- ---- ---- ------- x--- -x-- x--- x--- x--- -x-- ---- /QO*Q1*/Q2*/Q3*/Q4*Q5
---- -x-- x--- x--- x--- x--- ---- ---- QO*/Q1*/Q2*/Q3*/Q4
---- -x-- x~-- x--- ---- x--- x--- ---- QO*/Ql*/Q2*/Q4*/Q5
---- ---- -x-- -x-- -x-- x--- x--- ---- Ql*Q2*Q3*/Q4*/Q5
---- x--- -x-- ---- -x-- x--- x--- ---- /QO*Q1*Q3*/Q4*/Q5
---- x--- -x-- -x-- ---- x--- x--- --~- /QO*Q1*Q2*/Q4*/Q5
---- ---- ---- ---~ ---- ---x ---- ---- NC2S
24
25
26
27
28
29
30
31
32
33
34
----------------------------------
QO*Q1*/Q2*/Q3*/Q4
/QO*/Q1*Q2*/Q3*/Q5
/QO*Q1*Q2*Q3*/Q5
/Q1*/Q2*Q3*/Q5
Q1*/Q2*/Q3*/Q5
/QO*Q3*/Q4*/Q5
NC4S
---- ---- ---- ---- ---- ---- ----
x--x--x---x-x---x--
-x-----x-x---------
---x---x--x-x---x--
x--x--x---x--x--x--
-x-- x--x~-- -x----- x------ x--x--- x--x--- x------ ---x
----------------------
/QO*Q1*/Q3*Q4*/Q5
/QO*/Q2*/Q3*/Q4*Q5
/QO*Q1*Q2*/Q3*/Q5
QO*/Q1*Q2*Q3*/Q5
/QO*/Q2*Q3*/Q4*/Q5
QO*Q2*Q3*/Q4*/Q5
NelS
-------- ---- ---~
---- ---- ---- ---- ---- ---- ------- ---- -x-- -x-- x--- x--- ---- Q2*Q3*/Q4*/Q5
-x-- ---- -x-- ---- x--- x--- ---- QO*Q2*/Q4*/Q5
40 ---- ---- ---- ---- ---- ---- ---- ---41 ---- -x-- -x-- ---- x--- -x-- x--- ---- QO*Ql*/Q3*Q4*/Q5
42 ---- x--- x----x-- ---- -x-- x--- ---- /QO*/Ql*Q2*Q4*/Q5
43 ---- x--- ---- -x-- -x-- -x-- x--- ---- /QO*Q2*Q3*Q4*/Q5
44 ---- ---- x--- ---- x--- x--- x--- ---- /Ql*/Q3*/Q4*/Q5
45 ---- ---- x--- ---- -x-- -x-- x--- ---- /Ql*Q3*Q4*/Q5
48 ---- ---- ---- ---- ---- ---- ---- ---49 ---- -x-- ---- x--- x--- x--- x--- ---- QO*/Q2*/Q3*/Q4*/Q5
50 ---- -x-- x--- ---- x--- x--- x--- ---- QO*/Ql*/Q3*/Q4*/Q5
51 ---- x--- ---- _x-- x---' -x-- x--- ---- /QO*Q2*/Q3*Q4*/Q5
52 ---- -x-- x--- x--- ---- -x-- x--- ---- QO*/Q1*/Q2*Q4*/Q5
53 ---- -x-- ---- x--- -x-- -x-- x--- ---- QO*/Q2*Q3*Q4*/Q5
54 ---- x--- -x-- -x-- ---- -x-- x--- ---- /QO*Ql*Q2*Q4*/Q5
LEGEND: X: FUSE NOT BLOWN (L,N,O)
- : FUSE BLOWN
(H,P,l)
NUMBER OF FUSES BLOWN = 1351
4·278
Craps Game
Dice Decoder
Ne
Logic Diagram PAL16L8
1
o'i
J
4
~
891011
6 1
12131415
161]18i9
20212223
24252621
28293031
0
~
1
2
3
4
5
Ne 2
•,
.
'9
....
....
....:~
.'
......
;
>-t1
9
"
'11
12
.""
i-'----l
<~,'
18
15
...
...
J
~.t---
....
'8 ,
~
11'
fB
19
Q1
4
... >--
20
21
22
..
"
'
...
.'
,' ....
.
24
"
27
2B
5
....
"3'
31
16
"
'.'
...
.. :;
~t---
..,.
. '::
"
32
33
~
.
34
"
,.
36
37
38
6
....t--:-
~t>-J
25
.
11
:'"1'5
....
...
.....
4D
41
"
.1-:--..,.
J
43
..
14
~
44
45
NC2S
41
7
...
...
~
> ~<
,>
4.
....I------,-
"
,....;
.
49'
".
"
51
U
8
....
54
;~-.
55
.'
2-
"
"
..
"
57
,~
....:t----
b-J'
C"
5'
61
Ne 9
...
"6J
.
...
0, t 2 3
4 5 6 1
. , 1011
121314 IS
1&171119
13
.
;..
.
'.
."
~~.
21212223
24252&21
11
11
NC
NC
28293031
4.279
era.-Game
PAL16R4
IC4
STORE POINT /2, /7, AND /11 DECODE
Mm. FIELD APPLICATIONS ENGINEER DALLAS, TEXAS
CLK /8S /4S /2S /lS /A /B /C IT GND
/OC NC /11 /p1S /p2S /p4S /PBS /7 /2 VCC
P8S :-
8S
*T
*T
*T
*T,
,SAVE POINT
,SAVE POINT
4S
*/A* B./C
P4S*/A* B* C
P4S* A*/B
P4S* ..A* B* /C
*T
*T
*T
*T
,LOAD INTO POINT IF FIRST ROLL
,SAVE POINT IF NOT FIRST ROLL
,SAVE POINT
,SAVE POINT
2S
*/A* B*/C
P2S*/A* B*C,
P2S* A*/B
P2S* A* B*/C
*T
*T
*T
*T
,LOAD INTO POINT IF FIRST ROLL
,SAVE POINT IF NOT ,FIRST ROLL
*/A* B*/C
P1S*/A* B* C
P1S* A*/B
P1S* A* B*/C
*T
*T
*T
*T
,LOAD INTO POINT IF FIRST ROLL
,SAVE POINT IF NOT FIRST ROLL
+
+
+
P2S :-
+
+
+
P1S :-
, LOAD 'INTO PoINT ON FIRST ROLL
, SAVE POIN't IF NOT FtRS',I! ROLL
*/A* B*/C
PBS*/A* B* C
PBS* A*/B
PBS* A* B*/C
+
+
+
P4S :=
PAL DESIGN SPECIFlCATAION
BRAD MITCHELL 07/28/81"
lS
+
+
+
,SAVE POINT
,SAVE POINT
, SAVE PO.INT
,SAVE POINT
IF(VCC) 2
• /8S*/4S* 2S*/1S
, DECODE THE NUMBER 2
IF(VCC) 7
.. /8S* 48* 2S* lS
, DECODE THE NUMBER 7
IF(VCC) 11
.
, DECODE THE NUMBER 11
8S*/4S* 2S* lS
FUNCTION TABLE
CLK 8S 4S 2S lS
ABC T, P8S· P4S P2S. P1S 2 7 11
,-------INPUTS------,C 8 4 2 1
A B CT
,L S S S S
,K
C
C
C
C
C
C
C
C
L
a
L
L
L
L
L
a
LL
,L L
LL
L L
L L
La
H a
L a
L
a
L
L,
L
L
a
H
L L L
L a L
L B a
H L X
aa L
L a L
L a L
L a L
L
a
H
a
a
H
a
H
---..;.otJTPtJTs---P P P P
8 4 2 1
S S S S
LL L
a I. L
H L L
,'aLL
a L L
L L H
La a
L
a
a,
H
B
L
a
HI. H H'
2 71
1
L
L
L
L
L
a
L
L
L L
L L
LL
L L
L L
L L
H L
L H
INITIATE ALL REGISTERS TO LOW
LOAD,A NUMBER 'INTO POINT"
SAyZ THE NUMBER IN POINT
SAVE TJiE NmmER IN POINT
SAVE TBB, NOMBQ IN POINT.
LOAD POINT & DECOD~ A "2.LOAD POINT &' DECODE A "7·
.LOAD POINT & DECODE A "11"
"
-------------------------~~..-----------"'!"---~-...~-----~--------~------~---
Craps Game
DESCRIPTION
THIS PAL IS USED TO STORE THE POINT IN THE GAME.
IT ALSO. DECODES; THE NUMBERS
2, 7, AND 11 TO BE USED IN DETERMINING WIN OR LOSE.
STORE POINT /2,
1
2
3
4
5
6
7
8
/7, AND /11 DECODE
Cl1111111XXXHHHHHHHl
COI101010XXXHLHHLHHl
CIIIIIOOOXXXHLHHLHHl
C111101XOXXXHLHHLHHl
CIIII0010XXXHLHHLHHl
ClIOIIOIOXXXHHLHHHLl
ClOOOIOIOXXXHLLLHLHl
C01001010XXXLLLHLHHl
PASS SIMULATION
4.281
Crap8.Came
S'l'ORB POINT AND /2,
/7,
AND /11 DECODB
1111n 11112222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
0
1 x-- x-- -x8
x---
42
43
x-- -x-- -x- ..x-xx- -x----x
x-- -x---x
-x- x-.--- ·--x
-X- -x-x-·
x-- -x----x x--- -x---x -X-- x----X -X-- -x-xx--- -xX-X -x--x-x x--x-x -x-x- x..-- -xx-- -x-x
-x-- x--x
-x-- -x-x
48
49
-x- x--
9
16
17
18
19
24
25
26
27
32
33
34
35
40
41
LEGEND:
x:
/8S*/4S*2S*/1S
/8S*4S*2S*lS
x--
8S*/A*B*/C*T
P8S* /A*B*C.*T
PBS*A*jB*'1'
x-- -X- PBS*A*B*/C*'1'
x- -x--
-x:-
xx--xx--
4S*/A*B*/C*'1'
P4S*/A*B*C*'1'
-X-- P4S*A*jB*'1'
-x-- P4S*A*B*/C*'1'
-x--
-x--x--x-xx--- -x-x- -x-.... Xx-- -x-
--
----x-- -xPUSB NO'!' BLONN (L,N,O)
NUMBER OF FUSES BLONN. 616
-x--
-x- -x-x-
2S*/A*B*/C*'1'
P2S*/A*B*C*'1'
P2S*A*jB*T
P2S*A*B*/C*'1'
lS*/A*B*/C*'1'
P1S*/A*B*C*T
P1S*A*jB*T
PlS*A*B*/C*'1'
8S* /4S*2S*lS
roSB BLONN
(H,P;l)
Craps Game
store Point and 2, 7, and
ClK
11 Decode
Logic Diagram PAL16R4
1
0123
4567
891011
12131415
15171819
20212223
24252627
2B293031
,
0
~
.
2
3
5
6
19
)
3
...JF
.A
-'"
8
9
>--
'"
"
"
"
73
J
.......
:>--J
....
~
"
))
25
..
.
r-~
""'"
D
./
23
~
i::
....
Q-
~~
27
25
16
~
27
~
28
29
30
37
5
,;..
.
~
c
32
,.. .......
>--
3J
"
"
35
36
3)
38
6
..
..
"
.A
~
....
""'"
'"46
OJ
.""'/"
45
47
7
...
.
~
48
48
"
53
54
55
P45
tal
~
P25
tQ]
~
....
13
~.r---
...
....
"
""
"
:>--tl
60
62
...
~
~
...
....
5)
9
....
~
50
5)
B
7
>5
78
19
20
27
22
4
18
11
NC
6J
.1--.....
0123
4567
891011
12131415
16171819
Z(JZI2ZZJ
24252627
28293031
~
4·283
Notes
4·284
Traffic Signal Controller
PAL16R4
4·285
Traffic Signal Controller
An Example of Sequential Logic Design
with PALs
Figure 1 illustrates a simple traffic intersection consisting of two
one-way streets, direction A and direction B. Each direction has
a signal consisting of red, yellow and green lamps which are
activated with appropriately named active low signals. Also,
each direction has a sensor which provides an active low signal
indicating the presence of an oncoming vehicle. Our controller
Is to manage this intersection with the sensors as inputs and the
lamps as outputs, as shown in Figure 2.
The specifies of the controller operations are detailed with a
state graph, shown in Figure 3.
SENA . SENB
A
-------B
r------.
I
1--
... _----'.
'§EiiiA
SENA' SENB
Figure 1. Traffic Intersection
Figure 2 also includes the system clock and an initialize (or
reset) signal, which drives the controller to a pre-defined initial
state. This raises two important'issues in designing sequential
logic. with PALs. First, all circuit implementations of sequential
logic with PALs are totally synchronous. This implies that all
state variables (flip-flops) change at {he same time, precisely
after the rising edge of the clock. 6ecomd, PAL sequential logic
designs should include a means for initialization to implement
test programs and ensure reliable circuit operation.
SEf.iA----\
I----REDA
1-----__ R'Ei5B
miD----f
INIT----f
TRAFFIC 1-:----,-rn:A
SIGNAL
CONTROLLER 1----yELB
I------GRNA
I----GRNB
CLK---p
Figure 2. Traffic Signal Controller
Figure 3. State Graph -
Traffic Signal Controller
In this format. each bubble represents a stable state, i.e., an
output configuration, lasting at least one clock cycle. Inside the
bubble is the name of the state (60-611) and the outputs
associated with that state. This particular circuit's outputs are
specified to be a function of the state of the flip-flops only, and
are not directly affected by thT' inputs. For the sake of simplicity
in the state graph, the transitions involving INIT are omitted;
INIT Simply drives the circuit to 60 from any state, regardless of
other inputs.
Another method of expressing the state graph information is
with a state table, shown in Figure 4. Each row in the state table
corresponds to a state (or bubble from the state graph). The first
four columns give the next state for each of the possible input
combinations. The output is also given for each state in the
table. The state graph may be omitted but a state table is
generally required to design the circuit.
The next ,step in the design is to assign.state variables. This
process also involves selecting the PAL or PALs to be used.
Referring to Figures 2 and 3, the circuit requirements are seen to
be 4 input, 6 output and 12 internal states, 6ince the intputloutput
pin requirements do not impose restrictions in either a 20 or 24
pin package, the states requirement will be addressed first. A
PAL16R4 can implement the 12 states with its 4 flip flops.
However, only 4 combinatorial outputs are available. This
means that the flip-flop outputs (or state variables) will need to
Traffic Signa. Controtler
be utilized as circuit outputs as well. One such approach' is to
take advantage of the fact that REDA=
.and implementing
REDA with one flip"fl~p. and REDS with an external inverter.
Such a state variable aSSignment and resulting transition table is
in Figure 5. This Is generated by substituting the variable
assignments into the state table.
ReDs
NEXT STATE
CU~RENT
STATE
INPUT SENA, SENB
"
01
10
11
""
00
SO
S1
52
54
50
S2
52
53
54
53
54
53
54
55
$'
52
53
OUTPUT
GRNA
REDB
REDA
YELA
51
0
0
1
52'
0
0
1
0
0
54
53
54
0
55
55
55
0
YELB
GRNB
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
55
56
56
56
56
0
1
0
1
0
0
56
57
56
510
57
1
0
0
0
0
1
57
'.'. S8
59
510
S8
sa
58
1
0
o'
0
1
59
510
59
510
59
1
0
0
0
0
0
1
510
1
0
0
0
0
1
58
59
510
511
511
511
511
t
0
0
0
0
1
5.11
SO
50
50
50
1
0
0
0
1
0
Flg!,re 4. S.... Table -
CURRENT ','
STATE
Traffic SIgnal Control...,
INPUT/NEXT STATE
01
10
00
OUTPUTS
11
0
.0
0
0
0
0 0
0 1 1 0 0
0
0
0
0
0
0
1 0
0
0
0
0
0 1
1 0
0
0 0 0 1
0
0
0
b
0
0
0
0
0
1
0
0
1 1
0
0
1
1
0
0
1 1
0
0
0
0
0
0
0
0
0
0
0
0
1
P
0
0
0
0
1 0
0
1 0
0
1 0
1
0
1 0
0
0 1 1 0 0
0
0
1 0
0
1 0
1 0
0
0
0
0
0
0
1 1
0
0
0 0
<0:'-"
0
1
1
0
0
0
0 0 0
0 0 1
0
d 1
0 1 0
0
0
1 0
"
0
0
1
0
0
1 1
0
0
1
1 ' '0 0
1
1 0
0 0 0 0"
1
1
0
1 0 0 0
1 0 0 0
0
0
.(
0
t, 1,
0
0
0
00
1
0
1 0
0
0
0 1 1
1 0 0
1 0
l' 1
0
1
0
0
1 0
1
1
1 0 ,,1
0
0
0
0
0
0
0
0
0
0
0 1
0
1
1
1
1 0 0
1
0 1
0 ,0 0 0
0 1 0
1 0 0
1 0
0
0 0
1 0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0 0
1 .0 0 0 1
1
1
1
1
1
0
'.' O3,02.Q1 QO
0 0 0
SO
,0
51
0 0 0
52
53
54
55
D. 0
1 0
0'
0
0
1 0 0
1 0, 1
0
1
1
56
1 0
57
1' 0 0
0
1
sa
~
0 '1
0
0
~.
0
59
510
1
511
t
0
1
1 0
1
o
Input "SENA. 5ENB
CurrentiNext5tate= 03, 02.01. QO/03+,02+' 01+, 00+
Output =AEDA; VELA. GRNA. REDB.VEI-B. GRNB,
FIgure S. State A_gnman! No. 1ITnlnlltion Tab..
1
'4-287
m
TraHi.c~Sign."
From this table, Karllaugh maps for.D flipflop next.state
equations and output functions can be written, by trans<;ription
from the transition table, and minimized equations derived. This
is shown in Figures 6 through 10. The state machine and PAL
04
Controlier
implementation follows, Note that the INIT te.rm is simply
AND'ed with ali next state products tqgenerate the,initialize
function,
02
03,02
03,02
01, 00
03.,02
00
00
0
01.0
111
l-=+::..:.......,:-'--I~~
I\V y
0
X
0
X
01, 00
0
lller
lob
SENA, SENB
SENA, SENB = 00
SENA, SENB = 01
03,02
01, 00
03,02
00
11
01
01,0 0
03,02
00
= 01
01
01
0
0
0
0
11<[ X
X
Y
X.
X
0
/x ~ 1\
10 .0
X
X
SENA, SENB = 10
10 .,0
0
SENA, SENB " 11
02 = 01 00' + 02 01 QO +
SENA,SENB Q3 Qi Co
Figure 8. K Maps for 02+
01
03,02
01
11
10
00
0
0
0
0
01
J)
0
0
lei
11 . 0
x
X
0
10 . (
X
X
J)
SENA, SENB = 00
01,0 0
00
00
0
0<:Y
11
0
101c[
01
01
11
10
0
0
0
0
01Y
0
0
11
0
X
X
0
""
,,
,
../
....
....
••
10
11
13
14
to..
"
~
~
.""
...
...
A
.
../
22
23
....
c::....
~
~'l
r""""D 01-
'"
19
20
21
4
ral- ~
""
11
3
~1
~c::
~'l
24
"
26
~
""
"
D
j
28
"
30
11
Ne 5
....
to..
r
>
01-
,.
"
34
'"
j
36
38
...
39
lj
~
H~1
JC.
31
33
Ne
~
to..
...
....
~
~
40
"
""
""
""
./
44
Ne
,
41
....
to..
....
...
""
.,
""
\I
f
>J
Ne
B
to..
""
...
lit
~.
\6
-..
"
""
"
Ne
,
.
.
D
61
63
...1L
~
o
t 2 3
4!i 6,1
8 9 1011
1213 14
1~
16t} 11119
2021 2223
24 2S26 21
28293031
~
~
5
r--
./
61
Dl
~
~
....
01-
~1
~
~ GND
4-299
Notes
4·300
32·Bit CRC (Cyclical
Redundancy Checking)
Error Detection
PAL20X10
VCC
ClK
CHEcK
024
C
Q2s
026
027
Q23
NC
NC
NC
CHK1
(ffi
CHK2
OuT
DC
PAL20X8
PAL20X8
PAL20X8
vcc
vcc
CHK2
CHK3
as
Q1s
Q17
031
NC
010"
Qii
Qfi
Q19
012
oro
013
em
NC
NC
NC
4·301
D
32·Bit CRC Error Detection
CYCLIC REDUNDANCY CHECK (CRC)
USING PALS
Programmable Array Logic D~vices Provide
Efficie"nt Implementation of ·PopularLocal·Network
Error" Checking' Protocol"
There is a growing interest in providing data communication
links to connect several processors and peripherals into one
local area network. One of the most popular networks is the
Ethernet. To insure reliable communications in the network an
efficient error detection scheme is required. The Ethernet
protocol specifies a 32-bitcycle.redundancy which must operate
at 10 Mbits/sec.·
.
.
divisiOn will generate a quotient. Q(x). and a remainder. R(x).
PIx) is prescaled to insure that the order of PIx) is greater than
the order of G(x) so that the remainder is always different than
the message itself.
The following application opens with a tutorial on .the CRC and
then shows a detailed implementation of the Ethernet CRG
using PAL. The use of fuse programmable devices allows easy
modification to accommodate other data commul1ications
protocols as well as other applications (CRC in disk drives. etc.).
that operate at-rates up·to 13,'Mbits/sec.
". x"P(x) = Q(x) G(x) + R(x)
Introduction
The growing number of high speed digital links and the need for·
reliable communication requir~s implementation of efficient
error detection schemes at rates of 10 Mbits/sec ,a,nd higher. A
32-bit CRC using PAls meets these requirements.
WhatlsCRe?
CRC is the acronym for Cyclid Redundancy Check, an error
detection technique Y1(id~ly .used. in serial communication sys~
tems from computer to computer or from computer to peripheral
devices. This technique operates on serial bits of information
treated as the coefficients of a binary polynomial. PIx), and
processes these bits inmodul0-2 arithmetic.
The basic coding conceptofthe'CRC .is to modify the polynomial. PIx). so that it is exactly divisible by a fixed pqlynomial.
G(x); the divisorG(x) is referredto.as the generator polYromial.
The modified polynomial,.M(x), is.transmitted. M(x) is divided by
the same G (x) when received or fetched. If the remain?er is zero,
all bits are assumed to. be correct;; otnerwise. a flag is set tei
indicate an error.
..."
.
An Example UsingCRC
Specifically. PIx) is p.rescal~d by x" where n is the degree of
Six).
(1)
For a !3-bitCRC.lmd'G(x}=x' + 1 eqOation(1) becomes:
,- ....
.
-.
',
The operation is petformed using modulO-2 arithmetic where
the sum and difference are synonymous.
Equation 1 can equivalently be written as:
x" PIx) - R(x) = x" P(:l<)
+ R(x) = Q(x) G(x) = M(x)
M(X) is exactly dilrisibleby G(x) al'1d ifis M(x) that is transmitt.ed.
.nle messag,e.M(X) isfqrmEild by adding the remaining bits. R'(x)/
of a fixed 'Iengthn' to the message' bits. Because the· message'
was prescaled, addition is equivalent to appending the remainder at the end of the data bits. Forthe example given (remembering that LSB is sent first) the information transmitted is: 011
101110. Three redundancy bits are appended to facilitate error
detection.
In conclusion when performing cRe, the tr&nsmitter will generate and append R(x) while the receiver. Will verify the exact
division of M(x) by G(x) and signal the occurrence of an error.
WhyCftC?·
Compared to other error detection schemes such as parity
checking CRC is more powerful:
A 6-bit messaget101110) can be represented in pOlynomial forr"(f.
as:
PIx) = 1 + 0 x :+; 1 x' + 1 x' + 1 x 4 +'0 x·
or
PIx) = x· + x'. +'x 2 ..+ 1
'•. all errors within n successive bits are detected
The highest power of x.i~ attached to. the least significant bit
(LSB). The LSBis the'firs! bit transmitted in communication
channels. In general PIx) will not be exactly divisible by G (x); the
CRC is also more efficient (for large frame of information).
Efficiency is defined as the number of data bits divided by the
. total number of bits transmitted. For example: in the Ethernet
•
~or ~ven G(x) all errors With an odd numb~rof~bits in error are
'detected (50% of all possible random errors)
• all e.rror patterns thatate not divisible by G(x) are detected
32·Bit CRC Error Detection
specification the number of data bits ranges from 60 to 1500
bytes, the total number of bits transmitted will contain only an
extra 32-bits (if 32-bit CRC is used) instead of an extra 60to 1500
parity bits (if we assume one parity bit per byte of information is
used.)
Implementation
A binary division that ignores the quotient but retains the
remainder, R(x), is conventionally implemented with a shift
register. A feedback path from the output of the last stage
returns to the input of the stages corresponding to the powers of
x that have non zero coefficient in the generating polynomial. At
each such input, amodul0-2adder (Exclusive OR) combines the
feedback signal with the output from the previous stage.
This is equivalent to a shift subtract on each clock cycle. The
example in Fig. 1 shows a 32-bilCRC where G(x), the generator
polynomial, (used in ETHERNET and AUTOBAUD II) is given
by:
G(x) = x" + X'6 + x23 + X22 + X'6 + X12 + X" + x ' O +
x· + x' + )(, + X4 + x' + x + 1
Transmitter operation:
1. Initialize shift register to all Hs. (INIT = H)
2. Data is shifted in the feedback shift register to generate R(x)
and fed to the output. (Control C = H)
If the two R(x) match, the final content of the shift register is:
X31
XO
11000111000001001101110101111011
(residue)
4)
This value is tested. (Check = L indicates no error, as
shown in Fig. 2)
The same hardware can perform both the transmitter and
receiver function if the respective inputs are multiplexed.
PAL Configuration
Four PALs are used to implement the 32-bit CRC .. This configuration can process serial streams of data at rates of 10
Mbits/sec. The PAL interconnections are shown in Fig. 2. Eight
bits of the 32-bit shift register are distributed in eacH PAL. The
logic to check for the residue is distributed among the four PALs
as shown in Fig. 3.
Summary
The lack of standardization in data communication equipment
makes the use of PALs very attractive due to their flexibility and
ease of design modification. A good example is this 32-bit CRC
which achieves the speed requirements of 13 Mbits/sec while
being cost effective.
3. After last data bit has been processed, the complimented
R(x) is shifted out fortransmission. (Control C = L)
Receiver operation:
1. Initialize shift register to all Hs.
2. Data is shifted in the feedback shift register to regenerate
R(x).
REFERENCES
3. After last data bit has been processed, Control remains High
and the complement of R(x) is shifted (as generated by
transmitter).
The Ethernet, A Local Area Network, Data Link Layer and
Physical Layer Specifications,version 1.0 (joint publication of
Digital Equipment Corp., Intel Corp., and Xerox Corp., 1980).
4·303
32-Bit CAC Error Detection
fCRCt--------:-:--,----------r------------:----..,--,--·-,- CRc"%l
I ~IT
I
I
I
I
I
I
I
I
I
------------------jI
I
I
I
•I
I
~R~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
@
~OR
e
~XOR
III ~(INe031)' C 'INIT" IN' 031' C· INIT + iN· 031' C·
e
o
J _______________
I
I
~_CRC4J
iNiT
~AND
~NOT
Bn
CK
CLKr-- ~
~
INIT
C
IN
CHKl
-
Q26
~
CRC4~
PAL Q29
U~20Xl0~
031
t--
CRC1
PAL
>- ...
n
.......--
Lr031
031
CLK
INIT
C
IN
t--
CRC2
PAL
2QX8
---LrCRC3
PAL
20X8
----
f-~15
031
~~.
f!'!.
""""'-
I'I!!""
~C1--------~~------l
I
I
I
I
I
I
00
~;
03
04
CHK1
05
06
07
I
I
I
I
I 024'
I O~
1026
I 0",.27::..-_-'1
I
I
I
I
I
1 0 2 8
IcAcz-------- -1
I
I
I
I
I
I
I
Q29
~:
1030
010
1031
011
012
013
CHK2
~
I
I
~-I
i
J!I
I
I
I
I
I
I
I
~C3~-------1
I
I
I
I
I
I
I
IL
014
015
I
I
017
018
019
020
~~
023
CHK3
!
I
I
I _______
_________~
I
I
I
I
I
I
I
I
~
a• •It. ··CRe :Error DeteCtioni
PAL20XS
PAL DESIGN SPECIFICATION
CRCl
NADIA SACHS OS/14/S1
32-SIT CRe (CYCLICAL REOONDANCY CBECiING):J!:RROR DETECT.!ON, CHIP 1
MMI SUNNYVALE, CALIFORNIA
CLK INIT C IN /031 NC NC NC NC NC NC GND
/OC NC /07 /06 /05 /04 /03 /02 /01 /QO/cmuvcc'
32-Blt CRCBrrorlJetectlon
PONC'l'lON TABLE
eLK /OC INlT C IN 031 07 Q6 05. Q4 03 02 01 go ··ClIKl
,
,CLK
/OC
1NIT
C
1N
0
3
1
'''''.'
QQQQQQQQ.
76543210
em
.~----~------~-----~-------~-------------~-----H
x x x . 8".8,,8,18'8· :-., X
.C
L
L
C
a L B XoBLLBLLB X
~
X
L
LLBLLSLB
B
L
B
L
e
B
L
B
BHBHHHI,B
X
C
L
L
X
B
C
L
L
L
B
LBLLBBr.B
B
B
L
C
L
LLBLBBLB
X
L
X
B
e
L
L
B
L
BBBLBBLB
BBLBBLBt./;
e
L
L
B
L
X
L
e
L
B
X
L
L
L
BLBBLBLL
B
LBRr,BLLL
X
L
L
L
L
C
B
B L
x
L
C
L
LBBLLHBB
X
C
L
L
B
L
L
BBLLBBBL
B
L
X
L
C
L
L
BLLBBBLL
L
L
B
X
L
e
BIoIoI·S HHB.
B
L
B
L
L
B
C
BLBLBLLB
X
QBLLBLB
B
C
L
B
X
L
L
B
L
B
L
LBBBBBLB
X
C
L
BBBBIJl:jSr,
X
L
L
B
C
L
L
B
C
L
L
X
L
BH8BLBLL
L
B
BBBLBLLL
X
L
L
L
C
L
C
B
L
L
X
L
BBLBLLLL
L
L
L
L
L
C
B
BLBLLLLL
X
B
LBIoI,IoI.LL
C
L
L
L
X
L
L
B
L
L
L
X
C
BLLLLLLL
LLLLLLLL
X
L
L
L
L
e
If
BLBBLBBB· . X
B
L
C
L
B
L
x
B
C
L
L
L
L
LBBLBBBL
L
B
L
B
C
L
LBBLBLBB
X
C
L
B
B
X
L
L
LBBLLLLB
L
L
B
L
BBLLLLBL
L
e
X
C
L
B
X
L
L
B
LLBBLLBB.
B
L
L
L
LBBLLBBL
L
X
C
H
C
L
H
X
L
LaBBBLBB
L
C
X
H
X
X
L
X
XXXXXXXX'
-----------------------------------~~-~--~-----DBSClUPT10N
1!'1RST a-B1T SHUT RPlG1STBR AND CHECK.
32-8it CRC Error Detection
32-BIT CRC (CYCLICAL REDUNDANCY CHECKING) ERROR DE'l'ECTION, CHIP 1
1C1XXXXXXXXXXOXLLLLLLLLX1
2 C0100XXXXXXXOXBLBHLHHLXl
3 C0100XXXXXXXOXBHLHHLRLXl
4 coiOOXXXXXXXOXLLLLLLHLXl
5 C0100XXXXXXXOXBLBBLLHLXl
6 C0100XXXXXXXOXBHLHLLHLXl
7 C0100xXXXXXXOXLLLHLLHLXl
8 C0101XXXXXXXOXLLHLLHLBXl
9 C0101XXXXXXXOXLHLLHLHHXl
10 C0101XXXXXXXOXHLLHLHHHXl
11 C0100XXXXXXXOXHLLHHLLLXl
12 C0101XXXXXXXOXLLBBLLLHX1
13 C0101XXXXXXXOXLBHLLLHHXl
14 C0100XXXXXXXOXLSBHLLLLXl
15 C0100XXXXXXXOXLBLHLHHLXl
16 C0100XXXXXXXOXLLLHHLHLXl
17 C0100 XXXXXXXOXBLLLLLHLXl
18 C0101XXXXXXXOXLtoLLLHLHXl
19 C0101XXXXXXXOXLLLLBLHHXl
20C010IXXXXXXXOXLLLBLBBHXl
21 C0101XXXXXXXOXLLBLHIJHHXl
22 C0101XXXXXXXOXLBLHBHlmX1
23 C0101XXXXXXXOXBLBB8BBHXl
24 C010UCXxxXXXOXLBBBBBHBXl
25 C010IXXXXXXXOXBHHHHHHHXl
26 C0100 XXXXXXXOXLHLLBLLtXl
27 C0101XXXXXXXOXHLLHLLLHXl
28 C0100 XXXXXXXOXHLLHLHLLXl
'29 c0100 XXXXXXXOXHLLHHHHLXl
30 C0101XXXXXXXOXLLHHHHLBXl
31 C0100XXXXXXXOXBHLLHHLLXl
32 C010IXXXXXXXOXHLLHHLLHX1
33 C0100XKXXXXXOXBLLLLBLLXl
34 CXXXXXXXXXXXOXXXXXXXXXLl
J
PASS SIMVLATION
4-307
32-BlteRe, Error Detection
32-BIT CRC (CYCLICAL REOONDANCYcaEC!KINGF'i!lRROR Di!:~TI<»J, CHIP-1
11 1111 1111 2222 222~ 2233 3,3333333
0123 4567 8901 2345 6789 0123 4567 8901 234~ 6789
o
---x ---x --x- ---x ---x ---x ---x --x-
1
8
9
10
11
16
17
18
19
24
25
26
27
-x-- x--- x---x- x--- x---x-x--x--
/INIT*IN*C
/INIT*IN*C
Q31*C
INIT
-x- x--- x--- x---x-- x--- -x-- -x----x
x---x- x- x--- x---x-- x--- -x-- -x-:-
/INIT*C*IN*/Q31
/INIT*O* /IN*Q31 -INIT
/'INIT*C*IN*/Q31
/INIT*C*/IN*Q31
-,..-- Q1
INIT
---x
x-.,.
40
41
42
43
-x- x--- -x-- -x--
Q2
INIT
-x-- X--- X--- x-x---
48 -x49 -x-50 --51 x--.,..
64
65
66
67
CO
---x
x---
32
33
56
57
co *Q1 */Q2*Q3 *04 *Q5 *06 */-
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q3
.
mIT
---x
x--- x--- x---
x--- -x-- -x--
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
04
INIT
---x
---x
x---
-x-- x--- x--- x---x-- x--- -x-- -x-.,.-...-
---x
x--- ---- ---_ ---X: FUSE NOT BLOWN (L, ~, 0)
LEG$ND:
NUMBER
OF
FUSES BLOW = 1129
- : FUSE BLOWN
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
06
INIT
(H,P,l)
32·Bit CRC Error Detection
Logie Diagram PAL20X 8
32·Bit CRC, Chip 1
ClK
1
....
~O123
,
4
~
6
1
8
9 1011
1'2131415
16171819
20212221
24252621
182930]1
32333435
36 n lIl9
,
,
- ~
,
INIT
~
~
.,
3
;:::::::: .
R-1~D-
"
"
"
-b-L
"
4
~
IDD-~
"
"
"
"
;i9t>
--
"
031
NC
5_
6
7
--t~
..
"
8
~
...... ..-.
"
"
"
I~Lj
9
.~. ~ lfi;
.
~D-
"
"
"
NC
=1:):1.
10
11
17
04
05
~ 06
I.:J.......
15
07
Q
~
"'"
te(,
....L
-'6t,..r-v
"
"
"
"
NC
~
01
~
......
-t:5--L
""'.-..~D-
56
NC
~
5--L
00
~
02
......
~
"
NC
~
~
IDD~
IDD- ~
"
"
"
"
NC
22
......
~
"
"
"
CHK1
I
Il
"
IN
23
~D~R
-
"
C
......
v
.A.
>
14
NC
13
OC
~
(I
1
2 1
4 S "
. , 1011
121314 IS
1& 11 1119
20212223
24251521
U 2t 10 31
31 33 34
n
li 313139
4-309
32-Bit CRC Error Detection
PAL20xS
PAL DESIGN SPECIFICATION
CRC2
NADIA SACHS OS/14/S1
32-BIT CRC (CYCLICAL REDUNDANCY CBECKJ;NG) ERROR DETECTION, CHIP 2
MMI SUNNYVALE, CALIFORNIA
CLK INIT C IN /Q7 /Q31 NC NC NC NC NC GND
/OC NC /Q1S /Q14 /Q13 /Q12 /Q11 /Q10 /Q9 /Q8 /CHK2 vec
CHK2 =
Q8
Q8*/Q9* Q10* Ql1* Q12*/Q13* Q14* QIS
/INIT* C*IN* /Q31
/INIT* C*/IN* Q31
:+: Q7
INIT
+
:=!=
+
Q9
:=
+
QI0 :=
+
:+:
+
QS
INIT
/INIT* C* IN*/Q31
/INIT* C*/IN* Q31
Q9
INIT
/INIT* C* IN* /Q31
/INIT* C*/IN* Q31
:+: QI0
INIT
+
Ql1 :-
+
Q12 :=
/INIT* C* IN* /Q31
+ /INIT* C*/IN*Q31
:+: Qll
INIT
+
Q13
:=
+
Q14 :=
+
QIS :=
+
;CHECK BIT 2
;MODULO-2
; ADDITION
; SHIFT
; INITIALIZE
; SHIFT
; INITIALIZE
;MODULo-2
; ADDITION
;SBIFT
; INITIALIZE
;MODULo-2
; ADDITION
;SBIFT
; INITIALIZE
;MODULo-2
; ADDITION
;SBIFT
; INITIALIZE
Q12
INIT'
; SHIFT
; INITIALIZE
Q13
INIT
;SBIFT
; INITIALIZE
Q14
INIT
;SBIFT
; INITIALIZE
3.2-8"· CRCError Detection
I'ONCl'ION TABLE
ctK
J
,CLK
ICC
INIT C IN Q7 Q31 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 cBK2
ICC
INtT
C
Q
QQQQQQQQ
Q
3
IN
7
1
111111
54321098
L
B
L
L
B
L
L
B
B
B
B
B
B
CBK2
-----------------------------------------------------B
X
BBBBSBBS
X
L
X
X
X
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
c
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L.
L
L
L
L
L
L
L
L
L
L
L
B
B
B
B
B
B
B
II
B
L
L
L
L
L
L
L
L
L
L
B
L
L
L
L
B
L
B
L
B
L
B
L
B
L
L
L
L
L
B
B
L
L
B
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
B
B
B
B
B
B
B
B
B
C
C
C
C
L
C
L
C
L
L
L
L
L
L
L
t..
L
B
L
L
L
X
H
C
C
C
C
L
t.
B
B
B
11
B
B
X
L
L
L
L
L
L
L
L
L
L
L
X
B
B
L
L
B
B
B
B
B
B
B
L
B
L
B
L
L
L
B
L
L
X
B
L
L
L
B
t.
L
B
B
B
B
BBBLLLBL
BBLBBLLB
BLSI.BSSB
LBI.I.I.I.BL
BLLBBLLB
LLBLBBBB
LBLBBBBB
BLBBBJDm
LBBBBBBB
BBBLLLBB
BBLLLBBL
BLLLBBLB
LLLLLBBL
LLLBLLLL
LLBBBBLL
LBBLLBLL
L
L
L
L
L
L
L
L
B
L
B
B
L
B
L
B
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D
X
BLT.T.AAAA
X
LLBIDQDIL
x
x
LBBBBBL~
X
BBBLLBBB
BBLLBBBB
BLLLLLBB
LLLBBLBB
LLBBLBBL
LBBBLLLL
BBBLLLLL
BBLBBBLB
X
X
X
X
X
X
LLLBJJBBB
xxxxxxxx
X
X
B
-----------------------------------------.-------.•._-
.-~1"
·32·BitCRC Error Detection
DESCRIPTION
SECOND a-BIT SHIFT REGISTER AND CHECK.
32-81t CRe Error Detection
32-BIT CRC (CYCLICAL REDUNDANCYCBECKING) ERROR DETECTION, CHIP 2
1
2
3
4
S
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2S
26
27
28
29
30
31
32
33
34
C1XXXXXXXXXXOXLLLLLLLLXl
C01000XXXXXXOXLLLHHHLHBl
C01010XXXXXXOXLLHLLHHLHl
C01010XXXXXXOXLHLHLLLLX1
C01000XXXXXXOXHLHHHHLHXl
C01010XXXXXXOXLHHLLHHLXl
C01010XXXXXXOXHHLHLLLLXl
C01001XXXXXXOXHLHLLLLLXl
C01001XXXXXXOXLHLLLLLLXl
C01001XXXXXXOXHLLLLLLLXl
C01010XXXXXXOXLLLHHHLLXl
C01011XXXXXXOXLLHHHLLHXl
C01001XXXXXXOXLHHHLLHLXl
C01000XXXXXXOXHHHHHt.I.8Xl
C01000XXXXXXOXHHHLHHHHXl
C01000XXXXXXQXHBLLLLHHXl
C01000XXXXXXOXBLLHHLHHXl
C01011XXXXXXOXLLHHLHHRXl
C01001XXXXXXOXLHHLHHHLXl
C01001XXXXXXOXHHLHBBLLXl
C01001XXXXXXOXHLHHHLLLXl
C01001XXXXXXOXLHHHLLLLXl
C01001XXXXXXOXBlrm:'LLLLXl
C01011XXXXXXOXHHTJ.r.T.T.HXl
C01001XXXXXXOXHLLLLLHLXl
C01010XXXXXXOXLLLHHLLLXl
C01001XXXXXXOXLLHHLLLLXl
C01010XXXXXXOXLHHHHHLLXl
C01010XXXXXXOXHHHLLHLLX1
C01011XXXXXXOXHHLLHLLHXl
C01000XXXXXXOXHLLLHHHHXl
C01011XXXXXXOXLLLHHHHHXl
C01010XXXXXXOXLLHLLLHLXl
CXXXXXXXXXXXOXXXXXXXXXL1
PASS SIMULATION
4-313
32-Blt CAC Error Detection
32-BIT eRC (CYCLICAL REDUNDANCY CHECKING) ERROR DETECTION, CHlP2
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
0
1
11
--x --x- ---x ---x ---x --x- ---x ---x ---x---x-- x-.;.- x---x--x-- x--- -x--x-x---
16
17
x---
24
25
26
27
x--x- x-- x---x--x-- x--- -x----x ---x---
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q9
INIT
32
33
34
35
-x- x-- x---x-- x--- -x--
x---x----x ---
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q10
INIT
40
42
43
-x-- x-- x---x-- x--- -x-x---
x--x----x
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q11
INIT
48
49
x---
56
57
x---
64
65
x---
8
9
10
41
--x
x---
LEGEND:
Q8*/Q9*Q10*Q11*Q12*/Q13/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q7
INIT
Q8
INIT
---x
Q12
INIT
---x
Q13
INIT
---x ----
----'----
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW"
984
- : FUSE BLOWN
Q14
INIT
(H,P,l)
32 .. Blt CAC Error Detection
Logic Diagram PAL20X 8
32·Bit CAC, Chip 2
ClK 1
.,
012
J
. 5.'
1
8 ! 1011
12131415
16
n "'9
21212223
24252&21
21 ZllO 11
12133415
161111:n
,
,
IN IT 2
~
,
.
~=9~ ll] ~
-...
CHK2
Q8
~
"
"
"
4
"
"
"
"
5
IDD
-O-L
~
"
"
"
6
Q10
'Q
..
....-.;;
',";"';
.............
J~D
t;
~D :t;
"
.,"
-H-L
7
...
'
...
so
"
.
'Q
~
'"-;:J.
17
....
Q12
Q13
,
.
tl-L9
............ D
ll]~
Q14
IDD:f; I.J..
Q15
r--. .......
"
~
Ie{
59
NC 9
,"
,
20
,'''-
~
8
:f;
I.J..
......
Q9
~,
....
:~D
~
'32
NC
~J
.',
......
II
NC
23
ID~
- ~~
C .L
Q7
.rt>
~
""
IN
......
.."
15
i ....
"
NC ~~
-
"
""
-
J6l
"
.J.
./
.A..
NC ~~
I
1 ,1 3
..
5
Ii. 1
I
t
10 11
12 1l1~ 15
"
11 tt "
I
2021 U 23
~
24 25 ZIi 11
ZI Z' ,. 31
n
13:M lS
H
n
14
Ne
13'
OC
......
lilt
4·3,15
32-Bit CRC Error Detection
PAL DESIGN SPECIFICATION
PAL20X8
NADIA SACHS 08/14/81
CRC3
32-BIT CRC (CYCLICAL REDUNDANCY CHECKING) ERROR DETECTION CHIP 3
MMI SUNNYVALE, CALIFORNIA
CLK INIT C IN /Q15 /Q31 NC NC NC NC NC GND
/OC NC /Q23 /Q22 /Q21 /Q20 /Q19 /Q18 /Q17 /Q16 /CRK3 vec
CBK3
..
Q16
:=
/Q16*/Q17* Q18*/Q19*/Q20*/Q21*/Q22*/Q23
;CHECK BIT 3
/INIT* C* IN*/Q31
;MODULo-2
;ADDITION
; SHIFT
; INITIALIZE
+ /INIT* C*/IN* Q31
:+: Q15
INIT
+
Q17
:=
+
Q18
:=-
+
Q19
:=
+
Q20
:=
+
Q21
:+
Q22
:=
Q16
INIT
; SHIFT
; INITIALIZE
Q17
INIT
; SHIFT
; INITIALIZE
Q18
INIT
, SHIFT
; INITIALIZE
Q19
INIT
; SHIFT
; INITIALIZE
Q20
INIT
; SHIFT
; INITIALIZE
/INIT* C* IN*/Q31
+ /INIT* C*/IN* Q31
:+: Q21
+
INIT
Q23
:=
/INIT* C* IN* /Q31
+ /INIT* C*/IN* Q31
:+: Q22
+
INIT
4-316
;MODULo-2
; ADDITION
; SHIFT
; INITIALIZE
;MODULo-2
; ADDITION
; SHIFT
; INITIALIZE
32·Bit CRC Er.ror Detection
FUNCTION TABLE
CLKjOC INIT C IN Q15 Q31 Q23 Q22 Q21 Q20 Q19 Q18 Q17 Q16 CHK3
;CLK
JOC
INIT
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C
IN
Q
1
5
Q
3
1
QQQQQQQQ
22221111
32109876
BHHHHHlm
LLBHHHHL
HLHHHHLL
HLBHHLLL
HLHHLLLL
HLHLLLLH
HLLLLLHL
LI,I,I,I,HLL
LLLLHLLL
LLLHLLLH
HHHLLLHH
HHLLLBHH
CHK3
-----------------------------------------------------
X
X
X
X
x
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
H
L
H
H
H
L
L
L
L
H
H
L
L
H
L
L
L
H
H
H
L
L
L
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
L
H
L
H
HHLHHHHL
LBHHHHLH
LLHHHLHH
HLHHLHHH
LBHLHHHL
HHLHHHLH
HLHHHLHH
LHHHLHHL
HHHLHHLL
HHLHHLLH
HLHHLLHL
LHHLLHLL
LLLLHLLH
LLLHLLHH
HHHLLHHL
LLLLHHLL
LLLHHLLL
HHHHLLLH
RHHLLLHL
LLLLLHLL
X
X
X
X
XXXXXXXX
~
H
H
H
H
H
H
H
H
H
H
H
H
H
H
R
HLLLHHHH
x
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
x
X
X
X
0
x
X
X
X
X
X
X
X
X
X
X
X
H
----------------------------------------------------
.';!U7
,
32-Bit CRC Error Detection
DESCRIPTION
THIRD a-BIT SHIFT REGISTER AND CHECk.
32-Bit CRC Error Detection
32-BIT CRC (CYCLICAL REDUNDANCY CHECKING) ERROR DETECTION CHIP 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ClXXXXXXXXXXOXLLLLLLLLXl
COlOOOXXXXXXOXHHLLLLLHHl
COlOOOXX~XXXOXLHtLLLHHHl
COlOOOXXXXXXOXLHLLLHHHXl
COlOOOXXXXXXOXLHLLHHPHX1
C01010XXXXXXOXLHLHHHHLXl
COlOOOXXXXXXOXLHHHHHLHX1
COlOllXXXxxxOXHHHHHLHHXl
COlOllXXXXXXOXHHHHLHHHXl
c0100ixxxxxxoximin.Bmn.Xl
C01010XXXXXXOXLLLHHHLLXl
C01001XXXXXXOXLLHHHLLLXl
COl001XXXXXXOXL~LXl
C01000XXXXXXOXLLHLLLLHX1
C01010XXXXXXOXHLLLLLHLXl
C01010XXXXXXOXHHLLLHLLXl
C01010XXXXXXOXLHLLHLLLXl
C01011XXXXXXOXHLI.HLLLHX1
C01001XXXXXXOXLLHLLLHLXl
C01001XXXXXXOXLHLLLHLLXl
C01011XXXXXXOXHLLLHLLHX1
C01011XXXXXXOXLLLHLLHHXl
C01001XXXXXXOXLLHLLHHLXl
C01011XXXXXXOXLHLLHHLHXl
C01011XXXXXXOXHLLHHLHHXl
COl010 XXXXXXOXHHHHLHHLXl
COl001XXXXXXOXHHHLHHLLXl
C01000XXXXXXOXLLLHHLLHXl
C01000XXXXXXOXHHHHLLHHXl
C01011XXXXXXOXHHHLLHHHXl
C01010XXXXXXOXLLLLHHHLXl
COl011XXXXXXOXLLLHHHLHX1
C01000XXXXXXOXHHHHHLHHXl
CXXXXXXXXXXXOXXXXXXXXXL1
PASS SIMULATION
4-319
32·81t CRC. Error Detection
32-BIT CRe (CYCLICAL REDUNDANCY CBI!lCKING) ERROR DETECTION 'CHIP 3
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
0
1
8
9
10
11
16
17
24
25
32
33
40
41
48
49
56
57
58
59
64
65
66
67
-x- ....x- ---x.--x- --x- --x- --x- --x-x- x--- x--- _._- x--x-x- x--.;. -x--x-x--x
x-----x
x----...x
x----x
x-x---x--xx---x--x-x---
LEGEND:
x--x--
x--·x--x-- -x-
x--x--
016
tNIT
017.
tNIT
----
018
INIT
Q19
INIT
--,-- 020
INIT
912
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q21
INIT
---x
X : FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW.
4.320
/INIT*C*IN*/031
/tNIT*C*/IN*031
015
tNIT
----
---x
x--- x--x-- -x-
/016*/017*018*/019*/020-
/INIT*C*IN*/031
/INIT*C*/IN*Q31
022
INIT
---x
FUSE BLOWN
(H,P,l)
32-Blt. CRC Error Detection
Logic Diagram PAL20X 8
32-Blt CRC, Chip 3
.....
ClK 1
V.
,2l
.5' I
191011
N 111415
i817UI9
282122 U
24252627
28293031
3233:M35
3&31313 •
0
,
,
......
J
,
J
....,.
INIT ~
..
...... -J:j-~D......~~~
"
-t:}-L
"
C
3
"
"
"
4
...
...
.,"
.
s.
:
I.'
;"
",i
.,
.."
<
~
...
.'....
.,~
"
'.
..
.
'.
:..
",
-~D-
.{:S-;L
m,..
••
~
Ie(
Sf
...
.
~
~
'--
.
21
~2a
L....
'
"
~
'"J. ',.
~
~
11
~
R......
16
.J
.....
18
Qji •.
Q21
.
~g;D-
.
."
~C>~ ~
"
-
If
~
"
NC ~
"
"
"
"
NC
I
Je(.
ft;
"
~=OD...,
;"4,i'
NC .~
"
--
;'
R....
.;
IfKI
:.0-
NC
- ~
~I5
•
fGll
-~I>
....~:::..
I"
6.
031 4.
NC
~I>
:::::.
"
IN
23
lA(
.....
11
'
> .J. .
-
CI-----'
D 1 2 3
"S, 7
. , " 11
12 13 14 IS
" 11 " "
21 21 U U
24 15 21 21
1I zt 31 31
It 13 14 J5
3. 31 H B
14
...q...-E
NC
32-81t CRC Error Detection
PAL20XlO
PAL DESIGN SPECIFICATION
CRC4
NADIA SACHS 08/14/81
32~BIT CRC(cYCLICAL .REDUNDANCY CHECKING) ERROR DETECTION, CHIP 4
MMI SUNNYVALE, CALIFORNIA
CLK INIT C IN /Q23 NC NC NC /CHkl /CBK2 /CHK3 GND
/oe /OUT /Q31 /Q30 /Q29 ·/Q28 /Q27 /Q26 /Q25 /Q24 /CBECK vec
Cmx::K:-
CBK1* CBK2* CBK3* Q24* Q25* Q26*/Q27*/Q28*/Q29* Q30* Q31,CBECK ERROR
Q24
Q23
INIT
,SHIFT
, INITIALIZE
Q24
INIT
,SHIFT
,INITIALIZE
:-
+
Q25
;
..
+
Q26
:=
Q27
:-
/INIT* C* IN*/Q31
+ /INIT* C*/IN* Q31
:+: Q25
+ INIT
+
Q28
:-
+
Q29
:-
+
Q30
:'"
+
Q31
:-
+
OUT
4-322
Q26
INIT
,SHIFT
,INITIALIZE
Q27
INIT
,SRIFT
,INITIALIZE
Q28
INIT
,SHIFT
,INITIALIZE
Q29
INIT
,SHIFT
,INITIALIZE
Q30
INIT
,SHIFT
,INITIALIZE
Q31*/C
+ /IN* C
:-
,MODULo-2
,ADDITION
,SHIFT
,INITIALIZE
,SERIAL
:00'1'
32-Bit CAC Error Detection
FUNCTION TABLE
CLKjOC INIT C IN cmu CBK2 CHK3 Q23 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 OUT CHECK
JCLK
joe
INIT
C
IN
CBK
123
Q
2
3
QQQQQQQQ
33222222
10987654
OUT
CHECK
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-------------------------------------------------------.-----BHHHARAH
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X
H
L
L
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
S
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
H
L
H
L
L
L
L
L
Ii L
L
L
H
L
i:.
L
H
L
L
L
S
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
X
X
X
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _N
xxx
xxx
X
xxx
H
L
H
H
H
H
H
L
L
L
H
XXX
H
XXX
xxx
XXX
XXX
xxx
XXX
xxx
xxx
XXX
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
H
H
L
L
H
L
H
H
L
H
H
H
L
L
L
H
L
L
H
H
HHHHHLHH
HHHHLLHL
HHHLLLLH
HHLLLHHH
HLLLHLHH
LLLHLLHH
LLHLLHHH
LHLLHHHL
HLLHHHLL
LLHHHHLL
LHHHHLLH
HHHHLLHH
HHHLLLHH
HHLLLLHH
HLLLLLHL
LLLLLLLL
LLLLLLLH
LLLLLLBL
LLLLLm.H
LLLLHLBH
LLLHLHHL
LLHLHHLH
LHLHHLHH
HLHHLHHH.
LHHLHLHL
HHLHLHLL
HLHLHHLL
LHLHHHLH
HLHHHLHL
LHHHLLLL
HHHLLLLH
HHLLLHHH
x
x
D
X
X
X
X
XXX
X
X
XXX
K
X
XXX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
HHH
____________________________________
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xXx
xxxxxxxx
4-323
32·Bit CRC Error Detection
DESCRIPTION
FOURTH 8-BIT SHIFT REGISTER, CHECK, AND SERIAL OUT.
NOTE THAT A PAL20Xa CAN BE USED FOR THE CRC4 IF THE IMPLEMENTATION DOES
NOT REQUIRE OUT AND CHECK TO BE REGISTERED OUTPUTS.
4·324
32-Bit'CRCError Detection··
32-BIT CRC (CYCLICAL REDUNDANCY CHECKING) ERROR DETECTION, CHIP 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C1XOXXXXXXXXOXLLLLLLLLXl
C0100XXXXXXXOXLLLLLHLLXl
C0101XXXXXXXOXLLLLHHLHX1
C0100XXXXXXXOXLLLHHHHLXl
C0100XXXXXXXOXLLHHHLLLXl
C0100 XXXXXXXOXLHHHLHLLXl
C0100 XXXXXXXOXHHHLHHLLXl
C0100 XXXXXXXOXHHLHHLLLXl
C0101XXXXXXXOXHLHHLLLHXl
C0101XXXXXXXOXLHHLLLHHXl
C0101XXXXXXXOXHHIJ.I.LHHXl
C0100XXXXXXXOXHLLLLHHLXl
C0100XXXXXXXOXLLLLHHLLXl
C0100XXXXXXXOXLLLHHHLLXl
C0100XXXXXXXOXLLHHHHLLXl
COI0IXXXXXXXOXI.HHHHHI.8Xl
COI0IXXXXXXXOXBHHBHBBBXl
COI00XXXXXXXOXHHHHHHHLXl
COI0IXXXXXXXOXHHHHHHLHXl
COI00XXXXXXXOXHHHHHI.BLXl
COI00XXXXXXXOXHHHBLHLLXl
C0101XXXXXXXOXHHHLHLLHXl
COI00XXXXXXXOXHHLHLLHLXl
COI00XXXXXXXOXHLHLLHLLXl
COI00XXXXXXXOXLHLLHLLLXl
COI0IXXXXXXXOXHLLHLHLHXl
C0101XXXXXXXOXLLBLHLHHXl
C0101XXXXXXXOXLHLHLLHHXl
COI00XXXXXXXOXHLHLLLHLXl
C0101XXXXXXXOXLHLLLHLHXl
C0101XXXXXXXOXHLLLHHHHXl
COlO O.,XXXXXXXO XLLLHHHHLXl.
COI00XXXXXXXOXLLHHHLLLXl
CXXXXXXXOOOXOXXXXXXXXXLI
PASS SIMULATION
32·Bit CRC Error Detection
32-BIT CRC (CYCLICAL REDUNDANCY CHECKING) ERROR DETECTION, CHIP 4
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
o ---- ---x ---x ---x --x- --x- --x- -x-x -x-x -x-8 ---- ---- ---9 x--- ---- ---16 ---17 x---
-x-- ---- ---- ---- ---- ---- ------- ---- ---- ---- ---- ---- ----
---x ---- ---- ---- ---- ---- ---- ------- ---- ---- ---- ---- ---- ---- ----
24 -x-- x--25 -x-- x--26 ---- ---27 x--- ----
x--- ---- ---- ---- ---- ---- --x-x-- ~--- ---- ---- ---- ---- ---x ----
---x ---- ---- ---- ---- ---- ---- ----
---- ---- ---- ---- ---- ---- ---- ----
32 ---- ---- ---33 x--- ---- ----
/INIT*C*IN*/Q31
/INIT*C*/IN*Q31
Q25
INIT
Q26
INIT
---x ---- ---- ---- ---- ------- ---- ---- ---- ---- ----
Q27
INIT
---x ---- ---- ---- ------- ---- ---- ---- ----
Q28
INIT
---x ---- ---- ------- ---- ---- ----
Q29
INIT
---x ---- ------- ---- ----
Q30
INIT
56 ---- ---- ---- ---- ---- ---57 x--- ---- ---- ---- ---- ----
64 ---- ---- ---- ---- ---- ---- ---65 x--- ---- ---- ---- ---- ---- ----
-x-- ---- ---- ---- ---- ---- ---- ---x ---x--- -x-- ---- ---- ---- ---- ---- ---- ---X : FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
4·326
Q24
INIT
---- ---- ---- ---- ---- ---- ----
48 ---- ---- ---- ---- ---49 x--- ---- ---- ---- ----
LEGEND:
Q23
INIT
---x ---- ---- ---- ---- ---- ----
40 ---- ---- ---- ---41 x--- ---- ---- ----
72
73
CHK1*CHK2*CHK3*Q24*Q25*-
= 801
FUSE BLOWN
Q31*/C
/IN*C
(H,P,l)
32·Bit CRC Error Detection
Logic Diagram PAL20X10
32·Bit CRC, Chip 4
iCLK I ~
I'"
I
0123
·,
of
S. 1
1110.11
1213'415
",Jl"9.
nZlun
u»an
DaHl!
l23114U
llUlllt
~-
-~C> ~~
2
....
3
INIT
~
•
~-
"·
-ti~D-
-IA(
"
C
3
.....
..
"
-- fill
-
4
~
-t5~DR-J
"
"21
6
.
~~D-
"42
--
"
NC ~~
....
~~D-
"
~-
.
.
-~D-..... -
"
51
II
9
..
.....
-
~-9c>
u
"
~~
it
~
~
""J
.....
18
~
""J
V
17
~
""J.
.....
16
~.
r.J.V
15
~~~"""'--
"
""
"
:HK3
21
~-
32
11
tlV
~
""
"
NC
~
~
5
8
CHECK
t11
~
~!9Dt11
--
2S
NC
~
1fK-9D-
"
"
"
IN
-
...
..
Q
it
•
I
Z 3
..
5
•
1
•
t '111
121310115
' I n 1111
!iZI U 23
Z4 Ullin
21 II :Milt
111114 35
14,
V
13
If 31 lilt
4~327
Notes
4·328
a-Bit Error Detection
and Correction
VCC
eo
Bl
C3
C2
Ci
co
0
B2
B3
PAL16X4
PAL16L8
. PAL16L8
VCC
B1C
BOC
C3C
C1C
COC
ERROR
NC
,;'
8·Bit Error Detection and Correction
Single bit error detection and correction for an 8-bit data word
requires 4 check bits, making a 12-bit code word. The simplest
code to design is a 12-bit Hamming code. To arrive at the code,
we set up the following matrix:
B7 B6 B5 B4 B3 B2 B1
80
C3 C2 C1 CO
S3 X X X X
S2
X
X X X
X X
X X
X
X
X X
X X
X
S1
SO
Example
X
X
C3
C1
CO
The vertical columns are in a counting pattern, excluding
the single bit values of 8, 4, 2, 1. The single bit values are
assigned to the check bits C3-CO. By reading horizontally
across the rows of the matrix, we get the check equations
by exclusive OR'ing the data bits with X's in that row and
equating that to the check bit with an X in that row:
C3
B7$B6$85$B4
C2
B7 $
B3 $
B2 $ B1
C1
B6 $
B5 $
B3 $
B2 I3l BO
CO
B6 $
B4 $ B3 $
B1 $ BO
The check bits are stored along with the data bits in the
following message format:
M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1
B7
B6 B5
B4 C3
B3
B2
B1
C2
BO
C1
"
"
$
B7 $
B6 $ 85 $
B4 $ C3
B7 $
B3 $
B2 $
B1 $ C2
S1
SO
B6 $
B5 $
B6 I3l B4 $
B313l B2 $
B3 $
0
M12 Ml1 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1
1
1
1
0
0
1
1
1
1
1
1
0
B7 86 85 84 C3 83 B2 81 C2 80 C1 CO
EDAC System Block Diagram
ADDR
BUS
·DATA
aus
CHECK BIT
GENERATION
1-
-
64Kx4
CHECK
BIT
MEMORY
64Kx8
DATA
MEMORY
16
-
B1 I3l SO $ CO
TIMING
AND
CONTROL
I-
4
4
8
The Hamming code works by introducing enough other code
words to create a difference of exactly 3 bits between legal code
words. All other code words are illegal. If, in storage, one bit
flips, the result is an illegal word. In addition, there is only one
word in the set of legal code words from which it COuld have
come, hence the correction.
The Hamming matrix and resultant sets of check bit and
syndrome equations are selected so that when a single bit error
occurs, the syndrome gives the position of that bit (either data
or check) in the 12-bit message format.
CONTROL
BUS
4
t
The 4 syndrome bits indicate the location of any single bit errors
in the 12-bit message format which may than be corrected by
inversion.
4·330
0 $
$
message:
CO
BO $ C1
1
$
When a read occurs, the check bits are recalculated and
compared with the stored bits to generate the 4 bit syndrome:
S2
0
B7 $ B6 I3l 85 $ B4
1 I3l 1 I3l a $
B7 $ B3 I3l B2 $ B1
1 $ 1 I3l 1 I3l a
B6 I3l B5 $ B3 $ B2 I3l BO
1 $ a $ 1 $
$ 0
B6 $ B4 $ B3 $ B1 $ BO
8
S3
o
o
cheek bits:
C2
X
BO
B7
random data word:
SYNDROME
GENERATION
•1
ERROR
CORRECTION
8
t
CORRECTED
CHECK
I--
4
4_BIT
SYNDROME
FOR ERROR
LOGGING
ERROl!
a-Bit Error Detection and Correction
assume no error:
83
82
81
87
Syndrome Bit EqUations
86 ~ 85
~
84
~
C3
83= 87~86E1l85~ 84E1l C3
~
1
~
0
~
1 ES
1
87
~
B3
~
82
~
C2
1
~
1
1
ES
81 ~
0 ES
86 ES B5
~
83
~
82
~
80
~
Cl
~
ES
~
1
~
0
~
1
~
B4 ES 83
~
~
CO
~
E9
E9
1
86
80
~
0
0
~
= (87 '86 . 85 + 87 • 86' 85 + B7 . 86 • 85 + 87 • 86· 85)
Ell (84 •
1
81 ES BO
0
0
0
~
0
0
83
Q
~
E9
ES
1
~
1
Q
ei
E9
E9
0
E9
1
E9
E9
i
E9
0
E9
0
E9
E9
0
E9
0 E9
0
-b
>-b
1
3
B7
6
, ...
1
.
8
9
"
11
11
1l
B6
J
""
...
...
11
"
r;:,.
"
21
22
,
"
~""
21
-
3D
31
\
~31
J4
J5
.......
J6
J1
38
J9
-
"""
"
"""
r;:,.
6
47
NC
m
~
M
~D-fi~
4~
49
"
"
""
51
B4
~J),-
./
I
-Q."I
B5
~D- ~t..21 ~
.....-0
01--
~
J3
F
~
~D- r-r;;-;;~~
~~1
I-
28
29
NC
B1
,.....,
"
NC
18
BO
,.
16
18
NC
19
B
9
...
...
...
.
"
""
""
6D
61
62
6J
01234561891011
1213141516171119
202122232425262128293031
>-b
>-b
...
13
12
B2
B3
LA.!!
~
4-335
a..ait Er.....' Detectfon}andrCortection
PAL16X4
PAL DESIGN SPECIPICATION
SBG
B. BRAFMAN 03/13/81
SYNDROME BIT GENERATOR
MMI FIELD APPLICATIONS ENGINEER YORBA ,LINDA, CALIFORNIA
SYNCLK 07 06 BO B1 B2 B3 05 04 GND,
/oe 03 02 A3 A2 Al AO 01 DO vee'
:,
IN THE ABOVE PIN LIST, THEFOLLOWlN~ SUQSTlTUTIONS HAVE BEEN ,
MADE TO ACCO.,OATE THE SPECtFIO FORMAT MEANS
B1 MEANS
:B2!:MEANS
B3MEANS
AO'MEANS
Al -MEl\NS
A2 MEANS
A3 MEANS
/C3
/C2
/<=1
/eo
/S3
/S2
/Sl
ISO
(CHECKB!T 3)
(CBECKBIT2)
(CHECK BrT 1)
.)
(~KBITO)
(SYNDROMEB):T
(SYNDROME 'BIT
(SYNDROME BIT
(S'YNJ)ROMEBIT
3)
2)
1)
0)
BO-B7 ARE THE BITS OF .THE OAT~ WORD.
THE .SUBSTITUTIONS APPLY BELOW. WlTB THE
/AO :=
+
+
+
:+:
,+
/Al :=
+
+
+
:+:
+
/A2 :=
+
+
+
:+:
+
+
+
/A3 :=
+
+
+
:+':
+
+
+
A
~~A
EXC~TION.
07*06* 05
/07*/06* 05
/07* 06*/05
07*/06*/05
04* (/BO)
(04*( BO)
:B7 :+: B6 :+: Bs
:~4
:+: C3
0.7* 03* 02
/07*/03* 02
/07* D3*/02
07*/03*/02
01* (/B1)
/01*( B1)
:B7
:+:
OF COMMENTS.
:+:
B3 :+: B2
:+:
:B1 :+: C2
:06* 05* 03
/06"'/05* 03
/06* 05*/03
06*/05*/03
02* 00*( B2)
/02*/00* ( B2)
/02* 00* (/B2) 02*/00* (/B2)
1136 :.+: Bs :+: .B3
06* 04* 03
/06*/04* 03
/06* 04*/03
06*/04*/03
01* 00* ( B3)
/01*/00* ( B3)
/01* 00* (/B3)
01*/00* (/B3)
lB6 :.+: B4 ;+: B3
:+:
",
,"
lB2 :+: BO l.+: C1.
'
... \.
!
:'+:
lBl :+: ,BO
:+: CO
~
:",
8-Bit Error Detection and Correction
FONC'l'ION 'mBLE
SYNCLK
loe
,eON'l'ROL
,SYN I
, eLK oe
07 06 05 04 03 02 D1 DO BO B1 B2 B3
lAO IA1 IA2 IA3
IIII
-DATADDDDODOD
76543210
BBBB
0123
AAAA
0123
eoMMEN'l'S
LLLL
HHLL
HLBB
NO ERROR
D7 ERROR
06 ERROR
05 ERROR
D4 ERROR
03 ERROR
D2 ERROR
D1 ERROR
00 ERROR
BO ERROR
NO ERROR
B2 ERROR
B1 ERROR
NO ERROR
D7 ERROR
06 ERROR
D5 ERROR
D4 ERROR
03 ERROR
D2 ERROR
01 ERROR
DO ERROR
BO ERROR
B1 ERROR
B2 ERROR
B3 ERROR
------------------------------------------e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BBBBBBBH
LLBH
LARRABHH
LLHH
BLBBBBBB
BBLBBBBB
LLBH
LLHH
LLBB
BBBBLBBB LLBB
HBHBBLBB LLBB
tu1HHHl1LB LLHH
BBBBBBBL LLHH
BBBBBBBB BLBB
BARBARHH
LLBB
HBHtItItItItI
LLLB
BBBBBBHH LLHL
LLLLLLLL LLLL
BLLLLLLL LLLL
LBLLLLLL LLLL
LLHI.I,LLL. LLLL
LLLBLLLL LLLL
LLLLBLLL LLLL
LLLLLHLL LLLL
LLLLLLBL LLLL
LLLLLLLB LLLL
LLLLLLLL BLLL
LLLLLLLL LBLL
LLLLLLLL LLBL
LLLLLLLL LLLB
AAA',HHHH
BLHL
BLLH
LHBB
LBBL
LBLB
LLBB
BLLL
LLLL
LLHL
LLLB
LLLL
BBLL
HLBB
BLHL
HLLB
LBBB
LHHL
LBLB
LLBH
BLLL
LBLL
LLBL
LLLB
DI
-------------------------------------------
4-337
a.Blt Error Detection and Correction
DESCRIPTION
THIS PAL GENERATES THE SYNDROME BITS· FOR A 12 BIT HAMMING CODE WORD
AS A FUNCTION OF THE 8 DATA . BITS AND THE 4 CHECK BITS TO POINT TO
ANY SINGLE BIT IN ERROR.
8·Bit Error Detection and Correction
SYNDROME BIT GENERATOR
1 C11001111X011BBBB111
2 C0100111lX011BBLL111
3 C1000111lX011LLBL111
4 C11001101X011HLRL111
5 C11001110X011LBBL111
6 Cl1001111X001LLLH111
7 Cl100111lX010HLLH1l1
8 C1100111lX011LHLS011
9 Cl1001111XOllLLHH101
10 Cl1101111X011HHHL111
11 C1100111lX011HBHB111
12 CllOOOlllXOllHLHH111
13 C1100101lX011LHHH111
14 cOOOOOOOOXOOOHHHH001
15 C10000000XOOOHHLL001
16 C01000000XOOOLLHL001
17 C00000010XOOOHLHL001
18 COOOOOOOlXOOOLBBL001
19 COOOOOOOOX010LLLH001
20 COOOOOOOOX001HLLH001
21 COOOOOOOOXOOOLHLH101
22 COOOOOOOOXOOOLLHH011
23 C00100000XOOOHHHL001
24 C00010000XOOOHHLH001
25 ·COOOOlOOOXOOOHLHHOOl
26 C00000100XOOOLHHHOOl
PASS SIMULATION
4.338
·8-Bit Error Detection:and Correction
SYNDROME BIT GENERATOR
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
16 x--- x--17 -x-- -x-18 -x-- x--19 x--- -x-20 ---- ---21 ----
-------------x-x
x-x-
x--x---x--x--------
------------x---x--
07*06*05
/07*/06*05
/07*06*/05
07*/06*/05
04*/B0
/04*BO
24 x--25 -x-26 -x-27 x--28 ---29
-----------x---x
--x--x---- ---- ---- ---- ---x
---- ---- ---- ---- ---x
---- -x-x ---- ---- ------- x-x----
--x---x
--x---x
-------
07*03*02
/07*/03*02
/07*03*/02
07*/03*/02
01*/B1
/Ol*B1
x---x--x-x--------------x---x--x-x----x---x
---x
--x-
-------------------------------------------------
--x--x---x
---x
-------
--x- ----
06*05*03
/06*/05*03
/06*05*/03
06*/05*/03
02*00*B2
/02*/OO*B2
/02*00*/B2
02*/OO*/B2
-------------------------
06*04*03
/06*/04*03
/06*04*/03
06*/04*/03
01*00*B3
/Ol*/OO*B3
/01*00*/B3
01*/OO*/B3
32
33
34
35 ---36 --x37 ---x
38 --x39 ---x
40 ---41 ---42
43 ---44 --x45 ---x
46 --x47 ---x
LEGEND:
----------------
-------------------..;.-----------------------------
----------------
------------x-xx-x-x-x
-x-x
-------------------------
----------------
------------------------------------x-xx-x-x-x
-x-x
x---x-x---x---x---x
---x ----
x: FUSE roT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
828
x-x-xxx--x
-x-x
-------------
- : FUSE BLOWN
(H,P,l)
8-Bit Error Detection and Correction
Syndrome Bit Generator
SYNCLK
Logic Diagram PAL16X4
I
0123
4567
891011
12131415
16111819
20212223
24252621
2829]031
0
1
2
3
4
6
07
2
...
...
.,
8
12
13
.
3
~
18
0
14
15
...
16
1)
18
"
80
19
)
10
11
D6
~
;J
5
~
20
21
22
,
.........
AO
~D-
~
A1
~
A2
-D
.......
24
25
26
27
"
-
30
31
5
Ei
..........
~~1
H~n=t"""\.
-c -z.
~
36
~
37
38
39
,
--:-
~
6
F
~40
-~
-t> cr"
~D-;f::-~
41
"
43
44
45
46
47
83
- or--
-D
;
32
l3
34
35
82
or--
~~1
28
81
01
;}D ~~
23
m
DO
,
.
~
A3
-:-
.......... 48
~b-J
"
50
51
52
05
8
...
...
54
55
"
>;j
5)
58
"
04
9
...
13
.;J
53
6D
61
62
63
r
~
01234561891011
1213141516111111
20212223
2425262728293031
12
~
02
03
a-Bit· Error Detection and Correction
PAL16L8
PAL DESIGN SPOCIFlCATION
OCUl
B. BRAFMAN 03/13/81
ERROR CORROCTION UNIT No. 1
MMI FIELD APPLICATIONS ENGINEER YORBA LINDA, CALIFORNIA
/S3 /S2 /S1 ISO B7 B6 BS B4· B3 GND
B2 NC NC B2C B3C B4C BSCB6C B7C vee
IF (vee) /B7C
=
+
+
+
+
S3* S2*/S1*/SO* B7
/S3*/B7
/S2*/B7
S1*/B7
SO*/B7
1CORRECTION OF B7
1NO CORRECTION
1NOCORRECTION
1NO CORRECTION
1NO CORRECTION
IF (vee) /B6C •
+
+
+
+
S3*/S2* S1* SO* B6
/S3*/B6
S2*/B6
/S1*/B6
/SO*/B6
1CORRECTION OF B6
1NO CORRECTION
1NO CORRECTION
1NO CORRECTION
1NO CORRECTION
=
S3*/S2* S1*/SO* BS
/S3*/BS
S2*/BS
/S1*/BS
SO*/BS
1CORRECTION OF BS
1NO CORRECTION
1NO CORRECTION
1NO CORRECTION
1NO CORRECTION
S3*/S2*/S1* SO* B4
/S3*/B4
S2*/B4
S1*/B4
/SO*/B4
1CORRECTION OF B4
1NO CORRECTION
1NO CORRECTION
rNO CORRECTION
1NO CORRECTION
IF (vee) /BSC
+
+
+
+
IF (vee) /B4C
=
+
+
+
+
IF (vee) /B3C
= /S3*
S2* S1* SO* B3
S3*/B3
/S2*/B3
/S1*/B3
/SO*/B3
1CORRECTION OF B3
1NO CORRECTION
tNO CORRECTION
1NO CORRECTION
1NO CORRECTION
IF (vee) /B2C = /S3* S2* S1*/SO* .B2
+ S3*/B2
+ /S2*/B2
-I;jSl*/B2
+ SO*/B2
1CORRECTION OF B2
1NO CORRECTION
1NO CORRECTION.
1NO CORRECTION
1.NO CORRECTION
+
+
+
+
8·81t Error Detection and Correction
FONC'l'ION TABLE
S3 S2 Sl so B7 B6 B5 B4 B3 B2 B7C B6C B5C B4C B3C B2C
, SYNDROME
, SSSS
, 3210
INPUT
BBBBBB
765432
CORRECTED
BBBBBB
765432
LLLL
LLLL
aBLL
UBBBHB
UBBBHB
LLLLLL
LBBBBH
BLLLLL
COMMENTS
.
-----------------------------------------------.
aBLL
LLLLLL
~
LLLLLL
BLBB
BLBB
BLHL
BLHL
BBBHHH
BLHBBB
LLLLLL
LHLLLL
LLLLLL
LLHLLL
HLLB
HLLB
BBBmm
BBHLBB
LLLLLL
LLLBLL
LBBH
BBBBBH
BBHHLB
LBBH
LaBL
~
BB$m
mrimJm
LLLLLL
BHLHBB
toLLLHL
BBBHHL
LLLLLB
______________ _________
LLLI¥o
~_~
NO ERROR
NO ERROR
CORRECT B7
CORRECT B7
CORRECT B6
CORRECT B6
CORRECT B5
CORRECT BS
CORRECT B4
CORRECT B4
CORRECT B3
CORRECT B3
CORRECT B2
COlUUlCT B2
~~--------~.
___
~-----c
DESCRIPTION
THIS PAL PERFORMS ERROR CORRECTION ON BITS B2-B7 BASED ON THE 4-BIT
ERROR SYNDROME SO-S3.
'
ERROR CORRECTION UNIT U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
111111111X1XXHBHBHHl
111100000XOXXLLLLLL1
001l1l1l1X1XXBBHHHI,l
001100000XOXXLLLLLHl
01001111lXlXXHBBHLB1
010000000XOXXLLLLHL1
010111111X1XXBBHLHB1
01010QOOOXOXXLLLBLL1
01lO1l111X1XXHHLBHB1
011000000XOXX~L1
10001111lX1XXHLHBHB1
100000000XOXXLBLLLLl
100111111X1~1
100100000XOXXHLLLLL1
PASS SIMULATION
8-Blt Error Detection and Correction
ERROR CORRECTION UNIT No. 1
11 1111 1111 2222 222.2 2233
0123 4567 8901 2345 6789 0123 4567 8901
o --- ---I
2
3
4
5
8
9
10
11
12
13
16
17
18
19
20
21
-x-x x---
-x- ---x---x-
x~-
'----
x---
-x--x--
-x--x-- -x--
x--x -x-- -x--
x---x--
x--
-x..-
-x-x--
x--
S3*/S2*Sl*SO*B6
/S3*/B6
S2*/B6
/81*/B6
/SO*/B6
-x--
x---
-x--
x-x -x- x---
-x-x-
83,*S2* /81 */SO*B7
/S3*/B7
/S2*/B7
Sl*/B7
SO*/B7
x---x--x--x--x--
-x--
S3*/S2*81*/80*B5
/S3*/B5
S2*/B5
/Sl*/B5
SO*/B5
24
25
26
27
28
29
x--x x-- -x--x-x-x-x---
32
33
34
35
36
37
-xx- -x- -x---x
x-x-x---
x---x--x--x--x--
/S3*82*Sl*SO*B3
S3*/B3
/S2*/B3
/Sl*/B3
/80*/B3
-xx- -x-- x----x
x--x--x--
--x---x
/S3*S2*Sl*/SO*B2
S3*/B2
jS2*/B2
/Sl*/B2
SO*/B2
40
41
42
43
44
45
LEGEND:
~---
x--
----
4-344
-x-x--
x: FU8E NOT BLOWN (L,N,O)
NUMBER OF FU8ES BLOWN = 1074
S3*/S2*/Sl*SO*B4
/S3*/B4
S2*/B4
Sl*/B4
/SO*/B4
-x--x--
---x
---x
--x
- : FUSE BLOWN
(H,P ,1)
a-Bit Error Detection and Correction
Logic Diagram PAL16L8
Error Correction Unit No. 1
(J
12 3
4!i 61
891011
12131415
16171819
202122"23
24252627
28293031
0
~
1
2
J
4
5
6
2
7
.
:r-J
••
~SJ
10
fI
12
13
....
~
~
...
11:'1------
,.
t-
19
I-
20
>=11
21
22
"
""
27
""
5
.....
30
J1
~
...
-
~SJ
pJ
J5
36:
J7
J8
"
40
41
42
...
44
7
...
1"
..
51
54
84
...>
55
.."
61
U
..
B2C
...
)--
:r-J
13
NC
....
50
...
14
...'I---
'.
...
9
~~
:1-----
...
'0,
B3
B3C
~
41
"
""
8
15
...I - - -
...
43
IS
B4C
~
JJ
...
16
....
"
6
BSC
'~:.I---
J2
B6
17
~'
24
B7
B6C
15
17
.
18
!----,
\4
16
4
B7C
...' I - - -
~
3
19
"
:""
~
'
...
~
12
11
82
4-34'
8 ..Bit··Error .Detection and' Correction
PAL16L8
PAL DESIGN 5PECIFICATION
ECU2
B. BRAFMAN 03/13/81
ERROR CORRECTION UNIT No. 2
MMI FIELD APPLICATION5 ENGINEER YORBA LINDA, CALIFORNIA
/53 /52 /51 /SOB1 BO /C3 /C2 /C1 GND
/CO NC ERRORCOC CIC C2C C3C BOC B1C vec
IF (vee) /B1C =
+
+
+
/53* 52*/51* 50* B1
53*/B1
/52*/B1
51*/B1
,CORRECTION OF B1
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
IF (vee) /BOC •
+
+
+
+
/53*/52* 51* 50* BO
53*/B0
52*/B0
/51*/B0
/50*/B0
,CORRECTION OF BO
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
IF (vee) /C3C'. 53*/52*/51*/50* C3
+ /53*/C3
+ 52*/C3
+ 51*/C3
+ 50*/C3
,CORRECTION OF C3
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
IF (vee) /C2C •
+
+
+
+
/53* 52*/51*/50* C2
53*/C2
,CORRECTION OF C2
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
IF (vee) /C1c •
+
+
+
+
/53*/52* 51*/50*C1
53*/C1
52*/Cl
/51*/Cl
50*/C1
,CORRECTION OF C1
,NO CORRECTION
,NO CORREX::TION
,NO CORRECTION
,NO CORRECTION
IF (vee) /COC ..
+
+
+
+
/53*/52*/51* 50* CO
53'(r/CO
52*/CO
51*/CO,
/50*/CO
,CORRECTION OF CO
., NO CORRECTION
,NO CORRECTION
,NO CORRECTION
,NO CORRECTION
/52*/C2
51*/C2
50*/C2
IF (vee) /ERReR = /53*/52*/51*/50
4-346
,NO ERROR!
a-Bit Error Detection and Correction
FUNCTION TABLE
S3 S2 Sl
1SSSS
13210
so
BB
10
B1 BO C3 C2 C1
CCCC
3210
BB
10
CC
co
CCCC
3210
CCCC
B1C BOC C3C C2C C1C COC ERROR
ERROR
COw.mNTS
-----------------------------------~----------------
LLLL
LLLL
LLLL
LLLt
LHLH
LHLH
LLHH
LLHH
HLLL
HLLL
LHLL
LHLL
LLHL
LLHL
LLLH
LLLH
HH
Xx
LL
xx
JIH
LL
HH
LL
xx
xx
xx
xx
xx
xx
xx
xx
xxxx
HflHH
XXXX
LLr.;:r..
xxxx
xxxX,
XXXX
xxxx
HHHH
LLt:;L
flHRH
LLLL
HHHH
LLLL
HHHH
LLLL
HH
XX
XXXX
HHHH
4
xxxx
tH
Ht
HL
,LH
xxxx
xxxx
XXxX
xxxx
xx
xx
xx
xx
xx
xx
xx
xx
xx
LLLL
LHHH
HLLL
HLHH
LHLL
HHLH
LLHL
HHHL
LLLH
L
L
L
L
H
H
H
H
H
H
H
H
H
H
If
H
NO
NO
NO
NO
ERROR.
ERROR
ERROR
'ERROR
~()RRECTJ31
CORREC'r B1
CORRECT BO
CORRECT :eo'
CORRECT C3'
CORRECT C3
CORRECTC2 .,'
CORRECT C2
CORRECT ~1
CORRECT C1
CORRECT cO
CORRECT co
-------------------------~~-------------------------
DESCRIPTION
THIS PAL PERFORMS ERROR CORRECTION ON BITS BO-B1 AND CHECKS BITS
CO-C3 BAS]!:DON THE 4 BIT ERROR SYNDROME SO:"S3.
ERROR CORRECTION UNIT
'2
1 llllllXXX~XXLXXXXHHl
2 llllXXOOOXOxLHBBRXXl
3 111100XXXXXXLXXXXLLl
4 llllXXlllXlXLLLLLXXl
5 lOlOllXXXXXXBXXXXBLl
6 lOlOOOXXXXXXBXXXXLHl
7 1100llXXXXXXBXXXXLBl
8 llOOOOXXXXXXBXXXXBLl
9 OlllXXOOOXOXBBBBLXXl
10 OlllXX111XIXBLLLaXXl
11 lOllXXOOOXOXBBHLBXX1
12 101lXXIllXlXHLLHLXX1
1.3 llOlXXOOOXOXBHLBBXX1
14 llOlXXlllXlXBLBLLXX1
151110XXOOOXOXBLBBBXXl
16 1l10XX111XIXBHLLLXXl
PASS SIMULA'l'ION
4-847
8.Blt Errol' DetectIQft'.and.£orrectlon
ERROR CORRECTION UNIT No. 2
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
o ---- ---- ---- ----xx- x--- -x-- x--
1
2
3
---x ---- ---- -x-x---x--
4
-x--
-x--
8
9
x-x- -x-- -x--
------- ---------- ----
...:.;,....::·.,;'/S3*S2*/sl*sO*B1 .
---- sj*/Bl
-...;...:- /S2*/B1
---- ----
----
~--~'Sl*/B1
x--- ---- ---- ---- /S3*/S2*Sl*SO*BO'
10 ---x ---- ---- ---- -x-- ---- ---- ---- S~*/BO
11 -x--x----- ---- S2*/B0
12
x---x----- --~- /Sl*/BO
13
x---x----- ---- ./SO* /BO
16
17 x--x x--- x--18 --x- ---- ---19 -x-- ---20 ---- -x-21 ----x-24
25
'.26
27
28
29
,
---- ---- x--- ---- ---x--- ---- ----
x--- ---x--- ----
/S3*/C3
S2*/C3
---- Sl*/C3
----SO*/C3
'
----
-xx- x--- x-x-- ---- /S3*S2*/Sl*/SO*C2
---x ---- ---- ---- ---- ---- x--- ---- S3*/C2
x--X---, ---- /S2*/C2
-x-x--- ----Sl*/C2
-x--
32 ---- ---33 x-x- -x-- x--34 ---x ---- ---35 -x-36
x--37
-x-40
41
42
43
44
45
---- ----
-x-- ---- --,..., S3*/S2*/Sl*/SO*C3 .
x-x---x
-x--
x--- -x--
x--- ---- SO*/C2
--- ---- --------- -x--
48
49 x-x-
LEGEND:
-x----- ---- x--x--x--x---
----
---x S3*/CO
/S3*/S2*/Sl*SO*CO
____________ --xr
x---
x--- x---
---- ---- --x- S2*/CO
---- ---- --x- Sl*/CO
---- --x- /SO*/CO
---- ---- /S3*/S2*/Sl*/SO
x: FUSE mT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =1104
4-348
/S3*/S2*Sl*/SO*C1
S3*/C1
S2*/C1
/Sl*/C1
SO*/C1
- . FUSE BLOWN
(H,P,l)
a-Bit Error Detection and Correction
Error Correction Unit No. 2
Logic Diagram PAL16L8
S3 '
G 123
4561
891011
1213141fi
16171819
20212223
24252627
28293031
0
:>-J
1
2
,
J
5
6
7
2
...
..
11:
~
19
B1C
...
8
9
:=->--J
10
11
12
13
14
15
3
..
....1---
--I
sb---J
17
18
19
20
21
22
..
"
~
~b-J
16
27
28
29
JO
.
~
...
>-J
l'
J5
J6
J7
J8
6
...
C2C
~.t----
~
l2
J3
BO
1fi
f--
J1
81
C3C
11:.1---'
24
...
17
...
~
25
5
BOC
i-------,
16
4
18
15
C1C
39
....
...
... t----?-
~
"
"
~b-J
41
42
44
""
I.
CDC
47
7
.1---
""
""
~b-J
"
"
53
54
8
to.
ERROR
~
C3 - - 1
"
"
""
~~
63
f--
5)
61
62
g
13
to.
..
...
012,3
4561
891011
12131415
16171819
20212223
24252627
12
NC.
}'.
.",
11
28293031
4-3.49
Notes
5-1
Video Controller
to Video Section
..Introduction
.
.
Computer graphics is a rapidly growing field in the computer
industry. It enables communication between the human being
and the computer. The human eye can absorb information
displayed in diagrams, numbers, letters and images I\luch faster
than it can absorb tables with numbers only. Computer graphics
is penetrating into almost every professional field and the "video
games" syndrome is spreading into more and more living
rooms.
The PAL family teams up to help the wide-spread use of
computer graphics. By using high speed PAls, the designer can
implement simulations and real time systems in an efficient way.
The following designs are examples of the use of PALs in the
video world.
1. 10 BIT .COUNTER [SN54n4LS491] This is ideal for video
synch generation for CRT graphics including video games.
This counter provides the vertical and horizontal coordinates
required to address the graphic data. Video resolution is
usually 9 or 10 bits in the vertical and horizontal which in the
past·was supplied by three LS161's. These, of course, can be
replaced by one LS491. This counter can also count down
which allows screen coordinate reversal.
2. Analog to digital and digital to analog converters, change
analog signal into an equivalent digital code and vice versa.
This function is commonly required in a digital system when
the analog information has to be stored and then shown as a
displacement on a CRT.
3. The video logic deSign shows the reduction in the number of
parts on a video-interface board using PALs.
4. The video-controller board is an example of how to implement
a video system using PALs.
Implementing a Video Controller
Using Programmable Array Logic
by Ehud "Udi" Gordon
The use of video is definitely a sign of the times and will be with
us into the future. The video-controller board is the bridge
between 'the' outside world and the screen. There are many
possibilities to implement the video-controller board. but an
efficient one uses PALs. The following will simplify the construction of a video-controller bOllrd and will assist the cjesigner
in elimio/lting·board space problems.. PAt'$:are' the backbone o~
this application.
.
RS232
9600
VIDEO
CONTROLLER
BAUD
RS170
COMPOSITE
VIDEO
KEYBOARD
Overview
There are words that belong to spa.cifiY cq(lCepts within the
video industry. For a clear uriderstandintj{'o'thow the videocontroller board works we nee.d
, to define ; some of them:
~
FRAME -
,
A single complete picture· .'.
SCANNING - The process of analyzing successively, according to a predeterminecJ method, the light values of picture
elements which constitute th~ total picture area
FRAMI: FRI:QUI:NCY - The numbkr of times per second the
picture area is completely scann~a
The frame frequency has· been standardized at 30 frames per
second, which gives a satisfactory .illusion of motion continuity,
although the individual picture· elements are transmitted one
after the other. A frequency of 30 frames per second is equal to
half the power-line. frequency in most locations. Using this
standardized rate, the entire screen is illuminated 30 times per
second. This is too slow to give the impression of a truly steady
light, so a flickering occurs.
To overcome the flickering problem it is common to use the
INTERLACED SCANNING METIiQD. In this method the screen
is divided into 525 lines and into two fields. There is an odd
numbered field and an even numbered field. Each of these fields
is made up of one-half of the screen by dividing the frame into
odd and even numbered lines. First,.allthe odd numbered lines
1, 3, 5, ... are scanned from top to bottom. After scanning a
total of 262.5 odd numbered lines, the even numbered lines are
scanned from top to bottom, for the total of 525 lines. Each
scanning period from top to bottom"is 1/60 of a second and is
called a FIELD. Two fields constitute a frame.
'"':
Figure 1a. Odd Numbered Lines Scanned Generate the
Odd Field
Flgure1b.Even Numbered Lines Scanned ..Gene,ate the
Even Field
Video Controller
3
5
--
~
--
--
~
~ --
ETC.
-
r
r
-
- --------
--
Figure 1c. The Solid Lines 1, 3, 5, ... Represent the Odd Field.
The Dashed Lines 2, 4, 6 ... Represent the Even Field
Figure 1d. The Odd and Even Fields Combined Generate
One Frame
FIELD FREQUENCY - The number of times per second the
field is completely scanned
vertical retrace, blanking pulses are transmitted which blank out
the total screen for this time period. The rate of the vertical
synchronizihg pulse is equal to the number of fields transmitted
per second: 60 pulses/second.
The field frequency has been standardized at 60 fields per
s~cond. At this rate, the screen gets illuminated 60 times per
second which results in the disappearance of the flickering.
(Notice that the frame frequency is still 1/30 of a second.)
At the end of each scan line the electron beam moves rapidly
from right to left on the screen which gives the horizontal retrace.
Then it moves across the next odd/even numbered scan line
and returns retracing right to left. While the beam retraces,
blanking pulses are transmitted which blank out the total screen
for this tim., period.
A HORIZONTAL SYNCHRONIZED PULSE is used to time the
start of each horizontal scan line. The rate of the horizontal
synchronizing pulse is equal to the total number of lines per
frame multiplied by the number of frames transmitted per second:
525 lines' 30 frames = 15750 pulses/second
A VERTICAL SYNCHRONIZED PULSE is used to time the
start of each field. It occurs at the end of each field and causes
the beam to go from bottom to top of the screen. During the
Figure 2. Horizontal Scanned Lines With the Retraces
BLANKING FOR ~I
SYNCH AND
RETRACE
.16 H
I
Figure 3. Composite Video Signal
~
-
-
REFERENCE WHITE LEVEL
I
I
REF/!RENCE BLACK LEVEL
BLANKING LEVEL
I> = 1.0 ± 0.05 Volts
= 0.4 ± 0.051> Volts
H Time From Start of One
Line to Start of Next Line
0'
FRONT
PORCH
...
PORCH
'HORIZONTAL SYNC PULSE
H_
5·5
Video Controller
A picture signal is defined as voltage levels which when
combined with the synchronizing pulses generate A COMPOSITE VIDEO SIGNAL. There are two reference voltage levels;
i.e., a high voltage level =white and a low voltage level = black
(see Figure 3). In between these reference levels are the gray
tones. The synchronizing pulses are below the black level so
they do not produce light.
The horizontal and vertical pulses along with the picture signals
constitute a frame where 15,750 horizontal lines are scanned
every second making one complete horizontal cycle of approximately 63.5 microsceonds (commonly called 1H). Because
of the front and the back porches (see Figure 3) that are used for
retrace time and synchronization, the visible portion lasts approximately 54 microseconds. The time from the start of one
field to the start of the next field is 262.5H or 1V.
Figure 6 illustrates the relationship between (a) the horizontal
and vertical sweeps and (b) the line and the field blanking. A field
blanking signal starts at Point A which is the initiation of the
vertical retrace where the electron beam is at the bottom of the
screen. During the vertical retrace period, the beam moves back
and forth across the screen until it reaches the top of the screen
(see Figure 5). The field remains blank until the beam reaches
Point B. From Point B the beam is visible until it nears the right
edge of the screen. At this time, horizontal blanking occurs and
the beam moves from the right edge to the left edge of the
screen. Horizontal blanking occurs 263 times for each field. At
Point C, a new vertical retrace for the next field is initiated. At
Point D, the beam finishes the scan of the entire screen for one
frame. This point corresponds to POint A in the first field, so a
field blanking occurs again.
PAL MAN
LINE AROUND
PAL MAN
UNDER LEAD
~-----TIME 15~50 SEC (APPROX.)-----.~
Figure 4, A Waveform of Video Voltage Produced by Scanning
One Line on a Televised Screen
EVEN LINE TRACE
LINE TRACE
LINE TRACE
Figure 5. Vertical Retraces for the Odd and Even Fields
VideO. Controller
~_________________________1 COMP~~T~FRAME __________________________~_I
~_ _ _ _ _ _1~~2~~E~D ________-'l·~'"'I___________~2~~2:SI~L:t:D_ _ _--""_~I
I
TIME.
_: , . "••(';,2.5:>
HORIZONTAL
SWEEPS
15750 PER SECOND
~f~jl fiu~1'~1
1 - -.07v_I"
VERTICAL
SWEEPS
60 PER SECONO
..
_I
.93V
_1~-.07v---'-+-1
-.93V
~18.4 LINES--..j"-:--244.1 LINES-_~18.4 LINES-....1'+--244.1 LlNES-_1
I
I-
PICTURE
I_
-,
.1
PICTURE
Figure 6. Vertical and Horizontal Sweeps, and Blanking Within a Frame
I
I
1,",4~--~__-----H--------~------~~1
t.
LEFT EDGE OF SCREEN ~'. ,I
END OF HORIZONTAL
. "I
RETRACE
.
1
r
/
f' .
I I
I I
END OF HORIZONTAL
BLANKING
.
START OF HORIZONT~L -..I
BLANKING ;.
I
I
I~
I
I
1
I
I
I
I
END ~F VERTICAL
--'.~"'--~=-=-=-:==-=-====-=-=-==-=-1lr~&}~
RIGHT EDGE OF SCREEN
START OF HORIZONTAL
RETRACE
APPROXIMATELY 488
VISIBLE LINES
1
~!~~~~~~~~~~~~=~~~~~~~~~:....:::....:::....::2f,J~¥~
START OF VERTICAL
____B.!:..A!:!~~ __ fj
262.5 H INITIATiON
VERTICAL RETRACE
2ND FIELD
t--'---- 0.5 H -------""I
REPRESENTS THE RETRACE
PORTION .OF THE VERTICAL
SWEEP. AND IS ACTUALLY
FOLDED BACK FROM BOTTOM
. TO TOP OF SCREEN
Figure 7. Effect 01 Vertical and Horizontal Blanking on the Screen
Figure 7 shoWs the actual movement of the beam and the effect
of the line and the field blanking' on the screen. The shaded
portions at the top and bottom of the screen represent field
blanking, while the shaded portion at the left and right edges of
the screen 'represent line blanking. The combinatiOn of the
shaded portions. with the unshaded' portions represent the
available screen size, if nbretracing were .necessary.
From a single scan line to a complete picture which defines a
frame, we have presented the concept and the process for
sending information (a composite video signal) to a video
receiver.
5-7
Video Controller
RS232
9600
BAUD
VIDEO
CONTROLLER
RS170
COMPOSITE
VIDEO
KEYBOARD
16 LINES
48 CHARACTERS
PER LINE
Figure 8. A Very Simplified Diagram
From the Keyboard to the
Video Controller
The input to our video controlier comes from a keyboard
terminal or a computer. The information is transferred via an
RS232 port to the video controlier, one bit at a time. Each
character is represented in ASCII code and is detected by the
video controlier only if a start Signal was first issued.
+12V
,.:;:.:.:...,..........---..".~=...-=-T"O"",..=T~STOP
BIT
-12V MARK
"0"
"1"
ASCII CODE FOR A CHARACTER
Figure 9. Each Character Consists of 10 Bits
1 Start Bit
7 ASCII Bits
1 Parity Bit
1 Stop Bit
From the Video Controller to
the Video Screen
Our video controlier uses a NON-INTERLACED METHOD for
scanning (see Figrue 10). In this method, the traced lines are
adjacent and each frame consists of 260 scanned lines. Each
field is equal to a frame which changes the definition of a field
so that a complete frame is now transmitted in 1/60 of a second.
Figure 11 shows the horizontal and .the vertical sweeps which
cut in half the common frame frequency and now generate two
frames for the same amount of time. At the end of each
horizontal line, the electron beam moves rapidly from the right
edge to the left edge of the screen while blanking pulses are
transmitted (Points C-O in Figure 11).
5·8
The design is based on using 260 scan lines and an 8 MHz
crystal. In order to obtain the standard horizontal period of 63.5
microseconds, each horizontal line is divided into 512 cycles
giving a line period of 512/8 = 64.0 microseconds. The frequency
of the electron beam is equal to the power line frequency
(60 Hz) so in a clear environment (without noise) the picture is
clear and steady.
8 MHz
FRAME RATE =
.'
260 scan lines
=60.09 Hz
512 cycles per line
These figures and calculations are explained and diagrammed
in detail in the section on implementation.
START
A
OF EACH
FIELD OR FRAME
1
.:.::.
2
3
4
~"
" "'- "'-
5
"'- ~
"
ETC.
"'-
" "'-
""
Figure 10. Non"interlaced Scanning: 260 Solid Lines Represent
a Frame. The Dashed Lines are the Retrace Lines.
Video Controller
~I·~-------------------------------~OH--------------------------------~·~I
I.
.1.
260H
·1
260H
r~
r ~ A-_~~-~_~~:_-~_vJ
@I
1
V ~\
~r
r,
r.
r
,".
:
_r
...•..r
HORIZONTAL
SWEEP
15600 P.S.'
.
I-- START
I SECOND
j...--:"START
ONE
1
FRAME (FIELD)
1
1
I
I
1
1
FRAME (FIELD)
I VERTICAL
SWEEP
60 P.S •.
F
Figure 11. 5~ Horizontal Lines Generate Two Fields Which
Constitute Two Frames In A No~lnteriaced Scantling
between the character-lines.~ch dot in 'a dot-line is called
At the end of 260 horizontal lines, theeleotrOn beam is blanked
out while it goes \:lack from the bottom to the top of the screen
(Points E-F in Figure 11).
a PIXEL.
" Rgure 12 shows dne charader'-linewifh the characters"U,'D, '"
and all the pixels that built these three character's on the screen.
These pixels or character elements 'areisent'one after the other
in an orderly sequence across the dot-line. Twelve dot-lines are
rapidly transmitted to create one character-line. This is called
SUCCESSIVE NlETHOP OF TRANSMISSION (see Figure 13).
The video controller can display a maximum of 16 visible
character-lines with 48 visible characters per character-line.
Each character is produced by a 5X7 character generator. A
character-line on the screen consists of twelve dot-lines: seven
,dot-lines for the character and five blank dot-lines for space
5x7 CHARACTERS GEN£IIATED BY
5x7 CHARACT~R . GENERATOR
,
~
. 0 0 0 . 0 0 0 • • • • 0 0 0 0 0 • • • 0000
• 000.000.000.00000.00000
. 0 0 0 • 0 0 0 • 0 0 0 • 0 00 0 0 • 0 O~ 0 0
-FOR THE
• 0 0 0 • 0 0 0 • 0 0 0 • 0 0 0 0 0 • 0 0 0 0 0
CHARACTER
.000.000.000.00000.00000
.
.OOO.OOO.OOO.OQOOO.OOOOO
0 ••• 0 0 0 0 •••• 0 0 0 0 0 ••• 0 0 0 p
5 BLANK
DOT-LINES \ ' 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FOR SPACE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 DOT-LINES {
Figure 12.
One Character-line
With Three Characters
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000
-
. 0 0 0 • .000
•. 0 0 0 " 00 o·
.000.000
.000.000
.000.000
.000.000
0
,000000"00
,gggggggg ,:
00000000
00'000 D 0 0
0
0
0
•
0
0
0
o •••
•
0
0
0
•
0
0
0
0
0
0
0
0
0
•
0
0
0
•
0
11
"
0
0
•
0
0
0
•
0
0
0
•
0
00 •
0
0
0
•
0
0
0
•
0
0
0
DOT-LINE 3 __ _
DOT-LINE 2
0
0
PIXEL
Figure 13. Successive Method of Transmission. For Simplicity
'. ASSl!me pnly One Character 'U'. E.ac;t! Dot-line is
Sen•. Jn qrde~y Sequence.
.
o.·.·.no·o
•
12 DOT-LINES =
1 CHARACTER-LINE
.. .
.. .
.. .
gggggggggggg~oggggggggggg .. .
BETWEEN
CHARACTER
LINES
DOT-LINE 1
•••
•••
...
•••
.. .
.. .
0
000 000 000 000
DOT-LINE 12
Video Controller
Implementation
Our video-controller board is divided into two subsystems
which are connected by a RAM. The RAM is time shared by the
two subsystems and provides the effect of a multi-port RAM. An
8-bit ASCII code is entered into the system through a "write
only" port which is connected by the RS232 interface. The code
is written into the RAM in locations indicated by pointers
"SCROL" and. "CURS". We d,on't write every cycle, but we read
every cycle. The code is read from the RAM from locations
indicated by pointers "LINES" and "CHAR" and transferred
through ,a "read only" port to a character generator that
generates the pixels for the screen. The "read" is done
continuously so the picture looks steady. "Write" is done upon
receipt of a special signal.
KEYBOARD
I
ASCII
ASCII
R;f32.
To build the video-controller board we used a RAM, a character
generator and counters that are used as pointers/special
module counters. Monolithic Memories' PALs provide an excellent replacement for TTL counters. They can be programmed to
count in any desired mode. The PAL meets the requirements of
the standard TTL SSI/MSI of 25 nsec propagation delay while
reducing the chip count on the board. The PAL can generate
non-standard functions which are not available on standard
chips. By customizing the PAL to give only the functions that
are needed, the user can save board space. The following is a
detailed design of a video controller using Monolithic Memories
PALs.
* *
UART
RAM
WRITE ONLY PORT
CHARACTER
GENERATOR
r--Ts-
SHIFT
REGISTER
PIXEL
r+
VIDEO
RECEIVER
READ ONLY PORT
Figure 14. The RAM Divides tile Board Into Two Subsystems:
a) Write, Only Subsystem; From the Keyboard to the RAM.
b) Read Only Subsystem; From the RAM to the Video Receiver.
~
l
@£J
5
XTAL
DOTS OF
CHARACTERS
i
DOT
GENERATOR
VP1
DTCNT
3
ASCII CODE
CKOUT
D4
5
-
,
~
RAM
1
t
1
r
RAM
CONTROL
VP8
t
UEN
I
WE /
/1
SAMPLE
/1
9600x8 Ht
f..-.c-
L..,.
1
SCANNER/LINE
GENERATOR
VP3
,
UART
VP6
7
~
4 / 5
RS232
/
RXD
/1
+
ADDR
SCROL/LINES
GENERATOR
VP4
r--
CHARACTER
GENERATOR
7
LSB OF ADDR
M~~/
7
/1
1
CHARACTER/
CURSOR
GENERATOR
VP2
/
4
~
L...o..
BAUD RATE
GENERATOR
VP5
1
VIDEO 1
Figure 15. Block Diagram of the Video Controller
I
UART
CONTROL
VP7
READY
J
1
RXD
Video Controller
NOTES:
1. VP1 is a shift register for the dots in a dot-line of each character. "DTCNT" counts 8 dots for each character (PAL20X8).
2. VP2 generates the 5 least significant bits of the address to the RAM (PAL20X10): "CHAR", when reading from the RAM; "CURS", when writing into the RAM.
3. VP3 counts 12 dot-lines per 1 character-line and the number of lines in the whole screen (PAL20X10).
4. VP4 generates the 4 most significant bits of the address to the RAM (PAL20X10): "LINES", when reading from the RAM. "SCROL". when writing into the RAM.
5. VP5 generates the baud rate and the composite video signal (PAL20X8).
6. VP6 is a shift register. It loads the ASCII bits in serial form from the RXD line (PAL20X8).
7. VP7 generates the "SAMPLE" pulses. the "READY" signal when a code for a character is in the UART, and detects a false "START" signal (PAL20X10).
8. VP8 controls the RAM (PAL20X10).
9. Monolithic Memories' 6055 is used as a character generator.
10. Hitachi HM6116P: 2048 words x 8 bits high speed static CMOS RAM is used in our design.
5·11
Video. Controller
A
B
+5V
PAL20XB .' .. ~~
CKIN 1~
.1
-~_
1'-'------DO-I:~1J'H....:;..... II ~CKOUT
01:i
1..
1......._ _--::
.l.I3 H
1......._-'----"'OZ=-t:g:!l.H
I f:.!J.HAND
1'-____D3=1
,---===D4=i:fil;;'H ::R
HBLANK:;
~
, -_ _ _ _~r-------~S=C=AN~3i~'~
-+_________L~I~NE~4_~~II~
r -______
j
I
OSCIN:;
GATE
~RRA
, -_ _ _-==IN;;,IT;:S:.rn
"", H
Hr--"'::":'-="'''-Ill"H
:
CK
• *- ~:OOTO
• ~ fiJJ: OOT1
*-~:OOTZ
•
• ~ I;;t "DOT3
~Dc5i'i
II
: ~OTCNTO
~DTCNn
•
~OTCNn
• i<>" ~ OSCOUT
11
50~ ~ "-F-J~ffiiOc
,..
"""
~-----L
C
A~~
__~U~A=L
8 MHz
~
__~I'-
E
:.+SV .
.:'
HM6116P
A7
.:
ASr;
A4~
r;
AZr;
Al r;
AD r;
1/01 r;
IIoZ.1iii
.'
I
~
I,.-----------__:.::AS:.,""UJ,
A3
... ' .'
L!. ...:.--v-. m-1££J.
.
WAS,
ill
AS
j,lWE
;;.' OE
3
:iii
Al0
Ci
ill 1/08
iii
'iii
1/07
1108
1103. Iii
iii. 1105
GND~1li
:;;1 1104
.:~I!L,...-::-..:...f!I...;=:-:-I-i1-'"
,.. '.
,
+5V
G
H
:
.
-:.:-.
.
-'.
....
:.<.
--:
"'
.
K
L
.:.;
.::
5-12
-:=
,..
Video Controller'
~
A
B
+5V
6055
A7
I
AS::;:
A5;:;:
A4;:;:
A:I~
AOF,
5
I
A1 ::
A2~
i
..r:--'a
I
GNd_
I
-
I
I
I
.
-
~_VCC I
~~
~~
" 01
Iw
~-=---~02
rm 03
~04
1;;1 05
-=AS232
~r<
C
I
I
0
i
E
~
~
201m
F
-==K
L
COMPOSITE
.,.
VIDEO
SIGNAL
Video , Controner
Solder Side
•
•
•
•
5·114
.: • • • •
Video Controller
Component Side
5·t5
Video Controller
Video Controller Specifications
The Video controller provides a 16 line by 48 character display for use with
standard CRT monitors and televisions. The controller "listens" to standard
RS232C serial data via a 25 pin DB-25 plug/socket pair inserted into any
Computer/Terminal RS232C interface. The controller stores the serial data in
a 21.
Dl
~
21
~
~
20
~
"
"
"
"
~-9D-
"
"
"
"
~~D-
4
5
~
"
""
"
~D- ~- ~
~
.
~
~~D-
"
"
"
~-
7
-
....
~D-
'"
"
8
~9D-
..""
....... .-~
9
....
~D-
"
10
.
>.
~
~
18
P1
~
....
17
~
~
P1
~
....
-9D-ll1]
~..t1
"
"
"
"
....
~
-yo""'.....
11
-
U I
1
1
•
5
"
I
9 10 11
il 11 14 IS
16 11 11 It
20 21 21 2J
24 n U l l
21 29 n 31
12 JI M 35
36 11 11 It
14
Q
13
CHAR4
CURS4
CHAR3
Video Controller
5-32
SCAN/LINE Generator
PAL20X10
CHARs
2
CHAR4
3
CHAR3
4
CHAii2
5
INITS
6
H25s
WRiTE
7
8
TSVNc
9
CHAR1
CHARO 11
SCANl
SCAN2
u..r.-::LlJ~ 17
SCAN3
Video Controller
PAL20X10
PAL DESIGN SPECIFICATION
VP3
BIRKNER/UDI
7/13/81
SCAN/LINE GENERATOR
MMI SUNNYVALE, CALIFORNIA
CK /CHARS /CHAR4 /CHAR3 /CHAR2 /INITS /H255 /WRITE /TSYNC /CHARl /CHARO GND
/oe /LINE4 /LINE3 /SYNC /SCAN3 SCAN2 SCAN1 SCANO /LINE2 /LINE1 /LINEO vec
/SCANO
:= INITS
+ /INITS*/SCANO
:+:/INITS*H255
1INITIALIZE
1HOLD
1INCREMENT
/SCAN1
:= INITS
+ /INITS*/SCAN1
:+:/INITS*H255*SCANO
1INITIALIZE
1HOLD
1INCREMENT
/SCAN2
:= INITS
+ /INITS*/SCAN2
:+:/INITS*H255*SCANO*SCAN1*/SCAN3
1INITIALIZE
1HOLD
1INC IN. MODULUS 12
SCAN3
:= /INITS*SCAN3
+ /INITS*H255*LINE4*LINE2*LINEO
*SCAN2*SCAN1*SCANO
:+:/INITS*H255*SCANO*SCAN1*SCAN2
+ /INITS*H255*SCAN3*SCAN1*SCANO
LINEO
:= /INITS*LINEO
+ /TSYNC
:+:/INITS*H255*SCAN3*SCAN1*SCANO
+ /INITS*H255*LINE4*LINE2*LINEO
*SCAN2*SCAN1*SCANO
1HOLD
1DETECT SCAN LINE 2~O
1FOR VERTICAL RETRACE
1INCREMENT
1MODULE 12 CORRECTION
1INITIAL WHEN INITS=H
1HOLD
1TEST SYNC
1INCREMENT
1DETECT LINE 21 7/12
1FOR VERTICAL RETRACE
LINE1
:= /INITS*LINE1
+ /TSYNC
:+:/INITS*H255*SCAN3*SCAN1*SCANO*LINEO
1HOLD
1TEST SYNC
1INCREMENT
LINE2
:= /INITS*LINE2
+ /INITS*LINE2
:+:/INITS*H255*SCAN3*SCAN1*SCANO*LINEO*LINE1
+ /INITS*H255*LINE4*LINE2*LINEO
*SCAN2*SCAN1*SCANO
LINE3
LINE4
SYNC
5·34
:= /INITS*LINE3
+ /INITS*LINE3
:+:/INITS*H255*SCAN3*SCAN1*SCANO
*LINE2*LINE1*LINEO
:= /INITS*LINE4
+ /TSYNC
:+:/INITS*H255*SCAN3*SCAN1*SCANO
*LINE3*LINE2*LINE1*LINEO
+ /INITS*H255*LINE4*LINE2*LINEO
*SCAN2*SCAN1*SCANO
:=
+
:+:
1 HOLD
1EXTEND
1INCREMENT
1DETECT LINE 21 7/12
1FOR VERTICAL RETRACE
1HOLD
1EXTEND
1 INCREMENT
1HOLD
1TEST SYNC
1INCREMENT
1DETECT LINE 21 7/12
1FOR VERTICAL RETRACE
CHAR5*CHAR4*/CHAR3*CHAR2*/WRITE
1CHAR 52-55 HORIZ SYNC
LINEO *LINE1*/LINE2 *LINE4 */SCAN2 */SCAN3 * SYNC 1VERTICAL SYNC
LINEO*LINE1*/LINE2*LINE4*/SCAN2*/SCAN3*SYNC1WHEN LINE=19 SCAN 0-3
*CHARS*CHAR4*/CHAR3*/CHAR2
1AND CHAR 48-51
Video 'Controller
FUNCTION TABLE
CK
loe
CHARS CHAR4 CHARJ CHAR2 CHAR! CHARO TSYNC INITS H255 WRITE
LINE4 LINE3 LINE2 LINE1 LINEO,SYNC SCAN3 SCAN2 SCAN1 SCANO
C CHAR
K 543210
T I
S N
y I
N T
C S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
H
H
H
a
a
a
H
a
a
a
H
a
H
H
a
a
a
L
a
H
a
H
a
H
W
H
2
5
5
S
R
y
I I
LINE N SCAN
T 0
E C 43210 C 3210
COMMENTS
X
H
H
a
a
H
a
a
a
a
a
a
H
a
a
a
X L LLLLL
X L LLLLL
X L LLLLL
x L LLLLL
x L LLLLL
X L LLLLL
x L LLLLL
x L LLLLL
x L LLLLL
x L LLLLL
x L LLLLL
x L LLLLL
X L LLLLa
x L LLLLH
x L LLLLH
x L LLLLH
x L LLLLL
X L HLLHH
X L HLLHH
x L HLLHH
X L HLLHH
x L aLLHH
x L HLLHH
L L XXXXX
INITIALIZE COUNTERS
INC SCAN
INC SYNC
INC SYNC
INC SCAN
INC sCAN
INC SCAN
INC SCAN
INC SCAN
INC SCAN
INC 'SCAN
INC SCAN
INC LINE, INC SCAN MODULE 12
LINE = 1, INC SCAN
LINE = 1, INC SCAN
LINE = 1, INC SCAN
INITIALIZE COUNTERS
LINE .. 19, FOR TESTING VERTIC SYNC
VERTICAL SYNC
VERTICAL SYNC
VERTICAL SYNC
INC SCAN
INC SCAN
HORIZONTAL SYNC
------------------------------------------------------------------------XXXXXX
XXXXXX
XXXXXX
XXX XXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
HHLLXX
HHLLXX
HHLLXX
HHLLXX
HHLLXX
HHLLXX
HHLHXX
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
a
L
L
L
L
L
L
L
x
L
H
a
H
a
a
L
X
X
X
X
X
X
X
X
X
X
X
X
x
LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHL
LHHH
HLLL
HLLa
HLHL
HLHH
LLLL
LLLH
LLHL
LLHH
LLLL
LLLL
LLLH
LLHL
LLHH
LHLL
X
X
X
X
L
L
L
L
L
L LHLH
H XXXX
-----------------------------------------------------------------------------
$ .. 35
Video Controller
DESCRIPTION
EACH CHARACTER ON THE SCREEN CONSISTS OF 12 DOT LINES: 7 LINES FOR THE
CHARACTER AND 5 LINES FOR SPACE BETWEEN CHARACTER'S. THE FOLLOWING FIGURE
SHOWS THE LETTER nUn AND THE SPACE WITH ALL THE PIXELS AROUND IT AS IT IS
DISPLAYED BY THE VIDEO CONTROLLER.
7
CHAR
LINES
x
x
x
x
x
x
x
xxx
xxx
x x ~X
xxx
xx x
~
5
BLANK
LINES
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
~
CHARACTER PIXEL
X SPACE PIXEL
BLANK PIXEL
X>X
xx
xx
xx
"SCAN" IS A MODULE 12 COUNTER THAT COUNTS TRE NUMBER OF THE DOT LINES FOR
EACH CHARACTER.
"LINE" COUNTS THE NUMBER OF THE CHARACTER LINES. EACH CHARACTER LINE IS
12 SCAN LINES. THE COUNTER COUNTS UNTIL 21 ALTHOUGH ONLY 16 LINES ARE
VISIBLE ON THE SCREEN.
THE HORIZONTAL SYNC PULSES ARE GIVEN IN EVERY SCANNED LINE BETWEEN
CHAR 52 AND 55. THE VERTICAL SYNC PULSE IS GIVEN WHEN THE LINE COUNT IS 19,
SCAN IS BE'lWEEN 0 AND 3, AND CHAR IS BETWEEN 48 AND 51.
THE NEXT FIGURE SHOWS THE SCREEN WITH THE CORRESPONDING LINE AND CHAR
COUNTERS, AND THE SYNC PULSES.
HORIZONTAL
SYNC PULSE
LINE
~~rrrr77777777~~~~~~rr-----20
~~~~~~~~~~~""~.------19
~CHAR
= 48-51
VERTICAL SYNC
5-36
Video Controller
Vertical Sync
I
LINE 18
- - - - - - ( 1 2 SCAN L I N E S ) - - - - - - - - - I * " > - - - - - - - - - - - - - L I N E 1 9 - - - - - - - - - - - - - . . j .
I
SCAN
: 8
SCAN
SCAN
SCAN
SCAN
: 9
: 10
: 11
: 0
(52,55)
(52,55)
CHAR
0
630
(52,55)
630
630
16
1~.I-----VISIBLE-----;...1
LINES
(52,55)
SCAN
: 1
SCAN
SCAN
: 2
: 3
SCAN
: 4
I
SCAN
: 5
I
(51)
630
630
5 11/12 BLACK
LINES
o
LINE
o
16 17
19~01
19
21.8/12
1 PERIOD
21 8112 LINES
12 dot-lines generate one-character line. The total number of scanned lines is 260 or 21 8/12 character-lines. Out of the 21 8/12
character lines only 16 lines are visible. The vertical sync pulse is asserted during Line 19.
5-37
Video Controller
Horizontal Sync
I~..
_--------ONE
L I N E - - - - - - - - + - I__- - - - - - - N E X T
LINE-'---------t~
j-._ _ _ CHA~~~~E: s~~~~~YED---+t--
CHAR 0
4748
I
(52,55)
I·
630
4748
1 PERIOD
H255 ~ 512 PULsES
I
{52, 55)
630
~I
One character is represented in 8 pulses. Then the 512 pulses cause "CHAR" to count from 0 to 63. Out of the 64 characters only 48
characters are visible on the screen. The horizontal sync pulse is asserted during "CHAR" position 52 through and including "CHAR" 55.
5·38
Video Controller
SCAN/LINE GENERATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CXXXXOXXOXXXOHHXHLLLBHHI
CXXXXI0XOXXXOHHXHLLBHHHI
CXXXXI0XOXXXOHHXHLHLHHHI
CXXXXI0XOXXXOHHXHLBHHHHI
CXXXXI0XOXXXOHHXHHLLHHHI
CXXXXI0XOXXXQHHXHHLBHHHI
CXXXXI0XOXXXOHHXBHHLBHHI
CXXXXI0XOXXXOHHXHHHHHHHI
CXXXXI0XOXXXOHHXLLLLHHHI
CXXXXI0XOXXXOHHXLLLBHHHI
CXXXXI0XOXXXOHHXLLHLBHHI
CXXXXI0XOXXXOHHXLLHHHHHI
CXXXXI0XOXXXOHHXHLLLHHLI
CXXXXI0XOXXXOHHXHLLHHaLl
CXXXXI0XOXXXOHHXHLHLHHLI
CXXXXI0XOXXXOHHXHLHHHHLI
CXXXXOXXOXXXOHHXHLLLBHHI
COOIIIIXIXXXOLBHHLLLHLLI
COOIII0XOXXXOLHHHLLHHLLI
COOIII0XOXXXOLHHHLHLHLLI
COOIII0XOXXXOLBHHLBHHLLI
COOIII0XOXXXOLHHHHLLHLLI
COOIII0XOXXXOLHHHHLHHLLI
COOI0III0XXXOXXtXxxXXXXI .
PASS SIMULATION
Video Controller
SCAN/LINE GENERATOR
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
x--x------ --x- x-x- -x-- ---x ------x --x- x-x- -xxx------ ---x ------- ---x----x- x-x- -x-- ---x ------x ----
0 ---x ---1 ---- ---2 ---- ---3 ---x ---8
9
10
16 ---17 ---18 ---x
19 ---x
---x
/INITS*LINE1
/TSYNC
/INITS*H255*SCAN3*SCAN1-
---- ---x ---- x---
---- ---x ---- x---
---x ---- --x- x-x- -x-- ---x
---- ---x --x- x-x- -xx-
/INITS*LINEO
/TSYNC
/INITS*H255 * SCAN3 * SCAN1/INITS*H255*LINE4*LINE2-
---x
/INITS*LINE2
/INITS*LINE2
/INITS*H255*SCAN3*SCAN1/INITS*H255*LINE4*LINE2-
24
25
26
-x----x x--x--- -x--
INITS
/INITS*/SCANO
/INITS*H255
32
33
34
-x-x--x
--x- x--- -x--
INITS
/INITS*/SCAN1
/INITS*H255*SCANO
40
41
42
-x-x--- ---x
--x- x-x- -x-- --x-
INITS
/INITS*/SCAN2
/INITS*H255*SCANO*SCANl-
x---
48
49 ---x
50
51
---x --x- x-x- -xx-
---x
56
57
58
--x- X-X- -XX--x- x-x- -x-- ---x
x---x-- -x-- x--- -x----x --x- ---x
---x ---x --x.,.
-x-x -x-x x-x- x-----x --x- ---x
64
65
66
x-----x ---x ---x --x- x-x- -x-- ---x
72
---- ---- x------ ----
73
74
75
---- ---- x---
---x ---x ---x --x- x-x- -x-- ---x
x---
--x ---- ---x --x- x-x- -xx-
LEGEND:
X :
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
5·40
= 1222
-
---x
/INITS*SCAN3
/INITS*H255*LINE4*LINE2/INITS*H255 *SCANO *SCAN1/INITS*H255*SCAN3*SCAN1-
---x
---x
CHAR5*CHAR4*/CHAR3*CHARLlNEO*LINE1*/LINE2*LlNELINEO*LINE1*/LINE2*LINE-
---x ------x
/INITS*LINE3
/INITS*LINE3
/INITS*H255 *SCAN3 *SCAN1-
---x
/INITS*LINE4
/TSYNC
/INITS*H255 *SCAN3 *SCAN1/INITS*H255*LINE4*LINE2-
---x ------- ---x
: FUSE BLOWN
(H,P,l)
Video Controller
Logic Diagram PAL20X10
SCAN/LINE Generator
CK
1
.......
.,,
011
J
4!,
1
111011
12131415
li17111i
202122 13
24 n1621
2121)0)1
323]34
n
J6113139
~~~ ~~
,
CHAR5
~
,
,
'""
~~D-
3
..
~
;:::
"
"
"
......
D-
~
4
~
n
"
"
""
~-OD-
""
.~.~D-
5
"
6
..
,
"
"
....
~~D-
7
~-
'"
"
WRITE
~-
!...
~::?D-
I
9
..
~D-
."
"
CHAR1
10
~
~-
22
21
~
...
~
19
V
~
~18
~
~
17
~
~
16
~-
"
"
"
"
TSYNC
fll
~-
~::?D....
"
H255
t1l
~-
"
...
r.:J.
V
~
CHAR2
~
23
n
'"-;:L
....
15
~(
~S»lDl ~
"
""
"
'-'
11
.~'61
191011
12ll14U
16111111
1011112]
1'151$11
11 2930Jl
11Jl341~
SCAN1
SCAN2m
LINE3
L1NE4
Q
~
DIll
SCANO
;
.
...A.
~
13
36HlIl~
5~41
Video Controller
5-42
LINES/SCROL Generator
PAL20X10
vee
OE
iNifS
LlNES3
L.1.I.c=.... _ • •••
SciiOr3
iJNES2
SCiiOL2
5-43
Video Controller
PAL20X10
PAL DES~~ SPECIFI~TIO~
VP4
BIRKNER/UDI
7/14/81
LINES/SCROL GENERATOR
MMI SUNNYVALE, CALIFORNIA
CK /SWAP
SCANO
SCAN1 /INIT
/SCAN3
/H2SS
NC
/WRITE /LINE4
/INCSCR GND /oe
/SCROLO /LINESO /SCROL1 /LINES1 /SCROL2 /LINES2 /SCROL3
/LINES3 /INITS JOE vec
LINESO
:=
/SWAP* /INITS*LINESO
+
SWAP*/INITS*SCROLO
:+: /SWAP*/INITS*H2SS*/LINE4
+
SCROLO
:=
~ SCAN3*SCAN1*SCANO
/SWAP* /INtTS'*INCsCR
/SWAP* /INITS*SCROLO
+
SWAP*/INITS*LINESO
:+: /SWAP*/INITS*INCSCR
+
LINES1
INITS
/SWAP*/INITS*LINES1
SWAP*/INITS*SCROLl
:+: /SWAP*/INITS*H255*/LINE4
• SCAN.3:1rSCAN1 *SCANO*LINESO
+ /SWAP*/INITS*INCSCR*LINESO
:=
+
SCROLl
47)
'!lOLD
,SWAP WITH SCOOL
, INC (12 DOT LINES)
,INC (LF)
:=' /SWAP*/INITS*LINES2
,HOLD
, SWAP WITH SCROL
,INC (12 DOT LINES)
SWAP*/INITS*SCROL2
: +: /SWAP* /INITS*H255 */LINE4
. * SCAN3*SCAN1*SCANO
*LINES1*LINESO'
+ /SWAP*/INITS*INCSCR
*LINES1*LINESO
SCROL2
: = /SWAP* /INITS*SCROL2
+ SWAP*/INITS*LINES2
:+: /SWAP*/INITS*INCSCR*SCROLO*SCROL1
+
INITS
LINES 3
:=
/SWAP*/INITS*LINES3
+
SWAP*/INITS*SCROL3
:+: /SWAP*/INITS*H255*/LINE4
* SCAN3*SCAN1*SCANO
*LINES2*LINES1*LINESO
+ /SWAP*/INITS*INCSCR
*LINES2*LINES1*LINESO
:=
/SWAP*/INITS*SCROL3
+
SWAP*/INITS*LINES3
:+: /SWAP*/INITS*INCSCR
*SCROL2*SCROL1*SCROLO
INITS
+
INITS
:=
OE
.=
5-44
,HOLD
,SWAP WITH LINES
, INC (LF OR CHAR
,INITIALIZE
,HOLD
, SWAP WITH LINES
7.INC (LF OR CHAR = 47)
iINITIALIZE
+
SCROL3
, INC (LF)
/SWAP* /INITS* SCROLl
SWAP*/INITS*LINES1
: +: /SWAP* /INITS*INCSCR*SCROLO
+
: INITS
:=
+
LINES 2
,HOLD
, SWAP WITH SCROL
,INC (12 DOT LINES)
INIT*H255
/WRITE
, INC (LF)
,HOLD
, SWAP WITH LINES
,INC (LF OR CHAR = 47)
,INITIALIZE
,HOLD
, SWAP WITH SCROL
,INC (12 DOT LINES)
, INC (LF)
,HOLD
, SWAP WITH LINES
,INC (LF OR CHAR = 47)
,INITIALIZE
;INITIALIZATION SIGNAL
; ENABLE THREE STATE OF RAM
Video Controller
FUNCTION TABLE
CX
SWA.P
SCAN3 SCANl SCANO INIT
8255
WRITE LIN24 INCSCR
SCROL3 SCROL2 SCROLl SCROLO LINES3 LINBS2 LINESl LINElSO INITS
OE
loe
I
W L N
I
N
S
I 8 R I C
I
W
N 2 I N S I
C A SCAN I 5 T E C 0 SCJtOL LINElS· '1' 0
K P . 310 T 5: E 4" R C
,. 3210 3210 S E COMMENTS
------.-~---.--------~-.~~--~----~.----~---------.-~---~---~-~---~---~.---SET INITIALIZE BIT
XXXX 8 X
C x
XXX 8 H X X X L
XXXX
INITIALIZE COON~
XXX L X X x X L
C X
HHHH
t.LLL L X
LLLL L II: INITS • L
C L
XXX L L X X L L
HHHH
LLLH L X INC LINES, HOLO seROL
C L
HHH L 8 X L L L
HHHH
C L
HBH L If x L L L
HBHH
LLRI. L x JNC LlNElS, 80LO SCROL
HBHH
LLHH L X INC LlNES , SCAN • 11
C L
HBH L H X L. L L
lNC LINES, SCAN .. 11
HBHH
C L
LHLL L X
HHH L H X L L L
INC LINES & SCJtOL: LF
LLLL
LHLH L X
C L
XXX L H X X H L
C L
LUJI
L X X X H L
LBHL L X INC LINES & SCJtOL: LF
xxx L L X X t; L LtL!! LHHL L X HOLO· LINES & SCJtOL
C L
C H
xxx L L X X L L LHH'I. LLLH L X SWU LINES & SCJtOL
xxx L X X X 8 L LHBH LLHL L X INC LINES & SCJtOL
C L
C X
xxx x x L X X L XXXX XXXX X H SET OE
x X H X X L XXXX xxxx X L CLEAR OJ!:
C X
xxx
xxx
..----------~----
-----------------------------------~----------~---~~---~-DESCRIPTION
"SCROL" AND "LINES" ARE COQ'N'l'EM AND PoINTEIU3 TO TaE RAM. "LINES" IS A
POINTER TO THE LINE THAT z,s lU!lAD PROM 'rD. RAM. "SCROL" IS A POINTER
TO THE LOCATION IN TBE RAM W!!ERE A NEW LINE CAN BE STORED. BOTa OF THEM
COUNT UP TO A MAXIHOM OF 16 LIm:s.
THE BIT "SWAP" ENAIlLES THE 'tWO COUNTERS TO TALK TO 'l1!!l SAME ADDRESS LINES
OF THE RAM.
"
.~,
THE NEXT FIGURE SHOWS ALl. THE POINTERS THAT HAW BEEN DESCRIBED.
"W" MEANS WRITlt«; IN'l'O TBE RAM, WRit MlJ;ANS RPDING FROM THE RAM AND "C"
IS A TEMPORUY POlNTER.
$
LINE
C
CURS
W
...,o--TiMPCOUNTliR
SCRd ..
wi
LINiS
R
OTCNT R
CHAR
R
I
- - . , COUNTERS FOR THE FlAM
} -COUNTEFIS FOR THE SCFlEEN
5 ..45
Video;: Controller
+5V
lOOk!!
PAL
INIT
2OX10, .
t-~~"""··INITS
H255
R·e = .lOOk!! • 1 Mf =. 0.1
l
'i:,
vee
sec ...
",I."
. ,Initialization of the system when pqwer (+5V) Is turned on..
~_~ _ _ _._....: _ _ ~
_ _ _ _ -:--'-....: _ _
.1
.
....
....
r .'
:.
"c.
o ____________
•
-L~
:h
••.
.
I · :."
______________~--------~~----~~~~--1
1
•...,
.·1
"I
; ".I:'
elK
0
:"!
INIT
3
1.2
I
0
0.1 sec
3
\
INITS
0
~.5
it .
I;
3
H255
0
~.:
'
n
Video Controller
LINFS/SCROL GENERATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CXXXOXOXXXXXOXXXXXXXXLXl
CXXXIXXXXXXXOLHLHLHLHHXl
CIXXlXIXXXIXOLHLHLHLHHXI
CIIII00XXIIXOLLLHLHLHHXl
CIIII00XXIIXOLHLLLHLHHXl
CIIII00XXIIXOLLLLLHLHHXl
CIIII00XXIIXOLHLHLLLHEXl
CIXXIXOXXXOXOHLHHHLHHHXI
CIXXIXXXXXOXOLHHLHLHHHXI
CIXXIXIXXXIXOLHHLHLHHHXI
COXXIXIXXXIXOHLLHLHHHHXI
CIXXIXXXXXOXOLHLLLHHHHXI
CXXXXXXXIXXXOXXXXXXXXXLI
CXXXXXXXOXXXOXXXXXXXXXHI
PASS SIMULATION
5-47
Video Controller
LINES/SCROL GENERATOR
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
x---
0
-x--
8
/WRITE
-x--
INIT*H255
16
17
18
19
x---x-x--x---
24
25
26
27
x--- --x---x
-x-- --x- ---x ---x--- --x---x ----
32
33
34
35
x---x-x--x---
40
41
42
43
56
57
58
59
x--- --x---x
-x-- --x---x
x--- --x---x ---- -x-x
---x ---x--- -x---x
-x-- --x---x ---x--- x-x- x--- ---- ,..x-- -x-x--x
x--- --x---- ---x -x-x--- --x---x ----x-- --x---x
x--- --x-x-x
---x
/SWAP*/INITS*SCROLI
SWAP*/INITS*LlNESl
/SWAP*/INITS*INCSCR*SCRINITS
64
65
66
67
x---x-x--x---
/SWAP*/INITS*LlNESO
SWAP*/INITS*SCROLO
/SWAP*/INITS*H255*/LlNE/SWAP*/INITS*INCSCR
72
x--- --x-x-- --xx--- --x---x ----
48
49
50
51
73
74
75
LEGEND:
-x- ---x -----x---x
x-x- x---x-x -x-- ---x
--x---x
---x
-x- -----xx-x- x----x-
x--x ------x -x--
---x
-x-- -x--
x-----x
---- ----
----
FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
5·48
---x ---- ---x ---- -x-x
---x ------x
-x-- -x-- ---x
---x
-x--xx-x- x----x-
X :
x--x ------x -x--
= 1235
---x
-x----x
-x--
---- ---- ----
-
: FUSE BLOWN
/SWAP*/INITS*LINES3
SWAP*/INITS*SCROL3
/SWAP*/INITS*H255*/LlNE/SWAP*/INITS*INCSCR*LIN/SWAP*/INITS*SCROL3
SWAP*/INITS*LINES3
/SWAP*/INITS*INCSCR*SCRINITS
/SWAP*/INITS*LlNES2
SWAP*/INITS*SCROL2
/SWAP*/INITS*H255*/LlNE/SWAP*/INITS*INCSCR*LIN/SWAP*/INITS*SCROL2
SWAP*/INITS*LINES2
/SWAP*/INITS*INCSCR*SCRINITS
/SWAP*/INITS*LINESI
SWAP*/INITS*SCROLI
/SWAP*/INITS*H255*/LlNE/SWAP*/INITS*INCSCR*LIN-
/SWAP*/INITS*SCROLO
SWAP*/INITS*LINESO
/SWAP*/INITS*INCSCR
INITS
(H,P,l)
Video Controller
LlNES/SCROL Generator
CK
....
....
1
012
J
4
~
6
1
B 91011
12131415
Logic Diagram PAL20X10
161/1119
2021222]
U 251& II
2129]0]1
12 II
)I
l~
]6313139
""?D :GI]~
",
,
,
2
~-
--
~
,
.
~~D
'"
"
SCANO
4
I;J.
20
-
....
~~D
,....
,,~
~
...
tB»
~
~""9D
-~
~
"
"
"
6
....
"
"
7
" . .9[>
....
I;J.
~
'""'-t30
--~D
~
-'""'--
'"
"
...
19
18
17
~-
8
"
"
""
WRITE
21
19D
5
NC
-- ~
~
--
~~D
"
"
""
H255
22
-'""'
"
"
"
SCAN3
Dl
~
3
..
SCAN1
23
I
16
n--L
9
" . .9 D
....
..
J-L
~
-
"
~
,....-
riJ.
-yv-
Pl &
::9>tD] ~
"
"
"
"
~
11
0111
'~Ii
1
I ! fDII
Ulllt,!>
Ullll!!
2D212213
1(2!>lfiZl
1'1']831
311lMn
"
15
14
~
JiJIlIl'
5-49
Video' Controller
5-50
Composite Video/Baud
Rate Generator
PAL20X10
VCC
VIDEO
NC
NC
iiAUDo
BAUD1
INT
7
BAuD2
WRiTe
8
BAUD3
DTCNTD
9
ii'i'C'Ni'1
i5TCN'i'2
11
5~51
Video Controller
PAL20X8
PAL DESIGN SPECIFICATION
VP5
BIRKNER/KAZMI/UDI 7/14/81
COMPOSITE VIDEO/BAUD RATE GENERATOR
MMI SUNNYVALE, CALIFORNIA
CK /DOT4 /SYNC
NC NC NC
INT /WRITE /DTCNTO /DTCNT1 /DTCNT2 GND
/oe /SYNOUT /UEN /9600XS /BAUD3 /BAUD2 /BAUD1 /BAUDO' NC NC VIDEO vec
IF ( SYNC)
SYNOUT = SYNC
IF ( /OOT4 ) /VIDEO
= /DOT4
;SYNC PULSE
;PIXEL TO THE SCREEN
9600XS := INT
+ BAUD3*BAUD2*DTCNT2*DTCNTl*/DTCNTO
;TO INITIALIZE COUNTER BAUD
;104/S = 13, MODULE 102
;COUNTS 103 = 12 6/8
BAUDO := /9600X8*BAUDO
+ /9600X8*BAUDO
:+:/9600X8*DTCNT2*DTCNTl*DTCNTO
; HOLD
; EXTEND
; INC
BAUDI := /9600XS*BAUDI
+ /9600X8*BAUDI
:+:/9600X8*DTCNT2*DTCNTl*DTCNTO*BAUDO
: HOLD
; EXTEND
BAUD2 := /9600X8*BAUD2
+ /9600X8*BAUD2
:+:/9600X8*DTCNT2*DTCNTl*DTCN'l'0
*BAUDl*BAUDO
; HOLD
; EXTEND
; INC
; INC
BAUD3 := /9600X8*BAUD3
+ /9600X8*BAUD3
:+:/9600X8*DTCNT2*DTCNTl*DTCNTO
*BAUD 2*BAUDI *BAUDO
; HOLO
UEN
;DTCNT
;DTCNT
:= WRITE*/DTCNT2*DTCNTI
+ WRITE* DTCNT2*/DTCNTl*/DTCNTO
; EXTEND
; INC
= 2,3
=4
Video Controller
FUNCTION TABLE
CK DOT4 SYNC INT WRITE DTCNT2 DTCNTI DTCNTO loe SYNOUT UEN
9600X8 BAUD3 BAUD2 BAUDI BAUDO VIDEO
D S
o Y I
S
Y
9
W
6
V
R
I
N
IOU
0
0
I
D
DTCNT
210
E
N
U E
T N
X BAUD
8 3210
E
0
COMMENTS
XXX
XXX
XXX
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CHECK SYNOUT FOR H
CHECK SYNOUT FOR L
VIDEO = L
VIDEO = H
SET 9600X8
INITIALIZE BAUD COUNTER
INC BAUD
INC BAUD
INC BAUD
INC BAUD
HOLD BAUD: DTCNT NEQ HHH
INC BAUD
INC BAUD
INC BAUD
INC BAUD
INC BAUD
INC BAUD
INC BAUD
INC BAUD
HOLD BAUD
HOLD BAUD
HOLD BAUD, SET UEN
HOLD BAUD, SET UEN
HOLD BAUD, SET UEN
HOLD BAUD
SET 9600X8, HOLD BAUD
INITIALIZE BAUD
C T
K 4
N N T
C T E
L
L
L
L
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
x
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
xxx
LLL
LLL
HHH
HHH
HHH
HHH
HLH
HHH
HHH
HHH
HHH
HHH
HHH
HHH
HHH
LtL
LLH
LHL
LHH
HLL
HLH
HHL
HHH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
L
L
L
XXXX
XXXX
XXXX
XXXX
XXXX
LLL!·
LLLH
LLHL
LLHH
LHLL
LHLL
LHLH
LHHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLL
HHLL
HHLL
HHLL
HHLL
HHLL
HHLL
LLLL
5-53
Video Controller
DESCRIPTION
THIS PAL GENERATES THE BAUD RATE, THE VIDEO AND THE SYNC SIGNALS WHICH ARE
COMBINED AT THE OUTPUTS TO FORM THE COMPOSITE VIDEO SIGNAL, AND THE "UEN"
SIGNAL WHICH ENABLE THE "UART".
EVERY CHARACTER CONSISTS OF 10 BITS: 1 START BIT, 7 ASCII CODE BITS, 1
PARITY BIT, AND 1 STOP BIT. THE CHARACTER RATE IS 9600 Hz. EACH BIT IS
DIVIDED INTO 8 SMALL BITS SO THE NUMBER OF BITS PER SECOND REQUIRED
FOR OUR SYSTEM IS 9600*8 = 76800 OR 76800 Hz.
I
! . - - - T = 9600 H z - - - - '
I
T = 1/76800 = 13 MICROSECOND
THE CLOCK FREQUENCY IS 8000000 Hz.
WE NEED TO DIVIDE THE CLOCK FREQUENCY BY 104 TO GENERATE A FREQUENCY
OF 76800 Hz.
8000000/76800
=
104
= 13*8
"DTCNT" COUNTS 8, AND "BAUD" COUNTS 13. TO GET 104 COUNTS WE NEED TO
COUNT FROM 0 TO 103. BECAUSE THERE IS ONE CLOCK CYCLE DELAY UNTIL THE
DATA IS AVAILABLE ON THE OUTPUT PINS (REGISTERED PAL), MODULE 104 IS
DETECTED BY COUNT 102 WHICH IS EQUAL TO 102/8 = 12 6/8.
+5V
15011
SYNC
COMPOSITE
VIDEO
lan
75n
DOT4
VIDEO
VIDEO CONTROLLER
_1_6_ . 4.6
150 + 16
=
_75_. 5
150 + 75
1.66V
=
0.49V
When SYNC = H the output is at O.4V.
5·54
TV
Video Controller
DIGITAL TO ANALOG CONVERTER
SYNOUT
VIDEO
COMPOSITE
VIDEO
L
L
1.7V
L
H
O.9V
O.4V
O.4V
H
L
H
H
1.7Y--~--------WHITE REFERENCE
O.9Y-O.4Y-----
GRAY
TONES
--BLACK REFERENCE
---SYNC PULSE
COMPOSITE YIDEO SIGNAL
COMPOSITE VIDEO/BACD RATE GENERATOR
1
2
3
4
5
6
7
8
9
10
i1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
oXOXXXXXXXXXOLXXXXXXXXX1
OX1XXXXXXXXX01XXXXXXXXX1
01XXXXXXXXXXOXXXXXXXXXL1
00XXXXXXXXXXOXXXXXXXXXl1
CXXXXX1X111XOXXLXXXXXXX1
CXXXXXOX111XOXXHHHBHXXX1
CXXXXXOXOOOXOXXBHBHLXXX1
CXXXXXOXOOOXOXXBHHLRXXX1
CXXXXXOXOOOXOXXBHHLLXXX1
CXXXXXOXOOOXOXXBBLBHXXX1
CXXXXXOX010XOXXHHLBHXXX1
CXXXXXOXOOOXOXXHHLHLXXX1
CXXXXXOXOOOXOXXBBLLHXXXl
CXXXXXOXOOOXOXXBHLLLXXX1
CXXXXXOXOOOXOXXHLHHRXXX1
CXXXXXOXOOOXOXXHLHHLXXX1
CXXXXXOXOOOXOXXHLBLHXXX1
CXXXXXOXOOOXOXXBLB~XXX1
CXXXXXOXOOOXOXXHLLHHXXX1
CXXXXX00111XOXBBLLBBXXXl
CXXXXX00011XOXBBLLHHXXX1
CXXXXX00101XOXLHLLHHXXX1
CXXXXX00001XOXLHLLHHXXX1
CXXXXX00110XOXLHLLHHXXX1
CXXXXX00010XOXBBLLBBXXx1
CXXXXX00100XOXHLLLHHXXX1
cxxxXXOOOOOXOXBBBHHHXXX1
PASS SIMULATION
5·55
Video Controller
COMPOSITE VIDEO/BAUD RATE GENERATOR
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
o x--- ---- ---- ---- ---- ---- ------- ---x--- ---- ---- ---- ---- ---- ---- ---- ---- ----
1
24
25
26
---x ---- ---- ---- --x- ---- ------x ---- -----x------- ----XX- -x-- -x--
/DOT4
/DOT4
/9600X8*BAUDO
/9600X8*BAUDO
/9600X8*DTCNT2*DTCNT1*D-
32
33
34
---- ------x ---- ---- --x---- ------x ---- ---- --x---- ---- ---x ---- ---- ---- -xx- -x--
/9600X8*BAUDl
/9600X8*BAUDl
-X-- /9600X8*DTCNT2*DTCNT1*D-
40
41
42
---- ---- ---- ---- ---x ---- --X- ------- ---- ---- ---- ---x ---- --X- ------- ---- ---x ---x ---- ---- -xx- -x--
---- /9600X8*BAUD2
---- /9600X8*BAUD2
-X-- /9600X8*DTCNT2*DTCNT1*D-
48
49
50
---- ---- ---- ---- ---- ---x --x- ---- ------- ---- ---- ---- ---- ---x --x- ---- ------- ---x ---x ---x ---- -xx- -X-- -X--
56
57
---- ---- ---- X--- ----
64
65
---- ---- ---- ---- -X-- ----
72
-X-- ---- ---- ---- ---- ---- ----X-- ---- ---- ---- ---- ---- ----
73
LEGEND:
---- ---- ---- ---x ---x
INT
X--- -X-- -X-- BAUD3*BAUD2*DTCNT2*DTCN-
---- ---- ---- ---- -x-- x---
X: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
=
745
/9600X8*BAUD3
/9600X8*BAUD3
/9600X8*DTCNT2*DTCNT1*D-
-x--
X--- WRITE*/DTCNT2*DTCNTl
X--- -X-- WRITE*DTCNT2*/DTCNT1*/D-
- • FUSE BLOWN
SYNC
SYNC
(H,P,l)
Video Controller
Composite Video/Baud Rate Generator
CK
1
".
......
~
,
2 J
•
~
6
1
•
t
1011
n 13 14 IS
1611111!1
102112 2l
2'251621
Logic Diagram PALJOX 8
!lUlO)!
12 lllol U
Jill)'l'
'"'
,
,
,
~
,
,
.
m>9
- D
~~
-
MC
;~D
NC
--
4
.-.--
"
""
"
-R~D
""
"
"
~.-9D
5
~
6_
Q
IDD
"
"
"
INIT
VtHO
-A
"
"
"
"
NC
J
~
3
NC
23
~
"
NC
.J.
~
-
7
....,. ........
....
~~D
""
8
~
I.l.
21
~
Q.
......
20
~
I;l,
19
~
~
18
~
I;l,
17
I.:l...
16
~-=?D
""
......
""
"
"
rv-
...
......
~
t;L
ID~
-
L-
"
".
15
......
"
10
"
"
"
"
-
.!!:
I.
~.J..
...
~
•
1
I. I
'5
i
1
. , 10 11
U
u,. n
II 11 II "
2.11 22 11
l' 25,. 2J
If 11 111 31
J2 JJ 10I U
,Ji II
]I,.
Lq--E
Video Controller
UART Shift Register
and Control Key Detect
PAL20X8
Video Controller
PAL20X10
VP6
PAL DESIGN SPECIFICATION
BIRKNER/UDI
21/7/81
UART SHIFT REGISTER AND CONTROL KEY DETECT
MMI SUNNYVALE, CALIFORNIA
CK /SAMPLE RXD /CLRLIN /WRITE INIT NC NC NC NC NC GND
/UEN /BS /SPACE D6 D5 04 03 02 01 DO /LF vec
/DO := /DO*/SAMPLE
+ SPACE
: + : /D1 * SAMPLE
,HoLD
,SET SPACE CODE
,SHIFT
/D1 := /D1*/SAMPLE
+ SPACE
:+:/D2* SAMPLE
,HOLD
,SET SPACE CODE
,SHIFT
/02 : .. /D2*/SAMPLE
+ SPACE
:+:/03* SAMPLE
,HOLD
,SET SPACE CODE
; SHIFT
/D3 :=·/D3*/SAMPLE
+ SPACE
: +: /D4 * SAMPLE
,HOLD
rSET SPACE CODE
,SHIFT
/D4 := /D4*/SAMPLE
+ SPACE
: +: /D5 * SAMPLE
,HOLD
ISET S~ACE CODE
ISHI.FT
/D5
,SET SPACE CODE INSTEAD
/INIT*/D5*/SAMPLE*/SPACE
+ /05*/SAMPLE*/SPACE
:+:/INIT*/06*SAMPLE*/SPACE
:=
,OF ANY CONTROL CODE
,SHIFT
/D6 : .. /INIT*/D6*/SAMPLE
+ SPACE
:+:/INIT* RXO*SAMPLE
,HOLD
,SET SPACE CODl!:
1 DATA IS SHIFTED IN
SPAC.E := WRlTE*/D6*/D5
+ CLRLIN
,DETECT CTRL CHAR
,AND CLEAR LINE
LF :== /06*/05*/04*03*/02*01*/00
*WRITE
+ LF*WRlTE
,LINE FEED .. HEX OA
,LATCH ON WRITE
1HOLD DURING WRITE
Video Controller
FUNC'l'ION TABLE
CK SAMPLE RXD CLRLIN WRITE INIT
C
K
S
A
C
L
M
R
W
R
L
I
N
I
T
E
P
L
E
R
X
D
I
N
I
T
/
U
E
N
S
P
/ A
B ·C
S E
/UEN
!BS SPACE 06 05 04 03 02 01 DO LF
DATA· OUT
06----00
L
F
XXXXXXX
HBXXXXX
XXXXXXX
HXXXXXX
LHXXXXX
HLHXXXX
LHLHXXX
HLHLHXX
LHLHLHX
HLHLHLH
LHLHLHL
HLHLHLH
LHLHIJJL
HLHLHLH
LHLHLHL
LLHLHLH
LLLHLHL
LLLHLHL
LHLLLLL
X
X
COMMENTS
----------------------------------------------------------------------------C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
x
X L
X L
x X L
H L L
H H L
H L L
H H L
H L L
H H L
H L L
H H L
H L L
H H L
H L L
H H L
H H L
H H L
L X L
L X L
H
L L L
L H L
L L L
X L L
X L "~
X L L
X L L
X L L
X L L
X L L
X L L
X L L
X L L
X L L
X L L
X L L
L L L
H 'L L
L L L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
x
X
X
X
X
X
X
X
X
X
X
.X
X
X
X
H
X
INITIALIZE "SPACE"
INITIALIZE 06 AND 05
HOLD "SPACE" LO
SHIFT IN l'ST BIT OF ,au," CODE
SHIFT IN 2'ND BI.T OF n~a CODE
SHIFT IN 3'RD BIT OF nUn CODE
SHIFT IN 4' TH BIT OF "Un CODE
SHIFT IN 5'TH BIT OF nun CODE
SHIFT IN 6'TH BIT OF nun CODE
OUTFUT nUn CODE, STORE IN RAM
SHIFT IN l'ST BIT OF "LF~ CODE
SHIFT IN 2'ND BIT OF "LF" COPE
SHIFT IN 3'RD BIT OF nLF" CODE
SHIFT IN 4' TH BIT OF nLF" CODE
SHIFT IN 5'TH BIT OF "Lpn CODE "
SHIFT IN 6'TH BIT OF nLF" CODE
DETECT "LF" CODE
BOLD DURING WRITE
WRITE ·SPACE" CODE INTO RAM "
,
"
'~
---------.------------------------~~---~---.----------------------~-~---~~~-~
Video Controller
DESCRIPTION
THE "UART" SHIFT REGISTER ISA SEVEN BIT REGISTER FOR THE SEVEN BIT ASCII
CODE. THE INFORMATION ENTERS THE SHIFT REGISTER IN D6, ONE BIT AT A TIME.
IT COMES THROUGH RXD PIN WHICH IS THE TRANSMIT OR THE RECEIVE LINE OF THE
RS232. THE OUTPUTS ARE TRANSFERED IN PARALLEL TO THE RAM. "UEN" ENABLES THE
THREE STATE FOR THESE OUTPUTS. WHEN BITS D6 AND D5 TOGETHER IN THE ASCII
CODE ARE ZEROES OR WHEN THE "CLRLIN" BIT IS SET, A "SPACE" CODE IS SHIFTED
INTO THE "UART" REGISTER. THE SPACE CODE PRINTS A BLANK SPACE ON THE SCREEN.
"SPACE" IN ASCII CODE IS 0100000
20 HEX~
=
ASCII Code System and Character Set
06, 05 \
,.
7~
N
o
0
5
o
o
00
6
4 3 2
o
o
0
01
o
o
1
o
o
%
&
'i:
2
3
4
5
6
7
8
9
p
Q
a
b
B
R
S
c
D
T
d
E
u
v
e
F
u'
v
G
w
g
w
H
x
h
x
~~
~
,~
s
y
L
>
N
?
o
y
z
z
k
\
m
M
1 1 1 1 ~S(~~y~~
q
C
K
<
1
@
J
+
1
o
o
1,
A
1 1 1 ~BEL <5'..
PI
~D-
- ~
"
"
-Q-I
"
>..
~
~
~
~
~ 05
~
IDD-
"
6
>..
..
"
~~D-
..
.
1..(1
""
NC
7
~D,..,-
"
NC ~~
...
::::::::.
~D"'"
56
"
"
NC
9
>..
;;;.-
>..
~-
::~~
"
"
"
"
NC
15
Ie< 1
"
10
03
19(1
..,. _
.
11
"
1
2)
4
§
6
I
•
91011
12 131. 15
16 11 18 19
2011 l2 23
24252627
1129 JO 31
32 3314 lS
_a
-10.
04
~ os
1,,(1
...."
NC
19
~
~D- ~
~
"
01
R....
...
JJ
21
.....
~
49~
Mj
"
"
"J
DO
~ 02
~-
"
"
"
"
5
1C
~
"
4
-
SPACE
~
"
lA..E
"'f
36 l1lt19
5-65
Video Controller
5-66
UART Control
PAL20X10
5-67
Video Controller
PAL20X10
PAL DESIGN SPECIFICATION
VP7
BIRKNER/CD I
7/28/81
UART CONTROL
MMI SUNNYVALE, CALIFORNIA
CK /9600X8 RXD /WE /INIT /SETBC2 /SETBC1 /SETBCO ~ NC NC GND
/oe /READY /SAMPLE /BC3 /BC2 /BC1 /BCO /DET2 /DET1/DETO /START vec
START :.. /READY*START
+ /READY*RXD
:+:/READY*START*BC3*BC2*BC1*BCO
*/DET2*/DET1*DETO*/RXD
: HOLD
:DETECT START BIT
: FILTER FALSE START
:CANCEL START IF NO RXD
DETO := START*DETO
+ START*DETO
:+:START*9600X8
: HOLD
: EXTEND
DET1 :.. START*DET1
+ START*DET1
:+:START*9600X8*DETO
: HOLD
: EXTEND
: CARRY
DET2 : = START*DET2
+ START*DET2
:+:START*9600X8*DETO*DET1
: HOLD
: EXTEND
BCO
BC1
BC2
BC3
: = /SETBCO *BCO
+ /SETBCO*RFADY
:+:/SETBCO*START*9600X8*DETO*DET1*DET2
+ SETBCO
: = /SETBC1 *BC1
+ /SETBC1*RFADY
:+:/SETBC1*START*9600X8*DETO*DET1*DET2
*BCO
+ SETBC1
:.. /SETBC2 *BC2
+ /SETBC2*RFADY
:+:/SETBC2*START*9600X8*DETO*DET1*DET2
*BCO*BC1
+ SETBC2
BC3
+ READY
:+:START*9600X8*DETO*DET1*DET2
*BCO*BC1*BC2
:=
: CARRY
: CARRY
:liOLD
:SET BC TO -1 ON READY
: CARRY
: SET BC TO 7 FOR. TESTING.
: HOLD
: SET BC TO -1 ON READY
: CARRY
: S~ BC TO 7 FOR TESTING
: HOLD
: SET BC TO -1 ON READY
: CARRY
:SET BC TO 7 FOR TESTING
: HOLD
: SET BC TO -1 ON READY
: CARRY
SAMPLE : = START*960 OX8* /DET2*DETl */DETO */BC3
+ START*9600X8*/DET2*DET1*/DETO*/BC3
:+:START*9600X8*/DET2*DET1*/DETO
*/BC3*BC2*BC1*BCO
:DET=2 & BC=O •• 7
READY := /INIT*/WE*READY
+ /INIT*/WE*START*BC3*/BC2*/BC1*/BCO
:+: INIT
: HOLD
:SET ON BC=8
:INITIAL READY, START & BC
5·68
: EXTEND
: CANCEL BC = 7
Video Controller
FUNCTION TABLE
CK 9600X8 RXD /WE INIT SETBC2 SETBCl SETBCO loe READY
SAMPLE BC3 BC2 BC1 BCO
DET2 DET1 DETO
START
9
S
6
R
OlE
o R I N
I A
C X x W I SETBC 0 D
K 8 D E T 210
C Y
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
x x
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C H H H L
C
C
H H L L
H H L L
xxx
xxx
xxx
XXX
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
HLH
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
A
S
M
T
P
A
L BC
E 3210
DET
210
R
T
L H X XXXX xxx X
L H X HHHH XXX L
L L X HHHH LLL L
L L X HHHH LLL H
L L L HHHH LLH H
L L L HHHH LHL L
L L L HHHH LLL H
L L L HHHH tLH H
L L L HHHH LHL H
L L L HHHH LHH H
L L L HHHH HLL H
L L L HHHH HLH H
L L L HHHH HHL H
L L L HHHH HHH H
L L L LLLL LLL H
L L L LLLL LLH H
L L L LLLL LHL H
L L H LLLL LHH H
L L L LLLL HLL H
L L L LLLL HLH H
L L L LLLL HHL H
L L L LLLL HHH H
L L L LLLH LLL H
L L L LLLH LLH H
L L L LLLH LHL H
L L H LLLH LHH H
L L L LLtH HLL H
L L L LLLH HLH H
L L L LLLH HHL H
L L L LLLH HHH H
L L L LHHH LLL H
L L L LHHH LLH H
LLLLHHHLHLH
L L L LHHH LHH H
L L L LHHH HLL H
L L L LHHH HLH H
L L L LHHH HHL H
L L L LHHH HHH H
L L L HLLL LLL H
L H L HLLL LLH H
L L L HHHH LHL L
L L L HHHH LLL H
COMMENTS
INITIAL READY
CLEAR START & INITIAL BC
INITIAL DET & CLEAR READY
SET START
NO RXD, DETECT FALSE START
CLEAR START (NOISE ON RXD)
INITIALIZE DET
NOW IT IS A REAL SIGNAL
INC DET, NO SAMPLING
NO SAMPLE, START BIT OF INFO
INC DET, NO SAMPLING
INC DET, NO SAMPLING
INC DET, NO SAMPLING
INC DET, NO SAMPLING
INC DET AND BIT COUNTER
l'ST BIT OF ASCII CODE
INC DET
SAMPLE THE l'ST INFO BIT
INC DET
INC DET
INC DET
INC DET
INC DET AND BIT COUNTER
2 ' ND BIT OF ASCII CODE
INC DET
SAMPLE 2 ' ND BIT OF INFO
INC DET
INC DET
INC DET
INC DET
SET BIT COUNTER TO 7
7 ' TH BrT OF ASCII CODE
INC DET
NO SAMPLE 7 ' TH BIT ALWAYS 0
INC DET
INC DET
INC DET
INC DET
INC DET AND BIT COUNTER
SET THE READY SIGNAL
SET START BIT & INITIAL BC
REPEATE FOR NEXT CHARACTER
5·69
Vldeo,'Controlier
DESCRIPTION
BIT #7 IS
ALWAYS 0
STOP BIT
"BC" IS A COUNTER FOR THE ASCII CODE BITS. A SAM]?LE FROM EACH ASCII BIT
IS TAKEN WHEN "DET," = 3.
THE "START" SIGNAL IS SET:,WHEN A STAll,T BIT IS DE'l'ECTED ON THE RXD LINE
AND REMAINS SET UNTIL, THE :LAST ASCII BIT OF THE CHARACTER THAT IS SAMPLED.
AFTER ALL THE,7 BITS OF THE ASCII CODE WERE SAMPLED, A WRITE SIGNAL IS
SENT TO THE RAM AND THE 7 BITS,(A CODE FOR A C~CTER) ARE WRITTEN IN
PARALLEL INTO THE RAM.
WHEN "BC" COUNTS 8 THE "READY" SIGNAL GOES HIGH, "START" GOES LOW AND READY
TO BE SET AGAIN IF A NEW START BIT IS DETECTED. Ai NEW CODE FOR A NEW
CHARACTER WILL START TO BE SAMPLED.
BUT
ASSUME THAT A NOISE OCCURS ON THE RXD LINE WHICH SET THE "START" SIGNAL.
RXD~
START~
'
SIGNAL
NO CHARACTER IS S!',NT. THE START LINE
{ SHOULD BE HI, BUT IS FORCED LOW BY
'A NOISE ON THE RXDLINE
THE START SIGNAL IS SET
{ BY A FALSE S'TART BIT
, ,ON THE RXD LINE
TO DETERMINE IF THIS IS A TRUE OR FALSE STAR'l.', WE CHECK THE RXDLINE.
IF THE RXD LINE IS NOT SET, WE KNOW THAT NO CHARACTER WAS SENT O~ THE
RS232 LINE: THEREFORE, ~ NQISE/~~SE SIGNAL WAS DE~CTED.
5 ..70
Video Controller
ERROR ANALYSIS FOR SAMPLING
SINCE BOTH A TRANSMITTER AND A RECEIVER ARE USED IN OBTAINING INFORMATION,
AN ERROR CAN OCCUR THAT INVOLVES BOTH OF THESE COMPONENTS.
ASSUME: ERROR IN TRANSMITTING FREQUENCY = EX
ERROR IN RECEIVING FREQUENCY = ER
THEN THE TOTAL ERROR FOR ONE BIT OF INFORMATION IS (EX + ER).
AND THE TOTAL ERROR FOR THE N'TH BIT OF INFORMATION IS N*(EX + ER).
WHEN COUNTER "DET" IS EQUAL 3, WE HAVE THE IDEAL BIT FOR SAMPLING.
THE MAXIMUM ERROR THAT IS ALLOWED DUE TO THE TOLERANCES IN THE FREQUENCIES
IN BOTH TRANSMITTER AND RECEIVER, WILL BE WHEN THE SAMPLE IS TAKEN AT
"DET n = 0 OR.AT "DET" = 6, AS SHOWN HERE:
_1_ • .1
_-+-:-....,...-':-::~-'L-'-:+_=9600 8
THE DASHED LINES ARE
THE MAXIMUM ERROR ALLOWED
IN SAMPLING
THE FREQUENCY FOR EACH BIT OF INFORMATION IS 1/9600 Hz (104 MICROSECOND).
EACH BIT OF INFORMATION IS DIVIDED INTO EIGHT TIME SLOTS.
THE TOTAL ERROR ALLOWED FOR THE 7' TH BIT OF INFORMATION IS:
7 * (EX + ER)
=
(1/9600) * (3/8)
THE TOTAL ERROR ALLOWED FOR ONE BIT OF INFORMATION IS:
(EX + ER) = 104 * (3/8) * (1/7) = 5.5 MICROSECOND
THE FREQUENCY RATE BETWEEN RS232 AND THE RXD LINE FOR EVERY BIT OF
INFORMATION SHOULD BE BETWEEN 10150 Hz AND 9130 Hz.
5·71
Video Controller
DETAIL C
RXD
START
I
/
"
/
BC
SAMPLE
READY
CHAR
IFINISH TO LOAD
- - - - - - - - - - - - - - . . . J · A CHARACTER
INTO THE UART.
ONE CHARACTER
ONE CHARACTER
NEXT CHAR
r,
WRITE TO THE RAM AT ADDRESS POINTED BY "CURS"
WE: AND ·SCROL" THE CHARACTER CODE THAT IS IN
THE UART.
A SIGNAL TO THE UART CONTROLLER THAT THE UART
WRITE: HAS A CHARACTER CODE WHICH IS READY TO BE
WRITTEN INTO THE RAM.
Timing diagram for detecting a character and writing it into
the .RAM. Signals "WRITE" and "WE" are explained and derived in the next PAL specification VPB.
5·72
r---I
Video Controller
UART CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CXXXOXXXXXXXOLXXXXXXXXX1
CX01IXXXXXXXOLXLLLLXXXH1
CXOOIXXXXXXXOHXLLLLHHHH1
CX101XXXXXXXOHXLLLLHHHL1
C00011l1XXXXOHHLLLLHHLL1
COOOI1IIXXXXOHHLLLLHLHH1
C0101111XXXXOHHLLLLHHHLl
C0101111XXXXOHHLLLLHHLL1
C0101111XXXXOHHLLLLHLHLI
C010l111XXXXOHHLLLLHLLL1
C0101111XXXXOHHLLLLLHHL1
C0101111XXXXOHHLLLLLHLL1
C0101111XXXXOHHLLLLLLHL1
COI011l1XXXXOHHLLLLLLLL1
C0101111XXXXOHHHHHHHHHL1
C0101ll1XXXXOHHHHHHHHLL1
C0101111XXXXOHHHHHHHLHL1
C0101111XXXXOHLHHHHHLLLl
C010ll11XXXXOHHHHHHLHHL1
C0101111XXXXOHHHHHHLHLL1
C0101ll1XXXXOHHHHHHLLHL1
C0101111XXXXOHHHHHHLLLL1
C0101111XXXXOHHHHHLHHHLl
C010111IXXXXOHHHHHLHHLL1
COI01111XXXXOHHHHHLHLHLl
C010l111XXXXOHLHHHLHLLLl
COI01111XXXXOHHHHHLLHHL1
C0101111XXXXOHHHHHLLHLL1
C0101111XXXXOHHHHHLLLHLl
C01011IIXXXXOHHHHHLLLLL1
COI01010XXXXOHHHLLLHHHL1
C010llllXXXXO.HHHLLLHHLL1
COI0ll11XXXXOHHHLLLHLHLl
C010111IXXXXOHHHLLLHLLL1
C0101I11XXXXOHHHLLLLHHL1
C0101111XXXXOHHHLLLLHLL1
C0101l11XXXXOHHHLLLLLHLl
C010111IXXXXOHHHLLLLLLL1
C01011l1XXXXOHHLHHHHHHL1
C0111111XXXXOLHLHHHHHLLl
C0101lllXXXXOHHLLLLHLHH1
C01011l1XXXXOHHLLLLHHHLl
PASS SIMULATION
5·73
Video Controller
UART CONTROL
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
0
1
2
---x ------- x-----x -x-x
8
9
10
---x ---x ---- ------x ---x ---- ----x-x ---- ---- ----
START*DETO
START*DETO
START*9600X8
16
17
18
---x ---- ---x ------x ---- ---x ----x-x ---x ----
START*DET1
START*DET1
START*9600X8*DETO
24
25
26
---x ---- ---- ---x ---- ---- ------x ---- ---- ---x
-x-x ---x ---x
START*DET2
START*DET2
START*9600X8*DETO*DET1
--X:-
32 ---- ---- ---33 ---- ---- ---34 -x-x ---x ---x
35
--X- /READY*START
/READY*RXD
/READY*START*BC3*BC2*BC-
--x--x- ---x ---x ---x ---x ---- --x-
---x ---- x--x---
---x
40
41
42
43
x--x ---x---x-x ---x ---x ---x ---x x---x--
---x
48
49
50
51
x-----x
x---x-x ---x ---x ---x x--x ---x
-x--
---x
---x
x---x--
---x
56
57
58
-x-x ---x ---x ---x ---x ---x ---x ----
64
65
66
-x-x --x- ---x --x- ---- ---- ---- --x-x-x --x- ---x --x- ---- -----x-x-x --x- ---x --x- ---x ---x ---x --x-
72
73 ---x ---74 ---- ---LEGEND:
x--- x--x--- x--- --x- --x- --x- ---x
-x--
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW
5·74
= 1207
---x
/SETBCO*BCO
/SETBCO*READY
/SETBCO*START*9600X8*DESETBCO
/SETBC1*BC1
/SETBC1*READY
/SETBC1*START*9600X8*DESETBC1
/SETBC2*BC2
/SETBC2*READY
/SETBC2*START*9600X8*DESETBC2
BC3
READY
START*9600X8*DETO*DET1*START*9600X8*/DET2*DET1START*9600X8*/DET2*DET1START*9600X8*/DET2*DET1-
---x
/INIT*/WE*READY
/INIT*/WE*START*BC3*/BC---- INIT
- : FUSE BLOWN
(R,P,l)
Video Controller
UART Control
Logic Diagram PAL20X10
CK 1
0\
2)
4
~
,
I
891011
11 13 14
1~
16l/1I19
2Q 21 12
n
14 15
~ti
1I
21 19 10 31
12 JJJ4 lS
36]1]139
'""'-
~~~
~~
"
,
,
~
~
'""'-
,
""
~~D-
0
RXD
--
3
~
Xf9D-- ~
"
"
"
....
"
4
~
0-
~""9D-
"
"
"
"
-
5
6
.
"
H>o~
~
7
f--
...
,.
"
~
8
.
"
"
"
~D-
...
.
~9D~-
~J\7{
9
"
::k
~
~
:rL.
....
16
~ 15
-yo-
~~~
"
"
"
"
NC
20
~-
.,"
10
R
-vo-
~
~9DH>o~
~
~D- ~~
:L;lJ
"
NC
~
;:::..:=
~D-
"
u
"
NC
~
~
~
11
o \
2
1
_
~
,1
I ' 10 11
11 1114 IS
16 11 18 19
10]1 11 13
14 1S 16 11
11
1~
]0 31
31 11 l4 JS
l i 31
~
lin
5-75
Video Controller
5·76
RAM Control
PAL20X10
VCC
WRITE
CUiiSi
SWAP
CHAR1
5
tiiLANK
WE
CHA'R2
6
CHARi
7
CiiAiii
8
CHARS
9
J.UOOUU'><..JI'7
'6
r.:11 ... ·_ . .
'.
5.
CLRt'iN
iNCSCii
CHAiiii
5·77
Video Controller
PAL20X10
PAL DESIGN SPECIFICATION
VP8
BIRKNER/UDI
7/29/81
RAM CONTROL
MMI SUNNYVALE, CALIFORNIA
CK /DTCNTO /DTCNT1 /DTCNT2 /CHARl /CHAR2 /CHAR3 /CHAR~ /CHARS /READY /LF GND
/oe /H25S /CHARO /INCSCR /CLRLIN /SWAPC IWE/HBLANK /SWAP /CURSO /WRITE vec
WRITE:=READY*/DTCNT2*/DTCNT1*/DTCNTO*/H2S5
*CHARS*CHAR4*CHAR3*CHAR2*CHARl*CHARO
+ WRITE*/DTCNT2*/H2SS
:+:WRITE* DTCNT2*/DTCNT1*/H2SS
+ CLRLIN*/DTCNT2*/DTCNT1*/DTCNTO
;SET WHEN DTCNT=O
;& CHAR=63
;HOLD AT 0,1,2,3
;HOLD AT 4,S
; SET AT DTCNT=O
SWAP : = WRITE* /DTCNT2 */DTCNT1 *DTCNTO
+ WRITE* DTCNT2*/DTCNT1*/DTCNTO
;SWAP AT DTCNT=l
; SWAP BACK AT 4
SWAPC:= WRITE*/DTCNT2*/DTCNT1*DTCNTO*/CLRLIN
+ WRITE* DTCNT2 */DTCNT1 */DTCNTO */CLRLIN
:+:CHARS*CHAR4*/CHAR3*LF
; SWAP AT DTCNT=l
; SWAP BACK AT 4
;TEST CONDITION
WE
:= WRITE*/DTCNT2*DTCNT1*DTCNTO
; ENABLE WRITE
INCSCR
:= WRITE*DTCNT2*/DTCNT1*DTCNTO*/CLRLIN*/H2SS*LF
+ WRITE* CHARS */CHAR4 *CHAR3 *CHAR2 *CHARl *CHARO
*/CLRLIN*/H2SS
* DTCNT2 */DTCNTI *DTCNTO
:+:CHARS*CHAR4*/CHAR3*LF
; DE'l'ECT LINEFEED
;CURS=47, LAST
;VISIBLE CHAR ON
; LINE. DTCNT=S
,TEST CONDITION
H2SS
:= CHARS*CHAR4*CHAR3*CHAR2*CHARl*CHARO
*DTCNT2*DTCNTl*/DTCNTO
;END OF LINE
;DTCNT=6
CLRLIN := INCSCR
+ CLRLIN*CHARS*CHAR4*CHAR3*CHAR2*CHARl*CHARO
:+:CLRLIN*/CHARS
+ CLRLIN*/CHAR4
;SET ON LINE END
;HOLD THIS WRITE
;HOLD, CHAR=O-31
;HOLD, CHAR=32-47
HBLANK : = CHARS *CHAR4
+ CHARS*CHAR4
:+:CHARS*CHAR4*/CHAR3*/CHAR2*/CHARl*/CHARO*/DTCNT2
+ CHARS*CHAR4*/CHAR3*/CHAR2*/CHARl*/CHARO*/DTCNTl
;CHAR=48-63
; EXTEND
;CANCEL 48-48.S
;CANCEL 48.S-48.75
CHARO : = SWAPC*CURSO
+ /SWAPC*CHARO
: +:/SWAPC*DTCNTO*DTCNTl*DTCNT2
; SWAP WITH CURS
; HOLD
;INe
CURSO := SWAPC*/INCSCR*CHARO
;SWAP WITH CHAR
+ /SWAPC*/INCSCR*CURSO
; HOLD
:+:/SWAPC*/INCSCR*WRITE*/CLRLIN*DTCNT2*DTCNTl*/DTCNTO ;INC
5-78
Video. COntroller
FUNCTION TABLE
CK .O'l'CNT2 D'lQfrl D'l'CN'l'O CHARS. CAAR4 CaAR) C9AR2 CHARi CAARO READY
LF /oe H~S5 INCSCR Cf,RLIN SWAPe /WE aBLANt{ SWJ\P CURSO WRITE
~
C D'l'CN'!'
210
K
CAAR
54321 0
R
E
A
/
D L 0
Y F C
H
2
5
5
I
C
N
C
S
C
R
L
R
L
I
N
H
S
W
A /
P W
C E
B
C W
L SUR
A W R I
N A S T
K POE
COMMENTS
--------------~--------------------------------------------------------------SET INCSCR, SWAPC
LLL
HHLXX X X H L X H X H X X X X X
C
HHLXX
HHLXX
LLLXX
LLXXX
HHLXX
HHLXX
aHLXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
C
HHL
LLL
LLH
HHL
HHL
HHL
LLL
LLa
LBL
LHH
HLL
aLB
HHL
HHH
LLL
LLH
LEL
LHH
ELL
HLB
HHL
HHH
LLL
HHH
C
~LL
C
C
C
C
C
C
LHH
HHL
XXX
LLL
LLL
LLL
LLH
HHLLL
HHLXX
HHLXX
HHLXX
LLXXX
LLXXX
HHLXX
XXXXX
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
xxxxx
aHHBH
HHLXX
HHHXX
HHLXX
X
X
X
X
X
X
X
X
X
L
X
X
H
H
X
X
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
L
x x
L
x L
L
X L
L
X L
L
X L
L
x L
L
X L
L
H L
L
a L x L
a L x L
H L X L
H L X L
a L x L
H L X L
H L X L
L L L L
L aLL
H L L L
HaL L
H L L L
H L H L
L L L L
L L L L
L L L L
L L L L
L L L L
X
L
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
t
L
L
L
L
L
L
L
t
L
H
H
L
L
H
H
H
f,
L
X
H H
a H
X X
X X
X X
X X
X X
X X
L X
L X
L X
L X
L X
L X
L ~
L X
L L
L L
L L
L L
L L
H L
L H
L H
L H
L L
L L
H
H
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
X X
X
X
X
X
L
a
L
H
X
X
x x
~
x' x x
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
x x x x
X
X
X
X
X
X
X
X
X
X
X
X
H
H
a
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
x
L
L
.~
X
X X
X X
X X
x H
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
t
L
L
L
L
L
X
H
H
L
X
X
H
a
a
a
a
a
L
L
L
L
L
L
L
L
X
X
L
L
X
L
L
L
H
L
H
H
CLRLIN=H,CURS=L
SET WRITE
INCSCS,CLRLIN=L
SWAP CORSO, CAARO
SET INCSCR,CWAPC
CLRLIN"'H
SET WRITE SIGNAL
HOLD WRITE
HOLD WRITE
ENABLE WRITE
HoLD WRITE
HOLD WRITE
CLEAR WRITE SIGNAL
CAARO=H, INCSCR=L
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
END OF LINE
CriEAR CLRLIN & H2SS
SET HBLANt{
SET CORSO' LO
HBL(OO{=L
HOLD
SET INCSCR
SET CLRLIN
HOLD CLRLIN, SET WRITE
CLR WRITE, HOLD CLRLIN
CLEAR CLRLIN
SET SWAP & SWAPe
5·79
Video Controller
DESCRIPTION
THIS PAL CONTROLS BOTH THE TIMING FOR wRITING A CHARACTER INTO THE RAM
AND THE TIMING FOR READING A CHARACTER FROM THE RAM.
"WRITE~ IS A SIGNAL THAT DATA IS AVAILABLE AND CAN BE WRITTEN INTO THE
RAM WHEN "DTCNT" IS BETWEEN 0 AND 5.
"SWAP" AND "SWAPC" SWAP POINTERS TO ENABLE WRITING AND READING BY
ADDRESSING THE RAM THROUGH THE SAME ADDRESS LINES.
"UEN" ENABLES THE UART.
"WE" WRITES TO THE RAM THE DATA THAT IS IN THE UART REGISTER.
"INCSCR" IS A SIGNAL THAT DETECT LINEFEED AND 48 CHARACTERS PER LINE.
"CLRLIN" ERASES EARLIER INFORMATION AND ALLOWS TO WRITE TO THAT LOCATION.
WHEN THE "LF" KEY IS PUSHED, THE CLRLIN SIGNAL. IS SET. IT REMAINS SET AS
LONG AS A WRITE IS DONE TO THIS LOCATION.
"H255" DETECTS END OF LINE.
"HBLANK" BLANK OUT THE SCREEN WHEN "CHAR" IS BETWEEN 48 AND 63.
DTCNT
WRITE
tot f f f f t f t
I I I I I I I I I
I I I I I I I I I
---+-l I I I I I +11
2
3
4
5
6
7
f-.
SWAPC/SWAP
I I
I I
I
I
I
I I
I
RAM ADO.RESS POINTED BY: -+"..,...,,....,..,..,,,.,,+~....,,..,,~+,,..,...,,....,..,..,,,.,,
OPERATION: _~....;.;=:-~--:-:-:..;.;.;.;:'-+-....;.;=:-_
I
UEN
DATA BUS
CONTROLLED BY:
WE
I I I
!
I
I
I
I II
I
+1'1 H:+1 :+.
I II I
I I I
I I I I . . I I I
I I I I I I I I I
WRITE and READ signals to the RAM for one character
code (when CHAR = 63). (Z = THREE STATE)
~.80
Video Controller
RAM CONTroL
1 C111XX100XOXOXXLXLXXXXX1
2 C100XX100XOXOXXLLLXXXHX1
3 C111XX100XOXOHXLLLXXXBL1
4 C011XX111XXXOHXHHHXXXBL1
5 C100XXX111XXOHXHHHXXXXH1
6 C100XX100XOXOXXLXLXXXXX1
7 C100XX100XOXOXXLLLXXXHX1
8 C111XX100XOXOHXLLLXXXXLl
9 C011XXXXX1XXOHXXXXXXXXLl
10 C101XXXXX1XXOHXXXXHXXXL1
11 C001XXXXX1~OaxxXXLXXXL1
12 C110XXXXX1XXOHXXXXHXXXL1
13 C010XXXXX1XXOHXXXXXXXXL1
14 C100XXXXX1XXOHXXXHXXXXH1
15 COOOXXXXX1XXOHLHXHXXXXH1
16 C111XXXXX1XXOHLHXHXXXXHl
17 C011XXXXX1XXOBLHXHXXXXH1
18 C101XXXXX1XXOHLHXHXXXXH1
19 C001XXXXX1XXOHLHXHXXXXH1
20C110XXXXX1XXOBLHXHXXXXH1
21 C010XXXXX1XXOHLHXHXXXXH1
22 C100000001XXOLLHXHXXxxx1
23 COOOXX10011XOHHHHHXXXXX1
24 C111XX00001XOHHHHHXLXXHl
25 COOOXX10011XOBLHHHXLXHH1
26 C1111110001XOBLHHHXLXHX1
27 C001XX10011XOBLHHHXXHHH1
28 C100XX10010XOHLLHLXXHHH1
29 CXXXXX10011XOHHHLXXXXHH1
30 C111XXX11l1XOHHBLXXXXBL1
31 C111XXX1l11XOHHHLXXXXHH1
32 C111XX100llXOaHHHXXXXBLl
3.3 COllXXXXXllXOHHHHLXXLHL1
PASS SIMULATION
5 .. 81
Video· Controller
RAM CONTR:>L
11 1111 1111 2222 2222 2233 3333 3333
0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
o
1
2
3
x-----x
---x
x---
x-----x--x---
x--x---x-x---
-x-----------
-x--
-x--x-- -x----- ---- ---- ------- ---- ---- ------- ---- ---x ----
-x-x
----------
--x- READY*/DTCNT2*/DTCNT1*/--x- WRlTE*/DTCNT2~/H255
-~x- WRlTE*DTCNT2*/DTCNT1*/H---- CLRLIN*/DTCNT2*/DTCNT1*-
8 ---- ---- ---- ---- ---- ---x ---- ~-x- ---x ---- SWAPC*/INCSCR*CBARO
9 ---- ---x ---- ---- ---- --x- ---- --x- ---- ---- /SWAPC*/INc$CR*cuRSO
10 x--x -x-- -x-- ---- ---- --x- --x- --x- ---- ---- /SWAPC*/t~SCR,*WRlTE*/C16 -x-x x--- x--- ---- ---- ---- ---- --,..- ---- ---- WRITE*/DTCNT2*/DTCNT1*D17 x--x x--- -x-- ---- ---- ---- ---- ---- ---- ---- WRITE*DTCNT2*/DTCNT1*/D24
25
26
27 ----
---------x---
------x------
------x--x---
------x--x---
------x--x---
-x--x--x--x--
-x--x--x--x--
----.---- CBARS*CBAR4
---- ---- CBAR5*CBAR4
--x- ---- cHAR5*C~4*/CBAR3*/CBA--x- ---- CBARS*CBAR4*/CBAR3*/CBA-
32 -x-x -x-- x--- ---- ---- ---- ---- ---- ---- ---- WRlTE*/DTCNT2*DTCNTl*DT40 -x-x x--- x--- ---- ---- ---- --x- ---- ---- ---- WRlTE*/DTCNT2*/DTCNT1*D41 x--x x--- -x-- ---- ---- ---- --x- ---- ---- ---- WRlTE*DTCNT2*/DTCNT1*/D42 ---- ---- ---- ---- ---- x--- -x-- -x-- ---- -x-- CBARS*CBAR4*/CBAR3*LF
48
49
50
51
-------------
-------------
-------------
----x--------
----x--------
----x--------
----x-x
---x
x--x
---x
-x-x------
------x
-------
-------------
INCSCR
CLRLIN*CBARS*CBAR4*CBARCLRLIN*/CBARS
CLRLIN*/CBAR4
56 -x-x x--- -x-- ---- ---- ---- --x- ---- ---- -xx- WRITE*DTCNT2*/DTCNTl*DT57 -x-x x--- -x-- -x-- -x-- -x-- x-x- -x-- ---x --x- WRlTE*CBARS*/CBAR4*CBAR58 ---- ---- ---- ---- ---- x--- -x-- -x-- ---- -x-- CBARS*CBAR4*/CBAR3*LF
64
---x ---- ---- ---- ---x ---- ---- ---- ---- SWAPC*CURSO
65
---- ---- ---- ---- --x- ---- ---- ---x ---- /SWAPC*CBARO
66 -x-- -x-- -x-- ---- ---- --x- ---- ---- ---- ---- /SWAPC*DTCNTO*DTCNT1*DT72 x--- -x-- -x-- -x-- -x-- -x-- -x-- -x-- ---x ---- CBARS*CBAR4*CHAR3*CBAR2LEGEND:
x: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOW =
989
- : FUSE BLOWN
(H,P,l)
Video Controller
Logic Diagram PAL20X10
RAM Control
CK 1
.....
-v
D 113
•
S 11
·,
I' "'1
n n,.
15
15111119
102122ll
"lSun
21 nJa]1
J2 II M U
36 HllH
~~
,
,
DTCNTO
2
:::::.-
··
~D-
-Q-r
3
"
"
~~~
-
"
"
"
"
.......
"
,."
:~D-
DTcNT2 4
-
~-L9~
CHAR1 5
"
6
..
~-?D-
"
"
"
CHAR3
....
7
-
.
9
.
21
~
";L
2!)
~
19
~
~ SWAPC
10
~
~
....
....
17
SWAP
HBLANK
WE
CLRLlN
....
" 16
INCSCR
Q
.............
"
~
15
CHARo'
~
~~~
"
"
"
"
TF
~
~
Pl
~
.......
.."
READY
CURSO
::H:t
...."
-
22
....
~-
~
"
CHARS
~
....
. . . ~D- ~
~
. . --9D- R
~
0D- ~
~
...
CHAR4 8
WRi'TE
.......
""
CtiAR2
23
Q
~
""
DTCNT1
Pl";[
~
11
0'
t]
(
~
Ii
1
•
,
10 n
12
n ,.
IS
I i " 11
n
202111
n
14 2S111l
11 nll]1
JIll:MlS
L--
H
H25S
13
OC
]Ii Jl JlH
5·83
m
Video Contro.ller
Summary
This paper conveys the message that a video-controller board
can be designed in an efficient way by using PALs. The
above video controller was developed and is used by Monolithic
Memories, Inc.
We have presented the basic vocabulary and processes that are
presently common to the industry with an explanation of how
we developed our video-controller board.
Boolean transfer function equations, function tables, descriptions, simulations and fuse-plots are all offered within our PAL
specifications. These were developed on the company in-house
computer and are available from Monolithic Memories.
Video Controller Computer Interface
"TAP JACK"
--------
AUDIO JACK
--
KATZI VIDEO
CONTROLLER
AC CORD
WITRANSFORMER
References
1. Color TV Training Manual
by Howard W. Sams
Howard W. Sams & Co., Inc.
The Bobb-Merrill Co., Inc.
2. Television Fundamentals Theory, Circuit and Servicing
Fowler and Lippert
McGraw Hill
3. Principles of Interactive Computer Graphics
by William M. Newman and Robert F. Sproull
McGraw Hill
4. John Birkner, personal
Communication; 1981
Article Reprints
I#J
SINGLE-CHIP CONTROLLER INCREASES
MICROPROCESSOR THROUGHPUT
Design technique uses semicustom logic to minimize hardware in a DMA controller that combines fast response with
the potential to service multiple input or output devices and
the flexibility to handle many different applications
Alan W. Bentley
Cubic Corporation
9333 Balboa Ave, San Diego, CA 92123
Reprinted by permission from Compufer Design Magazine.
Copyright Computer Design Publishing Company, September 1980.
Microprocessors have a broad range of capabilities; yet
they are unable to perform specific functions efficiently
without hardware augmentation. One such function is trans·
fer of blocks of data to or from processor controlled
memory. Under specific conditions, such blocks may be
moved efficiently by direct memory access. Data must be se·
quentially ordered, a starting address must be specified for
both the processor associated memory and the external
source or destination, and the data block length must be
specified. When these three conditions are met, data
transfer responsibility passes to a hardware controller, and
data moves rapidly because instruction processing is elim·
inated during the transfer.
Although direct memory access (DMA) efficiently transfers
blocks of data between a source and a destination, it nor·
mally interfaces memory with only a single external device
and is unable to move data between memory and a dis·
tributed network. The need to interface a microprocessor
with a network of distributed devices led to a generalized
concept that can be structured to transfer data rapidly in
either direction.
6·2
This concept is analogous to the DMA function in that
blocks of sequential data are transferred to or from
memory. It differs in that, externally, each data word has an
associated device location. Implementing the transfer function in terms of this concept increases the data transfer rate
while imposing four constraints on the system: the data
block length must be constant; datac must occupy sequential
memory locations; the distributed devices are always ser·
viced in the same sequence; and each implementation is
committed to either input or output.
C
Controller Design Objectives
Conceptually, the controller accepts data transfer responsibility from the microprocessor upon command; steps
through the data block, sequentially creating data paths
between memory and various external devices; then returns
control to the microprocessor. Functionally, upon receipt of
the transfer mode command, the controller places the cen·
tral processing unit (CPU) in the 3-state mode, generates all
Single-chip Controller Increases Microprocessor Throughout
---
RESET
CPU
DECODED COMMANDS
FROM CPU
OTRAN$
.----
BIDIRECTIONAL
DATA BUS
HOLDA
END
END
DECREMENT MEMORY
ADDRESS
COMPLETE
o
5T ATE DIAGRAM
1
2
13 14
-.,.-
15
DATA LOAD COMMANDS
I'
IRC
ADDRESS==X===;===;===C
_
I----IAA--I
CS ,\I
\I \I \I \\I
\\I
DoUT
\
'1
HARDWARE CONFIGURATION
\
BIDIRECTIONAL
DATA BUS
GENERAL
I--IEA(
CPU HOLD COMMAND IS 0G
tRC
tAA
tEA
21'4
RAM
=
=
=
READ CYCLE TIME
ACCESS TIME - ADDRESS TO DOUl
ACCESS TIME· CHIP SELECT TO DoUT
+ 'OH
(STATE 1,2: OR 3)
ADDR~S; ANi) DATA
2,
STATE 2 IS ENTERED UPON RECEIPT OF HOLDA (CPU IN HOLD, CPU
BUSES 3-$T ATE) ,
3
IN STATES 2 AND 3 RAM ADDRESS COUNTER OUTPUT IS REMOVED FROM 3-STATE
MODE AND ITS COUNT CAPABiliTY ENABLED THROUGH C.ET
1
AT TRANSITION FROM STATE 3 TO STATE 2. BOTH DATA COUNTER AND RAM COUNTER
ADD~ESS ARE DECREMENTED BY RISING EDGE OF
5,
UPON COMPLETION OF DATA TRANSFER (END), 'STATE 0 fS ENTERED FROM STATE 3,
DATA COUNTER IS SET AT ITS INITIAL CO~NT"ADDRESS COUNTER IS PLACED IN 3-STATE
MODE, AND HOLD COMMAND ,10 CPU IS RELEASED' ,
RAM TIMING REOUIREMENTS
6G
SPECIFIC (TRANSFER CPU M'EMORY TO EXTERNAL DEVICES)
a;;
I,
RAM IS SELECTED IN STATES 2 AND 3,
2
IN STATE 3, ENABLE SELECTS DEMULTIPLEXER, AND CONTENTS OF DATA COUNTER
THROUGH
ARE DECODED TO GENERATE DATA LOAD (WRITE ENABLE) PULSE
(OA
00)
SEDUENCE OF EVENTS
Fig 1 Transfer from CPU memory to device. PAL implements two categories of Boolean expressions. data
cou,nters that control destination selection and state
,required timing and control signals, sequentially creates the
data paths, and transfers data through each path. Upon
completion of ·the data transfer,it relinquishes control to
the microprocessor, which then resumes instruction
processing.
Increased throughput is the implementation rationale;
therefore, the two primary design objectives are to enter
:and leave the data :transfer IJ\iOde in a minimum number of
,€:lock periods and to· transfer one dat'a word every two clo'ck
periods.: This. transfer rate allows. one clock period to
establish each data path, with the write pulse created in the
second period to complete the tran·sfer. Secondary design
objectives relate to implementation and allow modification
to meet varying 'applications using a minimal amount of
additional 'circuitry.
equations that control sequence of events shown in
state diagram
Design approaches that meet these objectives include use
of a state sequencer to meet the control transfer .and data
transmission 1iming requir~ments, and, use of fusible link,
semicustom logic to meet the circuit flexibility and
minimization requirements. A simplified microprocessor
interface is achieved ,by' incorporating 'the microprocessor
clo€,k and' held capabilities into the 'sequencer design.
St~te
Sequencer
The state sequencer, organizes lmd>Mncentrates' logical
functions to realize the high density Capabilities of
semicustom :logic. What deterniimes the 'number ()f'control
flipflops . is the, number of:. required states;' th~refore,
SIngle-chip Controller Increases Microprocessor Throughout
RESET
FROM CPU
CPU DECODED COMMANDS
"-'--
~
Ai5LOAo
ADDRESS
LOAD
COMMAND
PAL 16Re
BIDIRECTIONAL
DATA BUS
,-L.'-l..,'~,.,...,....,
00 1iC Oii iiA
HOLDA
END
25LS2569
RAM
ADOAESS
GND
.C
0
B
A
Gj
G2
74154
o
1
13
14
15
~
STATE DIAGRAM
SOURCE SELECT
I',
ADDRESS
'j
lwe
==x
2114 RAM
x::=
BIDIRECTIONAL
DATA BUS
I-IWR-l
IS\S'\'M\\
CS \ \ \ \ \ \ \ \ \ \ \
HARDWARE CONFIGURATION
'""'""'""'''"
WE "'\S""S.....
\\""ST'\\""S""'\\ I---tw-----i
.
IS\SSSS\SS\
I--IDW ,...-!-IDH-l
<
DIN
lwe
tw :;:
lOW
=
WRITE CYCLE TIME
WRITE TIME
=
>--
GENERAL
+
1.
CPU HOLD COMMAND ISOG
2.
STATE 2 IS ENTERED UPON RECEIPT OF HOLDA (CPU IN HOLD, CPU ADDRESS AND DATA
BUSES 3-STATE)
QH (STATE 1,2,OR3)
3.
IN STATES 2 AND 3 RAM ADDRESS COUNTER OUTPUT IS REMOVED FROM 3-STATE
MODE AND ITS COUNT CAPABILITY ENABLED THROUGH CET
4
AT TRANSITION FROM STATE 3 TO STATE 2, BOTH Dt,LA COUNTER AND RAM COUNTER
ADDRESS ARE DECREMENTED BY RISING EDGE OF 0G
5.
UPON COMPLETION OF DATA TRANSFER (END), STATE 0 IS ENTERED FROM STATE 3,
DATA COUNTER IS SET AT ITS INITIAL COUNT, ADDRESS COUNTER IS PLACED IN 3-STATE
MODE, AND HOLD COMMAND TO CPU IS RELEASED
DATA TO WRITE. TIME OVERLAP
tOH :; "DATA HOLD TIME FROM WRITE TIME
tWR = WRITE RELEASE TIME
RAM TIMING REQUIREMENTS
SPECIFIC (TRANSFER EXTERNAL SOURCE TO CPU MEMORY)
1.
2
~O~~'i!EE~ goAN~~JT~NDDE~~'E~~~E~:E~N~~~~0~crECODES DATA
ENA8LE
DURING STATE 3
IS RAM CHIP SELECT AND WRITE ENABLE, WRITING
SOURCE OATAWQRD IN SELECTED ADDRESS .lOCATION
SEQUENCE OF EVENTS
Fig 2 Transfer from device to CPU memory. Similar to Fig 1, with hardware configuration and state diagram
modified to transfer data in opposite direction
performing all logic functions-in four states reduces the se·
quencer design requirement to two flipflopsand helps meet
the secondary design objective. These four states are idle,
when the CPU has system control; transitional, while the CPU
is entering the hold mode and relinquishing control; and
two data transfer, one permitting address and data
stabilization, and the .other creating the write command
(Figs· rand 2).
In t!!!s .!!pplication, both flipflops are reset in the idle
stale (QH,QC' state 0) awaiting a software generated com·
mand (DTRANS), which sets the G flipflop, advances the se·
quencer to state 1 (QH,QJ; and initiates 8: CPU hold com·
mand, sustained until the sequencer returns to state O. The
CPU tests its hold command input each machine cycle and,
upon sensing a command, enters the hold state, placing its
data bus, address bus, and some control lines in the 3·state
mode. It remains in this. state until the hold command is
released by the sequencer.
• When it enters the hold state, the CPU issues a hold
acknowledge (HOLD). Upon receipt of HOLDA,the
Single.chlp Controller Increases Microprocessor Throughout
sequencer advances to state 2 (QH,QJ, which completes
transfer of the data handling function from the CPU to the
controller. It then toggles between state 2 and state 3
(QH,QJ, processing one data word each cycle until the
preestablished number of data words have been transferred
(END). Then, the sequencer returns to state 0 and releases
the hold command, allowing resumption of instruction processing'by the CPU.
While the sequence of states is the same for data transfer
in either direction, the events -that occur within states 2 and
3 differ. During transfer of data from memory to external
devices, state 2 is memory access time and state 3 generates
the load command for the specific device. When leaving
state 3, the edge of the G flipflop (Q c> advances the memory
address counter. When data front external devices are read
into memory, state 2 time is used to select the external
source and stabilize the data. The memory write enable
pulse is generated by state 3, and leaving state 3 changes
the memory address counter. Transfer states ST2 and ST3
are identified by the output of the H flipflop, which activates the random access memory (RAM) address counter
ou'tputs, enables address counting, and, additionally, selects
either the RAM or the multiplexer' when transferring to or
from the external devices, respectively.
Programmed Array Logic
Utilizing semicustom integrated circuitry satisfies the requirement for logic minimization and design flexibility.
This approach increases logic density by mitigating two factors that increase random logic package count: function
partitioning and pin limitation. To maximize these benefits,
the programmable logic chip must contain AND, OR, and
flipflop functions, as well as internal feedback. Flipflop
functions are required to implement the sequencer and, additionally, a counter that is decremented at the completion of
each data transfer (state 3 to state 2 transition). The counter
serves a dual purpose: the demultiplexed count selects external devices and, by monitoring the count, the controller
determines completion of the data block transfer (END).
Data block length determines the number of counters and
demultiplexers required. With three counters and a 3 to 8
demultiplexet(74138), block lengths up to eight may be' ac-
commodated. With four counters and a 4 to 16 demultiplexer (74157), the block length may be extended to 16. An
increase to six counters will allow block length expansion to
64, with additional demultiplexers. This approach focuses
on design for a block length of 16 words so that the flipflops
and associated input decoding can be contained on one fusible link, programmable array logic (PAL) integrated circuit.
PAL 16R6 contains six 0 flipflops (registers) connected to a
common clock input. Output Q of each register is available
externally through an inverting, 3-state buffer (Q). Input 0
of each register is an B-input OR gate; each input a program;
~able AND combination of the available terms. Each gate
array must be true to set the register on the following clock
pulse or false to allow the register to reset. Thus, Boolean
expressions state the conditions that cause the registers to
become or remain set.
Two additional, non-register, AND·OR gate outputs and
the six register outputs have internal feedback paths. With
the eight available inputs, they b!lcome the 16 terms
available when implementing Boolean expressions.
Boolean Expressions
Six counter equations are shown in Fig 3. For a maximum
block length of 16, the four least, significant counts (A
through D) are required; expansion up to length 32 requires
equation E; equation F must be implemented for block
lengths between 33 ,and 64. The counter flipflops are held
set during states 0 and 1. State~ 2 and 3 require only one
clock period each; hence, from leaving state I until completion of data translJlission and return to state 0, there is a
state transition in every clock cycle.
During this interval, each' equation must establish the
condition of its counter flipflop for the following state.
When entering state 2 fr,!m state I, the couriter flipflops are
set as established by state 1.. Since it is necessary to change
the counter on the transition from state 3 'to state 2, the
counting decision must be made during state 3, and the new
count must be established when entering state 2. The
counter register content mllst be maintained during state 2
to prevent change at the transition from state 2 to 3.
Fig 3 also shows the 2-state sequencer equations. Equation G is independent of block length, and equation !I
+ 0H • OG • OF + OH • 0G (OF: 0E + OF' 00 + OF • Cc + OF • 0B + OF' 0A)
Of< + 0H' Oa' to
establish block length
"$lntl.~oltip
Controller'nore,!,ses l't'Uoroprocessor Throughout
iijeorporate~ ,th~bi~k lin8t~
(KND) decoding: The taMe,
Block CIl~th t:~ntr()l. silo,!"$. tneeJ9>ressions for 00, when
si~ coul\t~s ate used.. orga~zed.by r~mainde~ of a ,modulo
l~ pun!.l>er.:' FOF,shorter.block . lengths, references'to
upjmpl~nlePted coubt,ers' are ignored. Both control flipflops
are reset (exJiressions false) when the computer issues a
RESET command, establishing state O. This state is main·
tained 'until the CPU issues DTRANS, advancing the se·
quencer to. ,state 1 by setting G.
A hold command is generated by the sequencer, which
waits in state 1 untii the CPU responds with HOLDA, verifying
that it has stopped instruction processing and that its buses
are 3·stated. HOLDA resets G and sets H, advancing the
sequencer to state 2. The G flipflop then toggles, causing
the sequencer to cycle between states 2 and 3. H remains set
during both states but tests the content of the data counter
during state 3 to determine if data transmission is complete
(END expression false). END.false also causes the H flipflop
to reset at the completion of state 3, returning the sequen·
cer to state 0 and releasing the hold command to the CPU.
System parameters were developed for use with the model
8085 microprocessor, the 2114 bidirectional RAM, and the
25LS2569 binary up/do";n counter. Attributes of these components th,at help meet the design goals are (a) availability
of the CPU interface signals reset, clock out, hold, and hold
EITHER
Remainder
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
o
QF +
QF +
QF +
QF +
QF +
QF' +
QF +
QF +
QF +
QF +
QF +
QF +
QF +
QF +
QF+
QF +
END expression
Qe
Qe + QA
Qe + Qs
Qe + QS + QA
QE + QC
Qe + QC + QA
Qe + QC + QS
QE + QC + Qs +
Qe + QD
QI! + QD + QA
Qe'+ QD + Qs
Qe + QD + QS +
Qe + QD + QC
Qe + QD + QC +
QE + QD + QC +
QE + QD + QC +
QA
QA
QA
QS
Qs + QA
• AaquiftId to oompIeIo~ H in F'II3. END.........,.,..... 11_ by modulo 16 ....
malnder of data word count. Counter F is not required for block sizes less than 33.
CounIarE isnotroqulred Iorblook .... Iees_,7. Single _
transmission isa trtvtaI
Implementation
DATA
FLOW
Block Length Control·
solution
r---
5H SELECT COMMAN~
RAM ADDRESS CHANGES ON
TRANSITION ST 3 TO ST 2
-A--f-A-'--I-A-2--1-A-3-+-A-4-+-A-5-+-A-S-+-A 7-+-A·B-t--A-9-
DIRECTION
ENABLE " 0H '
00
TIMING DATA FLOW
R~M TO EXTERNAL DEVICE
I
~-~-~~
- - - - - - - - - - - - - - - - -
LOAD 0 LOAD'
I~~_-I
LOAD 8 LOAD 9
lAC
TIMING DATA FLOW
EXTERNAL DEVICE TO RAM
~
I
~-
- - - - - - - - - - - - - - - - I
ENABLE ENABlE
SOURCE 0 SOURCE 1
~
ENABLE
~
ENABLE
SOURCE 8 SOURCE 9
lwe
Fig 4 6085 timing and interface signals. Register
contents reflect state controller interaction with
computer commands. Control states reflect state
flipflop outputs_ Signals common to transfer in either
direction are grouped. Current RAM address starts at
6.6
A and decreases during successive cycles. Memory
timing, shown for data flow both from and to RAM,
relates to RAM timing requirements for Fig 1 and Fig
2, respectively
.ln$l.-c;it•., c.ntron..... llWr•••.,. MIC;,.,.r..,••.,..,fitroughout
.
, . . . . L:, .. :" ..
J.
. ackn~wtedge; .(b) ih~ RAM'sl1ighdensity,4-bit data lI/Gl'd,
.6.ili/irectional databu~; and simplified ~UlilcontroHinein,.
terrace; and (c) the eo\iuter sY!lci:lroniJed load:, inc(emelt't,
a,qd decrement (:On trois, and alsG its3-l>tl'.t~ '\lutP.~t· and
casclidingcapabilitiea.. 4dditionl'.lly" the ~Pllnse' ai/.d
operating speeds of the RAM and counter are compatible
with the microprocessor clock.
Figs 1, 2, and 4 show the configuration a!ld timing rela·
tionships achieved by using these components.
Microprocessor choice establishes the system clock fate and
the method of passing control between the microprocessor
and the data controller. The method of implementing the
data controller, which meets the dual requirements of
simplicity and high throughput, restricts RAM selection. In
Figs I and 2, t Re and twe cannot exceed two clock periods.
When moving data to external devices, the devices must be
able to function within the constraints of t A• and tEA' When
moving data to the CPU memory, its write requirements, tw
and tow, must be le~s than one clock period. Because of the
controller stru.cturc, t DU alld tWR must both be zero, a restric·
tion satisfied by many RAMs currently available.
Adaptation
Pistributed data port servicing is the primary functional reo
quirement of the data controller, and the specific number of
ports is a parameter written into the Boolean expressions
Implemented by a member of the PAL family. The inherent
flexibility arising from implementation of many of the logic
functions by easily modified Boolean expressions can be
demonstrated by extending the application requirements to
include program control of the data block length. Now, the
design objectives are to incorporate' this feature with
..'
,'.
. ..... .
minimal~rdWat:e reconfigtjflltion lind, to retain all the
Operational attributes of the original LiMA controller.
?\lthougn ·tl/:etrtate sequencer remains conceptually Ull·
chaflged; its. int~l'll<:tion with the data !!o.unter. must be
'1l04i£iedJD jm.p~ment~ vllrillblehlock length. The original
cQncept hils fixed data block length,with the data counter
starting at all h and decrementing to a .predeterl\1ined end
coullt. Its advantages are that the CPU interface is mini·
mi~ed and th.at all data ports are serviced during each DMA
cycle. To implement the variable block length feature, the
CPU loads the data counter with the' actual count; then duro
ing data transfer, the state sequencer decrements the count
to 0, the end count that terminates the operation.
It is desirable to implement the state sequencer and data
counter on a single programmable chip while maximi~ing
the data counter length. To achieve this, a 16R8 program·
mabie logic chip replaces the 16R6 used previ~usly. This
change increases the nU.mber of registers by two at the ex·
pense of the two gated outputs. The chip configuration now
offers eight data inputs; eight 0 registers, each with an in·
verting output; a register clock input; and a 3·state control
input.
Of the eight registers, two are required for the state se·
quencer, allowing a maximum block length of 64 in a single·
chip implemel)tation. However, three control lines are reo
quired:HOLDA and DTRANS, as in the original concept, plus
a software generated LOADA, which transfers the content of
the data bus to the data registers. Additionally, the LoADA
command must be used to initialize the state counter (Fig
5). With thi.s approach, five inputs remain for the data bus,
limiting the block size to 32 words.
An alternative configuration using only three data bits
allows loading of the six flipflops in two instruction cycles
a
~!
STATE
SEOUENCER
DATA COUNTER
DATA COUNTERS
DE = LOAD A • 24 ;, DE
00
DC
oa
OA
IOH
+ 0H • OG} ;, 0H • 0G • DE 100
T
Dc +
DB + 0A}
= LOAD A.' 23 + ODIOH + ,0wOG} + 0H • 0G 100 IDC + DB ;, DA} + 6i) . Oc ·68· 0;;1
= LOAD A • 22 + DC 10;:; + OH • OG} + 0H • 0G 10c lOB + 0A} + Oc •68 . 0;;)
= LOAD A' 2' + Oa IOH + OH • OG} + 0H' 0GIOa' OA + 08 'GA}
= LOAD A • 2° + DA 10;:; + OH • OG} + OH • 0G • 0;;
STATE CONTROLLER
0G = LOAD A IOH •
OG • OTRANS
+ OH • 0G •
DH " LOAD A rOH • 0G • HOLDA + Ow
H5iJ5A
+ 0H • OG}
OG + 01< : 0G IDE
+ 00 +
C)C;
+ Oa + O~})
Fig 5 Adding program control over block
length. Hardware configuration and
Boolean'expressjons are modified to im·
plement progral\1 control of data block
length. Data input limitation prevents use
of orie register, restricting block length to
32 words
. '
Single-chip Controller Increases Microprocessor Throughout
CPU
DATA BUS
I
CPU DECODED
COMMANDS
FROM CPU
TTT~
22
21
tJ
CLOCK
HOlDA
ilFOEaoacOii5A
r-JI'
RESET DTRANS LOAD A LOAD B
PAL 16R8
illJ---lJJ
QATA COUNTER
0t1
QG
L-L
STATE
SEOUENCER
DATA COUNTERS
OF
= LOAD B • 22
+ OF
{o,:; + Ow OG) + 0H • 0G • OF (OE + 0D + Dc + Os + 0A)
(0,:; + 0H • OG) + 0H • 0d [ 0E (OD + 0c + 0a + 0A) + OE . On . Oc' OS . CAl
(0,:; + 0H' OG) + 0H' 0G[OO (OC + Os + 0A) + On·
Os· CiAI
+ Oc (0,:; + 0H • OG) + QH • 0G [DC (Oa + 0A) + Oc . OS' CAl
0E = LOAD a • 2' + 0E
ac'
00 = LOAD S· 2°+ 00
Dc = LOAD A • 22
Os
=, LOAD A' 2' + Os (OH + 0H • OG) + 0H • 0G (OS' 0A +
0A = LOAD A • 2° + 0A
(0,:; +
0H •
OS . CA)
OG) + 0H • 0G • CA
Fig 6 Extending block length.
Additional modification in·
creases block length to 64 words
by using all Internal registers. All
capabilities of previous con·
figuration have been maintained
across both modifications
STATE CONTROLLER
0G
0H
= RESET (OH . 6G ',DTRANS + 6H . 0G . HOLDA + QH • OG)
= RESET [0,:; • 0G • HOLDA + 0H • OG + 0H . 0G (OF + 0E + 00 + Dc
by implementing a second load command, LOADB. Tbe DMA
controller now handles block lengths as long as 64 data
words, and the RESET command can be used to initiali~e the
state counter as in the original concept (Fig 6).
+ Os + 0A))
Bibliography
"MCS·B5 Users Manual," Intel Corp, Santa Clara, Calif, 1978
J. Nissim, "DMA Controller Capitalizes on Clock Cycles to Bypass
CPU," Computer Design, Jan 1978, pp 117·124
"Programmable Array Logic Handbook," Monolithic Memories
Inc, Sunnyvale, Calif, 1978
Summary
Generally, a design approach and its means of implementa.
tion should be complementary. Specifically, the controller
design objectives are met by utilizing a state sequencer, and
implementation compatibility is assured by such features of
semicustom logic as multiple storage elements with internal
feedback paths, dense gating arrays, and interconnection
flexihility.
The process of creating a state sequencer to solve a
design problem results in a series of Boolean expressions
that define the controller capability and the gate array that
must be effected. Several partially dedicated gating and
register arrays constitute the semicustom logic family. After
"the most suitable arrily configuration is selected, the inter·
connections, as expressed by Boolean statements, are com·
pleted to implement the design. This creates Ii unique logic
pattern whose dense gating contributes to chip count
minimization. Design variations can be accommodated by
restructuring the gating arrays with minimal hardware
reconfiguration. Thus, the system can be tailored to the
original operating requirements and yet be easily adapted if
modifications are desired.
A.A
Alan W. Bentley is a design specialist,
technically responsible for the develop·
ment of a high speed data processing
and display system at Cubic Corp. He is
also an instructor in the Engineering
Department of San Diego Community
College. He has a BS degree in electrical
engineering from Tufts" University, an
MBA from United States International
University, and an -MA from San Diego
State University.
Reprinted by permission from Computer Design Magazine.
Copyright Computer Design Publishing Company, June 1981.
FPLA ARBITER CONCEPT ADAPTS
TO APPLICATION NEEDS
Reid programmable logic implements efficient. easily customized arbiter
whose versatile Boolean statement format meets numerous system
requirements
AI,n
w. Bentley
Cubic· Corporation
9333 Balboa Ave, San Diego, CA 92123
T
oday's trends toward shared resources, multiprocessing, and decentralized, bus oriented system organization underscore the demand for arbiters that work independently and iss\le grants according to predetermined algorithms. Functionally, a requirement for
stable processing of system requests is created when
several prOCessors use; a common device and each requests service asynchronously; It is the arbiter'S task to
issue grants foT sequential access in accordance with a
preestablished algorithm. By using a versatile Boolean
statement format to express its algorithms, an arbiter
can be cU.stomized' to iriterface . with single-array,
multiple-array, and hybrid logic con(iguration~. Designing arbiters to befiexible in impleMenting algorithms
can help to meet the demand for cost,.effective data pro'cessing systems and bring heretofore expensive, hence
scarce, devices into wider use.
'
Arbiter .Interface
From the system's perspective ofiheinterface, when a
system is ready for service from the device, it raises arequest 1i11e. The arbiter responds by issuing a grant to the
system that clear's it to conduct transactions with the
device. Upon cpmpletion of service, the system drops its
request line. 'the arbiter, in turn, cancels the grant and
is then free to issue a' grant to the next pending request
. Stable system requests are neCessary h.ecauseall requests and grants are evaluated each clock period. These
requests are generated .asynchronously and are synchronized thropgh a set of inpllt latches: If a 2-phase
balanced clock 'is used, with requests synchronized on
phase 0 and grants' iss tied o~,released on phase 1; the
maximum time from a system request for service until
syncbronization of that request is one clock period.
Minimum time from completion of the transaction to
release oftl\e synchronized request is the system's internal delay, as it drops the request line, plus. tbe setup time
oftbe synchronizing·iatches. At the completion Of a
transaction, there isahalf-clock period. the time frOIn
phase o to phase 1; when Ii unique signal combination
exists-a grant issued toa system that does not bave a
synchronized request. During this half-period, all other
synchronized requestS are examined and, according to
tbe servicing algorithm, the recipient 'oCthe next sequential grant is oetermined. Thenj' on phase 1, the existing
(unsolicited) grant is canceled atlci the next grant issued.
c
6-9
FLPA Arbiter Concept Adapts to Application Needs
PI<~
~
~~
LGUARDBAND
IlAUNCED 2·PHASE CLOCK
fbi
~
~
GUARD
~
~~~~~-l
BAND
UNIIAUNCED 2·PHASE CLOCK
ICI
G•• RESET· R.
iii,· .... R, (ti,
+ ••• + Gy +
G, ••••• Gzi
+ Gol
~ ~ ~TRANSFER-l--IDLE--J..r~
r---MoDIFIER
---j
.'MAINTENANCE /
fd)
Fig l· Arbiter circuitry, timing, and grant expression format .. ln (ai, 56 to SO are system requests.
Latch outputs R6 to RO .are synchronized requests
. that arbiter algorithm convarts to systam grants,
G6to GO. Unbalanced clock phases increase guard
band (b and cl, with maximum guard band needing
only one phase. Logic aquation for algorithm (dl
combines four subaxpressions
The sum of the requesting system's internaldelay in
dropping. its request line, the synchronizing iatchsetup
time,and on~-half the clock period,act as a/guard band
to ensure separation of systems interacting "w~th the
device .. Arbiter clock frequency, therefore, is a major
factor in determining guard band: time. For a given ar!;liter clock frequency, the guard band can be increased
by unbalancing the clock, increasing the time between
phase 0 and phase I to more than ha,lf the clock period.
The limiting case occurs when the time between phase 0
and phase 1 is increased until it equals. the clock period.
This makes phase 0 and phase 1 coincident, requires
only a single-phase clock, and maximizes the guard
&·1'0
band for a given clock frequency. The limiting casc.
relies on the propagation delay of the latch flip flops and
the setup time of the array logic grant flipflops to ensure
a delay of one clock period between release of the syn··
chronized request and the associated grant. Start
of the guard band signifies completion of the current
transaction, and guard band time is used to determine
the next grant recipient; then, at the start of the next
clock period, the current grant will be canceled, and,
if one or more requests are pending, the next grant
issued.
Octal D flip flops (LS273) are used to synchronize the
input requests, and a programmable gate array (16R8) is
used to evaluate the requests and issue grants. ID.the
i~phase clock, phase 0 synchronizes requests and ph"ase
I issues grants (Fig I). Both the octal flipflops and the
logic array are 2O-pin packages. In addition to the clock
and 3-state control inputs, the logic array has 8 data inputs and 8 D flipflop outputs. The Q output of each
flipflop is inverted and buffered, and is a 3-staie output;
the Q output is returned to the array internally, where
the 8 flipflop settings and the 8 data inputs are complemented and are available in both original and complement· form at 8-input OR gates. There are eight OR
gates, each forming the D il1Put for one of the eight
flipflops.
.
By programming through fusable links, the set condition of each flipflop is established from the eight data
inputs, the current state of the eight flipflops, and the
complements of both. Each flipflop's set condition can
be represented as a Boolean expressi()n of up to eight
ORed statements. Each statement is created by ANDing
terms drawn from the data inputs, the flipflop status,
and their complements. Limiting parameters of this
configuration are the 8 data inputs and the fIXed 8-term
OR gate at the D input of each flipflop. Boolean expressions implemented througp theprograminable fuses
must be true when the flipflop is to be set or maintained
in th.e set state, and false when the flipflop is to be reset
or to remain reset.
Single-Array Configuration
t.ny of several
servici~g algorithms, expressed as
Boolean statements, can be implemented with a single
logiC array that will process service requests for up to
seven systems. The first. two' algorithms· represent the
()rganizational extremes. "Priority service" algorithm
has a strict priority ranking {rom R6 to RO: a grant will
be issued only if no higher priority system has a pending
request. The other extreme. is the "polled service"
algorithm; here, aflsystems place equal demand on the
device arid are servicCd through Il rotating, ()r "roundrobin," method. In. this case, when one transaction has
been completed, the' following grant is issued in
response to the next ranking reqti~st (eg, next lower
number). Circular continuity is maintained by having R6
follow RO in the granting sequence. Between .the extremes, algorithms 3 and 4 represent hybrid organiza.tions. The "executive and polled service" algorithm
allows a single, high priority executive sy,stem (R6), with
the remaining systems (RS to RO) equal and polled in a
FLPA Arbiter Concept Adapts to Application Needs
ALGORITHM 1: PRIORITY SERVICE
:Reffi. RS [GS • As + G4 • Iii + G3 • R3 + G2 • R2 + G' • FIT + GO· Ro + GS • Go • G3 • G2 • Gi • GO + GS)
:Reffi. RS [M(GS + G4. Iii + G3. ii3 + G2 • R2 + G, • Ai + GO. liO + GS· Go. G3. G2. (IT. GO) + GS]
z :Reffi. R4 [M. As (GS + GS + G3 • R3 + G2 • R2 + G, • FIT + GO. iiO + G6. GS • G3. G2 • lIT • GO) + GO)
- REm • R3 [~. liS" • Iii (GS + GS • G4 + G2 • R2 + G, • FIT + GO. 1ili • G6 • il5 . ll4 • ~ • lIT • imi • G3]
- ~ • R2 [I!! • lf5" • "Iii • "Ii! (GS + GS • G4 + G3 + G, • lIT + GO. 110 + "GJ. ll5" • ll4. l!3" • lIT • imi + G2)
-REm. R, [Re • As .114·113 .11} (GS • GS + G4 + G3 •. G2 • Go."1ili • G6. liS. '(li.1l'3. ~.~) + G,)
- REm • AO [Re • As. R4 • R3 •Ai" • FIT (GS • GS • G4 + G3 + G2 + G, + GS • G5 • G4 • G3 • G2 • cm + GO]
GS GS
G4
G3
G2
G,
GO
&
ALGORITHM 2: POLLED SERVICE
GS -
REm.
G, • Rf • G2 • Ai". 1'ii + G3 • R3. R2". FIT +
• Gs • G4 • G3 • G2 • in • GO + GS]
•
[116 (GS + GO· Ro + G' • Ai • Ro + G2 • Ai • Ai • Ro +
• IllI • G4 • Il3 • G2 • en •
....
Figure 2. AND-OR Cell
INPUTS, FEEDBACK AND 1/0
CLOCK
OC
,.;..
r--
"'
....
h..
c
ot--
D
~
~~
~
Figure 3. Registered Cell With Internal Feedback
,
.
INPUTS, FEEDBACK AND 1/0
...
W
...
1/0
....
lII:::
....
"'"
Figure 4. Programmable I/O Cell
6-19
PAL: Quick Turnaround Alternative to Gate Arrays
x1_
Z1
.
x2~
.
xm_
Z2
Zn
~01
01+
COMBINATORIAL
SUBNETWORK
,.---J
3
4
5
6
J
x1
~
10
~r-~
""
11
12
13
14
15
.2
......it
.....
....
""
Figure 6. Section of a PAL16R6 Logic Diagram
6·20
Z1
...
8
9
3
19
~~
OC
01
PAL: Quick Turnaround Alternative to Gate Arrays
PAL20X8
The Second Generation: PAL24
The PAL24 is an evolution of the PAL20 and similarly has
combinatorial and registered partS. However, in the combinatorial
circuits, it is now possible to decode simultaneously up to 20
inputs. The registered parts now have as many as 10 outputs,
but the important thing to note about the architecture of the
registered part is the addition of a new cell: "ANO-OR-EXOR" as
illustrated in Figure 7. The significance of the cell is for
implementing various types of counters. Figure 8 shows the
logic diagram for the PAL20X8 that can be easily programmed
to implement an octal counter.
PAL Performance: Present and Future
The most critical parameter for the PAL performance is the
propagation delay for the combinatorial cells and the set-up
time for the registered cells. These two parameters are equal in
the PAL family and are listed below as function of time:
tpo
= tsu
1979
1981
1982
1983
40 ns
35 ns
25 ns
15 ns
These numbers are worst case fo~ commerc.ial temperature and
supply ranges. Add 5 ns to get the worst case numbers for
military temperature and supply.
Figure 8. PAL20X8
PAL'
VB
Other Alternatives
PAL Advantages Over SSIIMSI
PAL -
Industry Standard
The PAL has been accepted as ,an industry standard and is
being manufactured under license by National Semiconductor
(NSC). In addition, it was announced by Texas Instruments (TI).
It is very significant to note that TI and NSC, who are the leaders
in the TTL market have recognized that PAL will eventually
replace the present TTL. The PAL20 was adopted by the JEOEC
42.1 Committee as a de facto standard and it further proposed
that the PAL24 be also adopted.
HAL -
Hard Array Logic
The HAL to a PAL is the same as a ROM to a ,PROM. Instead of
having a fuse mask, a metal mask is used. This technique
reduces the PAL price almost by a factor of two. The HAL is
similar to a gate array. Both are customized in the last
fabrication stage by applying a unique metal mask to otherwise
standard wafer. However, the HAL is the only gate array in the
market with a fusible prototype.
The PAL can replace from 4"10 SSI/MSI and consequently it
reduces the board space required for a function. It also
increases reliability by moving the interconnections from the
less reliable PC solder connections to the si(icon Chip, Since the
PAL is programmable, it expedites the prototyping and debugging
process as compared to 90nventi9nal SSIIMSLl,.ast but not
least, is the PAL security fuse which makes it impossible to copy ~
the contents of a PAL.
'
-.:..
PAL vs Gate Arrays
Gate arrays typically have higher gate density than a PAL.
However, they have several drawbacks. The turn-around time
for gate array is 2-4 months for the first silicon and typically two
iterations are required to get a completely functional unit. Thus,
the actual turn-around time is
lLOAO 06
1COUNT
lCARRY OUT
~
PAL: Quick Turnaround Alternative to Gate Arrays
Following the logic equations, a FUNCTION TABLE is given.
Note that the FUNCTION TABLE includes some basic test
information:
FUNCTION TABLE
CLK joe Il 10 07 06 05 04 03 02 01 DO JCI JCO Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
,CONTROL
,CLK joe
INSTR
Il 10
-INPUT-00000000
76543210
CARRY
jCljCO
-OUTPUTQQQQQQQQ
76543210
COMMENTS
(HEX VALUES)
------------------------------------------------------------------------------,BASIC LOAD TEST AND INCREMENT-WITH-CARRY TESTS
C
L
H L
LLLLLLLH
X H
LLLLLLLH
LLLLLLHL
H H XXXXXXXX
C L
L
H
LLLLLLHH
X H
LLLLLLHH
L
H L
C
LLLLLHLL
L
H H XXXXXXXX
C
L
H
LLLLLHHH
LLLLLHHH
H L
C L
X H
LLLLHLLL
H H XXXXXXXX
C L
L
H
LLLLHHHH
X H
LLLLHHHH
L
H L
C
L
H
LLLHLLLL
L
H H XXXXXXXX
C
H L
C
L
LLLHHHHH
X H
LLLHHHHH
C
L
H H XXXXXXXX
L
H
LLHLLLLL
C L
H L
LLHHHHHH
X H
LLHHHHHH
LHLLLLLL
L
H H XXXXXXXX
C
L
H
LHHHHHHH
L
H L
C
X H
LHHHHHHH
C
L
H H XXXXXXXX
L
H
HLLLLLLL
C
L
H L
HHHHHHHH
HHHHHHHH
L
L
L
H H XXXXXXXX
L
H
LLLLLLLL
C
,COMPLEMENT LOAD TESTS
HHHHHHHH
C
L
H L
L
L
HHHHHHHH
L
H L
HHHHHHHL
C
X
H
HHHHHHHL
C L
H L
HHHHHHLH
X H
HHHHHHLH
HHHHHLHH
L
H L
C
X H
HHHHH1.HH
C
L
H L
HHHHLHHH
X H
HHHHLHHH
C
L
H L
HHHLHHHH
X H
HHHLHHHH
C
L
H L
HHLHHHHH
X H
HHLHHHHH
C
L
H L
HLHHHHHH
HLHHHHHH
X H
LHHHHHHH
L
C
H L
X H
LHHHHHHH
C
L
H L
HHHHHHHH
HHHHHHHH
L
L
,SHORT COUNT SEQUENCE - CONSECUTIVE COUNTS
C
L
L L
XXXXXXXX
X H
LLLLLLLL
LLLLLLLH
L
H H XXXXXXXX
C
L
H
C
L
H H XXXXXXXX
L
H
LLLLLLHL
C
L
H H XXXXXXXX
L
H
l.LLLLLHH
L
C
H H XXXXXXXX.
L
H
LLLLLHLL
,COUNT HOLD CHECK - CO GATING CHECK
HHHHHHHL
HHHHHHHL
L
H L
C
X H
H H XXXXXXXX
C
L
L
L
HHHHHHHH
C
L
H H XXXXXXXX
H H
HHHHHHHH
C L
L H LLLLLLLL
HHHHHHHH
L
L
C
L
H H HHHHHHHH
LLLLLLLL
L
H
,TEST OUTPUT CONTROL (jOC) FOR THREE-STATE OUTPUTS
X H
X X XXXXXXXX
X X
ZZZZZZZZ
6·24
LOAD (01)
INCREMENT
LOAD (03)
INCREMENT
LOAD (07)
INCREMENT
LOAD (OF)
INCREMENT
LOAD (IF)
INCREMENT
LOAD (3F)
INCREMENT
LOAD (7F)
INCREMENT
LOAD (FF)
INCREMENT (ROLL OVER)
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
(FF)
(FE)
(FD)
(FB)
(F7)
(EF)
(OF)
(BF)
(7F)
(FF)
CLEAR
INCREMENT
INCREMENT
INCREMENT
INCREMENT
TO
TO
TO
TO
(01)
(02)
(03)
(04)
LOAD (FE)
INCREMENT TO (FF) jCO=L
CI INHIBITS COUNT AND CO
HOLD SEL INHIBITS COUNT ONLY
INCREMENT TO (00)
TEST HI-Z
PAL: Quick Turnaround Alternative to Gate Arrays
Finally. it is highly recommended that a description be a part of
this computerized data sheet.
THIS IS AN 8-BIT SYNCHRONOUS COUNTER WITH PARALLEL LOAD, CLEAR, AND HOLD
CAPABILITY. THE LOAD OPERATION LOADS THE INPUTS (07-00) INTO THE OUTPUT
REGISTER (Q7-QO). THE CLEAR OPERATION RESETS THE OUTPUT REGISTER TO ALL LOWS.
THE HOLD OPERATION HOLDS THE PREVIOUS VALUE REGARDLESS OF CLOCK TRANSITIONS.
THE INCREMENT OPERATION ADDS ONE TO THE OUTPUT REGISTER WHEN THE CARRY-IN IS
TRUE (/CI=L), OTHERWISE THE OPERATION IS A HOLD. THE CARRY-OUT (/CO) IS TRUE
(/CO=L) WHEN THE OUTPUT REGISTER (Q7-QO) IS ALL HIGHS, OTHERWISE FALSE (/CO=H).
THESE OPERATIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
OPERATIONS TABLE:
loe
CLK
I1
H
L
L
L
L
L
X
C
C
C
C
C
X
L
L
H
H
H
10
ICI
07-00
X
X
X
X
H
L
X
X
X
0
X
X
Q7-QO
OPERATION
-------------------------------------------------X
L
H
L
H
H
Q
Z
L
Q
0
Q
PLUS 1
HI-Z
CLEAR
HOLD
LOAD
HOLD
INCREMENT
-------------------------------------------------CAD Software for PAL
PALASM
PALASM is a software which translates the LOGIC EQUATIONS
to a fuse pattern. The output of the PALASM is in.a format
compatible with either a PAL or a PROM programmer. The user
needs to specify only his "block-box" description and the
programmer will blow the corresponding fuse pattern. '
PALASM also uses the FUNCTION TABLE to perform two
critical operations for the sem!-custom user:
• Design Verification - Each entry of the FUNCTION
TABLE is checked against the logic equations and any
inconsistency is flagged as an error.
• Test Vectors - Each entry of the FUNCTION TABLE is
translated to a universal test vector. so there is a way of
testing the customized PAL once it is fabricated
PALASM is written in FORTRAN IV and it resides on an IBM
370/168. Users can access the program by calling the NCSS
time-share network. Additionally. Monolithic Memories makes
the source code of PALASM available to users at no cost.
PALASM is presently running on quite a few computers at
customer Sites. Several examples of such computers are the
DEC PDP/11. DG NOVA. HP2100. MDSSOO. and many others.
An example of the test-vectors generated from the FUNCTION
TABLE of the octal counter is given at right:
1
2
3
4
5
6
7
8
9
10
11
COI0000000IXOHI,LLLLLLHXI
CIXXXXXXXXIXOHLLLLLLHLOI
COII000000IXOHLLLLLLHHXl
CIXXXXXXXXIXOHLLLLLHLLOI
COIII00000IXOHLLLLLHHHXl
CIXXXXXXXXIXOHLLLLHLLLOI
COIIII0000IXOHLLLLHHHHXl
CIXXXXXXXXlxOHLLLHLLLLOI
COIIIII000IXOHLLLHHHHHXl
CIXXXXXXXXlXOHtLHLLLLLOI
COI11111001XOHLLHHHHHHXl
12 CIXXXXXXXXIxOHLHLLLLLLOI
13 COIIIII1101XOHLHHHHHHHXl ~
14 CIXXXXXXXXIXOHHLLL~LLOI - . : . .
15 COIIIII1111XOLHHHHHHHHOI
16 CIXXXXXXXXIXOHLLLLLLLLOI
17 COI11111111XOLHHHHHHHHOI
18 COOIII11111XOHHHHHHHHLXl
19 COI01111111xOHHHHHHHLHXl
20 COII0IIIIIIXOHHHHHHLHHXl
21 COIII011111XOHHHHHLHHHXl
22 COIIII01111XOHHHHLHHHHXl
23 COIIIII0IIIXOHHHLHHHHHXl
24 COIII111011XOHHLHHHHHHX1
25 COI11111101XOHLHHHHHHHXl
26 COIIIIIIIIIXOLHHHHHHHHOI
27 COXXXXXXXXOXOHLLLLLLLLXl
28 C1XXXXXXXXIxOHLLLLLLLH01
29 C1XXXXXXXX1XOHLLLLLLHL01
30 C1XXXXXXXXIXOHLLLLLLHHOI
31 CIXxXXXXXXIXOHLLLLLHLL01
32 COOI1111111XOHHHHHHHHLX1
33 CIXXXXXXXXIXOLHHHHHHHHOI
34 CIXXXXXXXXIXOHHHHHHHHH11
35 CI000000000XOLHHHHHHHH01
36 C1111111111XOHLLLLLLLL01
37 XXXXXXXXXXXXIXZZZZZZZZXl
PAL: Quick Turnaround Alternative to Gate Arrays
Testability
Low-Volume
The test vectors which resulted from the FUNCTION TABLE are
referred to as basic test vector and they indeed guarantee that
the part is functioning according to each entry in the FUNCTION
TABLE. However, to increase the confidence level that the
device will not "misbehave" (when unspecified inputs are
applied) it is necessary to insure that all nodes are toggled
during the testing. Monolithic Memories has an automatic testvector generation program which is used to test HAL, the
software uses the basic test-vectors as seed vector and from
there it iteratively adds more test vector'S until all nodes have
been toggled.
Low-volume requirement has been a continuous problem to the
military market place, but with PAls obviously the low-volume
requirement can be satisfied by customizing as little as one chip
at a time.
It is important to note that for testability it is always necessary to
have an initiallization mechanism, e.g., in the octal counter when
10 = 11 = 0, the counter is cleared to all zeros.
HMSI: Dedicated HAL Functions
In general, the PAL and HAL are programmed according to user
specifications. However, as an aid to customers, we make
certain dedicated 24-pin HAL. For example:
,. Octal Counter
• 10-Bit Counter
• 16:1 MUX and several other "new" TTL functions
PAL and the Military
Bipolar Technology
The PALs are fabricated using bipolar Schottky technology
which has been proven to be much more reliable at extreme
temperatures than the MaS technology. The PAL is being
programmed by blowing TiW fusible links which has proven
reliability on PROMs. The fusible link technique is much more
reliable than the EPROM or EEPROM which use a stored
charge that leaks with time and has a questionable operation at
the military temperature range.
Obsolete SSI/MSI
Anytime the demand for ICs exceeds the available supply, the
semiconductor manufacturer stops producing the least profitable
ICs. As the labor cost increases and the silicon cost decreases,
SSI/MSI devices (which are labor intensive) are the first to
become obsolete. With the fast turn-around time of the PAL.
These TTL devices can be quickly reduced by PAL.
Leadless Packages
The PAL is also available in the space saving lead less chip
carriers (LLC). These carriers are made according to JEDEC
outline (Type B) with 50 mil centers and 75 mil package
thickness. The 20-pin LCC is 350x350 mils and occupies only
40% of the space required by the equivalent of 20-pin DIP.
Military Processing
PAls, like all other Monolithic Memories' products, can be
processed to meet the HI-REL requirements of MIL-STD-883B.
This processing is available for both LCC and DIP packages
and also for dice where they are visually inspected by method
2010B and are shipped in a standard waffle pack.
Summary
The PAL family is already a valuable semi-custom approach in
the commercial market place. It will even be more valuable to
the military market that has been looking for a solution to the
problem of low-volume requirement.
The PAL, which is implemented in bipolar technology, presents
a high reliability programmable solution to the demanding
needs of the military market.
High Speed/Low Cost Fuse Link Arrays
Compete with TTL 74S/LS
John BirknerlWescon 78
Random Logic has remained virtually impenetrable
by today's state of the art LSI technology. This fact is
dramatically evidenced by the high percentage of TTL
74S/LS logic found in currently introduced small
board computers based on MaS microprocessors,
and also high performance minicomputers based on
bipolar bit slice chip sets.
LSI has vastly reduced the well defined, regular
logic functions found in these systems because of the
wide appeal, thus, high volume and low cost. When the
regular functions are applied to the specific needs of a
particular systems manufacturer, however, individual
interfacing requirements demand additional logic not
available in LSI functions. The present solution is to
use standard SSI/MSllogic functions at a high cost in
chip count, assembly/test labor and reliability.
To answer the need for LSI Random Logic, a family
of fuse Programmable Array Logic devices I PAL I has
recently been introduced. This family meets the speed
requirements of competing TTL SSI/MSI with typical
25ns propogation and set up delays while reducing
chip count 4 to 1.
Total system cost using PALs is comparable with
SSI/MSI, yet design time and inventory costs are
reduced. The 15 part family utilizes the latest
improvements in bipolar Schottky fusible link
technology with the proven reliability track record 01
bipolar PROMs. Titanium-tungsten fuses and emitter
follower arrays are used to achieve the 25ns delays
through three levels 01 logic.
DEFINING THE PROBLEM
Increasing the logic function density per chip is the
name of the game in the integrated circuit industry.
The standard procedure is to identify a logical block
which is common to many applications and users, and
then to integrate that function onto a single chip. The
problem with integrating the random and irregular
functions which are so prevalent in today's digital
systems is to identify a common denominator which
can provide a generalized solution that meets cost and
performance goals.
A Decade of TTL
The growth of TTL SSI/MSI during the last decade
provides a wealth of knowledge about the elements
that designers need to build digital systems. This
family of devices was defined by many users and
manufacturers over many years and is, therefore, an
evolutionary, emperical data base from which we can
extrapolate generalized logical primatives for LSI
implementation.
the basic gates, AND-OR-INVRT gates, Multiplexors,
de-multiplexors and priority encoders. More complex
combinatorial includes arithmetic functions such as
comparitors, adders, and ALUs. The common
denominator among the simple combinatorial
elements is the sum of products. An additional
primative in the arithmetic elements is a high density of
Exclusive-ORs.
BOOLEAN
TRANSFER
FUNCTION
INPUTS
OUTPUTS
Figure 1: Combinatorial function
Sequential includes all the registered functions
such as counters, shift registers, registered multipliexors, accumulators, and registered encoders. The
common denominator of these sequential elements is
a register driven by a combinatorial element whose
inputs are both external and internal from the register.
All of the sequential devices may be described as
simple state machines.
CLOCk
BOOLEAN
TRANSFER
FUNCTION
OUTPUTS
Figure 2: Sequenlia' Functfon
Both the combinatorial and the sequential functions
may have the optional characteristic of three-state
outputs. That is, the output function may be
disconnected as a driving source by placing the
outputs in a high impedance state (High-Z)
OUTPUTI
The Primitives
SSI/MSI functions can be classified as either
combinatorial or sequential. Combinatorial includes
Figure 3: Three--St.le Output Gltl
6·27
High Speed/LowCost Fuse Link Arrays
Definition of Terms
Before we can rigorously define the basic logical
primitives, we first need a precise language which
unambiguously describes the transfer functions.
Definitions:
Equality, after the propogation time, tpo, from any
input change .
.= Replaced by, after Ihe propogation delay, tpo,
from the low to high transition of the clock.
IF Conditional Equality, after the propogation delay,
tpo, from the enabling condition. Otherwide, high
impedance (High-ZI.
Complement, Boolean operator, placed to the left
of a Boolean variable.
AND, Boolean operator.
+ OR, Boolean operator.
:+: XOR, Boolean operator.
() Parenthetical separators.
hierarchical order / • + :+:
where / is evaluated first.
A sequential function is described as,
V:= fiX, VI
IFrEI V1 = V
CLOCK
Y'
Combining sequential, combinatorial and threestate we now have,
IF I f1IX, VI I Z = f2(X, V)
V: = f31X, VI
IF ,E)
V1 = V
Given these definitions, we can formulate rigoro~s
logical descriptions of stl\ndard SSI/MSI functions.
Rigorous Statement of Primitives
We can now state, in equation form, a generalized
set of equations suitable for LSI implementation.
For an input vector X and an output vector V, a
combinatorial function is described as,
,.
V = fiX)
CLOCK
'eX)
where f is Boolean Sl-lm of products transfer function.
A three state combinatorial function is described as,
IF (.f1IXI)
Z =;12(Xi
The above generalized Boolean functions are a
super set of virtually all of the standard SSI/MSI
fu·nctions.
For an LSI implementation to provide a better
solution than existing SSt/MSI it must meet the
following requirements:
1. Reduce package count
2. ~atch or improve pl;!rformance.
3. Reduce System Cost.
The Programmable -Array Logic (PALl family was
designed to meet these· requirements.
6·28
High Speed/Low Cost Fuse Link Arrays
SEOUENTIAL EXAMPLE:
COMBINATORIAL EXAMPLE:
4 to 1 Mux.wlth three-state Outputs (74LS253)
4 SIT. UP/DOWN COUNTER (74LS169)
4 tn 1 Mux Logic Symbol
Up/Down Count.r Logic Symbol
'o--~>----------.-------.
,co
---------'------:::I::::r-,
,C' --------,.,----f-+±...-......
'C2
--------:-~:::t:ft;[)
'C3
------~:$*3)
2CO ~-----t-l-+ft-L-..,
2C'
--------.t=1==¥f=L..)
2C2
--------~==FL.J
2C3
----~--~===f=L-'
20
_~~_~
4
_ _-+_ _ _ _
~
to 1 Mux Logic Dlag,r.m
Up/Oown Counter LogiC DI.',.rn
EOUATIONS:
EOUATIONS:
IF( 11G)
1Y = IA*/B*1CO
+
A-/S-1C1 +
lA-
S-1C2 +
A- B-1C3
IF( /2G)
+
+
2Y = IA-/S-2CO
A-/S-2C1
IA-S'<2C2 +
A-S-2C3
OA: = LOAO*A + ILOAO-OA :+:
ILOAO-poT .
OB: = LOAO·B + ILOAO'OS :+:
ILOAO'P*T*UO*OA +
ILOAO*P*T/UO*/OA
OC : = LOAO*C + ILOAO*OC :+:
ILOAO*P*T*UO*OA*OB +
ILOAO*P*T*/UO*/OA* lOB
00 : = LOAO*O + /LOAO*OO :+:
ILOAO*P*T*UO"OA*OS*OC +
ILOAO*P*T*/UO*/OA*/OB*/OC
/CARRY = T*UO*OA*OS*OC*OO + T*/UO*
IOA*/OB*/OC*/OO
6-29
High .p...., .... Cost.fuH1.inkArray.s
,
-' . .
"'f--
THE PROGRAMMABLE LSf'SOlUTlON
A family of 15 PAL devic~s .il:remanufacturedby
Monolithic Memories •. Inc. whi·ch provide a tarige
logic functions including combinatorial. thr.e'-State.
sequential. and arithmetic sequential. Tile TTL
devices utilize a platinum Siliciqe Schottky process'
andTitanium Tungsten fuse links to forma single
programmable emitter follower AND array which
drives a fixed OR array as shown in Figure 4.
.of
"
BasiC Combinatorial Cell.
Thebasic combinatorial cell implements the sumo!
prellduct$ over a range of input-output pin ratios. All
combinatorial output drivers conform tell the Low
Power SchOttky TTL eleclrical characteristics for
totem pole drivers. e.g., IOl = SmA.
I11I111111111111
..
~
Figure 6: Combinatorla' C.II
Programmable 1/0
A more complex combinatorial celi incorporaies
three-state drivers where the. enable function is
programmable. This allows a pin to be allocated as an
input, an output. or dynamically I/O. All three-state
outputs are designed to meet the Low Power Schottky
TTL three-state bus standard of 24mA IOl.
Figure 4: A.ND-OR Circuli Oiagram
The AND-OR array is described logically by a
distributed AND gate symbol to facilitate ease 6f
drawing. I Conventional AND symsol with single
input rail where X indicates a diode and a fuse.'
-=1111111111111111~
Figure 7: Programmable 110 Cell
Registered Feedback Cell
A D-type Register at the output of a combinatorial
cell forms the state machine primative. This cell can be
uSed to implement regular state sequences such as
count and shift, but more importantly, it can be used to
implement random state· sequences not ·available as
standard functions.
111111111!11
Figure 5: AND-O"R Logic DiagraM
6-30
t St
High Speed/Low Cost Fuse Link Arrays
Arithmetic Cell
The most complex of the PAL cells Includes an
exclusive OR and a gated fee:Jback to implement basic
arithmetic operations such as greater than, less than,
add and subtract.
The register forms an accumulator while the
combinatorial network forms an ALu.
111111111111W$i
Figure 9: Arithmetic Cell
Structured Pinouts
The 15 PALs are packaged In the popular 20 pin 300
mil wide Skinny DIP'· Input pins are generally. to the
left while output pins and 1/0 pins are to the right. This
feature conveniences PC board layout and allows the
PinouL'Logic Symbol to be. a Block diagram
~A;Ls~\,Programma,ble Logic Functions
Help, Minimize Hardware
Jpbn,; Birkner/Wescon
7,9
Taking lId~J~tage of PROM on-the-spotptogrammability, the
PALs ofjera range oUogic replacement ,capabilities - from
random gates to complex arithmetic circuits. Using a programmable AND array to feed a fixed OR array, PALs permit
compact realizations of sum-of-products expressions, This
paper will provide an overview of the PAL family, a basic
understanding of the PAL structure, some'guidelines as to how
systems can be partitioned to take advantage of the PAls and a
design example.
The Problem
A look at the three 1 billion dollar digital integrated circuit
marketplace provides inSight into the needs of systems designers.
First, Figure 1 breaks out the dollar marketplace into four
major areas.
Figure 2. Unit Digital IC Marketplace
. Comparison of Figure 1 and Figure 2 along with some quick
arithmetic shows the ASP (Average Selling Price) of the MPU,
RAM, ROM/PROM/EPROM is around $4,00, whereas, the ASP
of TTUCMOS is around $.50. As a ball-park cost of placing an
IC on a board is around $1.00 (board cost, assembly and test).
the major cost of using the TTUCMOS is the overhead, not the
silicon,
Programmable Logic
figure 1. $ Digital IC Marketplace
As the average system should contain a similar percentage cost
of silicon for MPU, RAM, ROM/PROM/EPROM, TTUCMOS, it
is of particular interest to hote the high percentage of Random
Logic; e.g., TTUCMOS. In spite of the great microprocessor
revolution, the systems marketplace spends 35% of its dollars
on random logic. To make this point shockingly clear, Figure 2
shows the three billion unit marketplace for MPU, RAM,
ROM/PROM/EPROM, TTUCMOS.
The systems marketplace devotes 87% of its IC chip count to
TTUCMOS, Dramatic evidence of this fact is demOnstrated by
observing the high percentage of. 16 and 20 pin DIPs on today's
small board computers and microprocessor systems.
Semiconductor manufacturers have been busy designing a host
of programmable logic devices to meet the challenge of
integrating this last holdout to LSI, namely random logic
gates/muxes/decoders/flip-flops. For the system. designer,
programmable logic holds the promise of balancing the level of
integration of his digital IGs while still further reducing the
printed circuit board real estate required per system. Further,
programmable logic gives the US,fiIr a custom IC which he can
buy as an inexpensive high volume/multiple sourced virgin
device, then customize on commonly available programmers.
The first and most commor programmable logic device suitable
for logic replacement is the bipolar PROM. Available in a wide
variety of inpuVoutput pin ratios, the PROM transforms an input
variable (address lines) to a desired output conditiOn (data out)
with a propagation delay in the range of 50 to 80 nanoseconds.
Normally thought of as a memory, the PROM is a sum of
products, boolean transfer function which will transform all
poSSible input vectors to any desired output vector, Caution!
PROM outputs glitch during the propagation delay of any input
change. This is true as any input change causes the source of
data to move from one product to another where there may be a
gap, overlap, ora third product causing unpredictable outputs.
Figure 3 shows a PROM architecture in slim of products form.
PALs: Programmable Logic Functions Help Minimize Hardware
PROM
16 Words X4 Bits
1
3
~
V
7 '
'\
"OR" ARRAY
(PROGRAMMABLE)
0
7
~
IV iV
FPLA
4 In • 4 Out • 16 Products
~
~
10
V
~
'\
'\
V
I,
V
""""'
""""'
=<
=<
=<
=<
=<
=<
F=<
F=<
F=<
F=<
F=<
?<
F=<
F=<
F=<
F=<
F=<
F=<
l......I
...J
~
~
~
~
~
c-_
"AND" ARRAY
"OR" ARRAY
(PROGRAMMABLE)
~
=<
=<
=<
=<
~
yyyy-
(FIXED)
"AND" ARRAY
(PROGRAMMABLE)
F"lgure 4. FPLA Architecture
Figure 3. PROM Architecture
The first programmable logic device designed specifically for
logic replacement was the-FPLA. The programmable AND array
overcomes the previous glitch problem in the PROM and allows
more input variables. Figure 4 shows an FPLA architecture with
programmable AND and programmable OR arrays.
complement of the PROM architecture as the AND array is
programl\1ablE! and the OR array ill_ fixed: The architectuni
affords simple programming in existing .PROM programmers
plus a fast propagation time of 40 nanoseconds maximum over
the commercial Vee and temperature ranges. In addition~ PAlS
have additional output options of Registers and 1/0 as sum-mari:l;ed in Figure 6. Figure 5 shows tHee PAL architecture with
programmablE! ArilD~amlY and fixed OR array.
~,
c
A recent entry into the progral\1mable_logic marketplace is the
PAL 2 (Programmable Array Logic). The PAL architecture is a,
yyyy
:PALs: Progl'ammableLogicFunctions Help Minimize Hardware
PALs -
PAL
4 In • 4 Out • 16 Products
"OR" ARRAY
(FIXED)
10
...
'7'
~
7 'Ii
7 ...
V ~ IV
~
K
K
K
b<
Fifteen PALs provide a family approach to the replacement of
random logic gates, muxs, decoders and flip-flops at a greater
than 4 to 1 chip count reduction. The die sizes range from 13K
squar~mils to 19K square mils which compare to 2K PROM and
4K PROM die sizes which sell in the $2.00 to $4.00 range. Two
major semiconductor manufacturers are now supplying PALs
with a third to appear shortly.
A description of the family is shown in Table 1 below.
PART
NUMBER
=<
~
DESCRIPTION
Octal
Hex
Quad
Dual
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16Cl
PAL10L8
PAL12L6
PAL14L4
PAL16L2
PAL16L8
PAL16R8
PAL16R6
PAL16R4
PAL16X4
PAL16A4
r=<
F<
-,
A Family of 15
=<
f::<
=<
F=<
F<
Octal
Hex
Quad
Dual
Octal
Octal
Hex
Quad
Quad
Quad
10 Input And-Or Gate Array
12 Input And-Or Gate Array
141nput And-Or Gate Array
161nput And-Or Gate Array
16 Input And-Or/ And-Or-Invert Gate Array
10 Input And-Or-Invert Gate Array
121nput And-Or-lrivert Gate Array
141nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or-Xor Gate Array
161riput Registered And-Carry-Or-Xor Gate
Table 1. PAL Family
yyyy
"AND" A RR AY
(PROGRAMMABLE)
Figure 5. PAL Architechlre
Ranging in complexity from simple gates to complex arithmetic
functions the PAL Family can functionally replace up to 90% of
the 7400 Series TTL.
.
A Simple Example
To demonstrate a PAL implementation, consider the following
Boolean functions:
B = A
A--J:>---B
D
/e
G
E *,
~
F
:=D-
G
J
H
+
I
~=D-.J
H~
I
..
J
~=D-M
~==D-M
~=D-P
~==Do-P
C---[>o--D
E
PROM
FPLA
FPGA
PMUX
PAL
AND
OR
Fixed
Prog
Pro~
Fix/ rog
Prog
Prog
Prog
None
Fixed
Fixed
OUTPUT OPTIONS·
TS;OC
IS, OC, Fusible PQIi'!.rity
TS, ~C, Fusible Polarity
IS
..,.
IS, Registered, Feedback, 1/9
Figure 6. Programmable Logic Summary
M = /K + /L
P
/N
* /0
.
.
..
. .G.
·=D---c
PALs: Programmable Logic Functions Help Minimize Hardware
Choosing the PAL10H~, these functions are now, implemented
as shown in the logic sympol of Figure 7.
PAL1GH8
The functions are described by the logic diagram of Figure 8.
The buffer which connects Pin 1 (A) to Pin 19 (8) is formed by
the ,single ·X" placed at the intersection of product term 0 (top
horizontal Line) and input line ~,(far left vertical line). The "X" is a
shorthand expression for an intact fuse connecting the product
lin,e (AND gate) to the input line thru an NPN transistor. The
absence of an "X" indicates a blown fuse . .The AND gate is
formed by two "Xs" on the same line which signifies ANDing as
all "Xed" inputs on the ,single rail AND symbol are' ANDed
together. The OR fLingtion is formed by two "Xs" on different
product lines.
This example has shown the implementation of common gate
structures. The versatility of the PAL is demonstrated by some
not so common gate structures shown below. Figure 9 shows a
PAL implementation of those gates.
c
A
* IB
F
o
+
Logic Symbol
Figure 7. Example Gates Logic Symbol
Example Gates
No~1
Logic Diagram
PAL10H8
r ' 'r
A '-'-'~==lm
IE
I = G*/H
L
J*K
+ IG*H ~=:)~
I
+/J*/K
"B
c'
"
"D
"G
PAL1GH8
" J
,
)------!' M
" NOT
USED
" NOT
USED
N~·~~=#~~t=~#=~~~I~====~~"o
Figure 8. Example Gates LogiC Diagram
Logic Symbol
Figure 9. Example Gates Logic Symbol
PALs: Programmable Logic Functions Help Minimize Hardware
Partitioning System Logic for PALs
The sum of products Boolean transfer function is the common
denominator and basic primitive of all digital logic systems.
From the sum of products, not only can all the gate functions be
derived, but so also can latches, edge triggered registers, MUXs,
encoders and decoders. The first nine PALs (PAL 10HB thru
PAl16L2) implement a. variety of input/output pin ratios and
product terms per output. Input pin loading is less than 0.25 mA
while output drive is 8' mA sink and 3.2 mA source. A typical
gate configuration is shown in Figure 10.
Latch Circuits can be implemented as shown in Figure 12. The
PAL 16LB is commonly used for this function as six of the eight
outputs are internally connected to an array input line. Edge
triggered flip flops can be constructed from two latches where
individual clocki['lg is required.
Figure 12. Latch Circuit
Figure 10. Typical Sum of Products
Three-state buses are commonly used in TTL systems to reduce
interconnect densities by sharing signal lines. The PAL 16L8
thru PAL16A4 output driversllre all three-state outputs which
sink 24 mA, compatible with the low power Schottky three state
standard. This 24 mA sink is sufficient to drive many standard
buses including the Intel Multibus.
Control logic containing D-type or J-K flip-flops is common
among memory, processor and controller interfaces. This logic
can generally be classified as state-sequence logic or smallstate machines. The PAL types PAL 16RB, PAL 16R6 and
PAL 16R4 contain output registers with feedback which can
implement simple state-sequences. Figure 13 shows a typical
control logic configuration.
The PAL three-state outputs are of two types. First, the register
outputs are controlled by a common enable pin for parallel bus
enabling. Second, the combinatorial outputs are individually
controlled by a product term. This feature allows an open
collector configuration to be logically derived as required in
bus-shared control Signals such· as memory transfer acknowledge. The latter type is shown in Figure 11.
Figure 13. Registered Sum of Products
Figure 11. Three-State Driver with Individual Enable
PALs: Programmable Logic Functions Help Minimize Hardware
Design Example
DATA
OUT
ENABLE
A typical control logic problem is the memory to processor
handshake on memory transfer used in many computer
architectures. The processor makes a transfer request by
activating a request line (REO) and specifies a read or write
operation on a, Read/Write line (R/W).
DATA
AVAILABLE
During a read operation the processor waits for a Data Available
signal at which time the data bus is sampled and the request line
lowered, completing the cycle. During a write operation, the
processor places data on the bus and waits for a write complete
signal after the write cycle is finished; Upon write complete, the
request line is lowered, completing the cycle. This handshaking
operation is described in the timing diagram of Figure 14.
The memory-board logic to implement this function may be
designed with gates and edge triggered flip flops as shown in
Figure 15. This particular 'design would require about five
SSI/MSI packages. The same design is implemented in Figure
16 by a single PAL16RB.
WRITE
COMPLETE
REO
Rffl ----+----+---+--~
Figure '15. Memory Handshake Logic
Logic Diagram PAL 16R8
CK~'~
,v------~"-."..-""-"'-...-,,... ,-,,.....-....-.. -....-"..--~----'
DA
WE
WC
Figure 14. Memory Handshake Timing
Bibliography
1. Semiconductor Industry Association, 1979, first four months
report.
2. John Birkner, High, Speed/Low Cost Fuse Link, Arrays
Compete with TTL 74S/LS, WESCON 'lB.
Figure 16. PAL Memory Handshake Logic
Oate 'Arrays Logjam Test 'Engineering
John BirknerlWescon 80
Gate arrays give logic designers the ability to create
numerous semi-custom ICs in a relatively short amount of
time. The number of \Jnique patterns may vary from 10 to 200
for a typical new, systems design. When the new system is
transferred to production, the Test Engineering department
is faced with one to two work weeks per pattern. Systems
manufacturers, using gate !irrays for the first time, are cautioned to plan for the increased demands on Test Engineering, or they will find a logjam infesting. This paper examines
the problems and solutions, in testing gate arrays and
semicustom logic.
Definitions
Many terms have recently appeared to describe the host of
integrated circuits which are configured late in the manufacturing process. These ICs are most generally described as
uncommitted logic. More specifically, there are classifications such as semicustom logic, gate arrays, programmable
logic arrays, field programmable logic arrays, programmable
array logic and hard array logiC;
All of these devlcliS provide the systems designer with
common advantages; higher board density, lower power,
higher speed, etc. For the purposes of this discussion, they
will all be classified as gate 'arrays; The specific example
chosen for this discussion will be hard array logic, HAL, and
Its programmable counteipart, PAL.
Replacing PCBs With Silicon
The problem of testing digital logic is steadily moving
from the printed circuit board (PCB) to the LSI chip. In the
case of gate arrays, the etched lines which connected the
random assortment ofSSl/MSI gates and flip flops is'being
lifted from the, PCB and placed on silicon. Test engineers,
who complain that the new gate arrays create a testing prob·
lem, forget that they once testedtf;lat same logiC on thePCB."
Gate arrays don't create new,testing problems; they just
move the old testing problem from the PCB onto the silicon
chip. This ITW-Y be viewed as an opportunity t9structure the
testing problem in the more regular environment of a fixed
package, structured array. We must be more clever, however,
in generating our test programs without the aid of Internal
test pOints which were available on the PCB.
The/Logjam
Testing LSI logic is certainly not a new problem. Standard
LSI chips, like the miCroprocessor and the variety of special
purpose controllers,are regularly tested.,The new problem
lies in large numbers of gate array patterns which can be
quickly designed and fabricated.
"
For a single systems design, a few design engineers can
create as many as 200 new and unique gate array patterns.
At one week per pattern, this translates to four work years of
test engineering time,
Test Vectors'
Test programs for LSI devices consist of electrical, switching and functional tests. The electrical, and switching
characteristics are tested by the semiconductor manufacturer, and may be opti,~>nally tested by the user. The function
test is supplieq to the manufacturer by the user. It consists
of a list of test vectors, which specify for each pin, instructions for driving high or low, or testing high or low, or not driving and not testing. ,
The time consuming job for:the user is the generation of
test vectors. At' this time, work is under, way toward
automating the generation' of test vectors, thus fa:r with
some success. Even with automated programs, man4al intervention and human interaction make the task time consuming. In addition, the automated programs are not self
starting. They need manually generated seed vectors.
Responsibility of the Designer
When a new system is transferred to production, the
systems designer hands over the responsibility for the
system to ,the test engineering department who now determines how and what tests should be performed to ensure
proper operation of the system. At this pont the systems,
designer transmits the necessary Information for understanding the system operation. Unfortunately, much information is lost at this pOint. All too often continuity is broken
and while the systems designer is off designing the next
great project, the test engineer is left to struggle with understanding how the system works. This struggle is exaggerated when system complexity is increased by the use of
gate arrays.
It is the design engineer who best knows the operation of
his, gate array design, and it is the design engineer who can
quickly specify a few seed vectors to give the test engineer a
starting point or to give the automatic vector generator a
starting point. The problem at hand is to entice designers into this task.
'
Tools for the Designer
The first step toward luring the designer into providing
test vector information is to give him a standard format for
specifying the vectors. The format should be easy to understand and convenient to write down either on paper or,
preferably, into a computer terminal. Fortunately, there is a
format that already exists, which with slight modification,
will suit our purpose. The format is the well known "Function
Table" format found in the Texas Instruments TTL Databook
and accepted by JEDEC. Let us now redefine that forlnat as
follows:
Function Table
The function table begins with the keyword, "FUNCTION
TABLE." It is followed by a pin list Which symbolically
Gate Arrays Logjam Test Engineering
defines each pin. The pin list is followed by a dashed line,
e.g.·······(length optional), which in turn is followed by a list of
vectors, one vector per line. A vector is a sequence of states
in order of the pin list followed by an optional comment. The
vector list is followed by another dashed line.
This is the approach takento specify designs for Hard Ar·
ray Logic, HAL, the mask version of Programmable Array
Logic, PAL. The design specification is a computer file which
contains part number, name of device, symbolic pin list,
design equations and a Function Table.
Definition of States
Outsmarting the Designer
H
HIGH LEVEL
L
LOW LEVEL
C
TRANSITION FROM LOW TO HIGH
Providing just the format for specifying test vector infor·
mation is not likely to seduce the busy systems designer into
such a boring task. We have to be a bit more clever to snare
him. Fortunately, we can charm him with a decoy, gate array
simulation.
x
IRRELEVANT
Gate Array Simulation
Z
OFF (HIGH IMPEDANCE)
With this definition, let us now write a function Table for a
simple two input AND Gate having inputs A and B with out·
put C.
FUNCTION TABLE
ABC
-------------L
H
L
L
L
L
L
T" H
H H H
The systems designer is impressed with computer·aided
tools that help him in his design task. What if he had a com·
puter program which would simulate his gate array design
and tell him if it works as he wants it to? Would he use it?
This author is betting that he will.
A simulator has been added to the PAL Assembler,
PALASM, which reads the Function Table and simulates the
device as specified in the state equations which specify the
transfer function. Inconsistencies between the Function
Table and the transfer function are reported as errors. The
simulator checks the operation of the gate array against the
equations, thus verifying the designer's intention for the
device. What the designer perhaps will never realize is that
he has also provided seed vectors for test engineering.
Future Considerations
The second step in persuading the designer into pro·
viding test vectors is to combine the Function Table with the
gate array design specification so as to provide one docu·
ment with design and functional information.
The. real objective here is to give the designer a format to
mimic the data sheet format which he is accustomed to see·
ing for standard TIL components.
The test vector generation problem is generally con·
sidered to be one of starting with the transfer function and
synthesizing the state table. The engineering problem is just
the reverse. That is, the designer starts off with the state
table and he synthesizes the transfer fucntion. A challenge
for gate array manufacturers is to provide their customers
with computer·aided tools to automatically generate gate ar·
rays from state tables.
m
_
High Level Language for Programmable
Array Logic
John BirknerlWescon 81
Introduction
Standards for silicon definition languages are under consideration by semiconductor manufacturers in order to provide a
means of communication between vendor and customer for
specifying semicustom ICs. The objective of an industry
standard language is to provide a hardware-independent,
manufacturer-independent, user-independent, unambiguous
definition of an IC. So far, the debates in subcommittees,
ranging from what symbol to use for an AND gate to whether
there should be a standard at all, would indicate that many
standards will evolve.
If the vendor implements the TTL function exactly as shown, the
user will pay the price of extra die size. If the vendor optimizes
the deSign, he must understand it, at a high cost of engineering
development time. In either case, the vendor is subject to the
risk that the IC version will not operate identically to the TTL
version. Figure 1 demonstrates the risk of copying TTL logic
directly. The 74LS161 four-bit counter is asynchronously set to
zero when the count reaches 12. Will this circuit hazard operate
the same when it is forged into one piece of silicon? Or, will it
oscillate?
Digital machines are most efficiently defined by explicit Boolean
state equations. These equations are unambiguous, they are
easily simulated, and they can be readily expanded to systems
of machines. This paper discusses such an equation-implemented language as applied to Programmable Array Logic.
74LSOO
74LS161
Logic Schematics Fall Short
Figure 1. Common Circuit Hazard
The predominant hardware description language of today is the
logic schematic. The predominant hardware verification technique of today is the hardware prototype. These tools are
inadequate for the development of silicon hardware.
The logic schematic may be a fine tool for human understanding of a digital system, but is is quite awkward to input it
into a computer for generation of photOlithographic plates used
in making semicustom or custom ICs. Likewise, the hardware
prototype is an awkward means of design verification of an IC.
Differences in propagation delay, circuit implementation, and
logic implementation degrade the effectiveness of the hardware
emulation. Also, the manual interaction increases the probability of error, especially in high complexity logic systems. The
cost of an error in making an IC is tens and thousands of dollars
and months of delay. The cost of multiple errors is years of
delay, which often kills the project.
TTL 7400-series logic schematics are commonly submitted to
semiconductor vendors for implementation in semicustom or
custom ICs. The semiconductor manufacturer then makes a
choice as to whether to implement the function exactly as
shown on the schematic, or to optimize the design to the
particular circuit technique.
Testability is another common trap lor the semiconductor
vendor. The user's TTL prototype may work fine in his system
and also be virtually untestable. A frequent example is the clock
phase generator which has no initialize control pin. Without a
known initial state, the tester must sequence the device until a
recognizable pattern is observed. Most IC testers do not have
this capability.
Discipline for Semicustom Users
Successful use of semicustom logic is best achieved when the
user understands the vendors manufacturing cycle and when
the user partiCipates in that cycle. The production of a
semicustom IC is basically the same as that required for a
standard IC, with the exception that the user takes part in some
of the steps. The major steps are outlined below.
1. Define
2. Simulate
3. Build
4. Test
High Level Language for Programmable Array Logic
USER
SILICON FOUNDRY
+
I
I
INPUT
EQUATIONS
AND
FUNCTION
TABLE
ASSEMBLE
~
I
EDIT
EQUATIONS
I
+
EQUATIONS
SIMULATE
~
+
PAL
I
TEST
FUNCTION
~OMIC
HAL
FABRICATE
AI
LINKS
..
TEST
ELECTRICAL
PARAMETERS
GENERATE
COMPRE:HENSIVE
VECTORS
I
I
+PAL
/
I.
L....,.
I
I
j
,-
I
..
~L
FABRICATE
Ti-W
FUSES
I
FUNCTION TABLE
I
GENERATE
CUSTOM
MASK
Hi
I
I
EDIT
FUNCTION
TABLE
YES
BLOW AND
VERIFY
FUSES
FABRICATE
WAFERS
TO
6TH MASK
I
I
YES
I
~
I
t
I
SAND
TEST
ELECTRICAL
PARAMETERS
.
TEST
FUNCTION
COMPREHENSIVE
I
I
Figure 2. PAL/HAL Development Cycle
These four steps are demonstrated.Jn the diagram above for the
development of PAL, Programrlllible Array Logic, and HAL;
Hard Array Logic. The user begins by defining his logic
functions using Boolean logic equations. THese equations are
automatically assembled into hardwani routing instruciions by
'the PAL assembler, PALASM. Syntax errors are reported. The
user edits and reassembles., repeating the proceSs Until no
syntax errors are ieported.
;.
The user then inputs a Function Tapleto verify his design.
PALASM simulates the PAL/HAL, using the equations, and
executes the Function Taple on the simulated device. Simulation errors are reported. The user corrects the Function Table
and/Or equations until no simulation errors occur. This com"
pletes the design verification process.
The automatic routing instructions from PALASM may now be
used to generate a custom mask for fabrication of a HAL.
Aluminum links implement the logic .equations, providing a
semicustom device. Comprehensive Test vectors are generated
using the Function Table as seed vectors.' One hundred percent
coverage for .s,tuck-high/low test conditions is usually achieved
with fewer th~1n 200 vectors.
HALs are cost-effective in volumes of 1000 or above, For lower
volumes, th~ prOgrammable version, PAL, may be programmed
low-cost programmers. The HAL is unique in
by the user
that it is a semicuslom device that has a programmable
prototype, the PAL.
on
EquatiorisSimplify
"Our life is frittered away by detail: .. Simplify, simplify."
Thoreau
Hardware Description Languages most often use network
topology to specify the interconnectioN of gates and flipflops.
Propagation delays are individiJaily specified; wire lists are
generated: long lists of generally unreadable network interconnection are printed out.
High Level Language for Programmable Array Logie
Explicit Boolean equations are a much simpler method of
writing logic functions. They are easily interpreted and can be
readily commented. An example of an AND gate feeding an OR
gate with a comment is shown below.
EXAMPLE SESSION 11
+INPOT
The AND gate is symbolIzed by"'" and the OR gate is
symbolized by "+".
PAL10LS
PAL DESIGN SPECIFICATION
PN12345
J. BI~
6/9/81
EXAMPLE
MMlSUNNYVALE,CA
ABC X X X X X X GND X X X X X X X x/F vce
F .. A*B + E : THIS IS A COMMENT
FUNCTION TABLE
ABC F
Function T.ble Simulates
I, L I,
H H L
L L B
F
= A'B
+ C ; This is a comment
Equations are easily simulated and can be exercised by HIGHs
and LOWs specified in a Function Table. A simulation of the
above equations is implemented in the Function Table below.
FCNC'l'ION TABLE
AB C' F
,~~---------------------
L I, I, TEST OUTPUT LOW
BB I, B TEST OOTPUT HIGH
I, L H H TEST OUTPUT HIGH
I,
The simulation is now used to generate test vectors and may
also be used as seed vectors for automatic generation of
comprehensive test vectors until a 100% coverage of stuckhigh/low conditions is achieved.
L
L
B
TEST OUTPUT LOW
TEST OUTPUT HIGH
TEST OUTPUT HIGH
---~---------------~-----+ASSEMBLE
ASSEMBLY ERROR .. E
FAIL
+EDI'l'
PAL10L8
i PN12345
t
PAL DESIGN SPECIFlCA'l'ION
6/9/81
J. BIRXNER
EXAMPLE
t MMI SUNNYVALE, CA
• ABC X X X X X X GND X X X X X X X X IF
t F" A*B + E :THIS IS A COMMENT
JCEP .. A*B + C
F .. A*B + C :THIS IS A COMMENT
t
vee
to
+SIMOLA'l'E
01 000XXXXXXXXXXXXXXXH1
VECTOR ERROR 02 F
FAI~
Design Verification
The design verification performed by a user in the PAUHAL
development cycle of Figure 2 is now demonstrated in a real
example. What follows is a computer printout from the terminal
of a PAL Development System during a development session.
Two errors are intentionally made during the sessi.on. First, a
syntax error, then a simulation errQr is made to demonstrate th!3
corrective feedback in the development cycle.
+EDIT
PAL10L8
PAL DESIGN SPECIFICATION
J. BI~
6/9/81
• P.Nl2345
t EXAMPLE
t MMI SUNNYVALE, CA
I ABCXXXXXXGNDXXXXXXXXIFvcC
t F" A*B +·C :THIS IS A C~~
t FUNCTION TABLE
I ABC F
t
•
---------------------
00'l'J?0'l'
L L L
L
TEST
LOW
H H L
B
TEST OUTPUT HIGH
t H H L I, TEsT OUTPUT HIGH
leLHHL H
I
to
+SIKJIA'l'E
01 000XXXXXXXXXXXXXXXH1
02 1l0XXXXXXXXXXXXXXXL1
03 00lXXXXXXXXXXXXXXXL1
PASS
+
High Level Language for Programmable Array Logic
A more complex example is an 8-bit synchronous counter as
shown in Figure 3. Example Session #2 reads, assembles and
simulates the PAL Design Specification.
EXAMPLE SESSION 12
+Rl!'AD
PAL20XS
PAL DESIGN SPECIFICATION
CTR8A
BIRKNER/KAZMI/BLASCO
·2/10/81
S-BIT SYNCBRONOOS COtTN'l'ER
MMI SUNNYVALE, CALIFOlINIA
CLK 10 DO 01 02 03 04 05 06 07 Il GND
/EN /CO Q7 Q6 Q5 Q4 Q3 Q~ Ql QO /CI vee
/00:- /Il'*/IO
+
10 '* /00
:+: ' Il'*/IO '* /DO
+
Il* 10 * CI
/01
:'CLEAR LSB
:COONT/HOLD
:t.oAD DO eLSB)
:COONT
/Il'*/IO
10 * /01
:+: Il'*/IO * /Dl
+
11* IO '* CI~OO
I.
+
/02:-
/Il*/10
,
10 * /02
:+: 11'*/10 * /D2
+
11* 10 * CI'*QO*Ql
+
/Q3
I-
+
;+:
+
/Q4 :-
+
:+:
+
/Il*/IO
I'O * /Q3
11*/10 * /D3
11* 10 * cr*00'*01'*Q2
/Il*/IO
10 • /Q4
Il·/IO * /04
Il* 10 '* CI*OO*Ql*02*Q3
/Q5:-
/Il'*/IO
IO * /Q5
:+1 Il*/IO * /05
+
Il*'ZO * CI'*QO'*Ql*02'*'Q3'*Q4
+
/Q6
I'"
+
1+:
+
/Il*/10
IO * /Q6
11*/ZO * /06
Il* IO * CI*OO*01*Q2*Q3*Q4*05,
/Q7:-
/Il*/ic
10 '* /07
:+: Il*/ID '* /07
+
11'* 10 * CI*QO*Ql*Q2*03*Q4'*Q5*Q6
+
Figure 3, 8-Blt Synchronou5 Counter
If (VCI;:)
CO "CI*QO'*Ql*Q2*Q3*Q4*Q5*Q6*Q7
,6.43
High Level Language forProgrammabl. Array Logic
+ASSEMBLE
FUNCTION TABLE
11 10 D7 D6 DS D4 D3 D2 D1 DO /CI CLK /EN
Q7Q6 Q5 Q4.Q3 Q2 Q1 QO /00
I SEX.
I n 10
INPOTS
CONTROL
ot1'1'PUTS
7------0 /CI.CLK /EN 7------0 /00
-----.-------------~~----------------------
10 10
H 10
a a
HL
a a
H, 10
a H
a 10
Ha
LLLLLLLL H
LLLLLLLB a
LLLLLLHL a
c
LLLLLLHR a
C
LLLLLELL a
IJJJ,IoHBB a
C
xxxxxxxX
C
~LL H
LttLmmB
C
LLLLmmB . H
I,IJ,mJJI, a
C
XXXlQCXXX
IIIsmmH H
BL LLIoBHBHH
C
II H XlqCClqCXX
C
LLSLLLLL H
C
H L LLHRmmB
LLHRmmB a
IoBIoI,I,I,LL a
a a
C
a L
C
LmmmmB a
a a
xxxxxxxX
C
HLLLLLLL a
dHBriBHriH
H L jiHBfU!HBa
C
L
xxxxxxxx
a a
C
LLLLLLLL H
a L "..nnnBBH
tu1I1"ntln n
C
10
C
1iBl1ita:mu.
~ 10
Iii1IUiBBHL a
a 10 IIBBBBmJi
C
HHmmBLa a
B L aBmmLBB
C to BBBHHLBB a
a 10 BHimI.ImB
C L BBHHLBBH H
a 10 BRI!LmmB
C L BI!I'l:t.mmB a
aL B!pIIBBB
C to BBLHHBBB B
a L atoHBBBBB
C L RLHBBHBB a
C 10 LfD!lI!IBBB a
H 10 LHBBHBBH
a 10 HHHEfflfiSB
C L mmBmmB L
10 L XXXXXXXX
C L LloI,j:,IoLIJ, . II
a a
xxxxxxxx
C L ELLLLLt.a a
Ba
XXXXXXXX
C L LttI,USI, a
aa xxxxxxxx
C 10 ~wm a
a a XXXXXXXX
C L LLLLLHLL a
H L IU1l1riBBBL
C to RHaHHRil+' B
H a XXXXXXXX
C 10 1I1.tl.ll.tl.tdDIH L
C 10 ~ B
It H .' XXXXXXXX B
La LLLLLLLL 10 C L IiHHBBHBB 10
a a BHBBHBBB L C 10 L~LL a
---------------------------~-~~~-----~----HSBBBHBB
LLLLLLLH
XXXXXXXX.
LLLLLLSH
xxxxxxxx
LLLLLmII'J
f.:~=
10
X
10
x
10
x
L
X
L
x
L
X
10
x
L
L
10
10
x
x
X
x
X
x
x
X
L
X
L
10
10
L
X
10
C
C
C
10
10
10
10
L
10
L
10
L
L
L
10
10
L
10
L
L
10
L
L
PASS
+SIMDIA'l'E
01 C0111111110XORLLLLLLLL01
02 C010QOOOO01XOBIJ.T.I.tJJ.HX1
03 C1XXXXXXXX1XORLLLLLLEL01
04 C0110000001XOHLLLLLLHRX1
os C1XxxXXXXX1XORLLLLLRLL01
06 C0111000001XOHLLLLLHRHX1
07C1XXXXXXXXlXORLLLLHLLL01
08 C0111100001XORLLLLHHBBX1
09 C1XXXXXXXX1XORLLLaLLLL01
10 C0111110001XOHLLLBBEBHX1
11 C1XXXXXXXX1XORLLRLLLLL01
12 C0111111001XOHLLHBBHBBXl
13 C1XXXXXXXX1XOBLBLLLLLL01
14 C0111111101XOBLBHBBHBBX1
15 C1XXXXXXXX1XOHHLLLLLLLOl
16 C0111111111XOLmmBBBBBOl
17 C1xxxXXXXX1XOHLLIoLLLLLOI
18 .eOl11~11111XOI,eHHHHHHHOl
19 COOIIil1111XOBBH~X1
20 C010111111ixoHHHHHHi!l,1IX1
21 COII0111il1XOBHBHBaLHBxl
22 CQ111011111XOBBHHBLBBBX1
23 C0111tOl111XOBBBBLHBBBX1
24 c0111110111xOHHB~1
25 C0111111011XOBBLHBBHBBX1
26 c01il1111PlXoBi.mmmmsxl
27 COllll11111XOt.!!HeHBH Ai101
28 crixxXXXxxXOXOHLLLLLLLLXl
29 ClxXxXXXXXlXOriLLLLLLLBOl
30 CIXXXxxxxxlXOHLLLLLL~Ol
31 CIXXXXXXlOC1XOHLLLI4BHP1'
32 C1XXXXxXXX1xoijLLLL~01
33 COOl,UlllllxpmpduWBSLXl
34 C1xxxx~lxOLijB~Dl
35 C1XXXXxxxXIXOBBH~11
36 CI00QooooogipLBBBBimBBD1
37 CllllllllllXOBLLtLIitt.;.0l
PASS
+
7·1
Programmable Array Logic Family
PA~Series 20
U.S. Patent 4124899
Features/Benefits
• Programmable replacement for conventional TTL
logic.
• Reduces Ie inventories substantially and simplifies
their control.
• Reduces chip count by 4 to 1.
• Expedites and simplifies prototyping and board
layout.
Saves space with 20-pin SKINNY DIP'"' packages.
• High speed: 25ns typical propagation delay.
• Programmed on standard PROM programmers.
• Programmable three-state outputs.
• Special feature reduces possibility of copying by
competitors.
Description
The PAL family utilizes an advanced Schottky TTL process and
the Bipolar PPOM fusible link technology to provide user programmable logic for replacing conventional SSI/MSI gates and
flip-flops at reduced chip count.
The family lets tht~ systems engineer "design his own chip" by
blowing fusible links to configure AND and OR gates to perform
his desired logic function. Complex interconnections which
previously required time-consuming layout are thus "lifted" from
PC board etch and placed on silicon where they can be easily
modified during prototype check-out or production.
The PAL transfer function is the familiar sum of products. Like
the PROM, the PAL has a single array of fusible links. Unlike the
PROM, the PAL is a programmable AND array driving a fixed
OR array (the PROM is a fixed AND array driving a
programmable OR array). In addition the PAL provides these
options:
• Variable input/output pin ratio
• Programmable three-state outputs
• Registers with feedback
• Arithmetic capability
March 1981
PART
NUMBER
PKG
PAL10H8
PAL12H6
PALHH4
PAL16H2
PAL 16Cl
PAL10L8
PAL 12L6
PAL 14L4
PAL 16L2
PAL 16L8
PAL16R8
PAL 16R6
PAL16R4
PAL16X4
PAL16A4
N,J.F
N,J.F
N,J,F
N,J,F
N,J,F
N,J,F
N,J.F
N,J,F
N,J,F
N,J.F
N,J,F
N,J,F
N,J,F
N,J
N,J
DESCRIPTION
Octal
Hex
Quad
Dual
Octal
Hex
Quad
Dual
Octal
Octal
Hex
Quad
Quad
Quad
10 Input And-Or Gate Array
12 Input And-Or Gate Array
141nput And-Or Gate Array
161nput And-Or Gate Array
16 Input And-Or/ And-Or-Invert Gate Array
10 Input And-Or-Invert Gate Array
121nput And-Or-Invert Gate Array
141nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or-Xor Gate Array
161nput Registered And-Carry-Or-Xor Gate
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any single
input assume the logical low state. Registers consist of D type
flip-flops which are loaded on the low to high transition of the
clock. PAL Logic Diagrams are shown with all fuses blown,
enabling the designer use of the diagrams as coding sheets.
The entire PAL family is .programmed on inexpensive conventional PROM programmers with appropriate personality and
socket adapter cards. Once. the PAL is programmed and verified, two additional fuses may be blown to defeat verification.
This feature gives the user a proprietary circuit which is very
difficult to copy.
Ordering Information
~
f-I
1[=="
PROIlRAM..
H~
L ~
C~
x ~
A~
ACTIVE HIGH
ACTIVE LOW
COMPLEMENTARY
EXCLUS.IVE-OR REGISTERED
ARITHMETIC REGISTERED
IEJ
1
11 j 1] ~
!
".
~.ABLE ARRAY LOIlIC FAMILY
:~~:~~ ~:p:RRAY INPUTS
NUMBER OF OUTPUTS
TEMP.ERATURE RANGE
C'" DC TO +75C
I
PA:~::~ T.O +12.5C
I
,
(CASE TEMPERATURE)
N ~ PLASTIC DIP
J ~ CERAMIC DIP
F ~ ~LATPACK
OPTIONAL HI-REL PROCESSING
883B -= MIL-STO-883, METHOD 5004 & 5005 LEVEL B
8.83C MIL-STD-883, METHOD 5004 & 5005 LEVEL C
B ~. MIL-STD-883, METHOD 5004 EaUIVALENT
PAL 14 L4 CJ8838
PAl:jj' is a registered trademark of Monolithic Memories
1165 East Arques Avenue. Sunnyvale. CA 94086 Tel: (408) 739-3535 TWX: 910-339-9229
7-2
MonolIthIc ~T!II
MemorIes InJlW
PAL Series 20
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16C1
PAL10L8
PAL12L6
PAL14L4
PAL16L2·
PAL16L8
PAL16R4
PAL16X4
PAL16A4
PAL16R8
PAL16R6
7-3
PALS.rl.. 20
Absolute Maximum Rating.
Operating
~~~I~~i~::e:~~. :::: :::::: ::::: :::: :::::::: ::: :::::::::::::::::::::::::::::::::: :::::::;::::::: ::::::: :::::::: '5:5~
>.................. .......... ',' ..........
Off-state' output Voltage' :~ .• , ...................... ',' .......•.........•..
~'
5.5V
Storage·temperiitur~'.,,, ...............:......................................................... ;., .. '........., -65. to +1SO·C.
Operating COQditions
"
SYMBOL
"
vec
tw
tsu
MILITARY
MIN TYP MAX
'PARAMETER
' SlJl'Ply
voltage>
16RS
input or.feedb!:lCk
'16X4 16A4
.; 5
5
.25'
10
25
10
25
10
25
10
45
25
55
30
-15
35
45
30
I" High
Set up time fr0tn
,
,.'
1"4.5
low
Width Qfclock
, COMMERCIAL
UNIT
MIN ,TYP MAX
16R6 16R4
th
Hold 'time
0
TA
Operating free;.air temperature
-55
TC
Operating case temperature
.5.5
.
4.75
5.25
ris
25
0
-15
0
5
V
ns
ns
75
·C
·C
125
Electrical Characteristics Over Operating Conditions
SYMBOL
*
VIH *
Vil
PARAMETER
TEST CONDITIONS
MIN TYP
low"Ie:~el input voltage
High~level
O,S
2
input voltage
V
V
VCC = MIN
VCC = MAX
VI = 0.4V
-0.02 -0,25
mA
IIH
t
High-level inpUl current t
Vee = MAX
VI = 2.4V
25
pA
II
Maximum inp'ut current
Vec = MAX
VI = 5.5V
1
mA
III
low-Ie¥el input 6urrent
.'
VOL
II = -lSmA
low-level output voltage
Vee = MIN
VOH
High-level output voltage
Off-state output current
t
10ZH
lOS
Vil
= O.SV
VIH
= 2V
Vee = MAX
10Zl
Outpuishort-<;ircuit current
-O.S
OHS. 12H6, 14H4
Mil·
10l = SmA
Vee = MIN 16H2,16Cl.l0lS
12l6, 14l4. 1612 COM
=
O.SV
Vil
16RS
16lS
Mil 10l - 12mA
VIR = 2V
16R6
16R4
16A4 eOM IOl = 24mA
16X4
...
**
Yll
=O.SY
V,H
= '2N
Yc.e
= 5V
I'
0.3
,
I.ee
Supply current
10H
c'
Vo
=6\w
-100
pA
YO
= 2.4Y
100
pA
-70
-130
mA
55
90
l6lS c,
16RS
16R6
16R4
.,16X4
16A4
"
-30
. 16R4. 16R&; '16RS,' 1618
16M
'
.
"
I/O pon leakage os Ihe \"Iorsl.case of 10ZX or IIX e.g,,'IIL and 10Z/oI'
Aillypical values are at VCC'= SV. TA = 2S·C.
• These are abso'jule v<)llages wil.hrespecl 10 pin 10 on ihe devi,ce arid includes all overshllOls due Ii> system and/or leSler noise,
Do notattempl to test theSe values wilhout suitable' equipment.
* * Only one output shorted at a lime.
7-4
2.S
V
-3.2mA
Vo = OY
,;
,,16X4
V
eOM
2.4
'.'
0.5
V
IOH = -2mA
10lS, 12l6.14l4, 16L2
Yee = MAX
-1,5
Mil
10HS, 12H6. 14H4.16R2.16:el
tt
UNIT
Input clamp voltage
VIC
t
MAX
.'
120
"
180
160
225
'170
240
mA
PAL Series 20
Switching Characteristics
OVer Operating Conditions
SYMBOL
MILITARY
MIN TYP MAX
TEST
CONDITIONS
PARAMETER.
COMMERCIAL
MIN TYP MAX
UNIT
10Ha 12H6 14H4
Input to
tpo
1414
output
Input or feedback to output
tpo
Al = 5600
R2 = 1.lkO
16H2 lOla 12L6
1612
25
45
25
35
16Cl
25
45
25
l6R6 16R4 16la
16X4 16A4
25
45
25
40
35,
30
45
30
40
ns
ns
tClK
tpZy
Clock to output or feedback
15
,25
. 15
25
ns
Pin 11 to output enable
25
15
25
ns
tpxz
Pin 11 to output disable
Rl =2000
15
15.
25
15
25
ns
R2 =3900
25
25
35
30
45
45
30
ns I
25
45
25
40
35
30
45
30
40
.
'.,
.'
tpz X
Input to
output enable
16R6 16R4 16la
16X4 16A4
tpxz
Input to
output disable
l6R6
fMAX
16R4 16La
16X4 16A4
16Ra
Maximum
frequency
'.
16R6' 16R4
16X4, 16M
14
25
16
25,
12
22
14
.22
:; ..
ns
MHz
Test Load
Available ;P~ogl'ammers
5V
OUTPUT
MANUFACTURER
o--+---.--tel TEST .POINT
Oata 1/0 Corporation
PERSONALITY' SOCKET ADAPTER
'CARD SET
.CONFIGURATION
900-1427
"
Sch~matic
Pro-log Corporati,on
PM9068
Stag SYstem~
PM202
of Inputs and Outputs
EQUIV~LENT INPUT
Vci:o-,---~..--~~
,
TYPICAL OUTPUT
-~='=;:':':"::":'_-ovcc
.
4OJ! NOM
INPUTo-..-f---KH-
"
,
Structured Design
5020/24
7151428'-1
7151428'-2
715 1428'-3
AM10Ha
AM12H6
AM)4H4
AM.16H2
AMl6Cl
AM10l8
AM12l6
AM14l4
AM16l2
PAL Series 20
Programming
PAL fuses are programmed using a low~voltage linear-select
procedure which is common to all15 PAL types. The array is
divided into two grOups, products thru 31 and products 32 thru
63, for which pin identifications are shown in Pin Configurations
below. To program a particular fuse, both an input line and a
product line are selected according to the following procedure:
°
Step 5 Program the fuse by pulsing th~output pins, 0, of the
selected product group to V IHH as shown in Programming Waveform.
Step 6 Lower VCC (pin 20) to 6.0 V
Step 7 Pulse the CLOCK pin and verify the output pin, 0, to be
Low for active Low PAL types or High for active High
PAL types.
Step 8 Lower VCC (pin 20) to 4.5 V and repeat step 7.
Step 1 Raise Output Disable, 00, to V IHH
Step 2 Select an input line by specifying '0, ' 1, '2' '3, '4, ' 5 , '6' '7
and L/R as shown in Table 1.
Step 3 Select a product line by specifying AO' A1 and A2 on~of
eight select as shown in Table 2.
Step 4 Raise VCC (pin20)toV,HH
°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
16
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
IS
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L·
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
14
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
13
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
11
12
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Table 1 Input Line Select
7·6
To prevent further verification, two last fuses may be blown by
raising pin 1 and pin 11 to Vp. VCC is not required during this
operation.
L/R
PRODUCT
LINE
NUMBER
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
0, 32
1,33
2, 34
3, 35
4, 36
5, 37
6, 38
7, 39
8, 40
9,41
10, 42
11,43
12,44
13,45
14, 46
15,47
16,48
17,49
18,50
19,51
20, 52
21,53
22, 54
23, 55
24, 56
25, 57
26, 58
27, 59
28, 60
29,61
30, 62
31,63
PIN IDENTIFICATION
17
This procedure is repeated for all fuses to be blown (see
Programming Waveforms).
L = Low-level input voltage, V,L
H = High-level input voltage, V,H
Voltage Legend
INPUT
LINE
NUMBER
Step 9 Should the output not verify, repeat steps 1 thru 8 up to
five (5) times.
10
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH = High-level program voltage, V,HH
Z = High impedance (e.g., 10k!} to 5.0V)
PIN IDENTIFICATION
03
02
01
00
A2
A1
AO
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Table 2 Product Line Select
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
HH
Z
HH
z
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
HH
Z
HH
PAL Series 20
Pin Configurations
PRODUCTS 0 THRU 31
Programming Parameters
SYMBOL
TA = 25°C
PARAMETER
Program-level input voltage
VIHH
PRODUCTS 32 THRU 63
MIN
LIMITS
TYP
11
11.5
Output Program Pulse
Program-level input current
IIHH
00, UR
ICCH
Program Supply Current
Tp
Program Pulse Width
10
to
Delay time
100
tov
Delay Time to Verify
100
Ip
Verify-Protect-input current
Tpp
Verify-Protect Pulse Width
12
V
50
25
mA
400
50
20
20
mA
IlS
ns
11 5
Program Pulse duty cycle
Verify-Protect-input voltage
UNIT
5
All Other Inputs
Vp
MAX
21
25
22
%
400
mA
50
msec
V
Programming Waveforms
00
VIL
VIHH--~~-r-~------------------------------------------------------------------~
I. L/R. A VIH
Vce
VIHH
VOH
a
VOL
VIH
CLOCK
VIL
7·7
6
PA.L
PAL DESIGN SPECIFICATION
PART NUMBER
I
USER'S PART NUMBER
NAME
REV
L
DATE
TITLE
COMPANY, CITY, STATE
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9
PIN 10
PIN 11
PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
GND
VCC
EQUATIONS
Description
LEGEND:
= EQUAL
:= REPLACED BY
+
*
OR
AND
F 110
7·8
:+:
: *:
XOR
XNOR
I
(
)
COMPLEMENT
THREE-STATE
FUNCTION
TABLE
PIN A
PIN B
PIN C
PIN D
PIN E
PIN F
PIN G
PIN H
PIN I
PIN J
PIN K
PIN L
PIN M
PIN N
PIN 0
PIN P
PIN Q
PIN R
;
COMMENT
- -- -- -- -- -- -- -- - -- -- --
; -A
- BCDE'FGH
~
-- - -- -'
COMMENT
JKLMNOPQR
------.-----~----------------------------------------------------------~---
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --, -- -- --- -- -- -- -- -- -'- -,- -'- -- --
~
- -
-"- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --,
-- -- - -- -- -- -- -- -- -- -- -- -- ,--,-- -- ----- -- -,- -- -- -- -- -- -- -- - -- -- -- - -- -- --- -- -- --'-' -- -- -- -- -- -- -- -'-'- -- -- -- -- -- -,
,
-- -- -- -- -- -- -- -- -- -- -- -- - '--"- -- --' --- -- --' -- -- -- - -- -- -- -- -- -- -- -- ----- -- -- --' .- -- - --' -,- -- -- -- -- -- -- - -- --- -- --- --- -- -- -- -- -- -- -- -- -- -- ----
-
-,.-
----------------~------------~------------------------~--~-----~----------~-
LEGEND:
H
L
HIGH
C CLOCK
LOW
X
F 109
z
OFF
IRRELEVANT
7-9
Programmable Array Logic Family
PAC Series 24
U.S. Patent 4124899
Features/Benefits
• Programmable replacement for conventional TTL logic.
• Reduces IC inventories substantially and simplifies their
control.
• Reduces chip count by 5 to 1.
• Expedites and simplifies prototyping and board layout.
• Saves space with 24-pin SKINNYDIP'· packages.
• Programmed on standard PROM programmers.
• Programmable three-state outputs.
• Special feature reduces possibility of copying by competitors.
Description
The PAL Series 24 family complements the PAL Series 20 family
by providing two additional inputs and two additional outputs,
allowing more complex functions in a single package. This new
family is made feasible by the Monolithic Memories new and
revolutionary 24-pin SKINNYDIP'".
In addition to providing more logiC function per chip, 24 pins
allows for many natural functions which were previously unavailable in skinny 300 mil-wide packages. Examples include:
•
•
•
•
•
8-bit parallel-in parallel-out counters
8-bit parallel-in parallel-out shift registers
16-Line-to-1-Line Multiplexors
Dual 8-Line-to-1-Line Multiplexors
Quad 4-Line-to-1-Line Multiplexors
These natural functions provide twice the density of traditional
16-pin packages.
The PAL family utilizes an advanced Schottky TTL process and
the Bipolar PROM fusible link technology to provide user
programmable logic for replacing conventional SSI/MSI gates
and flip-flops at reduced chip count.
The family lets the systems engineer "design his own chip" by
blowing fusible links to configure AND and OR gates to perform
his desired logiC function. Complex interconnections which
previously required time-consuming layout are thus "lifted" from
PC board etch and placed on silicon where they can be easily
modified during prototype check-out or production.
The PAL transfer function is the familiar sum of products. Like the
PROM, the PAL has a single array of fusible links. Unlike the
PROM, the PAL is a programmable AND array driving a fixed OR
array (the PROM is a fixed AND array driving a programmable
OR array). In addition the PAL provides these options:
• Variable inpuVoutput pin ratio
• Programmable three-state outputs
• Registers with feedback
7·10
PKG
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
PAL20L 10
PAL20X10
PAL20X8
PAL20X4
J.N
J.N
J,N
J,N
J,N
J,N
J,N
J,N
J,N
J,N
DESCRIPTION
Deca
Octal
Hex
Quad
Dual
Deca
Deca
Octal
Quad
121nput And-Or-Invert Gate Array
141nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
181nput And-Or-Invert Gate Array
20lnput And-Or-Invert Gate Array
20 Input And-OrlAnd-Or Invert Gate Array
20 Input And-Or-Invert Gate Array
20 Input Registered And-Or-Xor Gate Array
20 Input Registered And-Or-Xor Gate Array
20 Input Registered And-Or-Xor Gate Array
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any Single input
assume the logical low state. Registers consist of D type flip-flops
which are loaded on the low to high transition of the clock. PAL
LogiC Diagrams are shown with all fuses blown, enabling the
designer use of the diagrams as coding sheets.
To design a PAL, the user writes the logiC equations using PAL
DESIGN SPECIFICATION standard format (F108). This specification may be submitted to Monolithic Memories where it is
computer processed and assigned a bit pattern number, eg
P0123. Monolithic Memories accepts the PAL DESIGN SPECIFICATION in one of the three forms:
1. Computer generated listings.
2. Typed or hand-written forms F1 01 and F108.
3. Direct on line data transmission to Monolithic Memories
Timeshare computer system via telephone (local telephone
network to major U.S. cities, London and Paris) or TWX
online Boston TWX No.).
The entire PAL family is programmed on inexpensive conventional PROM programmers with appropriate personality and
socket adapter cards. Once the PAL is programmed and verified,
two additional fuses may be blown to defeat verification. This
feature gives the user a proprietary circuit which is very difficult
to copy.
Ordering Information
PROGRAMMABLE ARRAY LOGIC FAMILY
~-----NUMBER
OF ARRAY INPUTS
,------OUTPUT TYPE
L =ACTIVE LOW
C = COMPLEMENTARY
X = EXCLUSIVE OR REGISTERED
R =REGISTERED
, - - - - - NUMBER OF OUTPUTS
TEMPERATURE
~
"'" "., '""''
l~:t~~!i;'
r
c=
RANGE
OCTO+75C
LEVEL SEE "SCREENING
OPTIONS
PAL20X8CJ 8838
SKINNYDIP is a registered trademark of Monolithic Memories
1165 East Arques Avenue. Sunnyvale, CA 94086
PART
NUMBER
Tel: (408) 739-3535
TWX: 910-339-9229
mmn
•lIIonolll..1I10
emorle. U'1JnJJ
PAL S.rl•• 24
PAL12L10
PAL14L8
PAL20L2
PAL20L10
PAL20X10
PAL16L6
PAL18L4
PAL20C1
PAL20X8
PAL20X4
7·11
PAL Series 24
Absolute Maximum Ratings
Operating
Supply Voltage, vee ", .... , ..... , .. " .... " ........ " .......... , ................... , ... ,"', ....... 7
Programming
.......... 12V
Input Voltage .... ,.,."............................................................................ 5.5V ..... , .... 12V
Off-state output Voltage ............................................................................ 5.5V .......... 12V
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65° to +150" C
*
Operating Conditions
VCC
MILITARY
MIN TYP MAX
PARAMETER
SYMBOL
Supply voltage
4.5
I low
40
5
20
30
5.5
COMMERCIAL
UNIT
MIN TYP MAX
4.75
35
5
20
10
25
10
tw
Width of clock
tsu
Set up time
60
38
50
th
Hold time
0
-15
0
I High
TA
Operating free air temperature
TC
Operating case temperature
Electrical Characteristics
SYMBOL
low-level input voltage
VIH
High-level input voltage
VIC
Input clamp voltage
III
low-level input current
IIH
High-level input current
II
Maximum input current
TEST CONDITIONS
t
t
Vee
Vee
Vee
Vil
Vee
High-level output voltage
t
IOZH
lOS
ICC
t
tt
Output short-circuit current
**
Supply current
= MIN
= MAX
= MAX
= MAX
=
= O.BV
= 2V
MIN
= MIN
= O.BV
= 2V
All typical values are at Vee = 5V. T A = 25"C.
7·12
°c
MIN TYPtt MAX UNIT
II
= -18mA
VI = OAV
VI
VI
V
-0.8
-1.5
V
-0.02
-0.25
mA
25
p.A
1
mA
0.5
V
= 2AV
= 5.5V
12l10, 14lB, 1616
1Bl4, 20l2, 20e1
20l10,20X10
20XB, 20X4
10l
V
= BmA
0.3
Mil 10l = 12mA
COM 10l -124mA
= -2m A
Mil
10H
= -3.2mA
COM
Va
= 0.4V
-100
p.A
Vil
= MAX
= O.BV
VIH
= 2V
Va
= 2.4V
100
p.A
Vee
= 5V
Va
= OV
mA
Vee
= MAX
1/0 pin leakage is the worst case of 10ZX or IIX e.g. IIX and IOZH
* Pins 1 and 13 may be raised to 22V max.
* * Only one out-put shorted at a time.
°c
10H
Vil
VIH
Vee
Off-state output current
75
2
Vee
low-level output voltage
lOll
ns
0.8
VIH
VOH
38
Over Operating Conditions
Vee
Val
ns
125
PARAMETER
Vil
V
-15
0
-55
5.25
2.4
-30
2.B
V
-70
-130
12l10, 14lB, 16l6,
1Bl4, 20l2, 20e1
60
100
20X4, 20XB, 20X10
120
1BO
20L10
90
165
mA
PAL Series 24
Switching Characteristics
Over Operating Conditions
PARAMETER
SYMBOL
TEST CONDITIONS
MILITARY
MIN TYPMAX
COMMERCIAL
MIN TYP MAX
UNIT
25
45
25
40
ns
12L10, 14L8,
Input to
tpo
output
R1 = 5600
16L6, 18L4,
R2= 1.1kO
20L2, 2OC1
tpo
Input or feedback to output
35
60
35
50
ns
tCLK
Clock to output or feedback
20
35
20
30
ns
tpzx
Pin 13 to output enable
20
20
35
ns
tpxz
.Pin 13 to output disable
20
45
45
20
35
ns
tpzx
Input to output enable
35
55
35
45
ns
tpxz
Input to output disable
35
55
35
45
ns
fMAX
Maximum frequency
20L 10, 20X10
20X8, 20X4
R1 = 2000
R2 = 3900
10.5
16
Test Load
5V
OUTPUT o-4---<~:') TEST POINT
50pF
Schematic of Il;1puts and Output.
EOUIVALENT INPUT
Vcc 0---'-....-----'-8~0 NOM
INPUT0-_-t----I<(I--t'-
TYPICAL OUTPUT
-----_-ovcc
400 NOM
12:5
16
MHz
PAL 8.rle.:24
Programming
PAL fuses are programmed using a low-voltage linear-select
procedure which. is common to all PAL types. The array is
divided into twp groups, prOducts '0 thru 39 and products 40
thru 79, for which pin identifications are shown in Pin
Configurations below. To program
particular fuse, both an
input line and a product line are selected according to the
following ,Procedure:
a
Step 5 Program the fuse by pulsing the output pins, 0, of the
selected product group to V IHH as shown in Programming Waveform.
StepB Lower VCC (pin 24) to B.O V.
Step 7 Pulse the CLOCK pin and verify the output pin, 0, to
be Low for active Low PAL types or High for active
High PAL types.
Step a Lower VCC (pin 24) to 4.5 V and repeat step 7.
Step 1 Raise Output Disable, 00, to VIHH'
Step 2 Select an input line by specifying 10, 11, 12' 13, 14, 15, IB'
17 , la, 19 and UR as shown in Table 1.
Step 3 Select a product line by specifying Ao, A1 and A2
one-of-eight select as shown in Table 2.
Step 4 Raise VCC(pin 24) to VIHH'
Voltage Legend
INPUT
LINE
NUMBER
a
1
2
:3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
21
28
29
30
31
32
33
34
35
36
37
38
39
l
H
HH
Z
19
18
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
L HH
H HH
To prevent further verification, two last fuses may be blown by
raising pin 1 and pin 13to Vp. VCC is not required during this
operation.
= low-level input voltage, VIL
= High-level input voltage, VIH
= High-level program voltage, VIHH
= I High impedance (e.g. 10K n to 5.0V)
PIN IDENTIFICATION
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
Step 9 Should the output not verify, repeat steps 1 thru a up
to five (5) times.
This procedure is repeated for all fuses to be blown (see
Programming Waveforms).
17
16
15
14
13
12
I,
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Table 1 Input Line $elect
10 L/R
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Hf.J
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH.
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
PRODUCT
LINE
NUMBER
0,40
1,41
2,42
3,43
4,44
5,45
6,46
7,47
8,48
9,49
10,50
11,51
12,52
13,53
14,54
15,55
16,56
17,57
18, 58
HI,59
20,60
21,61
22,62
23,63
24,64
25,65
26,66
27,67
28,68
29,69
30,70
31,71
32,72
33,73
34,74
35,75
36,76
37, 77
38,78
39,79
PIN IDENTIFICATION
04
03
02
0,
00
A2
A,
Ao
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Hlil
HH
HH
HH
HH
HH
Z
HH
Z
HH
Z
HH
Z
HH 'Z
HH
Z
HH
Z
Z
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
z·
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
'Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Table 2 Product Line Select
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
Z
HH
Z
Z
HH
HH
HH
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
PAL Series 24
Pin Configurations
PRODUCTS 0 THRU 39
Programming Parameters
SYMBOL
TA ; 25°C
PARAMETER
Program-level input voltage
VIHH
Program-level input current
IIHH
PRODUCTS 40 THRU 79
MIN
LIMITS
TYP
11.5
i 11.75
50
00, L/R
50
Program Supply. Current
Tp
Program Pulse Width
10
to
Delay time
100
tov
Delay Time to Verify
100
Ip
Verify-Protect-input current
Tpp
Verify-Protect Pulse Width
rnA
400
50
/'S
ns
/,S
Program Pulse duty cycle
Verify-Protect-input voltage
rnA
5
ICCH
Vp
V
12
Output Program Pulse
All Other Inputs
UNIT
MAX
%
25
20
20
21
22
V
400
rnA
50
msec
PrOgramming Waveforms
00
VIL
VIHH--+-~+-~~----------------------------
I. LiR, A
VIH
Vce
VIHH
VOH
0
VOL
VIH
CLOCK
VIL
________________________________
~
PAL
PAL DESIGN SPECIFICATION
PART NUMBER
.I
I
USER'S PART NUMBER
REV
DATE
NAME
TITLE
COMPANY, CITY, STA TE
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9
PIN 10
PIN 11
PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
PIN 21
PIN 22
PIN 23
PIN 24
GND
VCC
EOUATIONS
DESCRIPTION:
},
LEGEND:
=
:=
EQUAL
REPLACED BY
+
*
OR
AND
F 108
7·16{
:+:
: *:
XOR
XNOR
I
(
COMPLEMENT
) THREE-STATE
.
FUNCTION
TABLE
PIN A
PIN 8
PINC
PIN 0
PIN E
PIN F
PiN G
PIN H
PIN I
PINJ
PIN K
PIN L
PIN M
PIN N
PIN 0
PIN P
PIN Q
PIN R
PiN S
PIN T
PIN U
PIN V
COMMENT
.
,A
COMMENT
8
C
0
F
E
G
H
K
J
L
M
N
--,.----,~----,----
_ . _ _ _ ,...;....o.. _ _ _
.~~.~ ~.--, ~
~
0
P
--
Q
-
STU
V
--- --
-
______
. ___
- - - ~ ---: -
R
,~_.
- - - - -
~
___ _
-
--
---~--.. ~------~--------~--
.
.
.
-------------.-------
--.-,........
----~------~---~...:....;,.;.--
.
.. - - - - -. -.-. - - - - .-. - - - - - -----.
----:--
- -'-'- -
-
--.
--
- - -.- -
--- -
- --
...,...;.,..--.-~......:...--------.--~----------
-------;,'---~---------------
~~----------------------'-
---------------------------~--
..
.
~-.-.-~----~----------.------~-
- --- --'-- -
- -- ------ - --------- .
T
---
--~--~------------~------~--------~-------------------------------------~~-·,·Z OFF
I£GEN8:
H HIGH
CCt::OCK
L
LOW
X
F 107
IRRELEVANT
'l ..17
Hard Array Logic Family
HAL Series 20 Data Sheet
Features/ Benefits
• Gate array equivalent of up to 200 gates.
• Semi-custom solution
• Reduces SSI/MSI chip count greater than 4 to 1.
• Prototype using field-programmable version -
PAL.
• Cost savings up to 40% compared to PAL.
• Security link disabled for design secrecy.
• Test and simulation made simple with PALASM Function
Table.
• Saves space with 2O-pin SKINNYDIp'· packages.
• Power consumption Is directly proportional to logic
complexity.
PART
NUMBER
PKG
HAL10H8
HAL12H6
HAL14H4
HAL16H2
HAL16e1
HAL10LB
HAL12L6
HAL14L4
HAL16L2
HAL16L8
HAL16R8
HAL16R6
HAL16R4
HAL16X4
HAL16A4
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N.F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
DESCRIPTION
Octal
Hex
Quad
Dual
Octal
Hex
Quad
Dual
Octal
Ottal
Hex
Quad
Quad
Quad
10lnput And-Or Gate Array
121nput And-Or Gate Array
141nput And-Or Gate Array
161nput And-Or Gate Array
16 Input And-Qr/ And-Or-Invert Gate Array
10 Input And-Or-Invert Gate Array
121nput And-Or-Invert Gate Array
141nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput And-Or-Invert Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
161nput Registered And-Or Gate Array
16 Input Registered And-Or-Xor Gate Array
161nput Registered And-carry-Or-Xor Gate
Description
The HAL family utilizes standard Low-Power Schottky TTL
process and automated mask pattern generation directly
from logic equations to provide a semi-custom gate array for
replacing conventional SSI/MSI gates and flip-flops at reduced chip count.
The family lets t~,e systems engineer "design his own chip"
by AND and OR gates to perform his desired logic function.
Complex interconnections which previously required timeconsuming layout are thus "lifted" from PC board etch and
placed on silicon where they can be easily modified during
prototype check-out or production.
The HAL transfer function .is the familiar sum of products.
Like the ROM, the HAL has a single array of selectable gates.
Unlike the ROM, the HAL is a selectable AND array driving a
fixed OR array (the ROM is a fixed AND array driving a
selectable OR array). In addition the HAL provides these
options:
•
•
•
•
Variable input/output pin ratio
Programmable three-state outputs
Registers with feedback
Arithmetic capability
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state. and product
terms connected to both true and complement of any single
input assume the logical low state. Registers consist of D type
flip~flops which are loaded on the low-to-high transition of the
clock. HAL Logic Diagrams are shown with all fuses blown,
enabling the designer to use the diagrams as coding sheets.:
To design a HAL,. the user first programs and debugs a PAL
using PALASM and the "PAL DESIGN SPECIFICATION"
standard format. This specification is submitted to Monolithic
Memories where it is computer processed and assigned a bit
pattern number, e.g. P01234.
Monolithic Memories accepts the PAL DESIGN SPECIFICATION
in one of three forms:
1. Computer generated listing.
2. Typed or hand-written forms F109 andF1.10. See example
on pages 6-7 and forms on pages 23-24.
3. Direct online data transmission to Monolithic Memories
Timeshare computer system via telephone (local telephone
network to major US cities, London and Paris) Or TWX
(online Boston TWX no.).
Monolithic Memories will provide a PAL sample for customer
qualification. The user then submits a purchase order for a
HAL of the specified bit pattern number. e.g. HAL14L4 P01234.
See Ordering Information below.
Ordering Information
, . . . - - - - - - - - - HARD ARRAY LOGIC FAMILY
~------- NUMBER OF ARRAY INPUTS
. . . - - - - - - - OUTPUT YPE
H ~ ACTIVE HIGH
L ~ ACTIVE LOW
c" COMPLEMENTARY
R ~ REGISTERED
X ~ EXCLUSIVE.OR REGISTERED
A ~ ARITHMETIC REGISTERED
r-------
NUMBER OF OUTPUTS
TEMPERATURE RANGE
c~
OC TO +7SC
M~
TO +125C (CASE TEMPERATURE)
. . . - - - - - PACKAGE
. N ~ PLASTIC DIP
J ~ CERAMIC DIP
F ~FLAT PACK
OPTIONAL HI-REL PRDCES81NG
r---~--
lr
"
.
r
HAL14
L4
8'~~f~~~T=~
5005 LEVEL B
~~~8-D~~3500s LEVEL c
~ ~ =:t::~g::: =fT~g
== ~g~:~:t:~
BIT PATTERN NUMBER
cJ 8838 P01234
1165 East Arques Avenue, Sunnyvale, CA 94086 Tel: (408) 739-3535 TWX: 910-339-9229
7-18
.
-ssc
""""'thlo on
"morl• • .
HAL Logic· Symbols
HAL10H8
HAL12H6
HAL14H4
HAL16H2
HAL16C1
HAL Series 20
Absolute Maximum Rating.
Operating
Supply Voltage, VCC •....•.......•..............................•............•••..•. , ••. , ••.•...••••..•. " ..•.•.•.•..• 7
Input Voltage .; ........•...........•...•......................... ; ........................••....•••.••.• ,.' •• . • • • • . ..•. 5.!!N
Off-state"output Voltage •.....................................................•...•..•.•..••..
• •...............••• 5.5V
Storage temperature ..............................................................................'.: •...•.... -{is' to +l50'C
Operating Conditions
.
.
. SYMBOL
PARAMETER
tw
,
. 4.5
s'
25
10
25
10
High
25
10
25
10
45
55
25
35
25
30
.,.45
0
30
"
Width of clock
tsu
,.
Set uptime from
16RS
input ot feedback
16X4 16M
16R6
16R4
Hold time
0
TA
Operafing free-air temperature
.,.55
TC
Operating case temperature
th
",
"
CO",MEijCJAL
UNIT
MIN .. T'fP MAX
Low
Supply voltage
VCC
.
MILITARY
MIN TYP MAX
5.5. 4.75.
-Hi
0
5
,V.
: 5.25
',,'
ns
I
ns
-15
' ': 5
ns
'0
75
·C
125
Electrical Characteristics Over Operating Conditions
SYMBQL
.'
V'L*
Low-level input voltage
VIH*
High-level input voltage
V'C
Input clamp voltage
VCC
',L
Low-level input current
VCC: MAX
"H
t
High-Ieyel input current t
: -lSmA
"
V, : O.;4V
VCC: MAX
I,
Maximum input current·
VCC: MAX
Low-level output ,voltage
10HS, 12H6, 14H4
MIL
VCC: MIN 16H2,16Cl,10LS
12L6, 14L4, 16L2 COM
V,L =O.SV
16RS
16LS
MIL
VIH = 2V
16R6
1684
16A4 COM
16X4
.VOL
MIN TYP tt MAX. UNIT
TEST CONDITIONS
PARAMETER
O.S
:
MIN
High-level output voltage
rnA
V,: 2.4V
25
pt.
V,: 5.SV
,1
rnA
VCC = MIN
V,L = O.SV
V,H
"Off-state output ,current
t
'OZH
Output short-circuit current * *
lOS .. '
V'L
V,H
=
o.siI
0.3
10L = 12mA
=2V
COM
IOH = -3.2mA
16R6
1684',
16X4
16M
Va
= O.4V
Va ,;, 2.4V
'
~ICC
1bl.s, 12L6, 14L4, 1~1,.2
".
Supply current
VCC = MAX
"
Va = OV
10H.S,
. , 12H6, 14H4, 161-12,16Cl
.
.
1~R4, lfiJ:~6,
2.S
'.
VCC : ,5V
16RS, 16L8
V '.
. ,
IOH = -2mA
16RS
6.5
IOL = 24mA
MIL
16LS •
V
IOL = SmA
2.4
= 2V
VCC = MAX
'OZL
V
'-O.S -1.5
..
-0.02 ~0.25
'.'.
VOH
V
2
,
-30
~'
V
.. '-100
pA
100
JJA
-70
'::'130
.55
90
$eeTablel
mK
~,,;,
180
"
:"
16X4
,
16A4
t
I Opln!eakageistheworstca·~.eof lozx or, IIX
eg
:
'IL and 'OZH
tf All typical values are at vee =sil. TA =2S'e.··
..
.
'::',
• These are apsolute voltages with respect to pin 10 on the pevlce and.·includes all overshoots due 10 system and/or tester~oise.
Do not attempt to teSt these values 'without suitable eQuipment.
' ".
** Only one output shorted at a time
7.-20
160
225
170
240 ..
rnA
,"
HAL Series 20
11
il
~i
Switching Characteristics
Over Operating Conditions
,'I
,
TEST
CONDITIONS
PARAM~ER
SYMBOL
MILITARY
MIN TYP MAX
COMMERCIAL
UNIT
MIN TYP ,MAX
10H8 12HS 14H4
1SH~
Input to
tpo
10L8
14L4
output
Rt
12LS
R2
1SL2
= 5600
= 1.1kO
25
16C1
tpo
16R616R4
Input·or feedback ~o output
1SX4
16L8
16A4
25
45
35
25
45
25
40
25
3Q
45
25
35
45
3Q
40
ns
ns
tCLK
Clock to output or feedback
15
25
15
25
ns
tpZy
Pi n 11 to output enable
15
~5
15
25
ns
tpxz
Pin 1t to output disable
ns
tplzx
tpxz
fMAX
t6R6 1SR4 1SL8
16X4 16A4
Input to
output enable
' Inpuna
output disable
16R6
Maximum
frequency
16R8
16R4
16X4
15
25
15
25
R 2 "3900
25
45
45
25
3Q
35
40
45
25
35
45
30
40
30
25
30
l6L8
16A4
16R6
16X4
R1 =2000
"
1SR4
16A4
14
25
16
25
12
22
14
22
ns
ns
MH~
Test Load
5V
OUTPUT o--+--~~) TEST POINT
" 50pF
HAL16L8, 16R4
HUM_ER OF
HAl16X4
16R6, 16R8
PRODUCT TERMS
0
1-4
5-8
g;.12
13-,16
17c;20
SChematic of Inputs and Outputs
vcco---.......-
__
INPUTo-~+_-_'KH~
_ T....
Vp
....
IC....
AL
....O:.::U....
TP.;:.IJT~---oVCC
21-24
25-28
29-32
3s.:SS
31,.4Q
41-44
45-48
49-52
53-00,
57-60
61-64 '
99
101
104 '
106
108
110
113
115
117
119
122
124
126
128
131
133
135
97
101
10S
110
115
119
124
128
133
137
142
146
151
155
160
1S4
169
HAl16A4
108
113
117
122
126
131
135
140
144
149
153
158
162
167
171
176
180
"
Table 1.:TypIcaIICC
VI.
Num~r of PfOduct. U I4Id
HAL i''2.'-1(.,
HAL DESIGN SPECIFICATION
PART NUMBER
PW 1'2~4
'2./ t./ !II
USER'S PART NUMBER
T:!:.A~LC
NAME
REV
c:..A-re.OS
DATE
Eo'" "IoI\PL.E
TITLE
MO\.JO'-''T~c..
.....~O«AEc..,
c.A'-'\~oe""IA
COMPANY, CITY, STA TE
C
D
PIN 1
PIN 2
\J
~
PIN 6
PIN 7
J
"'-
PIN 11
e:-
F
PIN 12
M
PIN 5
PIN 3
PIN 4
1:
GND
PIN 8
PIN 9
PIN 10
\..
12-
PIN 13
PIN 14
0
PIN 15
\-\
Eo
'&
A-
VCC
PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
EQUATIONS
~
~ \N'I6a.'T&Q.
-/A
e-=-c.·O
; At-JO
\-\:1=+0.
')
On.
)
t-J,..uo GATe.
o '= 1t-I\ iii'- l).l
;
~oa.
Grp."'te
2 "'P~/Q + Ip~Q
')
Xoa.
~A"Te
\... '=
/1 +/J +
I~
~
G~
DESCRIPTION
\~t:.
e...,c...c..-~c-e
~S\C.
LEGEND:
\ ~U ..,caA'"t'6S
~~c.
"To I ""'-PUS~e.e-sr
c...A.""t&S.
EQUAL
: = REPLACED BY
+
*
OR
AND
F 110
7·22
AeeA'i
:+:
: *:
XOR
XNOR
/
(
)
COMPLEMENT
THREE-STATE
FUNCTION
TABLE
A
l!>
PIN A
PIN B
a.
J:
t:::.
'-
PIN K
1>
PIN M
~o
en..
UAWQ
;..A. e. E-
~ .§.. .J!... ~
!:i
PIN N
0
PIN 0
PIN R
...,0. .
"OR.
A ~ d.. "'" ~ ~ ~ ...2- ~ ~
ABCDEFGH
J
PIN J
g
C\
PIN Q
COMMENT
PIN E
:1
PIN I
M.
PIN L
PIN P
,""'"
PIN H
e.
t)
PIN D
H
PIN G
PIN F
;
C
PINC
2-
COMMENT
IJKLMNOPQR
~~~~~X.~~~~~~X~A~~~
~~~~~AAAA~A~~A~~~~
~~~~~L~~AAA~~~A~~~
~~~~~~~~AA~~AA~A~~
A~~h~~AAA~AAAA~~~1
A~o
~X~~~XX~~~~A~AbAA~
XAAA~~~~AA~~~~~1~~
A~AL~~~A~~X~~~~~~~
~AA~A~~~AA~~X~XX~~
02.
~~~X~~~i~~~~~AA~~~
02
A~~~~X~~~~~~AXAAXX
~&A~AK~~~~~~~~X~~X
~~AA~i~A~~~~~~X~AX
X&~~1~~~~~~A~~ALA~
A~A1~A~A~~~~~XAAXX
~K~~~AX~Xg~A~~Ax~~
~~XXA~XKX~A~~~~X~~
~~A~~AXAX~~X~~~~~X
~~~~A~~~AA~~~~~~~~
~~~AA~~~~X~~~X~~~~
---------------~--------:-------- ...... -----------~--------'--- ..... ------------~-...:.:.... -'~~.;.
LEGEND:
Z
OFF
H HIOH
C CLOCK
.
X IRRELEVANT
L LOW
7;023
Not••
., i.A
HAL Series 20
Logic Diagram HAL 1 OHa
INPUTS (0-31)
0123
1
45
, 9
121l
1617
2021
2425
2B2g3031
I
.
~
•
~
1
19
"1
2
....
,
,......,
3
18
~
9
...
...
17
16
11
4
...
en
15
14
:::iE
25
a::
w
~
~
o
c
5
-
....
:::)
o
a::
Q.
,......,
32
15
33
6
...
~
4.
14
41
7
.
...
~
13
48
49
8
...
12
"
5)
9
...
11
L
""4
0123
4 S
, 9
1213
1617
2021
2425
282930]1
..
AI!'
HAL Series 20
Logic Diagram HAL 12H6
INPUTS (0-31)
0123
1
1
4561
·89
1213
1617
2021
24252627
28293031
...
~
.....
...
...
.
,•
10
"
J
~
16
!II
:E
w
lI-
,
...Jt
16
~
~
.
o
::l
o
"
J2
J3
o
a:
a.
17
-E
~
24
25
a:
,
18
, ./
...
.17
4
"""
19
.
.... ~
.....-
40
14
41
1
.....
~
~
48
49
50
.,
9
"""
13
;/
."
8
I
..
....~
\
111::
.
...
....
...
0123
4561
89
1213
1611
2021
242lH621
28Z93031
11
11
HAL Series 20
Logic Diagram HAL 14H4
INPUTS (0-31)
...
2
...
3
012 J
....
1
4561
B 91011
1213
1617
20212223
24252627
28293031
....
...
...
19
~
4
...
.
~.
P'
16
17
17
"
./
19
5
.
18
P'
U)
:IE
a:
w
~
24
16
15
~
Z6
27
~
-:1-./
(J
::;)
Q
oa:
Il.
......
32
J3
34
35
6
~
......
42
43
9
15
""
14
....
41
8
""
./
...
"
7
,
~
.....
J
13
"'"
....
11
...
"'"
....
...
...
0123
4567
891011
1213
16-17
20212223
24252627
282930Jl
"'"
11
HAL Series 20
Logic Diagram HAL 16H2
INPUTS (0-31)
1
2
...
0123
4567
891011
121314151617181920212223
-2425262'7
28293031
...
...
~
~
...
3
O"
,
I'
4C.
18
'"
...
...
....
17
14
25
"
"
27
28
II)
:E
30
IX
W
l-
5
t::l
...
...
""
16
"'
15
./
31
J2
lJ
34
Q
35
o
"
"
./
37
IX
38
Q.
G
.
....
O"
7
8
•
...
....
...
13
'"
......
....
I'
'"
.
....
12
'"
....
~
o1
2 J
4 5 6 1
8 91011
12131415
16111119
l0212223
24252621
28293031
11
HAL Series 20
Logic Diagram HAL 16C1
1
.
2
.
3
4
INPUTS (0-31)
(1123
4 S6 7
8111(111
12131415
1611181920212223
242!i2621
"28293031
~
...
C
...
19
....
....
18
....
17
...
....
...
...
....
24
15'
"
27
28
5
..
"
30
It
16
...
T
1
15
"
"36
31
J4
17
38
30
6
....
...
14
....
\
7
8
....
....
13
....
,
.....
'
....
12
,
"
9
po
(I
I 2 J
4 5 8 J
8 11011
12 1:11415
111 \11819
Z!U12Z23
24252&21
28 Z9 lD3:1
-.....
11
7-29
HAL Series 20
Logic Diagram HAL 1 OL8
INPUTS (0-31)
0123
1
45
, 9
1213
1611
2021
2425
ZUllO]!
....
~
,
19
1
2
..
--1
•
~
18
.~
17
9
3
..
..
"'-----I
""
•
~
...
~
16
24
"
5
....
15
32
"
6
.
~
.,.
I.
40
41
1
.
~
,
49
8
~
..
....~
r-.
""
9
13
~
48
12
~,
....
11
---1
""
01 Z 3
.........
4!i
'9
1213
1611
2021
2425
28293031
HAL Series 20
Logic Diagram HAL 1 2L6
INPUTS (0-31)
0123
1
...
2
...
4
r.
61
89
1213
1617
2021
24252627
28293031
I
~
....
...
J
8
9
10
11
3
18
./
~
...
,
"
17
4
.
19
17
.
16
24
Z5
!II
:i!
a:
w
~
5
ti:::l
....
...
a:
0..
6
..
:>:
i-< ~.
40
41
7
15
~
31
33
o
o
...
..
~
~
48
I
13
49
J
50
51
8
9
14
.
.. .:>:
...
12
...
11
...
-it.
...
0123
4 S. 67
89
1213
1617
2021
24252621
28293031
...
HAL Series 20
Logic Diagram HAL 14L4
INPUTS (0-31)
1
...
,
...
3
....
G 1 Z 3
4567
891011
1213
1611
20212223
24252617
:'8293031
...
....
~.
....
...
~
,
...
..c:
~
~
~
I
5
18
"'"
~
16
11
18
19
e.
..
19
11
./
...
VI
:::iii
~
24
15
II:
W
....
t;
16
"
16
.
./
~
......
::J
Q
oII:
D.
31
.
l3
"
lS
,
.
15
~
"41
41
-:J.-.-,/
'3
1
...
..
8
...
....
,
...
...
...
...
0123
4567
891011
1213
1617
20212223
24252621
I
28293031
"
13
...
"
....
11
...
HAL Series 20
Logic Diagram HAL 16L2
INPUTS (0-31)
o
1
2
3
•
...
...
...
1 2 3
4 5 6 7
8 9 1011
12131415
16171819
2021
a,n
24252627
28293031
I
~
~
JC:
...
19
~
....
....
....
....
...
.....
...
18
17
24
15
16
~
17
18
~
II:
W
5
lI-
.
16
../
19
30
CI)
31
~
31
U
33
34
35
36
:::>
o
"-
15
....
....
,
.....
....
13
.....
....
....
o
../
3J
II:
38
Q.
39
6
7
B
9
....
.
....
..
12
11
JC:
~
D 1 23
4567
8 '111111
12131415
16171819
20212223
24252627
211293031
7·33
HAL Series 20
Logic Diagram HAL 16L8
INPUTS (0-31)-11123
4!i 6 7
B 91011
12131415
16111819
20212223
242'52621
28293031
,0
~b-J
2
3
4
5
1
6
7
..
....1---
...:>
,
"
B
~~~
10
12
13
3
19
18
14
15
....
....
.1--~
16
17
>--J
1B
"
2D
21
22
17
23
4
...
...:>
c:.r-24
~;-J
25
"
27
""
"
I/)
::E
w
3D
a:
....
....
16
5
o
::;)
c
...
....
.r-~
32
b-J
,,""34
o
16
a:
31
Q.
3B
39
6
..
h
.r-40
41
42
~
43
7
.
..
44
~
45
f---;
"
~
41
~
.
51
52
53
"
55
14
..." I - - 13
..... r - -
.
h
~"
"
"
~
57
58
6D
61
62
h
f--'
~~
"
9
J
....
........
~
4B
8
15
"
A
...
~
o1
2 3
4 5" 6 1
1 9 lOti
121}1415
16111819
29212223
24252&11
l82,3031
12
11
HAL Series 20
Logic Diagram HAL 16R8
-
INPUTS (0 31)
1
0123
4561
891011
12131415
1617 1819
20212223
24252627
28293031
I""-'
0
I
1
3
4
5
6
rH '.-/
)
1
....~
A
~
...
....
8
9
10
II
11
13
14
15
J
~
t=J
...
........
.~
.Jt
....
'.-/
1U
11
11
....
...
~
~
~
~
)---'
16
17
I'
19
4
:C~
Q~
13
...
--
51
51
53
54
"'./
55
...
~
~
~
41
)
~
s::""4
tll
~
tll
56
5)
58
'j
59
60
r-D
61
62
9
...
)---j
63
>
-<£
""""I
0123
4561
891011
12131415
16111819
20212223
24252627
Q
f---
°l
~
-~
18 293031
7.35
HAL Series 20
Logic Diagram HAL 16R6
INPUTS (0-31)
1
012 ]
4561
891011
12131415
1611
19
2fl212~23
24252627
28293031
•,1
r-J
,
•
••
19
1
~
A
JIi~t---~
,
9
I.
11
1>
1!
I.
I•
J
~r-~
""', /"
....
A
~
~~
16
Il
1.
19
2D
....
r---
""'"
o or--
../
21
"
2!
... ...,
~~
t:...2
J
~
24
""
"
""
'\.
. ./
28
5
..
!1
~
""!4
"!6
""
>- ~
!l
6
..
...
,
4D
41
,
"44
4!
..
,/
45
1
..
4l
.......
~
~
~
~
P1
~
48
49
"""
"
"
~r-
,/
54
8
....
...
,
"
_~b-J
"""
"
9
.
"
62
"
012: 3
4561
• 9 1011
12131415
16171819
20212223
24252127
28293031
.....t----
~
~~
12
~
HAL Series 20
Logic Diagram HAL 16R4
-
INPUTS (031)
1
012 J
4561
891011
12131415
16111819
20212223
24252621
28293031
0
:>-J
1
2
3
4
5
6
7
3
...
.....
"I---
~
•
rJ
9
10
11
12
"
14
J
...
"1-17
18
ar-~
'"
20
21
D
./
,
22
...
18
15
"
"
4
19
"
....
c:
..........
~ °l
""
""
26
f/)
27
2B
:::E
w
3D
31
l-
5
t)
::::l
C
o
a:
~
.....
""
....
~
{t
°l
J
.
.c;
...
""
32
3J
34
J5
,
3B
./
37
ti
..
...
""
"--I
"
41
42
43
44
"'"../
"""
46
48
7
...
""
41
,
.
48
8
...
"55..
~
13
.....
.c;~1---
""
58
57
:r-J
""
eo
81
""
9
....
r-J
50
51
52
~
-Dl
Dl
'"
"
a:
12
;
...
"--I
o1
2 J
4 5 •
7
• 9 1011
12131415
1&11 tilt
211212223
24252621
212.93031'
..... t - - -
~
7·37
HAL Series 20
Logic Diagram HAL 16X4
INPUTS (1).31)
0.'2 1
4
~
6 1
891011
121J1415
1&111819
20212223
24252621
21293031
0
~
1
2
J
,
4
6
2
1
....
""'I
8
9
10
~
11
12
"
14
.......
3
"
16
"
18
;:::-
19
20
21
22
2J
,
r-<
=t:S-
~-,.
"
··,-,c
"'P
~
-t.,J-
28
"
~
18
~~D-~Q
~
~
2S
26
\
19
1~D-
~
~
~
~
~
~
12
II
34
:'~J)-
l5
l&
31
".
~::t-./
19
1-
6
fE
---"
~
~D-Cfl
41
42
43
44
""
47
I
,
~
-vo-"
f~
t:!:f-'r..
.: ,....
4ft
49
~
"
"
"""
""
"
51
8
.......
-.,...,.
~~J
""
61
62
9
7·38
.....
...
13
6l
-.,...,.
012 J
4-!i 61
891011
12131415
16171819
2~21
2223
24252621
282930Jl
12
11
HAL Series 20
Logic Diagram
INPUTS (11-31)
>-------------------------------------------~
"23
4511
8'1111
'213M'.
111'1111
HHHn
unnn
HAL 16A4
nH.~
1.
z ..
...
••
"
11
12
,.
"
t3
3
...
...
l'
11
17
11
"
"
"
21
23
4
1I
~
27
~
28
"
30
11
II)
:I
II:
""
"
5
~
w
l-
t)
~"
::l
.
.
33
Q
0
35
II:
IL
"
"
3.
6
1I
..
41
42
43
44
45
.,
44
7"
~
I
-- ..
""
""
IO
53
• •...
.
54
55
51
'7
51
51
if
.."
II
..
...
EI
HAL DESIGN SPECIFICATION
PART NUMBER
I
USER'S PART NUMBER
REV
NAME
I
DATE
TITLE
COMPANY, CITY, STATE
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9
PIN 10
PIN 11
PIN 12
PIN 13
PIN 14
PIN 15
f."'It.., PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
GND
VCC
~II'
EQUATIONS
DESCRIPTION
LEGEND:
= EQUAL
:=
REPLACED BY
+
*
OR
AND
F -110
'7.4n
: +:
: *:
XOR
XNOR
/
(
)
COMPLEMENT
THREE-STATE
FUNCTION
.
TABLE
PIN A
PIN B
PIN C
PIN D
PIN E
PIN F
PIN G
PIN H
PIN I
PIN J
PIN K
PIN L
PIN M
PIN N
PIN 0
PIN P
PIN Q
PIN R
I
COMMENT
1-- C
- - -D- -E- -F- - G
AB
-H- - - - J
COMMENT
-K- -L- - M -N- -0- - P -Q- - R
-~-------------------------------------------------------------------------
-"- -- -- --" -- - -- - - -- -- -- - --
-
-"-
-- --
-- --- -- -- -- -- -- -- -- -- - -- -- -- -- -- --"- -- -- -- -- - - -- -- -- -- -- -- -- -- -- -- --
-
-- -- -- -- -- --- -- -- -- -- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -"
"
----"----.-" "--------------------------
-- --"- -- -- -- -- -- -- -- -- -"- - -- -- --- -- -- -- - - --" -- -- -- -- --""
-- -- -- -- -- - -- -- -- --- -- -- ---"...-.-,
"--
---------~-~------------------~-~-~-~--~.~~~~-----------------------------LEGEND:
H HIGH
L" LOW
F 109
C
CLOCK
X
IRRELEVANT
z
OFF
Hard Array Logic Family
HAL Series 24 Data Sheet
Features/Benefits
• Gate array equivalent of up to 300 gates.
• Semi-custom solution
• Reduces SSI/MSI chip count greater than 5 to 1
• Prototype using field-programmable version -
PAL.
• Cost savings up to 40"10 compared to PAL
• Security link disabled for design secrecy.
• Test and simulation made simple with PALASM Function
Table
PART
NUMBER
PKG
DESCRIPTION
HAL 12L 10
HAL 14LS
HAL 16L6
HAL 1SL4
HAL20L2
HAL20C1
HAL20L 10
HAL20X10
HAL20XS
HAL20X4
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
J,N,F
Deca 12 Input And-Or-Invert Gate Array
Octal 141nput And-Or-Invert Gate Array
Hex 161nput And-Or-Invert Gate Array
Quad .1Slnput And-Or-Invert Gate Array
Dual 20lnput And-Or-Invert Gate Array
20 Input And-Or/ And-Or Invert Gate Array
Deca 20 Input And-Or-Invert Gate Array
Deca 20 Input Registered And-Or-Xor Gate Array
Octal 20 Input Registered And-Or-Xor Gate Array
Quad 20 Input Registered And-Or-Xor Gate Array
• Saves space with 24-pin SKINNYDIP'· packages
To design a HAL, the user first programs and debugs a PAL
using PALASM and the "PAL DESIGN SPECIFICATION"
standard format. This specification is submitted to Monolithic
Memories where it is computer processed and assigned a bit
pattern number, e.g., P01234. Monolithic Memories accepts the
PAL DESIGN SPECIFICATION in one of three forms:
Description
1. Computer generated listing.
The HAL family utilizes standard Low-Power Schottky TTL
process and automated mask pattern generation directly from
logic equations to provide a semi-custom gate array for
replacing conventional SSI/MSI gates and flip-flops at reduced
chip count.
2. Typed or hand-written forms F107 and F108. See example on
pages'7-30, 7-31 and forms on pages 7-42 and 7-43.
The family lets the systems engineer "design his own chip" by
AND and OR gates to perform his desired logic function.
Complex interconnections which preViously required timeconsuming layout are thus "lifted" from PC board etch and
placed on silicon where they can be easily modified during
prototype check-out or production.
The HAL transfer function is the familiar sum of products. Like
the ROM, the HAL has a single array of selectable gates. Unlike
the ROM, the HAL is a selectable AND array driving a fixed OR
array (the ROM is a fixed AND array driving a selectable OR
array). In addition the HAL provides thee options:
• Variable input/output pin ratio
• Programmable three-state outputs
• Registers with feedback
• Exclusive-OR gates
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any single
input assume the logical low state. Registers consist of D type
flip-flops which are loaded on the low-to-high transition of the
clock. HAL Logic Diagrams are shown with all fuses blown,
enabling the designer to use the diagrams as coding sheets.
SKINNYDIP is a registered trademark of Monolithic Memories
1165 East Arques Avenue, Sunnyvale, CA 94086
'7_A"
3. Direct online data transmission to Monolithic Memories
Timeshare computer system via telephone (local telephone
network to major US cities, London and Paris) or TWX
(online Boston TWX no.).
Monolithic Memories will provide a PAL sample for customer
qualification. The user then submits a purchase order for a HAL
of the specified bit pattern number, e.g., HAL 18L4 P01234. See
Ordering Information below.
Ordering Information
. - - - - - - - - - - - H A R D ARRAY LOGIC FAMILY
, - - - - - - - - - N U M B E R OF ARRAY INPUTS
. - - - - - - - - O U T P U T TYPE
L = ACTIVE LOW
C = COMPLEMENTARY
X =EXCLUSIVE-OR REGISTERED
. - - - - - - - N U M B E R OF OUTPUTS
.------TEMPERATURE RANGE
C = OC TO +75C
M = -55C TO +125C (CASE TEMPERATURE)
.------PACKAGE
N = PLASTIC DIP
J = CERAMIC DIP
F= FLAT PACK
.----OPTIONAL HI-REL PROCESSING
BB3B = MIL-STD-BB3,
METHOD 5004 & 5005 LEVEL B
BB3C = MIL-STD-BB3,
METHOD 5004 & 5005 LEVEL C
B = MIL-STD-BB3,
METHOD 5004 EQUIVALENT
C = MIL-STD-883,
METHOD 5004 EQUIVALENT
BIT PATTERN NUMBER
r
HAL 18 L4 CJ 8838 P01234
Tel: (408) 739-3535 TWX: 910-339-9229
16Jnollthlc mt!n
lIIemorles In.In.LI
HAL Series 24
HAL12L10
HAL14L8
HAL20L2.
HAL20L10
HAL20X10
HAL16L6
HAL18L4
HAL20C1
HAL20X8
HAL20X4
7-43
HAL "rl_ 24
Absolute Maximum Ratings
Operlllng Progl'lllMllng
Supply Voltage, vee ................................................................................ 7 .......... 12V
Input Voltage ...................................................................................... 5.5V .......... 12v*
Off-state output Voltage ............................................................................. 5.5V .......... 12V
Storage temperature, ................................................................................... -65° to +150"0
Operating Conditions
VCC
MILITARY
MIN TYP MAX
PARAMETER
SYMBOL
Supply voltage
I Low
COMMERCIAL
UNIT
MIN TYP MAX
4.5
~
40
20
35
5
20
30
10
25
10
5.5
4.75
tw
Width of clock
tsu
Set up time
60
38
50
th
Hold time
0
-15
0
TA
Operating free air temperature
-55
TC
Operating case temperature
I High
Electrical Characteristics
SYMBOL
VIL
High-level input voltage
Input clamp voltage
IlL
Low-level input current
IIH
High-level input current
II
Maximum input current
t
t
Vce
Vee
Vee
VIL
High-level output voltage
Vil
VIH
t
IOZH
Output short-circuit current
**
Supply current
= MIN
= 0.8V
= 2V
12L10, 14L8.. 16L6
18L4, 2Ol2, 20el
= MIN
= 0.8V
= 2V
Vee
= 5V
Vee
!i,
MAX
t
I/O pin leakage is the worst case of 10ZX or IIX e.'g. IIX and 10ZH
7·44
-0.8
-1.5
V
-0.02 -0.25
mA
VI = 2.4V
25
JJA
= 5.5V
1
mA
VI
,2OL10,20Xl0
2OX8,2OX4
10L
= 8mA
0.3
MIL 10l = 12mA
COM 10l = 24mA
0.5
V
IOH
= -2mA
Mil
IOH
=. -3.2mA
COM
Vo
= O.4V
-100
.JJA
Vo
= 2.4V
100
JJA
mA
2.4
VO= OV
2.8
V
-70
-130
12L10, 14L8. 16l6,
18L4,20l2, 20Cl
60
100
2OX4. 2OX8, 20X10
120
180
90
165
2OL10
. tt Alltypical~aluesareatvcc =5V. TA ~ 25°C.
* Pins 1 and 13 may'be raised to 22V milx.
* * Only one output shorted at a time.
V
V
= -18mA
= O.4V
VI
VIH
VIL
II
= MAX
= MAX
= MAX
= MAX
= 0.8V
= 2V
Vee
Off-state output current
ICC
MIN TYPtt MAX UNIT
2
VCC = MIN
Low-level output voltage
10ZL
°C·
·C
0.8
Vce
lOS
75
0
TEST CONDITIONS
VIH
VOH
ns
Over Operating Conditions
Vee
VOL
38
-15
Low-level input voltage
VIH
V
ns
125
PARAMETER
VIC
5.25
-30
,
rriA
HAL Series 24
Switching Characteristics
Over Opel8Ung CondlUons
PARAMETER
SYMBOL
TEST CONDITIONS
12L10, 14L8,
Input to
tpo
output
R1
16L6, 18L4,
R2
2OL2, 2OC1
MILITARY
MIN TYP MAX
= 5600
= 1.1kO
COMMERCIAL
UNIT
MIN TYP MAX
25
45
25
40
ns
tpo
Input or feedback to output
35
6Q
35
50
ns
tCLK
Clock to output or feedback
20
35
20
30
ns
tpzx
Pin 13 to output enable
20
45
20
35
ns
tpxz
Pin 13 to output disable
20
45
20
35
ns
35
35
55
35
45
45
ns
tpzx
Input to output enable
tpxz
Input to output disable
fMAX
Maximum frequency
20L 10, 2OX10
20X8,20X4
R1
R2
= 2000
= 3900
10.5
W
35
55
12.5
16
ns
MHz
Test Load
SV
A1
\lUTPUT
TEST POINT
Schematic of Inputs and Outputs
EQUIVALENT INPUT
VCCQ--.....:..........- - -
IkO NQM
TYPICAL OUTPUT
--""':"''''':''';'-=''.._-oVCC
400 NOM
INPUTQ-.._+----f« .....+_
7·45
HAL ZO)(IO·
HAL DESIGN SPECIFICATION
.PART NUMBER
o
aNT 8C.2
USER'S PART NUMBER
2/78/8'
REV
NAME
DATE
l)~
t)4
NOWA,I- '12~,s""l&
pOMPANY, CITY, STA TE
e'"
1>'2
1)\
po
PIN 3
PIN 4
.1)'5
AIN 2
Ole
07
D6
Ao
PIN 7
PIN 8
PIN 9
. PIN 10
PIN 11
PIN 1
loe
ge
NC
pai
4
PIN 15
PIN 19
PIN 20
PIN 21
PIN 16
Q2.
Q)
PaC)'
PIN 22
PJN23··
lao ~ = I ao ./LO
EQUATIONS
+ loa
/Q?:.
~
OS
PIN 18
vce
PIN 24
QD.
·;LOAO 00
;~Ql
; LOAD O.
Qt
I-OAO 02,",0'-0 Q3
; ,",OLD
t)!.. .. \..0
;
: -/O!> .. /\..o
)
;'-/03 #It-
GND
PIN 12
;Ha...o
LO
tQ\ :=/Gl'''' .fLO
+1 0\ JI. LO
/Q'2. ::/Q~ ,.. /1-0
+/
PIN 6
Q2
(;)7
P
Q4
.' PIN 5
Lo
; LOAD '03
/Q4- :~/G+ ,./\..O
)~1.'D
Q4'
+/1)4.. LD
IQS : =.J Q5 *" / L 0
;L~D
'04-
; \-k)L.t)
QS
; LQA.t)
0'5
+/05.
LO
;"-OLO QCo
+/01....
; LOAD 'O{g
L..O
.;~G7
Icto
+/'07 .... \"D
; \..01\0
01
::r./Q&" / LO
~Ha..O
~/05"
; LC»\D
QS
08
DESCRIPTION:
l\\e wOa.Jt..L.. U6\'a~. as'
\\l~
\F L-OAro L..\a.l6
LEGEND:
:=
7 ..46
A q-'O\T 2l:.E.iIi.Tea.. :!]urr . \...o~ -ntE. 'DA~
I~ SELrCt1!!;o O"n\e(bN,'$6 ~ ~
EQUAL
REPLACED BY
+
*
OR
AND
F 108
:+:
: *:
XOR
XNOR
1
(
02.\UtlJQL 0Al}l..
COMPLEMENT
). THREE-STATE
I
JUNCTION
TABLE
!'r-:--:--:CK
,
oe.
t:n
PIN A
PIN B
PIN C
PIN D
PIN E
D1S>
'04
])3
O~
PI
PIN H
PIN I
I PIN G
as
G7·
I
· PIN M
I
. Q2
I PIN S
Olp
PIN 0
PIN N
00
PIN L.
PIN K
QS
Q4
Q~
PIN P
PIN Q
PIN R
QO
Q\
PIN T
~
PIN J
PIN F
PIN U
PIN V
~-n. Our
'ODtp. \N
COMMENT
~~A~L&AL&AAX~~~~~~~~b_
~.Aahh~~~~~~~L~~~~~~~h~
~
Au....
~A~~~X~XXXAX~h~~k~b~h_
.tb.;O
AU-'~
~AJlA~~A~~AAAAA~~~~~~A_
~'P
ALl-.~
UOLO
A~. 0J.JeS
l~~X~XX~A~~X~~~~~~~~~_
~A&k •. ~~.I ~LA~~"~a~A~d~_
"2'.E£OS
"tEST E\lelJc",lC:iiIr.eoAID
[AAA:A~~:~~~~~&~~h&:~_
"T"E$;' 0t:J0 C"«~
~~---------:--------~:----
EI
-------..---_. ---~------,-.-----------------'~.----
- - ---- - - - - - - - - - , - - - - - - - - --- -
-
-
- - -
-
- - -
---~-- --:--
.
.
--:.- -,~
-
-"- -
-
~
- - - -----,--'--.
.
- - -,-
-"- -
-- -
----~--------
~'-'~
-
-
.
- -
-- -
~,--
-
.
----
---_._'!'-- - - - -
------.. .-----.. .-;...------------:-"-'----------~~---------------...:.------..:..----~-:"'--~7""--.....:;
LEGEND:
H
L
HIGH
LOW
C
X
F 107
CLOCK
IRRELEVANT
Z
OFF
7·47
HAL Series 24
Logic Diagram HAL 12L 10
INPUTS (0-39)
o·
123
45
8 ,
1213
21121
2425
2829
3233
3& 313839
L-b•
-Q-f""
23
-0---1"
~
22
~
21
-0-,
20
..n-
19
---'
1
~
..-0-
,
8
~>
"
11
4
-U-
.2
-
"
25
~----i~
l2
-t}-L.
33
6
~
..
':""~
18
B=D
17
~
16
...n..
-tJ-L.
15
-O-L
41
7
..
49
8
.2
-
"
"
9
.2
""
~>
~
"
~
~
012
7-48
-
-0- -L./
"
1
45
1213
2021
.l"
25
14
13
HAL Series 24
Logic Diagram HAL 14L8
INPUTS (11-39)
0123
4561
89
1213
16
n
2021
24 H
2829
32333435
J611J819
.
~
~
~
,
~
00(
•
3={1
"
11
3
23
22
....."
....2
~-.:5-.J
"
"
21
•
-
24
5
.
6
,
....,
--'"'-]
3J
2
-..... -,'"-
.
-
"
7
..
-Q-;'
-U.
17
-Q-;"-.
18
:>
"
"
1..)-
..
~
..
..
.l""\---I
51
1-t
-{ ' ".
1-t-j.....'
15
.....,.,
"
~~
~
~
11
18
~
..
•
.
2
12
8
20
.......
"
..
2
,
0'
,
1
456'1
,
.
c:
~
1-113
1611
2021
2425
""
123314JS
]6J1l1lt
1.
...
13
HAL Series 24
Logic Diagram HAL 1 6L6
INPUTS (0-39)
o
1
2 1
4
5
6 1
8!1 Hill
1213
1611
2021
2425
282930]1
323334 35
36313839
~
2
23
to..,-
v-
."
....,
41
7
8
...
)k
AI;
;e;:
...
9
19
18
~
....
~
.-rl
10
11
17
16
15
14
13
---I
D 12
J
8
9 1011
12131415
Ifi1J II"
20212223
24252621
21Z93031
12lJ14l5
7·53
HAL Series 24
Logic Diagram HAL20L 10
INPUTS (0-39)
012
J
4,
G I
a
91011
1213141S
1617 1819
10211221
242>2621
2629)031
121114 35
36]1 lBJ9
",
23
r--~t~
-,
,
J
~
.r---
.,
--'"""
J-".-L~
"
-.-
"
22
.....
3
4
--'"""
"
"
"
"
1:'~~
"
"
"
LJ'~
.
"
5
J>
(/)
-<-
JJ
W
tJ.
~:1
L.J .-
"
"
II:
19
6
o
::J
.....
'"
C
o
II:
7
..
;J
=P:=:l"\ N.
"
"
"
C.
.L.J
-
-
14
~
I
o ,
7-54
20
~
::E
lI-
21
1
J
4
~
6
I
I
8
I
9 10 11
12 I) 14 1~
,~ II
18 19
20 21 12 1]
Zq 2, 16 1I
II 19 ]0 31
]1 II 34 1,
16 11 3B 39
13
HAL Series 24
Logic Diagram HAL20X10
INPUTS (0-39)
1
.
0123
456
J
B
9 lOll
12131415
16111819
20212123
24252621
282930Jl
J211J4l5
.-...
......
r-..
......
36373839
,
,
J
-tH-9~
-b--L
Pl~
~DHL
~
~
..
,
...
Pl
~~ ~
Pl
"
"
"
"
~D-t5--!
;::::-
"
3
j(
"
"
"
"
4
5
-t5-L
~
~;::,
~
n~~
"
"
"
JJ
-t""'5--L
~~
~
.
"
=ti=L .
...
.-...
"
7
1;:1.
18
v
~
......
~D...
"
"
~...
"
"
"
;0
...
.
"
"
"
10.
~
~
~D- U]
"
9
...
~
i;:1 20
-vo-----
~
~
~D- U]
i;J.
......
=R:~D-
~
~
-t5--L
>.
~
16
V
~C
~~tfJ:]
~
-
"
.-...-
"
"
"
1-<1
~-
Q
"'"
11
o
1
2 1
4
~
6
J
a
9 10 11
11 13
14'~
II. 11 1119
1011 12 21
24 H 26 27
21 19 ]0 31
31 II J.I lS
36 11 3119
~
~.
HAL Series' 24
Logic Diagram HAL20X8
INPUTS (0-39)
1
II
121
4
~
ti
1
1"011
12131415
16111819
20212223
l' nZ&21
21Z93031
3211M]5
J6313839
D
,
,
,.....
~
J
...
~
.
I
~
-Q-,-9~ :f1]~
.,
"
3
23
~
"
"
"
"
4
;:::::::::
-R-f~D
::Jj:L
:f1] ~
~D
-O-L .
~~
~
"
"
"
~
-
"
~
III
:E
a:
w
t
::::I
C
~D
,.""
"
l-
6
...
o
If
~
...
'";l.
18
~D
&
-
--;J..
-yo-
17
=rL........
16
'";l.
15
~
"
8
"
"
,
"
"
IDD
..
.
,.....~D
9
"
10
Br
..
~
fiJ
t;.
.....
.....
~
~
..""
~
-
"
~~
II
7-56
~
.....
fiJ
;::::~D
m..
fiJ
~
"
"
7
fiJ
,
2 1
4 5 '1
.!
..J..
.....
14
.A.
""'F
1011
n 13'415
'611 11"
211 212223
24 25 16 21
2' 19 311 31
Ull)4 lS
3631 Jilt
13
HAL Series 24
Logic Diagram HAL20X4
1
INPUTS (0-39)
....
....
.,
012
J
456'
a
9 lQ 11
12131415
16111819
lO211213
ll252621
21
2~
JO 31
12111415
J611lSl9
~
~
--K-r
2
J
~
,
,.
J
~J
~
r\--L
9
3:F~
"
23
:J
:.;:l.
22
3
~
""
~
"
~Dt>-L
~~
""
4
"
"
"
en
:::e
5
IX
LIJ
:::-::::~D-
JJ
,.
O
5
o
"J2
t-
::{j:j
"
6
----I.
.
IX
Q.
~Dfu
"
"
"
7
21
::k
.
~
~
~
~
19
~D-~ ~
"
"
a
J-j
"
8
"
"
i:H>
~ ~1
";g
9
..
~
fu~
.
"
"
10
16
15
~
"
"
"
~l
"
~~
~r--'
o
1
1
1
4
~
6.
J
•
9 10!1
12 1314 ''''
1611
n
19
1021 22 23
14 25 26 11
21 1930]1
11 JJ 14 U
li lJ
]I
14
~
19
7-57
HAL
HAL DESIGN SPECIFICATION
PART NUMBER
I
USER'S PART NUMBER
REV
NAME
I
DATE
TITLE
COMPANY, CITY, STA TE
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9
PIN 10
PIN 11
PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
PIN 21
PIN 22
PIN 23
PIN 24
GND
VCC
EQUATIONS
DESCRIPTION:
LEGEND:
EQUAL
: = REPLACED BY
+
*
OR
AND
F 108
7-58
: +:
: *:
XOR
XNOR
I
(
COMPLEMENT
) THREE-STATE
FUNCTION
TABLE
PIN A
PIN B
PIN C
PIN 0
PIN E
PIN F
PIN G
PIN H
PIN I
PIN J
PIN K
PIN L
PIN M
PIN N
PIN 0
PIN P
PIN Q
PIN R
PIN S
PIN T
PIN U
PIN V
,.
COMMENT
,A
COMMENT
BCD
E
F
G
H
LEGEND
J
K
H
L
L
M
N
0
P
C
X
HIGH
LOW
Q
R
S
T
CLOCK
IRRELEVANT
U
V
z
OFF
F 107
7-59
Octal Counter
SN54/74LS461
Ordering Information
Features/Benefits
• Octal counter for microprogram-counter, OMA controller
and general purpose counting applications
• a bits match byte boundaries
PART NUMBER
PACKAGE
TEMPERATURE
SN54LS461
JS
MIL
SN74LS461
NS, JS
COM
• Bus-structured pinout
• 24-pln Skinny 01P® saves space
• 3-state outputs drive bus lines
• low current PNP inputs reduce loading
• Expandable in a-bit increments
Description
The LS461 is an 8-bit synchronous counter with parallel load,
clear, and hold capability. Two function select inputs (10' 11)
provide one of four operations which occur synchronously on
the rising edge of the clock (CLK).
Logic Symbol
The LOAD operation loads the inputs (DrDo) into the output
register (OrOo)' The CLEAR operation resets the output
register to all LOWs. The HOLD operation holds the previous
value regardless of clock transitions. The INCREMENT operation adds one to the output register when the carry-in input is
TRUE (CI = LOW), otherwise the operation is a HOLD. The
carry-out (CO) is TRUE (CO = LOW) when the output register
(OrOo) is all HIGHs, otherwise FALSE (CO = HIGH).
The output register (OrOo) is enabled when OC is LOW, and
disabled (HI-Z) when OC is HIGH. The output drivers will sink
the 24 mA required for many bus interface standards.
Two or more LS461 octal counters may be cascaded to provide
larger" counters. The operation codes were chosen such that
when 11 is HIGH, 10 may be used to select between LOAD and
INCREMENT as in a program counter (JUMP/INCREMENT).
Function Table
ClK
CI
OC
H
L
L
L
L
L
11
10
X
X
X
1
1
1
1
1
L
L
H
H
H
L
H
L
H
H
X
X
X
X
H
L
DATA
IN
07-0 0 07-0 0 OPERATION
X
X
X
0
X
X
Z
.L
HI-Z
CLEAR
0
HOLD
0
LOAD
HOLD
0
Oplus1 INCREMENT
For supplementary information. see appendix, this section.
.. --
1165 Eaet Arqwa Avenue, Sunnyvale, CA 94088 Tel: (408) 739-3535 TWX: 910-339-t228
II::::!,!/',f: DB
SN54/74LS461
Logic Diagram
Octal Counter
Octal Shift Register
SN54/74LS498
Ordering Information
Features/Benefits
• Octal shift register lor serial to parallel and parallel to serial
applications
• 8 bits match byte
~undaries
PART NUMBER
PACKAGE
TEMPERATURE
SN54LS498
JS
MIL
SN74LS498
!\IS, JS
COM
• Bus-structured pinout
• 24-pln SKINNYOIp'· saves space
• 3-state outputs drive bus lines
• low current PNP Inputs reduce loading
• Expandable in
8~blt
increments
Description
The LS498 is an 8-bit synchronous shift register with parallel
load and hold capability. Two function s~lect inputs (10, 11)
provide one of four operations which occur synchronously on
the riSing edge of the clock (CLK).
Logic Symbol
The LOAD operation loads the inp\Jt (DrDo) into the optpLit
register (OrOo). The HOLD operation holds the previous
value regardless of clock transitions. The SHIFT LEFT operation
shifts the output register, 0, one bit to the left; 00 is replaced
by LlRO. RILO outputs 07'
The SHIFT RIGHT operation shifts the output register, 0, one
bit to the right; 07 is replaced by RILp. LlRO out~uts 00:
The output register (OrOo) is enabled wl1en OC is LOW, and
disabled (HI-Z) when OC is HIGH. the output drivers will sink
the 24 mA required for many bus interface standards.
DATA
DATA
IN
OUT
Two or more LS498 octal shift registers m.!!y be cascaqed to
provide larger shift registers as shown iJ:! Ihe'application section.
07
Function Table
-
14 RILO SHIFT 1/0
OC
elK
11
10 07- 0 0 QrQo OPERATION
H
L
L
L
L
x
X
L
L
H
H
x
!
!
!
!
L
H
L
H
x
X
x
x
D
Z
l
SR(O)
SL(O)
D
For supplementary information, see appendix. this·
GNO
HI-Z
HOLD
SHIFT RIGHT
SHIFT LEFT
LOAD
sec~lQn:,
....,lthlo .1I1In
1165 East Arques Avenue, Sunnyvale, CA 94086 Tel: (408) 739-3535
7.62
TVI)(: 9111-339-9229
. .morl•• 1n.In.LI.
SN54/74LS498
Logic Diagram
Octal Shift Register
7-63
Multifunction Octal Register
SN54/74LS380
Features/Benefits
Ordering Information
• Octal Register for general purposes interfacing applications
PART NUMBER
• 8 bits match byte boundaries
• Bus-structured pinout
PACKAGE
TEMPERATURE
SN54LS380
JS
MIL
SN74LS380
NS, JS
COM
• 24-pln SKINNYOIp'· saves space
• 3-state outputs drive buB lines
• Low current PNP .Inputs reduce. loading
LogiC Symbol
Description
The LS380 is an 8-bit synchronous register with parallel load,
load compliment, preset, clear, and hold capacity. Four control
inputs (0:;, POL, CGi, PR) provide one of fqur operations which
occur synchronously on the rising edge of the clock (CLK). The
LS380 combines the features of the LS374, LS377, LS273 and
LS534 into a single 300 mil wide package.
The LOAD operation loads the inputs (DrDo) into the output
register (OrOo), when POL is HIGH, or loads the compliment
of the inputs when POL is LOW. The CLEAR operation resets
the output register to all LOWs. The PRESET operation presets
the output register to all HIGHs. The HOLD operation holds
the previous value regardless of clock transitions. CLEAR overrides PRESET, PRESET overrides LOAD, and LOAD overrides
HOLD.
DATA
IN
DATA
OUT
The output register (OrOo) is enabled when OC is LOW, and
disabled (HI-Z) when OC is HIGH. The output drivers will sink
the 24 mA required for many bus interface standards.
Function Table
OC
CLK
H
L
L
m
PR
07-00
Q7-QO
X
X
HI-Z
L
CLEAR
H
L
H
H
X
X
X
X
Z
L
H
H
H
D
D
LOAD true
L
H
H
D
5
LOAD comp
LO
POL
X
X
!
!
X
X
L
!
H
X
X
X
X
L
!
L
L
!
L
X
OPERATION
H
PRESET
a
HOLD
For supplementary information, see appendix, this section.
1165 East Arques Avenue, SUnnyvale, CA94086 Tel: (408) 739-3535 TWX: 910-339-9229
7_AA
.."",th,c
Memorle.
W.
SN54/74LS380
Logic Diagram
Octal Register
1 O-Bit Counter
SN54/74LS491
Ordering Information
Features/Benefits
PART NUMBER
• CRT vertical and horizontal liming generation
PACKAGE
TEMPERATURE
• Bus-structured pinout
SN54LS491
JS
MIL
• 24-pln SKINNVOIp'· saves
SN74LS491
NS, JS
COM
SpSce
• 3-s..te outputs drive bus lines
• Low current PNP Inputs reduce loading
Logic Symbol
Description
The ten-bit counter can count up, count down, set, and load 2
LSB's, 2 MSB's and 6 middle bits high or low as a group. All
operations are synchronous with the clock. SET overrides
LOAD, COUNT and HOLD. LOAD overrides COUNT. COUNT
is conditional on CIN, otherwise it holds.
DATA
IN
DATA
OUT
All outputs are enabled when OC is low, otherwise HIGH-Z.
The 24 mA IOL outputs are suitable for driving RAM/PROM
address lines in video graphics systems.
Function Table
OC
CLK
SET
Lo CNT
CIN
UP
D9·DO
X
X
X
Z
HI-Z
X
H
Set all HIGH
H
X
X
X
X
X
L
'1
H
X
X
L
1
L
L
X
X
X
L
1
L
H
H
j(
L
1
L
H
L
L
1
L
H
L
L
1
L
H
L
Q9-QO
OPERATION
X
D
D
LOAD D
x
Q
HOLD
H
X
X
X
Q
HOLD
L
L
X
Q plus 1
Count UP
L
H
X
Q minus 1
Count ON
For supplementary information see appendix this section.
1185 ~t Arqua.Avenue. Sunnyvala•.,CA 94088 Tal: (4De) 739-3535 TWX: 910-339-9229
.,
Maximum clock frequency
el to eOdetay
Clock ,to Q
Clock, to CO
Output enable delay
Output disable, delay.
TYP
COMMERCIAL
MAX
10,5
el = 50 pF
R1 =2000
R2 = 3900
':.
MILITARY,
MIN
.'
MIN
TYP
MAX
35
20'
55
35
50
12,5
35
20
55
35
35
60
35
95
55
55
.:'
UNIT
MHz
35
30
SO
45
45
!'Is
ns
ns
ns
n~
7·75
SN54/74LS498
Absolute Maximum Ratings
Supply voltage vee ................................................................................................ 7V
Input voltage .................................................................................... , ................ 5.5V
Off-state output voltage ........................................................................................... 5.5V
Storage temperature ............................................................................ ,....... _65° to +150°C
Operating Conditions
Vee
MILITARY
MIN TYP MAX
PARAMETER
SYMBOL
Supply voltage
4.5
I low
I High
35
30
25
Width of clock
tsu
Set up time
60
th
Hold time
0
Operating free-air temperature
Te
Operating case temperature
Electrical Characteristics
SYMBOL
VOL
low-level output voltage
VOH
High-level output voltage
0
0
75
Over Operating Conditions
MIN
TYPt MAX UNIT
0.8
Vee
Vee
Vee
Vee
Vee
= MIN
= MAX
- MAX
=
=
=
MAX
MIN
0.8V
2V
II
VI
VI
VI
Vil
VIH
Vee - MIN
Vil = O.BV
VIH = 'J,V
= -1BmA
-1.5
0.25
25
1
= OAV
- 2AV
- 55V
Mil
IOl = 12mA
COM
IOl = 24mA
Mil
IOH = -2mA
COM
IOH = -3.2mA
Vee - MAX
Vil = 0.8V
VIH = 2V
*
°e
°e
2
Supply current
V
ns
-15
125
TEST CONDITIONS
Off-state output current
Output short-circuit current
5.25
ns
low-level input voltage
High-level input voltage
Input clamp voltage
low-level input current
High-level input current
Maximum input current
10lH
lOS
ICC
5
50
-15
-55
PARAMETER
Vil
VIH
VIC
III
IIH
II
lOll
4.75
40
tw
TA
5.5
5
COMMERCIAL
UNIT
MIN TYP MAX
Vee - 5.0V
Vo
= OAV
Vo
= 2AV
Vo
= OV
0.5
2.4
/lA
mA
V
V
-100
-30
Vee - MAX
V
V
V
mA
120
/lA
100
/lA
-130
mA
180
mA
* No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second
t All typical values are at Vee = SV, T A = 2S' C
Switching Characteristics
t ..... 8BOL
PARAMETER
fMAX
tpo
tpo
tpo
Maximum clock frequency
tplX
tpXl
7-76
10, 11 to LlRO, RllO
Clock to Q
Clock to LlRO, RllO
Output enable delay
Output disable delay
Over Operating Conditions
TEST CONDITIONS
(See Test Load)
MILITARY
MIt-! TYP
COMMERCIAL
MAX
10.5
el = 50 pF
R1 = 2000
R2 = 3900
MIN
TYP
MAX
12.5
35
20
55
35
35
60
35
95
55
55
35
20
55
50
30
80
35
35
45
45
UNIT
MHz
ns
ns
ns
ns
ns
SN54/74LS380
Absolute Maximum Ratings
Supply voltage vee ................................................................................................ 7V
Input voltage ....................................................................................... , ............. 5.5V
Off~state output voltage ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5V
Storage temperature... .......... ........... ......... .. .. ........ .................................. ..... _65° to +l50o e
Operating Conditions
Vee
MILITARY
MIN TYP MAX
PARAMETER
SYMBOL
Supply voltage
4.5
5.5
4.75
I
High
40
40
I
low
35
35
tw
Width of clock
tsu
Set uptime
60
th
Hold time
0
TA
Operating free-air temperature
-55
Te
Operating case temperature
Electrical Characteri.stics
5
COMMERCIAL
UNIT
MIN TYP MAX
5
5.25
ns
50
-15
0
V
ns
-15
0
75
125
°e
°e
Over Operating Conditions
",
SyMBOL
PARAMETER
V il
low-I.evel input voltage
VIH
High-level input voltage
Input clamp voltage
low-level input current
Vie
III
IIH
II
High-level input current
Val
Low-level output voltage
Maximum input current
t£ST CONDITIONS
IOZl
Vec~
MIN
II
= -18mA
= O.4V
Vee = MAX
Vee ~ MAX
VI
VI - 2.4V
Vee = MAX
Vee - MIN
VIL = 0.8V
VI
= 2V
= MIN
= 0.8V
= 2V
High-level output voltage
Vil
Off-state output current
VIH
Vee - MAX
Vil = 0.8V
lOS
Output short-circuit current*
VIH = 2V
Vee - 5.0V
Ice
Supply current
Vee
10ZH
MIN
TyptMAX
.
...
= 5.5V
Mil
10l
eOM
10l
Mil
10H
eOM
10H
= 12mA
= 24mA
= -2mA
=-3.2mA
Va
= O.4V
= 2.4V
Va
= OV
Va
V
-1.5
V
V
0.25
mA
25
1
IJ.A
mA
0.5
V
2.4
V
-30
=MAX
UNIT
0.8
2
VIH
Vee
VOH
',".
120
-100
p.A
100
p.A
-130
mA
180.
mA
* No more than one output should be shorted at a time and duration of the short-Circuit should not exceed one second.
t All typical values are at Vee =5V. T A =25' C
Switching Characteristics
SYMBOL
PARAMETER
fMAX
Maximum· clock frequency
tpo
elock to Q
tpzx
Output enable delay
tpxz
Output disable .delay
Over Operating cond'mcms
TEST CONDITIONS
(See Teit'Loadl)
el
Rl
R2
= 50.pF
= 2000
= 3900
MILITARY
MIN TYP MAX
COMMERCIAL
UNIT
MIN TYP ~AX
10.5
12.5
MHz
20
35
2ri'
30
ns
35
55
55
~
35
45
'ns
45
ns
35
SN54/74LS491
Absolute Maximum Ratings
Supply voltage V CC .......................................... ..................................................... ·7V
Input voltage .: ........ , ..........................................................•.................. '.' .............. 5.5V
Off~state output voltage .................•............•...........................................•................. 5.5V
Storage temperatUre................ ... ...... .. . .... ........ ........... ....... ... ......... ... . ....... . ... _65· to +)50·C
Operating Conditions
MILITARY
MIN TYP MAX
PARAMETER
SYMBOL
Supply voltage
VCC
4.5
I High
I Low
35
35
tsu
Set up time
60
th
Hold time
0
Operating free-air temperature
Operating case temperature
Electrical Characteristics
VIL .'
Low-level input voltage
VIH
VIC.
IlL
IIH
II
High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current
VOL
Low-level output voltage
VOH
High-level output voltage
10ZL
Output short-circuit current
Supply current
5.25
ns
-15
75
0
·C
·C
Over Operating Conditions
MIN
TYPt MAX UNIT
0.8
-1.5
0.25
V
V
V
mA
25
1
JlA
mA
0.5
V
2
VCC ~ MIN
VCC ~ MAX
VCC - MAX
VCC - MAX
VCC = MIN
VIL = 0.8V
VIH = 2V
II = -18mA
VI - O.4V
VI = 2.4V
VI = 5.5V
VCC - MIN
VIL = 0.8V
VIH = 2V
MIL
10L = 12mA
COM
10L = 24m A
MIL
10H = -2mA
COM
10H = -3.2mA
VCC = MAX
VIL = 0.8V
*
V
ns
125
= 2V
ICC
0
TEST CONDITIONS
Off-state output current
10ZH
lOS
5
50
-15
-55
PARAMETER
SYMBOL
4.75
40
Width of clOCk
TC
5.5
40
tw
TA
5
COMMERCIAL
UNIT
MIN TYP MAX
VIH
VCC = 5.0V
Vo
= O.4V
Vo
= 2.4V
Vo
- OV
2.4
V
-30
VCC - MAX
120
-100
100
JlA
-130
mA
mA
180
JlA
* No more than. one output should ~e shorted at a time and duration of the short-circuit sho~.ld not exceed one second.
t All typical values are at VCC = 5V. T A
= 25· C:
Switching Characteristics
SYMBOL "
,PARAMETER
fMAX
Maximum clock frequency
tpo
Cloekto Q
tpzx
Output enable delay
tpxz
Output disable delay
7-78
Over Operating Conditions
TEST CONDITIONS
(See T.est Load,)
CL = 50pF
R1 = 2000
R2
= 3900
MILITARY
MIN TYP MAX
COMMERCIAL
UNIT
.MIN TYP MAX
10.5
12.5
MHz
20
35
20
30
ns
35
55
35
45
ns
35
55
35
45
ns
SN54/74LS450
Absolute Maximum Ratings
Supply voltage V cc ............................. ;................................................................... 7V
Input voltage ................................................................................. , ...•.........•....... 5.5V
Off-state output voltage ........................................................... : .................. ; . . • . . . . . . . .. 5:5V
Storage. temperature' ...........................•......................... : ............. , ............. ;... _65° to +150·(::
Operating Conditions
VCC
Supply voltage
TA
Operating free-air temperature
TC
Operating case temperature
VIL
VIH
VIC
IlL
I.IH
II
MIN NOM MAX
4.75
,5
0
UNIT
5.25
V
75
·C
·e
125
Over Operajing Conditions
.
h,
MIN
TYPt MAX UNIT
.;,
V
O.S
2
v:
VI "0.4V
VI- 2.4V
0.25
mA
25
VCC - MAX
Vec=MIN
VIL =O.SV
VIH = 2V'
VI - 5.5V
'1
Jl.A
mAo
Vce - MIN
VIL = .O.SV
VIH = 2V
MIL
VCC = MAX
VCC- MAX
Output short-clrcuit. current '"
Supply current
V
.,.1.5
II
Vcc - MIN
Maximum input current
High-level output voltage
5.5
TEST CONDITIONS
High-level input voltage
Input clamp voltage
Low-Ievelinpu! current
High~level input current
VOH
lOS
5
1-55
PARAMETER
Low-level output voltage
COMMERCIAL
NOM MAX
Low-level input voltage
VOL
ICC
MIN
4.5
Electrical Characteristics
SYMBOL.
MILITARY
PARAMETER
SYMBOL
VCC =.5.0V
.~
-lSmA
0.5
IOL= SmA
...
V
10H = -2mA
II
2.4
COM
. 10H= -3.2mA.
.
Vo
....30
- OV
VCC - .MAX
60
-130
100
rnA
rnA
* No more than one output ·should be shorted at a time and duration of the 'short-circuit should not exceed one second.
tAli typical values are at VCC =SV, TA = 2S"C
SwitchlngCha.racferistic8
,
SYMBOL
tpo
PARAMETER
Any inplJtto Y or W
over Operatil,g,CondIUons
...
TEST CONDITiONS
(See Test Load?
CL = 50 pF
Bl=5600
R2 = 1.1kO
MILITARY
MIN
I····
COMMERCIAL
TYP
MAX
25
45
MIN
TYP
MAX
25 .. ,40
UNIT
ns .;.
7;.79
SN54174LS451
Absolute Maximum Ratings
Supply voltage vee ............ ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7V
Input voltage ..................................................................................................... 5.5V
Off-state output voltage ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 5.5V
Storage temperature.... . .. ..... ... .. .. .. .... .... ... . .. ..... . . . . ........... . . ... . .. .. .. .. .. .. .. . ..... ... _65° to +150 0 e
Operating Conditions
SYMBOL
MILITARY
PARAMETER
MIN
Vee
Supply voltage
4.5
TA
Operating free-air temperature
-55
Te
Operating case temperature
VOL
Low-level output voltage
VOH
High-level output voltage
TEST CONDITIONS
Output short-circuit current
Supply current
* No more than
UNIT
5.25
V
75
°e
°e
MIN
TYPt MAX
O.B
Vee - MIN
Vee = MAX
Vee = MAX
Vee - MAX
Vee - MIN
VIL = O.BV
VIH = 2V
*
II - -1BmA
VI = O.4V
VI = 2.4V
VI = 5.5V
-15
0.25
25
1
10L
= MIN
VIL = O.BV
VIH = 2V
Vee = 5.0V
Vee - MAX
MIL
10H
COM
10H
Vo
= BmA
0.5
= -2mA
=-3.2mA
2.4
- OV
-30
UNIT
V
V
V
mA
JlA
mA
V
V
-130
60
100
mA
mA
one output should be shorted at a time and duration of the short-circu'it should not exceed one second.
t All typical values are at V CC ~ 5V. T A
~ 25°C
Switching Characteristics
Any input to Y
Over Operating Conditions
TEST CONDITIONS
PARAMETER
,
7-80
5
2
Vee
tpo
4.75
0
Low-level input voltage
High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current
SYMBOL
5.5
NOM MAX
Over Operating Conditions
PARAMETER
VIL
VIH
Vie
IlL
IIH
II
lOS
ICC
5
MIN
125
Electrical Characteristics
SYMBOL
COMMERCIAL
NOM MAX
(See Test Load)
eL
R1
R2
=50 pF
=5600
= 1.1kD
MILITARY
MIN
COMMERCIAL
TYP
MAX
25
45
MIN
TYP
MAX
25
40
UNIT
ns
SN541,74LS453
Absolute Maximum Ratings
Supply voltage vee ................................................................................................ 7V
Input voltage ..................................................................................................... 5.5V
Off-state output voltage ........................................................................................... 5.5V
Storage temperature ............................................................................ ,~ ....... _65° to +150 0 e
Operating Conditions
SYMBOL
MILITARY
PARAMETER
MIN
Vee
Supply voltage
4.5
TA
Operating free-air temperature
-55
Te
Operating case temperature
Electrical Characteristics
SYMBOL
VIL
VIH
5.5
4.75
NOM MAX
5
0
VIC
IlL
IIH
II
VOL
Low-level output voltage
VOH
High-level output voltage
5.25
V
75
°e
Over Operating Conditions
TEST CONDITIONS
MIN
TYPt MAX UNIT
O.B
2
Vee - MIN
Vee = MAX
Vee = MAX
Vee - MAX
Vee = MIN
VIL = O.BV
VIH = 2V
Vee
Output short-circuit current
Supply current
*
UNIT
°e
volt~ge
High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current
lOS
lee
5
MIN
125
PARAMETER
Low-level input
COMMERCIAL
NOM MAX
II - -1BmA
VI - O.4V
VI " 2.4V
VI - 5.5V
= MIN
VII. = O.BV
VIH = 2V
Vee - 5.0V
MAX
Vee
10L
= BmA
MIL
10H
2.4
eOM
10H
= -2mA
=-3.2mA
- OV
-30
Vo
V
V
V
rnA
-1.5
0.25
25
1
/loA
mA
0.5
V
V
-130
60
100
mA
mA
* No more than one output should be shorted at a time and duration of the short~circuit should not exceed one second.
t AlltypicalvaluesareatV CC =5V.T A = 25°C
.
Switching Characteristics
SYMBOL
tpD
PARAMETER
Any input to Y
Over Operating Conditions
TEST CONDITIONS
(See Test Load)
CL = 50 pF
R1 = 5600
R2 = 1.1kO
MILITARY
MIN
COMMERCIAL
TYP
MAX
25
45
MIN
TYP
MAX
25
40
UNIT
ns
7 ...81
7·82
. Representatives/Dlstributors
1:1
Monolithic Memories Area and Regional Sales Managers and FAEs
California
Cupertino
George Anderl
(408) 996-1477
(714) 556-1216
PaSadena
Wayne Caraway
Dick Jones. FAE
Minnesota
Edina
(312) 932-1940
Naperville
Huntington Beach
Dick Siemiatkowski
Illinois
Lombard
(714) 556-1216
Sal Graziano
Bernard Brafman. FAE (714) 556-1216
(312) 961-9200
(617) 256-3573
New Jersey
Sussex
Mike Wier
MassachuseHs
Chelmsford
Jack Abbott
Irvine
(617) 655-7070
Reading
Stan Karandanis
Florida
Longwood
(617) 944-5535
Newton Centre
Jim McGrath
(30S) 830-7867
Mike Volpigno. FAE
(612) 922-2260
(513) 439-D470
Bill Bartley
Framingham
Russ French
AlexSherbanenko
Ohio
Dayton
(201) 875-9430
Texas
Gariand
Bob Rainwater
(214) 233-5833
Dallas
(617) 332-4840
Brad Mitchell. FAE
(214) 233-5833
Monolithic Memories Representatives
U.S.A.
Kansas
Olathe
Alabama
Huntsville
(205) 881-9270
REP. Inc.
Scottsdale
Summit Sales
(602) 998-4850
(213) 870:9191
Irvine":'
. Bestronics
(714) 979-9910
¢upertlno
(408) 996-9889
"
Littlefield & Smith
(714) 455-005S
···Colorado
Wl1IIatridge
, '. Waugam~n A~ociates (303) 423-1020
Connecticut
Norih Hailen
Comp .Rep Associates
(203) 239-9762
Florida
Altemonte Springs
c>yne;-A-Mark . .:.
. (3QS) 831-2697
Clearwater
Dyne-A-Mark
(813) 441-4702
Fort Lauderdale
Dyne-A-Mark
(305) 771-6501
Palm Bay
Dyne-A-Mark
(305) 727-0192
REP/Inc.
(404) 938-4358
Leslie M. DeVoe Co.
Technical Sales. Inc.
(314) 394-7271
L:Mar Associates
L-Mar Associates
(201) 692-()200
(809) 832-9529
(615) 475-4105
Texas
Austin
West and Associates
(512) 441-6973
(716) 544-8000
(315) 43H77~
(214) 661-9400
Houston
(713) 777-4108
Utah
s.1t Lake City
(801) 467-4263
Virginia
Reston
Monolithic Sales
North Carolina
Raleigh
REP, Inc.
REP; Inc.
Waugaman ASsociates
New York
RoChester
Syracuse
Comp Rep Associates
West and Associates
New Je~y
Teall8ck
R.T. 'Reid Associ!ltes
(215) 885-5106
Tennessee
Jefferson City
wesi and Associates
(612) 941-9790
Missouri
Ballwin'
Rush and West
CMS Marketing
Puerto Rico
Mayagues
Dallas
Mlnne!lota
Edina
(703) 620-9558
Washington
Belle~
Northwest Marketing
Wisconsin.
BroOkfield
(206) 455-5846
"\''.,
Surney'
(414) 784-6641
(919) 85h-3001'
Makin Associates
(513) 871-2424
Columbus
(614) 459-2423
West & Associates
cantec
(918) 445-7429
(317) 842-3245
(319) 393-1845
CANADA
.Ontario
Brampton
Oklahoma
Tulsa
Iowa
Cedar Rapids
, ..'
(313) 499-0188
(312) 991-6500
Indiana
Indianapolis
8-2
Michigan .
Grosse Point
Makin Associates
illinois
Roiling Meadows
Sumer
(617) 329-3454
Pennsylvania
Oreland
Ohio
Cincinnati
Georgia
Tucker
o Sales
Comp Rep Associates
Greiner Associates
ihresum Associates
S &
(301) 296-2444
.:Westwood
Bestronics
'
M6nolithicSaies
MassachuseHs
'California
CulVer City
","
(913) 764-2700
Maryland
Baltimore
~rizona
$anDiego
Rush and West
Cantec
Oregon
Portland
North West Marketing
(416) 791-5922
OttaYia
(613) 725-3704
Quebec
Dollard Des Ormeaux
(503) 297-2581
Cantec
(514) 683-6131
Monolithic Memories Franchised Distributors
U.S.A.
M~~:,"oc:.
Alabama
Huntsville
Hall-fI.1ark Electronics
(205) 837-8700
A~ona
Kierulff Electronics
(602) 243-4101
Tempe
Marshall Electronics Group
Bell Industries
Kierulff Electronics
lionex
(617) 272-9400
(617) 933-£130
(213) 999-5001
Michigan
Ann Arbor
Arrow Electronics
(213) 686-{)141
Farmlngton
Diplomat/Northland
Irvine
Marshall Electronics Group
(714) 556-£400
Grand Rapids
RS Electronics
Los Angel..
Kierulff Electronics
Newport Beaq!I
Arrow Electronics
(213) 725-0325
Kalamazoo
RS Electronics
(714) 851-8961
Livonia
(415) 968-£292
Minnesota
RS Electronics
Palo Alto
Kierulff Electronics
SanD~
Anthem lectronics
Kierulff Electronics
Arrow Electronics
(714) 279-5200
(714) 278-2112
(714) 565-4800
San Jose
Anthem Electronics
(408) 946-8000
Sunnyvale
Arrow Electronics
DiplomatiWestland
(408) 745-8800
(408) 734-1900
TusHn
Anthem Electronics
Kierulff Electronics
(714) 730-8000
(714) 731-5711
Chatsworth
Anthem Electronics
Arrow Electronics
(213) 700-1000
(213) 701-7500·
Colonldo
Den_
~~~~~1t'lnectronics
=~~K:II Electronics
(303) 758-2100
(303) 371-£500
Bond Electronics
(616) 241-3483
(616) 381-5470
(313) 525-1155
Hall-Mark Electronics
St. louis
Arrow Electronics
(203) 852-1001
Arrow Electronics
Marshall Electronics Group
(603) 668-8968
(201) 575-£750
(201) 227-7960
Florida
Clearwater
Arrow Electronics
(201) 797-5900
Fort Lauderdale
Arrow Electronics
Hall-Mark Electronics
(813) 443-4514
(305) 776-7790
(305) 971-9280
Orlando
Hall-Mark Electronics
(305) 855-4020
~~ue1:'lronics
Arrow 1:lectroniCS
New York
Buffalo
Summit Distributors
Arrow Electronics
(305) 725-1480
Kierul!! Electronics
Georgia
Norcrosa
Diplomat Electronics
Arrow Electronics '"
Electronics
(813) 576-1966
l404)
449-4133
404) 449-8252
(404) 447-8000
(716) 884-3450
(1112) 640-0200
Melville
(312) 893-9420
LlverpoCil
Indiana
Indlenapolls
Advent Electronics
Arrow Electronics
Iowa
Cedar Rapids
Advent Electronics
(317) 872-4910
(317) 243c9353
(319) 363-{)221
Diplomat Electronics
Arrow Electronics
Hall-Mark Electronics
Winston/Salem
Arrow Electronics
Ohio
Solon
Centerville
(913) 688-4747
(716) 275-{)300
(716) 334-8110
(516) 273-2900
(516) 273-1660
(516) 231-1000
Arrow Electronics
(214) 388-7500
(214) 343-5000
Hell-Mark Electronics
Quality Components
(113) 781-6100
(713) 772-7100
(713) 4914100
Century/Bell Electronics
Kierulff Electronics
(801) 972-6969
(801) 973-8813
Washington
Bellevue
Almac/Stroum Electronics
Arrow Electronics
(206) 643-9992
(206) 643-4800
Kierulff Electronics
Arrow Elettronics
Hall-Mark Electronics
(206) 575-4420
'(414) 764-8800
(414) 761..3Q00
Wauk..ha
(414) 764-8160
Alberta
Calgary
,
~403)
403)
2.59-6408
230-1422
Edmonton
(403) 463-3014
British Columbia
Vancouver
RAE Electronics
Zentronics Limited
Future Electronics
(604) 291-8866
(604) 688-2533
(604) 436-5545
Manitoba
Winnipeg
Zentronics Limited
(204) 775c8881
Ontario
Brampton
Zentronics Limited
(4·16) 451-9600
(516) 454-£400
Zentronics Limited
Future Electronics
(6131' 238-£411
(613) 820-8313
(315)652-1000
Toronto
North Carolina
Raleigh
Arrow Electronics
Kansas
Hall-Mark Electronics
Roch..ter
Lionex
Arrow
Schaumburg
Arrow< Electronics'
(516) 694-8800
(312) 860-3800
Elk Grove Village
Kierulff Electronics
(315) 437-0300
~~=~~~rronics
Arrow Electronics"
(512) 258-8848
(512) 835-{)22O
Stefford
Arrow Electronics
Zentronics Limited
(607) 754-1570
Summit Distributors
Houston
Future Electronics
Zentronics Limited
Marshall Electronics
~~~=u~mponents
illinois
aensanville
Hall-Mark Electronics
Add Electronics
DallaS
(214) 387-4949
CANADA
(505) 292-2700
(505) 243-4566
Endwell
St. Petersburg
Quality Components
Kierulff Electronics
E. Syracuse
Palm Bay
Texas
Addison
(609) 424-0880
New Mexico
Diplomat/Southland
(215) 674-4000
(412) 856-7000
Arrow Electronics
Wisconsin
Oak Creek
Cherry Hili
Hallmark
Pioneer/Delaware Valley
Monroeville
(215) 627-1920
Saddlebrook .'
(918) 835-8458
(918) 864-8812
(918) 587-9123
(503) 641c9150
Kierulff Electronics
Tukwila
(609) 235.1900
(614) 891-4555
p-.:'on,:~:::nia
(201) 765-1830
Moorestown
(203) 265-7741
(203) 265-3822
Oregon
Portland
Utah
Salt Lake CIty
Totowa
Diplomat/IPC
Hall-Mark Electronics
Quality Components
Radio, Inc.
Arrow Electronics
Hall-Mark Electronics
(314) 567-£888
(513) 236-8088
Oklahoma
Tulsa
(612) 830-1800
(6)2) 941-7500
N~:rf~:ey
Lionex
Marshall Electronics
Welterville
(612) 884-9056
(314) 291-5350
(216) 473-2907
Dayton
Hall-Mark Electronics
Quality Components
New Hampshire
Manchester
Arrow Electronics
Hall-Mark Electronics
AusUn
Earth City
Mt. Laurel
Waillngtqnf
Arrow Electronics
Marshall Electronics Group
(313) 477-3200
.Missouri
(303) 424-1985
Connecticut
E. Nol'Wlltk
(313) 971-8220
Edina
Arrow Electronics
Kierul!!. Electronics Co.
Kierulff Electronics
Arrow Electronics
Kierul!! Electronics
(617) 667-8331
Wobum
Arrow Electronics
Burlington
Ohio (continued)
Clevetand
Hall-Mark Electronics
(602) 624-9968
EIMonte
Marshall Electronics Group
(301) 948-0710
(602) 968-£181
(602) 968-7800
Callfomla
Cenoga Park
Marshall Electronics Group
Massachusetts
Billerica
(301) 247-5200
(301) 796-9300
Kierulff Electronics
Tuecon
Lenexa
Gaithersburg
Pioneer Washington
Phoenix
Hall~Mark
Arrow Electronics
Hallmark Electronics
Ottawa
Future Electronics
(416) 663-5563
Watel100
(919) 832-4465
Zentronics Limited
(919) 725c8711
NOVII Scotia
Dartmo.uth
(216) 248-3990
Quebec
Montreal
(51~) 435-5563
ZentrQliiCs Limited
Future Electronics
Zentronlcs Limited
(519) 884-5700
(902) 46a-6411
(514) 6~"7710
(514) 735-5361
8-3
m
•
Monolithic Memories Overseas Representatives and Distributors
AUSTRIA
Ing. Erl1$tSteiner
Geylinggasse 16
A 1130 Wien
Phone: 22~822674
Telex: 135026
AUSTRALIA
R&D Electronics Pty Ltd.
257 Burwood Hwy.
Burwood, Vi.c. 3125
Phone: 3-288-8232
Telex: .M33288
R&D Electronics Pty Ltd.
133 Alexander SI.
Crows Nest-2065
Phone: 2-439-5488
Telex: AA25468
BELGIUM
Ritro Electronics, B.V.
Plantin & Moretuslei 172
B 2000 Antwerp
Phone: 31-353272
Telex: 33637
DENMARK
vaa APS
Kokkedal Industripark 42A
DK-2980 Kokkedal
Phone: 244888
Telex: 41198
ENGLAND
Monolithic Memories Ltd.
Lynwood House
1 Camp Road
Farnborough
Hampshire
GU146EN
Phone: (0252) 517431
Telex: 858051 MONO UK G
Memory Devices Ltd.
Central Avenue
East MOlesey
KT80SN
Phone: 1-9411066
Telex: 929962
Macro Marketing Ltd.
396 Bath Road
Slough, Berkshire
Phone: 628663011
Telex: 847083
Dice. Only:
Hy~Comp
Ltd.
7 Shield Road
Ashford,
Middlesex TW15 IAV
Phone: (07842) 46273
TeleX: 923802
FINLAND
Telereas O.Y.
P.O .. Sox 2
01511 Vantaa 51
Phone: 0-821655
Telex: 12111
FRANCE
Mon9lithic Memories France S.A.R.L.
Silic 463
94613 Rungis Cedex
Phone: 1-6874500
Telex: 202146
8·4
FRANCE (continued)
Alfatronic S.A.R.L.
La Tour d'Asnieres 4
Avenue Laurent Cely
F 92606 Asnieres
Phone: 1-7914444
Telex: 612790
Generlm S.A.R.L.,
Zone d'Activities de Courtaboeuf
Avenue de la Baltique
P.O. Box 88
91943 Les Ulis Cedex
Phone: 1-9077878
Telex: 691700
GERMANY
Monolithic Memories, GmbH
Mauerkircherstr 4
8000 Munich 80
Phone: 89-984961
Telex: 524385
Fax: 89-983162
Astronic GmbH
Winzerstrasse 47D
8000 Munich 40
Phone: 304011
Telex: 5216187
Dr. Dohrenberg Vertriess GmbH
Bayreuther Strabe 3
1000 Berlin 30
Phone: 030-2138043-45
Telex: 0184860
Elcowa GmbH
Strabe Der Republik 17-19
Postfach 129409
6200 Wiesbaden
Phone: 06121-65005
Telex: 04186202
Electronic 2000 Vertriebs GmbH
Neumarkter Strasse 75
8000 Munich 80
Phone: 89-434061
Telex: 522561
ITALY
Comprel S.R.L.
Viale Romagna 1
20092 Cinisello Balsamo/Milano
Phone: 2-6120841
Telex: 332484
JAPAN
Monolithic Memories Japan KK
4-5-15, Sendagaya
Shibuya-Ku
Tokyo 151
Phone: 3-4039061
Telex: 781-26364
NORWAY
Henaco AlS
P.O. Box 248
Okern Torgvei 1~
Oslo 5
Phone: 2-157550
Telex: 16716
SOUTH AFRICA
Radiokom Ltd.
P.O. Box 56310
Pinegowrie 2123
Phone: 789-1400
Telex: 424822
SOUTH AMERICA
Intectra
2349 Charleston Rd.
Mountain View, CA 94043
Phone: (415) 967-8818
Telex: 910-345545
SPAIN
Sagitron
C/Castello, 25, 2
Madrid 1
Phone: 88-011-27-402-6085
Telex: 43819
Nordelektronik GmbH KG
Harksheiderweg 238-240
2085 Quickborn
Phone: 04106-4031
Telex: 214299
SWEDEN
NAXAB
Box 4115
S 17104 Solna
Phone: 8-985140
Telex: 17912
Positron Bauelemente
Vertriebs GmbH
Benzstrasse 1
Postfach 1140
7016 Gerlingen-Stuttgart
Phone: 07 156-23051
Telex: 7245266
SWITZERLAND
Industrade AG
Gemsenstrasse 2
CH 8021 Zurich
Phone: 01-3632230
Telex: 56788
INDIA
Components & Systems Ltd.
3481, Najaji Subhash Marg.
Daryaganj, New Delhi-110002
Phone: 011-27388
ISRAEL
TELSYS Ltd.
12 Kehilat Venetsia St.
Tel Aviv
Phone: 972482126
Telex: 032392
TAIWAN
Multitech International Corp.
2nd Floor
977 Min Shene East Road
Taipei, Taiwan R.O.C.
Phone: 8-011-86
Telex: 23756 or 19162
24-Pin PAL Logic Symbols
PAL14L8
PAL12L10
I
PAL20L2
PAL20L10
PAL20~O
PAL16L6
PAL18L4
PAL20C1
PAL20X8
PAL20X4
ItIIonollthlc
W MemorIes
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:07 12:30:18-08:00 Modify Date : 2017:08:07 14:37:28-07:00 Metadata Date : 2017:08:07 14:37:28-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:92f04c3b-248a-f647-b513-66102e75f2dd Instance ID : uuid:645c4e12-c502-7440-8945-951dc9cc40ac Page Layout : SinglePage Page Mode : UseNone Page Count : 680EXIF Metadata provided by EXIF.tools