1981_Mostek_Z80_Microcomputer_Data_Book 1981 Mostek Z80 Microcomputer Data Book
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1981
Z80 MICROCOMPUTER
DATA BOOK
Copyright © 1981 Mostek Corporation (All rights reserved)
Trade Marks Registered ®
Mostek reserves the right to make changes in specifications at any time and without notice. The information furnished by
Mostek in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Mostek for its use;
nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Mostek.
The "PRELIMINARY" designation on a Mostek data sheet indicates that the product is not characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. Mostek Corporation
or an authorized sales representative should be consulted for current information before using this product. No responsibility
is assumed by Mostek for its use; nor for any infringements of patents and trademarks or other rights of third parties resulting
from its use. No license is granted under any patents, patent rights, or trademarks of Mostek. Mostek reserves the right to
make changes in specifications at any time and without notice.
PRINTED IN USA February 1981
1981 Z80 MICROCOMPUTER DATA BOOK
Table
of Contents
1981 Z80 MICROCOMPUTER DATA BOOK
I - Table of Contents
Functional Index .......................................................................... I-i
II - General Information
Package Descriptions .................................................................... II-iii
Introduction to Mostek ................................................................... II-vii
U.S. and Canadian Sales Offices ........................................................... II-xi
U.S. and Canadian Representatives ........................................................ II-xii
U.S. and Canadian Distributors ........................................................... II-xiii
International Marketing Offices ............................................................ II-xv
III - laO Family Technical Manuals
Central Processing Unit (MK3880) ......................................................... 111-1
Parallel I/O Controller (MK3881) ......................................................... 111-91
Counter Timer Circuit (MK3882) ......................................................... 111-127
Serial I/O (MK3884/5/7) .............................................................. 111-163
l80 Combo Circuit (MK3886) ........................................................... 111-235
IV - laO Family Data Sheets
Direct Memory Access Controller (MK3883) ................................................. IV-1
Serial Input/Output Controller (MK3884) .................................................. IV-19
Combo Chip (MK3886) .................................................................. IV-35
V - laO Development Equipment
MATRIX DS ............................................................................ V-1
Keyboard Display Unit CRT ............................................................... V-11
LinePrinter(LP) ........................................................................ V-15
PROM Programmer (PPG 8/16) .......................................................... V-19
Ansi Basic Software Interpreter (MK78157) ................................................ V-23
Fortran IV Compiler (MK78158) .......................................................... V-27
FLP80 DOS (MK78142, MK77962) ....................................................... V-29
Fortran IV Cross Assembler (XFOR-80) .................................................... V-33
FLP80 DOS Software Library (LIB 80 V1) .................................................. V-35
MACRO 80 (MK78165) ................................................................. V-37
AIM l80BE (MK78205) ................................................................. V-39
VI - laO Microcomputer Application Notes
Serial Communication Capability to the 8086/8088 Family Using the l80 SIO ................... VI-1
l80 Interfacing Techniques for Dynamic RAM ............................................... VI-7
Applying the l80 SIO in Asynchronous Data Communications ................................ VI-23
Use of the MK3805 Clock/RAM .......................................................... VI-29
Using the MK3807 VCU in a Microprocessor Environment ................................... VI-87
VII - laO Microcomputer Peripherals
CMOS Microcomputer Clock/RAM (MK3805) .............................................. VII-1
Programmable CRT Video Control Unit VCU (MK3807) ....................................... VII-9
STI-l80 Version (MK3801 ) .............................................................. VII-21
MK50808 ............................................................................ VII-25
J.LP-Compatible A/D Converters (MK5168(N)-1) ............................................ VII-33
MK50816 ............................................................................ VIIA1
VIII - laO Military/Hi-Rei
Introduction ............................................................................ VIII-3
Applications Guide ..................................................................... VIII-5
MKB Military Products Listing .......................•.................................... VIII-6
MKI Industrial Products Listing ..................... ! . . • . . . . . . . • • • • • • • • • • • . • • • • • • • . • . • . . . • VIII-7
MKB 3880 Data Sheet ........................•......................................... VIII-9
I-i
1981 Z80 MICROCOMPUTER DATA BOOK
General
Information
ORDERING INFORMATION
Factory orders for parts described in this book should include a four-part number as explained below:
Example: M
87 ¥-~
~1. Dash Number
2. Package
' - - - - - - - - - - 3 . Device Number
' - - - - - - - - - - - 4 . Mostek Prefix
1.
Dash Number
One or two numerical characters defining specific device performance characteristic.
2.
Package
P
J
N
R
K
T
E
3.
Gold side-brazed ceramic DIP
CER-DIP
Epoxy DIP (Plastic)
P-PROM
Tin side-brazed ceramic DIP
Ceramic DIP with transparent lid
Ceramic lead less chip carrier
Device number
1XXX or
2XXX or
3XXX or
38XX
4XXX or
5XXX or
7XXX or
4.
1XXXX
2XXXX
3XXXX
4XXXX
5XXXX
7XXXX
Shift Register, ROM
ROM, EPROM
ROM, EPROM
Microcomputer Components
RAM
Telecommunication and Industrial
Microcomputer Systems
Mostek Prefix
MK-Standard Prefix
MKB-1oo% 883B screening, with final electrical test at low, room and high-rated temperatures.
II-i
I\-ii
MOSTEI{.
MICROCOMPUTER PRODUCTS
Package Descriptions
Ceramic Dual-In-Line Package (P)
40 Pin
~!:~[]"
"."~"no.,", >o,
IOEIIITlflCATIONOF P""'1
llJ'JiWITi
,578
~"
-"
Plastic Dual-In-Line Package (N)
40 Pin
NOTE: Overall length includes .005 flash on either end of package
Cerdip Hermetic Packaging (J)
40 Pin
II-iii
'
aDJ]
Ceramic Dual-In-Line Package(P)
28 Pin
--.
,
I
.
u ••,.".
..
_I-do"
~~-=L~'
I~ UU UUI , li!Jt! ,~, ...,.~
JI
.o&CI!.o1,
~
..~,I;;;-Il
I-----,JEQUALapACES@1OO----!
t="""'=:j
1
f
I:::""~
iii
Cerdip Hermetic Packaging (J)
28 Pin
.0211
r--
no:!:..o16-1
-r~~'."'~
:LilrYr
Ldb
uvt~J I~\
J,,~~ ~ ~. ~".o10+.003~\-. "J
2PLCS,
13 EQUAlSPACESAT.l00 EACH
Plastic Dual-In-Line Package (N)
28 Pin
~~IC DUAL·IN UltE PACKAGINOI"I
OOI~
=
~
.'v'jvl.o::o:.
'.'ODMAX.~
~~.
,L.'21:!:.o.a.--\
II-iv
Cerdip Hermetic Package (J)
24 Pin
Leadless Hermetic Chip Carrier (E)
18 Pin
i·m""j
+~-D
Leadless Hermetic Chip Carrier (E)
18 Pin
II-v
Dual-In-Line Double Density Ceramic Package (D)
18 Pin
Ceramic Dual-In-Line Package (P)
16 Pin
Cerdip Hermetic Package (J)
16 Pin
lI·vi
Mostek - Technology For Today And Tomorrow
system.
In design, production and testing, the
Mostek goal is meeting specifications the
first time on every product. This goal requires
strict discipline from the company and from
its individual employees. Discipline, coupled
with very personal pride, has enabled
Mostek to build in quality at every level of
production.
TECHNOLOGY
From its beginning, Mostek has been an
innovator. From the developments of the 1K
dynamic RAM and the single-chip calculator
in 1970 to the current 64K dynamic RAM,
Mostek technological breakthroughs have
proved the benefits and cost-effectiveness of
metal oxide semiconductors. Today, Mostek
represents one of the industry's most
productive bases of MOS/LSI technology,
including Direct-Step-on-Wafer processing
and ion-implantation techniques.
The addition of the Microelectronics
Research Center in Colorado Springs adds a
new dimension to Mostek circuit design
capabilities. Using the latest computer-aided
design techniques, center engineers will be
keeping ahead of the future with new
technologies and processes.
PRODUCTION CAPABILITY
The commitment to increasing production
capability has made Mostek the world's
largest manufacturer of dynamic RAMs. We
entered the telecommunications market in
1974 with a tone dialer, and have shipped
millions of telecom circuits since then. More
than two million of our MK3870 single-chip
microprocessors are in use throughout the
world. To meet the demand, production
capability is being constantly increased.
Recent construction in Dallas, Ireland and
Colorado Springs has added some 50
percent to the Mostek manufacturing
capaCity.
QUALITY
The worth of a product is measured by
how well it is designed, manufactured and
tested and by how well it works in your
II-vii
alternative to discrete logic systems is
provided.
Memory Products
Through innovations.in both circuit design,
wafer processing and production, Mostek
has become the industry's leading supplier
of memory produCts.
An example of Mostek leadership is our
new BYTEWYDpM family of static RAMs,
ROMs, and EPROMs. All provide high
performance, N words x 8-bit organization
and common pin configurations to allow
easy system upgrades in density and
performance. Another important product
area is fast static RAMs. With major
advances in technology, Mostek static RAMs
now feature access times as low as 55
nanoseconds. With high density ROMs and
PROMs, .static RAMs, dynamic RAMs and
pseudostatic RAMs, Mostek now offers one
of industry's broadest and most versatile
memory product lines.
THE PRODUCTS
Telecommunications Products
Mostek is the leading supplier of tone
dialers, pulse dialers, and CODEC devices.
As each new generation of telecommunications systems emerges, Mostek is
ready with new generation components,
including PCM filters, tone receivers,
repertory dialers, new integrated tone
dialers, and pulse dialers.
These products, many of them using
CMOS technology, represent the most
modern advancements in telecommunications component design.
Microcomputer Components
InduStrial Products
Mostek's microcomputer components are
designed for a wide range of applications.
Our Z80 family is today's industry
standard 8-bit microcomputer. The MK3870
family is one of the industry's most popular
8-bit single-chip microcomputers, offering
upgrade options in ROM, RAM and I/O, all
in the same socket. The 38P7X EPROM
versions support and prototype the entire
family.
Mostek's line of Industrial Products offers
a high degree of versatility per device. This
family of components includes various
microprocessor -compatible A/D converters,
a counter/time-base circuit for the division
of clock signals, and combined
counter/display decoders. Asa result of the
low parts count involved, an economical
II-viii
Microcomputer Systems
function, reducing system cost because the
designer buys only the specific functional
modules his system requires. All MDX
boards are STD-Z80 BUS compatible.
Complementing the component product
line is the powerful MATRI)(TM
microcomputer development system, a Z80based, dual floppy-disk system that is used to
develop and debug software and hardware
for all Mostek microcomputers.
A software operating system, FLP-80DOS,
speeds and eases the design cycle with
powerful commands. BASIC, FORTRAN, and
PASCAL are also available for use on the
MATRIX.
Mostek's MD Series™ features both
stand-alone microcomputer boards and
expandable microcomputer boards. The
expandable boards are modularized by
Memory Systems
Taking full advantage of our leadership in
memory components technology, Mostek
Memory Systems offers a broad line of
products, all with the performance and
reliability to match our industry-standard
circuits. Mostek Memory Systems offers addin memory boards for popular DEC and Data
General minicomputers.
Mostek also offers special purpose and
custom memory boards for special
appl ications.
II-ix
II-x
u.s.
AND CANADIAN SALES OFFICES
CORPORATE HEADOUARTERS
Southeast U.S.
Mostek Corporation
1215 W. Crosby Rd.
P. O. Box 169
Mostek
Carrollton, Texas 75006
REGIONAL OFFICES
Eastern U.S.lCanada
Mostek
49 W. Putnam, 3rd Floor
Greenwich, Conn. 06830
203/622-0955
lWX 710-579-2928
Northeast U.S.
Mostek
29 Cummings Park, Suite #426
Woburn. Mass. 01801
617/935-0635
Chicago Region
Mostek
701 E. Irving Park Road
Central U.S.
Mostek
4100 McEwen Road
Suite 206
Suite 151
Tampa, Florida 33607
312/529-3993
214/386-9340
TWX 910-291-1207
North Central U.S.
Southwest Regkm
Mostek
Southam Califomia
Mostek
6101 Green Valley Dr.
Bloomington, Mn. 55438
4100 McEwen Road
Suite 237
Dallas. Texas 75234
Suite 140
813/876-1304
lWX 810-876-4611
Atlanta Region
2 Exchange Place
2300 Peachford Rd. #2105
Atlanta, GA 30338
404/458·7922
TWX 810·757-4231
Upstate NY Region
Mostek
4651 Crossroads Park Dr" Suite 201
Liverpool. NY 13088
TWX 710·348·0459
315/457-2160
Mid-Atlantic U.S.
Mostek
East Gate Business Center
125 Gaither Drive, Suite D
Mt. Laurel. New Jersey 08054
Florida Region
Mostek
22521 Southwest 66th Ave.
Apt.A211
Boca Raton. FL 33433
609/235·4112
TWX 710-897-0723
Seattle Region
Exchange Bank Bldg.
1111 N. Westshore Blvd.
Suite 414
Roselle. III. 60172
612/831-2322
Dallas. Texas 75234
214/386-9141
lWX 910·576·2802
TWX 910-860-5437
South Central U.S.
Mostek
3400 S. Dixie Ave.
Suite 1m
Kettering, Ohio 45439
5131299-3405
TWX 810·459·1625
Chevy Chase #4
7715 Chevy Chase Dr" #1 16
Austin, TX 78752
Michigan
Mostek
Livonia Pavillion East
29200 Vassar, Suite 520
Livonia. Mich. 48152
313/478·1470
lWX 810-242-2978
II-xi
512/458-5226
TWX 910·874·2007
Westem Region
Northern Califom~
Mostek
1762 Technology Drive
Suite 126
San Jose, Calif. 95110
Mostek
1107 North East 45th St.
Suite 411
Seattle, WA 98105
2061632-0245
TWX 910-444-4030
Mostek
18004 Skypark Blvd.
Irvine, Calif. 92714
714/549-0397
TWX 910-595-2513
Arizona Region
Mostek
2150 East Highland Ave.
Suite 101
Phoenix, AZ 85016
602/954-6260
TWX 910-957-4581
Denver Region
3333 Quebec Street, #9090
Denver, CO 80207
303/321-6545
1WX91Q·931·2583
U.S. AND CANADIAN REPRESENTATIVES
Beacon Elect Assoc.• Inc.
11309 S. Memorial Pkwy.
ALABAMA
GEORGIA
Conley & Associates, Inc.
3951 Pleasantdale Road
Suite 201
Doraville, GA 30340
404/447-6992
TWX 810-766-0488
KENlUCKY
Rich Electronic Marketing
5910 Bardstown Road
P. O. Box 911-47
Louisville, KY 40291
5021239-2747
TWX 810-535-3757
NEW JERSEY
Tritek Sales, Inc.
21 E. Euclid Ave.
Haddonfield, NJ 08033
609/429-1551
215/627..0149 (Philadelphia line)
TWX 710-896-0881
SuiteG
Huntsville, AL 35803
206/881 -5031
1WX 810-726-2136
ARIZONA
Summit Sales
7825 E. Redfield Rd.
ScottsdaI.,/I>Z85260
602/998-4850
TWX 910-950-1283
IWNOIS
Carlson Electronic Sales600 East Higgins Road
Elk Grove Village. IL 60007
312/956-8240
TWX 910-222-1819
MARYlAND
Arbotek Associates
3600 SI. Johns Lane
Ellicott City, MD 21043
301/461-1323
TWX 710-862-1874
NEW MEXICO
Waugaman Associates
P.O. Box 14894
Albuquerque, NM 87111
ARKANSAS
Beacon Elect. Assoc., Inc.
P.O. Box 5382, Brady Simian
little Rock, AI< 72215
5011224-5449
TWX 910-722-7310
INOIANA
Rich Electronic Marketing·
MASSACHUSETTS
New England Technical Sales·
135 Cambr.idge Street
Burlington, MA 01803
617/272-0434
TWX 710-332{)435
CAUFORNIA
Harvey King, Inc.
8124 Miramar Road
San Diego, CA 92126
714/566-5252
TWX 910-335-1231
COLORADO
Waugaman Associates
4800 Van Gordon
Wheat Ridge, CO 80033
303/423-1020
TWX 910-938-0750
CONNECTICUT
New England Technical Sales
240 Pomeroy Ave.
699 Industrial Drive
Carmel. IN 46032
317/844-8462
TWX 81.0-260-2631
Rich Electronic Marketing
3448 West Taylor 5t.
Fort Wayne, IN 46804
219/672-3329
TWX 810-332-1404
IOWA
cahill, Schmitz & Cahill, Inc.
208 Collins Rd. N.E. Suite K
Cedar Rapids, IA 52402
319/377-8219
TWX 910-525-1363
Carlson Electronic Sales
204 Collins Rd. NE
Cedar Rapids, IA 52402
319/377-6341
TWX 910-222-1819
Meriden. CT 06450
2031237-8827
TWX 710-461-1126
FLORIDA
Conley & Associates, Inc.
P.O. Box 309
235 S. Central
Oviedo, FL 32765
305/365-3283
TWX 810-856-3520
KANSAS
Rush & West Associates·
107 N. Chester Street
Olathe, KN 66061
913/764-2700
TWX 910-749-6404
MICHIGAN
Action Components
19547 Coachwood Rd.
Rivenriew, MI48192
313/479-1242
MINNESOTA
Cahill, Schmitz & Cahill, Inc.
315 N. Pierce
SI. Paul, MN 55104
612/646-7217
TWX 910-563-3737
MISSOURI
Rush & West Associates
481 Melanie Meadows Lane
Ballwin, MO 63011
314/394-7271
NORTH CAROLINA
Conley & Associates, Inc.
3301 Womans Club Drive
Suite 130
Raleigh, NC 27616
919IJ87-8090
TWX 510-928-1829
Conley & AsSOCiates, Inc.
4021 W. Waters
Suite 2
Tampa, FL 33614
813/885-7658
TWX 810-876-9136
or
9004 Menaul NE
Suite 7
Albuquerque, NM 87112
5051294-1437
505/294-1436 (Ans. Service)
NEW YORK
ERA Inc.
354 Veterans Memorial Highwav
Commack, NY 11725
516/543-0510
TWX 510-226-1485
(New Jersey Phone #
800/645-5500, 5501)
Precision Sales Corp.
5 Arbustus Ln., MR-97
Binghamton, NY 13901
607/648-3686
Precision Sales Corp.·
1 Commerce Blvd.
liverpool, NY 13088
315/451-3480
TWX 710-545-0250
Precision Sales Corp.
3594 Monroe Avenue
Pittsford. NY 14534
716/381 -2820
Precision Sales Corp.
Drake Road
Pleasant Valley, NY 12569
914/635-3233
OHIO
Rich Electronic Marketing
7221 Taylorsville Road
Dayton, Ohio 45424
513/237-9422
TWX 810-459-1767
Rich Electronic Marketing
141 E. Aurora Road
Northfield, Ohio 44067
216/468-0583
Conley & Associates, I!'\C.
P.O Box 700
TWX 810427-9210
1612 N.W 2nd Avenue
Boca Raton, FL 33432
305/395-6108
TWX 510-953-7548
OREGON
Northwest Marketing Assoc.
9999 S.w. Wilshire SI.
Suite 124
Portland OR 97225
5031297-2581
TELEX 36{)465 (AMAPORT PTl)
·Home Office
II-xii
TEXAS
Southern States Marketing, Inc.
P.O. Box 8000
Addison, TX 75001
214/387-2489
1\I\(X 910-860-5138
Southern States Marketing, Inc.
7745 Chevy Chase
Suite 219
'
Austin, TX 78752
512/452-9459
Sout.hern States Marketing, Inc.
9730 Town Park Drive, Suite 104
Houston, Texas 77036
713/988-0991
TWX 910-881-1630
UTAH
Waugaman Associates
2520 S. State Street
#224
Salt Lake City, UT 84115
801/4674263
TWX 910-925-4073
WASHINGTON
Nonhwest Marketing Assoc.
12836 Bellevue-Redmond Rd.
Suite 203E
Bellevue, WA 98CXJ5
206/455-5846
1WX 910-443-2445
WISCONSIN
Carlson Electronic Sales
Nonhbrook Executive Ctr.
10701 West Nonh Ave.
Suite 209
Milwaukee, WI 53226
414/476-2790
TWX 910-222-1819
CANADA
Cantec Representatives Inc.·
1573 laperriere Ave.
Ottawa, Ontario
Canada K1Z 7T3
613/725-3704
TWX 610-562-8967
Cantec Representatives Inc.
83 Galaxy Blvd., Unit 1A
!Rexdale)
Toronto, Canada M9W 5X6
416/675-2460
TWX 610-492-2655
Cantec Representatives Inc.
15737 rue Pierref0nds SI.
Ste-Genevieve, P. Q
(Montreal) H9H 1G3
514/620-6313
TWX 610-422-3985
u.s.
AND CANADIAN DISTRIBUTORS
ARIZONA
FLORIOA
Kierulff Electronics
4134 E. Wood St.
Arrow Electronics
1001 N.W. 62nd St.
Suite 108
Ft. lauderdale, FL 33309
Phoenix, AZ. 85040
602/243-4101
TWX 910/951-1550
Wyle Distribution Group
8155 North 24th Avenue
305/776-7790
TWX 510/955-9456
602/249-2232
1WX 910/951-4282
Arrow Electronics
115 Palm Bay Road, N.W.
Suite 10 Bldg. 200
Palm Bay, FL 32905
CALIFORNIA
305/725-1480
1WX 510/959-6337
Bell Industries
1161 N. Fair Oaks Avenue
Sunnyvale, CA 94086
Diplomat Southland
2120 Calumet
Clearwater, FL 33515
Phoenix, Arizona 85021
MARYLANO
MISSOURI
Advent Electronics
Arrow Electronics
8446 Moller
4801 Benson Avenue
Indianapolis, IN 46268
Baltimore, MD 21227
Olive Electronics
9910 Page Blvd.
St. Louis, MO 63132
INOIANA
3171297-4910
"TWX 810/341-3228
Ft. Wayne Electronics
3606 E. Maumee
Ft. Wayne, IN 46803
3011247-5200
314/426-4500
TWX 710/236-9005
Schweber Electronics
9218 Gaither Rd.
Gaithersburg, MD 20760
1WX 910/763-0720
301/840-5900
816/452-3900
TWX. 9101771-2114
219/423-3422
TWX 810"'332-1562
1WX 710/828-9749
PioneerIindiana
6408 Castleplace Drive
Indianapolis, IN 46250
317/849-7300
TWX 8101260-1794
Arrow Electronics
3810 Varsity Drive
Ann Arbor, MI48104
MICHIGAN
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116
NEW HAMPSHIRE
Arrow Electronics
1 Perimeter Rd.
Manchester, NH 031 03
603/668-6968
408/734-8570
813/443-4514
1WX 910/339-9378
1WX 810/866-0436
IOWA
1WX 8101223-6020
1WX 710/220-1684
Arrow Electronics
521 Weddell Dr.
Sunnyvale, CA 94086
Kierulff Electronics
3247 Tech Drive
St. Petersburg, FL 33702
Advent Electronics
682 58th Avenue
Coun South West
Cedar Rapids, IA 52404
Schweber Electronics
33540 Schoolcraft Road
Livonia, MI 48150
NEW JERSEY
Arrow Electronics
408/745-6600
813/576-1966
1WX 910/339-9371
1WX 810/863-5625
Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
213/725-0325
"TWX 910/580-3106
Kierulff Electronics
8797 Balboa Avenue
San Diego, CA 92123
7141278-2112
1WX 910/335-1182
Kierulff Electronics
14101 Franklin Avenue
Tustin CA 92680
714/731 -5711
lWX 910/595-2599
Schweber Electronics
17811 Gillette Avenue
Irvine, CA 92714
714/556-3880
lWX910/595-1720
Wyle Distribution Group
124 Maryland Street
EI Segundo, CA 90245
213/322-8100
TWX 910/348-71 1 1
Wyle Distribution Group
9525 Chesapeake Drive
San Diego, CA 92123
714/565-9171
GEORGIA
Arrow Electronics
2979 Pacific Ave.
Norcross. GA 30071
404/449·8252
1WX 810/766-0439
Schweber Electronics
4126 Pleasantdale Road
Atlanta, GA 30340
404/449-9170
313/971-8220
319/363-0221
1WX 910/525-1337
MASSACHUSElTES
Kierulff Electronics
13 Fortune Drive
Billerica, MA 01821
617/935-5134
TWX 710/390-1449
Lionex Corporation
1 North Avenue
Burlington, MA 01803
ILLINOIS
6171272-9400
TWX 710/332-1387
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193
Sch...veber Electronics
25 Wiggins Avenue
Bedford, MA 01730
6171275-5100
312/893-9420
1WX 9101291-3544
1WX 710/326-0268
Arrow Electronics
960 Commerce Way
Woburn, MA 01801
Bell Industries
3422 W. Touhy Avenue
Chicago. IL 60645
617/933-8130
312/982-9210
1WX 710/393-6770
TWX 910/223-4519
Kierulff Electronics
1536 lanmeier
Elk Grove Village, IL 60007
312/640-0200
1WX 9101222-0351
1WX 910/335-1590
Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714
714/641-1600
1WX 910/348-7111
Wyle Distribution Group
3000 Bowers Ave.
Santa Clara, CA 95051
408/727-2500
TWX 910/338-0296
COLORAOO
Kierulff Electronics
10890 E. 47th Avenue
Denver, CO 80239
303/371-6500
1WX 91 0/932-0169
Wyle Distribution Group
451 E. 124th Ave.
Thornton, CO 80241
303/457-9953
1WX 910/936-0770
CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford. CT 06492
203/265-7741
TWX 710/476-0162
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT06810
203/792-3500
TWX 710/456-9405
II-xiii
313/525-8100
TWX 8101242-2983
MINNESOTA
Pleasant Valley Avenue
Morrestown, NJ 08057
609/235-1900
TWX. 710/897-0829
Arrow Electronics
5251 W. 73rd Street
Edina, MN 55435
Arrow Electronics
285 Midland Avenue
Saddlebrook.. NJ 07662
612/830-1800
1WX 910/576-3125
1WX 710/988-2206
Industrial Components
5229 Edina Industrial Blvd.
Minneapolis, MN 55435
6121831-2666
lWX 910/576-3153
201/797-5800
Kierulff Electronics
3 Edison Place
Fainield, NJ 07006
201/575-6750
1WX 7101734-4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006
2011227-7880
TWX 7101734-4305
U.S. AND CANADIAN DISTRIBUTORS
NEW MEXICO
OHIO
TEXAS
Bell Industries
11728 Linn N.E.
Arrow Electronics
Arrow Electronics
13715 Gamma Road
Albuquerque, NM 87123
5051292-2700
1WX 910/989·0625
Arrow ElectronICS
2460 Alamo Ave. S.E.
Albuquerque, NM 87106
7620 McEwen Road
Centerville, OH 45459
513/435-5563
lWX 810/459-1611
Arrow Electronics
, 0 Knoll Crest Drive
Reading, OH 45237
P.O. Box 401068
Dallas, TX 75240
214/386-7500
TWX 910/860-5377
Quality Components
TWX 910/989-1679
513/761-5432
TWX 810/461-2670
10201 McKalla
Suite 0
Austin, TX 78758
NEWVQRK
Arrow Electronics
6238 Cochran Road
Solon, OH 44139
1WX 910/874-1377
5051243-4566
Arrow Electronics
900 Broad Hollow Rd.
Farmingdale. Lt, NY 11735
516/694-6800
TWX 510/224-6494
Arrow Electronics
7705 Maltlage Drive
P. O. Box 370
Liverpool. NY 13088
315/652·1000
TWX 710/545-0230
Arrow Electronics
3000 S. Winton Road
Rochester, NY 14623
7161275-0300
TWX 510/253-4766
Arrow Electronics
200ser Ave.
Hauppauge. NY 11787
516/231-1000
TWX 5101227-6623
Lionex Corporation
400 Oser Ave.
Hauppauge, NY 11787
516/273-1660
TWX 510/221.-2196
Schwaber Electronics
2 Twin line Circle
Rochester, NY 14623
716/424-2222
Schweber Electronics
Jericho Turnpike
Westbury. NY 11590
516/334-7474
lWX 5101222-3660
NORTH CAROLINA
Arrow Electronics
938 Burke 51.
Winston Salem, NC 27102
919/725-8711
TWX 510/931 -3169
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
919/275-6391
lWX 510/925-1094
2161248-3990
TWX 810/427-9409
Schweber Electronics
23880 Commerce Park Road
Beachwood, OH 44122
216/464-2970
TWX 810/427-9441
Pioneer/Cleveland
4800 East 131st Street
Cleveland, OH 44105
215/587-3600
lWX 810/422-2211
Pioneer/Dayton-Industrial
4433 Interpoint Blvd.
Dayton, OH 45424
5131236-9900
lWX810/459-1622
512/835-0220
Quality Components
4257 KeUway Circle
Addison, TX 75001
214/387-4949
TWX 910/860-5459
Quality Comp:ments
6126 Westline
Houston, TX 77036
713/772-7100
Sch\N9ber Electronics
7420 Harwin Drive
Houston, TX 77036
713/784-3600
TWX 910/881- 11 09
OREGON
Klerulff Electronics
14273 NW Science Park
Portland, OR 97229
503/641-9150
TWX 910/467-8753
PENNSYLVANIA
Schweber Electronics
101 Rock Road
Horsham, PA 19044
215/441--0500
Arrow Electronics
650Seco Rd.
Monroeville, PA 15146
4121856-7000
Pioneer/Pittsburgh
560 Alpha Drive
Pittsburgh, PA 15238
4121782-2300
TWX 7101795-3122
SOUTH CAROLINA
Hammond Electronics
1035 Lown Des Hill Rd.
Greenville, SC 29602
803/233-4121
TWX 8101281-2233
/I-xiv
UTAH
Bell Industries
3639 W. 2150 South
Salt lake City, UT 84120
801/972-6969
TWX 910/925-5686
Kierulff Electronics
2121 South 3600 West
Salt Lake City, ur 84104
801/973-6913
WASHINGTON
Kierutff Electronics
1005 Andover Park East
Tukwila, WA 98188
208/575-4420
lWX 910/444-2034
Wyle Distribution Group
1750 132ndAvenue N.E.
Bellevue, Washington 98005
206/453-8300
lWX 910/443-2526
WISCONSIN
Arrow Electronics
434 Rawson Avenue
Oak Creek, WI 53154
414/764-6600
lWX 9101262-1193
Kierulff Electronics
2212 E. Moreland a,Vd.
Waukesha, WI 53186
414/784-8160
TWX 9101262-3653
CANADA
Prelco Electronics
2767 Thames Gate Drive
Mississauga, Ontario
Toronto l4T lG5
416/678-0401
lWX 6101492-8974
Prelco Electronics
480 Port Roval 51. W.
Montreal 357 P.Q. H3l289
514/389-8051
lWX 610/421-3616
Prelco Electronics
1770 Woodward Drive
Ottowa, Ontario K2C OPS
6131226-3491
Telex 05-34301
RAE. Industrial
3455 Gardner Court
Burnaby, 8.C. V5G 4J7
604/291-8866
TWX 610/929-3065
Zentronics
141 Catherine Street
Ottawa, Ontario
K2P lC3
613/238-6411
Telex 05-33636
Zentronics
1355 Meyerside Drive
Mississauga, Ontario
(Toronto) L5T 1C9
416/676-9000
Telex 06-983657
Zentronics
5010 Rue Pare
Montreal, Quebec
M4P 1P3
5141735-5361
Telex 05-827535
Zentronics
590 Berrv Street
51. James, Manitoba
(Winnipeg) R2H OR4
204/775-8661
Zentronics
480A Dutton Drive
Waterloo, Ontario
N2l4C6
519/884-5700
INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
Mostek International
Av de Tervuren 270-272
8-1150 Brussels/Belgium
021762 18.80
Telex: 62011
GERMANY
PUB
PLZ 1-5
Mostek GmbH
Zaunkonigstr.18
0-8021 Ottobrunn
Mostek GmbH
FriedlandstraBe
0-2085 Quickborn
089-609 1017
JAPAN
Mostek Japan KK
Sanyo Bldg 3F
1-2-7 Kita-Aoyama
Minato-Ku. Tokyo 107
14106)2077I7B
Telex: 5216516
(03)404-7261
UNITED KINGDOM
Mostek U.K. ltd.
Masons House,
1 -3 Valley Drive
Kingsbury Road
London. N.W.9
Telex: J23686
01-204 9322
Telex: 213685
FRANCE
Mostek France s.a.r.!.
30 Rue du Morvan
SIUC 505
F-94623 Rungis Cedex
(1)68734.14
Telex: 204049
ITALY
PU 6-7
Telex: 25940
Mostek Italia SRl
Via G.D. Guerrazzi 27
120145 Milano
Mostek GmbH
SchurwaldstraBe 15
0-7303 Neuhausen/Filder
102) 31B.5337/349 2696
7158/66.45
Telex' 72.38.86
and 34.23.98
Telex: 333601
SWEDEN
Mostek Scandinavia AS
Magnusvagen 1/8 tr
5-1731 Jarfalla
0758-343 38/343 48
Telex: 12997
INTERNATIONAL SALES REPRESENTATIVES/DISTRIBUTORS
AUSTRIA
Transistor Vertriebsges. mbH
AuhofstraBe 41 A
A-ll30 Vienna
(0222)829451, B2 9404
Telex: 01-3738
BELGIUM
Sotronic
14 Rue Pere De Deken
B-1040 Brussels
02 736.10.07.
GERMANY
Dr Oohrenberg
Bayreuther StraBe 3
0-1000 Berlin 30
030-213.80.43
Telex: 0184860
Neye Enatechnik GmbH
SchilierstraBe 14
0-2085 Ouickborn
04106-612-1
Telex: 0 213.590
Telex: 25141
DENMARK
SemicapAPS
Gammel Kongevej 148
DK-1850 Copenhagen
01-22.15.10
Telex: 15987
FINLAND
S.W. Instruments
Karstulantie 48
SF..0J550 Helsinki 55
Branch offices in: Berlin, Hannover,
Dusseldorf, Darmstadt, Stuttgart,
Munchen.
Raffel-Electronic GmbH
LochnerstraBe 1
0-4030 Ratingen 1
02102-280.24
Telex: 8585180
B-0-73.82.65
Siegfried Ecker
Koenigsberger StraBe 2
0-6120 Michelstadt
Telex: 122411
06061-2233
Telex: 4191630
FRANCE
Societe Copel
Rue Fourny, Z.I.
B.P. 22, F-78 530 SUC
(1 r 735.33.20
Telex: 204 534
PEP.
Matronic GmbH
Lichtenberger Weg 3
0-7400 Tubingen
07071-24331
Telex: 7262879
4 Rue Barthelemy
F·92120 Montrouge
Oema-Electronic GmbH
BlutenstraBe 21
O-BOClO Munchen 40
(1)-735.33.20
(089)288018/19
Telex: 204 534
Telex: 05-29345
SCAI8
80 Rue d'Arcueil
SILIC 137
F-94150 Rungis Cedex
Telex: 204674
ITALY
Comprel S.r.l.
V.le Romagna. 1
1-20092 Cinisello B. (Mil
(02)61.20.641/2/3/4/5
Telex: 332484
Sorhodis
150-152 Rue A. France
F69100Villeurbanne
Emesa S.PA
Via L. da Viadana, 9
1-20122 Milano
(1)6B7.23.12
(78)850044
(02)869.0616
Telex: 380181
Telex: 335066
THE NETHERLANDS
Nijkerk Elektronika BV
Orentestraat 7
1083 HK Amsterdam
(020) 42B. 933
Telex: 11625
PORTUGAL
Oigicontrole LOA
Rua Tenente Ferreira Ourao 33 RIC
1300 Lisboa
19-688442/652613
Telex: 13639
ISRAEL
Telsys ltd.
12, Kehilat Venetsia
Tel Aviv. Israel
482126/7/8
Telex: 032392
SWEDEN
Interelko AB
5trandbergsgatan, 47
5-12221 Enskede
081 132160
Telex: 10 689
UNITED KINGDOM
Celdis Limited
37-39 loverock Road
Reading
Berks. RG 31 ED
0734-58.51.71
Telex: 848370
For all other countries
MOSTEK INTERNATIONAL
Av de Tervuren 270-272
B-1150 Brussels/Belgium
Lagercrantz Elektronik AB
Box M48 Kanalvagens
5-19421 UpplandsVasby
0760 861 20
Telex: 11275
SPAIN
ComeitaSA
CiaElectronica Tecnicas Aplicadas
Diputacion, 79
Entlo 1-2
Barcelona- 15
3257062
3257554
Telex: 519 34
Lock Distribution Ltd.
Neville Street
Chadderton
Oldham
Lancashire
OL96LF
061-652.04.31
Telex: 669971
Pronto Electronic Systems Ltd,
466-478 Cranbrook Road
Gants Hilllllford
Essex 1G2 6lE
01-544 6222
Telex: 895 4213
Comelta SA
Emilio Munoz 41, ESC 1
Planta 1 Nave 2
Madrid-17
01-754 3001/3077
Telex: 42007
VSI Electronics (UKI ltd.
Roydondury Industrial Park
Horsecroft Rd.
Harlow
Essex CM19 5SY
(0279)35477
SWITZERLAND
MemotecAG
CH-4932 Lotzwil
063-28.11.22
Telex: 68636
NORWAY
Hefro Tekniska AlS
Postboks 6596
Rodelkka
Oslo 5
02-38.02.B6
Telex: 16205
Branch offices in
Bologna, Firenze,
Lavagna, Loreto.
Padova, Roma, Torino
II-xv
Telex: 81387
YUGOSLAVIA
Chemcolor
Inozemma Zastupstva
Proleterskih brigada 37-a
41001 Zagreb
041-513.911
Telex: 21236
Branch office in Beograd
St.
021762 1B.SO
Telex: 62011
MOSTEK CORPORATION
International Dept.
1215 West Crosby Road, Carrollton,
Texas 75006, USA
214/323.6OOJ
Telex: 730423
1981 Z80 MICROCOMPUTER DATA BOOK
zao Family
Technical
Manuals
zao
MOSTEI(.
MICROCOMPUTER DEVICES
Technical Manual
MK3880
CENTRAL
PROCESSING
UNIT
111-1
111-2
TABLE OF CONTENTS
Chapter
Page
1.0 Introduction .............................................................. 111-5
2.0 ZBO-CPU Architecture ..................................................... 111-7
3.0 ZBO-CPU Pin Description ................................................ 111-11
4.0 CPU Timing ............................................................. 111-15·
5.0 ZBO-CPU Instruction Set ................................................. 111-23
6.0 Flags................................................................... 111-43
7.0 Summary of OP Codes and Execution Times ............................... 111-47
B.O Interrupt Response ...................................................... III-59
9.0
Hardware Implementation Examples ...................................... 111-65
10.0 Software Implementation Examples ....................................... 111-71
11.0 Electrical Specifications .................................................. 111-77
12.0 ZBO Instruction Breakdown by Machine Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. III-B3
13.0 Ordering Information .................................................... 111-90
111-3
111-4
1.0 INTRODUCTION
The term "microcomputer" has been used to describe virtually every type of small
computing device designed within the last few years. This term has been applied to
everything from simple "microprogrammed" controllers constructed out of TTL MSI up
to low end minicomputers with' a portion of the CPU constructed out of TTL LSI "bit
slices." However, the major impact of the LSI technology within the last few years has been
with MOS LSI. With this technology, it is possible to fabricate complete and very powerful
computer systems with only a few MOS LSI components.
The Mostek Z80 family of components is a significant advancement in the state-of-art of
microcomputers. These components can be configured with any type of standard semiconductor memory to generate computer systems with an extremely wide range of
capabilities. For example, as few as two LSI circuits and three standard TTL MSI packages
can be combined to form a simple controller. With additional memory and I/O devices a
computer can be constructed with capabilities that only a minicomputer could previously
deliver. This wide range of computational power allows standard modules to be constructed
by a user that can satisfy the requirements of an extremely wide range of applications.
The major reason for MOS LSI domination of the microcomputer market is the low cost of
these few LSI components. For example, MOS LSI microcomputers have already replaced
TIL logic in such applications as terminal controllers, peripheral device controllers, traffic
signal controllers, point of sale terminals, intelligent terminals and test systems. In fact the
MOS LSI microcomputer is finding its way into almost every product that now uses
electronics and it is even replacing many mechanical systems such as weight scales and
automobile controls.
The MOS LSI microcomputer market is already well established and new products using
them are being developed at an extraordinary rate. The Mostek Z80 component set has been
designed to fit into this market through the following factors:
1. The Z80 is fully software compatible with the popular 8080A CPU offered from
several sources. Existing designs can be easily converted to include the Z80 as a
superior alternative.
2. The Z80 component set is superior in both software and hardware capabilities to
any other 8-bit microcomputer system on the market. These capabilities provide the
user with significantly lower hardware and software development costs while also
allowing him to offer additional features in his system.
3. A complete development and OEM system product line including full software
support is available to enable the user to easily develop new products.
Microcomputer systems are extremely simple to construct using Z80 components. Any such
system consists of three parts:
1. CPU (Central Processing Un it)
2. Memory
3.
Interface circuits to peripheral devices
111-5
The CPU is the heart of the system. Its function is to obtain instructions from the memory
and perform the desired operations. The memory is used to contain instructions and in most
cases data that is to be processed. For example, a typical instruction sequence may be to
read data from a specific peripheral device, store it in a location in memory, check the
parity and write it out to another peripheral device. Note that the Mostek component set
includes the CPU and various general purpose I/O device controllers, as well as a wide range
of memory devices. Thus, all required components can be connected together in a very
simple manner with virtually no other external logic. The user's effort then becomes
primarily one of software development. That is, the user can concentrate on describing his
problem and translating it into a series of instructions that can be loaded into the microcomputer memory. Mostek is dedicated to making this step of software generation as simple
as possible. A good example of this is our assembly language in which a simple mnemonic
is used to represent every instruction that the CPU can perform. This language is self documenting in such a way that from the mnemonic the user can understand exactly what the
instruction is doing without constantly checking back to a complex cross listing.
111-6
2.0 Z80'CPU ARCHITECHURE
A block diagram of the internal architecture of the ZSO-CPU is shown in Figure 2.0-1
The diagram shows all of the major elements in the CPU and it should be referred to
throughout the following description.
Z80-CPU BLOCK DIAGRAM
ALU
13
CPU AND
SYSTEM
CONTROL
SIGNALS
INSTRUCTION
OECODE
&
CPU
CONTROL
CPU
CONTROL
iii
-<5V GND
FIGURE 2.0-1
2.1 CPU REGISTERS
The ZSo-CPU contains 20S bits of R/W memory that are accessible to the programmer.
Figure 2.0-2 illustrates how this memory is configured into eighteen S-bit registers and
four 16-bit registers. All ZSO registers are implemented using static RAM. The registers
include two sets of six general purpose registers that may be used individually as S-bit
registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag
registers.
Special Purpose Registers
1. Program Counter (PC). The program counter holds the 16-bit address of the current
instruction being fetched from memory. The PC is automatically incremented after
its contents have been transferred to the address lines. When a program jump occurs
the new value is automatically placed in the PC, overriding the incrementer.
2. Stack Pointer (SP). The stack pointer holds the 16-bit address of the current top of
a stack located anywhere in external system RAM memory. The external stack
memory is organized as a last-in first-out (LI Fa) file. Data can be pushed onto the
stack from specific CPU registers or popped off. of the stack into specific CPU registers through the execution of PUSH and POP instructions. The data popped from the
stack is always the last data pushed onto it. The stack allows simple implementation
of multiple level interrupts, unlimited subroutine nesting and simplification of many
types of data manipulation.
111-7
zao-cpu REGISTER CONFIGURATION
MAIN REG SET
ALTERNATE REG SET
/\
/
A
\./
ACCUMULATOR
A
FLAGS
F
ACCUMULATOR
A'
FLAGS
F·
8
C
B'
C'
0
E
0'
E'
H
L
H'
L'
INTERRUPT
VECTOR
I
I
,
}
GENERAL
PURPOSE
REGISTERS
MEMORV
REFRESH
R
INDEX REGISTER IX
INDEX REGISTER IV
SPECIAL
PURPOSE
REGISTERS
STACK POI NTER SP
PROGRAM COUNTER PC
FIGURE 2,0-2
3. Two Index Registers (IX & IV). The two independent index registers hold a 16-bit
base address that is used in indexed addressing modes. In this mode, an index register
is used as a base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify a displacement from this base. This displacement is specified as a two's complement
signed integer. This mode of addressing greatly simplifies many types of programs,
especially where tables of data are used.
4. Interrupt Page Address Register (I). The Z80-CPU can be operated in a mode where
an indirect call to any memory location can be achieved in response to an interrupt.
The I Register is used for this purpose to store the high order 8-bits of the indirect
address while the interrupting device provides the lower 8-bits of the address. This
feature allows interrupt routines to be dynamically located anywhere in memory with
absolute minimal access time to the routine,
5. Memory Refresh Register (R). The Z80-CPU contains a memory refresh counter to
enable dynamic memories to be used with the same ease as static memories. This 7-bit
register is automatically incremented after each instruction fetch. The data in the
refresh counter is sent out on the lower portion of the address bus along with a
refresh control signal while. the CPU is decoding and executing the fetched instructiQn. This mode of refresh is totally transparent to the programmer and does not
slow down the CPU operation. The programmer can load the R register for testing
purposes, but this register is normally not used by the programmer,
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers.
The accumulator holds the results of 8-bit arithmetic or logical operations while the flag
register indicates specific conditions for 8 or l6-bit operations, such as indicating whether
or not the result of an operation is equal to zero. The programmer selects the accumulator
and flag pair that he wishes to work with with a single exchange instruction so that he may
easily work with either pair.
111-8
General Purpose Registers
There are two matched sets of general purpose registers, each set containing six 8-bit registers that may be used individually as 8-bit registers or as l6-bit register pairs by the programmer. One set is called BC, DE, and HL while the complementary set is called BD', DE'
and H L'. At arlY one time the programmer can select either set of registers to work with
through a single exchange command for the entire set. In systems where fast interrupt
response is required, one set of general purpose registers and an accumulator/flag register
may be reserved for handling this very fast routine. Only a simple exchange command need
be executed to go between the routines. This greatly reduces interrupt service time by
eliminating the requirement for saving and retrieving register contents in the external
stack during interrupt or subroutine processing. These general purpose registers are used for
a wide range of applications by the programmer. They also simplify programming, especially
in ROM based systems where little external read/write memory is available.
2.2 ARITHMETIC & LOGIC UNIT (ALU)
The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally
the ALU communicates with the registers and the external data bus on the internal data bus.
The type of functions performed by the ALU include:
Add
Left or right shifts or rotates (arithmetic and logical)
Subtract
Increment
Logical AND
Decrement
Logical OR
Set bit
Logical Exclusive OR
Reset bit
Compare
Test bit
2.3 INSTRUCTION REGISTER AND CPU CONTROL
As each instruction is fetched from memory, it is placed in the instruction register and
decoded. The control section performs this function and then generates and supplies all of
the control signals necessary to read or write data from or to the registers, controls the
ALU and provides all required external control signals.
111-9
111-10
3.0 lBO-CPU PIN DESCRIPTION
The l8D-CPU is packaged in an industry standard 40 pin Dual In-Line Package. The I/O
pins are shown in Figure 3.0-1 and the function of each is described below.
lBO PIN CONFIGURATION
27
AO
Ml
SYSTEM
CONTROL
Al
MRW
A2
lORa
A3
RD
A4
A5
WR
A6
28
A7
AS
lS
39
ADDRESS
SUS
Ag
A10
All
Z80 CPU
CPU
CONTROL
INT
NMI
A12
A 13
MK 3880
MK 3880-4
A14
A 15
RESET
{SUSRO
CPU
SUS
CONTROL
SUSAK
'1'
+5V
DATA
SUS
GND
FIGURE 3.0-1
AO-A15
(Address Bus)
Tri-state output, active high. Ao-A15 constitute a 16-bit address
bus. The address bus provides the address for memory (up to 64K
bytes) data exchanges and for I/O device data exchanges. I/O
addressing uses the 8 lower address bits to allow the user to
directly select up to 256 input or 256 output ports. AO is the
least significant address bit. During refresh time, the lower 7 bits
contain a valid refresh address.
DO-D7
(Data Bus)
Tri-state input/output, active high. Do-D7 constitute an 8-bit
bidirectional data bus. The data bus is used for data exchanges
with memory and I/O devices.
M1
(Machine Cycle one)
Output, active low. M1 indicates that the current machine cycle
is the OP code fetch cycle of an instruction execution. Note that
during execution of 2-byte op-codes,
is generated as each op
code byte is fetched. These two byte op-codes always begin with
CBH, DDH, EDH, or FDH. M1 also occurs with 10RO to indicate
an interrupt acknowledge cycle.
MREO
(Memory Request)
Tri-state output, active low. The memory request signal indicates
that the address bus holds a valid address for a memory read or
memory write operation.
M1
111-11
Tri-state output, active low. The j"Q'ffQ signal indicates thai the
10RO
(Input/Output Request) lower half of the address bus holds a valid I/O address for a I/O
read or write operation. An 10RO signal is also generated with
an
signal when an interrupt is being acknowledged to indicate
that an interrupt response vector can be placed on the data bus.
Interrupt Acknowledge operations occur during M1 time while
I/O operations never occur during M1 time.
M1
1m
(Memory Read)
rrn
Tri-state output, active low.
indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device
or memory should use this signal to gate data onto the CPU data
bus.
WR
(Memory Write)
Tri-state output, active low. WR indicates that the CPU data bus
holds valid data to be stored in the addressed memory or I/O
device.
RFSH
(Refresh)
Output, active low. RFSH indicates that the lower 7 bits of the
address bus contain a refresh address for dynamic memories and
current MREO signal should be used to do a refresh read to all
dynamic memories. A7 is a logic zero and the upper B bits of the
Address Bus contains the I Register.
HALT
(Halt state)
Output, active low. HALT indicates that the CPU has executed a
HALT software instruction and is awaiting either a non maskable
or a maskable interrupt (with the mask enabled) before operation
can resume. While halted, the CPU executes NOP's to maintain
memory refresh activity.
WAIT*
(Wait)
Input, active low. WAIT indicates to the ZBO-CPU that the addressed memory or I/O devices are not ready for a data transfer.
The CPU continues to enter wait states for as long as this signal is
active. This signal allows memory or I/O devices of any speed to
be synchronized to the CPU.
INT
(Interrupt Request)
Input, active low. The Interrupt Request signal is generated by
I/O devices. A request will be honored at the end of the current
instruction if the internal software controlled interrupt enable
flip-flop (I FF) is enabled .and ifthe BUSRO signal is not active.
When the CPU accepts the interrupt, an acknowledge signal
(lORO during M 1 time) is sent out at the beginning of the next
instruction cycle. The CPU can respond to an interrupt in three
different modes that'are described in detail in section B.
Input, negative edge triggered. The non maskable interrupt request
line has a higher priority than I NT and is always recognized at the
end of the current instruction, independent of the status of the
interrupt enable flip-flop. NMI automatically forces the ZBO-CPU
to restart to location 0066H' The program counter is automatically saved in the external stack so that the user can return to the
program that was interrupted. Note that continuous WAIT cycles
can prevent the current instruction from ending, and that a
BOSFfQ will override a NMl.
111-12
Input, active low. RESET forces the program counter to zero and
mitralizes the CPU. The CPU initialization includes:
1)
2)
3)
4)
Disable the interrupt enable flip-flop
Set Register I = OOH
Set Register R = OOH
Set Interrupt Mode 0
During reset time, the address bus and data bus go to a high
impedance state and all control output signals go to the inactive
state. No refresh occurs.
BUSRQ
(Bus Request)
Input, active low. The bus request signal is used to request the
CPU address bus, data bus and tri-state output control signals to
go to a high impedance state so that other devices can control
these buses. When "BUSRTI is activated, the CPU will set these
buses to a high impedance state as soon as the current CPU
machine cycle is terminated.
BUSAK*
(Bus Acknowledge)
Output, active low. Bus acknowledge is used to indicate to the
requesting device that the CPU address bus, data bus and tristate control bus signals have been set to their high impedance
state and the external device can now control these signals.
Single phase system clock.
*While the Z80-CPU is in either a WAIT state or a Bus Acknowledge condition, Dynamic Memory Refresh
will not occur.
111-13
111-14
4.0 CPU TIMING
The ZSO-CPU executes instructions by stepping through a very precise set of a few basic
operations. These include:
Memory read or write
I/O device read or write
I nterrupt acknowledge
All instructions are merely a series of these basic operations. Each of these basic operations
can take from three to six clock periods to complete or they can be lengthened to synchronize the CPU to the speed of external devices. The basic clock periods are referred to as
T states and the basic operations are referred to as M (for machine) cycles. Figure 4.0-0
illustrates how a typical instruction will be merely a series of specific M and T cycles. Notice
that this instruction consists of three machine cycles (M 1, M2 and M3). The first machine
cycle of any instruction is a fetch cycle which is four, five or six T states long (unless
lengthened by the wait signal which will be fully described in the next section). The fetch
cycle (M 1) is used to fetch the OP code of the next instruction to be executed. Subsequent
machine cycles move data between the CPU and memory or I/O devices and they may have
anywhere from three to five T cycles (again they may be lengthened by wait states to
synchronize the external devices to the CPU). The following paragraphs describe the timing
which occurs within any of the basic machine cycles. In section 7, the exact timing for
each instruction is specified.
BASIC CPU TIMING EXAMPLE
T State
MachIne Cycle
Ml
(QP Code Fetch)
M2
M3
(Memory Read)
(Memory Write)
Instruction Cycle
FIGURE 4.0-0
All CPU timing can be broken down into a few very simple timing diagrams as shown in
Figure 4.0-1 through 4.0-7. These diagrams show the following basic operations with and
without wait states (wait states are added to synchronize the CPU to slow memory or
I/O devices).
4.0-1.
Instruction OP code fetch (M 1 cycle)
4.0-2.
Memory data read or write cycles
4.0-3.
I/O read or write cycles
4.0-4.
Bus Request/Acknowledge Cycle
4.0-5.
I nterrupt Request/Acknowledge Cycle
4.0-6.
Non maskable Interrupt Request/Acknowledge Cycle
4.0-7.
Exit from a HALT instruction
111-15
INSTRUCTION FETCH
Figure 4.0-1 shows the timing during an M1 cycle (OP code fetch). Notice that the PC is
placed on the address bus at the beginning of the M1 cycle. One half clock time later the
MREO signal goes active. At this time the address to the memory has had time to stabilize
so that the falli!2S.. edge of"NfR'EQ can be used directly as a chip enable clock to dynamic
memories. The RD line also goes active to indicate that the memory read data should be
enabled onto the CPU data bus. The CPU samples the data from the memory on the data
bus with the rising edge of the clock of state T3 and this same edge is used by the CPL!
to turn off the 'AD andlim'rn signals. Thus the data has already been sampleo,by the CPU
before the RO signal becomes inactive. Clock state T3 and T4 of a fetch cycle are used to
refresh dynamic memories. (The CPU uses this time to decode and execute the fetched
instruction so that no other operation could be performed at this time). During T3 and T4
the lower 7 bits of the address bus contain a memory refresh address and the RFSH signal
becomes active to indicate that a refresh read of all dynamic memories should be accom·
plished. Notice that a RD signal is not generated during refresh time to prevent data from
different memory segmeots from being gated onto the data bus. The MREO signal during
refresh time should be used to perform a refresh read of all memory elements. The refresh
signal can not be used by itself since the refresh address is only guaranteed to i;le stable
during MREO time.
INSTRUCTION OP CODE FETCH
Ml Cycle
T1
T2
T3
T4
T1
-~ r--L- ~ ~ r--I
AO - A15
I
I
PL
REFRESH ADDA.
T
I
\
L- -
I
\
----- ----- ------ - ----- ----- ~-- ----- ------ ----- --1
J
L ______
00- 07
-
'"iN'"
\-::.:..
\
II
FIGURE 4.0-1
Figure 4.0-1A illustrates how the fetch cycle is delayed if the memory activates the WAIT
line. During T2 and every subsequent Tw, the CPU samples the WAIT line with the falling
edge of <1». If the WAIT line is active at this time, another wait state will be entered during
the following cycle. Using this technique the read cycle can be lengthened to match the
access time of any type of memory device.
111-16
INSTRUCTION OP CODE FETCH WITH WAIT STATES
MI Cycle
T,
Tw
T2
Tw
T4
T3
-fL-. ~ fL-. r--L- ~ ~rAO - A'S
I
I
PC
I
REFRESH ADDR.
~
MREQ
\
RD
\
J
'"i"N tl
1,.;.;..:f1
00 - 07
-h
----- -_L.L__ =l.....I_-_ ~JL
- -----
-
I
----- ----- ------ ----- -
r
FIGURE 4.0-1A
MEMORY READ OR WRITE
Figure 4.0-2 illustrates the timing of memory read or write cycles other than an OP code
fetch (M 1 cycle). These cycles are generally three clock periods long unless wait states are
requested by the memory via the WAIT signal. The MREQ signal and the AD signal are used
the same as in the fetch cycle. In the case of a memory write cycle, the MREQ also becomes
active when the address bus is stable so that it can be used directly as a chip enable for
dynamic memories. The WR line is active when data on the data bus is stable so that it can
be used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore the WR signal goes inactive one half T state before the address and data bus contents
are changed so that the overlap requirements for virtually any type of semiconductor
memory type will be met.
MEMORY READ OR WRITE CYCLES
Memory Write Cycle
Memory Read Cycle
T,
AO - A15
RD
T2
~~
1
T1
T3
T2
I
r---L- ~ ~ IL1
MEMORY ADDR.
\
J
\
I
MEMORY ADDR.
WAIT
r--
I
I
I
\
I
\
DATA BUS
(00-07)
T3
DATA OUT
IN
- ---- YL-_- - - - - f - - - - - -JL--t.---- ----- ---- r-----
-t-----
FIGURE 4.0-2
111-17
Figure 4.0-2A illustrates how a WAIT request signal will lengthen any memory read or
write operation. This operation is identical to that previously described for a fetch cycle.
Notice in this figure that a separate read and a separate write cycle are shown in the same
figure although read and write cycles can never occur simultaneously.
MEMORY READ OR WRITE CYCLES WITH WAIT STATES
T1
AO - A15
T2
Tw
Tw
T1
T3
r----t- ~ ~ r----t- ~ ~
II
~
MEMORY ADDR.
\
I
DATA BUS
(00-07)
}
READ
CYCLE
}
WRITE
.cYCLE
IN
I
DATA BUS
(00-07)
WAiT
DATA OUT
- 1 - - - - - l J___- l...E-;:J-t::::_1 - - - - - - - - - -f - - - - - ----- --- ----
FIGURE 4.0-2A
INPUT OR OUTPUT CYCLES
Figure 4.0~3 illustrates an I/O read or I/O write operation. Notice that during I/O operations
a single wait state is automatically inserted. The reason for this is that during I/O operations,
the time from when the 10RQ signal goes active until the CPU must sample the WAIT line
is very short and without this extra state sufficient time does not exist for an I/O port to
decode .its address and activate the WAIT line if a wait is required. Also, without this wait
state it is· difficult to design MOS I/O devices that can operate at full CPU speed. During
this wait state time the WAIT request signal is sampled. During a read I/O operation, the
RD line is used to enable the addressed port onto the data bus just as in the case of a
memory read. For I/O write operations, the WR line is used as a clock to the I/O port, again
with sufficient overlap timing automatically provided so that the rising edge may be used as
a data clock.
Figure 4.0-3A illustrates how additional wait states may be added with the WAIT line.
The operation is identical to that previously described.
BUS REQUEST/ACKNOWLEDGE CYCLE
Figure 4.0-4 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSRQ
signal is sampled by the CPU with the rising edge of the last clock period of any machine
cycle .. lf the BUSRQ signal is active, the CPU will set its address, data and tri-state control
signals to the high impedance state with the rising edge of the next clock pulse. At that
time any ,exterhaf device can control the buses to transfer data between memory and I/O
devices. (This is generally known as Dirf;'lCt Memory Access [DMA] using cycle stealing).
The maximum time for the CPU to respond toa bus request is the length of a machine
cycle and the external controller can maintain control of the bus for as many clock cycles
as is desired. Note, however, that if very long DMA cycles are used, and dynamic memories
are being used, the external controller must also perform the refresh function. This situation
only' occurs if very large blocks of data are transferred under DMA control. Also note that
during a bus request cycle, the CPU cannot be interrupted by either a NMI or an INT signal.
111-18
INPUT OR OUTPUT CYCLES
I
T1
-
T1
T3
~~~~~
U
AD' A7
Tw'
T2
~
PORT AOORESS
J
\
RD
I
}
DATA BUS
Read
Cycle
IN
-
-
~----
1-----
- - - - - --:IL= r------
------\
WR
J
DATA BUS
} w",e
Cycle
OUT
* I nserted by
I
Z80 CPU
FIGURE 4.0.-3
INPUT OR OUTPUT CYCLES WITH WAIT STATES
T1
Tw'
T2
Tw
T3
- ~ ~ ~ r--L- ~ n-AD -
A7
1
11
PORT ADDRESS
\
IN
DATA BUS
}
WAIT
READ
CYCLE
- - - - - j - - - - - ~_1J:_= j - T L - - j - - - - - j - - - 1 - - - - -1 - - - - ---- 1 - - - - jOUT
DATA BUS
}
J
I
WRITE
CYCLE
* I nserted by
FIGURE 4.0-3A
111-19
Z8D CPU
BUS REQUEST/ACKNOWLEDGE CYCLE
- - - - - - A n y M Cycle'-----I_---BusAwailable States---+l
Last T Sta~.
AO-A15
00-07
MREQ.
RD.
-t----i----+----h
Wii.IDRQ
FIGURE 4.0-4
INTERRUPT REQUEST/ ACKNOWLEDGE CYCLE
Fi.llure 4.()..5 illustrates the timing associated with an interrupt cycle. The interrupt signal
(TJrr) is sampled by the CPU with the rising edge of the last clock at the end of any in·
struction. The signal will not be accepted ihthe internal CPU software controlled interrupt
enable flip-flop is not set or if the BUSR signal is active. When the signal is accepted a
special M1 cycle is generated. During this special M1 cycle the IORQ signal becomes active
(instead of the normal MREQ) to indicate that the interrupting device can place an B-bit
vector on the data bus. Notice that two wait states are automatically added tQ this cycle.
These states are added so that a ripple priority interrupt scheme can be easily implemented.
The two wait states allow sufficient time for the ripple signals to stablilize and identify
which I/O device must insert the response vector. Refer to section B.O for details on how the
interrupt response vector is utilized by the CPU.
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
M Cvcle
- -ofLastInstruction
MI
.
- ~ r---t- ~ ~ ~ r---L- ~
---------- ---- ---- ----- ---:'L .1-:---- --- ---- ---- 1 - - - - - ----- 1 - - - - - ----Last T State
AO - A15
T1
T2
I
Tw'
Tw
T3
I
PC
\
REFRESH
I
J
\
r--
DATA BUS
L...!!"r'
1--------- --_
----- r-------...... -r---- - - - - r-JL:: 1 - - - - ---------- 1
-- ----Mode
FIGURE 4.0-5
111-20
0 shown
Figure 4.0-5A illustrates how additional wait states can be added to the interr"r'lt respOf'l8
cycle. Again the operation is identical to that prriiously described.
INTERRUPT REQUEST/ACKNOWLEDGE WITH WAIT STATES
MI
Tl
.......I
AO - A15
T2
~~
A
T •
Tw'
w
TJ
Tw
T4
IL---IL--- ~ ~ ~
I
PC
-"'\
RE~RESH
~
ADDR.
I
-- ----- ---- ----- r_-_Lf.: TL'::: f---------- - - - - ----- ------ ----- ----I
h
f"iN
\
DATA BUS
' - - r--'
t
.r-
~
Mode
FIGURE 4.0-5A
NON MASKABLE INTERRUPT RESPONSE
Figure 4.0-6 illustrates the request/acknowledge cycle for the non-maskable interrupt.
A pulse on the NMI input sets an internal NMI latch which is tested by the CPU at the
end of every instruction. This NMI latch is sampled at the same time as the interrupt line,
but this line has priority over the normal interrupt and it can not be disabled under software control. Its usual function is to provide immediate response to important signals
such as an impending power failure. The CPU response to a non maskable interrupt is
similar to a normal memory read operation. The only difference being that the content'
of the data bus is ignored while the processor automatically stores the PC in the external
stack and jumps to location 0066H. The service routine for the non maskable interrupt
must begin at this location if this interrupt is used.
HALT EXIT
Whenever a software halt instruction is executed the CPU begins executing NOP's until an
interrupt is received (either a non-maskable or a maskable interrupt while the interrupt
flip flop is enabled). The two interrupt lines are sampled with the rising clock edge during
each T4' state as shown in Figure.4.0-7. If a non-maskable interrupt has been received or a
maskable interrupt has been received and the interrupt enable flip-flop is set, then the halt
state will 'be exited on the next rising clock edge. The following cycle will then be an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are
received at this time, then the non maskable one will be acknowledged since it was highest
priority. The purpose of executing NOP instructions while in the halt state is to keep the
memory refresh signals active. Each cycle in the halt state is a normal M 1 (fetch) cycle
except that the data received from the memory is ignored and a NOP instn ':tion is forced
internally to the CPU. The halt acknowledge signal is active during this time to indicate
that the processor is in the halt state.
111-21
0 shown
NON MASKABLE INTERRUPT REQUEST OPERATION
M2. M3'
MI
- - - Last M Cyde
LastT Time
T3
T2
Tl
TS
T4
---"L- - I"'L- I\...- ~IL-IL-IL--------- t----- -------- - - - - ----- ----- --- ~--.:.::
-- ---_L
~----
I
AO - A15
PC
\
I
REFRESH
I
J
\
J
I
\.
J
*M2 and M3 are stack write operations
FIGURE 4.0-6
HALT EXIT
--Ml----<*'I---------Ml-------_~--
Tl
T2
INTor
NMI
HALT INSTRUCTION
IS RECEIVED
DURING THIS
MEMORY CYCLE
FIGURE 4.0-7
111-22
Ml
T2
5.0
zao-cpu INSTRUCTION SET
The Z80-CPU can execute 158 different instruction types including all 78 of the 8080A
CPU. The instructions can be broken down into the following major groups:
•
•
•
•
•
•
Load and Exchange
Block Transfer and Search
Arithmetic and Logical
Rotate and Shift
Bit Manipulation (set, reset, test)
Jump, Call and Return
Input/Output
• Basic CPU Control
5.1 INTRODUCTION TO INSTRUCTION TYPES
The load instructions move data internally between CPU registers or between CPU registers
and external memory. All of these instructions must specify a source location from which
the data is to be moved and a destination location. The source location is not altered by
a load instruction. Examples of load group instructions include moves between any of the
general purpose registers such as move the data to Register B from Register C. This group
also includes load immediate to any CPU register or to any external memory location.
Other types of load instructions allow transfer between CPU registers and memory locations.
The exchange instructions can trade the contents of two registers.
A unique set of block transfer instructions is provided in the Z80. With a single instruction a
block of memory of any size can be moved to any other location in memory. This set of
block moves is extremely valuable when large strings of data must be processed. The Z80
block search instructions are also valuable for this type of processing. With a single
instruction, a block of external memory of any desired length can be searched for any 8-bit
character. Once the character is found the instruction automatically terminates. Both the
block transfer and the block search instructions can be interrupted during their execution so
as to not occupy the CPU for long periods of time.
The arithmetic and logical instructions operate on data stored in the accumulator and other
general purpose CPU registers or external memory locations, The results of the operations
are placed in the accumulator and the appropriate flags are set according to the result of
the operation. An example of an arithmetic operation is adding the accumulator to the contents of an external memory location. The results of the addition are placed in the
accumulator. This group also includes 1&:bit addition and subtraction between 16-bit CPU
registers.
The bit manipulation instructions allow any bit in the accumulator, any general purpose
register or any external memory location to be set, reset or tested with a single instruction.
For example, the most significant bit of register H can be reset. This group is especially
useful in control applications and for controlling software flags in general purpose programming.
The jump, call and return instructions are used to transfer between various locations in the
user's program. This group uses several different techniques for obtaining the new program
counter address from specific external memory locations. A unique type of jump is the
restart instruction. This instruction actually contains the new address as a part of the 8·bit
OP code. This is possible since only 8 separate addresses located in page zero of the external
memory may be specified. Program jumps may also be achieved by loading register HL, IX
or IV directly into the PC, thus allowing the jump address to be a complex function of the
routine being executed.
111-23
The input/output group of instructions in the zao allow for a wide range of transfers
between external memory locations or the general purpose CPU registers, and the external
I/O devices. In each case, the port number is provided on the lower a bits of the address
bus .during any I/O transaction. One instruction allows this port number to be specified by
the second byte of the instruction while other zao instructions allow it to be specified
as the content of the C register. One major advantage of using the C register as a pointer to
the I/O device is that it allows different I/O ports to share common software driver routines.
This is not possible when the address is part of theOP codE1 if the routines are stored in
ROM. Another feature of these input instructions is that they set the flag register automatically so that additional operations are not required to determine the state of the input data
(for example its parity). The zaO-cpu includes single instructions that can move blocks or
data (up to 256 bytes) automatically to or from any I/O port directly to any memory
location. In conjunction with the dual set of general purpose registers, these instructions
provide for fast I/O block transfer rates. The value of this I/O instruction set is demonstrated by the fact tli'ai the zao-cpu can provide all required floppy disk formatting (i.e.,
the CPU provides the preamble, address, data and enables the CRC codes) on double density
floppy disk drives on an interrupt driven basis.
Finally, the basic CPU control instructions allow various options and modes. This group
includes instructions such as setting or resetting the interrupt enable flip flop or setting
the mode of interrupt response.
5.2 ADDRESSING MODES
Most of the zao instructions operate on data stored in internal CPU registers, external
memory or in the I/O ports. Addressing refers to how the address of this data is generated
in each instruction. This section gives a brief summary of the types of addressing used
in the zao while subsequent sections detail the type of addressing available for each instruction group.
Immediate. In this mode of addressing the byte following the OP code in memory contains
the actual operand.
ne or 2 bytes
Examples of this type of instruction would be to load the accumulator with a constant,
where the constant is the byte immediately following the OP code.
Immediate Extended. This mode is merely an extension of immediate addressing in that the
two bytes following the op codes are the operand.
OP Code
one or 2 bytes
Operand
low order
Operand
high order
Examples of this type of instruction would be to load the H L register pair ( 16-bit register)
with 16 bits (2 bytes) of data.
111-24
Modified Page Zero Addressing. The Z80 has a special single byte call instruction to any of
8 locations in page zero of memory. This instruction (which is referred to as a restart) sets
the PC to an effective address in page zero. The value of this instruction is that it allows a
single byte to specify a complete 16-bit address where commonly called subroutines are
located, thus saving memory space.
lop Code I
bO
one byte
Effective address is (00b5b4b3000)
Relative Addressing. Relative addressing uses one byte of data following the OP code to
specify a displacement from the existing program to which a program jump can occur.
This displacement is a signed two's complement number that is added to the address of the
OP code of the following instruction.
OP Code }
Jump relative (one byte OP code)
Operand
8-bit two's complement displacement added to
Address (A+2)
The value of relative addressing is that it allows jumps to nearby locations while only
requiring two bytes of memory space. For most programs, relative jumps are by far the
most prevalent type of jump due to the proximity of related program segments. Thus,
these instructions can significantly reduce memory space requirements. The signed displacement can range between +127 and -128 from A + 2. This allows for a total displacement of +129 to -126 from the jump relative OP code address. Another major advantage
is that it allows for relocatable code.
Extended Addressing. Extended Addressing provides for two bytes (16 bits) of address to
be included in the instruction. This data can be an address to which a program can jump or
it can be an address where an operand is located.
OPCode
r---------------------------~
J
one or two bytes
Low Order Address or Low order operand
High Order Address or High order operand
Extended addressing is required for a program to jump from any location in memory to any
other location, or load and store data in any memory location.
When extended addressing is used to specify the source or destination address of an operand,
the notation (nn) will be used to indicate the content of memory at nn, where nn is the
16-bit address specified in the instruction. This means that the two bytes of address nn are
used as a pointer to a memory location. The use of the parentheses always means that the
value enclosed within them is used as a pointer to a memory location. For example, (1200)
refers to the contents of memory at location 1200.
Indexed Addressing. In this type of addressing, the byte of data following the OP code
contains a displacement which is added to one of the two index registers (the OP code
specifies which index register is used) to form a pointer to memory. The contents of the
index register are not altered by this operation.
OPCode
~-----I
}
two byte OP code
OPCode
Displacemen Operand added to index register to form a pointer
to memory.
111-25
An example of an indexed instruction would be to load the contents. of the memory location (Index Register + Displacement) into the accumulator. The displacement is a signed
two's complement number. Indexed addressing greatly simplifiesp(ograms using tables of
data since the index register can point to the start of any table. Two index registers are
provided since very often operations require two or more tables. Indexel! .addressing also
allows for relocatable code.
.
The two index registers in the Z80 are referred to as IX and IY. To indicate indexed addressing the notation:
(lX+d) or (lY+d)
is used. here d is the displacement specified after the OP code. The parentheses indicate that
this value is used as a pointer to· external memory.
Register Addressing. Many of the Z80 OP codes contain bits .of .information that specify
which CPU register is to be used for an op.eration. An example of register addressing would
be to load the data in register B into register C.
Implied Addressing. Implied addressing refers to operations where the OP code automatically implies one or more CPU registers as containing the operands. An example is the set of
arithmetic operations where the accumulator is always implied to be the destination of the
results.
Register Indirect Addressing. This type of addressing specifies a l6-bit CPU register pair
(such as H L) to be used as a pointer to any location in memory. This type of instruction is
very powerful and it is used in a wide range of applications.
I
OP Code
I}
one or· two bytes
An example of this type of instruction would be to load the accumulator with the data in
the memory location pointed to by the HL register contents. Indexed addressing is actually
a form of register indirect addressing except that a displacement is added with indexed
addressing. Register indirect addressing allows for very powerful but simple to implement
memory accesses. The block move and search commands in the Z80 are extensions of this
type of addressing where automatic register incrementing, decrementing and comparing
has been added. The notation for indicating register indirect addressing is to put parentheses around the name of the register that is to be used as the pointer. For example, the
symbol
(HL)
specifies that the contents of the H L register are to be used as a pointer to a memory
location. Often register indirect addressing is used to specify l6-bit operands. In this case,
the register contents point to the lower Qrdet portion of the operand while the register
contents are automatically· incremented to'obtain the upper ·portion of the operand.
Bit Addressing. The Z80 contains a large number of bit set, reset and test instructions.
These instructions allow any memory location or CPU register to be specified for a bit
operation through one of three previous addressing modes (register, register indirect and
indexed) while three bits in the OP code specify which of the eight bits is to be manipulated.
ADDRESSING MODE COMBINATIONS
Many instructions include more than one operand (such as arithmetic instructions or loads).
In these cases, two types of addressing may be employed. For example, load can use immediate addressing to specify the source and register indirect or indexed addressing to
specify the source and register indirect or indexed addressing to specify the destination.
111-.26
5.3 INSTRUCTION OP CODES
This section describes each of the Z80 instructions and provides tables listing the OP codes
for every instruction. In each of these tables the shaded OP codes are identical to those
offered in the 8080A CPU. Also shown is the assembly language mnemonic that is used for
each instruction. All instruction OP codes are listed in hexadecimal notation. Single byte
OP codes require two hex characters while double byte OP codes require four hex characters.
The conversion from hex to binary is repeated here for convenience.
Hex
0
Binary
0000 =
Hex
Decimal
0
0001 =
Binary
Decimal
8
1000
8
9
1001
9
A
1010
10
11
0010 =
2
3
0011 =
3
B
1011
4
0100 =
4
C
1100
12
5
0101 =
5
D
1101
13
6
0110 =
6
E
1110
14
7
0111 =
7
F
1111
15
2
Z80 instruction mnemonics consist of an OP code and zero, one or two operands.
Instructions in which the operand is implied have no operand. Instructions which have
only one logical operand or those in which one operand is invariant (such as the Logical OR
instruction) are represented by a one operand mnemonic. Instructions which may have
two varying operands are represented by two operand mnemonics.
LOAD AND EXCHANGE
Table 5.3-1 defines the OP code for all of the 8-bit load instructions implemented in the
Z80-CPU. Also shown in this table is the type of addressing used for each instruction. The
source of the data is found on the top horizontal row while the destination is specified by
the left hand column. For example, load register C from register B uses the OP code 48H.
In all of the tables the OP code is specified in hexadecimal notation and the 48H (=0100
1000 binary) code is fetched by the CPU from the external memory during M1 time,
decoded and then the register transfer is automatically performed by the CPU.
The assembly language mnemonic for this entire group is LD, followed by the destination
followed by the source (LD DEST., SOURCE). Note that several combinations of addressing
modes are possible. For example, the source may use register addressing and the destination
may be register indirect, such as load the memory location pointed to by register H L with
the contents of register D. The OP code for this operation would be 72. The mnemonic for
this load instruction would be as follows: LD (HL), D
The parentheses around the H L means that the contents of H L are used as a pointer to a
memory location. In all Z80 load instruction mnemonics the destination is always listed
first, with the source following. The Z80 assembly language has been defined for ease of
programming. Every instruction is self documenting and programs written in Z80 language
are easy to maintain.
Note in Table 5.3-1 that some load OP codes that are available in the Z80 use two bytes.
This is an efficient method of memory utilization since 8, 16, 24 or 32 bit instructions
are implemented in the Z80. Thus often utilized instructions such as arithmetic or logical
operations are only 8-bits which results in better memory utilization than is achieved with
fixed instruction sizes such as 16-bits.
All load instructions using indexed addressing for either the source or destination location
actually use three bytes of memory with the third byte being the displacement d. For
example a load register E with the operand pointed to by IX with an offset of +8 would be
written: LD E, (IX + 8)
111-27
The instruction sequence for this in memory would be:
Address A
~D}
A+l
5F
A+2
08
P Code
Displacement operand
The two extended addressing instructions are also three byte instructions. For example
the instruction to load the accumulator with the operand in memory location 6F32H would
be written:
LD A, (6F 32H)
and its instruction sequence would be:
Address A
A+l
A+2
A
~
OPCode
32
low order address
6F
high order address
Notice that the low order portion of the address is always the first operand.
The load immediate instructions for the general purpose 8-bit registers are two-byte instructions. The instruction load register H with the value 36H would be written:
LD H, 36H
and its sequence would be:
Address A
A+l
~
OP Code
~
Operand
Loading a memory location using indexed addressing for the destination and immediate
addressing for the source requires four bytes. For example:
LD (IX - 15), 21H
would appear as:
Address A
DD
OP Code
A+l
36
A+2
Fl
A+3
21
displacement (-15 in
signed two's complement)
operand to load
Notice that with any indexed addressing the displacement always follows directly after the
OP code.
Table 5.3-2 specifies the 16-bit load operations. This table is very similar to the previous one.
Notice that the extended addressing c~ability covers all register pairs. Also notice that
register indirect operations specifying the stack pointer are the PUSH and POP instructions.
The mnemonic for these instructions is ('PUSH" and "POP". These differ from other 16-bit
loads in that the stack pointer is automatically decremented and incremented as each byte
is pushed onto or popped from the stack respectively. For example the instruction:
111-28
PUSH AF
is a single byte instruction with the OP code of F5H. When this instruction is executed the
following sequence is generated:
Decrement SP
LD (SPI, A
Decrement SP
LD (SPI, F
Thus the external stack now appears as follows:
(SPI
F
(SP+11
A
8 BIT LOAD GROUP
A
ED
EO
57
SF
111-29
Top of stack
The POP instruction is the exact reverse of a PUSH. Notice that all PUSH and POP instructions utilize a 16-bit operand and the high order byte is always pushed first and popped last.
That is a:
PUSH BC is PUSH B then C
PUSH DE is PUSH. D then E
PUSH H L is PUSH H then L
POP HL is POP
L then H
The instruction using extended immediate addressing for the source obviously requires
2 bytes of data following the OP code. For example:
LD DE, 0659H
will be:
Address A
A+1.
A+2
~
1
OP Code
59
Low order operand to register E
06
High order operand to register D
In all extended immediate or extended addressing modes, the low order byte always appears
first after the OP code.
Table 5.3-3 lists the 16-bit exchange instructions implemented in the Z80. OP code 08H
allows the programmer to switch ·between the two pairs of accumulator flag registers while
D9H allows the programmer to switch between the duplicate set of six general purpose
registers. These OP codes are only one byte in length to absolutely minimize the time
necessary to perform the exchange so that the duplicate banks can be used to effect very
fast interrupt response times.
BLOCK TRANSFER AND SEARCH
Table 5.3-4 lists the extremely powerful block transfer instructions. All of these instructions
operate with three registers.
H L points to the source location.
DE points to the destination location.
BC is a byte counter.
After the programmer has initialized these three registers, any of these four instructions may
be used. The LDI (Load and Increment) instruction moves one byte from the location
pointed to by HL to the location pointed to by DE. Register pairs HL and DE are then
automatically incremented and are ready to point to the following locations. The byte
counter (register pair BC) is also decremented at this time. This instruction is valuable when
blocks of data must be moved but other types of processing are required between each
move. The LD I R (Load, increment and repeat) instruction is an extension of the LD I
instruction. The same load and increment operation is repeated until the byte counter
reaches the count of zero. Thus, this single instruction can move any block of data from one
location to any other.
Note that since 16-bit registers are used, the size of the block can be up to 64K bytes
(1 K = 1024) long and it can be moved from any location in memory to any other location.
Furthermore the blocks can be overlapping since there are absolutely no constraints on the
data that is used in the three register pair.
The LDD and LDDR instructions are very similar to the LD I and LD I R. The only difference
is that register pairs H L and DE are decremented after every move so that a block transfer
starts from the highest address of the designated block rather than the lowest.
111-30
16 BIT LOAD GROUP 'LD' 'PUSH' AND 'POP'
SOURCE
AF
BC
DESTINATION
R
E
G
I
S
T
E
R
DE
HL
SP
IX
IV
~~:~RUCTIONS---
EXT.
ADDR.
Inn)
REG.
IND.
ISP)
pop
NOTE: The Push & Pop Instructions adjust
the SP after every execution
INSTRUCTIONS
TABLE 5.3-2
EXCHANGES 'EX' AND 'EXX'
AF
BC.
DE
&
08
09
HL
DE
REG.
INDIR.
ISP)
DO
E3
TABLE 5.3-3
111-31
FD
E3
BLOCK TRANSFER GROUP
SOURCE
'LDI' - Load (DEI-(HLI
Inc HL & DE, Dec BC
'LDIR: - Load (DEI_(HLI
Inc HL &: DE, Oec BC, Repeat until
DESTINATION
~NE~·R.
Be = 0
(DEI
'LDD' - Load (DEI_(HLI
Dec HL & DE, Dec BC
'LOOR' - Load (DEI-(HLI
Dec HL & DE, Dec BC, Repeat until Be = 0
Table 5.3-4
Reg
Hl
Reg
Reg
Be
DE
points to source
points to destination
is byte counter
Table 5.3-5 specifies the OP codes for the four block search instructions. The first, CPI
(compare and increment) compares the data in the accumulator, with the contents of the
memory location pointed to by register H L. The result of the compare is stored in one of
the flag bits (see section 6.0 for a detailed explanation of the flag operations) and the H L
register pair is then incremented and the byte counter (register pair BC) is decremented.
The instruction CPI R is merely an extension of the CPI instruction in which the compare
is repeated until either a match is found or the byte counter (register pair BC) becomes
zero. Thus, this single instruction can search the entire memory for any 8-bit character.
The CPD (Compare and Decrement) and CPDR (Compare, Decrement and Repeat) are
similar instructions, their only difference being that they decrement H L after every compare
so that they search the memory in the opposite direction. (The search is started at the
highest location in the memory block).
It should be emphasized again that these block transfer and compare instructions are
extremely powerful in string manipulation applications.
ARITHMETIC AND LOGICAL
Table 5.3-6 lists all of the 8-bit arithmetic operations that can be performed with the
accumulator, also listed are the increment (I NC) and decrement (DEC) instructions.
In all of these instructions, except INCand DEC, the specified 8-bit operation is performed
between the data in the accumulator and the source data specified in the table. The result
of the operation is placed in the accumulator with the exception of compare (CP) that
leaves the accumulator unaffected. All of these operations affect the flag register as a result
of the specified operation. (Section 6.0 provides all of the details on how the flags are
affected by any instruction type). INC and DEC instructions specify a register or a memory
location as both source and destination of the result. When the source operand is addressed
using the index registers the displacement must follow directly. With immediate addressing
the actual operand will follow directly. for example the instruction:
AND 07H
would appear as:
~
A+l~
Address A
111-32
OP Code
Operand
BLOCK SEARCH GROUP
SEARCH
LOCATION
,....--REG.
INDIR.
t-(HLI
ED
A1
ED
B1
EO
A9
ED
B9
'cpr
Inc HL, Dec BC
'CPIR'. Inc HL, Dec BC
repeat until
Be = 0
or find match
'CPD' Dec H L & BC
'CPDR' Dec HL & BC
Repeat until
Be =
0 or find match
Hl points to location in memory
TABLE 5.3-5
to be compared with accumulator
contents
Be is byte counter
Assuming that the accumulator contained the value F3H the result of 03H would be placed
in the accumulator:
Acc before operation
Operand
Result to Acc
11110011 = F3H
00000111 = 07H
0000 0011 = 03H
The Add instruction (ADD) performs a binary add between the data in the source location
and the data in the accumulator. The subtract (SUB) does a binary subtraction. When the
add with carry is specified (ADC) or the subtract with carry (SBC), then the carry flag is also
added or subtracted respectively. The flags and decimal adjust instruction (DAA) in the
Z80 (fully described in section 6.0) allow arithmetic operations for:
multiprecision packed BCD numbers
multiprecision signed or unsigned binary numbers
multiprecision two's complement signed numbers
Other instructions in this group are logical and (AND), logical or (OR), exclusive or (XOR)
and compare (CP).
There are five general purpose arithmetic instructions that operate on the accumulator or
carry flag. These five are listed in Table 5.3-7. The decimal adjust instruction can adjust for
subtraction as well as addition, thus making BCD arithmetic operations simple. Note that to
allow for this operation the flag N is used. This flag is set if the last arithmetic operation was
a subtract. The negate accumulator (NEG) instruction forms the two's complement of the
number in the accumulator. Finally notice that a reset carry instruction is not included in
the Z80 since this operation can be easily achieved through other instructions such as a
logical AND of the accumulator with itself.
Table 5.3-8 lists all of the 16-bit arithmetic operations between 16-bit registers. There are five
groups of instructions including add with carry and subtract with carry. ADC and SBC affect
all of the flags. These two groups simplify address calculation operations or other 16-bit
arithmetic operations.
111-33
8 BIT ARITHMETIC AND LOGIC
SOURCE
REG.
INDIR.
'ADD'
'AND'
'XOR'
'OR'
COMPARE
'CP.'
INCREMENT
'INC'
FD
35
DECREMENT
'DEC'
d
TABLE 5,3-6
GENERAL PURPOSE AF OPERATIONS
Decimal Adjust Ace, 'DAA'
27
Complement Ace, 'CPL'
2F
Negete Ace, 'NEG'
(2', complemend
ED
44
Complement Carry Flag, 'CCF'
3F
Set Cerry Flog, 'SCF'
37
TABLE 5.3-7
111-34
SOURCE
16 BIT ARITHMETIC
IX
'ADD'
IX
DO
09
DO
19
DO
39
IV
FD
09
FD
19
FD
39
ADD WITH CARRV AND
SET FLAGS
'ADC'
HL
ED
4A
ED
5A
ED
6A
ED
7A
SUB WITH CARRV AND
SET FLAGS
'SBC'
HL
ED
42
ED
52
ED
62
ED
72
DESTINATION
IV
DO
29
FD
29
INCREMENT
'INC.
DO
23
FD
23
DECREMENT
'DEC'
DO
28
FD
28
TABLE 5,3-8
ROTATE AND SHIFT
A major capability of the Z80 is its ability to rotate or shift data in the accumulator, any
general purpose register, or any memory location, All of the rotate and shift OP codes are
shown in Table 5.3-9. Also included in the Z80 are arithmetic and logical shift operations.
These operations are useful in an extremely wide range of applications including integer
multiplication and division. Two BCD digit rotate instructions (RRD and RLD) allow a digit
in the accumulator to be rotated with the two digits in a memory location pointed to by
register pair H L. (See Figure 5.3-9). These instructions allow for efficient BCD arithmetic.
BIT MANIPULATION
The ability to set, reset and test individual bits in a register or memory location is needed
in almost every program. These bits may be flags in a general purpose software routine,
indications of external control conditions or data packed into memory locations to make
memory utilization more efficient.
The Z80 has the ability to set, reset or test any bit in the accumulator, any general purpose
register or any memory location with a single instruction. Table 5.3-10 lists the 240 instructions that are available for this purpose. Register addressing can specify the accumulator or
any general purpose register on which the operation is to be performed. Register indirect and
indexed addressing are available to operate on external memory locations. Bit test operations
set the zero flag (Z) if the tested bit is a zero. (Refer to section 6.0 for further explanation
of flag operation).
JUMP, CALL AND RETURN
Figure 5.3-11 lists all of the jump, call and return instructions implemented in the Z80
CPU; A jump is a branch in a program where the program counter is loaded with the 16-bit
value as specified by one of the three available addressing modes 'Immediate Extended,
Relative or Register Indirect). Notice that the jump group has several different conditions
that cali be specified to be met before the jump will be made. If these conditions are not met,
the program merely continues with the next sequential instruction. The conditions are all
dependent on the data in the flag register. (Refer to section 6.0 for details on the flag
register). The immediate extended addressing is used to jump to any location in the memory.
This instruction requires three bytes (two to specify the 16-bit address) with the low order
address byte first followed by the high order address byte.
111-35
ROTATES AND SHIFTS
Source iilndDelt,nat.on
IHL)
'RLe'
'RRC'
ca
07
ca
OF
'RL'
ca
ca
00
ca
0'
ca
ca
02
ca
oa
..
ca
ca
ca
ca
OA
ca
0'
ca
oa
ca
ca
ca
ca
"
OS
08
ca
00
ca
ca
DC
ca
ca
OE
ca
TYPE
>C
OF
ROTATE
OR
SHIFT
'SlA'
ca
"
ca
3F
38
2F
'SRL'
'RLO'
'RRD'
'"
29
ca
39
2A
ca
3A
OE
~a
OE
d
d
FD
ca
d
d
~
d
06
DO
ca
FD
d
DO
ca
23
24
25
26
d
d
2a
2C
20
2E
d
d
ca
3a
ca
3C
ca
3D
2E
ca
3E
~
~
~
ca
d
08
C8
27
'SRA'
DO
ca
UV +d)
" ca" "ca ca" ca" ca" ca" DO" "FD
ca
ca
ca
CB
,.
,. ,a
,a
" "DO "FD
" ca "CB
ca
ca
ca
ca
ca
ca
ca
20
" "
DO
FD
"
"
ca
ca
ca
ca
ca
ca
CB
ca
ca
CB
"
'RR'
ox t-dl
2E
DO
ca
FD
ca
3E
3E
d
d
Rotate
L.ltC,,,;ul,.
Rotite
Righi Ciu:ullr
Rotatl
Lo"
Rotlll
Right
~o ~~~~.rithm'liC
L§]
dJ- rJ
~
L§J
ED
ShIft
RIght Amhm&tic
Sholt
Right LOgical
O~'HlI'.""Di.'
SF,
7
ED
4
3
0
Left
ACC
67
~'HlI'.""Di.'
Right
ACC
TABLE 5.3-9
For example an unconditional Jump to memory location 3E32H would be:
Address A
~3 OP Code
A+l 32 Low order address
A+2 3E High order address
The relative jump instruction uses only two bytes, the second byte is a signed two's complement displacement from the existing PC. This displacement can be in the range of +129
to -126 and is mea,sured from the address of the instruction OP code.
Three types of register indirect jumps are also included. These instructions are implemented
by loading the register pair HL or one of the index registers IX or IY directly into the"PC.
This capability allows for program jumps to be a function of previous calculations.
A call is a special form of a jump where the address of the byte following the call instruction
is pushed onto the stack before the jump is made. A return instruction is the reverse of a call
because the data on the top of the stack is popped directly into the PC to form a jump
address. The call and return instructions allow for simple subroutine and interrupt handling.
Two special return instructions have been included in the
family of components. The
return from interrupt instruction (RETJ) and the' return from non-maskable interrupt
(RETN) are treated in the CPU as an unconditional return identical to the OP code C9H.
The difference is that (R ETI) can.be used at the end of an interrupt routine and all
peripheral chips will recognize the execution of this instruction for proper control of nested
priority interrupt handling. This instruction coupled with the
peripheral devices implementation, simplifies the normal return from nested interrupt. Without this feature the
following software sequence would be necessary to inform the interrupting device that the
interrupt routine is completed:
zao
zao
zao
111-36
BIT MANIPULATION GROUP
REG.
INOIR.
REGISTER ADDRESSING
A
B
C
0
E
H
L
~HL)
INDEXED
(IX+d)
(lY+d)
DO
CB
FD
CB
45
BIT
0
I
2
3
CB
47
CB
40
Cd
CB
42
CB
43
44
CB
45
CB
41
CB
CB
49
CB
4A
CB
4B
CB
4C
CB
40
CB
4E
DO
CB
40
FD
CB
4F
CB
48
d
d
CB
CB
CB
53
CB
CB
DO
CB
4E
FD
CB
50
CB
52
CB
57
CB
51
54
55
56
d
56
CB
..
d
56
CB
59
CB
5A
CB
5B
CB
5C
CB
CB
DO
CB
5E
d
FD
CB
50
SF
TEST
'BlT'
4
CB
07
CB
CB
45
CB
CB
CB
CB
60
CB
B2
63
64
0'
66
CB
OB
CB
OC
CB
00
CB
OE
CB
74
GB
5
CB
OF
CB
CB
6B
69
CB
OA
0
CB
n
CB
70
CB
CB
71
72
CB
73
75
CB
70
7
CB
7F
CB
7B
CB
7'
CB
7A
CB
7B
CB
7C
CB
CB
7D
7E
CB
B7
CB
CB
B1
CB
B2
CB
B3
CB
CB
B,
CB
BO
0
80
84
. ..
98
99
CB
9A
CB
9B
CB
9C
CB
90
CB
9E
CB
A7
CB
CB
A1
CB
A2
CB
A3
CB
CB
AF
CB
CB
CB
AS
CB
A9
AA
CB
BO
CB
B1
CB
B2
0
1
CB
BF
CB
C7
CB
CB
BB
CB
CO
CB
B9
CB
C1
CB
B3
84
CB
B5
CB
BB
CB
BC
CB
BD
CB
C3
C8
CB
CB
BO
CB
BE
CB
CB
CB
C4
CO
CB
CB
C9
CB
07
CB
DO
CB
01
CB
02
CB
03
D4
CB
05
3
CB
OF
CB
DB
CB
D9
CB
DA
CB
DB
CB
DC
CB
DO
CB
DE
CB
CB
EO
CB
CB
E2
CB
E.
CB
E1
CB
E3
EO
CB
EO
CB
E9
CB
EA
CB
EB
CB
EC
CB
ED
CB
EE
CB
CB
F.
CB
F5
CB
FO
CB
FC
CB
FD
CB
FE
,
CB
CB
EF
CB
EB
0
CB
F7
CB
FO
CB
f1
F2
CB
F3
7
CB
CB
FB
CB
CB
FA
CB
FB
FF
F9
T AS LE 5.3-10
111-37
d
d
BE
BE
DO
CB
FD
CB
d
d
96
DO
CB
FD
CB
d
d
DO
CB
FD
CB
AB
AO
d
DO
CB
9E
d
FD
CB
d
d
AE
AE
DO
CB
FD
CB
d
d
BO
CF
E7
CB
CB
C2
CB
AE
2
4
CB
CB
BA
AS
CB
AD
CB
CA
SET
BIT
'SET'
CB
B7
d
9E
CB
AC
70
FD
CB
d
CB
AS
d
BO
FD
CB
00
A4
d
OE
FD
CB
d
CB
AD
d
00
FD
CB
DO
CB
86
CB
9'
CB
FD
CB
7E
CB
CB
A'
5E
FD
CB
CB
93
CB
9F
d
7E
CB
92
CB
d
DO
CB
CB
91
3
7
d
CB
BD
CB
0
•
'0
DO
CB
CB
BC
CB
97
5
d
OE
DO
CB
CB
BB
2
4
DO
CB
CB
BA
B8
BIT
'RES'
d
BO
CB
89
CB
RESET
DO
CB
CB
BE
CB
BF
1
84
4E
5E
CB
01
CB
d
DO
CB
BO
FD
CB
d
BE
DO
CB
FD
CB
d
CO
DO
CB
CB
CC
CB
CD
CB
CE
CB
C8
DO
CB
06
d
d
CE
DO
DO
CB
d
BE
d
CB
FD
CB
d
CE
FD
CB
d
DO
FD
CB
d
d
DE
DE
gg
FD
CB
d
d
EO
EO
DO
CB
FD
CB
d
d
DO
CB
FD
CB
EE
d
FO
DO
CB
d
FE
EE
d
FO
FD
·CB
d
FE
Disable Interrupt
- prevent interrupt before
routine is exited.
LD A, n
OUTn, A
- notify peripheral that service
routine is complete
Enable Interrupt
Return
This seven byte sequence can be replaced with the three byte EI RETI instruction sequence
in the ZBO. This is important since interrupt service time often must be minimized.
To facilitate program loop control the instruction DJNZ e can be used advantageously.
This two byte, relative jump instruction decrements the B register and the jump occurs if
the B register has not been decremented to zero. The relative displacement is expressed
as a signed two's complement number. A simple example of its use might be:
Instruction
Comments
N, N+1
LD B, 7
; set B register to count of 7
N + 2 to N + 9
(Perform a sequence
of instructions)
; loop to be performed 7 times
N + 10, N + 11
DJNZ
; to jump from N + 12 to N + 2
N + 12
(Next Instruction)
Address
-10
JUMP, CALL AND RETURN GROUP
CONDITION
JUMP
'JP'
IMMED,
EXT,
JUMP
'JR'
RELATIVE
.. 2
JUMP
'JP'
JUMP
'JP'
JUMP
'JP'
'CALL'
.. 2
0·2
REG.
INDIR.
IMMED.
EXT.
DECR EMENT B,
JUMP IF NON
ZERO'DJNZ'
RELATIVE
RETURN
'RET'
REGISTER
INDIR,
nn
NOTE-CERTAIN
FLAGS HAVE MORE
THAN ONE PURPOSE.
REFER TO SECTION
6.0 FOR DETAILS
TABLE 5.3-11
111-38
Table 5.3-12 lists the eight OP codes for the restart instruction. This instruction is a single
byte call to any of the eight addresses listed. The simple mnemonic for these eight calls is
also shown. The value of this instruction is that frequently used routines can be called with
this instruction to minimize memory usage.
RESTART GROUP
OP
CODE
C
A
L
L
A
OOOOH
C7
'RST 0'
0008H
CF
'RST8'
0010 H
D7
'RST 16'
0018H
DF
'RST 24'
D
0
R
E
S
S
,
0020 H
E1
~
'RST 32·
"
0028 H
iF
'RST 40'
0030H
F7
'RST 48'
0038 H
FF
'RST 56'
"
TABLE 5.3-12
INPUT/OUTPUT
The Z80 has an extensive set of Input and Output instructions as shown in table 5,3-13 and
table 5.3-14, The addressing of the input or output device can be either .absolute or register
indirect, using the C register. Notice that in the register indirect addressing mode data can be
transferred between the I/O devices and any of the internal registers. In addition eight block
transfer instructions have been implemented. These instructions are similar to the memory
block transfers except that they use register pair H L for a pointer to the memory source
(output commands) or destination (input commands) while register B is used as a byte
counter. Register C holds the address of the port for which the input or output command
is desired. Since register B is eight bits in length, the I/O block transfer command handles up
to 256 bytes.
In the instructions I N A, n and OUT n, A an I/O device address n appears in the lower half
of the address bus (AO-Al) while the accumulator content is transferred in the upper half
of the address bus. In all register indirect input output instructions, including block I/O
transfers the content of register C is transferred to the lower half of the address bus (device
address) while the content of register B is transferred to the upper half of the address bus.
111-39
INPUT GROUP
PORT ADDRESS
IIMMED.
n
~:~·R.
(el
[E
78
B
ED
40
e
ED
48
0
0
0
R
E
S
S
I
N
G
ED
50
E
ED
58
H
ED
60
R
E
G
INPUT'IN'
INPUT
DESTINATION
A
L
ED
68
'IN I' - INPUT &
Inc HL, Dec B
ED
A2
'INIR'-INP,lnc HL,
Dec B, REPEAT IF B*O
REG,
INDIR
ED
82
(HLI
'IND'-INPUT&
Dec HL, Dec B
ED
AA
'INDR'-INPUT, Dec HL,
Dec B, REPEAT IF B*O
ED
BA
BLoeKINPUT
>COMMANDS
TABLE 5.3-13
CPU CONTROL GROUP
The final table, table 5.3-15 illustrates the six general purpose CPU control instructions. The
NOP is a do-nothing instruction. The HALT instruction suspends CPU operation until a
subsequent interrupt is received, while the DI and E I are used to lock out and enable interrupts. The three interrupt mode commands set the CPU into any of the three available
interrupt response modes as follows. If mode zero is set the interrupting device can insert
any instruction on the data bus and allow the CPU to execute it. Mode 1 is a simplified
mode where the CPU automatically executes a restart (RST) to location 0038H so that no
external hardware is required. (The old PC content is pushed onto the stack). Mode 2 is the
most powerful in that it allows for an indirect call to any location in memory. With this
mode the CPU forms a 16-bit memory address where the upper 8-bits are the content of
register I and the lower 8-bits are supplied by the interrupting device. This address points
to the first of two sequential bytes in a table where the address of the service routine is
located. The CPU automatically obtains the starting address and performs a CALL to this
address.
Address of interrupt
service routine
{~p~inter
to Interrupt table. Reg.
I IS upper address,
Peripheral supplies lower address
111-40
OUTPUT GROUP
SOURCE
REG.
IND.
REGISTER
A
B
C
0
E
H
L
(HL)
1.~1
IMMED.
n
REG.
IND.
(C)
'OUTI' - OUTPUT
Inc HL, Dec b
REG.
IND.
(C)
ED
A3
'OTlR' - OUTPUT, Inc HL,
Dec B, REPEAT IF B*O
REG.
IND.
(C)
ED
B3
'OUTD' - OUTPUT
DecHL&B
REG.
IND.
(C)
ED
AB
'OTDR' - OUTPUT, Dec HL
& B, REPEAT IF B"'O
REG.
IND.
(C)
ED
BB
'OUT'
ED
ED
ED
ED
ED
ED
ED
79
41
49
51
59
61
69
~
PORT
DESTINATION
ADDRESS
TABLE 5.3-14
MISCELLANEOUS CPU CONTROL
'NOP'
'HALT'
DISABLE INT '(01)'
ENABLE INT '(EI)'
SET INT MODE 0
'IMOO
ED
46
8080A MODE
SET INT MODE 1
'IM1'
ED
56
CALL TO LOCATION 003B H
SET INT MODE 2
'IM2'
ED
5E
INDIRECT CALL USING REGISTER
I AND 8 BITS FROM INTERRUPTING
DEVICE AS A POINTER.
TABLE 5.3-15
111-41
BLOCK
OUTPUT
COMMANDS
111-42
6.0 FLAGS
Each of the two Z80-CPU Flag registers contains six bits of information which are set or
reset by various CPU operations. Four of these bits are testable; that is, they are used as
conditions for jump, call or return instructions. For example a jump may be desired only if
a specific bit in the flag register is set. The four testable flag bits are:
1) Carry Flag (C) - This flag is the carry from the highest order bit of the accumulator.
For example, the carry flag will be set during an add instruction where a carry from
the highest bit of the accumulator is generated. This flag is also set if a borrow is
generated during a subtraction instruction. The shift and rotate instructions also
affect this bit.
2) Zero Flag (Z) - This flag is set if the result of the operation loaded a zero into the
accumulator. Otherwise it is reset ..
3) Sign Flag(S) - This flag is intended to be used with signed numbers and it is set if
the result of the operation was negative. Since bit 7 (MSB) represents the sign of the
number (A negative number has a 1 in bit 7), this flag stores the state of bit 7 in the
accumulator.
4) Parity/Overflow Flag(PN) - This dual purpose flag indicates the parity of the result
in the accumulator when logical operations are performed (such as AND A, B) and it
represents overflow when signed two's complement arithmetic operations are performed. The Z80 overflow flag indicates that the two's complement number in the
accumulator is in error since it has exceeded the maximum possible (+127) or is
less than the minimum possible (-128) number that can be represented two's
complement notation. For example consider adding:
+120 =
+105=
0111 1000
01101001
C = 0 1110 00Q1 = -95 (wrong) Overflow has occurred;
Here the result is incorrect. Overflow has occurred and yet there is no carry to indicate an
error. For this case the overflow flag would be set. Also consider the addition of two
negative numbers:
-5 =
-16 =
C=1
11111011
11110000
11101011 = -21 correct
Notice that the answer is correct but the carry is set so that this flag can not be used as an
overflow indicator. In this case the overflow would not be set.
For logical operations (AND, OR, XOR) this flag is set if the parity of the result is even and
it is reset if it is odd.
There are also two non-testable bits in the flag register. Both of these are used for BCD
arithmetic. They are:
1) Half carry(H) - This is the BCD carry or borrow result from the least significant
four bits of operation. When using the DAA (Decimal Adjust Instruction) this
flag is used to correct the result of a previous packed decimal add or subtract.
2) Add/Subtract Flag (N) - Since the agorithim for correcting BCD operations is
different for addition or subtraction, this flag is used to specify what type of instruction was executed last so that the DAA operation will be correct for either
addition or subtraction.
111-43
The Flag register can be accessed by the programmer and its format is as follows:
D7
Is I z I X ]
D0
H
I X I P!V I N I C I
X means flag is indeterminate.
Table 6.0-1 lists how each flag bit is affected by various CPU instructions. In this table
a '. 'indicates that the instruction does not change the flag, an 'X' means that the flag goes
to an indeterminate state, an '0' means that it is reset, a '1' means that it is set and the
indicates that it is set or reset according to the previous discussion. Note that
symbol
any instruction not appearing in this table does not affect any of the flags.
t
Table 6.0-1 includes a few special cases that must be described for clarity. Notice that the
block search instruction sets the Z flag if the last compare operation indicated a match
between the source and the accumulator data. Also, the parity flag is set if the byte counter
(register pair BC) is not equal to zero. This same use of the parity flag is made with the
block move instructions. Another special case is during block input or output instructions,
here the Z flag is used to indicate the state of register B which is used as a byte counter.
Notice that when the I/O block transfer is complete, the zero flag will be reset to a zero
(Le. B=O) while in the case of a block move command the parity flag is reset when the
operation is complete. A final case is when the refresh or I register is loaded into the
accumulator, the interrupt enable flip flop is loaded into the parity flag so that the complete
state of the CPU can be saved at any time.
111-44
SUMMARY OF FLAG OPERATION
07
DO
PI
Instruction
ADD A,s; AOC A.s
SUB.s;SBCA.s;CP.s;NEG
AND s
OA s; XOA s
INC s
DECs
ADD DO, SS
ADC Hl, SS
SBC Hl, SS
AlA;ALCA; AAA;AACA
Als; AlCs; AA s; AACs;
SlAs;SAAs;SAls
AlD; AAD
DAA
CPl
SCF
CCF
IN r, (C)
INI; IND; OUTI; OUTD
INIA; INDA; OTIA; OTDA
LOI; lDD
lDI A; lDD A
CPI; CPI A; CPO; CPO A
S
Z
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
·•
··
H
X
X
X
X
X
X
X
X
X
X
X
I
I
X
X
X
X
I
X
X
I
I
X
X
X
X
X
X
X
X
X
X
X
LO A, I; lD A, A
I
I
BIT b, s
X
I
• •
• •
··
I
I
I
1
0
I
I
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
V N
V 0
V I
P 0
P 0
V 0
V I
0
V 0
V I
0
P 0
C
P
P
•
I
•
•
·
I
X
X
X
X
X
X
X
X
X
X
X
X
0
X IFF 0
X
I
X
I
I
0
X
0
X
X
0
0
•
··
P
X
X
I
0
I
X
0
•
I
0
0
0
I
I
0
0
I
0
I
I
0
0
•
•
I
I
I
I
I
Comments
S-bit add or add with carry
S-bit subtract. subtract with carry, compare and negate accumulator
} logical operations
S-bit increment
S-bit decrement
16-bit add
16-bit add with carry
16-bit subtract with carry
Rotate accumulator
Aotate and shift locations
Aotate digit left and right
Decimal adjust accumulator
Complement accumulator
I
Set carry
I Complement carry
Input register indirect
X } Block input and output
X Z =0 if B 0 otherwise Z = I
} Block transfer instructions
PIV =I if BC 0, otherwise PIV =0
Block search instructions
Z = I if A =(HL), otherwise Z =0
PIV = I if BC 0, otherwise PIV =0
The content of the interrupt enable flip-flop (I FF) is copied into
the PIV flag
The state of bit b of location s is copied into the Z flag
•
•
•
·
•
•
'*
'*
'*
The follOWing notation is used in this table:
SVMBOL
C
Z
S
PIV
H
N
•o
1
X
V
P
55
ii
R
n
nn
OPERATION
Carry/link flag. C=1 if the operation producad a carry from the MSB of the operand or result.
Zero flag. Z=1 if the result of the operation is zero.
Sign flag. 8=1 if the MSB of the result is one.
Parity or overflow flag. Parity (P) and overflow (V) share the same flag. Logical operations affect this flag
with the parity of the result while arithmetic operations affect this flag with the overflow of the result.
If PIV holds parity, PN=1 if the result of the operation is evan, PN=O if result i. odd. If PIV holds over·
flow, P/V=1 if the result of the operation producad an ovarflow.
Half·carry flag. H=1 if the add or subtract operation produced a carry into or borrow from bit 4 of the
accumulator.
Add/Subtract flag. N-1 if the previous operation was a subtract.
Hand N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the
result into peckad BCD format following addition or subtrection using operands with packed BCD format.
The flag is affectad according to the result of the operation .
The flag is unchanged by the operation.
The flag is reset by the operation.
The flag is set by the operation.
The flag is a "don't care".
P/V flag affectad according to the overflow result of the operation.
PN flag affected according to the parity result of the operation.
Anyone of the CPU registers A, B, C, D, E, H, L.
Any S·bit location for all the addressing modes allowed for the panicular instruction.
Any 16-bit location for all the eddressing modes allowed for that instruction.
Anyone of the two index registers IX or IV.
Refresh counter.
S·bit value in range
16-1>it value in range
TABLE 6.0-1
111-45
111-46
7.0 SUMMARY OF OP CODES AND EXECUTION TIMES
The following section gives a summary of the Z80 instruction set. The instructions are
logically arranged into groups as shown on Tables 7.0·1 through 7.0-11. Each table shows
the assembly language mnemonic OP code, the actual OP code, the symbolic operation,
the content of the flag register following the execution of each instruction, the number
of bytes required for each instruction as well as the number of memory cycles and the
total number of T states (external clock periods) required for the fetching and execution
of each instruction. Care has been taken to make each table self-explanatory without
requiring any cross reference with the text or other tables.
111-47
a·BIT LOAD GROUP
• •
•
X
X
Flags
H
P/V N
X
X
• •
•
X
X
•
X
X
·
r -(lY+d)
• •
X
•
X
• • •
La (HLi,r
LD (lX+d), r
(HLi-r
(lX+d)-r
• •
• •
X
X
•
•
X
X
• • •
• • •
LD IIY+d), r
(lY+d)-r
• •
X
•
X
• • •
LD (HLi, n
(H Li- n
• •
X
•
X
• • •
LD (lX+d), n
IIX+d)-n
• •
X
•
X
• • •
LD r, 5
LD r, n
Symbolic
Operation
r-s
r-n
LD r, (HLi
LD r, (IX+d)
r -(HLi
r -(IX+d)
LD r, (lY+d)
Mnemonic
S
·•
Z
• •
La (lY+d), n
(IY+d)-n
LD A, (BG)
LD A, (DE)
LD A, (nn)
A-(BC)
A-(OE)
A-(nn)
• •
LD (BC), A
LD (DE), A
La (nn), A
(BC)-A
(DE)-A
(nn)-A
La A,I
A-I
I
La A, R
A-R
I
La I, A
I-A
LD R, A
R-A
X
• • •
• • •
•
·•
•
Op·Code
C 76 543 210
5
01 r
00 r 110
n
01 r 110
11 011 101
01 r 110
d
11 111101
01 r 110
d
01 110 r
11 011101
01 110 r
d
11 111101
01 110 r
-d
00 110110
- n
11 011 101
00 110110
- d
- n
11 111 101
00 110110
- d
- n
00 001010
00 011010
00 111 010
- n
- n
00000010
00 Gl00l0
00110010
n
- n
11 101101
01 010111
11 101101
01 011111
11 101101
01 000111
11 101101
01 001111
X
• • •
• •
-
-
-
-
-
-
-
-
-
Notes:
• •
• •
X
X
X
•
•
•
X
X
X
• • •
• • •
• • •
• •
•
• •
X
X
X
•
X
X
X
• • •
•
•
• • •
I
X
0
X IFF
0
•
I
X
0
X IFF
0
•
• •
• •
X
•
X
• • •
X
•
X
• • •
· ·•
·
-
-
-
-
-
-
.= flag not affected, 0 =flag reset, 1 =flag set, X =flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0·'
111·48
No. of M
Cycles
1
2
No. of T
States
4
7
1
3
2
5
7
FD
3
5
19
1
3
2
DD
5
7
19
FD
3
5
19
36
2
3
10
DD
36
4
5
19
FD
36
4
5
19
OA
lA
3A
1
1
3
2
2
4
7
02
12
32
1
1
3
2
2
4
7
ED
57
ED
5F
ED
47
ED
4F
2
2
9
2
2
9
2
2
9
2
2
9
r, 5 means any of the registers A, B, C, D, E, H, L
IFF the cORtent of the interrupt enable flip·flop II FF) is copied into the P/V flag
Flag Notation:
No. of
Bytes
1
2
DD
-
-
• • •
He.
19
7
13
7
13
Comments
r,s
Reg.
B
000
001
C
D
010
E
011
100
H
L
101
A
111
1S-BIT LOAD GROUP
Mnemonic
LD dd. nn
Symbolic
Operation
dd - nn
LD IX, nn
IX - nn
LD IY, nn
IY - nn
LD HL, Inn)
H - Inn+1I
L - Inn)
LD dd, Inn)
ddH -lnn+1)
dd L -Inn)
LD IX, Inn)
IXH- Inn+1)
IXL -Inn)
LD IY, Inn)
I IYH-Inn+1)
IYL -Inn)
LD Inn), HL
(nn+l) - H
Inn) - L
LD Inn), dd
Inn+1) - ddH
Inn)-ddL
LD Inn), IX
Inn+l) - IXH
Inn)-IXL
LD Inn), IY
Inn+1) - IYH
Inn) -IYL
LD SP, HL
LD SP, IX
SP - HL
SP - IX
LD SP, IY
SP - IY
PUSH qq
ISP,2i - qqL
ISp·1) - qqH
ISp·2i - IXL
ISp·1) - IXH
ISp·2i - IYL
ISp·1) - IYH
qqH- ISP+1)
qqL -ISPI
IXH -ISP+1)
IXL -ISPI
IYH -ISP+1)
IYL -ISPI
PUSH IX
PUSH IY
PDP qq
tlop IX
PDP IY
S
X
FI gs
H
PIV
X
X
X
X
X
•
X
X
·
X
X
•
X
X
X
X
X
X
X
X
X
X
Z
Op-Code
N
C
76 543 210
•
•
00 ddO
n
n
11 011
00 100
n
n
11 111
00 100
n
n
00 101
n
n
11 101
01 ddl
n
n
11 011
00 101
n
n
11111
00 101
n
n
00 100
n
n
11 101
01 ddO
n
n
11 011
00 100
n
n
11 111
00 100
n
n
11111
11 all
11111
11111
11111
11 qqO
· · ·
• •
•
·•
• ·
· ··
• •
· ••
• •
•
··
·• • ··
• ·
· ··
• •
•
·•
·· · • •
• •
•
··
• ·
•
··
·· ·· ·•• ·• ·••
·· • ·•
··
·
· · ·• • ••
·• ·• • ·
··
·· · • ·
·· · ··
•
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
----
·· -· --•
•
---
·•
•
·
·•
·
·
·
·
001
-- --
·-
-
No. 01
Bytes
3
DO
21
4
4
14
101
001
FD
21
4
4
14
010
2A
3
5
16
101
011
ED
4
6
20
101
010
DO
2A
4
6
20
101
010
FD
2A
4
6
20
010
-101
011
--
22
3
5
16
ED
4
6
20
101
010
DO
4
6
101
22
4
6
20
010
22
001
101
001
101
001
101
F9
DO
F9
FD
F9
1
2
1
2
6
10
DO
E5
FD
E5
----
-
---
--
101
101
101
101
001
11
11
11
11
011
100
111
100
101
001
101
001
FD
"
20
2
2
10
1
3
11
2
4
15
2
4
15
1
3
10
DO
2
4
14
El
FD
El
2
4
14
dd is any of the register pairs BC, DE, HL, SP
qq is any of the register pairs AF, BG. DE, HL
IPAI R)H, IPAI RI L refer to high order and low order eight bits of the register pair respectively.
e.g. BGL = G, AFH = A
Flag Notation: • =flag not affected, 0 = flag reset, 1 = flag set, X =flag is unknown,
I flag is affected according to the result of the operation.
111-49
Comments
Pair
dd
Be
00
01
DE
10
HL
11
SP
-
011
100
111
100
qqO
Table 7.0-2
No.oIM No. ofT
Cycles States
10
3
101
001
11
11
11
11
11
Notes:
Hex
qq
00
01
10
11
Pair
BC
DE
HL
AF
EXCHANGE GROUP AND BLOCK TRANSFER AND SEARCH GROUP
Mnemonic
EX,DE,HL
EX AF,AF'
EXX
Symbolic
Operation
DE7"HL
AF-AF~
S
Z
,.
FI s
H
PlY
• X
• X •
X
E3
1
5
19
011 101
100 011
111 101
11 100011
DO
E3
FD
E3
2
6
23
2
6
23
•
•
X
•
X
• • •
X
•
X
•
X
•
X
• • • 11
,11
11
•
· .'
'
(1)-
• •
LDO
(DEJ-(HU
DE - DE-I
HL - HL-l
BC - BC-l
• •
X
0
X
LDOR
(DEJ-(HU
DE - DE-I
HL - HL-l
BC -BC·l
Repeat until
BC= 0
• •
X
0
CPI
A - (HU
HL-HL+l
BC - BC-l
I
X
A - (HU
HL - HL+l
BC-BC-l
Repeat until
A=(HUor
BC = 0
I
CPD
A - (HU
HL -HL-l
BC-BC·l
I
CPDR
A- (HL)
HL - HL-l
BC - BC-l
Repeat until
A=(HUor
BC= 0
I
X
0
X
I
11 100 011
No. ofT
StItes Comments
0
•
11 101 101
10 100 000
ED
AD
2
4
16
0
•
11 101 101
10110000
ED
BO
2
2
5
4
21
16
"
X
0
X
I
X
•
11 101 101
10 101 000
ED
A8
2
4
16
X
0
0
•
11 101 101
10 111 000
ED
B8
2
2
5
4
21
16
I
X
CD
I
1
.~1 101 101
ED
Al
2
4
16
10 100 001
I
X
11 101101
10 110 001
ED
Bl
2
2
5
4
21
16
X
I
X
X
I
X
@
I
CD
I
1
CD
@
I
CD
0
@
I
0
t
@
CD
4
4
4
•
(DEJ-(HU
DE - DE+l
HL - HL+l
BC -BC-l
Repeat until
BC= 0
Notes:
No.ofM
Cycles
1
1
1
• • •
• •
• • •
• •
CPIR
No. of
Bytes
1
1
1
X
X
X
(DEJ-(HU
DE - DE+l
HL - HL+l
BC - BC-l
LDIR
Hex
EB
08
09
• •
•
• •
(BC-SC)
DE-DE'
HL-HL'
EX (SP), HL H -(SP+l) •
L -(SP)
EX (SP), IX IXH-lSP+l) •
IXL -lSP)
EX (SP), IY IYH -iSP+lI •
IYL -lSP)
LDI
Op·Code
C 76 543 210
11 101,011
~OOOI 000
11 011 001
N
I
CD
I
•
1
•
11101 101
10 101 001
ED
A9
2
4
16
1
., 11 101 101
10 111 .001
ED
B9
2
2
5
4
21
16
PIV flag is 0 if the result of BC-l = 0, otherwise PIV = 1
@ Z flag is 1 if A = (HL), otherwise Z = O.
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0-3
III-50
Register bank and
auxiliary register
bank exchange
Load (HU into
(DEI. increment the
pointers and
decrement the byte
cou nter (B C)
If BC4 0
If BC = 0
If BC4 0
If BC = 0
If BC 40 and A¥(HU
IfBC=OorA=(HU
If BC #Oand A 1- (HU
IfBC=OorA=(HL/
8-BIT ARITHMETIC AND LOGICAL GROUP
Symbolic
Operation
Fla s
H
Mnemonic
ADO A, r
ADO A, n
A - A+r
A - A+n
I
I
I
I
X
X
I
I
X
X
ADO A, (HL)
ADO A, (lX+d)
A - A+(HL)
A-A+(lX+d!
I
I
I
I
X
X
I
I
X
X
Z
5
.-~
Op·Code
C 76 543 210 Hex
No.of No.ofM No.ofT
Bytes Cycles States Comments
0
0
I 10 iQ2Q] r
1
2
1
2
4
7
0
0
I 10 iQ2Q]110
I 11 011 101
00
1
3
2
5
7
19
10 iQ2Q] 11 0
d
I 11 111 101
10 [QQQJll0
!- d
FD
3
5
19
PIV
N
V
V
V
-if
I
A-A+(lY+d)
I
I
X
I
X
V
0
ADC A, s
SUB s
SBC A, s
AND s
DRs
XOR s
CP s
INC r
INC (HL)
INC (IX+d)
A-A+s+CY
A-A·s
A-A·s· CY
A-A. ,
A-A v s
A-A (!) s
A·s
r - r+ 1
(HLHHL)+l
(lX+d) (lX+d)+l
I
I
I
I
t
I
I
Xi
X
X
X
X
X
X
X
X
X
I
X
X
X
X
X
X
X
X
X
X
V
V
V
P
P
P
V
V
V
V
0
1
1
0
0
0
1 :
0
0 ~
0
•
INC (IY+d)
(lY+d) (lY+d)+l
I
I
X
I
X iV
0
•
DECs
s -s·l
I
I
X
I
X
I
IV
1
•
I
II
I
I
I
I
I
I
i
I
I
j
I
I
j
;
I
1
0
0
I
j
t
i
- -
-
ADO A, (lY+d)
I
I
lliQ2Q]110
n
I
I II
I
0
0
0
I
I
[QIDJ
lQI[J
-
[QTIJ
AD 0 instruction.
I~
I·. ioo
,The indicated bits
Ireplace the [g]QJ in
the AD 0 set above.
[!JJJ
00
r [qQJ
110[qQJ
111 011 101 i
iOO 110[qQJ!
,_ d _
111 111 101
100 110[qQJ
,-
d
I
DO
1
1
3
1
3
6
4
11
23
FD
3
6
23
I
I
Notes:
The V symbol in the PIV flag column indicates that the PIV flag contains the overflow of the result of the
operation. Similarly the P symbol indicates parity. V = 1 means overflow, V = 0 means not overflow, P = 1
means parity of the result is even, P = 0 means parity of the result is odd.
Flag Notation:
• =flag not affected, 0 = flag reset, 1 =flag set, X =flag is unknown.
I = flag is affected according to the result of the operation.
Table 7.04
III-51
I
I
-
[QIJ
I
Reg.
B
C
0
E
H
L
A
s is any of r, n,
(HL), (IX+d),
(lY+d) as shown for
[[[J
I
r
000
001
010
011
100
101
111
Is is any of r, (H L),
(IX+dl, (lY+d) as
Ish own for INC.
DEC same format
and states as INC.
Replace [j]QJ with
[[j] in 0 P Code.
GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
CP L
Symbolic
Operation
S
Converts acc. I
content into
packed BCD
following add
or subtract
with packed
BCD operands I
A- A
NE G
A - A+ 1
I
CC F
CY-Cy
M nemonic
OA A
CY -1
No operation
CPU halted
IFF - 0
IFF - 1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2
..
EI
1M 0
1M 1
1M 2
Notes:
I
X
Flags
H
P/V
I X p
N
·
Op-Code
C 76 543 210
Hex
I 00 100 111 27
No.ofM No.of T
Cycles
States
1
4
Comments
Decimal adjus-t~
accumulator
i
X
1
X
· ·
I
X
I
X
V
1
I
• •
X
X
X
•
0
I
•
•
•
•
•
•
•
•
•
•
•
•
X
X
X
X
X
X
• •
X
• •
X
0
•
•
X
X
X
X
X
X
1
•
•
•
•
•
X
2F
1
1
4
111 101 101
101 000 100
00 111 111
ED
44
3F
2
2
8
1
1
4
37
00
76
F3
FB
ED
46
ED
56
ED
5E
1
1
1
1
1
2
1
1
1
1
1
2
4
4
4
4
4
8
2
2
8
2
2
8
I
0
•
•
•
•
•
1 100
00
01
11
11
11
01
11
01
11
01
•
•
•
•
•
··• ·
•
• • •
•
• · •
X
100 101 111
110
000
110
110
111
101
000
101
010
101
011
111
000
110
011
011
101
110
101
110
101
110
I FF indicates the interrupfenable flip-flop
CY indicates the carry flip-flop.
Flag Notation:
No_ of
Bytes
1
:
··
SC F
NO P
HA LT
01
Z
•
=flag not affected, 0 = flag
I
= flag
reset, 1 = flag set, X = flag is unknown,
is affected according to the result of the operation.
*Interrupts are not sampled at the end of EI or 01
Table 7.0-5
III-52
Complement
accumulator
( One's complementl
Negate acc, (two's
complementl
Complement carry
flag
Set carry flag
16-BIT ARITHMETIC GROUP
Mnemonic
ADDHL.ss
Symbolic
Operation
HL - HL+ss
• •
X
FI gs
H
P/V N
X X
0
ADC HL, ss
HL - HL+ss+CY
I
X
X
S
Z
I
•
X
V
0
Op·Code
C 76 543 210 Hex
I 00 ssl 001
I 11 101 101
ED
No.of No.ofM No.ofT
Bytes Cycles States Comments
Reg.
1
11
ss
3
BC
00
15
01
DE
2
4
10
HL
SP
11
4
15
2
DD
2
4
15
FD
2
4
15
1
2
1
2
6
2
2
10
1
2
1
2
6
2
2
10
ED
01 551 010
SBCHL,ss
HL - HL·ss·CY
ADD IX, pp
ADD IY,rr
I
I
X
X
X
V
1
I
IX -IX+pp
• •
X
X
X
•
0
I
IY -IY+rr
• •
X
X X
•
0
I 11111 101
ss - Ss+ 1
IX - IX+l
• •
• •
X
X
•
•
X
X
• • •
• • •
INC IY
IY - IY+l
• •
X
•
X
• • •
ss_ss·1
IX - IX· 1
DECIY
IY -IY·l
Notes:
• •
• •
• •
101
ssO
011
ppl
101
010
101
001
00 rrl 001
INCss
INC IX
DECss
DECIX
11
01
11
00
X
X
•
•
X
X
X
•
X
• • •
• • •
• • •
00 ssO
11 011
00 100
11 111
00 100
00 ssl
11 011
00 101
11111
00 101
011
101
011
101
011
011
101
011
101
011
ss is any of the register pairs BC, 0 E, HL, SP
pp is any of the register pairs BC, DE, IX, SP
rr is any of the register pairs BC, DE, IY, SP.
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown.
I = flag is affected according to the result of the operation.
Table 7.0·6
III-53
DO
23
FD
10
23
DO
2B
FD
2B
10
pp
00
01
10
11
rr
00
01
10
11
Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP
ROTATE AND SHIFT GROUP
Symbolic
FI gs
Op·Code
PI
Mnemonic
RLCA
Operation
[rnL[I3J
S
Z
• •
H
X
0
X
V
N C 76543210
•
0
I
00 000 111
No.of No.of No.of
M
T
Hex Bytes Cycles States Comments
07
1
1
4
A
RLA
L!m---rE::ID-~
• •
X
0
X
•
0
I
00 010 111
17
1
1
4
• •
X
0
X
•
0
I
00 001 111
OF 1
1
4
A
RRCA
~
A
RRA
~
X
0
X
•
0
j 00 011 111
1 F il
1
4
Rotate right
accumulator
X
0
j 11
00
I 11
00
001 011
[QQQl r
001 011
~ 110
CB 12
2
8
CB :2
4
15
DO !4
CB
6
23
Rotate left circular
register r
r
Reg.
B
000
001
C
0
010
011
E
100
H
101
L
111
A
FD
CB
6
23
j
I
X
p
0
RLC(HLI
j
I X 0 X
P
0
j
I X 0 X P 0 j 11 011 101
r,(H LI,(lX+d),(lY+d)
RLC (lY+d)
11 001 011
d
00 &QQlll0
-
j
-
I X 0 X P 0 I 11 111 101
11 001 011
d
00 [QQQlll0
-
-
Lril-i§]J
\
\ X
I
[QIQ]
RRCs
lit3=4m
s =r,(HLI,(IX+d),(IY+d)
j
I X 0 X P 0 I
IQID]
RRs
lI7-01_W
s =r,IH LI,(lX+d),(lY+d)
I
I X 0 X p 0 I
IQ!jJ
RLs
0
X
P
0
I
I
I
Instruction format and
states are as shown for
RLC's. To form new
Op·Code replace lQ.Qill
of RLC's with shown
code
s =r,(HLI,(lX+d),(lY+d)
SLAs
I I
X
0
X
P
0
I
[j]Q]
I
I
X
0
X
P
0
I
[ill]
I
I
X
0
X
p
0
I
IITIl
RLD
A~(HL I I
X
0
X
p
0
• 11 101 101
01 101 111
ED 12
6F
5
18
RRD
A~(HL) I I
X
0
X
P
0
• 11 101 101
01 100 111
ED 12
67
5
18
SRAs
0-17-01-0
s =r,(HLI,(lX+d),(lY+d)
[j-Ol-lill
Rotate right circular
• •
RLC r
~
Rotate left
accumulator
accumulator
A
RLC (IX+d)
Rotate left circular
accu mulator
s =r,(H LI,(lX+d),(lY+d)
SRLs
0-!7-01-ru
s =r,(HLI,(IX+d),(lY+d)
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 1.0·7
III-54
Rotate digit left and
right between the
accumulator
and location (H LI.
The content of the
upper half of the
accu mulator is
unaffected
BIT SET, RESET AND TEST GROUP
Flags
H
P/V
X 1 X X
0
I
X
1
X
X
a
I
X
1
X
X
a
Mnemonic
BIT b, r
Symbolic
Operation
Z - rb
S Z
X I
BIT b, IHU
Z - (HUb
X
BIT b, (IX+dlb
Z - {/X+d)b
X
Op·Code
N
Hex
CB
No. of No.ofM No-ofT
Bytes Cycles States
2
2
8
CB
2
3
12
DO
CB
4
5
20
11 111 101
11 001 011
d
01 b 110
FO
CB
4
5
20
11 001
[j]b
11 001
[j]b
11 011
11 001
d
[j]b
11 111
11 001
d
[j] b
CB
2
2
8
CB
2
4
15
DO
CB
4
6
23
FO
CB
4
6
23
C 76
• 11
01
• 11
01
• 11
11
-
01
BIT b, (IY+dlb
Z - (IY+d1b
X
I
X
1
X
X
a
•
543 210
001
b
001
b
all
001
d
b
-
SET b, r
Irb - 1
SET b, (HU
(HUb - 1
SET b, {/X+dl
(lX+dlb - 1
SET b, (lY+dl
(lY+dlb - 1
·•
• •
·•
• •
X
•
X
• • •
X
•
X
• • •
X
•
X
• • •
-
X
•
X
• • •
-
AES b, s
sb - a
s=r,(HU,
{/X+dl,
{/Y+dl
-•
x
•
x
all
r
all
110
101
011
-
110
-
011
r
011
110
101
all
+
110
101
011
-
110
• • -/lID
I
Notes:
The notation sb indicates bit b (0 to 71 or location s.
Flag Notation:
• = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0-8 "
III-55
Comments
Aeg.
r
B
000
001
C
0
010
all
E
H
100
101
L
111
A
Bit Tested
b
000
a
001
1
010
2
3
all
4
100
101
5
110
6
111
7
To form new Op·
Code replace [j]
of SET b, s with
[)]]. Flags and time
states for SET
instruction
JUMP GROUP
Symbolic
Operation
Mnemonic
JP nn
PC - nn
S
Z
• •
X
Flags
H
X
•
PIV
N
Op-Code
C 76 543 210 Hex
11 000 otl
C3
n
n
11 cc 010
n
n
• • •
JP cc, nn
If condition cc
is true PC - nn,
otherwise
continue
• •
X
•
X
• • •
JR e
PC - PC + e
•
e-
X
X
• • •
JR C, e
• •
X
X
• • •
JP (HL)
If C = 0,
continue
If C = I,
PC - PC+e
If C= I,
continue
If C= 0,
PC - PC+e
If Z= 0
continue
If Z= I,
PC - PC+e
If Z= I,
continue
If Z = 0,
PC - PC+e
PC - Hl
•
•
• •
X
JP (IX)
PC - IX
• •
JP (IV)
PC - IV
DJNZ, e
B - B·l
If B = 0,
continue
JR NC, e
JR Z, e
JR NZ, e
• •
• •
• •
X
X
X
•
•
•
X
X
X
• • •
• • •
• • •
--
-
--
00
00
-
-
00 110 000
- e·2
18
2
3
12
111
38
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
2
2
7
If condition not met
2
3
12
If condition is met
00 101 000
- e-2
28
-
20
X
• • •
11 101 001
E9
1
1
4
X
•
•
X
• • •
8
•
X
• • •
DO
E9
FD
E9
2
X
101
001
101
001
2
• •
11
11
11
11
2
2
8
• •
X
•
X
• • •
00 010 000
- e·2
10
2
2
8
If B = 0
2
3
13
If BjO
011
101
111
101
-
If BjO,
PC - PC+e
Notes:
10
30
00 100 000
- e·2
Condition
NZ non zero
Z zero
NC non carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative
3
-
-
cc
000
001
010
011
100
101
110
3
--
011 000
e-2
111 000
e-2
No_of No.ofM No.ofT
Bytes Cycles States Comments
3
10
3
e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range <126, 129>
e·2 in the op-code provides an effective address of pc+e as PC is
incremented by 2 prior to the addition of e.
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7.0-9
III-56
CALLAND RETURN GROUP
Symbolic
Operation
S
(Sp·l) - PCH
(SP·21 - PCl
PC - nn
Mnemonic
CAll nn
CALL cc, nn If condition
cc is false
Flags
H
Z
PV N
• •
X
•
X
•
• •
X
•
X
•
Op·Code
C 76 543 210 Hex
11 001 101 CD
n
n
·•·•-
11 cc 100
n
n
otherwise
same as
CAll nn
PCl - (SPI
PC H - (SP+ll
RET cc
If condition
cc is false
continue,
otherwise
same as
RET
RETI
Return from
interrupt
Return from
non maskable
RETNI
-.-
-
continue,
RET
--
·• · ·•
• ·
•
• •
X
X
•
X
X
• 111 cc 000
11 001 001
C9
No. of No.ofM No.of T
Bytes Cycles States Comments
3
5
17
3
3
10
If cc is false
3
5
17
If cc is true
1
3
10
1
1
5
If cc is false
1
3
11
If cc is true
cc
Condition
000 NZ non zero
zero
001 Z
010 NC non carry
carry
011 C
parity odd
100 PO
parity even
101 PE
sign positive
110 P
sign negative
111 1M
i
• •
X
•
X
• •
·•
X
•
X
•
• •
X
•
X
• •
• 111
101
111
101
101
001
101
000
101
101
101
101
• 111
t
111
·•
ED
40
ED
45
2
4
14
2
4
14
1
3
11
interrupt
RST p
(Sp·ll (SP·21 PCH PCl -
PCH
PCl
0
P
t
000
001
010
011
100
101
110
111
i
1 RETN loads IFF2 - IFFI
=flag not affected, 0 =flag reset, 1 =flag set, X =flag is unknown,
I = flag is affected according to the result of the operation.
Flag Notation: •
Table 7.0·10
III-57
P
OOH
08H
10H
18H
20H
28H
30H
38H
INPUT AND OUTPUT GROUP
Mnemonic
IN A, (n)
Symbolic
.operation
A • (n)
• •
IN r, (C)
r - (C)
if r = 110 only
the flags will
be affected
I
INI
(HU - (C)
B - B·l
HL-HL+l
(HU - (C)
8 - 8·1
HL-HL+l
Repeat until
8=0
X
INIR
INO
I X
.
I 'X
p
0
N
Op·Code
C 76 543 210 Hex
• 11 011 011 DB
n
• 11 101 101 ED
01 r 000
No.of No.ofM No.of T
Bytes Cycles States
2
3
11
2
3
12
-
-
Comments
n to AO - A7
Ace to AS - A15
Cto AO - A7
B to AS - A15
I
X
X X
X
1
X 11 101 101
10 100 010
ED
A2
2
4
16
Cto AO - A7
Bto AS - A15
X 1
X
X
X
1
X 11 101 101
10 110 010
ED
82
2
21
5
(If B 10)
4
16
(If 8 = 0)
Cto AO - A7
8 to AS - A15
X
2
CD
OUr (n), A
OUT (C), r
(C) - r
OUTI
8 - B·l
(C) - (HLr
HL-HL+l
B - 8·1
(C) - (HU
HL- HL+l
Repeat until
B=O
X
(C) - (HU
B - B·l
HL-HL·l
Ie) - (HU
B - B·l
HL-HL·l
Repeat until
B=O
X
OTiR
X
FI gs
PV
H
• X •
lCD
(HL) - (C)
8 - 8·1
HL-HL·l
(HU - (C)
B - B· 1
HL - HL·l
Repeat until
B=O
(n)-A
INOR
Z
S
XI
I X X X X
X 1
X X
X
1
X
11 101 101
10 101 010
ED
AA
2
4
16
eta AO - A7
B to AS - A15
1
X 11 101 101
10 111 010
ED
BA
2
5
21
(If B 10)
4
16
(If B = 0)
Cto AO - A7
B to AS - A15
n to Ao - A7
Ace to AS - A15
Cto AO - A7
8 to AB - A15
2
• •
• •
X
•
X
X
•
X
• • •
• • •
11 010 011
03
2
3
11
11 101 101
01 r 001
ED
2
3
12
X 11 101 101
ED
A3
2
4
16
Cto AO - A7
Bto AS - A15
ED
B3
2
5
21
(If B1 0)
4
16
If 8 = 0)
Cto AO - A7
Bto AS - A15
CD
X
I X X X X
1
1
1
X
X
X
X
10 100 011
X 11 101 101
10 110 011
2
'CD
aUTO
OTOR
Notes:
CD
I X X
X 1
X
X
X X
X
X
1
X 11 101 101
1 'x
ED
AB
2
4
16
10 101 011
Cto AO - A7
Bto AS - A15
11 101' 101
'10,111011
ED
BB
2
5
21
(If B 10)
4
16
(If 8 = 0)
CtoAo-A7
Bto AS - A15
2
If the result of B• 1 is zero the Z flag is set, otherwise it is reset.
Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,
I = flag is affected according to the result of the operation.
Table 7 ..0·11
III-58
B.O INTERRUPT RESPONSE
The prupose of an interrupt is to allow peripheral devices to suspend CPU operation in an
orderly manner and force the CPU to start a peripheral service routine. Usually this service
routine is involved with the exchange of data, or status and control information, between
the CPU and the peripheral. Once the service routine is completed, the CPU returns to the
operation from which it was interrupted.
INTERRUPT ENABLE - DISABLE
The ZBO-CPU has two interrupt inputs, a software maskable interrupt and a non-maskable
interrupt. The non~maskable interrupt (KIlIIIT) can not be disabled by the programmer and
it will be accepted whenever a peripheral device requests it. This interrupt is generally
reserved for very important functions that must be serviced whenever they occur, such as
an impending power failure. The maskable interrupt (INTI can be selectively enabled or
disabled by the programmer. This allows the programmer to disable the interrupt during
periods where his program has timing constraints that do not allow it to be interrupted.
In the ZB~CPU there is an enable flip flop (called IFF) that is set or reset by the programmer using the Enable Interrupt (EI) and Disable Interrupt (01) instructions. When the
IFF is reset, an interrupt can not be accepted by the CPU.
Actually, for purposes that will be subsequently explained, there are two enable flip flops,
called IFF1 and IFF2.
Actually disables interrupts
from being accepted.
Temporary storage location
for IFF.,.
The state of IFF, is used to actually inhibit interrupts while IFF2 is used as a temporary
storage location for IFF,. The purpose of storing the IFF, will be subsequently explained.
A reset to the CPU will force both IFF 1 and IFF2 to the reset state so that interrupts are
disabled. They can then be enabled by an EI instruction at any time by the programmer.
When an EI instruction is executed, any pending interrupt request will not be accepted until
after the instruction following EI has been executed. This single instruction delay is necessary for cases when the following instruction is a return instruction and interrupts must not
be allowed until the return has been completed. The EI instructions sets both IFF, and
IFF2 to the enable state. When an interrupt is accepted by the CPU, both IFF1 and IFF2
are automatically reset,inhibiting further interrupts until the programmer wishes to issue a
new E I instruction. Note that for all ofthe previous cases, IFF, and IF F2 are always equal.
The purpose of IFF2 is to save the status of IFF, when a non-maskable interrupt occurs.
When a non-maskable interrupt is accepted, IFF, is reset to prevent further interrupts
until reenabled by the programmer. Thus, after a non-maskable interrupt has been accepted
maskable interrupts are disabled but the previous state of IFF, has been saved so that the
complete state of the CPU just prior to the non-maskable interrupt can be restored at any
time. When a Load Register A with Register I (LD A, I) instruction or a Load Register A
with Register R (LD A, R) instruction is executed, the state of I FF2 is copied into the
parity flag where it can be tested or stored.
A second method of restoring the status of IFF, is thru the execution of a Return From
Non-Maskable Interrupt (RETN) instruction. Since this instruction indicates that the non
maskable interrupt service routine is complete, the contents of IF F2 are now copied back
into IFF" so that the status of IFF, just prior to the acceptance of thenon-maskable
interrupt will be restored automatically.
III-59
Figure 8.0-1 is a summary of the effect of different instructions on the two enable flip flops.
INTERRUPT ENABLE/DISABLE FLIP FLOPS
Action
o
o
o
LDA,R
•
•
•
•
Accept NMI
o
•
IFF2
•
o
0
•
•
CPU Reset
Dl
o
EI
LDA,I
RETN
Accept INT
RETI
FIGURE 8.0-1
IFF2 ~Parity flag
IFF 2 ~ Parity flag
". "indicates no change
CPU RESPONSE
Non-Maskable
A non-maskable 'interrupt wi" be accepted at a" times by the CPU. When this occurs, the
CPU ignores the next instruction that it fetches and instead does a restart to location
0066H. Thus, it behaves exactly as if it had received a restart instruction but, it is to a
location that is not one of the 8 software restart locations. A restart is merely a call to a
specific address in page 0 memory.
Maskable
The CPU can be programmed to respond to the maskable interrupt in anyone of three
possible modes.
Mode 0
This mode is identical to the 80S0A interrupt response mode. With this mode, the interrupting device can place any instruction on the data bus and the CPU will execute it. Thus, the
interrupting device provides the next instruction to be executed instead of the memory.
Often this wi" be a restart instruction since the interrupting device only need supply a
single byte instruction. Alternatively, any other instruction such as a 3 byte call to any location in memory could be executed by issuing a restart to the 3 byte op code.
The number of clock cycles necessary to execute this instruction is 2 more than the normal
number for the instruction. This occurs since the CPU automatically adds 2 wait states to an
interrupt response cycle to allow sufficient time to implement an external daisy chain for
priority control. Section 4.0 illustrates the detailed timing for an interrupt response. After
the application of RESET the CPU will automatically enter interrupt Mode O.
Mode 1
When this mode has been selected by the pr.ogrammer, the CPU will respond to an interrupt
by executing Ii restart to location 003SH. Thus the response is identical to that for a non
maskable interrupt except that the call location is 003SH instead of 0066H. Another
difference is that the number of cycles required to complete the restart instruction is 2
more than normal due to the two added wait states.
111-6Q
Mode 2
This mode is the most powerful interrupt response mode. With a single 8-bit byte from the
user an indirect call can be made to any memory location.
With this mode the programmer maintains a table of 16 bit starting addresses for every interrupt service routine. This table may be located anywhere in memory. When an interrupt
is accepted, a 16 bit pointer must be formed to obtain the desired interrupt service routine
starting address from the table. The upper 8 bits of this pointer is formed from the contents
of the I register. The I register must have been previously loaded with the desired value by
the programmer, i.e. LD I, A. Note that a CPU reset clears the I register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting
device. Actually, only 7 bits are required from the interrupting device as the least
bit must be a zero. This is required since the pointer is used to get two adjacent bytes to
from a complete 16 bit service routine starting address and the addresses must always start
in even locations.
Interrupt
Service
Routine
Starting
Address
Table
desired starting address
pointed to by:
low order }
high order
I REG
CONTENTS
The first byte in the table is the least significant (low order) portion of the address. The
programmer must obviously fill this table in with the desired addresses before any interrupts
are to be accepted.
Note that this table can be changed at any time by the programmer (if it is stored in Read/
Write Memory) to allow different peripherals to be serviced by different service routines ..
Once the interrupting device supplies the lower portion of the pointer, the CPU automat cally pushes the program counter onto the stack, obtains the starting address from the table
and does a jump to this address. This mode of response requires 19 clock periods to complete (7 to fetch the lower 8 bits from the interrupting device, 6 to save the program
counter, and 6 to obtain the jump address.)
Note that the Z80 peripheral devices all include a daisy chain priority interrupt structure
that automatically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to the Z80-PI0, Z80-S10 and Z80-CTC manuals for details.
111-61
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
Last M Cycle
MI
of Instruction
T,
Last T State
Tw
T3
~ ~ r--L h~ r--L ~
----------:---- ------- ------.r.------- ___
------- ------- f------f------- ------ ------- ------
INT
~"L
AO-A15
IX
MI
)(REFRESH
PC
I
\\
I
MREO
:
I
I
I
I
IORO
DATA BUS
RD
.
.
Tw
--......
--~-t
111-64
9.0 HARDWARE IMPLEMENTATION EXAMPLES
This chapter is intended to serve as a basic introduction to implementing systems with the
Z80-CPU.
MINIMUM SYSTEM
Figure 9.0-1 is a diagram of a very simple Z80 system. Any Z80 system must include the
following five elements:
1)
2)
3)
4)
5)
Five volt power supply
Oscillator
Memory devices
I/O circuits
CPU
MINIMUM Z80 COMPUTER SYSTEM
+5V
AO-AlO
GND
MREO
RD
+5V
MK 3880
zao
DATA BUS
CPU
RESET
r
lORa
AO
Mi
A,
OUTPUT
DATA
INPUT
DATA
FIGURE 9.0-1
Since the Z80-CPU only requires a single 5 volt supply, most small systems can be implemented using only this single supply.
The oscillator can be very simple since the only requirement is that it be a 5 volt square
wave. For systems not running at full speed, a simple RC oscillator can be used. When the
CPU is operated near the highest possible frequency, a crystal oscillator is generally required
because the system timing will not tolerate the drift or jitter that an RC network will
generate. A crystal oscillator can be made from inverters and a few discrete components
or monolithic circuits are widely available.
The external memory can be any mixture of standard RAM, ROM, or PROM. In this simple
example we have shown a single 16K bit ROM (2K bytes) being utilized as the entire memory
system. For this example we have assumed that the Z80 internal register. configuration
contains sufficient ReadlWrite storage so that external RAM memory is not required.
111-65
Every computer system requires I/O circuits to allow it to interface to the "real world."
In this simple example it is assumed that the output is an a bit control vector and the input
is an a bit status word. The input data could be gated onto the data bus using any standard
tri-state driver while the output data could be latched with any type of standard TTL latch.
For this example we have used a zao-Plo for the I/O circuit. This single circuit attaches to
the data bus as shown and provides the required 16 bits of TTL compatible I/O. (Refer to
the zaO-Plo manual for details on the operation of this circuit.) Notice in this example that
with only three LSI circuits, a simple oscillator and a single 5 volt power supply, a powerful
computer has been implemented.
ADDING RAM
Most computer systems require some amount of external Read/Write memory for data
storage and to implement a "stack". Figure 9.0-2 illustrates how 256 bytes of static memory
can be added to the previous example. In this example the memory space is assumed to be
organized as follows:
ROM & RAM IMPLEMENTATION EXAMPLE
_ _ _---, ADDRESS
OOOOH
r-
2 K bytes
ROM
07FFH
256 bytes 0800H
RAM
\
08 FFH
(
ADDRESS BUS
Ao-A ,O
Ao-A7
,..
~CEI MK 34000
~CE2
~CE3
--BQ
00
~ R/W
2~MJ
256 x 8
RAM
CE, ~
All
CE2 , - - - ' - ' -
""
00- 07
DO -07
,..
~
DATA BUS
J
FIGURE 9.0-2
In this diagram the address space is described in hexidecimal notation. For this example,
address bit A 11 separates the ROM space from the RAM space so that it can be used for the
chip select function. For larger amounts of external ROM or RAM, a simple TTL decoder
will be required to form the chip selects.
MEMORY SPEED CQNTROL
For many applications, it may be desirable to use slow memories to reduce costs. The
WAIT line on the CPU allows the zao to operate with any speed memory. By referring
back to section 4 you will notice that the memory access time requirements are most
severe during the M1 cycle instruction fetch. All other memory accesses have an additional
one half of a clock cycle to be completed. For this reason it may be desirable in some
applications to add one wait state to the M1 cycle so that slower memories can be used.
Figure 9.0-3 is an example of a simple circuit that will accomplish this task. This circuit can
be changed to add a single wait state to any memory access as shown in F,gure 9.0-4.
111-66
ADDING ONE WAIT STATE TO AN M1 CYCLE
+5V
~D
1
S
o~>--
01--
0
7474
Q
-~c
r--
c:
M1
Q
R
R
.Iv
.L
T1
I
T2
I
Tw
I
T3
I
T4
I
J\JLJ\.J\JU
S
7474
<1>,
e----M1---~'
f o.
o I.
l
I
r
--"""'\'_, -_ _ _oJ
FIGURE 9.0·3
ADDING ONEWAIT STATE TO ANY MEMORY CYCLE
+5V
o
~
01--1---1
7474
C
. MREO ~'-_ _ _ __
7474
a
a
c
R
+5V
FIGURE 9.0-4
INTERFACING DYNAMIC MEMORIES
This section is intended only to serve as a brief introduction to interfacing dynamic
memories. Each individual dynamic RAM has varying specifications that will require minor
modifications to the description given here and no attempt will be made in this document
to give details for any particular RAM.
Figure 9.0~5 illustrates the logic necessary to interface 8K bytes of dynamic RAM using
16·pin 4K dynamic memories. This Figure assumes that the RAM's are the only memory in
the system so that A12 is used to select between the two pages of memory. During refresh
time, all memories in the system must be read. The CPU provides the proper refresh address
on lines AD through A6. To add additional memory to the system it is necessary to only
replace the two gates that operate on A12 with a decoder that operates on all required
address bits. For larger systems, buffering for the address and data bus is also generally
required.
An application note entitled "280 Interfacing Techniques for Dynamic RAM" is avail·
able from your MO$TEK representative which describes dynamic RAM design techniques.
111-67
INTERFACING DYNAMIC RAMS
rr-
DELAY
DELAY
CAS
R/W.
-:=::J- '-
i
]\.
~
1
DATA
BUS
~
~
A"-A,,
Do-D7
Ao·A5
CAS
MUX
CONTROL
ADDRESS
BUS
RAS
]
-=::d
4Kx8 DYNAMIC
PAGE
RAM MEMORY {looot o IFFF)
ARRAY
ADDRESS
MU LTlPLEXER
R/W
I - - RAS
r--
4Kx8 DYNAMIC PAGE o
RAM MEMORY (0000 to OFFF)
ARRAY
r-• NO REFRESH ADDRESS MULTIPLEXER RE QUIRED
• MRfQ INITIATES MEMORY CYCLE
• Al'SH SELECTS REFRESH CYCLE
FIGURE 9.0-5
WR
ZBO-CPU DESIGN CONSIDERATIONS: CLOCK CIRCUITRY
Proper
clock circuitry design is of paramount importance when designing a
system. Parameters such as clock rise and fall times, min.lmax. clock high and low
times, and max clock over and under shoot should be closely adhered to. Violation of
these specs will result in unreliable and unpredictable CPU/peripheral behavior. Several
manufacturers offer a wide variety of combination oscillator/drivers housed in 14 pin
DIP packages. The following is a suggested source of reliable oscillators/drivers
currently available.
zao
zao
Vendor
Function
Part No ..
Motorola
Motorola
MFElectronics
Hybrid House
Oscillator /Driver
Oscillator
Oscillator
Driver
K 1160 series
K1114
MF1114
HH3006A
zao
Figure 9.0-6 illustrates a schematic recommended for driving the
CPU, as well as
other
peripherals. This configuration meets the 30 ns rise and fall time while driving
up to a 150 pf. load. Note the divide by two input flip flop to provide a 50 percent duty cycle
clock. This stage may be omitted if the oscillator is guaranteed to be within the
specifications.
zao
33 pf.
74S74
0
+5 V
r'I'F
Q
2N2907A:
2 into
ascending order using a standard exchange sorting algorithm.
01/22n6
LOC
11:14:37
BUBBLE LISTING
OBJ CODE STMT SOURCE STATEMENT
1
*** STANDARD EXCHANGE (BUBBLE) SORT ROUTINE***
2
3
4
AT ENTRY:HL CONTAINS ADDRESSOF DATA
C CONTAINS NUMBER OF ELEMENTS TO BE SORTED
5
6
7
(1 SECOND, NO JUMP
;EXCHANGE ARRAY ELEMENTS
;RECORD EXCHANGE OCCURRED
;POINT TO NEXT DATA ELEMENT
;COUNT NUMBER OF COMPARISONS
;REPEAT IF MORE DATA PAIRS
;DETERMINE IF EXCHANGE OCCURRED
;CONTINUE IF DATA UNSORTED
;OTHERWISE, EXIT
;DESIGNATION OF FLAG BIT
;STORAGE FOR DATA ADDRESS
The following program multiplies two unsigned l6-bit integers and leaves the result
in the H L register pair.
01/22/76
11 :32:36
LOC
OBJ CODE
STMT
0000
0000
0002
0003
0004
0005
0008
OOOA
0610
4A
7B
EB
210000
CB39
lF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OOOB
3001
26
MU LTI PLY LlSTI NG
SOURCE STATEMENT
MULT:;
UNSIGNED SIXTEEN BIT INTEGER MULTIPL Y.
ON ENTRANCE: MULTIPLIER IN HL.
MULTIPLICAND IN DE.
ON EXIT: RESULT IN HL.
REGISTERS USES:
MLOOP:
H
L
0
E
B
C
A
HIGH ORDER PARTIAL RESULT
LOW ORDER PARTIAL RESULT
HIGH ORDER MULTIPLICAND
LOW ORDER MULTIPLICAND
COUNTER FOR NUMBER OF SHIFTS
HIGH ORDER BITS OF MULTIPLIER
LOW ORDER BITS OF MULTIPLI ER
LD
LD
LD
EX
LD
SRL
RR
B,16;
C,D;
A,E;
DE,HL;
HL,O;
C;
A;
JR
NC, NOADD-$
111-75
NUMBER OF BITS-INITIALIZE
MOVE MULTIPLIER
MOVE MULTIPLICAND
CLEAR PARTIAL RESULT
SHIFT MULTIPLIER RIGHT
LEAST SIGNIFICANT BIT IS
IN CARRY.
IF NO CARRY' SKIP THE ADD.
01/22176 11 :32:36
MULTIPLY LISTING (Cont'd.)
LOC
OBJ CODE
STMT SOURCE STATMENT
OOOD
19
27
OOOE
OOOF
0010
0011
0013
EB
29
EB
10F5
,C9
29
30
31
32
33
34
ADD HL, DE;
NOADD:
EX DE,HL;
ADD HL,HL;
EX DE,HL;
DJNZ MLOOP-$;
RET;
END;
111-76
ElSE ADD MULTIPLICAND TO
PARTIAL RESULT.
SHIFT MULTIPLICANT LEFT
BY MULTIPLYING IT BY TWO.
REPEAT UNTIL NO MORE BITS.
11.0 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....................................... Specified Operating Range
Storage Temperature .................................................-65°C to +150°C
Voltage on Any Pin with Respect to Ground
......................•........ -0.3V to +7V
Power Dissipation ............................................................. 1.5W
D.C. CHARACTER ISTICS
T A = 0° C to 70° C, V CC = 5V ± 5% unless otherwise specified
MIN.
PARAMETER
VILC
-0.3
VIHC
Vcc-.6
VIL
-0.3
TYP.
MAX.
UNIT
TEST CONDITIO
0.8
2.0
IOL = 1.8mA
IOH = -250 p.A
2.4
oat
-10
Output Leakage Current in Float
p.A
±10
Data Bus Leakage Current in Input Mode
*200mA for -4, -10 or -20 devices
NOTE: All outputs are rated at one standard TTL load.
CAPACITANCE
T A = 25° C, f = 1 MHz unmeasured pins returned to ground
SYMBOL
PARAMETER
MAX. UNIT
C
Clock Capacitance
35
CIN
Input Capacitance
5
COUT
Output Capacitance 10
pF
pF
pF
·Comment
.Stresses above those listed under" Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition
above those indicated in the operational sections of this spacification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
111-77
VOUT = O.4V
MK 3880, MK 3880·10, MK 3880·20 Z80-CPU
A C CHARACTERISTICS
TA
=0
0
C to 700 C,
SIGNAL
Vee =+5V ± 5%, Unless Otherwise Noted
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
t
Clock
Clock
Clock
Clock
.4
[12]
(D)
2000
30
j.lSec
145
110
nsec
nsec
~(
tw(L)
tr,f
tD(AD)
tF(AD)
tacm
AO·15
taci
tca
tcaf
tD(D)
tF(D)
tS(D)
"
D0-7
tS4i(D)
tdcm
~ci
tcdf
tH
F.ifRfQ
iORO
Address Output Delay
Delay to Float
[1]
Address Stable Prior to iiAREO
(Memory Cycle)
[2]
Address Stable Prior to 10RO, RD
or iiJR (I/O Cycle)
Address Stable From RD, WtltFl0RO or MREO [3]
[4]
Address Stable From AD or W
During Float
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to R ising Edge of
Clock During Ml Cycle
Data Setu.P Time to Falling Edge at
Clock During M2!2...M5
Data Stable Prior to WR (Memory
Cycle)
. Data Stable Prior to WR (I/O Cyclet
Data Stable From WR
Input Hold Time
nsec
nsec
nsec
nsec
nsec
nsec
230
90
50
nsec
60
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
nsec
tDH(MR)
MREQ Delay From Rising Edge of
Clock, MREO High
100
nsec
M'FiEQ DeAAY Eam Falling Edge of
100
nsec
tw(MRL)
tw(liXlrn)
Clock, R
High
Pulse Width, MREO Low
Pulse Width, MREO High
tDL(lR)
iORQ Dela6~rom
tDL(RD)
90
nsec
110
nsec
100
nsec
110
nsec
m5 Delay From
Rising Edge of Clock,
100
nsec
RD Delay From Falling Edge of Clock,
RD Low
130
nsec
tDH(RD)
100
nsec
tDHi(BD)
RD Delay From Falling Edge of Clock,
AD High
110
nsec
tDL(WR)
Wf!..Q.elay From Rising Edge of Clock,
_WR Low
WR..Q.elay From Falling Edge of Clock
WR Low
WR Delay From Falling Edge of Clock,
WR High_
Pulse Width, WR Low
tDL(WR)
tDH(WR)
tw(WRi:.)
[10]
CL = 50pF
nsec
Ri5 Delay From Rising Edge of Clock,
_AD High
tDL4>(RD)
CL = 50pF
nsec
[8]
[9]
Rising Edge of
.Clock, I
0 Low
iORQ DelaO FQ'm Falling Edge of
Clock, I R Low
i'5RQ Delay From Rising Edge of
-flpck, 10RO High
IORO Delay From Falli~g Edge of
Clock, IORO High
1ID Low
Except T3·M 1
nsec
nsec
100
tDH~MR)
CL = 50pF
nsec
MREO Dea~Eam Falling Edge of
Clock,
Low
tDH4>(lR)
WR
180
180
tDL4i(MR)
tDH(lR)
RD
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
TEST CONDITION
80
nsec
90
nsec
100
nsec
CL = 50 pF
CL = 50pF
CL = 50pF
nsec
NOTES:
A
Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge data should be enabled when
and lORa are both active.
' .
.
B
The RESET signal must be active for a minimum of 3 Clock cycles.
corit'.d on page 81
111·78
Mi
MK 3880, MK 3880·10, MK 3880·20 Z80·CPU
SIGNAL
MAX.
UNIT
Ml...Q.elay From Rising Edge of Clock
Ml Low
Ml...Q.elay From Rising Edge of Clock
Ml High
130
nsec
130
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock,
RFSH High
180
nsec
150
nsec
SYMBOL
PARAMETER
tDL(Ml)
Ml
tDH(Ml)
RFSH
tDL(RF)
tDH(RF)
MIN.
70
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
tD(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(lT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw(NML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BO)
BUSRO Setup Time to Rising Edge of
Clock
80
nsec
BUSAK
tDL(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
ts(RS)
RESET Setup Time to Rising Edge of
Clock
tF(C)
De@v. to/frQ!!l.Float (MR EO, lORa,
RD and WR)
tmr
M 1 Stable Prior to lORa (Interrupt Ack.)
300
nsec
120
nsec
110
nsec
= 50pF
CL
= 30pF
CL
= 50pF
CL
= 50 pF
nsec
90
100
[ 11]
CL
nsec
WAIT
tDH(BA)
TEST CONDITIONS
nsec
nsec
LOAD CIRCUIT FOR OUTPUT
TEST POINT
[ 1] tacm
= tw (
A(}'15
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tc
tw(cI>H)
tw(cI>L}
t r, f
Clock
Clock
Clock
Clock
.25
110
110
[12]
(D)
2000
30
J.lSec
nsec
nsec
nsec
tD(AD}
tF(AD}
tacm
Address Output Delay
Delay to Float
Add ress Stable Prior to JI.lI'Rm
(Memory Cycle)
Address Stable Prior to 10RO, RD
orWR (I/O Cycle) _ _ _ _
Address Stable From RD, W!1JORO or MREO
Address Stable From RD or WR
During Float
110
90
[1]
nsec
nsec
nsec
[2]
nsec
[3]
[4]
nsec
nsec
taci
tea
tcaf
tdci
tcdf
tH
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During Ml Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
tDLcI>(MR)
I'iIIl1rn Delay From Falling Edge of
tD(D)
tFID)
tScI>(D)
00·7
tS~(D)
tdcm
KiI"R"rn
tDHcI>(MR)
tDH4i(MR)
tw(MRL)
tw (iiifi:fR)
tDLcI>(JR)
10RO
tDL~(lR)
tDHcI>(lR)
tDH~(lR)
tDLcI>(RD)
AD
tDL~(RD)
tDHcI>(RD)
tDH-;P(RD)
tDLcI>(WR)
WR
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
tDL~(WR)
tDHcI>(WR)
tw(WRL)
Clock, MREO Low
MREO Delay From Rising Edge of
~ck, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
35
nsec
nsec
nsec
50
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
150
90
20
WR Delay From
WR Low
WR Delay From
WR Low
WR Delay From
WR High _
Pulse Width, WR
nsec
85
nsec
85
nsec
[8]
[9]
CL
= 50pF
Except T3.M1
CL
= 50pF
CL
= 50pF
CL
= 50pF
nsec
nsec
10RO Del~om Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
f'OR'Cl Delay From Rising Edge of
Clock, 10RO High
~ Delay From Falling Edge of
Clock, 10RO High
RD Delay From
RD Low
RD.Q.elay From
RD Low
RD Delay From
_RD High
RD Delay From
RD High
85
TEST CONDITIONS
75
nsec
85
nsec
85
nsec
85
nsec
85
nsec
95
nsec
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
85
nsec
Rising Edge of Clock,
65
nsec
Falling Edge of Clock,
80
nsec
Falling Edge of Clock,
80
nsec
Rising Edge of Clock,
Falling Edge of Clock,
CL
= 50pF
CL
= 50pF
I
[10]
Low
nsec
NOTES:
A Data should be enabled onto the CPU data bus when
is active. During interrupt acknowledge data should be enabled when Ml
and IORQ are both active.
B The RESET signal must be active for a minimum of 3 clock cycles.
(Cont'd. on page 83)
AD
111·80
M K 3880-4 Z80A-CPU
SIGNAL
Ml
PARAMETER
tDL(Ml)
Ml Delay From Rising Edge of Clock
Ml Low
M1 Delay From Rising Edge of Clock,
Ml High
tDH(M1)
RFSH
MIN.
SYMBOL
tDL(RF)
tDH(RF)
MAX.
UNIT
100
nsee
100
nsee
130
nsee
120
nsee
CL; 50pF
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
CL; 50pF
WAIT
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
tD(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(IT)
INT Setup Time to Rising Edge of Clock
80
nsee
NMI
tw(NML)
Pulse Width, NMI Low
80
nsee
8USRO
ts(BO)
BUSRO Setup Time to Rising Edge of
Clock
50
nsee
BUSAK
tDL(BA)
tDH(BA)
RESET
TEST CONDITION
70
nsee
300
BUSAK Delay From Rising Edge of
BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
nsee
100
nsee
100
nsee
~k,
CL ; 50pF
CL; 50pF
ts(RS)
RESET Setup Time to Rising Edge of
Clock
tF(C)
De!!v. to/From Float (MREO, IORO,
RD and WR)
tmr
M1 Stable Prior to IORO (Interrupt Aek.)
60
nsee
80
[ 11]
nsee
nsec
LOAD CIRCUIT FOR OUTPUT
TEST POINT
[1]
taem ; tw ( H) + tf - 65
[2]
taci ; tc -70
[3]
tea; tw (L) + tr -50
[4]
tcaf; tw (L) + tr -45
[5]
tdcm; tc -170
[6]
tdci; tw (L) + tr - 170
[7]
tcdf; tw (L) + tr -70
[8]
tw (MRL); tc -30
[9]
tw (MRH) ; tw (H) + tf- 65
[12] tc;
!w (L) + tr + tf
111-81
Although static by design, testing guarantees tw
200 psec maximum.
( H) of
A.C. TIMING D,IAGRAM
Timing measurements are made at the following voltages, unless otherwise specified:
CLOCK
OUTPUT
INPUT
FLOAT
"1"
V ee -·6
2.0V
2.0 V
t:N
"0"
.BV
.BV
.BV
±0.5V
A O-A15
AO- 15
IN
DO_7
{
OUT
tOl (Mil
leal
1ft
'..
'mr
to
111-82
(HTJ
tcd!
r,rCI
--
-----~
'2.0 zao
INSTRUCTION BREAKDOWN BY MACHINE CYCLE
zao
This section tabulates each
instruction type and breaks each instruction down into its
machine cycles and corresponding T States. The different standard machine cycles (OP
Code Fetch, Memory Read, Port Read, etc.) are described in Section 4.0 of this manual.
This chart will allow the system designer to predict what the Z80 will do on each clock
cycle during the execution of a given instruction. The instruction types are listed together
by functions and in the same order as the Tables in Section 7.
The best way to learn how to use these tables is to look at a few examples. The first
example is to register exchange instructions (LD r, s) where r,s can be any of the following
CPU Registers: B,C,D,E,H,L, or A. The instruction breakdown table shows this instruction
to have one machine cycle (M 1) four T-States long (number in parenthesis) which is an OP
Code Fetch. Referring to Figure 4.0-1 one sees the standard form for an OP Code Fetch and
the state of the CPU bus during these four T-States. Taking the next instruction shown
(LD r, n) which loads one of the previous registers with data or immediate value "n" one
finds the breakdown to be a four T-State OP Code Fetch followed by a three T-State Operand Data Read. An Operand Data Read takes the form of the Standard Memory Read
shown in Figure 4.0-2.
After these two simple examples, a more complex one is in order. The LD r, (IX+d) is the
first double byte OP Code shown and executes as follows: First there are two M1 cycles
(and related memory refreshes) followed by an Operand Data Read of the displacement
"d". Next M3 consists of a five T-State Internal Operation which is the calculation of the
Indexed address (IX+d). The last machine cycle (M4) consists of a Memory Read of the
data continued in address IX+d and the loading of register "r" with that data.
The LD dd, (nn) instruction loads an internal 16-bit register pair with the contents of the
memory location specified in the Operand Bytes of the instruction. This instruction is four
bytes long (two bytes of OP Code + two bytes of Operand Address). As shown, there are
two M1 cycles to fetch the OP Code and then two Machine Cycles to read the Operand
Addresses, low order byte first. Machine cycle 4 is a read of memory to obtain the data for
the low order register (e.g., C of BC, E of DE and L of H L) followed by a read of the data
for the high order register.
The first instruction to use the Stack Register is the PUSH qq instruction which executes
as follows: Machine cycle 1 is extended by one cycle and the Stack Pointer is decremented
in the extra T-State to point to an empty location on the Stack. Machine cycle 2 is a write
of the high byte of the referenced register to the address contained in the Stack Pointer.
The Stack Pointer is again decremented and a write of the low byte of the referenced register is made to the Stack in Machine Cycle 3. Note that the Stack Pointer is left pointing to
the last data referenced on the Stack. The block transfer instructions such as LDI and LDIR
are very similar. LDI is 16 T-States long and is composed of a double byte OP Code Fetch
(two memory refreshes) followed by a memory read and a memory write. The memory
write is 5 T-States long to allow updating of the block length counter -BC. The repetitive
form of this instruction (LDI R) has an additional Machine Cycle (M4) of 5 T-States to
allow decrementing of the Program Counter by two (PC-2) which results in refetching of
the OP Code (LDI R). Each movement of data by this instruction is 21 T-States long (except
the last) and the refetching of the OP Codes results in memory refresh occurring as well as
the sampling of interrupts and BUSRQ.
The NMI Interrupt sequence is 11 T-States long with the first M1 being a dummy OP
Code Fetch of 5 T-States long. The Program Counter is not advanced, the OP Code on the
data bus is ignored and an internal Restart is done to address 66H. The following two
Machine Cycles are a write of the Program Counter to the Stack.
The INT Mode 0 is the 8080A mode and requires the user to place an instruction on the
data bus for the CPU to execute. If a RST instruction is used, the CPU stacks the Program
Counter and begins execution at the Restart Address_ If a CALL instruction is used, the
CALL Op Code is placed on the data bus during the INTA cycle (M1). M2 and M3 are
111-83
normal Memory Read cycles ~not INTAcycles) of the CALL addresses (low byte first).
Program Counter is stacked in M4 and M5.
zao
Mode 2 is used by the
System Peripherals and operates as foll8llVs: During the I NTA
cycle (M 1) a Vector is sent in from the highest priority interrupting device. M2 and M3
are used to Stack the Program Counter. The Vector (low byte) and an internal Interrupt
Register (I) from a pointer to a table containing the addresses of Interrupt Service Routines.
During M4 and M5 the Service Routines address is read from this table into the CPU.
The next M 1 cycle will fetch an OP Code from the address received is M4 and M5.
111-84
LEGEND
10
MR
MRH M RL MW
MWH MWL OCF ODH -
Internal CPU Operation
Memory Read
Memory Read of High Byte
Memory Read of Low Byte
Memory Write
Memory Write of High Byte
Memory Write of Low Byte
Op Code Fetch
Operand Data Read of High Byte
Operand Data Read of Low Byte
Port Read
Port Write
Stack Read of High Byte
Stack Read of Low Byte
Stack Write of High Byte
Stack Write of Low Byte
Number of T-States in that Machine Cycle
ODL
PR
PW
SRH
SRL
SWH
SWL
( )
Z80 INSTRUCTION BREAKDOWN BY MACHINE CODE
MACHINE CYCLE
INSTRUCTION
TYPE
LD r,
BYTES
-
M1
M2
M3
M4
MR (3)
MW(3)
M5
OCF (4)
5
1
LD r, n
2
OCF (4)
OD (3)
LD r, (HL)
LD (HL), r
1
OCF (4)
OCF (4)
MR (3)
MW(3)
LD r, (lX+d)
LD (IX+d). r
3
OCF (4)/OCF (4)
OCF (4)/OCF (4)
OD (3)
OD (3)
10 (5)
10 (5)
LD (HL). n
.BC
LD A, (DE)
2
OCF (4)
OD (3)
MW(3)
1
OCF (4)
MR (3)
LD (BC) A
DE'
LD A, (nn)
LD (nn), A
OCF (4)
MW(3)
3
OCF (4)
OCF (4)
ODL (3)
ODL (3)
ODH (3)
ODH (3)
LDA,~
2
OCF (4)/OCF(5)
LD dd, nn
3
OCF (4)
ODL (3)
ODH (3)
LD IX, nn
4
OCF (4)/OCF (4)
ODL (3)
ODH (3)
LD HL, (nn)
LD (nn), HL
3
OCF (4)
OCF (4)
ODL (3)
ODL (3)
ODH (3)
ODH (3)
MRL (3)
MWL (3)
MRH (3)
MWH (3)
4
OCF
OCF
OCF
OCF
ODL
ODL
ODL
ODL
ODH
ODH
ODH
ODH
MRL (3)
MWL(3)
MRL (3)
MWL(3)
MRH
MWH
MRH
MWH
LD SP, HL
1
OCF (6)
LD SP, IX
2
OCF (4)/OCF (6),
PUSH qq
1
OCF (5)
SP-1
SWH (3)
OCF (4)/OCF (5)
SP-1
SWH (3)
OCF (4)
SRH (3)
SP+1
SRL (3)
SRH (3)
SP+1
SRL (3)
MR (3)
MW(3)
I
LDR' A
LD
LD
LD
LD
dd, (nn)
(nn), dd
IX, (nn)
(nn). IX
PUSH IX
POPqq
POP IX
2
1
2
(4)/OCF
(4)/OCF
(4)/OCF
(4)/OCF
(4)
(4)
(4)
(4)
OCF (4)/OCF (4)
EX DE, HL
1
OCF (4)
EX AF, AF'
1
OCF (4)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
SWL(3)
SP-1
SWL (3)
SP-1
111-85
SP+1
SP+1
(3)
(3)
(3)
(3)
MACHINE CYCLE
INSTRUCTION
TYPE
BYTES
M1
EXX
1
OCF (4)
EX (SP). HL
1
OCF (4)
M2
SRL (3)
M3
M4
M5
SRH (4)
SWH (3)
SP-l
SWL (5)
SRH (4)
SWH (3)
SP-l
SWL (5)
SP+l
EX (SP).IX
2
OCF (4)/OCF (4)
SRL (3)
SP+l
LDI
LDD
CPI
CPO
2
OCF (4)/OCF (4)
MR (3)
MW(5)
LDIR
LDDR
CPIR
CPDR
2
OCF (4)/OCF (4)
MR (3)
MW(5)
ALU A. r
ADD ADC
SUB SBC
ANDOR
XOR CP
1
OCF (4)
ALU A. n
2
OCF (4)
00 (3)
ALU A. (HL)
1
OCF (4)
MR (3)
ALU A. (lX+d)
3
OCF (4)/OCF (4)
00 (3)
10(5)
DEC
INC r
1
OCF (4)
DEC
INC (HL)
1
OCF (4)
MR (4)
MW(3)
DEC
INC (lX+D)
2
OCF (4)/OCF (4)
00 (3)
10 (5)
DAA
CPL
CCF
SCF
NOP
HALT
01
EI
1
OCF (4)
NEG
IMO
IMl
1M2
2
OCF (4)/OCF (4)
10 (5)*
*onlv if BC f' 0
111-86
MR (3)
MR (4)
MW(3)
MACHINE CYCLE
INSTRUCTION
TYPE
BYTES
M1
M2
M3
M4
M5
MW(3)
55
1
OCF (4)
10 (4)
10 (3)
ADC HL, 55
SBC HL, 55
ADD IX, pp
2
OCF (4)/OCF (4)
10 (4)
10 (3)
INC 55
DEC 55
1
OCF (6)
DEC IX
INC IX
2
OCF (4)/OCF (6)
RLCA
RLA
RRCA
RRA
1
OCF (4)
RLC r
RL
RRC
RR
SLA
SRA
SRL
2
OCF (4)/OCF (4)
RLC (HL)
RL
RRC
RR
SLA
SRA
SRL
2
OCF (4)/OCF (4)
MR (4)
MW(3)
RLC (lX+d)
RL
RRC
RR
SLA
SRA
SRL
4
OCF (4)/OCF (4)
OD (3)
10 (5)
MR (4)
RLD
RRD
2
OCF (4)/OCF (4)
MR (3)
10 (4)
MW(3)
BITb, r
SET
RES
2
OCF (4)/OCF (4)
ADD HL,
111-87
MACHINE CYCLE
INSTRUCTION
TYPE
BYTES
M1
M2
M3
M4
BIT b, (HL)
2
OCF (4)/OCF (4)
MR (4)
SET b, (HL)
RES
2
OCF (4)/OCF (4)
MR (4)
MW(3)
BIT b, (lX+d)
4
OCF (4)/OCF (4)
00 (3)
10 (5)
MR (4)
SET b, (lX+d)
RES
4
OCF (4)/OCF (4)
00 (3)
10 (5)
MR (4)
JP nn
JP ce, nn
3
OCF (4)
OOL (3)
OOH (3)
JR e
2
OCF (4)
00 (3)
10 (5)
2
OCF (4)
00 (3)
10 (5)*
JR
JR
. JR
JR
C, e
NC, e
Z, e
NZ, e
M5
MW(3)
* If condition is met
JP (HL)
1
OCF (4)
JP (IX)
2
OCF (4)/OCF (4)
OJNZ, e
2
OCF (5)
00 (3)
10 (5)*
* If sf 0
CALL nn
CALL cc, nn
cc true
3
OCF (4)
OOL (3)
OOH (4)
SP-1
CALLcc, nn
ce false
3
OCF (4)
OOL (3)
OOH (3)
RET
1
OCF (4)
SRL (3)
SP+1
SRH (3)
RETcc
1
RETI
RETN
2·
RST p
1
OCF (5)
OCF (4)/OCF (4)
OCF (5)
SP-1
SWH (3)
SP-1
SP+1
SRL (3)*
SRH (3)*
* If cc is true
SP+1
SP+1
SRL (3)
SP+1
SRH (3)
SP+1
SWH (3)
SP-1
SWL (3)
··IH c88
SWL (3)
MACHINE CYCLE
INSTRUCTION
TYPE
BYTES
Ml
M2
M3
PR (4)
M4
M5
INA, (n)
2
OCF (4)
OD (3)
IN r, (e)
2
OCF (4)/OCF (4)
PR (4)
INI
IND
2
OCF (4)/OCF (5)
PR (4)
MW(3)
INIR
INDR
2
OCF (4)/OCF(5)
PR (4)
MW(3)
OUT (n), A
2
OCF (4)
OD (3)
PW(4)
OUT (C), r
2
OCF (4)/OCF (4)
PW(4)
OUTI
OUTD
2
OCF (4)/OCF (5)
MR (3)
PW(4)
OTIR
OTDR
2
OCF (4)/OCF (5)
MR (3)
PW(4)
10 (5)
-
OCF (S) *
SP-,
SWH (3)
SP-l
SWL (3)
*Op Code Ignored
-
INTA (6)
ODL (3)
(CALL INSERTED)
ODH (4)
SP-l
SWH (3)
SP-l
SWL (3)
-
INTA(6)
(RST INSERTED)
SP-l
SWH (3)
SWL(3)
INTA(7)
(RST 38H
INTERNAU
SP-,
SWH (3)
INTA(7)
(VECTOR
SUPPLIED)
SP-l
SWH (3)
MRL (3)
MRH (3)
10 (5)
INTERRUPTS
NMI
INT
MODE 0
MODEl
MODE 2
-
SP-,
SWL(3)
SP-l
SP-l
111-89
SWL(3)
ORDERING INFORMATION
PACKAGE TYPE
MAX CLOCK
FREQUENCY
MK3880N Z80-CPU
Plastic
2.5 MHz
MK38aOp zao-cpu
Ceramic
2.5 MHz
MK3880J Z80-CPU
Cerdip
2.5 MHz
MK3880N-4 Z80-CPU
Plastic
4.0 MHz
MK3880P-4 Z80-CPU
Ceramic
4.0 MHz
MK3880J-4 zao-cpu
Cerdip
4.0 MHz
Ceramic
2.5 MHz
PART NO.
MK3880P-10 Z80-CPU
111-90
TEMPERATURE RANGE
0° to +70°C
-40°C to +85°C
MOSTEI(.
Z80 MICROCOMPUTER DEVICES
Technical Manual
1
MK3881
PARALLEL 1/0
CONTROLLER
111-91
111-92
TABLE OF CONTENTS
SECTION
PAGE
1.0
INTRODUCTION ........................................................................ 111-95
2.0
ARCHITECTURE ........................................................................ 111-97
3.0
PIN DESCRIPTION ...................................................................... 111-99
4.0
PROGRAMMING THE PIO .............................................................. 111-103
5.0
TIMING .............................................................................. 111-107
6.0
INTERRUPT SERVICING ................................................................ 111-113
7.0
APPLICATIONS ....................................................................... 111-115
8.0
PROGRAMMING SUMMARY ........................................................... 111-119
9.0
ELECTRICAL SPECIFICATIONS .......................................................... 111-121
10.0 ORDERING INFORMATION ............................................................. 111-125
111-93
111-94
1.0 INTRODUCTION
The zao Parallel I/O Circuit is a programmable, two port device which provides a TTL
compatible interface between peripheral devices and the zaO-cpu. The CPU can configure
the zao-Plo to interface with a wide range of peripheral devices with no other external
logic required. Typical peripheral devices that are fully compatible with the zaO-Plo include
most keyboards, paper tape readers and punches, printers, PROM programmers, etc. The
zaO-Plo utilizes N channel silicon gate depletion load technology and is packaged in a
40 pin DIP. Major features of the zaO-Plo include:
Two independent a bit bidirectional peripheral interface ports with 'handshake'
data transfer control
I nterrupt driven 'handshake' for fast response
Anyone of four distinct modes of operation may be selected for a port including:
Byte output
Byte input
Byte bidirectional bus (Available on Port A only)
Bit control mode
All with interrupt controlled handshake
Daisy chain priority interrupt logic included to provide for automatic interrupt
vectoring without external logic
Eight outputs are capable of driving Darlington transistors
All inputs and outputs fully TTL compatible
Single 5 volt supply and single phase clock required.
One of the unique features of the zao-Plo that separates it from other interface controllers
is that all data transfer between the peripheral device and the CPU is accomplished under
total interrupt control. The interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the zao-cpu during I/O transfers. All logic necessary to implement a
fully nested interrupt structure is included in the PIO so that additional circuits are not
required. Another unique feature of the PIO is that it can be programmed to interrupt
the CPU on the occurrence of specified status conditions in the peripheral device. For
example, the PIO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor must spend in polling peripheral status.
111-95
111-96
2.0 Pia ARCHITECHTURE
A block diagram of the zao-Plo is shown in figure 2.0-1. The internal structure of the
zaO-Plo consists of a zao-cpu bus interface, internal control logic, Port A I/O logic,
Port B I/O logic, and interrupt control logic. The CPU bus interface logic allows the
Pia to interface directly to the zao-cpu with no other external logic. However, address
decoders and/or line buffers may be required for large systems. The internal control logic
synchronizes the CPU data bus to the peripheral device interfaces (Port A and Port B).
The two I/O ports (A and B) are virtually identical and are used to interface directly to
peripheral devices.
Pia BLOCK DIAGRAM
Figure 2.0-1
t::I-.::r-~
DATA OR CONTROL
I-_~}HANDSHAKE
CPU
INTERFACE {
DATAB~
CPU
BUS
110
6
PERIPHERAL
INTERFACE
PIO CONTROL
LINES
t::I-.::r-~DATA
OR CONTROL
I-_~}HANDSHAKE
3
INTERRUPT CONTROL LINES
The Port I/O logic is composed of 6 registers with "handshake" control logic as shown in
figure 2.0-2. The registers include: an a bit data input register, an a bit data output register,
a 2 bit mode control register, an a bit mask register, an a bit input/output select register,
and a 2 bit mask control register.
PORT I/O BLOCK DIAGRAM
Figure 2.0-2
DATA
OUTPUT
REG
IIBITII
181T
PERIPHERAL
DATA OR
CONTROL BUS
MASK
CONTROL
REG
12BITII
1-:==:>1
IINTERRUPT
REQUESTS
111-97
The 2-bit mode control register is loaded by the CPU to select the desired operating mode
(byte output, byte input, byte bidirectional bus, or bit control mode). All data transfer
between the peripheral device and the CPU is achieved through the data input and data
output registers. Data may be written into the output register by the CPU or read back to
the CPU from the input register at any time. The handshake lines associated with eacn port
are used to control the data transfer between the PIO and the peripheral device.
.
The 8-bit mask register and the 8-bit input/output select register are used only in the bit
control mode. In this mode any of the 8 peripheral data or control buspins can be programmed to be an input or an output as specified by the select register. The mask register
is used in this mode in conjunction with a special interrupt feature. This feature allows an
interrupt to be generated when any or all of the unmasked pins reach a specified state
(either high or low). The 2-bit mask control register specifies the active state desired (high
or' low) and if the interrupt should be generated when all unmasked pins are active (AND
Gondition) or when any unmasked pin is active (OR condition). This feature reduces the
requirement for CPU status checking of the peripheral by allowing an interrupt to be automatically generated on specific peripheral status conditions. For example, in a system with
3 alarm conditions, an interrupt may be generated if anyone occurs or if all three occur.
The interrupt control logic section handles all CPU interrupt protocol for nested priority
interrupt structures. The priority of any device is determined by its physical location in a
daisy chain configuration. Two lines are provided in each PIO to form this daisy chain. The
device closest to the CPU has the highest priority. Within a PIO, Port A interrupts have
higher priority than those of Port B. In the byte input, byte output or bidirectional modes,
an interrupt can be generated whenever a new byte transfer is requested by the peripheral.
In the bit control mode an interrupt can be generated when the peripheral status matches a
programmed value. The PIO provides for complete control of nested interrupts. That is,
lower priority devices may not interrupt higher priority devices that have not had their
interrupt service routine completed by the CPU. Higher priority devices may interrupt the
servicing of lower priority devices.
When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide
an 8-bit interrupt vector for the CPU. This vector is used to form a pointer to a location
in the computer memory where the address of the interrupt service routine is located.
The 8-bit vector from the interrupting device forms the least significant 8 bits of the indirect
pointer while the I Register in the CPU provides the most significant 8 bits of the pointer.
Each port (A and B) has an independent interrupt vector. The least significant bit of the
vector is automatically set to a a within the PIO since the pointer must point to two adjacent memory locations for a complete 16-bit address.
The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data
bus so that each PIO in the system knows at all times whether it is being serviced by the
CPU interrupt service routine without any other communication with the CPU.
111-98
3.0 PIN DESCRIPTION
A diagram of the ZSO-PIO pin configuration is shown in figure 3.0-1. This section describes
the function of each pin.
ZSO-CPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and commands between the ZSOCPU and the ZSO-PIO. DO is the least significant bit of the bus.
B/ASel
Port B or A Select (input, active high)
This pin defines which port will be accessed during a data transfer between the ZSO-CPU and the ZSO-PIO. A low level on this pin selects
Port A while a high level selects Port B. Often Address bit AD from the
CPU will be used for this selection function.
C/DSel
Control or Data Select (input, active high)
This pin defines the type of data transfer to be performed bwtween the
CPU and the PIO. A high level on this pin during a CPU write to the
PIO causes the ZSO data bus to be interpreted as a command for the
port selected by the B/A Select line. A low level on this pin means that
the ZSO data bus is being used to transfer data between the CPU and
the PIO. Often Address bit A1 from the CPU will be used for this function.
CE
Chip Enable (input, active low)
A low level on this pin enables the PIO to accept command or data
inputs from the CPU during a write cycle or to transmit data to the
CPU during a read cycle. This signal is generally a decode of four
I/O port numbers that encompass port A and B, data and control.
System Clock(input)
The ZSO-PIO uses the standard ZSO system clock to synchronize certain
signals internally. This is a single phase clock.
Machine Cycle One Signal from CPU (input, active low)
This signal from the CPU is used as a sync pulse to control several
internal PIO operations. When M1 is active and the RD signal is active,
the ZSO-CPU is fetching an instruction from memory. Conversely,
when M1 is active and 10RO is active, the CPU is acknowledging an
interrupt. In addition, the M1 signal has two other functions within the
ZSO-PIO.
1.
M1 synchronizes the PIO interrupt logic.
2.
When M1 occurs without an active RD or 10RQ signal the
PIO logic enters a reset state.
Input/Output Request from ZSO-CPU (input, active low)
The 10RQ signal is used in conjunction with the B/A Select, C/D
Select, CE, and RD signals to transfer commands and data between
the ZSO-CPU and the ZSO-PIO. When ~, fIT) and TORTI are active,
the port addressed by B/A will transfer data to the CPU (a read operation). Conversely, when CE and 10RQ are active but RD is not active,
then the port addressed by B/ A will be written into from the CPU with
either data or contlol information as specified by the C/D Select signal.
Also, if 10RQ and iiiif are active simultaneously, the CPU is acknowledging an interrupt and the interrupting port will automatically place
its interrupt vector on the CPU data bus if it is the highest device requesting an interrupt.
111-99
Read Cycle Status from the ZaD-CPU (input, active low)
If RD is active a MEMORY READ or I/O READ operation is in progress. The RD signal is used with B/A Select, C/D Select, CE and 10RQ
signals to transfer data from the ZaD-PIO to the ZaD-CPu.
lEI
Interrupt Enable In (input, active high)
This signal is used to form a priority interrupt daisy chain when more
than one interrupt driven device is being used. A high level on this pin
indicates that no other devices of higher priority are being serviced
by a CPU interrupt service routine.
lEO
Interrupt Enable Out (output, active high)
The IEO signal is the other signal required to form a daisy chain priority scheme. It is high only if IEI is high and the CPU is not servicing
an interrupt from this Pia. Thus this signal blocks lower priority devices from interrupting while a higher priority device is being serviced
by its CPU interrupt service routine.
Interrupt Request (output, open drain, active low)
When INT is active the ZaD-PIO is requesting an interrupt from the
ZaD-CPU.
Port A Bus (bidirectional, tri-state)
This a bit bus is used to transfer data and/or status or control information between Port A of the ZaD-PIO and a peripheral device. AD
is the least significant bit of the Port A data bus.
Port A Strobe Pulse from Peripheral Device (input, active low)
The meaning of this signal depends on the mode of operation selected
for Port A as follows:
A RDY
1)
Output mode: The positive edge of this strobe is issued by the
peripheral to acknowledge the receipt of data made available by
the Pia.
2)
Input mode: The strobe is issued by the peripheral to load data
from the peripheral into the Port A input register. Data is loaded into the Pia when this signal is active.
3)
Bidirectional mode: When this signal is active, data from the
Port A output register is gated onto Port A bidirectional data
bus. The positive edge of the strobe acknowledges the receipt
of the data.
4)
Control mode: The strobe is inhibited internally.
Register A Ready (output, active high)
The meaning of this signal depends on the mode of operation selected
for Port A as follows:
1)
Output mode: This signal goes active to indicate that the Port
A output register has been loaded and the peripheral data bus
is stable and ready for transfer to the peripheral device.
2)
Input mode: This signal is active when the Port A input register
is empty and is ready to accept data from the peripheral device.
3)
Bidirectional mode: This signal is active when data is available
in Port A output register for transfer to the peripheral device.
In this mode data is not placed on the Port A data bus unless
A STB is active.
111-100
4)
Control mode: This signal is disabled and forced to a low state.
Port B Bus (bidirectional, tristate)
This 8 bit bus is used to transfer data and/or status or control information between Port B of the PIO and a peripheral device. The Port B
data bus is capable of supplying 1.5ma@ 1.5V to drive Darlington
transistors. BO is the least significant bit of the bus.
Port B Strobe Pulse from Peripheral Device (input, active low)
The meaning of this signal is similar to that of A STB with the following exception:
In the Port A bidirectional mode this signal strobes data from the
peripheral device into the Port A input register.
Register B Ready (output, active high)
The meaning of this signal is similar to that of A Ready with the following exception:
In the Port A bidirectional mode this signal is high when the Port A
input register is empty and ready to accept data from the peripheral
device.
B RDY
PIO PIN CONFIGURATION
Figure 3.0-1
19
15
20
14
DO
01
02
CPU
DATA
BUS
03
04
05
06
07
PORT B/ASEL
CONTROL/DATA
13
1
~
40
12
39
10
38
9
3
8
2
7
18
6
5
SEL
zao.PIO
16
A1
A2
A3
A4
A5
PORTA
I/O
A6
A7
ARDY
Asi'B
MK3881
4
PIO
CONTROL
CHIP ENABLE
27
M1
37
iOiffi
36
RD
+5V
GND
28
29
35
30
26
31
11
32
33
25
iNT
INTERRUPT
CONTROL
AO
{
INT ENABLE IN
INT ENABLE OUT
34
BO
B1
B2
B3
B4
B5
B6
B7
23
24
21
22
17
111-101
BRDY
Bsi'"B
PORTB
I/O
lIi-102
4.0 PROGRAMMING THE PIO
4.1 RESET
The zao-Plo automatically enters a reset state when power is applied. The reset state performs the following functions:
1)
Both port mask registers are reset to inhibit all port data bits.
2)
Port data bus lines are set to a high impedance state and the Ready "handshake"
signals are inactive (low). Mode 1 is automatically selected.
3)
The vector address registers are not reset.
4)
Both port interrupt enable flfp flops are reset.
5)
Both port output registers are reset.
In addition to the automatic power on reset, the PIO can be reset by applying an M1 signal
without the presence of a RD or 'fOR'n signal. If no RD or IORO is detected during M1
the PIO will enter the reset state immediately after the M1 signal goes inactive. The purpose
of this reset is to allow a single external gate to generate a reset without a power down
sequence. This approach was required due to the 40 pin packaging limitation. It is recommended that in breadboard systems and final systems with a "Reset" push button that a
M1 reset be implemented for the PIO.
D
7408
CPU RESET
_ ___
.----PIOM1
CPU M1
A software RESET is possible as described in Section 4.4, however, use of this method
during early system debug may not be desirable because of non-functional system hardware
(bus buffers or memory for example).
Once the PIO has entered the internal reset state it is held there until the PIO receives a
control word from the CPU.
4.2 LOADING THE INTERRUPT VECTOR
The PIO has been designed to operate with the zao-cpu using the mode 2 interrupt response. This mode requires that an interrupt vector be supplied by the interrupting device.
This vector is used by the CPU to form the address for the interrupt service routine of that
port. This vector is placed on the zao data bus during an interrupt acknowledge cycle by
the highest priority device requesting service at that time. (Refer to the zao-cpu Technical
Manual for details on how an interrupt is serviced by the CPU). The desired interrupt
vector is loaded into the PIC by writing a control word to the desired port of the PIC with
the following format:
07
06
05
04
03
02
01
V7
V6
V5
V4
V3
V2
V1
00
zO
I
:nifies this control word
is an interrupt vector
111-103
•
00 is used in this case as a flag bit which when low causes V7 thru V1 to be loaded into the
vector register. At interrupt acknowledge time, the vector of the interrupting port will
appear on the Z80 data bus exactly as shown in the format above.
4.3 SELECTING AN OPERATING MOOE
Port A of the PIO may be operated in any of four distinct modes: Mode 0 (output model,
Mode 1 (input mode), Mode 2 (bidirectional model, and Mode 3 (control mode). Note
that the mode numbers have been selected for mnemonic significance; i.e. O=Out, 1=ln,
2=Bidirectional. Port B can operate in any of these modes except Mode 2.
The mode of operation must be established by writing a control word to the PIO in the
following format:
07
06
05
04
M1
MO
x
x
03
02
01
00
X=unused bit
..------~v~--------~
mode word
signifies mode word to be set
Bits 07 and 06 from the binary code for the desired mode according to the following
table:
07
06
MOOE
0
0
o (output)
0
1 (input)
2 (bidirectional)
3 (control)
a
Bits 05 and 04 are ignored. Bits 03-00 must be set to 1111 to indicate "Set Mode".
Selecting Mode o enables any data written. to the port output register by the CPU to be
enabled onto the port data bus. 'The contents of the output register may be changed at any
time by the CPU simply by writing a new data word to the port. Also the current contents
of the output register may be' read back to the Z8D-CPU at any time through the execution
of an input instruction.
With Mode 0 active, a data write from the CPU causes the Ready handshake line of that
port to go high to notify the peripheral that data is available. This signal remains high until
a strobe is received froin the peripheral. The rising edge of the strobe generates an interrupt
(if it has been enabled) and causes the Ready line to go inactive. This very simple handshake
is similar to that used in many peripheral devices.
Selecting Mode 1 puts the port into the input mode. To start handshake operation, the CPU
merely performs an input read operation from the port. This activates the Ready line to
the peripheral to signify that data should be loaded into the empty input register. The peripheral device then strobes data into the port input register using the strobe line. Again, the
rising edge of the strobe causes an interrupt request (if it has been enabled) and deactivates
the Ready signal. Oata may be strobed into the input register regardless of the state of
the Ready signal if care is taken to prevent a data overrun condition.
Mode 2 is a bidirectional data transfer mode which uses all four handshake lines. Therefore
only Port A may be used for Mode 2 operation. Mode 2 operation uses the Port A handIII~ 104
shake signals for output control and the Port B handshake signals for input control. Thus,
both A ROY and BROY may be active simultaneously. The only operational difference
between Mode 0 and the output portion of Mode 2 is that data from the Port A output
register is allowed on to the port data bus only when A STB is active in order to achieve a
bidirectional capability.
Mode 3 operation is intended for status and control applications and does not utilize the
handshake signals. When Mode 3 is selected, the next control word sent to the Pia must
define which of the port data bus lines are to be inputs and which are outputs. The format
of the control word is shown below:
07
06
1/07
1/06
05
04
03
02
DO
01
1/00
I
If any bit is set to a one, then the corresponding data bus line will be used as an input.
Conversely, if the bit is reset, the line will be used as an output.
Ouring Mode 3 operation the strobe signal is ignored and the Ready line is held low. Oata
may be written to a port or read from a port by the Z80-CPU at any time during Mode 3
operation. (An exception to this is when Port A is in Mode 2 and Port B is in Mode 3).
When reading a port, the data returned to the CPU will be composed of input data from
port data bus lines assigned as inputs plus port output register data from those lines assigned
as outputs.
4.4 SETTING THE INTERRUPT CONTROL WORD
The interrupt control word for each port has the following format:
07
06
05
04
03
~----~v
used in Mode 3 only
02
01
DO
v~--------~
signifies interrupt control word
If bit 07=1 the interrupt enable flip flop of the port is set and the port may generate an
interrupt. If bit 07=0 the enable flag is reset and interrupts may not be generated. If an
interrupt occurs while 07=0, it will be latched internally by the Pia and passed onto the
CPU when Pia Interrupts are Re-Enabled (07=1). Bits 06, 05 and 04 are used mainly with
Mode 3 operation, however, setting bit 04 of the interrupt control word during any mode
of operation will cause a pending interrupt to be reset. These three bits are used to allow
for interrupt operation in Mode 3 when any group of the I/O lines go to certain defined
states. Bit 06 (ANO/OR) defines the logical operation to be performed in port monitoring.
If bit 06=1, and ANO function is specified and if 06=0, an OR function is specified. For
example, if the ANO function is specified, all bits must go to a specified state before an
interrupt will be generated while the OR function will generate an interrupt if any specified
bit goes to the active state.
Bit 05 defines the active polarity of the port data bus line to be monitored. If bit 05=1
the port data lines are monitored for a high state while if 05=0 they will be monitored
for a low state.
111-105
•
;,
If bit D4=1 the next control word sent to the PIO must define a mask as follows:
07
06
05
04
03
02
01
00
Only those port lines whose mask bit is zero will be monitored for generating an interrupt.
The interrupt enable flip flop of a port may be set or reset without modifying the rest of
the interrupt control word by using the following command:
x
x
°
a
If an external Asynchronous interrupt could occur while the processor is writing the disable
word to the PIO (03H) then a system problem may occur. If interrupts are enabled in the
processor it is possible that the Asynchronous interrupt will occur while the processor is
writing the disable word to the PIO. The PIO will generate an INT and the CPU will acknowledge it, however, by this time, the PIO will have received the disable word and de-activated
its interrupt structure. The result is that the PIO will not send in its interrupt vector during
the interrupt acknowledge cycle because it is disabled and the CPU will fetch an erroneous
vector resulting in a program fault. The cure for this problem is to disable interrupts within
the CPU with the DI instruction just before the PIO is disabled and then re-enable interrupts
with the EI instruction_ This action causes the CPU to ignore any faulty interrupts produced
by the PIO while it is being disabled. The code sequence would be:
LD A,03H
DI
OUT (PIO),A
EI
DISABLE CPU
DISABLE PIO
ENABLE CPU
111-106
5.0 TIMING
5.1 OUTPUT MODE (MODE 0)
Figure 5.0-1a illustrates the timing associated with Mode 0 operation. An 0!:!!e.ut cycle is
always started by the execution of an output instruction by the CPU. A WR* pulse is
generated by the PIO during a CPU I/O write operation and is used to latch the data from
the CPU data bus into addressed port's (A or B) output register. The rising edge of the
WR* pulse then raises the READY line after the next falling edge of q, to indicate that
data is available for the peripheral device. In most systems, the rising edge of the READY
signal can be used as a latchin!l si!lnal in the peripheral device. The READY signal will
remain active until a positive edge is received from the STROBE line indicating that the
peripheral has taken the data shown in Figure 5.0-1 a. If already active, READY will be
forced low 1Y:. q, cycles after the falling edge of 10RO if the port's output register is written
into. READY will return high on the first falling edge of q, after the rising edge of 10RO
as shown in figure 5.0-1b. This action guarantees that READY is low while port data is
changing and that a positive edge is generated on READY whenever an Output instruction
is executed.
MODE 0 (OUTPUT)TIMING
MODE 0 (OUTPUT) TIMING
Figure 5.0-1a
Figure 5.0-1b
T2
TW
T3
T1
T2
1W
1'3
T1
.,..._-
PORT OUTPUT
18 BITS)
18 BITS)
READY
---+v-'----+--------
READY
STROBE "1", - - - - - - - - - - - - - - - -
STROBE
INT "1"
INT
WR* = RD' CEo CtD . iORa
By connecting READY to STROBE a positive pulse with a duration of one clock period
can be created as shown in Figure 5.0-1c. The positive edge of READY/STROBE will not
generate an interrupt because the positive portion of STROBE is less than the width of M 1
and as such will not generate an interrupt due to the internal logic configuration of the
PIO.
If the PIO is not in a reset status (i.e. a control mode has been selected), the output register
may be loaded before Mode 0 is selected. This allows port output lines to become active
in a user defined state. For example, assume the outputs are desired to become active in
a logic one state, the following would be the initialization sequence:
a) PIO RESET
b) Load Interrupt Vector
c) Select Mode 1 (input) (automatic due ro RESET)
d) Write FF to Data Port
e) Select Mode 0 (Outputs go to "1'5")
f) Enable Interrupt if desired
111-107
MODE 0 (OUTPUT) TIMING· READY TIED TO STROBE
Figure 5.0-1c
T2
PORT OUTPUT
iBBITS)
1'3
T1
------..,.......1---1--+------
\'-_.-JJ
Ml
INT
1W
, . _ _ _ _ _ _ _ _ _ _ _ _ _ __
WR *= RD • CE'
CiD . iORci
5.2 INPUT MODE (MODE 1)
.,"
't'.
Figure 5.0-2 illustrates the timing of an input cycle. The peripheral initiates this cycle using
The STROBE line after the CPU has performed a data read. A low level on this line loads
data into the port input register and the rising edge of the STROBE line activates the
interrupt request line (INT) if the interrupt enable is set and this is the highest priority
requesting device. The next falling edge of the clock line (cI» will then reset the READY
line to an inactive state signifying that the input register is full and further loading must be
inhibited until the CPU reads the data. The CPU will in the course of its interrupt service
routine, read the data from the interrupting port. When this occurs, the positive edge from
the CPU RD signal will raise the READY line with the next low going transition of cI>,
indicating that new data can be loaded into the PIO.
Since RESET causes READY to go Iowa dummy Input instruction may be needed in some
systems to cause READY to go high the first time in order to start "handshaking".
MODE 1 (INPUT) TIMING
MODE 1 (iNPUT) TIMING (NO STROBE INPUT)
Figure 5.0-2a
Figure 5.0-2b
PORT INPUT
(SRITS)
-----\-~--\_,~-----
·.,..".. ..0 .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
'" ..,. - - - - - - - - - - - - - - - - MODE 1 (INPUT) TIMING (NO STROBE INPUT)
If already active, READY will be forced low one and one-half cI> periods following the
falling edge of IORO during a read of a PIO port as shown in Figure 5.0·2b. If the user
strobes data into the PIO only when READY is high, the forced state of READY will
prevent input register data from changing while the CPU is reading the PIO. Ready will
go high again after the rising edge of the IORO as previously described.
a
111·108
5.3 BIDIRECTIONAL MODE (MODE 2)
This mode is merely a combination of Mode 0 and Mode 1 using all four handshake lines.
Since it requires all four lines, it is available only on Port A. When this mode is used on
Port A, Port B must be set to the Bit Control Mode. The same interrupt vector will be
returned for a Mode 3 interrupt on Port B and an input transfer interrupt during Mode 2
operation of Port A. Ambiguity is avoided if Port B is operated in a polled mode and the
Port B mask register is set to inhibit all bits. Furthermore, interrupts from Port B (Mode 3)will not
be generated wl1eR Port A is programmed for Mode 2, as B5TB would have to be active (low) in
order to generate interrupts. (BSfB is normally high).
Figure 5.0-3 illustrates the timing for this mode. It is almost identical to that previously
describec;l for Mode 0 and Mode 1 with the Port A handshake lines used for output control
and the Port B 'Iines used for input control. The difference between the two modes is that,
in Mode 2, data is allowed Out onto the bus only when the A STROBE is low. The rising
edge of this strobe can be used to latch the data into the peripheral since the data will
remain stable until after this edge. The input portion of Mode 2 operates identically to
Mode 1. Note that both Port A and Port B. m.ust have their interrupts enabled to achieve an
interrupt driven bidirectional transfer.
PORT A, MODE 2 (BIDIRECTIONAL) TIMING
Figure 5.0-3
WR*
ARDY
ASTB
~RTA
_______________________{:~~~~------~
DATA BUS
INT
B STB
B ROY
RD
The peripheral must not gate data onto a port data bus while A STB is active. Bus contention is avoided if the peripheral uses B STB to gate input data onto the bus. The PIO uses
the B STB low level to sample this data. The PIO has been designed with' a zero hold time
requirement for the data when latching in this mode so that this simple gating structure can
be used by the peripheral. That is, the data can be disabled from the bus immediately after
the strobe rising edge. Note that if A STB is low during a read operation of Port A (in response to a B STB interrupt) the data in the output register will be read by the CPU instead
of the correct data in the data input register. The correct data is latched in the input register
it just cannot be read by the CPU while A STB is low. If the A STB signal could go low
during a CPU Read, it should be blocked from reaching the A STB input of the PIO while
BRDY is low (the CPU read will occur while BRDY is low as the RD signal returns BRDY
high).
111-109
•
5.4 CONTROL MODE (MODE 3)
The control mode does not utilize the handshake signals and a normal port write or port
read can be executed at any time. When writing, the data will be latched into output registers with the same timing as Mode O. A ROY will be forced low whenever Port A is operated in Mode 3. B ROY will be held low whenever Port B is operated in Mode 3 unless
Port A is in Mode 2.ln the latter case, the state of B RDY will not be affected.
When reading the PIO, the data returned to the CPU will be composed of output register
data from those port data lines assighed as outputs and input register data from those port
data lines assigned as inputs. The-lr:!put register will contain data which was present immediately prior to the falling edge of RD. See Figure 5.0-4.
MODE 3 TIMING
Figure 5.0-4a
Tl
TW*
T3
X
X
PORT
V
DATABUS _____________.A~---D-A-T-A-W-O-R-D-l--~,~--DA-T-A-W-O-R-D
__
2 __J~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
t
INT
DATA MATCH OCCURS
~ERE
\ .......-------+"il}
)
(~' - -_ _ _ _ _ _ _ _- J
DATA IN
*Timing Diagram Refers to Bit Mode Read
L
}I-------------------------------
DATA WORD 1 PLACED ON BUS
An interrupt will be generated if interrupts from the port are enabled and the data on the
port data lines satisfies the logical equation defined by the 8-bit mask control registers.
Another interrupt will not be generated until a change occurs in the status of the logical
equation. A Mode 3 interrupt will be generated only if the result of a Mode 3 logical operation changes from false to true. For example, assume that the Mode 3 logical equation is
an "OR" function; An unmasked port data line becomes active and an interrupt is requested.
If a second unmasked port data line becomes active concurrently with the first, a new
interrupt will not be requested since a change in the result of the Mode 3 logical operation
has not occurred. Note· that port pins defined as outputs can contribute to the logical
equation if their bit positions are unmasked.
I f the result of a logical operation becomes true immediately prior to or during M 1, an
interrupt will be requested after the trailing edge of M1, provided the logical equation remains true after M 1 returns high.
111-110
Figure 5.0-4b is an example of Mode 3 interrupts. The port has been placed in Mode 3
and a R logic selected and signals are defined to be high. All but bits AO and A 1 are masked
out and are not monitored thereby creating a two input positive logic OR gate. In the
timing diagram AO is shown going high and creating an interrupt (INT goes low) and the
CPU responds with an Interrupt Acknowledge cycle (lNTA). The Pia port with its interrupt
pending sends in its Vector and the CPU goes off into the Interrupt Service Routine. AO is
shown going inactive either by itself or perhaps as a result of action taken in the Interrupt
Service Routine (making the logical equation false). An arrow is shown at the point in time
where the Service Routine issues the RETI instruction which clears the Pia interrupt
structure. A 1 is next shown going high making the logical equation-true and generating
another interrupt. Two important points need to be made from this example:
1)
A 1 must not go high before AO goes low or else the logical equation will not go
false - a requirement fo' A 1 to be able to generate an interrupt.
2)
In order for Alto generate an interrupt it must be high after the RETI issued
by AO's Service Routine clears the Pia's Interrupt structure. In other words, if
A 1 were a positive pulse that occurred after AO went low (to make the equation
false) and went low before the RETI had cleared the Interrupt Structure it would
have been missed. The logic equation must become false after the INTA for
AD's service and then must be true or go true after RETI clears the previous
interrupt for another interrupt to occur.
MODE 3 EXAMPLE
Figure 5.0-4b
EQUATION TRUE
AO
A1
~~==D--INTERRUPT
INT
INTA
111-111
111·112
6.0 INTERRUPT SERVICING
Some time after an interrupt is requested by the Pia, the CPU will send out an interrupt
acknowledge (M1 and IORO). During this time the interrupt logic of the Pia will determine
the highest priority port which is requesting an interrupt. (This is simply the device with
its Interrupt Enable Input high and its Interrupt Enable Output low). To insure that the
daisy chain enable lines stabilize, devices are inhibited from changing their interrupt request
status when M 1 is active. The highest priority device places the contents of its interrupt
vector register onto the Z80 data bus during interrupt acknowledge.
Figure 6.0-1 illustrates the timing associated with interrupt requests. During M 1 time, no
new interrupt requests can be generated. This gives time for the Int Enable signals to ripple
through up to four Pia circuits. The Pia with lEI high and lEO low during INTA will place
the 8-bit interrupt vector of the appropriate port on the data bus at this time.
If an interrupt requested by the Pia is acknowledged, the requesting port is 'under service'.
I EO of this port will remain low until a return from interrupt instruction (R ETI) is executed
while I E I of the port is high. If an interrupt request is not acknowledged, I EO will be forced
high for one M1 cycle after the Pia decodes the opcode 'ED'. This action guarantees that
the two byte RETI instruction is decoded by the proper Pia port. See Figure 6.0-2.
INTERRUPT ACKNOWLEDGE TIMING
Figure 6.0·1
LASTT
STATE
INT
lORa
}
r------
IORQANDMi
INDICATE
INTERRUPT
ACKNOWLEDGE
IINTA)
Ml
lEO
lEI " 1 " - - - - - - - - - - - - - - - - - - - - - - - -
RETURN FROM INTERRUPT CYCLE
Figure 6.0-2
\~_--,I
I
\
I
\
I
DO-D7-----~~~--------~G
Ml
\
RD
lEI
,-----------,
lEO of higher priority PIO going high to
- - - - - - - - -
allow lower priority device to decode RETI.
Higher priority device is not under service.
I
lEO
111-113
DAISY CHAIN INTERRUPT SERVICING
F igu re 6.0-3
HIGHEST PRIORITY PORT
"1"
HI
1. PRIORITY INTERRUPT DAISY CHAIN BEFORE ANY INTERRUPT OCCURS.
2. PORT 2A REQUESTS AN INTERRUPT AND IS ACKNOWLEDGED.
UNDER SERVICE
SERVICE SUSPENDED
3. PORT 1B INTERRUPTS, SUSPENDS SERVICING OF PORT 2A.
SERVICE COMPLETE
r----,
SERVICE RESUMED
HI
4. PORT 1B SERVICE ROUTINE COMPLETE, "RETI" ISSUED, PORT 2A SERVICE RESUMED.
5. SECOND "RETI" INSTRUCTION ISSUED ON COMPLETION OF PORT 2A SERVICE ROUTINE.
Figure 6.0-3 illustrates a typical nested interrupt sequence that could occur with four ports
connected in the daisy chain. In this sequence Port 2A requests and is granted an interrupt.
While this port is being serviced, a higher priority port (18) requests and is granted an
interrupt. The service routine for the higher priority port is completed and a RETI instruction is executed to indicate to the port that its routine is complete. At this time the
service routine of the lower priority .port is completed.
111-114
7.0 APPLICATIONS
7.1 EXTENDING THE INTERRUPT DAISY CHAIN
Without any external logic, a maximum of four Z80-P10 devices may be daisy chained
into a priority interrupt structure. This limitation is required so that the interrupt enable
status (lEO) ripples through the entire chain between the beginning of M1, and the beginning of mRTI during an interrupt acknowledge cycle. Since the interrupt enable status cannot
change during M1, the vector address returned to the CPU is assured to be from the highest
priority device which requested an interrupt.
If more than four PIO devices must be accommodated, a "look-ahead" structure may be
used as shown in figure 7.0-1. With this technique more than thirty PIO's may be chained
.
together using standard TTL logic.
A METHOD OF EXTENDING THE INTERRUPT PRIORITY DAISY CHAIN
Figure 7.0-1
Z80CPU
~~
__L-__-L__
~~
__
~
____________-L____
DATA
~
____L-__
~
____- - ,
BUS
7.2 I/O DEVICE INTERFACE
In this example, the Z80-P10 is connected to an I/O terminal device which communicates
over an 8 bit parallel bidirectional data bus as illustrated in figure 7.0-2. Mode 2 operation
(bidirectional) is selected by sending the following control word to Port A:
EXAMPLE I/O INTERFACE
Figure 7.0-2
07
06
05
04
o
x
x
03
02
01
DO
~------~v~--------~
MODE CONTROL
111-115
EXAMPLE 1/0 INTERFACE
Figure 7.0-2
ARDY
.-.
ASTB
BROY
~
BSTB
,~
1
0
S
T
B
DATA BUS
lORa
Z8G-CPU
M1
MK3880
-INT
~
ADDRESS
--"-
,
Z8G-PIO
...,.
MK3881
0
R
a
0
B/A
c/o
},
)
I/O
TERMINAL
CE
I'
f--
BUS
DECODER
Next, the proper interrupt vector is loaded (refer to CPU Manual for details on the operation of the interrupt).
V6
V5
0
R
c
v
PORT DATA BUS
ADDRESS BUS
V7
,~
\~
V4
·1
V3
I.
V2
V1
o
I nterrupts are then enabled by the rising edge of the first M 1 after the interrupt mode
word is set unless that M 1 defines an interrupt acknowledge cycle. I f a mask follows the
interrupt mode word, interrupts are enabled by the rising edge of the first M1 following
the setting of the mask.
Data can now be transferred between the peripheral and the CPU. The timing for this
transfer is as described in Section 5.0.
7.3 CONTROL INTERFACE
A typical control mode application is illustrated in figure 7.0-3. Suppose an industrial
process is to be monitored. The occurrence of any abnormal operating condition is to be
reported to a zaO-cpu based control system. The process control and status word has
the following format:
111-116
0
A
v
07
06
05
04
03
02
01
DO
CONTROL MODE APPLICATION
Figure 7.0-3
PORTA
BUS
INDUSTRIAL
PROCESSING
SYSTEM
Z80-PIO
MK3881
Z80-CPU
MK3880
AO-A1S
ADDRESS
DECODER
The PIO may be used as follows. First Port A is set for Mode 3 operation by writing the
following control word to Port A.
07
06
05
04
x
X
03
02
01
DO
Whenever Mode 3 is selected, the next control word sent to the port must be an I/O select
word. In this example we wish to select port data lines A5, A3, and AO as inputs and so the
following control word is written:
07
06
o
o
05
04
03
o
111-117
02
01
o
o
DO
Next the desired interrupt vector must be loaded (refer to the CPU manual for details);
07
06
05
04
03
02
01
00
V7
V6
V5
V4
V3
V2
V1
VO
An interrupt control word is next sent to the port:
D7
D6
D5
D4
0
Enable
Interrupts
OR
Logic
D3
I
Active
High
D2
D1
DO
0
\
I
y
Mask
Follows
I
Interrupt Control
The mask word following the interrupt mode word is:
D7
D6
D5
D4
o
D3
D2
D1
o
DO
o
Selects A5, A3 and AO to be monitored
Now, if a sensor puts a high level on line A5, A3, or AO, an interrupt request will be generated. The mask word may seleGt any combination of inputs or outputs to cause an interrupt. For example, if the mask word above had been:
D7
o
D6
D5
D4
D3
D2
o
o
D1
DO
o
then an interrupt request would also occur if bit A7 (special Test) of the output register
was set.
Assume that the following port assignments are to be used:
EOH=
E 1H=
E2H=
E3H=
Port
Port
Port
Port
A Data
B Data
A Control
B Control
All port numbers are in hexadecimal notation. This particular assignment of port numbers
is convenient since AO of the address bus can be used as the Port B/A Select and A1 of the
address bus can be used as the Control/Data Select. The Chip Enable would be the decode
of CPU address bits A7 thru A2 (111000). Note that if .only a few peripheral devices are
being used, a Chip Enable decode may not be required since a higher order address bit
could be used directly.
111-118
8.0 PROGRAMMING SUMMARY
8.1 LOAD INTERRUPT VECTOR
V7
V6
VS
V4
x
x
V3
V2
V1
o
8.2 SET MODE
M1
MO
MODE NUMBER
0
1
M1
MO
0
0
0
0
2
3
MODE
Output
Input
Bidirectional
Bit Control
When selecting Mode 3, the next word to the PIO must set the 1/0 Register:
11/071 1/061 I/OS
I
1/0 4 1 1/03 1 1/021 1/01 11/00
110 = 1 Sets bit to Input
1/0 = 0 Sets bit to Output
8.3 SET INTERRUPT CONTROL
USED IN MODE 3 ONLY
111-119
I
If the "mask follows" bit is high, the next control word written to thePIO must be the
mask:
MB = 0, Monitor bit
MB = 1, Mask bit from being monitored
Also, the interrupt enable flip flop of a port may be set or reset without modifying the
rest of the interrupt control word by using the following command:
x
x
o
111-120
o
9.0 ELECTRICAL SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS*
Specified operating range.
-65°e to +150o e
-O.3V to +7V
Temperature Under Bias
Storage Temperature
Voltage On Any Pin With
Respect To Ground
Power Dissipation
.6W
9.2 D. C. CHARACTERISTICS
Table 9.2·1
TA
= ooe to 70oe,
=5 V ±
Vee
Symbol
5% unless otherwise specified
Parameter
Min
Max
Unit
VILC
Clock Input Low Voltage
·0.3
0.80
V
VIHC
Clock Input High Voltage
VIL
Input Low Voltage
VCC-·6
-0.3
VCC+·3
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
Output High Voltage
VCC
0.4
2.4
VOH
70'
ICC
III
Power Supply Current
ILOH
Tri-State Output Leakage Current in Float
10
ILOL
ILD
Tri-State Output Leakage Current in Float
-10
Data Bus Leakage Current in Input Mode
±10
IOHD
Darlington Drive Current
±
Input Leakage Curre':1t
10
Test Condition
I)
V
V
IOL = 2.0mA
V
IOH
= -250JlA
mA
JlA
JlA
JlA
JlA
-1.5
mA
Unit
Test Condition
VIN= 0 to VCC
VOUT=2.4 to VCC
VOUT - 0.4 V
a.;;V IN<;V CC
VOW 1.5V
Port B Only
• 150mA for -4, -10, and -20 devices.
9.3 CAPACITANCE
Table 9.3-1
TA
= 25°e, f = 1 MHz
Symbol
Parameter
Max
C.p
Clock Capacitance
10
pF
Unmeasured Pins
CIN
Input Capacitance
Output Capaci tance
5
pF
Returned to Ground
10
pF
COUT
*Comment
Stresses above those listed under" Absolute Maximum Rating" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliabil ity.
111-121
--io. Z80-PIO
9.4A A.C. CHARACTERISTICS MK3881. MK3881-1 o. MK3881
T A= Doe to 7Doe. Vee = +5V ± 5%. unless otherwise noted
Table 9.4-1A
SIGNAL
tc
C/O SEL
tw (H)
tw (L)
t .. tf
Any Hold Time for Specified Set·Up Time
Control Signal Set·up Time to Rising Edge of Ouring Write or MT
tOI(D)
0 0 -0 7
10RO
UNIT
170
t5 During Read or Write.
nsec
250
nsec
210
nsec
240
nsec
[5J
[5J C L
[5J
= 50pF
Cycle
-M1
ts (M1)
M1 Set-Up Time to Rising Edge of Ouring ii\iTA or M1
Cycle. See Note B.
RD
ts (RO)
RO Set-Up Time to Rising Edge of Ouring Read or M1·
Cycle
ts (PO)
tos (PO)
AO-A7
BO-B7
tF (PO)
. Port Data Set-Up Time to Rising Edge of ~ (Mode 1)
Port Oata Output Oelay from Falling Edge of STROBE
(Mode 2)
230
nsec
nsec
[5J
Oelay to Floating Port Data Bus from Rising Edge of
200
nsec
CL
200
nsec
[5J
Port Oata Stable from Rising Edge of 10RO During 1iiiR
Cycle (Mode 0)
ASTB
BSTB
tw (ST)
Pulse Width,
INT
to (IT)
AROY
BROY
ST'ROliE
nsec
nsec
150
[4J
INT Delay Time from Rising Edge of STR'6'BE
INT Delay Time from Data Match During Mode 3 Operation
490
nsec
to (lT3)
420
nsec
tOH (RY)
Ready Response Time from Rising Edge of 10RO
nsec
tOL (RY)
Ready Response Time from Rising Edge of STROBE
t c+
460
t c+
400
A. 2.5tc >(N-2hOL (l0)+ tOM (10) +tS(lEI) + TTL Buffer Delay, if any
B.
= 50pF
ST'ROliE (Mode 2)
tOI (PO)
--
260
M1 must be active for a minimum
of 2 clock periods to reset the PIO.
[1J tc = tw (H) + tw (L) + tr + tf
[2J Increase tOR(O) by 10 nsec for each 50pF increase in loading up to 200pF max.
[3J
Increase tOi (D) by 10 nsec for each 50pF increase in loading up to 200pF max.
[4J
For Mode 2: tw (ST):>tS(PO)
[5J
Increase these values by 2 nseC for each 10pF increase in
loadin~
up to 100pF max.
111-122
nsec
[5J
CL
[5J
= 50pF
9.4B A.C. CHARACTERISTICS MK3881-4, Z80A-PIO
Table 9.4-1B T A=O°C to 70o e, Vce = +5V:!; 5%, unless otherwise noted
SIGNAL
4>
C/D SEL
nsec
nsec
nsec
nsec
Clock Period
250
[1]
Clock Pulse Width, Clock High
105
2000
tw (4)l)
Clock Pulse Width, Clock Low
105
t" tf
Clock Rise and Fall Times
th
Any Hold Time for Specified Set-Up Time
0
nsec
ts 4>(CS)
Control Signal Set-Up Time to Rising Edge of 4> During
145
nsec
2000
30
COMMENTS
Read or Write CY,cle
380
nsec
nsec
Data Output Delay from Falling edge of 10RO During INTA
250
nsec
tF (D)
Cycle
Delay to Floating Bus (Output Bufler Disable Time)
110
nsec
tS(lEJ)
I EI Set-Up Time to Falling edge of 10RO during INTA Cycle
tDH (10)
lEO Delay Time from Rising Edge of lEI
160
tDL (10)
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of M1 (Interrupt Occurring Just
130
190
tDR(D)
Data Output Delay Fr"m Falling Edge of RD
ts 4>(D)
Data Set-Up Time to Rising Edge of 4> During Write or
tDi (D)
50
M1 Cycle
tDM (10)
Prior to
10RO
UNIT
tw (4)H)
DO-D7
lEO
MAX
tc
CE ETC.
lEI
MIN
PARAMETER
SYMBOL
ts 4>(lR)
Ml)
[2]
Cl
[3]
= 50p~
nsec·
140
nsec
nsec
nsec
[5]
[5] C L
[5]
= 50pF
See Note A.
iORQ Set-Up
Time to Rising Edge of 4>During Read or
115
nsec
90
nsec
115
nsec
Write Cycle
M1
ts 4>(M1)
iiii1 Set-Up Time to Rising Edge of 4>
During INTA or
M1
Cycle. See Note B.
RD
ts 4>(RD)
RD Set-Up Time to Rising Edge of 4>During Read or M1
Cycle
ts (PD)
Port Data Set-Up Time to Rising Edge of STROBE (MODE 1)
tDS (PD)
Port Data Output Delay from Falling Edge of STROBE
210
nsec
[5]
180
nsec
CL
180
nsec
[5]
(Mode 2)
A O-A 7 ,
BO-B7
nsec
230
tF (PD)
Delay to Floating Port Data Bus from Rising Edge of STROBE
= 50pF
(Mode 2)
ASTB
tDi (PD)
Port Data Stable from Rising Edge of IORO During WR
Cycle (Mode 0)
tw (ST)
Pulse Width, STROBE
150
INT
ARBY,
nsec
nsec
[4J
BTSB
-INT Delay Time from
Rising Edge of STROBE
INT Delay Time from Data Match During Mode 3 Operation
440
tD ilT3)
tDH (RY)
Ready Response Time from Rising Edge of IORO
tc +
410
nsec
t c+
nsec
tD lIT)
BRDY
tDL (flY)
Ready Response Time from Rising Edge of STROBE
380
360
A. 2.5t c >(N-2ltDL(l0)+ tDM (10) + tS(lEJ) + TTL Buffer Delay, if any
B. M1 must be active for a minimum of 2 clock periods to reset the PIO.
[1] tc = tw (4) H) + tw (4)L) + tr
+ tf
[2J
Increase tDR(D) by 10 nsec for each 50pF increase in loading up to 200pF max.
[3J
Increase tDI (D) by 10 nsec for each 50pF increase in loading up to 200pF max.
[4] For Mode 2.: tw (ST»tS(PD)
[5J
Increase these values by 2 nsec for each 10pF increase in loading up to 100pF max.
111-123
nsec
nsec
[5]
CL
[5J
= 50pF
OUTPUT LOAD CIRCUIT
TEST POINT
Figure 9.4-1
lN914 OR EQUIVALENT
CL- 60pF on Do-D7
CR 2
CL= SOpF on All Others
CRa
9.5 TIMING DIAGRAM
Timing measurements are made at the following voltages, unless otherwise specified:
"'"
CLOCK
OUTPUT
INPUT
FLOAT
IE.
-
tOlUOI-
---,~,~:,~1-------
READY
fA ROY OR
BROY}
-
SfRO"Br
(A 5TB OR B STB)
(MODE 2)
(MODE 1)
MODE 3)
111-124
,",IAYI -
J~LIRYI
4.2V
2.0V
2.0y
t:N
"0"
O.BV
O.BV
O.8V
+O.5V
10.0 ORDERING INFORMATION
PART NO.
DESIGNATOR
PACKAGE TYPE
MAX CLOCK FREQUENCY
MK3881N
Z80-PIO
Plastic
2.5 MHz
MK3881P
Z80-PIO
Ceramic
2.5 MHz
MK3881J
Z80-PIO
Cerdip
2.5 MHz
MK3881N-4
Z80A-PIO
Plastic
4.0 MHz
MK3881P-4
Z80A-PIO
Ceramic
4.0 MHz
MK3881J-4
Z80A-PIO
Cerdip
4.0 MHz
MK3881P-l0
Z80-PIO
Ceramic
4.0 MHz
111-125
TEMPERATURE
RANGE
0° to 70°C
_40° to +85°C
111-126
Z8D MICROCOMPUTER DEVICES
Technical Manual
MI(3882
COUNTER TIMER
CIRCUIT
111-127
111-128
TABLE OF CONTENTS
SECTION
PAGE
1.0
INTRODUCTION ....................................................................... 111-131
2.0
CTC ARCHITECTURE ................................................................... 111-133
3.0
CTC PIN DESCRIPTION ................................................................. 111-137
4.0
CTC OPERATING MODES .............................................................. 111-141
5.0
CTC PROGRAMMING .................................................................. 111-143
6.0
CTC TIMING .......................................................................... 111-149
7.0
CTC INTERRUPT SERVICING ............................................................ 111-153
8.0
ABSOLUTE MAXIMUM RATINGS ....................................................... 111-157
111-129
111-130
1.0 INTRODUCTION
The Z80-Counter Timer Circuit (CTC) is a programmable component with four independent channels that
provide counting and timing functions for microcomputer systems based on the zao-cpu. The CPU can
configure the CTC channels to operate under various modes and conditions as required to interface with a
wide range of devices. In most applications, little or no external logic is required. The Z80-CTC utilizes
N-channel silicon gate depletion load technology and is packaged in a 28-pin DIP. The Z80-CTC requires
only a single 5 volt supply and a one-phase 5 volt clock. Major features of the Z80-CTC include:
• All inputs and outputs fully TTL compatible.
• Each channel may be selected to operate in either Counter Mode or Timer Mode.
• Used in either mode, a CPU-readable Down Counter indicates number of counts-to-go until zero.
• A Time Constant Register can automatically reload the Down Counter at Count Zero in Counter and
Timer Mode.
• Selectable positive or negative trigger initiates time operation in Timer Mode. The same input is monitored for event counts in Counter Mode.
• Three channels have Zero Count/Timeout outputs capable of driving Darlington transistors.
• Interrupts may be programmed to occur on the zero count condition in any channel.
• Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic.
111-131
111-132
2.0 CTC ARCHITECTURE
2.1
OVERVIEW
A block diagram of the Z80-CTC is shown in Figure 2.0-1. The internal structure of the Z80-CTC consists
of a Z80-CPU bus interface, Internal Control Logic, four sets of CounterfTimer Channel Logic, and Interrupt Control Logic. The four independent counter/timer channels are identified by sequential numbers
from 0 to 3. The CTC has the capability of generating a unique interrupt vector for each separate channel
(for automatic vectoring to an interrupt service routine). The 4 channels can be connected into four contiguous slots in the standard Z80 priority chain with channel number 0 having the highest priority.The
CPU bus interface logic allows the CTC device to interface directly to the CPU with no other external
logic. However, port address decoders and/or. line buffers may be required for large systems.
ZSO-CTC BLOCK DIAGRAM
Figure 2.0-1
+5V GND
'I'
1 1 1
f--
ZERO COUNT/TIMEOUT 0
CHANNEL 0
INTERNAL
I-- CLOCK!TRIGGER 0
CONTROL
LOGIC
DATA
CONTROL
.......
CPU
8
BUS
--
I/O
6
1T
CHANNELl
INTERNAL BUS
11
INTERRUPT
CONTROL
LOGIC
CHANNEL 2
---
ZERO COUNT/TIMEOUT 1
--
CLOCK/TRIGGER 1
---
ZERO COUNT!TIMEOUT 2
--
CLOCK/TRIGGER 2
--
CLOCK/TRIGGER 3
1
3
INTERRUPT
CONTROL
LINES
CHANNEL 3
2.2 STRUCTURE OF CHANNEL LOGIC
The structure of one of the four sets of CounterfTimerChannel Logic is shown in Figure 2.0-2. This logic
is composed of 2 registers, 2 counters and control logic. The registers are an 8-bit Time Constant Register
and an 8-bit Channel Control Register. The counters are an 8-bit CPU-readable Down Counter and an
8-bit Prescaler.
CHANNEL BLOCK DIAGRAM
Figure 2.0-2
CHANNEL
CONTROL
REGISTER
TIME
CONSTANT
REGISTER
(8 BITS)
AND lOGIC
(S BITS)
,
INTERNAL BUS
ZERO COUNTI
-I'
DOWN
COUNTER
PRESCAlER
(8 BITS)
(SBITS)
EXTERNAL CLOCK/TIMER TRIGGER
111-133
I
TIMED UT
2.2.1
THE CHANNEL CONTROL REGISTER AND LOGIC
The Channel Control Register (8-bit) and Logic is written to by the CPU to select the modes and
parameters of the channel. Within the entire eTC device there are four such registers, corresponding to the four Counter/Timer Channels. Which of the four is being written to depends on the encoding of two channel select input pins: CSO and CS1 (usually attached to AO and A 1 of the CPU
address bus). This is illustrated in the truth table below:
ChO
Ch1
Ch2
Ch3
CS1
0
0
CSO
0
1
0
1
1
1
In the control word written to program each Channel Control Register, bit 0 is always set, and the
other 7 bits are programmed to select alternatives on the channel's operating modes and parameters,
as shown in the diagram below. (For a more complete discussion see section 4.0: "CTC Operating
Modes" and section 5.0: "CTC Programming. ")
CHANNEL CONTROL REGISTER
USED IN
TIMER MODE ONLY
2.2.2
THE PRESCALER
Used in the Timer Mode only, the Prescaler is an 8-bit device which can be programmed by the CPU
via the Channel Control Register to divide its input, the System Clock (<1>), by 16 or 256. The output of the Prescaler is then fed as an input to clock the Down Counter, which initially, and every
time it clocks down to zero, is reloaded automatically with the contents of the Time Constant Register. In effect this again divides the System Clock by an additional factor of the time constant.
Every time the Down Counter counts down to zero, its output, Zero Count/Timeout (ZC/TOl, is
pulsed high.
2.2.3
TAE TIME CONSTANT REGISTER
The Time Constant Register is an 8-bit register, used in both Counter Mode and Timer Mode, programmed by the CPU just after the Channel Control Word with an integer time constant value of 1
through 256. This register loads the programmed value into the Down Counter when the CTC is first
initialized and reloads the same value into the Down Counter automatically whenever it counts down
thereafter to zero. If a new time constant is loaded into the Time Constant Register while a channel
is counting or timing, the present down count will be completed before the new time constant is
loaded into the Down Counter. (For details of how a time constant is written to a CTC channel, see
section 5.0: "CTC Programming. ")
111-134
2.2.4
THE DOWN COUNTER
The Down Counter is an 8-bit register used in both Counter Mode and Timer Mode loaded initially,
and later when it counts down to zero, by the Time Constant Register. The Down Counter is decremented by each external clock edge in the Counter Mode, or in the Timer Mode, by the clock output of the Prescaler. At any time, by performing a simple I/O Read at the port address assigned to
the selected CTC channel, the CPU can access the contents of this register and obtain the number of
counts-to-zero. Any CTC channel may be programmed to generate an interrupt request sequence
each time the zero count is reached.
I n channels 0, 1, and 2, when the zero count condition is reached, a signal pulse appears at the corresponding ZC/TO pin. Due to package pin limitations, however, channel 3 does not have this pin and
so may be used only in applications where this output pulse is not required.
2.3
INTERRUPT CONTROL LOGIC
The I nterrupt Control Logic insures that the CTC acts in accordance with Z80 system interrupt protocol
for nested priority interrupting and return from interrupt. The priority of any system device is determined by its physical location in a daisy chain configuration. Two signal lines (lEI and lEO) are provided
in CTC devices to form this system daisy chain. The device closest to the CPU has the highest priority;
within the CTC, interrupt priority is predetermined by channel number, with channel 0 having highest
priority down to channel 3 which has the lowest priority. The purpose of a CTC-generated interrupt, as
with any other peripheral device, is to force the CPU to execute an interrupt service routine. According to
Z80 system interrupt protocol, lower priority devices or channels may not interrupt higher priority devices or channels that have already interrupted and have not had their interrupt service routines completed. However, high priority devices or channels may interrupt the servicing of lower priority devices or
channels.
A CTC channel may be programmed to request an interrupt every time its Down Counter reaches a count
of zero. (To utilize this feature requires that the CPU be programmed for interrupt mode 2.) Some time
after the interrupt request, the CPU will send out an interrupt acknowledge, and the CTC's Interrupt Control Logic will determine the highest-priority channel which is requesting an interrupt within the CTC device. Then if the CTC's I E I input is active, indicating that it has priority within the system daisy chain, it
will place an 8-bit Interrupt Vector on the system data bus. The high-order 5 bits of this vector will have
been written to the CTC earlier as part of the CTC initial programming process; the next two bits will be
provided by the CTC's Interrupt Control Logic as a binary code corresponding to the highest-priority
channel requesting an interrupt; finally the low-order bit of the vector will always be zero according to a
convention described below.
INTERRUPT VECTOR
07
D6
D5
V7
V6
V5
04
V4
D3
D2
D1
DO
V3
X
X
0
I
I
0
0
1
0
1
0
CHANNEL
CHANNEL
CHANNEL
CHANNEL
0
1
2
3
This interrupt vector is used to form a pointer to a location in memory where the address of the interrupt
service routine is stored in a table. The vector represents the least significant 8 bits, while the CPU reads
the contents of the I register to provide the most significant 8-bits of the 16-bit pointer. The address in
memory pointed to will contain the low-order byte, and the next highest address will contain the highorder byte of an address which in turn contains the first opcode of the interrupt service routine. Thus in
mode 2, a single 8-bit vector stored in an interrupting CTC can result in an indirect call to any memory
location.
111-135
zao 16-BIT POINTER (INTERRUPT STARTING ADDRESS)
I REG
CONTENTS
2_3 INTERRUPT CONTROL LOGIC (Cont'd)
There is a Z80 system convention that all addresses in the interrupt service routine table shoLJld have their
low-order byte in an even location in memory, and their high-order byte in the next highest location in
memory, which will always be odd so that the least significant bit of any interrupt vector ,wi II always be
even. Hence the least significant bit of any interrupt vector will always be zero.
The RETI instruction is used at the end of any interrupt service routine to initialize the daisy chain enable
line I EO for proper control of nested priority interrupt handing. The CTC monitors the system data bus
and decodes this instruction when it occurs. Thus the CTC channel control logic will know when the CPU
has completed servicing an interrupt, without any further communication with the CPU being necessary.
111-136
3.0 CTC PIN DESCRIPTION
A diagram of the Z80·CTC pin configuration is shown in Figure 3.0-1. This section describes the function
of each pin.
07· DO
Z80·CPU Data Bus (bi·directional, tri·state)
This bus is used to transfer all data and command words between the Z80·CPU and the Z80·CTC. There
are 8 bits on this bus, of which DO is the least significant.
CS1 . CSO
Channel Select (input, active high)
These pins form a 2·bit binary address code for selecting one of the four independent CTC channels for an
I/O Write or Read (See truth table below.)
ChO
Ch1
Ch2
Ch3
CS1
0
0
CSO
0
1
1
0
1
1
CE
Chip Enable (input, active low)
A low level on this pin enables the CTC to accept control words, Interrupt Vectors, or time constant data.
words from the Z80 Data Bus during an I/O Write cycle, or to transmit the contents of the Down Counter
to the CPU during an I/O Read cycle. In most applications this signal is decoded from the 8 least signifi·
cant bits of the address bus for any of the four I/O port addresses that are mapped to the four Counter/
Timer Channels.
Clock (<1»
System Clock (input)
This single·phase clock is used by the CTC to synchronize certain signals internally.
M1
Machine Cycle One Signal from CPU (input, active low)
When liif'i is active and the R 0 signal is active, the CPU is fetching an instruction from memory. When M 1
is active and the 10RO signal is active, the CPU is acknowledging an interrupt, alerting the CTC to place an
Interrupt Vector on the Z80 Data Bus if it has daisy chain priority and one of its channels has requested
an interrupt.
10RO
Input/Output Request from CPU (input, active low)
The IORO signal is used in conjunction with the CE and RD signals to transfer data and Channel Control
Words between the Z80·CPU and the CTC. During a CTC Write Cycle, 10RO and CE must be true and
RD false. The CTC does not receive a specific write signal, instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read Cycle,'"j'(j"RQ, CE and RD must be active to place the contents
of the Down Counter on the Z80 Data Bus. Ifi'ORCl and i\iil are both true, the CPU is acknowledging an
interrupt request, and the highest·priority interrupting channel will place its Interrupt Vector on the Z80
Data Bus.
111·137
3.0 CTC PIN DESCRIPTION (CONT'D)
AD
Read Cycle Status from the CPU (input, active low)
The RD signal is used in conjunction with the iC5RCi and CE signals to transfer data and Channel Control
Words between the ZaD-CPU and the CTC. During a CTC Write Cycle, lORa and CE must be true and
R D false. The CTC does not receive a specific write signal, instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read Cycle, lORa, CE and RD must be active to place the contents
of the Down Counter on the zao Data Bus.
lEI
Interrupt Enable In (input, active high)
This signal is used to help form a system-wide interrupt daisy chain which establishes priorities when more
than one peripheral device in the system has interrupting capability. A high level on this pin indicates that
no other interrupting devices of higher priority in the daisy chain are being serviced by the zao-cpu.
lEO
Interrupt Enable Out (output, active high)
The I EO signal, in conjunction with I E I, is used to form a system-wide interrupt priority daisy chain. I EO
is high only if I E I is high and the CPU is not servicing an interrupt from any CTC channel. Thus this signal blocks lower priority devices from interrupting while a higher priority interrupting device is being
serviced by the CPU.
Interrupt Request (output, open drain, active low)
This signal goes true when any CTC channel which has been programmed to enable interrupts has a zerocount condition in its Down Counter.
Reset (input, active low)
This signal stops all channels from counting and resets channel interrupt enable bits in all control registers,
thereby disabling CTC-generated interrupts. The ZC/TO and I NT outputs go to their inactive states, I EO
reflects I EI, and the CTC's data bus output drivers go to the high impedance state.
CLK/TRG3-CLK/TRGO
External Clock/Timer Trigger (input, user-selectable active high or low)
There are four CLK/TRG pins, corresponding to the four independent CTC channels. In the Counter
Mode, every active edge on this pin decrements the Down Counter. In the Timer Mode, an active edge on
this pin initiates the timing function. The user may select the active edge to be either rising ,or falling.
ZC/T02-ZC/TOO
Zero Count/Timeout (output, active high)
There are three ZC/TO pins, corresponding to CTC channels 2 through O. (Due to package pin limita:
tions channel 3 has no ZC/TO pin.) In either Counter Mode or Timer Mode, when the Down Counter
decrements to zero an active high going pulse appears at this pin.
111-138
Z80-CTC PIN CONFIGURATION
Figure 3.0-1
DO
23
25
CLT/TRGO
ZC/TO O
D1
D2
CPU
DATA BUS
D3
CLK/TRG 1
D4
ZC/T01
D5
D6
CLK/TRG2
D7
ZC/T02
MK3882
Z80-CTC
CSO
CS1
CTC
CONTROL
CHIP
ENABLE
M1
lORa
MK3882-4
Z80A-CTC
RD
RESET
+5V
GND
ENA~~:
INTERRUPT {INT
CONTROL
IN
INT ENABLE
OUT
11
111-139
CHANNEL
SIGNALS
111-140
4.0 CTC OPERATING MODES
At power-on, the Z80-CTC state is undefined. Asserting RESET puts the CTC in a known state. Before
any channel can begin counting or timing, a Channel Control Word and a time constant data word must be
written to the appropriate registers of that channel. Further, if any channel has been programmed to
enable interrupts, an Interrupt Vector word must be written to the CTC's Interrupt Control logic. (For
further details, refer to section 5.0: "CTC Programming.") When the CPU has written all of these words to
the CTC, all active channels will be programmed for immediate operation in either the Counter Mode or
the Timer Mode.
4.1
CTC COUNTER MODE
In this mode the CTC counts edges of the ClK!TRG input. The Counter Mode is programmed for a
channel when its Channel Control Word is written with bit 6 set. The Channel's External Clock (ClK/
TRG) input is monitored for a series of triggering edges; after each, in synchronization with the next rising edge of (the System Clock), the Down Counter (which was initialized with the time constant data
word at the start of any sequence of down-counting) is decremented. Although there is no set-up time
requirement between the triggering edge of the External Clock and the rising edge of <1>, (Clock), the
Down Counter will not be decremented until the following pulse. (See the parameter ts(CK) in section
8.3: "A.C. Characteristics.") A channels's External Clock input is pre-programmed by bit 4 of the Channel Control Word to trigger the decrementing sequence with either a high or a low going edge.
I n any of Channels 0, 1, or 2, when the Down Counter is successively decremented from the original time
constant until finally it reaches zero, the Zero Count (ZC/TO) output pin for that channel will be pulsed
active (high). (However, due to package pin limitations, channel 3 does not have this pin and so may
only be used in applications where this output pulse is not required.) Further, if the channel has been so
pre-programmed by bit 7 of the Channel Control Word, an interrupt request sequence will be generated.
(For more details, see section 7.0: "CTC Interrupt Servicing.")
As the above sequence is proceeding, the zero count condition also results in the automatic reload of the
Down Counter with the original time constant data word in the Time Constant Register. There is no
interruption in the sequence of continued down-counting. If the Time Constant Register is written to
with a new time constant data word while the Down Counter is decrementing, the present count will be
completed before the new time constant will be loaded into the Down Counter.
CHANNEL - COUNTER MODE
Figure 4.1-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
TIME
CONSTANT
REGISTER
(8 BITS)
INTERNAL BUS
.
DOWN
COUNTER
(8 BITS)
EXTERNAL CLOCK/TIMER TRIGGER
111-141
ZERO COUNT/
TIMEOUT
4.2
CTC TIMER MODE
In this mode the CTC generates timing intervals that are an integer value of the system clock period. The
Timer Mode is programmed for a channel when its Channel Control Word is written with bit 6 reset. The
channel then may be used to measure intervals of time based on the System Clock period. The System
Clock is fed through two successive counters, the Prescaler and the Down Counter. Depending on the
pre-programmed bit 5 in the Channel Control Word, the Prescaler divides the System Clock by a factor of
either 16 or 256. The output of the Prescaler is then used as a clock to decrement the Down Counter,
which may be pre-programmed with any time constant integer between 1 and 256. As in the Counter
Mode, the time constant is automatically reloaded into the Down Counter at each zero-count condition,
and counting continues. Also at zero-count, the channel's Time Out (ZC/TO) output (which is the output of the Down Counter) is pulsed, resulting in a uniform pulse train of precise period given by the product.
tc * P * TC
where tc is the System Clock period, P is the Prescaler factor of 16 or 256 and TC is the pre-programmed time constant.
Bit 3 of the Channel Control Word is pre-programmed to select whether timing will be automatically
initiated, or whether it will be initiated with a triggering edge at the channel's Timer Trigger (CLK/TRG)
input. If bit 3 is reset the timer automatically begins operation at the start of the CPU cycle following
the I/O Write machine cycle that loads the time constant data word to the channel. If bit 3 is set the
timer begins operation on the second succeeding rising edge of after the Timer Trigger edge following
the loading of the time constant data word_ If no time constant data word is to follow then the timer
begins operation on the second succeeding rising edge of after the Timer Trigger edge following the
control word write cycle. Bit 4 of the Channel Control Word is pre-programmed to select whether the
Timer Trigger will be sensitive to a rising or falling edge. Although there is no set-up requirement between the active edge of the Timer Trigger and the next rising edge of <1>. If the Timer Trigger edge
occurs closer than a specified minimum set-up time to the rising edge of <1>, the Down Counter will not
begin decrementing until the following rising edge of <1>. (See parameter ts(TR) in section 8.3: "A.C.
Characteristics". )
If bit 7 in the Channel Control Word is set, the zero-count condition in the Down Counter, besides
causing a pulse at the channel's Time Out pin, will be used to initiate an interrupt request sequence, (For
more details, see section 7.0: "CTC Interrupt Servicing.")
CHANNEL - TIMER MODE
Figure 4.2-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
TIME
CONSTANT
REGISTER
(8 BITS)
INTERNAL BUS
DOWN
COUNTER
(8BITS)
PRESCALER
(8 BITS)
EXTERNAL CLOCK/TIMER TRIGGER
I
111-142
ZERO COUNT/
TIMEO UT
5.0
CTC PROGRAMMING
Before a ZBO-CTC channel can begin counting or timing operations, a Channel Control Word and a Time
Constant data word must be written to it by the CPU. These words will be stored in the Channel Control
Register and the Time Constant Register of that channel. In addition, if any of the four channels have
been programmed with bit 7 of their Channel Control Words to enable interrupts, an Interrupt Vector
must be written to the appropriate register in the CTC. Due to automatic features in the Interrupt Control Logic, one pre-programmed Interrupt Vector suffices for all four channels.
5.1
LOADING THE CHANNEL CONTROL REGISTER
To load a Channel Control Word, the CPU performs a normal I/O Write sequence to the port address
corresponding to the desired CTC channel. Two CTC input pins, namely CSO and CS1, are used to form
a 2-bit binary address to select one of four channels within the device. (For a truth table, see section
2.2.1: "The Channel Control Register and Logic".) In many system architectures, these two input pins
are connected to Address Bus lines AO and A 1, respectively, so that the four channels in a CTC device
will occupy contiguous I/O port addresses. A word written to a CTC channel will be interpreted as a
Channel Control Word, and loaded into the Channel Control Register, its bit 0 is a logic 1. The other
seven bits of this word select operating modes and conditions as indicated in the diagram below. Following the diagram the meaning of each bit will be discussed in detail.
CHANNEL BLOCK DIAGRAM
Figure 5.1-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(8 BITS)
...
TIME
CONSTANT
REGISTER
(8 BITS)
..
INTERNAL BUS
.. ..
DOWN
COUNTER
(8 BITS)
PRESCALER
(8 BITS)
EXTERNAL CLOCK/TIMER TRIGGER
CHANNEL CONTROL REGISTER
INTERRUPT
ENABLE
USED IN TIMER
MODE ONLY
USED IN TIMER
MODE ONLY
111-143
ZERO COUNT/
TlMEO UT
5.1
LOADING THE CHANNEL CONTROL REGISTER (CONT'D)
Bit 7 = 1
The channel is enabled to generate an interrupt request sequence every time the Down Counter reaches a
zero-count condition. To set this bit to 1 in any of the four Channel Control Registers necessitates that
an Interrupt Vector also be written to the CTC before operation begins. Channel interrupts may be programmed in either Counter Mode or Timer Mode. If an updated Channel Control Word is written to a
channel already in operation, with bit 7 set, the interrupt enable selection will not be retroactive to a pre.
ceding zero-count condition.
Bit 7 = 0
Channel interrupts disabled. Any pending interrupt by that channel will be cleared.
Bit 6 = 1
Counter Mode selected. The Down Counter is decremented by each triggering edge of the External
Clock (CLK/TRG) input. The Prescaler is not used.
Bit 6 = 0
Timer Mode selected. The Prescaler is clocked by the System Clock <1>, and the output of the Prescaler in
turn clocks the Down Counter. The output of the Down Counter (the channel's ZC/TO output) is a
uniform pulse train of period given by the product.
tc * P * TC
where tc is the period of System Clock <1>, P is the Prescaler factor of 16 or 256, and TC is the time
constant data word.
Sit 5
=1
(Defined for Timer Mode only.) Prescaler factor is 256.
Bit 5 = 0
(Defined for Timer Mode only.) Prescaler factor is 16.
INTERRUPT
ENABLE
USED IN TIMER
MODE ONLY
Bit 4
USED IN TIMER
MODE ONLY
=1
TIME R MODE - positive edge trigger starts timer operation.
COUNTER MODE - positive edge decrements the down counter.
Bit 4
=0
TIME R MODE - negative edge trigger starts timer operation.
COUNTER MODE - negative edge decrements the down counter.
111-144
5.1
LOADING THE CHANNEL CONTROL REGISTER (CONT'D)
Bit 3
=1
Timer Mode Only - External trigger is valid for starting timer operation after rising edge of T2 of the
machine cycle following the one that loads the time constant. The Prescaler is decremented 2 clock
cycles later if the setup time is met, otherwise 3 clock cycles. Once timer has been started it will free run
at the rate determined by the Time Constant register.
Bit 3 = 0
Timer Mode Only - Timer begins operation on the rising edge of T2 of the machine cycle following the
one that 'loads the time constant.
Bit 2 = 1
The time constant data word for the Time Constant Register will be the next word written to this channel. If an updated Channel Control Word and time constant data word are written to a channel while it
is already in operation, the Down Counter will continue decrementing to zero before the new time constant is loaded into it.
Bit 2
=0
No time constant data word for the Time Constant Register should be expected to follow. To program
bit 2 to this state implies that this Channel Control Word is intended to update the status of a channel already in operation, since a channel will not operate without a correctly programmed data word in the
Time Constant Register, and a set bit 2 in this Channel Control Word provides the only way of writing to
the Time Constant Register.
Bit 1 = 1
Reset channel. Channel stops counting or timing. This is not a stored condition. Upon writing into this
bit a reset pulse discontinues current channel operation, however, none of the bits in the channel control
register are changed. If both bit 2 = 1 and bit 1 = 1 the channel will resume operation upon loading a
time constant.
Bit 1 = 0
Channel continues current operation.
5.2
DISABLING THE CTC'S INTERRUPT STRUCTURE
If an external Asynchronous interrupt could occur while the processor is writing the disable word to the
CTC (01 H); a system problem may occur. If interrupts are enabled in the processor it is possible that the
Asynchronous interrupt will occur while the processor is writing the disable word to the CTC. The CTC
will generate an I NT and the CPU will acknowledge it, however, by this time, the CTC will have received
the disable word and de-activated its interrupt structure. The result is that the CTC will not send in its
interrupt vector during the interrupt acknowledge cycle because it is disabled and the CPU will fetch an
erroneous vector resulting in a program fault. The cure for this problem is to disable interrupts within
the CPU with the D I instruction just before the CTC is disabled and then re-enable interrupts with the E I
instruction. This action causes the CPU to ignore any interrupts produced by the CTC while it is being
disabled. The code sequence would be:
LD A, 01 H
DI
OUT (CTC), A
EI
111-145
; DISABLE CPU
DISABLE CTC
; ENABLE CPU
5.3
LOADING THE TIME CONSTANT REGISTER
A channel may not begin operation in either Timer Mode or Counter Mode unless a time constant data
word is written into the Time Constant Register by the CPU. This data word will be expected on the
next I/O Write to this channel following the I/O Write of the Channel Control Word, provided that bit 2
of the Channel Control Word is set. The time constant data word may be an integer value in the range 1256. If all eight bits in this word are zero, it is interpreted as 256. If a time constant data word is loaded
to a channel already in operation, the Down Counter will continue decrementing to zero before the new
time constant is loaded from the Time Constant Register to the Down Counter.
TIME CONSTANT REGISTER
Os
05
DO
TCs
TC5
TCo
MSB
CHANNEL BLOCK DIAGRAM
LSB
Figure 5.3-0
CHANNEL
CONTROL
REGISTER
AND LOGIC
(SBITS)
.
TIME
CONSTANT
REGISTER
(SBITS)
INTERNAL BUS
DOWN
COUNTER
(S BITS)
PRESCALER
(SBITS)
,(,
ZERO COUNT/
TIMEOUT
EXTERNAL CLOCK/TIMER TRIGGER
5.4
LOADING THE INTERRUPT VECTOR REGISTER
The ZaO-CTC has been designed to operate with the zao-cpu programmed for mode 2 interrupt response. Under the requirements of this mode, when a CTC channel requests an interrupt and is acknowledged, a 16-bit pointtlr must be formed to obtain a corresponding interrupt service routine starting address from a table in memory. The upper a bits of this pointer are provided by the CPU's I register, and
the lower a bits of the pointer are provided by the CTC in the form of an Interrupt Vector unique to the
particular channel that requested the interrupt. (For further details, see sElction 7.0: "CTC Interrupt
Servicing".)
MODE 2 INTERRUPT OPERATION
Desired starting address pOinted to by:
INTERRUPT
SERVICE
ROUTINE
STARTING
ADDRESS
TABLE
<
LOWORDER } .
HIGH ORDER
'--_ _ _---'_ _ _ _--'----'
111-146
5.4 LOADING THE INTERRUPT VECTOR REGISTER (Cont'd)
The high order 5 bits of this Interrupt Vector must be written to the CTC in advance as part of the initial
programming sequence. To do so, the CPU must write to the I/O port address corresponding to the CTC
channel 0, just as it would if a Channel Control Word were being written to that channel, except that bit
o of the word being written must contain a O. (As explained above in section 5.1, if bit 0 of a word
written to a channel were set to 1, the word would be interpreted as a Channel Control Word, so a 0 in
bit 0 signals the CTC to load the incoming word into the Interrupt Vector Register.) Bits 1 and 2, however are not used when loading this vector. At the time when the interrupting channel must place the
Interrupt Vector on the Z80 Data Bus, the Interrupt Control Logic of the CTC automatically supplies a
binary code in bits 1 and 2 indentifying which of the four CTC channels is to be serviced.
INTERRUPT VECTOR REGISTER
I,
D7
D6
D5
D4
D3
V7
V6
V5
V4
V3
V
,
I
D2
D1
DO
X
X
0
I
SUPPLIED BY USER
0
0
1
1
,
I
o CHANNEL
1 CHANNEL
o CHANNEL
0
1
2
1 CHANNEL 3
V
(Highest Priority) .
(Lowest Priority)
I
AUTOMATICALLY INSERTED BY ZaO-CTC
111-147
111-148
6.0
CTC TIMING
This section illustrates the timing relationships of the relevant CTC pins for the following types of operation: writing a word to the CTC, reading a word from the CTC, counting, and timing. Elsewhere in this
manual may be found timing diagrams relating to interrupt servicing (section 7.0) and an A.C. Timing
Diagram which quantitatively specifies the timing relationships (section 8.4).
6.1
CTC WRITE CYCLE
Figure 6.1-0 illustrates the timing associated with the CTC Write Cycle. This sequence is applicable to
loading either a Channel Control Word, an Interrupt Vector, or a time constant data word.
In the sequence shown, during clock cycle T1, the Z80-CPU prepares for the Write Cycle with a false
(high) signal at CTC input pin RD (Read). Since the CTC has no separate Write signal input, it generates
its own internally form the false RD input. Later, during clock cycle T2, the Z80-CPU initiates the Write
Cycle with true (low) signals at CTC input pins lORa (I/O Request) and CE (Chip Enable). (Note: iVi1
must be false to distinguish the cycle form an interrupt acknowledge.) Also at this time a 2-bit binary
code appears at CTC inputs CS1 and CSO (Channel Select 1 and 0), specifying which of the four CTC
channels is being written to, and the word being written appears on the Z80 Data Bus. Now everything is
ready for the word to be latched into the appropriate CTC internal register in synchronization with the
rising edge beginning clock cycle T3. No additional wait states are allowed.
CTC WRITE CYCLE
Figure 6.1-0
CSO-l, CE
________
~)(~_____C_H_A__N_N_E_L_A_D_D_R__ES_S_____J)(~_________
\~-----'/
Ml
DATA
"1"
_____________~X~______
IN
______
~X~
_____
"AUTOMATICALLY INSERTED BY Z80-CPU
6.2
CTC READ CYCLE
Figure 6.2-0 illustrates the timing associated with the CTC Read Cycle. This sequence is used any time
the CPU reads the current contents of the Down Counter. During clock cycle T2, the Z80-CPU initiates
the Read Cycle with true signals at input pins RD (Read), lORa (I/O Request), and CE (Chip Enable).
also at this time a 2-bit binary code appears at CTC inputs CS1 and CSO (Channel Select 1 and 0), specifying which of the four CTC channels is being read from. (Note: M1 must be false to distinguish the
cycle form an interrupt acknowledge.) On the rising edge of the cycle T3 the valid contents of the Down
Counter as of the rising edge of cycle T2 will be available on the Z80 Data Bus. No additional wait states
are allowed.
111-149
CTC READ CYCLE
Figure 6.2-0
-'X'-___
CSo-" CE _ _ _ _
---IX'-__. . . . . __
C_H_A_N_N_E_l_A_D_D_R_E_SS
__
IORQ
\~-----'/
RD
\'---_ _--J/
"1" - - - - - - - - - - - - - - - - - - - - - - - - -
M1
DATA
------------«
OUT
)~---
'AUTOMATICALLY INSERTED BY Z80-CPU
6.3
CTC COUNTING AND TIMING
Figure 6.3-0 illustrates the timing diagram for the CTC Counting and Timing Modes.
CTC COUNTING AND TIMING
Figure 6.3-0
ClK
--~/
\-----
INTERNAL
COUNTER
_ _ _ _ _ _- ' /
ZC/TO
_ _--J/
\ _______
_----J/
___----J/
\'--------
ZERO COUNT
\'--_ _ _ _ _ __
(I>
TRG
INTERNAL
TIMER
START TIMING
111-150
6.3 CTC COUNTING AND TIMING (Cont'd)
In the Counter Mode, the edge (rising edge is active in this example) form the external hardware connected to pin CLK/TRG decrements the Down Counter in synchronization with the System Clock -----
7.2
RETURN FROM INTERRUPT CYCLE
Figure 7.2-0 illustrates the timing associated with the RETI Instruction. This instruction is used at the
end of an interrupt service routine to initialize the daisy chain enable lines for proper control of nested
priority interrupt handling. The CTC decodes the two-byte RETI code internally and determines whether it is intended for a channel being serviced.
zao
When several
peripheral chips are in the daisy chain I E I will become active on the chip currently
under service when an EDH opcode is decoded. If the following opcode is 4DH, the peripheral being serviced will be re-initialized and its I EO will become active. Additional wait states are allowed.
<
RETURN FROM INTERRUPT CYCLE
Figure 7.2-0
T1
T3
JL
M1
\
/
RD
~
/
00-07
lEI
lEO
7.3
T2
T4
T1
T2
T3
T4
T1
/
\
\
/
0
@)
--------
_ _ _ _ _ _ _ --1 I
________________________-J/
DAISY CHAIN INTERRUPT SERVICING
Figure 7.3-0 illustrates a typical nested interrupt sequence which may occur in the CTC. In this example,
channel 2 interrupts and is granted service. While this channel is being serviced, higher priority channel 1
interrupts and is granted service. The service routine for the higher priority channel is completed, and a
RETI instruction (see section 7.2 for further details) is executed to signal the channel that its routine is
complete. At this time, the service routine of the lower priority channel 2 is resumed and completed.
<
DAISY CHAIN INTERRUPT SERVICING
Figure 7.3-0
111-154
7.4
USING THE CTC AS AN INTERRUPT CONTROLLER
All of the Z80 family parts contain circuitry 'for prioritizing interrupts and supplying the vector to the
CPU. However, in many Z80 based systems interrupts must be processed from devices which do not contain this interrupt circuitry. To hahdle this requirement the MK3882 CTC can be used, providing prioritized, independently vectored, maskable, edge selectable, count programmable external interrupt inputs.
The MK3882 parts may be cascaded, expanding the system to as many as 256 interrupt inputs.
Each MK3882 contains 4 channels with counter inputs able to interrupt upon one or more (up to 256)
edge transitions. The active transition may be programmed to be positive or negative. Each of the 4
channels has a programmable vector which is used in powerful Z80 mode 2 interrupt processing. When
an interrupt is processed the vector is combined with the CPU I register to determine where the interrupt
service routine start address is located. Additionally, priority resolution is handled within the MK3882
when more than one interrupt request is made simultaneously. When more than one MK3882 is used,
the prioritizing is done, with the I E I /1 EO chain resolving inter-chip priorities. Each channel can be independently "masked" by disabling that channel's local interrupt.
When programming the MK3882 to handle an input as a general purpose interrupt line, the channel is put
in the counter mode, with the count set to 1, the active edge specified and the vector is loaded. When
the programmed edge occurs a mode 2 interrupt will be generated by the CTC and the Z80-CPU can
vector directly to the service routine forthe non-Z80 peripheral device. Note that afterth'e interrupt, the CTC'
down counter is automatically reloadec;l with a count of one and the CTC channel begins looking for another
active edge after the RETI of the interrupt routine. Therefore, once a particular channel is under service, no
active edges will be recognized by that channel until execution ofthe RETI instruction of the corresponding
interrupt routine. Of course, other channels of the CTC can generate interrupts and/or pending interrupts
asynchronously, depending on their priority.
CTC AS AN INTERRUPT CONTROLLER
..,
Figure 7.4-0
18
A,
TAG I
10 iORQ
iOii'Q
..
,,"'., ,
14
"'
'
iiii
12
iiii'
INTERRUPT
0
INTERRUPT
,
INTERRUPT
,
eso
19 CSI
0,
"
Wi
TAG2 21
iii
TAG:5 20
CE
lEO
"
+SV GND
To
ZBO·CPU
"
lEI
L -_ _-+-_"'I19 CSI
L -_ _ _
TAG I 22
INTERRuPT
"
INTERRUPT
5
INTERRUPT
7
I--_''''l0 iOiiQ
L -_ _ _--j_---"'14 iii
L -_ _ _ _-+_~6Ro
TAG 2. 21
Hte:5 20
LOWEST
PRIORITY
MK 3882'S
111-155
111-156
8.0
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .......................................... Specified Operating Range
Storage Temperature .................................................... _65° C to +150° C
Voltage on Any Pin with Respect to Ground .................................... -0.3V to +7V
Power Dissipation ................................................................ 0.8V
8.1 D. C. CHARACTERISTICS
TA = O°C to 70°C, Vcc = 5V ± 5% unless otherwise specified
SYMBOL
V,LC
V,HC
V,L
V,H
VOL
VOH
ICC
'll
'LOH
'LOL
IOHD
PARAMETER
Clock Input Low Voltage
Clock I nput High Voltage (1)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Tri-State Output Leakage Current In Float
Tri-State Output Leakage Current In Float
Darlington Drive Current
MIN
-0.3
MAX
0.80
VCC-·6 VCC +.3
-0.3
0.8
2.0
VCC
0.4
2.4
120
±10
10
-10
-1.5
UNIT
V
V
V
V
V
V
mA
J.l.A
J.l.A
J.l.A
mA
TEST CONDITION
IOL=2mA
IOH = -250 J.l.A
TC = 400 nsec**
V,N = 0 to VCC
VOUT = 2.4 to VCC
VOUT = O.4V
VOH - 1.5V
**TC = 250 nsec for MK 3882-4
8.2 CAPACITANCE
TA=25°C,f= 1 MHz
SYMBOL
C
C'N
COUT
PARAMETER
Clock Capacitance
Input Capacitance
Output Capacitance
MAX
20
5
10
UNIT TEST CONDITION
pF
Unmeasured Pins
pF
Returned to Ground
pF
'COMMENT
Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
111-157
II
8.3 A.C. CHARACTERISTICS MK 3882, MK 3882-10, Z80-CTC
TA
= 0°
C to 70° C, Vcc
Signal
Symbol
tc
tW(H)
tW(L)
tr, tf
tH
tS(CS)
CS, CE, etc.
tDR(D)
ts'I>(D)
tDI(D)
DO-D7
tF(D)
lEI
tS(IEI)
lEO
tDH(IO)
tDl(IO)
tDM(IO)
IORO
= +5 V ±
5%, unless otherwise noted
Parameter
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Width, Clock low
Clock Rise and Fall Times
Any Hold Time for Specified Setup Time
Control Signal Setup Time to Rising
Edge of During Read or Write Cycle
Data Output Delay from Rising Edge of
RD During Read Cycle
Data Setup Time to Rising Edge of 'I>
During Write or M 1 Cycle
Data Output Delay from Falling Edge
of IORO During INTA Cycle
Delay to Floating Bus (Output Buffer
Disable Time)
lEI Setup Time to Falling Edge of IORO
During I NT A Cycle
I EO Delay Time from Rising Edge of I E I
lEO Delay Time from Falling Edge of lEI
I EO Delay from Falling Edge of M.L
(I nterrupt Occurring just Prior to M 1)
IORO Setup Time to Rising Edge of 'I>
During Read or Write Cycle
tS'I>(M1) M1 Setup Time to Rising Edge of
During INTA or M1 Cycle
tS'I>(RD) RD Setup Time to Rising Edge of 'I>
During Read or M 1 Cycle
tDCK(IT) Il\IT Delay Time from Rising Edge of
ClK/TRG
I NT Delay Time from Rising Edge of <\>
tD'I>(IT)
Clock Period
tC(CK)
Clock and Trigger Rise and Fall Times
tr, tf
tS(CK)
Clock Setup Time to Rising Edge of
for Immediate Count
Trigger Setup Time to Rising Edge of
tS(TR)
for Enabling of Prescaler on Following
Rising Edge of 'I>
ts'I>(IR)
1IJr1
RD
fI\lT
Min
Max
Unit
400
170
170
(1 )
2000
2000
30
ns
ns
ns
ns
ns
ns
480
ns
0
160
Comments
(2)
ns
60
340
ns
230
ns
(2)
ns
200
220
190
300
ns
ns
ns
250
ns
210
ns
240
ns
(3)
(3)
(3)
2tC(, ZC/TO High
ZC/TO Delay Time from Falling Edge of
190
'I> , ZC/TO low
OUTPUT lOAD CIRCUIT
ZC/TOO-2
tDl(ZC)
NOTES:
tc = tw( oll1t'IWI\e speci/red
~H--'WI'I'HI
--f \tw('i>L) --:
T2
T3ITW
n
:--
I... ·--·~ tc -------I
,.- .
CE
......... tOl(O)-.
-----------+"".... ts<,,(IRll--
lEI
1-----+·sIIEII
EIO
iNl'
rlCOUNTEA MODEl
ClKI
)
TRGO_3
l
llTiMER MODEl
ZC/TO O_2
111-159
8.5 AC. CHARACTERISTICS MK 3882-4.Z80A-CTC
TA
= 0°
C to 70° C, Vcc
Signal
Symbol
ct>
CS,
cr, etc
DO-D7
lEI
lEO
IIURQ
IM1
ImJ
INT
= +5 V ± 5%, unless otherwise noted
Parameter
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Width, Clock Low
Clock Rise and Fa" Times
Any Hold Time for Specified Setup Time
Control Signal Setup Time to Rising Edge
of ct> Durin!:! Read or Write Cvcle
Data Output Delay from Fa"ing Edge of
tDR(D)
RD During Read Cycle
Data Setup Time to Rising Edge of ct>
tSct>( D)
During Write or M 1 Cycle
Data Output Delay form Falling Edge
tD liD)
of IORO During INTA Cycle
Delay to Floating Bus (Output Buffer
tF(D)
Disable Time)
tS(I EI)
lEI Setup Time to Fa"ing Edge of i'ORTI
During I NT A Cycle
lEO Delay Time from Rising Edge of lEI
tDH(IO)
lEO Delay Time from Fa"ing Edge of lEI
tDL(10)
lEO Delay from Fa"ing Edge ofiiiil
tDM(10)
(Interrupt Occurring just Prior to M1)
tSct>(I R)
1URU Setup Time to Rising Edge of ct>
During Read or Write Cycle
tsct>(M1) M1 Setup Time to Rising Edge of ( RD) RD Setup Time to Rising Edge of ct>
During Read or M 1 Cycle
tDCK(IT) INT Delay Time from Rising Edge of
CLK/TRG
tDct>( IT) TNT Delay Time from Rising Edge of ct>
tC(CK)
Clock Period
Clock and Trigger Rise and Fall Times
tr, tf
tS(CK)
Clock Setup Time to Rising Edge of ct>
for Immediate Count
Trigger Setup Time to Rising Edge of ct>
tS(TR)
for enabling of Prescaler on Fo"owing
Rising Edge of
H)
tW(ct>L)
tr, tf
tH
tSct>(CS)
Min
Max
Unit Comments
250
105
105
(1)
2000
2000
30
ns
ns
ns
ns
ns
ns
380
ns
0
145
(2)
ns
50
160
ns
110
ns
(2)
ns
140
160
130
190
ns
ns
ns
115
ns
90
ns
115
ns
(3)
(3)
(3)
Counter Mode
2tC(ct» + 140
tc(ct» + 140
ns
Timer Mode
Counter Mode
130
ns
Counter Mode
130
ns
Timer Mode
Counter and
Timer Modes
Counter and
Timer Modes
Counter and
Timer Modes
Counter and
Timer Modes
2tC(, ZC/TO High
ZC/TO Delay Time from Falling Edge
of ct>, ZC/TO Low
NOTES:
tc = tw(. Control Or Data Select (input, High selects Control). This input defines the type of information
transfer performed between the CPU and the ZOO-SIO. A High at this input, during a CPU write to the
ZOO-SIO, causes the information on the data bus to be interpreted as a command for the channel
selected by B/A. A Low at C/O means that the information on the data bus is data. Address bit A1 is
often used for this function.
CEo Chip Enable (input, active Low). A Low level at this input enables the zao-slo to accept command
or data inputs from the CPU during a write cycle, or to transmit data to the CPU during a read cycle.
<1>. System Clock(input). The zao-slo uses the standard ZaOA System Clock to synchronize internal
Signals. This is a single-phase clock.
M1. Machine Cycle One (input from zao-cpu, active Low).When M1 is active and RD is also active,
the zeo-cpu is fetching an instruction from memory. When M1 is active, while 10RO is active, the
ZOO-SID accepts iiii1 and 10RO as an interrupt acknowledge if the zeO-SIO is the highest priority device
that has interrupted the ZOO-CPU.
lORa. Input/Output Request (input from CPU, active Low). 10RO is used in conjunction with BIA,
c/5, CE and RD to transfer commands and data between the CPU and the zeO-SIO. When CE, RD and
lORa are all active, the channel selected by BIA transfers data to the CPU (a read operation). When CE
and 10RO are active, but RD is inactive, the channel selected by BlAis written to by the CPU with either
data or control information, as specified by C/O. As mentioned previously, if 10RO and M1 are active
simultaneously, the CPU is acknowledging an interrupt and the Zao-SIO automatically places its
interrupt vector on the CPU data bus, if it is the highest priority device requesting an interrupt.
RD. Read Cycle Status. (input from CPU, active Low). If RD is active, a memory or 1/0 read operation is
in progress. RD is used with BIA. CE and 10RO to transfer data from the ZOO-SID to the CPU.
REm.
Reset (input, active Low). A Low RESET disables both receivers and transmitters, forces TxDA
and TxDB marking, forces the modem controls High and disables all interrupts. The control registers
must be rewritten after the ZOO-SID is reset and before data is transmitted or received.
lEI. Interrupt Enable In (input, active High). This signal is used with lEO to form a priority daisy chain
when there is more than one interrupt-driven device. A High on this line indicates that no other device
of higher priority is being serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active High). lEO is High only if lEI is High and the CPU is not
servicing an interrupt from this zeO-SIO. Thus, this signal blocks lower priority devices from
interrupting while a higher priority device is being serviced by its CPU interrupt service routine.
INT. Interrupt Request (output, open drain, active Low). When the ZOO-SID is requesting an interrupt,
it pulls INT Low.
W/RDYA, W/RDYB. Wait/Ready A, Wait/Ready B (outputs, open drain when programmed for
Wait function, driven High and Low when programmed for Ready function). These dual-purpose
outputs may be programmed as Ready lines for a DMA controller or as Wait lines that synchronize the
CPU to the ZOO-SIO data rate. The reset state is open drain.
CTSA, CTSB. Clear To Send (inputs, active Low). When programmed as Auto Enables, a Low on
these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may
be programmed as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate
slow-risetime inputs. The Zao-SIO detects pulses on these inputs and interrupts the CPU on both logic
level transitions. The Schmitt-trigger inputs do not guarantee a specified noise-level margin.
DCDA, DCDB. Data Carrier Detect (inputs, active Low). These signals are similar to the CTS inputs,
except they can be used as receiver enables.
RxDA, RxDB. Receive Data (inputs, active High).
TxDA, TxDB. Transmit Data (outputs, active High).
111-170
RxCA. RxCB*. Receiver Clocks (inputs). See the following section on bonding options. The Receive
Clocks may be 1, 16. 32 or 64 times the data rate in asynchronous modes. Receive data is sampled on
the rising edge of RxC.
TxCA. TxCB*. Transmitter Clocks (inputs). See section on bonding options. In asynchronous modes.
the Transmitter clocks may be 1, 16,32 or 64 times the data rate. The multiplierforthe transmitter and
the receiver must be the same. Both the TxC and RxC inputs are Schmitt-trigger buffered for relaxed
rise-and fall-time requirements (no noise margin is specified). TxD changes on the falling edge of TxC.
RTSA. RTSB. Request To Send (outputs, active Low). When the RTS bit is set, the RTS output goes
low. When the RTS bit is reset in the Asynchronous mode, the output goes High after the transmitter is
empty. In Synchronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can be
used as general purpose outputs.
DTRA. D'fRB. Data Terminal Ready (outputs, active Low). See note on bonding options. These
outputs follow the state programmed into the DTR bit. They can also be programmed as generalpurpose outputs.
SYNC A. SYNC B. Synchronization (inputs/outputs, active Low). These pins can act either as inputs
or outputs. In the Asynchronous Receive mode, they are inputs similar to CTS and DCD. In this mode,
the transitions on these lines affect the state ofthe Sync/Hunt status bits in RRO.ln the External Sync
mode, these lines also act as inputs. When external synchronization is achieved, SYNC must be driven
Low on the second rising edge of RxC after that rising edge of RxC, on which the last bit of the sync
character was received. In other words, after the sync pattern is detected. the external logic must wait
for two full Receive Clock cycles to activate the SYNC input. Once SYNC is forced Low, it is wise to keep
it Low until the CPU informs the external sync logic that synchronization has been lost or a new
message is about to start. Character assembly begins on the rising edge of RxC that immediately
precedes the falling edge of SYNC in the External Sync mode.
In the Internal Synchonrization mode (Monosync and Bisync), these pins act as outputs that are active
during the part of the receive clock (Axe) cycle in which sync characters are recognized. The sync
condition is not latched. so these outputs are active each time a sync pattern is recognized, regardless
of character boundaries.
1.5
BONDING OPTIONS
The constraints of a 4O-pin package make it impossible to bring outthe Receive Clock, Transmit Clock,
Data Terminal Ready and Sync signals for both channels. Therefore, Channel B must sacrifice a signal
or have two signals bonded together. Since user requirements vary, three bondings options are offered:
MK38B4 ZSO-SIO has all four signals, but TxCB and RxCB are bonded together (Fig. 1.1).
MK3885 ZBO-SIO sacrifices DTRB and keeps TxCB, RxCB and SYNCB (Fig. 1.2).
MK3887 ZSO-SIO sacrifices SYNCB and keeps TxCB, RxCB and DTRB (Fig. 1.3).
*These clocks may be directly driven by the ZBO-CTC (Counter Timer Circuit) for fully programmable
baud rate generation.
111-171
MK3887 PIN CONFIGURATION
Figure 1.3
Do~
01
Il2
40
1
39
RxDA
RxCA
TxDA
CPU
DATA
BUS
06
D7~
SIO
CONTROL
FROM
CPU
[
RESET
M1
a
10RQ
RD
&V
37
4
35
21
RTSA
CTSA
DTRA
]MOD~
CONTROL
DCDA
RilDS
8
36
32
9
RxCB
TxDB
TxCB
GND
W/RDYB
4>
DAISY
[
CHAIN
INTERRUPT
CONTROL
CH-A
"'W7FiDYA
0&
RTSB
INT
lEI --.{.
DTRB
lEO +-L
DCDB
CTSB
C/o
B/A
111-172
CH-B
]MDD~
CONTROL
2.0
ARCHITECTURE
2.1
INTRODUCTION
The device internal structure includes a ZSO-CPU interface, internal control and interrupt logic and two
full-duplex channels. Associated with each channel are read and write registers and discrete control
and status logic that provide the interface to modems or other external devices.
The read and write register group includes five 8-bit control registers, two sync-character registers and
two status registers. The interrupt vector is written into an additional8-bit register (Write Register 2) in
Channel B that may be read through Read Register 2 in Channel B. The registers for both channels are
designated in the text as follows:
WRO-WR7 -- Write Registers 0 through 7
RRO-RR2 -- Read Registers 0 through 2
The bit assignment and functional grouping of each register is configured to simplify and organize the
programming process. Table 2.1 illustrates the functions assigned to each read or write register.
FUNCTIONAL ASSIGNMENTS OF READ AND WRITE REGISTERS
Table 2.1
WRO
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Register pointers, CRC initialize, initialization commands for the various modes, etc.
Transmit/Receive interrupt and data transfer mode definition
Interrupt vector (Channel B only)
Receive parameters and controls
Transmit/Receive miscellaneous parameters and modes
Transmit parameters and controls
Sync character of SDLC address field
Sync character of SDLC flag
(a) Write Register Functions
Transmit/Receive buffer status, interrupt status and external status
Special Receive Condition status
Modified interrupt vector (Channel B only)
(b) Read Register Functions
RRO
RR1
RR2
The logic for both channels provides formats, synchronization and validation for data transferred to and
from the channel interface. The modem control inputs, Clear to Send (CTS) and Data Carrier Detect
(DCD), are monitored by the discrete control logic under program control. All the modem control signals
are general purpose in nature and can be used for functions other than modem control.
For automatic interrupt vectoring, the interrupt control logic determines which channel and which
device within the channel has the highest priority. Priority is fixed with Channel A assigned a higher
priority than Channel B; Receive, Transmit and External/Status interrupts are prioritized in that order
within each channel.
2.2
DATA PATH
The transmit and receive data paths for each channel are shown in Figure 2.1. The receiver has three
8-bit buffer registers in a FIFO arrangement (to provide a 3-byte delay) in addition to the 8-bit receive
shift register. This arrangement creates additional time for the CPU to service an interrupt at the
beginning of a block of high-speed data. The receive error FIFO stores parity and framing errors and
other types of status information for each of the three bytes in the receive data FIFO.
Incoming data is routed through one of several paths depending on the mode and character length. In
the Asynchronous mode, serial data is entered into the 3-bit buffer if it has a character length of seven
or eight bits, or is entered into the 8-bit receive shift register if it has a length of five or six bits.
In the Synchronous mode, however, the data path is determined by the phase of the receive process
currently in operation. A Synchronous Receive operation begins with the receiver in the Hunt phase,
during which the receiver searches the incoming data stream for a bit pattern that matches the
111-173
TRANSMIT AND RECEIVE DATA PATH
Figure 2.1
RlCOA
preprogrammed sync characters (or flags in the SOLC mode). If the device is programmed for
Monosync Hunt, a match is made with a single sync character stored in WR7.ln Bisync Hunt, a match
is made with dual sync characters stored in WR6 and WR7.
In either case, the incoming data passes through the receive sync registers and is compared against the
programmed sync character in WR6 or WR7. In the Monosync mode, a match between the sync
character programmed into WR7 and the character assembled in the receive sync register establishes
synchronization.
In the Bisync mode, however, incoming data is shifted to the receive shift register while the next eight
bits of the message are assembled in the receive sync register. The match between the assembled
character in the receive sync registers with the programmed sync character in WR6 and WR7
establishes synchronization. Once synchronization is established, incoming data bypasses the receive
sync register and directly enters the 3-bit buffer.
In the SOLe mode, incoming data first passes through the receive sync register, which continuously
monitors the receive data stream and performs zero deletion when indicated. Upon receiving five
contiguous I's, the sixth bit is inspected. If the sixth bit is a 0, it is deleted from the data stream. If the
sixth bit is a 1, the seventh bit is inspected. If that bit is a 0, a Flag sequence has been received; if it is a 1,
an Abort sequence has been received.
The reformatted data enters the 3-bit buffer and is transferred to the receive shift register. Note that the
SOLC receive operation also begins in the Hunt phase, during which the ZSO-SIO tries to match the
assembled character in the receive shift register with the flag pattern in WR7. Once the first flag
character is recognized, all subsequent data is routed through the same path, regardless of character
length.
111-174
Although the same CRC checker is used for both SOLC and synchronous data, the data path taken for
each mode is different. In Bisync protocol, a byte-oriented operation requires that the CPU decide to
include the data character in CRC. To allow the CPU ample time to make this decision, the ZBO-SIO
provides an 8-bit delay for sychronous data. In the SOLC mode, no delay is provided since the ZSO-SIO
contains logic that determines the bytes on which CRC is calculated.
The transmitter has an 8-bit transmit data register that is loaded from the internal data bus and a 20-bit
transmit shift register that can be loaded from WRS, WR7 and the transmit data register. WRS and
WA7 contain sync characters in the Monosync or Bisync modes or address field (one character long)
and flag, respectively, in the SOLC mode. During Synchronous modes, information contained in WAS
and WR7 is loaded into the transmit shift register atthe beginning of the message and, as a time filler,
in the middle of the message if a Transmit Underrun condition occurs. In the SOLC mode, the flags are
loaded into the transmit shift register at the beginning and end of message.
Asynchronous data in the transmit shift register is formatted with start and stop bits and is shifted out to
the transmit multiplexer at the selected clock rate.
Synchronous (Monosync or Bisync) data is shifted out to the transmit multiplexer and also to the CRe
generator at the x 1 clock rate.
SOLC/HOLC data is shifted out through the zero insertion logic, which is disabled while the flags are
being sent. For all other fields (address, control and frame check) a 0 is inserted following five
contiguous 1's in the data stream. The CRC generator result for SOLC data is also routed through the
zero insertion logic.
2.3
FUNCTIONAL DESCRIPTION
The functional capabilities of the zeD-SIC can be described from two different points of view: as a data
communications device, it transmits and receives serial data, and meets the requirements of various
data communications protocols; as a ZBO family peripheral, it interacts with the ZSO-CPU and other ZSO
peripheral circuits, and shares their data, address and control busses, as well as being a part of theZSO
interrupt structure. As a peripheral to other microprocessors, the ZSO-SIO offers valuable features such
as non-vectored interrupts, polling, and simple handshake capabilities.
The first part of the following functional description describes the interaction between the CPU and
ZSO-SIO; the second part introduces its data communications capabilities.
2.3.1
I/O CAPABILITIES
The ZBO-SIO offers the choice of Polling, Interrupt (vectored or non-vectored) and Block
Transfer modes to transfer data,status,and control information to and from the CPU. The Block
Transfer mode can be implemented under CPU or OMA control.
Polling. The Polled mode avoids interrupts. Status registers RRO and RR1 are updated at
appropriate times for each function being performed (for example, CRC Error status valid at the
end of the message). All the interrupt modes of the zeD-SIC must be disabled to operate the
device in a polled environment.
While in its Polling sequence, the CPU examines the status contained in RRO for each
channel; the RRO status bits serve as an acknowledge to the Poll inquiry. The two RRO status
bits DO and 02 indicate that a receive or transmit data transfer is needed. The status also
indicates Error or other special status conditions (see "ZSO-SIO Programming"). The Special
Receive Condition status continued in RR1 does not have to be read in a Polling sequence
because the status bits in RR1 are accompanied by a Receive Character Available status in
RRO.
Interrupts. The ZBO-SIO offers an elaborate interrupt scheme to provide fast interrupt
response in real-time applications. As mentioned earlier, Channel B registers WR2 and RR2
contain the interrupt vector that points to an interrupt service routine in the memory. To
service operations in both channels and to eliminate the necessity of writing a status analysis
111-175
routine, the ZSO-SIO can modify the interrupt vector in RR2 so it points directly to one of eight
interrupt service routines. This is dOr;1e under program control by setting a program bit (WR1,
02) in Channel B called "Status Affects Vector," When this bit is set, the interrupt vector in
WR2 is modified according to the assigned priority of the various interrupting conditions. The
table in the Write Register 1 description (ZSO-SIO Programming section) shows the
modification details.
Transmit interrupts, Receive interrupts and External/Status interrupts are the main sources
of interrupts(Figure 5). Each interrupt source is enabled under program control with Channel
A having a higher priority than Channel B, and with Receiver, Transmit and External/Status
interrupts prioritized in that order within each channel. When the Transmit interrupt is
enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the
transmitter must have had a data character written into it so it can become empty.) When
enabled, the receiver can interrupt the CPU in one of three ways:
Interrupt on first receive character
Interrupt on all receive characters
Interrupt on a Special Receive condition
Interrupt On FirSt Character is typically used with the Block Transfer mode.
Interrupt On All Receive Characters has the option of modifying the interrupt vector in the
event of a parity error. The Special Receive Condition interrupt can occur on a character or
message basis (End Of Frame interrupt in SOLC, for example). The Special Receive
condition can cause an interrupt only if the Interrupt On First Receive Character or Interrupt
On All Receive Characters mode is selected. In Interrupt On First Receive Character, an
interrupt can occur from Special Receive conditions (except parity Error) after the first
receive character interrupt (example: Receive Overrun interrupt).
The main function of the External/Status interrupt is to monitor the signal transitions of the
CTS, OCO and SYNC pins; however, an External/Status interrupt is also caused by a Transmit
Underrun condition or by the detection of a Break (AsynChronous mode) or Abort (SOLC mode)
sequence in the data stream. The interrupt caused by the Break!Abort sequence has a special
feature that allows the ZSO-SIO to interrupt when the Break!Abort sequence is detected or
terminated. The feature facilitates the proper termination of the current message, correct
initialization of the next message, and the accurate timing of the Break!Abort conditon in
external logic.
INTERRUPT STRUCTURE
Figure 2.2
RECEIVE CHARACTER
PARIlY ERROR
RECEIVE OVERRUN ERROR
FRAMING ERROR
END OF FRAME (SDLC)
SPECIAL RECEIVE
I---------I~.. CONDITION INTERRUPT
FIRST DATA CHARACTER
FIRST NON-SYNC CHARACTER (SYNC)
VAUD ADDRESS BYTE (SDLC)
~
- - - - I..~
INTERRUPT ON ALL
RECEIVE CHARACTERS
~ INTERRUPT ON
RECEIVE
INTERRUPT
FIRST CHARACTER
DCD TRANSITION
CTS TRANSITION
SYNC TRANSITION
Tx UNDERRUN/EOM
BREAK/ABORT DETECTION
EXTERNAL STATUS
INTERRUPT
TRANSMIT INTERRUPT
BUFFER BECOMMING EMPTY
111-176
~
f-
Z80-SIO
INTERRUPT
CPUIDMA Block Transfer. TheZaO-SIO provides a BlockTransfer mode to accommodate
block transfer functions and DMA controllers (ZaO-DMA or other designs). The Block
Transfer mode uses the WAITIREADY output in conjunction with the Wait/Ready bits of
Write Register 1. The WAITIREADY output can be defined under software control as a
WAIT line in the CPU Block Transfer mode or as a READY line in the DMA Block Transfer
mode.
To a DMA controller, the ZSO-SIO READY output indicates that the ZBO-SIO is ready to
transfer data to or from memory. To the CPU, the WAlT output indicates that the ZBO-SIO is
not ready to transfer data, thereby requesting the CPU to extend the 1/0 cycle. The
programming of bits 5, 6 and 7 of Write Register 1 and the logic states of the WAITIREADY
line are defined in the Write Register 1 description (ZSO-SIO Programming section.)
2.3.2
DATA COMMUNICATIONS CAPABILITIES
In addition to the 1/0 capabilities previously discussed, the zao-slo provides two independent
full-duplex channels as well as Asynchronous, Synchronous and SDLC (HDLC) operational
modes. These modes facilitate the implementation of commonly used data communications
protocols.
The specific features of these modes are described in the following sections. To preserve the
independence and completeness of each section, some information common to all modes is
repeated.
111-177
111-178
3.0
ASYNCHRONOUS OPERATION
3.1
INTRODUCTION
To receive or transmit data in the Asynchronous mode, the ZSO-SID must be initialized with the
following parameters: character length, clock rate, number of stop bits, even or odd parity, interrupt
mode, and receiver or transmitter enable. The parameters are loaded into the appropriate write
registers by the system program. WR4 parameters must be issued before WR1, WR3, and WR5
parameters or commands.
If the data is transmitted over a modem or RS232C interface, the REQUESTTD SEND (RTS) and DATA
TERMINAL READY (DTR) outputs must be set along with the Transmit Enable bit. Transmission cannot
begin until the Transmit Enable bit is set.
The Auto Enables feature allows the programmer to send the first data character of the message to the
ZSO-SID without waiting for CTS. If the Auto Enables bit is set, the ZSO-SID will wait for the CTS pin to
go Low before it begins data transmission. CTS,DCD.and SYNC are general-purpose liD lines that may
be used for functions other than their labeled purposes. If CTS is used for another purpose, the Auto
Enables Bit must be programmed to O.
Figure 3.1 illustrates asynchronous message formats. Table 3. 1 shows WR3,WR4,andWR5 with bits
set to indicate the applicable modes, parameters, and commands in asynchronous modes. WR2
(Channel B only) stores the interrupt vector and WR1 defines the interrupt modes and data transfer
modes. WR6 and WR7 are not used in asynchronous modes. Table 3.2 shows the typical program
steps that implement a full-duplex receiveltransmit operation in either channel.
3.2
ASYNCHRONOUS TRANSMIT
The Transmit Data output (TxD) is held marking (High) when the transmitter has no data to send. Under
program control, the Send Break (WA5, 04) command can be issued to hold TxD spacing (Low) until the
command is cleared.
The Z80-SID automatically adds the start bit, the programmed parity bit (odd, even or no parity) and the
programmed number of stop bits to the data character to be transmitted. When the character length is
six or seven bits, the unused bits are automatically ignored by the ZSO-SID. If the character length is five
bits or less, refer to the table in the Write Register 5 description (ZSO-SID Programming section)forthe
data format.
Serial data is shifted from TxD at a rate equal to 1, 111 6th, 1132nd, or 1/64th of the clock rate
supplied to the Transmit Clock input (TxC). Serial data is shifted out on the falling edge of (TxC).
If set. the External/Status Interrupt mode monitors the status of DCD, CTS and SYNC throughout the
transmission of the message. If these inputs change for a period of time greater than the minimum
specified pulse width, the interrupt is generated. In a transmit operation, this feature is used to monitor
.
the modem control Signal C'i'S.
ASYNCHRONOUS MESSAGE FORMAT
Figure 3.1
ASYNCHRONOUS FORMAT
MARKINGUNE
~~:~[ [~PARITYI
- Y
ALL TRANSACTIONS OCCUR
ON A FALLING EDGE
OF TxC.
--&-DN
N - 6. 6. 7. OR 8
MESSAGE FLOW
111-179
MARKINGUNE
I \
MAY 8E PRESENT OR
NOT. EVEN OR ODD
..
STOP
1.W, OR 2 BITS
3.3
ASYNCHRONOUS RECEIVE
Asynchronous Receive operation begins when the Receive Enable bit is set. If the Auto Enables option
is selected, oeD must be Low as well. A Low (spacing) condition on the Receive Data input (RxD)
indicates a start bit. If this
persists for at least one-half of a bit time, the start bit is assumed to be
valid and the data input is then sampled at mid-bit time until the entire character is assembled. This
method of detecting a start bit improves error rejection when noise spikes exist on an otherwise
marking line.
Leiw
If the x1 clock mode is selected, bit synchronization must be accomplished externally. Receive data is
sampled on the rising edge of RxC. The receiver inserts 1's when a character length of other than eight
bits is used. If parity is enabled, the parity bit is not stripped from the assembled character for character
lengths other than eight bits. For lengths other than eight bits, the receiver assembles a character
length of the required number of data bits, plus a parity bit and 1's for any unused bits. For example, the
receiver assembles a 5-bit character with the following format: 11 P 04 03 02 01 00.
Since the receiver is buffered by three 8-bit registers in addition to the receive shift register, the CPU
has enough time to service an interrupt and to accept the data character assembled by the Z80-SIO.
The receiver also has three buffers that store error flags for each data character in the receive buffer.
These error flags are loaded at the same time as the data characters.
After a character is received, it is checked for the following error conditions:
When parity is enabled, the Parity Error bit (RR1 , 04) is set whenever the parity bit of the character does
not match with the programmed parity. Once this bit is set, it remains set until the Error Reset
Command (WRO) is given.
CONTENTS OF WRITE REGISTERS 3, 4 and 5 in ASYNCHRONOUS MODES
Table 3.1
BIT 7
WR3
WR4
BIT 6
00 = Rx 5 B rrS/CHAR
10 = Rx 6 BITS/CHAR
01 = Rx 7 BITS/CHAR
11 = Rx 8 BITS/CHAR
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AUTO
ENABLES
0
0
0
0
Ax
ENABLE
00 = x1 CL6cK MODE
01 = X16 CLOCK MODE
10 = x32 CLOCK MODE 0
0
I
11 = x64 CLOCK MODE
WR5
DTR
00 = Tx 5 BITS (OR
LESS) CHAR
10 = Tx 6 BITS/CHAR
01 = Tx 7 BITS/CHAR
11 = Tx 8 BITS/CHAR
I
SEND
BREAK
00= NOT USED
01 = 1 STOP BIT/CHAR EVEN-ODD PARITY
PARITY
10 = 1% STOP
ENABLE
BITS/CHAR
11 = 2 STOP
BITS/CHAR
Tx
ENABLE
0
RTS
0
The Framing Error bit (RR1 , 06) is set ifthe character is assembled without any stop bits (that
is a Low level detected for a stop bit). Unlike the Parity Error bit, this bit is set (and not latched)
only for the character on which it occurred. Detection of framing error adds an additional
one-half of a bit time to the character time so the framing error is not interpreted as a new
start bit.
111-180
ASYNCHRONOUS MODE
Table 3.2
TYPICAL PROGRAM STEPS
FUNCTION
COMMENTS
REGISTER: INFORMATION LOADED:
WRO
WRO
WR2
WRO
WR4
INITIALIZE
WRO
WR3
WRO
WR5
CHANNEL RESET
POINTER 2
INTERRUPT VECTOR
POINTER 4, RESET EXTERNAUSTATUS
INTERRUPT
ASYNCHRONOUS MODE, PARITY
INFORMATION, STOP BITS INFORMATION, CLOCK RATE INFORMATION
POINTER 3
RECEIVE ENABLE, AUTO ENABLES,
RECEIVE CHARACTER LENGTH
POINTER 5
REQUEST TO SEND, TRANSMIT
ENABLE, TRANSMIT CHARACTER
LENGTH, DATA TERMINAL READY
WRO
POINTER 1, RESET EXTERNAUSTATUS
INTERRUPT
WR1
TRANSMIT INTERRUPT ENABLE,
STATUS AFFECTS VECTOR, INTERRUPT
ON ALL RECEIVE CHARACTERS,
DISABLE WAITIREADY FUNCTION,
EXTERNAL INTERRUPT ENABLE
Issue Parameters
Receive and Transmit both fully initialized.
Auto Enables will enable Tran!!mitter if
CTS is active and Receiver if DCD is
active.
Transmit/Receive interrupt mode
selected. External. Interrupt monitors the
status CTS. Deb and SYN"C inputs and
detects the Break sequence. Status
Affects Vector in Channel B only.
EXECUTE HALT INSTRUCTION
OR SOME OTHER PROGRAM
Program is waiting for an interrupt from
theSIO.
zao INTERRUPT ACKNOWLEDGE CYCLE
When the interrupt occurs, the interrupt
vector is modified by: 1. Receive
Character Available; 2. Transmit Buffer
Empty; 3. External/Status change; and 4.
Special Receive condition.
TRANSFERS RR2 TO CPU
IF A CHARACTER IS RECEIVED:
TRANSFER DATA CHARACTER TO CPU
UPDATE POINTERS AND
PARAMETERS RETURN FROM
INTERRUPT
DATA TRANSFER AND
ERROR MONITORING
Channel B only
This data byte must be transferred or no
transmit interrupts will occur.
TRANSFER FIRST DATA BYTE TO SIO
IDLE MODE
Reset SIO
IF TRANSMITTER BUFFER IS EMPTY:
TRANSFER DATA CHARACTER TO SIO
UPDATE POINTERS AND
PARAMETERS RETURN FROM
INTERRUPT
IF EXTERNAL STATUS CHANGES:
TRANSFER RRO TO CPU
PERFORM ERROR ROUTINES
(INCLUDE BREAK DETECTION)
RETURN FROM INTERRUPT
111-181
Program control is transferred to one of
the eight interrupt service routines.
If used with processors other than the
zao, the modified interrupt vector (RR2)
should be returned to the CPU in the
Interrupt Acknowledge sequence.
ASYNCHRONOUS MODE
Table 3.2
FUNCTION
TYPICAL PROGRAM STEPS
COMMENTS
REGISTER: INFORMATION LOADED:
IF SPECIAL RECEIVE CONDITION
OCCURS:
TRANSFER RR1 to CPU
00 SPECIAL ERROR (E.G. FRAMING
ERROR)
RETURN FROM INTERRUPT
REDEFINE RECEIVEITRANSMIT
INTERRUPT MODES
TERMINATION
When transmit or receive data transfer
is complete.
DISABLE TRANSMIT/RECEIVE MODES
UPDATE MODEM CONTROL OUTPUTS
(E.G. RTS OFF)
In transmit the All Sent Status bit
indicates transmission is complete.
If the CPU fails to read a data character while more than three characters have been received, the
Receive Overrun bit(RR1, D5) is set. When this occurs, the fourth character assembled replaces the
third character in the receive buffers. With this arrangement, only the character that has been
written over is flagged with the Receive Overrun Error bit. Like Parity Error, this bit can only be reset
by the Error Reset command from the CPU. Both the Framing Error and Receive Overrun Error cause
an interrupt with the interrupt vector indicating a Special Receive condition (if Status Affects Vector
is selected).
Since the Parity Error and Receive Overrun Errorflags are latched, the error status that is read reflects
an error in the current word in the receive buffer plus any Parity or Overrun Errors received since the
last Error Reset command. To keep correspondence between the state of the error buffers and the
contents of the receive data buffers, the error status register must be read before the data. This is easily
accomplished if vectored interrupts are used, because a special interrupt vector is generated for these
conditions.
While the External/Status interrupt is enabled, break detection causes an interrupt and the Break
Detected status bit fARO, D7), is set. The Break Detected interrupt should be handled by issuing the
Reset External/Status Interrupt command to the ZBO-SIO in response to the first Break Detected
interrupt that has a Break satus of 1 (RRO, D7). The ZSO-SIO monitors the Receive Data input and waits
for the Break sequence to terminate, at which point the Z80-SIO interrupts the CPU with the Break
status set to O. The CPU must again issue the Reset External/Status Interrupt command in its interrupt
service routine to reinitialize the break detection logic.
The External/Status interrupt also monitors the status of DCD. If the DCD pin becomes inactive for a
period greater than the minimum specified pulse width, an interrupt is generated with the DCD status
bit (RRO, D3) set to 1. Note that the DCD input is inverted in the RRO status register.
If the status is read after the data, the error data for the next word is also included if it has been stacked
in the buffer. If operations are performed rapidly enough so the next character is not yet received, the
status register remains valid. An exception occurs when the Interrupt On First Character Only mode is
selected. A special interrupt in this Mode holds the error data and the character itself (even if read from
the buffer) until the Error Reset command is issued. This prevents further data from becoming available
in the receiver until the Reset command is issued, and allows CPU intervention on the character with
the error even if DMA or block transfer techniques are being used.
111-182
If Interrupt On Every Character is selected, the interrupt vector is different ifthere is an error status in
RR1. If a Receiver Overrun occurs, the most recent character received is loaded into the buffer; the
character preceding it is lost. When the character that has been written over is read, the Receive
Overrun bit is set and the Special Receive Condition vector is returned if Status Affects Vector is
enabled.
In a polled environment, the Receive Character Available bit (RRO, DO) must be monitored so the
Zao-CPU can know when to read a character. This bit is automatically reset when the receive buffers
are read. To prevent overwriting data in polled operations, the transmit buffer status must be checked
before writing into the transmitter. The Transmit Buffer Empty bit is set to 1 whenever the transmit
buffer becomes empty.
111-183
111-184
4.0
SYNCHRONOUS OPERATION
4.1
INTRODUCTION
Before describing synchronous transmission and reception, the three types of character
synchronization-Monosync, Bisync, and External Sync-require some explanation. These modes use
the xl clock for both Transmit and Receive operations. Data is sampled on the rising edge of the
Receive Clock input (RxC). Transmitter data transitions occur on the falling edge of the Transmit Clock
input (TxC).
The differences between Monosync, Bisync, and External Sync are in the manner in which initial
character synchronization is achieved. The mode of operation must be selected before sync characters
are loaded because the registers are used differently in the various modes. Figure 4.1 shows the
formats for all three of these synchronous modes.
Monosync. In a Receive operation, matching a single sync character (8-bit sync mode) with the
programmed sync character stored in WR7 implies character synchronization and enables data
transfer.
Bisync. Matching two contiguous sync characters (16-bit sync mode) with the programmed sync
characters stored in WR6 and WR7 implies character synchronization. In both the Monosync and
Bisync modes, SYNC is used are the
command structure addressing controls, and are normally controlled by the CPU address bus.
Figures 8.' - 8.4 illustrate the timing relationships for programming the write registers, and
transferring data and status.
c/o
o
BIA
,
o
,,
o
,
o
Function
Channel A Oata
Channel B Oata
Channel A Commands/Status
Channel B Commands/Status
WRITE REGISTERS
The zao-slo contains eight registers (WRO-WR7) in each channel that are programmed separately by
the system program to configure the functional personality of the channels. With the exception ofWRO,
programming the write registers requires two bytes. The first byte contains three bits (00-02) that point
to the selected register; the second byte is the actual control word that is written into the register to
configure the Z80-SIO.
Note that the programmer has complete freedom, after pointing to the selected register, of either
reading to test the read register or writing to initialize the write register. By designing software to
initialize the ZBO-SIO in a modular and structured fashion, the programmer can use powerful block I/O
instructions.
WRO is a special case in that all the basic commands (CMOO-CM02) can be accessed with a single
byte. Reset (internal or external) initializes the pointer bits (00-02) to point to WRO.
The basic commands (CMOO-CM02) and the CRC controls (CRCo eRC, ) are contained in the first byte
of any write register access. This maintains maximum flexibility and system control. Each channel
contains the following control registers. These registers are addressed as commands (not data).
6.2
WRITE REGISTER 0
WRO is the command register; however, it is also used for CRC reset codes and to point to the other
registers.
07
06
05
04
03
02
0,
00
CRC
Reset
Code
1
CRC
Reset
Code
0
CMO
2
CMO
CMO
0
PTR
2
PTR
1
0
1
PTR
Pointer Bits (00-02)' Bits 00-02 are pointer bits that determine which other write register the next
byte is to be written into or which read register the next byte is to be read from. The first byte written into
each channel after a reset (either by a Reset command or by the external reset input) goes into WRO.
Following a read or write to any register (except WRO), the pointer will point to WRO.
111-205
Command Bits (03-051. Three bits. 03-05. are encoded to 'Issue the seven basic ZSO-SIO
commands.
COMMAND
CM02
0
1
2
3
4
5
6
7
CM01
CMOQ
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
Null Command (no effectl
Send Abort (SOLC Mode)
Reset External/Status Interrupts
Channel Reset
Enable Interrupt on next Rx Character
Reset Transmitter Interrupt Pending
Error Reset (latches)
Return from Interrupt (Channel A)
1
1
1
1
Command 0 (Null). The Null command has no effect. Its normal use is to cause the ZBO-SIO to do
nothing while the pointers are set for the followifl9 byte.
Command 1 (Send Abort). This command is used only with the SOLC mode to generate a sequence
of eight to thirteen l·s.
Command 2 (Reset External/Status Interrupts). After an External/Status interrupt (a change on a
modem line or a break condition, for example), the status bits of RRO are latched. This command
re-enables them and allows interrupts to occur again. Latching the status bits captures short pulses
until the CPU has time to read the change.
Command 3 (Channel Reset). This command performs the same function as an External Reset, but
only on a single channel. Channel A Reset also resets the interrupt prioritization logic. All control
registers for the channel must be rewritten after a Channel Reset command.
WRITE REGISTER BIT FUNCTIONS
Figure 6.1
WRITE REGISTER 0
I
07
I
06
I
05
I
04
t J
03
02
0
0
0
0
o
o
1
o
1
o
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
J
01
I
Do
0
0
0
1
1
0
1
J
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
1
0
0
1
1
1
0
1
1
0
1
1
1
NULLCOOE
SEND ABORT (SOLC)
RESETEXT/STATUSINTERRU FrS
CHANNEL RESET
ENABLE INT ON NEXT Rx CHARACTER
RESET Tx INT PENDING
ERROR RESET
RETURN FROM INT (CH-A ON LV)
NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNOERRUN/EOM LATCH
111-206
0
1
2
3
4
5
6
7
WRITE REGISTER 1
Os
06
07
04
03
I
I
0
0
0
1
0
1
1
DO
01
02
EXT INT ENABLE
Tx INT ENABLE
STATUS AFFECTS
VECTOR (CH. B ONLy)
Rx INT DISABLE
Rx INT FIRST CHARACTER
INT ON ALL Rx CHARACTERS (PARITY AFFECTS
VECTOR)
INT ON ALL Rx CHARACTERS (PARITY DOES NOT
AFFECT VECTOR)
1
*
'----WAIT/READy ON R/T
L..------WAIT/READy FUNCTION
L..----------WAIT/READy ENABLE
'OR ON SPECIAL CONDITION
"-"'D.N''''EL B ONLY)
I
07
I
06
I
05
I
04
I
03
I
D2
I
I
01
I
I
DO
t
VO
V1
V2
V3
V4
V5
V6
INTERRUPT
VECTOR
V7
WRITE REGISTER 3
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I
DO
I
Rx ENABLE
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES
.
o
o
1
1
o
1
o
Rx 5
Rx 7
Rx 6
Rx 8
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
111-207
WRITE REGISTER 4
J
01
J
J
DO
I
lL..-__
PARITY ENABLE
' - - - - - - - - - PARITY EVEN ODD
o
o
o
o
1
1
o
1
o
1
1
o
o
o
1
o
1
1
1
1
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1 112 STOP BITS CHARACTER
2 STOP BITS/CHARACTER
1
1
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE
X1 CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
WRITE REGISTER 5
I
D7
I
D6
I
0
0
1
1
D5
1
D4
I
D3
I
D2
l
I
D1
I
1
DO
J
J
Tx CRC ENABLE
RTS
SDLC/CRC-16
Tx ENABLE
SEND BREAK
Tx 5 BITS (OR LESS)/CHARACTER
Tx 7 BITS/CHARACTER
Tx 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER
0
1
0
1
DTR
WRITE REGISTER 6
I
D7
I
D6
I
D5
I
D4
I
D3
I
D2
I
*ALSO SOLe ADDRESS FIELD
111-208
1
D1
I
I
DO
I
SYNC BIT 0
SYNC BIT 1
SYNC BIT 2
SYNC BIT 3
SYNC BIT4
SYNC BIT 5
SYNC BIT 6
SYNC BIT 7
*
WRITE REGISTER
I
D7
I
I
D6
7
D5
I
D4
I
D3
I
D2
I
I
Dl
I
I
DO
I
I
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
BIT a
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
*
*FOR SDLC, IT MUST BE PROGRAMMED TO "01111110" FOR FLAG RECOGNITION
After a Channel Reset, four extra system clock cycles should be allowed for zao-slo reset time
before any additional commands or controls are written into that channel. This can normally be the
time used by the CPU to fetch the next op code.
Command 4 (Enable Interrupt On Next Character). Ifthe Interrupt On First Receive Character mode
is selected, this command reactivates that mode after each complete message is received to prepare
the Z80-SIO for the next message.
Command 5 (Reset Transmitter Interrupt Pending). The transmitter interrupts when the transmit
buffer becomes empty if the Transmit Interrupt Enable mode is selected. In those cases where there
are no more characters to be sent (at the end of message, for example), issuing this command prevents
further transmitter interrupts until after the next character has been loaded into the transmit buffer or
until CRC has been completely sent.
Command 6 (Error Reset). This command resets the error latches. Parity and Overrun errors are
latched in RRl until they are reset with this command. With this scheme, parity errors occurring in
block transfers can be examined at the end of the block.
Command 7 (Retum From Interrupt). This command must be issued in Channel A and is interpreted
by the zao-slo in exactly the same way it would interpret a RETI command on the data bus. It resets
the interrupt-under-service latch of the highest-priority internal device under service and thus allows
lower priority devices to interrupt via the daisy chain. This command allows use of the internal daisy
chain even in systems with no external daisy chain or RETI command.
CRC Reset Codes 0 and 1 (06 and 07)' Together, these bits select one of the three following reset
commands:
CRC Reset
Code 1
CRC Reset
Code 0
o
1
o
1
1
o
o
1
Null Code (no effect)
Reset Receive CRC Checker
Reset Transmit CRC Generator
Reset Tx Underrun/End Of Message Latch
The Reset Transmit eRe Generator command normally initializes the CRC generator to all O·s. If the
SDLe mode is selected, this command initializes the CRC generator to alil's. The Receive CRC checker
is also initialized to all l's for the SDLC mode.
111-209
6.3
WRITE REGISTER 1
WR1 contains the control bits for the various interrupt and Wait/Ready modes.
07
Wait/Ready
Enable
_06
Wait Or Ready
Function
05
Wait/Ready
On Receive/Transmit
04
Receive
Interrupt Mode 1
03
Receive
Interrupt
Mode 0
02
Status
Affects
Vector
01
Transmit
Interrupt
Enable
DO
External
Interrupts
Enable
External/Status Interrupt Enable I~ The External/Status Interrupt Enable allows interrupts to
occur as a result oftransitions on the DCD, CTS or SYNC inputs, as a result of a Break!Abort detection
and termination, or at the beginning of CRC or sync character transmission when the Transmit
Underrun/EOM latch becomes set.
Transmitter Interrupt Enable 1°1)' If enabled, the interrupts occur whenever the transmitter buffer
becomes empty.
Status Affects Vector 102)' This bit is active in Channel B only. If this bit is not set, the fixed vector
programmed in WR2 is returned from an interrupt acknowledge sequence. If this bit is set, the vector
returned from an interrupt acknowledge is variable according to the following interrupt conditions:
V3
0
0
0
0
1
1
1
1
ChB
ChA
1
V2
V1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
B Transmit Buffer Empty
B External/Status Change
B Receive Character Available
B Special Receive Condition*
A Transmit Buffer Empty
A External/Status Change
A Receive Character Available
A Special Receive Condition*
*Special Receive Conditions: Parity Error, Rx Overrun Error, Framing Error, End Of Frame (SDLC).
Receive Interrupt Modes 0 and 1 103 and 041. Together, these two bits specify the various
character-available conditions. In Receive Interrupt modes 1, 2 and 3, a Special Receive Condition can
cause an interrupt and modify the interrupt vector.
04
03
Receive
Interrupt
Mode 1
Receive
Interrupt
Mode 0
0
0
1
1
0
1
0
1
O.
1.
2.
3.
Receive Interrupts Disabled
Receive Interrupt On First Character Only
Interrupt On All Receive Characters-parity error is a Special Receive condition
Interrupt On All Receive Characters-parity error is not a Special Receive condition
111-210
Wait/Ready Function Selection (05-07)' The Wait and Ready functions are selected by
controlling OS, Os and 07. Wait/Ready function is enabled by setting Wait/Ready Enable(WR1,
07)to 1. The Ready Function is selected by setting Os (WaitiReady function) to 1.lfthisbit is 1, the
WAIT/READY output switches from High to Lowwhen the Z80-S10 is ready to transfer data. The
Wait function is selected by setting Os to O. If this bit is 0, the WAIT/READY output is in the
open-drain state and goes Low when active.
Both the Wait and Ready functions can be used in either the Transmit or Receive modes, but not both
simultaneously. If Os (WaitiReady or ReceivelTransmit) is setto 1, the WaitiReadyfunction responds
to the condition of the receive buffer (empty or full). If Os is set to 0, the Wait/Ready function responds
to the condition of the transmit buffer (empty or full).
The logic states of the WAIT/READY output when active or inactive depend on the combination of
modes selected. Following is a summary of these combinations:
AndOS=l
AndOS=O
ROO'VisHigh
WAIT is floating
AndOS=O
READY
WAIT
READY
WAIT
And Os
-
Is High when transmit buffer is full.
READY
Is Low when transmit buffer is full and
WAiT
an 510 data port is selected.
Is Low when transmit buffer is empty.
Is floating when transmit buffer is empty. WAIT
READY
=1
Is High when receive buffer is empty.
Is Low when receive buffer is empty and
an 510 data port is selected.
Is Low when receive buffer is full.
Is Floating when receive buffer is full.
The WAIT output High-to-Lowtransition occurs when the deiaytime tOIC(WR) after the I/O request.
The Low-to-High transition occurs with the delay tOH(WR) from the falling edge of cI>. The READY
output High-to-Low transition occurs with the delay tOL(WR) from the rising edge of cI>. The
READY output Low-to-High transition occurs with the delay tOIC(WR) after lORa falls.
The Ready function can occur any time the Z80-S10 is not selected. When the READY output becomes
active (Low), the OMA controller issues lORa and the corresponding B/A and C/O inputs to the
Z80-S10 to transfer data. The READY output becomes inactive as soon as lORa and CS become active.
Since the Ready function can occur internally in the 280-510 whether it is addressed or not, the READY
output becomes inactive when any CPU data or command transfer takes place. This does not cause
problems because the OMA controller is not enabled when the CPU transfer takes place.
The Wait function-on the other hand-is active only if the CPU attempts to read 280-510 data that has
not yet been received, which occurs frequently when block transfer instructions are used. The Wait
function can also become active (under program control) if the CPU tries to write data while the
transmit buffer is still full. The fact thatthe WAIT output for either channel can become active when the
opposite channel is addressed (because the 280-510 is addressed) does not affect operation of
software loops or block move instructions.
6.4
WRITE REGISTER 2
WR2 is the interrupt vector register; it exists in Channel B only. V4-V7 and Vo are always returned
exactly as written; V 1-V3 are returned as written ifthe Status Affects Vector(WR1, 02) control bit is O.lf
this bit is 1, they are modified as explained in the previous section.
111-211
6.5
WRITE REGISTER 3
WR3 contains receiver logic control bits and parameters.
07
Receiver
Bits/
Char 1
06
Receiver
Bits/
Char 0
Os
Auto
Enables
04
Enter
Hunt
Phase
03
Receiver
CRC
Enable
02
Address
Search
Mode
01
Sync Char
Load
Inhibit
DO
Receiver
Enable
Receiver Enable (DOl. A 1 programmed into this bit allows receive operations to begin. This bit should
be set only after all other receive parameters are set and receiver is completely initialized.
Sync Character Load Inhibit (01). Sync characters preceding the message (leading sync charactersl
are not loaded into the receive buffers if this option is selected. Because CRC calculations are not
stopped by sync character stripping, this feature should be enabled only at the beginning of the
message.
Address Search Mode (021. If SOLC is selected, setting this mode causes messages with addresses
not matching the programmed address in WR6 or the global (111111111 address to be rejected. In
other words, no receive interrupts can occur in the Address Search mode unless there is an address
match.
Receiver eRC Enable (031. If this bit is set, CRC calculation starts (or restarts) atthe beginning ofthe
last character transferred from the receive shift register to the buffer stack, regardless of the number of
characters in the stack. See "SOLC Receive CRC Checking" (SOLC Receive section) and "CRC Error
Checking" (Synchronous Receive section) for details regarding when this bit should be set.
Enter Hunt Phase (04). The zao-slo automatically enters the Hunt phase after a reset; however, it
can be re-entered if character synchronization is lost for any reason (Synchronous mode) or if the
contents of an incoming message are not needed (SOLC mode). The Hunt phase is re-entered by
writing a 1 into bit 04. This sets the Sync/Hunt bit (04) in RRO.
Auto Enables (05). If this mode is selected, OCO and CTS become the receiver and transmitter
enables, respectively. If this bit is not set, OCO and CTS are simply inputs to their corresponding status
bits in RRO.
Receiver Bits/Character 1 and 0 (07 and 061. Together, these bits determine the number of serial
receive bits assembled to form a character. Both bits may be changed during the time that a character is
being assembled, but they must be changed before the number of bits currently programmed is
reached.
o
o
1
1
Bits/Character
o
5
1
7
1
a
o
6
111-212
1.1
WRITE REGISTER 4
WR4 contains the control bits that affect both the receiver and transmitter. In the transmit and receive
initialization routine, these bits should be set before issuing WR 1, WR3, WR5. WRS, and WR7.
Os
Clock
Rate
Clock
Rate
o
1
05
Sync
Modes
Sync
Modes
Stop
Bits
1
o
1
Stop
Bits
o
01
Parity
Even/Odd
Parity (DO), If this bit is set. an additional bit position (in addition to those specified in the
bits/character control) is added to transmitted data and is expected in receive data. In the Receive
mode. the parity bit received is transferred to the CPU as part of the character. unless 8 bits/character is
selected.
Parity Even Odd (01)' If parity is specified, this bit determines whether it is sent and checked as even
or odd (1 =even).
Stop Bits 0 and 1 (02 and 03)' These bits determine the number of stop bits added to each
asynchronous character sent. The receiver always checks for one stop bit. A special mode (00) signifies
that a synchronous mode is to be selected.
03
Stop Bits 1
o
o
1
1
02
Stop Bits 0
o
1
o
1
Sync modes
1 stop bit per character
1V2 stop bits per character
2 stop bits per character
Sync Modes 0 and 1 (04 and 05)' These bits select the various options for character
synchronization.
Sync
Mode 1
o
o
1
1
Sync
Mode 0
o
1
o
1
a-bit programmed sync
1S-bit programmed sync
SDLC mode (0111111 0 flag pattern)
External Sync mode
Clock Rate 0 and 1 (06 and 07)' These bits specify the multiplier between the clock (TxC and RxC)
and data rates. For synchronous modes. the x1 clock rate must be specified. Any rate may be specified
for asynchronous modes; however, the same rOite must be used for both the receiver and transmitter.
The system clock in all modes must be at least 5 times the data rate.lfthe x1 clock rate is selected. bit
synchronization must be accomplished externally.
Clock Rate 1
Clock Rate 0
o
o
o
1
1
1
o
1
Data
Data
Data
Data
Rate
Rate
Rate
Rate
111-213
x1 -Clock Rate
x1S=Clock Rate
x32=Clock Rate
x64=Clock Rate
6.7
WRITE REGISTER 5
WR5 contains control bits that affect the operation of transmitter, with the exception of 02, which
affects the transmitter and receiver.
02
OTR
Tx
Bits/
Char 1
Tx
Bits!
Char 0
Send
Break
Tx
Enable
00
CRC-16/
SOLC
RTS
Tx
CRC
Enable
Transmit CRC Enable (DO), This bit determines if CRC is calculated on a particular transmit
character. If it is set at the time the character is loaded from the transmit buffer into the transmit shift
register, CRC is calculated on the character. CRC is not automatically sent unless this bit is set when
the Transmit Underrun condition exists.
Request To Send (01)' This is the control bit for the"RfS pin. When the Ffi'S bit is set, the RTS pin goes
Low; when reset, Ffi'S goes High. In the Asynchronous mode, RTS goes High only after all the bits of the
character are transmitted and the transmitter buffer is empty. In Synchronous modes, the pin directly
follows the state of the bit.
CRC-16/S0LC (02)' This bit selects the CRC polynomial used by both the transmitter and receiver.
When set, the CRC-16 polynomial (X'S + X'6 + X2 + 1) is used; when reset, the SOLC polynomial (X'6 +
X'2 + X5 + 1lis used. If the SOLC mode is selected, the CRCgenerator and checker are presettoalil's
and a special check sequence is used. The SOLC CRC polynomial must be selected when the SOLC
mode is selected.lfthe SOLC mode is not selected, the CRC generator and checker are presentto all O's
(for both polynomials).
Transmit Enable (03)' Oata is not transmitted until this bit is set and the Transmit Oata output is held
marking. Oata or sync characters in the process of being transmitted are completely sent if this bit is
reset after transmission has started. If the transmitter is disabled during the transmission of a CRC
character, sync or flag characters are sent instead of CRC.
Send Break (04)' When set, this bit immediately forces the Transmit Oata output to the spacing
condition, regardless of any data being transmitted. When reset, TxO returns to marking.
Transmit Bits/Character 0 and 1 (05 and 06)' Together, 06 and 05 control the number of bits in
each byte transferred to the transmit buffer.
06
Transmit Bits/
Character 1
05
Transmit Bits!
Character 0
1
1
o
o
o
Bits/Character
Five or less
o
7
6
8
1
1
Bits to be sent must be right justified, least-significant bits first. The Five Or Less mode allows
transmission of one to five bits per character; however, the CPU should format the data character as
shown in the following table.
07
06
05
04
03
02
01
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
111-214
00
0
0
0
0
0
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
Data Tenninal Ready (07)' This is the control bit for the OTR pin. When set, OTR is active (Low); when
reset, OTR is inactive (High).
6.8
WRITE REGISTER 6
This register is programmed to contain the transmit sync character in the Monosync mode, the first
eight bits of a 16-bit sync character in the Bisync mode or a transmit sync character in the External
Sync mode. In the SOLe mode, it is programmed to contain the secondary address field used to
compare against the address field of the SOLe frame.
07
Sync 7
6.9
Os
SyncS
05
Sync 5
04
Sync 4
03
Sync 3
02
Sync 2
01
Sync 1
00
Sync 0
WRITE REGISTER 7
This register is programmed to contain the receive sync character in the Monosync mode, a second
byte (last eight bits) of a 1S-bit sync character in the Bisync mode and a flag character (01111110) in
the SOLe mode. WR7 is not used in the External Sync mode.
07
Sync 15
Os
Sync 14
05
Sync 13
04
Sync 12
03
Sync 11
111-215
02
Sync 10
0; .
Sync 9
DO
Sync 8
111-216
7.0
READ REGISTERS
7.1
INTRODUCTION
The ZBO-SIO contains three registers, RRO-RR2 (Figure 7.1), that can be read to obtain the status
information for each channel (except for RR2-Channel B only). The status information includes error
conditions, interrupt vector and standard communications-interface signals.
To read the contents of a selected read register other than RRO, the system program must first write the
pointer byte to WRO in eXactly the same way as a write register operation. Then, by executing an input
instruction, the contents of the addressed read register can be read by the CPU.
The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example, when
the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the
appropriate error bits can be read from a single register (RR1).
7.2
READ REGISTER
a
This register contains the status of the receive and transmit buffers, the DCD, CTS and SYNC inputs,
the Transmit Underrun/EOM latch; and the Break/Abort latch.
Receive Character Available 100)' This bit is set when at least one character is available in the
receive buffer; it is reset when the receive FIFO is completely empty.
Interrupt Pending (01)' Any interrupting condition in the ZSO-SIO causes this bitto be set; however, it
is readable only in Channel A. This bit is mainly used in applications that do not have vectored interrupts
available. During the interrupt service routine in these applications, this bit indicates if any interrupt
conditions are present in all Z80-SIO. This eliminates the need for analyzing all the bits of RRO in both
Channels A and B. Bit 01 is reset when all the interrupting conditions are satisfied. This bit is always 0
in Channel B.
Transmit Buffer Empty (02)' This bit is set whenever the transmit buffer becomes empty, except
when a CRC character is being sent in a synchronous or SDLC mode. The bit is reset when a character
is loaded into the transmit buffer. This bit is in the set condition after a reset.
Data Carrier Detect (03)' The DCD bit shows the inverted state of the DCD input at the time ofthe
last change of any ofthe five External/Statusbits (DCD,
Sync/Hunt, Break! Abort or Transmit
Underrun/EOM). Any transition of the DCD input causes the DCD bit to be latched and causes an
External/Status interrupt. To read the current state ofthe DCD bit, this bit must be read immediately
following a Reset External/Status Interrupt command.
rn,
Sync/Hunt (04)' Since this bit is controlled differently in the Asynchronous, Synchronous and SDLC
modes, its operation is somewhat more complex than that of the other bits and, therefore, requires
more explanation.
In Asynchronous modes, the operation of this bit is similar to the DCD status bit, except that
Sync/Hunt showS the state ofthe SYNC input. Any High-to-Lowtransition on the SYNC pin sets this
bit and causes an External/Status interrupt (if enabled). The Reset External/Status Interrupt
command is issued to clear the interrupt. A Low-to-High transition clears this bit and sets the
External/Status interrupt. When the External/Status interrupt is set by the change in state of any
other input or condition, this bit shows the inverted state of SYNC pin at the time of the change. This
bit must be read immediately following a Reset External/Status Interrupt command to read the
current state of the SYNC input.
In the External Sync mode, the Sync/Hunt bit operates in a fashion similar to the Asynchronous mode,
except the Enter Hunt Mode control bit enables the external sync detection logic. When the External
111-217
Sync Mode and Enter Hunt Mode bits are set (for example, when the receiver is enabled following a
reset), the SYNC input must be held High by the external logic until external character synchronization
is achieved. A High at the SYNC input holds the Sync/Hunt status bit in the reset condition.
When external synchronization is achieved,SYNC must be driven Low on the seCond rising edge or
RxC on which the last bit of the sync character was received. In other words, after the sync pattern is
detected, the external logic must wait fortwo full Receive clock cycles to activate the SYNC input Once
SYNC is forced Low, it is a good practice to keep it Low until the CPU informs the external sync logic that
synchronization has been lost or anew message is aboutto start. Refer to Figure 18 for timing details.
The High-to-Low transition of the SYNC input sets the Sync/Hunt bit, which-in turn-sets the
External/Status interrupt. The CPU must clear the interrupt by issuing the Reset External/Status
Interrupt command.
When the SYNC input goes High again, another External/Status interrupt is generated that must also
be cleared. The Enter Hunt Mode control bit is set whenever character synchronization is lost or the end
of message is detected. In this case, the ZBO-SIO again looks for a High-to-Lowtransition on the SYNC
input and the operation repeats as explained previously. This implies the CPU should also inform the
external logic that character synchronization has been lost and thatthe ZBO-SIO is waiting for SYNC to
become active.
READ REGISTER BIT FUNCTIONS
Figure 7.1
READ REGISTER 0
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I
I
DO
I
I
Rx CHARACTER
AVAILABLE
INT PENDING (CH. A
ONLY)
Tx BUFFER EMPTY
DCD
SYNC/HUNT
CTS .
Tx UNDERRUN/EOM
BREAK!ABORT
*USEDWITH
"EXTERNAUSTATUS
INTERRUPT' MODE
j
*
READ REGISTER 1t
I
07
I
06
I
05
I
04
I
03
I
02
1
0
0
1
1
1
0
0
0
I
01
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)
111-218
I
DO
I
I
ALL SENT
I FIELD BITS
I FIELD BITS IN
IN PREVIOUS
SECOND
BYTE
PREVIOUS BYTE
0
3
*
0
4
0
5
0
6
0
7
0
8
1
8
2
8
*RESIDUE DATA FOR EIGHT Rx BITS/
CHARACTER PROGRAMMED
tUSED WITH SPECIAL RECEIVE
CONDITION MODE
READ REGISTER 2
I
07
I
Os
I
05
I
04
I
03
I
02
I
I
01
I
I
DO
I
VO
Vlt
V2t
V3t
V4
V5
VS
INTERRUPT
VECTOR
V7
tVARIABLE IF "STATUS AFFECTS VECTOR"IS PROGRAMMED
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to 1 by the Enter
Hunt Mode bit. The Sync/Hunt bit is reset when the ZOO-SIO establishes character synchronization.
The High-to-Low transition of the Sync/Hunt bit causes an External/Status interrupt that must be
cleared by the CPU issuing the Reset External/Status Interrupt command. This enables the ZBO-SIO to
detect the next transition of other External/Status bits.
When the CPU detects the end of message of that character synchronization is lost, it sets the Enter
Hunt Mode control bit, which-in turn-sets the Sync/Hunt bit to 1. The Low-to-High transition ofthe
Sync/Hunt bit sets the External/Status interrupt, which must also be cleared by the Reset
External/Status Interrupt command. Note that the SYNC pin acts as an output in this mode and goes
Low every time a sync pattern is detected in the data stream.
In the SOLC mode, the Sync/Hunt bit is initially set by the Enter Hunt mode bit or when the receiver is
disabled. In any case, it is resetto 0 when the opening flag ofthe first frame is detected by the ZOO-SIO.
The External/Status interrupt is also generated and should be handled as discussed previously.
Unlike the Monosync and Bisync modes, once the Sync/Hunt bit is reset in the SOLC mode, it does not
need to be set when the end of message is detected. The zao-slo automatically maintains
synchronization. The only way the Sync/Hunt bit can be set again is by the Enter Hunt Mode bit or by
disabling the receiver.
Clear to Send (05)' This bit is similar to the OCO bit, exceptthat it shows the inverted state ofthe CTS
pin.
Transmit Underrun/End of Message (06)' This bit is in a set condition following a reset (internal or
external). The only command that can reset this bit is the Reset Transmit Underrun/EOM Latch
command (WRO, Os and 07)' When the Transmit Underrun condition occurs, this bit is set; its
becoming set causes the External/Status interrupt, which must be reset by issuing the Reset
External/Status Interrupt command bits (WRO). This status bit plays an important role in conjunction
with other control bits in controlling a transmit operation. Refer to "Bisync Transmit Underrun" and
"SOLC Transmit Underrun" for additional details.
Break/Abort (07)' In the Asynchronous Receive mode, this bit is set when a Break sequence (null
character plus framing error) is detected in the data stream. The External/Status interrupt, if enabled, is
set when Break is detected. The interrupt service routine must issue the Reset External/Status
Interrupt command (WRO, CM02) to the break detection logic so the Break sequence termination can
be recognized.
The Break!Abort bit is reset when the termination of the Break sequence is detected in the incoming
data stream. The termination of the Break sequence also causes the External/Status interrupt to be
set. The Reset External/Status Interrupt command must be issued to enable the break detection logic
to look for the next Break sequence. A single extraneous null character is present in the receiver after
the termination of a break; it should be read and discarded.
In the SOLC Receive mode, this status bit is set by the detection of an Abort sequence (seven or more
l's). The External/Status Interrupt is handled the same way as in the case of a Break. The Break!Abort
bit is not used in the Synchronous Receive mode.
111-219
7.3
READ REGISTER 1
This register contains the Special Receive condition status bits and Residue codes for the I-field in the
SOLC Receive Mode.
01
End of
Frame
(SOLC)
CRC/
Framing
Error
Receiver
Overrun
Error
Parity
Error
Residue
Code 2
Residue
Residue
Code 1
Code 0
DO
All
Sent
All Sent (DO), In Asynchronous modes, this bit is set when all the characters have completely cleared
the transmitter. Transitions of this bit do not cause interrupts. It is always set in Synchronous modes.
Residue Codes 0, 1.and 2 (01-03)' In those cases ofthe SOLC receive mode where the I-field is not
an integral multiple of the character length, these three bits indicate the length of the I-field. These
codes are meaningful only for the transfer in which the End Of Frame bit is set (SOLC). For a receive
character length of eight bits per character, the codes signify the following:
Residue
Code 2
1
Residue
Code 1
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
Residue
Code 0
0
0
0
1
1
1
1
I-Field Bits
In Previous
Byte
0
0
0
0
0
0
1
0
I-Field bits are right-justified in all cases
2
I-Field Bits
In Second
Previous Byte
3
4
5
6
7
8
8
8
If a receive character length different from eight bits is used for the I-field, a table similar to the previous
one may be constructed for each different character length. For no residue (that is, the last character
boundary coincides with the boundary of the I-field and CRC field), the Residue codes are:
Residue
Code 2
0
0
0
0
BitS per Character
8 Bits per Character
7 Bits per Character
6 Bits per Character
5 Bits per Character
Residue
Code 1
Residue
Code 0
1
1
0
1
0
0
0
1
Parity Error (04)' When parity is enabled, this bit is set for those characters whose parity does not
match the programmed sense (even/odd). The bit is latched, so once an error occurs, it remains set
until the Error Reset command (WRO) is given.
Receive Overrun Error (05)' This bit indicates that more than three characters have been received
without a read from the CPU. Only the character that has been written over is flagged with this error,
but when this character is read, the error condition is latched until reset by the Error Reset command. If
Status Affects Vector is enabled, the character that has been overrun interrupts with a Special Receive
Condition vector.
CRC/Framing Error (061. If a Framing Error occurs (asynchronous modes), this bit is set (and not
latched) for the receive character in which the Framing error occurred. Detection of a Framing Error
adds an additional one-half of a bit time to the character time so the Framing Error is not interpreted as
a new start bit. In Synchronous and SOLC modes, this bit indicates the result of comparing the CRC
checker to the appropriate check value. This bit is reset by issuing an Error Reset command. The bit is
111-220
not latched, so it is always updated when the next character is received. When used for CRC error and
status in Synchronous modes, it is usually set since most bit combinations result in a non-zero CRC,
except for a correctly completed message.
End of Frame (07)' This bit is used only with the SDLC mode and indicates that a valid ending flag has
been received and that the CRC Error and Residue codes are also valid. This bit can be reset by issuing
the Error Reset command. It is also updated by the first character of the fQllowing frame.
7.4
READ REGISTER 2 (Ch. B Only)
This register contains the interrupt vector written into WR2 if the Status Affects Vector control bit is not
set. Ifthe control bit is set, it contains the modified vector shown in the Status Affects Vector paragraph
ofthe Write Register 1 section. When this register is read, the vector returned is modified by the highest
priority interrupting condition at the time of the read. If no interrupts are pending, the vector is modified
with V3=O, V2=1, and V 1=1. This register may be read only through Channel B.
Variable if Status
Affects Vector is
enabled
7.6
APPUCATIONS
The flexibility and versatility of the ZBO-SIO make it useful for numerous applications, a few of which
are included here. These examples show several applications that combine the ZBO-SIO with other
members of the ZBO family.
Figure 7.2 shows the simple processor-to-processor communication over a direct line. Both remote
processors in this system can communicate to the ZBO-CPU with different protocols and data rates.
Depending on the complexity of the application, other ZBO peripheral circuits (ZSO-CTC, for example)
may be required. The unused channel ofthe ZBO-SIO can be used to control other peripherals, or they
can be connected to other remote processors.
Figure 7.3 illustrates how both channels of a single ZBO-SID are used with modems that have primary
and secondary or reverse channel options. Alternatively, two modems without these options can be
connected to the ZBO-SID. A suitable baud-rate generator (ZBO-CTC) must be used for Asynchronous
modems.
Figure 7.4 shows the ZBO-SID in a data concentrator, a relatively complex application that uses two
ZBO-SIDs to perform a variety offunctions. The data concentrator can be used to collect data from many
terminals over low-speed lines and transmit it over a single high-speed line after editing and
reformatting.
The ZSO-DMA controller circuit is used with ZBO-SID #2 to transmit the reformatted data at high speed
with the required protocol. The high-speed modem provides the transmit clock for this channel. The
ZBO-CTC counter-timer circuit supplies the transmit and receive clocks for the low-speed lines and is
also used as a time-out counter for various functions.
The ZBO-SID #1 controls local or remote terminals. A single intelligent terminal is shown within the
dashed lines. The terminal employs a ZBO-SID to communicate to the data concentrator on one
channel while providing the interface to a line printer over its second channel. The intelligentterminal
shown could be designed to operate interactively with the operator.
Depending on the software and hardware capabilities built into this system, the data concentrator can
employ store-and-forward or hold-and-forward methods for regUlating information traffic between
slow terminals and the high-speed remote processor. If the high-speed channel is provided with a
dial-out option, the channel can be connected to a number of remote processors over a switched line.
111-221
SYNCHRONOUS/ASYNCHRONOUSPROCESSOR-TO-PROCESSOR COMMUNICATION (USING
TELEPHONE UNE)
Figure 7.2
-.
RSXYl
DRIVERS/
~ECEIVERS
-
lao
SID
-
l80
CPU
4~
l80
CPU
RSXYl
DRIVERS/
lao
SIO
~ECEIVERS
f+
~
~~
~
..
RSXYl
DRIVERS/
RECEIVERS
l80
SIO
-.
...
l80
CPU
BOTH CHANNELS OF A SINGLE zao-slo
Figure 7.3
PRIMARY
CHANNEL
CH.A
lao
CPU
RS232
DRIVER/
RECEIVER
lao
SIO
CH.8
SECONDARY
CHANNEL
111-222
-...
-
.
p
MODEM
ISYNCOR
ASYNCI
""
p
DATA LINK TO
REMOTE PROCESSOR
l!C
r------------SYSTEM aus
(DATA, ADDRESS 8. CONTROL)
I
I
I
I
SYSTEM
MEMORY
--
-
..
.
CH.A
lao
..
N
N
RS232
DRIVERS/
RECEIVERS
I
CPU
""-
-""
I
I
IL
lao
CH.A
Z80
SIO
#2
CH.B
ROY
i
--- ..
~
SIOCLOCK
GENERATOR
8. TIME OUT
COUNTERS
ROY
lao
DMA
- ...
-- .
UNE
PRINTER
~
a
l:I
lao
SIO
CPU
8.
MEMORY
0-
~
I
I
CTC
-,
I
• .-
[
I
I
.
--- .
.
Z80
________________
1
RS232
DRIVERS/
RECEIVERS
RS232
DRIVERS/
RECEIVERS
n
m
INTElliGENT
TERMINAL
~
I
RS232
DRIVERS/
RECEIVERS
RXCAr- TxCA
laO
RS232
DRIVERS/
RECEIVERS
I
CTC
.
W
I
t
(,J
PIO
I
I
SIO
#1
CH.B
DISPLAY
CONSOLE
-
lao
KEYBOARD
I
-------,
t
l
TERMINAL
_!U~
_____
I
TERM' NAL INTERFACES
I
COMMUNICATIONS UNK
HIGH-SPEED
MODEM
~:!:j
ii »
:-In
.so 0
Z
..... \
(SDLC PROTOCOL)
~
TO REMOTE PROCESSOR
I
I
...J
111-224
8.0
TIMING
8.1
READ CYCLE
The timing signals generated by a ZBO-CPU input instruction to read a Data or Status byte from the
Z80-SIO are illustrated in Figure 8.1.
READ CYCLE
WRITE CYCLE
Figure 8.1
Figure 8.2
T1
T2
TW
T3
T1
T1
cI>
4>
CE
CE
IORQ
iORO.
RD
RD
M1
M1
< OUT
DATA
8.2
>--
T2
TW
T3
T1
DATA
INTERRUPT ACKNOWLEDGE CYCLE
After receiving an Interrupt Request signal (iNT pulled Low,) the ZSO-CPU sends an Interrupt
Acknowledge signal (Ml and IC5FiQ both Low). The daisy-chained interrupt circuits determine the
highest priority interrupt requestor. The lEI of the highest priority peripheral is terminated High. For any
peripheral that has no interrupt pending or under service, IEO=IEI. Any peripheral that does have an
interrupt pending or under service forces its lEO Low.
To insure stable conditions in the daisy chain, all-interrupt status signals are prevented from changing
while Ml is Low. When IORQ is Low, the highest priority interrupt requestor (the one with lEI High)
places its interrupt vector on the data bus and sets its internal interrupt-under-service latch.
8.3
WRITE CYCLE
Figure 8.2 illustrates the timing and data signals generated by a ZBO-CPU output instruction to write a
Data or Control byte into the Z80-SIO.
.
ACKNOWLEDGE CYCLE
RETURN FROM INTERRUPT CYCLE
Figure 8.3
-J1
M1~~ ______________
IORQ
M1 \~__----JI
\~ _ _-II
RD
RD---------------------------------
00- 0 7
\::=::---~
DATA
\~__----JI
(VECTOR)
lEI
----------,~--------------+-------
----------' '
I
I
IEO _ _ _ _ _ _ _ _ _ _ _ _ _'-I:/
111-225
8.4
RETURN FROM INTERRUPT CYCLE
Normally, the ZSO-CPU issues a RETI (Return from interrupt) instruction at the end of an interrupt
service routine: RETI is a 2-bytebpcode (E0-40) that resets the interrupt-under-service latch to
terminate the interrupt that has just been processed. This is accomplished by manipulating the daisy
chain in the following way.
The normal daisy chain operation can be used to detect a pending interrupt; however, it cannot
distinguish between an interrupt under service and a pending unacknowledged interrupt of a higher
priority. Whenever "ED" is decoded, the daisy chain is modified byforcing High the lEO of any interrupt
that has not yet been acknOWledged. Thus, the daisy chain identifies the device presently under service
as the only one with an lEI High and an lEO Low. If the next opcode byte is "40",the interrupt-underservice latch is reset.
The ripple time of the interrupt daisy chain (both the High-to-Low and the Low-to-High transitions)
limits the number of devices that can be placedin the daisy chain. Ripple time can be improved with
carry-look-read, or by extending the interrupt aknowledge cycle. For further information about
techniques for increasing the number of daisy-chained devices, refer to Mostek Application Note on
extending the
Interrupt Daisy Chain.
zao
TYPICAL INTERRUPT SEQUENCE
FigureB.4
CHANNEL A CHANNEL A
RECEIVER TRANSMITTER
CHANNEL A
EXTERNAL/
STATUS
CHANNEL B
RECEIVER
CHANNEL B
TRANSMITTER
CHANNELB
EXTERNAL/
STATUS
1. PRIORITY INTERRUPT DAISY CHAIN BEFORE ANY INTERRUPT OCCURS.
2. CHANNEL B TRANSMITTER INTERRUPTS AND IS ACKNOWLEDGED.
SERVICE
SUSPENDED
3. EXTERNAL/STATUS OF CHANNEL A INTERRUPTS SUSPENDING SERVICE OF CHANNEl B
TRANSMITTER.
4. CHANNEL A EXTERNAL/STATUS ROUTINE COMPLETE. RETIISSUED. CHANNEL B TRANSMITTER
SERVICE RESUMED.
5. CHANNEL B TRANSMITTER SERVICE ROUTINE COMPLETE. SECOND RETIISSUED.
111-226
8.5
DAISY CHAIN INTERRUPT NESTING
Figure8.4illustrates the daisy chain configuration of interrupt circuits and their behavior with nested
interrupts (an interrupt that is interrupted by another with a higher priority).
Each box in the illustration could be a separate extern'al Z80 peripheral circuit with a user-defined order
of interrupt priorities. However, a similar daisy chain structure also exists inside the Z8()..SIO, which
has six interrupt levels with a fixed order of priorities.
The case illustrated occurs when the transmitter of Channel B interrupts and is granted service. While
this interrupt is being serviced, it is interrupted by a higher priority interrupt from Channel A. The
second interrupt is serviced and-upon completion-a RET1 instruction is executed or a RET1 command
is written into the Z80-SIO, resetting the interrupt-under-service latch of the Channel A interrupt. At
this time, the service routine'for Channel B is resumed. When it is completed, another RETI instruction
is executed to complete the interrupt service.
111-227
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs with respect to GND ........................................... -O.3V to + 7 .OV
Operating Ambient Temperature ............................................ As Specified in Ordering Information
Storage Temperature ........................................................................ -6Soe to +1S0oe
Stresses greater than those listed under Absolute Maximum Ratings mavcause permanent damage to the device. This is.8 stress rating only; op~ration aftha device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions. unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
2.1K
FROM OUTPUTo-_
UNDER TEST
• +4.7SV::; Vec ::; +S.2SV
• GND = OV
• TA as specified in Ordering Information
_+_-_....f....I
All ac parameters assume a load capacitance of 100 pF
max. Timing references between two output signals
assume a load difference of SO pF max.
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
UNIT
V,LC
Clock Input Low Voltage
-0.3
+0.80
V
V,HC
Clock Input High Voltage
VCC -0.6
+S.S
V
V,L
Input Low Voltage
-0.3
+0.8
V
V,H
Input High Voltage
+2.0
+S.S
V
VOL
Output Low Voltage
+0.4
V
VOH
Output High Voltage
+2.4
'll
Input Leakage Current
-10
IZ
3-State Output/Data Bus Input
Leakage Current
'L(SY)
SYNC Pin Leakage Current
ICC
Power Supply Current
TEST CONDITION
V
= 2.0mA
IOH = -2S0 JJ.A
±10
JJ.A
OC
DATA VALID
\
/
WRITE
X
4.4
DATA VALID
>C
1/0 TIMING
Figure 4.0-3 illustrates timing of liD Read or Write Operations with the Combo chip. These cycles
are independent of the Timer clock (TCLK) input. This feature allows the MK3886 to be CPU
independent. The input address lines and chip select are latched and all 110 cycle timing is initiated
from the falling edge of 10RO. Notice that the timing is very similar to the memory timing. The chip
select and liD address linesA3-AO must be stable before the falling edge of 10RO. The status of RD
and WR dictate whether a Read or Write cycle will occur. If RD becomes active, a data byte will be
gated from the selected liD port onto the data bus. If the selected port is Write only, no data will
appear and consequently be interpreted as all "1 's" by the CPU. Data is valid on the bus as long as
RD is active. If an liD operation is selected and INR becomes active, data is gated from the bus into
the addressed register port on the rising edge ofWR.
111-249
1/0 READIWRITE CYCLE TIMING
Fjgure 4.0-3
AO-7
~
..J)(I..____-:-_______
_ _V_A_L_ID
__
CSIO
lORa
\'---------/
RD
\'---------/
---<
00-7 - ____ - - - - - .... - - - - - - - - - - - - - - -
READ
DATAOUTPUTVAUD
) - -'- - - - - -
\'-------/
DO-7------------------~~~
4.5.
_ _ _D_A_T_A_V_A_U_D_ _
WRITE
~:>~---------
STANDBY POWER MODE
The MK3886 is designed to provide a low power standby mode for the 64 low order bytes of the
on-chip RAM. The standby power source(VSB) is connected to pin 37, RAM Protect Control is tied to
the '"FiESE'F pin and the substrate decoupling capacitor tied to pin 29. V CC must be greater than 4.75
volts before RESET changes states. As the power comes up, RESET should be held low until V CC is
above the minimum level.
Figure 4.0-4 illustrates the timing associated with this circuit for two cases. The first case illustrates
timing where no save routine is required. In this case whatever data is in the RAM is saved as power
goes down (assuming the RESET condition is satisfied). The second case demonstrates how an
external interrupt is generated notifying the processor of an impending power failure. All key data
must be stored in the RAM. After the save is done, RESET can fall. Remember that upon power up,
this portion of the RAM will be in the Read Only mode.
111-250
STANDBY POWER TIMING
Figure 4.0-4
CASE 1
I
1
______-,4!~:._
___M_UST BE GREATER THAN OR EQUAL TO 4 . 7
...._.....!!o1...l
? _ __
VC~AIN
POWER SUPPLY :
FAILURE DETECTED - ,
1
~
::
i
-
1
1
J:~II---
\
RESET
»~--------~.
I"
Vce SUSTAINED BY CAPACITOR OR
BATI'ERY UNTIL RAMPRT BROUGHT LOW
CASE 2
I
I
I
I
1
1
:\
1
I
~
________
____________
:
~1
MAIN POWER SUPPLY
FAILURE DETECTED
INT1
t
I
~
1-<:--:-
~1
I
I
I
1
1
I
((
/)
MUST BE AT LEAST 4.76 V
I
I
,
~\----t./__-;--- L-f,f--.(----Ii
I
I
I
I
'
'
' I
RESET
I
,
i~\~_________~(~(________~!~
____-JI
1
1
I
_ I DATA SAVE MUST ' - - :--___
: BE DONE HERE
I
I
'
I
,
1
111-251
)/
ACCESS TO
RAM INHIBITED
,
1
:
-----!- EXECUTION CAN
I
1
BEGIN AGAIN
111-252
5.0
TIMERS A AND B
6.1
OVERVIEW
The MK3886 has two programmable timers, designated as Timer A and Timer B. Each timer
consists of an 8-bit binary Down Counter, a programmable Prescaler, a Time Constant Register, and
a Zero Count output. There are some differences between Timer A and B. These differences
basically are due to the fact that the INTO line is tied directly to Timer A's control circuitry. This
feature gives Timer A three modes of operation: Interval Timer, Pulse-Width Measurement, and
Event Counter. Timer B operates in the Interval Timer Mode only. A basic block diagram which
applies to both Timers is illustrated in Fig. 5.0-1. The following description highlights the major
functions of each block.
TIMER BLOCK DIAGRAM
Figure 5.0-1
INTO
ZERO COUNT ZC
(TIMER A ONLY)
4l-T-C-LK~
PRESCALER
CLOCK
TIMER
B-BIT DOWN COUNTER
TIMER CONTROL
REGISTER
AND LOGIC
a-BITS
TIMER
INTERRUPT
CONTROL
TIME CONSTANT
REGISTER
a-BITS
5.1.1. THE CHANNEL CONTROL REGISTER AND LOGIC
The Channel Control Register (8-bit) and Logic, is written to by the CPU to select the modes
and parameters of the channel. Within the Combo chip there are two such registers,
corresponding to Channel A and Channel B. Each register is assigned a separate I/O port
address selected by the state of the lower fou r address inputs, (A3-AQ). For specific 1/0 port
assignments for each Timer, refer to the "Programming" section for each timer channel or
Section 8.0, "Combo Programming Summary."
5.1.2. THE PRESCALER
Both Timer A and Timer B have a Prescaler which can be programmed via the appropriate
Timer Control Register to divide its input, TCLK, by a predetermined prescale value. The
output of the Prescaler is then used to clock the Down Counter in the Interval Timer Mode of
operation or in the Pulse-Width Measurement Mode of operation. (Pulse-Width
Measurement on Timer A only).
111-253
5.1.3. THE TIME CONSTANT REGISTER
The Time Constant Register is an a-bit register used in all count modes and is programmed
by the CPU with an integer time constant value otO through 255. Under normal operation,
this register is loaded into the Down Counter when the Time Constant Register is first
written to and is reloaded automatically thereafter whenever the Down Counter counts to
zero. (For details of how a time constant is written to a Timer channel, see 5.2.1
"Programmi,ng Timer A" and 5.3.1 "Programming Timer, S").
5.1.4. THE DOWN COUNTER
The Down Counter is an a-bit register used in all count modes. The Down Counter is
decremented by the INTO edge in the Event Counter Mode (Timer A only), or by the clock
output of the Prescaler in the Interval Timer Mode. Atany time, the contents of the Down
Counter can be read by performing an I/O READ ofthe port address assigned to the Down
Counter of the selected Timer channel. Either timer channel may be programmed to
generate an interrupt request sequence each time the zero count condition in the Down
counter is reached.
5.2.
TIMERA
Timer A can function in the Interval Timer Mode, the Pulse Width Measurement Mode, or the Event
Counter Mode. The Interval Timer mode is used to count TCLK clock periods to generate accurate
time intervals. The Pulse Width Measurment Mode is used to accurately measure the duration of a
pulse applied to the INTO pin. The Timer begins counting TCLK clock periods when INTO becomes
active and stops when it returns to the inactive state. Timer A can also count pulses applied to the
INTO pin when it is programmed to operate in the Event Counter mode. A functional diagram of
Timer A circuit is shown in Figure 5.0-2.
TIMER A FUNCTIONAL SCHEMATIC
Figure 5.0-2
FROM TIMER A CONTROL PORT
I
INTO
EDGE
START/
STOP
PULSE WIDTH
INT TIMER
+2
+6
PORT 1
(READ)
+20
'1' SELECTS
INPUT A
TClK
-t--+--j
INTO _ _-"'--,,,
111-254
INTO
ENABLE
tiMER A
INTENABlE
5.2.1
PROGRAMMING TIMER A
The desired timer operation is selected by loading the Timer A Control Register. This
register is designated as Port 0 and is WRITE only.
The format of the Timer A Control Register is as follows:
07
06
05
04
03
02
+20
+5
+2
TIMER A
INTO
INTO
Interrupt
Enable
ENABLE
EDGE
DO
01
PULSE
Z
NTERVAL
TIMER
~
STOP
Bit 7, 6, 5 - Prescaler constants.
These bits determine the possible division values selectable for the prescaler. Any of three
conditions will cause the prescaler to be reset whenever RESET is active, whenever the
timer is stopped by clearing bit 0 (Start/Stop), or on the trailing edge transition of the INTO
pin when in the Pulse Width Measurement Mode. The following table defines the value
of the prescaler for various bit assignments.
07
06
o
o
o
1
1
o
1
1
1
1
05
PRESCALE
1
+2
+5
+10
+20
o
1
o
o
o
1
+40
1
+100
+200
o
1
1
Bit 4 - Timer A Interrupt Enable
When set, this allows Timer A to generate an interrupt request sequence every time the
Down Counter reaches a zero count condition.
When cleared interrupts are disabled and any pending interrupt is cleared.
Bit 3 - INTO Interrupt Enable
When set, this allows INTO to generate an interrupt on the active edge selected by Bit 2.
When cleared, interrupts are disabled and any pending interrupt is cleared.
Bit 2 - INTO Edge Active Level
When set, INTO is active high.
When cleared, INTO is active low.
Bit 1 - Pulse Width/Interval Timer Mode Select
When set, the Pulse Width Measurement Mode is selected.
111-255
When cleared and bits 7,6, and 5 are also cleared, the Event Counter Mode is selected. If
any prescale bit is set, the Interval Timer Mode is selected.
Bit 0 - Start/Stop
When set, it will
~nable
the Timer for operation.
When cleared, it will stop the counter and reset the prescaler.
Port 1 is designated as the Time Constant Register for Timer A. When a write operation is
made to the port, both the time constant register and the Down Counter are loaded. The
following is the bit assignment for the Port:
07
06
05
04
03
02
01
DO
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TCO
The following sections illustrate the operation of the Timer A Control Register in
conjunction with each of the three possible timer modes.
5.2.2
INTERVAL TIMER MODE
When Port 0 bit 1 is cleared and at least one prescale bit is set, the Timer operates in the
Interval Timer Mode. This mode counts the prescaled system clock and generates a zero
count output, ZCA, and an interrupt (if enabled) every time it counts to zero. When bit 0 of
the Control Register is set, the Timer will start counting down from the modulo-N value
loaded by the Time Constant Register. After counting down to H'01', the Timer returns to
the modulo-N value at the next count. On the transition form H'01' to H'N' the Timer sets a
timer interrupt request latch. Note thatthe interrupt request latch is set by the transition to
H'N' and not the presence of H'N' in the Timer, thus allowing a full 256 counts if the Time
Constant Register is preset to H'OO'. If bit 4 of the Control Register is set and the Timer
Interrupt is not masked by bit4 of Port 9, the interrupt request will be passed onto the CPU.
However, if bit 4 of the control register is a logic 0, the Interrupt Request is not recorded by
the Timer Control logic.
Consider an example in which the Time Constant Register is loaded with H'64' (deCimal
100). The timer interrupt request latch will be set and the ZCA output will be pulsed at the
100th count following the timer start and will be repeated precisely on every 100 count
interval.lfthe prescaler is set at +5, the timer will count to zero every 500 TCLK periods. For
a 2.5MHz TCLK clock, this will produce a 200 micro-second interval. The period of ZCA is
given by tc*P*TC where tc is the TCLK period, P is the prescale value, and TC is the time
constant value.
The range of possible intervals is from 2 to 51,200 TCLK clock periods (.8 microsecond to
20.48 milliseconds for a 2.5 MHz clock). However, approximately 50 TCLK periods is a
practical minimum because of interrupt service time requirements by the CPU. To establish
time intervals greater than 51,200 TCLK clock periods is a simple matter of using the timer
interrupt service routine to cvunt the number of interrupts, saving the result in a CPU
register until the desired interval is achieved. With this technique virtually any time interval,
or several time intervals, may be generated.
The Timer may be read at anytime and in any mode using an input instruction and may take
place "on the fly" without interferring with normal timer operation. Also, the Timer may be
stopped at any time by clearing bit 0 of the Control Register. The Timer will hold its current
contents indefinitely and will resume counting when bitO is again set. Recall however that
the prescaler is reset whenever the Timer is stopped; thus a series of starting and stopping
will result in cumulative truncation errors.
111-256
5.2.3
PULSE WIDTH MEASUREMENT MODE
When Timer A Control Register bit 1 is set (logic 1) and at least one prescale bit is set, the
Timer operates in the Pulse Width Measurement Mode. This mode is used for measuring
the duration of a pulse applied to the INTO pin. The Timer is stopped and the prescaler is
reset whenever INTO is at its inactive level. The active level of INTO is defined by Control
Register bit 2; if cleared, INTO is active low; if set. INTO is active high. If bit 0 is set, the
prescaler and Timer will start counting whenever a transition is made to the active level on
INTO. When INTO returns to the inactive level,the Timer then stops, the prescaler resets,
and if bit 3 is set, an external interrupt request latch is set.
As in the Interval Timer Mode, the Timer may be read at anytime, or may be stopped at any
time by clearing Control Register bit O. The prescaler and Control Register bit 4 function as
previously described and the Timer still functions as an 8-bit binary down counter with the
timer interrupt request latch being set on the Timer's transition from H '01' to H 'N'. Note
thatthe INTO pin has nothing to do with loading the Timer; its action is that of automatically
starting and stopping the Timer and of generating external interrupts. Pulse widths longer
than the prescale value times the modulo-N value are easily measured by using the timer
interrupt service routine to store the number of timer interrupts in one or more CPU
registers.
As for accuracy, the actual pulse duration is typically slightly longer than the measured
value because the status of the prescaler is not readable and is reset when the Timer is
stopped. Thus for maximum accuracy it is advisable to use a small division setting for the
prescaler.
5.2.4
EVENT COUNTER MODE
When Timer A Control Register bit 1 is cleared and all prescale bits(S, 6, and 7) are cleared
the Timer operates in the Event Counter Mode. This mode is used for counting pulses
applied to the INTO pin. IfTimer A Control Register bit 0 is set, the Timer will decrement on
each transition from the inactive level to the active level on the INTO pin. The prescaler is
not used in this mode.
Normally, control Register bit 3 should be kept cleared in the Event Counter Mode;
otherwise, external interrupts will be generated on every transition from the inactive level to
the active level of the INTO pin.
5.2.5
ZCA Output
Timer A generates an output called lCA whenever a transition (LOAD) is detected from
H'Ol 'to H'N' in the Down Counter indicating that zero count has occurred. An output will be
generated onlCA that is an integral multiple of TCLK cycles. The number ofTCLK cycles is a
function of the selected value of the Prescaler. For example if the Prescaler is set at 2 then
the lCA output will be active for 2 TCLK cycles. This is illustrated in the timing diagram in
Figure 6.4. Since the Prescaler is not used in the Event Counter mode, the lCA output will
only stay active for one INTO clock period. The output state of lCA is not defined when the
Time Constant Register is loaded with H"Ol ". Figure S.0-3 illustrates two cases for lCA
Output Timing.
111-257
lCA OUTPUT TIMING
INTERVAL TIMER AND PULSE WIDTH MODE
PRESCALER 2
=
Figure 5.0-3
TCLK
___----'I
LOAD
\~----------------
\\.-___---Jr
EVENT COUNTER MODE
INTO ACTIVE HIGH
5.3
INTO
-.-I
LOAD
~
ZCA
\
\
/
\
I
\
/
TIMER B
Timer B is similar in operation to Timer A; however, it functions only as an Interval Timer. Its output,
ZCB, is different from Timer A in that it toggles every time it counts down to zero. This feature
automatically produces a square wave which is one-halfthe time out frequency. This a"owsZCB to
be tied directly to the SRCLK pin to be used as the serial port clock. A functional diagram ofTimer B is
shown in Figure 5.0-4.
5.3.1
PROGRAMMING TIMER B
Control of the timer circuitry is provided through the Timer B Control Register. It is
designated as Port 2 and is WRITE only. The following diagram illustrates the bit
assignments within the register.
Timer B Control Register
07
06
05
04
03
PS1
PSO
X
X
Start
~
Stop
02
Timer B
Interrupt
Enable
The description of each bit assignment is as follows:
Bits 7 and 6 - PS1 and PSO
111-258
01
DO
X
X
These bits determine the division values selectable for the prescaler. The following bit
assignments are made for the corresponding prescale values.
PS1
PSO
PRESCALE
0
0
1
1
0
1
0
1
+2
+5
+10
+20
Bits 5 and 4 - Don't care
Bit 3 - Start/Stop
When set, the timer will be enabled to count.
When cleared, the timer will stop counting and the prescaler will be reset.
Bit 2 - Timer Interrupt Enable
When enabled, this bit allows Timer B to generate an interrupt request sequence every time
the Down Counter reaches a zero count condition and if the Timer B Interrupt Mask
Register (Port 9) bit 5 is enabled.
When cleared, interrupts are disabled and any pending interrupt is cleared.
Bits 1 and 0 - Don't Care
5.3.2
TIMER B TIME CONSTANT REGISTER
As with Timer A, Timer B has a single 8-bit Time Constant Register. However, Timer B's
Register has two modes of addressing. In the first mode the Time Constant Register and the
Down Counter are immediately loaded where in the second mode only the Time Constant
Register is loaded. The Former addressing mode is performed with a write command to Port
3; the latter addressing mode is commanded with a write command to Port 4.
During a write command. Port 3 is loaded with a data byte and its contents are immediately
loaded into the Down Counter and Time Constant Register regardless of its present state.
When this register is read, the present value of the Down Counter is examined.
Port 4 also addresses Time Constant Register forTi mer B. This port is Write only. Writing to
this port will not disturb the currenttimer count. When a new value of Port 4 is loaded, it will
not be transferred to the Down Counter until it counts down to zero. With this feature it is
possible to generate asymetrical wave forms with the ZCB output. The bit assignments for
the port are as follows:
TIMER B TIME CONSTANT REGISTER
07
06
05
04
03
02
01
00
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TCO
111-259
TIMER B FUNCTIONAL SCHEMATIC
Figure 5.0-4
FROM TIMER B CONTROL REGISTER
{~
________
__________
~A
07
03
08
~
02
PORT 3
(READ ONLY)
r-----~D
TIMERB
INTERRUPT
al---~-'
MASK
PORT 9
BIT 5
LOAD
TIMER B
INTACK
--r--q_/
DOWN COUNTER
LOAD
02 - INTERRUPT ENABLE
03 - START/STOP
D8-PSO
.
D7-PS1
LOAD
PORT 4
(WRITE
ONLY)
5.3.3
ZERO COUNT OUTPUT - ZCB
ThelCB output is inverted every time Timer B counts to zero. This can be used to produce a
square wave output which is one half the timeout frequency. However, this can be easily
modified to generate a pulse train with a variable pulse width and interpulse interval.
If a square wave is desired, the output period of lCB is given by the formula:
2*P*lc*TC
where lc is the period ofTimer Clock, TCLI<, P is the Prescaler factor, TC is the time constant
data word, and 2 is a constant to adjust for the toggle outputfeature on ZCB. Once the
desired Time Constant and Prescale values are loaded and the Timer started, a continous
square wave will be produced. Figure 5.0-5 illustrates the timing relationship for the lCB
output with a Prescale and Time Constant value of two.
Writing to the Timer B Counter Register, Port 3, will set lCB. Writing the Timer B control
Register (Port 2) with the Stop bit (3) equal to zero will force lCB to·be a zero. An active
RESET signal will also reset lCB.
111-260
zeB OUTPUT TIMING
Figure 5.0-5
PRESCALER =2
TIME CONSTANT
=2
TCLK
LOAD
DOWN
COUNTER
zca
111-261
111-262
6.0
SERIALIIO
6.1
OVERVIEW
The MK3886 contains circuitry to perform serial data transfers into and out of the unit under
program control. The serial port will allow input and output of either asynchronous or synchronous
serial data. The port consists of a 16-bit shift register that can be read from or written to while data is
being shifted into or out ofthe shift register. This port, controlled by the CPU, can provide serial data
communications or be used to interface external serial logic. The port uses 3 I/O pins to provide
input (SRIN), output (SROUT), and clock (SRCLK) for the serial data.
The block diagram shown in Fig. 6.0-1 depicts the functional operation of the Serial Port. This
diagram should be used as a reference throughout the remainder of the Serial Port description.
SERIAL PORT BLOCK DIAGRAM
Figure 6.0-1
PORT 6 SERIAL PORT CONTROL (WRITE ONLYI
XMIT
EDGE
TRIGGER
+1/+16
SERIAL REC
INTeRRUPT
ENABLE
LOAD N2 N1 NO
PORT 5 STATUS (READ ONLYI
.nw"~O:LY
COUNTER
ZERO
E.W.O.
SYNC
06
"1 "SELECTS + 1
E.O.W.
INTERRUPT
REC/XMT
INTERRUPT
ACKNOWLEDGE
SROUT
>-~~D
~~--------~--~
Q~------~27
6.1.1. SHIFT REGISTER
The Shift Register in the serial port is 16 bits long and can be read or written to at anytime. It
is addressed by the CPU via two ports that access two 8 bit bytes. The Upper Shift Register is
defined as Port 6 and is used to access the most significant 8 bits. The Lower Shift Register
is defined as Port 7 and is used to access the least significant 8 bits. Bit 0 is the least
significant bit of the Shift Register. It is used to form the serial output, SROUT. Bit 15 is the
most significant bit of the Shift Register. It is the bit position where serial input data first
enters the Shift Register.
111-263
6.1.2. SHIFT CLOCK
The internal SHIFT Clock is used to clock data transfers into and out of the 16-bit Shift
Register. It is also used to clock the internal Bit Counter register. In the receive mode, data is
clocked into the most significant bit of the upper half ofthe shift register (Port 6) on the rising
edge of the SHIFT clock. In the transmit mode, output data is transferred from the least
significant bit of the lower half of the Shift Register to the output (SROUT) latch when the
SHIFT clock is at a low level. The SHIFT clock is derived from the SRCLK input and is
programmed to operate in a +1 mode or a +16 mode from the SRCLK input.
6.1.3
BIT COUNTER
The Bit Counter is initally reset to zero and remains in said state until the first bit of a new
serial word is clocked into the MSB ofthe upper half ofthe shift register. The Bit Counter is
then incremented as the successive bits are clocked into the shift register. Counting occurs
on the rising edge of SHIFT. When the last bit ofthe programmed number of bits in the word
is received (clocked into the shift register), the Bit Counter will reset itself to zero. An
interrupt will be generated (if enabled) on the rising edge of SHIFT that resets the counter at
the count of the specified number of bits per word. This allows the CPU to be interrupted at
the word rate, not the bit rate. If the edge trigger mode is not selected, the Bit Counter will
continue to count and interrupt regardless of whether new data is being input or output.
Writing a new control word to the Serial Port automatically resets the Bit Counter to state
zero.
6.1.4. EDGE DETECT CIRCUIT
The Edge Detect Circuit is used in conjunction with the asynchronous receive mode in order
to prevent false start of word detection. This requires that the edge trigger circuit is enabled
by bit D5 of Port 5 and that the +16 mode is selected.
When programmed, the +16 counter is reset and SHIFT clock is held low until a negative
transition on the SRIN pin has occurred. After this edge has been detected, the circuitry will
continue to hold SHIFT clock low and will sample the logic level on the SRIN input for 7
SRCLK pulses. If the SRIN input has remained low throughout this time, then the start-ofword is assumed to be valid and SHIFT goes high coincident with the rising edge of the 8th
SRCLK pulse. The data on the SRIN input is then clocked into the shift register by the SHIFT
clock in the middle of each bit time.
When the preprogrammed number of bits per word are counted by the bit counter, an
End-of-Word interrupt occurs. At this time the +16 counter will be reset and the Edge
Detector rearmed in preparation for the next character. This scheme provides reliable
character synchronization with data sampling in the middle of each bit time.
6.1 .5. CONTROL CIRCUITRY
The Control Circuitry provides correct timing and coordination of the functions within the
Serial Port. Additionally, it is responsible for loading the Bit Counter and processing
interrupts for the PORT. Programmer control is directed through Port 5, the Serial Port
Control Register. Specifically, the register controls whether the serial port is in the transmit
or receive mode, the +1 or +16 clock select, edge trigger, interrupt enable, and the number
of shifts per word.
111-264
6.2
PROGRAMMING THE SERIAL PORT
6.2.1
SERIAL CONTROL REGISTER
Control of the Serial Port is provided via the Serial Control Register. This Register is
designated as Port 5 and is WRITE only. The bit designation is as follows:
Port 5 - SERIAL CONTROL REGISTER
07
+1
06
05
03
XMIT
~~
+16
04
EDGE
Trigger
X
RCV
01
02
Serial Port
Interrupt
Enable
N2
DO
N1
NO
Bit 7 - +1/-16 Select
When set, SRCLK is used as the internal SHIFT clock.
When cleared, SRCLK is divided by 16 to form the internal SHIFT CLOCK.
Bit 6 - XMIT/RCV
If set, the port is configured for the transmit mode.
When cleared, the port is configured for the receive mode.
Bit 5 - Edge Trigger
This bit is used primarily in the +16 receive mode for asynchronous data reception. When
set, edge trigger mode is selected. When a negative transition is detected on the SRIN Input,
the SHIFT CLOCK will begin to count. The state of SRIN is tested on the 7th clock pulse in
order to assure a valid Start bit was detected. If the Start is valid, the Shift Register will be
shifted on the 8th SRCLK pulse and subsequently every 16 pulses later until the
preprogrammed shifts per word occur. At this time an End-of-Word interrupt flag occurs,
and the Edge Detect circuit is rearmed.
If cleared the Edge Detect circuit is disabled. SRCLK is either divided by 1 or by 16 to
generate SHIFT CLOCK and is not controlled by the edge detect circuit.
Bit 4 - Don't Care
Bit 3 - Serial Interrupt Enable
When set, an interrupt will be generated when the programmed number of shifts per word
has occurred in either the transmit or receive mode. A different interrupt vector is generated
for the transmit and receive modes.
When cleared, interrupts are disabled. Any pending interrupts will be cleared.
Bits 2, 1,0 - N2,N1 ,NO
111-265
These bits determine the serial word size for both transmit and receive by the number of
shifts per word. The values selected represent the shift configuration needed to interface
most serial external logic and synchronous or asynchronous data communication
channels. The bit designation is as follows:
N2
N1
NO
Shifts/Word
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
7
8
9
10
11
12
16
6.2.2. SHIFT REGISTER PROGRAMMING
The Shift Register is divided into two 8-bit ports. These bytes are accessed via Ports 6 and 7
which are the Upper and Lower Shift Register bytes respectively. Both ports are
Read/Write. Bit deSignation for the two ports are as follows:
Port 6 - UPPER SHIFT REGISTER
07
06
05
04
03
02
01
DO
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
Port 7 - LOWER SHIFT REGISTER
07
06
05
04
03
02
01
DO
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SRO
6.2.3. STATUS REGISTER
A register is provided on the MK3886 that provides information as to the status of particular
functions within the chip. This register is Read Only and accessed as Port 5. The bit
designation is as follows:
Port 5 - STATUS REGISTER
07
II BitCounter
06
05
04
03
02
01
DO
End of
Word Sync
RAM
Protect
X
X
INT2
INT1
INTO
Zero
111-266
Bit 7 - Bit Counter Zero
When set, this bit indicates the Bit Counter is in the zero state.
Bit 6 - End of Word Sync
When set, this bit indicates that the bit counter of the serial port is in the ZERO state AND
the SHIFT clock is at a high level.
Bit 5 - RAM Protect
If set, it indicates the RAM write protection circuitry is enabled. Attempts made to write in
the lowest 64 bytes (0-63) of RAM will be unsuccessful. There is no indication if an illegal
write was attempted.
If clear, then all areas of RAM can be written to by the CPU.
Bits 2,1, and 0 External Interrupt State.
These bits indicate the current logic level being applied to External Interrupt inputs INT2,
INTl, and INTO.
6.3
ASYNCHRONOUS RECEIVE MODE
Figure 6.0-2 illustrates the timing for an example using the Serial Port in the asynchronous receive
mode. For operation in this mode, the Serial Port Control Register should be programmed for
Receive (XMITIREC=O) and the Edge Trigger bit should be enabled. Also, the +16 mode should be
selected since this also enables the Edge Detectcircuitry. Upon selecting the +16 and Edge Trigger,
both the Bit Counter and the +16 counter are reset and held low until a negative transition occurs on
the SRIN pin. After a valid edge has been detected (see section 6.1.4), the SHIFT clock will go high and
the bit count will begin at the eighth SRCLK pulse and will continue to clock every sixteenth clock
pulse thereafter. When the programmed number of bits have been shifted in, the Bit Counter will be
reset to zero and an End-of-Wordinterrupt will be generated. After the falling edge of SHIFT
following the End-of-Word interrupt, the Edge Detect circuitry will be rearmed in preparation for the
next word. Thus, if a start bit is present immediately following the time when the Edge Detect
circuitry is rearmed, SHIFT clock will again go high approximately one bit-time after the rising edge
of SHIFT which reset the Bit Counter and caused the End-of-Word interrupt. In other words, SHIFT
can go high again on the eighth SRCLK pulse as soon as the Edge Detect circuitry is rearmed.
The Shift Register must be read before the next rising SHIFT CLOCK edge; otherwise, the data will
be shifted to the right by one bit. Since data is gated directly on the data bus from the Shift Register, it
must be read witin one bit time. For a 9600 bps data rate, this would require reading the Register
within 104 microseconds from the time that the End-of-Word interrupt is generated.
It is possible to detect a receiver overrun condition by examining the state ofthe Bit Counter. Bit 7 of
Port 5 is designated as Bit Counter Zero (BCZ). After a end of word receive interrupt is processed, the
data in the shift register is transferred to processor. If Bit 7 is then read and is a logic 1 no overun
error has occurred. If the bit is a logic 0 an error has occurred.
The example in Figure 6.0-2 shows the timing required for asynchronous data reception from a
device such as a teletype. Within this data stream is start, stop, and data bits. A typical format
requires 1 start bit, 8 data bits and 2 stop bits for a total of 11 bits. All these bits will be residing inthe
16 bit shift register when the End of Word interrupt is generated. It is, therefore, necessary to strip
the start and stop bits from the data. An example of this is shown in Section 9 concerning MK3886
Applications.
111-267
SERIAL PORT TIMING ASYNCHRONOUS RECEIVE
Figure 6.0-2
SHIFT CLOCK
STATE
00
N·3
N
N-2
N-1
00
BIT COUNTER ZERO
~------jj~----------------'
INT
6.4
---------------------j,j~---------------,
SYNCHRONOUS RECEIVE
For synchronous operation, the Edge Trigger Mode must not be selected and bit 6 (XMIT/REC)
should be a O. Also, the +1 SHIFT Clock mode should be selected to establish the SRCLK input as the
synchronization clock for the data stream. Once the Serial Port Control word is written to with Edge
Trigger = 0 and the-;-1 SHIFT clock mode selected, then the Serial Port will continuously shift data
into the MSB of the upper half of the Shift Register at the +1 clock rate and interrupt when the
programmed number of bits have been shifted in.
An illustration of receive timing is shown in Figure 6.0-3. This diagram is for a +1, no edge triggered,
sychronous receive sequence for a 5 bit word. Note the relationship of SHIFT clock, state of the bit
counter, and Bit Counter Zero. Since Edge Trigger is not enabled(Port 5, bit5=0)the Bit counter will
continue to count and interrupt at the word rate regardless of whether or not new data is being
received. Writing a new control word to the Serial Control Port automatically resets the bit counter to
zero. Note that when the End-of-Word interrupt is received, the Shift Register must be read before
the rising edge of the next SHIFT clock pulse or data will be shifted to the right. At 9600 bps this
requires reading the Shift Register within 104 microseconds of the End-of-Word interrupt. As
explained in the previous section on Asynchronous Operation, the Bit Counter zero flag in the Status
Register can be used to verify the integrity of the data read from the shift register.
Writing to Port 5 resets the bit counter to zero.
111-268
SERIAL PORT SYNCHRONOUS RECEIVE TIMING
Figure 6.0-3
SHIFT
CLOCK
BIT
COUNTER
STATE
00
BIT
COUNTER
ZERO
END-OFWORD SYNC
6.5
01
02
03
04
00
J
n ~________________________~r--l~_______________
ASYNCHRONOUS OR SYNCHRONOUS TRANSMIT MODE
The Transmit mode is selected by setting bit 6 (XMITIREe) of the Serial Port Control word. In the
transmit mode data loaded into the Shift Register is enabled out of the Port 7 on the falling edge of
SHIFT CLOCK with the least significant bit, SRO, first. Data from the internal data bus is loaded
directly into the Shift Register whenever an output is done to either the Upper or Lower Shift
Register Ports. A Status flag is also available to insure that data can be written to the port without an
underrun condition occuring.
Figure 6.0-4 illustrates serial output timing in the +1 mode. This mode can be used for either
asynchronous or synchronous data output. This figure illustrates timing relationships necessary to
insure correct serial data output.
When the output operation is begun, the data within the shift register is shifted one bit position tothe
right on the falling edge of the SHIFT CLOCK. SRO, the least significant bit of Port 7, is output first.
SR15, the most significant bit of Port 6, is output last. SR15 is output on the 16th SHIFT CLOCK
pulse(assuming 16 shifts per word was selected). While the shift register contents are being output
on a bit by bit basis, data is simultaneously sampled and input to the shift register through the SRIN
pin.
Output data is transferred from SRO to the output holding buffer when SHIFT CLOCK is low.
Therefore to insure valid output data on the SROUT pin for a full bit time, the lower shift register (Port
7) must be written to while SHIFT CLOCK is at a high level. This condition is present when both Bit
Counter Zero and SHIFT CLOCK are high. This can be verified by reading Bit 6 of Port 5, which is
called End of Word Sync. The above condition must be met in order to assure continuous error
free output data. If the Upper and Lower Shift Register Ports are both utilized and are loaded on
opposite sides of the rising edge of SHIFT CLOCK, an extra bit will either be added or dropped from
the output data stream.
111-269
SERIAL PORT TRANSMIT TIMING
Figure 6.0-4
SHIFT CLOCK
SERIAL OUT
BIT COUNTER ZERO
END-Of-WORD
SYNC
~
L
-----InL--_ _ _ _----Inl--_
For continous data output, the Shift Register must be loaded within 112 bit time of the End-of-Word
interrupt. For a 9600 bps output rate, this requires loading the Shift Register within 52
microseconds of the rising edge of SHIFT that signals the End-of-Word condition.
For noncontinuous data output, as is used in Asynchronous data transmission, the user must still
take the same precautions in loading the Shift Register to prevent an overrun or underrun condition
as described above. One method that can be used to insure valid data out isto use the End-of-word
interrupt in the transmit mode to signal the proper time to load the Shift Register. In using this
method, the transmit mode would be set and the Serial Interrupt would always be enabled, so the
the Serial Port would be continually shifting out data and interrupting at the specified word rate. This
would occur regardless of whether or not data had been loaded into the Shift Register. Recall that
while the Shift Register is in the Transmit Mode, the SRIN input is being sampled and shifted in. If,
for example, it is desirable to have the SROUT Line at a marking condition (logic 1) between
asynchronous serial words, then the user should insure that a logic one is present at the SRIN pin.
Another method for sending asynchronous serial data would be to specify edge trigger in a write
operation to the Serial Port Control register. This would reset the internal +16 counter, thereby
stopping the SHIFT clock. It would then be possible to load both halves of the Shift Register without
the possibility of an overrun or underrun condition. This would be followed by a second control word
specifying no Edge Trigger. This sequence will stop the output process, reload the Shift Register,
reset the +16 counter, and then re-enable the +16 counter and SHIFT clock.
111-270
7.0
INTERRUPTS
7.1
OVERVIEW
A total of three external interrupt inputs are provided in the MK3886. Two of these inputs are
uncommitted. the third is associated with Timer A. These inputs are edge triggered with Schmitt
trigger inputs that allow slow rise time signals to be tied directly to the interrupt request lines. Ti\ITf
will set an interrupt request latch on a negative edge transition whereas INT2 sets the latch on a
positive edge. INTO can be programmed to interrupt on either edge transition.
The Combo's interrupt control logic insures that it acts in accordance with Z80 system interrupt
protocol for nested priority interrupt and proper return from interrupt. The priority of any Z80
peripheral is determined by its physical location in a daisy chain configuration. Two signal lines (lEI
and lEO) are provided on the Combo and all
peripheral devices to form the system daisy chain.
The device closest to the CPU has the highest priority; within the Combo. interrupt priority has been
pre-determined for each interrupt source. The following is the internally assigned priority in
decreasing order:
zao
1. INTO
2. Timer A
3. Timer B
4. End of Word - Receive
5. End of Word - Transmit
6. INT1
7.INT2
Each ofthe interrupt channels on the 3886 can be individually enabled and each provides a unique
interrupt vector to the CPU. Additionally. a programmable mask register. accessed via Port 9. allows
the interrupt requests on each channel to be selectively blocked without disabling them.
7.2
PROGRAMMING THE INTERRUPTS
The Combo chip can be programmed to request a CPU interrupt every time its interrupt request latch
is set. Some time after the interrupt request. the CPU will respond with an interrupt acknowledge
and the MK3886 will determine the highest priority channel which is requesting an interrupt within
the device. Then if the MK3886's lEI input is active. indicating that it has priority within the system
daisy chain. it will put an 8-bit word on the system data bus.
The Combo cllip has been designed to operate in two different interrupt modes. These modes are
RESTART and VECTOR. RESTART mode is provided for use with 8080 CPU's or theZ80 in Mode O.
VECTOR is used with Interrupt Mode 2 of the
CPU.
zao
If the MK3886 is in the RESTART mode upon receipt of a interrupt acknowledge. the Combo Chip
forces a Z80 RESTART instruction on the data bus. The CPU strobes in RESTART and executes the
instruction from one of eight locations as defined by the T field in the RESTART instruction. The
RESTART locations are 0000. OOOSH ..... 0030H. The interrupt channel assignments specify which
restart location is executed. The channel aSSignments are encoded into the instruction field. The
RESTART vector is shown in the convention below.
RESTART
07
06
05
04
03
12
11
10
111-271
02
01
DO
Where:
Z80 Mnemonic
12
11
10
SOURCE
RST56
RST48
RST40
RST32
RST24
RST 16
RST08
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INTO
Timer A
Timer B
End of Word Receive
End of Word Transmit
INT1
INT2
RESTART
LOCATION
38H
30H
28H
20H
18 H
10 H
08H
The VECTOR mode is a more powerful method of servicing interrupts. When an interrupt request
has been acknowledged and the Combo's lEI input is active, indicating it has priority within the
system daisy chain, it will place an 8-bit interrupt vector on the system data bus. This interrupt vector
is used to form a pointer to a location in memory where the address of the interrupt service routine is
stored. The interrupt vector has the following format.
VECTOR
07
06
05
04
03
02
01
DO
V7
V6
V5
V4
12
11
10
o
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
-
-
-
INTO
Timer A
Timer B
E.O.W. Receive
E.O.W. Transmit
INT 1
INT2
The high-order 4 bits of the vector, V7 through V4, are program selectable and are stored in upper
bits of Port 8. They should be written to the Combo Chip as part of the initialization process. The next
three bits will be provided by the Combo's internal control logic as a binary code corresponding tothe
highest priority channel requesting an interrupt; finally the low-order bit of the VECTOR will always
be zero.
The VECTOR represents the least significant 8 bits of a 16 bit interrupt vector. The most significant 8
bits are supplied by the I register within theZ80-CPU. This 16 bit vector points to an interrupt service
routine starting address table. Thus in Mode 2, a single 8-bit vector stored in an interrupting
MK3886 can result in an indirect call to any memory location.
'MODE 2 INTERRUPT OPERATION
Desired starting address pointed to by:
INTERRUPT
SERVICE
ROUTINE
STARTING
ADDRESS
TABLE
LOW ORDER
HIGH ORDER
I REG
CONTENTS
7 BITS FROM
MK3886
J11-272
7-3.
LOAOING THE INTERRUPT CONTROL ANO VECTOR REGISTER
Before an interrupt sequence can begin, the Combo Chip must be programmed to initialize the
desired response. Programming is done through two registers, the Interrupt Control and Vector
Register and the Interrupt Mask Register. Port 8 is designated as the Interrupt Control and Vector
register. The purpose of this register is to store the high order 4 bits of the Interrupt Vector and to
provide interrupt control information. Port 9 is designated as the Interrupt Mask Register. The
purpose of this register is to selectively block interrupting channels without disabling them.
Port 8 is the Interrupt Control Vector Register. To load this register, the CPU performs a normal 1/0
write sequence to the port address. This Port is WRITE only. The following diagram shows the
position of each bit in the Interrupt Control and Vector Register.
07
06
05
04
V7
V6
V5
V4
02
03
RESTART
-----VECTOR
INn
ENABLE
01
INT2
ENABLE
00
X
PORT 8
Bits 07-04
These bits represent the high order four bits of the Interrupt Vector. When combined with the
internal channel assignments, a complete 8 bit vector is specified.
Bit 03 Mode Select
When set the MK3886 will operate in the RESTART mode. This mode is directly compatible with the
aoaoA or Z80 Mode O.
When cleared, the MK3886 will operate in vectored interrupt mode (zao mode 2).
Bits 02-01
These bits are used to selectively enable or disable the two external interrupt inputs, INT1 and INT2.
When set, they will generate an interrupt request sequence every time the inputs become active (if
the appropriate mask bit is enabled).
Interrupt Mask Register
Port 9 is the Interrupt Mask Register. This register allows a mask word to be written to the port that
will selectively allow certain channels to interrupt the CPU. This will block the interrupts but will not
disable them. This operation can be thought of as a 2-input ANO gate. One input of the gate is the
mask bit while the other input is the latched interrupt active signal. The mask bit, therefore,
determines whether the channel interrupt will be further processed and prioritized within the 3886.
Any channel of the 3886 can be prevented from requesting an interrupt by loading a logic 0 in the
respective bit poSition. The Port assignments are shown below.
INTERRUPT MASK REGISTER
07
06
05
04
03
02
01
INT2
111-273
00
If an interrupt request has been made, andthe respective mask bit disabled it will be passed on to the
CPU interrupt circuitry when the mask bit is enabled. If this previous interrupt is not desired but
future interrupts needed, the appropriate interrupt enable bit must be disabled, then set again. This
is done using the respective interrupt enable bits designated in the specific channel's control
register.
7.4
INTERRUPT ACKNOWLEDGE CYCLE
Figure 7.0-1 illustrates the timing associated with the Interrupt Acknowledge Cycle. Some time after
an interrupt is requested by the Combo, the CPU will send out an interrupt acknowledge (M1 and
lORa). To insure that the daisy chain enable lines stabilize, channels are inhibited from changing
their interrupt request status when M1 is active. M1 is active about two cf> clock cycles earlier than
lORa, and RD is false to distinguish the cycle from an instruction fetch. During this time the interrupt
logic of the Combo will determine the highest priority interrupting channel within the Combo places
its Interrupt Vector onto the Data Bus when lORa goes active. Two wait states (TW*) are
automatically inserted by the CPU at this time to allow the daisy chain to stabilize. Additional wait
states may be added.
INTERRUPT ACKNOWLEDGE CYCLE
Figure 7.0-1
CPU CLOCK
\~----------------~/
\'--_ _-oJ!
RD "1"
lEI
DATA
7.5
------ -------7
-"- - - - - - - - - - - - -
_______________-«
VECTOR
)~_ _ _ __
RETURN FROM INTERRUPT CYCLE
zao
Unlike the other
peripheral circuits, the MK3886 will not respond to the Z80 RETI command.
This is due to the manner in which the lEO line in the daisy chain is manipulated by the 3886. The
standard Z80 daisy chain protocol dictates that the closest device to the CPU has the highest priority.
This priority is determined by the lEI and lEO Signals. If a peripheral is granted an interrupt
acknowledge, it will force lEO low thus blocking all other lower priority devices. The lEO line will stay
low until the interrupt service routine is executed and the CPU issues the two byte RETI code. If lEI is
high and lEO is low, the peripheral will decode the RETI instruction. The peripheral being serviced
will be reinitialized and its lEO will become active (assuming no other pending interrupts by that
device).
Operation with the MK3886 is slightly different. After an interrupt has been acknowledged and an
8-bitword gated onto the data bus by the MK3886, the lEO line will go back high unless another
channel of the Combo is requesting an interrupt. Therefore it is now possible for lower priority
peripheral circuits to interrupt the CPU. If a Combo interrupt occurred while a lower priority
peripheral device was being serviced, a potential conflict could arise if an RETI was to terminate the
111-274
RETURN FROM INTERRUPT CYCLE
Figure 7.0-2
\ _________f
\ ____~f
00- 0 7
lEI
--------~~~----------------~~~------------------
--- - - - - - ,r-------------------
---------'
Combo's Interrupt Service Routine. Since the lEO line of the 3886 was brought high after the
interrupt acknowledge. an RETI instruction issued by the CPU would be decoded and executed by
the lower priority peripheral device. Therefore an RET command is the correct method of exiting a
Combo Interrupt Service Routine."
"Rev "c" ofthe MK3886 should be placed at the end of the daisy chain. otherwise other peripheral
devices in the daisy chain might not decode the RETI instruction.
111-275
111-276
8.0
COMBO PROGRAMMING SUMMARY
The following is a summary of the programmable ports on the MK3886. It is provided for use as quick
reference and review of the port channel assignments. Detailed information on programming is provided in
the appropriate sections on channel operation (e.g. Timers, Serial Port, etc.)
The most significant digit, 07, is on the far left and least significant digit, DO, on the far right ofthe register
representation. An X indicates an unused bit position.
Port 0 - Timer A Control - Write Only
1+ 20
7
1+5
1+2
6
5
Event Counter Mode __ O
+2 Prescale
--0
+5 Prescale
-0
..-0
+10 Prescale
_1
+20 Prescale
_1
+40 Prescale
4-1
+100 Prescale
_1
+200 Prescale
4
0
0
1
1
0
0
1
1
3
2
0 ...
1
Bit No.
~Start/StopT;~
0
1
0
1
0
1
0
1
I
: Pulse Width/Interval Timer
INTO Active Level
INTO External Interrupt Enable
'Timer A Interrupt Enable
Port 1 - Timer A Time Constant Register - Write Only
TC7
TC6
TC5
TC4
TC3
TC2
TCl
7
6
5
4
3
2
o _ B i t No.
2
o ~BitNo.
TCO
PORT 1 - Timer A Down Counter - Re!'ld Only
7
6
5
4
3
PORT 2 - Timer B Control - Write Only
PSI
PSO
X
X
7
6
5
4
3
2
X
X
1
0 -
Bit No.
I
+2 Prescale - 0 0
+5 Prescale - 0 1
+10 Prescale -1 0
+20 Prescale - 1 1
L T i m e r B Interrupt Enable
.....--------StartIStop Timer B
PORT 3 - Timer B Counter - ReadIWrite
7
6
5
4
3
2
O-+----Bit No.
PORT 4 - Timer B Time Constant Register - Write Only
TC7
TC6
7
6
TC5
5
TC4
TC3
TC2
4
3
2
111-277
TC1
TCO
O-BitNo.
PORT 5 - Serial Port Control - Write Only
I
7
5
6
+1/~~
~~I; ~~i~~er
•
X
4
N2
3
0
0
0
0
1
1
1
1
Serial Port •
Interrupt Enable
0
0
1
1
0
0
1
1
Shift Word
Length
NO
0
2
I
.
Nl
~
0
1
0
1
0
1
0
1
Bit No.
4
7
8
9
10
11
12
16
PORT 5 - Status - Read Only
X
7
I
6
5
I
, - - - I_
X
3
_
O~BitNo.
2
I __
L..~: ~1~i~:
_
----------------------_=
L...
'----------------------------+-
End-of-Word Sync
Bit Counter Zero
PORT 6 - Upper Shift Register - Read/Write
SR15
SR14
SR13
SR12
SRll
SR10
SR9
SR8
SR3
SR2
SRl
SRO
PORT 7 - Lower Shift Register - Read/Write
SR7
SR6
SR5
SR4
PORT 8 - Interrupt Control and Vector Register - Write Only
V7
V6
V5
V4
7
6
5
4
I
X
2
I
I
1
111-278
o ..-- Bit No.
If the Vector Mode is selected, the following interrupt vector is returned during the interrupt acknowledge
cycle.
V7
V6
V5
V4
12
11
6
5
4
I
3
2
1
1
1
1
0
0
0
1
0
0
1
1
0
7
v
Supplied from PORT 8
O~
o ..--BitNo.
10
0
0
0
0
0
0
0
1
0
1
0
1
0
1
- INT 0
- Timer A
- Timer B
- E.O.W. Receive
- E.O.W. Transmit
- INT 1
- INT2
If the restart mode is selected, a RESTART instruction is returned to the CPU during the interrupt
acknowledge cycle in the following format.
7
Where:
6
ZSO Mnemonic
RST56
RST48
RST40
RST32
RST24
RST 16
RST08
12
11
10
5
4
3
O..-BitNo.
2
RESTART
LOCATION
12
11
10
SOURCE
1
1
1
0
0
1
1
0
1
0
1
0
1
0
INTO
Timer A
Timer B
End of Word Receive
End of Word Transmit
INn
INT2
o
o
o
3SH
30H
2SH
20H
1SH
10H
OSH
PORT 9 - Interrupt Mask Register - Write Only
x
X
7
6
5
4
I
3
2
I
I~--------------
O"'-BitNo.
__~:~\~~l
I
1-------------------------....
: Timer A Interrupt
B Interrupt
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- Timer
111-279
Serial Port
Interrupts
PORT A - Write Protect - Write Only
WP7
WP6
WP5
WP4
WP3
WP2
WP1
WPO
Write one byte: 55H
Write Uninhibited: 66H
Write Inhibit: Any value except 55H or 66H
All registers are cleared when RESET occurs.
The following is a list in descending order of the priority of each interrupting channel. The highest priority is first
1.INTO
2. TIMER A
3. TIMER B
4. End of Word - Receive
5. End of Word - Transmit
6.INT 1
7.INT2
111-280
9.0
APPLICATIONS
The MK3886 has been designed to function in a variety of ways utilizing the power and flexibility of the
functions on chip. The following sections illustrate hardware and software applications of this component.
9.1
MINIMUM SYSTEM
Figure 9.0-1 illustrates a minimum Z80 system configuration. Four basic components are needed:
the Oscillator, Z80 CPU, PROM or ROM, and the MK3886 Combo Chip. Since the Z80 CPU only
requires a single 5-volt supply, most small systems can be implemented only using a single supply.
Note that a powerful system can be implemented using only 3 LSI circuits, an oscillator, and a single
5-volt power supply.
This system configuration has 2K x 8 of ROM and 256 bytes of RAM. For this example, address bit
A 11 separates the ROM space from the RAM space so that it can be used for the chip select
function. For larger amounts of external ROM or RAM, a simple TIL decoder would be required to
form the chip selects. This memory configuration provides adequate storage space for programs
plus providing space to allow scratch pad data storage and implementation of a "stack."
The system also has the Timer, Serial 1/0 and Interrupt capability of the Combo chip to allow an
interface to an outside device. If additional parallel 1/0 were desired, TIL circuits could be added to
accomplish this function. Input data could be gated onto the data bus using any standard tri-state
driver while the output data could be latched with any type of standard TIL latch. As another
alternative, Z80-P10 could be used to provide 1/0 capable of operating in an input only, output only,
bidirectional or bit control mode.
MINIMUM Z80 SYSTEM
Figure 9.0-1
I I
~
+6VOLT
OWERSUPPL
ose
~
~
ADDRESS BUS
~~"\. "\.
MREO
WR
~
l80
+5
~AO'AIO
"\. "\."-"\..."\. '
] CE1
RD
MK3880·
"
1~
MK34000
16K BIT ROM
DATA BUS{)
~
CPU
+5
.~'\.
MREO
leA
-RD
,'\.'\.
-
SRCLK
-MI
MI
t
leB
WR
-lORa
lORa
t RESE~
~
GND
A4
SRIN
SROUT
CSI/0
~
CSM
MK3886
COMBO
AO·A7
J
TIMER A
TIMER B
SERIAL PORT
n
EXTERNAL INTERRUPTS
MEMORY MAP
ADDRESS
0000
.2K BYTES
ROM
.1.
t - - - - - - I 07AA
256 BYTES
RAM
iiiiT
RST _ _
0800
08FF
111-281
lT1K
lEO
9,2
WRITE PROTECT
The lowest 64 bytes in the Combo's RAM are write protected, Three modes are available for
dynamically configuring the write protect circuit. The configuration is done by writing to Port A, the
Write Protect Port, These modes are Read Only, ReadIWrite and ReadIWrite one byte,
Upon power up or whenever a RESET occurs, the 64 bytes of RAM are in Read Only mode, Any
attempt to Write to this portion of RAM will be inhibited within the MK3886. No error indication will
be reported. The status ofthe Write Inhibit circuit can be determined by examining the RAM Protect
bit in Port 5, the status Register. To examine this po'rt, an input and bit test is required, If Bit5 is set,
write protection is enabled, if cleared it is disabled and normal Read/Write operations can continue.
A typical sequence would be as follows:
IN
BIT
JR
A(5)
5,A
NZ,INH
;Input Status Register
;Test Bit 5
;Branch if Write Inhibited
;Continue Processing if ReadIWrite
If the Write Protect circuit is enabled and it needs to be disabled for normal ReadIWrite operations;
the following sequence would be used.
LD
OUT
A 66H
(OAH),A
;Output Hex '66'
;for ReadIWrite
If only 1 byte is to be written to the memory the following sequence would be used:
LD
LD
OUT
LD
EI
C,OAH
B,55H
(C),B
(ADDR),A
;Specify Port to
;Write one Byte
;Set Control Word
;Write one byte to RAM
;Re-enable Interrupts
This sequence directs the RAM to write 1 byte and then re-enable the Write Protect circuitry. The
control word to request this function is '55'H.
The interrupts are disabled in order to prevent any other write cycles from interrupt subroutines
occurring before the Write operation to the RAM. In the example above, the contents of the
Accumulator is written to the RAM memory. Also note that a 16 bit load instruction will not execute
properly. An example ofthis would be ifthe LD (ADDR), A instruction was replaced with LD (ADDR),
HL. The contents of the L register would be correctly loaded into ADDR but the H register would not
be loaded into ADDR =1 since the write circuitry would now be inhibited for the second write
operation.
In order to enable the write protection circuit any value except 55H and 66H should be written tothe
Write Protect Port. For this example all zeros are used. The sequence would be as follows:
LD
OUT
9,3
AO
(OAH).A
;clear accumulator
;Enable Write Protect Circuitry
INTERRUPT CONTROLLER
Three lines on the MK3886 are used to generate prioritized, vectored, maskable, edge triggered,
edge selectable(INTO only), external inputs. The following example illustrates the steps necessary to
set up theZ80 CPU to handle Mode 2 interrupts from this device. The memory map for the example
is shown in Figure 9.0-2.
111-282
MEMORY MAP
Figure 9.0-2
STACK
T
0900
}
OOM'O_
0800
.r-
INT2
0600
INTERRUPT
SERVICE
ROUTINE
AREA
INT 1
0500
INTO
0400
-
i-
The start bit must always be low. It lasts for 1 bit time and is used to indicate the beginning of a
character. The data bits are the actual data character transferred. In this example the character is 8
bits long with the least significant bit being sent out or received first. After the data bits have been
transmitted, 2 stop bits are sent.
In order to output asynchronous data, the following steps must be taken.
1. Load the start, data, and stop bits into the output port.
2. Start the shift register
3. Stop after receiving end-of-word transmit to reload more data + start bits
111-283
+ stop bits.
The followinl;j is an example routine to execute this task.
SELECT
;ALT. REGS.
;POINT TO DATA
;NUMBER OF BYTES
;MAINREGS.
;SERIAL INT.
;NOTMASKED
;INITIALIZE
;SERIAL PORT
;SEND 1st CHAR.
INIT
EXX
LDHL,DATA
LDB, NUMBER
EXX
LDA,40H
OUT (9),A
LDAADH
OUT (5),A
CALLXMIT
ASSUMED: Interrupt mode, Interrupt vector, Baud rate clock, etc. already initialized.
INTERRUPT
BACK EX AF.AF
EXX
EI
RET
;RESTORE MAIN
;REGISTER SET
;ENABLE INT.
;BACK TO MAIN
ASSUMED: B'contains # of bytes to be transferred
HC' points to bytes to be transferred
Part is programmed in asynchronous serial transmit mode
The following program will allow the MK3886 to operate in asynchronous receive mode. It is
assumedthatthe incoming character will consist of 8 bits per word and have two stop bits. However,
a programming shortcut is used in this example to facilitate a more efficient algorithm.
The algorithm assumes that ifthe edge detect circuit begins correctly then a valid incoming message
was being receivEid. Using this assumption, then only 9 shifts per word are required. Shifting in the
final 2 stop bits are meaningless since the MK3886 resynchronizes its edge detect circuits
automatically whenever an end-of-word interrupt occurs. Therefore, upon the End-of-Word
interrupt, the 8 bits of data are in the upper shift register and the start bit is in the most significant bit
of the lower shift register. The data can be input directly to the CPU from the upper shift register and
the start bit in the lower shift register simply ignored.
The following is an example of implementation of the asynchronous receive operation.
INIT
EXX
LD B,NUMBER
LD HL,DATA
EXX
LDA,2BH
OUT (5).A
;SELECT ALT. REGS.
;NUMBER OF BYTES
;POINT TO STORAGE
;RESTORE MAIN REGIS.
;RX. MODE, :16CK,
;EDGE TRIG., INT. ENABLE
;9 SHIFTS/wORD
The data can be input directly to the CPU from the upper shift register and the start bit in the lower
shift register simply ignored.
111-284
The following is an example of implementation of the asynchronous receive operation.
INT
EXX
;SELECT ALT.
LD B,NUMBER
;NUMBER OF BYTES
LD HL,DATA
;POINTTO STORAGE
EXX
;RESTORE MAIN REGIS.
LD A,2BH
;RX. MODE, :16 CK,
OUT (5),A
;EDGE TRIG., INT. ENABLE
;9 SHIFTS/wORD
RXINT
BACK
CPEX 1
EX AF,AF'
EXX
INA,(6)
LD(HL)A
INCHL
DJNZ BACK-$
LDA,23H
OUT (5),A
EX AF,AF'
EXX
EI
REI
;SELECT ALTERNATE
;REGISTER SET
;READ DATA WORD
;STOREWORD
;BUMP POINTER
;RETURN IF B NOT 0
;ELSE DISABLE
;RECEIVER
;RESTORE MAIN
;REGISTER SET
;ENABLE INTERRUPT
;BACK TO MAIN
01
1M2
LD HL,CRAM+255
LD SP,HL
LD HL,IVT
LDA,H
LDI,A
LDA,L
;DISABLE INTERRUPTS
;SELECT Z80 MODE 2 INTERRUPT
;ESTABLISH STACK
;AT TOP OF COMBO RAM
;FETCH TABLE START ADDR.
;SET UPPER 8 BITS
;OF INT. VECT. TABLE
;SET LOWER 8 BITS
111-285
The ZOO software routine will perform the following functions in this example:
(1) Select the Vector Interrupt Mode
(2) Establish the Stack at location 'FFFF'H
(3) Create the interrupt vector by loading the I and V registers in CPU and Combo respectively
(4) Enable INT 0 - 3 interrupt enable and mask register
(5) Specify the starting address of each INT service routine at each interrupt vector.
(6) Enable system interrupts
The following routine will perform the above tasks tne ready the Z80 CPU for interrupt from the
MK3886. Remember that an RET, not an RETI, is the correct instruction to be executed upon
completion of an interrupt service routine.
MOSTEK MACRO-SO ASSEMBLER V2.2
LOC
OBJ.CODE
STMT-NR
1
SOURCE-STMT PASS2 CPEX1
NAME
CPEX1
; COMBO PROGRAMMING EXAMPLE
CPEX1
CPEX1
REL
; THIS ROUTINE ENABLES THE THREE EXTERNAL INTERRUPTS
; ON THE COMBO CHOP. ALL OTHER INTERRUPTS ARE LEFT
; DISABLED.
=0800
=0000
=0200
=0300
=0400
15
0100
0100
0102
0104
0106
OlOE
0004
0003
0002
0000
0000
0001
0003
0005
0007
OOOA
OOOB
0000
OOOF
0011
0013
0015
0017
0019
9
10
11
12
13
17
18
19
20
21
23
F3
ED5E
3E01
ED47
21FF08
F9
3E06
0306
3EOC
0300
3EOO
0302
0305
FB
25
26
27
28
29
30
31
32
33
34
35
36
37
38
; EaUATES
EaU
CRAM
CPORT
EaU
INTO
DEFL
INn
DEFL
INT2
DEFL
0800H
0
0
02100H
01200H
ORG
CRAM
; INTERRUPT VECTOR TABLE
IVT
DEFS
2
DEFW
INT2
DEFW
INT1
; INT1 VECTOR
DEFS
8
DEFW
INTO
ORG
0
; INITIALIZATION ROUTINE
01
1M
2
LD
A,01H
LD
I,A
LD
HL,CRAM+255
LD
SP,HL
LD
A,06
(CPORT +6),A
OUT
LD
A.OCH
OUT
(CPORT +O).A
LD
A,O
(CPORT +2).A
OUT
OUT
(CPORT +5).A
EI
111-2S6
; START OF COMBO RAM
; COMBO PORT MAP START ADDR.
; INTO SERVICE ROUTINE START
; INT1 SERVICE ROUTINE START
; INT2 SERVICE ROUTINE START
RESERVE FOR FUTURE VECTOR
; INT2 VECTOR
; RESERVE: OTHER COMBO VECT.
; INTO VECTOR
; DISABLE INTERRUPTS
; SELECT ZOO MODE 2 INTERRUPT
; SET UPPER 8 BITS
OF INTERRUPT VECTOR TABLE
; ESTABLISH STACK
AT TOP OF COMBO RAM
; LOAD VECTOR AND
ENABLE INT 1 + 2
; ENABLE INTO, ACT. LEV. = 1
; DISABLE
OTHER
COMBO INTERRUPTS
;ENAB
CPEX1
; INITIALIZATION ROUTINE
EI
1M
2
LD
HL.CRAM+255
LD
SP.HL
LD
HL.IVT
LD
A.H
I.A
LD
A.L
LD
OFOH
AND
OR
07H
(CPORT +8).A
OUT
LD
A.OCH
OUT
9.4
; DISABLE INTERRUPTS
; SELECT Z80 MODE INTERRUPTS
; ESTABLISH STACK
; AT TOP OF COMBO RAM
; FETCH TABLE START ADDR.
; SET UPPER 8 BITS
; OF INT. VECT. TABLE
; SET LOWER 8 BITS
; MASK LOWER 4 BITS
; SELECT VECTOR MODE. ENABLE INT 1 +2
; SET INT VECT + CTL REG
TIMER CONSTANTS FOR USE AS BAUD RATE GENERATOR
The ZCB output of Timer B can be used to generate square waves that can be utilized as the clock
input for the serial port. The following table gives a list of prescale values and time constant values
for Timer B necessary to generate the correct frequencies for standard baud rates. The data are
tabulated for use in the +16 modes by the serial port. These calculations are based upon a clock
frequency of 2.458 MHz. This frequency was selected since it is a multiple of many baud rate
frequencies as well as being close to the maximum frequency for the standard 2.5 MHzZ80 chip set.
The period of clock was determined by using the following formula for the ACB output period:
2 * P* tc * TC
Where P is the Prescale factor. tc is the period of the Timer clock TCLK. TC is the Timer B Time
Constant data word loaded in Port 4. and 2 is a constant to adjust for the toggle output feature on
ZCB.
BAUD RATE
110
300
600
1200
2400
4800
9600
9.5
PRESCALE
5
2
2
2
2
2
2
TIME CONSTANT
139
128
64
32
16
8
4
ACTUAL
BAUD RATE
CLOCK FREO.
1769
4801
9602
19203
38406
76813
153625
DESIRED
BAUD RATE
CLOCKFREO.
1760
4800
9600
19200
38400
76800
153600
TIMER B AS A VARIABLE PULSE WIDTH TIMER
Timer B can be used ~o produce asymetrical square wave outputs. Using Port 4. the Timer B Time
Constant Register. a pulse train of variable pulse widths and interpulse intervals can be established.
This simply requires reloading the time constant register with alternating values on each occurance
that Timer B counts to zero. For example. consider a system using a 2.5MHz Time Clock. A
continuing pulse train with a 1 millisecond pulse width and a 2 millisecond interpulse interval is
desired. To obtain this output. the Prescaler would be loaded to divide by 20 and the Time Constant
Register alternately loaded with 125 and 250. An example of this program is illustrated below:
The program is divided into two parts: Initialization and Interrupt Service Routine. The Initialization
routine assl.lfmlS that the interrupt vector location was programmed and the stack area has been
established. Basically this routine sets up the Timer. conditions theZCB output. and starts the timer.
The interrupt service routine tests to see if 125 or 250 was last loaded into the Timer Constant
Register. The alternate value is then loaded into that register and then the subroutine is exited.
111-287
CPEX2
; INITIALIZATION
01
1M2
LD HL,IVT
LDA,H
LD I,A
LDA,L
OUT (CPORT +8),A
LD HL,CRAM+255
LD SP,HL
LD A,O
OUT (CPORT +O),A
OUT (CPORT +5),A
LD A,010H
OUT (CPORT +9),A
LDA,T1
OUT (CPORT +),A
LD A,OCl -I
OUT (CPORT +2),A
LD A,T2
OUT (CPORT +4),A
LD (TCVAL),A
LOC OBJ. CODE
7
=0000'
8
9
0400
10
0400'
12
13
0100
0102
010A
010C
17
18
19
20
0002'
0000
0000
0001
0003
0005
0007
oooA
oooB
0000
22
F3
ED5E
3E01
EP47
21FF04
F9
3E08
0308
; DISABLE TIMER A & INTO
; DISABLE SERIAL PORT
; UNMASK TIM. B, MASK REST
; START T1 HIGH PULSE,ZCB=1
; TIM. B ENABLE, PRESCALE=20
; LOAD NEXT TC FOR LOW PULSE
; SAVE NEXT TC
MOSTEK MACRO-80 ASSEMBLER V2.2
STMT-NR SOURCE-STMT PASS2 CPEX2 CPEX2 CPEX2 REL
1
NAME
CPEX2
; COMBO PROGRAMMING EXAMPLE
; THIS ROUTINE PROGRAMS TIMER B AS AN ASYMETRICAL
; PULSE GENERATOR. ALL OTHER INTERRUPTS ARE DISABLED.
=0400
=0070
=OOFA
; DISABLE INTERRUPTS
; Z80 MODE 2 INTERRUPT
; FETCH TABLE START ADDR
; SET UPPER 8 BITS
; OF INTERRUPT VECTOR TABLE
; SET LOWER 8 BITS &
; DISABLE INT1 & 2
; ESTABLISH STACK
; AT TOP OF COMBO RAM
24
25
26
27
28
29
30
31
; EQUATES
CRAM
EQU
CPORT
EQU
T1
EQU
T2
EQU
ORG
0800H
o
125
250
; START ADDR. OF COMBO RAM
; START ADDR. OF COMBO PORTS
; TC FOR HIGH T1 = 1 MS.
; TC FOR LOWT2 = 2 MS
CRAM
1
; INTERRUPT VECTOR TABLE
IVT
DEFS
2
DEFS
8
DEFW
TBI
4
DEFS
TCVAL
DEFS
1
ORG
0
; INITIALIZATION
EI
2
1M
HA,01
LD
I,A
LD
HL,CRAM+255
LD
SP,HL
LD
LD
A,08H
OUT
(CPORT +8),A
111-288
; RESERVE FOR FUTURE VECTOR
; RESERVE; OTHER COMBO VECT.
; TIMER B INT. START ADDR.
; RESERVE: OTHER COMBO VECT.
; CURRENT TIME CONSTANTVAC.
; DISABLE INTERRUPTS
; ZOO MODE 2 INTERRUPT
; SET UPPER 8 BITS
; OF INT. VECTOR TABLE
; ESTABLISH STACK
; AT TOP OF COMBO RAM
; SET INTERRUPT VECTOR &
; DISABLE INT1 & 2
OOOF
0011
0013
0015
0017
001F
0021
0023
0025
3EOO
D300
D305
3E10
D309
D302
3EFA
D304
FB
LD
OUT
OUT
LD
OUT
OUT
LD
OUT
EI
32
33
34
35
36
40
41
42
43
A,O
(CPORT +OI,A
(CPORT +51,A
A,010H
(CPORT +91,A
(CPORT +21.A
A,T2
(CPORT +41,A
; DISABLE TIMER A & INTO
; DISABLE SERIAL PORT
; UNMASK TIM. B, MASK REST
; TIM. B ENABLE, PRESCALE 20
; LOAD TC FOR LOW PULSE LENGTH
MOSTEK MACRO-SO ASSEMBLER V2.2
LOC
OBJ. CODE
48
0200
0200'
0201
0202
0205
0207
0208
020A
020A
02OC'
020E
0211
0212
0213
0214
STMT-NR SOURCE-STMT
F5
E5
210004'
3E7D
BE
2002
3EFA
3EFA
D304
320004'
F1
E1
FB
C9
50
51
52
53
54
55
36
36
57
58
59
60
61
62
PASS2 CPEX2 CPEX2
CPEX2 REL
ORG
020H
; TIMER B INTERRUPT SERVICE ROUTINE
TBI
PUSH
AF
; SAVE ACCUMULATOR, FLAGS
PUSH
HL
; SAVE HL REGISTER PAIR
LD
HL,TCVAL
; POINT TO CURRENT TC VALUE
LD
A.T1
; GETT1 VALUE
CP
(HLI
; COMPARE TO TC VALUE
NZ,TBI1-$
; IF NOT =, LOAD T1 INTO TC
JR
LD
A,T2
; OTHERWISE LOAD T2 INTO TC
LD
A,T2
; OTHERWISE LOAD T2 INTO TC
TBI1
OUT
(CPORT +41,A
; LOAD TIME CONSTANT
LD
(TCVALI,A
; STORE CURRENT TC IN BUFFER
POP
AF
; RESTORE
POP
HL
CPU REGISTERS
EI
; ENABLE INTERRUPTS
RET
; RETURN
111-2S9
9.6.
SERIAL ASYNCHRONOUS 1/0
The MK3886 is capable of half duplex serial asynchronous transmission and reception. Since this
port functions basically as a serial to parallel and parallel to serial converter, some software is
needed to add or strip the start and stop bits and to align the data word. The following example
illustrates a program sequence necessary to output an 8-bitASCIl word. It is assumed that the input
clock frequency has been generated and is input at SRCLK. An 8-bit asynchronous data word has
the following format.
The start bit must always be low. It lasts for 1 bit time and is used to indicate the beginning of a
character. The data bits are the actual data character transferred. In this example the character is8
bits long with the least significant bit being sent out or received first. After the data bits have been
transmitted, a stop bit is sent. During this period the stop bits are high for 1 or 2-bit times allowing for
both the transmit and receive terminals to asynchronize.
In order to output asynchronous data, the following steps must be taken.
1. Load the start, data and stop bits into the output port.
2. Start the shift register
3. Stop after receiving end-of-word transmit to reload more data
The following is an example routine to execute this task.
INIT
EXX
LD HL,DATA
LD B, NUMBER
EXX
LDA,40H
OUT (9),A
LDA,4DH
OUT (5),A
CALLXMIT
SELECT
;ALT. REGS.
;POINTTO DATA
;NUMBER OF BYTES
;MAIN REGS.
;SERIAL INT.
;NOTMASKED
;INITIALIZE
;SERIAL PORT
;SEND 1st CHAR.
ASSUMED: Interrupt mode, Interrupt vector, Baud rate clock, etc. already initialized.
IN'fERRUPT
XMIT EX AF,AF
EXX
LDA,(HL)
SLAA
OUT (7),A
LDA,OFFH
RLA
OUT (6),A
INCHL
DJNZ BACK-$
LDA,25H
OUT (5),A
;SELECT ALT.
;REGISTERS
;GETDATA
;MAKE START BIT
;OUT TO S.R. LO
;MAKE STOP BITS
;RESTORE DATA M.S.B.
;OUT TO S.R. HI
;BUMP POINTER
;JUMP IF MORE DATA
;ELSE DISABLE
;TRANSMITIER
BAC, EX AF,AF
;RESTORE MAIN
;REGISTER SET
;ENABLE INT.
;BACK TO MAIN
EXX
EI
RET
111-290
ASSUMED: B' contains # of bytes to be transferred
HL' points to bytes to be transferred
Part is programmed in asynchronous serial transmit mode
The following program will allow the 3886 to operate in asynchronous receive mode. It is assumed
that the incoming character will consist of 8 bits per word and have two stop bits. However, a
programming shortcut is used in this example to facilitate a more efficient algorithm .
.The algorithm assumes that ifthe edge detect circuit begins correctly then a valid incoming message
was being received. Using this assumption, then only 9 shifts per word are required. Shifting in the
final 2 stop bits are meaning less since the 3886 resynchronizes its edge detect circuits
automatically whenever an end-of-word interrupts occurs. Therefore, upon the End-of-Word
interrupt, the 8 bits of data are in the upper shift register and the start bit is in the most significant bit
ofthe lower shift register. The data can be input directly to the CPU from the upper shift register and
the start bit in the lower shift register simply ignored.
The following is an example of implementation of the asynchronous receive operation.
INIT
EXX
LD B,NUMBER
LD HL,DATA
EXX
LDA,2BH
OUT (5).A
;SELECT ALT. REGS.
;NUMBER OF BYTES
;POINT TO STORAGE
;RESTORE MAIN REGIS.
;RX. MODE, :16 CK,
;EDGE TRIG., INT. ENABLE
;9 SHIFTS/WORD
RXINT
EXXAF,AF'
EXX
INA,(6)
LD(HL),A
INC HL
DJNZ BACK-$
LDA,23H
OUT (5).A
EXAF,AF'
;SELECT ALTERNATE
;REGISTER SET
;READ DATA WORD
;STOREWORD
;BUMP POINTER
;RETURN IF B NOT 0
;ELSE DISABLE
;RECEIVER
;REGISTER MAIN
;REGISTER SET
;ENABLE INTERRUPT
;BACK TO MAIN
BACK
EXX
EI
RET
111-291
111-292
10.0 ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ..•.........•....••......••....•...•.•..•••• Specified Operating Range
Storage Temperature .•...•........••..•••..•....••....•....•...••.•••...•.• -65°C to + 150°C
Voltage on Any Pin With Respect to Ground. . . . . . . . . . . . . . . . . . • . . . . . . . • . . . • • • . . . • •. -O.3V to + 7V
Power Dissipation ••....•.•.............•.•..•.....••.................•.....••.••.•.•.• 0.8W
10.1 D.C. CHARACTERISTICS
TA = O°C to 70°C. VCC = 5V ± 5% unless otherwise specified
SYM
PARAMETERS
MIN
MAX
UNIT
TEST CONDITION
VILC
VIHC
VIL
VIH
VOL
VOH
ICC
III
ILOH
Clock Input Low Voltage
Clock Input High Voltage (1)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Tri-State Output Leakage
Current In Float
Tri-State Output Leakage
Current In Float
Standby VCC for RAM a
Standby Current
-0.3
2.2
-0.3
2.0
0.8
VCC'+.3
0.8
VCC
0.4
120
±10
10
V
V
V
V
V
V
mA
pA
pA
IOL = 2.0 mA
IOH = -250 pA
Outputs Open
VIN = OtoVCC
VOUT = 2.4 to VCC
-10
pA
VOUT =0.4V
5.5
6.0
3.7
V
mA
mA
VRAM = 5.5V
VRAM = 3.2V
MAX
UNIT
5
pF
ILOL
VSB
ISB
2.4
3.2
10.2 CAPACITANCE
SYM
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
10
pF
TEST CONDITION
Unmeasured Pins
Returned to Ground
*COMMENT
Stra..... above those listad under" Abooluta Maximum Rating" may causa permanent damage to the device. This i. a stress rating only and functional
operation of the device at thesa or any oth. condition above those indicated in the operational sections of this specification ia not implied. Expoaure to
absolute maximum rating conditions for extended periodl may affect device reliability.
111-293
LOAD CIRCUIT FOR OUTPUT
Figure 10.0-1
TEST POINT
VCC
R1=2.1 KO
CR1
OUTPUT
UNDER ~--------------~------------~t-------------~C
TEST
C1
250 p.A
MEMORY READ TIMING
Figure 10.0-28
t--
~~~_VAUD
twiMRH}
tarm(D) - - -_ _~
DATA OUTPUT VALID
~---------
tacm(O) _ _ _ _ _ _ _-+1'--________________--'
111-294
MEMORY WRITE TIMING
Figure 10.0-2b
tw(MRH)
CSM
tsm(D)
0-0
7 0 ----------------------------
thm(D)
INPUT DATA VALID
1/0 READ TIMING
Figure 10.0-2c
ADDRVALID
CSIO
lORa
tacl(D)
tari(D)
~-~----------------------------
111-295
DATA OUTPUT VALID
-
110 WRITE TIMING
Figure 10.0-2d
AD DR VALID
lORa
twi(WR)
WR
tsi(D)
DATA VALID
SERIAL 1/0 TIMING
Figure 10.0-2f
\"---
SRCLK
SRIN
VALID
SROUT
111-296
INTERRUPT RESPONSE TIMING
Figure 10.0-2e
SRCLK
TCLK
INT 1.2
tOSRC(lTI
INT
MI
\
tSI(MII
IORQ
\
tOI(O)
OOUT
--------
----
- ---<
------
VALID
t.(IEI)
lEI
/
tOH(IO)
~
tOL(lO)
lEO
j
f-.tOMIIOI-
111-297
10.3 A.C. CHARACTERISTICS
TA = O°C to 70°C. V C = +5V ± 5V unless otherwise noted.
MK3886
MAX
MIN
MK3886-4
MIN
MAX
SIGNAL
SYMBOL
PARAMETER
A7-Ao
tSM(A)
Address Setup time to falling edge of
MREQ
Address Hold time from falling edge
ofMREO
Address Setup time to falling edge of
10RO'
Address Hold time from falling edge
of 10RO
100
45
n.s.
40
40
n.s.
100
45
n.s.
40
40
n.s.
CSMsetup time to falling edge of
MREO
CSM Hold time from falling edge of
MREO
85
40
n.s.
40
40
n.s.
tHM(A)
tSI(A)
tHI(A)
CS m
tSM(CSM)
tHM(CSM)
eslO
tSI(CSIO)
~ Setup time to falling edge of
85
50
n.s.
tHI(CSIO)
lOR
CSIO Hold time from falling edge of
10RO
40
40
n.s.
tACM(D)
tACI(D)
D7- DO
UNIT CONDITIONS
tARM(D)
tARI(D)
tSI(D)
tHI(D)
tSM(O)
tHM(D)
tDI(D)
tFlD)
tw~WR)
Data Output Delay from MREO
during memory read
Data Output Delay from 10RO during
I/O read
Data Output Delay from RD to data
valid during memory cycle
Data Output Delay from RD to data
valid during I/O cycle
Data Setup time to rising 10RO or
WR during I/O WRITE
Data hold time from rising 10RO or
WR during I/O WRITE
Data Setup time to rising MREO or
WR during memory ii'i7RlTl: .
Data hold time from rising MREO or
INR during memory 'WRITE
Data Output delay from falling 10RO
during interrupt acknowledge
Delay to float
350
220
n.s.
380
335
n.s.
200
200
n.s.
380
335
n.s.
265
265
n.s.
30
30
n.s.
200
110
n.s.
30
30
n.s.
340
340
110
n.s.
n.s.
WR pulse width low (I/O cycle)
WR pulse width low (Mem cycle)
250
100
250
100
n.s.
n.s.
tSI(M1)
M1 Setup time to falling IORO
during interrupt acknowledge
250
250
n.s.
lEI
tS(IEI)
Setup to falling 10RO DURING
interrupt acknowledge
200
140
n.S.
lEO
tDH(IO)
lEO Delay Time from rising edge of
lEI
lEO Delay Time from falling edge of
lEI
lEO Delay from falling edge of M1
(interrupt just prior to M1)
WR
twM(WR)
MI
tDLlIO)
tDM(IO)
111-298
Load=50pF +
1TIL Load
160
160
n.s.
130
130
n.s.
190
190
n.s.
Load=50pF +
1TIL Load
10.3 AC CHARACTERISTICS (continued)
MK3886
MK3:1J86-4
SIGNAL
SYMBOL
PARAMETER
MIN
MREO
tvv(MRL)
tvv(MRH)
Pulse Width. MREO Low
Pulse Width. MREO High
480
1S0
tDX(IT)
Delay to falling INT from external
interrupt active transition
Delay to INT from Timer Interrupt at
rising TCLK
Delay to INT from rising edge of
SRCLK
400
400
n.s.
600
600
n.s.
SOO
SOO
n.s.
P* tCLK - tCLKI2 - 100
INT
tDnlT)
tDSRC(IT)
MAX
MIN
MAX
UNIT CONDITIONS
300
ZCA
tWC(ZCA)
Width of ZCA pulse
SRCLK
tc(SR)
tS(SI)
3.3
250
3.3
250
n.s.
150
150
n.s.
tDSR(SRC)
Period of SRCLK
SRIN setup with respect to SRCLK
edge
SRIN hold time from SRCLK
(x1 mode)
Delay to SROUT from SRCLK
tc(TC)
Period of Timer Clock
400
tvv(TC)
Timer Clock Low time
180
tH(SI)
TCLK
2.5
j./S.
1.S
250
220
110
n.s.
n.s.
n.s.
140
n.s.
ORDERING INFORMATION
PART
NO.
DESIGNATOR
MK3886N
PACKAGE
TYPE
MAXIMUM CLOCK
FREQUENCY
TEMPERATURE
RANGE
Z80-COMBO
PLASTIC
2.5 MHz
0° to 70°C
MK3886P
Z80-COMBO
CERAMIC
2.5 MHz
0° to 70°C
MK3886J
Z80-COMBO
CERDIP
2.5 MHz
0° to 70°C
MK3886N-4
Z80-COMBO
PLASTIC
4.0 MHz
0° to 70°C
MK3886P-4
Z80-COMBO
CERAMIC
4.0 MHz
0° to 70°C
MK3886J-4
Z80-COMBO
CERDIP
4.0 MHz
0° to 70°C
111-299
1981
zao MICROCOMPUTER DATA BOOK
zao Family
Data Sheets
MOSTEI<.
zao
MICROCOMPUTER
Direct Memory Access Controller MK3883
FEATURES
o
o
Transfers, searches and search/transfers in byte-ata-time, burst or continuous modes. Cycle length and
edge timing can be programmed to match the speed
of any port.
Dual port addresses (source and destination)
generated for memory-to-I/O, memory-to-memory,
or I/O-to-I/O operations. Addresses may be fixed or
automatically incremented/decremented.
o
Next-operation loading without disturbing current
operations via buffered starting-address registers.
An entire previous sequence can be repeated
automatically.
o
Extensive programmability of functions. CPU can
read complete channel status.
o Standard Z80 Family bus-request and prioritized
interrupt-request daisy chains implemented without
external logic. Sophisticated, internally modifiable
interrupt vectoring.
o
Direct interfacing to system buses without external
logic.
GENERAL DESCRIPTION
The MK3883 Z80 DMA (Direct Memory Access) is a
powerful and versatile device for controlling and
processing transfers of data. Its basic function of
managing CPU-independent transfers between two
ports is augmented by an array of features that optimize
transfer speed and control with little or no external logic
in systems using an 8- or l6-bit data bus and a l6-bit
address bus.
PIN FUNCTIONS
PIN ASSIGNMENTS
Figure 1
Figure 2
ZSODMA
~{
Ao
A1
A2
A3
DATA
BUS
""
As
As
SYSTEM
ADDRESS
BUS
~
As
Ag
BUS
{
CONTROL
AID
CONTROL
BUS
}
GND
40Ae
2
39
A3
3
38 lEI
A2
4
37
A1
5
36 lEO
CLK
IV-l
iNT
Ao
6
35 DO
7
340,
Viii
8
3302
RO
9
32 03
3104
30 GNO
MiiEQ 12
2905
~13
28 08
BAI 14
27
BUSRQ 15
26
CE/WArr 16
INTERRUPT
CONTROL
A-t
CLK
+5V 11
}DMA
CONTROL
+5V
1
~
iOiiOl0
A"
AU
A13
A14
A15
~{
"&
0-,
M1
25 ROY
A16 17
A14 18
24
As
23
As
A 13 19
22 A'0
A12 20
21 All
Transfers can be done between any two ports (source
and destination), including memory-to-IIO, memory-tomemory, and I/O-to-I/O. Dual port addresses are
automatically generated for each transaction and may
be either fixed or incrementing/decrementing. In
addition, bit-maskable byte searches can be performed
either concurrently with transfers or as an operation in
itself.
The MK3883 Z80 DMA contains direct interfacing to
and independent control of system buses, as well as
sophisticated bus and interrupt controls. Many programmable features, including variable cycle timing and
auto-restart minimize CPU software overhead. They are
especially useful in adapting this special-purpose
transfer processor to a broad variety of memory, I/O and
CPU environments.
FUNCTIONAL DESCRIPTION
Classes of Operation
The MK3883 Z80 DMA has three basic classes of
operation:
• Transfers of data between two ports (memory or I/O
peripheral)
• Searches for a particular 8-bit maskable byte/at a
single port in memory or an I/O peripheral
• Combined transfers with simultaneous search
between two ports
Figure 4 illustrates the basic functions served by these
classes of operation.
BASIC FUNCTIONS OF THE Z80 DMA
Figure 4
The MK3883 Z80 DMA is an n-channel silicon-gate
depletion-load device packaged in a 40-pin plastic,
ceramic DIP, or CERDIP. It uses a single +5V power
supply and the standard Z80 Family single-phase clock.
Z800MA
I/O
PERIPHERAL
Z80 ENVIRONMENT WriH MULTIPLE DMA
CONTROLLERS
Figure 3
I/O
PERIPHERAL
I..--f-~~
SYSTEM
BUSES
1.
2.
3.
4.
5.
PRIORITY 2
A
"
,. +5
I'
Search memory
Transfer memory·to-memory (optional .....""')
Transfer memory·to-I/O (optional .....!Ch)
Search 1/0
Transfer I/O-to-I/O (optional .....""')
OMA
INT
r
ROY
lEI
1-
TNT
I
During a transfer, the DMA assumes control of the
system control. address. and data buses. Data is read
from one addressable port and written to the other
addressable port, byte by byte. The ports may be
programmed to be either system main memory or
peripheral 110 devices. Thus, a block of data may be
written from one peripheral to another, from one area of
main memory to another, or from a peripheral to main
memory and vice versa.
During a search-only operation, data is read from the
source port and compared byte by byte with DMAinternal register containing a programmable match
byte. This match byte may optionally be masked so that
only certain bits within the match byte are compared.
Search rates up to 1.25M bytes per second can be
obtained with the 2.5MHz MK3883 Z80 DMA or 2M
bytes per second with the 4MHz MK3883-4 Z80 DMA.
lEO
lEI
~
PRIORITY 1
ROY
SIO
A
,.
~
OMA
In combined searches and transfers, data is transferred
between two ports while simultaneously searching for a
bit-maskable byte match.
r
Data transfers or searches can be programmed to stop
or interrupt under various conditions. In addition, CPUreadable status bits can be programmed to reflect the
condition.
IV-2
Modes of Operation
Variable Cycle
The MK3aa3 zao DMA can be programmed to operate
in one of three transfer andlor search modes:
The zao DMA has the unique feature of programmable
operation-cycle length. This is valuable in tailoring the
DMA to the particular requirements of other system
components (fast or slow) and maximizes the datatransfer rate. It also eliminates external logic for signal
conditioning.
• Byte-at-a-time: data operations are performed one
byte at a time. Between each byte operation the
system buses are released to the CPU. The buses
are requested again for each succeeding byte
operation.
• Burst: data operations continue until a port's Ready
line to the DMA goes inactive. The DMA then stops
and releases the system buses after completing its
current byte operation.
• Continuous: data operations continue until the end
ofthe progra mmed block of data is reached before the
system buses are released. If a port's Ready line goes
inactive before this occurs, the DMA simply pauses
until the Ready line comes active again.
There are two aspects to the variable cycle feature. First,
the entire read and write cycles (periods) associated
with the source and destination ports can be
independently programmed as 2, 3 or 4 T-cycles long
(more if Wait cycles are used), thereby increasing or
decreasing the speed with which all DMA signals
change (Figure 5).
VARIABLE CYCLE LENGTH
FigureS
In all modes, once a byte of data'is read into the DMA,
the operation on the byte will be completed in an orderly
fashion, regardless of the state of other signals
(including a port's Ready line).
Due to the DMA's high-speed buffered method of
reading data, operations on one byte are not completed
until the next byte is read in. Consequently, total transfer
or search block lengths must be two or more bytes, and
that block lengths programmed into the DMA must be
one byte less than the desired block length (count is N-1
where N is the block length).
Commands and Status
The zao DMA has several writeable control registers
and readable status registers available to the CPU.
Control bytes can be written to the DMA while the DMA
is enabled or disabled, but the act of writing a control
byte to the DMA disables the DMA until it is again
enabled by a specific command. Status bytes can also be
read at any time, but writing the Read Status command
or the Read Mask command disables the DMA.
Control bytes to the DMA include those which effect
immediate command actions such as enable, disable,
reset, load starting-address buffers, continue, clear
counters, clear status bits and the like. In addition, many
mode-setting control bytes can be written, including
mode and class of operation, port configuration, starting
addresses, block length, address counting rule, match
and match-mask byte, interrupt conditions, interrupt
vector, status-affects-vector condition, pulse counting,
auto restart, Ready-line and Wait-line rules, and read
mask.
Readable status registers include a general status byte
reflecting Ready-line, end-of-block, byte-match and
interrupt condition"s, as well as Dual-byte registers for
the current byte count, Port A address and Port B
address.
Second, the four signals in each port specifica
associated with transfers of data (110 Request, Me
Request, Read and Write) can each have its active
trailing edge terminated one-half T-cycle early. This
adds a further dimension of flexibility and speed,
allowing such things as shorter-than-normal Read or
Write signals that go inactive before data starts to
change.
Address Generation
Two 16-bit addresses are generated by the zao DMA for
every transfer or search operation, one address for the
source Port A and another for the destination Port B.
Each address can be either variable or fixed. Variable
addresses can increment or decrement from the
programmed starting address. The fixed-address
capability eliminates the need for separate enabling
wires to 110 ports.
Port addresses are multiplexed onto the system address
bus, depending on whether the DMA is reading the
source port or writing to the destination port. Two
readable address counters (2-bytes each) keep the
current address of each port.
Auto Restart
The starting addresses of either port can be reloaded
automatically at the end of a block. This option is
selected by the Auto Restart control bit. The byte
counter is cleared when the addresses are reloaded.
IV-3
The Auto Restart feature relieves the CPU of software
overhead for repetitive operations such as CRT refresh
a nd many others. Moreover, the CPU can write different
starting addresses into bufferregisters during transfers
causing the Auto Restart to begin at a new location.
Bus Acknowledge pin of the CPU. lower-priority DMAs
have their BAI connected to the BAO of a higher-priority
DMA.
Interrupts
The MK3883 Z80 DMA can be programmed to interrupt
the CPU on four conditions:
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
• Interrupt on Match at End of Block
Any of these interrupts cause an interrupt-pending
status bit to be set, and each ofthem can optionally alter
the DMA's interrupt vector. Due to the buffered
constraint mentioned under "Modes of Operation,"
interrupts on Match at End of Block are caused by
matches to the byte just prior to the last byte in the block.
The DMA shares the Z80 family's elaborate interrupt
scheme, which provides fast interrupt service in realtime applications. In a Z80 CPU environment, the DMA
passes its internally modifiable 8-bit interrupt vector to
the CPU, which adds an additional eight bits to form the
memory address of the interrupt-routine table. This
table contains the address of the beginning of the
interrupt rOiJtineitself.
Pulse Generation
External devices can keep track of how many bytes have
been transferred by using the DMA's puise output,
which provides a signal at 256-byte intervals. The
interval sequence may be offset at the beginning by 1 to
255 bytes.
.
PI", DESCRIPTIONS
AO-A15' System Address Bus (output, 3-state). Addresses generated by the DMA are sent to both source
and destination ports(main memory or 1/0 peripherals)
on these lines.
BAl. Bus Acknowledge In (input, active low). Signals
that the system buses have been released for DMA
control. In multiple-DMA configurations, the BAI pin of
the highe$t priority DMA is normally connected to the
BUSRQ. Bus Request (bidirectional, active low, open
drain). As an output, it sends requests for control of the
system address bus, data bus and control bus to the
CPU. As an input when multiple DMAs are strung
together in a priority daisy chain via BAI and BAO, it
senses when another DMA has requested the buses
and causes this DMA to refrain from bus requesting until
the other DMA is finished. Because it is a bidirectional
pin, there cannot be any buffers between this DMA and
any other DMA. It can, however, have a unidirectional
into the CPU. A pull-up resistor is connected to this pin.
CE/WAIT. Chip Enable and Wait (input, active low).
Normally this functions only as a CE line, but it can also
be programmed to serve a WAif function. As a CE line
from the CPU, it becomes active when WR and lORa are
active and the 110 port address on the system address
bus is the DMA's address, thereby allowing a transfer of
control or command bytes from the CPU to the DMA. As
a WAIT line from memory or 1/0 devices, after the DMA
has received a bus-request acknowledge from the CPU,
it causes wait states to be inserted in the DMA's
operation cycles thereby slowing the DMA to a speed
that matches the memory or 1/0 device.
In this process, CPU control is transferred directly to the
interrupt routine, so that the next instruction executed
after an interrupt acknowledge is the first instruction of
the interrupt routine itself.
The intertupt line outputs the pulse signal in a manner
that prevents misinterpretation by the CPU as an
interrupt request, since it only appears when the Bus
Request and~us Acknowledge lines are both active.
BAO. Bus Acknowledge Out (output, active low). In a
multiple-DMA configuration, this pin signals that no
other higher-priority DMA has requested the system
busses. BAI and SAO form a daisy chain for multipleDMA priority resolution over bus control.
ClK. System clock (input). Standard Z80 single-phase
plock at 2.5MHz (MK3883) or 4.0MHz (MK3883-4). For
slower system clocks, a TTL gate with a large pullup
resistor may be adequate to meet the timing and voltage
ievei specification. For higher-speed systems, use a
clock driver with an active pullup to meet the VIH
specification and risetime requirements.
00-07' System Data Bus (bidirectional, 3-state).
Commands from the CPU, DMA status, and data from
memory or 1/0 peripherals are transferred on these
lines.
lEI. Interrupt Enable In (input, active High). This is used
with lEO to form a priority daisy chain when there is
more than one interrupt-driven device. A High on this
line indicates that no other device of higher priority is
being serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active High). lEO is
High only if lEI is High and the CPU is not servicing an
interrupt from this DMA. Thus, this signal blocks lowerpriority devices from interrupting while a higher-priority
device is being serviced by its CPU interrupt service
routine.
IV-4
iNf. Interrupt Request (output, active Low, open drain).
This requests a CPU interrupt. The CPU acknowledges
the interrupt by pulling its lORa output Low during an
M1 cycle. It is typically connected to the INT pin of the
CPU with a pullup resistor and tied to all other iN'f pins
in the system.
RD. Read (bidirectional, active Low, 3-state). As an
input, this indicates that the CPU wants to read status
bytes from the DMA's read registers. As an output, after
the DMA has taken control of the system buses, it
indicates a DMA-controlled read from a memory or 1/0
port address.
lORa. InputlOutput Request (bidirectional. active
Low, 3-state). As an input, this indicates that the lower
half of the address bus holds a valid 1/0 port address for
transfer of control or status bytes from or to the CPU,
respectively; this DMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously active. As an
output, after the I?MA has taken control of the system
busses, it indicates that the lower half of the address bus
holds a valid port address for another 1/0 device
involved in a DMA transfer of data. When 10ROand M1
are both active simultaneously, an interrupt acknowledge is indicated.
WR. Write (bidirectional, active Low, 3-state). As an
input, this indicates that the CPU wants to write control
or command bytes to the DMA write registers. As an
output, after the DMA has taken control of the system
busses, it indicates a DMA-controlled write to a memory
or 1/0 port address.
ROY. Ready (input, programmable active Low or High).
This is monitored by the DMA to determine when a
peripheral device associated with a DMA port is ready
for a read or write operation. Depending on the mode of
DMA operation (byte, burst or continuous), the RDY line
indirectly controls DMA activity by causing the BUSRO
line to go Low or High.
M1. Machine Cycle One (input, active Low). Indicates
that the current CPU machine cycle is an instruction
fetch. It is used by the DMA to decode the return-frominterrupt instruction (RETI) (ED-4D) sent by the CPU.
During two-byte instruction fetches, M1 is active as
each opcode byte is fetched. An interrupt acknowledge
is indicated when both M1 and lORa are active.
INTERNAL STRUCTURE
The internal structure of the. MK3883 Z80 DMA
includes driver and receiver circuitry for interfacing
with an 8-bit system data bus, a 16-bit system address
bus, and system control lines (Figure 6). In a Z80 CPU
environment, the DMA can be tied directly to the
analogous pins on the CPU (Figure 7) with no additional
buffering, except for the CE/WAIT line. .
iiififEQ. Memory Request (bidirectional, active Low, 3state). This indicates that the address bus holds a valid
address for a memory read or write operation. As an
input, it indicates that control or status information from
or to memory is to be transferred to the DMA, if the
DMA's CE and WR or RD lines are simultaneously
active. As an output, after the DMA has taken control of
the system buses, it indicates a DMA transfer request
from or to memory.
The DMA's internal data bus interfaces with the system
data bus and services all internal logic and registers.
Addresses generated from this logic for Ports A and B
(source and destination) of the DMA's single transfer
channel are multiplexed onto the system address bus.
BLOCK DIAGRAM
Figure 6
INTERRUPT
AND BUS
PRIORITY
LOGIC
BYTE
COUNTER
PULSE
LOGIC
PORTA
ADDRESS
SYSTEM
DATA
BUS
CONTROL
SYSTEM
ADDRESS
BUS
BUS
CONTROL
LOGIC
CONTROL
AND
STATUS
REGISTERS
IV-5
BYTE
MATCH
LOGIC
PORTB
ADDRESS
RRO-RRS - Read Registers 0 through S
Specialized logic circuits in the DMA are dedicated to
the various functions of external bus interfacing,
internal bus control, byte matching, byte counting,
periodic pulse generation, CPU interrupts, bus requests,
and address generation. A set of twenty-one writeable
control registers and seven. readable status registers
provide the means by which the CPU governs and
monitors the activities of these logic circuits. All
registers are eight bits wide, with double-byte
information stored in adjacent registers. The two
starting-address registers (two bytes each) for Ports A
and B are buffered.
Writing to a register within a write-register group
involves first writing to the base register, with the
appropriate pointer bits set, then writing to one or more
of the other registers within the group. All seven of the
readable status registers are accessed sequentially
according to a programmable mask contained in one of
the writeable registers. The section entitled "Programming" explains this in more detail.
A pipelining scheme is used for reading data in. The
programmed block length is the number of bytes
compared to the byte counter, which increments at the
end of each cycle. In searches, data byte comparisons
with the match byte are made during the read Cycle of
the next byte. Matches are, therefore, discovered only
after the next byte is read in.
The 21 writeable control registers are organized into
seven base-register groups, most of which have
multiple registers. The base registers in each writeable
group contain both control/command bits and pointer
bits that can be set to address other registers within the
group. The seven readable status registers have no
analogous second-level registers.
In multiple-DMA configurations, interrupt-request
daisy chains are prioritized by the order in which their
lEI and lEO lines are connected. The system bus,
however, may not be pre-empted. Any DMA that gains
access to the system buses keeps them until it is
finished.
The registers are designated as follows, according to
their base-register groups:
WRO-WR6 - Write Register groups 0 through 6 (7 base
registers plus 14 assl,>ciated registers)
MULTIPLE-DMA INTERCONNECTION TO THE
Figure 7
zao CPU
, . . - - - - - - - - - 1 BiiSAK
CPU
U~MON
TONEXTDMA
FROM HIGHER·PRIORlty
INTERRUPTING DEVICE
DMA
DMA
IEOI---~
lEI
lEI
lEO
RDY
RDY
IV-S
TO LOWER·PRIORITY
INTERRUPTING DEVICE
Writing
WRITE REGISTERS
WRO
Base register byte
Port A starting address (low byte)
Port A starting address (high byte)
Block length (low byte)
Block length (high byte)
WR1
Base register byte
Port A variable-timing byte
Control or command bytes are written into one or more
of the Write Register groups (WRO-WR6) by first writi ng
to the base register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers in a group
are sequentially accessed by first writing a byte to the
base register containing register-group identification
and pointer bits (1's) to one or more of that base
register's associated registers.
WR2
Base register byte
Port B variable-timing byte
READ REGISTERS
WR3
Base register byte
Mask byte
Match byte
WR4
Base register byte
Port B starting address (low byte)
Port B starting address (high byte)
Interrupt control byte
Pulse control byte
Interrupt vector
WR5
Base register byte
WR6
Base register byte
Read mask
Figure 8a.
READ REGISTER 0
0 7 0 6 0 5 0 4 0 3 O2 0 1 DO
~:::!:=-;-"I~,~~I'"T
STATUS BYTE
~~
1
~
DMAOPERATION
HAS OCCURRED
o ~ READY ACTIVE
-UNDEFINED
o ~ INTERRUPT PENDING
' - - - - - - - - 0 ~ MATCH FOUND
~ END OF BLOCK
UNDEFINED
1.---------0
READ REGISTERS
READ REGISTER 1
RRO
Status byte
RR1
Byte counter (low byte)
RR2
Byte counter (high byte)
RR3
Port A address counter (low byte)
READ REGISTER 3
RR4
Port A address counter (high byte)
L--L--'L--L---'_...L---L_.L.-..J.
RR5
Port B address counter (low byte)
READ REGISTER 4
RR6
Port B address counter (high byte)
READ REGISTER 2
BYTE COUNTER
I (HIGH
BYTE)
L-........_ L -.........--'L--L--.L_..L.---'.
A ADDRESS COUNTER
I PORT
(LOW BYTE)
PORT A ADDRESS COUNTER
(HIGH BYTE)
READ REGISTER 5
PROGRAMMING
PORT B ADDRESS COUNTER
I (lOW
BYTE)
I.--L--'L.-...L.--'_...L---L_.L.-..J.
READ REGISTER 6
zao
The
OMA has two programmable fundamental
states: (1) an enabled state, in which itcan gain control
of the system buses and direct the transfer of data
between ports, and (2) a disabled state, in which it can
initiate neither bus requests or data transfers. When the
OMA is powered up or reset by any means, it is
automatically placed into the disabled state. Program
commands can be written to it by the CPU in either state,
but this automatically puts the OMA in the disabled
state, which is maintained until an enabled command is
issued by the CPU. The CPU must program the OMA in
advance of any data search or transfer by addressing it
as an I/O port and sending a sequence of control bytes
using an Output instruction (such as OTIR for the
CPU).
zao
PORT B ADDRESS COUNTER
I (HIGH
BYTE)
L-........_ L -.........--'L--L--.L_..L.---'.
This is illustrated in Figure a. In this figure, the
sequence in which associated registers within a group
can be written to is shown by the vertical position of the
associated registers. For example, if a byte written tothe
OMA contains the bits that identify WRO (bits ~O, 01
and 07), and also contains 1's in the bit positions that
point to the associated "Port A Starting Address (low
byte)" and "Port A Starti, II Address (high byte)" then
the next two bytes written to the OMA will be stored in
these two registers, in that order.
IV-7
WRITE REGISTERS
Figure 8b
WRITE REGISTER 2
WRITE REGISTER 0
~~~~-r~~-L~-...I
L....--L...,...-'-r...,...-'-r...,...-L,,...-L-r BASE REGISTER BYTE
o
o
1
1
0
1
0
o = PORT B
1 = PORT A
BASE REGISTER BYTE
0= MEMORY
1 = I/O
o = PORT B ADDRESS DECREMENTS
DO NOT USE
= TRANSFER
= SEARCH
= SEARCH/TRANSFER
1 = PORT B ADDRESS INCREMENTS
0= PORT B ADDRESS VARIABLE
1 = PORT B ADDRESS FIXED
r--r~r-'--'--~~--r-~\PORTB
VARIABLE TIMING BYTE
PORT A
PORT B
r-.,............-.L-........-J......,r,-L.,.......~
o = CYCLE LENGTH = 4
r--,.-'-T""'''-T-'-T''"''--y-r-""T--' PORT A STARTING ADDRESS
1 = CYCLE LENGTH = 3
o
L-........."T""'--r-'-T-''--...L.--L-L....... (LOW BYTE)
o = CYCLE LENGTH = 2
o
1 DO NOT USE
.....+ - - - - + - - t - - - = iiiiR ENDS V, CYCLE EARLY
L....____
= RD ENDS V. CYCLE EARLY
L-.+_ _ _ ~ MiiEa ENDS V, CYCLE EARLY
L -_ _ = lORa ENDS 'h CYCLE EARLY
r-""T-'-r'''-T-'-r-""T-r-""T--' PORT A STARTING ADDRESS
-I_+___
L-.-L"T""'--y..............- - ' -........_L....... (HIGH BYTE)
r--,.-'-T""'...-r--,.-r-~--, BLOCK LENGTH
'----'-"T""'---'----''--...L.--L_L....... (LOW BYTE)
WRITE REGISTER 3
r--,.'""-r-""T-r--,.-r-""T--' BLOCK LENGTH
L-........._L--'----''--...L........L_L....... (HIGH BYTE)
r.....;...........,...J....,,...L-,-..L...,..-L..,....L..::-L..:0.... BASE REGISTER BYTE
WRITE REGISTER 1
1 = STOP ON MATCH
L---'--rL,--'--r-'-~--'---'-~
-+--t-+--.,. = DMA ENABLE
-+--+-- = INTERRUPT ENABLE
BASE REGISTER BYTE
0= MEMORY
1 = I/O
L-........_.L-...........,...-'-........_.L--L--J MASK BYTE (0 = COMPARE)
o = PORT A ADDRESS DECREMENTS
1 = PORT A ADDRESS INCREMENTS
L -........_.L--L_.L--L__L--L--JMATCHBYTE
0= PORT A ADDRESS VARIABLE
1 = PORT A ADDRESS FIXED
are always read in a fixed sequence beginning with RRO
and ending with RR6. However, the register read in this
sequence is determined by programming the Read Mask
'-t........--r--'-........---'-,--L-r-L,r-r VARIABLE TIMING BYTE
in WR6. The sequence of reading is initialized bywriting
an Initiate Read Sequence or Set Read Status command
o = CYCLE LENGTH = 4
1 = CYCLE LENGTH = 3
to WR6. After a Reset DMA, the sequence must be
o = CYCLE LENGTH = 2
initialized with the Initiate Read Sequence command or
o
1 DO NOT USE
1..--+____+--+___ = WR ENDS 'h CYCLE EARLY a Read Status command. The sequence of reading all
registers that are not excluded by the Read Mask
L-_ _ _-+_+-___ = AD ENDS V. CYCLE EARLY
......- + - - - = MREo ENDS V. CYCLE EARLY register must be completed before a new Initiate Read
L-._ _ _ = lORa ENDS 'h CYCLE EARLY Sequence or Read Status command.
r-~~r-~-r-~-r-~--, PORTA
Fixed-Address Programming
Reading
The Read Registers (RRO-RR6) are read by the CPU by
addressing the DMA as an 1/0 port using an Input
instruction (such as INIR for the
CPU). The readable
bytes contain DMA status, byte-counter values, and
port addresses since the last DMA reset. The registers
zao
A special circumstance arises when programming a
destination port to have a fixed address. The load
command in WR6 only loads a fixed address to a port
selected as the source, not to a port selected as the
destination. Therefore, a fixed destination address must
be loaded by temporarily declaring it a fixed-source
IV-S
WRITE REGISTERS
WRITE REGISTER 6
Figure 8b
0 7 0 6 0 5 0 4 0 3 O2 0 1 DO
WRITE REGISTER 4
11 1 1 1 1 1 11 1 1BASE REGISTER BYTE
IIIII
HEX
C3 1
L....-L.,..-........-L.,..-"'-r-L.,.-.l.--L-"1..... BASE REGISTER BYTE
o
0
1
1
1
0
1
o
=
=
=
=
BYTE
CONTINUOUS
BURST
DO NOT PROGRAM
0
0
0
CF
o o o
o o
o
o o
03
o
AB 0
AF 0
A3 0
1
1
1
o
o
1
1
87
0
0
0
C7 1
~""T""--.r--""T""..L..,,.-L"""T"".L.,r--""T""---' PORT B STARTING
............--'L--........,.........,........--'L--.......- - I ADDRESS (LOW BYTE)
0
CB
1
....."""T""--.r--""T""-'-,r-'-"""T""--.r--""T""---. PORT B STARTING
............. - L - -.......-r-'L-.--L.---'L-........- - I
ADDRESS (HIGH BYTE)
....."""T""--r--""T""~r--r--r--r---. INTERRUPT
~-L~L,-L~~-L,-~-L~CONTROLBYTE
1 = INTERRUPT ON MATCH
= INTERRUPT AT END OF
BLOCK
= PULSE GENERATED
' - - + - 1 1 - - - - - = STATUS AFFECTS VECTOR
1 . . - - - 1 - + - - - - - = INTERRUPT ON ROY
0
o o
o
1
o o o
8300000
'--~~~~~__~~'--~--'PULSECONTROLBYTE
A7
0
............--''--~~~~~~~--'INTERRUPTVECTOR
BF
0
B3
0
8B
0
B7
0
BB
0
= INTERRUPT ON ROY
= INTERRUPT ON MATCH
= INTERRUPT ON END OF
BLOCK
= INTERRUPT ON MATCH
AT END OF BLOCK
0
0
0
0
0
.1
0
0
0
WRITE REGISTER 5
0
RESET INTERRUPT CIRCUITRY.
DISABLE INTERRUPT AND BUS
REQUEST LOGIC. UNFORCE
INTERNAL nEADY CONDITION.
DISABLE "MUXCE" AND STOP
AUTO REPEAT.
RESET PORT A TIMING TO
STANDARD l80 CPU TIMING.
RESET PORT B TIMING TO
STANDARD l80 CPU TIMING .
LOAD STARTING ADDRESS FOR
BOTH PORTS. CLEAR BYTE
COUNTER .
ADDRESS CONTINUE FROM
PRESENT LOCATIONS. CLEAR
BYTE COUNTER .
ENABLE INTERRUPTS.
DISABLE INTERRUPTS.
RESET AND DISABLE INTERRUPT
CIRCUITS (LIKE RETI) AND
UNFORCETHEINTERNALREADY
CONDITON.
BOTH AFFECT ALL
ENABLE DMA OPERATIONS EXCEPT INTERRUPTS.
DISABLE DMA BUT DO NOT RESET
ANY FUNCTIONS.
INITIATE READ SEQUENCE TO THE
FIRST REGISTER DESIGNATED AS
READABLE BY THE READ MASK
REGISTER .
SET READ STATUS SO NEXT READ
IS FROM STATUS REGISTER.
FORCE AN INTERNAL READY
CONDITION INDEPENDENT
"OF THE ROY" INPUT. (USED FOR
MEMORY-TO-MEMORY
OPERATIONS WHERE NO ROY
SIGNAL IS NEEDED. THIS
COMMAND DOES NOT FUNCTION
IN THE "BYTE-AT-A-TIME" MODE).
CLEAR MATCH AND END OF
BLOCK STATUS BITS.
ENABLE AFTER RETI SO DMA
REQUESTS BUS ONLY AFTER
RECEIVING A RETI. MUST BE
FOLLOWED BY AN ENABLE DMA
COMMAND.
READ MASK IS THE FOLLOWING
BYTE
L....:-L--'~~~L-,--L..;:..JL-.:..~~ BASE REGISTER BYTE
READ MASK (1 = ENABLE)
0= READY ACTIVE LOW
1 = READY ACTIVE HIGH
o = ClONLY
1 = CE/WAIT MULTIPLEXED
o = STOP ON END OF BLOCK
1 = AUTO REPEAT ON END OF BLOCK
STATUS
BYTE COUNTER (LOW BYTE)
BYTE COUNTER (HIGH BYTE)
L----PORT A ADDRESS (LOW BYTE)
'-------PORT A ADDRESS (HIGH BYTE)
L - - - - - - - P O R T B ADDRESS (LOW BYTE)
L -_ _ _ _ _ _ _ _ PORT B ADDRESS (HIGH BYTE)
IV-9
SAMPLE DMA PROGRAM
Figure 9
COMMENTS
07
WRO sets DMA to receive
block length. Port A starting address and temporarily
sets Port B as source.
0
Port A address (lower)
0
Port A address (upper)
Block length (lower)
08
Oil
1
1
Block Length Block Length
Upper
Lower
Follows
Follows
04
03
O2
0,
DO
HEX
1
PortA
Upper
Address
Follows
1
PortA
Lower
Address
Follows
0
B--"A
Temporary
for
Loading B
Address
0
1
79
1
0
0
0
0
Transfer, No Search
1
0
0
0
0
1
0
0
0
0
10
0
0
0
0
0
0
0
0
00
Block length (upper)
0
0
0
1
0
0
0
0
10
WRI defines Port A as
peripheral with fixed
address.
0
0
No Timing
Follows
0
Address
Changes
1
Address
Increments
0
Port is
Memory
1
This is
PortA
0
0
14
WR2 defines Port B as
peripheral with fixed
address.
0
0
1
Fixed
Address
0
1
Port is
0
This is
PortB
0
0
28
No Timing
Follows
WR4 sets mode to Burst.
sets DMA to expect Port B
address.
1
1
0
0
No Interrupt
Control Byte
Follows
0
No Upper
Address
1
Port BLower
Address
Follows
0
1
C5
Port B address (lower)
0
0
0
0
0
1
0
1
05
WR5 sets Ready active High
1
0
0
No Auto
Restart
0
No Wait
1
RDY
Active High
0
1
0
8A
States
0
1
1
1
1
CF
0
1
A--..B
1/0
Burst Mode
0
50
WR6 loads both Port addresses
and resets block counter.*
1
WRO sets Port A as source. *
0
0
WR6 reloads Port addresses
and resets block counter
1
1
0
0
Load
1
1
1
1
CF
WR6 enables DMA to start
operaticn.
1
0
0
0
Enable DMA
0
1
1
1
87
1
Load
0
0
No Address of Block
Length Bytes
0
1
Transfer, No Search
05
NOTE: The actual number of bytes transferred is one more than specified by the block length.
*These commands are necessary only in the case of a fixed destination address.
address and subsequently declaring the true source as
such, thereby implicitly making the other a destination.
The following example illustrates the steps in this
procedure. assuming that transfers are to occur from a
variable-address source (Port A) to a fixed-address
destination (Port B):
1. Temporarily declare Port B as source in WRO.
2. Load Port B address in WR6.
3. Declare Port A as source in WRO.
4. Load Port A address in WR6.
5. Enable DMA in WR6.
Figure 9 illustrates a program to transfer data from
memory (Port A) to a peripheral device (Port B). In this
example, the Port A memory starting address is 1050H
and the Port B peripheral fixed address is 05H' Note that
the data flow is 1001 H bytes-one more than specified
by the block length. The table of DMA commands may be
stored in consecutive memory locations and transferred
to the DMA with an output instruction such as the
CPU's OTIR instruction.
zao
INACTIVE STATE TIMING (DMA as CPU Peripheral)
In its inactive state, the DMA is addressed by the CPU as
an I/O peripheral for write and read (control and status)
operations. Write timing is illustrated in Figure 10.
Reading of the DMA's status byte, byte counter or port
address counters is illustrated in Figure 11. These
operations require less than three T-cycles. The CE,
10RQ and RD lines are made active over two riSing
edges of ClK, and data appears on the bus
approximately one T-cycle after they become active.
IV-10
ACTIVE STATE TIMING (DMA as Bus Controller)
CPU-TO-DMA WRITE CYCLE
Figure 10
The DMA is active when it takes control of the system
bus and begins transferring data.
ClK
Default Read and Write Cycles
CE_t---,
lORa
By default, and after reset the OM A's timing of read and
write operations is exactly the same as the zao CPU's
timing of read and write cycles for memory and liD
peripherals, with one exception: during a read cycle,
data is latched on the falling edge of T 3 and held on the
data bus across the boundary between read and write
cycles, through the end of the following write cycle.
iNA
CPU-TO-DMA READ CYCLE
Figure 11
Figure 12 illu!!trates the timing for memory-to-1I0 port
transfers and Figure 13 illustrates I/O-to-memory
transfers. Memory-to-memory and 1I0-to-1/0 transfer
timings are simply permutations of these diagrams.
MEMORY-TO-I/O TRANSFER
Figure 12
MEMORY
~READ
CLK
READ
WRITE
I
T1 I T2
-rL
f-
_1"-
I
Variable Cycle and Edge Timing
RD - \
I
rfrf-
t iORO
_
WR
.J
f-'~ f - -
-- --
--
I/O-TO-MEMORY TRANSFER
Figure 13
A O·A 15
t
10RQ
RD
During transfers, data is latched on the clock edge
causing the rising edge of RO and held until the end of
the write cycle.
0 0 .0 7
MREO
WR
t
>-
,-,'~ --..., -
The zao DMA's default operation-cycle length for the
source (read) port and destination (write) port can be
independently programmed. This variable-cycle feature
allows read or write cycles consisting of two, three or
four T -cycles (more if Wait cycles are inserted), thereby
increasing or decreasing the speed of all signals
generated by the DMA. In addition, the trailing edges of
the IORQ, MREQ, RD and WR signals can be
independently terminated one-haJf cycle early. Figure
14 illustrates this.
In the variable-cycle mode, unlike default timing,lORQ
comes active one-half cycle before MREQ, RD and WR.
CE/WAIT can be used to extend only the 3 or 4 T -cycle
variable cycles. It is sampled at the falling edge ofT2 for
3- or 4-cycle memory cycles, and at the falling edge of
T3 for 4-cycle liD cycles.
CLK
WRITE
I
MREO - \
{
----
READ
1/0 WRITE---+!
T3
T1
T2
TW' T3 I
rL.!L!L-;,-rr..~
I
The default timing uses three T-cycles for memory
transactions and four T-cycles for liD transactions,
which include one automatically inserted wait cycle
between T2 andT3.lfthe CE/WAIT line is programmed
to act as WAIT line during the DMA's active state, it is
sampled on the falling edge of T2 for memory
transactions and the falling edge of TW for liD
transactions. If CE/WAIT is low during this time another
T-cycle is added, during which the CE/WAIT line will
again be sampled. The duration oftransactionscan thus
be indefinitely extended.
t---
CE/WAIT:'
-
'\
-
Bus Requests
Figure 15 illustrates the bus request and acceptance
timing. The ROY line, which may be programmed active
IV-11
VARIABLE-CYCLE AND EDGE TIMING
BUS RelEASE WHEN NOT READY (BURST MODE)
Figure 14
Figure 18
CLK
CLK
ROY
ACTIVE
INACTIVE
j..--CURRENT
BYTE
OPERATION
lORa ,\....._ _..L-
r ..... ,-
MREO~
t
RD, WR
2-CYClE
EARLY
END
'---'-~_ _~~_ _ _ _ __
I
-'--
3-CYClE
EARLY
END
I
7--·
BUS RelEASE ON MATCH
(BURST AND CONTINUOUS MODES)
t
Figure 19
4-CYCLE
EARLY
END
BUS REQUEST AND ACCEPTANCE
ROY INACTIVE
Figure 15
I.
~BYTE
ClK
READ 100
.1 . .
BYTEn+1
READ IN AND
MATCH FOUND
ON BYTE N
iili'SRa .-_-:::.
- .../
DMA DMA
ACTIVE INACTIVE
BUS RelEASE (BYTE-AT-A-TIME MODE)
Figure 16
High or low, is sampled on every rising edge of ClK. If it
is found to be active, and the bus is not in use by any
other device, the following rising edge of ClK drives
BUSRQ low. After receiving BUSRQ, the CPU
acknowledges on the BAI input either directly or
through a multiple-DMA daisy chain. When a low is
detected on BAI for two consecutive rising edges of ClK,
the DMA will begin transferring data on the next rising
edge of ClK.
Bus Release Byte-at-a-Time
DMA ACTIVE
~
DMA INACTIVE
In Byte-at-a-Time mode, BUSRQ is brought high on the
rising edge of ClK prior to the end of each read cycle
(search-only) or write cycle (transfer and trllnsfer/
search) as illustrated in Figure 16. This is done
regardless of the state of RDY. There is no possibility of
confusion when a
CPU is used since the CPU
cannot begin an operation until the following T-cycle.
Most other CPUs are not bothered by this either,
although note should be taken of it. The next bus
request for the next byte will come after both BUSRQ
and BAI have returned high.
zao
BUS RelEASE (CONTINUOUS MODE)
Figure 17
ROY
ACTIVE
INACTIVE
I-+--lAST BYTE
OPERATION.
BLOCK
Bus Release at End of Block
DMA
INACTIVE
In Burst and Continuous modes, an end of block causes
BUSRQ to go High usually on the same rising edge of
ClK in which the DMA completes the transfer of the
data block (Figure 17). The last byte in the block is
transferred even if RDY goes inactive before completion
of the last byte transfer.
IV-12
being read. Matches at End-of-Block are, therefore,
actually matches to the byte immediately preceding the
last byte in the block.
Bus Release on Not Ready
In Burst Mode, when RDY goes inactive it causes
BUSRO to go High on the next rising edge of ClK after
the completion of its current byte operation (Figure 18).
The action on BUSRO is thus somewhat delayed from
action on the RDY line. The DMA always completes its
current byte operation in an orderly fashion before
releasing the bus.
The RDY line can go inactive after the matching
operation begins without affecting this bus-release
timing.
Interrupts
Timings for interrupt acknowledge and return from
interrupt are the same as timings for these in other Z80
peripherals.
By contrast, B1JS1«:l is not released in Continuous mode
when RDY goes inactive. Instead, the DMA idles after
completing the current byte operation, awaiting an
active RDY again.
Interrupt on RDY (interrupt before requesting bus) does
not directly affect the BUSRO line. Instead, the interrupt
service routine must handle this by issuing the
following commands to WR6:
1. Enable after Return From Interrupt (RETI) Command
-Hex B7
2. Enable DMA-Hex 87
3. A RETI instruction that resets the IUS latch in the
Z80 DMA
Bus Release on Match
If the DMA is programmed to stop on match in Burst or
Continuous modes, a match causes BUSRO to go
inactive on the rising edge of ClK after the next byte
following the match (Figure 19). Due to the pipelining
scheme, matches are determined while the next byte is
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Operating Ambient Temperature Under Bias ...................... As Specified Under "Ordering Information"
Storage Temperature .................................................................... -65°C to +150°C
Voltage on any pin with respect to ground .................................................... -0.3V to +7V
Power Dissipation .................................................................................. 1.5W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extende~
periods may affect device reliability.
STANDARD TEST CONDITIONS
Figure 20
The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
• +4.75 :5VCC:5 +5.25V
• GND = OV
• O°C:5 TA :5 + 70°C
FROM OUTPUT O-----,r--~..........-i
UNDER TEST
All AC parameters assume a load capacitance of
100pF max. Timing references between two output
signals assume a load difference of 50pF max.
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
UNIT
VllC
Clock Input low Voltage
-0.3
0.80
V
VIHC
Clock Input High Voltage
VCC-·6
5.5
V
Vil
Input low Voltage
-0.3
0.8
V
IV-13
TEST CONDITION
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
UNIT
VIH
Input High Voltage
2.0
5.5
V
VOL
Output Low Voltage
0.4
V
IOL=3.2hlA for BUSRO
IOL=2.0mA for all others
VOH
Output High Voltage
V
IOW250~A
ICC
Power Su~plY Current
MK388
MK3883-4
III
Input Leakage Current
ILOH
2.4
150
200
TEST CONDITION
mA
mA
±10
~
VIN = OtoVCC
Tri-State Output Leakage Current
in Float
10
~
VOUT=2.4 to VCC
ILOL
Tri-State Output Leakage Current
in Float
-10
~
VOUT=0.4V
ILD
Data Bus Leakage Current in
Input Mode
± 10
~
O:5VIN:5VCC
MAX
UNIT
Vee
= 5V ± 5% unless otherwise specified, over specified temperature range.
CAPACITANCE
SYM
PARAMETER
MIN
C
Clock Capacitance
35
pF
Unmeasured Pins
CIN
Input Capacitance
10
pF
Returned to Ground
COUT
Output Capacitance
10
pF
TEST CONDITION
f = 1MHz, over specified temperature range
INACTIVE STATE AC CHARACTERISTICS
(See Figure 21)
MK3883
MK3883-4
SYM
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
TcC
Clock Cycle Time
400
4000
250
4000
ns
2
TwCh
Clock Width (High)
170
2000
105
2000
ns
3
TwCI
Clock Width (Low)
170
2000
105
2000
ns
4
TrC
Clock Rise Time
30
30
ns
5
TfC
Clock Fall Time
30
30
ns
6
Th
Hold Time for Any Specified
Setup Time
7
TsC(Cr)
lORa, WR, CE
8
TdDO(RDF)
RD to Data Output Delay
9
TsWM(Cr)
Data In to Clock
TdCf(DO)
IORO to Data Out Delay (INTA Cycle)
NO
i 10
0
t to Clock t Setup
280
0
ns
145
ns
500
t Setup (WR or M1)
t
IV-14
50
380
50
340
ns
ns
160
ns
-
INACTIVE STATE AC CHARACTERISTICS (Continued)
MK3883
NO
SYM
PARAMETER
MIN
11
TdRD(Dz)
Rot-to Data Float Delay (output buffer
disable)
12
TsIEI(lORQ) lEI
13
TdIEOr(IElr) lEI tto lEO
14
TdIEOf(lElf) lEI
15
TdMl(1EO)
Mltto IEOt Delay (interrupt just prior
to Ml
16
TsM1f(Cr)
Ml
17
TsMlr(Cf)
18
t to IORQ l Setup (INTA Cycle)
MK3883-4
MAX
MIN
160
MAX
UNIT
110
ns
140
140
ns
t Delay
210
160
ns
t to lEO t Delay
190
130
ns
300
190
ns
+)
t to Clock t Setup
210
90
ns
Ml t to Clock
t Setup
20
0
ns
TsRD(C)
RD ~ to Clock
t Setup (Ml Cycle)
240
115
ns
19
Tdl(lNT)
Interrupt Cause to INT Delay (INT
generated only when DMA is
inactive)
20
TdBAlr
(BAOr)
BAit to BAO
21
TdBAlf
(BAOf)
BAI
f
500
500
ns
t Delay
200
150
ns
t to BAO t Delay
200
150
ns
ACTIVE STATE AC CHARACTERISTICS
I.
(See Figure 22)
MK3883-4
MK3883
MIN(ns) MAX(ns) MIN(ns)
MAX(ns)
SYM
PARAMETER
1
TeC
Clock Cycle Time
400
2
TwCh
Clock Width (High)
180
2000
110
2000
3
TwCI
Clock Width (Low)
180
2000
110
2000
4
TrC
Clock Rise Time
30
20
5
TfC
Clock Fall Time
30
20
6
TdA
Address Output Delay
145
110
7
TdC(Az)
Clockt to Address Float Delay
110
90
8
TsA(MREQ) Address to MREQ ~ Setup (Memory Cycle)
9
TsA(IRW)
Address Stable to IORQ, RD, WR ~ Setup
(I/O Cycle)
10
TdRW(A)
RD, WR
t to Addr. Stable Delay
(3)+(4)-40
(3)+(4)-50
*11
TdRW(Az)
RD, WR
t to Addr. Float
(3)+(4)-60
(3)+(4)-45
12
TdCf(DO)
Clock ~ to Data Out Delay
NO
250
(2)+(5)-75
(2)+(5)-75
(1 )-80
(1 )-70
230
IV-15
150
ACTIVE STATE AC CHARACTERISTICS
MK3883-4
MK3883
MIN(ns) MAX(ns MIN(ns)
MAX(ns)
90
90
NO
SYM
PARAMETER
13
TdCr(Dz)
Clockt to Data Float Delay (Write Cycle)
14
TsDI(Cr)
Data In to Clock Setup (Read cycle when
falling edge ends read)
50
35
15
TsDI(Cf)
Data In to Clockt Setup (Read cycle when
falling edge ends read)
60
50
16
TsDO(WfM) Data Out to WR
f Setup (Memory Cycle)
17
TsDO(Wfl)
Data Out to WR
t Setup (1/0 cycle)
18
TdWr(DO)
WR
19
Th
Hold Time for Any Specified Setup Time
*20
TdCr(Mf)
Clock
t to MREO t Delay
100
85
21
TdCf(Mf)
Clock
t to MREO t Delay
100
85
22
TdCr(Mr)
Clock
t to MREO t Delay
100
85
23
TdCf(Mr)
Clock
t to MREO tDelay
100
85
24
TwM1
MREO Low Pulse Width
(1 )-40
25
TwMh
MREO High Pulse Width
(2)+(5)-30
26
TdCr(lf)
Clock
t to 10RO t Delay
90
75
27
TdCf(lf)
Clock
t to 10RO t Delay
110
85
28
TdCr(lr)
Clock
100
85
29
TdCf(lr)
110
85
30
TdCr(Rf)
t to 10RO t Delay
Clock t to 10RO t Delay
Clock t to RD t Delay
100
85
31
TdCf(Rf)
Clock
t to RD t Delay
130
95
32
TdCr(Rr)
Clock
t to RD t Delay
100
85
33
TdCf(Rr)
Clock
t to RD t Delay
110
85
34
TdCr(Wf)
Clock
80
65
35
TdCf(Wf)
90
80
*36
TdCr(Wr)
100
80
37
TdCf(Wr)
t Delay
Clock t to WR t Delay
Clock t to WR t Delay
Clock t to WR t Delay
100
80
38
TwWI
WR Low Pulse Width
39
TsWA(Cf)
WAIT to Clock
40
TdCr(B)
Clock
41
TdCr(lz)
t
(1 )-210
(1)-170
100
t to Data Out Delay
100
(3)+(4)-80
(3)+(4)-70
0
t to WR
0
(1 )-30
(2)+(5)-20
(1 )-40
t Setup
(1 )-30
70
t to BUSRO Delay
Clock t to 10RO, MREO, RD, WR Float Delay
70
100
100
100
80
NOTES.
1.
Numbers in parentheses are other parameter-numbers in this table; their
2.
values should be substituted in equations.
All equations imply DMA default (standard) timing.
3. Data must be enabled onto data bus when RD is active.
4. Asterisk(*) before parameter number means the parameter is not illustrated
in the AC Timing Diagrams.
IV-16
INACTIVE STATE CHARACTERISTICS
Figure 21
CLK
WR
DO D7
NIl
r--.--+to=~=====
lEI
ICO
INTERR~:
r-'@"'--~--'--------
f
________________
CONDITION
BA1~
r
~1~-H9----J1----
ACTIVE STATE CHARACTERISTICS
Figure 22
CLK
DO
MEMORY CYCLE
\
INPUT
D7l
OUTPUT
MREQ
1/0 CYCLE
IV-17
ORDERING INFORMATION
PART NO.
PACKAGE TYPE
MK3883N
MK3883P
MK3883J
MK3883N-10
MK3883P-10
MK3883J-10
Z80-0MA Plastic
Z80-0MA Ceramic
Z80-0MA CERDIP
Z80-0MA Plastic
Z80-DMA Ceramic
Z80-DMA CERDIP
MK3883N-4
MK3883P-4
MK3883J-4
Z80A-OMA Plastic
Z80A-DMA Ceramic
Z80A-OMA CERDIP
MAX CLOCK FREQUENCY
2.5
2.5
2.5
2.5
2.5
2.5
MHz
MHz
MHz
MHz
MHz
MHz
4 MHz
4 MHz
4 MHz
IV-18
TEMPERATURE RANGE
O°C to +70°C
O°C to +70°C
O°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
MOSTEl(.
zao
MICROCOMPUTER
Seriallnput/Output Controller MK3884
FEATURES
DESCRIPTION
o
Two independent full-duplex channels, with
separate control and status lines for modems or other
devices.
o
Data rates of 0 to 500K bits/second in the x1 clock
mode with a 2.5MHzclock(MK3884l80SI0), orOto
800K bits/second with a 4.0MHz clock (MK3884-4
l80SI0).
The MK3884 zao 510 Serial Input/Output Controller is
a dual-channel data communication interface with
extraordinary versatility and capability. Its basic
functions as a serial-to-parallel, parallel-to-serial converter/controller can be programmed by a CPU for a
broad range of serial communication applications.
o
Asynchronous protocols: everything necessary for
complete messages in 5, 6, 7 or 8 bits/character.
Includes variable stop bits and several clock-rate
multipliers; break generation and detection; parity;
overrun and framing error detection.
o
Synchronous protocols: everything necessary for
complete bit- or byte-oriented messages in 5, 6, 7 or 8
bits/character, including IBM Bisync, SOLC, HOLC,
CCITT-X.25 and others. Automatic CRC generation/checking, sync character and zero insertion/deletion, abort generation/detection and flag
insertion.
The device supports all common asynchronous and
synchronous protocols, byte- or bit-oriented, and
performs all of the functions traditionally done by
UARTs, US ARTs and synchronous communication
controllers combined, plus additional functions
traditionally performed by the CPU. Moreover, it does
this on two fully-independent channels, with an
exceptionally sophisticated interrupt structure that
allows very fast transfers.
o
Receiver data registers quadruply buffered,
transmitter registers doubly buffered.
o
Highly sophisticated and flexible daisy-chain
interrupt vectoring for interrupts without external
logic.
MK3884 Z80 510 PIN FUNCTIONS
Full interfacing is provided for CPU or OMA control. In
addition to data communication, the circuit can handle
virtually all types of serial I/O with ,fast (or slow)
peripheral devices. While designed primarily as a
member of the l~O family, its versatility makes it well
suited to many other CPUs.
The l80 510 is an n-channel silicon-gate depletionload device packaged in a 40-pin plastic, ceramic DIP, or
CERDIP. It uses a single +5V power supply and the
standard zao family single-phase clock.
MK3884 Z80 SIO
PIN ASSIGNMENTS
Figure 1
Figure 2
0,
DO
03
O2
Os
04
07
i'NT
lEI
CHANNEL A
;iE~IMODEM
~
CONTROL
FROM
CPU
a/A
M1
c/o
'5V
iffi
iYNCA
I
I
co
lED
W/RDYA
CONTROL
D.
iOiiQ
GND
Wi'iii5Va
RxDA
SYNCS
RxCA
RxDB
'TxCA
CHANNElS
MOOEM
CONTROL:
TxDA
TxOS
6TRA
i!iTiA
l5'i'liii'
Riii'
CiiA
0CDi
ClK
IV-19
em
DCDi
ifEiET
PIN DESCRIPTIONS
the CPU during a read cycle.
Figures 1 through 6 illustrate the three pin configurations (bonding options) available in the 510. The
constraints of a 40-pin package make it impossible to
bring out the Receive Clock (RxC), Transmit Clock ('Ti'C),
Data Terminal Ready (DTR) and Sync (SYNC) signals for
both channels. Therefore, either Channel B lacks a
signal or two signals are bonded together in the three
bonding options offered:
ClK. System Clock (input). The SID uses the standard
Z80 System Clock to synchronize internal signals. This
is a single-phase clock.
•
•
•
MK3887 Z80 510 lacks SYNCB
MK3885 Z80 510 lacks DTRB
MK3884 Z80 510 has all four signals, but "i"XC"B and
RxCB are bonded together
CTSA, CTSB. Clear To Send (inputs, active low).
When programmed as Auto Enables, a low on these
inputs enables the respective transmitter. If not
programmed as Auto Enables, these inputs may be
programmed as general-purpose inputs. Both inputs
are Schmitt-trigger buffered to accommodate slowrisetime signals. The 510 detects pulses on these inputs
and interrupts the CPU on both logic level transitions.
The Schmitt-trigger buffering does not guarantee a
specified noise-level margin.
The pin descriptions are as follows:
B/A. Channel A Or B Select (input, High selects
Channel B). This input defines which channel is
accessed during a data transfer between the CPU and
the 510. Address bit Ao from the CPU is often used for
the selection function.
C/D. Control Or Data Select (input, High selects
Control). This input defines the type of information
transfer performed between the CPU and the 510. A
High at this input during a CPU write to the 510 causes
the information on the data bus to be interpreted as a
command for the channel selected by B/A. A low at
C/O means that the information on the data bus is data.
Address bit A1 is often used for this function.
CEo Chip Enable (Input, active low). A low level at this
input enables the 510 to accept command or data input
from the CPU during a write cycle, or to transmit data to
00-07' System Data Bus (bidirectional, 3-state). The
system data bus transfers data and commands between
the CPU and the Z80 510. DO is the least significant bit.
DCDA, DCDB. Data Carrier Detect (inputs, active
low). These pins function as receiver enables ifthe 510
is programmed for Auto Enables; otherwise they may be
used as general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slowrisetime signals. The 510 detects pulses on these pins
and interrupts the CPU on both logic level transitions.
Schmitt-trigger buffering does not guarantee a specific
noise-level margin.
DTRA, DTRB. Data Terminal Ready (outputs, active
low). These outputs follow the state programmed into
510. They can also be programmed as generalpurpose outputs.
In the MK3885 bonding option, DTRB is omitted.
zao
MK3885 Z80 SIO PIN FUNCTIONS
MK3885 Z80 SIO PIN ASSIGNMENTS
Figure 3
Figure 4
0,
I
I
CHANNEL A
0,
'MODEM
JCONTROL.
i'OFi'O
lEI
CE
R/A'
m
c/o
.5V
AD
W/RDVA
SVIiI'&
I
!
CHANNElB
MODEM
CONTROL
RxDA
SYNCB
RxCir
TxDA
TxCi
RxDO
i5TFiA
TxDB
RTsA
RTsii
'Ci'8A
CTsB
0C0i
RESET
ClK
IV-20
GND
W7RDvi
'RXcA
hCA
'6CDA
+5V GND elK
D.
iNT
lEO
CONTROL
FROM
CPU
O2
D.
07
DATA
CPU
BUS
DO
03
lEI. Interrupt Enable In (input, active High). This signal
is used with lEO to form a priority daisy chain when
there is more than one interrupt-driven device. A High
on this line indicates that no other device of higher
priority is being serviced by a CPU interrupt service
routine.
lEO. Interrupt Enable Out (output, active High). lEO is
High only if lEI is High and the CPU is not servicing an
interrupt from this SIO. Thus, this signal blocks lower
priority devices from interrupting while a higher priority
device is being serviced by its CPU interrupt service
routine.
INT. Interrupt Request (output, open drain, active Low).
When the SIO is requesting an interrupt, it pulls fNi
Low.
lORa. Input/Output Request (input from CPU, active
Low). lORa is used in conjunction with B/A, C/O, CE
and RD to transfer commands and data between the
CPU and the SIO. When 'CE, RD and lORa are all active,
the channel selected by B/A transfers data tothe CPU (a
read operation). When CE and lORa are active, but RD is
inactive, the channel selected by B/A is written to by the
CPU with either data or control information as specified
by C/O'. As mentioned previously, if lORa and M1 are
active simultaneously, the CPU is acknowledging an
interrupt and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest priority
device requesting an interrupt.
M1. Machine Cycle (input from l80 CPU, active Low).
When M1 is active and RD'is also active, thel80 CPU is
fetching an instruction from memory; when M1 is active
while lORa is active, the SIO accepts M1 and lORa as
an interrupt acknowledge if the SIO is the highest
priority device that has interrupted the l80 CPU.
RxCA, RxCB. Receiver Clocks (inputs). Receive data is
sampled on the rising edge of RxC. The Receive Clocks
may be 1, 16, 32 or 64 times the data rate in
asynchronous modes. These clocks may be driven by
the l80 CTC Counter Timer Circuit for programmable
baud rate generation. Both inputs are Schmitt-trigger
buffered (no noise level margin is specified).
In the MK3884 bonding option, RxCB is bonded together
with TxCB.
RD. Read Cycle Status (input from CPU, active Low). If
RD is active, a memory or 110 read operation is in
progress. RD is used with B/A, CE and lORa to transfer
data from the SIO to the CPU.
RxDA, RxDB. Receive Data (inputs, active High).
Serial data at TTL levels.
RESET. Reset (input, active Low). A Low RESET
disables both receivers and transmitters, forces TxDA
and TxDB marking, forces the modem controls High and
disables all interrupts. The control registers must be
rewritten after the SIO is reset and before data is
transmitted or received.
RTSA, RTSB. Request To Send (outputs, active Low).
When the RTS bit in Write Register 5 (Figure 14) is set,
the RTS output goes Low. When the RiS bit is reset in
the Asynchronous mode, the output goes High after the
transmitter is empty. In Synchronous modes, the RTS
pin strictly follows the state of the RTS bit. Both pins can
be used as general-purpose outputs.
MK3887 l80 510 PIN FUNCTIONS
MK3887 l80 510 PIN ASSIGNMENTS
Figure 5
Figure 6
0,
I
I
°3
0.
°7
!NT
DATA
CPU
BUS
CHANNEl A
lEI
!
lEO
MODEM
CONTROL
CPU
!
ICHANNELB
MODEM
CONTROl
+6V GND eLK
IV-21
IORO
CE
B/A
cio
'5V
RD
SYNCA
..
0.
iii
W/RDYA
CONTROL
FROM
°0
°2
°4
GNO
W/RDYB
RxDA
RxDB
RxCA
RxCB
TxCA
TxCi
TxOA
TxOS
DTRA
DTRB
RiiA
RTSS
eTSA
DCDA
CTsB
DCiiB
ClK
RESET
SYNCA, SYNCB. Synchronization ,(inputs/outputs,
active Low). These pins can act either as inputs or
outputs. In the asynchronous receive mode, they are
inputs similar to CTS and l)C[). In this mode; the
transitions on these lines affect the state of the Sync/Hunt status bit in Read Register 0 (Figure 13), but have
no other function. In the External Sync mode, these
lines also act as inputs. When external synchronization
is achieved, SYNC must be driven Low on the second
rising edge ofRiC' after that rising edge ofR~on which
the last bit of the sync character was received. In other
words, after the sync pattern is detected, the external
logic must wait for two full Receive Clock cycles to
activate the SYNC input. Once""SVf'JC is forced Low, it
should be kept Low until the CPU informs the external
synchronization detect logic that synchronization has
been lost or a new message is about to start. Character
assembly begins on the rising edge of lrxC that
immediately precedes the falling edge of SYNC in the
External Sync mode.
In the internal synchronization mode (Monosync and
Bisync), these pins act as outputs that are active during
the part of the receive clock (RxC) cycle in which sync
characters are recognized. The sync condition is not
latched, so these outputs are active each time a sync
pattern is recognized, regardless of character
boundaries.
In the MK3aa7 bonding option, SYNCB is omitted.
rate generation.
In the MK3aa4 bonding option, TxCB is bonded together
with~.
TxDA, TxDB. Transmit Data (outputs, active High).
Serial data at TTL levels.
W/RDYA, W/RDYB. Wait/Ready A. Wait/Ready B
(outputs, open drain, when programmed for Wait
function; driven High and Low when programmed for
Ready function). These dual-purpose outputs may be
programmed as Ready lines for a DMA controller or as
Wait lines that synchronize the CPU to the SID data rate.
The reset state is open drain.
FUNCTIONAL CAPABILITIES
The functional capabilities of the zao SID can be
described from two different points of view: as a data
communications device, it transmits and receives serial
data in a wide variety of data-communication protocols;
as a zao family peripheral, it interacts with the zao CPU
and other peripheral circuits, sharing the data, address
and control buses, as well as being a part of the zao
interrupt structure, As a peripheral to other microprocessors, the SID offers valuable features such as nonvectored interrupts, polling and simple handshake
capability.
Figure a illustrates the conventional devices that the
SID replaces.
TxCA, TxCB. Transmitter Clocks (inputs). TxD changes
from the falling edge of TxC. In asynchronous modes,
the Transmitter Clocks may be 1, 16,32 or 64 times the
data rate; however, the clock multiplier for the transmitter and the receiver must be the same. The Transmit
Clock inputs are Schmitt-trigger buffered for relaxed
rise- and fall-time requirements (no noise level margin
is specified). Transmitter Clocks may be driven by the
zao CTC Counter Timer Circuit for programmable baud
The first part of the following discussion covers SID
data-communication capabilities; the second part
describes interactions between the CPU and the SID.
DATA COMMUNICATION CAPABILITIES
The SID provides two independent full-duplex channels
that can be programmed for use in any common
asynchronous or synchronous data-communication
Block Diagram
Figure 7
} SERIAL DATA
_
} CHANNEl CLOCKS
SYNC
WAITIREADY
INTERNAL
CONTROL
lOGIC
I
MODEM OR
OTHER CONTROLS
DATA
CPU
BUS 1/0
CONTROl==>L-_ _.J
I
MODEM OR
OTHER CONTROLS
INTERRUPT
CONTROL
LINES
INTERRUPT
CONTROL
lOGIC
} SERIAL DATA
_
} CHANNEl CLOCKS
~READY
IV-22
Conventional Devices Replaced by the Z80 SIO
Figure 8
CHANNEL
A
MICROPROCESSOR
INTERFACE
CHANNEL
a
zao
MICROPROCESSOR
INTERFACE
CHANNEL
A
SIO
CHANNEL
a
protocol. Figure 9 illustrates some of these protocols.
The following is a short description of them. A more
detailed explanation of these modes can be found in the
MK3884 Z80 SIO Technical Manual.
receive and transmit clock inputs. In asynchronous
modes, the SYNC pin may be programmed as an input
that can be used for functions such as monitoring a ring
indicator.
Asynchronous Modes. Transmission and reception
can be done independently on each channel with five to
eight bits per character, plus optional even or odd parity.
The transmitters can supply one, one-and-a-half or two
stop bits per character and can provide a break output at
any time. The receiver break-detection logic interrupts
the CPU both at the start and end of a received break.
Reception is protected from spikes by a transient spikerejection mechanism that checks the signal one-half a
bit time after a Low level is detected on the receive data
input (RxOA or RxOB in Figure 5). If the Low does not
persist-as in the case of a transient-the character
assembly process is not started.
Synchronous Modes. The SIO supports both byteoriented and bit-oriented synchronous communication.
Synchronous byte-oriented protocols can be handled in
several modes that allow character synchronization
with an 8-bit sync character (Monosync), any 16-bit
sync pattern (Bisync) or with an external sync signal.
Leading sync characters can be removed without
interrupting the CPU.
Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occurred. Vectored interrupts allow fast servicing
of error conditions using dedicated routines. Furthermore, a built-in checking process avoids interpreting a
framing error as a new start bit: a framing error results
in the addition of one-half a bit time to the point at which
the search for the next start bit is begun.
'
CRC checking for synchronous byte-oriented modes is
delayed by one character time so the CPU may disable
CRC checking on specific characters. This permits
implementation of protocols such as IBM Bisync.
Both CRC-16 (X 16 + X15 + X2 + 1) and cCln (X16 + X12 +
X5 +1) error checking polynomials are supported. In all
non-SOLC modes, the CRC generator is initialized to O's;
in SOLC modes, it is initialized to 1 'so The SIO can be
used for interfacing to peripherals such as hard-sectored floppy disk, but it cannot generate or check
CRC for IBM-compatible soft-sectored disks. The SIO
also provides a feature that automatically transmits
CRC data when no other data is available for transmission. This allows very high-speed transmissions under
Five-, six- or seven-bit sync characters are detected
with 8- or 16-bit patterns in the SIO by overlapping the
larger pattern across multiple in-coming sync
characters, as shown in Figure 10.
The SIO does not require symmetric transmit and
receive clock signals-a feature that allows it to be used
with MK3882 Z80 CTC or many other clock sources. The
transmitter and receiver can handle data at a rate of 1,
1/16, 1/32 or 1/64 of the clock rate supplied to the
IV-23
DMA control with no need for CPU intervention at the
end of message. When there is no data or CRC to send
in synchronous modes, the transmitter inserts 8- or
16-bit sync characters regardless of the programmed
character length.
The 510 can be conveniently used under DMA control to
provide high-speed reception or transmission. In
reception, for example, the 510 can interrupt the CPU
when the first character of a message is received. The
CPU then enables the OMA to transfer the message to
memory. The 510 then issues an end-of-frame interrupt
and the CPU can check the status of the received
message. Thus, the CPU is freed for other service while
the message is being received.
a
The 510 supports synchronous bit-oriented protocols
such as SOLC and HDLC by performing automatic flag
sending, zero insertion and CRC generation. A special
command can be used to abort a frame in transmission.
At the end of a message the 510 automatically transmits
the CRC and trailing flag when the transmit buffer
becomes empty. If a transmit underrun occurs in the
middle of a message, an external/status interrupt
warns the CPU of this status change so that an abort
may be issued. One to eight bits per character can be
sent, which allows reception of a message with no prior
information aboutthe character structure in the information field of a frame.
I/O INTERFACE CAPABILITIES
The 510 offers the choice of polling, interrupt (vectored
or non-vectored) and block-transfer modes to transfer
data, status and control information to and from the
CPU. The block-transfer mode can also be implemented
under DMA control.
Polling. Two status registers are updated at
appropriate times for each fu nction bei ng performed (for
example, CRC error-status valid at the end of a
message). When the CPU is operated in a polling
fashion, one of the SIO's two status registers is used to
indicate whether the 510 has some data or needs some
data. Depending on the contents of this register, the
CPU wi" either write data, read data, or just go on. Two
bits in the register indicate that a data transfer is
needed. In addition, error and other conditions are
indicated. The second status register (special receive
conditions) does not have to be read in a polling
sequence, until a character has been received. A"
interrupt modes are disabled when operating the device
in a polled environment.
The receiver automatically synchronizes on the leading
flag of a frame in SOLC or HDLC, and provides a
synchronization signal on the SYNC pin; an interrupt
can also be programmed. The receiver can be
programmed to search for frames addressed by a single
byte to only a specified user-selected address or to a
global broadcast address. In this mode, frames that do
not match either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For transmitting data,
an interrupt on the first received character or on every
character can be selected. The receiver automatically
deletes a" zeroes inserted by the transmitter during
character assembly. It also calculates and automatically
checks the CRC to validate frame transmission. At the
end of transmission, the status of a received frame is
available in the status registers.
Interrupts. The 510 has an elaborate interrupt scheme
to provide fast interrupt service in real-time applications. A control register and a status register in Channel
B contain the interrupt vector. When programmed to do
Z80 SIO PROTOCOLS
Figure 9
MARKING LINE
MARKING LINE
I SYNC
I
DATA
I
:!
DATA
I
CRC,
CRc 2
1
I
CRC,
CRC2
I
CRC,
CRC2
I
MONOSYNC
I
SYNC
I
It
:;
:;
I
SYNC
DATA
SIGNAL
DATA I
I
DATA
BISYNC
I DATA I
EXTERNAL SYNC
,--F_lA_G--LIA_D_D_R_ES_S.LI_ _
-"IN.;.;F...;;O~i~ATION
CRC,
I
FLAG
SDlC/HDlC/X.25
VARIABLE LENGTH SYNC CHARACTERS
Figure 10
6 BITS
DATA
8
'6
IV-24
DATA
DATA
DATA
so, the 510 can modify three bits of the interrupt vector
in the status register so that it points directly to one of
eight interrupt service routines in memory, thereby
servicing conditions in both channels and eliminating
most of the needs for a status-analysis routine.
interrupt routine itself.
CPU/DMA Block Transfer. The SID's block-transfer
mode accommodates both CPU block transfers and
DMA controllers (Z80 DMA or other designs). The blocktransfer mode uses the Wait/Ready output signal,
which is selected with three bits in an internal control
register. The Wait/Ready output signal can be programmedWAJTline in the CPU block-transfer mode or
as a READY line in the DMA block-transfer mode.
Transmit interrupts, receive interrupts and external/status interrupts are the main sources of interrupts.
Each interrupt source is enabled under program control,
with Channel A having a higher priority than Channel B,
and with receive, transmit and external/status
interrupts prioritized in that order within each channel.
When the transmit interrupt is enabled, the CPU is
interrupted by the transmit buffer becoming empty.
(This implies that the transmitter must have had a data
character written into it so it can become empty.) The
receiver can interrupt the CPU in one of two ways:
To a DMA controller, the SIOFfEAC)V output indicates
that the 510 is ready to transfer data to or from memory.
To the CPU, the WAIT output indicates that the 510 is
not ready to transfer data, thereby requesting the CPU to
extend the I/O cycle.
TYPICAL ZSO ENVIRONMENT
Figure 11
• Interrupt on first received character
• Interrupt on all received characters
Interrupt-on-first-received-character is typically used
with the block-transfer mode. Interrupt-on-all-received-characters has the option of modifying the
interrupt vector in the event of a parity error. Both of
these interrupt modes will also interrupt under special
receive conditions on a character or message basis
(end-of-frame interrupt in SDLC, for example). This
means that the special-receive condition can cause an
interrupt only if the interrupt-on-first-received-character or interrupt-on-all-received-characters mode
is selected. In interrupt-on-first-received-character, an
interrupt can occur from special-receive conditions
(except parity error) after the first-received-character
interrupt (example: receive-overrun interrupt).
.oil
,.
..
,
OMA
-
INT
ROY
lEI
-lEO
iN'!'
The main function of the external/status interrupt is to
monitor the signal transitions of the Clear To Send
(CTS), Data Carrier Detect (DCD) and Synchronization
(SYNC) pins (Figures 1 through 6). In addition, an
external/status interrupt is also caused by a CRCsending condition or by the detection of a break
sequence (asynchronous mode) or abort sequence
(SDLC mode) in the data stream. The interrupt caused by
the break/abort sequence allows the 510 to interrupt
when the break/abort sequence is detected or
terminated. This feature facilitates the proper termination of the current message, correct initialization of the
next message, and the accurate timing of the break/abort condition in external logic.
lEI
SIO
IA.
'I
ROY
DMA
~
,
ARCHITECTURE
DESCRIPTION
In a Z80 CPU environment (Figure 11), 510 interrupt
vectoring is "automatic": the 510 passes its internallymodifiable 8-bit interrupt vector to the CPU, which adds
an additional 8 bits from its interrupt-vector (I) register
to form the memory address of the interrupt-routine
table. This table contains the address of the beginning of
the interrupt routine itself. The process entails an
indirect transfer of CPU control to the interrupt routine,
so that the next instruction executed after an interrupt
acknowledge by the CPU is the first instruction of the
The internal structure of the device includes a Z80 CPU
interface, internal control and interrupt logic, and two
full-duplex channels. Each channel contains its own set
of control and status (write and read) registers, and
control and status logic that provides the interface to
modems or other external devices.
The registers for each channel are designated as
follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The register group includes five 8-bit control registers,
IV-25
two sync-character registers and two status registers.
The interrupt vector is written into an additional 8-bit
register (Write Register 2) in Channel B that may be read
through another 8-bit register (Read Register 2) in
Channel B. The bit assignment and functional grouping
of each register is configured to simplify and organize
the programming process. Table 1 lists the functions
assigned to each read or write register.
The logic for both channels provides formats,
synchronization and validation for data transferred to
and from the channel interface. The modem control
inputs, Clear To Send (CTS) and Data Carrier Detect
(DCD), are monitored by the external control and status
logic under program control. All external
control-and-status-Iogic signals are general-purpose in
nature and can be used for functions other than modem
control.
Read Register Functions
Data Path. The transmit and receive data path
illustrated for Channel A in Figure 12 is identical for
both channels. The receiver has three 8-bit buffer
registers in a FIFO arrangement, in addition to the 8-bit
receive shift register. This scheme creates additional
time for the CPU to service an interrupt atthe beginning
of a block of high-speed data. Incoming data is routed
through one of several paths (data or CRC) depending on
the selected mode and-in asynchronous modes-the
character length.
RRO
RR1
RR2
Transmit/Receive buffer status, interrupt
status and external status
Special Receive Condition status
Modified interrupt vector (Channel B only)
Write Register Functions
WRO
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Register pointers, CRC initialize, initialization
commands for the various modes, etc.
Transmit/Receive interrupt and data transfer
mode definition.
Interrupt vector (Channel B only)
The transmitter has an 8-bit transmit data buffer
register that is loaded from the internal data bus, and a
20-bit transmit sh ift reg ister that ca n be loaded from the
sync-character buffers or from the transmit data
register. Depending on the operational mode, outgoing
data is routed through one of four main paths before it is
transmitted from the Transmit Data output (TxD).
Receive parameters and control
Transmit/Receive miscellaneous parameters
and modes
Transmit parameters and controls
Sync character or SDLC address field
Sync character or SDLC flag
The system program first issues a series of commands
that initialize the basic mode of operation and then other
commands that qualify conditions within the selected
C~PU
1/0
TRANSMIT AND RECEIVE DATA PATH (CHANNEL A)
Figure 12
_
1110 OATA BUFFERI
TOCHANNELB----------------------------~~~-----------------------------
EXTERNAL STATUS LOGIC
CONTROL LOGIC. ETC.
INTERNAL DATA BUS
r--------.,
TxDA
IV-26
mode. For example, the asynchronous mode, character
length, clock rate, number of stop bits, even or odd parity
might be set first; then the interrupt mode; and finally,
receiver or transmitter enable.
Both channels contain registers that must be
programmed via the system program prior to operation.
The channel-select input (B/A) and the control/data
input (C/O) are the command-structure addressing
controls, and are normally controlled by the CPU
address bus. Figures 15 and 16 illustrate the timing
relationships for programming the write registers and
transferring data and status.
Read Registers. The 510 contains three read registers
for Channel B and two read registers for Channel A
(RRO-RR2 in Figure 13) that can be read to obtain the
status information; RR2 contains the internally-modifiable interrupt vector and is only in the Channel B
register set. The status information includes error
conditions, interrupt vector and standard
communications-interface signals.
To read the contents of a selected read register other
than RRO, the system program must first write the
pointer byte to WRO in exactly the same way as a write
register operation. Then, by executing a read
instruction, the contents of the addressed read register
can be read by the CPU.
The status bits of RRO and RR1 are carefully grouped to
simplify status monitoring. For example, when the
interrupt vector indicates that a Special Receive Condition interrupt has occured, all the appropriate error bits
can be read from a single register (RR1).
Write Registers. The 510 contains eight write registers
for Channel B and seven write registers for Channel A
(WRO-WR7 in Figure 14) that are programmed
separately to config u re the functiona I persona Iity of the
channels; WR2 contains the interrupt vector for both
channels and is only in the Channel B register set. With
the exception of WRO, programming the write registers
require two bytes. The first byte is to WRO and contains
three bits (00-02) that point to the selected register; the
second byte is the actual control word that is written
into the register to configure the 510.
WRO is a special case in that all of the basic commands
can be written to it with a single byte. Reset (internal or
external) initializes the pointer bits 00-02 to point to
WRO. This implies that a channel reset must always
point to WRO.
The 510 must have the same clock as the CPU (same
phase and frequency relationship, not necessarily the
same driver).
READ REGISTER BIT FUNCTIONS
Figure 13
READ REGISTER 0
READ REGISTER 2
*Used With External/Status
Interrupt Mode
READ REGISTER 1
1071061051041031021011
Dol
INTERRUPT
VECTOR
L-ALLSENT
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
I FIELD BITS
IN PREVIOUS
BYTE
I FIELD BITS IN
SECOND PREVIOUS
BYTE
0
0
0
0
0
0
1
2
3
4
5
6
7
8
8
8
0
0
0
1
1
1
1
0
PARITY ERROR
~_ _ _ _ ~~g::::~~~RERR~'6R
~
*Variable if Status Affects
Vector is Programmed
'Residue Data For Eight
Rx Bits/Character Programmed
_ _ _ _ _ END OF FRAME (SOLC)
Used With Special Receive Condition Mode
IV-27
WRITE REGISTER BIT FUNCTIONS
Figure 14
WRITE REGISTER 0
WRITE REGISTER 4
107/0610510410310210,1 Dol
10710610510410310210,1001
I II
I
o
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
o
,
1
o
o
1
1
o
1
o
1
o
1
o
1
0
1
2
3
4
5
6
7
o
1
0
1
0
NULLCQDE
RESET Rx CRe CHECKER
RESET Tx CRe GENERATOR
1
1
RESET Tx UNDERRUN/EOM LATCH
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1% STOP BITS/CHARACTER
o
1
o
1
o
1
o
1
III I
o
0
1
0
,
X1 CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
10710610510410310210,1001
IIL...!:::'I =I====
I
I
EXT INT ENABLE
Tx INT ENABLE
L _ _ _ _ STATUS AFFECTS VECTOR
(CH. B ONLY)
o
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (0111 1 1 1 0 FLAG)
EXTERNAL SYNC MODE
WRITE REGISTER 5
WRITE REGISTER 1
10710610.10410310210,1001
1
,
Rx INT DISABLE
Rx INT ON FIRST CHARACTER
tNT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR)
INT ON ALL FIx CHARACTERS (PARITY DOES NOT AFFECT VECTOR)
WAIT IREADY ON AIT
WAIT IREADY FUNCTION
'-----WAIT/READY ENABLE
*OrOn
Special
Condition
WRITE REGISTER 2 (CHANNEL B ONLY)
!
Tx 5
Tx 7
Tx 6
Tx 8
•
BITS {OR LESS)/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
OTR
III [[I ~i~li!i
SYNC BIT5
SYNC BIT6
SYNC BIT 7
*Also SDLC Address Field
WRITE REGISTER 3
WRITE REGISTER 7
10710610.10410310210,1001
I[[I
5
7
6
8
~~~RC ENABLE
Tx
ENABLE
SDLC/CRC·16
SEND BREAK
WRITE REGISTER 6
INTERRUPT
VECTOR
Rx
Rx
Rx
Rx
PARITY ENABLL..
PARITY EVEN/ODD
2 STOP BITS/CHARACTER
NULL CODe
SEND ABORT (SOLe)
RESET EXT/STATUS INTERRUPTS
CHANNEL REseT
ENABLE tNT ON NEXT Rx CHARACTER
RESET TxlNT PENDING
ERROR RESET
RETURN FROM INT (CH-A ONLY)
o
I
"~"
L.::=
I L- "SYNC
.. CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SoLC)
Rx CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
·For SDLC It Must Be Programmed
to "01111110" For Flag Recognition
IV-28
zao
Read Cycle. The timing signals generated by a
CPU input instruction to read a data or status byte from
the 510 are illustrated in Figure 15.
zao
Write Cycle. Figure 16 illustrates the timing and data
CPU output instruction to
signals generated by a
write a data or control byte into the 510.
zao
Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an 510 (lNT pulled Low), the
CPU sends an interrupt-acknowledge sequence (M1
Low, and lORa Low a few cycles later) as in Figure 17.
The 510 contains an internal daisy-chained interrupt
structure for prioritizing nested interrupts for the
various functions of its two channels, and this structure
can be used within an external user-defined daisy chain
that prioritizes several peripheral circuits.
zao
The I EI of the highest-priority device is termi nated High.
A device that has an interrupt pending or under service
forces its lEO Low. For devices with no interrupt
pending or under service, lEO = lEI.
To insure stable conditions in the daisy chain, all
interrupt status signals are prevented from changing
while M1 is Low. When lORa is Low, the highest
priority interrupt requestor (the one with lEI High) places
its interrupt vector on the data bus and sets its internal
interrupt-under-service latch.
READ CYCLE
Return From Interrupt Cycle. Figure 1a illustrates the
return from interrupt cycle. Normally, the
CPU
issues a RETI (return from interrupt) instruction at the
end of an interrupt service routine. RETI is a 2-byte
opcode (EO-40) that resets the interrupt-under-service
latch in the 510 to terminate the interrupt that has just
been processed. This is accomplished by manipulating
the daisy chain in the following way.
The normal daisy-chain operation can be used to detect
a pending interrupt; however, it cannot distinguish
between an interrupt under service and a pending
unacknowledged interrupt of a higher priority.
Whenever "EO" is decoded, the daisy chain is modified
by forcing High the lEO of any interrupt that has not yet
been acknowledged. Thus the daisy chain identifies the
device presently under service as the only one with an
lEI High and an lEO Low. If the next opcode byte is "40",
the interrupt-under-service latch is reset.
The ripple time of the interrupt daisy chain (both the
High-to-Low and the Low-to-High transitions) limits the
number of devices that can be placed in the daisy chain.
Ripple time can be improved with carry-look-ahead, or
by extending the interrupt-acknowledge cycle. For
further information about techniques for increasing th
number of daisy-chained devices, refer to the IV"""""""
CPU Product Specification.
zao
INTERRUPT ACKNOWLEDGE CYCLE
Figure 15
Figure 17
T,
CLOCK
CLOCK
CE. C/D. BIA
M1~~__________~~
_ _-J"+___\-___-J
I
'---U
AD _ _ _ _ _ _ _ _ _...J1L-_ __
lEI
M'-------~------
:::::::=:7
DATA _ _ _ _ _ _ _ _
DATA -------~_<
I
:\::::=
~ECTO~---
WRITE CYCLE
RETURN FROM INTERRUPT CYCLE
Figure 16
Figure 18
M1 __________
DATA _ _ _ _ _ _ _ _
IEI------
------.1
I~----
>E)(______
,
I
IEO _ _ _ _ _ _ _ _ _........
:;----
IV-29
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs with respect to GND ........................................... -0.3V to +7 .OV
Operating Ambient Temperature ................................... , ........ As Specified in Ordering Information
Storage Temperature ...... , ................................................................. -6SoC to +1S0°C
Stresses greater than those listed under Absolute Maximum Ratings maycause permanent damage tathe device. This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
2.1K
FROM OUTPUTO-_......_-..~H
UNDER TEST
• +4.7SV::::; VCC::::; +S.2SV
• GND = OV
• TA as specified in Ordering Information
All AC parameters assume a load capacitance of 100 pF
max. Timing references between two output signals
assume a load difference of SO pF max.
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
VILC
Clock Input Low Voltage
-0.3
+0.80
V
VIHC
Clock Input High Voltage
VCC -0.6
+S.S
V
VIL
Input Low Voltage
-0.3
+0.8
V
VIH
Input High Voltage
+2.0
+S.S
V
VOL
Output Low Voltage
+0.4
V
VOH
Output High Voltage
+2.4
III
Input Leakage Current
-10
IZ
3-State Output/Data Bus Input
Leakage Current
IL(SY)
SYNC Pin Leakage Current
ICC
Power Supply Current
UNIT
TEST CONDITION
V
= 2.0mA
IOH = -2S0 JJA
±10
J.l.A
O_0
R
= 1000 OHMS:
DATA LINES
R = 470 OHMS: DATA STROBE AND
INPUT PRINT LINES
+5
~
DRIVER:
o----------<~------o
CONNECTOR: AMPHENOL 57 40360 SERIES, 36-PIN
(CENTRONICS 31310019)
INTERFACE TIMING
PARALLEL DATA
I
I
..-J
DATA STROBE
I
I
1.01's J..- -.j 1.0 I's ~
(MIN) I
I (MIN)
I
I
----~~r-------------------------I
I
---J
ACKNOWLEDGE
I
I
t+I
1.0 I'S (MIN)
500 I'S (MAX)
:I
I
I
ACK DELAY
I
I
1 - - - FOR NORMAL DATA----t..~II-'- - A C K I
....1
I-ACK DELAY
I
I
FOR BUSY CONDITION
..
BUSY
~
I
I
~BUSY DELAY~
V-16
II
I
BUSY-t
Internal Controls
Auto motor control:
Turns stepping motors off when
no data is received.
Electronic top of form: Allows paper to space to top of
form when command is received.
Preset for 11 in. (279 mm) or 12 in. (305 mm) forms Opt.
VFU must be used for other form lengths.
Humidity
Operating: 20% to 90% (No condensation)
Storage: 5% to 95% (No condensation)
Normal Data ACK Delay
Input Timing ACK
BUSY DELAY
ACK DELAY
ACK
BUSY DURATION:
Line Feed
Verfical Tab (1-in.)
BUSY
CONDITION
Form Feed (11-in.)
Delete
TIMING
Bell
Select*
Deselect
Data Input
7- or 8-bit ASCII parallel; microprocessor electronics; TTL
levels with strobe.
Acknowledge pulse indicates that data was received.
INTERFACING
Electrical Requirements
50/60 Hz, 1151230 VAC; -10%/-15% of Nominal
Tappable Transformer (1 00,110,115,120,200,220,230,
240 VAC).
Printer
Physical Dimensions
Model 702
Weight: 60 Ibs. (27 Kg)
Width:
24.5 in. (622 mm)
Height: 8 in. (203 mm)
18 in. (457 mm)
Depth:
0- 1.5 Ilsec
1 - 6 Ilsec
4 Ilsec
350 - 500 Ilsec
135 - 145 msec
1.48 - 1.50 sec
160 - 400 Ilsec
0
0- 1.5 Ilsec
Unit Printer is
selected
8.33 msec/char; plus
148 msec
non-printing time/line
*No busy if inhibit prime on select option is used.
Temperature
Operating: 40° to 100°F (4.4° to 37.7°C)
Storage: -10° to 160°F (-40° to 71.1 0C)
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
LP
Mostek line printer featuring 120 cps operation, 7x7 dot
matrix, 10 cpi, and paper slew rate of 8 ips. Includes
MATRI)(TM cable, 60 Hz operation.
MK78191-1
LP-50
Same as above but for 50 Hz operation.
MK78191-2
MD-CPRT-C
MATRIX System or MDX-PIO to Centronics Line Printer Interface MK79089
cable.
V-17
V-18
MOSIEI{.
PERIPHERAL
PPG S/16-PROM Programmer
MK79181-1
FEATURES
PPG 8/16 PHOTO
o Programs, reads, and verifies 2708-, 2758-, and
271 6-type PROMs (2758 and 2716 PROMS must be
5-Volt only type)
o Interfaces to MATRIX and MDX-PIO
o Driver software included on system diskette for
FLP-80DOS
o Zero-insertion-force socket
o Power and programming indicators
DESCRIPTION
The PPG-8/16 PROM Programmer is a peripheral which
provides a low-cost means of programming 2708, 2758, or
2716 PROMs. It is compatible with Mostek's MATRIX
Microcomputer Development System and the MDX-PIO.
The PPG-8/1 6 has a generalized computer interface (two
8-bit 1/0 ports) allowing it to be controlled by other types of
host computers with user-generated driver software. A
complete set of documentation is provided with the PPG8/16 which describes the internal operation and details
user's operating procedures
The PPG-8/1 6 is available in a metal enclosure for use with
the MATRI)(TM and the MDX-PIO. Interface cables for either
the MATRIX or MDX-PIO must be purchased separately.
SOFTWARE DESCRIPTION
The driver software accomplishes four basic operations.
These are (1) loading data into host computer memory, (2)
reading the contents of a PROM into host computer
memory, (3) programming a PROM from the contents of the
host computer memory, and (4) verifying the contents of a
PROM with the contents of the host computer memory.
The driver software is provided on the FLP-80DOS system
diskette. The user documentation provided with the PPG8/16 fully explains programming procedures to enable a
user to develop a software driver on a different host
computer.
V-19
PPG8/16 BLOCK DIAGRAM
J1
CONNECTOR
2
A-...L....L.~
AS - A9 (270S/275S)
AS - A 10 (2716)
TO
HOST
COMPUTER
BSTB
0 1 Os
275S1
MK270S1
MK2716
SOCKET
MODE
SELECT
CIRCUIT
J2
+12VDC
CONNECTOR
TO
+5, +12, -12
POWER SUPPLY
+5VDC
GND
-12VDC
PROGRAM
PULSE
CONVERTER
",~U~~OR
to
+27.5 VDC
I I
PROGRAM
LED
STEP-UP
VOLTAGE
REGULATOR
-5VDC +5VDC
+12VDC
INTERFACE
OPERATING TEMPERATURE
25-pin control connector (0 type)
40-pin control connector (0.1-in. centers card edge)
for A10-80F, SOB-80, 508-50170, or MATRI)(TM
12-pin power connector (0.156-in. centers card edge)
All control signals are TTL-compatible
DOC -60°C
POWER REQUIREMENTS
PROGRAMMING TIME
2708 - 2.5 minutes
2758 - 0.9 minutes
2716 - 1.8 minutes
+ 12 VOC at 250mA typical
+5 VOC at 1OOmA typical
-12 VOC at 50mA typical
V-20
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
PPG-S/16
PROM Programmer for 270S1275S12716 PROMs
with Operations Manual for interface with MATRIX.
MK790S1-1
MATRIX to PPG-S/16
PPG-S/16 Interface Cable for MATRIX
MK79090
MD-PPG-C
PPG-S/16 Interface Cable for MDX-PIO
MK77957
PPG-S/16 Operations Manual
MK79603
*NOTE: The PPG-S/16 will only program the 270S, 275S, and 2716 PROMs. The 275S and 2716 are 5 Volt only type
PROMs. THE PPG-S/16 WILL NOT PROGRAM THE TI2716 MULTIPLE-VOLTAGE 2K x S PROM.
V-21
V-22
MOSTEI{.
SOFlWARE DISK BASED
ANSI BASIC Software Interpreter
MK78157
FEATURES
o Meets ANSI standard on BASIC (X3.60 - 1978)
o
Occupies only 23K bytes, not including operating system
o
Direct access to CPU I/O Ports
o
Supports console and line printer 110
o
Ability to read or write any memory location (PEEK,
POKE)
o
Allows console output to be redirected to the line printer
o
WHILE ... WEND structured construct
o
Arrays with up to 255 dimensions
o
o
Dynamic allocation and deallocation of arrays
Programs can be saved on disk in a protected format that
cannot be listed on console
o
IF ... THEN ... ELSE and IF ... GO TO (both it's may be
nested)
DESCRIPTION
o
Direct (immediate) execution of statements
o
Error trapping, with error messages in English
o
Four variable types: Integer, string, real and doubleprecision real
o
Long variable names significant up to 40 characters
o
Full PRINT USING capabilities for formatted output
o
Extensive program editing facilities
o
Trace facililties
o
Can call any number of assembly-language subroutines
o
Boolean (logical) operations
o
Supports up to six sequential and random access files on
floppy disk
o
Variable record length in random access files from one to
128 bytes/record
o
Complete set of file manipulation statements
Mostek ANSI BASIC is an extensive implementation of
Microsoft BASIC for the Z80 microprocessor. Its features
are comparable tothe BASICs found on minicomputers and
large mainframes. Mostek ANSI BASIC is among the fastest
microprocessor BASICs available. Designed to operate on
Mostek Systems with FLP-80DOS V2.1 and with 48K bytes
or more memory, Mostek BASIC provides a sophisticated
software development tool.
Mostek ANSI BASIC is implemented as an interpreter and is
highly suitable for user-interactive processing. Programs
and data are stored in a compressed internal format to
maximize memory utilization. In a 64K system, 28K of
user's program and data storage area are available.
Unique features include long variable names, substring
assignments and hexadecimal and octal constants. Many
other features ease the task of programming complex
functions. The Programmer is seldom limited by array size
(up to 255 dimensions, with run-time allocation and
deallocation) or 110 restrictions. Full PRINT USING
capabilities allow formatted output. while both input and
output may be performed with multiple sequential and
random files on floppy disk as well as with the CPU I/O
ports. Editing, error trapping, and trace facilities greatly
simplify program debugging.
V-23
Commands:
AUTO
FILES
NEW
SAVE
EDIT
MERGE
RUN
WIDTH
CLEAR
LIST
NULL
SYSTEM
CO NT
LLiST
RENUM
TRON
DELETE
LOAD
RESET
TROFF
CHAIN
DEFSNG
ERASE
IF ... THEN(ELSE)
ON ... GOTO
RESUME
COMMON
DEFSTR
ERROR
IF ... GOTO
OPTION BASE
STOP
DEF DBL
DEFUSR
FOR .. NEXT
LET
RANDOMIZE
SWAP
DEF FN
DIM
GOSUB ... RETURN
ON ERROR GOTO
FIELD
LINE INPUT
NAME
PRINT#
RESET
GET
LINE INPUT#
OPEN
PRINT# USING WRITE
RSET
INPUT
LPRINT
OUT
PUT
WRITE#
>
<
<=
MOD
IMP
NOT
EQU
AND
Program Statements:
CALL
DEFINT
END
GOTO
ON ... GOSUB
REM
WHILE ... WEND
Input/Output Statements:
CLOSE
INPUT#
LPRINT USING
PRINT
READ
DATA
KILL
LSET
PRINT USING
RESTORE
Operators:
+
1\
"-
>=
<>
OR
XOR
/
Arithmetic Functions:
ABS
EXP
LOG
USR
ATN
ERR
RND
VARPTR
CDBL
ERL
SGN
CINT
FIX
SIN
COS
FRE
SQR
CSNG
INT
TAN
CHR$
OCT
VAL
HEX$
RIGHT$
INSTR
SPACES
LEFT
SPC$
LEN
STR$
CVD
LOF
PEEK
DSKF
LOG
POKE
EOF
LPOS
POS
INP
MKD$
TAB
String Functions:
ASC
MID$
STRINGS
Input/Output Functions:
CVI
INPUT$
MKI$
WAr.
CVS
LOC
MKS$
V-24
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
Mostek ANSI
BASIC
BASIC INTERPRETER high-level language to run
on FLP-80DOS. Requires 48K or more bytes of memory.
MK78157
BASIC Operation Manual Only
MK79708
In order to receive Mostek ANSI BASIC, the Mostek BASIC
non-disclosure agreement must be signed and returned
with each purchase order.
V-25
V-26
MOSI£I(.
SOFTWARE DISK BASED
FORTRAN IV Compiler
MK78158
FORTRAN IV COMPILER PHOTO
FEATURES
o All of ANSI standard FORTRAN IV (X3.9-1966) except
complex data type
o
Generates relocatable linkable object code
o
Subroutines may be compiled separately and stored in a
system library
o
Compiles several hundred statements per minute in a
single pass
o
Enhancements include
1.
2.
3.
4.
5.
6.
7.
8.
LOGICAL variables which can be used as integer
quantities
LOGICAL DO loops for tighter, faster execution of
small-valued integer loops
Mixed-mode arithmetic
Hexadecimal constants
Literals and Holleriths allowed in expressions
Logical operations on integer data .. AND., .OR., .NOT.
and .x0R. can be used for 16-bit or 8-bit Boolean
operations
READ/WRITE End-of-File or Error Condition transfer.
END=n and ERR=n (where n is the statement
number) can be included in READ or WRITE
statements to tra nsfer control to the specified
statement on detection of an error or end-of-file
condition
ENCODE/DECODE for FORMAT operations to
memory
o
Long descriptive error messages
o
Extended optimizations
o
Z80-assembly-language subprograms may be called from
FORTRAN programs
DESCRIPTION
Mostek's FORTRAN IV Compiler package provides new
capabilities for users of Z80-based microcomputer systems.
Mostek FORTRAN is comparable to FORTRAN compilers on
large mainframes and minicomputers. All of ANSI Standard
FORTRAN X3.9-1966 is included except the COMPLEX data
type. Therefore, users may take advantage of the many
applications programs already written in FORTRAN.
Mostek FORTRAN IV is unique in that it provides a
microprocessor FORTRAN development package that
generates relocatable object modules. This means that only
the subroutines and system routines required to run
FORTRAN programs are loaded before execution.
Subroutines can be placed in a system library so that users
can develop a common set of subroutines that are used in
their programs. Also, if only one module of a program is
changed, it is necessary to re-compile only that module.
The standard library of subroutines supplied with FORTRAN
includes:
ABS
lABS
DABS
AINT
INT
IDINT
MOD
AMOD
AMAXO
AMAX1
MAXO
MAX1
DMAX1
AMINO
AMIN1
MINO
MIN1
DMIN1
FLOAT
IFIX
SIGN
ISIGN
DSIGN
DIM
101M
SNGL
DBLE
EXP
DEXP
DLOG
AL0G10
ALOG
DLOG10
SIN
DSIN
COS
DCOS
TANH
DSORT
SORT
ATAN
DATAN2
DATAN
ATAN2
DMOD
PEEK
INP
POKE
OUT
V-27
showing the addresses assigned to labels, variables and
constants.
LINKER
The library also contains routines for 32-bit and 64-bit floating
point addition, subtraction, multiplication, division, etc. These
routines are among the fastest available for performing these
functions on the Z80.
A relocating linking loader (LlNK-80) and a library manager
(LlB-BO) are included in the Mostek FORTRAN package.
A minimum system size of 48K bytes (including FLP-80DOS)
is required to provide efficient optimization. The Mostek
FORTRAN compiler optimizes the generated object code in
several ways:
1.
Common subexpression elimination. Common subexpressions are evaluated once, and the value is
substituted in later occurrences of the subexpression.
2.
Peephole Optimization. Small sections of code are
replaced by more-compact, faster code in special cases.
LlNK-80 resolves internal and external references between
the object modules loaded and also performs library searches
for system subroutines and generates a load map of memory
showing the locations of the main program, subroutines and
common areas.
LIBRARY MANAGER
3.
Constant folding. Integer' constant expressions are
evaluated at compile time.
4.
Branch Optimizations. The number of conditional
jumps in arithmetic and 10gicailFs is minimized.
LlB-80 allows users to customize libraries of object modules.
LlB-80 can be used to insert, replace or delete object modules
within a library, or create a new library from scratch. Library
modules and the symbol definitions they contain may also be
listed.
XCPM UTILITY
Long descriptive error messages are another feature of the
compiler. For instance:
?Statement unrecognizable
is printed if the compiler scans a statement that is not an
assignment or other FORTRAN statement. The last twenty
characters scanned before the detected error are also printed.
A utility program (XCPM) is included which allows the user to
copy FORTRAN source programs from CP/M diskettes to
FLP-80DOS diskettes. At this point the programs can be
compiled using the Mostek FORTRAN compiler.
As an option, the compiler generates a fully symbolic listing of
the machine language to be generated. At the end of the
listing, the compiler produces an error summary and tables
FTRANS allows the user to convert object programs produced
by the Mostek Z80 assembler to a form that is linkable to
FORTRAN programs.
FTRANSUTILITY
DESIGNATOR
DESCRIPTION
PART NO.
Mostek FORTRAN IV
FORTRAN IV high-level compiler to run on FLP-80DOS.
Requires 48K bytes of RAM. Includes Operations Manual.
MK78158
Mostek FORTRAN IV Operations Manual only
MK79643
V-28
MOSIEI(.
i
SOFTWARE DISK BASED
FLP-80DOS
MK78142, MK77962
INTRODUCTION
FLP-80DOS BOARD PHOTO
The Mostek FLP-aODOS software package is designed for
the Mostek dual floppy disk zao Development System or an
MD board system. Further information on this system can
be found in the MATRI)(TM Data Sheet. FLP-aODOS
includes:
o
o
o
o
o
o
o
o
Monitor
Debugger
Text Editor
zao Assembler
Relocating Linking Loader
Peripheral Interchange Program
Linker
A Generalized I/O System For Peripherals
These programs provide state-of-the-art software for
developing zao programs as well as establishing a firm
basis for OEM products.
MONITOR
The Monitor provides user interface from the console to the
rest of the software. The user can load and run system
programs, such as the Assembler, using one simple
command. Programs in object and binary format can be
loaded into and dumped from RAM. All I/O is done via
channels which are identified by Logical Unit Numbers. The
Monitor allows any software device handler to be assigned
to any Logical Unit Number. Thus, the software provides
complete flexibility in configuring the system with different
peripherals. The Monitor also allows two-character
mnemonics to represent 16-bit address values. Using
mnemonics simplifies the command language. Certain
mnemonics are reserved for I/O device handlers such as
'OK' for the flexible disk handler. The user can create and
assign his own mnemonics at any time from the console,
thus simplifying the command language for his own use.
The Monitor also allows "batch mode operation" from any
input device or file.
The Monitor commands are:
$ASSIGN assign a Logic Unit Number to a device.
$CLEAR remove the assignment of a Logical Unit
Number to a device.
$RTABLE print a list of current Logic Unit Numberto-Device assignments.
$DTABLE -
print default Logical Unit Number-toDevice assignments.
$LOAD load object modules into RAM.
$GTABLE print a listing of global symbol table.
$GINIT initialize global symbol table.
$DUMP dump RAM to a device in object format.
$GET load a binary file into RAM from disk.
$SAVEsave a binary file on disk.
$BEGIN start execution of a loaded program.
$INIT initialize disk handler.
enter DDT debug environment.
$ODT IMPLIED RUN COMMAND - get and start execution of a
binary file.
DESIGNER'S DEVELOPMENT TOOL - DDT
The DDT debugger program is supplied in a combination of
... on the FLP-aODOS diskette.... and absolute zao
programs. Standard commands allow displaying and
modifying memory and CPU registers, setting breakpoints,
and executing programs. Mnemonics are used to represent
zao registers, thus simplifying the command language.
V-29
•!
The allowed commands are:
BInsert a breakpoint in user's program.
CCopy contents of a block of memory to another
location in memory.
EExecute a program.
FFill an area of RAM with a constant.
H16-bit hexadecimal arithmetic.
LLocate and print every occurrence of an 8-bit
pattern.
M Display, update, or tabulate the contents of
memory.
PDisplay or update the contents of a port.
RDisplay the contents of the user's register.
SHardware single step - requires Mostek's AIM-80
board or AIM-Z80A board.
W Software single step.
VVerify memory (compare two blocks and print
differences).
TEXT EDITOR -EDIT
The FLP-80DOS Editor permits random-access editing of
ASCII character strings. The Editor works on blocks of
characters which are rolled in from disk. It can be used as a
line-or character-oriented editor. Individual characters may
be located by position or context. Each edited block is
automatically rolled out to disk after editing. Although the
Editor is used primarily for creating and modifying Z80
assembly language source statements, it may be applied to
any ASCII text delimited by "carriage returns".
The Editor has a pseudo-macro command processing
option. Up to two sets of commands may be stored and
processed at any time during the editing process. The Editor
allows the following commands:
An Advance record pointer n records.
Bn Backup record pointer n records.
Cn dS1 dS2d - Change string S1 to string S2 for n
occurrences.
On Delete the next n records.
En Exchange current records with records to be
inserted.
Fn If n = 0, reduce printout to console device (for
TIY and slow consoles).
Insert records.
1Ln Go to line number n.
Mn Enter commands into one of two alternate
command buffers (pseudo-macro).
QQuit - Return to Monitor.
Sn dS1 d -Search for nth occurrence of string S1.
TInsert records at top of file before first record.
Output n records to console device.
Vn Wn Output n records to Logical Unit Number five
(LUN 5) with line numbers.
Xn Execute alternate command buffer n.
mnemonics and pseudo-ops and outputs an assembly
listing and object code. The assembly listing shows address,
machine code, statement number, and source statement.
The code is in industry-standard hexadecimal format
modified for relocatable, linkable assemblies.
The Assembler supports conditional assemblies, global
symbols, relocatable programs, and a printed symbol table.
It can assemble any length program, limited only by a
symbol table size of over 400 symbols. Expressions
involving arithmetic and logical operations are allowed.
Although normally used as a two-pass assembler, the
Assembler can also be run as a single-pass assembler or as
a learning tool. The following pseudo-ops are supported:
COND
DEFB
DEFL
DEFM
DEFS
DEFW
END
ENDC
ENDIF
EQU
GLOBAL
IF
INCLUDE
NAME
ORG
PSECT
EJECT
TITLE
LIST
NLiST
same as IF.
define byte.
define label.
define message (ASCII).
defi ne storage.
define word.
end statement.
same as ENDIF.
end of conditional assembly.
equate label.
global symbol definition.
conditional assembly.
include another file within an assembly.
program name definition.
program origin.
prog ra m section defi n ition.
eject a page of listing.
place heading at top of each page of listing.
turn listing on.
turn listing off.
RELOCATING LINKING LOADER - RLL
The Mostek FLP-80DOS Relocating Linking Loader
provides state-of-the-art capability for loading programs
into memory. Loading and linking of any number of
relocatable or nonrelocatable object modules is done in one
pass. A non-relocatable module is always loaded at its
starting address as defined by the ORG pseudo-op during
assembly. A relocatable object module can be positioned
anywhere in memory at an offset address.
The Loader automatically links and relocates global symbols
which are used to provide communication or linkage
between program modules. As object modules are loaded, a
table containing global symbol references and definitions is
built up. The symbol table can be printed to list all global
symbols and their load address. The number of object
modules which can be loaded by the Loader is limited only
by the amount of RAM available for the modules and the
symbol table.
zao ASSEMBLER - ASM
The FLP-80DOS Assembler reads standard Z80 source
The Loader also loads industry-standard non-relocatable,
non-linkable object modules.
V-3~
LINKER - LINK
INPUT10UTPUT CONTROL SYSTEM - 10CS
The Linker provides capability for linking object modules
together and creating a binary (RAM image) file on disk. A
binary file can be loaded using the Monitor GET or IMPLIED
RUN command. Modules are linked together using global
symbols for communication between modules. The linker
produces a global symbol table and a global cross reference
table which may be listed on any output device.
The first package is called the 1/0 Control System (lOCS).
Th is is a genera lized blocker I deblocker wh ich ca n interface
to any device handler. Input and output can be done via the
10CS in any of four modes:
1. Single-byte transfer.
2. Line at a time, where the end of a line is defined by
carriage return.
3. Multibyte transfers, where the number of bytes to be
transferred is defined as the logical record length.
4. Continuous transfer to end-of-file, which is used for
binary (RAM-image) files.
The Linker also provides a library search option for all global
symbols undefined after the specified object modules are
processed. If a symbol is undefined, the Linker searches the
disk for an object file having the file-name of the symbol. If
the file is found, it is linked with the main module in an
attempt to resolve the undefined symbol.
PERIPHERAL INTERCHANGE PROGRAM - PIP
The Peripheral Interchange Program provides complete file
maintenance facilities for the system. In addition, it can be
used to copy information from any device orfile to any other
device or file. The command language is easy to use and
resembles that used on DEC minicomputers. The following
commands are supported:
COMMAND
APPEND
COpy
DIRECT
ERASE
FORMAT
INIT
RENAME
STATUS
QUIT
FUNCITON
Append files.
Copy files from any device to another
device or file.
List Directory of specified Disk Unit.
Delete a file.
Format a disk.
Initialize the disk handler.
Rename a file.
List number of used and available sectors
on specified disk unit.
Return to Monitor.
The first letter only of each command may be used.
The 10CS provides easy application of 110 oriented
packages to any device. There is one entry point, and all
parameters are passed via a vector defined by the calling
program. Any given handler defines the physical attributes
of its device which are, in turn, used by the 10CS to perform
blocking and deblocking.
FLOPPY DISK HANDLER - FDH
The Floppy Disk Handler (FDH) interfaces from the 10CS to a
firmware controller for up to four floppy disk units. The FDH
provides a sophisticated command structure to handle
advanced OEM products. The firmware controller interfaces to Mostek's FLP-80E Controller Board. The disk
format is IBM 3740 soft sectored. The software can be
easily adapted to double-sided and double-density disks.
The Floppy Disk Handler commands include:
- erase file
- create file
- open file
- close file
- rename file
rewind file
read next n sectors
reread current sector
read previous sector
- skip forward n sectors
- skip backward n sectors
- replace (rewrite) current sector
- delete n sectors
DISK OPERATING SOFTWARE
The disk software, as well as being the heart of the MATRIX
development system, can be used directly in OEM
applications. The software consists of two programs which
provide a complete disk handling facility.
V-31
The FDH has advanced error recovery capability. It supports
a bad sector map and an extensive directory which allows
multiple users. The file structure is doubly-linked to
increase data integrity on the disk, and a bad file can be
recovered from either its start or end.
FLP·aO DOS BLOCK DIAGRAM
FLP80DOS
MONITOR
-
+
t
t
t
DEBUGGER
(DDT)
TEXT
EDITOR
(EDIT)
Z80
ASSEMBLER
(ASM)
t
t
t
-- --- -.- -- -- --
t
RELOCATING
LINKAGE
LOADER
(RLL)
*
PERIPHERAL
INTERCHANGE
PROGRAM
(PIP)
;
;
LINKER
(LINK)
OEM
APPLICATION
j
t
1
1
-- - -- -- -- -- -- -- -- -- -
-
1/0 CONTROL
SYSTEM
(lOCS)
t
~
1
CONSOLE
DEVICE
HANDLER
LINE
PRINTER
HANDLER
+
FLOPPY DISK
HANDLER
(FDH)
;
+
HARDWARE
UART
HARDWARE
PIO
t
f
CONSOLE
LINE
PRINTER
L---
1
OTHER
DEVICE
HANDLERS
DISK
CONTROLLER
FIRMWARE
DD
-
CLOPPY DISK UNITS)
AND
FLP-80 BOARD
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
FLP-80DOS
SDE based development system software (SD PROMs)
MK78142
FLP-80DOS
MD based development system software (MD PROMs)
MK77962
FLP-80DOS Operations Manual Only
MK78557
V-32
Z80 MICROCOMPUTER SOFTWARE SUPPORT
FORTRAN IV Cross Assembler (XFOR-80)
FEATURES
D
ANSI-FORTRAN IV Source
D
Executes on most 8-32 bit wQrd length machines
D
Cross Assembler is machine independent for:
Character representation (ASCII or BCD)
Numerical representation (1 's or 2's
complement)
D
I/O logical device assignments are user definable
D
2 pass assembly easily accomodated if no
secondary storage is available
D
Memory required: 20K words (typical)
D
Assembles all standard Z80 source statements
and MACROs
D
Size of program to be assembled is limited only
by memory available for symbol table.
D
Includes the following pseudo-ops:
·ORG
• EQU
• DEFL
• DEFM
• DEFB
.DEFW
• DEFS
• END
• MACR
• ENDM
DESCRIPTION
Program Origin
Equate
Define Label ('Set')
Define Message (ASCII Text)
Define Byte
Define Word
Define Storage
End Statement
MACRO Definition
End MACRO Definition
accomodate reading of the user input for the second
phase of the assembly.
ORDERING INFORMATION
The XFOR-80 is a Cross Assembler for assembling
Z80 source programs into the corresponding machine
code for the Z80 microprocessor.
The XFOR-80 Cross Assembler is written in ANSI
FORTRAN IV. It may be compiled and executed on
any computer system which has at least a 20K words
memory for program storage. The Cross Assembler
is independent of machine character representation
(ASCII, BCD, etc.) and numerical representation
(2's complement, 1's complement, etc.) Logical
device assignments are set up in the source of the
main program module, and may be easily changed to
suit the installation. Also, if no secondary storage
is available the main program may be changed to
V-33
The XFOR-80 is available directly from MOSTEK
by filling out a copy of the Software Licensing
Agreement printed on the back of this data sheet
and returning it with the appropriate payment
on Customer Purchase Order to:
MOSTEK CORPORATION
Microprocessor Systems Dept.
1215 West Crosby Road
Carrollton, Texas 75006
Order Number
Description
MK 78117
X FOR-80
STANDARD SOFTWARE LICENSE AGREEMENT
All Mostek Corporation products are sold
on condition that the Purchaser agrees to
the following terms:
1.
The Purchaser agrees not to sell, provide, give away, or otherwise make available to any unauthorized
persons, all or any part of, the Mostek software products listed below; including, but not restricted
to: object code, source code and program listings.
2.
The Purchaser may at any time demonstrate the normal operation of the Mostek software product
to any person.
3.
All software designed, developed and generated independently of, and not based on, Mostek's software by purchaser shall become the sole property of purchaser and shall be excluded from the
provisions of this Agreement. Mostek's software which is modified with the written permission of
Mostek and which is modified to such an extent that Mostek agrees that it is not recognizable as
Mostek's software shall become the sole property of purchaser.
4.
Purchaser shall be notified by Mostek of all updates and modifications made by Mostek for a one·
year period after purchase of said Mostek software product. Updated and/or modified software and
manuals will be supplied at the current cataloged prices.
5.
In no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever,
direct or indirect, regardless of whether such arises out of the law of torts or contracts, or Mostek's
negligence, including incidental damages, consequential damages and lost profits, arising out of or
connected in any manner with any of Mostek's software products described below.
6.
MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITTEN,
ORAL, EXPRESSED OR IMPLIED (INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY AND WARRANTIES ARISING FROM COURSE
OF DEALING OR USAGE OF TRADE) WITH RESPECT TO THE SOFTWARE DESCRIBED
BELOW.
The Following Software Products Subject To this Agreement:
Order Number
Description
Price*
Ship To: _ _ _ _ _ _ _ _ _ _ _ __
Bill To: _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Method of Shipment:
Customer P.O. Number _ _ _ _ _ _ _ _ ___
Agreed To:
PURCHASER
MOSTEK CORPORATION
By: __________________ By: ________________________________
Title: _ _ _ _ _ _ _ _ _ _ _ _ _ _ Title: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Date:
Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
*Prices Subject To Change Without Notice
V-34
MOSIEI(.
SOFTWARE DISK BASED
LIB-SO-V1
MK78164
FEATURES
o Includes 23 useful subroutines and programs for the
Z80, including:
• Lawrence Livermore Lab's Basic
• Generalized sort program for up to eight fields per
record
• 8080 - Z80 source-code converter
• Fast disk-to-disk copy utility
• Hexadecimal Dump Utility to dump memory on files
• Assembly Language Formatter Utility to format Z80
source into columns
• Word Processor Program Version 2.0, used to format
documents
• Disk Recovery Utility used to recover bad disk files
o
All programs are supplied in source, object, and binary
format with complete documentation on a standard FLP80DOS diskette
o
Requires FLP-80DOS Version 2.0 or higher
DESCRIPTION
The Mostek FLP-80DOS Software Library is a collection of
programs of general utility that run under FLP-80DOS
Version 2.0 or higher. These programs are used quite
extensively at Mostek. They are being offered in source
format on diskette so that the user may not only use them as
supplied, but may use them as a base for individuallytailored software.
This software library differs from other libraries in that all
programs in the library have been developed or modified
in-house. All programs in the library are in use at Mostek
and all have some utility.
The FLP-80DOS Software Library Volume 1 consists of a
User's Guide and two diskettes containing the source and
binary (or object for subroutines) forms for each one of the
twenty-three included programs. In order to reduce the cost
of the library, printed source listing are not supplied. The
user can obtain a source listing easily by assembling the
required source program. A brief User's Guide is a part of
each program source.
The FLP-80DOS Software Library is a "Level 2" product.
"Level 2" software products are supplied by Mostek but are
not supported in the areas of technical assistance or
updates.
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
LIB-SO Volume 1
Software Library including source, object, and binary
formats on diskette, and a printed user's guide.
MK78164
Software Library Operation Manual Only
MK79621
V-35
V-36
MOSTEI{.
SOFlWARE DISK BASED
MACRO-SO
MK78165
FEATURES
D Listing and object modules can be output on disk files or
any device.
D Assembles standard Z80 instruction set to produce
D Compatible with other Mostek Z80 assemblers and FLP-
relocatable, linkable, object modules
D Provides nested conditional assembly, an extensive
expression evaluation capability, and an extended set of
assembler pseudo-ops:
ORG
EQU
DEFL
DEFM
DEFB
DEFW
DEFS
END
GLOBAL
NAME
PSECT
IF/ENDIF
INCLUDE
L1ST/NLIST
CLIST
ELIST
EJECT
TITLE
D
- origin
- equate
- set/define macro label
- define message
- define byte
- define word
- define storage
- end of program
- global symbol definition
- module name definition
- program section definition
- conditional assembly
- include another file in source module
- list on/off
- code listing only of macro expansions
- list/no list of macro expansions
- eject a page of listing
- place title on listing
80DOS Version 2.0 or higher. Requires 32K or more of
system RAM.
DESCRIPTION
MACRO-80 is an advanced upgrade from the FLP-80DOS
Assembler (ASM). In addition to its macro capabilities, it
provides for nested conditional assembly and allows symbol
lengths of any number of characters. It supports global
symbols, relocatable programs, a symbol cross-reference
listing, and an unused-symbol reference table. MACRO-80
is upward compatible with all other Mostek Z80
assemblers.
The Mostek Z80 Macro Assembler (MACRO-80) is
designed to run on the Mostek Dual-Disk Development
System with 32K or more of RAM. It requires FLP-80DOS,
Version 2.0 or higher. Macro pseudo-ops include the
following:
MACRO/MEND
MNEXT
MIF
Provides options for obtaining a printed cross-reference
listing, terminating after pass one if errors are
encountered, redefining standard Z80 opcodes via
macros, and obtaining an unused-symbol reference
table.
D Provides the most advanced macro handling capability in
the microcomputer market which includes:
- optional arguments
- default arguments
- looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation
- conditional expansion based on symbol definition
- call-by-value facility
- expansion of code-producing statements only
- expansion of macro-call statement only
MGOTO
MEXIT
MERROR
MLOCAL
- define a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label
Predefined macro-related parameters include the following:
%NEXP
%NARC
#PRM
%NPRM
%NCHAR
- current number of this expansion
- number of arguments passed to
expansion
- expand last-used argument
- number of last-used argument
- number of characters in
argument
The operations manual describes in detail all facilites
available in MACRO-80 and provides a host of examples
and sample print-outs.
V-37
ORDERING INFORMATION
D ESIGNATOR
DESCRIPTION
PART NO.
M ACRO-80
Z80 Macro Assembler, binary program supplied on a standard
MK78165
FLP-80DOS diskette, with Operations Manual.
MACRO-80 Operations Manual
V-38
MK79635
MOSI 'EI{.
DEVELOPMENT SYSTEMS EMULATION BOARDS
AIM-Z80BE
MK78205
HARDWARE FEATURES
AIM-zeOSE SYSTEM PHOTOGRAPH
o
Direct interface to Mostek's development system
o
In-circuit emulation of 2.5, 4.0, and 6.0 MHz
microprocessors.
o
Real-time execution (6 MHz - no wait states)
o
Flexible breakpoints (hardware and eight single-byte
software)
o
Single-step execution
o
32K bytes emulation RAM
o
Memory Mappable into Target system in 256 byte blocks
o
Illegal write to memory detection
o
Nonexistent memory access detect
o
Forty-eight dhannel by 1024 words history memory
o
Event counter
zao
space or ports are used and all signals including RESET, JNi
and NMI are functional during emulation.
Single-step circuitry allows the user to execute Target
instructions one at a time to see the exact effect of each
instruction. Single step is functional in ROM as well as
RAM.
o Delay counter
o
Execution T-state timer
o Keyboard escape function
Sixteen K bytes of emulation RAM may be mapped into the
Target memory map at any desired address so that software
may be developed even before Target memory is available.
SOFTWARE FEATURES
Breakpoint-detect circuitry allows real-time execution to
proceed to any desired point in the user's program and then
terminate with all registers and status information saved so
that execution may later be resumed. Real-time execution
may also be terminated at any time by enabling the Escape
Key. EVENT and DELAY counters give added flexibility for
viewing the exact point of interest in the user's program.
o Simple-to-use, single character commands
o Flexible display format includes disassembly of opcodes
o System configuration parameters stored on disk for
future use
DESCRIPTION
A 4S-channel history circuit will simultaneously record any
bus transaction which the user may desire to see. The
address bus, data bus and control signals plus eighteen
external probes which can be used to monitor the Target
system's circuitry at other points are recorded by the History
circuit.
AIM-ZSOBE is an advanced development tool which
provides debug assistance for both software and hardware
microprocessor. Use of
via in-circuit emulation of the
the AIM-ZSOBE is completely transparent to the user's final
system configuration (referred to as the Target). No memory
zao
*Trademark of Mostek Corporation
V-39
AIM-Z80SE INITIALIZATION
EXAMPI.E 1
$AIMl80{CR)
(MR)
-tS(D)
where: tc = Clock period
tD Liii(M R) = iiifREQ delay from falling edge of clock
tS(D)
= Data Setup time to falling edge of clock
let: tc = 400ns; tDL (MR) = lOOns; ts (D) iii = 60ns
then: tACCESS MEMORY READ = 640ns'
The access times computed in equations 1 and 2 are
overall worst case access times required by the CPU.
The overall access times must include all TTL buffer
delays and the access time for the memory device.
For example, a typical dynamic memory design
would have the following characteristics, (see
Figure 2).
The example in Figure 2 shows an overall access time
of 336ns. This would more than satisfy the 45Dns
required for the op code fetch and the 64Dns required
for a memory read.
CPU MREQ buffer delay ........... , .. 12ns (8T97)
Memory gating and timing delays . . . . . . . . . . . . . 40ns
Memory device access time .... 250ns (M K4027 14116-4)
Memory data bus buffer delay .......... 17ns (BT2B)
CPU data bus buffer delay . . . . . . . . . . . . . 17ns (BT2B)
336ns
(1) tACCESS OP CODE= 3(tc/2)-tDLiii (MR) -tScp(D)
OP CODE FETCH TIMING
Figure la.
VAll D REFRESH
ADDRESS AD-AS
AO-AI~
Mm
-r----.
RFSH -r---~-------'r-~
t ClCCt . . op code
DO-D7
.st (0)
450,,,
VI-8
MEMORY READ TIMING
Figure 1b.
_ _ - - - 400ns
Ie
/
AO-AI5
VALID MEMO RY ADDRESS AO-AI5
lOOns _
\
tDL1(MR)
1\
Isf (0)_ 60ns
00-07
-
L,oc,... m,mo,
640ns
MEMORY WRITE TIMING
Figure 1c.
AO-AI5
ADDRESS
90ns -
-
AO-AI5
fDLT(WRI
WR
IW(WRL)
2000s
10(01
-360ns--_~
00-07
DATA OUT
VI-9
zao REFRESH CONTROL AND TIMING
One of the most important features provided by the
for interfacing to dynamic memories is the
execution of a refresh cycle every time an op code
fetch cycle is performed. By placing the refresh cycle
in the op code fetch, the
does not have to allocate time in the form of "wait states" or by
"stretching" the clock to perform the refresh cycle.
I n other words, the refresh cycle is "totally transparent" to the CPU and does not decrease the system
throughput (see Figure 1a). The refresh cycle is
transparent to the CPU because, once the op code
has been fetched from memory during states T 1
and T2, the memory would normally be idle during
states T 3 and T 4.
(1)
(2)
(3)
(4)
zao
zao
Therefore, by placing the refresh in the T 3 and T 4
states of the op code fetch, no time is lost for refreshing dynamic memory. The critical timing parameters
involving the
and dynamic memories during
the refresh cycle are: tw(MRH) and tw(MRL)' The
parameter known as tw(MRH) refers to the time that
MREQ is high during the op code fetch between the
fetch of the op code and the refresh cycle. This time
is known as "precharge" for dynamic memories and is
necessary to allow certain internal nodes of the RAM
to be charged-up for another memory cycle. The
equation .for the minimum tW(MRH) time period is:
Prolonged reset> 1ms
Prolonged wait state operation> 1ms
Prolonged bus acknowledge (DMA) > 1ms
clock of 1.216 MHz for 16K RAMs
.608 MHz for 4K RAMs
<
<
zao
The clocks rate in number 4 are based on the
continually executing the worst case instruction
which is an EX (SP), HL that executes in 19 T
states. Therefore, by operating the
at or above
these clocks frequencies, the user is ensured that the
dynamic memories in the system will be refreshed
properly.
zao
Remember to refresh memory properly, the
must be able to execute op codes!
zao
DELAY FOR A TYPICAL MEMORY SYSTEM
Figure 2.
MK4027-4/MK4116-4
250n5 ACCESS
oCIQ ns
zao
DIN
Dour
00-07
(3)
where:
let:
then:
tW(MRH) = tW( H) + tf -30
tW( H) is clock pulse width high
tf is clock fall time
tW( H) = 180ns; tf = 10ns
tW(MRH) = 160ns (min)
1705
170s
'"::::c:
'"~
'"~
'"~
el2S
A tW(MRH) of 160ns is more than adequate to meet
the worst case precharge times for most dynamic
RAMs. For example, the MK4027-4 and the
MK4116-4 require a 120ns precharge.The other
refresh cycle parameter of importance to dynamic
RAMs is tw(MRL), (the time that MREQ
is low during the refresh cycle). This time is important
because MREQ is used to directly generate RAS. The
equation for the minimum time period is:
(4)
where:
let:
then:
tW(MRL) = tc-40
tc is the clock period
tc = 400ns
tW(MRLI = 360ns
SUPPORT CIRCUITS FOR DYNAMIC MEMORY
INTERFACE
Two support circuits are necessary to ensure reliable
operation of dynamic memory with the
zao.
The first of these circuits is an address latch shown in
Figure 3. The latch is used to hold addresses A12"
A15 while MREQ is active. This action is necessary
because the
does not ensure the validity of the
address bus at the end of the op code fetch (see
Figure 4). This action does not directly affect dynamic memories because they latch addresses internally. The problem comes from the address decoder
which generates RAS. If the address lines which drive
the decoder are allowed to change while MREQ is
low, then a "glitch" can occur on the RAS line or
lines (if more than one row of RAMs are used)
which may have the effect of destroying one row of
data.
zao
A 360ns tW(MR L) exceeds the 250ns min RAS time
required for the MK4027-4 and the MK4116-4.
zao,
By controlling the .refresh internally with the
the designer must be aware of one limitation. The
limitation is that to refresh memory properly, the
CPU must be able to execute op codes since the
refresh cycle occurs during the op code fetch. The
following conditions cause the execution of op codes
to be inhibited, and will destroy the contents of
dynamic memory.
zao
8T28
The second support circuit is used to generate a
power on and short manual reset pulse. Recall from
the discussion under
Timing and Memory Con-
VI-10
zao
ADDRESS LATCH
Figure 3.
7475
AI2
ID
IQ
AI2
AI3
20
2Q
AI3
AI4
30
3Q
AI4
AI5
40
4Q
AI5
G
G
I
1
T
RAS TIMING WITH AND WITHOUT ADDRESS LATCH
Figure 4.
\
OP CODE FETCH
/
\
' - - - - - _ _- - J
VALID REFRESH ADDRESS
VALID MEMORY .. DDRESS
RAS
RAS
\
\
REFRESH ADDRESS/
WITHOUT ADDRESS
LATCH
~U
\
/
\
WITH ADDRESS
LATCH
VI-"
/
/
trol Signals that one of the conditions that will
cause dynamic memory to be destroyed is a reset
pulse of duration greater than 1ms. The circuit shown
in Figure 5a can be used to generate a short reset
pulse from either a push button or an external
source. Additionally the manual reset is synchronized
to the start of an M1 cycle so that the reset will not
fall during the middle of a memory cycle. Along with
MANUAL AND POWER-ON RESET CIRCUIT
the manual reset, the circuit will also generate a
power on reset.
If it is not necessary that the contents of the dynamic
memory be preserved, then the reset circuit shown in
Figure 5b may be used to generate a manual or
power on reset.
+5
+5
Figure 5a.
+5
10K
10K
1000pf
+
68~f
l
111
CPU RESET
10K
+5
EXTERNAL
2201l.
RESET
~l
,..14
+
168~f
MANUAL AND POWER-ON RESET CIRCUIT
Figure 5b.
10K
CPU RESET
+5
+
68~fl
10K
EXTERNAL
RESET
>__-.-___V\.2f\20N'-_~
.......-
.....- - - - - '
VI-12
74132
7404
..::!!c
m
!;en
CD-
me)
---
'Z
m
X
~7
~~~~~~'8 g8
AO
A7
AI
AB
A2
A9
:
~
~
~p ~
~
=
~
~
4A
'3
AI' ,
J..
'8
•G
S
,'-',
' J5
~SI!1
-======:.....==...~I:A-~
IB
Af-
AI2
A6
AI3
.-
1 'J6
~
ill
~
I-I-I---
es" A6 I-RAS
MK4027-4
-=
~
I--
I--
r--
~
~
~
~
~
I--~
I--~
~
~
~
~ r--
r-
..u
II
~
I-I-~
I-I--~
~I--
'---~
r~
I---
~
I-r--
4~~6-4
(8l
3B
-=
:$
..Ll I I
"r-m
1---1---
I-I---
9
I-I--
en
n
Z
T
I---
1r-
:I:
m
r---
----;''O-_-_-~';::2-J-t~; eB~-+-~404
+5V - - - - - - , 4 A
;::;
J.
~
AA
~
MK
A4
All AS
1..L
N
:s:
I
j
WR
»
81LS97
0
L
rn
~
(,J
~
AI2 _ _ _ _ _ _ _ _ _#!-J~o
"0
_ _ _ _ _ _ _ _---""-',110
AI
AI~
_ _ _ _~.-----"""'3
AI
..115
()!l.!'B'----_~
J~
AO
..112
~r
~
,
:~
7400
~
RAS
7400
.~
5~
EI
6~-
~
7~
E2
+!5V- E3
~
......--
~~
yJI6
7404
"17
,~
~
2
'---
J25
110IIII32-
.........---<11
~~
MREQ
+5V
.-
See Tables 1 and 2 for jumper options.
~----4---~~D
s
7404
,---------------+--heK
74574
RF'§"H
1ft;
f
QI~M~U~X_ _ _~
TA
:s:
Bu I·
:j
OA s
0
t~~~~~g~E~
4
5
6
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:s:
DESIGN EXAMPLES FOR INTERFACING THE
Z80TO DYNAMIC MEMORY
To illustrate the interface between the Z80 and
dynamic memory, two design examples are presented.
Example number 1 is for a 4K/16Kx8 memory and
the example number 2 is a 16K/64Kx8 memory.
Design Example Number 1: 4KI16Kx8 Memory
This design example describes a 4K/16Kx8 memory
that is best suited for a small single board Z80 based
microcomputer system. The memory devices used in
the example are the MK4027 (4,096x1 MOS Dynamic RAM) and the MK4116 (16,384x1 MOS Dynamic RAM). A very important feature of this design
is the ease in which the memory can be expanded
from a 4Kx8 to a 16Kx8memory. This is made
possible by the use of jumper options which configure the memory for either the MK4027 or the
MK4116. See Table 1 and 2 for jumper options.
during an op code fetch or memory read when
ADDRESS DECODE, MREQ, and RD are all low.
The switch multiplexer signal (MUX) is generated on
the rising edge of after MREQ has gone low during
an op code fetch, memory read or memory write.
After MUX is generated and the address multiplexers
switch from the row address to column address,
~ will be generated. CAS comes from one of the
outputs of the multiplexer and is delayed by two
gate delays to ensure that the proper column address
set-up time will be achieved. Once RAS and CAS
have been generated for the memory array, the
memory will then access the desired location for a
read or write operation.
Figure 6 shows the schematic diagram for the
4K/16Kx8 memory. A timing diagram for the Z80
control signals and memory control signals is shown
in Figure 7_ The operation of the circuit may be
described as follows: RAS is generated by NANDing
MREQ with RFSH + ADDRESS DECODE. RFSH
is generated directly from the Z80 while address
decode comes from the 74LSI38 decoder. Address
decode indicates that the address on the bus falls
within the memory .boundaries of the memory.
If an op code fetch or memory read is being executed
the 81 LS97 output buffer will be enabled .at approximately the same time as RAS is generated for the
memory array. The output buffer is enabled only
DESIGN EXAMPLE NO.1 MEMORY TIMiNG
Figure 7.
MREQ------'----,
MUX-----t----'
52ns
CAS-----+-~
187ns
DATA BUS
VI-14
7404
7400
22ns}
Generate RAS from MREQ
15ns
63ns
RAS to rising edge of
10ns
to MUX
7404
15ns)
22ns
Generate CAS from MUX
7404
15ns
tCAC
165ns
CAS access time
81 LS97
22ns
Output buffer delay
349ns
Worst case access
74S74
74S157
The worst case access time required by the CPU
for the op code fetch is 450ns (from equation 1);
therefore, the circuit exceeds the required access time
by 101ns (worst case).
The circuit shown in Figure 6 provides excellent
performance when used as a small on board memory.
The memory size should be held at eight devices
because there is not sufficient timing margin to allow
the interface circuit to drive a larger memory array.
Design Example Number 2: 16Kx8 Memory
This design example describes a 16K/64Kx8 memory
which is best suited for a Z80 based microcomputer
system where a large amount of RAM is desired.
The memory devices used in this example are the
same as for the first example, the MK4027 and the
MK4116. Again as with the first example, the
memory may be expanded from a 16Kx8 to a 64Kx8
by reconfiguring jumpers. See Table 3 and 4 for
jumper options.
Figure 8. shows the schematic diagram for the 16K/
64K memory. A timing diagram is shown in Figure 9.
The operation of the circuit can be described as
follows: RAS is generated by NAN Ding MREQ with
ADDRESS DECODE (from the two 74LS138s) +
RFSH. Only one row of RAMs will receive a RAS
during an op code fetch, memory read or memory
write. However, a RAS will be generated for all rows
within the array during a refresh cycle. MREQ is
inverted and fed into a TTL compatible delay line to
generate MUX and CAS. (This particular approach
differs from the method used in example number 1
in that all memory timing is referenced to MREQ,
whereas the circuit in example number 1 bases its
memory timing from both MREQ and the clock.
Both methods offer good results, however, the TTL
delay line approach offers the best control over the
memory timing.) MUX is generated 65ns later and is
used to switch the 74157 multiplexers from the
row to the column address. The 65ns delay was
chosen to allow adequate margin for the row address
hold time tRAH. At 110ns, CAS is generated from
the delay line and NANDed with RFSH, which
inhibits a CAS during refresh cycle. After CAS is
applied to the memory, the desired location is then
accessed. A worst case access timing analysis for the
circuit shown in Figure 8can be computed as follows:
74LS14
74LSOO
delay line
delay line
7400
tCAC
8833
22",}
Generate RAS from MREQ
15ns
50ns
MUX from RAS
45",}
20ns
165ns
30ns
CAS delay from MUX
Access time from CAS
Output buffer delay
347ns
The required access time from the CPU is 450ns
(from equation 1). This leaves 103ns of margin for
additional CPU buffers on the control and address
lines.This particular circuit offers excellent results for
an application which requires a large amount of RAM
memory. As mentioned earlier, the memory timing
used in this example offers the best control over the
memory timing and would be ideally suited for an
application which required direct memory access
(DMA).
4K x 8 CONFIGURATION(MK4027) JUMPER
Table 1
Connect: J2 to J3
CONNECT: J13 toJ14
J4 to J6
ADDRESS
CONNECT
J7 to J8
aOOO-OF FF
J 17 to J25
J9toJ10
1000-lFFF
J18toJ25
J11toJ12
2000-2FFF
J19 toJ25
3000-3FFF
J20 to J25
4000-4FFF
J21 to J25
5000-5FFF
J22toJ25
6000-6FFF
J23 to J25
7000-7FFF
J24 to J25
16K x 8 CONFIGURATION (MK4116)'JUMPER CONNECTIONS
CONNECT: J14toJ15
ADDRESS
CONNECT
8000-8F F F
J 17 to J25
9000-9FFF
J18 to J25
AOOO-AF F F
J 19 to J25
BOOO-BFFF
J20 toJ25
COOO-CFFF
J21 to J25
DOOO-D F F F
J22 to J25
EOOO-EFFF
J23 toJ25
FOOO-FFFF
J24 to J25
Table 2
CONNECT:
J 1 to J2
J4 to J5
J8toJ11
J10 to J 13
J12 to J 16
J14 to J16
ADDRESS
CONNECT
0-3FFF
4000-7FFF
8000-BFFF
COOO-FFFF
J17 to J25
J18toJ25
J19 to J25
J20 to J25
VI-15
16K x 8 CONFIGURATION (MK4027)
Table 3
J1 to J3
J5 to J6
J7 to J8
J9 to J10
J11toJ12
J13toJ14
CONNECT:
~A~D~D~R~E~SS~:~~0~-~3F~F~F
~A~D~D~R~ES~S~:__~4~00~0~-7~F~F~F
CONNECT:
CONNECT:
64K
X
J24 to J25
J26toJ27
J28 to J29
J30 to J31
J16 to J17
J18toJ19
J20 to J21
J22 to J23
ADDRESS:
CONNECT:
8000-BFFF
J40toJ41
J42 to J43
J44 to J43
. J46 to J47
ADDRESS:
CONNECT:
8 CONFIGURATION(MK4116)
Table 4
CONNECT: J1 to J2
J4 to J5
J8toJ11
J10 to J13
J12toJ15
J14toJ15
ADDRESS: O-FFFF
CONNECT: J32 to J33
J34 to J35
J36 to J37
J38 to J39
SYSTEM PERFORMANCE CHARACTERISTICS
Table 5
The system characteristics for the preceeding design
examples are shown in Table 5.
EXAMPLE
2
#
MEMORY CAPACITY
MEMORY ACCESS
POWER REQUIREMENTS
4K/16Kx8
349ns max.
16K/64Kx8
347ns max.
+12V @ 0.0250 A max.
+5V @ 0.422 A max .•
-5V @ 0.030 A max.
+12V @ 0.600 A max.
+5V @ 0.550 A max. *
-5V @ 0.030 A max .
• All power requirements are max.; operating temperature O°C
to 70°C ambient, max +12V current computed with Z80
executing continuous op code fetch cycles from RAM at
1.6 /l s intervals.
VI-16
COOO-FFFF
J32 to J33
J34 to J35
J36 to J37
J38 to J39
DESIGN EXAMPLE NO.2 SCHEMATIC DIAGRAM
Figure 8.
74LSI4
lID
A7
AI
AS
A2
AS
A3
AIO
A4
Ali
A5
AI2
FOR JUMPER OPTIONS SEE TABLES 3 AND 4
VI-17
A6
AI3
AI4
AI5
DESIGN EXAMPLE NO.2 MEMORY TIMING
Figure 9.
OP CODE FETCH
37n5
RAS-------------+~
160ns
MUX-------------4----J
65 ns
CAS------------~------~
•
195ns ..
DATA BUS
347 ns ------_I
PRINTED CIRCUIT LAYOUT
One of the most important parts of a dynamic
memory design is the printed circuit layout. Figure
10 illustrates a recommended layout for 32 devices.
A very important factor in the P.C. layout is the
power distribution. Proper power distribution on
the VDD and VBB supply lines is necessary because
of the transient current characteristics which dynamic
memories exhibit. To achieve proper power distribution, VDD, VBB, VCC and ground should be laid
out in a grid to help minimize the power distribution
impedance. Along with good power distribution,
adequate capacitive bypassing for each device in the
memory array is necessary. In addition to the individual by-passing capacitors, it is recommended that
each supply (VSB, VCC and VDD) be bypassed with
an electrolytic capacitor 20J,lF.
By using good power distribution techniques and
using the recommended number of bypassing capacitors, the designer Can minimize the amount of noise
in the memory array. Other layout considerations
are the p.lacement of signal lines. Lines such as
address, chip select, column address strobe, and
write should be bussed together as rows; then, bus
all rows together at one end of the array. I nterconnection between rows should be avoided. Row
address strobe lines should be bussed together as a,
row, then connected to the appropriate RAS driver.
TTL drivers for the memory array signals should be
located as close as possible to the array to help
minimize signal noise.
For a large memory array such as the one shown in
design example number 2, series terminating resistors
should be used to minimize the amount of negative
undershoot. These resistors should be used on the
address lines, CAS and WRITE, and have values
between 20 n to a 33 n .
The layout for a 32 device array can be put in a 5" x
5" area on a two sided printed circuit board.
VI-18
SUGGESTED P. C. LAYOUT FOR MK4027 or MK4116
Figure 10.
VI-19
zao
4MHz
DYNAMIC MEMORY
CONSIDERATIONS
A tW(MRH) of 95ns will not meet the minimum precharge time of the MK4027-2 or MK4116-2 which is
lOOns. The MK4027-3 and MK4116-3 require a
120ns precharge. Figure 11 shows a circuit that will
lengthen the tW(MRH) pulse from 95ns to a minimum of 126n5 while only inserting one gate delay
into the access timing chain. Figure 12 shows the
timing for the circuit of Figure 11. The operation of
the circuit in Figure 11 can be explained as follows:
The D flip flops are held in a reset condition until
MREO goes to its active state. After MREO goes
active, on the next positive clock edge, the D input of
Ul and U2 will be tran~ferred to the outputs of the
flip flops. Output OA will go high if Ml was high
when clocked UL Output OB will go low on the
next positive going clock edge, which will cause
the output of U3 to go low and force the output of
U4, which is RAS, high. The flip flops will be reset
when MREO goes inactive.
INTERFACE
A 4MHz Z80 is available for the microcomputer designer who needs higher system throughput. Considerations which must be faced by the designer when
interfacing the 4MHz
to dynamic memory are
the need for memories with faster access times
and for providing minimum RAM precharge time.
The access times required for dynamic memory interfaced to a 4MHz
can be computed from equations 1 and 2 under Z80 Timing and Memory Control
Signals.
zao
zao
Access time for op code fetch for 4MHz Z80,
let: tc = 250ns; tDL~ (MR)= 75ns; tS (D) = 35ns
then: tACCESS OP CODE = 265ns
Access time for memory read for 4MHz Z80,
let: tc = 250ns; tDL~(MR) = 75ns; ts; (D) = 50ns
then: tACCESS MEMORY READ = 375ns
The problem of faster access times can be solved by
using 200ns memories such as the MK4027-3 or
MK4116-3. Depending on the number of buffer
delays in the.system, the designer may have to use
150ns memories such as the MK4027-2 or MK4116-2.
The most critical problem that exists when interfacing dynamic memory to the 4MHz
is the
RAM precharge time (trp). This parameter is called
twIMRH) on the
and can be computed by the
.
fol owing equation.
The circuit shown in Figure 11 will give a minimum
of 126ns precharge for dynamic memories, with the
operating at 4MHz. The 126ns tw(MRH) is computed as follows.
zao
110ns
zao
5ns
20ns
-9ns
zao
126ns
(4) tW(RH) = tW(H) + tf-20ns
let: tW(H) = 110ns; tf = 5ns
then: tW(MRH) = 95ns
4MHz
tW( H) - clock pulse width high (min)
tF - clock full time (min)
tDL;;iMR) - MREQdeiay (min)
74St4 delay (min)
tW(MRH) modified (min)
zao PRECHARGE EXTENDER FOR DYNAMIC MEMORIES
Figure 11
+5
MI
D SQ
cp
CK
~5
QA
D S
CK
74S74
QS
RQ
MREQ
b - - - - RAS
ADDRESS DECODE
+
RFSH
VI-20
TIMING DIAGRAM FOR 4MHz
zao PRECHARGE EXTENDER
Figure 12
MREQ
------+-"""'\
QA _ _ _ _ _ _ _ _ _J
9ns
QB
---------------------i
126min
ns
RAS - - - - - - . . . . ,
~~_ _ _O_P_C_O_D_E_F_E_T_C_H_~
)
APPENDIX
This section is intended to give the microcomputer
designer a memory diagnostic suitable for testing
memory systems such as the ones shown in Section
VI.
The routine is a modified address storage test with an
incrementing p'attern. A complete test requires 25610
OBJ CODE
r--~_ _ _RE_F_R_E_S_H_ _~;f
passes, which will execute in less than 4 minutes
for a 16Kx8 memory. If an error occurs, the program
will store the pattern in location '2C'H and the
address of the error at locations '2D'H and '2E'H.
MEMORY TEST ROUTINE
LOC
PRECHARGE
~
The program is set up to test memory starting at
tion '2F'H up to the end of the block of memory
defined by the bytes located at 'DC'H and 'DD'H.
The test may be set up to start at any location by
modifying locations '03'H - '04'Hand 'll'H - '12'H
with the starting address that is desired.
MXRTS LISTING
STMT SOURCE STATEMENT
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
PAGE
0001
TRANSLATED FROM DEC 1976 INTERFACE MAGAZINE
THIS IS A MOJIFIED ADDRESS STORAGE TEST WITH AN
INCREMENTIJG ?AlTERN
256 PASSES MUST BE EXECUTED BEFORE THE MEMORY IS
COMPLETELY TESTED.
IF AN ERROR OCCURS, THE PATTERN WILL BE STORED
AT LOCATION '002C'H AND THE ADDRESS OF THE
ERROR LOCATION WILL BE STORED AT '002D'H AND
'002E'H.
VI-21
MEMORY TEST ROUTINE (Cont'd.)
BE
C22500
23
7C
FE10
C21300
04
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
OBJ CODE
PlXRTS LISTING
STMT SOURCE STATEMENT
0000
0000
0600
0002
0005
0006
0007
0008
0009
OOOA
OOOB
0000
212FOO
70
AC
A8
77
23
7C
FE10
C20500
0010
0013
0014
0015
0016
0017
001A
001B
001C
001E
0021
212FOO
70
AC
LOC
P.8
0022
C30200
0025
0028
002B
002C
002D
002F
222000
322COO
76
2FOO
THE CONTENTS OF LOCATIONS 'OOOC'H AND '001D'H
SHOULD BE SELECTED ACCORDING TO THE FOLLOWING
MEMORY SIZE TO BE TESTED
TOP OF MEMORY TO
BE TESTED
4K
8K
16K
32K
48K
S4K
VALUE OF EPAGE
'10'H
'20'H
'40'H
'80'H
'CO'H
'FF'H
THE PROGRAM IS SET UP TO START TESTING AT
LOCATION '002F'H. THE STARTING ADDRESS FOR THE
TEST CAN BE MODIFIED BY CHANGI~G LOCATIONS
'0003-0004'3 AND '0011-0012'H.
TEST TIME FOR A 16K X 8 MEMORY IS APPROX. 4 MIN
ORG
OOOOH
LD
9,0
;CLEAR B PATRN MODIFIER
; LOAD UP MEMORY
LOOP:
LD
HL,START ;GET STARTING ADDR
FILL:
LD
A,1
;LOW BYTE TO ACCM
XOR
H
;XOR WITH HIGH 3YTE
XOR
B
;XOR WITH PATTERN
LD
(HL),A
;STORE IN ADDR
INC
HL
;INCRBMENT ADDR
LD
A,H
;LOAD HIGH BYTE OF ADDR
CP
EPAGE
;COMPARE ~ITH STOP ADDR
JP
NZ,FILL
;NOT DONE,GO BACK
;READ AND CHECK TEST DATE
LD
HL,START ;GET STARTING ADDR
TEST:
LD
A,L
;LOAD LOW BYTE
XOR
H
;XOR WITH HIGH BYTE
XOR
B
;XOR WITH MODIFIER
CP
(HL)
;COMPARE WITH MEMORY LOC
JP
NZ,FXIT
;ERROR EXIT
INC
HL
;UPDATE MEMORY ADDRESS
LD
A,H
;LOAD HIGH BYTE
;COMPARE WITH STOP ADDR
CP
EPAGE
;LOOP BACK
JP
NZ,TEST
;UPDATE MODIFIER
INC
B
0059
JP
0060 ;ERROR EXIT
0061 HIT:
LD
0062
LD
0063
HALT
0064 PATRN:
DEFS
0065 BYTE:
DEFS
DEFW
0066 START:
0068 EPAGE:
::CU
END
0069
VI-22
LOOP
PAGE
;RST WITH NEW MODIFIER
(BYTE),HL ;SAVE ERROl' ADDRESS
(PATRN),A ;SAVE BAD PATTERN
;FLAG OPERATOR
1
2
$
10H
0002
;SET UP FOR 4K TEST
MOSTEI(.
APPLYING THE zao SIO IN ASYNCHRONOUS
DATA COMMUNICATIONS
Application Note
corresponding error buffer, enabling the programmer to poll
the various Read Registers and ascertain error conditions
corresponding to the data. This concept is illustrated in
Figure 2. Recieve Buffer 3 contains data, has no associated
errors, a nd will be read next by the CPU, as it is at the top of
the stack. Receive Buffer 2 has a parity error associated with
it's data word, indicated by the "1" in the parity column.
Similarly, Receive Buffer 1 has an associated overrun error
condition, indicating it has been overwritten at least once.
This type of FIFO arrangement allows the programmer
three full receive word-times to read the 510 before losing
any data, which is extremely advantageous when the
programmer must perform numerous housekeeping
functions. The 510 is also capable of full duplex operation,
illustrated in Figure 2 by separate data paths for the
transmitter and receiver. Notice the separate transmit and
receive clock inputs for situations requiring different clock
rates. A SYNC input is provided as a general purpose input
in asynchronous communications, and is used to establish
synchronization in monosync and bisync communications.
Finally, all standard modem control signals are present for
handshaking including DCD, DTR, CTS, and RTS.
Serial asynchronous data links, probably the most prevelent
mode of data communications in existence today, require
versitile, easy to interface communications devices. The
Z80 510 is just such a device. Although it is just as equally
suited in virtually all serial protocol environments, no
compromises were made in asynchronous applications.
The
510 operating features include:
zao
o Data communications rates of up to 800K bits/s
o Three FIFO receive data buffers per channel
o Full duplex operation
o Break generation and detection
o Parity, overrun, and framing error detection
o Polled or interrupt driven
The most salient of the SID's many features is its capability
to operate using prioritized vector interrupts, offering
unparalleled speed and efficiency in maximizing data
throughput. Although the 510 can be operated in polled as
well as interrupt modes, the latter shall be emphasized in
the following discussion due to its inherent power and
versatility.
The 510 interfaces easily with the Z80 CPU, and generally
requires little, if any modification of control signals when
used with other CPU's. Figures 3A and 3B show the typical
interconnections and addressing techniques between the
510 and CPU. Note that the cio (control data) and BiA
(Channel BfA) pins may be connected to AD and A 1 of the
address bus, respectively. Figure 3B further illustrates 510
addressing, where even numbered addresses decode the
channel (A or B) and define a data operation. Conversely, odd
numbered addresses define a control operation to the
addressed port.
In order to better understand use of the 510 in serial data
communications, a look at the internal organization of the
chip would be helpful. Figure 1 depicts the functional logic
of one of the 510 channels. As shown, there are a total of 11
registers accessible by the programmer. "Write Registers"
(WRO-WR7), as they are referred to, are used to configure
the 510 to the desired type of protocol and includes such
information as data rates, parity information, word length,
etc. In addition, three "Read Registers" (RRO-RR2) are
provided for monitoring data flow and error conditions. For a
detailed description of these registers, as well as the entire
MK3884, reference should be made to the MK3884 Z80
510 Technical Manual. In the receiver section, notice that
data flows from the receive shift register to the three receive
buffers.
THE ASYNCHRONOUS MODEL
These registers are configured in a first in, first out (FIFO)
arrangement, thus providing the data link with additional
overrun protection. Associated with each receive buffer is a
In discussing the use of the Z80 510 in Async
communications, the illustration in Figure 4 depicts the
method in which the 510 receiver logic assembles and
There are also two clock considerations that deserve
attention. 1) The 510 is a synchronous device, whose clock
(<1» must be identical to that of the CPU clock. 2) Although
the 510 is capable of high data rates, care should be taken to
ensure that the system clock (<1» is at least 5 times the data
rate, as specified in the data book.
VI-23
transmitter logic sends serial data asynchronously. The.
data stream consists of one start bit, a variable length data
word (selectable 5-8 bits), an optional partity bit, and
selectable stop bits (', , y, or 2). Note that the data word is
sent low order bit first and must be right justified if less than
8 data bits are contained in the data field.
FUNCTIONAL lOGIC OF AN SIO CHANNEl
Figure 1
OATABUS
.~
ROY/WAIT
RRO
WRO
RR1
WR1
RR2
WR2
WR3
r-l
XMIT
REGISTER
I
CONTROL
LOGIC
1~llall~llgl
I
I
XMIT
BUFFER
I
WR5
RCV
ERRORS 3
i
I
RCV
BUFFER 3
WR6
RCV
BUFFER 2
I
RCV
ERRORS 2
I
RCV
BUFFER 1
I
RCV
ERRORS 1
I
RCV
REGISTER
I
XMIT
LOGIC
I
RECEIVE
LOGIC
f
,
I~I
WR4
Igi
f
i
Isll~II~1
SIO RECEIVE FIFO DATA/ERROR BUFFERS
Figure 2
Receive Buffer 3
, 0
o ,
o,
000
Receive Buffer 2
o
, 0
, 0
o0
o,
Receive Buffer
00'00
Receive
Register
00'00 ,
WR7
0
ttL
Error
Buffer 3
Error
Buffer 2
Error
Buffer'
Parity
~overrun
Framing
VI-24
...
;;:.
zao CIO - CPU INTERCONNECTIONS
Figure3A
FROM HIGHER
lEI _
PRIORITY DEVICE - - -
D'-"AT.;.;.A_B_U;..:S'-'D;...O;...-_D;..:7_ _ _ _ _ {
} _ _ _ _c:..
TO LOWER PRIORI~ lEO
DEVICE
ZBO
SIO
ZBO
CPU
C/D~---------------------iAO
B/A~------------------------iA1
CE
:>
I
5V
DECODE
I
l
J
ADDRESS B u s T
zao SIO-CPU INTERCONNECTIONS
Figure3B
Address Label
SIOADD
SIO ADD +1
SIOADD +2
SIOADD +3
CE
0
0
0
0
B/A C/O
0
0
0
1
1
0
1
1
Channel
Channel
Channel
Channel
A XMITIRCV ADDRESS
A READIWRITE ADDRESS
B XMITIRCV ADDRESS
B READIWRITE ADDRESS
ASVNCHRONOUSFORMAT
Figure 4
DATA FIELD
START BIT
1
MARKING LINE
STOP BITS (1, 1 Y2, or 2)
PARITY BIT
10,"ON\,
/
I'
U--- __ -3_
ID:(5-B:S)iru.-DA: -
_ ____
VI-25
i
-1_
MARKING LINE
ASYNCHRONOUS PROGRAMMING
The design of a serial data communications link utilizing the
SIO will comprise three basic software modules:
• Initialization
• Data tra nsfer
• Error detection and recovery
The program flow for initialization is illustrated by the flow
diagram in Figure 5. This procedure consists of writing a
string of control bytes to the SIO using the pointer register,
WRO. Each control byte is preceded by the pointer register
byte, which tells the SIO which of 8 write registers is to be
addressed. Initialization is executed in this alternating
pointer register/control-data fashion until the SIO is
configured as desired, as shown in Table 1.
Although SIO initialization is not necessarily order
dependent, the logical order as depicted in Figure 5 and
Table 1 is highly recommended.
Also, a word of caution concerning the use of WRO is
appropriate at this time. As WRO has a dual function - that of
a pointer to other control registers and commands (i.e., reset
channel, error reset, etc.) to the SIO - it is possible to perform
both of these functions simultaneously. This is not
recomended because following each command, the
internal register pointer resets to zero, thus preventing the
ensuing control word from loading properly. Each command
issued should address WRO, as pointed out in the example.
Data transfer and error handling methods are presented in
there simplest form in Table 1. The first eight bytes of code
initialize the SIO, which consists of initializing the CPU
internal registers B, C, and HL with the table length, port
address, and table address, respectively. Notice how
efficiently the use of the OTIR instruction transfers the
entire block of data to the SIO. Although channel A is the
active channel being used in this example, channel B must
also be accessed, as shown. This is because the WR2 and
the status affects vector bit are active in channel B only.
Another instruction of interest is the "EI" instruction, both
because of it's existence and placement. Whenever the
CPU acknowledges an interrupt, interrupts within the CPU
are disabled and remain so until an "EI" instruction is
executed. Hence, the placement of "EI" in the program
example forms a non-nested interrupt structure. Conversly,
placing "EI" at the beginning of a subroutine would
constitute nested interrupts, as other devices could now
cause interrupts.
The interrupts themselves may be initiated by the SIO in
many different ways. The transmitter and receiver
interrupts are initiated when the transmit buffer empty and
receiver character available bits are set. In the case of
receive errors, interrupt requests are made (if programmed
to do so) when any of several special error conditions exist.
As shown in the program initialization (Table 1), the special
effects vector is enabled, allowing the SIO to modify the
returned vector, indicating either a) transmit buffer full, b)
receive-character available, c) External/Status change, or
d) special receive conditions. This powerful feature further
reduces programming overhead and thus allows greater
efficiency and data throughput. Also, at the programmers
discretion is the abilityto initiate data transfer automatically
by monitoring the modem control signals. This is effected by
the SIO detecting DCD and CTS in an active state which, in
turn, enables the receiver and transmitter, respectively.
Also, if External interrupts are enabled as they are in the
example, interrupts are generated upon transition of DCD or
CTS. This feature is useful in initiating line turn-around and
detecting break conditions. Once External/Status Interrupts have been acknowledged, they must be reset by
writing to register 0 of the appropriate channel. Note also in
the initialization procedure that immediately following a
chip or channel reset, the "Reset External/Status
Interrupts" command should be executed to prevent
possible spurious interrupts.
Should the programmer choose not to operate in an
interrupt mode, all of the aforementioned conditions would
have to be polled by reading the appropriate read register
(RRO-RR2). When operating in this mode, the proper
sequence of checking the SIO for receive characters would
be:
1. Read RRO; determine if a character is available.
2. If so, interrogate RR1 to ascertain error status.
3. Read the DATA.
The status of errors should be checked before reading the
data to preserve the proper error to data word
correspondence. An example of reading the Read
Registers is given in Table 1 under Error Handler. As illustrated, RR1 is accessed by first performing a "write" to
WRO which points to register 1, and followed by a "READ"
operation. Once the status byte is in the accumulator, each
of the pertinent error bits are interrogated using the "bit"
instruction. Associated with each type of error is it's error
routine which takes the appropriate recovery action. When
interrupts are used, as in this example, care should be taken
within each Error Routine to perform an Error Reset
command, thus allowing future error interrupts to occur.
The preceding example should equip the user with a
"guide" for programming the SIO, not only in
asynchronous communications, but synchronous and
SDLC/HDLC as well. Of course, the latter protocols deserve
special attention, and are covered in detail in the MK3884
Technical Manual. As demonstrated, the SIO, when taken
advantage of, can be an extremely powerful device in any
data communications link.
VI-2S
LOGICAL FLOW OF SIO INITIALIZATION
Figure 5
START
INITIALIZATION
SET RTS LOW, ENABLE TRANSMIT,
INITIALIZATION DEFINE CHARACTER
LENGTH AND SET DTR
WR5
CHANNEL RESET
WRO
RESET EXTERNALI
STATUS INTERRUPTS
WRO
LOAD INTERRUPT VECTOR
WR2
ENABLE TRANSMIT INTERRUPTS
INTERRUPTS ON ALL RECEIVE
CHARACTERS STATUS AFFECTS VECTOR,
ENABLE EXTERNAL INTERRUPTS. DISABLE
WAIT I READY FUNCTION
WR1
RESET EXTERNALI
STATUS INTERRUPTS
WRO
LOAD SIO WITH
FIRST XMIT DATA BYTE
CONFIGURE ASYNC
MODE, STOP BITS, ETC.
WR4
SIOARMED
RETURN TO MAIN
PROGRAM
DEFINE RECEIVE
CHARACTER LENGTH,
AUTO ENABLE, ENABLE
RECEIVER
WR3
EXIT
VI-27
TYPICAL PROGRAM EXAMPLE
TRANSMIT DATA HANDLER
Table 1
LABEL
SOURCE STATEMENT COMMENTS
LABEL
UNIT
LD B, LENG B
LD C, SIOCTL +2
lD HL, CTlTB
OTIR
lD B, lENG A
lD C, SIOCTl
LD Hl, CTLTA
OTIR
; LENGTH ofTable, CH B
; Port Address, CH B
; TABLE Address, CH B
; Initialized CH B
; Length ofTable, CH A
; Port Address, CH A
; Table Address, CH A
; Initialize CH A
XMTINT EXAF,AF
LD A(T BUF)
OUT (SIODAT),A
EXAF,AF
EI
RETI
; WRO, RESET CH A
; WRO, Reset External/Status
Interrupts
; Pointer to WR4
; X16 CLK, ODD Parity, 2 stop
bits
; Pointer to WR3
; 7 bits/char, receive and
auto enable
; Pointer to WR5
; Set RTS, DTR; 7 bits/char.,
enable Xmit
; WRO; reset EXT/STATUS
INT.
; Poi nter to WR 1
; Enable external and
transmit interrupts,
status affects vector,
interrupt on all RCV
characters.
RCVINT EX AF,AF
IN A(SIODAT)
LD(RBUF),A
EXAF,AF
EI
RETI
CTRLTA DEFB'18'H
DEFB'1O'H
DEFB'04'H
DEFB'4Q'H
DEFB'03'H
DEFB'61'H
DEFB'05'H
DEFB 'AA' H
DEFB'10'H
DEFB'01'H
DEFB '17' H
CTLTB
DEFB'18'H
DEFB'10'H
DEFB '02' H
DEFB'OO'H
DEFB'01'H
DEFB '14' H
SOURCE STATEMENT COMMENTS
; Save Registers
; Load Character
; Ship it Out
; Restore Registers
; Re-enable interrupts
RECEIVE DATA HANDLER
; WRO, Reset CH B
; WRO, Reset External/Status
Interrupts
; Pointer to WR2
; Load Interrupt Vector
; Pointer to WR1
; Status affects vector
VI-28
;
;
;
;
Save Registers
Read Character
Save in Memory
Restore Registers
ERROR HANDLER
INTERR
EXAF,AF
lOA, '01' H
OUT (SIOCTl),A
IN A(SIODAT)
BIT 6,A
JR Z, FMER
BIT 5,A
JR Z,ORER
JP PAER
EXAF,AF
EI
RETI
; Save Registers
; Set Pointer to
; Reg. 1
; Framing Error
; Overrun Error
; Parity Error
; Restore Registers
MOSI'EI(.
USE OF THE MK3805 CLOCK/RAM
Application Note
INTRODUCTION
PINOUT DIAGRAM
Many microprocessor applications require a real time clock
a nd/or memory that can be battery powered with very low
power drain. A typical application might be an automobile
trip computer, where the clock could provide the time of day
and the memory would be used to retain vital information
when the ignition switch is off. The interfacing technique
needs to be kept as simple as possible so as to minimize the
required overhead in software, and it should minimize the
number of pins required in order that other I/O
requirements can be efficiently accommodated.
Figure 1
CKO
X2 3
PIN
1
2
3
4
5
The real-time clock/calendar provides all timekeeping
functions. It contains registers for seconds, minutes, hours,
day, date, month, and year. The end of the month date is
automatically adjusted for months with less than 31 days.
The clock operates in either the 24 hour or 12 hour format
with an AM/PM indicator. Since the MK3805 is designed
to interface to a microcomputer, the alarm function is easily
accommodated in the microcomputer, should it be required.
The on-chip oscillator provides the clock source for the
clock/calendar. It incorporates a programmable divider so
that a wide variety of crystal frequencies can be
accommodated. The oscillator also has an output available
that is designed to serve as the clock generator for the
microcomputer. A separately programmable divider provides several different output frequencies for any given
crystal frequency. This feature can eliminate having to use a
separate crystal or external oscillator for the microcomputer, thereby reducing system cost.
Interfacing the CLOCK/RAM with a microcomputer is
greatly simplified using asynchronous serial communication. Only 3 lines are required to communicate with the
CLOCK/RAM: (1) CE(chip enable), (2) I/O (data line), and (3)
SCLK (shift register clock). Data can be transferred to and
from the CLOCK/RAM one byte at a time, or in a burst of up
to 24 bytes.
6
7
8
Vee
7 SCLK
6 1/0
GND 4
FEATURES
Mostek's CLOCK/RAM microcomputer peripheral chip
satisfies all of these requirements. The device, designated
MK3805, contains a real-time clock/calendar, 24 bytes of
static RAM, an on-chip oscillator and communicates serially
with the microcomputer via a simple interface protocol. The
MK3805 is fabricated using CMOS technology, thus
insuring very low power consumption.
'0'
X1/CI 2
5 CE
NAME
DESCRIPTION
CKO
X1/CI
X2
GND
CE
I/O
SCLK
System clock (output).
Crystal or external clock (input).
Crystal (input).
Ground.
Chip enable (input, active low).
Data I/O (input/output).
Shift register clock (input).
Positive supply Voltage.
Vee
PINOUT DESCRIPTION
Figure 1 is a pinout diagram of the MK3805. It is packaged
in an 8-pin DIP to conserve PC board space. A brief
description of the function of each pin is listed.
TECHNICAL DESCRIPTION
Figure 2 is a block diagram of the CLOCK/RAM chip. The
main components are the oscillator and divider,
real time clock/calendar, the static RAM, the command
register and logic, the control register and logic, and .the
serial shift register.
The shift register is used to communicate with the outside
world. Data on the I/O line is either input or output on each
shift register clock pulse when the chip is enabled. If the
chip is in the input mode, the data on the I/O line is input to
the shift register on the rising edge of SCLK. If in the output
mode, data is shifted out onto the I/O line on the falling
edge of SCLK.
The command register receives the first byte input by the
shift register after CE goes true (low). This byte must be the
command byte and will direct further operations within the
CLOCK/RAM. The command specifies whether subsequent transfers will be read or written, and what register or
RAM location will be involved.
VI-29
MK3805 CLOCK/RAM BLOCK DIAGRAM
EXTERNAL CLOCK INPUT
Figure 2
I
X1
'riDh
X2
BUFFER
OSCILLATOR
AND
DIVIDERS
REAL TIME CLOCK/CALENDAR
.
1"-
J.
1"-
II.
1/0
!
SHIFT
REGISTER
r
CONTROL
REGISTER
AND
LOGIC
.
i'"-
...
~
A
DATA BUS
~
"'Z
SCLK
CKO
i
COMMAND
REGISTER
AND
LOGIC
.-11.
I ADDRESS & CONTROL BUS
.
24 x8 RAM
-CE
The control register has bits defined which control the
divider for the internal real-time clock and the external
system clock. One bit serves as the write protect control
flag, preventing accidental write operations during powerup or power-down situations.
The real-time clock/calendar is accessed via seven
registers. These registers contain seconds, minutes, hours,
day, date, month, and year information. Certain bits within
these registers also control a run/stop function, 12/24
hour clock mode, and indicate AM or PM (12 hour mode
only). These registers can be accessed either randomly in
byte mode, or sequentially in burst mode.
The static RAM is organized as 24 bytes of 8-bits each. They
can be accessed either randomly in byte mode, or
sequentially in burst mode.
The reader should refer to the MK3805 data sheet for
operating specifications and detailed timing information.
DATA TRANSFERS
Data transfer is accomplished under control of the CE and
SCLK inputs by an external microcomputer. Each transfer
consists of a single byte (COMMAND) input followed by a
single or multiple byte input or output (as defined by the
command byte).
The general format for the command byte is shown in
Figure 3. The most sign'ificant bit (bit 7) must be a logical 1;
bit 6 specifies a clock function if logical 0 or a RAM function
if logical 1. Bits 1 -5 specify the clock register(s) or RAM
location(s) to be accessed. The least significant bit (bit 0)
specifies a write operation if a logical 0 or a read operation if
a logical 1.
In the clock burst mode, all clock, calendar, and control
registers are transferred beginning with register 0 (seconds)
and ending with register 7 (control). Unless terminated
early, this burst mode requires that CE be true and 72 SCLK
cycles be supplied. This mode may be terminated at any
time by taking CE false. This mode is specified by setting all
aqdress bits in the command byte to a logical 1.
In the RAM burst mode, all RAM locations are transferred
beginning with location 0 and ending with location 23
(017H). Unless terminated early, this burst mode transfer
VI-30
MK3805 CLOCK/RAM
Figure 3
COMMAND. REGISTER. DATA FORMAT SUMMARY
I. GENERAL COMMAND FORMAT:
765432
I' t?;l
0
A41 A3 I A2 I A, I Ao
[Xl
II. CLOCK COMMAND FORMAT:
IV. CLOCK PROGRAMMING MODEL:
765432
0
7
6
5
o
2
4 3
SECIL-'~_O__~O__~O__L-°~I__O~I__O~~~·~~~
00.59ISTOpl,0 SEC
MINIL-'~ O~_O ~O~L-°~I O~I '~~~w~
00. 59 1L-____
,_0_M
__
IN____...I..._____M
_I_N______...J
__
HRI,
DATE
I,
1
0
1 0
__
1
__
1
0
1
0 I 0
MONTHI~__~_O~__0-L_O__
DAYI~__~_O~__0-L_O__
YEAR
I, [6;l
o I I'~
IL-'~__O~I O~~~._w~
L-~__O~I '~~~w~
o
0
__
1
0
__
__
~I_'~L-0~__O~_O__~I_'__IL-'~__O~~~R_W~
CONTROLI~_'~__O~__°-LI_O__IL-'~__~__~~~w~
0'-2B/29 1 T
0'-30
,
0'-31L-~
1101'0
[A7P]
HR
1
1
DATE
O'ODATE
__ ______-L_____________ J
~.
0,.,21 0
0
0
1~ 1
01.071 T2
0
0
0
0-99
I
HR
10 YEAR
I
1
MONTH
0
DAY
YEAR
0
NOTES:
WP
X4 - Xo
C,·C o
III. RAM COMMAND FORMAT:
T2 -T,
o
o
RAMO
0
••
•
1_'
RAM 23 1'--,-_'
.....
......
RAM
BURST
I,
o
O~
I_'_II---'. .1_,
. . . .I<~- :;.:.jW
....L.I_O.....
1'111'1'1~
VI-31
I
I~I~I~I~I~I~I~I~I
~
1 I, I' I
CLOCK
BURST
0'.'21'2/1
00.23. 24 . 0
SEC
Write protect.
Program dividers for real time clock.
Program dividers for clock output.
Test bits (normally set to 0).
requires that CE be true and 200 SCLK cycles be supplied.
This mode may be terminated at anytime by taking CE false.
This mode is specified by setting all address bits in the
command byte to a logical 1 .
Refer to Figure 3 for a summary of the command, register,
and data formats.
POWER-ON STATES
When the MK3805 is first powered up, all eight clock
registers come up to a pre-defined state. These are listed
below. The RAM locations contain unspecified data.
DESIGN EXAMPLE
As a demonstration of the software and hardware
interfacing for the CLOCK/RAM chip, the design of a
demonstration used for electronic shows is given here. The
hardware used was a standard CRT terminal. an
MK38P73 single chip microcomputer, the MK3805
CLOCK/RAM chip, and some miscellaneous parts to
interface to the CRT. Refer to Figure 5 for a schematic ofthe
circuit used. Note how simple the design is. The MK3805
interfaces directly to the MK38P73 via 3 pins, and it
provides the clock input to the MK38P73 via a fourth pin.
HARDWARE DESCRIPTION
Clock:
Seconds
Minutes
Hours
Date
Month
Day
Year
Halt
12/24 Hour
Control:
Write Protect
CO & C1
X3&X4
XO, X1 & X2
The MK38P73 is an 8-bit single-chip microcomputer with 4
parallel ports, a serial port, 128 bytes of RAM, and 2K bytes
of EPROM (in the form of a piggy back 2716). Because the
serial communications with the CLOCK/RAM uses a
simple shift register type interface, the serial port of the
38P73 is not used here. It remains free for serial
communications with the CRT.
00
00
00
01
01
01
00
1
o
1
01
00
000
(clock stopped)
(24 hour mode)
(protect on)
(CKO = crystal frequency 12)
(crystal frequency is binary:
2h)
(divide by 2 23 )
SERIAL TIMING
The timing sequence for data transfer with the
CLOCK/RAM is started when CE goes low (see Figure 4).
After CE goes low, the next 8 SCLK cycles will input the
command byte of the proper format. If the most significant
bit (bit 7) is a logical 0, the command byte will be ignored, as
will all SCLK cycles until CE goes high and returns low to
signify the start of a new transfer. Command bits are input
on the rising edge of SCLK.
The MK3805 is interfaced to the microcomputer via port 4.
This is done to take advantage of the STB line associated
with that port. The STB line goes low for a short time after
each output to port 4 instruction is executed. This normally
would be used to strobe data into an output device attached
to the port. In this example, the STB line provides the SCLK
pulse to the CLOCK/RAM shift register to clock data into
and out of the chip. By using this line, toggling another port
bit to strobe data in and out is not required. Such an
interface to other microcomputers is straightforward.
The CLOCK/RAM chip also provides the clock source for
the microcomputer. By selecting a crystal frequency of
3.6864 MHz and setting the CKO divider to divide by 1, the
serial port on the MK38P73 operates at standard Baud rates
(9600, 4800, 2400, 1200, etc.).
The 75150 and 1489 chips convert the TTL level signals
output by the microcomputer to RS-232 levels in order that
the circuit can be interfaced to a standard CRT.
SOFTWARE DESCRIPTION
Input data will be input on the rising edge ofthe next 8 SCLK
cycles (per byte jf burst mode is specified). Additional SCLK
cycles will be ingored, should'they inadvertently occur.
Output data will be output on the falling edge of the next 8
SCLK cycles (per byte if burst mode is specified). Additional
SCLK cycles will retransmit the information, thereby
permitting continuous transmission of clock information for
certain applications.
A data transfer will terminate if CE goes high, and the
transfer must be reinitiated by the proper command when
CE goes low again. The I/O pin will be in the high
impedance state when CE is high.
The heart of the software is the subroutine labeled
'CLKRAM'. This subroutine provides all the necessary
software interfacing to the CLOCK/RAM.
Before calling the subroutine, the necessary parameters
must be set up in the proper registers. The ISAR is used as a
pointer to where the data is to be read from or written to in
the MK38P73 RAM area.
The scratchpad register 'CMD' must contain the command
to be sent to the CLOCK/RAM. (See the description of the
command given earlier.)
The bit pattern for enabling the CLOCK/RAM must be
VI-32
!13:
cc ~
c:: Co)
iil CO
"'0
en
::D
l>
3:
Notes:
c
1) Data input sampled on rising edge of clock.
2) Data output changes on falling edge of clock.
3) Rising edge of CE terminates operation and resets command register.
!il>
~
::D
I. SINGLE BYTE TRANSFER
l>
Z
en
."
SCLK~
m
::D
JLJ
--AAJ
en
c
3:
3:
CEL
l>
::D
-<
0123456701234567
~
tl
1/0-{0IAOIA1IA2IA3IA4r:t]1X 1
I
ADDRESS/COMMAND
I
I
I
I
DATA INPUT
I
0123456701234567
)
IAOIA1IA2IA3IA4~ 1X
(1
ADDRESS/COMMAND
1
I
I
I
I
I
1
)>--
DATA OUTPUT
II. BURST MODE.TRANSFER
1
2
3
4
n
SCLK~
CEI
~
- - - - - - . . . , ( "....; . ; . - - - - - - - - - - - '
~.
012345670123
I/O---<%] 1 11 11 11 11
MX
ADDRESS/COMMAND
1
1
I
I
DATA I/O
4
5
6 7
[[n)~DATA I/O N
FUNCTION
N
n
CLOCK
8
72
24
200
RAM
stored in the scratchpad register 'CHIPEN'. This bit pattern
should contain a logic 1 in the bit position that corresponds
to the port 41ine tied to the CLOCK/RAM
pin. All other
bits should be 0. This technique allows multiple serial
microcomputer peripheral chips to be tied together with
common I/O and SCLK lines, with a separate port line for
each device CEo
begins execution of the program at location OOOOH. The
code at this point initializes the system and checks for valid
CLOCK/RAM data. This condition is indicated by the state
of the write protect bit in the control byte. If the bit is set to a
logical 1, then the CLOCK/RAM has also just been powered
up. This indicates that the registers contain invalid data and
should be initialized before continuing. 1ft he bit is reset to a
logical 0, the CLOCK/RAM did not just power up, and the
data in its registers should be valid.
cr
The subroutine also provides an option for using the port 4
pins not used by the CLOCK/RAM interface for any other
purpose. To accomplish this, a copy of whatever is written to
port 4 by other routines must be kept in the scratchpad
register 'PT4IMG'. This option is not used in this example.
After the clock data is verified, the routine prints a message
consisting of CLOCK/RAM features. The timer is then set to
interrupt once every 1 /36 second so that the time, etc., may
be updated on the CRT screen. The routine then just waits
for an interrupt from the timer or the keyboard.
The main demonstration routine (listing 1) is quite basic. Its
purpose is to print the features of the CLOCK/RAM on the
CRT, then read the clock and display it's contents once every
second. A reentry point is provided in order that the
clock/calendar settings may be changed after power up.
(See the flowchart in Figure 6.)
When a timer interrupt occurs, the service routine checks to
see if 1 second has elapsed since the last service. If not, it
resets the timer and returns to the wait for interrupt state. If
1 second has gone by, the routine proceeds to erase the
When power is applied to the microcomputer, it resets and
SCHEMATIC OF DEMONSTRATION CIRCUIT
Figure 5
401
5~
+Vcc
--
9
CE
P4·1
110
6
8_
P4·0
SRCLK
I
7
7
30K
+Vcc
5
RESET
39
-
STB
EXTINT
38
1K
SI 35
+vcc
OUT
IN
1
Rx
1489
GNO
XTAl
-J;
1
N C - XTll
c::J
-C
14
3
MK38P73
MK3805
r
FI 1bt--
RESET
10IL
CLK 1
OUT
XTAL
2
1
XTl2
so
GNO
GNO
-t
21-
34
2
STB
7
IN
OUT
TX
75150
8
r-----
+Vee -Vee
GNO
5
- 12
-t
+12
~-------GNO
1
VI-34
time, etc., from the top of the screen and print new data
obtained from the CLOCK/RAM. The timer is then reset and
returns to the wait for interrupt state.
send the command to the CLOCK/RAM chip and then
transfer the number of data bytes specified by the
command.
When a receiver interrupt occurs, the serial port contains a
valid character from the keyboard. The service routine
checks to see if it is a 'DC3' (control-S) character. If not, the
routine returns to the wait for interrupt state. If it is,
the routine goes to the clock set entry point of the main
routine and the user is allowed to set the clock and calendar
values. The main routine entered in this fashion is executed
similarly to a power on reset with the CLOCK/RAM write
protect bit set to a logical 1.
As seen in the flowchart(Figure 7), either 1,7, or24 bytes of
data may be transferred between the microcomputer and
the CLOCK/RAM. The command sent to the subroutine is
exactly the command sent to the CLOCK/RAM, so there is
no confusion as to the format of the command byte. When
this routine is called, the ISAR must be pointing to the
scratchpad RAM area where the data transferred is to be
read from or written to. Note that only 7 bytes are
transferred in a clock burst. This is to eliminate reading and
writing the control register every time.
The CLOCK/RAM subroutine (listing 2) was designed to
VI-35
MAIN ROUTINE FLOWCHART
Figure 6
RCVINT
)
(
~
1
INITIALIZE
CLK/RAM
SUBROUTINE
PARAMETERS
SAVE
STACK
~
l
INPUT A
CHARACTER
INITIALIZE
SERIAL PORT
PARAMETERS
)
~YES
r
PROTECT
SET?
YES
DATE IN
INPUT
DATE
STATWR
•
(
MODE IN
INPUT 12 OR
24 HOUR MODE
~
24 HOUR
MODE?
NO
AMPMIN
INPUT AM
ORPM
DATAOK
)
WRITE NEW
CLOCK/RAM
STATUS BYTE
~
DAY
PRINT
DAY
-~
DATE
PRINT
FEATURES
PRINT
DATE
+
TIME
PRINT
TIME
~
l
OUTMSG
SEND CURSOR
HOME
ENABLE
INTERRUPTS
ENABLE
INTERRUPTS
RETURN
READ CLOCK
REGISTERS
+
OUTMSG
INPUT
TIME
-~
CLKRD
~
l
~
1
t
NO
PRINT AM/PM
MESSAGE
INITIALIZE
SERIAL PORT
FOR RECEIVE
W/INTERRUPT
TIME IN
RESET
COUNT
AMPM
INITIALIZE
TIMER FOR
1/36 SECOND
INTERRUPTS
I
~
YES
~
,
)
PASSED?
READ
CLOCK/RAM
STATUS BYTE
INPUT
DAY
FIN ISH
.o~
!
DAY IN
(
DECREMENT
1/36 COUNT
STATRD
'DC3;?
SeTCLK
SAVE
STACK
~
INCHR2
.o~
(
T
DEMO
~
WAIT
)
VI-3S
)
~
SETUP
SERIAL PORT
FOR RECEIVE
W/INTERRUPT
CLKRAM SUBROUTINE FLOWCHART
Figure 7
LOAD BYTE
INTO TEMP.
PUT CHIP
ENABLE BIT
INTO PORT
4 IMAGE
PUT COMMAND
INTDTEMP.
FOR OUTPUT
COMPLEMENT
AND MIX
W/PT4MG
VI-37
VI-38
LISTING 1 - DEMO PROGRAM
CLOCK/RAM DEMONSTRATION MODULE
Fa/3a1D ~ACRO CROSS ASSM. V2.2
LOC 06J.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ASS
1
2
3
4
.,
TITLE CLeCK/RAM DEMONSTRATION MODULE
NAME JEMO
PSECT ASS
GLOBAL CLKRAM
• THIS MODULE MUST BE LINKED WIT~ THE CLOCK/RAM MODULE
• TO CREATE A WORKING PROGRAM.
.,•
****************.*****************
.,
.,
• DEMO FOR MK3805 CLOCK/RAM CHIP •
.,
*
***~******.*****.***
VI-39
•• ***********.
CLOCK/RAM DEMONSTRATION MODULE
F8/3810 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
************************************
*
*
* SCRATCH PAD REGISTER DEFINITIONS *
*
*
************************************
=0000
=0001
=0002
=0003
=000.
=0005
=0006
=0007
=0010
=0011
=0012
=0013
=0014
=0015
=0016
*
* GLOBAL REGISTERS. THESE REGISTERS MUST BE THE S4ME
* AS IN THE CLOCK/RAM MODULE.
*
25 PT4IMG EQU OOH
;PORT • IMAGE STORAGE
26 CHIPEN EQU 01H
;CHIP ENABLE STORAGE
EQU 02H
;COMMANO STORAGE
27 CHD
*
* LOCAL REGISTERS. THESE REGISTERS DO NOT NEED TO BE
* MADE KNOWN TO THE CLOCK/RAM MODULE.
*
;TEMPERARY STORAGE
32 TEMP
EQU 03H
33 CNTSAV
EQU O.H
;OIGIT COUNT SAVE
34 DCOUNT
EQU OSH
;OIGIT COUNHR
; TIMER COUNTER
35 TIMCNT EQU 06H
36 CTRL
EQU 01H
;CLOCK/RAM CONTROL STORAGE
; SECOND BUFFER
37 SECOND EQU 10H
38 MINUTE EQU 11H
;MINUTE BUFFER
39 HOUR
EQU 12H
;HOUR BUFFER
40 DAY
EQU 13H
;OAY BUFFER
41 DATE
EQU 14H
;DATE BUFFER
42 MONTH
EQU 1SH
;MONTH BUFFER
43 YEAR
EQU 16H
; YEAR BUFFER
*
*****.****.* ••• ****.
*
*
* PORT DEFINITIONS *
*
*
=0004
=0006
=0007
=OOOC
=0000
=OOOE
=OOOF
********************
*
51 CRDATA
52 TI CTRL
53 TIMER
51+ RXCTRL
55 RXSTAT
56 MSBYTE
51 LSBYTE
*
EQU
EQU
EQU
EQU
EQU
EQU
EQU
OlfH
06H
07H
OCH
ODH
OEH
OFH
;CLOCK/RAM DATA PORT
;TIMER, INTERUPT CTRL PORT
;TIMER PORT
;SERIAL CONTROL PORT
;SERIAL STATUS PORT
;SERIAL MSB PORT
,SERIAL LSB PORT
*****************.***
=0004
=OOOA
=OOOC
=0000
=0013
=001B
65
66
67
68
69
70
*
*
* ASCII DEFINITIONS *
*
***.*** ••••••••••••••*
*
EQU 04H
EOT
EQU OAH
LF
EQU OCt;
FF
EQU ODH
CR
EQU UH
DC3
EQU iBH
ESC
VI-40
;END OF TEXT
; LINE FEED
;FORM FEED
iCARIAGE RETURN
iDEVICE CONTROL 3 (AS)
,ESCAPE
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
.... ** ••• *****
*
*
* CONSTANTS *
*
*
••••• *.*.* •••
*
* DAYS OF THE wEEK
=0001
=0002
=0003
=0001+
=0005
=0006
=0007
=0001
=0002
=0003
=0004
=0005
=0006
=0001
=0008
=000 '3
=OOOA
=0008
=OOOC
=0000
=0001
=0002
=0003
=0004
=0005
=0006
=0001
=0008
=0009
=OOOA
=0010
=OOOF
=OOFO
=0013
=0012
*
EQC 1
80 SUN
81 MON
EQU· 2
EQU 3
82 TUES
EQU 1+
83 WED
EQU 5
84 THURS
(QU 6
85 FR I
EQU 7
86 SA T
*
* MONTHS OF THE YEAR
*
EQU 1
'30 JA N
£QU 2
91 FEB
EQU 3
92 MARCH
EQU 4
93 APRIL
EQU 5
94 MA Y
EQJ 6
'35 JU NE
(QU 7
% JULY
EQU 8
97 AUG
EQU 9
98 SEPT
EQU 10
93 OCT
EQU 11
100 NOV
(QU 12
101 DEC
*
* COUNTER VALUES
*
EQu 0
105 ZERO
EQU 1
106 ONE
EQU 2
107 TwO
108 THREE
t:Qu
3
EQU ,.
109 FOUR
EQU 5
110 FIVE
EQU 6
111 SI X
EQU 7
112 SEVEN
EQU 8
113 EIGHT
EQU 9
114 NINE
EQU 10
115 TEN
116 TENSCD EQU 10H
*
* BCD MASKS
*
EQU OFH
120 LSD
EQU OFOh
121 MSD
*
* LEAP YEAR MASKS
*
EQU
125 LEAP1
[QU
126 LEAP2
*
* ISAR MASK
VI-41
13H
12H
;SUNDAY IS DAY 1
;MONOAY IS DAY 2
;TUESDAY IS DAY 3
;WEDNESDAY IS DAY 4
;THURSDAY IS DAY 5
;FRIDAY IS DAY 6
;SATURDAY IS DAY 7
;JANUARY IS MONTH 1
;FEBRUARY IS MONTH 2
;MARCH IS MONTH 3
;APRIL IS MONTH 4
;MAY IS MONTH 5
;JUNE IS MONTH 6
;JULY IS MONTH 7
,AUGUST IS MONTH 8
;SEPTEMBER IS MONTH 9
;OCTOBER IS MONTH 10
;NOVEMBER IS MONTH 11
;DECE~B£R IS MONTH 12
;COUNT IS 0
,COUNT IS 1
iCOUNT IS 2
i COUNT 13 3
iCOUNT IS 4
,COUNT IS 5
;COUNT IS 6
;COUNT IS 7
;COUNT IS 8
;COUNT IS 9
;COUNT IS 10
; BCD VALUE OF 10
;MASK FOR ONE'S DIGIT
.MASK FCR TEN'S DIGIT
;MASK TC CHECK FOR ?
;MASK TO CHECK FOR?
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC 08J.COD£
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
=003F
*
130 ISMASK
•
EQU
3FH
; MASK TO 6 BITS
* CLOCK/CALENDAR MASKS
=0080
lY+
•
HALT
EQU
80H
iHALT FLAG IS BIT 7 OF
SECO~
S
=0070
=OOOF
=0070
=OOOF
=0080
1.35 SE CMSD
1-36 SECLSD
137 MINMSD
138 MINLSD
1.39 MODE
=0020
=00.30
=0010
=OOOF
=0007
=0030
=OOOF
=0010
=OOOF
=OOFO
=OOOF
140 AMPM
EQU 2011
141 HR2MSD EQL 3011
142 HR1MSD EQU 10H
1'+3 HRLSD
EQU OFI1
144 DA YlSD EQU 07H
145 DATMSD
EQU 30H
146 DA TlSD
EQU OFH
11+ 7 MNMSD
EQU 10H
148 MNLSD
EQU OFH
149 YRMSD
EQU OFOH
150 YRLSD
EQU OFH
*
* TIMER VALUES
*
154 MAXCNT EQU 36
155 TMCTRL EQU OEAH
*
* CHIP ENABLE BITS
=0024
=OOEA
EQU
EQU
EQU
EQU
EOL
70H
OFH
70H
OFH
8011
iSECONDS TEN'S DIGIT
iSECONDS ONE'S DIGIT
iMINUTES TEN'S DIGIT
iMINUTES ONE'S DIGIT
i12/24 HOUR MODE IS BIT 7 OF
HOURS
iAM/PM FLAG IS BIT 5 OF HOU~
;24 HOUR MODE TEN'S DIGIT
;12 HOUR MODE TEN'S DIGIT
iHOURS O~E'S DIGIT
iDAY MASK
iDATE TEN'S DIGIT
iDATE ONE'S DIGIT
iMONTH TEN'S DIGIT
iMONTH ONE'S DIGIT
iYEARS TEN'S DIGIT
iYEARS ONE'S DIGIT
iTIMER MAXIMUM COUNT
iTIMER CONTROL BYTE
•
=0001
=0002
159 DATA
EQU 01H
iDATA 8IT IS BIT 0
EQU 02H
160 CE 1
iCHIP ENABLE BIT IS BIT 1
*
• PARITY FOR TRANSMITTER
=OOFE
104 PARITY
*
EQU
OFEH
iPARITY (BIT 0) IS 'SPACE'
*
=0008
=00A2
=OOBO
=0 OB 1
168
1b9
170
171
* SERIAL PORT VALUES
*
EQU OSH
BAUD
XMIT
EQU OA2H
RCV
EQU 080H
RCVI
EQU 08111
=
;BAUD RATE
9000
;TRANSMIT COMMAND
iRECIEVE COMMAND
iRECIEVE W/INTERUPT
*
=0000
=0002
=008F
=008E
=OOSF
=OOBE
175
176
177
178
179
180
* CLOCK/RAM VALUES
*
CRCTRL EQU OOH
CRCHIP EQU 02H
RDSTAT EQU 8FH
WRSTAT EQU BEH
RDCLK
EQU OeFH
WRCLK
EQU OBEI1
VI-42
;CLK/RAM CONTROL BYTE
;CLK/RAM CHIP ENABLE BYTE
jREAD eLK/RAM STATUS
iWRITE CLK/RAM STATUS
iREAD CLOCK REGISTERS
;WRITE CLOCK REGISTERS
:LOCK/RAM DEMONSTRATION MODULE
F8/3B70 MACRO CROSS ASSM. V2.2
_DC 08J.COOE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
*
*
* INITIALIZATION *
*
*
********.*.*******
*
* FUNCTION:
* THIS IS THE START OF THE DEMO PROGRAM. WHEN THE
* MICROCOMPUTER RESETS DUE TO POWER UP OR A HARDWARE
* (PUSH BUTTON) RESET9 THIS CODE IS ENTERED. THE
* INITIALIZATION CONSISTS OF CLEARING ALL SCRATCH PAD
* REGISTERS, SETTING UP THE CHIP ENABLE PARAMETER,
* SETTING THE SERIAL PORT BAUD RATE AND PARITY,
* AND CHECKING IF THE CLOCK DATA IS VALID. IF IT IS
* NOT VALIC, THE ROUTINE CONTINUE ON TO SET THE CLOCK.
* OTHERWISE, THE DATA IS ASSUMED OK.
*
* ENTRY STATUS:
(1000
(1000
0001
0002
0003
a004
0005
0006
JOoa
70
OB
70
5C
OA
IF
213F
94F8
JOOA 2002
Jooe 51
)000
)OOF
)010
) 0 12
200B
BC
209
210
211
212
213
21'+
21'5
216
217
221
222
226
20FE
227
228
8E
229
)013
2B02AE
)016 '+7
)011 F7
235
236
231
)018 B169
238
* THE CPU HAS BEEN RESET.
*
* EXIT STATUS:
* IF THE CLOCK DATA IS VALID, THEN THE ROUTINE EXITS
* TO THE DATA OK ROUTINE. OTHERWISE, THE ROUTINE
* EXITS TO THE SET CLOCK ROUTINE.
*
* CLEAR SCRATCH PAD
*
ORG OOOOH
CLR
;CLEAR ALL SCRATCH PAD
IS,A
INIT
lR
;PUT POINTER INTO ISAR
CLR
;CLEAR THAT LOACTION
;
LR
StA
lR
;BUMP POINTER
AdS
;BUMP POINTER
INC
ISMASK
NI
;MASK TO 6 BITS
;GO IF NOT DONE
BNZ IN!T
*
* SET UP CLOCK/RAM SUBROUTINE PARAMETERS.
*
LI
LR
CRCHIP
CHIPEN,A
; SET CLK/RAM CHIP ENABLE
*
* I NIT ALIlE SERIAL PORT PARAMETERS.
*
BAUD
; SET SERIAL SAUD RATE
LI
;
GLTS RXCTRl
; SET PAR ITY TO 'SPACE'
PARITY
LI
OUTS MSBYTE
*
* CHECK IF CLOCK/RAM HAS JUST BEEN POWERED UP. IF SO,
* INITIALIZE AND SET THE CLOCK. IF NOT, THEN THE CLOCK
* DATA SHOULD 5£ VALID.
*
PI
STATRD
;REAO ClK/RAM STATUS
A,CTRl
LR
;CHECK WRITE PROTECT BIT
NS
CTRL
BP
DATAOK
;BRANCH IF DATA GOOD
VI-43
CLOCK/RAM DEMONSTRATION MODULE
f8/3870 MACRO CROSS ASSM. V2.2
lOC OBJ.COD£
STMT-NR SQURC£-STMT PASS2 DEMO
DEMO
DEMO
ASS
•
•
• CLOCK/RAM JUST POWERED UP, SO INITAlIZE IT.
OOIA 280286
242
0010 29006C
2it3
PI
JMP
VI-44
STAHIR
SETClK
;WRITE ClK/RAM STATUS
;SET CLOCK
JEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM.
V2.2
OBJ.COD€
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
_OCK/~AM
)C
•• ***.*** ••• **** •• * •••• **.***.*****
*
* TIMER INTERRUPT SERVICE ROUTINE *"
*
"
*" FUNCTION:
* THE TIMER INTERRUPT SERVICE ROUTINE IS ENTERED EVERY
* TIME THE HARDWARE TIMER TIMES OUT (APPROXIMATELY
* EVERY 1/36 SECONDS.) THE TIMER COUNTER IS
" OECREMENTED TO DETERMINE IF 1 SECOND HAS PASSED
* SINCE THE LAST SCREEN UPDATE. IF NOT, THE ROUTINE
* TERMINATES. IF SO, NEW DATA IS READ FROM THE CLOCK/
" RAM AND THE SCREEN IS UPDATED.
"" ENTRY STATUS:
* THE TIMER HAS TIMED OUT.
"
*
EXIT STATUS:
* IF 1 SECOND HAS NOT PASSED, THEN THE COUNTER IS
no
08
)21 00
1122 os
323 01
~20
~24
iJ7
269
2.70
271
272
273
274
" DECREMENTED. OTHERwISE, THE COLNTER IS RESET AND
* THE NEW TIME IS READ FFROM THE CLOCK/RAM AND
" PRINTED.
*
ORG 0020H
K,P
;SAVE STACK
LR
A,KU
LR
QU,A
LR
A,KL
LR
QL,A
LR
"
"
)25 36
)26 941C
128
12A
128
12E
131
134
137
13A
130
2024
56
2802C1
2dOlA,,+
2801CO
2801CC
2J'l01F7
2A05EB
28029F
278
CHECK IF 1 SECOND HAS PASSED SINCE LAST INTERRUPT.
*
279
284
285
286
2137
OS
BNZ
TIMCNT
FINISH
; DECREMENT COUNT
iBRANCH IF NOT ZERO
*
* IT HAS, SO RE SET COuNTER, R£AD NEW CLOCK DATA AND
" DISPLAY IT.
*
LI
LR
PI
PI
PI
PI
PI
DCI
PI
288
289
290
291
292
MAXCNT
THCNT,A
CLKRD
AMP~OT
DAYOT
OATEeT
TI MEOT
HOME
OUHSG
lRESET COUNT
lREAD CLOCK REGISTERS
jPRINT AM/PM MESSAGE
;PRINT DAY
lPRINT DATE
;PRINT TIME
iSEND CURSOR HOME
"
"
PUT SERIAL PORT BACK IN RECEIVE MODE AND RETURN
* FROM INTERRUPT.
140 2081
142 BD
43 13
44 OD
"
297
298
299 FI NISH
300
RCVI
OUTS RXSTAT
;ENABLE RCV INTERUPT
£1
iENABLE INTERUPTS
jRETURN
LI
LR
po,c;
VI-45
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
lOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
**************************************
*
*
* RECEIVER INTERRUPT SERVICE ROUTINE *
*
*
**************************************
*
* FUNCTION:
* THE RECEIVER INTERRUPT SERVICE ROUTINE IS ENTERED
* EVERY TIME A CHARACTER IS RECEIVED IN THE SERIAL
* PORT. THE CHARACTER IS CHECKED FOR 'DC3' (CONTROL
* S). IF NOT A 'CC3'9 THEN THE ROUTINE IS TERMINATED.
* OTHERWISE, THE USER IS ALLOWED TO SET THE CLOCK
* VALUES.
*
* ENTRY STATUS:
* A CHARACTER HAS BEEN RECEIVED FROM THE KEYBOARD •
•
* EXIT STATUS:
* IF THE CHARACTER WAS NOT A 'DC3', THEN A RETURN
0060
0060
0061
0062
0063
0064
08
00
06
01
07
324
325
326
327
328
329
* FROM INTERRUPT IS DONE. OTHERWISE, THE ROUTINE
* EXITS TO THE SET CLOCK ROUTINE.
*
ORG
LR
LR
LR
LR
LR
0060H
K,P
A,KU
QU,A
A.KL
QLtA
*
• THIS KEY FOUND •
*
334
PI
INCHR2
335
CI
DC3
BNZ FINISH
336
;SAVE STACK
* CHECK FOR 'DC3' FROM KEYBOARD. SET THE CLOCK IF
0065 280287
0068 2513
006A 9408
*
;GET CHARACTER
; CHECK FOR 'DC3'
;BRANCH IF NOT
* WAS 'OC3', SO FALL THROUGH TO SET CLOCK.
VI-46
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.COOE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
.***************.
•
•
•
•
•
SET THE CLOCK •
*****************
•
• FUNCTION:
• THIS ROUTINE ALLO~S THE USER TO SET THE CLOCK AND
• CALENDAR SETTINGS.
•
• ENTRY STATUS:
• EITHER THE CLOCK DATA WAS INVALID AT POWER UP OR
• THE USER ENTERED A 'DC3' FROM THE KEYBOARD.
•
• EXIT STATUS:
• ALL CLOCK/CALENDAR SETTINGS ARE SET.
006C 68
0060 62
006E 2800AB
0071 280126
OOH 280096
0077 810~
0079 2800BC
001C 280000
007F 2802C9
*
357 SETCLK
358
359
360
361
362
363
364 SEll
365
LISL
LISU
PI
PI
PI
BP
PI
PI
PI
SECOND.AND.7 ;POINT TO CLOCK BUFFER
SECONO.SHR.3 ;
DAVIN
;SET DAY OF WEEK
;SET DATE IN CALENDAR
DATEIN
;SET 12/2~ HOUR MODE
MOCEIN
SEll
;BRANCH IS 24 HOUR MODE
AMPPIIN
; SET AM/PM flAG
TIMEIN
;SET TIME IN CLOCK
;WRITE DATA TO CLOCK
CLKWR
*
• CLOCK NOW SET, SO FALL THROUGH TO START INTERRUPTS.
VI-47
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STHT PASS2 DEMO
DEHO
DEMO
ABS
*************************
*
*
* SET UP FOR INTERRUPTS *
*
*
*************************
*
*
*
*
*
*
FUNCTION:
THIS ROUTINE INITIALIZES THE TIMER AND SERIAL PORT
AND EN~BLES INTERRUPTS.
ENTRY STATUS:
* EITHER THE DATA WAS VALID AT POWER UP, OR THE CLOCK
* HAS JUST BEEN SET.
*
* EXIT STATUS:
* THE TIMER AND RECEIVER INTERRUPTS ARE THE ONLY EXIT.
0082
0083
0084
0086
0087
0089
008A
0080
0090
0092
*
70
B7
2024
56
20EA
B6
386 OATAOK
387
388
389
390
2A02DF
392
393
394
395
396
397 STOP
28029F
2081
BO
0093 18
0094 90FF
391
CLR
OUTS TIMER
MAXCNT
LI
LR
TIMCNTtA
TMCTRl
LI
OUTS TICTRL
OCI SIGNON
PI
OUTMSG
LI
ReVI
OUTS RXSTAT
E1
BR
STOP
VI-48
; CLEAR TIMER
;
;SET COUNTER
;SET TIMER CONTROL
;
;PRINT HATURES
;
iENABLE RCV INTERUPT
iENABLE INTERUPTS
iWAIT FOR 1NTERUPT
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASS~.
V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
******.*********************.**** •• *
*
*
* 12/24 HOUR MODE INPUT SUBROUTINE *
*
*
************************************
*
*
FUNCTION:
*
*
12 OR 24 HOUR FORMAT. THE ANSWER IS AQUIRED, AND THE
PROPER MODE IS SET.
* THIS SUBROUTINE ASKS THE USER IF THE MODE IS TO BE
*
* ENTRY STATUS:
* NONE.
*
*
*
0096
00'37
0098
0099
O09A
009B
009E
OOA1
OOA2
OOA5
00A6
00A7
OOAa
00A9
OOAA
08
00
06
01
07
2A0611
28029F
*
416 MODEIN
417
418
419
420
421
if 22
6A
423
28023'+
'+24
425
'+26
427
428
429
430
15
13
13
13
5C
00
EXIT STATUS:
THE MODE IS SET FOR 12 OR 24 HOUR OPERATION.
LR
LR
LR
LR
LR
DCI
PI
LISL
PI
SL
SL
SL
SL
LR
LR
K,P
AtKU
QU,A
A,KL
QLtA
MODMSG
OUTMSG
HOUR.AND.7
o IGIT2
4
;SAVE STACK
;PRINT MODE MESSAGE
;POINT TO HOURS
;GET DIGIT (0-1)
; PUT INTO BIT 7
1
1
1
S.A
pate
VI-49
;STORE IT AT HOURS
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3810 MACRO CROSS ASSM. V2.2
LOC DBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
*
*
* DAY INPUT SUBROUTINE *
*
*
************************
*
* FUNCTION:
* THIS SUBROUTINE ASKS THE USER FOR THE DAY AND
* INPUTS THE ANSWER.
*
* ENTRY STATUS:
* NONE.
*
OOAB
OOAC
OOAD
OOAE
OOAF
OOBO
OOB~
0086
0087
OOBA
OOBB
OB
HB
00
06
01
01
2A05FO
28029F
68
2B0222
5C
00
449
450
'+51
'+52
453
'+54
455
456
457
458
* EXIT STATUS:
* THE DAY OF THE WEEK IS
*
K,P
DAYIN
LR
A,KU
LR
QU,A
LR
A,KL
LR
LR
GL.A
DCI DA H'SG
OUTMSG
PI
LISL OAY.AND.l
OIGIl7
PI
S,A
lR
PO,Q
lR
VI-50
IN THE DAY BUFFER.
;SAVE STACK
;
;PRINT DAY MESSAGE
;POINT TO DAY
; GET DIGIT (1-1)
;STORE IT AT DAY
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
***.*********** ••• ******.********
*
*
.*
AM/P~
*
SELECT INPUT SUBROUTINE *
******t****.****~*************
*
•••
*
*
*
*
*
FUNCTION:
THIS SUBROUTINE ASKS THE USER FOR THE AM OR PM
SETTING. THE ANSWER IS AQUIRED AND THE PROPER MODE
IS SET. THIS ROUTINE IS CALLED IN THE 12 HOUR
* MODE ONLY.
*
* ENTRY STATUS:
* NONE.
*
* EXIT STATUS:
* THE AM/PM FLAG IS SET OR RESET IN THE HOUR BUFFER.
OOBC
OOBD
DOBE
DOBF
OOCO
OOCI
00C4
DOC7
00C8
00C8
OOCC
OOCO
OOCE
OOCF
08
00
0&
01
*
H8 AMPMIN
EC
5C
479
480
481
482
483
484
485
486
487
'+88
'+89
490
00
491
07
2A0631
28029F
6A
280234
15
13
LR
LR
LR
LR
LR
DCI
PI
LISL
PI
SL
SL
XS
LR
LR
K,P
. iSAVE STACK
A,KU
QU,A
A,KL
QL,A
AMPMSG
;PRINT AM/PM MESSAGE
OUTMSG
HOUR.AND.7 ;POINT TO HOURS
,GET DIGIT (0-1)
DIGIT2
;PUT INTO BIT 5
'+
1
;
S
S,A
;STORE IT AT HOURS
PO,Q
;RETURN
VI-51
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
**.**********************
*
*
* TIME INPUT SUBROUTINE *
*
*
************* •• * •• ****~**
0000
0001
0002
0003
0004
0005
0008
08
00
06
!l1
07
2A0648
28029F
*
*
*
*
*
*
*
*
*
*
*
*
*
*
FUNCTION:
THIS SUBROUTINE ASKS THE USER FOR THE TIME. IT
INPUTS THE TIME AND SETS THE CLOCK UP ACCORDINGLY.
THE TIME IS INFUT IN THE HR:MIN:SEC FORMAT. lEADING
ZEROS MUST BE INPUT.
ENTRY STATUS:
NONE.
EXIT STATUS:
fHE TIME OF DAY IS SET IN THE HOUR, MINUTE. AND
SECOND BUFFER.
512 TIMEIN
513
514
515
516
517
518
LR
lR
LR
LR
LR
DCI
PI
K,P
A,KU
QU,A
A,KL
Ql,A
TIMMSG
OUTMSG
;SAVE STACK
;
;PRINT TIME MESSAGE
*
* CHECK IF 12 OR 24 HOUR MODE.
OODB
OODC
0000
OODE
OOEO
00E3
00E5
00E6
00E7
00E8
00E8
OOEC
OOED
OOEF
00F2
OOFit
OOF7
OOF8
00F9
OOF8
OOFO
0100
6A
4C
FC
8115
280234
840B
15
EC
5C
280239
EC
5C
901B"
28022A
90F8
280239
15
5C
2520
B408
280240
EC
522
523
524
525
*
LISL
LR
NS
BP
HOUR.AND.7
A,S
;POINT TO HOURS
;CHECK IF 24 HOUR MODE
S
;
HOUR24
;BRANCH IF SO
*
* 12 HOUR MODE, SO VALID HOURS ARE 01-12.
*
529
530
531
532
533
534
535 HOURi
536
537
538 HOUROX
539
PI
BZ
SL
XS
LR
PI
XS
LR
BR
PI
BR
DIGIT2
HOUROX
4
S
StA
DIGIT3
S
S,A
MIN
DIGIT9
HOURl
GET CIGIT (0-1)
;BRANCH IF 0 ENTERED
;STORE IT AT TENS
; GET DIGIT (0-2)
;STORE IT AT UNITS
;GO TO MINUTES
; GET DIGIT (1-9)
;STORE IT AND CONTINUE
*
* 21t HOUR MODE, SC VALID HOURS ARE 00-23.
*
(0-2)
5lt3 HOUR21t
5'14
5lt5
546
51f7
548
5lt9 HOUR2
PI
Sl
LR
CI
BZ
PI
DIGIT3
4
S,A
TWC.SHL.4
HOUR2X
DIGITO
XS
S
VI-52
; GET DIGIT
;STORE IT AT TENS
;
;SEE IF DIGIT WAS '2'
iBRANCH IF SO
; GET DIGIT (0-9)
;STORE IT AT UNITS
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 ~ACRO CROSS ASSM.
V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
0101
0102
010'+
0107
5C
9006
28023E
90F8
550
551
552 HOUR2X
553
LR
BR
PI
BR
S,A
MIN
DIGIT.
HOUR2
iGO TO MINUTES
iGET DIGIT (0-3)
iSTORE AND CONTINUE
*
* VALID MINUTES ARE 00-59.
0109
010C
0100
0110
0111
0112
0115
0116
0117
OllA
OllB
011E
ollF
0120
0123
012'+
0125
*
28026A
69
280243
15
5C
28024D
557 MIN
558
559
560
561
562
£C
563
5C
564
28026A
£:.3
280243
15
5C
2802'+0
EC
5C
00
568
569
570
571
572
573
PI
LISL
PI
SL
LR
PI
XS
LR
OUTCOL
iPRINT COLON SEPARATOR
MINUTE.AND.7 ;POINT TO MINUTES
DI6IT6
iGET DIGIT (0-5)
'+
iSTORE IT AT TENS
S,A
DIGIlO
i GET DIGIT (0-3)
S
;STORE IT AT UNITS
S,A
*
* VALID SECONDS ARE 00-59
*
PI
LISL
PI
SL
lR
57'+
515
PI
XS
LR
576
lR
VI-53
DUTCOL
iPRINT COLON SEPARATOR
SECOND.AND.7 ;POINT TO SECONDS.
DIGIT6
;GET DIGIT (0-5)
4
iSTORE IT AT TENS
S,A
i
; GET DIGIT (0-9)
DIGITO
iSTORE IT AT UNITS
S
;
StA
PO,G
; RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBd.CODE
STMT-NR SOURCE·STMT PASS2 DEMO
DEMO
DEMO
ABS
•••••• * ••• * ••••••••• * ••••
•
•
•
DATE INPUT SUBROUTINE •
•
•
•
•
•
•
•
FUNCTION:
THIS SUBROUTINE ASKS THE USER FOR THE DATE. IT
INPUTS THE DATE AND SETS THE CALENDAR ACCORDINGLY.
THE DATE IS INPUT IN THE YR:MNTH:DAY FORMAT.
LEADING ZEROS MUST BE INPUT.
*****.******* •• * •• ******.
*
• ENTR Y ST HUS:
• NONE.
•
• EXIT STATUS:
• THE DATE IS IN THE YEAR, MONTH, AND DATE BUFFER.
0126
0127
0128
0129
012A
012B
012E
08
00
06
01
07
2A05FD
28029F
•
596 DAfEIN
597
598
599
600
601
602
•
•
0131 6E
0132 280240
0135 15
0136 5C
0137 280240
. OUA EC
0138 5C
013C
013F
0140
0143
0144
0145
o1't1
28026A
60
280234
15
5C
8408
280239
EC
5C
9006
28022A
014A
014B
014C
014E
0151 90F8
606
607
608
609
610
611
612
•
•
•
•
•
0153 28026A
•
K,P
A,KU
QU,A
A,KL
QL,A
DATMSG
OunSG
;SAVE STACK
;PRINT DATE MESSAGE
VALID YEARS ARE 00-99.
LISL
PI
SL
LR
PI
XS
LR
YEAR.AND.7
DIGITO
4
S,A
DIGnO
s
;POINT TO YEAR
; GET DIGIT (0-9)
;STORE IT AT TENS
;
; GET DIGIT (0-9)
;STORE IT AT UNITS
S,A
VALID MONTHS ARE 01-12.
616
617
618
613
620
&21
622
623 MONTHl
624
625
626 MNTHOX
627
•
•
•
•
LR
LR
LR
LR
LR
DCI
PI
PI
LISL
PI
SL
LR
B2
PI
XS
LR
BR
PI
8R
OUTCOL
MONTH.AND.7
DIGIT2
'+
S,A
MNTHOX
DIGIT3
S
S,A
DDATE
DIGIT9
MONTH1
;PRINT COLON SEPARATER
;POINT TO MONTH
; GET DIGIT (0-1)
;STORE IT AT TENS
.•
;BRANCH IF DIGIT IS '0'
; GET DIGIT (0-2)
;STORE IT AT UNITS
;
;GO TO DATE
; GET DIGIT <1-9)
;STORE AND CONTINUE
CHECK MONTH. IF MONTH IS FEBURARY, ALLOW 28 OR
29 DAYS IN THE MONTH. IF MONTH IS APRIL, dUNE,
SEPTEMBER OR NOVEMBER, ALLOW 30 DAYS IN THE
MONTH. FOR OTHER MONTHS, ALLOW 31 DAYS.
63'+ ooATE
PI
OUTCOL
VI-54
;PRINT COLON SEPARATOR
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OSJ.CODE
STMT-NR SOURCE-8TMT PASS2 DEMO
DEMO
DEMO
ASS
0156 4E
0157 2502
0159 842f
LR
CI
BZ
635
636
637
A,e
FEB
FEBXX
;GET MONTH, POINT DATE
;CHECK IF 'FEBRUARY'
;BRANCH IF SO
*
* NOT FEBRUARY, SO ALLOW 30 OR 31 DAYS.
015B 28023E
015E 15
015F 5C
641
0160 840B
0162 2530
644
01M 840C
0166
0169
016A
016B
016C
016F
*
642
6li3
645
646
28024D
647 DDATE3
EC
5C
648 ODATE1
649
00
28022A
650
651 OAYOX
90F9
652
PI
SL
LR
BZ
CI
BZ
PI
XS
LR
LR
PI
BR
DIGIT'+
; GET DIGIT (0-3)
4
iSTORE IT AT TENS
S,A
DAYOX
THREE.SHL.4
DAnx
OIGITO
S
StA
PO,Q
01 GIT9
OOATE1
;BRANCH IF DIGIT WAS 0
;CHECK IF DIGIT WAS '3'
;BRANCH IF SO
; GE T 0 I GIT ( 0-9 )
;STORE IT AT UNITS
;
;RETURN
;GET DIGIT (1-9)
;STORE AND RETURN
*
* CHECK FOR APRIL, JUNE, SEPTEMBER AND NOVEMBER.
0171
0172
01H
0175
0175
0119
017A
*
60
656 OA OX
200li
657
55
4E
2A02DB
658
80
8'+09
661 OLOOP
017C 35
0170 94fB
017F 28023't
659
660
662
663
664
665
LISL MONTH.AND.7 ;POINT TO MONTH
'+
;LOOP COUNT
'+
LI
LR
LR
OCI
CM
BZ
OS
BNZ
PI
DcaUNT,A
AtO
TAB30
DAno
DcaUNT
OLeop
OIGIT2
=
;GET MONTH, POINT DATE
;POINT TO 30-0AY TABLE
;CHECK IF IN TABLE
,BRANCH If SO
,DECREMENT COUNT
;BRANCH IF NOT DONE
;GET DIGIT (0-1)
*
0182 90E6
0184 28022F
0187 90E1
* 31 DAY MONTH, SO ALLOW DAYS OF 01-31.
*
;STORE AND RETURN
669
BR
DOATE!
*
* 30 DAY MONTH, SC ALLOW DAYS OF 01-30.
613
*
DAY30
674
PI
BR
DIGITI
DOATEI
*
;GET DIGIT (0)
;STORE AND RETURN
* FEBRUARY, SO ALLOw 28 OR
0189 28023'3
018C 15
0180 5C
018E 84DO
0190 2520
0192 9,+03
0191+ 5E
0195 4C
0196 OC
*
29
DAYS.
678 FEBXX
679
680
681
PI
DIGIT3
SL
'+
iGET DIGIT (0-2)
;STORE IT AT TENS
LR
682
CI
BNZ
S,A
OAYOX
TWG.SHL.4
DDATE3
;BRANCH IF DIGIT WAS a
;CHECK IF DIGIT WAS '2'
;BRANCH IF NOT
683
687
688
689
0197 2113
690
0199 84CC
691
8Z
*
* CHECK IF IT IS A LEAP YEAR.
*
;POINT TO YEAR
LISL YEAR.AND.7
A,S
;G£T YEAR
LR
;POINT TO DATE
LISL DATE.AND.7
LEAP1
iCHECK IF LEAP YEAR
NI
.BRANCH IF IT IS
DDATE3
BZ
VI-55
F8/3a10 MACRO CROSS ASSM. V2.2
CLOCK/RAM DEMONSTRATION MODULE
STMT-NR SOURCE-STMT PASS2'DEMO
LOC 08.1.CODE
DEMO
DEMO
ASS
019B 2312
0190 8~C8
692
693
XI
BZ
LEAP2
DDATE3
;CHECK AGAIN
; BRANCH IF IT IS
*
019F 2802~8
01A2 90C6
691
698
* NOT A LEAP YEAR, S C ALLOW DAYS OF 01-28.
*
PI
BR
VI-56
DIGIT8
DDATEl
; GET DIGIT (0-8)
;STORE AND RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
*
*
* AM/PM PRINT SU8ROUTINE *
*
*
**** ••• *****.*.*.* ••• *****
*
* FUNCTION:
* THIS SUBROUTINE PRINTS THE MESSAGE 'GOOD MORNING'
* IF THE AM/PM BIT IS CLEAR, OR 'GOOD AFTERNOOD' IF
* THE AM/PM BIT IS SET.
*
* ENTRY STATUS:
* THE MODE AND AM/PM 8ITS MUST BE IN THE HOUR BUFFER.
*
* EXIT STATUS:
* IF THE MeDE IS 12 HOUR, THEN THE 'GOOD MORNING' OR
* 'GOOD AFTERNOON' MESSAGE WAS PRINTED (DEPENDING ON
* THE STATUS OF THE AM/PM BIT.) OTHERWISE, THE FIRST
* LINE OF THE CRT WAS 8LANKED.
OlH 08
OlAS 2A05l2
01A8 28029F
OlAB 6A
OlAC IfC
DIAD FC
alAE 3110
OlBO
0181
01B2
018 '+
0187
01B9
olBC
OlBF
13
13
810b
2A0527
9004
2A0519
28029F
OC
*
720 AMPMOT
721
722
727
728
729
730
LR
DCI
PI
K,P
GOODPT
OUTMSG
;SAVE STACK
;CURSOR TO LINE 1
*
* CHECK IF IN 12 OR 24 HOUR MODE. SKIP THIS
* ROUTINE IF 24 HOUR MODE.
*
llSL
LR
NS
BP
HOUR.AND.7
A,S
S
ML TRYl
;POINT TO HOURS
;CHECK 12/24 HOUR BIT
;SET FLAGS
;BRANCH IF 24 HOUR
*
* 12 HOUR MODE, SO CHECK AM/PM FLAG. PRINT 'GOOD
* MORNING' IF AM, 'GOOD AFTERNOON' IF PM.
*
735
736
737
738
739
740 AMPMI
741 AMPM2
742 ML TRYl
SL
SL
BP
DCI
BR
DCI
PI
PK
1
;CHECK AM/PM FLAG
1
AMPMI
GDAFTR
AMPM2
GDMORN
OUHSG
VI-57
;BRANCH IF AM
;POINT TO PM MSG
; CONTINUE
;POINT TO AM MSG
;PRINT MESSAGE
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ASS
~*****.*****************
*
* DAY PRINT SUBRCUTINE *
*
*
*
***********************.
*
* FUNCTION:
* THIS SUBROUTINE PRINTS THE DAY.
*
* ENTRY ST ATUS:
* THE DAY OF THE WEEK MUST BE IN THE DAY BUFFER.
*
* EXIT STATUS:
01CO
01C1
DICit
01Cl
01C8
01C8
08
2A0537
28029F
6B
280295
ac
* THE DAY IS PRINTED ON THE CRT.
*
759 DAYOT
760
761
762
763
76'+
LR
DCI
PI
LISL
PI
PK
VI-58
K,P
OAYPT
OUTMSG
OAY.AND.7
FNDCUT
;SAVE STACK
;CURSOR TO LINE 3
;
;POINT TO DAY
;PRINT DAY MESSAGE
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM.
V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
.
****************A***** •••
..
* DATE PRINT SUBROUTINE ..
*
..
****************.********
..
* FUNCTION:
.. THIS SUBROUTINE PRINTS THE DATE •
.
..
..
..
*
*
..
..
OlCC 08
OlCD 2A0516
0100 28029F
0103 60
*
4C
2110
IfC
8405
210F
OlOC 2'+OA
OlDE 5C
OlDF
01[2
01[3
01E6
01E9
01EC
01EF
01FO
280295
6C
280278
28027E
2A05DF
28029F
oE
280278
01F3 28027E
01F6 OC
EXIT ST ATUS:
THE DATE IS PRINTED ON THE CRT •
782 DATEOT
783
184
785
....
0104
0105
0107
0108
01DA
ENTRY STATUS:
THE DATE MUST BE IN THE YEAR, MONTH, AND DATE
BUFFERS.
789
805
806
807
808
809
K,P
;SAVE STACK
DATEPT
;CURSOR TO LINE 5
OUTMSG
MONTH.ANO.7 ;POINT TO MONTH
MAKE BCD MONTH BINARY •
790
791
192
793
794
795 DATEI
800
801
802
803
80lf
LR
DCI
PI
LISL
LR
NI
LR
BZ
NI
AI
LR
*
* FIND MONTH
* THEN PRINT
*
PI
LISL
PI
PI
DCI
PI
LISL
PI
PI
PK
VI-59
A,S
TENSCD
A,S
DATEI
MNLSD
TEN
S,A
;GET MONTH
;SEE IF MONTH> 9
;RECALL MONTH
;BRANCH IF <= '"
;KEEP ONLY LSD
;AOO 10
;PUT IT ALL BACK
IN MESSAGE AREA AND PRINT IT.
DATE ANC YEAR.
FNDOUT
DATE. AND. 7
OUTMSO
OUTLSD
SEPAR
OUTMSG
YEAR.ANO.7
OUT~SD
;PRINT MONTH
;POINT TO DATE
;PRINT DATE
;PRINT SEPARATER
;POINT TO YEAR
,PRINT YEAR
OUTLSD
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSH. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT·PASS2 DEMO
DEMO
DEMO
ABS
*************.***.*******
•
*
• TIME PRINT SUBROUTINE.
•
•
•••••••••••••••••••••••••
•
• FUNCTION:
• THIS SUBROUTINE PRINTS THE TIME.
•
• ENTRY STATUS:
• THE TIME MUST 8E IN THE HOUR, MINUTE, AND SECOND
• BUFFERS.
•
• EXIT STATUS:
• THE TIME IS PRINTED ON THE CRT.
01F7 08
01F8 2A0'5E4
01F8 28029F
•
827 TI MEOT
828
829
•
lR
DCI
PI
K,P
TI MEPT
OUTMSG
;SAVE STACK
;CURSOR TO LINE 7
• CHECK IF 12 OR 24 HOUR MODE. FOR 12 HOUR MODE,
• FLAGS MUST BE STRIPPED FROM HOURS BYTE.
01H 6A
01FF
0200
0201
0203
0204
0206
4C
FC
8105
4C
211F
5C
834
835
836
837
838
839
840
•
•
LISl
lR
NS
BP
lR
NI
LR
HOUR.AND.l ;POINT TO HOURS
A,S
;CHECK 12/24 HOUR BIT
S
;
MLTRY2
;BRANCH IF 24 HOUR
A,S
;STRIP FLAGS FROM HOURS
HRIMSD+HRLSD ;
S,A
• PRINT HOURS, MINUTES AND SECONDS.
0207
020A
0200
0210
0211
0214
0217
021A
0218
021E
0221
280278
28027E
28026A
69
280278
28027E
28026A
68
280278
28021£
OC
•
844 ML TRY2
845
846
847
848
849
850
851
852
853
854
PI
PI
PI
LISL
PI
PI
PI
LISL
PI
PI
PK
VI-60
OUTMSD
;PRINT HOURS
OUnSD
OUTCOL
;PRINT COLON
MINUTE.AND.7 ;POINT TO MINUTES
OUTMSD
;PRINT MINUTES
OUTLSD
OUTCOL
;PRINT COLON
SECOND.AND.7 ;POINT TO SECONDS
OUTMSD
;PRINT SECONDS
OUTLSD
;
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3d70 ~ACRO CROSS ASSM. V2.2
LOC 08J.CODE
STMT-NR SOURCE-STMt PASS2 DEMO
DEMO
DEMO
ABS
************************
*
*
* GET DIGIT SUBRCUTINE *
*
*
****.*****.****** ••• ****
•
• FUNCTION:
* THIS SUBROUTINE, ~ITH IT'S VARIOUS ENTRY POINTS,
* GETS A DIGIT FROM THE KEYBOARD AND ECHOS IT TO THE
* CRT.
*
* ENTRY STATUS:
* THE RANGE IS SPECIFIED BY A CALL TO THE APPROPRIATE
* ENTRY POINT.
•
* NORMAL EXIT STATUS:
* THE DIGIT IS ECHOED TO THE CRT, AND RETURNED
* IN A AS A BINARY VALUE.
*
* ERROR EXIT STATUS:
* THE CHARACTER IS ~OT ECHOED TO THE CRT, AND THE
• ROUTINE LOOPS BACK FOR ANOTHER CHARACTER UNTIL
* A CHARACTER THAT IS IN THE RANGE IS INPUT.
*
0222
0223
0225
0228
08
2007
2A02D2
902A
022A 08
0228 2009
0220 90F7
022F 08
0230 2001
0232 9010
882
883
884
885
* GET DIGIT (1-7) SUBROUTINE
*
LR
K,P
01 GIT7
;SAVE STACK
;COUNT :: 7
LI
SEVEN
OCI TAB19
;POINT TO SECOND TABLE
DGT
BR
DIGITT
i GO GET A DIGIT
•
• GET DIGIT (1-9) SUBROUTINE
*
889 DIGIT9 LR
KtP
iSAVE STACK
;COUNT :: '3
890
LI
NINE
891
BR
DGT
; GO G£T A DIGIT
•
* GET DIGIT
*
895 01 GIll
LR
896
LI
897
BR
(0)
SUBROUTINE
K,P
ONE
DIGIT
;SAVE STACK
iCOUNT :: 1
;GO GET A DIGIT
*
* GET DIGIT (0-1) SUBROUTINE
•
K,P
TWO
01 GIT
0234 08
0235 2002
0237 9018
901 DIGIT2
LR
902
903
LI
0239 08
023A l003
023C 9013
* GET DIGIT (0-2) SUBROUTINE
*
K,P
;SAVE STACK
907 01 GIT3 LR
;COUNT :: :3
908
LI
THREE
OIGIT
;60 GET A DIGIT
909
BR
•
BR
•
iSAVE STACK
;COUNT :: 2
; GO GET A DIGIT
• GET DIGIT (0-3) SUBROUTINE
*
VI-61
CLOCK/RAM DEMONSTRATION MODULE
F8/387a MACRO CROSS ASSH. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
023E 08
023F 200lt
02H 900E
913 01 GITit
9H
915
LR
LI
BR
K,P
FOUR
DIGIT
;SAVE STACK
iCOUNT
If
; GO GET A DIGIT
=
*
* GET DIGIT (0-5) SUBROUTINE
OH3 08
02H 2006
0246 9009
*
919 DIGIT6
920
921
LR
LI
BR
K,P
SIX
DIGIT
; SAVE STACK
;COUNT
6
; GO GET A DIGIT
=
*
* GET DIGIT (0-8) SUBROUTINE
0248 08
0249 2009
OHB 9004
*
925 01 GIT8
926
lR
927
BR
LI
K,P
NINE
DIGIT
;SAVE STACK
;COUNT: 9
; GO GET A DIGIT
*
* GET DIGIT (0-9)
0240 08
OHE 200A
0250 2A02D1
•
931 DIGITO
932
933 DIGIT
LR
Ll
DCI
K,P
TEN
TAB09
;SAVE STACK
;COUNT : 10
iPOINT TO 0-9 TABLE
*
* SAVE COUNT AND POINTER IN CASE A CHARACTER IS
• ENTERED WHICH IS NOT WITHIN RANGE.
0253 51+
025'+
0255
0256
0251
025A
025B
0250
025E
11
55
10
280283
80
8lt07
35
'HFB
0260 1+'+
0261 90F3
026!
02E6
0267
0269
280260
43
210F
ac
*
938 01 GITT
939
'HO DGTBAo
9H
91+2
LR
LR
LR
LR
PI
CM
B.Z
OS
BNZ
LR
BR
CNTSAV.A
H,DC
DCOUNT.A
DC,H
INCHR
943 DGTLOP
9H
OGTCK
945
OCCUNT
DGTLOP
946
A,CNTSAV
9H
948
DGTBAD
*
* GOT A VALID CHARACTER,
• AND MAKE IT BINARY.
*
OUTCHR
953 DGTOK
PI
95'+
LR
A.TEMP
955
NI
LSD
956
PK
VI-62
;SAVE COUNT FOR ERROR
;SAVE POINTER FOR ERROR
;SAVE COUNT
iPOINT TO TABLE
;GET A CHARACTER
;SEE IF IT IS IN TABLE
;BRANCH IF IT IS
;DECREMENT COUNT
;BRANCH IF NOT DONE
;RESET COUNTER
;TRY AGAIN
SO ECHO IT TO SCREEN
;ECHO CHARACTER
;MAKE IT BCD
;RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM.
V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
.*.***********************.****
*
*
* CHARACTER OUTPUT SUBROUTINE *
*
*
******************************.
*
*
*
*
*
*
*
*
*
*
*
FUNCTION:
THIS SUBROUTINE, WITH IT'S VARIOUS ENTRY POINTS,
OUTPUTS THE SPECIFIED CHARACTER TO THE CRT.
ENTRY STATUS:
THE CHARACTER TO BE OUTPUT IS DETERMINED BY THE
ENTRY POINT TO THE ROUTINE.
EXIT STATUS:
THE CHARACTER IS OUTPUT TO THE CRT.
*
* OUTPUT COLON SUBROUTINE
026A 203A
026C 53
0260
026F
0270
0271
0272
0273
0214
0275
0217
20A2
BD
43
13
BF
AD
13
B1FO
lC
*
I : t
;LOAD COLON INTO TEMP
977 OUTCOL LI
TEMP,A
978
LR
*
* CHARACTER OUTPUT SUBROUTINE
*
* THE CHARAC TER IS OUTPUT FROM REGISTER TEMP.
*
984 OUTCHR
985
986
987
988
989 LOOP1
990
991
992
LI
OUTS
LR
SL
OUTS
INS
SL
BP
POP
XMIT
RXS TA T
A,TEMP
1
LSBYTE
RXSTAT
;PUT INTO XMIT MODE
; GET CHARACTER
;START BIT
0
; SEND IT
;WAIT TILL IT'S SENT
=
1
LOOP1
;RETURN
*
* OUTPUT MOST SIGNIFICANT DIGIT SUBROUTINE
*
* THE DIGIT IS OUTPUT FROM BITS 7-4 OF THE BYTE A
* THE LOCATION POINTED TO BY ISAR.
0278 IfC
0219 14
027A 2230
onc
90EF
021E IfC
027F 210F
0281 90FB
*
999 OUTMSD
1000
1001 ASCII
1002
LR
SR
01
BR
A,S
;GET MSD
4
030H
OUTCOL+2
; MAKE IT ASC II
;SEND IT OUT
*
* OUTPUT LEAST SIGNIFICANT DIGIT SUBROUTINE
*
* THE DIGIT IS OUTPUT FROM BITS 3-0 OF THE BYTE AT
* THE LOCATION POINTED TO BY ISAR.
*
1009 OUTLSD
1010
1011
LR
NI
BR
A,S
LSD
ASCII
VI-63
;GET LSD
;MAKE IT ASCII AND PRINT
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
lOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
******************************
*
*
* CHARACTER INPUT SUBROUTINE *
*********.*.****t***************
*
* FUNCTION:
* THIS SUBROUTINE INPUTS A CHARACTER FROM THE
* KEYBOARD.
*
* ENTRY STATUS:
* NONE.
*
* EXIT STATUS:
0283
0285
0286
0287
0288
028A
028B
028C
0280
028E
028F
0290
0291
0292
0293
029'+
20BO
BO
AF
AD
81FE
AF
14
12
12
53
AE
13
13
£3
S3
1C
* THE CHARACTER IS RETURNED IN A IN ASCII FORMAT.
*
1029 INCHR
1030
1031
1032 INCHR2
1033
1034
1035
1036
1037
1038
1039
10'+0
1041
10'+2
10'+3
10'+'+
LI
OUTS
INS
INS
BP
INS
SR
SR
SR
LR
INS
SL
SL
XS
LR
POP
VI-64
RCV
RXSTAT
LSBYTE
RXSTAT
INCHR2
LSBYTE
4
1
1
TEMP,A
MSBYlE
1
1
TEMP
TEMPt A
;PUT INTO RCV MODE
;
;CLEAR READY BIT
;WAIT TILL INPUT READY
;
;GET BITS 1 AND 0
;SAVE THEM
;GET BITS 7 THRU 2
;
;MIX BITS INTO BYTE
;SAVE INPUT
; RETURN
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ASS
****************************
..
....
..
PRINT MESSAGE SUBROUTINE ..
..************** •• ************
.. FUNCTION:
.. THIS SUBROUTINE PRINTS THE MESSAGE WHOSE NUMBER I
.. IN THE LOCATION AT THE POINTER •
..
..
..
..
..
..
..
ENTRY STATUS:
ISAR MUST POINT TO THE LOCATION CONTAINING THE
NUMBER OF THE MESSAGE TO BE PRINTED. (TYPICALLY
THE NUMBER OF THE MONTH OR DAY.) DC MUST POINT TO
THE START OF THE STRING OF MESSAGES. EACH MESSAGE
MUST END WITH AN 'EOT' CHARACTER •
..
EXIT STATUS:
THE APPROPRIATE MESSAGE WAS PRINTED ON THE CRT •
...
..
0295 3C
0296 8408
02S8 16
0299 2504
0298 94FC
0290 90F7
1066 FNDOUT
1067
1068 FNOLCP
1069
1070
1071
....
OS
8Z
LM
CI
BNZ
BR
S
OUnSG
EOT
FNCLOP
FNDOUT
; DECREMENT MSG COUNT
;BRANCH IF FOUND
;GET CHARACTER
;CHECK FOR END OF TEXT
;BRANCH IF NOT FOUND
;ELSE, CHECK COUNT
MESSAGE LOCATED, SO FALL THROUGH TO PRINT IT.
V/-65
'
CLOCK/RAM D~MONSTRATION MODULE
F8/3870 ~ACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
..*** •••
..
******.***~*********.**
.. MESSAGE OUTPUT SUBROUTINE ..
*
..
..
************.*.**************
.. FUNCTION:
.. THIS SUBROUTINE PRINTS THE MESSAGE STARTING AT
.. POINTER •
T~
..
.. ENTRY STATUS:.
* DC MUST POINT TO THE START OF THE MESSAGE TO BE
.. PRINTED. IT MUST END WITH AN 'EOT' CHARACTER •
..
.. EXIT STATUS:
.. THE MESSAGE IS PRINTED ON THE CRT •
029F
02A1
02A2
02AJ
02A5
02A 7
02A8
02A9
02AA
02AC
20A2
80
16
2304
84CD
13
BF
AD
81H
90F5
.
1092 OUTMSG
1093
109lt LOOP3
1095
1096
1097
1098
1099 LOOP4
1100
1101
LI
OUTS
LM
CI
Bl
SL
OUTS
INS
BP
BR
VI-66
XMIT
RXSTAT
EOT
LoOPI
1
LSBYTE
RXSTAT
LOCP4
LOCP3
;PUT INTO XMIT MODE
;GET CHARACTER
;CHECK FOR END OF TEXT
;BRANCH IF END
;START BIT
0
;SENT CHARACTER
;WAIT TILL READY FOR NEXT
;BRANCH IF NOT READY
;NEXT CHARACTER
=
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 ~ACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
******** •••• * •• *.***************
• CLOCK/RAM SU8RCUTINE PATCHES *
*
*
**************************** •• **
* FUNCTION:
* THESE PATCHES ARE TO SET UP THE COMMAND REGISTER
* FOR THE CLOCK/RAM SUBROUTINE. THE DIFFERENT ENTRY
• POINTS SET UP CIFFERENT COMMANDS.
*
* ENTRY STATUS:
• FOR WRITE COMMANDS, THE DATA MUST BE IN THE CLOCK
* BUFFER AREAS.
•
•
•
*
•
•
EXIT STATUS:
THE DATA IS TRANSFERED BETWEEN SCRATCH PAD AND TH
CLOCK/RAM.
READ CLOCK/RAM STATUS SUBROUTINE
•
* READ CLOCK/RAM ST ATUS SUBRUTI NE
02A[
02AF
0280
02B2
02B3
02B6
02B1
02B8
02BA
02B8
02BD
028E
60
6F
208F
52
29FFFF
60
6F
208E
52
2000
57
290284
•
1126 STATRD
1127
1128
1129
1130
•
•
•
LISU CTRL.SHR.3
LISL CTRL.AND.7
RDSTA T
LI
CMD,A
LR
JMP CLKRAM
;POINT TO CTRL REG
;
;SET UP COMMAND
;EXECUTE IT
WRITE CLOCK/RAM STATUS SUBROUTINE
1134 STATWR
1135
1136
1137
1138
1139
IHO
LISU
LISL
LI
LR
LI
LR
JMP
CTRL.SHR.3
CTRL.AND.7
WRSTAT
CMD,A
CRCTRL
CTRL,A
CLKRAH
;POINT TO CTRL REG
;
;SET UP COMMAND
;
;SET UP CONTROL BYTE
; DECUTE IT
*
* READ CLOCK SUBROUTINE
02C1
02C2
02C3
02C5
02C6
62
68
20BF
52
2902BF
02C9 62
o2C A 68
02C8 208E
02CD 52
02CE 2902C 7
*
1141+ CLKRD
IH5
1146
1147
1148
LISU
LISL
LI
LR
JMP
SECOND.SHR.3 ;POINT TO CLOCK BUFFER
SECOND.AND.7
; SET UP COMMAND
RDCLK
CMO,A
CLKRAM
;EXECUTE IT
*
* WRITE CLOCK SUBROUTINE
*
1152 CLKWR
1153
1154
1155
1156
LISU SECOND.SHR.3 ;POINT TO CLOCK BUFFER
LISL SECOND.AND.7
; SET UP COMMAND
WRCLK
LI
LR
CMD,A
JMP CLKRAM
; EXECUTE IT
VI-67
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM.
V2~2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
*****************.
*
*
*
*
* PROGRAM TABLES *
*******.*******.*.
*
* DIGIT CHECK TAeLE
0201 30
0202 31323334
35363738
*
1166 TAB09
1167 TAB19
DEfB '0'
DEFB '1','2','3','4','5','6','7','8'.'9'
39
*
* TABLE OF 30 DAY MONTHS
02DB 04060911
*
1171 TAB30
*
**********.*.*******
*
*
* PROGRAM MESSAGES *
*
********************
*
* FEATURES MESSAGE
02DF OC1B592A
20
02E'+ 2A2A2A2A
2A2A2A2A
2A2A2020
20202050
52455345
4E5H94E
47204D4F
5354454B
275320
0307 4E'I55720
4.HC4F43
4B2F521fl
40205045
52495048
4'552414C
20434849
50202020
20·20
0329 2A2A2A2A
2A2A2A2A
2A2A
0333 OOOAOAOA
0337 46'154154
55524553
3A
0340 OOOAO A
0343 2A2043lfD
4F532044
45534947
4E20464F
*
1181 SIGNON
OEFB FF,ESC,'Y','*',' ,
1182
DEFM '**********
1183
OEFM 'NEW CLOCK/RAM PERIPHERAL CHIP
1184
OEFM '**********'
1185
1186
OEFB CR,LF,lF,LF
DEFM 'FEATURES:'
1187
1188
DEFB CR,LF,LF
OEFM '* ~MOS DESIGN FOR EXTREMELY LOW
VI·68
PRESENTING MOSTEK"S ,
POWE~
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM.
V2.2
LaC OBJ.CODE
STMT-NR SOURCE-ST~T PASS2 DEMO
DEMO
DEMO
ABS
52204558
54524540
454C':I920
4C4F5720
504F5745
52
0368 20434FI+E
53554050
54494FltE
1189
DEFM '
CCNSUMPTION.'
1190
1191
CEF8 CR,LF
DEFM '* ASYNCHRONOUS SERIAL COMMUNICATION AT'
1192
DEFM '
1193
1194
DEF8 CR ,LF.
DEFM '* 12/24 HOUR CLeCK/CALENDAR WITH AUTO'
1195
DEFM '
ACJUST FOR SHORT MCNTHS AND LEAP'
1196
OEFM
YEARS~'
1197
DEFB CR,LF
DEFM '* 21t BYTES OF RAM fOR POWER DOWN'
2E
0375 ODOA
0.377 2A20ltl53
!:>94EIt.H8
52ltF4E4F
55532053
45524941
4C20434F
4D4D55ltf.
494H154
4'HF4E20
1t154
0390 20564952
5lt55414C
4C592041
4E592042
'+15544 20
52415445
VIRTUALLY ANY BAUD RATE.'
2£
0386 OOOA
0388 2A203132
2F323420
484F5552
20434C4F
434B2F43
41'+C454£
44415220
"57495448
20415554
4F
0300 2041444A
55535420
ItS4F5220
53484F52
54204D4F
4£544853
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50
03FE 20594541
52532E
0'+05 ODOA
0407 2A203234
20425954
,+55320'+F
462052'+1
4D20464F
5220504F
1198
VI-69
f
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSH. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
57455220
H4F5HE
0427 205354ltF
1199
DEFM ' STORAGE OF VITAL INFORMATION.'
1200
1201
DEFB CR,LF
DEFM ,* ON CHIP OSCILLATOR THAT PROVIDES A'
1202
DEFM , CLOCK SIGNAL FOR YOUR MICROPROCESSOR.'
1203
1204
DEFB CR,LF
DEFM '* SIMPLE INTERFACING TO ANY'
1205
DEFM , MICROPROCESSOR.'
1206
1207
OEFB CR,LF,LF,LF
DEFM '**********
1208
DEFM 'SENTATIVE FOR FURTHER DETAILS
52411+745
0445
0447
046B
0491
0493
oHE
04BE
o4C2
04E6
204F4620
56495441
4C20494E
464F524D
4154494F
4E2E
OOOA
2A204F1JE
20lf34849
5020lfF53
43494C4C
41'5HF52
205448'+ 1
54205052
4F564'H4
45532041
2043IJC4F
43482053
49474E41
4C20lf64F
5220594F
55522040
4943524F
50524F43
4553534F
522E
OOOA
2A205349
40504C45
20494[54
45524641
43494E47
20541fF20
414£59
20404943
524F5052
4F434553
5HF522E
ODOAOAOA
2A2A2A2A
242A2A2A
2A2A2020
20202053
45452059
4F555220
404F5354
454B2052
45505245
53454E54
4151f1f956
4520464F
52204655
5231f1f845
VI-70
SEE YOUR MOSTEK REPRE'
,
CLOCK/RAM DEMONSTRATION MODULE
F8/3810 MACRO CROSS ASSM. V2.2
LOC OBJ.COOE
STMT-NR SOURCE-STMT PASS2 DEMO
DEMO
DEMO
ABS
52201J445
5H1494C
53202020
20
0501 2A2A2A2A
2A2A2A2A
2A2A
0511 04
1209
DEFM '**********'
1210
DEFB EOT
*
0512 1B592020
1B4B04
0519 474F4F44
20IJD4F52
4£l+94E1J1
21
0526 04
0527 474f4F41J
20414654
4S52IJE4F
IJFIJE21
0536 04
* AM/PM MESSAGES
*
1214 GOODPT
DEFB Ese,'Y',' ','
',ESC,'K',EOT
1215 GOMORN
DEFM 'GOOD MORNING!'
1216
1217 GOAFTR
DEFB EOT
DEFM 'GOOD AFTERNOON!'
1218
DEFB EOT
*
0531 18!:92220
1B4BOIJ
053£
53551J~H
* DAY MESSAGES
*
1222 DAYPT
DEF8 ESC,'Y','u,,'
1223
DEFM 'SUNDAY'
1224
1225
DEFB EOT
DEfM 'MONDAY'
1226
1221
DEFB EOT
DEFM 'TUESDAY'
1228
1229
DEF8 EOT
DEFM 'WECNESDAY'
1230
1231
DEFB EaT
DEFM 'THLRSDAY'
1232
1233
OEFB EOT
DEFM 'FRIDAY'
1234
DEFB EOT
DEFM 'SATURDAY'
4159
OSH OIJ
OSIJ5 4D4F4E'+4
H59
0548 OIJ
054C 51J554553
444159
055:3 0 IJ
0551+ 5 H5444[
1J5531+441
53
0550 04
05S£: 54485552
5:3H4159
0566 04
0561 1+6524944
4159
0560 04
056E 53415455
521+44159
1235
*
0576 18592420
1i3.4B04
0570 IJA'+14E55
41525920
0585 OIJ
* MONTH MESSAGES
*
1240
DEFM 'JANUARY ,
1241
DEfB EOT
VI-71
',ESC,'K',EOT
CLOCK/RAM DEMONSTRATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT P~SS2 DEMO
DEMO
DEMO
ASS
0586 461t51t252
55415259
20
058F 04
0590 ItD41521t3
4820
0596 04
0597 41505249
4C20
0590 Olt
059E 4DH5920
05A2 04
05A3 4A55ltE45
20
05A8 04
05A9 4A554CS9
20
OSAE Olt
05AF 41554755
535420
0586 04
0587 53455054
45'*04245
5220
05Cl 04
05C2 4F43544F
42455220
05CA 04
05C8 4E4F5645
40'*2'*552
20
0504 04
0505 4'+,*54345
40424552
20
OSoE 04
1242
oEFM 'FEBRUARY ,
1243
1244
OEFB EOT
oEfM 'MARCH •
1245
1246
DEFB EOT
O£FM 'APRIL '
1247
1248
1249
1250
DEFB
oEFM
DEFB
DEFM
1251
1252
oEFB EDT
DEFM 'JULY'
1253
125'+
DEFB EDT
DEFM 'AUGUST •
1255
1256
DEFB EOT
DEFM 'SEPTEMBER'
1257
1258
oEFB EOT
D£FM 'OCTOBER '
1259
1260
DEFB EOT
oEFM 'NOVEMBER '
1261
1262
DEFB EDT
OEFM 'DECEMBER'
1263
EOT
'MAY ,
EOT
'JUNE •
DEfS EDT
*
* YEAR SEPARATOR M[SSAG£
...
050F 2C203139
05£3 04
1267 SEPAR
126B
OEFM " 19'
OEfB EOT
*
* SEND CURSOR TO TIME LINE MESSAGE
..
05E4 1B592620
184804
1272 TIMEPT
.
...
05EB 1B59376F
04
DEF8 ESC,'Y','&',' ',ESC,'K',EOr
SEND CURSOR HOME MESSAGE
1276 HOME
..
.. PROMPT MESSAGES
..
05FO DC
05F 1 44'415920
28312037
1280 oAYMSG
1281
DEFB FF
oEFM 'DAY (1-7)1 •
VI-72
F8/3870 MACRO CROSS ASSM.
CLOCK/RAM DEMONSTRATION MODULE
V2.2
DEMO
SIMT-NR SOURCE-STMI PASS2 DEMO
DEMO
LOC OBJ.CODE
ASS
293F20
OSFC 04
05Fo ODOA
05FF 4HlS4lf5
20285952
3A1+D4F3A
H41293F
20
0610 Olf
DEFB EaT
1282
*
128,. DATMSG
1285
DEFB CR,LF
DEFM 'DATE ?
1298
oEFS Ear
065C
1300
*
END
VI-73
•
,
•
CLOCK/RAM DEMONSTRATION MODULE
REFERENCES
NAME TYP VALUE DEF
AMPM
AMPMl
AMPM2
AMPMIN
AMPMOT
AMPMSG
APRIL
ASCII
AUG·
BAUD
CE1
CHIPEN
ClKRAII1
ClKRD
CLKWR
CMD
CNTSAV
CR
CRCHIP
CRCTRL
CRDATA
CTRl
DATA
CATAOK
DATE
DATE!
DATEIN
DAHOT
DAT(PT
OATlS!)
DATMSD
OATMSG
DAY
OAYOX
. DAno
OAY3X
DAYIN
DAYLSD
OAYMSG
OAYOT
oAYPT
OC3
oCOUNT
oOATE
DDATE!
DOATL>
,
•
•
·
,
,
,
•
,
.,
,
,
,
DEC
OGT
CGTBAD '
DGTlOP
DGTOK
DIGIT
DIGITO
DIGITI
OIGIT2
OIGIT3
,
,
,
,
•
0020
0189
01BC
OOBC
01AIf
0631
0004
027A
0008
0008
0002
0001
02CF
02C1
02C9
0002
ODOlf
0000
0002
0000
0004
0007
0001
0082
a 011+
01DE
0126
01CC
0516
OOOF
00 30
05FD
0013
016C
0184
0171
OOAB
0007
05FO
01CO
0537
0013
0005
0153
0169
0166
OOOC
0225
0255
025A
0263
0250
0240
022F
0234
0239
140
71f0
HI
IfIB
720
1292
93
1001
97
168
160
26
1144
1152
27
33
68
176
175
51
36
1 ;j9
386
41
195
596
182
1239
146
H5
1284
40
651
613
656
41+8
1 If 1+
1280
759
1222
69
3'+
63'+
648
647
101
881+
9'+0
943
953
933
931
895
901
907
F8/3870 MACRO CROSS ASSM.
V2.2
PASS2 DEMO
DEMO
DEMO
ABS
731
739
363
2137
483
1011
226
222*
1+ 1130 111+0 1148 1156
286
365
1129*1137*1147*1155*
938* 91f7
1185 1187 1190 1193 1197 1200 1203 1206 1284 1288 1292
1296
221
1138
236
238
689
792
360
289
783
601
1+55
644
662
646
359
237 1126 1127 1134 1135 1139*
801
762
681
453
288
760
335
658* 663* 91f0* 945*
625
652 669 614 698
683 691
693
891
948
91+6
91f4
897
51f 8
673
421+
534
903
562
909
513
915
601
921
610
486
51f3
529
622
1318
678
665
VI-74
927
641
CLOCK/RAM DEMONSTRATION MODULE
REFERENCES
NAME TVP VALUE DEF
913
919
882
925
889
938
S61
113
65
DIGITlf •
DIGIT6
DIGIT7
DIGITS
DIGIT9 ,
DIGITT t
DLOOP
EIGHT
EOT
023E
0243
0222
0248
022A
0253
0179
0008
0004
ESC
FEB
FEBXX
FF
FINISH f
FIVE
FNDLOP
FNDOUT f
FOUR
FRI
GDAFTR f
GDMORN '
GOODPT
HALT
HOME
HOUR
HOUROX f
HOURI
HOUR2
HOUR24 f
HOUR2X
HRIMSO
HR2MSD
HRLSD
INCHR
INCHR2 •
INIT
ISMASK
JAN
JULY
JUNE
LEAPI
LEAP2
LF
OC1B
0002
0189
OOOC
0043
0005
0298
0295
0004
0006
0527
0519
0'512
0080
05EB
0012
OOEF
00E8
0100
00F4
0104
0010
0030
GOOF
0283
0287
0001
003F
0001
0007
0006
0013
0012
OOOA
LOOP1
LOOP3
lOOP4
LSBYTE
0273 989
02A2 1094
02A9 1099
OOOF
57
OOOF 120
92
0003
0024 154
0005
'H
0109 557
OOOF 138
•
•
•
•
•
,
LSD
MARCH
MAXCNT
folAY
MIN
MINLSD
552
559
456
697
538
885
664
70
1069
1232
+2 57
1298
1181
91
636
678
67
299
110
1068
1066
109
85
1217
1215
1214
134
1276
39
538
535
549
543
552
142
HI
143
1029
1032
211
130
90
F8/3870 MACRO CROSS ASSM. V2.2
PASS2 DEMO
DEMO
DEMO
ABS
641
570
626
651
1095 1210 1214 1216 1218 1222 1224 1226 1228 1230
1234 1239 12'+1 1243 1245 1247 1249 1251 1253 1255
1259 12E:l 1263 1268 1272 1276 1282 1286 1290 1294
1214 121'+ 1222 1222 1239 1239 1272 1212 1276
637
1181 1280
279 336
1070
70;)3
914
800 1071
738
1'+0
721
291
423
530
539
553
525
547
839
485
522
727
834
839
942
334 1033
217
216
96
95
125
126
66
690
692
1185
1206
991
1101
1100
988
955
1185 1185 1187 1187 1190 1193 1197 1200 1203 1206
1206 1284 1288 1292 1296
1096
1031 1034 1098
1010
284
388
537
551
VI-75
CLOCK/RAM DEMONSTRATION MODULE
Rt:F ERE NCES
NAME TYP VALUE DEF
MINMSD
MINUTE
ML TRYl
MlTRY2
MNLSD
~NMSD
MNTHOX
MODE
P"OOEIN
MOOMSG
MON
MONTH
P"ONTH1
MSBYT€
MSO
NINE
NOV
OCT
ONE
OUTCHR
OUTCOL
OUT LSD
OUTMSD
OUTMSG
PARITY
PT4IMG
RCV
RCVI
RDCLK
RDSTAT
RXCTRl
RXSTAT
SAT
SEC LSD
SECMSD
SECOND
SEPAR
SEPT
SEll
SETCLK
SEVEN
SIGNON
SIX
STATRO
STATWR
STOP
SUN
TAB09
TAB19
TAB30
TEMP
TEN
TEN8CD
THREE
THURS
TICTRL
,•
•
,
,
t
,
•
,
,
t
•
,
,
,
131
0070
38
0011
742
01BF
0201 844
OOOF 148
0010 141
014E 626
0080 139
0096 416
0611 1288
81
0002
0015
42
OHA 623
OOOE
56
OOFO
121
0009 114
OOOB 100
OOOA
99
106
0001
0260 984
026A 917
027E 1009
0278 999
029F 1092
OOH
0000
00 BO
00B1
OOBF
008F
00 DC
0000
0007
OOOF
0010
0010
050F
0009
007C
006C
0001
020F
0006
02 AE
02B6
0091+
0001
0201
0202
020B
0003
OOOA
0010
0003
0005
0006
164
25
110
111
179
117
54
55
86
136
135
37
1267
98
364
357
558
130
831
193
361
1+21
611 656
627
229 1039
890
896
953
557
803
802
292
805
228
1029
291
11'+6
1128
227
298
357
804
785
926
,; 34
8'19
848
454
568 616
808 8'15
807 8'1'1
393 /t22
829 1067
846
853
852
'18'1
850 1002
518
883
392
920
235
242
397
933
884
660
954
794
790
645
602
722
391+
395
985
989 1030 1032 1093 1099
358
569
851 114/t 1145 1152 1153
362
243
112
116
108
8452
8/t7
621
1181
111
1126
1134397
80
1166
1167
1111
32
115
Fa13870 MACRO CROSS ASSM.
V2.2
PASS2 DEMO
DEMO
ABS
DEMO
978* 986
932
lO~8*10/t2
908
391
VI-76
101+3 *
741
161
784
CLOCK/RAM O~MONSTRATION MODULE
REfERENCES
NAME TYP VALUE O(f
TIMCNT
TIMEIN
TIMEOT
TIMEPT
TIMER
TIMMSG
TMCTRL
lUES
TWO
t.iEO
WRCLK
WRSTAT
XMIT
YEAR
YRLSO
YRMSr:;
ERO
t
t
,
•
0006
35
0000 512
0lF7 827
05E4 1272
0007
53
0648 1296
000 155
0003
82
0002 107
0004
83
OOBE 180
008£ 178
00A2 169
0016
43
OOOF 150
OOFO 149
0000 105
F8/3S 70 "ACRO CROSS ASSM.
PASS2 OEMO
278* 285* 389"
364
290
828
387
517
590
682
902
1136
984 1092
606
687
806
546
1154
VI-77
DEMO
V2.2
DEMO
ASS
VI-78
LISTING 2 - CLOCK/RAM COMMUNICATIONS SUBROUTINE
:LOCK/RAM COMMUNICATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
_DC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 CLKRAM CLKRAM CLKRAM REL
TITLE CLOCK/RAM COMMUNICATION MODULE
NAM£: CLKRAM
PSECT REL
GLOBAL CLKRAM
1
2
3
4
"
" THIS MODULE MUST BE LINKED WITH OTHER MODULES
" IN ORDER TO CREATE A wORKING PROGRAM.
"*** •••• *** •• ********** ••••• ***, •• *****
"* CLOCK/RAM COMMUNICATION SUBROUTIN[ "*
"~.************.************************
""
THIS SUBR00TINE IS CALLED BY THE APPLICATION
" PROGRAM TO S£NC AND RECIEVE QATA TO AND FROM THE
" CLOCK/RAM CHIP. WHEN CALLED, THE COMMAND TO B~
" EXECUTED MUST BE IN THE SCRATCH-PAD REGISTER
* 'CMO'. THi CHIP ENABLE CODE MUST 8E IN REGISTiR
* 'CHIPEN' AND THE ISAR MUST POINT TO THE TOP OF
* THE OA fA AREA.
"
"
"
"
*
*
"
THIS ROUTINE ALLOWS THE PORT 4 BITS THAT ARE NCT
USED FOR CHIP ENABLE LINES TO BE USED ~OR OTHER
PURPOSES. TO DO THIS, AN IMAGE OF WHATEVER IS
WRITTEN TO THC PORT BY OTHER ROUTINES MUST BE
KEPT IN REGISTER 'FT4IMG'. IN THIS WAY, THOSE
PORT LINES NOT USED BY THIS ROUTINE WILL NOT BE
ALTERED. HOWEVER, ANY OF THE PORT 4 LINES THAT
* ARE USED FOR THE CLOCK/RAM MUST ALWAYS ~E LEFT
" AT A LOGICAL O.
•
*
"
"
•
"
COMMAND BYTC FORMAT:
BIT 7 - MUST BE 1
BIT 6 - SOURC~/DESTINATION (l=RAM, O=CLOCK)
BITS 5 THRU 1 - ADDRESS
aIT a - DIRECTION (l=REAO, G=WRITE)
" FOR clYTE
"
*
"
*
"
MOJE. THE ADDRESS OF THE BYTE IS PUT
INTO THE ADDRESS FIELD OF THE COMMAND. FOR BURST
MODE, TH£ AJDRESS SHCULD BE OlFH. NOTE THAT A
CLOCK BURST cU~CTION TRANSFERS ONLY THE 7 CLOCK
BYTES. IT DOES NOT TRANSFER TH( CONTROL BYTE.
* VALID ADDRESSES FOR THE COMMAND 8YTE (FOR BYTE
" MODE> AR·::
" CLOCK - 0 THRL 07H
"RAM
- 0 THRU 017H
*
• CHIP :NA3L~ CO~TROL BYTE FORMAT:
* BIT 7 THRU 1 - CONTROLS PORT. bITS 7 THRU 1
• BIT 0 - MUST dE 0 (USED FOR DATA 1/0 LINE)
*
"
*
*
•
TO SELECT A CLCCK/RAM CHIP WITH IT'S ICE PIN
TIED TO A PCHT , FIN, THE CORRESPONDING BIT
POSITION SHOULC BE SET TO A 1 (ALL OTHER BITS
SHOUlO 0::: 0).
VI-79
CLOCK/RAM COMMUNICATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT~NR SOURCE-STMT PASS2 CLKRAM CLKRAM CLKRAM REL
• CALLING SEQUENCE:
• 1) DATA SHOULD BE IN DATA AREA (WRITE ONLY)
* 2) LOAD ISAR TO POINT TO BOTTOM OF DATA AREA
• 3) CHIPEN BYTE SHOULD BE IN REGISTER 'CHIPEN'
• ~) COMMAND BYTE SHOULD BE IN REGISTER 'CMD'
• 5) PORT ~ IMAGE SHOULD BE IN REGISTER 'PT4IMS'
• 6) CALL CLKRAM
• 7) RETURN WITH DATA AREA FILLED (READ ONLY)
•
• PORT 4 IS USED FOR ALL I/O SO THAT IT'S /STROBE
* SERVES AS THE SHIFT REGISTER CLOCK (SRCLK) TO
• THE CLOCK/RAM.
*
• AS PRESENTED HERE, THIS SUBROUTINE MUST NOT BE
• INTERUPTED. aUT THE USER MAY EASILY MODIFY THE
• CODE TO SUPPORT INTERUPTS.
VI-SO
CLOCK/RAM COMMUNICATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 CLKRAM CLKRAM CLKRAM REL
*************
..
*
=0000
=0001
=0002
* CONSTANTS *
*
*
............. ******
*
* GLOBAL REGISTERS. THESE REGISTERS MUST BE THE SAME
* AS IN THE APPLICATION MODULE(S).
*
84 PT4IMG
85 CHIPEN
86 CHD
..
EQU
EQU
EQU
0
1
2
,PORT 4 IMAGE STORAGE
;CHIP ENABLE STORAGE
;COMMAND STORAGE
* LOCAL REGISTERS. THESE REGISTERS 00 NOT NEED TO BE
* MADE KNOWN TO THE APPLICATION MODULE(S). HOWEVER,
=0003
=OOOlt
=0005
=0004
=0001
=0080
* THEY ARE DISTROYED. SO THE APPLICATION MODULE(S)
* SHOULD NOT KEEP NEEDED INFORMATION IN THEM.
*
93 TEMP
94 BIlCNT
95 BYTCNT
EQU
EGU
EQU
3
'*
5
*
* PORT DEFINITIONS
*
99 PORH
..
* BIT MASK
*
103 BITO
104 BIT7
'*
EQU
;TEMPERARY STORAGE
; BIT COUNTER
;BYTE COUNTER
;PORT
'*
DEFI~ITIONS
EQU
EQU
01H
80H
iBn 0 MASK
;BIT 7 MASK
*
=0001
=0007
=0008
=0018
* COUNTER VALUES
*
108 ONE
109 SEVEN
llO EIGHT
III TWFOUR
..
EQU
EQU
EQU
EQU
1
7
8
24
;COUNT
;COUNT
;COUNT
;COUNT
IS 1
IS7
IS 8
IS 24
* COMMAND eIT DEFINITIONS
=0001
=003£
=0040
*
115 RDWR
116 AOR
117 CKRM
EQU
EQU
£QU
VI-81
OlH
3EH
40H
;READ/WRITE IS BIT 0
;ADDRESS IS BITS 1-5
;CLOCK/RAM IS BIT 6
CLOCK/RAM COMMUNICATION MODULE
F8/3870 MACRO CROSS ASSM. V2.2
lOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 ClKRAM ClKRAM ClKRAM REl
************.****~***.*******
*
*
* START CF CLOCK/RAM DRIVER *
*
*
*********_.*****-*-*.*****.*-
0000'<+1
0001 EO
0002 50
•
125 ClKRAM
126
127
lR
XS
LR
A,CHIPEN
FT4 I~G
PT4IIIG,A
,PUT CHIP ENABLE INTO
PT~l
*
• SEND OUT COMMAND TO CLOCK/RAM
0003 42
0004 53
000'5 2008
0007 54
0008'43
0009'2101
0008 2301
0000 EO
OOOE 84
OOOF 43
0010 12
0011 53
0012 34
0013 94F5
*
131
132
133
134
135 BLOOP
136 BlOOPl
137
138
139
140
1'+1
H2
14.3
144
•
A,CMD
TEMP,A
EIGHT
LI
lR
BITCNT,A
A,TEMP
lR
NI
BITO
XI
BITO
XS
FT't IIIG
OUTS PORH
A,TEMP
lR
SR
1
TEMP,A
lR
OS
BITCNT
BNZ BlOCP1
LR
lR
,GET COMMAND
;SAVE COMMAND FOR OUTPUT
; BIT COUNT = 8
;GET COMMAND BYTE
;MASK OFF ALL BUT BIT 0
;COMPlEMENT BIT 0
,MIX IT WITH CONTROL BYTE
;SEND IT OUT
;SHIFT FOR NEXT BIT
;OECREMENT BIT COUNT
;BRANCH IF NOT DONE
* SET BYTE COUNT TO PROPER lENGTH
0015 42
0016 2l.3E
0018 253E
001A 9400
001C 42
001D 13
001E 9105
0020'2007
0022 9007
0024'2018
0026 9003
0028'2001
002A'55
002B'42
002C 2101
002E 70
002F 9402
0031 '+C
0032'53
0033 2008
0035 54
0036 42
0037 2101
0039 841B
148
149
150
151
152
153
154
155
156
157
158
159
150
-
CLOCK
lR
NI
CI
BNZ
lR
SL
BM
LI
BR
RAM
LI
BYTE
BR
II
LR
CONT
•
A,CPlD
ADR
ADR
BYTE
A,CMD
1
RAM
SEVEN
CONT
TWFOlJR
CONT
ONE
iG~T COMMAND
iMASK OFF All BUT ADDRESS
;CHECK IF BYTE OR BURST
;BRANCH IF BYTE
;GET COMMAND BACK
;CHECK RAM/CLOCK BIT
;BRANCH IF RAM
;CLOCK, SO BYTE COUNT
7
; CONTINUE
;RAM, SO BYTE COUNT
24
; CONTINUE
;BYTE, SO BYTE COUNT
1
=
=
=
BYTCNT, A
• MAIN BYTE TRANSFER lOOP
*
164 MlOOP
LR
A,CIID
;CHECK READ/WRITE BIT
NI
RDWR
165
165
CLR
167
BNZ XFER
;BRANCH IF READ DIRECTION
lR
A,S
;WRITE, SO lOAD BYTE
168
LR
TEMP,A
169 XFER
LI
EIGHT
170
iBIl COUNT
8
;
171
LR
BITCNT,A
172
LR
A,CMD
;CHECK READ/WRITE BIT
173
NI
RDWR
174
BZ
WRITE
iBRANCH IF WRITE DIRECTIOI
*
=
VI-82
CLOCK/RAM COMMUNICATION MODULE
F8/3870 MACRO CROSS ASSM.
V2.2
LOC OBJ.CODE
STMT-NR SOURCE-STMT PASS2 CLKRAM CLKRAM CLKRAM REL
003B'43
003C'12
0030 53
003f 40
003F 84
0040 A4
0041 2101
0043 70
0044 9403
0046 2080
0048'E3
0049 34
004A34Fl
004C 5C
* READ A BYTE
*
178 READ
179 READ1
180
181
182
183
184
185
186
187
188 READ2
189
190
191
*
*
0040'35
004f 8415
0050 OA
0051 IF
0052 OB
005.3 9007
LR
SR
LR
LR
OUTS
INS
NI
CLR
BNZ
LI
XS
OS
BNl
LR
A,TEMP
1
TEMP,A
A,PHIMG
PORH
PORT4
BITO
REAC2
BIT7
TEMP
81 TeNT
READI
S,A
iSHIFT FOR NEXT BIT
;SEND OUT DUMMY CLOCK
iINPUT DATA BIT
iMASK All EXCEPT DATA BIT
;IF DATA=l, FORCE BIT-7=0
;BRANCH IF DATA = 1
iOATA=O, FORCE BIT-7=1
;MIX WITH PREVIOUS BITS
;DECREMENT BIT COUNT
;BRANCH IF NOT 8 BITS
;STOR£ BYTE
CHECK IF ALL BYTES WERE TRANSFEREO
*
195 ENDCK
196
197
138
199
200
OS
BZ
LR
INC
LR
BR
aYTeNT
EXIT
A,IS
;OECREMENT BYTE COUNT
iBRANCH IF DONE
;INCREMENT POINTER
IS,A
MLOOP
i
ilOOP BACK FOR NEXT BYTE
*
* WRITE A BYTE
0055'43
0056'2101
0058 2301
005A EO
005B B4
OOSC 43
0050 12
OOSE 53
005F 34
0060 94F5
0062 90EA
*
204 WRITE
205 WR ITEl
206
207
208
209
210
211
212
213
214
lR
NI
XI
XS
OUTS
lR
SR
lR
OS
BNZ
BR
A,TEMP
BITO
BITO
PT4IMG
PORH
A,TEMP
; GET OA TA BYTE
;MASK OFF ALL BUT BIT 0
;COMPLEMENT BIT 0
;MIX IT WITH CONTROL BYTE
; SEND IT OUT
;SHIFT FOR NEXT BIT
1
TEMP,A
BI TeNT
WRITE1
ENOCK
;DECREMENT BIT COUNT
;BRANCH IF NOT 8 BITS
; CONTINUE
*
* EXIT FROM SUBRCUTINE
0064'41
0065 EO
0066 50
0067 B4
0068 lC
*
218 EXIT
219
220
221
222
lR
XS
LR
OUTS
POP
VI-S3
A,CHIPEN
PH IMG
PT4IMG,A
PORT4
;RESTORE PORT 4 IMAGE
,DISABLE CHIP
iFINISHEO
CLOCK/RAM COMMUNICATION MODULE
NAME TVP VALUE OEF
REFERENCES
AOR
BITO
BIT 7
B ITCNT
BLOOP
BLOOP1 '
BYTCNT
BYTE
CHIPEN
CKRM
CLKRAM I
CLOCK
CMD
CONT
EIGHT
ENDCK
EXIT
flLODP
ONE
PORT4
PHIMG
~AM
RDWR
READ
READ1
READ2
SEVEN
TEMP
TWFOUR
WRITE
wRITEl
XF£R
,
003E
0001
0080
0004
0008
0009
0005
0028
0001
0040
0000
0020
0002
002A
0008
0040
0064
002B
0001
0004
0000
0024
0001
003B
003C
0048
0001
0003
0018
0055
0056
0032
116
103
104
94
135
136
95
159
85
117
125
155
86
160
110
195
218
164
108
99
84
157
115
178
119
188
109
93
III
20lJ
205
169
F8/3810 MACRO CROSS ASSM. V2.2
PASS2 CLKRAM CLKRAM ClKRAM REL
149 150
136 131 184 205 206
187
134..- 143* 171 * 189* 212*
144
160* 195*
151
125 218
4
131
156
133
214
196
200
159
139
126
154
165
148
158
110
152
164
172
182 183
121* 1~8
208
181
221
201
219
220*
113
190
186
155
132* 135
157
174
213
167
140
VI-84
1'12* 165* 118
180* 188
204
209
211-
LISTING 3 - LOAD MAP AND GLOBAL CROSS REFERENCE
LOAD MAP
DKl:DEMO .OBJ[lJ
DKl:CLKRAM.OBJ[l]
AdS
BEG ADDR COOO
REL
8EG AGQR 065C
GLOBAL CROSS REfiRENCE TABLE
SYMBOL AeOR
CLKRAM 065C
REFEReNCES
02CF 02C7 D2BF 028,
VI-8S
END ADOR 0658
END ADDR 06C4
VI-86
MOSfEI(.
USING MK3807 VCU IN A MICROPROCESSOR ENVIRONMENT
Application Note
INTRODUCTION
PROGRAM REGISTERS
MK3807, the programmable CRT Video Control Unit (VCU),
is a user programmable 4O-pin n-channel MOS/LSI chip
containing the logic functions required to generate all the
timing signals for the formatting and presentation of
interlaced or non-interlaced video data on a standard or
non-standard CRT monitor.
The VCU contains 9 working registers (7 control registers
and 2 data location registers).
SELF LOADING SCHEME
FOR VCU SET-UP
Figure 1
All the formatting, such as horizontal, vertical, and
composite sync, characters per data row and per frame are
totally user programmable. The data row counter has been
designed to facilitate scrolling.
DBO
Programming is accomplished by loading seven 8 bit control
registers directly off an 8 bit bidirectional data bus. Four
register address lines and a chip enable line provide
complete microprocessor compatibility for program controlled set up. The device can also be "self loaded" via an
external PROM tied on the data bus. (See Figure 1).
Ao A; A2A3CE
-------
MK3807
VCU
DB7
ROR, R2 R3
Ao
9 BYTE
PROM A,
A2
SLOAol CE
from system)
A3
In addition to the seven control registers, two additional
registers are provided to store the cursor character and row
addresses for generation of the cursor video signal. The
contents of these two registers can be read out onto the bus
for update by the progra ni or used by the microprocessor as
two memory locations. (See Figure 2).
T
OS
~
ROW SELECTS
TO CHARACTER GENERATOR
BIT ASSIGNMENT
Figure 2
HORIZONTAL LINE COUNT
REG 0
I; I I I
iI
I I 0I
SKEW BITS
REG 31
LAST DISPLAYED DATA ROW
DATA ROWS/FRAME
ill I ~ I I i I
I 0I
SCAN LINES/FRAME
REG 61 X
REG 21x
I~I
i I ~ I rrn I
CHARACTERS/DATA ROW
VERTICAL DATA START
I--IoI--'-I_i.........I.......I__1 0....I
REG 51....; .....
VI-87
iI
I~ I
CURSOR CHARACTER ADDRESS
REG 7
SCANS/OATA ROW
IX I ~ I I
1
1;1 I I
iI
I I~I
CURSOR ROW ADDRESS
REG8Ixlxl~1 I
iI
I~I
REGISTER 0
This 8 bit register contains the number of character times
for 1 horizontal period of the TV raster scan. For example,
using American Standard Television (63.5 I'-s per line) at a
character time of 500 ns, the value for this register would
be 63.5 divided by .5 = 127. The number in this register is
normally 1.25 times the number of characters per line
displayed on this screen. ThE! value loaded into this register
is the binary equivalent of 126 (127-1). Since character
times are counted from zero instead of one, the value loaded
into this register is one less than the actual number of
character times. (Refer to Figure 3 for timing diagrams).
which defines the number of characters per line. The VCU is
pre-programmed for 20, 32, 40, 64, 72, 80, 96, and 132
characters per line. The 3 bit binary number used in this
field determines the particular format, for example, 80
characters being the 6th value would be coded as a binary 5
(101 ).
CHARACTERS/DATA ROW
DB1
DBO
°
°
°
0
0
0
1
1
1
REGISTER 1
This register contains 3 fields of information. The most
significant bit (7) is the interlace bit. If this bit is set to a 1,
Interlace mode is indicated; if set to a 0, Non-Interlace mode
is indicated. The next 4 bits (6-3) define the number of
character times for the width of the horizontal sync pulse.
For example, using American Standard Television (4.5 I'-s)
and a character time of 500 ns indicates that it would
require 9 character times, therefore the binary equivalent 9
would be loaded in these bits. The least significant 3 bits
(2-0) are used to specify the horizontal sync delay. This is
commonly called the Front Porch and is the period between
the end of active video to the beginning of the horizontal
sync pulse. The value here is not critical and can be used to
position the video horizontally on the screen.
DB2
0
1
1
0
0
REGISTER 3
This register contains both the propagation delay
compensation field (skew bits) as well as the data row fields.
Bits 7 and 6 are used to adjust the blanking, cursor position
and sync delay so as to compensate for either 0, 1 or 2
character time propagation delays of the character
generator and the frame buffer RAM.
SKEW BITS
REGISTER 2
Sync/Blank Delay
Cursor Delay
(Character Times)
DB7 DB6
This register contains both the number of characters to be
displayed per line as well as the number of scans per
character. Bit 7 is not used (B7 = X). Bits 6 through 3 define
the number of scans per character. For example, using a 7 X
9 dot matrix character generator, the normal number of
scans might be 12. Therefore, using 12 scans per character,
the binary equivalent of eleven (12-1) is inserted into this
field. The least significant 3 bits (2-0) contain a 3 bit code
= 20
= 32
= 40
= 64
=72
= 80
= 96
= 132
1
0
1
0
1
0
1
o
0
o
1
0
1
2
2
o
1
1
o
o
1
2
The 6 least significant bits (5-0) define the number of
data rows to be displayed on the screen. The number of
rows begins at 000000 (single row) and continues to
111111 (64 rows).
HORIZONTAL AND VERTICLE TIMING
Figure 3
~STARTOFLINEN
HORIZONTAL TIMING
olJ1zmz
STARTOFLlNEN+1
C
Z777777ZZZlZZlZZZZZOZ77/J
n
"1""j
ACTIVE VIDEO =
CHARACTER. S PER DATA LINE
HORIZONTAL SYNC DELAY
(FRONT PORCH)
HORIZONTAL SYNC WIDTH
HORIZONTAL LINE COUNT = H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
SCAN LINES PER FRAME
r-
~
I"
VERTICAL DATA
START
START OF FRAME M + 1 OR EVEN FIELD
"I
rZZZZZZZZZZZZZZZZZZZZZ/%ZZZZZZ4 r-l
V777
j~
ACTIVE VIDEO
. .. 1-.1 IDATA ROWS PER FRAME
L VERTICAL SYNC
= 3H
VI-88
,
~.r
c~
7_
VIDEO DOT
CLOCK
.B'C5
c c:
iil"!.:
"'"1:1
+5V
?
74160
DOT
COUNTER
(+N)
CP
I
CHARACTER CLOCK
"'I"
"7
ADDRESS BUS
I
ENABLE
LOGIC
rI
HSYNC
DBO-7
V SYNC
CONTROL BUS
~
V SYNC
SET
INTERRUPT TO "p
(TO UPDATE
DATA IN RAM)
4
~.s[)1n
~.>
r
RAM&ROM
(FOR "P)
I :
I-
1
I(
IV
DATA
IN
RO-3
:!:
oz
a
I BLANKING
21
CRV
4
.>-
lASCII
7 ..
DATA BUS
ADDRESS
·Z-PORTRAM
1Kx8to4Kx8
CHARACTER
FRAME
BUFFER
BL
~
DRO-5
SELECTOR
WITH
OPTIONAL
MEMORY
MAPPING
CIRCUIT
(IF REQUIRED)
Jl
Q
COMPOSITE SYNC
CSYNC
d
o
:!l
CHARACTER ROW
CHARACTER
ADDRESS
BUS
1
ADDRESS BUS
~
~
z
(5
OS
V
3873
OR
[Z80J
MICROPROCESSOR
.
HO-7
6
~
VERT. SYNC
:21
CHARACTER COLUMN
v
DATA BUS
MK3807
VCU
CE
DATA STROBE
Co
CD
HORIZ.SYNC
4
CHIP ENABLE
8
c:
DCC
AO-3
r
Z
."
C5
Voo
8
BI-DIRECTIONAL DATA BUS
+-
o
?
Vee
CARRY
o
+1ZV
::r
VIDEO DOT
DATA
OUT
·OR 1 PORT RAM
WITH BI-DIRECT
PORT
y
TIMING
FROM
DOT COUNTER
OR
CHARACTER
CLOCK
..
FL
CHARACTER
GENERATOR
MK34073
it
N BIT SHIFT REGISTER
rI
SERIAL
OUTPUT
~.
II~
REGISTER 4
REGISTER 8
This 8 bit register defines the number of raster lines in the
field (frame). Care should be taken when programming this
register to make sure that the product of the scans per data
row times the number of data rows is less than the number
of raster scans. There are 2 methods of programming this
register. In the interlaced mode subtract 513 from the
number of raster lines desired and divide by 2. For example,
for 525 scahs, the register should contain the number 6. In
the non-interlaced mode subtract the number 256 from the
desired number of raster lines and divide by 2. For example,
for 262 raster lines, the value is 3.
The least significant 6 bits (5-0) of this register define the
data row for the cursor; similar to Register 7.
REGISTER 5
This register defines the number of raster lines between the
beginning of the vertical sync pulse and the start of the first
data row being displayed. Typically, values of 20 or 21 lines
are used. Higher values can be used to position data lower
on the screen to a maximum 255. This is called Vertical
Data Start and is the sum of Vertical Sync and Vertical Scan
Delay.
REGISTER 6
The least significant6 bits (5-0) of this register define the
last data row to be displayed on the screen. Bits 7 and 6 are
not used. This featUre is useful for both scrolling and
positioning of data. For example, ifthe display was set for 24
data rows, normally row 0 would be on top ofthe screen and
row 23 would be atthe bottom. 1fthe scroll register (register
6) contained the number 15, then row 15 would be at the
bottom and row 16 would be at the top of the screen. Row
23 and row 0 would be contiguous in the middle of the
screen.
REGISTER 7
This 8 bit register contains the character number at which
the cursor is to be addressed. For example, if the last
character of an 80 character per line display were to be
cursored, the binary equivalent of 79 would be in this
register.
BASIC DISPLAY CONFIGURATION
Figure 4 shows the basic configuration for a Bus Oriented,
microprocessor based, CRT display system utilizing
Mostek's MK3807, the Programmable CRT Video Control
Unit (VCU). Either a standard or a non-standard CRT monitor
may be used. The user programmable VCU provides
Horizontal Sync, Vertical Sync and Composite Sync with
serrations, to the monitor's sync deflection circuitry. (Figure
5 shows the composite sync timing). A serial output
character generator provides video dot clock frequency data
to the Z axis video input of the monitor.
In addition to the VCU, character generator, and shift
register, the display system requires a crystal oscillator and
a dot counter, typically consisting of two gates of a 7404 and
a crystal as well as a 74160(orequivalent) dot counter. The
dot counter divisor(N) is set for the number of horizontal bits
in the character plus the number of dots desired for spacing
(Le., for a 7 bit wide character + 2 dots of spacing N =9). The
carry output of the dot counter pulses once per character
(character clock) and is fed into the MK3807 DCC (pin 12)
input. This enables the VCU to keep track of the character
positions as well as generate the entire video timing chain.
At the same time the output of the oscillator is fed into the
video dot clock input of the shift register of the Video Signal
Generator.
An 8 bit bidirectional Data Bus (D8O-DB7), a 4 bit Address
Bus (AO-A3), a Chip Enable and a Data Strobe are used in
programming the VCU. These buses connect to the
microprocessor Data Bus and Address Bus. The VCU
appears to the microprocessor as 16 memory or I/O
locations. Page logic (high order address bit decoder)
connects the Address Bus to the Chip Enable (CE) thereby
determining where in the microprocessor memory space
the VCU will be located. The Data Strobe (DS) signal is
connected to the microprocessor Control Bus. This is used
to read or write via the Data Bus, as well as to activate
control functions.
COMPOSITE SYNC TIMING DIAGRAM
Figure 5
HSVNC
L-----...jn~rL--IL-JL
,
,
,
!
I
I
V SYNC
I
i
1 - ,_ _ _ _ _ __
I,
COMPOSITE
SYNC
VI-90
The VCU raster scan counter outputs (RO-R3) are connected
directly to the raster line address inputs of the character
generator. This 4 bit address indicates which raster line of
the selected character is to be parallel loaded into the shift
register. The bit pattern, along with the additional blank
spaces, is then shifted out of the video output at the video
dot clock rate. The blanking signal can be connected to
retrace blanking logic to provide both horizontal and vertical
blanking of the video signal to the CRT monitor. The
load/shift signals for character generator logic can be
derived from the outputs ofthe dot counter (74160) or taken
directly from the character clock (DCC, pin 12 of 3807).
Page Scrolling
Scrolling a smaller page through a larger page (1 K in 4K)
can be done on a row by row basis. If the DRO-DRSlines are
offset by a pointer register, the smaller page can be moved
up or down inside the larger page by the offset number of
rows. This is shown in Figure 7. In this example, if the
pointer register contains zero, the VCU will address the first
12 lines of the 32 line page. When the pointer register
contains ten, the VCU will address rows 10 to 21 . Thus, by
loading the pointer register (from the microprocessor data
bus), the display can scroll row by row through the data
base.
HOW TO USE ROW-COLUMN ADDRESSING
Software Addressing
The VCU outputs the character position via the character
counter outputs (HO-H7) and the data row counter outputs
(DRO-DRS). These outputs define the character column and
row location. They are used to address a character frame
buffer RAM in which the frame image is stored. Since the
VCU keeps counting horizontal addresses (HO-H7) during
both horizontal and vertical blanking, dynamic RAMs may
be refreshed.
Many advantages are realized using Row-Column (X-V)
Addressing. Among these are:
Oversize Characters
Character fonts with heights greater than 16 dots (raster
lines) can be achieved. This is done by using the LSB of the
row counter (DRO) as the MSB of the raster scan counter
(R4), and then moving the remaining bits ofthe row counter
down one bit (DR1 becomes DRO, etc.). This is achieved by
connecting the pins of the VCU in a different configuration.
No additional components are required. This is shown in
Figure 6. In addition, the VCU must be programmed for
twice the desired number of data rows; thus using the
above configuration (FigUre 6), 32 rows of data with up to 32
lines per character (or 16 rows of data with up to 64 lines
per character) can be accomplished.
Most programmers use X - V (row-column) addressing
when writing software for CRT terminals. This makes it
easier to blank the bottom line when scrolling, changing
cursor positions, etc. Therefore, by having row-column
addressing in the VCU, the address bus of the
microprocessor can also have the preferred row-column
addressing, and the two buses can be mapped together as
shown in Figure 8. Without this feature, a software
algorithm would have to convert a row-column address to
binary address every time the microprocessor wanted to
access the frame buffer. This algorithm usually requires a
16 bit multiplication. Thus the VCU, by utilizing row-column
addressing, can save significant overhead and program
execution time.
SCROLLING A 12 ROW PAGE THRU A 32 ROW PAGE
Figure 7
B-BIT DATA BUS
USING THE VCU WITH CHARACTER FONTS OF
HEIGHTS GREATER THAN 16 DOTS (LINES)
Figure 6
4-BITADDER
(7483A)
DRS
TO
DR4
BUFFER { DR3
RAM
DR2
DR1
ORO
31 MK3807
30 VCU
29
28
27
26
4 S 7 8
~3 ~2 ~1 ~o
'----v-----'
TO
CHARACTER
GENERATOR
A. 64 ROWS OF 16 LINES
D. R4 31 MK3B07
TO
DR3- 30 VCU
BUFFER { DR2 29
RAM
DR1- 28
ORO 27
,26
4 S 7 8
I
R4
DR4'
§
0DISPLAYED
12
PAGE
11 _ ROW
R~ RI2 ~1 ~o
'--v-------'
TO
CHARACTER
GENERATOR
_o
DATA
PAGE
(32 ROWS)
-31
B. 32 ROWS OF 32 LINES
VI-91
MEMORY MULTIPLEXING
The character column and character row outputs combine
to form the character address bus. This bus, along with the
microprocessor address bus, is connec;:ted to a 2 X 1 selector
which addressl'ls the character frame buffer RAM. Figure 8
shows the selector and the mapping for the various formats
of the standard VCU. Numerous methods are available to
build 2 X 1 selectors. One low-cost technique uses three
ADDRESS BUS MAPPING
FigureS
FROM I'P { I'P ADDRESS BUS
SYSTEM
ROW & CHARACTER
I
ADDRESS FORMAT
PAGE IROW I CHARACTER
I
HO-H8
}
CHARACTER FROM
VCU
I
DRO-DR6
DATA ROW
B
FROM I'P
CONTROL BUS
(i.e. 74167,
267 etc.)
ADDRESS MATCHING
74157 or equivalent(74LS157 or 257, 9322, etc.)quad2X
1 selector chips. Figure 8 tabulates the mapping on to the
microprocessor address bus into the.selector with the DR
and H lines of the VCU. The output of the selector (Z), is
decomposed into two fields, row (Y) and column or
character (X). Refer to Table 1.
Memory Addressing
When the number of characters per row is non-binary, i.e. 80,
addressing the frame buffer RAM lswasteful of memory. To
solve this problem and still retain the advantages of rowcolumn addressing, an address mapping ;s performed. The
output of the selector (Z) ;s connected to another 74157
quad 2 X 1 selector chip or equivalent. Figures 6A, B, and C
show the connection for 12 rows (1 K), 24 rows (2K), and 48
rows (4K) of 80 characters. Figure 5 shows the mapping
technique. The first 64 characters are .mapped directly and
the next 16 characters(H6 = 1) are mapped in a higher part
ofthe RAM. The microprocessor acldress(row and column),
is overlayed onto the VCU address bus (row and column) via
the selector. The output of the selector maps into the frame
buffer. Thus, every character is addressed by its row and
column from both the microprocessor and the VCU. The
ADDRESS BUS MAPPING
Table 1
SELECTOR
J.lP ADDRESS BUS
(UNUSED BITS ARE FOR PAGE LOCATION)
AB12 ABll ABle AB9 IAB8 ~B7 AB6 AB5 AB4 ~B3 ~B~ ABl ABO
INPUT (A)
20 & 32 CHARACTERS/LINE
ROW
FUNCTIONS
VCU OUTPUTS
SELECTOR OUTPUTS
INPUT (B)
CHARACTER
DR5 DR4 DR3 DR2 DRl DRO H4 H3 H2 Hl HO
OUTPUT(Z)
Y5
Y4
Y3 Y2 Yl
YO X4 X3 X2 Xl XO
40 & 64 CHARACTERS/LINE
FUNCTIONS
VCU OUTPUTS
SELECTOR OUTPUTS
ROW
INPUT (B)
CHARACTER
DR5 DR4 DR3 DR2 DRl DRO H5 H4 H3 H2 Hl HO
Y5
OUTPUT(Z)
Y4
Y3 Y2 Yl
YO X5 X4 X3 X2 Xl XO
72, 80 & 96 CHARACTERS/LINE
ROW
FUNCTIONS
VCU OUTPUTS
SELECTOR OUTPUTS
INPUT (B)
CHARACTER
DR5 DR4 DR3 DR2 DRl DRe H6 H5 H4 H3 H2 Hl HO
OUTPUT(Z)
Y5
Y4
Y3
Y2 Yl
YO X6 X5 X4 X3 X2 Xl XO
132 CHARACTERS/LINE
ROW
FUNCTIONS
VCU OUTPUTS
SELECTOR OUTPUTS
CHARACTER
DR4 DR3 DR2 DRl DRO H7 H6 H5 H4 H3 H2 Hl HO
INPUT (B)
OUTPUT(Z)
Y4
VI·92
Y3
Y2
Yl
YO X7 X6 X5 X4 X3 X2 Xl XO
MEMORY MAPPING CIRCUITS FOR 72
OR 80 CHARACTERS/LINE
Figure 9
10 BIT BINARY ADDRESS TO 1024 BYTE RAM
12 LINES INTO 1K
Y
FROM
SELECTOR
x
\31211101161514131211101
Figure9A
I
1K
~
~
13 14110 11 6 15 3
2
48 4A 38 3A 28 2A 18 1 A 1
E
74157
S
QUAD 2 x 1 SELECTOR
(74LS157. 257. ETC.)
16
GND
Vee
4Y 3Y 2Y 1Y
112 9
714
A9
h...
AS
A7 A6
11 BIT BINARY ADDRESS TO 2048 BYTE RAM
24 LINES INTO 2K
Y
+~
A5 A4 A3A2 A1 AO
FROM
SELECTOR
x
141 3 1211101161514131211101
Figure9B
I
1K
r
+5
~
16
13 14 10 11 615 3 12
48 4A 38 3A 28 2A 18 1 A 1
E
74157
QUAD 2 x 1 SELECTOR
(74LS157. 257. ETC.)
S
GND
Vee
4Y 3Y 2Y 1Y
12 9 7 14
n.
AS A7 A6
A10 A9
12 BIT BINARY ADDRESS TO 4096 BYTE RAM
48 LINES INTO 4K
Y
+~
A5 A4 A3 A2 A1 AO
FROM
SELECTOR
x
1514131211101161514131211101
Figure9C
I
I
1K
13 14 10 11 6 15
48 4A 38 3A 28 2A
3
2
1A
1
74157
QUAD 2 x 1 SELECTOR
(74LS157. 257. ETC.)
S
16
GND
Vee
4Y 3Y 2Y 1Y
1( E
+5 ,...
h
12 9
A11
A10
VI-93
7 14
AS A7 A6
t
~
A5 A4 A3 A2 A1 AO
same memory location will be accessed whether the
identical address originates from the microprocessor or
VCU address bus.
OPERATION
The character frame buffer RAM is initially loaded via the
microprocessor data and address buses (see Figure 1). After
the microprocessor has loaded the character frame buffer
RAM with a complete page, the selector flip-flop is switched
(via the microprocessor control bus) so that the RAM is
addressed by the character address bus of the VCU. In this
mode the VCU operates independent of the microprocessor
by addressing the character frame buffer RAM which sends
the ASCII data to the CRT character generator. The selected
character is then further decomposed by the raster scan
counter (RO-R3), from the VCU, and loaded into the
character generator shift register. This bit pattern is then
serially shifted out at the video dot clock frequency and the
data can be encoded so as to compose the video signal.
external (off-the-air) video. Figure 11 illustrates a simple
technique of externally synchronizing the VCU using 2
chips (7474 and 7402 or equivalent).The external video can
come from a closed circuit television system, off-the-air
television, or some other video display system. The
technique involves stopping the character clock (DCC)when
the VCU sync occurs and restarting it when the external
sync occurs. In this way, the VCU will be synchronized to the
external video. One requirement for the reliable operation of
this system is that the VCU horizontal and vertical sync rates
must be programmed to be slightly faster than the external
sync rate (i.e., the horizontal line counter register ofthe VCU
must be programmed to be less than 63.5 /-IS., which is the
American TV horizontal rate).
HOW TO PROGRAM THE MK3807 VCU
In order to pick the correct video dot clock frequency and to
program the registers in the VCU, it is first necessary to
determine several key parameters. Among these parameters are: the vertical refresh rate, the number of horizontal
raster lines perframe, the number of characters per line and
the format of the characters.
One possible way to change the data in the frame buffer
(which is in microprocessor address space but physically
separate) is: whenever the data in the character frame
buffer is to be changed or updated, the microprocessor (via
the control bus) sets an external flip-flop. The output of this
flip-flop is ANDed with the vertical sync signal from the
VCU. When this occurs an interrupt is generated to the
microprocessor. This alerts the microprocessor to the fact
that the vertical blanking interval has begun; it then
switches the address selector (via control bus) so that the
character frame buffer is now addressed by the micro•processor instead of the VCU. Since the system is in the
vertical blanking interval. the screen is blank at this time.
Using the American standard of 63.5 fJ.S. per horizontal line
and a typical value of 21 horizontal lines for the blanking
interval. this gives the system 1.33 ms. in which the
microprocessor can change data in the character frame
buffer. Ifthis time is not sufficient, the 1.33 ms. window will
appear every 1/60 of a second allowing the microprocessor
to change part of the RAM data each time.
Tables 2A, B list work sheets which give the designer an
ADDRESS COMPRESSION SCHEME
FOR 80 CHARACTERS/LINE
Figure 10
I1-::....------------------64-----_8_0~~~~~~~:..:;----1-6----.I'
1
I 1
!
I
SCREEN
~
After the microprocessor has completed its updating of the
character frame buffer RAM, it resets the external flip-flop
(via the control bus) and switches the selector back to the
character address bus of the VCU. Then the microprocessor
goes about its normal system operation without being
interrupted or having its thrughput slowed down. This is
because the VCU refreshes the CRT independently with the
character frame buffer RAM, supplying the data, while the
microprocessor operates at full speed with its own RAM
and ROM. This method is more efficient for microprocessor
throughput and control as opposed to having to DMA (cycle
steal) or interrupt the processor continually, thereby
reducing its throughput.
MAPPING
~
SYNC-LOCK
Some applications require adding alphanumeric characters
(text) or graphics to the same screen as closed circuit or
VI-94
--16_1-- 16--l--16-1--16j
64 ______
1•
~~
MEMORY
24
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SYNCHRONIZING
LOGIC
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REPRESENTATIVE
SYSTEM LOGIC
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VIDEO CLOCK
CRYSTAL OSCILLATOR
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MK3807
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... - - - - -
NOTES:
1. PROGRAM N IN REGISTER 0 SUCH THAT
IN + 3] x CHARACTER CLOCK RATE:'O 63.6 "SEC.
2. PROGRAM HORIZONTAL SYNC WIDTH =
1 CHARACTER TIME
....
CHARACTER
CLOCK
orderly method of determining the frequencies and register
contents from the above parameters. In order to
demonstrate its use, typical examples will be shown.
EXAMPLE FOR 80 CHARACTERS BY 24 ROWS
A 7 X 9 character matrix is chosen as it is the most popular
for the display of both upper and lower case characters.
Also, a non-interlaced system is chosen. The character
block of 9 X 12 allows for a 2 dot space between characters
and a 3 line space between data rows. The impact of the
character block size on the horizontal frequency and the
video clock rate will be shown below. A frame refresh rate of
60Hz is chosen for this example. These numbers can be
modified for 50Hz systems.
This system will have 24 rows of data and 80 characters per
data row. Thus, there are (24 X 12) 288 active scan lines.
The monitor chosen for this example is capable of accepting
a composite video signal or separate TTL horizontal and
vertical sync pu~el?' The sum of the horizontal sync delay
(front porch), horizontal sync pulse, and horizontal scan
delay (back porch) is the horizontal blanking interval. This
interval is required as a window in the horizontal scan
period to allow retrace. The retrace time is internal to the
CRT monitor; this time is a function of monitor horizontal
scan components. This time, at a minimum, is the time it
takes the display to return from the right to the left hand side
of the display. The retrace time is less than the horizontal
blanking interval. The horizontal blanking interval is
normally about 20% of the total horizontal scanning period.
See Figure 12 for horizontal and verticle timing, and Figure
13 for derived register bit assignments.
In an 80 character per data row system, this would give 20
character times for the sum of the Front Porch, Horizontal
Sync Pulse, and Back Porch. In the example of table 2C, a
sum of 22 character time is used to illustrate that some
flexibility exists in the choice of these parameters.
The vertical scanning frequency can be obtained by
counting the total number of horizontal lines. The total
number of scan lines generated for a vertical field equals the
number of data rows times the number of lines per
character plus the vertical sync delay plus the vertical sync
pulse plus the vertical scan delay.
Vertical sync delay is the number of scan lines delay before
vertical sync. Vertical sync pulse width should be expresed
in scan line units. The VCU is fixed at the standard vertical
sync width of 3 horizontal scan lines (3H). Scan line delay is
the delay between vertical sync and the display information
in scan line units. The sum of the vertical sync and the 2
delays in the vertical blanking interval is normally 5% to 8%
of the total number of scan lines.
The vertical period (for 60Hz vertical refresh rate) can be
calculated as: 1 divided by 60Hz = 16.67 ms.
Thus, the vertical blanking period (at 8%) equals 1.3 ms. In
the example of table 2C, the sum of the "Front Porch,
Vertical Sync Pulse, and Back Porch" are 22 scan lines long.
Again, some flexibility exists in the choice of these
parameters.
Adding the displayed lines (24 X 12 =288) plus the vertical
blanking interval (0 + 3 + 19 =22), 31 0 horizontal scan lines
are required. These 310 lines must be repeated 60 times a
second (every 16.67 ms.). Thus 18,600 horizontal scan lines
per second is the horizontal frequency. It can now be seen
that any further increase in the number of scan lines per
data character block will cause a direct increase in the
horizontal frequency, possibly to a point beyond the
monitor's specification.
HORIZONTAL AND VERTICAL TIMING
Figure 12
HORIZONTAL TIMING
~STARTOFLINEN
STARTOFLlNEN+1~
YlZZaZOZ77ZZZZZIZWUZll
rI&..___"I!llz:lz.""","",u-
[CHARACTE~:'':.'~~~~ UN' .~J,j..jolJ
HORIZONTAL SYNC DELAY
(FRONT PORCH)
HORIZONTAL SYNC WIDTH
HORIZONTAL LINE COUNT: H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
SCAN LINES PER FRAME
14
~
\111
VERTICAL DATA
START
:1--
START OF FRAME M + 1 OR EVEN FIELD
.. ,
r!(ZZZZZZZOZZ7777Z777ZZ7Z7ZZ~
ACTIVE VIDEO
DATA ROWS PER FRAME
VI-96
.... I~
L
VZZ7
~ VERTICAL SYNC
: 3H
MK3B07 VCU WORK SHEET
Table2A
1. H CHARACTER MATRIX (No. of Dots):
......................................................... _ - -
2. V CHARACTER MATRIX (No. of Horiz. Scan Lines): .............................................. _ _ __
3. H CHARACTER BLOCK (Step 1 + Desired Horiz. Spacing
= No. in Dots): ............................ _ _ __
= No. in Horiz.
Scan Lines): ..........................................................•..................... _ _ __
4. V CHARACTER BLOCK (Step 2 + Desired Vertical Spacing
5. VERTICAL FRAME (REFRESH) RATE (Freq. in Hz): ..................•..••.....................•.. _ __
6. DESIRED NO. OF CHARACTER ROWS: ......•...•....•....•••..•.............................. _ __
7. TOTAL NO. OF ACTIVE "VIDEO DISPLAY" SCAN LINES
(Step 4 x Step 6 = No. in Horiz. Scan Lines): .........................•........................ _ _ __
8. VERT. SYNC DELAY (No. in Horiz. Scan Lines): .................................................. _ _ __
9. VERT. SYNC (No. in Horiz. Scan Lines; T =- - !lS*): .......................................... _ _ __
10. VERT. SCAN DELAY (No. in Horiz. Scan Lines; T
=_ _ ms*): ......•..•......................... _ _ __
11. TOTAL VERTICAL FRAME (Add steps 7 thru 10 = No. in Horiz. Scan Lines): •.••..•.................. _ _ __
12. HORIZONTAL SCAN LINE RATE (Step 5 x step 11
=Freq. in KHz):
................................. _ _ __
13. DESIRED NO. OF CHARACTERS PER HORIZ. ROW: .................••...•........•.•.........•. _ __
14. HORIZ. SYNC DELAY (No. in Character Time Units; T =--!lS**): ............................... _ _ __
15. HORIZ. SYNC (No. in Character Time Units; T = _ _ I's**): ..•...........••.......•............. _ _ __
16. HORIZ. SCAN DELAY (No. in Character Time Units; T
=_ _ I's**): .•.....••••................... _ _ __
17. TOTAL CHARACTER TIME UNITS IN (1) HORIZ. SCAN LINE
(Add Steps 13 thru 16): ...................................... '•............................. _ _ _--:
18. CHARACTER RATE (Step 12 x Step 17
= Freq. in MHz):
.......................................... _ __
19. CLOCK (DOT) RATE (Step 3 x Step 18 =Freq. in MHz): ........................................... _ __
*Verticallnterval
**Horizontallnterval
VI-97
MK3807 VCU WORK SHEET
Table2B
<
REG.#
ADDRESS
A3-AO
o
0000
HORIZ. LINE COUNT _ _
DTlrrlTl
0001
INTERLACE _ _
H SYNC WIDTH _ _
HSYNC DELAY _ _
IIIIIIIII
2
0010
SCANS/DATA ROW _ _
CHARACTERS/ROW _ _
IX I I I
3
0011
SKEW CHARACTERS _ _
DATA ROWS _ _
II I I I I I I I
4
0100
SCANS/FRAME _ _
IIIIIIII]
5
0101
VERTICAL DATA START
3 + VERTICAL SCAN DELAY:
SCAN DELAY _ _
DATASTART _ _
IIIII(II I
6
0110
LAST DISPLAYED DATA ROW
DATA ROWS)
Ix IXI I I I I I I
cD
co
FUNCTION
X= __
=
(=
BIT ASSIGNMENT
I I I LJ
HEX.
DEC.
MK3807 VCU WORK SHEET
Table2C
1. H CHARACTER MATRIX (No. of Dots):
......................................................... _7..L.-_
9..L..._
2. V CHARACTER MATRIX (No. of Horiz. Scan Lines): ..•••..•..•....•••••..••••..••••........•••..• __
3. H CHARACTER BLOCK (Step 1 + Desired Horiz. Spacing
'1
=No. in Dots): .•••••••.•••••.....•••....•• ----!'---
=No. in Horiz.
Scan Lines): .••••••.••••......••...••••••.•...•..•...•.•.••••.......•....•.•.••••...••...•.. _1:..,::2=--.
4. V CHARACTER BLOCK (Step 2 + Desired Vertical SpaChlg
5. VERTICAL FRAME (REFRESH) RATE (Freq. in Hz): ..•.•••.••••••..•.....•....•....••••..•........ _Jt..3~_
10. VERT. SCAN DELAY (No. in Horiz. Scan Lines; T = ~ ms*): ...................................
_.1.19-1-_
11. TOTAL VERTICAL FRAME (Add steps 7 thru 10 =No. in Horiz. Scan Lines): •.•••.....•.•••..........
$10
12. HORIZONTAL SCAN LINE RATE (Step 5 x step 11
= Freq. in KHz):
IB.(P
................................ .
80
13. DESIRED NO. OF CHARACTERS PER HORIZ. ROW: ..•..........•.••.••......•.....•••........•.
~ !lS**): •••.••..•••••....•.•••••••.•.. __4,,--_
HORIZ. SYNC (No. in Character Time Units; T =.!::l..1.=L !lS**): .•.••..••••••••.•••••........••...•.• __9....L..._
14. HORIZ. SYNC DELAY (No. in Character Time Units; T =
15.
16. HORIZ. SCAN DELAY (No. in Character Time Units; T = ~ !lS**): .••••••••••.•••........•.•••.. __C}-1-_
17. TOTAL CHARACTER TIME UNITS IN (1) HORIZ. SCAN LINE
(Add Steps 13 thru 16): ................................................................... .
18. CHARACTER RATE (Step 12 x Step 17
=Freq. in MHz):
102.
1.8> Cj7Z
..........................................
19. CLOCK (DOT) RATE (Step 3 x Step 18 =Freq. in MHz): ........................................... 17.0748
*Verticallnterval
**Horizontallnterval
BIT ASSIGNMENT
Figure 13
HORIZONTAL LINE COUNT
REG 01
~ 11 11 10 i 0 11 101 ; 1
MO~~~NJ..ET'::':~~~D
H SYNS WIDTH
SCANS/DATA ROW
REG2 1 0 1
REG31
H SYNC DELAY
REG 1 1 0 11 1 0 1 0 11 1 # 1
m~
SKEW BITS
1
~ 1 0 '11.1 ~ 1 iliD I
i
11 10 1 11
I~ I
SCAN LINES/FRAME
REG
4\ 0 1 0 \ 0 11 i do 11 11 1
CHARACTERS/DATA ROW
REG 51
LAST DISPLAYED DATA ROW
DA'FA ROWS/FRAME
VERTICAL DATA START
~ I0 1 0 11 i0 11 11 1 ~ 1
VI-99
REG
&1 0 1 0 1 ~ 11 1 0
i
1 11 1
~I
CURSOR CHARACTER ADDRESS
REG 71
~ 1 01010
i
0 101010
I
CURSOR ROW DDRESS
REG£' 010 1
~ 101 0
i
010 1
~I
XTAl Frequency
At a frequency of 18.6KHza scan line takes 53.76 JJS.lnthis
time 102 characters (80 displayed + 22 blanked) have to be
accessed. Thus the character time is 527.06 ns (53.76
Ms/l02). Since each character is 9 dots in this example (7
character and 2 blank), the dot period is 58.56 ns (527.06
ns/9). The inverse of the dot period is the video dot clock
XTAL frequency. Forthisexample, the video dot clockXTAL
is 1/58.56 ns 17.0748 MHz(53.76 Ms/l02). Since each
character is 9 dots in this example (7 character and 2 blank),
the dot period increases in the video clock rate, possibly to a
point beyond the monitor's specification.
=
A more detailed example, using 40 character by 12 row
format, follows.
Having chosen the display format and diliplay monitor, the
actual settings for the VCU registers can now be
established. See Table 2C.
EXAMPLE FOR 40 CHARACTER BY 12 ROWS
Using the VCU worksheet (Table 2A), steps 1 and 2
determine the character matrix. In this example, a 7 X 9 dot
matrix will be used, thus in step 1, 7 dots are used
horizontally and in step 2,9 scan lines are used vertically.
This defines the character size (other character sizes might
be 5 X 7 etc.). Steps 3 and 4 determine the character block
size. The character block is composed of the character
matrix along with both the horizontal and vertical blank
spaces between characters. Step 3 shows the H character
block for this example to be 7 dots from step 1 plus 2
additional dots for blank space, giving a total of 9. Step 4
shows the vertical height (V character block) being 9 lines
from step 2, plus 3 additional raster lines for vertical
spacing, giving a total of 12. The next parameter is the
vertical frame refresh rate and this example uses the
American Standard of 60Hz (in this example the noninterlace mode will also be used).
As this example uses twelve rows of data, step 6 indicates
12. Step 7 determines the number of active video display
raster scan lines. This is determined by taking the number of
raster scan lines from step 4 and multiplying that by the
number of data rows in step 6, thus giving usthe number of
displayed horizontal scan lines. In this example, multiply 12
raster lines per data row by 12 data rows to give 144 active
video raster scan lines.
The next portion of this example is dependent upon the
characteristics of the video monitor being used. For the
purposes of this example a standard sync driven video
monitor using RS-170 non-interlace sync is used. In
accordance with the standard for this monitor, the vertical
sync pulse width will be between 180 and 200 MS. with 190
MS. as the nominal value. In addition, the vertical blanking
interval, which is made up ofthe vertical sync pulse and the
2 delays, is defined as being 1 ms. minimum. The same
monitor specification defines the horizontal sync pulse
width as being between 4 and 6 MS. with 5 MS. as the
nominal horizontal sync pulse width. In addition, the
horizontal sync·delay or front porch is defined as 2.5 MS.
MONITOR HORiZONTAL TIMING
Figure 14
BLANKING INTERVAL----.I
I -HORIZONTAL
/11 p.S MINIMUM)
-I
]I
VIDEO
HORIZONTAL SYNC PULSE
/5 p.S NOMINAl.; 4-6 p.S)
j'
T'
HORIZONTAL SYNC DELAY
/'2.5 p.S NOMINAl; 2 p.S MIN.)
I
VIDEO
'j_"'VOC
~
D
I•
f
HORIZONTAL SCAN DELAY
/5 p.S NOMINAL; 4 p.S MIN.)
VI-100
nominally with a 2 pS. minimum. At the same time, the
horizontal blanking interval, which is composed of the front
porch, horizontal sync pulse, and the back porch is defined
as 11 JJ.s. minimum. See Figures 14 and 15.
The monitor characteristics determine the values for steps 9
and 10. Step 9 lists the vertical sync pulse width. The VCU
has a fixed vertical sync pulse width of 3 horizontal raster
scan lines (3H). Later, the period of a horizontal raster scan
line will be determined and verified that this meets the
RS-170 specification. Enough time must be allowed for
vertical retrace and some blanking at the top of the screen.
This is indicated in step 10 as the vertical scan delay. The
VCU can be programmed for a vertical scan delay between 0
and 255 raster sca n Ii nes to allow util ization of various types
of monitors, as well as to position the data vertically on the
screen. For purposes ofthisexample, a vertical scan delay of
19 raster lines is chosen. After the horizontal period is
determ i ned, it ca n be verified thatthese val ues comply with
the specification. Step 11 is the total number of raster lines
per frame or, in other words, the number of raster lines per
vertical refresh time. Normally, this will be determined by
adding to the number of displayed scan lines, the vertical
sync pulse width, the vertical scan delay, and the vertical
sync delay which has not yet been determined. However, in
this case, since the example uses a standard monitor, it is
possible to work backwards. Therefore, for step 11 we will
enter 262 raster lines per frame (a typical number of raster
lines/field of a standard monitor). Now work backwards to
step 8 and determine the vertical sync delay. This is the
number of raster lines between the last displayed video
raster line and the beginning of vertical sync. Subtracting
144, 19, and 3 from 262 leaves 96, thus for step 8, 96
horizontal lines is the vertical sync delay. We have now
determined the vertical timing waveform for this example.
The next part of the example is to determine the horizontal
scan line rate or how many raster lines per second will be
displayed. This is determined by multiplying the vertical
frame refresh rate from step 5; in this case 60 frames per
second by the total number of raster lines per frame from
step 11, in this case 262. The product will be 15,720 raster
lines per second. This is the horizontal scan rate. The
horizontal period is determined by taking the inverse of
horizontal scan rate, 1 divided by 15,720 Hz is 63.6132 JJ.S.
This is the time of 1 horizontal raster line. This information is
now used to go back and check on meeting the
specifications in steps 9 and 10. Step 9 lists 3 horizontal
lines as the vertical sync pulse width. 3 X 63.6132 JJ.S. yields
190.84 JJ.S. This is the nominal value specified for the
monitor. Step 10 lists the vertical scan delay as 19 raster
lines multiplying that by 63.61 JJ.s. yields 1.21 ms., thus the
values picked for the above parameters meet the
specification for the monitor.
In step 13 the desired number of active display characters
per horizontal data row is listed. 40 character per row have
been chosen. Steps 14, 15 and 16 are now selected using
the horizontal period and the monitor specifications. Step
14 is the horizontal sync delay or front porch. In this case 2
character times. The period of a character will be
determined later in this example which will be used to verify
that this parameter meets the RS-170 specification given
earlier. In step 15 the horizontal sync width is chosen to be4
character times and in step 16 the horizontal scan delay is
MONITOR VERTICAL TIMING
Figure 15
r
4_ _ _ VERTICAL
BLANKING INTERVAL _ _~.~I
(1 mS MINIMUM)
VERTICAL SYNC PULSE
(1901'S NOMINAL 1 BO-200 1'5)
VIDEO
f......-1--,
I_
illIi
1-
f ·1
VERTICAL SYNC DELAY
(0-190 .. 5)
~
VIDEO
~I
t ·1
------,I
iL-----'·'."
DC
I- VERTICAL SCAN DELAY __I
(BOO 1'5 MINIMUM)
1_ VERTICAL SYNC & SCAN DELAY ___I
(1 mS MINIMUM)
VI-101
chosen to also be 4 character times. Step 17 is the total
number of character times per horizontal scan line and this
is determined by adding steps 13 through 16, thus we add
40+2+4+4=50 character times per horizontal scan line. In
step 18 the character rate is determined by multiplying the
horizontal line rate of step 12 by the total character units per
horizontal line., thus, 15,720 X 50 = 786,000 charact.ers per
second. The character period is the inverse of the character
rate, thus 1 over 786,000 yields a character period of 1 .272
p.S. This information is used to verify steps 14,15, and 16.ln
step 14 the horizontal sync delay was chosen as 2 character
units. 2 times 1 .272 p's yields 2.54 p.S. Step 15, the
horizontal sync width was 4 character units. 4 times 1.272
J.IS. yields 5.089 p.S. and similarly, step 16, four character
units also is 5.089 J.IS. These three values are in agreement
with the specification for the monitor. The next step is to
determine the video dot clock frequency. It is determined by
mUltiplying the number of dots per character from step 3 by
the character rate in step 18, 9 X 786 KHz = 7.074 MHz.
Thus, the crystal frequency required for this example is
7.074 MHz and the dot clock counter divisor N is 9 (from
step 3).
Register Programming
Register 0 (Horizontal Line Count) determines the total
number of character units per horizontal line. From step 17
we have determined that there would be 50 character units
per line. This register is loaded with (N- 1) the decimal
number 49.
Register 1 contains 3 fields. The first field is the most
significant bit and this determines the interlaced or noninterlaced mode of operation. This example uses the none
interlaced mode, therefore, bit 7 is loaded with a O. The next
field is the horizontal sync pulse width and this field is bits 6
through 3. Step 15 determines that the horizontal sync
width is 4 character times. Therefore the binary equivalent
of 4 is loaded into these bits. Thos bits 6 through 3 are
loaded with 0100. The thifd field is the horizontal sync
delay, step 14 determines that this is 2 character time units.
Therefore, bits 2 through 0 are loaded with 010.
Register 2 contains 2 fields, with the most significant bit
unused. Bits 6 through 3 determine the scans per data row.
In this example from step 4, there will be 12 raster lines per
data row, and from the VCU data sheet note this is an N + 1
register. Therefore the decimal number eleven is loaded
into bits 6 through 3. the second field is characters per data
row, bits 2 through O. In this example 40 active characters
per data row was chosen. The VCU data sheet specifies that
01 0 in this field will give 40 characters per data row, thus
bits 2 through 0 are loaded with 010.
Register 3 also contains 2 fields. The first field, bits 7 and 6,
are the skew bits. These bits allow the hardware designer to
MK3807 VCU WORK SHEET
1.
2.
3.
. 4.
H CHARACTER MATRIX (No. of Dots): .........................................................
V CHARACTER MATRIX (No. of Horiz. Scan Lines): ...•...................•.......•..........•...
H CHARACTER BLOCK (Step 1 + Desired Horiz. Spacing = No. in Dots): .........•.....•............
V CHARACTER BLOCK (Step 2 + Desired Vertical Spacing = No. in Horiz.
Scan Lines): •.............................................•........•......•.....•...........
5. VERTICAL FRAME (REFRESH) RATE (Freq. in Hz): ...............................................
6. DESIRED NO. OF CHARACTER ROWS: ..................................•.......•.....•....••.•
7. TOTAL NO. OF ACTIVE "VIDEO DISPLAY SCAN LINES"
(Step 4 x Step 6 = No. in Horiz. Scan Lines): .....•....................•..•.•............••....
8. VERT. SYNC DELAY (No. in Horiz. Scan Lines): ..................................................
9. VERT. SYNC (No. in Horiz. Scan Lines; T = ~ J.IS*): ...............•..•••.......••.....••.....
10. VERT. SCAN DELAY (No. in Horiz. Scan Lines; T = ~ ms*): ...................................
11. TOTAL VERTICAL FRAME (Add steps 7 thru 10 = No. in Horiz. Scan Lines): ..............•..........
12. HORIZONTAL SCAN LINE RATE (Step 5 x step 11 = Freq. in KHz): .......••......•......••.........
13. DESIRED NO. OF CHARACTERS PER HORIZ. ROW: .....................•.•............•....•...
14. HORIZ. SYNC DELAY (No. in Character Time Units; T = ~ J.IS**): ............•...•........•....
15. HORIZ. SYNC (No. in Character Time Units; T = ~ J.IS**): .......................•.....•.•.....
16. HORIZ. SCAN DELAY (No. in Character Time Units; T = ~ J.IS**): ....•.......•.................
17. TOTAL CHARACTER TIME UNITS IN (1) HORIZ. SCAN LINE
(Add Steps 13 thru 16): ........ '.' ..........................................................
18. CHARACTER RATE (Step 12 x Step 17 = Freq. in MHz): ..........................................
19. CLOCK (DOT) RATE (Step 3 x Step 18 = Freq. in MHz): ...........................................
*Verticallnterval
**Horizontal Interval
VI-102
_-,7<--_
__94-_
_---.:19__
_ ....I",,;J.L-_
_ ....","""0""-_
_ .....
1:1__
_LIL/:;;-,-ADDRESS/COMMAND
DATA INPUT
ADDRESS/COMMAND
DATA OUTPUT
II. Burst Mode Transfer
1
2
3
4
n
~
SCLKLMJUL
CE~L...______________~fr-________________~~
ff
012345670123
4
5
6 7
II I I)
I/o~'I'I'I'I'I¥1'~
ADDRESS/COMMAND
DATA 110 1
OATAI/O
NOTES
1) Data input sampled on rising edge of clock
2) Data output changes on falling edge of clock
3) Rising edge of CE terminates operation and resets address/command
VII-3
N
FUNCTION
N
n
CLOCK
8
72
RAM
2_ 20O
REGISTER DEFINITION
X4
o
o
CLOCK/CALENDAR
1
1
The Clock/Calendar is contained in 7 addressable/
llliriteable/readable registers, as defined below.
Address
Range (BCD)
Function
0
1
2
Seconds+Clock Halt Flag
Minutes
Hours/ AM-PM/12-24 Mode
3
Date
4
5
6
Month
Day
Year
00-59
00-59
00-23 or
01-12
01-28,29,
30,31
01-12
01-07
00-99
Data contained in the Clock/Calendar registers is in binary
coded decimal format (BCD).
X3 Xtal Mode
o
Binary.
Microprocessor
o Baud Rate
1 Color Burst
1
Primary Frequencies
2 22 , 2 21 , 2 20 Hz
8, 5, 4, 2.5, 2, 1.25, 1 MHz'
7.3728,3.6864,1.8432 MHz
3.5795 MHz
CRYSTAL DIVIDER PRESeALER
X2, Xl, and XO specify a particular prescaler divider
selection necessary to generate a 1 Hz frequency for the
Clock/Calendar. Refer to Figure 4 for complete definition.
SYSTEM CLOCK OUTPUT
Cl and CO designate the system clock output frequency
selected. The options are X, X/2, X/4, and -2 kHz. When in
the Binary Mode, the output frequency is 2048 Hz. In any
other mode the output frequency is -2048 Hz. Refer to
Figure 5 for complete definition.
WRITE PROTECT
CLOCK HALT FLAG
Bit 7 of the Seconds Register is defined as the Clock Halt
Flag. Bit 7 = logical 1 inhibits the 1 Hz input to the
Clock/Calendar. Bit 7 is set to logical 1 on power-up to
prevent counting, and it may be set high or low bywriting to
the seconds register under normal operation of the device.
AM-PM/12-24 MODE
Bit 7 of the Hours Register is defined as the 12 or 24 hour
mode select bit. In the 12-hour mode, bit 5 is the AM/PM
bit, and in the 24-hour mode, bit 5 is the second 1O-hour bit
(20-23 hours).
TEST MODE BITS
Bit 7 of the Date Register and Bit 7 of the Day Register are
Test Mode Bits utilized in testing the MK3805. These bits
should be logic 0 for normal operation.
The Control Register specifies the crystal mode/frequency
to be used, the system clock output frequency, and the
WRITE PROTECT Mode for data protection. The Control
Register is located at address 7 in the Clock/Calendar/
Control address space.
765432
0
WP
Cl
CO
CLOCK/CALENDAR/CONTROL BURST MODE
Address 31 of the Clock/Calendar/Control Address space
specifies Burst Mode operation. In this mode, the 7
Clock/Calendar Registers and the Control Register may be
consecutively read or written. Addresses above address 7
(Control Register) are non-existent; only addresses 0-7 are
accessible.
RAM
The static RAM is contained in 24 addressable/
writeable/readable registers, addressed consecutively in
the RAM address space beginning at location O.
CONTROL REGISTER
I I I I
Bit 7 of the Control Register is the WRITE PROTECT Flag. Bit
7 is set to logical 1 on power-up, and it may be set high or
low by writing to the Control Register. When high, the
WRITE PROTECT Flag prevents a write operation to any
internal register, including the other bits of the Control
Register. Further, logic is included such that the WRITE
PROTECT bit may be reset to a logic 0 by a Write operation
without altering the other bits of the Control Register.
X4
X3
X2
Xl
XO
CRYSTAL DIVIDER MODE
X4 and X3 specify the Crystal frequency divider mode
selected.
RAM BURST MODE
Address 31 of the RAM address space specifies Burst Mode
operation. In this mode, the 24 RAM registers may be
consecutively read or written. Addresses above the
maximum RAM address location are non-existent and are
not accessible.
REGISTER SUMMARY
A Register, Data Format summary is shown in Figure 3.
VII-4
MICROCOMPUTER CLOCK/RAM
ADDRESS/COMMAND, REGISTER, DATA
FORMAT SUMMARY
Figure 3
I. ADDRESS/COMMAND FORMAT
7
6
f]¥1
4
5
A41 A3
I
2
3
A21 A,
II. REGISTER ADDRESS
A. CLOCK
7
6
5
4
3
2
SECI
0
0
0
0
0
MINI
0
0
0
0
HR\
0
0
0
0
DATE \1
0
0
0
0
0
0
0
MONTH 1
0
I l%1
Ao
REGISTER DEFINITION
DAY 1 1
0
0
YEAR 11
0
0
CONTROL 11
1 0
CLOCK
BURST 11
0
1 0
0
I
0
0
11
01- 12 1121
00-23
24 \ 0
11
RAM23 11
RAM
BURST
I
11
1
1
0
0
I
o
••
•
0
11
11
1
MONTH
01
[h;l
01- 07
0
0
0
l%l
0-99
Crwl
00
DAY
0
10YEAR
01
YEAR
I
X
IWpl C, 1 Co 1 4 1 X31 X21
x,
1 Xo 1
00
AO
~
o
0
1 1
1
1
01
11
I I
1
DATE
10
M
B. RAM
RAMO
110DATEI
0
1 1
00
HR
0
\
80
1;~pl HR 1
01- 12 1 0
1 T21
I
MIN
C%l
0
11
11
10 MIN
00- 59 1 0
1
0
11
1
0
0
0
l%1
r%l
SEC
01- 2 8/29\
01-30 T,
01-31
0
0
I~
0
4 3
10SEC
00-591 CH 1
1~
11
11
0
11
11
11
7
0
POWER
ON
RESET
11
~
RAM
D~TA
~
RAM
D:~A
1:%1
VII-5
I
I
I I
XX
••
•
1
I
XX
CRYSTAL FREQUENCY SELECTION TABLE
Figure 4
fXTALIMHz)
X4 X3
X2 X1
XO
Crystal Frequency
8.388608
8.388608
4.194304
4.194304
2.097152
2.097152
1.048576
0.032768
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.000000
5.000000
4.000000
2.500000
2.000000
1.250000
1.000000
0.031250
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.372800
7.372800
3.686400
3.686400
1.84:3200
1.843200
0.921600
0.028800
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.159040
7.159040
3.579520
3.579520
1.789760
1.789760
0.894880
0.027965
1
Comments
Power on condition
"
CLOCK OUTPUT SELECTION TABLE
Figure 5
C1
CO
0
0
1
1
0
1
0
1
CKO
Output Frequency
Comments
fXTAL
f XTAL ";- 2
fXTAL ..;- 4
Power on condition
2048 Hz
Binary mode
VII-6
ELECTRICAL S~ECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS .........................................•.•..........•..... -D.5V to + 12.0V
Operating Temperature, TA (Ambient) ................................................•...•..... -4Q°C to + 85°C
Storage Temperature .............•....................•.................•............•....• -55°C to +125°C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
-40°C ::S TA ::S + 85°C
SYMBOL PARAMETER
VCC
Vss
Supply Voltage
Supply Voltage
MIN
·TYP
MAX
UNIT
NOTES
3.0
0
5.0
0
9.5
0
V
V
1
1
MIN
TYP
MAX
UNIT
NOTES
2.0
0.1
1.0
10.0
rnA
rnA
pA
pA
V
V
V
V
V
V
2
3
4
4
1
1
l(loH =-l00pA)
l(IOL = 1.8 rnA)
1(I OH = -400pA)
1(IOL = 4.0 rnA)
DC ELECTRICAL CHARACTERISTICS
_40°C ::S TA ::S + 85°C, Vcc = 5V ± 100;0
SYMBOL PARAMETER
ICCl
ICC2
IlL
IOL
VIH
VIL
VI/OH
VI/0L
V CKH
V CKL
Power Supply Current
Power Supply Current
Input Leakage Current
Output Lea~age Current
Logic "1" Voltage, All Inputs
Logic "0" Voltage, All Inputs
Output logic "1" Voltage, 1/0 pin
Output Logic "0" Voltage, I/O pin
Output Logic "1 " Voltage, CKO pin
Output Logic "0" Voltage, CKO pin
-1.0
-10.0
2.0
0.8
2.4
0.4
2.4
0.4
NOTES
1. All voltages referenced to Vss.
2. Crystal/Clock Input frequency = 8.4 MHz, outputs open.
3. Crystal/Clock Input frequency = 32,768 Hz. outputs open.
4. Measured with Vee = S.OV, 0:::; VI:::; S.OV, outputs deselected.
VII-7
AC ELECTRICAL CHARACTERISTICS
-40°C:::; TA + 85°C, Vcc 5V ± 10"A>
SYMBOL P~RAMETER
CI
CliO
Cx
fx
tcs
tos
tOH
tOA
too
tCWL
tCWH
fSCLK
tsR, tSF
tCR' tCF
tCEH
MIN
Capacitance on Input pin
Capacitance on I/O pin
CapacitC!rce on XI/CI and X2
Crystal frequency
CE to SCLK set up time
Input Data to SCLK set up time
Input D"ta from SCLK hold time
Output Data from SCLK delay time
to I/O high impedance
SCLK low time
SCLK high time
SCLK frequency
SCLK Rise and Fall Time
CKO Ris.e and Fall Time
CE high time
TVP
MAX
UNIT
NOTES
6
7
10
12
12
pF
pF
pF
5
5
5
8400
kHz
7
27
1.0
1.0
1.0
!JoS
!J.S
!JoS
1.0
1.5
cr
1.95
1.95
DC
2.0
Measured as C = ~ with l:::.V = 3V, and unmeasured pins grounded.
6V
6.
7.
8.
9.
Measured at VIH = 2.0 V ofVIL =, 0.8 V and 5 ns rise and fall times on inputs.
Measured at VOH = 2.4V and VOL = O.4V.
Load Capacitance = 100 pF
tr and tf measured from O.SV to 2.0V
I/O TIMING DIAGRAM
Figure 6
SCLK
1/0
00
!JoS
00
!J.S
250
50
50
kHz
ns
ns
!J.S
NOTES
5.
!J.S
!J.S
----~-.....,
-------IC
OUTPUT DATA
VALID
Vli-B
1,6
1,6
1,6
1,6,7,8
1,6,7,8
9
8,9
MOSTEI(.
MICRO PERIPHERAL COMPONENTS
MK3807
Programmable CRT Video Control Unit (VCU)
FEATURES
PIN CONFIGURATION
o Fully Programmable Display Format
Characters per data row (1-200)
Data rows per frame (6-64)
Raster scans per data row (1-16)
A1
AO
HO
H1
H2
H3
o Programmable Monitor Sync Format
Raster Scans/Frame (256-1 023)
"Front Porch"
Sync Width
"Back Porch"
Interlace/Non-I nterlace
Vertical Blanking
R1
H4
H5
H6
o Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync
Blanking
Cursor coincidence
eSYN
H7/0R5
VSYN
DR4
Dee
DR3
VOO
OR2
Vee
OR1
HSYN
ORO
eRV
080
8L
081
OB7
082
OB6
083
086
o Programmed via:
Processor data bus
External PROM
o BUS Oriented: Compatible with most microprocessors
o Standard or Non-Standard CRT Monitor Compatible
o Second source to SMC CRT 5037
o Refresh Rate: 60 Hz
ON-Channel Silicon Gate Technology
o Scrolling
Single Line
Multi-Line
GENERAL DESCRIPTION
o Cursor Position Registers
o Programmable Character Format
o Programmable Vertical Data Positioning
o Balanced Beam Current Interlace
o Graphics Compatible
o Split-Screen Applications
Horizontal
Vertical
o Interlace or Non-Interlace operation
o TTL Compatibility
The Programmable CRT Video Control Unit (VCU) Chip is a
user programmable 4O-pin n channel MOS/LSI device containing the logic functions required to generate all the
timing signals for the presentation and formatting of
interlaced and non-interlaced video data on a standard or
non-standard CRT monitor. The MK3807 VCU is a second
source to SMC CRT 5037.
With the exception of the dot counter, which may be clocked
at a video frequency above 25 MHz and therefore not
recommended for MOS implementation, all frame
formatting, such as horizontal, vertical, and composite sync,
characters per data row, data rows per frame, and raster
scans per data row and per frame are totally user
programmable. The data row counter has been designed to
facilitate scrolling. Refer to Table 1 for description of pin
functions.
VII-9
Programming is accomplished by loading seven 8-bit
control registers directly off an 8-bit bidirectional data bus.
Four register address lines and a chip enable line provide
complete microprocessor compatibility for program controlled set up. The device can be "self loaded" via an
external PROM tied on the data bus as described in the
OPERATION section.
The MK3807 (VCU) may be programmed for an odd or even
number of scan lines per data row in both interlaced and
non-interlaced modes.
In addition to the seven control registers, two additional
registers are provided to store the cursor character and data
row addresses for generation of the cursor video signal. The
contents of these two registers can also be read out onto the
bus for update by the program.
Figure 1 shows a block diagram of the internal functional
components of the VCU.
DESCRIPTION OF PIN FUNCTIONS
Table 1
Inputl
Output Function
Pin No.
Symbol
25-18
DBO-7
Data Bus
CE
AO-3
I
Name
1/0
9
OS
Chip Enable
Register
Address
Data Strobe
12
DCC
Dot Counter Carry
I
38-32
HO-6
0
7,5.4
R1-3
H7/DR5
Character
Counter Outputs
Scan Counter
Outputs
H7/DR5
RO
Scan Counter LSB
0
26-30
DRO-4
0
17
15
11
10
BL
HSYN
VSYN
CSYN
Data Row
Counter Outputs
Blank
Horizontal Sync
Vertical Sync
Composite Sync Output
16
14
13
CRV
VCC
VDD
Cursor Video
Power Supply
Power Supply
3
39.40,1,2
31
8
I
I
0
0
0
0
0
0
0
PS
PS
VII-10
Data bus. Input bus for control words from microprocessor
or PROM. Bi-directional bus for cursor address.
Signals chip that it is being addressed.
Register address bits for selecting one of seven control
registers or either of the cursor address registers.
Strobes DBO-7 into the appropriate register or outputs the
cursor character address or cursor line address onto the
data bus.
Carry from off-chip dot counter establishing basic character clock rate. Character clock.
Character counter outputs.
Three most significant bits of the Scan Counter; row select
inputs to character generator.
Pin definition is user programmable. Output is MSB of
Character Counter if horizontal line counter (REG.O) is 2':
128; otherwise output is MSB Of Data Row Counter.
Least significant bit of the scan counter. In the interlaced
mode with an even number of scans per data row, RO will
toggle at the field rate; for an odd number of scans per data
row in the interlaced mode, RO will toggle at the data row
rate.
Data Row counter outputs.
Defines non-active portion of horizontal and vertical scans.
Initiates horizontal retrace.
Initiates vertical retrace.
Composite sync is provided on the MK3807. This output is
active in non-interlaced mode only. Provides a true RS,
170 composite sync wave form.
Defines cursor location in data field.
+5 volt Power Supply
+12 volt Power Supply
~~~~~~==----_ _ _~.5l~""
cO
~(")
I ... C
DATA BUS DB 0-7
r--
l>
G)
25-18
j
»
~
SELR2
12
DOT COUNTER
CARRY
CURSOR V ADDRESS
REGISTER
38-32
+
lAi'
:::
...,
mNe
I
I
INTERLACED
t:
q"Ne
_
BL
1_ u
COMPARATOR
I
26 -30
ilR:,: 3'
-
DATA BUS DB 0-7
39,40.1.2
.....
'
~
3CHIP ENABLE
9 DATA STROB~
SCROLL
RESET
START
SElF LOAD
6
17
".lie,'.
OPERATION
The design philosophy employed was to allow the
MK3!307 Programmable CRT Video Control Unit (VCU) to
interface effectively with either a microprocessor based or
hardwire logic system. The device is programmed by the
user in one of two ways; via the processor data bus as part of
the system initialization routine, or during power up via a
Horizontal Formatting:
Characters/Data Row
PROM tied on the data bus and addressed directly by the
Row Select outputs of the chip (See Figure 2). Seven 8-bit
words are required to fully program the chip. Bit
assignments for these words are shown in Tables 2, 3 and
4. The information contained in these seven words consists
of the following:
A 3 bit code providing 8 mask programmable character lengths from 20 to 132. The
standard device will be masked for the following character lengths; 20, 32, 40, 64, 72,
80, 96, and 132.
Horizontal Sync Delay
3 bits assigned providing up to 8 character times for generation of "front porch".
Horizontal Sync Width
4 bits assigned providing up to 16 character times for generation of horizontal sync
width.
Horizontal Line Count
8 bits assigned providing up to 256 character times for total horizontal formatting.
Skew Bits
A 2 bit code providing from a 0 to 2 character skew (delay) between the horizontal
address counter and the blank and sync (horizontal, vertical, composite) signals to
allow for retiming of video data prior to generation of composite video signal. The
Cursor Video signal is also skewed as a function of this code.
Vertical Formatting:
Interlaced/Non-interlaced
This bit provides for data presentation with odd/even field formatting for interlaced
systems. It modifies the vertical timing counters as described below. A logic 1
establishes the interlace mode.
= value of 8
assigned bits.
1) in interlaced mode-scans/frame =2X + 513. Therefore for 525 scans, program X
= 6 (00000110). Vertical sync will occur precisely every 262.5 scans, thereby
producing two interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans,
program X =3 (00000011 ).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (::3H).
Scans/Frame
8 bits assigned, defined according to the following equations: Let X
Vertical Data Start
8 bits defining the number of raster scans from the leading edge of vertical sync until
the start of display data. At this raster scan the data row counter is set to the data row
address at the top of the page.
Data Rows/Frame
6 bits assigned providing up to 64 data rows per frame.
Last Data Row
6 bits to allow up or down scrolling via a preload defining the count of the last
displayed data row.
Scans/Data Row
4 bits assigned providing up to 16 scan lines per data row.
VII-12
ADDITIONAL FEATURES
MK3807 VCU Initialization:
Under microprocessor control-The device can be reset
under system or program control by presenting a 1010
address on A3-0. The device will remain reset at the top of
the even field page until a start command is executed by
presenting a 1110 address on A3-0.
Via "Self Loading"-In a non-processor environment, the
self loading sequence is effected by presenting and holding
the 1111 address on A3-O, and is initiated by the receipt of
the strobe pulse (OS). The 1111 address should be
maintained long enough to insure that all seven registers
have been loaded (in most applications under one
millisecond). The timing sequence will begin one line scan
after the 1111 address is removed. In processor based
systems, self loading is initiated by presenting the 0111
address to the device. Self loading is terminated by
presenting the start command to the device which also
initiates the timing chain.
Scrolling-In addition to the Register 6 storage of the last
displayed data row a "scroll" command (address 1011)
presented to the device will increment the first displayed
data row count to facilitate up scrolling in certain
applications.
CONTROL REGISTERS PROGRAMMING CHART
Table 2
Horizontal Line Count:
Characters/Data Row:
Total Characters/line = N + 1, N = 0 to 255 (DBO = LSB)
DB2
DB1
DBO
Active Characters/Data Row
000
= 20
= 32
o
0
1
o
1
0
=40
1
1 = 64
1
0
0
=72
1
0
1
=80
1
1
0
96
1
1
1
132
= N, from 1 to 7 character times (DBO = LSB, N =0 Disallowed)
=N, from 1 to 15 character times (DB3 = LSB, N =0 Disallowed)
Sync/Blank Delay
Cursor Delay
DB7
DB8
(Character Times)
0
0
0
1
0
1
0
o
=
=
Horizontal Sync Delay:
Horizontal Sync Width:
Skew Bits
o
o
Scans/Frame
Vertical Data Start:
Data Rows/Frame:
Last Data Row:
Mode:
Scans/Data Row:
1
2
1
1
1
2
2
8 bits assigned, defined according to the following equations:
Let X =value of 8 assigned bits. DBO = LSB)
1) in interlaced mode- scans/frame =2X + 513. Therefore for 525 scans, program X =6
(0000110). Vertical sync will occur precisely every 262.5 scans, thereby producing two
interlaced fields.
.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame =2X + 256. Therefore for 262 scans, program
X =3 (00000011).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (= 3H)
N = number of raster lines delay after leading edge of vertical sync of vertical start position.
(DBO = LSB)
Number of data rows = N + 1, N =0 to 63 (DBO = LSB)
N = Address of last displayed data row, N =0 to 63, ie; for 24 data rows, program N = 23.
(DBO =LSB)
Regster, 1, DB7 = 1 established Interlace.
Interlace Mode
Scans per data Row = N + 2. N =0 to 14, odd or even counts.
Non-Interlace Mode
Scans per Data Row = N + 1, odd or even count, N =0 to 15.
VII-13
SELF LOADING SCHEME
Figura 2
-.
...
DBO ~
.......
....
..
........
v-
... '"
.A
"'"
...
~
........
.......
...
...
~
!
A1 A 2 . Aa. CE
!
MK3B07
PROGRAMMABLE
CRT VIDEO CONTROL UNIT
(VCU)
.-.
A
DB7 ...
Ao
... 1..0
......
..
! +~
.-
A
RO
R1
R2 R3
Ao
A1
MK2716
SLOAD
(FROM SYSTEM)
A2
;'
Aa
CE
A4
+5
ROW SELECTS
TO CHARACTER GENERATOR
OPTIONAL START-UP SEQUENCE
When employing microprocessor controlled loading of the
MK3807 VCU's registers. the following sequence of
instruction may be used optionally:
ADDRESS
1 1 1 0
1 0 l' 0
o 0 0 0
COMMAND
Start Timing Chain
Reset
Load Register 0
o
Load Register 6
Start Timing Chain
1
1
1
0
0
The sequence of START RESET LOAD START is necessary
to insure proper initialization of the registers.
This sequence is not required if register loading is via either
of the Self Load modes.
VII-14
REGISTER SELECTS/COMMAND CODES
Table 3
A3
0
0
0
0
0
0
0
0
A2
0
0
0
0
A1
0
0
AO
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
Description
Select/Command
Load Control Register 0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load
See Table 4
Command from processor instructing
MK3807 VCU to enter Self Load Mode (via
external PROM)
Read Cursor Line Address
Read Cursor Character Address
Reset
1
Resets timing chain to top left of page. Reset is
latched on chip by OS and counters are held
until released by start command.
Increments address of first displayed data row
on page, i.e.; prior to receipt of scroll
command-top line =0, bottom line =23. After
receipt of Scroll Command-top line = 1,
bottom line =O.
Up Scroll
0
o
o
o
1
o
1
Load Cursor Character Address 1
Load Cursor Line Address1
Start Timing Chain
Receipt of this command after a Reset or
Processor Self Load command will release the
timing chain approximately one scan line later.
In applications requiring synchronous operation of more than one VCU the dot counter
carry should be held low during the OS for this
command.
Device wi II begin self load via PROM when OS
goes low. The 1111 command should be
maintained on A3-0 long enough to guarantee
self load. (Scan counter should cycle through at
least once). Self load is automatically terminated and timing chain initiated when the all
"1 's" condition is removed, independent of OS.
For synchronous operation of more than one
VCU, the Dot Counter Carry should be held
low when the command is removed.
Non-Processor Self Load
NOTE 1:
During Self-Load. the Cursor Character Address Register (REG 7) and the Cursor Row Address Register(REG 8) are enabled during states 0111 and 1000 of the
R3-RO Scan Counter outputs respectively. Therefore, Cursor data in the PROM should be stored at these addresses.
BIT ASSIGNMENT CHART
Table 4
HORIZONTAL LINE COUNT
. .&. I- II~
;-,-1. . . .
REG 0 L-I
I_IL-...I--,I--I-I
117161 i R. I
SKEW BITS DATA ROWS/FRAME
REG
31m
REG
I
I
1312~
REG
[
I0I REG 6 r-Ix-'-Ix" 'I. r: :~;::1~i:::::;:::1:::;\L,~I
SCAN LINES/FRAME
MODE INTERLACED H SYNC WIDTH H SYNC DELAY
NON-INTERLACED
II I
41
I
21 X I! I
i I~ I[TI I
REG
CURSOR CHARCTER ADDRESS
i
I
I I I i I I I! I 71 ; I I I I I 10 I
REG
CHARACTERS/DATA ROW VERTICAL DATA START
REG
LAST DISPLAYED DATA ROW
51 ~ I
I \ i I I II I
VII-15
CURSOR ROW ADDRESS
I I~ I
REGS x \ x
i
I~ \
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ........••.....•.•....•...••.....•......••••.•.•.•••...•..•..... O°C to + 70°C
Storage Temperature Range ........•••...•...•..•.•..••...........•••••..•••••.•......... -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ...•.......••.......•..............••...........•.....•....... + 325°C
Positive Voltage on any Pin, with respect to ground ......................•.•.....•..•...••.•.......... + 1B.0 V
Negative Voltage on any Pin, with respect to ground .............•••..........•.•.......•..•....•••...•• -0.3 V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and funcitonal operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result.
Some power supplies exhibit.voftage spikes or "glitches" on their outputs when the AC power is switched on and off. In addition. voltage transients on the AC power line may
appear on the DC output. For example. the bench power supply programmed to deliver + 12 volts may have large voltage transients when the AC power is switched on and off. If
this possibility exists it is suggested that a clamp circuit be used.
DC CHARACTERISTICS
(TA = O°C to 70°C; VCC = +5V
± 5%, VOO
= +12V
PARAMETER
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level - VOL for RO-3
Low Level - VOL, all others
High Level- VOH for RO-3, OBO-7
High Level - VOH all others
± 5%, unless otherwise noted)
MIN
TYP
MAX
O.B
VCC-1.5
UNIT COMMENTS
VCC
V
V
0.4
0.4
V
V
250
10
p.A
p.A
15
15
pF
pF
pF
10
p.A
100
rnA
rnA
2.4
2.4
INPUT CURRENT
Low Level, IlL (Address, CE only)
Leakage, IlL (All inputs except Address, CE)
INPUT CAPACITANCE
Data Bus, CIN
OS, Clock, CIN
All other, CIN
10
25
10
40
IOL=3.2 rna
IOL=1.6 rna
IOWBOl.La
IOw4OI.La
VIWO.4V
0::; VIN ::; VCC
DATA BUS LIOAKAGE in INPUT MODE
lOB
POWER SUPPLY CURRENT
BO
40
ICC
100
VII-16
60
0.4 ::; VIN ::; 5.25 V
AC CHARACTERISTICS
(TA = 25°C)
PARAMETER
MIN
DOT COUNTER CARRY
frequency
PWH
PWL
t r , tf
0.5
35
215
TVP
4.0
10
DATA STROBE
PWDS
150ns
MAX
50
UNIT COMMENTS
MHz
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 4
lOlls
ADDRESS, CHIP ENABLE
Set-uptime
Hold time
125
50
ns
ns
Figure 4
Figure 4
DATA BUS - LOADING
Set-up time
Hold time
125
75
ns
ns
Figure 4
Figure 4
125
60
ns
ns
Figure 4, CL =50pF
Figure 4, CL =50pF
125
ns
Figure 3, CL =20pF.
500
ns
Figure 5, CL =20pF
DATA BUS - READING
TOEL2
TOEL4
5
OUTPUTS, HO-7, HS, VS, BL, CRV
CE-TDELl
OUTPUTS: RO-3, DRO-5
*
TDEL3
AC TIMING DIAGRAMS
VIDEO TIMING
Figure 3
trll+
-'Iljtt
rr---------.~
DOT COU"". ' \
CARRY
~~--~~~~~~=========-PW--L------------~--------------------~--~.:J~.~~~------PWH-----4.J~I'---
HO-7
H SYNC, V SYNC, BLANK,
CURSOR VIDEO,
COMPOSITE SYNC
...
TDEL1 -----+I
RESTRICTIONS
1.
Only one pin is available for strobing data into the device via the data bus. The cursor X and Y coordinates are loaded into the chip by presenting one set of addresses
and outputed by presenting a different set of addresses. Therefore, the standard WRITE and READ control signals from most microprocessors must be "NORed" externally to
present a single strobe {OS) signal to the device.
2. In interlaced mode the total number of character slots assigned to the horizontal scan must be even to insure that vertical sync occurs precisely between horizontal sync
pulses.
VII-17
LOAD/READ TIMING
Figure 4
I....- - - - T S E T UP 1 - - - - - l..
~1
ADDRESS
CHIP ENABLE
DBO·7
LOADING IN
OF DATA
DBO·7
READING OUT
OF DATA
5S----------------------------~
SCAN AND DATA ROW COUNTER TIMING
FigureS
HSYNC~
RO·3
DRO.5
-----------_-!_-,..._---J~
. - TDEL3 *
*RO·3 and DRO·5 mav change prior to tha felling edge of H sync
GENERAL TIMING
Figure 6
HORIZONTAL TIMING
t::
START OF LINE N
START OF LINE N+1 - .
JlI....----ILV..L./t.......!Z'-L/..I-It.. . . Z2~7..1-Z/'-'Z..L.7L,...j/Z[....LZ_L.Z..I_O'_'_!_'_/.L...I.O[....LZ_'_Z~ZA"----In
...
I-TV/'T70-r-Z'T7/
ACTIVE VIDEO =
CHARACTERS PER DATA LINE ----+t""""0t4~
HORIZONTAL SYNC DELAY
(FRONT PORCH)
HORIZONTAL SYNC WIDTH
HORIZONTAL LINE COUNT=H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
START OF FRAME M+1 OR EVEN FIELD
11-0.......- - - - - - - - SCAN LINES PER FRAME - - - - - - - - - - '..
~I
J1~__..LV.L.I.//_L./..I-/L,...j//[....L/..L.ZL.../.Z2~7..1_ZZI......l.Z_L.Z..L.Z.L..JZ/-,-Z..l-Z,-,ZZ'-LZ..l_!.L...I.ZZ'-LZ..L-Z~/I1~nl77l7
I...
VERTICAL DATA
START
~..
------1'
ACTIVE VIDEO =
DATA ROWS PER FRAME
VII-18
.1
~
.
L
VERTICAL
SYNC:; 3H
COMPOSITE SYNC TIMING
Figure 7
n
n
,,
n
n
I
,
,
,
,,
,
I
I
rL
V SYNC
I
I
I
.:'"
H-";
,
- I
r -________~~H/2~
'
:
COMPOSITE
SYNC
VERTICAL SYNC TIMING
Figure 8
---------------t_-il.."'i----------- FRAME M+I - - - - - - - - - - - -
- - - - - - - - - - - - - - FRAME M
SCAN COUNTER IS HELD
RESETDURINGV BLANK--,
SCANS/DATA
H
I I
ROW
13579~
COUNTER-RO 0
2
4
6
8
0
2
4
6
8
0
N=9
DATA ROW COUNTER
MAINTAINS LAST COUNTDURING V BLANK
DATA ROW
23
COUNTER-DROl
N=23
22
~
J
I
23~
231
o--'
' - - - - - -7f
__
fVERTICAL DAtA START SCAN = (REG6)
lJU1JU1JlJ1JillJLJlJ111JU1JUL
BLANK
VERTICAL
SYNC
-----------------EXAMPLE BASED ON NON-INTERLACED (REG 1. 81T7
VII-19
0
0).24 DATA ROWS. 10 SCANS/DATA ROW
VIl-20
MOSTEI(.
Z80 MICROCOMPUTER PERIPHERALS
STI-Z80 Version
MK3801
DEVICE PINOUT
Figure 1
FEATURES
o Full Duplex USART
o
Two Binary Delay Timers
o
Two Full Feature Timers with
• Delay to Interrupt Mode
• Pulse Width Measurement Mode
• Event Counter Mode
o
Eight General Purpose Lines with
• Full Bi-Directionall/O Capability
• Edge Triggered Interrupts on Either Edge
o
Full Control of Each Interrupt Channel
• Enable/Disable
• Maskable
• Automatic End-of-Interrupt Mode
• Software End-of-Interrupt Mode
• Automatic End-of-Service Mode
TAO
TBO
TCO
TOO
TCL1
Mi
AESE'F
10
11
12
13
14
15
16
17
PI
IRQ
PO
iiii'i'A
Vss
AO-A3
INTRODUCTION
The MK3a01 is a multifunctional peripheral device for use
in zao based systems. It provides a USART, four timers (two
binary and two full function), and eight bi-directional I/O
lines with individually programmable interrupts. The
interrupt structure ofthe device is fully programmable for all
interrupts, provides for interrupt vector generation,
conforms to the zao daisy chain interrupt priority scheme,
and supports automatic end-of-interrupt and end-of-service
functions for the zao.
DO - D7
RESET
10 -17
IRQ
PIN DESCRIPTION
Figure 1 illustrates the pinout ofthe MK3ao1. The functions
of these individual pins are described below.
SIGNAL
NAME
DESCRIPTION
Ground.
+5 volts (± 5 or 10 percent)
Chip Select (negative true)
Read Enable (negative true)
Write Enable (negative true)
PI
PO
SO
SI
RC
TC
TAO - TOO
TCL1
Mi
VII-21
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11 )
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
.
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
Vee
RC
81
80
TC
AO
A1
A2
A3
~
C$
R5
07
06
05
04
03
02
01
DO
Address Inputs. Used to address one of
the internal registers during a read or
write operation.
Data Bus (bi-directional).
Device Reset (negative true). When
activated, all internal registers (except
for Timer or USART Data Registers) will
be cleared, all timers stopped, USART
turned off, all interrupts disabled and all
pending interrupts cleared, and all I/O
lines placed in tri-state mode.
General purpose I/O and interrupt lines.
Interrupt Request Output (active
open drain).
Interrupt Acknowledge. Used t~ signal
the MK3a01 that the CPU is acknowledging its interrupt.
Priority Input.
Priority Output.
Serial Output.
Serial Input.
Receiver Clock Input.
Transmit Clock Input.
Timer Outputs.
Timer Clock Input.
zao Machine Cycle One (negative true)
,
INTERNAL ORGANIZATION
Figure 2
RESET
TCl1
INTERNAL CONTROL
lOGIC
!'
-.
TIMERS
C&D
DATA
~
..
I
I
WR
'f
-..
C
P
U
..-
T DO
-'~
ADDR
RD
TC o
..-
TIMERS
A&B
TAo
TBo
..
SI
0
..
B
U
S
- ...-.
-
~
USART
-
...
.. I
I
GENERAL
PURPOSE
1/0 ·INTRPT
RC
So
TC
10·17
r
INTERRUPT
CONTROL
-
,~
INTA
PI
-
I RQ
PO
INTERNAL ORGANIZATION
transfer status and data between the system and the
MK3801.
Figure 2 illustrates the MK3801 internal organization,
supporting the full set of timing, communications, parallel
1/0, and interrupt processing functions available in the
device.
CPU 1/0 BUS
Each register in the MK3801 is addressed over the address
bus and with Chip Select (/CS). while data is transferred
over the eight bit Data bus under control of Read (lRD) and
Write (lWR) signals.
INTERRUPT CONTROL
The CPU 1/0 Bus provides the means of communications
between the system and the MK3801. Data, Status, and,
Control Registers in the MK3801 are accessed by the bus in
order to establish device parameters, assert control, and
The Interrupt Control section provides full vectored interrupt
control processing for all 110 facilities ofthe MK3801. Each
individual function is provided with a unique interrupt
VII-22
vector that is presented to the system during the interrupt
acknowledge cycle. All interrupts are fully maskable, with
individual enable and disable controls. In addition, the
interrupts associated with each ofthe General Purpose 1/0
lines may be programmed to occur on either the rising edge
or the falling edge of the incoming signal. Optional End-ofInterrupt modes and End-of-Service modes are available
under software control.
section is capable of either asynchronous or synchronous
operation. Variable word width and start and stop bit
configurations are available under software control for
asynchronous operation. For synchronous operation, a
Sync Word is provided to establish synchronization during
receive operations. The Sync Word will also be repeatedly
transmitted when no other data is available for
transmission.
TIMERS
Separate receive and transmit clocks are available, and
separate receive and transmit status and data bytes allow
independent operation ofthe tra nsmit a nd receive sections.
Four timers are available on the MK3801. Two provide full
service features including delay timer operation, event
counter operation, pulse width measurement operation,
and pulse generation. The other two timers provide delay
timer features only, and may be used for baud rate
generators for use with the USART.
All timers are prescalerlcounter timers, with a common
independent clock input, and are not required to be operated
from the system clock. In addition, all timers have a time-out
output function that toggles each time the timer times out.
USART
Serial Communication is provided by the USART. This
GENERAL PURPOSE 1/0 - INTERRUPT PORT
The General Purpose 1/0 -Interrupt Port provides eight 1/0
lines that may be operated either as inputs or outputs under
control of software. In addition, each line may generate an
interrupt on either a positive going edge or a negative going
edge of the input signal.
Two ofthe lines in this port provide auxiliary input functions
for the timers in the pulse width measurement mode and
the event counter mode. Two others serve as auxiliary
output lines for the USART, and reflect the status of the
receive and transmit buffers, for control of DMA operations.
VII-23
VII-24
MOSTEI(.
8-BIT A/D CONVERTER/8-CHANNEL ANALOG MULTIPLEXER
MK50808(N/P)
FEATURES
The pin configuration of the MK50aOa is shown in
Figure 1.
o Single 5-Volt Supply (± 5%)
o
Low Power Dissipation - 6.825mW(max) at 640kHz
o
Total Unadjusted Error
o
Linerarity Error
o
< ± Y2
LSB
PIN CONNECTIONS
Figure 1
< ± Y2 LSB
No Missing Codes
o
Guaranteed Monotonicity
o
No Zero Adjust Required
o
No Full-Scale Adjust Required
IN3_1
28_IN2
IN4-2
27_INl
IN5_3
26-INO
IN6_4
25_AOOA
IN7-5
24-AOOB
2 3 _ AOOC
START-6
EOC.-.7
o
10aILs Conversion Time (Typically)
o
Easy Microprocessor Interface
o
03_8
THREE-STATE_.
CONTROL
o
8-channel Analog Multiplexer
o
Latched Address Input
o
Fixed Reference or Ratiometric Conversion
o
Continuous or Controlled Conversion
o
On-Chip Chopper-Stabilized Comparator
o
Low Reference-Voltage Current Drain
DESCRIPTION
The MK50aOa is a monolithic CMOS device with an 8bit successive approximation AID converter, an 8channel analog multiplexer and microprocessorcompatible c~>ntrollogic. The 8-channel multiplexer can
directly access anyone of a single-ended analog
channels. The 8-bit AID converter consists of 256
series resistors with an analog switch array, a chopperstabilized comparator and a successive approximation
register. The series resistor approach guarantees
21_07
9
20-06
CLOCK-10
19-05
Vee -..11
18_04
REF(+)-..12
Latched TIL-Compatible Three-State Output with
True Bus-Driving Capability
22-ALE
GNO-..13
01_14
17_00
16-REF(-)
15-02
monotonicity and no missing codes as well as allowing
both ratiometric and fixed-reference measurements.
The need for external zero and full-scale adjustments
has been eliminated and an absolute accuracy of:S;; 1
LSB, including quantizing error, is provided. A block
diagram of the MK50aOa is shown in Figure 2.
All digital outputs are TIL-compatible, all digital inputs
are TTL-compatible with a pull-up resistor, and all
digital inputs and outputs are CMOS-compatible; this
makes it easy to interface with most microprocessors.
The output latch is three-state and provides true busdriving capability (300ns from Three-State Control to Q
Logic State with 200pF load). A Start signal initiates the
conversion process, and, upon completion, an End-OfConversion signal is generated. Continuous conversion
is possible by tying the Start-Convert pin to the End-ofConversion pin.
VII-25
The MK50808 fealures low power, high accuracy,
minimal temperature dependence, and excellent longterm accuracv and repeatability. These characteristics
make this device ideally suited to machine and
MK60BOB BLOCK
industrial controls.
A block diagram of a microprocessor control system
using the MK50808 is shown in Figure 3.
DIA~RAM
Figure 2
START CLOCK
...,
r7c;;m.t.:f~
____
-oEND OF
CONVERSION
,-
CHANNEL
8 ANALOG
INPUTS
~~t~rG 1----1
PLEXER
.... ,T
}
3.~IT
ADDRESS
L _...,
{
AODRESS
LATCH
ENABLE
II
Vee GNO REFf+)
REF(-I THREE·STATE
CONTROL
TYPICAL MICROPROCESSOR CONTROL SYSTEM
Figure 3
DISPLAY
MK&0808
PHYSICAL
VARIABLE
Tem......ture
Pr....re
Weigh.
Flow
Ugh.
Humidity
pH
ate.
AID
CONTROLLER
OAC
VII-26
OUTPUT
FUNCTIONAL DESCRIPTION (Refer To Figure 2 for
a Block Diagram)
ADDRESS, Pins 23-25
The address decoder allows the a-input analog
multiplexer to select anyone of a single-ended analog
input channels. Table 1 shows the required address
inputs to select any analog input channel.
resistors in the ladder. They are chosen so that the
output characteristic will be symmetrical about its fullscale and zero points. The first output transition occurs
when the analog signal reaches +¥2 LSB and
succeeding transitions occur every 1 LSB until the
output reaches ful! scale.
ANALOG INPUTS, Pins 1-5, 26-28
These inputs are multiplexing analog switches which
accept analog inputs from OV to VCC.
ADDRESS LATCH ENABLE, Pin 22
A positive transition applied to the Address Latch
Enable (ALE) input latches a 3-bit address into the
address decoder. ALE can be tied to Start with
parameter to being satisfied.
CLOCK INPUT, Pin 10
This Clock Input will accept an external clock input from
100kHz to 1 .2MHz
The comparator is the most important section of the
AID converter because this section determines the
ultimate accuracy of the entire converter. It is the DC
drift of the comparator which determines the repeatability of the device. A chopper-stabilized comparator
was chosen because it best satisfies all the converter
requirements.
The chopper-stabilized comparator converts the DC
input signal into an AC signal. This signal is amplified by
a high-gain AC amplifier and the DC level is restored.
This technique limits the drift component of the
comparator because the drift is a DC component which
is not passed by the AC amplifier.
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES [REF (+) and REF (-I], Pins 12 and 16
These inputs supply voltage references for the analogto-digital converter. Internal voltage references are
derived from REF (+) and REF H by a 2S6-R ladder
network, Figure 4.
Since drift is virtually eliminated, the entire AID
converter is extremely insensitive to temperature and
exhibits very little long-term drift and input offset error.
This approach was chosen because of its inherent
monotonicity, which is extremely important in closedloop feedback control systems. A non-monotonic
transfer characteristic can cause catastrophic oscillations within a system.
RESISTOR LADDER AND SWITCH ARRAY
Figure 4
The top and bottom resistors of the ladder network in
Figure 4 are not the same value as the rest of the
.
CONTROLS FROM SAR
REFI+)
ANALOG CHANNEL SELECTION
Table 1
SELECTED
ANALOG CHANNEL
R
R
ADDRESS LINE
C
B
A
INO
L
L
L
INl
L
L
H
IN2
L
H
L
INJ
L
H
H
IN4
H
L
L
IN5
H
L
H
IN6
H
H
L
IN7
H
H
H
··
·
250R:
R
R
REF!·)
VII-27
TO
COMPARATOR
INPUT
•
START. Pin 6
8-BIT DIGITAL OUTPUT. Pins 8,14.15.17-21
The AID converter's successive approximation register
(SAR) is reset by the positive edge of the Start pulse.
Conversion begins on the falling edge ofthe Start pulse.
These pins supply the binary digital output code which
corresponds to the analog input voltage. DO is the least
significant bit (LSB) and 07 is the most significant bit
(MSB). This output is stored in a TTL-compatible threestate output latch which can drive a 200pF bus from
high impedance to either logic state in 300ns. Each pin
can drive one standard TTL load.
A conversion in progress will be interrupted if a new
Start pulse is received and a new conversion will begin.
END OF CONVERSION. Pin 7
THREE-STATE CONTROL. Pin 9
The End-Of-Conversion (EOC) output goes high when
the conversion process has been completed. The
positive edge of the EOC output indicates a valid digital
output. Continuous conversion can be accomplished by
tying the EOC output to the Start input. If the AID
converter is used in this mode, an external Start
pulse should be applied after power up. End of
Conversion will go low within 2 clock periods after the
positive edge of Start.
The Three-State Control allows the converter to be
connected to an 8-bit data bus. A low level applieq to
this input causes the digital output to go to a high
impedance state and a high level causes the output to go
to a Q logic state.
ABSOLUTE MAXIMUM RATINGS* (Note 1)
Absolute Maximum VCC ............................................................................. 6.5V
Operating Temperature Range ..................................................... MK50808 O°C to + 70°C
MK50808-1 -40° to +85°C
Storage Temperature Range ............................................................... -65 0 to +150°C
Power Dissipation at 25°C ....................................................................... 500mW
Voltage at any Pin except Digital Inputs ................................................. -0.3 to VCC + 0.3V
Voltage at Digital Inputs ..................................................................... -0.3 to +15V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operationaf
the device at these or any other condition above those indicated in the operational section~ of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
MK50808, MK50808-1 (Note 1)
SYM
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCC
Power Supply
Voltage
Measured at
VCC pin
4.75
5.00
5.25
V
From REF(+)
to REF(-)
0.512
5.12
5.25
V
VCC
VCC+0.1
V
~ VCC+0.1
V
VLADDER Voltage Across
Ladder
VREF(+)
(VREF(f)+)
VBEFH
2
VREFH
Voltage at Top
of Ladder
Measured at
REF(+)
Voltage at Center
of Ladder
Measured at
RLADDERI2
Voltage at Bottom
of Ladder
Measured at
REF(-)
~-0.1
2
-0.1
VII-28
2
0
UNITS NOTES
2"
V
2
DC CHARACTERISTICS
All parameters are 100% tested at 25°C. Device parameters are characterized at high and low temperature
limits to assure conformance with the specification.
MKS0808, MKS0808-1
4.75 ';;;VCC';;; 5.25V, -40';;; TA';;; +85°C unless otherwise noted
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VINHIOH
Logic In~ut
High Vo tage
Vec = 5V
V1NLOW
Logic Input
Low Voltage
Vec = 5V
Logic Output
High Voltage
lOUT = -360MA
Logic Output
Low Voltage
lOUT = 1.6mA
0.4
V
Logic Input
High Current
V1N = 15V
1.0
MA
Logic Input
Low Current
V1N = OV
VOUTHIGH
VOUTLOW
IINHIGH
hNLOW
Icc
Supply Current
lOUT
Three-State
Output Current
3.5
V
1.5
VOUT = VCC
VOUT = OV
V
V
VCC-0.4
-1.0
Clk. Freq=500kHz
Clk. Freq=640kHz
NOTES
MA
300
1000
MA
MA
3
MA
MA
MAX
UNITS
1300
-3
DC CHARACTERISTICS
MK50808-1, -40';;; TA';;; +85°C; MK50808, 0° ,;;; TA';;; + 70°C
S YMBOL
PSR
RLADDER
PARAMETER
CONDITIONS
Power Supply
Rejection
4.75';;; Vec = VREP(+)
';;;5.25V;VREF(-)=GND
Ladder Resistance
From REF(+) to
REFH
MIN
TYP
0.05
3.8
7
0.15
%/V
NOTES
10
kfl
ANALOG MULTIPLEXER
MKS0808, MKS0808-1
-40° ,;;; TA';;; +85°C unless otherwise notea
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ION
On-Channel Input
Current
fe = 640kHz
!?uring Conversion
-2
±.05
+2
MA
11
10
200
nA
IOFF(+)
IOFFH
Off - Channel
Leakage Current
Vcc=5V, V1N =5V,
TA=25°C
Off - Channel
Leakage Current
Vcc=5V, V1N=OV,
TA = 25°C
-200
VII-29
-10
nA
CONVERTER SECTION
Vee =VREF(+) 5V. VElEF(-) =GND. VIN=;VeOMPARATOR IN. fe = 640kHz
MK50BOB-l.-40~TA~+B5°e unless otherwise noted
=
PARAMETER
CONDITIONS
MIN
TVP
Resolution
MAX
UNITS
8
Bits
NOTES
Non-Linearity Error
±%
±Y2
LSB
3
Zero Error
±%
± Y2
LSB
5
Full-Scale Error
±%
± Y2
LSB
6
±'A
± .Y2
±%
LSB
LSB
7
±Y2
LSB
B
±%
±%
±1
±1%
LSB
LSB
9
TVP
MAX
UNITS
NOTES
B
Bits
Total Unadjusted
Error
TA= 25°C
±%
Quantizing Error
Absolute Accuracy
TA = 25°C
MK50BOB. 0° ~ TA ~ + 70°C
PARAMETER
MIN
Resolution
Non-Linearity Error
±Y2
±1
LSB
3
Zero Error
±%
±Y2
LSB
5
Full-Scale Error
±%
± Y2
LSB
6
Total Unadjusted Error
±Y2
± 1
LSB
7
± Y2
LSB
B
±1Y2
LSB
9
Quantizing Error
± 1
Absolute Accuracy
FULL-SCALE. QUANTIZING AND ZERO ERROR
NON-LINEARITY ERROR
Figure 5
Figure 6
OUTPUT
OUTPUT
CODE
CODe
INFINITE RESOLUTION
PERFECT CONVERTER
111
110
101
100
011
010
001
000
CSB
VII-30
AC CHARACTERISTICS (Figure 7)
MK50808. MK50808-1.TA = 25°C.VCC = VREF(+) = SV or S.12V,VREFH = GND
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tws
Start Pulse Width
200
ns
tWALE
Minimum ALE
Pulse Width
200
ns
Address Set-Up
Time
50
ns
tH
Address Hold Time
50
ns
tD
Analog MUX Delay RS+RONO:;;; 5kU
Time from ALE
tHI. tHO
Three-State Control CL = 50pF
to Q Logic State
CL = 200pF
tiH. toH
Three-State Control CL = lOpF.
RL = 10k!)
to Hi-Z
ts
1
2.5
I-'s
125
250
300
ns
ns
125
250
ns
106
108
110
I-'s
100
640
1200
kHz
2
Clock
Periods
tc
Conversion Time
fe
External Clock Freq.
tEOl"
EOC Delay Time
CIN
Input Capacitance
At Logic Inputs
At MUX Inputs
10
5
15
7.5
pF
pF
COUT
Three-State Output At Three-State
Capacitance
Outputs
S
7.5
pF
fC= 640kHz
0
VII-31
NOTES
12
4
TIMING DIAGRAM
Figure 7
A
CLOCK_~~
,I
50%
ALE
,J50%
----,1,
ADDRESS
l
I-tWALE
!--rlTABLE ADDRESS
.
ts ....
!
50%
50o/~
\
1- ~~tH
----,
INPUT
.-
[-- r-
STABLE
-
\\
~
MUX
OUTPUT
START
"
-<;;1/2 lSB
:--
tD _ _
50%
~
50%
i4- t WS ....
50%
THREE-STATE
CONTROL
---tc
EOC
i--- tEOC
OUTPUTS
(50pF Load)
~50%
50%/
.
tHl. tHO-=--'
!
10%
l
S.
6.
7.
l~tHO
t lH. tOH
r--90%
~
10%
~:~1___________________________2__.4~-O-4V------~--'~------1
___________________H_I_G_H_I_M_P_E_D_A_N_C_E______
NOTES:
1. All voltages are measured with respect to GNO.
2. The minimum value for VLADDER will give 2mV resolution. However, the
guaranteed accuracy is only that which is specified under "DC
Characteristics"
3. Nonwlinearity error is the maximum deviation from a straight line through
4.
r-r
O%
HIGH IMPEDANCE
tHl=:
~~ci:~I!adl
50%
J
8.
9.
the end points of the AID transfer characteristics. Figure 6.
10.
When EOC is tied to START. EOC delay is 1 clock period.
Zero Error is the difference between the actual input voltage and the
design input voltage which produces a zero output code, Figure 5.
Full~Scale Error is the difference between the actual input voltage and the
design input voltage which produces a full~scale output code, Figure 5.
Total Unadjusted Error is the true measure of accuracy the converter can
provide less any quantizing effects.
11.
12.
VII-32
Quantizing Error is the ±% LSB uncertainty caused by the converter's
finite resolution, Figure 5.
Absolute Accuracy is the difference between the actual input voltage and
the full~scale weighted equivalent of the t,inary output code. This includes
quantizing and all other errors.
Power Supply Rejection is the ability of an AOe to maintain accuracy as
the power supply voltage varies. The power supply and VREF(+) are varied
together and the change in accuracy is measured with respect to
full·scale.
Input Current is the time average current into or out of the chopper~
stabilized comparator. This current varies directly with clock frequency
and has little temperature dependence.
This is the time required for the output of the analog multiplexer to settle
within ±% LSB of the selected analog input signal.
MOSTEI(.
INDUSTRIAL PRODUCTS
ILP-Compatible AID Converter
MK5168(N)-1
FEATURES
PIN CONNECTIONS
Figure 1
o Complete system in 16-pin package operates standalone or JLP-driven
o
Optional Clocks - external signal or internal oscillator
o
Easy microprocessor interface
o
Bus-compatible, 3-state data outputs
o
Single 5 volt supply
o
low power - 1.5 mW typical
o s
Vcc __ 1
START __2
BUSV ... 3
ANALOG IN __4
CS __ 5
CLK_6
vREF(+) ___7
± Y2 lSB total unadjusted error
o
No full-scale or zero adjust required
o
Guaranteed monotonicity
o
No missing codes
GNO-8
16 __ 07 (MSB)
15-+-06
14 __ 05
13-+-04
12-+-03
11-+-02
10--01.
9--00 (LSB)
DESCRIPTION
The MK5168 is an 8-bit, JLP-compatible AID Converter
using the successive-approximations technique. CMOS
construction provides low-power operation and the 16-pin
package saves valuable board space, keeping system costs
low.
The MK5168 AID Converter is designed to interlace with
microprocessors or operate as a stand-alone subsystem.
The AID converter consists of 256 series resistors with an
analog switch array, a chopper-stabilized comparator, and a
successive approximation register. The series resistor
approach guarantees monotonicity and no missing codes.
The need for external zero and full-scale adjustments has
been eliminated and an absolute accuracy of :S 1 lSB,
including quantizing error, is provided.
All digital inputs are CMOS compatible. The data outputs
DO to 07 are 3-state latches providing true bus-driving
capability (250 ns from CS to a valid logic level with 56 pF
load). A START signal starts the conversion process and,
upon completion, BUSY is driven to logic O. Continuous
conversion is possible by tying the START pin to the BUSY
pin. The ClK pin may be connected to an external signal or
tied to ground to enable the on-chip oscillator.
The MK5168 features high accuracy, minimal temperature
dependence, and excellent long-term accuracy and
repeatability, characteristics which make this device ideally
suited to machine and industrial controls. A block diagram
of a microprocessor control system using the MK5168 is
shown in Figure 3.
FUNCTIONAL DESCRIPTION (Refer to Figure 2 for Block
Diagram)
Vcc' Pin 1
Vee must be connected to +5 Vdc ±5%.
START, Pin 2
The AID Converter's successive approximation register
(SAR) is reset by the falling edge of the STAAT pulse.
pulse. A
Conversion begins on the rising edge ofthe
conversion in progress will be interrupted if a new S'i'AR'i'
pulse is received and a new conversion will begin.
VII-33
smr
MK5168 BLOCK DIAGRAM
Figure 2
Si'A'RT
CLK
16
?2
t 1
I
CONTROL
AND
TIMING
~
ANALOG
IN
4
COMPARATOR
9
l
,
..
256R
RESISTOR
LADDER
10
~
11 -
-V
... ~
3-STATE
OUTPUT
LATCH!
BUFFER
VCC
4
GND
r
16
~5
CS
TYPICAL MICROPROCESSOR CONTROL SYSTEM
DISPLAY
f--+
SENSOR
r-~
V
FILTER
.1
\
1''_-"_11_'
1'_"_'
SAMPLE \ ...
AND
HOLD
J,
r
MK5168
A!D
CONVERTER
MP
A.
I
~
CONTROLLER
DAC
,
1
etc;.
4~
8-81T
0 UTPUT
15
Figure 3
PHYSICAL
VARIABLE
TEMPERATURE
PRESSURE
WEIGHT
FLOW
LIGHT
HUMIDITY
pH
....
13
SWITCH
ARRAY
67
8
12
14 -
f
1
BUSY
SAR
V
f----
3
..
VII-34
-"
...1
BUSY. Pin 3
RESISTOR LADDER AND SWITCH ARRAY
Figure 4
The BUSY output goes low when the conversion process
has been completed. The falling edge of the BUSY output
indicates a valid digital output. Continuous conversion can
be accomplished by tying the BUSY output to the START
input.lfthe AID Convener is used in this mode, an external
START conversion pulse should be applied after power up.
BUSY will go high within two clock periods after the positive
edge of the START pulse.
CONTROLS FROM SAR
,...------"--.
TO
COMPARATOR
INPUT
ANALOG IN. Pin 4
250R:
~--+.
The ANALOG INPUT accepts an analog signal from 0 V to
VCC·
The comparator is the most imponant section of the AID
Converter because this section determines the ultimate
accuracy of the entire convener. It is the dc drift of the
comparator which determines the repeatability of the
device. A chopper-stabilized comparator was chosen
because it best satisfies all the convener requirements.
The chopper-stabilized comparator convens the dc input
signal into an ac signal. This signal is amplified by a highgain ac amplifier and the dc level is restored. This technique
limits the drift component of the comparator because the
drift is a dc component which is not passed by the ac
amplifier.
Since drift is vinually eliminated, the entire AID Convener
is insensitive to temperature and exhibits little long-term
drift and input offset error.
CS. Pin 5
The CHIP SELECT (CS) allows the convener to be connected
to an 8-bit data bus. A high level applied to this input causes
the digital outputstogoto a high impedance state anda low
level applied causes the digital outputs to go to valid logic
levels.
GNO
This approach was chosen because of its inherent
monotonicity. A non-monotonic transfer characteristic can
cause oscillations within a closed-loop feedback system.
The top and bottom resistors of the ladder network in Figure
4 are not the same value as the rest of the resistors in the
ladder. They are chosen so that the output characteristic
will be symmetrical about the full-scale and zero points. The
first output transition occurs when the analog signal
reaches + Y2 lSB and succeeding transitions occur every 1
lSB until the output reaches full-scale.
GND. PinS
CLK. Pin 6
All inputs and outputs are referenced to GROUND (GND),
which is defined as 0 V and 0 logic level.
The CLOCK input (elK) will accept an external clock input
from 100kHz to 1.2 MHz. For an external clock signal to be
recognized by the MK5168, the signal must have a duty
cycle from 20% to 80%.
DIGITAL OUTPUT. Pins 9-16
DO-D7
If ClK is grounded, the conversion process will be controlled
by an on-chip oscillator, resulting in a typical conversion
time of 150 IJ.s.
V REF (+). Pin 7
These pins supply the digital output code which
corresponds to the analog input voltage. DO is the least
significant bit (lSB) and D7 is the most significant bit (MSB).
This output is stored in a TTL-compatible, 3-state output
latch which can drive a 56 pF bus from high impedance to
either logic state in 250 ns. Each pin can drive one standard
TTL load directly without a pull-up resistor.
This input supplies the voltage reference for the AID
Convener. Internal voltage references are derived from
VREF(+) and GND by a 256 resistor ladder network, as
shown in Figure 4. V REF(+) may be tied to Vee or to a higher
precision 5 V source for greater noise immunity.
VII-35
ABSOLUTE MAXIMUM RATINGS* (Note 11
Absolute Maximum Vee ............................................................................ 6.5 V
Operating Temperature Range ................................................................ _40° to +85°e
Storage Temperature Range ................................................................. -65° to +150 0 e
Power Dissipation at 25°C Ambient ........................................................ . . . . . . .. 500 mW
Voltage at any pin except Digital Inputs .................................................... -0.3 to Vee + 0.3 V
Voltage at Digital Inputs ...................................................................... -0.3 to +15 V
*Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
MK5168-1 (Note 11
SYMBOL
PARAMETER
CONDITIONS
MIN
TVP
MAX
Vce
Power Supply
Voltage
Measured at
Vee pin
4.75
5.00
5.25
V
VREF{+I
Voltage Across
Ladder
From VREF(+I
toGND
Vee-O.12
Vee+0 .12
V
UNITS NOTES
DC CHARACTERISTICS
MK5168-1
4.75 S Vee S 5.25 V, -40 STA S +85°C unless otherwise noted
SYMBOL
PARAMETER
CONDITIONS
VINHIGH
Logic Input
High Voltage
Vec = 5V
VINLOW
Logic Input
Low Voltage
Vee = 5V
VOUTHIGH
Logic Output
High Voltage
lOUT = -360 pA
VOUTLOW
Logic Output
Low Voltage
lOUT = 1.6 mA
IINHIGH
Logic Input
High Current
VIN = 15V
IINLOW
Logic Input
Low Current
VIN = OV
ICC
Supply Current
elk Freq=500 kHz
Clk Freq=64O kHz
ILEAK
High Impedance
Output Current
VOUT= VCC
VOUT = OV
VII-36
MIN
TVP
MAX
3.5
V
1.5
Vee -0.4
V
V
0.5
1.0
V
pA
pA
-1.0
300
-3
UNITS NOTES
1000
1300
pA
pA
3
pA
pA
DC CHARACTERISTICS
MK5168-1 -40:S; TA:S; +85°C.
SYMBOL
PARAMETER
CONDITIONS
RpS
Power SupplV
Rejection
4.75 :s; VCC :s; 5.25
VREF(+) = VCC
ICOMPIN
Comparator Input
Current
During Conversion
fc = 640 kHz
RLADDER
Ladder Resistance
From VREF(+) to
GND
.MIN
TYP
MAX
UNITS NOTES
0.05
0.15
%IV
9
-2
±O.5
2
pA
10
3.3
7
kG
CONVERTER SECTION
Vee =VREF(+) =5 V
fc =640 kHz
MK5168-1 -4O:S; TA:S; + 85°C unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
Resolution
MAX
UNITS NOTES
8
Bits
Non-Linearity Error
±1A
±%
LSB
2,
Zero Error
±1A
±%
LSB
4
Full-Scale Error
±1A
±%
LSB
5
±1A
±1A
±3A
±%
LSB
LSB
6
6
±Y2
LSB
7
±11A
±1
LSB
LSB
8
8
Total Unadjusted
Error
TA = 25°C
Quantizing Error
Absolute Accuracy
TA = 25°C
VII-37
±3A
±3A
AC CHARACTERISTICS (Reference Figure 7)
MK5168-1 TA = 25°C. VCC = VREF (+) = 5 Vor 5.12 V
SYMBOL
PARAMETER
tSTART
START Pulse Width
tcso
Chip Select Time to Valid
Logic Levels On Digital
Outputs
CL =56 pF
CL =200 pF
125
300
250
ns
ns
tcso
Time to HI-Z
From CS = VCC
CL = 10 pF
RL = lOk!l
125
250
ns
Conversion Time
fc 640 kHz
fc = f'nternal Clock
fc = 1200 kHz
110
57
108
150
58
59
MS
MS
MS
100
640
1200
kHz
11
2
Clock
Periods
3
tc
CONDITIONS
MIN
TVP
MAX UNITS NOTES
200
=
106
ns
fc
External Clock Freq.
taUSY
BUSY Delay Time
CIN
Input Capacitance
At Logic Inputs
10
15
pF
COUT
Output
Capacitance
At Digital
Outputs CS=VCC
5
7.5
pF
0
VII-38
FULL-SCALE. QUANTIZING AND ZERO ERROR
NON-LINEARITY ERROR
FigureS
Figure 6
OUTPUT
COOE
OUTPUT
COOE
FULL-SCALE ENOPOINT
INFINITE RESOLUTION
PERFECT CONVERTER
111
-
_ _ INFINITE RESOLUTION
CONVERTER
110
101
100
011
010
001
ZERO ENOPOINT
V
~ ~-''---~--~----r---'----r--~---ANALOGIN
000
o
1
3
4
6
7
LSB
TIMING DIAGRAM
Figure 7
CLOCK
50%
50O/C
L~~~:1=:=========~5:0~
BUSY
1:50%
50%
./
tCSQ ---.j
---"-..-""'--'t'-B-U-Sy-=+1
j50%
l+-
r-
tcso
I
HIGHIMPED_A_N~C~E_ _41 \~______________~~'1F-9~0_o/c_O~V_A~L~ID~~~9_0_o/c_o___
OUTPUTS
10%
10%
NOTES:
1. All voltages are measured with respect to GND.
2. Non-linearity error is the maximum deviation from a straight line through the
end-points of the AID transfer characteristic. (Figure 6)
3. When BUSY is tied to
BUSY delay is 1 clock period.
4. Zero Error is the difference between the actual input voltage and the design input
voltage which produces a zero output code. (Figure 5)
5. Full-Scale Error is the difference between the actual input voltage and the design
input voltage which produces a full-scale output code. (Figure 5)
6. Total Unadjusted Error is the true measure of accuracy the converter can provide
less any quantizing effects.
7. Quantizing Error is the ±% LSB uncertainty caused by the converter's finite
resolution. (Figure 5)
STARr,
8.
Absolute Accuracy is the difference between the actual input voltage and the
full-scale weighted equivalent of the binary output code. This includes quantizing
and all other errors.
9. Power Supply Rejection is the ability of anADeto maintain acc:u"'cy,.sthe lpo.var
supply voltage varies. The power supply and V REF(+) are varied together and
change in accuracy is measured with respect to full-scale.
10. Comparator Input Current is the time average current into or out of the chopper
stabilized comparator. This current varies directly with clock frequency and has
little temperature dependence.
11. A minimum duty cycle of 20% is required at the clock input.
VII-39
VII-40
MOSTEl(8
8-BIT AID CONVERTER/16-CHANNEL ANALOG MULTIPLEXER
MK50816(N/P)
The pin configuration of the MK50816 is shown in
Figure 1 below:
FEATURES
o Single 5 Volt Supply (± 5%)
PIN CONNECTIONS
o Low Power Dissipation - 6.825mW(max) at 640kHz
o Total Unadjusted Error
o Linerarity Error
Figure 1
< ± '12 LSB
< ± '12 LSB
•
40-+-IN2
o No Missing Codes
39 ____ INl
o Guaranteed Monotonicity
lB-4-INO
37 . - ~~~~~~~N
o No Zero Adjust Required
36...-ADD A
o No Full-Scale Adjust Required
35~ADDB
o 1081's Conversion Time (Typically)
34-+-ADD C
o Easy Microprocessor Interface
334-ADDO
o Latched TTL Compatible Three-State Output with
True Bus-Driving Capability
MK50816
31
~D7
o Expandable 16-channel Analog Multiplexer
30 --..06
o Latched Address Input
29 --.05
28 --+-04
o Fixed Reference or Ratiometric Conversion
27 - . 0 3
o Continuous or Controlled Conversion
COMMON4-15
o On-Chip or External Clock
VCC-"17
o On-Chip Chopper-Stabilized Comparator
o Low Reference-Voltage Current Drain
COMPARAT~:-"18
22....-CLOCK
DESCRIPTION
The MK50816 is a monolithic CMOS device with an 8bit successive approximation AID converter, a 16channel analog multiplexer and microprocessorcompatible control logic. The 16-channel multiplexer
can directly access anyone of 16 single-ended analog
channels and provides logic for additional channel
expansion. The 8-bit AID converter consists of 256
seri~~ resistors with an analog switch array, a chopperstabilized comparator and a successive approximation
register. The series resistor approach guarantees
monotonicity and no missing codes as well as allowing
both ratiometric and fixed-reference measurements.
The need for zero and full-scale adjustments has been
eliminated and an absolute accuracy of 0::;; 1 LSB
including quantizing error, is provided.
'
All digital outputs are TTL-compatible, all digital inputs
are TTL-compatible with a pull-up resistor, and all
digital inputs and outputs are CMOS-compatible; th
makes it easy to interface with most microprocessors.
The output latch is three-state and provides true busdriving capability (300ns from Three-State Control to Q
Logic State with 200pF load). A Start Convert signal
initiates the conversion process, and, upon completion,
an End Of Conversion signal is generated. Continuous
conversion is possible by tying the Start-Convert pin to
the End-of-Conversion pin. The clock pin may be
connected to an external oscillator or tied to ground to
enable an on-chip oscillator.
VII-41
The'MK50816 features low power, high accuracy,
minirnal temperature dependence, and excellent longterm accuracy and repeatability. These characteristics
make this device. ideally suited to machine and
industrial controls.
MK50816 BLOCK DIAGRAM
Figure 2
COMPAR~~ORo-
COMMON
A block diagram of a microprocessor control system
using the MK50816 is shown in Figure 3.
__________- ,
0----------,
START CLOCK
I~~~~~~--------_oENDOF
CONVERSION
16 ANALOG
INPUTS
,-----yi
THREE·
STATE
OUTPUT
LATCH/
BUFFER
l
B.BIT
OUTPUT
[[
Vee GND REF(+)
REFI-J THREE·STATE
CONTROL
TYPICAL MICROPROCESSOR CONTROL SYSTEM
Figure 3
DISPLAY
-
-,
MK50816
PHYSICAL
VARIABLE
TEMPERATURE
PRESSURE
WEIGHT
FLOW
LIGHT
HUMIDITY
FIL TER
pH
etc.
MUX
j.tP
I
"""
CHANNELS
{
CONTROLLER
PWR
AMPL
DAC
VII-42
AID
FUNCTIONAL DESCRIPTION (Refer To Figure 2 for
a Block Diagram)
ADDRESS, Pins 33-36
The address decoder allows the 16-input analog
multiplexer to select anyone of 16 single-ended analog
input channels. Table 1 shows the required address and
expansion control inputs to select any analog input
channel.
CLOCK INPUT, Pin 22
The Clock Input will accept an external clock input from
100kHz to 1.2MHz. A minimum duty cycle of 20% is
required for the Clock Input to detect the presence of an
external clock signal.
If the Clock pin is grounded, the conversion process will
be controlled by an on-chip oscillator.
ADDRESS LATCH ENABLE, Pin 32
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES [REF (+) and REF (-IJ, Pins 19 and 23
A positive transition applied to the Address Latch
Enable (ALE) input latches a 4-bit address into the
address decoder. ALE can be tied to Start with
parameter til being satisfied.
These inputs supply voltage references for the analogto-digital converter. Internal voltage references are
derived from REF (+) and REF (-) by a 256-R ladder
network, Figure 4.
COMMON OUTPUT, Pin 15
EXPANSION CONTROL, Pin 37
This approach was chosen because of its inherent
monotonicity, which is extremely important in closedloop feedback control systems. A non-monotonic
transfer characteristic can cause catastrophic
oscillations within a system.
Additional single-ended analog signals can be
multiplexed to the AID converter by holding the
Expansion Control low, disabling the multiplexer. These
additional externally-multiplexed signals are to be
connected to the Comparator Input and the device
ground. Additional signal conditioning such as sampleand-hold or instrumentation amplification can be added
between the analog signal and the Comparator Input.
The top and bottom resistors of the ladder network in
Figure 4 are not the same value as the rest of the
resistors in the ladder. They are chosen so that the
output characteristic will be symmetrical about its fullscale and zero points. The first output transition occurs
when the analog signal reaches + Y2 LSB and
succeeding transitions occur every 1 LSB until the
output reaches full scale.
ANALOG CHANNEL SELECTION
Table 1
RESISTOR LADDER AND SWITCH ARRAY
Figure 4
This is the output of the 16-channel analog multiplexer.
The maximum ON resistance is 3kfl.
CONTROLS FROM SAR
SELECTED
A-.!ALOG CHANNEL
ADDRESS LINE
EXPANSION
CONTROL
~
REF!+1
IN'
IN5
TO
COMPARATOR
INPUT
IN'
IN7
250R:
IN9
IN12
IN13
AUCh~nnelsOFF
REFl-I
VII-43
.----+..
ANALOG INPUTS. PINS 1- 12. 14. 38-40
start conversion pulse is received and a new conversion
will begin.
These inputs are mUltiplexing analog switches which
accept analog inputs from OV to Vcc.
END OF CONVERSION. Pin 13
COMPARATORINPU~~n18
The comparator is the most important section of the
AID converter because this section determines the
ultimate accuracy of the entire converter. It is the DC
drift of the comparator which determines the
repeatability of the device. A chopper-stabilized
comparator was chosen because it best satisfies all the
converter requirements.
The End Of Conversion (EOC) output goes high when
the conversion process has been completed. The
positive edge of the EOC output indicates a valid digital
output. Continuous conversion can be accomplished by
tying the EOC output to the Start input. If the AID
converter is used in this mode, an external start
conversion pulse should be applied after power up. End
of Conversion will go low within 2 clock periods after the
positive edge of Start.
The chopper-stabilized comparator converts the DC
input signal into an AC signal. This signal is amplified by
a high-gain AC amplifier and the DC level is restored.
This technique limits the drift component of the
comparator because the drift is a DC component which
is not passed by the AC amplifier.
8-BIT DIGITAL OUTPUT. Pins 24-31
These pins supply the digital output code which
corresponds to the analog input voltage. DO is the least
significant bit (LSB) and D7 is the most significant bit
(MSB). This output is stored in a TTL-compatible threestate output latch which can drive a 200pF bus from
high impedance to either logic state in 300ns. Each pin
can drive one standard TTL load.
Since drift is virtually eliminated, the entire AID
converter is extremely insensitive to temperature and
exhibits very little long-term drift and input offset error.
THREE-STATE CONTROL. Pin 21
START. Pin 16
The AID converter's successive approximation register
(SAR) is reset by the positive edge of the Start pulse.
Conversion begins on the falling ~dge ofthe Start pulse.
A conversion in progress will be interrupted if a new
The Three-State Control allows the converter to be
connected to an 8-bit data bus. A low level applied to
this input causes the digital output to go to a high
impedance state and a high level causes the output to go
to a Q logic state.
ABSOLUTE MAXIMUM RATINGS* (Note 1)
Absolute Maximum VCC ............................................................................ 6.5V
Operating Temperature Range ....................................................... MK50816 0° to + 70°C
MK50816-1 -40°C to +85°C
Storage Temperature Range .............................................................. -65°C to +150°C
Power Dissipation at 25°e ........................................................................ 500mW
Voltage at any Pin except Digital Inputs .................................................. -0.3 to Vec + 0.3V
Voltage at Digital Inputs ...................................................................... -0.3 to +15V
·Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VII-44
ELECTRICAL OPERATING CHARACTERISTICS
MK50816. MK50816-1 (Note 1)
SYM
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Power Supply Voltage
Measured at VCC Pin
4.75
5.00
5.25
V
0.512
5.12
5.25
V
VCC
VCC+0.1
V
VCC _ 0.1
2
VCC
2
VCC + 01
2
.
-0.1
0
VLADDER Voltage Across Ladder From REF(+) to REF (-)
VREF(+)
(
VREF(+)
VREF(-)
2
+)
VREF(-)
Voltage at Top of
Ladder
Measured at REF (+)
Voltage at Center of
Ladder
Measured at
RLADDER/2
Voltage at Bottom of
Ladder
Measured at REF(-)
NOTES
2
V
V
DC CHARACTERISTICS
All parameters are 100% tested at 25°C. Device parameters are characterized at low and high temperature limits to
assure conformance with the specification.
MK50816. MK50816-1
4.75:5 VCC:5 5.25V, -40:5 TA:5 +85°C unless otherwise noted
SYM
PARAMETER
CONDITIONS
MIN
VINHIGH
Logic Input
High Voltage
VCC
= 5V
3.5
VINLOW
Logic Input
Low Voltage
CC
= 5V
Logic Output
High Voltage
lOUT
= -360/LA
Logic Output
Low Voltage
lOUT
= 1.6mA
IINHIGH
Logic Input
High Current
IINLOW
Logic Input
Low Current
ICC
TYP
MAX
V
V
VCC - 0.4
0.4
V
1.0
/LA
-1.0
/LA
1000
1300
/LA
/LA
3
/LA
/LA
TYP
MAX
UNITS
NOTES
0.05
0.15
%/V
10
2
/LA
11
300
lOUT
Output Current
NOTES
V
1.5
Current
UNITS
-3
DC CHARACTERISTICS
MK50816-1 -40:5 TA:5 +85°C, MK50816 0°:5 TA:5 +70°C
SYM
PARAMETER
CONDITIONS
RpS
Power Supply
Rejection
4.75:5 VCC:5 5.25
VREF (+) = VCC
VREF(-) = GND
MIN
ICOMP IN Comparator Input
Current
fC = 640kHz
During Convs.
-2
±0.5
RLADDER Ladder Resistance
From REF(+) to REF (-)
3.8
7
VII-45
kCl
ANALOG MULTIPLEXER
MK50816, MK50816-1
_40° :5 TA :5 +85°C unless otherwise noted
SYM
PARAMETER
CONDITIONS
RON
Analog Multiplexer
ON Resistance
L:.RON
L:. ON Resistance
Between Any 2
Channels
TYP
MAX
UNITS
(Any Selected Channel)
TA = 25°C, RL = 10k
1.5
3
kn
(Any Selected Channel)
RL = 10k
75
10
MIN
IOFF(+)
OFF Channel
Leakage Current
VCC=5V, VIN=5V,
TA=25°C
IOFFH
OFF Channel
Leakage Current
VCC=5V, VIN=OV,
TA=25°C
-200
NOTES
n
200
-10
nA
nA
CONVERTER SECTION
VCC = VREF(+) = 5V, VREFH = GND, VIN = VCOMPARATOR IN,
fC = 640kHz
MK50816-1 -40:5 TA:5 +85°C unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
Resolution
MAX
UNITS
8
Bits
NOTES
Non-Linearity Error
±1.4
±%
LSB
3
Zero Error
±1.4
±Y2
LSB
5
Full-Scale Error
±1.4
±%
LSB
6
±1.4
±1.4
±%
±%
LSB
LSB
7
±Y2
LSB
8
±%
±%
±1
±11.4
LSB
LSB
9
TYP
MAX
UNITS
NOTES
8
Bits
Total Unadjusted Error
TA = 25°C
Quantizing Error
Absolute Accuracy
TA = 25°C
PARAMETER
CONDITIONS
MIN
Resolution
Non-Linearity Error
±%
±1
LSB
3
Zero Error
±1.4
±Y2
LSB
5
Full-Scale Error
±1.4
±%
LSB
6
Total Unadjusted Error
±%
±1
LSB
7.
±Y2
LSB
8
±1%
LSB
9
Quantizing Error
Absolute Accuracy
±1
VII-46
AC CHARACTERISTICS (Figure 7)
MK50B16. MK50B16-1 TA = 25°C. VCC
= VREF(+) = 5V or 5.12V. VREF(-) = GND
SYM
PARAMETER
tws
Start Pulse Width
200
ns
tWALE
Minimum ALE
Pulse Width
200
ns
ts
Address Set-Up Time
50
ns
tH
Address Hold Time
50
ns
tD
Analog MUX Delay
Time from ALE
Common Tied to
Comparator In.
RS + RON :S 5kO.
CL = 10pF
tH1. tHO
Three-State Control
to Q Logic State
CL
CL
t1 H. tOH
Three-State Control
to Hi-Z
tc
Conversion Time
fC
External Clock Freq
tEOC
EOC Delay Time
CIN
Input Capacitance
At Logic Inputs
At MUX Inputs
COUT
Three-State Output
Capacitance
At Three-State
Outputs
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
1
2.5
J.Ls
= 50pF
= 200pF
125
300
250
ns
ns
CL
RL
= 10pF.
= 10kO
125
250
ns
fC
fC
= 640kHz
= flNTERNAL CLOCK
106
10B
150
110
J.Ls
J.Ls
100
640
1200
kHz
13
2
Clock
Periods
4
10
5
15
7.5
pF
pF
5
7.5
pF
0
FULL SCALE. QUANTIZING AND ZERO ERROR
Figure 5
12
NON-LINEARITY ERROR
Figure 6
OUTPUT
COOE
INFINITE RESOLUTION
PERFECT CONVERTER
VIN
o
7
VII-47
TIMING DIAGRAM
Figure 7
CLOCK
ALE
,I
5~
\50.%
!
--''''WALE
- -+jSTABLE ADDRESS
ADDRESS
's .....
INPUT
MUX
OUTPUT
1
50%.
!
,
50.%
-+I-!-'H
--
,
STABLE
f+--S: 112
~
LSB
X
I - 'D ___
START
50%
~
50%
!
j--'WS"
j
50.%
THREE·STATE
CONTROL
J
.te
\50%
EOC
I---'EOC
OUTPUTS
(5OpF Loadl
50%
-3
!
'H1. 'HO=-'
l
i-
X90·.10%%
HIGH IMPEDANCE
Z
tHl==:
f1::='HO
~lH,tO H
X
10%
(
OUTPUTS
~
~
~
(20.0pF Loadl _ _ _ _ _ _ _ _ _ _
H_IG_H_IM_P_E_D_A_N_C_E_ _ _--l!!!-_ _ _ _ _ _ _ _ _ _ _ _ _2_4~~O'-4-V---J~
NOTES:
1. All voltages are measured with respect to GND.
2. The minimum value for VLADDER will give 2mV resolution. However. the
guaranteed accuracy is only that which is specified under "DC
Characteristics" .
3. Non-linearity error is the maximum deviation from a straight line through
the end points of the AID transfer characteristic, Figure 6.
4. When Eae is tied to START, EaC delay is 1 Clock period.
5. Zero Error is the difference between the actual input voltage and the
design input voltage which produces a zero output code, Figure D.
6. Full-Scale Error is the difference between the actual input voltage and the
design input voltage which produces 8 full-scale output I code, Figure 5.
7. T01B1 Unadjusted Error i. the true measure of accuracy the converter can
provide I... any quantizing eflacta.
Quantizing Error is the ± 1h LSB uncertainty caused by the converter's
finitejresoh.ition, Figure 5.
9. Absolute Accuracy is the difference between the actual input voltage and
the full·scale weighted equivalent of the binary output code. This includes
quantizing and all other errors.
10. Power Supply Rejection is the ability of an ACe to maintain accuracy as
the power supply voltage varies. The power supply and VREF(+) are varied
together and the change in accuracy is measured with respect to
full-scale.
11. Comparator Input Current is the time average current into or out of the
chopper·stabilized comparator. This current varies directly with clock
frequency and has little temperature dependence.
, 2. This is the time required for the output of the analog multiplexer to senle
within ± 'h LSB of the selected analog input signal.
13. A minimum duty cycle of 20% is required at the clock input.
8.
VII-48
1981 Z80 MICROCOMPUTER DATA BOOK
zao Military/
Hi-Rei
MILITARY/HI-RELIABILITY PRODUCTS
Table of Contents
I. Introduction ................................................••....................... VIII-3
II. Applications Guide ........................................••.•....................... VIII-5
III. MKB Military Products Listing .......................................................... VIII-6
IV. MKllndustrial Products Listing .............................•........................... VIII-7
V. MKB3880(P)-80/84 Data Sheet. ............................•••••.•.••................. VIII-9
VIII-1
VIII-2
Military and High Reliability Products
INTRODUCTION
Overview
Mostek's Military/Hi-Rei Products
Department serves the special needs of the
Defense, Aerospace and Commercial Hi-Rei
markets. The organization's principal objective
is to provide Mostek's state-of-the-art products
screened to MIL-STD 883, Methods 5004 and
5005.
Traditional Military IC manufacturers have
met stringent Military reliability requirements
at a cost of being several years behind the
state-of-the-art in commercial products.
Mostek Military brings the leading edge in
high reliability RAM, ROM, EPROM and
microprocessor devices to the Military systems
designer today. As MIL-M-3851 0 slash sheets
are announced, the Military Products
Department will qualify Mostek's products in
the JAN 38510 program. Mostek has already
received QPL listing of its 4116 dynamic RAM.
Designated JM-3851 01240, this device is one
of the most advanced MOS circuits to receive
QPL listing to date.
The Military Products Department is also
heavily engaged in the development of high
density leadless chip carrier packaging
technology. Several circuits are currently
offered in carriers with more planned for the
near future.
Product offerings are broken into two
categories'. Devices prefixed "MKB" are
screened to the full requirements of MIL-STD883 Class B. "MKI" (Industrial grade) prefixed
devices are screened to a subset of 883B
requirements and offer high reliability at
significantly reduced cost (see the following
sections for more detail concerning MKI
products).
specification (Mostek data sheet). Group B, C
and D inspections are performed periodically
per the requirements of Standard 883,
A data report documenting the results of
Group B, C and D testing through the present
is available at no charge.
SCD Program
Support Customer Documentation
The Military/Hi-Rei Products Department
has instituted a program to provide customers
with source'control drawings for nonstandard
parts requirements, patterned after DESC
"mini-spec" documents. This new
documentation from Mostek is an effort to
provide a reliable, detailed spec where no
DESC drawing or slash sheet exists. This
benefits the customer's procurement effort
and should help hasten the development of a
standard, government-approved, industry
accepted specification.
All new military devices will have a Mostek
SCD control document generated describing
them. They will be written around DDL 103
Guidelines for DESC Selected Item Drawings,
Their usage in programs should be restricted
to that period prior to the introduction of an
appropriate DESC prepared Selected Item
Drawing.
In sum, we feel the Mostek SCD offers
customers a ready-made source control
document customizable with his name and
part number and acceptable to his ultimate
customer - the U.S. Government.
SCD's AVAILABLE: MKB4118A
SCD's FORTHCOMING: MKB4801, 4802,
4164,2764
For more information contact:
Quality Conformance/Reliability
Mostek Corporation
Military Products Department
Mail Station 1100
1215 West Crosby Road
Carrollton, Texas 75006
Mostek has been providing MKB versions of
selected memory products since 1978. Quality
conformance inspections in accordance with
Method 5005 of Standard 883 are a central
part of MKB screening procedures. Group A
inspections are performed on a 100% basis to
the requirements contained in the detail
Telephone - (214) 323-6250/7718
TWX -910-860-5856
Telex - 730423
VIII-3
/
VIII-4
/
MILITARYIHI-REL PRODUCTS
Applications Guide
APPLICATION
TYPE OF SYSTEM
MOSTEK TYPE
Military/Aerospace
Ground
Airborne
Tactical Missile
Space
MKI/MKB
MKB/JAN
MKB/JAN
Class S Equiv.
Industrial
Process Control
Instrumentation
Telecom
MKI
Automotive
Engine Control
Instrumentation
MKI
Commercial
FAA
Airborne
MKB/MKI
Medical
Instrumentation
MKI
"MKB" SCREENING: 100% tested to the detail procedures of MIL-STD-883, Method 5004 Class Band
qualification and quality conformance procedures of Method 5005, Class B.
"MKI" SCREENING:
Tested to a cost-effective hi-rei subset of 883B including extended burn-in. AQL levels are
tightened.
VIII-5
MOSI'EI(.
MILITARYIHI-REL PRODUCTS
MKB Military Products Listing
OrganiProduct
Device
JAN DYNAMIC JM-38510124001 8EC
RAMs (4116)
JM-3851 0/24002 8EC
Standby
zation
Psckages
Temp.
Range
Access
Timesl Freq.
Active
Power
Power
16K x 1
16K x 1
P
P
-55°CI + 110°C
-55°CI + 11 O°C
200,ns
250 ns
462mw
462 mw
30mw
30mw
-55°CI + 110°C
150/2001250ns
462 mw
30mw
-55°C/+85°C
-55°C/ + 110°C
1501200 ns
2001250 ns
-
-
495 mw
60mw
250/300/350ns
70/90/120 ns
150mw
53mw
-
-
DYNAMIC
RAMs
MKB4116
MKB4164t
MKM4332
16K x 1
64Kx 1
32K x 1
E,F,J
E,P
D
STATIC RAMs
MKB4104
MKB2147Ht
MKB4167
MKB4118
MKB4oo1t
MKB4oo2t
4Kx 1
4K x 1
16K xl
1Kx8
1Kx 8
2Kx8
E,J
E,P
E,P
*E,P
*E,P
*E,P
-55°C/ + 125°C
-55°CI + 125°C
-55°CI + 125°C
-55°C/ + 125°C
-55°c/+125°C
-55°C/+125°C
120ns
1501200 ns
90/120 ns
90/120 ns
MKB36000
MKB37000t
8K x 8
8K x 8
P
*E,P
-55°c/+125°C
-55°C/ + 125°C
300 ns
MKB2716
MKB2764t
2K x 8
8K x8
*E,J
"E,T
-55°CI + 100°C
-55°C/ + 100°C
633 mw
165mw
450 ns
-
-
MKB3880
ZOO CPU
P
-55°C/ + 125°C
2,5/4,0 MHz
-
-
ROMs
EPROMs
MICROPROCESSORS
250/300 ns
390/450 ns
*NOTE: Bytewyde™ Products in leadless chip carrier (E package) will become available beginning 2nd half, 1981,
t1981 Introduction
VIII-6
500mw
400mw
-
-
220mw
-
55mw
-
MOSTEI(.
MILITARYIHI-REL PRODUCTS
M KI Industrial Products Listing
Product
Device
Organization
Packages
Temp.
Range
Access Time
Or Frequency
DYNAMIC RAMs
MKI4116
MKI4164t
16K x 1
'64Kx 1
J
J
-40°C/+85°C
-40°C/+85°C
15012001250 ns
150 ns
STATIC RAMs
MKI4118
MK14802t
1Kx8
2Kx8
J
J
-40°C/ +85°C
-40°C/+85°C
1501200 ns
70/90/120 ns
ROMs
MK137000t
8Kx8
J
-40°C/ +85°C
300 ns
EPROMs
MKI2716
MKI2764t
2K x 8
8Kx8
J
J
-40°C/+85°C
-40°C/+85°C
390/450 ns
450 ns
MICROPROCESSORS
MKI3880
Z80 CPU
P
-40°C/+85°C
2.5/4.0 MHz
t1981 Introduction
VIII-7
VIII-8
MOSTEI(.
zao CENTRAL PROCESSING UNIT
Processed to MIL-STD 883, Method 5004, Class B
MKB3880(P)-80/84
FEATURES
D Single 5-Volt supply and single-phase clock required
D Screened per MIL-STD-883, Method 5004 Class B
D Z80 CPU and Z80 A CPU
D Software compatible with 8080A CPU
D -55°C to 125°C temperature range
D Complete
D Two speeds
• 2.5 MHz
• 4.0 MHz
development and OEM system product
support
MKB3880)P)-80
MKB3880(P)-84
D Industrial MKI version available (-40°C to 85°C)
DESCRIPTION
The Mostek Z80 family of components is a significant
advancement in the state-of-art of microcomputers. These
components can be configured with any type of standard
semiconductor memory to generate computer systems with
an extremely wide range of capabilities. For example, as few
as two LSI circuits and three standard TIL MSI packages
can be combined to form a simple controller. With additional
memory and 1/0 devices, a computer can be constructed
with capabilities that only a minicomputer could deliver
previously. This wide range of computational power allows
standard modules to be constructed by a user that can
satisfy the requirements of an extremely wide range of
applications.
The CPU is the heart of the system. Its function is to obtain
instructions from the memory and perform the desired
operations. The memory is used to contain instructions and,
in most cases, data that is to be processed. For example, a
typical instruction sequence may be to read data from a
specific peripheral device, store it in a location in memory,
check the parity, and write it out to another peripheral
device. Note that the Mostek component set includes the
CPU and various general purpose 1/0 device controllers, as
well as a wide range of memory devices. Thus, all required
components can be connected together in a very simple
manner with virtually no other external logic. The user s
effort then becomes primarily one of the software
development. That is, the user can concentrate on
describing his problem and translating it into a series of
instructions that can be loaded into the microcomputer
memory. Mostek is dedicated to making this step of
software generation as simple as possible. A good example
of this is our assembly language in which a simple
mnemonic is used to represent every instruction that the
CPU can perform. This language is self-documenting in
such a way that from the mnemonic the user can
understand exactly what the instruction is doing without
constantly checking back to a complex cross listing.
zao-cpu BLOCK DIAGRAM
zao PIN CONFIGURATION
Figure 1
Figure 2
A,
A]
A,
SYSTEM
CONTROL
A5
A,
__3? ______ A)
~, RFSH
38
A8
ADDRESS
BU5
39____ A9
4~
ALU
'-_-~./
13
CPU AND
SYSTEM
!NSTRUCTION
DECODE
&
CPU
CONTROL
l80 CPU
MK83880(PI-80
MKB38liO(PI-84
A\O
~:~;
An
CONTROL
SIGNALS
rrr
DATA
8US
+-5V GND 'I'
VIII-9
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................................................................... -55°C to +125°C
Storage Temperature ....................................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground ...................................................... -0.3V to + 7V
Power Dissipation ................................................................................... 1 .5W
"'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage tathe device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC CHARACTERISTICS
(TA = -55°C to 125°C, Vee = 5 V ± 5% unless otherwise specified)
SYM
PARAMETER
MIN
MAX
UNIT
VILe
Clock Input Low Voltage
-0.3
0.8
V
V IHe
Clock Input High Voltage
V ec- 6
V ee +·3
V
V IL
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
All inputs except NMI
2.4
Vee
V
V1H(NMI)
Input High Voltage (NMI)
2.7
Vee
V
VOL
Output Low Voltage
0.4
V
IOL = 1.8mA
V OH
Output High Voltage
V
IOH
= -250 IlA
lee
Power Supply Current
200
mA
III
Input Leakage Current
10
IlA
V IN
= 0 to Vee
ILOH
Tri-State Output Leakage
Current in Float
10
IlA
V OUT
Tri-State Output Leakage
Current in Float
-10
IlA
VOUT = O.4V
Data Bus Leakage Current
In Input Mode
±10
IlA
O
MAX
UNIT
TEST CONDITIONS
Clock Capacitance
35
pF
Unmeasured Pins
CIN
Input Capacitance
5
pF
Returned to Ground
COUT
Output Capacitance
10
pF
VIII-10
AC CHARACTERISTICS
MKB3880(P)-80 Z80-CPU
(TA = -55°C to 125°C, VCC = +5V, ±5%, Unless Otherwise Noted)
SIGNAL
Ao-15
SYM
PARAMETER
MIN
MAX
UNIT
te
tw(H)
tw(l)
t,f
Clock
Clock
Clock
Clock
.4
180
180
[12]
(D)
2000
30
Msec
nsec
nsec
nsec
t DIAD )
t FIAD )
taem
Address Output Delay
Delay to Float
Address Stable Prior to MREO
(Memory Cycle)
Address Stable Prior to 10RO, RD or
WR (1/0 Cycle)
Address Stable From RD, WR, 10RO
or MREO
Address Stable From RD or WR
During Float
145
110
[1]
nsec
nsec
nsec
[2]
nsec
[3]
nsec
[4]
nsec
tae;
tea
tea!
t DID )
t FID )
tSID)
0 0 _7
ts;j;ID)
t dem
tde;
ted!
tH
tDL;j;IMR)
MREO
tDHIMR)
tDH;j;IMR)
!wIMRL)
twIMRH)
tDLIIR)
tDL;j;(lR)
10RO
tDHIIR)
tDH;j;(lR)
tDLIRD)
RD
tDL;j;IRD)
tDHIRD)
tDH;j;IRD)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During Ml Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
MREO Delay From Falling Edge of
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
60
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
100
nsec
100
nsec
100
nsec
nsec
110
nsec
100
nsec
110
nsec
Rising Edge of Clock,
100
nsec
Falling Edge of Clock,
130
nsec
Rising Edge of Clock,
100
nsec
Falling Edge of Clock,
110
nsec
VIII-11
CL = 50pF
Except T3-Ml
CL = 50pF
CL = 50pF
nsec
nsec
[8]
[9]
90
10RO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
10RO Delay From Rising Edge of
Clock, 10RO High
10RO Delay From Falling Edge of
Clock, 10RO High
RD Delay From
RD Low
RD Delay From
RD Low
RD Delay From
RD High
RD Delay From
RD High
50
nsec
nsec
nsec
250
90
TEST CONDITION
CL = 50pF
CL = 50pF
AC CHARACTERISTICS (Cont.)
SIGNAL
SYM
. tOL(WR)
WR
toL(WR)
tw(WRI)
t Ol(Ml)
M1
tOH(Ml)
RFSH
tOl(RF)
tOH(RF)
PARAMETER
MIN
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRHigh
Pulse Width, WR Low
nsec
90
nsec
100
nsec
[10]
130
nsec
RFSH Delay From Rising Edge of Clock,
~Low
RFSH Delay From Rising Edge of Clock
RFSH High
180
nsec
150
nsec
HALT
to(HT)
HALT Delay Time From Falling Edge
of Clock
iN'f
ts(IT)
INT Setup Time to Rising Edge of Clock
NMI
tw(MiifC)
Pulse Width,
i30SRQ
ts(BQ)
BUSRO Setup Time to Rising Edge of
Clock
BUSAK
tOl(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
tF(C)
Delay to/from Float (MREO, IORO,
RD andWRI)
tmr
M1 Stable Prior to IORO (Interrupt Ack.)
Although static by design_ testing guarantees tw IH) of 200 ~sec maximum.
[2]
taci = tc -80
[3]
tea:::
[4]
teaf = tw (
SYM
PARAMETER
MIN
MAX
UNIT
te
t,JH)
Clock
Clock
Clock
Clock
.25
110
110
[12]
(D)
2000
30
!-,sec
nsec
nsec
nsec
110
90
[1]
nsec
nsec
nsec
[2]
nsec
[3)
nsec
[4)
nsec
~(L)
tr,f
to(AO)
tF(AO)
taem
Ao-15
tae;
tea
tea!
tOlD)
tF(O)
tS(O)
DO_7
ts;j;(O)
t dem
tde;
ted!
tH
tOL;j;(MR)
MREO
tOH(MR)
t OH4>(MR)
tw(MRL)
tw(MRH)
tOL(lR)
tOL¥(IR)
10RO
tOH;j;(IR)
tOH(lR)
tOL(RO)
RD
tOL¥(RO)
tOH(RO)
tOH¥(RO)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
Address Output Delay
Delay to Float
Address Stable Prior to MREO
(Memory Cycle)
Address Stable Prior to 10RO, RD or
WR (I/O Cycle)
Address Stable From RD, WR. 10RO
or MREO
Address Stable From RD or WR
During Float
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During M1 Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
MREO Delay From Falling Edge of
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
50
nsec
nsec
nsec
60
nsec
[5)
nsec
[6)
[7)
0
nsec
nsec
nsec
170
90
20
85
nsec
85
nsec
85
nsec
[8)
[9)
CL = 50pF
Except T3-M1
CL = 50pF
CL = 50pF
nsec
nsec
10RO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
10RO Delay From Rising Edge of
Clock, 10RO High
10RO Delay From Falling Edge of
Clock, 10RO High
75
nsec
85
nsec
85
nsec
85
nsec
RD Delay
RD Low
RD Delay
RD Low
RD Delay
RD High
RD Delay
RD High
From Rising Edge of Clock,
85
nsec
From Falling Edge of Clock,
95
nsec
From Rising Edge of Clock,
85
nsec
From Falling Edge of Clock,
85
nsec
VIII-13
TEST CONDITION
CL = 50pF
CL = 50pF
AC CHARACTERISTICS (Cont.)
SIGNAL
SYM
PARAMETER
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WR High
Pulse Width, WR Low
tDL(WR)
WR
tDLij;(WR)
tDH(WR)
tw(WRL)
tDL(Ml)
Ml
tDH(Ml)
RFSH
MIN
tDL(RF)
tDH(RF)
MAX
UNIT
65
nsec
80
nsec
80
nsec
[10]
Ml Delay From Rising Edge of Clock
Ml Low
Ml Delay From Rising Edge of Clock,
Ml High
100
nsec
100
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
130
nsec
120
nsec
CL = 50pF
CL = 50pF
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
tD(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(IT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw(NML)
Pulse Width, NMI Low
80
nsec
BUSRQ
ts(BO)
BUSRQ Setup Time to Rising Edge of
Clock
50
nsec
BUSAK
tDL(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
300
tF(C)
Delay to/From Float (MREO, IORO,
RD and WR)
tmr
Ml Stable Prior to IORO (Interrupt Ack.)
The RESET signal must be active for a minimum of 3 clock cycles
Output Delay vs. Load Capacitance
4.
Add 10 nsec delay for e~ch 50pF increase in load up to a maximum of 200pF for
the data bus and 1OOpF for address and control hnes
Although static by design, testing guarantees tw (!:PH) of 200 Msec maximum.
taci = tc -70
tea = ~ (4)L) + tr -50
[4)
teaf = tw (4)L) + tr -45
[5]
[6]
[7]
tdem = te -1 70
t dei = tw (4)L) + tr -170
tedf = tw (4)L) + tr -70
[8]
tw (MRL)
100
nsec
nsec
60
80
[9]
111)
nsec
nsec.
tw (MRH) = tw (4)H) + t f -40
[10) tw (WR) = te -30
it -65
LOAD CIRCUIT FOR OUTPUT
Vee
Figure 4
it -65
[2]
[3]
nsec
CL = 50pF
[12] te = 6 w (4)H) + twl4>L) + tr + t f
TAo 125"CVCCo5V±5%
taem = tw (4)H) +
100
[11] tmr = 2te + tw (4)H) +
2.
3
[1]
nsec
CL = 50pF
RESET Setup Time to Rising Edge of
Clock
active
nsec
70
ts(RS)
NOTES
1 Data should be enabled onto the CPU data bus when R5 IS active. During
interrupt acknowledge data should be enabled when M1 and IORO are both
CL = 50pF
nsec
WAIT
tDH(BA)
TEST CONDITION
TEST POINT
= te -30
VIII-14
R,.2.1Kn
A.C. TIMING DIAGRAM
Timing measurements are made at the following voltages, unless otherwise specified.
CLOCK
OUTPUT
INPUT
FLOAT
"'"
VC~-·6
2.4V
2.4V
t:,V
"0"
.8V
.8V
.8V
±O.5V
AO_AI5
A O- 15
IN
DO_7 {
OUT
'",
tOllMIl
t~dl
-- -----~
__
_.r--
t=-i~_
--------...,,~,------
'0 (HTI
VIII-15
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