1981_NEC_Microcomputer_Catalog 1981 NEC Microcomputer Catalog

User Manual: 1981_NEC_Microcomputer_Catalog

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1981 CATALOG

NEe Microcomputers, Inc.

NEe

© 1981 NEe Microcomputers, Inc.
The information presented in this document is believed to be aCCUrate and reliable.
The information is subject to change without notice.

Printed in USA

ttiEC

CONTENTS
FUNCTIONAL AND NUMERICAL INDEXES
ROM ORDERING PROCEDURE

MEMORY SELECTION GUIDE
AND ALTERNATE SOURCE GUIDE

RANDOM ACCESS MEMORIES

READ ONLY MEMORIES

MICROCOMPUTER SELECTION GUIDE
AND ALTERNATE SOURCE GUIDE

SINGLE CHIP
4-BIT MICROCOMPUTERS

SINGLE CHIP
8-BIT MICROCOMPUTERS

M ICROPROC ESSORS

PERIPHERALS

BOARD PRODUCTS

. NEC Microcomputers, Inc.
1981
Product Catalog

REFERENCE SECTION
Quality Assurance Chart
Representatives & Distributors

II

II
II
II
II
II
II
II
II

1m
III

NOTES

2

NEe

NEe Microcomputers, Inc.
FUNCTIONAL INDEX
RANDOM ACCESS MEMORIES
Selection Guide. . . . .
8
Alternate Source Guide
9
Dynamic NMOS RAMs
!,PD411 .. .
11
!,PD411A
19
!,PD416 . . . .
27
!,PD2118 .
37
!,PD4164
47
Static NMOS RAMs
!,PD4104 . . . . .
53
!,PD2114l . . . . . . .
59
!,PD2147
65
!,PD2149 . . . . . . . .
71
!,PD421 . . . . . . . . . . . .
77
!,PD2167 .
81
Static CMOS RAMs
!,PD5101l
83
!'PD444/6514. . . . . . . . . .. 89
!,PD445l . . . . . . . . . . .
93
!,PD446 . . . . . . . . . . . . .. 99
!,PD447 . . . . .
105

!,COM-75
!,PD7502 . . . . . . . . . . . . .
!,PD 7503 . . . . . . . . . . . . .
!,PD7507 . . . . . . . . . . . . .
!,PD7520 . . . . . . . . . . . . .
Evaluation Chip
!,PD7500 '" . . . . . . . ..
SINGLE CHIP
8-BIT MICROCOMPUTERS
Selection Guide. . . . . . . .
Alternate Source Guide . . . . . . .
ROM Ordering Procedure . . . . . .
!,PD7800 . . . . . . . . . . . . .
!,PD7801 . . . . . . . . . . . . .
!,PD7802 . . . . . . . . . . . . .
!,PD8021 . . . . . . . . . . . . .
!' PD8022 . . . . . . . . . . . . .
!,PD8041 . . . . . . . . . . . . .
!,PD8041A/8741A . . . . . . . .
!'PD8048/8748/8035L . . . . .
!,PD80C48/80C35 . . . . . . . .
!'PD8049/8039L . . . . . . . . .

155
157
111
239
251
277
303
309
315
323
333
345
357

PROGRAMMABLE READ
ONLY MEMORIES
Selection Guide. . . . . . .

MICROPROCESSORS
Selection Guide . . . . . . . . . . . .
Alternate Source Guide . . . . . _ .
!,PD780 . . . . . . . . . . . . . .
!,PD8080AF . . . . . . . . . . .
!,PD8085A . . . . . . . . . . . .
!,PD8086 . . . . . . . . . . . _ .

155
157
367
383
397
411

PERIPHERALS
Selection Guide . . . . . . . . . . . .
Alternate Source Guide . . . . . . .
!,PD765 . . . . . . . . . . . .
!,PD781 . . . . . . . . . . . . . .
!,PD782 . . . . . . . . . . . . . .
!,PD3301 . . . . . . . . . . . • .
!,PD7001 • . . . . . . . . . . • .
!,PD7002 . . . . . . . . . . . . . .
!,PD7201 . . . . . . . . . . . . .
!,PD7210 . . . . . . . . . . . . .
!,PD7225 . . . . . . . . . . . . .
!,PD7227 . . . . . . . . . . . . .
!,PD7720 . . . . . . . . . . . . .
!,PD8155/8156 . . . . . . '. . . .
!,PB8212 . . . . . . . . . . . . .
!,PB8214 '. . . . . . . . . . .
!'PB8216/8226 . . . . . . . .
!,PB8224 . . . . . . . . . . . . .
!,PB8228 . . . . . . . . . . . . .
!,PD8243 . . . . . . . • . . .
!'PD8251/8251A . . . . . . .
!,PD8253/8253-5 . . . . . . .
!'PD8255/8255A-5 . . . . . .
!'PD8257/8257-5 . . . . . . .
!'PD8259/8259-5 . . . . . . .
!,PD8259A . . . . . . . . . . . .
!,PD8279-5 . . . . . . . . . . . .
!'PB8282/8283 . . . . . . . . . .
!,PB82B4 . . . . . . . . . . . . .
!'PB8286/8287 . . . . . . . . . .
!,PB8288 . . . . . • . . . . . . .
!'PD8355/8755A . . . . . . . . .

155
157
423
443
455
467
475
479
483
495
505
517
519
537
545
553
561
565
571
577
583
601
609
617
625
641
659
669
673
681
687
695

BOARD PRODUCTS
BP-0200 . . . . . . . . . . . . . .
BP-0220 . . . . . . . . . . . . . .
BP-0575 . . . . • . • . . . . . . .
BP-2190 . . . . . . . . . . . . . .

703
705
707
709

Alternate Source Guide . .

ROM Ordering Procedure .
Mask Programmable ROMs
!,PD2308A . . . . . . . . . . .
!,PD2316E . . . . . . . . . . . .
!,PD2332A/8 . . . . . . . . .
!,PD2364 . . . . . . . . . . .
!'PD23128..........
Field Programmable ROMs
(Bipolar)
!'PD406/426
!'PD409/429 . . . . . . . . . . .
(U.V. Erasable)
!,PD2716 . . . . . . . . . . . . .
!'~V~ . . . . . . . . . . . .
Bipolar Field Programmable
logic Arrays
!,PD450 . . . . . . . . . . . . . .
SINGLE CHIP
4-BIT MICROCOMPUTERS
Selection Guide. . . . . .

8
9
111
113
117
121
125
129

133
137
143

1G
151

155

Microcomputer Alternate

Source Guide . . . . . . .
ROM Ordering Procedure
!,COM-4 . .
. ..........
!,COM-43 . . . . . . . . . . . . . . .
!,PD546 . . . . . . . . . . . . . .
!,PD553 . . . . . . . . . . . . . .
!,PD557l . . . . . . . . . . . . .
!,PD650 . . . . . . . . . . . . . .
~OMM

157
1.11
159
169
173
175
177
179

...............

1~

!,PD547 . . . . . . . . . . . . . .
!,PD5471 . . . . . . . . . . . . .
!,PD552 . . . . . . . . . . . . . .
!,PD651 . . . . . . . . . . . . . .
!,COM-45 . . . . . . . . . . . . .
!,PD550 . . . . . . . . . . . . . .
!,PD550L . . . . . . . . . . . . .
!,PD554 . . . . . . . . . . . .
!,PD554l .. . . . . . . . . . . .
!,PD652 . . . . . . . .
Evaluation Chip
!,PD556 . . . . . . . . . . . . . .

185
187
189
191
193
195
197
199
201
203
205

209
223
225
227
237

3

NOTES

4

NEe

NEe Microcomputers, Inc.
NUMERICAL INDEX
PRODUCT

PAGE

ILCOM4 . . . . . . . . . . . . . . . .
ILCOM43 . . . . . . . . . . . . . . .
ILCOM44 . . . . . . . . . . . . . . .
ILCOM45 . . . . . . . . . . . . . . .
ILPB406/426 . . . . . . . . . . . . .
ILPB409/429 . . . . . . . . . . . . .
ILPD411 . . . . . . . . . . . . . . . .
ILPD411A . . . . . . . . . . . . . . .
, ILPD416 . . . . . . . . . . . . . .. ,
ILPD421 . . . . . . . . . . . . . . . .
ILPD444/6514 . . . . . . . . . . . . ,
ILPD445L . . . . . . . . . . . . . ..
ILPD446 . . . . . . . . . . . . . . ..
ILPD447 . . . . . . . . . . . . . . . .
ILPB450 . . . . . . . . . . . . . . . .
ILPD546 . . . . . . . . . . . . . . . .
ILPD547 . . . . . . . . . . . . . . . .
ILPD547L . . . . . . . . . . . . . . .
ILPD550 . . . . . . . . . . . . . . . .
ILPD550L . . . . . . . . . . . . . . .
ILPD552 . . . . . . . . . . . . . . . .
ILPD553 . . . . . . . . . . . . . . . .
ILPD554 . . . . . . . . . . . . . . . .
ILPD554L . . . . . . . . . . . . . . .
ILPD556 . . . . . . . . . . . . . . . .
ILPD557 L . . . . . . . . . . . . . . .
ILPD650 . . . . . . . . . . . . . . . .
ILPD651 . . . . . . . . . . . . . . . .
ILPD652 . . . . . . . . . . . . . . . .
ILPD765 . . . . . . . . . . . . . . . .
ILPD780 . . . . . . . . . . . . . . . .
ILPD781 . . . . . . . . . . . . . . . .
ILPD782 . . . . . . . . . . . . . . . .
ILPD2114L . . . . . . . . . . . . . .
ILPD2118 . . . . . . . . . . . . . . .
ILPD2147 . . . . . . . . . . . . . . .
ILPD2149 . . . . . . . . . . . . . . .
ILPD2167 . . . . . . . . . . . . . . .
ILPD2308A . . . . . . . . . . . . . .
ILPD2316E . . . . . . . . . . . . . .
ILPD2332A/B . . . . . . . . . . . . .
ILPD2364 . . . . . . . . . . . . . . .
ILPD2716 . . . . . . . . . . . . . . .
ILPD2732 . . . . . . . . . . . . . . .
ILPD3301 . . . . . . . . . . . . . . .
ILPD4104 . . . . . . . . . . . . . . .
ILPD4164 . . . . . . . . . . . . . . .
ILPD51 01 L . . . . . . . . . . . . . .
ILPD7001 . . . . . . . . . . . . . . .

159
169
181
193
133
137
11
19
27-77
89
93
99
105
151
173
185
187
195
197
189
175
199
201
205
177
179
191
203
423
367
443
455
59
37
65
71
81
113
117
121
125
143
149
467
53
47
83
475

PRODUCT

PAGE

ILPD7002 . . . . . . . . . . . . . . .
ILPD7201 . . . . . . . . . . . . . . .
pPD7210 . . . . . . . . . . . . . . .
pPD7225 . . . . . . . . . . . . . . .
pPD7227 . . . . . . . . . . . . . . .
ILPD7500 . . . . . . . . . . . . . . .
pPD7502 . . . . . . . . . . . . . . .
pPD7503 . . . . . . . . . . . . . . .
pPD7507 . . . . . . . . . . . . . . .
pPD7520 . . . . . . . . . . . . . . .
.uPD7720 . . . . . . . . . . . . . . .
pPD7800 . . . . . . . . . . . . . . .
ILPD7801 . . . . . . . . . . . . . . .
pPD7802 . . . . . . . . . . . . . . .
pPD8021 . . . . . . . . . . . . . . .
pPD8022 . . . . . . . . . . . . • . .
pPD8041 . . . . . . . . . . . . . . .
pPD8041 A/8741 A . . . . . . . . . .
pPD8048/8748/8035 L . . . . . . .
pPD80C48/80C35 . . . . . . . . . .
pPD8049/8039L . . . . . . . . . . .
pPD8080AF . . . . . . . . . . . . .
pPD8085A . . . . . . . . . . . . . .
pPD8086 . . . . . . . . . . . . . . .
pPD8155/8156 . . . . . . . . . . . .
pPB8212 . . . . . . . . . . . . . . .
pPB8214 . . . . . . . . . . . . . . .
pPB8216/8226 . . . . . . . . . . . .
pPB8224 . . . . . . . . . . . . . . .
pPB8228 . . . . . . . . . . . . . . .
pPD8243 . . . . . . . . . . . . . . .
pPD8251 /8251 A . . . . . . . . . . .
pPD8253/8253-5 . . . . . . . . . . .
pPD8255/8255A-5 . . . . . . . . . .
pPD8257/8257-5 . . . . . . . . . . .
pPD8259/8259-5 . . . . . . . . . . .
pPD8259A . . . . . . . . . . . . . .
pPD8279·5 . . . . . . . . . . . . . .
pPB8282/8283 . . . . . . . . . . . .
pPB8284 . . . . . . . . . . . . . . .
pPB8286/8287 . . . . . . . . . . . •
pPB8288 . . . . . . . . . . . . . . .
pPD8355/8755A . . . . . . . . . . .
pPD23128 . . . . . . . . . . . . . . .
BP'()200 . . . . . . . . . . . . . . . .
BP-0220 . . . . . . . . . . . . . . . .
BP-0575 . . . . . . . . . . . . . . . .
BP-2190 . . . . . . . . . . . . . . . .

479
483
495
505
517
237
209
223
225
227
519
239
251
277
303
309
315
323
333
345
357
383
397
411
537
545
553
561
565
571
577
583
601
609
617
625
641
659
669
673
681
687
695
129
703
705
707
709

5

NOTES

6

MEMORIESfi

7

NEe

NEe Microcomputers, Inc.
MEMORY SELECTION GUIDE
DEVICE
DYNAMIC RANDOM ACCESS MEMORIES
pPD41 1
pPD411·4
,uPD411A

4K xl TS
4K xl TS
4K xl TS

NMOS
NMOS
NMOS

pPD416
pPD2118

16K x 1 TS
16K xl TS
64K xl TS

NMOS
NMOS

200 ns
120 ns
100 ns

NMOS.

150 ns

,uPD4164

150 ns
135 ns

380
320
400
320
235
270

ns
ns
ns
ns
ns
ns

+12,+5,-5
+15,+5,-5
+12,-+:5,-5
+12,+5,-5

D
D
C
C/D

22
22
22
16

+5
+5

C/D
C/D

16
16

450 ns
200 ns

+5
+5

C

22

C

450 ns
120 ns

+5
+5
+5
+5

C
C/D
C/D

18
20
24
24

STA TIC RANDOM ACCESS MEMORIES
pPD5101 L
pPD444/6514
,uPD445L
pPD446
pPD447
pPD4104
pPD2114L
,uPD2147
pPD2149
pPD421
pPD2167

256 x 4 TS
lK x 4 TS

CMOS
CMOS

lK x 4 TS
2K x 8 TS
2K x 8 TS

CMOS
CMOS
CMOS

4K x
lK x
4K x
1K x
lK x
16K x

NMOS
NMOS

1 TS
4 TS
1 TS
4 TS
8 TS
1 TS

NMOS
NMOS
NMOS
NMOS

450 ns
200 ns
450 ns
120 ns
120 ns

120 ns

200 ns
150 ns
45 ns
35 ns
150 ns
55 ns

310 ns
150 ns
45 ns
35 ns
150 ns
55 ns

+5
+5
+5
+5
+5

C/D
C/D
D
D
D
D

18
18
18
18
22
20

MASK PROGRAMMED READ ONL Y MEMORIES
pPD2308A
,uPD2316E
,uPD2316E· 1
pPD2332A/B
pPD2332A/B· 1
,uPD2364
,uPD23128

1K x
2K x
2K x
4K x

8
8
8
8

TS
TS
TS
TS

NMOS
NMOS
NMOS
NMOS
NMOS

4K x 8 TS
8K x 8 TS
16Kx8TS

NMOS
NMOS

+5
+5

C
C
C
C

24
24
24
24
24
24
28

ns
ns
ns
ns

+5
+5
+5
+5

C/D
C/D
C/D
C/D

18
18
24
24

200 ns

200 ns

+5

D

48

450 ns
450 ns

450 ns

+5

450 ns

+5

D
D

24
24

450 ns
450 ns
350 ns
450 ns
350 ns
450 ns
250 ns

450
450
350
450

ns
ns
ns
ns

350 ns
450 ns
250 ns

+5
+5
+5
+5
+5

C/D
C
C

FIELD PROGRAMMABLE READ ONL Y MEMORIES
(Bipolar)
,uPB406
,uPB426
,uPB409

lK
1K
2K
,uPB429
2K
(Bipolar Logic Array)

,uPB450

x
x
x
x

4 OC
4 TS
8 OC
8 TS

9216 bit

BIPOLAR
BIPOLAR
BIPOLAR
BIPOLAR
BIPOLAR

50
50
50
50

ns
ns
ns
ns

50
50
50
50

(U.V. Erasable)
,uPD2716
,uPD2732

2K x 8 TS
4K x 8 TS

Notes: O.C. = Open Collector
C - Plastic Package
D TS -

8

Hermetic Package
3·State

NMOS
NMOS

NEe

NEe Microcomputers, Inc.
MEMORY ALTERNATE SOURCE GUIDE

I

MANUFACTURER

AMD

EM&M

FAIRCHILD

PART NUMBER,

DESCRIPTION

2716

2K x 8 EPROM

IlPD2716

27S33

lK x 4 PROM

IlPB426

8308
9016

lK x 8 ROM
16K x 1 DRAM

9060
9107

4K x 1 DRAM

9124

lK x 4 SRAM

IlPD2114L

9147

IlPD2147

9216

4K xl SRAM
2K x 8 ROM

AM91 L14

lK x 4 SRAM

IlPD444/IlPD6514

AM91 L24

lK x 4 SRAM

IlPD444/IlPD6514

2114

lK x 4 SRAM

IlPD2114L

Bl08

lK x B SRAM

IlPD421

93453

lK x 4 PROM

IlPB426

93511

2K x 8 PROM

IlPB429

F2114

lK x 4 SRAM

IlPD2114L

F2716

2K x 8 EPROM

IlPD2716

HARRIS

IlPD2114L

IlPD2316E

IlPD416

7122

lK x 4 PROM

IlPB426

7138

2K x 8 PROM

IlPB429

MBM2147

4K xl SRAM

IlPD2147

MBM2716
MBM2732

2K x 8 EPROM
4K x 8 EPROM

,uPD2716

MB8107

4K x 1 DRAM

IlPD411/IlPD411 A
,uPD2114L

,uPD2732

MB8114

lK x 4 SRAM

MB8116

16K x 1 DRAM

,uPD416

MB8216
MB8264

16K x 1 DRAM
64K x 1 DRAM

,uPD416
,uPD4164

MB8308

lK x 1 ROM

IlPD2308A

MB8414
7643

lK x 4 SRAM
lK x4 PROM

PD444/6514
IlPB426

2K x 8 PROM

,uPB429

76161

HITACHI

x1 DRAM

HM6501

256 x 4 SRAM

HM6514

lK x 4 SRAM

IlPD444/6514

lK x 4 SRAM

IlPD444/6514

HM4334
HM435101

256 x4 SRAM

II

IlPD416
IlPD411/411A
IlPD411/411A

4K x 1 DRAM
lK x 4 SRAM

16K

I

IlPD2308A

9114

F16K
FUJITSU

NEC REPLACEMENT

IlPD5101L

IlPD5101L

HN462716

2K x 8 EPROM

IlPD2716

HN462732

4K x 8 EPROM

,uPD2732

HM472114

lK x 4 SRAM

,uPD2114

HM4716A

16K x 1 DRAM

IlPD416

HM4816

16K x 1 DRAM

,uPD2118

HM4864

16K x 1 DRAM

HM4864

64K x 1 DRAM

IlPD4164
IlPD4164

HM6116

2K x 8 SRAM

,uPD446

9

NEe

NEe Microcomputers, Inc.
MEMORY ALTERNATE SOURCE GUIDE

l

MANUFACTURER

HITACHI (CaNT.)

INTEL

PART NUMBER

MMI

MOTOROLA

4K xl SRAM

f.LPD2147

HM6148

1 K x 4 SHAM

f.LPD444/6514

2107

4K x 1 DRAM

f.LPD411/f.LPD411A

2114

1K x 4 SRAM

2117

16K x 1 DRAM

f.LPD416

2118

16K x 1 DRAM

f.L PD2118

2141

4K xl SRAM

f.LPD41 04

2147

4K xl SRAM

f.LPD2147

2164

64K x 1 DRAM

f.LPD41 64

2167

16K xl SRAM

f.LPD2167

1K x 8 ROM

f.LPD2308A

2316E

2K x 8 ROM

f.LPD2316E

2332

4K x 8 ROM

f.LPD2332A/8

2364

8K x 8 ROM

f.LPD2364

2716

2K x 8 EPROM

f.LPD2716

2732

4K x 8 EPROM

f.LPD2732

3625

1K x 4 PROM

f.LPB426

5101
M5K4164$

2K x 8 PROM
256 x 4 SRAM
64K x 1 DRAM

f.LPB429

-

f.LPD5101L
f.LPD4164

63S1681

2K x 8 PROM

f.LPB429

63S441

lK x'4 PROM

f.LPB426

6353

1Kx4PROM

f.LPB426

2K x 8 EPROM

f.LPD2732

MCM2132
MCM4516/4517

16K xl DRAM

f.LPD2118

MCM6665

64K x 1 DRAM

f.LPD4164

MM2732

lK x 4 PROM

f.LPB426

2K x 8 EPROM

IlPD2732

NMC4164

64K x 1 DRAM

f.LPD4164

NMC5295

16K x 1 DRAM

f.LPD2118

74S573

lK x 4 PROM

f.LPB426

OKI

MSM5114

1K x 4 SRAM

f.LPD444/6514

RAYTHEON

29681

2K x 8 PROM

IlPB429

SIGNETICS

82S137

lK x4 PROM

f.LPB426

82$191

2K x 8 PROM

f.LPB429

T.!.

TOSHIBA

10

f.LPD2114L

2308A

7643
NATIONAL

NEC REPLACEMENT

HM6147

3636·1
MITSUBISHI

DESCRIPTION

TMS4164

64K xl DAAM

f.LPD4164

TMS4516

16K x 1 DRAM

f.LPD2118

TBP24S41

lK x 4 PROM

f.LPB426

TBP28S166

2K x 8 PROM

f.LPB429

74S476

lKx4PROM

f.LPB426

TMM4164

64K xl DAAM

TC5516P

2K x 8 SAAM

f.LPD4164
f.LPD447

I

NEe

NEe Microcomputers, Inc.

!J PD411
JJ PD411·1
f'PD411·2
,... PD411·3
flo PD411·4

FULLY DECODED RANDOM ACCESS MEMORY

o ESCR I PTION

The J,lPD411 Family consists of six 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The J,lPD411 Family is designed using dynamic
circuitry which reduces the standby power dissipation.
Reading information from the memory is a non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high ol'a logic low.

FEATUR ES

PIN CONFIGURATION

All of these products are guaranteed for operation over the 0 to 70°C temperature
range.
Important features of the fJPD411 family are:
• Low Standby Power
• 4096 words x 1 bit Organization
• A single low-capacitance high level clock input with solid ±1 volt margins.
• Inactive Power/0.3 mW (Typ.)
• Power Supply: +12, +5, -5V
• Easy System Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
• 22 pin Ceramic Dual-in-Line Package
• Replacement for INTEL'S 2107B, TI'S 4060 and Equivalent Devices.
• 5 Performance Ranges:
ACCESS TIME

RIW CYCLE

RMW CYCLE

REFRESH TIME

)1PD411

300 ns

470 ns

650 ns

? ms

)1PD411·1

250 ns

470 ns

640 ns

2 ms

)1PD411·2

200 ns

400 ns

520 ns

2 ms

)1PD411·3

150 ns

380 ns

470 ns

2 ms

)1PD411-4

135 ns

320 ns

320 ns

2 ms

VBB
Ag

vss
2

AlO

PIN NAMES

AS

AO All
AO AS

Address Inputs

A7

CE

Chip Enable

Refresh Addresses

A11

4

A6

CS

Chip Select

CS

5

jJPD

VDD

Data Output

411

CE

DiN
DOUT
WE

Write Enable

NC

VDD

Power (+12V)

DIN

6

8

As

9

A4

A2

10

A3

VCC

11

WE

Data Input

VCC

Power (+5V)

VSS

Ground

VBB

IPower

NC

No Connection

Rev/3
11

II

}LPD411
CE Chip Enable
A single external clock input is required. All read, write, refresh and read·modify·write
operations take place when chip enable input is high. When the chip enable is low, the
memory is in the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.

FUNCTIONAL DESCRIPTION

CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
AO-A"

Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are provided on the chip to reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify-write cycle while the chip enable is high.
The data in terminal can be driven from standard TTL circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower-order-address inputs AO through A5 or by addressing every row within any
2-millisecond period. Addressing any row refreshes all 64 bits in that row.
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.

AO
Al
A2
A3
A4

ROW
DECODE
AND
BUFFER

-oVDD
MEMORY
ARRAY
64 X 64

64

--<> VCC
-¢

A5

CE
DIN
WE
CS

DOUT

12

A6

AS
A7

VSS

--<> VBB

A10
Ag A11

BLOCK DIAGRAM

JLPD411
ABSOLUTE MAXIMUM
RATINGS*

f.LPD411-4

f.LPD411 FAMILY
(EXCEPT 411-41

... oOe to +70 o e

Operating Temperature.
Storage Temperature
All Output Voltages ..
All Input Voltages ...
Supply Voltage VDD ..
Supply Voltage Vee
Power Dissipation ...

CD

Note:

. +1O o e to +55°e
. .. -55°C to +150o e
-0.3 to +25 Volts CD
-0.3 to +25 Volts· CD
-0.3 to +25 Volts CD
-0.3 to +25 Volts CD
. . . . . . . . . . 1.5W

-55°C to +150 o e
-0.3 to +20 Volts
-0.3 to +20 Volts
-0.3 to +20 Volts
-0.3 to +20 Volts
. . . . . . . . 1.0W

Relative to VBB

COMMENT: Stress above those listed ·under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
"Ta = 25'C

DC CHARACTERISTICS

Ta "" o°c to 70°C, Voo "" +12V ±5%, Vee = +5V ±S%-, Ves '" -5V ±5%, VSS = av.
Except VOO = +15V ±5%- for 4114.

LIMITS
PARAMETER

SYMBOL

UNIT
MIN

TYP(D

Input Load Current

ILl

0.01

10

"A

CE Input Load Current

ILC

0.01

10

"A

Output Leakage Current
for High Impedance State

0.01

ILO

VOO Supply Current

TEST CONDITIONS

MAX

VIN '" VIL MIN to VIH MAX
VIN '" VILe MIN to VIHC MAX

CE

= VILC

or CS

= VIH

10

"A

VO:: OV to 5.25V

200

"A

CE:: 1.0V to O.SV

100 OFF

20

IOOON

35®

SO@

mA

CE::: VIHC. T a = 25°C

"P0411

IOOAV

37

60

mA

Cycle Time:: 470 ns

"PD411·1

IOOAV

37

60

",A

CYcle Time = 470 ns

"P0411·2

IODAV

37

60

mA

Cycle Time

"P0411·3

IOOAV

41

65

mA

Cycle Time = 380 ns

IOOAV

CYcle Time = 320 ns

during CE off
V DO Supply Current
during CE on

Ta:: 25°C

Average VOO Current

"P0411-4

Vaa

Supply Current

®

55

80

mA

IBS

5

100

"A

ICC OFF

0.01

10

"A

V CC Supply Current

during CE off

@

Input Low Voltage

VIL

1.0

Input High Voltage

VIH

2.4

VILC
VIHC

Output Low Voltage

VOL

0

Output High Voltage

VOH

2.4

Notes:

= 12V ± 5%, Vce::o 5V ,± 5%, VeB '" 5V ± 5%, VSS "' OV, unless otherwise noted,
Except VDD '= +15V ± 5% for 411·4
.
LIMITS
PARAMETER

14

SYMBOL

J,lPD411

~O4"-'

~PD411-2

"P04"-3

~PD411-4

MIN MAX

MIN MAX

MIN MAX

MIN MAX

MIN MAX

650

640

520

470

320

UNIT

Read-Modify-Write
(RMWI Cycle Time

tRwe

Time Between Refresh

tREF

Address to CE Set Up Time

tAC

0

0

0

0

0

ns

Address Hold Time

tAH

150

150

150

150

100

ns

CE Off Time

tcc

130

170

130

130

80

CE Transition Time

tT

0

40

0

40

0

40

0

40

0

40

ns

CE Off to Output High
I mpedance State

tCF

0

130

0

130

0

130

0

130

0

130

ns

480

3000

430

3000

350

3000

300

3000

200

3000

ns

CE Width During RMW

tCRW

WE to CE on

twc

WE to CEoff
WE Pulse Width

2

2

2

2

ns
2

ms

ns

ns

0

0

0

0

0

tw

180

180

150

150

_65

ns

twp

180

180

150

100

65

ns
ns

DIN to WE Set Up

tow

0

0

0

0

0

DIN Hold Time

tDH

40

40

40

40

40

CE to Output Display

tco

280

230

180

130

115

ns

Access Time

tACC

300

250

200

150

135

ns

ns

","PD411
CD

READ CYCLE

TIMING WAVEFORMS

'CE

CE

f-----CD

tACC _ _ _ _ _~

II

For ,e/'esh cvcle 'Ow and column add,,,ss,,, musl be ,table TAC and ,ema,n
.table lor entn" tAH period

@

VOO

2V IS the reference level 1o, measurong tImIng of CE

@

VSS • 2V IS the ,,,ference level for mea"",ng !Omlng 01 CE

@

VIHMIN" Ihe ,,,ierence level 1of meawrong Hm,,,,,, 01 the addresses,

CS,

WE and DIN

®

VI LMAX IS the reference level 10' meaSU""9 tIming of Ihe add,e'S"5,

Cs,

WE and DIN

®
CD

VSS .2.QV oS the reference lev"llor measurIng !lm,ng 01

VSS -Q.BV I, the ,,,Ie,ence level lor mea!u,,,,,! limIng 01

Dour.
Dour

WRITE CYCLE

t----------'Cy----------!
CE

----~::::;;;:==.::::::.:===rt=;;;;;=::l

r-++=o-:-----+- V'H

----+-------,.j,,--'------f-'--""'-:-,..,.,,+- V,H
----+-------1.1"--------f-'--, '---"-=::.::...+-- V IL

G)

Notes

VOO -2V IS Ihe ,,,Ierence level for mealu,;ng 1,m"1gof CE

®

VSS '2v IS the ,eterence level for measu'""9 ItrT""9 01 CE

@

VIHMIN" The reference level lor measu"ngTlm,ng 01 The addresses,

Cs,

WE and DIN
@)

VILMAX" The releren<;e level 10' mea\U"ngT,mmg ollhe addresses,

WE and

CS,

DIN

READ-MODI FY-WRITE CYCLE

t---------'RWC-----------i
tCRW
'CC
CE

Ao -

V'H

All

ANDCS

I~==~========~!:====~ct:::::==~_++_-------+_--VIH
---+-+r------------"\.,,---'------~-t_'_--.,,~r::___:_:_::_+-VIH

--+-+r-------------'1'----------I--::~p.-==:_+-V0 0

"~

:;- ~

('I

20

~ 1'\

........ l\..

·10

V

00

.'- ~

~ SPEC LIMIT: .2ml',2.4V
I
I

10

I'...

,0

V
'/

Iv

V

V

V/

L?
1/-

V. V

SPEC LIMIT: 3.2mA,O.4V

t--

I

3
VOH (V)
VOO - Vas

14

13

~

g

1000

- ru~y
~

_~L

t"
,7'

J....,'"

12

.........

.........

I

N'y~

100

"

SJ
0<·)'

R

.........

]
"-

'"'"

.........

........

.........

10

"

10C

~

,/~

~

%

10

./'
·3.

........

6~~R:T~~~E~EG10N

-

/

>

........

·4

·5

·6

SPE~ LI~T ~m'

,/

·7

7'"

I

-

20

60

·8

Vas (V)

Power consumption; V DD x IDDAV + VBB x IBB .

POWER CONSUMPTION

Typical power dissiption for each product is shown below.
mW (TYP.)
/lPD411

450

/lPD411-1

450

/lPD411-2

450

/lPD411-3

550

/lPD411-4

660

CONDITIONS

= 470ns, tCE; 300ns
Ta = 25° C, tcy = 470ns, tCE = 260ns
Ta = 25° C, tcy = 400ns, tCE = 230ns
Ta; 25° C, tcy = 380ns, tCE = 210ns
Ta ; 25° C, tcy ; 320ns, tCE = 200ns

Ta; 25° C, tcy

See above curves for power dissipation versus cycle time.

16

JLPD411
100

CURRENT WAVEFORMS

CE(V)

ICE (mA)

200

] I

~I

300

400

500

\

11

v

7\

II

120
80
IDD (mAl

40

40
20 r---------~.---------------------~----------------188 (rnA)

-20 f-----------\-------,I-------""~---------------------------+__+---40 ' - -______.>0.<._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ' ' ' -___

PACKAGE OUTLINE
J-IPD411 D

M

(Plastic)
ITEM

MILLIMETERS

INCHES

A
B
C
D

27.43 MAX
1.27 MAX
2.54 ± 0.1
0.42 ± 0.1
25.4 ± 0.3
1.5 ± 0.2
3.5 ± 0.3
3.7 ± 0.3
4.2 MAX
5.08 MAX
10.16 ± 0.15
9.1 ± 0.2
0.25 ± 0.05

1.079 MAX
0.05 MAX
0.10
0.016
1.0
0.059
0.138
0.145
0.165 MAX
0.200 MAX
0.400
0.358
0.009

E
F

G
H
I

J
K
L
M

411DS-REV3-12-8()'CAT

17

NOTES

18

NEe
Jl.PD411A
Jl.PD411A-1
Jl.PD411A-2

NEe Microcomputers, Inc.

4096 BIT DYNAMIC RAMS
DESCR IPTION

The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The ,uPD411 A Family is designed using
dynamic circuitry which reduces the standby power dissipation.
Reading information from the memory is non·destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed whether
Chip Select is a logic high or a logic low.

FEATURES

• Low Standby Power
• 4096 words x 1 bit Organization
• A single low·capacitance high level clock input with solid ±1 volt margins.
•

Inactive Power 0.7 mW (Typ.)

•

Power Supply +12, +5, -5V

•

Easy System Interface

• TTL Compatible (Except CE)
•

Address Registers on the Chip

• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
•

22 pin Plastic Dual·in-Line Package

•

Replacement for INTEL's 21078, TI's 4060 and Equivalent Devices.

•

3 Performance Ranges:

ACCESS TIME

RfW CYCLE

RMWCYCLE

REFRESH TIME

~PD411A

300 ns

65Uns

2m.

~PD411A·l

250 ns
200 ns

470 ns
430 ns
400 ns

600ns
520 ns

2m.

~PD411A·2

PIN CONFIGURATION

VBB

2m,

Vss

Ag

AS

A10
A11

Cs

Address Inputs

AO-AS

Refresh Addresses

A7

CE

ChiD Enable

AS

CS

Chip Select

DIN

Data Inpl..It

DOUT
WE

Write Enable

VOD

Power (+12V)

Vce

Powe, (+5V)

VOD
CE

DIN

PIN NAMES
AO' All

Data O"tput

DOUT

NC

AO

A5

VSS

Ground

"1

A4

Vas

(Pow... -5V)

A2

.4.3

VCC

WE

INC

No Connection

Rev/1
19

II

,..,PD411A
CE Chip Enable.
A single extemal clock input is required. All read, write, refresh and read-modify-write
operations take place when chip enable input is high. When the chip enable is low, the
memory isin the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.

FUNCTIONAL DESCRIPTION

CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data input is disabled when the
read mode is selected.
AO-A11 Addresses
All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are provided on the chip to repuce overhead and simplify system design.
DIN Data Input
Data is written during a write or read-modify·write cycle while the chip enable is high.
The data in terminal can be driven from standard TT L circuits. There is no register on
the data in terminal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower-order-address inputs AO through AS or by addressing every row within any
2-millisecond period. Addressing any row refreshes all 64 bits in that row ..
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.

AO o--_~
AI

A20--_--I
Aa 0--_'"
A40--_--I
AS 0--_"'1

BLOCK DIAGRAM

a:
w

----0

l>I>-

::>

'"

Voo

------

~ must be at

VIH until end of teO·

23

p.PD411A

.c- - f-IMIN:MU1 CY~LE ;,MEr- c-

tODAV - Ta

IODAV - tey

70

1.25

I

1
1 1

60

1

i

l/

1.0

+T

r- r- r- SP1C

·~yp}DDAV
- - - f'yCLlf TIME", .

"r

teE

30

'\.

0.5

- --

14 00 l)S

0.25

1 1 1 1
1 1 1 1
25

50

I

I CONST,
J_ L

1\

1

~

'"

TYPICAL OPERATING
CHARACTER [STICS

c- C-

........

r-

75
NORMALIZED CYCLE TIME
tOL - VOL

50

"

I"

"" "- "~
- :-

20

~0

"""

1'-..

10

r-

/

40

SPEC LIMIT"

"
~

,0

30

20

""- :::--,

2m.A,2AV

,/

~

V

/'

/y

10

~

V

;~o V

_0

."

V

/

.?/o

i'...

SPEC LIMIT: 3.2mA, DAV

C-

Voo - Vaa
14

r-~l
~

Z'~~V _v=
,,'b
"c.

13

,,?

1000

"" "'- "- ~I

t- ~~:R:AT~~~EgEGION
b

r-...

100

i'"

0<'>'

R

]

"ocw

1

.........

r-....

10

11

7"
~~
~-t?
.,
'0

10

./

SPE

t

I

lI!:t,T' __

ms

I I
20

40
Ta (C)

60

·6

Vaa IVI

Power consumption; VDD x IDDAV + VBB x IBB
Typical power dissipation for each product is shown below.
mW (TYP.l
Il PD411A
IlPD411A-l
Il PD411A-2

460mW
460mW
460mW

CONDITIONS
T a = 25 C, tcy ; 470 ns, tCE ; 300 ns
T a; 25°C, tcy ; 430 ns, tCE ; 260 ns
T a = 25°C, tcy ; 400 ns, tCE ; 230 ns

See curve above for power dissipation versus cycle time.

24

POWE R CONSUMPTION

CURRENT WAVEFORMS

J-'- PD411A



5

0

50

100

150

200

250

300

350 400 450
TIME Insl

500

100
80

;;(

E

II

60

0

.9

40
20

0

50

100

150

200

250

300

350

400

450

500

TIME Insl

;;(

E

'"

20

E'

10
0
450

500

-10

-20

;;(

40

E
u

~

30
20

0

50

100

150

200

250

300

350

400

450

TIME Insl

-

500

~

E

w
~

20

•

10
250

0
50

100

150

200

,
300

I

350 400 450
TIME Insl

500

..

-10
-20
-30

25
Note: G) VDD

= 12V. VSS = -5.0V. Vee = 5.0V

J.L PD411A
PACKAGE OUTLINE
J,lPD411AC

rF~~
,

,
M

(PLASTIC)

ITEM
A
B

C
D
E
F

G
H

I
J
K

L
M

26

MILLIMETERS
28.0 Max.
1.4 Max.
2.54
0.50
25.4
1.40
2.54 Min.
0.5 Min.
4.7 Max.
5.2 Max.
10.16
8.5
025+ 0•10
• -0.05

INCHES
1.10 Max.
0.025 Max.
0.10
0.Q2
1.00
0.055
0.10 Min.
0.02 Min.
0.18 Max.
0.20 Max.
0.40
0.33
+0.004
0.01_ 0.002

411 AOS-12-8C).CAT

NEe

NEe Microcomputers, Inc.

f' PD416
P. PD416·1
f' PD416·2
f'PD416·3
J.L PD416·5

18384 x 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
DESCPIIIPTION

The NECI1PD416 is a 16384 words by 1 bit Dynamic MOS RAM. It is designed for
memory applications where very low cost and large bit storage are important design
objectives.
The I1PD416 .is fabr,icated using a double-poly-layer N channel silicon gate process
which affords high -storage cell density and high performance. The use of dynamic
circuitry throughout, including the sense amplifiers, assures minirnal power dissipation.
Multiplexed address inputs permit the IlPD416 to be packaged in the standard 16 pin
dual-in-line package. The 16 pin package provides the highest system bit densities and
is available in either ceramic or plastic. Noncritical clock timing requirements allow
use of the multiplexing technique while maintaining high perforrnance.

F I!: AT U iii ES

• 16384 Words x 1 Bit Organization
• High Memory Density - 16 Pin Ceramic and Plastic Packages
• Multiplexed Address Inputs
• Standard Power Supplies +12V, - 5V, +5V
• Low Power Dissipation; 462 mW Active (MAX)' 40 mW Standby (MAX)
• Output Data Controlled by CA'S and Unlatched at End of Cycle
• Read-Modify-Write, RAS-only Refresh, and Page Mode Capability
• All Inputs TTL Compatible, and Low Capacitance
• 128 Refresh Cycles
• 5 Perform~nce Ranges:

..

PIN CONFIGURATION

_-

ACCESS liME

RIW CYCLE

I1PD416

300 ns

510 ns

575 ns

I1PD416-1

250 n$

410 ns

465 ns

I1PD416-2

200 ns

375 ns

375 ns

I1PD416-3

150 ns

375 ns

375 ns

I1PD416-5

120 ns

320 ns

320 ns

~

RMW CYCLE

vBB

Vss

DIN

CAS

AO-A6
CAS

Column Address Strobe

WRITE

DOUT

DIN

Data In

RAS

Data Out

A6

DOUT
RAS

AO

A3

WRITE

ReadlWrite

A2

A4

VBe
VCC

Power (-5Vl

Al

A5

VDD

Power (+12Vl

Vee

VSS

Ground

VDD

Address Inputs

Row Address Strobe"

Power (+5Vl

Rev/2

27

II

JL PD416
BLOCK
DIAGRAM
"
CHlMATRIX

~'''
. . h+==~gt

.

t--o

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OOC to +70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to +150 o C
All Output Voltages CD .............................. -0.5 to +20 Volts
All Input Voltages CD ............................... -0.5 to +20 Volts
Supply Voltages VDD, VCC, VSS CD. . . . . . . . . . . . . . . . . . . .. -0.5 to +20 Volts
Supply Voltages VDD, VCC ~ . . . . . . . . . . . . . . . . . . . . . . .. -1.0 to +15 Volts
Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
Notes:

MIl swing from VSS to Vee when activated with no current loading. For purposes of maintaining
data in standby mode, Vee may be reduced to VSS without affecting refresh operations or data retention. However,
the VOH (min) specification is not guaranteed If1 this mode.

1001, 1003, and IOD4 depend on cycle rate. See Figures 2, 3 and 4 for 100 limits at other cycle rates

® il~~d~~~~1ff5~~~~~ tU:~~t~~t~t~t~~~~li~;h~rutrii~~sr~~dCO~~~s~s~~g~f \~::~ad;t~u~~e~ti: ~~~y~ected through a low

29

#PD416
AC
CHARACTERISTICS
Ta '"

aCc to

+70°C. VOO = +12V

i

10%

Vee

= +5V t 10%,

Vae

= -5V t 10%,

Vss =ov
LIMITS

PARAMETER

SYMBOL

Random read or write
cycle time

'RC

Read-write cycle lime

'Awe

Page mode cycle time

'PC

Access ti,ne from
RAS

tRAe

",P04"
MIN
MAX
510

Access time from

CAS
Output buffer
turn-off delay

'OFF

Transition time
(rise and fall)

'T

RAS precharge time

'RP

CAS pul$l! width

RAS to CAS"delay
CAS to 'R7i3
precharge tune

410

375

320

320

465

375

375

320

MAX

"5

",'0416-3
MIN
MAX

,I.IP0416-5
MIN
MAX

UNIT

TEST
CONDITIONS

160

170

300

250

200

150

120

@®

200

165

135

100

80

®®

80

60

50

40

35
35

35

50
200

150

300

10,000;250

lASH

200

165

RAS pulse width

R"'iU hold time

MIN

275

330

",PD.,,·:

",P0416-,
MIN
MAX

100

120
10,000

200

32,000

135

150

100

32,000

100

120

10,000

80

tCAS

200

10,000

165

'?,OOO

135

10,000

100

10,000

SO

10,000

IACD

40

100

35

85

25

65

20

50

15

40

tCAP

-20

-20

-20

®

-20

Row address

set-up time
RowaddreS5
hold tuM

tAAH

Column address
set-up time
Col\.lmn address
hold time

ICAH

40

35

25

20

15

-10

-10

-10

-10

-10

90

75

55

45

40

190

160

120

95

80

COlumn address hold

time referenced to
RAS
Read command

set-up lime

'AR

lACS

Read command
hold time
Write command
hole time

tWCH

90

75

55

45

40

Write command
hold time
referenced to'R'AS

'WCR

190

160

120

95

80

Write command
pulse w.dth

'WP

55

45

40

70

50

50

Write command to
'FiAS lead time
Write command 10
CAS lead time

90

75

120

.5

120

85

70

50

50

90

75

55

45

40

'DS
Data·in hold t.me

'DH

Dala·in hold lime
referenced to RAS

tDHR

190

'60

120

95

80

CAS precharge time
(for page mode
cycle only)

'CP

120

100

80

60

60

Aefresh period

'REF

-20

-20

20

-20
80
120

WAITE command
twcs

NOles:

CAS to WRITE
delav

'CWD

<40

<25

95

70

RAS 10 WRITE
delay

IAWD

240

200

160

120

®
®

@
@

CD

AC measurements assume tT " 5 ns.

@
@

VIHC (m.n) or VIH (min) and V I L !max) are reference levels for me~sUflng t.mlf'lg of mput SIgnals. Also, trans.tlon times are l1"easured between V tHe or V IH and VI L
The specif.catlons for tAC (min) and tAWC (mm) are used only to !nd.cate cycle "me at wh.ch proper operat.on over the full temperature ,,,nge (O~C « T a" 70~C)
is assured.

® Assum~s that 'RCD';;; tRCO (max). If tACO IS great~r than the max,mum recommended value shown in th,s table. tRAC WIll mcrease by Ihe amount that tRCD
exceeds the values shown
® Assumes that tRCO ;;. tRCD (max).
® Measured WIth a load eqUivalent to 2 TTL loads and 100 pF.
(Z)

®

®

®

tOFF (max) defines the t,me at wh,ch the OUlput achIeves the open clfcuit condition and IS not referenced to output voltage levels
Operation Within the tRCD (max) limit ensures that tRAC (max) can be met, tACO (max) .s speCified as a ,elerence pomt only, ,f tRCD IS greater than the speCified
IRCD ~mal() limn, then access lime IS controlled excluslvelv by tCAC
These parameters are referenced to CAS leading edge in early write cycles and to"WR"iTE leading edge In delayed wrote or read·mod,fy,wnte cycles.
IWCS, ICWD and IRWD are not restrictive operating parameters. They are .ncluded in the data sheet as electrical characteristics only. If twcs --' IWCS (mm). Ihe cycle
.s an early wr.te cycle and the data Ol,ll pin Will remain open circuit (high Impedance) ~ IRWD lminl, the cycle IS a read·write cycle and the data out will conlaln data
read from lhe selected cell: If neither of Ihe above sets 01 conditions is satisfied the conciitlon of the data out lat access lime) IS indeterminate.

30

JL PD416
CYCLE TIME tRC Ins)
320

DERATING CURVES

500 400 375

1000

300 250

50 mA
j.LP0416· 5

«

CYCLE TIME tRC Ins)

E

320

1000

500

I
70 --TaIMAX)

40~ 1375 I~OO

Cl.

::;;

~

60

I-

Z
w

iii
::;;
50

<{

o

1.0

cr:
cr:

'"

1-'"

2.0

U

'9"

Cl.
Cl.

'"Ci

./
10 mA

,/

CYCLE RATE IMHz) = 10 3 /tRC Ins)

I

j.LP04!J

=

10 3 /tRC Ins)

FIGURE 2
Maximum 1001 versus cycle rate for device
operation at extended frequencies.

CYCLE TIME tpc Ins)

320
300 250
375

40mA

4.0

3.0

2.0

1.0

CYCLE RATE 1M Hz)

CYCLE TI ME t RC Ins)

50 mA

"'./

.,'

a

rate for extended frequency operation. T a
lmax) for operation at cycling rates greater
than 2.66 MHz ItCYC < 375 ns) is deter·
minAd by T a Imax) ['C] = 70 - 9.0 x
Icye!e 'ate [MHz] -2.661. For j.LP0416-5.
it is Ta Imax) ['C] = 70 - 9.0 Icycle rate
[MHz] - 3.1251.

I 500 400

./

a

FIGURE 1
Maximum ambient temperature versus cycle

1000

II

,7 ./'

X

«

~-\q./

./

~y
20 rnA

_0

::;;

~./

'-

::J

././ ) ,

~

30mA

...J

4.0

3.0

SPEC LIMIT

w

::J

""

40 mA

IZ

250

500

1000

400

300

250

200

160

50mA

5

-_<{e

40mA

Ii!w
cr:

cr:

30 mA

::J 30mA

SPEC LIMIT

U

.",.'"

SPEC LIMIT

,\"0.<"

20 mA

~".

I ,<::I- fR"'" r-:o.'\~"'.",.'
G

.",.'

...o

"

"

o
o

.",."

-

x

~ lamA

10-"

--,'II' _

o

....

~

).

Cl.
Cl.

::J
'" 20mA

.",.

oo{~:; oo{~~

10mA

>..J

I--

a
1.0

2.0

3.0

CYCLE RATE IMHz) = 103/tRC Ins)
FIGURE 3

4.0

a

1.0

2.0

3.0

4.0

5.0

6.0

CYCLE RATE IMHz) = 103/tRC Ins)
FIGURE 4

Maximum 1003 versus cycle rate for device

Maximum 1004 versus cycle rate for device

operation at extended frequencies.

operation in page mode.

31

,.,. PD416
READ CYCLE

TIMING WAVEFORMS

~--------------------'RC------------------~
I--------------------'RAS---------.
V 1HC

RAS

----~t------

~------~

V IL _

CAS

VIHC~
V 1L _·

V 1H _
ADORESSES

V 1l _

VIHC_7T.~~~~~~~------~---------------------4---,~~T.M~~
V 1L _

WRITE CYCLE

I.,o------------------'RC ----------------------,
V 1HC _

CAS

ADDRESSES

- - - - - -____________________ O'EN ______________________________

READ·WRITE/READ·MODIFY-WRITE CYCLE
~----------------------'RWC------------------------1

ADDRES!iES

O'N

32

fL PD416
TIMING WAVEFORMS
(CONT.)

"RAS-ONL Y" REFRESH CYCLE

ADDRESSES

--------------------------OPEN-----------------------------Note

CAS

V 1HC ' WRITE ~ Don't Care

PAGE MODE READ CYCLE

RAS

V 1HC

Vil

CAS

V 1HC

V ,L

V ,H

ADDRESSES V 1L

V OH

DOUT
VOL

WRITE

V 1HC _

V'L

PAGE MODE WRITE CYCLE

V 1HC

RAS

CAs

V 1L _

V 1L _

V 1H _

ADDRESSES

WRITE

V 1l _

V 1L _

V 1H _

D,N

33

II

jLPD416

The 14 address bits required to decode 1 of 16,384 bit locations are multiplexed onto
the 7 address pins and then latched on the chip with the use of the Row Address
Strobe (RASl, and the Column Address Strobe (CAS). The 7 bit row address is first
applied and RAS is then brought low. After the RAS hold time has elapsed, the 7 bit
column address is applied and CAS is brought low. Since the column address is not
needed internally until a time of tCRD MAX after the r~address, this multiplexing
operation imposes no penalty on access time as long as CAS is applied no later than
tCRD MAX. If this time is exceeded, access time will be defined from CAS instead of

ADDRESSING

Ms.

For a write operation, the input data is latched on the chip by the negative going
edge of WRITE or CAS, whichever occurs later. If WRITE is active before CAS, this
is an "early WR ITE" cycle and data out will remain in the high impedance state
throughout the cycle. For a READ, WRITE, OR READ·MODIFY·WRITE cycle, the
data output will contain the data in the selected cell after the access time. Data out
will assume the high impedance state anytime that CAS goes high.

DATA I/O

The page mode feature allows the pPD416 to be read or written at multiple column
addresses for the same row address. This is accompl ished by maintaining a low on .RAS
and strobing the new column addresses with CAS. This eliminates the setup and hold
times for the row address resulting in faster operation.

PAGE MODE

Refresh of the memory matrix is accomplished by performing a memory cycle at each
of the 128 row addresses every 2 milliseconds or less. Because data out is not latched,
"RAS only" cycles can be used for simple refreshing operation.

REFRESH

Either RAS and/or CAS can be decoded for chip select function. Unselected chip
outputs will remain in the high impedance state.

CH IPSE LECTI ON

.In order to assure long (erm reliability, V BB should be applied first during power
up and removed last during power down.

POWER SEQUENCING

34

fL PD416
PACKAGE OUTLINE
/lPD416C

~-----------A,----------~

~-----------

E:----------

(Plastic)
ITEM

MILLIMETERS

INCHES

A

19.4 MAX.

0.76 MAX.

B

0.81

0.03

C

2.54

O.lit

0

0.5

0.02

E

17.78

0.70

F

1.3

0.051

G

2.54 MIN.

0.10MIN.

H

0.5 MIN.

0.02 MIN.

I

4.05 MAX.

0.16 MAX.

J

4.55 MAX.

0.18 MAX.

K

7.62

0.30

L

6.4

M

0.25

II

0.25

+0.10
-0.05

0.01

/lPD416D

l

"~~~'---------E--------~
(Ceramic)
ITEM

MILLIMETERS

INCHES

A

20.5 MAX.

0.81 MAX.

8

1.38

0.05

C

2.54

0.10
0.02

0

0.5

E

17.78

0.70

F

1.3

0.051
0.14 MIN.

G

3.SMIN.

H

o.SMIN.

0.02 MIN.

I

4.& MAX.

0.18 MAX.

J

5.1 MAX.

0.20 MAX.

K

7.&

0.30

L

7.3

0.21

M

0.27

0.01

416DS·12·80-CAT .

35

NOTES

36

NEe

NEe Microcomputers, Inc.

,uPD2118
,uPD2118-2
JI. PD2118-3

[~OO~[~~~~ffirnW

16384 x 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
DESCR IPTION

ThepPD2118 is a single +5V power supply, 16384 word by 1 bit Dynamic MOS RAM.
The IlPD2118 achieves high speed with low power dissipation by the use of single tran·
sistor dynamic storage cell design and advanced dynamic circuitry. This circuit design
results in the minimizing of current transients typical of dynamic RAMS. This in turn
results in high noise immunity of the IlPD2118 in a system environment. By using a
multiplexing technique, the IlPD2118 can be packaged in an industry standard 16·Pin
Dip utilizing 7 address input pins for the 14 address bits required. The two 7 bit address
words are referred to as the ROWand COLUMN address. Two TTL clocks, ROW address
strobe (RAS) and COLUMN address strobe (CAS") latch these two words into the
IlPD2118. Non·critical timing requirements for RAS and CAS permit high systems per·
formance without placing difficult constraints upon the multiplexing control circuitry.
The IlPD2118 has a three·state output controlled by CAS, independent of RAS. Follow·
ing a valid read or read·modify·write cycle, data will be held in the output by holding
CAS low. Returning CAS to a high state will result in the data out pin reverting to the
high impedance mode. Use of this CAS controlled output means that the IlPD2118 can
perform hidden refresh by holding CAS low to maintain latch data output while using
RAS to execute RAS·only·refresh cycles.
The use of single transistor storage cell circuitry ~equires that data be periodically
refreshed. Refreshing can be accomplished by performing RAS·only·refresh cycles,
hidden refresh cycles or normal read or write cycles on each of the 128 address combinations of AO through A6 during a 2 ms period. The write cycle will refresh stored
data on all bits of the selected row, except that the bit which is addressed will be mod·
ified to reflect the data input.

FEATURES

• Single+5VSupply,±10%Tolerance
• Low Power: 138 mW Max Operating
16 mW Max Standby
• Low VDD Current Transients
• All Inputs, Including Clocks, TTL Compatible
•• Non·Latched Output is Three·State
• RAS·Only·Refresh
• 128 Refresh Cycles Required
• Page Mode Capability
• CAS Controlled Output Allows Hidden Refresh

PIN

RIW CYCLE

IlPD2118

150 ns

320 ns

410 ns

IlPD2118·2

120 ns

270 ns

345 ns

100 r1'S

235 ns

295 ns

IlPD2118·3

PIN CONFIGURATION

RMWCYCLE

ACCESS TIME

NC

Vss

DIN

CAS

WE

PIN NAMES
An·All

ADDRESS INPUTS

DOUT

CAS

COLUMN ADDRESS STROBE

RAS

A6

DIN
DOUT

DATA IN

AO

A3

WE

WRITE ENABLE

A2

A4

Al

AS

DATA OUT

RAS

ROW ADDRESS STROBE

VDD,

POWER (+SV)

Vss

GROUND

NC

37

II

,uPD2118

BLOCK
DIAGRAM

64 x 128 CELL
MEMORY ARRAY

128 SENSE
AMPLIFIERS
1 OF 64 COLUMN
DECODERS

1 OF 2
I/O
GATING

OUTPUT
BUFFER

DOUT

64 x 128 CELL
MEMORY ARRAY

Ambient Temperature Under Bias ..
Storage Temperature . . . . . . . . . . .
Voltage On Any Pin Relative to VSS
Data Out Current
Power Dissipation . . . . . . . . . . . . .

.
.
.
.

. -10°C to +80°C
-65°C to +150°C
. -2.0 to +7.5V
. .50mA
....... 1.0W

*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these
or at any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliabiiity.

38

ABSOLUTE MAXIMUM
RATINGS*

J'PD2118
DC CHARACTERISTICS
READ, WRITE, AND
READ MODIFY WRITE
CYCLESCD

Tam O°C to 70°C,

Veo"" 5V:t

10%. VSS=

av,

unless otherwise noted.
LIMITS

SYMBOL

PARAMETER
Input Load Current

Output Leakage Current
for High Impedance State

Veo Supply

MIN

MAX

TEST CONOITIONS

UNIT

'll

10

"A

VIN = VSS to Veo

'LO

10

"A

Chip Deselected ~at
VIH,VOUT= Oto5.5V

'DOl

3

mA

CAS and RAS at V'H

"P02118·3

1002

25

mA

j.lPD2118·2

1002

22

mA

"P02118·0

'002

22

mA

Current

NOTES

(Standby)

VOO Supply Current
(Operating)

VOO Supply Current
(RAS-Only Cycle)

"P02118·3

1003

20

mA

"P02118·2

'003

18

mA

,.,.PD2118-0

'003

18

mA

20

mA

VoO Supply Current Page

"P02118-3

'004

Mode, Maximum tpc

"P02118·2

10D4

17

mA

Minimum teAS

jJ.P0211S-Cl

'004

15

mA

1005

4

mA

VOO Supply Current

TRC = TRC Min

®

®
TRC= TAC Min

®
CAS at VIL. RAS at VIH

®

(Standby. Output Enabled)
Input Low Voltage

V,L

-2.0

0.8

Input High Voltage

V,H

2.4

7.0

V

0.4

V

O':!tput low Voltage

VOL

Output High Voltage

VOH

Notes:


VALID
QATAOUT

DC

-

p'' '

NOTES: See page 7.

41

f'PD2118

RAS-ONL Y REFRESH CYCLE

""
CAS

VIH--~~++---------------------------------------------------------

ADDAI: ••,. V,M

-~l!i'"-------.l;r-------------------------------------------­

'''--~~-----~~---------------------------------------------~~T

~:

________________

~~~

___________________________________________

HIDDEN REFRESH CYCLE

PAGE MODE READ CYCLE

1l000T

~~

-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-::~

PAGE MODE WRITE CYCLE

42

TIMING WAVEFORMS (C(}NT.)

JI. PD2118
PAGE MODE READ-MODI FY·WRITE CYCLE

TIMING WAVeFOPlMS (CONT.)

Notes:

CD
®

All voltages referenced to

Vss.

Eight cycles are required after power-up or prolonged periods greater than 2 ms of

RAs inactivity before

proper device operation is achieved. Any 8 cycles which perform refresh are adequate for this purpose.

@
@)

®
®

AC Characteristics assume tT '" 5 ns.
Assume that tRCO .; tACO (max). If tACO is greater than tACO (max), then tAAe will increase by the J
amount that tACO exceeds tACO (max).
Load = 2 TTL loads and 10OpF.

Assumes tRCD :> tACO (max).

c>

1 RCO

®

1T IS

(max) is specified as a reference point only: if tACO is less than tRCD (max) access time is tRAe·
If \I1CO is greater than tRCO (max) access time is tRCD + tCAe·

G;~) 1,"
.

measured between VIH (min) and VIL (max).

.;. tCWD and tRWD are specified as reference points only. If twcs

;;50 nsec.
Note that if 20 nsec <;;;tRCD <;;;50 nsec device access time is determined by the first
equa.tion and is equal to tRAC. If tRCD >50 nsec, access time is determined by the
second equation. This 30 nsec interval (shown in the tRCD inequality in the first
equation) in which the falling edge of CAS can occur without affecting access time is
provided to allow for system timing skew in the generation of CAS.

43

,.,.. PD2118
Each of the 128 rows of the ~PD2118 must be refreshed every 2 milliseconds to maintain data. Any memory cycle (read, write, or RAS only) refreshes the selected row as
defined by the low order (RAS) addresses. Any Write cycle, of course, may change the
state of the selected cell. Using a Read, Write, or Read-Modify-Write cycle for refresh
is not recommended for systems which utilize "wire-OR" outputs since output bus
contention will occur.

RE FRESH CYCLES

A RAS-only refresh cycle is the recommended technique for most applications to
provide for data retention. A RAS-only refresh cycle maintains the DOUT in the
high impedance state with a typical power reduction of 20% over a Read or Write
cycle.

RAS and CAS have minimum pulse widths as defined by tRAS and tCAS respectively.
Ihese minimum pulse widths must be maintained for proper device operation and dz:ta
integrity. A cycle once begun by bringing RAS and/or CAS low must not be ended or
aborted prior to fulfilling the minimum clock signal pulse width(s). A new cycle can
not begin until the minimum precharge time, tRP, has been met.

RAS/CAS TIM ING

Data Output (DOUT), which has three-state capability, is controlled by CAS. During
CAS high state (CAS at VIH) the output is in the high impedance state. The following
table summarizes the DOUT state for various types of cycles.

DATA OUTPUT
OPERATION

Type of Cycle

DOUT State

Read Cycle

Data From Addressed
Memory Cell

Early Write Cycle

HI-Z

RAS-Only Refresh Cycle

HI-Z

CAS-Only Cycle

HI-Z

Read/Modify!Write Cycle

Data From Addressed
Memory Cell

Delayed Write Cycle

Indeterminate

HIDDEN REFRESH
A feature of the ~PD2118 is that refresh cycles may be performed while maintaining
valid data at the output pin. This feature is referred to as Hidden Refresh. Hidden
Refresh is performed by holding CAS at VI L and taking RAS high and after a specified
precharge period (tRP) executing a "RAS-Only" refresh cycle, but with CAS
held low (see Figure below).

\'---_ _-----..J/
DOUT __~~~IG~H~Z~~(

DATA

)-

\.--------'

This feature allows a refresh cycle to be "hidden" among data cycles without affecting
the data availability.

44

JLPD2118
POWE R ON

The pP02118 requires no power on sequence. After the application of the VOO
supply, or after extended periods of bias (greater than 2 ms) without clocks, the device
must perform a minimum of eight (8) initialization cycles (any combination of cycles
containing a RAG clock such as RAS·only refresh) prior to normal operation.
The VOO current (100) requirement of the pP02118 during power on is, however,
dependent upon the input levels of RAS and GAS. If the input levels of these clocks
are at VIH or VOO, whichever is lower, the 100 requirement per device is 1001 (100
standby). If the input levels for the two clocks are lower than VIHor VOO, the 100
requirement will be greater than 1001. For large systems, this current requirement
for 100 could be substantially more than that for which the system has been designed.
A system which has been designed assuming the majority of devices to be operating
in the refresh/standby mode may produce sufficient I DO loading such that the power
supply might current limit. To assure that the system will not experience such loading
during power on,.a pullup resistor for each clock input to VOO to maintain the nonselected current level (1001) for the power supply is recommended.

Cerdip

PACKAGE OUTLINE

INCHES

IlPD2118D
0.46± 0.10

254 MIN

00098

.00039
0.0019

Plastic

IlPD2118C
~-------A------

__~

211BOS-12-80·CA T

45

II

NOTES

46

NEe

NEe Microcomputers, Inc.
65,536 x 1 BIT DYNAMIC
RANDOM ACCESS MEMORY
DESCR I PTI ON

Jo&PD4164-1
,.,. PD4164-2
J.L PD4164-3

~rn~[m~~~illrnw

The NEC /lPD4164 is a 65,536 words by 1 bit Dynamic N-Channel MOS RAM designed
to operate from a single +5V power supply. The negative-voltage substrate bias is
internally generated - its operation is both automatic and transparent.
The /lPD4164 utilizes a double-poly-layer N-channel silicon gate process which provides
high storage cell density, high performance and high reliability.
The /lPD4164 uses a single transistor dynamic storage cell and advanced dynamic
circuitry throughout, including the 512 sense amplifiers, which assures that power
dissipation is minimized. Refresh characteristics have been chosen to maximize yield
(low cost to user) while maintaining compatibility between Dynamic RAM generations.
The /lPD4164 three-state output is controlled by CAS, independent of RAS. After a
valid read or read-modify-write cycle, data is held on the output by holding CAS low.
The data out pin is returned to the high impedance state by returning CAS to a high
state. The /lPD4164 hidden refresh feature allows CAS to be held low to maintain
output data while RAS is used to execute RAS only refresh cycles.
Refreshing is accomplished by performing RA"S" only refresh cycles, hidden refresh
cycles, or normal read or write cycles on the 128 address combinations of AO through
A6 during a 2 ms period.
Multiplexed address inputs permit the /lPD4164 to be packaged in the standard 16
pin dual-in-line package. The 16 pin package provides the highest system bit densities
and is compatible with widely available automated handling equipment.

FEATURES

• High Memory Density
• MUltiplexed Address Inputs
• Single +5V Supply
• On Chip Substrate Bias Generator
• Access Time: /lPD4164-1 - 250 ns
/lPD4164-2 - 200 ns
/lPD4164-3 - 150 ns
• Read, Write Cycle Time: /lPD4164-1 - 410 ns
/lPD4164-2 - 335 ns
/lPD4164-3 - 270 ns
• Low Power Dissipation: 250 mW (Active); 28 mW (Standby)
• Non-Latched Output is Three-State, TTL Compatible
• Read, Write, Read-Write; Read-Modify-Write, RAS Only Refresh, and Page Mode
Capability
• All Inputs TTL Compatible, and Low Input Capacitance
• 128 Refresh Cycles (AO-A6 Pins for Refresh Address)
• CAS Controlled Output Allows Hidden Refresh
• Available in Both Ceramic and Plastic 16 Pin Packages

PIN CONFIGURATION

NC

VSS

DIN

CAS

WE
RAS

DOUT
A6

PIN NAMES
AO-A7

Address Inputs

RAS

Row Address Strobe

CAS

Col umn Address Strobe

WE

Write Enable

AO

A3

DIN

Data Input

A2

A4

DOUT

Data Output

A1

A5

VCC

Power Supply (+5V)

VCC

A7

VSS

Ground

NC

No Connection

47

JLPD4164
Operating Temperjlture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . . . . -55°C to +150°C
(Plastic Package) . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Supply Voltages On Any Pin Except VCC . . . . . . . . . . . . . . . . . -1 to +7 Volts CD
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts CD
Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt

CD

Note:

ABSOLUTE MAXIMUM
RATINGS*

Relative to VSS

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional 'operation of the device at these or
any other conditions above those indicated in the, operational sections of this specification is' not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
rei iability.

'Ta = 25°C
Ta=O° to 70°C

CD

DC CHARACTERISTICS

;VCC=+5V± 10%;VSS =OV

LIMITS
PARAMETER
Supply Voltage
High Level Input Voltage.

IRAS. CAS. WE)

MAX
5.5
0

UNIT
V
V

2.4

5.5

V

VIH

2.4

5.5

V

VIL

·2.0

0.8

V

SYMBOL
VCC
Vss

MIN
4.5
0

VIHC

High Level Input Voltage.,

All Inputs Except RAS.
CAS. WE
Low Level Input Voltage,

All Input'
Operating Current

Average Power Supply
Operating Current

RAS. CAS" Cycling;
tRC = tRC (Min.)
Standby Current
Power Supply Standby
Current IRAS = V IHC.
DOUT = Hi-Impedance)
Refresh Current

Average Power Supply
Current,

Refresh Mode;

RAS Cycling. CAS = VIHC.
tRC

= tRC

(Min.)

Page Mode Current

Average Power Supply
Current,
Page Mode Operation
~ = VIL; CAS Cycling

tpc

= tpc (Min.)

TYP
5.0
0

jtPD4164-1

45

ICC1 jtPD4164-2

50

jtPD4164-3

60

ICC2

5.0

jtPD4164-1

35

ICC3 jtPD4164-2

40

jtPD4164-3

45

jtPD4164-1

35

ICC4 jtPD4164-2

40

I'PD4164-3

45

mA

TEST
CONDITIONS

All Voltages
Referenced

toVSS

@

mA

mA

@

mA

@

I "put Leakage Current

Any Input
VIN = 0 to +5.5 Volts.
All Other Pins Not
Under Test = OV
Output Leakage Current
DOUT i. Disabled.
VDUT =0 to +5.5 Volts
Output Level.
High Level Output
Voltage (lOUT = 5 mAl
Low Level Output
Voltage (lOUT = 4.2 mAl
Notes:

CD
@

48

II(L)

-10

10

/LA

IO(L)

-10

10

/LA

VOH

2.4

VCC

V

VOL

0

0.4

V

Ta is specified here for operation at frequencies to tRC ~ tRC (min). Operation at
higher cycle rates with reduced ambient temperatures and high power dissipation is
permissible. however. Ilrovided AC operating parameters are met.
,ICC1. ICC3 and ICC4 depend on output loading and cycle rates. Specified rates are
obtained with the output open.

jLPD4164

AC CHARACTERISTICS

Ta "00 to +70"CG);

Vcc -

+5V:!: 10%: VSS· OV

@ @
LIMITS
~184-2

,dID4184-1
PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

pP041M-3
MIN

335

270

335

270

MAX

UNIT

TEST
CONDITIONS

®

'RC

410

Read Write Cycle Time

'RWC

46.

Page Mode Cycle Time

'PC

275

Access Time from RAS

tRAC

250

200

150

AccltSfi Time from CAs

tCAC

165

135

100

tOFF

60

50

40

®

IT

50

50

50

®

Random Read or Write

Cycle Time

Output Buffer Turn-Off

®

170

225

®

®

Oelay
Transition Time IRiM and
Fall)

'RP

150

RAS Pulse Width

tRAS

250

RAS Hold Time

tRSH

16.

CAS Pulse Width

'CAS

16.

CAS Hold Time

tCSH

250

tRCD

35

RAS Precharge Time

RAS to CAS Delay Time
CAS to RAS Precharge Time

10,000

200

10,000

13S
10.000

13.
30

150

10.000

100
10,000

100

10,000

150

200
85

tCPN

CAS Precharge Time (For

'CP

8S

2.

.0

qg

35

30

25

100

80

60

25

20

15

Mode C~18 Only)

RAS Pracharge ~Hold
Time
Row Addreu Set-Up Time

'RPC
tASA

Row Address Hold Time

tRAH

Column Addrs. Set-UP
Time

'ASC

Column Addl'8Sl Hold Time

teAH

Column Addres. Hold Tima

'AR

Referenced to RAS

75

65

4.

160

120

95

30

25

20

Read Commend Set·Up
Time

'RCS

Read Command Hold Time
Referenced toRAS

tRRH

Rnd Commend Hold Time

tRCH,

Write Command Hold Time

'WCH

75

55

45

Write Command Hold Time
Referenced to""fiAS

-WCR

160

120

Write Commend Pul.. Width

'WP

Write Command to RAS
LeaclTime

tRWL

100

.

95

55

45

Write Command to CAS
Lead Time

'ewL

100

65

45

Data·ln Set·Up Time

'OS

Date·ln Hold Time

'OH

75

55

4S

Date-In Hold Time
Referenced to1iAS

tDHR

160

120

95

0
()

75

45

{}
{}

Refr..h Period

tREF

WRITE Command Set-Up
Time

'wes

20

20

-20

CAS to WFii=rr D.I.V

'ewo

116

80

60

~

RAS to WRITE Datay

tRWD

200

14S

'110

()

Notal:

II

100

tCRP

CAS Precherge Time
Pa~

120

\21

 tRCO Ima~).
@ ~Ured with • load aquiWIlWlt to 2 TTlloeds end 100 pF.
@ tOFF (med dtf",.. the tlme.t which the outPUt achlevts the OIJ8n circuit condition and II not ...ferenced to OU1P1It
voItegrlevels.

~ ()pemion within the tRCD (mex) limit enlu .... that tRAC (mIIX) can t. met, tRCO (max) is specifled In a....m.nce
point onlV, If tACO Is greater then th.speclfled tACO (max) limit, then acoe. time is controllec:lexclualwlv bV tCAt.
TheM perllmetel'l.,. referenced to ~ leadil'll edlll In ..rtV write c:yda. a'\Cf to WJ!fiTE 1_lnl edlll jn dtlayed write

o

or nted-modlfy-wrlte cyd...

0) twcs. tcWD and tAWO .... muled_ operatl"" perarnet8rs In ...ed-wrlte lAd re.t-modlfy-wri1e cydn only. If twcs;;"
twcs Imlnl. the evcle II en _Iv write cyde end the date output will .......... n open circuit throughout the ..,ti... cyde.
If tcwD;;" tCWD (mil'll If'Id tRWD > tRWD (min). the cycle It • tfled-wrtte and the de.. OUtpu1 will c:onteIn cine rem
from the _!ectad cell. It neither of the above conditio"' .... met the condltJon of 1M data out Cat accHI 14m. Ind until
~goesbeck lOVIH) is Indatannlnate.

4)

Etther tARH or tRCH must t. ..dlfled for e Nad cycle.

49

P. PD4164
READ CYCLE

ADDRESSES

V1HC_

m7TJ7TJ'77:~m.mr---+---------++--f,'77:'77:'7T.""

WRITE CYCLE (EARLY, WRITEI

cAs

ADDReSSES

----------_~

_____

~D.'N-------------------

READ-WRITE/READ-MODIFY-WRITE CYCLE

ADDRESSES

D,.

50

TIMING WAVEFORMS

~PD4164
··iiA$.ONLY" REFRESH CYCLE

TIMING WAVEFORMS
(CONT.)
V 1HC _

RAS
"11.._
V IM _

ADDREsses
"11.._

"IHC

CAS
V'L
"OH-

DOUT

"01.._

-------------------------OP'N----------------------------

II

HIDDEN REFRESH CYCLE

PAGE MODE READ CYCLE
RAS

V 1HC_
V IL _

---++-"':'::::::.10.

V 1H _

ADDRESSES V
.
11..-·

PAGE MODE WRITE CYCLE

RAS

CAS
"11.._

V 1H _

ADDRESSES

"11.._

WRITE

V11.._

V IH _

o'N

11 11._

51

'J.'PD4164
Ta

CAPACITANCE

=O· to +70·C;VCC =+5V ± 10%; VSS =OV
PARAMETER

SYMBOL

Input Capacitance
(AO-A7), DIN
Input Capacitance
RAS, CAS, WRITE
Output Capacitan<:e
(DOUT)

MIN

LIMITS
TYP MAX
5

C}1
C}2

UNIT

6

pF

10

pF

7

pF

TEST
CONDITIONS

"

Co

PACKAGE OUTLINES
IlPD4164C

Plastic
ITEM

MILLIMETERS

INCHES

A

19.4 MAX.

0.76 MAX.

0.81

0.03

2."

0.10

0.5

0.02

11.78

0.10

1.3

0.061

2.54 MIN.
O.eMIN.

4.06 MAX.

4.56 MAX.

O.IOMIN.

-"~
o.lBMAX.

7.62
L'

B.'

M

0.25

+0.10

-0.06

IlPD4164D

.,1--/-- - A - - - - - i

0-lo"~ rCeramic
ITIM

MILLIMETERS

INCHIS

A

20.6 MAX.

0.81 MAX.

•
C

D
E
F

1.38

0.0.

...2."

0.'0
0.02
0.70

17.78

G

1.3
301 MIN•.

H

D.IMIN.

I

.... MAX.
1.1 MAX.
7.•
7.3
0.37

J

K

L·
M

0.01'
0.14 MIN.
0:02 MIN.
0.11MA)(,

o.ZOMAK.
0.30
0.21
0.01.

4164DS.g.gO-CAT

52

NEe

NEe Microcomputers, Inc.

p.PD4104
p.PD41 04·1
pPD41 04·2

4096 x 1 STATIC NMOS RAM
DEseR IPTION

The J.LPD4104 is a high performance 4K static RAM. Organized as 4096 x 1, it uses
a combination of static storage cells with dynamic input/output circuitry to achieve
high speed and low power in the same device. Utilizing NMOS technology, the
J.LPD4104 is fully TTL compatible and operates with a single +5V ± 10% supply.

II

FEATURES '. FastAccessTime-200ns (J.LPD4104-2)
•
•
•
•
•

•

Very Low Stand-By Power - 28 mW Max.
Low VCC Data Retention Mode to +3 Volts.
Single +5V ±10% Supply.
Fully TTL Compatible.
Available in 18 Pin Plastic and Ceramic Dual-in-Line Packages.
'3 Performance Ranges:

SU PPL Y CURRENT
ACCESS TIME

RIWCYCLE

ACTIVE

STANDBY

jlPD4104

300 ns

4S0 ns

21 mA

5mA

5mA

jlPD4104-1

250 ns

.386 ~s

21 mA

6mA

3.3mA

jlPD4104-2

200 ns

310 ns

25mA

6mA

3.3mA

A3

VCC

A2

A5

A1

A4

AO

A7

A"

AS

AlO

Ag

DOUT
WE
VSS

LOWVCC

PIN NAMES
AO-A11

Address Inputs

CE

Chip Enable

DIN

Data Input

DOUT

Data Output

VSS

Ground

AS

VCC

Power (+5V)

DIN

WE

Write Enable

CE

Rev/2

53

,uPD4104
AO~-----------'

Al
A2
A3
A4

ROW
DECODER
AND
BUFFER

MEMORY

ARRAY
64 x 64

A57L-----r----~

DIN

-ir--.L.---'_f-__'-'~

COLUMN
DECODER AND
BUFFER

DOUT

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O·C to +70·C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6S·C to +ISO·C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 to +7 Volts
Power Dissipation . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA



- - - GND

AS ---------i~

ROW
SELECT

A7----------~~·

•
•
•
•

MEMORY ARRAY
64 ROWS
64 COLUMNS

AS------t2.-,
A9----------~~~

COLUMN 1/0 CIRCUITS

II

INPUT
DATA
1/03 _ _-t-I-++-D___-iCONTRO L

WE------OL __--'
. -10°C to +85°C
-65°C to +150°C
-O.5Vto+7V CD
..20mA

Operating Temperature
Storage Temperature.
Voltage on Any Pin ..
DC Output Current ..
Power Dissipation ...
Note:

CD

ABSOLUTE MAXIMUM
RATINGS*

... 1.2W

with respect to ground

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta ~ 25°C

Ta

=

aOe to

+70°C;

Vee

PARAMETER

='

+5V:±- 10%, unless otherwise noted.

SYMBOL

MIN

MAX

UNIT

DC CHARACTERISTICS
TEST CONDITIONS

Input Leakage Current

III

-10

+10

p.A

VIN ~ GND to VCC

Ouput Leakage Current

ILO

-50

+50

p.A

es ~ VIH
VOUT ~ GND to 4.5V

MA

VIN - Vec. 1/0 - open

180

Power Supply Current

ICC

Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

VOL

Output High Voltage

VOH

Output Short Circuit
Current

lOS

0.8
Vce
0.4

2.4
TBD

TBD

V
V
V

10L

V

10H

MA

8 MA
~-4

MA

VOUT ~ GND to VCC

-

Note: The operating temperature range is guaranteed with transverse air flow exceeding 400 feet per minute.

73

J.LPD2149
Ta =

oOe to +70°C; Vee = +5V

±

10%. unless otherwise noted.

2149-2
PARAMETER

SYMBOL

Write Cycle Time

TWC

Write Time

TW

Write Release

Time
Data to Write

Output 3-8tate
From Write

Data Hold From
Write Time
Address to Write

Setup Time

MIN

MAX

2149

2149-1
MIN

MAX

MIN

45

35

UNIT

60

ns

TWR

5

5

5

ns

TOW

20

25

30

ns

15

10

TOTW

AC CHARACTERISTICS
WRITE CYCLE

ns

55
40

30

MAX

TEST
CONDITIONS

20

ns

TDH

5

5

5

ns

TAW

0

0

0

ns

W

@

+5V

510n
DOUT---------1--~

330n

5 pF

Figure 3

Notes:

G)

TW is measured from the latter of CS or WE going low to the earlier of CS or WE going
high.

@

Transition is measured +500 MV from steady state with load of Figure 3. This param-

@

WE or CS must be high during all address transitions.

eter is sampled and not 100% tested.

READ CYCLE

CD

~

~-------------TRC--------------~

74

TIMING WAVEFORMS

,uPD2149
WR ITE CYCLE ~

.

TWC
ADDRE.~

-

.-

\\ \ll",

// ////11
//

\\

__ TAW!--

TWR---

-- --

II

TW

TOTW

DOU T

TOW--- TDH

Notes:

CD WE is high for read cycle.
® WE orCS must be high during all address transitions.

I'ACf(AGIf OUTLINE

#1'021410

Ceramic
ITEM

MflltMETERS

A
B
C

23.2 MAX.
1.44
2.54

0

0.45
20.32
1.2

E
F
G
H

J

2.5
0.5
4.6
5.1

K
L
M

6.7
0.25

T

MIN.
MIN.
MAX.
MAX.

7.62

INCHES
0.91 MAX.

0,055

0.1
0.02
0.8
0.06
0.1 MIN.
0.02 MIN.

0.18 MAX.
0.2 MAX.

0.3
0.26
0.01

2149DS·12·8()"CAT

75

NOTES

76

NEe

NEe Microcomputers, Inc.

fL PD421
J.L PD421-1
fL PD421-2
fL PD421-3
J.L PD421-5

8K BIT STATIC RAM
DESCR IPTION

FEATURES

The NEC MPD421 is a very high speed 8192 bit static Random Access Memory organized as 1024 words by 8 bits. Features include a power down mode controlled by the
chip select input for an 80% power saving.

• 1024x8-bitOrganization
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Very Fast Access Time: 150/200/250/300/450 ns
Single +5V Power Supply
Low Power Standby Mode
N-Channel Silicon Gate Process
Fully TTL Compatible
6-Device Static Cell
Three State Common I/O
Compatible with 8108 and Equivalent Devices
Available in 22 Pin Ceramic Dual-in-Line Package
22

Vee

2

21

A7

A3

3
4

19

A9

AO-Ag

Address Inputs

A2

5

lS

Cs

WE

Write Enable

A1

6

17

WE

es

Chip Select

1/°1
1/° 2

S

16
15

Data I nput Output

AO

7

1/0,- 1/08

9

14

1/° 3

10

13

1/°6
1/° 5

GND

11

12

1/°4

A6
As
A4

PIN NAMES

AS

MPD
421

I/OS

1/°7

VCC

Power (+5V)

GND

Ground

77

11

~PD421
BLOCK DIAGRAM
A3
A4
A5

MEMORY ARRAY
,2S ROWS
64 COLUMNS

AS
A7
AS
Ag

110,

1/°2
1/°3
INPUT
OATA
CONTROL

1/°4
1/°5
I/OS

1/°7
IIOS

cs-~""-'
WE-!-=t-)-------------------------~

..... O°C to +70°C ABSOLUTE MAXIMUM
.. -65°C to +150°C RATINGS*
. -0.5 to +7 Volts CD

Operating Temperature
Storage Temperature ..
Voltage on Any Pin.
Note: CD With respect to grol!nd.

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliabil ity.

T a = O'C to +70o e; Vee

= +5V

± 10%,

PARAMETER
Input Load

DC CHARACTERISTICS

unless otherwise specified
SYMBOL

LIMITS
MIN

TYP

UNIT

MAX

III

10

pA

ILO

50

pA

lec

120

rnA

IS8

20

TEST CONOITIONS
VIN

= 0 to +5.5V

Current
(All Inputs Pins)

I/O Leakage
Current
Operating
Current

Stand·bv

Vee'''''

Max;

CS = VIL;

i

Outputs Open
rnA

Current

Vee = Min.
CS = VIH

to Max.

VIL

-0.3

0.8

V

Input High
Voltage

VIH

2.0

6.0

V

Output Low

VOL

0.4

V

IOL =4.0mA

V

IOH = -1 mA

Input Low

Voltage

Voltage
Output High
Voltage

78

VOH

2.4

l'1PD421
CAPACITANCE

Ta = 25°C; f = 1.0 MHz
PARAMETER

SYMBOL

Input/Output
Capacitance
Input Capitance

CliO
CIN

LIMITS
MAX
MIN

UNIT

TEST CONDITIONS

7

pF

V I/O = OV

5

pF

VIN = OV

AC CHARACTERISTICS
Ta = o°c to +70'-C;

vcc = +5V ±

10%, unless otherwise specified
LIMITS

PARAMETER

SYMBOL

I'PD421
MIN

I'PD421·1

MAX

MIN

MAX

I'PD421·2
MIN

MAX

I'PD421·3
MIN

MAX

I'PD421-5
MIN

UNIT

MAX

READ CYCLE
Read Cycle Time

tRC

Address Access Time

tAA

Chip Select Access Time

tACS

Output Hold from Addre••
Change

tOH

10

10

10

10

10

ns

Chip Selection To Output
in LowZ

tLZ

10

10

10

10

10

ns

Chip Deselection to
Output in High Z

tHZ

0

Chip Selection to Power
UpTime

tpu

0

Chip Oeselection to Power
DownTime

tpoCD

450

300
450
450

100

250
300

80

0
100

0

70

0

200

0

60

0
70

80

ns

150
200

250

300

0

200
250

0

150

ns

150

ns

50

ns

0
50

60

ns

ns

WRITE CYCLE
Write Cycle Time

twc

450

300

250

200

150

ns

Chip Selection to End of
Write

tcw

360

240

200

160

130

ns

Address Valid to End of
Write

tAW

360

240

200

160

130

ns

Address Setup Time

tAS

10

10

10

10

10

ns

Write Pulse Width

twp

300

230

190

160

130

ns

Write Recovery Time

tWR

10

10

10

10

10

ns

Data Valid to End of Write

tow

200

150

120

100

80

ns

Data Hold Time

tOH

10

Write Enabled to Output in
High Z

twz

Output Active from End of
Write

tow

10
100

10

10

10

10
70

80

10

10
60

10

ns
50

10

ns
ns

Note: CD ICC (t = tPO) = 1/2 ICC Active.

79

I'P0421

TIMING WAVEFORMS

READ CYCLE
__- - - -

tRe--------1

DATA VALID

t

RC

tpu

lee-- - - Vee SUPPLY

CURRENT

WRITE CYCLE

~
_~.L' -~
~I

PACKAGE OUTLINE
IlPD421D

~K

~~~~ml

,-L'

--L---~
B

I'

' .

-

--:IE

__

C

f--

c-,--:;I

--!

0_15'

M

c.

0.016
1,0
0.059
0.138
0.145
a.165 Max,

L
M

80

0,200 Max.
0.400
0.358
0,009

421 DS-9-80-CAT

NEe

NEe Microcomputers. Inc.

JLPD2167

~rn~[~~~~illrnW

16,384 X 1 BIT STATIC MOS
RANDOM ACCESS MEMORY,
DESCRIPTION

FEATURES

The NECJ.lPD2167 is a 16,384 words by 1 bit Static MOS RAM. Fabricated with
NEC's NMOS technology, it offers the user single power supply operation and fast
access times in a standard 20 pin dual-in·line package. Its use of automatic power
down circuitry minimizes system operating power requirements. Fuliy static circuitry throughout means the cycle time and access time are equal.

II

• 16,384 x 1 Organization
•
•
•
•
•
•
•
•
•

Fully Static Memory - No Clock or Timing Strobe Required
Equal Access and Cycle Times
Single +5V Supply
Automatic Power Down
Directly TTL Compatible - All Inputs and Outputs
Separate Data Input and Output
Three-State Output
Access Time: 55 ns Max.
Power Dissipation: 160 mA Max. (Active)
20 mA Max. (Standby)
• Available in a Standard 20 Pin Dual-in·line Package

PIN CONFIGURATION

PIN NAMES
AO
Al

vcc
A7

A2

AS

A~

Ag

A4

AlO

A5
A6

AO - A13

Address Inputs

WE

Write Enable

CS

Chip Select

DIN

Data Input

DOUT

Data Output

A11

Vce

Power (+5V)

A12

VSS

Ground

DOUT
WE
VSS

DIN

cs

TRUTH TABLE
es

WE

MODE

OUTPUT

POWER

H

X

Not Selected

High Z

Standby

L

L

Write

High Z

Active

L

H

Read

DOUT

Active

2167DS-12-80-CAT

81

NOTES

NEe
JLP05101L
JL P05101 L·1

NEe Microcomputers, Inc.
1024 BIT (256x4) STATIC CMOS RAM
DESC R IPTION

The PPD5101 Land pPD5101 L-l are very low power 1024 bit (256 words by 4 bits)
static CMOS Random Access Memories_ They meet the low power requirements of
battery operated systems and can be used to ensure non-volatil ity of data in systems
using battery backup power_
All inputs and outputs of the PPD5101 Land PPD5101 L-l are TTL compatible_ Two
chip enables (CE1, CE2) are provided, with the devices being selected when CEl is
low and CE2 is high_ The devices can be placed in stafldby mode, drawing 10 pA
maximum, by driving CE 1 high and inhibiting all address and control line transitions_
The standby mode can also be selected unconditionally by driving CE2 low_

II

The PPD5101L and PPD5101L-l have separate input and output lines_ They can be
used in common I/O bus systems through the use of the OD (Output Disable) pin
and OR-tying the input/output pins_ Output data is the same polarity as input data
and is nondestructively read out_ Read mode is selected by placing a high on the
RIW pin_ Either device is guaranteed to retain data with the power supply voltage as
low as 2_0 volts_ Normal operation requires a single +5 volt supply_
The PPD5101L and pPD5101L-l are fabricated using NEC's silicon gate complementary MOS (CMOS) process_

FEATURES

• Directly TTL Compatible - All Inputs and Outputs
•

Three-State Output

• Access Time - 650 ns (PPD5101L); 450 ns (PPD5101L-l)
• Single +5V Power Supply
•

CE2 Controls Unconditional Standby Mode

• Available in a 22-pin Dual-in- Line Package

PIN CONFIGURATION

A3

vce
21

A4

20

R/W

19

CEI

18

OD

RIW

Read/Write Inout

17

CE2

CEI. CE2

Chip Enables

A7

16

D04

00

Output Disable

GND

15

DI4

A2
Al

3

AO
A5
A6

6

Dll

j.lPD
5101L

14

DOl

10

DI2

11

D0 3

PIN NAMES
Dil -- 014

Data Input

AO- A7

Address Inputs

001- 004

Data Output

Vee

Power (+5VI

DI3
12

D0 2

83

f'PD5101L
BLOCK DIAGRAM

Vee

22

,OW

ADDRESS
BUFFERS

DECODERS

{DIS~aLE)

-I

INPUT
DATA
CONTROL

DO&-{>--Operating Temperature. . . .
Storage Temperature . . . . . . . . . . .
Voltage On Any Pin With Respect to Ground.
Power Supply Voltage. . . . . . . . . . . . . . . .
COMMENT:

. ....... "
oDe to +70 0 e
. . . . . . .. -40°C to +125°e
-0.3 Volts to Vee +0.3 Volts
. . . . . . .. -0.3 to +7.0 Volts

ABSOLUTE MAXIMUM
RATINGS*

Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.
*Ta=25"C
Ta"'" O°C to 70o e;

Vee

=

+5V ± 5%, unless otherwise specified.

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN TYPeD

MAX

TEST CONDITIONS

UNIT

Input High Leakage

11IH@

1

IlA

VIN = VCC

Input Low Leakage

ILlL@

-1

IlA

VIi'll = OV

Output High Leakage

ILOH@

1

IlA

CE1 = 2.2V, VOUT = VCC

Output Low Leakage

ILOL@

-1

IlA

CE1 = 2.2V. VOUT = O.OV

Operating Current

ICC1

22

mA

Operating Current

ICC2

27

rnA

Standby Current

ICCLQ)

10

IlA

input Low Voltage

VIL

-0.3

0.65

V

2.2

VCC

V

0.4

VIN - VCC Except CE1
<;0.65V, Outputs Open
VIN = 2.2V Except CE1
<;0.65V, Outputs Open
VIN - 0 to 5.25V
CE2 <; 0.2V

Input High Voltage

VIH

Output Low Voltage

VOL

V

IOL = 2.0 rnA

Output High Voltage

VOHl

2.4

V

IOH=-1.0rnA

Output High Voltage

VOH2

3.5

V

IOH - -100 IlA

Notes:

G)
@

Typical values at Ta:= 25°C and nominal supply voltage.
Current through aU inputs and outputs included in

'eelCAPACITANCE

LIMITS
PARAMETER
I nput Capacitance

TYP

MAX

CIN

4

8

pF

VIN

COUT

8

12

pF

VOUT - OV

SYMBOL

MIN

UNIT

TEST CONDITIONS
OV

(All Input Pins)

Output

84

Capacitance

I-' PD5101L

READ CYCLE

AC CHARACTERISTICS
Ta '"

aOc to 70°C; Vee ==

5V±S%, unless otherwise specified
LIMITS

PARAMETER

SYMBOL

5101L-l

5101L
MIN

TYP MAX MIN

650

450

UNIT

TEST CONDITIONS

TYP MAX

Read Cycle

'RC

Access Time

,

650

450

n'

Chip Enable (eE,)

teol

600

400

'"

Chip Enable (CE2)
to Output

tC02

700

500

n'

Output Disable to
Output

'00

350

250

n'

Data Output to
High Z State

'OF

0

Previous Read Data
Valid with Respect

tOHl

0

0

n'

tOH2

0

0

'"

n'

to Output

I nput pulse amplitude:
0.65 to 2.2 Volts

I nput rise and fall
times: 20 ns
Timing measurement
reference level:

1.5 Volt
Output load: 'TTL

150

130

0

n'

Gate and CL;:: 100 pF

to Address Change

Previous Read Data
Valid with Respect
to Chip Enable

WRITE CYCLE
Ta =

aOc

to 70°C; Vee = 5V±5%, unless otherwise specified
LIMITS

PARAMETER

LOWVCC DATA RETENTION
CHARACTE R ISTICS

SYMBOL

5101L

5101L-1

MIN

TYP MAX MIN

Write Cycle
Write Delay

'wc

650

450

'AW

150

130

Chip Enable (CEl)
to Write

feW1

550

350

Chip Enable (CE21
to Write

UNIT

TEST CONOITIONS

ns
ns
' ns

Input pulse amplitude:
0.65 to 2.2 Volts

TYP MAX

tCW2

550

350

n,

Data Setup

'OW

400

250

n,

Data Hold

'DH

100

50

Write Pulse

'WP

400

250

n'
n.

Write Recovery
Output Disable Setup

'WR

50

50

n'

'OS

150

130

Input rise and fall
times: 20 ns
Timing measurement
reference level:
1.5 Volt
Output load: ITTL
Gate and CL
l00pF

=

Ta =O'Cto70'C
L1MITS
PARAMETER

SYMBOL

MIN

VCC for Data
Retention

VCCDR

+2_0

Data Retention
Current

ICCDR

Chip Deselect
Setup Time

tCDR

Chip Deselect
Hold Time

tR

Note:

TYP

MAX

+10

UNIT

TEST CONDITIONS

V

CE2'; +O-2V

IJA

VCCDR = +2.0V
CE2'; +0.2V

0

ns

tRCG:

ns

CD tRC = Read Cycle Time

85

p.PD5101L
READ CYCLE

TIMING WAVEFORMS
ADDRESS

ee,

00
(COMMON 1/0)

®

OUT

WRITE CYCLE
~--~------twc------------~

ADDRESS
~-----tcw,----~~

~r-------tcw2------~~

00
(COMMON I/O)@

DATA
IN

DATA IN
STABLE

tow
I

...

RIW

Notes:

1------- twp-----~ ,.....;.;.;.;.-t--



0.2
0.1

100 pF

"'-

\\

500

/. ~

;;

LOAD'" ITTL +

+2.1{/

T.-+8D"C
0.5

II

tA -Vee ITII

VOL - IOL (T.I
0.6

\~ ~=_e

~

0

..........
300

I';?

200
Vee" 5V
10

"

Vec tV)

ICCOR-TI

700

Ta -2!f'c
Vec'; 5V

r==

600

eE2' +D.2V

1.0 _

500

--

I.---

'1

~

V

v,-OloVee

a:
~

O.

./"f

1

=

r- _-e I-

,
'
I

'
.
I

:
.

.

,

'

;

:
•
~ F i- _ _':~~---

1.1 J

I

,-.~

:

-b~.~

j

(PLASTIC)
ITEM

MILLIMETERS

A

27.00

B

2.07

0.08

1 - - - - - 1---~5_4_ _ ..
C

~-.
E

----

INCHES

1.07

0.50
--

0.10
0.02

22.86

0.90
0.05

F

1.20

G

2.54 MIN

0.10 MIN

H

0.50 MIN

0.02 MIN

I

4.58 MAX

0.18

J

5.08 MAX

0.20

K
L

1-----M

10.16

------- 860
_.
025+ 0. 10
. -0.05

0.40
0.39
0.01 +0.004
-0.002

44SLDS-12-80-CAT

97

NOTES

98

NEe

NEe Microcomputers, Inc.

f'PD446
f'PD446-1
pPD446-2

~rn~[~~~ ~illrnW

2048 x 8 BIT STATIC CMOS RAM
DESC R I PTION

The IlPD446 is a high speed, low power, 2048 word by 8 bit static CMOS RAM
fabricated using an advanced silicon gate CMOS technology. A unique circuitry
technique makes the IlPD446 a very low operating power device which requires
no clock or refreshing to operate. Minimum standby power current is drawn by this
device when CE equals VCC independently of the other input levels.

II

Data retention is guaranteed at a power supply voltage as low as 2V.
The IlPD446 is packaged in a standard 24'pin dual-in-line package and is plug-in
compatible with 16K EPROMs.

F EATU R ES

• Single +5V Supply
•
•
•
•
•
•

Fully Static Operation - No Clock or Refreshing required
TTL Compatible - All Inputs and Outputs
Common I/O Using Three-State Output
OE Eliminates Need for External Bus Buffers
Max Access/Min Cycle Times Down to 120 ns
Low Power Dissipation, 45 mA Max Activel100 IlA Max Standby/
10 IlA Max Data Retention
• Data Retention Voltage - 2V Min
• Standard 24-Pin Plastic and Ceramic Packages
• Plug-in Compatible with 16K EPROMs

PIN ·CONFIGURATION
2

A2

AS
PIN NAMES

A9

4

21

WE

AO-Al0

Address Inputs

5

20

OE

'WE

Write Enable

19

Al0

DE

Output Enable

1B

CE

CE

Chip Enable

1/01-I/OB

Data InputlOutput

IlPD
446

6

17

S

1/01

VCC

22

Al

AD

24
23

1/08

16

9

1102

1107

15

1106

14

1105

13

1104

VCC

Power (+5V)

GND

Ground

TRUTH TABLE
CE

OE

WE

MODE

H

X

X

NOT SELECTED

L

H

H

NDT SELECTED

HZ

ACTIVE

L

L

H

READ

DOUT

ACTIVE

L

X

L

WRITE.

DIN

ACTIVE

'

'

110
HZ

ICC
STANDBY

99

p.PD446
BLOCK DIAGRAM

A4
AS
CELL ARRAY

As

128 ROWS

A7

128 COLUMNS

As
A9
AI 0 - " ' - _ " " "

I/~' _ _+_~" INPUT

SENSE SWITCH
OUTPUT
DATA
DATA r-~-----------f-,
CONTROL
COLUMN
CONTROL
1/08 --+-.-IH
DECODER
:
t

WE~6J~->------------------------~

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Input or Output Voltage Supplied . . . . . . . . . . . . . . . . . . . . . -0.3 to vee + O.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to· 125°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . , ... oOe to70PC.

ABSOLUTE MAXIMUM
RATI NGS*

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of .this sp~eifieatlon Is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*TIi=25°e
Ta - 0 to 70"C; Vee" 5.0V:t 10%
CHARACTERISTIC

SYMBOL

~!I""Z

MIN

TV.

,.,.,...

"PD448-1

MAX

MIN

TV.

TV.

DC CHARACTERISTICS

MAX

MIN

MAX

2.2

Vee
<0.3

2.'

Vee
+0.3

UNIT

CONDITIONS

V

Input High Volt.

V'H

2.2

Vee
<0"

Input low Voltage

VIL

-0.3

0.8

-0.3

0.8

-0.3

0.8

V

Input Leakage Current

ILl

-1.0

I.D

-t.O

I.D

-1.0

1.0

.A

VIN .. a-Vee

I/O Leakage Current

ILO

-1.0

I.D

:-'.0

I.D

-1.0

1.0

.A

Ves" VIH
VI/O=O-VcC

3D

mA

YeS-VILII/O-O
MIN TCYCLE

lD

mA

30

letA1
Operating SuppJy.Current

ICCS

OutpUt High Voltage

VOH

Output Low Voltegt

VOL

2.

lD

100

100
2.'

20

38

lD

1CCA2
Standby Current

••

100
2.'

2.'
D••

D.'

D.'

.A

Ves" VIL 11/0" 0
OCCURRENT

Yes-Vee
YIN-O-Vee

V

IO~--l.0mA

V

'OL .. .2.0mA

CAPACITANCE
LIMITS
PARAMETER

100

SYMBOL

MIN

MAX UNIT

TEST
CONDITtONS

Input Capacitance

elN

6

pF

VIN =OV

Input/Output Capacitance

CI/O

8

pF

VI/O = OV

J.L PD446
AC CHARACTERISTICS

READ CYCLE

LIMITS
~PD446·2

SYMBOL

PARAMETER
Read Cycle Time

MAX

120

tRC

Address Access Time

MIN

~PD446·1

MIN

MAX

~PD446

MIN

MAX

UNIT

ns

200

150
150

200

ns

tAA

120

Chip Enable Access Time

tACS

t20

150

200

ns

Output Enable to Output Valid

tOE

60

75

100

ns

Output Hold from Address Change

tOH

20

20

20

ns

Chip Enable to Output in LZ

tCLZ

10

10

10

ns

tOLZ

10

10

10

Output Enable to Output in LZ
Chip Disable to Output in HZ

tCHZ

60

75

Output Disable to Output in HZ

tOHZ

60

75

,I'PD446·2

I'PD446·1

VCC

= 5,OV

± 10%, T a

= oOe

to 70'C

II

ns
100

ns

100

ns

WRITE CYCLE
LIMITS

PARAMETER

MIN

MAX

MIN

MAX

!,PD446
MIN

MAX

UNIT

Write Cycle Time

twe

120

150

200

ns

Chip Enable to End of Write

tcw

100

125

170

ns

Address Valid to End of Write

tAW

100

125

170

ns

tAS

0

0

0

ns

Address Setup Time

Write Pulsewidth

twp

100

125

170

ns

Write Recovery Time

tWR

0

0

0

ns

Data Valid to End of Write

tow

60

75

100

ns

Data Hold Time

tOH

0

0

0

Write Enable to Output in HZ

tWHZ

Output Active from End of Write

LOW VCC DATA
RETENTION

SYMBOL

Ta

=

60
20

tow

75

ns
100

ns
ns

20

20

oOe to 70'e
LIMITS
PARAMETER

SYMBOL

TEST
CONDITIONS

MIN

TYP

MAX UNIT

2,0

vee for Data Retention

VeeDR

VIN=O-Vee,
VCE,= Vee

V

Data Retention Current

leeDR

Vee = 3.0V,
VIN=O-Vee
VCE = Vee

Chip Deselection to Data
Retention Time

tCDR

0

ns

Operation Recovery Time

tR

tRC

ns

0.1

10

I'A

101

P. PD446
READ CYCLE (1)

TIMING WAVEFORMS

~------------tRC------------~
ADDRESS

DOUT

READ CYCLE (2)
~--------------tRC------------~~

OE

DOUT
NOTES:

(j) We is high for read cycle•.

CD

Device I. continuously selected, CE· VIL·

~ Address valid prior to or coincident with

cetransition low.
WRITE CYCLE (1)

~-------------twC------------~~
ADDRESS

~---------tAW----------

__-I



A4

I-

~
~

A5

~
a:

AS

0
0

'"

A7
AS
Ag

AlO

-lo°C to +70°C
. -65°Cto+125°C
-0.5 to + 7.0 VoltsCD

Operat ing T em peratu re
Storage Temperature ..
Supply Voltage On Any Pin
Note:

CD With

ABSOLUTE MAXIMUM
RATINGS*

Respect to Ground

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functiona-l operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS

Ta = -10oe to +70°C' Vee = +5V ±il0%- unless otherwise specified
LIMITS
PARAMETER
Input Load Current
(All Input Pins)

SYMBOL

MIN.

MAX.

ILOH

Output Leakage Current

ILOL

Power Supply Current

ICC

SO

Input "Low" Voltage

V IL

-0.5

Input "High" Voltage

V IH

2.0

Output "Low" Voltage

VOL

Output "High" Voltage

VOH

UNIT

TEST CONDITIONS

10

)lA

VIN "'0 to +5.5V

+10

)lA

CS = 2.2V (Deselected) V OUT = V CC

III

Output Leakage Current

Note:

TYP., 7.0V Ref.

-----":~20mASenSing (AfterP)
'GND

Output Voltage Sensing

Figure 2 - Typical Output Voltage Waveform

135

JLPB406/426
Ta = O°C to +75°C VCC = 4 75V to 5 25V
PARAMETER

SYMBOL

Input High Voltage

V IH

Input Low Voltage

V IL

Input High Current

IlL

Input Low Current

-IlL

IOFFl

Output Leakage Current

-IOFF2

Input Clamp Voltage

-VIC

Output High Voltage(!)
Output Shon Circuit CurrentL""~11V

-1.0

VOH1

Ports C through I,

V

'OH"'-1.0mA

Output Voltage High

-2.3

VOH2

Output Leakage Current Low

ILOL

Supply Current

IGG

-30

Ports C through I,

V

··10

"A

-50

mA

IOH '" -3.3 mA

Ports C through I,
VO"-11V

CAPACITANCE
LIMITS
MAX

UNIT

Input Capacitance

CI

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

CIO

'5

pF

PARAMETER

SYMBOL

MIN

TYP

TEST
CONDITIONS

f= 1 MHz

AC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

MIN

TYP

MAX

Oscillator Frequency

f

Rise and ~all Times

tr,tf

0

0.3

"WH

0.5

5.6

"WL

0,5

5.6

Clock Pulse Width High

Clock Pulse Width Low

~----

174

150

440

UNIT

TEST
CONDITIONS

KH,

.'.'
"'

EXHRNAL CLOCK

______ 1/f ____________

~

CLOCK WAVEFORM

546DS-1 0-80-CA T

NEe

NEe Microcomputers, Inc.

,",PD553

4-81T SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The fJP0553 is a fJCOM-43 4-bit single chip microcomputer with high voltage outputs
that can be pulled to -35V for direct interfacing to vacuum fluorescent displays. The
fJP0553 is manufactured with a standard PMOS process, allowing use of a single -1 OV
power supply. The fJP0553 provides all of the hardware features of the fJCOM-43
family, and executes all 80 instructions of the fJCOM-43 instruction set.

PIN CONFIGURATION

PIN NAMES

Cll
PCO
PCl
PC2
PC3

TNT
RESET
PDO
PDl
PD2
PD3
PEO
PEl
PE2
PE3
PFo
PFI
PF2
PF3
TEST
VSS

ABSOLUTE MAXIMUM
RATINGS*

1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17
18
19
20
21

ClO
VGG
PB3
PB2
PBl

fJPD
553

PBo
PA3
PA2
PAl
PAO
PI2
Pll
PIO
PH3
PH2
PHI
PHO
PG3
PG2
PGl
PGo

PAO-PA3

Input Port A

PBO-PB3

Input Port B

PCO-PC3

Input/Output Port C

PDO-PD3

Input/Output Port 0

PEo-PEa

Output Port E

PFo-PFa

Output Port F

PGo-PGa

Output Port G

PHo-PHa

Output Port H

PIO-PI2

Output Port I

CLO-CLI

External Clock Signals

INT

Interrupt Input

RESET

Reset

VGG

Power Suppl y Negative

VSS

Power Supply Posi tive

TEST

Factory Test Pin
(Connect to VSS)

Operating Temperatu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10° C to +70° C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages (Port A, B, INT, RESET) . . . . . . . . . . . . . . . _ ... -15 to +0.3 Volts
(Ports C, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Ports C through I, each bit) ............ _ . . . . . . . . . -12 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability,

175

II- PD553
a

DC CHARACTERISTICS
LIMITS
PARAMETER

Input Voltage High

SYMBOL

MIN

V,H

0

TYP

MAX
-3.5

TEST
CONOITIONS

UNIT
V

Ports A through D, INT,
RESET
Ports A, B, INT, RESET

VILl

-7.5

VGG

V

VIL2

-7.5

-35

V

Ports C, D

Clock Voltage High

V¢H

0

V

CLO Input, External Clock

Clock Voltage Low

V¢L

-6.0

VGG

V

CLO Input, External Clock

Input Leakage Current High

ILiH

+10

pA

Input Leakage Current Low

ILlLl

-10

pA

ILlL2

-30

pA

Ports C, D. VI '" -35V

Clock Input Leakage Current High

IL¢H

+200

pA

CLo Input, V(,bH

Clock Input Leakage Current Low

'L¢L

-200

pA

CLO Input, V(,bL = -llV

Output Voltage High

VOH

Input Voltage Low

-0.8

-2.0

Ports A through D, INT.
RESET, V, =-lV
Ports A through D. INT.
RESET, V, =-11V

=

V

Ports C through I.
IOH =-SmA

ILOL,

-10

pA

Ports C through I.
VO=-11V

ILOL2

-30

pA

Ports C through I,
Vo = -35V

-50

mA

OV

Output Leakage Current Low

Supply Current

-30

IGG

CAPACITANCE
LIMITS
MAX

UNIT

Input Capacitance

PARAMETER

SYMBOL
CI

MIN

TYP

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

C,O

15

of

TEST
CONDITIONS

f'" 1 MHz

AC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT
KHz

Oscillator Frequency

f

Rise and Fall Times

tr,tf

0

0.3

~,

Clock Pulse Width High

t¢wH

0.5

5.6

p'

Clock Pulse Width Low

t¢WL

0.5

5.6

p'

150

440

t------l/f------;~

176

TEST
CONll'ITIONS

EXTERNAL CLOCK

CLOCK WAVEFORM

553DS-10-80-CAT

NEe

NEe Microcomputers, Inc.

JLPD557L

4-81T SINGLE CHIP MICROCOMPUTER
DESCR IPTION

PIN CONFIGURATION

The pP0557L is a pCOM-43 4-bit single chip microcomputer with high voltage outputs,and low power consumption. The outputs can be pulled to- 35V' for direct
interfacing to vacuum fluorescent displays. The pPD557L is manufactured with a lowpower-consumption PMOS process, allowing use of a -8V, low current power supply.
The pPD557L provides all of the hardware features of the pCOM-43 family, except
that it has 21 I/O lines in a 28-pin dual-in-line package to reduce device cost. The
pP0557 L executes all 80 instructions of the pCOM-43 instruction set.

Cl,

PIN NAMES

Clo

PCo

2

VGG

PAO-PA3

PC,

3

RESET

PCO-PC3

Input/Output Port C

PC2

4

INT

PDO-PD3

Input/Output Port D

PC3

Output Port E

Input Port A

5

PA3

PEO-PE3

PDO

6

PA2

PFO-PF3

Output Port F

PD,

7

PGO

Output Port G

PD2

8

INT
ClO-Cl,

External Clock Signals

PD3

9

PEO

pPO
557L

PAl
PAO
PGO
PF3

Interrupt Input

RESET

Reset

VGG

Power Supply Negative

PEl

PF2

VSS

Power Supply Positive

PE2

PF,

TEST

PE3

PFo

Factory Test Pin
(Connect to VSS)

VSS

TEST

II

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .-lO°Cto +70°C
RATINGS* Storage Temperature . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . -40°Cto+125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . - 15 to +0.3 Volts
Input Voltages (Port A, INT, RESET) . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
(PortsC, 0) . . . . . . , . . . . . . . . . . . . . . '" .. , .-40to +0.3 Volts
Output Voltages . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Ports C, D, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -100 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

177

,...PD557L
DC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Input Voltage High

Input Voltage Low

MIN

TYP

MAX

TEST
CONOITIONS

UNIT

VIH

0

-2.5

V

Ports A. C. O.INT. RESET

VILl

-6.5

VGG

V

Ports A. INT. RESET

VIL2

-6.5

-35

V

Ports C. D

Clock Voltage High

VH

0

-0.6

V

CLO Input, External Clock

Clock Voltage Low

VL

-5.0

V

CLO Input, External Clock

Input Leakage Current High

IUH

+10

~A

Ports A. C. D. INT. RESET
VI =-lV

lULl

-10

I'A

Poets A. C. D.INT. RESET
VI =-9V

IUL2

-30

~A

Ports C. D. VI = -35V

ILH

+200

I'A

CLO Inpu,. V H = OV
CLO Inpu,. V L = -9V

VGG

Input Leakage Current Low
Clock Input Leakage Current High
Clock Input Leakage Current Low

ILL

-200

~A

VOHl

-1.0

V

VOH2

-4.0

V

ILOLl

-10

I'A

ILOL2

-30

~A

-36

mA

Output Voltage High

OutPut Leakage Current Low

Supply Current

-20

IGG

Ports C through G,
IOH =-2 mA

Ports E, F,G, IOH =-20 rnA
Ports C through G,
Vo =-9V
Ports C through G,

Vo = -35V

CAPACITANCE
LIMITS
PARAMETER

Input Capacitance
Output Capacitance
Input/Output Capacitance

SYMBOL

MIN

TYP

MAX

UNIT

CI

15

pF

Co

15

pF

CIO

15

pF

TEST
CONOITIONS

f= 1 MHz

AC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

180

kHz

Oscillator Frequency

f

Rise and Fall Times

tr,tf

0

0.3

I"

'WH

2.0

8.0

I"

'WL

2.0

8.0

I"

Clock Pulse Width High
Clock Pulse Width Low

100

1------1/f-------Io-i

178

TEST
CONDITIONS

External Clock

CLOCK WAVEFORM

557 LDS-1 O.aO-CA T

NEe

NEe Microcomputers, Inc.

Jl.PD650

4-81T SINGLE CHIP MICROCOMPUTER
OESCR IPTION

PIN CONFIGURATION

The pPD650 is a pCOM·43 4·bit single chip microcomputer manufactured with a
low·power·consumption CMOS process, allowing use of a single +5V power supply.
The pPD650 provides all of the hardware features of the pCOM·43 family, and exe·
cutes all 80 instructions of the pCOM·43 instruction set.

CL,
PCo
PC,
PC2
PC3

mT
RESET
POO
PO,
P02
,P0 3
PEO
PEl
PE2
PE3
PFo
PF,
PF2
PF3
TEST

Vcc

PIN NAMES

,

CLo

2

VSS

4

5
6
7

8
9

pPD

650

PAQ· PA3

Input Port A

PB3
PB2
PB,

PBO·PB3

Input Port B

PCO·PC3

Input/Output Port C

PBO
PA3
PA2
PAl
PAO
PI2
PI,
PIO
PH3
PH2
PH,
PHO
PG3
PG2
PG,
PGo

POO·P03

Input/Output Port 0

PEO·PE3

Output Port E

PFO·PF3

Output Port F

PGO·PG3

Output Port G

PHO·PH3

Output Port H

PIO·PI2

Output Port I

INT

Interrupt Input

CLQ-<:L,

External Clock Signals

RESET

Reset

VCC

Power Supply Positive

VSS

Ground

TEST

Factory Test Pin
(Connect to VCe)

II

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30°C to +85°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltages (Port A through 0, INT, RESET) . . . . . . . . . . . .
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ..
Output Current (Ports C through I, each bit). . . . . . . . . . . . . . .
(T otal, all ports 1. . . . . . . . . . . . . . . . . . . . . . .

-0.3 to +7.0 Volts
-0.3 to +7.3 Volts
- 0.3 to +7.3 'volts
. . . . . .. 2.5 rnA
. . . . . . .. 28mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other c;onditions above those indicated in the operational sections of this specification is not
implied". Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

179

J'PD650
DC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

TEST
CONDITIONS

I"put Voltage High

VIH

0.7 Vec

Vcc

V

Ports A through D, INT
RESET

Input Voltage Low

VIL

0

0.3 VCC

V

Ports A through 0, I NT
RESET

Clock Voltage High

V~H

0.7 VCC

VCC

V

CLO Input, External Clock

Clock Voltage Low

V~L

0

0.3 VCC

V

eLa I "put, External Clock

input Leakage Current High

ILiH

+10

~A

Input Leakage Current low

ILiL

-10

~A

Clock Input Laakage Current High

IL4>H

+200

~A

ela Input, V¢H:Z Vee

-200

~A

eLa Input, V¢l.=OV

Clock I "put Leakage Current Low

IL4>L

Ports A through D, I NT
RESET. VI VCC

=

Ports A tluough 0, INT,
RESET. VI

=OV

VOHl

VCC-0•5

V

ports C through I,
IOH" -1.0 mA

VOH2

VCC -2.5

V

Ports C through I,
IOH =-2.0 rnA

Output Voltage High

VOLl

+0.6

V

PortS E through I,
IOL = +2-.0 mA

VOL2

+0.4

V

Ports E through I,
IOL =+1.2 mA

Output Voltage Low

Output Leakage Current Low

ILOL

Supply Current

ICC

-10

+d.8

+2.0

~A

Ports C, 0,

Va" OV

rnA

CAPACITANCE
LIMITS
IPARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

OF

Input Capacitance

CI

15

Output Capacitance

Co

15

pF

Input/Output Capacitance

CIO

15

of

Ta

= -30"e to +85"C; Vee = +5 ±

AC CHARACTERISTICS·

SYMBOL

MIN
150

TYP

MAX

UNIT

440

KHz

Oscillator Frequency

f

Rise and Fall Times

tr,tf

0

0.3

"5

Clock Pulse Width High

t¢WH

0.5

5.6

"5

Clock Pulse Width Low

tt/>WL

0.5

5.6

~5

t - - - - - - 1 / f --------;~

180

f"" 1 MHz

10%
LIMITS

PARAMETER

TEST
CONDITIONS

TEST
CONDITIONS

EXTERNAL CLOCK

CLOCK WAVEFORM

6500S-1 0-80-CAT

NEe

NEe Microcomputers, Inc.

~COM-44

4-81T SINGLE CHIP MICROCOMPUTERS

DESC R I PTION

The MCOM-44 4-bit single chip microcomputers described below comprise the
medium·performance portion of the MCOM-4 Microcomputer Family. They are dis·
tinguished from other MCOM-4 products by their ROM and RAM, and their extensive
351ine I/O capability.

FEATURES.1000x8ROM
•
•
•

•
•

•
•
•
•
•
•
•
•

64 x 4 RAM
10 MS Instruction Cycle Time, Typical
58 Powerful Instructions
- Table Look·Up Capability with CZP and JPA Instructions
- Single Bit Manipulation of RAM or I/O Ports
1-Level Subroutine Stack (MPD651 has a 2-Level Stack)
Extensive I/O Capability
Two 4-Bit Input Ports
Two 4-Bit I/O Ports
Four 4-Bit Output Ports
One 3-Bit Output Port
Software Testable Interrupt
Built·ln Clock Signal Generation Circuitry
Built-In RESET Circuitry
Single Power Supply
Low Power Consumption
PMOS or CMOS Technologies
42-Pin Plastic DIP
Choice of 5 Different Products to Suit a Variety of Applications
Power

Part #

Technology

Supply

Package

"PD547

PMOS

-10V

42-pin DIP

"PD547L

PMOS

-8V

42-pin DIP

"PD552

PMOS

-10V

42-pin DIP

"PD651C

CMOS

+5V

42-pin DIP

"PD651G

CMOS

+5V

52-pin Flat
Plastic

Features

35V Vacuum Fluorescent
Display Drive

181

jLCOM-44
MCOM-44
BLOCK DIAGRAM
INSTRUCTION BUS 8 BIT

RAM

CONTROL
AND
DECODe

RAM

64x 4

8 BIT

4 BIT

110
INTERFACE

STACK 1

8 BIT

I~P0651

o
INT

1

RES

MCOM-44 PACKAGE
OUTLINES

~------------------E----------------~

ITEM

MILLIMETERS

A

56.0 MAX

2.2 MAX

B

2.6 MAX

0.1 MAX

C

2.54

0.1

D
E

0.5 + 0.1

0.02 + 0.004

50.8

F

1.5

2.0
0.059

G

3.2MIN

0.126 MIN

H
I

0.5 MIN

0.02 MIN

5.22 MAX

0.20 MAX

J

5.72 MAX

0.22 MAX

K

15.24

0.6

L

13.2

0.52

M

182

INCHES

0.3± 0.1

0.01 ± 0.004

42-PIN DIP
IlPD 547
MPD547L
MPD552
MPD651C

ONLYI

JLCOM-44
52-PIN FLAT PLASTIC
PACKAGE
pPD651G

ITEM

MILLIMETERS

A

12.0 MAX.

B

1.0' 0.1

C

14.0

0

0.4

E

21.8· 0.4

INCHES

0.47 MAX.
0.04' 0.004
O.SE

0.Q16

0.86' 0.016

F

0.15

0.006

G

2.6

0.1

!,COM-44DS-12-80-CAT

183

NOTES

184

NEe

NEe Microcomputers, Inc.

J.'PD547

4-BIT SINGLE CHIP MICROCOMPUTER
OEseR IPTION The /lPD547 is the original /lCOM-44 4-bit single chip microcomputer. It is manufactured with a standard PMOS process, allowing use of a single - 10V power supply.
The /lPD547 provides all of the hardware features of the /lCOM-44 family, and executes all 58 instructions of the /lCOM-44 instruction set.

PIN NAMES

PIN CONFIGURATION

CL,
PCo
PC,
PC2
PC3

TNT
RESET
POD
PO,
P02
P03
PEO
PE,
PE2
PE3
PFo
PF,
PF2
PF3
TEST
Vss

2
3
4

5
6
7

a

pPD
547

CLo
VGG
PB3
PB2
PB,
paO
PA3
PA2
PA,
PAO
PI2
PI,
PIO
PH3
PH2
PH,
PHO
PG3
PG2
PG,
PGo

PAO-PA3

Input Port A

PBO-PB3

Input Port a

PCO-PC3

Input/Output Port C

PDO-PD3

Input/Output Port D

PEO-PE3

Output Port E

PFO-PF3

Output Port F

PGO-PG3

Output Port G

PHO-PH3

Output Port H

PIO-PI2

Output Port I

INT

Interrupt Input

CLO-CL,

External Clock Signals

RESeT

Reset

VGG

Power Suppl y Negative

VSS

Power Supply Positive

TEST

Factory Test Pin
(Connect to VSS)

ABSOLUTE MAXIMUM Operating Temperature _ . . . . . . . . . . . _ . . . . . . . . . . . _ ...... -10°C to +70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... -40°C to +125°C
Supply Voltage . . . . . . . . . . _ . . . . . . . . . . . _ ..... _ ...... _-15 to +0.3 Volts
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Current (Ports C through I, each bit) . . . . . . . . . . . . . . . . . _ ..... -4 mA
(Total, all ports) _ . . . . . . . . . . . . . . . . . . . . . . . . _ .... -25 mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

185

JI. PD547
Ta '" _lone to +70"C' VGa '" -lOV

t

10%

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

TEST
CONDITIONS

Input Voltage High

VIH

0

-2.0

V

Ports A through D, INT,.
RESET

Input Voltage low

VIL

-4.3

VGG

V

Ports A through D. INT,
RESET

Clock Voltage High

V~H

0

Clock Voltage Low

VL

-6.0

-0.8
VGG

V
V

eLa
eLa

Input, External Clock
Input, External Clock

IUH

+10

"A

Ports A through D. INT,
RESET, VI" -1V

Input Leakage Current Low

'UL

-10

"A

RESET, VI'" -11V

Clock Input Leakage Current High

IL~H

+200

"A

GLa I nput, VIJ>H '" OV

Clock I nput Leakage Current Low

ILL

-200

"A

GLa Input, V<1>L '" -11V

Input Leakage Current High

Ports A through D. INT,

VOH,

-1.0

V

VOH2

-2.3

V

Ports C through I,
IOH=-1.0mA

Output Voltage High

Output Leakage Current Low

ILOL

SUpply Current

IGG

-30

SYMBOL

MIN

TYP

IOH '" -3.3 mA
Ports C through 1,

-10

"A

-50

mA

MAX

UNIT

VO"-l1V

CAPACITANCE

LIMITS
PARAMETER

Ports C through I,

I nput Capacitance

CI

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

Cia

15

pF

MAX

UNIT

TEST
CONDITIONS

f'" 1 MHz

AC CHARACTE R ISTICS
LIMITS
PARAMETER

SYMBOL

MIN

TYP

440

KHz

Oscillator Frequency

f

Rise and Fall Times

t r• tf

0

0,3

~,

Clock Pulse Width High

'WH

0.5

5.6

~,

Clock Pulse Width Low

t,pWL

0.5

5.6

~,

150

1------1/f-------o-.j

186

TEST
CONDITIONS

EXTERNAL CLOCK

CLOCK WAVEFORM

547DS-l0-80-CAT

NEe

NEe Microcomputers, Inc.

IJ.PD547L

4-BIT SINGLE CHIP MICROCOMPUTER
OESCR IPTION

The IlPD547L is a IlCOM·44 4·bit single chip microcomputer, manufactured with the
low power consumption PMOS process, allowing use of a single -8V power supply. The
IlPD547L provides all of the hardware features of the IlCOM·44 family, and executes
all 58 instructions of the IlCOM·44 instruction set.

PIN NAMES

PIN CONFIGURATION

CL.,

~C
~,

PC2
PC3

nqr
RESET
POO
PO,
P02
P03
PEe
PEl
PE2
PE3
PFo
16
PF, q 17
PF2[j18
PFj
19

nST

C1

w;

VSS( 21

-o..::..~

CL.C
VGG

PAO·PA3

Input Port A

~3

PBO·PB3

Input Port B

PB2
PB,
'PBC
PA3
PA2
PAl
IlPD
PAC
647L
PI2
PI,
PiC
PH3
PH2
PHl
PHO
PG3
PG2
PG,
_ _ _....=.;;. PGo

PCO,PC3

Input/Output Port C

POO·P03

Input/Output Port 0

PEO·PE3

Output Port E

PFO·PF3

Output Port F

PGO·PG3

Output Port G

PHO·PH3

Output Port H

PIO·PI2

Output Port I

iN'!'

Interrupt Input

CL.O·CL.,

External Clock Signals

RESET

Resat

VGG

Power Suppl y Negativa

VSS

Power Supply Posi tiva

TEST

Factory Test Pin
(Connect to VSS)

II

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C t<>+70°C
RATINGS· Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +126°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Output Current (Ports C through I, each bit) . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA

COMMENT: Stress above those listed under "AbSOlute MaXimum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

187

'" PD547L
DC CHARACTERISTICS
LIMITS
PARAM~TER

SYMBOL

Input Voltage High

VIH

Input Voltage Low

VIL

Glock Voltage High

V¢H

Clock Voltage Low

V¢L

Input Leakage Current High

Input LeL

·-200

"A

CLO Input, Vq>L "" -9V

-1.0

VOH,

V

=0

OV

Ports C through I,

IOH

==

-1.0mA

Output Voltage High

~_V

VOH2

Output Leakage Current Low
Supply Current

··10

'LOL

--------IGG

--15

. -25

I

Ports C through I,

IOH = -3.3 mA
Ports C through I.

"A
rnA

Va·=

-9V

--

CAPACITANCE
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Input Capacitance

CI

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

CIO

15

~

TEST
CONDITIONS

f '" 1 MHz

AC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

OscillatOr Frequency

f

Rise and Fall Times

tr,tf

0

0.3

Clock Pulse Width High

t¢WH

2.0

8.0

Clock Pulse Width Low

trpWL

2.0

B.O

100

180

UNIT

TEST
CONOITIONS

KH,

"'
"'
"'

EXTERNAL CLOCK

CLOCK WAVEFORM

541LS-l 0-80-CA T

188

NEe

NEe Microcomputers, Inc.

JLPD552

4·81T SINGLE CHIP MICROCOMPUTER
D ESC R I PTION

The .uPD552 is a .uCOM-44 4-bit single chip microcomputer with high voltage outputs
that can be pulled to -35V for direct interfacing to vacuum fluorescent displays_ The
.uPD552 is manufactured with a standard PMOS process, allowing use of a single -10V
power supply. The .uPD552 provides all of the hardware features of the .uCOM-44
family, and executes all 58 instructions of the .uCOM-44 instruction set.

PIN CONFIGURATION
PIN NAMES

Cll

PCo

PAO-PA3

Input Port A

PCl

PBO-PB3

Input Port B

PC2

PCO-PC3

Input/Output Port C

PC3

iN'f

PDO-PD3

Input/Output Port D

RESET
PDO
PDl

PEO-PE3

Output Port E

PFO-PF3

Output Port F

PD2

PGO-PG3

Output Port G

PD3

PHO-PH3

Output Port H

PIO-PI2

Output Port I

PEa
PEl
PE2

Tl\IT

1nterrupt Input

PE3

ClO-Cll

External Clock Signals

PFo
PFl

RESET

Reset

PF2

VGG

Power Supply Negative

PF3

VSS

Power Supply Positive

TEST

Factory Test Pin

TEST

Vss

ABSOLUTE MAXIMUM
RATINGS*

II

(Connect to VSS)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages (Port A, S, INT, RESET) . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (ports C through I, each bit) . . . . . . . . . . . . . . . . . . . . . . -12 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

189

I' PP552
DC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Input Voltage High

Inf:!ut Voltage Low

MIN

TVP

MAX

UNIT

TEST
CONDITIONS
PortS A through 0, INT,
RESET

V,H

0

V,Ll

-7.5

VGG

V

Ports A, 8, INT, RESET

VIL2

-7.5

-35

V

Partse,D

-3.5

Clock Voltage High

VH

0

Clock Voltage Low

VL

-6.0

V

V

CLo Input, External Clock

VGG

V

CLQ Input, External Clock

"A

RESET, V, • -1 V

"A

Ports A through D. TNT,
RESET, V, = -llV

-0.8

PortS A through D. INT,
Input Leakage Current High

'L'H

+10

Input Leakage Current Low

ILill

-10

ILIL2

-30

"A

Clock Input Leakage Current High

ILH

+200

"A

Clock Input leakage Current Low

'LL

-200

"A

Output Voltage High

-2.0

VOH

V

CLO Input, V¢l '" -11V
Ports C through I.

IOH=-SrnA
Ports C through I,

ILOLl

-10

"A

VO=-llV

ILOL2

-30

"A

Ports C through I.
Vo = -35V

-50

rnA

OUlPut Leakage Current Low

Supply Current

Ports C, 0, V I '" -35V
CLo Input, V¢H" OV

-30

IGG

CAPACITANCE
LIMITS
MAX

UNIT

Input Capacitance

C,

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

C,O

15

pF

PARAMETER

SYMBOL

MIN

TYP

TEST
CONDITIONS

f'" 1 MHz

AC CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN
150

TYP

MAX
440

Oscillator Frequency

f

Rise and Fall Times

t,.tf

0

0.3

Clock Pulse Width High

t,pWH

0.5

5.6

Clock Pulse Width low

'WL

0.5

5.6

UNIT
KHz

"'
"' .
"'

t - - - - - - 1 / 1 -------1001

190

TEST
CONDITIONS

External Clock

CLOCK WAVEFORM

66205-9-8o.CAT

ttlEC

NEe Microcomputers, Inc.

jl.PD651

4-81T SINGLE CHIP MICROCOMPUTER
OESCR IPTION

The IlPD651 is a IlCOM-44 4-bit single chip microcomputer manufactured with a
low-power-consumption CMOS process, allowing use of a single +5V power supply.
The IlPD651 provides all of the hardware features of the J.LCOM-44 family, except
that it has two subroutine stack levels to enhance software development. The J.LPD651
executes all 58 instructions of the IlCOM-44 instruction set, and it is available either in
a 42-pin Dual-in-line package (IlPD651C), or in a space-saving 52-pin Flat'package
(J.LPD651G).
PIN NAMES

PIN CONFIGURATION

Cl,
pCo
pc,
PC2
PC3

Clo

iNT

PBo
PA3
PA2
PA,
PAo
P'2
p, ,

vss
PB3
PB2
PB,

RESET

PDo
PD,
P02
P03
PEa
PE,

P'o
PH3
PH2
PH,
PHo
PG3
PG2
PG,
PGo

PE2
PE3
PFo
PF,
PF2
PFJ
TEST
VCC

ifif€i~@f£i~~

PAO-PA3

Input Port A

PBO-PB3

Input Port 8

PCO-PC3

Input/Output Port C

PDO-PD3

Input/Output Port 0

PEO-PE3

Output Port E

PFO-PF3

Output Port F

PGO-PG3

Output Port G

PHO-PH3

Output Port H

PIO·PI2

Output Port I

INT

Interrupt Input

CLO·CL,

External Clock Signals

RESET

Aeset

VCC

Power Supply Positive

VSS

Ground

TEST

Factory Test Pin
(Connect to

Vee)

NC

NC

NC

PE,
PE2

No Connection

..-

p"

/JPD651G

PA,
PA,

PEo
PD,
PD,
PD,
PDO

'"
P90

~:

ABSOLUTE MAXIMUM
RATINGS*

ff ~d~

d~f~fl~

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . .
. .. -55°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0 Volts
Input Voltages (Port A through D, INT, RESET)
-0.3 to+7.3 Volts
-0.3 to+7.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . .
Output Current (Ports C through I, each bit)
. 2.5 mA
(Total, all ports) . . . . . . . .
. . . . . . . . 28 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanant:
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions abolle those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

191

",P[)651

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

DC CHARACTERISTICS

TEST
CONDITIONS
Ports A through D. INT

Input Voltage High

V,H

0.7 Vee

Vee

V

Input Voltage low

V,L

0

0.3 Vee

V

Clock Voltage High

VH

0.7 Vee

Vee

V

CLO Input, External Clock

Clock Voltage Low

VL

0

0.3 Vee

V

CLO Input,

~A

RESET
Ports A through D. I NT

RESET

~)(ter"al

Clock

Ports A through D.INT

Input Leak.g. Currant High

ILIH

+10

I "put Leakage Current Low

ILiL

-10

~A

Ports A through 0, INT,
RESET, V, ·OV

Clock Input lalkage Current High

'LH

+200

~A

eLo Input, VH - Vee

Clock Input LNkag. Current Low

'LL

-200

~A

CLO Input. V~L· OV

RESET, V, - Vee

Ports C through I.

VOH,

Vee-o,5

V

VOH2

Vee -2.5

V

Ports C through 1,
IOH --2.0mA

Output Voltag. High

IOH --1.0mA

VOL,

+0.6

V

Portl E through I.
IOL -+2.0mA

VOL2

+0.4

V

Portl E through I.
IOL - +1.2 mA

OUtPUt Voltage Low

OUtput L.aakege Current Low

'LOL

SupplV Current

lee

-10

+0.8

+2,0

~A

Portl C. 0, Va ·OV

mA

T a --30°Cto+8S0C;VCC=+5:t 10%
LIMITS

PARAMETER

SYMBOL

MIN

TYP

150

MAX

UNIT

440

KHz

Oscillator Frequency

f

Aise and Fall Times

tr,tf

0

0.3

~S

Clock Pulse Width High

t¢WH

0.5

5.6

.S

Clock Pulse Width Low

'WL

0.5

5.6

~S

TEST
CONDITIONS

AC CHARACTERISTICS

EXTERNAL eLOeK

CLOCK WAVEFORM

1 0 4 - - - - - 1/1 - - - - - - - . l

VCC

VI/lL

VSS

LIMITS
[PARAMETER

SYMBOL

MIN

TYP

TEST
MAX

UNIT

Input Clpaclt.noe

C,

15

pF

Output Clpacitance .

eO

15

pF

I"put/Output CIPIciunce

CIO

15

pF

CAPACITANCE

CONDITIONS

I - I MHz

6510S-10-80-CAT

192

NEe

NEe Microcomputers, Inc.

J£COM-45

4-81T SINGLE CHIP MICROCOMPUTERS
DESC RIPTI ON

FEATURES

The IlCOM-45 4-bit single chip microcomputers described below comprise the
lower-performance portion of the IlCOM-4 Microcomputer Family. They are dis·
tinguished from other IlCOM-4 products by their smaller ROM and RAM, and their
reduced 21 line I/O capability.

• 1000 x 8 ROM (IlPD550 and IlPD550L have 640 x 8 ROM)
• 32 x 4 RAM
• lOlls Instruction Cycle Time, Typical
• 58 Powerful Instructions
- Table Look·Up Capability with CZP and JPA Instructions
- Single Bit Manipulation of RAM or I/O Ports
• l-Level Subroutine Stack
• Extensive I/O Calla~iI ity
- One 4-Bit Input Ports
- Two 4-Bit I/O Ports
- Two 4-Bit Output Ports
- One l-Bit Output Port
• Software Testable Interrupt
• Built·ln Clock Signal Generation Circuitry
• Built·ln RESET Circuitry
• Single Power Supply
• Low Power Consumption
• PMOS or CMOS Technologies
• 28-Pin Plastic DIP
• Choice of 5 Different Products to Suit a Variety of Applications

II

Power

Part #

Technology

Supply

Package

"PD550

PMOS

-10V

281'in DIP

"PD550L

PMOS

-8V

28-pin DIP

"PD554

PMOS

-10V

28-pin DIP

"PD554L

PMOS

-8V

28'pin

"PD652

CMOS

-15V

28-pin

Features

35V Vacuum Fluorescent
Display Drive

193

p.COM-45
J.lCOM-45

INSTRUCTION BUS 8

B~LOCK

DIAG RAM

PGo

PCO-3

PA O_3

Clo
INT

Cll

1

RES

J.lCOM-45 PACK
OUTLINE
AGE

1"-===---

0° _15 0

28-PIN DIP
J.lPD550C
J.lPD550LC
J.lPD554C
J.lPD554LC
J.lPD652C

,uCOM-45DS-128
- O-CAT

194

NEe

NEe Microcomputers, Inc.

fLPD550

4-81T SINGLE CHIP MICROCOMPUTER
OESCR IPTION The f,lPD550 is a f,lCOM-45 4-bit single chip microcomputer with high voltage outputs
that can be pulled to - 35V for direct interfacing to vacuum fluorescent displays_ The
f,lPD550 is manufactured with a standard PMOS process, allowing use of a single -10V
power supply_ The f,lPD550 provides all of the hardware features of the f,lCOM-45
family, except that it has a 640 x 8 bit ROM to reduce device cost_ The f,lPD550 executes all 58 instructions of the f,lCOM-45 instruction set_

PIN NAMES

PIN CONFIGURATION

Cll

Clo

PAO-PA3

Input Port A

PCo

VGG

PCO-PC3

Input/Output Port C

PCl

RESET

PC2

iN'f

PC3

PA3

PDO
PDl

PDO-PD3

Input/Output Port D

PEO-PE3

Output Port E

PFO-PF3

Output Port F
Output Port G

PA2

f'GO
ClO-Cll

PAl

INT

Interrupt Input

External Clock Signals

PD2

PAO

RESET

Reset

PD3

PGO

VGG

Power Suppl y Negative

PEO

PF3

Power Supply Positi ve

PEl

PF2

VSS
TEST

PE2

PFl

PE3

PFo

VSS

TEST

Factorv Test Pi n
(Connect to VSSI

II

ABSOLUTE MAXIMUM Operating Temperature_ . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10·C to +70·C
RATINGS· Storage Temparature .... _ ............. _. _ ..... _..... -40·Cto+125·C
Supply Voltage ... _ ............ __ . _ ................ -15 to +0_3 Volts
Input Voltages (Port A, iNT, RESET) ..... __ .............. -15 to +0.3 Volts
(Ports C, 0) .... _ . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . _ ............- 40 to +0.3 Volts
Output Current (Ports C, 0, each bit) .............. , ..... _ ...... -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) .. _ ... _ . . . . . . . . . . . . . . . . . . . . _. -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

195

Jl- P0550
T. - -1<>"C to +70'C; VGG ~ -10V' 10%

DC CHARACTERISTICS
LIMITS

SYMBOL

PARAMETER
Input Voltag. High
Input Voltage Low

MIN

TYP

TEST
CONDITIONS

MAX

UNIT

VIH

0

-2.b

V

Ports A, C,

VILl

-4.3

VGG

V

Ports A,INT, RESET

o,l1ilT: RESET

VIL,

-4.3

-35

V

PortIC,C

Clock Voltoga High

V~H

0

-0.6

V

CLo Input, External Clock

Clock Voltag. Low

V~L

V

CLO Input, External Clock

Input leakage Current High

ILIH

+10

~A

Port. A, C, 0, INT, RESET
VI =-1V

ILILl

-10

~A

Ports A, C, 0, INT, RESET
VI =-11V

-6.0.

VGG

Input Leakage Current Low
Clock Input Leakage Current High
Clock Input L.eakage Current L.ow
Output Voltage High

ILlL,

-30

~A

Ports C, 0, VI - -35V

Il.WH

0.5

5.6

~.

5.6

~.

'4>WL

MIN

0.5

TVP

TEST
CONDITIONS

External Qack

! - - - -__ l/f_,....-_ _ _..-I

196

CAPACITANCE

CLOCK WAVEFORM

550DS-9-80-CAT

NEe

NEe Microcomputers, Inc.

JLPD550L

4-81T SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The tlPD550L is a tlCOM-45 4-bit single chip microcomputer with high voltage outputs, and low power consumption. The outputs can be pulled to -35V for direct
interfacing to vacuum fluorescent displays. The tlPD550L is manufactured with a lowpower-consumption PMOS process, allowing use of a -8V, low current power supply.
The tlPD550L provides all of the hardware features of the tlCOM-45 family, except
that it has a 640 x 8 bit ROM to reduce device cost. The tlPD550L executes all
58 instructions of the tlCOM·45 instruction set.
PIN NAMES

PIN CONFIGURATION

Clo

PAO-PA3

Input Port A

2

VGG

PCO-PC3

Input/Output Port C

Cl,
PCo
PC,

3

RESET

PC2

4

iNT

PC3

5

PA3

POo

6

PO,

7

P02

8

P03

9

PA2

tl PD
550L

POO-P03

Input/Output Port D

PEO-PE3

Output Port E

PFO·PF3

Output Port F

PGo
ClO·Cl,

Output Port G
External Clock Signals

PAl

INT

Interrupt Input

PAo

RESET

Reset

PGo

VGG

Power Suppl y Negative

PEO

PF3

Power Supply Positi ve

PEl

PF2

VSS
TEST

PE2

PF,

PE3

PFo

VSS

TEST

Factory Test Pi n
(Connect to VSS)

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°Cto +70°C
RAT I NGS* Storage Temperature . . . . . . . . . . . . . . . . . . '.............. -40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages (Port A, iNT, RESET) ..................... -15 to +0.3 Volts
(Ports C, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3 Volts
Output Current (Ports C, 0, each bit)' ... ,. . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Ports E, f, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) ....... ; . . . . . . . . . . . . . . . . . . . . , -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions fpr extended periods may affect device
reliability.

197

p.PD550L

T a'" -lO"e to +70"C; VGG = -S.DV ± 10%

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

TEST
CONDITIONS

VIH

0

-1.6

V

Ports A, C, 0, INT, RESET

VILl

-4.5

VGG

V

Ports A, tNT, RESET

VIL2

-4.5

-35

V

PortsC,D

Clock Voltage High

V¢H

0

-0.6

V

CLO Input, External Clock

Clock Voltage Low

V¢L

-5.0

Input Voltage High
Input Voltage Low

Input Leakage Current High

VGG

CLO Input, External Clock

V

PorrsA, C, D, INT, RESET

ILiH

+10

~A

I LlLl

-10

~A

Ports A, C, D. INT, RESET
VI' -9V

VI'-lV

Input leakage Current Low

III L?

-30

~A

Ports C, D, VI ::: -35V

Clock Input Leakage Current High

IL¢H

+200

~A

CLO Input, V¢H - OV

Clock I nput leakage Current Low

IL¢L

-200

~A

VOHl

-1.0

V

Ports C, D, IOH = -2 mA

VOH2

-2.5

V

Ports E, F, G, IOH

Output Voltage High

CLO Input, V¢L '" -9V

ILOLl

-10

~A

Ports C through G,
Vo ' -9V

ILOL2

-30

~A

Ports C through G,
Vo ' -35V

-24

mA

MAX

UNIT

Output Leakage Current Low

SupplV Current

··12

IGG

'=

-10 mA

= 25°C

Ta

CAPACITANCE

LIMITS
PARAMETER

SYMBOL

MIN

TYP

Input Capacitance

CI

15

pF

Output Capacitance

Co

15

pF

I nput/OutPut Capacitance

CIO

15

pF

Ta

TEST
CONOITIONS

f= 1 MHz

= -10°C to +70o C; VGG = -S.OV ± 10%

AC CHARACTERISTICS

LIMITS
SYMBOL

MIN

MAX

UNIT

Oscillator Frequency

f

100

180

KHz

Rise and Fall Times

tr'tf

0

0.3

~,

Clock Pulse Width High

t¢WH

2.0

8.0

Clock Pulse Width Low

tW L

2.0

8.0

PARAMETER

TYP

-'

External Clock

~,

f - - - - - - l / f - - - - -.......~

198

TEST
CONDITIONS

CLOCK WAVEFORM

550'LDS·9-80·CA T

NEe

NEe Microcomputers, Inc.

Jl-PD554

4-81T SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The J,lP0554 is the standard J,lCOM-45 4·bit single chip microcomputer. with high
voltage outputs that can be'pulled to -35V for direct interfacing to vacuum fluorescent displays. The J,lP0554 is manufactured with a standard PMOS process. allowing
use of a single -1 OV power supply. The J,lP0554 provides all of the hardware features
of the J,lCOM-45 family. and executes all 58 instructions of the J,lCOM-45 instruction
set.

PIN NAMES

PIN CONFIGURATION

Input Port A

Cll

Clo

PCo

VGG

PAo-PAa
PCo,PC3

PC,

RESET

POO-P03

Input/Output Port 0

PC2

iNT

PCa

PAa

PEo·PEa
PFo·PFa

Output Port E
Output Port F

POo

PA2

PGO
INT

Output Port G

PO,

PAl

ClO·Cll

P02

PAo

RESET

POa

PGO

VGG

PEO

PF3

PEl

PF2

VSS
TEST

PE2

PF,

PE3

PFo

VSS

TEST

Input/Output Port C

Interrupt Input
External Clock Signals
Reset
Power Suppl y Negative

II

Power Supply Positi ve
Factory Test Pi n
(Connect to V55)

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10·C to +70·C
RAT I NGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40·C to +125·C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . -15 to +0.3 Volts
Input Voltages (Port A. i'N'T. RESET) . . . . . . . . . . . . . . . . . . . . .-15 to +0.3 Volts
(Ports C, 0) ......•........•..•......... -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .-40 to +0.3 Volts
Output Current (Ports C, 0, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 rnA
(Ports E, F, G, each bit) • . . . . . . . . . . . . . . . . . . . . . . . . -15 rnA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -60 rnA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damege to the davice. This is a stra.1 rating only and functional operation of tha davica 8t the.. or
any other condition. above tho .. indicated in the operational ..ctlonl of this specification is not
implied. Exposure to absolute maximum rating conditions tor axtended periods may affect davlca
reliability.

199

'" PD554
'ia = -;cfc'to +70'C' VGG = -10V·- 10%

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

Input Voltage Hleh
Input Volt. Low
"
Clock Voltage High
Clock Voltaga Low
Input L•• kagi Curront Hleh

MIN

TYp

MAli

UNIT

Clock Input Laokaga Current Low
Output Voltage High

",

0

-2.0

V

Ports A, C, D,

VILI

-4.3

VGG

V

Ports A, I NT, RESET

VIL2

-4.3

-36

Y

Portle,O

V~H

0

-0.6

V

CLO Input, External Clock

V"L

-6.0

VGG

V

CLO Input, External Clock

ILIH

+10

~A

Ports A,'C,D, iiiIT, RESET
V =~IV,

ILILI

-10

~A

Ports A, C, D, iNi', RESET
VI--l1V

ILIL2

-30

~A

Ports C, D, VI • -36V

I~H

+200

~A

CLO Input, V¢}t = OV
CLO Input, V¢L =-11V

I~L

-200

~A

VOHI

-1.0

V

Ports C, D, IOH • -2 rnA

VOH2

-2.5

V

Ports E, F, G, IOH = -10 mA

ILOLI

-10

~A

POrts C through G,
VO=-IIV

ILOL2

-30

~A

Ports C through G.
Vo =-36V

-40

mA

Output Laokage Current Low

Supply Current

-20

IGG

LIMITS
PARAMETER

SYMBOL

MIN

TVP

MAX

UNIT

Input Capacitance

CI

15

pF

Output Capacitance

Co

15,

pF

CI

15

pF

I"put/Output Capacitance

T•• -1~'C to +70'C; VGG

CAPACITANCE

f= 1 MHz

AC CHARACTERISTICS

SYMBOL

MIN

MAX

UNIT

Oscillator Frequency

f

160

440

KHz

Rlia and Fall Time.

t r• tf

0

0.3

Cloc,k Pulse Width High

'4>wH

0.5

5.6

~.

'4>W L

0.6

5.6

~.

Clock Pulse Width Low

TEST
CONDITIONS

=-10V ± 10%
LIMITS

PARAMETER

mT: RESET

VIH

Input L.akage Current Low

Clock Input Laakago Currant High

TEST
, CONDITIONS

TVP

TEST
CONDITIONS

,..

~----l/f-----'---t

External Clock

CLOCK WAVEFORM

554DS-12-80-CAT

200

NEe

NEe Microcomputers, Inc.

,.,. PD554L

4-81T SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The j.lPD554L is a j.lCOM-45 4-bit single chip microcomputer with high voltage outputs. and low power consumption_ The outputs can be pulled to -35V for direct
interfacing to vacuum fluorescent displays. The j.lPD554L is manufactured with a lowpower-consumption PMOS process, allowing use of a -8V, low current power supply.
The j.lPD554 L provides all of the hardware features of the j.lCOM-45 family, and
executes all 58 instructions of the j.lCOM-45 instruction set.

PIN NAMES

PIN CONFIGURATION

Cll

CLo

PAO-PA3

Input Port A

PCo

VGG

PCO-PC3

Input/Output Port C

RESET

POO-P03

Input/Output Port 0

PEO-PE3

Output Port E

PCt

3

PC2

4

iNT

PC3

5

PA3

POo

6

POI

7

P02

8

P03

9

PA2

j.lPD
554L

PAl
PAO

PFO-PF3

Output Port F

PGO

Output Port G
External Clock Signals

ClO-Cll
INT

Interrupt Input

RESET

Reset

PGo

VGG

Power Suppl y Negative

PEO

PF3

Power Supply Positi ve

PEl

PF2

VSS
TEST

PE2

PFI

PE3

PFo

Vss

TEST

II

Factory Test Pi n
(Connect to VSS)

ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . _ ... _ ...... -10?Cto +70°C
RATlNGS* Storage Temperature . . . . . . . . . • . . . . . . . . . _., _ .... _ .... -40°Cto+126°C
Supply Voltage .... _ ...•..... ; . . . . . . . . . . _ . _ ........ -16 to +0.3· Volts
Input Voltages (Port A, iNT, RESET) .. _ ...... _ ..... _ ..... -16 to +0.3 Volts
(Ports C, D) .....•......•........ _ ...... -40 to +0.3 Volts
Output Voltages . . . . . . . . . . . , . _ . . . . . . . . . . . . . . . . . . . . . -40 to +0.3 Volts
Output Current (Ports C, D, each bit) ....... _ .. _ . . . . . . . . . . . . . . . . -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) ........ _ . . . . . . . . . . . . . . . . . _ .. -60 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other cQnditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°C

201

f' PD554L
-

DC CHARACTERISTICS

LIMITS
PARAMETER
Input Voltage High
Input Voltage Low

SYMBOL

MIN

TYP

MAX

TEST
CONDITIONS

UNIT

'i'N"T, RESET

VIH

0

-1.6

V

Ports A, C, 0,

VILl

-4.5

VGG

V

Ports A,INT, RESET

VIL2

-4.5

-35

V

Ports C,O

Clock Voltage High

V¢H

0

-0.6

V

CLO Input, External Clock

Clock Voltage Low

V¢L

-5.0

VGG

V

CLO Inpu!, External Clock

Input Leakage Current High

IUH

+10

~A

Ports A, C, D, INT, RESET
VI ~-lV

lULl

-10

~A

III L2

-30

~A

Ports C, 0, VI"" -35V

Input Leakage Current Low

Ports A, C, D. INT, RESET
VI

~

-9V

Clock Input Leakage Current High

IL.pH

+200

~A

CLO Input, V.pH

~

OV

Clock Input Leakage Current Low

IL.pL

-200

~A

CLO Input, V¢L

~

-9V

VOHl

-1.0

V

Ports C, 0, IOH = -2 mA

VOH2

-2.5

V

Ports E, F, G,IOH = -10 rnA

ILOLl

-10

~A

Ports C through G,
Va ~ -9V

iLOL2

-30

~A

Ports C through G,
Va ~ -35V

-24

mA

Output Voltage High

Output Leakage Current Low

Supply Current

-12

IGG

CAPACITANCE

LIMITS
MAX

UNIT

Input Capacitance

CI

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

Cia

15

pF

PARAMETER

SYMBOL

MIN

TYP

SYMBOL

MIN

TYP

f

~

1 MHz

AC CHARACTERISTICS

LIMITS
PARAMETER

TEST
CONDITIONS

MAX

UNIT

Oscillator frequency

f

100

180

KHz

Rise and Fall Times

t r • tf

0

0.3

~s

Clock Pulse Width High

t.pWH

2.0

8.0

~s

Clock Pulse Width Low

t.pWL

2.0

8.0

~s

TEST
CONDITIONS

External Clock

f.4-----1/f-------I

CLOCK WAVEFORM

55.4LDS·9·80·CAT

202

NEe

NEe Microcomputers, Inc.

p.PD652

4-81T SINGLE CHIP MICROCOMPUTER
DESC R I PTI ON

The IlPD652 is a IlCOM-45 4-bit single chip microcomputer manufactured with a lowpower-consumption CMOS process, allowing use of a single +5V power supply. The
IlPD652 provides all of the hardware features of the IlCOM-45 family, and executes all
58 instructions of the IlCOM-45 instruction set.

PIN NAMES

PIN CONFIGURATION

ABSOLUTE MAXIMUM
RATI NGS*

Cl,

Clo

PAO-PA3

Input Port A

PCo

vss

PCO-PC3

Input/Output Port C

PC,

RESET

POO-P03

Input/Output Port 0

PC2

jjiji-

PEO-PE3

Output Port E

PC3

PA3

POO

PA2

PO,

PAl

PFO-PF3

Output Port F

PGO
INT

Output Port G

ClO·Cl,

External Clock Signals
Reset

Interrupt Input

P02

PAO

RESET

P03

PGO

VCC

Power Supply Positive

PEO

PF3

VSS
TEST

Power Supply Negative

PEl

PF2

PE2

PF,

PE3

PFo

VCC

TEST

Factory Test Pi n
(Connect to Vcel

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30°C to +85~C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . .
. - 55°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7.0V
Input Voltages (Ports A, C, D, INT, RESET) " . . . . . . . . . . . . . . . . -0.3 to 7.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7.3V
Output Current (Ports C through G, each bit) . . . . . . . . . . . . . . . . . . . . - 2.5 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -28.0 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

203

JI. PD652
DC CHARACTERISTS
LIMITS
PARAMETER

SYMBOL

MIN

TVP

MAX

UNIT

TEST
CONDITIONS
Ports A, C, D, INT, RESeT

Input Voltage High

V,H

0.7 Vee

VCC

V

Input Voltage Low

V,L

0

0.3 Vee

v

Ports A. C, D, INT. RESeT

Clock Voltage High

V~H

0.7 Vee

VCC

v

CLO Input, External Clock

Clock Voltage Low

V~L

0

0.3 Vee

v

CLO Input, External Clock

Input Leakage Current High

ILiH

+10

.A

Ports A, C, 0, INT. RESET,
VI'" Vee

Input Leakage Current Low

ILIL

-10

.A

Ports A, C, 0, INT, RESET,
VI'" OV

Clock Input Leakage Current High

IL¢H

+200

.A

CLO Input, V¢H '"

Vee

Clock Input Leakage Current Low

IL¢L

-200

.A

CLO Input, V¢L =

av

Output Voltage High

VOH1

Vee-a.s

V

Ports C through G, IOH - -1.0 mA

VOH2

VCC- 2 .5

V

Ports C through G, IOH - -2.0 rnA

VOll

+0.6

V

Ports E, F, G, IOL - +2.0 rnA

VOL2

+0.4

V

Ports E, F, G, 10L = +1.2 mA

Output Leakage Current Low

ILOL

-10

.A

Supply Current

ICC

+2.0

mA

Output Voltage Low

+0.8

Ports C, D, Vo

~

OV

Ta=2S"C

CAPACITANCE
LIMITS

MAX

UNIT

Input Capacitance

C,

15

pF

Output Capacitance

Co

15

pF

Input/Output Capacitance

C,O

15

pF

MAX

UNIT
kH'

PARAMETER

SVMBOL

MIN

TVP

LIMITS
PARAMETER

SYMBOL

MIN

TVP

Oscillator Frequency

f

150

440

Rise and Fall Times

tr,tf

0

0.3

Clock Pulse Width High

t.pwH

0.5

5.6

t¢WL

0.5

5.6

Clock Pulse Width Low

.,"'

.'

TEST
CONDITIONS

f= 1 MHz

TEST
CONDITIONS

External Clock

t-----1/f-----~

652DS-9-80-CAT

204

AC CHARACTERISTICS

CLOCK WAVEFORM

NEe

NEe Microcomputers, Inc.

fLPD556

EVACHIP·43
DESCR IPTION

The IlPD556 is an evaluation chip for the IlCOM-43/44/45 single chip microcomputers_
Designed to be used for both hardware and software debugging, the EVACH IP-43 is
functionally equivalent to the IlCOM-43, except that it does not contain on-chip ROM.
Instead, it is able to address external memory. In addition, in order to facilitate debugging, the IlPD556 is capable of displaying the contents of the internal accumulator and
data pointer and of being single stepped.
When the IlPD556 is being used to evaluate IlCOM-44/45 designs, the external memory
capacity should be restricted to that of the respective.on-chip ROM and the instructions
should be restricted to the 58 comprising the IlCOM-44/45 instruction set.

F EA TU R ES

• 4-bit Parallel Processor
•

Full 80 Instruction Set of IlCOM-43

•

lOlls Instruction Cycle

• Capable of addressing 2K x B-bits of external program memory
• Single step capability
•

Full Functionality of IlCOM-43

• Single supply: -10V PMOS Technology
• Available in a 64-pin Ceramic Quad-in-line Package

PIN CONFIGURATION

PIN NAMES
PFo

PF3

Output PDft F

PGo

PG3

OutPUt Po.! G

PH3

OutPut POri H

PHD
Plo

PI2

Output Port I

PAD

PA3

Input PO'! A

PBO

PB3

Input Port 8

PCO

PC3

INT

RES
POD

Input/Output Port C
Interrupt Input

Reset
P03

PEa - PEJ

InputJOutput Pon D
Output Port E

BREAK

Hold Input

STEP

Single 51ep Input

Ace/PC

Dlsplav Ace/PC Input

Po - PlO

PC OutPut
Instruction Input

'0 - 17
CLO

TEST

Cl,

External Clock Source

Tied to VSS iGNOI

205

JLPD556

BLOCK DIAGRAM
AcelPC

BREAK

PA3_0

P-$ElECTOA

RAM
96,4

I

--BREAK

I

AND
STEP
CONTROL_STEP

RAM
DECODER

PB3-0

UPI
DOWN
CDUN-

&BIT

PG3_0

CONTROL
AND
DECODE

1----.:....-1NT

~RES
~~-------------------~--------------~I

i=l
ell

CLa

-1O°Cto+70°C
-40°C to +125°C
-15 to +0.3 Vol ts
-15 to +0.3 Volts
-15 to +0.3 Volts
.... -4 mAWH

0.5

5,6

"S
"S

Clock Pulse Width Low

tQJ,WL

0.5

5.6

Input Setup Time

'IS

Input Hold Time

tlH

0

Frequency

f

Clock Rise and Fall Times

tr,tf

Clock Pulse Width High

5

"'

SR EAK to STEP Interval

tBS

80

tcy

tSB

80

tcy

STEP Pulse Width

tws

12

tcy

tBA

80

tcy
tcy

Acc Interval

ACC/PC Pu lse Width

twA

12

STEP to ACC Interval

tSAl

80

PC to STEP Overlap

tSA2

PC to RUN IntelVai

tAB

ACC/PC ...... P 1O-PO Delay

TEST
CONOITIONS

"'"S

STEP to RUN I ntelVal

BREAK to

CLOCK WAVEFORM

MIN

tcy
2

tcy

"S

0

tDAPl

6

tcy

tDAP2

6

ICy

~-----1/f ------~

- - - - - -O.BV

207

J.LPD556

TIMING WAVEFORM

>[
"Sj

Pl0-0

~"'E

(pcl

17-0

BREAK

STEP

ACC/PC

PlO-0
(Pc)n

I

•

I

J.~ ~~ ~~m ~ ~ ~ ~ ~ ~ ~l~ ~ ~ I~ ~ ~ ~ ~~

PACKAGE OUTLINE

"P0556B

(CERAMIC)
ITEM
A

MILLIMETERS
41.5

INCHE,S
1.634 MAX

B

1.05

0.042

C

2.54

0
E
F

0.5 ± 0.1

0.1
0.2 ± 0.004

G
I

39.4

1.55

1.27

0.05

5.4 MIN

0.21 MIN

2.35 MAX

0.13 MAX

J
K

24.13

0.95

19.05

0.75

L

15.9

0.626

M

0.25 ± 0.05

0.01 ± 0.002

556DS-12-80-CAT

208

NEe Microcomputers, Inc.
4-81T SINGLE CHIP MICROCOMPUTER
I

DESCRIPTION

The IlPD7502 is a IlCOM-75 4-bit single chip miCrocomputer with a 2048 x 8 ROM, a
128 x 4 RAM, a programmable 8-bit timer/event counter, and 4 vectored, prioritized
interrupts. It is also capable of directly driving a 24-segment, 3 or 4-backplane multiplexed Liquid Crystal Display (LCD). The IlPD7502 is manufactured with a lowpower-consumption CMOS process, allowing use of a single power supply between 2.7
and 5.5V, and providing programmable power-down capability. It has 23 I/O lines,
organized into one 3-bit parallel port, five 4-bit parallel ports, and one 8-bit serial port.
The IlPD7502 exesutes !J2 instructions of the IlCOM-75 instruction set, and it is avail·
able in a 64-pin plastic flat package.

FEATURES • 2048 x 8 Bit ROM
•
•
•

•
•
•

•

•
•

•
•
•
•
•
•

128x4BitRAM
15!J.s Instruction Cycle Time
92 Powerful Instructions
- ROM Data Table Look-up Capability with LHL T and LAMT Instructions
- Subroutine Address Table Look-Up Capability with CAL T Instruction
RAM Stack
4 General Purpose 4-Bit Registers (0, E, Hand L)
Extensive I/O Capability
One 3-Bit Input Port
One 4-Bit Input Port
One 4-B it Output Port
Three 4-Bit I/O Ports, of which two are 8-Bit Byte Accessible
One 8-Bit Serial I/O Port
Programmable LCD Controller
24 Segment Outputs and 4-Backplane Outputs
Can Directly Drive 3- or 4-Backplane Multiplexed LCDs
Automatic Synchronization of Segment and Backplane Signals, Transparent
to Program Execution
Programmable 8-elit Timer/Event Counter with Crystal Clock Generator
Vectored, Prioritized Interrupts
- 2 External
- 2 Internal (Timer and Serial I/O)
Programmable Power-Down Operation with HALT and STOP Instructions
Built-In System Clock Generator
Bu ilt-I n Reset Circu itry
Single Power Supply, Variable from 2.7V to 5.5V
CMOS Technology
64-Pin Plastic Flat Package

PIN CONFIGURATION

PIN NAMES
50-523

s,
s,
So

cc,
VDD

cc,

'"'"

'"

PlofLNTO

P2,

",Sn

LCD Segment Outputs
B8ckpl~n8

COMO..cOM3

LCD

POa/SI

Input Port 03/5erial Input

Outputs

P02/S0

Input Port 02/Serial Output

P01/SCK

Input Port 01/SeriaJ Clock

Pl0/INTO

Input Port 1a/lnterrupt 0

INT1

Interrupt 1

Pl0·P13

Input Port 1

P30-P33

Output Port 3

P40-P43

Input/Output Port 4

P50·P53

Input/Output Port 5

P60-P63

Input/Output Port 6

X1,X2

Crystal Clock Input, Output

Cl. C2

System Clock Input,Output

RESET

Reset

VLCD1·VLCDa

LCD Power SupplV

VOD

Power SupplV Positive

VSS

Ground

209

~

1:

P01/SCK

o

~

C
Xl

X2

CL

INTl

LCDCL

.....

en

INTO

(:)
~

x

€OUNT
CLOCK
GENERATOR

CP

I'

H (41

(Pl 011 NT 01

L(41

STACK POINTER (7)

2048 x 8 BIT ROM

INSTRUCTION
DECODER

128 x 4 BIT RAM

CL

SYSTEM
CLOCK
GENERATOR

CLl

CL 2

LCD CONTROLLER/DRIVER

STANDBY
CONTROL

OJ

r

t

VDD

t

VSS

o(")

t
RESET

LCDCL

5o-S23

COMo-COM3

VLCD1. VLCD2. VLC03

"o

»
G>
:D

»
s::

p.PD7502
FUNCTIONAL
DESCRIPTION

ROM
The pPD7502 is equipped with a 2048 x 8 bit general purpose ROM, organized as one
large, single field. It is accessible anywhere between addresses OOOH and 7FFH by the
Program Counter. Several portions of the ROM are reserved for special operations, as
follows:
Address

Function

OOOH

Program start address after RESET
Input

010H

Timer/Counter Interrupt (INTT)
Start Address

020H

Serial Interface or External Interrupt
(lNTO/S) Start Address

030H

External Interrupt (I NT 1) Start
Address

OCOH - OCFH

LHL T Instruction Reference Table

ODOH -OFFH

CAL T Instruction Reference Table

These ROM addresses can be used for other purposes if these features are not used.
RAM
The pPD7502 is equipped with a 128 x 4 bit general purpose RAM. It is accessible
between addressed DOH and 7FH by Direct Addressing with immediate data, by
Register Pair Indirect Addressing, or by Stack Pointer Addressing. Two portions of
the RAM are reserved for special operations, as follows:
Address

Function

DOH - 17H

LCD Segment Data

(Definable by
Stack Pointer)

LI F a Stack Address Storage

In addition, there are four general purpose 4-bit registers, D, E, H, and L, which may
be used individually, or as register pairs DE, DL, or HL, during program execution.
Clocks
The pPD7502 can accept two different clock signals. Pins CL 1 and CL2 can accept a
simple RC input for the system clock. Pins X1 and X2 can accept a more accurate'
crystal, such as 32.768 kHz, for timer/event counter functions where clock accuracy
is important to the application.
Timer/Event Counter
The timer of the pPD7502 is an 8-bit Binary-Up counter. It is reset during execution
of RESET, or the "Timer" instruction. During operation, the count register of the
timer is incremented until it coincides with the value of the modulus register. At this
point, the timer interrupt INTT becomes active, the count register is reset, and counting begins again_ The count register can also be read at any time by executing the
"TCNTAM" instruction_
The Event Counter of the IlPD7502 takes advantage of the Timer capabilities to
measure external pulses occurring on pin X 1.

211

J.L PD7502
FUNCTIONAL
DESCR I PTI ON
(CaNT.)

Interrupts
There are four interrupts available on the pPD7502. Two of them are generated
externally (INTl and INTO), and two of them are generated internally (Timer
interrupt INTT, and SIO interrupt INTS).
Under software control, the four interrupts can be prioritized in any order. They
can be controlled individually, or under a master control.
Stack Pointer
The Stack Pointer is a 7-bit register containing the leading address information of
the LI Fa stack, located in RAM. The Stack Pointer is decremented when CALL,
CALT, PSHDE, or PSHHL instructions are executed, and incremented when RT,
RTS, TRPSW, POPDE, or POPHL instructions are executed.
The Stack Pointer can be accessed by executing the TAMSP or TSPAM instructions.·
Serial I/O
The Serial I/O port of the pPD7502 consists of an 8-bi\shift register, a 4-bit shift
mode register, and a 3-bit counter. Data Is output at the fall of the serial clock, with
the MSB transferring first: Serial data input at the rise of the serial clock, with the MSB
transferring first. The serial clock SCK can be selected under software control from the
internal system clock, an external clock signal, or the Timer-Out F/F.
The TSIOAM and TAMSIO instructions facilitate the I/O operations of the pPD7502
SIO port. These instructions make it easy for the pPD7502 to handle odd-sized data
containing parity, start or stop bits.
LCD Controller
When direct LCD drive is required for an application, a portion of the RAM mu(st be
reserved for LCD segment data storage. This segment data is decoded by ROM table
look-up instructions during program execution.
It must then be stored in the RAM, for direct access by the LCD Controller Hardware
according to the following pattern:

COMO
COM,

COMa

A;DAA~SS

OOH

OlH

02H

03H

04H

05H

06H

07H

08H

091'i

OAH

OSH

DCH

OOH

oeH

OFH

10H

llH

12H

13H

t4H

15H

16H

17H

For applications using 3-backplane multiplexed LCDs, the third bit of each RAM location is not used, and it may be used for other general purpose storage.
Actual determination of functioning of the LCD Controller occurs when the Display
Mode Register is set.

212

fLPD7502
INSTRUCTION SET
SYMBOL DEFINITIONS

The following abbreviations are used in the description of the IlPD7502
SYMBOL
A

EXPLANATION AND USE
Accumulator

address

Immediate address
Bit "n" of Accumulator

An

Carry Flag

C
data

I mmediate data

D

Register D

DE

Register Pair DE

DL

Register Pair DL

Dn

Bit "n" of immediate data or immediate address

E

Register E

H

Register H

HL

Register pair H L

IER

Interrupt Enable Register

IME

Interrupt Master Enable F/F

INT n

Interrupt "n"

L
P(

Register L
)

Parallel Input/Output Port addressed by the value within the brackets

PC n

Bit "n" of Program Counter

PSW

Program Status Word

rp

Register Pair, selected by 3 bits of immediate data, D2-0, as follows:
rp

0201 DO

RQF

0
0

0
0

0

1
1

0
0

0
1

DL
DE
HLHL+

1

1

0

HL

1

Additional Action
none

none
decrement L; skip if L; FH
increment L; skip if L; OH
none

Request Flag
Number of bytes in next instruction when skip condition occurs

S

Serial I/O Shift Register

SIO
SIOCR
SP

Serial I/O Count Register
Stack Pointer

TCR

Time Count Register

TMR
)

Timer Modulo Register
The contents of RAM addressed by the value within the brackets

1

The contents of ROM addressed by the value within the brackets

(

[
<~

-

Load, Store, or Transfer
Exchange
Complement

1\

LOGICAL AND

V

LOGICALOR

V

LOGICAL Exclusive OR

213

Jl.PD7502
INSTRUCTION SET
FUNCTION

MNEMONIC

DESCRIPTION

I
I 07 I

Os

I

INSTRUCTION CODe

05

LOAD

LAI data

A +--03_0

load A with 4 bits of

0

0

immediate data 1
LOI datil

LEI data

LHI data

LLI data

LAMrp

0 ..... °3·0
E ...... 03_0

H ...... 03_0

L ...... 03_0

A-(rp)

Load 0 with 4 bits ot
immediate data

0
0

0
0

Load E with 4 bits of

immediate data

0
0

0
0

Load H with 4 bits of
immediate data

0
0

0
0

Load L with 4 bits of

immediate data

0
0

0
0

Load A with the RAM con-

0

,

LOEI data

A-IDS.OI

DE ..... 07.0

LH l T address

HL ...... 07.0

I

03

I

02

I

0,

0

,
, , , ,
,
,
,,
,
,, , , ,

0

02

0

,,
,
,,
,
0

I

Do

I
I BYTES

CYCLES

SKIP
CONDITION

String

03

02

0,

DO

,

,

0

2

2

0

D3

02

0,

DO

1
03

2

02

1
0,

2

0

DO

1
03

1
0,

2

2

02

DO

0

2

2

03

02

0,

DO

0

0

0,

DO

,

1+S

Load A with the RAM contents addr~ssed by 7 bits of
immediate data

0
0

0

, ,

Os

05

D.

Load DE with 8 bits of

0
07

Os

0
0

0
05

D.

03

0

1
03

0
02

0
0,

0

2

2

Load H L with 8 bits of

0

immediate data 2

07

Os

0
05

D.

1
03

1
02

0,

DO

1

0

0

03

02

0,

DO

1

2

,

0

, , , ,

0

,

2

0

1

, , ,

,

,

,
, ,,
,,
, ,,

0
0

2

2

0

1
0

H -- [f0001 100D3.0tl H

Load the upper 4 bits of ROM

l - [tOOO1100D3.()t] L

000110003_0 to H;
Load the lower 4 bits of ROM

See explanation

DO

,
,

immediate data
LHLt data

04

of "rp" in
symbol definitions

tents addressed by the
register pair selected by
3 bits of immediate data
LADR address

I

,

0

, , ,
,

2

0,

1
DO

2

02

0

2

2

String

Table Oats at address

Table Data at address
OOOUOOD3-O to L 3

lAMT

A -- (tPClO-{),O,C.At ) H

(HL) -- [tPC1O-6.0,C,At) L

Load the upper 4 bits of ROM
Table Data at address
PClO-6.0,C,A to A;

0

String

Load the lower 4 bits of ROM

Table Data at address
PC10-6.0,C,A to the RAM
location addressed by Hl
STORE
ST

IHL)- A

Store A into the RAM location

0

,

0

addressed by H L

TRANSFER
TAD
TAE

D-A
E-A

Transfer A to 0
Transfer A to E

,
,

0
0

0
0

0
0

TAH

H-A

Transfer A to H

0
1

0
0

TAL

L-A

Transfer A to l

0

,
,

0

TDA

A-D

Transfer 0 to A

0

Transfer E to A

0

Transfer H to A

0
1

0

,

0
0

Transfer L to A

0

2

2

0

0

1

1
1

1
0

0
0

2

2

0
0

2

2

0

0

2

2

0

2

2

0

2

2

0

2

2

1

,
,
,

1
1

A-H

0
0
0

1

1
0

1

1

0

0

1
1

0

1

1
1

,, ,
, ,
, ,, ,
0
, , ,
1
0

0

EXCHANGE

214

1

0

0
0

A-E

A-L

1

1

0

0

1
0

TEA

TLA

0

0

THA

1

, , ,,
, , ,
,,
,
,, ,
,
, , ,
,,
,
,
,,

1

XAD

A"D

Exchange A with 0

0

XAE

A<-, E

Exchange A with E

0

XAH

A-H

Exchange A with H

0

XAL

A-L

Exchange A with l

0

,
,
,
,
, , ,
, ,
1

1

XAMrp

A_lrp)

Exchange A with the RAM
contents addressed by the
register pair selected by
3 bits of immediate data

0

1

0

0

0

0

0

0

0

1

02

0

0
0

,

1

1

,
, ,
,
, ,
0

0

0,

DO

,
,
,
,

,

1 +S

See explanation
of "rp" in
symbol definitions

pPD7502

INSTRUCTION SET
(CaNT.)
MNEMONIC
XAOR address

DESCRIPTION

FUNCTION
A~ 106.01

D7

Exchange A with the RAM

contents addressed by

I

D6

I

INSTRUCTION CODE
DS

I

D4

I D3 I D2 I Dl I

DO

BYTES

CYCLES

0
0

0
06

·1
D5

1
D4

1
D3

0
02

0
01

1
DO

2

2

0
0

0
06

1
05

1
04

1
03

0
02

1
01

0
DO

2

2

0
0

0

1
05

1
04

1
03

0
02

1
01

1
DO

2

2

Os

SKIP
CONDITION

7 bits of immediate data
XHDR address

H ~ 106.01

Exchange H with the RAM

contents addressed by 7 bits
of immediate data
X LOR address

L~ 106.01

Exchange L with the RAM

contents addressed by 7 bits

of immediate data
ARITHMETIC
AISC data

ASC

A +- A + 03.0

Add 4 bits of immediate data to

Skip if overflow

A; Skip if overflow occurs

A+-A + (HL)
Skip if overflow

Add the RAM contents
addressed by HL to A: skip if

0

0

0

0

03

02

01

DO

1

1+S

Overflow'" 1

0

1

1

1

1

I

0

1

1

1+S

Overflow'" 1

0

1

1

1

1

1

0

0

1

I+S

Carry Flag"" 1

overflow occurs

ACSC

A. C-A+ (HLI + C
Skip if carry

Add the RAM contents
addressed by H L and the carry
flag to A; skip if carry is

generated
LOGICAL
EXL

A-A>,. tf$

System Clock Pulse Width

tOWH

23

50

tow

40

50

Count Clock Frequency

Count Clock Pulse Rise and
Fall Times
Count Clock Pulse Width

SC'K Cycle

SCi<. Pulse Width

"f XExt

0.2

"'
"'

External Clock

Crystal Oscillator

kH,

External Pulse Input

"'

External Clock

"'

External Pulse Input

txWL

23
4.0

tCYK

"'

6.0

tKWH

1.8

tKwL

3.0

51 Hold Time

"H

450

SO Delay Time

too

tl,wH

~
tRWH

~

~

2%

SCi<.

VOO - 5V

i

10%

Input
VOD"3V±10%
Voo - 5v t 10%

"'

SCK Input

VOO"3V' 10%
VOO - 5V ± 10%
VOo '" 5V , 10%

850

~

5%, R = 240 kn

Voo = 5V • 10%

kH,

23

!

± 10%

External Clock "'V-=-O=-O-=""2C";.7c:'=-O""5"".5"V------I

50

t rx • tfx

33 pF

]VOO-3V±lO%

200
0.2

eo

LVOO - 5V

External Clock

32

txWH

tlOWH

"DO - 2.7 to 5.5V, C

kH,

32

300

Reset Pu!se Width

kH'

25

'I.

I NT 1 Pulse Width

Voo '" 5V ± 10%, C - 33 pF ± 5%, R - 160 kn • 2%

DC

51 Setup Time

INTO Pulse Width

CONOITIONS

UNITS

Voo" 5V :'- 10%

10

Voo '" 5V ± 10%

10

Voo '" 5V ' 10%

10

/.lS

VOO "5V ± 10%

CAPACITANCE
PARAMETER

LIMITS

SYMBOL
MIN

UNITS
TYP

CONDITIONS

MAX

Input Capacitance

C,

20

pF

Output Capacitance

Co

20

pF

C¢

20

pF

System Clock

Capacitance

219

I-' PD7502
TIMING WAVEFORMS
VDD
SYSTEM
CLOCK (eL,)

V¢H

If,

COUNT CLOCK (Xl)

SERIAL CLOCK (SCKJ

SERIAllNPur (51)

SERIAL OUTPUT (SO)

220

I.---_X~_

p.PD7502
PACKAGE
DIMENSIONS
IlPD7502G

II

7502DS·12·80·CAT

221

NOTES

222

NEe Microcomputers, Inc.
4-81T SINGLE CHIP MICROCOMPUTER
DESCRIPTION

The IlPD7503 is a IlCOM-75 4-bit single chip microcomputer with a 4096 x 8 ROM, a
224 x 4 RAM, a programmable 8-bit timer/event counter, and 4 vectored, prioritized
interrupts. It is also capable of directly driving a 24-segment, 3 or 4-backplane multiplexed Liquid Crystal Display (LCD). The IlPD7503 is manufactured with a lowpower-consumption CMOS process, allowing use of a single power supply between
2.7V and 5.5V, and providing programmable power-down capability. It has 23 I/O
lines, organized into one 3-bit parallel port, five 4-bit parallel ports, and one 8-bit serial
port. The IlPD7503 executes 92 instructions of the IlCOM-75 instruction set, and it is
available in a 64-pin plastic flat package.

FEATURES • 4096 x 8 Bit ROM
• 224 x 4 Bit RAM
• 151ls Instruction Cycle Time
• 92 Powerful Instructions
- Table Look-up Capability with LHLT and LAMTL instructions
- Indirect indexed addressing with CALT instruction
• RAM Stack
• Extensive I/O Capability
One 3-Bit Input Port
One 4-Bit Input Port
One 4-Bit Output Port
Three 4-Bit I/O Ports, of which two are 8-Bit Byte Accessible
One 8-Bit Serial I/O Port
• Programmable LCD Controller
24 Segment Outputs and 4-Backplane Outputs
Can Directly Drive 3- or 4-Backplane Multiplexed LCDs
Automatic Synchronization of Segment and Backplane
Signals, Transparent to Program Execution
• Programmable 8-Bit Timer/Event Counter with Crystal Clock Generator
• Vectored, Prioritized Interrupts
- 2 External
- 2 Internal (Timer and Serial I/O)
• Programmable Power-Down Operation with HALT and STOP Instructions
• Built-In System Clock Generator
• Built-In Reset Circuitry
• Single Power Supply, Variable from 2.7V to 5.5V
• 'CMOS Technology
• 64-Pin Plastic Flat Package
PIN NAMES

PIN CONFIGURATION

s,

'"
s"

s,

S,

COMO

INT,

COM1

50-523

LCD Segment Outputs

COMO-COM3

LCD Bltek,;!I,", Outputs

PO,/SCK

Input Port O,/seri.' Clock

P02/S0

Input Port 02/Serl" Output

POa/SI

Input Port OJ/Storiai Input

Pl0llNTo

In.,lIt Port 'o/lnt.r,upi 0

P10.p13

Input PorI 1

P30-P33

Output Port 3

voo

P40·P43

Input/Output Port 4

VL.CD,

P50·P53

Input/Output Port !i

'So",,"

Input/OutpuI Port 6

COM2

ce,
Voo

ce,

.'",

'"
'"

P'O'INTO

o

IlPD7503

o

COM3

VLC02

o

VLC03

Vss

x,
x,

INT,

Int.r~ptl

X,. X2

Cry.tIIl Clock l!\pllt. Outpt,lt

C,.C2

System Clock Input, O"lput

RESET

R ...,

VLCD"VLCDa

Lep POMr Supply

VDD

Power Supply Potlti\llt

VSS

Ground

NC

No (:onn.ctlon

223

JLPD~503
BLOCK DIAGRAM

vaD

COMO-COM3

Vss

VLCD1, VLCD2. VLCD3

The .u PD7503 executes the identical instruction set of the ~P07502, with only two exceptions. First, all instructions referencing the

I NST RUCT ION SET

11·bit Program Counter PC10.o of the .uPQ7502 will now refer to the 12-bit Program Counter PC11-O of the ~PD7503. Second, the

LAMTL instruction below replaC8$ the .u PD7502 LAMT instruction.
INSTRUCTION CODE
MNEMONIC

FUNCTION

DESCRIPTION

07

06

05

04 03

02

D1

DO

BYTES

CVLCES

SKIP
CONDITION

LOAD
LAMTL

Load the upper 4 bits of ROM

Table Data at address
PClO-8,A,(HLl to A;
IHLJ +-[PC10-8.A,IHLlJL

0

0

° °

1

1

1

° °

Load the lower 4 bits 01 ROM
Table Data at address
PClO-8,A,(HLI to the RAM
location addressed by HL

PACKAGE OUTLINE
J,LPD7503G

t=

1,0 TYP

o

TTTTTTITr"1T1Tl~~

0.4 TYP

t=

o

hrrnnn°

".0""
20.0""

~r=C Q~
'''"A<
224

L

Q

a

a

~ ~ ~
a

a

a

2M'0.<

~ ~ ~ ~ ~ ~ ~JI

=====.:J
..

Q

a

a a

Q

a

a

h

.I
7503DS-l0-80-CAT

NEe

NEe Microcomputers, Inc.

pPD7507

~rn~[~~~~ffirnW
4-81T SINGLE CHIP MICROCOMPUTER
DESCR I PTI ON

FEATURES

The I1PD7507 is a I1COM-75 4-bit single chip microcomputer with a 2048 x 8 ROM,
a 128 x 4 RAM, a programmable 8-bit timer/event counter, and 4 vectored, prioritized
interrupts_ The I1PD7507 is manufactured with a low power consumption CMOS
process, allowing use of a single power supply between 2_7V and 5_5V, and providing
programmable power-down capability _ It has 32 I/O lines, organized into eight 4-bit
parallel ports and one 8-bit serial port_ The I1PD7507 executes 92 instructions of the
I1COM-75 instruction set, and it is available in a 40 pin dual-in-line package_

• 2048 x 8 Bit ROM
•
•
•

•
•

•
•

•
•
•
•
•
•

12Bx4 Bit RAM
lOlls Instruction Cycle Time
92 Powerful Instructions
- Table Look-Up Capability with LHLT and LAMTL Instructions
- Indirect I ndexed Addressing with CALT Instruction
RAM Stack
Extensive I/O Capability
One 4-Bit I nput Port
Two 4-Bit Output Ports
Four 4-Bit I/O Ports, of which two are 8-Bit Byte Accessible
One 4-Bit I/O Port with Output Strobe
One 8-Bit Serial I/O Port
Programmable 8-Bit Timer/Event Counter with Crystal Clock Generator
Vectored, Prioritized Interrupts
- 2 External
- 2 I nternal (Timer and Serial I/O)
Programmable Power-Down Operation with HALT and STOP Instructions
Built-In System Clock Generator
Built-In Reset Circuitry
Single Power Supply, Variable from 2_7V to 5_5V
CMOS Technology
40-Pin Dual-In-Line Package

II

PIN NAMES

PIN CONFIGURATION

X2

P20/STB
P2l/TOUT
P22
P23
Plo
Pll
P12
P13
P30
P3l
P32
P33
P70
P7l
P72
P73
RESET
CLl
Vao

Xl
VSS
P43
P42
P4l
P40
P53
P52
P5l
P50
P63
P62
P6l
P60
P03/S1
P02/S0
P01/SCK
POO/INTO
INTl
CL2

POO/INTO

Input Port Do/Interrupt a

POl/SCi<

Input Port 01/Serial Clock

P02/S0

Input Port 02/Serial Output

P03/SI

Input Port 03/Serial Input

PIO-P13

Input/Output Port 1

P20/STB

Output Port 2a/Port 1 Strobe Output

P21/TOUT

Output Port 21 {Timer Output

P20-P23

Output Port 2

P30-P33

Output Port 3

P40-P43

Input/Output Port 4

P50-P53

Input/Output Port 5

P60-P63

Input/Output Port 6

P70-P73

Input/Output Port 7

INTI

Interrupt 1

C1. C2

System Clock Input, Output

Xl,X2

Crystal Clock Input, Output

RESET

Reset

Vee
Vss

Power Supply Positive
Ground

225

p.PD7507
BLOCK DIAGRAM

cc,

cc,

Voo

Vss

The !,PD7507 executes the identical instruction set of the !,PD7502, with the sole exception being
that·the LAMTL instruction below replaces the !,PD7502 LAMT instruction.
INSTRUCTION CODE
MNEMONIC

FUNCTION

DESCRIPTION

D7 De

Dli 04 03 02 0,

LOAD

\...AMTL

A-

(PC10_a.A.IHLlI H

(HLI- {PC10-8.A.(HL.)J L

Load 1he upper 4 bIts of ROM
Table Data at address
PC1O-S.A.(HU to A;

0
0

0
0

DO BYTES

INSTRUCTION SET

SKIP
CONDITION

CYLCES

,

,
1

o

1

0

0

Load the lower 4 bits of ROM
Tllble Data 111 address

PC, O-a.A,IHU to the RAM
location addressed by H L

I

. .

-!

I

A

~

~

~
I J ----- ..J..
.
loll'
I
G '
.

-B~~

PACKAGE OUTUNE
.PD7507C

0°_15°-1----

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

8

1.62

C

2.54 ± 0.1
0.5 ± 0.1

0
E

48.26

INCHES
2.028 MAX
0.064
0.10 ± 0.004
0.019 ± 0.004

F

1.2MIN

1.9
0.047 MIN

G

2.54 MIN
0.5MIN

0.10MIN
0.019 MIN
0.206 MAX

K

5.22 MAX
5.72 MAX
15.24

L

13.2

0.520

H

I
J

M

0.25

0.225 MAX
0.600

+ 0.1
0.05

0.010

+ 0.004

0.002

7507DS·10-80-CAT

226

NEe

NEe Microcomputers, Inc.

,.,.PD7520

4-BIT SINGLE CHIP MICROCOMPUTER
DESCR I PTION

FEATU RES

The j.lPD7520 is a IlCOM-75 4-bit single chip microcomputer with a Programmable
Display Controller capable of directly driving a multiplexed 8-segment, 8-digit LED
Display. It has a 768 x 8 ROM, a 48 x 4 RAM, and 24 I/O lines for communication
with and control of external circuitry. The j.lPD7520 is manufactured with a lowpower consumption PMOS process, allowing use of a single power supply between
-6V and -10V. The j.lPD7520 executes 47 instructions of the j.lCOM-75 instruction
set, and is available in a low-cost 28-pin plastic dual-in-line package.

• 768 x 8 Bit ROM
•
•
•
•
•
•
•
•

•
•
•
•
•
•

PIN CONFIGURATION

48 x 4 Bit RAM
20 j.lS Instruction Cycle Time, Typical
47 Powerful Instructions
- Table Look-Up Capability with LAMT Instruction
2-Level Subroutine Stack
One 4-Bit Input Port
One 4-Bit I/O Port
One 2-Bit Output Port (Capable of Driving Piezo Element)
Programmable Display Controller
- 6 LED Direct Digit Drive Outputs (8 Possible Using P40-1)
8 LED Direct Segment Drive Outputs
Selection of a 4, 5, 6, or 8-Digit Display Strobe Cycle
Can Directly Drive 8-Segment, Multiplexed Displays,
or up to an 8 x 8 Dot Matrix
Automatic Synchronization of Segment and Digit Signals,
Transparent to Program Execution
- Segment Outputs also Function as Latched, 8-Bit Parallel Output Port
Built-In Clock Signal Generation Circuitry
Built-In Reset Circuitry
Single Power Supply, Variable from -6V to -10V
Low Power Consumption: 45 mW, Typical
P-Channel MOS Technology
28-Pin Plastic Dip

P31

ClK

P30

RESET

P13

VGG

P12

So

P11

S4

P10

PIN NAMES
So -S7

Segment Drive
Output Port S

TO-T5

Digit Drive
Output Port T

S1

P10 - P13

Input Port 1

P43

S5

P30 - P3 1

Output Port 3

P42

S2

P41

S6

P40

S3

T5

S7

T4

TO

T3

T1

VSS

T2

II

P4 0 - P43

Input/Output Port 4

ClK

Clock Input

RESET

Reset

VGG

Power Supply
Negative

VSS

Ground

227

OCCHARACTERISTICS

~PD7520

Ta = -10·C to +70·C, VGG· -6V 10 -10V

PARAMETER

SYMBOL

Input Voltage
High

VIH

Input Voltage
Low

VIL

Clock Voltage
High

VH

Clock Voltage
Low

VL

I nput Current
High

IIH

Input Leakage
Current High

ILiH

I nput Leakage
Current Low
Clock Current
High

IH

Clock Current
Low

IL

LIMITS
MIN

TYP

MAX
-2

V

TEST CONDITIONS

Ports 1,4, RESET

VGGH.S

V

VGG+O.8

-OB

VGG =-9V ± lV
VGG --6V to-l0V

-1.8
Ports 1,4, RESET

VGG=-9V±lV
VGG =-6V to-l0V

V

CLK, External Clock

V

CLK, External Clock

jJA

Port 1, RESET

+S

jJA

Port 4, VI = OV

ILILl

-S

jJA

Port 1, RESET, VI =-10V, VGG =-10V

ILlL2

-S

jJA

Port 4, VI =-10V

0.5

mA

ClK, External Clock, V.pH = OV,
VGG =-9V ± lV

-2.1

mA

Output Voltage
Low

VOL

Output Current
High

IOHl

-S.o
4S

200

40

200

V

VGG+O.5
-1.0
-0.6

-2.0
IOH2

IOH3

IOH4

Output Current
l.9w
lOLl

-1.2
-S

-10

-3

-6

-1

-3

-24

-48

-13
-9

-27

LVI

=ov, VGG =-9V ± lV

I VI - OV, VGG - -6V to -10V

ClK, External Clock, V.pL =-SV,
VGG --9V ± lV
Port 3, No load

mA

Port 3,'

mA

Port 4,

mA

Port S,

Vo =-LOV, VGG =-9V ± lV
Vo --1.0V, VGG --6V
VO=-1.0V,VGG=-9V± lV
Vo --LOV. VGG --6V
Vo =-2.0V, VGG =-9V ± lV
Vo --2.0V, VGG =-6V
Vo =-1.0V, VGG· -6V to -10V
Vo =-2.0V, VGG =-9V ± lV

mA

Port i"

Vo =-1.0V, VGG =-9V ± lV
VO--l.0V,VGG

-18

1

2

Vo = VGG + 1.SV, VGG =-9V ± lV

02

0.3

0.6

Vo VGG +3.SV, VGG =-9V ± lV
VO= ':'4.5V, VGG = -6V

0.1

02

mA

9

CD

VO· VGG +5.0V, VGG =-9V ± lV
PortS,

2

Vo = VGG + 3.5V, VGG =-6V to -10V'

ILOH

+5

jJA

Ports 4, TL.YO =OV

Output Leekage
Current' Low

ILOL

-5

jJA

Ports 4, T, Vo =-10V

Supply Current

IGG·

~.8

mA

Te = 25·C. VGG = -9V, No Load

G>

-S

Q)

Vo - -2.5V, VGG - -6V

mA
1

Port 3,

Output Leakage
Current High

Note:

>----------1

CLOCK WAVEFORM

VSS

V¢L

VGG1-~::~~------------~::::::::~-------The NEC Microcomputers' NDS Development System is available for the development of software source code, edi'ting, and assembly into object code_ In addition,
the ASM-75 Cross Assembler is available for systems supporting the ISIS-II (TM
Intel Corp.) OpErating System, and the CASM-75 Cross Assembler is available for
systems supporting the CP/M (® Digital Research Corp.) Operating System,
The EVAKIT-7520 Evaluation Board is available for production device evaluation
and prototype sY$tem debugginq_

230

DEVE LOPMENT TOO LS

J.LPD7520
Clock and Reset Circuitry
The Clock Circuitry for the J.1PD7520 can be implemented by connecting a resistor
from the ClK input to VGG. The Power-On-Reset Circuitry for the J.1PD7520 can be
implemented by connecting a capacitor from the RESET input to VSS.
I/O Capability
The J.1PD7520 has 24 I/O lines for communication with and control of external circuitry_ The Port configuration is selectable under software control via the Mode
Select Register as follows:
Port 1

P1O-3

4-Bit Schmidt Input

Port 2

P2O-1

2-Bit latched Output Option, Accessible through

Port 3

P3O-1

2-B it latched Output

Port 4

P4O-3

4-B it Input/latched Output

Port S

SO-7

latched 8-Bit Parallel/Segment Drive Output

TO-5

6-Bit High-Current/Digit Drive Output

T6-7

Additional 2-Bit Digit Drive Output Option, Accessible
through Port 4 (P40-1)

Port T (T4-5)

Port T

DISPLAY CONTROLLER
BLOCK DIAGRAM

So-7

TO-S
(TO-3. P20_11

231

fLPD7520
The uisplay Controller is the major feature of the pPD7520. It automatically per·
forms scan or display strobe operations which would otherwise require considerable
software.

DISPLAY
CONTROLLER

The Oisplay Controller interfaces to a common-anode LED display without external
components. Connections from the uisplay Controller to the display are made from
Port S to the cathodes (segments), and from Port T to the anodes (digit enables).
Up to 6 digits can be driven directly by the pPD7520 in this manner. A total of 8
digit drives are available by using the two digit drives accessible through Port 40-1, and
adding only two small driver transistors and four resistors externally. When Port T 4-5
is not used to drive a display, it may be used as a high current driver, accessible
through Port 20-1.
During operation, a 3-to-8 decoder selects which digit of a Display Buffer in the
RAM will be mUltiplexed onto the display. The contents of the pair of RAM locations,
corresponding to the digit chosen from the Display Buffer, are transferred to the 8
latched outputs of Port S, and the corresponding Port T digit drive is enabled. After
13 machine cycles have been completed, the digit drive is disabled, the decoder is
updated to select the next digit of the Display Buffer to be multiplexed onto the display, and this cycle is repeated. Thus, the pPD7520 program needs only to load the
properly decoded display data into the Display Buffer and it immediately appears
on the display. Operation in this manner is completely transparent to the pPD7520,
and requires no intervention once the proper display mode has been selected.
The use of a Mode Select Register enhances the utility of the Display Controller by
allowing a choice of a 4, 5, 6, or 8 digit display strobe cycle output, or a direct latched
output. A choice can also be made between one of the two possible Display Buffers,
resident in either Row 0 or Row 2 of the RAM.
The Mode Select Register (MSR) is a separate 4-bit register of the Display Controller
which determines the function that the Display Controller will perform. The value of
the MSR can range from 016 to F 16, and it can be modified by data in the Accumulator. This is accomplished by execution of the OPL (output-to-port) instruction,
where L (the lower 4-bits of the data pointer) is set to the value B16 in order to
address the MSR. Execution of this instruction transfers the contents of the Accumulator into the MSR, and the Display Controller begins operating according to the
following table:
M3

M2

M,

MO

0

0

0

0

Reset (SO-7: High level); (TO-5: OFF)

0

0

0

1

8-bit parallel output: SO-3 .... (OEH); S4-7 .... (OFH); (TO-3: OFF)

0

0

1

0

Not used

0

0

1

1

Not used

0

1

0

0

4.<:Jigit display (TO-3); Segment data: OOH-D7H
5.<:Jigit display (TO-4); Segment data: 00H-D9H

DISPLAY CONTROLLER OPERATION

0

1

0

1

0

1

1

0

6.<:Jigit display (TO-5); Segment data: OOH-DBH

0

1

1

1

8.<:Jigit display (TO.7.); Segment data: OOH-OFH

1

0

0

0

Not used

1

0

0

1

8-bit parallel output: SO-3 .... (2EH); S4-7 .... (2FH); (TO-3: O'FF)

1

0

1

0

Not used

1

0

1

1

Not used

1

1

0

0

4.<:Jigit display (TO-3); Segment data: 20H-27H

1

1

0

1

5.<:Jigit display (TO-4); Segment data: 20H-29H

1

1

1

0

6.<:Jigit display (TO.51; Segment data: 20H-2BH

1

1

1

1

8.<:Jigit display (TO.7); Segment data: 20H-2FH

The MSB, M3, of the Mode Select Register defines the Row of RAM (0 or 2) to be
used for the Display Buffer and M2 distinguishes between a digit strobe cycle output,
or a direct Iatched output.
232

MODE SELECT REGISTER

I.l PD7520

I NSTR UCTION SET The following abbreviations are used in the description of the ).lPD7G20 instruction set:
SYMBOL DEFINITIONS
SYMBOL
EXPLANATION AND USE
A

Accumulator

address
data

Immediate data
Bit "n" of immediate data or immediate address

Dn
H

Register H

HL

Register pair H L

L
P(

Immediate address
Carry Flag

C

Register L
)

PC n

Parallel Input/Output Port addressed by the value within the brackets
Bit "n" of Program Counter
Number of bytes in next instruction when Skip Condition occurs

S
STACK

Stack Register

(

)

The contents of RAM addressed by the value within the brackets

[

1

The contents of ROM addressed by the value within the brackets

<-

Load, Store, or Transfer

*'
-

Exchange
Complement

V-

LOGICAL Exclusive-OR

II

INSTRUCTION SET
I
MNEMONIC

FUNCTION

DESCRIPTION

INSTRUCTION CODE
D7

I De I D5 [

D41

Da

D3

I D2 I D, I Do

J

SKIP
BYTES

CYCLES

,

,
,

,

CONDITION

LOAD
LAI data

A - D3-0

L.oad A with 4 bits of Imme-

0

0

0

,

0

0

,

0

, ,

0

D4

,

0

, , , ,

Instructions
LHI date

H .-01-0

LHLI data

HL - D4-0

D2

D,

DO

1

0

D,

DO

D3

D2

D,

DO

,
,

0

,

2

,

,

String

dlate data; execute lucce.ding
LAI instructions 81 NOP
Load H with 2 bits of immediate data
Load HL with 5 bits of

-

String

immediate data; executa
succeeding LH LI instructions
as NOP instructions
LAMT

A - [PCS-S, 0, C, Al H

Load the upper 4 bits of ROM

0

Table Data at address
PCS-S, 0, C, A to A
(HL) - [PCS-6,
0, C, Al L

Load the lower 4 bits of ROM

Table Data at address
PCg-S, 0, C, A to the RAM

L

A-(HL)

Load A with the contents of
RAM addressed by HL

0

LIS

A-(HL)
L - L +'

Load A with the contents of
RAM addressed by H L; Increment L; skip if L "" OH

0

Load A with the contents of
RAM addressed by H L;
decrement L; skip if L'" FH

0

,
,
,

load A with the contents of
RAM addressed by 6 bits of
immediate data

0
0

0
0

(HL) -A

Store A into the RAM location
addressed by H L

0

IHL) -D3_0

Store 4 bits of immediate data
into the RAM location
addreS$8d by Hl; increment L

0

location addressed by H L

Skip if L=OH
LDS

A-(HL)
L-L-l

Skip if L "" FH
LAOR address

A- (D5-O)

0
0

0

STII data

l-l+ 1

,
,

0

0

,

0

0

0

0

,

,

'+S

L-OH

0

0

0

0

,

'+S

L= FH

0
D,

, , ,
03

0
DO

2

D4

0
D2

2

05

0

,

0

, , ,

,

0

0

D3

D2

,
,

STORE
ST

,
,
,

D,

DO

,
233

pPD7520
INSTRUCTION SET
(CONT.)
MNEMONIC

FUNCTION

I

OESCRIPTION

INSTRucnON CODE

D71D&IDsID4ID3I

Dz

SKIP

ID1IDo

BYTES

CYCLES

CONDITION

EXCHANGE
XAH

Al.o - Hl.o
A3-2 -OOH

Exchange A with H

0

1

1

1

1

0

1

0

1

1

XAL

A-L

Exchange A with L

0

1

1

1

1

0

1

1

1

1

X

A-IHL)

Exchange A with the contents
of RAM addressed by HL

0

1

0

1

0

1

1

0

1

1

A-IHL)

Exchange A with the contents
of RAM addressed by 'HL;
increment L; skip if L = OH

0

1

0

1'

0

1

0

1

1

1+5

L=OH

Skip If L= OH
XOS

A-IHL)
L+-L-1
Skip if L = FH

Exchange A with the contents
of RAM addressed by HL;
decrement L; skip if L = FH

0

1

0

1

0

1

0

0

1

1+5

L-FH

XADR address

A -105-0)

Exchange A with the contents
of RAM addressed by 6 bits of
immediate data

0

0
0

1

1

0

1

2

2

Os

D4

XIS

L-L+ 1

0

D3

Dz

0
Dl

Do

1

ARITHMETIC AND LOGICAL
AI$C data

A-A+ 03_0
Skip If overflow

ASC

AC5C

A-A+ IHL)
Skip if overflow
A, C - A + IHL)
Skip if C "" 1

Add 4 bits of immediate data
to A; Skip if overflow is
generated

0

0

0

0

OJ

D2

Dl

Do

1

1+5

Overtlow

Add the contents of RAM

0

1

1

1

1

1

0

1

1

1+5

Overflow

0

1

1

1

1

1

0

0

1

1+5

C-l

0

1

1

1

1

1

1

0

1

1

addressed by H L to A; skip if
overflow is generated

+C

EXL

A-A

CMA

A .... 'A

Complement A

0

1

1

1

1

1

1

1

1

RC

C-O

Reset earry Flag

0

1

1

1

1

0

0

0

1

SC

C-I

Set Carry Flag

0

1

1

1

1

0

0

1

1

1

ILS

L-L+ 1
Skip if L = OH

Increment L;
Skip if L= OH

0

1

0

1

1

0

0

,

1

1+5

L-OH

IDRS address

105.0) -105.0) + 1
5kip if 105.0) = OH

Increment the contents of
RAM addressed by 6 bits of
immediate data; Skip if the

0
0

0

1
05

1
D4

1

1

2

2+5

(OS-O) = OH

OJ

Dz

0
0,

1

0

Do

Decrement L;

0

1

0

1

1

0

0

0

1

1+5

L=FH

0

0

1

1

1

1

0

0

2

2+5

(D5.Q) = FH

0

0

05

D4

OJ

Dz

Dl

Do

\,L

IHL)

Add the contents of RAM

addressed by H L and the carry
flag to A; skip if carry is
generated
Perform a LOGICAL
Exclusive-OR operation
between the contents of
RAM addressed by HL and
A; store the result in A

ACCUMULATOR AND CARRY FLAG

INCREMENT AND DECREMENT

1

I

1

contents =OH
OLS
ODRS addre$$

L .... l - l
Skip if L= FH
105.0) - 10s-0) - 1
Skip if 105.0) = FH

Skip if L= FH

Decrement the contents of
RAM addressed by 6 bits of
immediate data, skip if the
contents = F H

BIT MANIPULATION
RMB data

(HL)bit _0

Reset a single bit (denoted by
01 Dol of the RAM location
addressed by HL to zero

0

1

1

0

1

0

D,

Do

1

1

5MB data

(HL}bit +-1

Set a single bit (denoted by
01 DO) of the RAM location
addressed by H L to one

0

1

1

0

1

1

Dl

Do

1

1

JMP address

PCg.o-Og.o

Jump to the addresa ~ified

0

0

0

0

D7

Do

1
D5

0

by 10 bits of immediate data

D4

OJ

Dz

Og
D,

Do

PCg-a - 01-0
PC7-4 - A
PCl-O -IHL)

Jump to the addreS$ specified
by 2 bits of immediate data, A.
and the RAM contents

0
0

0
0

1
0

1
1

1
0

1
0

1
Dl

Do

1

0

Os

D4

OJ

Dz

Dl

Do

JUIW'. CALL. AND RETURN

JAM data

Os

2

2

1

2

2

1

1

addressed by H L

JCP address

PC5.o - Os.o

Jump to the address specified
by the histaer-order bits PCg....s

of the PC, and 6 bits of
immediate data

234

,uPD7520

INSTRUCTION SET
(CONT.)
INSTRUCTION COOE
MNEMONIC

CALL address

STACK +- PC

+2

PCg·O- Dg.O

CAL address

OESCRIPTION

FUNCTION

STACK +- PC

+1

PCg.O - 0' D403
ooo02 D,OO

Store a return address (PC + 2)
in the stack; call the subroutine
program at the location speci·
fied by 10 bits of immediate
data
Store a return address (PC + 1)

07
0
07

SKIP

I Os I Os I 04 I D:I I 02 10 '1 Do
0
06

, ,

DS

, , ,

Os

BYTES

CYCLES

2

2

,

CONDITION

D4,

0
D3

0
02

Dg
0,

DO

04

D3

02

0,

DO

,

,

0

0

1

0

,
, ,

,

, +S

Unconditional

0

in the stack; call the subroutine
program at one of the 32 spe-

cial locations specified bV 5
bits of immediate data

,

RT

PC +- STACK

Return from Subroutine

0

,

0

RTS

PC +- STACK
Skip unconditionally

Return from Subroutine; skip
unconditionally

0

1

0

SKC

Skip if C - 1

Skip if carry flag is true

0

1

0

1

1

0

C=1

0

1

1

0

0

D,

DO

1 +5

(HUbil = 1

SKMBF data

Skip if (H L)bit - 0

Skip if the single bit (denoted
by 0100) of the RAM location addressed by H L is true
Skip if the single bit (denoted
by 0, DOl of the RAM location addressed by H L i~ false

,
,

, +S

Skip if (HL)bit '" 1

,

1

SKMBTdata

0

1

1

0

0

0

0,

DO

1

1+S

IHLlbit - 0

SKABT data

Sk ip if Ailit - 1

Skip if the single bit i,J~'Ned
by 0, DOl of A is tru,

0

1

1

1

0

,

D,

DO

,

1+S

Abit= 1

Skip if A equals 4 bits c';
immediata data

0
0

a
1

1
1

1
0

1
D3

1
DO

2

2+5

A"" data

a

1

0

1

1

,
, 0,, ,

1

, +S

A= (HLI

1

1

,

1

SKIP

SKAEI data

Skip if A - data

SKAEM

Skip if A - (HLI

Skip if A equals the RAM contents addressed by H L

IPL

A-P(LI

Input the Port addressed

1

02

1

PARALLEL 1/0

0

1

,

1

0

0

0

0

IPI

A-Pl

Input Port 1 to A

0

1

1

1

0

0

0

,

1

1

OPL

P(LI-A

Output A to the port
addressed by L

0

1

1

1

0

0

1

0

1

1

OP3

P3

Output the lower 2 bits of A
to Port 3

0

,

1

1

0

0

1

1

1

1

0

0

0

0

0

1

,

by L to A

-+-

Al-O

CPU CONTROL
NOP

Perform no operation; consume one machine cycle

ABSOLUTE MAXIMUM
RATINGS*

0

0

0

Operating Temperature
Storage Temperature.
Supply Voltage
Input Voltage .... .
Output Voltage . . . . . . . . .
Output Current (IOH Total)
(IOL Total) .

... -10° to +70°C
.. -40° to +125°C
~ 15 to +0.3 Volts
-15 to +0.3 Volts
-15 to +0.3 Volts
.. ~100mA
, ....... gOmA

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections 'of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

235

Jl.PD7520
PACKAGE OUTLINE
"

A

-,

H~,,-,
'
r
,rr
~
U, '.~ ,'
-

B

,F

-,-

-

---ll-o

!'

~PD7520C

G..

PLASTIC
ITEM

MILLIMETERS

INCHES

A

38,0 MAX.

1.496 MAX.

8

2.49

0.098

C

2.54

0.10

0

0.5:! 0.1

0.02' 0.004

1.3

E

33.02

F

1.5

0.059

G

2.54 MIN,

0.10MIN.

H

0.5MIN.

0.02 MIN.

I

5.22 MAX.

0.205 MAX.

J

5.72 MAX.

0.225 MAX.

K

15.24

0.6

L

13.2

0.52

M

025 + 0.10
.
0.05

0.Q1

+0004
0:002

752005-10-80-CAT

236

NEe Microcomputers, Inc.
4-81T MICROPROCESSOR
,uPD750X EVALUATION CHIP
DESCR I PTI ON

The !,PD7500 is a !,COM-75 4-bit microprocessor with a 256 x 4 RAM, a programmable 8-bit

timer/event counter, and 5 vectored, prioritized interrupts. It is capable of addressing 8,192 bytes
of external memory, and also functions as the prototype Evaluation Chip for the ,uPD750X family
of 4--bit single chip microcomputers. The ,uPD7500 is manufactured with a low-power-consumption
CMOS process, allowing use of a single power supply between 2.7 and 5.5V, and providing pro·
grammable power-down capability. It has 46 I/O lines, organized into eight 4-bit parallel ports,
one 14-bit parallel address/instruction port, and one 8-bit serial port. The ,uPD7500 executes 102
instructions of the ,uCOM-75 instruction set, and it is available in a 64 pin quad-in-line package.

FEATURES

•
•
•
•
•
•

4-Bit Microprocessor
Evaluation Chip for !'PD750X Family of 4-Bit Single Chip Microcomputers
Addresses up to 8,192 Bytes of External Memory
256 x 4 Bit RAM
10MS Instruction Cycle Time
102 Powerful Instructions
- Table Look-up Capability with LHLT and LAMTL instructions
- Indirect indexed addressing with CAL T instruction

•
•

•

RAM Stack
Extensive I/O Capability
One 4-8it Input Port
Two 4-Bit Output Ports
Four 4·Bit I/O Ports, of which two are 8-Bit Byte Accessible
One 4-Bit I/O Port with Output Strobe
One 14·Bit Address/Instruction Port
One 8-Bit Serial I/O Port
Programmable 8-Bit Timer/Event Counter with Crystal Clock Generator
Vectored, Prioritized Interrupts
- 3 External
- 2 Internal (Timer and Serial I/O)
Programmable Power-Down Operation with HA L T and STOP Instructions

•
•
•

Built-In System Clock Generator
Built-In Reset Circuitry
Single Power Supply, Variable from 2.7V to 5.5V

•
•

CMOS LSI
64-Pin Quad-In-Line Package

•
•

PIN CONFIGU~ATION

II

PIN NAMes

x,

Vss
BUS7

X,

TEsT

BUS6

BUSS
BUS9

BUS5
BU S4

BUS10

SUS3

BUS11
BUS12

BUS2
BUS,

BUS;3

BUSO

'40
'4,

P13
P1,

'4,

P1,

'43
'50
'5,

P10

tL PD

'5,

7500

ill

BUSO-BUS,3

Address/Instruction Bus

'00
PO,/SCK

Input Port 00
Input Port O,/Serlal Clock

P02/S0

Input Port 02/Serial Output

P03/S1

Input Port 03/Serlallnput

P'O·P1 3
P20/STB

Output Port 20/Pon 1 Strobe Output

P2, /PTOUT

Output Port 2,/Tlmer OutpUt

P20·P23

Output Port 2

P30·P33

Output Port 3

P40·P43

Input/Output POrt 4

Input/Output Port 1

P50·P53

Input/Output Port 5

P~O·~63

Input/Output Port 6

CsQ"O'T

P70·P73

Input/Output Port 7

LCD CL

INTO

Interrupt InputO
Interrupt Input 1

'53

P'S'EN

INT,

'60
'6,

P20/STB
P2,/PTOUT

INT2

Interrupt Input 2

Cl" CL2

System Clock Input, Output

'6,
'63

'"

'"

"3
P03/S1
P02JSO
PO,/Sci<

"3
tNT,

'00
NC

"0

'"

INTO

ALE

INT2
AESET

Do"UT

CL,

'"

CL,
VOO

"3

'"
'30

Xl, X2

Crystal Clock Input, Output

ALE

Addrass LATCH ENABLE

CSOUT

Chip Select Output

DOU

LCD CL

LCD Clock OutPut

PSEN

Program Store ENABL.E

STB

Strobe'

AESET

Aelet

VDD

Power Supply Positive

VSS

Ground

TES

Factory Telt Pin

NC

No Connection

237

JLPD7500
BLOCK DIAGRAM

.lot,Loll.

PACKAGE OUTLINE
~1"075(J()B

Ceramic
ITEM
A

41.5

I'NCHES
1.634 MAX

B

1,05

C

2.54

0.1

0
E
F

0.5 ± 0.1

0.2 ± 0.004

G
I

39.4

0.042

1.55

1.27

0.05

5.4 MIN

0.21 MIN

2.35 MAX

0.13 MAX

J

24.13

0.95

K

19.05

0.75

L

15.9

0.626

M

238

MILLIMETERS

0.25 ± 0.05

0.01 ± 0.002

7!!iOODS-10-80-CAT

NEe

NEe Microcomputers, Inc.

JLPD7800

HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
ROM-LESS DEVELOPMENT DEVICE
DESCRIPTION

FEATU R ES

The NEC tlPD7800 is an advanced 8-bit general purpose single-chip microcomputer
fabricated with N-channel Silicon Gate MOS Technology_ Intended as a ROM-less
development device for NEC tlPD7801/7802 designs, the tlPD7800 can also be used
as a powerful microprocessor in volume production enabling program memory flexibility_ Basic on-chip functional blocks include 128 bytes of RAM data memory, 8-bit
ALU, 32 I/O lines, Serial I/O port, and 12-bit timer. Fully compatible with the
industry standard 8080A bus structure, expanded system operation can be easily
implemented using any of 8080A/8085A peripheral and memory products. Total
memory address space is 64K bytes.

• NMOS Silicon Gate Technology Requiring Single +5V Supply.
• Single-Chip Microcomputer with On-Chip ALU. RAM and I/O
- 128 Bytes RAM
- 32 I/O Lines
• Internal 12-Bit Programmable Timer
• On-Chip 1 MHz Serial Port
• Five-Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
• Bus Expansion Capabilities
- Fully 8080A Bus Compatible
;- 64K Byte Memory Address Range
• Wait State Capability
• Alternate Z80™ Type Register Set
• Powerful 140 Instruction Set
• 8 Address Modes; Including Auto-Increment/Decrement
• Multi-Level Stack-Capabilities
• Fast 2 tls Cycle Time
• Bus Sharing Capabilities

PIN CONFIGURATION

AS,!

rr

DB-

Vee (+5V)

AB'4
AB'3

DBt

A8'2

DB!

AB11

DB.

AB'0

D8~

ABO

DB;

ABB

DB

AB7

DB,

AB.

INT:

ABS

INT·

AB,

INT(

ABJ

WAii

'B2
AB,

M

WR

ABO

m:

PB7

PCj

PBS

PC,

PBs
PB,

PC,
PC,
PC,

PBJ
PB2

PC2
PC,

PB,

PCo

PA7

S'CK

PA6

SI
SO

PAS
PA,

Jmri'

PA,

STB

X,

PA2
PA,

Vss lov)

PAo

PBo

239

p.PD7800
PIN NO.
1,49·63
2

3·10

ABO·AB15

EXT

DBO-DB7

11
12

INTO
INTl

13

INT2

14

WAIT

15

Ml

16

WR

17

RD

18-25

PCO-PC7

26

SCK

27

SI

28

SO

29
30

RESET
STB

31
33-40
41-48

240

DESIGNATION

Xl
PAO-PA7
PBO-PB7

.

FUNCTION

(Tri·State, Output) 16·bit address bus.
(Output) EXT is used to simulate IIPD780111802
external memory reference operation. EXT distinguishes between internal and external memory
references, and goes low when locations 4096
through 65407 are accessed.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transitions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is programmable. By setting the ES bit in the Mask
Register'to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, Ml indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) Rij is used as a
strobe to ~e data from external devices on the
data bus. R D goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the rising edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through theSI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this \.ine on the falling edge of SCK,
MSB to LSB.
(Input, active low) RESET initializes the IIPD7801.
(Output) Used to simulate IIPD7801 Port E operation, indicating that a Port E operation is being
performed when active.
(I nput) Clock Input
(Output) 8-bit output port with latch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable independently as an
input or output.

PIN DESCRIPTION

jLPD7800
BLOCK DIAGRAM

,.

~

AB6-16

.ill'"

ABQ..7

INC/DEC

.f----l

,NToo---.....

PC

OP
INT1o---.....-t

INT

V

CONTROL

INT2o-----t

A
C

0

lI

MAIN

G.A.

DATA
MEMORY
(128 BYTE)

H
V

A
C

0

} ALT
G.R.

SIO----~~
--------~SIO

SCK~

0004~-----------J

PC3JSAK~

INST
DECODER

PA7-O

PC71

PCfj

M1

Vee Vss

x,

HOLD HLDA

241

}lJPD7800
Architecturally consistent with ,uPD7801/7802 devices, the ,uPD7800 uses a slightly
different pin-out to accommodate for the adEJfe~s bus and lack of on-chip clock
generator. For complete ,uPD7800 functional operation, please refer to ,uPD7801
product information. Listed below are function'aIi differences that exist between
,uPD7800 and ,uPD7801 dey ices.
,uPD7800/7801 Functional Differences
1. The functionality of ,uPD7801 Port E is somewhat different on the ,uPD7800_
Because the ,uPD7800 contains no progrilm memory, the address bus is made
accessible to address external prQgram memory. Thus, lines normally used for Port
E operation with the ,uPD7801 are used as the address bus on the ,uPD7800. ABOAB15 is active during memory access O~hrough 4095.
2. Consequently Port E instructions (PEX,-pEN, and PER) have different
functionality.
PEX Instruction - The contents of Band C register are output to the address bus.

The value 01 H is output to the data bus. STB becomes active.
PEN Instruction - B and ~>'register contents are output to the address bus. The

value 02H is output to the data bus. STB becomes active.
PER Instruction - The address bus goes to the high impedance state. The value

04H is output to the data bus. STB becomes active.
3. ON-CHIP CLOCK GENERATOR. The ,uPD7800 contains no internal clock generator. An external clock source is input to the Xl input.
4. PIN 30. This pin functions as the X:2;Crystal connection on the ,uPD7801. On the
,uPD7800, pin 30 functions as a strobe output (STB) and becomes active when a
Port E instruction is executed. This;~ontrol signal is useful in simulating ,uPD7801
Port E operation - indicating that a port E operation is being performed.
5. PIN 2. Functions as the 1> out clock output used for synchronizing system external
memory and I/O devices, on the ,uPD7801. On the ,uPD7800, this pin is used to
simulate external memory reference operation of the ,uPD7801. EXT is used to
distinguish between internal and external memory references and goes low when
location 4096 through 65407 are accessed.

RECOMMENDED CLOCK DRIVE CIRCUIT

200pF

I

242

,.

FUNCTIONAL DESCRIPTION

jI.,PD7800
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature ........ , . . . . . . . . . . . . . . . . . . . . . -lOoe to +70o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . , . .. -65°e to +125°e
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.3V to +7.0V
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliabilitY .

DC CHARACTE RISTICS

Ta = -10 - +70°C, VCC = +5.0V ± 10%
LIMITS
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

CAPACITANCE

SYMBOL

MIN

TYP

MAX

UNITS

TEST
CONDITIONS

VIL

0

0,8

V

VIH1

2.0

VCC

V

Except SCK, Xl

VIH2

3,8

VCC

V

SCK,Xl

V

IOL = 2,0 rnA

VOHl

2.4

0.45

V

IOH =-100/lA

VOH2

2.0

V

IOH = -500 /lA

-10

/lA

VIN = OV

VOL

Low Level Input Leakage Current

ILiL

High Level Input Leakage Current

ILiH

10

/lA

VIN = VCC

Low Level Output Leakage Current

ILOL

-10

/lA

VOUT = 0.45V

High Level Output Leakage Current

ILOH

10

/lA

VOUT = VCC

VCC Power Supply Current

ICC

110 200

rnA

Ta = 25°C, VCC = GNO = OV
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Input Capacitance

CI

10

pF

Output Capacitance

Co

20

pF

Input/Output Capacitance

CIO

20

pF

TEST
CONDITIONS
Ic = 1 MHz
All pins not'

under test at OV

243

J.LPD7800
Ta

= -10 to

+70·C, VCC

=

AC CHARACTERISTICS

+5.0V ± 10%

CLOCK TIMING
LIMITS
PARAMETER

SYMBOL

MIN

MAX
2000

TEST
UNITS CONDITIONS

XOUT Cycle Time

tCYX

454

ns

tCYX

XOUT Low Level Width

tXXL

212

ns

tXXL

XOUT High Level Width

tXXH

212

ns

tXXH

READIWRITE OPERATION
LIMITS
PARAMETER
RD L.E ..... X OUT L.E.

SYMBOL
tRX

Address (PEO-15) .... Data
Input

tADl

RD T.E ..... Address

tRA

RD L.E ..... Data Input

tRD

ROT.E ..... Data Hold
Time

tRDH

MIN

MAX

20

TEST
UNITS CONDITIONS
ns

550 + 500 x N

ns
ns

200(T3F 700(T4)
350 + 500 x N

ns
ns

0

RO Low Level Width

tRR

RD L.E ..... WAIT L.E.

tRWT

850+500xN
450

ns
ns

Address (PEO-15) ....
WAIT L.E.

tAWTl

650

ns

WAIT Set Up Time
(Referenced from
XO UT L.E.)

tWTS

180

ns

WAIT Hold Time
(Referenced from
XO UT L.E.)
Ml .... 'RU"L.E.

tWTH

0

ns

tMR

200

ns

RDT.E ..... Ml

tRM

200

ns

IO/iIi! .... 1m' L.E.

tlR

200

ns

R!i' T.E ..... 101M

tRI

200

XO UT L.E ..... WR L.E.

txw

270

ns

Address (PEO-15) ....
XOUTT.E.
Address (PEO-15) ....
Data Output

tAX

300

ns

tAD2

450

ns

Data Output .... WR
T.E.

tow

600+500xN

ns

WR T.E ..... Data

two

150

ns

Address (PEO-15) ....
WR L.E.

tAW

400

ns

WR T.E ..... Address
Stabilization Time

tWA

200

ns

WR Low Level Width

tww

600+500xN

ns

IO/'fJ'".... WR L.E.

tlW

500

ns

WR T_E ..... IOIM

tWI

250

ns

ns

Stabilization Time

244

tCYX

= 500 ns

p.PD7800
AC CHARACTERISTICS
(CONT.)

SERIAL I/O OPERATION
PARAMETER

SYMBOL

SCK Cycle Time

tCYK

MIN

MAX

UNIT
ns

SCK Input

900 4000

ns

SCK Output

ns
ns

SCK Input
SCK Output
SCK Input
SCK Output

SCK Low Level Width

tKKL

350
400

SCi< High

tKKH

350
400

ns
ns
ns

Level Width

CONDITION

800

SI Set·Up Time Ireferenced from SCK T.E.)

tSIS

140

SI Hold Time Ireferenced from SCK T.E.)

tSIH

260

SCK L.E. -+ SO Delay Time

tKO

SCSHigh -+ SCK L.E.

tCSK

100

SCK T.E. -+ SCS Low

tKCS

100

SCK T.E. -+ SAK Low

tKSA

ns
180

ns
ns
ns

260

ns

MAX

UNIT

250

ns

PEN, PEX, PER OPERATION
PARAMETER

SYMBOL

MIN

Xl L.E. -+ EXT

tXE

Address IABO-15) -+ STB L.E.

tAST

200

Data IDBO-7) -+ STB L.E.

tDST

200

STB Hold Time

tSTST

300

STB -+ Data

tSTD

400

CONDITION

tCYX

~

500 ns

HOLD OPERATION
PARAMETER

SYMBOL

MIN

HOLD Set-Up Time Ireferenced from
X OUT L.E.)

tHDS
tHDS2

100
luu

HOLD Hold Time Ireferenced from £lOUT
L.E')

tHDH

100

X OUT L.E.

-+

HLDA

tXHA

HLDA High -+ Bus Floating IHigh Z State)

tHABF

H LOA Low -+ Bus Enable

tHABE

-150

MAX

UNIT

CONDITION

ns
ns
ns
100

ns

150

ns

350

ns

Notes:

CD

AC Signal waveform lunless otherwise specified)

X :::::=> M~~~~~~NG ~

2.4 - - -.....

0.45---.J

:::

X~
-

@

Output Timing is measured with 1 TTL + 200 pF measuring points are VOH = 2.0V

@

L.E. = Leading Edge, T.E. = Trailing Edge

___

VOL =0.8V

245

fLPD7800
tCYX DEPENDENT AC PARAMETERS
PARAMETER

(1/25) T

tRX

MINIMAX

UNIT

MIN

ns

tADl

(3/2 + N) T - 200

MAX

ns

tRA (T3)

(1/2) T- 50

MIN

ns

tRA (T4)

(3/2) T- 50

MIN

ns

tRD

(l+N)T-150

MAX

ns

tRR

(2+N)T- 150

MIN

ns

t'RWT

(3/2) T- 300

MAX

ns
ns
ns

tAWTl

(2) T- 350

MAX

tMR

(1/2) T - 50

MIN

tRM

(l/2)T-50

MIN

ns

tlR

(l/2)T-50

MIN

ns

tRI

(1/2) T- 50

txw

(27/50) T

tAD2

T- 50

tDW

(3/2 + N) T

150

MIN

ns

MAX

ns

MIN
MIN

ns
ns

tWD

(1/2) T- 100

MIN

ns

tAW

T- 100

MIN

ns

tWA

(l/2)T-50

MIN

ns

tww

(3/2 + N) T- 150

MIN

ns

tlW

T

MIN

ns

twl

(1/2) T

MIN

ns

tHABE

(1/2) T - 150

MAX

ns

tAST

(2/5) T

MIN

ns

tDST

(2/5) T

MIN

ns

tSTST

(3/5) T

MIN

ns

tSTD

(4/5) T

MIN

ns

Notes:

CD
@
@
@)

N = Number of Wait States
T=tCYX
Only above parameters are tCYX dependent .
When a crystal frequency other than 4 M Hz is used (tCYX = 500 ns)
the above equations can be used to calculate AC parameter

values.

246

EQUATION

AC CHARACTERISTICS
(CONT.)

",PD7800
CLOCK TIMING

TIMING WAVEFORMS

'Cv,

----------l
'XXH

READ OPERATION

"

. . "-4==t=====-:.;;::::t:==::;------.:=======:rlAO,

D~,--_+----i----<:::::::::i::::::X::::!~~:jt:)-----~------~

~--~----+-----------1

.,

,-

II

WRITE OPERATION

x,
A~" --~~--------~--~--------~------------------------~---

D~~----t-----------~~::::::::~::::::::::::::::::~::::~
-----~--------~~I

WMT------------------~----u

.0lIl

"w-----~

247

JLPD7800
TIMING WAVEFORMS
(CONT.)

SERIAL I/O OPERATION
tCYK

Sl-+-{::~~-

SCS ___________

J'

SAK _ _ _ _ tKSA
_

PEN, PEX, PER OPERATION

HOLD OPERATION

248

t

JLPD7800
PACKAGE OUTLINE
ILPD7800C

STRAIGHT LEADS
~------A------~

~l

M
(Plastic)
ITEM

MILLIMETERS

05.0.1

36.1

'"

01&'0011

INCHES

0.02 ! 0004

...'"

00' ,

GOO~

BENT LEADS

II
(Unlt:mm)

rrI.
I

II
"
24

~~
.111

7BOODS-12-80-CAT

249

NOTES

250

NEe

NEe Microcomputers, Inc.

,u.PD7801

HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
WITH 4K ROM
PRODUCT DESCRIPTION

The NEe ,uPD7801 is an advanced 8-bit general purpose single-chip microcomputer fabricated wIth
N-Channel Silicon Gate MOS technology.
The NEe ,uPD7801 is intended to serve a broad spectrum of 8-bit designs ranging from enhanced
single chip applications extending into the multi -chip microprocessor range. All the basic functional
blocks - 4096 x 8 of ROM program memory, 128 x 8 of RAM data memory, 8-bit ALU, 48 1/0
lines, Serial I/O port, 12-bit timer. and clock generator are provided on-chip to enhance stand-alone

applications. Fully compatible with the industry standard 80S0A bus structure, expanded system
operation can be easily implemented using any of the 8080A/SOS5A peripherals and memory
products. Total memory space can be increased to 64K bytes.
The powerful 140 instruction set coupled with 4K bytes of ROM program memory and 128 bytes
of RAM data memory greatly extends the range of single chip microcomputer applications. Five
level vectored interrupt capability combined with a 2 microsecond cycle time enable the ,uPD7801
to compete with multi-chip microprocessor systems with the advantage that most of the suppOrt
functions are on-chip.

FEATURES

•
•

•
•
•

•

•
•
•
•
•
•
•
•

PIN CONFIGURATION

NMOS Silicon Gate Technology Requiring +5V Supply
Complete Sinqle-Chip Microcomputer with On-Chip ROM'~ RAM and 1/0
- 4K Bytes ROM
'
- 128 Bytes RAM
- 48 1/0 Lines
Internal 12-81t Programmable Timer
On-Chip 1 MHz Serial Port
Five Level Vectored, Prioritized Interrupt Structure
~ Serial Port
~ Timer
~ 3 External Interrupts
Bus Ex-pansion Capabilities
- Fully 8080A Bus Compatible
- 60K Bytes External Memory Address Range
On-Chip Clock Generator
Wait State Capability
Alternate Z80™ Type Register Set
Powerful 140 Instruction Set
8 Address Modes; Including Auto-Increment/Decrement
Multi-Level Stack Capabilities
Fast 2 }.lS Cycle Time
Bus Sharing Capabilities

PE15
SII)
PE14
PE13
PE12
PE11
PE1Q
PE 9
PEa
PE7
PE6
PES
PE4
PE3
PE2
PEl
PEo
PB7
PB6
PBS
PB4
PB3
PB2
PBl
Pao
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO

251

}LPD7801
PIN NO.

1,49-63
2

3·10

ABO-AB15
EXT

DBO-DB7

11
12

INTO
INT1

13

INT2

14

WAIT

15

M1

16

WR

17

RD

18·25

PCO-PC7

26

SCK

27

SI

28

SO

29
30

RESET
STB

31
33·40
41·48

252

DESIGNATION

Xl
PAO·PA7
PBO·PB7

FUNCTION

(Tri·State, Output) 16-bit address bus.
(Output) EXT is used to simulate J,lPD7801/7802
external memory reference operation. EXT distin·
guishes between internal and external memory
references, and goes low when locations 4096
through 65407 are accessed.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level·sensitive interrupt input.
(Input, active high) Rising·edge sensitive interrupt
input. Interrupts are initiated on low-to·high transitions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is pro·
grammable. By setting the ES bit in the Mask
Register to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T 2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri·State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri·State Output, active low) RTI is used as a
strobe to ~e data from external devices onto the
data bus. RD goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8·bit I/O configured as a nibble
I/O port or as control lines.
(I nput/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the ris·
ing edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through the SI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this line on the falling edge of SCK,
MSB to LSB.
(I nput, active low) RESET initializes the J,lPD7801.
(Output) Used to simulate J,lPD7801 Port E opera·
tion, indicating that aPort E operation is being
performed when active.
(I nput) Clock Input
(Output) 8-bit output port with latch capability.
(Tri·State Input/Output) 8·bit programmable I/O
port. Each line configurable independently as an
input or output.

PIN DESCRIPTION

}LPD7801
BLOCK DIAGRAM

1
PC1,Q

FUNCTIONAL
DESCRIPTION

1M'"
I'"

PC12

Memory Map
The I1PD7801 can directly address up to 64K bytes of memory. Except for the on·chip
ROM (0·4095) and RAM (65,408·65,535). any memory location can be used as either
ROM or RAM. The following memory map defines the 0-64K byte memory space for
the I1PD7801 showing that the Reset Start Address, I nterrupt Start Address, Call
Tables, etc., are located in the internal ROM area.

INTERNAL
ROM
10·40951
4095
4096

0

RESET

4

INTO

8

INT1

16

INT2

32

1NT3

EXTERNAL
MEMORY

~

61.312x8

65,407
65.409

INTERNAL
RAM
65.535

64

INTS

56

SOFT I

128

LOW ADDR

129

HIGH ADDR

130
131

LOWADDR
HIGH ADDR

254

LOWADDR

255

HIGH ADDR

} t '" 63

USER·S
AREA

253

,...PD7801
I/O Ports
I

PORT

FUNCTIONS

FUNCTIONAL
DESCRIPTION
(CONT.)

8-bit output port with latch

Port A
Port B

8-bit programmable Input/Output port w/latch

Port C

8-bit nibble I/O or Control port

Port E

l6-bit Address/Output Port

Port A
Port A is an 8-bit latched output port. Data can be readily transferred between the
accumulator and the output latch buffers. The contents of the output latches can be
modified using Arithmetic and logic instructions. Data remains latched at Port A unless
acted on by another Port A instruction or a RESET is issued.
Port B
Port B is an 8-bit I/O port. Data is latched at Port B in both the Input or Output modes.
Each bit of Port B can be independently set to either Input or Output modes. The
Mode B register programs the individual lines of Port B to be either an Input
(Mode Bn = 1) or an Output (Mode Bn = 0)'
Port C
Port C is an 8-bit I/O port. The Mode C register is used to program the upper 6 bits of
Port C to provide control functions or to set the I/O structure per the following table.
MODE Cn

=0

MODE C n

=1

PCO

Output

PCl

Output

Input

PC2

SCS Input

Input

PC3

SAK Output

Output

PC4

To Output

Output

PC5

10iM Output

Output

PC6

HLDA Output

Output

PC7

HOLD Input

Input

Input

Port E
Port E is a l6-bit address bus/output port. It can be set to one of three operating modes
using the PE R, PEN, or PEX instructions.
• l6-Bit Address Bus - the Per instruction sets this mode for use with external I/O or
memory expansion (up to 60K bytes, externally).
• 4-Bit Output Port/12 Bit Address Bus - the PEN instruction sets this mode which
allows for memory expansion of up to 4K bytes, externally, plus the transfer of 4-bit
nibbles.
•

254

l6-Bit Output Port - the PEX instruction sets Port E to a l6-bit output port. The con·
tents of Band C registers appear on PE8-l5 and PEO-7, respectively.

~PD7801
FUNCTIONAL
DESCRIPTION
(CONT.)

Timer Operation

TO

TIMER BLOCK DIAGRAM

A programmable 12-bit timer is provided on-chip for measuring time intervals, generating pulses, and general time-related control functions. It is capable of measuring time
intervals from 4 IlS to 16 IlS in duration. The timer consists of a prescaler which
decrements a 12-bit counter at a fixed 4 IlS rate. Count pulses are loaded into the
12-bit down counter through timer register (TMO and TM 1). Count-down operation is
initiated upon extension of the STM instruction when the contents of the down
counter are fully decremented and a borrow operation occurs, an interval interrupt
(INTT) is generated. At the same time, the contents of TMO and TM1 are reloaded
into the down-counter and countdown operation is resumed. Count operation may be
restarted or initialized with the STM instruction. The duration of the timeout may be
altered by loading new contents into the down counter.
The timer flip flop is set by the STM instruction and reset on a countdown operation.
Its output (TO) is available externally and may be used in a single pulse mode or general
external synchronization.

II

Timer interrupt (I NTT) may be disabled through the interrupt.
Serial Port Operation

PC,/SAK

~

"

MC3

,

a

A

"

WA,

AI>;

SERIAL PORT BLOCK DIAGRAM

255

J.I. PD7801
The on·chip serial port provides basic synchronous serial communication functions
allowing the NEC pPD7801 to serially interface with external devices.
Serial Transfers are synchronized with either the internal clock or an external clock
input (SCK). The transfer rate is fixed at 1 Mbit/second if the internal clock is used
or is variable between DC and 1 Mbit/second when an external clock is used. The
Clock Source Select is determined by the Mode C register. The serial clock (internal
or external SCK) is enabled when the Serial Chip Select Sigllal (SCS) goes low. At this
time receive and transmit operationsthrough the Serial Input port (SI)/Serial Output
port (SO) are enabled. Receive and transmit operations are performed MSB first.
Serial Acknowledge (SAK) goes high When data transfers between the accumulator
and Serial Register is completed. SAK goes low when the buffer becomes full after
the completion of serial data receive or transmit operations. While SAK is low, no
further data can be received.
I nterrupt Structure
The pPD7801 provides a maskable interrupt structure capable of handling vectored
prioritized interrupts. I nterrupts can be generated from six different sources; three
external interrupts, two internal interrupts, and non·maskablesoftware interrupt.
Each interrupt when activated branches to a designated memory vector location
for that interrupt.

INT

256

VECTORED MEMORY
LOCATION

PRIORITY

TYPE

INTT

8

3

I nternal, Timer
Overflow

INTS

64

6

I nternal, Serial
Buffer Full/Empty

INTO

4

2

Ext., level sensitive

INT1

16

4

Ext., Rising edge
sensitive

INT2

32

5

Ext., Rising/Falling
edge sensitive

SOFTI

96

1

Software Interrupt

FUNCTIONAL
DESCRIPTION
(CONT.)

JoLPD7801
FUNCTIONAL

RESET (Resed

DESCRIPTION
(CONT.)

An active low-signal on this input for more than 4 /J.S forces the /J.PD7801
into a Reset condition. RESET affects the following internal functions:
•
•
•
•
•
•
•
•
•
•
•

The Interrupt Enable Flags are reset, and Interrupts are inhibited.
The Interrupt Request Flag is reset.
The HALT flip flop is reset, and the Halt-state is released.
The contents of the MODE B register are set to FFH, and Port B
becomes an input port.
The contents of the MODE C register are set to FFH. Port C becomes
an I/O port and output lines go low.
All F lags are reset to O.
The internal COUNT register for timer operation is set to FFFH and the
timer F /F is reset.
The AC K F/F is set.
The HLDA F/F is reset.
The contents of the Program Counter are set to OOOOH.
The Address Bus (PEO-15), Data Bus (DBO-7), RD, and WR go to
a high impedance state.

Once the RESET input goes high, the program is started at location OOOOH.

REGISTERS

The /J.PD7801 contains sixteen 8-bit registers and two 16-bit registers.
0

15
PC

I

SP

01

70
V

I

7

A

B

C

D

E

H

L

V'

A'

B'

C'

D'

E'

H'

L'

Main

Alternate

General Purpose Registers (B, C, D, E, H, L)
There are two sets of general purpose registers (Main: B, C, D, E, H, L:
Alternate: B', C', D', H', L'). They can function as auxiliary registers to the
accumulator or in pairs as data pointers (BC, DE, HL, B'C', D'E', H'L'). Auto Increment and Decrement addressing mode capabilities extend the uses for the DE, HL,
D'E', and H'L' register-pairs. The contents of the BC, DE, and HL register-pairs
can be exchanged with their Alternate Register counterparts using the EXX
instruction.

257

pPD7801
Vector Register (V)
When defining a scratch pad area in the memory space, the upper 8-bit memory
address is defined in the V-register and the lower 8-bits is defined by the immediate
data of an instruction. Also the scratch pad indicated by the V-register can be used
as 256 x 8-bit working registers for storing software flags, parameters and counters.

FUNCTIONAL
DESCRIPTION (CONT.)

Accumulator (A)
All data transfers between the IlPD7801 and external memory or I/O are done through
the accumulator. The contents of the Accumulator and Vector Registers can be
exchanged with their Alternate Registers using the EX instruction.
Program Counter (PC)
The PC is a 16-bit register containing the address of the next instruction to be
fetched. Under normal program flow, the PC is automatically incremented. However,
in the case of a branch instruction, the PC contents are from another register or
an instruction's immediate data. A reset sets the PC to OOOOH.
Stack Pointer (SP)
The stack pointer is a 16-bit register used to maintain the top of the stack area (lastin-first·out). The contents of the SP are decremented during a CALL or PUSH
instruction or if an interrupt occurs. The SP is incremented during a RETURN or
POP instruction.
Register Addressing

Working Register Addressing

Register Indirect Addressing

Direct Addressing

ADDRESS MODES

Auto-Increment Addressing

Immediate Addressing

Auto-Decrement Addressing

Immediate Extended Addressing

Register Addressing

I

OPCODE

1---~-----t......1OPERAND I

The instruction opcode specifies a register r which contains the operand.
Register Indirect Addressing
rp

-'-""""11

10PCODEI.....- -........""I!ADDRESsl.....

memory
OPERAND

1

The instruction opcode specifies a register pair which contains the memory address
of the operand. Mnemonics with an X suffix are ending this address mode.
Auto-Increment Addressing
rp
10PCODEI

... IADDREssl

memory
;C--IOPERAND

I

+"""--0
The opcode specifies a register pair which contains the memory address of the.
operand. The contents of the register pair is automatically increm'ented to point to
a new operand. This mode provides automatic sequential stepping when working with
a table. of operands.

258

}LPD7801
ADDRESS MODES (CONT.)

Auto-Decrement Addressing

IOPCODE

I

Working Register Addressing

PC
PC + 1

o
The contents of the register is linked with the byte following the opcode to form a
memory address'whose contents is the operand. The V register is used to indicate
the memory page. This address mode is useful as a short-offset address mode when
working with operands in a common memory page where only 1 additional byte
is required for the address. Mnemonics with a W suffix ending this address mode.
Direct Addressing
Memory

PC

OPCODE

PC + 1

Low Address

operand

PC + 2

High Address

1 byte

T

----.."

The two bytes following the opcode specify an address of a location containing the
operand.
Immediate Addressing

II

PC
PC + 1
Immediate Extended Addressing
PC

OPCODE

PC+ 1

Low Operand

PC+ 2

High Operand

259

pPD7801
INSTRUCTION SET

Operand Description

DESCRIPTION

OPERAND
r
r1
r2

Notes:

V,A,B,C,D,E,H, L
B,C,D,E,H,L
A,B,C

sr

PA PB PC MK MB MC TMO TM1 S

sr1

PA PB PC MK

sr2

PA PB PC MK

rp

SP, B, D, H

rp1

V,B,D,H

rpa

B,D,H,D+,H+,D-,H-

rpa1

B,D,H

wa

8 bit immediate data

word

16 bit immediate data

byte

8 bit immediate data

bit

3 bit immediate data

f

FO, F 1, F2; FT, FS,

S

1. When special register operands sr, sr1, sr2 are used; PA=PorJ: A, PB=Port B,
PC=Port C, MK=Mask Register, MB=Mode B Register, MC=Mode C
Register, TMO=Timer Register 0, TM1 =Timer Register 1, S=Serial Register.
2. When register pair operands rp, rp1 are used; SP=Stack Pointer, B=BC,
D=DE, H=HL, V=VA.
3. Operands rPa, rPa 1, wa are used in indirect addressing and auto-increment/
auto-decrement addressing modes.
B=(BCI. D=(DE), H=(HL)
D+=(DE)+, H+=(HL)+, D-=(DE)-, H-=(HL)-.
4. When the interrupt operand f is used; FO=INTFO, F1=INTF1, F2=INTF2,
FT=INTFT, FS=INTFS.

260

p.PD7801
INSTRUCTION GROUPS
MNEMONIC OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY Z

a·BIT DATA TRANSFER
MOV

rl,A

1

4

r1-A

MeV

A,rl

1

4

A-r1

Mev

sr,A

2

10

sr-A

MOV

A,srl

2

10

A-sr1

Mev

r, word

4

17

r-(word)

MOV

word, r

4

17

(word) - r

MVI

r, byte

2

7

MVIW

wa, byte

3

13

lv, wei - byte

MVIX

rPal, byte

2

10

Irpall - byte

STAW

wa

2

10

IV,wal-A

LDAW

wa

2

10

A-IV,wal

STAX

rpa

1

7

Irpal-A

LDAX

rPa

1

7

A-Irpal

EXX

1

4

Exchange register sets

EX

1

4

V,A"V,A

BLOCK

1

131C+1I

r -byte

IDEI+ - H!lLI+, C - C - 1

II

16·BIT DATA TRANSFER
SBCD

word

4

20

Iwordl - C, Iword + 11 - B

SDED

word

4

20

Iwordl- E, Iword + 11- D

SHLD

word

4

20

Iwordl - L, Iword + 11 - H

SSPD

word

4

20

(wordl- SPL, (word + 11- SPH

LBCD

word

4

20

C - Iwordl, B - (word + 11

LDED

word

4

20

E - Iwordl, D -Iword + 11

LHLD

word

4

20

L - (word I, H - (word + 11

LSPD

word

4

20

SPL - Iword!, SPH - Iword + 11

PUSH

rpl

2

17

(SP - 1.1 - rpl H, ISP - 21 - rpl L
rpl L -ISPI

POP

rpl

2

15

LXI

rp,word

3

10

rp+-word

1

19

C- (PC + 2 + AI
B-IPC+2+A+ll

TABLE

rp~-ISP

+ II, SP-SP + 2

261

JLPD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY Z

ARITHMETIC
ADD

A.r

2

8

A +-:-A +r

t

t

ADD

r,A

2

8

r+-r+A

t

t

A!)DX

rpa

2

11

A -A + (rpal

t

t

ADC

A.r

2

8

A -A + r +CY

t

t

ADC

r,A

2

8

r-r

t

t

ADCX

rpa

2

11

t

t

SUB

A,r

2

8

A-A-r

t

t

SUB

r,A

2

8

r+-r-A

t

t

sUBX

rpa

2

11

A - A - (rpal

t

t

sSB

A,r

2

8

A -A- r - CV

t

t

r _ r - A - CY

t

t

A - A - (rpal - CV

t

t

+ A + CY

' A - A + (rpal + CV

sBB

r.A

2

8

sSBX

rpa

2

11

ADDNC

A,r

2

8

A-A+r

No Carry

t

t

ADDNC

r,A

2

8

r-r+A

No Carry

t

t

ADDNCX

rpa

2

11

A -A + (rpal

No Carry

t

t

sUBNB

A,r

2

8

A-A-r

No Borrow

t

t

sUBNB

r,A

2

8

r-r- A

No Borrow

t

t

sUBNBX

rpa

2

11

A-A - (rpal

No Borrow

t

t

LOGICAL
ANA

A,r

2

8

A-Al\r

ANA

r,A

2

8

r ...... r

ANAX

rpa

2

11

ORA

A,r

2

ORA

r,A

ORAX

"A

t

A - A 1\ (rpal

t

8

A-AV r

t

2

8

r-rvA

t

rpa

2

11

A-Av(rpal

t

XRA

A,r

2

8

A-AVr

t

XRA

r,A

2

8

A-r'IJA

t

XRAX

rpa

2

11

GTA

262

t

A,r

2

8

t

A -A ¥ (rpa)

A- r - 1

No Borrow

I

I

p.PD7801
INSTRUCTION GROUPS (CaNT,)
MNEMONIC OPERANDS

NO,
BYTES

CLOCK
CYCLES

FLAGS
SKIP
CONDITION CY Z

OPERATION

LOGICAL (CONT,I
GTAX

rpa

2

11

LTA

A,r

2

LTA

r,A

LTAX

A - (rpal- 1

No Borrow

I

I

8

A-r

Borrow

I

I

2

8

r-A

Borrow

I

I

rpa

2

11

A- (rpal

Borrow

I

I

ONA

A,r

2

8

Allr

No Zero

I

ONAX

rpa

2

A II (rpal

No Zero

I

OFFA

A,f

2

Allr

Zero

I

All (rpal

Zero

I

11

8

..

OFFAX

rpa

NEA

,A,r

2

8

A-r

No Zero

I

I

NEA

r;A

2

8

r- A

No Zero

I

I

NEAX

rpa

2

11

No Zero

I

I

Zero

I

I

Zero

I

I

Zero

I

I

I

2

11

: :".

A- (rpal

EOA

A,r

2

8

A- r

EOA

r,A

2

8

r- A

EOAX

rpa

2

11

":

..

A- (rpal

,

IMMEDIATE DATA TRANSFER (ACCUMULATOR I

.. ,

XRI

A,bvte

2

7

A-A¥bvte

ADINC

A,bvte

2

7

A-A + byte

No Carry

I

I

SUINB

A,bvte

2

7

A-A-bvte

No Borrow

I

I

ADI

A,bvte

2

7

A-A+byte

I

I

ACI

A,bvte

2

7

A-A +bvte" CY

I

I

SUI

A,bvte

2

7

A.,.. A - bvte.':,.

I

I

sal

A,bvte

2

7

A-A- bv'te - CY

I

I

ANI

A,bvte

2

7

A - All byte

I

ORI

A,bvte

2

7

.A-AV·bvte

I

GTI

A,bvte

2

7

A- bvte-1

LTI

A,b¥te

2

7

A - byte

ONI

A,byte

2

7

All byte.

OFFI

A,bvte

2

7

All bvt'<"

NEI

A,bvte

2

7

A - byte.
',:,

EOI

,

A,bvte

2

7

..

A - byte
~

I

,}:.
,.....

• ':'(!

No Borrow

I

I

Borrow

I

I

No Zero

I

Zero

I

No Zero

I

I

Zero

I

I

263

II

Jl.PD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY

Z

IMMEDIATE DATA TRANSFER

I

XRI

,.byte

3

11

r-r ¥-byte

ADINC

,.byte

3

11

r-r+byte

No Carry

I

I

SUINB

',byte

3

11

r-r-byte

No Borrow

I

I

ADI

r,bvte

3

11

r-r+byta

I

I

ACI

,.byte

3

11

r ..... r

I

I

SUI

',byte

3

11

r+-r-byte

I

I

SBI

'. byte

3

11

r-r-byte-CY

I

I

ANI

'. byte

3

11

r

+-

r "byte

I

I

ORJ

,.byte

3

11

r

+-

rvbyte

GTI

',byte

3

1i

,-byte-1

No Borrow

I

I

LTI

" byte

3

11

,- byte

Borrow

t

,\

ONI

',byte

3

11

,1\ byte

No Zero

I

OFFI

',byte

3

11

,1\ byte

Zero

\

NEI

r,bvte

3

11

r - byte

No Zero

I

I

EOI

" byte

3

11

r -byte

Zero

I

I

+ ~yte + Cy

I

IMMEDIATE DATA TRANSFER (SPECIAL REGISTERI
XRI

sr2, byte

3

17

.,2 - s,2 ¥

ADINC

.,2, byte

3

17

sr2 ..... sr2 + byte

No Carry

I

I

SUINB

sr2, byte

3

17

sr2 ..... sr2 - byte

No Borrow

I

I

ADI

.,2, byte

3

17

.r2 +- sr2 + byte

I

I

ACI

5r2, byte

3

17

sr2 - sr2 + byte + CY

I

I

SUI

.,2, byte

3

17

sr2

sr2 - byte

I

I

SBI

sr2,bvte

3

17

.'2'~ sr2 - byte - Cy

I

I

ANI

.,2, byte

3

17

.,2 - .,2 1\ byte

I

ORI

.,2, byte

3

17

sr2 - sr2 V byte

I

GTI

.,2, byte

3

' 14

LTI

.,2, byte

3

14

ONI

.,2, byte

3

14

264

+-

sr2 - byte -

I

byte

No Borrow

I

I

.,2 - byte

Borrow

I

I

"21\ byte

No Zero

I

I

}LPD7801
INSTRUCTION GROUPS (CONT,)
MNEMONIC

OPERANDS

NO,
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY

Z

IMMEDIATE DATA TRANSFER (SPECIAL REGISTER) (CONT,)
OFFI

sr2, byte

NEI
EOI

t

3

14

sr2 /\ byte

Zero

sr2, byte

3

14

sr2 - byte

No Zero

t

I

sr2, byte

3

14

sr2 - byte

Zero

I

I

WORKING REGISTER
XRAW

wa

3

14

A~A>'«V,wa)

ADDNCW

wa

3

14

A

SUBNBW

wa

3

14

A - A- (V, wa)

ADDW

wa

3

14

ADCW

wa

3

SUBW

wa

SBBW

~

A + (V, wa)

I
I

I

.1

I

A~A+(V,wa)

!

t

14

A - A + (V, wa) + CY

t

I

3

14

A

t

t

wa

3

14

A - A - (V, wa) - CW

t

t

ANAW

wa

3

14

A -A/\ (V, wa)

I

ORAW

wa

3

14

A-Av(V,wa)

t

GTAW

wa

3

14

A -IV, wa) - 1

No Borrow

I

I

LTAW

wa

3

14

A - IV, wa)

Borrow

t

!

ONAW

wa

3

14

A /\IV, wa)

No Zero

t

OFFAW

wa

3

14

A /\ IV, wa)

Zero

!

NEAW

wa

3

14

A - IV, wa)

No Zero

t

t

EOAW

wa

3

14

A - IV, wa)

Zero

t

t

ANIW

wa, byte

3

16

IV, wa) - IV, wa) /\ byte

!

ORIW

wa, byte

3

16

IV, wa) -IV, wa) vbyte

t

GTIW

wa, byte

3

13

IV, wa) - byte - 1

No Borrow

I

t

LTIW

wa, byte

3

13

IV, wa) - byte

Borrow

I

!

ONIW

wa, byte

3

13

(V, wa) 1\ byte

No Zero

!

OFFIW

wa, byte

3

13

(V, wa) 1\ byte

Zero

I

NEIW

wa, byte

3

13

IV, wal - byte

No Zero

I

I

EOIW

wa, byte

3

13

IV, wal - byte

Zero

t

!

~

No Carry
No Borrow

A - (V, wa)

INCREMENT/DECREMENT
INR

r2

1

4

INRW

wa

2

13

r2~<2+1

Carry

t

(V, wal - IV, wa) + 1

Carry

!

265

}LPD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

SKIP
CONDITION

OPERATION

~
CY

Z

INCREMENT/DECREMENT ICONT.I
r2 - r2 - 1

Borrow

I

IV, wal- lv, wal- 1

Borrow

t

OCR

r2

1

4

DCRW

wa

2

13

INX

rp

1

7

rp ....... rp

+1

DCX

rp

1

7

rp ....... rp

~

DAA

1

4

Decimal Adjust Accumulator

t

STC

2

a

CY-1

1

CLC

2

a

CY -0

°

1

ROTATE AND SHIFT
RLD

2

17

Rotate Left Digit

RRD

2

17

Rotate Right Digit

RAL

2

a

Am + 1 - Am, AO - CY. CY - A7

t

RCL

2

a

Cm + 1 - Cm, Co - CY, CY - C7

t

RAR

2

8

Am-1-Am,A7- CY ,CY- AO

t

RCR

2

a

Cm-l-Cm,C7- CY ,CY- Co

t

SHAL

2

a

Am + 1 - Am, AO - 0, CY - A7

t

SHCL

2

a

Cm + 1 - CM, Co - 0, CY - C7

t

SHAR

2

a

Am-1-Am,A7-0,CY- Ao

t

SHCR

2

a

Cm - 1 - Cm, C7 - 0, CY - Co

t

JUMP
JMP

word

JS

3

10

1

4

PC

+-

word

PCH -a,PCL-C

JR

word

1

13

PC - PC + 1 + jdispl

JRE

word

2

13

PC - PC + 2 + jdisp
CALL

CALL

word

CALS

3

16

1

13

ISP - 11 - IPC 31H, ISP - 21IPC - 31L, PC - word
ISP-ll-IPC-1IH, ISP- 21IPC - 11 , PCH - S, PCL - C
ISP-l HPC-2IH, ISP-21-IPC-2IL
PC15 -11-00001 ,PC10 - -fa

°

CALF

word

2

16

CALT

word

1

19

ISP-ll-IPC-lIH,ISP-21-IPC-lIL
PCL-112a-2tal, PCH-1129+2tal

1

19

ISP- 11- PSW, SP - 2, ISP - 31- PC
PC - 0060H, SIRQ-1

SOFTI

266

t

~PD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

W
CY

Z

RETURN
RET

I

II

RETS

I

11+a

RETI

I

15

2

10

SKC

2

SKNC

PCl ~ (SPI, PCH
SP ~ SP - 2

~

(SP + II

PCl ~ (SPI, PCH ~ (SP + 1),
SP ~ SP + 2, PC ~ PC + n
PCl

~

(SPI, PCH

~

(SP + I I
SIRQ--{)

PSW~(SP+21, SP~SP+3,

SKIP
BIT

IV, wa1bit

Bit test

=I I

8

Skip if Carry

CY = I

2

8

Skip jf No Carry

CY

SKZ

2

8

Skip if Zero

Z = I

SKNZ

2

8

Skip if No Zero

Z=O

bit,wa

Skip if INT X = I,

SKIT

f

2

8

SKNIT

f

2

B

NOP

I

4

No Operation

EI

2

8

Enable Interrupt

DI

2

8

Disable Interrupt

HlT

I

6

Halt

SIO

I

4

STM

I

4

then reset I NT X

Skip if No INT X
otherwise reset INT X

=0

f= I
f

=0

CPU CONTROL

SERIAL PORT CONTROL

II

Start lTrigg-er) Serial I/O
Start Timer
INPUT IOUTPUT

IN

byte

2

10

AB'5.8 ~ 8,AB7-O - byte
A - OB7-O

OUT

byte

2

10

AB15-B - B,AB7-O - byte
DB7-O - A

PEX

2

II

PE'5-8 - B, PE7-0 ~ C

PEN

2

II

PE,5-12 ~ B7-4

PER

2

II

Port E A B Mode

267

JLPD7801
Program Status Word- (PSW) Operation
OPERATION
REG,MEMORY

IMMEDIATE

SKIP

D5

D4

D3

D2

DO

Z

SK

HC

Ll

LO

CY

~

0

~

0

0

~

~

0

·

0

0

·

~

~

~

0

0

~

ADD
ADC
SUB
SBB

ADDW
ADCW
SUBW
SBBW

ADDX
ADCX
SUBX
SBBX

ADI
ACI
SUI
SBI

ANA
ORA
XRA

ANAW
ORAW
XRAW

ANAX
ORAX
XRAX

ANI
ORI
XRI

ADDNC
SUBNB
GTA
LTA

ADDNCW
SUBNBW
GTAW
LTAW

ADDNCX
SUBNBX
GTAX
LTAX

ADINC
SUINB
GTI
LTI

GTlW
LTIW

ONA
OFFA

ONAW
OFFAW

ONAX
OFFAX

ONI
OFF I

ONIW
OFFIW

~

~

•

0

0

•

NEA
EQA

NEAW
EQAW

NEAX
EQAX

NEI
EQI

NEIW
EQIW

~

~

~

0

0

~

INR
DCR

INRW
DCRW

ANIW
ORIW

DAA
RAL, RAR, RCL, RCR
SHAL, SHAR, SHCL, SHCR
RLD, RRD
STC
CLC
MVI A, byte
MVI L, byte
LXI H, word
BIT
SKC
SKNC
SKZ
SKNZ
SKIT
SKNIT
RETS
All other instructions
Flag affected according to result of. operation

1

o
•

268

D6

Flag set
Flag reset
Flag not affected

~

~

t

0

0

•

~

0

~

0

0

t

•
•
•

0

0

0

I

0

0

•

0

0

1

•

0

0

0

0

•
•

0

•
•
•
•
•
•

1

0

0

1

•
•

•

~

•

0

0

•

1

•

0

0

0

0

•
•

•
•

0
0

0

0

·

p.PD7801
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70o C
RATlNGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - O.3V to +7 .OV
COMMENT: Stress abeve these listed under "Abselute Maximum Ratings" may cause permanent
damage te the device. This is a stress rating enly and functi'1nal eperatien ef the device at these er
any ether cenditiens abeve these indicated in the eperatienal sectiens ef this specificatien is net
implied. Expesure te abselute maximum rating cenditiens fer extended perieds may affect device
'
rei iabili'ty.

*Ta=25°C

DC CHARACTERISTICS

-10 te +70·C. VCC = +S.OV ± 10%
LIMITS
PARAMETER
Input Lew Veltage
Input High Voltage
Output Lew V"'lta~e
Output High Veltage

CAPACITANCE

SYMBOL MIN

TYP

MAX

UNITS

TEST
CONDITIONS

VIL

0

0.8

V

VIHI

2.0

VCC

V

Except SCK, XI

VIH2

3.8

VCC

V

SCK,Xl

V

IOL =2.0 mA

0.45

VOL
VOHI

2.4

V

IOH =-I00/LA

VOH2

2.0

V

IOH =-500/LA

Low Level Input Leakage Current

ILIL

-10

/LA

VIN =OV

High Level Input Leakage Current

ILiH

10

/LA

VIN = VCC

Lew Level Output Leakage Current

ILOL

-10

/LA

VOUT = 0.45V

High Level Output Leakage Current

ILOH

10

/LA

VOUT= VCC

VCC Pewer Supply Current

ICC

110 200

mA

Ta = 2S·C, VCC· GND = OV
LIMITS
PARAMETER

SYMBOL MIN

TYP

MAX

UNITS

Input Capacitance

CI

10

pF

Output Capacitance

Co

20

pF

Input/Output Capacitance

CIO

20

pF

TEST
CONDITIONS
fc - 1 MHz
All pins net
under test at OV

269

I'P01801
AC CHARACTERISTICS

-10 to +70·C. VCC = +5.0V ± 10%

CLOCK TIMING
LIMITS
SYMBOL

MIN

MAX

UNITS

tCYX
' tXXL

227

1000

ns

106

ns

Xl Input High Level
Width

tXXH

106

ns

oUT Cycle Time

454

o UT High Level Width

tCYoUTT;E.

tA = 500 ns

ns

150

ns

350

ns

Notes:

 dependent

AC CHARACTERISTICS
(CONT.)

T=tCY

When a crystal frequency other than 4 MHz is used (tCY<1>= 500 nsl
the above equations can be used to calculate AC parameter
velues.

CLOCK TIMING
;-------tCYX--------1

x,

272

TIMING WAVEFORMS

,u.PD7801
TIMING WAVEFORMS
(CaNT.)

~------------tCY~--------------~
t~H

(/.lOUT

READ OPERATION

!----"

-"---+~--

oIIOUT

PEa.H:;

00-7

r------!____ tAwTI

'ACTIVE ONLY WHEN 101M IS ENABLED.

WRITE OPERATION

'<>u'
PEO·IS

00-7

--------I_"wo

1,11,02

Vi10
'AW

WArf
tWTS

'ACTIVE ONLY WHEN

loiM

IS ENABLED.

273

j.l.PD7801
SERIAL I/O OPERATION
tCYK

Sl-+-t~~-

SCS ____________-'

tKCS

t

SAK _ _ _ _ _
tKSA

HOLD OPERATION
_

274

--MACHINECYCLE'-----i

·

p.PD7801
STRAIGHT LEADS

PACKAGE INFORMATION

(Plastic)

BENT LEADS

(Unit:mm)

rf'-------L-L-ii_ll~
I I.

II!

_ _ _ _ 24 _ _ _ _·

7801 DS-12-80-CAT

275

NOTES

276

NEe

NEe Microcomputers, Inc.

},(PD7802

HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
WITH 6K ROM
PRODUCT DESCRIPTION

The NEC !,PD7802 is an advanced 8-bit general purpose single-chip microcomputer fabricated with
N-Channel Silicon Gate MOS technology.
The NEC !,PD7802 is intended to serve a broad spectrum of 8-bit designs ranging from enhanced
single chip applications extending into the multi-chip microprocessor range. All the basic func-

tional blocks - 6144 x 8 of ROM program memory, 64 x 8 of RAM data memory, 8-bit ALU, 48
I/O lines, Serial I/O port,12-bit timer,and clock generator are provided on-chip to enhance standalone applications. Fully compatible with the industry standard 8080A bus structure, expanded
system operation can be easily implemented using any of the 8080A/8085A peripherals and
memory products. Total 'memory space can be increased to 64K bytes.
The powerful 140 instruction set coupled with 6K bytes of ROM program memory and 64 bytes
of RAM data memory greatly extends the range of single chip microcomputer applications. Five

level vectored interrupt capability combined with a 2 microsecond cycle time enable the !,PD7802
to compete with multi-chip microprocessor systems with the advantage that most of the support
functions are on--chip.

FEATURES

•
•

NMOS Silicon Gate Technology Requiring +5V Supply
Complete Single-Chip Microcomputer with On-Chip ROM, RAM and I/O
- 6K Bytes ROM
- 64 Bytes -RAM
- 48 I/O "Lines

•

Internal 12-8it Programmable Timer

•

On-Chip 1 MHz Serial Port

•

Five Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
Bus Expansion Capabilities

•

-

PIN CONFIGURATION

Fully 8080A Bus Compatible
58K Bytes External Memory Address Range

•

On-Chip Clock Generator

•
•

Wait State Capability
Alternate Z80™ Type Register Set

•
•

Powerful 140 Instruction Set
8 Address Modes; Including Auto-Increment/Decrement

•
•

Multi-Level Stack Capabilities
Fast 2 !,S Cycle Time

•

Bus Sharing Capabilities

PE15
!/>OUT
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
INT2
INTl
INTO
WAIT
MI

ViR
m5
PC7
PC6
PC5
PC4
PC3
PC2
PC,
PCa

SCK
SI
So
RESET
X2
Xl
VSS(OV)

4
5
6
7
a
9
10
11
12
-13
14
15
16
17
la
19
20
21
22
23
24
26
26
27
28
29
30
31
32

IlPD
7802

44
43
42
41
40
39
38
37
36
35
34
33

Vcc (+5V)
PE14
PE13
PE12
PEn
PE10
PES
PEa
PE7
PE6
PE5
PE4
PE3
PE2
PEl
PEo
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO

277

J'PD7802
PINNa.

1,49-63
2

3-10

ABO-AB15
t/>OUT

DBO-DB7

11
12

INTO
INTI

13

INT2

14

WAiT

15

Ml

16

WR

17

RD

18-25

PCO-PC7

FUNCTION

(Tri-State, Output) 16-bit address bus.
(Output) .pOUT provides a prescaled outp.ut
c\9ck for use with exte~nal 1/0 devices or
memories . .pOUT frequency is fXTAU2.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transitions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is programmable. By setting the ES bit in the Mask
Register to a I, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T 2, if active processor enters a wait
stateTw and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) RD is used as a
strobe to ~e data from external devices onto the
data bus. R D goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(I nput/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the rising edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through the SI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.

26

SCK

27

SI

28

SO

29
30

RESET

(Output) SO is the Serial Output Port. Serial data
is output on this line on the falling edge of SCK,
MSB to LSB.
(Input, active low) RESET initializes the IlPD7801.

X2

(Output) Oscillator output.

Xl
PAO-PA7

(Input) Clock Input
(Output) a-bit output port with latch capability.
(Tri-State Input/Output) a-bit programmable I/O
port. Each line configurable independently as an
input or output.

31
33-40
41-48

278

DESIGNAnON

PBO-PB7

PIN DESCRIPTION

fLPD7802
BLOCK DIAGRAM

FUNCTIONAL
DESCRIPTION

Memory Map
The ~PD7802 can directly address up to 64K bytes of memory. Except for the on-chip
ROM (0-6144) and RAM (65,471-65,535), any memory location can be used as
either ROM or RAM. The following memory map defines the 0-64K byte memory
space for the ~PD7802 showing that the Reset Start Address, Interrupt Start Address,
Call Tables, etc., are located in the Internal ROM area.
o
INTERNAL
ROM
10-61441

0

RESET

•

INTO

8

INT1

16

INT2

32

INT3

64

INTS

61"
6145

E~!~~~~LS

I

61,312)( 8

56

65,470
65,471
INTERNAL
RAM
65,535

I

SOFT I

128

LOWADDR

129

HIGH AOOR

130
131

LOWADDR
HIGH AOOR

}

t= 1

I
254
255

I

LOWADDR
HIGH ADDR

USER'S
AREA

t'·,!

279

, fLPD7802
FUNCTIONAL
DESCRIPTION
(CONT.)

I/O PORTS
FUNCTIONS

PORT
Port A

8·bit output port with latch

Port B

a·bit programmable Input/Output port w/latch

Port C

8·bit nibble I/O or Control port

Port E

16·bit Address/Output Port

Port A
Port A is an 8·bit latched output port. Data can be readily transferred between the
accumulator and the outPUt latch buffers. The contents of the output latches can be
modified using Arithmetic and Logic instructions. Data remains latched at Port A
unless acted on by another Port A instruction or a RESET Is issued.
Port 8
Port B is an 8·bit I/O port. Data is latched at Port B in both the Input or Output modes.
Each bit of Port B can be independently set to either Input or Output modes. The
Mode B register programs the individual lines of Port B to be either an Input
(Mode Bn = 1) or an OutPl!t (Mode Bn = 0)'
Port C
Port C is an 8·bit I/O port. The Mode C register is used to program the upper 6 bits of
Port C to provide control functions or to set the I/O structure per the following table.
MODE Cn = 0
PCo

Output

MODE Cn = 1
Input

PCl

Output

Input

PC2

SCS Input

Input

PC3

SAK Output

Output

PC4

To Output

Output

pe5

10iM Output

Output

PC6

HLDA Output

Output

PC7

HOLD Input

Input

Port E
Port E is a 16·bit address bus/oUtput port. It can be set to one of three operating modes
using the PE R, PEN, or PEX instructions.
•

16·8it Address Bus - the PE R instruction sets this mode for use with external I/O
or memory expansion (upto 60K bytes, externally).

• 4·Bit Output Port/12 Bit Address Bus - the PEN instruction sets this mode which
allows for memory expansion of an additional 4K bytes, externally, plus the
transfer of 4·bit nibbles.
•

280

16·Bit Output Port - the PEX instruction sets Port E to a 16·bit output port. The can·
tents of Band C registers appear on PE8.15 and PEO· 7, respectively.

j.l.PD7802
FUNCTIONAL
DESCRIPTION
(CONT.)

TIMER OPERATION

t-_o-oTO

TIMER BLOCK DIAGRAM
A programmable 12·bit timer is provided on-chip for measuring time intervals, generating pulses, and general time-related control functions. It is capable of measuring time
intervals from 4 J-lS to 16 ms in duration. The timer consists of a prescaler which
decrements a 12-bit counter at a fixed 4 J-lS rate. Count pulses are loaded into the
12-bit down counter through timer register (TMO and TM 11. Count-down operation is
initiated upon extension of the STM instruction when the contents of the down
counter are fully decremented and a borrow operation occurs, an interval interrupt
(INTTI is generated. At the same time, the contents of TMO and TM1 are reloaded
into the down-counter and countdown operation is resumed. Count operation may be
restarted or initialized with the STM instruction. The duration of the timeout may be
altered by loading new contents into the down counter.
The timer flip flop is set by the STM instruction and reset on a countdown operation.
Its output (TOI is available externally and may be used in a single pulse mode or general
external synchronization.
Timer interrupt (lNTII may be disabled through the interrupt.

SERIAL PORT OPERATION

PCsrSAK

"

~
, "
MCJ

Q

R

WR,

RD.

SERIAL PORT BLOCK DIAGRAM

281

J.L PD7802
The on·chip serial port provides basic synchronous serial communication functions
allowing the N EC IlPD7802 to serially interface with external devices.
Serial Transfers are synchronized with either the internal clock or an external clock
input (SCK). The transfer rate is fixed at 1 Mbit/second if the internal clock is used
or is variable between DC and 1 Mbit/second when an external clock is used. The
Clock Source Select is determined by the Mode C register. The serial clock (internal
or external 'SCK) is enabled when the Serial Chip Select Signal (SCS) goes low. At this
time receive and transmit operations through the Serial I nput port (SI )/Serial Output
port (SO) are enabled. Receive and transmit operations are performed MSB first.
Serial Acknowledge (SAK) goes high when data transfers between the accumulator
and Serial Register is completed. SAK goes low when the buffer becomes full after
the completion of serial data receive or transmit operations. While SAK is low, no
further data can be received.

INTERRUPT STRUCTURE
The IlPD7802 provides a maskable interrupt structure capable of handl ing vectored
prioritized interrupts. Interrupts can be generated from six different sources; three
external interrupts, two internal interrupts, and a non·maskable software interrupt.
Each interrupt when activated branches to a designated memory vector location
for that interrupt.

INT

282

VECTORED MEMORY
LOCATION

PRIORITY

TYPE

INTT

8

3

I nternal, Timer
Overflow

INTS

64

6

Internal, Serial
Buffer Full/Empty

INTO

4

2

Ext., level sensitive

INT1

16

4

Ext., Rising edge
sensitive

INT2

32

5

Ext., Rising/Falling
edge sensitive

SOFTI

96

1

Softwa re I nte rru pt

FUNCTIONAL
DESCRIPTION
(CONT.)

""PD7802
FUNCTIONAL RESE'T(Resetl
D ESCR I PTION An active low'signal on this input for more than 4 f..lS forces the f..lPD7B02
(CONT.) into a Reset condition. RESET affects the following internal functions:
•
•
•
•
•
•
•
•
•
•
•

The Interrupt Enable Flags are reset, and Interrupts are inhibited.
The Interrupt Request Flag is reset.
The HALT flip flop is reset, and the Halt·state is released.
The contents of the MODE B register are set to FFH, and Port B
becomes an input port.
The contents of the MODE C register are set to FFH. Port C becomes
an I/O port and output lines go low.
All Flags are reset to O.
The internal COUNT register for timer operation is set to FFFH and the
timer F/F is reset.
The ACK F/F is set.
The HLDA F/F is reset.
The contents of the Program Counter are set to OOOOH.
The Address Bus (PEO.15), Data Bus (DBO.7). RD, andWif go to
a high impedance state.

Once the

REG ISTE RS

RES'E'T input goes high, the program

is started at location OOOOH.

The f..lPD7B02 contains sixteen B·bit registers and two 16·bit registers.

o

15
PC
SP

o

70

7

v

A

B

C

D

E

H

L

V'

A'

B'

C'

D'

E'

H'

L'

Main

Alternate

General Purpose Registers (B, C, D, E, H, L)
There are two sets of general purpose registers (Main: B, C, D, E, H, L:
Alternate: B', C', D', H', L'). They can function as auxiliary registers to the
accumulator or in pairs as data pointers (BC, DE, HL, B'C', D'E', H'L'). Auto Incre·
ment and Decrement addressing mode capabilities extend the uses for the DE, HL,
D'E', and H'L' register·pairs. The contents of the BC, DE, and HL reglster·palrs
can be exchanged with their Alternate Register counterparts using the EXX
instruction.

283

)J.PD7802
Vector Register (V)
When defining a scratch pad area in the memory space, the upper a·bit memory
address is defined in the V·register and the lower a·bits is defined by the immediate
data of an instruction. Also the scratch pad indicated by the V·register can be used
as 256 x a·bit working registers for storing software flags, parameters and counters.

FUNCTIONAL
DESCRIPTION (CONT.)

Accumulator (A)
All data transfers between the MPD7a02 and external memory or I/O are done through
the accumulator. The contents of the Accumulator and Vector Registers can be
exchanged with their Alternate Registers using the EX instruction.
Program Counter (PC)
The PC is a 16·bit register containing the address of the next instruction to be
fetched. Under normal program flow, the PC is automatically incremented. However,
in the case of a branch instruction, the PC contents are from another register or
an instruction's immediate data. A reset sets the PC to OOOOH.
Stack Pointer (SP)
The stack pointer is a l6·bit register used to maintain the top of the stack area (last·
in·first·out). The contents of the SP are decremented during a CALL or PUSH
instruction or if an interrupt occurs. The SP is incremented during a RETURN or
POP instruction.
Register Addressing

Working Register Addressing

Register Indirect Addressing

Direct Addressing

Auto·lncrement Addressing

Immediate Addressing

Auto·Decrement Addressing

Immediate Extended Addressing

Register Addressing

~O~PC~O£!DE:...JI------t
.. 1OPERANDI

LI

The instruction opcode specifies a register r wh ich contains the operand.
Register Indirect Addressing
rp

memory

I OPCODEII-- - - - o..~1 ADD RESSII-- - - - 1.....1OPERAND I
The instruction opcode specifies a register pair which contains the memory address
of the operand. Mnemonics with an X suffix are ending this address mode.
Auto·1 ncrement Addressing
rp
10PCODEI

memory

...IADO't-RE_S_sl--I[£]"IOPERANO

I

The opcode specifies a register pair which contains the memory address of the
operand. The contents of the ragister pair is automatically incremented to point to
a new operand. This mode provides automatic sequential stepping when working with
a table of operands.

284

ADDRESS MODES

J.LPD7802
ADDRESS MODES (CaNT.)

Auto·DecrementAddressing
rp

IOPCOD E 1-1--"~I ADDfESS I

[jJ I

memory
OPERAND

I

Working Register Addressing

PC
PC + 1

o
The contents of the register is linked with the byte following the opcode to form a
memory address whose contents is the operand. The V register is used to indicate
the memory page. This address mode is useful as a short·offset address mode when
working with operands in a common memory page where only 1 additional byte
is required for the address. Mnemonics with a W suffix ending this address mode.
Direct Addressing
PC

OPCODE

PC + 1

Low Address

pC+ 2

High Address

Memory
.; operand

1

r-----....,

1 byte
2 byte

The two bytes following the opcode specify an address of a location containing the
operand.
Immediate Addressing
PC
PC + 1
Immediate Extended Addressing
PC

OPCODE

PC + 1

Low Operand

PC+ 2

High Operand

285

,uPD7802
INSTRUCTION SET

Operand Description
DESCRIPTION

OPERAND
r
r1
r2
sr

Notes:

V,A,B,C,D, E,H, L
B,C,D,E,H,L
A, B,C
PA PB PC MK MB MC TMO TM1 S

srl

PA PB.PC MK

sr2

PA PB PC MK

rp

SP, B, D,H

rpl

V,B,D,H

rpa

B,D,H,D+, H+,D-,H-

rpal

B,D,H

wa

8 bit immediate data

word

16 bit immediate data

byte

8 bit immed iate data

bit

3 bit immediate data

f

FO, F 1, F2, FT, FS,

S

1. When special register operands sr, sr1, sr2 are used; PA=Port A, PB=Port B,
PC=Port C, MK=Mask Register, MB=Mode B Register, MC=Mode C
Register, TMO=Timer Register 0, TM 1=Timer Register 1, S=Serial Register.
2. When register pair operands rp, rp1 are used; SP=Stack Pointer, B=8C,
D=DE, H=HL, V=VA.
3. Operands rPa, rPa 1, wa are used' in indirect addressing and auto-incrementl
auto-decrement addressing modes.
B=(BC), D=(DE), H=(HL)
D+=(DE)+, H+=(HL)+, D-=(DE)-, H-=(HL)-.
4. When the interrupt operand f is used; FO=INTFO, Fl=INTF1, F2=INTF2,
FT=INTFT, FS=INTFS.

286

P. PD7802
INSTRUCTION GROUPS
MNEMONIC OPERANDS

NO.
BYTES

C~OCK

CYCLES

SKIP
CONDITION

OPERATION

FLAGS
CY Z

a·BIT DATA TRANSFER
MOV

,l,A

1

4

r1

MOV

A"l

1

4

A+- r1

MOV

sr, A

2

10

sr-A

MOV

A, sr1

2

10

A-srl

,vlOV

r, word

4

17

r_ (word)

MOV

word, r

4

17

(word)-r

MVI

r, byte

2

7

MVIW

we, byte

3

13

lv, wa) - byte

MVIX

,pal, byta

2

10

I,pall - byte

STAW

wa

2

10

(V,wa)-A

~OAW

wa

2

10

A-(V,wa)

STAX

,pa

1

7

I,pa)-A

~OAX

,pa

1

7

A-Irpa)

EXX

1

4

Exchange register sets

EX

1

4

V,

B~OCK

1

13IC+l)

r

+-

A

byte

+-

A~V,A

IDE)+ - IH~)+, C - C - 1

16-BIT DATA TRANSFER
SBCO

word

4

20

Iword) - C, Iword + 1) - B

SOEO

word

4

20

Iword) - E, Iword + 1) - 0

SHLD

word

4

20

Iword) - L, Iword + 1) - H

SSPO

word

4

20

Iword) - SPL, Iword + 1) - SPH

LBCO

word

4

20

C - Iword), B - (word + 1)

LOEO

word

4

20

E - Iword), 0 -Iword + 1)

LH~O

word

4

20

~

LSPO

word

4

20

SP~

PUSH

rpl

2

17

ISP - 1)- rplH, ISP - 2)-

POP

rpl

2

15

rpl ~ - ISP)
rp'1.t:i - (SP + I), SP - SP + 2

LXI

rp, word

3

10

rp -word

1

19

C-IPC + 2 + A)
B - IPC + 2 + A + 1)

TABLE

- Iword), H - (word + 1)
-Iword), SPH - lword + 11

-

rpl~

287

J'PD7802
INSTRUCTION GROUPS (CONT.)
MNEMONIC OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY Z

ARITHMETIC
ADD

A,r

2

8

A-A+r

t

t

ADD

r,A

2

8

r-r+A

I

t

ADDX

rpa

2

11

A-A + (rpa)

I

t

ADC

A,r

2

8

A-A+r+CY

I

t

ADC

r,A

2

8

r -r

+ A +CY

I

t

ADCX

rpa

2

11

A - A + (rpal + CY

I

t

SUS

A,r

2

8

A-A- r

I

I

SUB

r,A

2

8

r .... r- A

I

I

SUSX

rpa

2

11

A- A- (rpal

I

I

SSB

A,r

2

8

A - A - r - CY

I

I

SSS

r,A

2

8

r -r - A - CY

I

I

SBSX

rpa

2

11

A - A - (rpal - CY

I

I

ADDNC

A,r

2

8

A-A+r

No Carry

I

I

ADQNC

r,A

2

8

r ..... r+A

No carry

I

t

ADDNCX

rpa

2

11

A-A + (rpal

No CarrV

I

I

SUSNS

A,r

2

8

A-A-r

No Borrow

I

I

SUSNB

r,A

2

8

r-r-A

No Borrow

I

I

SUSNBX

rpa

2

11

A-A- (rpal

No Borrow

I

I

LOGICAL

288

ANA

A,r

2

8

A-A"r

I

ANA

r,A

2

8

r - r I\A

I

ANA X

rpa

2

11

A - A "(,pal

I

ORA

A,r

2

8

A-Avr

I

ORA

r,A

2

8

r-rvA

I

ORAX

rpa

2

11

A-Av(rpal

I

XRA

A,r

2

8

A-A¥r

I

XRA

r,A

2

8

A-rVA

I

XRAX

rpa

2

11

A-A II (rpal

I

GTA

A,r

2

8

A- r - 1

No Borrow

I

I

p.PD7802
INSTRUCTION GROUPS (CONT,)
r---'

MNEMONIC OPERANDS

NO,
BYTES

CLOCK
CYCLES

FLAGS

SKIP
CONDITION

CY

Z

A - (rpa) - 1

No Borrow

t

t

OPERATION

LOGICAL (CONT.)
GTAX

rpa

2

11

LTA

A,r

2

8

A-r

Borrow

t

t

LTA

r,A

2

8

r-A

Borrow

t

t

LTAX

rpa

2

11

A- (rpa)

Borrow

I

t

ONA

A,r

2

8

AAr

No Zero

t

ONAX

rpa

2

11

A A(rpa)

No Zero

I

OFFA

A,r

2

8

AAr

Zero

I

OFFAX

rpa

2

11

A A (rpa)

Zero

t

NEA

A,r

2

8

A- r

No Zero

t

t

NEA

',A

2

8

r- A

No Zero

I

t

NEAX

rpa

2

11

A - (rpa)

No Zero

t

t

EQA

A,r

2

8

A- ,

Zero

t

t

EQA

r,A

8

,- A

Zero

t

I

EQAX

,pa

A- (rpa)

Zero

I

t

2
2

11

IMMEDIATE DATA TRANSFER (ACCUMULATOR)
XAI

A,byte

2

7

A-A 10' byt.

ADINC

A,byt.

2

7

A-A+byt.

No Carry

I

I

SUINB

A,byt.

2

7

A-A-byte

No Borrow

t

t

ADI

A,byt.

2

7

A-A+byte

I

I

ACI

A,byt.

2

7

A - A + byte + CY

t

I

SUI

A,byt.

2

7

A-A-byte

I

I

SBI

A,byt.

2

7

A-A- byt.- CY

I

t

ANI

A,byt.

2

7

A - AA byte

t

OAI

A,byt.

2

7

A - AV byte

t

GTI

A,byt.

2

7

A - byte - 1

No Borrow

t

t

LTI

A,b¥t.

2

7

A - byte

Borrow

t

t

ONI

A,byt.

2

7

AAbyt.

No Zefo

I

OFFI

A,byt.

2

7

AA byte

Zero

I

NEI

A,byt.

2

7

A - byte

No Zero

t

t

EQI

A,byt.

2

7

A- byte

Zero

t

t

t

289

II

J.L PD7802
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY

Z

IMMEDIATE DATA TRANSFER

I

r ¥ byte

XAI

r. byte

3

11

r

ADINC

r, 'byte

3

11

r-r+byte

No Carry

I

I

SUINB

r, byte

3

11

r-r-byte

No Borrow

I

I

ADI

r, byte

3

11

r-r+byte

I

I

ACI

r, byte

3

11

r +- r + byte

I

I

SUI

r, byte

3

11

r +- r - byte

I

I

S81

r, byte

3

".

r

+-

r - byte - CY

I

I

ANI

r, byte

3

11

r

+-.

r 1\ byte

I

I

OAJ

r, byte

3

11

r

+-

rv byte

GTI

r, byte

3

11

r-bvte-1

No Borrow

I

I

LTI

r, byte

3

11

r - byte

Borrow

I

I

ONI

r, byte

3

"'11

r 1\ byte

No Zero

I

OFFI

r, byte

3

11

r 1\ byte

Zero

I

NEI

r, byte

3

11

r - byte

No Zero

I

I

EOI

',byte

3

11

r - byte

Zero

I

I

+-

+ CY

I

IMMEDIATE DATA TRANSFEA (SPECIAL AEGISTER)

290

XAI

5r2, byte

3

17

sr2

+-

sr2 ¥ byte

ADINC

5r2, byte

3

17

sr2

+-

sr2 + byte

No Carry

!

I

SUIN8

5r2. byte.

3

17

sr2

+-

sr2 - byte

No Borrow

I

I

ADI

5r2, byte

3

17

sr2

+-

5r2 + byte

I

I

ACI

sr2, byte

3

17

sr2

+-

sr2 + byte + CY

I

I

SUI

5r2, byte

"3

17

sr2

+-

sr2 - byte

I

I

S81

5r2. byte

3

17

sr2 +- sr2 - byte - CY

I

I

ANI

5r2, byte

3

17

sr2

+-

sr2 1\ byte

I

OAI

1'2. byte

3

17

sr2

+-

sr2 V byte

I

GTI

5r2, byte

3

14

sr2 - byte - 1

No Borrow

I

I

LTI

5r2, byte

3

14

sr2 - byte

Borrow

I

I

ONI

sr2, byte

3

14

5r21\ byte

No Zero

I

I

,.,. PD7802
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

FLAGS
CY

Z

IMMEDIATE DATA TRANSFER (SPECIAL REGISTER) (CONT.)
OFFI

sr2, byte

3

14

5r2/\ byte

Zero

NEI

5r2, byte

3

14

sr2 - byte

No Zero

!

!

Eal

5r2, byte

3

14

sr2 - byte

Zero

I

I

XRAW

wa

3

14

A-AVIV,wa)

ADDNCW

wa

3

14

A-A+(V,wa)

No Carry

!

!

SUBNBW

wa

3

14

A - A - (V, wa)

No Borrow

!

!

ADDW

wa

3

14

A-A+IV,wa)

!

!

ADCW

wa

3

14

A -A + (V,wa) + CY

I

!

SUBW

wa

3

14

A-A-(V,wa)

I

I

SBBW

wa

3

14

A-A- (V,wa)- CW

I

I

ANAW

wa

3

14

A - A" (V,wa)

I

ORAW

wa

3

14

A-Av(V,wa)

I

GTAW

wa

3

14

A-IV,wa) -1

No Borrow

I

!

LTAW

wa

3

14

A - IV, wa)

Borrow

I

I

ONAW

wa

3

14

A" IV, wa)

No Zero

I

OFFAW

wa

3

14

A" IV, wa)

Zero

!

NEAW

wa

3

14

A - IV, wa)

No Zero

!

I

EaAW

wa

3

14

A-IV,wa)

Zero

I

!

ANIW

wa, byte

3

16

IV, wal - IV, wal" byte

I

ORIW

wa, byte

3

16

IV, wal -IV, wal Vbyte

I

GTIW

wa, byte

3

13

IV, wal- byte - 1

No Borrow

I

I

LTIW

wa, byte

3

13

IV, wa) - byte

Borrow

I

I

ONIW

wa, byte

3

13

IV, wal" byte

No Zero

I

OFFIW

wa, byte

3

13

IV, wa)" byte

Zero

I

NEIW

wa, byte

3

13

IV, wal - byte

No Zero

!

I

EalW

wa, byte

3

13

IV, wal - byte

Zero

I

I

INR

r2

1

4

INRW

wa

2

13

!

WORKING REGISTER

!

INCREMENT IDECREMENT

r2 -r2 + 1

Carry

I

IV, wal -IV, wal + 1

Carry

I

291

P. PD7802
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONDITION

~
CY Z

INCREMENT/DECREMENT (CONT.)
r2 - r2-1

Borrow

!

(V, wa) - (V, wa) - 1

Borrow

t

DCR

r2

1

4

DCRW

wa

2

13

INX

rp

1

7

rp- rp + 1

DCX

rp

1

7

rp- rp-1

DAA

1

4

Decimal Adjust Accumulator

!

STC

2

8

CY-l

1

CLC

2

8

CY-O

0

ROTATE AND SHIFT
RLD

2

17

Rotate Left Digit

RRD

2

17

Rotate Right Digit

RAL

2

8

Am + 1 - Am, AO - CY, CY - A7

!

RCL

2

8

Cm + 1 - Cm, Co - CY, CY - C7

!

RAR

2

8

Am - 1 -Am, A7 -CY, CY - AO

t

RCR

2

8

Cm- 1 - Cm, C7 - CY, CY - Co

I

SHAL

2

8

Am + 1 -Am,Ao-O,CY -A7

I

SHCL

2

8

Cm + 1 - CM, Co -0, CY - C7

I

SHAR

2

8

Am-l-Am,A7- 0 ,CY- Ao

I

SHCR

2

8

Cm - 1 - Cm, C7 - 0, CY - Co

I

3

10

1

4

JUMP
JMP

word

JB

PC -word

PCH - B, PCL - C

JR

word

1

13

PC - PC + 1 + jdispl

JRE

word

2

13

PC - PC+ 2 + jdisp

CALL

word

3

16

1

13

CALL

CAlB
CALF

word

2

16

CAlT

word

1

19

1

19

SOFT!

292

(SP 1 J - (PC 3)H, (SP 2)(PC - 3)L, PC - word
(SP - 1)- (PC - 1)H, (SP - 2)(PC-l) ,PCH -B,PC -C
(SP-l )-(PC-2)H, (SP-2)-(PC-2) l
PC15 -11-00001 ,PC10- O-f.
(SP-l )-(PC-l )H,(SP-2)-(PC-l) l
PCl-(128-2ta), PCH-,(129+2ta)
(SP-l) -PSW,SP- 2, (SP- 3) -PC
PC - 0060H, SI RQ - 1

t

po PD7802
INSTRUCTION GROUPS (CONT.)
MNEMONIC

OPERANDS

NO.
BYTES

CLOCK
CYCLES

OPERATION

SKIP
CONOITION

W
CY

Z

RETURN
RET

1

11

PCL - (SPI, PCH - (SP + 1)
SP - SP - 2

RETS

1

II+a

PCL - (SPI, PCH - (SP + II,
SP - SP + 2, PC - PC + n

RETI

1

15

2

10

SKC

2

SKNC

PCL - (SP), PCH - (SP + 11
PSW-(SP+2I, SP-SP+3, S IRQ<-{)
SKIP
Bit test

\v,wa bit
= 1)

8

Skip if Carry

CV = 1

2

8

Skip if No Carry

CV =0

SKZ

2

8

Skip if Zero

Z= 1

SKNZ

2

8

Skip if No Zero

ZoO
f = 1
f=O

BIT

bit,wa

SKIT

f

2

8

Skip if INT X = I,
then reset INT X

SKNIT

f

2

8

Skip if No INT X
otherwise reset INT X

NOP

1

4

No Operation

EI

2

8

Enable Interrupt

01

2

8

Disable Interrupt

HLT

1

6

Halt

SID

1

4

Start (Trigger! Serial I/O

STM

1

4

Start Timer

CPU CONTROL

SERIAL PORT CONTROL

INPUTIOUTPUT
IN

byte

2

10

AB15-8 - B,AB7'{) - byte
A- DB 7.{)

OUT

byte

2

10

ABI5-8 - B,AB7'{) - byte
DB7.{)-A

PEX

2

11

PEI5-8 - B. PE7'{) - C

PEN

2

11

PE15-12 - B7-4

PER

2

11

Port E A8 Mode

293

JI.

PD7802
Program Status Word (PSW) Operation
OPERATION
REG,MEMORY

IMMEDIATE

SKIP

05

04

03

02

DO

Z

SK

HC

L1

LO

CY

t

0

t

0

0

t

t

0

•

0

0

·

t

t

t

0

0

t

ADD
ADC
SUB
SBB

ADDW
ADCW
SUBW
SBBW

ADDX
ADCX
SUBX
SBBX

ADI
ACI
SUI
SBI

ANA
ORA
XRA

ANAW
ORAW
XRAW

ANAX
ORAX
XRAX

ANI
ORI
XRI

ADDNC
SUBNB
GTA
LTA

ADDNCW
SUBNBW
GTAW
LTAW

ADDNCX
SUBNBX
GTAX
LTAX

ADINC
SUINB
GTI
LTI

GTlW
LTIW

ONA
OFFA

ONAW
OFFAW

ONAX
OFFAX

ONI
OFFI

ONIW
OFFIW

t

t

0

0

•

NEA
EOA

NEAW
EOAW

NEAX
EOAX

NEI
EOI

NEIW
EOIW

·

t

t

t

0

0

t

INR
DCR

INRW
DCRW

t

t

t

0

0

•

DAA

t

0

t

0

0

t

RAL, RAR, RCL, RCR
SHAL, SHAR, SHCL, SHCR

•
•
•

0

0

0

t

•

•

0

•
•

0

BIT
SKC
SKNC
SKZ
SKNZ
SKIT
SKNIT

•

RETS

ANIW
ORIW

RLD, RRD
STC
CLC
MVI A, byte
MVI L, byte
LXI H, word

All other instructions
Flag affected according to result of operation

o
•

294

06

Flag set
Flag reset
Flag not affected

0

.'
•

0

0

0

0

1

0

0

0

1

0

•

0

•
•
•
•

0

1

•

t

•

0

0

•

•

1

0

•

0

•
•

0

•

0

0

•

0

p.PD7802
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10o e to +70o e
RATINGS* Storage Temperature ............................... -65°e to +125°e
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.3V to +7.0V
COMMENT: Stress above those listed under "'Absolute Maximum Ratings"' may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS

-10 to +70°C. VCC = +5.0V;: 10%
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage

SYMBOL MIN

LIMITS
TYP MA.X

UNITS

TEST
CONDITIONS

VIL

0

0.8

V

VIHI

2.0

VCC

V

Except SCK. Xl

VIH2

3.8

VCC

V

SCK.Xl

0.45

V

IOL = 2.0 mA

VOHI

2.4

V

IOH =-I00"A

VOH2

2.0

V

IOH =-500 "A

-10

"A

VIN =OV

VOL

Low Level Input Leakage Current

ILiL

High Level Input Leakage Current

ILiH

10

"A

VIN = VCC

ILOL

-10

"A

VOUT-0.45V

High Level Output Leakage Current

ILOH

10

ICC

"A
mA

VOUT- VCC

VCC Power Supply Current

Low Level Output Leakage Current

110 200

II
CAPACITANCE

Ta = 25°C. VCC = GND = OV
PARAMETER

SYMBOL MIN

LIMITS
TYP MAX

UNITS

Input Capacitance

CI

10

pF

Output Capacitance

Co

20

pF

Input/Output Capacitance

CIO

20

pF

TEST
CONDITIONS
fc -I MHz
All pins not
under test at OV

295

,.,. PD7802
-10 to +7O·C, Vcc

= +5.0V

AC CHARACTERISTICS

± 10%

CLOCK TIMING
LIMITS
PARAMETER

SYMBOL

MIN

MAX

UNITS

1000

ns

X1 Input Cycle Time

tCYX

227

X 1 I nput Low Level
Width

tXXL

106

ns

X1 Input High Level
Width

tXXH

106

ns

"'OUT Cycle Time

tcv",

454

"'OUT Low Level Width

tL

150

"'OUT High Level Width

tH
tr,tf

150

"'OUT Rise/Fall Time

2000

TEST
CONDITIONS

ns
ns
ns

40

ns

READIWRITE OPERATION
LIMITS
PARAMETER

SYMBOL

R15" L.E .... "'OUT L.E.

tR",

Address (PEO-15) ... Data
Input

tAD1

RD T.E .... Address

tRA

FilrL.E .... Data Input

tRD

1f[)T.E .... Data Hold
Time

tRDH

MIN

MAX

100

TEST
UNITS CONDITIONS
ns

550+500xN
200(T3); 700(T4)

ns
ns

350 + 500 x N

ns
ns

0

R15" Low Level Width

tRR

Fi1h.E .... WAIT L.E.

tRWT

450

ns

Address (PEO-15)'"
WAIT L.E.

tAWT1

650

ns

WAIT Set Up Time
(Referenced from

tWTS

290

ns

tWTH

0

ns

"'OUT L.E.)
WAIT Hold Time

ns

850+500xN

(Referenced from

"'OUT L.E.l
M1"'RD L.E.

tMR

200

ns

R15 T.E .... M1

tRM

200

ns

IO/f.if ... 1m L.E.

tlR

200

ns

1mT.E .... IO/f.if

tRI
t",w

200

tA",

100

tAD2

450

ns

Data Output -+ WFf
T.E.

tow

600+500xN

ns

WFI T.E. -+ Data
Stabilization Time

two

1SO

ns

~ress (PEO-15)-+

tAW

400

ns

tWA

200

ns

WR Low Level Width

tww

600+S00xN

ns

IOrM".... WR L.E.

tlW

SOO

ns

WR T.E ..... IOfM

tWI

250

ns

"'OUT L.E .... WR L.E.
Address (PEO-1S)'"
"'OUTT.E.
Address (PEO-1S)'"
Data Output

40

n.

125
300

ns
ns

WR L.E.

I WR T.E. -+ Address
Stabilization Time

296

tcv", = 500 ns

JL PD7802
SERIAL I/O OPERATION
PARAMETER

SYMBOL

MIN

MAX

UNIT

CONDITION

SCK Cycle Time

tCYK

800
900 4000

SCK Low Level Width

tKKL

350
400

ns
ns

SCK Input
SCK Output

SCi< High

tKKH

350
400

ns
ns

SCK Input
SCK Output

ns

Level Width

SI Set-Up Time (referenced from SCK T.E.)

tSIS

140

SI Hold Time (referenced from SCK T.E.)

tSIH

260

SCi< L.E ..... SO Delay Time

tKO

~High .... SCK L.E.

tCSK

100

SCK T.E ..... SCS Low

tKCS

100

SCK T.E ..... SAK Low

SCK Input
SCK Output

ns
180

ns
ns
ns
ns

260

tKSA

ns
ns

HOLD OPERATION
PARAMETER

SYMBOL

MIN

MAX

UNIT

HOLD Set-Up Time (referenced from
fi!OUT L.E.)

tHDS,
tHDS2

200
200

ns
ns

HOLD Hold Time (referenced from 1l0UT
L.E.)

tHDH

ns

IlOUT L.E ..... HLDA

°

tDHA

HLDA High ... Bus Floating (High Z State)

tHABF

HLDA Low ... Bus Enable

tHABE

110

100

ns

-150

150

ns

350

ns

CONDITION

tCYrI> = 500 ns

Notes:

 DEPENDENT AC PARAMETERS
PARAMETER
tRr/>

Notes:

CD

EQUATION
(1/5) T

MIN/MAX

UNIT

MIN

ns

tADl

(3/2 + N) T - 200

MAX

ns

tRA (T3)

(1/2) T - 50

MIN

ns

tRA (T4)

(3/2) T - 50

MIN

ns

tRD

(1 + N) T-150

MAX

ns

tRR

(2+N)T-150

MIN

ns

tRWT

(3/2) T- 300

MAX

ns

tAWTl

(2)T-350

MAX

ns

tMR

(1/2) T

50

MIN

ns

tRM

(1/2) T - 50

MIN

ns

tlR

(1/2)T-50

MIN

ns

tRI

(1/2) T- 50

MIN

ns

trpW

(1/4) T

MAX

ns

tM

(1/5) T

MIN

ns

tAD2

T

MIN

ns

tDW

(3/2+N)T

MIN

ns

50
150

tWD

(1/2) T - 100

MIN

ns

tAW

T- 100

MIN

ns

tWA

(1/2) T- 50

MIN

ns

tww

(3/2+N)T-150

MIN

ns

tlW

T

MIN

ns

tWI

(1/2) T

MIN

ns

tHABE

(112) T

MAX

ns

150

AC CHARACTERISTICS
(CaNT.)

N = Number of Wait States

@

T=tCY
OWERSTANOBY

t!iV SUPPLY

Vss _ _ GROUND

Operating TemprHature ..
Storage Tempel ('Itl!re (Ceramic Package)
Storage Tempel dture (Plastic Package) .

. . ..
..

Voltage on Any Pin

Power Dissipation

aOc to +70°C
-65°C to +150°C
-6SoC to +125°C
-0.5 to +7 Volts ght by '·b,t
through carry

SWAP A

(A4-71.· (AO' 31

Swap the 24-b'l n,bbles ,n the
Accumulator.

XRLA,..-data

(AI· (AI XOR data

Log,cal XOR spe£lf,ed Immediate data
With Accumulator.

XRL A, Rr

(AI ~- (A) XOR (Rr)
tor r ~ a - 7

Logical XOA contents of des,gnated
reg»te, With Accumulator.

XALA,@Rr

(AI' (AI XOR ((Rd)
tor, = 0 - 1

Logical XOR Indirect the contents of data
memory location w'th Accumulato,

1

1

0

d7

d6

dS

1

BRANCH
DJNZ Rr, addr

(Rr) +- (Rr) - 1" ~ 0 - 7
If (Rr)" a
(PC 0 - 7) +- addr

Jab addr

(PC a - 7)'" addr ,f Bb = 1
(PC), (PC) + 2 ,f Bb = a

Jump to SpeCified address if
Accumulator bit IS set.

JCadd,

(PC 0 - 7) ~ addr ,I C ~ 1
(PC)· (PCI + 2 ,f C = 0

Jump to spec,f,ed address ,I caHy flag

. 2

De£rement the specll,ed register and

b2
a7

~

bl

bO
as

84

a3

al

~

~

•

~

~

Q

~

~

~

aO

o

32
1

JFO addr

(PC 0 7) ... addr If FO '" 1
(PCI ~I(PC) + 2 If FO = 0

Jump to spec,fled address ,f Flag Fa 1$
a7

a6

as

a4

a3

a2,

a1

JF1 addr

(PC 0 - 71 +- add, If F 1 = 1
(F-C) ,. (PCI + 2 ,f F1 '" 0

Jump to speclf,ed address ,f Flag F 1 +s
set.

~

•

~

~

Q

~

~

~

(PC 8 - 101'- addr 8 - 10
(PC 0 - 7) ..... addr 0 - 7
{PC 111 •. DBF

D'rect Ju_mp to spec,f,ed address Within
the 2K address block.

al0
a7

a9
a6

a8
8S

84

0
a3

1
a2

0,
a1

0
aO

'S

'3

'2

'1

JMP addr

1

JMPP@A

{PC 0 .. 7) ..... ((A)I

Jump Ind+rect to specrf,ed address WIth
With address page.

JNC addr

(PC 0 - 7) .... addr if C '" a
(PC) +- (PC) + 2 if C '" 1

Jump to specified address if carry flag IS
low.

a7

..

JNIBF addr

(PC 0 - 7) .... addr if tBF '"
(PC) .... (PC) + 2 If ISF '" 1

Jump to specified address if input buffer
lutl flag is low

1
a7

..

'S

87

a6

as

JOBF

(PC 0 - 7) .... addr jf OBF '" 1 Jump to specified address it output
(PC) .... (PC) + 2 if OBF '" a
buffer fult flag is set.

1

o

0

..

''..
1

o

1

'2

o

'3
D
'3

.,

'1

'0

'1

'"

o

1

BYTES

C AC

FO

Fl

ISF

gBF

P. PD8041

INSTRUCTION SET (CaNT.)
INSTRUCTION CODe

MNEMONIC

FUNCTION

0.,

BRANCH
JNTO addr

(PC 0- 7) .... addr If TO '" 0
(PC) ~ (PC) +2il TO'"' 1

Jump to specified address if Test 0 is low.

JNTl addr

(PC 0 - 7) ... addr If T1 - 0
(PC) .. (PC) + 2 If Tl '" 1

Jump to specified address If Test 1 is low.

JNZ add,

(PC 0 - 7) .... addr If A '" 0
(PC)
(PC) + 2 If A '"' 0

Jump to specified address If accumulator

JTF addr

(PC 0- 7) <-addr if TF '" 1
(PC) ... (PC) + 21f TF '" 0

Jump to specified address II Timer Flag

no addl

(PC 0 - 7) ..... addr if TO " 1
(PCI - (PC) + 2 if TO '"' 0

Jump to specified address if Test 0 is a L

JTl addr

(PC 0 .. 7l .... addr if T1 = 1
(PC) ,- (PC) + 2 If Tl '" 0

Jump to spee,fled address If Test 1 'S a 1

J2 addr

(PC 0·- 7) .... addr If A '" 0

Jump to specified address if Accumulator

(PC) .- (PC) + 2 of A

is

I

0

EN'

'7
0
'7
1

'7
IS

set to 1.

'7

•

'7

,

'7
CON1'ROl

Enable the External Interrupt mput

DIS t

D.

'.
'.
''•.. '.
'6
1

'5

0

'5
1

'5

FLAGS

0,

03

02

0,

DO

"
"1
"
"

'3

"1
"1
"1

'1

'0
0

"1
"1
"1
"

'I
1

"

,

1

d3

d,

dj

dO

d3

d,

dl

dO

d3

d,

d,

dO

',. • '.
''.. '.
0

1

'7
O.

06

"1

'5
0

"

'3
'3

•

'3
0
'3

•

'3
0
'3

'1

''..
'.
'.
0

'1

0

'I
'I

0

0
'0

•

'0

Disable the Externai.!nterrupt Input

a~

SELRBO

(85) .... 0

Select Bank 0 (locations
Memory.

SEL RB1

18SJ

Select Bank 1 (locations 24

1

7) of Data

31) of

Data Memory
DATA MOVES
Mav A, ""data

(A)- data

MaV A, Ar

(M~{Rrl.r"

MOV A,@Ar

(AI

+-

((Ad);r "'0

+-

(PSW)

Move Immediate the speclflf:!d data into
the Accumulator
0- 7

0
d7

•

d.

d5

Move the contents of the deSignated

d,
1

registers Into the Accumulator

1

Move Indirect the contents of data
memory location onto the Accumulator

MaV A, PSW

(AI

MOV Rr, .. data

(Ar) .... data; r " 0 - 7

Move Immediate the specified data Into
the deSignated register.

MOV Ar, A

(Ar)~-

Move Accumulator Contents mto the
designated register

Move contents of the Program Status
Word Into the Accumulator.

(A); r=O - 7

1M;

MQV@Ar,A

((Ad)""

MOV @ Ar, .. data

({Arl) - data; r '" 0

r=O··l

MOV PSW. A

(PSW) .... (AI

Move Immediate the speCified data Into
data memory.

(PC 0 - 71 <- (AI
(A) ...· ({PC)}

Move data in the current page onto the
Accumulator

(PCO-71 ..... (AJ
(PC B -- 101 .... 011
(A) .... ({PC))

Move Program data In Page 3 Into the
Accumulator.

XCH A. Ar

(M~IArI;r=0-7

E)(change the Accumulator and
designated register's contents

xeHA.@Ar

1M -;:: ((Ad); r = 0 - 1

E)(Change Indirect contents of Accumu·
lator and location in data memory

XCHD A.@Rr

IAO-31~((Ar)}O-3));

E)(change Indirect 4-blt contents of
Accumulator and data memory.

CPL C

(C)

CPL FO

(FO) ..... NOT (FO)

Complement Content of Flag FO.

Complement Content of carry bit.

CPL Fl

IF1) -NOT IFll

Complement Content of Flag Fl

CLA e

leI

Clear content of carry bit to O.

eLA FO

(FOI <-0

Clear content of Flag 0 to O.

CLA Fl

(F1) -0

Clear content of Flag 1 to O.

320

+- (

d6

d5

1

FLAGS
NOT (C)

d5

d,
0

,
'7

Move contents of Accumulator Into the
program status w.;>rd

MOVP3 A.@ A

<-

,
d6
0

Move Indtrect Accumulator Contents
mto data memory location

1

MOVP A.@A

r '"' 0 - 1

,
d7

d,

CYCLES

BYTES

C AC

F.

F1

lBF

OBF

fL PD8041

INSTRUCTION SET (CaNT.)

FLAGS

INSTRUCTION CODE
FUNCTION

MNEMONIC

DESCRIPTION

07

D.

os

0'

Dl

02

0'

D.

CYCLES

BYTES

C

AC

F.

F1

IBF

OBF

INPUT/OUTPUT

, ,
,

ANL pp. :: data

(Ppl· (Pp) ANOdala

ANLO PP. A

{Ppl-

(Pp) AND (A 0

p

7

P

Log,cal and Immed''1te specified data
With deSignated port (1 Of 21

31

P

P

d,

d,

dO

p

p

d3

d,

d,

dO

0

0

0

"

'3

"

d7

d6

d5

d,

d3

d7

d6

d5

d,

0

0

Logical and contents of Accumulator

,,

(Al· (Ppl, p-

IN A, Pp

,

with desiQnated pon (4 - 7).

21

(nputdata from deSignated port (1
Into Accumulator

(A) ..... (DBB)

IN A, DBB

MOVO A. Pp

IA 0

3) - (Ppl:p

lA'

71- 0

MOVO PP. A

(Ppl·· A 0

=

Input strobed DBB data into
Accumulator and cJeer IBF

,

'nl0Accumuiator

7

(Ppl - (Pp) OR (A 0

31

Move contents of Accumulator to

designated port 14
GRlO PP. A

p = 4
IPp~

ORL pp. '" data

p

=

71

Move contents of deSignated port (4

7

3, p' 4

71

7

log,eal or contents of Accumulator With
deSignated port 14 71

,

Logical or Immediate specified data With
deSignated port 11
21

• IPpl OA data
1

OUT DBB, A

(DBBI (AI

OUTL pP. fJ.

(Ppl

IAI, p-

IArl·

lAd

INC Rr

IArl

lArl + 1, r

INC@Ar

IIArll· (lArll + 1,
r ~ 0

,

Output contents of Accumulator onto
DBB and set OBF.

, ,

0

Output conlents of Accumulator to
deSignated port II
21
REGISTERS

DEC Ar

IAr)

1, r

0

~

~

0

Decrement by 1 contents of deSignated
reg'ster

7

Increment by 1 contents of deSignated
register

7

,

Increment Indirect by 1 the contents of
data memory locat.on
SUBROUTINE

liSP)) • (PCI, (PSW4

CALL add.

71

Call deSignated Subroutone

(SPI' ISP) + 1
(PC 8 10)· add. 8 10
(PC 0 71- addrO 7
(PC 111· D8F
RET

(SPI· (SPI
(PC) . (ISP))

,

'9

'8

'7

'6

'5

"

'0

Aeturn from Subroutine Without
restOring Program Status Word

,

(SPI' (SP)
iPC)·· liSP))
(PSW4 7~· ((SPH

AETA

"0

Return from Subroutine restOring
Program Status Word.
TIMER/COUNTER
Enable Internal Interrupt Flag for
T.mer/Counter output

EN TCNTI
DIS TCNTI

Disable Internal onterrupt Flag lor
Timer/Counter output.

MOV A. T

1M· IT)

MOV T, A

(T).

Move contents of Timer/Counter ,nto
Accumulator

IA)

Move content: 01 fJ.ccumulator ontO
Timer/Counter.

STOP TCNT

SlOP Count for Event Counter

STAT ':::NT

Start Count for Event Counter

STAT T

Start Count for Timer
MISCELLANEOUS

Notes

I

I

NOP

No Operation performed

I

0

o

0

ill

Instruction Code DeSignations rand p form the binary representation of the Registers and Ports involved.

<%>

The dot under the appropriateJlag bit indicates that its content IS subject to change by the instruction it appears In.

®

References to the 'l.ddress and data are specified in bytes 2 and or 1 of the instruction.

@)

Numerical Subscripts appearing in the FUNCTION column reference the specific bits affected.

I

1

I

Symbol Definitions:
SYMBOL
A
AC
addr
Bb
BS
BUS
C
ClK
CNT
D
data
DBF
FO, F1
I
p
IBF

DESCRIPTION
The Accumulator
The Auxiliary Carry Flag
Program Memory Address (12 bits)
Bit Designator (b 0 7)
The Bank Switch
The BUS Port
Carry Flag
Clock Signal
Event Counter
Nibble Designator (4 bits)
Number or Expression (8 bits)
Memory Bank Flip-Flop
Flags 0,1
Interrupt
"In-Page" Operation Designator
Input Buffer Full Flag

SYMBOL
Po
PSW
Rr
SP
T
TF
TO, T1

X
#
@

$
(x)
((x))
+-

OBF
DBB

DESCRIPTION
Port Designator (p =1,2 or 4 - 7)
Program Status Word
Register Designator Ir =0, 1 or 0 - 7)
Stack Pointer
Timer
Timer Flag
Testable Flags 0, 1
External RAM
Prefix for Immediate Data
Prefix for Indirect Address
Program Counter's Current Value
Contents of External RAM Location
Contents of Memory Location Addressed
by the Contents of External RAM location.
Replaced By
Output Buffer Full
Data Bus Buffer

321

Jl. PD8041
PACKAGE OUTLINE
J.lPD8041C

(Plastic)
ITEM

A
B
C

0
E
F

G

H

I
J
K
L

M

MILLIMETERS

51.5 MAX
1.62
2.54 ± 0.1
0.5 ± 0.1
48.26
1.2MIN
2.54 MIN
O.5MIN
5.22 MAX
5.72 MAX
15.24
13.2
+ 0.1
0.25 _ 0.05

INCHES

2.028 MAX
0.064
0.10± 0.004
0.019 ± 0.004
1.9
0.047 MIN
0.10 MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.520
+ 0.004
0.010 _ 0.002

J.lPD8041D

G

~fD

'
.\

(Ceramic)
ITEM
A
B
C

0
E

F
G

H
I

J
K
L
M

322

MILLIMETERS
51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.05

INCHES
2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13 MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0.01 ± 0.0019

8041 OS-1 o.8o.CAT

NEe

NEe Microcomputers. Inc.

~PD8041A
~PD8741A

UNIVERSAL PROGRAMMABLE PERIPHERAL
INTERFACE - 8-BIT MICROCOMPUTER
D ESC R I PTiON

FEATURES

The IlPD8041 A/8741 A is a programmable peripheral interface intended for use
in a wide range of microprocessor systems. Functioning as a totally self-sufficient
controller, the IlPD8041A/8741A contains an 8-bit CPU, 1K x 8 program
memory, 64 x 8 data memory, I/O lines, counter/timer, and clock generator in a
40'pin DIP. The bus structure, data registers, and status register enable easy interface
to 8048, 8080A or 8085A based systems. The IlPD8041 A's program memory is factory mask programmed, while the IlPD8741 A's program memory is UV EPROM to
enable user flexibility.

• Fully Compatible with 8048, 8080A, 8085A and 8086 8us Structure
•
•
•
•
•
•
•

PIN CONFIGURATION

8·8it CPU with 1K x 8 ROM, 64 x 8 RAM, 8·Bit Timer/Counter,
18 I/O Lines
8-Bit Status and Two Data Registers for Asynchronous Slave·to-Master
Interface
Interchangeable EPROM and ROM Versions
Interrupt, DMA or Polled Operation
Expandable I/O
40·Pin Plastic or Ceramic Dip
Single +5V Supply

vcc

TO
x,
x2
RESET

55
CS
EA
RO
AO
WR
SYNC
DO
01
02
03
04
05
06
07
VSS

IlPD

8041A/
8741,6

T1
P27/0ACK
P26/0RQ
P25/iBF
P24/0BF
P17
P16
P15-

.r14
1'13
P12
P11
P10
VOO
PROG
P23
P22
P21
P20

323

j'PD8041A/8741A
PIN IDENTIFICATION

PIN
NO.

SYMBOL

FUNCTION

1,39

TO,Tl

Testable input pins using conditional transfer functions
JTO, JNTO, JT1, JNT1. T 1 can be made the counter/timer
input using the STRT CNT instruction. The PROM pro·
gramming and verification on the IlPD8741A uses TO.

2

Xl

One side of the crystal input for external oscillator or
frequency source.

3

X2
RESET

The other side of the crystal input.

4
5

SS

Single Step input (active-Iowl. SS together with SYNC output allows the IlPD8741A to "single-step" through each
instruction in program memory.

6

CS

Chip Select input (active-low). CS is used to select the
appropriate pPD8041 A/8741 A on a common data bus.

7

EA

External Access input (active-high). A logic "1" at this input
commands the IlPD8041 A/8741 A to perform all program
memory fetches from external memory.

8

RD

Read strobe input (active-I owl. RD will pulse low when the
master processor reads data and status words from the DATA
BUS BUFFER or Status Register.

9

AO

Address input which the master processor uses to indicate if
a byte transfer is a command or data.

10

WR

Write strobe input (active-Iowl. WR will pulse low when the
master processor writes data or status words to the DATA
BUS BUFFER or Status Re~ister.

11

SYNC

The SYNC output pulses once for each IlPD8041A/8741A
instruction cycle. It can function as a strobe for external
circuitry. SYNC can also be used together with SS to
"single-step" through each instruction in program memory.

Active-low input for processor initialization. RESJ:i is also
used for PROM programming, verification, and power down.

12-19 DO-D7 BUS

The 8-bit, bi-directional, tri-state DATA BUS BUFFER lines
by which the IlPD8041 A/8741 A interfaces to the 8-bit
master system data bus.

20
VSS
21-24, P20 -P27
35-38

Processor's ground potential.
PO RT 2 is the second of two 8-bit, quasi-bi-directional I/O
ports. P20-P23 contain the four most significant bits of the
program counter during external memory fetches. P20-P23
also serve as a 4-bit I/O bus for the IlPD8243, INPUT /
OUTPUT EXPANDER. P24-P27 can be used as port lines or
can provide Interrupt Request (lBF and OBF) and DMA
handshake lines (DRG and DACK).

25

PROG

Program Pulse. PROG is used in programming the IlPD8741A.
It is also used as an output strobe for the uPD8243.

26

VDD

VDO is the programming supply voltage for programming
the IlP08741 A. It is +5V for normal operation of the
IlP08041 A/8741 A. V DO is also the Low Power Standby
input for the ROM version.

27-34 PlO-P 17

PO RT 1 is the first of two 8-bit quasi-bi-directional I/O ports.

40

Primary power supply. VCC must be +5V for programming
and operation of the IlP08741 A and for the operation of the
IlP08041A.

324

VCC

~PD8041 A/8741 A

FUNCTIONAL
DESCRIPTION

~PD8041

A/8741 A
FUNCTIONAL
ENHANCEMENTS

The pPD8041A/8741A is a programmable peripheral controller intended for use
in master/slave configurations with 8048, 8080A, 8085A, 8086 - ~s well as most
other 8-bit and 16-bit microprocessors. The pPD8041A/8741A functions as a
totally self-sufficient controller with its own program and data memory to effectively
unburden the master CPU from I/O handling and peripheral control functions. The
pPD8041A/8741A is an intelligent peripheral device which connects directly to the
master processor bus to perform control tasks which off load main system processing
and more efficiently distribute processing functions.
The pPD8041A/8741A features several functional enhancements to the earlier
pPD8041 part. These enhancements enable easier master/slave interface and increased
fu nctionality.
1. Two Data Bus Buffers. Separate Input and Output data bus buffers have been
provided to enable smoother data flow to and from master processors.

INPUT DATA
BUS BUFFER
(8)

2. 8-Bit Status Register. Four user-definable status bits, ST 4~ST7, have been
added to the status register. ST 4-ST7 bits are defined with the MOV STS, A
instruction which·meves ac.cumulator bits 4-7 to bits 4-7 of the status register.
ST O-ST 3 bits are not affected.

FO

STe

De

D3

IBF

OBF

D1

00

MOV STS, A Instruction OP Code 90H

3.

Ri5 and iNA inputs are edge-sensitive. Status bits IBF, OBF, F1

and INT are

affected on the trailing edge at RD or WR.
AD orW"R --......."'...._ _ _ _ _ _ _ _ _ _...,d."p_ Flags affected

325

p.PD8041 A/8741 A
4. P24 and P25 can be used as either port lines or Buffer Status Flag pins. This
feature allows the user to make OBF and IBF status available externally to
interrupt the master processor. Upon execution of the EN Flags instruction,
P24 becomes the OBF pin. When a "1" is written to P24, the OBF pin is
enabled imd the status of OFB is output. A "0" written to P24 disables the
OBF pin and the pin remains low. This pin indicates valid data is available from
the ~P08041 A/8741 A. EN Flags instruction execution also enables P25 indicate that the ~PD8041 A/8741 A is ready to accept data. A "1" written to P25
enables the IBF pin and the statl!s of IBF is available on P25. A "0" written to
P25 disables the IBF pin.

MPD8041 A/8741 A
FUNCTIONAL
ENHANCEMENTS (CaNT.)

EN Flags Instruction Op code - F5H.
5. P26 and P27 can be used as either port lines or'DMA handshake lines to allow
DMA interface. The EN DMA instruction enables P26 and P27 to be used as
DRO (DMA Request) and DACK (DMA acknowledge) respectively, When a
"1" is written to P26, D RO is activated and a DMA request is issued. Deactivation of DRO is accomplished by the execution of the EN DMA instruction,
DACK anded with FlO, or DACK anded with WR. When EM DMA has been
executed, P27 (DACK) functions as a chip select input for the Data Bus
Buffer registers during DMA transfers.
EN DMA Instruction Op Code - E5H.

BLOCK DIAGRAM
eAYSTAL, LC,ORCLOCIC

MASTER SYSTEM INTERFACE

'ERIPHERAL INTEftFACE

-

RI.tOENT
11)24,,1

i-Ot-.-,.-IST-'-._--.' M~:NT
....
STACK

DATA MEMORY

'lOG _

. v. _

POWER'{

326

MOGRAM POWER JU'PL Y

'Icc --.. tlY IWPL Y
OftOUND

,uPD8041 A/8741 A

ABSOLUTE MAXIMUM
RATINGS'"

ODC to +70°C
-65°C to +150°C
-65°C to +125°C
-0.5 to +7 Volts -----IAO-------J

DATA8US
(OUTPUT)

ADDRESS BUS

~OATA VALID

.."

WRITE OPERATION - DATA BUS BUFFER REGISTER
' - -_ _ _ _ _ _ _ SYSTEM

ADOAESSBUS

WR

DATA BUS _ _..:D",A.:,;TA;.:C",A",N;::CH;:;A::;NG:::E'-_'F==D:::A:.:;TA:..V:.;A::;LI:::D===if,,___.::DA:::T:,::A.:;:CA:;N:.;C;::H:;AN:::G::,E_ _
IINPUT.

328

WRITe CONTROL

jL,PD8041A/8741A

INSTRUCTION SET
INSTRUCTION CODE

MNEMONIC

fUNCTION

DESCRIPTION

0,

0,

Os

0,

03

0,

FLA.GS

0,

AT
ADO A. ' d·,ta

IAI • data

Accumulate ••

,

the Accumuiato.

ADO A. @Ar

o.

,

ml'mo.yl}oc,)I,on to The Accumulall"

fA). jAr)

Add

IAI- IAI • IIRrI)

conl~nlS

AOOC A. R,

IAI • lel • (Ar!

Add ..... '11'1 carry the Conlenh olInI'

0

deSignated legilier 10 Ihe Accumulato'

AD[1C A.@Rr

fAt, lei' HAd)

0

,

,

0

,

"0

d.

d,

d,

d,

"

'.

ANl A, @R,

IAI AND IIRrl1
0 I

log,ca' Clnd Ind"eCI Ihe (onlenl\ of dala
memory .... ,11'1 Accumuialor

NOT IAI

Complement Ihe conlen!\ 01 fhe
AccumulalO.

•

d3

d,

d,

dO

0
d3

d,

d,

dO

IA! . 0

0

'3

d,

'I

dO

d3

d,

d,

dO

d3

d,

d,

I
dO

'J

"

"
",

"

'0

'2

"

'0

'I

'0

CLEAR Ihe Conlen[\ c,1 Ihe Accumula!Or

0

OA A

DECIMAL ADJUST IhP
AccumulalO'

0'

DfC A

DECREMENT hy 1 the acc"mulal(>'\

INC A

Ae

F.

F1

I.F

g.F

ST4.7

(0'11"''111

,

0111'11'

Incremenl by 1 Ihe accumulalO' \

ORl A, = dala

IAI OR dala

ORl A. R,

IAI OR IR,I
10' ,

0

lOQ,eal OR 0' spee,I,ed >mmt'd'ale dald
w,lh AccumulaTor

,

log.cal ORCOnle"lS 01 des,gn3lM
,eCj>\le, w,lh AccumulalO,

IAI· IAI OR flRdl
10' , 00 I

Logreal OR IndoreCI Ihe conlenlS of dala
memo,y 10Cal'On w,lh AccumUlator

AL A

IAN·ll· IANI
IAO"- (A7 '
10' N 0 0
IAN' 11- IANI, N '- 0
lAO' • lei
lei- IA71

ROlall~

•

RlC A

(AN) - IAN. 11. N
IAOI
IA7"
RRe A

SWAP A

0

•
••
•

ACCumulalO' lefl by 1 b,1 ... ,lhOul

ROtale Ac(Vmulalo, lei I by 1 b,1 Ih'O!.Igh

AOlale ACcumulator "ghl by 1 b,t
(hrough carry

IA4-71.- lAO

Swap Ihe 2 4·b'I n,bbles
Accumuialor

31

,'1

XRl A. A,

IAI· IAI XOR (Ar)
fot r "0 - 7

log.cal XOR conlenu 01 des'9"ated
teg,ste' .... ,11'1 Accumulato.

XRlA.@lA,

IAI- (AI XOR ((At))
lor t = 0 - 1

log,cal XOA Indoteel Ihe conlenl~ of dala
memory local,on w'th ACCumulal0r

DJNZ A •. add.

J8b add.
JC add.
JFOaddr
JFI add,

,

Dectement the spec,f,ed 'eg's!er and

(PCO- 71-adclr IIC ~ 1
(PCI- (PC) + 2 of C '0

Jump 10 speelfled addten If carry flag

(PCO 71 - add!' .f FO ~ 1
[PCI ~ HPCI • 2,1 FD ~ 0

Jump to $p«:.f.ed addltl'$$.f Flag FQ.s

lPC 0 71·- addt of Fl • 1
(PCI- fPCI' 2.t FI - 0

Jump to spec.f.ed add.en If Flag F 1 ,s

fPC 8 101 - add, 8
(PCO- 7)-addrO
[PC 111- O.F

_"A

CPC 0

,

'0

d,

d,

0

,
I

I
d,

,
d.

0

Jump 10 speelfled addteSS II
Accumul,to. b'l IS sel

Q"Kt Jump 10 speelf,ed addtess wllhln
the 2K addres5 blOCk

71_ !CAli

Jump .nd•• eel 10 5peclfled addtess w.th
w.th address page

(PCO- 71 .... .ad"IC .. O
IPCI'" lPCI + 2,IC ~ 1

Jump to spec,fled add,es' ,f carrv 1119 ,.

JNIBF .:tel.

IPC 0 - 71 ... .adr ,f ISF ~
fPCI'" (PCI + 2 II (SF ~ 1

Jump to specified
lull 1119 .,10Ir0\t

JOBF

(PCO-71-add.-,tOSF *1 Jump 10 5P«ifi«J add'"' If outpU!
(PCI ... (PCI + 2 .1 OaF .. 0
buff.,. full flag "Mt

JIIIC_,

d,

,

BRANCH

(Ad- (Ad I, r: 0
If (Ar! # 0
(PC 0 7) - add.
(PC 0 11 - addr .1 8b : 1
(PC! - (PC)+ 2,18b'O

JMP add,

"0

Ihe

log'cal XOR spec,l,ea ,mmed,ate della
.... >11'1 AcCumulalO'

dala

d.

ROIClle AccumulatO' roght by 1,b,1
"',Ihoul carry

(ANI - (AN. 11. N • 0
IA71 - lei
(CI- lAO)

(A) . IA) XOR data

It

d,

0

ORl A, @R,

XRl A.

e

,

lO<],CClI Clnd '-On!enl\ 01 des'gnCl'ed
'eg'''''' "',In Accurnulalo'

CPl A
CLR A.

d,

log,cal anu spt'e,!oed Imm",d'ate Data
W,lh AccumulCll0'

IA.I AND IR,)
~

d,

Add Ind<'eCl ...... 111 carr", The Conle'IIS 01
dolt" memory 10cal,On to 'he
AccumulaTO'

rAI ANOdaia

ANl A, R,

d.

Add Immediate ..... '11'1 carry the lipecd,ed

dala to the Acc",mulalOr

lor' .

BVTES

Add Ind"ect the cantllng the data

IAI • lei. dala

dala

d,
01 de\lgOlHed reg'ster 10

AQOe A, -" data

ANL A.

CYCLES

,

Add Immediau' Ihe specified 011110 the

00

ADD A. AI

D.

,-

add,", if input buff••

b,

"
"
"
'10
"

"
"
"

'.

"

''.. ',. ,
''..
''.. '.
bl

bO
I

"I

'3

"

"

'3

"I

"I

"
'8
"

,"

.., . .
.. ..
.. .
'

0
'J
0
'J

"

's

0

0

'3

"

"

'0

'3

"
",

"

II()

'I

II()

"

'I

II()

0

0

0

.,
,

'0

'3
0
'3

0

329

fLPD8041A/8741A
INSTRUCTION SET (CaNT.)
INSTRUCTION CODe

MNEMONIC

FUNCTION

D7

o.

Os

O.

FLAGS

03

0,

0,

DO

"0
"0
"0
"0
"0

"
"
"
"
"
"
"

'0
0
'0
0
'0
0
'0
0
'0
0
'0

BAA
JNTO add,

(PC 0 71· ilddr.1 TO - 0
IPCI· ,PC) + 2.! TO- 1
{PC a 71· add"fT1=a
(PC1. (PCI + "] ,I Tl

,

JNTli1('1o'

Jump to

Specified

address" Teu 0

low

IS

Jump to specified address ,f Tu! 1 ,s lOW

JNl,I(I(I,

(PC a 71 ~ add. ,I A • a
(PCI· IPCI + "] ,I A - a

Jump to specIfied

J1F ,leta,

(PC 0 71 +- add, II TF = 1
IPCI· (PC) • 2.1 TF " a

Jump 10 specifIed address ,f Timer Flag

JTO add,

(PC 0 71 .- addr ,I TO ~ 1
(PCI· (PCI • 2,1 TO ~ 0

Jump to sPecified addren.' Test

JTl ikld,

IPCO 71· add, tl Tl : 1
(PCI' (PCI' "] ,I Tl 0

Jump 10 specol,t'd address ,I Test 1 's

JZadd,

(PC 0 - 7)· addr ,f A = 0
'PCI' IPC) • "] ,f A' 0

Jump

,sset to

10

addreu,' accumulator

1

"
"
"

"0

o,~ ill

"

iii ,

specified address ,f Accumuiato.

.. 0

"

CONTROL

EN'

Enabl!.' the Elllernal Interrupt ,nput

DIS I

''.. '.
'. ,
''.. '.
',.
'.
'S
0
'S

0

'S

0

'S

0

"

"

",
"
",
",
"
"
"

d,

d,

d,

d,

dO

d,

d,

d,

d,

dO

d,

d,

d,

dO

"
"
"

'S
0
'S
'S

'3

'0

Olsable the ExternallMefrUpl mpu!

SEL RBO

(8SI

~

a

Select Bank 0 ilOC(lhOl'l4o 0 - 7) of Data

Memory.

Select Bank 0 (locations 24 - 31) of

18S)-1

SEL AS1

Oata Memory
ENDMA

Enable DMA Handshake

EN FLAGS

Enable I nterrupt to Mast.r Device
DATA MOVES
Moyt' Immediate the speed,ed data Into
the Accumulato'

MOV A.. RI

(AI.- IRrl.' • 0

,

,

0
d,

d.

dS

d,

d.

dS

MOllE' the contents of ,ne deSignated

7

reg_stefl ,nto the Accumulator

Mav A.

(0)

Mav

pSW

1,.

RI

(AI - IIRdl., • 0

Malle contents of the Program Statu5
Word on 10 Ihe Accumulator

(Rd - data. I - 0

MOV R,. A

(A,) - 1M.

([II

RI. A

MOV (ill RI,

II

Malle Ind.reCI the contenu of data
memo',; local.on .nto the Accumulator

IAI· IPSWI

MOV Rr .• data

MOV

1

dlta

I =

0

((AI)) - IAI.'

=

Malle Immed.ate Ihe speC.f,ed data .nlO
the des.gnated ,eg'Sltr

7

0

ItRdl' data, r • 0

Move Ind,rect Accumulator Contents
,nto data memo,,; locat.on

,
1

Malle Immed,alt the spec,l,ed data .010
data memo,v

IPSWI' IAI

Move contenl$ 01 AccumulatO' onto the
Ploglam $latus wa,d

MOVP A.@A

IPC 0 71- LAI
IA) - I(PCll

Mo"e dala .n Ihe current page ,nto the
Accumulator

MOVPJ A.@ A

(PC 0 7) - 1M
(PCB 101-011
IA) ~ IIPC))

Malle Program data on Page 3 .nto the
Accumulato,

XCH A. AI

(AI;:: IRIL r: 0 - 7

E_change the Accumulatol and
dn,gnattd leg,stt,s conTents

XCH A,ilRr

IA) ;: HRIJI. 150. 1

E)(chlltlge IndlrKt contenu of Accumu
Iitor and loc,l,on In data memolv

XCHQ A•• Rr

IA 0 - 3):;; IIRrll 0-311.
r a0 _1

E)(change Indirect C-b,t contenn 01
Accumullto. ancl dati memOI';

CPL C

ICI- NOT ICI

ComplemenT ContenT of call ... b,1

CPL Fa

(FOI .... NOT IFO}

Complemenl Content 01 FlaI -

-<'__.;;,':':..;,:..;:':.;;.!~:..;'o'_...JX'__,o...;~:;;;~~:;.::'o'_"'_J>- - - -<,__-"AO;.;N~";~;;;,,,--___~ - --

____-...JX

X~

_______________

VERIFV MODE TIMING
(pPDB048I8748 ONLY)
No.~, (DCond,,,on.

a

TTl.l.oyoe M I".Ao TTl. Logoc .. O........ 'bemef .
.... 1000 ....llo. 10 Vee lor CS. and 10K ..."to< 10 Vss lorAoI
S ... c.n lie a"' ........'nq. 3 MH, t._y-.:.tLC.
XYAl ... e. ......U ...... XTAl.landXTAL2,nputl.

® 'CV

339

f'PD8048/8748/8035L

INSTRUCTION SET

INSTRUCTION CODE

MNEMONIC

FUNCTION

+ data

ADD A, # data

fA) ..... (AI

AODA. AT

(A) ....... IA)+ (Ar)

D7

DESCRIPTION

D6
ACCUMULATOR

Add Immediate the specif ied Data to the
Accumulator.

re9i~ter

forr-0-7

Add co'ntents at' designated
the Accumulator.

ADOA.IiIRr

(AI ..... (AI + (lRrll
for r =0- 1

Add Indirect the contents the data
memory location to the Accumulator.

AODC A.

(AI

#

data

<-

(AI + leI + dala

0
d7

Add Immedljlte with carry the specified

ADDCA. Rr

(AI ...· IAI + leI + (Rr)
for r = 0- 7

Add with carry the contents of the
designated f!!gister to the Accumulator.

ADDCA,@lRr

(A) -fAI + lei + HRd)
for r = 0- 1

data memory location to the

0
d7

<--

(A) AND data

Add Indirect with carry the contents of

ANL A, Rr

(A) .... (A) AND (Rd
for r = 0 - 7

ANLA,@Rr
CPLA

(AI (A) AND HAd)
forr'" 0
(A) NOT (AI

CLR A

IA)-O

,

0-

0-

Logical and contents of designated
register With Accumulator.

,

DEC A

IA) •.. IA)

INCA

(A)- (A) + 1

ORL A, = data

(AI

d3

d2

d,

CYCLES

d3

d2

d,

dO

dO

do

, ,

d.

d.
0

d.

0
d3

d2

d,

d.

d.

0
d3

d2

d,

dO

0

d.

,

d3

d2

d,

dO

,
,

0
d7
0

Os

d7

d6

,

Logical and Indirect the contents of data
memory with Accumulator.
Complement the contents of the
AccumUlator.

(A) OR data

DECIMAL ADJUST the contents of the
Accumulator.
DECREMENT by 1 the accumulator's
contents.
Increment by 1 the accumulator·s
contents.

,

Logical OR speclhed Immediate data
with Accumulator

0

0

ORL A,@Rr

(A) - iAJ OR !lRd)
for r = 0 - 1

logical OR Indirect the cor('8nti of data
memory location with Accumulator.

0

0

RLA

(AN +ll-IANJ
lAO) -IA 71
for N a 0- 6
(AN + 11 ..... (AN); N = 0 - 6
IAO)-Ie)
Ie) -IA7)

·Aotate Accumulator left by 1·blt wltho}.!t
carry.

(ANI ... IAN + 1); N = 0 - 6
IA7) - lAO!.
(ANI ... (AN + 1); N = 0-6
IA,) - Ie)
Ie)·· lAO)

Rotate Accumulator right by 1·blt
without carry.

RACA

SWAP A

(A4-71": (AO - 3)

Swap the 24·blt nibbtes in the
Accumulator.

XRL A, #d.ta

IAI .... (AI XQA data

Logltal XQR speCified immediate data
with Accumulator.

XRL A,OA,

DO

d.

Logical OR contents of deSignated
register with Accumulator.

XRLA, R,

D,

,

,
d&

(A) ~- fA) OR (Rr)
for r = 0- 7

RRA

D2

0

ORLA,.Rr

RLCA

d.

D3

CLEAR the contents of the Accumulator.

DAA

<-

Logical and specified Immediate Data
with Accumulator.

D4

0

Accumulator.

(A)

d.

0

to

data to the Accumulator.

ANL A• .=data

0
d6

D.

IAI ... (AI XOA (Ar)
forr=0-7
(AI (AI XOR IIRr))
for r =0-1
0-

, ,

Rotate Accumulator left by 1·blt through
carry.

Rotate Accumulator right by l·bit
throogh carry.

, ,
d7

Logical XOR contents of designat~d
register with Accumulato,.
Logical XOR Indirect the conten1fl of data
memory location with Accumulator.

""&

,

0
d.
0

,

0

BRANCH
DJNZ Rr, addr

JBb addr
JC addr
JFOaddr

(Rrl"'(RrJ l;r '" 0- 7
If(Rr)*O:
(PC 0 - 71 ..... addr
(PC 0- 7) ....ddr if Bb = 1
(PCI ... (PC) + 2 If Bb .. 0

Decrement the speCified register and
test contents.

87

8&

8.

8,

83

82

8,

80

Jump to specified address If
Accumulator bit IS set.

b2
87

b,
8&

bO
8.

8.

82

,

8,

Jump to specified address if carry flag
is set.

82

8,

IPC 0 - 71- addr if·FO '" 1
(PCI ....)(PCI + 2 if FO = 0

se •.

, , , ,
,
, ,
, , ,

83

(PCO-71 ..... addrifC .. 1
(PCI .... (PCI + 2 if C .. 0

82

8,

82

,

8,

82

0
8,

80
0
80
0
80
0
80
0
80

Jump to specified address if Flag FO is

87

JF1 addr

(PCO-71-addrifF1 =,
(PC) ... IPCI + 2 jf F1 = 0

se'.

Jump to specified address if .Flag F1 is

87
0
87

JMPaddr

(PC8-101-addr8-10
(PCO-71-addrO-7
IPC ,"., DBF

Direct Jump to specified address within
the 2K address block.

8'0
87

86

8.

8.

0
86

8.

8,

'6

85

8.

0
83
0
83
0
83

89
86

8S
8.

0
8.

0
83

JMPP@A

IP.C 0-11- (iAil

Jump indirect to specified address with
with address page.

JNCadd.

(PCO- 71-addr ifC= 0
(PCI'" (PCI + 2 if C = 1

Ju·mp to

low.

87

~&

JNladdr

(PC 0- 71"'addr if I- 0
(PCI .... (PCI + 2 if I = 1

Jump to speCIfied address if interrupt
is low.

81

0
88

340

,
,

2·

SP~ified address if ca':~v flag is

,

8.
0
85

..

0
8,

0
83
0
83

, ,

82

8,

"2

8,

80
0
80

BYTES

FLAGS
C AC FO

F,

j.LPD8048/874818035L

INSTRUCTION SET (CaNT.)

FLAGS

INSTRUCTION CODE
MNEMONIC

FUNCTION

01

DESCRIPTION

06

Os

04

03

02

01

00

CYCL,eS

BYTes

C AC

FO

Fl

BRANCH (CaNT.)

a

a IS low

JNTO addr

(PC 0
(PC)·

7)· addr " TO "(PC) + 2 " TO" 1

JNTl addr

(PC 0
(PCl'

7) - addr " T1 ~ 0
(PCI + 2 ,f T1 .- 1

Jump to specified address If Test 1

(PC 0
(PCI

7)
addr If A '" 0
(PCI + 2 If A

Jump to specified address If accumul
.progra,n Status Word

,P-

(PC 0 7) _. addr If A =
(PC) . (PC)+2dA-=Q

JNZ addr

a

(PC 0·- 71 - addr If TF " 1

JTF addr

(PC) .

~

(PC) + 2 If TF

0

JTO addr

(PC 0 - 71-addr if TO" 1
(PC) - IPCI + 2 If TO" 0

JT1 addr

(PC 0

7)

~-

IPC) . IPC)

addr If T1 '" 1

(PC 0- 7) .-- addr If A '" 0

JZ addr

(PC)+2dA

(PCl'

0

'6

's

'4

'3

'2

'1

'0

'7

'6
0

's

'4

'3

'2
1

'1

'7

'6

'5

'4

'3

'2

'1

'0
0
'0

'7

'6

'S
1

'4

'3

'2

"

'0

'7

0
'6

'S

'4

'3

0

'2
1

'1

1
'7

'6

'S

'4

'3

'2

'1

'0
0
'0

'7

'6

'S

"

'3

'2

'1

'0

d,

d6

dS

d.

d3

d2

d1

dO

1
d7

d6

dS

1
d,

d3

d2

d,

dO

d3

d2

d1

dO

0

Jump to specified address If accumulptor

Jump to speCified address if Test 0 IS a
Jump to specified address

If

Tes! 1

IS

1

0

Jump to specified address If Timer Flag
IS set to 1

a 1.

0

2" T1

+

'7

Jump to specified address if Accumulator
is O.

0

CON1ROL

EN I

Enable the External Interrupt Input.

DIS I

Disable the External Interrupt Input.
Enable the Clock Output pin TO.

ENTO CLK
SEL MBa

(OBF) . 0

Select Bank 0 (iocatlons 0
Program Memory

SEL MBI

(oBFI

Select Bank 1 (locations 2048
Program Memory

SEL RBO

(85) . 0

Select Bank 0 (locations 0 - 7) of Data
Memory.

SEL RB1

1851· 1

Select Bank 1 (locat,ons 24
Data Memory

1

HALT

2047) of
4095) 01

31) of

Initiate Halt State

DATA MOVES
MQVA,

(AI'

data

MOV A, Rt"

IAl·

(Rrl. r

0

MOVA,@Rr

(A\ .

I!Ar)): r

=

MOV A. PSW

IAI·

IPSWI

MOV Rr,

IRrl . data: r . 0

MOV R"

data

data

(Rr)

A

MOV@Rr.

data

MOV PSW. A

0

Move Ind,rect the contents of data
memory locat,on InIO the Accumulato,

1

Move contents of the Program Status
W?rd Into the A!;cumtliator.

tAl: r

Move Immediate the specified data ,nto
the des'gnated ,eg,ster

7

0

=

Move Indirect Accumulator Content$
,nto data memory locat.on

1
1

0

IAI

IPSWI·

a

MOVP A. @ A

IPC
(AI·

MOVP3 A,@A

IPC a
71·
(PC 8
10)'
(A)' I(PC)I

71· IAI

MOVX A,@R

IAI·

((Rrll·

d,
1

d6

d5

d4

0

Move dota ,n the current page ,nto the
Accumulator.

IAI

Move Program data .n Page 3 mto the
Accumulator.

011

0

,

(AI;r . a

1

((RrD, r

XCH A, Rr

(AI

XCHA,@Rr

IAI " (IRrH: r" 0

XCHD A,@Ar

IA 0

,
~

Move Indirect the contents of external
data memory Into the Accumulator.
Move (nd'rect the contents of the
Accumulator I~to external data memory

(Ad; r "0 - 7

3)~.

1

Move Immed.ate thE' specpf'ed data Into
data memory
Move contents of Accumulator Inlo Ihe
program status word

IIPCI)

MOVX@R,A

0

Move Accumul<':tlOr Contents ,nlO the
deSignated register

7

IIRrl) . data. r

~-:.

Move the contents of the deSignated
registers Into the Accumulator

7

(AI. r - a

I(Rr)) .

MOV 01 Rr, A

1

Move Immed.ate the specpf'ed data ,nto
the Accumulator

Exchanqf> the Accumulator and
deSlqnated register's contents
Exchange Indirect contents of Accumu
lator and location In data memory

r""' 0- 1

Exchan~e Ind'rect 4·blt contents of
Accumulator and data memory

CPL C

IC) . NOT ICI

Complement CO(1tent 01 carry bit.

CPL FO

(FO) .

NOT (Fa)

Complement Content of Flag Fa

CPL Fl

IF 11 . NOT IF1)

Complement ConTent of Flag Fl

CLR C

lei

CLA FO

(Fa)'

0

Clear content of FlagO to O.

CLR Fl

IF11·

0

Clear content of Flag 1 to O.

((Rdl 0

3)}:

FlAGS

0

Clear content of carry bl! to a

353

JL

PD80C48/80C35

INSTRUCTION SET (CONT.)
INSTRUCTION CODE

MNEMONIC

FUNCTION

07

DESCRIPTION

06

05

04

03

FLAGS

02

01

DO

da

CYCLES

INPUT/OUTPUT

ANL BUS, :: data

(BUS) . (BUS) AND data

ANL pp. :=. data

(Pp) •

(Pp) AN 0 data

p

2

~

,

ANLD pp. A

(Pp) •
p -" 4

IN A, Pp

(A) .

INS A, BUS

IA! . (BUS)

MOVD A. Pp

Logical and Immediate specified data
With deSignated port (lor 2)

fPp} AND fA 0

31

7
(Pp); p - 1

2

7

(Pp).- A 0

OR L BUS, ..,- data

(BUS) . (BUSi OR data

Logical or Immediate specified data With
contents of BUS.

fPp) .- (Pp) OR fA 0

Logical or contents of Accumulator With
deSignated port (4
71.

CRLO Pp, A

OR L Pp, -= data

7

p -' 4

7

(Pp) •

(Pp) OR data

p = 1

2

DUll BUS, A

(SUS) . IAI

DUlL Pp, A

(Pp) .

(A); p -

DEC Rr

(Rr)·

(Rr)

INC Rr

(Rr)-

(Rr)+l:r~O

INC@AI

HRr))'

d5

d.

d2

d,

a
d5

,

d3

a
d6
a

1

d.

a
d2

p

d3

d6

d5

d,

d3

d2

a

a

a

d6

d5

d,

d3

d2

a

a

"

'3

,

dO

, ",

da

a

Move contents of Accumulator to
deSignated port (4
71.

31

Logical or Immediate specified data with
deSignated port (1
21

d7

P

d7

OutPut contents of Accumuiator onto
BUS,

,

p

",

71

Move contents of deSignated port 14
Into Accumulator.

MOVO Pp, A

3; p '" 4

d6

1

21

Input strobed BUS data Into Accumulator.

lA'

d7
d7

Logical and contents of Accumulator With
deSignated p'ort (4
71.
Input data from deSignated port i1
into Accumulator.

,

(A 0- 3) - (Ppl; p
7) .-- 0

1

Logical and Immedlate·specifled data
With c'ontents of BUS.

2

",

P

da
a

Outnut contents of Accumulator to
deSignated port (1
21.
REGISTERS

IAr)

r" 0

1: r - 0

(IRr))

4

7
7

Decrement by 1 contents of deSignated
rfl9,ster
Increment by 1 contents of deSignated
register

1;

Increment Indirect by 1 the contents of
data memory location

,

SUBROUTINE

(ISP))'

CALL addr

(PC), (PSW 4

7)

Call deSignated Subroutine.

ISPI· (SP) + 1

(PC 8

10)· addr 8

(PCO 7)"addrQ
(pel1)' OBF

RET

10

ISP)· ISP)
(PC)·

'8

'6

'5

'2

"

'a

Return from Subroutine Without
restoring Pro£lram Status Word

1

(ISP))

(PSW 4

'9

'7

7

ISP)· (SP)
(PCI' USP))

RETR

'10

Return from Subroutine restoring
Program Status Word.

71· ((SP))
TIMER/COUNTER

EN TeNTI

Enable Internal interrupt Flag for
Timer/Counter output,

DIS TeNT!

Disable Internal Interrupt Flag for
Timer/Counter output

MOV A. T

(A)·

IT)

MOV T, A

(II·

(A)

Move contents of Timer/Counter Into
Accumuiator
Move contents of Accumulator Into
Timer/Counter.

STOP TeNT

Stop Count for Event Counter

STAT CNT

Start Count for Event Counter

STRT T

Start Count lor Timer

NOP

No Operation performed.

MISCELLANEOUS

G)
@
@
@)

Notes

a

InstrU~\lon Code DeSignations rand p form the bmary representation of The Registers and Ports Involved
The dot under the appropriate flag bit indicates that Its content IS subject to change by the IIlstruct,on It appears In
References to the address and data are specified In bytes 2 and/or 1 of the Instruction.
Numerical Subscropts appearing in the FUNCTION column reference the specific bits affected.

Symbol Definitions:

SYMBOL
A
AC
addr

Bb
BS
BUS
C
ClK
CNT
D
data

DBF
FO, F,
I

P

354

DESCRIPTION
The Accumulator
The Auxiliary Carry Flag
Program Memory Address (12 bits)
Bit Designator (b - 0 - 7)
The Bank Switch
The BUS Port
Carry Flag
Clock Signal
Event Counter
Nibble Designator (4 bits)
Number or Expression (8 bits)
Memory Bank Flip-Flop
!=Iags 0,1
Interrupt
"In-Page" Operation Designator

SYMBOL
Pp
PSW

Rr
SP
T

TF
TO. T,
X

@

S
(xl
((xii
~

DESCRIPTION
Port Designator (p "" 1, 2 or 4 - 7)
Program Status Word
Register D'esignator (r - 0,1 or 0 - 7)
Stack Pointer
'Timer
Timer Flag
Testable Flags 0, 1
External RAM
Prefix for Immediate Data
Prefix for Indirect Address
Program Counter's Current Value
Contents of External RAM Location
Contents of Memory Location Addressed
by the Contents of External R AM Location.
Replaced By

BYTES

C

AC

FO

F1

J-LPD80C48/80C35
LOGIC SYMBOL
PORT

~1

PORT

~2

8
RESET

READ

SINGLE
STEP

MPD
SOC4S/
SOC35

WRITE
PROGRAM STORE
ENABLE
ADDRESS LATCH
ENABLE

PORT EXPANDER
STROBE

BUS

8

PACKAGE OUTLINES
J.IPD80C48C
J.IPD80C35C

(Plastic)
ITEM

MILLIMETERS

A

51.5MAX

INCHES
2.028 MAX

8

1.62

0.064

C
D

2.54±O.1

0,10 ± 0.004

E

0.5 ± 0.1
48.26

0.019 ± 0.004
1.9

F

1.2 MIN

0.047 MIN

G

2.54 MIN

0,10 MIN

H

0.5 MIN

0.019 MIN

I

5.22 MAX

0.206 MAX

J

5.72 MAX

K

15.24

L

13.2

M

0.25

0.225 MAX

II

0.600
0.520

+ D.'
0.05

0.010 +

~'.~:

J.IPD80C48D
J.IPD80C35D

(Ceramic)
ITEM
A

MILLIMETERS
51.5 MAX

INCHES
2.028 MAX

8

1.62

0.064

C

2.54 + 0.1

0.100 ± 0.004

D

D.SOiO.l

0.0197 ± 0.004

E

48.26 ± 0.2

1.900 ± 0.008

F

1.27

0.050

G

3.2 MIN

0.126MIN

H

1.0MIN

0.04 MIN

J

4.2 MAX

0.17 MAX

J

5.2 MAX

K

15.24 ± 0.1

L

13.5

M

+ 0.2
0.25

0.30 ± 0.1

0.205 MAX

0.6

-t

0.531

0.004
+ 0.008
- 0.010

0.012 ± 0.004

80C48/80C35DS-11-80-CAT

355

NOTES

356

NEe

NEe Microcomputers, Inc.

p.PD8049
p.PD8039L

HIGH PERFORMANCE
SINGLE CHIP8-BIT MICROCOMPUTERS

DESCRIPTION

F EATU R ES

PIN CONFIGURATION

The NEC /.IPDS049 and /.IPDS039L are single chip 8-bit microcomputers. The processors
differ only in their internal program memory options: the /.IPDS049 has 2K x S bytes
of mask ROM and the /.IPDS039L has external program memory. Both of these devices
feature new, high performance 11 MHz operation.
• High Performance 11 MHz Operation
• Full',' Compatible with Industry Standard S049/S039
• Pin Compatible with the./.IPD8048/S74S/S035
• :'JMOS Silicon Gate Technology Requiring a Single +5V ±10%Supply
• 1.36/.1s Cycle Time. All Instructions 1 or 2 Bytes
• Programmable Interval Timer/Event Counter
• 2K x 8 Bytes of ROM, 12S x S Bytes of RAM
• Single Level Interrupt
• 96 Instructions: 70 Percent Single Byte
• 27 I/O Lines
• I nternal Clock Generator
• Expandable with SOSOA/SOS5A Peripherals
• Available in Both Ceramic and Plastic 40-Pin Packages

TO
XTALl
XTAL2
RESET

ss

INT
EA
RD

PsEN

WR
ALE
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
Vss

/.IPD
8049/
8039L

II

Vee
Tl
P27
P26
P25
P24
P17
P16
P15 .
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P21
P20

357

J.L PD8049/8039L
The NEC IlPDS049 and pPDS039L are high performance, single component, S-bit
parallel microcomputers using N-channel sil icon gate MOS technology_ T,he pPDS049
and pPDS039L function efficiently in control as well as arithmetic applications. The
powerful instruction set eases bit handling applications and provides facilities for binary
and BCD arithmetic. Standard logic functions implementation is facilitated by the
large variety of branch and table look-up instructions.

FUNCTIONAL
DESCRIPTION

The pPDS049 and pPDS039L instruction set is comprised of 1 and 2 byte instructions
with over 70 percent single-byte. The instruction set requires only 1 or 2 cycles per
instruction with over 50 percent single-cycle.
The pPDS049 and pPDS039L microprocessors will function as stand-alone micro·
computers. Their functions can easily be expanded using standard SOSOA/SOB5A
peripherals and memories.
The pPDS049 contains the following functions usually found in external peripheral
devices: 204S x S bits of mask ROM program memory; 12S x S bits of RAM data
memory; 27 I/O lines; an S-bit interval timer/event counter; and oscillator and clock
circuitry.
The pPDS039L is intended for applications using external program memory only. It
contains all the features of the pPDS049 except the 204S x S-bit internal ROM. The
external program memory can be implemented using standard SOSOA/SOS5A memory
products.
POWER (UPPL Y

BLOCK DIAGRAM
I

IVDD

PROGRAM

SUPPLY

Ivcc
·w

flOW POWER
STANDBYI

EXPANSION TO ADDITIONAL
EXTERNAL MEMORY AND' 0

AND
PORT 1

REGISTER 1
REGISTER 2
REGISTER 3

REGISTER 6
REGISTER 7
8-LEVELSTACK
IVARIABLE WORD LENGTH)

Aee

PTIONAl SECOND
EGISTEA BANK

ACCStT TEST

CONTROL AIIIO TIMING

INTERRUPT

PAOMIEXPANOER
STROBE

ADDRESS PROORAM SINGLE READ WRITE
MEMORY
STEP
STROBES
ENABLE

STROBEl
CYCLE

358

RESIDENT DATA MEMORY

(128 x 81

fL' PD8049/8039L
PIN IDENTIFICATION

PIN
FUNCTION

NO.

SYMBOL

1

TO

2

XTAl1

One side of the crystal, lC, or external frequency source. (Non·TTl
compatible VIH')

3

XTAL2

The other side of the crystal or LC frequency source. For external
sources, XTAl 2 must be driven with the logical complement of
the XTAl 1 input.

4

RESET

Active low input from processor initiali~ation. RESET is also used for

Testable input using conditional transferfunctionsJTOand,JNTO. The
internal State Clock (ClK) is available to TO using the ENTO ClK
instruction. TO can also be used during programming as a testable flag.

PROM programming verification and power·down (non·TTl com·
patible VIH).
5

SS

Single Step input (active·low). SS together with ALE allows the
processor to "single-step" through each instruction in program
memory.

6

INT

7

EA

Interrupt input (active·low). INT will start an interrupt if an enable
interrupt instruction has been executed. A reset will disable the inter·
rupt. INT can be tested by issuing a conditional jump instruction.
External Access input (active·high). A logic "1" at this input com·
mands the processor to perform all program memory fetches from
external memory.

8

RD

9

PSEN

READ strobe outputs (active·low). RD will pulse low when the proces·
sor performs a BUS READ. m5 will also enable data onto the
·processor BUS from a peripheral device and function as a READ
STROBE for external DATA MEMORY.
Program Store Enable output (active·low). PSEN becomes active only
during an external memory fetch.

10

WR

WR ITE strobe output (active·low). WR will pulse low when the
processor performs a BUS WR ITE. WR can also function as a WR ITE
STROBE for external DATA MEMORY.

11

ALE

Address Latch Enable output (active·high). Occurring once each cycle,
the falling edge of ALE latches the address for external memory or
peripherals. ALE can also be used as a clock output.

12·19

DO·D7 BUS

8-bit, bidirectional port. Synchronous reads and writes can be per-

formed on this port using RD and WR strobes. The contents of the
DO·D7 BUS can be latched in a static mode.
During an external memory fetch, the DO·D7 BUS holds the least
significant bits of the program counter. PSEN controls the incoming'
addressed instruction. Also, for an external RAM data store instruction the DO·D7 BUS, controlled by ALE, R15 and WR, contains
address and data information.
20

VSS

21·24,
35·38

P20,P27:
PORT 2

Processor's GROUND potential.
Port 2 is the second of two 8-bit quasi~bidirectional ports. For external
data memory fetches, the four most significant bits of the program
counter are contained in P20·P23' Bits P20,P23 are also used as a
4·bit I/O bus for the "PD8243,INPUT/OUTPUT EXPANDER,

25

PROG

PROG is used as an output strobe for "PD8243's during I/O expan·
sian. When the "PD8049 is used in a stand·alone mode the PROG pan
can be allowed to float.

26

VDD

VDD is used to provide +5V to the 128 x 8 bit RAM section. During
normal operation V CC must ~Iso be +5V to provide power to the other
functions in the device. During stand·by operation VDD must remain
at +5V while VCC is at ground potential.

27·34

P10,P17:
PORT 1

39

T1

40

VCC

Port 1 is one of two 8·bit quasi·bidirectional ports,
Testable input using conditional transfer functions JTl and JNT1. T1
can be made the counter/timer input using the STRT CNT instruction.
Primary Power supply. VCe. is +5V during normal operation.
"

359

II

J.L PD8049/8039L
o°C to +70°C
-65°C to +150°C
. -65°Cto+125°C
- 0.5 to +7 Volts CD
. . . . . . .. 1.5 W

Operating Temperature . . . . . . . . . .
Storage Temperature (Ceramic Package) .
Storage Temperature (Plastic Package) .
Voltage on Any Pin
Power Dissipation
Note:

CD

ABSOLUTE MAXIMUM
RATINGS*

With respect to ground.

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
'Ta = 25°C
Ta '" O°C to +70°C;

Vee'" VOD '" +5V

± 10%;

DC CHARACTERISTICS

Vss '" OV
LIMITS
SYMBOL

PARAMETER

MIN

TYP

MAX

VIL

-0.5

Input High Voltage
(AI! Except XTAL 1, XTAL 2. RESET)

VIH

2.0

Vee

V

VIHl

3.8

Vee

V

Input High Voltage

(RESET, XTAL 1. XTAl 2)
Output Low Voltage (BUS. AD.

0.8

TEST CONDITIONS

UNIT

Input Low Voltage
(AU Except XTAL 1, XTAL 2)

V

WR. PSEN. ALE)

VOL

0.45

V

IOl = 2.0 mA

Output Low Voltage (All Other
Outputs Except PROG)

VOLl

0.45

V

IOL=1.6mA

Output Low Voltage (PROG)

VOl2

V

IOL

= 1.0 rnA

VOH

2.4

V

IOH

= -lOO"A

VOHl

2.4

V

IOH = -50 "A

Output High Voltage (BUS, RD,
WR, PSEN. ALE)
Output High Voltage (AI! Other
Outputsl
Input Leakage Current
(Tl. EA. INT)

III

Output Leakage Current
(BUS, TO - High Impedance State)

IOl

Power Down Supply Current
Total Supply Current

-

0.45

I'

±10

"A

VSS'; VIN .; Vee

±lO

"A

Vee;;' VIN;;' VSS + O.45V

IDD

25

50

mA

Ta"" 2S"C

IDO + ICC

100

170

mA

Ta = 25°e

LOGIC SYMBOL
PORT #1

s

PORT #2

RESET

READ

SINGLE
STEP

WRITE
I'PD

B049/
8039L

PROGRAM STORE
ENABLE
ADDRESS LATCH
ENABLE

sus

360

s

PORT EXPANOER
STROBE

}L:PD8049/803IL
AC CHARACTERISTICS

READ, WRITE AND INSTRUCTION FETCH - EXTERNAL
DATA AND PROGRAM MEMORY
0' C to +70"C; VCC

Ta

VDD ~ +5V ± 10%; VSS ~ OV

c

LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

ALE Pulse Width

tLL

150

ns

Address Setup before ALE

tAL

70

ns
ns

Address Hold from ALE

tLA

50

Control Pulse Width IPSEN, RD, WRI

tcc

300

ns

Data Setup before WR

tnw

250

ns

Data Hold after WR

two

40

Cycle Time

tCY

1,36

15,0

Data Hold

tOR

0

100

ns

PSEN, RD to Data In

tRD

200

ns

Address Setup before WR

tAW

Address Setup before Data In

tAD

400

ns

Address Float to RD, PSEN
Notes

CD
@
@

For Bus Outputs CL

=

=

ns

200

CL=20pF@

I'S

ns

-40

tAFC

For Control Outputs: CL

TEST
CONDITIONS

UNIT

ns

80 pF

150 pF

tCY = 1,361's

PORT 2 TIMING
Ta

=

O'c to +70'C; Vcc

=

+5V ± 10%; VSS

=

OV
LIMITS

PARAMETER

SYMBOL

MIN

TYP

TEST
MAX

UNIT

CONDITIONS

Port Control Setup before Failing

Edge of PROG

tcp

100

ns

tpr:

60

ns

Port Control Hold after Failing

Edge of PROG
PROG to Time P2 I nput must be
Valid

tpR

Output Data Setup Time

top

200

Output Data Hold Time

tpD

20

Input Data Hold Time

tPF

0

PROG Pulse Width

tpp

700

ns

Port 2 110 Data Setup

tPL

150

ns

Port 2 1/0 Data Hold

tLP

20

ns

TIMING WAVEFORMS

650

ns
ns
ns

150

ns

II

t---~tLL~-tCY-~·1
ALE

~

~I____________~I--~L_

FLOATING

BUS

INSTRUCTION FETCH FROM EXTERrlAL MEMORY

361

J.L PD8049/8039L
ALE

L

--1

FLOATING

FLOATING

BUS

READ FROM EXTERNAL DATA MEMORY

ALE

BUS

-'

L

FLOATING

FLOATING -

WRITE TO EXTERNAL MEMORY

'--______1

ALE
EXPANDER PORT

-_ ... tDP

OUTPUT

PCH
I

PORT 20-3 DATA

EXPANDER PORT

PORT CONTROL

!
INPUT

PCH

PROG--------------------------------~

PORT 2 TIMING

362

----

a4

"3

1
"2

a,

aO

d6

il5

"4

ilJ

"2

J,

aO

il6

il5

14

"3

1
;02

,q

,10

I,

,

Within

ildd,e~~

tJ,

b2
a7

0

aa

0

wlih
!I':lIj

1\

363

,.,. PD8049/8039L
INSTRUCTION SET (CONT.)
FLAGS

INSTRUCTION CODe

MNEMONIC

FUNCTION

DESCRIPTION

07

05

D.

03

02

0,

DO

'6

'5

'0

'3

'2

'1

'6
0
'6

'5

'0

'2

'1

'5
0
'5

'0

'3
0
'3
0
'3
0
'3

'0
0
'0

06

BRANCH (CQNT.)

JNTO addr

(PC 0 -- 71· add!' if TO - 0
(PCi .- (PC) + 2 If TO'" 1

Jump to specified address II Test 0 IS low.

JNT1 addr

(PC 0 -. 7) ~- addr If Tl ~ 0
(PC)- (PC) + 21f T1 1

Jump to specified address

JNZ addr

{PC 0 7\· addr If A .. 0
(PC)· (PC) t 21f A 0

Jump to

(PC 0 7) - addr if TF ~ 1
(PC)· (PC) t 211 TF 0

Jump to sfjl!cilled address If Timer Flag
IS set to 1

JTF addr

~pecdll;ld

If

Test t

IS

low.

address If accumulator

1

'7

JTO addr

(PC 0 . 7i -, addr if TO = 1
(PC)~· (PC) + 2 If TO "'- 0

Jump to specified address If Test 0 IS a

(PC 0 7)· addr If T1 = 1
(PC)· (PC) t 2 If T1 0

Jump to speCified address " Test 1 IS a 1.

JZ addr

(PC 0 7)·-addr if A '" 0
(PC)' (PC) + 2 If A 0

Jump to specified address if Accumulator

'5
0
'5

'0

'3

'2

'1

'6

'0

'3

'2

'1

'0

d7

0
d6

d5

dO

d3

d2

dl

dO

d7

0
d6

d5

dO
0

d3

d2

dl

dO

d7

d6

d5

0
d3

0
d2

0
dl

dO

'7

1

'5

'.
'0

1

'2

'1

1

'2

'1

1

'7
is O.

'6
0
'6

'2

'1

'0
0
'0
0
'0
'0
'0

'7

JTl addr

EN I

'7
0
'7

'7
CONTROL

'6

1

Enable the External Interrupt ,'(lput.

DIS I

Disable the External Interrupt input.

ENTO eLK
SEL MBO

Enable the Clock Output pin TO.

a

(OBF)·

Select Bank 0 (iocations 0
Program Memory.

2047) of

SEL M8l

(OBF)· 1

Select Bank 1 (locatiOns 2048
Program Memory.

SEL RBO

18S) - 0

Select Bank 0 {locations 0 - 7) of Data
Memory.

SEL RSl

(8SI· 1

Select Bank 1 (locations 24

4095) of

31) of

Data. Memory,
DATA MOVES
MOV A, "data

(A): data

Move Immediate the speCified data Into
the Accumulator'.

MOV A, Rr

(AI-

MOV A,@Rr

(A) - ((Rrli;

MOV A, PSW

(Af - (PSWI

MOV Rr, ."': data

(Rr)· data; r

MOV Rr, A

(Rrl-- (A};

(Rrl;r

0

Move the conte!"'ts of the deSignated
registers Into the Accumulator.

7

r '" 0

1

Move Indirect the contents of data
memory location Into the Accumulator.
Move contents of the Program Status
Word mto the Accumulator.

=

0

Move Immediate the speCified data Into
the deSignated register.

7

r '" 0

7

Move Accumulratlon performed.

MISCELLANEOUS

Notes'

IWR)

90

80

WR Delay from Failing Edge of Clock to WA High

IDH'I·!WRl

100

Pulse Width to WA Low

Iw(WALl

MI Delay from RIsing Edge 01 Clock 10 MI Low

'DL(MJ)

DQ

100

MI Delay from Rls.ng Edge of Clock to MI High

'DH(MI)

130

100

RFSH Delay from Rising Edge of Clock to AFSH low

tDL(RF)

180

130

RFSH Delay from RIsing Edge of Clock 10 RFSH High

'OH(RF)

WAIT Setup Time to Failing Edge of Clock

Is(WTl

HALT Delay Time from Failing Edge of Clock

to(HT)

INT Setup Time 10 RIsing Edge 01 Clock

'sIlT)

50 pF

CL

=

30pF

CL

~

50 pF

120
70

300

300

80

80
80

'wINML)

80

BUSRO Selup Time to R,slng Edge of Clock

Is(BO)

80

8USAK Delay hom Rising Edge of Clock to BUSAK low

'OL(BA)

120

100

BUSAK Delay from Failing Edge of Clock to BUSAK High

tDH(BA)

110

100

RESET Setup Time to R'slng Edge of Clock

's(AS}

Delay 10 Floal (MREQ, IORG. RD and WR)

tFIC)

MI Stable Pnor to IORO (Interrupt Ack_)

'm,

I

~

80

150
70

50

90

CL" 50pF

60
80

100

®

Cl

@>

@

Pulse Width, NMI Low

NOles:

Cl- 200pF

(j)

.!'&'df

Any Hold Time for Setup Time

10AG Delay from Failing Edge of Clock to 10RO low

50 pF

CL

0

@
@

Data Output Delay

Dala Slable Prior

90

Q)

'"

Address Siable from AD or WR Dunng Float

CONDITIONS

110

30

Address Siable from AD or WR

TEST

UNIT

®

Ll + Ir ·50 (40)'
tcaf ~ Iw ('I>Ll + Ir -45 (6Q)"
Idem ~ Ie 170 (2101'
Idc! '" Iw (¢Ill + Ir -170 (2101'
tcdf~ ('~Ll + tr 70 (80)'
tVII (MRLl ~ tc 30 (40)"
tw (MRH) " tw ('I.H) + If 20 (30)"

Rl + 2.1 k!1
FROM OUTPUT <>-~----+---I.---i
UNDER TEST

tw (WRI " Ic -30 (401'
Imr"' 2tc + tw I'I-H) + If 65 ISO)"
IC = tw (

RD

-r---\.---L
_ _ _-

WAIT

-'

\.._----

MI
-+--------t---~IN

Memory Read or Write Cycles
This diagram illustrates the timing of memory read or write cycles other than an op
code fetch (Ml cycle). The function of the MREO and RD signals is exactly the same
as in the op code fetch cycle. When a memory write cycle is implemented, the MR EO
becomes active and is used directly as a chip enable for dynamic memories, when the
address bus is stable. The WR line is used directly as a RIW pulse to any type of semiconductor memory, and is active when data on the data bus is stable.
\ - - - - Memory Read Cycle.----o~--- Memory Write Cycle



WR

-l----+----HIN

DATA OUT

:.JL- - - -- -:.-:..-_ TL -

372

fL PD780
TIMING WAVEFORMS
(CaNT.)

Input or Output Cycles
This illustrates the timing for an I/O read or I/O write operation. A single wait.state
(TW) is automatically inserted in I/O operations to allow sufficient time for an I/O
port to decode its address and activate the WAIT line, if necessary.
T,

- ~

'I'

~

T,

T3

~~
Jc

PORT ADDRESS

} Read

WAIT

-

-

-- ----- :n:- -

-r----

"iN'
---

Cycle

-- ---

WR
}

OUT

Write

Cycle

,
Interrupt Request/Acknowledge Cycle
The processor samples the interrupt signal with the rising edge of the last clock at the
end of any instruction. A special Ml cycle is started when an interrupt is accepted.
During the Ml cycle, the 10RO (instead of MREO) signal becomes active, indicating
that the interrupting device can put an 8-bit vector on the data bus. Two wait states
(TW) are automatically added to this cycle. This makes it easy to implement a ripple
priority interrupt scheme.
Last M CYcle

- - o f Instruction

-_-+-o---------~ M I - - - - - - - - - - - -

INT
AO-A15

REFRESH

PC

MI

MREO
10RO

-r-----~------_t------_t------4-------t_--_1JiNr----WAIT

-----r----

----

==-= r- -------- _-'::_-=-_TL : :- ==:=

RD

I NSTR UCTION SET

The following summary shows the assembly language mnemonic and the symbolic
operation performed by the instructions of the IlPD780 and IlPD780-1 processors.
The instructions are divided into 16 categories:
Miscellaneous Group
Rotates and Shifts
Bi t Set, Reset and Test
Input and Output
Jumps
Calls
Restarts
Returns

8-Bit Loads
16-Bit Loads
Exchanges
Memory Block Moves
Memory Block Searches
8-Bit Arithmetic and Logic
16-Bit Arithmetic
General Purpose Accumulator and Flag Operations

The addressing Modes include combinations of the following:
Indexed
Register
Implied
Register Indirect
Bit

Immediate
Immediate Extended
Modified Page Zero
Relative
Extended

373

#L PD780

TIMING WAVEFORM

~

AO-15

AO-A1S

00_7

r-

OUT

M1

FiFSH

MREci

AD

WR

iORQ

AD

Note:

374

 100®
nn nnn nnn
nn nnn nnn

a

7

2

001
bbb

1
1

!

19

Compare location (HLl and ACC,
decrement H l and Be

110
nnn

!

rrr@

I

1

I

I@ l CD l

1

1

11
10

101
101

101
001

!@ ICD I

1

1

11
10

101
111

101
001

375

INSTRUCTION SET TABLE
(CaNT.)

fLPD780
SYMBOt.lC
OPERATlaN

MNEMONIC
CPI

A-IHll
HL ....... HL+ 1

NO.
BYTES

OESCRIPTION
Compare joca~ion (HLl and ACe,
increment HL and decrement Be

2

Compare location (HLI and ACe,
increment HL, decrement Be
Repeat until Be'" c

2

NO. T
STATES
16

BC - BC - 1
CPIR

A-IHLI
HL-HL+ 1

BC-BC-l
until
A=(HL)orBC=O

CPL

A-A
(- r - 1

DEC (lY +dl

!lY + dl- !lY + dl

DECIX

Complement ACe (1'5 comp.)

1

4

Decimal adjust ACe

1

4

IHLI ~ IHLI - 1
!IX + dl - (IX + dl - 1

Decrement Reg. r
Decrement loco (HLl
Decrement loc. !IX + dl

4
11
23

1

Decrement loc. IIY +dl

23

IX -- IX - 1

Decrement I X

2

10

DECIY

IY -IY-l

Decrement IY

2

10

OECss

5S ...... S5 -

Decrement Reg. pair 5S

1

6

DI

IFF -0

Disable interrupts

1

4

DJNZ, e

B +- B-1 if B '" 0
continue if B f 0
PC - PC + e

Decrement B and jump relative If

2

8

EI

IFF -1

Enable interrupts

1

4

EX ISPI. HL

H~

ISP+ 11
L-ISPI

Exchange the location (SP) and HL

1

19

EX ISPI. IX

IX H ~ ISP "1
IX L ~ ISPI

Exchange the location (SP) and IX

2

23
23

1

B=O

EX ISPI. IY

IYH~ ISP+ 11
IY I. ··ISPI

Exchange the location (SP) and IY

2

EX AF, AF'

AF - AF'

Exchange the contents of AF, AF'

1

4

EX DE. Hl

DE - HL

Exchange the contents of DE and HL

1

4

EXX

BC- Be'
DE ~ DE'

Exchange the contents of BC, DE, HL
with contents of BC', DE', HL',
respectively

1

4

HL-HL'

HALT

Processor Hal ted

HAL T (walt for Interrupt or reset)

1

4

1M 0

Set Interrupt mode 0

2

8

1M 1

Set

2

8

1M 2

Ime~p..!pt

rT'ode 1

I

Set Interrupt mode 2

2

IN A. Inl

A -- (n)

Load ACe with input from device n

2

11

IN '. ICI

,-ICI

Load Reg. r with input from deVice

2

12

B

ICI
INC IHLI

IHLI-IHLI + 1

Increment location (HLI

1

11

INC IX

IX -IX + 1

Increment IX

2

10

INC IIX + dl

(IX + d)

Increment location (IX + d)

3

23

INC IY

IV ....... IV + 1

Increment IV

2

10

INC IIY +dl

(ly + d)

Increment location llY + d)

3

23

<-

<-

(IX + d) + 1

(ly + d) + 1

INC r

r ---r + 1

Increment Reg. r

1

4

INCss

ss-ss+ 1

Increment Reg. pair ss

1

6

IND

IHLI-ICI
B - B'-l
HL-HL-l

Load location (HL) with input from
port (e), decrement HL and B

2

16

376

·

Z

·

FLAGS
PIV S

OP COOE
76 543 210

N

H

I2
INTE
DBIN
WR
SYNC
VCC

1
2
3
4
5
6
7
S
9
10

,",PO
118080AF

12
13
14
15
16

27
25

17

18
19
20

21

All
A14
A13
A12
A15
A9
AS
A7
A6
A5
A4
A3
VDD
A2
AI
AO
WAIT
READY
<1>1
HLDA

II

Rev/l

383

ILPD8080AF
The IlPD8080AF contains six 8-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit. The IlPD8080AF also provides
decimal arithmetic capability and it includes 16-bit arithmetic and immediate operators
which greatly simplify memory address calculations, and high speed arithmetic
operations.

FUNCTIONAL
DESCRIPTION

The IlPD8080AF utilizes a 16-bit address bus to directly address 64K bytes of
memory, is TTL compatible (1.9 mAl, and utilizes the following addressing
modes: Direct; Register; Register Indirect; and Immediate.
The IlPD8080AF has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (LI FO) stack to store/retrieve the contents of the
accumulator, the flags, or any of the data registers.
The IlPD8080AF also contains a 16-bit stack pointer to control the addressing of this
external stack. One of the major advantages of the stack is that multiple level interrupts can easily be handled since complete system status can be saved when an interrupt occurs and then restored after the interrupt is complete. Another major advantage
is that almost unlimited subroutine nesting is possible.
This processor is designed to greatly simplify system design. Separate 16-line address
and 8-line bidirectional data buses are employed to allow direct interface to memories
and I/O ports. Control signals, requiring no decoding, are provided directly by the
processor. All buses, including the control bus, are TTL compatible.
Communication on both the address lines and the data lines can be interlocked by
using the HOLD input. When the Hold Acknowledge (HLDA) Signal is issued by the
processor, its operation is suspended and the address and data lines are forced to be in
the FLOATING state. This permits other devices, such as direct memory access channels (DMA), to be connected to the address and data buses.
The IlPD8080AF has the capability to accept a multiple byte instruction upon an inter·
rupt. This means that a CALL instruction can be inserted so that any address in the
memory can be the starting location for an interrupt program. This allows the assignment of a separate location for each interrupt operation, and as a result no polling is
required to determine which operation is to be performed.
NEC offers three versions of the IlPD8080AF. These processors have all the features
of the IlPD8080AF except the clock frequency ranges from 2.0 MHz to 3.0 MHz.
These units meet the performance requirements of a variety of systems while maintaining software and hardware compatibility with other 8080A devices.
A8 0-15 (THREE STATE)

AB _
LATCH

BUFFER

a IN/QECREMENTER
PC (16\

SP It6)
TIMING

a CONTROL

STATE CNTR

CVCLE CNTR

FLAG REGISTER
BIT 7- S:SIGN
81T 6 - Z:ZERO
BIT5-0:AL.WAYS·O·
alT 4 - ACY:AU)CILIARY CARRY

81T 3- O·AL.WIIYS·O·
BIT2-P:PARITY

81T I -I AlWAYS "IBITO-CV.CARRY

384

HIli
0(11

DECOD£R

UB)
EI8i

-TEMPORARY REGISTER
DBO_7 (THREE STATEI

BLOCK DIAGRAM

J.L PD8080AF

PIN IDENTIFICATION

PIN
NO.

SYMBOL

1,
25.27,
29·40

A15 - AO

NAME

Address 8us
(output three-

state)

FUNCTION

The address bus is used to address memory (up to 64K S·bit words)
or specify the I/O device number (up to 256 input and 256 output
devices), AO is the least significant bit.

2

VSS

Ground (input)

Ground

3·10

D7 - DO

Data Bus (input/
output three-state)

The bidirectional data bus communicates between the processor,
memory, and 1/0 devices for instructions and data transfers. Dur-

ing each sync time, the data bus contains a status word that
describes the current machine cycle. DO is the least significant bit.
11

Vas Supply Voltage

Vss

'-5V ± 5%

(input)

12

RESET

Reset !input)

If the RESET signal is activated, the program counter is cleared.

After RESET, the program starts at location a in memolY. The
INTE and HLDA flip·flops are also reset. The flags, accumulator,
stack pointer, and registers are not cleared. (Note: External syn·
chronization is not required for the RESET input signal which
must be active for a minimum of 3 clock periods.)
13

HOLD

Hold (input)

HOLD requests the processor to enter the HOLD state. The HOLD
state allows an external device to gain control of the /lPD8080AF
address and data buses as soon as the ,uPD8080AF has completed
its use of these buses for the current machine cycle. It is recog·
nized under the following conditions:
The processor is in the HALT state.
The processor is in the T2 or TW stage and the READY signal
IS active.
As a result of entering the HOLD state, the ADDR ESS BUS
(A15 - AO) and DATA BUS (07 - 00) are in their high imped·
ance state. The processor indicates its state on the HOLD
ACKNOWLEDGE (HLDAI p;n.

··
14

INT

15

¢2

16

INTE

17

Interrupt Request
(input)

The ,uPDB080AF recognizes an interrupt request on this line at
the end of the current instruction or while halted. If the
pPD80BOAF is in the HOLD state, or if the Interrupt Enable
Hip-flop is reset, it will not honor the request.

Phase Two (input)

Phase two of processor clock.

Interrupt Enable
(output)

INTE indicates the content of the internal interrupt enable flipflop. This flip·flop is set by the Enable (EI) or reset by the
Disable (01) interrupt instructions and inhibits interrupts from
being accepted by the processor when it is reset. INTE is automatically reset Jdisabling further interrupts) during T 1 of the
instruction fetch cycle (M 1) when an interrupt is accepted and
is also reset by the RESET signal.

DSIN

Data Bus In
(output)

DBIN indicates that the data bus is in the input mode. This
signal is used to enable the gating of data onto the ,uPD8080AF
data bus from memory or input ports.

lS

WR

Write (output)

WR is used for memory WR ITE or I/O output control. The data
on the data bus is valid while the WR signal is active (WR ::= 0).

19

SYNC

Synchronizing Signal
(output)

The SYNC signal indicates the beginning of each machine cycle.

20

VCC

VCC Supply
Voltage (input)

+5V ± 5%

21

HLDA

Hold Acknowledge
(output)

HLOA is in response to the HOLD signal and indicates that the
data and address bus will go to the high impedance state. The
HLDA signal begins at:
T3 for READ memory or input operations.
The clock period following T3 for WRITE memory or
OUTPUT operations.
In either case, the H LOA appears after the rising edge of ¢1 and
high impedance occurs after the rising edge of ¢2.

CD

··
22

¢1

Phase One (input)

Phase one of processor clock.

23

READY

Ready (input)

The READY signal indicates to the /-IP08080AF that valid memory or input data is available on the ,uPDB080AF data bus.
READY ;s used to synchronize the processor with slower memory
or t/O devices. If after sending an address out, the ,uPD80BOAF
does not receive a high on the READY pin, the ,uPDB080AF enters
a WAIT state for as long as the READY pin is low. (READY can
also be used to single step the processor.)

24

WAIT

Wait (output)

The WAIT signal indicates that the processor is in a WAIT state.

28

VDD

VDO Supply Voltage

+12V ± 5%

(input)

Note_

CD After the EI inuruction, the ,..PD8080AF accepts interrupts on the second instruction follOllvtng the EI. ThiS
allo'NS proper execution of the RET instruction if an interrupt operation is pending after the service routine.

385

II

J.L PD8080AF
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature (Ceramic Package). . . . . . . . . . . . . . . . . .. _65°(; to +150°C
Storage Temperature (Plastic Package). ;. . . . . . . . . . . . . . . . . .. _40°C to +125°C
All Output Voltages
-0.3 to +20 Volts
All Input Voltages
-0.3 to +20 Volts
Supply Voltages Vce, VDD and VSs·(1) . . . . . . . . . . . . . . . . . -0.3 to +20 Volts
Power Dissipation. . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .. 1.5W
Note:  VIH internal active pull-up resistors will
®
'@

be switched onto the data bus.
Minus (-) designates current flow out of the device.
AI supply/ATa = -0.45%fC.

CAPACITANCE

Ta = 25°C, VCC = VDD = VSS = OV, VBB = -5V.
LIMITS
PARAMETER

386

SYMBOL MIN TYP MAX

Clock Capacitance

Cti>

I nput Capacitance

CIN
CaUT

Output Capacitance

17

6
10

25
10
20

UNIT TEST CONDITIONS
pF
pF
pF

Ic· 1 MHz

Unmeasured Pins
Returned to Vss

~PD8080AF
AC CHARACTERISTICS
fJPD8080AF

Ta '"

aOc to +70°C, Voo =

+12V ± 5%,

Vee = +SV

± 5%,

Vss = -5V ± 5%, Vss = av,

unless otherwise

specified.
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Clock Period

'CY@

O.4S

2.0

,usee

Clock Rise and Fall Time

tr,tf

0

50

nsec

¢1 Pulse Width

'1

60

nsec

4>2 Pulse Width

'2

220

nsec

Delay 1 '0 2

'01

0

nsec

Delay q,2 to 4>1

'02

70

nsec

Delay 4>1 to 2

'OD@

220

osec

120

nsec

140

nsec

'OF

nsec

TEST CONOITIONS

nsec
CL"l00pF

Signal Output Delay From ¢1,

or <1>2 (SYNC, WR. WAIT,
HLOAI

'OC@

DBIN Delay From t:/>2

'OF@

Delay for I nput Bus to Enter
Input Mode

'01

Data Setup Time During 4>1 and
OSIN

'OSl

30

nsee

Data Setup Time to ¢2 During
OBIN

'OS2

150

nsec

25

CD

CL" 50 pF

Data Hold Time From ¢2 During

CSIN

'OH

INTE Output Delay From

ct>2

'IE

CD
®

CD

nsec
200

CL - 50 pF

nsec

READY Setup Time During cP2

'RS

120

nsec

HOLD Setup Time to ¢2

'HS

140

nsec

tNT Setup Time During ¢2
(During $1 in Halt Mode)

'IS

120

nsec

INT, HOLOI

'H

0

nsec

Delay to Float DUring Hold
(Address and Data Bus)

'FO

Address Stable Prior to WR

'AW@

Output Data Stable Prior to WR

'OW@

Output Data Stable From WR

'WO®

Address Stable from WR

'WA®

HLDA to Float Delay

'HF

WR to Float Delay

'WF ®

Address Hold Time after DBIN
during HLDA

'AH

Hold Time from 4>2 (READY,

Notes:

2 + '<1>2 + 'f2 + '02 + 'rl
TYPICAL
f).

>

~

'"0

+10

...

0

"

-10

...i'

0
 'CY

/

/

......... SPEC

o

+50

+100

a CAPACITANCE (pH
(CACTUAL - CSPEcl

387

II

,...PD8080AF
Ta

= O°C to +70°C, VOO = +12V

± 5%,

Vee = +5V ± 5%, Ves = -5V

± 5%,

Vss = av, unless otherwise

specified.
LIMITS
PARAMETER

MAX

UNIT

0.32

2.0

,usee

0

25

SYMBOL

MIN

Clock Period

tCY@

Clock Rise and Fall Time

tr,tf

411 Pulse Width

tl

50

nSec

TYP

rEST CONOITIONS

nsec

(/>2 Pulse Width

t2

145

nsec

Delay 1 to 2

tDl

0

nsec

Delay 2 to 1

tD2

60

nsec

Delay 411 to 4>2 Leading Edges

tD3

60

nsec

Address Output Delay From 1>2

tDA@

150

nsec

Data Output Delay From ¢2

tDD@

180

nsec

110

nsec

130

nsec

tDF

nsec

CL = 50 pF

Signal Output Delay From 1/)1,

or 2 (SYNC. WR. WAIT.
HLDA)

tDC@

DBIN Delay From 2

tDF@

Delay for Input Bus to Enter
Input Mode

tDI

25

CD

CL = 50 pF

Data Setup Time During ¢1 and

DBIN

tDSl

10

nsec

tDS2

120

nsec

Data Setup Time to 412 During

DBIN
Data Hold Time From

rp2

During

CD

CD

DBIN

tDH

INTE Output Detay From ¢2

tiE ~

READY Setup Time During ¢2

'RS
tHS

90

nsec

120

nsec

tiS

100

nsec

0

nsec

HOLD Setup Time to cfJ2

nsec

200

nsec

CL - 50 pF

tNT Setup Time During 2
(for all modes)

Hold Time from ¢2 (READY,

INT, HOLD)

tH

Delay to Float During Hold
(Address and Data Bus)

tFD

Address Stable Prior to WR

tAW@

Output Data Stable Prior to WR

tDW@

®
®

Output Data Stable From WA

tWD@

7

Address Stable from WR
HLDA to Float Delay

tWA
tHF (6)

8

nsec

WR

tWF

®

9

nsec

-20

nsec

to Float Delay

Address Hold Time After DBIN
during HLDA

120

0

tAH @

nsec
nsec
nsec
nsec

CL = 50 pF: Addre..,
Data

nsec

CL = 50 pF: WR,
HLDA, DB IN

Notes Continued:

@

The following are relevant when interfacing the .uPDB080AF to devices having VIH

= 3.3V.

a. Maximum output rise time. from O.BV to 3.3V = 100 ns at CL = SPEC.
b. Output delay when measured to 3.0V = SPEC +60 ns at CL = SPEC.
c. If CL oF SPEC, add 0.6 ns/pF if CL > CSPEC. subtract 0.3 ns/pF (from modified delay) if

CL

388

AC CHARACTERISTICS

MPD8080A F-1

< CSPEC.

fLPD8080AF
AC CHARACTERISTICS
J.lPD8080AF-2

Ta '"

o°c to

+70°C, VOD = +12V ± 5%,

Vee

==

+5V ± 5%,

Vss

=

-5V ± 5%,

Vss av,
=:

unless otherwise

specified.

LIMITS
PARAMETER

MAX

UNIT

0.38

2.0

~sec

0

50

nsee

SYMBOL

MIN

Clock Period

'Cy@

Clock Rise and Fall Time

tr,tf

$1 Pulse Width

'¢1

60

nsee

$2 Pulse Width

t¢2

175

nsee

Delay $1 to 1/>2

tOl

0

nsee

Delay 1 to $2 Leading Edges

t03

Address Output Delay From 1/J2

tOA

TYP

TEST CONOITIONS

nsee

70

ell
ell

175

nsee

200

nsee

Data Output Delay From <1>2

too

Signal Output Delay From 1>1,
or ¢2 (SYNC, WR, WAIT,
HLOAI

toc

DBIN Delay From 1>2

tOF

ell
ell

Input Mode

tOI

CD

Data Setup Time During 411 and
081N

tOSl

20

tOS2

130

nsee

CD

nsee

25

120

nsee

140

nsee

tOF

nsee

CL=l00pF

CL = 50 pF

Delay for Input Bus to Enter

nsee

Data Setup Time to $2 During

OBIN
Data Hold Time From $2 During

OBIN

tOH

CD

_'! E ell

INTE Output Delay From $2

---_._---------

200

nsee

READY Setup Time During $2

'RS

90

nsee

HOLD Setup Time to cp2

'HS

120

nsec

tNT Setup Time During ¢2
(for all' modes)

'IS

100

nsec

'H

0

nsec

CL - 50 pF

Hold Time from 2 - 140
130
2tCY
t r¢2
t03
110
2tCY
t03
tr2 - 170
17u
tCY
'03
'r2
150
t03
tr2
'CY

If not HLOA, two = tWA" t03 + tr¢2 + 10 ns, If HLOA, tWO" twA" 'WF,
tHF" t03

+ 'r2 - 50 ns.

'WF" t03 + t r¢2 - 10 ns,

389

JoLPD8080AF
PROCESSOR STATE
TRANSITION DIAGRAM

RESET

YES

CD
HOLD
I MODE

'---~()-o---"-

- -

I
I
I
.J
RESET HLTA

Notes:

390

~

INTE F/F IS RESET IF INTERNAL INT F/F IS SET.
INTERNAL INT F/F IS RESET IF INTE F/F IS RESET.
IF REQUIRED, T4 AND T5 ARE COMPLETED SIMULTANEOUSLY
WITH ENTERING HOLD STATE.

TIMING WAVEFORMS

G)

(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V.
"0" = 1.0V; INPUTS "1" = 3.3V. "0" = 0.8V; OUTPUTS "1" = 2.0V. "0" = 0.8V.J

" _ _ _ _- - J

"

r
. . IDA

7

"0

.~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - _ _ • _ _ _ _ _ A
r------~-

...

'AW
...

.- too -;

°

~~

--X __ _

A'S-AO

tOI

_

X _________ ::

0

. . ':tS~sT _

SYNC _ _ _ _ _ _ _ _ _ _~=

.... toe

..

:-

tDD~
-

-+-

-

-.

-

twA

----_._----- ~_--------- I -.

1.....

------ .....~~.~
'ow'

~u·

~

---+- -...

-~

two

1-

'AH

DBIN ______________________________~-J
.. tOF

WR

-----------

--ltDC

READY
r"-'HF

WAIT

IDe

..

~.

HOLD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : _ - tHS __

_lloe

-1-1'---+--1

HWA

'NT

-

~----;_--------------------115 : - '

'H ~ _,1_

Notes:



INSTRUCTION CODE 2
MNEMONIC'

DESCRIPTION

07

06

Os

04

03

02

0,

eloele

DO

eve.as 3

*~

INSTRUCTION CODE 2

~

MNEMONIC'

DESCRIPTION

MOVE

MOV,' ,

Mov~

o
d

Move Immed,a!e to ,e9"le,
MVI M,D8

,

l;XI8,016

LOdO immed"l1e ,eq's!",

LXI 0,016

load ,mmed,ale reg"'er

LXI H,D16

pair DE
Load Immed',l1e ,eqlSlel

p,'" Be

n

1

"

Move ,mmedl,l1e to memory

06

Os

04 03

02

0,

Clock

DO

eye'lsl

LOAD REGISTER PAIR

'eql'lP' 10 rpq1'1~r

Moveregtswr wrT1emory
Move memory to req,ster

07

0

'0

,

0

o
o
o

0

0000000

INCREMENT "DECREMENT
'flcremenlreg,ste r
Dec.emefll reqlster
tocrementmemo,y

" "
d

o

o

Decrement memory

,

-_R_'G~'_ST_'_R_TO~A~C~CU~M~U~L_AT~O_R________________~

,

0

,

0

ANA s

AND reg'Sle, "'t!h A

1

XRA s

e,cluslve OR Reg'11e,

Push reglSl!!r

Pdlr

BC

PUSHD

Push reg'SI!!r

p~"

DE

PUSH H

Push reg,stel pair HL
1

Push A and

0

a

1

o

0

o

,

,

0

,

OR req"le' w"h A
Compdre ,eglsler w,lh A

SBID8

o

on slack

Pop regtster pair BC all

POP D

Pop reg,sTer palf DE off

o

,

,
o

0

0

0

1

0

,

0

,

1

0

a

""

POP PSW

Pop A and flags off Slack

a

1

'0

PAD B

Add BC to HL

,

DADSP

Add Stack Po,nter !O Hl

0000100

Add DE to HL

o

a

o

0
0

a
0

0
1
,

1

a

1

0
INCREMENT REGISTER PAIR

Add Immed'~le 10 A
Add Immed,ale 10 A wllh

1

1

0

'0
0

0

1

'0

,
,

0
0

,

0

INX B
INX 0

0

1

0

,
1

1

a

0000001

Incremem DE
Increment HL
Increment Stack Poonter

a

a

a

1

0

0

1

0010001

o

0

DECREMENT REGISTER PAIR

0
DCX 0
DCX H
I)CX SP

,

AND Immediate With A
E~clus've OR Immediate

,

Oecremem BC

000010

Decrement Stack POln!er

a
o

1

a

1

0

,

o

0

,

o

,

0

,

REGISTER INDIRECT
,

ORI DB

0

DOUBLE ADO

,

AND memory With A
Exclus've OR memory
wllh A
OR memory wllh A
Comp"'e memory With A

Subtract ,mmedla1e tram A
SUblldC1lmmed'dle from A

fla~.

POP B

IMMEDIATE TO ACCUMULATOR
AOI DB

0

Pop register pair HL off

MEMORY TO ACCUMULATOR
Add memory 10 A
Add memory to A wllh
Cdrry
Subtract memory from A
Subtract memory from A

1

eo,

,

with A

ORA M

1

",,[1\

ca"y
,
Subtract ,,,glster from A
Subtract ,eglsTe, t'om A

ADC M

0

PUSH

r-___________________
Add '''!l,S(er to A
Add r~q,\!er 10 A

o

Po,m/!,

,

0

0

STAX B
STAX 0

OR Immed,ate wllh A
Compare Immediate w'Ih A

Store A ~t
Slore A at
Load A at
Load A at

ADDR
AD DR
ADDR
ADDR

on
In
tn
,n

BC
DE
BC
DE

00000010

o
o

0

0

0

0

o

0

,

0

,

0

,

0
0
0

1

a

1

ROTATE
Rotate A lefl, MSB to
carrl'lB_blll
Rotate A ri9h1, LSB 10
ca"v IB-bltl
Rotate A leflthrough
carry IS-bill
Rotate A fIght Through
CaffY IS-b'tl

DIRECT

o

0

0

0

o

0

0

1

o

0

STA ADDR
LOA ADOR
SHLD AODR

1

JNZ 'ADDR
JZ ADDR
JNC ADDR
JC ADDR

JP ADDR
JM AODR

uncond'tlonal
on not ~ero
On zero
On nO carry
on carry
on parity odd
On parl1y even
on Posl!lve
On minus

a

0

1

1

000010
o 0 1 0 1 0
o 1 0 0 1 0
o 1 1 0
1

a

a

0

o

1
0

0
0

1

1
1

0
0

o
a

,

SPHL

CZ ADOR
CNC ADDR
CC ADOR
CPO ADDR
CPE ADDR

o

o

1

1

0

,

0

0

0

o

1
1

0

Exchange top of stack
and HL
HL!o Stack Po,nter
HL to Program Counter

RM

I

'6

1

0
,

,

0

0

1
0

1

"

5
5

"

STC

Set carry

DAA
NO'

Complement carry
Decimal adJust A
No operation
Halt

0

o

II

1

0

o

o

,

o

a

0
1

1

0

1
1
1
1
1

0
0
0
0

a
a

MISCELLANEOUS

0

11/17

a

11/17

0

11117
11117

a
0
0

11/17

11/17

Complement A

HeT

0

o
o

0

o

,

,

,

0

,

,
C;

,

0

o a
o 1

0

0

1

0

11117

o

R"

a

0
1
0
1

a

1

NOTes

I-______________________R_'_TU_R_N________________________-I 10peran~ ~y::,~I:~;~:~s or expreSSion

R'

0

RST A

o

1----------------------------------------------------1
RZ

1
1
1

Exchange DE and HL

froput
Output
Enable Interrupts
DlSable,nterrupT ..

'N A
OUT A

o

CMADDR

RNC
RC
R'O

1
0

HL dtrect
Hl dlrec1

INPUT/OUTPUT

CALL
Call uncond,t,oroal
Call on not zero
Call on ~ero
Callan nO carry
Call On carry
Call on parl!y odd
Callan panty eV!!n
Callan POiltlV!!

A direct
A direct

MOVE REGISTER PAIR
XCHG

Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump

Store
Load
Store
Load,

Return
Return
Return
Return
Return
Return
Return
Returro

On not zero
on uro
on no carry
on carr,;
on p~"ty odd
onparoty even
on poso!lve
on monu5

1
1

0
0

1

0

o

0
0
0
1

0
1
0

0

a
a

a

5111

0
0

0
0

5111
5111

1

5111
5111

o

5,11
5/11

1

o
1

0

a

51,1

~ = SOurce regisTel
d ~ deSTinaTioro register
PSW ~ ProceSSOr STaTu~ Word
SP ~ Stack Poonter
08 ~ B-b,t daTa quanli!,;, e.p,esSlon, or
constant, always B2 of on5Truct,on
016 - lS-b,T data quantity, el(pre~5;on, Or
conStant, always 83B2 of instrucT,on
ADOR - lS-b,t"Memory address expression

2~~~ :r_sslsl~ ~Oe~~r~~; 1~ ~.010 a

- 011 E - 100 H -

lTwo possible cycle times IS/II) ond'cate
instrllction cycles dependenT on cond,noro
!tags,
4. _ flag af1ecled

_ flag nOT affected
reset
.et

a - flag
I

= flag

393

jLPD8080AF
One to five machine cycles (M 1 -- M5) are required to execute an instruction. Each
machine cycle involves the transfer of an instruction or data byte into the processor
or a transfer of a data byte out of the processor (the sole exception being the double
add instruction). The first one, two or three machine cycles obtain the instruction
from the memory or an interrupting I/O controller. The remaining cycles are used to
execute the instruction. Each machine cycle requires from three to five clock times
(T 1 - T5). During tPl • SYNC of each machine cycle, a status word that identifies the
type of machine cycle is available 01) the data bus.
Execution times and machine cycles used for each type of instruction are shown
below.
CLOCK TIMES
(MINIMAX I

MACHINE CYCLES EXECUTED

INSTRUCTION

®

AST X and PUSH AP

PCA5



INR M and DCA M

PCA4

MVIM

PCA4

MVI A; ADI; ACI; SUI;
SBI; ANI; XAI; ORI; CPI

PCR4

MOV M,A

PCR4

EI; 01 ADD R;
ADC A;SUB R;
SBB R; ANA R; XRA A;
OAA A; CMP R; ALC;
AAC; RAL; RAA;
DAA; CMA; STC;
CMC; NOP; XCHG

PCR4

0

Clock

In

X2

470

~II I r> I
X1

Clock

In

Note:

STATUS OUTPUTS

 50% DC

Input frequency must be twice the internal operating frequency.

The Status Outputs are valid during ALE time and have the following meaning:

Halt
Write
Read
Fetch

51

SO

0
0

0
0

These pins may be decoded to portray the processor's data bus status.

403

II

I-' ,PD8085A
The J,lPD8085A has five interrupt pins available to the user. INTR is operationally the
same as the 8080 interrupt request, three (3) internally maskable restart interrupts:
RESTART 5.5, 6.5 and 7.5, and TRAP, a nonmaskable restart.

PRIORITY

RESTART
ADDRESS

INTERRUPT

Highest

TRAP

2416

RST 7.5

3C16

I

RST 6.5

34 16

I

RST 5.5

2C16

I

INTERRUPTS

INTR

Lowest

INTR, RST 5.5 and RST 6.5 are all level sensing inputs while RST 7.5 is set on a rising
edge. TRAP, the highest priority interrupt, is nonmaskable and is set on the rising edge
or positive level. It must make a low to high transition and remain high to be seen, but
it will not be generated again until it makes another low to high transition.
Serial input and output is accomplished with two new instructions not included in the
8080: RIM and SIM. These instructions serve several purposes: serial I/O, and reading
or setting the interrupt mask.
The R 1M (Read Interrupt Mask) instruction is used for reading the interrupt mask and
for reading serial data. After execution of the R 1M instruction the ACC content is as
follows:

I
,SERIAL
DATA
IN

I

PENDING
INTERRUPTS

INTERRUPT
MASKS
INTERRUPT
ENABLE

Note: After the TRAP interrupt, the R 1M instruction must be executed to preserve the
status of IE.
The SIM (Set Interrupt Mask) instruction is used to program the interrupt mask and to
output serial data. Presetting the ACC for the SI M instruction has the following
meaning:

M
5.5

I

SERIAL
OUT
DATA
SERIAL
OUT
DATA
ENABLE
(1 = ENABLE)

404

I
RESET
RST7.5
ENABLE
MASK
SET
ENABLE
(1 = ENABLE)

RST
MASKS
(1 = SET)

SERIAL I/O

,.,.p D8085A
INSTRUCTION SET

The instruction set includes arithmetic and logical operators with direct, register,
indirect, and immediate addressing modes.
Move, load, and store instruction groups provide the ability to move either 8 or 16 bits
of data between memory, the six working registers and the accumulator using direct,
register, indirect, and immediate addressing modes.
The ability to branch to different portions of the program is provided with direct, con·
ditional, or computed jumps. Also, the ability to call and return from subroutines is
provided both conditionally and unconditionally. The RESTART (or single byte call
instruction) is useful for interrupt vector operation.
Conditional jumps, calls and returns execute based on the state of the four testable
flags (Sign, Zero, Parity and Carry). The state of each flag is determined by the result
of the last instruction executed that affected flags. (See Instruction Set Table.)
The Sign flag is set (High) if bit 7 of the result is a "1 "; otherwise it is reset (Low). The
Zero flag is set if the result is "0"; otherwise it is reset. The Parity flag is set if the
modulo 2 sum of the bits of the result is "0" (Even Parity); otherwise (Odd Parity) it
is reset. The Carry flag is set if the last instruction resulted in a carry or a borrow out
of the most significant bit (bit 7) of the result; otherwise it is reset.
In addition to the four testable flags, the f.lPD8085A has another flag (ACY) that is
not directly testable. It is used for multiple precision arithmetic operations with the
DAA instruction. The Auxiliary Carry flag is set if the last instruction resulted in a
carry or a borrow from bit 3 into bit 4; otherwise it is reset.
Double precision operators such as stack manipulation and double add instructions
extend both the arithmetic and interrupt handling capability of the f.lPD8085A. The
ability to increment and decrement memory, the six general registers and the accumulator are provided as well as extended increment and decrement instructions to
operate on the register pairs and stack pointer. Further capability is provided by the
ability to rotate the accumulator left or right through or around the carry bit.
Input and output may be accomplished using memory addresses as I/O ports or the
directly addressed I/O provided for in the f.lPD8085A instruction set.
Two instructions, RIM and SI M, are used for reading and setting the internal interrupt
mask as well as input and output to the serial I/O port.
The special instruction group completes the f.lPD8085A instruction set: NOP, HALT
stop processor execution; DAA provides decimal arithmetic capability; STC sets the
carry flag; CMC complements it; CMA complements the contents of the accumulator;
and XCHG exchanges the contents of two 16·bit register pairs directly.

DATA AND INSTRUCTION
FORMATS

Data in the f.lPD8085A is stored as 8-bit binary integers. All data/instruction transfers
to the system data bus are in the following format:

10710610510410310210,1001
MSB

OAT A WORD

LSB

Instructions are one, two, or three bytes long. Multiple byte instructions must be
stored in successive locations of program memory. The address of the first byte is used
as the address of the instruction.
One Byte Instructions

TYPICAL INSTRUCTIONS

Two Byte Instructions

Register to register, memory
reference, arithmetic or logical
rotate, return, push, pOP. enable,
or disable interrupt instructions

1071 061 051 04 103 102 10, 1DO 1OP CODE
10710610510410310210,1001 OPERAND

Immediate mode or I/O instructions

Three Byte Instructions

I D71 06 I 051 04 103 102 I 0, I DO I OP CODE

~~on::;ncs~~u~rti~i~::t load and

107106105104103 10210, 1DO 1LOW ADDRESS OR OPERAND'
10710610510410310210, 1DO 1HIGH ADDRESSOR OPERAND 2
405

II

p.P D8085A
INSTRUCTION SET
TABLE
INSTRUCTION CODE 2

INSTRUCTION CODE l

MNEMONIC'

DESCRIPTION

07

06

o

1

05

04

D3

1

0

d

d

02

0,

DO

Clock
Cvcles3

MNEMONIC'

DESCRIPTION

MOV d,M
MVI d,DS

Move register 10 register
Move reS"ler to memory
Move memory 10 register
Mov\! ,mmedl

07

MEMORY TO ACCUMULATOR

1

1
1

0

0

0

0

0

1

1
0
1
0

1

POP PSW

Pop regiSter pair Hl. off
stack
Pop A and flags off .tack

o

0

1

10

1

0

0

0

1

10

o

0

0
0

0
0

1
1

o
o

0

1

0

0

o

1

DOUBLE ADD
DAD B
DAD 0
DAD H

AddBCtoHL
Add HL to HL
Add Stock Po'nter

to

O'

0

0

o

0

1
1

HL

0

1
IIliCREMENT REGISTER PAIR
INX 6

00
Increment DE

~

Add ,mmediale 10 A
And Immediate to A w,th
carry
Subtract ,mmed'ale tram A
Subtract ,mmed,ate Irom A

INX H
INX SP

IMMEDIATE TO ACCUMULATOR

1

0

w'th bOrrow
AND ,mmed'ate'w"h A
ExclUSIVe OR Immediate
With A
OR Immed,ale Wit'" A
Compare ,mmed,ate wllh A

0

0

1

o

1
1

1
InCrement Stack POlOter

0001
1
0
1
0
0
1
o 0 1

DECREMENT REGISTER PAIR
DCX
DCX
OCX
OCX

1

1

B

D
H
SP

Decrement BC
Decrement DE

0
0

0
0

0
0

o

0

1

0

1

0

1

0

OecrerT'ent Stack POlOte,

0

REGISTEA INDIRECT

o

1

o

1

0
1

o

STAX B
STAX D
LOA X B
LDAX 0

Store
Store
Load
Load

A
A
A
A

al ADOA ,n Be
at AOOR ,n DE
ill ADOR 10 Be
at AOOA 10 DE

ROTATE

0000010
0010010
0000
010

o

0

0

1

1

0

0

0

DIRECT
ROlale A lelt, MSB 10
carry 18-bitl
Aotate A "ght, LSB to
carry 18.blll
R()tateA left through
carry 19.b'tl
Ratate A right through
carry Ig·bll)

o

0

0

1

STA ADO A
LOA AOOA
SHLD AD OR

o

o
Store HL direct
Load HL direct

1
1

00

1

0

1
0001
o 1

13
16

16

MOVE REGISTER PAIR
XCHG

E~change

PCHL

ExChal)ge top of stac~
and HL
HL to Stack Pointer
HL to Program Counter

DE and HL

JUMP
JMP AOOA
JNZ AOOR
JZ AOOR
JC AOOA
JPO ADOR
JPE AODR
JP AOOA
JM ADDA

Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump

unconditional
On nOI zero
on zero
on no carry
on carry
on panty odd
on parity even
on pOs.t,ve
on minus

1
1

0
0

o
1

o
o

0

0

7/10

0
1
1
0

1
0

7/10
7/10
7/10
7/10
7/10
7110

o

0

1

0
0

1
1

0

1

1

0

1
1

1
0

1
1

0
0

1
1

0

o

0
0

7/10

Calt uncondil.onal
Call on not ~ero

1
Call on
Cal! on
Calion
Calion
Cal! on

no carry
carry
parity odd
panty even
pos1llve

o
o

0
0

0

0

o

,
o

1

1
0

0

o

0

1

1

0

0
0

o .

16

1
1

6

INPUT/OUTPUT

'N A
OUT A

"D'
R'M
S'M

CALL
CALL ADDR
CNZ ADOR
CZ ADOA
CNC ADOR
CC AOOR
CPO AOOA
CPE AODR
CP ADDA
CM AD OR

tOO

18

o

Input

o

Qutp.."
Enable >nterrupu
Disable InterruptS
Read InterrUP1Mask
Set Interrupt Ma~k
RMtart

1
1
1

10

10

o
o

o

1

0

0

1

A

A

9/18
9/18

MISCELLANEOUS

9/18
9/18

o

0
0

0

0

o

0

9/18
9/18

9/18

9/18

eMA
STe
eMC

Complement A
Set carry
Complllment carry
DeCimal adju~t A
No operat,on

o

0

o

0

o

0

Halt

o

1

1

0

1

I

0

0

0
0

RETURN

RET
RNZ
RZ

RNe
RC
RPO

RPE
RP

406

1
Return on
Return on
Aeturn on
RlItlJrn On
RelUrn On
Return on
Return on
RetlJrnon

notlero

0

o

0

0
0

lefO

no carry
carry
parlly odd
parfly !!\Oen
pos,tlve
m,nu;

0

0

0

1
0

o

0

0

010000

o
1

0
0

0
0

o

1
0
1

0

0

I

0
1

0
0

0
0

6112

6/12
6/12
6112

6112
0

6/12
6112
6/12

1

C,
1
0

IOperand Symbots used
A ' B·b" address Or e~preSSIO"
S - SOUr!;e rejjiSler
d ~ destlnat,on reg.ster
PSW ~ Processor Status Word
SP ~ Stack POlOter
08 ~ 8·b,t data quan1l1y, e~preSSlon> Or
constant, always 82 of lOst ruction
016 ~ 16·blt data quantity, e~press,on, Or
constant, alway~ 8382 of IOs\ructlOn
AOOR ~ 16·blt Memory address e~Press'on

2dddor sss ~ 0006 ~ 001 C -0100 - 011 E ~ 1001-1 ~
lOlL - 110 Memory __ 111 A
3Two pou,ble cycle times 17/10) mdl!;ate
mstruct,on cycleS dependent on cond,t,on
flags
4 • • flag affected
flag "01 affected
. flag reset
ollag;et

p.PD8085A

INSTRUCTION CYCLE
TIMES

One to five machine cycles (Ml - M5) are required to execute an instruction. Each
machine cycle involves the transfer of an instruction or data byte into the processor or
a transfer of a data byte out of the processor (the sole exception being the double add
instruction). The first one, two or three machine cycles obtain the instruction from the
memory or an interrupting I/O controller. The remaining cycles are used to execute the
instruction. Each machine cycle requires from three to five clock times (Tl - T5).
Machine cycles and clock states used for each type of instruction are shown below.
INSTRUCTION
TYPE

MACHINE CYCLES EXECUTED
MIN/MAX

ALU R
CMC
CMA
DAA
DCR R
DI
EI
INR R
MOV R, R
NOP
ROTATE
RIM
SIM
STC
XCHG
HLT
DCX
INX
PCHL
RETCOND.
SPHL
ALU I
ALU M
JNC
LDAX
MVI
MOV M, R
MOV R, M
STAX
CALL CONDo
DAD
DCR M
IN
INR M
JMP
LOAD PAIR
MVIM
OUT
POP
RET
PUSH
RST
LDA
STA
LHLD
SHLD
XTHL
CALL

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/3
1
2
2
2/3
2
2
2
2
2
2/5
3
3
3
3
3
3
3
3
3
3
3
3

4
4
5
5
5
5

CLOCK STATUS
MIN/MAX

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
6
6
6
6/12
6
7
7
7/10
7
7
7
7
7
9/18
10
10
10
10
10
10
10
10
10
10
12
12
13
13
16
16
16
18

II

407

p.PD8085A
~PD8085A FAMILY MINIMUM
SYSTEM CONFIGURATION

A minimum computer system consisting of a processor, ROM, RAM, and
I/O can be built with only 3-40pih packs. This system is shown below with
its address, data, control busses and I/O ports.

VCC
INTERRUPTS

,~

I

I

RST 7.5 RST 6.5 RST 5.5 TRAP

rl

~ t

X2
ADo - - - - --AD7 AS - - - - -- A,S

11

ADO

..l

AD,

w

...
0
...

1:;>

~ l:i I~ 2:i

'"

...
u

PORTS

I

'1111'

PAo - - - - -- PA7

:>

.POS085A PROCESSOR

~

t t 'II

SIO SOO S' SO

RESET IN

X,

B

PORTC

PORT A

'Ill 11 l'

1

1111 '1111'

pco-----pc5 PSo - - - - - PS7

.PDS'56 RAM-IIO 1256 x 8)

< 1<
~w ...0 ...0 «......
« :r :r ~ !
C

w

ADO - - - - - AD7

TIMER
- IN

-

l:tcn

~ ~I:il~~~

11

TIMER
OUT

-

AD2
AD3
DATA

AD4
ADS
AD6

-

AD7

As
Ag
A,O
A11

r- ADR

A12
A'3
A'4
A,S
ALE

RD
ViR
101Pi!
ROY

"- CON

ClK
RESET
HOLD

HlDA
INTR

iNTi.

~~:~~::l ~1~1~1:i
«u0:2

ALE ADO - - - - - AD7

FEATURES OF .PDS085A
~PD8355

MINIMUM SYSTEM

2K
256
,
4
'
4

-

BYTE ROM
SYTE RAM
INT,ERVAl TIMER
S-SIT 110 PORTS
6-BIT IIO-STATUS
INTERRUPT lEVELS

PAO - -

II

- - - - - - PA7

II I ,
I
PORTA

408

ROM-I/O

/JPD8755A PROM·1I0 2K X 8
PBo - -

-

-

-

- -- PB7

,11111111,
,
PORTS

p.PD8085A

PACKAGE OUTLINE
J,lPD8085AC

Plastic
ITEM

MILLIMETERS

A

51.5 MAX

B
C
0
E
F

INCHES
2.028 MAX

1.62

0.064

2.54.' 0.1

0.10 ± 0.004

0.5 ± 0.1

0.019 ± 0.004

48.26

1.9

1.2 MIN

0.047 MIN

G

2.54 MIN

0.10MIN

H

0.5 MIN

0.019 MIN

[

5.22 MAX

0.206 MAX

J

5.72 MAX

0.225 MAX

K

15.24

0.600

L

13.2

0.520

0.25

M

+ 0.1

0.05

0.010

+ 0.004

0.002

J,lPD8085AD

G

l~:J~
0·10°

~------------E------------~

II

Ceramic

ITEM

MILLIMETERS

INCHES

A

51.5 MAX.
1.62 MAX.
2.54 ± 0.1
0.5 ± 0.1
4S.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14MAX.
O.lS MAX.
0.6 TYP.
0.59 TYP.
0.01 ± 0.0019

B

C
D

E
F
G

H
I
J

K
L
M

SOS5ADS-R EV2·1 O-SO·CAT

409

NOTES

410

NEe

NEe Microcomputers, Inc.

JLPD8086
JLPD8086-2'"

16 BIT MICROPROCESSOR
D ESC R I PT ION

F EA TU R ES

The /lPD8086 is a 16-bit microprocessor that has both 8-bit and 16-bit attributes_ It
has a 16-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz /lPD8085A-2.

• Can Directly Address 1 Megabyte of Memory
•
•
•
•
•
•
•

PIN CONFIGURATION

Fourteen 16-Bit Registers with Symmetrical Operations
Bit, Byte, Word, and Block Operations
8 and 16-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal
Multiply and Divide Instructions
24 Operand Addressing Modes
Assembly Language Compatible with the /lPD8080/8085
Complet.e Family of Components for Design Flexibility

GND
AD14
AD13
AD12
ADll
AD10
AD9
ADB
AD7
ADS
AD5
AD4
AD3
AD2
ADl
ADO
NMI
INTR
elK
GND

Vee
AD15
A1S/S3
A17/S4
A1B/S5
A19/SS
SHE/S7
MN/MX
RD
HOLD

(Fffi/GTIi)

HlDA

(ROIGT1)

iNA

(C5CT<)

M/iQ
DTIR

(S1)

(82)

DEN

(Sci)

ALE
INTA
TEST
READY
RESET

(OSO)
(OSl)

II

*Preliminary

411

HPD8086
NO.

FUNCTION

NAME

SYMBOL
ADO-AD15

Address/Data Bus

Multiplexed address IT1) and data (T2. T3. TW. T 4) bus.
8-bit peripherals tied to the lower 8 bits, use AO to condition
chip select functions. These lines are tri-state during interrupt
acknowledge and hold states.

17

NMI

Non-Maskable
Interrupt

This is an edge triggered input causing a type Z interrupt. A
look-up table is used by the processor for vectoring
information.

18

INTR

Interrupt Request

A level triggered input sampled on the last clock cycle of
each instruction. Vectoring is via an interrupt look-up table.
I NTR can mask in software by resetting the interrupt enable
bit.

19

ClK

Clock

The clock input is a 1/3 dutY cycle input basic timing for the
processor and bus controller.

21

RESET

Reset

This active high signal must be high for 4 clock cycles. When
it returns low, the processor restarts execution.

22

READY

Ready

An acknowledgement from memory or I/O that data will be
transferred. Synchroni2ation is done by the p.PD8284 clock
generator.

23

TEST

Test

This input is examined by the "WAIT" instruction. and if
low, execution continues. Otherwise the processor waits in an
"Idle" state. Synchronized by the processor on the leading
edge of ClK.

24

iN'i'A

Interrupt
Acknowledge

This is a read strobe for reading vectoring information.
During T2, T3, and TW of each interrupt acknowledge
cycle it is low.

25

ALE

Address Latch Enable

This is used in conjunction with the $£PD8282/8283 latches
to latch the address, during T 1 of any bus cycle.

26

DEN

Data Enable

This is the output enable for the $£PD8282/8287 transceivers.
It is active low during each memory and I/O access and
INTA cycles.

27

DTtA

Data Transmit/Receive

2·16.39

Used to control the direction of data flow through the
".n~.;v."

28

MilO

Memory/IO Status

This is used to separate memory access from I/O access.

29

WR

Write

Depending on the state of the MIlO line, the processor is
either writing to 1/0 or memory.

30

HlDA

Hold Acknowledge

A response to the HOLD input, causing the processor to
tri-state the local bus. The bus return active one cycle after
HO LD goes back low.

31

HOLD

Hold

When another device requests the local bus. driving HOLD
high, will cause the $£P08086 to issue a H LOA.

32

Ro

Read

Depending on the state of the MIlO line. the processor is
reading from either memory or I/O.

33

MN/MX

Minimum/Maximum

This input is to tell the processor which mode.it is to be used
iri. This effects some of the pin descriptions.

34

BRE/S7

Bus/High Enable

This is used in conjunction with the most significant half of
the data bus. Peripheral devices on th is half of the bus use
BHE to condition chip select functions.

35-38

A16-A19

Most Significant
Address Bits

The four most significant address bits for memory operations. Low during I/O operations.

50-57

Status Outputs

These are the status outputs from the processor. They are
used by the p.PD8288 to generate bus control signals.

oS1.QSO

Que Status

Used to track the Internal p.PD8086 instruction que.

lOCK

lock

This output is set by the "lOCK" instruction to prevent
other system bus masters from gaining control.

RQ/GTO
ROIGT 1

Req.uest/Grant

Other local bus masters can force the processor to rebase
the local bus at the end of the current bus cycle.

26.27.2S
34-38
24.25

29
30.31

412

PIN IDENTIFICATION

jLPD8086
BLOCK DIAGRAM

UECUTION UNIT
"EGISTI" FILE
DATA.
POINTE". AND
INDEX "EGS
II WORDSI

IUS INTE"FACE UNIT
RELOCATION
r
MOIaTE" FILE
HOIIENT
"IOISTI"S
AND
INST"UCTION
I'OtNTI"
(I WO"DSI

I

1H!Is,

A,tIIt

,."T ALU

A1~
FLAOS

IUS

INTERFACE
UNIT

ADtS-ADo

DTIA,ISIN.ALE

.IYTE
INSTAUCTION
QUEUE

Hft---r------~~------~
INT_

NIIt

CONTIlOL • TIlliNG

AQroTO.,
HOLD

II

HLDA----~~____r-__~----~--~~

CUt

IlIMT "lADy....,... aND

Vee

413

J'PD8086

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
-1.0 to +7V
Voltage on Any Pin with Respect to Ground. . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under "Absolute Maxim~m Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation 01 the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

PARAMETER

SYMBOL

MAX

UNITS

+O.S

V

VCC+0.5

V

0.45

V

IOl = 2.0 mA

V

IOH=- 4OO I1A

Input low Voltage

Vil

-0.5
2.0

Input High Voltage

VIH

Output low Voltage

VOL

Output High Voltage

VOH

Power Supply Current

ICC

2.4

I1PDSOS6/
I1PDSOS6·2
Input leakage Current

III

Output leakage Current

ILO

340
350

mA
mA

Ta = 25°C

±10

I1A

OV < VIN

0.45V';; VOUT';; VCC

< VCC

±10

I1A

+0.6

V

VCC+l.0

V

CIN

15

pF

fe = 1 MHz

CIO

15

pF

Ie = 1 MHz

Clock Input low Voltage

VCl

Clock Input High Voltage

VCH.

Capacitance of Input Buffer
(All input except
ADO-AD15. RQ/GT)
Capacitance of lID Buffer
(ADO-AD15. RQ/GT)

414

TEST
CONDITIONS

MIN

-0.5
3.9

DC CHARACTERISTICS

~PD8086

AC CHARACTERISTICS
TIMING REQUIREMENTS

J.lPDB086-2 (Preliminary I

}.JPD8086

MINIMUM COMPLEXITY
SYSTEM

PARAMETER

SYMBOL

MIN

MAX
500

MIN

MAX

125

500

UNITS

TEST
CONDITIONS

elK Cycle Period -IlPDB086

TCLCL

200

elK low Time

TeLCH

(2/3 TCLCLl-15

eLK High Time

TCHCL

(1/3 TClCLi +2

eLK Rise Time

TCH1CH2

10

10

From 1.0V to 3,SV

elK Fall Time

TCL2Cll

10

10

From 3.SV to 1.0V

Data In Setup Time

reVel

Data In Hold Time

TelDX

10

10

ROY Setup Time into /lPD8284

TR1VCL

15

35

(2/3 TCLCL)-15

(2/3 reLell -15

(1/3 reLeLl +2

20

30

Q)@
ROY Hold Time into /.IP08284

TeLA1 x

,Q)@
READY Setup Time ,nto j.lPD8086

TRYHCH

(2/3 TCLCLl-15

READY Hold Time into J.!PD8086

TCHAYX

30

20

READY Inactive to elK

TRYLCL

-8

-8

HOLD Setup Time

THVCH

35

20

INTR, NMl, TEST Setup Time

TINVCH

30

15

@

@

TIMING RESPONSES

TIMING RESPONSES

>,PD8OB6-2 (Preliminary I

IlPDS086
PARAMETER

SYMBOL

MIN

MAX
110

Address Valid Delay

TCLAV

10

Address Hold Time

TCLAX

10

Addre~

TCLAZ

TCLAX

ALE Width

Float Delay

TLHLL

TCLCH-20

ALE Active Delay

TCLLH

ALE Inactive Delay

TCHLL

Address Hold Time to ALE Inactive

TLLAX

TCHCL-l0

Data Valid Delay

TCLDV

10

Data Hold Time

TCHDX

10

MIN

MAX

10

60

10
80

TCLAX

50

55
TCHCL-l0

110

10

60

10

Data Hold Time After WR

TWHDX

TCLCH-30

TCVCTV

10

110

10

70

Control Active Delay 2

TCHCTV

10

110

10

60

Control Active Delay

TCVCTX

10

110

10

70

Address Float to READ Active

TAZRL

RDActive Oelay

TCLRL

10

165

10

100

AD Inactive Delay

TCLAH

10

150

10

80

RD Inactive to Next Address Active

TAHAV

TCLCL-45

TCLCH-30

HLOA Valid Delay

TCLHAV
TRLRH

2TCLCL-75

)TCLCl-50

WRWldth

TWLWH

2TCLCL-60

2TCLCL-40

TAVAL

TCLCH-60

TCLCH-40

CD
@
@

CL = 20-100 pF tor
all ,uPD8086 Outputs
(In addition to
",PD9086 self-load)

TCLCL-4Q

FlDWldth

Address Valid to ALE La.....

"'

50

85

Control Active Delay 1

NOTES:

CONDITIONS

TCLCH-1O

80

10

TEST
UNITS

160

10

100

Signal at ",PD8284 sho..... n for reference only
Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
Applies only to T2 stata. (8 ns into T3)

415

II

.uP 08086
TIMING WAVEFORMS
Minimum Complexity
Systems

®

elK (8284 Output)

MliD

ALE

RDY (8284 Inputl

0®

READ CYCLE

CD

(WR,

'iN'fA",

VOH)

DT/R

416

I

r--

}LPD8086
TIMING WAVEFORMS
Minimum Complexi~
Systems (Con't.) @
CLK(82840UTPUTI

M/iLI

ALE

WRITE CYCLE \

AD15 : : :

G:l

(RiS iNTA,
DT/R = VOH)

We

~--~----~t--T-·

AD1S·ADS

OT/R

INTA CYCLE

G:l@

(R5,WR

= VOH
SHE = VOL)

SOFTWARE HALT

iSEN.Ri5,WA,INTA

=

INVALID ADDRESS

V OH

SOFTWARE HALT

II

TeLAV

NOTES:

------------<1 :
>-------------< >-_ _ _ _

..J

8HE1S7

NOTE:

CD

COPROCESSOR

(j)

The coprocessor may not drive the buses outside the region shown without
rjsking contention.

*for Maximum Mode only

421

JoCPD8086
HOLD/HOLD
TIMING*
ACKNOWLEDGE

'" ~~ rI""""'~

~,,~~~'1-,~

~::;~~-:
DT/A.
BHE!S,.M/ffi
WR. DEN

I

OJ,,, Minimom Mod. onlv

J~ : C: -LH-A-v- <",

-,,:=:x'
.

___ l (TrAV

/

C~CESSOA
';}-E
~.
BOBS

II:
G

K ---"1
_ L;:;;;]I

PACKAGE 0 UTLINE
JlPD8086D

-F.J~
0_100

Cerdip
MILLIMETERS

51.5 MAX
.62
2.54 ± 0.,'
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN
3.2 MIN'
1.0 MIN:
3.5 MAX

1 MAX~-:--t--;;:~~~-

15.24 TY~
14.93 TYP'
0.25 ± 0.05

80860S-1 0-80-CA T

422

NEe
NEe Microcomputers, Inc.

/LPD765

SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
DESCRIPTION

The J,tPD765 is an LSI Floppy Disk Controller (FDC) Chip, which contains the circuitry and control
functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either
IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including
double sided recording. The J,tPD765 provides control signals which simplify the design of an
external phase locked loop, and write precompensation circuitry. The FDC simplifies and handles
most of the burdens associated with implementing a Floppy Disk Interface.
Hand-shaking signals are provided in the J,tPD765 which make DMA operation easy to incorporate
with the aid of an external DMA Controller chip, such as the J,tPD8257. The FDC will operate in
either DMA or Non·DMA mode. In the Non·DMA mode, the FDC generates interrupts to the
processor every time a data byte is available. In the DMA mode, the processor need only load the
command into the FDC and all data transfers occur under control of theJ,tPD765 and DMA
controller.
There are 15 separate commands which the J,tPD765 will execute. Each of these commands requ ire
multiple 8·bit bytes to fully specify the operation which the processor wishes the FDC to perform.
The following commands are available:
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal

FEATURES

Scan High or Equal
Scan Low or Equal
Specify
Write Data
Format a Track

Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense Int"rrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the F DC which simplifies the phase locked loop ana
read electronics. The track stepping rate, head load time, and head unload time may be programmed
by the user. The J,tPD765 offers many additional features such as multiple .ector transfers in both
read and write with a single command, and full IBM compatibility in both single and double
density modes.
IBM Compatible in Both Single and Double Density Recording Formats
Programmable Data Record Lengths: 128,256,512, or 1024 Bytes/Sector
Multi·Sector and Multi-Track Transfer Capability
Drive Up to 4 Floppy Disks
Data Scan Capability - Will Scan a Single Sector or an Entire Cylinder's Worth of Data Fields,
Comparing on a Byte by Byte Basis, Data in the Processor's Memory with Data Read from the
Diskette
• Data Transfers in DMA or Non-DMA Mode
o Parallel Seek Operations on Up to Four Drives
o Compatible with Most Microprocessors Including 8080A, 8085A, J,tPD780 (Z80TM)
o Single Phase 8 MHz Clock
o Single +5 Volt Power Supply
o Available in 40 Pin Plastic Dual-in-Line Package
RESET
1
40 vcc
o
o
o
o
o

PIN CONFIGURATION

RD

2

FiW/SEEK

4
5

FR/STP

LCT/DIR

WR

Cs

HDL

AO
DBO

6

ROY

OB,

7

WP/TS

DB2

8
9
10

DB3
DB4
DB5
DB6
DB7

FLT/TR(

/oIPD
765

'PSo

11
12
13
14
15
16
17
18

RO

19

ROW

VCO

= ______-'WCK
TM:Z80 is. registered tredemark of Zilog, Inc,

Rev/2

423

JI. PD765
BLOCK D.lAGRAM

ORO

0AcK
INT

RO

WR

READY
WRITE PROTECT/TWO SIDE

AO

INDEX
FAULT/TRACK 0

RESET

UNIT SeLECT 0
UNIT SELECT 1
MFM MODE

eLK

RWISEEK

Vee

HEAD LOAD

eND

LOW CURRENT/DIRECTION
FAULT AeSETiSTEP

HEAD SELECT

. ~ lOoe to +70oe
-40°C to +125°e
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts
. . • . . . . .. 1 Watt

Operating Temperature.
Storage Temperature
All Output Voltages.
All Input Voltages ..
Supply Voltage Vee
Power Dissipation ..

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

*Ta = 25°e
Ta

= _10°C to +70°C; Vee = +5V
PARAMETER

LIMITS

SYMBOL
VIL

MIN
-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

VOL

Output High Voltage

VOH

Input Low Voltage
(CLK + WR Clock)

VIL(CY

Clock Active (High)

<1>0

Clock Rise Time

r

20

ns

Clock Fall Time

f

20

ns

AO. CS. DACK Set Up Time to R 0 I

TAR

0

ns

AO. CS. DACK Hold Time from RD t

TRA

0

ns

RDWidth

TRR

250

Data Access Time from R 0 ,/.

TRD

DB to Float Delay Time from RD t

TDF

AO. CS. DACK Set UP Time to WR I

TAW

0

ns

AO. CS. DACK Hold Time to WR t

TWA

0

ns

WRWidth

TWW

250

ns

Data Set Up Time to WR t

TOW

150

ns

Data Hold Time from WR t

TWO

5

INT Delay Time from RD t

TRI

500

INT Delay Time from WR t

TWI

500

ORO Cycle Time

TMCY

ns

40

ns

20

200

ns

CL = 100 pf

100

ns

CL - 100 pF

ns

13

ns
ns
I'S

200

ns

ORO Delay Time from DACK I

TAM

TC Width

TTC

Reset Width

TRST

WCK Cycle Time

TCY

WCK Active Time (High)

TO

350

ns

WCK Rise Time

Tr

20

ns

WCK Fall Time

Tf

20

ns

Pre-Shift Delay Time from WCK t

TCp

20

100

ns

WDA Delay Time from WCK t

TCD

20

100

ns

ROD Active Time (High)

TROD

40

Window Cycle Time

1

0.
(1 to 16 rns in 1 ms increments.) Stepping Rate

ST a
ST 1
ST 2
ST3

Status

Cylinder.

applies to all drives, (F

a

=:

1 ms, E = 2 ms, etc.1.

ST 0·3 stand for one of four registers which
store the status information after a command
has been executed. This information is
available during the result phase after command
execution. These registers should not be confused with the main status register (selected by

Status 1

Status 2
Status 3

AO = 0). ST 0-3 may be read only after a com·
mand has been executed and contain informatio
relevant to that particular command.
During a Scan operation, if STP = 1, the data in
contiguous sectors is compared byte by byte
with data sent from the processor (or DMA);
and if STP = 2, then alternate sectors are read
and compared.

STP

usa, USl

Unit Select

US stands for a selected drive number

MEMORIES

J

a or 1.

SYSTEM CONFIGURATION

I
I

8080 SYSTEM BUS
~

DB0-7

AO

'M'EMR

DB0-7

iO"R

AD

MEMW

ViR
CS

iOW
CS

,

INT

HRa

,

HLDA

RESET

OMA
CONTROLLER

DAc'K

WR DATA
~PD765

FOG
TC
TERMINAL
COUNT

432

)

RD DATA

ORa

~POB257

READ

DATAG-rWINDOW
PLL

INPUT CONTROL

OUTPUT CONTROL

DRIVE
INTERFACE

(

~

p,PD765
PROCESSOR I NTE R FACE

During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. After each byte of data read or written to Data Register, CPU should
wait for 12 J.i.s b~fore reading MSR. Bits D6 and D7 in the Main Status Register must
be in a a and 1 state, respectively, before each byte of the command word may be
written into the J.i.PD765. Many of the commands require mUltiple bytes, and as a
result the Main Status Register must be read prior to each byte transfer to the J.i.PD765.
On the other hand, during the Result Phase, D6 and D7 in the Main Status Register
must both be 1's (D6 = 1 and D7 = 1) before reading each byte from the Data Register.
Note, this reading of the Main Status Register before each byte transfer to the pPD765
is required in only the Command and Result Phases, and NOT during the Execution
Phase.
During the Execution Phase, the Main Status Register need not be read. If the J.i.PD765
is in the NON-DMA Mode, then the receipt of each data byte (if J.i.PD765 is reading
data from FDD) is indicated by an Interrupt signal on pin 18 (INT = 1). The generation
of a Read signal (RD = 0) or Write signal (WR = 0) will reset the Interrupt as well as
output the Data onto the Data Bus. If the processor cannot handle Interrupts fast
enough (every 13 J.i.s) for MFM and 27 J.i.s for FM mode, then it may poll the Main
Status Register and then bit D7 (ROM) functions just like the Interrupt signal. If a
Write Command is in process then the WR signal performs the reset to the Interrupt
signal.
If the pPD765 is in the DMA Mode, no I nterrupts are generated during the Execution
Phase. The J.i.PD765 generates DRO's (DMA Requests) when each byte of data is available. The DMA Controller responds to this request with both a DACK = a (DMA
Acknowledge) and a FlD = a (Read signal). When the DMA Acknowledge signal goes
low (DACK = 0) then the DMA Request is reset (DRO = 0). If a Write Command has
been programmed then a WR signal will appear instead of RD. After the Execution
Phase has been completed (Terminal Count has occurred) or EaT sector was read/
written, then an Interrupt will occur (INT = 1). This signifies the beginning of the
Result Phase. When the first byte of data is read during the Result Phase, the Interrupt
is automatically reset (I NT = 0).
It is important to note that during the Result Phase all bytes shown in the Command
Table must be read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes must be read in order to successfully complete the
Read Data Command. The J.i.PD765 will not accept a new command until all seven
bytes have been read. Other commands may require fewer bytes to be read during the
Result Phase.
The J.i.PD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STO, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only after
completing a command. The particular command which has been executed determines
how many of the Status Registers will be read.
The bytes of data which are sent to the J.i.PD765 to form the Command Phase, and are
read out of the J.i.PD765 in the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent first and the other bytes
sent in the prescribed sequence. No foreshortening of the Command or Result Phases
are allowed. After the last byte of data in the Command Phase is sent to the pPD765,
the Execution Phase automatically starts. In a similar fashion, when the last byte of
data is read out in the Result Phase, the command is automatically ended and the
J.i.PD765 is ready for a new command.

POLLING FEATURE OF
THE pPD765

After the Specify command has been sent to the J.i.PD765, the Unit Select line usa and
US1 will automatically go into a polling mode. In between commands (and between
step pulses in the SEEK command) the J.i.PD765 polls all four FDD's looking for a
change in the Ready line from any of the drives. If the Ready line changes state (usually
due to a door opening or closing) then the J.i.PD765 will generate an interrupt. When
Status Register a (STO) is read (after Sense I nterrupt Status is issued), Not Ready (N R)
will be indicated. The polling of the Ready line by the J.i.PD765 occurs continuously
between commands, thus notifying the processor which drives are on or off line. Each
drive is polled every 1.024 ms except during the ReadlWrite commands.

433

II
•

p.PD765
READ DATA
A set of nine (9) byte words are required to place the FOC into the Read Data Mode. After the Read Data
command has been issued the FDC loads the head (if it is in the unloaded state), waits the specified head
settling time (defined in the Specify Command), and begins reading 10 Address Marks and 10 fields. When
the current sector number ("R") stored in the 10 Register (lOR) compares with the sector number read. off
the diskette, then the FOC outputs data (from the data field) byte·to-byte to the main system via the data
bus.
After completion of the read operation from the current sector, the Sector Number is incremented by one,
and the data from the next sector is read and output on the data bus. This continuous read function is called
a "Multi-8ector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. TC should be issued at the same time that the OACK for the last byte of data is sent. Upon
receipt of this signal, the FOe stops outputting data to the processor. but will continue to read data from the
current sector, check CRe (Cyclic Redundancy Count) bytes, and t!len at the end of the sector terminate
the Read Data Command.

The amount of data which can be handled with a single command to the FOC depends upon MT (multi·
track), MF (MFM/FM), and N (Number of Bytes/Sector), Table 1 below shows the Transfer Capacity.
Multi-Track
MT

MFM/FM
MF

Bytes/Sector
N

0
0
1
1
0
0

0
1

00
01

0
1
0
1

1
1
0
0
1
1

0
1
0
1
0
1

00
01
01
02
01
02
02
03
02
03

Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)
(12B)
(256)
(128)
(256)
(256)
(512)
(256)
(512)
(512)
(1024)
(512)
(1024)

(26) = 3,328
(26) = 6,656
(52) = 6,656
(52) = 13,312
(15) = 3,840
(15) = 7,680
(30) - 7,680
(30) = 15,360
(8) = 4,096
(8) = 8,192
(16) = 8,192
(16) = 16,384

Final Sector Read
from Diskette
26at Side 0
or 26 at Side 1
26 at Side 1
15at Side 0
or 15 at Side 1
15 at Side 1
8at Side 0
or 8 at Side 1
8at Side 1

Table 1, Transfer Capacity
The "multi·track" function (MT) allows the FDC to read data from both sides of the diskette, For a
particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing at Sector L, Side 1
(Sector L = last sector on the side). Note, this function pertains to only one cylinder (the same track) on
each side of the diskette,
When N = 0, then OTL defines the data length which the FDC must treat as a sector, If OTL is smaller than
the actual data length in a Sector, the data beyond OTL in the Sector, is not sent to the Data Bus. The FOC
reads (internally) the complete Sector performing the CRC check, and depending upon the manner of com·
mand termination, may perform a Multi-Se~or, Read Operation. When N is non-zero, then DTL has no
meaning and should be set to FF Hexidecimat.,
At the completion of the Read Data Command, the head is not unloaded until after Head Unload Time
Interval (specified in the Specify Comrnand) has elapsed. ·If the processor issues another command before
the head unloads then the head settling time may be saved between subsequent reads. This time out is
particularly valuable when a diskette is copied from one drive to another.
If the FDC detects the Index Hole twice without finding the right sector, (indicated in "R"), then the FOC
sets the NO (No Data) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
(Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
After reading the 10 and Data Fields in each sector, the FOC checks the CRC bytes. If a read error is
detected (incorrec"t CRC in iD field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high),
and if a CRC error occurs in the Data Field the FOC also sets the DO (Data Error in Data Field) flag in
Status Register 2 to a 1 (high) .. and terminates the Read Data Command. (Status Register 0 also has bits 7
and II set to 0 and 1 respectively.)
If the FDC reads a Deleted Data Addres. Mark off the diskette, and the SK bit (bit 05 in the first Command
Wordl is not set (SK = 0), then the FOC .ets the CM (Control Markl flag in Statu. Register 2 to a 1 (high),
and terminates the Read Data Command, after reading all the data in the Sector. If SK '" 1, the FOC skips
the sector with the Deleted Data Address Mark and reads the next sector. The CRC bits, in the deleted dEfita
field are not checked when SK '" 1.
During disk data transfers between the FOC and the processor, via the data bus, the FOC must be serviced
by the processor every 27 1" in the FM Mode, and every 131's in the MFM Mode, or the FOC sets the OR
(Over Run) flag in Status Ragister 1 to a 1 (high), and terminates the Read Data Commend.
If the processor terminates a read (or write) Op8ration in the 'FOC, then the 10 Information in the Result
Phase i. dependent upon the state of the MT bit and EOT byte. Table 2 shows the value. for C, H, R, and
N, when the processor terminates the Command.
'

434

FUNCTIONAL
DESCRIPTION OF
COMMANDS

}LPD765
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

10 Information at Result Ph_

MT

a

1

HD

Final Sector Transferred to Processor

a
a
1
1

C

H

R

N

Less than EDT

NC

NC

R+1

NC

Equal to EDT

C+1

NC

Less than EDT

NC

NC

Equal to EDT

C+1

NC

a
a

Less than EDT

NC

Equal to EDT

1
1

Notes:

= 01

NC

R+1

NC

= 01

NC

NC

R+1

NC

NC

LSB

R

= 01

NC

Less than EDT

NC

NC

R+1

NC

Equal to EDT

C+1

LSB

R

= 01

NC

R

R

NC (No Change): The same value as the one at the beginning of command execution.

2

LSB (Least Significant Bit): The least significant bit of H is complemented.

WRITE DATA
A set of nine (9) bytes are required to set the FOe into the Write Data mode. After the Write Data command
has been issued the FOC loads the head (if it is in the unloaded state), waits the specified Head Settling Time
(defined in the Specify Command), and begins reading 10 Fields. When all four bytes loaded during the com-

mand Ie, H, R. N) match the four bytes of the 10 field from the diskette, the FOC takes data from the
processor byte-by-bvte via the data bus, and outputs it to the FDD.

After writing data into the current sector, the Sector Number stored in "R" is incremented by one, and the
next data field is written int~. The FOC continues this "Multi-Sector Write Operation" until the issuance of
a Terminal Count signal. If a Terminal Count signal is sent to the FOC it continues writing Into the current

sector to complete the data field. If the Terminal Count signal is received while a data field is being written
then the remainder of the data field is filled with 00 (zeros).
The ,FDC reads the 10 field of each sector and checks the CRC bytes. If the FDC detects a read error
(incorrect CRC) in one of the ID Fields. it sets the DE (Data Error) nag of Status Register 1 to a 1 (high).
and terminates the Write Data Command. (Status Register a also has bits 7 and 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manner as the Read Command. The following items are the

same. and one should refer to the Read Data Command for details:
• Transfer Capacity
• EN (End of Cylinder) Flag
• NO (No Data) Flag

•
•

Head Unload Time Interval
10 Information when the processor terminates command (see Table 2)

• Definition of DTL when N = a and when N

*a

In the Write Data mode, data transfers between the processor and FOC, via the Data Bus, must occur every
27 IJ.S in the FM mode, and every 13 IJ.S in the MFM mode. If the time interval between data transfers is
longer than this then the FOe sets the OR (Over Run) flag in Status Register 1 to a 1 (high), and terminates
the Write Data Command. (Status Register 0 also has bit 7 and 6 set to 0 a,nd 1 respectiv~ly.l

WRITE DELETED DATA
This command is the same as the Write Data Command except a Deleted Data Address Mark is written at the
beginning of the Data Field instead of the normal Data Address Mark.

READ DELETED DATA
This command is the same as the Read Data Command except that when the FOC detects a Data Address

Mark at the beginning of a Data Field (and SK

eM flag

= a (low).

it will read all the data in the sector and se' the

in Status Register 2 to a 1 (high), and then terminate the command. If SK
the sector with the Data Address Mark and reads the next sector.

= 1, then the FOC skips

READ A TRACK
ThiS command is similar to READ DATA Command except that this is a continuous READ operation
where the entire data fiel~ from each of the sectors are read. Immediately after encountering the
INDEX HOLE, the FOC starts reading all data fields on the track, as continuous blocks of data. If the
F DC finds an error in the I D or DATA CRe check bytes, it continues to read data from the track. The
FOe compares the 10 information read from each sector with the value stored in the lOR, and sets the
NO flag of Status Register 1 to a 1 (high) if there is no comparison. Multi-track or skip operations are not
allowed with this command.

This command tarminates when number of sectors read is equal to'EDT. If the FDC does not find
an 10 Address Mark on the diskette after it encounters the INDEX HOLE for the second time.
then it sets the MA (missing address mark) flag in Status Register 1 to a 1 (high). and terminates
the command. (Status Register 0 has bits 7 and 6 set to 0 and 1 respectively,)

435

II

I-' PD765

FUNCTIONAL
DESCR IPTION OF
COMMANDS (CONT.)

READID
The READ 10 Command is used to give the present position of the recording head The FDe stores the
values from the first 10 Field it 'is able to read. If no prop'er 10 Address Mark

IS

found on the diskette,

before the INDEX HOLE is encountered for the second time then the MA (MIssing Address Mark) flag in
Status Register 1

IS

set to a 1 (high), and

If

no data

IS

found then the NO (No Data) flag is also set in Status

Register 1 to a 1 (high), The command is then terminated with Bits 7 and 6 in Status Register 0 set to 0
and 1 respectively. During this command there is no data transfer between FOe and the CPU except dUring
the result phase.

FORMAT A TRACK
The Format Command allows an entire track to be formatted. After the INDEX HOLE is detected, Data is
vvritten on the Diskette; Gaps, Address Marks, ID Fields and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density) Format are recorded, The particular format which will be written
is controlled by the values programmed into N (number of bytes/sector), SC (sectors/cylinder), GPL (Gap
Length), and D (Data Pattern) which are supplied by the-processor during the Command Phase. The Data
Field is filled with the Byte of data stored in D,'The 10 Field for each sector is supplied by the processor;
that is, four data requests per sector a.re made by the FOe for C (Cylinder Number), H (Head Number),
R (Sector Numbed and N (Number of Bytes/Sector). This allows the diskette to be formatted with nonsequential sector numbers, if desired.
The processor must send new values for C, H, R, and N to the ,uPD765 for each sector on the track. If FDC
IS set for DMA mode, it will issue 4 DMA requests per sector. If it is set for Interrupt mode, it will issue four
interrupts per sector and the processor must supply C, H, Rand N load for each sector. The contents of
the R register is incremented by one after each sector is formatted, thus, the R register contains a value of
R when it IS read during the Result Phase. This incrementing and formatting continues for the whole track
until the FOC encounters the INDEX HOLE for the second time, whereupon It terminates the command
If a FAULT Signal is received from the FOO at the end of a write operation, then the FOC sets the EC
flag of Status Register a to a 1 (high), and terminates the command after setting bits 7 and 6 of Status
Register a to 0 and 1 respectively. Also the loss of a READY signal at the beginning of a command
execution phase causes bits 7 and 6 of Status Register a to be set to 0 and 1 respectively.
Table 3 shows the relationship between N, SC, and GPL for va'rious sector sizes:

5%" MINI FLOPPY

8" STANDARD FLOPPY
FORMAT

FM Mode

FM Mode

MFM Mode

SECTOR SIZE

N

128 bytes/Sector

00

SC

GPLG)

1A(161

.07(161

1 B(161

I BM Diskette 1

REMARKS

256

01

OE(161

2A(161

I BM Diskette 2

512

02

OF(161
08

1 B(161

3A(161

GPL®

N

SC

GPL

00

12

07

128

00

10

10

19

256

01

08

18

30

1%

09

1024 bytes/Sector

03

04

47

8A

512

02

04

46

87

04

02

C8

FF

1024

03

02

C8

FF

4096

05

01

C8

FF

2048

04

01

C8

FF

256

01

12

OA

OC

256

01

10

20

32

512

02

08

2A

50

256

01

1A(161

OE(161

36(161

512

02

1B(161

54(161

1024

03

OF(161
08

74(161
FF

IBM Diskette 2D

IBM Diskette 2D

2048

04

04

35(161
99

1024

03

04

80

FO

4096

05

02

C8

FF

2048

04

02

C8

FF

8192

06

01

C8

FF

4096

05

01

C8

FF

CD

Suggested values of GPL in Read or Write Commands to avoid splice point between data field
and 10 field of contiguous sections.

<1>

Suggested values of GPL in format command.

® In MFM mode FOC can perform a read operation only with 128 bytes/sector. (N

=

00)

SCAN COMMANDS
The SCAN Commands allow data which is being read from the diskette to be compared against data which
is being supplied from the main system. The FOC compares the data on a byte-by-byte basis, and looks for
a sector of data which meets the conditions of DFDO:= DProcessor. DFDD";; Dprocessor. or OF DO ;;;;.
Dprocessof' The hexidicernial byte of FF either from memory or from FDO can be used as a mask byte
because it always meet the condition of the compare, Ones complement arithmetic is used for comparison
(FF = largest number, 00 = smallest number). After a whole sector of data is compared, if the conditions
are not met, the sector number is incremental (R + STP -+ R), and the scan operation is continued. The scan
operation continues until one of the following conditions Occur; the conditions for scan are met (equal,
low, or high), the last sector on the track is reached (EDT), or the terminal count signal is received.

436

GPL

2048

Table 3
Note:

G:

SECTOR SIZE
128 bytes/Sector

J.LPD765
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)

If the conditions for scan are met then the F DC sets the SH (Scan Hit) flag of Status Register 2 to a 1
(high). and terminates the Scan Command. If the conditions for scan are not met between the starting
sector (as specified by R) and the last sector on the cylinder (EOTI. then the FOC sets the SN (Scan Not
Satisfied) flag of Status Register 2 to a 1 (high), and terminates the Scan Command. The receipt of a
TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the
FOe to complete the comparison of the particular byte which is in process, and then to terminate the command. Table 4 shows the status of bits SH and SN under various conditions of SCAN.

STATUS REGISTER 2
COMMAND

= SN

BIT 2
Scan Equal

COMMENTS

= SH

BIT 3

a

1

DFDD

1

a

DFDD

1

Scan Low or Equal

a
a

Scan High or Equal

a
a

a
a

1

1

=
*"

DProcessor

DFDD

=

DProcessor

DFDD

< DProcessor

DProcessor

OF DO > Dprocessor

1

DFDD = Dp rocessor

a
a

DFDD

DFDD

> DProcessor
< DProcessor

Table 4

If the FDC encounters a Deleted Data Address Mark on one of the sectors (and SK = 01, then it regards the
sector as the last sector on the cylinder, sets CM (Control Mark) flag of Status Register 2 to a 1 (highl and
terminates the command. If SK = 1, the FDC skips the sector with the Deleted Address Mark, and reads
the next sector. In the second case (SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2
to a 1 (high) in order to show that a Deleted Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (MultiTrack) are programmed, it is necessary to remember that the last sector on the track must be read. For
example, if STP = 02, MT = 0, the sectors are numbered sequentially 1 through 26, and we start the Scan
Command at sector 21; the following will happen. Sectors 21, 23. and 25 will be read. then the next sectol
(26) will be skipped and the Index Hole will be encountered before the EOT value of 26 can be read. This
will result in an abnormal termination of the command. If the EOT had been set at 25 or the scanning
started at sector 20, then the Scan Command would be completed in a normal manner.
During the Scan Command data is supplied by either the processor or DMA Controller for comparison
against the data read from the diskette. In order to avoid having the OR (Over Run) flag set in Status
Register 1. it is necessary to have the data available in less than 2711s (FM Mode) or 1311S (MFM Mode). If
an Overrun occurs the FOe ends the command with bits 7 and 6 of Status Register 0 set to 0 and 1,
respectively.

SEEK
The read/write head within the FDO is moved from cylinder to cylinder under control of the Seek Command. FOC has four independent Preient Cylinder Registers for each drive. They are clear only after
Recalibrate command. The FOC compares the PCN (PJ".esent Cylinder Numbed which is the current head
position with the NCN (New Cylinder Number). and if there is a difference performs the following
o~eration:

PCN < NCN: Direction signal to FDD set to a 1 (highl, and Step Pulses are issued. (Step In.1
PCN> NCN: Direction signal to FDD set to a (Iawl. and Step Pulses are issued. (Step Out.1
The rate at which Step Pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECI FY Command. After each Step Pulse is issued NCN is compared against PCN. and when NCN '" PCN, then the SE
(Seek End) flag is set in Status Register 0 to a 1 (high), and the command is terminated. At this point
FOC interrupt goes high. Bits 00B-03B in Main Status Register are set during seek operation and are
clear bv Sense Interrupt Status command.
During the Command Phase of the Seek operation the FOC is in the FOe BUSY state, but during the
Execution Phase it is in the NON BUSY state. While' the FOC is in the NON BUSY state, a~other Seek
Command may be issued. and in this manner parallel seek operations may be done on up to 4 Drives at
once. No other command could be issue for as long as FOC is in process of sending Step Pulses to any
drive.
If an FDD is in a NOT READY state at the beginning of the command execution phase or during the seek
operation, then the NR (NOT READYI flag is set in Status Register to a 1 (high), and the command is
terminated after bits 7 and 6 of Status Reaister a are set to a and 1 resoectivelv.
If the time to write 3 bytes of seek command exceeds 150 Ils, the timing between first two Step Pulses
may be shorter then set in th.e Specify command by as much as 1 ms.

a

a

437

II

p.PD765
RECALIBRATE
The function of this command is to retract the read/write head within the FDD to the Track 0 position.
The FDC clears the contents of the PCN counter, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step Pulses are issued.
When the Track 0 signal goes high, the SE (SEEK END) flag in Status Register 0 is set to a 1 (high) and the
command is tenminated. Ifthe Track 0 signal is still low after 77 Step Pulse have been issued, theFDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags of Status Register 0 to both 15 (highs), and
terminates the command after bits 7 and 6 of Status Register 0 is set to 0 and 1 respectively.

The ability to do overlap RECALIBRATE Commands to multiple FDDs and the loss of the READY signal,
as described in the SEEK Command, also applies to.the RECAll BRATE Command.
SENSE INTERRUPT STATUS
An Interrupt signal is generated by the FDC for one of the following reasons:

1. Upon entering the Result Phase of:
e. Write Data Command
a. Read Data Command
f. Format aCyl inder Command
b. Read a Track Command
c, Read I 0 Command
g. Write Deleted Data Command
h. Scan Commands
d. Read Deleted Data Command
2. Readv Line of FOD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON·DMA Mode
Interrupts caused by reasons 1 and 4 above occur during normal command operations and are easily discernible by the processor. During an execution phase in NON-OMA Mode, DB5 in Main Status Register
is high. Upon entering Result Phase this bit gets clear. Reason 1 and 4 does not require Sense Interrupt

Status command. The interrupt is cleared by reading/writing data to FOC. Interrupts caused by reasons
2 and 3 above may be uniquely identified with the aid of the Sense Interrupt Status Command. This
command when issued resets the interrupt signal and via bits 5, 6, and 7 of Status Register 0 identifies
the cause of the interrupt.

SEEK END
BIT5

.0
1
1

INTERRUPT CODE

CAUSE

BIT6

BIT7

1
0

1
0

Normal Termination of Seek or Recalibrate Command

1

0

Abnonmal Termination of Seek or Recalibrate Command

Ready Line changed state, either polarity

Table 5
Neither the Seek or Recalibrate Command have a Result Phase. Therefore, it is mandatory to use the Sense
Interrupt Status Command aftar these commands to effectively terminate them and to provide veri,fication of
where the head is positioned (peN).
Issuing Sense Interrupt Status Command without interrupt pending is treated as an invalid command.

SPECIFY
The Specify Command sets the initial values for each of the three internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of one of the ReadIWrite Commands to the head unload
state. This timer is programmable from 16 to 240 ms in increments of 16 ms (01 = 16 ms, 02 = 32 ms .... OF =
240 ms). The SRT (Step Rate Time) defines the time interval between adjacent step pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E "" 2 ms, 0 = 3 ms, etc.). The HlT (Head load
Time) defines the time between when the Head load signal goes high and when the ReadlWrite operation starts.
This timer is programmable from 2 to 254 ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms . .. 7F =

254m.).
The time intervals mentioned above are a direct function of the clock (ClK on pin 19), Times indicated above
are for an 8 MHz clock, if the c~ock was reduced to 4 MHz (mini-floppy application) then all time intervals are
increased by a factor of 2.

The choice of OMA or NON·OMA operation i. mode by the NO (NON·OMA) bit. When this bit is high (NO
the NON-OMA mode is selected, and when NO =0 the OMA mode is selected.

= 1)

SENSE DRIVE STATUS
This command may be used by the processor whenever it wishes to obtain the status of the ,FOOs. Status
Register 3 contains the Drive Status information stored internally in FOC registers.

INVALID
If an invalid command is sent to the FOC (a command not defined above), then the FOe will terminate the command after bits 7 'and 6 'of Status Register 0 are set to 1 and 0 respectively. No interrupt is generated by the

I'P0765 during this condition. Bit 6 and bit 7 (010 and RaM) In the Main Status Register are both high ("1 ")
indicating to the processor that the ,uP0765 is in the Result Phase and the contents of Status Register 0 (STO)
must be react. Whe:n the processor reads Status Register 0 it will find a 80 hex indicating an invalid command
was received.
A Sense Interrupt Status Command must be sent after'a Seek or Re~librate Interrupt. otherwise the FOC wili
consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a
standby or no operation state.

438

FUNCTIONAL
DESCRIPTION OF
COMMANDS (CO NT.)

JLPD765
STATUS REGISTER
IDENTI FICATION

BIT
NAME

NO.

I
SYMBOL

DESCRIPTION

STATUS REGISTER 0
D7
Interrupt
Code

IC

D7 = 0 and D6 = 0
Normal Termination of Command, (NT). Command was completed and properly executed.
D7 - 0 and D6 - 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not
successfu lIy compl eted.

D6

D7 = 1. and D6 = 0
Invalid Command issue, (lC). Command which
was issued was never started.
D7 = 1 and D6 = 1
Abnormal Termination because during command
execution the ready signal from FDD changed
state.
D5

Seek End

SE

When the FDC completes the SEEK Command,
this flag is set to 1 (high).

D4

Equipment
Check

EC

D3

Not Ready

NR

If a fault Signal is received from the FDD, or if
the Track 0 Signal fails to occur after 77 Step
Pulses (Recalibrate Command) then this flag is
set.
When the F DD is in the not-ready state and a
read or write command is issued, th is flag is set.
If a read or write command is issued to Side 1 of
a single sided drive, then this flag is set.

D2

Head
Address

HD

This flag is used to indicate the state of the head
at Interrupt.

D1
DO

Unit Select l'
Unit Select 0

US 1
IUSO

These flags are used to indicate a Drive Unit
Number at Interrupt

D7

End of
~Ylinder

EN

D6
D5

Data Error

DE

D4

Over Run

OR

D3
D2

No Data

NO

STATUS REGISTER 1

I

When the F DC tries to access a Sector beyond
the final Sector of a Cylinder; this flag is set.
Not used. This bit is always 0 (low).
When the FDC detects a CRC error in either the
10 field or the data field, this flag is set.
If the FDC is not serviced by the main-systems
during data transfers, within a certain time
interval, this flag is set.
Not used. This bit always 0 (low).
During execution of READ DATA, WRITE
DELETED DATA or SCAN Command, if the
FDC cannot find the Sector specified in the lOR
Register, this flag is set.

II

During executing the READ ID Command, if
the FDC cannot read the ID field without an
error, then this flag is set.
During the· execution of the READ A Cylinder
Command, if the starting sector cannot be
found, then this flag is set.

439

ILPD765
BIT
NO.

NAME

DESCRIPTION

SYMBOL

STATUS REGISTER 1 (CONT.)

01

Not
Writable

NW

During execution of WRITE DATA, WRITE
DELETED DATA or Format A Cylinder Com·
mand. if the F DC detects a write protect signal
from the FDD, then this flag is set.

DO

Missing
Address
Mork

MA

If the FDC cannot detect the 10 Address Mark
after encountering the index hole twice, then
th is flag is set.
If the FDC cannot detect the Data Address Mark
or Deleted Data Address Mark, this flag is set.
Also at the same time, the MD (Missing Address
Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2

07
06

Not used. This bit is always

a (low).

Control
Mark

CM

During executing the READ DATA or SCAN
Command, if the F DC encou nters a Sector wh ich
contains a Deleted Data Address Mark, this
flag is set.

05

Data Error in
Data Field

DO

If the FDC detects a CRC error in the data field
then this flag is set.

04

Wrong
Cylinder

WC

This bit is related with the NO bit, and when the
contents of C on the medium is different from
that stored in the I DR, th is flag is set.

03

Scan Equal
Hit

SH

During execution. the SCAN Command. if the
condition of "equal"" is satisfied, th is flag is set.

02

Scan Not
Satisfied

SN

During executing the SCAN Command, if the
FDC cannot find a Sector on the cylinder which
meets the condition, then this flag is set.

01

Bad
Cylinder

BC

This bit is related with the NO bit, and when the
content of C on the medium is different from
that stored in the I DR and the content of C is
FF, then this flag is set.

DO

Missing
Address Mark
in Data Field

MD

07

Fault

FT

This bit is used to indicate the status of the
Fault signal from the F DO.

06

Write
Protected

WP

This bit is used to indicate the status of the
Write Protected signal from the FDD.

05

Ready

RY

This bit is used to indicate the status of the
Ready signal from the F DO.

04

Track

TO

This bit is used to indicate the status of the
Track a signal from the FDD.

03

Two Side

TS

This bit is used to indicate the status of the
Two Side signal from the FDD.

02

Head Address

HD

This bit is used to indicate the status of Side
Select signal to the FDD.

01

Unit Select 1

US 1

This bit is used to indicate the status of the Unit
Sel ect 1 signal to the F DO.

DO

Unit Select a

usa

This bit is used to indicate the status of the Unit
Select a signal to the FDD.

When data is read from the medium, if the FDC
find a Data Address Mark or Deleted
Data Add"ress Mark, then this flag is set.

ca~not

STATUS REGISTER 3

440

a

STATUS REGISTER
IDENTIFICATION {CONT.)

NOTES

It is suggested that you utilize the following applications notes:

CD

#8 - for an example of an actual interface, as well as a "theoretical" data
separator.

CZ> #10 - for a well documented example of a working phase lock loop.

II
765DS·R EV2·12·BO-CAT

441

NOTES

442

NEe

NEe Microcomputers, Inc.

p.PD781

DOT MATRIX PRINTER CONTROLLER
DESCRIPTION

The /lPD781 is an LSI Dot Matrix Printer Controller chip which contains all the
circuitry and control functions for interfacing an 8-bit processor to the Epson model
512,522, and 542 Dot Matrix Printers_ These printers are capable of printing 40
columns per row with a 5 x 7 dot matrix_ The /lPD781 is ideally suited for low-cost
Electronic Cash Registers (ECR) and Point of Sale (POS) systems because it frees
the processor from direct control of the printer and simplifies I/O software_
There are nine separate instructions which the /lPD781 will execute. Each of these
instructions requires only a single 8-bit byte from the processor to be executed_
Upon receipt of the instruction the /lPD781 assumes control of the printer, increments
the print head, activates the print solenoids, performs line feed on either receipt or
journal registers (or both), and performs these operations for an entire print line of
40 columns_
The /lPD781 contains its own on-board character generator of 96 symbols_ It contains a 40 column printer buffer and is capable of supplying status information to the
host processor on both the controller itself as well as the printer_ Characters to be
printed are written into the /lPD781 by the processor, and after the receipt of 40
characters the entire row is printed out with a single print command_

F EATU R ES

• Compatible with most Microprocessors including 8080A,lIo85A, /lPD780 (Z80™)
•
•
•
•

Capable of Interfacing to Epson Model 512, 522, or 542 Printers
Print Technique - Serial Dot Matrix
Print Font - 5 x 7 Dot Matrix
Column Print Capacity: 40 Columns for Model 512 and 522; 18 Columns for
Receipt and 18 Columns for Journal-Model
• Buffer Capacity: 40 Columns - Model 512 and 522; 2 to 18 Columns - Model 542
• 96 Character Set (Alphanumerics Plus Symbols)
• Print Speed - Approximately 3 Lines/sec (Bidirectional Printing)
• Paper Feed: Independent or Simultaneous; Receipt and Journal Feed; Fast Feed.
• Stamp Drive Output - Also Cutter Drive Output and Slip Release for Model 522.
• Sense Printer Status: Validation (Left/Right) Sensor - Model 512 and 522; TOF,
BOF Sensor - Model 542; Low Paper Detector - Model 512 and 522
• On-Board 6 MHz Oscillator (External Crystal Required)
• Operates from a Single +5V Power Supply (NMOS Technology)
• Available in 40-Pin Plastic Package

PIN CONFIGURATION

PIN NAMES
RL

X,
x2

RL
RR

Reset Signal (LI
Reset Signal (R)

Xl,X2

REsEi'

PR7

RESET

Crystal Inputs
Reset

vCC3

PAS
PA5

CS

Chip Select

RD
C/O

Read
Command/Data

WJl

Write
Data Bus

cs

PFR
PFJ
STM

vSS2

AD
c/o
WR
OPEN,

DO

0,
02
03

04
05

Os

Il PD

SO'i

781

MTIi

00-7

1'Rl-PFi 7

NE
VOLITOF
VDR/BOF

Print Solenoids
VDR/BOF Validation (R)/BOF Sensor
VDL/TOF Validation (L)/TOP Sensor
Low Paper Detector
NE

VCC2
OPEN2

MTD
SO'i

Motor Drive

1'R4

mil

PR3

PF.i
I'FR
mil

Stamp
Paper Feed Journal

07

PR2

Vss,

1'R,

II

Slip Release

Paper Feed Receipt
Timing Signal

TM: Z80 is a registered trademark of Zilog, Inc.

443

ILPD781
BLOCK DIAGRAM

+--..f

cs
c/O
Rei

+---1

READ/WRITE
CONTROL

1---......-.

I,IDR/BOF
VDL/TOF

WR+-_~

PIN IDENTIFICATION

PIN
NUMBER

SYMBOL

2,3

X1,X2

4

RESET

NAME

I/O

External
Crystal
Input

I

Reset

I

FUNCTION
This is a connection to external crystal

(Frequency: 6 MHz).

X1~could

also be

used as input for external oscillator.

The Reset signal initializes the "P07S1.
When RESE'F = 0, the buffer and register
contents are:
Bus Buffer - (lOM-1, IOB=PSR=O).
Column Buffer - All characters in this
buffer become 20(16) (ASCII).
Column Buffer Pointer -

It indicates

the left side of the buffer.
Column Capacity - 40 columns.
Print Head - Current Position.

6

CS

Chip Select

I

If the Chip Select is 0 when the data bus
becomes active, it enables the transfer of
data between the processor and the
"P07S1 via the data bus. If it is 1, the
data bus goes into High-Impedance state
(inactive). However, the operation of the
printer is not affected when CS=l.

S

RO

Read

I

The Read Control Signal is used to read
controller status or printer status to the
host processor. When RO=l, status information is presented.

10

WR

Write

I

The Write Control Signal is used to write
commands ·or print data to the "P07S1.
When' WR=O, data on the data bus is written into the "P07S1.

9

C/O

Command/
Data Select

I

The C/O Select is used to indicate what
kind of data is being input/output on the
data bus by the host processor. When
C/O=l in Read Operation, it is a Controller
Status· and in Write Operation it gives
commands. When C/O=O in Read Operation it is a Printer Status and in Write
Operation it is print data.

444

fLPD781
PIN IDENTIFICATION
(CaNT.)

PIN
I/O
NUMBER
12-19

SYMBOL
DO-7

FUNCTION

NAME
Data Bus

I/O
3-State

It is an a-bit bi..cfirectional data bus and is

used to transfer the data between the host
processor and the I'PD7B1.

5.26.
40

VCC1-3

DC Power

7.20

VSS1-2

Signal
Ground

11.25

OPEN1_2

:rhese are connected to +5V power supply.

These pins must be open. Do not connect

No

them to +5V. GND or any other signals.

Connection
21-24.
35-37

38

PR1-PR7

TIM

0

Print
Solenoid

I

Timing
Signal

These are drive signals for the print
solenoids. When these signals are 0, the print
solenoid should be activated. They are synchronized with the timing signal (TiM).
which is issued from the orinter.
The timing signal is issued from the printer.
It is used to generate and synchronize all the

basic printer operations such as paper feed,
1

39

RL

RR

Reset Signal
Left

I

Reset Signal

I

Right
30

MTD

Motor Drive

0

34

PFR

Paper Feed

0

Receipt
(j

33

PFJ

Paper Feed
Journal

0

32

STM

Stamp

0

31

SLR

Slip

0

Release

27

VDR/BOF

Validation

I

Right/BOF

Sensor

28

VDLlTOF

CD

Validation

I

Left/TOF
Sensor

29

Note:

NE

CD

Low Paper
DetectorCD

I

paper cut, etc.
The reset signal (R L=1) is issued by the

printer and indicates that the print-head is
positioned at the left margin.
The reset signal (RR-1) is issued by the
printer and indicates that the print-head is
positioned at the right margin.
The motor drive signal is issued to the
crinter and is active durinQ low state.
This is the drive signal for the paper feed
magnet and is active during low state. In
Model 512 and 542 it is used as a paper feed
magnet drive signal, and in Model 522 it is
used as a receipt paper feed magnet drive
sional.
This is the drive signal for the journal paper
feed and is active during low state. It is used
only with Model 522. and is not used at all
in Model 512 and 542.
This is the drive signal for both the stamp
magnet and the paper cutter and is active
during the low state. This signal is used only
with Model 522. If partial-cut or stamp and
full-cut are required, they may be implemented by using the Fast Feed command
which is synchronized with each timing pulse
before it is output. This signal is not used in
the Model 512 and 542.
This is the drive signal for the slip release
magnet and is active during low state. It is
used only with Model 542, and is active only
during the Print command or Fast Feed COm·
mand. This signal is not used in the Model
512 and 522.
In Model 512 and 522, the Validation Right
signal (VDR) is used to detect when the
print-head is located at the right side of the
paper. In Model 542. the BOF Sensor signal
(BO F) is used to detect the end of the paper.
I n Model 512 and 522. the Validation Left
signal (VDL) is used to detect when the
print-head is located at the left side of the
paper. In Model 542. the TOF Sensor signal
(TOF) is used to detect the top of the paper.
This signal is used to indicate a low paper
condition and is active in high state.

CD The VDR/BOF. VDLlTOF and NE signals are available on the data bus when a Printer
Status is requested by the host processor. The IJ.PD781 passes these signals onto the
host processor.

445

,.,.PD781
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOC to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts 7

DB2

CCs
CC4

DB3

CC3

DB4

CC2

CCO-7
HLGT

DBS

CC1

GPA

General Purpose Attribute

CCo
CCLK

SL12
VSP

Slit Line 12

HRTC

LCO_3

Line Counter 0 to 3

SLO

Slit Line 0

DBS
oB7
GND

High-light

Video Suppression

II

,",PD3301

BLOCK DIAGRAM
CHARACTER COUNTER

DBO-7

C elK

DATA BUS
BUFFER

CCO_7

ORO
DACK
INT
LINE COUNTER

LCO_3

RD

>VA
HRTC
VRTC

AO
LOGIC

HLGT
RASTER TIMING
AND
VIDEO CONTROL

RVV
VSP
SLO
SL12
CSR
GPA

LIGHT PEN REGISTER

L PEN

CS

Character Counter'
Counts the characters in a row, up to the number of the characters defined in Characters/Row,

Row Buffer
Consists of a dual RAM buffer. Each buffer can store up to 80 characters. During a DMA operation, the characters are written into the Row Buffer. One of the buffers is used for display.
Each character in the buffer is read with Character Clock (C ClKl, and the data appears in CCO_7.
At the same time, the data on the next row is written into another buffer by DMA control.
Buffer Input/Output Controller
•
•
•
•
•

Writes the characters into the Row Buffer, up to the number defined by Characters/Row.
Outputs the data from the Row Buffer to CCO-7.
Writes the attributes and special control character codes in"to the FIFO, up to the number
defined by Attributes/Row.
Reads the attribute codes from the FIFO and transfers them to the video circuit.
In case of Non~Transparent Attribute Mode, it distinguishes an ordinary character code from an
attribute code among the character data read from the Row Buffer.

FIFO (F irst Input, First Outputl
Consists of a dual RAM buffer. Each buffer can store up to 20 characters. By DMA operation,
attribute codes and special control characters are written into the FIFO. One of the buffers is used
for display. Whenever the read flag bit for FIFO is detected, an attribute code is read and
transferred to the video circuit. And at the same time, the attribute codes in the next row are written
into the rest of the buffers (another buffer) by DMA operation.

468

FUNCTIONAL DESCRIPTION

jLPD3301
FUNCTIONAL
DESCRIPTION (CONT.)

Line Counter
Counts the events of Rasters/Line, up to the number indicated by Lines/Character.
Raster Timing and Video Control
•
•

•

•

Outputs the HRTe based on the Character Counter during the time indicated by Horizontal
Retrace Time.
Outputs the VATe based on Row Counter which counts up the contents, row by row, during
the time indicated by Vertical Retrace Time.
Outputs HLGT, RVV, VSP, SLO, SL12, GPA based on attribute codes transferred from the
Buffer Output Controller.

Outputs the CSA based on the Blinking Time etc. at the position indicated by Cursor Address.

Light Pen Register
Memorizes a row address and column address when the L PEN signal is input. By using READ
LIGHT PEN instruction, the CPU can read the contents.

ABSOLUTE MAXIMUM
RATINGS*

.0°c to +70°C
-65' C to +125° C
· -0.5 to + 7 Volts
· -0.5 to +7 Volts
· -0.5 to +7 Volts

Operating Temperature.
Storage Temperature.

All Output Voltages
All Input Voltages
Supply Voltage VCC .

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .

'Ta = 25'C

DC CHARACTE R ISTICS

Ta = o°c to +70°C; VCC = +5V ± 5%
LIMITS
PARAMETER

SYMBOL

UNIT
MAX

MIN TYP
Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.2

Output Low Voltage

VOL

Output High Voltage

VOH

V

0.8

2.4

TEST
CONDITIONS

VCC + 0.5

V

0.45

V

IOL - 1.6 rnA

V

DBO-7:IOH - -150 !lA,
All Others: -80 !lA

VCC

Low Level Input Leakage

IlL

-10

il A

VIN =O.v

High Level I nput Leakage

IIH

+10

!lA

VIN ~ VCC

Low Level Output Leakage

IOL

-10

ilA

VOUT = OV

High Level Output Leakage

IOH

+10

ilA

VOUT - VCC

Power Supply Current

ICC

mA

90

CAPACITANCE

PARAMETER

SYMBOL

LIMITS
MIN

MAX

UNIT

I nput Capacitance

CIN

10

pF

Output Capacitance

COUT

20

pF

TEST CONDITIONS
fc; 1 MHz,
All Pins Except Pin
Under Test Tied to
AC Ground

469

JLPD3301
AC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

UNIT

MIN

MAX

Clock Cycle !"PD3301.1

tCY

0.5

10

liS

Time

tCY

0.38

10

liS

I"PD3301-2

TEST
CONDITIONS

Clock High level

tCH

150

Clock low level

tCl

150

1000

ns

Clock Rise Time

tCR

5

30

ns

Clock Fall Time

tCl

5

30

ns

Output Delay from C ClK t

tC01

0

150

ns

1TTl+15pF:
HRTC. CCO-7

400

ns

1TTl+15pF:
Except HRTC. CCO-7

300

ns

Output Delay
from C ClK t

I'PD3301·1

tC02

"PD3301·2

tC02

Command Cycle Time
AO. CS Set Up Time to WR

ns

tE

2tCY + 200

ns

tCY;;' 400 liS

tE

1

I'S

tCY

tAW

0

ns

AO. CS Hold Time to WR

tWA

0

ns

WR Pulse Width

tww

200

ns

Data Set Up Time to WR

tow

150

ns

Data Hold Time to WR

two

30

ns

DACK

tKW

0

ns

DACK t Hold Time to WR

tWK

0

ORO Delay from DACK I

tKO

0

INT Delay from WR t

tWI

INT Delay from C ClK t

tCI

j

Set Up Time to WR

ICY + 20

ns
ns

2tCY + 300

ns

1TTl + 50 pF

300

ns

1TTL + 50 pf

tAR

0

AO. CS Hold Time to RD

tRA

0

ns

RD Pulse Width

tRR

300

ns

Data Access Time from R D 1

tRD

0

tOR

ns

250

ns

150

ns

Cl = 100pF

ns

Cl=15pF

20

!------tCy------oool

CCLK

'CR

----+""'"

CCo-7

LCO-3. RVV
VRTC.HLGT------t----,
VSP.GPA
SLO.SL12
CSR
'C02

470

Cl -100pF

TIMING WAVEFORMS

CLOCK AND OUTPUT DELAY

HRTC

1TTL + 50 pF

250

AO. CS Set Up Time to RD

Data Float Delay from RD t

< 400 I'S

'C02

,",PD3301
READ OPERATION

TIMING WAVEFORMS
(CaNT.)

RD-----__.I

080 . 7 - - - - - - - -

DMA, INTERRUPT AND WRITE OPERATION
tE

AO

)~
r--

_tWA_

tAW

WR

\
_tww_
tE

- ---

_-tow_

two

)

DBO· 7

---

- --tWK

tKW

DACK

\
-tKO-

ORO

_tKO_

\

/
I--tWI

INT-----

CCLK--J

471

JLPD3301

The data is transferred from the external memory which contains the information about characters
and attributes to the Row Buffer under the control of ).IPD8257 DMA Controller. The data read
from the Row Buffer are Video Control Outputs and ROM Address Signal Outputs toward External
Character Generator. The ,uPD3301 also outputs horizontal and vertical retrace signals.

SYSTEM BUS

R

r-

G
B

I

r-....

~

n
~lLCO-3

_

RD

CS....

H

WR

L PEN
C CLK

HLGT
GPA
SL12
VSP
SLO

CC O-7

,.

).IPD3301
CRTC

INT

......
... DBO-7
DRQ
MEMR
~

ts HLDA RESET
A

DBO_7 AO-3
IIOR

100-

472

DACK

MEMW

A5 - A15 HLDR

IIOW

cjJ2

.

VIDEO
H. DRIVE

r- V. DRIVE
r- BRIGHTNESS

VRTC
RVV
CSR
HRTC

CHARACTER
GENERATOR

AO

r-

HI-SPEED
VIDEO INTERFACE

COLO~

MEMORY

SYSTEM CON F I GU RAT ION

).IPD8257
DMA CONTROLLER

f'PD3301

PACKAGE OUTLINES

I1PD3301C

I

1ft,

"Ii~'G

l~l}-~--~A

"00,,]-

(PLASTIC)
ITEM

MILLIMETERS

INCHES

A

51.5 MAX.
1.62 MAX.
2.54±0.1
0.5 ± 0.1
48.26 ± 0.1
1.2 MIN.
2.54 MIN.
0.5 MIN.
5.22 MAX.
5.72 MAX.
15.24 TYP.
13.2 TYP.
+0.1
0.25 -0.05

2.028 MAX.
0.064 MAX.
0.10 ± 0.004
0.019 ± 0.004
1.9 ± 0.004
0.047 MIN.
0.10MIN.
0.019 MIN.
0.206 MAX.
0.225 MAX.
0.600 TYP.
0.520 TYP.

B

C
0
E
F

G
H
I

J
K
L

M

a 010 +0.004
.

-0.002

/JPD3301D

G

o

F

r---------E-------~

(CERAMIC)
ITEM

MILLIMETERS

INCHES

A
B
C
0

51.5 MAX.
1.62 MAX.
2.54±0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN.
3.2 MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.05

2.03 MAX.
0.06 MAX.
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0.01 ± 0.0019

E

F

G
H
I

J
K

L
M

33010S-12·8Q.CAT

473

NOTES

474

t-IEC

NEe Microcomputers, Inc.

I'PD7001

8-BIT SERIAL OUTPUT AID CONVERTER
DESCRIPTION

TheMPD7001 is a high performance, low power 8-bit CMOS AID converter which
contains a 4 channel analog multiplexer and a digital interface circuit for serial
data 1/0. The AID converter uses a successive approximation as a conversion
technique.

AID conversion system can be easily designed.with the MPD7001 including all
circuits for AID convertion. The MPD7001 can be directly connected to 8-bit or
4-bit microprocessors.

FEATU R ES

• Single chip AID Converter
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Resolution: 8 Bit
4 Channel Analog Multiplexer
Auto-Zeroscale and Auto-Fullscale Corrections without any external components
Serial Data Transmission
High Input Impedance: 1,000 Mn
Single +5V Power Supply
Low Power Operation
Available.in 16 Pin Plastic Package
Conversion Speed 140 MS Typ_
PIN NAMES

EOC
Dl

V DD

EOC*

End of Conversion

VREF

Dl

Analog Channel Data load

SI

AG

SI

Serial Data Input

SCK

Aa

SCK

Serial Data Clock

SO

A2

SO*

Serial Data Output

CS

A1

CS

Chip Select

ClO

AO

Cl O,Cl 1

Successive Approximation Clock

Cl1

VSS

VSS

Digital Ground

AO.A1,A2,Aa

Analog Inputs

AG

Analog Ground

(TOP VIEW)

V REF

Reference Voltage Input

V DD

+5V

*Open Drain

Rev/1

475

p.PD7001
The 4 channel analog inputs are selected by the 2-bit signal which is applied to a serial
input and latched with a D L signal. The converted 8-b~t digital signals are output from
an open collector serial output (SO)_ The serial digital signals are synchronized with an
external clock signal applied to a SCK terminaL The intern~1 sequence controller' controls AID conversion by initiating a conversion cycle at a rise of the Chip Select (CS)_
At the final step of each AID conversion cycle the converted data is transmitted to an
8-bit shift register and immediately the 'next conversion cycle is started_, This results in
storage of the newest data in a shift register. At the final step of the first AID conversion cycle, an end of conversion signal (EOC) is output indicating that the converted
data is stored in a shift register. At a low level (active) of the chip select, the sequence
controller and EOC are re,set and the AID, conversion is stopped.

FUNCTIONAL
DESCR IPTION

BLOCK DIAGRAM

4 KQ

4 KO

Ao
A,
ANALOG
SYSTEM

A2

A3

CLa
Cl,

Operating Temperature . . . . . . . . . . _ ...... __ . _ . __ .. _ .... _O°C to +70°C
Storage Temperature. _ . _ . . . . . . _ . . . . . . . . . . . . . . . _ ..... ·65°C to +125°C
Analog Input Voltage . _ . . . . . . _ . _ ..... _ ..... _ ... -0.3 to VDD +0_3 Volts
Reference Input Voltage .... _ .. _ ... _ .. _ . . . . . . . . . -0_3 to VDD +0.3 Volts
Digital Input Voltage .. _ ..... _ . . . . . . . . _ .. _ .. _ . _ . . . .. -0.3 to +12 Volts
Max. Pull-up Voltage .. _ .. _ . _ .. _ . __ ... __ .. _ . _ .... _ . _ . _ .. __ +12 Volts
Supply Voltages __ ... _ .... _ .. _ . _ . _ ... _ . . . . . . . . . ____ -0.3 to +7 Volts
Power Dissipation .... _ . _ . _ ..... _ .. _ .... _ . __ . _ . __ .... ____ .200 mW
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.
*Ta = 25°C

476

ABSOLUTE MAXIMUM
RATINGS*

J'PD7001
PARAMETER

Em:

LIMITS

SYMBOL

Hold Time

MIN

tHECS

0

C'S Setup Time

tSCSK

12.5

Address Data Setup Time

tSIK

Address Data Hold Time
High Level Serial Clock
Pulse Width

TYP

MAX

EOC to

~s

CS to SCK,

ns

tHKI

100

ns

tWHK

400

ns

Low Level Serial Clock
Pulse Width

tWLK

400

ns

Data Latch Hold Time
Data Latch Pulse Width

tHKDL

200

ns

tWHOL

200

ns

Serial Data Delay Time

tOKO

Delay Time to Floating SO

tFCSO

CS Hold Time

tHKCS

CD

At a low level of
~PD7001

CS the data

SOO

ns

2S0

ns

200
IS

CS

~s

1SO

Notes:

TEST
CONDITIONS

UNIT

C!)

SCK to OL
SCK to SO, RL - 3K,
CL = 30 pF
~~

0

to High Impedance SO

ns

exchanged With external digital cirCUIt and at a high level of CS the

performsAJO conversion and does not accept any external digital signal. However, 5 pulses

of internal clock are needed before digital data output and then the IJPD7001 remains at the previous state of high level CS.
The rating corresponds to the 5 pulses of clock signal.
tSCSK IMin.1 = SliCK

@ The serial data delav time depends on load capacitance and pull-up resistance.

PARAMETER

SYMBOL

LIMITS
MIN

TVP

MAX

8

Resolution

TEST
CONDITIONS

UNIT
Bit

Voo = 5V
VREF = 2.25 to 2;75V
VOO - 5V

Non Linearity

0.8

%FSR

Full-Scale Error

2

LSB

VOD SV
VREF = 2.25 to 2.75V

ppmtC

VOO - 5V
VREF = 2.25 to 2.7SV

LSB

VOO - 5V
VREF = 2.2S to 2.75V

ppmtC

VOO 5V
VREF = 2.2S to 2.75V

LSB

VOO 5V
VREF = 2.25 to 2.75V

LSB

VOO - 4.S to 5.5V
VREF = 2.5V

VREF

30

Full-Scale Error Temp.
Coefficient
Zero Error

2

Zero Error Temp.
Coefficient

30

Total Unadjusted
Error 1

T.U.E.l

Total Unadjusted
Error 2

T.U.E.2

Analog Input Voltage

VI

Analog Input Resistance

RI

Conversion Time

tCONV

Clock Frequency Range

ICK

Clock Frequency
Distribution

AICK

Serial Clock Frequency

ISCK

High Level Voltage

VIH

Low Level Voltage

VIL

Digital Input Leakage
Current

II

Low Level Output
Voltage

VOL

2
2
0

VREF
1000

0.01

140
0.4
±5

0.5
±20
1

V

VI-OtoVDD

@

MHz
%

R -27 Kn,C 47 pF
liCK = 0.4 MHzl

MHz

@

V

3.6
1.4
1.0

10
0.4

V
~A

VI

V

IOL:= 1.7 mA

Va

IL

1.0

10

~A

Pd

5

15

mW

CD

CD

Mn

Power Dissipation

@

2.25 to 2.75V

~s

Output Leakage Current

Not..:

~

All digital outputs are put at a high level when VI

VSS to +12V

+12V

> VREF.

The AID conversion is started with CS going to a high level and at the final step of the first AID
conversion the EOC is at a low.
The conversion time is:

ICONV • 14 x 4 x 1 liCK

@

For fSCK > 500 kHz, the load capacitor (stray capacitance included) and the pull-up resistor which
are connected to serial output are required to be not more than 30 pF and 4 Kn. respectively,

477

I'PD7001

TIMING WAVEFORMS

DIGITAL DATA OUTPUT

..

L-J~------~tJ~-----------­
tHECS~:,.·

so

ANALOG CHANNEL SELECTION

tscsKH

I-tHKCS-\

SCK
HtSIK

HtHKI

SI------""'X'-__o..;1_@_2_....J~""_O.;;.O_@
......,,::::=====::
____

~

-

-

-

-

-

-

-

-

-

-

-

-

-

-

~

I----I'HKOL
OL _________

n

L __________

H'wHOL

Notes:

CD

The address set can be performed simultaneously with the digital data
outputting.

~ Analog Multiplexer Channel Selections:

Analog Input Address

DO

01

AO

L

L

A1

H

L

A2

L

H

A3

H

H

@ Rise and fall time of the above waveforms should not'be more than 50 ns.

PACKAGE OUTLINE
~PD7001C

~---------A--------~

\'(PLASTIC)
'TEM

MILLIMETERS

INCHU

A

19.4 MAX,

0.78 MAX.

n

G

H

I

0.81

....

0.03

0.6

17.71

0.0.
0.70

1.3

0.051

2.64 MIN.
0.6 MIN.
4.DlMAX.

Q.02MIN.

0.10

4.5& MAX.
7.•~r

...
M

0.10 MIN.

Q.18MAX.
0.18 MAX.

0.30
0.21

G. 2I -tO.10

-q.oo

0.01

70010So12·8()'CAT

478

NEe

NEe Microcomputers, Inc.

,.,. PD7002

12-BIT BINARY AID CONVERTER
DESCRIPTION

FEATURES

The tlPD7002 is a high performance, low power, monolithic CMOS AID converter
designed for microprocessor applications. The analog input voltage is applied to one
of the four analog inputs. By loading the input register with the multiplexer channel
and the desired resolution (8 or 12 bits) the integrating AID conversion sequence is
started. At the end of conversion EOC signal goes low and if connected to the interrupt line of microprocessor it will cause an interrupt. At this point the digital data can
be read in two bytes from the output registers. The tlPD7002 also features a status
register that can be read at any time.

• Single Chip CMOS LSI
• Resolution: 8 or 12 Bits
• 4 Channel Analog Multiplexer
• Auto-Zeroscale and Auto-Fullscale Corrections without any
External Components
• High Input Impedance: 1000Mn
• Readout of Internal Status Register Through Data Bus
• Single +5V Power Supply
• Interfaces to Most 8-Bit Microprocessors
• Conversion Speed: 5 ms
• Power Consumption: 20 mW
• Available in a 28 Pin Plastic Package

PIN CONFIGURATION

Xo

PIN NAMES

EOC
XO,xI

External Clock Input

AO

VSS

TTL Ground

RO

CI

Integrating Capacitor

WR

GO

Guard

2

A1

Vss

3

CI

4

XI

GO

5

CI

6

GO

7

tlPD

VREF

B

7002

GNO

9

cs

VREF

Reference Voltage Input

00

GNO

Analog Ground

CH3

Analog Channel 3

CH2

Analog Channel 2

CHI

Analog Channell

01
02

CH3

03

CH2

04

CHI

05

CHO

06

VOO

07

Rev/1

CHO

Analog Channel 0

VOO

TTL Voltage (+5V)

00-0 7

Oata Bus

CS

Chip Select

WR,RO

Control Bus

AOAI

Address Bus

EOC

End of Conversion Interrupt

479

jc.PD7002
c
n
1/0 SECTION

.1
)I

0,0- r - -

'I

0,0--

c

c

H

H

n

BLOCK DIAGRAM

C

2

n

n

I I I I
MPX DECODE
AND 12/8 BIT

REGISTER

050-HIGH 8YTE

0,0-0,0-0,00,0000-

THREE
STATE
BUFFER

-~

VREF

I

=+=

AID ANALOG
SECTION

I

I II I

INTEGRAT 'NG

_

--0 ,CAfACITOR
ANALOG
GNO

CONV'RS'ON
DATA
REGISTER

CONTROL
MODE
DATA
REGISTER

fr

r-

csoWiio- r-

rAOo- r-

\lOD

LOW BYTE

r- ...... ~

I

--0

I

ANALOG
MULTIPLEXER

L.-.-

12/8

AllO-

A,o- rEOCo--

1

12 BIT DATA
SEQUENCE
CONTROL
SECTION

AID DIGITAL
SECTION

r-

r-o

Vss

$
d::

II
DC CHARACTERISTICS

Ta '" 25.:t 2°C; VOD = +5 ± O.25V. VREF '" +2.50V, fCK '" 1 MHz
PARAMETER

SYMBOL

LIMITS
MIN

TYP

MAX

12

Resolution

TEST
CONDITIONS

UNIT
Bits

VOO = SV,
VREF = 2'.5 ± O.2SV

Non Li'nearity

0.05

0.08

%FSR

VOO - SV,
VREF = 2.S ± 0.2SV

FuliscaJe Error

O.OS

0.08

%FSR

VOO - SV,
VREF = 2.S ± 0.2SV

Zeroscale Error

O.OS

0.08

%FSR

VOO - SV,
VREF = 2.5 ± 0.2SV

Fullscale Temperature Coefficient

10

PPMtC

VOO -SV

Zeroscale Temperature Coefficient

10

PPMtC

VOO

Analog Input Voltage Range

VIA

Analog Input Resistance
Total Unadjusted Error 1

RIA
T.U.E.l

0

VREF
1000

Mfl

O.OS

0.08

%FSR

0.08

%FSR

Total Unadjusted Error 2

T.U.E.2

O.OS

Clock Input Currant

IXI

S

Clock Input High Level

VXIH

Clock Input Low Level

VXIL

High Level I nput Voltage

VIH

Low Level Input Voltage

VIL

High Level Output Voltage

VOH

= 5V

V
VIA - VSS to VOO
VREF 2.25 to 2.75V.
VOO = SV
VREF - 2.SV,
VOD 4.75 to 5.25V

=

SO

~A

V

VOO-l.4
VSS+l.4
22
0.8
3.S

V

=

V

Ta

V

T a --20°Cto+70°C

V

10 - -1.6 rnA
T a .= _20°C to +70°C

V

10 - +16mA
Ta '" -20°C to +70°C

20 C to +70 C

Low Level Output Voltage

VOL

Oigltal Input Leakage Current

II

1

10

~A

VI

High-Z Output Leakage Current

I Leak
Pd

1

10

~A

Vo - VSS to VOO

1S

2S

rnW

fCK" 1 MHz

Power Dissipation

480

0.4
(

Vssto VOD

JJ.PD7002
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature
Storage Temperature .. .
All Input Voltages .. .
Power Supply
Power 0 issipation ....
Analog GNO Voltage ..

· . . . . . . . . -20°C to +70°C
. . . . . . . . -65°Cto+125°C
. . -0.3 to VOO + 0.3 Volts
. -0.3 to +7 Volts
· . . . . . . . . . . . . . . 300 mW
· . . . . . . .. VSS ± 0.3 Volts

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°C

AC CHARACTE R ISTICS

Ta = 25" , 2'C; VDD = +5 , 0.25V; VREF = 2.5V; fCK = 1 MHz; CINT = 0.033 J'F
PARAMETER

SYMBOL

LIMITS
MIN

TYP

MAX

TEST
CONDITIONS

UNIT

Conversion Speed 112 bitl

tCONV

8.5

10

15

ms

fCK = 1 MHz

Conversion Speed (8 bit)

'CONV

2.4

4

5

ms

fCK = 1 MHz

Clock Frequency Range

fCK

0.1

1

3

MHz

Integrating Capacitor Value

CINT'

0.029

Address Setup Time
CS,AO,Al,toWR

tAW

50

ns

Address Setup Time
CS, AO, Al, to RD

tAR

50

ns

Address Hold Time WR to

tWA

50

ns

Address Hold Time RD to
CS,AO,Al

tRA

50

ns

low level WR Pulse Width

tww

400

ns

low Level RD Pulse Width

tRR

400

ns

Data Setup Time Input
Data to WR

tow

300

ns

Data Hold Time WR
Input Data

tWD

50

ns

J'F

VREF - 2.50V,
fCK=lMHz

CS,AO,Al

to

Output Delay Time R D to
Output Data

tRD

300

ns

Delay Time to High Z
Output RD to Floating
Output

tDF

150

ns

TIMING WAVEFORMS
AO.Al
CS

~
----tAWt--o----t-t----t
ww

1;

lTTl + 100 pF

*

tW-A---

~-'"'I-.::::::::t-D-w---i>K

~A

,~

tRR

~ "t'
tAR

.""

----- - - - - _ . /

--

-

tAD

II

:

"/
-tDF_

- --

- -

-

481

,",PD7002
CONTROL TERMINALS
CS

RD

WR

AI

AO

MODE

H

x

x

x

x

Not selected

L

H

Ii

x

x

Not selected

L

H

L

L

L

,Write mode

INTERNAL
FUNCTION

CONTROL TERMINAL
FUNCTIONS

DATA INPUT-OUTPUT
TERMINALS
High impedance

Data latch

Input status, 0" DO = MPX address
03,* 8 bit/12 bit conversion

AID start

designatiO~.

-

RxB>TxA>TxB
PR lOR ITY RxA>TxA>RxB>TxB

o
o

0

o

8085 MASTER MODE
8085 SLAVE MODE
8086 MODE
UNDEFINED

INTERRUPT VECTORED/NON·VECTORED
'-- ALWAYS ZERO

o

RTSB PIN 10
SYNC8 PIN 10

WRITE REGISTER 3

Rx ENA8LE
SYNC CHARACTER LOAD INHIBIT
'-----ADDRESS SEARCH MODE (SDLC)
' - - - - - - - Rx CRC ENABLE
' - - - - - - - - ENTER HUNT PHASE
' - - - - - - - - - - AUTO ENABLES

a

a

a

a

Rx
Rx
Rx
Rx

5
7
6
8

BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

WRITE REGISTER 4

PARITY ENABLE
PARITY EVEN/ODD

a
a
a
a
a
a

492

a
a

a
a

a
1

a

SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1 1/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER

8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE

X 1 CLOCK MODE
X16CLOCKMODE
X32 CLOCK MODE
X64 CLOCK MODE

WRITE REGISTER
BIT FUNCTIONS
(CONT.)

JLPD7201
WRITE REGISTER
BIT FUNCTIONS
(CONT.)

WRITE REGISTER 5

I 07 I

06

I

Os

I 04 I 03 I

02

I
l

I 01 I DO I

I

L

Tx CRC ENABLE
'----RTS
'------CRC-16/CRC-CCITT
' - - - - - - - - T x EN~\BLE
'----------SENDBREAK

o
o

0
1

o

Tx
Tx
Tx
Tx

5
7
6
8

BITS lOR LESSl/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

-DTR

WRITE REGISTER 6

I 07 I 06 I Os I 04 I 03 I 02 I 01 I DO I

I I

L
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC

BITO
BIT 1 \
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7

ALSO SDLC
ADDRESS FIELD

WRITE REGISTER 7

I 07 I 06 I Os I 04 I 03 I 02 I 01 I DO I

I I

L

!~~giH~ \

SYNC
SYNC
SYNC
SYNC
Note:

CD

BIT
BIT
BIT
BIT

12
13
14
15

Q)

For SDLC it must be programmed to "01111110" for flag recognition.

493

fLPD7201
....-----, INTERRUPT STRUCTURE

RECEIVE CHARACTER

PARITY ERROR
'RECEIVE OVERRUN ERROR
FRAMING ERROR
END OF FRAME ISOLC)

FIRST DATA CHARACTER
FIRST NON-SYNC
CHARACTER ISYNC)
VALID ADDRESS
BYTE ISOLC)

,uPD7201
INTERRUPT

DeD TRANSITION
CTS TRANSITION
SYNC TRANSITION
Tx UNOERRUN/EOM
BREAK/ABORT DETECTION
BUFFER BECOMING EMPTY

WR2s BITS
IN CH.A

-PRIN

MODE

x

x

x

1st INTA

2nd INTA

3rd INTA (*)

D7 D6 D5 D4 D3 D2 D1 DO

D7 D6 D5 D4 D3 D2 D1 DO

D7 D6 D5 D4 D3 D2 D1 DO

Non-vectored

High-Z

High-Z

High-Z

1

0

1

V7 Vs V5 V4 V3 V2 Vl Vo

1

1

0

1

High-Z

D5 D4 D3

0

CONTENTS ON DATA BUS DRIVEN BY THE fJPD7201 AT EACH INTA SEQUENCE

1

0

0

0

8086 Master

1

1

0

(Call)
0 1

1

0

0

1

8085 Master

1

1

0

0

1

0

1

0

8085 Slave

High-Z

V7 V6 V5V4 V3 V2 Vl Vo

1

0

1

1

8086 Slave

High-Z

High-Z

1

1

0

0

8086

High-Z

V7 V6 V5 V4 V3 V2 Vl Vo

1

1

0

1

8086

High-Z

High-Z

(0) 3rd

0

0

0

0

0

0

0

0

(I

0

0

High-Z
(I

0

0

0

0

High-Z

jjiij'fA is 8085 Mode

7201 DS-12-80-CAT

494

NEe

NEe Microcomputers, Inc.

j.LPD7210

INTELLIGENT GPIB INTERFACE CONTROLLER
DESCRIPTION

FEATURES

The MPD7210 TLC is an intelligent GPIB Interface Controller designed to meet all of
the functional requirements for Talkers, Listeners, and Controllers as specified by the
IEEE Standard 488-1978. Connected between a processor bus and the GPIB, the TLC
provides high level management of the GPI B to unburden the processor and to simplify
both hard~are and software design. Fully compatible with most processor arch)tectures,
Bus Driver/Receivers are the only additional components required to implement any
type of GPIBinterface.

• All Functional Interface Capability Meeting IEEE Standard

•
•
•

•
•
•
•
•
•
•
•
•
•

SH 1 (Source Handshake)
AHl (Acceptor Handshake)
T5 or TE5 (Talker or Extended Talker)
L3 or LE3 (Listener or Extended Listener)
SR 1 (Service Request)
RL 1 (Remote Local)
PP1' or PP2 (Parallel Port (Remote or Local Configuration))
DCl (Device Clear)
DTl (Device Trigger)
Cl-5 (Controller (All Functions))
Programmable Data Transfer Rate
16 MPU Accessible Registers - 8 Read/8 Write
2 Address Registers
- Detection of MTA, MLA, MSA (My Talk/Listen/Secondary Address)
- 2 Device Addresses
EOS Message Automatic Detection
Command (IEEE Standard 488-78) Automatic Processing and Undefined Command
Read Capability
DMA Capability
Programmable Bus Transceiver I/O Specification (Works with T.I.IMotorola/lntel)
1 to 8 MHz Clock Range
TTL Compatible
N Channel MaS
+5V Single Power Supply
40-Pin Plastic DIP
8080/85/86 Compatible

PIN CONFIGURATION

II

T/R 1
T/R 2

CLOCK
RESET
T/R 3
DMAREQ
DMAACK
CS
RD
WR
INT
DO
D1
D2
D3
D4
D5
D6 :
D7
GND

MPD721 0

495

p.PD7210
PIN

NAME

1

T/Rl

0

Transmit/Receive Control - Input/Output Control Signal
for the GPIB Bus Transceivers.

2

T/R2

0

Transmit/Receive Control - The function of T/R2, T/R3
are determined by the value of TRM1, TRMO of the
address mode register.

3

ClK

I

Clock - (1-8 MHz) Reference Clock for generating the
state change prohibit times T1, T6, T7, T9 specified in
IEEE Standard 488-1978.
Reset - Resets 7210 to an idle state when high (ac):ive high).

I/O

DESCRIPTION

4

RST

I

5

T/R3

0

6

ORO

0

7

DACK

I

8

CS

I

9

RD

I

Read - (Active low) Places contents of read register
specified by RSO-2 - on 00-7 (Computer Bus).

10

WR

I

Write - (Active low) writes data on 00-7 into the write
register specified by RSO-2.

0

Interrupt Request - (Active High/low) Becomes active
due to any 1 of 13 internal interrupt factors (unmasked)
active state software configurable, active high on chip reset.

11

l%
INT

12-19

00-7

I/O

Transmit/Receive Control - Function determined by
TRMl and TRMO of address mode register (See T/R2).
DMA Request - 7210 requests'data transfer to the com·
puter system, becomes low on input of DMA acknowledge
signal DACK.
DMA Acknowledge - (Active low) Signal connects the
computer system data bus to the data register of the 7210.
Chip Select - (Active low) Enables access to the register
selected by RSO-2 (read or write operation).

Data Bus - 8 bit bidirectional data bus, for interface to
computer system.

20

GND

21-23

RSO-2

24

IFC

I/O

Interface Clear - Control line used for clearing the inter·
face functions.

25

REN

I/O

26

ATN

I/O

Remote Enable - Control line used to select remote or
local control of the devices.
Attention - Control line which indicates whether data on
010 lines is an interface message or device dependent message.

27

SRO

I/O

Service Request - Control line used to request the con·
troller for service.

28-35

0101-8

I/O

36

DAV

I/O

Data Input/Output - 8 bit bidirectional bus for transfer
of message on the GPIB.
Data Valid - Handshake line indicating that data on 010
lines is valid.

37

NRFD

I/O

Ready for Data - Handshake )ine indicating that device is
ready for data.

38

NDAC

I/O

Data Accepted - Handshake line indicating completion of
message reception.

39

EOI

I/O

40

VCC

End or Identify - Control line used to indicate the end of
'multiple byte transfer sequence or to execute a parallel
polling in conjunction with ATN.
+5V DC - Technical SpecifiCations: +5V; NMOS;
500 MW; 40 Pins; TTL Compatible; 1-8 MHz.

496

I

Ground.
Register Select - These lines select one of eight read
(write) registers during a read (write) operation.

PIN IDENTIFICATION

J.I. PD721 0

BLOCK DIAGRAM

REGISTERS

DATA IN

07-00
MESSAGE
DECODER

COMMAND PASS

THROUGH

BYTE OUT
INTERFACE
FUNCTIONS

ADDRESS STATUS
SH 1

AH 1
ADDRESS MODE

T5!TE5

ADDRESS 0/1

L3/LE3

GPIB CONTROL

SR 1
END OF STRING

RLl

P?1/PP2

INT

_fr-------

DC 1

r/R 3-T/R 1

oT 1
SEA IAL POLL

Cl

C2
PARALLEL POLL

C3

AUX.IAIIIBI/IEI
C4

CLOCK

--------1

C6

INTERNAL
COUNTER

AUX. COMMAND
DECODER

RESET ---~~-----------------4~~

________J

497

fLPD7210
INTRODUCTION

The IEEE Standard 488 describes a "Standard Digital Interface for Programmable
Instrumentation" which, since its introduction in 1975, has become the most
popular means of interconnecting instruments and controllers in laboratory, automatic test and even industrial applications_ Refined over several years, the 488-1978
standard, also known as the General Purpose Interface Bus (GPIB), is a highly
sophisticated .standard providing a high degree of flexibility to meet virtually most
all instrumentation requirements. The MPD721 0 TLC implements all of the functions that are required to interface to the GPIB. While it is beyond the scope of
this document to provide a complete explanation of the IEEE 488 Standard, a
basic description follows:
The GPIB interconnects up to 15 devices over a common set of data control lines.
Three types of devices are defined by the standard: Talkers, Listeners, and Controllers, although some devices may combine functions such as Talker/listener or
Tal ker /Controller.
Data on the GPI B is transferred in a bit parallel, byte serial fashion over 8 Data I/O
lines (Dl0l - Dl08). A 3 wire handshake is used to ensure synchronization of
transmission and reception. In order to permit more than one device to receive data
at the same time, these control lines are "Open Collector" so that the slowest
device controls the data rate. A number of other control lines perform a variety of
functions such as device addressing, interrupt generation, etc.
The MPD721 0 TLC implements all functional aspects of Talker, Listener and Controller functions as defined by the 488-1978 Standard,and on a single chip.

GENERAL

The MPD7210 TLC is an intelligeil! controller designed to provide high level protocol
management of the GPIB, freeing the host processor for other tasks. Control of the
TLC is accomplished via 16 internal registers. Data may be transferred either under
program control or via DMA using the TLC's DMA control facilities to further reduce
processor overhead. The processor interface of the TLC is general in nature and may
be readily interfaced to most processor lines_
In addition to providing all control and data lines necessary for a complete GPIB
implementation, the TLC also provides a unique set of bus transceiver controls
permitting the use of a variety of different transceiver configurations for maximum
flexibility.
INTERNAL REGISTERS
The TLC has 16 registers, eight of which are read and 8 write.
ADDRESSING

REGISTER NAME

CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS

WA
WA
WA
WA
WA
WA
WA
WA

CS
CS
CS
CS
CS
CS
CS
CS

,

Data In [OR]

Interrupt Status 1 [lR)
Interrupt Status 2 (2R 1

Serial Poll Status [3Rl
Address Status [4R)
Command Pass Through [5Rl
Address 0 [SR I

Address 1 [7Rl

,

,
,

,
, ,
, ,

,
,
,
,

Byte Out [OWl

0

0

Interrupt Mask 1 [tW)

0

0

Interrupt Mask 2 [2Wl

0

Serial Poll Mode [3W)

0

, ,

Address Mode [4W]
Auxiliary Mode (5W]

Address 0/1 [SWJ
End of String [7W]

498

SPECIFICATION

A A A WA
S S S WA
0 WA
2
0
0 WA
0
0
0
WA
0
0 WR
0
WR
0
0 WR
WR
0
0 WR
WA

,

0

,
0

,
, ,
, ,
, , ,
0

0

0

0

I 017
I CPT
I INT
L§.8
I CIC

I CPT7
I

X

I EOI
B07
CPT

016
APT

I

015
I DET
SROl I LOK
PEND I S6
ATIii I SPMS
CPT6 I CPT5
DTO I DLO
I DT' I DL'

I B06 I B05
I APT I DET
0
I SAOI IDMAO
S8 I ,"v I S6
ton
I Ion I TRM'
CNT2 I CNT' I CNTO
AAS I DT I DL
I EC7 I EC6 I EC5

I 014
I END
I REM
I S5
I LPAS
I CPT4
I AD5-Q

I AD5-1

013
DEC
CO
S4
TPAS
CPT3
A04-0
AD4-'

I 804 I B03

I END I DEC
I OMAI I CO
I S5 I S4
I TRMO I 0
I COM4 I COM3
I AD5 I AD4
I EC4 I EC3

012
EAR

I 011 I DIO I
I DO I 01 I

REMC I ADSci
I S2 I S, I
I TA I MJMNI
CPT2 I CPT1 I CPTO I
AD3-0 I AD2-o I AD'-ol
I AD3-' I AD2-' I AD 1-1 I
LOKe

I

S3
LA

B02 I BD'
EAA I DO
LOKC I AEMC
S3 I S2
0
I ADM'
CQM2 I COM'
AD3 I AD2
EC2 I EC'

BOO I
01 I
ADScl
S' I
ADMOI
COMO I
AD'I
ECO I

ILPD7210

DATA REGISTERS
The data registers are used for data and command transfers between the GPIB and the
microcomputer system.
DATA IN (OR)

IDI7

OI6

DI5

OI4

OI3

OI2

I OIl

DIO

Holds data sent from the GPIB to the computer
BYTE OUT (OW)

I B07 I B06 I B05 I B04 I B03 I B02 IBOl I BOO I

Holds information written into it for transfer to the GPIB
INTERRUPT REGISTERS
The interrupt registers are composed of interrupt status bits, interrupt mask bits,
and some other non interrupt related status bits.
READ
INTERRUPT
STATUS 1 [lR]

I CPT

APT

DET

END

DEC

INTERRUPT
STATUS 2 [2R]

liNT

I SROl I

LOK

REM

CO

ERR

DO

DI

I LOKC IREMC IADSC I

WRITE
INTERRUPT
MASK 1 [lW]
INTERRUPT
MASK 2 [2W]

I CPT

I

a

APT

DET

END

I DEC

ERR

DO

DI

ISROl IDMAO IDMAI I CO I LOKC IREMC IADSC I

There are thirteen factors which can generate an interrupt from the J.lPD721 0, each
with their own status bit and mask bit.
The interrupt status bits are always set to one if the interrupt condition is met.
The interrupt mask bits decide whether the INT bit and the interrupt pin will be
active for that condition.

I nterrupt Status Bits
INT
CPT
APT
DET
END
DEC
ERR
DO
DI
SRQI
LOKC
REMC
ADSC
CO

OR of All Unmasked Interrupt Status Bits
Command Pass Through
Address Pass Through
Device Trigger
End (END or EOS Message Received)
Device Clear
Error
Data Out
Data In
Service Request Input
Lockout Change
Remote Change
Address Status Change
Command Output

II

Non Interrupt Status Bits
LOK
REM
DMAO
DMAI

Lockout
Remote/Local
Enable/Disable DMA Out
Enable/Disable DMA In

499

J.L PD721 0
SERIAL POLL REGISTERS
READ
SERIAL POLL
STATUS [3R]

S8

I PEND I

S6

I

S5

S4

S3

S2

S1

S3

S2

S1

WRITE
SERIAL POLL
MODE [3W]

S8

rsv

S6

I

S5

S4

The Serial Poll Mode register holds the STB (status byte: 58, 56-51) sent over the
GPIB and the local messagerSV (request service). The Serial Poll Mode register
may be read through the Serial Poll Status register. The PEND is set by rsv; 1, and
cleared by NPRS ·,rsv; 1 (NPRS; Negative Poll Response State).
ADDRESS MODE/STATUS REGISTERS

IGIG I ATi'J I SPMS I LPAS ITPAS
Iton I Ion I TRM1 I TRMO I 0

ADDRESS STATUS [4R]
ADDRESS MODE 14W]

LA

o

TA

I MJMN I

I ADM1 I ADMO I

The Address Mode register selects the address mode of the device and also sets the
mode for T/R3 and T /R2 the transceiver control lines.
The TLC is able to automatically detect two types of addresses which are held in
address registers 0 and 1. The addressing modes are outlined below.
ADDRESS MODES

ton

Ion

ADM1

ADMO

1

0

0

0

ADDRESS
MODE
Talk only

CONTENTS OF
ADDRESS (0)
REGISTER

CONTENTS OF
ADDRESS (1)
REGISTER

Address Identification Not Necessary

mode

0

1

0

0

Listen on Iy

Not Used

mode

0

0
0

0

0
0

0

1
1

1

0
1

Address mode 1

Add ress mode 2
Address mode 3

or Major listen

Minor talk address
or Minor listen

address

Major tal k address

address

Primary address

Secondary address

(talk or listen)

(talk or listen)

Primary address

Primary address

(major talk or
major listen)

(minor talk or
minor listen)

Combinations other than above
indicated Prohibited.
Notes:

Al -

Either MTA or MLA reception is indicated by coincidence of either address with the
received address. Interface function Tor L.

A2 - Address register 0 = primary, Address register 1

=

secondary, interface function TC

or LG.

A3 - CPU must read secondary address via Command Pass Through Register. TE or LC
Command.

500

ILPD7210

ADDRESS STATUS BITS
ATN
LPAS
TPAS
CIC
LA
TA
MJMN
SPMS

Data Transfer Cycle (device in CSBS)
Listener Primary Addressed State
Talker Primary Addressed State
Controller Active
Listener Addressed
Talker Addressed
Sets minor TIL address Reset; Major TIL address
Serial Poll Mode State

ADDRESS REGISTERS
ADDRESS

a [6RI

I x

ADDRESS 1 [7RI

I

ADDRESS all [6WI

I ARS

EOI

I
I

DTO

DLO

DTl

OLl

DT

DL

I AD5-D I AD4-D I AD3-0 IAD2-D I AD1-D I
I AD5-1 I AD4-1 I AD3-1 I AD2-1 I AD1-1 1
I AD5 I AD4 I AD3 I AD2 I ADl I

Address settings are made by writing into the address Oil register. The function
of each bit is described below.
ADDRESS Oil REGISTER BIT SELECTIONS
ARS
Selects which address register 0 or 1
DT - Permits or Prohibits address to be detected as Talk
o L - Permits or Prohibits address to be detected as Listen
AD5 - ADl - Device address value
EO! - Holds the value of EO! line when data is received
COMMAND PASS THROUGH REGISTER
COMMAND PASS
THROUGH [5RI

The CPT register is used such that the CPU may read the 010 lines in the cases of
undefined command, secondary address, or parallel poll response.
END OF STRING REGISTER
END OF
STRING [7wl

IEC7 I

EC6

EC5

EC4

EC3

EC2

ECl

ECOI

This register holds either a 7 or 8 bit EOS message byte used in the GPIB system to
detect the end of a data block. Aux Mode Register A controls the specific use of
this register.
AUXILIARY MODE REGISTER
AUXILIARY
MODE [5W]

I CNT2 I CNTl

CNTO

I COM4 I COM3 I

COM2

COMl

COMO

I

501

f'PD7210
This is a multipurpose register. A write to this register generates one of the following
operations according to the values of the CNT bits.
COM

CNT
2

1

0

4

3

2

1

0

0

0

C4

C3

C2

C,

Co

0

0

,

0

F3

F2

F,

FO

0

, ,

,
, ,
, ,
0

0

0

0

OPERATION

0

Issues an auxiliary command specified by

C4 to CO.
The reference clock frequency is specified

and T" T6, T7, T9 are determined as a
result.

Makes write operation to the parallel poll

U

S

P3

P2

P,

A4

A3

A2

A,

AO

register.

84

B3

B2

B,

BO

register.

0

0

0

El

EO

AUXILIARY COMMANDS

register.

Makes write operation to the aux. (AI
Makes write operation to the aux. (B)
Makes write operation to the aux. (E)

register.

0 0 0 C4 C3 C2 Cl Co

COM
43210
00000

iepon

00010
00011
00100
00101
00110
00111

crst
rrfd
trig
rtl
seoi
nvld

01111

vld

aXOOl
10000
10001
10010
11010

sppf
gts
tca
tcs
tcse

Immediate Execute pon - Generate local
pon Message
Chip Reset - Same as External Reset
Release RFD
Trigger
Return to Local Message Generation
Send EOI Message
Non Valid (OSA reception) - Release DAC
Holdoff
Valid (MSA reception, CPT, DEC, DET) Release DAC Holdoff
Set/Reset Parallel Poll Flag
Go To Standby
Take Control Asynchronously
Take Control Synchronously
Take Control Synchronously on End

10011
11011
11100
11101
lXl10
1X 111
10100

Itn
Itnc
lun
epp
sifc
sren
dsc

Listen
Listen with Continuous Mode
Local Unlisten
Execute Parallel Poll
Set/Reset I FC
Set/Reset R EN
Disable System Control

INTERNAL COUNTER

0 0 1 0 F3 F2 Fl FO

The internal counter generates the state change prohibit times (T 1, T6, T7, Tg)
specified in the IEEE std 488·1978 with reference to the clock frequency.
AUXILIARY A REGISTER

1 0 0 A4 A3 A2 Al AO

Of the 5 bits that may be specified as part of its access word, two bits control the
GPIB data receiving modes of the 7210 and 3 bits control how the EOS message is
used.

502

Jl.PD7210

DATA RECEIVING MODE

Al

AO

0

0

Normal Handshake Mode

0

1

RFD Holdoff on all Data Mode

1

0

RFD Holdoff on End Mode

1

1

Continuous Mode

BIT
NAME

FUNCTION

A2

0
1

Prohibit
Permit

Permits (prohibits) the setting of the END bit
by reception of the EOS message.

A3

0
1

Prohibit
Permit

Permits (prohibits) automatic transmission of
EN D message simultaneously with the transmission of EOS message TACS.

A4

0
1

7 bit EOS
8 bit EOS

Makes the 8 bits/7 bits of EOS register the
valid EOS message.

AUXILIARY B REGISTER

1 0 1 B4 B3 B2 B1 BO

The Auxiliary B Register is much like the A Register ih that it controls the special
operating features of the device.
BIT
NAME

FUNCTION
1

Permit

0

Prohibit

1

Permit

0

Prohibit

BO

B1

1
B2
0
B3

1
0

1

Permits (prohibits) the detection of undefined
command. In other words, it permits (prohibits) the setting of the CPT bit on reception
of an undefined command.
Permits (prohibits) the transmission of the
END message when in serial poll active state
(SPAS).

T1
(high-speed)
T1
(low-speed)

T 1 (high speed) as T 1 of handshake after
transmission of 2nd byte following data
transmission.

INT
INT

Specifies the active level of INT pin.

1st; SROS

SROS indicates the value of 1 st level local
message (the value of the parallel poll flag is
ignored).
SROS; 1 ... 1st; 1.
SROS; 0 ... 1st; O.

B4

0

1st ; Parallel
Poll Flag

The value of the parallel poll flag is taken
as the 1st local message.

503

J.LPD7210
AUXILIARY E REGISTER

1 1 0 0 0 0 El EO

This register controls the Data Acceptance Modes of the TLC.
BIT

FUNCTION
1

EO

0
1

El

0

Enable
Disable

DAC Holdoff by initiation of DCAS

Enable
Disable

DAC Holdoff by initiation of DTAS

o

Parallel Poll Register

U

S

The Parallel Poll Register defines the parallel poll response of the pPD721 O.

I0

11

1 1 1U 1s.1

P3

1P21 Pll

L

"""'>'G ".,u, ,n

OUTPUT LINE (DIOl TO DIOS)

SPECIFYING STATUS BIT
'--------POLARITY
S= 1: IN PHASE
S - 0 : IN REVERSE PHASE
L..-_ _ _ _ _ _ _ { U

=1

: NO RESPONSE TO PARALLEL POLL

U = 0 : RESPONSE TO PARALLEL POL L

504

7210DS-12-S0·CAT

NEe

NEe Microcomputers, Inc.

,., PD7225

PROGRAMMABLE LCD CONTROLLER/DRIVER
DESCR IPTION

F EATU R ES

The J1PD7225 is a programmable peripheral device containing all the circuitry
necessary for interfacing a microprocessor to a wide variety of alpha-numeric Liquid
Crystal Displays (LCDs). The display controller hardware automatically synchronizes
the drive signals for any static or multiplexed LCD containing up to 4 backplanes,
and up to 32 segments _The J1PD7225 is fully compatible with most microprocessors,
and communicates with them through a 2-line, 8-bit Serial port_ It can be easily
configured into multiple chip designs for larger LCD applications_ In addition, the
J1PD7225 includes on board 8-segment Numeric and 15-segment Alpha-Numeric
decoders, and programmable blinking capabilities_ The J1PD7225 is manufactured with
a low-power single 5V CMOS process, and is available in a 52-pin plastic flat package_

• Single Chip LCD Controller
•
•
•

•
•
•
•
•

•
•
•
•
•
•
•

Direct LCD Drive
Selectable Backplace Drive Configuration
- Static; 2-, 3-, or 4-Backplane Multiplexed
Programmable Display Configurations
- 8-Segment Numeric - up to 16 Characters
- 15-Segment Alpha-Numeric - up to 8 Characters
32-Segment Drive Li nes
Selectable Display Bias Configuration
- Static; 1/2 or 1/3
Automatic Synchronization of Segment and Backplane Drive Lines
Dual 32 x 4 Bit RAMs for Display Data Storage
Programmable Display Data Addressing
Individual Segment
- 16-Character, 8-Segment Numeric Decoder
- 64-Character, 15-Segment Alpha-Numeric Decoder
Programmable Blinking Capability
- Individual Segment, Individual Character, or Entire Display
8-Bit Serial Interface
Compatible with most 4-Bit, 8-Bit, and 16-Bit Microprocessors
Fully Cascadable for Larger LCD Applications
Single +5V Power Supply
CMOS Technology
52-Pin Plastic Flat Package
PIN DESCRIPTION

PIN CONFIGURATION
SYMBOL

DESCRIPTION

LCD Segment Drive Outputs
COMO·COM3

LCD Backplane Dnve Outputs

Vss

Ground

VDD

Power Supply POSitive

VLCD,·VLCD3

LCD Power Supply

SCK

Serial Clock Input

51

Senal Input

CS

Chip Select

C/O

Command/Data Select
System Clock Input, Output

SYNC

Synchronization Signal \/0 Port
for f:"1ultlpie chip

BUSY

Busy Output

RESET

Reset Input

NC

No Connection

505

p.PD7225
8"

830

.,. ______________________________ 8,

LCD
TIMING
CONTROL

"0

COM, COM,

CQM, COMO

DISPLAY

DATA
LATCH

32x4RAM

SEGMENT
DECODER

32x4RAM

FOR

FOR

DISPLAY DATA

BLINKING DATA

voo___..
Vss_

C/O

WRITE

COMMAND
DECODER

CONTROL

SI

506

seK

BLOCK DIAGRAM

}L PD7225

COMMAND DESCRIPTION,
1, MODE SET

I

40-5F

0

I

The MODE SET command sets up the Backplane Drive Configuration, the Display
Bias Voltage Configuration, and the AIC Drive Frequency for the MPD7225,
The Backplane Drive Configuration is defined as follows:
03

D2

Backplane Drive Configuration

0
1
1
0

1
1
0
0

Static (l-Backplane)
2-Backplane Multiplexed
3-Backplane Multiplexed
4-Backplane Multiplexed

The Display Bias Voltage Configuration is defined as follows:
04

Display Bias Voltage Configuration

0
1

113 (three voltage)
112 (two voltage)
Static (single voltage; default when D3D2; 00)

X

The AIC Drive Frequency is defined as follows:
Dl

DO

A/C Drive Frequency

0

0

fc/27 Hz

0

1

fc/2 S Hz

1

0

fc/29 Hz

1

1

fc/211 Hz

,
_
Note, LCD Frame Frequency -

2. UNSYNCHRONOUS DATA
TRANSFER

A/C Drive Frequency

# of active
' B k i D ' I'
ac pane rive Ines

10

0 1 1

0 0 0 0

30

-

II

I
-

The Normal Transfer of data from the Display Data RAM to the segment output latches
latches occurs with the rising edge of CS. The UNSYNCHRONOUS DATA TRANSFER command implements this mode of data transfer, and also disables the
SYNCHRONOUS DATA TRANSFER operation.
3. SYNCHRONOUS DATA
TRANSFER

100110001

31

Data can also be transferred from the Display Data RAM to the segment output
latches with the rising edge of f c. The SYNCHRONOUS DATA TRANSFER command implements this mode of data transfer, and also disables the UNSYNCH RONOUS DATA TRANSFER operation,

507

•

~PD7225

4. INTERRUPT DATA TRANSFER

COMMAND DESCRIPTION
(CONT.)

100111000

Occasionally, the Host microprocessor system may experience events, such as prior·
itized Hardware interrupts, that may disrupt communications with the MPD7225.
Display Data transfers to the MPD7225 may be interrupted, without disrupting the
MPD7225 internal display data protocol, by issuing an INTERRUPT DATA TRANS·
FER command at the beginning of the interrupt service routine. Display data
updating may be resumed in an orderly fashion after the interrupt service routine is
completed.

10

5. CLEAR Display Data

0100000

20 ]

All locations in the Display Data RAM are set to zero by executing the CLEAR
D ISPLA Y DATA command. The Data Pointer is also cleared, and set to its initial
location.
6. CLEAR BLINKING DATA

100000000

00

I

All locations in to Blinking Data RAM are set to zero by executing the CLEAR
BLINKING DATA command. The Data Pointer is also cleared, and set to its
initial location.
7. LOAD DATA
POINTER
To access a particular location in either the Display Data RAM, or the BLINKING
DATA RAM the Data Pointer must be given the corresponding address of that
location. The LOAD DATA POINTER command transfers 5 bits of immediate
data to the Data Pointer.
8. WRITE DISPLAY
DATA

o

DO·DF

The WR ITE D ISPLA Y DATA command transfers 4 bits of immediate data to the
Display Data RAM location addressed by the Data Pointer. After the transfer is
complete, the Data Pointer is automatically incremented.
9. WRITE BLINKING
DATA
The WRITE BLINKING DATA command .transfers 4 bits of immediate data to the
Blinking Data RAM location addressed by the Data Pointer. After the transfer is
complete, the Data Pointer is automatically incremented.
10. ENABLE DISPLAY

10

0 0

o0

0 1

11

The ENABLE DISPLAY command turns on the LCD, and starts the automatic
display controller ~ardware of the MPD7225.

508

p.PD7225

11. DISABLE DISPLAY

1000 1

0 0 0 0

The DISABLE D ISPLA Y command turns off the LCD, and stops the automatic
display controller hardware of the fJPD7225.
•
12. ENABLE BLINKING

I

0

0

0

o

If a particular LCD application requires blinking several segments, the appropriate
information must have been transferred to the Blinking Data RAM previously. The
ENABLE BLINKING command selects the Blinking frequency according to the
value of DO, and turns the Blinking feature on.
DO

Blinking Frequency

0

fc/216 Hz

1

fc/217 Hz

13. DISABLE BLINKING

10 0 0 1

1 0 0 0

The DISABLE BLINKING command turns the Blinking feature OFF.
14. ENABLE SEGMENT DECODER

10 0 0 1

0 1 0 1

The fJPD7225 has an internal 8·segment Numeric data decoder, and an internal
15·segment Alpha-Numeric data decoder. These decoders can be used for automatic
display data addressing, by the Host microprocessor to absorb some of the system
overhead required to decode display data for the fJPD7225.
The ENABLE SEGMENT DECODER command implements this mode of display
data addressing. Upon execution, display data received by the fJPD7225 is diverted
to one of the segment decoders. The segment decoder then writes display data to
the Display Data RAM. The distinction between 8-segment decoding and 15-segment
decoding is made by the MSB of the display data:
MSB

Decoding Selected

0

8-segment Numeric
15-segment Alpha-Numeric

1

15. DISABLE SEGMENT DECODER

II

100010100

The DISABLE SEGMENT DECODER command stops the segment decode
addressing, and enables the transfers of Display Data from the Host microprocessor
directly to the Display Data RAM.

509

p.PD7225

a

16. OR DISPLAY DATA

BO-BF

I

The OR DISPLAY DATA command performs a LOGICAL OR between the
Display Data addressed by the Data Pointer, and 4 bits of immediate data.
The result is written to the same Display Data location, and the DataPointer is
automatically incremented.
17. AND DISPLAY DATA
The AND DISPLAY DATA command performs a LOGICAL AND between the
Display Data addressed by the Data Pointer, and 4 bits of immediate data. The result
is written to the same Display Data location, and the Data Pointer is automatically
incremented.

a

18. OR BLINKING DATA

The OR BLINKING DATA command performs a LOGICAL OR between the Blinking
Data addressed by the Data Pointer, and 4 bits of immediate data. The result is
written to the same Blinking Data location, and the Data Pointer is automatically
incremented.
19. AND BLINKING DATA

11

a a a

D3 D2 D1 DO

I

80-8F

The AND BLINKING DATA command performs a LOGICAL AND between the
Blinking Data addressed by the Data Pointer, and 4 bits of immediate data. The
result is written to the same Blinking Data location, and the Data Pointer is automatically incremented.

510

1

JI. PD7225

COMMAND SUMMARY

INSTRUCTION CODE

BINARY

COMMAND
1. Mode Set

DESCRIPTION
Sat up Driving Mode of LCD,
induding:

07

I

Do

I Os I D. I
D.

03

I 02 I

0,

D3

02

D,

I

DO
DO

I

HEX
4o.5F

1) Backplane drive
2) Display Bias
3) LCD Frame Frequency
2. Unsychronous Data Transfer

30

Synchronize writing of display

data with CS
3, Synchronous Data Transfer

Synchronize writing of display
data with LCD Frame

3'

Frequency

4. Interrupt Data Transfer
5. Clear Display Data

Interrupt writing of display

38

Clear the Display Data RAM

20

d",

and the Oats Pointer
6. Clear Blinking Data

00

Clear the Blinking Data RAM

and the Data Pointer
7. Load Data Pointer

Load Data Pointer with 5 Bits
of Immediate Data

8. Write Display Data

Write 4 Bits of Immediate Data
to the Display Data Location
addressed by the Data Pointer;
Increment Data Pointer

D3

D2

9. Write Blinking Data

Write 4 Bits of Immediate Data
to the Blinking Data location
addressed by the Data Pointer;
Increment Data Pointer

D3

D2

D.

03

D2

DO

EO-FF

D,

DO

DO·OF

D,

DO

CO-CF

D,

10. Enable Display

Start Automatic LCD
Controller Hardware

11

11. Disable Display

Stop AutomH

0.7 VOO

VOO

V

eL1. External Clock

Clock Low Voltage

VL

0

0.3 VOO

V

el"

High Level
Leakage Current

ILiH

10

I'A

SI, SCK, C/O, CS, RESET
VI = VOO

Low Level
Leakage Current

ILiL

-10

I'A

SI, SCK, C/O, CS, RESET
VI = OV

High Level
Output Voltage

VOH

Low Level

VOL
IOH

VOO -0.5

= -10 I'A

V

BUSY, IOH

0.5

V

SYNC, BUSY, IOL = 550 I'A,
VOO = 5.5V, Ta = 25'C

-180

I'A

Output Voltage
High Level

External Clock

Output Current

SYNC, Vo = 0.5,
VOO = 5.5V, Ta = 25°C

2.7':; VLCD':; VDD
PARAMETER

SYMBOL

LIMITS
MIN

TYP
2

Backplane Drive
Output Impedance

RCOM

Segment Drive
Output Impedance

RSEG

512

11

MAX

UNITS

CONDITIONS

kll

COMO' COM3,
Display Bias ~ 1/3
or Static

kll

COMO' COM3
Display Bias ~ 1/2

kll

50. 531

DC ELECTRICAL
CHARACTERISTICS
FOR LCD

'" PD7225
CAPACITANCE
LIMITS
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS
SI, SCK,

c/i), CS,

CI

pF

Output Capacitance

Co

pF

CL2, BUSY, COMOCOM3, SO-S31

I nput/Output Capacitance

Cia

pF

SYNC

Clock Capacitance

CCLK

pF

CLl

Input Capacitance

REsET

AC ELECTRICAL
CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

UNITS
MIN

Clock Frequency

Ic

Clock Cycle

tCY.p

Clock Pulse Width
High

TYP

CONDITIONS

MAX

200

~

kHz

RI

itS

External Clock

tW.pH

MS

External Clock

Clock Pulse Width
Low

tW.pL

MS

External Clock

SCK Cycle

tCYK

SCK Pulse Width
High

tWKH

nS

SCK Pulse Width
Low

tWKL

nS

SCK Hold Time

tHKS

0

nS

SI Setup Time

tSIK

250

nS

to SCKt

SI Hold Time

tHK

200

nS

after SCKI

BUSY" Delay

tDBC

1

MS

after CS"

MS

alter Bth SCKt

5

1

kn

MS

after BUSY1

Time

BUSY I Delay

3

tDKB

Time

C/D Setup Time

tSDK

9

MS

to Bth SCKI

C/D Hold Time

tHKD

1

MS

alter 8th SCKt

CS Setup Time

tSCK

CS"Hold Time

tHKr.

High Level CS
Pulse Width

tWHC

8tCY.p

MS

Low Level CS

tWLC

8tCY.p

MS

1

MS

to 1st SCKI

MS

after 8th SCK 1

Pulse Width

513

II

J'PD7225

CLOCK WAVE FORM

tWLO--~'"

SERIAL INTERFACE
TIMING

514

ILPD7225

I-IPD7225G PACKAGE
DIMENSION

I~

12.0TYP

----1
.. 1

--I

I-- 1.0±O.1

0

1
a.

>t-

o

N

=
=
=
0
=
=

~

0

I

1.0±O.1

PIN 1

0.4 TYP

--l f..

UNIT: mm

14.0 TVP

0.11

~

f - - I_

_

T==(

_

C

_

_

cOCO 0

----t"1

2.6 TVP

21.8±0.4-_ _

CO

C

0

C

C

C

) _ _ _- . -

7225DS·12·80·CAT

515

NOTES

516

NEe
NEe Microcomputers, Inc.

JLPD7227

[~Joolm~~~~illrnW

PROGRAMMABLE LCD CONTROLLER/DRIVER
DESCR IPTION

The IlPD7227 is a programmable peripheral device containing all the circuitry necessary for interfacing a microprocessor to a wide variety of dot matrix Liquid Crystal
Displays (LCDs). The display controller hardware automatically synchronizes the drive
signals for a multiplexed dot matrix LCD containing up to 16 rows and up to 48
columns. The IlPD7227 is fully compatible with most microprocessors, and communicates with them through a 3-line, B-bit serial I/O port. It can be easily configured into
multiple chip designs for larger LCD applications, and includes an ASCII 5 x 7 dot
matrix decoder to simplify alphanumeric display data decoding. The IlPD7227 is
manufactured with a low-power single 5V CMOS process, and is available in a 64-pin
plastic flat package.

FEATURES

• Single Chip LCD Controller
•
•
•

•
•
•
•

•
•
•
•
•
•

Direct LCD Drive
Selectable 8- or 16-Backplane Multiplexed Drive
Programmable Display Configurations
8-Row by 40-Column Dot Matrix
Cascadable into
- 16-Row Multiplexed Backplane Applications
- 40-Column Drive Applications
Selectable Display Bias Configuration
Automatic Synchronization of Rowand Column Drive Lines
Dual 40 x 8 Bit RAMs for Display Data Storage
Programmable Display Data Addressing
-- Individual Dot
- 64-Character ASCII 5 x 7 Dot Matrix Decoder
8-Bit Serial Interface
Compatible with most 4-Bit, 8-Bit, and 16-Bit Microprocessors
Fully Cascadable for Larger LCD Applications
Single +5V Power Supply
CMOS Technology
64-Pin Plastic Flat Package
PIN NAMES

PIN CONFIGURATION

DESCRIPTION

SYMBOL
COLo-COL39

o

,"PD7227

0

LCD Column Drive Outputs

ROWa-ROW7

LCD Row/COlumn Drive Outputs

Vss (V LCDo )

Ground

VLCD1-VLCD4

LCD Power Supply

VOO IV LCD5 )

Power Supply Positive

SCK

Serial Clock Input

SI

Serial Input

SO/BUSY

Serial Output/Busy Output

~.

Chip Select

cifi

Command Data Select

SYNC

Synchronization Signal 1/0 Port
for cascaded applications

CL

System Clock Input

RESET

Reset Input

NC

No Connection

517

II

}LPD7227
BLOCK DIAG RAM
ROW a

_.

ROW 7

I

OR
:
ROWS - ROW 15 I

,,

COLO - COL39

I
I

Vao (V LCOO )
VLCD1

VLC02
VLCD3

LCD
VOLTAGE
CONTROL

VLCD4
VSS (V LCD5 l

16

READ/WRITE

CONTROL

i

I

cs

C/O

s,

SO/BUSY

JlPD7227G PACKAGE
DIMENSIONS

~~t

O.16MAX

518

~~

7227DS-9-80-CAT

NEe

NEt Microcomputers, Inc.

,.,. PD7720

DIGITAL SIGNAL PROCESSOR
DESCR I PTION

~rn~[~~~ ~illrnW

The NEC pPD7720 Signal Processing Interface (SPI) is an advanced architecture
microcomputer optimized for signal processing algorithms. Its speed and flexibility
allow the SPI to efficiently implement signal processing functions in a wide range of
environments and applications.
The NEC SPI is the state of the art in signal processing today, and for the future.

APPLICATIONS

• Speech Synthesis and Analysis
• Digital Filtering
• Fast Fourier Transforms (FFT)
• Dual·Tone Multi·Frequency (DTMF) Transmitters/Receivers
• High Speed Data Modems
• Equalizers
• Adaptive Control
• Sonar/Radar Image Processing
• Numerical Processing

PERFORMANCE
BENCHMARKS

• Second Order Digital Filter (BiQuad)
• SINE/COS of Angles
• p/A LAW to Linear Conversion
• FFT: 32 Point Complex
64 Point Complex

FEATURES

• Fast Instruction Execution - 250 ns

2.25ps
5.25ps
0.50 ps
0.7 ms
1.6 ms

•
•
•

16 Bit Data Word
Multi-Operation I nstructions for Optimizing Program Execution
Large Memory Capacities
512 x 23 Bits
- Program ROM
- Coefficient ROM
510 x 13 Bits
128x16Bits
- Data RAM
• Fast (250 ns) 16 x 16-31 Bit Multiplier
• Dual Accumulators
• Four Level Subroutine Stack for Program Efficiency
•

•

•
•
•

Multiple I/O Capabilities
- Serial
- Parallel
- DMA
Compatible with Most Microprocessors, Including:
- pPD8080
- pPD8085
- pPD8086
- pPD780 (Z80™*)
Power Supply +5V
Technology NMOS
Package - 28 Pin Dip

II

*Z80 is a trademark of Zilog Corporation.

519

p.PD7720

NC

vcc

~

2

AO

ORa

3

~

PO

4

lfD'

P1

5

WFf

DO

6

SORa

01

71lPD7720D

SO

02'

8

SI

03

9

'MElir
'SJ'EN"

O~

05

SCK

06
07

INT
RST

GNO

ClK

PIN CONFIGURATION

Fabricated in high speed NMOS, the JlPD.7720 SPI is a complete 16-bit microcomputer
on a single chip. ROM space is provided for program and coefficient storage, while
the on-chip RAM may be used for temporary data, coefficients and results. Computational power is provided by a 16-bit Arithmetic/Logic Unit (ALU) and a separate
16 x 16 bit fully parallel multiplier. This combination allows the implementation of a
"sum of products" operation in a single 250 nsec instruction cycle. In addition, each
arithmetic instruction provides for a number of data movement operations to further
increase throughput. Two serial I/O po'rts are provided for interfacing to codecs and
other serially-oriented devices while a parallel port provides both data and status
information to conventional JlP for more sophisticated applications. Handshaking
signals, including DMA controls, allow the SPI to act as a sophisticated programmable
peripheral as well as a stand alone microcomputer.

FUNCTIONAL DESCRIPTION

Memory is divided into three types, Program ROM, Data ROM, and Data RAM.
The 512 x 23 bit words of Program ROM are addressed by a 9-bit Program Counter
which can be modified by an external reset, interrupt, call, jump, or return instruction.

MEMORY

The Data ROM is organized in 512 x 13 bit words and is also addressed through a 9-bit
ROM pointer (RP Reg,) which may be modified as part of an arithmetic instruction
so that the next value is available for the next instruction. The Data ROM is ideal
for storing the necessary coefficients, conversion tables and other constants for all
your processing needs.
The Data RAM is 128 x 16 bit words and is addressed through a 7-bit Data Pointer
(DP Reg.). The DP has extensive addressing features that operate simultaneously with
arithmetic instructions so that no added time is taken for addressing or address
modification.

BLOCK DIAGRAM
RAM

,ax'.

STACK

. ..
.
o

FLAGA

m

CLK_

RST_
'NT

Vcc_
ONo-

520

INTERRuPT

~

v

o
v

0

v

MULTIPL.IER

J.L PD7720

PIN IDENTIFICATION
PIN

NAME

FUNCTION

I/O

1

NC

I

No Connection.

2

DACK

I

DMA Request Acknowledge. Indicates to the
IlPD7720 that the Data Bus is ready for a DMA
transfer. IDACK ~ CS.AO ~ 0)

3

ORO

0

DMA Request signals that the IlPD7720 is
requesting a data transfer on the Data Bus.

PO, Pl

0

PO, P1 are general purpose output control lines.

6-13

00-0 7

I/O Tristate

Port for data transfer between the Data Register
or Status Register and Data Bus.

14

GND

15

ClK

I

16

RST

I

4,5

Single phase Master Clock input.
Reset initializes the ,LLPD7720 internal logic and

sets the PC to O.
17

INT

I

I nterrupt. A low to high transition on this pin

will lif interrupts are enabled by the program)
execute a call instruction to location 1DOH.

18

SCK

I

19

SIEN

I

Serial Data Input/Output Clock. A serial data
bit is transferred when this pin is high.
Serial Input Enable. This line enables the shift
clock to the Serial Input Register.

20

SOEN

I

Serial Output Enable. This pin enables the shift
clock to the Serial Output Register.

21

51

I

Serial Data Input. This pin inputs 8 or 16 bit
serial data words from an external device such

as an AID .converter.

22

SO

0

Serial Data Output. This pin outputs 8 or 16

bit data words to an external device such as an
DI A converter.

23

SORa

0

Serial Data Output Request. Specifies to an
external device that the Serial Data Register
has been loadE!d and is ready for output.

SORa is reset when the entire 8 or 16 bit
word has been transferred.

24

WR

I

25

AD

I

Write Control Signal writes the contents of
data bus into the Data Register.

Read Control Signal. Enables an output to
the Data Port from the Data or Status
Register.

26

CS

I

Chip Select. Enables data transfer with
Data or Status Port with RD or WR.

27

AO

I

Selects Data Register for Read/Write (tow) or
Status Register for read Ihigh).

28

VCC

+5V Power

521

,.,.PD7720
ARITHMETIC

General

CAPABILITIES
One of the unique features of the SPI's architecture is its arithmetic facilities. With a
separate multipler, ALU, and multiple internal data paths, the SPI is capable of
carrying out a multiply, an add, or other arithmetic operation, and move data between
internal registers in a single instruction cycle.

AlU
The ALU is a 16-bit 2's complement unit capable of executing 16 distinct operations
on virtually any of the SPI's internal registers, thus giving the SPI both speed and
versatility for efficient data management.
Accumulators (ACCA/ACCB)
Associated with the ALU are a pair of 16-bit accumulators, each with its own set of
flags, which are updated at the end of each arithmetic instruction (except NOP). In
addition to Zero Result, Sign Carry, and Overflow Flags, the SPI incorporates auxilliary Overflow and Sign F lags (SA 1, SB 1, OVA 1, OVB 1). These flags enable the
detection of an overflow condition and maintain the correct sign after as many as 3
successive additions or subtractions.

FLAG A

SAl

SAO

CA

ZA

OVAl

OVAO

FLAG B

SBl

SBO

CB

ZB

OVBl

OVBO

ACC A/B FLAG REGISTERS
Sign Register (SGN)
When OVAl (or OVB1) is set, the SAl (or SB1) bit will hold the corrected sign of the
overflow. The SGN Register will use SA 1 (SB 1) to automatically generate saturation
constants 7FFFH(+) or 8000H(-) to permit efficient limiting of a calculated valve.
Multiplier
Thirty-one bit results are developed by a 16 x 16 bit 2's complement multiplier in
250 ns. The result is automatically latched in 2-16-bit registers M&N (LSB in N is
zero) at the end of each instruction cycle. The ability to have a new product available
and to be able to use it in each instruction cycle, provides significant advantages in
maximizing processing speed for real time signal processing.
Stack
The SPI contains a 4-level program stack for efficient program usage and interrupt
handling.
Interrupt
A single level interrupt is supported by the SPI. Upon sensing a high level on the INT
terminal, a subroutine call to location 100H is executed. The EI bit of the status
register is automatically reset to 0 thus disabling the interrupt facilities until reenabled
under program control.

522

Il-PD7720

INPUT/OUTPUT

General
The NEC 5PI has 3 communication ports; 2 serial and one 8-bit parallel, each with
their own control lines for interface handshaking_ The parallel port also includes DMA
control lines (DRQ and DACK) for high speed data transfer and reduced processor
overhead_ A general purpose 2 bit output (see Figure 1) port, rounds out a full complement of interface capability_

<:

-

:> 00- 07
SO
SORQ

AD
WR

S5Eiii

CS
AO
OMA
INTERFACE

DACK

{

SERIAL I/O
INTERFACE

SCK
",P07720

SI
SIEN

ORQ

INTERRUPT

INT

RESET
CLOCK

RST
CLK

Po
}

PI

OUTPUT PORT

Serial I/O
Two shift registers (51, 50) that are software-configurable to 8 or 16 bits land are
externally clocked (5CK) provide simple interface between the 5PI and serial peripherals such as, A/D and D/A converters, codecs, or other 5Pls_
SERIAL I/O TIMING
SCK

s
SORa
SQEN

~--------~.-----

OUTPUT
DATA

SO ACK

HIGH Z

____

tSORS

140A6

--~/ ______

------

.- --- HIGH Z
_(' _______ _

5 OR

.J

SOLOAD~~

______________________________~,_____L,_________

I NPUT OAT A __..J'~__...r..---"__J\....__'____.J"___=___"'""""*_ _...r..-'"8:..,:0:.:.;Rc:;5J'-'-'4-,-O",R.:.;6:J\.-'"5;..;0;.;.;Rc;.7J'--__- - ' ' - - _

~~-----------------------------~I
__________________

~rI~

SI REG

LOAS~:~~E

CD

Data clocked out on falling edge of SCK.

@

Data clocked in on rising edge of SCK.

_____

~

@ Broken line denotes consecutive sending of next data.

PARALLEL I/O

The 8-bit parallel I/O port may be used for transferring data or reading the 5PI's
status_ Data transfer is handled through a 16-bit Data Register (DR) that is softwareconfigurable for double or single byte data transfers_ The port is ideally suited for
operating with 8080,8085 and 8086 processor buses and may be used with other
processors and computer systems_

523

",PD7720
PARALLEL RIW OPERATION

CS

AO

1
X

X
X

0

WR

Ij;:

OPERATION

RO

{NO effect on intern~1 operation. 00-07 are at
high impedance levels.

1

~}

0

0

1

Data from 00-07 is latched to DR

0

0

1

0

Contents of 0 R are output to 00- 0 7 G)

0

1

0

1

Illegal

0

1

1

0

Eight MSBs of SR are output to 00-07

0

X

0

0

Illegal

l

-0.5

ClK High Voltage

Vt/>H

3.5

Output low Voltage

VOL

Output High Voltage

VOH

Input load Current

Illl

TYP

MAX
0.8

UNIT
V

VCC+O·5

V

0.45

V

VCC +0.5

V

0.45

V

2.4

CONDITION

V

IOl = 2.0 mA
IOH =-400IJA

-10

IJA

VIN =OV

Input load Current

ILiH

10

IJA

VIN = VCC

Output Float leakage

IlOl

-10

IJA

VOUT= VCC

Output Float leakage

IlOH

10

IJA

VOUT = 0.47V

Power Supply Current

ICC

200

280

mA

TYP

MAX

UNIT

Ct/>

20

pF

CIN

10

pF

COUT

20

pF

PARAMETER
ClK, SCK Input
Capacitance
Input Pin Capacitance
Output Pin Capacitance

SYMBOL

MIN

CONDITION

fc = 1 MHz

II
531

,uPD7720
Ta = -10 - +70°C. VCC = +5V ± 5%
PARAMETER

MIN

TYP

MAX

UNIT

2000

ns

ClK Cycle Time

CY

ClK Pulse Width

<1>0

ClK Rise Time

R

20

ns

ClK Fall Time

F

20

ns

Address Setup Time for R 0

tAR

0

ns

Address Hold Time for RD

tRA

0

ns

R 0 Pulse Width

tRR

200

Data Delay from RD

"tRD

Read to Data Floating

tDF

20

125
50

ns
150

ns

CL

100

ns

CL

= 100 pF
= 100 pF

CL

= 100 pF

CL

= 100 pF

Address Setup Time for WR

tAW

0

tWA

0

ns

WR Pulse Width

tww

200

ns
ns

Data Setup Time for WR

tow

150

Data Hold Time for WR

two

0

ORO Delay

tAM

SCK Cycle Time

tSCY

480

SCK Pulse Width

tSCK

230

SCK Rise/Fail Time

tRSC

SORa Delay

tDRa

30

SOEN Setup Time

tsoc

50

SOEN Hold Time

tcso

10

SO Delay

tDCK

SO Delay from SORQ

tDzRa

SO Delay from SCK

tDZSC

ns

ns

,

150

ns

DC

ns
ns

20

ns

150

ns
ns
ns

150

ns

"
"

SO Delay from SOEN

tDZE

SOEN to SO Floating

tHZE

SCK to SO Floating

tHZSC

"

SORO to SO Floating

tHZRO

"

CONDITION

ns

Address Hold Time for WR

"
"

SIEN. SI Setup Time

tDC

50

SIEN. SI Hold Time

tCD

20

PO. Pl Delay

top

RST Pulse Width

tRST

4

CY

"To be specified

532

SYMBOL

ns
ns
300

ns

AC CHARACTERISTICS

}LPD7720
TIMING WAVEFORMS

CLOCK

\~

ClK

READ OPERATION

tRR---

WRITE OPERATION

AO.CS.~

~

WR ___J_tt_AW(

-

~_tWA_t____

OBO-7

DMA OPERATION

OACK

ORO

533

JLPD7720
TIMING WAVEFORMS
(CON'T.)

SERIAL TIMING

tRSC

tSCK

SCK

tDRO
SORa

SOEN - - - , -

-1------1---

~
tDZSC

-------

SO

SI

tCD

PORT OUTPUT

CLK

RST

INT

534

tHZSC

r""~~_

----

-~/I----t---­

"--__

~ltHzRO

-x:=:;~------

J'PD7720
PRODUCT EXAMPLE
USING THE "PD7720

..

~
MICROPHONE
THERMAL
PRESSURE
LIGHT

:

.. : ......... ... :
FREa_

BANDLIMITING
FILTER

SPECTRUM ANALYSIS SYSTEM

AN ANALOG TO
ANALOG DIGITAL
PROCESSI NG SYSTEM
USING A SINGLE SPI

ANALOG
OUT

ANALOG
IN

RECONSTRUCTION
FILTER

sORaf--[)o-I "SfE'i\j

1----.lSI

SO!------...j

SPI

t--r--t-gm;r

mrn

ANALOG
OUT

SPI
SO

1----/

SI

SORa 1 - - - - 1
SOEN

A SIGNAL PROCESSING SYSTEM USING
CASCADED SPls & SERIAL COMMUNICATION.

HOST
CPU

II

MEMORY

B

A SIGNAL PROCESSING
SYSTEM USING SPl(s)
AS A COMPLEX COMPUTER
PERIPHERAL

DRal
DMA
CONTROLLER

•
•

•

•
•
•
DRa(n)

i5AcK (n)
7720DS-12-80-CAT

535

NOTES

536

NEe

NEe Microcomputers, Inc.
2048 BIT STATIC MOS RAM WITH
1/0 PORTS AND TIMER

OESCR IPTION

fLPD8155
p.PD8155-2
fLPD8156
fLPD8156-2

The J.LPDB1 55 and J.LPDB1 56 are J.LPDBOB5A family components having 256 X B Static
RAM, 3 programmable I/O ports and a programmable timer. They directly interface
to the multiplexed J.LPD80B5A bus with no external logic. The J.LPDB155 has an active
low chip enable while the J.LPDB1 56 is active high.

FEATURES.256XB·BitStaticRAM

PIN CONFIGURATION

•

Two Programmable B·Bit I/O Ports

•

One Programmable 6·Bit I/O Port

•

Single Power Supplies: +5 Volt, ±10%

•

Directly interfaces to the J.LPDB085A and J.LPD8085A·2

•

Available in 40 Pin Plastic Packages

PC3
PC4
TIMER IN
RESET
PCs
TIMER OUT

vcc

101M

CE/CE*

AD
WR
ALE
ADO
ADl
AD2
AD3
AD4
ADS
AD6
AD7

IJPD
8155/
8156

Vss

PC2
PCl
PCo
PB7
PB6
PBS
PB4
PB3
PB2
PBl
PBo
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAo

II

*I'PD81S5: CE
I'PD8l56: CE

Rev/2

537

fLPD8155/8156

The pPD8155 and pPD8156 contain 2048 bits of Static RAM organized as 256 X 8.
The 256 word memory location may be selected anywhere within the 64K memory
space by using combinations of the upper 8 bits of address from the pPD8085A as a
chip select.

FUNCTIONAL
DESCRIPTION

The two general purpose 8·bit ports (PA and PB) may be programmed for input or
output either in interrupt or status mode. The single 6·bit port (PC) may be used as
control for PA and PB or general purpose input or output port. The pPD8155 and
pPD8156 are programmed for their system personalities by writing into their
Command/Status Registers (CIS) upon system initialization.
The timer is a single 14·bit down counter which is programmable for 4 modes of oper·
ation; see Timer Section.

VCC (+5VI

BLOCK
DIAGRAM

I
8

~.

-

r--

r--

A

T f---

C

CE

R
A
M

---

---

'--

"C
N

T

R

B

8

l

J

p
C

1---

6

-

'-TIMER IN

P

-

r-

0

RD

r--

'--

0

RESET

8

'--

H

ALE

--

p
A

L

-

TIMER

L

I

TIMER OUT

I

Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to +70°C
Storage Temperature (P~astic Package) . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to. +7 VoltsCD
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
Note:

CD

With Respect ~o Ground.

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
"Ta = 25°C

538

ABSOLUTE MAXIMUM
RATINGS*

P. PD815518156
PIN IDENTIFICATION

DC CHARACTERISTICS

PIN
NO.

SYMBOL

FUNCTION

1.2.5
39.38.37

PC3. PC4. PC5
PC2. PC1. PCO

Port C

Used as control for PA and
PB or as a 6·bit general
purpose port

3

TIMER IN

Timer Clock In

Clock input to the 14·bit
binary down counter

4

RESET

Reset In

From IlPDOO85A system reset
to set PA. PB. PC to the input
mode

6

TIMER OUT

Timer Counter Output

The output of the timer
function

7

10/M

I/O or Memory
Indicator

Selects whether operation to
and from the chip is directed
to the internal R AM or to
110 ports

8

CE/CE

Chip Enable

Chip Enable Input. Active
low for II PD8155 and
active high for IlPD8156

NAME

9

RD

Read Strobe

Causes Data Read

10

WR

Write Strobe

Causes Data Write

11

ALE

Address low Enable

latches low order address
in when valid

12·19

ADO - AD7

Low Address/Data

3-State address/data bus
to interface directly to
Il PD8085A

Ground

Ground Reference

20

VSS

21-28

PAO - PA7

Port A

General Purpose I/O Port

29-36

PBO - PB7

Port B

General Purpose 110 Port

40

VCC

5 Volt Input

Power Supply

Ta

= o°c to +70°C; VCC = 5V ±

10%
LIMITS

PARAMETER

SYMBOL MIN

Input Low Voltage

VIL

-0.5
2.0

Input High Voltage

VIH

Output Low Voltage

VOL

Output High Voltage

VOH

Input Leakage

IlL

Output Leakage Current

TYf MAX
0.8

UNIT

TEST
CONDITIONS

V

VCC+
-1I
'
: :
H, I

,

::

'

PACKAGE OUTLINE
I'PD8155C
I'PD8156C

M

J

Plastic
ITEM

MILLIMETERS

L

51.5 MAX
1.62
2.54 t 0.1
0.5tO.1
48.26
1.2MIN
2.54 MIN
0.5 MIN
5.22 MAX'
5.72 MAX
15.24
13.2

M

+0.1
0.25 _ 0.05

A
8
C
0

E
F
G
H
I
J
K

INCHES
2.028 MAX
0.064
0.10t 0.004
0.019 ± 0.004
1.9
0.Q47 MIN
0.10 MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.520
+ 0.004
0.010 _ 0.002

8155/56DS-REV 2-10·~!O-CAT

544

.NEe

NEe Microcomputers, Inc.

IJ. PB8212

EIGHT-BIT INPUT IOUTPUT PORT

DESCRIPTION

The J.LPB8212 input/output port consists of an 8-bit latch with three-state output
buffers along with control and device selection logic. Also included is a service request
flip-flop for the control and generation of interrupts to the microprocessor.
The device is multimode in nature and can be used to implement latches, gated buffers
or multiplexers. Thus, all of the principa1 peripheral and input/output functions of a
microcomputer system can be implemented with this device.

FEATURES

• Fully Parallel8-Bit Data Register and Buffer
•

PIN CONFIGURATION

Service Request Flip-Flop for Interrupt Generatlon

•

Low Input Load Current - 0.25 mA Max.

•

Three State Outputs

•

Outputs Sink 15 mA

•

3.65V Output High Voltage for Direct Interface to 8080A Processor

•

Asynchronous Register Clear

•

Replaces Buffers, Latches and Multiplexers in Microcomputer Systems

•

Reduces System Package Count

•

Available in 24-pin Plastic and Cerdip Packages

VCC

0s1
MD

2

23

iNT
PIN NAMES

011

3

22

DI8

001

4

21

D08

DI, -.DI8

Data In

01 2

5

20

01 7

DO, - D08

Data Out

D02

6

19

007

DS1. DS2

Device Select

18

01 6

MD

Mode
Strobe

DI3
D03

8

DI4

9

J.LPB
8212

D06

STB

DI5

INT

Interrupt (Active Low)

D04

005

CLR

Clear (Active Low)

STB

ct:R

GND

DS2

17

II

Rev/1

545

,",PB8212
BLOCK DIAGRAM

STB MO IDS, . OS2)

,
,
, ,

0

0
0

0

0

Three-State

0
0
0

Three-State

Data Latch

,
,
,

, ,
, ,

0

0
0

,

0

OATAQUT
EQUALS

Notes:

Data Latch

Data Latch
Data In

Data In
Data In

CLR

0

,
,
,

0

,
,

IDS, • OS2) STB SR~ 'NT

,

0

0

0

~
0

,

,

0

(j)

(j)

, ,
"-- ,
0

0

, ,

,

0

0

"'"

0

0

0

0

CD

CLR resets data !atch sets SA flip-flop. (No effect on output buffer)

CZl

Internal SR flip-flop

0

@ Previous data remains

Operating Temperature .... .
Storage Temperature ...... .
All Output or Supply Voltages.
All Input Voltages.
Output Currents . . . . . . . . . .

o°C to +70°C
-65°C to +150°C
. -0.5 to +7 Volts
-1.0 to +5.5 Volts
. . . . . . . . . 125mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

546

ABSOLUTE MAXIMUM
RATINGS*

p.~PB8212
DC CHARACTERISTICS

T,-0·Cto70·C;VCC-+5V±5%
PARAMETER

LIMITS

SYMBOL

UNIT TEST CONDITIONS

TYP

MAX

-0.14

-0.26

mA

VF -0.45V

-0.25

-0.75

mA

VF - 0.45V

-0.26

-1.0

mA

VF - 0.45V

IR

10

~A

VR - 5.25V

Input Leakage Current MO
Input

IR

30

~A

VR - 5.25V

Input Leakage Current Ern1 '
Input

IR

40

~A

VR - 5.25V

-1.3

V

Ic--5mA

I"put load Current ACK. 052.
CR. 011 - Olslnputs
Input Load CUrrent MO Input

IF
IF

Input Load Current 'D"S1 Input

IF

Input Leakage Current ACK.

MIN

OS, CR, 011 - DiS Inputs

Input Forward Voltage Clamp
Input "Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage
Short Circuit Output CUrrent
Output Leakage CUrrent High
Impedance State
Power SupplV Current

CAPACITANCE

C ---- --- - - __ _
~~

1,:::="W:::::j--'H~

------ .../
STB o. 55,.052

15V/

\

......
,,_V_ _ _ __

- - - - - f--'W'::1
------- ------

_____ _

J\;':-

"vi

---~

I

k_v_

t

f--'o-j

'-iGl

f-'\lr---------~ II

_______ J'\

•

----"V\"w-;,'V

VOH

VOL

----I--'c~"V

--------------\,r---15V/,\

---.../1--I-----

!SET

L"0:1

'-._---

-----~

I

---I

tH

'- ___ _

---t

"V\'----_ _
___ _

~v--_ _ _ _ _ _ _ ....J

--~~tpw

CD

II

Alternative Test Load

549

P. PB8212
OUTPUT CURRENT VS.

INPUT CURRENT VS. INPUT VOL rAGE

100

VCC=I~50V

OUTPUT "LOW" VOL rAGE

r---.,.----,---,----,
VCC=+50V

50

1a =:Jc
-; I~
100

Ta = 7S'C

~

"

150

T, " DOC

200
25 0

1
0
+1
iNPUT VOLTAGE' IV)

+2

.,

00'-_-'---l._ _--',_ _ _L-_---'
OUTPUT' lOW" VOL TAGE (vi

DATA TO OUTPUT DELAY

vs LOAD CAPACITANCE
50,--,--.,.---,--,---,----,
VCC=+50V

fa = +2S'C

'O~-+--~-4--~--+-~

,o~-+---+---~--t--+-~

2a

<10

50

OUTPUT "HIGH' VOL TAGE IV)

°OL--5~O---',00~-15LO-~2ooL--2~50-~joo
LOAD CAPACITANCE IpFI

DATA TO OUTPUT OEL4Y

22 r-_~_V,-,S::..;.:TE:::M,-PE::R=A:;-TU:::R:..:E,--~_~
WRITE ENABLE TO OUTPUT DELAY

Vee = +5.0V

20e---+--+---+--+--~

,or-_~~V~S~TETM=P~ER~A::TTUR~E~-r_--'

1B~-~--~-~~~=~~-~
__ t .. +

'5~C~-+--+---+--+--~

Vee = +5.0V

OS,

4L-_-L__L-_-L__
~

25

+15

+SO

TEMPERATURE lOG)

550

L-_~

+75

+100

~2~5--L---'~25--'50L---'~'5--.-J,oo
TEMPERATURE 1° e)

TYPICAL CHARACTERISTICS

J.L PB8212
PACKAGE OUTLINE
J.lPB8212C

I--------A

,
--' '-- ---< C ' - -

E------~

D

(PLASTIC)
ITEM

A

D

G

MILLIMETERS

INCHES

33 MAX

1.3 MAX

2.53

0.1

2.54

0.1

0.5 ± 0.1

0.02 ± 0.004

27.94

1.1

1.5

0.059

2.54 MIN

0.1 MIN

0.5 MIN

0.02 MIN

5.22 MAX

0.205 MAX

5.72 MAX

0.225 MAX

15.24

0.6

13.2

0.52
+0.10

+0.004

M

0.25

ITEM

MILLIMETERS

INCHES

A

335 MAX.

1.32 MAX.

-0.05

0.01

-0.0019

J.lPB8212D'

(CERDIP)

D

2.78

0.11

2.54

0.1

0.46

0.018

27.94

1.1

1.5

0.059

G

2.54 MIN.

0.1 MIN.

H

0.5 MIN.

0.019 MIN.

4.58 MAX.

0.181 MAX.

5.08 MAX.

0.2 MAX.

15.24

0.6

13.5

0.53

O.25~:~~

+0.004
0.01_ 0 .002

K

M

II
8212DS-12-80-CAT

551

NOTES

552

NEC

NEe Microcomputers, Inc.

fL PB8214

PRIORITY INTERRUPT CONTROLLER

DESCRIPTION

The jlPB8214 is an eight-level priority interrupt controller. Designed to simplify
interrupt driven microcomputer systems, the jlPB8214 requires a single +5V power
supply and is packaged in a 24 pin plastic Dual-in-line package.
The jlPB8214 accepts up to eight interrupts, determines which has the highest priority
and then compares that priority with a software created current status register. If the
incoming requires is of a higher priority than the interrupt currently being serviced, an
interrupt request to the processor is generated. Vector information that identifies tl"1
interrupting device is also generated.
Q

The interrupt structure of the microcomputer system can be expanded beyond eight
interrupt levels by cascading jlPB8214s. The jlPB8214's interrupt and vector information outputs are open collector and control signals are provided to simplify expansion
of the interrupt structure.

F EATU R ES

PIN CONFIGURATION

•

Eight Priority Levels

•

Current Status Register and Priority Comparator

•

Easily Expanded Interrupt Structure

•

Single +5 Volt Supply

B(j

vcc

B,

ECS

B2
SGS

ClK

22

FG

4

21

R6

5

20

R5

19

R4

18

R3

6

8214

INTE

AD
Ai
IS
GND

j..tPB

PIN NAMES
Inputs

RO

R7

Request Levels IR7 Highest PnorHyl

6 0 , B2

Current Status

SGS

Status Group Select

Ees

Enable Current Status

INTE

Interrupt Enable

eLK

Clock liNT F·F)

ELR

Enable Level Read
Enable ThIs Level Group

8

17

R2

ETLG

9

16

R,

Outputs

10

AO--A2

Request Levels

15

RO

INT

Interrupt (Act. Low) ~Collector

14

ENlG

ENLG

Enable Next Level Group

13

ETlG

12

II

JOpen

553

'" PB8214
BLOCK DIAGRAM

ElR l l i ) - - - - - - - - - - - - - - - - - - - - Q
ETlG 13~----------------_1~__i

(OPEN COLLECTOR)

A>B

Ie
pRIORITY

COMPARATOR

iNTERRUPT
FLIP-FLOP

INTERRUPT

DISABLE
FLIP·FLOP

1C

INTE

elK

G)r-------------------~
6}--------------------------------------~

Operating Temperature ..... .
Storage Temperature
All Output and Supply Voltages
All Input Voltages
Output Currents

. . . 0° C to + 70° C
-65°C to +125°C
. -0.5 to +7 Volts
-1.0 to +5.5 Volts
. . . . . . . 100mA

ABSOLUTE MAXIMUM
RATINGS*

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other cond,tions above those Indicated in the operational sections of this specification is not
Implied. Exposure to "absolute maximum rating conditions for extended periods may affect device
reliability.

554

P. PB8214
DC CHARACTE RISTICS

Ta = oOe to +7o o e, vee = 5V ± 5%
PARAMETER

SYMBOL

Input Clamp Voltage~ (all inputs)

.15
.. 08

IA

all other inputs
Input LOW Voltage: all inputs

Short Circuit Output Current: ENLG output

VIL
VIH
ICC
VOL
VOH
lOS

Output Leakage Current: INT and AO A2

ICEX

Input HIGH Voltage: all inputs
Power Supply Current
Output LOW Voltage: all outputs
Output HIGH Voltage: ENLG output

UNIT

MAX.

V
mA
mA

80
40

"A
"A
V
V

VCC 5.0V
VCC 5.0V

mA
V

10l 10mA

55

V
mA

'OH-' lmA
VOS OV, VCC 5.0V

100

"A

VCEX- 5.25V..........-....

0.8
2.0
90
2.4
. 20

.3
3.0
35

TEST CONDITIONS

1.0
·05
0.25

130
.45

IC-- 5mA

VF 0.45V
VA-5.25V

Q)

Ta=25°e
PARAMETER

AC CHARACTER ISTICS

LIMITS
TYP.(j)

Vc
IF

Input Forward Current: ETLG input
all other inputs
Input Reverse Current: ETLG input

CAPACITANCE@

MIN.

SYMBOL

MIN.

LIMITS
TYp.CD

MAX.

UNIT

TEST CONDITIONS

Input Capacitance

CIN

5

10

pF

VBIAS=2.5V

Output Capacitance

COUT

7

12

pF

VCC=5V
f=lmHz

MIN.

LIMITS
TYP.(j)

Ta = oOe to +7o o e, Vee = +5V ± 5%
PARAMETER

eLK Cycle Time

SYMBOL

MAX.

UNIT

TEST CONDITIONS

'CY
tpw

80

50

ns

Input pulse

elK, ECS, tNT PulsE' Width

25

15

os

amplitude: 2.5

lNTE Setup Time to elK

ttss

16

12

ns

INTE Hold Time after GlK

ttSH

20

10

ns

ETlG Setup Time to GlK

tETCS®

25

12

ns

Input rISe and fall

ETlG Hold Time After GlK

tETCH®

20

10

ns

times: 5 ns between

EGS Setup Time to GlK

tECCS®

80

50

ns

1 and 2 Volts

EGS Hold Time After GlK

tECCH (§)

0

EGS Setup Time to ClK

tECRS (hi

110

ECS Hold Time After GlK

tECRH@

0

EGS Setup Time to GlK

tECSS®

75

EGS Hold Time After GlK

tECSH®

0

SGS and BO-82 Setup Time to GlK

tDCS®

70

SGS and BO-82 Hold Time After elK

tDCH®

0

RO-R7 Setup Time to ClK

tRCS@

90

RO-R) Hold Time After elK

tRCH@

a

INr Setup Time to GlK

lICS

55

ns
70

ns

70

ns

Output loading of

ns

50
55

Speed measurements

ns

taken at the ·1.5 Volts

ns

levels.

ns

35
15

ns

25

ns

tCI

RO-R7 Setup Time to 'NT

tRIS@

10

0

RO-R7 Hold Time After INT

tRIH@

35

20

RO-R7 to AO-A2 Propagation Delay

tRA

80

100

ns

ElR to AO-A2 Propagation Delay

tELA

40

55

ns

EGS to AO-A2 Propagation Delay

tECA

100

120

ns

ETlG to AO-A2 Propagation Delay

tETA

35

70

ns

SGS and BO 82 Setup Time to ECS

tDECS@

15

SGS and BO-82 Hold Time After ECS

tDECH@

15

'"Ffo-RJ

tAEN

ns
ns

10
45

II

ns

10

ns
70

os

ElTG to ENlG Propagation Delay

tETEN

20

25

ns

EGS to ENlG Propagation Delay

tECAN

85

)0

ns

ECS to ENLG Propagation Delay

tECSN

35

55

ns

Notes:

15 mA and 30 pF.

ns

ClK to 'NT Propagation Delay

to ENlG Propagation Delay

\jc!t~

Typical values are tor T a=25 °C, VCC=5.0V
SO-B2' SGS, ClK, RO-R4 grounded, all other inputs and all outputs
open.
This parameter is periodically sampled and not 100% tested.
Required for proper operation if INTE is enabled during next clock pulse.
These times are not required for proper operation but for desired
change in interrupt flip-flop.
Required for new request or status to be properly loaded.

555

p.PB8214
General
The J..lPB8214 is an lSI device designed to simplify the circuitry required to
implement an interrupt driven microcomputer system. Up to eight interrupting
devices can be connected to a J..lPB8214, which will assign priority to incoming
interruPt requests and accept the highest. It will also compare the priority of the
highest incoming request with the priority of the interrupt being serviced. If the
serviced interrupt has a higher priority, the incoming request will not be accepted.

FUI\ICTIONAL
DESCRIPTION

A system with more than eight interrupting devices can be implemented by inter·
connecting additional IlPB8214s. In order to facilitate this expansion, control
signals are provided for cascading the controllers so that there is a priority estab·
lished among the controllers. In addition, the interrupt and vector information
outputs are open collector.
Priority Encoder and Request latch
The priority encoder portion of the J..lPB8214 accepts up to eight active low
interrupt requests (RO-R 7 ). The circuit assigns priority to the incoming requests,
with R7 having the highest priority and RO the lowest. If two or more requests.
occur simultaneously, the J..lPB8214 accepts the one having the highest priority.
Once an incoming interrupt request is accepted, it is stored by the request latch and
a three·bit code is output. As shown in the following table, the outputs, (AO-A 2 )
are the complement of the request level (modulo 8) and directly correspond to the
bit pattern required to generate the one byte RESTART (RST) instructions
recognized by an 8080A. Simultaneously with the Ao-A2 outputs, a system
interrupt request (INT) is output by the J..lPB8214. It should be noted that incoming
interrupt requests that are not accepted are not latched and must remain as an
input to the IlPB8214 in order to be serviced.

Interrupt Control Circuitry
The J..lPB8214 contains two flip-flops and several gates which determine whether an
accepted interrupt request to the J..lPB8214 will generate a system interrupt to the
8080A. A condition gate drives the 0 input of the interrupt flip-flop whenever an
interrupt request has been completely accepted. This requires that: the ETlG
(Enable This level Group) and INTE (Interrupt Enable) inputs to the J..lPB8214 are
high; the ElR input is low; the incoming request must be of a higher priority than
the contents of the current status register; and the J..lPB8214 must have been enabled
to accept interrupt.requests by the clearing of the interrupt disable flip-flop.
Once the condition gate drives the 0 input of the interrupt flip-flop high, a system
interrupt (lNT) to the 8080A is generated on the next rising edge of the ClK input
to the J..lPB8214. This ClK input is typically connected to the --t--,

BLOCK DIAGRAMS

01 0
DBa

" - - - 0 DBa

0°0
01,0---+--1>-+--,

01,
DB,

DB,

OO,o---+---~t--+~

DO,

01 2o---t--C~-t-,

01 2

.....- - 0 OB 2

0°2

o 13o---t--C~--i-.,
OB 3

Cs

562

RESULT

0

DI4DB

DB "'00

0

~---+~----ocs

OlEN

cs

0

, 0
,
---,-- r-;-

01 3
0°3

DIE N 0 - -.....>--------'

OlEN

)Hi9h Impedance

fLP 88216/8226
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature ..... .
Storage Temperature (Cerdip) ..
(Plastic) ..
All Output and Supply Voltages
All Input Voltages ..
Output Currents

.... o°c to 70°C
-65°C to +150°C
-65°C to +125°C
· . -0.5 to +7 Volts
· -1.3 to +5.5 Volts
· . . . . . . . 125 mA

COMMENT: Stress above those listed under "Absolute Maximum Ratings" l7lay cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

'Ta

DC CHARACTERISTICS

Ta

=

25°C

=

O'c to +70"(; Vee - +5V' 5";,

SYMBOL

PARAMETER

LIMITS
MIN

TYP

CD

MAX

UNIT

TEST. CONDITIONS

IF 1

~-0.5

mA

VF " 0.45

Input Load Cum~nt All
Other Inputs

IF2

~-0.25·

mA

VF - 0.45

Input Leakage

rent

IR 1

20

~A

VR" 5.25V

Input Leakage CUT lent

IR2

10

~A

VR - 5.25V

Vc

-1.0

V

Ie --5 mA

Input Load CUI lent

llftN. CS

OlEN.

CUI

CS

01 Inputs
Input Forwdld Voltage

Clamp
Input "low" Voltage

VIL

Input "High" Voltdge

VIH

Output leakage CUrient DO
(3·State)
DB

In
10

20
100

~A

ICC
ICC

130
120.

mA
mA

Power Supply Current

8216
8226

V
V

VOl1

Output "low . Voltage

0.48

V

Vo

=

0.45/5.25V

DO Outputs 10L 15 rnA
DB Outputs tOl = 25 rnA

8216

VOL2

O~ 7

V

DB Outputs tOl - 55 rnA

8226

0.7

V

DB Outputs IOH - 50 rnA

Output "High" Voltage

VOL2
VOH1

3.6~

V

DO Outputs 10H

1 mA

Output "High" Voltage

VOH2

2.4

V

DB Outputs 10H

lOrnA

Output Short CirCUit
Current

Ins

mA
mA

DO Outputs Vo OV
DB Outputs Vec 5.0V

Output "Low . Voltage

Note

CAPACITANCE

0.95
2.0

CD

lOS

15
-30

TYPical values are for Ta~: 25"C, Vec

=

65
-120

5.0V.

CD
PARAMETER

SYMBOL

Input Capacitance
Output Capacitance

COUTl

Output Capacitance

COUT2

Notes:

CIN

LIMITS
MIN

TYP

MAX
8
10Q)
18Q)

UNIT

n
IiII

TEST
CONDITIONS

pF

VBIAS

pF

VCC = 5V
Ta ~ 25°C

pF

~

2.5V

f = 1 MHz



@

8226

tE

54

ns

35,

ns

~

@

Output Disable Time
Notes:

CD

tD

Typical values are for Ta

= 2Soc, Vee""

5.0V

~ DO Outputs, CL" 30 pF, Rl "300/10 KQ, R2" 600/1 KQ,

DB Outputs, CL" 300 pF, Rl "90/10 K!1, R2" 180/1 KQ,
~ DO Outputs, CL " 5 pF, R 1 " 300/10 KQ, R2 "600/1 KQ,

DB Outputs, CL" 5 pF, Rl "90/10 KQ, R2" 180/1 KQ,

®.

Input pulse amplitude: 2.5V

Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 rnA and 10 pF.

TEST CIRCUIT

Speed measurements are made at 1.5 volt levels.

INPUTS

______

~~~1,_5V

TIMING WAVEFORMS

____________________

rtFD
OUTPUT
ENABLE

1.5V

1.5V

OUTPUTS

PACKAGE OUTLINE
J,lPB8216C/D
J,lPB8226C/D

Cerdip
INCHES

o 10MJN

00098

'---"-Plastic

-

A

"'mfvWiJLi -A
I,

""B~

,

-J_
D

--iFf---- ----.:

UJG

c -

'"'
'"

l

0_15 o

J-

[-'c----

r----+--

.00M"
';;M"

'"

;~

"'"

-

8261/8226DS-REV2-12-80-CAT

564

NEe
NEe Microcomputers, Inc.

,.,. PB8224

CLOCK GENERATOR AND DRIVER FOR
8080A PROCESSORS

D ESC R I PT ION

The pPB8224 is a single chip clock generator and driver for 8080A processors.
The clock frequency is determined by a user specified crystal and is capable of
meeting the timing requirements of the entire 8080A family of processors. MOS
and TTL level clock outputs are generated.
Additional logic circuitry of the !1I'B8224 provides signals for power-up reset, an
advance status strobe and properly synchronizes the ready signal to the processor.
This greatly reduces the number of chips needed for 8080A systems.
The !1I'B8224 is fabricated using NEe's Schottky bipolar process.

FE A TU R ES

• Crystal Controlled Clocks
•

PIN CONFIGURATION

Oscillator Output for External Timing

•

MOS Level Clocks for 8080A Processor

•

TTL Level Clock for DMA Activities

•

Power-up Reset for 8080A Processor

•

Ready Synchronization

•

Advanced Status Strobe

•

Reduces System Package Count

•

Available in 16-pin Cerdip and Plastic Packages

RESET

RESIN

RESiN

XTAL 1

RDYIN

XTAL 2

READY

PIN NAMES

Vee

TANK

OSC

Reset Output

ROY IN

Ready Input

READY
SYNC
$TSTB
1,)1

01
STSTB

GND

02

VDD

Reset Input

RESET

Ready Output
Sync Input

Status STB
Output

Processor

"2
XTAL 1

Clocks

XTAl2

ConnectIons

TANK

Overtone

Crystal

Used With

II

Crystal
OSCillator

OSC

Output

1>2 eLK
02 (TTL)

Vec

Rev/l

(TTL Level)

+5V

VDD

+12V

GND

OV

565

J.L PB8224
FUNCTIONAL DESCR IPTION

Clock Generator
The clock generator circuitry consists of a crystal controlled oscillator and a
divide-by-nine counter. The crystal frequency is a function of the SOSOA
processor speed and is basically nine times the processor frequency, i.e.:
Crystal frequency

=

~
tCY

where tCY is the SOSOA processor clock period.
A series resonant fundamental mode crystal is normally used and is connected
across input pins XTAL 1 and XTAL2. If an overtone mode crystal is used, an
additional LC network, AC coupled to ground, must be connected to the
TANK input of the j.1PBS224 as shown in the followir:g figure.

r------,
I

LC

( ....1_\2

\2rrFj

I FOR OVERTONE CRYSl ALS ONLY
l.

I

I

I

I

01-,

I

r_±_,3-10PF
I (ONLY NEEDED

if

I
L_

I

I
~

_

..I

ABOVE 10MHzI

I

_______

OSC

r

..t~'~3~~~~

12

I-

The formula for the LC network is:
LC

=(_1)2
27TF

where F is the desired frequency of oscillation.
The output of the oscillator is input to the divide-by-nine counter. It is also
buffered and brought out on the OSC pin, allowing this stable, crystal controlled
source to be used for derivation of other system timing signals. The divide-bynine counter generates the two non-overlapping processor clocks, c;D1 and ¢2,
which are buffered and at MOS levels, a TTL level c;D2 and internal timing signals.
The c;Dl and c;D2 high level outputs are generated in a 2-5-2 digital pattern,with c;Dl
being high for two oscillator periods, 

-10

Vo

-60

(All Low Voltage Outputs Only)
Power Supply Current

'CC

115

Power Supply Current

'00

15

Note'

ill

- OV

VCC = 5,OV

mA
mA

Caution. 411 and <1>2 outPut dnvers do not have short circuit proteCtion

Ta "" 25°C; f '" 1 MHz; VCC '" 5V; VDD '" 12V; VBIAS '" 2.5V

CAPACITANCECD

PARAMETER

TEST CONDITIONS

Input Capacitance
Note:

G)

This parameter is periodically sampled and not 100% tested.

567

~PB8224
Ta '" O°C to +70c C;

vee

PARAMETER

=- +5V ±5%;

Voo '"

LIMITS (i
MIN

t~t

2tCY

1>2 Pulse Width

t¢2

5tCY

$1 10 Q2 Delay

tOt

0

02 to 1>1 Delay

t02

2tg v -14 ns

9

MAX

-35ns
ns
C L =- 20 pF to 50 pF

2tCY

2tCY

9

9
1>1 and 1)2 Rise Time

20

1>1 and 92 Fall Time

tF

10112

92 (TTL) Delay

+2005

20

tR

1>2

to

TEST CONDITIONS

-20ns

9

t03

UNIT

TYP

¢, Pulse Width

91 to 92 Delay

AC CHARACTERISTICS

+12V ±5%

SYMBOL

-5

+15

ns

92 TTL, CL - 30 pF

R, =- 300n

R2
,'1210 ')TST8 D9\ay

STSTB Pulse Width

ROY I N Setup Time

tDSS

Gtey

tPw

tCY

9

9"""

tORS

RDYIN Hold Time

After STSi3

-9-

READY or RESET

tOR

4tCY

'>2

GOOH

STSTB. CL '" 15 pF
A, " 2K

4tCY

--g-

ns

,

A2=4K

4tCY

tORH

to

9

=-

ns

--15ns

50 ns -

10 STSTB

StC'1'

-300s

9

Delay

Ready and Reset
ns

-25ns

CL==10pF
R, '" 2K
R2 = 4K

Crystal Frequency

MH,

...2....

fCLK

ICY

Maximum Oscillating

27

fMAX

MH,

Frequency

Note:

CD

ICY represents the processor clock period

tri

R,

vcc

INPUT

J

CL

GND

R2

~ GND

TEST CIRCUIT

TIMING WAVEFORMS

'R

-f'

'7 fTTLl _ _ _ _ _ _ _ _ _ _

SYNC
(FROM PROCESSORI

tDSS+-----~-

1----rORH----j
RDY1N OR

AESi'N

READY

----------'1'-- ------ --- -- - - --- --- --- - --.

RESET

568

Voltage Measurement Points: 1>1.1>2 Logic "0" ~1.0V. Logic "1"
All other signals measured at 1.5V.

~

a.ov.

J.L PB8224
CRYSTAL REQUIREMENTS

0.005% at 0° C-70° C
Series (Fundamental) CD
20-35 pF
75-20 ohms
4mW

Tolerance . . . . .
Resonance
Load Capacitance
Equ ivalent Resistance.
Power Dissipation (Min)
Note:

PACKAGE OUTLINE
[lPB8224C

CD

With tank circuit use 3rd overtone mode.

K

_----A

A '\
L

M

,

,

(PLASTIC)
ITEM

MILLIMETERS

INCHES

A

194 MAX

076 MAX

8

081

003

C

254

010

D

05

002

E

1778

010

F

13

0051

G

2 54

H

05 MIN

I

4

x

016 fo,1AX

J

455 MAX

018 r-."AX

as

~JI

N

~~A

010 MIN
002 ',liN

-~~

K

762

030

L

64

025

"

025

__

-010

001
005

J,tPB8224D

----- K-

II

'I
(CERDIP)
ITEM

MILLIMETERS
199 MAX

INCHES
0784 MAX

106

00ol2

254

010

046 . 010

0018 . 0004

1778

070

15

0059

2.54 MIN

010 MIN

05MIN

0.019 MIN

458 MAX

0.181 MAX

5.08 MAX

0.20 MAX

7.62

0.30
0.27

6.8
+ 0 10
M

0.25. 0.05

0.0098 •

~:~~:

8224DS-12-80-CAT

569

NOTES

570

fttIEC

NEe Microcomputers, Inc.

Jl,PB8228

J.I PB8238
8080A SYSTEM CONTROLLER
AND BUS DRIVER
OESCR IPTION

The pPB8228/8238 is a single chip cOntroller and bus driver for 8080A based
systems. All the required interface signals rrecessary to connect RAM, ROM and
I/O components to a pPD8080A are generated.
The pPB8228/8238 provides a bi·directional three·state bus driver for high TTL
fan-out and isolation of the processor data bus from the system data bus for
increased noise immunity.
The system controller portion of the pPB8228/8238 consists of a status latch for
definition of processor machine cycles and a gating array to decode this information
for direct interface to system components. The controller can enable gating of a
multi·byte interrupt onto the data bus or can automatically insert a RESTART 7 Onto
the data bus without any additional components.
Two devices are provided:. the pPB8228 for small systems without tight write timing
constraints and the pPB8238 for larger systems.

F EATU R ES

• System Controller for 8080A Systems
•

Bi-Directional Data Bus for Processor Isolation

•

3.60V Output High Voltage for Direct Interface to 8080A Processor

•• Three State Outputs on System Data Bus
•

Enables Use of Multi-Byte Interrupt Instructions

•

Generates RST 7 Interrupt Instruction

• pPB8228 for Small Memory Systems
• pPB8238 for Large Memory Systems
•

Reduces System Package Count

• Schottky Bipolar Technology

PIN CONFIGURATION

Vee

STSTB
HLDA

I/OW

WR

PIN NAMES

MEMW

DBIN
DB4

I/OR

07 - Do
DB7 DB

MEMR

liaR

D4

MEMW

DS

DBIN
I 'ITA

Interrupt Al:.knowledge

HLDA

HLDA (From Processor)

INTA

D7
DB3

DBS

D3

D5

DB2

DB5

D2

Si-~----

VOLTAGE MEASUREMENT POINTS

all.5V

574

- - - -- - ---

0 0.0 7 (wh8fl outputsl Lo~'c "0' "O.8V, Log'c "'" - 3.0V. All other s'gnals measurotd

Jl. P 88228/8238
STATUS WORD CHART

DO

INTA

02

STACK

CD000®®0®®@
0000000101

06
07

MEMR

1
1
0
1
0
000
1
1
o 0
0
0
0
o 0 0 0 0
1
0
000
001 0
0
0
1
1
a 1 a

24

MEMR

o

26

MEMW

a

25
27
23

I/OR

1
1
1

INP

I

I/OW
INTA

PIN\.
NO\

\

o

1

0
1
1
1
1

1
0
1
1
1

1
0
0
0
0
I

0
0
0
1
0
0

a

a

1
1

1
1
1

a
1
1

a
1

1
1
1
000

o

1

o

0

1

0

a
o

0
1

1
1
1
1
0

1
1
1
1
0

o

IlP0 8080A
OUTPUT

a
o

IlPB8228/8238
OUTPUT

SIGNAL STATUS

IlP88228/8238 CONTROL SIGNALS

II
575

J.L PB8228/8238

PACKAGE OUTLINE

IlPB8228C
IlPB8238C

(Plastic)
ITEM

MI LLiMETERS

INCHES

A

38.0 MAX.

1.496 MAX.

2.49

C

2.54

D

05

E

33.02

F

1.5

0.059

G

2.54 MIN.

0.10MIN.

H

0.5 MIN.

0.02 MIN.

I

5.22 MAX.

0.205 MAX.

J

5.72 MAX.

0.225 MAX.

t

0.10
0.1

0.02 ± 0.004
1.3

K

15.24

0.6

L

13.2

0.52

M

I--------A--~~-

0.098

B

025 + 0.10
. - 0.05

+ 0.004
0.01 _ 0.002

IlPB8228D
IlPB8238D

----.j

(Ceramic!
ITEM
A
B
C
D
E
F

G
H
I
J
K
L
M

576

MILLIMETERS
36.2 MAX.
1.59 MAX.
2.54
0.46 ± 0.05
33.02
1.02
3.2 MIN.
1.0
3.5
4.5
15.24
14.93
0.25 ± 0.05

INCHES
1.43
0.06
0.1
0.02 ± 0.004
1.3
0.04
0.13
0.04
0.14
0.18
0.6
0.59
0.01 ± 0.002

8228/8238DS-12-80-CA T

NEe

NEe Microcomputers, Inc.

f'PD8243

INPUT/OUTPUT EXPANDER FOR
fLP 08048/8748/8035
DEseR IPTION

The IlPD8243 input/output expander is directly compatible with the IlPD8048 family
of single-chip microcomputers. Using NMOS technology the IlPD8243 provides high
drive capabilities while requiring only a single +5V supply voltage.
The IlPD8243 interfaces to the IlPD8048 family through a 4-bit I/O port and offers
four 4-bit bi-directional static I/O ports. The ease of expansion allows for multiple
IlPD8243's to be added using the bus port.
The bi-directional I/O ports of the IlPD8243 act as an extension of the I/O capabilities
of the IlPD8048 microcomputer family. They are accessible with their own ANL, MOV,
and OR L instructions.

FEATURES

• Four 4-8it I/O Ports
•
•
•
•
•
•
•
•

Fu.lly Compatible with IlPD8048 Microcomputer Family
High Output Drive
NMOS Technology
Single +5V Supply
Direct Extension of Resident IlPD8048 I/O Ports
Logical AND and OR Directly to Ports
Compatible with Industry Standard 8243
Available in a 24-Pin Plastic Package

24

Vee

P40

2

23

P51

P41

3

22

P52

P42

4

21

P53

P50

P43

CS

6

PROG

I-IPD
8243

20

P60

19

P61

18

P62

P23

8

17

P63

P22

9

16

P73

P21

15

P20

14

P72
P71

13

P70

GND

12

II
577

j.LPD8243
General Operation
The I/O capabilities of the MPD8048/8748/8035 can be enhanced in four 4-bit I/O port
increments using one or more MPD8243's_ These additional I/O lines are addressed as
ports 4-7_ The following lists the operations which can be performed on ports 4-7.
• logical AND Accumulator to Port.
• logical OR Accumulator to Port.
• Transfer Port to Accumulator.
• Transfer Accumulator to Port.
Port 2 (P20-P23) forms the 4-bit bus through which the MPD8243 communicates with
the host processor. The PROG output from the MPD8048/8748/8035 provides the
necessary timing to the MPD8243. There are two 4-bit nibbles involved in each data
transfer. The first nibble contains the op-code and port address followed by the second
nibble containing the 4-bit data_ Multiple MPD8243's can be used for additional I/O.
The output lines from the MPD8048/8748/8035 can be used to form the chip selects
for the additional MPD8243's.
Power On Initialization
Applying power to the MPD8243 sets ports 4-7 to the tri-state mode and port 2 to the
input mode. The state of the PROG pin at power on may be either h19h or low. The
PROG pin must make a high-to-Iow transition in order to exit from the power on
mode. The power on sequence is initiated any time Vce drops below lV_ The table
below shows how the 4-bit nibbles on Port 2 correspond to the MPD8243 operations.
Op-Code

Port Address
P21
0

P20

Address Code

P23
0

0

Port 4

P22
0

Instruction Code

0
1

1
0

Port 5
Port 6

0

1

1

0

Write
ORlD

1

1

Port 7

1

1

ANlD

Read

For example an 0010 appearing on P20-P23, respectively, would
result in a Write to Port 4.
Read Mode
There is one Read mode in the MPD8243. A falling edge on the PROG pin latches the
op-code and port address from input Port 2. The port address and Read operation are
then decoded causing the appropriate outpU(S to be tri-stated and the input buffers
switched on. The rising edge of PROG terminates the Read operation_ The Port
(4,5,6, or 7) that was selected by the Port address (P21-P20) is returned to the tri-state
mode, and Port 2 is switched to the input' mode.
Generally, in the read mode, a port will be an input and in the write mode it will be an
output. If during program operation, the MPD8243's modes are changed, the first read
pulse immediately following a write should be ignored_ The subsequent read signals are
valid. Reading a port will then force that port to a high impedance state.
Write Modes
There are three write modes in the MPD8243. The MOVD Pp,A instruction from the
MPD8048/8748/8035 writes the new data directly to the specified port (4,5,6, or 7).
The old data previously latched at that port is lost. The OR lD Pp,A instruction performs a logical OR between the new data and the data currently latched at the
selected port. The result is then latched at that port. The final write mode uses the
AN lD Pp,A instruction. It performs a logical AND between the new data and the
data currently latched at the specified port. The result is latched at that port.
The data remains latched at the selected port following the logical manipulation until
new data is written to that port.

578

FUNCTIONAL
DESCRIPTION

",PD8243
BLOCK DIAGRAM

PIN IDENTIFICATION

PIN
NO.

SYMBOL

2-5
1, 21-23
17-20
13-16

P40- P43
P50- P53
P60- P63
P70- P73

The four 4-bit static bi-directional I/O ports. They
are programmable into the following modes:
input mode (during a Read operation); low
impedance latched output mode (after a Write
operation); and the tri-state mode (following a
Read operation). Data appearing on I/O lines
P20-P23 can be written directly. That data can
also be logically ANDed or ORed with the previous
data on those lines.

6

e'S

Chip Select input (active-low). When the J,lPD8343
is deselected (Cs '" 1). output or internal
status changes are inhibited.

7

PROG

Clock input pin. The control and address information are present on port lines P20-P23 when PROG
makes a high-to-Iow transition. Data is present on
port lines P20-P23 when PROG makes a low-to-high
transition.

8-11

P20- P23

P20-P23 form a 4-bit bi-directional port. Refer to
PROG function for contents of P20-P23 at the
rising and falling edges of PROG. Data from a
selected port is present on P20-P23 prior to the
rising edge of PROG if during a Read operation.

12

GND

The J,lPD8041 /8741 ground potential.

24

VCC

+5 volt supply.

FUNCTION

579

II

,.,.PD8243
o°C to +70°C
-65°C to +150°C
-65°C to +125°C
- 0.5 to + 7 Volts CD

Operating Temperature· . . . . . . . . . .
Storage Temperature (CeramicPackage) .
Storage Temperature (Plastic Package) .
Voltage on Any Pin
Power Dissipation . . . . . . . . .
Note:

CD

. . . . . . ..

ABSOLUTE MAXIMUM
RATINGS*

1W

With respect to groL'nd.

COMMENT: Stress above those listed under "Absolute Maximum Ratings·· may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other condi,tions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.
"Ta = 25°C

DC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

MLN

VoJ~age

V'L

-0.5

Input High Voltage

V'H

2.0

Input Low

MAX

TVP

UNIT

0.8

V

VCC+ O.5

V

TEST
CONDITIONS

Output Low Voltage (Ports 4-7)

VOLl

0.45

V

LOL ~ 5mAl!)

Output Low Voltage (POrt 7)

VOL2

1

V

IOL'" 20mA

0.45

V

tOl '" 0.6 mA

V

IOH '" 240 pA

Output Low Voltage (Port 2)

VOL3

Output High Voltage (Ports 4-7)

VOH1

2.4

Output High Voltage (Port 2)

VOH2

2.4

Sum of AlilOl From 16 Outputs

10'

Input Lea~age Current (Ports 4· 7)

I'Ll

Input Leakage Current (Port 2,

I'L2

CS, PROG)
V CC Supply Current
Note:

,

-

G)

V

IOH

eo

100 f../A

100

.mA

-10

20

"A

VIN '" VCC to OV

-10

10

"A

Y,N '" VCC to OV

20

mA

10

ICC

5 mA Each Pin

Refer to graph of additional sink current drive.

-

AC CHARACTERISTICS
LIMITS

PARAMETER

SYMBOL

MIN

Code Valid Before PAOG

IA

100

Code Valid After PAOG

IB

60

Data,Valid Before PAOG

Ie

200

Data Valid After PAOG

10

20

Port 2 Floating After PAOG

IH

a

PAOG Negative Pulse Width,

IK

900

Ports 4· 7 Valid After PAOG

IpO

Ports 4·7 Valid Before/After PAOG

tLPl

Port 2 Vafid After PROG

tACC

CS Valid Before/After PROG

les

TV.

MAX

UNITS

150

n,
n,
n,
n,
n,
n,
n,
n,
n,

700
100
750
50

TEST
CONDITIONS
80 pF Load
20 pF Load
80 pF Load
20 pF Load
20 pF Load

100 pF Load

80 pF Load

m

TIMING WAVEFORMS

PROG

PORT2
r------tACC-~---I

PORT 2

PORTS4·7 -----T"""-----.....:;;:.:;.::.:::;~:::.:;;.::.:...;:;.:.:.:;:.----...,.-------r

PORTS 4·7

58Q

ILPD8243
CURRENT SINKING
CAPABI LITY

CD

.
~

75

~
~

G
~

z

50

;;;
~

~
~

25

10
11
12
13
MAXIMUM SINK CURRENT AT ANY PIN (VOL'" O.4V)
MAXIMUM tOl WORST CASE PIN IN rnA.

Note:

CD

14

15

16

This curve plots the guaranteed worst case current Sinking capability of any I/O port line versus the total sink current of all pi,1S.
The ,uPD8243 is capable of sinking 5 rnA (for VOL'" O.4V) through each of the 16 I/O lines simultaneously. The current Sinking
curve shows how the individual 1/0 tine drive increases if all the 110 lines are not fully loaded.

PACKAGE OUTLINES
J-LPD8243C

(PLASTIC)
ITEM

MilliMETERS

1.3MAX

2.53

01
0.1

2.54

0.5

M

INCHES

33MAX

~

0.1

0.02

~

27.94

1.1

1.5

0.059

0.004

2.54 MIN

0.1 MIN

0.5 MIN

0.02 MIN

5.22 MAX

0.205 MAX

5.72 MAX

0.225 MAX

15.24

0.6

13.2

0.52

0.25

+0.10

-0.05

0.Q1

+0.004

-0.0019

II
8243DS-12-8o.CAT

581

NOTES

582

NEe

NEe Microcomputers, Inc.

p.PD8251
p.PD8251A

PROGRAMMABLE COMMUNICATION INTERFACES
DESCRIPTION

FEATURES

The}.lPD8251 and}.lPD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters (USARTs) are designed for microcomputer systems data communications.
The USART is used as a peripheral and is programmed by the 8080A or other
processor to communicate in commonly used serial data transmission techniques includ·
ing IBM Bi-Sync. The USART receives serial data streams and converts them into
parallel data characters for the processor. While receiving serial data, the USART will
also accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors and control signals such as TxE and SYNDET, is available
to the processor at any time.

• Asynchronous or Synchronous Operation
Asynch ronous:
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (}.lPD8251 A)
Synchronous:
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
• Baud Rate (1X Mode) - DC to 56K Baud (}.lPD8251)
- DC to 64K Baud (}.lPD8251A)
• Full Duplex, Double Buffered Transmitter and Receiver
• Parity, Overrun and Framing Flags
• Fully Compatible with 8080A/8085/}.lPD780 (Z80TM)
• All Inputs and Outputs are TTL Compatible
• Single +5 Volt Supply, ±10%
• Separate Device Receive and Transmit TTL Clocks
• 28 Pin Plastic DIP Package
• N-Channel MOS Technology
PIN NAMES

PIN CONFIGURATION

02

0,
00

vCC
~

Di'R
RTs
DSR
RESET

RxROY

0,.00
CIO
RO

WR

Data Bus 18 bitt)
Control or Data is to be Written or Read

Chip Enable

RESeT

R.."

TxC

Transmitter Ctock (TTL)

TxO

Transmitter

RxC
RxO

Rewlve, Clock (TTL)

RxRDY

Receiver Ready (has character for 8080)

Clock Pulse (TTL!

o.t.

Receiver Data

TKRDY

Transmitter Readv (readv for char. from

CLK

Q.!lR

O.t. Set Rudy

T.O

OTR
SYNDET

Data Terminal Ready
Sync Oetect

TxE

SVNDET/BO

Sync Detect/Break Detect

CTS"

RTS

Requillt to Send Oat.

CTS
T ••

CI •• r 10

SYNDET ("PD82511
SYNDET/BD ("PD8251A)
TxRDY

II

And Data Command
Write Data or Control Command

CS
CLK

80an

Send Data

Transmitter Empty

Vee

+5 V04t Supply

GNO

Ground

TM: Z80 is a registered trademark of Zilog.

Rev/4

583

JLPD825118251A
The pPDB251 and pPDB251 A Universal Synchronous/Asynchronous Receiver/
Transmitters are designed specifically for BOBO microcomputer systems but work with
most B-bit processors. Operation of the pPDB251 and pPDB251A, like other I/O devices
in the BOBO family, are programmed by system software for maximum flexibility.

FUNCTIONAL
DESCRIPTION

In the receive mode, the pPD8251 or pPDB251A converts incoming serial format data
into parallel data a'nd makes certain format checks. In the transmit mode, it formats
parallel data into serial form. The device also supplies or removes characters or bits that
are unique to the communication format in use. By performing conversion and formatting services automatically, the USART appears to the processor as a simple or "transparent" input or output of byte·oriented parallel data.
The pPDB251A is an advanced design of the industry standard B251 USART. It
operates with a wide range of microprocessors, including the B080, B085, and
pPD7BO (ZBOTM). The additional features and enhancements of the pPDB251A over
the pPDB251 are listed below.

pPD8251A FEATURES AND
ENHANCEMENTS

1. The data paths are double-buffered with separate I/O registers for control, status,
Data In and Data Out. This feature simplifies control programming and minimizes processor overhead.
2. The Receiver detects and handles "break" automatically in asynchronous
operations, which relieves the processor of this task.
3. The Receiver is prevented from starting when in "break" state by a refined Rx
initialization. This also prevents a disconnected USART from causing unwanted
interrupts.
4. When a transmission is concluded the TxD line will always return to the marking
state unless SBR K is programmed.
5. The Tx Disable command is prevented from halting transmission by the Tx
Enable Logic enhancement, until all data previously written has been transmitted. The same logic also prevents the transmitter from turning off in the middle of a word.
6. Internal Sync Detect is disabled when External Sync Detect is programmed. An
External Sync Detect Status is provided through a flip-flop which clears itself
upon a status read.
7. The possibility of a false sync detect is minimized by:
ensuring that if a double sync character is programmed, the characters be
contiguously detected.
clearing the Rx register to all Logic 1s (VOH) whenever the Enter Hunt command is issued in Sync mode.
B. The RD and WR do not affect the internal operation of the device as long as the
/-lPDB251A is not selected.
9. The pPDB251A Status can be read at any time, however, the status update will
be inhibited during status read.
10. The pPDB251A has enhanced AC and DC characteristics and is free from
extraneous glitches, providinll higher speed and improved operating margins.
11. Baud rate from DC to 64K.

C/O

RD

WR

CS

0
0
1
1

0
1
0
1

1
0
1
0

X
X

X

X

1

1

0
0
0
0
1
0

BASIC OPERATION
pPD8251/pPDB251A ~ Data Bus
Data Bus ~ pPDB251!W'DB251A
Status ~ Data Bus
Data Bus ~ Control
Data Bus

TM:Z80 is a registered trademark of Zilog.

584

~

3-Stcte

ILPD825118251A
BLOCK DIAGRAM
hO

TxROY

hE
he

RxRDY

SYNDET (.I.IP08251)
SYNDET/SD (j,OPD8251AI

ABSOLUTE MAXIMUM
RATINGS*

. . . - 0° C to + 70° C
-65°C to +125°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts

Operating Temperature.
Storage Temperature
Ali Output Voltages.
All Input Voltages
Supply Voltages ...

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause perr:'anent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indica'ted in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

*Ta = 25°C

DC CHARACTERISTICS

Ta

= o'e to

70'e; Vee

= 5.0V

±

= OV.

10%; GND

LIMITS
PD825!
PARAMETER

SYMBOL MIN TYP

Input Low Voltage

VIL

-0.5

Input High Voltage

VIH

2.0

Output Low Voltage

VOL

Output High Voltage

Data Bus Leakage

VOH

IlL

Power Supply Cur,rent

ICC

MIN

MAX

O.B

0.5

O.B

Vee

2.0

Vee

0.45

0.45

UNIT

TEST CONDITIONS

V
V
V

"PDB251 :

IOL

= 1.7 mA

= 2.2 mA
= -10e"A
IOH = -400 "A

"POB251A: IOL
2.4

2.4

V

"POB251 :
"POB251A:

IOL

Input Load Current

uPD8251A

MAX

45

-50

-10

10

10

10

10

"A

BO

100

mA

"A

IOH

VOUT

= 0.45V

VOUT

= Vce

At 5.5V
"PDB251A: All Outputs ::
Logic 1

CAPACITANCE
LIMITS
PARAMETER

SYMBOL

MIN

TV'

MAX

UNIT

TEST
CONDITIONS

Input Capacitance

CIN

10

pF

te = 1 MHz

110 Capacitance

CliO

20

pF

Unmeasured
pins returned
to GNO

585

fLP 08251/8251 A
Ta =

aOc to 70°C; Vee =

AC CHARACTERISTICS

5.OV ± 10%; GNO = OV
LIMITS

PARAMETER

SYMBOL

Io'P08251

I

MIN

I

Io'PD8215A

I

MAX

MIN

I

TEST
CONDITIONS

MA~ UNIT

READ
Address Stable before READ,

(E'S. C75)

Address HOld Time for READ.

'AR

(a. CD)

50

'RA

READ Pulse Width

'RR

Data Delay trom READ

'RD

350

200

'DF

200

100

READ to Data Floating

430

250

25

jJPD8251: CL ~ 100 pF
j.!P08251A: CL ~ 150 pF
,uP08251

10

Cl" 100pF
CL"15pF

WRITE
Address Stable before WRITE

'AW

Address Hold T,me for WAITE

'WA

20

'WW

400

250

'DW

200

150

'WD

40

WAl

E Pulse Width

Data Set-Up Time for WRITe
Data Hold Time for'W'l!ITT'r

Recovery Time Between WAITES

C2.)

20

6

'RV

'CY

OTHER TIMING
Clock Penod

3

0.420

'CY

Clock Pulse Width High

'OW

Clock Pulse Width Low

220

1.35

'OTK

R)( Data Set·Up Time to Samplmg Pulse

ISAx

Ax Data HOld Time to SamplIng Pulse

tHAx

Transmmer Input Clock Frequency
lX Baud Rate
l6x Baud Rilte
64X Baud Aate

'T.

Transmitter Input Clock Pulse '.'\I,dm
lX Baud Aate
l6X and 64X Baud Rate

tTPW

Transmitter Input Clock Pulse Delay
1 X Baud Aate
l6X and 64X Baud Rate

tTPD

Receiver Input Clock Frequency
1 X Baud Ra~e
16x Baud Rate
64X Baud Rate

fR.

Receiver Input Clock Pulse WIdth
1 X Baud Rate
16X and 64X Baud Rate

tRPW

ReceIver Input Clock Pulse Delay
1 X Baud Rale
l6X and 64X Baud Rate

tRPD

ICy·9O

50

'R.IF

TxD Delay from Failing Edge of TxC

1.35

120
90

'oW

Clock R,se and Fall Time

0.32

O. 7t CY

20

DC
DC
DC

56

kH,
kH,
kH,

6'
310

520
520

615

12

12

'"'
'CY

15

15

J

3

'CY
'CY

DC
DC

I UC

56

H,
kH,
kH,

64
310
615

520
520

12

12

~,

15

15

,

'CY

j

'CY

TxRDY Delay from Center 01 Dala Bit

'T.

16

RxRDY Delay from Center of Data B,t

'RX

20

24

'CY

Internal SYNDET Delay 110m Center
of Data B,I

'IS

25

24

'CY
'CY

'CY

External SYNDET Set-Up T,me before
Failing Edge of RxC

'ES

16

16

TxEMPTY Delay from Center of Data B,t

tTxE

16

20

Control Delay J!.2!!I Blwg Edge of
WRITE lTxE, DTR, RTS)

'wc

16

ContrOl 10 READ Set·Up T,me CDSR, CTS)

'CR

16

NOles.

«
..J
UJ

0

>;)
D.U.T.

+10

0

/

0.

>;)

24K 182511
6K 18251AI

0


DATA CH:A;ACTER

RECEIVE FORMAT
Notes

CD

@
G)

Generated by ~PD8251/82S1 A
Does not appear on the Data Bus.

If character length IS defined as 5. 6, or 7 bits, the
unused bits are set to "zero."

595

J4PD8251 18251 A
SYNCHRONOUS
TRANSMISSION

As in Asynchronous transmission, the TxD output remains "high" (marking)
until the ~PDB251 and ~PDB251 A receive the first character (usually a SYNC
character) from the processor. After a Command Instruction has set TxEN and
after Clear to Send (CTS) goes low, the first character is serially transmitted.
Data is shifted out on the falling edge of TxC and the same rate as TxC:
Once transmission has started. Synchronous Mode format requires that the serial data
stream at TxD continue at the TxC rate or SYNC will be lost. If a data character is
not provided by the processor before the ~PDB251 and ~PDB251A Transmit
Buffer becomes empty, the SYNC character(s) loaded directly following the Mode
Instruction will be automatically inserted in the TxD data stream. The SYNC
character(s) are inserted to fill the line and maintain synchronization until new data
characters are available for transmission. If the ~PDB251 and ~PDB251A become
empty. and must send the SYNC character(s), the TxEMPTY output is raised to signal
the processor that the Transmitter Buffer is empty and SYNC characters are being
transmitted. TxEMPTY is automatically reset by the next character from the processor.
In Synchronous Receive, character synchronization can be either external or internal.
If the internal SYNC mode has been selected. and the Enter HUNT (EH) bit
has been set by a Command Instruction, the receiver goes into the HUNT mode.

SYNCHRONOUS
RECEIVE

Incoming data on the RxD input is sampled on the rising edge of RxC. and the
Receive Buffer is compared with the first SYNC character after each bit has been
loaded until a match is found. If two SYNC characters have been programmed, the
next received character is also compared. When the SYNC character(s) programmed
have been detected. the ~PDB251 and ~PDB251A leave the HUNT mode and are in char·
acter synchronization. At this time, the SYNDET (output) i.s set high. SYNDET is
automatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction. a "one" applied
to the SYNDET (input) for at least one RxC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the Synchronous as in the
Asynchronous Mode. If not in HUNT. parity will continue to be checked eVEtn
if the receiver is not enabled. Framing errors do not apply in the Synchronous
format.
The processor may command the receiver to enter the HUNT mode with a Command
Instruction which sets Enter HUNT (EH) if synChronization is lost.
07

06

05

+,

.04

I scs IESO I EP 1..

03

I
I

I

0'/

0,

ILl I

0

DO

I

0

MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE

I

I

CHARACTER lENGT H

0

1

0

0

0

1

1

5
BITS

6
BITS

7

8

BITS

BITS

:

1

PARITY ENABLE

11
(0

ENABLE)
DISABLEl

EVEN PARITY GENERATIONfCHE CK
1 EVEN

o

ODD

EXTERNAL SYNC DETECT
SYNDET IS AN INPUT
SYNOET IS AN OUTPUT

' - - - - - - - - - - - - _ SINGLE CHARACTER SYNC
1 SINGLE SYNC CHARACTER
o DOUBLE SYNC CHARACTER

596

","PD8251 18251 A
TRANSMIT/RECEIVE
FORMAT
SYNCHRONOUS MODE

PROCESSOR BYTES 1,,8 BITS CHARI

OAT A CH:\:RACTERS
l\SSE~,lRl

SYNC
CHAR 1

EO SERIAL DATf\ OUTPlJT (h.D)

SYNC
CHAR

~'

rlA T

~ CH~R:I-'_C_T_Ef_1S

_ _ _...J

TRANSMIT FORMAT
SE~~ll\l

OAT A INPUT iG ... ()1

OAT

~

OI'\H:I-"_C_T_U_'S_ _ _.J

PROCESSOR BYTES 158 BITS CHAR'

CD

DATAC:~
RECEIVE FORMAT
Note

CD

If

Chcll,lctE'1

blt~

COMMAND INSTRUCTION
FORMAT

STATUS READ FORMAT

PARITY ERROR

OVERRUN ERROR

FRAMING ERROR

CD

lenqlh I~ dplll1t'd ,1:' 5, Gar 7 ll'tS ttl,' ullu~l'd

,Hr' St'! to "1(>10

After the functional definition of the I1PD8251 and I1PD8251A has been specified by
the Mode Instruction and the SYNC character(s) have been entered (if in SYNC model,
the USART is ready to receive Command Instructions and begin communication. A
Command Instruction is used to control the specific operation of the format selected
by the Mode Instruction. Enable Transmit, Enable Receive, Error Reset and Modem
Controls are controlled by the Command Instruction.
After the Mode Instruction and the SYNC character(s) (as needed) are loaded, all
subsequent "control writes" (C/O ~ 1) will load or overwrite the Command Instruction
register. A Reset operation (internal via CMD IR or external via the RESET input)
will cause the I1PD8251 and I1PD8251A to interpret the next "control write", which
must immediately follow the reset, as a Mode Instruction.
It is frequently necessary for the processor to examine the status of an active
interface device to deter'l'ine if errors have occurred or if there are other conditions
which require a response from the processor. The I1PD8251 and I1P[)8251 A have
features which allow the processor to read the device status at any time. A data fetch
is issued by the processor while holding the C/O input "high" to obtain device Status
Information. Many of the bits in the status register are copies ot"external pins. This
dual status arrangement allows the I1PD8251 and I1PD8251A to be us~d in both Polled
and interrupt driven environments. Status update can have a maximum delay of 16
clock periods in the I1PD8251 and 28 clock periods in the I1PD8251 A.
When a parity error is detected, the PE flag is set. It is cleared by setting the
ER bit in a subsequent Command Instruction. PE being set does not inhibit USART
operation.
If the processor fails to read a data character before the one following is available,
the OE flag is set. It is cleared by setting the E R bit in a subsequent Command
Instruction. Although OE being set does not inhibit USART operation, the
previously received character is overwritten and lost.
If a valid STOP bit is not detected at the end of a character, the FE flag is ~et. It
is cleared by setting the ER bit in a subsequent Command Instruction. FE being set
does not inhibit USART operation.
Note:

CD

ASYNC mode only.

597

,u.PD8251/8251 A

COMMAND INSTRUCTION
FORMAT
TRANSMIT ENABLE

1 "enable
0"- disable

DATA TERMINAL

READY
"high" Will force
output to zero

'B'TR

RECEIVE ENABLE
1 " enable
0" disable

SEND BREAK
CHARACTER
1 '" forces TxD "low"

o " normal

opera lion

ERROR RESET
1'" reset all error flags
PE. QE, FE

REQUeST TO SENO
"high" will force
output to zero

RTs

INTEANAL RESET
"high" returns USART to
Mode Instruction Format

ENTER HUNT MQDE
1 " enable se31ch for Sync
Characters

CD

STATUS READ FORMAT

I I I
DSR

I

SYNDET

ISO

1

0,

FE

1 I I I I L.
DE

PE

T,E

R,ROY

T,RDY

1 1

SAME DEFINITIONS AS 110 PINS

PARITY ERROR

The PE flag IS set when a parity
error is detected. It is reset by
the ER bit of the Command
Instruction. PE does not Inhibit
operation of Ihe

~PD8251

and

,IlPD8251A.

OVERRUN ERROR
The OE flag IS set wh~n the CPU

~

does not r~ad a character before
the next one becomes. available.
It is reset by the ER bn of the
Command Instruct!on. DE does
not mhiblt operatIon of the /.IP08251
and /.IP08251 A; but, the preVIously overrun character IS lost.

FRAMING ERROR lAsync only)
The FE flag is set when a v!'Ilid
Stop bit is not d~tected at the
end of every character. It is reset
bv the ER bit of the Command
Instruction. FE do" not inhibit
the oper!'ltion of the ~P06251 and
/,tPD8251A.
Notes

CD
RP
clock cycles; Low Period --> ~ clock periods, where N is the decimal value of count
data). If the count register is reloaded with a new value during counting, the new value
will be reflected immediately after the output transition of the current count.
The OUTPUT will be held in the high state while GATE is asserted. Counting will start
from the full count data after the GATE has been removed.

QUTPUTI".~I~

"m,e"m~---------

OUTPUT ,"".,

Mode 4: Software Triggered Strobe
The OUTPUT goes high when MODE 4 is set, and counting begins after the second
byte of data has been loaded. When the terminal count is reached, the OUTPUT will
pulse low for one clock period. Changes in count data are reflected in the OUTPUT as
soon as the new data has been loaded into the count registers. During the loading of
new data, the OUTPUT is held high and counting is inhibited.
The OUTPUT is held high for the duration of GATE. The counters are reset and
counting begins from the full data value after GATE is removed.

".~,..--------~r--------------

Mode 5: Hardware Triggered Strobe
Loading MODE 5 sets OUTPUT high. Counting begins when count data is loaded and
GATE goes high. After terminal count is reached, the OUTPUT wi:1 pulse low for one
clock period. Subsequent trigger pulses will restart the counting ser:uence with the
OUTPUT pulsing low on terminal count following the last rising ecge of the trigger
input (Reference bottom half of timing diagram).

"'.

...

II

~---------------------

~r---------

_ _ _IL..J

607

fLPD8253-5
PACKAGE
iJ PD8253C OUTLINE
iJPD8253-5C

608

8253-5DSR EV 4-1 0-80-CAT

NE'C

NEe Microcomputers, Inc.

fLPD8255
fLPD8255A·5

PROGRAMMABLE PERIPHERAL INTERFACES
D ESCR I PTI ON

F EATU R ES

The IlPD8255 and IlPD8255A-5 are general purpose programmable INPUT/OUTPUT
devices designed for use with the 8080A/8085A microprocessors. Twenty-four (24)
I/O lines may be programmed in two groups of twelve (group I and group II) and used
in three modes of operation. In the Basic mode, (MODE 0), each group of twelve I/O
pins may be programmed in sets of 4 to be iniJut or output. In the Strobed mode,
(MODE 1), each group may be programmed to have 8 lines of input or output. Three
of the remaining four pins in each group are used for handshaking strobes and interrupt
control signals. The Bidirectional Bus mode, (MODE 2), uses the 8 lines of Port A for
a bidirectional bus, and five lines from Port C for bus control signals. The IlPD8255
and IlPD8255A-5 are packaged in 40 pin plastic dual-in-line packages.

• Fully Compatible with the 8080A/8085 Microprocessor Families
•

PIN CONFIGURATION

All Inputs and Outputs TTL Compatible

•

24 Programmable I/O Pins

•

Direct Bit SET/RESET Eases Control Application Interfaces

•

8 - 2 mA Darlington Drive Outputs for Printers and Displays (IlPD8255)

•

8 - 4 mA Darlington Drive Outputs for Printers and Displays (IlPD8255A-5)

•

LSI Drastically Reduces System Package Count

•

Standard 40 Pin Dual-In-Line Plastic and Ceramic Packages

PA3
PA2
PAl
PAo
RD

cs

GND
Al
AO
PC7
pC6
PC5
PC4
PCo
PCl
PC2
PC3
PBo
PBl
PB2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Il PD
8255/
8255A-5

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Rev/2

PA4
PA5
PA6
PA7
WR
RESET
Do
Dl
D2
D3
D4
D5
D6
D7

PIN NAMES
D7- DO

Data Bus {SI-Dlrectlonal}

RESET

Reset Input

es

Chip Select

RD
WR

Read Input
Write Input

AO. A,

Port Address

PA7,PAO

Port A (Bit}

PB7-PBO

Port 8 (Bltl

pe7-pea

Vee
GND

II

Port C (Bit)

+5 Volts

o Volts

Vcc
PB7
PB6
PB5
PB4
PB3

609

fL P D8255/8255A·5
General
FUNCTIONAL DESCRIPTION
The .uPD8255 and .uPD8255A-5 Programmable Peripheral Interfaces (PPI) are designed
for use in 8080A/8085A microprocessor systems_ Peripheral equipment can be effectively
and efficiently interfaced to the 8080A/8085A data and control busses with the.uPD8255
and .uPD8255A-5_ The .uPD8255 and .uPD8255A-5are functionally configured to be
programmed by system software to avoid external logic for peripheral interfaces_
Data Bus Buffer
The 3-state, bidirectional, eight bit Data Bus Buffer (DO-D71 of the .uPD8255 and
.uPD8255A-5 can be directly interfaced to the processor's system Data Bus (DO-D7)The Data Bus Buffer is controlled by execution of IN and OUT instructions by the
processor. Control Words and Status information are also transmitted via the Data Bus
Buffer.
Read/Write and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
peripheral interfaces.
Chip Select, CS, pin 6
A Logic Low, VI L, on this input enables the .uPD8255 and .uPD8255A-5 for communication with the 8080A/8085A.
Read, RD, pin 5
A Logic Low, VIL on this input enables the .uPD8255 and pPD8255A-5 to send Data
or Status to the processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, V I L, on th is input enables the Data Bus Buffer to receive Data or Control Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin 8
These two inputs are used in conjunction with CS, RD, and WR to control the selection of one of three ports on the Control Word Register. AD and A 1 are usually
connected to AD and Al of the processor Address Bus.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode. The input latches in ports A, B, and C are not cleared.
Group I and Group II Controls
Through an OUT instruction in System S.oftware from the processor, a control word
is transmitted to the .uPD8255 and .uPD8255A-5. Information such as "MODE,"
"Bit SET," and "Bit RESET" is used to initialize the functional configuration of each
I/O port.
Each qroup (I and II) accepts "commands" from the Read/Write Control Logic and
"control words" from the internal data bus and in turn controls its associated I/O
ports.
Group I - Port A and upper Port C (PC7-PC4)
Group II - Port B and lower Port C (PC3-PCO)
While the Control Word Register can be written into, the contents cannot be read back
to the processor.
-Ports A, B, and C
The three 8-bit I/O ports (A, B, and CI in the .uPD8255 and .uPD8255A-5 can all be
configured to meet a wide variety of functional requirements through system software.
The effectiveness and flexibility of the .uPD8255 and .uPD8255A-5 is further
enhanced by special features unique to each of the ports.
Port A = An 8-bit data output latch/buffer and data input latch.
Port B = An 8-bit data input/output latch/buffer and an 8-bit data input buffer.
Port C = An 8-bit output latch/buffer and a data input buffer (input not latched).
Port C may be divided into two independent 4-bit control and status ports for use with
Ports A and B.

610

fL PD8255/8255A·5
BLOCK DIAGRAM
~OWER

\ ---

SUPPllH

,r,v

I ___ '"

'"

PC

~C.

WAITE

CONTROL
LOGIC

a _ _ _ _J

ABSOLUTE MAXIMUM
RATINGS'

o°c to +70°C
-65°C to +125°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to + 7 Volts

Operating Temperature
Storage Temperature ..
All Output Voltages CD .
All Input Voltages CD
Supply Voltages CD ...
Note:

CD

With respect to VSS

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specificatIOn IS not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS

Ta =o°c to +70°C;Vcc =+5V

10

1O%;VSS =ov
LIMITS
,uPD8255A 5

/JPD8255

PARAMETER
~u I Low Voltage
In~ut

High Voltage

SYMBOL

MIN

V,L

VSS-O.5

VOL

Output High Voltage

VOH

Power Supply Current

lee
lLIH

Input Leakage Current

ILiL

Output Leakage Current
Notes:

1

MAX
0.8
Vee

04

IOH(1

Input Leakage Current

TVP

2

Vee

045
24

2.4

Darlington Drive Current

Output Leakage Current

MIN

0.8 -0.5

2

V,H

Output Low Voltage

TVP MAX

2

4

40

120

~

TEST
CONDITIONS

UNIT
V

v

~'0

V

3

V

1

~4

mA

VOH

1 5V, REXT

120

mA

Vee

'5V, Output Open

10

10

10

750H

MA

V,N

Vee

~1O

,A

V,N

o 4V

ILOH

10

±10

MA

VOUT - Vee; CS

20V

ILOL

~10

~1O

MA

VOUT - 0 4V. CS

20V

~

G)

Any set of eight 38) outputs from e,ther Pon A, 8, or C can source 2 mA ,nlO 1 5V for ",PQ8255. or 4 rnA 11110
1,5V tor .. PD8255A-5

@

For .. PD8255 IOL
1 7 mA
For .. PD8255A-5 IOL
25 mA for

Q)

For pPD8255: IOH "" - 100 pA for DB Port: 50}Js for Peripheral Ports.
For pPD8255A-5: IOH -400 pA for dB Port: - 200 ps for Peripheral Ports

08 Port. I 7 mA tor Peripheral

Porl~

0;

CAPACITANCE

Ta = 25°C: VCC = VSS = OV
PARAMETER

SYMBOL

LIMITS
MIN TYP MAX UNIT

TEST CONDITIONS

Input Capacitance

CIN

10

pF

fc=lMHz

1/0 Capacitance

CliO

20

pF

Unmeasured pins
returned to VSS

611

,.,. PD8255/8255A·5
T. -Ifc to+7O"c;

vee" +!iV:t

5'JI,;

vss" ov

.....

AC CHARACTERISTICS

L.. ITS

SYMBOL

PARAMETER

MIN

MAX

TEST

A·I
MIN

MAX

UNIT

CONDITIONS

.EAD
Address Stll~. Befor. ~

'AR

Addr_ Stable Aftn READ

'RA

IRQDPuIMWldttI

'"

'RD

,..

'OF

,,0



"'"

WAITE

8255:Cl.-l00pF
8266A·5: CL .. 150 pF

200
100
10

.'"

'RV

300

OlMER TIMING
WR" OTo 0u1(lUt

'VI.

hrlph'" Datlla.tOf1llm

'IR

ACK PuI.. WIchh

'AK

. ~PuI.. Widlh

'ST

,.,
,,.,

"'H

150

hrlphera! 0.111 Att.

1m

'HR

500

500

"'.

&K-OToOutpUl

'AD

400

'JQ:'R' .. 0 To OutpUt Float

'KO

30.

m

'0
180

'00
20

20

-""-IT.o.,--.

300

'WOO

'50
'5O

xeR'''OToOBF.'

tAOB
ISIB

4'"
450

350

m"OToI8F·'

RD.' ToIBF-O

tRIB

360

300

"'IT
"IT

4"
400

400

300

I"IT

400

350

twiT

850

860

_"'1?-OToINTA-O
STI·' To INTA·'
ACK .. 1 To INTR .. 1

lIFt .. 0 To INTH .. 0

Notes:

8255: Cl .. 60 pF
8266.A·6: CL .. 150 pF

'00

Per. DIta Aft., T.E. Of STB

"',0.111 Beton T.E. Of

,'"

500

300

8255: CL" 50 pF
8265A·5: CL -1&OpF

82$5{~L·50PF
CL-15pF

82&&: CL .. 60 pF

8266A·5: Cl .. , &0 pF


1 Watt

Operating Temperature ...
Storage Temperature
Voltage on Any Pin
Power Dissipation
Note:

ABSOLUTE MAXIMUM
RATINGS*

 With Respect to Ground

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
*Ta = 25°C
Ta = o°c to +70o e; vee = +5V ± 10% GND.= OV
SYMBOL

PARAMETER

I nput Low Voltage

V IL

-0.5

Input High Voltage

V IH

2.0

Output Low Voltage

VOL

Output High Voltage

VOH

DC CHARACTERISTICS

LIMITS
MIN.

TYP.

MAX.
0.8

UNIT

TEST CONDITIONS

Volts

Vee +0.5 Volts
0.45

2.4

Vee

Volts

IOL· 1.7 mA

Volts

IOH =-150~A forAB,
DB and AEN
IOH· -80~A for others

HRQ Output High Voltage

V HH

Vee Current Drain

IOH· -80~A

Vee

Volts

ICC

120

mA

Input Leakage

IlL

10.

~

V IN = VCC

Output Leakage During Float

IOFL

10

~

VOUT(j)

Note:

CD Vee> V OUT >

3.3

GND + 0.45V

Ta = 2Soc; VCC = GND = OV

CAPACITANCE

LIMITS

UNIT

TEST CONDITIONS

PARAMETER

SYMBOL

Input Capacitance

CIN

10

pF

fc = 1 MHi

CI/O

20

pF

Unmeasured pins
returned to GND

I/O Capacitance

618

MIN.

TYP.

MAX.

AC CHARACTE R ISTICS
PERIPHERAL (SLAVE) MODE

fLPD8257-5

BUS PARAMETERS
T.-Q"Cto70oe;Vee=5V',0%;GNO-ov---- (~~~

ADR)

_ _ _ _ _ _ _ _ _ _ DATAo-7

-------<::::>"--+---t----------

(UPPER ADRl

ADR STS

- - - - - i5ACKO•3

~,....,;:::j::==::j:==7. . . . ----

TCfMARK _ _ _ _ _ _ _

=

M'EMRo/ilOFiO

U:;.....---...J.c--\=:::..-------___,c.'=====L__

..J~t::::::::j;:......=.___'c__\C:::)~_ _ _..

=TA<

FUNCTIONAL
DESCRIPTION

The /LPDS257-5 is a programmable, Direct Memory Address (DMA) device. When used with an
S212 I/O port device, it provides a complete four-channel DMA controller for use in SOSOA/SOS5A
based systems. Once initialized by an SOSOA/SOS5A CPU, the ILPDS257-5 will block transfer up to
16,364 bytes of data between memory and a peripheral device without any attention from the
CPU, and it will do this on all 4-DMA channels. After receiving a DMA transfer request from a
peripheral, the following sequence of events occurs within the /LPDB257-5.
•

It acquires control of the system bus (placing SOSOA/BOB5A in hold mode).

•

Resolves priority conflicts if multiple DMA requests are made.

•

A 16-bit memory address word is generated with the aid of an 8212 in the following manner:

The /LPDS257-5 outputs the least significant eight bits (AO-A7) which go directly onto the
address bus.
.
The /LPDS257-5 outputs the most significant eight bits (AB-A15) onto the data bus where
they are latched into an B212 and then sent to the high order bits on the address bus.
•

The appropriate memory and I/O read/write control signals are generated allowing the
peripheral to receive or deposit a data byte directly from or to the appropriate memory
location.

Block transfer of data (e.g., a sector of data on a floppy disk) either to or from a peripheral may be
accomplished as long as the peripheral maintains its DMA Request (DROn ). The /LPDS257-5 retains
control of the system bus as long as DROn remains high or until the Terminal Count (TC) is
reached. When the Terminal Count occurs, TC goes high, informing the CPU that the operation is
complete.
There are three different modes of operation:

•

DMA read, which causes data to be transferred from memory to a peripheral;

•

DMA write, which causes data to be transferred from a peripheral to memory; and

•

DMA verify, which does nOl"actually involve the transfer of data.

The DMA read and write modes are the normal operating conditions for the /LPDS257-5: The DMA
verify mode responds in the same manner as read/write except no memory or I/O read/write
control signals are generated, thus preventing the transfer of data. The peripheral gains control of
the system bus and obtains DMA Acknowledgements for its requests, thus allowing it to access
each byte of a data block for check purposes or accumulation of a CRC (Cyclic Redundancy Code)
checkword. In some applications it is necessary for a block of OMA read or write'cycles to be
followed by a block of DMA verify cycles to allow the peripheral to verify its newly acquired
data.

621

II

f.J. PD8257-5
Internally the J,lPD8257-5 contains six different states (SO, S1, S2, S3, S4 and SW). The
duration of each state is determined by the input clock. In the idle state, (S1). no DMA
operation is being executed. A DMA cycle is started upon receipt of one or more DMA
Requests (DRO n ), then the J,lPD8257-5 enters the 50 state. During state SO a Hold
Request (HRO) is sent to the 8080A/8085A and the J,lPD8257-5 waits in 50 until the
8080A/8085A issues a Hold Acknowledge (HLDA) back. During SO, DMA Requests
are sampled and DMA priority is resolved (based upon either the fixed or priority
schemel. After receipt of HLDA, the DMA Acknowledge line (DACK n ) with the high·
est priority is driven low, selecting that particular peripheral f<;>r the DMA cycle. The
DMA Request line (DRO n ) must remain high until either a DMA Acknowledge
(BACK n ) or both DACK n and TC (Terminal Couht) occur, indicating the end of a
block or sector transfer (burst model).

DMA OPE RATION

The DMA cycle consists of four internal states; 51, S2, 53 and S4. If the access time
of the memory or I/O device is not fast enough to return a Ready command to the
,uPD8257-5 after it reaches state S3, then a Wait state is initiated (5W). One or more
than one Wait state occurs until a Ready signal is received, and the ,uPD8257-5 is
allowed to go into state S4. Either the extended write option or the DIVI,AVerify mode
may eliminate any Wait state.
If the J,lPD8257-5 should lose control of the system bus (i.e., HLDA goes low) then the
current DMA cycle is completed, the device goes into the S1 state, and no more
DMA cycles occur until the bus is reacquired. Ready setup time (tRS). write setup,
time (tOW). read data access time (tRD) and HLDA setup time (t05) should all be
carefully observed during the handshaking mode between the J,lPD8257-5 and the
8080A/8085A.
During DMA write cycles, the I/O Read (I/O R) output is generated at the beginning
of state 52 and the Memory Write (MEMW) output is generated at the beginning of
53. During DMA read cycles, the Memory Read (MEMR) output is generated at the
beginning of state S2 and the I/O Write (I/O W) goes low at the beginning of state 53.
No Read or Write control signals are generated during DMA verify cycles.

RESET

Notes:

 Data Bus
IMR -> Data Bus

1
1
1
1

a
0
0
0

0
0
0
0

1

1
X

0
1

CO

PROCESSOR OUTPUT OPERATION (WRITE)

°
0
0
1

0
0
1

0
1

X

X
X

X
X

X
X

Data
Data
Data
Data

Bus ->
Bus ->
Bus ->
Bus ->

OCW2
OCW3
ICW1
OCW 1, ICW2, ICW3

@

DISABLE FUNCTION
X
X

Notes:

X

Data Bus -> 3-State
Data Bus -> 3-State

TEST POINTS

_Q8

Q8_

TIMING
WAVEFORMS

WRITE MODE

Cs - - - - - - " " \

r----

[,--1_-------++--.,.1

ADDRESS BUS
AO _ _ _ _ _ _J

~_ _I_--------++-~

~----

DATA BUS

READ/iNfA MODE

RD/iNTA---------..

t-----tRLRH---

EN-------~~

cs -------..

tRLEL

tRHAX

Ir-I_---------f--,.]

ADDRESS BUS
AO _ _ _ _ _....J

DATA BUS-- _ _ _ _ _ _ _ _ _ _ _

tJ- _____ _

tRLD~'-_ _ _t_RH_D_Z___
~A~~V_
-

-1_

OTHER TIMING

646

AC CHARACTERISTICS
(CONT.)

p.PD8259A
TIMING WAVEFORMS
(CONT.)

"\ 1
IR

INTA SEQUENCE
r-tJHIH

-~~J-_C_.-..

-----.._---"\<@

\ - CD

INT

\

INTA - - - - - - - - . .

-p-- -0-tc~::~~-I - L J ~---;tf~--~---~-~-------~-

08-------------

tCVIAL

\

,

CO.2--_ _ _ _ _ _

-tIALCV-:t

DETAILED OPERATIONAL
DESCRIPTION

The sequence used by the IlPD8259A to handle.. an interrupt depends upon whether
an 8080A/8085A or 8086/8088 CPU is being used.
The following sequence applies to 8080A/8085Asystems:
The IlPD8259A derives its versatility from programmable interrupt modes and the
ability to jump to any memory address through programmable CALL instructions. The
following sequence demonstrates how the IlPD8259A interacts with the processor.
1. An interrupt or interrupts appearing on I R0-7 sets the corresponding IR bit(s)
high. This in turn sets the corresponding I R R bit(s) high.
2. Once the I R R bit(s) has been set, the j.lPD8259A will resolve the priorities
according to the preprogrammed interrupt algorithm. It then issues an INT signal
to the processor.
3. The processor group issues an INTA to the j.lPD8259A when it receives the INT.
4. The i'iiifA input to the j.lPD8259A from the processor group sets the highest
priority ISR bit and resets the corresponding IR R bit. The INTA also signals the
j.lPD8259A to issue an 8-bitCALL instruction op-code (11001101) onto its Data
bus lines.
5. The CALL instruction code instructs the processor group to issue two more
INTA pulses to the j.lPD8259A.
6. The two ii\iTA pulses signal the j.lPD8259A to place its preprogrammed interrupt
vector address onto the Data bus. The first INTA releases the low-order 8-bits
of the address and the second i'iiifA releases the high-order 8-bits.
7. The j.lPD8259A's CALL instruction sequence is complete. A preprogrammed
EOI (End-of-Interrupt) command is issued to the j.lPD8259A at the end of an
interrtfl'! service routine to reset the ISR bit and allow the j.lPD8259A to service
the next interrupt.
For 8086/8088 systems the first three steps are the same as described above, then the
following sequence occurs:
4. During the first iNTA from the processor, the j.lPD8259A does not drive the
data bus. The highest priority ISR bit is set and the corresponding I RR bit is
reset.
5. The j.lPD8259A puts vector onto the data bus on the second INT A pulse from
the 8086/8088.
6. There is no third iNTA pulse in this mode. In the AEOI mode the ISR bit is
reset at the end of the second INTA pulse, or it remains set until an EOI command is issued.

647

IJ. PD8259A
SOSOA/SOS5A MODE

INTERRUPT

SEQUENCE
For these processors, the pPD8259A is controlled by three INTA pulses. The first
ii\iTA pulse will cause the ,uPD8259A to put the CALL op-code onto the data bus. The
second and third INTA pulses will cause the upper and lower address of the interrupt
vector to be released on the bus.
07

Of

05

D4

03

02

O.

I'

CALL CODE

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

DO

,I

Int.,.I_4

1ft
07

Of

os

D4

7

A7

A6

A5

6

A7

A6

A5

•1

5

A7

A6

A5

4

A7

A6

A5

3

A7

A6

A5

0

2

,

A7

A6

A5

0

A7

A6

A5

0

A7

A6

,

07

Of

Ai

A6

6

A7

AS

,

02

O'

DO

1

0

0

0

,

0

0

1

•
0

0

0

1

0

0

0

0

,
•
0

0

A5

0

0

05

04

03

,

03

1

0

0

0

0

0

1

0

0

0

0

0

,

02

D.

DO

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

SECOND INTA

Interv.I ....

1ft

5

A7

A6

4

A7

A6

,
,
,
,

3

A7

A6

0

2

A7

A6

0

,

1

A7

A6

0

0

,

0

"7

A6

0

0

0

,

,

0

07

Of

05

D4

03

02

D.

DO

A15

A1.(

A13

A12

A.l1

A'O

A9

AS

THIRDTNiA

In this mode only two INTA pulses are sent to the pPD8259A. After the first INTA
pulse, the ,uPD8259A does not output a CALL but internally sets priority resolution.
If it is a master, it sets the cascade lines. The interrupt vector is output to the data bus
on the second INTA pulse.

IR7
IR6
IR5
IR4
IR3
IR2
IR1
IRO

648

FIRST TIiiTA

~

07

06

T7
T7

T6
T6
T6
T6
T6
T6
T6
T6

T7

T7
T7
T7

T7
T7

OS
T5
T5
T5
T5
T5
T5
T5
T5

D4

D3

T4
T4
T4
T4
T4
T4
T4
T4

T3
T3
T3
T3
T3
T3

T3
T3

02
1
1

01

DO

1

1

1

0

1

0

1

1

0

0

0

1

1

0
0

1
0

0
1

0

0

0

p.PD8259A
INITIALIZATION ICW1 AND ICW2
COM MAN D WOR DS A5-A 15_ Page starting address of service routines. In an 8085A system, the 8 request
levels generate CALLs to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 routines
occupy a page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (AO-A15). When the routine interval is 4, AO-A4 are
automatically inserted by the /lPD8259A, while A5-A15 are programmed externally.
When the routine interval is 8, AO-A5 are automatically inserted by the /lPD8259A,
while A6-A15 are programmed externally.
The 8-byte interval maintains compatibility with current software, while the 4-byte
interval is best for a compact jump table.
In an MCS-86 system, T7-T3 are inserted in the five most significant bits of the vectoring byte and the /lPD8259A sets the three least significant bits according to the interrupt level. AlO-A5 are ignored and ADI (Address Interval) has no effect.
LTIM:

If LTIM; 1, then the /lPD8259A operates in the level interrupt mode.
Edge detect logic on the interrupt inputs is disabled.

ADI:

CALL address interval. ADI ; 1 then interval = 4; ADI = 0 then
interval = 8.

SNGL:

Single. Means that this is the only /lPD8259A in the system. If SNGL;
1 no ICW3 is issued.

IC4:

If this bit is set - ICW4 has to be read. If ICW4 is not needed, set
IC4 = O.

ICW3
This word is read only when there is more than one /lPD8259A in the system and cascading is used, in which case SNGL; O. It will load the 8-bit slave register. The functions of this register are:
a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in
ICW4) a "1" is set for each slave in the system. The master then releases
byte 1 of the call sequence (for 8085A system) and enables the corresponding slave to release bytes 2 and 3 (for 8086/8088 only byte 2) through the
cascade lines.
b. In the slave mode (either when SP = 0, or if BUF; 1 and M/S = 0 in ICW4)
bits 2-0 identify the slave. The slave compares its cascade input with these bits
and if they are equal, bytes 2 and 3 of the CALL sequence (or just byte 2 for
8086/8088) are released by it on the Data Bus.
ICW4
SFNM:

If SFNM = 1 the special fully nested mode is programmed_

BUF:

If BUF = 1 the buffered mode is programmed. In buffered mode SP/EN
becomes an enable output and the master/slave determination is by
M/S.

M/S:

If buffered mode is selected: MIS; 1 means the /lPD8259A is programmed to be a master, MIS = 0 means the /lPD8259A is programmed
to be a slave. If BUF; 0, MIS has no function.

AEOI:

If AEOI ; 1 the automatic end of interrupt mode is programmed.

/lPM:

Microprocessor mode: /lPM ; 0 sets the /lPD8259A for 8085A system
operation, /lPM ; 1 sets the /lPD8259A for 8086 system operation.

II
649

JI. PD8259A

I

AD

D7

De

De

0

A7

AI

AI

1M

III

D2

Dl

LTlIl

AD/

IHOL

A11/T3

A'O

A.

S2/102

S1/101

IllS

AEOI

INITIALIZATION
SEQUENCE

DO
1C4 IICWl

I

I

1

A15/17

A14/TS

A131T5

A121T4

*.~
.

AI

I'CW2

(SNGL.1)

NO (SNOL.II/

I '

17

II

SO

12

SO/IDOJ ICWS

t

~~,

IIC.. O)

VEl (1C4. 'I

I '

0

SFNM

IUF

I

I

READY TO ACCEPT INTERRUPTS

650

~P"IICW4

jLPD8259A
OPPERATIONAL COMMAND
WORDS (OCW's) @

Once the !lPD8259A has been programmed with Initialization Command Words,
it can be programmed for the appropriate interrupt algorithm by the Operation
Command Words. Interrupt algorithms in the !lPD8259A can be changed at any time
during program operation by issuing another set of Operation Command Words. The
following sections describe the various algorithms available and their associated OCWs.

INTERRUPT MASKS
The individual Interrupt Request input lines are maskable by setting the corresponding
bits in the Interrupt Mask Register to a logic "1" through OCW1. The actual masking
is performed upon the contents of the In-Service Register (e.g., if Interrupt Request
line 3 is to be masked, then only bit 3 of the IMR is set to logic "1." The IMR in turn
acts upon the contents of the ISR to mask b~t 3). Once the /.lPD8259A has acknowledged
an interrupt, i.e., the !lPD8259A has sent an INT si!jnal to the processor and the system
controller has sent it an I NTA signal, the interrupt inp\Jt,' ,although it is masked,
inhibits lower priority requests from being acknowledged. There are two means of
enabling these lower priority interrupt lines. The first is by issuing an End-of-Interrupt
(EO\) through Operation Command Word 2 (OCW2), thereby resetting the appropriate ISR bit. The second approach is to select the Special Mask Mode through OCW3.
The Special Mask Mode (SMM) and End-of-Interrupt (EO)) will be described in more
detail further on.

FUllY NESTED MODE
The fully nested mode is the !lPD8259A's basic operating mode. It will operate in this
mode after the initialization sequence, without requiring Operation Command Words
for formatting. Priorities are set IRO through I R7, with I RO the highest priority. After
the interrupt has been acknowledged by the processor and system controller, only
higher priorities will be serviced. Upon receiving an I NTA, the priority resolver
determines the priority of the interrupt, sets the corresponding IR bit, and outputs the
vector address to the Data bus. The EOI command resets the corresponding ISR bits at
the end of its service routines.
Notes:

CD

@

Reference Figure 2
Reference Figure 3

II
651

,.,. PD8259A

ROTATING PRIORITY MODE COMMANDS
The two variations of Rotating Priorities are the Auto Rotate and Specific Rotate
modes. These two modes are typically used to service interrupting devices of equivalent
priorities.
1. Auto Rotate Mode
Programming the Auto Rotate Mode through OCW2 assigns priorities 0·7 to the
interrupt request input lines. Interrupt line IRO is set to the highest priority and
I R7 to the lowest. Once an interrupt has been serviced it is automatically
assigned the lowest priority. That same input must then wait for the devices
ahead of it to be serviced before it can be acknowledged again. The Auto Rotate
Mode is selected by programming OCW2 in the following way (refer to Figure 3):
set Rotate Priority bit "R" to a logic "1";, program EOI to a logic ",1" and SEOI
to a logic "0." The EOI and SEOI commands are discussed further on. The
following is an example of the Auto Rotate Mode with devices requesting
interrupts on lines IR2 and IR5.
Before Interrupts are Serviced:

In-Service Register

Prior ity Status
Register

IS7

IS6

0

0

IS5

IS4

IS3

IS2

ISl

I I I I I I I
0

0

0

ISO
0

---I

Highest
Priority

IIR711R611R511R411R311R211Rl11RO

According to the Priority Status Register, IR2 has a higher priority than IR5 and
will be serviced first.
After Servicing:
IS7

In-Service Register

I0

IS6
0

IS5

IS4

IS:3

IS2

ISl

ISO

0

0

0

0

0

...

Highest
Pril)rity

Priority Status
Register
At the completion of IRts service routine the corresponding In-Service Register
bit, IS2 is reset to "0" by the preprogrammed EOI command, I R2 is then assigned
the lowest priority level in the Priority Status Register. The ILPD8259A is now
ready to service the next highest interrupt, which in this case, is I R5.
2. Specific Rotate Mode
The priorities are set by programming the lowest level through OCW2. The
ILPD8259A then automatically assigns the highest priority. If, for example, I R3 is
set to the lowest priority (bits L2, Ll, LO form 'the binary code of the bottom
priority level). then IR4 will be set to the highest priority. The Specific Rotate
Mode is selected by programming OCW2 in the following manner: set Rotate
Priority bit "R" to a logic "1," program EOI to a logic "0," SEOI to a logic "1"
and L2, Ll, LO to the lowest priority level. If EOI is set to a logic "1," the ISR
bit defined by L2, L 1, LO is reset.

652

OPERATIONAL COMMAND
WORDS (CONT.)

JLPD8259A

OPERATIONAL COMMAND
WORDS (CONT.)

END·OF-INTERRUPT (EOI) AND SPECIFIC END-OF-INTERRUPT (SEOI)
The End·of-Interrupt or Specific End·of-Interrupt command must be issued to reset the
appropriate In·Service Register bit before the completion of a service routine. Once the
ISR bit has been reset to logic "a," the IlPD8259A is ready to service the next interrupt.
Two types of EOls are available to clear the appropriate ISR bit depending on the
IlPD8259A's operating mode:
1. Non·Specific End-of·lnterrupt (EOI)
When operating in interrupt modes where the priority order of the interrupt inputs
is preserved (e.g., fully nested model. the particular ISR bit to be reset at the com·
pletion of the service routine can be determined. A non·specific EOI command
automatically resets the highest priority ISR bit of those set. The highest
priority ISR bit must necessarily be the interrupt being serviced and must necessarily be the service subroutine returned from.
2. Specific End-of-Interrupt (SEOI)
When operating in interrupt modes where the priority order of the interrupt
inputs is not preserved (e.g., rotating priority mode) the last serviced interrupt
level may not be known. In these modes a Specific End-of-Interrupt must be
issued to clear the ISR bit at the completion of the interrupt service routine.
The SEOI is programmed by setting the appropriate bits in OCW3 (Figure 2)
to logic "1"s. Both the EOI and SEOI bits of OCW3 must be set to a logic "1"
with L2, L 1. La forming the binary code of the ISR bit to be reset.
SPECIAL MASK MODE
Setting up an interrupt mask through the Interrupt Mask Register (refer to Interrupt
Mask Register section) by setting the appropriate bits in OCWl to a logic "1"
inhibits lower priority interrupts from being acknowledged. In applications requiring
that the lower priorities be enabled while the IMR is set. the Special Mask Mode can be
used. The SMM is programmed in OCW3 by setting the appropriate bits to a logic "1."
Once the SMM is set, the IlPD8259A remains in this mode until it is reset. The Special
Mask Mode does not affect the higher priority interrupts.
POLLED MODE
In Poll Mode the processor must be instructed to disable its interrupt input (tNT).
Interrupt service is initiated through software by a Poll Command. Poll Mode IS
programmed by setting the Poll Mode bit in OCW3 (P ; 1). during a WR pulse. The
following RD pulse is then considered as an interrupt acknowledge. If an interrupt
input is present, that R D pulse sets the appropriate ISR bit and reads the interrupt
priority level. Poll Mode is a one-time operation and must be programmed through
OCW3 before every read. The word strobed onto the Data bus during Poll Mode is of
the form:
D7

06

D5

D4

D3

D2

Dl

DO

I I I X I X I X I X I W2 I Wl I WO]
where: I ; 1 if there is an interrupt requesting service
= a if there are no interrupts
W2-0 forms the binary code of the highest priority
level of the interrupts requesting service
Poll Mode can be used when an interrupt service routine is common to several interrupt inputs. The IN-tA sequence is no longer required, thus saving in ROM space.
Poll Mode can also be used to expand the number of interrupts beyond 64.

653

II

IJ. PD8259A
INITIALIZATION COMMAND
WORD FORMAT

'cw,

1 1CW4 NI£DED

o· NO ICW. NEEOIO

1

OIl

o•

SINGLE
CASCADE MODE

CALL AOORUS INTERVAl.
1 • INTERVAL Of ..
0- INTERVAL OF'

1•

o-

LEVEL TRtGGEAEO MODE
EDGE _RED MODE

'CW>

Ian IMASTIR OIYtCEI

1 " .A INrOl "AS A SLAVI

' - - ' - - ' - - ' - - - ' ' - - - ' - - - ' - - ' - - - t 0" UI fWUT DOIS NOT HAVI
A SLAVE

,

ICW) 'SLAVI DEVIC(I

~

~

~

~

~

~

~

~

I I I I I I I,D, I,D, I,D, I
1

0

0

0

0

0

SLAV(10I1!

o , 1
o , 0
o 0 ,
o 0 o

J

,

•

0

S • ,
, o ,

,,
,,,

, 0 0
0 ,

t - MM'IOIIMODE
O-MCIHO/IllMOCE

,

/&UTO lOl

o " NOII"...i. 101

Efm
;1

M

. MJH BUFFEREO MODI

a

- aUfF[REO MODElS"",,!

1

- BUFFfRIDMOO(IMASTER

'-----------1

1 • SPECIAL FULLY NESTED

0 _

~SPECIAL FULl.Y
NESTED MODE

NOTE ,. SLAVE ID IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.

654

fLPD8259A
READING IlPD8259 STATUS

The following major registers' status is available to the processor by appropriately
formatting OCW3 and issuing RD command.

INTERRUPT REQUEST REGISTER (8-BITS)
The Interrupt Request Register stores the interrupt levels awaiting acknowledgement.
The highest priority in·service bit is reset once it has been acknowledged. (Note that
the Interrupt Mask Register has no effect on the IRR.) A WR command must be issued
with OCW3 prior to issuing the RD command. The bits which determine whether the
IRR and ISR are being read from are RIS and ERIS. To read contents of the IRR, ERIS
must be logic "1" and R IS a logic "0."

IN-SERVICE REGISTER (8-BITSI
The In-Service Register stores the priorities of the interrupt levels being serviced.
Assertion of an End-of-Interrupt (EOI) updates the ISR to the next priority level. A
WR command must be issued with OCW3 prior to issuing the R D command. Both ER IS
and R IS should be set to a logic "1."

INTERRUPT MASK REGISTER (8-BITS)
The Interrupt Mask Register holds mask data modifying interrupt levels. To read the
IMR status a WR pulse preceding the RD is not necessary. The IMR data is available to
the data bus when RD is asserted with AO at a logic "1."
A single OCW3 is sufficient to enable successive status reads providing it is of the same
register. A status read is over-ridden by the Poll Mode when bits P and ERIS of OCW3
are set to a logic" 1."

OPERATION COMMAND
WORD FORMAT

OCWI

L----'---L---'-----'---'---'--'--i

Ao
OCW2:

I

07

06

05

04

03

02

0,

I RI .EOII EOI I 0 I 0 I L2 I LI I

0

I

DO

La

1 = Corresponding bit in
IRR is masked.
0 ~ No mask present for
the corresponding
IAR bit.

BINARY lEVEL. TO BE RESET
OR PUT INTO LOWEST PRIORITY

j

23
OI
o I o I
o 0 I I

I L
I

4 5 6

I

,

I
I I
o 0 o 0 I I I I
NON-SPECIFIC END OF INTERRUPT
o

o

0 o

' .. R"et the High"' Priority

I o=~:~:!:
I SPECIFIC END OF INTERRUPT
' - L2. L.l. 4) Bits are u.d
l 0" No Action

I

I

I ROTATE PRIORITY
l ~: ::'~:tate
0,
OCW3:

I

0

0,

05

I -IESMMI'MMI

0

I I I piERI. I

R1S~
r Reed In·SlrviC* Registltf
0
0

0

I

I 0
I I
I

No Action
No Action
F1Md.!!! Reg. on
NlPt AD PUIM

A_,S Reg. on
NhtlfliPulte
Polling

A.d Binwv CadI of
HI......t Lew! Requlfting
Int.rupt Qf'I Next AD Pul..

101NoAc,...

t '....'..
0
0
1
1

0
1
0
1

_M. .

I
j

NoAc:lion
No Acteon
FInd If*:ill M.k
s.t:Specili Mnk

655

p.PD8259A

INSTRUCTION SET SUMMARY
SUMMARY OF 8259A INSTRUCTION SET

In....

Operation DelCrlptlon

ICWI

A

o

A7

A8

A5

o

ICWI

B

o

A7

A8

A5

1

=4, single, edge triggered

0

Format

1

0

Format = 4, single, level triggered

0
0

0
0
0

ICWI

C

A6

A5

o

ICWI

0

o
o

A7

4

A7

A8

A5

1

5
8
7
8

ICWI

E

o

A7

A6

0

o

1
0

ICWI

F

o

A7

A8

0

1

0

1

0

ICWI

G

A7

A6

0

o

0

0

0

ICWI

H

A7

A6

0

A7

A6

A5

o

A7

A6

A5

1

A7

A6

A5

o

1

A7

A6

A5

1

1

A7
A7

A6
A6

0

o

0

1

0

I

Format = 4, not single, edge triggered

Byte 1 Initialization

Format = 4, not single, level triggered
Format = 8, single, edge Iriggered

No ICW4 Requlrfld

Format = 8, single, level triggered
Format

=8, not olngle, edge trlggenod
=8, not olngte, le.el trlggenod

11

ICWI

12

ICWI

13
14

ICWI
ICWI

M
N

o
o
o
o
o
o
o

15

ICWI

0

o

A7

A6

0
0

16

ICWI

P

o

A7

A6

0

17

ICW2

18

ICW3

M

57

56

55

54

53

19

ICW3

5

o

0

0

0

0

20

ICW4

A

00000000

No action, redundant

21

ICW4

B

00000001

Non-buffered mode, no AEOI, 8086/8088

22

ICW4

C

0000000

Non-buffered mode, AEOI, 80/85

23

ICW4

0

00000011

Non-buffered mode, AEOI, 8086/8088

24

ICW4

E

o

No action, redundant

25

ICW4

F

0000001

26

ICW4

G

27

ICW4

H

o
o

28

ICW4

0000000

29

ICW4

0000001

30
31

ICW4

K

ICW4

L

32

ICW4

M

33

ICW4

N

34

0

35

ICW4
ICW4

38

ICW4

37

ICW4

38
39

10

656

Mnemonic

ICWI

I

ICWI

J

K

000

o

1

0

0

0

0

0

0
A8

Byte 2 initialization
Byte 3 Initialization -

ma.ter

52

51

SO
SO

Byte 3 Initialization -

.Ia ••

0

0

1

1

0

0

0

0

0

0

0

1

NA
NB

o

ICW4

NC

o

ICW.

NO

o
o
o

ICW4

NE

ICW4

NF

42

ICW4

NG

43

ICW4

NH

44

ICW4

NI

45

ICW4

NJ

46

ICW4

NK

47

ICW4

NL

48

ICW4

NM

o

49

ICW4

NN

o

50

ICW4

NO

51

ICW.

NP

52

OCWI

53

OCW2 E
OCW2 5E

56

OCW2 R5E

57

OCW2 R

58

OCW2 CR

59

OCW2 RS

60

OCW3 P

o
a
o
o

61

OCW3 RI5

o

Buffered mode, slave, AEOI, 80/85
Buffered mode, slave, AEOI, 8086/8088

0

0

0

1

Buffered mode, master, no AEOI, 80/85

0
0

o

Buffered mode, master, no AEOI, 8086/8088

0

0
0

0

0

0

0

0

o

0

Buffered mode, master AEOI, 8086, 8088

0

1

Fully nested mode, 8085A, non-buffered, no AEOI

o

0

0

0

0

0

0

0

0

o

0

0

0

0

0
0
0
0
0
0
0
0

o
o

0
0

Buffered mode, master, AEOI, 80/85

1

o

0
1

0

o
o
o
o

o

0

Ml

MO

0

0

Non--specific EOI

Ll

LO

Specific EOI, LO-L2 code of IS FF to be reset

0

0

Rotate on Non-5pecific EOI

L2

Ll

LO

0

0

0

0

0

0

0

0

0

1

0
0

0

o
o
o
o
o

0

uL2l1LO

o

o
1

0

0

0

0
0

0
0

ICW4 NF through ICW4 NP are Identical 10
ICW4 F through tCW4 P with the addition of
Fully Nested Mode

1

1

o
o

Fully Nested-Mode, 80/85, non-buffered, no AEOI

1

M3

M5

ICW4 NB through ICW4 NO are identical to
ICW4 B through ICW4 0 with the addition of
Fully Nested Mode

0

1

M6

}

1

M4

M7

0

Buffered mode, slave, no AEOI, 8086/8088

0

o
o

OCW2 RE

Buffered mode, slave, no AEOI, 80/85

0

o
o
o
o

54

Non-buffered mode, AEOI, 8086/8088

0

o

55

Non-buffered mode, AEOI, 80/85

1

0

40

Non-buffered mode, no AEOI, 8086/8088

0

0

41

=
=8, olngle, le.el triggered
Format =8, not olngle, edge trigger.d
Format =8, not Single, level triggered

51

o
o
o
o
o
o
o

P

Format = 4, not ,Ingle, 1...1 triggered
Format 8, olngle, edge triggered

Format

52

0

0

Format = 4, 'ingle, edge trlggenod
Format = 4, oingle, level trlggenod
Format = 4, not ,Ingle, edge trlggenod

A9

0
0

ICW4 Required

0

o

A15 AU A13 A12 All Al0

0

}

Byte 1 Initialization

0

Format

1
M2
L2

0

1

0

o

0

0

Load mask register, read mark register

Rotate on 5pecific EOI LO-L2 code of line
Rotate in Auto EOI (set)
Rotate in Auto EO I (clear)

Set Priority Command
Poll mode

Read IS register

fLPD8259A
SUMMARY OF OPERATION
COMMAND WORD
PROGRAMMING

AO

,

OCW,
OCW2

04

03

X

X

0

0

IMR (Interrupt Mask Registerl WR loads IMR data \fVhile

M7"MO

0

AD reads status

R

SEOI

EOI

0

0

0

0

,

No Action

0

0

No Action

,
,

0
0

,

,
,
, ,
, ,
0

0

OCW3

0

0

,

No Action

0

Rotate Priority, L2. L1, LO specifies bottom priority without
End-at-Interrupt

Rotate Priority at End-af·lnterrupt (Auto Mode)

,

ESMM

SMM

0

0

Rotate Priority at End-af-Interrupt (Specific Model. l2. L,. LO

,
,

0

,
,

Special Mask not affected
Reset Special Mask

0

ERIS

RIS

0

0

Set Special Mask

,
,

0

,

No Action

0

,
LOWER MEMORY
INTERRUPT VECTOR
ADDRESS

Specific-EncJ.of·lnterrupt L2. L1, LO forms binary representation
of level to be reset.

specifies bottom priority, and its In-Service Register bit is reset.

,

0

Non-Specific End-af-Interrupt

Read IR Register Status

Read IS Register Status

INTERVAL·4

I 07

Os

05

A7

As
As
As
As
As
As
As
As

A5

IR7

IR6

A7

I

IR5

A7

IR4

A7

IR3

A7

IR2

A7

IR,

A7

IRO

A7

A5
A5
A5
A5

INTERVAL - 8
0,

DO

07

Os

0

0

A7

0

0

A7

0

0

A7

As
As
As

0

0

0

A7

AS

0

0

A7

As

0

0

0

A7

AS

0

0

0

A7

0

0

A7

As
As

, , ,
, ,
,
,
,
, ,
,
,

04

03

02

0

0
0

0

A5

0

A5

0

0

A5

0

0

0

, , ,
, ,
,
,
,
, ,
,
,

02

0,

DO

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

05

03

04

0

0
0

0

FIGURE 4
Note: Insure that the processor's interrupt input is disabled during the execution of any control command and
initialization sequence for all J.l.PD8259As.
""'OCESSOR ADDRESS BuSII61

I

.... OCESSOR CONTROL 8US

",0

"'OCESSOROATA BuS 181

--

-- --- --- --

--,"

"

"

------- - - --

-

CA50

"P08259"
ISlAVE

CASI

~

C"l

iP

IR

IR

'R

,R

'R

OR

'R

'R

111111111

f-I-I--

-

r--

-

u

~
,"

"

"

"P08259A

,in
CASI

(SlAVEIl

CA52

fF

IR

'R

IA

IR

IR

IR

IR'R

Itltt!!11

"

'"'

"0

CASO

"P08259"

CAS I

'MASTERI

,~,

w
S;

'R

'R

,R

IR

IR

'R

lR

'R

111111
657

II

PD8259A

H~~~·'
'--'nF~~
F~
~
~
I-- -

B

----

:C'

E

~I--D

PACKAGE
J,lPD8259AgUTLINE

'

' G

0 0 _15 0

J,lPD8259AD

-;!-M

658

8259ADS-12-80-CAT

NEe

NEe Microcomputers, Inc.

fLPD8279·5

PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
DESCR IPTION

The ~PD8279-5 is a programmable keyboard and display Input/Output device. It
provides the user with the ability to display data on alphanumeric segment displays
or simple indicators. The display RAM can be programmed as 16 x 8 or a dual
16 x 4 and loaded or read by the host processor. The display can be loaded with
right or left entry with an auto-increment of the display RAM address.
The keyboard interface provides a scanned signal to a 64 contact key matrix expandable to 128. General sensors or strobed keys may also be used_ Keystrokes are stored
in an 8 character FIFO and can be either 2 key lockout or N key rollover. Keyboard
entries generate an interrupt to the processor.

FEATURES

• Programmable by Processor
•

32 HEX or 16 Alphanumeric Displays

•

64 Expandable to 128 Keyboard

•

Simultaneous Keyboard and Display

•

8 Character Keyboard - FIFO

•

2 Key Lockout or N Key Rollover

•

Contact Debounce

•

Programmable Scan Timer

•

Interrupt on Key Entry

•

Single +5 'i/olt Supply, ±10%

• Fully Compatible with 8080A, 8085A, ~PD780 (ZOOTM)
•

PIN CONFIGURATION

Available in 40 Pin Plastic Package
PIN NAMES

RL2
RL3
CLK

VCC
RL1
RLo
CNTL/STB
SHIFT

IRQ
RL4
RLS
RLS
RL7
RESET
RD
WR
DBO
DB1
DB2

~PD

8279-5

SL3
SL2
SL1
SLO
OUT BO
OUT B1
OUTB2
OUT B3
OUT -AO
OUTA1
OUT A2
OUT A3

DB3
DB4
DBS
DBS
DB7
VSS

OBO·7
ClK

Data Bus (Si-directional)
Clock Input

RESET

Reset Input

CS

Chip Select

RO

Read Input

WR

Write Input

AO
IRQ

Buffer Address

SlO-3

Scan Unes

RlO-7
SHIFT

Shift Input

CNTllSTS

Control/Strobe Input

OUT A0-3

Display (AI Outputs

Interrupt Request Output

Return Lil')es

OUT S0-3

Display (BI Outputs

1m

Bland Display Output

So

CS
AO

TM: Z80 is a registered trademark of Zilog.

Rev/1

659

II

fLPD8279.S
The /.lPD8279-5 has two basic functions: 1) to control displays to output and 2) to
control a keyboard for input. Its specific purpose is to unburden the host processor
from monitoring keys and refreshing displays. The /.lPD8279-5 is designed to directly
interface the microprocessor bus. The microprocessor must program the operating
mode to the /.lPD8279-5, these modes are as follows:

FUNCTIONAL
DESCRIPTION

Output Modes
• 8 or 16 Character Display
• Right or Left Entry
Input Modes
• Scanned Keyboard with Encoded 8 x 8 x 4 Key Format or Decoded 4 x 8 x 8
Scan Lines.
• Scanned Sensor Matrix with Encoded 8 x 8 or Decoded 4 x 8 Scan Lines.
• Strobed Input.

BLOCK DIAGRAM
elK RESET

OUT AO_3

OUT 80-3

08 0_7

IRO

SLO_J
CNTLlSTB

...... OOC to +70°C
Operating Temperature
. _65°C to +125°C
Storage Temperature . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .. -0.5 to +7 Voltso_--------I_--------- osc

F/O'-__._-I ~>o-----------_l~1I:

EF'---=========:[y.
~YNC------------------------------------~----~----~

1-------00_

ABSOLUTE MAXIMUM
RATINGS*

READY

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . -65°C to +150o C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
*Ta = 25°C

DC CHARACTERISTICS

Conditions: Ta = O°C to 70D C; VCC = 5V ± 10%
PARAMETER
Forward Input Current
Reverse Input Current
Input Forward Clamp Voltage

SYMBOL

TEST
CONDITIONS

MAX

UNIT

IF

-0.5

mA

VF = 0.45V

IR

50

JJ.A

VR = 5.25V

Vc

-1.0

'V

IC=-5 mA

Power Supply Current

ICC

Input low Voltage

VIL

MIN

140
0.8

Input High Voltage

VIH

2.0

Reset Input High Voltage

VIHR

2.6

Output low Voltage

VOL

Output High Voltage ClK
Other Outputs

VOH

RES Input Hysteresis

VIHR,VllR

rnA
V

VCC= 5.0V

V

VCC= 5.0V

V

VCC = 5.0V

V

5 rnA =IOl

4
2.4

V
V

-1 rnA}
-1 rnA IOH

0.25

V

VCC= 5.0V

0.45

675

,.,.PB8284
The clock generator can provide the system clock from either a crystal or an external
TTL source. There is an internal divide by three counter which receives its input from
either the crystal or TTL source (EFI Pin) depending on the state of the F/Cinput
strapping. There is also a clear input (C SYNC) which is used for either inhibiting the
clock, or synchronizing it with an external event (or perhaps another clock generator
chip). Note that if the TTL input is used, the crystal oscillator section can still be used
for an independent clock source, using the OSC output.

FUNCTIONAL DESCRIPTION

For driving the MOS output level, there is a 33% duty cycle MOS output (ClK) for the
microprocessor, and a TTL output (PClK) with a 50% duty cycle for use as a peripheral
clock signal. This clock is at one half of the processor clock speed.
Reset timing is provided by a Schmitt Trigger input (RES) and a flip-flop to synchronize
the reset timing to the falling edge of ClK. Power-on reset is provided by a simple RC
circuit on the RES input.
There are two READY inputs, each with its own qualifier (AEN 1, AEN2). The unused
AEN signal should be tied low.
The READY logic in the 8284 synchronizes the RDY1 and RDY2 asynchronous inputs
to the processor clock to insure proper set up time, and to guarantee proper hold time
before clearing the ready signal.

x,

....L

1 - - - - osc

D

t - - - - ClK

~r3 TO'O pF

t - - - - PClK

X2

8284
VCC

r

~
t----RESET

RES
TANK

!
r - - - - - - - - - - - ---,
I
I

I
IL

l

[-~

1= _ _
'_

2..

lCT
Cap

*

CT

*

I

_ _ _ _ _ _ _ _ _ _ _ _ _ JI

The tank input to the oscillator allows the use of overtone mode crystals.
The tank circuit shunts the crystal's fundamental and high overtone frequencies and allows the third harmonic to oscillate. The external LC network is connected to the TAN K input and is AC coupled to ground.

676

I

USED WITH OVERTONE
CRYSTALS ONLY

TANK INSERT
CIRCUIT DIAGRAM

,.,. PB8284
AC CHARACTERISTICS
TIMING REQUIREMENTS
TEST

PARAMETER

SYMBOL

MIN

MAX

UNITS

CONDITIONS

External Frequency High Time

TEHEL

20

ns

90%-90% VIN

External Frequency Low Time

TELEH

20

ns

10%-10% V IN

EFI Period

TELEL

ns

(j)

TEHEL + TELEH +

lj

12

XTAL Frequency

25

MHz

ROY1, RDY2 Set-Up to elK

TR1VCL

35

ns

ROY1, RDY2 Hold to elK

TCLR1X

0

ns

AEN1, AEN2 Set-Up to ROY1, RDY2

TA1VR1V

15

ns

AEN1, AEN2 Hold to elK

TCLA1X

0

ns

CSYNC Set-Up to EFt

TYHEH

20

ns

CSYNC Hold to EFt

TEHYL

20

ns

CSYNCWidth

TVHYL

2 TELEL

ns

RES Set-Up to elK

TllHCL

65

ns

RES Hold to elK

TCLI1H

20

ns

@
@

TIMING RESPONSES

PARAMETER

SYMBOL

MIN

MAX

UNITS

TEST
CONDITIDNS

elK Cycle Period

TCLCL

elK High Time

TCHCL

11/3 TCLCL) +2.0

ns
ns

Figure 3 and Figure 4

elK Low Time

TCLCH

12/3 TCLCL) -15.0

ns

Figure 3 and Figure 4

elK Rise and Fall Time

TCH1CH2
TCL2CL1

ns

1.0V to 3.5V

PCLK High Time

TPHPL

TCLCL -20

ns

PCLK Low Time

TPLPH

TCLCL -20

Ready Inactive to

elK

Ready Active to elK

125

10

~

TRYLCL

-8

ns
ns

Figure 5 and Figure 6

@

TRYHCH

12/3 TCLCL) -15.0

ns

Figure 5 and Figure 6

elK To Reset Delay

TCLIL

40

ns

CLK to PCLK High Delay

TCLPH

22

ns

eLK to PClK low Delay

TCLPL

22

ns

OSC to CLK High Delay

TOLCH

-5

12

ns

OSC to ClK low Delay

TOLCL

2

20

ns

Notes:

CD

8 = EFI rise (5 ns max) + EFI fall (5 ns max).
Set up and hold only necessary to guarantee recognition at next clock.
3 Appl ies only to T3 and TW states.
4 Applies only to T2 states.

~
TIMING WAVEFORMS*

____~r-------------~"-mt=
+ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.

677

Jl.PB8284
AC TEST CIRCUITS
FIC

~PF

Xl

24MHzc:::J

"

FIGURE 2
CLOCK HIGH AND lOW TI ME

FIGURE 1
CLOCK HIGH AND lOW TIME

FIGURE 4
READY TO ClK

FIGURE 3
READYTO ClK

LOAD

TEST
POINT

Vce
ALL DIODES 1N3064
OR EQUIVALENT

800n

OUTPUT
NOTES, 

COMMAND
BUS

DTIR
5 ALE

MN!MX

,\,-33
TO STB OF ,uPB8282/B283 L ATCH
TO T OF j,lPB8286/8287 TR ANSCE1VER
TO OE OF IlPB8286/8287 T RANSCEIVER

ABSOLUTE MAXIMUM
RATINGS*

OPERATING TEMPERATURE ..
Storage Temperatu re . . . . . . . . . .
All Output and Supply Voltages G? .
All Input Voltages 0
Power Dissipation . . . . . . . . .

.... oOe to 70°C

-65°C to +150 o e
. . -O.5V to +7V
. -l.OV to +5.5V
........ 1.5W

Note:Q)With Respect to Ground.
COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

689

E1

ILPB8288
The three status lines (SO, 51, 52) from the IlPD8086 CPU are decoded by the command
logic to determine which command is to be issued. The following chart shows the
decoding:
I'PD8086 Stat.

0

0

0

0

0

1

0

1
0

0
0
0

0
0

j£PB8288 Command

Interrupt Acknowledge

INTA

Read I/O Port

iORc

Writa I/O Port

lOWe,

Halt

None

Code Access

Mmsc

Ai"OWC

Read Memory

~

Write Memorv

"MW'i"C, AMWC

Passive

None

There are two ways the command is issued depending on the mode of the IlPB8288.
The I/O bus mode is enabled if the lOB pin is pulled high. In this mode, all I/O com·
mand lines are always enabled and not dependent upon AEN. When the processor
sends out an I/O command, the IlPB8288 activates the command lines using P5EN
and DT/A to control any bus transceivers.
This mode is advantageous if I/O or peripherals dedicated to one microprocessor
a're in a multiprocessor system, allowing the IlPB8288 to control two external buses.
No waiting is required when the CPU needs access to the I/O bus, as an i l l low
signal is needed to gain normal memory access.
If the lOB pin is tied to ground, the IlPB8~s in the system bus mode. In this mode,
commanu signals are dependent upon the AEN line. Thus the command lines are
activated 105 ns after the
line goes low. In this mode, there must be some
bus arbitration logic to toggle the A'EN line when the bus is free for use. Here,
both memory and I/O are shared by more than one processor, over one bus, with
both memory and I/O commands waiting for bus arbitration.

m

Among the command outputs are some advanced write commands which are initiated
early in the machine cycle and can be used to prevent the CPU from entering
unnecessary wait states.
The ii\i'TA signal acts as an I/O read during an interrupt cycle. This is to signal the
interrupting device that its interrupt is ceing acknowledged, and to place the interrupt
vector on the data bus.
The control outputs of the ,(lPB8288 are used to control the bus transceivers in a system,
DT/R determines the direction of the data transfer, and DEN is used to enable the
outputs of the transceiver. In the lOB mode the MCE/Pi5Eiii' pin acts as a dedicated
data enable signal for the I/O bus.
The MCE signal is used in conjunction with an interrupt acknowledge cycle to control
the cascade address when more than one interrupt controller (such as a IlPD8259AI is
used. If there is only one interrupt controller in a system, MCE is not used as the
INTA signal gates the interrupt vector onto the processor bus. In multiple interrupt
controller systems, MCE is used to gate the IlPD8259A's cascade add reS's onto the
processors local bus, where ALE strobes it into the address latches. This occurs during
the first 11iITA cycle. During the second iN'I'A cycle the addressed slave IlPD8259A gates
its interrupt vector onto the processor bus.
The ALE signal occurs during each machine cycle and is used to strobe data into
the address latches and to strobe the status (SO,
S2) into the ,uPB8288, ALE also
occurs during a halt state to accomplish this,

m-,

The CEN (Command Enable) is uSeO to control the command lines. If pulled high the
IlPB8288 functions normally and if grounded all command lines are inactive.

690

FUNCTIONAL
DESCRIPTION

JLPB8288
DC CHARACTE RISTICS

Vcc = 5V ± 10%, Ta = O·C to 70°C
SYMBOL

PARAMETER

MAX

TEST CONOITIONS

UNIT

Vc

-1

V

Power Supply Current

ICC

230

mA

Forward Input Current

'F

-0.7

mA

VF = 0.45V

'R

50

~A

VR = VCC

Reverse Input Current

Output Low Voltage - Command Outputs
Control OutputS

AC CHARACTERISTICS

MIN

Input Clamp Voltage

0.5
0.5

VOL

Output High Voltage - Command Outputs
Control Outputs

VOH

Input Low Voltage

V,L

Input High Voltage

V,H

Output Off Current

IOFF

2.4
2.4

Ic=-5mA

V
V

IOL = 32 mA
'OL=16mA

V
V

'OH=-5mA
IOH =-1 mA

V

0.8

V

2,0

~A

100

VOFF = 0.4 to 5.25V

VCC= 5V ± 10%, Ta= o"Ct070°C
TIMING REOUIREMENTS
SYMBOL

MIN

elK Cycle Period

PARAMETER

TCLCL

125

ns

MAX

UNIT

elK Low Time

TCLCH

66

ns

eLK High Time

TCHCL

40

ns

Status Active Setup Time

TSVCH

65

ns

Status Active Hold Time

TCHSV

10

ns

Status Inactive Setup Time

TSHCL

55

ns

Status Inactive Hold Time

TCLSH

10

ns

LOADING

TIMING RESPONSES
MIN

MAX

UNIT

Control Active Delay

TCVNV

5

45

ns

Control Inactive Delay

TCVNX

10

45

ns

ALE MCE Active Delay (from elK)

TCLLH, TCLMCH

15

ns

ALE MCE Active Delsy (from Status)

TSVLH, TSVMCH

15

ns

ALE Inactive Delay

TCHLL

15

ns

Command Active DelaY

TCLML

10

35

n.

Command Inactive Delay

TCLMH

10

35

n.

Direction Control Active Delay

TCHDTL

PARAMETER

SYMBOL

50

n.

Direction Control Inactive Delay

TCHDTH

30

n.

Command Enable Time

TAELCH

40

n.

Command Disable Time

TAEHCZ

Enable Delay Time

TAELCV

AEN to OEN

40

n.

275

n.

TAEVNV

20

ns

CEN to DEN, PDEN

TCEVNV

20

ns

CEN to Command

TCELRH

105

TCLML

LOAOING

~"
IORC

~

iOWC

}

IOl'" 32 mA

IOH'" -SmA

iNfA

CL = 300 pF

AMWC

AiOWC
Other

j

I

IOL= 1SmA
IOH=-1 mA

CL

=

80 pF

ns

691

JLPB8288
STATE _ T ,

T,

T2

ClK

--1
TCHSV....

~

~

\

-4TSVCH TCHCl

SH"
TCLS

Lr
-1

I-

TCllH"

Y
P

i+

f\
"---.J

.'--

-TSHCl

f i

I\.

X~lX
~

ADDRESS/DATA

TIMING WAVEFORMS

T,_

T3

r-'lI-TClCH
( \ I--TCLCl=~

WRITE
DATA VALID

CD

!.-TCHll

tlH

ALE

(i)

MFi'i5C, i'6'A'C, iNfA
AMWC, Ai'5WC

TClMH"

TClMl ....

}

....

(READ I
(lNTA)

TCLML

!*-TCVNV

~

DEN

00-

J
TCVNX ..

I

.

l-

t- TCVNV

DEN (WRITE I

1"---TCVNX'"

P'i5'EiiJ'

TC~D2H~
DT/A{READ I

~

V--

(WRITE I

---

t-

~1

1-'

Ii 11G)

MCE

TCLMCH"'I

~

..

Ir--TCHDTl

TCHOTH

~

I-

r-TCVNX

TSVMCH

NOTES:

o

ADDRESS/DATA BUS IS SHOWN ONl Y FDA REFERENCE PURPOSES.

® ~~~~I~~ ~~:~~~~L:U~~~~~E ~~~I~TE~~~II~~~:;RT~~;U~LSL~~~T.

® ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS SPECIFIED
OTHERWISE.

DEN, PDEN QUALIFICATION
TIMING

:::

rr-----+---t- -

·~--+-TAEVNV§j.

DEN _ _ _

PDEN

692

~TCEVNV

------------------------

_ _

/-LPB8288
IlPB8288 ADDRESS ENABLE
(AEN) TIMING
(3-STATE ENABLE/DISABLE)

AEN

OUTPUT
COMMAND

CEN ______________________

TEST LOAD CIRCUITS

~

1.5V

OUT

i

I"on
"0 "

3-STATE TO HIGH

1.5V

OUT

~

""

roo "

3-STATE TO LOW

3-STATE COMMAND OUTPUT
TEST LOAD

2.14V

J

52.7n

OUT~

I

300 pF

COMMAND OUTPUT
TEST LOAD

2.2BV

1114n

OUT~

I

BO pF

~

CONTROL OUTPUT
TEST LOAD

693

},PB8288

r-

PACKAGE 0
/lPB8288C UTLINES

-I
H-L~TT
TI:
:.:
i
B~
,~
A

r:C

I '

E

__ F::j
U~

J

0

Hi~TT
~,=I
IF
.lJ~l'
!!=i1
r:=
J L: ¥
': j
\_

A

--I C I--

694

-..1'-E- 0

_\

F

.I~

5

K

M 0_15 0

8288DS-9-80-CAT

NEe

NEe Microcomputers, Inc.

fLPD8355
fLPD8755A
16,384 BIT ROM WITH 1/0 PORTS
16,384 BIT EPROM WITH 1/0 PORTS·

DESCR I PTION

F EA TU R ES

The IlPD8355 and the IlPD8755A are IlPD8085A Family components. The IlPD8355
contains 2048 x 8 bits of mask ROM and the IlPD8755A contains 2048 x 8 bits of
mask EPROM for program development. Both components also contain two general
purpose 8-bit I/O ports. They are housed in 40 pin packages, are designed to directly
interface to the IlPD8085A, and are pin-for-pin compatible with each other.

• 2048 X 8 Bits Mask ROM (IlPD8355)
•
•
•
•
•
•
•
•

PIN CONFIGURATIONS

2048 X 8 Bits Mask EPROM (IlPD8755A)
2 Programmable I/O Ports
Single Power Supplies: +5V
Directly Interfaces to the IlPD8085A
Pin for Pin Compatible
IlPD8755A: UV Erasable and Electrically Programmable
IlPD8335 Available in Plastic Package
~PD8755A Available in Ceramic Package

CE
CE
ClK
RESET
NC
READY
101M

loR
AD
lOW
ALE
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
VSS

I'PD
8355

VCC
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBo
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
AlO
Ag
AS

CE
CE
ClK
RESET
VDD
READY
101M

lOR
RD
lOW
ALE
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
VSS

PPD
8755A

VCC
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBo
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
Al0
Ag
AS

NC: Not Connected

695

EJ

fLPD835518755A

The tLPD8355 and tLPD8755A contain 16,384 bits of mask ROM and EPROM
respectively, organized as 2048 X 8. The 2048 word memory location may be
selected anywhere within the 64K memory space by using the upper 5 bits of
address from the tLPD8085A as a ch ip select.

FUNCTIONAL DESCRIPTION

The two general purpose I/O ports may be programmed input or output at any
time. Upon power up, they will be reset to the input mode.
voo

;t

ffi...
~

~

5

.'"
z

:J

TO J1·J5

t.>

Z

'""
8'"

MULTIBUS
INTERRUPT

INTERRUPT
STATUS
REGISTERS

INTERFACE

-'
0

'"~

5

...z
a:

'""

0
t.>

""

ADRO/· ADR7/

DATA
BUS
BUFFER

OATO/·OAT7/

IORC/lowel

708

BP-0575-12-Bo.CAT

NEe Microcomputers, Inc.

BP-2190

Floppy Disk Controller/RAM
STANDARD FEATURES
The BP-2190 is a complete floppy disk controller
with on-board RAM and the following features:
• Occupies a single card slot
• Handles up to four double-sided standard 8"
or three mini 5%" floppy disk drives
• Drives may be a mixture of single- or doubledensity types (software programmable)
• IBM compatible soft-sector recording format
in both single- and double-density modes
• Performs fifteen different READ, SCAN,
WRITE, FORMAT, SEEK, SENSE and
SPECIFY commands with minimal processor
overhead
• 48K x 8 of on-board, automatically refreshed
dynamic RAM

~

~

• Dual-ported memory allows direct DMA data
transfers to/from disk without processor
intervention
• On-board priority logic arbitrates simultaneous
memory accesses by disk, system bus or
refresh logic
DESCRIPTION
The NEC Microcomputers BP-2190 Floppy Disk
Controller/RAM is a dual-purpose board. It combines a floppy disk controller (FDC) capable of
controlling up to four 8" standard or three 5%"
mini-floppy disk drives with up to 48 kilobytes of
dual-ported RAM. Dual-porting makes the RAM
available both to the disk for DMA data transfers
and to the host processor for data storage and program execution. The BP-2190 can be paired with
any compatible single-board computer to make a
very powerful two-board, floppy disk based
computer system.

,..

...

!~

709

BP-2190
With on-board RAM and all necessary Direct Memory Access Control (DMAC) logic, the BP-2190 is a
complete interface between the drives and any
Multibus™ single-board computer system_ It provides a powerful facility for the control of disk
data transfers, and many of its features have been
included specifically to minimize processor overhead. All disk data transfers are under control of
the FDC (MPD765) and DMAC (MPD8257) and are
independent of the processor. Once a disk transfer
has been requested by the processor, the F DC and
DMAC work together to obtain the proper data
and transfer it to/from the on-board memory
through one of its dual ports. When the transfer is
complete, the F DC notifies the processor by generating an interrupt.
A single READ or WRITE command allows the
transfer of a single sector, multiple sectors, an
entire track or even an entire cylinder's worth of
data (one track on both sides of the diskette).
READ and WR ITE operations may be performed
on normal and/or deleted data fields.
Execution of a FORMAT A TRACK command
allows an entire track to be formatted in one diskette revolution. The FDC supplies all information
for formatting in either single- or double-density,
except for 4 bytes in each I D field. The DMA controller fetches these 4 bytes/sector, thus allowing
the user to have non-sequential numbered sectors.
SEEK and RECALIBRATE operations can occur
on up to four drives simultaneously.
Between F DC commands trom the processor, the
BP-2190 automatically polls all drive Ready lines;
if one changes state (usually due to a door openjng
or closing), the BP-2190 notifies the processor via
an interrupt. This allows the processor to keep
track of which drives are on-line or off-I ine.
In addition to programmable selection of operating
mode, key time intervals are selectable under software control. Head load time (2 to 254 ms), head
unload time (16 to 240 ms) and stepping rate (1 to
16 ms) are programmable. For mini-floppies these
times are automatically doubled. Either singledensity (FM) or double-density (M FM), singtesided or double-sided reading/writing can be selected
under software control.
An on-board crystal-controlled oscillator is the
master clock for all board timing requirements.
The data recovery circuit, which separates raw data
into Data Window and RD Data signals, is capable
of handling wide peak shift variations. Precompensation circuitry is also employed during doubledensity recording in order to improve performance.

710

OPTIONS
The BP-2190's powerful jumper option structure
accommodates most floppy disk drives on the
market. Along with the standard features, the BP2190's on-board jumpers allow selection of:
• Standard or Mini-Floppy Drives
• Internal or External Clock
• Generate/Receive/Ignore Bus Clock
•
•
•
•
•

Memory Bank Base Addresses
FDC I/O Port Base Address
Memory Protect/Disable
Interrupt Line (1 of 9)
Reset at Power-Up, by Software Command or
External Switch Closure

• XACK/ and/or AACK/ Acknowledgements
In addition, four radial HEAD LOAD signals are
provided, as are four general-purpose software controlled output lines useful for controlling minifloppy motors, Drive-I n-Use lights, door locks, etc.'
ON-BOARD MEMORY
The on-board memory is implemented with NEC
MPD416 dynamic RAMs. Its dual-port architecture
allows either disk data transfers to take place under
DMA control, or for the host processor to have
access to the memory. All disk data transfers occur
between the drive and the on-board RAM.
Each of the three memory banks of 16K are base
address selectable at OOOOH, 4000H, 8000H or
COOOH. Facilities are provided to deselect the
entire memory either under hardware or software
control. This feature is especially useful when
system initialization ROMs are required to have the
same base address as used by RAM.
RAM refresh logic is provided, as well as priority
circuits which arbitrate simultaneous disk, bus and/
or refresh memory access requests.
SOFTWARE DISK DRIVERS
A complete set of I/O Driver routines is supplied
with the BP-2190 board. A complete, heavily commented source listing is provided in 8080 assembly
language so that the user can easily understand and
modify, if necessary, the software to fit his particular application.

TM: Multibus is a trademark of I ntel Corporation

BP-2190
BLOCK DIAGRAM
DATA BUS

I
N
T
E

I
I

ADDRESS

~ I
I

aus

A

i

I

RAM

I / l - - - ' CONTROL
BUS

I ncluded in the software routines are READ,
WRITE, FORMAT, SEEK, RECALIBRATE and
DRIVE STATUS commands. These commands
allow multiple sector READs and WR ITEs to occur
under DMA control. Drive-related parameters such
as head load time, head unload time, stepping rate,
drive number, etc., are set up or controlled via a
convenient I/O parameter block.
These software driver programs allow a first-time
user of floppy disk systems to get his BP-2190
board "on the air" in minimum time. The serious
OEM may wish to modify or to totally revamp the
supplied software, and the accompanying documentation makes this task easy to do.
PROGRAMMING
Eight I/O Ports (relocatable via jumpers) are
required to program the BP-2190. While most of
the instructions are very simple single-byte transfers, the DMA controller (,uPD8257) and the FDC
Controller (,uPD765) require multi-byte transfers
from the processor. These bytes may be supplied
in an asynchronous manner. However, once the
request for the disk transfer has been made, the
operations of loading the head, finding the proper
sector and transferring it to the on-board RAM
occur automatically with no processor intervention. After the disk transfer has been completed,
an interrupt is generated and the processor must
read out the results of the disk transfer. This
read-out is typically a multi-byte transfer.

OPERATION
Most floppy disk controller operations are performed in three stages: the Command Phase, the
Execution Phase and the Result Phase. Each command is initiated by a multi-byte transfer from the
processor, after which the BP-2190 executes the
command in true asynchronous fashion. It signals
completion of the command via an interrupt to
the processor, which then reads the information
presented in the F DC's Result Status registers.
As an example, the reading of a sector on one of
four drives into a specific block of on-board RAM
would involve the following:
PHASE

PROCESSOR
READ/WRITE
W
W

Command

W
W

FUNCTION OF
INSTRUCTION IS)

Specify memory starting address
and block length to DMA.
Specify a Sector Read, select
drive
Specify (current) track, head,

sector number and bytes/sector
Declare track's final sector
number and gap length

Head is loaded, specified sector
is located, data is recovered,
Execution

-

reassembled and written info
specified memory block - all
with no further intervention by

processor. -Completion is signaled by an interrupt.
R
Result
R

Read status registers to determine success of execution phase,
source of error if execution
failed.

Read post-p.xecution track, head
and sector numbers.

711

BP-2190
FDC STATUS REGISTERS
The FDC on the BP-2190 contains five status registers
which supply the processor with extensive information
about disk transfers. One of these, the Main Status Register, may be read by the processor at any time. It indicates
whether any of the FDDs are in Seek Mode (FDDO, 1,2
or 3 Busy), whether the FDC has a Read/Write operation
in process (FDC Busy), and whether the FDC is ready to
transfer commands from or results to the processor.
The other four status registers are only available after an
F DC operation has been completed. Three of these are
presented after each Read or Write operation and supply
detailed information on how the data transfer progressed.
The fourth indicates the condition of the FDD itself.

SPECIFICATIONS
Media
• Flexible diskette, 8" standard or 5%" mini
• One or two surfaces per diskette
• 77 tracks per surface (8"), 35 tracks per surface (5%")
• 128/256/512/1024/2048/4096 bytes per sector singledensity
• 256/512/1024/2048/4096/8192 bytes per sector
double-density
Transfer Rate: Rates are in kilobits per second
DIAMETER
DENSITY

COMMAND SUMMARY
Memory
• Memory Read (processor reads a single byte of data
frol1') memory)
• Memory Write (processor writes a single byte of data
into memory)
Disk
• Read Data
• Read Deleted Data

• Write Data
• Write Deleted Data

• Read Track

• Format Track

• Read ID

• Scan Equal
• Scan High or Equal

• Seek
• Scan Low or Equal
• Recalibrate
• Sense Interrupt Status

• Sense Drive Status
• Specify (Head Load and Unload Times, Step Rates)
• Set/Reset Auxiliary Outputs (e.g., Motor On/Off)

5:'4

8

Single

125

250

Double

250

500

Physical Characteristics
• Mounting - occupies one chassis or card cage slot
• Height-6.75 in (171.5mm)
• Width - 12.00 (304.8 mm)
• Depth - 0.5 in (12.7 mm)
DC Power Requirements
• +12V ± 5%; 150 mA
• +5V ± 5%; 1.3 Amps
• -5V ± 5%; 6 mA
Environment
• Operating: O°C to 50°C
• Non-operating: -55°C to +85°C
• Humidity - up to 90% RH, non-condensing
Documentation Supplied
• UM-2190 Users' Manual
DRIVES

I/O
• DMA Data Channel
• DMA RAM Refresh
Channel

• External Control
• FDC Status
• FDC Data

• DMA Mode
MUL TlBUS™ COMPATIBILITY
The BP-2190 is fully compatible with all mechanical and
electrical requirements of Intel iSBC™ and National
BLC Multibus™ systems. It will also operate as a loworder 8-bit slave on the expanded Multibus™ (such as
required by the 16-bit Intel iSBCTM 86/12). TheBP-2190
conforms to all Multibus™ voltage level, current level
and timing requirements, and is ready to plug in and run
as supplied.
TM: iSBC is a trademark of Intel Corporation

712

The BP-2190 directly interfaces with the following drives.
Other types may require modification or additional interface circuitry and/or software.
MANU·
FACTURER

8" FLOPPY
DRIVES

BASF

-

Caldisk

143M
550/552

MFE

500/700 Series

-

Persci

70,270,288

Pertee

FD5x4,FD650

Qume

6106.6108

-

Memorex
Micropolis

5.25" MINIFLOPPY DRIVES

1015·1.2,4;1016-2,4;

F D200 ,F D250

Datatrak·8

Siemens

FDD 200-8,100-8

FD200-5, FD100-5

Shugart Assoc.

SA800,850

SA400,SA450

NEe

NEe Quality Assurance
Procedures
One of the important factors
contributing to the final quality of
our memory and microcomputer
components is the attention

given to the parts during the
manufacturing process. All
Production Operations in N EC

follow the procedures of MI L
Standard 883A. Of particular
Visual

importance to the reliability
program are three areas that
demonstrate NEC's commitment
to the production of components

Inspection

Method
2010.2 Condo B

of the highest quality.
I. Burn·ln - All memory and
microcomputer products are

dynamically burned in at an
ambient temperature sufficient to
bring the junction to a temperature

of 1500 C. The duration of the
burn-in is periodically adjusted

to reflect the production history
and experience of N EC with each
product. 100% of all NEC memory
and microcomputer products
receive an operational burn-in

stress.
II. Electrical Test - Memory and
microcomputer testing at NEC is

not considered a statistical game
where the device is subjected to a

series of pseudo random address
and data patterns. Not only is this
unnecessarily time consuming,
but it does not effectively
eliminate weak or defective parts.

N EC's test procedures are based
on the internal physical and
electrical organization of each
device and are designed to
provide the maximum electrical
margin for solid board operation.
For further information on
NEe's testing procedures see your
local N EC representative.

III. After completion of all
100% test operations, production
lots are held in storage

until completion of two groups
of extended sample testing: an
operati ng life test and a series
of environmental tests. Upon

successful completion of
these tests, the parts are released
from storage and sent to final

,- --- -

A

-- ------

I

I
I

,I

•
I
I

I
I
I

A

L ______ --

Q.A. testing.

NEe Microcomputers, Inc.

III
713

NEe Microcomputers, Inc.

NEe

173 Worceste r Street
Wellesley, Massachusetts 02181
TeI61 7-237-1 910 TWX 710-383-1745

NEC REGIONAL SALES OFFICES
EASTERN REGION
275 Broadhollow Road , Route 110
Melville, NY 11747
TEL 516-293-5660
TWX 510-224-6090

MIDWESTERN REGION
5105 Tollview Drive, Suite 190
Rolling Meadows, IL 60008
TEL 312-577-9090
TWX 910-233:4332

NORTHEASTERN REGION
21-G Olympia Avenue
Woburn. MA 01801
TEL 617-935-6339
TWX 710-348-6515

NORTHWESTERN REGION
20480 Pacifica Drive , Suite E
Cupertino , CA 95014
TEL 408-446-0650

OHIO VA LLEY REGION
19675 West Ten Mile Road
Southfield , MI48075
TEL 313-352-3770

SOU TH WESTERN REGI ON
1940 West Orangewood Avenue , Suite 205
Orange, CA 92668
TEL 714-937-5244
TWX 910-593-1629
FAX 714-639-1100

SO UTH CENTRAL REGION
16475 Dallas Parkway, Suite 290
Dallas . TX 75248
TEL 214-931-0641

SOU THEASTERN REGION
Vantage Point Office Center, Su ite 209
4699 North Federal Highway
Pompano Beach, FL. 33064
TEL 205-785-8250

Price $3,00



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:05:25 16:27:41-08:00
Modify Date                     : 2013:05:25 16:59:17-07:00
Metadata Date                   : 2013:05:25 16:59:17-07:00
Producer                        : Adobe Acrobat 9.53 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:730c3966-7aa5-7f4d-8a2f-3a0a632673b4
Instance ID                     : uuid:7203952b-6c15-e24e-8502-91b93bb5f0ef
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 717