1981_Rockwell_Electronic_Devices_Division_Data_Book 1981 Rockwell Electronic Devices Division Data Book

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Electronic Devices Division

4j~ Rockwell
...
~ International
...where sc:ience gets down to business

'1'

Rockwell International

R6500
NMOS
p,Ps & p,Cs

R6500
I/O
DEVICES

R6500
MEMORY I/O
COMBOS

AIM 65
MICROCOMPUTER

RM 65
BOARD
PRODUCTS

Electronic Devices Division
Data Catalog

SYSTEM 65
DEVELOPMENT
SYSTEM

NMOS
MEMORY
PRODUCTS

R6S000
16-BIT p,P
PRODUCTS

PPS-4/1
PMOS p,Cs

INTEGRAL
MODEMS

TELECOM
DEVICES

FILTER
PRODUCTS

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TABLE OF CONTENTS
R6500 NMOS JLPS & JLCS
R6500 Brochure
R6500 CPUs
R6500/1 One-Chip Microcomputer
R6500/1 E Emulator Device
R6500/1 EB Backpack Emulator
R6500/1-11 One-Chip Microcomputer
R6500/1-11 Q One-Chip Microcomputer
R6500/2-11 Extended Microprocessor
R6500 I/O DEVICES
R6520 Peripheral Interface Adapter (PIA)
R6522 Versatile Interface Adapter (VIA)
R6545-1 CRT Controller (CRTC)
R6551 Asynchronous Communication Interface Adapter (ACIA)
R6592 Single-Chip Printer Controller
R6500 MEMORY-I/O COMBOS
R6530 ROM-RAM-I/O-Timer (RRIOT)
R6531 ROM-RAM-I/O-Counter (RRIOC)
R6532 RAM-I/O-Timer (RIOT)
AIM 65 MICROCOMPUTER
AIM 65 Brochure
AIM 65 Expansion Motherboard
AIM 65 PROM Programmer & CO-ED
Forth Language for AIM 65
PU65 Language for AIM 65
RM 65 BOARD PRODUCTS
RM 65 Brochure
Single Board Computer (SBC) Module
Floppy Disk Controller (FDC) Module
Asynchronous Communications Interface Adapter (ACIA) Module
General Purpose Input/Output (GPIO) & Timer Module
IEEE-488 Bus Interface Module
8K Static RAM Module
32K Dynamic RAM Module
16K PROM/ROM Module
Single-Card Adapter
Adapter/Buffer
Cable Driver Adapter/Buffer
DeSign Prototyping Module
Extender Module
4-Slot Piggyback Module Stack (PMS)
8-Slot Card Cage
16-Slot Card Cage
SYSTEM 65 DEVELOPMENT SYSTEM
System 65 Brochure
USER 65 Option Module
R6500/1 Evaluation Module
16K Static RAM Module
PROM Programmer Module
16K PROM/ROM Module
Design Prototyping Module
Extender Module
R6500 Macro Assembler and Linking Loader
PU65 Language for System 65

NMOS MEMORY PRODUCTS
R2316 2048 x 8 Static ROMs
R2332 4096 x 8 Static ROMs
R2332-xL 4096 x 8 Low-Power Static ROMs
R2364A 8192 x 8 Static ROMs
R2364B 8192 x 8 Static ROMs
R81 04/R8114 1024 x 8 Static RAMs
R68000 16-81T JLP PRODUCTS
R68000
R68120
R68451
R68450
R68561

Microprocessing Unit
Intelligent Peripheral Controller (IPC)
Memory Management Unit (MMU)
DMA Controller (DMAC)
Multi-Protocol Communications Controller (MPCC)

PPS-4/1 PMOS JLCS
PPS-4/1 Brochure
MM75 Microcomputer
MM76EL Low-Power Microcomputer
MM78 Microcomputer
MM78L Low-Power Microcomputer
MM78LA Low-Power Microcomputer
Serial Communication Protocol for Multiple PPS-4/1 Systems
Using PPS-4/1 to Operate a Liquid Crystal Display
INTEGRAL MODEMS
R24 2400 BPS Modular Modem
R24 DC 2400 BPS Direct Connect Modem
V96P/1 Multi-Configuration 9600 BPS Modem
TELECOM DEVICES
MaS/LSI Telecommunication Products Flyer
CRC8000,8001 Binary to Dial Pulse Dialer
CRC8030 Dual Tone Multi-Frequency Detector
R8040 T-1 Tri-Port Memory
R8050 T-1 Serial Transmitter
R8060 T-1 Serial Receiver
FILTER PRODUCTS
Rockwell-Collins Disc Wire Mechanical Filters
Collins Low Frequency Mechanical Filters
Collins USB-LSB-AM Mechanical Filters
F455FD Low-Cost Mechanical Filters
Disc Wire Mechanical Filters Standard Products
Low Frequency Narrowband Mechanical Filters Standard Products

Rasoo
MICROCOMPUTER SYSTEM

Printed in the U.S.A.

•

R6500 Family
A family of 10 software-compatible CPUs and 11 1/0,
ROM, RAM and one-chip memory-I/O-timer circuits
operating at proven 1 MHz and 2 MHz speeds with a
single 5V power supply, provides you with economic
system solutions for a broad range of applications.
The R6500/1 provides you with CPU, ROM, RAM,
interrupts, counter and bi-directional data ports on a
single chip. And it's totally software compatible with all
other members of the R6500 family.
The R6500 promises you boosted performance and
improved economics through its third generation architecture, which includes 13 powerful addressing modes,
and its innovative circuit design and processing technology which reduce chip size and power consumption.

Rockwell is solidly backing
the R6500
Rockwell has dedicated facilities for the high volume
manufacturing of R 6500 circuits produced with its
own depletion load, silicon-gate N-channel process.
And Rock\~/ell provides complete system development support: Rockwell's SYSTEM 65, a floppy-disk
based, powerful yet low-cost complete development
system. Plus AIM 65, TIM or timesharing program,
complete documentation and extensive applications
engineering support.

For the future, Rockwell is developing new R 6500
devices that will enhance your own product development opportunities.

I
Rockwell's R650X CPU options offer a selection of
features in 40- and 28-pin versions to meet your system
needs (see table below). The R6502 - R6507 Series has
on-chip clock generation. The R6512 - R6515 Series
allows the user to generate and control the clock
externally.

R6500 CPU Options

Why the R6500 is a
cost performance winner
- Proven 1 MHz or 2 MHz performance
- Pipeline architecture for fast operation with
fewer cycles
- Single 5-volt power supply
- On-the-chip clock or an external clock
- 56 instructions
- 13 addressing modes and true indexing capability
- Decimal/binary arithmetic mode selection
- Bi-directional Data Bus (compatible with the
MC6800)
- Addressable memory range up to 65K bytes
- Multi-level interrupts - maskable/non-maskable
- Use with any type or speed memory
- Programmable stack pointer and variable
length stack
- 40- and 28-pin DIP package options

40-Pin DIP
R6504
R6514

28-Pin DIP
R6505
R6515

R6506

R6502

R6512

R6503
R6513

Memory Address Space

65K

65K

4K

8K

4K

4K

8K

I nterrupts- Maskable
- Non-Maskable

Yes
Yes

Yes
Yes

Yes
Yes

Yes
No

Yes
No

Yes
No

No
No

SYNC-Output indicates
op code fetch cycle

Yes

Yes

No

No

No

No

No

RDY -Single step and slow
memory synchronization

Yes

Yes

No

No

Yes

No

Yes

0,

Yes

Yes

No

No

No

Yes

No

Clock Output

DBE - Extended Data
Bus Hold Time
No
Yes
The 40-pm versions proVide full functIOnal capability
for memory intensive systems with extensive I/O
requirements The 28-pin versions offer flexibility in

R6507

No
No
No
No
No
selectmg the lowest cost CPU best SUited to your
application 28-pin packages also provide denser
board layout.

. Thirteen addressing modes + true indexing = R6500 software power
The R 6500 features 13 addressing modes. The
first byte of each instruction is the operation code
specifying both the instruction and the addressing
mode. The addressing modes are summarized below
- ACCUMULATOR ADDRESSING - A one byte
instruction, operating on the accumulator.
-IMMEDIATE ADDRESSING - The operand is in
the second byte of the instruction.
- ABSOLUTE ADDRESSING - The second and
third bytes of the instruction specify the effective
address in 65K bytes of addressable memory.
- ZERO PAGE ADDRESSING - Allows shorter code
and execution times by assuming a zero page
address.
- INDEXED ZERO PAGE ADDRESSING eX or Y. indexing.) - Zero page addressing used with an index
register.

-INDEXED ABSOLUTE ADDRESSING eX or Y, indexing) - Absolute addressing used with X or Y
index registers.
-IMPLIED ADDRESSING - The register containing
the operand is implicitly stated in the operation code.
- RELATIVE ADDRESSING - Used only with branch
instructions. The second byte is an "Offset" added
to the contents of the program counter.
-INDEXED INDIRECT ADDRESSING - Uses an
indirect zero page address indexed by X to fetch
the effective address.
- INDIRECT INDEXED ADDRESSING - Uses a zero
page address to fetch the effective base address
to be indexed by Y.
• ABSOLUTE INDIRECT - Used only withJMP. the
second and third bytes point to a two-byte effective
address.

Execution Time (clock cycles)

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BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
eLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EOR

Exclusive OR·· Memory with Accumulator

•

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Y by One

··56-67-

JMP
JSR

Jumpto New Location
Jump to New Location saving Return Address

LOA
LOX
LOY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift Right One Bit (Memory or Accumulator)

NOP

No Operation

ORA

··OR·· Memory with Accumulator

PHA
PH P
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

ROL
ROR
RT!
RTS

Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from In:errupt
Return from Subroutine

20560670
20560670

SBC
SEC
SED
SEI
STA
STX
STY

Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory

0

TAX
TAY
TSX
TXA
TXS
TYA

Transfer Accumulator to I ndex X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Pointer
Transfer Index Y to Accumulator

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·AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

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Add one cycle if branch is taken. and one additional cycle if branching opera lion crosses page boundary

•
•

I
The R6500/1

R6500/1 Features

In the R6500/1 , Rockwell has combined the highperformance R6502 CPU with such versatile features as
2048 bytes of ROM, 64 bytes of RAM, 32 bi-directionall/O
lines, four interrupts and a 16-bit programmable counter
(with four separate interval/event modes) - all in a single
40-pin package.
The R6500/1 also has on-the-chip 1 MHz or 2 MHz clock
operation with external single clock, crystal or RC
frequency input.
The R6500/1 includes a separate power pin that maintains RAM on 10% of the operating power. In the event
power is lost, this standby power retains RAM data until
execution is resumed.
Rockwell backs up the R6500/1 with solid system
development support in two ways:
The R6500/1 E, a 64-pin emulator device with 40
pins electrically identical to the R6500/1 , may be used
for program development and prototyping with
external EPROM or RAM.
A Personality option to SYSTEM 65 customizes
Rockwell's popular microcomputer development system
for complete R6500/1 software and hardware
development.

•
•
•
•
•

2K-Byte Mask Programmable ROM
64-Byte Static RAM
R6502 CPU
Four 8-Bit Bidirectional 110 Ports
16-Bit Programmable Counter/Latch With Four Modes:
- Interval Timer
- Pulse Generator
- Event Counter
- Pulse Width Measurement
• Five Interrupts
• Fully UpwardlDownward Compatible With 5500 Family
• 54-Pin PROM-compatible Emulator Device Available

~

PORTS

•

The R6500 system bus enables you to use low cost,
widely available standard memory devices. For your convenience, Rockwell now offers the five memory devices.
described below. All are completely TTL compatible, fully
static - no clocks or refresh strobes required - and
operate from a single + 5 V power supply
• R21144KSTATIC RAM
1024 x 4 in high-density 18-pin package with common
data I/O; 450ns access and cycle time; fully static - no
clocks or strobes required; single + 5V power supply;
total TTL compatibility. (Industry standard.)

General·Purpose 1/0 Devices
These versatile peripheral controllers allow effective
trade-offs between software and hardware, enabling
implementation of complex R6500 microcomputer
systems at minimum overall cost. Both are available in
1 MHz and 2 MHz versions. All R6500 I/O devicesincluding the memory-I/O combos-have TTL and
CMOS compatible peripheral lines with transistor
drive capability and high-impedance, tri-state data
outputs.
• R6520 Peripheral Interface Adapter (PIA)
40-pin package, two 8c bit bi-directionall/O ports,
four peripheral control/interrupt input lines. fully
automatic data transfers between processor and
peripheral devices.

• R2316B 16K STATIC ROM
2048 x 8 in standard 24-pin package; pin-compatible
with 2708 EPROM; 450 ns. max. cycle time; three chip
selects. (Industry standard; replaces two 8K EPROMs.)
• R2332 32K STATIC ROM
The industry's first static 4096 x 8 N-channel ROM;
standard 24-pin package; 450 ns. max. cycle time;
two chip selects.
• R2332·3 32K STATIC ROM
Same as R2332, but has 300 ns. max. cycle time.

The PIA provides individual I/O line control for
keyboard strobes and returns, driving displays and
discrete indicators as well as 8-bit parallel communications in handshake or clocked control modes.
• R6522 Versatile Interface Adapter (VIA)
40-pin package, has R 6520 PIA features plus two
16-bit programmable interval timers/counters.
data latching on I/O ports, 8-bit buffered shift register for serial I/O interfacing.
The enhanced features of the VIA provide a serial
interface for inter-system communications, ASCII
serial data generation, pulse width modulation, and
waveform synthesis. The two timers work in conjunction with the serial channel or may prOVide interval timing for real time applications

Memory·I/O· Timer Combination
Devices
By combining an R650X Series CPU with one-ctlip
memory, I/O and timer combination devices, the designer
nets a powerful, cost-effective two chip microcomputer
system which can also be the base configuration for
modular, expandable applications.
• R6530 ROM·RAM-I/O·Timer(RRIOT}
40-pin package; 1 MHz operation; 1024 x 8 ROM; 64 x
8 static RAM: two 8-bit bi-directional data I/O ports:
two progammable data direction registers: programmable 8-bit interval timer with prescale and interrupt
control.
• R6531 ROM·RAM·I/O·Counter(RRIOC)
40-pin package: 1 MHz or 2 MHz operation: 2048 x 8
ROM: 128 x 8 static RAM: 8-bit serial data channel:
two bi-directionall/O ports, with a total of 15 data lines,
including four external interrupts and handshake
control.
The RRIOC also provides a fully-buffered 16-bit
counter/timer with four program s.electable modes interval timer, pulse generator, event counter and pulse
width measurement.

Intelligent Peripheral Controller
Devices
The devices listed below get your interface design off to
a solid start.
• R6541 Programmable Keyboard/Display Controller
(PKDC)
40-pin package, 8-character FIFO/Sensor RAM for
keyboard entries, two CPU-addressable 16-byte display
RAMs.
The PKDC is a general-purpose keyboard and segmented display interface device. The keyboard portion
can scan up to 128 matrix-type key switches, and can
also interface with an array of 64 sensors or a strobed
interface keyboard. The display portion provides a

Communications Interface Device
• R6551 Asynchronous Communication Interface
Adapter (ACIA)
28-pin package provides the interface between R6500based systems and serial communication data sets
and modems. With its on-chip baud rate generator, the

A separate 52-pin version of RRIOC offers expanded
I/O in additional 8-bit output port and 4-bit input port.
• R6532 RAM·I/O·Timer(RIOT}
40-pin package: 1 M Hz operation: 128 x 8 static RAM;
two 8-bit bi-directional data ports; two programmable
data direction registers: programmable 8-bit interval
timer with prescale and interrupt control: programmable edge detect interrupt, for fast service of critical
events.
• R6534 ROM·I/O·Counter (RIOC)
40-pin package: 1 MHz operation: 4096 x 8 ROM: 8-bit
serial data channel: two bi-directional data I/O ports,
with a total of 14 data lines, including four external
interrupts and handshake control.
The RIOC also provides a programmable 16-bit
counter/latch with interval timer, pulse generator and
event counter modes.
A separate 52-pin version of RIOC offers an
additional 8-bit output port, 3-bit input port and one
additional I/O line.

buffered scanned display interface with LED, fluorescent, Borroughs SELF-SCAN@ , and other display
technologies.
• R6545 CRT Controller (C RTC)
40-pin package, refresh RAM, fully-programmable
scanning and cursor, light pen register.
The CRTC is designed to interface an 8-bit microprocessor to CRT raster scan video displays. It provides
refresh memory addresses and character generator
row addresses, which allow up to 16K characters with
32 scan lines per character to be addressed. Refresh
memory may be addressed in either straight binary or
by row/column.

ACIA is capable of transm,itting at 15 different programselectable rates between 50 baud and 19,200 baud,
and receiving at 8ither the transmit rate or at 16X an
external clock rate.
The ACIA has programmable word lengths of 5,6, 7
or 8 bits; even, odd or no parity; 1, 1-1/2 or 2 stop bits.

..-••
s1'StlM65

rr•

Rockwell's SYSTEM 65
SYSTEM 65 is a new easy to use, powerful, complete development system for the R6500 family of
microcomputers. The basic configuration includes
'two built-in, mini-floppy disk drives, 16K bytes of user
memory and 16K bytes of resident operating system.
Monitor commands :He self-prompting whenever
memory, peripheral, or disk file assignment is required.
Text editor provides line, string, and character editing
functions. A resident two-pass assembler and dynamic
debug package complete the operating system. Both
source and object code may be maintained in memory
for fast editing, assembling, and checkout. Since the
total monitor, editor, debug and assembler are resident
in ROM, 100% of the disk storage and drive utilization
is available to the user.
The mini-floppy diskettes may be used as storage for
source and object code and documentation. Each
diskette has the capacity for 78K bytes of information
in a maximum of 60 files.
SYSTEM 65 supports a vareity of terminals with
serial data from 100 baud to 9600 baud. Connectors
are provided for both RS-232 C and current loop interfacing. Reader ONIOFF signals and RTSICTS control
signals are standard. Included is a parallel port providing automatic control to high speed printers, such as
Diablo, Centronics and Tally.

And Rockwell offers these options to
SYSTEM 65:
• PU65 High-Level Language
• USER 65 in-circuit emulation option
• PROM Programmer Module, for programming a
2704/2708/2716/2758 PROM device from the front
panel socket

• R6500/1 Personality option, for developing with the
R6500/1 single-chip microcomputer
• 16K x 8 Static RAM Modules
• PROMIROM Module, accepts 2316/2332 ROM or
2708/2716/2758 PROM devices
• Wire-wrap Design Prototyping Module
• Extender Card for circuit probing

PL/65 High·Level Language
A high-level language resembling PU1 and ALGOL
is now available to designers developing programs for
the R6500 microprocessor family using the SYSTEM 65
development system.
Designated PU65, the language is considerably
easier to use than assembly language or object code,
thus increasing programmer productivity while
reducing software development time and costs. The
PU65 compiler outputs source code to the SYSTEM
65's resident assembler. This permits enhancing
or debugging at the assembler level before object
code is generated. In addition, PU65 statements may
be mixed with assembly language instructions for
timing or code optimization.
The PU65 compiler is available to SYSTEM 65
users as a preprogrammed mini-floppy diskette. No
additional memory is required other than the standard 16K bytes of RAM.
The PU65 language supports modular program
design. Its general control structures for conditiohal
and iterative looping allow the language to be used
effectively for structured programs. Other language
features include: assignment, integer arithmetic, conditional execution, collective execution, linear array
manipulation, data area declaration and array initialization. Block structures, subscripts and parenthetical
expressions are also supported.

•

For learning, designing, work or just plain fun ....
Dual Cassette, TTY
and General-Purpose
I/O Interfaces

Dot Matrix
Printer

R6500
NMOS

Read/Write
RAM
Memory

20-Character
Alphanumeric
Display

PROM/ROM
Expansion
Sockets

Interactive
Monitor
Firmware

Rockwell's R6500 Advanced Interactive Microcomputer (AIM 65) can get you into the exciting world
of microcomputers a lot easier and at a lot lower cost
than you may have thought possible.
As a learning aid, AIM 65 gives you an assembled,
tested and warranted R6502-based microcomputer
system with a full-sized keyboard, an alphanumeric 20character display and, uniquely, an alphanumeric 20column thermal printer.
An on-board Advanced Interactive Monitor program
provides extensive control and program development

functions. You'" be writing your programs in assembly
language - there's no need to memorize "opcodes".
And for more specialized applications, we offer a twopass, symbolic assembler and a BASIC interpreter as
plug-in ROM options.
You'" master fundamentals rapidly. Then you'"
appreciate the fact that unlike the computer "toys" on
the market, AIM 65 offers flexibility and expandability
you would expect to find only in a sophisticated microcomputer development system.

I
How to make it all work for you
Rockwell has put together a complete set of
documentation and reference manuals to help you
implement the R6500 microprocessor family.

• R6500 Hardware Manual
A detailed description of each chip in the family,
how they interface, how the peripherals are controlled, as well as the design techniques facilitating
system operation, testing and maintenance. Special
emphasis is on "bringing up" a system with testing
techniques, scope synchronizing and general
trouble-shooting procedures - $5.
• R6500 Programming Manual
Defines the architecture of the R6500 Series, the
function of each instruction and valuable programming information. Special emphasis is on the sophisticated addressing modes of the family - $5.
• Cross·Assembler Manual
Cross-Assembler directives are described as used
in time-share and batch operations, with special aids
on understanding and resolving error messages
-$5.
• SYSTEM 65 User's Manual
Instructs the user in operating the SYSTEM 65
Microcomputer Development System and its application in developing a working microprocessor
system -$5.

• PU65 User's Manual
A complete guide to PLl65, the high-level language
for the R6500 family - $10.
• AIM 65 User's Guide
Full technical details tell you everything you need to
operate the AIM 65 - $5.
• AIM 65 BASIC Language Reference Manual
A how-to guide for using AIM 65 with the BASIC
language ROM option installed-$5.
• TIM Manual
Defines how to apply the Teletype 1/0 Monitor - $2.
• R6500 Data Sheets
Provides quick understanding of the capabilities
and characteristics of each available R6500 device
and support equipment. To order data sheets simply
specify the part number or the name of the support
equipment.

Where to get more on the R6500
Rockwell's normal procedure is to provide you with
free data sheets so that you can select the R6500
devices and support equipment of most interest to you.
A nominal charge is made for reference manuals.
For data, devices or support equipment contact the
nearest Rockwell office or distributor listed on the back
page of this brochure. For in-depth assistance, obtain
the name of your nearest Rockwell sales representative
from any Rockwell office.

PART NUMBER

DOCUMENT NO. 29000 039
REV. 3, FEBRUARY 1979

'1'

Rockwell ,:

R650X and R651X

R6500 Microcomputer System
DATA SHEET

R6500 MICROPROCESSORS (CPU's)
SYSTEM ABSTRACT

FEATURES

The 8-bit R6500 microcomputer system is produced with NChannel, Silicon Gate technology. Its performance speeds are
enhanced by advanced system architecture. This innovative
architecture results in smaller chips - the semiconductor threshold
to cost-effectivity. System cost-effectivity is further enhanced by
providing a family of 10 software-compatible microprocessor
(CPU! devices, described in this document. Rockwell also provides memory and microcomputer system ... as well as low-cost
design aids and documentation.

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

R6500 MICROPROCESSOR (CPU) CONCEPT
Ten CPU devices are available. All are software-compatible.
They provide options of addressable memory, interrupt input,
on-chip clock oscillators and drivers. All are .ti'us-compatible
with earlier generation microprocessors like the M6800 devices.
The family includes six microprocessors with on.board clock
oscillators and drivers and four microprocessors driven by external
clocks. The on-chip clock versions are aimed at high performance,
low cost applications where single phase inputs, crystal or RC
inputs provide the time base. The external clock versions are
geared for multiprocessor system applications where maximum
timing control is mandatory. All R6500 microprocessors are
also available in a variety of packaging (ceramic and plastic),
operating frequency (1 MHz and 2 MHz) and temperature (commercial, industrial and military) versions.

MEMBERS OF THE R6500 MICROPROCESSOR
(CPU) FAMILY

Single +5V supply
N channel, silicon gate, depletion load technology
Eight bit parallel processing
56 Instructions
Decimal and binary arithmetic
Thirteen addressing modes
True indexing capability
Programmable stack pointer
Variable length stack
Interrupt capability
Non-maskable interrupt
Use with any type of speed memory
8-bit Bidirectional Data Bus
Addressable memory range of up to 65K bytes
"Ready" input
Direct Memory Access capability
Bus compatible with M6800
1 MHz and 2 MHz operation
Choice of external or on-chip clocks
On-the-chip clock options
External single clock input
- RC time base input
- Crystal time base input
• Commercial, industrial and military temperature versions
• 'Pipeline architecture

R6502
R6503
R6504
R6505
R6506
R6507

Addressable Memory
65K
4K
8K
4K
4K
8K

Bytes
Bytes
Bytes
Bytes
Bytes
Bytes

Microprocessors with External Two Phase Clock Output
Modal
R6512
R6513
R6514
R6515

@

Addressable Memory
65K
4K
8K
4K

Bytes
Bytes
Bytes
Bytes

Rock_II Intern.tional Corporation 1979
All Rights Reserved
Pri.lIed in U.S.A.

en

(JI

o
o

s:n

:D

O·
"'tJ

:D

o
n

m
en
en

o

:D

en

Ordering Information
Order Number:

R65XX __ _

Microprocessors with On-Chip Clock Oscillator
Model

::a

lTemperature Range:
No suffix = OOC to +70 0 C
0
E = -40°C to +85 C
!Industrial)
MT

=

M =

0

-550 C to +125 C
(Military)
MIL-STD-883,
Class B

Package:
C

=

Ceramic;
Piastre
(Not Avaible for
M or MT suffix)
Frequency Range:
No suffix = 1 MHz
A = 2 MHz
Model Designator:
XX = 02,03,04, ..• 15
NOTE: Contact your local Rockwell Represantative
concerning availability.
P

K

Specification. IUbJect to
change without notice

-n
c:
-

"'tJ
0'"

•

R6500 Signal Description
Clocks (4)1' 4>2)

Non-Maskable Interrupt (FJMI)

The R651X requires a two phase non-overlapping clock that runs
at the VCC voltage level.

A negative going edge on this input requests that a non-maskable
interrupt sequence be generated within the microprocessor.

The R650X clocks are supplied with an internal clock generator.
The frequency of these clocks is externally controlled.

NMI is an unconditional interrupt. Following completion of the
current instruction, the sequence of operations defined for IRO
will be performed, regardless of the state interrupt mask flag. The
vector address loaded into the program counter, low and high, are
locations FFFA and FFFB respectively, thereby transferring program control to the memory vector located at these addresses.
The instructions loaded at these locations cause the microprocessor to branch to a non-maskable interrupt routine in memory.

Address Bus (AO-A15)
These outputs are TTL compatible, capable of driving one standard
TTL load and 130 pF.
Data Bus (00-07)
Eight pins are used for the data bus. This is a bidirectional bus,
transferring data to and from the device and peripherals. The outputs are tri-state buffers capable of driving one standard TTL load
and 130pF.
Data Bus Enable (OBE)
This TTL compatible input allows external control of the tri-state
data output buffers and will enable the microprocessor bus driver
when in the high state. In normal operation OBE would be driven
by the phase two (4)2) clock, thus allowing data output from
microprocessor only during 4>2. During the read cycle, the data
bus drivers are internally disabled, becoming essentially an open
circuit. To disable data bus drivers externally, OBE should be held
low.
Ready (ROY)
This input signal allows the user to halt or single cycle the microprocessor on all cycles except write cycles. A negative transition
to the low state during or coincident with phase one (4)1) will halt
the microprocessor with the output address lines reflecting ~he
current address being fetched. If Ready is low during a write
cycle, it is ignored until the following read operation. This condition will remain through a subsequent phase two (4)2) in which
the Ready signal is low. This feature allows microprocessor interfacing with the low speed PROMs as well as fast (max. 2 cycle)
Direct Memory Access (DMA).
Interrupt Request (lRO)
This TTL level input requests that an interrupt sequence begin
within the microprocessor. The microprocessor will complete the
current instruction being executed before recognizing the request.
At that time, the interrupt mask bit in the Status Code Register
will be examined. If the interrupt mask flag is not set, the microprocessor will begin an interrupt sequence. The Program Counter
and Processor Status Register are stored in the stack. The microprocessor will then set the interrupt mask flag high so that no further interrupts may occur_ At the end of this cycle, the program
counter low will be loaded from address FFFE, and program
counter high from location FFFF, therefore transferring program
control to the memory vector located at these addresses. The
ROY signal must be in the high state for any interrupt to be recognized. A 3Kn external resistor should be used for proper
wire-OR operation.

NMI also requires an external 3K n register to V CC for proper
wire-OR operations.
Inputs IRO and NMI are hardware interrupts. lines that are sampled during 4>2 (phase 2) and will begin the appropriate interrupt
routine on the 4> 1 (phase 1) following the completion of the current instruction.
Set Overflow Flag (S.O.)

A negative going edge on this input sets the overflow bit in the
Status Code Register. This Signal is sampled on the trailing edge of
4>1 and must be externally synchronized.

SYNC
This output line is provided to identify those cycles in which the
microprocessor is doing an OP CODE fetch. The SYNC line goes
high during 4>1 of an OP CODE fetch and stays high for the
remainder of that cycle. If the ROY line is pulled low during the
4>1 clock pulse in which SYNC went high, the processor will stop
in its current state and will remain in the state until the ROY line
goes high. In this manner, the SYNC signal can be used to control
ROY to cause single instruction execution.

Reset
This input is used to reset or start the microprocessor from a
power down condition. During the time that this line is held low,
writing to or from the microprocessor is inhibited. When a positive edge is detected on the input, the microprocessor will immediately begin the reset sequence.
After a system initialization time of six clock cycles, the mask
interrupt flag will be set and the microprocessor will load the pro·
gram counter from the memory vector locations FFFC and FFFD.
This is the start location for program control.
After VCC reaches 4.75 volts in a power up routine, reset must be
held low for at least two clock cycles. At this time the R!W and
(SYNC) signal will become valid.
When the reset signal goes high following these two clock cycles,
the microprocessor will proceed with the normal reset procedure
detailed above.

ADDRESSING MODES
ACCUMULATOR ADDRESSING - This form of addressing is
represented with a one byte instruction, implying an operation on
the accumulator.

IMPLIED ADDRESSING - In the implied addressing mode, the
address containing the operand is implicitly stated in the operation
code of the instruction.

IMMEDIATE ADDRESSING - In immediate addressing, the
operand is contained in the second byte of the instruction, with
no further memory addressing required.

RELATIVE ADDRESSING - Relative addressing is used only
with branch instructions and establishes a destination for the conditional branch.

ABSOLUTE ADDRESSING - In absolute addressing, the second
byte of the instruction specifies the eight low order bits of the
effective address while the third byte specifies the eight high
order bits. Thus, the absolute addressing mode allows access to
the entire 65K bytes of addressable memory.
ZERO PAGE ADDRESSING - The zero page instructions allow
for shorter code and execution times by only fetching the second
byte of the instruction and assuming a zero high address byte.
Careful use of the zero page can result in significant increase in
code efficiency.
INDEXED ZERO PAGE ADDRESSING - (X, Y indexing) - This
form of addressing is used in conjunction with the index register
and is referred to as "Zero Page, X" or "Zero Page, V". The effective address is calculated by adding the second byte to the can·
tents of the index register. Since this is a form of "Zero Page"
addressing, the content of the second byte references a location in
page ZHO. Additionally due to the "Zero Page" addressing nature
of this mode, no carry is added to the high order 8 bits of memory
and crossing of page boundaries does not occur.
INDEXED ABSOLUTE ADDRESSING - (X, V indexing) - This
form of addressing is used in conjunction with X and V index reg·
ister and is referred to as "Absolute, X", and "Absolute, V". The
effective address is formed by adding the ·contents of X or V to
the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or
count value and the instruction to contain the base address. This
type of indexing allows any location referencing and the index to
mOdify multiple fields resulting in reduced coding and execution
time.

The second byte of the in~truction becomes the operand which is
an "Offset" added to the contents of the lower eight bits of the
program counter when the counter is set at the next instruction.
The range of the offset is ·128 to +127 bytes from the next
instruction.
INDEXED INDIRECT ADDRESSING - In indexed indirect
addressing (referred to as (Indirect, X)), the second byte of the
instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory
location on page zero whose contents is the low order eight bits
of the effective address. The next memory location in page zero
contains the high order eight bits of the effective address. Both
memory locations specifying the high and low order bytes of the
effective address must be in page zero.
INDIRECT INDEXED ADDRESSING - In indirect indexed
addressing (referred to as (Indirect!, V), the second byte of the
instruction points to a memory location in page zero. The can·
tents of this memory location is added to the contents of the V
index register, the result being the low order eight bits of the
effective address. The carry from this addition is added to the
contents of the next page zero memory location, the result being
the high order eight bits of the effective address.
ABSOLUTE INDIRECT - The second byte of the instruction
contains the low order eight bits of a memory location. The high
order eight bits of that memory location is contained in the third
byte of the instruction. The contents of the fully specified memo
ory location is the low order byte of the effective address. The
next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program
counter.

INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC Add Memory to Accumulator with Carry
AND "AND" Memory with Accumulator
ASL Shift left One Bit (Memory or Accumulator)
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC Clear Carry Flag
CLD Clear Decimal Mode
CLI Clear Interrupt Disable Bit
CLV Clear Overflow Flag
CMP Compare Memory and Accumulator
CPX Compare Memorv and Index X
CPV Compare Memory and Index V
DEC Decrement Memory by One
DEX Decrement Index X by One
DEV Decrement Index V by One
EOR

"Exclusive-or" Memory with Accumulator

INC
INX
INV

Increment Memory by One
Increment Index X by One
Increment Index V by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return Address

LOA
LOX
LOY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index V with Memory
Shift One Bit Right (Memory or Accumulator)

NOP

No Operation

ORA "OR" Memory with Accumulator
PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

ROL
ROR
RTI
RTS

R9tate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine

SBC
SEC
SED
SEI
STA
STX
STY

Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index V in Memory

TAX
TAV
TSX
TXA
TXS
TVA

Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index V to Accumulator

I

R6502 - 40 Pin Package

VSS

RES

ROY

2 (OUT)
rJ>0 (IN)

1/11 (OUT)

Riw

IRQ

DO

VCC
AO

01

02
03

Al

A2

04

A3

05

A4

06
07

A5

Features of R6506
•
•
•
•
•

4K Addressable Bytes of Memory (AO-A 11)
On-the-chip Clock
IRQ Interrupt
Two phase output clock for timing of support chips
8 Bit Bidirectional Data Bus

All
Al0

A6

A7
AS

A9

R6507 - 28 Pin Package
RES
VSS
ROY

VCC
AO
Al

A2

rJ>2 (OUT)
rJ>0 (IN)

Rm
DO
01

02
03

A3

04

A4

05

A5

06
07

A6

A7
AS
A9

Features of R6507
•
•
•
•

8K Addressable Bytes of Memory (AO-AI2)
On-the-chip Clock
ROY Signal
8 Bit Bidirectional Data Bus

A12

All
Al0

R6512 - 40 Pin Package
VSS

RES

ROY

rJ>2 (OUT)
S.D.

1/11
IRO

VSS

rJ>2
OBE

NMI

N.C.

SYNC

R/W

VCC
AO

DO

Al

02
03

A2
A3

01

04

A4

05

A5

06
07

A6

A7
AS

A15

A9

A13

Al0

A12

All

VSS

A14

Features of R6512

•

•
•
•
•
•
•

65K Addressable Bytes of Memory (AO-AI5)
IRQ Interrupt
NMI Interrupt
ROY Signal
8 Bit Bidirectional Data Bus
SYNC Signal
Two phase clock input
Data Bus Enable

•

R6513 - 28 Pin Package
VSS

RES

ct>1

ct>2

IRQ

R/W

NMI

DO

vee

01

AO
A1
A2

02
03

04

A4
A5

05
06
01

A6

A11

A1

A10
A9

A3

AS

Features of R6513
•
•
•
•

•

4K Addressable Bytes of Memory (AO-A 11)
Two phase clock input
IRQ Interrupt
NMI Interrupt
8 Bit Bidirectional Data Bus

R6514 - 28 Pin Package

VSS

ct>1
IRQ

vee
AO
A1
A2

RES
2(OUTI Pul •• Width Im'lnured .t 1.6VI

PWH4>2

PWH4>oH..cO

4>1l0UT)' 4>2COUT) Aile, fill Tim.
Im'Mured II 0.8\1 to 2.0V)
(loKI. 130 pF + 1 TTU

TR,T F

ol

,20

Typ

'ymbol
10,0

'1'.5111

PWH4>o

.oIlN) RI", Fin Tim.

TR4Io. TF. o

O".y Tim. B.twet'n Cocks

TO

(m.asured.11,5VI

PWH4IOL

4>1I0UTI Pul. Width lmenured It 1.5\11

PWH.,

PWH(,toH,10

¢'2fOUTl Pul .. Width Im ...urld It 1.5\11

PWH4>2

.HOUl)' 4>210UTl Ri... Fell Tim.

T R' T F

25

(measured .1 O.8V to 2.0V)
fLo.. -130pF + I TTL)

'The lowest operating frequency for the commercial temperature range CPU's is 100 KHz, which corresponds to a maximum cycle time
(TCYCI of 10 I's. The lowest operating frequency for the industrial and military temperature range CPU's is 250 KHz, which corresponds
to a maximum cycle time (TCYCI of 41'S.

Clock Timing - R6512, 13, 14,15

Clock Timing - R6512, 13, 14, 15

IM..suredlt Vcc·D.2VI

.y.....

T.,.

'ymbol

Cycl.Time

.'

.2

430
410

ClockPu"'Wldth
tMelllUred ., Vee ·O.2vl

T.,.

.1

21'

_2

23'

Fall Time
Imeasullld from O.2V to Vee· O.2VI

Del.., Time between Clock,
(Measured a, O.2VI

Dele ... Time between Clocks
(measured a' O.2vl

Read/Write Timing ••

ReadiWrite Timing ••
Typ

Typ

Symbol

ReedlWnte SetuP Tim. from R6500

R.adlWrite Setup Tim. from R6500A

TAWS

Addr.u Setup Tim. from R6500

Addr... Setup Time from R6500A

TAOS

Memory Read Aceeu Time

Memory A ..d Ace,", Tim.

T

O"aStebihtyTimeP.riod

ACC

TOSU
THA

T HW
Oeta Setup Tim. from R6S00

Oet8 Setup Tim. from A6500A

T

ROY. 5.0. Setup Time

ROY. 5.0. Setup Tim.

TROY

SYNC Setup Tim. frotn R6500

SYNC Setup Time from R6500A

MOS

TSYNC
THA

RIW

Hold Time

T

Load Conditions

=1

HRW

TTL Load + 130 pf

RECOMMENDED TIME BASE GENERATION
1.8K

3.3K

7404

1.8K

7404

~-~Dt--------'
XTAL
(1 MHz - 5 MHzl'
'CRYSTAL: CTS KNIGHTS MP SERIES, OR EQUIVALENT

1/12

. . . . - - REGISTER SECTION

CONTROL SECTION - - - - - .

AO

Al

A2

ABL

INSTRUCTION

DECODE

ADDRESS
BUS

4>1 liN) }

Al0

R6512, 13, 14. 15

~+--4>21IN)

ABH

~OIlN)

A12

4>1 OUT

r---------4~-t-----,

'--_----'.._

4>2 OUT

L------l~ RiW
L -_ _ _ _

A15

LEGEND

11

"B BIT LINE

I '"
1
2

L -_ _ _ _ _ _ _

;-;-~~--~..-D4

L -_ _ _ _ _ _ _ _~~------..D5

1 BIT LINE

'--________

-+~-----~D6

Clock Generator is not included on R6512. 13, 14, 15
Addressing Capability end control options vary with each

of the R6500 Products.

R6500 Internal Architecture

DBE

R6502, 03, 04, 05, 06, 07

•

SPECIFICATIONS
Maximum Ratings
Rating
Supply Voltage
Input Voltage
Operating Temperature
Commercial
Industrial
Military
Storage Temperature

Symbol

Unit

Value

Vdc
Vdc

-0.3 to +7.0
-0.3 to +7.0

VCC
V.
In
T

°c

o to +70
40to +85
-55 to +125
-55 to +150

T STG

°c

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to
avoid application of voltages higher than the maximum rating.

Electrical Characteristics
(V cc

= 5.0±5%, vss = 0)



"

•

PART NUMBER

DOCUMENT NO, 29000 051
REVISION 3, JUNE 1979

R6500 Microcomputer System

DATA SHEET

~ ~

R6500/1 ONE-CHIP MICROCOMPUTER
INTRODUCTION

FEATURES

The Rockwell R6500/1 is a complete, high-performance 8-bit
NMOS microcomputer on a single chip, and is totally upwardl
downwa'rd software compatible with all members of the R6500
family.

•

The R6500/1 consists of an R6502 CPU, an internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes of
Random Access Memory (RAM) and flexible interface circuitry.
The interface circuitry includes a 16-bit programmable counterl
latch with four operating modes, 32 bidirectional inputloutput
lines (including two edge1lensitive lines), five interrupts and a
counter 1/0 line.

R6502 CPU
Software upwardldownward compatibility
Decimal or binary arithmetic modes
13 addressing modes
True direct and indirect indexing
Memory addressable 1/0

•
•
•
•
•

2048 x 8 mask programmable ROM
64 x 8 static RAM
32 bi~irectional TTL compatible 1/0 lines (4 ports)
1 bi~irectional TTL compatible counter I/O line
16-bit programmable counterllatch with four modes
Interval Timer
Pulse Generator
Event Counter
Pulse Width Measurement

PRODUCT SUPPORT
To allow prototype circuit development, Rockwell offers a PROM
compatible 64"pin E;mulator device. This device provides all
Rn500/1 interface lines plus routing the address bus, data bus,
and associated control lines off the chip to be connected to
external memory.

•

To facilitate system and program development for the R65OD/l,
Rockwell offers extensive product support. The SYSTEM 65
Microcomputer Development System with the R6500/1 Personality Module supports both hardware and software development.
Complete in-circuit user emulation with the R6500/1 Personality
Module allows total system test and evaluation.

•

Regularly scheduled designer's courses are offered at regional
centers.
The support products available are:
•
•
•
•
•
•

SYSTEM 65 Microcomputer Development System
1 MHz R6500/1 Personality Module
2 MHz R6500/1 Personality Module
1 MHz R6500/1 Emulator Device
2 MHz R6500/1 Emulator Device
R6500/1 Evaluation Module

PIN S65-101
PIN
PIN
PIN
PIN
PIN

M65-{)81
M65-{)82
R6500/1 EC
R6500/1 EAC
PS01-Dl00

"...a
2

m
I

n

Reset
Non-maskable
Two external edge sensitive
Counter

•
•
•
•
•
•
•
•
•

o
o

o

Five Interrupts

l:
."

1 of 3 frequency references
-

:XI

en
en

Crystal
Clock
RC (resistor only)

~

4 MHz max crystal or clock external frequency
2 MHz or 1 MHz internal clock.
1 Jls minimum instruction execution
N-channel, Silicon gate, depletion load technology
Single +5V power supply
500 mW operating power
Separate power pin for RAM
40 pin DIP
64 pin PROM compatible Emulator device

n
:XI
o
n
o
S
."

c:

-t

ORDERING INFORMATION
Order
Number

Package
Type

R6500/1P
R6500/1AP
R6500/1AC

Plastic
Ceramic
Plastic
Ceramic

R6500/1PE
R650D/lCE
R650D/lACE

Plastic
Ceramic
.Ceramic

R6500/1C

Note:

1
1
2
2

MHz
MHz
MHz
MHz

1 MHz
1 MHz
2 MHz

:XI

Temperatura
Range
OOC to 70 0 C
OoC to 70°C
OoC to 70 0 C
OoC to 70 0 C
-40°C to +85 0 C
0
-40°C to +85 C
0
-40°C to +85 C

The RC frequency option is available only in the 1 MHz
R6500/1.

@

Frequency
Option

m

Rockwell Internationat Corporation 1979
All Rights Reserved
Printed in U. S.A

Interface Diagram
Speciflcetlons subject to
change without notice

FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
Clock Oscillator
The Clock Oscillator provides the basic timing signals used by the
R6500/1 CPU. The reference frequency is provided by an external
source, and can be from a crystal, clock or RC network input. The RC
network mode is a mask option. The external frequency can vary from
200 kHz to 4 MHz. The internal Phase 2 (02) frequency is one-half the
external reference frequency. A 4.7K ohm resistor will provide nominal 2 MHz oscillation and 1 MHz internal operation in the RC mask
option (±35%1.

CARRy ICIIII

1 •

.,..,.s..

o • c.ryC ...
ZEROIZII1I
,

-

o •

ZewoR ... tt

Non-Z.o Aew"

L -_ _ _ _ INTERRUPT DISABLE

,

•

o •

IIJ 121

IRQlnt..,.uptDtub ....
IROlntllfl'upt E",.blld

' - - - - - - - - DECIMAL MODE 101111

Timing Control
The Timing Control Logic keeps track of the specific instruction cycle
being executed. Each data transfer which takes place between the
registers is caused by decoding the contents of both the Instruction
Register and Timing Control Logic.

,

•

o

•

0.1,...1 Mod,
BiNl'yMode

L--_ _ _ _ _ _ _ BREAK COMMAND 181111
1

•

o •

BrellkCotnlNftd
Not Bruk Com,.,.nd

L -_ _ _ _ _ _ _ _ _ _ OVERflOW 101 111

Program Counter
The 16-bit Program Counter provides the addresses which step the
CPU through sequential instructions in a program. The Program
Counter is incremented each time an instruction or data is fetched
from memory.

1 •

o •

OwrerftowSet
OverftowCfN,

'--------------NEGATIVEINII1I
NOTES
(1) Not initialind by

'Ril

,

•

o •

121 SettoLovie1byW

Neva_i.,V,lue
PoaItIYIIV,lul

Processor Status Register
Instruction Register and Decode
Instructions fetched from memory are gated onto ttle Internal Data
Bus. These instructions are latched into the Instruction Register then
decoded, along with timing and interrupt signals, to generate control
signals for the various registers.
Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place in the ALU, including
incrementing and decrementing internal registers (except the Program
'
Counter).
Accumulator
The accumulator is a general purpose 8-bit register that stores the
results of most 'arithmetic and logic operations. In addition, the accumulator usually !=ontains one of the two data words used in these
operations.
Index Registers
There are two 8-bit index registers, X and Y _ These registers can be
used for general purpose storage, or as a displacement to modify the
base address and thus obtain a new effective address. Pre- or postindexing of indirect addresses is possible.
Stack Pointer
The Stack Pointer is an 8-bit register. It is automatically incremented
and decremented under control of the CPU to perform stack manipulation under direction of either the program or interrupts liIm and
IRO. The stack allows simple implementation of nested subroutines
and multiple level interrupts.

Processor Status Register
The 8-bit Processor Status Register contai~~ seven status flags. Some
of the flags ere controlled by the program, others may be controlled
both by the program and the CPU_ The R6500 instruction set contains
a number of conditional branch instructions which are designed to
allow testing of these flags.

MEMORY
2048 x8 ROM
The 2048 byte Read-Only Memory (ROM) contains the program
instructions and other fixed constants. These program instructions and
constants are mask programmed into the ROM during fabrication of the
R6500/1 device. The R6500/1 ROM is memory mapped from 800 to
FFF.
64 x8 RAM
The 64 byte Random Access Memory (RAM) is used for read/write
memory during system operation, and ,contains the stack_ This RAM is
completely static in operation and requires no clock or dynamic refresh.
A standby power pin, VRR, allows RAM memory to be maintained on
10% of the operating power in the event that VCC power is lost.
In order to take advantage of efficient zero page addressing capabilities, the RAM is assigned memory addresses 0 to 03F.

INPUT/OUTPUT
Bidirectional I/O Ports
The R650011 provides four 8-bit 'input/output ports (PA, PB, PC, and
PO). Associated with the 1/0 ports are four 8-bit registers located on
page zero. See the system memory map for specific addresses. Each
I/O line is individually selectable as an input or an output without line
grouping or port association restrictions.
An internal active transistor drives each I/O line to the low state. An
internal passive resistance pulls the I/O lines to the high state, eliminating the need for external pull-up resistors.
An OPtion is available to delete the internal pull-Up resistance on B-bit
port groups or on the CNTR line at mask time. This option is employed
to permanently assign an 8-bit port group to input functions, to interface with CMOS drivers, or to interface with external pull-up devices.
Inputs
Inputs are enabled by setting the appropriate bit of the I/O port to the
high state (Logic 1). A low input Signal causes a logic 0 to be read_ A
high input signal causes a logic 1 to be read. 'i'ftS" loads Logic 1 into the
I/O ports, thereby initializing all I/O lines as inputs.

Interrupt Logic

Outputs

Interrupt logic controls the sequencing of three interrupts; RES, NMI
and IRO. IRO is generated by anyone of three conditions: Counter
Overflow, PAO POSitive Edge Detected, and PA 1 Negative Edge Detected.

Outputs are set by loading the desired bit pattern into the corresponding I/O ports. A Logic 1 selects a high output; a Logic 0 selects a low
output.

CONTROL REGISTER
The Control Register (CR) controls four Counter operating modes and
three maskable interrupu. It also reporu the status of three interrupt
conditions. There are five control bits and three status bits. The control bits are set to Logic 1 or cleared to Logic 0 by writing the desired
state into the respective bit positions. The Control Register is cleared
to Logic 0 by the occurrence of RES.
•

ICTAotAOED IAUD(

elE

t AGII lAUE tcuc1 1CMCO I

LL

COUNTER MODE CONTROL fCUC' • CMCO)

o

o

0 •
1

•

to·

1 1 •

',",,".Tim.
, ..... G ........,

E...., Count ...
'U'" Width Me.urwnent

PA1 INTERRUPT ENABLE lAUE)

The Counter can be preset at any time by writirlg to address 088. Presetting the Counter in this manner causes the contanU of the accumulator to be stored into the UL before the 1I)-I>lt value In the Latch (UL
and LL) is transferred in the Counter (UC and LC).
The Counter Is preset to the Latch value when the Counter overflows.
When the counter decrements from 0000. Counter overflow occurs
causing the next counter value to be the Latch value, not FFFF.
When the Counter overflows, Counter Overflow bit - Bit 7 of the
Control Register - is set tb Logic 1. When both this bit and the Counter
Interrupt Enable bit - Bit 4 of the Control Register - are set, an
iRa interrupt request is generated. The Counter Overflow bit in the
Control Register can be examined in an
interrupt service routine
to determine that the1RQ was gen.era~ed by Cou"!ter overflow.

rnrr

The Counter Overflow bit is cleared when the LC is read or Counter
preset is performed by writing into address 088.

, - E. . . . PAl Interrupt
O· DiMbI. ' .. 'Interrupt

PM INTERRUPT EN ....LE IAOIEI
, - [neb.. 'AO '"t.mlpt

o•

Diubl. PAG Interrupt

COUNTER INTERRUPT ENABLE (CIEI
1· [NIb.. Count., In,..,.upt
o • Diubl. Count., 'nterTUpt

.COUNTER MODES
The Counter operates in any of four modes. These modes are selected
by the Counter Mode Control bits in the Control Register.

'A, NEGATIVE EDGE DETECTED fAtEDI

1 •

o •

'A1Negati.,.Ect,.Oetected
'A 1 N.... i". E.... Not DetllCted

'AO POSITIVE EDGE DETECTED (AOEOI

1 •

o •

'AG Pos"i" Edge OetKted
'AO Positive Ed,. Not DetllCted

Mode

CMC1

Interval Timer
Pulse Generator
Event Counter
Pulse Width Measurement

0
0
1
1

~
0
1
0
1

COUNTER OVERFLOW fCTROI
1

•

o •

Count .. Oftrflow Dcculnd
No Count.. Owerilow

Control Register

The Interval Timer, Pulse Generator, and Pulse Width Measurement
Modes are tP2 clock counter modes. The Event Counter Mode counts
the occurrences of an external event on the CNTR line.
Interval Timer (Mode 0)

EDG'E DETECT CAPABI LITY
There is an asynchronous edge detect capability on two of the Port A
I/O lines. This capability exists in addition to and independently from
the normal Port A I/O functions. The maximum rate at which an edge
can be detected is one-half the tP2 clock rate. The edge detect logic is
continuously active. Each edge detect signal is associated with a mask- ,
able interrupt.
PAO Positive Edge Detection
A positive (rising) edge is detectable on PAO. When this edge is detected,
the PAO Positive Edge Detected bit - Bit 6 in the Control Register is set to Logic 1. When both this bit and the PAO Interrupt Enable
Bit - Bit 3 of the Control Register - are set to Logic " an IRQ inter,
rupt request is generated. The PAO Positive Edge Detected bit is cleared
by writing to address 089.
PA 1 Negative Edge Detection
A negative (falling) edge is detectable on PA1. When this edge is
detected. the PA 1 Negative Edge Detected bit - Bit 5 of the Control
Register - is set to Logic 1. When both this bit and the PA 1 Inter·
rupt Enable bit - Bit 2 of the Control Register - are set to Logic "
an IRQ interrupt request is generated. The PA 1 Negative Edge Detected
bit is cleared by writing to address 08A.

In this mode the Counter is free running and decrements at the tP2
clock rate. Counter overflow sets the Control Register status bit and
causes the Counter to be preset to the Latch value.
The CNTR line is held in the high state.
Pulse Generator (Mode 1)
In this mode the Counter is free running and decrements at the tP2
clock rate. Counter overflow sets the Control Register status bit and
causes the Counter to be preset to the Latch value.
The CNTR line toggles from one state to the other when Counter overflow occurs. Writing to address 088 will also toggle the CNTR line.
A symmetric or asymmetric output vvaveform can be generated on the
CNTR line in this mode. A one-shot waveform can easily be generated
by changing from Mode 1 to Mode 0 after only one occurrence of the
output toggle condition.
Event Counter (Mode 2)
In this mode the CNTR line is used as an event input line. The Counter
decrements each time a rising edge is detected on CNTR. The maxi·
mum rate at which this edge can be detected is one-half the tP2 clock
rate. Counter overflow sets the Control Register status bit and causes
the Counter to be preset to the Latch value.
Pulse Width Measurement (Mode 3)

COUNTER/LATCH
The Counter/Latch consists of a 16-1>it decrementing Counter and a
16-1>it Latch. The Counter is comprised of two 8-1>it registers. Address
086 contains the Upper Count (UC) and address 087 contains the
Lower Count (LCI. The Counter cou nts either tP2 clock periods or
occurrences of an external event, depending on the selected counter
mode. The UC and LC can be read at any time without affecting
counter operation.
The Latch contains the Counter preset value. The Latch consists of
two 8-1>it registers. Address 084 contains the Upper Latch (UL) and
address 085 contains the lower latch (LU. The 16-1>it Latch can hold
a count from 0 to 65,535. The Latch can be accessed as two write·only
memory locations.
The Latch registers can be loaded at any time by storing into UL and
LL. The UL can also be loaded by writing into address 088.

This mode allows the accurate measurement of the duration of a low
state on the CNTR line. The Counter decrements at the ",2 clock rate
as long as the CNTR line is held in the low state. The Counter is stopped
when CNTR is in the high state. If the CNTR pin is left disconnected.
this mode may be selected to stop the Counter since the internal
pull·up device will cause the CNTR input to be in the high state.

RESET CONSIDERATIONS
The occurrence of RES going from low to high causes initialization of
various conditions in the R6500/1. All of the I/O ports (PA, PB, PC,
'and PO) and CNTR are forced to the high (Logic 1) state. All bits of
the Control Register are reset to Logic 0, causing the Interval Timer
Mode (Mode 0) to be selected andJo all interrupt enabled bits to be
cleared. Neither the Latch nor the Counter registers are initialized
by RES. The Interrupt Disable bit in the CPU Processor Status Register is set and the program starts execution at the address contained
in the Reset Vector location.

I

TEST LOGIC

SIGNAL DESCRIPTIONS

Special test logic provides a method for thoroughly testing the R6S00/1.
Applying a +10V signal to the RES line places the R6S00/1 in the test
mode. While in this mode, all memory fetches ilre'madefrom Port PC.
External test equipment can use this feature to test internal CPU logic
and I/O. A program can be loaded into RAM allowing the contents of
the instruction ROM to be dumped to any port for external verification.

SIGNAL NAME
VCC

PIN NO.
30

VRR

DESCRIPTION
Main power supply +SV
Separate power pin for RAM. In
the event that VCC power is lost,
this power retains RAM data.

All R6S00/1 microcomputers are tested by Rockwell using this feature.

MEMORY ADDRESSABLE I/O
'The I/O ports, registers, and commands are treated as memory and are
assigned specific addresses. See the system memory map for the
addresses. This I/O technique allows the full set of CPU instructions
to be used in the generation and sampling of I/O commands and data.
W!!!.n an instruction is executed with an I/O address and appropriate
R/W state, the corresponding I/O function Is performed.
HEX
IRQ Vector High

FFF

IRQ Vector Low

FFE

RES Vector High

FFO

RES Vector Low

FFC

NMIVectorHigh

FF8

NMI Vector Low

FFA

VSS

12

Signal ground

XTLI

10

Crystal, clock or RC network
input for internal clock oscillator.

XTLO

11

Crystal or RC network output
from internal clock oscillator.

RES

39

The Reset input is used to initialize the R6S00/1. This signal must
not tranSition from low to high for
at least eight cycles after VCC
reaches operating range and the
internal oscillator has stabilized.

NMT

40

A negative going edge on the NonMaskable Interrupt signal requests
that a non-maskable interrupt be
generated within the CPU.

38-31
29-22
20-13
9-2

Four 80bit ports used for either
input/output. Each line consists
of an active transistor to VSS and
a passive pull-up to +SV. The two
lower bits of the PA port (PAC and
PA 1) also serve as edge detect
inputs with maskable interrupts.

ROM

FF9
UHr Program

+10V input enables the test mode.

800
Une.. igned

OOF

Control Register

OSE

Unassigned

CI., PAl

N~

OS8

Edge Detected

111

OSA

Clear PAO POI Edge Oltect.:i

111

OS9

Upper Utch and Transf.r latch to Count.r

121

OS8

Lawver Count

121

OS7

Upper Count

Input/Output

086
085
084

lower Latch
Upper latch

PORT 0
pORTe

OS3

PORTB

OSI

PAO·PA7
PBO·PB7
PCO-PC7
PDO-PD7

OS2

OBO

PORTA

CNTR

Unassigned
03F}
000 RAM

Us.rRAM

Notes:
111 1/0 command only; I.•.• no stored data.
(2) Clears Counter Overflow - Sit 7 in Control Register.

System Memory Map

R6500/1 Block Diagram

21

This line is used as a Counter
input/output line. CNTR is an
input in the Event Counter and
Pulse Width Measurement modes
and is an output in the Interval
Timer and Pulse Generator
modes.

INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC
AND
ASL

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift left One Bit (Memory or Accumulator)

BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CL V
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EOR

"Exclusive-or" Memory with Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return Address

LDA
LDX
LDY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)

NOP

No operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

ROL
ROR
RTI
RTS

Rotate
Rotate
Return
Return

SBC
SEC
SED
SEI
STA
STX
STY

Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory

TAX
TAY
TSX
TXA
TXS
TYA

Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator

One Bit Left (Memory or Accumulator)
One Bit Right (Memory or Accumulator)
from Interrupt
from Subroutine

ADDRESSING MODES
ACCUMULATOR ADDRESSING - This form of addressing is represented with a one byte instruction, implying an operation on the
accumulator.

IMPLIED ADDRESSING - In the implied addressing mode, the
address containing the operand is implicitly stated in the operation
code of the instruction.

IMMEDIATE ADDRESSING - In immediate addressing, the operand
is contained in the second byte of the instruction, with no further
memory addressing required.

RELATIVE ADDRES~ING - Relative addressing is used only with
branch instructions and establishes a destination for the conditional
branch.

ABSOLUTE ADDRESSING - In absolute addressing, the second byte
of the instruction specifies the eight low order bits of the effective
address while the third byte specifies the eight high order bits.

The second byte of the instruction becomes the operand which is an
"Offset" added to the contents of the lower eight bits of the program
counter when the counter is set at the next instruction. The range of
the offset is -128 to +127 bytes from the next instruction_

ZERO PAGE ADDRESSING - The zero page instructions allow for
shorter code and execution times by only fetching the second byte
of the instruction and assuming a zero high address byte. Careful use
of the zero page. can result in significant increase in code efficiency.
INDEXED ZERO PAGE ADDRESSING - (X, Y indexing) - This
form of addressing is used in conjunction with the index register
and is referred to as "Zero Page, X" or "Zero Page, Y"_ The effective
address is calculated by adding the second byte to the contents of the
index register. Since this is a form of "Zero Page" addressing, the
content of the second byte references a location in page zero. Additionally due to the "Zero Page" addressing nature of this mode, no
carry is added to the high order 8 bits of memory and crossing of page
boundaries does not occur.
INDEXED ABSOLUTE ADDRESSING - (X, Y indexing) - This
form of addressing is used in conjunction with X and Y index register
and is referred to as "Absolute, X", and "Absolute, Y". The effective
address is formed by adding the contents of X or Y to the address
contained in the second and third bytes of the instruction. This mode
allows the index register to contain the index or count value and the
instruction to contain the base address. This type of indexing allows
any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

INDEXED INDIRECT ADDRESSING - In indexed indirect addressing (referred to as (Indirect, X)), the second byte of the instruction is
added to the contents of the X index register, discarding the carry_
The result of this addition points to a memory location on page zero
whose contents is the low order eight bits of the effective address.
The next memory location in page zero contains the high order eight
bits of the effective address. Both memory locations specifying the
high and low order bytes of the effective address must be in page zero.
INDIRECT INDEXED ADDRESSING - In indirect indexed addressing
(referred to as (Indirect). Y), the second byte of the instruction points
to a memory location in page zero. The contents of this memory location is added to the contents of the Y index register, the result being
the low order eight bits of the effective address. The carry from this
addition is added to the contents of the next page zero memory location, the result being the high order eight bits of the effective address.
ABSOLUTE INDIRECT - The second byte of the instruction contains
the low order eight bits of a memory location. The high order eight
bits of that memory location is contained in the third byte of the
instruction. The contents of the fully specified memory location is
the low order byte of the effective address. The next memory location
contains the high order byte of the effective address which is loaded
into the sixteen bits of the program counter.

I
I

~-·

I
. .

NMI

P07.
P06
P05
P04
P03
P02
'p01
POO
XTLI
XTLO

m\m*:!:~;

CO.IIIII

0.08: TV~'i

iD.Ui

0.011

!!;!!!
11.011

O.IM

!!:!!!! TY~..

~L. ,:::=~~
C;"211 MMI

III MMI

:!!: ::::00

MMI

VSS

VCC
PBO

PC7
PC6

PB1
PB2

PC5

PB3

PC4

PB4

PC3

PB5

PC2

PB6

PC1
PCO

CNTR

EQUAL "'~~~CUM.
P.loo'l TOL
C2.MMMI

I.

NOTE:

Pin NO.1" in

oymbOU.... _

RES
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

........ftc.,.,.... .......n
'" fMHmeI _'-nUtlo

~bging Diagram

TIMING CHARACTERISTICS

PB7

SPECIFICATIONS
Maximum Ratings
Rating

Symbol

Supply Voltage
Input Voltage

VCC
V.

Operating Temperature Range

T

Unit

Value

In

-0.3 to +7.0

Vdc

-0.3 to +7.0

Vdc

°c
o to +70

Commercial
Industrial
Storage Temperature Range

T

-40 to +85
·55 to + 150

stg

°c

This deVice contains circuitry to protect the inputs against damage due to high static voltages, however, It IS adVised that normal precautions be
taken to avoid application 01 any voltage higher than maximum rated voltages to this circuit.

Static D.C. Characteristics (V CC - 5V ±.10% for R6Soo/1, VCC - SV ±.S" for R6500/1A)
Characteristic
Power Dissipation (Outputs High)
OoC to+70 0 C
-40 0 C to +8SoC
RAM Standby Voltage (Retention Mode)
RAM Standby Current (Retention Mode)
OoC to +70 0 C
-40 0 C to +8SoC
Input High Voltage (Normal Operating Levels)
Input Low Voltage (Normal Operating Levels)
Input Leakage Current
Yin = 0 to S.O Vdc
RES,NMI
Input High Voltage (XTLI)
Input Low Voltage (XTLI)
Input Low Current
(VIL = 0.4 Vdc)
Output High Voltage
(VCC = min,lLoad - ·100 "Adc)
Output High Voltage
(VCC= min)
Output Low Voltage
(VCC = min,lLoad - 1.6 mAdc)
Output High Current (Sourcing)
(VOH = 2.4 Vdc)
Output Low Current (Sinking)
(VOL = 0.4 Vdc)
Input Capacitance
(V in ·0, TA = 2S o C, I · 1.0 MHz)
PA, PB, PC, PD, CNTR
XTLI, XTLO
Output Capacitance
(Vin' 0, TA = 25 0 C, f = 1.0 MHz)
I/O Port Resistance
PAO·PA7, PBO·PB7, PCO·PC7,
PDO·PD7, CNTR

Symbol

Min

Typ

Max

-

Soo
550

-

Po

-

-

3.S

VRR
IRR

-

-

VCC
+0.8

±'1.0

±2.5

+4.0
-0.3

-

VCC
+0.8

Vdc
Vdc

-

·1.0

·1.6

mAde

VOH
VCMOS

Vdc
mAdc

-

+2.0
-0.3

VIH
VIL
liN

VIHXT
VILXT
IlL

mW

VCC

10
12

-

Unit

VOL

-

-

·2.4
VCC·30%

-

-

Vdc
Vdc
"Adc

10H

-

Vdc
Vdc

+0.4

Vdc

-

·100

"Adc

10L
1.6

-

-

-

-

-

10
50

-

;0
11.S

mAdc
pF

Cin

Cout

-

3.0

RL

6.0

pF

Kn

NOTE: Negative sign indicates outward current flow, positive indicates inward flow.

AC Characteristics (V CC - 5V ±.10% for R65oo/1. VCC· 5V ±.5" for R65ool1Al
1 MHz
Parameter
XTLI Input Clock Cycle Time
Internal Write to Peripheral Data Valid (TTL)
Internal Write to Peripheral Data Valid (CMOS)
Peripheral Data Setup Time
Count and Edge Detect Pulse Width

2MHz

Symbol

Min

Max

Min

Max

TCYC
T pDW
T
CMOS
T pDSU
Tpw

0.500

5.0

0.2S0

5.0

1.0

0.5

Unit
"sec:

"sec

2.0

1.0

400

200

"sec:
nsec:

1.0

0.5

"sec:

I

,-----,---,---r-----r---r---r--r----,--,,----y----y---r----, ..OCESSO.SUruS
IMMEDIATE

QP n

AoC

(4)(1) 69

AND

(1129

ASl

2

60

•

lEflO'AGE

OP n

•

ACCUM

(IND,X)

fiND). Y

1 'AGE. X

= 0 (2)

B C S

BRANCH ON C

=

AIS.X

AIS,'

• OP

QP n

flnATlvE

n

,

2

32532

1 'AGE,' CODES

,op

n

•

3t 52
IE

~ ~ ~

N II

73

!~~

MHEMONIC

Nv • • • • lC

ADC

N ••••• l.

AND

No

90

0

0

0

0

Z C

•

•

•

••

22

1 (21

BRANCHONZ = 1 121

•

2C

"

3 24

3

2

• •

BRANCHONN

=1

B N E

BAANCHONZ

=0

(2)

DC

2

2

8 P l

BRANCH ON N

=0

121

to

2

2

Bile

BRANCHONV

=0 m

v5

BRANCHQNV

= 1 (2)

BE

a

B I f

M,M,·

B M I

B

INDIRECT

OP n

~

06 5 2 0"

BRANCH ON C

a

OP n

c~-o

Bee

8 E

2

ABSOLUTE

•

(2)

BVS

7022

CLC

1821

CLC

CLo

06 2

CLo

C L

1

B8 21
C9 2
CPx

EO

2 CO "

2

3 C5

3

2

3 E4

3

2

3 C6

5

2

3

2

C L V

0

Cl 6

2 01

5

2 05 ..

2 00 ..

3 09"

2 DE

3

3

N

CE

(I)

49

2

N C

•

.

2 40 ..
EE

4C

JUMP TO NEW loe

I C

CMP

I C

CPx

I C

CJ 2
DEC

J

C L I

0

J

3

345

06 •

2

7

sq "

I
I

3

6C

5

3
J S R

LOX

1'1,.,9

2

(1J

A2

2

2 AE

(1)

AO

2

2 AC 4

4

o-~c

NOP

3 A5

3

2

3 A6

3

2

34.

5

305

3

Al

6

2

81

LOA

5
B6 4
2 Be

4.

2

1

3

ORA

092

0162115215

2

ca

3.'

08

31

..

I

ORA

tlHP

P L A

Z
5 + 1-5

R 0 L

LOY

I C

25E

NOPPERATION

Ms-P

P,l P

(RESTOREDI

t::t:=:5i-©:J

3265

I C

N

3665

73

IC

N
IRESTORED)

R T S
5 B C

A - M -

SEC

l-C

SED

1-0

C-

A

(1)

E9

2

2 EO ..

3 E5

3

Et

2

6

2

Fl

5' 2 F5 ..

2 FO ..

3 F9 ..

3

N V

Z(31

1
1

S E I

STA

38532

STy

38432

2 95
94
AA

2

1

BA

2

1

..

2 90 5

3 99

5

STA

3

STY

42

T A Y

I

T S X

Z
I

T X S

T

o.

T Y A

98
C1I

ADO 1 to "N"IF PAGE BOUNDARY IS CROSSED

C2I

ADD 1 TO"N"'F 8RANCHOCCURS TOSAME PAGE
ADO 2 TO UN" IF BRANCH OCCURS TO DIFFERENT PAGE

e31

CARRY NOT:: BORROW

141

IF IN DECIMAL MODE,Z FLAG IS INVALID
ACCUMULATOR MUST BE CHECKED FOR ZERO RESUl T

21

Z

N

M,
INDE-X Y
ACCUMULATOR
M

MEMORY PER EFFECTIVE ADDRESS
MEMORY PER STACK POINTER

SUBTRACT

M.

M'EMOR't8IT7

it:

A

PART NUMBER

DOCUMENT NO. 29000051 S
REV. 1. APRIL 1979

R6500/1E

R6S00 Microcomputer System
DATA SHEET SUPPLEMENT

R6S00/1 E EMULATOR DEVICE
INTRODUCTION

EXTERNAL FREQUENCY REFERENCE

To airl in designing R6500/1 microcomputer systems, Rockwell
has developed a PROM compatible, 64-pin, R6500/1 E Emulator
device. The architecture of the Emulator device is basically the
same as the R6500/1 except that the address, data, and associated
control lines are routed off the chip for connection to an external
memory_
The functions and operation of the Emulator device are identical to the R6500/1 with only some minor differences, described
herein. The R6500/1 data sheet (Document No. 2900051) contains the description of R6500/1 and R6500/1 common interface signals and functions.

The external frequency reference may be a crystal or a clock the RC option is not available in the Emulator device_

ORDERING INFORMATION
Order
Number

Package
Type

Frequency
Option

Temperature
Range

R6500/1EC

Ceramic

1 MHz

OOC to 70 0 C

R6500/1EAC

Ceramic

2 MHz

OOC to 70 0 C

SIGNAL DESCRIPTIONS

I/O PORT PULLUPS
The R650011 E has the internal 1/0 port pullup resistance only.

R6500/1 E DEVICE ADDITIONAL SIGNALS
Signal
Name

Pin
No.

RM

62

Read/Wrlte. The Read/Wrlt. output controls
the direction of data transfer between tha
R650011 E Emulator CPU and external memory. This line Is high when reading data from
memory and low when wrltlnll data to memory.

ROY

3

Ready. The Ready Input delays execution of
any cycle durinll which the ROY line Is low.
This ellows the user to halt or lingle step the
CPU on any cycle' except a write cycle. A negative tranlitlon to tha low ltate during the
o.

r

271.

DE
Cf

EXAMPLE 2: R6500/1 E Connected to Three PROMS (3K Bytes)
Memory Map

Connection Diagram
00
01
02
03

2708 NO.3
PROM

04

c------

OS

08
07
A.
Al
A2
A3

FFF

coo

BFF

2708 NO.2
PROM
2708

1------

NO.3

2708 NO.1
PROM

BOO

7FF

1
J

","o.21 TIMING REFERENCE

R6500/1 E DET AI LED MEMORY MAP
HEX

r.1~Ro~v~eC~'O-'~H~09h~-----------------'FFF}

Vector I.ow

fFE

RES Ve-ito; H-;g..

RES~w-

fFD
HC

NMI Vector H-'gh

FF8

NMI VeC1or~~_- _

fFA

IRQ

A/W

7FF
400

.______ . __ _

Unass~ned

\-:C"'"le-a,--;P'""A--=-l""'"'N-eg--;E'"""'d-e-=Oo--e'c-e.:t;;d---- Clear PAO Pas Edge .. ected

~

I

ROM

ADDRESS FROM
CPU

Unassigned
Regi~_

0':'(

TIMING FOR READING FROM MEMORY

~~

R650011 User Program
R6500/1E Extended Program Area 11)

Control

.,~'

(2)
(2)

08F
08E
08B
08A
089

~:::rr ~:~~tand Tra_"s_fe_,_La_'C_h_'O'----'c::::o:::.un"-"e::..'_----'\~ll:-4) ~:~
Upper Count

086

lower Latch

______

Upper Latch

PORT
PORT
PORT
PORT

0
C
B
A

Input/Output

ROY

085
084

____________

Unassigned

08l
082
081
080

SYNC

-_-===-__-J:~ }

L.U_se_'_R_A_M______-___
- _--_--_-_-_-

RAM(4)

NOTES
(1) Additional 1024 bytes are decoded for external memory addressing by
the R6500/1 E Emulator Device. This area can be used during debug,
but cannot be used in a masked ROM R6500/1.
(21 1/0 command only; i.e .• no stored data.
(31 Clears Counter Overflow - Bit 7 in Control Register
(4) CAUTION: The R65OOl1E allows RAM mapp;ng ;n,o 040-07F.
100-llF. 140-17F. 200-2lF. 240-27 F. lOO-llF. and 34P.l7F; as well as
OOO·03F. The production R6500/t, however allows RAM mapping only
at OOO-OlF.

--THAW

A/Vi

ADDAESS FADM
CPU

T MDS "t-----O-1

ELECTRICAL CHARACTERISTICS
(Vcc - 5.0~5%, Vss -

0

0, T A - 25 CI

Symbol

Characteristic

Input High Threshold Voltage

V

Min

Typ

Max

IHT

OO·tH, ROY,

Vss + 2.4

Input Low Threshold Voltage

Vde

V ILT

00.07, ROY,

Vss + OB

Three-State (011 Statellnput Current

Unit

Vde
~A

ITSI

(V - 0.4 to 2.4V, V CC - 5.25VI
00·07

10

Output High Voltage

V
OH

"LOAD - l00~Ade, VCC - 4.75VI
00.o7,SYNC,AO·All, RtW, ~2
Output Low Voltage

Vde

Vss + 2.4
VOL

"LOAD - 1.6 mAde, V CC - 4.75VI
00·07, SYNC, AO·Al1 , RIW,4>2

Vss + 0.6

Power 0 issipation

Po

Capacitance

C

1.20

0.75

Vde
W

pF

(V in - 0, T A - 25°C, I - 1 MHz)
ROY

Cin

10
15

Cout

12

DO-07
AQ·All, R/W, SYNC
_2

C~2

I/O Port Pull·up Resistance

RL

3.0

50

80

6.0

11.5

O'~"'''""O'~DO~~,
:~: t:: ~~:

:~:~ ::;: ~~I

~_~ I '~'~I~
: It~
J~l)MIN :~ ~ g:6~ ~~I
(3.05 MM)

(;~:40~Ml)OO Ii.

NOTE: PIN NO.1 IS IN LOWER LEFT CORNER WHEN
SYMBOLIZATION IS IN NORMAL

ORIE~TATION

Packaging Diagram

TO

C!.

kohm

DOCUMENT NO. 29000 D60
FEBRUARY, 1980

PART NUMBER

R6500/1EB
R6500 Microcomputer System
DATA SHEET

R6500/1 EB BACKPACK EMULATOR
INTRODUCTION
The Rockwell R6500/1 EB Backpack Emulator is the PROM
prototyping version of the 8-bit, masked-ROM R6500/1 one-chip
microcomputer_ Like the R6500/1, the R6500/1 EB is totally
upward/downward compatible with all members of the R6500
family_ The R6500/1EB is designed to accept standard 5-volt,
24-pin PROMs, EPROMs or ROMs directly, in a socket on top
of the Emulator. This packaging concept allows a standard
EPROM to be easily removed, re-programmed, then reinserted
as often as desired_
The R6500/1 EB has the same pinouts as the masked-ROM
R6500/1 microcomputer_ These 40 pins are functionally and
operationally identical to the pins on the R6500/1, with some
minor differences (described herein). The R6500/1 Microcomputer Data Sheet (Rockwell Document No_ 29000D51) includes
a description of the interface signals and their functions_ Whereas
the masked-ROM R6500/1 provides 2K bytes of read-only memory, the R6500/1 EB will address 3K bytes of external program
memory _ This extra memory accommodates program patches,
test programs or optional programs during breadboard and prototype development states_

ORDERING INFORMATION
ORDER
NUMBER
R6500/1 EB-1

MEMORY
CAPACITY
2K

R6500/1 EB-2

3K

R6500/1 EB-3

3K

R6500/1 EB-4

1K

TEMPERATURE
RANGE

2716,2516,
82S2708,
2316B
2532,2332,
82S2708
2732,
82S2708
2758,
82S2708

OOC to 70 0 C

0

OOC to 70 C
OOC to 70 0 C
OOC to 70 0 C

PRODUCT SUPPORT

Further, the SYSTEM 65 Microcomputer Development System
with R6500/1 Personality Module supports both hardware and
software development_ Complete in-circuit user emulation with
the R6500/1 Personality Module allows total system test and
evaluation_ With the optional PROM Programmer, SYSTEM 65
can also be used to program EPROMs for the development
activity_ When PROM programs have been finalized, the PROM
device can be sent to Rockwell for masking into the 2K ROM of
the R6500/1. In addition to support products, Rockwell offers
regularly-secheduled designers courses at regional centers_

All Rights Reserved
Printed In U.S A

"

:.

,

The available support products include:
•

COMPATIBLE
MEMORIES

The R6500/1 EB Backpack Emulator is just one of the products
that Rockwell offers to facilitate system and program development for the R6500/1. Additional support products include the
R6500/1 E, a 64-pin emulator device with interface lines for connecting external memory_ Another support product is the
R6500/1 Evaluation Module, which has 40 R6500/1-compatible
pins and provision for inserting external memory_

© Rockwell International Corporation 1980

. ...

•
•
•

SYSTEM 65 Microcomputer Development
System
PROM Programmer Module
1-MHz R6500/1 Personality Module
2-MHz R6500/1 Personality Module

•
•
•

1-MHz R6500/1 Emulator Device
2-MHz R6500/1 Emulator Device
R6500/1 Evaluation Module

PIN
PIN
PIN
PIN
PIN
PIN
PIN

S65-101
M65-040
M65-081
M65-082
R6500/1 EC
R6500/1 EAC
M65-089

FEATURES
•
•
•
•

•
•
•
•
,.
•
•
•
•
•
•

PROM version of the R6500/1
Completely pin compatible with R6500/1 single-chip
microcomputers
Profile approaches 40 pin DIP of R6500/1
Accepts 5 volt, 24 pin industry-standard EPROMs, PROMs,
ROMs
4K memories - 2532, 2732, 2332 (3K bytes addressable)
- 2K memories - 2716,2516, 2316B
1 K memories - 2758, 82S2708
Use as prototyping tool or for low volume production
3K bytes of memory capacity (1 K, 2K, 4K memories)
64 x 8 static RAM
Separate power pin for RAM
Software compatibility with the R6500 family
32 bi-directional TTL compatible I/O lines (4 ports)
1 bi-directional TTL compatible counter I/O line
16 bit programmable cO,unter/latch with four modes (jnterval
timer, pulse generator, event counter, pulse width measurement)
5 interrupts (reset, non-maskable, two external edge sensitive,
counter)
Crystal or extenal time base
Single +5V power supply

Specifications subJect to
change without notice

I

R6500/1EB CONFIGURATIONS

R6500/1EB BACKPACK MEMORY SIGNAL DESCRIPTIu.

The R6500/1 EB is available in four different versions, to accommodate
various 24-pin 1 K-, 2K- and 4K-memories. All four versions provide
04 bytes of RAM and I/O, as well as 24 signals to support the external
memory "backpack" socket. The 24 backpack signals differ somewhat
between versions (due to memory pin differences) but always consist
of the address bus (12 lines), the data bus (8 lines) and the DE, Vcc,
Vrr and Vss signals (one line each!. See Interface Diagram.

SIGNAL
NAME
DO-D7

9S-11S, Data Bus Lines. All instruction and data transfers
13S-17S take place on the data bus lines. The buffers driving the data bus lines have full three-state capability. Each data bus pin is connected to an input
and an output buffer, with the output buffer
remaining in the floating condition

The external memories must always occupy the upper 1 K of available
memory (addresses 800 through FFF) for implementation of interrupt
vectors. See Memory Map. The R6500/1 EB provides a read block to
the external memory where internal RAM or I/O are located at the
same addresses as that occupied by external memory.

AO-A9

lS·8S,
Address Bus Lines. The address bus lines are
23S,24S buffered by push/pull type drivers that can drive
one standard TTL load.

Al0

19S

EXTERNAL FREQUENCY REFERENCE

All

The external frequency reference may be a crystal or a clock - the
RC option is not available in the emulator device.

I/O PORT PULLUPS
The R6500/1 EB has the internal I/O port pullup resistance only.

PIN NO.

DESCRIPTION

Address Bus Line 10. This address line has the
same characteristics and functions as Lines AOA9. However, in the R6500/1 EB-4, pin 19S is
tied to Vss instead of to the address bus.
18S+21S Address Bus Line 11. This address line has the
same characteristics and function as Lines AO·A9.
In the R6500/1 EB-l and -4 versions, All is
inverted by a standard TTL inverter before reaching pin 18S. In the R6500/1EB-2, All is connected directly to pin 18S. In the R6500/1EB-3,
A 11 is routed to pin 21S and pin 18S is tied to
Vss.

20S

Memory Enable Line. This signal provides the
output enable for the memory to place information on the data bus lines. This signal is driven by
the R/W signal from the CPU and then inverted
by a standard TTL inverter, to form DE.

TEST MODE DELETED
The test mode of the R6500/1 is not available on the R6500/1EB.

R6500/1EB I/O PORT INITIALIZATION

Vcc

24S

Main Power Supply +5V. This pin is tied directly
to pin 30 (Vee).

Ports A, B, C, and D and the CNTR line in the R6500/1 EB are initialized to the logic high state two 02 clock cycles earlier than in the
R6500/1. The ~ line to the R6500/1 EB must, however, still be
held low for at least eight 02 clock cycles after Vcc reaches operating range. See timing diagram.

Vpp

21S

Main Power Supply +5V. This pin is tied directly
to pin 30 (Vce), except in the R6500/1EB·3,
where it is tied to A 11. During backup power,
power is supplied only to the RAM memory, and
not to the PROMs.

Vss

12S

Signal and Power Ground (zero volts). This pin
is tied directly to pin 12 (Vss).

RAM MAPPING
The R6500/1EB allows RAM mapping into 040-07F, 100-13F, 14017F, 200-23F, 240-27F, 300-33F and 340-37F, as well as 000-03F.
The production R6500/1, however, allows RAM mapping only at
000·03F. This means that a write to location 40, for example, will
write to location 0 in the R6500/1 EB, and to invalid RAM in the
R6500/1 production port.

INSERTED MEMORY

....
c_

o~

c

FFF

PROM

r-----

~~~

I
J

Program Memory

PROM

r------

800
7FF

PROM

I-----~j~~

Extended Program
} Memory

NOT USED
(1)

(8)

(8)

(8)

(8)

(6)

+ U U UU I
t~--------------~v~--------------~
(40 COMPATIBLE 6500/1 PIN-OUTS)

R6500/IEB Interface Diagram

I-----.~g:~
RAM & I/O
L..-________....I

000

'See R6S00/1EB Detailed Memory Map

Memory Map

I

R6500/1 EB DEVICE TIMING
1 MHz

I

Signal

Symbol

Min.

Max.

Unit

OE setup time from CPU

TOES

300

ns

Address setup time from CPU

T

300

ns

Memory read access time

T

525

ns

Data stabilization time

T

Data hold time - Read

ADS
ACC

150

ns

THR

10

ns

Address hold time

THA

30

ns

BE

T HOE

30

ns

TCYC

1.0

hold time

Cycle Time

RES

110
PORTS

I

~
~~ _

DSU

10.0

~2

8
clock
cycles mln,mum
_ _
_
_ _ _~~, -

~s

~

RES t"nsition window

~

Don't care state

~~~~------------------------------------~~

R6500/1EB~
R6500/1

"'~'TTT"<'''<'''<''''<'''<''''<'''<'''<'T'or<"'''''''''''''''--------------------'V--

R6500/1 EB I/O Port Initialization Timing Diagram
HEX

~1~Ro~ve-ct-or~H~ig~h----------------~FFFl

:R~1 ~:::: ~~~ =_~- _~~~~ ~~g PR~MS
__

NMI Vector High
NMI Vector low

FFB
FFA

~

ROMS

=~~

R6500/1 User Program

R6500I1EB Extended Program Area (11
7FF
___________________________
400

<

Unassigned

Control Register

>

OSf

Unassigned

-~08E
.~

Clear PAl Neg Edge Detected
Clear PAD Pas Edge Detected
and Transfer latch to Counter

~~atch

g::

(21
(31

089
088

~::;; ~:~~:

_---.ill.. g~

Lower latch
Upper Latch

085
084
Ml
_ _ _ _ _ 082
Ml
080

ro~D

PORT C
roRTB
roRT A
Unassigned

<

....U_se_r_R_A_M_ _ _ _ _ _ _ _ _ _ _--J

~~:

PHASE 2

(cP21 TIMING REFERENCE

InputlOutput

}

RAM(41

NOTES
(1) Additional 1024 bytes are decoded for external memory addressing by
the R6500/l EB Emulator Device. This area can be used during debug,
but cannot be used in a masked ROM R650011.
(2~ 1/0 command onlv; i.e., no stored data.
(l~ Clears Counter Overflow - Bit 7 in Control Register

ADDRESS FROM
CPU

(41 CAUTION: The R6500/1EB allows RAM mapping into 040-07F.
100-llF. 140-17F. 200-23F. 240-27F. lOO·llF. and 340-l7F; as well as
OOO-OlF. The production R6500/1, however allows RAM mapping only
at OOO-OlF.

R6S00/1 EB Detailed Memory Map

R6500!1 EB Timing Diagram

•

ELECTRICAL CHARACTERISTICS
(V CC = 5.0 ±5%. VSS = 0, T A

= 25°C)

Characteristic

Symbol

Input High Threshold Voltage

V

V
V

= 0.4

(V

to 2.4V, VCC

I

-

-

-

-

Vdc

Vdc

VSS + 0.8

/JA

V

= 100/J Adc, VCC
LOAO
00-07, AO-A11, OE
(I

-

10

-

-

OH

= 4.75V)
VSS + 2.4

Output Low Voltage

Vdc

VOL

(I
= 1.6 mAdc, VCC
LOAO
00-07, AO-A11, OE

= 4.75V)

Power Dissipation

Po

Capacitance

C

in

+2.4

TSI

00-07

= 0, T A

Unit

= 5.25V)

Output High Voltage

(V

SS

ILT

00-07
Three-State (Off State) Input Current

Max

IHT

00·07
Input Low Threshold Voltage

Typ

Min

-

-

-

0.80

Vdc

VSS + 0.6

W

1.30

pF

= 25 0 C, f = 1 MHz)

00-07
AO-A11
I/O Port PUll-up Resistance

-

-

C
in
C
out

-

RL

3.0

15
12

6.0

11.5

kohm

0
VRR
P07
P06
P05
PD4
P03
P02
POl
POO
XTLl
XTLO
VSS
PC7
PC6
PC5
PC4
PC3
PC2
PCl
PCO

40
39
38

0

10
11
12
13
14
15
16
17
18
19
20

A7. 1.
A6. 2.
A5. 3.
A4 •
4.
A3. 5.
A2 •
6.
Al •
7.
AO. 8.
DO •
9.
01 .10.
02.11.
VSS.12.

t;:;

:.:

U

Sl
Z

c;:
~

24 • •
23• •
22• •
21 • •
20 • •
19• •
18• •
17• •
16• •
15• •
14• •
13• •

vee
A8
A9
VPP/All

Of
Al0NSS
All/ATINSS
07
06
05
04
03

R6500!1 EB Pin Configuration

37
36
35
34
33
32
31
30
29

28
27
26
25
24
23
22
21

NMI
RES
PA-O
PA-l
PA·2
PA-3
PA-4
PA-5
PA·6
PA·7
vee
PBO
PBl
PB2
PB;J
PB4
PB5
PB6
PB7
eNTR

.300

OENOTES PIN NO. ,

~

r-~£:r1*~~~
.......
.....
T[T
ill


'"

R6500 Microcomputer System
PRODUCT PREVIEW

."I'"t

•

R6500/1-11Q ONE-CHIP MICROCOIVIPUTER
INTRODUCTION
The Rockwell R6500/1-11Q is a complete, high-performance 8-bit
NMOS-3 microcomputer on a single chip, and is compatible with all
members of the R6500 family.
The R65OO11-11Q consists of an enhanced 6502 CPU, an intemal
clock oscillator, 3072 bytes of Read-Only Memory, 192 bytes of
Random Access Memory (RAM) and versatile interface circuitry.
The interface circuitry includes two 16-bit programmable timer/
counters, 56 bidirectional input/output lines (including four edgesensitive lines and input latching on one' 8-bit port), a full-duplex serial I/O channel, ten interrupts and bus expandability.

DEVELOPMENT SUPPORT
To allow prototype circuit development, Rockwell oHers a PROMcompatible 54-pin Emulator device. This device, the R65OO12-11,
provides all R6500/1-11Q interface lines (except Ports E, F and G),
plus the address bus, data bus and control lines to interface with external memory. The R6500/2-11 may also be used as a CPU-RAMI/O counter device in multichip systems.

192· 8 RAM

13072

• a ROM

II
I

PORTC

~
~

PCO.PC71(AO;A3. A12.
RIW. A13 VEMA)"

<

a::;> POO·PD71(DATAIADDR
BUS (A4·Allj)

.SO(PA6)"

~~

~ ~

<;H::;>PEO·PE7

PORT F
<;8~PFO.PF7

'MULTIPLEXED FUNCTIOfi PINS (Software Salectable)

Interface Diagram

F¥.O-PA7 (PAD. PAl.

PA2. PA3:
EDGE DETECTS).
<:;: S;;>P80-P87
(LATCHED INPUTS)
~DS(PAD)

~~7

<:;:8;;>
A
AD:c I2.AI5
~SYNC

I ~X81~
L:::.::.J

• Serial port
-Full-duplex asynchronous operation mode
-Synchronous shift registermode
-Selectable 5- to 8-bit characters
-Wake-up feature
-Programmable bit rates to 62.5 bits/sec (@ 2 MHz)

DATA STROBE)"
<:;:e;;>PCO-PC7/AI3. AI •.
(Extended address mode)"

~TD

<:;:

~

8;;>rD~~~DR
BUS (M·Al1))

~CA(PA4)'
~CB(PA5)'
~SO(PA6)'
~SI(PA7)'

• Ten interrupts
-Reset
-Non-maskable
-Four external, edge-sensitive
-Two counter
-Serial data received
-Serial data transmitted

Interface Diagram

o Rockwell Inlemational Corpoallon 1980
All Rights Reserved
Printed in U.S.A.

....

.m

z

cm
C

3:

n
:u
o

J

o
o

m

m

o
:u

• Flexible clock circuitry
-2-MHz or 1-MHz internal operation
-Internal clock with external XTAL at two or four times internal frequency
-External clock input divided by one, two or four
• 1 p's minimum instruction execution time
• NMOS-3 silicon gate, depletion load technology
• Single +5V power supply

'MULTIPlEXED FUNCTIONS PINS (Software Selectable)

m
)(.

• 16 mW stand-bY power for 32 bytes of the 192-byte RAM
• 64-pin QUIP

Specifications sdlject 10
chenge~noIlce

Document No, 29000 D66

November 1980

ELECTRICAL SPECIFICATIONS
llulmum RatIng.
Rating

Symbol

Supply Voltage

Value

Unit

Vee

-0.3 to +7.0

Vdc

IIllUl Voltage

Vln

-0.3 to +7.0

Vdc

Operating Temperatura Range. Commercial
Industrial

T

Oto+70
-40 to +85

·C

Storage Temperatura Range

Tstg

-55 to +150

"C

This device contains cirruitry to protect the inputs against damage due to high static voltages. however. it is adVised that nonnal precautions be taken to avoid application
of any voltage higher than maximum rated voitages to this drcuit.
D. C. Charac:tart.tlca (Vee

= 5V :!:5% Vss =

0)

Characteristic

Min

Symbol

Power Dissipation (OJIputs High)
Commercial @ 25"C
IrdJstrial @ 25"C

Po

-

RAM Standby Voltage (Retention Mode)

V RR

3.0

RAM Standby Current (Retention Mode)
Commercial @ 25"C
IrdJstrial @ 25·C

IRR

Input High Voltage Except XTLI
Input High Voltage (XTLI)

Max

Typ

Unit

1000
1200

mW

-

Vee

Vdc

-

4
5.2

-

V IH

+2.0

-

Vee

Vde

V IH

+4.0

Vee

Vdc

Input Low Voltage

Vll

-0.3

-

+0.8

Vbc

Input Leakage Current (RES. NMI)

liN

:t1.0

:t2.5

V~

mWde

-

p.Adc

= Ot05.0Vdc

Input Low Current Af.. PB. PC. PO
(Vll

-

III

-

-1.0

-1.8

mWde

VO H

+2.4

-

-

Vdc

VOL

-

-

+0.4

Vdc

= 0.4 Vdc)

Output High Voltage Except XTLO
~Load

= .100 ,.Adc)

Output Low Voltage
~Load

= 1.6 mAde)

Input Cepadtance

pF

Cln

(Vln-O. T A = 25"C. t= 1.0 MHz)
~PB.PC.PD
XTLI. XTLO

-

1,0 Pod Pull-Up Resistance
Af.O.f¥.7. PBO-PB7. PCO-PC7. POO-PD7

Rl

-

-

50

3.0

6.0

11.5

10

Kn

NOTE: Negative sign indicates outward current now. positive indicates inward flow.
N;

Charactart.tIca (Vee

= 5V :t5"1o Vss = 0)
2 MHz

1 MHz
Parameter

Symboi

Min

Max

Min

Max

Unit

XTLI Input Clock Cycle Time
Internal Write to Peripheral Data Valid (TTL)
Peripheral Data Setup Time
Count and Edge Detect Pulsa WIdth

Teye

0.500
1.0

5.0

0.250

5.0

,.sac
,.sac

TPDW
TPDsu
Tpw

400
1.0

0.5
200
0.5

nsac

,.sac

R6500

I/O
DEVICES

•

•

PART NUMBER

DOCUMENT NO. 29000 040
REVISION 2. OCT. 1978

R6520

:'1' Rocl(~eu'
•

~;

'.;- ~~
~ ~

III·

I

•

"

.

.

R6S00 Microcomputer System

-

DATA SHEET

PERIPHERAL INTERFACE ADAPTER (PIA)
DESCRIPTION

FEATURES

The R6520 Peripheral Interface Adapter is designed to solve a
broad range of peripheral control problems in the implementation
of microcomputer systems. This device allows a very effective
trade-off between software and hacdware by providing significant
capability and flexibility in a low cost chip. When coupled with
the power and speed of the R6500 family of microprocessors,
the R6520 allows implementation of very complex systems at a
minimum overall cost.

•

Control of. peripheral devices Is handled primarily through two
a-bit bidirectional ports. Each of these lines can be programmed
to act as either an Input or an output. In addition, four peripheral
control/interrupt input lines are provided. These lines can be used
to interrupt the processor or for "hand-shaking" data between the
processor and a peripheral device.

High performance replacement for Motorola/AMI/MOSTEKI'
Hitachi peripheral adapter.

•

N channel, depletion load technology, single +5V supply.

•

Completely Static and TTL compatible.

•

CMOS compatible peripheral control lines.

•

Fully automatic "hand-shake" allows positive control of data
transfers between processor and oerioheral devices.

•

Commercial, Industrial and military temperature range versions.

Ordering Information
Order Number: R6520 - -

L Temperature Range:
0

No suffix· = OOC to +70 C
0
0
E = -40 C to +85 C
!Industrial)
0

MT = -55°C to +125 C
(Military)
M" MIL-STD-883,
Class B
Package:
C .. Ceramic
P .. Plastic
(Not Available for
M or MT suffix)

i"RQA
IAaB
ASD
AS1

RES
DO
01
02
03
04
OS
06
07
ENABLE
CS1

Cs2
CSO
R/W

Frequency Range:
No suffix = 1 MHz
A" 2MHz

......

.....

.

>

R6500
MICROPROCESSOR
(CPU)
CONTROL

........

.....

...

.....

.....

Rockwell International Corporation 1978
All Rights Reserved
Printed in U.S.A.

l>

nm
l>

C

l>

-);

."

CONTROL

8BIT
DATA PORT

8 BIT
DATA PORT

PERIPHERAL
DEVICES PRINTERS,
DISPLAYS. ETC.

CONTROL

Basic R6520 Interface Diagram

@

-n

::D

R6520

.... ;>

::D

....m

...

-

:2
....
m

."

Pin Configuration

NOTE: Contact your local Rockwell Representative
concerning availability.

8 BIT
DATA BUS

CA1
CA2

VSS

PAD
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBD
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CB1

Specifications subject to
change without notice

-

I

SUMMARY OF R6520 OPERATION
See Rockwell Microcomputer Hardware Manual for detailed description of R6520 operation .

•

CA1/CB1 Control
CRA (CRB)
Active Transition
of Input Signal·

IRQA (lROB)
Interrupt Outputs

Bit 1

Bit 0

0

0

Negative

Disable·- remain high

0

1

Negative

Enable - goes low when bit 7 in CRA (CRB) is set by active transition of signal on CA 1 (CB1)

1

0

Positive

Disable - remain high

1

1

Positive

Enable - as explained above

·Note:

Bit 7 of CRA (CRB) will be set to a logic 1 by an active transition of the CA 1 (CB1) signal. This is independent of the state
of Bit 0 in CRA (CRB).

CA2/CB2 Input Modes
CRA (CRB)
IROA(lROB)
Interrupt Output

Bit 5

Bit4

Bit 3

Active Transition
of Input Signal·

0

0

0

Negative

Disable - remains high

0

0

1

Negative

Enable - goes low when bit 6 in CRA (CRB) is set by active transition
of signal on CA2 (CB2)

0

1

0

Positive

Disable - remains high

0

1

1

Positive

Enable - as explained above

Note:

Bit 6 of CRA (CRB) will be set to a logic 1 by an active transition of the CA2 (CB2) signal. This is independent of the
state of Bit 3 in CRA (CRBI.

CA2 Output Modes
CRA
Bit 5

Bit 4

Bit 3

1

0

0

"Handshake"
on Read

CA2 is set high on an active transition of the CA 1 interrupt input signal and set low by
a microprocessor "Read A Data" operation. This allows positive control of data
transfers from the peripheral device to the microprocessor.

1

0

1

Pulse Output

CA2 goes low for one cycle after a "Read A Data·' operation. This pulse can be used
to signal the peripheral device that data was taken.

1

1

0

Manual Output

CA2 set low

1

1

1

Manual Output

CA2 set high

Mode

Description

CB2 Output Modes
CRB
Bit 5

Bit 4

Bit 3

Description

1

0

0

"Handshake"
on Write

CB2 is set low on microprocessor 'Write B Data" operation and is set high by an active
transition of the CBl interrupt input signal. This allows positive control of data transfers from the microprocessor to the peripheral device.

1

0

1

Pulse Output

CB2 goes low for one cycle after a microprocessor "Write B Data" operation. This
can be used to Signal the peripheral device that data is available.

1

1

0

Manual Output

CB2 set low

1

1

1

Manual Output

CB2 set high

Mode

A.C. CHARACTERISTICS
Read Timing Characteristics (Loading 130 pF and one TTL load)
2MHz

1 MHz
Max

Min

Max

Unit

180

-

-

395

90

-

ns

-

190

300

ns

-

150

-

ns

10

-

ns

-

1.0

J.ls

1.0

-

1.0

-

0.5

-

2.0
25

Symbol

Min

Delay Time, Address valid to Enable positive transition

T AEW

Delay Time, Enable positive transition to Data valid on bus

TEDR
T pDSU

Characteristics

Peripheral Data Setup Time

10

Data Bus Hold Time

THR

Delay Time, Enable negative transition to CA2 negative transition

Rise and Fall Time for CA 1 and CA2 input signals

TCA2
T RS1
\,t f

Delay Time from 9A 1 active transition to CA2 positive transition

T RS2

Rise and Fall Time for Enable input

trE' tfE

Delay Time, Enable negative transition to CA2 positive transition

0.5

J.ls

0.5

J.ls

-

1.0

J.ls

-

25

ns

•

Write Timing Characteristics
2 MHz

1 MHz
Characteristics

Symbol

Min

Max

Min

Max

Unit

0.235

Enable Pulse Width

TE

0.470

25

25

J.ls

Delay Time, Address valid to Enable positive transition

T AEW

180

-

90

-

ns

T DSU

300

-

150

-

ns

Delay Time, Read/Write negative transition to Enable positive
transition

TWE

130

-

65

-

ns

Data Bus Hold Time

T HW

10

-

10

-

ns

Delay Time, Enable negative transition to Peripheral Data valid

T pDW

-

1.0

-

0.5

J.ls

Delay Time, Enable negative transition to Peripheral Data valid
- 30%) PAO·PA7, CA2
CMOS (V
CC
Delay Time, Enable positive transition to CB2 negative transition

T CMOS

-

2.0

-

1.0

J.ls

-

1.0

-

0.5

J.ls

0.75

J.ls
J.ls

Delay Time, Data valid to Enable negative transitio~

Delay Time, Peripheral Data valid to CB2 negative transition

TCB2
T
DC

Delay Time, Enable' positive transition to CB2 positive transition

T RS1

-

1.0

-

0.5

Rise and Fall Time for CB 1 and CB2 input signals

tr,t f

-

1.0

-

0.5

J.ls

Delay Time, CB1 active transition to CB2 positive transition

T RS2

-

2.0

-

1.0

J.ls

0

PEAtPHEAAL.---,-,"'\.;~,.......-t--+----+------­

1.5

0

-----"=5-'''--==F~---t----~::__
_______

D.'V

.vcc_~

DATA

PERIPHERAL
DATA

-----,1-':.:;-----4------

cs,
IPULSEOUTI

CAl
IPUl.SEOUn

-----------~,,.I,-i
7~·~:;..~x===:.::
FtT RS2

\ ....______,-J.ovr-:::

Read Timing Characteristics

______~I-------·'·....·,--t= t- . :::

-----;-l-------:"T::.:..:.:~~o.V

IHAN~~~

. .KEI -------.\.ov

Write Timing Characteristics

2.0,:.::

SPECIFICATIONS
Maximum Ratings

I

Symbol

Rating
Supply Voltage
Input Voltage

VCC
V.,n

Operating Temperature Range

T

Value

Unit

·0.3 to +7.0

Vdc

·0.3 to +7.0

Vdc

°c

Commercial

o to +70

Industrial

·40 to +85

Military

·55 to +125

Storage Temperature Range

T

I

°c

·55 to + 150

STG

This device contains circuitry to protect the inputs against damage due to high static voltages, however, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this circuit.

Static D.C. Characteristics
0
(VCC = 5.0V ± 5%, VSS = 0, TA = 25 C unless otherwise noted)
Characteristic

Symbol

Input High Voltage (Normal Operating Levels)

V

Input Low Voltage (Normal Operating Levels)

IH
V IL

Input Threshold Voltage

V

Input Leakage Current

I.,n

IT

V. =Ot05.0Vdc
on
R/W, Reset, RSO, RS1, CSO, CS1, CS2, CAl, CB1,<%>2
Three·State (Off State Input Current)
(V in = 0.4 to 2.4 Vdc, V CC = max)
Input High Current
(V
= 2.4 Vdc)
IH
Input Low Current
(V = 0.4 Vdc)
IL
Output High Voltage
(V CC = min, ILoad = ·100 ~Adc)

00·07, PBO·PB7, CB2

O

PAO·PA7, CA2
IlL
PAO·PA7, CA2
V

OH

VOL

-

·0.3
0.8

Max

Unit

-

VCC
+0.8

Vdc

-

2.0

Vdc

-

±1.0

±2.5

-

±2.0

±10

·100

·250

-

-

·1.0

·1.6

Vdc

~Adc

~Adc

~Adc

mAdc

2.4

-

-

-

·100

·1000

-

~Adc

·1.0

·2.5

-

mAdc

+0.4

Vdc
Vdc

IOH

= 1.5 Vdc, the current for driving other than
TTL, e.g., Darlington Base)
PBO·PB7, CB2

Output Low Current (Sinking)
(V OL = 0.4 Vdc)
Output Leakage Current (Off State)

Typ

IIH

Output Low Voltage
(V
= min, I
= 1.6 mAde)
CC
Load
Output High Current (Sourcing)
(V OH = 2.4 Vdc)
(V

I
TSI

Min
+2.0

IOL
IROA, IROB

I

off

Power Dissipation

Po

Input Capacitance
0
(V in ·0, T A = 25 C, f = 1.0 MHz)
00·07, PAO·PA7, PBO·PB7, CA2, CB2
R/W, Reset, RSO, RS1, CSO, CS1, CS2,
CA1,CB1,<%>2

Cin

Output Capacitance
(V in · 0, T A = 25 0 C, f = 1.0 MHz)

Cout

1.6

-

-

mAdc

-

1.0

10

~Adc

200

500

mW

-

-

-

10
7.0
20

-

-

10

pF

-

NOTE: Negative sign indicates outward current flow, positive indicates inward flow.

pF

PART NUMBER

R6522

:'1,1" R~CkW~1I ;
•

...",

'.

.

\

-

'I

.

R6500 Microcomputer System
DATA SHEET

VERSATILE INTERFACE ADAPTER (VIA)
•
•
•
•
•
•

Two 8-Bit Bidirectional I/O Ports
Two 16-Bit Programmable Timer/Counters
Serial Data Port
Single +5V Power Supply
TTL Compatible
CMOS Compatible Peripheral Controi Lines

•

•
•

The R6522 Versatile Interface Adapter (VIA) is a
very flexible I/O control device. In addition, this device contains 3 pair of very powerful 16-bit interval
timers, a serial-to-parallcl/parallel-to-serial shift register and input data latching on the peripheral ports.
Expanded handshaking capability allows control of
bi-directional data transfers between VIA's in multiple
processor systems.

Expanded "Handshake" Capability Allows Positive
Control of Data Transfers Between Processor and
Peripheral Devices
Latched Output and Input Registers
1 MHz and 2 MHz Operation

be programmed as either an input or an output. Several
peripheral I/O lines can be controlled directly, from
the interval timers for generating programmable frequency square waves or for counting externally generatp.d pulses. To facilitate control of the many powerful features of this chip, an interrupt flag register, an
interrupt enable register and a pair of function control registers are provided.

Control of peripheral devices is handled primarily
through two 8-bit bi-directional ports. Each line can

INTERRUPT
CONTROL

0)

UI
N
N

<
m
:JJ

en

»

:! .!
rm
2

~------------------------------------- ~

-I
m
:JJ."

INPUT LATCH
IIRAI

FLAGS
IIFRI

':JJ

ENABLE
IIERI

PORTA

»'
n

m

»
c

DATA
BUS
PERIPHERAL
(PCRI

1------------------

AUXILIARY
(ACR)

I-----------------~.

CAl
CA2

l>
"'CJ

-I

m

. FUNCTION
CONTROL

:JJ

RES

Rm
02
CSI

LATCH
(TlL·HI

:

i

LATCH
(TlL·LI

-------"t------C~~~~~R ! C~~~.~~R

1 - - - - - - 4......- - - - - - - - - CB 1

....._--......1-----.-.----------_

CB2

TIMER 1

CS2

RS2

PORTB

RSJ

Figure 1. R6522 Block Diagram

Rockwell International Corporation 1981
All Rights RElserved
Printed in U.S.A.

Document No. 2tOO 047
Rev. 3, February , . ,

-<
-l>

I

R6522/R6522A
SPECI F ICATIONS

Maximum Ratings
Rating

Symbol

Supply Voltage
Input Voltage
Operating Temperature Range
Commercial
Industrial
Military
Storage Temperature Range

VCC
VIN
T

Value

Unit

to +7.0
to +7.0

·0.3
·0.3

Vdc
Vdc
°c

o to +70
TSTG

-40
·55
·55

to +85
to +125
to +150

°c

This device contains circuitry to protect the inputs against damage due to high static voltages. However. it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages.

ELECTRICAL CHARACTERISTICS (Vee
Symbol

= 5.0V ± 5%, TA = 0-70°C unless otherwise noted)

Characteristic

Min.

Max.

Unit

VIH

Input High Voltage (all except <1>2)

2.4

Vee

V

VeH

Clock High 'voltage

2.4

Vee

V

VIL

Input Low Voltage

-0.3

0.4

V

liN

Input Leakage Current - VIN = 0 to 5 Vdc
RM, RB", RSO, RS1, RS2, RS3, CS1, CS2,
CA1,2

-

±2.5

p.A

ITSI

Off·state Input Current - VIN = .4 to 2.4V
Vee = Max, DO to 07

-

±10

p.A

IIH

Input High Current - VIH = 2.4V
PAO-PA7, CA2, PBO-PB7, CB1, CB2

-100

-

p.A

IlL

Input Low Current - VIL = 0.4 Vdc

-

-1.6

mA

PAO-PA7,CA~PBO-PB~CB1,CB2

VOH

Output High Voltage
Vec = min, lload = -100 p.Adc
PAO-PA7, CA2, PBO-PB7, CB1, CB2

2.4

-

V

VOL

Output Low Voltage
Vee = min, lload = 1.6 mAdc

-

0.4

V

IOH

Output High Current (Sourcing)
VOH = 2.4V
VOH = 1.5V (PBO-PB7)

-100
-1.0

-

p.A
mA

IOL

Output Low Current (Sinking)
VOL = 0.4 Vdc

1.6

-

mA

IOFF

Output Leakage Current (Off state)
IRO

-

10

p.A

CIN

Input Capacitance - TA = 25°C, f = 1 MHz
(RM, fIT"S, RSO, RS1, RS2, RS3, CS1, CS2,
00-07, PAO-PA7, CAl, CA2, PBO·PB7)

-

7.0

pF

-

10
20

pF
pF

(CB1, CB2)
(<1>2 Input)
COUT

Output Capacitance - TA = 25°C, f = 1 MHz

-

10

pF

Po

Power Dissipation

-

700

mW

R65221R6522A
VCC

R~fJ2

--------._--......- - 1 (

~--_4t------

Figure 2. Test Load (for all Dynamic Parameters)

v.,
CLOCK

CHIP SELECTS
RE~ISTER SELECT~.

RIW

PERIPHERAL

DATA

2.0y
DATA BUS - - - - - - - - - - - - . . . . (

0.8y

Figure 3. Read Timing Characteristics

READ TIMING CHARACTERISTICS (FIGURE 3)

R6522
Parameter

Symbol

R6522A

Min.

Max.

Min.

Max.

1

50

0.5

50

iJ.s

180

-

90

-

ns

0

-

0

-

ns

300

-

300

-

ns

-

200

ns

10

-

ns

TCY

Cycle Time

TACR

Address Set·Up Time

TCAR

Address Hold Time

TpCR

Peripheral Data Set·Up Time

TCDR

Data Bus Delay Time

-

340

THR

Data Bus Hold Time

10

-

NOTE: tr, tf = 10 to 30ns.

Unit

R6522/R6522A

"

CLOCK

CHIP SELECTS.
REGISTER SELECTS

RIW

DATA

BUS

PERIPHERAL
DATA

Figure 4. Write Timing Characteristics

WRITE TIMING CHARACTERISTICS (FIGURE 4)

R6522
Symbol

Parameter

R6522A

Min.

Max.

Min.

Max.

1

50

0.50

50

J,1s

J,1s

Unit

Tcy

Cycle Time

Tc

92 Pulse Width

0.44

25

0.22

25

TACW

Address Set-Up Time

180

-

90

-

ns

TCAW

Address Hold Time

0

-

0

-

ns

180

-

90

-

ns

0

-

0

-

ns

300

-

200

ns

10

-

TwCW

R/W Set-Up Time

Tcww

R/W Hold Time

Tocw

Data Bus Set·Up Time

THW

Data Bus Hold Time

10

-

Tcpw

Peripheral Data Delay Time

-

1.0

-

1.0

J,1s

TCMOS

Peripheral Data Delay Time
to CMOS Levels

-

2.0

-

2.0

J,1s

NOTE: tr, tf

=

10 to 30ns.

ns

R6522/R6522A
PERIPHERAL INTERFACE CHARACTERISTICS
Symbol

Min.

Max.

Unit

Figure

-

1.0

p.s

-

Delay Time, Clock Negative Transition to CA2 Negative
Transition (read handshake or pulse mode)

-

1.0

p.s

5a,5b

TRSl

Delay Time, Clock Negative Transition to CA2 Positive
Transition (pulse mode)

-

1.0

p.s

5a

TRS2

Delay Time, CA 1 Active Transition to CA2 Positive
Transition (handshake mode)

-

2.0

p.s

5b

TWHS

Delay Time, Clock Positive Transition to CA2 or CB2
Negative Transition (write handshake)

0.05

1.0

p.s

5c,5d

TDS

Delay Time, Peripheral Data Valid to CB2 Negative
Transition

0.20

1.5

p.s

5c,5d

TRS3

Delay Time, Clock Positive Transition to CA2 or CB2
Positive Transition (pulse mode)

-

1.0

p.s

5c

TRS4

Delay Time, CA 1 or CB1 Active Tran~ition to CA2 or
CB2 Positive Transition (handshake mode)

-

2.0

p.s

5d

T21

Delay Time Required from CA2 Output to CA 1
Active Transition (handshake mode)

400

-

ns

5d

TIL

Set-up Time, Peripheral Data Valid to CA 1 or CB1
Active Transition (input latching)

300

-

ns

5e

TSRl

Shift-Out Delay Time - Time from 92 Falling Edge
to CB2 Data Out

ns

5f

ns

5g

Characteristic

t r , tf

Rise and Fall Time for CA 1, CB 1, CA'2, and CB2
Input Signals

TCA2

~

~!

-

300

Shih-In Setup Time - Time from CB2 Data In to
92 Rising Edge

300

TSR3

External Shift Clock (CB1) Setup Time Relative To
¢;2 Trailing Edge

100

Tcy

ns

59

TlPw

Pulse Width - PB6 I nput Pulse

2

-

p.s

5i

Tlcw

Pulse Width - CB1 Input Clock

2

-

p.s

5h

liPS

Pulse Spacing - PB6 Input Pulse

2

-

p.s

5i

Pulse Spacing - CB1 Input Pulse

2

-

p.s

5h

----

IICS

I

-

:

I

•

R6522/R6522A

CA2
"DATA TAKEN"

0.8v

teA2

Figure 5a. CA2 Timing for Read Handshake. Pulse Mode

CA2
"DATA TAKEN"

CAl
"DATA READY"

L
Figure 5b. CA2 Timing for Read Handshake. Handshake Mode

WRITE ORA. ORB
OPERATION

CA2. CB2
"DATA READY"

I------tos - - - - _ 1
PA. PB
PERIPHERAL
DATA

Figure 5c. CA2. CB2 Timing for Write Handshake. Pulse Mode

6

ACTIVE
TRANSITION

R65221R6522A

WRITE ORA. ORB
OPERATION

CA2. CB2
··DATA READY··

1 - - - - - - 'os - - - - - i
PA. PB
PERIPHERAL
DATA

2.0v

o 8v

CAl. CBl
"DATA TAKEN··

Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode

PA. PB
PERIPHERAL
INPUT DATA

CAl. CBl
INPUT LATCHING
CONTROL

_____________._'L_=x_-' :.;...::_____________
LACTIVE
TRANSITION

Figure 5e. Peripheral Data Input Latching Timing

;'2

CB2
SHIFT DATA
(OUTPUT)

CBl
SHI FT CLOCK
(INPUT OR
OUTPUT)
DELAY TIME MEASURED FROM THE FIRST 02
FALLING EDGE AFTER CBl FALLING EDGE

Figure Sf. Timing for Shift Out with Internal or External Shift Clocking

R6522/R6522A

CB2
SHIFT DATA
IINPUTI

CBl
SHIFT CLOCK
IINPUT OR
OUTPUll
SETUP TIME MEASURED TO THE FIRST '02
RISING EDGE AFTER CBl RISING EDGE

Figure 5g. Timing for Shift In with Internal or External Shift Clocking

CBl
SHIFT CLOCK
INPUT

Figure 5h. External Shift Clock Timing

PBG
PULSE COUNT
INPUT

o.,~'"'

\'"
i

1------

IIPW

------1

1----------.-

Figure 5i. Pulse Count Input Timing

"'\~_
lIPS

_..

------.1

R6522/R6522A
PIN DESCRIPTIONS

RES

DBD-DB7 (Data Bus)

(Resetl

The eight bi-directional data bus lines are used to
transfer data between the R6522 and the system
processor. During read cycles, the contents of the sel·
ected R6522 register are placed on the data bus lines
and transferred into the processor. During write
cycles, these lines are high-impedance inputs and data
is transferred from the processor into the selected register. When the R6522 is unselected, the data bus
lines are high-impedance.

The reset input clears all internal registers to logic 0
(except T1 and T2 latches and counters and the Shift
Register). This places all peripheral interface lines in
the input state, disables the timers, shift register, etc.
and disables interrupting from the chip.
¢2 (Input Clock)
The input clock is the system ¢2 clock and is used to
trigger all data transfers between the system processor
and the R6522.

CS1,

The direction of the data transfers between' the
R6522 and the system processor is controlled by the
R/W line. If R/W is low, data will be transferred out
of the processor into the selected R6522 register
(write operation). If R/W is high and the chip is select·
. ed, data will be transferred out of the R6522 (read
operation ).

RS Coding

CS2

(Chip Selects)

The two chip select inputs are normally connected to
processor address lines either directly or through decoding. The selected R6522 register will be accessed
lNhen CS1 is high and CS2 is low.

RNi (ReadlWrite)

RSD- RS3 (Register Selects)
The four Register Select inputs permit the system processor to select one of the 16 internal registers of the
R6522, as shown in Figure 6.

Register
Number

RS3

RS2

RSl

RSO

Register
Desig.

0

0

0

0

0

ORB/IRB

Output Register "B"

Input Register "B"
Input Register "A"

Description
Write

Read

1

0

0

0

1

ORA/IRA

Output Register" A"

2

0

0

1

0

DDRB

Data Direction Register "B"

3

0

0

1

1

DDRA

Data Direction Register "A"

4

0

1

0

0

T1C·L

T1 Low-Order Latches

0

1

T1C-H

Tl High-Order Counter
T1 Low-Order Latches

5

0

1

6

0

1

1

0

T1L-L

7

0

1

1

1

T1L·H

T1 High-Order Latches

8

1

0

0

0

T2C-L

T2 Low-Order Latches

9

1

0

0

1

T2C-H

T2 High-Order Counter
Shift Register

T1 Low-Order Counter

T2 Low-Order Counter

10

1

0

1

0

SR

11

1

0

1

1

ACR

Auxiliary Control Register

12

1

1

0

0

PCR

Peripheral Control Register

13

1

1

0

1

IFR

Interrupt Flag Register

14

1

1

1

0

IER

I nterrupt Enable Register

15

1

1

1

1

ORA/IRA

Same as Reg 1 Except No "Handshake"

Figure 6. R6522 Internal Register Summary

9

R6522/R6522A
iRQ (Interrupt Request)

PA port. In addition, the polarity of the PB7 output
signal can be controlled by one of the interval timers
while the second timer can be programmed to count
pulses on the PB6 pin. Peripheral B lines represent one
standard TTL load in the input mode and will drive
one standard TTL load in the output mode. In addition, they are capable of sourcing 1.0mA at 1.5VDC
in the output mode to allow the outputs to directly
drive Darlington transistor circuits. Figure 8 is the
circuit schematic.

The Interrupt Request output goes low whenever an
internal interrupt flag is set and the corresponding interrupt enable bit is a logic 1. This output is "c ,lendrain" to allow the interrupt request signal to be
"wire-or'ed" with other equivalent signals in the
system.
PAO-PA7 (Peripheral A Port)
The Peripheral A port consists of 8 lines which can
be individually programmed to act as inputs or outputs under control of a Data Direction Register. The
polarity of output pins is c~ntrolled by an Output
Register and input data may be latched into an internal register under control of the CA 1 line. All of
these modes of operation are controlled by the system processor through the internal control registers.
These lines represent one standard TTL load in the
input mode and will drive one standard TTL load in
the output mode. Figure 7 illustrates the output
circuit.

CB1, CB2 (Peripheral B Control Lines)
The Peripheral B control lines act as interrupt inputs
or as handshake outputs. As with CA 1 and CA2, each
line controls an interrupt flag with a corresponding interrupt enable bit. In addition, these lines act as a
serial port under control of the Shift Register. These
lines represent one standard TTL load in the input
mode and will drive one standard TTL load in the
output mode. Unlike PBO·PB7, CBl and CB2 cannot
drive Darlington transistor circuits.

CA 1, CA2 (Peripheral A Control Lines)
The two Peripheral A control lines act as interrupt inputs or as handshClke outputs. Each line controls an
internal interrupt flag with a corresponding interrupt
enable bit. In addition, CA 1 controls the latching of
data on Peripheral A port input lines. CAl is a highimpedance input only while CA2 represents one standard TTL load in the input mode. CA2 will drive one
standard TTL load in the output mode.

INPUT
OUTPUT _ _ _ _ _ _po__-\
CONTROL

INPUT DATA

Figure 8. Peripheral B Port Output Circuit
PAO-PA7,
CA2

I

IIOCONTROl~

FUNCTIONAL OESCR IPTION

OUTPUTDATA~

Port A and Port B Operation

I

Each 8-bit peripheral port has a Data Direction Register (DDRA, DDRB) for specifying whether the peripheral pins are to act as inputs or outputs. A 0 in a
bit of the Data Direction Register causes the corresponding peripheral pin to act as an input. A 1 causes
the pin to act as an output.

INPUT DATA ...... -_ _ _ _ _ _--J

Figure 7. Peripheral A Port Output Circuit

PBO-PB7 (Peripheral B Port)

Each peripheral pin is also controlled by a bit in the
Output Register (ORA, ORB) and an Input Register
(IRA, IRB). When the pin is programmed as an output, the voltage on the pin is controlled by the cor-

The Peripheral B port consists of eight bi-directional
lines which are controlled by an output register and a
data direction register in much the same manner as the

10

R6522/R6522A
responding bit of the Output Register. A 1 in the Out·
put Register causes the output to go high, and a "0"
causes the output to go low. Data may be written into
Output Register bits corresponding to pins which are
programmed as inputs. In this case, h"wever, the out·
put signal is unaffected.

REG 1 - ORA/IRA

I 71s151413121'-' oj

~ PA2PA3

PAO

L--- PA '
OUTPUT REGISTER "A"IORAI

L----

Reading a peripheral port causes the contents of the
Input Register (I RA, I R B) to be transferred onto the
Data Bus. With input latching disabled, I RA will always
reflect the levels on the PA pins. With input latching
enabled, I RA will reflect the levels on the PA pins at
the time the latching occurred (via CA 1).

DR

'------PA4

INPUT REGISTER "A" IIRAI

1....------PA5

'-------- PAS
1....-_ _ _ _ _ _ _ PA7

Pon
Data Duectlon

WRITE

READ

Selection

The IRB register operates similar to the IRA register.
However, for pins programmed as outputs there is a
difference. When reading I RA, the level on the pin
determines whether a 0 or a 1 is sensed. When reading
I RB, however, the bit stored in the output register,
ORB, is the bit sensed. Thus, for outputs which have
large loading effects and which pull an output "1"
down or which pull an output "0" up, reading IRA
may result in reading a "0" when a "1" was actually
programmed, and reading a "1" when a "0" was pro·
grammed. Reading I RB, on the other hand, will read
the "1" or "0" level actually programmed, no matter
what the loading on the pin.

DORA:: ,.," (OUTPUT!
(Input I.tchlngdlubledl

MPU writes Output Level
(ORAl

DORA" "'" (OUTPUT)
(Input I.tchlng en.bledl

MPU ruds level on PA pin
MPU ,ud, IRA bit which IS
the lee"eel ot thePAplA.t the
hmeotthe lanCA1 i1ellye

DORA" "0" (INPUT!
I!nput latching d'ubled)

MPU writes Into ORA, but MPU ,eads Ipycel on PA pm
no pttpcl on Pin lcewel. until

17:':'N-=:'PU:-::T~'-1

I-:O::-=O-::'RA:-O--:':-:::'O'::-:'

DORA changed

MPU ,uds IRA bit which I'

flnpullalchlngl'nablpdl

thee ll'wl'1 of thl'PApIA.t thl'
tlml'ofthl'lutCA1,ctlYl'
H'"'I'Ion

Figure 10. Output Register A (ORA),
Input Register A (IRA)
REG 2 (DDRBI AND REG 3 (DDRAI

1716~/sI413EI2~1;IOLpBOPAO

Figures 9,10, and 11 illustrate the formats of the port
registers. In addition, the input latching modes are
selected by the Auxiliary Control Register (Figure
16.l

L-

PB1 !PAl

pe2/PA2

II

Handshake Control of Data Transfers

PB3/PA)
PB4/PA4

DATA DIRECTION REGISTER
"B" OR "A" 10DRB/DORAI

PB5/PA5

The R6522 allows positive control of data transfers
between the system processor and peripheral devices

PB6/PA6
" - - - - - -_ _ _ _ PB7/PA7

0"

REG 0 - ORB/IRB
'1

1716151413121' 1 1

ASSOCIATED PB/PA PIN IS AN INPUT
IHIGH IMPEOANCEI
ASSOCIATED pe/PA PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BY
ORBORA REGISTER BIT

0

~

PBO

Figure 11. Data Direction Registers (DDRB, DORA)

L - PB '

through the operation of "handshake" lines. Port A
lines (CAl, CA2) handshake data on both a read and
a write operation while the Port B lines (CB1, CB2)
handshake on a write operation only.

PB2

1-----PB3
PB5
PB6
PB7

L-----PB4

OUTPUT REGISTER "B" 10RBI
OR
INPUT REGISTER "B"IORBI

L -_ _ _ _ _

L -_ _ _ _ _ _

Read Handshake

L -_ _ _ _ _ _ _

Positive control of data transfers from peripheral devices into the system processor can be accomplished
very effectively using Read Handshaking. In this case,
the peripheral device must generate the equivalent of
a "Data Ready" signal to the processor signifying that
valid data is present on the peripheral port. This signal
normally interrupts the processor, which then reads
the data, causing generation of a "Data Taken" signal.
The peripheral device responds by making new data
available. This process continues until the data transfer is complete.

PO"

READ

DalaD.rectlon
Selection

WRITE

DORB '" "1" (OUTPUT!

MPU writes Output level
IORBI

In ORB Pin level has no affect

DORB:: "0" (INPUT)

MPU writes IOta ORB, but

MPU reads Input level on PB

IInput latching dISabled)

no effect on pin level, until pin

I--.,...,---,.,-_----l

MPU reads output u!g.,ter bit

OORB changed

DORB'" "0" !INPUT!

MPU ruds lAB bit, which

Iinput latching enabled)

the level of the PB PI" at Ihe
time of the last CBl act,ve
tranSition

IS

Figure 9, Output Register B (ORB),
Input Register B (lRB)

11

R6522/R6522A

•

12~~~

)?AA,~AREADY

'I!

IIZc7/@Z2?21IIL..!---

IRQ O U T P U T .

!

•

REA:~:::::::T.'ON ----------rl----;:I
- - -I- - i . .~-HANDSHAKE MODE
leA2)

~~t;: ~~~~N"

---------------------11

I

L--..-.-J

ICA21

Figure 12. Read Handshake Timing (Port A, Only)

"2~~~
WRITE ORA. ORa
OPERATION
"OATA READY"

HANDSHAK E MODE
ICA2. ca21
"DATA READY"
PULSE MODE
ICA2. ca21

~

t

I

I
I
I

"DATA TAKEN
ICA'. CBlI

iRa OUTPUT

I

I

~

I
r-

I

Figure 13. Write Handshake Timing

In the R6522, automatic "Read" Handshaking is
possible on the Peripheral A port only. The CAl in·
terrupt input pin accepts the "Data Ready" signal
and CA2 generates the "Data Taken" signal. The
"Data Ready" signal will set an internal flag which
may interrupt the processor or which may be polled
under program control. The "Data Taken" signal can
either be a pulse or a level which is set low by the sys·
tem processor and is cleared by the "Data Ready"
signal. These options are shown in Figure 12 which
illustrates the normal Read Handshaking sequence.

Timer Operation
Interval Timer Tl consists of two 8·bit latches and a
16·bit counter. The latches are used to store data
which is to be loaded into the counter. After loading,
the counter decrements at 02 clock rate. Upon reach·
ing zero, an interrupt flag will be set, and TAO will go
low if the interrupt is enabled. The timer will then
disable any further interrupts, or will automatically
transfer the contents of the latches into the counter
and will continue to decrement. In addition, the timer
may be programmed to invert the output signal on a
peripheral pin each time it "times·out". Each of
these modes is discussed separately below.

Write Handshake
The sequence of operations which allows handshaking
data from the system processor to a peripheral device
is very similar to that described for Read Handshaking.
However, for Write Handshaking, the R6522 gener·
ates the "Data Ready" signal and the peripheral device must respond with the "Data Taken" signal. This
can be accomplished on both the PA port and the
PB port on the R6522. CA2 or CB2 act as a "Data
Ready" output in either the handshake mode or pulse
mode and CA 1 or CBl accept the "Data Taken" sig·
nal from the peripheral device, setting the interrupt
flag and cleaning the "Data Ready" output. This
sequence is shown in Figure 13.

The Tl counter is depicted in Figure 15 and the
latches in Figure 16.
REG 12 - PERIPHERAL CONTROL REGISTER

a

0

0

INPUT NEGATIVE ACTIVE EDGE

o a
o

a

1 INDEPENDENT INTERRUPT
INPUT NEG EDGE
1 0 INPUT POSITIVE ACTIVE EDGE
1 1 INDEPENDENT INTERRUPT
INPUT pas EDGE

1 0 0 HANDSHAKE OUTPUT
1 0 1 PULSE OUTPUT

1 1 1 HIGH OUTPUT

C81 INTERRUPT CONTROL

Selection of operating modes for CAl, CA2, CB 1,
and CB2 is accomplished by the Peripheral Control
Register (Figure 14).

o~

NEGATIVE ACTIVE EDGEl
1 : POSITIVE ACTIVE EDGE ,

U

NEGATIVE ACTIVE EDGE

1 ' POSITIVE ACTIVE EDGE

CA2 CONTROL

J 2 lOPE RATION
0 0 INPUT NEGATIVE ACTIVE EDGE
0 1 INDEPENDENT INTERRUPT
INPUT NEG EDGE
o 1 0 INPUT POSITIVE ACTIVE EDGE
o 1 1 INDEPENDENT INTERRUPT
INPUT POS EDGE
1 0 0 HANOSHAKE OUTPUT
1 0 1 PULSE OUTPUT
, 1 0 lOW OUTPUT
1 1 1 HIGH OUTPUT

o

a

Figure 14. CA 1, CA2, CB1, CB2 Control

12

CA11NHRRUPT CONTROL

o~

R6522/R6522A
Two bits are provided in the Auxiliary Control Register (bits

6

ating modes_ The four possible modes are depicted

and 7) to allow selection of the T1 oper-

in Figure 17_

REG 4 - TIMER 1 LOW-ORDER COUNTER

REG 5 - TIMER 1 HIGH-ORDER COUNTER

""1'1"1111~:-

~:

17

61514131211101

~::
I

1024

2U48

_CO""

16

VALUE

COUNT
VALUE

4096

32

8192

64

16384

12~

3276~

WRITE - 8 BITS LOAOED INTO T1LOW ORDER
LATCHES. LATCH CONTENTS ARE
TRANSFERRED INTO LOW·ORDfR
COUNTER AT THE TIME THE HIGH
ORDER COUNTER IS LOADED IREG 51.

WRITE - 8 BITS LOADED INTO 11 HIGH·ORDER
LATCHES. ALSO. AT THIS TIME BOTH
HIGH AND LOW·ORDER LATCHES
TRANSFERRED INTO 11 COUNTER.
T11NTERRUPT FLAG ALSO IS RESET.

READ -

READ -

8 BITS FROM TlLOWORDER COUNTER
TRANS"ERRED TO MPU. IN ADDITION.
TlINTERRUPT FLAG IS RESET IBIT 6
IN INTERRUPT FLAG REGISTER)

8 BITS FROM Tl HIGH·ORDER COUNTER
TRANSFERRED TO MPU.

Figure 15_ T1 Counter Registers
REG 6 - TIMER 1 LOW-ORDER LATCHES

REG 7 - TIMER 1 HIGH'{)RDER LATCHES

1+1+1+1,ll

m!,

17161514131211101

m~

COUNT
VALUE

32

64

COUNT
VALUE

16384

12~

32768

-

WRITE - 8 BITS LOADED INTO Tl LOW ORDER
LATCHES THIS OPERATION IS NO
DIFFERENT THAT A WRITE INTO
REG4

WRITE - 8 BITS LOADED INTO T1 HIGHORDfR
LATCHES. UNLIKE REG 4 OPERATION
NO LATCH·TO COUNTER TRANSFERS
TAKE PLACE

READ -

READ -

8 BITS FROM T1 LOW ORDER LATCHES
TRANSFERRED TO MPU. UNLIKE REG 4
OPERATION, TillS DOES NOT CAUSE
RESET OF T1 INTERRUPT FLAG

8 BITS FROM Tl HIGH ORDER LATCHES
TRANSFERRED TO MPU.

Figure 16. T1 Latch Registers
REG 11 - AUXILIARY CONTROL REGISTER

L "' "' ' ' '

1 716151413121' 1 0

~

Tl TIMER CONTROL
7 6 OPERATION
o 0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
o 1 CONTINUOUS
INTERRUPTS
1 0 TIMED INTERRUPT
EACH TIME T1 IS

PB

PB7

DISABLED

ONE SHOT
OUTPUT
43 '2
0 o
0 1
1 o
1 1
1 0 0
101
1 1 0
111

SOUARE

o
o
o
o

WAVE

OUTPUT
T2 TIMER CONTROL
51 OPERATION
101 TIMEO INTERRUPT
1

~~~~~ ~~w,,~:'TH

:1
l ' ENABLE LATCHING

SHIFT REGISTER CONTROL

lOADED

11 CONTINUOUS
INTERRUPTS

10~OISABlE

I
I

i

OPERATION

DISABLED
SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF 02
SHIFT IN UNDER CONTROL OF EXT. ClK
SHIFT OUT FREE RUNNING AT T2 RATE
SHIFT our UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF 02
SHIFT OUT UNDER CONTRDL OF EXT. CLK

Figure 17. Auxiliary Control Register
Note: The processor does not write directly into the low order counter (T1C-U. Instead, this half of the counter is loaded automatically from the low order latch when the processor writes into the high order counter. In fact, it may not be necessary to
write to the low order counter in some applications since the timing operation is triggered by writing to the high order counter.

13

R6522/R6522A

WRITE T1C·H
OPERATION

fRO

W

----.J

~I----I//~-----+--.

)1'

------j

,jl

OUTPUT

(;Bl~ g~~~~T

I

C'"''':':''~ __ ".I

NJ

I

----+l1

Figure 18_ Timer 1 and Timer 2 One-Shot Mode Timing
Timer lOne-Shot Mode
The interval timer (me-shot mode allows generation
of a single interrupt for each timer load operation. As
with any interval timer, the delay between the "write
Tl C-H" operation and generation of the processor
interrupt is a direct function of the data loaded into
the timing counter. In addition to generating a single
interrupt, Timer 1 can be programmed to produce a
single negative pulse on the PB7 peripheral pin. With
the output enabled (ACR7=1) a "write T1C-H" operation will cause PB7 to go low. PB7 will return high
vvhen Timer 1 times out. The result is a single programmable width pulse.

series of evenly spaced interrupts and the ability to
produce a square wave on PB7 whose frequency is
not affected by variations in the processor interrupt
response time_ This is accomplished in the "freerunning" mode_
In the free-running mode, the interrupt flag is set and
the signal on PB7 is inverted each time the counter
reaches zero_ However, instead of continuing to decrement from zero after a time-out, the timer automatically transfers the contents of the latch into the
counter (16 bits) and continues to decrement from
there_ The inter~upt flag can be cleared by writing
T1C-H, by reading T1C-L, or by writing directly into
the flag as described later. However, it is not necessary to rewrite the timer to enable setting the interrupt flag on the next time-out.

In the one-sho~ mode, writing into the high order
latch has no effect on the operation of Timer 1. However, it will be necessary to assure that the low order
latch contains the proper data before in itiating the
count-down with a "write Tl C-H" operation. When
the processor writes into the high order counter, the
Tl interrupt flag will be cleared, the contents of
the low order latch will be transferred into the low
order counter, and the timer will begin to decrement
at system clock rate. If the PB7 output is enabled,
this signal will go low on the phase two following the
write operation. When the counter reaches zero, the
Tl interrupt flag will be set, the I RQ pin will go low
(interrupt enabled), and the signal on PB7 will go
high. At this time the counter will continue to decrement at system clock rate. This allows the system
processor to read the contents of the counter to determine the time since interrupt. However, the Tl
interrupt flag cannot be set again unless it has been
cleared as described in th is specification.

All interval timers in the R6522 are "re-triggerable".
Rewriting the counter will always re-initialize the
time-out period. In fact, the time-out can be prevented completely if the processor continues to rewrite
the timer before it reaches zero. Timer 1 will operate
in this' manner if the processor writes into the high
order counter (T 1C-H). However, by loading the
latches only, the processor can access the timer during each down-counting operation without affecting
the time-out in process. Instead, the data loaded into
the latches will determine the length of the next timeout period. This capability is particularly valuable in
the free-running mode with the output enabled. In
this mode, the signal on PB7 is inverted and the interrupt flag is set with each time-out. By responding
to the interrupts with new data for the latches, the
processor can determine the period of the Flext half
cycle during each half cycle of the output signal on
PB7. In this manner, very complex waveforms can be
generated. Timing for the free-running mode is shown
in Figure 19.

Timing for the R6522 interval timer one-shot modes
is shown in Figure 18.
Timer 1 Free-Run Mode
The most important advantage associated with the
latches in Tl is the ability to produce a continuous

14

R65221R6522A

w"""::~~1~I
~.

OPERATION

I

iR6 OUTPUT

pe7 OUTPUT

/1

I

if

----,

1'---__

,",'

'------,I,'

I-N+l.5CYCLES--_I+I_----N+2CYCLES-------<.~1
Note: A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both
DDRB bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer output. If one is 1 and the other is 0, then PB7 functions
as a normal output pin, controlled by ORB bit 7.

Figure 19. Timer 1 Free-Run Mode Timing

Timer 2 Operation

Timer 2 One-Shot Mode

Timer 2 operates as an interval timer (in the "one·
slot" mode only~, or as a counter for counting negative pulses on the PB6 peripheral pin. A single con·
trol bit is provided in the Auxiliary Control Register
to select between these two modes. This timer is com·
prised of a "write-only" low-order latch (T2L-LI. a
"read-only" low-order counter and a read/write high
order counter. The counter registers act as a 16-bit
counter which decrements at ct>2 rate. Figure 20 illus·
trates the T2 Counter Registers.

As an interval timer, T2 operates in the "one·shot"
mode similar to Timer 1. In this mode, T2 provides a
single interrupt for each "write T2C-H" operation.
After timing out, the counter will continue to decrement. However, setting of the interrupt flag will be
disabled after initial time-out so that it will not be set
by the counter continuing to decrement through zero.
The processor must rewrite T2C-H to enable setting
of the interrupt flag. The interrupt flag is cleared by'
reading T2C·L or by writing T2C·H. Timing for this
operation is shown in Figure 18.

REG 8 - TIMER 2 LOW-ORDER COUNTER

REG 9 - TIMER 2 HIGH·ORDER COUNTER

256
512
1024
COUNT
VALUE

2048

'------16
' - -_ _ _ _ _ 32

COUNT
VALUE

4096
8192

'---_ _ _ _ _ _ 64
16384
1...--------128

WRITE -

8 BITS LOADED INTO T2 LOW·DRDER
LATCHES

READ -

8 BITS FROM T2LDW ORDER COUNTER
TRANSFERRED TO MPU. T2 INTERRUPT
flAG IS RESET.

32768

WRITE -

8 BITS LOADED INTO T2 HIGH·ORDER
COUNTER. ALSO. LOW-ORDER LATCHES
TRANSFERRED TO LOW-ORDER
COUNTER. IN ADOITIDN. T2 INTERRUPT
FLAG IS RESET.

READ -

8 BITS FROM T2 HIGH-ORDER COUNTER
TRANSFERRED TO MPU

Figure 20. T2 Counter Registers

15

•

R6522/R6522A
Timer 2 Pulse Counting Mode

I nterrupt Operation

In the pulse counting mode, T2 serves primarily to
count a predetermined number of negative-going
pulses on PB6_ This is accomplished by first loading
a number into T2. Writing into T2C-H clears the interrupt flag and allows the counter to decrement each
time a pulse is applied to PB6. The interrupt flag will
be set when T2 reaches zero. At this time the counter
will continue to decrement with each pulse on PB6.
However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on subsequent down-counting
operations. Timing for this mode is shown in Figure
21. The pulse must be low on the leading edge of (1)2.

Controlling interrupts within the R6522 involves
three prinCipal operations. These are flagging t~e interrupts, enabling interrupts and signaling to the processor that an active interrupt exists within the chip.
Interrupt flags are set by interrupting conditions
which exist within the chip or on inputs to the chip.
These flags normallv remain set until the interrupt
has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags
in order from highest to lowest priority. This is ac·
complished by reading the flag register into the processor accumulator, shifting this register either right
or left and then using conditional branch instructions
to detect an active interrupt.

Shift Register Operation

Associated with each interrupt flag is an interrupt
enable bit. This can be set or cleared by the processor to enable interrupting the processor from the corresponding interrupt flag. If an interrupt flag is set to
a logic 1 by an interrupting condition, and the corresponding interrupt enable bit is set to a 1, the Interrupt Request Output (I RO) will go low. I RO is an
"open-collector" output which can be "wire-or'ed"
with oth.er devices in the system to interrupt the
processor.

The Shift Register (SR) performs serial data transfers
into and out of the CB2 pin under control of an in·
ternal modulo·8 counter." Shift pulses can be applied
to the CBl pin from an external source or, with the
proper mode selection, shift pulses generated internally will appear on the CBl pin for controlling external devices.
The control bits whiCh select the various shift register
operating modes are located in the Auxiliary Control
Register. Figure 22 illustrates the configuration of the
SR data bits and the SR control bits of the ACR.

In the R6522, all the interrupt flags are contained
in one register. In addition, bit 7 of this register will
be read as a logic 1 when an interrupt ex ists within
the chip. This allows very convenient polling of several devices within a syst~m to locate the source of
an interrupt.

Figures 23 and 24 illustrate the operation of the various shift register modes.

~:~~~~12~: ---fI~

___________________________

PB61NPUT

IRO

OUTPuT

//

N2

Figure 21. Timer 2 Pulse Counting Mode
REG 10 - SHIFT REGISTER

REG 11 - AUXILIARY CONTROL REGISTER

17161514131211101

JD

L

SHIFT
REGISTER
BITS

SHIFT REGISTER
MODE CONTROL

3

1
1

0
1
1
0
0

1

OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF '1'2
SHIFT IN UNDER CONTROL OF EXT CLK
SHIFT OUT FREE· RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF T2

1
1

1
1

0
1

SHIFT OUT UNDER CONTROL OF '1'1
SHIFT OUT UNDER CONTROL OF EXT CLK

o
o
o
o

NOTES
1 WHEN SHIFTING OUT. BIT 7!S THE FIRST BIT
OUT AND SIMUL TANEOUSL Y IS ROTA TED BACK
INTO BIT 0
2. WHEN SHIFTING IN. BITS INITIALLY ENTER
BIT 0 AND ARE SHiFTED TOWARDS BIT 7

2
0

Figure 22. SR and ACR Control Bits

16

R6522/R6522A
SR Disabled (000)
The 000 mode is used to disable the Shift Register. In this mode the microprocessor can write or read the SR, but the
shifting operation is disabled and operation of CBl and CB2 is controlled by the appropriate bits in the Peripheral
Control Register (PCR). In this mode the SR Interrupt Flag is disabled (held to a logic 0).
Shift in Under Control of T2 (001)
In the 001 mode the shifting rate is controlled by the low order 8 bits of T2. Shift pulses are generated on the CBl pin
to control shifting in external devices. The time between transitions of this output clock is a function of the system
clock period and the contents of the low order T2 latch (N).
The shifting operation is triggered by writing or reading the shift register. Data is shifted first rnto the low order bit
of SR and is then shifted into the next higher order bit of the shift register on the negative·going edge of each clock
pulse. The input data should change before the positive'going edge of the CBl clock pulse. This data is shifted into
the shift register during the 92 clock cycle following the positive·going edge of the CBl clock pulse. After 8 CB 1
clock pulses, the shift register interrupt flag will be set and I RQ will go low.

Shift in Under Control of 92 (01O)
In mode 010 the shift rate is a direct function of the system clock frequency. CBl becomes an output which
generates shift pulses for controlling external devices. Timer 2 operates as an independent interval timer and has no
effect on SR. The shifting operation is triggered by reading or writing the Shift Register. Data is shifted first into
bit 0 and is then shifted into the next higher order bit of the shift register on the trailing edge of each 92 clock pulse.
After 8 clock pulses, the shift register interrupt flag will be set, and the output clock pulses on CBl will stop.

I

I

~~:~A~ON~~__~~__________________________~-+

______________________

CB10UTPUT

iRa

Shift in Under Control of External CB 1 Clock (011)
In mode 011 CB 1 becomes an input. This allows an external device to load the shift register at its own pace. The
shift register counter will interrupt the processor each time 8 bits have been shifted in. However, the shift register
counter does not stop the shifting operation; it acts simply as a pulse counter. Reading or writing the Shift
Register resets t:le Interrupt flag and initializes the SR counter to count another 8 pulses.
Note that the data is shifted during the first system clock cycle following the positive·going edge of the CB 1 shift
pulse. For this reason, data must be held stable during the first full cycle following CBl going high.

CB2 INPUT
OATA

~~~~K::!::J~~OC~:)~~OC::2:J~~~::!::~7
{J.

Figure 23. Shift Register Input Modes

17

•

I

R6522/R6522A
Shift Out Free-Running at T2 Rate (100)
Mode 100 is very similar to mode 101 in which the shifting rate is set by T2. However, in mode 100 the SR Counter
does not stop the shifting, operation. Since the Shift Register bit 7 (SR7) is recirculated back into bit 0, the 8 bits
loaded into the shift register will be clocked onto CB2 repetitively. In this mode the shift register counter is disabled.

Shift Out Under Control of T2 (101)
In mode 101 the shift rate is controlled by T2 (as in the previous mode). However, with each read or write of the shift
register the SR Counter is reset and 8 bits are shifted onto CB2. At the same time, 8 shift pulses are generated on CB1
to control shifting in external devices. After the 8 shift pulses, the s:lifting is disabled, the SR Interrupt Flag is set and
CB2 remains at the last data level.

,n n n n n

'1'2

CLOCK

/""

~

_

~

_

_

~~~~~~N~-:~~~i:::::~~:::::t~~~t-------r------t--------~------~!------N'2 CYCLES

cal OUTPUT
SHIFT CLOCK

~
'f--v __i~1
x~__~~__JX~__~__~/~~

-----

LShift Out Under Control of rt>2 (110)
In mode 110, the shift rate is controlled by the ¢2 system clock.
'1'2
CLOCK

~~~~~~N ~-----+--~--4---+---~~--~--~--~---+--~--~---------CBlOUTPUT
SHIFT CLOCK

CB2 OUTPUT
OAT A

Shift Out Under Control of External CB1 Clock (111)
In mode 111 shifting is controlled by pulses applied to the CB1 pin by an external device. The SR counter sets the SR
Interrupt flag each time it counts 8 pulses but it does not disable the shifting function. Each time the microprocessor
wlites or reads the shift register, the SR Interrupt flag is reset and the SR counter is initialized to b!!gin counting the
next 8 shift pulses on pin CB1. After 8 shift pulses, the interrupt flag is set. The microprocessor can then load the
shift register with the next byte of data.

Figure 24. Shift Register Output Modes

18

R65221R6522A
The Interrupt Flag Register (IFR) and Interrupt Enable Register (I ER) are depicted in Figures 25 and
26, respectively.

by writing to address 1110 (lER address). If bit 7 of
the data placed on the system data bus during this
write operation is a O. each 1 in bits 6 through 0
clears the corresponding bit in the Interrupt Enable
Register_ For each zero in bits 6 through O. the corresponding bit is unaffected.

The IF R may be read directly by the processor. In addition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IFR. When the
proper chip select and register signals are applied to
the chip, the contents of this register are placed on
the data bus. Bit 7 indicates the status of the I RO output. This bit corresponds to the logic function: I RO =
IFR6 x IER6 + IFR5 x IER5 + IFR4 x I ER4 + IFR3 x'
IER3 + IFR2 x IER2 + IFRl x IERl + IFRO x IERO.
Note: X = logic AND, + = Logic OR.

Setting selected bi.ts in the Interrupt Enable Register
is accomplished by writing to the same address with
bit 7 in the data word set to a logic 1. In this case.
each 1 in bits 6,through 0 will set the corresponding
bit. For each zero. the corresponding 'bit will be unaffected_ This individual control of the setting and
clearing operations allows very convenient control of
the interrupts during system operation.

The IF R bit 7 is not a flag. Therefore, th is bit is not
directly cleared by writing a logic 1 into it. It can
only be cleared by clearing all the flags in the register
or by disabling all the active interrupts as discussed
in the next section.

In addition to setting and clearing IER bits. the processor can read the contents of this register by placing
the proper address on the register select and chip
select inputs with the R/W line high. Bit 7 will be
read as a logic O.

REG 13 - INTERRUPT FLAG REGISTER
REG 14 - INTERRUPT ENABLE REGISTER

1716151·131Z111 1
0

l

.1

l

CAZ

CAZ

A~~~V:YEDGE

READOR WRITE
REG 1 (ORA)'

lCA1 _ CAl ACTIVE EDGE

SHIFT REG COMPLETE 8 SHIFTS

CBZ CBl
TIMER Z

'+"'t"'tL,~

CLEARED BY

CBZ ACTIVE EDGE
CBl ACTIVE EDG
TlME·OUT OF TZ

READ OR WRITE
SHIFT REG
READ OR WRITE ORB'
R~AD
R WRITE ORB
READ TZ LOW OR
WRITE TZ HIGH

II1I

-

:,~'""

CB2
CBl

f-- o·

INTERRUPT DISABLED

l ' INTERRUPT ENABLED

TIMER 2
L..--------TIMER 1
SET/CLEA~

• I F THE CAZ/CBZ CONTROL IN THE PCR IS SELECTED AS
"INDEPENDENT" INTERRUPT INPUT. THEN READING OR
WRITING THE OUTPUT REGISTER ORA/ORB WILL NOT
CLEAR THE FLAG BIT. INSTEAD. THE BIT MUST BE
CLEARED BY WRITING INTO THE IFR. AS'DESCRIBED
PREVIOUSLY

NOTES:
1. IF BIT 7 IS A "0". THEN EACH "1" IN BITS 0 - 6 DISABLES THE
CORRESPONDING INTERRUPT.
2. I F BIT 7 IS A "1". THEN EACH "1" IN BITS 0 - 6 ENABLES THE
CORRESPONDING INTERRUPT.
3. IF A READ OF THIS REGISTER IS DONE. BIT 7 WILL BE "0" AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.

Figure 25. Interrupt Flag Register (J FR)

Figure 26. Interrupt Enable Register (JER)
For each interrupt flag in IF R, there is a corresponding bit in the Interrupt Enable Register. The
system processor can be set or clear selected bits in
this register to facilitate controlling individual interrupts without affecting others. This is accomplished

19

•

R6522/R6522A

•

PACKAGE OUTLINE

PIN CONFIGURATION

10 ma.

0
40

D21-L---[~
600 miU
I1S24 mml

•

"

II

20

TOp~~~~T~

RSO

PAl

155ma!!

1020ma.,

. - t393mml

PAS

RES

190 mall
11482m m l

PA6

DO

I

DI

m ffil-t -?= 1~:07:~':'1
t

.

11651 0 6 5 :

flo'l 040

- - :~: We

---l

I

PBO

f

!

1111 I

TVP
TYP

1910 (4851 mml

L

i

RS2
RSl

1

t5130mml

-. 11-

CA2

RSI

I

!

I

CAl

PAO

11587) 625
1151115-95

---.

DOT OR NOTCH

I

VSS

Dl

PB2

D4

I

PBl

DS

(]54mml

PB4

D6

010 mm

PBS

D7

125 mml

PB6

1·2

PB7

CSI

CBI

CS2

100 m,n

'---~

1-.-

D2

PBI

Ii fS90 148 00 mml Ii
19 EOUAl SPACES
100 Ii TOl NONCUM
(254 mml

NOTE Pin No 1.s In lower left
symboillation

corn~'

when

"In normal Orientation

CB2

R/W

VCC

iRa

Ordering Information

Order
Number

Package
Type

R6522P
R6522AP
R6522C
R6522AC
R6522PE
R6522APE
R6522CE
R6522ACE

Plastic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic

Frequency

1 MHz
2 MHz
1 MHz
2 MHz
1 MHz

2 MHz
1 MHz

2 MHz

Temperature
Range
OOC
OOC
OOC
OOC
0
-40 C
0
-40 C
0
-40 C
o
-40 C

to +70 0 C
to +70 o C
0

to +70 C
to +70 0 C
0
to +85 C
0
to +85 C
0
to +85 C
0
to +85 C

PART NUMBER

R6545-1

R6S00 Microcomputer System
DATA SHEET
CRT CONTROLLER (CRTC)
DESCRIPTION

FEATURES

The R6545-1 CRT Controller (CRTC) is designed to interface
an B-bit microprocessor to CRT raster scan video displays,
and adds an advanced CRT controller to the established and
expanding line of R6500 products.

• Compatible with 8-bit microprocessors

The R6545-1 provides refresh memory addresses and character generator row addresses which allow up to 16K characters with 32 scan lines per character to be addressed. A
major advantage of the R6545-1 is that the refresh memory
may be addressed in either straight binary or by row/column.
Other functions in the R6545-1 include an intemal cursor register which generates a cursor output when its contents are
equal to the current refresh address. Programmable cursor
start and end registers allow a cursor of up to the full character scan in height to be placed on any scan lines of the
character. Variable cursor display blink rates are provided.
A light pen strobe input allows capture of the current refresh
address In an Intemallight pen register. The refresh address
tines are configured to provide direct dynamic memory refresh.
All timing for the video refresh memory signals is derived
from the character clock input. Shift register, latch, and multiplex control signals (when needed) are provided byextemal
high-speed timing. The mode control register allows noninterlaced video display modes at SO or 60 Hz refresh rate.
The intemal status register may be used to monitor the
R6545-1 operation. The RES input allows the CRTC-generated field rate to be dynamically-synchronized with line frequency jitter.

ORDERING INFORMATION
Part
Number
R6545-1P
R6545-1AP
R6545-1C
R6545-1AC

Package
Type
Plastic
Plastic
Ceramic
Ceramic

• RockweIInIemaIIonaI Corporation 1980
AURIgtD~

PrInI8d iii U.SA

Frequency
1 MHz
2 MHz
1 MHz
2 MHz

Temperature
Range

acc to +7(rC
O"C to + 7O"C
O"C to +70"C
O°C to +70°C

• Up to 2.5 MHz character clock operation
• Refresh RAM may be configured in row/column or straight
binary addressing
• Alphanumeric and limited graphics capability
• Up and down scrolling by page, line, or character
• Programmable Vertical Sync Width
• Fully programmable display (rows, columns, character
matrix)
• Non-interlaced scan
• SO/50. Hz operation
• Fully programmable cursor
• Light pen register
• Addresses refresh RAM to 16K characters
• No extemal DMA required
• Intemal status register
• 4o-Pin ceramic or plastic DIP
• Pin-compatible with MC6845
• Single +5 ±5% Volt Power Supply

VSS

An
LPEN
CCO/MAO
CC1/MA1
CC2/MA2
CC3/MA3
COlIMA..
CC5IMA5
CC8/MA8
CC7/MA7
CROIMA8
CR1IMA9
CR2IMA10
CR3/MA11
CR4IMA12
CR5/MA13
DISPLAY ENA8LE
CURSOR
VCC

R6545-1 Pin Configuration

VSYNC
HSYNC
RAO
RA1
RA2
RA3
RA...
DO
01
02
03
0 ..
05
DlI
07

cs

RS
.2
R/il
CCLK

I

•

INTERFACE SIGNAL DESCRIPTION
CPU INTERFACE
_2 (Phase 2 Clock)
The input clock is the system Phase 2 (~2) clock and is used
to trigger all data transfers between the system processor (CPU)
and the R6545-1. Since there is no maximum limit to the allowable ~2 clock time. it is not necessary for it to be a continuous
clock. This capability permits the R6545-1 to be easily interfaced
to non-65OO compatible microprocessors.
R/W (Read/Write)
The R/W input signal generated by the processor is useti to
control the direction of data transfers. A high on the R/W pin
allows the processor to read the data supplied by the R6545-1.
a low on the R/W pin allows data on data lines 00-07 to be
written into the R6545-1.

CS (Chip Select)
The Chip Select input is normally connected to the processor
address bus either directly or through a decoder. The R654S-1
is selected when tS is low.
RS (Register Select)
The Register Select input is used to access internal registers.
A low on this pin permits writes (R/W = low) into the Address
Register and reads (R/W = high) from the Status Register. The
contents of the Address Register is the identity of the register
accessed when RS is high.

CURSOR (Cursor Coincidence)
The CURSOR signal is an active-high output used to indicate
when the scan coincides with the programmed cursor position.
The cursor position may be programmed to be any character
in the address field. Furthermore. within the character. the cursor may be programmed to be any block of scan lines. since
the start scan line and the end scan line are both programmable.
The cursor position may be delayed by one character time by
setting Bit 5 of RS to A "1".
LPEN (LIght Pen Strobe)
The LPEN signal is an edge-sensitive input used to load the
internal Ught Pen Register with the contents of the Refresh
Scan Counter at the tirne the active edge occurs. The active
edge of LPEN is the low-to-high transition.
CCLK (Clock)
The CCLK signal is the character timing clock input and is used
as the time base for all internal count/control functions.
~

The ~ signal is an active-low input used to initialize all internal scan ,counter circuits. When ~ is low. all internal
counters are stopped and cleared. all scan and video outputs
are low. and control registers are unaffected.
must stay
low for at least one CCLK period. All scan timing is initiated
when ~ goes high. In this way.
can be used to synchronize display frame timing with line frequency. RES may also
be used to synchronize multiple CRTC's in horizontal and/or
vertical split screen operation.

m

m

DO-D7 (Data Bus)

REFRESH RAM AND CHARACTER ROM INTERFACE

00-07 are the eight data lines used to transfer data between
the processor and the R654S-1. These lines are bidirectional
and are normally high-impedance except during read cycles
when the chip is selected (~ = low).

MAG-MA13 (Refresh RAM Address LInes)

VIDEO INTERFACE
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to determine
the horizontal position of displayed text. It may drive a CRT
monitor directly or may be used for composite video generation.
HSYNC time position and width are fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal is an active high output used to determine
the vertical position of displayed text. Like HSYNC. VSYNC may
be used to drive a CRT monitor or composite video generation
circuits. VSYNC time position and width are both programmable.
DISPLAY ENABLE (Display Enable)
The DISPLAY ENABLE signal is an active-high output used to
indicate when the R654S-1 is generating active display information. The number of horizontal display characters per row
and the number of vertical display rows are both fully programmable and together are used to generate the DISPLAY ENABLE
signal. DISPLAY ENABLE can be delayed one character time
by setting bit 4 of RS equal to 1.

These 14 signals are active-high outputs used to address the
Refresh RAM for character storage and display operations. The
starting scan address is fully programmable and the ending
scan address is determined by the total number of characters
displayed. which is also programmable. in terms of characters/
line and lines/frame.
There are two selectable address modes for MAO-MA13:
In the straight binary mode (RS. Mode Control. bit 2 = "0").
characters are stored in successive memory locations. Thus.
the software must be designed such that row and column character coordinates are translated into sequentially-numbered addresses. In the row/column mode (RS. Mode Control. bit 2 =
"1"). MAO-MA7 become column addresses CeO-CC7 and MASMA13 become row addresses CRO-CRS. In this case. the software can manipulate characters in terms of row and column locations, but additional address compression circuits are needed
to convert the CCO-CC7 and CRO-CRS addresses into a memory-efficient binary address scheme.
RAG-RA4 (Raster Address LInes)
These S signals are active-high outputs used to select each raster scan within an individual character row. The number of raster
scan lines is programmable and determines the character height.
including spaces between character rows.

INTERNAL REGISTER ORGANIZATION
Read
(R/W=
Highl

Address Register
RS

CS

X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

4

X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1

3

2

1 0

X X X X
X X X X
X X X X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0

0
0
0
0
1
1
1
1
0
0
0
0

0
0

1

0
1
0

1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1

Reg.
No.

X
X
X
RO
Rl
R2
R3
R4
R5
RS
R7
RS
R9
Rl0
Rll
R12
R13
R14
R15
R16
R17

Register Units

Register Name

Address Register
Status Register
Horizontal Total Char
Horizontal Displayed Char
Horizontal Sync Position
YSYNC, HSYNC Widths
Vertical Total Rows
Vertical Total Adjust Lines
Vertical Displayed Rows
Vertical Sync Position
Mode Control
Scan Line
Cursor Start Line
Cursor End Line
Display Start Address (HI
Display Start Address (L1
Cursor Position Address (HI
Cursor Position Address (LI
Light Pen Register (HI
Light Pen Register (L1

Write
(R/WLowl

-

V
V
V
V
V

V
V
V

-

V
V

-

V

V

-

V
V

V

-

3

5/ /
5 4 3
5 4 3
5 4 3
5 4 3
V' 6 5 4 3
./' / / 4 3
L6 5 4 3
l.C6 5 4 3
7 6 5 4 3
L //4 3
'/6 5 4 3
y //4 3
./' / 5 4 3
7 6 5 4 3
Y L 5 4 3
7 6 5 4 3
V V 5 4 3
7 6 5 4 3

V

-

5 4

,/6
7 6
7 6
7 6
7 6

V
V
V

No. of Scan Lines
Scan Line No.
Scan Line No.

6

2

1

0

~ //4 3 2 1 0

V

No. of Characters/Row
No. of Characters/Row
Character Position
No. of Scan Lines, Characters
No. of Character Rows
No. of Scan Lines
No. of Character Rows
No. of Character Rows

7

,/ /,1 / / l!~

V

Register No.

Register Bit

V

Vk"
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Table 1. Overall Register Structure and Addressing

GND

00-07

STATUS REGISTER (SR)

~

poooI....- - _......"--............. HSYNC

This a-bit register contains the status of the CRTC. Only two
bits are assigned. as follows:

VSYNC
DISPLAY ENABLE
CURSOR
LPEN
CCLK
RES

02

Rm
a

RS

L - - - - - N O T USED

MAO-MA13
RAO-RA4
REFRESH RAM AND CHARACTER ROM

Vonical Ro·T,aco CVRTI
o • Sc.n is not currently in its yerticll r.-trace time,
1 - Scan is currently in its vertical re·trace timl.

R 6545-' Interface Diagram

Not. that this bit actually goes to ••• ,.. when vertical
,e-trKe starts, but goes to I "0" five characte, clock
times hahn. vertical r.-trace ends. so that critical
timings for refresh RAM operations .r. avoided.
LPEN Register Full (LRF)
o '"' Register R16 or R17 has been "ad by the CPU.

INTERNAL REGISTER DESCRIPTION
ADDRESS REGISTER
This 5-bit write-only register is used as a "pointer" to direct
CRTC/CPU data transfers within the CRTC. Its contents is the
number of the desired register (0-17). When CS and RS are low.
then this register may be loaded; when CS is low and RS is
high. then the register selected is the one whose identity is
stored in this address register.

1 '"'
L....-_ _ _ _

NOTE:

LPEN strobe has been received.

NOI Used

The Status Register takes the State.

1-I 0 11 1-1-1-1 -I - I

immediately after power IVeel turn-on.

RO-HORIZONTAL TOTAL CHARACTERS

R7-VERTICAL SYNC POSITION

This 8-bit write-only register contains the total of displayed and
non-displayed characters, minus one, per horizontal line. The
frequency of HSYNC is thus determined by this register.

This 7-bit write-only register is used to select the character row
time at which the vertical SYNC pulse is desired to occur and,
thus, is used to position the displayed text in the vertical direction.

R1-HORIZONTAL DISPLAYED CHARACTERS

RB-MODE CONTROL (MC)

This 8-bit write-only register contains the number of displayed
characters per horizontal line.

This 8-bit write-only register selects the operating modes of the
RS545-1 , as follows:

R2-HORIZONTAL SYNC POSITION
This 8-bit write-only register contains the position of the horizontal SYNC on the horizontal line, in terms of the character
location number on the line. The position of the HSYNC determines the left to right location of the displayed text on the video
screen. In this way, the side margins are adjusted.

Must Prooramto"O

R3-HORIZONTAL AND VERTICAL SYNC WIDTHS
This 8-bit write-only register contains the widths of both HSYNC
and VSYNC, as follows:

A.frnh RAM Add.aH,ng Mod. IRAQI

~

DI~IIV

::: ~::~~~~~:~v

ENbie Skew IDESI

0- fOf raG _t.v.
, - to dIt~v 0 .... "" (ftllbl.

0 ....

ch.r.ct.r tlln•.

The width of the horizontal sync

pulse (HSYNCI in the number of
character clock times (CCLKI.
L...-_ _ _ _ _ _ _

VSYNC Pul.. Width
The width of the vertical sync
pulse (VSYNCI in the number of
SCJIn lines. When bits 4·7 are
all "0", VSYNC will be 16 scan

R9-ROW SCAN LINES
This 5-bit write-only register contains the number of scan lines,
minus one, per character row, including spacing.

lines wide.

Control of these parameters allows the RS545-1 to be interfaced
to a variety of CRT monitors, since the HSYNC and VSYNC
timing signals may be accommodated without the use of external one shot timing.
R4-VERTICAL TOTAL ROWS
The Vertical Total Register is a 7-bit register containing the total
number of character rows in a frame, minus one. This register,
along with R5, determines the overall frame rate, which should
be close to the line frequency to ensure flicker-free appearance.
If the frame time is adjusted to be longer than the period of the
line frequency, then RES may be used to provide absolute
synchronism.
R5-VERTICAL TOTAL LINE ADJUST
The Vertical Total Line Adjust Register (R5) is a 5-bit write-only
register containing the number of additional scan lines needed
to complete an entire frame scan and is intended as a fine adjustment for the video frame time.
RS-VERTICAL DISPLAYED ROWS
This 7-bit write-only register contains the number of displayed
character rows in each frame.

R10-CURSOR START LINE
R11-CURSOR END LINE
These 5-bit write-only registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and S of R10 are
used to select the cursor blink mode, as follows:
Bit

Bit

~

~

Cursor Blink Mode

o
o

o

Display Cursor Continuously
Blank Cursor Continuously
Blink Cursor at 1/16 Field Rate
Blink Cursor at 1/32 Field Rate

1

o

R12-DISPLAY START ADDRESS HIGH
R13-DISPLAY START ADDRESS LOW
These registers form a 14-bit register whose contents is the
memory address of the first character of the displayed scan (the
character on the top left of the video display, as in Figure 1).
Subsequent memory addresses are generated by the RS545-1
as a result of CCLK input pulses. ScrOlling of the display is accomplished by changing R12 and R13 to the memory address
associated with the first character of the desired line of text to
be displayed first. Entire pages of text may be scrolled or
changed as well via R12 and R13.

NUMBER OF HORIZONTAL TOTAL
CHARACTERS (ROI
r -____________________
______________________
--JA~

~

NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (RlI

rr----------------JA~---------DISPLAY START ADDRESS HIGH (R121°
/DISPLAY START ADDRESS LOW (R131°

____~
NU MBER OF
} SC
AN LINES (R91
CURSOR START LINE (Rl01

I

\:
1\
NUMBER OF
VERTICAL
DISPLAY
ROWS
NUMBER OF
VERTICAL
TOTAL
ROWS
(R41

CURSOR END LINE (Rll1

I

\~URSOR

POSITION ADDRESS HIGH (R141
CURSOR POSITION ADDRESS LOW (R151
HORIZONTAL
RETRACE
PERIOD
(NON.DISPLAYI

(R6)

DISPLAY PERIOD

VERTICAL RETRACE PERIOD
(NON·DISPLA Y)

VERTICAL

!~i~T

-

(R5) {

Figure 1. Video Display Format
R14-CURSOR POSITIOlll HIGH
Rl5-CURSOR POSITION LOW

DESCRIPTION OF OPERATION

These registers form a 14-M register whose contents is the
memory address of the current cursor position. When the video
display scan counter (MA lines) matches the contents of this
register, and when the scan line counter (RA lines) falls within
the bounds set by Rl 0 and Rll, then the CURSOR output becomes active. Bit 5 of the Mode Control Register (RB) may be
used to delay the CURSOR output by a full CCLK time to accommodate slow access memories.

VIDEO DISPLAY

Rl6-LlGHT PEN HIGH
R17-LlGHT PEN LOW
These registers form a 14-bit register whose contents is the light
pen strobe position, in terms of the video display address at
which the strobe occurred. When the LPEN input changes from
low to high, then, on the next negative-going edge of CCLK, the
contents of the internal scan counter is stored in registers R16
and R17.
REGISTER FORMATS
Register pairs R12/R13, R14/R15, and R16/R17 are formatted
in one of two ways:
(1) Straight binary, if register RB, bit 2 = "0".
(2) Row/Column, if register RB, bit 2 = "1". In this case the
low byte is the Character Column and the high byte is the
Character Row.

Figure 1 indicates the relationship of the various program registers in the R6545-1 and the resultant video display.
Non-displayed areas of the Video Display are used for horizontal and vertical retrace functions of the CRT monitor. The horizontal and vertical sync signals, HSYNC and VSYNC, are programmed to occur during these intervals and are used to trigger
the retrace in the CRT monitor. The pulse widths are constrained by the monitor requirements. The time position of the
pulses may be adjusted to vary the display margins (left, right,
top, and bottom).

REFRESH RAM ADDRESSING
Shared Memory Mode (R8. bit 3 = "0")
In this mode, the Refresh RAM address lines (MAO-MA 13) directly reflect the contents of the internal refresh scan character
counter. Multiplex control, to permit addressing and selection of
the RAM by both the CPU and the CRTC, must be provided
exlernal to the CRTC. In the Row/Column address mode, lines
MAO-MA7 become character column addresses (CCO-CC7) and
MAB-MA13 become character row addresses (CRO-CR5).

•

Bits 5 and 6 in the Cursor Start Line High Register (R1 0) control
the cursor display and blink rate as follows:

ADDRESSING MODES
Row/Column
In this mode, the CRTC address lines (MAO-MA13) are generated as 8 column (MAO-MA7) and 6 row (MA8-MA13) addresses. Extra hardware is needed to compress this addressing
into a straight binary sequence in order to conserve memory in
the refresh RAM.

Bit6

Bit 5

Cursor Operating Mode

0
0
1
1

0
1
0
1

Display Cursor Continuously
Blank Cursor Continuously
Blink Cursor at 1/16 Field Rate
Blink Cursor at 1/32 Field Rate

Binary
In this mode, the CRTC address lines are straight binary and
no compression circuits are needed. However, software complexity is increased since the CRT characters cannot be stored
in terms of their row and column locations, but must be
sequential.
USE OF DYNAMIC RAM FOR REFRESH MEMORY
The R6545-1 permits the use of dynamic RAMS as storage devices for the Refresh RAM by continuing to increment memory
addresses in the non-display intervals of the scan. This is a viable technique, since the Display Enable signal controls the
actual video display blanking. Figure 2 illustrates Refresh RAM
addressing for the case of binary addressing for 80 columns and
24 rows with 10 non-displayed columns and 10 non-displayed
rows.

The cursor of up to 32 characters in height can be displayed on
and between the scan lines as loaded into the Cursor Start Line
(R10) and Cursor End Line (R11) Registers.
The cursor is positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor Position Address Low
(R15) registers with the desired refresh RAM address. The cursor can be positioned in any of the 16K character positions.
Hardware paging and data scrolling is thus allowed without loss
of cursor position. Figure 3 is an example of the display cursor
scan line.
UNDERLINE
CURSOR

OVERLINE
CURSOR

o -4-+4-1-I-I--+-

TOTAL' 90
DISPLAY' 80

>

....

~

~0

'6801'68' '682
,
'~57
'758 ,1759 1760
i
'1769
f---+-+'-l- .---1-----1--- - --+---+--+-.----<-~
i

17601176'

'7621

'840 "84'

'8421

i '92'

'9221

'920

~_._L.-- ,I~,~~

10 -++-l-+t-t-t11 -+-+--"f-+-+-f-+-

26401264' 2642[

: '929

i

i

'997 '998 '999 2000

+---+-·i~717 127,8

CURSOR START
LINE = 1

CURSOR START
LINE = 1

CURSOR END
LINE = 1

CURSOR END
LINE = 9

8~~"H~

9 ...."~"~

I

2009

CURSOR END

L1NE=9

I 2089

2079 2080
2720

L1NE=9

7~~"H'"

1'849

'840

, ' 9 ' 7 I '9'8 '9'9 '920
I

~o.l:o~ 2~L_--I..--~.~12078

CURSOR START

O-+-+-I-I-+-+.-+-

1 ....IM~H...
2 -4-~-I-Hl>..J.3-+-e4-1-Hl>..J.4 -I-e4-1-Hl.-+~t6 -4-e4-1-Hl>..J.7 -+-e4-1-Hl>..J.8 -+-e4-1-Hl>..J.9 -++-l-+-+-+-+10 -++-l-+-+-+-+11 -+-+-I-I-+--+-+-

5-+<....

~

I_
BOX

CURSOR

..

-t---f-;ng

Figure 2. Memory Addressing Example (80 x 24)

CURSOR OPERATION
A one character wide cursor can be controlled by storing values
into the Cursor Start Line (R10) and Cursor End Line (R11) registers and into the Cursor Position Address High (R14) and Cursor Position Low (R15) registers.

Figure 3.

Cursor Display Scan Line Control Examples

MPU WRITE TIMING CHARACTERISTICS
(V cc

= 5.0V

±.5%. T A

=0

to 70°C. unless otherwise noted)
2MHz

1 MHz
Characteristic

Symbol

Min

Max

Min

Max

Unit

Cycle Time

TCYC

1.0

-

JlS

TC

440

-

0.5

02 Pulse Width

200

-

ns

Address Set-Up Time

T

180

-

90

-

ns

ACW

Address Hold Time

TCAH

0

-

0

-

nS

R/W Set-Up Time

TWCW

180

-

90

-

ns

RiW Hold Time

TCWH

ns

Data Bus Set-Up Time

T

Data Bus Hold Time

DCW
T HW

0

-

0

-

265

-

100

-

ns

10

-

10

-

ns

Itr and t f - 10 to 30 nsl

WRITE CYCLE

~----------TCYC-------------'~

2.0V

2.0V

2_0V

0.8V ....._ _ _ _ _ _-l

I----_.... T ACW

CS.

..

i---_+-T CAH
~~~~~~~~~

2.0V

RS

O.BV

RiW
O.BV

rTOCW

T HW _

~D7 "~;';:';'::;":______" ';: ;':';~B;';:~

•

I

MPU READ TIMING CHARACTERISTICS
(V cc = 5.0V 1.5%. T A = 0 to 70°C. unless otherwise noted)

I

1 MHz
Characteristic

Symbol

2 MHz

Min

Max

Min

Max

Unit

Cycle Time

TCYC

1.0

-

0.5

-

~s

02 Pulse Width

TC

440

-

200

-

ns

-

ns

~.

ns

Address Set-Up Time

T

180

-

90

Address Hold Time

TCAR

0

-

0

R IW Set-Up Time

TWCR

180

-

90

-

ns

Read Access Time

TCDR

-

340

-

150

ns

Read Hold Time

THR

10

-

10

-

ns

Data Bus Active Time
(Invalid Data)

TCDA

40

-

40

-

ns

It, and

ACR

tf = 10 to 30 ns)

READ CYCLE

~------------TCYC------------~

2.0V

t---_+- T CAR
2.0V

CS,

RS
O.SV

R/W

2.0V
DO-D7·_ _ _ _ _ _ _ _ _

~

O.SV

rr.~~~~~~~

MEMORY AND VIDEO INTERFACE CHARACTERISTICS
IV

cc

= 5 OV t 5%, T A "'

a 10

70

0

e. unless otherwise noted)

Symbol
Char Clock Cycle Time

40
TeCH

Char Cluck Pulsr Width

MAO·MA 13 Propagation Delay

T MAO

RAO RA4 PropagatiOn Delay

T RAO

DISPlA Y ENABLE Prop Delay

TOlD

HYSNC Propagation Delay

450

450

VSYNC Propagation

450

Cursor Propagation Delay

150

LPEN Strobe Width
lPEN 10 CelK

D~tav

CeLK 10 LPEN Delay

',.t,"20nsf mall;)

SYSTEM TIMING DEFINITIONS
I-------Tccv---------"'i

\'--1

CClK

*

SIGNAL

SIGNAL
SYMBOL IXI
TMAD
TRAQ

DISPLAY ENABLE

TOTO

HSYNC

T

HSD

lVSO
CURSOR

LIGHT PEN STROBE TIMING DEFINITIONS

lPEN

MAO·MA13

SLASH AREA OEF INES THE "WINDOW" IN WHICH AN

LPEN POSITIVE EDGE WILL CAUSE ADDRESS N+2 TO
LOAD INTO LIGHT PEN REGISTER. TRANSITIONS ON
EITHER SIDE OF THIS "WINDOW" WILL RE$UL T IN
UNPREDICTABLE VALUES BEING LOADED INTO THE

LIGHT PEN REGISTER

T COD

SPECIFICATIONS
Maximum Ratings
Rating

Symbol

Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature

Value

Unit

VCC

-0.3 to +7.0

Vdc

V

-0.3 to +7.0

Vdc

TOp

o to +70

T

-55 to 150

°c
°c

IN

STG

All inputs contain protection circuitry to prevent damage due to high static discharges. Care should be taken to prevent unnecessary application of voltages in excess of the allowable limits.

Electrical Characteristics
0

(V CC = 5.0V ±5%, T A = 0- 70 C, unless otherwise noted)
Characteristic

Symbol

Input High Voltage

V

Input Low Voltage

V

Input Leakage (02, R/Vi, ~,~, RS, LPEN, CCLK)

Min

Max

Unit

2.0

VCC

Vdc

0.3

0.8

Vdc

liN

-

2.5

#lAdc

I

-

10.0

#lAdc

IH
IL

Three-State Input Leakage (DO-D7)
(V IN = 0.4 to 2.4V)

TSI

Output High Voltage
I

LOAD

= 205 #lAdc (DO-D7)

V

2.4

OH

-

Vdc

I LOAD = 100 #lAdc (all others)
Output Low Voltage
I LOAD = 1.6 mAdc
Power Dissipation

VOL

-

0.4

Vdc

P

-

1000

mW

-

10.0

pF

-

12.5

pF

-

10.0

pF

D

Input Capacitance
02, RiW, RES,

CS, RS,

LPEN, CCLK

CIN

DO-D7
Output Capacitance

COUT

TEST LOAD

2.4KO
R6545-1 PIN

130pF

I

R

R=llKO FOR 00-07
=24KO FOR ALL OTHER OUTPUTS

PART NUMBER

R6551

R6500 Microcomputer System
PRODUCT DESCRIPTION
R6551 Asynchronous Communications Interface Adapter
(ACIA)

:J:J

en
en
en

...
l>
~

SECTION 1
INTRODUCTION
The Rockwell R6551 Asynchronous Communications
Interface Adapter (ACIA) provides an ~asi Iy implemented, program controlled interface between 8-bit
microprocessor-based systems and serial communication
data sets and modems.
The R655 I has an internal baud rate generator. This
ft:!ature eliminates the need for multiple component
support circuits, a crystal being the only other part
required. The Transmitter baud rate can be selected
under program control to be either I of 15 di Herent
rates from 50 to 19,200 oaud, or at 1/16 times an
externa I clock rate. The Receiver baud rate may be
selected under program control to be either the Transmitter rate, or at 1/16 times the external clock rate.
The R655 I has programmable word lengths of 5, 6, 7,
or 8 bits; even, odd, or no parity; I, 1-1/2, or 2
stop bits.
The R655 I is designed for maximum programmed
control from the CPU, to si.mplify hardware implementation. Three separate registers permit the CPU to
easi Iy select the R6551's operating modes and data
checking parameters and determine operational status.

::s

n
::s-

Registers, and Overrun, Framing and Parity Error
conditions.
The Transmitter and Receiver Data Registers are used
for temporary data storage by tbe R655 I Transmit and
Receiver circuits.

3

• Compatible with 8-bit microprocessors
•

Full duplex operation with buffered receiver and
transmitter

o·

,::S

en

5'

•

Internal baud rate generator with 15 programmable
baud rates (50 to 19,200)

(I)

•

Program-selectable internally or externally controlled receiver rate

•

Programmable word lengths, number of stop bits,
and parity bit generation and aetection
Programmable interrupt control

•

Program reset

The Control Register controls the number of stop bits,
word length, receiver clock source and baud rate.



Co

m

-0

"CD...

SECTION 2
R6551 INTERFACE REQUIREMENTS

•

This section describes the interface requirements for the
R6551 ACIA. Figure 2-1 is the Interface Diagram and
Figure 2-2 shows the pin-out configuration for the R655 1.

vss
csa

AIW
~2

CSl

iRCi

ATI

D7
D6
D5
D.
D3
D2

AxC
XTLI

CTS
CTS

TxD

OTA

DO

DSA

AxD
ASO

DCD

hO
IRa

Figure 2-2.

R6551 PIN CONFIGURATION

oeD
RIW

csa

DSR

ESi

RxC

RSO

XTLI

RSI

XTLO

R/W (Read/Write) (28)
The R/W input, generated by the microprocessor, is used to
control the direction of data transfers. A high on the R/W
pin allows the processor to read the data supplied by the
R6551, a low allows a write to the R6551.

/.12
OHI

RES

RTS

IRQ (Interrupt Request) (26)

VCC
RxO
VSS

Figure 2-1.

R6551 INTERFACE DIAGRAM

2.1 MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION

The IRQ pin is an interrupt output from the interrupt control
logic. It is on open drain output, permitting several
devices to be connected to the common IRQ microprocessor
input. Normally a high level, IRQ goes low when on
interrupt occurs.

00-07 (Data Bus) (18-25)
The 00-07 pins ore the eight data lines used to transfer
data between the processor and the R6551. These lines are
bi-directional and are normally high-impedance except
duri ng Read cycl es when the R6551 is selected.

RES (Reset) (4)
During system initialization a low on the RES input will
couse a hardware reset to occur. The Command Register
and the Control Register will be cleared. The Status
Register will be cleared with the exception of the indications of Data Set Ready and Data Carrier Detect, which
are externally controlled by the DSR and DCD lines, and
the transmitter Empty bit, which will be set. RES must be
held low for one ~2 clock cycle for a reset to occur.

CSO. CS1 (Chip Selects)(2.3)
The two chip select inputs are normally connected to the
processor address lines either directly or through decoders.
The R6551 is selected when CSO is high and CST is low.

RSO. CS 1 (Register Selects)(13.14)
112 (Input Clock) (27)
The input clock is the system ~2 clock and is used to clock
all data transfers between the system microprocessor and
the R6551.

The two register select lines are normally connected to the
processor address lines to allow the processor to select the
various R6551 internal registers. The following table shows
the int~rnal register select coding.

RS1

RSO

Write

Read

a

a

Transmit Data
Register

Receiver Data
Register

0

1

Programmed
Reset (Data is
"Don't Care")

Status Register

1

a

Command Register

1

1

Control Register

rate is either the programmed baud rate or under the
control of an externally generated receiver clock. The
selection is made by programming the Control Register.

RxC (Receive Clock) (5)
The RxC is a bi-directional pin which serves as either the
receiver 16x clock input or the receiver 16x clock output.
The latter mode results if the internal baud rate generator
is selected for receiver data clocking.

RTS (Request to Send) (8)

Only the Command and Control registers are read/write.
The Programmed Reset operation does not couse any data
transfer, but is used to clear bits 4 through 0 in the
Command register and bit 2 in the Status register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Programmed Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figures 3-2, 3-3, and 3-4.

The RTS output pin is used to control the modem from the
processor. The state of the RTS pin is determined by the
contents of the Command Register ..

CTS (Clear to Send) (9)

2.2 ACIA/MODEM INTERFACE
SIGNAL DESCRIPTION
XTLI. XTlO

The CTS input pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter
is automatically disabled if CIS is high.

(Crystal Pins) (6. 7)
DTR (Data Terminal Ready) (11)

These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see Section 4.5). Alternatively, an externally generated
clock may be used to drive the XTU pin, in which case
the XTlO pin must float. XTU is the input pin for the
transmit clock.

This output pin is used to indicate the status of the R6551
to the modem. A Iowan DIR indicates the R6551 is
enabled, a high indicates it is disabled. The processor
controls this pin via bit 0 of the Command Register.

TxD (Transmit Data) (10)
DSR (Data Set Ready) (17)
The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The lSB (least
significant bit) of the Transmit Data Register is the first
data bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of
an external clock. This selection is made by programming
the Control Register.

The DSR input pin is used to indicate to the R6551 the
status of the modem. A low indicates the "ready" state
and a high, "not-ready".

DCD (Data Carrier Detect) (16)

RxD (Receive Data) (12)

The DCD input pin is used to indicate to the R6551 the
status of the carrier-detect output of the modem. A low
indicates that the modem carrier signal is present and a
high, that it is not.

The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, lSB first. The receiver data

3

SECTION 3
INTERNAL ORGANIZATION
This section provides a functional description of the R6551.
A block diagram of the R6551 is presented in Figure 3-1.

data bus and the direction of the transfer to or from
the register.
The registers are selected by the Register Select and Chip
Select and Read/Write lines as described in Table 2-3
previously.

3.4 TIMING AND CONTROL
6Co

IRQ

The Timing and Control logic controls the timing of data
trans fers on the i nterna I da to bus and the reg is ters, the
Data Bus Buffer, and the microprocessor data bus, and the
hardware reset features.

5SR

R.,w

cs;
OTR

Rrs

Timing is controlled by the system fJ2 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the fJ2 high period when selected.

~2

RES:

Figure 3-1.

All registers will be initialized by the Timing and Control
Logic when the Reset (RES) line goes low. See the individual register description for the state of the registers
following a hardware reset.

INTERNAL ORGANIZATION

3.1 DATA BUS BUFFERS

3.5 TRANSMITTER AND RECEIVER
DATA REGISTERS

The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bi-directional.
When the R/W line is high and the chip is selected, the
Data Bus Buffer passes the data from the system data lines
to the R6551 internal data bus. When the R!W line is low
and the chip is selected, the Data Bus Buffer writes the
data from the internal data bus to the system data bus.

These registers are used as temporary data storage for the
R6551 Transmi t and Receive Circuits. Both the Transm i tter
and Receiver are selected by a Register Select 0 (RSO) and
Register Select 1 (RSl) low condition. The Read/Write
line determines which actually uses the internal data bus;
the Transmitter Data Register is write only and the Receiver
Data Register is read only.

3.2 INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor to go low when conditions are met that require
the attention of the microprocessor. The conditions which
can cause an interrupt will set bit 7 and the appropriate bit
of bits 3 through 6 in the Status Register if enabled. Bits 5
and 6 correspond to the Data Carrier Detect (DCD) logic
and the Data Set Ready (DSR) logic. Bits 3 and 4 correspond to the Receiver Data Register full and the Transmitter
Data Register empty conditions. These conditions can cause
an interrupt request if enabled by the Command Register.

Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are
"don't care".
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order
bits are "0". Parity bits are not contained in the Receiver
Data Register. They are stripped off after being used for
parity checking.

3.3 1/0 CONTROL

3.6 STATUS REGISTER

The I/O Control Logic controls the selection of internal
registers in preparation for a data transfer on the internal

Figure 3-2 indicates the format of the R6551 Status Register.
A description of each status bit follows.

4

I~:':'~:;: ',,-,
1

3.6.4

0

Framing Error (Bit 1). Overrun (2).
and Parity Error (Bit 0)

None of these bits causes a processor interrupt to occur,
but they are normally checked at the time the Receiver
Data Register is read so that the validity of the data can
be verified.

, . P""V En", O.toe"d
Framing Error·

a .. No Framing Error

1" Framing Error DetectKt

3.6.5

0'" No Overrun
1 .. Overrun Has Dccuned

Interrupt (Bit 7)

Receiver Data Reglstllr Full

This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1" whenever any
kind of interrupt occurs.

Transmlttt"f Data R~I!>"1:er Empty
0" Not Empty

1" Empty

Dan Came, Detect lOCO)

o ..

I

1

DCD low (Detectl
htgh INot Detectedl

3.7 CONTROL REGISTER

-oeD

Data Set Ready
0"

1 •

DSR
DSR

(OSAI

low (Readvl
hIgh (Not Readyl

The Control Register selects the desired baud rate,
frequency source, word length, and the number of stop bits.

Interrupt IIRQ)

7

6

5

4

3

2

1

0

~.~H"d",,"R''''
. _ .:... __ 0 _ . Program Reset

Figure 3-2.

3.6.1

0- No Interrupt

, ... Interrupt Has Occurred

-No Interrupt occurs tor theu conditions

3.7.1

Selected Baud Rate (Bits 0. 1. 2. 3)

These bits, set by the processor, select the Transmitter baud
rate, which can be at 1/16 an external clock rate or one
of 15 other rates controlled by the internal baud rate
generator as shown in Figure 3-3.

STATUS REGISTER FORMAT

Receiver Data Register Full (Bit 3)

This bits goes. to a "1" when the R6551 transfers data from
the Receiver Shift Register to the Receiver Data Register,
and goes to a "0" when the processor reads the Receiver
Data Register.

3.6.2

T

Transmitter Data Register Empty
(Bit 4)

I

This bits goes to a "1" when the R6551 transfers data from
the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.

3.6.3

L

Data Carrier Detect (Bit 5) and Data
Set Ready (Bit 6)

These bits reflect the levels of the DCD and DSR inputs to
the R6551. A "0" indicates a low level (true condition)
and a "1" indicates a high (false). Whenever either of
these inputs change state, an immediate processor interrupt
occurs, unless the R6551 is disabled (bit 0 of the Command
Register is a "0"). When the interrupt occurs, the status
bits wi II indicate the levels of the inputs immediately
after the change of state occurred. Subsequent level
changes wi II not affect the status bits unti I the Status
Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status
bits wi II reflect the new iOlput levels.

rf r~ ; ': : ~ '
~:!~ ~l

::~:

, 0 0 0
1 0 0 1
1 0 1 0

Baud
Bolud
Baud

1200
1800

2400

1 0 1 1

3600

1 1 0 0

4800
7200
9600

1 1 0 1
1 1 1 0
1 1 1 1

19200

Baud
Baud
Baud
baud

RECEIVER CLOCK SOURCE (RCS)

0'" External Receiver Clock

L -_ _ _ _ _ _ _ _ _ _ WORD lENCiTH IWl!

65

00
01

1 0

8 Sits
7Biu
6 BIB

' - -_ _ _ _ _ _ _ _ _ _ _ _ _ STOP BIT NUMBER ISBN!

0" 1 StOpSI'

I: I~ I: I~ I~ I: I~ I~ I
_

_

_

_

_

_

_

_

1" 2 Stop Bru
~

H"d .." , R ... , I RES!

Program Reset

Figure 3-3.

5

IE

1112 Stop Bits
For WL. 5 and No Panty
1 Stop Sit
ForWL-S_nd Parltv

R6551 CONTROL REGISTER

3.7.2

Receiver Clock Source (Bit 4)

This bit controls the clock source to the Receiver. A "a"
couses the Receiver to operate at a baud rate of 1/16 an
external clock. A "I" causes the Receiver to operate at
the same baud rate as is selected for the transmitter as
shown in Figure 3-3.

3.7.3

L-...J

~

Word Length (Bits 5. 6)

These bits determine the word length to be used (5, 6, 7
or 8 bits). Figure 3-3 shows the configuration for each
number of bits desired.

3.7.4

OATATERMINAL

REACV 10TRI

O· Data T_mtNl Not ANdy IOTA H'IIhl
1·011. T"""MI A"dy IOn lo.1
INTERRUPT REQUEST DISABLED ClRDI
O-IRQ I ... bled
l-IROD_bled

TRANSMITTER INTERRUPT CONTAOllTICI

~~

Aft· H"h, Trant"'"
RTS • low, T'antmlf

''''''',upt Oeubted •

'"'IIf,U'" 'Nbled

, 0

All. low, Yra"""" Int."upl D,ubled

1 1

IfTS-Low. T,,,,,,,,,t Int."upID.ub1ed
T••" ...."8, .... 0"T.0

~------ R(CEIVER (CHOMaD! (REMI

No,,,..,

D. Aece._
Mode
, - "ace,", EchoModa.
L -_ _ _ _ _ _ _ _ 'A'lIIlV MODE ENABUD '''MEl

O·'....'yMudeD •• b ...

Stop Bit Number (Bit 7)

No ....... .,

alt G~.... ,ed

' .. "yChItdID . . ....

'-'IIf,IyModeE"."'ed

This bit determines the number of stop bits used. A "a"
always indicates one stop bit. A "I" indicates 1-1/2 stap
bits if the word Iength is 5 with no parity selected,
1 stop bit if the word length is 8 with parity selected, and
2 stop bits in all other configurations.

' - - - - - - - - - - - - ,AAIlV MODE CONTAOll'MCI

II

mmH_d. . .R
..
7 6 5 .. 1

2 1 0

-

0

e 0
e ,

1 0

'RU'

-

-

0

0

0

0

"'"yCheckO~*,

1 1

"" ••• ,,,R. ..

-aITS:I AND:3 MUST IE ZERO FOR RECEIVER ECHO MODE,

Figure 3-4.

3.8 COMMAND REGISTER

Odd '_If" T'.M",."ed/R~ •.-d
E..... 'a','V T,a ...nnn_/RMe.MeI
Merll '.,.ty BIf T'.~I"".rM
$peoce'.lTtyal1 T,an."."tlKl
,.,,,yC"-dr; O ...blH

Ali WILL

IE LOW.

R6551 COMMAND REGISTER

The Command Register controls specific modes and functions.

3.8.6
3.8.1

These bits determine the type of parity generated by the
Transmitter, (even, odd, mark or space) and the type of
parity check done by the Receiver (even, odd, or no
check). Figure 3-4 shows the possible bit configurations
for the Parity Mode Control bits.

This bit enables all selected interr~ and controls the
state of the Data Terminal Ready (OTR) line. A "a"
indicates the microcomputer system is not ready by setting
the OTR line high. A "I" indicates the microcomputer
system is ready by setting the OTR line low.

3.8.2

3.9 TRANSMITTER AND RECEIVER

Receiver Interrupt Control (Bit 1)

This bit disables the Receiver from generating on interrupt
when set to a "I". The Receiver interrupt is enabled when
this bit is set to a "a" and Bit a is set to a "I".

3.8.3

Parity Mode Control (Bits 6, 7)

Data Terminal Ready (Bit 0)

Bits 0-3 of the Control Register select divisor used to
generate the baud rate for the Transmitter. If the Receiver
clock is to use the same baud rate as the transmitter, then
RxC becomes on output and can be used to slave other
circuits to the R65SI. Figure 3-5 shows the transmitter and
Receiver layout.

Transmitter Interrupt Control
(Bits 2. 3)

These bits control the state of the Ready to Send (RTS) line
and the Transmitter interrupt. Figure 3-4 shows the various
configurations of the RTS line and Transmit Interrupt bit
settings.

3.8.4

J4--r-- RxD

Receiver Echo Mode (Bit 4)

This bit enables the Receiver Echo Mode. Bits 2 and 3
must also be zero. In the Receiver Echo Mode, the Transmitter returns each transmission received by the Receiver
delayed by one-half bit time. A "I" enables the Receiver
Echo Mode. A "a" bit disables the mode.

, . . . - - - - - - - - - RxC

XTLI

XTLO

3.8.5

Parity Mode Enable (Bit 5)

This bit enables parity bit generation and checking. A "a"
disables parity bit generation by the Transmitter and parity
bit checking by the Receiver. A "I" bit enables generation
and checking of parity bits.

Figure 3-5.
6

TRANSMITTER/RECEIVER CLOCK CIRCUITS

SECTION 4
OPERATION
4.1 TRANSMITTER AND RECEIVER
OPERATION
4.1.1

Continuous Data Transmit (Figure
4-1 )

In the normal operating mode, the processor interrupt (IRQ)
is used to signol when the R6551 is ready to accept the
next doto ward to be transmitted. This interrupt occurs at
the beginning of the Start Bit. When the processor reads
the Status Register of the R6551, the interrupt is cleared.

CHAR#n+l

CHAR:;n

I

lJlf

iii01JI]

CHAR;;:n+2

/LJI]

~~ ~ ~ '~"o~:~'

,"0""" /
'''''""''
(TRANSMIT DATA

\
'"0"""
""''''"u,
REGISTER. CAUSES IRQ

REGISTER EMPTY I

TO CLEAR

Figure 4-1.

4.1.2

The processor must then identify that the Transmit Data
Register is ready to be loaded and must then load it with
the next dota word. This must occur before the end of
the Stop Bit, otherwise a continuous "MARK" will be
transmitted.

L

CHAR::n+3

Lm

l

"m,,,,",

INTERVAL; OTHERWISE.

~O::!~~~~:T'~~ARK"

CONTINUOUS DATA TRANSMIT

Continuous Data Receive (Figure
4-2)

Simi lor to the above case, the normal mode is to generate
a processor interrupt when the R6551 has received a full
data word. This occurs at about the 9/16 point through the

Figure 4-2.

Stop Bit. The processor must read the Status Register and
read the data word before the next interrupt, otherwise the
Overrun condition occurs.

CONTINUOUS DATA RECEIVE

7

4.1.3

Transmit Data Register Not Loaded
by Processor (Figure 4-3)

If the processor is unable to load the Transmit Data Register
in the allocated time, then the TxD line will go to the
"MAR K" condition unti I the data is loaded. Processor
interrupts continue to occur at the some rate as previously,

CONTINUOUS "MARK"

CHAR#n
I

TxD

except no data is transmitted. When the processor finally
loads new data, a Start Bit immediately occurs, the data
word transmission is started, and another interrupt is
initiated, signaling for the next data word.

CHAR#n+2

CHAR :.tn+1
I

/

r---r-r-"-'-----

I

I

RSI.rt5El~ ~GJiJSlopl

-CHARACTER-I
TIME

LJlr

'LJIJu
"-

INTERRUPT
FOR DATA
REGISTER
EMPTY
PROCESSOR
READS
STATUS
REGISTER

/

INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED

Figure 4-3.

4.1.4

\

~

PRocLoR L...J

WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS. INDICATING TRANSMIT
DATA REGISTER EMPTY

TRANSMIT DATA REGISTER NOT LOADED BY PROCESSOR

Effect of CTS on Transmitter (Figure
4-4)
indicate that the Transmit Data Register is empty. Since
there is no status bit for CTS, the processor must deduce
that CTS has gone to the FALSE (high) state. This is
covered later in this note. CTS is a transmit control line
only, and has no effect on the R6551 Receiver Operation.

CTS is the Clear-to-Send Signal generated by the modem.
It is normally low (True State) but may go high in the event
of some modem problems. When this occurs, the TxD line
immediately goes to the "MARK" condition. Interrupts
, continue at the some rate, but the Status Register does not

CHAR#n

TxD

IRQ

EI~ liE]

CHAR#n+l

CONTINUOUS "MARK"

/

'-/
Slopll

SI.rl~GI~-...L._L-.....L_+---''--.....L_~B2

----;LJI]

r-I

CHARACTER

LllJrn---t---iLllJ

TIME

1
LJIJ

CLEAR·TO·SEND

CTS GOES HIGH.
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. TxD
IMMEDIATELY GOES
TO "MARK" CONDITION

Figure 4-4.

EFFECT OF CTS ON TRANSMITTER

8

NEXT
PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME

PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS NOT EMPTY. PROCESSOR
MUST DEDUCE THAT
IS SOURCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTEI.

m

4.1.5

Effect of Overrun on Receiver
(Figure 4-5)

See 4.1. 2 for normol Receiver operation. If the processor
does not read the Receiver data Register in the allocated
time, then, when the following interrupt occurs, the new
data word is not transferred to the Receiver Data Register,

CHAR#n+l

CHAR#n

"'/

"'/

CHAR#n+3

"'/

P

I

IRQ

CHAR#n+2

}:lsta,t5"EJ ~ ~ liEJStoplstart5"EJ ~ ~ lSEJSto IStart GT\l ~ ~ liEJStoplSta,tr:\El ~ ~ ~
~/

RxD

but the Overrun status bit is set. Thus, the Data Register
will contain the last valid data word received and all
following data is lost.

I
LJl]"

LJ]

PROCESSOR)
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

I

I

LJl]

/LJI]

~

1

PROCESSOR
READS
STATUS
REGISTER

RECEIVER DATA REGISTER
NOT UPDATED. BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA. OVERRUN
BIT SET IN STATUS
REGISTER

,'-------:----------/ ~
"

Figure 4-5.

4.1.6

OVERRUN BIT SET IN
STATUS REGISTER

EFFECT OF OVERRUN ON RECEIVER

Echo Mode Timing (Figure 4-6)

In Echo Mode, the TxD line re-transmits the data on the
RxD line, delayed by 1/2 of the bit time.

TxD

\ \ \ \ \ \ \ \ p\ \
~__...---'== liEJ Stop IStart royt]_Ji.E]Sto ISta,t5T

Figure 4-6.

ECHO MODE TIMING

9

4.1.7

•

Effect of CTS on Echo Mode
Operation (Figure 4-7)
case, however, the processor interrupts signify that the
Receiver Data Register is full, so the processor has no way
of knowing that the Transmitter has ceased to echo.

See 4.1.4 for the effect of CTS on the Transmitter. Receiver
operation is unaffected by CTS, so, in Echo Mode, the
Transmitter is affected in the same way as 4.1.4. In this

CHAR:itn+1

CHAR#n

CHAR#n+2

CHAR#n+3

NOT .cLEAR·TO·SEND

TXD~~~

<;;!:',~:,,~':,L"

L

I' - - - - - - - - - - - - - - - - -

NORMAL
RECEIVER DATA
REGISTER FULL _ _ _ _ _ _ _ _ _ _ _ _ _----1
INTERRUPTS

Figure 4-7.

4.1.8

EFFECT OF CTS ON ECHO MODE

Overrun in Echo Mode (Figure 4-8)

If Overrun occurs in Echo Mode, the Receiver is affected

"MARK" condition until the first Start Bit after the Receiver
Data Register is read by the processor.

the same way as described in 4.1.5. For the re-transmitted
data, when overrun occurs, the TxD line goes to the

CHAR #><+1

CHAR#><

CHAR:;:"

~I!
~~\---Ull
I-L----'---I

LJI]

L-~_....L.---I =~ ~

t

I

TxD DATA
PROCESSOR FINALLY
RESUMES
READS RECEIVER
DATA REGISTER.
LAST VALID
CHARACTER «#nl
PROCESSOR
INTERRUPT
FORCHAR#x
IN RECEIVER
DATA REGISTER

PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER

OVERRUN OCCURS
TxDGOESTO
''MARK''
CONDITION

Figure 4-8.

OVERRUN IN ECHO MODE

10

4.1.9

Framing Error (Figure 4-9)

Framing Errar is caused by the absence of Stop Bit{s) on
received dato. The status bit is set when the processor
interrupt occurs. Subsequent data words are tested for
Framing Error separately, so the status bit will always
reflect the last data word received.

RxD
(EXPECTED) --'_..L...--I

RxD
(ACTUAL) ........_..L...--I

I

iRci

I

----iLllJ~---/--,..;..--1

rrr-

L.lU

r
PROCESSOR
INTERRUPT.
FRAMING
ERROR
BIT SET

NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.

2. IF NEXT DATA WORD ISOK.
FRAMING ERROR IS CLEARED.

Figure 4-9.

FRAMING ERROR

4.1.10 Effect of OeD on Receiver (Figure
4-10)
DCD is a modem output used to indicate the status of the
carrier-frequency-detection circuit of the modem. This
line goes high for a loss of carrier. Normally, when this
occurs, the modem will stop transmitting dato (RxD on the
R6551) some time later. The R6551 wi II cause a processor
interrupt whenever DCD changes state and will indicate
this condition via the Status Register.

Once such a change of state occurs, subsequent transitions
will not cause interrupts or changes in the Status Register
until the first interrupt is serviced. When the Status
Register is read by the processor, the R6551 outomatically
checks the level of the OCO line, and if it has changed,
another interrupt occurs.

CONTINUOUS "MARK"

,

t

NORMAL
PROCESSOR
INTERRUPT

/

AS LONG AS

i>cD IS HIGH.
PROCESSOR
INTERRUPT
FOR DC5
GOING HIGH

Figure 4-10.

NO FURTHER
INTERRUPTS
FOR RECEIVER
WILL OCCUR

PROCESSOR
INTERRUPT
FOR DCD
GOING LOW

EFFECT OF OCD ON RECEIVER

11

NO INTERRUPT
WILL OCCUR
HERE. SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED

PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA

4.1.11 Timing with 1-112 Stop Bits (Figure
4-11 )
It is possible to select 1-1/2 Stop Bits, but this occurs only
for 5-bit data words with no parity bit. In this case, the
processor interrupt for Receiver Data Register Full occurs
in halfway through the trailing half-Stop Bit.

CHAR:it n+1

CHAR#n
I

(

RxD

LJI]
t
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 112
STOP BIT

Figure 4-11.

TIMING WITH 1-1/2 STOP BITS

4.1.12 Transmit Continuous "BREAK"
(Figure 4-12)
This mode is selected via the R6551 Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted.
At least one full "BREAK" character will be transmitted,

even if the processor quickly re-programs the Command
Register transmit mode. Later, when the Command Register
is programmed back to normal transmit mode, an immediate
Stop Bit will be generated and transmission will resume.

P
I

/
"'-/
Stop 1\ ~==EEJStopIStartG;8

t---+--il
~

PERIOD DURING
WHICH PROCESSOR

/ + - - - - - - - - - 1 - SELECTS
CONTINUOUS
"BREAK" MODE

POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

NORMAL
INTERRUPT

Figure 4-12,

TRANSMIT CONTINUOUS "BREAK"

12

I
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
DATA

/

4.1.13 Receive Continuous "BREAK"
(Figure 4-13)
In the event the modem transmits continuous "BREAK"
characters, the R6551 wi II terminate receiving. Reception
will resume only after a Stop Bit is encountered by the
R6551.

~
RxD

CONTINUOUS "BREAK"

]~~~[]iEJStlopIStart,

BO I

B,

, BN

P

,Stop,

"'~--

/

(!-f..l.,-....I...--'rr'""B;~r-~±}·1

plStortl BO

~--------~I

ur'~'__~~________~

U

I

r
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL

~~~RE

B,

IL_..J.J
"

~

PROCESSOR
INTERRUPTS
INTERRUPT
WITH FRAMING
ERROR (PARITY
AND OVERRUN
CHECKS NORMAL)

Figure 4-13.

I I

NO INTERRUPT
SINCE RECEIVER
DISABLED UNTIL
FIRST STOP BIT

r

NORMAL
RECIEVER
INTERRUPT

RECEI VE CONTINUOUS "BREAK"

4.2 STATUS REGISTER OPERATION

4.3 PROGRAMMED RESET
OPERATION

Because of the special functions of the various status bits,
there is a suggested sequence for checking them.
When
an interrupt occurs, the R6551 should be interrogated, as
follows:

A program reset occurs when the processor performs a write
operation to the R6551 with RSO low and RSI high. The
program reset operates somewhat different from the hardware
reset (RES pin) and is described as follows:

1. Reod Status Register

1. Internal registers are not completely cleared. The data

This operation automatica!!Lclear~J (IRQ).
Subsequent transitions on DSR and DCD will cause
another interrupt.

sheet indicates the effect of a program reset on internal
registers.

2. The DTR line goes high immediately.

2. Check IRQ Bit

3.

Receiver and transmitter interrupts are disabled
immediately. If IRQ is low when the reset occurs, it
~ lo~til serviced, unless interrupt was caused by
DCD or DSR transition.

4.

DCD and DSR interrupts disabled immediately. If IRQ
is low and was caused by DCD or DSR, then it goes high,
also DCD and DSR status bits subsequently will follow
the input lines, although no interrupt will occur.

If not set, interrupt source is not the R6551.
3. Check DCD and DSR
These must be compared to their previous levels, which
must have been saved by the processor. If they are both
"0" (modem "on-line ") and they are unchanged then
the remaining bits must be checked.

5. Overrun cleared, if set.
4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.

4.4 MISCELLANEOUS NOTES ON
OPERATION

5. Check Parity, Overrun, and Framing Error (Bits 0-2)

1. If Echo Mode is selected, RTS goes low.

Only if Receiver Data Register is full.

2. If Bit 0 of Command Register is "0" (disabled), then:

6. Check TORE (Bit 4)

a) ~nterr~ disabled, including those caused by
OCD and DSR transitions.
b) Transmitter disabled immediately.
c) Receiver disabled, but a character currently being
received will be completed first . •

Check for Transmitter Data Register Empty.

7. If none of the above, then CTS must have gone to the
FALSE (high) state.

13

float (un-connected). If unused, they must be terminated
either to GND or Vcc.

3. Odd parity occurs when the sum of all the "1" bits in
the data word (including the parity bit) is odd.

•

4. In the receive mode, the received parity bit does not go
into the Receiver Data Register, but is used to generate
parity error for the Stotus Register.

4.5 GENERATION OF
NON-STANDARD BAUD RATES

5. Transmitter and Receiver may be in full operation
simultaneously.

4.5.1

This is "full-duplex" mode.

6. If the RxD line inadvertently goes low and then high

Divisors

The internal counter/divider circuit selects the appropriate
divisor for the crystal frequency by means of bits 0-3 of
the R6551 Control Register.

right after a Stop Bit, the R6551 does not interpret this
as a Start Bit, but samples the line again halfway into
the bit to determine if it is a true Start Bit or a false
one. For false Start Bit detection, the R6551 does not
begin to receive data, instead, only a true Start Bit
initiates receiver operation.

The divisors, then, are determined by bits 0-3 in the
Control Register and their values are shown in Figure 4-14.

7. Precautions to consider with the crystal oscillator

4.5.2

circuit:
a) The external crystal to be used should be a "series"
mode crystal.
b) The XTAlI input may be used a an external clock
input. The unused pin must be floating and may
not be used for any other function.

Generating Other Baud Rates

By using a different crystal, other baud rates may be
generated. These can be determined by:
B d R t =_ Crystal Frequency
au
a e
Divisor

8. DCD and DSR transitions, although causing immediate
Furthermore, it is possible to drive the R6551 with an offchip oscillator to ochieve the some thing. In this case,
XTAL\ (pin 6) must be the clock input and XTALO (pin 7)
must be a no-connect.

processor interrupts, have no affect on transmi Iter
operation. Data will continue to be sent, unless the
processor forces transmitter to turn off. Since these are
high-impedance inputs, they must not be permitted to

r -co-N,'iloi-"--OIViSoRSElECTED ---r-iAUD RArEGENiRATED--T --BAUD-RATE GENERATED
REGISTER

FOR THE

I

WITH 1.8432 MHz

WITH A CRYSTAL

tn~~~0~~F~~~~1}:;:ITI~~~,==:~--~~Ri~~;'o

0

1

0

24576

f-----.--. ' - - - - - - - . - - - -

!Jl432 x J.Q' "' 75
-~-.--~§-.----.------- - - - . __ ._..?!.~r§____ . ____ .

0 1 1
16.769
1. 8~~27:9 10' = 109 92
1-6.~69---------------- ._-------------- - --------- -------------o
1 0 0
13 704
~..2'...~ = 13451
__f.... __
/--____________
. _ _ _ +-____
13.704
o 1 0 1
12.288
18432 x 10'
50
-----------F"-------

o

---------------

~_______

________ 1_----------- _~

~.1
o

1

12.288- ~ _______ I_----

'2.2~~ ____ _

1

0

6.144

~ = 3 0 0 _ f -_ _ _ _ .:...6.~44 :_______.

1

1

3.072

~ = 600

t------ - - 1 - - - - -

1 0 0 0
1.536
1.84 3.2 X 10' = 1.200
1 53 6
f-----.-f-------------I------"-'-"""'-----184;.202X4 10' = 1.800
1 0 0 1
1.024

3.~72~_______

- - f - - - - _____

_F_

.-------~

___--+_ _----=-='--__.______

1.536
F
--.--1.024

1.8432 x 10'
--------F--:-:--·768
____
_ _ _ _-I--_~~~7;6""8-_-___=__=_2_.4_0_0____ I---_~ ______ _
1.8432 x 10'
_F_
1 0 1 1
512
---si2-- = 3.6_0_0___1--_ _ _--"--'~
512 ___ _
f-----+-----------I--.
-__F_
184;~4X 10' = 4.800
1 1 0 0
384
384
_F_
1.84;~: 10' = 7.200
1 1 0 1
256
256
_F_
I.B432
x
10'
=
9600
192
1 1 1 0
192
._
192
_F_
1843!,x 10' = 19.200
1 1 1 1
96
96
1

0

1

0

---

Figure 4-14.

DIVISOR SELECTION FOR THE R6551

14

4.6 DIAGNOSTIC LOOP-BACK
OPERATING MODES

to its own receiver, so that the processor con perform
diagnostic checks an the system, excluding the actual
data channel.

A simplified block diagram for a system incorporating an
R6551 ACIA is shown in Figure 4-15.

2. Remote Loop-Back
Loop-back from the point of view of the Data link and
Modem. In this case, the processor, itself, is disconnected and all received data is immediately
retransmitted, so the system on the other end of the
Data link may operate independent of the local system.

MICRO·

PROCE~OR~--~~------~------~------~---

The R6551 does not contain automatic loop-back operating
modes, but they may be implemented with the addition of
a small amount of external circuitry.
Figure 4-16 indicates the necessary logic to be used with
the R6551.
The LLB line is the positive-true signal to enable local
loop-back operation. bsentially, LLB = high does the
following:

TO DATA LINK

1. Disables outputs TxD, DTR, and RTS (to Modem).
Figure 4-15.

SIMPLIFIED SYSTEM DIAGRAM

2. Disables inputs RxD, DCD, CTS, DSR (from Modem).
3. Connects transmitter outputs to respective receiver
inputs :

Occasionally it may be desirable to include in the system
a facility for "loop-back" diagnostic testing, of which
there are two kinds:

a) TxD to RxD
b) DTR to DCD
c) RTS to CTS

1. Local Loop-Back

LLB may be tied to a peripheral control pin (from an R6520
or R6522, for example) to provide processor control of local
loop-back operation. In this way, the processor can easily
perform local loop-back diagnostic testing.

Loop-back from the point of view of the processor. In
this case, the Modem and Data link must be effectively
disconnected and the ACIA transmitter connected back

I

R6551
RTS OTR TxO

RxO

LLB

;dJ

SEL

-:r-

6CD ffi 0sR

I

3Y

STO

4Y

-

74157
10

1A

20

2A

30

3A

~40

4A

RxO
OCO
CTS
DSR
MODEM

-

SEL

TxO

1Y

OTR

2Y

F
+5

C
-

STO

RTS

3Y
4Y

74157

-

10

1A

20

2A

3D

3A

40

4A -

NOTES:

1. HIGH ON LLO SELECTS LOCAL LOOP·OACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES "0" INPUTS
TO "y" OUTPUTS; LOW GATES "A" TO "Y".

Figure 4-16.

LOOP-BACK CIRCUIT SCHEMATIC

15

•

•

The circuit connections are quite simple and are outlined
in Figure 4-17.

Remote loop-bock does not require this circuitry, so UB
must be set low. However, the processor must select the
following:

6551

+5

1. Control Register bit 4 must be "1", so that the transmitter
clock = receiver clock.

~-+_-+_-<:~ ~~Tp::ES

2. Command Register bit 4 must be "1" to select Echo
Mode.

Dci5

3. Command Register bits 3 and 2 must be "1" and "0",

DsR~-----<:~11

/

respectively to disable IRQ interrupt to transmitter.

WIRES

4. Command Register bit 1 must be "0" to disable IRQ
interrupt for receiver.
In this way, the system re-transmits received data without
any effect on the local system.

Figure 4-17.

4.7 DCD AND DSR AS SWITCH

CIRCUIT CONNECTIONS FOR
DCD AND DSR

Note that pull-up resistors are required, since DCD and
DSR are high-impedance inputs on the R6551.

SENSE INPUTS

In order to sense the state of the inputs, it is necessary to
do the following:

The R6551 (Asynchronous Communication Interface
Adapter) has several specia~pose control pins. Among
them are the input signals, DCD (Data Carrier Detect)
and DSR (Data Set Ready). The normal functions of these
pins are adequately described in the R6551 data sheet and
are not covered here. However, it is possible to use these
pins as switch sense inputs; that is, as input pins used to
detect the state of switches or circuit jumpers in the
system.

1. Disable the R6551 by setting bit
Register to a "0".

a of the Command

2. Read the R6551 Status Register. Bits 5 and 6 will then
indicate the levels on DCD and DSR, respectively.
A "0" is a low level and a "\" is a high.
As long as the R6551 is disabled, the Status Register will
reflect the levels on the pins and no interrupts will occur,
even if the pins change state. However, if the R6551 is
enabled, then changes of state of the DCD and DSR levels
couse immediate interrupts and the Status Register indicates
the levels taken on the interrupt. Subsequent level
changes are not indicated by the Status Register until the
interrupt is serviced. Thus, it is not convenient to use
DCD and DSR os general switching inputs, but they may
easily be used as inputs which do not change regularly.

An important requirement of the use of DCD and DSR as
sense inputs is that they must not normally change state
during system operation. If they do, and if the R6551 is
enabled, then immediate processor interrupts wi I I occur
and norma I operation wi II be interrupted. If, however,
these pins are connected to switches or circuit-board
jumper wires which do not change state during operation,
then they can be sensed by the processor and may be used
to select special operating modes.

16

APPENDIX
CHARACTERISTICS AND RATINGS

READ/WRITE CYCLE CHARACTERISTICS
(Vee

= 5.0V ±5%. T A = 0

to 70°C. unless otherwise noted)
1 MHz
Symbol

Characteristic

2 MHz

Min

Max

Min

Max

Unit

Cycle Time

teye

1.0

40

0.5

40

J.ls

02 Pulse Width

te

400

-

200

-

ns

Address Set·Up Time

tAe

120

-

70

-

ns

Address Hold Time

teAH

0

-

0

-

ns

R/iN Set· Up Time

twe

120

--

70

-

ns

R/Vi Hold Time

tewH

0

-

0

-

ns

-

ns

Data Bus Set-Up Time

tDCW

150

-

60

Data Bus Hold Time

tHW

20

-

20

-

-

ns

Read Access Time (Valid Data)

teDR

150

ns

Read Hold Time

tHR

20

-

20

-

ns

Bus Active Time (Invalid Data)

teDA

40

-

40

-

ns

200

(t r and tf = 10 to 30 ns)
'CYC
'C

\'-______...J/r-----::~

--J/

02 _ _ _ _

4

CSO.

ffi.

RSO. RSl

'CAH.

~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~X~---------------VIH
-----IL
.....____________ V
1L

-

RtW

'WC

•

~
j'--------V 1H
V
\ '_-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
1L

,JXL________________-'X

V1H

r

DATA BUS _ _ _ _ _ _ _ _ _ _ _

------

~-----VIL

-

Write Timing Characteristics

Read Timing Characteristics

17

TRANSMIT/RECEIVE CHARACTERISTICS
1 MHz

--- tCCY
XTLI
(TRANSMIT
CLOCK INPUT)

2MHz

Symbol

Min

Max

Min

Max

Unit

Transmit/Receive
Clock Rate

tCCY

400"

-

400"

-

ns

Transmit/Receive
Clock High Time

tCH

175

-

175

.-

ns

Transmit/Receive
Clock low Time

tCl

175

-

175

-

ns

XTll to TxD
Propagation Delay

too

-

500

-

.500

ns

RTS Propagation
Delay

t Dly

-

500

--

500

ns

\~:-

tlRQ

-

500

-

500

ns

_ - - - + - - .Dt

Characteristic

rna Propagation

~CL'-

~\.._ _ __

'DO,

TxO

NOTE: TxO rate is 1/16 TxC rate

Transmit Timing with External Clock

'
LYC

Delay (Clear)

DTR, RTS
(t , t =
r f

10 to 30 nsl

"The baud rate wilh exlernal clocking is: Baud Rale

=

~
x

-------------4---

CCy

IRQ
______
(CLEAR) _

~

i_t_IR~Q}-j

__________

Interrupt and Output Timing

i·· -.---- tCCY .- ----- - -!
1_---

i
RxC
(INPUT)

NOTE: RxO rate is 1/16 RxC rate

Receive External Clock Timing

PACKAGE OUTLINES
28 LEAD PLASTIC

28 LEAD CERAMIC

I
~~~~~~~~~~~~~
-I~'

(.5SOI

~_-=--

__ :~::: ____~

~

1.1151
1.0101

~

~Al.ol2t

~

1--1.6201
I
(.1101
(.5901-'"
1.0901
(.1551 1.0661
(.llSl (.0151

1.0011

(1.4701

- ( 1 . 4 4 0 I - i t r = : I ; : = t , ...,

II

(.0151
(.0661

18

1.1&01

jt(·0661
(.0451

_

t I

-j

t-

(.0231 .032 REf. (.1101
(,0151
1.0101

~T
LI.
\ "\

7OO'

(&001

1.1501 (.0101
1.1251 (.0201

---l

(.0011

SPECIFICATIONS
Maximum Ratings
Rating

Symbol

Value

Unit

Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature

VCC
Vin
T
TSTG

-0.3 to +7.0
-0.3 to +7.0
o to +70
-55 to +150

Vdc
Vdc

°c
°c

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to
avoid application of voltages higher than the maximum rating.

Electrical Characteristics
(VCC ; 5.0 ±.5%, T A ; 0-70 0 C, unless otherwise noted)
Characteristic

Symbol

Input High Voltage
(Except XTLI and XTLO)
(XTLI and XTLO)

VIH

Input Low Voltage
(Except XTLI and XTLO)
(XTLI and XTLO)

VIL

Input Leakage Current: VIN; 0 to 5V.
(02, R/W, RES, CSO, CS1, RSO, RS1, CTS, RxD, DCO, DSR)

liN

Typ

Max

2.0
2.4

-

-

VCC
VCC

VSS'
VSS

-

0.8
0.4

Unit
V

V

-

±'2.5

~A

ITSI

-

VOH

2.4

-

-.

V

Output Low Voltage: I LOAD; 1.6 mA
(00-07), TxO, RxC, RTS, OTR, IRO)

VOL

--

-

0.4

V

Output High Current (Sourcing): VOH; 2.4V
(00-07, TxO, AxC, ATS, OTA)

IOH

-100

Output low Current (Sinking): VOL; O.4V
(00-07, TxO, RxC, RTS, OTR,IRO)

IOL

1.6

Input Leakage Current for High Impedance State (Three State)
Output High Voltage: ILOAO; -100
(00-07, TxO, RxC, RTS, OTR)

r-'

Min

~A

Output Leakage Current (off state): VOUT; 5V (JRO)

IOFF

-

Clock Capacitance (02)

CCLK

-

Input Capacitance (except XTLI and XTLO)
Output Capacitance

-

Power Dissipation

~A

-

~A

-

-

mA

10.0

~A

-

20

pF

CIN

-

-

10

pF

. COUT

-

-

10

pF

-

170

300

mW

Po

19

±.10.0

•

•

DOCUMENT NO. 29000058
JUNE 1979

:;"l'::RockW~~~:
•

R6592

,

•

R6S00 Microcomputer System

~i

',,".:'
,

PART NUMBER

DATA SHEET

I

SINGLE-CHIP PRINTER CONTROLLER
INTRODUCTION

FEATURES

The Rockwell R6592 is a single-chip printer controller for eight
different EPSON* dot-matrix impact printers, models 210,220,
240, 511l, 512, 522, 541l, and 542. The R6592 offers the flexibility to support any of these models with a minimum of circuitry.
Generation of 96 standard ASCII upper and lower case characters
and 6 special characters is provided. In addition, up to 10 ASCII
control commands are accepted, depending upon the printer.
logic is included in the R6592 to print up to 26 columns on the
210, 220, and 240 models, and up to 40 columns on the 511l,
512,522, 541l, and 542 models.

•

Input data may be selected to be in the RS-232 serial format with
selectable baud rate from 50 to 7200 bits/second or the parallel
format_ External circuitry is required to convert RS-232 logic
levels to R6592 interface logic levels. An external latch may be
required for the R6592 to sample parallel data. If both selectable
serial and parallel data interface capability is desired, two external
multiplexers are required; one to combine four serial baud select
lines and four parallel data interface lines into four R6592 input
lines and the other to combine two serial data/control lines and
two parallel control lines into two other R6592 input lines.
This data sheet summarizes the interface specifications of the
R6592. Product Description 29650N56 describes the operation
of the R6592 in .?etail.

r-

•

On-Chip 5 x 7 Dot-Matrix Character Generation

•

96 Standard Upper and lower Case ASCII Characters (7 Bit
Code)

o

•

Six Special ASCII Characters (7 Bit Code)

•

Up to 10 ASCII Commands Accepted (Printer Dependent)

•

Selectable Serial or Parallel Input Data Operation

•

Centronics Standard Parallel Interface
- Seven Data lines Plus Data Strobe and Input Drive Input
- Busy and Acknowledge Output
RS-232C Serial Interfaea
Baud Rate from 50 to 7200 Bits per Second
- Received Data and Data Set Ready Input
- Data Terminal Ready Output

•

Single +5V ± 10% power supply

•

40 pin plastic or ceramic DIP

•

1 MHz operation (2 MHz external crystal)
VCC (+S Vdcl

PCi:2

PTR TIM

PCU

DS/ifSD

NC

ACt<

SER SEL
PRT
PM2
PM3

BUSY/DTR

irn

XTLI
XTLO

VCC

RL/RL.
DLl
DL2
DL3
DL4
DLS

PS4

DL6

I>s3
PS2

DL7
INP/DSR
SER CLK

PSl

"'0
"'0

-::xJZ

-t

m
::xJ

o

o
::xJ

RES

PSS

:I:

2

VRR

MDS

I

-t

PEL3

PS7
PS6

All Right. RnaMld
Printed in U.S.A.

G")

m

VSS

@ Roct

N

t

n

?

0

--

-

/

0

DEL

A

1010

LF

¥

.

9

B

1011

VT

t

+

;

C

1100

FF

12

0

1101

CR

ri

E

1110

F
LF
VT
FF
CR
DCl
DC2
DC3
DC4
CAN

a
000

1111

-

N
T
T

X

-

Line Feed
Vertical Tabulation
Form Feed
Carriage Return
Device Control 1
Device Control 2
Device Control 3
Device Control 4
Cancel
Yen
Pound
Cent
One-Half
No Tax
Tax

Note: Valid control commands are dependent upon printer model.

Parallel Data Interface
r-BUSY
BUSY RET

11
29

INPUT PRIME
INPUT PRIME RET

31
30

DATA STROBE
DATA STROBE RET

1
19

ACKNOWLEDGE
ACKNOWLEDGE RET

10
28

2
20

DATA 1
DATA 1 RET

3
21

DATA 2
DATA 2 RET
DATA 3
DATA 3 RET

4
22

DATA 4
DATA 4 RET

5
23

DATA 5
DATA 5 RET

6
24

~

BUSY/DTR

~

iP/DSR

~

~&~

8
R6592

DLlIBR1

29

--.. 28
DL3/BR3

,.

27

~

LATCH*

DL4/BR4
26

~
~

8
26
9 ~
___
27

37

DL2/BR2

,.

DATA 7
DATA 7 RET

"--

--..

--..

~

7
25

CENTRONICS
PARALLEL INTERFACE

22

ACK

DATA 6
DATA 6 RET

DATA 8
DATA 8 RET

--..

-

Os

~

9

~

,.

DL5

.

DL6

25

.

DL7

-

24

23

~
R6592 INTERFACE

*NOT REQUIRED IF PARALLEL DATA IS HELD FOR ~50J.LS
AFTER LEADING EDGE OF
OR UNTIL ACK IS RECEIVED.

os

Parallel Data Timing
------~(
INPUT PRIME (iP)

-

\-S

----~f r----f~1t_- - -

- - - - - - - - q - - - - ---H-U~-~$

'-f- - - - - (

-H- --{ f- - - -

f----{f---{ J

DATA STROBE (OS)

:.f.~'1 I-

r-

PARALLEL DATA (DL1.DL71

I

---.....

50

~S (M,N'"

----J

1 t----i

L----f ~f--{ .,..~- - -

!

-----!(

'-f

ACKNOWLEDGE lACK)

5J.LS
(TYP)

BUSY

r-

f-----4 r-,

~I ~I
•

------~Jf~--~r~~~~-*OR UNTIL

AcK IS RECEIVED.

Serial Data Interface
DET ENA

7

SER ClK
21

ClK
RECEIVED SERIAL
DATA IRSD)

3

2

a

0

DS/RSD
5

37
R6592

7474

iP/DSR

DATA SET READY IDSR)

22

+12V
DATA TERMINAL READY (DTR)

BUSY/DTR

20 . .------C~
·12V

~

9

~

R6592 INTERFACE

RS·232 INTERFACE

Serial Data Timing
----------------...---------...---------------------~$~r4r____
DATA SET READY (DSR)

- - - - --ff--/r -{ f- ---

SERIAL DETECT ENABLE (DET ENA)

SERIAL CLOCK (SER ClK)
7 BIT CODE DATA SAMPLES:

t

RECEIVED SERIAL DATA (RSD)

RECEIVED SERIAL DATA IRSD)

--:--________---11'

k~BI

START B I T 1 - :

t--

3

I I I I
4

5

6

7 BIT CODE

b~d
:=:j-7

RECEIVED DATA BITS
DATA TERMINAL READY IDTR)

DATA TERMINAL READY (DTR)

I H H J---r-

PARITY BIT AND----l
2 OR MORE STOP BITS

--------------------~st\r_

PRINTER INTERFACE SPECIFICATIONS
The R6592 is designed to meet the interface requirements stated in
the following printer specifications'

•

For further printer information, contact:
EPSON America, Inc.
23844 Hawthorne Blvd. Ltd.
Torrance, CA 90505
Phone: (213) 378·2220
TWX: 910·344·7390

Model·210 Impact Dot Matrix Mini·Printer (Preliminary) Rev. 4,
AUGUST 30, 1978
Model·220 Impact Dot Matrix Mini·Printer, SEPTEMBER 18,1978
Model·240 Impact Dot Matrix Mini·Printer, SEPTEMBER 18, 1978
Model·511 L Impact Dot Matrix Printer (Enlarged Char3cter)
Revision 1,JULY 13,1978

C. Itoh Electronics, Inc.
5301 Beethoven Street
Los Angeles, Calif. 90066
Phone: (213) 390·7778
Telex: WU 65·2451

Model 512 Dot·Matrix Impact Printer (P512DFl. APRIL 10, 1978
Model 522 Dot·Matrix Impact Printer (P522DF), MARCH 1, 1978
Model 541 L Impact Dot Matrix
Revision 1,JULY 19,1978

C. Itoh Electronics, Inc.
280 Park Avenue
New York, New York, 10017
Phone: (212) 682·0420
Telex: WUD·12·5059

Printer (Enlarged Character),

Model 542 Dot·Matrix Impact Printer (P542DFl. MARCH 1,1978

100 MAX

D

DOT OR NOTCH
TO LOCATE

PIN NO 1

-

o

L-

.-r
dl~
~
~.87)
JO (:;::tt:5~
0.600 MAX

0625

0155 MAX
(3.93 MM)
2.020 MAX
(51.30 MM)

cm~h~AX

~~TYP~t
(1.01) 0.040

~ ~-L",~"·.~,~MI

.

0.100 MIN
(2.54 MM)

(0.55) 0.022
(0.45) 0.018 TYP.

~
~

(48.51 MM)

1.890

(48.00 MM)

(0.25 MM)

19 EQUAL SPACES


~
I

"

o
I

Ordering Information

The R6530 is designed to operat.. In conjunction with the R6500
Microprocessor Family. It is comprised of a mask programmable
1024 x a ROM, a 64 x a static RAM, two software controlled
a bit bidirectional data ports allowing direct interfacing between
the microprocessor unit and peripheral devices, and a software
programmable interval timer with interrupt, capable of timing in
various intervals from 1 to 262,144 clock periods.

•
-

ROM-RAM-I/O-INTERVAL TIMER DEVICE (RRIOT)

Number

Package
TVpe

Temperatura
Range

R6530P
R6530C

Plastic
Ceramic

OOC to+700C
OOC to +700C

A custom number will be assigned by Rockwell.

z~

m
::a

~.

r-

:!
PAO

DATA
DIRECTION
REGISTER

pao

PA7

OUTPUT
REGISTER

~

m

PB7

:a
OUTPUT
REGISTER
B

INTERVAL
TIMER

A

om

S·
m

(")

-

::a
::a

-.::t
o

DATA
BUS
BUFFER

DO

@ Rockwell

ADDRESS
DECODER

07

AO

International Corporation 1979
All Rights Reserved
Printed in U.S.A.

CHIP
SELECT

R/W

64 x a
RAM

1Kx a
ROM

DATA
DIRECTION
REGISTER
B

A9

Specifications subJect to
change without notice

-...

INTERFACE SIGNAL DESCRIPTION

I
-.

--

Reset (RES)

Address Lines (AO-A9)

During system initialization a Logic "0" on the RES input will
cause a zeroing of all four I/O registers. This in turn will cause all
I/O buses to act as inputs thus protecting external components
from possible damage and erroneous data while the system is being
configured under software control. The Data Bus Buffers are put
into an off state during Reset. Interrupt capability is disabled
with the RES signal. The ~ signal must be held low for at least
one clock period when reset is required.

There are , 0 address pins (AO·A9). In addition, there is the
ROM Select pin (RSO)' Further, pins PB5 and PB6 are mask
programmable, and can be used either individually or together as
chip selects. When used as peripheral data pins they cannot be
used as chip selects.

~.

Read/Write (R/W)
The R/W signal is supplied by the microprocessor and is used to
control the transfer of data to and from the microprocessor and
the R6530. A high on the R/W pin allows the processor to read
(with proper addressing) the data supplied by the R6530. A low
on the R/W pin allows a write (with proper addressing) to the
R6530.

INTERNAL ORGANIZATION
The R6530 is divided into four basic sections: RAM, ROM,
I/O and Timer. The RAM and ROM interface directly with the
microprocessor through the system data bus and address lines.
The I/O section consists of two B·bit halves. Each half contains
a Data Direction Register (DDR) and an Output Register.

Interrupt Request (iRQ)
The IRQ pin is an interrupt pin from the interval timer. This same
pin, if not used as an interrupt, can be used as a peripheral I/O pin
(PB7). When used as an interrupt, the pin should be set up as an
input by the Data Direction Register. The pin will be normally
high with a low indicating an interrUPt from the R6530. An exter·
nal pull·up device is not required; however, if collector·OR'd with
other devices, the internal pullup may be omitted with a mask
OPtion.

Data Bus (00-07)
The R6530 has eight bidirectional data pins (DO·D7). These pins
connect to the system's data lines and allow transfer of data to
and from the microprocessor. The output buffers remain in the
off state except when selected for a Read operation.
Peripheral Data Ports
The R6530 has 16 pins available for peripheral I/O operations.
E~ch pin is individually software programmable to act as either
an input or an output. The 16 pins are divided into two B·bit
ports, PAO·PA7 and PBO·PB7. PB5, PB6 and PB7 also have other
uses which are discussed in later sections. The pins are set up as
an input by writing a "0" into the corresponding bit of the Data
Direction Register. A "'" into the Data Direction Register will
cause its corresponding bit to be an output. When in the input
mode, the Peripheral Data Buffers are in the "'" state and the
internal pull·up device acts as less lhan one TTL load to the
peripheral data lines. On a Read operation, the microprocessor
unit reads the peripheral pin. When the peripheral device gets
information from the R6530 it receives data stored in the Out·
put Register. The microprocessor will read correct information
if the peripheral lines are greater than 2.0 volts (for a "1") or
less than O.B volts (for a "0") as the peripheral pins are all TTL
compatible.

ROM 1 K Byte (8K Bits)
The BK ROM is in a 1024 x B configuration. Address lines AO·A9,
as well as RSO are needed to address the entire ROM. With the
addition of CS1 and CS2, seven R6530's may be addressed, giving
7168 x B bits of contiguous ROM.
RAM - 64 Bytes (512 Bits)
A 64 x B static RAM is contained on the R6530. It is addressed
by AO·A5 (Byte Select), RSO, A6, A7, AB, A9 and, depending
on the number of chips in the system, CS1 and CS2.
Internal Peripheral Registers
There are four internal registers, two data direction registers and
two output registers. The two data direction registers (A side
and B side) control the direction of the data into and out of the
peripheral pins. A "'" written into the Data Direction Register
sets up the corresponding peripheral bu ffer pin as an output.
Thereiore, anything tilen written into the Output Register will
appear on that corresponding peripheral pin. A "0" written
into the DDR inhibits the output buffer from transmitting data
from the Output Register. For example, a "'" loaded into Data
Direction Register A, pOSition 3, sets up peripheral pin PA3 as an
output. If a "0" had been loaded, PA3 would be configured as
an input and remain in the high state. The two Data Output
Registers are used to latch data from the Data Bus during a Write
operation until the peripheral device can read the data supplied
by the microprocessor.
During a Read operation the microprocessor is reading the periph·
eral data pins. For the peripheral data pins which are programmed
as outputs the microprocessor will read the corresponding data
bits of the Output Register. The only way the Output Register
data can be changed is by a microprocessor Write operation.
The Output Register is not affected by a Read of the data on the
peripheral pins.

Interval Timer
The Timer section of the R6530 contains three basic parts: pre·
scale divide down register, programmable 8·bit register and inter·
rupt logic.
The interval timer can be programmed to count up to 256 time
intervals. Each time interval can be either 1T, 8T, 64T or 1024T
increments, where T is the system clock period. When a full count
is reached, an interrupt flag is set to a logic "1". After the inter·
rupt flag is set the internal clock begins counting down to a maxi·
mum of ·255T. Thus, after the interrupt flag is set, a Read of the
timer will tell how long since the flag was set up to a maximum of
255T.
The 8 bit system Data Bus is used to transfer data to and from the
Interval Timer. If a count of 52 time intervals were to be counted,
the pattern 0 0 1 1 0 1 0 0 would be put on the Data Bus and
written into the Interval Timer Register.
At the same time that data is being written to the Interval Timer,
the counting interval (1, 8, 64 or 1024T) is decoded from address
lines AO and A 1. During a Read or Write operation address line
A3 controls the interrupt capability of PB7, i.e., A3 ; 1 enables
IRQ on PB7, A3 ; 0 disables IRQ on PB7. When PB7 is to be used
as an interrupt flag with the interval timer it should be pro·
grammed as an input. If PB7 is enabled by A3 and an interrupt
occurs PB7 will go low. When the timer is read prior to the interrupt flag being set, the number of time intervals remaining will be
read, Le., 51, 50, 49, etc.

When the timer has counted down to 0 0 0 0 0 0 0 0 on the
next count time an interrupt will occur and the counter will read
1 1 1 1 1 1 1 1. After interrupt, the Timer Register decre·
ments at a divide by "1" rate of the system clock. If after inter·
rupt, the timer is read and a value of 1 1 1 0 0 1 0 0 is read, the
time since interrupt is 27T. The value read is in one's complement.
Value read
1 1 1 0 0 1 0 0
Complement; 0 0 0 1 1 0 1 1; 27

Thus, to arrive at the total elapsed time, merely do a one's com·
plement and add to the original time written into the timer. Again,
assume time written as 0 0 1 1 0 1 0 0 (;521. With a divide
by 8, total time to interrupt is (52 x 8) + 1 ; 417T. Total elapsed
time would be 417T + 27T ; 444T, assuming the value read after
interrupt was 1 1 1 0 0 1 0 O.
After the interrupt, whenever the timer is written or read the
interrupt is reset. However, the reading of the timer at the same
time the interrupt occurs will not reset the interrupt flag. When
the interrupt flag is read on DB7 all other DB outputs (OBO thru
DB6) go to "0".
When reading the timer after an interrupt, A3 should be low so as
to disable the IRQ pin. This is done so as to avoid future interrupts until after another Write timer operation.

R!W

DIVIDE

DOWN

06

07

04

<1>2

02 DO

Basic Elements of Interval Timer

<1>2 IN
WRITET ~~________________________________________________________________________________

1. Data written into interval timer is 0 0 1 1 0 1 0 0 ; 52 10
2. Data~~dnterval timer is 0 0 0 1 1 0 0 1 ; 25 10
52 . 8 . 1 ; 52·26·1 ; 25
3. Data~~5Interval timer is 0 0 0 0 0 0 0 0; 0 10
52·

a

· l ;52·51·1;0

4. Interrupt has occurred at 02 pulse #416
Data in Interval timer = 1 1 1 1 1 1 1
5. Data in Interval timer is 1 0 1 0 1
0 0
two's complement is 0 1 0 1 0 0 1 1 = 83 10
83 + (52 x 8) + 1 = 500
10

•

- ...

--

I

Seven-Chip Addressing

ADDRESSING

I
-

...

--

Addressing of the R6530 offers many variations to the user for
greater flexibility. The user may configure his system with RAM
in lower memory, ROM in higher memory, and 1/0 registers with
interval timers between the extremes. There are 10 address lines
(AO·Ag). In addition, there is the possihility of 3 additional
address lines to be used as chip-selects and to distinguish between
ROM, RAM, 1/0 and interval timer. Two of the additional lines
are chip·selects 1 and 2 (CSl and CS2l. The chip-select pins can
also be PB5 and PB6. Whether the pins are used as chip-selects or
peripheral 1/0 pins is a mask option and must be specified when
ordering the part. Both pins act independently of each other in
that either or both pins may be designated as a chip-select. The
third additional address line is RSO. The R6502 and R653a in a
2·chip system would use RSO to distinguish between ROM and
non·ROM sections of the R6530. With the addressing pins available, a total of 7K contiguous ROM may be addressed with no
external decode. Below is an example of a l-chip and a 7-chip
R6530 Addressing Scheme.

One·Chip Addressing
A l-chip system decode for the R6530 is illustrated on the top of
the following page.

In the 7-chip system the objective would be to have 7K of contigu·
ous ROM, with RAM in low order memory. The 7K of ROM
could be placed between addresses 65,535 and 1024. For this
case, assume A13, A14 and A15 are all 1 when addressing ROM,
and 0 when addressing RAM or 1/0. This would place the 7K
ROM between addresses 65,535 and 58,367. The 2 pins desig.
nated as chip·select or 1/0 would be masked programmed as
chip·select pins. Pin RSO would be connected to address line
A 10. Pins CSl and CS2 would be connected to address lines
A 11 and A 12 respectively. See illustration below.
The two examples shown would allow addressing of the ROM
and RAM; however, once the 1/0 or timer has been addressed,
further decoding is necessary to select which of the 1/0 registers are desired, as well as the coding of the interval timer.
I/O Register - Timer Addressing
Addressing Decode for 1/0 Register and Timer illustrates the
address decoding for the internal elements and timer program·
mingo Address lines A2 distinguishes 1/0 registers from the timer.
When A2 is high and 1/0 timer select is high, the I/O registers are
addressed. Once the 1/0 registers are addressed, address lines Al
and AO decode the desired register.
When the timer is selected Aland AO decode the divide by matrix.
In addition, Address A3 is used to enable the interrupt flag to
PB7.

R6530 Seven Chip Addressing Scheme
The addressing of the ROM select, RAM select and 1/0 Timer select lines would be as follows:

R6530 #1,

R6530 #2,

R6530 #3,

R6530 #4,

R6530 #5,

R6530 #6,

R6530 #7

CS2

CSl

~

.8.l!

RSO
Ala

ROM SELECT
RAM SELECT
1/0 TIMER

0
0
0

0
0
0

1
0
0

ROM SELECT
RAM SELECT
1/0 TIMER

0
0
0

1
0
0

ROM SELECT
RAM SELECT
1/0 TIMER

0
0
0

ROM SELECT
RAM SELECT
1/0 TIMER

A6

A9

~

jg

X

X

X

X

0

0

0
0

0

0
0
0

X

X

X

X

0

0

0
0

1

1
0
0

X

X

X

X

0
0

0

0
0

1
0
0

0
0
0

0
0
0

x

x

0

0
0

ROM SELECT
RAM SELECT
1/0 TIMER

0
0
0

1
0
0

X

X

0
0

ROM SELECT
RAM SELECT
1/0 TIMER

1
0
0

1
0
0

a
0
0

x
0

ROM SELECT
RAM SELECT
1/0 TIMER

X

0
0

0
0

0
0

0

'RAM select for R6530 #5 would read

A 12 em e A 10 eM eA8 eA7

eA6

0

x

X

1
X

X

0
0

0

x

x

X

1

0
0

1

X

X

0

X

0
0

. - - - - - - AJ
_ _ _ A1

r-

AO

II/OSEL

~

~

Al

110

AO

•
-

.

r - - - - - - - - - - - - - - - - --r=-=;-

:

(I

(')

I

hrl

I

:~~+-~-+-r+-~-+-r+-~-+-r+-r

__ -1---1-1--

AJ
A1

A1
__ AO

::--t>>O+-+-H-++-+-H-++-+-H-+*""+

AB

A7

A6

:l{)>O+-~~-++-+-H-++-~~----­

:_l{)~+-H-r*~~-r+-+-~-+----­
:~~+-~-+-r*-~-+-r+-~r+----:l{)>o+-~-+~~~-+~+-~~-----

X
I

,"dlcilte~maskpf09rammlnq

e. ROM select

~ ~S 1.

RAMseleCI -

RSO

ffi.R'SQeAq'_A7eA6

I/O TIMER SELECT: CS'l.FiSci.A9.AS.A1eA6
NOllce thai A8 IS iI don"' care tor RAM ~t"lecl

CS2Cdflbe used as PB5m th,se.llampl",

R6530 One Chip Address Encoding Diagram

Addressing Decode for 1/0 Register and Timer
Addressing Decode
ROM

Sele~

RAM Select

Read ROM

1

Write RAM

0

Read RAM

0

1

Write DORA

0

0

0

I/O Timer Select

R/W

0

A3

A2

.M

X

X

X

X

X
X

X
X

X

0

0

0

1

X
X

0

X

0

0
0

Read DORA

0

0

1

X

0

Write DDRB

0

0

0

X

0

X

0

1

X

0

0

X

0

0

X
X

0

Read DDRB

0

0

Write Per. Reg. A

0

0

Read Per. Reg. A

0

0

Write Per. Reg. B

0

0

Read Per. Reg. B

0

0

0
0

0

X

o
o
o
o

Write Timer
+IT

0

0

0

0

o

+8T

0

0

0

0

1

+64T

0

0

0

+1024T

0

0

0

Read Timer

0

0

Read Interrupt Flag

0

0

• A3

1 Enables IRO t~ PB7

A3

0 ·Disables IRO to PB7

o
X

1

1

X

o

X

1

...

-

Write Timing Characteristics
Symbol

Characteristic

•
.-

Typ

1

Max

Unit

10

IlS

25

ns

Clock Period

TCYC

Rise & Fall Times

TR,T F

Clock Pulse Width

TC

470

ns

R!W valid before positive transition of clock

TWCW
T
ACW
T
DCW
T
HW

180

ns

180

ns

Address valid before positive transition of clock

- ...

Min

Data Bus valid before negative transition of clock
Data Bus Hold Time

300

ns

10

ns

Peripheral data valid after negative transition
of clock

TCpW

1

IlS

Peripheral data valid after negative transition
of clock driving CMOS (Level; VCC - 30%)

T

2

IlS

Max

Unit

CMOS

Read Timing Characteristics
Characteristic

Symbol

Min

TWCR
T
ACR

180

ns

180

ns

Peripheral data valid before positive transition
of clock

TpCR

300

ns

Data Bus valid after positive transition of clock

TCDR

Data Bus Hold Time

THR

R/W valid before positive transition of clock
Address valid before-positive transition of clock

IRQ (Interval Timer Interrupt) valid before
positive transition of clock

Loading

TIC

Typ

395

ns

10

ns

200

ns

30 pF + 1 TTL load for PAO-PA7, PBO-PB7
130 pF + 1 TTL load for DO-D7

~TIC

--------------~

'-------Write Timing Characteristics

Read Timing Characteristics

PROGRAMMING INSTRUCTIONS
The Rockwell R6530 utilizes computer aided techniques to manufacture and test custom bit patterns. The custom bit pattern and
address information is supplied on mini-floppy diskettes prepared
on the SYSTEM 65, or paper tape, or standard 80-column com·
puter cards in the format described below.

Th~

All addresses and related output patterns must be completely
defined. Mask options should be noted on the ROM order form
and in the title cards.

; 301 101 10 0000
;301:02 10 0010
;30QD3 10 0037
; ~ 01.00

format for the last card in a file IS as follows:

;40000
EXAMPLE:
b%~bSb~7Sbn9b~00bD~CO~ 7D~con9

OSH

~CO~blb~71b~29b~2SbBSb09b~002D

0~b3

2~b~2C~CD~OOOOOaooooooOOOOOOOOOO

010~

•

Title Cards

.

A set of six Title Cards should accompany each data deck. These
cards give our computer programs additional information necessary to accurately produce high density ROMS. These six Title
Cards must contain the following information:
Column
First Card

Information

1-30
31-50
60-72

Second Card
Third Card
(2)

Fourth Card
(2)

Fifth Card
(2)

Customer Name
Customer Part Number
Rockwell Order Number
(Example: R6530XX)
Customer Contact Name,
Customer Contact Phone Number
Pin 17 : IRO/PB7 with Pull·up or IRO/
PB7 without Pull-up.
Pin 18: CSl or PB6,
Pin 19: CS2 or PB5
(Example: Pin 17 : IRO NO PULL-UP,
PIN 18: CS1, PIN 19: PB5)
(1) ROM SEL, RSO : X, CSl : X, CS2 : X
(Example: ROM SEL, CSl : H, RSO: H,
CS2: N)
(1) RAM SEL, RSO : X, CSl : X, CS2: X,
A9: X, A8: X, A7: X, H6: X
(Example: RAM SEL, CSl : L, CS2: N,
RSO : L, A9 : L, A8 : N, A7 : H,
A6: H)

NOTE:
is keypunched as IRO
Sixth Card
(2)

(2)

(1)

Paper Tape Format
Rockwell can accept ROM coding in paper tape prepared using
SYSTEM 65, Cross Assembler or AIM 65 output. Mask optIons
shou'd be noted on the ROM order form. The format for paper
tape is as follows:

-----

~1~OA3A2A1AOD1DOD1DOX3X2X1XOCRLF

1

2

The format for the last record in" file is as follows:

NOTE 1
1. 00: zero bytes of data in this record. This identifies this as the
fInal record in a file.
2. C3C2Cl Co = the total number of records (in hexadecimal) in
this file, including the last record.

rna

(1)

I

110 SEL, RSO: X, CSl : X, CS2 : X,
A9: X, A8: X, A7 : X, A6: X
(Example: I/O SEL, CSl .: L, RSO : L,
CS2 : N, A9 : H, A8 : H, A7 : H,
A6: H)

X:HorLorN
H = +2.4 Volts L: +0.4 Volts N = No Effect
Free Format - Delimiters are commas or blanks

3. The valid record is identified by the starting delimitor (;) and
It!rminated by the check sum (X3X2Xl XO>' All other characters
such as the CR and LF are not processed. The next semi-colon
initiates the next record.

EXAMPLE:
; 18FOOOCA8bOO'tC DOFOF DF9 2120 21 FF 29 2D5F 21b 1 FSF 7fFbS 70b 77000 .. [J

; 18FU 18ES b~ b 12DFD75 1SE snooocn 112F 800 925 1 9802001]9 1 92F 20C90
; 18 F 0]0 a 8 DBO 2 OS 0 81 00 E 12089 _I B 9AC 2 0]0 E 9 0 0 0 F BOb 2 32F a 8 7F b 5 OAA 5
;00000]000]

Data Card Format
The required data card format is generated by the Cross Assembler.
All addresses are coded in hexadecimal form (0 through
FFFFI. All output words' are coded both in binary and octal
forms. Output 8 (OB7) is the MSB, and Output 1 (OBO) is the LSB.

Unless otherwise stated, the field definitions are defined as follows:
1. All Characters (N,A,D,X) are the ASCII characters 0 through
F, each representing a hexadecimal (hex) digit.

The format for all cards in a file, except the last card, is as follows:

2.

; is a record mark indicating the start of a record.

~S2S1S0~N1NO~A3A2A1AOD1DOD1DObX3X2X1XO

3.

Nl NO = the number of bytes of data in this record (in hex).
Each pair of hex characters (01 DO) represents a single byte
in the record.

...-....-...-..
1

2

-

•••

4.

7.

S2S1 So

8.

CR = ASCII character for Carriage return.

9.

LF = ASCII character for line feed.

stored in (A3A2Al AO)
5.

I

- ....

.

-

6.

= the

A3A2A1AO = the hex starting address for the record. A3 represents address bits 15 through 12, etc. The 8·bit byte represented by (0100)1 stored in address A3A2A1AO: (0100)2

hex sequence number for the card record.

+ 1, etc.

(01 DO) = two hex digits representing an 8-bit byte of data.
(01 = high-order 4 binary bits and DO = low-order 4 bits).
A maximum of 18 (hex) or 24 (decimal) bytes of data per

10.

record is permitted.

Mini-Floppy Diskette Format

~ = Space character

X3X2Xl Xo = record check sum. This is the hex sum of all

Rockwell can accept ROM coding on mini-floppy diskettes pre-

characters in the record, excluding the record mark and the

pared using the SYSTEM 65 Assembler output. The format is
Similar to the Paper Tape format shown in the preceding para·

check sum characters. To generate the check sum, each byte
of data (represented by two ASCII characters), is treated as
8 binary bits. The binary sum of these 8-bit bytes is trun·
cated to 16 binary bits (4 hex digits) and is then represented
in the record as four ASCII characters (X3X2Xl XOl.

graph. Title card information should be recorded using the file
name "TITLE." Data information should be recorded using the
file name "DATA." Mask options should be noted on the ROM
Order form.

VSS
PAO
(/12
RSO
A9
AS
A7
A6

PAl
PA2
PA3
PA4
PA5
PA6
PA7
DO
01
02
03
04
05
06
07
PBO
PBl
PB2
PB3
PB4

R/W

A5
A4
A3
A2
Al
AO
RES
iFi"Q/PB7
eSl/PB6
eS2/PB5
vee
~ymhollzatlon

IS

In

normal Orientation

Packaging Diagram

Pin Configuration

•
-

-

...

-

SPECIFICATIONS
Maximum Ratings
Rating

Symbol

Supply Voltage

I
-

...

--

Voltage

Unit

-0_3 to +7_0

VCC

V

Input/Output Voltage

-0_3 to +7_0

V

Operating Temperature Range

o to

°c

70

°c

-55 to +150

Storage Temperature Range

Ali inputs contain protection circuitry to prevent damage due to high static charges_ Care should be exercised to prevent unnecessary application of voltage outside the specification range_

Electrical Characteristics
0

(VCC=5.0%, VSs=ov, T A =25 C)
Characteristic

Symbol

Input High Voltage

V

Input Low Voltage

V

Input Leakage Current; V
AO-A9, RS, R/W,

IN

= VSS + 5V

IL

SS

VSS - 0.3
1.0

liN

Max

Typ

+2.4

Unit

VCC

V

VSS + 0.4

V

2_5

P.A

~10.0

P.A

REs, 02, PBS', PB5'

Input Leakage Current for High Impedance State
(Three State); V

IH

Min
V

IN

I

±1.0

TSI

= O.4V to 2.4V; 00-07

Input High Current; V IN = 2.4V

IIH

-100.

-300.

IlA

PAO-PA7, PBO-PB7
Input Low Current; V

IN

= 0.4V

-1.0

IlL

-l_S

MA

PAO-PA7, PBO-PB7
Output High Voltage
VCC

= MIN,

V

V

OH

I

" -100 P.A (PAO-PA7, PBO-PB7, 00-07)
LOAO
I LOAD "-3 MA (PAO-PBO)

VSS + 2.4
VSS + 1_5

Output Low Voltage
VCC = MIN, 'LOAD';; 1.S MA
Output High Current (Sourcing);

Clock Input Capacitance

V

IOH

VOH ;;. 2.4V (PAO-PA7, PBO-PB7, 00-07)
;;. 1.5V Available for other than TTL
(Oarlingtons) (PBO, PB7)
Output Low Current (Sinking); VOL" 0_4V (PAO-PA 7)
(PBO-PB7)

VSS + 0,4

VOL

-100
-3.0

IOL

-1000
-5_0

P.A
MA

1.S

MA

CClk

30

pF

Input Capacitance

C

10

pF

Output Capacitance

C

10

pF

Power Dissipation

Po

1000

MW

'When programmed as address pins
All values are D_C. readings

IN
OUT
500

PART NUMBER

DOCUMENT NO. 29000052
REV. 3, NOVEMBER 1979

'1'

R6531

R6500

Rockwell

Microcomp~ter

System

DATA SHEET

ROM-RAM-I/O-COUNTER (RRIOC)
SYSTEM ABSTRACT

FEATURES

The ROM-RAM-I/O Counter (RRIOC), Part Number Fl6531 ,
further enhances the cost-effectivity of the R6500 NMOS 8-bit
microcomputer system by providing a powerful, flexible twochip minimum system option_ Produced with N-channel depletion load, silicon gate technology, the R6500 system employs
advanced architecture, including 13 instruction addressing modes
to achieve third generation performance speeds and smaller chips,
the key to lower hardware and design costs. Included in the
R6500 system are 10 software-compatible microprocessor (CPU)
options, a growing number of memory and I/O devices, a very
efficient, low-cost SYSTEM 65 development aid and complete
documentation.

DESCRIPTION
The R6531 is primarily designed to provide innovative Equipment
Designers with a wide span of two-chip minimum systems in
combination with the R6500 family of 10 CPUs. It can also be
combined in a variety of multi-chip system configurations with
other R6531 :s, ROMs, RAMs and other I/O devices.
There are two R6531 versions: a 40-pin dual-in-line package;
another with expanded I/O in a compact 52-pin quad-in-line
package - see Table 1. Both versions contain a 2048 x 8 maskprogrammable ROM, a 128 x 8 static RAM, a software programmable multi-mode counter, an 8-bit serial data channel, and 15
bidirectional data lines (two ports) with a handshake control
mode and four interrupt inputs. The 52-pin version has an 8-bit
output port and a 4-bit input port for a total of 27 110 lines.
Several mask options are available tp provide a RAM standby
power pin and chip selects for multi-chip systems - see Figure 1.
Prototyping circuits are available in both the 40- and 52-pin packages, and in 1- and 2-MHz versions. They are offered as part
numbers R6531-098 and R6531-098A for the 40-pin part, and as
part numbers R6531-099 and R6531-099A for the 52-pin part.
PA7

PAO

PB6

•
•
•

•
•
•
•
•
•
•
•

2048 x 8 mask programmable ROM
128 x 8 static RAM
16-bit multi-mode counter/latch
interval timer (one shot or free running)
pulse generator (one shot or free running)
event counter
external trigger
8-bit serial channel
TTL compatible I/O, drive oneTTL load
15 bi(jirectional I/O lines (2 ports - 40 pin package)
Expansion 8-bit output port· and 4-bit input port (52 pin
package)
I/O handshake control
Four edge sensitive interrupt inputs
2 MHz or 1 MHz operation
Single +5V power supply

Table 1 Ordering Information
Order Number: R6531

[

Temperature Range:
No suffix - OOC to·+70 0 C
0
0
E = -40 C to +85 C
(Industrial)
Package:
C = 40-Pin DIP, Ceramic
P = 40-Pin DIP, Plastic
Q = 52-Pin QUIP, Plastic
Frequency Range:
No suffix = 1 MHz
A = 2 MHz

NOTE:

PBO

Pe7

_2

Contact your local Rockwell representative for availability.
PeO

cS2

POl

POO

RM

R6531 Block Diagram

@ Rockwell InternatIonal Corporatoon 1979
All R,ghts Reserved
Printed in U.S.A

Specifications subject to
change without notic.

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTl
PB6/i'RQ

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTI

•
-

...

--

PB3/S010

Riw
pe6
PB2/SCLK

PC7

PB1/CA2

RES

PBO/CAl

PB3/S010

07

Riw

06

PA7

PB2/SCLK

05

PA6

PB6/1-ml

PB1/CA2

RTI

PBO/CAl

(CS3) P02

PC5

PA5

AS

PA4
PC4

07

PA7

A7

06

PA6

02

05

A5

PA5

POl

A6

AS

PA4

04

PC3
PA3

A7

A5

03

02

A6

POO

PA2

04

PA3

02

PAl
PAO

PA2

01

PAl

DO

01

PAO

AO

A4

DO

A2

All

PC2

AO

A4

PCO

PCl

All

Al

A9

Al

A9

A3

A10

A3

VCC

VRR

VCC

03
02

A10

A2

52·Pin Configuration
RG5310. VRR OPtion

40· Pin Configuration
RG531. PBG OPtion

VSS
(CS2) PB4/CNTO
(CSll PB5/CNTI
PB6/i'R'O

PB3/S010
R/W
PC6
PB2/SCLK
PB1/CA2
PBO/CAl

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTI

PB3/S010

07

PC5

Riw

06

PA7

05

PA6

PB2/SCLK

RE'S

PB1/CA2

07

PBO/CAl

06

PA7

AS

PC4

05

PA6

A7

A5

AS

PA5

02

A6

P03
(CS3) P02

PA5
PA4

A7

PA4

POl

PC3

02

A5

04

PA3

04

A6

03

PA2

03

PA3

POO

PAl

02

PA2

02

PAO

01

PAl

01

A2

DO

PAO

DO

A4

AO

A2

AO

PC2

All

A4

All

PCl

A9

Al

PCO

Al

A10

A3

A9

A3

VCC

A10

VCC

VRR

52·Pin Configuration
RG5310. P03 Option

4O·Pin Configuration
RG531. VRR Option

Figure 1. R6531 Pin Configuration Options

INTERFACE SIGNALS
RESET (RES)
This active low signal is used to initialize the R6531. It clears all
internal registers (except the counter and serial registers) to logic
zero. This action places all bidirectional I/O lines in the input state
and the Port C outputs in the high state. The timer, shift register, and
interrupts are disabled. The RES signal must be low for at least four
clock periods when reset is required.

ADDRESS BUS (AO-A11) AND CHIP
SELECTS (CS1-CS3)
Memory and register selection is accomplished using the 12 address
lines and, in multiple device systems, also using one or more of the
three Chip Select mask options. When PB4, PB5, or PD2 are chosen
as chip selects, they cannot be used as peripheral I/O pins.

DATA BUS (DO·D7)
The R6531 has eight data bus lines, which allow data to be transferred
to or from the microprocessor. The output buffers remain in the offstate except when the R6531 is selected for a read operation.

Chip
Selects
RS531
Function

Address Inputs (AO-A11)

CS3 CS2 CS1

1110191817IsI5[41312[1[0

X

ROM

X

RAM

V V V

X

Z Z Z

1/0

2K ROM Decode

X

V V Iv IV IV I
Z z IZ IZ IZ IZ

128 RAM Decode

IZ IZ

11/0 Decode

The X, V, and Z bits may be selected as high, low or no effect.
The chip select pins are also discrete 110 pins PB5, PB4, and PD2. The
pins are independent of each other in that anyone may be used as a
chip select. The user specifies as mask options which pins are to be
used as I/O and which as chip selects.

ROM - 2K BYTES (16K BITS)
The 16K ROM is a 2048 x 8 bit configuration. An address on lines
AO-Al0 uniquely selects one byte of ROM. Additionally, address
line All and the chip selects are required to select the ROM function
on a given chip. In a system with multiple R6531's, the CS1, CS2,
and CS3 mask options allow up to seven devices with 14K bytes of
ROM without the need for external decoding.

READ/WRITE (RiWI

RAM - 128 BYTES (1024 BITS)

The RiW signal is supplied by the microprocessor and is used to control
the transfer of data to and from the microprocessor and the R6531. A
high on the RiW pin allows the processor to read (with proper addressing) the data supplied by the R6531. A Iowan the R/W pin allows a
write (with proper addressing) to the R6531.

The 128 ~ 8 static RAM of a given R6531 is addressed by lines AO-A6.
Additionally, address lines 'A 7-A 11 and chip selects CS1, CS2, and
CS3 provide selection of the RAM section of the device as well as the
device itself when additional RAM devices or R6531's are in the system.

PERIPHERAL DATA PORTS (PAO-PA7, PBO-PB6,
PCO-PC7, PDO-PD3)
Both versions of the R6531 have 15 pins available for peripheral 1/0
operations. Each pin is software programmable to act as an input or
an output. The pins are grouped into an 8-bit port, PAO-PA7, and a
7·bit port, PBO-PB6. The lines of the PB port may serve other functions. Ports PA and PB have associated data direction registers.
The expanded 1/0 of the 52-pin version provides an 8·bit output only
port, PCO·PC7, and a 4-bit input only port, PDO-PD3. PD2 and PD3
may be assigned other functions as described herein.
The outputs are pushlpull type drivers capable of driving a single TTL
load. When inputs are selected the drivers float. If PB6 is programmed
as the IRO request output, the line is driven low and requires an external pull-up, thus allowing the wire OR-ing of IRO from other devices.

RAM RETENTION VOLTAGE (VRR)
A separate pin for a power supply for the read/write memory is available as a mask option. This allows the retention of RAM data by using
a battery back-up for the RAM only. Pin PB6 in the 40-pin version
or PD3 in the 52-pin version is mask programmable as the VRR pin.
Address line Al0 must be held in the logic state which deselects RAM
(user-defined) in order to protect the RAM data when VCC falls below
the specified level or is turned off.

INTERNAL ORGANIZATION
The R6531 is divided into three basic functions: ROM, RAM, and I/O.
The selection of anyone of these three is accomplished by Issuing
the appropriate address information on the address bus when the chip

R6531 40 PIN PROTOTYPING CIRCUIT
Prototyping circuits R6531·098 (1 MHz) and R6531-098A (2 MH7)
are packaged i~ a 40-pin dual in-line package that has the same pinouts
as the 40-pin R6531 with PB6 option. In this prototyping circuit,
the ROM is disabled and there is no VRR option.
Access codes for this prototyping circuit are shown in the table below.
Chip
R6531-098
Function

Addressing of the R6531 offers many variations to the user for system
configuration flexibility.
Combination with other R6531's, ROMs,
RAMs or 1/0 devices is possible without need for external address
decoding. Each of the three basic functions on the device has its own
decode mask for unique selection.
The specific address ranges and chip selects are defined by the user
and are dependent on the number of chips in the system. The programmed options to be fixed by masking are:

CS2 CS1

RAM

N

N
N

1/0

N

11

10

9

8

7

6151413121110

L
L

L
H

L
H

N
H

L
L

L I L I L 1110 Decode

128 R AM Decode

In the above table, N means No Effect, H means High (2.0 volts or
greater! and L means Low (0.8 volt or less).

R6531 52-PIN PROTOTYPING CIRCUIT
Prototyping circuits R6531-099 (1 MHz) and R6531·099A (2 MHz)
are packaged in the 52-pin quad in-line package, With VRR option.
PD2 is used as a chip select (CS3), and PB4 and PB5 are available as
1/0 lines.
Access codes for the prototyping circuit are shown

R6531-099
Function

is selected.

ADDRESSING

Address Inputs (AO - A 11)

Selects

Chip
Selects

In

the table below.

Address Inputs (AO·A 11)

CS3 CS2 CSl

11 1019181716151413/2/110
H
2K ROM Decode

ROM

H

N

N

RAM

L

N

N

L

L I LIN ILl

I/O

L

N

N

L

H

128 RAM Decode

I HI H I L I L I L I L I

I/O Decode

The 128 words of RAM have been mapped into the first half of both
Page 0 and Page 1, to accomodate zero page addressing and stack
operations. The full I/O capabilities described for the R6531 are available in the prototyping circuit, except that I/O lines PD2 and PD3
are dedicated to the VRR and CS3 mask options.

•

- ...
--

INPUT/OUTPUT
The input/output section is comprised of the data ports, direction registers, counter and associated latches, control registers, and interrupt
registers. These I/O functions are all accessible by the R6502 CPU's
instruction set using address bits AO·A3 for the specific function of
the device. Address bits A4-A 11 and CS1, CS2, and CS3 additionally
may be decodQd to select a given R6531 device in a multichip system.
The addresses of the 15 internal peripheral registers are:
A3

I

- ...

--

A2

AD

Al

PBO. 1 CONTROL

00

0

0

Port A

0

0

0

Port B

0

0

Port C (write only)

0

0

Port 0 (read only)

1

o
1

0

Read Lower Counter/Write Lower
Latch

0

0

Read Upper Counter/Write Upper
Latch and Download

Write Upper Latch
0

0

0

Interrupt Enable Register
Auxiliary Control Register

0

Peripheral Control Register

0

• Data Direction Register - Port A

0

• Data Direction Register - Port B

0
• Write Only

CONTROL REGISTERS
Two control registers, Peripheral Control and Auxiliary Control, are
provided for software selection of various I/O functions. The Peripheral Control Register is primarily associated with Port B functions and
the Auxiliary Control Register is associated with the counter and serial
data functions which also affect Port B. The register bit assig"ments
are:

I
A;R

SERIAL CONTROL
A;R

A;R

L,.....J

I

COUNTER CONTROL

I

I I IA~R I I
AiR

""

Static 1/0

rna Request QUIP

Spare (Unused)

Peripheral Control Register (PCR)

Two registers are provided for interrupt control. Corresponding b
in the enable and flag registers are logically ANDed to set the Interru
Request Pending flag. If the pending flag is set and PB6 is selected
an IRQ Request Output, then PB6 will be set low to request the R651
CPU to service IRQ.
The interrupt enable bits are set or reset by writing into the Interrul
Enable Register. The interrupt flag bits IF RO-I F R6 can be clean
directly by writing a byte to the flag register which has l's in tho
bit positions to be cleared.
IFR4 and IFRS may also be cleared by reading or writing the Port
or Serial Data Registers respectively. IF R6 may also be cleared t
reading the lower counter with I/O address hex 4 or writing the upp
latch with I/O addresses h'ex 5 or 7.
These registers and their bit assignments are:

Interrupt Enable Register

I I A~R I

'Z

INTERRUPT ENABLE AND FLAG REGISTERS

Interrupt Flag Register

0

0

Static 1/0
Pos Edge Detect

Serial Data Register

0

0

E

Write Lower Latch

0
0

PA Handshake
Neg Edge Detec

' - - - - - - - - PBS CONTROL

0

0

...

o ,.,

L....._ _ _ _ _ _ _ _ _ _ _

0

:II

' - - - - - - PB2,3CONTROL

Register

0

Static 1/0

01
lX

A;R

AgR

L

COUNTER SOURCE SELECTION
Counter Off

01

*'

External Event (PBS)

10
11

•
,.

Phase 2
Phase 2. Ext Trigger low

PULSE GENERATION CONTROL

o ""

Pulse Output Off

1

Pulse Output on (PB4)

,.

FREE RUN CONTROL

o ,.

One Shot

1

Free Run

,.

SERIAL CLOCK SOURCE

00

,.

01

..

SerialOff
External Clock {PB21

, X

'"

Phase 2 Clock (PB2 Outl

SERIAL OATA OIRECTION

o ,.
1

:II

Serial In (PB31
Serial Out (PB31

Spare (Unu58dl

Auxiliary Control Register (ACR)

PERIPHERAL DATA PORTS
Each line of the B-bit data Port A may be individually selected as an
input or output. Associated with the port is Data Direction Register Port A (DORA). Each line of the 7-bit date Port B may be individually
selected as an input or an output. This port also has a Data Direction
Register (DDRB). The two data direction registers (A and B) control
the direction of the data into and out of the peripheral pins. A "1"
written into the Data Direction Register sets up the corresponding
peripheral pin as an output. Therefore, anything written into the data
register will appear on that corresponding peripheral pin. A "0" written
into the DDR inhibits the output buffer from transmitting data from
the data register. For example, a "1" loaded into DORA, position 3,
sets up peripheral pin PA3 as an output. If a "0" had been loaded,
PA3 would be configured as an input and would be in a float state.
Note that when lines in the PB port are used alternately as control
lines for other on-chip functions, Direction Register B must also be
loaded to set up the proper direction the Control Registers have
no effect on data direction.

Mode 2 -

Interval Timer - counts 1/>2 system clock pulses.

Mode 3 -

External Trigger - counts 02 system clock pulses starting
with a negative transition on PB5.

Mode Modifier A - Pulse Generation Control - causes the output level
on PB4 to switch low each time the counter is loaded using
I/O address hex. 5. At counter overflow, PB4 switches high.
If in the free run mode, PB4 continues to toggle at each
subsequent counter overflow; otherwise there are no further transitions until the counter is reactivated by the
software.
Mode Modifier B - Free Run Control - causes the full 16·bit latch to
be downloaded to the counter, continues to count, and sets
the counter overflow flag bit every time the counter overflows. Otherwise the counter is a one shot mode in which
the counter overflow flag is set one time only until the
counter is reactivated by the software.

The B-bit data Port C is an output only port. The 4-bit data Port 0
is an input only port.
For those lines being used as outputs, the data registers are used to
latch data from the Data Bus during a Write operation so the peripheral device can read the data supplied by the microprocessor.
For the lines being used as inputs, the microprocessor is reading the
peripheral data pins. For the peripheral data pins which are pro·
grammed as outputs the microprocessor will read the corresponding
data bits of the Output data.

EDGE DETECT LOGIC
Operating in parallel with the I/O operation of PBO·PB3 is edge detect
logic that is enabled by Peripheral Control Register bits 1 and 2. PCR1
enables logic that upon detection of a negative edge on PBO or PBl
will set a corresponding flag in the Interrupt Flag Register. PCR2
enables logic that upon detection of a positive edge on PB2 or PB3
will set corresponding flags in the l:1terrupt Flag Register. If corresponding bits are set in the Interrupt Enable Register, then the Interrupt Request Pending flag will be set.

MULTI-MODE COUNTER/LATCH
The R6531 contains a 16-bit counter with an associated 16-bit latch
whose modes are software selectable by setting appropriate bits in the
Auxiliary Control Register. The latch holds the counter preset value
and all 16 bits download to the counter simultaneously lIpon command
(I/O address hex 5) of the software or automatically in free run modes
upon overflow of the counter. The counter is a decrementing counter
and causes the setting of a flag in the Interrupt Flag Register when it
overflows. This interrupt flag, bit 6, is logically ANDed with a corresponding counter overflow interrupt enabled bit to set the Interrupt
Request Pending flag. The Auxiliary Control Register is used to set
four basic modes which specify the source of the count information,
and to select two mode modifiers that apply equally to the three active
modes.
Mode 0 -

Counter Off

Mode 1 -

Event Counter - counts external event inputs (negative
transitions) at PB5

SERIAL DATA CHANNEL
The R6531 has an B-bit serial channel. PB2 and PB3 are software
selectable as the serial clock (SCLK) and serial data (SOlO) lines
respectively.
The software sets Auxiliary Control Register bits 4 and 5 to enable
the serial channel and to specify the source of the shift clock. Selection of the internal clock will shift data at one half the system 02
clock rate. If the external clock is used, data may be shifted at any
rate up to one half the system 02 clock rate. In the external clock
mode, the counter may be operated in the free run pulse generator
mode using the CNTO line externally connected to the SCLK line to
provide the desired shift rate.
Auxiliary Control Register bit 6 sets the serial data direction. Data are
shifted in or out, most significant bit first, under control of the shift
clock.
In the external clock mode, the ~ompletion of eight shifts of the serial
register will set bit 5 of the interrupt flag register. If the corresponding
bit of the Interrupt Enable Register is also set an Interrupt Request
Pending flag will be set.

HANDSHAKE OPERATIONS
PBO and PB1 may be used as handshake control lines for date transmissions over Port PA; see PCR definition. PBO is a control input,
PB 1 is a control output. PB 1 switches low on a read or write to Port
PA, and switches high in response to a negative transition on PBO.
IFR4 in the Flag Register is set by a negative transition on PBO, and
cleared by a Read or Write to Port PA; see Handshake Timing Diagram
for timing details.

•

- '.-

I

10° MAX,

40
21_l_-~
DDT DR NDTcOtJo600
MAX~'5.87) ~
TO LOCATE

PIN NO 1

(15.24 M\o1)

-

(1511)

040

~~"""'~-r

0.595

•

!

---1_~'55MA~

L J1[0.,.90
~m - T ,
~~TYP~.t. ~ 1[~
o

13.93 MM)

2.020 MAX
151.30 MM)

•

- ...
-

-

MAX
(482 MM)

~

t

=-=h-

J

=r-

(101) 0.040

0.310 MAX

IJ

.'::'~

(2.54 MM)

__ ~

10.551 0.022 TYP
(0451 0,018

(025 MM)

1910

(48.51 MM)

1'""'8'90

(48.00 MMI

-

19 EQUAL SPACES

O.lOO .;'.

. .

DATA SHEET

. ~,

•

- ...
-

RAM, 1/0, INTERVAL TIMER DEVICE (RIOT)
SYSTEM ABSTRACT

FEATURES

The 8-1>it R6500 microcomputer system is produced with NChannel, Silicon-Gate technology. Its performance speeds are
enhanced by advanced system architecture which enables multiple
addressing. Its innovative architecture results in smaller chips the semiconductor threshold to cost-effectivity. System costeffectivity is further enhanced by providinga family of 10 softwarecompatible microprocessor (CPU) devices. Rockwell also provides memory and I/O devices that further enhance the costeffectivity of the R6500 microcomputer system' .•. as well as
low-cost design aids and documentation.

•

DESCRIPTION
The R6532 is designed to operate in conjunction with the R6500
Microprocessor Family. It is comprised of a 128 x 8 static RAM,
two software controlled S bit bidirectional data ports allowing
direct interfacing between the microcomputer and peripheral
devices, a software programmable interval timer with interrupt,
capable of timing in various intervals from 1 to 262,144 clock
periods, and a programmable edge detect circuit.

PAO

DATA
DIRECTION
REGISTER
A

8 bit bidirectional Data Boos for direct communication with the
microprocessor

•

128 x 8 static RAM

•

Two 8 bit bidirectional data ports for interface to peripherals

•

Two programmable Data Direction Registers

•

Programmable Interval Timer Interrupt

•

TTL & CMOS compatible peripheral lines

•

Peripheral pins with Direct Transistor Drive Capability

•

High Impedance Three-State Data Bus

•

Programmable edge-sensitive interrul>t

-

........

p

Ordering Information
Order

~
R6532P
R6532C

PA7

OUTPUT
REGISTER
A

-

Package
Type

Temperature
RanI!!

Plastic
Ceramic

OOC to +70 0 C
0
OOC to +70 C

PB7

PBO

INTERVAL
TIMER

PERIPHERAL
DATA BUFFER

OUTPUT
REGISTER

B

B

:a

.(5:
-to

DATA
BUS
BUFFER

DO'

ADDRESS
DECODER

07

AO

CHIP
SELECT

R/W

128 X 8
RAM

INTERRUPT
CONTROL

DATA
DIRECTION
REGISTER
B

A6

R6532 Block Diagram

<5) Rockwell

International CorPOration 1977
All Rights Re..rved
pfinted in U.S.A.

Specificatlonl lubJect to
change without notice

I

-.

--

INTERFACE SIGNAL DESCRIPTION

INTERNAL ORGANIZATION

Reset (RES)

The R6532 is divided into four basic sections, RAM, I/O, TIMER,
and Interrupt Control. The RAM interfaces directly with the
microprocessor through the system data bus and address lines.
The I/O section consists of two 8-bit halves. Each half contains a
Data Direction Register (DDR) and an Output Register.

During system initialization a logic "0" on the RES input will
cause a zeroing of all four I/O registers. This in turn will cause
all I/O buses to act as inputs thus protecting external components
from possible damage and erroneous data while the system is being
configured under software control. The Data Bus Buffers are put
into an OF F -ST ATE during Reset. Interrupt capability is disabled with the RES signal. The RES signal must be held low for
at least two clock periods when reset is required_
~.

Read/Write (R/W)
The R/W signal is suppllerJ hy the microprocessor and IS used to
control the transfer of data to and from the microprocessor
and the R6532. A high on the R/W pin allows the processor
to read (with proper addressing) the data supplied by the R6532.
A low on the H/W pin allows a wri!e (with proper addressing) to
the R6532.

Interrupt Request (I Ra)
The I RO pin is an interrupt pin from the interrupt control logic.
The pin will be normally high with a low indicating an interrupt
from the R6532_ An external 3K pull-up resistor is required. The
I RO pin may be activated by a transition on PA 7 or timeout of
the interval timer.

Data Bus (00-07)
The R6532 has eight bidirectional data pillS (D0-D7). These
pins connect to the system's data lines and allow transfer of
data to and from the microprocessor array. The output buffers
remain in the off state except when the R6532 is selected for a
Read operation.

Peripheral Data Ports (PAO-PA7, PBO-PB7)
The R6532 has 16 pins available for peripheral I/O operations.
Each pin is individually software programmable to act as either
an input or an output. The 16 pins are divided into 2 8-bit ports,
PAO-PA7 and PBO-PB7. PA7 also has other uses which are discussed in later sections_ The pins are set up as an input by writing
a "0" into the corresponding bit of the data direction register.
A "1" into the data direction register will cause its corresponding
bit to be an output. When in the input mode, the peripheral output buffers are in the "'" state and the internal pull-up device
acts as less than one TTL load to the peripheral d"t~ lines. On a
Read operation, the microprocessor unit reads the peripheral
pin. When the peripheral device gets information from the R6532
it receives data stored in the output register. The microprocessor
will read correct information if the peripheral lines are greater
than 2.0 volts for a "1" and less than 0.8 volt for a "0" as the
peripheral pins are all TTL compatihle. Pins PBO-PB7 are also
capable of sourcing 3 ma at 1.5V, thus making them capable of
Darlington drive.

Address Lines (AO-A6)
There are 7 address pins_ In addition to these 7, there is the RAM
SE LECT (RS) pin.
The pins AO-A6 and RAM SELECT are
31ways used as addressing pins_ There are two additional pins
which are used as CHIP SELECTS. The'l are pins CS, and CS2_

RAM - 128 Bytes (1024 Bits)
The 128 x 8 Read/Write memory acts as a conventional static
RAM_ Data can be written into the RAM from the microprocessor
by selecting the chip (CS1 ~ 1, CS2 ~ 0) and by setting As to a
logic 0 (O.4VI. Address lines AD through A6 are th' used to
select the desired byte of storage_

Internal Peripheral Registers
The Peripheral A I/O port consist. of eight lines which can be
individually programmed to act as either an input or an output. A
logic zero in a bit of the Data Direction Register (DDRA) causes
the corresponding line of the PA port to act as an inout_ A logic
one causes the corresponding PA line to act as an output. The
voltage on any line programmed to be an output is determined by
the corresponding bit in the Output Register (ORAL
Data is read directly from the PA pins during any read operation_
For any output pin, the data transferred into the processor will
be the same as that contained in the Output Register if the voltage
on the pin is allowed to go to 2.4V for a logic one. Note that for
input lines, the processor can write into the corresponding bit of
the Output Register_ This will not affect the polarity on the pin
until the corresponding bit of DDRA is set to a logic one to allow
the peripheral pin to act as an output_
In addition to acting as a peripheral I/O line, the PA 7 line can be
used as an edge-detecting input_ In this mode, an active transition
will set the internal interrupt fl<:g (bit 6 of the Interrupt Flag register)_ Setting the interrupt flag will cause iRO output to go low
if the PA 7 interrupt has been enabled_
Control of the PA7 edge detecting mode is accomplished by writing to one of four addresses_ In this operation, AD controls the
polarity of the active transition and A' acts to enable or disable
interrupting of the processor_ The data which is placed on the
Data Bus during this operation is discarded and has no effect on
the control of PA7_
Setting of the PA7 interrupt flag will occur on an active transition
even if the pin is being used as a normal input or as a peripheral
control output. The flag will also be set by an active transition
if interrupting from PA7 is disabled_ The reset Signal (RES) will
disable the PA7 interrupt and will set the active transition to negative (high to lowl. During the system initialization routine, it is
possible to set the interrupt flag by a negative transition_ It may
also be set by changing the polarity of the active interrupt. It is
therefore recommended that the interrupt flag be cleared before
enabling interruptin!l from PA7_
Clearing of the PA7 Interrupt Flag occurs when the micorprocessor reads the Interrupt Flag Register.
The operation of the Peripheral B Input/Output port is exactly
the same as the normal I/O operation of the Peripheral A port.
The eight lines can each be programmed to act as either an input
or as an output by placing a 0 or a 1 into the Data Direction register (DDRB). In the output mode, the voltage on a peripheral
pin is controlled by the Output Register (ORB).

The primary difference between the PA and the PB ports is in the

When the timer has counted thru 0 0 0 0 0 0 0 0 on the next

operation of the output buffers which drive these pins.

The PB

count time an interrupt will 'occur and the counter will read

output buffers are push-pull devices which are capable of sourcing

1 1 1 1 1 1 1 1. After interrupt, the timer register decrements
at a divide by "1" rate of the system clock. If after interrupt, the

3 ma at 1.5V.

This allows these pins to directly drive transistor

on a "Read PB" operation, sufficient logic is provided in the chip

timer is read and a '/alue of 1 1 1 0 0 1 0 0 is read, the time
since interrupt is 27T. The value read is in two's complement,

to allow the microprocessor to read the Output Register instead
of reading the peripheral pin as on the PA port.

but remember that interrupt occurred on count number one.
Therefore, we must subtract 1.

switches.

To assure that the microprocessor will read proper data

Interval Timer
The Timer section of the R6532 contains three basic parts:

pre-

liminary divide down register, programmable 8-bit register and
interrupt logic.

Value read

1 1 1 0 0 1 0 0

Complement
ADD 1

o0
o0

SUB 1

complement of register
o 0 0 1 1 0 1 1 = 27

The interval timer can be programmed to count up to 255 time
intervals.

Each time interval can be either 1T, 8T, 64T or 1024T

0 1 1 0 1 1
0 1 1 1 0 0 = 28 Equals two's

increments, where T is the system clock period. When a full count
is reached, an interrupt flag is set to a logic "1 ". After the interrupt flag is set the internal clock begins counting down to a maximum of -255T. Thus, after the interrupt flag is set, a Read of the

Thus, to arrive at the total elapsed time, merely do a two's com-

timer will tell how long since the flag was set up to a maximum

plement add to the original time written into the timer. Again,
assume time written as 0 0 1 1 0 1 0 0 (=52). With a divide

of 255T.

by 8, total time to interrupt is (52 x 8)

The 8-bit system Data Bus is used to transfer data to and from the

time would be 416T + 27T

Interval Timer. If a count of 52 time intervals were to be counted,

rupt is reset.

However, the reading of the timer at the same time

the interrupt occurs will not reset the interrupt flag. When the
interrupt flags are read (07 for the timer, 06 for the edge detect)
data bus lines 00-05 go to O.

A3 controls the interrupt capability of PB7, i.e., A3 = 1 enables
IRO, A3 = 0 disables IRO. When the timer is read prior to the
interrupt flag being set, the number of time intervals remaining
will be read, i.e., 51,50,49, etc.

When reading the timer after an interrupt, A3 should be low so as
to disable the IRO pin. This is done so as to avoid future interrupts
until after another Write timer. operation.

A3

AO

A1

INTERRUPT

DIVIDE

CONTROL

DOWN

04

06

= 417T. Total elapsed

After the interrupt, whenever the timer is written or read the inter-

At the same time that data is being written to the Interval Timer,
the counting intervals of 1,8,64, 1 024T are decoded from address
lines AO and A 1. During a Read or Write operation address line

07

+1

443T, assuming the value read after

interrupt was 1 1 1 0 0 1 0 O.

the pattern 0 0 1 1 0 1 0 0 would be put on the Data Bus and
written into the Interval Time register.

R/W

=

Q2

02 DO

Basic Elements of Interval Timer

~~~TNETN\~

2
CSl

CS2
AS
R/W
RES

00
01
02
03
04
05
06
07
iRQ
PBO
PBl
PB2
PB3

symbolization IS in normal orientation

Packaging Diagram

o

10° MAX

0.600 MAX

1

o

o
o

NOTE: For all operations CS1 = 1, CS2 = 0_

tJl.-.-L

PIN N O . 1 .

o

A3 = 1, enable timer interrupt
A3 = 0, disable timer interrupt

enable interrupt from PA7
disable interrupt from PA7
positive edge detect IPA 7)
negative edge detect IPA 7)

I
-

o

Write Edge Detect Control

A1
A1
AO
AO

1

0

R/W = 1 to read, 0 to write

Pin Configuration

...
-

SPECIFICATIONS
Maximum Ratings
Rating

•
-

...

--

Symbol

Voltage

Unit

Supply Voltage

VCC

-0_3 to +7_0

Input/Output Voltage

V

-0_3 to +7_0

V

Operating Temperature Range

TOp

o to 70

°c

Storage Temperature Range

T

IN

V

°c

-55 to +150

STG

All inputs contain protection circuitry to prevent damage due to high static charges_ Care should be exercised to prevent unnecessary application of voltage outside the specification range_

Electrical Characteristics
(VCC;5.0%,

vss;ov, T A ;25 0 CI
Characteristic

Symbol

Input High Voltage

V

Input Low Voltage

V

Input Leakage

Cur~;

~

5V
IN
SL
AD·A6, RS, R/W, RES, 1P2, CS1, CS2

liN

Input Leakage Current for High Impedance State

I

(Three State); V

IN

V

V

IH
IL

Min
V

SS

VSS - 0.3
1.0

tl.0

TSI

Max

Typ

+2.4

Unit

VCC

v

VSS + 0.4

V

2.5

!10_0

j.lA

-1.6

MA

; O.4V to 2.4V; 00-07

Input High Current; V

IN

; 2_4V

IIH

-100_

-300_

PAO-PA7, PBO-PB7
Input Low Current; V

IN

; O.4V

-1.0

IlL

PAO-PA7, PBO-PB7

- - . - . - - - - - . - - - - - ._--- -_._-----_. ---- ..Output High Voltage
VCC = MIN, I
I

LOAO
LOAO

V

V

OH

';;; -100 j.lA (PAO-PA7, PBO-PB7, 00-07)

VSS + 2.4

";-3 MA (PBO-PB7)

VSS + 1.5

Output Low Voltage
VCC = MIN, I

LOAO

,,1_6 MA (00-07)

Output High Current (Sourcing);

Clock Input Capacitance

V

IOH

VOH ... 2_4V (PAO-PA7, PBO-PB7, 00-07)
... 1,5V Available for other than TTL
(Darlingtons) (PBO-PB7)
Output Low Current (Sinking); VOL" 0.4V (PAO-PA7)
(PBO-PB7)

VSS + 0_4

VOL

-laO
-3.0

IOL

-1000
-5_0

j.lA
MA

1_6

MA

CClk

30

pF

CIN

10

pF

Output Capacitance

C

10

pF

Power Dissipation

Po

1000

mW

Input Capacitance

All values are D_C, readings

OUT
500

AIM 65
MICRO·
COMPUTER

I

I

RockwellAIM65•••gilleG
System Applications Connector - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ __
44-pin connector lets
connect peripherals interfaced with AIM
65's versati!e 1;0
for example, one or two cassette
tape recorders, a
current
switches
and
TTL-!evel "''''''C''''''''',
and sensors using
and contra! functions Via built-in
and more,

•

120-LinefMin. 20-Column, Hard-Copy Printer
On-board thermal
t'nr'no,qr,qhlp rnll~rn-r.(lrnputers Easy-read

large, 20-Character Alphanumeric Display
Hrgh contrast. 16-segment characters for optimum readability. 64- - - - - - - - - - - /
charnc!er ASCII formal,

54-Key Alphanumeric Terminal-Style Keyboard
Provides 70 different aiphabetic, nucneric, control and special
functions

Among persona! computers, AlM 65 stars as the professional's microcomputer, Irs gifted with professional features for
those seriously interested in appiying Of learning rnicfoprocessors,
it's priced so (ow that most everybody can afford it.
architecture;
int.,rf",r;r,n c,ap,~biliHes: expandable memory;
computer-like
multi-mode
interactive, se!f~prompting software; on-board printer
dis-

2

play. ,.AIM 65 is the professional's microcomputer for systerr
development and products, the amateur's headstart for pro
fessional learning.
Harnessed for work, AIM 65 as a "bare-board" micro
computer out-performs in its price category --, and in muct
higher priced categories-as an intelligent, programmabl(
stand-alone or terminal contro!!er or processor. By itself. it':
an economically feasible system for small-volume product:
or one-of-a-kind work projects.

r------

Third-Generation, High Performance 1·MHz 6502
Microprocessor
The 6502 is
Ihe \\"ortd's most
has millirl)rr11'lt ttpf-i'lkA
details on Page

CPU;

Full~Bus System Expansion Connector
44!pin connector extends address, data, control
PROM ""',r",<,mrnor

•

BASIC Interpreter Firmware
Contained on two R2332 ROMS; simphiies programming;
to learn, {Optional)

Plug-In Sockets for 20K-Bytes of ROM or PROM
sockets
five industry-standard 2332
Memory
or compatible Prc)Qr,ammable
or
program firmware.

Advanced Interactive Monitor Firmware
on two R2332 ROMs. interactIve Monilor Program
innovative software. A Text
ROMs, For ful!
4

3

RockweIIAlM65•••inspired
AIM 65's gifted features are realized by its owners through
truly inspired software which is made available as "firmware"
contained on ROMs, Software packages include

I

Advanced Interactive Monitor
The heart of AIM 65's software, this program provides
you with a comprehensive set of single-keystroke commands see "Monitor Commands" at right.
All commands are self-prompting: each displays an appropriate message when more information is required, or if
you happen to make a mistake, an error code is displayed,

Sed·promptmg program cleveloprnen!

Included in the Interactive Monitor is a Mnemonic Assembler program that translates instructions in simple
three-letter abbreviations (called "mnemonics") that we humans easily understand, into binary codes that the microprocessor understands. The Mnemonic Assembler frees you
from hassling with the confusing array of hexadecimal
"opcodes" that most low-priced microcomputers use.

language programming is like building a house with boards
and nails. while high level language programming is like
using pre-fabricated sections.
Examples of the programming simplicity that AIM 65's
Interactive Monitor software gives you, are the following
functions you can command with single keystrokes:
o Print step-by-step program listings on the on-board printer
or on an attached TTY or terminal:
Display and change selected Registers and
o Set breakpoints, and trace program execution for
ging in single-step modes:
o Transfer data from attached TIY or cassette recorders,
including manipulating programs from one tape to
another;
o Store programs in on-board or external RAM. ROM. PROM.
or in other external memories such as tapes. Hoppy disks,
bubbles. etc,
Text Editor
This program is stored as firmware on the same ROMs con·
taining the Interactive Monitor. It gives you the advantages of
displayed or printed program entries and listings which are
translated by the Symbolic Assembler and the PL/65 Cornpile! into machine codes. It also
you supenor
capabiHties. Most of the Text
commands-see
-are
Tt1e Text Editor even includes a
command
automatically locates instructions, comment8
and labels in the program being developed.
With the Text Editor, you can add. delete and changE
instructions anywhere in the program without affecting any
other portion.

Mnemonic input lor an acidllion progra,"n,

With only the Interactive Monitor installed, you can assemble simple microcomputer programs based on mnemonic entries. This is 'the best way to start learning how a
microcomputer "thinks,"
AIM 65's Interactive Monitor contains single-stroke
commands enabling you to interface with a powerful but
simple-to-use Text Editor. or with higher level programming
languages-Symbolic Assembler, BASIC Interpreter, PLl65
Compiler -all of which are available now and are described
fater - and with other higher level languages whose firm·
ware is being developed, Applicable commands are shown
at right.
While the Mnemonic and Symbolic Assembler gives
aspiring professionals easier-understanding of the fundamentals of programming, the higher level languages facllltate and speed up the process, An analogy is that assembly

4

Symbolic I:nput to tile Text Editor for same addition program

Symbolic Assembler
Firmware is contained on a separate ROM. The Symbolic
Assembler software gives practicing professionals a highl;
efficient means for developing the most complex programs
permitting the shortculting at programming time and doc
umentation by assigning labels to Instructions, subroutine~
and data locations,
At the same time. it introduces students to the fundarnen
tals of microcomputer programming in a basically simplE
fashion.

pro#essionalsollware.
The software inspiration in the AIM 65 approach is that
the Interactive Monitor and the Text Editor work together with
the Symbolic Assembler to provide displayed and printed
details of entries, listings and debug operations.

-t=:

=;; -

BASIC version of the same addition program

BASIC Interpreter
Firmware is contained on separate ROMs. AIM 65's highlevel BASIC is the most effective 8K version developed by
Microsoft.
The practicing professional will use BASIC to speed up
programming microcomputers designed as systems for
many computational and processing applications.
BASIC, which stands for Beginner's All-purpose Symbolic Instructions Code, is also the easy-use language offered by most amateur personal computers for fun and
games. Which says that when you want diversion from professional work or learning, your AIM 65's ready.
BASIC is universally recognized as the most easily
learned computer programming language. Even a complete
microprocessor novice should be able to begin writing
BASIC programs after only a few hours of study.

PLi65 version ol/he same addition program.

PL/65 Compiler
Firmware is contained on two separate ROMs. PU65 is a
high.level language that practicing professionals and advanced students use when large programs have to be
developed very rapidly-where software development costs
are important.
Rockwell's Future Software Plans
Rockwell is developing firmware {or the AIM 65 that will
provide owners with high-level languages facilitating a
variety of development projects.

Single-Keystroke MonItor ConurJands
Major Function Entry
(RESET Button)-Enter and initialize Monitor
ESC-Re-enter Monitor
E -Enter and initialize Text Editor
T -Re·enter Text Editor
N -Enter SymboliC Assembler
5 -Enter and initialize BASIC Interpreter
6 -Re-enter BASIC interpreter
Instruction Entry and Disassembly
I -Enter mnemonic instruction entry mode
K -Disassemble memory
Display/Alter Registers and Memory
* -Alter Program Counter to (address)
A -Alter Accumulator to (byte)
X -Alter X Register to (byte)
Y -Alter Y Register to (byte)
P -Alter Processor Status to (byte)
S -Alter Stack Pointer to (byte)
R --Display all registers
M-Display four memory locations. starting at (address)
(SPACE)-Display next four memory locations
! -Alter current memory location
Manipulate Breakpoints
# -Clear all breakpoints
4 -Toggle breakpoint enable on/off
B -Set one to four breakpoint addresses
? -Display breakpoint addresses
Control Instruction/Trace
G -Execute user's program
Z -Toggle instruction trace mode on/off
V -Toggle register trace mode onloff
H -Trace Program Counter history
Control Peripheral Devices
L --Load object code into memory from peripheral I/O
device
D -Dump object code to peripheral I/O device
1 -Toggle Tape 1 control on/off
2 -Toggle Tape 2 control onloff
3 -Verify tape checksum
CTRL PRINT-Toggle Printer on/o:(
LF-Line Feed
PRINT-Print Display contents
Call User-Defined Functions
Fl-·Ca!l User Function 1
F2,-Call User Function 2
F3-Call User Function 3
Text Editor Commands
R -Read lines into text buffer from peripheral 110 device
I -Insert line into text buffer from Keyboard
K -Delete current fine of text
(SPACE)-Display current line of text
L -List lines of text to peripheral 1/0 device
U -Move up one tine
-Move down one llne
T -Go to top line of text
B -Go to bottom line of text
F -Find character string
C -Change character string
Q-Quit Text Editor, return to Monitor

o

5

•

RockwellAIM 65•••",or. Ie

I

Third-Generation R6500 Microprocessor System
Functional heart of the AIM 65 microcomputer is an R6502
CPU (Central Processing Unit). The high-performance 8-bit
R6502 has 65K-byte memory address3bility and the power
of a 56-command, 13-addressing mode, minicomputer-like
instruction sel.
The R6502 is supported wittl selected R6500 microprocessor family devices to implement AIM 65's intern31 system and to provide vers3tile, used-dedic3ted applications'
interfaces,
An R6522 Versatile Interface Adapter (VIA) provides
/\!~Y1 65 uscrB \vHh hvo !nput/Output (f/O) ports, each vvith
eight lines. an 8-bit serialliO pon. and access to two on-cllip
16-bit interval-timer/event counters.
Broad Applications Options
This 1/0 capability gives you an amazingly broad range of
applications options. You can easily interface with sensors
6

and switches to perform item or batch rosponse functions.
You can readily include D-AiA-D converters and
vide audio and other functions in an ,AIM 65-baseci
(AIM 65 has a nine octave music "',,'''!Tno,",," "c>,""c';'\li,f"
An Application Note is
so that you can
lace AIM 65 to a CRT monitor or TV set.
Inqenious professionals also use AIM 65's inspired software to increase its applications potentials. For exarnple, one
engineer uses the Text Editor to list and look up stored telephone numbers so that Ilis AIM 65 functions as an automatic
telephone dialler.
A!M 65's !fO abilities also allow you to directly hook up
one or two cassette recorders. One use of cassette recorders
is permanently storing programs you develop for bookkeep. ing. home environmental and security control, student education, etc. When you want to use your AIM 65 for a special
purpose, you simply load the applicable taped program
into RAM.

lures lorprofessionals.

•

:xpansion Motherboard Available
'or System Add-On Modules
aslly attached to AIM 65's full-bus
:ormector is a Motherboard with five
tandard and
modules available from
·urr-Brown,
and other rnanufacturers,
AIM 65'~; Expansion Connector and Motherboard
full
bus lines
address.
provide ample drive capacity.
for rnapping internal and external
increments is provided,
ddresses in
Using the Expansion Connector and/or the Motheroard, you can readily enlarge your system to include PROM
roorammer module. PROM modules, floppy disk controller
lodule. RAM modules and ottler subsystem modules.

For
you can add
Prototyping
for the
Rockwell SYSTEM 65
microprocessor) and the
Motorola EXORciser A
rnicroprocessor),
To convert your processor or controller into an intl21lii;:jellt
terminal, you can
add a Rockwell fi24
Modem (2400 bps) or
board modems. This means
can use your AIM 65 to "talk" over ordinary telephone
to otlier computers or other AIM 65s.
to let
use the emergAnd your AIM 65 is now
ing memory generation-Bubble
Memories. Under
available software control, your AIM 65 can address air
128K-bytes of a Rockwell Bubble Memory module, providing
you with a magnificent file directory.

7

RockwellAIM65•••lor working
Rockwell AIM 65 Advanced

Interactive Microcomputer

•
Professionally Written Texts
With your AIM 65, you're supplied with all required explanatory and operating documentation.
AIM 65 texts include: 1)
AIM 65 User's Guide-450
pages; everything you need
to know about operating
your AIM 65 in clear, concise
language. 2) AIM 65 Monitor
Program Listing-118 pages:
a complete commented
listing of AIM 65's ROMresident Monitor software.
with both a symbol table
and a cross-reference index.
3) AIM 65 Summary Card
-pocket size; handy summary of Monitor, Text Editor and
Assembler commands, the System Memory Map, R6522 VIA
and Monitor subroutines. 4) AIM 65 Schemat/c-A postersize circuit diagram. 5) R6500 Programming Manual-260
pages; reference guide to 6502 assembly language programming: covers many of the If 0 and other 6500 family devices. 6) R6500 Hardware Manual-208 pages: reference
guide to the microprocessors, I/O and other 6500 devices. 7)
R6500 Programming Reference Card-pocket size; summarizes all instructions and addressing modes for the 6502
CPU. 8) AIM 65 BASIC Reference Manual-S9 pages; a
complete reference gulde. By special arrangement with the
publishers, Rockwell also offers two excellent books to AIM
65 customers. at reduced prices: 1) Microprocessor Systems
Engineering-641 pages: college level textbook by R. C.
Camp. T. A. Smay and C. J. Triska: generally recognized as an
outstanding text for all seriously interested in acquiring pro8

Praiessionally written texIS.

fessional understanding of microprocessing and microcomputers. 2) 6502 Software Oesign-270 pages; tutorial book
by L. J. Scanlon; gives a step-by-step approach to programming 6502 microprocessor-based computers in assembly language, with special emphasis on the AIM 65.
Rockwell Keeps You Current
Your purchase of AIM 65 entitles you to become a subscriber
to Interactive. a professional newsletter Rockwell publishes
regularly to keep AIM 65 o'!vners up to date on innovative design ideas, programming shortcuts and other professional
applications data. Subscription price is minimal.
Applications Notes
Rockwell is continually producing Applications Notes which

and learning professionals.
I

•

Professional teaching and learning

are availab1e to AIM 65 owners at no charge. New Applications Notes will be described in issues of Interactive.
Typical of existing Applications Notes are: "Interfacing KiM4 to AIM 65"-Docurnent R6500 N11; "Using KIM-1 Tapes
with AIM 65"-R6500 N19; "Preparing an AIM 65 BASIC Program for PROM/ROM Operation"-R6500 N15; "SYSTEM
65 to AIM 65 Interface"-.. R6500 N04, "A CRT Monitor or TV
Interface for AIM 65" -R6500 N12; "R232C Interface for
AIM 65"---R6500 NOB.
Professional Teaching and Learning
AIM 65 is tops in any class for microprocessor learning. And
its special educational features come at a low price school
budgets can afford. Its on-board printer produces hard
copies of exercises for easy checking by student and instruc-

Professiollal microcomputer dovelopment

tor. Interactive Monitor software prompts students each step
of the way in learn-lhrough-doing education.
Microcomputer Design Courses
Rockwell offers 6500 microcomputer design courses that
include using the AIM 65. For details, schedules, locations,
contact Rockwell Offices-see back cover of this brochure.
Professional Microcomputer Development
Now for a few hundred dollars-instead of many thousands
-AIM 65 functions as a complete programming and system
development aid. Personality modules are available. You can
develop your program in RAM, store it on tape or Happy disk
for debugging and prototyping. then lransfer it into PROM for
field testing.

9

I

I

RockwellAIM 65•••/01
Process control and management, chemical mixing and
control, test equipment and instrumentation, data logging
and computing ... AIM 65 as a "bare-board" microcomputer is already being used in an astonishing variety of work
assignments.
For a few hundred doliars, the "bare-board" AIM 65
gives you dedicated or programmable controllers or processing systems that duplicate functions now being performed
with minicomputers costing thousands of dollars.
And today the "bare-board" AIM 65 has proved to be
economically feasible as the implementing system of control
and processing products designed for low-volume use.
(100 units a year is a generalized rule of thumb, but do your
own calculations.)
Rockwell's Applications Engineers will be happy to consult with you on contemplated programs. Call the nearest
Rockwell Office listed on the back cover of this brochure.

Bare-Board AIM 65 Is Now Being Used in Low-Volume
Products Like:

Electronic Components Testers
Energy Management Systems
Card and Badge Readers
Chemical Mixing Controllers
Hotel Wake-Up Systems
Manufacturing Controllers
Industrial Appliance Controllers

Radio Burst Testers
Machine Tool Controllers
Digital Plotting Systems
Coin Counters
Medical Equipment
Postal Scales
Label Printers

AIM 65 Lets Professional Imaginations Fly but Keeps
Product Costs on the Ground ...

~rolessional work.
Designed in Days instead of Months ... Costing Hundreds instead of
Thousands of Dollars ... AIM 65-based Systems Record, File, Retrieve,
Analyze, Compare Data ... Monitor and Control Processes and Operations

AIM 65
The Professional's
Microcomputer ...
more of the power in
ROCKWELL MICROPOWER

I

DQCUMENT NO. 29650 N57
MAY 1979
.~.

.~ . .

:.

r. . ~

A65-009

'f:;

l'l'~~OCkWelr~

,-'- .

PART NUMBER

}~~~

R6500 Microcomputer System
PRODUCT DESCRIPTION

AIM 65 EXPANSION MOTHERBOARD
OVERVIEW

FUNCTIONAL DESCRIPTION

The AIM 65 Expansion Motherboard (Part No. A65-009) is used
to extend the AIM 65 system bus to external add-on modules. Its
five on-board connectors support all modules designed for Rockwell's SYSTEM 65 or Motorola's Exorcisor® , as well as other
modules offered by Rockwell, Motorola, Burr-Brown and a variety
of other manufacturers.

In reading the following text, refer to the attached schematic,
PAOO-X143.

The AIM 65 system bus lines (address, data and control) are
buffered to provide ample drive capability. Address decode logiC
for mapping internal and external addresses in 4K-byte increments
is also provided.

® "Exorcisor" is a registered trademark of Motorola, Inc.

The Address Bus lines AO-A15 and Control Bus lines 02, SYNC,
R/iii and 01 from the AIM 65 are buffered with 8T97 devices
Z3, Z4, Z5 and Z6. The Data Bus lines 00-07 are buffered and
inverted with 8T26A devices Zl and Z2. The address, data and
RIW lines are controlled by the external 5MA line. If ~ is
high, the address, data and RIW buffers are enabled 10 drive. If
DMA is low, these buffers are placed in the off state, allowing an
external controller to drive the address, data and R/W lines. The
remaining buffered lines, 01, 02 and SYNC, are unaffected by the
state of DMA.
Control lines RDY, RES, NMI, IRQ and S.D. are unbuffered, but
are brought directly to the AI M 65 Expansion Connector.

FEATURES
•
•
•
•

AI M 65 bus expansion
Accepts up to five compatible modules
Address selection in 4K-byte increments
System bus lines are fully buffered
DMA logic provided

<9 Rockwell International COrporation 1979
All Rights Reserved.
Printed in U. SA

Address decoding is provided on the AIM 65 Expansion Motherboard. Device Z10 (SN74159) is used to decode the four highorder address lines, A12-A15. The one-of-16 outputs are connected to a set of 16 switches, Sl and S2. When one or more of
the switches are closed/opened, the de~ode logic (Zll, Z7, Z8 and
Z9) enables/disables Data Bus drivers Zl and Z2. The Rlii line
determines the direction of data flow.

$peclfications subject to
change Without notice

SWITCHES AND JUMPERS
Internal/External Address Selection Switches

02 Clock Jumper

Sixteen switches on the AIM 65 Expansion Motherboilrd permit the
user to define whether eilch 4K-byte portion of the system address
sp"ce is internal or external to the AIM 65. When a switch is set to ON,
its correspondinq 4K address rilnge is external li.e., on the AIM 65
Expilnsion Motherboard). Conversely, when a switch is set to OF F,
its correspondin'l 4K address range is internal (i.e., on the AIM 65
Microcomputer). Tilble 1 shows the address range corresponding to
each switch on the Expansion Motherboard.

AIM 65 Expansion Motherbcard connectors J2 through J6 provide
the 02 clock on Pin J. This clock signal can be optionally provided on
Pin L as well, by installing Jumper W4 on the Expansion Motherboard.

CAUTION
Br Cilrf!ful ill assiqninq externlll address space,
since it nlily conflict With internal functions of
II", AIM 65. Sef"Seclion 7.3.2 of the AIM 65
Us"r's GuidI! for AIM 65 ilddress ilssiqnments.

I

Table 1. Address Selection Table
Switch

Address Range (Hex)

S2·1
-2
-3
-4
-5
-6
-7
-8

0000 to OFFF
1000 to lFFF
2000 to 2FFF
3000 to 3FFF
4000 to 4FFF
5000 to 5FFF
6000t06FFF
7000t07FFF

Sl-8
-7
-6
-5
-4
-3
-2
-1

8000 to 8FFF
9000 to 9FFF
AOOO to AFFF
BOOO to BFFF
COOO to CFFF
DOOO to DFFF
EOOO to EFFF
FOOO to FF FF

DC Power Selection Jumpers
Power for the AIM 65 Expansion Motherboard can be supplied in either
of two ways. For add-on modules with current requirements of less
than 0.5 amp, the DC power (+5, +12 and -12 Vdc) brought in on
AIM 65 Expansion Connector J3 is adequate. For higher current
retjuirements, DC power should be supplied through Expansion Con·
nector power strip TB 1, and Jumpers W1 (+5 Vdc), W2 (+12 Vdc)
and W3 (·12 Vdc) should be removed.

INSTALLATION
The following procedure should be used to install the AIM 65 Expan
sion Motherboard onto the AIM 65 Microcomputer:
1.

Mount the ten supplied card guides on the AIM 65 Expansion
Motherboard with the screws provided (two screws per guide),
with one card guide on each end of connectors J2 through J6.

2.

The kit includes five self·adhesive rubber feet. Install a rubber
foot in each corner of the Expansion Motherboilrd, and one foot
in the center.

3.

Remove jumpers W1, W2 and W3, if required.
Selection Jumpers.

4.

Certain add-on modules access the 02 clock on Pin L.
Jumper W4 if your add-on modules have this requirement.

5.

Connect Expansion Motherboard Connector P1 to AIM 65 Expansion Connector J3.

CLOCK
JUMPER
(W4)

DC POWER
SELECTION
JUMPERS
(Wl,W2,W3)

Install

CAUTION
Never install or remove the AIM 65 Expansion
Motherboard or add-on modules with system
power on. It may cause damage to the AIM 65,
the Expansion Module or the add-on module.

6.

Install the add-on modules into any of the slots on the AIM 65
E'xpansion Motherboard, J2 through J6, With the component
side of each add-on module facing the AIM 65.

7.

Configure address selection Switches S 1 and S2, as appropriate
to your system. See I nternal/External Address Selection Switches.

8.

Apply power to the AIM 65 and, if retjuired, to the AIM 65
Expansion Motherboard.

CARD
GUIDES



s:
s:m

:lJ

l>

2

C

(')

o
I

m

o

s:

o
c
C

r-

m

© Rockwell International Corporation 1980
All Right. Reserved
Printed in U.S.A.

Specifications subject to
change without notice
Oocument No. RMA65 N17
September 1980

•

FUNCTIONAL DESCRIPTION
The R6520 Peripheral Interface Adapter (PIA) is the primary
interface device between the AIM 65 Expansion Connector
and the 24-pin Zero Insertion Force PROM socket and control
_,.circuits. During PROM programming, PROM address, PROM
data and programming control signals are transmitted to the
PIA on the AIM 65 Expansion Connector data lines. During
PROM check, verify and read operations, only PROM address
and control signals are issued to the PIA from the AIM 65.

I

Four PIA I/O Lines carry the most significant address signals
to the PROM. Eight other PIA I/O lines mUltiplex the PROM
data and least significant address signals. One output line controls the Tri-State Data Latch. Five other PIA I/O Lines control the Power Switches.
During PROM programming, PROM data is transferred to the
tri-state Data Latch, which drives the latched data to the
PROM. The PROM address is then sent to the PROM on the
eight multiplexed data/address lines and the four dedicated
address lines. The Power Switches are then turned on to
apply the proper voltage levels for the required time duration
to transfer the 8-bits of data into one PROM location. The
process is repeated until the specified PROM address range
is fully programmed. The tri-state Data Buffer is disabled
during programming.

During PROM read operations, the PIA sets the address lines
to the PROM. The tri-state Data Buffer drives the PROM data
onto the AIM 65 Expansion Connector data lines. The Data
Latch is disabled at this time.
The Power Switchrs drive +5V or +26V onto three PROM
socket programming lines depending on the PROM type
selected.
The 4K R2332 ROM contains the PROM Programmer and
CO-ED firmware.
1 K bytes of on-board RAM are provided for use by the PROM
Programmer and CO-ED software. The RAM is mapped from
$1000-$13FF to provide contiguous addressing from the top
of a 4K RAM AIM 65.
The Address Decode circuitry generates individual chip select
signals to the RAM, ROM, PIA and the Data Buffer.
The PROM Programmer and CO-ED Module may be powered
from the AIM 65 or from an external +5V power supply. A
DC/DC Voltage Converter generates +30V from +5V. The
+30V is regulated to +26V for on-board use. The +30V may be
connected to an external power supply to minimize current
drain on the +5V supply.

CONNECT TO AIM-65
EXPANSION CONNECTOR

r--

2

1

2 ,

~

4K
R2332
ROM

10

4

ADDRESS
DECODE

~

1

8

)~

_IDATA
BUFFER
(TRISTATE)

1
1

~

CHIP SELECT

2

I,

5

3

CLOCK AND
CONTROL
ADDRESS

16

LATCH
(TRISTATE)

R6520
PIA

4

8/

8

24·PIN
PROM
ZIF
SOCKET

4

I

8

DATA

8 _1
5

~

L!.,t....
10

l J

, .. -:.

_ A_,

+5V

tI

1

~

b

A
+5V

1JL

+5V TO +30V
OC/DC
CONVERTER

I
b

B
GND

I
b

C
GND

1-r1

POWER
SWITCHES

1~

lK
2114
RAM

1

GND

-.I DATA

8

+Z6V
VOLTAGE
REGULATOR

r-

.tv I

AIM 65 PROM Programmer and CO-ED Module Block Diagram

3
~

AIM 65 Expansion Connector Pin Assignments
Top (Component Sidel
Signal
Mnemonic

Bottom (Solder Sidel
Signal

Illput!

Signal Name
·Sync

SYNC
ROY
<1>1

"Ready

·Phase 1 Clock

iAO

'Interrupt Request

S.O
NMI

·Set Overflow

Pin

Mnemonic

0
I
0

A
B
C
0

Address 811 0
Address 81t 1

H
J

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
SYS <1>2
SYS R/Vi

RiW

Read/Write "Not"

TEST

Test
Phase 2 Clock "Not"
RAM ReadIW"te

Output

Pin

°Non-Maskable Interrupt

RES
07
06
05
04
03
02
01
DO
·12V
,12V
CS8
CS9

Reset

I

Data B,t 7

110

Data Sit 6

110

Data
Data
Data
Data

110
110

B,t
B't
B,t
Sit

5
4
3
2

Data Bit 1
Data B,t 0
'·12 Vdc
',12Vdc
Ch,p Select 8
Ch,p Select 9

GSA

·Chlp Select A

+5V
GND

Ground

10
11
12
13
14
15
16
17
18
19
20
21
22

110
110
110

110

0
0
0

,5 Vdc

M
N
R
S
U
V
W
Y
Z

R
R>
R
PICK
SP@
RP@
SO
BOUNDS

.S

Duplicate top of stack.
Duplicate top two stack items.
Delete top of stack.
Delete top two stack items.
Exchange top two stack items.
Copy second item to top.
Rotate third item to top.
Duplicate only if non-zero.
Move top item to return stack.
Retrieve item from return stack.
Copy top of return stack onto stack.
Copy the nth item to top.
Return address of stack pOSition.
Return address of return stack pointer.
Return ac:ldress of pointer to bottom of stack.
Convert "address count" to "end-address
start-address."
Print contents of stack.

+
0+
I
MOD

IMOD
"/MOD
"I
U"

UI
M
MI
M/MOD

MAX
MIN
NUMERIC REPRESENTATION
DECIMAL
HEX
BASE
DIGIT

o
1
2

3

Set decimal base.
Set hexadecimal base.
Set number base.
Convert ASCII to binary.
The number zero.
The number one.
The number two.
The number three.

+0+ABS
DABS
NEGATE
DNEGATE

S

-> 0

1+
2+
1-

2COMPARISON OPERATORS

<
>

0<
0=

U<
NOT

True if n1 less than n2.
True if n1 greater than n2.
True if top two numbers are equal.
True if top number negative.
True if top number zero.
True if u1 less than u2.
Same as 0=.

AND
OR
XOR

Add.
Add double-precision numbers.
Subtract (n1 - n2).
Multiply.
Divide (n1/n2).
Modulo (i.e. remainder from division).
Divide, giving remainder and quotient.
Multiply, then divide (n1"n2ln3), with double
intermediate.
like "/MOD, but give quotient only.
Unsigned multiply leaving double product.
Unsigned divide.
Signed multiplication leaving double product.
Signed remainder and quotient from double
dividend.
Unsigned divide leaving double quotient and
remainder from double dividend and single
divisor.
Maximum.
Minimum.
Set sign.
Set sign of double-precision number.
Absolute value.
Absolute value of double-precision number.
Change sign.
Change sign of double-precision number.
Sign ~xtend to double-precision number.
Increment value on top of stack by 1.
Increment value on top of stack by 2.
Decrement value on top of stack by 1.
Decrement value on top of stack by 2.
logical AND (bitwise).
logical OR (bitwise).
logical exclusive OR (bitwise).

AIM 65 FORTH WORDS (con't)
OUTPUT FORMATTING

CONTROL STRUCTURES
DO ... LOOP
DO ... +LOOP

I
LEAVE
BEGIN ... UNTIL
BEGIN ... WHILE
... REPEAT
BEGIN ... AGAIN
IF ... THEN
IF ... ELSE ... THEN

Set up loop, given index range.
Like DO ... LOOP, but adds stack value to
index.
Place current index value on stack.
Terminate loop at next LOOP or +LOOP.
Loop back to BEGIN until true at UNTIL.
Loop while true at WHILE; REPEAT loops
unconditionally to BEGIN.
Unconditional loop.
If top of stack true, execute following clause
THEN continue; otherwise continue at
THEN.
If top of stack true, execute ELSE clause
THEN continue; otherwise execute following
clause, THEN continue.

DUMP
TYPE
?TERMINAL
KEY
EMIT
EXPECT
WORD
IN
HOLD
BAUD
BL
C/L
TIB
B/SCR
QUERY
10.

Carriage retum.
Type one space.
Type n spaces.
Print text string (terminated by").
Dump n2 words starting at address.
Type string of nl characters starting at
address n2.
True if terminal break request present.
Read key, put ASCII value on stack.
Output ASCII value from stack.
Read nl characters from input to
address n2.
Read one word from input stream, until
delimiter.
User variable contained within TIB.
Waits for KEY.
Set BAUD rate.
Output a SPACE character.
Number of characters/line.
Pointer to terminal input buffer start address.
Number of blocks/editing screen.
Input text from terminal.
Print  from name # field
address (nfa).

C@
C!

?
+!
CMOVE
FILL
ERASE
BLANKS
TOGGLE

#

#S
SIGN
#>
HOLD
HLD
-TRAILING
.LlNE
COUNT

DPL

Fetch value addressed by top of stack.
Store nl at address n2.
Fetch one byte only.
Store one byte only.
Print contents of address.
Add second number on stack to contents of
address on top.
Move n3 bytes starting at address nl to area
starting at address n2.
Put byte n3 into n2 bytes starting at
address nl.
Fill n2 bytes in memory with zeroes, beginning
at address nl.
Fill n2 bytes in memory with blanks, beginning
at address nl.
Mask memory with bit pattem.

Convert string at address to double-precision
number.
Start output string.
Convert next digit of double-precision number
and add character to output string.
Convert all significant digits of doubleprecision number to output string.
Insert sign of n into output string.
Terminate output string (ready for TYPE).
Insert ASCII character into output string.
Hold pointer, user variable.
Suppress trailing blanks.
Display line of text from mass storage.
Change length of byte string to type form.
Print number on top of stack.
Print number nl right justified n2 places.
Print double-precision number n2 nl.
Print double-precision number n2 nl right
justified n3 places.
Number of digits to the right of decimal point.

MONITOR & CASSETTE I/O
COLD
MON
?TTY
CHAIN
CLOSE
?IN
?OUT
GET
PUT
READ
WRITE
SOURCE
FINIS
-CR

AIM 65 FORTH cold start.
Exit to AIM 65 Monitor.
Switch: true = TTY; false = KB.
Chain tape file.
Close tape file.
Set to active input device (AID).
Set to active output device (AOD).
Input a character from the AID.
Output a character to the AOD.
Input n2 characters from AID to address nl.
Output n2 characters to AOD at address n 1.
Compile from the AID.
Terminate compile from SOURCE.
Output CR to printer only.

VIRTUAL STORAGE
LOAD
BLOCK
BlBUF

MEMORY

@
!

<#

.R
D.
D.R.

INPUT-OUTPUT
CR
SPACE
SPACES

NUMBER

BLK
SCR
UPDATE
FLUSH
EMPTY-BUFFERS
+BUF
BUFFER

R/W
USE
FIRST
OFFSET
PREV

Load mass storage screen
(compile or execute).
Read mass storage block to memory address.
System constant giving mass storage block
size in bytes.
System variable containing current block
number.
System variable containing current screen
number.
Mark last buffer accessed as updated.
Write all updated buffers to mass storage.
Erase all buffers.
Increment buffer address.
Fetch next memory buffer.
User read/write linkage.
Variable containing address of next buffer.
Leaves address of first block buffer.
User variable block offset to mass storage.
Variable containing address of latest buffer.

•

I

AIM 65 FORTH WORDS (con't)

MISCELLANEOUS AND SYSTEM

VOCABULARIES

(  )

CONTEXT

IN
LIMIT
QUIT

Begin comment (terminate by right
parentheses on same line).
System variable containing offset into input
buffer.
Top of memory.
Clear return stack and return to terminal.

COMPILER-TEXT INTERPRETER

->
;S
COMPILE
LITERAL
DLiTERAL
EXECUTE

Interpret next screen.
Stop interpretation.
Compile following  into dictionary.
Compile a number into a literal.
Compile a double-precision number into a
literal.
Execute the definition on top of stack.

DICTIONARY CONTROL

FORGET
HERE
ALLOT
TASK
-FIND
DP

C,

PAD

FORGET all definitions from  on.
Returns address of next unused byte in the
dictionary.
Leave a gap of n bytes in the dictionary.
A dictionary marker.
Find the address of  in the dictionary.
Search dictionary for .
User variable containing the dictionary pointer.
Store byte into dictionary.
Compile a number into the dictionary.
Pointer to temporary buffer.

DEFINING WORDS

: 
VARIABLE 
CONSTANT 
CODE 
;CODE

CREATE
USER

Begin colon definition of .
End colon definition.
Create a variable named  when initial
value n; returns address when executed.
Create a constant named  with value
n; returns value when executed.
Begin definition of assembly-language
primitive operation named .
Used to create a new defining word, with
execution'time "code routine" for this data
type in assembly.
Used to create a new defining word, with
execution-time routine for this data type in
higher-level FORTH.
Create a dictionary header.
Create a user variable.

Retums address of pointer to CONTEXT
vocabulary.
Retums address of pointer to CURRENT
vocabulary.
FORTH
Main FORTH vocabulary.
ASSEMBLER
Assembler vocabulary.
VOCABULARY  Create new vocabulary.
VLlST
Print names of all words in CONTEXT
vocabulary.
VOC-LlNK
Most recently defined vocabulary.

CURRENT

SECURITY

ABORT
ERROR
MESSAGE
WARNING
FENCE
WIDTH

Error; operation terminates.
Execute error notification and restart system.
Displays message.
Pointer to message routine.
Prevents forgetting below this point.
Controls significant characters of .

PRIMITIVES

OBRANCH
BRANCH
PUT
ENCLOSE
RO
RPI
SO
SP!
NEXT

Run-time conditional branch.
Run-time unconditional branch.
Stores registers and jumps to next.
Text scanning primitive used by WORD.
Location of retum Stack.
Initializes return Stack.
Initial value of stack pointer.
Initialize stack pointer.
The FORTH virtual machine.

Software Development is Fast and Easy With ...

'1'

Rockwell
PU65
A High-Level Language
for the
AIM 65 Advanced Interactive Microcomputer
• PU65 Resembles PU1 and Algol
• PU65 ROMs Plug into AIM 65 Board
• Generates 6500 Assembly Language, for PostCompilation Editing and Assembling

• Upward-Compatible With System 65 PU65
• Has Control Structures for Conditional and Iterative
Looping
• Drop Down to Assembly Language, For Optimal Coding
Efficiency

In Rockwell's AIM 65, you have not only a low-cost, general-purpose
microcomputer, but also the basis for a cost-efficient, low-end development
system. By coupling AIM 65 with the advanced PU65 Compiler option
(Rockwell Part No. A65-030), you're even further ahead with valuable
savings in time, effort and cost.
Resembling PU1 and ALGOL in general form, PU65 is designed to improve
your productivity and efficiency by simplifying the overall software
development effort.
The coding is easier, since PU65's powerful, high level language
statements enable you to implement even complex applications with
minimal programming.
Program readability is enhanced by the self-documenting nature of PU65.
This results in programs that are easier to understand. These programs are
easier to update, too, which means lower maintenance costs.

PUS5 = Software Simplification
All language features are aimed at improving productivity by simplifying
software development. PU65's structured programming support features
encourage modular program design, and its general control structure for
conditional and Iterative looping allows the language to be applied to highly
structured programs.

Coding Flexibility ... When You Need It Most
PU65 allows you to freely mix assembly language instructions in portions of
the program where timing or code optimization requirements are critical.
This flexibility carries through the compile cycle: The PU65 compiler outputs
source code to AIM 65's optional assembler, rather than object code. You'll
be able to enhance or debug at the assembler level and indeed to drop into
assembly language whenever you desire. PU65 thereby provides the
structuring potential and programming simplicity of a high-level language,
while retaining the power and flexibility of an assembler.

The PU65 Package
PU65 for AIM 65 (Part No. A65-030) comes on two pre-programmed
4K-byte ROMs, and is supplied with a comprehensive PU65 User's Manual.
It's available now from your local Rockwell Distributor. For the name of your
nearest Distributor, call toll-free 800-854-8099 (within California,
800-422-4230).
For more information on PU65, SYSTEM 65, AIM 65, or the rapidly growing
family of R6500 products, contact
ROCKWELL INTERNATIONAL
P.O. Box 3669, RC55
Anaheim, CA 92803
Attn: Marketing Services, D/727

PUGS Language Statements
Declaration
DECLARE
DEFINE
DATA

Specification
ENTRY
EXIT
TFiLE
DFILE

Assignment
Conditional Execution
Direct Single
Byte Move
indirect Single
Byte Move
Direct Multiple
Byte Move
Imperative
SHIFT
ROTATE
ASSEMBLY CODE
iNC
INCW
DEC
DECW
STACK
UNSTACK

IF-THEN-ELSE
Branching
GOTO
CALL
RETURN
RTI
BREAK
HALT
Block
BEGIN
DO
END
Miscellaneous

Looping
FOR-TD-BY
WHILE

Comment
Tab

•

I

RM65
BOARD
PRODUCTS

:1..

-

~-

•
. ::-:-

,-"

r-,;-'~~~'-~~,-'~'~-"'~~'~-,

~~~_'''''~".''':'_~_':'~_:''~_","M.:':W_'~:_'_'''''''''''''

i\

',,,., """"'~~ =',.". " r ' , 'C'- ""',W"". ~''''''''~-''''

r

RM 65 Modulal

f

Standard size boards -. Buy only what y<
- Proven R6502 microprocessor •

It
~

Rockwell
International

Single Board Compu1

The Rockwell RM 65 microcomputer consists of hardware modules and software packages designed for OEM and end· user applications, The modules are compact functionally-oriented boards that
provide state-of-the-art performance at ofHhe-shelf cost. The
software packages inclUde biOIl level language interpreters and peripheral drivers.
The RM 65 microcomputer provides an "already complete"
flexible desIgn concept tIlat ahows you to build, and expand, asystem
exactfy to your needs. By using standard hardware and software. you
, reduce engineering costs, shorten product introduction cycles, buy
only what you need as you need It. '

RM65-1000
The Single Board Computer is the s
configurations, This single module incl
static RAM, 16K bytes PROM/ROM ca
8-bit parallel ports with handshake conl
serial shift register. This module alone,
makes a custom RM 65 microcompul

Modules

8K Static RAM Module
RM65-3108, RM65-3108N
Static RAM memory configurable as one 8192 byte block or as two
4096 byte blocks, On board switches select bank and address as·
signments, (RM65-3108N less RAM devices)
32K Dynamic RAM Module
RM65·3132. RM65-3132N
32,768 bytes of dynamic RAM, transparent refresh maintains performance, Bank selection in 16K blocks. address in 4K blocks, switch
selectable, (RM65-3132N less RAM devices)

CRT Controller (CRTC) Module
RM65·5102
Provides an R6545 CRT device for timing and control. 2K bytes
refresh RAM and 2K by!es ROM software, The module outputs
HSYNC, VSYNC, and Video signals as well as composite video,
Provides alphanumeric and limited graphics characters.
IEEE·488 Bus Controller Module
RM65·7102
Implements standard general purpose interface bus, communicates
with up to 15 peripherals. On-board ROM software implements talk.
listen, and controller functions.

16K PROMIROM Module
RM65·3216
Socketed to accept 2K, 4K or 8K 24-pin-devices up to a total of 16K
bytes of memory, May be assigned to one of two memory banks,
switch selectable in 4K byte sections.
Floppy Disk Controller (FDC) Module
RM65-5101
Controls up to four 8' single density or 5 v." single or double density
disk drives, single or double sided, Software in on-board 4K ROM.

General Purpose Inpul/Output and Timer Module
RM65-5222
Total of 40 buffered I/O lines, Two R6522 devices provide four 8-bit
parallel ports with hand-shake. four multi·mode 16·bit timers. two
8-bit shift registers,
Asynchronous Communications Interface Adapter (ACIA) Module
RM65-5451
For RS232C serial interface, Two R6551 ACIA devices control two

~n~~~ngi~~.RiJ~iCrf~~te~~~/~J~~~~;~~~/~~sd~~~

50 to

hicrocompufer
~ed,

when you need it • Cut design costs

v cost AIM 65 development system

3int for all RM 65 microcomputer
)opular R6502 CPU with 2K bytes of
dan R6522 VIA which provides two
lulti-mode 16-bit timers and an 8-bit
ne or more memory or 1/0 modules.

Software
Software drivers for peripheral 1/0 devices and higher level
language interpreters make fitting the RM 65 microcomputer to your
application both easy and flexible. You can interface directly with the
software drivers or the programmable devices. You can turn your RM
65 microcomputer into a BASIC machine.
CRT Controller Software Package
CRT driver. screen generation and test subroutines.
fDC Software Package
Disk driver. file management and test subroutines.
IEEE·488 Software Package
Subroutines implement 1978 standards and module test.
BASIC Run Time Software Package
Directly compatible with AIM 65 BASIC. 8K byte ROM resident.
Universally recognized as the most easily learned programming language.

Features: 100mm x t60mm (3.9" x 6.3") RM 65 modules are
size efficient with each providing a needed microcomputer function.
There is no need for buying unwanted electronics. The boards are
available with a high-reliability European DIN compabble 54-pin can·
nectar or a lower cost edge connector. Quality is built-in - all
components are pre-tested and all finished assembtiesare burned-In.
RM 65 microcomputer software packages are designed fOf in~
corporation into the appllcation end-product. The Intelligent peripheral controller modules include associated software; at the system
level a SASIC language interpreter is provided. And, only Rockwell
offers the AIM 65 as a low-cost complete development system, to
support the design using RM 65 microcomputer products.

•

Accessories
4-, 8-, and 16-Slot Card Cages
RM65-7D04, RM65·7008, RM65-7016
Modules insert into card cage, edge or pin connector style mother
boards. power supplies connect to screw-down terminals.
Single Card Adapter
RM65·71D1
Attach a single RM 65 module to the AIM 65 microcomputer.
Adapter/Buffer Module
RM65·7104
Allows connection of multiple RM 65 modules to the AIM 65
microcomputer.
Cable Driver Adapter /Buffer
RM65·7116
Remotely locate RM 65 modules from AIM 65.

, ~..

Design Prototyping Module
RM65·72D1
Allows custom circuit fabrication. Power and return lines pre-routed
through module. Plated-through hole pattern permits manual or automatic wire-wrap.
Exlender Module
RM65-7211
Maintains electrical continuity with RM 65 bus while troubleshooting.
extends any module outside the card cage.

AIM 65 Microcomputer
The low-cost AIM 65 microcomputer can be used as a complete
development system for the RM 65 microcomputer. The AIM 65
functionally replaces the Single Board Computer for in-circuit evalua·
tion of the RM 65 microcomputer system in the application. The
PROM Programmer and CO-ED module, BASIC interpreter. PLl65
compiler and 2-pass assembler are all options.
SYSTEM 65 Development System
SYSTEM 65 offers the more traditional microprocessor development
system. SYSTEM 65 comes with dual floppy disk drives, RS232G
interface. parallel interface to printers, plus debug, text editor and
two-pass assembler. Options include PU6S compiler. BASIC interpreter. PROM programmer and User 65 module.

,
~

I

PART NUMBER

RM65-1000(E)
~~' ~! "~

r"

"1' .Rockwel~
•~

RM 65
DATA SHEET

.. '4.

SINGLE BOARD COMPUTER (SBC) MODULE
RM 65

FEATURES

The RM 65 product line is designed for OEM and end user microcomputer applications requiring state-of-the-art performance,
compact size, modular design and low cost. Software for RM 65
systems can be developed in R6500 Assembly Language, PL/65,
BASIC and FORTH. Both BASIC and FORTH are available in
ROM and can be incorporated into the user's system.

•
•
•
•
•
•

The RM 65 product line uses a motherboard interconnect concept
and accepts any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 128K bytes, high immunity to electrical
noise and includes growth provisions for user functions. A selection of card cages provides packaging flexibility. RM 65 products
may also be used with Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable or desktop microcomputer applications.

•
•
•
•

PRODUCT OVERVIEW
The Single Board Computer Module (SBC) allows users to design
their products into compact modular stacks. The SBC module
plugs into a single slot in an RM 65 card cage/motherboard and
controls other memory and I/O modules. The heart of the SBC
module is an R6502 CPU, which is capable of addressing 65K
bytes of memory.. In addition, the SBC module contains bank
address logic which allows addressing of one or two 65K byte
memory banks. Sockets on the module accept up to 16K bytes
of PROM/ROM. 2K bytes of static RAM are also provided.
An R6522 Versatile Interface Adapter (VIA) provides two 8-bit
parallel I/O data lines, two 2 bit control lines, two countertimers and an B-bit shift register. On-board switches assign memory sections to 4K byte blocks. All address, data and control lines
are buffered.

•
•

Compact size - about 4" x 6Yz" (100 mm x 160mm)
Edge connector and Eurocard versions
On-board R6502 CPU
2K of 2114 static RAM
Two sockets for up to 16K PROM/ROM
Supports the following PROM/ROM or equivalents
- TI TMS 2516, TMS 2532 and Motorola MCM6B764 PROMs
- Rockwell R2316, R2332, or R2364 ROMs
R6522 Versatile Interface Adapter (VIA) and I/O Interface
Fully Buffered Address, Data, and Control lines for RM 65
Bus
Separate switches allow RAM, PROM/ROM, and VIA to be
individually dedicated to one or two 65K byte memory banks
Jumpers allow selection of the following
2K, 4K or BK PROM/ROMs
RAM, PROM/ROM and I/O starting address to 4K byte
boundary
On-board or External bank addressing source
Programmable DMA Terminate
On-board or external clock sounce
+5V operation
Fully assembled, tested and warranted

-

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ORDERING INFORMATION
The SBC Module is available in an Edge Connector version (RM651000) and a Eurocard version (RM65-1000EI.

DJ

-s:
n

O.
C
C
rm

CCRockwelllnternatioAal Corporation 1981
All Rights Reserved
Printed in U.S.A.

Eurocard Version

Edge Connector Version

RM65-1000E

RM65-1000

Specifications subject to
change without notice

Document No_ RMA8S N10

R.v_ 1. MllrCh 1981

FUNCTIONAL DESCRIPTION
The Clock Circuit uses a crystal-controlled oscillator to provide a stable
1·MHz clock reference. A jumper selects between the internal-clock
reference or an external clock Ito 1 MHz) as the source for the R6502
and the derived system clock.
The Reset ContrOl circuit conditions the Reset signal to drive the
R6502 Reset line. A reset can be generated by either the on·board
reset pushbutton or an external switch. This circuitry also generates
a reset automatically, upon power·up.
The R6502 Central Processing Unit (CPU) is the heart of the SBC
Module and any interfacing Modules connected to the RM 65 Bus.
The R6502 controls all program execution by means of the address,
data, control, and timing lines. All internal R6502 operations are
synchronized to the clock source.

•

The Bank Select Control circuit detects when the SBC Module's assigned
memory bank is addressed, by comparing the Bank Address signal to
the Bank Select Enable and Bank Select switches. The Bank Select
Enable Switches allow all on·board PROM/ROM, RAM, & VIA to be
independently assigned common to both Bank 0 !lower .35K) and
Bank 1 lupper 65K) or dedicated to either Bank 0 or Bank 1, depend·
ing on the Bank Select switches. A jumper allows the Bank Address
signal to be driven by the on·board R6522 VIA orfrom another module.
The Base Address Decoder uses the six most·significant address bits
and the Base Address Jumpers to generate chip selects for the on·board
PROM/ROM, RAM, and VIA. The RAM and VIA can be independ·
ently mapped into any 4K block of the selected 65K bank, The PROM/
ROMs may be mapped into any 4K or BK block of the selected bank.
The 16K PROM/ROM section has two sockets which can accept 2K,
4K or BK PROM/ROM devices. The size and type of PROM or ROM

is specified by the Base Address selection jumpers and the PROM/
ROM type jumpers.
The 2K RAM section uses four 1K x 4 RAM devices to provide on·
board read/write memory,
The R6522 Versatile Interface Adapter IVIA) provides input·output
capability to the SBC Module. The VIA provides two B·bit I/O ports
each with two control lines. Both ports and control lines are brought
out to a connector for user applications.
The SBC Module can control up to 15 additional support modules by
means of the RM 65 Bus. There are three groups of signals on the
RM 65 Bus: data, address, and control.
The Data Transceivers invert and transfer eight bits of parallel data
between the SBC Module and the RM 65 bus. The direction of the
transceivers is controlled by the read/write signal from the R6502.
The transceivers are disabled when the on·board PROM/ROM RAM,
or VIA is addressed or when the Bus Float signal from the RM 65 Bus
is active.
The Address Buffers invert and transfer 16 parallel address bits from
the SBC Module to the RM 65 bus.
The Control Buffers buffer all control and clock signals between the
SBC MOdule and the RM 65 bus. The Non·Maskable Interrupt, Interrupt Request, Set Overflow, External Clock (00), Ready and Bus Float
input lines are buffered coming from the RM 65 bus into the SBC
Module. The DMA Terminate, Reset and Phase 1 Clock 101) output
lines are always driven from the SBC Module onto the RM 65 Bus.
The other six output lines for Read/Write, Phase 2 Clock, sync, and
Bank Address are also .buffered, but are tri·stated Idisabled) when the
Bus Float signal is active.

I/O CONNECTOR
PORT A

DATA
PORTA
CONTROL
PORTB
DATA

PORTB
CONTROL

R_
BUS CONNECTOR
BUS FLOAT
oMA TERMINATE

I
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II

CLOCK.
CONTROL

BANK AOoRESS

:mEl

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ADDRESS

RMlS5

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EXTERNAL
CLOCK

SBe Block Diagram

RM 65 Bus Pin Assignments
Bottom (Solder Side)

Top (Component Side)
Signal
Mnemonic

Signal Name

Signal
Mnemonic

Signal Name

Pin

Pin

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Notel

Xa

Xc

+5V

+5-Vdc (See Notel

GND

Ground

la

lc

+5V

+5 Vdc

BADR!

Buffered Bank Address

2a

2c

BA15!

Buffered Address Bit 15

GND

Ground

3a

3c

BA14!

Buffered Address Bit 14

BA13!

Buffered Address Bit 13

4a

4c

BA12!

Buffered Address Bit 12

BAll!

Buffered Address Bit 11

5a

5c

GND

Ground

BA10!

Buffered Address Bit 10

6a

6c

BA9!

Buffered Address Bit 9

Buffered Address Bit 8

7a

.

BA8!

7c

BA71

Buffered Address Bit 7

GND

Ground

Ba

8c

BA61

Buffered Address Bit 6

Not Connected (See Notel

BA51

Buffered Address Bit 5

9a

9c

BA41

Buffered Address Bit 4

BA31

Buffered Address Bit 3

lOa

lOe

GND

Ground

BA21

Buffered Address Bit 2

lla

llc

BAlI

Buffered Address Bit 1

BAOI

Buffered Address Bit 0

12a

12c

B01

Buffered Phase 1 Clock

GND

Ground

13a

13c

BSYNC

BSa

Buffered Set Overflow

14a

14c

BDR011

Buffered Ready

Buffered Sync
"Buffered DMA Request 1
Ground

15a

15c

GND

• User Spare 1

16a

16c

-12V/-V

• +12 Vdc/+V

17a

17c

GND

Ground Line

18a

18c

BFlTI

BDMTI

Buffered DMA Terminate

19a

19c

B;o

Buffered External Phase 0 Clock

20a

20c

GND

Ground

21a

21c

BDR021

22a

22c

BRm
BACTI

BRDY

+12V/+V

• User Spare 3
BR!WI

Buffered Read/Write "Not"
• System Spare

• -12 Vdc/-V
• User Spare 2
Buffered Bus Float

"Buffered DMA Request 2
Buffered ReadlWrite

GND

Ground

23a

23c

• Buffered Bus Active

BIROI

Buffered Interrupt Request

24a

24c

BNMII

Buffered Non-Maskable Interrupt

B~21

Buffered Phase 2 "Not" Clock

25a

25c

GND

Ground

B~2

Buffered Phase 2 Clock

26a

26c

BRES/

Buffered Reset

BD71

Buffered Data Bit 7

27a

27c

BD61

Buffered Data Bit 6

GND

Ground

28a

28c

BD51

Buffered Data Bit 5

BD41

Buffered Data Bit 4

29a

29c

B031

Buffered Data Bit 3

BD21

Buffered Data Bit 2

30a

30e

GNO

Ground

BOll

Buffered Data Bit 1

31a

31c

BDOI

Buffered Data Bit

+5V

+5 Vdc

32a

32c

GNO

Ground

+5V

+5 Vdc (See Note)

Ya

Yc

+5V

+5 Vdc (See Note)

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, Wc, Xa, Xc, Ya, Yc, Za and Zc are not used on Eurocard version •
• Not used on this module.

a

Not Connected (See Note)

•

SBC Module Physical and Electrical Characteristics
Value

Characteristic
Physical characteristics (See Notes)
Width
Length
Height
Weight

Edge Connector Version
3.9 in. (100 mm)
6.5 in. (164 mm)
0.56 in. (14 mm)
5.3 oz. (150 g)

Environment
Operating Temperature
Storage Temperature
Relative Humidity

Eurocard Version
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
5.6 oz. (160 g)

OOC to 70 0 C
0
0
-40 C to +85 C
0% to 85% (without condensation)
+5 Vdc ±5%. 0.75 A (3.5 W) - Typical
1.2 A (6.0 W) - Maximum

Power Requirements
RM 65 Bus Interface
Edge Connector Version
Eurocard Connector Version

72-pin edge connector (0.100 in. centers)
64·pin plug (0.100 in. centers) per DIN 41612 (Row B not installed)

I/O Connector

40'pin 3M mass termination (0.100 in. centers)

RESET Switch Connector

2 vertical pins (0.3 in. high) on 0.200 in. center

NOTES:

•

1. The height includes the maxirr.um values for component height above the board surface (004 in. for populated modules). printed circuit board
thickness (0.062 in.!. and pin extension through the bottom of the module (0.1 in.!.
2. The length does not include extensions beyond the edge of the module due to connectors or the module ejector.
3. The Eurocard dimensions conform to DIN 41612.

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EUROCARD VERSION

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--~

--l!--EUROCONNECTOR
EXTENSION
EUROCARD CONNECTOR

EDGE CONNECTOR
COMPONENT AREA

r----\-----,

COMPONENT AREA

~----~- -----,

HEIGHT

r

Module Dimensions

PART NUMBER

RM65-S101 (E)

RM 65
DATA SHEET
FLOPPY DISK CONTROLLER (FDe) MODULE
RM 65

FEATURES

The RM 65 product line is designed for OEM and end user microcomputer applications requiring state-of-the-art performance,
compact size, modular design and low cost. Software for RM 65
systems can be developed in R6500 Assembly Language, PL/65,
BASIC and FORTH. Both BASIC and FORTH are available in
ROM and can be incorporated into the user's system.

•
•
•
•
•

The RM 65 product line uses a motherboard interconnect concept
and accepts any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 12SK bytes, high immunity to electrical noise and includes growth provisions for user functions.
A selection of card cages provides packaging flexibility. RM 65
products may also be used with Rockwell's AIM 65 Microcomputer for product development and for a broad variety of portable
or desktop microcomputer ap~lications.

•
•
•
•
•
•
•

PRODUCT OVERVIEW
The RM 65 Floppy Disk Controller (FDC) Module controls up
to four standard (S") or mini- (5%") floppy disk drives, single or
double sided, soft sectored with either single density (FM) or
double density IMFM) format. Software control of media density allows single or double density disks to be used in any connected drives.
Two DIP headers configure the FDC to interface with either
standard or mini-floppy disk drives. An on-board jumper selects
single or double sided drives and a switch disables on-board ROM.
The FDC directly interfaces to most popular drives with only
switch and/or header changes.
Bank Select and Bank Select
Enable switches allow the FDC module to be dedicated to one of
two 65K memory banks or assigned common to both banks. The
FDC module I/O can be assigned to any pa!}€l (256 bytes) using
a standard PROM if the ROM is deselected.

•
•
•

Compact size - about 4" x 6%" (100 mm x 160 mrn)
Edge Connector and Eurocard versions
RM 65 Bus compatible
Buffered address, data and control lines
Supports single or double sided, standard or mini-floppy disk
drives
Controls up to four disk drives
Interfaces directly to Shugart SA-S50 or SA-450 disk drives,
with \lser oPtions for other popular floppy disk drives
Supports single-density IBM 3740 (FM) or double-density
IBM System 34 (MFM) formats
DMA data transfer capability
Supports interrupt-driven or polled operation
Bipolar PROM Base Address decoding
Switches or jumpers for
- Bank Selection to one or two banks
- Double or Single sided operation
- Select or deselect ROM·
- Module disable
On-board header configures I/O for S" or 5Y." drive interface
On-board Program ROM containing disk utility and file management functions
Fully assembled,-tested and warranted.

'TI

r-

o

""-43 (Remex & MFE or equivalents)
N.C.
N.C.
Track >43 (Caldisk or equivalents)
N.C.
N.C.
2nd Side Select
N.C.
Head Load
Index
Drive Ready
N.C.
Drive Select #1
Drive Select #2
Drive Select #3
Drive Select #4
Direction In
Step Pulse
Write Data
Write Gate
Track Zero
Write Protected
Read Data
N.C.
N.C.

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

N.C.
N.C.
Drive Select #4
Index
Drive Select #1
Drive Select #2
Drive Select #3
Motor On
Direction In
Step Pulse
Write Data
Write Gate
Track Zero
Write Protected
Read Data
2nd Side Select
N.C.

NOTES:

1. All odd numbered pins are GND.
2. Pin 1 of the 34-pin mini-floppy disk drive interface cable connector should be keyed to pin 17 of the FDC module I/O connector.

::

.
~

RM 65 Bus Pin Assignments
Top (Component Side)

Bottom (Solder Side)

•

Signal
Mnemonic

Signal
Mnemonic

Signal Name

Pin

Pin

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

Xc

+5V

+5 Vdc (See Note)

GND

Ground

la

lc

+5V

+5 Vdc

BADRI

Buffered Bank Address

2a

2c

BA151

Buffered Address Bit 15

GND

Ground

3a

3c

BA141

Buffered Address Bit 14

BA131

Buffered Address Bit 13

4a

4c

BA121

Buffered Address Bit 12

BAlli

Buffered Address Bit 11

5a

5c

GND

Ground

BA101

Buffered Address Bit 10

6a

6c

BA91

Buffered Address Bit 9

BABI

Buffered Address Bit B

7a

7c

BA71

Buffered Address Bit 7

GND

Ground

Ba

Bc

BA61

Buffered Address Bit 6

BA51

Buffered Address Bit 5

9a

9c

BA41

Buffered Address Bit 4

BA31

Buffered Address Bit 3

lOa

10c

GND

Ground

BA21

Buffered Address Bit 2

lla

llc

BAli

BAOI

Buffered Address Bit 0

12a

12c

B~l

• Buffered Pnase 1 Clock

Ground

13a

13c

BSYNC

• Buffered Sync

14a

14c

BDR01/

Buffered DMA Request 1

15a

15c

GND

Ground

-12V/-V

GND
BSO
BRDY

"Buffered Set Overflow
Buffered Ready

Signal Name
Not Connected (See Note)

Buffered Address Bit 1

• -12 Vdc/-V

16a

16c

+12V/+V

+12Vdc

17a

17c

GND

Ground Line

lBa

lBc

BFLTI

• Buffered Bus Float

• Buffered DMA Terminate

19a

19c

B~O

• Buffered External Phase 0 Clock

• User Spare 3

20a

20c

GND

21a

21c

BDRQ2/

22a

22c

BRJW

• User Spare 1

BDMT/

BR/WI

Buffered ReadlWrite "Not"
• System Spare

• User Spare 2

Ground
Buffered DMA Request 2
• Buffered ReadlWrite
Buffered Bus Active

GND

Ground

23a

23c

BACTI

BIROI

Buffered Interrupt Request

24a

24c

BNMII

Buffered Phase 2 "Not" Clock

25a

25c

GND

Ground

26a

26c

BRESI

Buffered Reset

B~21
B~2

"Buffered Phase 2 Clock

"Buffered Non-Maskable Interrupt

BD71

Buffered Data Bit 7

27a

27c

BD61

Buffered Data Bit 6

GND

Ground

2Ba

28c

BD51

Buffered Data Bit 5

BD41

Buffered Data Bit 4

29a

29c

BD31

Buffered Data Bit 3

BD21

Buffered Data Bit 2

30a

30c

GND

Ground

BDll

Buffered Data Bit 1

31a

31c

BDOI

Buffered Data Bit 0

+5V

+5 Vdc

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

+5V

+5 Vdc (See Note)

Ya

Yc

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, Wc, Xa, Xc, Va, Yc, Za and Zc are not used on Eurocard version_
"Not used on this module

Not Connected (See Note)

Floppy Disk Controller (FDC) Module Physical and Electrical Characteristics
Characteristic

Value

Physical Characteristics (See Notes)
Width
Length
Height
Weight

Edge Connector
3.9 in. (100 mm)
6.5 in. (164 mml
0.56 in. (14 mml
4.8 oz. (135 gl

Environment
Operating Temperature
Storage Temperature
Relative Humidity

Eurocard
3.9 in. (100 mml
6.3 in. (160 mm)
0.56 in. (14 mm)
5.2 oz. (145 gl

OOC to 70 0 C
0

0

-40 C to +85 C
0% to 85% (Without condensation)

Power Requirements

+5 Vdc ±.5% @ 600 m A - Typical
900 mA - Maximum
+12 Vdc ±.5% @ 60 mA - Typical
100 mA - Maximum

RM 65 Bus Interface
Edge Connector Version
Eurocard Version

72-pin edge connector (0.100 in. centers)
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)

I/O Interface

50-pin mass terminated connector (0.100 in. centers)
Mates with I&B/Ansley Part No. 609-5001 M or equivalent

NOTES:
1. The height includes the maximum values for component height above the board surface (0.4 in. for populated modules), printed circuit board
thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.).
2. The length does not include the added extension due to the module ejector.
3. The Eurocard dimensions conform to DIN 41612.

•
,

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EUROCARD CONNECTOR

EDGE CONNECTOR
COMPONENT AREA

r - - - _\ - - - - --,

Module Dimensions

--tJ"

I--EUROCONNECTOR
EXTENSION

I

=-

. :: :-

•

PART NUMBER

'1'

RM65-5451 (E)

RM 65
DATA SHEET

Rockwell

ASYNCHRONOUS COMMUNICATIONS INTERFACE
ADAPTER (ACIA) MODULE
RM65

FEATURES

The RM 65 product line is designed for OEM and end user micro·
computer applications requiring state-of·the-art performance,
compact size, modular design and low cost. Software for RM 65
systems can be developed in R6500 Assembly language, Pl/65,
BASIC and FORTH. Both BASIC and FORTH are available in
ROM and can be incorporated into the user's syste~.
The RM 65 product line uses a motherboard interconnect concept
and accepts any card in any slot. The 64·line RM 65 Bus offers
memory addressing up to 128K bytes, high immunity to electrical
nOise and includes growth provisions for user functions. A selec·
tion of card cages provides packaging flexibility. RM 65 products
may also be used with Rockwell's AIM 65 Microcomputer for
. product development and for a broad variety of portable or desk·
top microcomputer applications.

ORDERING INFORMATION
The ACIA. Module is available in an Edge Connector version
(AM65·54511 and a Eurocard version (AM65·5451 EI.

IC>Roct

......

~ ~ 'u.~.o

I

',","0'

--p,

:

--l ~EUROCONNECTOR
EXTENSION

,

EUROCARD CONNECTOR

EDGE CONNECTOR
COMPONENT AREA

Lr----\-----,

HEIGHT

Module Dimensions

PART NUMBER

RM65-7102(E)

'1'

RM 65
DATA SHEET

Rockwell

IEEE-488 BUS INTERFACE MODULE
RM 65
The RM 65 product line is designed for OEM and end user microcomputer applications requiring state-of-the-art performance;
compact size, modular design and low cost_ Software for RM 65
systems can be developed in R6500 Assembly Language, PL/65,
BASIC and FORTH. Both BASIC and FORTH are available in
ROM and can be incorporated into the user's system.
The RM 65 product line uses a motherboard interconnect concept
and accepts any card in any slot. The 64-line RM 65 Bus offers
memory addressing up to 128K bytes, high immunity to electrical noise and includes growth provisions for user functions.
A selection of card cages provides packaging flexibility. RM 65
products may also be used with Rockwell's AIM 65 Microcomputer for product development and for a broad variety of portable
or desktop microcomputer applications.

PRODUCT OVERVI EW
The RM 65 IEEE-488 Bus Interface Module connects an AIM 65
or AM 65 SBC based system to the IEEE-488 General Purpose
Interface Bus (G~IBI. Complete controller, talker' and listener
functions, as defined in the I EEE-488, 1978 Standard, are implemented. The module also supports extended addressing and multiple bus ~ontrollers. On·board ROM firmware implements all
12 functions specified by the interface standard. Features not
defined in the standard, but also supported, include manual talk
or listen disable, dual primary addressing, and an external trigger
line. Switches select the Device Talk/Listen Address, Enable Dual
Primary Addressing Mode, Disable Talk, Disable Listen, and System Controller mode. The bus interface transceivers meet the
electrical specifications of the I EEE-488 interface standard. An
8-inch ribbon cable mates the IEEE-488 module to the IEEE-488
. bus with a standard 24'pin connector.

Eurocard Version
RM65·7102E

©RockwelllnternatlonaJ Corporatlof') 1981
All Rights Reserved
Printed In U.S.A

Standard RM 65 features include switches to dedicate the module
to one' of two 6SK byte memory banks, or to assign it common to
both banks, A jumper allows the on-board ROM to be' enabled or
disabled. Base address select switches allow the module I/O
address to be assigned to any page (256 bytes) if the ROM is
disabled.
.

ORDERING INFORMATION
The IEEE-488 Bus Interface Module is available in an Edge Connector version (RM65-7102) and a Eurocard version ,(RM657102EI.

FEATURES
•
•
•
•
•
•
•
•
•

•
•
•
•
•

Compact size - about 4" x 6%" (100 mm x 160 mm)
Edge Connector and Eurocard versions
RM 65 Bus compatible
Buffered address, data and control lioes
Listen, talk, and controller functions
IEEE-488, 1978 standard fully implemented
Uses TI 9914 GPIB Adapter device
On-board ROM contains bus protocol and utility firmware
Switches for
Device Talk/Listen Address
- Disable Talk
Disable Listen
Enable Dual Primary Addressing mode
System Controller
Base Address to page boundary for I/O
Bank Selection to one or both 6SK banks
Jumper for ROM enable/disable
LEOs show current address register cOl1tents
Supports DMA data transfers
+5V operation
Fully assembled, tested and warranted

Edge Connector Version
RM65·7102
Specifications subject to

change without notice

Document No_ AMASS N13
A.v. 1, March 1981

,.

..
,

I

FUNCTIONAL DESCRIPTION
The Data Transceivers invert and transfer 8-bits of parallel data between
the IEEE-4BB Bus Interface Module and the RM 65 bus, based on
data direction signals from the Base Address Decoder_
The Address Buffers invert and transfer the 16-bit parallel address lines
from the RM 65 bus to the Base Address Decoders, to the R2332
ROM and to the GPIB Adapter.
The Control Buffers invert and transfer phase 2 clock, reset, and read/
write control signals from the RM 65 bus onto the module. The
interrupt request is buffered and driven onto the RM 65 bus.
The Bank Select Control circuit detects when the module's assigned
memory bank is addressed by comparing the bank address signal from
the RM 65 bus to the Bank Select and Bank Select Enable switches.
The Bank Select Enable switch allows the board to reside in common
memory (both Bank 0 and Bank 1) or only in the Bank set by the
Bank Select switch (either Bank 0 or Bank 1).
The DMA Control circuit allows DMA requests from the TI 9914 GPIB
Adapter device to be driven on the RM 65 bus or disabled under program control. This line is jumper selectable for either of two DMA
request lines on the RM 65 bus.

•
.

--

The Base Address Decoder compares the eight most significant address
lines to the eight Base Address switches. The ROM Disable jumper
allows the module to be active in a 4K block when enabled Or active
in a page (256 locations) when disabled. When an address for the
selected bank matches the four most significant switches and the ROM
is enabled, the Data Transceivers are enabled and the bus active signal
is generated. When this address also matches the four least significant
switches the GPIB Adapter and I/O are selected. When there is no
match on the four least significant switches, the ROM is selected.
When the GPIB Adapter and I/O are selected, the four least significant
address lines, phase 2 clocks, and read/write control lines are used to
derive register selects for the GPIB Adapter, device selects for the
GPIB Status Latch, GPIB Sense Buffers, System Controller Select, and
~

DMA Control Circuits. The read/write control lines also determine the
direction for the Data Transceivers.
The TMS 9914 GPIB Adapter device provides hardware control of the
IEEE-4BB bus interface, using firmware subroutines provided in ROM.
All bus interface lines are buffered by the GPIB Data and Control
Transceivers, to conform to the electrical specifications of the IEEE4BB Standard. These lines are brought out through a cable to a standard IEEE-4BB connector. An additional connector provides an external
trigger output not defined by the I EEE-4BB Standard.
The System Controller Select circuit allows manual selection of System
Controller capabilities in mUltiple controller configurations.
The GPIB Sense Buffer allows the GPIB Sense Switches to be read for
Device Talk/Listen Address, Talk or Listen Disable, and Dual Primary
Address Mode selection. The GPIB Status Latch latches the positions
of the GPIB Sense Switches and displays them on the GPIB Status
Indicators. This allows a visual verification of the Device Talk/Listen
Address and Operating modes.
On-Board Program ROM Firmware
The Program ROM firmware completely supports all 12 Bus functions
described in the IEEE-4BB, 197B Standard, as well as features of the
TMS 9914 GPIB Adapter device not defined in the Standard. These
utility functions make both the Bus protocol and the GPI B Adapter
device transparent to the programmer. The firmware, organized as
subroutines, is linked to the user program through a jump table. Many
of these routines are interrupt-driven, to minimize the processor time
in servicing the module. User-alterable vectors and parameters are
located in RAM, to allow custom appl ications. Output data or commands for the Bus are handled as tables, easing the set-up and transfer
of information. Extensive error checking by the utility subroutines
allow resident or user-provided error handling routines to ensure proper
operation of the module, the IEEE-4BB Bus and status of data transfer.
Two self-test routines verify proper module operation.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...,

~1~T!~ENRAl

IEEE-488 Bus Interface Module Block Diagram
External Trigger Pin Assignments
Pin

Signal Mnemonic

Signal Name

1

TRIG
GND

Trigger Out
Ground

2

Input/Output

a

IEEE-488 Bus Interface Connector Pin Assignments

Pin

Signal
Mnemonic

10
11
12

0101
DI02
0103
0104 .
EOI
DAV
NRFD
NDAC
IFC
SRQ
ATN
SHIELD

Signal Name
Data Input/Output 1
Data Input/Output 2
Data Input/Output 3
Data Input/Output 4
End or Identify
Data Available
Not Ready for Data
Not Data Accepted
I nterface Clear

Service Request
Attention
Ground

Signal

Input!
Output

Pin

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/A

13
14
lS
16
17
18
19
20
21
22
23
24

Mnemonic

Inputl
Output

Signal Name
Data Input/Output S
Data Input/Output 6
Data Input/Output 7
Data Input/Output 8
Remote Enable

DIOS
DI06
DI07
DI08
REN
GND
GND
GND
GND
GND
GND
GND

I/O
I/O
I/O
I/O
I/O
N/A
N/A
N/A
N/A
N/A
N/A
N/A

Ground
Ground
Ground
Ground

Ground
Ground
Logic Ground

RM 65 Bus Pin Assignments
Bottom (Solder Side)

Top (Component Side)
Signal

Signal

Mnemonic

Signal Name

Signal Name

Pin

Pin

Not Connected ISee Note!

W.

Wc

+SV

+5 Vc1c Lone ISee Notel

X.

Xc

+SV

+5 Vdc ISee Note!

GND

Ground

la

lc

+SV

+S Vdc

BADR/

Buffered Bank Address

2.

2c

BA1SI

Buffered Address B,t IS

GND

Ground

3.

3c

BA141

Buffered Address Bit 14

BA13/

Buffered Address Bit 13

4.

4c

BA121

Buffered Address Bit 12

BAlli

Bullered Address B,t 11

Sa

50

GND

Ground

BAlO/

Bullered Address B,t 10

6a

6c

BA91

8uffered Address B,t 9

BA81

Buffered Address B,t 8

7.

BA71

Buffered Address 8,t 7

GND

Ground

8.

8c

BAGI

Buffered Address B't 6

BAS/

Bullered Address B,t S

9.

9c

BA41

Buffered Address Bit 4

BA3/

Bullered Address B,t 3

lOa

10c

GNO

Ground

BA21

Buffered Address Bit 2

I I.

11c

BAli

BAO/

Bullered Address B't 0

12.

12c

Bgl

• Buffered Phase 1 Clock

Ground

• Buffered Sync

Mnemonic

Not Connected ISee Note!

I

Buffered Address Bit 1

13a

13c

BSYNC

BSO

• Buffered Set Overflow

14a

14c

BOR01/

Buffered OMA Request 1

BRDY

• Buffered Ready

lS.

150

GNO

Ground

• User Spare 1

16a

16c

·12V/·V

+12V/+V

• +12 Vdc/+V

17.

17c

18a

18c

BFL TI

• Buffered Bus Float

• Buffered DMA Terminate

19a

19c

B~O

• Buffered External Phase

• User Spare 3

20a

20c

GNO

Ground

21a

21c

BOR02/

Buffered OMA Request 2

22a

22c

BR/W

Buffered Read/W"te

BACTI

Buffered Bus Active

GND

GND
BDMT/

BR/WI

Ground

Buffered Read/W"te "Not"

• System Spare

• -12 Vdcl·V
• User Spare 2

GND

Ground

23a

23c

BIRO/

Buffered Interrupt Request

24a

24c

BNMII

B/!21
B/!2

Buffered Phase 2 "Not" Clock

2Sa

250

GNO

Ground

Bullered Phase 2 Clock

26a

26c

BRESI

8uffered Reset

BD7I

Buffered Data B,t 7

27a

27c

B061

8uffered Data B,t 6

GND

Ground

28a

28c

BOSI

Buffered Data B,t S

BD41

Buffered Data B,t 4

29a

29c

B031

Buffered Data Bn 3

BD2/

Buffered Data B,t 2

30a

30c

GNO

Ground

B01/

Buffered O.t. B,t 1

31a

31c

BOO/

Buffered Dat. B,t 0

+SV

+S Vdc

32a

32c

GNO

Ground

+SV

+S Vdc (See Note!

Ya

Yc

Not Connected ISee Note!

Za

Zc

NOTE
Pins Wa, Wc# Xa, Xc, Va, Ye. Za and Zc are not used on Eurocard version .
• Not used on this module.

+SV

..

0 Clock

• Buffered Non·Maskable Interrupt

+S Vdc (See Note!
Not Connected (See Note!

I EEE-488 Bus Interface Module Physical and Electrical Characteristics
Value

Characteristic
Physical Characteristics (See Notes)
Width
Length
Height
Weight

Edge Connector
3.9 in. (100 mm)
6.5 in. (164 mm)
0.56 in. (14 mm)
4.6 oz. (130 g)

Environment
Operating Temperature
Storage Temperature
Relative Humidity

OOC to 70 0 C
0
0
-40 C to +85 C
0% to 85% (without condensation)

Power Requirements

+5 Vdc ±.5% @ 0.65A (3.25W) - Typical
1.0A

•

Eurocard
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
5.00z.(140g)

(5.25 W) - Maximum

RM 65 Bus Interface
Edge Connector Version
Eu rocard Version

72'pin edge connector (0.100 in. centers)
64-pin plug (0.100 in. centers) per DIN 41612 (Row b not installed)

Module
I/O Interface
Cable Receptacle
Trigger Connector

26-pin mass terminated (0.100 in. centers)
Two vertical wire wrap pins (0.3 in. high On 0.200 in. centers)

IEEE-488 Bus Interface Cable
IEEE-488 Bus Connector

24-pin mass terminated (2.16 mm centers) with metric thread lock
screws (Amphenol 57 Or equivalent)
26-pin mass terminated (0.100 in. centers)

MOdule Connector
Cable Length
Type
Number of Conductors
Wire Size

8 inches
Flat ribbon
24
#28 AWG

NOTES:
1. The height includes the maximum values for component height above the board surface (0.4 in. for populated modules), printed circuit
board thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.1.
2. The length does not include the added extension due to the module ejector
3. The Eurocard dimensions conform to DIN 41612.

r - - - ~;~;r;.M)

----j

~~~~NEGRBOARD

r---~1~;'!;,.)

----j

~~~~~';.80ARD

~"'""lll''''''''' r--"'''"1-l7'''''~U

:: r
r
(c?~~o'''~ ''O".'"''~ U 0~~~

B.DIN

::'

B.DIN.

..

.~
-

RIB~ON CABLE

IEEE-488

BUS CONNECTOR

RECE.TACL COM~O:: A_\ ____ .,

HEF-

~

j

::

'""~""o.'""O"

VIEEE..-88

EDGE CONNECTOR

:

BUS CONNECTOR

~ ~EEUXRTEOCNSO,NONNECTOR

EUROCARD CONNECTOR
RIBBON CABLE

"ECE'TA~ CO:O~E= ~\. ___

HEf-

Module Dimensions

-"1

PART NUMBER

RM65-3108(E)

RM 65
DATA SHEET
8K STATIC RAM MODULE
RM 65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-the-art
performance, compact size, mpdular design and low cost.
Software for RM 65 system, can be developed in R6500
Assembly Language, PL/65, BASIC and FORTH. Both
BASIC and FORTH are available in ROM and (;an be
incorporated into the user's system.

•
•
•
•
•
•
•
•
•
•

The RM 65 product line uses a motherboard interconnect
concept and accepts any card in any slot. The 64-line RM
65 Bus offers memory addressing up to 128K bytes, high
immunity to electrical noise and includes growth pro·
visions for user functions. A selection of card cages
provides packaging flexibility. RM 65 products may also
be used with Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable
or desktop microcomputer applications.

ORDERING INFORMATION
The 8K Static RAM Module is available in an Edge Connector version (RM65-3108) and a Eurocard version
(RM65-3108E). These modules may also be ordered
without the RAM devices installed, as part numbers
RM65-3108N and RM65-3108NE, respectively_

Compact size - about 4" x 6%" (100 mm x 160 mm)
Edge Connector and Eurocard versions
RM 65 Bus compatible
Buffered address, data and control lines
Two separately addressable 4K byte sections
16 socketed 2114 static RAM devices
Write·protect switch for each memory section
Bank Select and Enable switches
+5V operation
Fully assembled, tested and warranted.

co

"en
~

:::1
o

PRODUCT OVERVIEW
The RM 65 8K Static RAM Module contains 8192 8-bit
bytes of Random Access Memory (RAM), in sixteen
2114 static RAM devices. The memory is arranged as two
separately addressable 4K memory sections. The starting
address of each 4K section is. selectable by on-board
address switches. A Bank Select switch allows the RAM
module to be assigned to one of two 64K memory banks.

:c
l>

s:
s:

o
c
c:
r-

m

Eurocard VersionRM65·3108E

iClRockwelllnternauonal Corporation 1981
All Rights Reserved
Pronted in U.S.A.

Edge Connector Version
RM65·3108
SpeCifications subject to
change without notice

Document No. RMA65 N01
Rev. 1, March 1981

FUNCTIONAL DESCRIPTION
8K bytes of static 2114 RAM are divided into two separately address·
able 4K blocks. Two devices per 1 K bytes are required since each
device is 1 K x 4 bits.
The Data Transceivers invert and transfer 8·bits of parallel data between
the RAM devices and the RM 65 Bus, based on data direction signals
from the Data Transceiver Control Circuit.
The Address Buffers invert and transfer 16 address bits from the
RM 65 Bus to the RAM devices, to the Base Address Decoders and to
the Chip Select Decoder.

Two Base Address Decoders detect when either 4K RAM Section (lor
2) is addressed, by comparing the address lines to Base Address Select
switch settings. When a match occurs, an enable signal is sent to the
Chip Select Decoder.
The Chip Select Decoder uses outputs from the Bank Select Control
circuit, the Base Address Decoders, and the PROM/ROM size jumpers
as well as address lines A 11 and Al 0 to generate one of eight chip select
lines to the RAM devices. A signal indicating that a chip select line is
active is also sent to the Write Control and Data Transceiver Control
circuits.

The Control Buffers invert and transfer phase 2 ciock and read/write
control signals from the RM 65 Bus onto the RAM module, and drive
the bus active signal onto the RM 65 Bus.

The Write Control circuit generates the write enable signals to the RAM
devices and to the Data Transceiver Control circuit. If the correspond·
ing write protect switch is off, the write enable signal is activated. If
the Write Protect switch is on, the Data Transceivers are disabled.

The Bank Select Controller detects when the RAM module's assigned
memory bank is addressed, by comparing the bank address signal from
the RM 65 Bus to the settings of the Bank Select and Bank Select
Enable switches. If the addressed bank is the same as the selected
memory bank, an enable signal is sent to the Chip Select Decoder.

The Data Transceiver Control circuit determines whether a valid read
or write operation is in progress, and provides transcejver enable and
data direction signals to the Data Transceivers. The Data Transceivers
are enabled if both the bank address and the address lines correspond
to the selected bank and a selected base address, respectively.

RM65
BUS CONNECTOR

DATA
DATA
TRANSCEIVER . .+-......,~~
CONTROL

RIW
WRITE
CONTROL
BUS
ACTIVE
TIMING AND
CONTROL

~~~~CT

1-_ _ _ _--.1-.:......8......~

DECODER
BANK
ADDRESS

BANK
SELECT
CONTROL

10

ADDRESS

8K Static RAM Module Block Diagram

TWO
4K

~:C~IONS

RM 65 Bus Pin Assignments
Top (Component Side)

Bottom (Solder Side)
Signal
Mnemonic

Signal Name

Input/
Output

Pin

Pin

Signal
Mnemonic

Signal Name

Input/
Output

Not Connected (See Note)

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

Xc

+5V

+5 Vdc (See Note)

GND

Ground

BADR/

Buffered Bank Address

GND

Ground

BA13/

Buffered Address Bit 13

BAll/

la

lc

+5V

+5 Vdc

2a

2c

BAI5/

Buffered Address Bit 15

I

3a

3c

BAI4/

Buffered Address Bit 14

I

I

4a

4c

BA12/

Buffered Address Bit 12

I

Buffered Address Bit 11

I

5a

5c

GND

Ground

BA10/

Buffered Address Bit 10

I

6a

6c

BA9/

Buffered Address Bit 9

I

BA8/

Buffered Address Bit 8

I

7a

7c

BA7/

Buffered Address Bit 7

I

GND

Ground

8a

8c

BA6/

Buffered Address Bit 6

I

BA5/

Buffered Address Bit 5

I

9a

9c

BA4/

Buffered Address Bit 4

I

BA3/

Buffered Address Bit 3

I

lOa

10c

GND

Ground

BA2/

Buffered Address Bit 2

I

11a

11c

BAI/

BAO/

Buffered Address Bit 0

I

12a

12c

B¢1

I

Buffered Address Bit 1

13a

13c

BSYNC

·Buffered Sync

BSO

*Buffered Set Overflow

14a

14c

BOROI/

·Buffered OMA Request 1

BROY

*Buffered Ready

15a

15c

GND

* User Spare 1

16a

16c

-12V/-V

*+12 Vdc/+V

17a

17c

Ground Line

18a

18c

BFLT/

·Buffered Bus Float

*Buffered DMA Terminate

19a

19c

B¢O

·Buffered External Phase 0 Clock

• User Spare 3

20a

20c

GND

21a

21c

BOR02/

GND

+12V/+V
GND
BOMT/

BR/Wt

Ground

Buffered Read/Write "Not"

I

·System Spare
GND
BIRO/
B¢2/
B¢2

Ground
• Buffered I nterrupt Request
Buffered Phase 2 "Not" Clock

I

·Buffered Phase 2 Clock
I/O

I

•

• Buffered Phase 1 Cloc k

Ground

,

·-12 Vdc/-V
·User Spare 2

Ground
·Buffered DMA Request 2

22a

22c

BR/W

Buffered Read/Write

I

23a

23c

BACT/

Buffered Bus Active

0

24a

24c

BNMI/

25a

25c

GND

26a

26c

BRES/

27a

27c

B06/

Buffered Data Bit 6

I/O

28a

28c

B05/

Buffered Data Bit 5

I/O
I/O

·Buffered Non·Maskable Interrupt
Ground
·Buffered Reset

B07/

Buffered Data Bit 7

GNO

Ground

BD4/

Buffered Data Bit 4

I/O

29a

29c

BD3/

Buffered Data Bit 3

B02/

Buffered Data Bit 2

I/O

30a

30c

GND

Ground

I/O

31a

31c

BDO/

Buffered Data Bit 0

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

BDI/

Buffered Data Bit 1

+5V

+5 Vdc

+5V

+5 Vdc (See Note)

Ya

Yc

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, Wc, Xa, Xc, Ya, Yc, Za, Zc are not used on the Eurocard version .
• Not used on this module.

Not Connected (See Note)

I/O

I

8K Static RAM Module Physical and Electrical Characteristics
Characteristic

Value

Physical Characteristics (See Notes)
Edge Connector
3.9 in. (100 mm)
6.5 in. (164 mm)
0.56 in. (14 mm)
4.90z. (135g)

Width
Length
Height
Weight
Environment
Operating Temperature
Storage Temperature
Relative Humidity

Eurocard
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
5.3 oz. (145 g)

0
OOC to 70 C
0
0
_40 C to +85 C
0% to 85% (Without condensation)

Power Requirements

+5 Vdc ±5% @ 1.0A (5.0W) - Typical
1.9A (9.5W) - Maximum

Access Time

450 ns - Maximum

RM 65 Bus Interface
Edge Connector Version
Eurocard Version

72'pin edge connector (0.100 in centers)
64-pin plug (0.100 in centers) per
DIN 41612 (Row b not installed)

NOTES:

•

1. The height includes the maximum values for component height above the board surface (0.4 in. for populated modules),
printed circuit board thickness (0.062 in.), and pin extension through the bottom of the module 10.1 in.).
2. The length does not include the added extension due to the module ejector.
3. The Eurocard dimensions conform to DIN 41612.

r-~i~~~M)-----1 ~~~~NE~BOARD

~"NG'"lll

r l?

WLIDTH

:-n
EDGE CONNECTOR VERSION

I

I(

I

I

:::

I
I

r

r-~i~~~M)-1 ~~~~NE~BOARD

r-"NG'"i

",C","C"

I JANDRECEPTACLE

~ --::

)Y

::

i:
"

WLIDTH

EUROCARD VERSION

I'
II

"
::

'---___________~ ~_~

..... --tJ

~ ~EUROCONNECTOR
EXTENSION
EUROCARD CONNECTOR

EDGE CONNECTOR

LCOMPONENT A \

.-

HEIGHT

I

Module Dimensions

-

-

-

-

--\

SJ

PART NUMBER

RM65-3132(E)

'1'

RM 65
DATA SHEET

Rockwell
,

.

32K DYNAMIC RAM MODULE
RM 65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-the-art
performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PL/65, BASIC and FORTH.
Both
BASIC and FORTH are available in ROM and can be
incorporated into the user's system.
The RM 65 product line uses a motherboard interconnect
concept and accepts any card in any slot. The 64-line RM
65 Bus offers memory addressing up to 128K bytes, high
immunitY to electrical noise and includes growth provisions for user functions.
A selection of card cages
provides packaging flexibility.
RM 65 products may also
be used with
Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable
or desktop microcomputer applications.

PRODUCT OVERVIEW
The 32K Dynamic RAM module provides 32K bytes of read/write
memory using 16 16K bit x 1 dynamic RAM (DRAM) devices.
Two bank select switches allow the board to be dedicated to
either one of two 65K Banks, or to be assigned common to both
banks. A 24-pin DIP header allows each of the eight 4K sections
to be independently mapped into any 4K block of the selected
65K bank. The independent addressing of blocks provides flexibility with system Q1emory maps. An on-board switch allows the
entire board to be write-protected.

a
a
a
a
a
a
a
a
a
a
a

Compact size - about 4" x 6%" (100 mm x 160 mm)
Edge connector or Eurocard Versions
RM 65 bus compatible
Buffered data, address, and control lines
Internal Refresh controller is completely transparent to the
Microflex 65 bus
On-board switch allows write protection
Base Address Header allows each 4K memory section to be
assigned to any 4K block as a selected bank
Bank select switches allow the entire board to be mapped into
either or both 65K banks
On-board DC-DC converter for -5 volt power supply
Requires +5 and +12 volt power from the RM 65 bus
Fully assembled, tested, and warranted

I

W
N

"C
-<

:2

ORDERING INFORMATION
The 32K Dynamic RAM is available in an Edge Connector version (RM65-3132) and a Eurocard version (RM65-3132El. These
modules may also be ordered without the RAM devices installed,
as part numbers RM65-3132N and RM65-3132NE, respectively.

»
~

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:::D

»

s:
s:

All refreshing of the dynamic RAM chips is automatic and completely transparent to the RM 65 Bus, thus providing low power
performance at no loss of bus speed.

0

c

C

r-

m

Eurocard Version

Edge Connector Version

RM65-3132E

RM65·3132

Rockwelllnternat1ona.1 Corporation 1981

All RIghts Reserved
Pronted in U.S.A.

Specifications subject to
change without notice

Documant No. RMA65 N11
Rav. 1, March 1981

•
.

~ ~

I

FUNCTIONAL DESCRIPTION
The Data Transceivers invert and transfer 8-bit parallel data between
the selected DRAMs to the RM 65 bus. During a read operation,
data from the DRAMs are latched and driven by the transceivers onto
the RM 65 bus. During a write operation, data from the RM 65 bus
drives the DRAMs. The transceivers are disabled when the module is
not addressed.
The Address Buffers invert and transfer 16-bit parallel address lines
from the RM 65 bus into th" DRAM module.
The Bank Select Control circuit detects when the DRAM module's
assigned memory bank is addressed by comparing the bank address
signal from the RM 65 bus to the Bank Select and Bank Select Enable
switches. The Bank Select Enable switch allows the board to reside
in common memory (both Bank 0 and Bank 1) or only in the Bank
set by the Bank Select switch (either Bank 0 or Bank 1)_
The Control Buffers buffer the control and timing signals used from the
RM 65 bus.
The DRAM devices require 3 voltages. Two of these (+5 and +12 volts)
are available directly from the RM 65 bus. The third voltage (-5 volts)
is generated on board with a DC/DC converter_

•

The Address Decoder uses the four MSB address lines to decode and
enable one of 16 lines, each of which correspond to 4K blocks. The
Base Address Selection Jumpers are placed in a 28 pin socket which
consists of 16 lines from the Address Decoder, four lines from +5 volts,
and 8 lines to the Base Address Encoder_ The Base Address Selection
is made by connecting each of the eight encoder inputs to anyone of
the 16 decoder outputs or to +5 volts. This allows each 4K block to

be addressed anywhere in the selected 65K memory bank or disabled_ .
The Base Address Encoder produces a 3 bit code for the enabled line
and an additional signal for any line active (Board Select!. The 3 bit
code from the encoder becomes the 3 MSB address bits for the Memory
Address Multiplexer. The Board Select line and a valid Bank Select
signal are used to enable the Memory Controller and Data Transceivers,
as well as create a Data Bus Active Signal.
The Write Control logic uses the Write Protect switch and the Read/
Write line to enable writing into the DRAMs. If the Write Protect
switch is off, the Read/Write signal is transferred directly to the Memory Controller. If the Write Protect switch is on, the Memory Controller forces a read operation so that the contents of the DRAMs
will not be altered.
The Timing Control generates all the clocks required by the Memory
Controller, Memory Address Multiplexer, and the Refresh Clock. The
Refresh Clock generates a refresh cycle for every seven RM 65 clock
cycles.
The Memory Controller uses the clocks derived in the timing control
to sequence the signals to the DRAM devices. During normal read or
write cycles, the Memory Controller allows Row Address, then Column
Address information to be applied to the addressed DRAMs and generates the read/write signal. When a refresh is required, the timing is
controlled so that the refresh is transparent to the RM 65 bus.
The Memory Address Multiplexer and Refresh Counter multiplexes
Row, Column, or Refresh Addresses onto the DRAM address lines in
response to the Memory Controller_ There is also a Refresh Counter
whiCh is incremented by the Refresh Clock_

RM65
BUS CONNECTOR

OATA

ADDRESS
DYNAMIC
RAM
DEVICES
(161

32K Dynamic RAM Block Diagram

I

RM 65 Bus Pin Assignments
Top (Component Side)

Bottom (Solder Side)

Signal
Mnemonic

Signal
Mnemonic

Signal Name

Pin

Pin

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

XC

+5V

+5 Vdc (See Note)

GND

Ground

la

lc

+5V

+5 Vdc

BADRI

Buffered Bank Address

2a

2c

BA151

Buffered Address Bit 15

GND

Ground

3a

3c

BA141

Buffered Address Bit 14

BA131

Buffered Address Bit 13

4a

4c

BA121

Buffered Address Bit 12

BAllI

Buffered Address Bit 11

5a

5c

GND

Ground

BAlOl

Buffered Address Bit 10

6a

6c

BA91

Buffered Address Bit 9

BA81

Buffered Address Bit 8

7a

7c

BA71

Buffered Address Bit 7

GND

Ground

8a

8c

BA61

Buffered Address Bit 6

BA51

Buffered Address Bit 5

9a

9c

BA41

Buffered Address Bit 4

BA31

Buffered Address Bit 3

lOa

10c

GND

Ground

BA21

Buffered Address Bit 2

l1a

llc

BAli

BAOI

Buffered Address Bit 0

12a

12c

B01

• Buffered Phase 1 Clock

Ground

Signal Name
Not Connected (See Note)

Buffered Address Bit 1

13a

13c

BSYNC

• Buffered Sync

BSO

• Buffered Set Overflow

14a

14c

BDR01/

"Buffered DMA Request 1

BRDY

• Buffered Ready

15a

15c

GND

• User Spare 1

16a

16c

-12V/-V

+12V/+V

+12 Vdc/+V

17a

17c

GND

Ground Line

18a

18c

BFLTI

" Buffered Bus Float

• Buffered DMA Terminate

19a

19c

B~O

"Buffered External Phase 0 Clock

• User Spare 3

20a

20c

GND

21a

21c

BDR02/

22a

22c

BRM

23a

23c

BACTI

24a

24c

BNMII

25a

25c

GND

26a

26c

BRESI

GND

Ground

•
,

BDMTI

BR/WI

Buffered Read/Write "Not"
• System Spare

GND
BIROI
B02/
B02

Ground
• Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
• Buffered Phase 2 Clock

• -12 Vdc/-V
• User Spare 2

Ground
"Buffered DMA Request 2
Buffered ReadlWrite
Buffered Bus Active
• Buffered Non-Maskable Interrupt
Ground
" Buffered Reset

BD71

Buffered Data Bit 7

27a

27c

BD61

Buffered Data Bit 6

GND

Ground

28a

2Sc

BD5/

Buffered Data Bit 5

BD41

Buffered Data Bit 4

29a

29c

BD31

Buffered Data Bit 3

BD21

Buffered Data Bit 2

30a

30c

GND

Ground

BD11

8uffered Data Bit 1

31a

31c

BDOI

Buffered Data Bit 0

+5V

+5 Vdc

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

Ya

Yc

+5V

+5 Vdc (See Note)

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, We, Xa, Xc, Ya, Yc, Za and Zc are not used on Eurocard version_
"Not used on this module

Not Connected (See Note)

I

32K Dynamic RAM Module Physical and Electrical Characteristics
Characteristic
Physical Characteristics Isee note)
Width
Length
Height
Weight
Environment
Operating Temperature
Storage Temperature
Relative Humidity
Power Requirements
RM 65 Bus Interface
Edge Connector Version
Eurocard Version

Value
Edge Connector Version
3.9 in. 1100 mm)
6.5 in. 1165 mm)
0.56 in. 114 mm)
4.4 oz.1125 g)

Eurocard Version
3.9 in.ll00 mm)
6.3 in. 1160 mm)
0.56 in.114 mm)
4.5 oz. 1140 g)

OOC to 70 0 C
0
0
-40 C to 85 C
0% to 85% Iwithout condensation)
+5 Vdc ±5% 1.4 A 17.0 W) - Maximum
+12 Vdc ±5% 170 mA 12.1 W) - Maximum
72·pin edge connector 10.100 in. centers)
64-pin plug 10.100 in. centers) per DIN 41612 IRow b not installed)

NOTES:
1. The height includes the maximum values for component height above the board surface 10.4 in. for populated modules), printed circuit board
thickness 10.062 in.), and pin extension through the bottom of the module 10.1 in.).
2. The length does not include extensions beyond the edge of the module due to connectors or the module ejector.
3. The Eurocard dimensions conform to DIN 41612.

r--

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rL ______

WIDTH

EDGE CONNECTOR VERSION

r

II

---1 ~~~~NE~BOARD

~LENGTHI

AND RECEPTACLE

r---r.:,

y
t

II
'I

WIDTH

L

EUROCARD VERSION

II

l:

L -________________________

~~

-uII

~ ~EUROCONNECTOR
EXTENSION

EUROCARD CONNECTOR

EDGE CONNECTOR
COMPONENT AREA

L

HEIGHT

r

r - - - _\ - - ---,
Module Dimensions

PART NUMBER

RM65-3216(E)

:-'1- ROCk~~il.

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•

•

~

RM 65
DATA SHEET

•

,

16K PROM/ROM MODULE
RM 65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of·the-art
performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R6500
Assembly Language, PLl65, BASIC and FORTH. Both
BASIC and FORTH are available in ROM and can be
incorporated into the user's system.

•
•
•
•
o

•
The RM 65 product line uses a motherboard interconnect
concept and accepts any card in any slot. The 64-line RM
65 Bus offers memory addressing up to 12SK bytes, high
immunity to electrical noise and includes growth provisions for user functions. A selection of card cages
provides packaging flexibility. RM 65 products may also
be used with Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable
or desktop microcomputer applications.

•
•
•
•
o

Compact size - about 4" x 6%" (100 mm..)( 160 mm)
Edge connector and Eurocard versions
RM 65 Bus compatible
Buffered address, data and control lines
Supports the following PROMs/ROMs or equivalents:
Intel 2716 or 2732 PROMs
TI TMS 2516 or 2532 PROMs
Rockwell R2316, R2332 or R2364 ROMs
Low-power PROM operation selectable by individual
socket jumpers
Jumpers allow selection of 2K, 4K or SK byte devices
Starting address selectable for each of four 4K memory
blocks
Separate switch allows SK to be dedicated to one or
two memory bank operation
+5V operation
Fully assembled, tested and warranted.

PRODUCT OVERVIEW

ORDERING INFORMATION
The 16K PROM/ROM Module is available in an Edge
Connector version (RM65-3216) and a Eurocard version
(RM65-3216E).

Eurocard Venion
RM65-3216E

©Rockwellinternational Corporation 1981
All Rights Reserved
Printed in U.S.A

The RM 65 16K PROM/ROM Module has eight, 24-pin
sockets to accept up to 16K bytes of either programmable
read-only memory (PROM) or masked read-only memory
(ROM) devices. On-board jumpers permit selection of
2K, 4K or SK byte PROM/ROM devices. Switches allow
setting of the starting address for independent 4K byte
blocks of memory. All 16K bytes can be assigned to two
memory banks, or SK can be assigned to common memory while the other SK can be dedicated to one or two
65K memory banks. Low power operation is jumper
selectable for PROMs that have this option.

Edge Connector Version
RM65-3216
Specifications subject to

change without notice

Document No. RMAS5 N02
Rev. 1, March 1981

FUNCTIONAL DESCRIPTION

while the remaining 8K is assigned either to Bank 0 or Bank 1,
as determined by the Bank Select switch_

The PROM/ROM module has eight 24-pin sockets which can
accept up to 16K of either 2K, 4K, or 8K PROM or ROM_
The Data Buffers invert and transfer 8-bits of parallel data
from the selected PROM/ROM devices to the RM 65 Bus
during read operations.
The Control Buffers invert and transfer phase 2 clock, and
read/write control signals from the RM 65 Bus onto the
PROM/ROM module, and drive the bus active signal onto
the RM 65 Bus_
The Bank Select control circuit detects when the PROM/
ROM module's assigned memory bank is addressed, by comparing the bank address signal from the RM 65 Bus to the
Bank Select and Bank Select Enable switches. TI,e Bank
Select Enable switch allows 8K of the PROM/ROM to be
common memory (addressable in both Ban\.; 0 and Bank 1)

•

Four Base Address Decoders allow 4K PROM/ROM sections
to be independently addressed on any 4K boundary within
the selected bank. When an address falls with in any section
(per the Bilse Address switches), an enable signal is sent to
the Chip Select Decoder.
The Chip Select Decoder uses outputs from the Bank Select
Control circuit, the Base Address Decoders, and the PROM/
ROM size jumpers as well as the address lines to generate chip
selects to the PROM/ROM devices_ The PROM/ROM type
jumpers route the chip select I ines to the correct pins on the
PROM/ROM sockets.
The Data Buffer Control circuit enables the Data Buffers
during a read operation when an address corresponding to a
selected base address is decoded and the selected PROM/ROM
memory bank is addressed_

RM65
BUS CONNECTOR

DATA

CLOCK AND
CONTROL
CHIP
SELECT
DECODER

BUS
ACTIVE

BANK
ADDRESS

BANK
SELECT
CONTROL

16
SOCKETS
FOR 16K OF
PROM/ROM

~-;__~_16-4M

BASE
ADDRESS
DECODERS

ADDRESS

11

16K PROM/ROM Module Block Diagram

RM 65 Bus Pin Assignments
Top (Component Side)

Bottom (Solder Side)
Signal
Mnemonic

Input!
Output

Signal Name

Pin

Pin

Signal
Mnemonic

Signal Name

Input!
Output

Not Connected (See Note)

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

Xc

+5V

+5 Vdc (See Note)

GND

Ground

BADR!

Buffered Bank Address

GND

Ground

BA13!

Buffered Address Bit 13

BAll!

la

lc

+5V

+5 Vdc

2a

2c

BA15!

Buffered Address Bit 15

I

3a

3c

BA14!

Buffered Address Bit 14

I

I

4a

4c

BA12!

Buffered Address Bit 12

I

Buffered Address Bit 11

I

5a

5c

GND

Ground

BA10!

Buffered Address Bit 10

I

Sa

Sc

BA9!

Buffered Address Bit 9

I

BA81

Buffered Address Bit 8

I

7a

7c

BA7!

Buffered Address Bit 7

I

GND

Ground

8a

8c

BASI

Buffered Address Bit 6

I

BA5/

Buffered Address Bit 5

I

9a

9c

BA4!

Buffered Address Bit 4

I

BA3/

Buffered Address Bit 3

I

lOa

10c

GND

Ground

BA2/

Buffered Address Bit 2

I

lla

l1c

BA1/

BAO/

Buffered Address Bit

a

I

12a

12c

B~l

GND
BSO
BRDY

+12V/+V
GND
BDMT/

BR/W/

GND

I

Buffered Address Bit 1

13a

13c

BSYNC

"Buffered Sync

"Buffered Set Overflow

14a

14c

BDR01!

"Buffered DMA Request 1

Ground

"Buffered Ready

15a

15c

GND

"User Spare 1

16a

16c

-12V!-V

"+12 Vdc/+V

17a

17c

Ground Line

I

"Buffered Phase 1 Clock

Ground

'-12 Vdc!-V
'User Spare 2

18a

18c

BFLT/

"Buffered Bus Float

'Buffered DMA Terminate

19a

19c

B¢O

"Buffered External Phase 0 Clock

"User Spare 3

20a

20c

GND

"Buffered Read/Write "Not"

21a

21c

BDR02!

"System Spare

22a

22c

BRiw

Buffered Read!Write

I

23a

23c

BACT/

Buffered Bus Active

0

Ground

Ground
"Buffered DMA Request 2

"Buffered Non-Maskable Interrupt

BIRO!

"Buffered Interrupt Request

24a

24c

BNMI!

B~2/

"Buffered Phase 2 "Not" Clock

25a

25c

GND

Bi'12

"Buffered Phase 2 Clock

2Sa

2Sc

BRESI

27a

27c

BDSI

Buffered Data Bit 6

28a

28c

BD5!

Buffered Data Bit 5

0
0

0

Ground
"Buffered Reset

BD7/

Buffered Data Bit 7

GND

Ground

B041

Buffered Data Bit 4

0

29a

29c

BD31

Buffered Data Bit 3
Ground

BD2/

Buffered Data Bit 2

0

30a

30c

GND

B01!

Buffered Data Bit 1

0

31a

31c

BOO!

Buffered Data Bit 0

+5V

+5 Vdc

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

Ya

Yc

+5V

+5 Vdc (See Note)

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, Wc, Xa, Xc, Va, Yc, Za, Zc are not used on the Eurocard version_
"Not used on the 16K PROM/ROM module_

Not Connected (See Note)

0

0

•

16K PROM/ROM Module Physical and Electrical Characteristics
Characteristic

Value

Physical Characteristics (See Notes)
Edge Connector
3.9 in. (100 mm)
6.5 in. (164 mm)
0.56 in. (14 mm)
4.6 oz. (130 g)

Width
Length
Height
Weight
Environment
Operating Temperature
Storage Temperature
Relative Humidity

OOC to 70 0 C
0
0
-40 C to 85 C
0% to 85% (without condensation)

Power Requirements
wlo PROM/ROM Devices

+5 Vdc ±.5% 0.17A 1O.85W) - Typical
0.27A (1.35W) - Maximum

Access Time

450 nanoseconds (max)

RM 65 Bus Interface
Edge Connector Version
Eurocard Version

•

Eurocard
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
5.0 oz. (140 g)

72·pin edge connector 10.100 in. centers)
64-pin plug (0.100 in. centers) per
DIN 41612 (Row b not installed)

NOTES:
1. The height includes the maximum values for component height above the board surface 10.4 in. for populated modules),
printed circuit board thickness (0.062 in.), and pin extension through the bottom of the module (0.1 in.).
2. The length does not include the added extension due to the module ejector.
3. The Eurocard dimensions conform to DIN 41612.

r----

r----

~l~~~M) ~ ~~i~NE~BOARD
J-LENGT~II

r

JAND " ' " ' " " ' , ,

r

WLIDTH

~-f:

0

EDGE CONNECTOR VERSION

L....._ _ _ _ _ _ _ _ _ _ _- - '

,

I,

,

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I

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I

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I

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~l~~~M)

---1 ~~i~NE~BOARD

J-"NGTHi

JANDRECEPTACLE

..- --r,::

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t

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"
"

WLIDTH

EUROCARD VERSION

::

"
::

~-~

',-

--tJ

~ ~EUROCONNECTOR
EXTENSION
EUROCARD CONNECTOR

EDGE CONNECTOR

COMPONENT AREA

j-r----~-

.-

HEIGHT

'

Module Dimensions

PART NUMBER

RM65-7101 (E)

RM 65
DATA SHEET
SINGLE CARD ADAPTER
RM65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-theart performance, compact size, modular design and low
cost. Software for RM 65 svstems can be developed in
R6500 Assembly Language, PU65, BASIC and FORTH.
Both BASIC and FORTH are available in ROM and can
be incorporated into the user's system.

•
•
•
•
•

The RM 65 product line uses a motherboard interconnect concept and accepts any card in any slot. The 64line RM 65 Bus offers memory addressing up to 128K
bytes, high immunity to electrical noise and includes
growth provisions for user functions. A selection of card
cages provides packaging flexibility. RM 65 products
may also be used with Rockwell's AIM 65 Microcomputer for product development and for a broad variety
of portable or desktop microcomputer applications.

ORDERING INFORMATION
The Single Card Adapter is available in an Edge Connector version (RM65-7101) and a Eurocard version
(RM65-7101 E).

Drives one RM 65 Bus-compatible module
Provision for power and ground routing
Extends address, data and control lines
Edge connector and Eurocard versions
Fully assembled, tested and warranted

-en
2

C)

r-

m

o

PRODUCT OVERVIEW

l>

The RM 65 Single-Card Adapter allows one RM 65 Bus
compatible module to be connected to the AIM 65
Master Module, through the AIM 65 Expansion connector. The Adapter routes the AIM 65 address, data
and control lines from the AIM 65 Expansion connector
pin assignments to the RM 65· Bus pin assignments.
Drive circuitry is included on the address and data lines.

::D

o

l>

o

l>

"'tJ
-I

m

::D

Eurocard Version
RM65-7101E
©Rockwellinternational Corporation 1981
All Rights Reserved
Printed in U.S.A.

Edge Connector Version
RM65-7101
Specifications SUbject to
change without notice

Document No. RMA6S N03
Rev. 1, March 1981

FUNCTIONAL DESCRIPTION
The Single Card Adapter interfaces AI M 65 Expansion Connector signals to an attached RM 65 Bus receptacle. Data and
address lines are buffered, whereas control lines are directly
wired. All signals are. routed from the AIM 65 Expansion
Connector positions to corresponding RM 65 Bus receptacle
pin positions. Ground is connected to the interspersed RM 65
Bus GND pins.
The Data Transceivers invert and drive 8-bits of parallel data
between the AIM 65 Expansion Connector and the RM 65
Bus interface. During a write operation, data received from
the AIM 65 Expansion Connector are driven into the interfacing RM 65 module. During a read operation, data read
from the RM 65 module are transmitted into the AIM 65.
When theRM 65 module is not addressed, the transceivers
are disabled.
The Address Buffers invert and buffer 16 parallel address

bits from the AIM 65 to the connected RM 65 module.
The bank address line is held high to address Bank a (lower
65K) in the interfacing RM 65 module.
Eleven control and timing signals are directly connected
between the AIM 65 Expansion Connector and the RM 65
module. The read/write, phase 2 clock, phase 1 clock, sync
and reset AIM 65 output lines are routed directly to the
RM 65 receptacle. The ready, interrupt request, set overflow and non-maskable interrupt lines from the RM 65 receptacle are connected straight through to the AIM 65 Expansion
Connector interface.
A terminal block allows external +5V, +12V /+V, and -12V I-V
power supplies to be connected as required. An on-board
jumper allows the +5V for the RM 65 module to originate
from the AIM 65 Expansion Connector or from the external
+5V power supply.

•
POWER CONNECTION
+5V Power Connection
The +5V required for the Single Card Adapter can be provided
from the AIM 65 microcomputer through the AIM 65 Expansion Connector or directly from an external power supply
through a connection to the on-board terminal board (TB 1).
Jumper A/B routes the +5V power from the selected source.

External +5V Power Source Connection

(1) Install Jumper A/B in the B position.
(2) Connect the +5V lead from the external power supply
to the +5V connection on TB 1.
(3) Connect the ground lead from the external +5V power
supply to either of the two GND connections on TB1.

Turn off the external power supply before
connecting power leads to the Single Card
Adapter.
AIM 65 +5V Power Source Connection

±12V/±V Power Connection
(1) Install Jumper A/B in the A position.
(2) Disconnect the +5V lead of the external power supply
from the +5V connection on TB 1.

Connection points are provided on TB 1 for ± 12 Vdc, or other
voltages, as required by the mating RM 65 module.
(1) Connect the +12V /+V lead from the external power
supply to the TB 1 connection marked +15V or +V.
This terminal is connected to connector Jl pin 17a.

If the mating RM 65 module draws over
a.5A, the external connection to +5V
must be used or the AIM 65 Master Module
may be damaged.

(2) Connect the -12V/-V lead from the external power
supply to the TBl connection marked -15V or -V.
This terminal is connected to connector Jl pin 16c_

INSTALLING THE SINGLE CARD ADAPTER
d. Install the RM 65 module into the J1 connector on the
Adapter using installation procedures described in the
documentation for the particular module. Ensure that
Bank Select switches on the add-on module are positioned
to Bank Select 0 or Bank Select Disable, as appropriate.

Before installing the module, ensure that it is not damaged and
is free of grease, dirt, liquid or other foreign material.
.~

Prior to module installation, turn off power
to the AIM 65 and, if applicable, the optional external +5V and/or ± 12V /± V power
supply input to the Adapter.

e. Turn on power to the AIM 65 and, if applicable, turn on
external +5 Vdc and/or ±12V/±V to the SCA module.

REMOVING THE SINGLE CARD ADAPTER
a. Align pin 1 of J3 on the SCA with pin 1 of the Expansion
Connector on the AIM 65 Master Module (component side
up).

a. Turn off power to the AIM 65 and if applicable, to the'
external ± 12V /± V power supplies.

b. Carefully insert the Adapter into the Expansion Connector.

b. Pull the Adapter straight back while moving it slightly from
side to side to disconnect it from the AIM 65 Expansion
Connector.

c. Press in firmly until all pins are securely seated.

•
,

CONNECT TO AIM 65
EXPANSION CONNECTOR

J3
DATA

TIMING
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Eurocard Version
RM65-7104E
©Rockwellinternational Corporation 1981
All Rights Reserved
Printed in U.S.A.

Edge Connector Version
RM65-7104
Specifications subject to
change without notice

Document No. RMA6S N04
Rev. 1, Merch 1981

•

. ::-:::-

I

FUNCTIONAL DESCRIPTION

bus active signal enables the Transceivers. When the bus
float signal is active, the Transceivers are disabled.

The Adapter/Buffer consists of two modules and two interconnect cables. The Adapter module connects to the AIM 65
Expansion connector and the Buffer module connects to an
RM 65 Bus motherboard receptacle.

The Address Buffers invert and transfer 16 parallel address
lines from the interconnect cable to the RM 65 Bus. When
the bus float signal is active, the Buffers are disabled.

The Adapter module transfers data, address and control lines
from AIM 65 Expansion Connector to the interconnect
cables. The eight data and 16 address lines are routed directly,
without buffering. The read/write, clock, sync and reset
AIM 65 output control lines are also routed directly through
the Adapter. The ready, set overflow, interrupt request and
non-maskable interrupt AIM 65 input lines are buffered on
the module.

•
-;

. :::-

Two 16·inch 40 conductor flat ribbon cables connect the
Adapter module to the Buffer module. The cables are mass
terminated at each end, and are permanently attached to the
interfacing module .
The Buffer module buffers and routes all interface signals
between the interconnect cables and the RM 65 Bus connector.
The. Data Transceivers invert and drive 8·bits of parallel data.
During a write operation, data received from the cables are
driven onto the RM 65 Bus. During a read operation, data
received from the RM 65 Bus are driven onto the cables. The

Jumper E 1 selects the source for the bank address line
(BADR/) - either the buffer module or an external module.
When the buffer module is the source (position Al. the bank
address line is held high to address Bank 0 (Lower 65K) on
the Bus; this line is disabled when the bus float line is active.
For an external source (position Bl. the bank.address line is
not used by the buffer module, and must be controlled by
another module on the Bus.
The seven read/write, clock, sync and reset lines from the
cables to the bus are buffered by the Control Drivers. All of
these lines, except reset and phase 1, are disabled when the bus
float. line is active. The ready, set overflow, interrupt request
and non·maskable lines from the bus to the interconnect
cables are also buffered by the Control Drivers.
Jumper E2 selects the source for the DMA Terminate line
(BDMTI) - either the buffer module or an external module.
When the .buffer module is the source (position A), the DMA
terminate line is held high (inactive). For an external source
(position Bl. the DMA terminate line is not used by the buffer
module, and must be controlled by another module on the bus.

INSTALLATION

Installing the Adapter/Buffer

Before installing the module, ensure that it is not damaged and
is free of grease,dirt, liquid or other foreign material.

a. Before installing the Adapter/Buffer, turn off power
to the AIM 65 and the interfacing RM 65 Bus motherboard.

RM 65 Bus connectors are keyed to prevent
improper module connection. If the module
does not insert into the receptacle with
moderate pressure applied, check the orientation and connector alignment of the module. Forcing the module improperly into
the receptacle may damage the receptacle
and/or the module.
f. Apply power to the AIM 65 and to the mating RM 65
Bus motherboard.
Removing the Adapter/Buffer

b. Configure Jumpers E 1 and E2, per the Functional
Description.
c. Align the Adapter module connector J3 pin 1 with the
AIM 65 Expansion Connector J3 pin 1.
d. Plug the Adapter module onto the Expansion Connector. Press i"n firmly on the end of module until all
pins are securely seated.
e. Install connector. P1 of the Buffer module into the
desired slot on the mating RM 65 Bus motherboard.

a. Turn off power to the AIM 65 and to the RM 65 Bus
motherboard.
b. Lift up on the Buffer module ejector tab to release the
module from the mating RM 65 Bus receptacle. Pull
the module straight back until it is free from the card
slot guides.
c. Pull back on the Adapter module while moving it
slightly from side to side until it is free from the AIM 65
Expansion Connector.

Buffer Module to RM 65 Bus Connector Pin Assignments
Top (Component Side)

Bottom (Solder Side)
Signal
Mnemonic

I

Signal Name

Input/
Outllut

Pin

Pin

Signal
Mnemonic

Signal Name

Input!
Output

Not Connected (See Note)

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

Xc

+5V

+5 Vdc (See Note)

GND

Ground

BADR/

Buffered Bank Address

GND

Ground

BA13/

Buffered Address Bit 13

BAll/

1a

1c

+5V

+5 Vdc

2a

2c

BA15/

Buffered Address Bit 15

0

3a

3c

BA14/

Buffered Address Bit 14

0

0

4a

4c

BA12/

Buffered Address Bit 12

0

Buffered Address Bit 11

0

5a

5c

GND

Ground

BAlO/

Buffered Address Bit 10

0

6a

6c

BA9/

Buffered Address Bit 9

0

BA8/

Buffered Address Bit 8

0

7a

7c

BA71

Buffered Address Bit 7

0

GND

Ground

8a

8c

BA61

Buffered Address Bit 6

0

BA51

Buffered Address Bit 5

0

9a

9c

BA41

Buffered Address Bit 4

0

BA31

Buffered Address Bit 3

0

lOa

10c

GND

Ground

BA21

Buffered Address Bit 2

0

lla

llc

BAlI

Buffered Address Bit 1

0

BAOI

Buffered Address Bit 0

0

12a

12c

B~l

Buffered Phase 1 Clock

0

GND

Ground

13a

13c

BSYNC

Buffered Sync

0

BSO

Buffered Set Overflow

I

14a

14c

BDR011

Buffered Ready

I

BRDY

0

15a

15c

GND

*User Spare 1

16a

16c

-12V/-V

17a

17c

Ground Line

18a

18c

BFLTI

BDMTI

Buffered DMA Terminate

19a

19c

B¢O

*User Spare 3
BRfW!

Buffered Read/Write "Not"

0

'System Spare

Ground
*-12 Vdc/-V
*User Spare 2

*+12 Vdc/+V

GND

+12V/+V

*Buffered DMA Request 1

Buffered Bus Float

I

*Buffered External Phase 0 Clock
Ground

20a

20c

GND

21a

21c

BDR021

22a

22c

BRffl

Buffered Read/Write

0

23a

23c

BACTI

Buffered Bus Active

I
I

*Buffered DMA Request 2

GND

Ground

BIROI

Buffered Interrupt Request

I

24a

24c

BNMII

Buffered Non-Maskable Interrupt

B¢21

Buffered Phase 2 "Not" Clock

0

25a

25c

GND

Ground

B~2

Buffered Phase 2 Clock

0

26a

26c

BRESI

Buffered Reset

0

BD71

Buffered Data Bit 7

1/0

27a

27c

BD61

Buffered Data Bit 6

1/0

GND

Ground

28a

28c

BD51

Buffered Data Bit 5

1/0

BD41

Buffered Data Bit 4

1/0

29a

29c

BD31

Buffered Data Bit 3

1/0

BD21

Buffered Data Bit 2

1/0

30a

30c

GND

Ground

1/0

31a

31c

BDOI

Buffered Data Bit 0

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

BOll

Buffered Data Bit 1

+5V

+5 Vdc

+5V

+5 Vdc (See Note)

Ya

Yc

Not Connected (See Note)

Za

Zc

NOTE
Pins Wa, Wc, Xa, Xc, Ya, Yc, Za, Zc are not used on the Eurocard version.
*Not used on this module.

Not Connected (See Note)

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Adapter Module to AIM 65 Expansion Connector Pin Assignments
Top (Component Side)
Signal
Mnemonic
SYNC
RDY
01
IRQ
S.D.
NMI

RES
D7
D6
D5
D4
D3
D2
Dl
DO
-12V
+12V

•

Cs8
CS9
CSA
+5V
GND

Signal Name
SYNC
Ready
Phase 1 Clock
Interrupt Request
Set Overflow
Non·Maskable Interrupt
Reset
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit a
'-12Vdc
"+12 Vdc
"Chip Select 8
'Chip Select 9
"Chip Select A
+5 Vdc
Ground

Bottom (Solder Side)
Input/
Output
I
0
I
0
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Pin

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

A
B
C
D
E
F

H
J
K
L
M
N
P
R
S
T
U

V
W

X
Y
Z

Signal
Mnemonic
AO
Al
A2
A3
A4
A5
A6
A7
AB
A9
Ala
All
A12
A13
A14
A15
SYS 02
SYS RfW
R/W
TEST

02
RAM Rm

Input/
Output

Signal Name
Address Bit a
Address Bit 1
Address Bit 2
Address Bit 3
Address Bit 4
Address Bit 5
Address Bit 6
Address Bit 7
Address Bit 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12
Address Bit 13
Address Bit 14
Address Bit 15
System Phase 2 Clock
System ReadlWr'ite
ReadlWrite "Not"
"Test
Phase 2 Clock "Not"
"RAM ReadlWrite

I

NOTE:

" = Not used on this module.

CONNECT TO
AIM65
EXPANSION
CONNECTOR

CONNECT TO

r-------~B~U~FF~E~R~M~O~D~U~L~E~-------,:~C~P~~~LE

ADAPTER MODULE
TWO 16 INCH CABLES

BUS ACTIVE
DATA

DATA

BUS FLOAT

ADDRESS

16

16
ADDRESS

CLOCK
AND
CONTROL

I

CLOCK
AND
} CONTROL
DMA TERMINATE

Adapter/Buffer Block Diagram

Adapter/Buffer Physical and Electrical Characteristics
Value

Characteristics
Dimension (See Notes)
Adapter Module
Width
Length
Height
Buffer Module
Width
Length
Height

4.4 in. (111 mm)
2.6 in. (67 mm)
0.56 in. (14 mm)
Edge Connector
Eurocard
3.9 in. (100 mm)
3.9 in. (100 mm)
6.5 in. (164 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
0.56 in. (14 mm)

Weight

6.9 oz. (195 g)

Power
Adapter Module
Buffer Module

7.2 oz. (205 g)

+5V ±.5% 30 rnA (0.15W) - Typical
50 rnA (0.25W) - Maximum
+5V ±.5% 190 rnA (0.95W) - Typical
330 rnA (1.7 W) - Maximum

Environment
Operating Temperature
Storage Temperature
Relative Humidity

OOC to 70 0 C
o
0
-40 C to 85 C
0% to 85% (without condensation)

Propagation Time

20 ns - Maximum

I nterface Connectors
AIM 65 Expansion Connector
RM 65 Bus
Edge Connector Version
Eurocard Version
Interface Cables
Number of Cables
Cable Length
Type
Number of conductors per cable
Wire Size

22/44 - edge receptacle
(0.156 in. centers)
72-pin edge connector
(0.100 in. centers)
64·pin plug (0.100 in. centers) per DIN 41612
(Row b is not installed)
Two
16 inches
Flat ribbon
40
H28AWG

NOTES:
1.
2.
3.

The height includes the maximum values for component height above the board surface (0.4 in. for populated modules),
printed circuit board thickness (0.062 in.!, and pin extension through the bottom of the module (0.1 in.!
The length does not include extensions beyond the edge of the module due to connectors or the module ejector.
The Eurocard dimensions conform to DIN 41612.

~-

•
...

•

ADAPTER MODULE

CABLE 2

BUFFER MODULE

~
~
U-_lJ

f~~~MI=41 ~~~~NE~BOARD
LENGTHi

lANDRECEPTACLE

CABLE 2

CABLE 1

-1

)fj-

'I

o

EDGE CONNECTOR VERSION

o

WIDTH

' :

"

EUROCARD VERSION

"

i:
-LJ"

--l ~EUROCONNECTOR
EXTENSION

EUROCARD CONNECTOR

EDGE CONNECTOR

Module Dimensions

PART NUMBER

'1'

RM65-711.6(E)

RM 65
DATA SHEET

Rockwell

CABLE DRIVER·ADAPTER/BUFFER
RM 65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-theart performance, compact size, modular design and low
cost. Software for RM 65 systems can be developed in
R6500 Assembly Language, PL/65, BASIC and FORTH.
Both BASIC and FORTH are available in ROM and can
be incorporated into the user's system.

•
•
•
•
•
•

The RM 65 product line uses a motherboard interconnect concept and accepts any card in any slot. The 64line RM 65 Bus offers memory addressing up to 128K
bytes, high immunity to electrical noise and includes
growth provisions for user functions. A selection of card
cages provides packaging flexibility. RM 65 products
may also be used with Rockwell's AIM 65 Microcomputer for product development and for a broad variety
of portable or desktop microcomputer applications.

ORDERING INFORMATION
The Cable Driver Adapter/Buffer is available in an Edge
Connector Version (RM65-7116) and a Eurocard version
(RM65-7116El.

RM 65 Bus compatible
Buffered address data and control lines
Drives up to 15 modules
Long cable for distances of up to 6 feet
Edge connector and Eurocard versions
Fully assembled, tested and warranted

n

l>-

·:m
. ,...

m

PRODUCT OVERVIEW

.0

The Cable Driver Adapter/Buffer extends the RM 65 Bus
from the AIM 65 Expansion Connector to a compatible
motherboard that is situated up to six feet away. Included
circuitry permits the Cable Driver ~dapter/Buffer to drive
up to 15 RM 65 Bus-compatible modules. (The similar
Adapter/Buffer, Part Number RM65-7104, provides the
same drive capability for applications in which the mother-.
board ne.ed not be more than 16 inches from the Expansion Connector.)
The Cable Driver Adapter/Buffer consists of a cable driver
adapter module, a buffer module. and two 6-foot interconnect cables. Both cables are flexible, so the motherboard may be installed in a wide variety of locations and
orientations relative to the AIM 65.

::0

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CORockweli International Corporation 1981
All Rights Reserved
Printed in U.S.A.

Eurocard Version

Edge Connector Version

RM65-7116E

RM65·7116
Specifications subject to
change without notice

Document No. RMASS N22
March 1981

FUNCTIONAL DESCRIPTION
The Cable Driver Adapter/Buffer consists of two modules and
two interconnect cables. The Adapter Module connects to
the AIM 65 Expansion connector and the Buffer module
connects to an RM 65 Bus motherboard receptacle.

The Data Transceivers invert and drive 8-bits of parallel data.
During a write operation, data received from the cables are
driven onto the R M 65 Bus. During a read operation, data
received from the RM 65 Bus are driven onto the cables. The
bus active signal enables the Transceivers. When the bus float
signal is active, the Transceivers are disabled.

The Cable Driver Adapter module buffers data, address and
control lines between the AIM 65 Expansion Connector and
the interconnect cables.

The Address Buffers invert and transfer 16 parallel address
lines from the interconnect cable to the RM 65 Bus. When the
bus float signal is active, the Buffers are disabled.

The Data Transceivers drive 8·bits of parallel data. During a
write operation, data received from the AIM 65 are driven
onto the cables. During a read operation, data received from
the cables are driven into the AIM 65. The bus active signal
enables the Data Transceivers.
The Address Buffers drive 16-bits of parallel data from the
AIM 65 onto the cables.

Jumper E 1 selects the source for the bank address line
(BADR/) - either the buffer module or an external module.
When the buffer module is the source (position AI. the bank
address line is held high to address Bank 0 (lower 65K) on
the Bus; this line is disabled when the bus float line is active.
For an external source (position B), the bank address line is
not used by the buffer module, and must be controlled by
another module on the Bus.

The Control Buffers transfer the timing and control signals
between the AIM 65 and the cables. The seven read/write,
clock, sync, and reset lines are driven from the AIM 65 onto
the cables. The four ready, set overflow, interrupt request
and non·maskable interrupt lines are driven from the cables
onto the AIM 65.

The seven read/write, clock, sync and reset lines from the
cables to the bus are buffered by the Control Buffers. All
of these lines, except reset and phase 1, are disabled when the
bus float line is active. The ready, set overflow, interrupt
request and non-maskable lines from the bus to the interconnect cables are also buffered by the Control Buffers.

Two 6-foot 40 conductor flat ribbon cables connect the
Cable Driver Adapter module to the Buffer module. The
cables are mass terminated at each end, and are permanently
attached to the interfacing module.

Jumper E2 selects the source for the DMA Terminate line
(BDMT/) - either the buffer module or an external module.
When the buffer module is the source (position A), the DMA
terminate line is held high (inactive). For an external source
(position Bl. the DMA terminate line is not used by the
buffer module, and must be controlled by another module
on the bus.

The Buffer module buffers and routes all interface signals
between the interc~nnect cables and the RM 65 Bus connector.

INSTALLATION

Installing the Cable Driver Adapter/Buffer

Before installing the module, ensure that it is not damaged and
is free of grease, dirt, liquid or other foreign material.
a. Before installing the Cable Driver Adapter/Buffer, turn
off power to the AIM 65 and the interfacing RM 65 Bus
motherboard.
b. Configure Jumpers E1
Description.

and E2, per the Functional

c. Align Cable Driver Adapter module connector J3 pin
with the AIM 65 Expansion Connector J3 pin 1.
d. Plug the Cable Driver Adapter module onto the Expan·
sion Connector. Press in firmly on the end of module
until all pins are securely seated.
e. Install connector P1 of the Buffer module into the
desired slpt on the mating RM 65 Bus motherboard.

RM 65 Bus connectors are keyed to prevent
improper module connection. If the module
does not insert into the receptacle with
moderate pressure applied, chec~ the orien·
tation and connector alignment of the module. Forcing the module improperly into
the receptacle may damage the receptacle
and/or the module.
f. Apply power to the AIM 65 and to the mating RM 65
Bus motherboard.
Removing the Cable Driver Adapter/Buffer
a. Turn off power to the AIM 65 and to the RM 65 Bus
motherboard.
b. Lift up on the Buffer module ejector tab to release the
module from the mating RM 65 Bus receptacle. Pull
the module straight back until it is free from the card
slot guides.
c. Pull back on the Cable Driver module while moving it
slightly from sjde to side until it is free from the AIM 65
Expansion Connector.

Buffer Module to RM 65 Bus Connector Pin Assignments
Top (Component Side)

Bottom (Solder Side)
Signal
Mnemonic

Signal Name

Input!
Output

Pin

Pin

Signal
Mnemonic

Signal Name

Input!
Output

Not Connected (See Note)

Not Connected (See Note)

Wa

Wc

+5V

+5 Vdc Line (See Note)

Xa

Xc

+5V

+5 Vdc (See Note)

GNO

Ground

BADR!

Buffered Bank Address

GND

Ground

BAI3/

Buffered Address Bit 13

BAllI

Buffered Address Bit 11

BA101

Buffered Address Bit 10

BA8/

Buffered Address Bit 8

GND

Ground

BA51

la

lc

+5V

+5 Vdc

2a

2c

BAI5!

Buffered Address Bit 15

0

3a

3c

BAI4!

Buffered Address Bit 14

a
a
a
a

4a

4c

BAI2/

Buffered Address Bit 12

a
a

5a

5c

GND

Ground

6a

6c

BA9/

Buffered Address Bit 9

7a

7c

BA7!

Buffered Address Bit 7

8a

8c

BA6/

Buffered Address Bit 6

Buffered Address Bit 5

0

9a

9c

BA41

Buffered Address Bit 4

BA31

Buffered Address Bit 3

10c

GND

Ground

Buffered Address Bit 2

lla

llc

BAI/

Buffered Address Bit 1

BAO/

Buffered Address Bit 0

a
a
a

lOa

BA21

12a

12c

B~1

Buffered Phase 1 Clock

GND

Ground

13a

13c

BSYNC

BSO

Buffered Set Overflow

I

14a

14c

BOROI/

Buffered Ready

I

15a

15c

GND

16a

16c

-12V/-V

BRDY

0

"User Spare 1

Buffered Sync

a
a
a
a
a
a
a

"Buffered DMA Request 1
Ground
"-12 Vdc/-V
"User Spare 2

"+12 Vdc/+V

17a

17c

GND

Ground Line

18a

18c

BFLT/

BDMTI

Buffered DMA Terminate

19a

19c

B~O

20a

20c

GND

21a

21c

BDR021

22a

22c

BR/W

Buffered ReadlWrite

a

23a

23c

BACT/

Buffered Bus Active

I
I

+12V/+V

"User Spare 3
BRIW!

Buffered ReadlWrite "Not"

0

"System Spare

Buffered Bus Float

I

"Buffered External Phase 0 Clock
Ground
"Buffered OMA Request 2

GND

Ground

BIRO/

Buffered Interrupt Request

I

24a

24c

BNMII

Buffered Non-Maskable Interrupt

B~2/

Buffered Phase 2 "Not" Clock

25a

25c

GNO

Ground

26a

26c

BRES/

Buffered Reset

a

27a

27c

BD6/

Buffered Data Bit 6

I/O

28a

28c

B05/

Buffered Data Bit 5

I/O
I/O

B¢2

Buffered Phase 2 Clock

a
a

B07/

Buffered Data Bit 7

I/O

GND

Ground

BD4/

Buffered Data Bit 4

1/0

29a

29c

BD3/

Buffered Data Bit 3

BD21

Buffered Data Bit 2

I/O

30a

30e

GNO

Ground

1/0

31a

31c

BDO/

Buffered Data Bit 0

32a

32c

GND

Ground

+5V

+5 Vdc (See Note)

BD11

Buffered Data Bit 1

+5V

+5 Vdc

+5V

+5 Vdc (See Note)

Ya

Yc

Not Connected (See Notel

Za

Zc

NOTE
Pins Wa, We, Xa, Xc, Ya, Yc, Za, Zc are not used on the Eurocard version.
"Not used on this module.

Not Connected (See Notel

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•

Cable Driver Adapter Module to AIM 65 Expansion Connector Pin Assignments
Bottom (Solde. Side)

Top (Component Side)
Signal
Mnemonic

•
-:-

. :::-

SYNC
ROY
01
IRQ
S.O.
NMI
RES
07
06
05
04
03
02
01
DO
-12V
+12V

Signal Name
SYNC
Ready
Phase 1 Clock
Interrupt Request
Set Overflow
Non·Maskable Interrupt
Reset
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
*-12Vdc
*+12 Vdc
'Chip Select 8
'Chip Select 9
'Chip Select A
+5 Vdc
Ground

CS8
CS9
GsA
+5V
GND

Input!
Output
I
0
I
0
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Pin

Pin

1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16
17
18
19
20
21
22

A
B
C
0
E
F
H
J
K
L

M
N
P
R
S
T
U

V
W

X
Y
Z

Signal
Mnemonic
AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All
A12
A13
A14
A15
SYS 02
SYS R{W
R/W
TEST

02
RAM R/W

Input/
Output

Signal Name
Address Bit 0
Address Bit 1
Address Bit 2
Address Bit 3
Address Bit 4
Address Bit 5
Address Bit 6
Address Bit 7
Address Bit 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12
Address Bit 13
Address Bit 14
Address Bit 15
System Phase 2 Clock
System ReadlWrite
ReadlWrite "Not"
'Test
Phase 2 Clock "Not"
'RAM ReadlWrite

I

NOTE:
• =

Not used on this module.

CONNECT TO'
AIM65
EXPANSION
CONNECTOR

BUFFER
MODULE

CABLE DRIVER
ADAPTER MODULE
TWO 6 FOOT CABLES

CONNECT TO
RM 65 BUS
RECEPTACLE
BUS ACTIVE
DATA

DATA

BUS FLOAT

16

ADDRESS

16
ADDRESS

CLOCK
AND
CONTROL

!

CONTROL
BUFFERS

CLOCK
AND
} CONTROL
DMA TERMINATE

J3

Cable Driver Adapter/Buffer Block Diagram

Cable Driver Adapter/Buffer Physical and Electrical Characteristics
Characteristics
Dimension (See Notes)
Cable Driver Adapter Module
Width
Length
Height
Buffer Module
Width
Length
Height

Value

4.4 in. (111 mm)
5 in. (127 mm)
0.56 in. (14 mm)
Edge Connector
3.9 in. (100 mm)
6.5 in. (164 mm)
0.56 in. (14 mm)

Eurocard
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
1.0 Ib (450 g)

Weight
Power
Cable Driver Adapter Module
Buffer Module

+5V ±5% 30 rnA (0.15W) - Typical
275 rnA (0.25W) - Maximum
+5V ±5% 190 rnA (0.95W) - Typical
330 rnA (1.7W)- Maximum

Environment
Operating Temperature
Storage Temperature
Relative Humidity

-40 0 C to 85 0 C
0% to 85% (without condensation)

Propagation Time

50 ns - Maximum

Interface Connectors
AIM 65 Expansion Connector
RM 65 Bus
Edge Connector Version
Eurocard Version
Interface Cables
Number of Cables
Cable Length
Type
Number of conductors per cable
Wire Size

OOC to 70 0 C

22/44 - edge receptacle
(0.156 in. centers)
72·pin edge connector
(0.100 in. centers)
64-pin plug (0.100 in. centers) per DIN 41612
(Row b is not installed)

Two
6 feet
Flat ribbon
40
H28AWG

NOTES:
1.
2.
3.

The height includes the maximum values for component height above the board surface (0.4 in. for populated modules).
printed circuit board thickness (0.062 in.1. and pin extension through the bottom of the module (0.1 in.!
The length does not include extensions beyond the edge of the module due to connectors or the module ejector.
The Eurocard dimensions conform to DIN 41612.

•

. .:.:

•

CABLE DRIVER ADAPTER MODULE
CABLE 1

CABLE 2

BUFFER MODULE

~
CABLE 2

Tt

I:
I I

ll

MATING
MOTHERBOARD

1172 M M I = i
LENGTH-------i

JAND RECEPTACLE

I

CABLE 1

J]-

WIDTH

-

6'8IN'

r-n

EDGE CONNECTOR VERSION

--U

I
I
I

II
II
I(

EUROCARD VERSION

l::
I
I

II
II

~------------------~~-~

EUROCARD CONNECTOR

EDGE CONNECTOR

Module Dimensions

PART NUMBER

RM65-7201 (E)

'1'

RM 65
DATA SHEET

-Rockwell

DESIGN PROTOTYPING MODULE
RM65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-the-art
performance, compact size, modular design and low cost.
Software for RM 65 systems.can be developed in R6500
Assembly Language,PL/65, BASIC and FORTH. Both
BASIC and FORTH are available in ROM and can be
incorporated into the user's system.

•

The RM 65 product line uses a motherboard interconnect
concept and accepts any card in any slot. The 64-line RM
65 Bus offers memory addressing up to 128K bytes, high
immunity to electrical noise and includes growth provisions for user functions. A selection of card cages
provides packaging flexibility. RM 65 products may also
be used with Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable
or desktop microcomputer applications.

ORDERING INFORMATION
The Design Prototyping Module is available in an Edge
Connector version (RM65-7201) and a Eurocard version
(RM65-7201E).

Compact size - approximately 4" x 6%" (100 mm x
160mm)
•. Provision for mounting mass-terminated cable connectors
•
All wire-wrap holes pre-drilled on 0.100 in. centers
•
Provision for installing decoupling capacitors
•
Spacing for 0.300, 0.400 and 0.600 in. wide components
•
+5V and ground extended throughout the module
•
isolated power strips allow connection to other supply voltages
•
Edge Connector and Eurocard versions

C

m

-

tJ)

C)

2

"o

:D

PRODUCT OVERVIEW
The Design Prototyping Module allows you to develop
custom application circuits for installation in any RM 65
motherboard.
Power and return lines are pre routed throughout the module. Plated-through holes, spaced beside the power lines,
permit wire-wrap sockets to be installed. The hole pattern
allows manual or automatic wire-wrapping. The holes at
the I/O end of the module accept a variety of wire-wrap
flat ribbon cable connectors_ Additional pre-drilled holes
permit mounting of decoupling capacitors.

-I

o
~

-"2

C)

3:

o
c
c:
r-

m

Eurocard Version
RM65-7201E
«:I Rockwell International Corporation 1981
All Rights Reserved
Printed in U.S.A.

Edge Connector Version
RM65-7201
Specifications subject 10
change withoul notice

Document No_ RMAI& N08
Rev_ 2, M ..ch 1981

GND (ALL STRIPS)

Ze

32e

•

1e

X e - -_____

~

We

CONNECTOR
HOLES

+5V
FIT

I
FIT

+5V
FIT

I
FIT

+5V
FIT

I
FIT

+5V
FIT

I
FIT

+5V
FIT

Design Prototyping Module - Edge Connector (Component Side)

+5V

Wa

32a

~---~-------~-------~~~'-------t-------J-------~FEEDTHROUGH

HOLES TOGND
I = ISOLATED POWER STRIPS
FIT - FEEDTHROUGH HOLES

Design Prototyping Module - Edge Connector (Wirewrap Side)

RM 65 Bus Connector Pin Assignments
Top (Component Sidel

BaHam ISolder Side I
Signal
Mnemonic

Signal
Mnemonic

Signal Name

Signal Name

Pin

Pin

Not Connected ISee Note!

Wa

Wc

+5V

+5 Vdc Line ISee Note!

Xa

Xc

+5V

+5 Vdc ISee Note!

GND

Ground

la

lc

+5V

+5 Vdc

BADRI

Buffered Bank Address

2a

2c

BA151

Buffered Addre .. Bit 15

GND

Ground

3a

3c

BA141

Buffered Address Bit 14

BA131

Buffered Address Bit 13

4a

4c

BA121

Buffered Addre .. Bit 12

BA111

Buffered Address Bit 11

5a

5c

GND

Ground

BAIOI

Buffered Address Bit 10

6a

6c

BA91

Buffered Address Bit 9

BASI

Buffered Address Bit S

7a

7c

BA71

Buffered Address Bit 7

GND

Ground

Sa

Be

BA61

Buffered Address Bit 6

BA51

Buffered Addre .. Bit 5

9a

9c

BA41

Buffered Address Bit 4

BA31

Buffered Addre .. Bit 3

IDa

lOe

GND

Ground

BA21

Buffered Addre .. Bit 2

l1a

l1c

BA1I

Buffered Address Bit 1

BAOI

Buffered Addre .. Bit 0

12a

12c

Blfl

Buffered Phase 1 Clock

GND

Ground

13a

13c

BSYNC

Buffered Sync

Not Connected ISee Note!

BSO

Buffered Set Overflow

14a

14c

BDRal/

Buffered DMA Request 1

BRDY

Buffered Ready

15a

15c

GND

Ground

User Spare 1

16a

16c

-12V/·V

·12 Vdcl·V

+12V/+V

+12 Vdcl+V

17a

17c

GND

Ground Line

ISa

lBe

BFLTI

Buffered Bus Float

BDMTI

Buffered DMA Terminate

19a

19c

BIto

Buffered External Phase 0 Clock

User Spare 3

20a

20e

GND

Ground

User Spare 2

Buffered ReadlWrite "Not"

21a

21c

BDRa21

Buffered DMA Request 2

Sys tern Spare

22a

22c

BRIW

Buffered ReadlWrite

GND

Ground

23a

23c

BACTI

Buffered Bus Active

BRIWI

BIRal

Buffered Interrupt Request

24a

24c

BNMII

Buffered Non-Maskable Interrupt

Bif21

Buffered Phase 2 "Not" Clock

25a

25c

GND

Ground

Bif2

Buffered Phase 2 Clock

26a

26c

BRESI

Buffered Reset

BD71

Buffered Data Bit 7

27a

27c

BD61

Buffered Data Bit 6

GND

Ground

2Sa

2Be

BD51

Buffered Data Bit 5

BD41

Buffered Data Bit 4

29a

29c

BD31

Buffered Data Bit 3

BD21

Buffered Data Bit 2

30a

30e

GNO

Ground

BOIl

Buffered Oat. Bit 1

31a

31c

BOOI

Buffered Data Bit 0

+5V

+5 Vdc

32a

32c

GND

Ground

+5V

+5 Vdc IS•• Not.!

+5V

+5 Vdc ISee Note!

Ya

Yc

Not Connected (See Note)

Za

Zc

Not Connected ISe. Note!

NOTE
Pins Wa, We, Xa. Xc, Va, Ye, Za and Zc are not used on Eurocard version.

INSTALLATION
1. Solder jumpers between the isolated power strips and the power
1+5V. +12V/+V. or -12V/-V! traces as required.
4. Double check the hookup to ensure proper connection.
CAUTION
CAUTION
Before proceeding, ensure that the power strips
are not shorted to GND.
2. Solder power filter capacitors as required between the power strips
and GND.

Ensure that no power lines are shorted to GND
belore installation into the AM 65 bus. Shorting
power to ground may damage your circuitry. module, power supply and/or interfacing modules unless proper current limiting protection is provided.

3. Install and V'.'ire components on the Design Prototype Module:
5. Install components into sockets as required.
a. Insert wire·wrap sockets into the desired holes. Solder two
pins (on opposite ends of the socked to the associated feed·
through to hold the socket in place.

6. Remove power Irom the RM 65 bus.
CAUTION

b. Insert the solder stakes for mounting of discrete components.
power connection and test points into the desired holes and
solder to the associated feedthroughs.
C. Insert and solder individual or strip stakes into connector holes
lor all RM 65 bus signals used on the module.
d. Wire wrap wires between the protruding pins and other pins or
power/GNO traces IS requirad.

Never install or remove modules with power on it may cause damage to your module andlor host
system.
7. Insert the module in the RM 65 Bus motherboard or single cerd
adapter receptacle.
'
B. Apply power to the RM 65 bus.

•

Design Prototyping Module Physical and Electrical Characteristics
Value

Characteristic
Edge Connector Version
3.9 in. (100 mm)
6.5 in. (164 mm)
0.06 in. (1.6 mm)
2.0 oz. (55 g)

Physical Characteristics (See Notes):
Width
Length
Height
Weight
RM 65 Bus Interface
Edge Connector
Eurocard

-1;
. :::-

Eurocard Version
3.9 in. (100 mm)
6.3 in. (160 mm)
0.56 in. (14 mm)
2.5 oz. (65 g)

72-pin edge conn'ector (0.100 in. centers)
64-pin plug (0.100 in. centers) per DIN 41612 (Row b
is not installed)

Component Mounting Area:
Number of Component Hole Columns:
Number of Component Hole Rows:
Number of +5V power strips:
Number of isolated power strips:
Number of ground strips:
Vertical hole spacing:
Horizontal hole spacing:

36
36
6
4
9
0.100 in.
0.100 in.

NOTES:
1. The height includes the maximum values for component height above the board suface (0.4 in. for populated modules).
printed circuit board thickness (0.062 in.). and pin extension through the bottom of the module (0.1 in.).
2. The length does not include the added extensions due to the module ejector.
3. The Eurocard dimensions conform to DIN 41612 .

r--~;~~~MI---1 ~~~~NE~BOARD
~LENGTH~

r

WtDTH

EDGE CONNECTOR VERSION

LL-----------I

r

I

JANDRECEPTACLE

---r,

~

It

::

WIDTH

L

~

II
II
II

EUROCARD VERSION

________________________

II

~ ~EUROCON~ECTOR
EXTENSION
EUROCARD CONNECTOR

EDGE CONNECTOR

Module Dimensions

II

~~--u

PART NUMBER

RM65-7211 (E)

'1'

RM 65
DATA SHEET

Rockwell

EXTENDER MODULE
RM65

FEATURES

The RM 65 product line is designed for OEM and end
user microcomputer applications requiring state-of-the-art
performance, compact size, modular design and low cost.
Software for RM 65 systems can be developed in R65DD
Assembly Language, PLl65, BASIC and FORTH. Both
BASIC and FORTH are available in ROM and can be
incorporated into the user's system.

•
•
•
•

The RM 65 product line uses a motherboard interconnect
concept and accepts any card in any slot. The 64-line RM
65 Bus offers memory addressing up to 128K bytes, high
immunity to electrical noise and includes growth provisions for user functions. A selection of card cages
provides packaging flexibility. RM 65 products may also
be used with Rockwell's AIM 65 Microcomputer for
product development and for a broad variety of portable,
or desktop microcomputer applications.

ORDERING INFORMATION
The Extender Module is available in an Edge Connector
version (RM65-7211) and a Eurocard version (RM657211E).

Eurocard Version
RM65·7211E

o Rockwell International Co

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•

JUMPER DESCRIPTION

COMPONENT DESCRIPTION

JUMPER A - Connects address line All to pin 18 of the PROM after inverting for 2716 operation.

Connector Jl - Connector with extended pins that allows the R6500/1
Evaluation Module to be directly plugged into the R65001
1 connector in the user circuit or to be connected to the
user circuit R6500/1 connector through the 40 conductor
interface cable assembly.

JUMPER B -

Connects address line All directly to pin 18 of the PROM
for 2532 operation

JUMPER C - Connects GND to pin 18 of the PROM for 2732 operation.

Socket ZI

- 64-pin DIP socket that contains the R6S00/1 EAC 2-MHz
Emulator Device.

JUMPER D - Connects the high side 01 the external clock or crystal to pin
63 (XTLI) of the R6500/1E Emulator Device.

Socket Z2

- 24-pin DIP socket. which accepts the user-supplied program PROM

JUMPER E - Connects the low side of the external clock or crystal to pin
64 (XTLO) 01 the R6500/1E Emulator Device.

Crystal Yl

- A 2-MHz crystal. which is used to operate the R6S001
lEAC Emulator Device at 1 MHz.

JUMPER F - Connects address line All to pin 21 of the PROM for 2732
operation.

Inverter Z3

- Inverts RtW to provide a low on pin 20 of the PROM when
R/W is high.

JUMPER G - Connects +5V to pin 21 of the PROM for 2716 or 2532
operation.

- Inverts A 11 when jumper A is insta lied to provide a 13-Test point to monitor

R/W.

Post El-Crystal solder post to XTLI.
Post E2-Crystal solder post to XTLO.

DOCUMENT NO. 29650 N46
AUGUST 1978

PART NUMBERS

M65-031, M65-032
R6500 Microcomputer System

PRODUCT DESCRIPTION
16K STATIC RAM MODULE
OVERVIEW

FUNCTIONAL'DESCRIPTION

The Static RAM Module contains 16K
Access Memory (RAM), implemented
Static RAM devices. The Module also
and selection, write protection and

In reading the text to follow, refer to the Functional Block Dia·
gram below and the attached schematics:

(16,384) bytes of Random
with 32 R21,14 1024 x 4
includes address decoding
data buffering circuitry.

The Module's 16K bytes of RAM memory are segmented into two
independent 8K-byte sections. Each 8K section is controlled by
an enable/disable switch and three address range select switches,
located at the top of the Module. Each 8K section can be inde·
pendently write·protected via special lines.

The Static RAM Module is directly compatible with Rockwell's
SYSTEM 65 Microcomputer Development System, and can be
used to increase the System's read/write memory capacity from
16K bytes to 48K bytes, without hardware modification. The
Module may also be installed into user-designed equipment, via
the Auxiliary Card Cage.

FEATURES
SYSTEM 65 compatible
•

Available in 1 MHz (450 ns access) and 2 MHz (250 ns
access) versions,

•

16K bytes of Random Access Memory, with two indepen·
dent 8K sections

•

Separate write protect capability for each 8K section

•

Static - no clocks or strobes required

•

9.75 in. x 6.00 in. module

•

Single +5V supply

•

PSOO·X131, the '()01 assembly of the RAM Module

•

PSOO·X133, the -071 assembly of the RAM Module

The edge connector pin assignments for the RAM Module are
compatible with the Motherboard pin assignments given in Sec·
tion 4 of the SYSTEM 65 User's Manual (Document No. 29650
N35).
The RAM Module's 16K bytes of read/write memory are pro·
vided by 32 R2114 1024 x 4-bit Static RAM devices.
Address Buffers Z47, Z46 and Z33 and Data Buffers Z32 and
Z45 present a single TTL load to the Motherboard edge con·
nector. The data signals are inverted to make them compatible
with the SYSTEM 65 Data Bus (DO·D7).
Module Switches S1 and S2 provide independent 8K RAM section
enable/disable and address selection. S14 and S24 permit each
8K section of RAM to be enabled or disabled. S1·1,·2 and ·3
and S2·1, ·2 and ·3 select the base address to which the respective
8K sections will respond. These switch settings are compared to
upper address bits A 13, A 14 and A 15 in Address Comparator
devices Z10 and Z21. The Comparator outputs enable or disable
1·of·8 Decoder devices Z9 and Z20 to provide the input chip
select signals to the two 8K RAM sections.
Write protection is controlled by seven Write Protect lines, WP1·
WP7, one line for each 8K section of memory Ithe lowest section,
addresses $OOOO·$1FFF, may not be write protected; note that
Z48·2 is tied to ground to permanently enable writing to this
section). A low voltage on WP1·WP7 enables writing into the
associated 8K section.
When the Address Comparator enables the RAM Device Select
Decoders, Address Select switches S1·1 through 51-3 and S2·1
through 52·3 are used by Z35 and Z36 to select one of the seven
Write Protect lines, The selected line controls the RAM Write
Control signals, Z34-6 and Z34-8.

\.
.~

@

..
Rockwell International Corporation 1978
All Rights Reserved
Printed in U.S.A.

RAM Module Functional Block Diagram
Specifications subject to
change wIthout notice

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Table 1. RAM Enable/Disable Switch Settings

INSTALLATION
The procedure below should be used to install 16K Static RAM Mod·
ules in the SYSTEM 65 or, with appropriate changes, in an Auxiliary
Card Cage.
1.

Turn SYSTEM 65 power off.
CAUTION

Down (On)

RAM Enabled (Selected)

Switch S1/S2 Position

Remove the top cover of the SYSTEM 65.

Up

3.

The RAM Module has two banks of switches - S1 and S2 one bank for each SK section of RAM. Using Tables 1 and 2,
select the enable/disable and address range characteristics
for each SK section.

Down

NOTES
For proper SYSTEM 65 operation ...

I

RAM Disabled (Deselected)

Page 0 (address range $OOOO·$OOFF) and Page 1 ($0100·
$01 FF) must be provided in RAM - either internal
RAM or external RAM as interfaced by USER 65 or
its equivalent.

Insert the RAM Module(s) into any vacant slot(s) in the
SYSTEM 65 chassis.

5.

Install the top cover of the SYSTEM 65.

6.

Turn SYSTEM 65 power on.

BK Address Range Selected

-3

Up

Up

$0000

$1FFF

Up

Up

$2000

$3FFF

Up

Down

Up

$4000

$5FFF

Down

Down

Up

$6000

$7FFF

Up

Up

Down

$SOOO

$9FFF

Down

Up

Down

$AOoo

$BFFF

Up

Down

Down

$COOO

$DFFF

Down

Down

Down

$EOOO

$FFFF

NOTE: "Up" is toward the top edge of the Module.

RAM addresses in the range $COOO·$FFFF are used by
the SYSTEM 65 Monitor Board, and must not be
enabled in RAM Modules.

4.

·2

·1

2.

b.

Up (Off)

Table 2. RAM Address Range Select Switch Settings

Never install or remove modules with SYSTEM 65 power
on - It may cause damage to the module and/or to the
System.

a.

RAM Enable/Disable State

Switch S1/S2-4 Position

SPECI F ICATIONS
Memory Size:
Word Length:
Interface:
Max. Access Time:
Module Components:
Module Dimensions:
Edge Connector:
Operating Temperature:
Power Requirements:

16K bytes
8 bits
SYSTEM 65 compatible
450 ns (P/N M65-03l)
250 ns (P/N M65'()32)
32 R2l14 Static 1024 x 4-bit RAM devices
9_75 in. wide x 6.00 in. high
86 pins on 0.156-in. centers
OoC to +700 C
+5 VDC ±5% @ 3.0 amps (typical)

LOGIC LEVELS

Characteristic

Symbol

Min

Max

Unit

Condition

O.S

V

IlL = 400 I'a

2.0

VCC

V

IIH = 40 I'a

0.5

V

10L = 4S ma

VCC

V

I'OH = 10 ma

Inputs (00-07), AO-A15,
WP1-WP7, 02, R/W)
Input Low Voltage

V IL

Input High Voltage

V

Outputs

IH

(Do-51)

Output Low Voltage
Output High Voltage

VOL
V
OH

2.4

PART NUMBER

DOCUMENT NO. 29650 N42

REV. 2, FEBRUARY 1980

"

'1'
~

•• > •

~

M65-040

R6S00 Microcomputer System
PRODUCT DESCRIPTION

Rockwell
-

PROM PROGRAMMER MODULE
OVERVIEW
The PROM Programmer Module provides SYSTEM 65 users with
a means to program, verify, read and. check Programmable Read
Only Memory (PROM) devices,
2516, 2532 and 2758 devices.
connects directly ~o the PROM
SYSTEM 65 chassis, via supplied

and supports 2704, 2708, 2716,
The PROM Programmer Module
Socket on the front panel of the
cable.

-c

The Module is supplied with a mini·floppy diskette which holds a
set of software routines that allow the user to check a PROM for
proper initialization, program the PROM from SYSTEM 65
memory, verify the PROM with SYSTEM 65 memory, and read
the contents of the PROM into memory. Utility functions to
load, verify and dump memory are also supplied.

J:J

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FEATURES
•

SYSTEM 65 compatible

• Supports programming of 2704, 2708, 2516, 2532,2716
(Intel and Texas Instruments) and 2758 PROM devices.
•

Comes with software on mini·f1oppy diskette

FUNCTIONAL DESCRIPTION
In reading the text to follow, refer to the Functional Block
Diagram in Figure 1 and the attached schematic, PSOO·X201.
The edge connector pin assignments for the PROM Programmer
Module are identical to the Motherboard pin assignments given
in Section 4 of the SYSTEM 65 User's Manual (Document No.
29650 N35).
Table 1 summarizes the PROM Socket interface, and applies
to both the PROM socket located on the PROM Programmer
Module and the PROM socket located on the SYSTEM 65 front
panel.
The PROM Programmer Module consists of two R6520 Peri·
pheral Interface Adapters (PIAs), data buffers, address decoders,
26V power supply, level shifters and power·up circuitry.

The power·up circuitry (Z9) generates an automatic reset during
power·up. A reset signal may also come from the Reset line of
the SYSTEM 65 Bus.
The PROM Programmer Module contains data bus buffers, Z12
and Z13, to provide a logical inversion and a single TTL load
to the SYSTEM 65 bus signals. The two R6520 PIAs, Z5 and
Z8, are used to store the address, data and control information
for the PROM device. The address, Read/Write (R/W), and
2 signals are buffered and decoded by Z10, Zll, Z14, Z15 and
Z16. PIA No. 1 is addressed at locations $C018·$COl B. PIA
No.2 is addressed at locations $COl C·$COl F.
The PROM device receives address lines AO·A9 and data lines
00·07 directly from the PIA devices. The program lines (see
Table 1, PROM socket pin nos. 18, 19 and 20) are level·shifted
to provide either OV, +5V, +12V, +25V or +26V to the PROM
device, depending on the device type. The 26·volt power is gen·
erated from the +5·volt poiNer through a DCDC converter, Z6,
and an adjustable voltage regulator, Zl. Relays XR 1 through
XR4 are used to switch the power lines (see Table 1, PROM
socket pin nos. 21 and 23) to +5V, +12V and -5V to the PROM
device, depending on the device type. The ·5V power is gen·
erated from the ·12V power line through a voltage regulator,
09.

Note: All examples were prepared
using SYSTEM 65 Operating
System Version 3

Figure 1. PROM Programmer Functional Block Diagram
©

Rockwell International Corporation 1980
All Rights Reserved
Printed In USA

Specifications subject to
change without notice

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Table 1. SYSTEM 65 P'ROM Socket Interface Summary

PROM DEVICE INSERTION/REMOVAL
CAUTION

Int.1

Int.1

Int.1

T.I.

T.I.

T.I.

Connector
JI
Pin

Number

2704

2708

2758

2716

2716

2516

2532

Number

1
2
3
4
5
6
7
8
9
10
11
12
lJ
14
15
IS
17
18
19
20
21
22
2J
24

A7
A6
AS
A4
A3
A2
AI
AO
00
01
D2
GND
D3
D4
05
DS
07
PGM
VDD
CsIWE
VBB
GND
A8
VCC

A7
AS
AS
A4
AJ
A2
AI
AO
DO
Dl
02
GND
D3
D4
05
DS
07
PGM
VOD
CsIWE
V8B
A9
A8
VCC

A7
A6
AS
A4
A3
A2
AI
AO
DO
Dl
D2
GND
D3
D4
DS
DS
D7
CE/PGM
GND

A7
A6
AS
A4
AJ
A2
AI
AO
DO
Dl
D2
GND
D3
D4
DS
DS
D7
CE/PGM
Al0

PROM Device Type

PROM
Socket
Pin

I - - - --'- t - - - - - - - f - -

OE

VPP
A9
A8·
VCC

OE

VPP
A9
A8
VCC

A7
A6
AS
A4
AJ
A2
Al
AO
01
02
OJ
V55
04

A7
A6
AS
A4
AJ
A2
AI
AO
01
02
OJ
VS5
04

06
07
08
Cs/PGM
VDD
Al0
VBB
A9
A8
VCCtPEI

06
07
08
PO/PGM
Al0
Cs
VPP
A9
A8
VCC

as

as

A7
AS
AS
A4
AJ
A2
Al
AO
01
02
OJ
vss
04

as
as

Q1

08
A11
Al0
PD/PGM
VPP
A9
A8
VCC

21
19
17

15
2J
25
26
24

The PROM device is fragile, and dropping, twisting or uneven
pressure may break it. Never press down on the window area
of the chip
The PROM device may be inserted into SYSTEM 65 front panel socket
or into the socket located on the PROM Programmer Module.

CAUTION

22

20
18
16
10
8
S
2
4
lJ
11
9
7
5
3
1

Only one PROM device should be installed at a time -- in
either the SYSTEM 65 socket or the PROM Programmer
Module socket. Programming with PROM devices installed
in both locations may cause erroneous results and/or damage
to the PROM.
PROM INSERTION/REMOVAL ON THE
SYSTEM 65 FRONT PANEL
To insert the PROM device:
1.

Push the PROM socket lever out from the SYSTEM 65 front
panel, to release pin pressure.

'2.

Position the PROM device in front of the socket, being care·
ful to observe the Pin 1 location.

CAUTION
Incorrect PROM installation may cause PROM damage and/or
may blow Fuses Fl and F2 0" the PROM Programmer Module.

•

3.

MODULE INSTALLATION
Install the PROM Programmer Module as follows:
1.

Turn SYSTEM 65 power off.

CAUTION
Never install or remove modules with SYSTEM 65 power
on
it may cause dama(le to the module and/or to the System.
'2.

Remove the top cover of the SYSTEM 65.

3.

I nsert the PROM Programmer Module il1to any vacant slot
in the SYSTEM 65 chassis.

4.

Connect one end of the supplied callie to the connector on
top of the PROM Programmer Module and the other end to
the conl1ector mounted on the inside front panel of SYSTEM
65. Observe the correct polarity of the' plugs and sockets;
i.e., aliyn the arrows marked on the plugs and sockets.

5.

Il1st,,1I the top cover of the SYSTEM 65.

6.

Sct the SYSTEM 65 RUN/STEP Switch to RUN.

I nsert the PROM into the socket, then push up and in on the
socket lever to apply pressure to the pins.

To remove the PROM device. grasp the PROM device at each end, then
push the socket lever away from the SYSTEM 65 front panel to release
pin pressure.
PROM INSERTION/REMOVAL ON
PROM PROGRAMMER MODULE
To insert the PROM device, position the PROM device in front of the
socket, being careful to observe the PI N 1 location.

CAUTION
I ncorrect PROM installation may cause PROM damage and/or
may blow Fuses F 1 and F2 on the PROM Programmer Module.
With the PROM properly orie'nted, gently start all pins evenly into the
socket pin guides. Then press firmly and evenly on the device (avoiding
contact wi~h the light window) until the device is securely seated.
To remove the PROM device, exert an even, upward force on both
sides of the device while counteracting with a lesser, evenly-applied
downward force. This will prevent the PROM device from popping out
one side and bending or breaking pins still engaged at the other end of
the socket.

NOTE
The PROM Programmer will not operate properly if the
RUN/STEP Switch is in the STEP position.
7.

Turn SYSTEM 65 power on.

8.

The PROM Programmer Module has an automatic reset feature.
The standard power-up message should appear on the system
terminal device at power-un. A manually-initiated reset may,
however, be performed whenever required.

OPERATION
The PROM Programmer software allows checking, reading, verifying
and programming 2704, 2708, 2758,2516,2532 or 2716 type devices.
The data/instructions are copied to/from the SYSTEM 65 RAM memory in the address rongc specified by the user. Thp. user can then transfer this information to/from the diskette (Dr other I/O device) using
SYSTEM 65 software routines.

LOADING THE PROM PROGRAMMER ROUTINES
There is one PROM programmer object file supplied on the PROM
Programmer diskette, PROM"n, where "n" is the progr"m release revision letter. File PROM"n occupies from $0200 to $OFFF. User programs can be loaded starting at $1000. To load the PROM"n program,
use the SYSTEM 65 Load Command L. Then enter the file name
(PROM"n) and disk drive number desired. Since the PROM"n program
may occupy the same memory area in which user's data may reside,
an offset may be applied to the user's data to locate it to $1000 or
above (See Load, Verify and Dump functions with offset). PROM"n.
uses page 0 ($0080-$009A) and page 1 ($0100-$01 FFl.

NOTE
The SYSTEM 65 RUN/STEP switch must be in the Run position
for PROM programming.

Next, the data to be copied to the PROM device can be loaded using
the L command. In this example, the file USERIN was loaded. Type 5
(or 6) to start the routines. Next, enter the device type. If a 2716
was entered, the message TMS 2716 (Texas Instruments) PROM? will
be printed. Enter Y for yes or N for no. The routines will reprint the
device type for verification each time a new function is requested.
A single character should now be entered to indicate the function
requested as outlined in the subsequent text.


PROl1 PROGRHM~lER FOR.! MHZ SYSTEM (VER E)

ENTER 2704. 2708, 2758. 2716. 2516. 2532
-2716
THS 2716 PROM?
-N

................................
[,IEVIeE TYPE-

2716
•••••• ++ ............... .

After the program is loaded, use the five (5) key to start the PROM
Programmer routines for a 1 MHz system or the six (ii) key for a
2 MHz system. The 5 (or 6) key may also be used for reentry into
the PROM Programmer routines. Once the routines are entered, the
only way to exit back to the SYSTEM 65 monitor is to press the
ESC key, if the program is waiting for input, or the Reset switch.
The PROM Programmer PROGRAM PROM (P) and VERIFY PROM
(V) functions require that the data to be programmed and/or verified
be in RAM memory prior to execution. If the program data resides on
diskette (or other media), use the SYSTEM 65 Monitor L command to
load the object code into memory before entering the PROM programmer functions with key 5 (or 6). Alternatively, use the PROM
Programmer L command to load the program data with optional offset
after the PROM Pro~rammer functions have been entered.

vERIFY<'y'>. f"ROGRAM(.P). READ(R), OR CHECK, LOAD, DUMP

Figure 4. Verify Function Example with Errors

If fuse Fl or F2 on the PROM Programmer Module is blown,
the PROM may not verify correctly. Verify that both are
good if a verify error occurs.

(5)

PROM PROGRAMMER FOR 1 MHZ SYSTEM 

ENTER 2704. 2708.

27~8.

2716.

2~1.6. 2~l2

-2716
TMS 271.6 PROM?
-N

...........................

.........................
DEVICE TYPE2716

ENTER PROM COMMAND: VERIFY, READ, LOAD, t>UMP, MEM FILUM>, INVERT< I)

-P
PROGRAM
ERROR LIST

READ FUNCTION (THE R COMMAND)
The Read Function (R) reads the contents of PROM into SYSTEM 65.
RAM. It is entered by pressing the R key in response to the ENTER
command message .
After the first and last addresses are entered, power will be applied
to the PROM and the contents copied into the specified RAM locations. When completed, the message DONE will be printed and the
next operation requested. Figure 5 shows an example of a Read Func·
tion.

OUT-L
ENTER FIRST ADDRESS
-2000
ENTER LAST ADDRESS
-27FF
PROM NOT INITIALIZED
CONTlNUE, LOAD

Figure 3. Program Function Example
VERIFY FUNCTION (THE V COMMAND)
The Verify Function (V) verifies the contents of the PROM with the
contents of SYSTEM 65 RAM. It is entered by pressing the V key in
response to the ENTER command message.
The routines will request where any errors detected should be printed.
This is indicated by the message ERROR LIST OUT=. Enter any of the
standard I/O device characters defined in the SYSTEM 65 User's
Manual (space for CRT, P for Printer, etc'!. Next. type in the first and
last addresses. As soon as the last address is entered, power will be
applied to the PROM device and the contents of the PROM compared
to the respective content of the RAM. If no errors are found, the
message DONE will be printed, and the next operation requested. If
errors are detected, the address, contents of PROM, and contents of
RAM in disagreement will be displayed/printed on the selected I/O
device. Figure 4 shows an example of the Verify Function with errors.

<~>

PROM PROGRAMMER FOR 1 MHZ SYSTEM < VER E)
ENTER 2704,2708,2758.2716,2516, 2532
-2716
TI'15 2716 PROM'?
-N

.....................
DEVICE lVPE2716

ENTER PROM C.OMMAND: VERIFY(V). PROGRAM(P}. READi..R). OR (HECK(C)
OR MEMORY COMMAND: VERIFY(F). LOftD(L). vUMP(D). MEM FILL(M}. I NVERT ( I)
-R
READ
ENTER FIRST ADDRESS
-1000
ENTER LAST ADDRESS

-HFF

.....................

DONE

.........................
DEVICE TVPE2716

ENTER PROM COMMAND· VERIFY(V), PROGRAM"P). REFt[)i..R), OR CHECKB, 2716, 2:>16, 2532
-27j,6
TMS 27:1.6 PROM?

27~8,

271.6. 2516. 253:2

.....................

.....................
.....................

-N

=N

.....................
DEVICE TYPE2716

toEVICE TVPE-

2716

ENTER PROM COMMAND:

VERJFV, DUMP([;.), MEM FILL, LOADCL), DUMPCD), MEM FILUM), INVERT< I)
-F
VERIFY
QFFSET-D000
IN-F FlLE-AIMBAS DISK-2
ERROR LIST
OUT-L
ADDR;'MEM;'FILE
2009 £0 50
2200 4C 52

ENTER PROM COMMAND: VERIFYCV), PROGRAM(P), READCR), OR CHECK(C)
OR MEMORY COMMAND: VERIFYCF), LOFtDCL), DUMPCD), MEM FILUM), INVERT< I>

VERIFY",V). PRQ6RAM
, REAO(FO. OR CHECK
VERIFY, DUMP<[n, MEM FILL(M), INVERT( J)

Figure 6, Check Function Example

LOAD MEMORY WITH OFFSET FUNCTION (THE L COMMAND)
The Load Memory with Offset Function (Ll copies data from an input
object code file into memory addresses offset by an entered amount
from the addresses on the input file. The entered offset value is addi·
tive with carry from bit 15 ignored, e.g.;
Input File
Address

Offset
Value

Address in
Memory

$1000
$1000
$7000
$EOOO

0
$2000
$AOOO
$2000

$1000
$3000
$1000
$1000

Figure 8, Verify Memory with Offset Function Example
with Errors
DUMP MEMORY WITH OFFSET FUNCTION (THE D COMMAND)
The Dump Memory with Offset Function (D) copies data from memory
to an output object code file with addresses in the output file offset
an entered amount from the addresses in memory. The entered offset
value is additive from the output file to memory with carry from
bit 15 ignored; e.g.:
Output File
Address (FROM=)

Offset
Value

Address in
Memory

$1000
$4000
$1000
$AOOO

0
$0000
$8000
$1000

$1000
$1000
$9000
$8000

Figure 9 is an example of the Dump Memory with Offset Function.

Figure 7 is an example of the Load Memory with Offset Function.
(5)

PROM PROGRAMMER FOR 1 MHZ SYSTEM WER E>
<~>

PROM PF'OG"FtMI1ER FOR 1 MHZ SYSTEM  , DUi1PCL), DlJMPCD),I1EM FILUM), INVERTe I)

-D

OUT-F

OFFSET-DOO0

-L

IN-F

2716, 2:>16, 2:>:>2

.716

tJEVIC.E Y''I'PE2716

LOAD
OFFSET-oeee

27~8,

..........•..........

f'~OM?

.......................
ENTER FPOM COMMAND
O~ MEMOPY COMMAND

ENTEP 2704, 270B,
-.716
TMS 2716 PROM?
-N

FILE-PRMOUT

DISK-2

TO-47FF

.....................
MOf', DUMPC(»,I1EM FILLCM), INVERTeD

Figure 9, Dump Memory with Offset Function Example

•

MEMORY Fill FUNCTION (THE M COMMANO)

INVERT MEMORY (THE I COMMAND)

The Memory Fill Function (M) allows a user selected range of RAM to
be initialized to an entered bit pattern. The desired PROM object code
can then be loaded. All unloaded memory in the PROM address range
will remain initialized with the previously filled bit pattern. This
allows PROM codes over a total PROM address range to be easily veri·
fied without invalid data errors being indicated due to random bit
patterns in unused addresses.

The Invert Memory Function (I) allows selected bits to be inverted
within a selected address range. This function allows the contents
of RAM to be easily one's complemented if the PROM code is to be
inverted from the ROM code.

Figure 10 is an example of the Memory Fill Function. Enter the bit
pattern to be loaded in hexadecimal in response to the MEM Flll=
prompt. The last two digits entered will be accepted. Terminate the
entry with a carriage return. Then enter the starting and ending addresses
in hexadecimal of the RAM to be filled. Terminate entries with a
carriage return. The last four digits entered will be accepted.
<:I)
PROM PROC.R'AMMER FOR 1 MHZ SVSTEM

<. . . EP:

EJ

Figure 11 is an example of the Invert Memory Function. Enter the
bit pattern to be exclusively or'ed with memory. A "1" in a bit posi·
tion will invert the bit value while a "0" will leave the bit value un·
changed. Enter "FF" to invert all bit values and "00" to invert none of
the bit values. Terminate the entry with a carriage return. The last
two digits entered will be accepted. Enter the starting and ending
addresses as described for the MEM FilL function.

<:I>

PROM PROGRAMMER FOR 1 MHZ SYSTEM . PROGRAI1(P>. READ'R). OR CHECK'C)
01> MEMO."( C.OMMFtNO· VERIFY'F>. LOf1()'L) , DUI1P'[n.MEM FILUM,. INVERT< I )
-M

MEM F ILL-00

......................
........................

FP0r1-:1000

TO-11FF

FROM-100e

I

TO-11FF

DEYICE TYPE2716

VERIFV(\I). F'ROGRAM(P). FO:EA[lUO .. OR (.HECI«(C)
VEPIF"'~F), LOAD. IN'./ERT< 1)

Figure 10. Memory Fill Function Example

ENTER PROM COMMAND: VERIFY'V). PROGRAM'P). READ'R). OR C.HECK'C)
OR MEMORY COMMANO: VERIFy,F>, LOFtD'L), DUMP'D), MEM FILUM). INVERT< I)
-I
INVERT 8 ITS-FF

.....................

toEV 1 ('E TYPE-

2716

ENTER PROM COMMAND
OF' MEMORY C.OMMAN()

.....................
.....................

ENTER PROM COMMAND: VERIFY' V), PROGRAM'P). READ'R). OR CHECK'C)
OR MEMORY COMMAND: VERIFY'F>. LOFtD'L>, DUMP(D), MEM FILL'M). INYERT< J)

Figure 11. Invert Bits Function Example

SPECIFICATIONS
PROM Devices Supported:

2704,2708,2758, Intel 2716 and Texas Instruments 2716

Programming Time (approximately):

2704 - 100 sec.
2708 - 200 sec.
2758 - 60 sec.
Intel 2716 - 120 sec.
T.I. 2716 - 400 sec.
2516 - 120 sec.
2532 - 240 sec.

Interface:

SYSTEM 65 compatible

Module Dimensions:

9.75 in. wide x 6.00 in. high

Edge Connector:

86 pins on 0.156-in. centers

Operating Temperature:
Power Requirements:

t5 VDC ± 5% @ 750 ma (fused at 2 amps)
+ 12 VDC _+ 5% @ 50 ma (fused at Y. amp)
-12 VDC ± 5% @50ma.

Fuse Description:

Fl - AGC Y.A-250V (Bussman)
F2 - AGC 2A-250V (Bussman)

DOCUMENT NO. 29650 N47
AUGUST 1978

PART NUMBER

M65-045

...-,----_._.._-------_._-------------------------

R6500 Microcomputer System
PRODUCT DESCRIPTION
_A_ _._. _ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ __

PROM/ROM MODULE
OVERVIEW

FUNCTIONAL DESCRIPTION

The PROM/ROM Module (Part Number M65-045) permits system
read only memory to be increased by up to 16K bytes. The
Module provides 16 24-pin DIP sockets for accepting industrystandard 2708, 2716 or 2758 PROM devices, or 2316 or 2332
ROM devices. PROMs and ROMs cannot be mixed on the Module.

In reading the text to follow, refer to the Functional Block
Diagram below and the attached schematics:

The PROM/ROM Module's 16K-byte address space is segmented
into four independent 4K·byte sections. Each 4K-byte section is
provided with a switch for selecting its base address. Further, each
socket has an individual enable/disable switch, providing resolution down to 1 K bytes.

The edge connector pin assignments for the PROM/ROM Module
are identical to the Motherboard pin assignments given in Section
4 of the SYSTEM 65 User's Manual (Document No. 29650 N351.

FEATURES
•

SYSTEM 65 compatible

•

16K-byte read only memory capacity

•

Accepts 2708, 2716 or 2758 PROM devices

•

Accepts 2316 or 2332 ROM devices

•

Sockets can be individually enabled/disabled

•

Base address is switch-selectable for each 4K-byte
address space

•

Single +5V supply

•

PSOO·X-141, the -001 version of the PROM/ROM Module

•

PSOO·X·143, the -011 version of the PROM/ROM Module

The PROM/ROM Module comes with 16 sockets for accepting
the following types of memory devices:
•

Up to four 2332 ROMs, or

•

Up to eight 2316 ROMs, or

•

Up to eight 2716 PROMs, or

•

Up to 162708 or 2758 PROMs

~

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•
"

The address switches on the Module are set in accordance with
the type and number of PROM or ROM devices installed. Each
socket may also be selected by a switch. Further, each 4K address
space also has a separate switch for selection of its base add ress.
The Chip Select Logic specifies the PROM/ROM to be accessed
and the address lines from the System bus select the memory
location. The selected PROM/ROM device responds by placing
8 bits of data on the data lines (50 through (7) for transfer
to the CPU.

~
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Rockwell International Corporation 1978
All Rights Reserved
Printed in U.S.A.

-O-i-ag-r-am--j

--P-R-O-M-/R-O-M-M-O-d-u-Ie-F-u-n-ct-io-n-a-I-B-I-O-ck

Specifications subject to
change without notice

-.

I

SWITCHES AND JUMPERS
The PROM/ROM Module can accommodate a variety of standard
PROM and ROM devices. The user must configure the Module for
his specific application, and does so with various switches and jumpers
on the Module itself.
The PROM/ROM Module has a total address space of 16K bytes,
divided into four 4K·byte sections. Each 4K section has a separate
base address select switch, S3 through S6, which must be set to the
desired hexadecimal value (0 . F). For example, if Switch S3 is'set to
C, the base address for Sockets Z4, Z5, Z6 and Z7 is $COOO (where $
indicates hexadecimal)' Further, each individual socket can be enabled
or disabled from driving the Data Bus by setting/resetting Switches Sl
and S2.

There is a further restriction for ROMs: Since ROMs have chip selects,
they will only work in the proper sockets with proper base address
switch settings. For example, a 2316 ROM with CS3=l, CS2=0 and
CSl =1 will work only in Socket Z22 (see Table 4) and with a selected
base address value of 2,6, A or E.

As mentioned above, the PROM/ROM Module must also be jumper·
configured for the device being used. Jumper information is given
with switch select tables. The function of each jumper is summarized
in Table 1.

Table 1. PROM/ROM Board Jumper Functions
Jumper No.

Jumper Function

1

•

Connects A 12 to Pin 18 of all sockets

2

Enables 1 K address selection

3
4

Connects +12VDC to Pin 19 of all sockets

5

Connects A 13 to Pin 21 of all sockets

6

Connects A 10 to Pin 19 of all sockets

7

Connects All to Pin 21 of all sockets

Enables 2K address selection

8

Connects +5VDC to Pin 21 of all sockets

9

Connects All to Pin 18 of all sockets

10

Connects -5VDC to Pin 21 of all sockets

11
12

Connects GND to Pin 18 of all sockets
Enables active low chip selects on Sockets Z7, Z14, Z22 and Z29

Table 2. Switch Settings for 2716 PROM Operation
Base Address
(A15, A14, A13, A12)

Address A11

Socket

Enable/Disable Switch

S3 (O·F)

0
1

Z5
Z7

Sl·2
S14

S4 (O·F)

0
1

Zll
Z14

Sl-6
SI-8

S5 (O·F)

0
1

52·2
S24

S6 (O·F)

0
1

Z18
Z22
Z24
Z29

S2·6
S2-8

For 2716 PROMs, add Jumpers 4,6,8,11 and 12.

Table 3. Switch Settings for 2708 or 2758 PROM Operations
Base Address
(A15, A14, A13, A12)

Address
A11 A10

Socket

Enable/Disable Switch

53 (O·F)

0
0
1
1

0
1
0
1

Z4
Z5
Z6
Z7

SI-1
Sl·2
Sl·3
S14

S4 (O·F)

0
0
1
1

0
1
0
1

Z10
Z11
Z13
Z14

Sl·5
Sl-6
Sl-7
SI-8

S5 (O·F)

0
0
1
1

0
1
0
1

Z17
Z18
Z21
Z22

S2·1
S2·2
S2-3
S24

S6 (O·F)

0
0
1
1

0
1
0
1

Z23
Z24
Z28
Z29

S2·5
S2-6
S2·7
S2-8

I

For 2708 PROMs, add Jumpers 2, 3, 4, 11 and 12 and add Capacitors C6-C9, C14-C17, C21-C24, C29-C32, C37-C40, C45-C48, C52·C55 and C59·
C62. All capacitors are 0.1 Ilf.
For 2758 PROMs, add Jumpers 2, 8, 11 and 12 and jumper left post of Jumper 3 to right post of Jumper 4.

Table 4. Switch Settings for 2316 ROM Operation

I

ROM Chip Selects·
A12
CS2

A13
CS3

Base Address
(A15, A14, A13, A12)

0

S3 (0,4,8, C)

0

Socket

Enable/Disable Switch

0
0

0
1

Z5
Z7

51·2
51-4

1
1

0
1

Zll
Z14

51-8

Z18
Z22

52·2
S2-4

Z24
Z29

S2~

0

S4 11,5,9, D)

A11
CS1

0

S5 (2, 6, A, E)

1
1

0

0

0

1

56 (3,7, B, F)

1
1

1
1

0

1

Sl~

S2-8

-Assumes CS1=All, CS2=A12 and CS3=A13
For 2316 ROMs, add Jumpers 1,4,5 and 6

Table 5. Switch Settings for 2332 ROM Operation
Base Address
(A15,A14, A13, A12)

ROM Chip Selects·
A13
A12
52
51

Socket

Enable/Disable Switch

S3 1O,4,8,C)
54 (1,5,9, D)

0

0

Z7

Sl-4

0

1

Z14

S1-8

S5 (2,6, A, E)

1

0

Z22

S2-4

S6 (3,7, B, F)

1

1

Z29

S2-8

- Assumes Sl =A 12 and S2=A 13
For 2332 ROMs, add Jumpers 2, 5,6 and 9

INSTALLATION
The procedure below should be used to install PROM/ROM Modules
in the SYSTEM 65 chassis or, with appropriate changes. in an Auxiliary Card Cage.
1. Turn SYSTEM 65 power off.

CAUTION
Never install or remove modules with SYSTEM 65 power
on - it may cause damage to the module and/or to the
System.
2. Remove the top copver of the S¥STEM 65.

3. Set the switches on the PROM/ROM module per Tables 2
through 5. The base memory addresses are assigned by four
hexadecimal switches, S3 through S6. Individual sockets are
enabled/disabled by Switches Sl and S2.
4. Install the required jumpers per directions given with the switch
table.
5. Install the required PROM ·or ROM devices in their appropriate sockets.
6. Insert the PROM/ROM Modulels) into any vacant slot Is) in
the SYSTEM 65 chassis.
7. Install the top cover of the SYSTEM 65.
8. Turn SYSTEM 65 power on.

•

I,

SPECIFICATIONS
Memory Capacity:

16K bytes

Word Length:

8 bits

Interface:

SYSTEM 65 compatible

Module Components:

16 24-pin DIP sockets

Module Dimensions:

9.75 in. wide x 6.00 in. high

Edge Connector:

86 pins on 0.156-in. centers

Operating Temperature:
+5 VOC + 5% @ 500 mao with no devices
installed

Power Requirements:

LOGIC LEVELS

Characteristic

•

Symbol

Min

Max

Unit

Condition

0.8

V

IlL = 400 Ila

Vec

V

IIH= 4O lla

0.5

V

IOL = 48 ma

VCC

V

IOH=10ma

Inputs 100.07, AO·A15,
~2, RiW)
Input Low Voltage

V

Input High Voltage

V

IL
IH

2.0

Outputs 100·51)
Output Low Voltage

VOL

Output High Voltage

V

OH

2.4

PART NUMBER

M65-071

R6500 Microcomputer System
PRODUCT DESCRIPTION
DESIGN PROTOTYPING MODULE
OVERVIEW
The Designing Prototyping Module (Part Numoer M65071) allows development of custom circuits for installation in either Rockwell's SYSTEM 65 Microcomputer
Development System or in user-designed equipment, via
the Auxiliary Card Cage.

The pin assignments for the Design Prototyping Module's
86-pin edge connector are identical to the Motherboard
pin assignments given in Section 4 of the SYSTEM 65
User's Manual (Document No. 29650 N35).

C

m

en

-

This Module is a SYSTEM 65-compatible printed circuit
module with no mounted components, but with prerouted power bus and power return lines. Spaced beside
the power lines are plated-through holes that permit wirewrap sockets to be installed. Additional holes, at the top
edge of the Module, permit a variety of wire-wrap flat
ribbon cable connectors to be installed.

C)

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C> Rockwell Inlernalionll Corporllion 1980
All RlghlS Reserved
Printed in U. SA

Specificalions subjec1lo
chonge without notice

Document No_ 29850 N41
Rev_ 1, November 1910

•

I

INSTALLATION
The procedure below should be used to install a Design Prototyping Module in the SYSTEM 65 or, with appropriate changes,
in an Auxiliary Card Cage.

3.

Insert the Design Prototyping Module into any vacant
slot in the SYSTEM 65 chassis.
CAUTION

1.

Turn SYSTEM 65 power off.
Installation of improperly-operating circuits may
cause malfunction and/or damage to the SYSTEM 65.

CAUTION
Never install or remove modules with SYSTEM 65
power on - it may cause damage to the module
and/or to the System.
2.

4.

Install the top cover of the SYSTEM 65.

5.

Turn SYSTEM 65 power on.

Remove the top cover of the SYSTEM 65.

SPECIFICATIONS
Component Mounting Area:
Number of Component Rows:

14

Number of Hole Rows:

35

Vertical Hole Spacing:

46 holes on O. Hn. centers

Horizontal Hole Spacing:

35 holes on either 0.3- in.
or O.l·in. centers

Flat Ribbon Connector Mounting Area:
Number of Pins Per Connector

170

Module Dimensions:

7.50 in. high x 9.75 in. wide
x 0.062 in. thick

Edge Connector:

86 pins on 0.156·in. centers

PART NUMBER

DOCUMENT NO. 29650 N41
AUGUST 1978

M65-060

R6S00 Microcomputer System
PRODUCT DESCRIPTION

EXTENDER CARD
OVERVIEW

INSTALLATION

The Extender Card is used to provide easy access to a printed
circuit module installed in its system enclosure, for signal tracing
or troubleshooting. In that context, the Extender Card consists
of a series of bus lines connecting the Card's standard contact
edge, on one end, and a connector used for accepting the standard contact edge of an 86-pin system module.

The procedure below should be used to install an Extender Card
in the SYSTEM 65 chassis or, with appropriate changes, in an
Auxiliary Card Cage.
1. Turn SYSTE M 65 power off.

CAUTION
This contact edge and the edge connector pins are connected
pin-for-pin via the bus lines on the Card. Each of the bus lines
is provided with a clip-on terminal to allow test equipment to
be readily connected_ With the module under test connected
to the Extender Card and this assembly installed in the system's
Auxiliary Card Cage or SYSTEM 65 chassis, the user is given
free access to both sides of the module being tested.
The edge connector pin assignments for the SYSTEM 65 Motherboard are given in Section 4 of the SYSTEM 65 User's Manual
(Document No. 29650 N35).

SPECIFICATIONS
Edge Contacts:

86 pins on 0.156-in. centers

Edge Connector:

86 pins on 0.156-in. centers

Extender Card Dimensions:

9.75 in. wide x 9.00 in. high
x 0.062 in. thick

Never install or remove modules with SYSTEM 65
power on - it may cause damage to the module
and/or to the System.

5. Insert the desired circuit module into the plug on top of
the Extender Card.

s.

6. Turn SYSTEM 65 power on.

m

2. Remove the top cover of the SYSTEM 65.
3. Remove the desired circuit module from SYSTEM 65,
if installed.

m

4. Insert the Extender Card into any vacant slot in the SYSTEM 65 chassis.

2

C

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@

Rockwell International Corporation 1978

All Rights R.served
Printed in U.S.A.

Speclflcatlonl lubJect to
change without notlc.

:.

-

I

Cut the Cost of Your System Development With ...

'1'
R6500 Macro Assembler
Rockwell

and Linking Loader
Macro Assembler Features
• Macro definition and call
• Absolute and relocatable object code
• Conditional assembly capability
• Symbol cross·reference table

The R6500 Macro Assembler and Linking Loader (Part
No. M65·650) is a minifloppy diskette·based software
package to support the Rockwell SYSTEM 65
Microcomputer Development System. The R6500
Macro Assembler transiates symbolic source code
into absolute or relocatable object code.
The absolute code may be directly executed on any
6500·famlly CPU-6502, 6503, 6504, etc.- or on the
R6500/1 single·chip microcomputer. Absolute and
relocatable object files generated by the Macro
Assembler can be subsequently combined into a
single object file, or "load module", using the Linking
Loader. The Macro Assembler and Linking Loader are
both written in assembly language, to maximize
system efficiency.
The Macro Assembler
The Macro Assembler has all of the features of
SYSTEM 65's ROM·resident, two· pass assembler,
plus a variety of additional features that are aimed at
increasing your programming productivity. It enables
a programmer to call repeatedly·used instruction
sequences with a single "macro" statement. It also
allows large programs to be developed in small, easy·
to·handle modules.

And a conditional assembly feature permits sections
of source code to be included in (or excluded from)
the assembly, depending on certain user·specified
parameters. Besides object code, the Macro
Assembler generates a cross reference synbol table,
which lists the memory address where each label is
defined, and the line number of each instruction that
references that label.

Linking Loader Features
• Interactive or command file input
• Generates load map and absolute object code

Assembler Directives
Assembly Listing Control
.TIL
Title
.SKI
Skip
.SBTIL
Subtitle
.ERR
Error
.PAG
Page
Source File Control
.END
End of Assembly
.FILE
Next File
.lNCL
Include
Data Storage
.BYTE
Initialize byte memory location
.WORD
Generate 16·bit address
.DBYTE
Generate 16·bit data word
.SBYTE
Initialize ASCII string
Equate
Assign value to symbol
Option Control
.OPT
Option
Assembly listing
LlST/NOLIST
Object code listing
GEN/NOGEN
ERR/NOERR
Error generjltion
SYM/NOSYM
Symbol generation
CREF/NOCREF
Cross reference
generation
Absolute object code
ABS
Relocatable object
REL
code
Absolute object code
MEM
to memory
Table of contents
TOC/NOTOC
OBJ/NOOBJ
Object code generation
Macro definition
MD/NOMD
Macro expansion
ME/NOME
CC/NOCC
Conditional list
Page length
PLEN
Line length
LLEN
FF/NOFF
Form feed
CLS
Clear definitions
.RAD
Radix
2,8, 10, or 16
Relocatlon/Llnklng
.DEF
Internal definition
.REF
External reference
.ZREF
Zero page reference
.PSECT
Program section
.IDENT
Module identification
Condlllonal
.IF
Condition
Complementary condition
.ELSE
End of conditional
.EIF
Macro
.MACRO
Define Macro
.ENDM
End of macro definition
.MEXIT
End of macro expansion
.NARG
Number of passed arguments

Document No. 29850 N84 Aprtl, 198Q

•

I

The linking Loader
The Linking Loader combines independently·
assembled object modules (absolute or relocatable)
Into a single, executable object file. Linking commands
can be entered interactively from the system terminal
or from a prevlously·prepared command file.
For More Information •••
. On the R6500 Macro Assembler and Linking Loader
(Part No. M65-650), SYSTEM 65, AIM 65 or the rapidly
growing family of R6500 products, contact
ROCKWELL INTERNATIONAL
P.O. Box 3669, RC55
Anaheim, CA 92803
Attn: Marketing Services
or phone 7141632·3729.

•

linking Loader Directives
ERR
OBJ
MAP
CALS
SYM
DEBUG
ORG
ORDER
DEF
LOAD
END

Errors destination
Object code generation
Load map generation
Symbol table location
Global symbol table
Debug symbol table
Origin
Section order
Symbol definition
Load code specification
Command file end

MACRO
ASSEMBLER

~--.--------------------------------------------------------------

Now Rockwell Cuts The Low-Cost of R6S00 Designing ...

'1'

Rockwell

Pl/65
A High-Level Language
for the
R6500 Microprocessor Family

In Rockwell's SYSTEM 65, you have one of the industry's
most cost-effective microcomputer development
systems. By coupling SYSTEM 65 with the advanced
low-cost PU65 Compiler option, you're even further
ahead with valuable savings in time, effort and cost.
Resembling PU1 and ALGOL in general form, PU65
is designed to improve your productivity and efficiency
by simplifying the overall software development effort.

The coding is easier, since PU65's powerful, high level
language statements enable you to implement even
complex applications with minimal programming.
Program readability is enhanced by the self-documenting
nature of PU65. This results in programs that are easier
to understand. These programs are easier to update,
too, which means lower maintenance costs.

'1'

Rockwell International

PU6S = Software Simplification
All language features are aimed at improving productivity
by simplifying software development. PU65's structured
programming support features encourage modular
program design, and its general control structure for
conditional and iterative looping allows the language
to be applied to highly structured programs.
Coding Flexibility ... When You Need It Most
PU65 allows you to freely mix assembly language
instructions in portions of the program where timing
or code optimization requirements are critical.
This flexibility carries through the compile cycle: The
PU65 compiler outputs source code to SYSTEM 65's
resident assembler, rather than object code. You'll
be able to enhance or debug at the assembler level
and indeed to drop. into assembly language whenever
you desire - a big plus in structured programming.
PU65 thereby provides the structuring potential and
programming simplicity of a high·level language, while
retaining the power and flexibility of an assembler.
No "Hidden" Memory Costs With PL/65
And while other microcomputer high·level languages
require adding more memory to the host development
system, PU65 runs with only 16K bytes of RAM - and
that comes standard with every SYSTEM 65 as do
the dual minifloppy disk drives.
For PDP 11 Users
A PU65 Compiler and an R6500 cross·assembler are
also available for installation using the RT-11 operating
system.
The PU65 Package
A pre-programmed minifloppy diskette and the
comprehensive PU65 User's Manual is available now
from Rockwell and your local Hamilton/Avnet
distributor.

For more information on PU65, SYSTEM 65, AIM 65,
or the rapidly growing family of R6500 products,
contact
ROCKWELL INTERNATIONAL
Microelectronic Devices
P.O. Box 3669
Anaheim, CA 92803
Attn: Marketing Services
0/727
RC55
or phone 714/632-3729.
PU65 LANGUAGE STATEMENTS
Declaration
DECLARE
DEFINE
DATA
Comment
Assignment
Single-Byte Move
Multiple-Byte Move
Imperative
SHIFT
ROTATE
CLEAR
SET
CODE
HALT
WAIT
STACK
UNSTACK
INC
INCW
DEC
DECW
PULSE

Specification
ENTRY
EXIT
Conditional
IF·THEN-ELSE
IF·THEN
BEGIN-END
CASE
Branching
GOTO
CALL
RETURN
RTI
BREAK
Looping
FOR-TO·BY
WHILE

NMOS
MEMORY
PRODUCTS

•

•

DOCUMENT NO. 29000 043
REVISION 3, MAY 1979

'1'

PART NUMBERS

R23168 and R2316E

R6500 Microcomputer System
DATA SHEET

Rockwell

2048 X 8 STATIC READ ONLY MEMORY
DESCRIPTION

GND

The R2316B and R2316E high performance read only memories
are organized 2048 words by 8 bits with access times of less than
450 ns. These ROMs are designed to be compatible with all
microprocessor and similar applications where high performance,
large bit storage and simple interfacing are important design considerations. These devices offer TTL input and outp\Jt levels
with a minimum of 0.4 Volt noise immunity in conjunction
with a +5 Volt power supply.

00

AD

01

A1

Q2

A2

Q3

A3

04

A4

as

AS
The R2316B and R2316E operate totally asynchronously. No
clock input is required. The three programmable Chip Select
inputs allow eight 16K ROMs to be OR-tied without external
decoding. The R2316E features a high-speed chip select response
for use in time-critical applications such as multiplexed control
lines. Both devices offer three-state output buffers for memory
expansion.

Q6

AS

07

m
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Z

Block Diagram

!(
~

2048 x 8 Bit Organization
Single +5Volt Supply
Max. Access Time - 450 ns
Totally Static Operatiol'!
Completely TTL Compatible
Three-State Outputs for Wire-OR Expansion
Three Programmable Chip Selects
Chip Select Times
250 ns max for R2316B
- 120 ns max for R2316E

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o

Ordering Information

CI)

Order Numa-: R2316

)C

MT •
M •

OOC to +700 C
-4Q0C to +850 C
Undustrian
-550 C to+125OC
(Military)
MIL-5TD-883;
Class B

Package:
C • Ceramic
P • Plastic
(Not Available for
M or MT suffix)
Model:
B •
E -

2316B
2316E

NOTE: Contact your local Rockwell Representative for availability.

Rockwell International Corporation .1979
All R'IIhts Reserved
Printed in U.S.A

CI)

Temperatura Range:
No suffix •
E •

@

en
~

:II

FEATURES

--L

....

G)

-t
(;

Designed to replace two 2708 8K EPROMs, the R2316B and
R2316E can eliminate the need to redesign printed circuit boards
for volume mask programmed ROMs after proto typing with
EPROMs.

•
•
•
•
•
•
•
•

:II

N
W

:a

vee

A7
AS
AS

o

AS
A8

M
A3
A2
A1

-

~

S3"
S1"
A10
52"
07

AD
01

as
as

02

04

GND

03

00

"Mask Programmable Option S/!!f/NC

Pin Configuration
Specifications subject to
change without notice

SPE.CI FICATIONS
Maximum Ratings
Rjlting

Symbol

Supply Voltage
Input Volt~ge
Operating Temperature
Commercial
Industrial
Military
Storage Temperature

VCC
Vin
TA

Value

Unit

-0:3 t~ +7.0
-0.3 to. +7.0

Vdc
Vdc
OC;·

o to +70
-40 t~ +85
-55 tq +125
-55 to+150

TSTG

.,

°C

This device contains input protection against damage due to high static voltages or electric fields; however. precautions sh~uld be taken to
avoid application of voltages higher than the maximum rating.

Electrical Characteristics
VCC = 5.0V ±10% (unless otherwise specified)
Symbol

Test Conditions

Min

Max

Units

2.4

VCC
0.4

Volts

Vec = 4.5V. IOH = -200 jJA

Volts

VCC = 4.5V.I OL = 2.1 rnA

VCC
0.8

Volts
Volts

See Note 1

Input Load Current

10

IJA

VCC = 5.5V.OV S VinS 5.5V

Parameter

V OH

Output HIGH Voltage

VOL
V
IH
V
IL
III
I
LO

Output LOW Voltage

Output Leakage Current

±10

IJA

Chip Deselected. V CC a 5.5V

ICC

Power Supply Current

65

rnA

Vout = +O.4V to V CC
OoC to 70 0 C

Input HIGH Voltage

2.0

Input LOW Voltage

-0.5

0

,

0

75

-40 Cto +85 C

80

-55°C to +125 0 C
Output Unloaded

••••

•
--

CI

Input Capacitance

Co

Output Capacitance

7

pF

Vce = 5.5V, V in = Vec
All pins except pin under test tied to AC ground
except V CC = 5.5V

10

pF

T A = 25 0 C, f = 1.0 MHz, See Note 2

Note 1: Input levels that swing more negative than -0.5V may be clamped and may cause damage to the device.
Note 2: This parameter is periodically sampled and is not 100% tested.

Timing Characteristics
vCC = 5.0V ±10% (unless otherwise specified)
R2316E

R2316B
Symbol

Parameter

Min

t ACC

Address Access Time

tco

Chip Select Delay

tDF

Chip Deselect Delay

10

tOH

Previous Data Valid After
Address Change Delay

20

Max

Min

Max

Units

Test Conditions

450
475
550

450
475
550 .

ns

OOCto 70 0 C
0
0
-40 C to 85 C
-55 0 C to 1250 C
Output load: 1 TTL load and 100 pF

250

120

ns

250

100

ns

Input transition time: 20 ns

ns

Timing reference levels:
Input: 1.5V
Output: O.BV and 2.0V

20

Timing Diagram
ADDRESS
INPUTS

"'~"""'IN><"V""A"""'L""ID""""7.~

VALID

~--------------------------~

CHIP~

~~;~;;I

~

B_LE_D~_______~--~-C~~~~~

tc_o_.____________
EN_A
__

DATA
OUTPUTS HIGH IMPEDANCE

~~

~I------tACC----~

~~C:J{~aT

________

HIGH IMPEDANCE

Typical Characteristics
Supply Current ys Supply Voltage

Supply Current ys Ambient Temperature
70

70

60

60

so

1

40

I
_~

30

50

-5S0
I

1 40
a
.J:! 3D

.................

...... ~)'yp

~{
............. ~2S0

20

V
·S.5Vcc

-I

~OO

-30°

0°

30°

60°

/

~

20

I

10

~V\Cp.\...........

TA ·2SoC-

10

1

I I

o3.S

90° 120° 1S00

4.0

4.5

T A - AMBIENT TEMPERATURE .oc

S.O

5.S

6.0

6.S

7.0

Vee-VOLTS

Access Time ys Ambient Temperature
700
600
SOO

..c
I

u
u

..<
CO

The R2332 operates totally asynchronously; no clock input is
required_ Two mask-programmable chip select inputs allow up to
four R2332 32K ROMs to be OR-tied without external decoding.
The device provides three-state output buffers for memory expansion. The R2332 offers TTL input and output levels with a minimum noise immunity of 0.4 volts.

(I)

~

t28

n

256

FEATURES

:IJ

•
•

C

•
•
•
•
•
•
•
•

m
~

32,768 bits, organized in 4,096 8-bit words
Max access time: 250 ns for R2332·25
300 ns for R2332·3
Typical power dissipation is 350 mW
Drives one TTL load and 100 pF
Single +5·volt power input
Totally static operation, no clock input required
Completely TTL compatible
Two mask-programmable chip select inputs
Three state outputs for memory expansion
Identical cycle and access time

o
Z

r-

<

R2332 Block Diagram
Order Number:

A7

24

VCC (+5V)

A6

2

23

A8

A5

3

22

A9

A4

4

21

S2/S2INC·

A3

5

20

Sl/SlINC·

A2

6

19

Al0

18

All

Al
AO

8

17

07

00

9

16

06

01

10

15

05

02

11

14

04

GND

12

13

03

• Mask-programmable oDtion

R2332 Pin Configuration

co Rockwell InternatIOnal CorporatIon
All RIghts Reserved
Pronted In USA

1980 .

3:
m
3:

R2332' __ [
~-

Temperature Range:
No suffix "OoC to +70 0 C
0
E = -40 0 C to +85 C
(industrial)
Package:
C = Ceramic
P = Plastic
Access Time (Max):
25 = 250 ns t

ACC
3 " 300 ns t ACC

NOTE: Contact your local Rockwell Representative for avail·
ability. Submit ROM codes using the Rockwell'NMOS
ROM Code Order Form, Document No. 29650 N80.

Specifications subject to
Change without notice
Document No. 29000 D48
Rev. 4. August 1980

o
:IJ
<

'$

o

~

•

SPECIFICATIONS
Maximum Ratings.
Symbol

Rating
Supply Voltage
Input Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature

VCC
V
in
T

T

Value

Unit

-0.5 to +7.0
-0.5 to +7.0

Vdc
Vdc
°c

o to +70
-40 to +B5
-65 to +150

STG

°c

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to
avoid application of voltages higher, than the maximum rating.

Electrical Characteristics
VCC

= 5.0V ± 5% (unless otherwise specified)
Symbol
VOH

Output HIGH Voltage

VOL
V
IH
V
IL

Output LOW Voltage

III
I
LO

C

Typ

Min
.2.4

Input HIGH Voltage

2.0

Input LOW Voltage

-0.5

I

Co

Max

Units

VCC
0.4

Volts

VCC

Volts

VCC

VCC
O.B

Test Conditions

= 4.75V,I OH = -200 IJA'
= 4.75V,I OL = 2.1 mA

Volts
Volts

Input Load Current

10

P.A

Output Leakage Current

±10

IJA

VCC - 5.25V, OV S V in :::: 5.25V
Chip Deselected, VCC = 5.25V,
Vout = +OAV to VCC

mA

VCC

VCC = 5.0V, chip deselected,
0
pin under test at OV, T A = 25 C,
f = 1 MHz

Power Supply Current
Commercial Temp
Industrial Temp

ICC

I

Parameter

70
70

= 5.25V

135
150

Input Capacitance

7

pF

Output Capacitance

10

pF

Timing Characteristics
VCC

= 5.0V ± 5% (unless otherwise specified)

Parameter

R2332-25
Max

R2332-3
Max

Units

Test Conditions

tA

Address Access Time

250

300

ns

Output load:
1 TTL load, 100 pf
Input transition time: 20 ns

tco

Chip Select Delay

150

150

ns

tDF

Chip Deselect Delay

150

150

ns

Timing reference levels:
Input: 1.5V
Output:· O.BV & 2.0V

Symbol

Timing

~~~~SS~

V_A_~_ID

________________

~;;~i~
DATA
OUTPUTS

____________- - J

_________________

~
f~

EN_A
__
B_LE_D
______________

~I~tco

I

INVALIDX;~~~~=":,,:,:,

~~~~~;c.:f~~-----J ,~~~SC~~fHIGH IMPEDANCE

HIGH IMPEDANCE to _----______

Typical Characteristics
Supply Current

120

120

80

I
U
_U

Ambient Temperature
140

100

: 1.',):i. :'~2~.::':;::·.\: "

LOW-POWER
4096 x 8 STATIC READ ONLY MEMORY
MASK PROGRAMMABLE
OPTION

DESCRIPTION
GND

The R2332-L, R2332-4L and R2332-35L are 32,76B·bit static
Read Only Memories (ROMs), organized as 4,096 eight·bit bytes,
that offer maximum access times of 450, 400 and 350 nanoseconds, respectively. Like their high·speed counterparts, the
R2332-25 and the R2332-3 (see Rockwell Documen't No,
29000 D4Bl. these ROMs are in industry·standard, 24 pin, dual
in-line packages, and are available in ceramic or low-cost plastic.
However, R2332-xL series ROMs operate with a typical power
dissipation of only 240 mW.

SII51 INC

S2lSi/NC

r-

o
:E

32.768 BIT
ROM
CelL ARRAY

I

-0

o

:E
m

All three R2332-xL ROMs operate asynchronously, and require
no clock input. Two mask-programmable chip select inputs
allow up to four 32K ROMs to be OR-tied without external
decoding, These devices provide tri·state output buffers for
memory expansion. The R2332-xL ROMs offer TTL input and
output levels with a minimum noise immunity of 0.4 volts.

::D
~

12B

o

(D
0)

256

)(

FEATURES
•
•

•
•
•
•
•
•
•
•

CO

en

32,768 bits, organized in 4,096 B-bit bytes
Max access time: 450 ns for R2332-L
400 ns for R2332-4L
350 ns for R2332-35L
Typical power dissipation is 240 mW
Drives two TTL loads and 100 pF
Single +5-volt power input
Totally static operation, no clock input required
Completely TTL compatible
Two mask·programmable chip select inputs
Three state outputs for memory expansion
Identical cycle and access time

~

-4

o
::D

m

A6

2

A5

24

VCC (+5V)

23

AB

22

A9

A4

4

21

S2/S2/NC*

A3

5

20

Sl/Sf/NC*

A2

6

19

Al0

lB

All

Al
AO

B

17

07

00

9

16

06

01

10

15

05

02

11

14

04

GND

12

13

03

* Mask.programmable oPtion

R2332 Pin Configuration

«:> Rockwell

Inlernal'onal Corporallon 1980
All Rlghls Reserved
Pnnled In USA

C

o
2

Ordering Information
Order Number:

A7

:J>

R2332 Block Diagram

!(

R2332-__ L __
- - LTemperature Range:
No suffix = OOC to +70 0 C
0
0
E = -40 C to +B5 C
(industrial, avail·
able only for
R2332-L)
Package:
C = Ceramic
P = Plastic
Access Time (Maxi:
No prefix = 450 ns t
ACC
4 = 400 ns t
ACC
35 = 350 ns t
ACC

NOTE: Contact your local Rockwell RepresentativlI for availability. Submit ROM codes using the Rockwell NMOS
ROM Code Order Form, Document No. 29650 NBO.
Specifications subject to
change without notice
.:>acumant No. 29000 061
Augultl980

3:
m
3:

o

::D

-<

•

SPECI FICATIONS
Maximum Ratings
Symbol

Rating
Supply Voltage
Input Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature

VCC
V in
T

T

Valul

Unit

-0.5 to +7.0
·0.5 to +7.0

Vdc
Vdc

°c

o to +70
-40 to +85
-65 to t150

STG

°c

~

This device contains input protection against damage due to high static voltages or electric fields; however. precautions should be taken to
avoid application of voltages higher than the maximum rating.

Electrical Characteristics for R2332·L and R2332-4L
VCC = 5.0V ± 10% (unless otherwise specified)
Symbol

Parlmeter

V OH

Output HIGH Voltage

VOL
V
IH
V IL

Output LOW Voltage

III
I LO

Min
2.4

C
I
Co

Max

Units

VCC
0.4

Volts

V CC = 4.5V. IOH = ·240 IJA

Volts

VCC = 4.5V. IOL = 3:7 mA

Test Conditions

VCC
0.8

Volts

Input Load Current

10

IJA

V CC = 5.5V. OV ~ Yin ~ 5.5V

Output Leakage Current

±10

IJA

Chip Deselected. V CC = 5.5V.
Vout = +O.4V to Vcc
VCC = 5.5V

Input HIGH Voltage

2.0

Input LOW Voltage

-0.5

Volts

mA

Power Supply Current
Commercial Temp
Industrial Temp

Ia:C

Typ

48
48

I

87
101

Input Capacitance

7

pF

Output Capacitance

10

pF

VCC = 5.0V. chip deselected.
0
pin under test at OV. T A = 25 C •
f = 1 MHz

Electrical Characteristics for R2332·35L
VCC - 5.0V

± 5% (unless otherwise specified)

Symbol

Parlmeter

Min

Typ

Units

VCC
0.4

Volts

VCC = 4.75V. IOH = ·240 IJA

Volts

VCC = 4.75V. IOL = 3.7 mA

Test Conditions

Output HIGH Voltage

VOL
V IH

Output LOW Voltage
Input HIGH Voltage

2.0

V IL

Input LOW Voltage

-0.5

ILl
I LO

Input Load Current

10

IJA

VCC = 5.25V. OV

Output Leakage Current

±10

IJA

Chip Deselected. VCC = 5.25V.
Vout = +O.4V to VCC

ICC

Power Supply Current

mA

VCC = 5.25V

VCC = 5.0V. chip deselected.
0
pin under test at OV. T A = 25 C.
f = 1 MHz

Commercial Temp

C

I
Co

2.4

Max

VOH

VCC
0.8

48

Volts

;

Volts

:s

Yin ~ 5.25V

87

Input Capacitance

7

pF

Output Capacitance

10

pF

Timing Characteristics

vCC

a

5.0V ±.10% for R2332·L and R2332-4L, VCC

a

5.0\1 ±.5% for R2332-35L

R2332-L

R2332-4L

R2332-35L

Max

Max

Max

Address Access Time
Commercial Temp
Industrial Temp

450
450

400

350

-

-

tco

Chip Select Delay

120

120

tDF

Chip Deselect Delay

100

100

Symbol
tA

Parameter

UniU

Test Condition.

ns

Output load:
2 TTL loads, 100 pF
Input transition time: 20 ns

120

ns

100

ns

Timing reference levels:
Input: 1.5V.
Output: O.BV & 2.0V

Timing

~~~~iSS ~_______________V__A_L_ID____________

--J

~~1~~; ~~I~_o________________

~

E_N_A_B_L_ED
______________

DATA
OUTPUTS

1_-----------~:QQs;::Q~~>f-~-----J

.

HIGH IMPEDANCE ...

•

Packaging Diagram
Ceramic: Package

Pilitic PKkage

I

Typical Characteristics
Supply Current vs Ambient Temperature

Supply Current vs Supply Voltage

70

60
50

<

E

40

I

0
_0

70
~

"

60

1"JI

'lJic.,

......... ~

30

---

\ .".

250

..

c
I

0
0

..<

200

~~

. "'"

4.5

5.0

5.5

VCC,.vOLTS

350

•

........

20

20

o

_____
r'1'1\l\~\

50

./

150
100

V

50

2 TTL LOADS
C -100pF
L

CC

I

-5.0V

I

T A' AMBIENT TEMPERATURE.oC

6.0

6.5

7.0

PART NUMBERS
R2364A2,R2364A25,R2364A3

'1' 'ROCkW~li
-'

,

PRODUCT PREVIEW

8192 X 8 STATIC READ ONLY MEMORY
The R2364A2. R2364A25 and R2364A3 are 65.536-bit static
Read-Only Memories (ROMs). organized as 8.192 eight-bit
bytes. that offer maximum access times of 200. 250 and 300
nanoseconds. respectively. These ROMs are in industrystandard 28-pin. dual in-line packages. and are available in
ceramic or low-cost plastic. These fully-static 64K-bit ROMs
are compatible with all eight-bit N-channel microprocessors.
including the R6500 family of microprocessors.
All three R2364A ROMs 9perate totally asynchronously. and
require no clock input. These devices provide tri-state output
buffers for memory expansion. The R2364A ROMs offer TIL
input and output levels with a minimum noise immunity of 0.4
volts.
The mask-programmable chip enable input (E) may be programmed to function as a chip select with no power down or
as a chip select with power down (standby mode). The active
level of the enable input is also programmable.

E

CD

IlIA

CO
I\)

VCC
GND
00

AO

01
02

A1

II:

A2

0(0'

A3

W

Wu.

A4

00

AS

:::~

A6

65,536 BIT
ROM
CELL ARRAY

Oil)'
UC\I

03
04
05
06

O~

II:

07

A7

><
en,
CD

-E
n
::D

m

:J>
C

FEATURES
• 65.536 bits. organized as 8.192 eight-bit bytes

,·0

• Max. access time: 200 ns for R2364A2
250 ns for R2364A25
300 ns for R2364A3

Z
....

A8 A9 A10 A11 A12

• Low typical power dissipation is 125 mW active. 37.5 mW
standby

-<

R2364A Block Diagram

if:

m

• Drives two TIL loads and 100 pf

i:

• Single +5-volt power input
• Totally static operation. no input clock required

A7

1

24

Vcc(+5V)

• Completely TIL compatible

A6

2

23

AS

• Mask-programmable chip enable

AS

3

22

A9

• Three state outputs for memory expansion

A4

4

21

A12

• Identical cycle and access time

A3

5

20

E/E·

A2

6

19

A10

A1

7

18

A11

AO

8

17

07
06

Ordering Information
Order Number: R2364A __ [

-'-~L..
.

Temperature Range:
No suffix = O°C to + 70°C
E = -40°C 10 +85°C
Qnduslrial)
Package:
C = Ceramic
P = Plastic
Access Time (Max):
2 = 200 os IACC
25 = 250 ns IACC
3 = 300 ns IACC

(l:) Rockwell Internat.onal Corporation 1980
All Rights Reserved
Printed in U. S.A

00

9

16

01

10

15

05

02

11

14

04

GND

12

13

03

-Mask-programmable option

R2364A Pin Configuration

Specificalions subject to
change without notice

Document No. 29000 083
September 1980

0

::D

-<

~-

::D

0

s:
.......

I

•
I

-

SPECIFICATIONS
Maximum Ratings
Rating

Value

Unit

-0.5 to +7.0
-0.5 to +7.0

Vdc

Symbol

Supply Voltage
Input Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature

Vee
V ln
T

Vdc
°C

o to +70
-40 to +85
-65 to +150

T STG

°C

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should
be taken to avoid application of voltages higher than the maximum rating.
Electrical Characteristics
Vee = 5.0V ± 10% (unless otherwide specified)
Symbol

Parameter

Min
2.4

V IL

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage

III
ILO

Output Leakage Current

lee
IS8

Power Supply Current, Active
Power Supply Current, Standby

25
7.5

CI

Input Capacitance

5

pF

Co

Output Capacitance

7

pF

VOH
VOL
V IH

•

Typ

2.0
-0.5

Input Load Current

Max

Units

Vee
0.4

Volts

Vee
0.8

Volts
Volts
Volts

10
±10

ILA
ILA

55
16

mA
mA

Test Conditions
Vee = 4.5V, IOH = -400 ILA
Vee = 4.5V, IOL = 3.3 mA

Vee = 5.5V, OV .;; V ln

.;;

5.5V

Chip Deselected, Vee = 5.5V,
Vout = +O.4V to Vee
Vee = 5.5V, -40°C to +85°C
Vee = 5.5V, -40°C to +85°C
Vee = 5.0V, chip deselected, pin
under test at OV, TA = 25°C
f = 1MHz

PART NUMBERS
R2364B2,R2364B25,R2364B3

.'1'
...

~h'

')

Rockwell
I

PRODUCT PREVIEW
•

8192 X 8 STATIC READ ONLY MEMORY
The R2364B2, R2364B25 and R2364B3 are 65,536-bit static
Read-Only Memories (ROMs), organized as 8,192 eight-bit
bytes, that offer maximum access times of 200, 250 and 300
nanoseconds, respectively. These ROMs are in industrystandard 28-pin, dual in-line packages, and are available in
ceramic or low-cost plastic. These fully-static 64K-bit ROMs
are compatible with all eight-bit N-channel microprocessors,
including the R6500 family of microprocessors.
All three R2364G ROMs operate totally asynchronously, and
require no clock input. Three mask-programmable Chip select inputs allow up to eight 64K ROMs to be OR-tied without
extemal decoding. These devices provide tri-state output
buffers for memory expansion. The R2364B ROMs offer TTL
input and output levels with a minimum noise immunity of 0.4
volts.
The mask-programmable chip enable input (E) may be programmed to function as a chip select with no power down or
as a chip select with power down (standby mode). The active
level of the enable input is also programmable.

E---------.-------,
G
VCC

51

--------1

52
GND - - - - - - - ,
AO
Al

A2
A3
A4
A5
A6
A7

FEATURES
• 65,536 bits, organized as 8,192 eight-bit bytes

I

• Max. access time: 200 ns for R2364B2
250 ns for R2364B25
300 ns for R2364B3

A8 A9 Al0 All A12

R2364B Block Diagram

• Low typical power dissipation is 125 mW active, 37.5 mW
standby
• Drives two TTL loads and 100 pf
• Single +5-volt power input

NC

1

A12

2

28
27

Vcc (+5V)
52152'

• Totally st!'\tic operation, no input clock required

A7

3

26

51/S1'

• Completely TTL compatible

A6

4

25

A8

• Three mask-programmable chip select inputs

A5

5

24

A9

• Mask-programmable chip enable

A4

6

23

All

• Three state outputs for memory expansion

A3

7

22

GIG'

• Identical cycle and access time

A2

8

21

Al0

Al

9

20

ElE*

AO

10

19

07
06

Ordering Information
Order Number: R2364B __ [

--~L.

Temperalure Range:
No suffix = O°C 10 + 70°C
E = -40°C 10 +85°C
Qnduslrial)
Package:
C = Ceramic.
P = Plastic
Access Time (Max):
2 = 200 ns IACC
25 = 250 ns IACC
3 = 300 ns IACC

IC Rockwell International Corporation 1980
All R'ghts Reserved
PrInted in U.S.A.

00

11

18

01

12

17

05

02

13

16

04

GND

14

15

03

• Mask·programmable option

R2364B Pin Configuration

Specifications subject to

change without notice

Document No. 29000 062
September 1980

•

SPECIFICATIONS
Maximum Ratings
Rating

Symbol

Supply Voltage
Input Voltage

Vee
V in

Operating Temperature
Commercial
Industrial

T

Storage Temperature

T STG

Value

Unit

-0.5 to +7.0

Vdc
Vdc

-0.5 to +7.0

°C

o to

+70
-40 to +85
-65 to +150

°C

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should
be taken to avoid application of voltages higher than the maximum rating.

Electrical Characteristics
Vee = 5.0V ::!: 10% (unless otherwide specified)

Symbol

•

Parameter

Min

VOH

Output HIGH Voltage

2.4

VOL
VIH

Output LOW Voltage

Vil

Input LOW Voltage

III
ILO

Output Leakage Current

Input HIGH Voltage

Typ

2.0
-0.5

Input Load Current

. Max

Units

Vee
0.4

Volts

Vee = 4.5V, IOH = -400 p.A

Volts

Vee = 4.5V, IOl = 3.3 mA

Vee
0.8

Volts

10
:::!:10

Test Conditions

Volts

p.A

Vee = 5.5V, OV ~ V in ~ 5.5V

p.A

Icc

Power Supply Current, Active

25

55

mA

Chip Deselected, Vee = 5.5V,
VOU! = +O.4V to Vee
Vee = 5.5V, -40°C to +85°C

ISB

Power Supply Current, Standby

7.5

16

mA

Vee

CI

Input Capacitance

5

pF

Vee = 5.0V, chip deselected, pin
under test at OV, T A = 25°C

Co

Output Capacitance

7

pF

f

= 5.5V,

= 1MHz

-40°C to +85°C

PART NUMBERS

R8104-R8114

,'1'

f"~

~~

~....

~

DATA SHEET

R-o,?kwell
~ .~'

""

_

":".

~.

1024 X 8 STATIC RAMs
GENERAL DESCRIPTION
The R8104 and R8114 devices are 1024 x 8 "byte-wide" static
RAMs. Both devices are available with a maximum access time
of 200, 300 or 400 nanoseconds.
The non-latched write function allows input data to be stable
after WE is asserted - a feature ideally suited for microprocessor
applications. Chip Enable (~) latches the address, while data-in
is latched by the trailing edge of Write Enable (WEI. The devices
provide common data input/output pins for connection to a data
bus. It operates on a single +5V power supply and all input/
outputs are TTL compatible_ The device dissipates less than
30 mW when in standby mode with CE negated.

FEATURES

A6
A5
A4
A3
A2
A,
AO

Vcc

A7
AS
Ag
~

WE
1/°7

1/°0
110,
1/°2

1/°6
1/°5
1/°4
1/°3

VSS

A7
A6
A5
A4
A3
A2
A,
AO

Vcc

AS

~7C
CE
N/C

WE

1/°0
110,

11°2
VSS

1/°7
1/°6
1/°5

...a.

1/°4
1/°3

0

Order
Number:

e 1024 bytes

R8104O<
en
(X)

e

t; Rockwell International Corporation ·1981

N

~

Pin Configurations

Specifications subject to
change Without notice

Document No. 29000 089
June 1981

»-I
~

n

::rJ

»
s:
en

•

I

Recommended Operating Conditions: (T AMB
PARAMETER
Supply Voltage
Input High Level
Input Low Level

= OOC to 70°C)

SYMBOL
VCC
VIH
VIL

MIN

NOM

MAX

UNIT

4.75
2.0
-0.5

5.0

5.25
5.25
0.8

V
V
V

-

DC Characteristics: T A = OOC to +70 o C, VCC ~ +5V ±.5%, unless otherwise noted
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONOITIONS

Output HIGH Voltage
Output lOW Voltage
Output Leakage Current
Input leakage Current
Power Supply Current
(Device Disabled18104/8114
Power Supply Current
(Device Enabled18104/8114
Power Supply Current
(Device Disabledl 8104L18114l
Power Supply Current
(Device Enabled) 8104l/8114l

VOH
VOL
ILO
III
ICCl

2.4

-

5.25
0.4
+10
+10
10

V
V
p.A
p.A
mA

IOH = -200 p.A (NOTE 11
IOl = 2.1 mA (NOTE 21
VOL = O.4V to VCC CE = WE = 2.0V
VIN = 0 to 5.25V (An. CEo WE. Onlyl
CE ~2.0V

25

50

mA

CE

-

5

mA

CE

~2.0V

25

mA

CE

.;;0.8V

-

-

-10
-10

ICCl

-

ICC2

-

ICC2

5

';;:0.8V

AC Characteristics: T A = OOC to 70°C, \lCC = 5V ±.5%, unless otherwise noted
Read Cycle
8104/8114·2

•

8104/8114·3

8104/8114-4

CHARACTERISTICS

SYMBOL

MIN

Cycle Time
Chip Enable Pulse Width
Chip Enable Rise and Fall Time (NOTE 21
Address Set Up Time
Access Time
Address Hold Time
Output Hold Time
Recovery Time

TC
TCE
TCR.TCF
TAS
TA
TAH
TOH
Tp

350
200

CHARACTERISTICS

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Cycle Time
Chip Enable Pulse Width
Chip Enable Rise and Fall T,ime (NOTE 21
Address Set Up Time
Address Hold Time
Recovery Time
Write Enable Pulse Width
Write Enable Oelay Time
Write Data Hold Time
Data Set Up Time

TC
TCE
TCR.TCF
TAS
TAH
Tp
TWp

350
200

-

450
300

-

700
400

-

nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

MAX

co

MIN

MAX

MIN

MAX

UNIT

450
300

-

700
400

100

nS
nS
nS
nS
nS
nS
nS
nS

co

-

100

-

100

-

0

-

0

-

0

-

200

100
20
130

100

-

-

300

100
20
130

100

-

00

-

-

400

200
20
280

100

-

-

Write Cycle
8104/8114·2

0
100
130
175

-

TWD
TDH
TDS

15
7~

8104/8114·3

00

-

100

-

-

-

00

-

100

-

0
100
130
175

-

15
75

-

-

25

8104/8114-4

0
200
280
225

-

25

15
100

00

100

-

25

-

Capacitance
PARAMETER

SYMBOL

Input Capacitance
Output Capacitance

CIN
COUT

MIN

MAX

UNIT

-

5
5

pF
pF

-

CONOITIONS

CE

= 2V
VI/O = O.4V

NOTE 1: Output terminated per Test Output Load diagram. Any valid combination of input voltages. VCC. and temperature
NOTE 2: Typical Chip Enable 'Rise and Fall Time (TCR and TCFl is 10 nS for Read and Write Cycle

Absolute Maximum Ratings
(See NOTE 1) (Referenced to VSS)

I

Rating

Value

OUTPUT
UNDER TEST

Unit

Voltage to Any Pin With Respect to VSS

-0.5 to +7.0

Vdc

Power Dissipation

1.6 (NOTE 2)

W

Current Into/From Output

50

rnA

Operating Ambient
Temperature Range (T AMB)

o to 70

°c

Storage Temperature (TSTOR)

-B5 to +150

°c

f

I
"Z"

This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages.
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure
to higher than recommended or maximum voltages for extended periods of time could affect device reliability.
NOTE 2: At 25 0 C Ambient Derate 13.5 mW/oC.

lN3064
DIODES

Test Output load

FUNCTIONAL DESCRIPTION
The R8104 and R8114 are 8192·bit Static RAMs with memory cells
organized in eight arrays of 128 rows by 8 columns (1024 x 8 bits).
Each eight·bit byte is addressed by simultaneously decoding the X
addresses (A3 through A9) for the rows, and the Y addresses (AO
through A2) for the columns. Data is written or read in parallel on
eight common input/output pins. Operation of the 8104 and 8"14
is controlled by Chip Enable (CE) and Write Enable (W"E).
When CE is high, all outputs are in a high impedance state, and power
is supplied only to the memory elements. When CE is low, the memory
is enabled for reading and writing.

AOoRESS

_
OOUT

___

r--~r=TOH
VALID

t-

The negative gOing edge of CE begins timing for a read or a write cycle.
Address and WE must be stable for T AS prior to CE being asserted.
Data on address pins AO·A9 are latched into "D" type f1ip·flops and
no longer need to be held stable. WE, however, must be held stable
throughout the cycle. For a read cycle (WE = high), data will be
available on the data I/O pins within time T A of CE asserted, and
will remain valid until time TOH after CE is negated.
For a write cycle (WE = low), data being written must be stable for
TDS prior to CE returning high, and must remain stable for time
TDH·

Truth Table

CE

WE

I/O n

Status

Mode

H

Don't Care

High Z

Disabled

Standby

L

H

Data

Enabled

Read

L

L

L

Enabled

Write 0

L

L

H

Enabled

Write 1

•
.

.

-:.:

.

PACKAGING DIMENSIONS
R8104 (22 Pin) Dimensions
PLASTIC PACKAGE
Millimeters

Inches

Dim.

Min

Mex

Min

MIX

A

27.940
8.636
4.318
0.356
1.016
2.413
1.016
0.203
9.144
10.160
0.508'
2.540

29.718
9.144
5.080
0.559
1.778
2.667
2.032
0.305
10.160
REF.
1.016
3.937

1.100
0.340
0.150
0.014
0.040
0.095
0.040
0.008
0.360
0.400
0.020
0.100

1.170
0.360
0.180
0.022
0.070
0.105
0.080
0.012
0.400
REF.
0.040
0.155

Typical Outline Drawing
B
C
0
E
F
G

H

J
K

L
M

R8114 (24 Pin) Dimensions
PLASTIC PACKAGE
Millimeters
Dim.

Min

MIx

Min

MIX

A

31.369
12.954
3.937
0.381
1.016
2.286
0.381
0.203
15.240
15.748
0.381
2.540

32.131
13.462
5.588
0.584
1.651
2.794
1.270
0.305
15.748
16.764
1.016
4.064

1.235
0.510
0.155
0.015
0.040
0.090
0.Q15
0.008
0.600
0.640
0.015
0.100

1.265
0.530
0.215
0.023
0.065
0.110
0.050
0.012
0.620
0.660
0.040
0.160

B
C
0
E

I

Inches

F
G

H
J
K

L
M

Typical Outline Drawing

~1
i,
"
ttL!
I

...

G

0

~ ~,

.

, ..

SEATING

• ..... ,

R6S000
16-81T JLP
PRODUCTS

•
.

~.-

:

-: 0;-

I

R68000

R68000 Microcomputer System
PRODUCT DESCRIPTION
16-BIT MICROPROCESSING UNIT
Advance; in semiconductor technology have provided the capability to place on a single silicon chip a microprocessor at least an
order of magnitude higher in performance and circuit complexity than
has been previously available. The R68000 is the first of ' a family of
such VLSI microprocessors from ROCkwell. It combines state-of-theart technology and advanced circuit design techniques with computer sciences to achieve an architecturally advanced 16-bit
microprocessor.
The resources avaJiable 10 the R68000 user consist of the follOWing
• 32-9it Data and Address Registers
• 16 Megabyte Direct Addressing Range
• 56 Powerful Instruction Types
• Operations on Five Main Data Types
• Memory Mapped I/O
• 14 Addressing Modes
As shown in the programming model. the R68000 offers seventeen
32-bit registers in addition to the 32-bll program counter and a 16-blt
slatus register. The first eight registers (00-07) are used as data registers for byte (8-bit), word (16-bit), and long word (32-bit) data operations. The second set of seven registers (AO-A6) and the system
stack pointer may be used as software stack pointers and base address regislers. In addition, these registers may be used for word and
long word address operations. All 17 registers may be used as Index

re~~~e~6aooo microprocessor is available in three models:
•
•
•

R68000C4 (4 MHz)
R68OOOC6 (6 MHz)
R68OOOC8 (8 MHz)

~

0')
I

m

31

r-

--

-

-3t

!

I
I

I
I
I

I
I
I

-

I

02
01

DB

DO

09

-.02
03

- 04
- 05
- D6
- 07

I
1

t615

0

l~

i
15

87

ISystem Byte: User Byle

Rockwell InternatIonal Corporation 1981
All Rights Reserved
Printed '" USA

0

I

Seven
Address
Registers

Status
Register

"tJ

UOS
LOS

011
012

0

R/W

013

OTACK

014

BG

015
GNO

m
en
en

A23
A22

C)

GNO
Eight
Data
Registers

0

J:J

AS

VCC
CLK

- 01

I
I
I
I
I

0
J:J

03

BR
DO

s:

04

BGACK
PROGRAMMtNG MODEL
1615
87

=i

PIN ASSIGNMENT

A21

HALT

VCC
A20

RESET

A19

VMA
E

AlB

VPA

A17
A16

BERR
IPL2

A15
A14

IPD

A13

IPLO
FC2
FCI

A12
All
Al0

FCO
Al

A9
AB

A2

A7

A3

A6

A4

A5

Specifications subject to
changa without notice
Document No. 68650 NOI
Rev. I, March 1981

0

Z

c:
Z
=i

•
."

-: ~

R68000C4.R68000C6.R68000C8
Five basic data types are supported. These data types are:

A 23-bit address bus provides a memory addressing range
of greater than 16 megabytes. This large range of addressing
capability, coupled with a memory management unit, allows
large, modular programs to be developed and operated
without resorting to cumbersome and time consuming software bookkeeping and paging techniques.
The status register contains the interrupt mask leight
levels available) as well as the condition codes; extend IX),
negative INI, zero IZI, overflow IV), and carry ICI. Additional status bits indicate that the processor is in a trace ITI
mode and/or in a supervisor lSI state.

•
•
•
•
•

In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 1, include six
basic types:

STATUS REGISTER
System Byte

Bits
BCD Digits (4-bits)
Bytes (8-bits)
Words (16-bits)
Long Words (32-bits)

• Register Direct
• Register Indirect

User Byte

• Absolute
• Immediate
• Program Counter Relative
• Implied
Included in the register indirect addressing modes is the
capability to do postincrementing, predecrementing, offsetting and indexing. Program counter relative mode can also
be modified via indexing and offsetting.

Zero
Overflow

Interrupt
Mask

Carry

TABLE 1 -

DATA ADDRESSING MODES
Generation

Mode
Register Direct Addressing
Data Register Direct
Address Register Direct

EA=Dn
EA=An

Absolute Data Addressing
Absolute Short
Absolute Long

EA= (Next Word)
EA = (Next Two Words)

Program Counter Relative Addressing
EA= (PC) + d16
Relative with Offset
EA=(PC)+(Xn)+de
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

EA=l"An)
EA=(An), An":"An+N
An-An-N, EA=(An)
EA= (An) + d16
EA = (An) + (Xn) + de

Immediate Data Addressing
Immediate
Quick Immediate

DATA=Next Word(s)
Inherent Data

Implied Addrasaing
Implied Register

EA= SR, USP, SP, PC

NOTES:
EA = Effective Address
An = Address Register
On = Data Register
Xn = Address or Data Register used
as Index Register
SR Status Register
PC = Program Counter
( ) = Contents of

da= Eight-bit Offset
(displacement)
d16= Sixteen-bit Offset
(displacement)
N = 1 for Byte, 2 for
Words and 4 for Long
Words
- = Replaces

=

2

R68000C4.R6BOOOC6·R68000CB
long words and most instructions can use any of the 14 addressing modes. Combining instruction types, data types,
and addressing modes, over 1000 useful instructions are
provided. These instructions include signed and unsigned
multiply and divide, "quick" arithmetic operations, BCD
arithmetic and expanded operations (through traps).

The 68000 instruction set is shown in Table 2. Some additional instructions are variations, or subsets, of these and
they appear in Table 3. Special emphasis has been given
to the instruction set's support of structured high-level languages to facilitate ease of programming.·· Each instruction, with. few exceptions, operates on bytes, words, and

TABLE 2 - INSTRUCTION SET

Add Decimal with Extend
Add
logical And
Arithmetic Shift left
Arithmetic Shift Right

BCC
BCHG
BClR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register Against Bounds
Clear Operand
Compare

DBCC

Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide

DIVS
DIVU

Description

Mnemonic

Description

Mnemonic
ABCD
ADD
AND
ASl
ASR

EOR
EXG
EXT

Exclusive Or
Exchange Registers
Sign Extend

JMP
JSR

Jump
Jump to Subroutine

lEA
LINK
lSl
lSR

Description

Mnemonic
PEA

Push Effective Address

load Effective Address
link Stack
logical Shift left
logical Shift Right

RESET
ROl
ROR
ROXl
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate left without Extend
Rotate Right without Extend
Rotate left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

MOVE
MOVEM
MOVEP
MUlS
MULU

Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply

SBCD
SCC
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on ·Overflow
Test

OR

logical Or

UNlK

Unlink

TABLE 3 - VARIATIONS OF INSTRUCTION TYPES
lnatruc:tion
Type

ADD
ADDA
ADDO
ADDI
ADDX

Add
Add
Add
Add
Add

AND

AND
ANDI

logical And
And Immediate

CMP

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR
EORI

Exclusive Or
Exclusive Or Immediate

ADD

EOR

lnatruc:tion
Type

Description

Variation

Description

Variation

MOVE

MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move Address
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer

NEG

NEG
NEGX

Negate
Negate with Extend

OR

OR
ORI

logical Or
Or Immediate

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Subtract
Subtract
Subtract
Subtract
Subtract

Address
Ouick
Immediate
with Extend

3

Address
Immediate
Quick
with Extend

R68000C4-R68000C6-R68000C8

DATA ORGANIZATION AND ADDRESSING CAPABILITIES
The following paragraphs describe the data organization
and addressing capabilities of the 68000.

entire register is affected regardless of the operation size. If
the operation size is word. any other operands are sign extended to 32 bits before the operation is performed.

OPERAND SIZE
Operand sizes are defined as follows: a byte equals 8 bits.
a word equals 16 bits. and a long word equals 32 bits. The
operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction
operation. All explicit instructions support byte,word or long
word operands. Implicit instructions support some subset of
all three sizes.

DATA ORGANIZATION IN MEMORY
Bytes are individually addressable with the high order byte
having an even address the same as the word. as shown in
Figure 1. The low order ~yte has an odd address that is one
count higher than the word address. Instructions and
multibyte data are accessed only on word (even byte) boun- .
daries. If a long word datum is located at address n tn even).
then the second word of that datum is located at address
n+2.
The data types supported by the 68000 are bit data, integer data of 8, 16, or 32 bits, 32-bit addresses and binary
coded decimal data. Each of these data types is put in
memory, as shown in Figure 2.

DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1,8. 16.
or 32 bits. The seven address registers together with the active stack pointer support address operands of 32 bits.
DATA REGISTERS. Each data register is 32 bits wide.
Byte operands occupy the low order 8 bits. word operands
the low order 16 bits. and long word operands the entire 32
bits. The least significant bit is addressed as bit zero; the
most significant bit is addressed as bit 31.
When a data register is used as either a source or destination operand. only the appropriate low-order portion is
changed; the remaining high·order portion is neither used
nor changed.

ADDRESSING
Instructions for the 68000 contain two kinds of information: the type of function to be performed, and the location
of the operand(s) on which to perform that function. The
methods used to locate (address) the operand(s) are explained in the following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number cf the register is
given in the register field of the instruction.
Effective Address - use of the different effective
address modes.
Implicit Reference - the definition of certain instructions implies the use of specific registers.

ADDRESS REGISTERS. Each address register and the
stack pointer is 32 bits wide and holds a full 32 bit address.
Address registers do not support byte sized operands.
Therefore, when an address register is used as a· source
operand. either the low order word or the entire long word
operand is used depending upon the operation size. When
an address register is used as the destination operand, the

FIGURE 1 - WORD ORGANIZATION IN MEMORY
15

14

13

12

11

10

9

8

·2

6

Word 00000o
Byte 00000o

J

Byte 000001

Word 000002

I

Byte 000002

Byte 000003

Word FFFFFE
Byte FFFFFE

I

4

Byte FFFFFF

0

FIGURE 2 -

DATA ORGANIZATION IN MEMORY
Bit Data

1 Byte=B Bits
5

6

0

3

Integer Data

1 Byte = 8 Bits
15

14

12

13

1MS.

11

10

9

6

8

5

3

4.

Byte 0

0

Byte 1

"'1

Byte 2

Byte 3

1 Word= 16 Bits
15

14

13

12

11

10

9

8

4

5

0

3

Word 0

IMS.

Word 1

"'1

Word 2

1 Long Word = 32 Bits
15

14

13

11

12

3

10

MSB
-Long Word 0- -

-

6

7

5

4

0

3

High Order

- - -- - - - - - - - - -

-

Low Order

LSB

-

-Long Word 1- -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Long Word 2 -

-

Addresses
1 Address = 32 Bits

15

14

13

12

10

11

9

MSB
-

-

Address 0 -

-

-

-

-

8

-

o

6

High Order
-

-

-

-

-

-

-

-

-

-

-

Low Order

-

-

Address 1 -

-

-

-

-

-

-

-

-

-

LSB

-

-

-

-

-

-

-

-

-

-

-

--~~2----~~--------------MSB= Most Significant Bit
LSB = Least Significant Bit
Decimal Data
2 Binary Coded Decimal Digits= 1 Byte

15

14

13

12

11

10

9

8

6

o

5

MSD
BCD 0

BCD 1

BCD 4

BCD 5

LSD

MSD= Most Significant Digit
LSD = Least Significant Digit

5

BCD 2

BCD 3

BCD 6

BCD 7

Data Register Direct. The operand is in the data register
specified by the effective address register field.

INSTRUCTION FORMAT·
Instructions are from one to five words in length, as
shown in Figure 3. The length of the instruction and the
operation to be performed is specified by the first word of
the instruction which is called the operation word. The remaining words funher specify the operands. These words
are either immediate operands or extensions to the effective
address mode specified in the operation word.

Address Register Direct. The operand is in the address
register specified by the effective address register field.
MEMORY ADDRESS MODES. These effective addressing modes specify that the operand is in memory and provide
the specific address of the operand.

PROGRAM/DATA REFERENCES

Address Register Indirect. The address of the operand is in
the address register specified by the register field. The
reference is classified as a data reference with the exception
of the jump and jump to subroutine instructions.

The 68000 separates memory references into two
classes: program references, and data references. Program references, as the name implies, are references to
that section of memory that contains the program being
executed. Data references refer to that section of memory
that contains data. Generally, operand reads are from the
data space. All operand writes are to the data space.

Address Register Indirect With Postincrement. The address of the operand is in the address register specified by
the register field. After the operand address is used, it is incremented by one, two, or four depending upon whether the
size of the operand is byte, word, or long word. If the address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.

REGISTER SPECIFICATION
The register field within an instruction specifies the
register to be used. Other fields within the instruction specify
whether the register selected is an address or data register
and how the register is to be used.
EFFECTIVE ADDRESS
Most instructions specify the location of an operand by using the effective address field in the operation word. For example, Figure 4 shows the general format of the single effective address instruction operation word. The effective address is composed of two 3-bit fields: the mode field, and the
register field. The value in the mode field selects the different
address modes. The register field contains the number of a
register.
The effective address field may require additional informatio'n to fully specify the operand. This additional information,
called the effective address extension, is contained in the
following word or words and is considered part of the instruction, as shown in Figure 3. The effective address modes
are grouped into three categories: register direct, memory
addressing, and special.

Address Register Indirect With Predecrernent. The address of the operand is in the address register specified by
the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address
register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is classified
as a data reference.
Address Register Indirect With Displacement. This address mode requires one word of extension. The address of
the operand is the sum of the address in the address register
and the sign-extended 16-bit displacement integer in the extension word. The reference is classified as a data reference
with the exception of the jump and jump to subroutine instructions.

REGISTER DIRECT MODES. These effective addreSSing
modes specify that the operand is in one of the 16 multifunction registers.

Address Register Indirect With Index. This address mode
requires one word of extension. The address of the operand

FIGURE 3 - INSTRUCTION FORMAT

15

14

13

12

11

10

9

7

8

6

5

4

Operation Word
(First Word Specifies Operation and Modes)
Immediate Operand
IIf Any, One or Two Words)
Source Effective Address Extension
(If Any, One or Two Words)
Destination Effective Address Extension
(If Any, One or Two Words)

FIGURE 4 - SINGLE-EFFECTIVE-ADDRESS
INSTRUCTION OPERATION WORD GENERAL FORMAT

6

3

2

o

is the sum of the address in the address register. the signextended displacement integer in the low order eight bits of
the extension word. and the contents of the index register.
The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions.

stack pointer (SSP). the user stack pointer (USP). or the
status register (SRI. Table 5 provides a list of these instructions and the registers implied.
SYSTEM STACK. The system stack is used implicitly by
many instructions; .user stacks and queues may be created
and maintained through the addressing modes. Address
register seven (A7) is the system stack pointer (SPI. The
system stack pointer is either the supervisor stack pointer
(SSP) or the user stack pointer (USP). depending on the
state of the S-bit in the status register. If the S-bit indicates
supervisor state. SSP is the active system stack pointer. and
the USP cannot be referenced as an address register. If the
S-bit indicates user state. the USP is the active system stack
pointer. and the SSP cannot be referenced. Each system
stack fills from high memory to low memory.

SPECIAL ADDRESS MODES. The special address modes
use the effective address register field to specify the special
addressing mode instead of a register number.
Absolute Short Address. This address mode requires one
word of extension. The address of the operand is the extension word. The 16-bit address is sign extended before it is
used. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
Absolute Long Address. This address mode requires two
words of extension. The address of the operand is
developed by the concatenation of the extension words. The
high-order part of the address is the first extension word; ttJe
low-order part of the address is the second extension word.
The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions.

TABLE 4 -

EFFECTIVE ADDRESS ENCODING SUMMARY
Mode

Register

Data Register Direct

000

register number

Address Register Direct

001
010

register number

Address Register Indirect with
Postincrement

011

register number

Address Register Indirect with
Predecrement

100

register number

Address Register Indirect with
Displacement

101

register number

Program Counter Wrth Index. This address mode requires
one word of extension. The address is the sum of the address in the program counter. the sign-extended displacement integer in the lower eight bits ot the extension word.
and the contents of the index register. The value in the program counter is the address of the extension word. This
reference is classified as a program reference.

Address Register Indirect with
Index

110

register number

Absolute Short

111

000

Absolute Long

111

001

Program Counter with
Displacement

111

010

Program Counter with Index

Immediate Data. This address mode requires either one or
two words of extension depending on the size of the operation.
Byte operation - operand is low order byte of extension word
Word operation. - operand is extension word
Long word operation - operand is in the two extension
words. high-order 16 bits are in the first extension
word. low-order 16 bits are in the second extension
word.

Immediate or Status Register

111
111

011
100

Addressing Mode

Program Counter Wrth Displacement. This address mode
requires one word of extension. The address of the operand
is the sum of the address in the program counter and the
sign-extended 16-bit displacement integer in the extension
word. The value in the program counter is the address of the
extension word. The reference is classified as a program
reference.

Address Register Indirect

register number

TABLE 5 - IMPLICIT INSTRUCTION REFERENCE SUMMARY
Instruction
Branch Conditional (BCC), Branch Always (BRA)
Branch to Subroutine (BSR)

Condition Codes or Status Register. A selected set of instructions may reference the status register by means of the
effective address field. These are:
ANDI to CCR
ANDI to SR
EORI to CCR
EORI to SR
ORI to CCR
ORI to SR

Check Register against Bounds (CHK)

SSP, SR
SSP, SR

Unsigned Divide IOIVUI

SSP,SR

Jump to Subroutine (JSR)
Link and Allocate (LiNKI

PC
PC, SP
SP
SR

Move Status Register (MOVE SRI

SR
USP

Push Effective Address (PEAl

SP

Return from Exception (RTEI

PC,SP, SR

Return and Restore Condition Codes (RTR)

PC, SP, SR

Return from Subroutine (RTS)

PC, SP

Trap ITRAPI

SSP, SR

Trap on Overflow ITRAPVI

SSP, SR

Unlink (UNLKI

7

PC

Move Condition Codes (MOVE CCRI
Move User Stack Pointer (MOVE USPI

IMPLICIT REFERENCE
Some instructions make implicit reference to the program
counter (PC). the system stack pointer (SP). the supervisor

PC
PC, SP

Test Condition, Decrement and Branch IOBCCI
Signed Divide (DIVS)
Jump (JMPI

EFFECTIVE ADDRESS ENCODING SUMMARY
Table 4 is a summary of the effective addressing modes
discussed in the previous paragraphs.

Implied
Register{s)

SP

R68000C4·R68000C6.R68000C8

.
INSTRUCTION SET SUMMARY

The following paragraphs contain an overview of the
form and structure of the 68000 instruction set. The instructions form a set of tools that include all the machine functions to perform the following operations:
Data Movement
Integer Arithmetic
logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
The complete range of instruction capabilities combined
with the flexible addressing modes described previously provide a very flexible base for program development.

INTEGER ARITHMETIC OPERATIONS
The arithmetic operations include the four basic operations of add (ADD). subtract (SUB), multiply (MULl. and
divide (DIV) as well as arithmetic compare (CMP), clear
(ClR), and negate (NEG), The add and subtract instructions
are available for both address and data operations, with data
operations accepting all operand sizes. Address operations
are limited to legal address size operands (16 or 32 bits).
Data, address, and memory compare operations are also
available. The clear and negate instructions may be used on
all sizes of data operands.
The multiply and divide operations are .available for signed
and unsigned operands using word multiply to produce a
long word product, and a long word dividend with word
divisor to produce a word quotient with a word remainder.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These instructions are: add extended (ADDX),. subtract extended
(SUBX), sign extend (EXT), and negate binary with extend
(NEGXI.
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is
also available. Test and set (TAS) is a synchronization instruction useful in multiprocessor systems. Table 7 is a summary of the integer arithmetic operations.

DATA MOVEMENT OPERATIONS
The basic method of data acquisition (transfer and
storage) is provided by the move (MOVE) instruction. The
move instruction and the effective addressing modes allow
both address and data manipulation. Data move instructions
allow byte, word, and long word operands to be transferred
from memory to memory, memory to register, register to
memory, and register to register. Address move instructions
allow word and long word operand transfers and ensure that
only legal address manipulations are executed. In addition to
the general move instruction there are several special data
movement instructions: move multiple registers (MOVEM),
move peripheral data (MOVEPI. exchange registers (EXGl,
load effective address (lEA), push effective address (PEA),
link stack (LINK), unlink stack (UNlK), and move quick
(MOVEO)' Table 6 is a summary of the data movement
operations.

TABLE 7 - INTEGER ARITHMETIC OPERATIONS
Instruction
ADD

AOOX

TABLE 6 - DATA MOVEMENT OPERATIONS

~'-

•
.

'.

Instruction
EXG
LEA

Operand Size
32
32

LINK

-

MOVE

a, 16,32

MOVEM

16,32

MOVEP

16,32

MOVEa
PEA
SWAP

a
32
32

UNLK

-

Operand Size
a, 16, 32

CLR

Operation
Rx-Ry
EA-An
An-SP@SP-An
SP+d-SP
(EAls-EAd
(EAI-An, On
An,On-EA
(EAI-On
On-EA
lxxx-On
EA-SP@On[31:16)- On[15:0)
An-Sp
SP@+-An

16,32
a, 16, 32
16,32
a, 16, 32
a, 16,32

CMP
OIVS
OIVU
EXT
MULS
MULU
NEG
NEGX

16,32
32+ 16
32+ 16
a-16
16-32
16"16-32
16"16-32
a, 16,32
a, 16,32
a, 16,32

SUB
16,32

NOTES:
s=source
d = destination
[ ) = bit numbers
@ - = indirect with predecrement
@ + = indirect with postdecrement

SUBX

a, 16,32

TAS
TST

a
a, 16,32

NOTE: [ )= bit number

8

Operation
On+IEAl-On
IEAl+On-EA
lEAl + Ixxx- EA
An+IEAI-An
Ox+Dy+X .... Dx
Axa@- + Ay@- + X .... Ax@
O-EA
On- lEAl
IEAl- 'xxx
Ax@+ -Ay@+
An- lEAl
On/lEAl-On
On/lEAl-On
(O nla- On 16
(O n1 16- On32
On"IEAl-On
On"IEAl-On
O-IEAl- EA
0- lEAl - X- EA
On-lEAl-On
IEAI-On-EA
IEAl-lxxx- EA
An-lEAl-An
Ox-Oy-X-Ox
Ax@- -Ay@- -X-Ax@
lEAl - 0, 1- EA(7)
(EAl-O

BIT MANIPULATION OPERATIONS
Bit manipulation operations are accomplished using the
following instructions: bit test (BTST), bit test and set
(BSET), bit test and clear IBClR), and bit test and change
(BCHGl. Table 10 is a summary of the bit manipulation
operations. (Bit 2 of the status register is Z.)

LOGICAL OPERATIONS
Logical operation instructions AND, OR, EOR, and NOT
are available for all sizes of integer data operands. A similar
set of immediate instructions (ANDI, ORI, and EORI) provide
these logical operations with all sizes of immediate data.
Table 8 is a summary of the logical operations.

TABLE 10 - BIT MANIPULATION OPERATIONS
TABLE B - LOGICAL OPERATIONS
Instruction

Operand Size

AND

8, 16,32

OR

8, 16,32

EOR

8, 16,32

NOT

8, 16,32

NOTE: -

Instruction

Operand Size

Operation

BTST

8,32

-bit of (EAI-Z

BSET

8,32

-bit of (EAI-Z
1-blt of EA

BClR

8,32

-bit of IEAI-Z
O-bit of EA

BCHG

8,32

Operation
DnAIEAI-Dn
IEAlADn- EA
IEAIA/xxx- EA
Dn v IEAI-Dn
lEAl v Dn-EA
lEAl v /xxx- EA

-bit of (EAI-Z
-bit of (EAI-bIt of EA

IEAlilDy-EA
lEAl ii/xxx - EA
-IEAI-EA

BINARY CODED DECIMAL OPERATIONS

= invert

Multiprecision arithmetic operations on binary coded
decimal numbers are accomplished using the following instructions: add decimal with extend (ABCDI, subtract
decimal with extend (SBCD), and negate decimal with extend (NBCDl. Table 11 is a summary of the binary coded
decimal operations.

SHIFT AND ROTATE OPERATIONS
Shift operations in both directions are provided by the arithmetic
instructions ASR and ASL and logical shift instructions LSR and
LSL. The rotate instructions (with and without extend) available are
ROXR, ROXl, ROR, and ROL. All shift and rotate operations can
be performed in either registers or memory. Register shifts and
rotates support all operand sizes and allow a shift count specified
in the instruction o(one to eight bits, or Q to 63 specified in a data
register.
Memory shifts and rotates are for word operands only and allow
only single-bit shifts or rotates.
Table 9 is a summary of the shift and rotate operations.

TABLE 11 - BINARY CODED DECIMAL OPERATIONS
Instruction

Operand
Size

ABCD

8

SBCO

8

NBCD

8

Operation
Dx1O+ Dy1O+ X- Dx
AX@-1O+ AY@-lQ+X-Ax@
Dx1O- Dy1O- X- Dx
AX@-1O- AY@-10- X- Ax @
O-(EAllO-X-EA

TABLE 9 - SHIFT AND ROTATE OPERATIONS
Instruc- Operand
tion
Size

Operation

ASl 8,16,32

~

ASR

8,16,32

d

lSl

8,16,32

~

lSR

8, 16,32

0+1

ROl

8, 16,32

ROR

8,16,32

ROXl 8, 16,32
ROXR 8, 16,32

rn
~
rn

~

III

PROGRAM CONTROL OPERATIONS

1+

Program control operations are accomplished using a
series of conditional and unconditional branch instructions
and return instructions. These instructions are summarized
in Table 12.
The conditional instructions provide setting and branching
for the following conditions:

0

.~
oE

/+0

.~
III

~

.~
III

~

.. ~

9

CC

- carry clear
- carry set

lS
IT

- low or same

CS
EO

- equal

MI

- minus
- not equal

- less than

- never true

NE

GE

- greater or equal

Pl

- plus

GT

- greater than

T

- always true

HI

- high

VC

- no overflow

lE

- less or equal

VS

- overflow

TABLE 12 -

PROGRAM CONTROL OPERATIONS

Instruction

TABLE 13 -

Operation

Conditional
BCC
DBCC

SYSTEM CONTROL OPERATIONS

Instruction

Operation

Privileged
Branch conditionally (14 conditions)
8- and 16-bit displacement

RESET

Reset external devices

RTE

Return from exception

Test condition, decrement, and branch
16-bit displacement

STOP

Set byte conditionally (16 conditions)
SCC
Unconditional
BRA

Branch always
8- and 16-bit displacement

BSR

Branch to subroutine
8- and 16-bit displacement

JMP

Jump

JSR

Jump to subroutine

Logical OR to status register

MOVE USP

Move user stack pointer

ANDI to SR

Logical AND to status register

EORI to SR

Logical EOR to status register

MOVE EA to SR
TRAP
CHK

Returns
RTR

Return and restore condition codes
Return from subroutine

Load new status register

Trap Generating
TRAPV

RTS

Stop program execution

ORI to SR

Trap
Trap on overflow
Check register against bounds

Status Register
AND I to CCR

Logical AND to condition codes

EORI to CCR

Logical EOR to condition codes

MOVE EA to CCR Load new condition codes

SYSTEM CONTROL OPERATIONS
System control operations are accomplished by using
privileged instructions. trap generating instructions, and instructions that use or modify the status register. These instructions are summarized in Table 13.

ORI to CCR
MOVE SR to EA

Logical OR to condition codes
Store status register

SIGNAL AND BUS OPERATION DESCRIPTION
FIGURE 5 - INPUT AND OUTPUT SIGNALS

The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation during the various machine cycles and operations is also given.
SIGNAL DESCRIPTION
The input and output signals can be functionally organized
into the groups shown in Figure 5. The following paragraphs
provide a brief description of the signals and also a reference
(if applicable) to other paragraphs that contain more detail
about the function being performe~l.
ADDRESS BUS (A1 THROUGH A23). This 23-bit,
unidirectional, three-state bus is capable of addreSSing 8
megawords of data. It provides the address for bus operation
during all cycles except interrupt cycles. During interrupt
cycles, address lines A 1, A2, and A3 provide information
about what level interrupt is being serviced while address
lines A4 through A23 are all set to a logic high.
DATA BUS (DO THROUGH 015). This 16-bit, bidirectional, three-state bus is the general purpose data path. It
can transfer and accept data in either word or byte length.
During an interrupt acknowledge cycle, the external device
supplies the vector number on data lines 00-07.

Address Strobe (AS). This signal indicates that there is a
valid address on the address bus.

ASYNCHRONOUS BUS CONTROl. Asynchronous data
transfers are han died using the following control signals: address strobe, read/write, upper and lower data strobes, and
data transfer acknowledge. These signals are explained in
the following paragraphs.

Read/Write (R/Vh This signal defines the data bus
transfer as a read or write cycle. The RiliJ Signal also works
in conjunction with the upper and lower data strobes as explained in the following paragraph.

10

3. data transfer acknowledge is inactive which indicates
that either memory or the peripherals are not using
the bus
4. bus grant acknowledge is inactive which indicates
that no other device is still claiming bus mastership,

Upper And Lower Data Strobes (UDS, LOS). These
signals control the data on the data bus, as shown in Table
14. When the R/IN line is high, the processor will read from
the data bus as indicated. When the R/IN line is low, the
processor will write to the data bus as shown.

INTERRUPT CONTROL (lPLO, IPL1, IPL2). These input
pins indicate the encoded priority level of the device requesting an interrupt- Level seven is the highest priority
while level zero indicates that no interrupts are requested,
The least significant bit ~en in IPLO and the most significant bit is contained in IPL2.

TABLE 14 - DATA STROBE CONTROL OF DATA BUS
~

~

R/W

08-015

00-07

High

High

-

No valid data

No valid data

Low

Low

High

Valid data bits
8-15

Valid data bits
0-7

High

Low

High

No valid data

Valid data bits
0-7

Low

High

High

Valid data bits
8-15

No valid data

Low

Valid data bits
8-15

Valid data bits
0-7
Valid data bits
0-7
Valid data bits
8-15'

Low

Low

High

Low

Low

Valid data bits
O-l"

Low

High

Low

Valid data bits
8-15

SYSTEM CONTROL. The system control inputs are used
to either reset or halt the processor and to indicate to the
processor that bus errors have occurred. The three system
control inputs are explained in the following paragraphs,
Bus Error (BERR). This input informs the processor that
there is a problem with the cycle currently being executed,
Problems may be a result of:
1. nonresponding devices
2. interrupt vector number acquisition failure
3. illegal access request as determined by a memory
management unit
4. other application dependent errors,
The bus error signal interacts with the halt signal to determine if exception processing should be performed or the current bus cycle should be retried.
Refer to BUS ERROR AND HALT OPERATION paragraph
for additional information about the interaction of the bus error and halt signals.

'These conditions are a result of current implementation and may
not appear on future devices.

Data Transfer Acknowledge (DTACK). This input indicates that the data transfer is completed. When the processor recognizes DT ACK during a read cycle, data is
latched and the bus cycle terminated. When DT ACK is
recognized during a write cycle, the bus cycle is terminated.

Reset (RESET). This bidirectional signal line acts to reset
(initiate a system initialization sequence) the processor in
response to an external reset signal. An internally generated
reset (result of a RESET instruction) causes all external
devices to be reset and the internal state of the processor is
not affected. A total system reset (processor and external
devices) is the result of external halt and reset signals applied
at the same time. Refer to RESET OPERATION paragraph
for additional information about reset operation.

BUS ARBITRATION CONTROL. These three signals form
a bus arbitration circuit to determine which device will be the
'
bus master device.
Bus Request (BR). This input is wire ORed with all other
devices that could be bus masters. This input indicates to the
processor that some other device desires to become the bus
master.

Halt (HALTI. When this bidirectional line is driven by an
external device, it will cause the processor to stop at the
completion of the current bus cycle, When the processor has
been halted using this input, all control Signals are inactive
and all three-state lines are put in their high-impedance state.
Refer to BUS ERROR AND HALT OPERATION paragraph
for additional information about the interaction between the
halt and bus error signals.
When the processor has stopped executing instructions,
such as in a double bus fault condition, the halt line is driven
by the processor to indicate to external devices that the processor has stopped.

Bus Grant (BG). This output indicates to all other potential
bus master devices that the processor will release bus control at the end of the current bus cycle.
Bus Grant Acknowledge (BGACKI. This input indicates
that some other device has become the bus master. This
Signal cannot be asserted until the following four conditions
are met:
1. a bus grant has been received
2. address strobe is inactive which indicates that the
microprocessor is not using the bus

11

R68000C4.R68000C6·R68000C8
cycle type currently being executed. as shown in Table 15.
The information indicated by the function code outputs is
valid whenever address strobe (AS) is active.

R6S00 PERIPHERAL CONTROL. These control signals
are used to allow the interfacing of synchronous R6500 peripheral devices with the asynchronous 68000. These signals are explained in the following paragraphs.

TABLE 15 -

Enable (E). This is the standard enable signal commonly
called ¢2 in R6500 peripheral devices. The period for this
output is ten 68000 clock periods (six clocks ·Iow; four
clocks high).
Valid Peripheral Address (VfV\). This input indicates that
the device or region addressed is a R650D family device
and that data transfer shoUld be synchronized with the enable (E) signal. This input also indicates that the processor
should use automatic vectoring for an interrupt. Refer to
INTERFACE WITH R6S00 PERIPHERALS.

FUNCTION CODE OUTPUTS

FC2

FC1

FCO

Cycle Type

Low

low

low

(Undefined. Reserved)

low

Low

High

User Data

Low

High

low

User" Program

Low

High

High

(Undefined. Reservedl

High

low

low

(Undefined. Reservedl

High

Low

High

Supervisor Data

High

High

low

Supervisor Program

High

High

High

Interrupt Acknowledge

Valid Memory Address (VMA). This output is used to indicate to R6500 peripheral devices that there is a valid address on the address bus and the processor is synchronized to enable. This signal only responds to a valid
peripheral address (VPA) input which indicates that the
peripheral is a R6500 family device.

CLOCK (CLK). The clock input is a TTL compatible Signal
that is internally buffered for development of the internal
clocks needed by the processor. The clock input shall be a
constant frequency.

PROCESSOR STATUS (FCO. FC1. FC2). These function
code outputs indicate the state (user or supervisor) and the

SIGNAL SUMMARY. Table 16 is a summary of all the
Signals discussed in the previous paragraphs.

TABLE 16 -

SIGNAL SUMMARY

Mnemonic

InputlOutput

Active State

Three

Address Bus

Al-A23

output

high

yes

Data Bus

00-015

input/output

high

yes

~

output

low

yes

R/W

output

read·high
write-low

yes

UUS.~
~

output

low

yes

input

low

no

Bus Request

Im

input

low

no

Bus Grant

BG

output

low

no

rmACK

input

low

no

input

low

no

Signal Name

Address Strobe
Read/Write
Upper and lower Data Strobes
Data Transfer Acknowledge

Bus Grant Acknowledge
Interrupt Priority level

wrn.IPU.

m

State

Bus Error

BERR

input

low

no

Reset

RESET

input/output

low

no·

Halt

HALT

input/output

low

no·

E

output

high

no

VMA

output

low

yes

Enable
Valid Memory Address

VPA

input

low

no

FCO. FC1. FC2

output

high

yes

Clock

ClK

input

high

no

Power Input

VCC
GND

input

-

-

Valid Peripheral Address
Function Code Output

Ground
·open drain

12

input

BUS OPERATION

NOTE

The following paragraphs explain control signal and bus
operation during data transfer operations, bus arbitration,
bus error and halt conditions, and reset operation.

The terms assertion and negation will be used extensively.
This is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true independent of whether that voltage is low or high. The term
negate or negation is used to indicate that a signal is inactive
or false.

DATA TRANSFER OPERATIONS. Transfer of data between devices involves the following leads:
• Address Bus A 1 through A23

Read Cycle. During a read cycle, the processor receives
data from memory or a peripheral device. The processor
reads bytes of data in all cases. If the instruction specifies a
word (or double word) operation, the processor reads both
bytes. When the instruction specifies byte operation, the
processor uses an internal AO bit to determine which byte to
read and then issues the data strobe required for that byte.
For byte operations, when the AO bit equals zero, the upper
data strobe is issued. When the AO bit equals one, the lower
data strobe is issued. When the data is received, the processor correctly positions it internally.
A word read cycle flow chart is given in Figure 6. A byte
read cycle flow chart is given in Figure 7. Read cycle timing is
given in Figure 8 and Figure 9 details word and byte read cycle operation.

• Data Bus DO through D15
• Control Signals

The address and data buses are separate parallel buses used
to transfer data using an asynchronous bus structure. In all
cycles, the bus master assumes responsibility for deskewing
all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the
acknowledge and data signals from the slave device.
The following paragraphs explain the read, write, and
read-modify-write cycles. The indivisible read-modify-write
cycle is the method used by the 68000 for interlocked multiprocessor communications.

FIGURE 7 - BYTE READ CYCLE FLOW CHART

FIGURE 6 - WORD READ CYCLE FLOW CHART
BUS MASTER

SLAVE

BUS MASTER
Address Device
1) Set R/W to Read
2) Place Address on A 1-A23
3) Place Function Code on FCO-FC2
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LOS) (based on Am

Address Device
Set R/W to Read
2) Place Address on A 1-A23
3) Place Function Code on FCO-FC2
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe (UDS) and Lower Data Strobe ([i5S)
1)

,

I

t

Input Data
1) Decode Address
2) Place Data on 00-07 or DB-D15 (based on
UDS or LOS)
3) Assert Data Transfer Acknowledge

Input Data
1) Decode Address
2) Place Data on 00-015
3) Assert Data Transfer Acknowledge
IDTACK)

(Di'AcK)

f

ACquire Data

ACquire Data

1) Latch Data
2) Negate UDS or LOS
3) Negate AS

1) Latch Data
2) Negate UDS and LOS
3) Negate AS

,

SLAVE

t

Terminate Cycle
Remove Data from 00-07 or 08-015
2) Negate i5"fACR

Terminate Cycle
Remove Data from 00-015
2) Negate DT ACK

,
1)

1)

Start Next Cycle

Start Next Cycle

13

FIGURE 8 -

READ AND WRITE CYCLE TIMING DIAGRAM

ClK

========~~~==========~~~==============~~

~~~------~~
'----_ ___Jr--\

~

I ~

r--\

'--_ ___J!

I

\\....--_ _-Jr_\

____~======~!~~~~-~\'------Jr-\
~_\~====~----~!
I

00-07

Ir-----r--~_-_-_-_---'_\-=======~r

\

)

}-----(

)

}-----(

.-IH

4

-Read-

~

>-

H

FCO-23--<_ _ _ _ _ _ _ _ _

j..- - -

;--

-Write·

-

~
-Slow Read-

- .

-

-~

FIGURE 9 - WORD AND BYTE READ CYCLE TIMING DIAGRAM

ClK

~======~~~======~~~========~~
H
H
)AO·

f:S
UOS
lOS
R/IN

OTACK

r - - \. . . ____ 1

\

---J

\

f

}--

08-015
00-07

)

)

FC0-2::>-{~_ _ _ _ _~}-{~____________~}_{~____________~}_

·Internal Signal Only

h- - -

Word Read-

-

~

-

Odd Byte Read-

Write Cycle. During a write cycle, the processor sends
data to memory or a peripheral device. The processor writes
bytes of data in all cases. If the instruction specifies a word
operation, the processor writes both bytes. When the instruction specifies a byte operation, the processor uses an
internal AO bit to determine which byte to write and then
issues the data strobe required for that byte. For byte opera-

~

-Even Byte Read -

~

tions, when the AO bit equals zero, the upper data strobe is
issued. When the AO bit equals one, the lower data strobe is
issued. A word write cycle flow chart is given in Figure 10. A
byte write cycle flow chart is given in Figure 11. Write cycle
timing is given in Figure 8 and Figure 12 details word and
byte write cycle operation.

14

FIGURE 10 - WORD WRITE CYCLE FLOW CHART
BUS MASTER

1)

2)
3)
4)

5)
6)

FIGURE 11 -

SLAVE
1)
2)
3)
4)
5)

Address Device
Place Address on A 1-A23
Place Function Code on FCO-FC2
Assert Address Strobe lAS)
Set R/W to Write
Place Data on 00-015
Assert Upper Data Strobe IUDS) and
Lower Data Strobe ILOS)

BYTE WRITE CYCLE FLOW CHART

,

6)

Address Device
Place Address on A1-A23
Place Function Code on FCO-FC2
Assert Address Strobe (AS)
Set R/W to Write
Place Data on 00-07 or 08-015 (according
to AOl
Assert Upper Data Strobe (UOS) or Lower
Data Strobe (lOS) (based on AOl

~

Input Data
1) Decode Address
2) Store Data on 00-07 if LOS is asserted
Store Data on 08-015 if UDS is asserted
3) ~ata Transfer Acknowledge

Input Data
1) Decode Address
2) Store Data on 00-015
3) Assert Data Transfer Acknowledge
IDTACK)

ID~

t

Terminate Output Transfer
1) Negate UOS and LOS
2) Negate AS
3) Remove Data from 00-015
4) Set R/W to Read

1)

SLAVE

BUS MASTER

Terminate Output Transfer
Negate UOS and LOS
2) Negate AS
3) Remove Data from 00-07 or" 08-015
4) Set R/W to Read
1)

~

Terminate Cycle
Negate DT ACK

1)

Terminate Cycle
Negate OT ACK

f

f

Start Next Cycle

Start Next Cycle

~--

•

FIGURE 12 - WORD AND BYTE WRITE CYCLE TIMING DIAGRAM

...

ClK

H

AO·

H
I

I
------------------------~

AS~

' ....._ _ _ _-1

LOS

,"--______- J

R/WJ\
OTACK

\

r
r

~

~

I
I

UDS

>

\

1\
I

I

\
\

1\
I

r

r)

\

08-015===>--<=>--C3=~~~
<
<
)

D0-07~
FC0-2

)

)

)

)-<________J H

H

>

·Internal Signal Only

/4-

-Word Write-

-

~

--

. Odd Byte Write

15

-

~

- - Even Byte Write-

-

~

R68000C4.R68000C6.R68000C8

,

'.'.

Read-Modify-Write Cycle. The read-modify-write cycle
performs a read, modifies the data in the arithmetic-logic
unit. and writes the data back to the same address. In the
68000 this cycle is indivisible in that the address strobe is
asserted throughout the entire cycle. The test and set
(TAS) instruction uses this cycle to provide meaningful
communication between processors in a multiple procesFIGURE

13 -

sor environment. This instruction is the only instruction that
uses the read-modify-write cycles and since the test and
set instruction only operates on bytes, all read-modify-write
cycles are byte operations. A read-modify-write cycle flow
chart is given in Figure 13 and a timing diagram is given in
Figure 14.

READ-MODIFY-WRITE CYCLE FLOW CHART
SLAVE

BUS MASTER

1)
2)
3)
4)

'"

Address Device
Place Address on A1-A23
Set R/W to Read
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LDS)

,

I

Input Data
1) Decode Address
2) Place Data on DO-D7 or D8-D15
3) Assert Data Transfer Acknowledge
IDTACt()

t

Acquire Data
1) Latch Data
2) Negate UDS or LOS
3) Start Data Modification

I

t

Terminate Cycle
1) Remove Data from 00-D7 or D8-D15
2) Negate i3TACi<

,

•
~'-

.- -:

Start Output Transfer
1) Set R/W to Write
2) Place Data on DO-D7 or D8-015
3) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LDS)

,

t

~

Input Data
1) Store Data on DO-D7 or D8-D15
2) Assert Data Transfer Acknowledge
IDTACt()

t

1) Negate

Terminate Output Transfer
or LDS

mrn

2) Negate P3
3) Remove Data from DO-D7 or D8-D15
41 Set R/W to Read

~'--------------------------------------------------~

t

Terminate Cycle
1) Negate DT ACt<

t

Start Next Cycle

16

FIGURE 14 -

READ-MODIFY-WRITE CYCLE TIMING DIAGRAM

ClK

\

~ -- -

-

-lndivisibleCycle- -

BUS ARBITRATION. Bus arbitration is a technique used
by master-type devices to request. be granted. and
acknowledge bus mastership. In its simplest form. it consists
of:
1. Asserting a bus mastership request.
2. Receiving a grant that the bus is available at the end
of the current cycle.
3. Acknowledging that mastership has been assumed.

-

FIGURE 15 -

-_._....j

BUS ARBITRATION CYCLE FLOW-CHART
REQUESTING DEVICE

PROCESSOR

Request the Bus
1) Assert Bus Request (BR)

I

f

Grant Bus Arbitration
1) Assert Bus Grant (BG)

Figure 15 is a flow chart showing the detail involved in a
request from a single device. Figure 16 is a timing diagram
for the same operations. This technique allows processing of
bus requests during data transfer cycles.

t

Acknowledge Bus Mastership
1) External arbitration determines next bus
master
2) Next bus master waits for current cycle to
complete
3) Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
4) Bus master negates BR
I

The timing diagram shows that the bus request is negated
at the time that an acknowledge is asserted. This type of
operation would be true for a system consisting of the processor and one device capable of bus mastership. In systems
having a number of devices capable of bus mastership. the
bus request line from each device is wire ORed to the processor. In this system. it is easy to see that there could be
more than one bus request being made. The timing diagram
shows that the bus grant Signal is negated a few clock cycles
after the transition of the acknowledge (BGACK) signal.

f

Terminate Arbitration
11 Negata BG (and wait for BGACK to be
negated)

However. if the bus requests are still pending. the processor will assert another bus grant within a few clock cycles
after it was negated. This additional assertion of bus grant
allows external arbitration circuitry to select the next bus
master before the current bus master has completed its requirements. The following paragraphs provide additional information about the three steps in the arbitration process.

t

Operate as Bus Master
1) Perform Data Transfers (Read and Write
cycles) according to the same rules the pro,
cessor uses.
Release Bus Mastership
1) Negate BGACK

t

Re-Arbitrate or Resume Processor
Operation

17

R68000C4-R68000C6-R68000C8
FIGURE 16 -

BUS ARBITRATION CYCLE TIMING DIAGRAM

ClK

As
UDS

lOS
R/W

OTACK
08-015

/
\
Processor-

~.-

•
...

,

I

~--------~'====~--~I

r -__________~\~==~~I

/

~ -DMA Device- ~

-

-Processor- -

,---------

~

-DMA Device· -

pleted its cycle, the negation of bus grant acknowledge indicates that the previous master has released the bus. (While
address strobe is asserted no device is allowed to "break into" a cycle.) The negation of data transfer acknowledge indicates the previous slave has terminated its connection· to
the previous master. Note that in some applications data
transfer acknowledge might not enter into this function.
General purpose devices would then be connected such that
they were only dependent on address strobe. When bus
grant acknowledge is issued the device is bus master until it
negates bus grant acknowledge. Bus grant acknowledge
should not be negated until after the bus cycle(s) is (are)
completed. Bus mastership is terminated at the negation of
bus grant acknowledge.

Requesting the Bus. External devices capable of becoming
bus masters request the bus by asserting the bus request
(SR) signal. This is a wire ORed signal (although it need not
be constructed from open collector devices) that indicates to
the processor that some external device requires control of
the external bus. The processor is effectively at a lower bus
priority level than the external device and will relinquish the
bus after it has completed the last bus cycle it has started.
When no acknowledge is received before the bus request
Signal goes inactive, the processor will continue processing
when it detects that the bus request is inactive. This allows
ordinary processing to continue if the arbitration circuitry
responded to noise inadvertently.
Receiving the Bus Grant. The processor asserts bus grant
(BG) as soon as possible. Normally this is immediately after
internal synchronization. The only exception to this occurs
when the processor has made an internal decision to execute
the next bus cycle but has not progressed far enough into
the cycle to have asserted the address strobe (AS) signal. In
this case, bus grant will not be asserted until one clock after
address strobe is asserted to indicate to external devices. that
a bus cycle is being executed.
The bus grant Signal may be routed through a daisychained network or through a specific priority-encoded network. The processor is not affected by the external method
of arbitration as long as the protocol is obeyed.

The bus request from the granted device should be dropped when bus grant acknowledge is asserted. If bus request
is still asserted after bus grant acknowledge is negated, the
processor performs another arbitration sequence and issues
another bus grant. Note that the processor does not perform
any external bus cycles before it re-asserts bus grant.

BUS ERROR AND HALT OPERATION. In a bus architecture .that requires a handshake from an external device, the
possibility exists that the handshake might not occur. Since
different systems will require a different maximum response
time, a bus error input is provided. External circuitry must be
used to determine the duration between address strobe and
data transfer acknowledge before issuing a bus error signal.
When a bus error signal is received, the processor has two
options: initiate a bus error exception sequence or try running the bus cycle again.

Acknowledgement of Mastership. Upon receiving a bus
grant, the requesting device waits until address strobe, data
transfer acknowledge, and bus grant acknowledge are
negated before issuing its own BGACK. The negation of the
address strobe indicates that the previous master has com-

18

R68'OOOC4.R6~o6·oC6.R68000C8
'I

.:

..' .

'I

\

•

-

.

[

,

handler routine is then executed by the processor. Refer to
EXCEPTION PROCESSING for additional information.

Exception Sequence. The bus error exception sequence is
entered when the processor receives a bus error signal and
the halt pin is inactive. Figure 17 is a timing diagram for the
exception sequence. The sequence is composed of the
following elements:
1. Stacking the program counter and status register
2. Stacking the error information
3. Reading the bus error vector table entry
4. Executing the bus error handler routine
The stacking of the program counter and the status
register is the same as if an interrupt had occurred. Several
additional items are stacked when a bus error occurs. These
items are used to determine the nature of the error and correct it. if possible. The bus error vector is vector number two
located at address $CXXlOO8. The processor loads the Mw
program counter from this location. A software bus error

Re-Running the Bus Cycle. When the processor receives a
bus error Signal and the halt pin is being driven by an external
device, the processor enters the re-run sequence. Figure 18
'is a timing diagram for re-running the bus cycle.
The processor completes the bus cycle, then puts the address, data and function code output lines in the highimpedance state. The processor remains "halted," and will
not run another bus cycle until the halt signal is removed by
external logic. Then the processor will re-run the previous
bus cycle using the same address, the same function codes,
the same data (for a write operation), and the same controls.
The bus error Signal should be removed before the halt signal
is removed.

FIGURE 17 - BUS ERROR TIMING DIAGRAM

~

' _---

\~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J~

,-----.........I
Jr----

UDS ---~\
lOS

\

....

~----~\~-------

\'--------

R/W
~-----------------------------------------------

\

--;~~;~~~~~~~~~~~~~~~~}----l\,-------~=====
}----l\,-------~=====

08-015
00-07 :

~_~====

FCO-2:J--{

\ !
_...
HAlT------------------------~============~----~-------------BERR

I _ Initiate _ I _
R- d~ ea

r-

_ 1_
_I_
_I_
Initiate Bus
-Response Failure- ~Bus Error Oetectio~Cycle Terminates~ - - -- -:- Error Stacking

~'-

•

FIGURE 18 - RE-RUN BUS CYCLE TIMING INFORMATION
ClK

.- -: =-

/
\......_ - - _ /
/ ,.----------------------~\
/
\
;-----

\
\
\

AS
IT5S

CDS

;-----

R/W

\

i5fACK

(

08-015
00-07
FC0-2

)
)

:>-<
\

BEifR

\

HATf
~

-

- - Read- - -

>-C

I
I

-+-- -- -- --

'Halt- - - - - - -

19

~

- - Rerun- - -

~

I

R68000C4eR68000C6eR68000C8

. .
Note that when the processor honors a request to halt, the
function codes are put in the high-impedance state (their
buffer characteristics are the same as the address buffers!.
While the processor is honoring the halt request, bus arbitration performs as usual. That is, halting has no effect on bus
arbitration. It is the bus arbitration function that removes the
control signals from the bus.
The halt function and the hardware trace capability allow
the hardware debugger to trace single bus cycles or single
instructions one at a time. These processor capabilities,
along with a software debugging package, give total debugging flexibility.

NOTE
The processor will not re-run a read-modify-write cycle.
This restriction is made to guarantee that the entire cycle
runs correctly and that the write operation of a Test-and-Set
operation is performed without ever releasing AS.
Halt Operation with No Bus Error. The halt input signal to
the 68000 performs a HaltlRun/Single-Step function in a
similar fashion to the M6800 halt function. The halt and run
modes are somewhat self explanatory in that when the halt
signal is constantly active the processor "halts" (does
nothing) and when the halt signal is constantly inactive the
processor "runs" (does something).
The single-step mode is derived from correctly timed transitions on the halt signal input. It forces the processor to execute a single bus cycle by entering the "run" mode until the
processor starts· a bus cycle then changing to the "halt"
mode. Thus, the single-step mode allows the user to proceed through land therefore debug) processor operations
one bus cycle at a time.
Figure 19 details the timing required for correct single-step
operations. Some care must be exerci~ed to avoid harmful
interactions between the bus error signal and the halt pin
when using the single cycle mode as a debugging tool. This
is also true of interactions between the halt and reset lines
since these can reset the machine.

Double Bus Faults. When a bus error exception occurs,
the processor will attempt to stack several words containing
information about the state of the machine. If a bus error exception occurs during the stacking operation, there have
been two bus errors in a row. This is commonly referred to as
a double bus fault. When a double bus fault occurs, the processor will halt. Once a bus error exception has occurred,
any bus error exception occurring before the execution of
the next instruction constitutes a double bus fault.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus
fault. Note also that this means that as long as the external
hardware requests it, the processor will continue to re-run
the same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external reset input. The processor reads the vector table after a reset to determine the
address to start program execution. If a bus error occurs
while reading the vector table (or at any time before the first
instruction is executed), the processor reacts as if a double
bus fault has occurred and it halts. Only an external reset will
start a halted processor.

When the processor completes a bus cycle after recognizing that the halt signal is active, most three-state Signals are
put in the high-impedance state. These include:
1. address lines
2. data lines
3. function code lines
This is required for correct performance of the re-run bus cycle operation.

FIGURE 19 -

HALT SIGNAL TIMING CHARACTERISTICS

ClK

AS

..J/

''''____..J/

'''' _ _ _ _

mrn------'
lOS

\

/~-------------------------\

/~-----

/

/

\

R/W
OTACK

\

r-

(>----

/

\

00-07 :::>--<))=~;;;~g{~~>---08-015~;g§~)
(>-C
FCO-2

-J/

'~ _ _ _ _ _ _ _ _ _ _ _ _

HALT

j.- -

-Read- -

-

+-

Halt -

20

- - -~ -

- - Read- - -

.J

the status register to an interrupt level of seven. No other
registers are affected by the reset sequence.
When a RESET sequence is ex.ocuted, the processor
drives the reset pin for 124 clock pulses. In this case, the processor is trying to reset the rest of the system. Therefore,
there is no effect on the internal state of the processor. All of
the processor's internal registers and the status register are
unaffected by the execution of a RESET instruction. All external devices connected to the reset line should be reset at
the completion of the RESET instruction.
When Vee is initially applied to the processor, an external
reset must be applied to the reset pin for 100 milliseconds.

RESET OPERATION. The reset signal is a bidirectional
signal that allows either the processor or an external signal to
reset the system. Figure 20 is a timing diagram for reset
operations. Both the halt and the reset lines must be applied
to ensure total reset of the processor.
When the reset and halt lines are driven by an external
device, it is recognized as an entire system reset, including
the processor. The processor responds by reading the reset
vector table entry (vector number zero, address $QOO()(X))
and loads it into the supervisor stack pointer (SSP)' Vector
table entry number one at address $CXXXX)4 is read next and
loaded into the program counter. The processor initializes

FIGURE 20 - RESET OPERATION TIMING DIAGRAM
ClK

t-

~ 1~

HALT

1~

> 100 Milliseconds

~,....._ _ _ _ _ _ _ _ _ _ _ _ __

______________________-J1

__________________

~

I-.- -++-t<4
NOTES:
11 Internal start-up time
2) SSP High read in here
3) SSP low read in here

4

4) PC High read in here
Bus State Unknown:)OOOO(
5) P.C low rea~ in here
All Control Signals Inactive.
6) First instruction fetched here. Data Bus In Read Mode:

>---<

EXCEPTION PROCESSING
The following paragraphs describe the actions of the
68000 which are outside the normal processing associated with the execution of instructions. The functions of the
bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace enable bit, and the
processor interrupt priority mask. Finally, the sequence of
memory references and actions taken by the processor on
exception conditions is detailed.

The halted proceSSing state is an indication of catastrophic
hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. Only
an external reset can restart a halted processor. Note that a
processor in the stopped state is not in the halted state, nor
vice versa.

=:--'
...

PROCESSING STATES
The 68000 is always one of three processing states: normal, exception, or halted. The normal processing state is
that associated with instruction execution; the memory references are to fetch instructions and operands, and to
store results. A special case of the normal state is the
stopped state which the processor enters when a.STOP instruction is executed. In this state, no further memory references are made.
The exception proceSSing state is associated with interrupts, trap instructions, tracing and other exceptional conditions. The exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing
can be forced by an interrupt, by a bus error, or by a reset.
Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions.

PRIVILEGE STATES
The processor operates in one of two states of privilege:
the "user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the external memory management device to control and translate accesses, and is used to choose between the supervisor stack
pointer and the user stack pointer in instruction references.
The privilege state is a mechanism for providing security in
a computer system. Programs should access only their own
code and data areas, and ought to be restricted from accessing information which they do not need and must not
modify.
The privilege mechanism provides security by allowing
most programs to execute in user state. In this state, the accesses are controlled, and the effects on other parts of the
system are limited. The operating system executes in 'the
supervisor state, has access to all resources, and performs
the overhead tasks for the user state programs.

21

-:-;

•
I

R68000C4eR68000C6eR68000C8
processing, the current setting of the S-bit of the status
register is saved and the S-bit is asserted, putting the processing in the supervisor state. Therefore, when instruction
execution resumes at the address specified to process the
exception, the processor is in the supervisor privilege state.

SUPERVISOR STATE. The supervisor state is the higher
state of privilege. For instruction execution, the supervisor
state is determined by the S-bit of the status register; if the
S-bit is asserted (high), the processor is in the supervisor
state. All instructions can be executed in the supervisor
state. The bus cycles generated by instructions executed in
the supervisor state are classified as supervisor references.
While the processor is in the supervisor privilege state, those
instructions which use either the system stack pointer implicitly or address register seven explicitly access the supervisor stack pointer.
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles
generated during exception processing are classified as
supervisor references. All stacking operations during exception processing use the supervisor stack pointer.

REFERENCE CLASSIFICATION. When the processor
makes a reference, it classifies the kind of reference being
made, using the encoding on the three function code output
lines. This allows external translation of addresses, control of
access, and differentiation of special processor states, such
as interrupt acknowledge. Table 17 lists the classification of
references.
TABLE 17 - REFERENCE CLASSIFICATION
Function Code Output

USER STATE. The user state is the lower state of
privilege. For instruction execution, the user state is determined by the S-bit of the status register; if the S-bit is
negated (low), the processor is executing instructions in the
user state.
Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have
important system effects are made privileged. User programs
are not permitted to execute the STOP instruction, or the
RESET instruction. To ensure that a user program cannot
enter the supervisor state except in a controlled manner, the
instructions which modify the whole. status register are
privileged. To aid in debugging programs which are to be
used as operating systems, the move to user stack pointer
(MOVE USP) and move from user stack pointer (MOVE from
USP) instructions are also privileged.
.
The bus cycles generated by an instruction executed in
user state are classified as user state references. This allows
an external memory management device to translate the address and to control access to protected portions of the address space. While the processor is in the user privilege
state, those instructions which use either the system stack
pointer implicitly, or address register seven explicitly, access
the user stack pointer.

FC1

FCO

0

0

0

0

0

1

User Data

0

1

0

User Program
(Unassigned)

(Unassigned)

0

1

1

1

0

0

(Unassigned)

1

0

1

Supervisor Data

1

1

0

Supervisor Program

1

1

1

Interrupt Acknowledge

EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and tracing, a general description of exception processing is in order.
The processing of an exception occurs in four steps, with
variations for different exception causes. During the first
step, a temporary copy of the status register is made, and
the status register is set for exception processing. In the second step the exception vector is determined, and the third
step is the saving of the current processor context. In the
fourth step a new context is obtained, and the processor
switches to instruction processing.
EXCEPTION VECTORS. Exception vectors are memory
locations from which the processor fetches the address of a
routine which will handle that exception. All exception vectors are two words in length (Figure 211, except for the reset

PRIVilEGE STATE CHANGES. Once the processor is in
the user state and executing instructions, only exception
processing can change the privilege state. During exception
FIGURE 21 -

Reference Class

FC2

EXCEPTION VECTOR FORMAT

Word 0

New Program Counter (High)

AO=O, Al =0

Word 1

New Program Counter (Low)

AO=O, Al=l

FIGURE 22 -

PERIPHERAL VECTOR NUMBER FORMAT

Ignored
Where:
v7 is the MSB of the Vector Number
va is the LSB of the Vector Number

22

vector, which is four words. All exception vectors lie in the
supervisor data space, except for the reset vector which is in
the supervisor program space. A vector number is an eightbit number which, when multiplied by four, gives the address of an exception vector. Vector numbers are generated
internally or externally, depending on the cause of the exception. In the case of interrupts, during the interrupt
acknowledge bus cycle, a peripheral provides an 8-bit vector
number (Figure 22) to the processor on data bus lines DO
through 07. The processor translates the vector number into
a full 24-bit address, as shown in Figure 23. The memory
layout for exception vectors is given in Table 18.
As shown in Table 18, the memory layout is 512 words
long (1024 bytes). It starts at address D and proceeds

through address 1023. This provides 255 unique vectors;
some of these are reserved for TRAPS and other system
functions. Of the 255, there are 192 reserved for user interrupt vectors. However, there is no protection on the first 64
entries, so user interrupt vectors may overlap at the discretion of the systems designer.
KINDS OF EXCEPTIONS. Exceptions can be generated by
either internal or external causes. The externally generated
exceptions are the interrupts and the bus error and reset requests. The interrupts are requests from peripheral devices
for processor action while the bus error and reset inputs are
used for access control and processor restart. The internally
generated exceptions come from instructions, or from ad-

FIGURE 23 - ADDRESS TRANSLATED FROM 8-BIT
VECTOR NUMBER
AlO A9 A8

A7

A6

A5

A4

All Zeroes

TABLE 18 - EXCEPTION VECTOR ASSIGNMENT
Address

Vector

Assignment

Number(s)

Dec

Hex

Space

0

0

000

SP

Reset: Initial SSP

-

4

004

SP

Reset: Initial PC

2

8

008

SO

Bus Error

3

12

OOC

SO

Address Error

4

16

010

SO

Illegal Instruction

5

20

014

SO

Zero Oivide

6
7

24

alB

SO

CHK Instruction

28

01C

SO

TRAPV Instruction

8

32

020

SO

Privilege Violation

9

36

024

SO

Trace

10

028

SO

Line 1010 Emulator

11

40
44

02C

SO

Line 1111 Emulator

12"

48

030

13"

52

034

SO
SO

(Unassigned, reservedl
(Unassigned, reserved)

14"

56

038

SO

15

60

03C

SO

(Unassigned, reserved)
(Unassigned, reserved)

SO

(Unassigned, reserved)

16-23"

64

O4C

95

05F

24

96

060

SO

Spurious Interrupt

25
26

100

064

SO

Levell Interrupt Autovector

104

068

SO

Level 2 Interrupt Autovector

27

108

06C

SO

Level 3 Interrupt Autovector

28

112

070

SO

Level 4 Interrupt Autovector

-

29

116

074

SO

Level 5 Interrupt Autovector

30

120

078

SO

Level 6 Interrupt Autovector

31
32-47

124

07C

SO

Level 7 Interrupt Autovector

128

080

SD

TRAP Instr.uction Vectors

191

OBF

192

OCO

SD

(Unassigned, reserved)

255

OFF

256

100

SO

User Interrupt Vectors

1023

3FF

48-63"
64-255

-

-

·Vector numbers 12,13,14,16 through 23 and 48 through 63 are reserved for future enhancements. No user peripheral devices should be
assigned these numbers.

23

A3

A2

Al

AD

R68000C4.R68000C6.R68000C8

"

.

dress errors or tracing. The trap (TRAP), trap on overflow
(TRAPVl. check register against bounds (CHK) and divide
IDIV) instructions all can generate exceptions as part of their
instruction execution. In addition, illegal instructions, word
fetches from odd addresses and privilege violations cause exceptions. Tracing behaves like a very high priority, internally
generated interrupt after each instruction execution.

.'

.

,

privilege violation. Since only one instruction can be executed at a time, there is no priority relation within Group 2.
The priority relation between two exceptions determines
which is taken, or taken first, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the
TRAP instruction processing is aborted. In another example,
if an interrupt request occurs during the execution of an instruction while the T-bit is asserted, the trace exception has
priority, and is processed first. Before instruction processing
resumes, however, the interrupt exception is also processed,
and instruction processing commences finally in the interrupt handler routine. A summary of exception grouping and
priority is given in Table 19.

EXCEPTION PROCESSING SEQUENCE. Exception processing occurs in four identifiable steps. In the first step, an
internal copy is made of the status register. After the copy is
made, the S-bit is asserted, putting the processor into the
supervisor privilege state, Also, the T-bit is negated which
will allow the exception handler to execute unhindered by
tracing. For the reset and interrupt exceptions, the interrupt
priority mask is also updated.
.
In the second step, the vector number of the exception is
determined. For interrupts, the vector number is obtained by
a processor fetch, claSSified as an interrupt acknowledge.
For all other exceptions, internal logic provides the vector
number. This vector number is then used to generate the address of the exception vector.
The third step is to save the current processor status, except for the reset exception. The current program counter
value and the saved copy of the status register are stacked
using the supervisor stack pointer. The program counter
value stacked usually points to the next unexecuted instruction, however for bus error and address error, the value
stacked for the program counter is unpredictable, and may
be incremented from the address of the instruction which
caused the error. Additional information defining the current
context is stacked for the bus error and address error exceptions.
The last step is the same for all exceptions. The new program counter value is fetched from the exception vector.
The processor then resumes instruction execution. The instruction at the address given in the exception vector is
fetched, and normal instruction decoding and execution is
started.

TABLE 19 -

EXCEPTION GROUPING AND PRIORITY

Group

Exception

0

Reset
Bus Error
Address Error

1

Trace
Interrupt
Illegal
Privilege

2

Pro~essing

Exception processing begins at
the next minor cycle

Exception processing begins before
the next instruction

TRAP, TRAPV,
Exception processing is started by
CHK,
normal instruction execution
Zero Divide

EXCEPTION PROCESSiNG DETAILED DISCUSSION
Exceptions have a number of sources, and each exception
has processing which is peculiar to it. The following
paragraphs detail the sources of exceptions, how each
arises, and how each is processed.

MULTIPLE EXCEPTIONS. These paragraphs describe the
processing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to
their occurrence and priority. The Group o exceptions are
reset. bus error, and address error. These exceptions cause
the instruction currently being executed to be aborted, and
the exceptioQ processing to commence at the next minor cycle of the processor. The Group 1 exceptions are trace and
interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to
execute to completion, but preempt the execution of the
next instruction by forCing exception processing to occur
(privilege violations and illegal instructions are detected
when they are the next instruction to be executed!. The
Group 2 exceptions oo::r:ur as part of the normal processing of
instructions. The TRAP, TRAPV, CHK, and zero divide exceptions are in this group. For these exceptions, the normal
execution of an instruction may lead to exception processing.

RESET. The reset input provides the highest exception
level. The processing of the reset Signal is deSigned for
system initiation, and recovery from catastrophic failure.
Any processing in progress at the time of the reset is aborted
and cannot be recovered. The processor is forced into the
supervisor state, and the trace state is forced off. The processor interrupt priority mask is set at level seven. The vector
number is internally generated to reference 'the reset exception vector ·at location 0 in the supervisor program space.
Because no assumptions can be made about the validity of
register contents, in particular the supervisor stack pointer,
neither the program counter nor the status register is saved.
The address contained in the first two words of the reset exception vector is fetched as the initial supervisor stack
pointer, and the address in the last two words of the reset
exception vector is fetched as the initial program counter.
Finally, instruction execution is started at the address in the
program counter. The power-up/restart code should be
pointed to by the initial program counter.
The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external
devices. This allows ·the software to reset the system to a
known state and then continue processing with the next instruction.

Group 0 exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by bus error and then address error. Within Group 1, trace has priority over external interrupts, which in turn takes priority over illegal instruction and

INTERRUPTS. Seven levels of interrupt priorities are provided. Devices may be chained externally within interrupt
priority levels, allowing an unlimited number of peripheral
devices to interrupt the processor. Interrupt priority levels

24

FIGURE 24 - INTERRUPT ACKNOWLEDGE SEQUENCE
FLOW CHART

are numbered from one to seven, level seven being the
highest priority. The status register contains a three-bit mask
which indicates the current processor priority, and interrupts
are inhibited for all priority levels less than or equal to the
current processor priority.
An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request lines; a
zero indicates no interrupt request. Interrupt requests arriving at the processor do not force immediate exception processing, but are made pending. Pending interrupts are
detected between instruction executions. If the priority of
the pending interrupt is lower than or equal to the current
processor priority, execution continues with the next instruction and the interrupt exception processing is postponed.
(The recognition of level seven is slightly different, as explained in a following paragraph.)
If the priority of the pending"interrupt is greater than the
current processor priority, the exception processing sequence is started. First a copy of the status register is saved,
and the privilege state is set to. supervisor, tracing is suppressed, and the processor priority level is set to the level of
the interrupt being acknowledged. The processor fetches
the vector number from the interrupting device, classifying
the reference as an interrupt acknowledge and displaying the
level number of the interrupt being acknowledged on the address bus. If external logic requests an automatic vectoring,
the processor internally generates a vector number which is
determined by the interrupt level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and
the generated vector number references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program counter and status
register on the supervisor stack. The saved value of the program counter is the address of the instruction which would
have been executed had the interrupt not been present. The
content of the interrupt vector whose vector number was
previously obtained is fetched and loaded into the program
counter, and normal instruction execution commences in the
interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 24; a timing
diagram is given in Figure 25.

INTERRUPTING DEVICE

PROCESSOR

Request Interrupt

I

t

Grant Interrupt
11 Compare interrupt level in status register
and wait for current instruction to complete
2) Place interrupt level on A 1, A2, A3
3) Set R/W to read
4) Set function code to interrupt acknowledge
5) Assert address strobe (AS)
6) Assert lower data strobe (CiS'S)

,

I

Provide Vector Number
1) Place vector number of 00-07
2) Assert data transfer acknowledge IDTACK)

-r

Acquire Vector Number
1) latch vector number
2) Negate IDS
3) Negate~

1) Negate OT ACK

-

•
.-

FIGURE 25 - INTERRUPT ACKNOWLEDGE SEQUENCE TIMING DIAGRAM
ClK

}-I
AS

\
\

lOS

\

I

r--\
r--\
r--\

r

\

r

r--\
\
I

r

R/iN

\

OTACK

I

\

I

\

08-015
00-07

)

FC0-2::>-<

)-1

IPL0-2

)

y
I

\
k- -

Read Cycle -

-+-

.:-

I

H
UOS

I

~'-

Start Interrupt Processing

-Vector Number ACQuisition-

25

->-/

R68000C4.R68000C6·R68000C8
TRACING. To aid in program development, the 68000
includes a facility to allow instruction by instruction traCing.
In the trace state, after each instruction is executed an exception is forced. allowing a debugging program to monitor the execution of the program under test.
The trace facility uses the T -bit in the supervisor portion of
the status register. If the T-bit is negated (off), tracing is
disabled. and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at
the beginning of the execution of an instruction, a tracf:j exception will be generated after the execution of that instruction is completed. If the instruction is not executed. either
because an interrupt is taken, or the instruction is illegal or
privileged. the trace exception does not occur. The trace exception also does not occur if the instruction is aborted by a
reset. bus error, or address error exception. If the instruction
is indeed executed and an interrupt is pending on completion. the trace exception is processed before the interrupt exception. If, during the execution of the instruction, an exception is forced by that instruction, the forced exception is processed before the trace exception.
As an extreme illustration of the above rules. consider the
arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is
processed. then the trace exception. and finally the interrupt
exception. Instruction execution resumes in the interrupt
handler routine.

Priority level seven is a special case. Level seven interrupts
cannot be inhibited by the interrupt priority mask, thus providing a "non-maskable interrupt" capability. An interrupt is
generated each time the interrupt request level changes from
some lower level to level seven. Note that a level seven interrupt may still be caused by the level comparison if the request level is a seven and the processor priority is set to a
lower level by an instruction.
INSTRUCTION TRAPS. Traps are exceptions caused by
instructions. They arise either from processor recognition of
abnormal conditions during instruction execution, or from
use of instructions whose normal behavior is trapping.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is
useful for implementing system calls for user programs. The
TRAPV and CHKinstructions force an exception if the user
program detects a runtime error, which may be an arithmetic
overflow or a subscript out of bounds.
The Signed divide !DIVS) imd unsigned divide !DIVU) instructions will force an exception if a diviSion operation is attempted with a divisor of zero.
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS. illegal instruction is the term used to refer to any of the word
bit patterns which are not the bit pattern of the first word of
a legal instruction. During instruction execution, if such an
instruction is fetched, an illegal instruction exception occurs.
Word patterns with bits 15 through 12 equaling 1010 or
1111 are distinguished as unimplemented instructions and
separate exception vectors are given to these patterns to permit efficient emulation. This facility allows the operating
system to detect program errors, or to emulate
unimplemented instructions in software.

BUS ERROR. Bus error exceptions occur when the external logic requests that a bus error be processed by an exception. The current bus cycle which the processor is making is
then aborted. Whether the processor was doing instruction
or exception processing, that processing is terminated. and
the processor immediately begins exception proceSSing.
Exception processing for bus error follows the usual sequence of steps. The status register is copied. the supervisor
state is entered. and the trace state is turned off. The vector
number is generated to refer to the bus error vector. Since
the processor was not between instructions when the bus error exception request was made. the context of the processor is more detailed. To save more of this context. additional information is saved on the supervisor stack. The program counter and the copy of the status register are of
course saved. The value saved for the program counter is advanced by some amount. two to ten bytes beyond the ad-

PRIVILEGE VIOLATIONS. In order to provide system
security, various instructions are privileged. An attempt to
execute one of the privileged instructions while in the user
state will cause an exception. The privileged instructions are:
STOP
AND (word) Immediate to SR
RTE

RESET

EaR (word) Immediate to SR
OR (word) Immediate to SR

MOVE to SR

MOVE USP
FIGURE 26 15

14

13

12

SUPERVISOR STACK ORDER

B

9

10

11

6

5

4

o

2

3

Lower Address

Function Code

r- -

Access Address -

-

-

-

-

-

-

-

High
- - -

-

-

-

-

-

-

-

Low
Instruction Register
Status Register
High
f- - Program Counter -

-

Low

R/W (read/Write): write=O. read = 1. I/N jlnstructlon/not): Instruction=O. not= 1

26

-

-

-

-

-

-

-

dress of the first word of the instruction which made the
reference causing the bus error. If the bus error occurred
during the fetch of the next instruction, the saved program
counter has a value in the vicinity of the current instruction,
even if the current instruction is a branch, a jump, or a return
instruction. Besides the usual information, the processor
saves its internal copy of the first word of the instruction being processed, and the address which was being accesse.d
by the aborted bus cycle. Specific information about the access is also saved: whether it was a read or a write, whether
the processor was processing an instruction or not, and the
classification displayed on the function code outputs when
the bus error occurred. The processor is processing an instruction if it is in the normal state or processing a Group 2
exception; the processor is not processing an instruction if it
is processing a Group or a Group 1 exception. Figure 26 illustrates how this information is organized on the supervisor
stack. Although this information is not sufficient in general
to effect full recovery from the bus error, it does allow software diagnosis. Finally, the processor commences instruction processing at the address contained in the vector. It is

the responsibility of the error handler routine to clean up the
stack and determine where to continue execution.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted,
and all processing ceases. This simplifies the detection of
catastrophic system failure, since the processor removes
itself from the system rather than destroy all memory contents. Only the RESET pin can restart a halted processor.
ADDRESS ERROR. Address error exceptions occur when
the processor attempts to access a word or a long word
operand or an instruction at an odd address. The effect is
much like an internally generated bus error, so that the bus
cycle is aborted, and the processor ceases whatever processing it is currently doing and begins exception processing.
After exception processing commences, the sequence is the
sam" as that for bus error including the information that is
stacked, except that the vector number refers to the address
error vector instead. Likewise, if an address error occurs during the exception processing for a bus error. address error,
or reset, the processor is halted.

a

INTERFACE WITH R6SDD PERIPHERALS
FIGURE 27 -

Rockwell's line of R6500 peripherals are directly compatible with the 68000. Some of these devices that are particularly useful are:
R6520 Peripheral Interface Adapter (PIA)
R6522 Versatile Interface Adapter (VIA)
R6545 CRT Controller
R6551 Asynchronous Communication Interface Adapter

R6500 INTERFACING FLOW CHART

PROCESSOR
Initiate Cycle
1) The processor starts a normal Read or
Write cycle

SLAVE

t

To interface the synchronous R6500 peripherals with the
asynchronous 68000, the processor modifies its bus cycle
to meet the R6500 cycle requirements whenever an R6500
device address is detected. This is possible since both
processors use memory mapped 110. Figure 27 is a flow
chart of the interface operation between the processor and
R6500 devices. 6800 peripherals are also compatible with
the 68000 processor.

Define R6SDD Cycle
1) External hardware asserts Valid Peripheral

?

Synchronize With Enable
11 The processor monitors Enable (E) until it is
low (Phase 1)
2) The processor asserts Valid Memory Address (VMA)

DATA TRANSFER OPERATION
Three Signals on the processor provide the R6500 interface. They are: enable (E), valid memory address (VMA),
and valid peripheral address (VPA). Enable corresponds
to the E or cp2 Signal in existing R6500 systems. It is the bus
clock used by the frequency clock that is one tenth of the
incoming 68000 clock frequency. The timing of E allows 1
MHz peripherals to be used with an 8 MHz 68000. Enable
has a 60/40 duty cycle; that is, it is low for six input clocks
and high for four input clocks. This duty cycle allows the
processor to do successive VPA accesses on successive
E pulses.
R6500 cycle timing is given in Figure 28. At state zero
(SO) in the cycle, the address bus and function codes are
in the high-impedance state. One half clock later, in state
1, the address bus and function code outputs are released
from the high-impedance state.
_
During state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus. If the
bus cycle is a read cycle, the upper and/or lower data
strobes are also asserted in state 2. If the bus cycle is a write
cycle, the read/write (R/W) Signal is switched to low (write)

•
~:.-

. -.

Transfer Data
1) The peripheral waits until E is active and
then transfers the data

~

Terminate Cycle
1) The processor waits until E goes low. (On a
Read cycle the data is latched as E goes
low internally)
2) The processor negates '\i"MA
3) The processor negates AS, UoS, and LOS

+

Start Next Cycle

27

.

·

R68000C4.R68000C6·R68000C8
during state 2. One half clock later, in state 3, the write data
is placed on the data bus, and in state 4 the data strobes are
issued to indicate valid data on the data bus.
The processor now inserts wait states until it recognizes
the assertion of VPA. The VPA input signals the processor
that the address on the bus is the address of an R6500 device (or an area reserved for R6500 devices) and that the
bus should conform to the cf>2 transfer characteristics of the
R6500 bus. Valid peripheral address is derived by decoding the address bus, conditioned by address strobe.
After the recognition of VPA, the processor assures that
the Enable (E) is low, by waiting if necessary, and subsequently asserts VMA. Valid memory address is then used
as part of the chip select equation of the peripheral. This
ensures that the R6500 peripherals are selected and deselected at the correct time. The peripheral now runs its
cycle during the high portion of the E signal.

FIGURE 28 -

During a read cycle, the processor latches the peripheral
data in state 6. For all cycles, the processor negates the address and data strobes one half clock cycle later in state 7,
and the Enable signal goes low at this time. Another half
clock later, the address bus is put in the high-impedance
state. During a write cycle, the data bus is put in the highimpedance .state and the read/write signal is switched high
at this time. The peripheral logic must remove VPA within
one clock afte" address strobe is negated.
Figure 29 shows the timing required by R6500 peripherals, the timing specified for the R6500 and the corresponding timing for the 68000. For further details on
peripheral timing, consult the current data sheet for the
peripheral of interest. Notice that the 68000 VMA is active
low. This allows the processor to put its buses in the highimpedance state on DMA requests without inadvertently
selecting peripherals.

R6500 CYCLE OPERATION

w~~~w~~~~~~~~~~~~~w~~~~~~~~~w

ClK

}(~_ _ _ _ _ _ _ _ _ _ _ _~}{~_ _ _ _ _ _ _ _.....

A1-A23}{

_____
r--\'-_____

AS ' - - J \
UDS ' - - J \

I\~

LOS~

~""'_ _ _ _ _- - '

R~

---J

...J

\

OTACK~

<

08-015 - - < : : )
0()'07--<::)
FC()'2X

~~========~r
}----{
}).{

}{

I

VPA

1\

\

VMA

\ ....._ _ _ _ _..",

'-- Normal

r"'" -

-

Cycle

-+- -

K

.
-R6S00 Pertpheral Read Cycle-

28

-+-

L
r

.."r

,'-_ _ _ _ _

R6S00 Peripheral Write Cycle--..j

FIGURE 29 -

68000 TO R6S00 PERIPHERAL TIMING DIAGRAM

68000 CLK

Peripheral'

R6S00 cb2 Clock Freq.
2.0 MHz
1.0 MHz

~ 90 ns ~ Type A
~180ns~Std

R6500. Rm
R6500 Address

~~~..I..Ll"h..t.J.ljh.l..l.'Ih.£..7_ _ _ _ _ _ _ __
~

~

Peripheral'
TypeA~190ns--""';~~1
Std~395ns
..

~ 30 ns R6500'

~ 10 ns Peripheral'

~

~

I ]..----

W/f//!$/lIlli/I!

R6500 Road Data

~10nsR6500'
,10nsperi Pheral

Peripheral'

TypeA~150ns~

I

Std~300 ns-+/

~

{'l'/////I///I//I///

R6500WriteData
68000 Address

AS

m

»)-----

)--1(1(!

M

~
\~~~~~~~~~___________
68000 (8 MHz)
~200ns--.f

~~\

VMA
Write Data

)~----

----------<

68000 CLK
'TImes are expressed for different device clock frequencies

,:111

,

,

"II

•

.

R68000C4-R68000C6-R68000C8

INTERRUPT INTERFACE OPERATION
During an interrupt acknowledge cycle while the processor is fetching the vector, if VPA is asserted, the 68000 will
assert VMA and. complete a normal R6500 read cycle as
shown in Figure 30. The processor will then use an internally generated vector that is a function of the interrupt
being se·rviced. This process is known as autovectoring.
The seven autovectors are vector numbers 25 through 31
(decimal).

FIGURE 30 -

This operates in the same fashion (but is not restricted
to) the R6500 interrupt sequence. The basic difference is
that there are six normal interrupt vectors and one NMI
type vector. As with both the R6500 and the 68000's normal vectored interrupt, the interrupt service routine can be
located anywhere in the address space. This is due to the
fact that while the vector numbers are fixed, the contents
of the vector table entries are assigned by the user.
Since VMA is asserted during autovectoring, the R6500
peripheral address decoding should prevent unintended
accesses.

AUTOVECTOR OPERATION TIMING DIAGRAM

Al-A3
A4-A23

AS
UOS
LOS

R/W
OTACK

~

08-015

--<::)-~---------------

~D7 ~~----------------------------FC0-2

E

>-<

)J

~-~==~~------~====~L\

VPA

\

I\..

I

L......... ~r~I_~ _ _ _ -Autovector Operation- _ _ _ _ ~
~

Cycle

-r

--r

RS8000C4.RS8000CS·RS8000C8

.

INSTRUCTION SET
Control

The following paragraphs provide information about the
addressing categories and instruction set of the 68000.

ADDRESSING CATEGORIES
Effective address modes may be categorized by the ways
in which they may be used. The following classifications will
be used in the instruction definitions.
Data
If an effective address mode may be
used to refer to data operands, it is
considered a data addressing effective
address mode.
Memory
If an effective address mode may be
used to refer to memory operands, it is
considered a memory addressing effective address mode.
Alterable
If an effective address mode may be
used to refer to alterable (writeablel
operands, it is considered an alterable
addressing effective address mode.

TABLE 20 -

If an effective address mode may be
used to refer to memory operands
without an associated size, it is considered a control addressing effective
address mode.

Table 20 shows the various categories to which each of the
effective address modes belong. Table 21 is the instruction
set summary.
The status register aadressing mode is not permitted
unless it is explicitly mentioned as a legal addressing mode.
These categories may be combined, so that additional,
more restrictive, classifications may be defined. For example, the instruction descriptions use'such classifications as
alterable memory or data alterable. The former refers to
those addressing modes which are both alterable and
memory addresses, and the latter refers to addressing modes
which are both data and alterable.

EFFECTIVE ADDRESSING MODE CATEGORIES

Effective
Address
Modes

Mode

Register

Data

Memory

Control

Alterable

On
An
An@

000
001
010

register number
register number
register number

X

-

-

An@+
An@An@(d)

all
100
101
110
111
111
111
111
111

register number
register number
register number

An@(d, ix)
xxx.W
xxx.L
PC@(d)
PC@(d, ix)

Ixxx

Addressing Categories

register number

000
001
010

all
100

-

-

X
X
X

X
X
X

-

X
X
X
X
X

X
X
X
X

X

X

X

X
X
X
X
X
X

X
X
X

X

X
X

-

X
X
X

X

-

X
X

I

•
~'--:

:

-;

I

31

"

,R68000C4-R68000C6-R68000C8

'

.

.'

TABLE 21 - INSTRUCTION SET
Condition
Description

Mnemonic

Codes
X N Z V C

Operation

ABCD

Add Decimal with Extend

(Destination)lO + (Source)lO- Destination

ADD

Add Binary

!Destination) + (Source)- Destination

ADDA

Add Address

!Destination) + (Source) -

ADDI

Add Immediate

!Destination) + Immediate Data -

U

- -

Destination

Add Quick

(Destination) + Immediate Data

ADDX

Add Extended

!Destination) + (Source) + X -

AND

AND Logical

!Destination) A (Source) -

ANDI

AND Immediate

!Destination) A Immediate Data- Destination

ASl, ASR

Arithmetic Shift

!Destination) Shifted by < count> -

BCC

Branch Conditionally

If CC then PC+d-PC

-

BCHG

Test a Bit and Change

- « bit number» OF Destination - Z
-«bit number» OF Destination OF Destination

- -

BClR

Test a Bit and Clear

BRA

Branch Always

BSET

Test a Bit and Set

- « bit number» 0 F Destination 1 - < bit number> OF Destination
PC-SP@-; PC+d-PC

-

0 0
0 0

Destination

- « bit number» OF Destination - Z
0-  -OF Destination
PC+d-PC
Z

Branch to Subroutine

- « bit number» OF Destination -

CHK

Check Register against Bounds

If On <0 or On> «ea» then TRAP

ClR

Clear an Operand

0- Destination

CMP

Compare

!Destination) - (Source)

CMPA

Compare Address

!Destination) - (Source)

CMPI

Compare Immediate

(Destination) - Immediate Data

-

CMPM

Compare Memory

!Destination) - (Source)

-

DBCC
DIVS

Test Condition, Decrement and Branch
Signed Divide

If-CC then Dn-1- On; if Dn* -1 then PC+d- PC

-

!Destination)/ (Source) -

Destination

-

DIVU

Unsigned Divide

!Destination)/ (Source) -

Destination

EOR

Exclusive OR logical

(Destination). (Source) -

EORI

Exclusive OR Immediate

!Destination) • Immediate Data -

EXG

Exchange Register

Rx-Ry

-

Z

Destination
Destination

EXT

Sign Extend

!Destination) Sign-extended -

Jump

Destination -

JSR

Jump to Subroutine

PC- SP@-; Destination- PC

lEA

load Effective Address

LINK

Link and Allocate

Destination - An
An-SP@-; SP-An; SP+d-SP

lSl, lSR

logical Shift

!Destination) Shifted by < count> -

MOVE

Move Data from Source to Destination

(Source) - Destination
(Source) -,CCR

1 set

32

Destination

PC

(Source)- SR

U defined

- - -

-

U U U
0

1 0 0

-

- - -

-

JMP

o cleared

- -

- - - - - - - - - - - - - - -

Test a Bit

Move to the Status Register

-

-

BSR

• affected
- unaffected

-

Destination

Destination

BTST

MOVE to SR

-

Destination
Destination

ADDO

MOVE to CCR Move to Condition Code

U

-

0
0
0 0
0 0

- -

- 0 0

- - - - - - - - - - - - - - - - 0

Destination

-

0 0

•

~

• '

•

II

, R68'OOOC4eR68000C6eR68000C8 ,
.

',
'

-,

'\,

" .........'.'

' .

~

TABLE 21 - INSTRUCTION SET (CONTINUED)

Mnemonic

Description

MOVE from SR Move from the Status Register

Condition
Codal
X N Z V C

Operation

-

SR - Destination
USP- An; An- USP .

MOVE USP

Move User Stack Pointer

MOVEA

Move Address

(Source) -

MOVEM

Move Multiple Registers

Registers- Destination
(Source) - Registers

MOVEP

Move Peripheral Data

(Source) -

MOVEQ

Move Quick

Immediate Data- Destination

- - - - - - -

- - - - - - - - - " 0 0
0 0
0 0
-

Destination

Destination

MULS

Signed Multiply

(Destination)"(Source) -

MULU

Unsigned Multiply

lDestinatiol))" (Source) -

Destination
Destination

NBCD

Negate Decimal with Extend

0- (Destination) 10- X -

Destination

NEG

Negate

O-lDestination)- Destination

NEGX

Negate with Extend

0- (Destination) - X- Destination

NOP

No Operation

-

NOT

Logical Complement

-lDestination) -

OR

Inclusive OR Logical

lDestination) v (Source)- Destination

ORI

Inclusive OR Immediate

lDestination) v Immediate Data- Destination

PEA

Push Effective Address

Destination -

RESET

Reset External Devices

-

ROL, ROR

Rotate (Without Extend)

lDestination) Rotated by

U

- -

Destination

S P@ -

< count> < count> -

-

Destination

ROXL, ROXR Rotate with Extend

(Destination) Rotated by

RTE

Return from Exception

SP@--SR; SP@+-PC

RTR

Return and Restore Condition Codes

SP@+-CC; SP@+-PC

RTS

Return from Subroutine

SP@+-PC

SBCD

Subtract Decimal with Extend

lDestination)lO- (Source)lO- X -

SCC
STOP

Set According to Condition
Load Status Register and Stop

If CC then 1's - Destination else O's Immediate Data-SR; STOP

SUB

Subtract Binary

(Destination) - (Source) -

Destination

SUBA

Subtract Address

(Destination) - (Source) -

Destination

SUBI

Subtract Immediate

lDestination) - Immediate Data -

Destination

SUBQ

Subtract Quick

lDestination) - Immediate Data -

Destination

SUBX

Subtract with Extend

(Destination) - (Source) - X-Destination

SWAP

Swap Register Halves

Register [31:16)- Register [15:0)

TAS

Test and Set an Operand

TRAP

- -

-

0

0

0

0

-

0

0

- - - - -

-

-

0

"

..
.

0

"

Destination

- Destination
Destination

U

"

-

U

U

-

"

- -

.- -

- "

- -

..

-

"
"

-

-

.

"

0

0

lDestination) Tested- CC; 1 - [7) OF Destination

-

"

0

0

Trap

PC-SSP@-; SR-SSP@-; (Vectorl-PC

-

TRAPV

Trap on Overflow

If V then TRAP

-

-

TST

Test an Operand

lDestination) Tested- CC

UNLK

Unlink

An-SP; SP@+-An

[

) = bit number

33

-

- - - - - 0

-

-

0

- -

•
~'-

....-.-

I

R68000C4.R68000C6·R68000C8
INSTRUCTION EXECUTION TIMES
The following paragraphs contain listings of the instruction execution times in terms of external clock (ClKI
periods. In this timing data, it is assumed that the memory
cycle time is no greater than four periods of the external processor clock input, which prevents the insertion of wait
states in the bus cycle. The number of bus read and write
cycles for each instruction is also included with the timing
data. This data is enclosed in parenthesis following the execution periods and is shown as: (r/wl where r is the number
of read cycles and w is the number of write cycles.

STANDARD INSTRUCTION CLOCK PERIODS
The number of clock periods shown in' Table 25 indicates
the time required to perform the operations, store the
results, and read the next instruction. The number of bus
read and write cycles is shown in parenthesis as: (r/wl. The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
In Table 25, the headings have the following meanings:
An = address register operand, Dn = data register operand,
ea = an operand specified by. an effective address, and
M = memory effective address operand.

NOTE
The number of periods includes instruction fetch and all
applicable operand fetChes and stores.

IMMEDIATE INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 26 includes
the time to fetch immediate operands, perform the opera~
tions, store the results, and read the next operation. The
number of bus read and write cycles is shown in parenthesis
as: (r/wl. The number of clock periods plus the number of
read and write cycles must be added to those of the effective
address calculation where indicated.
In Table 26, the headings have the following meanings:
# = immediate operand, Dn = data register operand,
M = memory operand, and SR = status register.

EFFECTIVE ADDRESS OPERAND CALCULATION TIMING
Table 22 lists the number of clock periods required to compute an instruction's effective address. It includes fetching
of any extension words, the address computation, and
fetching of the memory operand. The number of bus read
and write cycles is shown in parenthesis as (r/wl. Note there
are no write cycles involved in processing the effective address.

SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 27 indicates the number of clock periods for the
single operand instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/wl. The number
of clock periods plus the number of read and write cycles
must be added to those of the effective address calculation
where indicated.

MOVE INSTRUCTION CLOCK PERIODS
Tables 23 and 24 indicate the number of Clock periods for
the move instruction. This data includes instruction fetq"
operand reads, and operand writes. The number of bus read
and write cycles is shown in parenthesis as: (r/wl.

TABLE 22 -

EFFECTIVE ADDRESS CALCULATION TIMING

Addressing Mode

Byte, Word

Long

010/01
010/01

010/01
010/01

411/01
411/01
611/01
812/01
10(2/0)
8(2101
12(3/01
812/01
10(2/01
4(1101

812/01
812/01
10(2/0)
12(3/01
14(3/01
12(3/01
16(4/01
12(3/01
14(3/01
8(2/01

Register
On
An

Data Register Direct
Address Register Direct

An@
An@+

Memory
Address Register Indirect
Address Register Indirect with Postincrement

An@An@(dl

Address Register Indirect with Predecrement
Address Register Indirect with Displacement

An@(d, ixlxxx.W

Address Register Indirect with Index
Absolute Short

xxx.L
PC@(dl

Absolute Long
Program Counter with Displacement

PC@(d, ixl-

Program Counter with Index
Immediate

Ixxx

"The size 01 the index register (ixl does not affect execution time.

34

R68000C4.R68000C6·R68000C8

.

-

.

.

.

TABLE 23 - MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS
Source

An
4(1/01
411/01
8(2/0)

On
411/01
411101
8(210)

On
An
An@

14(3/01
12(3/01
16(4/0)

8(2/01
10(2101
12(3/0)
14(3/01
12(3/01
16(4/01

12(3/01
14(3/0)
8(2/01

12(3/01
14(3/01
8(2/01

An@+
An@An@(dl

812/01
10(2/0)
12(3/0)

An@ld, ix)·
nx.W
nx.L
PC@ldl
PC@(d, ixl'
Ixxx

Destination
An@9(111)
911/11
9(111)
9(111)
13(211)
13(211)

An@

An@+

911111
911111
13(2/1)

An@ldl
13(2/1)
13(2/11
17(3/1)

An@ld,ixl·

15(2/1)
15(211)
19(3/1)

xxx.W
13(2/1)
13(2/1)
17(3/1)

xxx.L
17(3/11
17(3/11
21(411)

1913/11
21(311)
23(411)
25(411)
23(411)
27(511)

1713/11
19(3/1)
21(4/1)
23(4/1)
21(4/1)
25(511)

21(4/1)
23(4111
25(5/11
27(5/1)
25(5/1)
29(6/11

23(4/11
25(4/1)
19(3/11

2114/11
23(411)
17(3/1)

25(5/1)
27(5/11
21(4/11

19(3/1)
17(3/1)
21(411)

13(2/11
1512/11
1713/11
1913/11
17(3/1)
21(4/1)

19(3/11
17(311)
21(411)

17(3/11
1913/11
2114111
23(411)
21(4/1)
25(5/1)

17(3/1)
19(3/11
13(2/1)

17(311)
19(3/11
13(211)

17(311)
19(311)
13(2/11

2114/11
23(4/11
17(311)

13(211l
15(2/11
17(311)

13(211)
15(3/11
17(3/1)

"The size of the index register (ix) does not affect execution time.

TABLE 24 -

SourCe

MOVE LONG INSTRUCTION CLOCK PERIODS

An@

An
An@

On
4(1/0)
4(1/0)
12(3/01

An
4(1101
4(1/01
12(3/01

14(1/2)
14(1/2)
22(312)

An@+
14(1/2)
14(1/2)
22(3/2)

An@+
An@An@ld)

12(3/01
14(3/0)
16(4/0)

12(3/0)
14(3/01
16(4/01

22(312)
24(3/2)
26(412)

An@ld, ixl'
xxx.W
xxx.L

18(4/01
16(4/01
20(5/0)

PC@ldl
PC@ld, ixl'
Ixxx

16(4/0)
18(4/0)
12(3/01

18(4/01
16(4/01
20(5/01
16(4/01
18(4/01
12(3/01

28(412)
26(412)
30(5/2)
26(412)
28(412)
22(312)

On

Destination
An@16(112)
16(1/2)
22(3/2)

18(iI2)
18(2/2)
26(4/2)

20(212)
20(212)
26(4/2)

xxx.W
18(2/2)
18(2/2)
26(4/2)

xxx.L
22(312)
22(312)
30(5/2)

22(3/2)
24(3/2)
26(4/2)

22(3/2)
24(3/2)
26(4/2)

26(4/6)
28(412)
30(5/2)

28(4/2)
30(4/2)
32(5/2)

26(4/2)
28(4/2)
30(5/2)

30(5/2)
32(5/2)
34(6/2)

28(4/2)
26(4/2)
3(j(5/2)

28(4/2)
26(412)
30(5/2)
26(4/2)
28(4/2)
22(3/2)

32(5/2)
30(5/2)
34(6/2)
30(5/2)
32(512)
26(4/2)

34(5/2)
32(5/2)
36(6/2)

32(5/2)
30(5/2)
34(6121

36(6/2)
34(6/2)
38(7/2)

32(5/2)
34(5/2)
28(4/2)

30(5/2)
32(5/2)
26(4/2)

34(6/2)
36(6/2)
30(5/2)

26(4/2)
28(4/2)
22(3/2)

An@ldl An@ld,ixl"

"The size of the index register (ix) does not affect execution time.

TABLE 25 Instruction
ADD
AND
CMP

Size

op , An

op , On

op Dn, 

8(1/01+

4(1/01+

Long

611/01+""

6(1/01+""

9(1/1)+
14(1/2)+

Byte, Word
Long

-

4(1101+
6(1/01+""

911111+
14(1/21+

Byte, Word

Byte, Word
Long

DIVS

-

DIVU

-

fOR

STANDARD INSTRUCTION CLOCK PERIODS

Byte, Word
Long

6(1101+
6(1/01+

411/01+
611101+

-

140(1/01 +"

-

158(1/01+"
4(110)"'"

-

9(111)+
14(1/2)+

-

-

811/01"""
70(1/01+"
70(1/01+'

-

OR

Byte, Word
Long

-

-

4(110)+
6(1/0) +""

911111+
14(1/2)+

SUB

Byte, Word
Long

411101+
6(1/01+""

9(1/1)+
14(1/2)+

MULS
MULU

+ add effective address calculation time
" indicates maximum value

8(1101+
611101 + ,"

-

". total of 8 clock periods for instruction if the effective address is register direct
•• " only available effective address mode is data register direct

35

R68000C4-R68000C6-R68000C8
TABLE 26 - IMMEDIATE INSTRUCTION CLOCK PERIODS
Instruction

Size
Byte. Word

ADDI

Long
BYte, Word

ADDO

Long

ANDI

Byte. Word
Long

CMPI

BYte, Word
Long
Byte. Word

EORI

Long

MOVEO

Long
BYte. Word
Long

ORI

BYte, Word

SUBI

Long
BYte, Word
Long

SUBO

op I. Dn
8(2101
18.(3/01
411101
811/01
8(2/01
18(3/01
8(2/01
14(3/01
8(2101
18(3/01
411/01
8(2/01
18(3/01
8(2/01
18(3/01
4(1101
811/01

opl. M

op I. SR

13(2/11+
22(3/21+

-

911/11+
1411/21+
13(2/11+
22(3121+
8(2/01+
12(3/01+

20(3101

13(2/11+
22(3121+

20(3101

-

-

-

13(2/11+
22(3121+

13(2111+
22(3121+
9(1111+
14(1/21+

20(3101

-

-

+ add effective address calculation time

TABLE Xl - SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Instruction
CLR
NBCD

Size

Register

Memory

Byte, Word
Long

4(1101
6(1/01
6(1101
4(1101
6(1/01
4(1101
6(1/01
4(1101
6(1/01
4(1101
6(1/0)
4(1/01
4(1/01
4(1/01

911/11+
14(1/21+
9(1/11+

BYte

NEG

Byte. Word
Long

NEGX

Byte, Word
Long

NOT

Byte. Word
Long
Byte, False

SCC
TAS
TST

Byte, True
Byte
Byte, Word
Long

911/11+
14(1/21+
911/11+
14(1/21+
9(1111+
14(1/21+
9(1/11+
9(1/11+

1111111 +
4(1/01
4(1/01+

+ add effective address calculation time

CONDITIONAL INSTRUCTION CLOCK PERIODS

SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
Table 28 indicates the number of clock periods for the shift
and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/wl. The number of
clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.

Table 30 indicates the number of clock periods required for
the conditional instructions. The number of bus read and
write cycles is indicated in parenthesis as: (r/wl. The number
of clock periods plus the number of read and write cycles
must be added to those of the effective address calculation
where indicated.

BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Table 29 indicates the number of clock periods required for
the bit manipulation instructions. The number of bus read
and write cycles is shown in parenthesis as: (r/wl. The
number of clock periods plus the numbe"r of read and write
cycles must be added to those of the effective address
calculation where indicated.

JMP, JSR. LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 31 indicates the number of clock periods required for
the jump. jump to subroutine. load effective address. push
effective address. and move multiple registers instructions.
The number of bus read and write cycles is shown in parenthesis as: (r/wl.

36

...

R68000C4.R68000C6·R68000C8.....~.

,~ .

;r

I

.,

TABLE 28 - SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
Instruction

Size

Register

Memory

AsR,AsL

Byte, Word
Long

6 + 2n(1/0)
8 + 2n11/0I

911/11 +

LsR, LsL

Byte, Word
Long

6 + 2n11/0I
8 + 2n1.1/0I

9(1/11 +

Byte, Word

6 + 2n(1/01
8 + 2n11/01

9(1/11+

6 + 2n11/01
8 + 2n(1/0I

9(1111+

ROR,ROL

Long
Byte, Word

ROXR,ROXL

Long

TABLE 29 -

Instruction

Byte
Long

BCLR

Byte
Long

BsET

Bvte
Long

BTsT

-

BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Dynamic

Size

BCHG

-

Static

Register

Memory

Register

-

9(1/11+

-

-

8(1101-

-

Memory
13(211)+

-

12(2/01-

911111+

10(1101-

-

-

9(1111+

Byte

-

Long

6(1/01

-

1312111+

-

14(2/01-

-

1312111+

4(1/01 +

-

812/01+

-

10(2/01

1212/01-

811101-

-

+ add effective address calculation time
• indicates maximum value

TABLE 30 - CONDITIONAL INSTRUCTION CLOCK PERIODS

Instruction
Bee

BRA
BsR
DBce
CHK
TRAP
TRAPV

Trap or Branch
Taken

Displacement

Word

10(1/01
10(1/01

Byte
Word

10(1/01
10(1/01

Byte

20(212)
20(2/2)

Byte

Word

-

ec true

1012/01
43(513)+ 37(4/3)

ee false

-

3715/3)

+ add effective address calculation time
• indicates maximum value

37

Trap or Branch
Not Taken
8(110)

12(2/01

-

-

12(2/01
14(3/0)
8(1/01+

411/0)

TABLE 31 - JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
Instr

Size

-

An@

An@+

An@-

812/0l
18(2/2)

-

-

14(1/2)

-

MOVEM

Word

12+40
13+ n/Ol

12+40
13+ n/Ol

M-R

Long

12+8n
13+2n/0l

12+8n
13+ 2n/0l

MOVEM

Word

8+50
12/n)

R-M

Long

8+1On
(2/2n)

JMP
JSR
LEA
PEA

411/0l

-

An@(d)

An@(d, ix)"

PC@(d)

PC@(d, ix)"

'XJU.W

'XJU.L

24(2/2)

1012/0l
20(212)

1213/0l
22(3/2)

20(2/2)

1413/0l
24(2/2)

812/0l
18(2/2)

1212/0l
22(212)

812/0l
18(2/2)

1213/0l
22(312)

812/0l
18(2/2)

1212/0l
22(212)

16+40
14+ n/Ol

18+40
14 + n/Ol

16+40
14+ n/Ol

20+40
15+ n/Ol

16+40
14 + n/Ol

18+40
14+n/0l

16+8n
14+ 2n/0l

18+8n
14+ 2n/0l

16+8n
14+2n/0l

20+8n
15+2n/0l

16+8n
14+2n/0)

18+8n
14+2n/0l

8+50
12/n)

12+50
13/n)

14+50
(3/n)

12+50
(3/n)

16+50
14/n)

-

8+ 10n
12/2n)

12+1On
13/2n)

14+ 10n
13/2n)

12+1On
13/2n)

16+1On
14/2n)

-

-

-

1012/0l
20(212)

1413/0l

n is the number of registers to move
• is the size of the index register lix) does not affect the instruction·s execution time

~

TABLE 32 - MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Instruction

Size

op On, On

ADDX

Byte, Word
Long

41l/0l
81l/0l

opM, M
19(311)
32(5/2)

CMPM

Byte, Word
Long

-

201510l

SUBX

Byte, Word
Long

411/0l
81l/0l

1913/1l
32(5/2)

ABCD

Byte

61l/0l

19(311)

SBCD

Byte

611/0l

19(311)

12(3/0)

1012/0l

-

-

RS8000C4-RS8000CS-RS8000C8
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 32 indicates the number of clock periods for the
multi-precision instructions. The number of clock periods includes the time to fetch both operands, perform the operations, store the results, and read the next instructions. The
number of read and write cycles is shown in parenthesis as:
Ir/wl.
In Table 32, the headings have the following meanings:
Dn = data register operand and M = memory operand.

read and write cycles is shown in parenthesis 8S: Ir/wl. The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.

EXCEPTION PROCESSING CLOCK PERIODS
Table 34 indicates the number of clock periods for exception processing. The number of clock periods includes the
time for all stacking, the vector fetch, and the fetch of the
first instruction of the handler routine. The number of bus
read and write cycles is shown in parenthesis as: Ir/wl.

MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Table 33 indicates the number of clock periods for the
following misce'lIaneous instructions. The number of bus

TABLE 33 - MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Register

Memory

MOVE from SR

-

6(1/0)

-

MOVE to CCR

-

12(2/01
12(2/01

9(1111+
12(2/0)+
12(2/01+

-

-

-

18(2/2)
28(2/4)

16(4/0)
24(6/0)

-

-

Instruction

MOVE to SR
MOVEP
EXG

EXT
LINK

Size

Long

Long

-

MOVE to USP
NOP

-

RESET
RTE
RTR
RTS
STOP
SWAP
UNLK

611/01
4(1101
4(1/01
18(2/2)
4(1101

Word

-

MOVE from USP

-

Word

4(1/01

4(1/01

-

13211/01
2015101

-

16(4/01
4(010)

-

4(1/01
12(3/01

20(5/01

-

Register -

Memory

-

-

-

+ add effective address calculation time

TABLE 34 -

EXCEPTION PROCESSING CLOCK PERIODS
exception

Perioda

Error
BUI Error

57(4171
57(417)
47(5/3)37(4/31
37(4/3)
37(4/3)

Addr_

Interrupt
Illegal Instruction
Privileged Instruction
Trace

"The interrupt acknowledge bus cycle is assumed
to take four external clock periods

39

Memory-R..,

-

-

-

R68000C4.R68000C6.R68000C8

FIGURE 31 - AC ELECTRICAL WAVEFORMS

These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a
functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation.

\

~

,
--@-----

;-- --

\

r-------

H9---

- i€>

®

\1
~

€} o..--@"-

'e/I

I

C-!~
- l@- ~~

~kD--

-e- ~~-

b------,
ClK

A23-Al
FC2-FCO

'---

~

I:---

~ ----<

Gr

~

~

@-

i--f-

'----

/
5

rns. ODS Write Cyel e

~
r- - - -

-~

r-&f.- 0.
rns. (J"[)S Read Cyele

t-----

I@

J

L

k2r
\

.J

fji.'f.?J

14
'--

r----

--

--II

Riw

Read Cycle

:&

~"\

R/W Write Cyele

CDData Ou t

AsynchronOlls Inputs
(See Note 1I
HALT.

~

"----

-@-

~

'1;.7

~

r-------~
®---1

------

}-----

r----

)t

iITSEf (Input ~----------------

--------------------

~~
r---

------------------

--------

\

~
Data In ---------------------------------~

~

4

~
~

}----

NOTE 2: Waveform measurements for all inputs and outputs are

NOTE 1: Setup time for the asynchronous inputs BERR. BGACK.

specified at: logic high = 2.0 volts, logic low =0.8 volts.

BR. O'TACK, IPLO-IPL2, and VPA guarantees their recognition at the next falling edge of the clock.

40

}

. .
."
,RS8000C4.RS8000CS.RS8000C8
.
,4. .

.,

~.

~

AC ELECTRICAL SPECIFICATIONS (Vcc

=

~

. , '

~

I 'L'

• \

50 Vdc

,

+

5%; Vss

= 0 Vdc' TA = O'C 10 70'C

Figure 31)

4 MHZ
Number

6 MHz

8 MHz

Symbol ~~R~~~~C4~+-R_~~~~C~6_+-R-6-8,~--C8~
Min
Max
Min
Max
Min
Max

Characteristic

Unit

Clock Period

ICYC

250

500

167

500

125

500

ns

Clock Widlh low

ICl

115

250

75

250

55

250

ns

Clock Widlh High

ICH

115

250

75

250

55

250

ns

Clock Fall Time

ICt

10

ns

10

10

Ic,

10

10

10

ns

ICLAV

90

80

70

ns

Clock High 10 Address/FClDala High Impedance (maximum)

ICHAZx

120

100

80

ns

Clock High 10 Address/FC Invalid (minimum)

ICHAZn

9'

Clock High 10 AS. OS low (maximum)

ICHSlx

10

Clock High 10 AS. OS low (minimum)

ICHSln

Clock Rise Time
Clock Low 10 Address/FC Valid

20

20

70

80
20

ns

20

-

20

-

ns

60

20 -t-_-_-1I--_n_s_

f____l_l'__~-A-d-d-re-$-/-FC~V=al~id~IO~A-S~.O~S~(~re~a~d~)L~0~w_______________+--~tA~v~Sl~+-~5~5_+----~~35~~---.~-~301-----~_n_s___ ~

r-__l_2_'__i_C_I_OC_k_l_o_W_10__
AS~.~O_S_H_i~9h______________________-+__~tC~l~SH~+_----,-9-0-4-----1--8-0~ ___
13'

AS. OS High 10 Address/FC Invalid

14'

AS. OS Widlh Low

~_~

ISHAZ

60

-

40

-

30

-

ISl

285

-

170

-

115

-

ns

1---ns

r-~1~5'__~A~S~.~O~S~W~i~dt~h~H~ig~h~------------------------_+----t~s~H__ ~_2_8_5_r__ _+-18_0-+__
-_t_l_5_0 r_---+--~ns~16

Clock High 10 AS. Os High Impedance

ICHSZ

17'

OS High 10 AIW High

ISHAH

18'

Clock High to R/W High (maximum)

tCHAH

120

-

40
80

90

ns

80

I 100

50

60

ns
,------70
ns
f---------

:____1~9___ ~C~IOC~k~H~ig~h~IO~A/~W~H~ig~h~(m~in~i~m~Um~)~--______________r-~IC~H~A~H~n_~~20~.r_---~-~20~~--- ~

r--____ns___

r-~2~O'__~C~I~oc~k~H~ig~h~I~0~~~W~lo~w~----------------------_+--~IC~H~A~l_+-----~9~0__ +-----~~8~0-+___
-

70

ns

r-~2~l'___ rA~d~d~re~s~s/~FC~V=al~id~IO~R~/W~lO~W~___________________+--~tA~V~AlL-r-~45~~---.~=25~~~-I~
~W

22'

low 10 OS low (write)

IAlSl

200

-

140

-

80

-

ns
ns

r-~2~3__~C~I~oc~k~l=0-w~lo~Oa~l=a=O=ul=V~a~li=d--------------------_+__~IC~l~OO~+-_-_ _t~OO~~----1~8~0-~-+--70-~---ns----i

+-__~ltC~H~A~Z_+-----+-1=20~-----l--l0~0~t----~8~0.~__n~s___ 1

r-~2~4__~C=I~oc~k~H~ig~h~I=0~R~/W~.~V~M~A~H~i~gh~l~m~pe~d=a=nc=e~____________
25'

OS High 10 Oala Oullnvalid

ISHOO

60

-

~40i-=-+-~-

ns

~-=2~6'--+O~a:..::la~O::..u::.:l-,v..:::a~lid:....I:::.0~Oc::S-=l=0.:..:.w...!.(w:..::r..:.:ile=.!.)--________________+--I"'O""-"'OS,l"--~ __=55~ -

35

i~

30

-

ns

1--~2~7__+0~a~la:....l..:.:n~lo:....C~I~OC~k:..::l~0~w...!.(s=e~l~up:....l:....im..:.:e~)--________________r_--~to~IC~l~-I--=30~

25

t~

15

-

ns

-

1--__
2_8'__~O-S-H-i~gh--lo-O-T-A-C-K-H~ig~h------------------------+_--IS~H~O~A~H~--,0__1--24~0~.~_+_1_60_
r-__2_9__~O_S__
H~ig_h_lo_O_a_la_l_nv_a_li_d~(h-=0-=ld_li_m-=e~)________________-+__~tS~H~O~I_~~O~+___ ~~30

AS. OS High 10 BEAR High

ISHBEH

0

~

-

I

0

I

-

0

r~~

0

-

ns

0

-

ns

90- -n-s--r -__3_2__~H_A_l_T_a_n_d_A=E=SE=T~ln~pu~I~T-,ra=ns~il~io~n-,T~im..:.:e_______________+--~tA~H~'t~+-~0~+-2~00~~1~rcJ ~
ns
OTACK low to Data In (setup time)

31'

1__

IOAlOI

180 I -

: 120

~3~3--~C~I~OC:....k~H~ig~h~I~0~B~G~l=0.:..:.W------------------------_+--~tc~H~G~l_+___- __~OO~1.__
- __ 1 80
34

Clock High 10 BG High

~t-B_R_L_OW__IO_B_G__lO_W___________________________ Ii

tCHGH
tBALGl

I

-

9O! -

1.5

3.0! 1.5

3,0

__t-"B-",RH,,-,G,,-H,-+__1~.5-+-,3=-'0'--tI__
l...:.....,5 j~

36

BR High 10 BG High

37

BGACK low 10 BG High

38

BG low 10 Bus High Impedance (wilh AS high)

IGlZ

39

BG Width High

tGH

40

Clock low 10 VMA low

41
42

IGALGH

1.5

3.0

1.5 i 3.0

1.5

1.5

1.5

70

ns

1.5

3,0

elk. per.

1.5

3.0

elk. per.

1.5

3.0

elk. per.

1.5

-=_

clk. per.

ns

;80 -

1.5

~

1.5

ns

elk. per.

ICLVMl

90

80

70

Clock low 10 E Transilion

tClE

65

60

55

ns

E OulpUI Rise and Fall Time

IE,t

25

25

25

ns

1--__
4~3'__1-V~M~A~l~0=-W=-I~0~E=-H~lg~h~_________________________+--~IV~/~~E~H~~3~2~5_+-___~2:....4~0~ __-__+~2~00
44

AS. DS High 10 VPA High

45

E Low 10 AddressNMNFC Invalid

tSHVPH

0

tELAI

55

240

0

160

35

0
30

~_

ns

120

ns

-

+_....cn.:.::.s_-j

r-__4_6__~B-G-A-C-K-W-i-dl-h------------------------------+_--~tB~G~l--l---l.~5_+-_-__4_1__.~____ ~_~_ ~
r-__4_7__-rA~s~Y-,nc=-h~ro=-no~u~s~ln~p~u~I~~lu~p~T=-im~e~__________________+_---'t~AS~II--+-~30~-~_

25

-

20

-

ns

1--__4~8__+B:..::E~A-R~l::..:0=W=_IO~O-'TA-,C=-K~l::.:o=-w'--____________________-t ___~1B",E""lO""Ao=L-t_-,-50,,-- _ _ _ ~_ I - - - ~. _ _ _ _
ns___

+ . .:E::....::.:LO=-W~I:::.O~A~S~.-O=-S::....::.:ln~va::..:l~id------------------------r_--.:..!tE"'L"'SI_I----'8:.::..0_

1--__4~9__
50

E Width High

tEH

900

-

-80
600

-

.. 80
·150

-_~
~

ns

-

ns

____5_1__ ~_E__
W_id_lh_l_o_w_______________________________ ~____I~E~l__~1_40_0~___~9_0_0.~_____ ~700
NOTE 1: For a loading capacilance of less than or equal to 50 picofarads.
subtracl 5 nanoseconds from Ihe values given in Ihese columns.

NOTE 2: Aclual value depends on actual clock period

41

FIGURE 32 -

AC ELECTRICAL WAVEFORMS -

BUS ARBITRATION

These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are
not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related
diagrams for device operation.

~

Strobes
and R/IN

3~

BR
37

-@

BGACK

3S--~

3'3

34'

I

BG
33

.t>.

38

N

AC ELECTRICAL SPECIFICATIONS-BUS ARBITRATION (Voo
Number

Characteristic

~

5.0 Vdc =: 5%; Vss = 0 Vdc; T A
Symbol

~

O'C to 70'C. Figure 32)

4 MHZ

6 MHz

8 MHz

R6800OC4

R68000C6

R68000CB

Min

Min

Min

Max

Max

Unit

Max

33

Clock High to BG Low

tCHGL

-

90

-

80

-

70

ns

34

Clock High to BG High

tCHGH

-

90

-

80

-

70

ns

35

BR Low to BG Low

'BRLGL

1.5

'3.0

1.5

3.0

1.5

3.0

elk. per.

36

BR High to BG High

tBRHGrl

1.5

3.0

1.5

3.0

1.5

3.0

clk. per.

37

BGACK Low to BG High

tGALGH

1.5

3.0

1.5

3.0

1.5

3.0

clk. per.

38

BG Low to Bus High Impedance (with-AS high)

tGLZ

0

1.5

0

1.5

0

1.5

clk. per.

-

clk. per--,-

--.

39

BG Width High

tGH

1.5

-

1.5

46

BGACK Width

tBGL

1.5

-

1.5

NOTE 1: Setup time for the asynchronous inputs BERR. BGACK. BA.
DTACK. IPLO-IPL2. and VPA guarantees their recognition at the
next falling edge of the clock.

-

- I

1.5
1.5

clk. per.

NOTE 2: Waveform measurements for all inputs and outputs are specified dt: logic high - 2.0 volts. logic low - 0.8 volts.

R68000C4.R68000C6·R68000C8

ELECTRICAL CHARACTERISTICS (VCC=5.0 Vdc±5%; VSS=O Vdc; TA OOC to 70°C. Figures 33.34.35)
Symbol
Min
Characteristic
Input High Voltage

VIH

2.0

Input Low Voltage

VIL

VSS-0.3

SERR.SGACK.BR.DTACK.
iPLa-ru. VPA
HALT. RESET

Input Leakage Current

Typ

Max

Unit

-

VCC
O.S

Vdc
Vdc

1.0
2.0

-

"Adc

7.0

-

"Adc

Three-State (Off State) Input Current

AS. A1-A23. DO-D15
FCO-FC2. [55. R/IN. iToS. VMA

ITSI

-

Output High Voltage UOH = - 400 "Adc)

AS. A1-A23. BG. DO-D15. E.
FCO-FC2. [55. R/W. UDS. VMA

VOH

2.4

-

-

Vdc

HALT
A1-A23. BG. E. FCO-FC2
RESET
AS. DO-D15.l5S. R/W.
UDS. VMA

VOL

-

-

0.5
0.5
0.5
0.5

Vdc

Output Low Voltage
(lOL= 1.6mAl
(lOL =3.2 mAl
(lOL=5.0mAl
(lOL =5.3mAl

lin

-

Power Dissipation (Clock Frequency = S MHz)

PD

-

1.0

-

W

Capacitance (Package Type Dependent)
(Vin=OVdc; TA=25°C; Frequency = 1 MHz)

Cin

-

10.0

-

pF

FIGURE 33 - RESET TEST LOAD

FIGURE 34 - HALT TEST LOAD

FIGURE 35 - TEST LOADS
+5 Vdc

Q
+5 Vdc

~910D

~29kO

RESET

I

<>
>Ro=7400

+5 Vdc
Test
Point

HALT

130pF

r:'"

>
~

~,

70PF

~,

-=
-

--

~

...

~RL

l

e

1

--

±

....

MMD6150 •
or Equivalent

MMD7000
or EqUivalent

~,
CL = 130 pF
'(Includes all Parasitics)
RL = 6.0 kO for
AS. A l-A23. BG. DO-D15. E
FCO-FC2. lDS. R/W. UDS. VMA
OR = 1.22 kO for A l-A23. fiG.
E. FCO-FC2

-:?"

•
~'-

: ":

FIGURE 36 - INPUT CLOCK WAVEFORM

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3to+7.0

Vdc

Input Voltage

Yin

-0.3 to + 7.0

Vdc

Operating Temperature Range

TA
Tstg

o to 70

°c

-55 to 150

°C

Rating

+-tcyc---'

~tCl~

~~~

0.8V

~

tCr

Storage Temperature

I

CLOCK TIMING (Figure 36)
Characteristic

Symbol

Frequency ot Operation

4 MHz

6 MHz

R68000C4

R68000C6

8 MHz
R68000C8

Unit

Min

Max

Min

Max

Min

Max

Unit

F

2.0

4.0

2.0

6.0

2.0

8.0

MHz

Cycle Time

tcyc

250

500

167

500

125

500

ns_

Clock Pulse Width

tCl
tCH

115
115

250
250

75
75

250
250

55
55

250
250

ns

Rise and Fall Times

tCr
tCt

-

10

-

10
10

-

10
10

ns

43

10

~

R68000C4.R68000C6·R68000C8

_

~~:o:~1~l~:]J

f
I-~- [E ------11

ii" .

NOTES:
1. DIMENSION [AJIS DATUM.
2. POSITIONAL TOLERANCE FOR LEADS:
1$10.25 (O.010)@IT 1A ®

I

3. II] IS SEATING PLANE.
4. DIMENSION."L"TO CENTER OF LEADS
WHEN FORMED PARALLEL.
5. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5, 1973.
MILLIMETERS
MIN
MAX
80.52 82.04
22.25 22.96
4.32
3.05
0.53
0.38
1.40
0.76
2.54 BSC
0.33
0.20
4.19
2.54
L
22.61 23.11
100
M
N
1.52
1.02

DIM
A
B
C
0
F
G
J
K

INCHES
MAX
MIN
3.170 3.230
0.876 0.904
0.120 0.170
0.015 0.021
0.030 0.055
0.100 BSC
0.008 0.013
0.100 0.165
0.890 0.910
100
0.040 0.060

R68120
R68000 Microcomputer System
PRODUCT PREVIEW
INTELLIGENT PERIPHERAL CONTROLLER (IPC)
The R68120 Intelligent Peripheral Controller (IPC) is a general-purpose, user-programmable, peripheral controller. It
contains a system interface, an 8-bit CPU, a serial communications interface, 21 parallel 110 lines, a 16-bit timer, 2048
bytes of ROM, and eight operating modes. In addition, the
R68120 features 128 bytes of dual-ported RAM and six semaphore registers that are accessable to both the internal CPU
and an externat processor or device through the system interface. The R68120 provides all the control signals necessary to interface with the asynchronous bus of the R68000.

HMOS
(HIGH DENSITY N-CHANNEl,
SILlCON·GATE DEPLETION LOAD)

INTELLIGENT
PERIPHERAL CONTROLLER

• Bus Compatible with the 16-Bit R68000 Microprocessor
• Bus Compatible with all 6500 and 6800 Family Processors
and Peripherals
• TIL Compatible 110
• Single 5-Volt Power Supply
• 8-Bit CPU
• 2K Bytes ROM

PIN ASSIGNMENT

• 128 Bytes Dual-Ported RAM

Vss

• 6 Shared Semaphore Registers

IR01

• External Clock Input
• 16-Bit Timer

HAlT/BAINMI

• 21 Parallel I/O and Two Handshake Lines
• Serial Communications Interface

S.R/W

• Interrupt Capability

OTACK

• Operates in Single-Chip Mode or Expandable to 64K Byte
Addressing Range

CS
S.A7

• DMA Capability

S.A6

• 8 x 8 Bit Multiply

S.A5

• Software Control of:
Semaphore Registers
16-Bit Timer
Serial Communications Interface
Parallel I/O Ports
Interrupts

S.A4

Vee
S.A3
S.A2
S.A1

PROGRAMMING MODEL

S.AO
S.OO

1'
...________----'°1 ,.,....."... "
-'01 s·~, Pa·r'e'

...
1" _ _ _ _ _
"____

....I·~_____rc_ _ _ _.....ol

1I

p.Q9 .....

SP

c~,,~!.· ~~

:.""":C""~,""C ...... '.•. ,cc.
Bo"o .... ·o .... VS8
0.,.04'0'"

S.01
S.02
S.03
S.04
S05

(."\1'

z...

~·'W.

1"le" .. ,,·

......'c .. ·.,.'·0"'8·)1

S.06
S.07

R68120

BLOCK DIAGRAM

(5_
S RIIN
-OTACK

S DO
SO,
S 02
S 03
S 04
S 05
S 06
S 07

r=E=#i 1

H -- - - - - ,

1~
I

H"ALf BA,NMI

P=i

V>

SAO
SAl

110 Po"l

S A2

i

S A3
S A4

S A5

iRQ,

S A6
- 5 A7

RTSET

Vss
vee

j

SI~gle

ch'Plgg g g g ~g gl~l~
Expanded Non-M ul"PI.X.d{88 8 (Ii 8 c: 0 81~IQ

SUMMARY OF OPERATING MODES
Common to all Modes:
System Bus Interface
Reserved Register Area
6 Semaphore Registers
I/O Port 2
16-Bit Programmable Timer
Serial Communications Interface
12B Bytes of Dual-Ported RAM

--

Single Chip Mode - Mode 7
2048 Bytes of ROM (Internal)
Port 3 is a Parallel I/O Port with Two Control Lines
Port 4 is a Parallel I/O Port
SCI is Input Strobe 3 (lS3)
SC2 is Outout Strobe 3 (OS3)
Expanded Non-Multiplexed Mode - Mode 5
2048 Bytes of ROM (Internal)
256 Bytes of E_ternal Memory Space
Port 3 is an 8-Bit Data Bus
Port 4 is an Address Bus
SCI is Input/Output Select (lOS)
SC2 is Read/Write (R/W)

Rockwell
International

Expanded Multiplexed Modes - Modes 1, 2, 3, 6
Four Memory Space Options (64K Address Space):
(1) MOOS Compatible
(2) No ROM
(3) External Vector Space
(4) ROM with Partial Address Bus
External Memory Space Accessed Through:
Port 3 as a Multiplexed Address/Data Bus
Port 4 as an Address Bus (High)
SCI is Address Strobe (AS) Input
SC2 is Read/Write IA/W)
Test Modes - Modes 0, 4
Expanded Multiplexed Test Mode May be Used to Test RAM and ROM
S;~gle Chip and Non-Multiplexed Test Mode May be Used to Test Ports 3 and 4 as I/O Ports

~'l!'!I!'!:I!II'IEI:lt
Electronics Devices Division
P.O. Box 3669, RC55; Anaheim, CA 92803
Phone (714) 632-3729

R68451

'1'

R68000 Microcomputer System

Rockwell

PRODUCT PREVIEW

MEMORY MANAGEMENT UNIT (MMU)
HMOS
The R68451 Memory Management Unit (MMU) provides address translation and protection of the 16 megabyte addressing space of the R6S000. The MMU can be accessed by any
potential bus master, such as instruction set processors, or
DMA controllers. Each bus master (or processor) in the
R6S000 family provides a function code and an address during each bus cycle. The function code specifies an address
space while the address specifies a location within that address space. The function codes are provided by the R6S000
to distinguish between program and data spaces as well as
supervisor and user spaces. This separation of address
spaces provides the basis of protection in an operating system. By simplifying the programming model of the address
space, the MMU also increases the reliability of a complex
multi-process system.

(HIGH DENSITY N-CHANNEL.
SILlCON·GATE DEPLETION LOAD)

MEMORY
MANAGEMENT UNIT

• Separates Address Spaces of System and User Resources
• Provides Write Protection
• Increases System Reliability
• Provides Efficient Memory Allocation

FUNCTIONAL DIAGRAM

• Allows Interprocess Communication through Shared Resources
• Simplifies Programming Model of Address Space

A8·A23

MAS

• Minimizes Operating System Overhead with Quick Context Switches
• 32 Segments with Variable Segment Sizes
• Multiple MMU System Capability
• Supports both Paging and Segmentation
• DMA Compatible
• Provides Virtual Memory Support
• R6800D Bus Compatible

CS
FCJ

IAQ

FC2

lACK

FC1
FCC

A68451

A'\8·AI\23
00·015

As
UOS

EO

LOS

HAO

AlW
OTACK
BEAA

GO
CLOCK
RESET

VCC

ALL

R68451

. .

MAPPING LOGICAL SEGMENTS TO PHYSICAL MEMORY

Read
Only

A
Shared
Data

Read
Only

A
Program
A

Read/
Write

A
Stack

Shared
Data

Undefined

Read
Only

B

A

Program

B

B

Read
Only

B

Shared
Data

Undefined
Read/
Write

B
Stack
B

Read/
Write

B
Data

Physical Memory

Logical Address Space

Rockwell
Internationa,l

Electronics Devices Division

P.O. Box 3669, RC55; Anaheim, CA 92803 - - - - - - - - - - - '
Phone (714) 632-3729

R68450
'.,1".~t../.. _l~~,t"..\:: ~...

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R68000 Microcomputer System

:;i

PRODUCT PREVIEW

DIRECT MEMORY ACCESS CONTROLLER (DMAC)
HMOS
The R68450 Direct Memory Access Controller (DMAC) offers
the system deSigner unparalleled performance where both
speed and flexibility in data transfer are required. Sophisticated chaining techniques. memory-to-memory block transfers. and variable bus bandwith utilization result in optimum
data transfers. Internal 32-bit address registers provide upward software compatibility with future R68000 Family processors.

(HIGH DENSITY N-CHANNEL,
SILICON-GATE DEPLETION LOAD)

DMA CONTROLLER

• Compatible with both R68000 Family and 6500/6800 Peripherals
• Four. Fully-Independent Channels
• Single or Dual Address Transfers
FUNCTIONAL DIAGRAM

• Byte. Word. or Long Word Transfers
• Memory-to-Memory Block Transfers
• Supports both Chained and Unchained Operations
• Transfer Rates up to 4 Megabytes Per Second
• Supports Vectored Interrupts
• Supports Array or Linked Array Chaining
• 16-Bit Data Bus
Programmable Priorities

~'-

. -.
•
.
. . . o.

INTR

R68450

lACK

OWN
UAS

HIBYTE
DBEN
DDIR

BEW
BECI
BEC2

DIC
FCD
FCI
FC2

-

..

-

R68450

.

INTERNAL ORGANIZATION

Channel

Chlnne'

Status Reglslef

S,.tusReo'Sler

Ct1annel

EnOl Reglste,
De',IIce

DevlCI

COlllrOI Register

Corl1folA .... ,Sler

Opelal'on
CunHol Reg,sIPI

Conllo'R~ISI.r

Oper.I,on

Sequence

SeQuence

Conirol Register

COnlrolA~lstel

Channel

Channel
Control Reglsler

ConliOlReg'5ter

Channel 0

Normal
InterruptI/ector

Channell

Enor

In,errupt Vector
PrIOf,I" Reg,slI!I

Channel
P"orolyReg,ster

Memorv
FunChon Codes

Memory
Function Codes

Channel

Devoee
Function Codes

B.,.
funChOnCodes

I

Memorv Transler Countt'r

I

I

I

Base Trans1er Co>.:nler

Memory Address Regls,e,
Device Addles!> Reg,ster

ease

Address Reg.ster

Cl'1armel

Base Address Register

Channel
Stal\JsReg,sler

Sl31usReglSlt'r
Channel

EllorReglster

EnorReg,s,e,

Device
ConlfolReglsler

DeVice
ContlOl Register

Operation
CvntrolReg,sler

•
~:.-

Operation
Control Reg,ster

Sequence

SeQuence
Control Reg,sler

ConlfolReg l 5U!f
Channel

Channel
Control Register

Con1fOIReg l sler

. -.

Channel 2

Channel 3
Intell'.JplVector

Channel

Channel
PnorltyReglsler

Pr1 olllvReg,sler
Memory
FurCI.on COdP,5

Memorv
FunCllonCodes
DeVice
Function Codes

Base

Belse
FuncltonCodes

Functloneode!>
Memory Transler Counier

I

J

Memorv TransierCounler

I

I

Base Trans1er Coun\er

Memolv Address Reg.sler

Memory Address Reg'ster

DevIl-I! Address Register

Base Address Reglslel

Rockwell
International

Electronics Devices Division
P.O. Box 3669, RC55; Anaheim, CA 92803
Phone (714) 632-3729

R68561

'1'

Rockwell

R68000 Microcomputer System
PRODUCT PREVIEW

MULTI-PROTOCOL
COMMUNICATIONS CONTROLLER (MPCC)
The R68561 Multi-Protocol Communication Controller
(MPCC) is a serial data communications interface for the
R68000 Family. This device meets the basic interface requirements of asynchronous, bit- and byte-oriented synchronous communication protocols. To keep device count
low, the MPCC also contains an internal crystal oscillator and
baud rate generator.

HMOS
(HIGH DENSITY N-CHANNEL,
SILICON-GATE DEPLETION LOAD)

MULTI-PROTOCOL
COMMUNICATIONS CONTROLLER

• Complete Data Communications Interface
• Line Protocols:
Asynchronous
Bit-Oriented Synchronous (X.25, SDLC, HDLC)
Byte-Oriented Synchronous (BISYNC, DDCMP)

• Interface Compatible with R68450 DMAC
• Self Test Loop Mode
• Single 5-Volt Power Supply
• Full or Half Duplex Operation
• Multiple CRC Character Generation and Error Detection
FUNCTIONAL DIAGRAM

• Internal Baud Rate Generator
• Internal Crystal Oscillator
• Complete Status Reporting Capability

AI·AS

• Buffered Transmit and Receive Registers

00-07

OSA

DCO

• Supports Vectored Interrupts
• R68000 Bus Compatible

TXO

iRa
lACK

AES

cs

UOS

A68561
TXC
RXO
AXC
EXTAL

LOs

XTAL

eLK

BClI(

Vee
GNO

55 -

TOSA
AOSA
OACK

OTC

DONE

PPS-4/1
PMOS /-LCS

when one-chip gets you more ... lt's a

Rockwell PPS·4/1
The common component in
uncommon success PPS-4/1 one-chip microcomputer

41~ Rockwell

~.~ International
... where science gets down to business

•

•

Why a Rockwell One-Chip PPS-411
Microcomputer Gets You More ...
Lower Total System Cost
If you're designing manual-input equipment such as business
machines, games, controllers or telephone terminals, Rockwell
PPS-4/1 one-chip microcor:nputers have high promise of lowering
your total system costs. These four.;bit chips are so powerful they
often fit applications where with ordinary one-chip microcomputers
you'd need eight-bit devices at about twice the cost.
More tban 10 million Rockwell one-chip microcomputers are in use
worldwide. Study the chart at right. You'll quickly see why Rockwell
PPS-4/1 microcomputers are so cost-conscious and so useful.

Highlights of Features
Instruction efficiency: Typically, instructions are executed in one
byte in one cycle and in 10 microseconds - all you need for manmachine interfacing.
Lots of I/O Ports: Including serial ports for easy cascading or
combining with host systems, and some I/O ports will source up to 10
milliamps.
On-Chip Display Drives: Directly drive VF or LED displays.
Battery Level Power: In a phrase, "CMOS power at PMOS prices."
Low Cost Designing: Rockwell fully supports you with applications
engineering, designers' classes and ready-to-go software packages.
And Much More: High immunity to noise; broad operating voltage
tolerances, and high breakdown voltage .

Applications Where Rockwell PPS-411 Microcomputers
Get You More in End-Product Features for Less Cost
MM75

MM78

MM78L

MM78L

MM78LA

APPLIANCE CONTROLS
• General
• Microwave Ovens
• Ranges
• Blenders
AUTOMOTIVE FEATURES CONTROLS

1:i _ __

CASH REGISTERS, STAND-ALONE
COIN CHANGER CONTROL
ENVIRONMENTAL CONTROL
• Intelligent Thermostat
• Heat Pump/Air Conditioner
EQUIPMENT CONTROLLERS
• Dot Matrix Printers
• Motor Controllers
• Keyboard-Display
GAMES
• Hand-Held
• Arcade
GAS PUMPITRAFFIC CONTROLS
INSTRUMENTS, SIMPLE/SMART
LANGUAGE TRANSLATORS
MACHINE TOOUPROCESS CONTROLS
RADIO

i
1:
1
~

..

1
1

• Tuners
• Scanners
SCALES
• Commercial
• Consumer
SECURITY SYSTEMS
SMALL BUSINESS SYSTEMS
• Portable Data Entry
• Desk-Top Calculators
TELEPHONE
• Auto-Dial
• Switching
• Answering Equipment
TIMERS/CLOCKS
TV TUNERS
UNIVERSAL LOGIC MODULE
UTILITY MONITORING EQUIPMENT

,
1

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.,
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!

Rockwell PPS-411 Microcomputers Get You More
Through Low-Cost Design Approaches
Prototype Devices
Rockwell provides a 64-pin DIP Emulation
Device for each PPS-4/1 model. The Emulator
is designed to interface with external PROM
or ROM or RAM, and with peripherals of the
total system. This enables you to test your
system in real time, including software testing
and debugging, and circuit hardware
checking. You can even perform field analysis
of the prototype equipment prior to submitting
your ROM code for production.

XPO-1 Evaluation Module
At the low end of software development operations, Rockwell provides a sophisticated
evaluation module with hexadecimal keyboard. Designated XPO-1, this module can
be used for software development with a
PPS-4/1 Emulator device. It has the advantage of low price - below $500. But developing a full program with it is time-consuming.

SUMMARY OF PPS-411
ONE-CHIP MICROCOMPUTER
MODELS
STANDARD MODELS
MM75

Has CPU, 640 x 8 ROM, 48 x 4 RAM,
internal clock logic and 22 liD lines.
28-pin dual in-line package.

A75XX
(A7699)

MM7B

Has CPU, 2048 x 8 ROM, 128' x 4 RAM,
internal clock logic and 31 liD lines.
42-pin quad in-line package.

A78XX
(A7899)

LOW POWER/LOW VOLTAGE
MODELS
MM76EL

Has CPU, 1024 x 8 ROM, 48 x 4 RAM,
internal clock logic and 31 liD lines.
40-pin dual in-line package.

B86XX
(B8699)

MM7BL

Same internal features as MM78. 40-pin
dual in-line package.

B78XX
(B7899)

M78LA

Has CPU, 2048 x 8 ROM, 128 x 4 RAM,
internal clock logiC and 35 110 lines
(including speaker and display liD).
42-pin quad in-line package.

B90XX
(B9099)

NOTE: PART NUMBERS IN BRACKETS ARE FOR PROTOTYPE DEVICES.

Vf'.

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•

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PPS-411 Personality Subsystem
For fast, complete development of programs
for PPS-4/1 devices, Rockwell has developed
a PPS-4/1 Personality Subsystem for use with
our SYSTEM 65 Development System.
The PPS-4/1 Personality Subsystem serves
as a cross-assembler for all PPS-4/1 devices.
Similarly it enables in-circuit emulation.
Debugging capability of the subsystem is total,
including breakpoints, trace, up load/down
load, register alter, program memory alter and
single stepping. Full prototyping of the endproduct's system and peripherals is also provided. This advanced development system,
including SYSTEM 65, is priced well under
$10,000.

Rockwell Services
Rockwell provides Applications Engineering
assistance for all of its customers, usually at
no cost. Designers' Courses are available.
Rockwell is also ready to discuss designing
your product's microelectronic system with its
own resources. Module manufacturing is also
available.

Rockwell PPS-411 One-Chip Microcomputers Give You More
Because You Can Pick The Right Chip At The Right Price
Features/Models

MM75

MM78

ROM (x 8)

640

2048

1024

2048

2048

RAM (x 4)

48

128

48

128

128

12.5

12.5

10.0

10.0

10.0

22

35

Speed (/-Ls)
Total I/O Lines
Condo Interrupt
Parallel Input

1

MM76EL

MM78L

31

31

31

+ 1*

2

2

2

1*

4

8

8

8

8

Parallel Output

14

Bidirectional Parallel

8

8

8

8

Discrete

9

10

10

10

3

3

3

Serial
Speaker
Programmable Logic Array
(PLA)

Power
*Multiplexed

10
3

16 x 8

16 x 8

32 x 14

Tone Generator Counter
Package (In-Line)

MM78LA

8-bit
28-pin
dual

42-pin
quad

- 15V @ 75 mw (typical)

40-pin
dual

40-pin
dual

42-pin
quad

- 6.5 to -11V @ 15 mw (typical)

PART NUMBER

A75XX
.

-

"l' RO~K~ell .

'"

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;

~

~.

,

~

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•

.

.

••

..

PARALLEL PROCESSING SYSTEM (PPS)
DATA SHEET

PPS-411 One-Chip
Microcomputer Family

MM75
one-chip microcomputer system

""CJ
""CJ

(I)
INTRODUCTION

RIOS/INn
RIOl

The Rockwell MM75 one-chip microcomputer is primarily designed
to fit the lowest cost rl:quirements of equipment designers. But in
addition to cost advantage, it provides system functions not presently available in competitive microPlocessors.

RI02

On a single LSI chip, the MM75 provides a complete 4-bit parallel
microcomputer system - versatile Central Processing Unit (CPU),
Instruction Decode, Program Save Register, Program Memory
(ROM). Data Memory (RAM). Program Counter (P)' Data Address
Register (B). nine input/output discrete drivers/receivers, two
4·bit parallel input/output channels, one 4·bit parallel input
channel, Interrupt and Control logic, and a self-contained Clock
Generator circuit.

RI07
RI06
RI05

RI03

INTO

RI04

PO

01/00

PI4

01/01

PI3

01/02

PI2
Pll

01/03
01/04

VSS

01/05

VOD

01/06

VC

01/07

A

VSS

01/08

PPS-4/1 MM75 Pin Configuration

In addition to stand-alone system applications, the MM75 can be
directly included in other multi-chip systems as a dedicated slave
controller.

Operating Temperature
OOC to +50 0 C (Consumer)
OOC to +70 0 C (Commercial)
Maximum Negative Voltage
-30 Volts (Vacuum Fluorescent Drive)
-15 Volts (Standard)

©Rockwellinternational Corporation 1981
All RIghts Reserved
Printed 10 U.S.A

s:

n

::D

0

n
0

s:""CJ

::D

FEATURES

The MM75 may be ordered with combinations of the following
features (not every combination is available!.

"...at

c:
-t
m

To facilitate system and program development, Rockwell provides
powerful development aids listed under "Features" at right.
The MM75 is a member of the MM76 series of microcomputers,
Consult the MM76 SERIES USER'S MANUAL for detailed hardware and software specifications (Document Number 29410N47).
MM75 device codes may be submitted using the PMOS ROM
CODE ORDER FORMS (Document Number 29000N33),

I

~

e
e
e
e
e
e
e
e
•
e
e
e
e

640 8-bit bytes of program memory (5120 bits)
48 4-bit data words (192 bits)
16 8-bit word decode matrix (128 bits)
Two interrupt request input lines
TTL and CMOS compatible
Arithmetic logic unit and four working registers
22 input/output ports
Large instruction set - over 50 instructions
Multifunction instructions increase throughput
Single power supply operation (-15 volts ±5%)
Low power (75 milliwatts typical, 125 milliwatts max)
28-pin, dual-in-line package
Powerful development aids:
- SYSTEM 65 with built in mini-floppy disks and PPS4/1
Personality subsystem
- XPO-1 Evaluation Microcomputer Module
- Development Circuit (P/N A7699) provides address and/
device data lines so that the Program Memory can be in
e'xternal PROM or RAM for emUlating the MM75
Training Courses are available
International Applications Engineering Support

Specifications subject to
change without notice

Document No, 29000 037
Rev, 4. May 1981

I

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(I)

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•

FUNCTIONAL DESCRIPTION
PROGRAM COUNTER (P) and SA REGISTER
A BUFFER
The Program Counter contains the ROM address of the next program instruction. The address in the P Register is automatically
incremented each cycle time during normal operation to address
the next instruction. In addition, instructions are available to
alter the address in the P Register as necessary to fetch an instruction from any address in program memory.
After PO reset, the program counter contains address Hex 1 CO.
This location must contain a Nap instruction.
The SA Register is a "save" register which saves the incremented
value of current address in the P Register during subroutine
execution. This provides a means of returning from a subroutine
directly to the next instruction after the subroutine call.

The contents of the Accumulator or 4 of the bits from the 16 x 8
Decode Matrix may be output for control, display, or data transfer
functions through the A Buffer. The A Buffer holds the data for
output until new data is received from the Accumulator or the
Decode Matrix, or until the power is turned off.

B BUFFER
The 4-bit B Buffer functions the same as the A Buffer except it
outputs the other 4 bits of the 16 x 8 Decode Matrix. The A and
B Buffers combined provide the full eight outputs for the Decode
Matrix.

PROGRAM MEMORY - READ ONLY MEMORY (ROM)
The ROM provides 640 8·bit words of storage for instructions and
constants required to· operate the microcomputer. Under control
of the Program Counter the ROM will read out the addressed
instruction which is to be decoded and executed.
INSTRUCTION DECODE
The I nstruction Decode logic circuitry interprets the instructions pulled from ROM to provide contro: for data transfers,
arithmetic operations, other processing functions and input/
output operations.
DATA ADDRESS REGISTER (8)
The Data Address Register is 6 bits in length and is made up of
two segments, B Upper (BU) and BLower (BLI. Data locations
in RAM and the discrete input/output ports are addressed by the
4 bits in BL and the 2 bits in BU.

A number of multifunction instructions simultaneously modify
B Upper and cause B Lower to be automatically incremented
or decremented and tested for overflow or underflow.
S REGISTER
The S Register is a 4-bit register which is used as a working register
or an auxiliary storage register to the Accumulator. It can be used
as a temporary storage register executing the XAS instruction.
ACCUMULATOR and ARITHMETIC LOGIC UNIT
(A, ALU, and C)
The primary working register in the MM75 is the Accumulator
(A). It is the Accumulator which ties with the Arithmetic Logic
Unit (ALU) and the Carry flip-flop (C) to perform either binary
or decimal arithmetic. Constants may be loaded into the Accumulator from the read only memory or variable data may be
loaded from, or exchanged with the random access memory
(RAM) under control of the Data Address Register (B). The
Accumulator is also the primary path for 4-bit parallel input
or output data.
CLOCK CONTROL (VC, OSCILLATOR)
The internal Oscillator and Clock circuit generates a four-Phase
dock signal used for all internal logic functions. The A clock
term is also brought out so external logic can be synchronized_
The clock frequency is a nominal 90 kHz ±.40%.
An external clock mask option is available. If this option is
chosen, the A clock becomes the external clock input and VC
must be tied to VDD through the appropriate resistor.
DATA MEMORY (RAM)
The Random Access Memory (RAM) used for data memory contains 48 4·bit words. Data memory can be used to buffer input
or output values, hold intermediate results, or be used as a register
for timers, counters, compar'1tors, etc.

CHANNEL 1 INPUT PORTS (Pll through P14)
The parallel input port Pl1 through PI4 will be loaded into the
Accumulator upon command. The receivers are TTL compatible
and are synchronized (phase 1 time) so that asynchronous input
signals may be used.

CHANNEL A I/O PORTS (RlOl through RI04)
The four parallel input/output ports R 101 thru R 104 provide a
masked input capability and an output from either the 16 x 8
Decode Matrix or directly from the Accumulator.

CHANNEL B I/O PORTS (RI05 through RIDS)
The four parallel input/output ports of Channel B function the
same as the four ports of Channel A. Together, they provide an
8-bit parallel output. RIOa also has the capability to be used
as a conditional interrupt (lNT1).

CONDITIONAL INTERRUPTS (INTO and OPTIONAL INT1)
The conditional interrupts I NTO and R 108 (I NT1 ) may be used to
detect external signals and set internal control flip-flops. The
receivers are TTL compatible and synchronized with INTO sampled at phase 3 and RI08 sampled at phase 1.
The conditional interrupts (edge detect) input lines in the PPS-4/1
family are very useful. The RI08 line can be used in two ways
a, part of the parallel I/O Channel B or as the INTl line. When
used as an interrupt line, RI08 will respond to the INT1H and
DIN1 commands. When used as part of the bidirectional I/O
Channel B, it is controlled with the 18M, OB and the SEG2
instructions.

DISCRETE INPUT/OUTP~T PORTS (01/00 through 01/08)
There are nine discrete input or output lines each of which can be
controlled individually under program control. The receivers are
fully synchronized so that asynchronous input signals may be used.

16 X 8 DECODE MATRIX
The Decode Matrix provides a means of decoding the contents
of the Accumulator to provide an S-bit output suitable for driving
various displays or other external devices. The user may define
any code desired. The Development device for the MM75 has a
BCD to seven segment conversion provided. Accumulator contents of Othru F produce 0 thru 9, A, -, P, d, E and blank respectively. The carry flip-flop controls one independent output line.

PPS-4/1 MM75 INSTRUCTION SET
RAM Addressing Instructions
XAB
Exchange A with BL
LBA
Load BL from A
LB
Load BU=O, BL=lmmediate
EOB
Exclusive OR BU
LB L
Load B Long
INCB
Increment B
DECB
Decrement B

Input/Output Instructions
SOS
Set Output Selected
ROS
Reset Output Selected
SKISL
Skip on Input Selected Low
IBM
Input Channel BANDed with A
OB
Output from A to Channel B
lAM
Input Channel A ANDed with A
OA
Output from A to Channel A
11
Input Channel 1
INT1H
Skip if INTl Input (RIOB) is Low
DIN1
Skip if INT1 Flip·flop is Reset
INTOL
Skip if INTO Input is High
DINa
Skip if INTO Flip·flop is Reset
SEG1
Decoder Matrix to Channel A
SEG2
Decoder Matrix to Channel B

Bit Manipulation Instructions
SB
Set Bit
RB
Reset Bit
SKBF
Skip on Bit False
Register to Register Instructions
XAS
Exchange A and S
LSA
Load S from A

Conditional Transfer Instructions
TC
Transfer on Carry Set
TNC
Transfer on No Carry Set
TLC
Transfer Long on Carry Set
TLNC
Transfer Long on No Carry Set
TBF
Transfer on Bit in Memory False
TBT
Transfer on Bit in Memory True
TLBF
Transfer Long on Bit in Memory False
TLBT
Transfer Long on Bit in Memory True
TE
Transfer on A = Memory
TNE
Transfer on A '" Memory
TLE
Transfer Long on A = Memory
TLNE
Transfer Long on A '" Memory
TIH
Transfer if Input High
TIL
Transfer if Input Low
TLiH
Transfer Long if Input High
rLiL
Transfer Long if Input Low

Register Memory Instructions
L
Load A from Memory
X
Exchange A and Memory
XDSK
Exchange A with Memory. Decrement BL and Skip if
BL Counts to 15
XNSK
Exchange A with Memory. Increment BL and Skip if
BL Counts to a
Arithmetic
A
AC
ACSK
ASK
DC
COM
RC
SC
SKNC
LAI
AISK

Instructions
Add Memory to A
Add Memory with Carry to A
Add Memory with Carry to A and Skip on No Carry·out
Add Memory to A and Skip on no Carry·out
Decimal Correction
Complement A
Reset Carry
Set Carry
Skip on No Carry
Load A with Immediate Field
Ad" Immediate and Skip on No Carry·out

ROM Addressing Instructions
RT
Return from Subroutine
RTSK
Return and Skip
T
Transfer on Page
NOP
No Operation
TL
Transfer Long
TM
Transfer and Mark
TML
Transfer and Mark Long

Logical Comparison Instructions
SKMEA
Skip if Memory Equals A
SKBEI
Skip if BL Equals Immediate Field
SKAEI
Skip if A Equals Immediate Field

9 DISCRETE
INPUTS/OUTPUTS

PII-4

CHANNEll

PPS-4/1 MM75 System Block Diagram

SPECIFICATIONS
I nput Leakage:

OPERATING CHARACTERISTICS

< 10 "a

Supply Voltage:

Open Drain Driver Leakage (R OFF):

VDD = -15 Volts±5%
(Logic "1" = most negative voltage VIL and VOL,)

.e 10

VSS = 0 Volts (Gnd.)
(Logic "0" = most positive voltage VIH and VOH,)

"a at maximum voltage

Operating Ambient Temperature (TA):
0

OOC to 70 C (TA

System Operating Frequencies (Internal Clock):

= 25 0 C unless otherwise

specified,)

Storage Temperature:

90 kHz ±40% with external resistor

0

0

-55 C to 120 C

Max Operating Frequency (External Clock):

ABSOLUTE MAXIMUM VOLTAGE RATINGS
(with respect to VSS)

100 kHz
Device Power Consumption:

Maximum negative voltage on any pin -30 volts (vacuum fluorescent drivel.

75 mw, typical
Input Capacitance;

Maximum negative voltage on any pin -15 volts (standardl.

< 5 pf

Maximum positive voltage on any pin +0.3 volts.

LIMITS (VSS
SYMBOL

INPUT/OUTPUT
Supply Current (Average)
for VDD
Discrete 1/0's

(1)

MIN

5 ma

IDD
VIH

TYP

= 0)
MAX

LIMITS (VSS
MIN

5 ma

a ma

·1.0V

TYP

= +5V)
MAX

4>3·4
+0.8V

DI/O O·DI/O a

VIL

DIIO 0·5

RON

500 ohms

500 ohms

01/06·8

RON

400 ohms

400 ohms

i---

Channel 1 Input

VIH

P11·P14
I/O Channel A

(1)

. RI/01·RI/04

I/O Channel B

·4.2V
·1.5V

(1)

(2)

VIH

-4.2V
250 ohms

VIH

A

VOH

250 ohms

250 ohms

6.0 ma max.

4>3
+o.av

·5.0V

VC
PO

<1>4*

+4.0V
·10.0V

VOL

6.0 ma max.

+0.8V

·4.2V
·1.0V

<1>4*
4>3

+3.5V

'1.5V

VIL
Clock

4>3

+3.5V

RON

3.0 ma max.

+o.av

250 ohms

VIL

I
I

4>1

+3.5V

·1.5V

<1>4*

+0.8V

·4.2V

VIL
RON

R1/05·R1/08
INTO

VIH

+3.5V

·1.5V

VIL

TEST
CONDITIONS
VDD = ·15.75V

a ma

+4.0V
·4.2V

TIMING
(SAMPLE/
GOOD)

-5.0V

CL: = 50 pf (max)
56K ±,5%

VIH

·2.0V

VIL
*State established by <1>2 (minimum impedance during <1>4).
(l)These pins only tested for leakage: < 10 IJa @ -30V.
(2)This pin only tested for leakage: <10 IJa@V
'
DO

+3.0V
·6.0V

Special circuit

-1.0V

PART NUMBER

886XX

PARALLEL PROCESSING SYSTEM (PPS)
DATA SHEET
PPS-411 One-Chip
Microcomputer Family

MM76EL
low-voltage, low power
one-chip microcomputer system

SUMMARY

BP
VC
XTLIN
XTLOUT
VOO
PI2
TE"ST
PI6
PI1
PIS
PI7
PI3
Pia
PI4
PO
INTO
INT1
AIOS
AI06
VSS

The Rockwell MM76EL microcomputer is a complete 4·bit paral·
lei processing system. The MM76EL is a low voltage (6.5 to
11 volt rangel. very low power (15 milliwatts typical) version of
the well known PPS4/1 one-chip microcomputer. The MM76EL
is especially desirable where low-cost battery operation as the pri·
mary or backup power source is required, or where power con·
sumption or heat dissipation is a consideration, or where porta·
bility is required. The MM76EL is distinguished from competi·
tive microprocessors by superior I/O capability, and by other
functional features identified on this page.
On a single LSI chip, the MM76EL provides a complete system
consisting of a versatile Central Processing Unit (CPUI. Instruc·
tion Decode, one Program Save Register, Program Memory (ROM),
Data Memory (RAM), Program Counter (PI. Data Address Regis·
ter (B), 10 I/O discrete Drivers/Receivers, two 4·bit parallel I/O
channels, two 4·bit parallel input channels, a Serial I/O port,
Interrupt and Control logic, and a self·contained four·phase Clock
Generator circuit.
In addition to stand·alone applications, the MM76EL can be
directly included in other multi-chip systems as a dedicated
controller or in other functions. Also, two or more MM76EL
microcomputers can be directly combined to perform parallel
processing. or control operations. I n the design of families of
end·products, a total range of features can be designed so that
increasingly higher levels of performance can be produced by
low·cost wiring changes and chip additions, minimizing design
costs and production inventories.
The MM76EL may be ordered with combinations of the follow·
ing features (not every combination is available!.
Operating Temperature
OOC to +50 0 C
(Consumer)
OOC to +70 0 C
(Commercial)
_40 0 C to +85 0 C /Industrial) .
Maximum Negative Voltage
-30 Volts
(Vacuum Fluorescent Drive)
-11 Volts
(Standard)
Nominal Internal Clock Frequency
100 kHz (±30%) with VC to VDD

ELECTRICAL FEATURES
e Battery Compatible (-6.5 to -11.0 volt operation)
e Low Power - 15 milliwatts nominal @ -8.5 volts
e 4 Clock Modes including external crystal
e Low Impedance Drivers
e

e

01/0 - less than 100 ohm @ 10 ma
RIO - less than 250 ohm @ 6 ma
Mask Programmed Pull·down Resistors on Outputs
Mask Programmed Enhancement FET Pull·downs on Inputs

(ORockwelllnternalional Corporatton 1981
All RIghts Reserved
Printed on U.S.A

A
01/09
olloa
01107
01106
01105
01104
01103
01/02
01/01
01/00
CLOCK
OATAO
DATAl
AI04
AI03
AI02
AI01
Aloa
AI07

MM76EL Pin Configuration

s:
s:--J

en

m

r-

s:

(")

:IJ

o
(")
o

s:

."

c:
~.

FUNCTIONAL FEATURES
e

Standard 40·pin Dual.in·Une /DIP) package

e 1024 8·bit bytes of program memory
e 48 4·bit words (192 bits) of data memory
e Clocked simultaneous serial input/output capability
e Externally controlled serial input/output capability
•
•
•
•
•
•
•
•
•

Two interrupt request input lines
TTL and CMOS compatible
Arithmetic logic unit and four working registers
31 input/output ports
Large instruction set - over 60 instructions
Multifunction instructions increase throughput
Single power supply operation (-8.5 volts -2.5, +2.0 volts)
Low power (15 milliwatts typical)
Powerful development aids:
SYSTEM 65 with built·in mini·floppy disks and PPS4/1
Personality subsystem
XPO·1 Evaluation Microcomputer Module
Development Circuit (P/N B7699) provides address and
data lines so that Program Memory can be in external
PROM tcir emulation purposes
Scheduled and Special Training Courses
I nternational Applications Engineering Support

SpecificatIons subject to

change without notice

Document No. 29000 D49
Rev. 3, February 1981

m

:IJ

en
-<
en
~

m

s:

FUNCTIONAL DESCRIPTION
PROGRAM COUNTER (P) AND SA REGISTER
The Program Counter contains the ROM address of the next
program instruction. The address in the P Register is automatically incremented each cycle time during normal operation to
address the next instruction. I n addition, instructions are available
to alter the address in the P Register as necessary to fetch an
instruction from any address in program memory. After PO
reset, the program counter contains address hex 3CO. This location must contain a NOP instruction.

A BUFFER
The contents of the Accumulator or 4 of the bits from the 16 x S
Decode Matrix may be output for control, display, or data transfer
functions through the A Buffe •. The A Buffer holds the data for
output until new data is received from the Accumulator or the
Decode Matrix, or until the power is turned off.
B BUFFER

The SA Register is a "save" register which saves 'the incremented
value of current address in the P Register during ~ubroutine execution. This provides a means of returning from a subroutine directly
to the next instruction after the subroutine call.

The 4-bit B Buffer functions the same as the A Buffer except it
outputs the other 4 bits of the 16 x S Decode Matrix. The A and
B Buffers combined provide the full eight outputs for the Decode
Matrix.

PROGRAM MEMORY - READ ONLY MEMORY (ROM)

CHANNEL 1 INPUT PORTS (Pll through P14)

The ROM provides 1024 bytes of storage for instructions and constants required to operate the microcomputer. Under control of
the Program Counter the ROM will read out the addressed instruction which is to be d~coded and executed.

The parallel input port Pll through PI4 will be loaded into the
contents of the Accumulator upon command. The receivers are
TTL compatible and are synchronized (phase 1 time) so that
asynchronous input signals may be used.

INSTRUCTION DECODE

CHANNEL 2 INPUT PORTS (PIS through PIS)

The Instruction Decode logic circuitry interprets the instructions
pulled from ROM to provide control for data transfers, arithmetic
operations, other processing functions and input/output operations.

The inverted state of the inputs at parallel input ports PIS thru
PIS will be loaded into the Accumulator upon command. The
receivers are TTL compatible and are synchronized (phase 3 time)
so that asynchronous input signals may be used.

DATA ADDRESS REGISTER (B)

CHANNEL A I/O PORTS (RIOl through R104)

The Data Address Register is 6 bits in length and is made up of
two segments, B Upper (BU) and B Lower (BU. Data locations in
RAM and the discrete input/output ports are addressed by the 4 bits
in BL and the 2 bits in BU.
A number of multifunction instructions simultaneously modify
B Upper and cause B Lower to be automatically incremented or
decremented and tested for overflow or underflow.
ACCUMULATOR AND ARITHMETIC LOGIC UNIT
(A, ALU, and C)

The four parallel input/output ports RIOl thru RI04 provide a
masked input capability and an output from either the 16 x S
Decode Matrix or directly from the accumulator.
CHANNEL B I/O PORTS (RIOS through RIOS)
The four parallel input/output ports of Channel B function the
same as the four ports of Channel A. Together, they provide an
S-bit parallel output.
CONDITIONAL INTERRUPTS (INTO and INTll

The primary working register in the MM76EL is the Accumulator
(A). It is the Accumulator Which ties with the Arithmetic Logic
Unit (ALU) and the Carry flip-flop (C) to perform either binary
or decimal arithmetic. Constants may be loaded into the' Accumulator from the read only memory or variable data may be
loaded from, or exchanged with the random access memory
(RAM) under control of the Data Address Register (Bl. The
Accumulator is also the primary path for 4-bit parallel or serial
input or output data.

The conditional interrupts INTO and INTl may be used to detect
external signals and set internal control flip-flops. The receivers are
TTL compatible and synchronized.
DISCRETE INPUT/OUTPUT PORTS (01/00 through 01/09)
There are ten discrete input or output lines each of which can be
controlled individually under program control. The receivers are
fully synchronized so that asynchronous input signals may be used.
16 x S DECODE MATRIX

DATA MEMORY (RAM)
The Random Access Memory (RAM) used for data memory contains 4S 4-bit words. Data memory can be used to buffer input or
output values, hold intermediate results, or as a register for timers,
counters, comparators, etc.
CLOCK CONTROL (VC, XTLIN, XTLOUT, A, AND BP)
The internal Oscillator and Clock Circuit generates a four-phase
A and BP clock signal used for all internal logic functions. The A
and BP clock terms are also brought out so external logic can be
synchronized. The clock for the MM76EL can be selected to
operate in one of four modes as shown by the table below. These
options are selected by control voltages applied to the VC and
XTLIN pins.

The Decode Matrix provides a means of decoding and contents of
the Accumulator to provide an S-bit output suitable for driving
various displays or other e'xternal devices. The user may define
any code desired. The Development Circuit version of the MM76EL
has a BCD to seven segment conversion provided. Accumulator
contents of 0 thru F produce 0 thru 9, A, -, P, d, E and blank
respectively. The carry flip-flop controls one independent output
line.
S REGISTER - SERIAL INPUT/OUTPUT - SHIFT COUNTER
The S register is a 4-bit serial-in/serial-out, parallel exchange,
register which is used as either an auxiliary storage register or
buffer for the simultaneous serial input/output functions. The
shift rate can be controlled either internally or externally.

Pins
Mode

Vc

XTLIN

INTERNAL

"VC

VSS

EXTERNAL

GRD

CLOCK

CRYSTAL""

GRD

XTAL

SLAVE

V

V

"Can be adjusted to vary

DD

fr~quency

XTLOUT

XTAL

-

DO

- Normally set to V DO

··Suggest Murata part nurnber CSBSOOA4 with 2-120

pF shunt capacitors.

A I/O

BP I/O

Frequency

OUT

OUT

100 kHz ±30%@ S.SV

OUT

OUT

400 - SOO kHz @ B.OV

OUT

OUT

:: BOO kHz @ B.OV

IN

IN

50 kHz - 100 kHz@ B.SV

PPS-4/1 MM76EL INSTRUCTION SET

Input/Output Instructions
SOS
Set Output Selected
ROS
Reset Output Selected
SKISL
Skip on Input Selected Low
IBM
Input Channel BANDed with A
OB
Output from A to Channel B
lAM
Input Channel A ANDed with A
OA
Output from A to Channel A
lOS
Serial Input/Output
11
I nput Channel 1
12C
Input Channel 2 and Complement
INTI H
Skip If INTI Input is Low
DINI
Skip if INT1 Flip-flop is Reset
INTOL
Skip if INTO Input is High
DINO
Skip if INTO Flip-flop is Reset
SEG 1
Decoder Matrix Output to Channel A
SEG2
Decoder Matrix Output to Channel B

RAM Addressing Instructions
XAB
Exchange A with BL
LBA
Load BL from A
LB
Load BU=O. BL=lmmediate
EOB
Exclusive OR BU
LBL
Load B Long
INCB
Increment B
DECB
Decrement B
Bit Manipulation Instructions
SB
Set Bit
RB
Reset Bit
SKBF
Skip on Bit False
Register to Register Instructions
XAS
Exchange A and S
LSA
Load S from A
Register Memory Instructions
L
Load A from Memory
X
Exchange A and Memory
XDSK
Exchange A with Memory_ Decrement BL and Skip if
BL Counts to 15
XNSK
Exchange A with Memory_-Increment BL and Skip if
BL Counts to 0
Arithmetic
A
AC
ACSK
ASK
DC
COM
RC
SC
SKNC
LAI
AISK

Instructions
Add Memory to A
Add Memory with Carry to A
Add Memory with Carry to A and Skip nn No Carry-out
Add Memory to A and Skip if No Carry Overflow
Decimal Correction
Complement A
Reset Carry
Set Carry
Skip on No Carry
Load A with Immediate Field
Add Immediate and Skip on No Carry-out

Logical Comparison Instructions
SKMEA
Skip if Memory Equals A
SKBEI
Skip if BL Equals Immediate Field
SKAEI
Skip if A Equals Immediate Field

Conditional Transfer Instructions
TC
Transfer on Carry Set
TNC
Transfer on No Carry Set
TLC
Transfer Long on Carry Set
TLNC
Transfer Long on No Carry Set
TBF
Transfer on Bit in Memory Falso
TBT
Transfer on Bit in Memory True
TLBF
Transfer Long on Bit in Memory False
TLBT
Transfer .Long on Bit in Memory True
TETransfer on A = Memory
TNE
Transfer on A ~ Memory
TLE
Transfer Long on A = Memory
TLNE
Transfer Long on A # Memory
TIH
Transfer if Input High
TI L
Transfer if Input Low
TLiH
Transfer Long if Input High
TLiL
Transfer Long if Input Low
ROM Addressing Instructions
RT
Return from Subroutine
RTSK
Return and Skip
T
Transfer on Page
NOP
No Operation
TL
Transfer Long
TM
Transfer and Mark
TML
Transfer and Mark Long

IQOIKREJ£

INPuTI/OUTPUTS

.--.,..1----------+- ISERIAL INI
DATAl

SEE ClOCIC OPTION
TA6lfFORPROPER

CONNECTIONS

....- - - - - t - + ~S~~·CLOC.)
I - - - - - - - - - - - - - t t - + ~;~~~ OUT)

vc~---t-----1

PPS411 MM76EL System Block Diagram

SPECI F ICATIONS

I nput Capacitance: < 5 pf
Input Leakage: <10 "a
Open Drain Driver Leakage (A OFF): --::10 "a at -30 Volts
Operating Ambient Temperature (T A):
OOC to +70 0 C (Commercial): MM76EL
OOC to +50 0 C (Consumer): MM76EL-l
-40 0 C to +85 0 C (Industrial): MM76EL-2
Storage Temperature: -55 0 C to 125~C

OPERATING CHARACTERISTICS
Supply Voltage:
Voo = -8.5 Volts, -1.5, +2.0 Volts (MM76EL-l)
VOO = -8.5 Volts, -2.5, +2.0 Volts (MM76EL)
(Logic "1" = most negative voltage VIL and VOL-)
VSS = 0 Vo.lts (Gnd)
(Logic "0" = most positive voltage VIH and VOH.I
System Operating Frequencies:
(1) Internal: 100 kHz Nominal at VOO = -8.5·V
(2) External 800 kHz Crystal: 100 kHz
Device Power Consumption: 15 mw, typical

ABSOLUTE MAXIMUM VOLTAGE RATINGS
(with respect to VSS)
Maximum negative voltage on any pin -30 Volts
Maximum positive voltage on any pin +0.3 Volts

TEST CONDITIONS: VDD - -U.5V, TA = 0-70DC
L'M'TS

,vss· 01

LIMITS IVSS· +5VI'

'NPUT /OUTPUT

IAvet'-oe' for veo
Oiser.lel/O',
.·01/00·9

V'H
V,

1.7SrMI

3m.

3.0m.

6 ... "

1.75",- 3 ..."
ma 6m.
+4.0V

-4.2V

Chennel 2 Input
PIS-PIS

I/OChlinnel A
RIOt·RI04
I/O,=~nn.IB

RIOS-RIOS

V'H
V'L

.J.•

Interna'Clock
SlweClock
4

-'.SV

~,

+3.5V

V'H
V'L

-4.2V

+O.SV

V'H
V'L
RON

+O.SV

2S00hms

V'H
V'L

-4.2V

V'H
V'L
RON

-4.2V

V'H
V'L

-4.2V

,'
1

+3.5V
-4.2V

2SOohms
1/0';h,nnll B

TIMING
ISAMPLE/
GooDI

TV'
3m.

VIH
VI
RON
VIH
VIL

.·01100.9

LIMITS IVSS· +5VI'

TY'
1.751N

+4.0V

-1.0V
.... 2V

"'.BV

-1.5V
+C.BV
+3.5V

-t.2V

"'.BV

.....7V

H

-'.'V

VIH
VIL

·6.0V

VIH
VIL

1/>"
1/>'
"1/>3
1
CL- 50 pftm •••
6~:.to, )(TL

"'.3V

SI.."Ctock

"'.6V
+3.5V

-2.5V

6.0m.mu.

.... V

-O.6V

-1.0V

"
1/>,

+4.7V

.Q.3V

VIH
VIL
RON
VIH
VIL

3
'

-I.OV

..... 2V

"'.BV

500 ohms

.....OV

.3, .4

4"

+2.5V

·5.0V

2.0 m. m ...
V-l'.0VmlX.
Speci.lcircuit

OV

·Stete fttablished by '2 (minimum emJMdence during •• 1.
• ·Sem. es ebovt except (>. minimum et (>2 01 n .. t cycle.

NOTES:
MASK PROGRAMMED PULL-DOWN RESISTORS
ON OUTPUTS
Resistor pull-downs are available as an option on all RIO, CLOCK,
OATAO and 0110 outputs. These pull-downs are connected to
VOO. The following values ±SO% are available: SK, 10K, 2SK,
or Open Circuit. The SK ohm option is not available on the clock
or OAT AO outputs.

PULL-DOWNS ON INPUTS
MOS FET pull-downs are also available as an option on the PI,
INT, and DATAl inputs. The output current is 50 pa ±35 pa
with the input grounded and VDO at -8.S volts.

PART NUMBER

A78XX

PARALLEL PROCESSING SYSTEM (PPS)
DATA SHEET
PPS-411 One-Chip
Microcomputer Family

MM78
one-chip microcomputer system

SUMMARY
The Rockwell MM78 microcomputer is e complete, 4-bit parallel
processing system_ Its lerge instruction set is augmented by powerful multi-function Instructions. 31 I/O ports further identify the
power of this system. Serial I/O capability, which can be clocked
simultaneously or externally controlled, extend their power.
On a single LSI chip, the MM78 provides a complete 4-bit parallel
processing system - Central. Processing Unit (CPU), Program
Memory (ROM), Data Memory (RAM), Program Counter (P),
Instruction Decode, two Program Save registers, Data Address
register (8),·10 I/O discrete drivers/receivers, two 4-bit parallel
I/O channels, two 4-bit parallel input channels, a serial input/
output port, Interrupt and control logic, and a self-contained
four·phase clock generator circuit.
In addition to stand-alone system applications, this microcomputer can be directly Interfaced with other multi-chlp systems es
dedicated slave controllers or for other purposes. Also, two or
more MM78 systems can be directly combined to perform parallel
processing or control operations.

BP
A
CLKIN
EXCLK
VC
VOO
VSS
NC
VSS
PI4
PI8
PI3
PI7
PI8
PI2
PIS
VOO·
PI1
PO
RIOS
RI06

01/09
01/08
01/07
01/08
01/05
01/04
01/03
01/02
01/01
01/00
INT1
INTO
DATAl
DATA 0
CLOCK
RI04
RI03
RI02
RI01
RIOB
RI07

PPS-4/1 MM78 Pin Configuration

FEATURES

()Rockwellinternatoonal CorporatIon 1981
All R,ghts Reserved
Pronted In U.S A

3:
""0

The MM78 may be ordered with combinations of the following
feltures lnot every c.ombinatlon is available).
Operating Temperature
OOC to +50 0 C
(Consumer!
OOC to +70 0 C
(Commercial)
Maximum Negative Voltage
-30 Volts
(Vacuum Fluorescent Drive)
-15 Volts
(Standard)

-

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o

2048 8·bit bytes of program memory and 128 4·bil data words
Clocked simultaneous serial input/output capability
Externally controlled serial input/output capability
Two interrupt request input lines
TTL and CMOS compatible
Arithmetic logic !Jnit and six working registers
Two-level subroutine nesting
31 input/output ports
Easy circuit level testing by user
Large instruction set - ovei' 60 instructions
Multifunction instructions increase throughput
Single power supply operation (-15 volts ±5%)
Low power (75 milliwatts typical, 125 milliwatts max)
Powerful development aids:
SYSTEM 65 with built-in mini·floppy disks and PPS-4/1
Personality subsystem
- XPO-1 Evaluation Microcomputer Module
Development Circuit (PIN A7899) provides address and
data lines so that Program Memory can be in external
PROM or RAM for emulation purposes
- Scheduled and Special Training Courses
International Applications Engineering Support

SpecifiClltionl subject 10
change wilhout notice

Document No. 29000 D01
Rev. e, May 1911

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FUNCTIONAL DESCRIPTION
PROGRAM COUNTER (P), SA REGISTER, AND SB REGISTER
The Program Counter contains the ROM address of the next program instruction. The address in the P Register is automatically
Incremented each cycle time during normal operation to address
the next instruction_ In addition, instructions are available to alter
the address in the P Register as necessary to fetch an instruction
from any address in program memory. After PO reset, the program counter contains address hex 3CO. This location must contain a NOP instruction.
The SA Register is a "save" register which saves the incremented
value of current address in the P Register during subroutine execuo
tion. This provides a means of returning from a subroutine
directly to the next instruction after the subroutine call.
The 5B Register provides a second hardware stack register so that
two levels of subroutines may be nested in the microcomputer.
PROGRAM MEMORY - READ ONLY MEMORY (ROM)
The ROM provides 2048 bytes of storage for instructions and constants required to operate the microcomputer. Under control of
the Program Counter the ROM will,read out the addressed instruction which is to be decoded and executed.

X REGISTER
The X Register is an auxiliary register which may be used as temporary storage for 4 bits of data without reference to data memory. The X Register is also used as a data path to the X Buffer
output register and from receiver inputs.
CHANNEL 1 INPUT PORTS (Pll through P14)
The parallel input port Pl1 through P14 will be added to the contents of the Accumulator upon command. The receivers are TTL
compatible and are synchronized (phase 1 time) so that asynchronous input signals may be used.
CHANNEL 2 INPUT PORTS (PIS through PIS)
The inverted state of the inputs at parallel input ports PI5 thru PI8
will be loaded into the Accumulator upon command. The receivers are TTL compatible and are synchronized (phase 3 timel so
that asynchronous input signals may be used.
CHANNEL A I/O PORTS (RIOl through RI04)
The contents of the Accumulator may be output for control or
data transfer purposes through the A Buffer. The A Buffer
will hold 'the data output until new data is output or power
is turned off.

INSTRUCTION DECODE
The Instruction Decode logic circuitry interprets the instructions
pulled from ROM to provide control for data transfers, arithmetic
operations, other processing functions and input/output operations.

CHANNEL X I/O PORTS (Rl0S through Rl0S)
The four parallel input/output ports of Channel X function as
described in X Buffer and X Register paragraphs.

DATA ADDRESS REGISTER (B)

CONDITIONAL INTERRUPTS (INTO and INT1)

The Data Address Register is 7 bits in length and is made up of
two segments, B Upper (BU) and BLower (BLI. Data locations in
RAM are addressed by all 7 bits and the discrete input/output
ports are addressed by the 4 bits in BL when the value in BU is
between 0 and 3.

The conditional interrupts INTO and INTl may be used to detect
external signals and set internal control flip-flops. The receivers
are TTL compatible and synchronized with INTO sampled at
phase 3 and INTl sampled at phase 1.

A number of multifunction instructions simultaneously modify
B Upper and cause B Lower to be automatically incremented
or decremented and tested for overflow or underflow.
ACCUMULATOR AND ARITHMETIC LOGIC UNIT
(A, ALU, AND C)
The Primary working register in the MM78 is the Accumulator
(AI. It is the Accumulator which ties with the Arithmetic Logic
Unit (ALU) and the Carry flip-flop (C) to perform binary arithmetic. By means of software routines, decimal arithmetic can be
performed. Constants may be loaded into the Accumulator from
the read only memory or variable data may be loaded from, or
exchanged with the random access memory (RAM) under control
of the Data Address Register (B). The Accumulator is also the
primary path for 4-bit parallel or serial input or output data.
A BUFFER
The contents of the Accumulator may be output for control, display, or data transfer functions through. the A Buffer. The A Buffer holds the data for output until new data is received from the
Accumulator or until the power is turned off.
X BUFFER
Tha X Buffer comprises four latches which will output the last
bit pattern loaded until either a new Output X Register command
is executed or power is turned off.

DISCRETE INPUT/OUTPUT PORTS (01/00 through 01/09)
There are ten discrete input or output lines each of which can be
controlled individually under program control. The receivers are
fully synchronized so that asynchronous input signals may be used.
CLOCK CONTROL (VC, CLKIN, EXCLK, AND OSCILLATOR)
The internal Oscillator and Clock circuit generates a four Phase A
and n clock signal used for all Internal logic functions. The A
and B terms are also brought out so external logic can be synch:
ronized. The clock frequency is a nominal 90 kHz ±40%. When
precise timing is required, a reference frequency may be input at
CLKIN.
DATA MEMORY (RAM)
The Random Access Memory (RAM) used for data memory contains 128 4-bit characters. Data memory can be used to buffer
input or output values, hold intermediate results, or be used as
a register for timers, counters, comparators, etc., when the MM78
is used as a universal logic element.
S REGISTER - SERIAL INPUT/OUTPUT - SHIFT COUNTER
The 5 Register is a 4-bit serial-in/serial·out, parallel exchange,
register which is used as either an auxiliary storage register or
buffer for the simultaneous serial input/output functions. The
shift rate
be contrQlled either internally or externally.

can

PPS-4/1 MM78 INSTRUCTION SET
Logical Comparison Instructions
SKMEA
Skip If Memory Equals A
SKBEI
Skip If BL Equals Immediate Field
SKAEI
Skip If A Equals Immediate Field
TAB
Table Look Up
Input/Output I nltructions
SOS
Set Output Selected
ROS
Reset Output Selacted
SK ISL
Skip on Input Selected Low
IX
Input X from RIO 5-8
OX
Output X to RIO 5-8
lOA
Input A Receivers to A and output A to RIO 1-4
105
Serial Input/Output
11SK
Input Channel 1, Add to A. Skip If No Carry
12C
Input Channel 2 and Complement
INn L
Skip If INT1 Input Is Low
INTOH
Skip If INTO Input Is High
Conditional Transfer Instructions
TC
Transfer on Carry Set
TNC
Transfer on No Carry Set
TLC
Transfer Long on Carry Set
TLNC
Transfer Long on No Carry Set
T8F
Transfer on Bit In Memory False
TBT
Transfer on Bit In Memory True
TLBF
Tranlfer Long on Bit in Memory Fals.
TLBT
Transfer Long on Bit in Memory True
TE
Tranlfer on A ~ Memory
TNE
Transfer on A J' Memory
TLE
Transfer Long on A - Memory
TLNE
Transfer Long on A,. Memory
TIH
Transfer if Input High
TIL
Transfer If Input Low
TLiH
Transfer Long If Input High
TLIL
Transfer Long if Input Low
Register Memory Instructions
L
Load A from Memory
X
Exchange A and Memory
XDSK
Exchange A with Memory_ Decrement BL and Skip if
BL Counts to 15
XNSK
Exchange A with Memory_ Increment BL and Skip if
BL Counts to 0

RAM Addressing Instructions
XAB
Exchange A with BL
LBA
Load BL from A
LB
Load BL. BU ~ 0
EOB
Exclusive OR BU
LBL
Load B Long
INCB
Increment B
DECB
Decrement B
SAG
Special Address Generation
Bit Manipulation Instructions
SB
Set Bit
RB
Reset Bit
SKBF
Skip on Bit False
Register to Register Instructions
LXA
Load X from A
XAS
Exchange A and S
XAX
Exchange A and X
Arithmetic Instructions
A
Add Memory to A
AC
Add Memory with Carry to A
ACSK
Add Memory with Carry to A and Skip on Carry-out
DC
Decimal Correction
COM
Complement A
RC
Reset Carry
SC
Set Carry
SKNC
Skip on No Carry
LAI
Load A with Immediate Field
AISK
Add Immediate and Skip on No Carry-out
ROM Addressing Instructions
RT
Return from Subroutine
RTSK
Return and Skip
T
Transfer on Page
NOP
No Operation
TL
Transfer Long
TLB
Transfer Long Banked
TM
Transfer and Mark
TML
Transfer and Mark Long
TMLB
Transfer and Mark Long Banked

10 DISCRETE
INPUTS/OUTPUTS

Vss
O.OI..,f
VDO

,---,..1------_____+_

SE~::L

1+------;-... i~~K

~---------~~ S~~L

OPTIONAL

PRECISION
OSCILLATOR

EX
CLK

TEST

Pl5-8

CHANNEL 2

PPS-4/1 MM78 System Block Diagram

SPECIFICATIONS
OPERATING CHARACTERISTICS
Supply Voltage
VDD = -15 Volts±5%
(Logic "1" .. most negative voltage VIL and VOL,)
VSS = 0 Volts (Gnd)
(Logic "0" = most positive voltage VIH and VOH,)
System Operating Frequencies:
90 kHz ±40% with external resistor
Device Power Consumption:
75 mw, typical
Input Capacitance:
<5pf
Input Leakage:
<10 Ila

Open Drain Driver Leakage (R OFF):
<10 Ila at -30 Volts
Operating Ambient Temperature (TA):
OoC to 70 0 C (Commercial!
OoC to 50 0 C (Consumer)
Storage Temperature:
-55 0 C to 1200 C
ABSOLUTE MAXIMUM VOLTAGE RATINGS
(with respect to VSS)
Maximum negative voltage on any. pin -30 Volts
Maximum positive voltage on any pin +0.3 Volt

TEST CONDITIONS: VDD:" -15V ±5%, T A ·0·70o C
LIMITS (VSS - 01

FUNCTION

SYMBOL

LIMITS (VSS - +sVI

1---------+---------\
MIN

TYP

MAX

MIN

TYP

MAX

Discrattll/O',

TIMING
(SAMPlEI
GOOOI

TEST
CONOITIONS

...

+3.5V
+O.BV
Channel 2 Input

.'

PI5-PI8

+O.8V

...
..•..•...
.3

Notlync.

+o.SV

Ftl/0!5-AI/08

Mu.t~

Itabl •••

• ' and 2 .

DATA 0
+3.5V

+O.8V

.'

Cl-SOp

ma•.

·1Q.OV

A, BP. CS)

..

'

2.U

mo mo •.

56K .t.5"
S~cj.lcjrcuit

.2'uo,

• Stat•• It.bli.h~ by .2 (minimum Impedance during .4).

··Sam. as above .xcapt •• minimum at

• ··CO"nKt VC to VOO through a 661«(1 r ..

of na.t cyc'.,
for GO kHz.

DOCUMENT NO. 29410 N21
NOVEMBER 1977

~~tl~" Rockwell
~J .. ~,.: ~':_.

. .'~ , ;: '~-

PARALLEL PROCESSING SYSTEM (PPS)

APPLICATION NOTE

.~ ;:'

SERIAL COMMUNICATIONS PROTOCOL
FOR MULTIPLE PPS-4/1 SYSTEMS
A simple communications protocol can be implemented between two PPS-4/1 microprocessors using only five interface lines. In order to
prevent both units from attempting to transmit simultaneously, one processor must be designated as the Moster and the other as the Slave. The
Moster initiates all communication. The Slave responds to commands and inquiries from the Moster.

COMMUNICATIONS BUS
The Communications Bus consists of the Serial Channel lines - Serial Data Out (DATAO), Serial Data In (DATAl) and CLOCK - and twa bidirectional handshake lines (01/0). One of the handshake lines will be used to transmit the Data Ready control signal (DR), the other will be
used to transmit the Xmit Acknowledge control signal (XA). The connection of these lines is shown in the Serial Communication Block Diagram.
The normal (inactive) state of the handshake lines is low (driver off), which results in a "wired-OR" arrangement that allows either processor to
IIraise li the line by turning on its output driver.

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COMMUNICATIONS PHASES

c:

Communications are nonmally conducted in two phases. During the Command Transmission Phose, the Moster transmits a command or inquiry to
the Slave. During the Data Transmission Phose, the Slave responds by transmitting one or more data words. The general sequence of events
for each phase is described tn the text to follow, and illustrated by the accompanying timing diagram.

o

Command Trlnsmillion Phase

o
z

The sequence is:
I.

voo

Both handshake lines are low, indicating a "clear to send" condition.

2. Moster transmits the command code to Slave via the Serial Channel.
Eight cycles are needed to transmit four bits.

MASTER

10K

01/0

3. Moster raises DR.
4.

- D A T A REAOY-

SLAVE

01/0

OATAO

COMMANOS---

7. Slave decodes command and perfonms required function.
Data Transmission Phase

I.

2.

SERIAL
CLOCK

B?th handshake lines are low, indicating a "clear to send" condition.
Slave trans"lits data to Moster via the Serial Chonnel.
are needed to transmit four bits.

_SHIFlCLOCK_

Slave raises DR.
Moster senses DR high, saves data in RAM buffer and raises XA.

DATAl

-DATA

~

OATAO

Slave senses XA low, and steps 2 through 6 are repeated for the
required number of data words, including a four-bit checksum value.
In the event of a checksum error, Moster will transmit a new command
and the entire process will be repeated.

01/0

_ _ ACKNOWLEDGEMENT __

"'0
"'0

~

01/0

PPS-4/1 SERIAL COMMUNICATION BLOCK DIAGRAM

+--_

_-l...ITTJl....l..-..L.....JL.......L_ _ _ _ _ _-+_--'CITDL.......L-L...-'-"--_ _ _ _ _ _

'-v--'

DATA
READY - - - - - . . . . . . .

ALL UNO LOW .. CU .... 1Q

S{NO~

_

J

____

I
--.J .

}_______

-.l

I

:~~~~~~t~!~~:I~~~~N[ }- - - - - - - - ...J

~~~;-:g:~~!~~~E5A~~ HIGH

) __ - - - - - - - ~

~ER~~~~~~t~~;~~~~~D~~~INt

}-

~l~~~NOLOWAGAJN ..'CLEARTO)-

-

-

-

-

-

-

-

-

-

___________

-.J

SERIAL DATA HANDSHAKE TIMING DIAGRAM
~-~----.-----.--.--------~-,---~----,,,,

<9 Rockwell International Corporltion 1977
All Rights Reserved
Printed in U.S.A.

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TRAN~ITTEISlN05SUIALD"TA
~~~~5MITTEI:RAIS{S OAIA READY

"....
en
3:

I

I

XMIT
ACK. _ _ _ _ _ _----J

rm

en

10K

6. Moster senses DR low, and drops XA.

3:

c:

"'0

VOO

5. Slave senses XA high, and drops DR.

S~:I;;;

:a
SERIAL
CLOCK

10K

3.

or."

VOO

Eight cycles

o~

o

10K

4.

7.

DATAl

VOO

The sequence is:

en
:a
"'0

o

5. Moster .enses XA high, and drops DR.

6. Slave senses DR low, and drops XA.

~

o

Voo

Slave senses DR high, saves command in RAM buffer and raises XA.

z

Rockwell Microelectronic Devices
P. O. Bo)("3669
Anaheim, Calif. 92803

DOCUMENT NO. 29410 N24
JULY 1979

PARALLEL PROCESSING SYSTEM (PPS)

APPLICATION NOTE
Using PPS-4/1 to Operate a Liquid Crystal Display
PURPOSE

internal oscillator is used to generate the AC frequency

This application note illustrates the use of a PPS-4/1

for the LCD wave forms.

one-chip microcomputer to operate a liquid crysta'i
display that is driven by a Hughes HLCD 0438 device.
Although an MM78L is used as the microcomputer in
the example interface, the material in this note can
be easily adapted to the MM77, MM77L or MM78.

Here is how the display is updated: New segment data
are stored in the MM78L RAM.

The dota ore then

transferred to the HLCD shift register through the
MM78L serial output port.

Finally, the HLCD load

line is pulsed by 0106 to transfer the data to the
HLCD latches and implement the new display pottern.

DESCRIPTION

Figures 2 and 3 show the flowchart and the PPS-4/1
Segment data from the display are loaded into the

coding for this procedure.

driver from the MM78L serial output port, as shown
in Figure I.

Because the PPS-4/1 is a PMOS circuit

and the HLCD is a CMOS circuit, VSS of the MM78L
and VOO of the HLCD are connected to ground, and
VDD of the MM78L and the ground pin of the HLCD
are connected to -8.SV.

For this example, DI06 of

the MM78L drives the HLCD load line and the HLCD

DATA IN
LCD
CLOCK
SEGMENTS BACKPLANE

LOAD
SEG1·32

32

BP

MM78L

L-.._ _

HLCD 043

~

Figure I.

o

_ _" "_ _ _

.8.5V

INTERFACE BLOCK DIAGRAM

Rodlwellinternational Corporation 1979
All RIghts Reserved
Printed In U.S.A.

Figure 2.

DRIVER FLOWCHART

Specifications subject to
change without notice

BL=
BU =

~O~~~~2~~3~~4~~5~__6~__1~

21__--'--__'____'__~--'----'--I__,_DP--,L
_I YI
SEGMENT DATA REGISTER
LLiNE
DPLY

EDU

6

E~U

#21

DISP
DISP1

LBL
L
XAS

i

DPLY

lOS
NOP
NOP
NOP
NOP
NOP
DECR
T
LR
SOS
NOP
ROS

POINT TO SEGMENT DATA REGISTER
FETCH DATA
TRANSFER TO SERIAL REGISTER
OUTPUT
WAIT FOR SHIFT OUT
COMPLETE

DISP1
LLINE

REPEAT FOR REMAINDER OF DATA

··
·

Figure 3. DISPLAY DRIVER

INTEGRAL
MODEMS

PART NUMBER

R24

MODEM PRODUCTS
DATA SHEET
R24 2400 BPS INTEGRAL MODEM
INTRODUCTION

FEATURES/BEN EFITS

The Rockwell R24 is a high performance synchronous serial 2400 bps
DPSK modem. Utilizing .extensive MOSILSI technology, the R24 is
implemented in three modular building blocks. It is innovatively de·
signed to enable its economic integration by system designers in a
broad range of communication, computer, and control equipment.

•
•
•
•
•
•
•

Having Bell 20t B/C and CCIIT V.26 compatibility, the modular R24
ofrers the user sufficient flexibility to customize a 2400 bps modem
to his specific packaging and functional requirements. With a mini·
mum amount of interface circuitry, the modem can be configured for
operation on leased lines or on the general switched network.

MODULE VERSATILITY
The versatility of the R24 design is achieved by dividing the modem's
functions into three mOdules:
Transmitter - Module T
Receiver - Modules RI, R2

•
•
•
•
•
•
•
•
•
•

LSI high density; low power
2400/1200 bps modes
Transmitter·Differential phase modulation
Receiver·Coherent phase detection
Bell 201 B/C, CCIIT V.26 compatible
CCIIT AlB encoding options
Operating modes:
Half duplex (2 wire)
Full duplex (4 wire)
Simplex (Transmit or Receive only)
Outstanding performance over unconditioned lines
LSITUCMOS compatible digital interface
Fixed compromise equalizer
V.27 compatible scramblerldescrambler
Answer·back tone generation
Clear·to·send delay options
New sync option provides rapid resynchronization
Typical power consumption 2 watts
Total module area 25 sq. in.
R24 Modem Evaluation Board facilitates evaluation and
design·in tasks.

RI and R2 modules are used to implement
a complete receiver function.

Half Duplex (2·Wirel:

Requires both transmit and receive func·
tions (although not simultaneouslYI,
therefore. all three modules are used.

Full Duplex (4·Wirel:

Requires both transmit and receive func·
tions simultaneously. again all three
modules are used.

C>Rockwelllnternatlonal Corporation 1981
All R'ghts Reserved
Printed In USA

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In general, the modules can be configured to operate in the following
modes:

Simplex - Receive only:

N

::D

MODEM OPERATION MODES

Only the transmitter module (T) is used.

~

Ci)

Each module can be plugged into standard connectors or can be
wave soldered on one or more printed circuit boards. The pin
spacing is on 100 mil centers. Modem modules are functionally
independent.

Simplex - Transmit only:

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N

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s:

I
Specifications subject to
change without notice

Document No. MD01
Rev. 2. March 1981

•

INTERCONNECT

~---------------O

INTERCONNECT

--------------O-~------------------__,

RECEIVER

1(;:=~>lCONTROl

~==I~DATA

t

~----------------~
MODULE R24·T

I·ANALOCI4---4"-----.

DATA

I CONTROL'

TRANSMITTER

INTERCONNECT

CONTROL

R24 Functional Diagram

TECHNICAL DESCRIPTION
Transmitter carrier frequency ......................... 1BOO Hz ± 0.01 %

DIBIT

Echo suppression and answer lone frequencies - 2100 Hz ± 0.01 % or 2025
Hz ±0.01%

00
01
11
10

Received signal frequency tolerance - The receiver can adapt to received
frequency errors up to ± 10 Hz with less than a 0.5 dB degradation in bit
error rate.

2400 BPS
PHASE CHANGE
V.26A
V.26B/Be1l201

0°

+90°

I
I
{\ f'V {\ r\

ALTERNATIVE A

+270°

f\

vvv\J

Data signaling and modulation rate: .

ALTERNATIVE B
1) Normal: Signaling Rate - 1200 baud ± 0.01 %.
Data Rate - 2400 bps ± 0.01 %
2) Fallback: Signaling Rate -12oobaud ± 0,01%.
DataRate-12oobps ±0.01%.

+45 0
+135 0
+225°
+315°

0°
+90°
+180°
+270°

+45°

+135°

1

+180°

1

f\
f\
\f\J \N V
+225°

+315°

f\df\Af\lf\hf\
v UVV WVV
LIne Signal Diagram (V.26 A & B)

Transmitted Data Spectrum - The transmitted spectrum's bandwidth
extends from BOO Hz to 2Boo Hz. Phase distortion characteristics are within
the limits specified in CCITT Recommendation V.26 bis. The out of band
signal power limitations meet those specified by Part 6B or Tariff 261 of
the FCC's regulations, and typically exceed the requirements of inter·
national regulatory bodies as well.

Data Encoding (DPSK) - At 2400 bps, differential four·phase modulation
Is used. The data stream Is transmitted in pairs of consecutive bits (dibits).
Each dibit Is encoded as a phase change relative to the phase of the preced·
Ing signal element.
The R24 implements the phase A and B recommendations of CCITT V.26.
The modulation coding In Bell 201 modems is the same as V.26B. Definition
of these coding arrangements Is shown in the following table:

At 1200 bps, differential two·phase modulation is used. Each bit is trans·
mitted at a relative phase change to preceding signal element in accord·
ance with CCITT V.26 bis.
1200 BPS
BIT

PHASE CHANGE

0
1

+90°
+270°

Turn On Sequences - A total of twelve selectable turn on sequences can
be generated by the transmitter module.
Turn Off Sequence - When the transmitter has. been sending data and
"Request to Send" is turned off, any remaining data bit Information is trans:
mitted withiri 6 milliseconds.

Ready for Sending (Tl06) Response Times - These resp'onse times are
determined by the modem configuration selected and lis associated turn
on sequence.
Tum On
Sequence
Number

Ready for Sending
Response
Time

Configuration and
Carrier Type

1

6.67 msec

Switched Carrier - 4·Wire
(Bell 200

2

8.33 msec

Switched Carrier - 4·Wire

3

30 msec

CCITT - 4·Wire

4

30 msec

CCITT - 4·Wire with Scrambler

5

90 msec

CCITT - 2·Wire

6

90 msec

CCITT - 2·Wire with Scrambler

7

148.3 msec

Switched Carrier - 2·Wire

8

148.3 msec

Switched Carrier - 2-Wire with
Scrambler

9

220 msec

CCITT - 2·Wire Echo Protection

10

220 msec

Switched 2·Wire Echo Protection
with Scrambler

11

800 msec

CCITT - 2-Wire Auto Call

12

800 msec

CCITT - 2·Wire Auto Call with
Scrambler

Response Time tolerance (+ 0.9, ·0.1) msec
ScramblerlDescrambler - As a selectable option, the scrambler/de·
scrambler may be inserted into the transmitter/receiver path. The purpose
of this scrambler is to ensure that the line signal will evenly span the alia·
cated bandwidth. This minimizes pattern sensitivity problems arising from
simple fixed and periodic data sequences. The scrambler is V.27 or V.27
bisller compatible.
Carrier Detect (Tl09) - The modem receiver incorporates a line signal
energy detector whose output responds to three selectable thresh hold
levels.

Set 1 (V.26 bis, switched network) - Greater than ·43 dBm
Less than ·48 dBm

= ON
= OFF

Set 2 (V.26 bis, switched network) - Greater than ·33 dBm = ON
Less than ·38 dBm
= OFF
Set3 (V.26, leased line)

- Greaterthan·26dBm = ON
Less than ·31 dBm
= OFF

NOTE: A minimum hysteresis of 2db exists between the actualturn·on
and turn·off transition levels for each threshhold sel.
Selectable Tl09 Response Times - This time is defined as the interval be·
tween the sudden connection or removal of the received line signal to the
modems receive filter, and the subsequent transition of Carrier Detect
(Tl09) from one state to the other.
Carrier Detect
Tra.nsltlon

Response Time

OFF to ON
(connection)

6±1 ms}
14 ± 1 ms Selectable

ON to OFF
(removal)

8±3 ms}
22 ±3 ms Selectable

Receive Level- The modem receives line signals from 0 to ·43 dBm.

Transmit Timing - The modem generates a Transmll Clock (T114) having
the following characteristics: Frequency - 2400 Hz %.01% (1200 Hz
%.01% In fallback mode), duty cycle - 50 % 1%. The modem Is also optionally capable of tracking an External Transmit Clock (T113) supplied by
the modem user. Tl13 has similar characteristics to Tl14.

Receive Timing (T115)·- The modem provides a data derived "Receive
Clock" output In the form of a nominal squarewave (50 %1% duty cycle).
The modem timing recovery function Is capable of tracking a %0.01 % frequency error in the associated transmlltimlng source.

Transmitter Output Levels - This output can be strap conlrolled in 2 %0.2
dB steps from-l dBm % 1 dB to·15 dBm % ldB.

Answer Tone Generation tone of 2100 Hz %0.01%
CCITI Recommendations
Bell System requirements
disabling tone.

The modem generates a selectable answering
or 2025 Hz %0.01%. The 2100 Hz tone meets
G.161 and V.25, and the 2025 Hz tone meets
for both answering tone and echo suppressor

Equalizer - As a strap option, the modem contains a fixed compromise
delay equalizer which can be used to improve performance over unconditioned schedule 3002 lines. This option is normally pOSitioned in the reo
ceiver, but it can be repositioned in the transmitter or bypassed entirely.
II is designed to compensate for the mean of the range of group delay dis·
tortions generally encountered in the United States. lis amplitude response
is nominally flat at 0.0 dB.

Test Pattern Generation-The scrambler/descrambler funclion can be used
to implement a 127·bit test pattern feature. For example, a constant mark
input could be scrambled and transmitted as a pseudo·random signal to be
descrambled at the receiver back to the constant mark. A transmission error
would be represented as a space for the duration of an incorrect bit.

Mullipoll Synchronization - The "new sync" (NSYNC) digital input can be
pulsed to cause rapid resynchronization of the receiver for sequences of
incoming messages. This feature is necessary in some polling applications.
However, if the user's hardware/software does not support the use of "new
sync" (NSYNC), then the optional "fast sync" (FSYNC) can be utilized to
enable a fast resynchronization procedure.
Selectable Clamping Options1)

Received Data (Tl04) - This output is clamped to a selectable constant
(space or mark) when "Carrier Detect" is off, to prevent disturbances
on the line from gelling through the receiver to the dataoutpul.

2)

Carrier Detect (Tl09) Clamp - This output may be clamped OFF
(squelched) in 2·wire applications during the time when "Request to
Send" (Tl05) is on. An additional option extends this clamp for 148
msec beyond Tl05transilioning off, providing echo protection.

3)

Receive Clock (T115) - This clock output can be clamped OFF when
"Carrier Detect" is off, thereby preventing any disturbances from pro·
pagating through the receiver to the receive clock output.
-

I

SYSTEM DESIGN

MODEM OPERATION -

The R24 modem modules provide the user with sufficient flexibility to
implement a wide range of modem functional configurations. This flexi·
bility is achieved by digital control at the module interfaces. For a given
application, such as a lease network V.26 Alternative B modem (Bell 201 B),
the complexity of the user interface can be significantly reduced by
strapping those data interface inputs which do not change. The modem
interface can also be under software control.

Figure 3 indicates the module interconnections necessary for half·duplex
operation. For full·duplex operation, the transmitter/receiver Interconnec'
tions are similar to the half·duplex case with the exception that "REC IN"
is not connected to T2 or n. In full·duplex operations, the transmission
and receiver paths are independent.

Figures 1 and 2 show the basic interface connections for the transmitter
module (T) and the receiver modules (R1,R2). These diagrams are ap~licable
for any operation mode of the modem·simplex, half·duplex, or fuil·duplex.

HALF OR FULL·DUPLEX

As shown in the diagram, a transformer Is sufficient to connect directly
to a leased line In the U.S. For the switched network, registered protective
circuitry or a data access arrangement (DAA) Is generally required. Rockwell
offers an FCC registered protective circuitry product to support this appli·
cation. Requirements for line Interface and protective circuitry vary inier·
nationally.

COMMON MODEM DIGITAL
CONTROLS
V26A
I
SaGR
NSYNC
CLAMP

TO LEASED
L1NEOR
TO SWITCHED
NETWORK
PROTECTIVE
CIRCUITRY

DIAGNOSTICS
RECEIVER
CONTROL

)11

CAUTO
TONA
TBC

Z
T2Wf4W
X

INTERCHANGE
TIN
-ldBm
-3dBm
-5dBm
-7dBm
-9dBm
-lldBm
-13dBm
- l5dBm

TRANSMITIER
CONTROL

K
Y
TC06
BOOMS

Tl03

Tl05
TlOS

DATA (Tl03)

E

Tlll
Tl13
Tl14

TRANSMITIER·RECEIVER INTERCONNECTION
(HALF DUPLEX)

Figure 3
Secondary Channel - The modem modules provide the user with all the
interface connections needed to add an external secondary channel If reo
quired. This data transmission channel would operate at a lower rate, and in
a different portion of the available bandwidth than the primary. Additional
external receive filtering would also have to be added to allow Simultaneous
operation of the primary and secondary channels.

TRANSMITIER INTERFACES

Figure 1

Analog and Digital Loopback - To check out or diagnose the communlca·
tion link, loopback testing is often performed. A test word is transmitted
and "looped" back to the originati ng DTE. Typical types of loop back tests
are:

DIGITAL

> INTERCHANGE
RECEIVER
DIGITAL
CONTROLS
R2Wf4W
TH09
PBS
CP04
CP15
FSYC

I

f

I

Tl04

CD
®

LOCAL DIGITAL

0

REMOTE ANALOG

LOCAL ANALOG

@

REMOTE DIGITAL

i~~~
V26A
I
SaGR
NSYNC
CLAMP

...

COMMUNICATION
CHANNEL

DTE • Data Terminal Equipment

RECEIVER INTERCONNECTION

Figure 2

The modem modules provide the user with all the necessary interface
connections to implement almost any loopback scheme desired. With a
minimum amount of external circuitry, loopback testing can be controlled via Ii
communications adapter/software approach or manually. For local analog,
remote analog and remote digital loopback, the V.27 scrambler within the
modem can be used to generate a 127-bit word.

INTERFACE DESCRIPTION
TRANSMITTER ANALOG CONTROLS

STANDARD DIGITAL INTERCHANGE
Term
(CCITTV.24 EIA RS232C Module Interface
Output
Equivalent) Equivalent Input
n03
BA
T·9
n04
BB
R2·5
CA
Tl05
T·8
Tl06
CB
T·6

Description
Transmitted Data
Received Data
Request to Send
Ready for Sending
(Clear to Send)
Data Channel Received Line
Signal Detector (Carrier Detect)

Tl09

CF

Rl·4

Tlll

CH

T·12.
R2·9

n13

DA

T·7

n14

DB

T·l0

Transmit Clock (Transmittec;l
Signal Element Timing)

n15

DO

R2·6

Receive Clock (Receive Signal
Element Timing)

R2·22

Data Signalling Rate Selector
Selects 2400 bps or 1200 bps
Mode
External Transmit Clock
(Transmitted Signal Element
Timing)

Term

Module Interface
Input
Output
T·22

DACOUT
TFIL

T·23

TIN
-ldBm
-3dBm
-5dBm
-7dBm
-9dBm
-lldBm
-13dBm
-15dBm

T·31

T·39
T·38
T·37
T·36
T·35
T·34
T·33
T·32

Description
Output of Digital to Analog Converter
Input to Low Pass Filter. DAC OUT is
Normally Connected to TFIL Unless
Additional Filtering or an Equalizer is to be
Inserted.
These Nine Signals Implement the
Transmitter Output Level Attenuator. One of
the Signals -ldBm •...• - 15dBm is
Strapped to TIN to Set the Desired Output
Level.

RECEIVER DIGITAL CONTROLS
Term
ANALOG LINE INTERFACES
Module Interlace
Input
Output
Rl·12

Term
RECIN

n

T·l
T·2

T2

Description
Analog Line Signal Input (Receive Filter
Input)
Low Impedance Transmitter Output
Standard Transmitter Output 600 ohms
Impedance

COMMON MODEM DIGITAL CONTROLS
Term

Modulelnl8rface
Input
Output

V26A

T·16
R2·13.

S8GR
NSYNC
CLAMP

~

T.15}
R2·12
T·17
R2·14
T·14
R2·11
R2·10

Module Interface
Input
Output

Description

RBCK
RLSD
THRH
R2W/4W
TH09

Rl·l

R2·25

Receiver Baud Clock

R2·24
Rl·3
R2·8
R2·18

Rl·2 } Control Signals to Generate Carrier Detect
R2·23 (Tl09) and Implement n09 Threshold Set
Select Function

TC09

R2·15

PBS

R2·16

Determines Carrier Detect (Tl09) Off·to·On
Response
Determines Carrier Detect (Tl09) On·to·Off
Response

CP04

R2·17

Clamps Received Data (n04) to a mark
or space when Carrier Detect(Tl09) is Off

CP15

R2·19

Optional Clamping of Received Clock (Tl15)

FSYC

R2·20

Fast Sync Optional Fast Resynchronization
Procedure

Tlrm

Module Interface
Input
Output

DeSCription
Selects V.26A orV.26B Dibit Encoding
RECEIVER DIGITAL DIAGNOSTICS
Controls for Scramble Operation

T·13

Controls Tl09 to Force Rapid
Resynchronlzatlon of the Receiver
Implements Squelch for Carrier Detect
(Tl09)

SYC
RCVDS
DCP
A
PE

R2·1
R2·2
R2·4
R2·3

DeSCription
Digital Outputs which Enable User to
Generate Eye Pattern and Phase Error
Information

RU

TRANSMITTER DIGITAL CONTROLS
Term
CAUTO
TONA

Moduleinterfaci
Input
Output
T·3
T·5

TBC

T·4

Description
Initiates AnswerTone
Indicates Completion of Transmission
of AnswerTone
Transmitter Baud Clock

Z

T·28

Input Forcing Transmit Clock (Tl14) to
Phase and Frequency Lock to External
Transmit Clock (n13)

T2W/4W
X
K
Y
TC06
800MS
E

T·ll
T·24
T·25
T·26
T·27
T·29
T·30

Inputs Affecting Ready for Sending
Response Times. AnswerTone Frequency
and Carrier Detect (n09) Squelch

RECEIVER ANALOG CONTROLS
Term

Module Interllce
Input
Output

REC OUT
EQ IN
EQOUT

Rl·7
Rl·8
Rl·6

RLSD IN
AGC IN
AGCOUT

Rl·5
R2·21

GAIN
Gl
G2

Rl·ll
Rl·9

lANA LOG

R2·27

R2·26

Description
Receive Filter Ouput
Equalizer Input
Equalizer Output
Carrier Detect Circuitry Input
Automatic Gain Control Circuitry Input
Automatic Gain Control Circuitry Output

Rl.l0} Optional Carrier Detect (Tl09) Threshold
Selection Controls
Sample and Hold Circuitry Input

•

MODEM PERFORMANCE
DISPERSION
DUETOGAIN
ERRORS

The R24 Is a high performance synchronous 2400 bps DPSK modem,
utilizing a coherent demodulation technique to achieve reliable operation
over the switched network or unconditioned lines. This section contains
a quantitative discussion of the R24's typical performance under varying
test conditions.

Timing Jitter - The maximum steady state timing jitter of "receive clock"
with respect to "transmit clock" Is less than 10% p.p for an Input slgnal·to·
noise ratio of 12 dB.

DISPERSION DUE
TO PHASE ERRORS

DISPERSION AROUND
PROPER POSITION DUE
TO COMBINATION OF
RANDOM NOISE, PHASE
ERROR, ANDIOR GAIN
ERROR.

CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL

Bit Error Rate - The following graph represents typical R24 performance:

Typical Eye Pattern: 4 Phase-24oo bps-12oo Baud (V26A)
Phase error and eye pattern can be extremely useful for modem acceptance
testing, product evaluation, and observation of line signal quality under
actual operation.

ELECTRICAL CHARACTERISTICS
POWER REQUIREMENTS

Voltage

Ripple

Maximum
Current

T

+5 Vdc±5%
+12 Vdc±5%
-12 Vdc±5%

100 mV p-p
50 mV p-p
50 mV p-p

38mA
16mA
48mA

Rl

+12 Vdc ±5%
-12 Vdc±5%

50 mV p-p
50 mV p-p

23mA
16mA

R2

+5 Vdc±5%
+12 Vdc±5%
-12 Vdc±5%

100 mV p-p
50 mV p-p
50 mV p-p

64mA
25mA
78mA

Module

Maximum total power consumption approximately 3 watts.
Typical total power consumption approximately 2 watts.
1
2
3
"
5

1200 BPS,
2400 BPS,
2400 BPS.
2400 BPS,
2400 PBS,

BACK.TO.BACK, SCAAMel ER, NO EQUALIZER
V.2eA OR B. BACK·TO·BACK, SCRAMBLER. NO EQUALIZER
V."" OR B. 150 .150 HZ PHASE JITTER. NO SCRAMBLER. NO EQUALIZER
V.26ACR B, 30°·120 HZ PHASE JITTER, NO SCRAMSLER,NO EQUALIZER
V.2tiA OR B. 3002 UNCONDITIONED LINE. NO SCRAMBLER, EQUALIZER

Typical Bit Rate Performance

Phase Error - Phase error can be measured by using the modem's output
signals PE, SYC, and A. With an external test circuit, a numerical value can
be derived to Indicate the quality of received data. This numerical value can
be directly correlated to bit error rate performance. The required test circuit
can be implemented with discrete circuitry or in software within a micro·
computer.

DIGITAL INTERFACE
The R24 provides LS TTL or CMOS compatible logic levels that are functionally equivalent to EIA RS2321449 and CCITT V.24.
Input
Logic

Allowed Input Voltage Levels

Low
High

-12.0V to +0.8V Sinking <10 /J.A
+4.0V to +5.0V Sourcing <10 /J.A

Digital Inputs are directly CMOS compatible. Interfacing with standard
TTL or low·power Schottky TTL requires an external pull-up resistor.
Output
Logic

Eye Pattern - By using the modems digital output signals RCVDS, SYC,
and A along with an added test circuit, the user can generate an oscilloscope quadrature eye pattern. This pattern displays the received signal as
a group of dots in the baseband signal plane; hence, it is a graphic representation of modem performance.

Low
High

Allowed Output Voltage Levels
O.OV to + OAV Sinking 0.36 mA
+4.0V to + 5.0V Sourcing 100 "A

Digital outputs are directly CMOS or low-power Schottky TTL compatible.

~

(17) S8GR
(16)V26A
lIS) I
(14) NSYNC
(13) ClAMP
(12) T111
(11)T2W/4W
lID) T114
I 9) Tl03
I 8) Tl05
I 7) T113
I 6) Tl06
I 5)TONA
1'4)T8C
I 3)CAUTO
I 2)T2

.325
(S.26)

TRANSMISSION LINE INTERFACE

The R24 provides an analog Interface that must generally be transformer
coupled to ensure normal telephone line Isolation. Through appropriate
selection of transformers and other interface circuitry, the R24 can be con·
figured to operate on leased or dlal·up telephone lines, or on other special
private networks. For the dial·up line interface, Rockwell offers an FCC
registered module that allows direct connection to this network. For the
leased line interface, only transformers with characteristics similar to those
utilized on the F,l24 modem evaluation board are required forthis connection.

The receiver and transmitter line interfaces are single·ended (non·trans·
former coupled) signals with the following characteristics:

·12V(18)
+12V (19)
COM (20)
+5V(21)
OAC OUT (22)
TFIL (23)
X (24)
K (25)

.325
(S.26)

Y (26)

TC06(27)
Z (28)
BOOMS (29)
E (30)
TIN (31)
·15dBm (32)
·13dBm (33)
·l1dBm (34)
·9dBm (35)
·7dBm (36)
·5dBm (37)
·3dBm (38)
·ldBm (39)

I I) TI

sa.

.025 (.64)
PIN
39 PLACES

Transmitter Module Package

-r

G21 9)
GAIN (10)
G111I)
REC IN (12)

1.025
(26.04)

L

Transmitter Output (Normal)
Output Impedance: 600 ohms ± 2%
Maximum output level:" 0.0 dBm

-~

L.

t

Transmitter Output (Alternate) Low Impedance:

.100
(2.54)
TYP.

Output Impedance: 0 ohms (op amp output)

·12V(13)
+12V(14)
COM lIS)

Maximum output level" + 6.0dB

sa.

.025 (.64)
PIN
15 PLACES

Note: This output for transformer loss compensation.

Receiver· Rl Module Package

Receiver Input:

11-

Input Impedance: lS.BK ohms ± 1%
Maximum Input Level: 0.0 dBm

L
MECHANICAL SPECIFICATIONS

I·

'CO:TNTS't ___________ -:!_
.00' MAX.

.-'i~

.062

I

~ 18~~~)

.soo

Tt09(22)
AGCIN(21)
THRH (23)
RLSO (24)
RBCK (25)
AGCOUT(26)
IANALOG (27)

(20.32)

1 . " " .,'"]

'",00

I
2.75

I

± .03

NOTE: This cross·section is common to all modules.

~II~~
I-.
.j :~S~. ±

.100
.007
MAX.
(LEAD PROTECTION)

~ :~g! ~~1~

(18) TH09
(17) CP04
(16) PBS
lIS) TC09
(14) S8GR
(13) V26A
(12)1
(11) NSYNC
110) CLAMP
I 9) Tll1
I 8)R2W/4W
I 7) PE
'1 G)TlI5
I 5) Tl04
(4)OCP

'~'l

2.500

I'JST' I~;:~'
MAX.

L. : ~!~CVOS

+SV (28)
COM (29)
+12V (30)
·12V (31)

,'\II)SYC
.100
(2.54)
TYP.

sa.

\025 (.64)
PIN
31 PLACES

Receiver· R2 Module Package
NOTES: 1) Dimensions in inches (millimeters).
2) Component side shown

•

•

PRINTED CIRCUIT BOARD MOUNTING OPTIONS
FOR THE R24 MODULES
Three methods of mounting are commonly used. Each configuration
has certain distinct advantages.
Mounting
Method

Type of Connection
or Connector Used

Basic
Advantage

Standard Flush
PCB Component
Mount

Wave Soldered Into Standard
PCB Eyelets

Lowest Height
Profile

Above Board
Low Profile
Socket

Connectors (SAE Series
3000 or Methode Series 1000)
These Sockets are Wave
Soldered Into Standard
PCB Eyelets

Plug·in Capa·
bility at Low
Cost

PCB Plug·in
Sockets (Bullets)

Connectors (AMP Miniature
Spring Sockets.)
Pin Sockets are Individually
Soldered Into PCB Eyelets

Lowest Pro·
file for Plug·in
Capability

R24 MODEM EVALUATION BOARD
To facilitate evaluation and deslgn·in of the R24 modem for new and exist·
ing equipment designs, an R24 Modem Evaluation Board (R24MEB) is
available - see below. The R24MEB can be easily combined with terminal
systems for real·tlme performance evaluation.

RECEIVER

ENVIRONMENTAL SPECIFICATIONS:
Operating temperature: O'C to 60'C
Storage temperature: ·40'C to + eo'c
Relative humidity: to 95% (non·condensing)
Altitude: ·200 to 10,000 feet (·61 meters to 3,049 meters)
Burn·ln: 96 hours at70'C

Order Information

R24 Modem Evaluation Board (R24MEB)
When ordering, specify products as follows:
R24 - Set of 3 modules (T, Rt, R2)
R24MEB - Modem Evaluation Board
The R24 transmitter function (R24·T module) and the R24 receiver function
(R24·R1, R24·R2 modules) can be purchased separately. Contact your
Rockwell Sales office or Anaheim to quote specific customer requirements.

The Modem Evaluation Board is equipped with a stand?rd 31 pin edge con·
nector, control switches, output ievel jumper, and interface transformers.
These features allow full control of the interface circuitry. In addition, this
unit can be used directly in a U.S. leased line configuration.
The R24MEB is recommended for all first·time users to assist in their evalu·
ation. Complete documentation is supplied with each initial R24MEB.

"1' Rockwell

MODEM PRODUCTS
PRODUCT SUMMARY

R24 DC 2400 BPS Direct Connect Modem
INTRODUCTION

FEATURES/BENEFrrs

The Rockwell R24 DC is a high-perfonnance, serial synchronous DPSK modem suitable for direct connection to
domestic switched network or two-wire private lines. Utilizing extensively MOS/LSI Technology and Hgh Quality
Components, the Modem plus registered protective cirruitry is implemented on a single 5.ocr by 7.850" card. Performance and versitility are enhanced while cost and size
are reduced by the on-board Rockwell PPS-4l1 One Chip
Microcomputer.

• High Performance; Low Cost
• LSI High Density; Low Power
• Microcomputer ControDed Une Conned/Disconnect
Sequence; Low Component Count
• Bell 201 BlC, CCITT V 26 Compatible
• Half Duplex (2-Wire) Operating Mode
• 2400 BPS Data Rate
• Auto or Manual Answer
• Auto or Manual Call Originate (Pulse Dialing)
• Automatic Answer Back Tone Generation upon Auto

The Rockwell R24 DC offers the user a complete high performance 2400 BPS Modem that is FCC registered for direct connection to the dial-up network. OEM's can easily
incorporate the Single Card into their computer terminals,
communication networks, PABX equipment, Data concentrators, Stand-alone box modems or any appications where
reliable data communication is required.

MAXIMUM MODULE DIMENSIONS
w

L

H

5.00"

7.850"

0.600"

INTERFACE CONNECTORS
DTE

40 pin, 0.100" spacing
20Iside

TELEPHONE LINE

10 pin, 0.100" spacing
51side

Answer
Direct Connect to Swtiched Networ1<
Programmable or Permissive Connection Arrangement
Local Analog Loopback Test Mode
Compromise Equalizer (Strap Selectable)
Scrambier/Descrambier Facility (Selectable)
Une Current Sensing (Selectable)
DTE Interface LSTTLICMOS Compatible
External Transmit Data Clock Tracking
Power Requirements, ±12V, +5V
Typical Power Consumption 3 Watts
Diagnostic Outputs Available for Eye Pattern and Data
Quality Monitor
• 15 Second Abort Timer (Selectable)
•
•
•
•
•
•
•
•
•
•
•

:II

~

C

n
~

8

m

"1J

tn
C

3
..
n

o

~
~

..Z
i:

8.
CD

3

CRocIrMIIIlnIIrnaIiaIaI Corporation 1981
AI RigIts Rasened
Prdad in U.S.A.

•

R24 DC FUNCTIONAL BLOCK DIAGRAM

AGC

IANALOG

AIIP

Receiver

Device
IIOSILSI
(111M3)

PPS411
Micro-

Proe..,or
Devlc.

(111M4)

(A7552)

Oi_gnostlca

A
SYC
ReVDS

DCP
PE

POWER SUPPLIES:

ENVIRONMENTAL SPECIFICATIONS

+5VDC ± 5% at 102ma (max.)
+12VDC ± 5% at 64 ma (max.)
-12VDC ± 5% at 142 ma (max.)

Operating temperature: O°C to 600C
Storage temperature: -40°C to +80°C
Relative humidity: to 95% (non-condensing)
Bum In: 96 hours at 70°C

For more information contact your local Rockwell Representative
or Regional Office, or Telecom/Subsystem Marketing, Rockwell
Microelectronic Devices, P.O. Box 3669, Anaheim, CA 92803.
TWX 910-591-1698. Telephone: (800) 854-8099, in CalifOOlia (800)
422-4230.

,~,

Rockwell International

'1' Roc~well

MODEM PRODUCTS
PRODUCT SUMMARY

V96P/1 Multi-Configuration 9600 BPS Modem
INTRODUCTION

FEATURES/BENEFITS

The Rockwell V96P/l is a versatile, high-performance modem on a single printed circuit board. Having CCITT V.29
and V.27 compatibility, the V96P/l offers the user sufficient
flexibility to customize a 9600 bps modem. With minimum
interface circuitry, the V96P/l can operate on dedicated
lines or on the general switched network. In addition, the
V96P/l is compatible with the Rockwell V96P and M96P
products.

• Maximum digital LSI signal processing
• 9600/7200/4800/2400 bps modes
• Ultimate user flexibility (CCITT V.29, V.27 ter, V.27 bis
compatible, and 300 bps per CCITT T.30)
• Single printed circuit card
• Smallest full-feature modem
• High reliability
• Approaches theoretical performance limits
• Operating Modes:
Half duplex (2 wire)
Full duplex (4 wire)
• TTL-compatible
• 0 to -45 dBm dynamic AGe range
• Analog loopback test circuitry
• Automatic adaptive equalizer
• Typical power consumption 3.5 watts

MARKET RESTRICTIONS
Minimum purchase must be 1000 units/year. Additional restrictions are application dependent. Please contact Rockwell for further information.

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BOARD DIMENSIONS

Dl

9.188 in. (233.38 mm) x 6.288 in. (159.7 mm)

0::s

i

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CD

3

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All Rights Rea.ved

Prinled in U.S.A.

__'__

'-~_.'~'4'_'_"~-'~--'---'~'--'-'-~------'-sp;;;;i~;;;;~~~to

change without noCice
Document No. 12400 N45

Aprtl'.'

•

I

•

V96P/1 FUNCTIONAL DIAGRAM

CONTROLS
TRANSMIT
HIGH SPEED
DATA
INPUT

ANALOG
OUTPUT

RECEIVE
LINE
SIGNAL

RECEIVE
,...-----------------_

~~T~ SPEED
OUTPUT

POWER SUPPLIES:

ENVIRONMENTAL SPECIFICATIONS

+5V (~ 5%) +VM, <200 rna
+12V (~ 5%) +VA, <110 rna
-12V (~ 5%) -V, <280 rna
(maximum currents)

Operating temperature: O°C to 60°C
Humidity: Up to 90%, non-condensing, or a wet bulb temperature up to 35°C, whichever is less

For more information contact your local Rockwell Representative
or Regional Office, or Telecom/Subsystem Mar1

16 Digit First-In-First-Out (FIFO) Memory
Asynchronous Operation
JOpps (2KHz Clock) Dial Pulse Operation with a Minimum
650ms Interdigit Time
20pps (4KHz Clock) Dial Pulse Operation with a Minimum
325ms Interdigit Time
CRC 8000, TTL Input compatible
CRC 8001, MOS Input compatible

eRe 8030 -

1~;-r

¢

CENTRAL
OFFICE

The dialer accepts binary data, stores the data in a first-infirst-out memory, and generates dial pulses at normal telephone rates. Internal timing is derived from an external
2KHz or 4KHz clock. With a 2KHz clock, a 10pps (60%
break/40% make) dial pulse frequency having a minimum 650
ms interdigit time is generated. If a 4KHz clock is used, the
dial pulse frequency is 20pps and the interdigit time is reduced to 325ms minimum. The memory section is necessary
as the incoming data rate may be much faster than the
normal dial pulse output rate. Binary codes one (I) through
fifteen (15) produce the same number of dial pulses. A binary
zero input produces sixteen (16) dial pulses.

Dual Tone Multi-Frequency Detector
TOUCH·TONE@

CENTRAL
OFFICE

ELECTRONIC
SYSTEM

Digital range filter detects all 16
combinations

Touch-Tone~

signal

Detects a tone pair in 22 ms to 39 ms
Digital logic impervious to frequency or bandwidth drift
caused by time, temperature, or voltage
Automatic internal reset when no tones are present
Variable pulsewidth Strobe output provides increased
talk-off protection
Binary or 2-of8 coded outputs option
Inputs/outputs can be left floating when not used
Single or dual power supply option
On-chip osciilator - 3.579545 MHz color-burst crystal

Dual-Tone Multi-Frequency (DTMF) or Touch-Tone~ signaling has made telephone communication faster, more efficient
and more convenient than dial pulse signaling. Touch- Tone~
telephone instruments or automatic dialers generate a tone
pair representing the "dialed" number and send them over
the lines to a receiver which detects the tones and reliably
identifies the number.
Utilizing a digital filter algorithm, the eRe 8030 provides
a low-cost and high-performance solution for DTMF
detection.
A strobe output indicates when the output data are valid .
When linked with a front-end band-split filter/limiter. the
DTMF receiver.

Central-office-qllality detection

eRe 8030 implements a complete

Excellent talk-offprotection -As little as one hit on Mitel te.ft
tape (CM 7290)

This design approach provides the optimum technological
benefits of analog and digital design techniques.

~ Registered trademark of AT&T

•

•

DTMF to Dial Pulse Conversion
TOUCH - TONE@

--~--......-_ _..,DIGITAL......-_ _..,

~

Lf

FRONTEND
FILTER/LIMITER

A DTMF to dial pulse converter can be easily implemented
using the eRe 8030 and the eRe 800t.
For example, where electronic switching systems (ESS) are
not available, the eRe 8030, a Dual-Tone Multi-Frequency
Detector, and the eRe 8001, a Binary to Dial Pulse Dialer,

L----oIC/,--------,
can be utilized to convert Touch-Tone® signals to dial pulse
signals. The eRe 8030 decodes Touch-Tone signals to their
binary equivalent and the eRe 8001 converts the binary
information to a train of pulses compatible with the standard
telephone dial pulse signals.

CRC 8000, 8001

MOS/LSI TELECOMMUNICATIONS DEVICES
TECHNICAL BULLETIN
Binary to Dial Pulse Dialer
16 Digit First-In-First-Out (FIFO) Memory
Asynchronous Operation
10pps (2KHz Clock) Dial Pulse Operation with a
Minimum 650ms Interdigit Time
20pps (4KHz Clock) Dial Pulse Operation with a
Minimum 325ms Interdigit Time
TTL Compatible
General Description
The eRe 8000 and eRe 8001 are P-channel enhancement mode MOS Binary to Dial Pulse Dialer utilizing
ion implant, low threshold voltage processing. The
Dialer accepts binary data, stores the data in a first-infirst-out memory, and generates dial pulses at normal
telephone rates. Internal timing is derived from an external 2KHz or 4KHz clock. With a 2KHz clock, a
10pps (60% break/40% make) dial pulse frequency
having a minimum 650 ms interdigit time is generated.
If a 4KHz clock is used, the dial pulse frequency is
20pps and the interdigit time is reduced to 325ms minimum. eRe 8000 and eRe 8001 are identical except
for their input interface. eRe 8000 inputs are TTL
compatible and eRe 8001 inputs are MOS compatible.
The devices are available in a 16 pin dual-in-line package.
The eRe 8000 can be installed in telephone central
office stations to perform binary to dial pulse conversions. In areas where electronic switching systems
(ESS) are not available, the eRe 8000 and eRe 8030,
a Dual-Multi-Frequency Detector, can be utilized to
convert Touch-Tone® signals to dial pulse signals. The
eRe 8030 decodes Touch-Tone signals to their binary
equivalent and the eRe 8000 converts the binary
information to a train of pulses compatible with the
standard telephone dial pulse signals.

CRC 8000, 8001
The Memory Read Inhibit line can be used to delay the
Dial Pulse Output. If the Memory Read Inhibit line is
low (binary zero), the first digit entering the FIFO
memory initiates the dialing sequence. The digit is
transferred from the memory to a down counter that
generates the appropriate number of dial pulses. Internal timing produces the proper interdigit time between
pulse trains. If there is a pause in the binary data
input, the circuit generates an extra length interdigit
time in a manner identical to that created by a rotary
dial.
A high level (binary one) Memory Read Inhibit prevents
the reading of the memory thereby causing a pause.
During this condition, existing data in the FIFO will
be stored until Memory Read Inhibit is released (low
level). When the inhibit line is changed from a low
level (binary zero) to a high level (binary one), a dial
pulse train in process will be completed before pausing.
Additional digit data may be input to the FIFO
memory as long as the 16 digit capacity is not exceeded.

Technical Characteristics
MAXIMUM RATINGS

Non·operating Yoltages with no damage to device
SuPply Voltage Vee .
•
SuPply Voltage VGG
•
•
POSitive Voltage on any pin
Negative Voltage on any pin

Power DISSipation at 25°C.

.

.

VSS = +5.0V. VGG = ·12.0V
Operating Temperature Range Icase) .

Storage Temperature Range (case)

V SS ·8.0V
VSS ·21.0V
VSS + O.3V
VSS ·20.0V

2l5mw
• . oOe to +lOoe
. .55 0 e to +Isooe

en
CD
c

...CD

INTERNAL CLOCKS

CLEAF~

"'"CJ

c

Dr

CLOCK~

----_

Registered Trademark

Q)

o
o
9
Q)
o
o......

The Reset input is a "Master Reset". If the Reset
input line is low, Busy is set to a low level and Dial
Pulse Out is set to a high level. The outputs will
remain in that state until a new digit is input to the
FIFO.

Dialer operation is controlled by the "Load" and
"Memory Read Inhibit" inputs. A load pulse is required
in order to input each digit into the FIFO. With a
2KHz clock, the maximum data entry rate is 500 digits
per second.

® AT&T

:tJ

o

The Busy output line is high when there is data in
memory or dial pulses are being generated.

Operation
Digits, in the form of four binary inputs, are loaded
asynchronously relative to the clock into a 16 digit
first-in-first-out (FIFO) memory. This memory section
is necessary as the incoming data rate may be much
faster than the normal dial pulse output rate. Binary
codes one (1) through fifteen (15) produce the same
number of dial pulses. A binary zero input produces
sixteen (16) dial pulses.

o

ALL CIRCUITS

33177·3

RECOMMENDED OPERATING CONDITIONS/ELECTRICAL
CHARACTERISTICS FOR IOpps OPERATION
Unless Otherwise Noted VSS = +5.0V, VGG = -12.0V, V DD = O.OV,
OOC "TA " 7oDC, and clock frequency = 2.0KHz !.. 5%
PARAMETER

MIN

TVP

MAX

UNITS

CONDITIONS

Power Supplies
VSS

Supply Voltage

VGG

Supply Voltage

4.75

V

V DD

-11.0

V

V DD

0.8

V

5.0

-13.0

-12.0

-1.0

0.0

5.25

= O.OV
= O.OV

See Note 1

Inputs
VIN(O)

Logical "0" Input voltage

V IN (l)

Logical "1" Input voltage

C IN

I nput capaCitance

V SS -0.7

}

V

V SS +0.2

See Note 2

pF

10

V IN

= VSS - 1.0V

Input Timing
fc

Clock repetition rate

tpc

Clock duty cycle

45

1.9

tr

Input pulse rise time

40

500

ns

tf

Input pulse fall time

40

500

ns

tLH

Load pulse width "High"

1.9

ms

See

tLL

Load pulse width "Low"

0.1

ms

Timing

td1

Data set·up time

ms

Diagram

td2

Data hold time

tML'

Memory Read Inhibit stable
time relative to Load

t MDP

Memory Read Inhibit stable

2.0
50

1.75

650
1.0

1. Other supply parameters are permissible including VSS = O.OV,
VOO = -6V, and VGG = -12V. Input/output parameters will
be adjusted accordingly.
Min. Typical
Max.
-7.0
-0.7

-6.0
0.0

-5.2
+0.2

Vout (0)
Vout (l)

0.0
-2.6

0.0
0.0

-5.6
0.0

PARAMETER

all Inputs
Including ClOCk

ms

See Note 4

ms

See Note 4

ps

NOTES

Yin (0)
Yin (1)

}

Applies to

ms

650

Reset pulse width

See Note 3

%

0.5

time relative to Dial Pulse Out
tR

KHz

2.1
55

MIN

2. All
up
All
up

inputs of eRe ROOO have "on chip" 3200 .±,30% ohm pull·
resistor to V SS and are suitable for being driven by TTL.
inputs of eRe 8001 have a high impedance input (no pull·
resistor) and are suitable for interface with MOS devices.

3. For 20pps operation, a 4.0 KHz is clock required. If the clock
has a 5% tolerance, the operating specification can be derived
from the above table. All parameters will remain the same
except for the following timing parameters which will be
reduced by one half: tLH, tLL. td2' tML, tMOP, topo, top,
tOPL, tOPH, tID' Similarly, a 10 KHZ clock could be used,
producing a 50pps output rate.

TVP

MAX

UNITS

CONDITIONS

Outputs
Vout(O)

Logical "0" output voltage

tf(out)

Output fall time

V out (l)
tr(out)

Output rise time

Logical \'1" output voltage

0.4

V

500

ns

400

ns

V

2.4

I Slnk = 1.6 mA
90% to 10%
Isource = 0.1 mA
10% to 90%

Output Timing
topo

Dial Pulse Out Delay

900

ms

top

01.1 Pulse Period

95

100

105

ms

See Note 3

t oPL

Dial Pulse WIdth "Low"

57

60

63

ms

and Timing

t oPH

01.1 Pulse Width "High"

38

40

42

ms

Diagram

tiD

Dial Pulse Interdlglt TIme

650

740

tb1

Busy L.ow/Hlgh Delay

tb2

Busy Hlgh/L.ow Delay

700

ms
2.1
10

ms
/-Ls

Power
Po

Power Dlsslpitlon

125

275

mw

LOAD

DATA

1

f--

1
DIAL
PULSE
OUT

VIA

VI///j

Will]

1--1

DATA MUST BE STABLE

'DP

'10

I 1 ~
l~~

'DPD

I
I

I

1-1 t--'DPH
--i f--'DPL

I

--J f--'bl

q

~'~.--------------------------~

I

~~~gRY
INHIBIT

RESET

~-----------'ML--------~~I

','~

~

X
-------------------------------------'l,t------f\L..._______-' L ___________________

-U

- l t--'R
NOTE: CLOCK INPUT IS ASYNCHRONOUS

30377·6

4. To prevent a dial pulse train from being output, Memory Read
Inhibit must be stable prior to initiating that pulse train. This
stabilization point is specified for two cases: (1) If no pulse
trains are presently in process (e.g., the device has been reset),

Memory Read Inhibit must be stable 650ms after the load
pulse was initiated;(2) If a pulse train is in process, to prevent
the next pulse train from being output, Memory Read Inhibit
must be stable 650ms after the interdigit time was initiated.

Packaging and Ordering Information
BINARY TO DIAL PULSE DIALER (CRC8000·1·3)

PIN 1

0017 !0.OO3

r~l
0.B2~

1
2
3
4
~

6

1
B

9

LEADS 0.100
TO

t

MAX

t

l J
I--~i~~

The Binary to Dial Pulse Dialer is available in a 16-pin
hermetically sealed ceramic dual-in-line package (see pin
assignments and package dimension diagram). Order by
type numbers.
eRe 8000-1-3 (ceramic DIP) 765-1892-001
eRe 8001-1-3 (ceramic DIP) 765-5841-001

PIN ASSIGNMENTS

10
11
12
13
14
I~

16

VSS
BUSY
DATA (2)
N.C.
DATA (I)
DATA (4)
DIAL PULSE OUT
DATA (B)
VGG
VOO
MEMORY READ INHIBIT
LOAD
CLOCK
TEST OUT·
TEST INRESET

·PlN 141S AN OUTPUT CLOCK RUNNING AT A
FREQUENCY OF (PIN 13. 200)H •. THE PERIOD
IS 6011 BREAK/4011 MAKE.
··PIN I~ MUST BE GROUNDED (VOO) DURING
CIRCUIT OPERATION.

30377·7

•

•

CRC 8030
Rev.

~~_'~oc~~en
'..

\ ..

•

~,

I'

5/78

MOS/LSI TELECOMMUNICATIONS DEVICES
DATA SHEET

~"I"

Dual Tone Multi-Frequency Detector
Digital range filter detects all 16 Touch Tone® signal
combinations
Detects a tone pair in 22 ms to 39 ms
Digital logic impervious to frequency or bandwidth
drift caused by time, temperature, or voltage
Automatic internal reset when no tones are present
Variable pulsewidth Strobe output provides increased
talk-off protection
Binary or 2-0f-8 coded outputs option

c

Inputs/outputs can be left floating when not lIsed
Single or dual power supply option
On-chip oscillator - 3.579545 MHz color-burst crystal

cQ)

-4

Central-office-quality detection

o

Excellent talk-off protection - As little as one hit on
Mitel test tape (CM 7290)

3:

::::I

DTMF Signaling and Receivers

Dual-Tone Multi-Frequency (DTMF) or Touch-Tone@
signaling has made telephone communication faster,
more efficient and more convenient than dial pulse
signaling. Touch-Tone® telephone instruments or automatic dialers generate a tone pair representing the
"dialed" number and send them over the lines to a
receiver which detects the tones and reliably identifies
the number. DTMF signals are defined by a 4 x 4 audio

CD

tone matrix as illustrated in figure 1. Each digit is represented by one tone from the low-group and one tone
from the high-group. These non-harmonically related
frequencies protect the message against false-keying by
stray signals and voice-generated tones.
A DTMF receiver must recognize the dual tones within
a certain bandwidth while tolerating dial tone, noise,
input amplitude variation and "twist" or amplitude
differential between the two tones. In addition, the
receiver has to comply with timing restrictions imposed
by the DTM F generation process and meet other specific
requirements of the particular application.
CRC 8030 General Description

DTMF
SIGNAL

or'

-n

CD
.Q

C

CD

::::I

n

<

C

CD
CD

r+

..o

~

DECODED
OUTPUTS

HIGH GROUP
FREQUENCIES

Figure 1. Touch Tone® Pad (Dual Tone
•
Si{!naling)

lI1ulli.Frequenc~1477.8

Fi{!ure 2. DTMF Receil'er l'lilizin{! CRC H(),'J()

................ ".,..........."

® Registered trademark of AT&T

..

The eRe 8030 provides a low-cost and high-performance
solution for DTMF detection. Utilizing a unique digital
filter algorithm, the patented* eRe 8030 performs
the key critical functions of a DTMF receiver. When
used in conjunction with a front-end band-split
filter/limiter, the eRe 8030 implements a complete
DTMF receiver (figure 2). This design approach provides the optimum technological benefits of analog and
digital design techniques.

lOW·GROUP
FREQUENCIES

'-"".,.. "

c

::;

21477·9

.......... _... /
* C.S.

Patent No. ·1 () 1 (j:rj 1

•

I

The exact requirements for the front-end filter/limiter
vary with the particular receiver application. For
example, high quality central office receivers require
a more selective front-end filter. Conversely, low-noise
environment keyphone systems can use a less stringent
front-end filter design.

Operation

The CRC 8030 is a DTMF detector implemented with
PMOS ion-implantation processing. This detector
accepts group-filtered and square-shaped DTMF frequencies and converts them to binary data or 2-of-8
coded data in 22 ms to 39 ms;out-of-tolerance frequencies are rejected. The device ignores the first few
pulses of the input signal in order to prevent errors in
detection due to the transients from the Touch-Tone®
pad. The signal is then analyzed several times by a
digital range filter prior to being accepted as valid. As
soon as the range filter has recognized a frequency
below 1680 Hz, the Audio Detect (AUD) output is
enabled. This output provides the user with a signal for
controlling the limiter gain at the receiver front-end. A
Strobe (ST) output indicates when the output data are
valid.

DTMF receivers historically have been implemented
with all-analog filtering techniques, i.e., phase-locked
loops, LC filters and active filters. Compared to a
phase-locked-loop receiver, the CRC 8030 provides
much superior performance. Compared to LC or active
filter receivers, the CRC 8030 can be manufactured for
a significantly lower cost wnile providing improved
performance. The CRC 8030 provides the economy,
performance, size and reliability benefits of digital
MOS/LSI. The CRC 8030 is packaged in a 28-pin DIP.

Once a digit is accepted as valid, the CRC 8030 will
ignore any change in tone frequency until either the
high-group or low-group tone disappears for more than
10 ms. When this occurs, the device is reset internally
and will be ready to accept another Touch-Tone®
digit. This feature provides immunity to frequency
drift that could be caused by Doppler shift. Should a
frequency in either the high- or low-group disappear
for less than 10 ms, the gap is bridged resulting in only
one digit.

Applications

The eRC 8030 can be applied to all systems requiring
DTMF detection. This includes the traditional telephony systems: keyphone, PABX, central office, intercom and mobile radio communications. Other applications include computer signaling and control systems.
Where it is necessary to interface with a dial pulse
system, the CRC 8030 and the CRC 8000 (a Binary-toDial-Pulse Dialer) implement a DTMF-to-dial-pulse
conversion system.

A block diagram of the CRC 8030 is shown in figure 3.
The functions include timebase generation, wave shaping circuitry, range counters with correlation circuitry,
and the output timing and decoding functions.

The CRC 8030 has been functionally designed to provide optimum performance for a wide variety of DTMF
detection applications.

Vss

voo

VGG

1633 Hz DISABLE (NI6)

r-----.Ll~­

I

STROBE
CONTROL (SC)

__-----+-- BINARY OUTPUT
SELECT (BIN)
OUTPUT HOLD (HLo)
I - - - - - - r. . AUDIO DETECT (AUo)

TEST
ENABLE (TE) - - - - - - ,

I

I--------t-. . SILENCE RESET (SIL)

xd
XIID

X2

II

TIMING AND 1-------;.... STROBE (ST)
DECODING
1209 Hz

TIMEBASE

1336 Hz
1477 Hz

TEST
OUTPUT (X0)4--'-----'

HIGH-GROUP
OUTPUTS

1633 Hz

01/697 Hz
021770 Hz

04/852 Hz

LOW-GROUP
OUTPUTS

08/941 Hz

--------CHIP INHIBIT (lNH)

-tt-t
C32

C16

_-.J

C2

21477-10

Figure 3_ CRC 803U Bluch Diagram_

2

Technical Characteristics
Maximum Ratings: Non-operating voltages with no
damage to device Supply Voltage VDD.· ................ VSS -8.0V·
Supply Voltage VGG ................ VSS -21.0V
Positive Voltage on any pin ........... VSS +0.3V
Negative Voltage on any pin .......... VSS -io.ov
Power Dissipation (OoC:!( TA :!( 70 0 C) ...... 200 mW
Operating Temperature Range (case) .... 00 to +70 0 C*
Storage Temperature Range (case) .. -65 0 C to +150 0 C
* An extended temperature range device will be available in the future.
Inputs and Outputs
The inputs and outputs are illustrated in figure 3 and
are described below with a positive logic convention
assumed. However, the operation is defined such that
when a 2-of-8 output format is chosen, the Strobe and
the low-gr04P outputs display data with a negative
logic convention. The high-group outputs always display data in a negl:'tive logic convention. Detailed timing
is shown in the timing diagram, figure 4.
Inputs
Logic levels are MOS compatible. Inputs BIN, INH,
HLD, SC, NI6, and TE have on-chip active pull-up
devices to Vss with a minimum of 50 Kn resistance;
therefore, no connection is required to these pins if a
high-level input is desired.
• High- and low-group DTMF signals (FL, FH) -These
are the filtered and square-shaped DTMF tones. When
no signal is present, both input levels should be low
(most negative level).
• Binary Output Select (BIN) - If this input is low
(most negative level), the decoded outputs are displayed in a binary format and Strobe (ST) pulses
from a normally low state to a high state (figure 4).
If this input is high or open, the decoded outputs
are displayed in a 2-of-8 code and Strobe pulses
from a normally high state to a low state.
• Chip Inhibit (lNH) - If this input is low, the device
is inhibited from decoding any DTMF tones. When
decoding binary, the outputs stay low. When decoding 2-of-8, the outputs stay high. If this input is high
or open, the outputs function normally. Chip Inhibit
is also a master reset except for the output data
registers when Output Hold is low.
• Output Hold (HLD) - If this input is low, the output
data, if valid, are stored in the output registers. If
the input is high or open, the outputs will function
normally ..
• Strobe Control (SC) - This input controls the pulsewidth of the Strobe (ST) output.
When Strobe Control is high or open, the signal is
analyzed for the full 39 ms data acquisition (tDA1,
Long Strobe) period. If the input tone-pair is
detected within 22 ms, then the Strobe (ST) output
pulsewidth is at a maximum of 17 ms. If detection
takes more than 22 ms, the Strobe pulsewidth is
reduced by the extra time needed for detection. If
the signal is detected after the 39 ms 'period, no
Strobe pulse will occur.
3

When Strobe Control is low, the input signal is
analyzed for a 33 ms period (tDA2, Short Strobe).
If the tone is detected within 25 ms after its inception, then the Strobe pulsewidth is 8 ms. If detection occurs after 25 ms, then the Strobe pulsewidth
is reduced by the lag time. If no signal is detected
within the 33 ms period, no Strobe pulse will occur.
When a Short Strobe is selected, a higher quality
input signal must be present in order to be accepted
as a valid signal. Thus, voice or noise signals on the
telephone line, which require a longer detection
time, will be ignored by the chip. As a result,. the
device has a higher immunity to false-keying when
Strobe Control is low.
In either case, the tone pair may be detecteo, but
the Strobe signal may not necessarily be generated,
depending on the quality of the input tone-pair.
• 1633 Hz Disable (N16) - If this input is low, the
device will not respond to the 1633 Hz tone, thus
improving the talk-off rate. If this input is high or
open, the device will respond to the 1633 Hz tone.
• Clock Inputs and Control (Xl, X2, TE) - The
eRC 8030 contains an on-chip oscillator for a
3.57954 MHz parallel resonant crystal. This crystal is
connected to Xl and X2 and TE is held high or left
open. As an option, an external 447.443 kHz oscillator can be used t.o clock the CRC 8030. In this
case, Xl is the 447.443 kHz clock input, X2 is left
open, and TE is held low. For some applications (e.g.,
using several CRC 8030 devices on a board), it is possible to drive the chip with an external 3.579545MHz clock at pin X2, while leaving the TE pin open, and
tying pin Xl to VSS.
Outputs
All outputs feature open-drain devices. With a singlepower supply (Vee = VOD), they will drive LPTTL,
MOS or CMOS inputs. With a dual power supply, they
will drive the base of a transistor. The open-drain output devices must be tied thrQugh a pull-down resistor
to a negative voltage between VDD and VGG (when used);
the value ofthis resistor depends upon the type of interface.
Typically:
Res~~!

I.!lJelfA~

1.5Kn
10.0KH
7.5KSl

LPTTL
MOS or CMOS
Base of a Transistor

These outputs ca.n also drive LEDs. For more design
details, consult the Collins Application Note,
"CRC 8030 Telephone DTMF Receiver".
• Decoded Outputs (D1/697 Hz, D2/770 Hz, D4/852
Hz, D8/941 Hz, 1209 Hz, 1336 Hz, 1477 Hz,
1633 Hz) - These outputs display decoded information in either a binary or a 2-of-8-coded format
as described below.
When a 2-of-8 format is selected (BIN input is held
high or left open), all 8 outputs are utilized. When a
particular digit is decoded, the corresponding highand low-group outputs go low (figure 1). For

RECOMMENDED OPERA TING CONDITIONS/ELECTRICAL CHARACTERISTICS
Unless Otherwise Noted VSS = +5.0\.-', VGG = -B.OV, Vnn = O.OV
OOC";; TA ,,;; 70 0 C
Positive Logic
MIN.

TYP.

MAX.

UNITS

VSS

<4.75

+5

+5.25

V

VGG
V DD

-13.0

-8.0

V DD

V

PARAMETER

CONDITIONS

Power Supplies

0

Inputs
VIN{O)

Logical "0" input voltage

-13.0

V

Logical "I" i'nput voltage

V SS -O·7

IN

{I)

R'N
C IN
t r & tf

Input impedance

-8.0

VSS-4.0

V

VSS+0.2

V

kn

50

Input capacitance

10.0

pF

VIN = V SS -l.0V

Input voltage rise or fall time

15.0

pS

Voltage swing 10% to 90% of final level

±0.005%

Input Timing
F,

Clock Crystal Frequency

3.579545

MHz

F2

Opt ional Clock Frequency

447.443

KHz

±0.005%

DC

Clock duty cycle

45

%

Optional Clock

tr

Input clock pulse rise time

40

200

tf

Input clock pulse fall time

40

200

ns

90% to 10% of final level

Detected Frequencies Low Group

I nput signal (F L or F H) duty cycle

55

697
770
852
941

Detected Frequencies High Group

IDC

50

Optional
Clock

Hz

H,
Hz )
Hz

1209
1336
1477
1633
30

10% to 90% of final level

Hz
Hz
Hz
Hz

50

70

Bandwidth range:
-1.9 to -3.2%
+2.0 to +3.3%

%

Outputs'
VOUT{O) Logical "0" output voltage
tf{OUT)

VGG + RL 'sink
2.2 RL CL

Output fall time

V OUT {I) Logical "I" output voltage
tr{OUT) Output rise time

V

VSS-O·4
4

pS

ms

ISO URCE = 2.0 mA
10% to 90% of final level (with 30 pF load)

Output Timing
tsp

Silence Period

9.4

10

10.6

tR

Silence Pulsewidth

1.0

1.1

1.2

tDAl

Data Acquisition Time Option 1

22

39

tDA2

Data Acquisition Time Option 2

25

33

tAUD

Audio Detection Time

1.5

8

tH

Output Hold Set·up Time

10

pS

2

pS

tlNH
C2
C
'6
,C 32

Chip Inhibit Pulsewidth

ms
ms

kHz

Clock
Clock

16

kHz

Clock

32

kHz

tSI

Strobe Pulsewidth OPtion 1

0

17

ms

tS2

Strobe Pulsewidth Option 2

0

8

ms

I

±0.1 %

Power
POI

Power Dissipation (Dual Power Supply)

200

mW

VSS = 5.25V; VGG = -13V

P02

Power Dissipation (Single Power Supply)

180

mW

VSS = 5.25V; VGG =

VOO = OV

• For a full description of the 9utput buffer capabilities, refer to the CRC 8030 Application Note.

4

21477-11

FL

FH
"1" ------------+----~----------OUTPUT HOLD

"0" -

CHIP INHIBIT

"1"
"0"---

-

-

-------------7-----.....------------~tA~~~----------~~------~.,,~___________________

AUDIO DETECT

----------~/

BINARY OUT
2 OF 8 OUT

,,~-----------------

,,~---:---~/

STROBE LONG

l-tDA1~

STROBE SHORT

rtDA2~

~~------~--------~-----------

~-.-----------------------------

SILENCE RESET

NORMAL HOLD OPERATION

~

_ _ _ _ _ _ _ _ _ _1 - , tH

OUTPUT HOLD

~.----------~--------~I

-------'- - - - - - - - - - - - - - -

BINARY OUT

.

I,
I

~I

'---_._--I
I

2-0F-8 OUT

\~------- _____~I
OUTPUT HOLD OPERATION

CHIP INHIBIT

'----1

--l

OUTPUT HOLD

I-

tlNH
"'" - - - - - - - - - - ; - ,.-,;..~..:-------------:---------

____ .-r--'L-

"0"--- BINARY OUT

I

I
I

2·0F-8 OUT

-------------------

I
INHIBIT OPERATION

-

- - OUTPUT LEVELS FOR BINARY OPERATION

- - - - OUTPUT LEVELS FOR 2·0F·8 OUTPUT OPTION

21477·12

Figure 4. Timing Diagram

5

•

•

Touch.Tone@ Matrix: Binary Outputs

1209
697
770
852
941

01
1
0
1
1

02
0
0
1
1

04
0
1
1
0

1336
08
0
0
0
1

01
0
1
0
0

02
1
0
0
1

04
0
1
0
0

1477
08
0
0
1
1

01
1
0
1
0

02
1
1
0
0

04
0
1
0
1

1633
08
0
0
1
1

01
1
0
1
0

02
0
1
1
0

04
1
1
1
0

08
1
1
1
0
21477·13

Figure 2 illustrates this design. With this approach, a
central-office-quality receiver with the following specification can be implemented:

Outputs (continued)
example, for digit 1, D1/697 Hz and 1209 Hz outputs will go low when detected. All other outputs
remain high.

•

•

•

•

•

•
•
•
•
•

When the binary format is selected (BIN input is held
low), the high-group outputs operate as described
above. The low-group outputs (D1/697 Hz, D2/770
Hz, D4/852 Hz and D8/941 Hz) provide the binary
coded information. These binary outputs are normally low and go high when a tone is detected. The
ou tpu ts are defined by the above matrix:
Strobe (ST) - This output indicates when the output data are valid. Validity is defined as detection
within 39 ms or 33 ms depending upon the level of
Strobe Control. For a description of the operation,
refer to the inputs BIN and SC and figure 4.
Silence Reset (SIL) -This output pulses to a low level
when silence is detected. This occurs 9 ms after the
interruption of a signal on either high- or low-group
inputs. This output can be uSl'd to reset any external
logic or to l'xercise the Output Hold option. The chip
will reset itself after the Silence Resl't output returns
to a high level. Silence reset pulses at 10 ms intl'rvals
until a signal is present on either FL or FH.
Audio Detect (AUD) - Audio is defined as energy
carried by any frequency lower than 1680 Hz. AUD
remains low when both FL and FH are low; AUD
will go high if either FL or FH is toggling and will
return to a low level as soon as Silence Reset returns
from a low to a high level. This output may be used
to control the aW'nissible level in the Front-End circuitry (off-chip) or to give advance notice of a
tone-pair.
Test Output (XO) - When using thl' 3.579545 MHz
crystal on-chip oscillator, XO will display a 447.443
kHz clock. If the 447.443 kHz external oscillator
option is utilized, XO will display a 55.930 kHz
clock. The XO output frequency will be the Xl input
frequency divided by 8.
Clock Outputs (C2, C16, C32) - These outputs
will generate 2 kHz, 16 kHz and 32 kHz clocks,
respectively.

Input Dynamic Range ........ -26 dBm to +6 dBm
Twist ......................... -8 dB to +4 dB
Valid Tone Tolerance ................... ± 1.5%
Invalid Tone Reject Limit ................ ±3.5%
Tone Burst (minimum) ... 40 ms ON, 11 ms OFF at
12 bursts per second

Inasmuch as the front-end filter is an essential part of
the total receiver, its characteristics have a major impact
on the performance of the system. For example, for
high-quality central-officl' receivers, a more selective
front-end filtpr is required. Conversely, low-noise
environment keyphone systems will .operate with a
less stringent front-end filter design. In view of the
diffen'llces in specifications for DTM F receivers, the
front-end dl'sign must be tailored for the particular
application. Several manufacturers have off-the-shelf
hybrid products which ml'pt these filtering requirements. For more details concerning these design considerations, refer to the Collins "Application Note CRC 8030 Telpphone DTMF Receiver".
For specialized applications, the CRC S030 has several
mask programmable· features. The parameters that can
be programmed include the bandwidth, detection time,
strobe timp, silencp timp, and output decode format.
Contact Collins Applications Engineering for details.
Packaging and Ordering Information
The DTMF Detector is available in a 2S-pin, hermetically sealed ceramic dual-in-line package and in a 2S-lead
ceramic chip carrier (see pin assignments and package
dimension diagrams). Order by type number.
CRC 8030-1-3 (ceramic DIP) . . . . 765-5795-001
CRC 8030-4-3 (ceramic carrier) . . . 765-5795-003
For further information on Rockwell MOSjLSI Standard
Products, call your local Rockwell Sales office or:
MOS/LSI Marketing
Rockwell International
Microelectronic Devices
3310 Miraloma Avenue
Anaheim, California 92803
Telephone (714) 632-2558
TWX 910-591-1698

DTM F Receiver Design
The CRC 8030, in conjunction with a front-end analog
filter/limiter, implements a complete DTMF receiver.
6

DTMF DETECTOR (CRC 8030-1-3)

DTMF DETECTOR (CRC 8030-4-3)

rtf

~

II
:

I

I

__ .600NOM-j

--m
ir=

010

OiI-

'90

PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14

1-1-

I

TW· --J,~;

~.12~MIN

--j

f-060NOM

PINS ARE READ COUNTERCLOCKWISE

PIN

PIN

.@. Q!i!f!!.~
VSS
1633 HZ
SIL
INH
C2
C16
C32
X2
VGG
Xl

TE
XO
AUO
1336 HZ

II

!:!!!:
15
16

17
18
19
20
21
22
23
24
25
26
27
28

PIN

.@. Q!i!f!!.~

Q!i!fJ'!'~
1209 HZ
HlO
SC
VOO
041852 HZ
081941 HZ
ST
021110 HZ
BIN
Fl
FH
011697 HZ
1477 HZ
N16

1
2
3
4
5
6
7
8·
9
10
11
12
13
14

VSS
1633 HZ
Sil
INH
C2
C16
C32
X2
VGG
Xl

TE
XO
AUO
1336 HZ

!:!!!:
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Q!i!f!!.~
1209 HZ
HlO
SC
VOO
041852 HZ
081941 HZ

ST
021110 HZ
BIN
Fl
FH
011697 HZ
1471 HZ
N16

21477·15

21477-14

NOTE: Collins MaS/LSI Products is now a part of Microe/rc/ronic Devices, ROc/lweI/International.

7

DOCUMENT NO. R8040D
REV. 1. AUGUST 1979

PART NUMBER

R8040

MOS/LSI TELECOMMUNICATIONS DEVICES
DATA SHEET
T-1 TRI-PORT MEMORY
OVERVIEW

FEATURES

The Tri·Port Memory circuit Is designed to function as an assem·
bly point and temporary storage area for 8·bit T·1 data. It provides
64 8·bit locations of on-chip random access memory which can be
accessed via external addresses or Internal sequential addressing.

•

64 x 8 bit static memory

•

Single +5V supply

TRI·PORT MEMORY OPERATION
The Tri·Port Memory device accepts 8·bit parallel input data on
lines A through H. This data is stored in an internal memory
location that is selected by either random address lines R01
through R32 or by the device's Sequential Address Counter.
Write Select signal WSEL determines the source of the address;
in the logic 0 state, WSEL selects the random address, in the
logic 1 state, WSEL selects the internal sequential address.
The state of Write Enable signal We determines whether or not the
data on lines A through H will be written into memory. Data will
only be written into memory when WE goes low Ito a logic 0
state) and the address inputs have stabilized.
The on·chip, six·bit Sequential Address Counter is a binary counter
that increments on each positive transition of Sequential Clock
(SCLK). When the Counter attains binary 111111, the next
positive transition on SCLK will clear it to binary 000000. The
Counter will also be cleared unconditionally if Reset signal RST
has been set to logic 0 when the pOSitive transition of SCLK
occurs.
The Sequential Read Enable signal, SRE, enables sequentially.
addressed read operations. If SRE is logic 0, the sequential
accessed data outputs (SA through SH) will become valid within
430 ns after the next positive transition on SCLK. If SRE is
logic 1, and 350 ns have elapsed since the positive transition of
SCLK, the sequential accessed data Qutputs will become valid
80 ns after the negative transition of SR'E. The Sequential Read
Data will cease to be valid within 100 ns after the positive tran·
sition of SRE, or within 340 ns after the negative tranSition of
WE (in the case of a same·location read/write cycle), or within
430 ns after the next positive transition of SCLK.
The Random Read Enable signal, R'RE, enables random·accessed
read operations. If RAE is logic 0, the random accessed data
outputs IRA through RH) will become valid within 380 ns after
the random address lines have stabilized. If'R"RE is logic 1, and
300 ns have elapsed since the random address lines have stabi·
lized, the random accessed data outputs will become valid 80 ns
after the negative transition of RRE. The random accessed data
outputs cease to be valid after a pOSitive transition of R"RE, or
within 340 ns after the negative transition of WE lin the case of
a same·location read/write cycle) or within 380 ns after the
random address input lines change.

o

Rockwell International Corporation 1979
All Rights Reserved
Printed in U.S.A.

•

Two totally independent read ports

•

MUltiple Read access time <430 ns (worst case)

•

Selectable random- or sequential·address Write operation

•

On-chip sequential address counter

•

Tri·state drivers, for chip-selectable bus operation

•

40·pin plastic dual in-line package

•

LSTTL Schottky-compatible (12K

n pullup, to drive CMOS)

--a
I

o

::D
-I

3:
3:

m

o

::D

A04
A08

R02

A16
A32

RST
SCLK

WSEL

N.C.
vOO

ROl

WE
AH
AG

N.C.'
SH

GND

SG

AF
RE

SF
SE

RD

SO

RC

SC

AB

SB

AA

SA

F'iRE

SRE

A
C

0

E

F

G

H

·PIN 34 HAS AN OUTPUT SIGNAL APPLICABLE ONLY TO
ROCKWELL TESTING. MAKE NO CONNECTION TO THIS
PIN.

Pin Configuration

Specifications subject to
change without notice

--<

::D

CO

o
~
o

-

R32 RANDOM ADDRESS INPUTS
R18

10F84
READ
RANDOM
ADDRESS
DECODER

ROot

RANDOM
READ PORT

WRITE
ADDRESS
SELECTOR

WSEl
"O"-RANDOM

SEQUENTIAL
ADDRESS COUNTER

SClK

t

10F84

=~=~++===J
S02

>-----"""1) ClK
R

..

SEQUENTIAlREAD PORT

S32
S18

S01

READ
SEQUENTIAL.
ADDRESS
DECODER

~+5
GND
0
~

)

Tri-Port Memory Block Diagram

RANDOM READ

:~~~~~ :?";'l1aTLllm7Ulm7l1:1~=:================]717271~=========
IR01-R321

RANDOM
OUTPUTDATA ______
IRA-RHI

~--------------~~------------~~~~----~-------20 ns
MIN. HOLD

380 ns ItRAI
MAX.

RANDOM WRITE

~:i~E
IA·HI

-----rr.,,----jlmUrrZ---I

~100 ns MIN.ItWHI
RANDOM ---~~---------~---~r-~~-------------------ADDRESS __LULU~_______~-------------IR01-R321

RANDOM
OUTPUTDATA __________~LU~t_--------------~r_---IRA-RHI

,.._ _ _ 340 ns

I

MAX.------j

SEQUENTIAL READ

E~b

~LK_ _ _ _ _ _ _~~______________~r---l
SEQ.
DATA OUT
(SA·SH)

L----.._

MIN. HOLD

SEQUENTIAL WRITE
~LK

MAX 150 ns

,-

h WS'

~~~~E 1Il1l1l1lt

I

JOIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

rTT1rrTirT71rrr;TTT~..-------------------

SEQ. REAO------------:\il

~~~:HfUT

1~lllllllllllllllltK

L340nS-J
MAX.

---I

80 ns
MAX.
It
)
pE

RANDOM READ DATAl
SEQUENTIAL READ DATA

t

------4.(

I

I
I

»)----

_ _ _ _ _ _ _.... 1
VALID READ DATA

SEQUENTIAL COUNTER RESET
SCLK

RST

---------------------'----1

~'r- :":"-~8~i·-L
+- ·~- -+- -fC

100 ns
MAX.
ItpD )

0 m MIN.
(tRH)

WRITE ENABLE AND WRITE SELECT TIMING
SCLK

W-DATA
(A-H)

WSEL

-------"1

SEa READ

RAN. REA1

~ ~ 'sH

'ss--l

Timing Characteristics
Parameter

Symbol

Min

Typ

Max

Unit

Random Read Access Time

tRA

380

ns

Sequential Read Access Time

tSA

430

ns

Random Read Address Setup Time

380

ns

Read Port Disable (to Hi Z)

tAS
tpD

100

ns

Read Port Enable

tpE

80

ns

WE Pulse Width
WE Pulse Delay

twp

WE Pulse Setup
SCLK Pulse Width
SCLK Frequency
Write Data Setup Time
Write Data Hold Time
Write Select Setup Time

tWEl
tWE2
tsp

170
300

300

220

325

f

tWH

100

tss
tSH

0

tRS

RST Hold Time

tRH

0

ns
ns

150

ns
ns

280

ns
ns

180

ns

MHz

1.544

tws

Write Select Hold Time
RST Setup Time

ns
ns

0

ns

SPECIFICATIONS
MaximOm Ratings
Rating

Symbol

Unit

Voltage

V

Supply Voltage

VOO

Operating Temperature Range

TOp

Oto 70

°c

Storage Temperature Range

T

·55 to +150

°c

+4.75 to +5.25

STG

All inputs contain protection circuitry to prevent damage due to high static charges. Care shoold be exercised to prevent unnecessary application of voltage outside the specification range.

Electrical Characteristics
(Voo= +5V ±5%,

vss= OV

0

T A=25 CI

Characteristic

Symbol

Input Logic "1" Voltage

V IH

Input Logic "0" Voltage

V

Output Logic "1" Voltage

V OH

Output Logic "0" Voltage

VOL

Output Source Current

Min

Max

Unit

0.8

V

V

2.0

IL

V

2.4
0.4

V

IOH

-100

p.A

Output Sink Current

IOL

400

P.A

Input Capacitance

CI

5

pF

Co

25

pF

300

mW

Output Capacitance
0

Power Dissipation (at 25 CI

POSS

D
L

DOT OR NOTCH
TO LOCATE
PIN NO.1

o

d1~

0.600 MAX
(15.24 MM)

•

O~

2.020 MAX
(51.30 MM)

J

0.155 MAX
(3.93 MM)

~m~

~~TYP~Jt. ~

(1.01) 0.040
(0.55) 0.022
(0.45) 0.018

TYP.

1.910

(48.51 MM)

1.ii9O

148.00 MM)

19 EaUAL SPACES
0.100ct. TOL NONCUM.
(2.54 MM)
NOTE:

Pin No.1 is in lower left corner when
symbolization is in normal orientation

Packaging Diagram

0.010 MIN
(0.25 MM)

SPECIFICATIONS
Maximam Ratings
Voltage

Symbol

Rating

Unit
V

Supply Voltage

VOO

Operating Temperature Range

TOp

o to 70

°c

Storage Temperature Range

T STG

-55 to +'50

°c

+4.75 to +5.25

All inputs contain protection circuitry to prevent damage due to high static charges. Care shocld be exercised to prevent unnecessary application of voltage outside the specification range.

Electrical Characteristics
0

(Voo= +5V ±5%. VSS= OV T A=25 C)
Symbol

Characteristic
Input Logic "'" Voltage

V IH

Input Logic "0" Voltage

V IL

Output Logic "'" Voltage

V

Output Logic "0" Voltage

VOL

Output Source Current

Min

Max

2.0

V
0.8

2.4

OH

Unit

V
V

0.4

V

IOH

-'00

IJA

Output Sink Current

IOL

400

IJA

Input Capacitance

CI

Output Capacitance

Co

Power Oissipation (at 25 0 C)

5

POS S

0 q1-.-L

0.600
(15.24 M'JI)

e

L

pF
mW

MAX

~

(15.11)

.~~:.::::;=::r....L...-

~TYP.~Jt

(1.01) 0.040
(1.65)
(0.55) 0.022 TYP.
(0.45) 0.018

...

1.910

(48.51 MM)

1.890

(48.00 MM)

~

19 EaUAL SPACES
0.100 ct. TOL NONCUM.
(2.54 MM)
Pin No.1 is in lower left corner when
symbolization is in normal orientation

Packaging Diagram

0.010 MIN
(0.25 MM)

0.625
0.595

~

0.155 MAX
(3.93 MM)

2.020 MAX
(51.30 MM)

NOTE:

0

25
300

--rMAX~15'87)

:0 J0'-

DOT OR NOTCH
TO LOCATE
PIN NO.1

10

pF

DOCUMENT NO. R8050D
APRIL 1979

~

PART NUMBER

R8050

,1' R~~,k~ell

,),: >. . :~:);~ - - - - - - - - - - - - . . - - - - - - - ,
~---~~---~------r_-~CHCLKF

SYNCIN>--+----r:==:'1
CLOCK>--~--_;~~~

+5 voc

r..

~~~_+-~_+~r+-----;--~SYNO~

r - - - - - + - - - + S STB
BIT 1
BIT2
BIT3
BIT.
BITS
BIT.
BIT7
BITS
ALARM

BINOUT
UNPLRA
UNPLRB

ACH
BCH
B701'TN>-----~

CCIS>------t

SBITr------t
INH

LOOP~::::::::::::::::::::::::::::~-~
Figure 1. T·1 Serial Transmitter

@

RocI

ORDERING INFORMATION
The T-1 Serial Receiver is available in two versions_ With the
standard commercial version, R8060, data will be stable within
900 ns after the bit clock. With the selected version, R8060A,
data will be available within 600 ns after the !;lit clock.

.!."
>---C:> IGNOI

VOD>---e:::::>

"'7

vSS

f'11

--t,,=,~--1

8;
:

rr _-_-_-_-_-_

I
CHANNf l

~! J ~~~A
COINH

r!-P~17_ _ _ _ _ _-f....L..J~~'IT-'I

Extracts 8-bit parallel channel data

a

Provides timing signals to capture and synchronize channel and

a

Monitors and detects

;;;;, "
SYNCEN~P'tO===~f=~~~~~~~~

frame information

_.
----

Errors in signaling bit pattern
Loss of frame sync
Loss of carrier
Remote alarm reporting

•

Single 5V supply

a

LSTTL Schottky compatible

t:~Rockwelllnternat'onal Corporation 1981 .
All Rlytlls Reservpd
Printed In USA

<
m
::D

-

-

FEATURES
Synchronizes serial T-1, 02 or T-1, 03 signals in less than 5 ms_

m

o
0)
o

Timing relationships are given in figures 3 through 5.

a

m

n

::D
CO

The Rockwell T-1 Receiver chip operates on a single 5 volt supply
and directly interfaces to the low power TTL Schottky logic
family_ The Receiver is packaged in a 28 pin dual in-line (DIP)'

a

r::D

TESTI~

SHIT

SiGF'R

tlFAVE OPENI

Figure 1.

SHAlHM

R8060 Block Diagram

SpeCifications subJect to
change without notice

Document No_ R8060D
Rav_ 2. May 1981
.

T-' RECEIVER INPUTS

CHCLK - CHANNEL CLOCK

Any input ~O.BV = LOGIC 0, LOW, ZERO. Any input 2:2.0V =
LOGIC 1, HIGH, ONE. A transition from a low level to a high
level is called a rising edge, while the converse is true for the
falling edge.

The rising edge of CHCLK indicates a change of parallel output
channel data. CHCLK is four TCLKS high then four TCLKS low
except for when an "F." or "S" bit is received. Then CHCLK
stretches to five TCLKS high and four TCLKS low. Refer to
Figures 3 and 4.

TDATA: UNIPOLAR T-l-D2, T-l-D3 SERIAL DATA INPUT
CHSYNC: CHANNEL SYNC
Unipolnr T-l Data is docked in on the falling edge of TCLK_
Thereafter, TDAT A is processed on the rising edge of TCLK_
TDAT A must be stable 100 ns before and remain stable 100 ns
after the falling edge of TCLK.
TCLK: T-' CLOCK
Typical clock frequency is 1.544 MHz. Maximum clock frequency
is 1.B5 MHz. The T-l bit period is bounded by the rising edges of
TCLK_
SYNCEN: FRAME SYNCHRONIZATION ENABLE
Provides a means to disable the automatic resync search initiated
by a FRAME ALARM condition. If the SYNCEN signal is low,
the synchronization function is inhibited and remains inhibited
until SYNCEN transitions high. SYNCEN must be stable 200 ns
before the rising edge of FRALRM, in order to inhibit the synchronization function.

Channel Sync occurs one time in a 24 channel period, making it
suitable for synchronizing external counters to the T-l Frame
rate. CHSYNC goes low one TCLK period before the falling edge
of CHCLK at channel 24 date sample time. CHSYNC returns
high 1 TCLK period after the next rising edge of CHCLK. Refer to
Figures 3 through 5.
TESTO: ROCKWELL DEVICE TEST OUTPUT
Designed to aid in Rockwell device testing. No connection required
for normal operation.
WIHBT: WRITE INHIBIT
WI HBT covers the parallel channel data transition period. WIHBT
is suitable for clocking or strobing channel data into external
memories. WIHBT is high for two TCLK periods, beginning one
TCLK period before the rising edge of CHCLK. Refer to Figures 3 and 4.

MR: MASTER RESET
MAXCNT: MAXIMUM COUNT OF 386 MODULUS
Master Reset, when low, performs an initialization dear of the
T-l R~ceiver; SBALRM and CALRM are reset to low levels while
FRALRM, CHCLK, WIHBT and CHSYNC are set to high levels.
Frame synchronization search begins on the rising edge of MR
provided that SYNCEN signal has been high for 200 ns. Minimum
pulse width is one T-l dock period.
CDINH: CHANNEL DATA INHIBIT
Provides a means to disable channel data bit outputs. When at a
high level, CDINH forces channel data Bits 1 through 7 high.
Bit B, the least significant channel data bit, is not controlled by
CDINH.
TESTI: ROCKWELL DEVICE TEST INPUT
Used only for Rockwell device testing, no connection to TESTI is
required for normal operation.
VSS, VDD: GROUND AND POWER
VDD = +5.0 ±. 0.25 VDC
VSS = Ground, 0 VDC

MAXCNT is low for one TCLK period, marking the completion of
a two-frame period corresponding to the expected receipt of an
F-bit at the TDATA input. Ref~r to Figures 4 and 5.
SBCLK: S-BIT CLOCK
SBCLK will be high during the S-Bit frame and low during the
F-bit frame. The transitions will occur within 300 ns after the
rising edge of TCLK as channel 24 data is being transferred to the
parallel channel outputs. Refer to Figures 3 through 5.
S-BIT: SIGNALING BIT OUTPUT
The S-Bit output monitors the previous S-Bit received which
occurred two frames before the receipt of the current S-Bit.
An S-Bit output transition occurs one TCLK period after the
rising edge of SBCLK.
During a signaling frame (SIGFR is loW), frame 6 or" A" highway
signaling is identified by S-Bit output being low. If S-Bit is high
during a signaling frame, frame 12 or "B" highway signaling is
identified. Refer to Figures 3 through 5.
SIGFR: SIGNALING FRAME

T-' RECEIVER OUTPUTS
Low Power TTL Schottky - compatible
"1"::? 2.4 Vdc; "0" ~ 0.4 Vdc
CMOS - 12 K n pullup to VDD required.
COB 11-8): CHANNEL DATA BIT 1 THROUGH 8
Bit 1 is the sign bit, Bit 2 is the most significant bit and Bit B is
the least significant bit. If CDINH is low, new parallel channel
data becomes valid within 200 ns after the rising edge of CHCLK
and remains valid until the next rising edge of CHCLK. If CDINH
is high, channel data Bits 1 through 7 are forced to a high level.
Bit B, the least significant bit, is not controlled by CDINH. Channel data Bits 1 through 7 are enabled or disabled within 300 ns
(RB060) or 150 ns (R8060A) by CDINH. Refer to Figures 3
through 5.

SIGFR identifies frame 6 or 12 when low. If the sequence of five
consecutive received S-Bits is either 0111 X or 1 XOOl lIeft to
right, as received), SIGFR shall go low after the rising edge, but
at least 375 ns before the falling edge of WIHBT corresponding to
channell data sample time. S'i'G'F'R returns high one frame later
(193 bits). Refer to Figures 3 through 5.
SBALRM: S-BIT ALARM
SBALRM goes high if the sequence of five S-Bits received contains
four consecutive ones (01111), and remains high until three consecutive "zero" bits are preceded and followed by a "one" S-Bit
(10001). The actual transition of SBALRM output occurs after
the rising edge, but at least 375 ns before the falling edge of
WIHBT corresponding to channell data sample time.

B2ALRM: BIT 2 ALARM

C)

B2ALRM goes high, detecting a remote alarm condition, if 255
consecutive channel data samples are received with Bit 2 low.
B2ALRM returns low upon the receipt of any channel sample with
Bit 2 high.

D)

An F-Bit is received which ;s not the inverse of the last
F-Bit and the same condition also occurred two or three
or four F-Bit frames earlier.
Within 250 ns after the falling edge of CALRM, (CALRM
being reset by high level TDATA bit).

CALRM: CARRIER LOSS ALARM

FRALRM goes low upon completion of the synchronization
function or within 250 ns after the rising edge of CALRM_ (Carrier loss condition during frame synchronization function).

A carrier loss is detected and CALRM is set high if 31 consecutive low level TDATA bits are received. CALRM is reset low,
FRALRM is set high and frame sync search begins when the first
TDATA high level is received.

OUTPUT CLOCK SIGNALS DURING FRAME
SYNCHRONIZATION FUNCTION

FRALRM: FRAME ERROR ALARM
FRALRM detects an out-of-frame condition.
high if:
A)
B)

FRALRM goes

The framing synchronization function is in progress.
Within 250 ns after the falling edge of MR.

Following the Declaration of Frame Sync loss (FRALRM goes
high). output signals will continue normally for a two-frame
period with the exception of CHSYNC, which has the above
mentioned second frame sync pulse inhibited. Following the twoframe period CHCLK, CHSYNC, and WIHBT are held high until
frame sync has been located, as indicated by the falling edge of
FRALRM. With typical data patterns, frame synchronization takes
less than five milliseconds_ See Figure 2.

/FRAMESYNC
FRALRM------Jr--------------------------------------------~I~

II-...f - - - - 2
CHSYNC

________________

~I

FRAME PERIOD----....;. .

~~

_

..J~fl-----------.L....Jr-----

WIHBT

Figure 2. Signal Relationship During Frame Alarm and Search for Resynchronization

- - - F BIT FRAME
CH24
,

INPI~6~:~~ I

1

I

I

S BIT FRAME

..

±

CLOCKEO OATA 11 I

164 1 32 1 16 1 8

±

------CHl

I

I

4 I 2 11

IB~T

1641321161 8 I 4 I 2 11

I

,.......- - - - . . . . . ,

±

IB~T I

1641321161 8

±

I I
4

1641321161 8 I 4

I

I

±

164 1 32

2 11 I

± 1 64 1

2 11

TCLK 11.54 MHZI

CHCLK

WIHBT

----JI

L..--_ _

SBCLK

SBIT

________________

~x~

CHANNELDATA~I...____
CH_2_3_0_U_TP_U_T_D_A_T_A__~X\..
. .

PARALLEL OUT - - - "

__________________

_____

C_H_24_0_U_T_P_UT
__
DA_T_A_______ ~
~

Figure 3. Signal Relationships at Beginning of FS Frame (S-BIT)

_

FBITFRAME _

SBITFRAME
CH24

,

INPI~6~~~ 11

I±

CLOCKED DATA 11 I

CHl

..

1 64 1 32 1 16 1 B

±

I

I

4 I 2 11

IB~T

1641321161 8 14 12 11

I

,.......- - - - - - . ,

±

IB~TI

1 64 1 32 1 16 1 8

I I
4

± 1641321161 B I 4

I

I

±

164 1 32

2 11 I

± / 64 1

2 11

TCLK 11.544 MHZ I

L--_----II

CHCLK

WIHBT

-----JI

L..--_ _

SBCLK

SBIT

•

NO CHANGE

u
CHANNELDATA~,
DA_T_A_______~
~
--1'L___C_H_2_3_0_U_TP_U_T_D_A_T_A__--JX.
. ______C_H_24_0_U_T_P_UT__

PARALLEL OUT

Figure 4. Signal Relationships at Beginning of FT Frame (F-BIT)

FRAME SYNCHRONIZATION
BIT (F BIT) PATTERN

SIGNALING SYNCHRONIZATION
BIT (S BIT) 'PATTERN

FRAME NO.

SBCLK

~IT~~

________________________~

(OUTPUT)
SIGFR

u

u
FRAME

u

u

u

= 24 TIME SLOTS = 193 BITS - 125J.lS
= 5.18J.lS ONE BIT", 648 NS

TIME SLOT

MULTI FRAME - 12 FRAMES - 1.5 MS.

F BIT (F ) FRAME ALIGNMENT SIGNAL
T
(ODD·NUMBERED FRAMES)

S BIT (FS) MUL TIFRAME ALIGNMENT SIGNAL
(EVEN·NUMBERED FRAMES)

FRAME

FIRST BIT

FRAME

FIRST BIT

1

1

2
4
6
8

o
o

3
5
7
9
11

o
1
o
1
o

10
12

Figure 5.

1
1
1

o

Multiframe Signal Relationships

Table 1. Output Propagation Delay Worst Case, From Rising Edge to TCLK
OUTPUT
CHCLK
CHSYNC
WIHBT
MAXCNT
SBCLK
SBIT
SIGFR
SBALRM
B2ALRM
CALRM
FRALRM
COB (1-8)

MAX DELAY (NS)
300
300
300
300
300
400
475
475
450
300
900 (R8060)
600 (R8060A)
400

•

SPECIFICATIONS
Maximum Ratings
Symbol

Rating

Voltage

Unit

+4.75 to +5.25

V

Supply Voltage

V

Operating Temperature Range

TOp

o to 70

°c

Storage Temperature Range

T

-55 to +150

°c

DD

STG

All inputs contain protection circuitry to prevent damage due to high static charges. Care should be exercised to prevent unnecessary application of voltage outside the specification range.

Electrical Characteristics
0

V DO; +5V ±5%. T A; 25 C)
Symbol

Characteristic
Input Logic "1" Voltage

V

Min

IH

Input Logic "0" Voltage

V

Output Logic "1" Voltage

V

Output Logic "0" Voltage

VOL

Output Source Current

IL

Max

2.0

V

-0.3

0.8

DD

+ 0.3

2.4

OH

Unit
V
V
V

0.4

V

IOH

-100

~A

Output Sink Current

IOL

400

~A

Clock Freque,l1cy

TCLK

1.85

MHz

Input Capacitance

C

5

pF
pF

mW

I

Output Capacitance

Co

25

Power Dissipation

P

550

DSS

I

(,5501
(,530)

L,;;,...,.,..~"""""""'.......-.rTT"~......,.J~
(.160)

1-'tT1r=:I:r:1-

UIlt(065) UII ij_ I I ];\T L(700)-..j
~ I~~~~ ~ \~ (~)
__

(0231 032 REF ~
(.015)
(.090)

(150) (060)
1.125) 1.020)

Packaging Diagram

~
(0081

FILTER
PRODUCTS

•

-

•

-

.

Rockwell-·Coll ins
Disc-Wire
Mechanical Filters

'1'

Rockwell

•

Table of Contents
Section
1.0
1.1
1.2
2.0
2.1
2.2
3.0
4.0
5.0
5.1
5.2

5.3
6.0
6.1
6.2
6.3
6.4

6.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3

Page
Introduction ......................................................................... 1
Filters Using Magnetostrictive Transducers ............................................ 2
Filters Using Piezoelectric Transducers ............................................... 2
Design Considerations ............................................................... 2
Disc Resonators ..................................................................... 2
Mechanical Coupling ................................................................ 3
Practical Design Limits ............................................................... 4
Enclosure Styles ............................. ,....................................... 6
Application Guidelines ............................................................... 8
Magnetostrictive Transducers ........................................................ 8
Piezoelectric Transducers ............................................................ 11
Application Conclusions ............................................................. 11
Disc-Wire Filter Characteristics ....................................................... 12
Effects of Terminating Circuits ....................................................... 12
Group-Delay Response .............................................................. 14
Dynamic Range and Power Level ..................................................... 16
Intermodulation Distortion ........................................................... 16
Spurious Responses ................................................................. 19
Filter-to-Filter Variations ............................................................. 19
Stability ............................................................................. 21
Aging ............................................................................... 22
Reliability ........................................................................... 23
Environmental Effects ................................................................ 24
Temperature Effects on Center Frequency, Bandwidth, Loss, and Ripple ................ 24
Shock ............................................................................... 25
Vibration ............................................................................ 25

Rockwell-Collins Disc-Wire Mechanical Filters
1.0

I ntraduction

Disc-wire mechanical filters consist of metal disc resonators that are coupled together by wires. As shown in
figure 1A, three basic elements comprise the filter structure: (1) magnetostrictive or piezoelectric transducers, used for converting electrical signals into mechanical vibrations; (2) high 0, mechanically resonant
discs; and (3) disc coupling wires.

Disc Coupling Wire
Disc Resonator

Biasing Magnet

N~3S

~~~S

Magn etost ric t ive,-r.+-,-+-,--+-,,--+---,_
Transducer

1A. Physical Structure

Coil Losses""

/

Coil Inductance

/

Coupling Wire Analogy

SO"'C' (f;:J[~QI~f?i~}lLO'd
Resistance '"

~~ . ~
Resonating Capacity

JJResistance

Disc Resonator Analogy

1B. Electrical Analogy

Figure 1. Disc-Wire Mechanical Filter Analogy

•

1.1

Filters Using Magnetostrictive Transducers

When an electrical signal is applied to the input coil of a magnetostrictive transducer (figure 1A), an
alternating magnetic field is produced. This field then passes through the magnetostrictive rod that is
attached to the first disc. When properly biased, the rod will vibrate at the frequency of the impressed signal.
This is due to dimensional changes of magnetostrictive material that occur when being subjected to a magnetic field. The vibrating rod drives the first disc which, by means of the connecting coupling wires, drives the
next disc. Each successive disc is then driven by the preceding disc until the signal reaches the output transducer. Strains developed in the output magnetostrictive rod produce an alternating magnetic field which, in
turn, induces a voltage across the output coil.
1.2

Filters Using Piezoelectric Transducers

These filters operate in a manner similar to those described above, but a piezoelectric rod is used instead of
the coil, biasing magnet and magnetostrictive rod shown in figure 1A. The coil inductance and resonating
capacitance shown in figure 1B are replaced by the transducer static capacitance and resonating inductance,
respectively. When a voltage is applied across the input piezoelectric transducer, an alternating electric field
is produced, causing it to vibrate. The vibrations are transmitted through the disc-wire assembly in the same
manner as described in paragraph 1.1, and are converted to a voltage at the filter output. In addition to
converting energy from one form to another, the transducers also reflect the source and load resistances into
the mechanical circuit. The reflected impedances provide a termination for the filter.
2.0

DESIGN CONSIDERATIONS

The disc resonators are made from a specially processed nickel-iron-chromium-titanium alloy .. The
constant-modulus characteristic of this material minimizes frequency shifts with changes in temperature.
Figure 1B shows that the filter center frequency is determined by the disc resonator frequencies.
Several considerations are important in choosing the physical configurations of disc resonators and the
mechanical coupling for a particular filter.
2.1

Disc Resonators

It must first be determined which mode of vibration is to be used. The two modes of vibration that are generally
used in Rockwell-Collins filters are both flexure modes. The discs flex symmetrically about theircenter, similar
to the vibration of a drum head. Both vibration modes use a nodal circle, or circles, which are not coincident with
the edge of the disc. A mode with a single-nodal circle is generally used at frequencies of 200 kHz or lower,
whereas a mode with 2-nodal circles is used up to 500 kHz. Figure 2 represents a mode with 2-nodal circles.
The frequency of a disc resonator is directly proportional to thickness and inversely proportional to the
square of the diameter.

Top View

Cross Section

Figure 2. Vibration Mode Using 2-Nodal Circles

2

I

Other normal modes of vibration occur near the frequency region of interest, most of them having nodal
diameters. The primary reason for attaching transducers at the centers of the first and last discs in a filter is to
suppress these vibrations. Figure 3 illustrates four basic configurations of transducers used for this purpose.

Direct Attached Ferrite

Indirect Attached Ferrite

Alloy (End) Wire

Piezoelectric Ceramic

Figure 3. Transducer Configurations

2.2

Mechanical Coupling

The coupling inductors shown in figure 1B represent the wires which couple the disc resonators together and
also act as their physical support. Varying the mechanical coupling between the discs, in effect making the
coupling wires larger or smaller,varies the filter bandwidth. Since the bandwidth varies as a function of the
approximate total cross-sectional area of the coupling wires, it can be increased either by using larger
diameter wires or a greater number of coupling wires. It should also be noted that the physical structure
becomes weaker as the filter bandwidth is reduced, assuming a fixed coupling wire configuration is used. This
is one of the reasons why disc-wire filters are built using three basic coupling wire configurations. See figure
4.

•

Edge Coupling
(Medium Bandwidth)

Off-Resonance Coupling
(Narrow Bandwidth)

Center Coupling
(Wide Bandwidth)

Figure 4. Disc Coupling Techniques.

Notably the least obvious of the three configurations shown in figure 4 is "off-resonance coupling", used in
narrow bandwidth filters. In this scheme each alternate disc, shown shaded, is tuned so that its resonant
frequency is higher than the filter passband region. Since the off-resonance disc is a shunt tank circuit, in the
bandpass region in the filter (below the resonant frequency of the disc), it appears as a shunt inductance. This
results in a "tee" of coupling inductors between the shaded discs. The net result produces a narrow bandwidth
filter with coupling wires significantly larger in diameter than could be used without the "off resonance" discs.
3.0

Practical Design Limits

An analysis of all design considerations outlined in Section 2.0, results in definition of a set of design limits.
The center frequency vs percent bandwidth is plotted in figure 5. The horizontal axis is filter centerfrequency
and the vertical axis is filter bandwidth expressed as a percentage of center frequency. Practical limits within
which mechanical filters can be built are represented in figure 5 as the shaded area. Special filters outside of
these limits have been built, however, they are very costly.

4

10

I
f-

0

DISK-WIRE
MECHANICAL
FILTERS

~
0

1.0

f-

0.6
0.4

z
«
co
zw

0

a:
w
a..
0.10
O.

0.02'----'-'-'-_-'-_-'--'-.....
o 0
o
o
o
o 0
o
o
"ro

a;

20

0

go

(5
""0

.~

~

16

0

z

12

4t----------~

o

0.2

0.6

0.4

0.8

1.0

1.2

Normalized Frequency (FN)

Figure 16. Group-Delay Characteristics for a Chebyshev Filter with 0.1 dB Ripple.

15

•

•

6.3

Dynamic Range and Power Level

There is no practical lower limit on the dynamic range since essentially no internally-generated noise exists.
However, where vibration conditions exist, the microphonic electrical output from the filter is dependent on
the vibration frequency and on the filter type. A typical output is in the orderof-70 dB below a 100 percent, 1V
rms modulated output signal at a vibration level of 5 g's betwen 0 and 500 Hz vibration frequencies.
The upper limit of the dynamic range is the linearity of the output signal. This, again, depends on the type of
filter. A 3V rms input signal is a typical limit, although signals as high as 10V rms can be specified in some
designs before appreciable non-linearities appear. See figure 17.

4

2

6

8

Input Voltage (RMS)

Figure 17. Voltage Linearity.

6.4

Intermodulatlon Distortion

Intermodulation distortion in a mechanical filter is the result of non-linearities in the electro-mechanical
transducers. Therefore, intermodulation distortion is dependent on the type of transducer used and on the
specific transducer design. Figure 18 shows curves of third-order intermodulation products as a function of
signal level and transducer design.

16

-45
Q;

"E
0

-Om
.=
'0

.c I-.'!J
o :J

-50

-0

c: U

.- 0
Ol ...
(!lQ.

.~~

-55

iii

Q)

II:

-60

Input Level (dBm)

Figure 18. Third-Order Intermodulation Products
The intermodulation distortion test circuit is shown in figure 19. Generator F3 and the short-circuit that
bypasses the mechanical filter are used as a reference level. Generators F1 and F2 are set at frequencies in the
stopband of the filter which result in F3 falling within the passband of the filter, as shown in figure 20. To obtain
accurate results, isolation between generators F1 and F2, and proper signal levels are of the utmost
importance.

17

•

Selective
Voltmeter

I

_ _ _ _ --1I

Figure 19. Filter Intermodulation Distortion Test Circuit.

Q)

"0

:e0..
E

«

Figure 20. Third-Order Intermodulation Distortion f- roduct.

18

6.5

Spurious Responses

Disc-wire filters do not have the resonant frequ_ency overtones (nearly exact multiples) commonly found in
quartz crystals. Mechanical filters do not have adjacent flexure and radial modes which appear in some filters
as spurious responses.
With some exceptions, in mechanical filters the adjacent spurious modes are suppressed more than 60 dB
below the passband reference level. Filters in the 5 to 10kHz bandwidth range have spurious responses that
exceed 60 dB. Filters in the 40 to 50 kHz bandwidth range may have spurious reversals in the transition bands
or in the skirts of the filter response. Figure 21 compares spurious responses between filters with wire
transducers, filters with ferrite transducers and center-coupled wideband filters.

End Wire

Ferrite

O~-----'-r--------,

~-------P~-------.

Center Coupled
r---~~----~---,

Frequency (dB)

Figure 21. Comparison of Spurious Responses

6.6

Filter-Io-Filter Variations

Paragraph 6.1 made the statement that "there are almost no perfect filters". Figure 22 below shows plots of 18
production filters superimposed on top of each other. This particular filter type was designed as a lower
sideband filter for a 455 kHz carrier frequency. It can be seen that there are slight variations from filterto filter.
It is also obvious that the specification on the skirt of the filter on the carrier side of the passband is tighter than
the specification on the other skirt of the response. As a consequence, there is less filter to filter variation on
that skirt.
In general, mechanical filter specifications are written conservatively, and the average filter is well inside the
specified limits. Figure 23 clearly illustrates this point. It shows four histograms of selected parameters on a
large (10,060 unit) sample of filters built for commercial application. The consistency of performance is an
outcome of good process controls.

19

I

•

REF

-20

iii'

-40

~

c
.Q

~c

-60

.!

:(

-80

-100

Frequency (kHz)

Figure 22. Filter-To-Filter Variations

20

,

Specification
Maximum

Typical
10,000
IJ)

~

u::
z

4,000

6,000

2

3

4

5

6

8

I

I
I
I

0
0

o

9

Insertion Loss (dB)

10,000
IJ)

~
u::

'0
ci

z

8,000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Passband Response Variation (dB)

10,000
Specification
Minimum

6,000

t

Typical

4,000

I
I
I

2,000

Specification
Maximum

8,000

I
I

6,000

'0
ci

10,000

I
I

8,000

Typical

8,000

tI

6,000

I

Typical

4,000

4,000

2,000

2,000

1.51.651.80 1.952.102.252.402.552.702.85

3.7

4.1

3 dB Bandwidth (kHz)

4.3 4.5

Specification
Maximum

4.7 4.9 5.1

5.3 5.5

60 dB Bandwidth (kHz)

Figure 23. Typical Production Results.

6.7

Stability

The stability of disc-wire mechanical filters depends on the characteristics of the discs themselves. Collins
disc-wire mechanical filters use an iron-nickel-chromium-titanium alloy (Ni-Span C) as the disc material. The
titanium in the material allows the alloy to be heat-treatable. This means that the parabolic resonant frequency
vs temperature curve can be shifted along the temperature axis to meet a precise filter specification. Figure 24
shows the frequency shift characteristics of a typical disc resonator at 455 kHz. To approximate the frequency
shift at other frequencies, simply scale by the ratio of the new frequency to 455 kHz.
Example:
f _
(kHz)
_0
__

M fo(kHz)

455

21

(for 2-nodal circles)

•

100

I

I

80

I

Frequency = 455 kHz
N

~
..c

/

60

(J)

/

>.
u

c

Q)

I

I

I

I

/

40

,/

:J

C7

//0

~

u.

/

20

//
~

",-",,-"

0
-50

-40

-30

-20

-10

o

+10

+20

+30

+40

+50

+60

+70

+80

+90 +100

Temperature (0 C)

Figure 24. Disc Resonator Frequency Shift Characteristics

The one-sigma limits resulting from a variation in the heat treatment process are shown in figure 24 as dotted
lines. Where single-nodal circles are used (normally below 200 kHz), the frequency shift equation must be
multiplied by 1.5.
6.B

Aging

Frequency stability of mechanical filters with age is directly related to the resonator mode and to the
characteristics of the material. A good estimate of center frequency shift, with age, is 50 ppm over a 20-year
period or a 25 Hz shift of a 500 kHz center frequency.
The curves in figure 25 show the effect of accelerated aging at the 10 dB points of a typical 500 kHz filter having
a bandwidth of 3 kHz.
Accelerated aging was accomplished by subjecting the filter to temperature cycles for9 hours at 25°C and for
15 hours at 90°C. The cycles were repeated daily for a period of eight months.

22

30

i
CD
-0

20
10

~
~

0

:::l

-10

FO

-20

BW

a.
a.

<:J

N

;;.
CD

20

= 500 kHz
= 3 kHz

Accelerated Aging

(8-Month Period)

Temperature

25°e ( 9 Hrs)
90 0 e (15 Hrs)

10

-0

~

0

~
0

-10

--l

<:J

-20

2

4

3

6

8

Time (Months)

Figure 25. Effects of Accelerated Aging.

6.9

Reliability

Disc-wire mechanical filters are, by design, very reliable components. A collection of field service data is
shown below:
Field Data: 277,000 Units
2.5 Years
374 Failures
MTBF
277,000 x 2.5 x 365 x 24
374
1.622 x 107 Hours

= 61.6 x 10-9 (61.6 FIT)

23

•

7.0

ENVIRONMENTAL EFFECTS

This section describes the environmental effects on disc-wire mechanical filters due to temperature, shock
and vibration.
7.1

Temperature Effects on Center Frequency, Bandwidth, Loss and Ripple

Disc-wire filter designers use design techniques with compensating factors. These factors minimize center
frequency shift and bandwidth of the filter with a change in temperature. Table 1 compares the variations of fa
and BW 3dB obtained from 10 single sideband filters at 450 kHz. All values shown are in Hz.
~f

M

f
a
at 25°C

a
at -40°C

a
at +85°C

Average

451742

+48

+46

Minimum Value

451681

+39

+37

Maximum Value

451803

+56

+59

Table 1. Variations of fa and BW

~BW3dB

BW
3dB
at 25°C

3dB

~BW3dB

at -40°C

at +85°C

3037

-1.3

-9.4

2871

-23

-26

3138

+13

+2

vs Temperature.

Table 2 shows effects of temperature change on a number of parameters for a sample of upper sideband filters
designed for a 455 kHz carrier frequency. This filter was designed for a commercial application, so that the
operating temperature range was not as great as the filter referenced in Table 1. The Table 1 filter is used in a
military application.

+25°C
Parameter

Average Value

-30° C to +50° C
Minimum Value Maximum Value

Maximum ~
from 25°C

Response Variation in dB

0.88

0.4

2.1

1.22

Insertion Loss in dB

2.7

2.4

4.1

1.40

3 dB Bandwidth in Hz

2152

2070

2230

82

60 dB Bandwidth in Hz

4342

4210

4480

138

Frequency in kHz of Low Side
3 dB Point

455.392

455.350

455.450

58

Frequency in kHz of High Side
3 dB Point

457.541

457.450

457.640

99

Frequency in kHz of Low Side
60 dB Point

454.305

454.170

454.400

135

Frequency in kHz of High Side
60 dB Point

458.624

458.480

458.770

146

Table 2. Temperature Variations ..

24

A typical variation of insertion loss with temperature is ± 1.0 dB over a temperature range of -10°C to +70°C.
Changes in passband ripple, due to changes in temperature, depend mainly on the transducer design. Filters
using piezoelectric transducers use internal components designed to optimize the response and therefore
display better characteristics over temperature changes. A typical change in ripple over a temperature range
of -40°C to +85°C is less than 1 dB. Most filters using ferrite or wire transducers have twice the amount of
ripple of their actual room temperature values, over this same temperature range.
Temperature variations in center frequency, bandwidth, loss and ripple are temporary. The filter is restored to
its original operating condition when the temperature is restored to +25° C without measurable hysteresis.

7.2 Shock
To prevent damage from shock, the mechanical filter structure uses an internal resilient rubber shock mount.
This shock mount enables the average SSB filter to withstand greater than 50 G, 11 msec shocks without
changing the filter response. Many mechanical filters can withstand 75 G's of shock before permanent
damage occurs. See figure 26 for a comparison of shock level versus filter bandwidth. Note that filters using
off-resonant discs have narrow bandwidths, and filters using the mini-single-nodal circle have wide
bandwidths.
1oor-------------------------------------------~--------------------------__,

~
75

Mini-One
Nodal Circle

Off-Resonant Disks
2-Nodal Circle
fJ)

Q.
~Ql 50

....J

Conventional
2-Nodal
Circle

.>£

U

~

Center Coupled
2-Nodal Circle

2

en

25

Fo = 450 to 500 kHz

°3LO-0--------------10LO-0-------------3-0LO-0-------------10-,OLO-0-------------3-0~,OO-0------------~10~0~,OOO
Bandwidth (Hz)

Figure 26. Shock Level vs Filter Bandwidth.

7.3 Vibration
The internal shock mount that so effectively isolates the filter from shock is also excellent for suppressing
vibration. All Collins disc-wire mechanical filters exceed MIL-STO-202. Method 201.

25

•

I

Collins
low Frequency
Mechanical
Filters

'1'

Rockwell

•

Table of Contents

Page
1.0
1.1

1.2
1.3
1.4

2.0
2.1
2.2
2.3
2.4

2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4

Introduction to Low Frequency Mechanical Filters
Practical Design Limits
Enclosure Styles
Application Circuits
Applications for Low Frequency Mechanical Filters
Characteristics for Low Frequency Mechanical Filters
Center Frequency Vs. Termination
Center Frequency Vs. Input Voltage Level
Differential Phase Vs. Input Voltage Level
Input to Output Level Linearity
Group Delay Response
Impulse Response
Spurious Responses
Aging
Reliability
Environmental Effects
Temperature Effect on Center Frequency. Loss
and Bandwidth
Shock
Vibration
Moisture Resistance

1
1
6

6
8
9
9
10
10
10

11
13
15

16
16
16
16
17
17
20

Collins Low Frequency Mechanical Filters

1.0 Introduction to Low Frequency Mechanical Filters
The low frequency mechanical filter consists of two metal alloy bars bonded to piezoelectric ceramic transducers and coupled mechanically with wires which also act as the supporting structure. See figure 1. The
bars are made out of a constant modulus nickel-iron alloy whose temperature coefficient is adjusted by heat
treatment to help compensate for the high positive temperature coefficient of the ceramic. The composite
resonators operate in the flexure mode with wires coupling the bars torsionally. Figure 2 shows the equivalent circuit of the filter.
1.1

Practical Design Limits

The mechanical filter may be designed as a Chebyshev, Butterworth, TBT, Linear Phase or Bessel filter in
either a 2, 3 or 4 pole (resonator) configuration. The Chebyshev (equal passband ripple) designs are available with ripple values ranging from .01 to 1.5 dB. Typical response curves for these designs are available
in standard filter handbooksJ

Out

In

NI-FE Alloy Bar

Figure 1. Low Frequency Mechanical Filter

G. Hansell, Filter Design and Evaluation, Van Nostrand Reinhold Company, 1969.
Howard W. Sams, Reference Data for Radio Engineers, 1968.
A. Zverev, Handbook of Filter Synthesis, John Wiley and Sons, Inc., 1967.

•

The practical design limits for low frequency mechanical filters are illustrated in figure 3. The fractional
bandwidth (BW 3dB /F 0) varies from .2% to 1.5% over a center frequency (F Q) range of 3.5 to 70 kHz.
The fractional bandwidth is further influenced by the environmental restrictions (shock and vibration) and
the type of design, such as Chebyshev or Bessel.
Typically, Chebyshev designs having fractional bandwidths between .2% and 1.5% can be achieved for shock
levels to 100 G's and vibration levels to 10 G's.
An attenuation comparison for .25 dB ripple Chebyshev filters is presented in figure 4 and a linear phase
equiripple (.5° error) design in figure 5.

Coupling Wire Analogy

Load
Resistance

Figure 2. Equivalent Circuit of A low Frequency Mechanical Filter

2.0
1.5
1.0
~

-ti

.B

"0

.6

.~

li

CD

E
II>
u

&

.4

.2

Frequency (kHz)

Figure 3. Practical Design Limits of Low Frequency Mechanical Filters

2

Shape Factor

o1r---------~2r-----~3r----4r-~5r--6r-;7--8r-~9-1rO-----------2rO~

10

IiJ

~

c
0

20

.~

:::J
C

~

~

30

40r---------~r_~~_r~~~--~_r~--~~+_----------~

Figure 4. Attenuation Comparison for .25 dB Ripple Filters

3

•

•

Shape Factor

oor-------------~2r_-------3r_----~4-----5r_--6r_~7--~8--~9__10

10~----~~~~--+---------~----~----+---4---+--4--4-~

0

Figure 5. Attenuation Comparison for Linear Phase Equiripple (.5 Error) Filters

The Chebyshev designs are primarily for tone selectors while the linear phase designs are used where phase
or FSK modulation is transmitted. The linear phase designs have 0 dB ripple and a low ringing impulse
response (4% ringing for a 2·Polel. Typical mechanical filter specifications are tabulated in table 1. The
values are interrelated (and therefore not independent) and are a function of the type of design. i.e. a very
narrow filter would probably not have a high level shock specification.

Table 1. Mechanical Filter Specifications and Characteristics

Specifications

Minimum

Typical

Maximum

Center Frequency (F 0)

3.5 kHz

70 kHz

Fractional Bandwidth BW3 dB

0.2%

1.5%

1

4

~
Number of Poles (Resonators)
Characteristics

Minimum

Typical

Maximum

Insertion Loss

1 dB

3.5 dB

10 dB

Terminating Resistance

2 Kn

20 Kn

50 Kn

Temperature Coefficient of F0

± 3 PPMtC

± 10 PPMtC

± 25 PPMrC

500 PPMtC

Temperature Coefficient of BW 3 dB
Passband Ripple

OdB

0.2 dB

1.5 dB

Vibration (10 Hz to 2000 Hz)

lG

10 G's

15 G's

Shock

15 G's

100 G's

1500 G's

0

Differential Phase Vs. I nput Level
(-70 to -10 dBm)

0.5

Volume

0.51 N3

0.5

0

0.51N 3

0

2

1.01N 3

5

•

•

1.2

Enclosure Styles

There are four enclosures currently available with low frequency mechanical filters. Three of the enclosures (PA, FS, and LC) are plastic, the fourth (FP) is a hermetically-sealed metal case. It is recommended
that the' LC' case be used whenever possible as it is significantly lower in cost.
Case style 'PA' is a plastic version of the 'FP' enclosure. It is normally not available except under special
ci rcu msta nces.
The 'FS' enclosure is used only on 2-Pole filters which have a 'fail-safe' requirement, i.e. the input can at no
time short circuit to the output. This type of filter is normally found in railway systems, people carriers and
automated rapid-transit trains. The enclosure is rated for a-20° C to +95° C environment and is not
hermetically-sealed.
The 'LC' case is made of plastic and is ultrasonically sealed. It is rated for a -55°C to +95°C environment.
Filters in these enclosures have been tested with two consecutive cycles of Mil-Std 202, method' 06 for a
total time of 20 days at 90% humidity. During the 20 day period filters are thermally-cycled from _10°C
to +65° C and intermittently vibrated at 9 G's. This test is designed to evaluate the resistance of component
parts to tropical environments. Although the cases and the filters withstood this environment, they may not
be able to withstand extremely long period environments because of the permeability of the plastic case.
However, if the user provides an additional moisture barrier such as 'post-coat', filters in this enclosure will
pass a more rigorous environment.
The alternative enclosure for tropical or high altitude service is the 'FP' case style. This is a cold-welded
metal enclosure with glass to metal terminal seals. The filters in this package are rated for a -55°C to +95°C
environment and guaranteed to meet the moisture resistance test. A disadvantage is that they are several
times more expensive than the 'LC' enclosure.

1.3 Application Circuits
The following constraints are suggested limitations on the application circuit. Although these values may be
exceeded without damage to the part, the filter will operate in a non-linear portion of its spectrum or will
not meet the specifications.
Signal input level (across the terminals):

1 Vrms

DC voltage across the terminals:

50VDC

Source and load termination:

.± 5%

Stray capacitance across the input/output terminals to ground:

50 pf Max

The application circuits of figure 7 demonstrate the use of bridging capacitors (C" C 2 ) which are used to
convert a monotonic response to an elliptic function response. Bridging the filter with a capacitor between
the input and output terminals provides the attenuation poles (transmission zeros) shown in figure 4. This
capacitor is typically about 30 pf in value. Although there is a substantial improvement in the filter's shape
factor (the ratio of the bandwidth, at a specified attenuation level to the 3 dB bandwidth) the disadvantage
with this technique is that the attenuation level in the stopband of the filter decreases as the bridging
capacitance is increased. See figure 4 for an illustration of a 2 Pole - 2 Zero design.
A method used for realizing greater performance from a mechanical filter and still maintain a high stopband
attenuation level is to cascade two or more units. This method results in an addition of the attenuation
levels of each filter at any specific frequency.
The cascading is accomplished by using an active network to prevent interaction between the filters. The
network could be either a transistor buffer amplifier or an Op-Amp. See figure 7.

6

Case Style FS (Plastic)

Case Style PA (Plastic)

i 1 . 6 2 Max _ _ ,

[

Jx"

D

L_-----....,030!. .0lD

,tr

)lJ

~~x (

(

-.

U~·25!. .03

°u

U

I•


u
c

11>

::l

g-

2

Il:
~

c

c3
'0
c

0
0':;

co

0;

C'l

Deviation of Termination - %

Figure 8. Variation of Filter Center Frequency with Resistive Termination

9

•

•

2.2 Center Frequency Vs. Input Voltage Level
Low frequency mechanical filters remain very linear with drive level up to 0.5 v, at which point they rapidly
become non-linear. See figure 9. The shift in the center frequency at a ten volt level is enough to move
some filters out of specification. AI~o, along with the non-linear effects, excessive drive level causes time
dependent changes in the ceramic material. These changes cause the center frequency of the filter to be
lower after being driven at a high voltage level. Once the drive level is reduced the filter response begins
to return to its original frequency.
2.3 Differential Phase Vs. Input Voltage Level
The differential phase at the center frequency of a linear-phase eqLiiripple (.5° error) filter is 0.5 degree over
an input level variation of 60 dB, namely -10 dBm to -70 dBm. The change in phase is due to a center
frequency shift caused by the nonlinearity of the input transducer.
2.4 Input to Output Level Linearity
The linearity of the output signal level to the input level at the filter center frequency is 0.1 dB over an
input voltage range of 60 dB (-10 dBm to -70 dBm).

0
-50

e-o.

.e-...

-

-100

>
c

-150

:.c

(I)

u

~

::J

g-

u:

-200
-250
-300
.001

.01

.1
Input Level (Volts)

Figure 9. Variation in Center Frequency with Input Voltage Level

10

10

2.5 Group Delay Response
The approximate group (envelope) delay for a mechanical filter can be determined from figures 10, 11, 12
and 13 as well as the following equation.

NGD

Group delay (sec)
at center frequency

1T

BW 3 dB

NGD = Normalized Group Delay from figures 10, 11,12, or 13
BW 3 dB = 3 dB Bandwidth (in Hz)

Example:
The group delay for a 2 Pole .1 dB Chebyshev filter which has a 40 Hz bandwidth is
N=2
BW 3 dB = 40 Hz
NGD from figure 12 = 1.4 sec
Group delay = ~ = .011 sec = 11 msec
1T

3

40

r------------------,------------------,,-----------------~------------~

3.0

2.0

1.0

Normalized Frequency

Figure 10. Group-Delay Characteristics for Linear Phase (Phase Error =

11

.5') Filter

•

-

---

~

~ .-

~

-

J
2

1
I

I

I

0.2

0.4

I

0.8

0.6

-~
r-......

1.0

1.2

Normalized Frequency

Figure 11. Group·Delay Characteristics for Chebyshev Filter with 0.01 dB Ripple

U

B



(/)

-

~

~

a.
::l

o

---

4

l;

]

r-

iO

E

o

z

0

I

o

I

--..

~
2

I

1
I

~

-

I

O.B

0.6

0.4

0.2

y ~~

1.0

1.2

Normalized Frequency

Figure 12. Group-Delay Characteristics for Chebyshev Filter with 0.1 dB Ripple

B~-------r--------.--------''--------'--------'--------'

OL-__

o

~

__- L_ _

0.2

~L-

__

~

0.4

__- L_ _

~~

_ _~_ _- L_ _~~_ _~_ _- L_ _~

0.6

O.B

Normalized Frequency

Figure 13. Group-Delay Characteristics for Chebyshev Filter with 0.5 dB Ripple

1.0

1.2

2.6 Impulse Response
Figures 14 thru 17 can be used to approximate the impulse response ringing value of a mechanical filter.
A definition of ringing is the ratio of V 1IV 2 in percent.

v,
For example:

A two-pole mechanical filter designed as a linear-phase filter has an impulse response ringing value
of 4%.
N=2
V 1 = .02 from figure 14
V 2 = .48 from figure 14
Impulse response ringing =

~
V2

X 100=·02 X 100=4.1%
.48

A three-pole .5 dB Chebyshev design has an impulse response of 21%.

0.2 f--+----,/--__----+-~__'<-r--t---

0.1

I+--+-+----+----'o,:---~-'t------I--

-0.1 ' - - - - - - - - - ' - - - - - - - - - ' - -

o

Figure 14. Impulse Response for Linear Phase (Phase Error

10

= .[)J

Filters

13

•

0.5
n • 2
0.4

0.3

0.2

0.1

-0.1 ~----------~-----------+------------~----------~--------4

-0.2

L..-_ _ _ _ _ _ _ _. _ - ' -_ _ _ _ _ _ _ _ _ _- L_ _ _ _ _ _ _ _ _ _ _ _..l...-_ _ _ _ _ _ _ _ _ ___'__ _ _ _ _- - - '

o

12

16

Time (t)

Figure 15. Impulse Response for Chebyshev Filters with 0.01 dB Ripple

0.5

r----------,------------.-----------~---------_r------__.

0.4

f---+---1I--,.--_+_-----------+-----------+_----------~------____j

0.3

~~-r~~~~~--------~------------+_---------~------~

0.2

rr~~~-+--~-~~--------+·------------+_----------_r------____j

n = 2

0.1

-0.1 ~----------_+_--------~~------------+_-----------~------~

~.2

L -__________--'-__________- L_ _ _ _ _ _ _ _ _ _ _ _

o
Time (t)

Figure 16. Impulse Response for Chebyshev Filters with 0.1 ~8 Ripple

14

•

~

12

_ _ _ _ _ _ _ _ _ ___'__ _ _ _ _ _

16

~

0.5

n • 2
0.4

0.3

0.2

0.1

-0.1 ~----------~------~~~---------+----------~------~

-0.2 '--__________'--________---1__________----1..._ _ _ _ _ _ _ _ _ _-1....______---1

o

12

16

20

Time (t I

Figure 17. Impulse Response for Chebyshev Filters with 0.5 dB Ripple

2.7

Spurious Responses

Mechanical filters have resonant frequency overtones very similar to those found in quartz crystals. These
overtones occur at mUltiples of the fundamental; the multiples are 2.4, 4.8, 7.6, 10.6, etc.
As an example, a mechanical filter designed for Omega navigation system applications at 10.2 kHz will have
spurious responses (frequency overtones) at 24.5, 49,77.5 and 108 kHz.
These overtones are inherent to the flexure mode ofvibration used in the design of low-frequency mechanical
filters. They cannot be suppressed without compromising the filter design. The odd-numbered modes, 2.4
and 7.6, are normally 50 dB below the fundamental. Suppression ofthese occurs because of the transducer
coupling method utilized to drive the fundamental mode. The even-numbered overtones, 4.8, 10.6, have
levels approximately 15 dB belowthe fundamental. These modes cannot be suppressed internally, however,
a low-pass filter can be used to reject these higher frequency modes. Another alternative is the use of a
bandpass "roofing" filter. See figure 22. The 'roofing' filter will reject both the low frequency microphonic and
the high frequency spurious responses. It should be placed after the mechanical filter i.e., the incomingsignal
should go through the mechanical filter first, then through the 'roofing' filter. In this way, the microphonic
responses are rejected as well as the spurious responses. The 'roofing' filter should be compatible with the
mechanical fi Iter; it should not affect its passband response.

15

•

2.8 Aging
Aging is defined herein as the change of center frequency with time. Since insertion loss and bandwidth do
not change an appreciable amount, they will not be considered.
The low frequency mechanical filter has four components and processes which are likely to contribute to
aging problems: the nickel-iron alloy bar, the ceramic transducer, the solder bond between the bar and
transducer and the welds that connect the coupling wires to the bars. When heat treated properly, the
nickel-iron alloy bar is very stable. Because its mass is much greater than any of the other components, the
stability of the bar helps to compensate for the instability of the ceramic and solder bond.
Since the aging characteristics of low frequency mechanical filters are dependent on the ratio of the ceramic
transducer mass to the nickel-iron alloy bar mass, the rate of aging for various types of filters is not only
dependent on the center frequency, but perhaps, to a greater extent, on the design bandwidth of the filter.
The narrower the bandwidth, the smaller the ceramic transducer need be. This means that the narrower bandwidth filters will age, as a percentage of their center frequency, less than wider bandwidth filters at the same
frequency.
The aging rate of a mechanical filter is predictable and always in the positive direction. The aging (t. f) of a
filter can be computed using the following equation, where t is the time in days, BW is the 3 dB bandwidth
in Hertz and to is 10 days, the time required to manufacture a mechanical filter.

M = .02 BW (Log ..!..)
to

For example: A 12 kHz filter which is 50 Hz wide at 3 dB after 5 years will have aged:

M = .02 (50) Log 5(365)
10
2.9

= 2 .26. z
H

Reliability

The MTBF (mean time between failures) is 3 X 107 hours. This is based on field data which was accumulated
over a period of several years.
3.0 Environmental Effects
3.1

Temperature Effect on Center Frequency, Loss and Bandwidth

Design techniques for low frequency mechanical filters utilize compensating factors which minimize the
shift of the filter center frequency with a change in temperature.
The center frequency shift vs. temperature is normally compensated to a tolerance of ±. 10 ppmt C over a
temperature range of -20°C to +65°C. The tolerance can be as high as ±. 25 ppmtC for the largest fractional bandwidth filters. The filters may be used over larger temperature ranges, such as _55° C to +95° C without any physical damage or permanent effect on the frequency response characteristics.
The variation of insertion loss with temperature is typically ±. 1 dB (with a maximum variation of ±. 1.5 dB)
over a temperature range of -20°C to +65°C. The narrower the filter bandwidth the smaller the insertion
loss variation.
Bandwidth normally changes very little with temperature in absolute terms. A typical variation for a filter
with a 100 Hz bandwidth would be 1.5 Hz over a temperature range of +25° C to +65° C. This is a bandwidth
shift of +375 ppmr C.
The variations in center frequency, loss and bandwidth due to temperature change are temporary in nature;
the filter will return to its original condition when the temperature is restored to +25°C.

16

3.2 Shock
A resilient rubber shock mount is used to isolate the mechanical filter structure from shock forces which
could cause damage. This mount allows the average filter to withstand 100 G, 6msec, shocks without a change
in the filter response. Certain mechanical filters can withstqnd 1500 G's of shock before permanent damage
occurs.
3.3 Vibration
The internal shock mount, that so effectively isolates the filter from shock, also does an excellent job against
vibration forces. The average filter will safely withstand a constant 10 G vibration level between 10 to 2000 Hz.
At approximately 15 G's the elastic limit is reached causing the filter to become permanently damaged.
Often it is not only important that a filter survive a specific vibration level, but it is also important that it
retains the proper response characteristics during the vibration. While the attenuation response shows
little change, there is some variation of phase and some microphonic effects during vibration. These are
important characteristics in applications like Omega navigation systems.
The variation of phase of an Omega filter as a function of vibration frequency is shown in figure 18. It will
be noticed that there is a peak deviation point around 400 Hz. The reason for the peak is that the entire
filter structure has a resonance at this point. This structural resonance also has an effect on the microphonic
noise level.

1.0

Unit 1

0

...
'"'"6.
0

:c
...'"
.&:
'"
Q.

Unit 2
Unit 3

-1.0
Phase Measured at Center
Frequency (11.333 kHz)
3 dB Bandwidth 60 Hz

tI)

-2.0

-3.0

10

30

aoo

100

Vibration Frequency (Hz)

Figure 18. Variation in Phase with External Vibration (10 G Level)

17

1000

3000

•

Figure 19 illustrates the levels of microphonic responses of a 100 Hz bandwidth Omega filter. These levels
were measured while the filter was vibrated at a constant 5 G level over the frequency range of 50 to 4000 Hz.
The maximum output occurred at 525 Hz at a level of -50 dBv.
In applications where these levels are intolerable, special structural designs can be incorporated into the
equipment in order to dampen the vibrations around 500 Hz. Methods such as mounting the filter near a
brace or an equipment corner, using a low-Q rubber or elastomer as an external filter mount and other
vibration suppression techniques will help in limiting the phase shift and amplitude response microphonics.
A successful technique for attenuation of the low frequency microphonic responses is the use of a high pass
filter network. These filters are placed in the signal path between the mechanical filter and the detector.
Figures 20, 21 and 22 illustrate 3 types of filters which may be used to reduce microphonic responses.
They differ in the type and number of components required. The improvement in microphonic amplitude
response as a result of using ~hese filters is presented in figures 23 through 26.
The filter circuit of figure 20 will attenuate the microphonic level by approximately 15 dB. It is a single
section consisting of 1 reactive component, however, it will not attenuate any spurious frequencies above
the filter passband.
The high-pass circuit of figure 21 consists of 3 reactive components and will attenuate only frequencies
below 9 kHz. This LC circuit provides 60 dB of rejection at microphonic frequencies.
A "roofing" bandpass filter may be used to attenuate both the spurious modes at high frequencies and the
microphonic signals at low frequencies. One circuit which may be used appears in figure 22. The complexity
of this circuit is a function of how much attenuation is required by the user, i.e., additional sections provide
greater attenuation.

40r-----------------------------------------------------------,
Vibration Level - 5 9'S Constant

-;

60

CD

~

~

-J

11000"'1~

80 -(100pv)

100

120

+

(10pv)

(1 pv)
10

Vibration Frequency (Hz)

Figure 19_ Omega Filter Microphonic Response

18

430 pf

1I

I I

Omega
Filter

?
?<;

20 Kr2

?

>

20 Kr2

Figure 20. RC High·Pass Filter

620 pf

620 pf

Omega
Filter
20Kr2

20Kr2

Figure 21. LC High·Pass Filter

Omega
Filter

Figure 22. Bandpass Filter

19

•

3.4 Moisture Resistance
The four available low-frequency mechanical filter enclosures have been tested to MI L-STO-202, method 106.
This strenuous test is used to evaluate materials which are subjected to high humidity tropical environments.
The test consists of ten days at 90-95% humidity with the temperature being cycled from _10°C to
+65° C. At the end of each 24 hr. cycle, the filter enclosures are vibrated at a 9 G level.
Two enclosures, 'LC' and 'FP', passed the test without a change in the filter response or the enclosure.
Although the all-plastic' LC' enclosure passed the test, it should receive additional moisture protection,
such as "post coat", if the filter is to be subjected to this type of environment for a long period of time.
The additional moisture barrier is necessary because most plastics are permeable to moisture, therefore,
there would be an eventual effect on the filter response. No precautions need to be taken with the all-metal
'FP' enclosure.
The plastic 'PA' and 'FS' enclosures were also subjected to the above moisture test. On these, the epoxy
seal around the cases showed signs of degradation and cracking. Moisture apparently enters the filters
through the damaged seal, however, the filter response was unchanged and the filters functioned normally.
It is not recommended that these enclosures be used in tropical environments because of the possibility of
seal failure.

40.---------------------------------------------------------------~

Fo - 11.333 kHz, 100 Hz Bw with
RC Hi·Pass Filter on the Output

-;

60

CD

.~

~

-l

80

:;
a.
:;

o

100

120 (1 pv)
10
Vibration Frequency (Hz)

Figure 23. Omega Filter Microphonic Response

20

•

40
Vibration Level - 59'S Constant

Fo - 11.333 kHz, 100 Hz BW with l-C
Hi-Pass Filter on the Output

60

80

120

I

II

(1 "V)
10

I I II I

100

1000

10,000

Vibration Frequency (Hz)

Figure 24_ Omega Filter Microphonic Response

40.------------------------------------Fo -11.333 kHz, 100 Hz BW with same
l-C Hi-Pass Filter as Fig. 24

Vibration Level - 10 9'S Constant

60

(1000"V)

80

(100~V)

>

CD

~

~

...J
:l

.9-

o

100

120

(lllv)
10
Vibration Frequency - Hz

Figure 25, Omega Filter Microphonic Response

40.----------------------------------------------------------------,
Fa - 11.333 kHz, 100 Hz BW with Same

Vibration Level - 15 9'S

60

80

L-C Hi-Pass Filter as Fig. 24

{1000"VI~
(100"V)

+

:l

a.

8- 100
120 (1 "V)
10

1000

100

10,000

Vibration Frequency (Hz)

Figure 26, Omega Filter Microphonic Response

21

•

DOCUMENT NO. FD-05
FEBRUARY 1980

'1'

FILTER PRODUCTS
DATA SHEET

Rockwell

COLLINS US8-LS8-AM MECHANICAL FILTERS

n
o

o

r-

!:
Z

10

CD

"0

en
c:
en

20

~

z
o

~

c(

aJ

30

I

r-

::>
zw

~

40

en

50

l>

w

c(

I

00

~~~

449

____-LL-__

450

451

~

452

____

~

453

____

~

__

454

~

__

455

~-L

____

456

~

457

____

~

458

__

~~

459

__

~

__

460

~~

461

s:
s:
m

n

FREQUENCY IN KHZ

J:

l>

:2

n
Rockwell·Collins Filter Products offers a complete set of mechan·
ical filters for the communication radio service. Either upper or
lower sideband filters plus a super·selective AM filter are available.
The unique design features of the original upper sideband filter are
incorporated into all three of these filters. You get the inherent
stability with time and environmental change of all Rockwell·
Collins Mechanical Filters, along with low volume prices. Here
is a very cost·effective package for the ultimate SSB and AM
radio.

The curves shown here illustrate the typical response character·
istics of the three filters. Even with the exceptional selectivity
and stability of these fine filters, they are competitively priced
in volume. Contact your local Rockwell Sales Representative and
find out how little it costs to use the best.

tion loss low. Normal welded construction is used for the filter
assembly. The result is a trio of filters that are very stable with
time and/or temperature and have the high performance charac·
teristics needed for minimum interference operations.

•

-!:4-n

m

\Nculd be 45 Hz. Custom-made ferrite transducers keep the inser-

All Rights Reserved
Printed in U.S.A.

r-

::a
en

These fj!ters incorporate quality features that have made Collins
Mechanical Filters famous. The disk resonators are made from
specially processed Ni·Span "C", so that filter frequency shift with
change in temperature is minimized. For example, over the tem·
per'!ture range of ·30 0 C to +50 0 C a typical value of total fre·
quency shift for the carrier side 3 dB point of a sideband filter

It> Rockwell International Corporation 1980

l>

Specifications subject to
change without notice

The filters were designed with the input balanced and the output
unbalanced, so that the radio designer can operate them in a balanced
modulator circuit (or any other balanced circuit). Either end may be
used as input (or output) but only one end is balanced. Both ends of
the sideband filters should be terminated with 2700 ohms resistance,
with the filter terminals shunted by 360 pf of capacitance. The AM
filter should be terminated with 12,000 ohms resistance and 360 pf
of capacitance.

DIMENSIONS (mm)

Part Numbers are:

526·9897·010, USB
526-9939-010, LSB
526-9920-010, AM

FILTER TEST CIRCUIT

FilTER

FURTHER INFORMATION
For technical information on Rockwell filter products or to discuss a
filter to your specifications, contact

c1

FOR
RS
FOR
RS
FOR

c1

Rockwell International
Filter Products
4311 Jamboree Road
Newport Beach, CA 92660

SIDEBAND FilTERS,
•
Rl
• 2700 OHMS
AM FILTER;
•
Rl
• 12.000 OHMS
All THREE FilTERS;
•

c2

•

360pf

Phone 714/833-4632 or contact your local Rockwell Representative.

TYPICAL PERFORMANCE CHARACTERISTICS:
Parameter

Filter Type

Min.

Typ.

3 dB Bandwidth

USB/LSB
AM

1.950
5.000

2.200
5.500

60 dB Bandwidth

USB/LSB
AM

Insertion Loss

USB/LSB
AM

3.5
8

Passband Response Variation

USB/LSB
AM

1
2.5

4,500
11,000

Max.

Units
Hz
Hz

5,500
13,000

Hz
Hz

8
12

dB
dB

3
3.5

dB
dB

•

DOCUMENT NO. FD-06
MARCH 1980

'1'

FILTER PRODUCTS
DATA SHEET

Rockwell

F455FD SERIES LOW-COST MECHANICAL FILTERS
Rockwell-Collins' low cost F455FD-series of Mechanical Filters
takes full advantage of advances in manufacturing techniques to
realize superior performance at a modest price for manufacturers
of SSB, AM and ON communications equipment_ An additional
saving in cost is achieved by writing worst-case limit specification
requirements which are suitable for the intended applications,
and then over-designing the filters to minimize costly inspection
and test procedures_ As an example, actual insertion loss values
are typically 5 or 6 dB, while the specified maximum is 10 dB.
Actual 6(} dB to 3 dB bandwidth ratios are typically 2 to 1 while
the specified maximum ratios range from 2.3-to-l to 3.3-to-1.
Actual response variation values are typically 1 to 1.5 dB, while
the specified maximum is 3 dB.

RECOMMENDED OPERATING PARAMETERS
All seven of the filters in the F455FD-series are designed to operate with 2,OOO-ohm source and load resistances, and need to be
parallel-tuned with a fixed capacitance, the value of which can
vary ±5% from nominal with negligible effect on the filter performance. This makes for easy and inexpensive assembly in
production radios. The signal input voltage should not exceed
2 volts RMS.
A common ground connection and effective shielding between
the input and the output must be used to obtain full advantage
of tho! Mechanical Filter's selectivity.
The filters are normally used inter-stage. Used in an IF stage of a
receiver, or the modulator stage in an exciter, the filter eliminates
the need for additional selectivity components, and permits simplified circuit design and production tuning procedures.

ELECTRICAL CHARACTERISTICS

."

Mechanical
Filter

.a::.
c.n
c.n

Ct

."

C

en

[
]~n
i~1
i h=nl
OtJ
t-.--.--,~" ..~
~ I l~mI . COO'
DO

1--0100'0008

U-02oo

t0015

- - - 2 5 3 m..

Termination circuits should be designed to eliminate DC currents
and voltages from the filter. Satisfactory results may be obtained
with current up to 2 ma DC, but in no case to exceed 3 ma DC.
DC voltage should not exceed 100 volts DC.

@2SoC

Numbers

1kHz)

(kHz)

(kHz)

('")

Shock . . . . . . . . . _ . . . . . . . . . . MIL-STD-202, Method 202
Vibration . . . . . . . . _ .. __ . . . . _MI L-STD-202, Method 201

»
Z

0

0.375

0.375

3.5

4.0

350

1.2

1.2

8.7

9.5

350

526·9691·010
F455FD-19

Maximum Ripple Voltage
@25 0 C . . . . . . . . . . _ . . . . _ . . . . . . . ___ .3.0 dB

1.9

1.9

5.4

5.9

330

Operating Temperature Range (OTR) • . . . . . . . .4.0 dB

526·9692-010
F455FD-25

2.5

2.5

6.5

7.0

510

526·9693·010
F455FD-29

Maximum Insertion Loss
@25 0 C . . . . . . . . . . . . . . _ . . . . . . . . _ .. 10.0dB

2.9

2.9

7.0

8.0

510

Operating Temperature Range (OTA) . . . . . _ . _ 12.0 dB
Minimum 60 dB Stop Band Aange .. _ . . . 445 kHz to F60L

3.8

9.0

10.0

1000

5.8

5.8

14.0

15.0

1100

!!

F60H to 465 kHz
RS and R ,±5% . . . . _ .. _ . _ . _ . . . . . . . . . . 2,OOOn
L

c_. _______._____________________________--'"
It> Rockwell International Corporation 1980
All R'ghts Reserved
Printed in U.S.A.

-

»
r-

COMMON CHARACTERISTICS:

526-9690-010
F455FD

3.8

::I:

('")

(pt)

526·9695·010
F455FD-58

o
en

s:

526·9689·010
F455FD·Q4

526·9694·010
F455FD·38

I

m

Maximum Maximum Ct, C2
60 dB BW 60 dB BW Res Cap
@ 2SDC
OTR
±S%
(kHz)

~

('")

ENVIRONMENTAL SPECI FICATIONS

0

Part and Type

m

en
ro

-f

Operating Temperature Range (OTR) . . . . . . . _10 C to +60 C
Minimum
4 dB BW
OTR

Minimum
3dBBW

m

::JJ

Specifications subject to
change without notice

!:tm
::JJ

en

APPLICATION EXAMPLES
Transistor Amplifier
-----------------~--........---+12V

15K

33K

lK

Carrier Input

60mVRMS

lK

0.1.' .---J'V'VIr+--------o-.,-i
~r~----------------~~

Signal
Input

51

-8V

Carner
Null

Mechanical
Filter

I.C. Modulalor

I.C. Amplifier

MECHANICAL FILTERS/GENERAL INFORMATION
Biasing Magnet

/'

Impedance Transforming Wire ."

COil Losses~

Sou.rce
ReSistance

/COillnductance

/couPlin g Wire Analogy

IT::

Com

'"""

Resistance

Re:::C::::::::O:

The Rockwell-Collins Mechanical Filter is a mechanically resonant
device which receives an electrical signal, converts this signal into
mechanical vibrations, rejects unwanted frequencies within the mechanical structflre, and then converts the mechanical vibration back into
electrical energy. The filter consists of three basic elements: (1) transducers which convert electrical signals into mechanical vibrations, (2)
high Q mechanically resonant metal discs, and (3) disc coupling wires.
The multi-element filter shown in the diagram illustrates how the center frequency is determined by the discs. Each disc is represented by
a parallel resonant circuit.
Applications for the wide range of standard filters include single sideband, high performance transmitting and receiving equipment, multiplexing equipment, missile guidance systems, precision navigation
equipment, spectrum analyzers, FM communications receivers, CB
transceivers, and others.

FURTHER INFORMATION
For technical information on Rockwell filter products or to discuss a
filter to your specifications, contact
Rockwell International
Filter Products
4311 Jamboree Road
Newport Beach, CA 92660
Phone 714/833-4632 or contact your local Rockwell Representative.

•

'1'

ROCKWELL-COLLINS
FILTER PRODUCTS

Rockwell International

Disc-Wire M'echanical Filters
Standard Products and Specifications
Cntr.
Freq
(kHz)

Typical Typical Source
Pie
Stopband & Load
Part Number (kHz/dB) (kHz/dB) K ohms

Res
Cap.
(pI)

256

526-9700-010

8.4/600

5.0

300
300
450
4SO
4SO
450
4SO
4SO
4SO
4SO
4SO
4SO
4SO
4SO
4SO
450
4SO
4SO
4SO
4SO
455
455
455
455
455
455
455

526-9311-000 2.95/2.5
5.2160
526-9312-000 2.95/2.5
5.2160
526-9963-010 0.320/3.0 1.2/60
526-9963-020 0.6SO/3.0 2.1160
526-9963-030 1.2/3.0
31160
526-9963-040 3.4/3.0
6.0/60
526-9963-060 6.8/3.0
1.5/60
526-9643-010 6.0/6.0 23.0/60
526-9643-030 6.75/60 23.0/60
526-9776-010 8.0/6.0 31.0/60
526-9901-010 2.35/6.0
4.0.'60
526-9902-010 23~/60
4.0/60

100.0
100.0
5.0
5.0
5.0
50
50
200
20.0
20.0
20.0
20.0

3SO
110
110

455
455
455
455
455
455
455
455
455
455

3.6/1.0

526-9955-010 2.8/3.0
526-9956-010 2.8/3.0
526-9923-010 28/3.0
526-9924-010 2.8/3.0
526-9678-010 3.35/2.0
526-9679-010
526-9936-010
526-9937-010
526-9764-010
526-9689-010
528-9494-000
526-9521-000
526-9765-010
526-9446-000
528-9770-010

3.35/2.0
61/30
6.1/3.0
0.2/3.0

0.525/3.0
0.5/60
05/60

0.5/3.0
0.90/6.0

1.175/3.0
526-9690-010 1.35/3.0
526-9495-000 I.S0/60
526-9691-010 2.05/3.0
526-9337-000 2.1160
526-9427-000 2.1160
526-9766-010 22513 0
526-9860-010 2.8/3.0
526-9692-010 2.8/3.0
528-9904-010 2.65/3.0
526-9500-000 2.3/3.0

455
455
455
455
455

526-9693-010 3\>5/3.0
526-9772-010 :).0/3.0
526-9496-000 3.116.0
526-9338-000 3.116.0
526-9694-010 3.95/3.0

455
455
455
455
455

526-9339-000 4.0/60
526-9639-010 4.0/6.0
52& 9767-010 4.0/3.0
526-9497-000 4.0/8.0
528-9920-010 5.5/3.0
526-9930-010 5.8/4.0
526-9695-010 5.95/30
526-9498-000 8.0/8.0
528-9522-001 6.0/3.5
52&-9340-000 6.0/8.0
526-9773-010 6.0/3.0
526-9341-000 8.0/6.0
526-9768-010 8.0/3.0
526-9774-010 12.013.0
526-9667-010 15.018.0

455
455
455
455
455
455
455
455
455
455
455
455

526-9343-000 16.0/8.0
526-9769-01
16.0/3.0

o

4.6/60
46160
45/60
4.5/60
475/60
475/60
87/50.0
87/50.0

2.4/60
3.5/60
3.0/60
3.0/60
3.5/60
4.0/60
60/60
80/60
35/60
54/60
5.3/60
53/60
63/60
11.75170

6.5/60
7.0/60
6.2/60
7.0/60
9.0/60
6.5/60
6.5/60
9.0/60
8.5/60
8.5/60
12.0/60
85160
13.0/60
120/83
14.0/60
12.6/60
25.0/60
12.6/60
18.0/60
18.5160

Function
LSB

Spec
L Spec
L Spec

180
270
110
360
750
30
30
30
30
30

LSB
USB
CW
CW
BP
BP
BP
BP
BP
BP
USB
LSB

5.0
5.0
50
5.0
20.0

30
30
30
30
30

USB
LSB
USB
LSB
USB

FD
FD
FD
FD

20.0
2.0
2.0
5.0
2.0
100.0
100.0
50
100.0
50

30
30
30
50
350
130
130
200
130
100

2.0
1000
2.0
100.0
100.0

350
130
330
130
130

lSB
lSB
USB
CW
CW
CW
CW
CW
CW
BP
BP
BP
BP
BP
BP

5.0
2.0
2.0
2.0
1000

130
1500
510
510
130

BP
BP
BP
BP
BP

2.0
5.0
100.0
1000
2.0

510
50
130
130
1000

BP
BP
BP
BP
BP

FD

1000
0.7SO
50
100.0
120
3.0
2.0
1000
100.0
100.0

130
130
470
130
360

BP
BP
BP
BP
BP

V
V
FA
HS

820
1100
130
130
130

BP
BP
BP
BP
BP

VA
FD
FA
FA
V

7SO
130

V

V

30.0/60

50
100.0
5.0
5.0
0.500

See Spec

BP
BP
BP
BP
BP

27.5/60
30 0/60

100.0
5.0

130
1100

BP
BP

24.0160

36.0/60

CaSe
Style

680

-

HS
HS
HS
HS
HS

V
V
V
V
V

V
V
FA
FA

V
FD
FA
V

V
FA

V
FD
FA
FD
V
FA

V
V
FD

V
FA

V
FA
V
FD

V

Cntr.
Freq.
(kHz)

Typical Typical
Source
PIB
Stopband & Load
Part Number (kHz/dB) (kHz/dB) K ohms

Res.
Cap
(pI)

Functoon

Case
Style

455
455
455
455
455
455
455
455
455

526-9605-010 1.8513.0
526-9606-010 1.85/3.0
526-9897-010 2.1/3.0
526-9939-010 2.1/3.0

5.0/60
5.0160
6.25/60
6.25/60

130.0
130.0
360
360

USB
LSB
USB
LSB

FA
FA
HS
HS

526-9967-010 2.3/3.0
526-9870-010 2.4/3.0
526-9724-010 2.65/6.0
526-9640-010 2.8/3.0
526-9641-010 2.8/3.0

4.8/60
5.35/60

1000
100.0
2.7
2.7
1.0
2.0
2.0
0750
0.750

30
680
700
130
130

USB
USB
USB
lSB
USB

VA

455
455
455
455
455
455
455
455
455
455
455
455

526-9958-010 3.15/3.0
526-9959-010 3.15/3.0
526-9364-000 3.0/30
526-9365-000 3.0/3.0
526-9903-010 3.2/1.5
526-9698-010 3.3/3,0
526-9699-010 3.0/3.0
526-9899-010 3.0/3.0
526-9900-010 30/3.0
526-9892-010 33/3.0
526-9783-010 63/30
526-9784-010 6.3/3.0

50
5.0
100.0
100.0
2.0

270
270
130
130
30

USB
LSB
LSB
USB
USB

FD
FD

500

526-9588-010

08/3.0

49160
4.9/60
475/60
8.7/SO
87/SO
3.0/60

500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500

526-9719-010
526-9717-010
526-9717-020
526-9378-000
526-9718-010
526-9646-010
526-9663-010
526-9664-010
526-9663-020
526-9906-010
526-9906-020
526-9414-000
526-9415-000
526-9616-010
526-937$-000
526-9377-000
526-9873-010
526-9874-010

1.15/3.0
33/3.0
3.3/30
6.4/3.0
6.3/30
8.3/3.0
1.8/2.0
1.8/2.0

56/60
7.0/60
7.0/60
13.2/60
13.0/60
20.0/40
5.38/sd
538/60

2.313.0

430/60

46160
4.6/60

526-9927-010
526-9928-010
526-9644-010
526-9645-010
526-9968-010

234/60
234/6.0
2.7/3.0
2.7/3.0
2.7/3.5
3.0/30
30/30
2.85/3.0
2.85/3.0
3.3/3.0
3.3/3.0
3.35/3.0
3.35/30
4.6/3.0

526-9711-010
526-9712-010

6.3/3.0

6.3/3.0

43/60
7.5/60
7.5/60
4.9160
49/60
60160
6.0/60
49140
4.8/40
4.8/40

6.1160
6.1160
6.1160
58/60

5.8/60
6.5160
6.5160
6.5/60

6.5/60
5.9/SO
5.9/SO
6. 75/SO
10.5/50
10.5/SO

V

FA
V
V
lSB
HS
USB
HS
USB V Long
lSB V Long
LSB
FD

2.0
30
2.0
30
20
30
2.0
30
2.0
30
2.0
30
2.0
30
S=I.0 See Spec
L=0330
2.0
30
2.0
300
20
300
100.0
120.0
20
300
10
51
160
200
160
200
200
160
30
180
180
30
100.0
120
1000
120

BP
BP
BP
BP
BP
BP
USB
'LSB
USB
lSB
LSB
USB
LSB

1000
1000
100.0
20.0
20.0

120
105
105
100
100

lSB
LSB
USB
USB
LSB

20.0
20.0
1.0
1.0
1.0
1.0
1.0

100
100
20
20
20
30
3Q

USB
LBS
USB
LSB
USB

LSB
USB

V
V
V
V
V

CS

V Flange

LSB
USB

V
V
FD
V

V
V
V long
V Lana
FD
FD
VA
V
V

V
V
V
VA
VA
V
V

V
V
V
V
V

FURTHER INFORMATION
For technical information on Rockwell filter products or to discuss a
filter to your specifications, contact

V

V
V
T

V

Rockwell International
Filter Products
4311 Jamboree Road
Newport Beach, CA 92660
or phone 714/833-4324 or 714/833-4544. To order. phone 714/
833-4632 or contact your local Rockwell Representative.

DOCUMENT NO. F-02
REV. 1. FEBRUARY 1980

Specil,cations subject to
change without not tee

Disc-Wire Mechanical Filters Case Styles

Case Style HS

if
~O~~,

Case Style FA

r~
n
t-.l d~1

TT1fI---'~"'=
I

I

2779 max

I '""'= -j

I-

0 701 max

~

Case Style FD

if

rltl

0.188

Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:19 09:34:36-08:00
Modify Date                     : 2013:08:19 12:54:21-07:00
Metadata Date                   : 2013:08:19 12:54:21-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:d3a7a9e3-03a2-9e4c-bb94-194e5a6abdc1
Instance ID                     : uuid:483b9469-2d89-8744-8e82-c52f4bbe8873
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 524


EXIF Metadata provided by EXIF.tools

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