1981_Systems_Data_Catalog 1981 Systems Data Catalog
User Manual: 1981_Systems_Data_Catalog
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inter SYSTEMS DATA CATALOG JANUARY 1981 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7·104.9 (a) (9). Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are implied. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation and may only be used to identify Intel products: BXP CREDIT i ICE ICS im Insite Intel Intelevision Intellec iSBC iSBX Library Manager MCS Megachassis Micromap MULTIBUS' MULTI MODULE PROMPT Promware RMX UPI I'Scope and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix. MDS is an ordering code only and is not used as a product name or trademark. MDS@ is a registered trademark of Mohawk Data Sciences Corporation. ~MULTIBUS is a patented Intel bus. Additional copies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 © INTEL CORPORATION, 1980 AFN·01300A·l Table of Contents Quality Assurance Flow Chart CHAPTER 1 Single Board Computers iSBC 80104 Single Board Computer .......... , . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . iSBC 80105 or (pSBC 80105*) Single Board Computer. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . iSBC 80/10B or(pSBC 80/10B*) Single Board Computer. . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . iSBC 80/20-4 or(pSBC 80/20-4*) Single Board Computer. . . . . . . . . . . . . . . . .. .. . . . . . .. . . . . . . iSBC 80/24 or(pSBC 80/24*) Single Board Computer. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . iSBC 80/30 or (pSBC 80/30*) Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBC 86/12A or(pSBC 86/12A *) Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBC 88/40 Measurement and Control Computer ...................................... , iSBC 310 High Speed Mathematics Unit ...................... , . . . . . . .. . . . . . . . . . . . . . . . . 1-1 1-7 1-12 1-19 1-26 1-35 1-43 1-51 1-59 CHAPTER 2 iSBXTM MULTIMODULETM Boards iSBX331 Fixed Floating Point Math MULTIMODULE Board.............................. iSBX 332 Floating Point Math MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBX 350 Parallel 110 MULTIMODULE Board. . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . iSBX 351 Serial 110 MULTIMODULE Board. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 2-1 2-7 2-12 2-16 CHAPTER 3 iCSTM Industrial Control Series " iCS 80 Industrial Chassis ............................................... " ... ~. . . . . . iCS 910/920/930 Signal ConditioninglTermination Panels. . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . iSBC941 Industrial Digital Processor _..................................... '" . . . . . . . . . 3-1 3-6 3-14 CHAPTER 4 Run-Times Systems Software iRMX/80 Real-Time Multi-Tasking Executive......................... .................. iSBC801 FORTRAN Run-Time Package............................. .................. iSBC 802 BASIC-80 Configurable RMX/80 Disk-Based Interpreter. . . . . . .. . . . . . . .. . . . . . . . . . . iRMX860peratingSystem ...................,... , ................. , .. ,............. iRMX88 Real-Time Multi-Tasking Executive......................... .................. iSBC 957 A Intellec-iSBC 86/12A Interface and Execution Package. . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.6 4~9 4-13 4-25 4-31 CHAPTER 5 Peripheral Controllers iSBC 202 Double Density Diskette Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 iSBC 204 Single Density Flexible Diskette Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 iSBC 208 Flexible Disk Controller ................................. ,. . . . . . . . . . . . . . . . . . 5-8 iSBC 215A/iSBC 21,5B Winchester Disk Controller. . . . . . . .. . . . . . . . . . . ... . . . . . . . . . . . . . . . . 5-12 iSBC 218 Flexible Disk Controller ....................................... ~ ............ ' 5-17 iSBC 220 SMD Disk Controller .............. , . , . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 CHAPTER 6 Memory Expansion Boards iSBC 01616K-Byte RAM Memory Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBC 032/048/064 RAM Memory Boards .............................................. '" iSBC 090 Memory System .......................................................... iSBC 094 4K-Byte CMOS RAM Memory Battery Backup Board ............................ iSBC 2501 Megabit Bubble Memory Board ............................................ , iSBC 254 Bubble Memory Board .......................' ............... :. . . . . . . . . . . . . . iSeC 41616K EPROM Expansion Board .................................... : .. . . . . . . . . iSBC 464 or(pSBC 464*) 64K-Byte EPROM Expansion Board ............................. iSBC 108A/116A Combination Memory and 1/0 Expansion Boards. . . . . . . . . . . . . . . . . . . . . . . . . iSBC 300 or (pSBC 300*) 32K-Byte RAM Expansion Module iSBC 340 or (pSBC 340*) 16K-Byte EPROM Expanison Module .............. :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBC 301 4K-Byte RAM MULTIMODULE Board ....... ~. . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . 6-1 6-3 6-5 ,6-9 6-12 6-15 6-16 6-18 6-21 6-29 6-30 CHAPTER 7 Digital 1/0 Expansion and Signal Conditioning Boards iSBC 337 MULTIMODULE Numeric Data Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBC 501 Direct Memory Access Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. iSBC 508 I/O Expansion Board ..................................................... , . iSBC 517 Combination I/O Expansion Board .................................... ; . . . . . . iSBC 519 or (pSBC 519*) Programmable I/O Expansion Board. . . . . . . . .. . . . . . . . . . . .. . . . . . . . iSBC 530 Teletypewriter Adapter ........... ; ................................. ; . . . . . . . iSBC 556 Optically Isolated I/O Board ..................... '... . . .. . . . . . . . . . . . . . . . . . . . . . iSBC 569 Intelligent Digital Controller ..................... " . . . . . . . . . . . . . . . . .. . . . . . . . 7·1 7·9 7·13 7·15 7·19 7·23 7·25 7·27 CHAPTER 8 Communication Controllers iSBC 534 or(pSBC 534*) FourChannel Communications Expansion Board..... ............ ISBC 544 Intelligent Communications Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·1 8·5 CHAPTER 9 Analog I/O Expansion & Signal Conditioning Boards iSBX 311 Analog Input MULTIMODULE Board ... ; . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . iSBX 328 Analog Output MULTI MODULE Expansion Board.......... ; . . . . . . . . . . . . . . . .. . . . iSBX 711 Analog Input Board. . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iSBX 724 Analog Output Board ................................. ; . . . . . . . . . . . . . . . . . . . . iSBX 732 Analog Combination I/O Board .............................................. 9·1 9·5 9·9 9·13 9·16 CHAPTER 10 System Packaging & Power Supplies ISBC 604/614 or (pSBC 604/614 *) Modular Cardcage/Backplane . . . . . . . . . . . . . . . . .. . . . . . .. . . iSBC 655 System Chassis ...................................... ;................... iSBC 660 System Chassis .......................................................... ISBC635 PowerSupply .. '.......................................................... iSBC640 PowerSupply ............................................................ 10·1 10·3 10·5 10·8 10·11 CHAPTER 11 Microcomputer Development Systems Introduction' New Dimensions in Development Solutions ........ , ............ ,............ Model 120 Intellec Series II Microcomputer Development System .................. '" : . . . Model 225 Intellec Series 11/85 Microcomputer Development System ...................... Model2861ntellec Series III Microcomputer Development System .................... ,... Model 290 Network Manager Intellec Network Development System·1 (NDS·1) . . . . . . . . .. . . . . 11·1 11·3 11·7 11-12 11·18 CHAPTER 12 Microcomputer Development Systems Options Expansion Chassis Intellec Series II Microcomputer Development System. . . . . . • . . .. . .. . . . Model 503 Double Density Upgrade Kit for Intellec Microcomputer Development System. . . . . Model 505 Intergrated Processor Card .....................................'.' .... : . . . . . Model 556 iAPX 86 Resident Processor Board Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model 590 Network Manager Upgrade Package Intellec Network Development System·1 (NDS·1) .... ·................................................................. : .. Model810 Software Development Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Mainframe Link for Distributed Development ............. , ... , .. , .......... ; .......... ,... Credit CRT·Based Text Editor Microcomputer Development Systems ................ , ..... , 12·1 12·3 12·5 12·8 12·11 12·14 12·18 12·21 CHAPTER 13 Flexible and Hard Disk Systems Intellec Single/Double Density Flexible Disk System ........•....... , . . . . . . . . . .. . . . . . . • . Model 740 Intellec Hard Disk Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13·1 13·5 CHAPTER 14 MCS 80185™ Development Systems and Options FORTRAN 808080/8085 ANS FORTRAN 77lntellec Resident Compiler .................... Basic·80 Extended ANS 1978 Basic Intellec Resident Interpreter. . . . . . . . . . . . . . . . . . . . . . . . . . ii 14·1 14·5 8080/8085 Fundamental Support Package (FSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iCIS COBOL Software Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. PUM 80 High Level Programming Language Intellec Resident Compiler. . . . . . . . . . . . . . . . . ..• PASCAL 80 Software Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP80 Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. SP85 Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ICE-80, 8080 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ICE-85B, MCS·85 In-Circuit Emulator with Multi-ICE Software. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-8 14-12 14-16 14-19 14-24 14-26 14-28 14-34 CHAPTER 15 iAPX 86/88 Support Options Series 118086/8088 Software Development Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PUM 86/88 Software Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. PASCAL 86/88 Software Package. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8087Software Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8089 lOP Software Support Package. . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . .. . . . . . . . . . . . . . . . . SP86A/SP86B Support Package................................ .... ... ..... .......... SP88 Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ICE-86, 8086 In-Circuit Emulator ................................. ,.................... ICE-88, 8088 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15-11 15-16 15-19 15-22 15-25 15-27 15-30 15-36 CHAPTER 16 Prototype Microcomputer Kits SDK-85, MCS-85 System Design Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDK-86, MCS-86 System Design Kit .... , . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDK-C86, MCS-86 System Design Kit Software and Cable Interface to Intellec Development System. . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16-7 16-13 CHAPTER 17 MCS-48™ Development Systems MCS-48 Diskette-Based Software Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICE-49, MCS·48 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSE-49 High Speed Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EM1 8021 Emulation Board ......................................................... EM2 8022 Emulation Board ............ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ICE-22, 8022 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17-1 17-3 17-7 17-13 17-16 17-19 CHAPTER 18 MCS-SPM Development Systems 8051 Software. Development Package. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 CHAPTER 19 UPI·41ATM Development Systems ICE-41A, UPI-41A In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 CHAPTER 20 2920 Signal Processor Development Systems 2920 Software Support Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 CHAPTER 21 Memory Systems Introduction .................... , ................... ;; .. . . . . . . . . . . . . . . . . . . . . . . . . . . . Series 90 General Purpose Memory System ........................................... in-5770 Video Refresh Memory System ............................................... in-1670, PDP*-11/70Add-On Memory System .......................................... in-5150 Eclipse Add-In Memory ... , .... , . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. in-5160 Nova3 Add-In Memory ....... ,.. . . . . . .. .. . . . . . . . .. . . . . . . .. . . . . . .. . . . . . .. . .... MU-5780 VAX·11/780 Add-In Memory Card; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21-1 21-2 21-5 21-11 21-15 21-19 21-24 CHAPTER 22 Insite T " User's Program Library .... ; ........., ..........• ' . .. . . .. .. . . .. . . .... ... . . . ... . .. . . . 22-1 CHAPTER 23 Intel Microcomputer Workshops ........................................................... 23-1 CHAPTER 24 Product Service 24-1 iii QUALITY ASSURANCE A typical product flow Automatic Test Systems Utilized in . Board Testing iv Visual Inspection of Printed Wire Assemblies Ovens Utilized for Board Pffj"Bake Cable Testing Using an Automatic Test System Checking Alignment of Floppy Disk Drives XYZ Measurement of Sheet Metal ASSEMBLY In·Process QC of System in Assembly SYSTEM TEST Aging in System Test Boot·Up Test in System Test v Shipping Inspection Single Board Computers 1 inter iSBC 80/04 SINGLE BOARD COMPUTER • Programmable 14-bit binary timer • 8085A CPU used as central processor • 256 bytes of static readlwrite memory • TTL serial 110 interface with hole patterns for RS232C line drivers and receivers • Sockets for 4K bytes of erasable reprogrammable read only memory • 22 programmable parallel 1/0 lines with sockets for interchangeable line drivers and terminators • Four-level vectored interrupt • Optimized for stand-alone applications with provisions for on-board + 5V regulator, heat sink, and mounting holes for attachment to user's equipment • Upward compatibility with iSBC 80/05 • Single + 5V power supply The iSBC 80/04 Single Board Computer is a member of Intel's complete line of OEM computer systems which take full advantage of Intel's LSI technology to provide economical, self·contained computer·based solutions for OEM applica· tions. The iSBC 80/04 is a complete computer system on a single 6.75 x 7.85·inch printed circuit card. The CPU, system clock, readlwrite memory, nonvolatile read only memory, 1/0 ports and drivers, serial interface, priority interrupt logic, and programmable timer all reside on the board. 1·1 iSBC 80/04 RAMIIOITimer. The system software is used to configure the 110 lines in any combination of unidirectional input or output ports as indicated in Table 1. The 110 interface may, therefore, be customized to meet specific peripheral requirements. In order to take full advantage of the large number of possible 110 configurations, sockets are provided for interchangeable 110 line drivers and terminators. Hence, the flexibility of thelIa interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity, and driveltermination characteristics for each application. The 22 programmable 110 lines and signal ground lines are brought out to a 50-pin edge connector that mates with flat, woven, or round cable. FUNCTIONAL DESCRIPTION Intel's powerful8-bit n-channel8085A CPU, fabricated on a single LSI chip, is the central processor for the iSBC 80104. The 8085A CPU is directly software compatible with the popular intel8080A CPU. The 8085A contains six 8-bit general purpose registers and an accumulator. The six general pwpose registers may be addressed individually or in pairs, providing both single and double precision operators. Minimum on-board instruction execution time is 2.03 microseconds. A block diagram of iSBC 80104 functionalcomponents is shown in Figure 1. Memory Addressing The 8085A CPU has a 16-bit program counter which allows addressing of up to 65,536 bytes of memory. An external stack, located within any portion of iSBC 80104 readlwrite memory, may be used as a last-inlfirst-out storage area for the contents of the program counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls the addressing of this external stack. This stack provides subroutine nesting bounded only by memory size. Stand·Alone Applications The iSBC 80104 is designed to be a cost-effective solution for applications requiring a self-contained computer on a single board without the need for external memory or 110 options. In order to help minimize power supply cost in small systems, the iSBC 80104 includes provision for an on-board + 5V regulator allowing unregulated voltage to be connected directly on the board. Regulated DC voltages are applied to the board through two 12-pin edge connectors which mate with flat, woven, or round cables. The iSBC 80104 also includes pins that will accept MOLEX-type connectors for connection of regulated DC voltages. Mounting holes are provided in the corners of the iSBC 80104 board which permit direct attachment to the user's equipment, thereby eliminating the need for cardcage and backplane. Memory Capacity The iSBC 80104 contains 256 bytes of readlwrite memory using the Intel 8155 RAMIIOITimer. Two sockets for up to 4'K bytes of nonvolatile read only memory are provided on the board. Read only memory may be added in 2K-byte increments using Intel 2716 erasable and electrically reprogrammable ROMs (EPROMs) or Intel 2316E masked ROMs. Optionally, if only 2K bytes are required, read only memory may be added in 1K-byte increments using Iniel 2708 EPROMs or Intel 2608 masked ROMs. Compatibility with iSBC 80105 Parallel 1/0 Interface TheiSBC 80104 is fully upward compatible with the iSBC 80105 Single Board Computer. Pin assignments for parallel 110, serial 110, and regulated DC voltages are The iSBC 80104 contains 22 programmable parallel ,1/0 lines implemented using the 110 ports of the Intel 8155 EXTERNAL 22 PROGRAMMABLE I/O LINES INTERRUPT SERIAL REQUEST I/O INTERFACE SERIAL I/O INTERFACE LINE ITTLlEVELS) IRS2J2C LEVELSI Figure 1. ISBC Block Diagram Showing Functional Components 1·2 iSBC 80/04 Table 1. Input/Output Port Modes of Operation Mode of Operation Unidirectional Port Lines (qty) Unlatched 1 8 2 8 3 3 4 3 Output Input Latched & Strobed X X X X X X Latched X X X X Control Latched & Strobed X X X1 X2 Noles 1. Port 3 must be used as a control port when port 1 is used as a latched and strobed input or a latched and strobed output port. 2. Port 4 must be used as a control port when port 2 is used as a latched and strobed input or a latched and strobed output port. indentical to those of the iSBC 80/05. Additionally, soft· ware developed for the iSBC 80/04 will execute directly in the iSBC 80/05. In addition to the iSBC 80/04 features, the iSBC 80/05 contains a total of 512 bytes of read/write memory, allows for expansion of memory and I/O capacity, and provides full MULTI BUS arbitration con· trol for multimaster applications. Serial I/O Interface The iSBC 80/04 prvides serial I/O capability through the serial input data (SID) and serial output data (SOD) func· tions of the Intel 8085A CPU. These functions are con· trolled exclusively by software through execution of the 8085A RIM and SIM instructions. The baud rate for the serial I/O interface is determined by the system time available for execution of serial I/O support software. Hence, the maximum baud rate supported by the iSBC 80/04 is solely dependent on the overall system real· time software requirements. Serial I/O signals are TTL compatible, and hole patterns are provided on the board for optional installation of RS232C line drivers and receivers. Programmable Timer The iSBC 80/04 provides a fully programmable binary 14·bit interval timer utilizing the Intel 8155 RAM/la/Timer. The systems deSigner simply configures the time via software to meet system requirements. Whenever a given timer delay is needed, software com· mands to the programmable timer select the desired functions. Four functions are available as shown in Table 2. The contents of the timer counter may be read at any time during system operation. Interrupt Capability The iSBC 80/04 takes advantage of the powerful interrupt processing capability of the 8085A CPU. Interrupt requests are routed to four interrupt inputs of the 8085A CPU (i.e., TRAP, RST 7.5, RST 6.5, and RST 5.5 in order of priority, TRAP highest), and each input generates a unique memory address (i.e., TRAP: 26 16 , RST 7.5: 3C 16, RST 6.5: 34 16 , RST 5.5: 2C 16 ). A single 8085A jump instruction at each of these addresses then provides linkage to locate each interrupt service routine independently anywhere in memory. All interrupt inputs with the exception of one (TRAP) may be masked via software. The trap interrupt should be used for conditions such as power-down sequences which require attention by the 8085A CPU. Table 2. Programmable Timer Functions Function Operation Programmable pulse Timer out goes low during the sec· ond half of count. Therefore, the count loaded in the count length register should be twice the pulse width desired. Square wave rate generator Timer out remains high until one· half the count has been completed, and goes low for the other half of the count. The count length is auto· matically reloaded when terminal count is reached. Rate generator Divide by N counter. A repetitive timer out low pulse is generated and new timeout initiated every time ter· minal count is reached. Programmable strobe A single low pulse is generated upon reaching terminal count. This func· tion is extremely useful for genera· tion of real·time clocks. Interrupt Generation - The iSBC 80/04 accepts inter· rupts from four sources. An interrupt is automatically generated by the programmable interval timer/event counter upon completion of the selected function. Two interrupts are automatically generated by the I/O ports section of the 8155 when ports 1 or 2 of the 8155 are programmed to operate in the "latched and strobed" mode (see Table 1). The fourth interrupt source is available to the user and should be used to inform the 8085A CPU of catastrophic errors such as power failure. This userdefined source is connected to the trap input of the 8085A CPU. 1·3 iSBC 80/04 capability to program in a natural, algorithmic language and eliminates the need to manage register usage or allocate memory. PUM programs can be written in a much shorter time than assembly language programs for a given application. Systems Development Capability The development cycle of the iSBC SOl04-based products may be significantly reduced using an Intellec microcomputer development system. The resideni macroassembler, text editor, and system monitor greatly simplify the design, development, and debug of iSBC SOlO4 system software: An optional diskette operatingsystem provides a relocating macroassembler, a relocating loader and linkage editor, and a library manager. A unique in-circuit emulator (ICE-S5) option provides the capability of developing and debugging software directly on the iSBC S0104. PL/M-80 - Intel's high level programming language, PUM, is also available as a resident Intellec microcomputer development system option. PUM provides the FORTRAN-BO - For applications requiring computational and formatted 1/0 capabilities, the high level FORTRAN-SO programming language is also available as a resident option of the Intellec system. The FORTRAN compiler produces relocatable object code that may be easily linked with PUM or assembly language program modules. This gives the user a wide flexibility in developing software. SPECI FICATIONS Interrupts Word Size Four-level interrupt routed to SOS5 CPU interrupt inputs. Each interrupt automatically vectors the processor to a unique memory location Programming Capability Instruction - S, 16, or 24 bits Data - S bits Cycle Time Basic Instruction Cycle - 2.03 I'S, ± 0.1 % Note Condition Interrupt Input Memory Address User·defined Timer 1/0 Port 2 1/0 Port 1 TRAP RST 7.5 RST 6.5 RST 5.5 24 16 3C16 34 16 2C16 Basic instruction cycle is defined, as the fastest instruction (i.e., four clock cycles). ., Priority Type Highest Non-rnaskable Maskable Maskable Maskable t Lowest Memory Addressing Timer ROMIEPROM - O-OFFFH RAM - 3FOO H Input Frequency Reference - 122.SS ·kHz ± 0.1 % (S.14 I's period nominal) Output FrequencieslTimlng Intervals Memory Capacity ROMIEPROM - 4K bytes (sockets only) RAM - 256 bytes TlmerlCounter Function 1/0 Addressing On-Board Programming 1/0 - see Table 1 Port Control 8155 Port 1 8155 Port 2 8155 3&4 8155 .Ports 8155 Timer Low·Order Byte 8155 Timer Hlgh·Order Byte Address 00 01 02 03 04 05 Programmable pulse Square' wave rate generator Rate generator Programmable strobe Min Max 8.14 ~s 7,50 Hz 7.50 Hz 8.14 ~s 66.67ms 61.44 kHz 61.44 kHz 133.33 ms Interfaces 1/0 .Capacity Parallel - Parallel 1/0 - All signals TTL compatible Interrupt Request - All TTL compatible (active-low) Serial 1/0 - TTL; hole patterns available for user installation of RS232C line drivers and receivers 22 programmable lines (see Table 1) Serial Communications Characteristics SID and SOD functions of the S085 CPU are used for serial 1/0. Controlled by software through RIM and SIM instructions of the SOS5A CPU. Baud rate determined by system time available for serial 1/0 handling, On-board timer may be used to greatly ease serial 1/0 timing requirements. System Clock (8085 CPU) 1.966 MHz ±0.1% 1-4 iSBC 80/04 Connectors Line Drivers and Terminators The following line drivers are all compati· ble with the I/O driver sockets on the iSBC 80/04: 110 Drivers - Interface Pins (no.) Center (In.) Mating Connectors 1 Molex 09·66·1071 Connector Molex 09·50·7071 + 5V, + 12V, _ 5V 2 7 single· Connector 0.156 sided Driver Characteristic Sink Current (rnA) 7438 I,OC 48 7437 I 48 7432 NI 16 7426 I,OC 16 7409 NI,OC 16 7408 NI 7403 I,OC 16 16 7400 I 16 Note AMP 87194·6 I;;; inverting; NI;;; non-inverting; OC;;;;: open collector. Connector AMP 3·87025·4 Connector I/O Terminators - Intel provides 220Q/330Q divider and 1 kQ pull·up resistive terminator packs for termination of 110 lines programmed as inputs. These options are as follows: Molex 09·66·1071 Connector Molex 09·50·7071 Connector 7 Voltages + 5V, -12V 3 single- 0.156 sided AMP 87194·6 220Q +5V - - - - - ; : - - - - - - , Connector AMP 3·87025·4 220QI330QL Connector Molex 09·66·1021 ~-----+----~O isec 901 OPTION 1 kQ 1 kQ Connector + 5V ----~'VV\_------__o isec 902 OPTION Molex 09·50·7021 Unregulated +5V 2 singlesided Connector RS232C Drivers and Receivers 0.156 The following RS232C drivers and receivers are compati· ble with the RS232C socket on the iSBC 80/04: RS232C Driver - National DS1488 or TI SN75188 RS232C Receiver - National DS1490 or TI SN75189 AMP 89194·1 Connect"or AM P 2·87025·5 Connector Parallel 1/0 50 double· sided 0.1 3M 3415·000 (flat cable) Sockets Sockets may be installed in the hole patterns provided ior the RS232C drivers and receivers. The following sockets are compatible with the iSBC 80/04: TI C93·14·02 and SCANBE US·2·14·160·N·B. MOlex 09·66·1071 Connector Molex 09·50·7071 Connector 7 Serial 1/0 single· ended 0.156 Compatible Voltage Regulator AMP 87194·6 National LM 323 - 3A, 5V Positive Regulator Fairchild J.S = sign bit 0= positive 1 = negative E2 - Eo = biased exponent (8 bits) (bias = 7F H) F22 - Fo = fraction (23 bits) where: Fixed Point Integer (1S·Bit) Memory Location I I F7 - FO F15 - Fa where: F15 - Fo = 16·bit integer 1,61 ~.- .... = 5 4 < R R ERR R is reserved for future use = is equal (for FCOMP and FTST) > is greater than (for FCOMP and FTST) < Is less than (for FCOMP and FTST) and: ERR is a 3·bit error code that specifies one of the following error conditions: 000 No error 001 Divide by zero 010 Square root of negative number 011 Overflow 100 Underflow 101 First argument valid 110 Second argument valid 111 Reserved Note F is always normalized (i.e., a "1"ls assumed In the highest bit position), yielding an effective 24·bit fraction. M+l F24 Result Byte Fa F22 - where: Base Address (M) F30 - where: S = sign bit F30 - Fo = two's complement integer Memory Location Base Address (M) I S M+3 iSBC 310 Status Byte connected to any ,of the 8 interrupt levels on the ISBC 80 'bus via jumpet selection. Contains the following Information: 7 I 5 8 I R where: 'R I R is B Is C is E is R I 4 3 2 R R E ',0 I c B Bus Interface I All signals are TTL compatible. reserved for fUture use bl,lsy operation complete without error operation complete with error Bus Connector Bus Connector - 86-pin, double-sided PC edge connector with 0.156-in. contact centers. ' Mating Connector -Viklng3KH43/9AiVlK12 Addressing 1/0 Addressing - Used to pass operation codes, memory address boundaries, and result and status bytes between host processor and iSBC 310 " Port Add..... Base (p) , P+l P+2 , P+3 P+4 P+S P+6 P+7 Output OPCODE MEM LOW MEMHIGH 'R R R R R Physical Characteristics Width - 12.00 in (30.48 cm) Height -- 6.75 in. (17.15 cm) Depth- 0.50 In. (1.27 cm) Weight - 12 oz (340.5 gm) Input ,,' R Result byte R R R R R Slatus byte Electrical Characterls'tics DC Power Requirements I P= 110 base address, of XO or X8 (where X = any hex digit) R = reserved for iSBC 310 usage OP CODE = mathematic commands (see Table 1) MEM LOW, _ programmable base address (see MemMEM HIGH - ory Addressing) vee SV:l:S% I , iec 6.7A max; 4.9A Iyp 'where:, Environmental Characteristics Operating ,Temperature - O·C to 55·C Equipment Supplied High speed mathematics units Standard preprogrammed ROMs (installed) Schematics Assembly drawing Memory Addressing - Sixteen memory locations are used; the first eight are used for argument/result storage; the second eight are reserved for future use. Memory addresses are assigned froin the host processor via an 1/0 output instruction (see I/O Addressing). MEM LOW (the lower address byte) must be XO (where X is any hex digit). MEM HIGH (the upper address byte) , may be any value. " Reference Manual 9800410A - iSBC 310 Hardware Reference Manual (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel LiteratUre Department, 3065 Bowers Avenue, Santa Clara, California 95051. Interrupts Interrupts are generated, on operation complete and operation error. Either one or both interrupts may be ORDERING INFORMATION Part Number Description SBC 310 High Speed Mathematics Unit - 1-62 iSBXTM Multimodule™ Boards 2 = iSBX 331 FIXED/FLOATING POINT MATH MULTIMODULE BOARD • iSBX bus compatible high speed fixed/floating point math expansion • Square root, log, and exponential functions • 4 M Hz operation • Float·to·fixed and fixed·to·float conversions • Fixed point single and double precision (16/32·bit) • End of operation interrupt • Floating point double precision (32·bit) • Software reset control • Binary data formats • Low power requirements • Add, subtract, multiply and divide • iSBX bus on·board expansion elimi· nates MULTIBUS system bus latency and increases system throughput • Trignometric and inverse trigonometric functions The Intel'" iSBX 331 Fixed/Floating Point Math MULTIMODULE Board is a member of Intel's new line of iSBX bus compatible MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host board offering low cost incremental on·board expansion. As a result, any iSBX bus compatible host board may be expanded to perform high speed math computations, affording up to a 40 x improvement in speed compared to software math. The iSBX 331 module performs single/double (16/32-bit) precision fixed point plus double (32-bit) precision floating point arithmetic operations. In addition, the module performs transcendental, data manipulation, and fixed to float/float to fixed point conversion operations. The command operations run entirely independent of the host board permitting efficient concurrent processing. The iSBX board is closely coupled to the host board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS system traffic for other system resources. Incremental power dissipation is minimal requiring only 2.73 watts. 2-1 .....:..:.. -. iSBX 331 returned to TOS. There are four types of transcendental operations that can be performed in floating point numbers: trigonometric functions, logarithms, exponentials, and square roots. The results of these operations will be returned to TOS. There are four types of data manipulation operations that can be performed in either fixed or floating point numbers: sign change of TOS, exchange of TOS and NOS and copying or popping operands onto or off of TOS. Fixed to floating point conversion can be performed on floating point instructions and floating point to fixed point conversion can be performed on fixed point instructions. FUNCTIONAL DESCRIPTION The iSBX 331 module uses the Intel 8231 Arithmetic Processing Unit (APU) to accomplish high speed (4 MHz) math operation. The system software may communicate with the iSBX 331 module across the iSBX bus using 1/0 readlwrite commands. All transfers, including operand, result, status, and command information, take place over an 8-bit bidirectional data bus. Operands are pushed onto an internal stack and. commands are issued to perform operations on the data. Results are then available from the stack. A status byte may be read to monitor execution completion and the nature of the result (zero, sign, or errors). In addition, control logic is included on the iSBX 331 module to facilitate single instruction software reset control. The execution times of the commands are shown in Table 2. Interrupt Requests There is one interrupt line from the APU that may generate an interrupt request to the host: END (MINTRI). The END interrupt line is active upon command completion. The END signal is cleared by a reset or status register read. Command Functions The iSBX 331 module commands fall into three categories: double preCision floating point, single precision fixed point, and double precision fixed point (see Table 1). There are four arithmetic operations that can be performed in either fixed or floating point numbers: add, subtract, multiply, and divide. These operations require two operands. The 8231 assumes these operands are located in the internal stack as Top of 'Stack (TOS) and Next on Stack (NOS). The result will always be Installation The iSBX 331 module plugs directly into the female iSBX connector on the host board. The module is then secured at one additional point with nylon hardware to insure the mechanical security of the assembly (see Figures 1 and 2). INTEL ISBX 331 MULTI MODULE BOARD HOST BOARD ~ .. ::- .. ;:::.:':::" INTEL ISBX _MULTIMODULE CONNECTOR " " Figure 1_ Installation of Isax 331 Module on a Host Board 2-2 AFN·01486A .. ~. iSBX 331 Table 1. Command Summary Double Precision Floating Point Instructions (32·Bit) Instruction Hex Code Description Stack Contents After Execution(ll A B C D ACOS Inverse Cosine of A 0 6 R U U U ASIN Inverse Sine of A 0 R U U U ATAN Inverse Tangent of A 0 5 7 R B U U R B C D CHSF Sign Change of A 1 5 COS 0 3 R B U U EXP Cosine of A (radians) eA Function 0 A R B U U FADD Add A and B 1 0 FDIV Divide B by A 1 3 R C. D U R C D U FLTD 32·Bit Fixed to Floating Point Conversion 1 C R B C U FLTS 16·Bit Fixed to Floating Point Conversion 1 D R B C U FMUL Multiply A and B 1 2 R C D U FSUB Subtract A from B 1 1 R C D U LOG Common Logarithm (base 10) of A 0 8 R B U U LN Natural Logarithm of A 0 9 R B U U POPF Stack Pop 1 B C D A PTOF Stack Push 1 8 7 PUPI Push onto Stack 1 A R A B C PWR BA Power Function 0 B R C U U SIN Sine of A (radians) 0 2 R B U U 7r A A B C SQRT Square Root of A 0 1 R B C U TAN Tangent of A (radians) 0 4 R B U U XCHF Exchange A and B 1 9 B A C D Status Flags Affected(3 1 S,l, S,l, S,l S,l S,l S,l, S,l, S,l, S,l S,l S,l, S,l, S,l, S,l, S,l S,l S,l S,l, S,l S,l, S,l, S,l E E E E E E E E E E E E Double Precision Fixed Point Instructions (32·Bit) Instruction Hex Code Description Stack Contents After Execution(ll A B C D CHSD Sign Change of A 3 4 R B C D DADD Add A and B 2 C R C D A DDIV Divide B by A 2 F R C D DMUL Multiply A and B (R 2 E R C D U DMUU =lower 32 bits) Multiply A and B (R =upper 32 bits) 3 6 R C D U DSUB Subtract A from B 2 D R C D A R B C U Li FIXD Floating to Fixed Point Conversion 1 E POPD Stack Pop 3 8 B C D A PTOD Stack Push 3 7 A A B C XCHD Exchange A and B 3 9 B A C D 2·3 AFN·01486A • ..:::::Jo .•• Status Flags Affected(31 S,l,O S,l, C, E S,l, E S,l,O S,l,O S, l,C,O S,l,O S, l S,l S,l iSBX331 Table 1. Command Summary (continued) Single Precision Fixed Point Instructions (16·Bit) , Hex Code ' Description Instruction ," ," .' Stack Contents Status Flags After Execution(2) 4ffected(3) Au' AL BuBL C u C L Du DL CHSS Change Sign 'of Au 7 4 FIXS Floating to Fixed Point Conversion 1 F POPS' Stack Pop 7 .8, AL Bu .BL Cu CLDu DL Au' PTOS Stack Push 7 .7 Au Au A~ Bu BL C Ci. Du SADD Add Au and Ai. 6 C R Bu BL Cu CLO'u DL Au SDIV Divide AL by Au 6 F R Bu BL SMUL Multiply AL by Au'(R= lower 16 bits) 6 E R Bu BL Cu C L Du DL U R Bu BL Cu CL Du DL U R Bu BL Cu C~ Du DL Au " R AL Bu BL Cu CL Du DL R Bu BL' Cu CL 'u ,'U U u CU CL Du DL U SMUU Multiply AL by Au (R = upper 16 bits) 7 6 SSUB Subtract Au from AL 6 0 XCHS, Exchange Au and AL 7 . 9 AL Au Bu BL NOP No Operation 0 Au A~ Bu BL Cu :C L Du DL 0 CU CLDu DL , S,l,O S,l,O S,l S,l S, l, C; E 'S,l, E S,l, E S,Z, E S,l, C, E S,l NOTES:, 1, The stack initially is composed of four 32·bit numbers (A, B, C, D), A is equivalent to Top Of Stack (TOS) .and B is Next On Stack (NOS), Upon completion ;{f a command the stack is composed of: the result (R); undefined (U); or the'initiill contents (A.B. C, or D). 2. The stack initially is composed of eight 16·bit numbers (A~, AL" Bu, SL, Cu, CL, Du. DL), Au is the TOS and AL is NOS. Upon comple· tion of a command the stack is composed of: the result (R); undefined (U); or the initial contents (Au. A L• Su. SL.:")' 3, Nomenclature: Sign (S); Zero (Z); Overflow (0); 'Carry (C); Error Code Field (E). Table 2. Command Execution Times Command Mnemonic " : SADD SSUB SMUL SMUU SDIV DADO DSUB DMUL DMUU DOIV FIXS FIXD FLTS, FLTD FADD FSUB , FMUL FDIV SORT SIN COS " TAN ., . ,..Seconds Command Mnemonic ,..Seconds 4.25 7.5 21-23.5 20-24.5 21-23.5 5.25 9.5 48.5-52.5 45.5-54.5 ,52 23-54 25-.86.5 24:5-46.5 24.5-94.5 13.5-92 17.5-92.5 36,.5-42' 38.5-46 200 1116 1029.5, 1438.5 ASIN ACOS ATAN LOG LN EXP ." PWRNOP CHSS CHSD CHSF PTOS PTOD PTOF POPS POPD POPF XCHS XCHD XCHF PUPI 1917 1933.5 1501.5 1118.5-1783 1074.5-1739 948.5-1219.5 ,2072.5-300.8 1 5.75 6;75 4.5 4 5 5 2.5 3 :3 4.5 6.5 6.5 4 .' "' '" , NOTE: Assumes 4 MHz operation:" AFN·01486A iSBX 331 __ r L.C. .;.O_NI:_:~_TO"';'". . L. _- -L I _ _ _- L _ - - ' OOSOl(m,no) (FEMALE) Figure 2. ISBX 331 MULTIMODULE Board Mounting Clearanc.es (inches) Bits 0-14: Values in the range from - 32, 768 to +32,767. SPECIFICATIONS Word Size Double Precision Fixed Point (32 bits) Data-8 bits. 1 On-Board Clock Rate S 4.0 MHz ±0.1%. 31 1 VALUE I I I I I I I I I I I I I I I I I I I II I I I I I I I I II S =Sign of operand. Positive values are represented by a sign of zero (S = 0). Negative values are represented by the two's complemet of the corre· sponding positive value with a sign bit equal to 1 (S = 1). Bits 0-30: Values in the range from - 2,147, .483, 648 to + 2, 147, 483, 647. Bit 31: 110 Addressing Function Type of Operation iSBX Connector Port Address Data Transfer Command Transfer Status Transfer Reset Read or Write Write Read Write XD, X2, X4, or X6 X1, X3, X5, or X7 X1, X3, X5, or X7 X8 through XF NOTE: Double Precision Floating Point (32 bits) The port addresses are determined on the host iSBC micro· computer. Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit (X) of the connector port addresses. 1 EXPONENT Arithmetic Functions Bit 31: See Table 1. Data Formats AFN·01486A 'I 0 MS = Sign of the mantissa. 1 repre· sents negative and 0 represents pOSitive. = I' I I I I I I I I I I I I I I I Bit 15: MANTISSA 2423 Bits 24-30: ES the exponent expressed as a two's complement 7·bit value having a range of - 64 to· + 63. Single Precision Fixed Point (16 bits) ~I I mllllllllllllllllllllllllllill 3130 g 0 Bits 0-23: The mantissa is expressed as a 24·bit (fractional) value. The 8231 APU requires that floating point data be represented by a fractional mantissa value between 0.5 and 1 multiplied by 2 raised to an appropriate power (expo· nent). This is expressed as follows: VALUE 0 S = Sign of the operand. Positive values are represented by a sign bit of zero (S = 0). Negative values are repre· sented by the two's complement of the corresponding positive value with a sign bit equal to 1 (S = 1). Value = mantissa x 2exponent 2-5 iSBX 331 Device Status Interrupts Device status is provided by means of an internal status register whose format is shown below: One interrupt request may originate from the APU indicating command completion (END). I BUSY I S'GN I ZERO I ERRORCODE---II CARRY I Interface BUSY: Indicates that 8231 is currently executing a command (1 = Busy) iSBX Bus-All signals TTL. compatible SIGN: Indicates that the value on the top of stack is negative (1 = Negative) Physical Characteristics Width-6.35 cm (2.50 in.) Length-9.40 cm (3.70 in.) Height*-2.04 cm (0.80 in.) iSBX 331 Board --':2.86 cm (1.13 in.) iSBX 331 Board + Host Board Weight-51 gm (1.79 oz) ZERO: Indicates that the value on the top of stack is zero (1 = Value is zero) ERROR CODE: This field contains an indication of the validity of the result of the last operation. The error codes are: 0000 No error 1000 Divide by zero 0100 Square root or log of negative number 1100 Argument of inverse sine, cosine, or eX too large XX10- Underflow XX01- Overflow 'See Figure 2. Electrical Characteristics DC Power Requirements Vee= +5V ±5% lee=365 mA max. Voo= + 12V ±5% 100=75 mA max. CARRY: Previous operation resulted in carry or borrow from most significant bit. (1 = Carry/Bor· row, 0= No Carry/No Borrow.) Environmental If the BUSY bit in the status register is a one, the other status bits are not defined; if zero, indicating not busy, the. operation is complete and the other status bits are defined as given above. Operating Temperature-O·C to 55·C Free moving air across the base board and iSBX board. Access Time Reference Manual Read-1900 ns (max.) Write-1900 ns (max.) 142668~01-iSBX 331 Floating Point Math MULTIMODULE Board (NOT SUPPLIED) NOTE: Actual transfer speed isdepende.nt upon the cycle. time oHhe host microcomputer. The listed times assume no operation in progress. 11 an operation is executing when an access is at· tempted, the command execution time must be added to the above times for all accesses except status read. Reference manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. . ORDERING INFORMATION ~art Number SBX331 Description Fixed/Floating Point Math MULTIMODULE Board 2·6 iSBX 332 FLOATING POINT MATH MULTIMODULE' BOARD • iSBX bus compatible high speed floating point math expansion • Add, subtract, multiply and divide functions • 4 M Hz operation • End-of-operationand error interrupts . • Compatible with proposed IEEE format and existing Intel floating point standard ' . . • Software reset control • Accessed as 1/0 port .Iocations • Single (32-bit)1 double (64-bit) precision arithmetic and data manipulation commands • Low power requirements • iSBXbus on-board expansioneiim.i. nates MULTIBUS system bus latency and increases system throughput • Performs functions independently and concurrently with the MULTIBUS host board The Intel® iSBX 332 Floating Point Math MULTI MODULE Board is Ii member of Intel's new line of iSBX bu's compatible MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host board offering incremental on-board expansion. The iSBX 332 module performs single (32·bit) and double (64·bit) precision floating point add, subtract, multiply, and divide functions compatible with the proposed IEEE floating pOint standard. The command operations run entirely independent of the host board permitting efficient concurrent processing. The iSBX board is closely coupled to the host board through the iSBX bus; and as such, offers maximum on-board perform· ance and frees MULTIBUS system traffic for other system resources. In addition, Incremental power dissipation Is minimal requiring only 2.73 watts 2·7 iSBX 332 The results will be raunded ta preserve the accuracy. In additian ta the arithmetic aperatians, the 8232 implements eight data manipulating aperatians. These include changing the sign .of a dauble .or single precisian .operand lacated in TOS, exchanging single precisian operands lacated at TOS and NOS, as well as capying and papping single .or dauble precisian .operands. See alsa the sectlans an status register and .operand farmats. FUNCTIONAL DESCRIPTION The iSBX 332 madule uses the Intel'" 8232 Flaating Paint Pracessar (FPP) ta accamplish high speed math aperatian. The system saftware may cammunlcate with the iSBX 332 madule acrass the iSeX bus using 1/0 readl write cammands. All transfers, including .operand, result, status, and cammand infarmatian, take place aver an 8-bit bidirectianal data bus. Operands are pushed anta an internal stack and cammands are issued ta perfarm aperatians an the data stack. Results are then available ta be retrieve'd fram the stack. A status byte may be read ta manitar executian campletian and the nature .of the result (zera, sign, .or errars). In additian,cantral lagic is, included an the iSBX 332 madule ta facilitate single instructian saftware reset cantral. The executian times .of the cammands are all data dependent. Table 2 shaws .one example .of each cammand executian time. Interrupt Requests There are twa interrupt lines fram the FPP that may generate an interrupt request ta the .hast: END (MINTR1) and ERINT (MINTRO). The END interrupt line is aciive upan cammand campletian and the ERINT lineis active when the current cammand executian results in an errar canditian. The errarcanditians are: attempt ta divide by zera, expanent averflaw and expanent underflaw. Bath the END and ERINT signals are cleared by a reset .or status register read. Command Functions The iSBX 332 madulecainmands lallinta three categories: single precisian arithmetic, dauble precisian arithmetic and data manipulatian (see Table 1). There are faur arithmetic aperatians that can l;ie perfarmed with single precisian (32-bit) .or dauble precisian (64-bit) flaating pain'tnumbers: add .. subtract, n\ultiply and divide. These aperatians require' twa, .operands. The 8232 assumes that these .operands are Ipcated in the internal stack as Tap .of Stack (TOS) and Next an Stack (NOS). The result will always be returned ta the previaus NOS which becames the new TOS. Results fram an aperatian are .of the same precisian and farmat as the .operands. Installation The iSBX 332 madule plugs directly inta the female iSBX can nectar an the hast baard. The madule is then secured at .one additianal paint with nylan hardware ta insure the mechanical security .of the assembly (see Figures 1 and 2). INTEL Isax 332 MULTIMODULE aOARD HaST. BOARD .'. . INTEL ISBX • .. " .... ~. MULTIMOD.ULE ." ' CONNECTOR ~ .. : .. ' .0.:0 . ." .... ,. .. "". . . . .\. .' Figure 1. Installation of ISBX 332 Module on a Host Board 2·8 iSBX 332 Table 1. Command Summary Command Bits 765 4 3 2 1 0 Mnemonic Description X 0 0 000 0 1 SADD Add TOS to NOS single precision and result to NOS. Pop stack. X 0 0 000 1 0 SSUB Subtract TOS from NOS single precision and result to NOS. Pop stack. SMUL Multiply NOS by TOS single precision and result to NOS. Pop stack. X 0 0 000 1 1 X 0 0 0 0 1 o0 o1 SDIV Divide NOS by TOS single precision and result to NOS. Pop stack. CHSS Change sign of TOS single precision operand. X 0 0 0 0 1 1 0 PTOS Push single precision operand on TOS to NOS. X 0 0 0 0 1 1 1 POPS Pop single precision operand from TOS. NOS becomes TOS. X 0 0 0 1 000 XCHS Exchange TOS with NOS single precision. o1 X 0 0 0 0 1 o1 CHSD Change sign of TOS double precision operand. X 0 1 0 1 1 1 0 PTOD Push double precision operand on TOS to NOS. X 0 1 0 1 1 1 1 POPD Pop double precision operand from TOS. NOS becomes TOS. X 0 0 0 0 000 CLR CLR status. X 0 1 0 1 001 DADD Add TOS to NOS double precision and result to NOS. Pop stack. X 0 1 0 1 0 1 0 DSUB Subtract TOS from NOS double precision and result to NOS. Pop stack. o1 o1 0 1 1 DMUL Multiply NOS by TOS double precision and result to NOS. Pop stack. 100 DDIV Divide NOS by TOS double precision and result to NOS. Pop stack. X 0 1 X 0 1 X 0 1 1 NOTE: X = Don't care. Operation for bit combinations not listed above is undefined. Table 2. Execution Times Command TOS SADD SSUB SMUL SDIV CHSS PTOS POPS XCHS CHSD PTOD POPD CLR DADD DSUB DMUL DDIV 3F800000 3F800000 40400000 3F800000 3F800000 3F800000 3F800000 . 3F800000 3FFOOOOOOOOOOOOO 3FFOOOOOOOOOOOOO 3FFOOOOOOOOOOOOO 3FFOOOOOOOOOOOOO 3 F FOOOOOAOOOOOOO 3FFOOOOOAOOOOOOO BFF8000000000000 BFF8000000000000 Result NOS 3F800000 3F800000 3FCOOOOO 40000000 40000000 00000000 40900000 3FOOOOOO BF800000 - - 40000000 - - - -,- 8000000000000000 8000000000000000 3FF8000000000000 3FF8000000000000 3FFOOOOOAOOOOOOO 3FFOOOOOAOOOOOOO C002000000000000 B F FOOOOOOOOOOOOO B F FOOOOOOOOOOOOO - NOTE: lOS, NOS and result are in hexadecimal; clock period is in decimal. 2·9 Clock Periods Time!i iSBX 350 Parallel Interface Connectors Interlace No. 01 Center. Connector Pairs! (In.) Type Pins Parallel 110 Connector 25150 0.1 Female Parallel 1/0 Connector 25150 0.1 Female, Soldered Physical Characteristics Vendor Vendor Part No. 3M 3415'()OO1 with Ears Width - 7.24 cm (2.85 in.) Length - 9.40 cm (3.70 in.) Height" - 2.04 cm (0.80 in.) iSBX 350 Board - 2.86 cm (1.13 in.) iSBX 350 Board Board Weight - 51 gm (1.79 oz) GTE 6AD01251A1DD Sylvania + Host ·See Figure 2. Note: Connector compatible with those listed may also be used. Line Drivers and Terminators Electrical Characteristics 1/0 Drivers - The following line drivers and terminators are all compatible with the 1/0 driver sockets on the iSBX 350. DC Power Requirements Driver Characteristic 7438 7437 Power Requirement Conllguratlon +5V@320mA Sockets XU3, XU4, XU5, and XU6 empty (as shipped). +5V@500mA Sockets XU3, XU4, XU5, and XU6 contain 7438 buffers. +5V@620mA Sockets XU3, XU4, XU5, and XU6 contain iSBC 901 termination devices. Sink Current (mA) I.OC I 48 7432 NI 7426 I.OC 16 16 7409 7408 7403 NI.OC 16 NI I,OC 7400 I 16 16 16 48 Environmental Note: Operating Temperature - O°C to 55°C I = Inverting, NI = Non·lnverting, OC= Open Collector Port 1 has 25 mA totem pole drivers and 1 kO termi· nators. Reference Manual 1/0 Terminators - 220013300 divider or 1 kO pull up. 9803191·01 - iSBX 350 Parallel I/O MULTIMODULE Manual (NOT SUPPLIED) 22011/33011 (lSBC 901 OPTION) 220u +5V ---....,~'-;- - - - , a .f 1 kl! (ISBC 902 OPTION) Reference Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Ave., Santa Clara, California 95051. 1 kU +5V - - - -.....IW/O-·- - - - - - - - 0 0 ORDERING INFORMATION Part Number Description SBX 350 Parallel I/O MULTIMODULE Board 2·15 iSBX 351 SERIAL.I/O MULTIMODULE BOARD • iSBX bus compatible I/O expansion • Four jumper selectable interrupt request sources • Programmable synchronous/asynchro· nous communications channel with RS232C or RS449/422 interface • Accessed as 1/0 port locations • Low power requirements • Single + 5V when configured for RS449/422 interface • Software programmable baud rate generator • iSBX bus on·board expansion elimi· nates MULTIBUS system bus latency and increases system throughput • Two programmable 16·bit BCD or binary timers/event counters The Intel® iSBX 351 Serial I/O MUL TIMODULE board is a member of Intel's new line of iSBX bus compatible MUL TIMODULE products. The iSBX MUL TIMODULE board plugs directly into any iSBX bus compatible host board offering incremental on"board 110 expansion. The iSBX 351 module provides one RS232Cbr RS449/422 programmable synchronous/asynchronous communications channel with software selectable baud rates. Two general purpose programmable 16·bit BCD or binary timers/event counters are available to the host board to generate accurate time intervals under software control. TheiSBXboard is closely coupled to the host board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS system traffic lor other system resources. In addition, incremental power dissipation is minimum requiring only 3.0 watts (assumes RS232C interface). 2-16 = iSBX 351 FUNCTIONAL DESCRIPTION and framing error detection are all incorporated in the USART. The command lines, serial data lines, and signal ground lines are brought out to a double edge connector configurable for either an RS232C or RS449/422 interface (see Figure 3). In addition, the iSBX 351 module is jumper configurable for either point-to-point or· multidrop network connection. Communications Interface The iSBX 351 module uses the Intel® 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (U8ART) providing one programmable communications channel. The USART can be programmed by the system software to individually select the desired asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). The mode of operation (i.e. synchronous or asynchronous), data format, control character format, parity, and baud rate are all under program control. The 8251A provides full duplex, double buffered transmit and receive capability. Parity, overrun, 16-SIt Interval Timers The iSBX 351 module uses an Intel 8253 Programmable Interval Timer (PIT) providing 3 fully programmable and independent BCD and binary 16-bit USER I/O CONNECTOR------. INTEL ISBX 351 MULTIMODULE BOARD HOST BOARD / INTEL iSBX .~. '.-:::.' _ _ MULTIMODULE -:::::::::::;" CONNECTOR . . . Figure 1. Installation of iSBC 351 Module on a Host Board 2-17 iSBX 351 interval. timers. One timer is available to the system designer to generate baud rates for the USART under software control. Routing for the outputs from the other two counters is jumper selectable to the host board. In utilizing the iSBX 351 module, the systems designer simply configures, via software, each timer independently to meet system requirements. Whenever a given baud rate or time delay is needed, software commands the programmable timers to select the desired function. The functions of the timers are shown in Table 1. The contents of each counter may be read at any time during system operation. hardware to insure the mechanical security of the assembly (see Figures 1 and 2). Table 1. Programmable Timer Functions Operallon Function Interrupt on terminal count When terminal count is reached, an interrupt request is generated. This function is useful for generation of real-time clocks. Programmable Output goes low up,on receipt of an external trigger edge and returns high when terminal count is reached. This function is ret riggerable. one-shot Rate generator Divide by N counter. The output will go low for one input clock cycle, and the period from one low going pulse to the next is N times the input clock period. Square-wave rate generator Output will remain high until one-hall the count has been completed. and go low lor the other half 01 the count. Software triggered strobe Output remains high until software loads counl (N). N counts after count Is loaded, output goes low lor one input clock period. Hardware triggered strobe Output goes low lor one clock period N counts after rising edge counter trigger in· put. The counter is retrlggerable. Event counter On a jumper selectable basis, the clock input becomes an input from the external system. CPU may read the number of events occurring after the counting "window" has been enabled or an interrupt may be generated after N events occur in the system. Interrupt Request Lines Interrupt requests may originate from four sources. Two interrupt requests can be automatically generated by the USART when a character is ready to be transferred to the host board (i.e. receive buffer is full) or a character has been transmitted (i.e. transmit buffer is empty). In addition, two jumper selectable requests can be generated by the programmable timers. Installation The iSBX 351 module plugs directly into the female iSBX connector on the host board. The module is then secured at one additional point with nylon .40 .80 MAX ~~ ~L-~L____ ______L-______ SO_C_K_E_T______L-__ ~ ISBX 351 MULTIMODULE BOARD T 1.13 MAX ISBX CONNECTOR (MALE) .50 ~ ~ ~ CONNECTOR ____L-__'_SB_X__ (FEMALE) ____ _______ SO_C_K_E_T______L-__ ~lM'N Figure 2. Mounting Clearances (Inches) 2·18 =- intel' iSBX 351 RS232C CABLING RS449/422 CABLING CONNECTOR PIN 1 FIgure 3. Cable Construction and Installation for RS232C and RS449/422 Interface SPECIFICATIONS Word Size Data - . Serial Communications Synchronous - 5 - 8-bit characters; internal character synchronization; automatic sync insertion; even, odd or no parity generation/detection. 8 bits I/O Addressing 1/0 Addre•• XO, X2, X4, or X6 XI, X3, X5, or X7 Chip Selecl Funclion Write: Data 8251A USART Read: Data Write: Mode or Command Read: Status Asynchronous - 5 - 8-bit characters; break character generation and detection; 1, 1%, or 2 stop bits; false start bit detection; even, odd or no parity generation/detection. Write: Counter 0 (Load Count -<- N) X8 or XC Read: Counter 0 . Sample Baud Rate: 8251 USART Baud Rate (Hz)' Write: Counter 1 X9 or XD 8253 PIT XA or XE (Load Count -<- NI Read: Counter 1 Write: Counter 2 (Load Count -<- N) Read: Counter 2 XS or XF Write: Control Read: None NOTE: The first digit of each port 1/0 address is listed as "X" since it will change depending on the type of host iSSC microcomputer used. Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit of the 110 address. Access Time 250 nsec max Write - 300 nsec max Read - Nole Actual transfer speed is dependent upon the cycle time of the host microcomputer. 8253 PIT Frequency' (kHz, Solfware Selecfable) 307.2 153.6 76.8 38.4 19.2 9.6 4.8 2.4 1.76 Synchronous 38400 19200 9600 4800 2400 1760 Asynchronous -<- 16 19200 9600 4800 2400 1200 600 300 150 110 -<- 64 4800 2400 1200 600 300 150 75 - NOTES: 1. Frequency selected by 110 writes of appropriate 16-bit frequency factor to Baud Rate Register. 2. Baud rates shown here are only a sample subset of possible software-programmable rates available, Any frequency from 18.75 Hz to 614.4 kHz may be generated utilizing on-board crystal oscillator and 16-bit Programmable Interval Timer (used here as frequency divider), iSBX 351 Interval Timer and Baud Rate Generator Interfaces Input Frequency (selectable): iSBX Bus - 1.23 MHz ±0.1% (.813 flSec period nominal) Serial - configurable for EIA Standards RS232C or RS449/422 153.6 kHz ±0.1% (6.5 J1sec period nominal) EIA Standard RS232C signals provided and supported: Clear to Send (CTS) Data Set Ready (DSR) Data Terminal Ready (DTR) Request to Send (RTS) . Receive Clock (RXC) Receive Data (RXD) Transmit Clock (DTE TXC) Transmit Data' (TXD) Output Frequency: Rate Generator (Frequency) Real-Time Interrupt (Inlerval) Min. Max. Miri.' Max. Single Timer 1 18.75 Hz 614.4 kHz 1.63/iSec 53.3 msec Single Timer 2 2.34 Hz 76.8 kHz 13.0/iSec 426.7 msec Dual Timer3 (Counters o and 1 in series) 0.000286 Hz 307.2 kHz 3.26 psec 58.25 min Dual Timer 4 (Counters o and 1 in series) 0.0000358 Hz 38.4 kHz 26.0 /iSec 7.77 hrs. ali signals TTL compatible. EIA Standard RS449/422 signals provided and supported: Clear to Send (CS) Data Mode (OM) Terminal Ready (TR) Request to Send (RS) Receive Timing (RT) Receive Data' (RD) Terminal Timing (TT) Send Data (SO) NOTES: 1. Assuming 1.23 mHz clock input. Physical Characteristics 2. Assuming 153.6 kHz clock input. 3. Assuming Counter 0 has 1.23 mHz clock input. Width Length Height" - 4. Assuming Counter 0 has 153.6 kHz clock input. - Interrupts Weight - Interrupt requests may originate from the USART (2) or the programmable timer (2). * 7.24 cm (2.85 inches) 9.40 cm (3.70 inches) 2.04 cm (0.80 inches) iSBX 351' Board 2.86 cm (1.13 inches) iSBX 351 Board and Host Board 51 grams (1.79 ounces) (See Figure 2) Serial Interface Connectors Configuration Mode2 MULTI MODULE Edge Connector Cable Connector 8 RS232C DTE 26-pin 5 , 3M-3462-0001 3M3_3349/25 25-pin', 3M-3482-1000 RS232C DCE 26-pin 5 , 3M-3462-0001 3M3_3349/25 25-pin', 3M-3483-1000 RS449 DTE 40-pin', 3M-3464-0001 3M'-3349/37 37-pin',3M-3502-1000 RS449 DCE 40-pin', 3M-3464-0001 3M'-3349/37 37-pin', 3M-3ii03-1000 NOTES: 1. Cable housing 3M-3485-4000 may be used with the connector. 2. OTE - Data Terminal mode (male connector),-DCE - Data Set mode (female connector). 3. Cable is tapered at one end to fit the 3M 7 3462 connector. 4. Cable is tapered to fit 3M-3464 connect9r. 5. Pin 26 of the edge connector is not connected to the flat cable. 6. Pins 37, 39, and 40 of the edge connector are not connected to the flat cable. 7. May be used with cable housing 3M-3485-:-1000. 8. Connectors compatible with those listed may also be used. 2-20 iSBX 351 Electrical Characteristics Environmental Characteristics DC Power Requirements Temperature - 0 - 55°C, free moving air across the base board and MUL TIMODULE board. Mode RS232C Voltage +5V ±0.25V +12V ±0.6V -12V ±0.6V RS449/422 +5V ±0.25V Amps Reference Manual (Max.) 9803190·01 - iSBX 351 Serial 110 MULTIMODULE Manual (NOT SUPPLIED) Reference Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Ave., Santa Clara, California, 95051. 460 mA 30 mA 30 mA 530 mA ORDERING INFORMATION Description Part Number SBX 351 Serial I/O MUL TIMODULE Board 2·21 Co = iCSTM Industrial Control Series = . 3 iCS 80 INDUSTRIAL CHASSIS • MULTIBUS standard 4-slot backplane, expandable to 12 slots • Vertical board orientation for convection. cooling • 19-inch wide RETMA rack mounting or NEMA type backwall mounting. brackets • Four fans for forced-ciir cooling • Submitted for approval as recognized component aUL • 110/230V, 50160 Hz operation • Slide inlout mounting rails for iSBC power supplies - Quick disconnect cabling for serviceability - Your choice of supply • Lockable service panel • All front access serviceability ;",.. iSBC boards - Power supplies - Interrupt and reset buttons - Operation indicators and fuse • Recessed mounting space for signal. conditioninglwire termination panels The iCS 80 lridustrial Chassis provides industrially· oriented mbunting space for Intel single board computer (iSBC) products, associated iSBC power supplies, and related iCS 9XX analog and digital signal conditioning/termination panels. The base unit provides a 4-siot MULTIBUS backplane (iSBC 604) with expansion space and cabling to expand to 12 MULTIBUS backplane slots by adding additional 4-slot iSBC 614s as needed (up to two). Allbf the 25-plus Intel MULTlBUS bus-compatible iSBC boards can be inserted into any oneofthe 12slots. In addition, over 50 products from 30 independent manufacturers have been designed for mounting into the MULTI BUS backplane. Full MULTIBUS compatibility in the iCS 80 chassis also allows configuration of multiple single board computers to share system tasks through communication over the bus (through multimaster bus arbitration built on the multiple iSBC processors). les 80 FUNCTIONAL DESCRIPTION Power Supply Flexibility To provide a iTlodular base on which to build a vallety of configurations, no power supply is provided in the iCS 80 Industrial Chassis. Users choose one of the low cost Intel iSBC 635 (14-amp) or iSBC 640 (30-amp) power supplies based on their application. Slide in!out mounting rails are provided to match the iSBC 635 and iSBC 640 supplies, and quick disconnect cabling and connectors are provided for rapid service replacement. An AC wiring barrier strip allows simple wiring connections for integration into larger systems (see Figure 4). Self Contained Low Cost Controllers Small, self contained Industrial controllers can be configured with the 4-slot cardcage and ISBC 635 power supply. As shown in Figure 2, this packaging can also accommodate the iCS 9XX series signal conditioning! termination panels. Or Large Power and Point Counts in a Small Package At the high end of performance for the iCS 80 chassis, a user can build a 12-slot configuration with the Intel iSBC 640 Power Supply. This iCS 80 chassis can support the iSBC 86/1216-bit computer with 112K bytes memory (96K RAM, 16K ROM), 64 differential analog inputs, 180 digital inputs, 52 isolated digital outputs, and 8 analog outputs (four current loops); in total a 304-channel, mixed analog and isolated digital, input and output controller, large enough for most dedicated applications (see Figure 3). Industrial Rack Mounting The chassis mounts directly into 19-inch standard width RETMA (Radio-Electronics-Television Manufacturers Association) customer provided rack. Alternately, mounting brackets and power cabling access are provided for mounting directly on a backwall, such as the backwall panel of a NEMA-type (National Electrical Manufacturers Association), front-access-onlycabinet. Engineered for Industrial Applications The MULTIBUS slots are mounted vertically to Improve convection cooling and the top, bottom and sides are engineered to allow maximum air flow over the boards. Four fans are provided as standard to increase air flow, allowing users to eliminate or minimize the need for supplementary fans or air conditioning. Front Access Serviceability To simplify serviceability, front access is provided for all iSBC boards, the power supply, operation indicator lights, interrupt and reset buttons, and the AC power fuse. TOP VIEW 1 =~1'~ ~ -_-_~- 17-.4=:= = = :'1~ %. .. .. .. .. r L ·1 <;; ? Ie ::> ? 5 I• 19.0 0 0 7 'Tj- . .. .. .. .. i[][]o 15.9 11.97 a ~Itrr . _t 00000000 0 11.47 FRONT VIEW SIDE VIEW Figure 1_ iCS 80 Chassis Dimensions 3-2 => iCS 80 Typical Small Configuration • • • • • • .. • • Figure 2. Small Configuration ies 8-bit 8080 processor (iSSC 80/20-4) 2K bytes RAM 8K bytes ROM/EPROM 16 analog inputs 2 analog outputs 8 isolated digital inputs 8 isolated digital outputs 12 TTL outputs 12 TTL inputs so with ISBC 635, ICS 910 and ICS 930 Signal Conditioning/Termination Panels Typical Maximum Configuration • • • • • 16·bit 8086 processor (iSSC 86/12) 96K bytes RAM 16K bytes EPROM 64 analog inputs 4 analog voltage outputs • 4 analog current outputs (4-20 mAl • 132 Isolated digital inputs • 48 TTL digital inputs • 52 Isolated digital outputs (All iCS 9XX Signal CondltionlnglTermination Panels are not shown) Figure 3. iCS SO with 12 MULTIBUS Card Slots and iSBC 640 Power Supply, Large Configuration Figure 4. Rear View ICS SO Chassis Showing Power Distribution Panel, and Cabling from ICS"SO Chassis to ICS 9XX RETMA Mounted Signal Conditioning Panels (Top of ICS SO Chassis) 3-3 iCS 80 Lockable Service Panel Submitted for UL Recognition To assist in development, checkout and service, two push buttons are provided. The RESET button pulls low the initialize line (iiiiIT) on the MULTIBUS backplane. The INTERRUPT button pulls low one interrupt line On the MULTI BUS backplane (INT1). Logic within the iCS 80 en, sures that these buttons function with all versions of Intel single board computers. From the front of the iCS 80 chassis, without a CRT or other panel, an operator or service person can reset or interrupt on·going iCS 80 system operations to get attention, signal an alarm, or start a self-test operation. The iCS 80 chassis has been submitted to Underwriters Laboratories for approval as a U.L. listed component under the Underwriters Laboratories Safety Standard for Process Control Equipment, UL1092. When installed as described in theiCS 80 manual, the iCS 80 chassis provides adequate protection against shock, fire and casualty hazards, and should comply with most local and regional requirements for installation in ordinary locations. Mounting Space for Signal Conditioning/Wire Terminations Three indicator light emitting ·diodes record basic chassis status. POWER ON (GREEN); RUN (GREEN); and HALT (RED); the RESET or INTERRUPT buttons will remove the HALT state. The cardcages and power supplies in the iCS 80 chassis are recessed behind the front edge of the rack mounting ears to provide mounting space for the iCS 9XX series signal conditioning/termination panels and field wiring. For smaller systems with on Iy one or two iSBC 604/614 cardcages (4 to 8 slots), up to two iCS 910, iCS 920, or iCS 930 signal conditioning/termination panels can be mounted vertically over the area where the second orthird cardcage would mount (see Figure 2), The benefit of this design is a completely self-contained industrial chassis with iSBC cards, power supply, signal conditioning and field wiring terminations, all in one enclosure. SPECIFICATIONS Equipment Supplied A front panel key provides three positions: OFF (AC power off and key removable), ON (AC power on, push· buttons enabled, key unremovable), and LOCK (AC power on, pushbuttons disabled, key removable). iCS 80 industrial chassis, three fans forcardcages, one fan for power supply, 4-slotcardcage with MUL TIBUS backplane, control panel with switches, indicators, keylock, power distribution barrier strip, AC power fuse, line filter, 115V power cable, and logic for interrupt and reset buttons. An installation package is also provided, inciLiding a NEMA cabinet mouilting kit, power supply extension cables, and RETMA cabinet mounting screws, 110/230 VAC operation. Capacity Four slots for MULTIBUS compatible single board computers, memory, I/O or other expansion boards Expandable to 12 slots using customer plug-together iSBC 614 cardcages Front Panel Controls Pushbuttons RESET: Connected to Initialize/ on MULTIBUS backplane Software See the RMX/80 Real-time Multitasking Executive specifications for industrial related applications. In addition, system monitors for most of the Intel single board computers are available in the INSITE (Intel's Software Index and Technology Exchange) User's Program Library. INTERRUPT: Connected to Interrupt 1/ line on MULTIBUS backplane. Panel Indicator Lights (LEOs) POWER ON (green): + 5V power exists on the MULTIBUS backplane RUN (green): CPU is executing an instruction. Light goes out if CPU is in WAIT or HALT state HALT (red): CPU has executed a HALT instruction Physical Characteristics Height - 39.3 cm (15.7 in.) Width - 48.5 cm (19.0 in.) at front.panel 43.5 cm (17.4 in.) behind front panel Depth - 30.0 cm (12.0 in.) with all protrusions Weight - 16.8 kg (37.0 Ib) without power supplies Keylock OFF: AC power off, key removable ON: AC power on, push buttons enabled, key unremovable LOCK: AC power on, push buttons disabled, key removable Fuse - Environmental Characteristics (Ambient at iCS-80 air intake, bottom of chassis) Temperature (Ambient) Operating: O°C to 50°C (32°F to 122°F) Non-operating: - 40°C to + 85°C AC power (6A) Humidity - 3-4 Up to 90% relative, noncondensing at 40°C iCS 80 supply) peak-to-peak, max (DC to 500 kHz) Electrical Characteristics The iCS 80 chassis provides mounting space for either the iSBC 635 or iSBC 640 power supply. Unless otherwise stated, electrical specifications apply to both power supplies when installed by user in iCS 80 chassis. Output Transient Response - Less than 50 Ilsec for ±50% load change. Maximum Watts Dissipation (load plus losses) (iSBC 640 supply), 250W (iSBC 635 supply) Input Power Frequency: 47 to 63 Hz. Voltage (Nominal) (Single Phase): 100, 115, 215, or 230 VAC +10%, jumper selectable. ISBC635 3.0A max 1.5A max 315 watts With Current: (Including fans) Power, max: ISBC640 5.6A max 2.BA max 5BO watts Input Voltage 103 VAC 206 VAC Overvoltage ISBC 635 + 14V to +16V + 5.BV to + 6.6V - 5.BV to - 6.6V -14V to -16V Protection ISBC 640 + 14V to + 16V + 5.BV to + 6.6V - 5.BV to - 6.6V -14V to -16V With Installation Complete instructions for installation are contained in the iCS 80 Site Planning and Installation Guide, including RETMA and NEMA cabinet mounting, and field signal, ground wiring and cooling suggestions. Warranty The iCS 80 Industrial Chassis is warranted to be free from defects in materials and workmanship under normal use and service for a period of 90 days from date of shipment. Output Power Voltage + 12V +5V -5V -12V Output Current (max) iSBC635 ISBC640 2.0A 4.5A 14.0A 30.0A 0.9A 1.75A O.BA 1.75A Reference Manuals 9800799A :- iCS 80 Industrial Chassis Hardware Reference Manual (SUPPLIES) 9800798 - iCS 80 Industrial Systems Site Planning and Installation Guide (SUPPLIED) Combined Line/Load Regulation - ±1'10 at ±10% static line change and ±50% static load change, measured at the output connector (±0.2% measured at the power supply under the same conditions). Remote Sensing regulation. 9800708A - iSBC 604/614 Cardcage Hardware Reference Manual (SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Provided for +5 VDC output line Output Ripple and Noise-10 mV (iSBC 635and iSBC 640 ORDERING INFORMATION The iCS 80 I ndustrial Chassis must be ordered as a kit with an Intel power supply of your choice. Ordering as a kit will ensure shipment olthe power supply and iCS 80 chassis at the same time. Typical configurations and ordering instructions are: Part Number Description ICS 80 Kit 635 iCS 80 system consisting of: iCS 80 Industrial Chassis iSBC 635 Power Supply ICS 80, Kit 640 iCS 80 system consisting of: iCS 80 Industrial Chassis iSBC 640 Power Supply 500W 3-5 iCS 910/920/930 SIGNAL CONDITIONING/TERMINATION PANELS • Interconnects iSBC and digital I/O ports to field signal/control wiring • Digital signal conditioning (iCS 920/930) - Sockets for optically isolated input filters and solid state output switches - Pad space for transient suppressors, current limiting resistors, and voltage dividers - Socketed fuse for overload protection (iCS 930) - LED/channel status indicators • Ribbon cable connection from panel is pin compatible with iSBC analog, CPU, and digital board I/O ports • Barrier strip screw terminals for - iCS 910: 32 single-ended analog inputs (or 16 differential signal plus shield) plus four analog voltage outputs or two analog 4 to 20 rnA current outputs - iCS 920: 24 medium power digital inputs and/or outputs (55V, 300 rnA max) - iCS 930: 16 high power AC or DC digital inputs or outputs (280 VAC, 3A max) • Engineering printed circuit mounting space for customer analog input components (iCS 910) - Noise liters - Current loop resistors - Open circuit detection resistors - Voltage divider resistors - Thermistor bias current • Flexible mounting kits for - 19" width RETMA rack - N EMA type backwall - iCS 80 Industrial Chassis • Submitted for UL recognition The iCS 910/920/930 Signal Conditioning/Termination Panels are heavy duty printed circuit boards with screw terminations which allow industrial customers to easily connect their heavier gauge field signal wiring to Intel's line of 8and 16-bit single board computers, and iSBC analog and digital I/O boards. Flat ribbon cables connect the iCS 910 panels to any of the Intel iSBC 700 series analog input and output board pin-outs. Flat ribbon cables also connect the iCS 920 panels and iCS 930 panel to the 50-pin digital I/O ports (8255 or UPI) on Intel's single board computers and digital I/O boards. Power for opto-isolators or line drivers (+5 VDC) can be supplied via this cable from the iSBC boards. Jumpers and a screw terminal block are provided on the iCS 920/930 panels to allow an external supply of +5V power. A similar jumper/terminal block is provided on the iCS 910 panel to allow users to connect external +15V (or greater) compliance voltage for larger analog output loads. 3·6 .c, iCS 910/920/930 FUNCTIONAL DESCRIPTION COMMON TO iCS 910/920/930 Large Wire or Spade Lug Connections The barrier strip screw terminations on the iCS 910/920/ 930 panels provide familiar connection points for factory electricians to terminate the heavier gauge wiring often pulled through conduits from sensors or control elements. These screw terminals securely connect up to 14 AWG gauge wire size (16-gauge on iCS 910/920 panels). Alternately, spade lugs can be crimped on field wiring and inserted under the screw terminals. Mounting Flexibility and Serviceability The iCS 910/920/930 panels were designed to be physically separate from iSBC boards or the iCS 80 chassis to allow maximum mounting flexibility and ease of serviceability. The panels and field wiring can be mounted in one area of the cabinet where electricians have access. Flat ribbon cable can then be run to the area where control electronics technicians have access. Figure 2. iCS 910/920 Signal Conditioning/Termination Panel Mounted on a NEMA Cabinet Backwall The iCS 910/920/930 panels may b'e mou nted horizontally in a 19" standard width (RETMA) rack using a recessed mounting panel (see Figure 1). Alternately, the panels can be mounted on a cabinet wall (e.g., NEMA cabinet backwall) using standoffs provided (see Figure 2). 0;-, for the most compact packaging, users can mount up to two iCS 910/920/930 panels vertically, directly on the front of the iCS 80 chassis using standoffs and holes provided (see Figure 3). A black metal labelling strip is provided with each iCS 910/920/930 panel. White, blank gummed labels are in· cluded so that users can custom identify each input or output channel. A clear plastic cover is provided to pro· tect against inadvertent touching or damage to the screw terminals or customer mounted components. Figure 3. iCS 910/930 Signal Conditioning/Termination Panels Mounted on iCS 80 Industrial Chassis iCS 910 ANALOG SIGNAL CONDITIONING/TERMINATION PANEL Mixed Analog Input and Output Signals A single iCS 910 panel connects up to 32 single ended analog inputs (or 16 differential analog inputs plus shield) to the iSBC 711 or iSBC 732 analog input boards. In addition, the same iCS 910 panels can connect up to four analog output voltages from the iSBC 724 analog output board, or two voltage or 4 to 20 mA current loop outputs from the iSBC 732 combination analog input/output board. Three flat ribbon cables are included in the iCS 910 installation kit (two analog inputs, one analog output) to route signals to iSBC 711/724/732 boards. Figure 1. iCS 930 AC and iCS 920 Digital Signal Conditioning/Termination Panel Mounted on a 19" Width RETMA Rack 3·7 =. iCS 910/920/930 Engineered Signal Conditioning Mounting Space circuit area onto which users may mount components to signal condition analog input signals. Pad traces and holes are designed to allow easy mounting of R-C noise filters, input voltageresistorldivider networks, current loop input resistors, open circuit detection resistors, or to supply thermistor bias current (see Figure 4 for schematic of a typical analog input channel). Printed circuit traces on the iCS 910 panel connect each screw terminal analog input channel to the flat ribbon cable connector. Users can jump straight through signal connections if they desire. Each input channel trace, however, passes through a custom engineered printed +V I I OPEN CIRCUIT DETECTION OR THERMISTOR BIAS RESISTORS :~ ~~ BARRIER STRIP I I .... ..., :~ E~~~ENT I 1 I I _L .: c VOLTAGE DIVIDER RESISTOR 1 1 r - --A.,"'..,'''v- - --, I I I I .... J NOISE FILTER -T- "". RESISTOR 1 FIELD WIRING FROM TRANSDUCER I .> ~: I 1 I I I _.L_ DECOUPLING I I CAPACITORS FOR -T- -r I I I -v C~~AF~m=s SINGI\;Jp~~DED I SHIELD RIBBON CABLE TO ISBC-711/732 ANALOG INPUT BOARD _L I I I !Q]'---------------------<6)-------~ Figure 4. iCS 910 Analog Input Signal Conditining Examples mounting voltage divider/threshold resistors and protection diodes. iCS 920 DIGITAL SIGNAL CONDITIONING/TERMINATION PANEL Groups of four inputs can have mixed voltage levels, opto-isolation, or straight through connections in groups of two. Output groups of four can be mixed optoisolated or high current drive in groups of two. DIP components from a wide variety cif vendors are selected and inserted by users based on their application. The iCS 920 manual recommends several alternative components and bffers design assistance for your I/O configuration. Digital signal conditioning examples for several common industrial voltages are shown in Table 1 and in the diagrams below (see Figure 5). The iCS 920 panel interconnects up to 24, 2-wire digital input or output channels from barrier strip screw terminals to the 16- or 24-bit digital 1/0 ports, standard on many Intel single board computers and digital 1/0 expansion boards. Screw terminals allow for one each 16 AWG size wire for differential (2-wire) connections or two each AWG IS-gauge wire for daisy chaining grounds or power for external contact sensing. Flexibility in Isolation and Serviceability Active Channel Indicators Dual-in-line sockets are in series with each channel (see Figure 5) to allow customer jumpering for straight through connections (TTL I/O), or for insertion of popular DIP packaged opto-isolators or digital output high current driver transistors. Circuit pads are available for Light emitting diodes (LEDs) are mounted adjacent to each channel's screw terminals and may be jumperedin to indicate the Hi-Lo status of each of the 24 input or output channels. . 3-8 iCS 910/920/930 iSBC BOARD CURRENT LIMITING AND THRESHOLD RESISTORS OPTO·ISOLATOR SOCKETS I I -;;'.~ Til 117) I ,- + + I I I IN FROM FIELD RIBBON CABLE SCREW TERMINALS 8255 iSBC 902 -= I 1 OF 4 CHANNELS I I I L ___ -1 OPTICALLY ISOLATED DC INPUT EXAMpLE (iCS-920 panel) + OPTO·ISOLATOR SOCKETS (e.g. TIL 113) +'I + I I ,-----] I iSBC BOARD I RIBBON CABLE 8255 I I I '-------~ I .-J OPTICALLY ISOLATED DC OUTPUT EXAMPLE (iCS-920 panel) iSBC BOARD LINE DRIVER OPTO·ISOLATOR LED SOCKETS 8255 I I I L ____ J -1 CURRENT DRIVER OUTPUT (55V. 300 mAl EXAMPLE (iCS-920 panel) Figure 6. Digital Signal Conditioning Examples 3·9 iCS 910/920/930 Table 1. iCS 920 Digital 1/0 Signal Conditioning Plug·ln Component Examples Digital Voltage Input or Output Load Voltage Maximum Input Current (mA) Threshold Voltage (V) Oplo·lsolators" Diode Protection" 50 50 40 3 6 6 TIL 117 TIL 117 TIL117 1N4002 1N4002 1N4002 20 12 4N36 1N4002 Oplo-Isolated Input 5 VDC 12 VDC 24 to 26 VDC 48 VDC Maximum Output Currenl (mA) Line Driver" Opto·lsolators" Opto·lsolated Output TIL113 TIL119 100 - 300 T175472 - 300 150 - - GE4N40 MCS 2 12 VDC 24 VDC 100 100 48 VDC MCS 2 Current Drivers 55 VDC Half Wave Rectifier Outputs 24 VAC SCR 115 VAC SCR 'Example component - alternate source components are listed in the iCS 920 Hardware Reference Manual. iCS 930 AC Signal Conditioning/Termination Panel each channel can be individually mixed for AC or DC in· put (or AC or DC output). The user pays only for those channels implemented. User supplied compatible modules are shown in Table 2. The iCS 930 panel interconnects 16 2-wire digital input or output channels from barrier strip screw terminals to 16 bits of the digital I/O ports available on many Intel single board computers and digital I/O expansion boards. The iCS 930 panel differs from the iCS 920 digital signal conditioning/termination panel in that the iCS 930 panel handles higher AC or DC voltages and currents (up to 280V, 3A), such as those found on many 115 VAC machines, motor starters, and industrial control panels. The iCS 930 panel is also recommended for optically isolated DC outputs greater than 100 mAo DC and AC input modules are current actuated and thus provide a 5·ms filter against spurious noise spikes or contact bounce. AC solid state output modules provide zero crossing turn on to minimize arcing. Protection Circuitry Each of the 16 channels contain a socketed fuse to pro· tect against overload. In addition, mounting pads are available on each channel output for user supplied voltage transient RC "snubber" components or inductive pulse suppression, e.g., metallic-oxide·varistor (MOV) for large motor starting. The iCS 930 screw terminals accept up to 14 AWG size wire each for differential (2 wires per channel) connec· tions, or two 14 AWG size wires for daisy chaining grounds or power from external sources. Active Channel Indicators Modular Isolation/Switching with Easy Serviceability Light emitting diodes (LEDs) are mounted adjacent to each channel's screw terminals and opto·module to indicate Hi·Lo status of that channel and to assist in troubleshooting servicing. Each iCS 930 panel accepts up to 16 user supplied, op· tically isolated input modules or optically isolated solid state switches, for either AC or DC voltages (see Figure 6). Each module is screw mountable/replaceable and can be mixed for AC or DC input, or AC or DC output, in groups of four. Among groups of four inputs (or outputs) Examples of iCS 930 input and output schematics are shown in Figure 6. 3·10 -= iCS 910/920/930 Table 2. Opllcally Isolated Modules Compallble with ICS 930 Signal CondlllonlnglTermlnallon Panel Signal Conditioning Desired Voltage Rallng Maximum Input Current Opto·22 Numberr Motorola Number· AC Input - 95 to 130 VAC 180 to 280 VAC 10 mA 10 mA IAC5 IAC5A IAC5 DC Input - 5 !lsec Filter Fast, 50 !lsee On 10 to 32 VDC 4 to 16 VDC 32 mA 14 mA IDC5 IDC5B IDC5 AC Output 12 to 140 VAC 24 to 280 VAC 3A 3A OAC5 OAC5A OAC5 DC Output 10 to 60 VDC 200 VDC 3A 1A ODC5 ODC5A ODC5 115 VAC 220 VAC Output Current Rating • Motorola and Opto·22 sales offices are localed In North America, Europe, and Japan. +5V -, I r----------- SCREW TERMINALS I + I I I 3 OPTO·ISOLATOR ,-I RIBBON CABLE --, I II I I L ____ ...lI ISBC·902 8255 I I I ISBC BOARD ~ AC INPUT EXAMPLE (iCS-930 panel) +5V LED r---------, TRANSIENT ! 3AMP (§) f':~oad r----.., ?-- ~IP-JY I I RIBBON CABLE 8255 ZENER DIODE I I ..J ISBC BOARD DC SOLID STATE OUTPUT r LED ZEROYOLTAGECIRCuiT-l ~______Q-______~______1~1~~~4 3 RIBBON CABLE ~~.--~~---~~~--~ FUSE3A I. I L __ ~g~~~ _ _ ...J I I ...J AC SOLID STATE RELAY OUTPUT EXAMPLE (iCS-930 panel) Figure 6. Typical ICS 930 Signal Conditioning Examples 3-11 c::::'. 8255 iCS 91019201930 FLAT RIBBON CABLE (3 Included with ICS-910 and 1 with IC$-920 and 930 EDGE CONNECTOR TO ISBC ANALOG OR DIGITAL BOARDS ICS.910, 920. or 930 SIGNAL CONDITIONING PANEL TERMINAL LABEL STRIP ~ RETMA BRACKET OR NEMA BACKWALL MOUNTING SPACERS HIGH VOLTAGE PROTECTION CLEAR PLASTIC COVER BLANK LABELS TO IDENTIFY INPUT/OUTPUT CHANNELS Figure 7. Mounting Arrangements for Signal ConditioninglTerminal Panels SPECIFICATIONS (For iCS 910/920/930 panels unless otherwise specified) 'iCS 9)0 455 gm(16 Ol) Number of Lines iCS 920 iCS 930 (Minimum. PC panel only) Weight: 455 gm (16 Ol) 681 gm (24 Ol) (Maximum with all components and mounting kit installed) iCS 910 Panel Analog Inputs - Sixteen 3-wire (differential signal plus shield) or 32 single ended Analog Outputs - Four 2-wire voltage output (iSBC 724 Analog Board) or two 2-wire current output (iSBC 732 Analog Board) iCS 920 Panel -'- Zero to 24 digital inputs or outputs in groups of four iCS 930 Panel - Zero to 16 digital inputs or outputs in groups of four 1.6 Kg (56 Ol) Depth: 1.8 Kg (64 Ol) 3.4 Kg (120 Ol) (With compone'nis and clear plastic cover installed) 5.08 cm(2.0 in.) 5.08 cm (2.0 in.) 5.08'cm(2.0 in.) (Barrier strip) Connectors: 2/56 screws 48 AI 12 AO 2 power 2156 screws 48 DIlDO 2 + 5V power 6132 screws 32 DIlDO 2 + 5V power (J1. J2, J3 to iSBC boards) 50·pin 0.1 in. centers (2.54 mm) Isolation Characteristics line-to-line Isolation - 250 VDC or RMS AC (iCS 910/920 panels), 500 VDC or RMS AC (iCS 930 panel) 50·pin 0.1 in. centers (2.54 mm) 50·pin 0.1 in. centers (2.54 mm) (Mating connector: 3M 3415·0000 or TI H3·12125) Input/Output Isolation - 250 VDC or RMS AC (iCS 920 panel), 500 VDC or RMS AC (iCS 930 panel) Maximum Distance from iSBC Boards The iCS 910/920/930 panels are shipped with 4-ft. long cables., With customer provided 50-conductor or,twisted pair ribbon cable. however. the iCS 910/920/930 panels can be mounted remote from the iSBC analog or digital 1/0 boards. In electrically quiet environments using normal iSBC board line driver/receivers. the iCS 910/920/930 panels should be able to operate up to 25 ft. (7.69m) from the iSBC board. Physical Characteristics Width: 36.63 cm (14.65 in.) Height: 8.13 cm (3.25 in.) Thickness: 0.24 cm (0.093 in.). iCS 910/920panei 0.32 cm (0.125 in.). iCS 930 panel 3·12 - .:::;;;;.:. iCS 910/920/930 ies 930 - AC Signal Conditioning/Termination Panel, one 4-ft, 50-conductor ribbon cable with connectors, and Installation kit below Electrical Characteristics Power Requirements iCS 920 panel- +15V ±5%, 25 mA max ifiSBC 724 or iSBC 732 ±15V power is used for user mounted open circuit detection, or thermistor bias components. Additional power must be supplied via +15V terminal block. Installation kit consisting of RETMA (19" rack) mounting bracket, clear plastic safety cover, labelling strip with blank gummed labels, hex standoffs and mounting screws iCS 920 panel - +5V ±5%, 1.46A max (24 channels high current drive) ICS 920 Channel Conllgurallon Documentation Supplied Maximum per Channel Currenl (Includ.s pullups, LEOs, Isolalors, drivers) TTL in TTL out Opto·lsolated in Opto.isolated out Open collector driver oulput 23 23 23 41 61 A schematic diagram and assembly diagram are supplied . with each iCS 910/920/930 panel. mA mA mA rnA rnA. Reference Manuals 9800800A - iCS 910 Analog Signal Conditioriing/Termination Panel Hardware Reference Manual (NOT SUPPLIED). Nole: Both iCS 920 and iCS 930 panels have jumpered provision for externally supplied +5V power via a screw terminal block. 98008D1A - iCS·920 DigitalSignal Conditioning/Termination Panel Hardware Reference Manual (NOT SUPPLIED) iCS 930 panel - +5V ±5%, 320 mA max. Output AC or DC channel: 20 mA/chan max; Input AC or DC channel: 12 mA/chan max. 9800802A - iCS 930 AC Signal Conditioning/Termination Panel Hardware Reference Manual (NOT SUPPLIED) Maximum Power Dissipation iCS 910 panels - 3 watts with 16 channels analog input signal conditioning and +15V external compliance voltage iCS 920 panels - 12 watts with 24 channels each containing high current driver outputs iCS 930 panels - 80 watts with 16 channels of AC or DC output 9800798A - iCS 80'Systems Site Planning and Installatjon Guide (NOT SUPPLIED), but supplied with iCS 80 Industrial Chassis Reference manuals are shipped with each product only if designated SUPPLIED (see' above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Underwriters Laboratory (UL) Recognition The iCS 910/920/930 signal conditioning/termination panels have been submitted to Underwriters Laboratories for approval as a UL recognized component under the UL safety standard for process control equipment, UL 1092. Installation Complete instructions for installation and service are contained in the applicableiCS 910/920/930 Hardware Reference Manual. Additional system level information is available in the iCS 80 Systems Site Planning and Installation Guide, including RETMA and NEMA cabinet mounting, field signals, ground wiring and cooling suggestions. Environmental Characteristics Operating Temperature - 0 to 70°C (32°F to 158°F) Relative Humidity - 0 to 90%, noncondensing Hardware Supplied ICS 910 - Analog Signal Conditioning/Terminating Panel, three 4-ft, 50-conductor flat ribbon cables with connectors, and Installation kit below ICS 920 - Digital Signal Conditioning/Termiriation Panel, one 4-ft, 50-conductor flat ribbon cable with connectors, and installation kit below Warranty The iCS 80 Industrial Chassis is warranted to be free from defects in materials and workmanship under normal use and service for a period of 90 days from date of shipment. ' ORDERING INFORMATION Part Number Description iCS 910 Analog signal conditioning/ termination panel iCS 920 Digital signal conditioning/ termination panel iCS 930 AC signal conditioning/termination panel 3·13 . ..:...::-..:::::........:"...... iSBC 941 INDUSTRIAL DIGITAL PROCESSOR • Compatible with 8041A Universal Peripheral Interface (UPI·41J,\) sock.ets such as those provided on I.htel iSBC 569 Intelligent Digital Processor • Provides measurement and control of common industrial digital input and . output signals . - Sense change state - Pulse counting - Pulse generation - Period measurement -. Frequency measurement • Applications include - Switch senSing - Motor speed control - Stepper motor actuation - Serial communications • Off·loads host processor from time· consuming task of digital 1/0 processing • 16 programmable 1/0 lines, TTL compatible • Simplified command protocol with MCS 80/85/86 "Master" Processor • Single + 5V supply The iSBC 941 Industrial Digital Processor is a 40;'pin DIP device which provides the user with easy-to-use processing of digital input and output signals desired in many industrial automation environments. Onaof nine digital I/O functions can be selected.at anyone time for measuring, counting, or controlling up to 16 separate I/O lines. Additional utility commands allow reading or setting the condition of unused I/O lines. Simplex serial input and output modes can assemble or disassemble bytes transmitted asynchronously over TTL lines, including insertion and deletion of start/stop bits. The device has two a-bit, TTL compatible I/O ports. BLOCK DIAGRAM PIN CONFIGURATION Vee Vee .. . EA CLOCK { ii6 WI! SYNC CO~~~N:~~:~;. CONTROL INTERFACE 00-07 {Rii \Vii ~ CS Vss p"-P,, } 8·BITII0 RESET . Do :~ Vss Voo PORTS P20 .. P27 } To, T, TEST INPUTS .SVN·C . '-----" 3-14 -= iSBC 941 Stepper motors designed for up to eight phase control may be controlled directly or stepper motor translator signals may be generated .. FUNCTIONAL DESCRIPTION Industrial Digital Processor Designed to operate as a slave device, the iSBC 941 processor may be requested to implement one of nine Primary Functions. These Primary functions are subrou· tines which are stored in program memory of the iSBC 941 device. Each Primary Function has a specific 1/0 task. Available Primary Functions include: EVENT - Monitors and counts up to eight input lines for event counting or comparison to a preset count for each line. Interrupts may be generated or counter can be read 'on-the-fly' without changing its state. FCOUNT - Measures frequency of one of eight digital inputs over a programmable period. Inputs may be selected under user program control or iSBC 941 processor may be requested to automatically scan inputs in sequential order, update, and hold or interrupt for reading each 16-bit counter. Input frequencies up to 18 KHz may be measured. FREQ - Any of the sixteen UPI processor 1/0 lines that are not used by a Primary Function are available for general pur· pose use; e.g., direct status reads or latched digital out· puts, through the use of Utility Commands. Commands recognized by the iSBC 941 Industrial Digital Processor are defined by one of two categories, Control Commands or Utility Commands. Control Commands are used to start and stop a Primary Function. Utility Commands are typically associated with moving a byte of information or reading the status of the iSBC 941 processor through the COMMANDIDATA Bus Buffer. Control Commands available are: ENFLAG - Enables the iSBC 941 processor to send interrupts via its 1/0 lines to the host processor. INITPF - Generates up to eight gated frequency outputs with separately programmable pulse width and periods and complementary synchronous outputs. Selects the desired Primary Function and initializes parameters used by the Primary Function. LOOP - Continuously executes the selected Primary Function at a specific rate. PERIOD - Measures the period of up to four in· puts (Sing Ie cycle). PACIFY - SCAN - Monitors up to 16 input lines for changeof-state and direction of change. Change-of-state interrupts may be generated. User can individually disable inputs. Resets all iSBC 941 processor 1/0 lines to the input state and clears all control variables. PAUSE - Commands the iSBC 941 processor to exit the LOOP or INITPF mode. SERIN - Enables simplex reception and 8-bit byte assembling of asynchronously transmitted serial data bits for communications applications. Includes detectionl deletion of start/stop bits. Baud rates up to 1200 baud may be programmed. SEROUT - Enables simplex transmission of asynchronous serial data bits for communications applications. Includes insertion of start/stop bits. Baud rates up to 1200 baud may be programmed. SHOT1 - Emulates a gated one-shot pulse generator (edge triggered and retriggerable modules) with programmable delay and period. Complimentary, synchronous one-shots can be created on separate output lines, on up to eight lines. STEPPER - Utility Commands include: Generates up to eight programmable outputs that may be used for control of stepper motors. Step rate, step count, and step direction are user defined. CLRP1 (CLRP2) Sets (to logic level 0) selected iSBC 941 processor Port 1 (port 2) output lines. All other lines are unaffected. ENP11N (ENP2IN) Enables user-defined mask to inhibit the writing of'O's by the iSBC 941 processor to Port 1 (Port 2) input lines. This function is used by SETP1 (SETP2), CLRP1 (CLRP2), STEP and LOOP. IDEN - Requests the identity code of the iSBC 941 processor accessed. LATCH - Transfers to holding area for reading all eight counters used by the EVENT Primary Function. RDEC - Enables host processor to read one of eight user-specified event accumulators used by the EVENT Primary Function. RDFQ - Reads bytes from the iSBC 941 processor's 3·15 c. iSBC941 first-in-first-out (FIFO) buffer (used by . SCAN andSEROUT Primary Functions). R DH R - (5) Enable selected SCAN input lines (Parameter byte) (enabled in groups of eight) Enables the host processor to read the contents of the iSBC 941 holding register specified (used by PULSE, PERIOD, and EVENT Primary Functions), RDIDV - Enables the host processor. to read the iSBC 941 processor's input-data-valid (IDV) flags. RDLC - Enables host processor to read one of eight user specified EVENT counters previously stored by LATCH command. RDP1 (RDP2) - Reads data byte present at iSBC 941 processor Port 1 (port 2) and sends to host processor. SETOE - Sets output enable parameter bits. (6) Terminate parameter list (7) Enable iSBC 941 processor inter- (Command byte) rupt outputs .. (B) Request execution - Sets the Time Reference Period scale factor for value. WRP1 (WRP2) - Allows host processor to write to iSBC 941 processor Port 1 (Port 2). Signal P1o-P17 B·bit, PORT 1 Quasi·bidirectional I/O lines. P20 -P27 B-bit, PORT 2 quasi-bidirectional 1/0 lines. Control can configure P24 as OBF (Output Buffer Full), P2Sas IBF (Input Buffer Full) to send interrupt signals to master CPU. iSBC 941 functions may be implemented with minimum software overhead required of the host processor. An easy·to·implement protocol ensures that communica· tion between the iSBC 941 processor and host CPU is straightforward and uncomplicated. Implementing a Primary Function involves simple pro· gramming; the host processor transmits to the ISBC 941 processor a command byte followed by parameter bytes (the number of parameter bytes required is dependent upon the Primary Function selected). For example,to execute the Primary Function SCAN: WR . I/O write input which enables the master CPU to write data and command words to the iSBC 941 COMMANDIDATA BUS BUFFER. RD I/O read input which enables the master CPU to read data and status words from the COM· MANDIDATA BUS BUFFER or status register. CS Chip select input used to select one iSBC 941 processor out of several connected to a com· mon data bus. Ao Address input used by the master processor to indicate whether byte transfer is data or com· mand. To, T1 Input pins used by various iSBC 941 processor routines. x1, X2 Inputs for a crystal, LC or an external timing signal to determine the internal oscillator frequency. SYNC Output signal which occurs once per iSBC 941 instruction cycle. SYNC can be used as a strobe for external circuitry. RESET Input used to reset status flip·flops and to prepare iSBC 941 processor to receive com· mands. (Command byte) (2) Select SCAN as Primary Function (Parameter byte) and select internal or external time reference (3) Program Time Reference Period (Parameter byte) (scan rate - this byte is required only if internal time reference was selected in (2) ) (4) Define return message format Description Three·state, bidirectional COMMANDIDATA BUS BUFFER lines used to interface the iSBC 941 processor to an B·bit master system data bus. Simple Command Protocol (1 ) Initialize iSBC 941 processor (Command byte) PIN DESCRIPTION - Sets (to logic level 1) selected iSBC 941 SETP1 (SETP2) processor Port 1 (Port 2) output lines .. All other lines are unaffected. SETSF (Command byte) (Parameter byte) 3-16 Vee +5V power supply pin. V DD + 5V during normal operation. Vss Circuit ground potential. EA Circuit ground potential. SS Connect to +5V through 10K-ohm pu II-up resistor iSBC 941 ELECTRICAL CHARACTERISTICS 'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this Absolute Maximum Ratings* Ambient Temperature Under Bias ......... O·C to 70·C Storage Temperature ............. - 65·C to + 150·C Voltage on Any Pin With Respect to Ground .......................... 0.5V to + 7V Power Dissipation ......................... 1.5 Watt specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. D.C. and Operating Characteristics TA=O·C to 70·C, vss=ov, vcc= +5V ±5% Min. Max. Unit V il Input Low Voltage (All Except X t , X2) -0.5 0.8 V VIHl Input High Voltage (All except Xl, X2, RESET, WR, CS) 2.0 Vcc V VIH2 Input High Voltage (Xl, X2, RESET) 3.0 Vcc V V IH3 Input High Voltage (WR, CS) 2.2 . Vee V VOL1 Output Low Voltage (D 2-D 7, Sync) 0.45 V VOl2 Output Low Voltage (All Other Outputs Except Prog) . 0.45 V IOl= 1.6 rnA V OHl Output High Voltage (Do-D7) 2.4 V IOH= - 400,..A V OH2 Output High Voltage (All Other Outputs) 2.4 V IOH= -50,..A III Input Leakage Current (To, T l , RD, WR, CS, A o,) ± 10 ,..A VSS~VIN~Vee loz Output Leakage Current (Do-D7' High Z State) ± 10 ,..A V ss + 0.45~VIN~Vee ILil Low Input Load Current (P lO P17, P2O P27) 0.5 rnA V ll =0.8V Ill2 Low Input Load Current (RESET, SS) 0.2 rnA V ll =0.8V 100 Voo Supply Current 15 rnA lee+ 100 Total Supply Current 125 rnA Max. Unit Symbol Parameter Test Conditions IOL=2.0 rnA A.C. Characteristics TA=O·C to 70·C, vss=ov, vcc=voo= +5V ±5% DBB READ Symbol' Parameter Min. Test Conditions . tAR CS, AD Setup to RD~ tRA CS, AD Hold After RDt tRR RD Pulse Width tAD CS, AD to Data Out Delay 225 ns C l =150pF tRO RD~ 225 ns C l =150pF tROF RDt to Data Float Delay '.100 ns :.- 0 ns 0 ns 250 ns to Data Out Delay tRY Recovery Time Between Reads And/Or Write 300 tey Cycle Time 2.5 15 ,..s Min. Max. Unit .. ns DBB WRITE Symbol Parameter tAw CS, AD Setup to WR~ tWA CS, AD Hold After WRt tww WR Pulse Width tow Data Setup to WRt 150 ns two Data Hold Aftert WRt 0 ns 3·17 0 ns 0 ns 250 ns Test Conditions iSBC 941 1. READ OPERATION-DATA BUS BUFFER REGISTER. C"S OR AO =x K -"'-1 . IRV 'RR _ 'I -tRA- li \ _f (SVSTEM'S ADDRESS BUS) RQ \ (READ CONTROL! _ tAO _IOF , 2. WRITE OPERATION-DATA BUS BUFFER REGISTER. ~ORAO =>i~----~D< " "·l r \{ WR AOOA ESS BUS) "·~·n-'w.J , . - - - - - - - - - - - - - - - (WRITE CONTROL) ~'ow~ DATA BUS DATA ) ONPUT,, _ _ _ _ _ M_AV_C_"_AN_G_' _ _---J (SYSTEM'S -'wo _OATAVAlIO_W DATA V\_______MA_V_C_"A_N_G_' _ _ __ Reference Manuals 9803077 - iSBC 941 Industrial Digital Processor User's Guide (NOT SUPPLIED) if deSignated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Reference manuals are shipped with each product only ORDERING INFORMATION Part Number Description SBe 941 Industrial Digital Processor 3·18 0= Run- Time Systems Software 4 iRMX 80 REAL·TIME MULTI·TASKING EXECUTIVE • Small, efficient nucleus • Designed for Intel® iSBC 80/10B, iSBC 80/20-4, 80/24 and iSBC 80/30 based applications • Simple user task interface • Comprehensive 1/0 support • Completely user configurable through interactive configuration utility • Library of flexible modules • Structured application environment • Priority-oriented scheduling The Intel® iRMX 80 Real-Time Multi-Tasking Executive is an easy-to-use, sophisticated software system which operates on Intel's 8-bit single board computers and System 80 packaged systems. The iRMX 80 executive provides real-time facilities for priority-based resource allocation, intertask communications, standard 1/0 device control, and other features suitable for many applications including medical electronics, industrial process control,instrumentation, test systems, and data communications. The iRMX 80 package provides the framework that allows system developers to begin immediate application software implementation. The implementation and integration process is aided by the Interactive Configuration Utility (ICU80) program, a configuration tool which accelerates the development process. Figure 1_ Structure Diagram 4-1 iRMX 80 time facilities such as intertask communication and control are included. FEATURES The iRMX 80 executive provides users of Intel Single Board Computers simple, easy-to·use tools for creating a wide range of application systems. The most popular features of the iRMX 80 are: Priority-Oriented Scheduler· The iRMX 80 scheduler insures that the highest priority task which is ready to execute is given system control, allowing the application system to be responsive to its external world. Structured Environment The iRMX 80 executive provides a consistent structure, as diagrammed in Figure 1, from application to application thus allowing experience gained on one system to be easily transferred to others. Often, entire programs may be used in multiple applications. Comprehensive 1/0 Support The iRMX 80 libraries contain support for a wide range of 1/0 boards supplied by Intel, simplifying the addition of peripherals to an application system. For applications which require custom boards the iRMX 80 device handler philosophy allows easy addition of user written handlers. Simple Interface The iRMX 80 executive provides a simple, straightforward program interface for user programs. This interface is consistent throughout the range of facilities offered, reducing the number of con· cepts which must be learned. Interactively Configurable The Interactive Configuration Utility (ICU80) pro· gram provides the user with an easy·to·use method of configuration of iRMX 80-based applications. Responding to questions from the ICU80 program running on the Intellec Microcomputer Development System, the user tailors theapplication system by selecting modules, e.g., nucleus flexibility as shown in Figure 2, from the wide variety of iRMX 80 facilities. The resultant system contains only the modules necessary for its use, allowing the iRMX 80 executive to fit a wide range of applications from small special purpose dedicated applications to large general purpose sys· tems. Library Modules The iRMX 80 executive is constructed in a thoroughly modular manner with the full range of facilities being offered in multiple library modules, see Table 1, allowing easy selection of the exact facilities required. Small Nucleus The iRMX 80 nucleus provides a small, efficient foundation upon which application systems may be easily built. A wide range of multi-tasking, real· Figure 2_ Configuration Flexibility Provides Application Freedom. The iRMX 80 executive allows you the freedom to choose from a wide range of iSBCfamily processors and peripherals upon which your application may be built. It allows you to break the software "chain" which ties your application to a single processor type and thereby gain application freedom. 4-2 AFN-01553A iRMX 80 Board Technological Support iRMX 80 DFS allows for either Intellec Development Systems, ISIS-II compatible media format, or a user specified format. iRMX 80 DFS offers the following services in an ISIS-II compatible media format: The iRMX 80 executive provides support for a range of processor technologies from the 8080based iSBC 80/10 Single Board Computer to the 8085-based iSBC 80/30 Single Board Computer. Applications are offered an easy upgrade path with the iRMX 80 executive which allows greater pricelperformance to be achieved without expensive software modification. • • • • • • • Extensive Debugging Aids The iRMX 80 executive provides two user oriented, interactive software debugging aids. The debuggers allow memory examination and modification, execution breakpoints, and automatic stack overflow monitoring. These powerful aids allow simplified task debugging and faster application system development. OPEN a file for processing READ data from a file WRITE data to a file SEEK to a specific location within a file CLOSE a file to further processing RENAME a file DELETE a file. For those applications which require unique media formats the iRMX 80 executive offers a level of processing which allows complete user flexibility in formatting data. The services offered are: The various facilities offered by the iRMX 80 executive are provided as independent library modules, thus allowing simple inclusion or exclusion, depending on the user's specific requirements. These facilities are described below. • • • • • • • Nucleus Terminal Handler The iRMX 80 executive provides nuclei for operation on various iSBC single board computers. The nuclei provide real-time scheduling, interrupt handling, intertask communications, and task control. The services offered are: The iRMX 80 terminal handler provides a data path between a console device (CRT or TTY) and user tasks. Communications between task and device are affected by using the nucleus services SEND and WAIT. Two versions of the terminal handler are offered: FACILITIES • Send a message from one task to another • Accept a message from another task • Wait for a message to be transmitted from another task • Transmit a special interrupt message to a task • Suspend execution of a task temporarily • Continue execution of a previously suspended task. SEEK to a specific track READ a sector WRITE a sector FORMAT a track RECALIBRATE to Track 0 VERIFY a sector DELETE a sector. 1) Full Terminal Handler - The full terminal handier has a built-in interface to the debugger. It also provides for: • Correction of data previously input • Automatic buffering of data prior to a read request • Priority output path which allows "emergency" messages to bypass any other messages which may be queued for output • Automatic baud rate search to determine communications terminal speed. Disk File System The iRMX 80 Disk File System (DFS) provides for the filing and retrieving of data using disks. The Table 1. iRMX 80 Memory Requirement Memory Requirements" (Bytes) Module Nucleus Full Terminal Handler Minimal Terminal Handler Free Disk Space File Manager System Minimum Development System Requirements Disk 1/0 Analog 1/0 Bootstrap Loader & Initializer Operating Syslem Memory Size (Bytes) Minimum Diskette Drives ISIS-II 64K RAM 2 PROM' 2K 3K 600 1K 5.5K 700 800 600 RAM 250 950 120 250 1.6K 100 50 900 "Indicates amount of code which can be configured •• All figures are approximate. AFN·01553A In PROM . 4-3 iRMX 80 2) Minimal Terminal Handler - The minimalter' minal handler provides a limited feature version of the full terminal handler for memory space critical applications. The minimal terminal handler provides for correction of data previously input. set of questions on the terminal of the Intellec Development System and elicits the configuration information about the application system, e.g. CPU TYPE: 80130, or TERM HNDLER: FULL. After describing the application system configuration the ICU80 program will initiate the housekeeping chores (linking and locating), thereby supplying the target iRMX 80 application. The result is the rapid development of the target iRMX 80 application system. Free Space Manager The iRMX 80 free space manager provides the capability of dynamically allocating RAM memory based upon user requests. Requests may be made for any size memory blocks and will be accommodated based on memory availability. The free space manager services are: The iRMX 80 generation process allows application programs written in PUM-80, FORTRAN-80, BASIC-80, or 8080/8085 Assembly Language to be merged with the specific iRMX 80 modules desired,see Figure 3. The system may then be debugged using Intel's sophisticated In-Circuit Emulation (ICE™) products oriRMX 80 debugger. The final application system is then available for either PROM or disk-based systems. • Request memory • Release memory. Analog Handlers The iRMX 80 analog handlers provide a convenient mechanism for obtaining and transmitting analog values between user tasks and Intel's iSBC 711, 724 and 732 Analog Boards. The analog handlers offer a full range of services including: . • • • • • Repetitive channel input Sequential channellsingle gain input Sequential channellvariable gain input Random channellvariablegain input Random channel output. The input and output modules are individually configurable allowing greater application flexibility. Bootstrap Loader The iRMX 80 bootstrap loader allows those applications using disk to create essentially, a "soft" system that may be loaded into RAM from disk rather than being permanently PROM reside.nt. This provides greater application flexibility in building and supporting disk-based systems. iRMX 80 LIBRARY Interactive Configuration The Interactive Configuration Utility (ICU80) program provides relief from the. burden of manually creating hardware configuration tables and combining selected software components. Using the environment information, the iRMX 80 nucleus effectively controls and orchestrates the appl ication system. l:I Wo DEBUG The iRMX 80 package provides two avenues for configuring applications; an effective macro mechanism allbws specific detail manipulation of structures for the experienced iRMX 80 user or, secondly, an easy-to-use interactive ICU80utility program generates the structures automatically. This latter program displays a clear and concise {j APPLICATION SYSTEM D EXECUTE V=>C Figure 3. The System Generation Process 4-4 AFN·01553A iRMX 80 Minimal Terminal Handler Free Space Manager Disk File System Analog Handlers Debuggers Bootstrap Loader Configuration Macros Interactive Configuration Utility Program (ICU80) Problem Reports Registration Card Reference Manuals SPECIFICATIONS Supported Hardware SINGLE BOARD COMPUTERS iSBC 80/10A iSBC 80/10B iSBC 80/20 iSBC 80/20-4 iSBC 80/24 iSBC 80/30 MASS STORAGE CONTROLLERS iSBC 201 iSBC 202 iSBC 204 iSBC 206 Reference Manuals 9800522 - iRMX 80 User's Guide (SUPPLIED) 9803087 - iRMX 80 Installation Instructions (SUPPLIED) 142603 - iRMX 80 Interactive Configuration Utility User's Guide (SUPPLIED) ANALOG BOARDS iSBC 711A iSBC 711 iSBC 724A iSBC 724 iSBC 732A iSBC 732 Reference Manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. iRMX 80 Executive Shipping Package Single and double density diskettes containing: iSBC 80/10,80/20, and 80/30 Nuclei Terminal Handler ORDERING INFORMATION Part Number Description RMX 80 Real-Time Multi-Tasking Executive AFN·01553A 4-5 iSBC S01 FORTRAN·SO RUN·TIME PACKAGE FOR RMXlSO SYSTEMS • Includes FORTRAN-80 terminal I/O via RMXl80 mini or full Terminal Handler • The ideal iSBC 80 Single Board Computer run·time environment for programs written in Intel's ANSI FORTRAN 77 standard compiler • Software floating point libraries are compatible with Intel floating point standard • Fully compatible with Intel's RMXl80 Real·Time Multitasking Executive software • iSBC 310 High Speed Math Unit driver~ allow acceleration of floating point operations • Includes FORTRAN·80 disk I/O via RMXl80 Disk File System The iSBC 801 FORTRAN-80 Run-Time Package is a complete, ready-to-use set of linkable object modules which are fully compatible with RMX/80systems_ The modules, when combined with the FORTRAN-80 coded application, provide the appropriate interfaces to the disk file system and terminal handler of RMX/80_ The FORTRAN-80 application, in addition to usage of the disk file or terminal 1/0, can take advantage of the software floating point routines_ In those cases where accelerated operations are necessary, the FORTRAN-80 Run-Time Package provides the necessary interface to use the iSBC 310 High Speed Math Unit. 4-6 iSBC801 Direct communication with the mini or full Terminal Handler and Disk File System by using the formatted 1/0 facility in FORTRAN·80 coded application tasks. The user is able to specify the external format of data (inte· ger, floating point, and character) as either input or out· put on those devices. The universality of formatted data statements In FORTRAN·80 facilitates storing relevant data for later retrieval, as well as summary display of the information. For example, to read two variables: FUNCTIONAL DESCRIPTION The FORTRAN·80 Run·Time Package is a complete, ready·to·use set of linkable object module libraries on both a single and a double density diskette. it can be combined with the RMX/80 modules and user·supplied application software modules on the Intellec Develop· ment System. The FORTRAN·80 Run·Time Package for RMX/80 systems is the ideal environment for executing the FORTRAN·80 code in an iSSC 80 system. It provides full data formatting and storage capability through the RMX/80 Disk File System. The package allows utiliza· tion of the RMX/80 Terminal Handler for entry and dis· play of information on a TIV or CRT. In addition, the FORTRAN·80 Run·Time Package facilitates effective use of the iSSC 310 High Speed Math board to optimize floating pOint calculations. READ (5,88) X, V 88 FORMAT (F10.3, F6.2) The run·time software support modules are built for selective utilization at link time with FORTRAN·80 coded tasks. Selective linking can be profitably used to Insure that only those modules which exactly match FORTRAN·80 application requirements are included in the run time systems. This insures that the minimum memory is required in the final system. Features and Benefits of the FORTRAN·80 Run·Time Package Software modules provided with the package are con· veniently linkable with the RMX/80 library modules. This allows-use of the right software tool (whether 8080/8085 Assembler, PUM·80, or FORTRAN·80) for the right job. The user is also able to combine all the software elements into a highly effective RMX/80 based applica· The modules included on the diskettes are readily usable by linking with the user·coded FORTRAN·80 reo locatable object modules for operation in the RMX/80 environment. Advantages forthe iSSC user include: LINK AND LOCATE The RMX/BO executive based environment is specified by configuration parameters supplied at the time of system linking. These parameters define ex- . pected system characteristics and the relationship of FORTRAN·BO coded tasks to other RMX/BO modules. The linker output is the object code which may be placed in PROM or loaded into RAM via the bootstrap loader. Configuration parameters are discussed in detail in the RMX/80 User's Guide, Chapter 3. Figure 1. Configuration Flow Diagram 4·7 ~-.- Q iSBC 801 Description and Capabilities Summary tion. FORTRAN routines can be interfaced to PUM or assembler coded routines so portable software can be run on all RMX/SO based systems. To run FORTRAN·SO programs under RMX/SO, libraries are selected from two packages: the RMX/SO Real-Time Multitasking Executive and the FORTRAN-SO Run-Time Package for RMX/SO systems. The FORTRAN-SO RunTime· Package provides libraries to support FORTRAN-SO coded programs running under RMX/SO: Application writing with the floating point algorithms of FORTRAN-SO is enhanced thru the accuracy insured by FORTRAN-SO adherence to the Intel Floating POint Standard. Accuracy is insured thru software; it can beduplicated and accelerated thru the interface modules for the iSBC 310 High Speed Math Board. The iSBC customer now can effectively perform high speed, accurate computations with pre-coded and debugged mathematical functions. FSORMX.LlB FORTRAN-SO input/output formatting and interface routines for the RMX/SO environment. FPSFTX.LlB Software floating point arithmetic routines for the RMXlSOenvironment. FPHRDX.LlB Software interface routines for the iSBC 310 facilitate floating point calculations in the RMXlSO environment of an iSBC SO/20 or iSBC SO/30 hardware based sy"tem. FPHX10.LlB is another libm,y provided specifically for the iSBC SO/1 0 based RMX/SO system. Generation Considerations The FORTRAN-SO Run-Time Package consists of several relocatable library modules. The modules are. configurable with the RMX/SO supplied library modules and user coded FORTRAN-SO, PUM-SO or SOSO/SOS5 system. Through the proper linkage and location of the appropriate modules, a complete software solution for the target iSBC SO system can be generated. This software then can be quickly loaded into the target iSBC SO system through ICE-SO or S5 during debug. The final application code is placed in EPROM or loaded directly from disk via the RMX/SO boostrap loader. . SPECI FICATIO NS Reference Manuals Generation Environment The following material is shipped with the product: #9S004S0 ISIS-II FORTRAN-SO Compiler Operator's Manual Intellee Microcomputer Development System with ISIS-II Diskette Operating System. Minimum of 64K bytes RAM memory. Dual Floppy Diskettes. RMX/SO Real-Time Multi-Tasking Executive library diskettes. FORTRAN-SO (V2.0 or later) Compiler diskettes. Additional information for FORTRAN-SO and RMX/SO can be found in the #9S004S1 FORTRAN·SO Programming Manual #9S00522 RMX/SO User's Guide #9S00547 SOSO/SOS5 FORTRAN-SO Reference Card Compatible Run-Time Hardware Additional manuals may be ordered from any Intel sales representative, distributor office or from I ntel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Single Board Computers: iSBCSO/10A iSBC S0/20-4 iSBCSO/30 Disk Controllers: iSBC 202 iSBC 204 iSBC 206 Other: iSBC 310 Math Unit ORDERING INFORMATION Part Number Description SBC SOl FORTRAN-SO Run-Time Package for RMX/SO Systems FORTRAN-SO Run·Time Package is copyrighted and licensed by Intel Corporation. It can be purchased only under a required license agreement with Intel. Software may be developed with the FORTRAN-SO Run-Time Package to run on Intel RMX/SO based systems. Physical Characteristics Product distributed on both a single and a double density diskette. 4-8 iSBC 802 BASIC·80 CONFIGURABLE RMX/80 DISK BASED INTERPRETER • Resident BASIC interpreter for iSBC 80 Single Board Computers • Totally compatible with Intel's RMXl80 Real·Time Multitasking Executive software • Sequential or random access diskette storage for programs and data • Exceeds the ANS X3.60·1978 and the ECMA·55 minimal BASIC standard • Single and double precision software floatin'g point arithmetic • Interpreter supplied in two forms: - A i'elocatable module for tailoring systems to exact requirements • Direct port 110 instructions for special input and output requirem~nts - • Interface upto 25 user defined software functions written in 8080/8085 assembler, PLlM·80, or FORTRAN·80 A predefined version which incorporates the RMXl80 Nucleus, Terminal Handler, and Disk File System for. an iSBC 80/30 and iSBC 204 based system The iSBC S02 BASIC·SO Configurable RMX/SO Disk Based Interpreter has acomplete ready·to·use set of linkable object modules which are fully compatible with Intel's RMX/SO Real·Time Multitasking Executive Software, The modules combine with RMX/SO to provide a BASIC·SO interactive interpreter system, BASIC·SO programs may be created, stored, and interpreted on the iSBC SO based system. These programs may use the disk file and terminal 110, software floating point, or interface to other routines provided by the user to tailor the BASIC·SO system. 4·9 iSBC 802 as the relocatable BASIC-80 modules, 2) a set of bootstrap PROMs that will load the executable RMXSYS module from the diskette into the iSBC main memory, and 3) a cable that connects the iSBC 204 Floppy Diskette Controller to the bulkhead connector on any Intellec diskette.drive chassis. The predefined system offers an "instant-on" software capability for the user's supplied hardware system consisting of the following items: FUNCTIONAL DESCRIPTION The RMX BASIC-80 Interpreter provides a high level language interpreter with extended disk capabilities which operates under the RMX/80 Real-Time Multitasking Executive and translates BASIC-80 source programs into an internally executable form. This universally accepted language is designed for the OEM who requires a pass through programming language suitable for usage by both beginners and experienced programmers. BASIC80 offers users an expedient method of utilizing the powerful computational and input/output capabilities of an iSBC 80 microcomputer system and applying them to solving a wide range of application problems;The BASIC80 language has a rich complement of statements, functions, and commands to program applications requiring a full range of 1) string manipulation and disk I/O for data processing, 2) single and double precision floating point and array handling for numeric analysis, or 3) port I/O with mask operations controlled through bitwise Boolean logical operators. In addition, Intel's BASIC-80 meets and exceeds the requirements of ANS X3.60-1978 Minimal BASIC Standard and, similarly, the Standard ECMA-55 Minimal BASIC. Dual Solution The iSBC802 provides BASIC-80 to the OEM in two forms. First, the product is supplied as a set of linkable object modules on both a single and a double density diskette which can readily be combined with RMX/80 library and user application modules. The Intellec Development System is used to form a complete software solution for the iSBC 80 based system from this configurable version. Second, for users who want an "instanton" BASIC system and have no need to add additional software routines for their end product, a predefined BASIC-80 software system has been included in the iSBC 802. The predefined system inCludes 1) the RMX/80 and BASIC-80 software modules configured into an executable object module (RMXSYS) which is supplied on the same single and double density diskettes iSBC 80/30 Single Board Computer iSBC 204 Universal Flexible Diskette Controller 32K bytes additional RAM memory (either iSBC 032 or two iSBC 016s) Compatible teletypewriter terminal Compatible diskette drives RMXl80 BASIC·80 FEATURES AND BENEFITS Meets New Industry Standard BASIC-80 provides the OEM and end-user with a resident programming language for the iSBC 80/10A, iSBC 80/20, iSBC 80/20-4, or iSBC 80/30 based systems. A desirable and cost effective language feature is its PROM or disk resident capability. BASIC-80 also complies with an industry standard that defines the Minimal BASIC language specification and provides a level of confidence and structure not previously available to the OEM with BASIC interpreters. Since Intel's BASIC-80 meets this standard, the user can be assured of a maximum amount of compatibility with other BASIC interpreters. Major Features of ANS X3.60·1978 Include: Constants and Variables-The user can describe and manipulate constants and variables in a form most suited to the application. The numeric expression can be constructed from variables, numeric constants, and function references. The string expression is composed of a string variable or a string constant. Numeric Functions-Commonly used single precision scientific numeric functions are provided for cosine, sine, The RMX/80 based environment is specified by configuration parameters supplied at the time of system linking. These parameters define expected system characteristics and the relationship of the BASIC-BO tasks to other RMXfBO modules. The linker output is the obiect code which may be placed in EPROM or loaded into RAM via the bootstrap loader. Configuration parameters are discussed in detail in the RMX/80 User's Guide, Chapter3. Figure 1. Configuration Flow Diagram 4·10 iSBC 802 tangent, arctangent, square root, exponentiation, abso· lute value, integer, sign of a number, log, and random number generation. In addition, RANDOMIZE can be used to override the predefined pseudo·random number values. All underflow and overflow conditions are recog· nized and reported in a consistent and defined manner. Program Control and Sequencing-Specific program control and the sequencing of statement execution is provided. GENERATION CONSIDERATIONS Generation of Configurable Version The configurable portion of the iSBC 802 BASIC·80 pack· age consists of several relocatable library modules. These modules are configurable with the appropriate RMX/80 library routines (Minimal Terminal Handler, Nu· cleus, Disk File System and Loader) and the other appli· cation tasks to form a full system. Through the proper linkage and location of the appropriate modules, a com· plete software solution for the iSBC 80 system can be generated. This software then can be quickly loaded into the iSBC 80 system through ICE 80 or 85 during debug. The final application code is placed in EPROM or loaded directly from disk via the RMXlBO bootstrap loader. Assigned Variable Values-Variables can be assigned values by the use of DATA statements which can be READ and manipulated through the RESTORE statement. Custom Functions-The user can defin'e custom func· tions for use during program execution. Indexed Arrays-Arrays can be indexed starting with 0 or 1 and the array's size is established through a dimension (DIM) statement. Interactive'I/O-Program directed prompts can be sent to the terminal through the INPUT statement in addition to accepting input data values. Effective tabular output is accomplished through the PRINT statement which will cause the transmission of a character string to an ex· ternal device. DESCRIPTION AND CAPABILITIES SUMMARY Configurable Version To create a tailored BASIC·80 System for an iSBC BO based product, libraries are selected from two packages: the RMXlBO Real·Time Multitasking Executive and the BASIC·BO Conflgurable RMXlBO Disk Based Interpreter package. The BASIC·BO Configurable RMX/80 Disk Based Interpreter package provides the following files for use with RMXl80 (Version 1.3 and above). EXTENSION BEYOND INDUSTRY STANDARD Intel's BASIC·80 has enhancements and extensions beyond the standard. These include the following: PROM Storage-BASIC·80 interpreter and program source can be stored In PROM and then executed at sys· tem startup. This allows users to take advantage of spe· cial routines they have written in other languages, PUM· 80, FORTRAN·80, or 8080/8085 Assembler. Floating Point Standardization-The OEM can code float· ing pOint algorithms in BASIC·80 because the accuracy is insured by the BASIC·80 interpreter's adherence to the Intel Floating Point Standard. Single precision is accu· rate to a maximum value 3.40282E+38 and double preci· sion is accurate to a maximum value of 1.79769313486231 D + 308 for the utmost in creditability for scientific and mathematical computation. File Management Statements-Abundant file managing statements aid in the orderly usage of programs and data stored on disk files. Direct Port I/O-Communicate directly to the 1/0 ports of the iSBC product line through the byte oriented INP and OUT instructions. Use the WAIT statement to mask in· puts from a port until the indicated bit pattern appears. Specific memory locations can be examined with the PEEK statement or modified via the POKE statement. BASIC.L1B Necessary modules for linkage with RMX/80 BOOPS.ASM "Include" source file for BASIC·BO options related to the creation of a tailored system BASCM.ASM The macro assembler source for the Configuration Module used for RMXIBO BOMEM.ASM Module to describe the memory allo· cation for the BASIC·80 task BOOTCM.ASM Assembler source for the Configura· tion Module used by the bootstrap loader BOBMEM.ASM Module to describe the memory allo· cation for the system to the boot· strap loader Predefined Version The following modules are related to the predefined BASIC·80 System which can be loaded via the supplied bootstrap loader. Formatted Output-Valuable output formatting of data can be accomplished through the PRINT USING format· ting characters, i.e. asterisk (0) fill, floating dollar sign ($), leading or trailing sign (+, -), comma (,), insertion and scientific notation (exponent display). Enhanced Interactive Programming-Interactive pro· gramming is enhanced through easy to use source line modification commands. Program modules stored on disk can be readily MERGED with statements in memory. 4·11 RMXSYS Predefined BASIC·80 System soft· ware configured, linked, and located to support the required configuration BOBOOT Exact copy of the bootstrap loader as supplied on the ROMs for the prede· fined system iSBC 802 SPECIFICATIONS Physical Characteristics Configurable Version Generation Requirements Product distributed on both a single and double density diskette. Each diskette contains both the modules for configuring a tailored system and the predefined soft· ware system. Intellec® Microcomputer Development System with ISIS· II Diskette Operating System Minimum of 48K bytes RAM memory Two ROMs which contain the bootstrap loader. Dual Floppy Diskettes One cable for the predefined system which provides a connection from the iSBC 204 to the user's Intellec Diskette Drive Chassis (MDS DDS, MDS DDR, and MDS 2DS, MDS 710, MDS 720, MDS 730). RMX/80 Real·Time Multitasking Executive library disk· ettes (Version 1.3 and above) Compatible Run-Time Hardware Reference Manuals Single Board Computers iSBC80/10A iSBC BO/20·4 iSBCBO/30 The following material is shipped with the product: 980075B 9B00774 Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be or· dered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Disk Controllers iSBC 202 iSBC 204 iSBC 206 Predefined Versiol1Generation Requirements No system generation is required as the software system has been predefined to execute in the run·time environ· ment specified below: iSBCBO/30 iSBC 204 disk controller Additional 32K bytes memory (either iSBC 032 or two iSBC 016 memory boards) Compatible Intellec diskette drives and cable (cable supplied with iSBC 802) RS232C compatible terminal ORDERING INFORMATION Part Number SBC802 BASIC·BO Reference Manual (SUPPLIED) BASIC·80 Pocket Reference (SUPPLIED) Description BASIC·BO Configurable RMX/BO Disk Based Interpreter BASIC·80 Configurable RMX/BO Disk Based Interpreter is copyrighted and licensed by Intel Corporation. It is avail· able only under a license agreement with Intel. Software may be developed with the BASIC·BO to run on Intel RMX/80 based systems. 4·12 iRMX86 OPERATING SYSTEM • Structured application environment •• Real~time priority-oriented scheduling • User configurable • Powerful error management • User extensible • Interactive system debugger • PROM or RAM based • Comprehensive 1/.0 system • Object-oriented nu.cleus • Extensive human interface The Intel® iRMX 86 Real-Time Operating System is an easy-to-use, sophisticated software system Which operates on Intel iSBC 86/12 b.oards and user iAPX 86 (8086)-based boards. TheiRMX 86 Operating.System extends the iAPX 86 (8086) arch(tecturEl, providing a structured, .efficient environment for many applications, including process contro·i, intelligent.terminals, office systems, medical electronics, and data com. munications. iRMX 86 ™ Operating SystelTiLayers 4-13 iRMX 86 facilities being offered in library modules, allowing easy selection of the exact features required. Overhead for unused facilities is then eliminated. FUNCTIONAL DESCRIPTION Services provided by the iRMX 86 Operating System include facilities for executing programs concurrently, sharing resources and information, servicing asynchronous events, and interactively controlling system resources and utilities. In addition, the iRMX 86 Operating System provides all major real-time facilities including priority-based system resource allocation; the means to concurrently monitor and control multiple external events; real-time clock control; interrupt management and task dispatching. The iRMX 86 Operating System contains the following modules: a Nucleus, a device independent Input/Output Subsystem, a Human Interface Subsystem with command language interpreter and ASCII console interface, a Terminal Handler, and an interactive object'oriented Debugging Subsystem. Because the modules and services provided by the operating system are user selectable, application-specific operating systems can be created by iRMX 86 users. The iRMX 86 Operating System thus eliminates the need for custom operating system design and hence reduces development time, cost and risk. USER EXTENSIBLE The iRMX 86 Operating System provides a framework in which to extend the system and have these extensions look like facilities provided by Intel. These extensions include not only the abil~ ity to add custom system calls, but also the ability to add operating system data structures. Check' out of these extensions is easily accomplished by using the Debugging Subsystem since extensions become an integral part of the operating system. Because the operating system is designed for user extensibility, the extensions can be 'added in a symmetric manner, resulting in a homogeneous customized operating system. EPROM OR RAM BASED The iRMX 86 system can be EPROM resident or loaded from a mass storage device into RAM, depending upon application requirements. Being able to place all of the software in EPROM offers two benefits. First, if the application is in a harsh environment, mass storage devices cannot be used because of the danger of contamination. Second, if the application is small, the expense and overhead of mass storage devices is eliminated. Feature Overview The iRMX 86 Operating System provides users of the iAPX 86 (8086) simple, easy-to-use to'olsfor creating a wide range of application systems. The most important features of the iRMX 86 Operating System are: Nucleus" OBJECT-ORIENTED NUCLEUS The iRMX 86 Nucleus provides a foundation upon which a variety of application systems can be built. Object-oriented architecture provides a symmetric interface for' application programs and operating system ,extensions. Objects provide . facilities including multiprogramming" mUltitasking; critical section management, extensive taskto-task communication and control. STRUCTURED APPLICATION ENVIRONMENT The iRMX 86 Operating System provides a consi!;ltent structure from application to application, thus allow,ingexperience gained on one system to be easily transferred to others. Often, entire programs may be ported from one application to ano.ther. USER CONFIGURABLE REAL-TIME PRIORITY-ORIENTED SCHEDULER iRMX 86·basedapplications can use a wide range of facilities, selecting only those which meet the specific requirements of the application system. , The resultant system contains only the modules necessary for its use, allowing the IRMX 86 Operating System to be cost-effectively applied in a wide range of application environments from performance-oriented industrial applications, to security-conscious data-processing systems. The iRMX 86 Operating System is constructed In a thoroughly modular manner with the full range of The iRMX 86 Scheduler ensures that the highest priority task ready to execute is given system control because the scheduler recognizes 255 software priority levels. Also, the system supports eight hardware priority levels, allowing the application system to be responsive to its external environment. 4-14 ERROR MANAGEMENT SUBSYSTEM The iRMX 86 Operating System provides extensive error management and reporting mechaAFN·01528A iRMX 86 nisms. Both excessive system loading and user programmer errors can be reported, reducing system debug time. The flexibility of the Error Management Subsystem allows errors to be ser· viced directly by the user task 'or sent to a specific error handler. -Critical section management -User extensible • Real·time prioritY'oriented scheduling • Interrupt management • Extensive error management OVERVIEW Debugging System The Nucleus is the heart of the iRMX 86 Operating System. All other subsystems require the Nucleus. The iRMX 86 Operating System provides inter· active software debugging. The Debugging Sub· system has two capabilities that greatly siniplify the process of debugging a multitasking system. First, the Debugger allows you to debug several tasks while the balance of the application system continues to run in real·time. Second, the Debug· ger lets the programmer interactively view and modify system constructs as well as RAM and • iAPX 86 (8086) registers. Embedded in the Nucleus are two main facilities: first, the facility for concurrent program execu· tion; second, the faCility for handling simultane· ous asynchronous events. iRMX 86 systems solve problems that require real-time response. For ex· ample, interrupts coming from specialized periph· eral devices can be serviced in an efficient man· nero iRMX 86.systems allow the hardware to be used by more than one application, thus reducing the overall system size and hardware cost. 1/0 System The iRMX 86 device·independent I/O Subsystem provides a standard interface for application pro· grams to communicate with all I/O devices. File management systems provide powerful features like a hierarchical directory structure for quick, ef· ficient file access. A standardized device driver in· terface allows users to easily create custom device drivers. A wide range of standard drivers are available including; iSBC 204 Single Density Diskette Controller, iSBC 206 Hard Disk Control· ler, and terminal handler (via on·board 8251 USART device). The object'oriented architecture provides the power necessary to solve the complex problems of today and tomorrow. The system is comprised . of uniform system calls ensuring that the Nucleus is both easy to learn and easy to extend. Only four concepts must be mastered to learn the system: object management, interrupt management, the scheduling algorithm, and error management. Human Interface The iRMX 86 Human Interface provides a powerful man·machine interface for interactive control of system resources and utilities. iRMX 86 system utilities include display file directories, copy files, rename files, etc. The Intel supplied command line interpreter is table driven, allowing easy modification by the user for the creation of application'oriented commands. SYSTEM LAYERS AND FACILITIES Nucleus Application Code Interface Nucleus FEATURES OBJECT·ORIENTED ARCHITECTURE • Object'oriented architecture -Dynamic memory manager -Multitasking -Multiprogramming -Interprogram and intertask communication and control AFN·QI528A The Nucleus is composed primarily of "objects." Objects are data structures with a fixed set of at· tributes. Just as a floating point number is a data structure with operators to manipulate it, like add or multiply, iRMX 86 objects have system calls to manipulate them. Because of the uniform struc· 4·15 iRMX86 ture of the system, users have aJoundation on which to tailor the Nucleus to the application by adding application-specific objects .and system calls. ' ager automatically allocates and deallocate$ avaiJable RAM memory when objects are created and deleted. iRMX 86 objects include: Object Description - SEGMENTS, for dynamic buffering - MAILBOXES, for intertask and interprogram object and data transfer. - SEMAPHORES, for intertask and interprogram synchronization and mutual exclusion - REGIONS, for critical section management - TASKS, for code execution . -JOBS, for program isolation • USER OBJECTS, for system extensions SEGMENT - Dynamically created RAM buffer with a specified length used to store data. Provides intertask and interprogram object and data transfer. Mailboxes are locations for objects to be sent af)d retrieved. For example, intertask communication permits a time·critical task.to.forward data to a.non-time·critical task for processillg. Mailboxes a~e generally .used to pass data from task to task, although any object (useror system·provided) may be passed. MAILBOX - AlliRMX 86 objects are dynamic; they can be created and deleted. Thefree space memory man: Manages mutual exclusion and synchronization. A semaphore, an integer be- SEMAPHORE - Nucleus Object Management System Calls System Calls for All Objects O.S. Objects Object·Specific System Calls Attributes JOBS Tasks Memory pool. Object directory Exception handler TASKS Priority Stack Code State Exception handler SEGMENTS Buffer with length MAILBOXES List of objects CREATE$JOB DELETE$JOB SET$POOL$MIN GET$POOL$ATTRIB OFFSPRING CREATE$TASK DELETE$TASK SUSPEN D$TASKRESUMEHASK GET$EXCEPTION$HANDLER· SET$EXCEPTION$HANDLER SLEEP GET$TASK$TOKENS GET$PRIORITY SET$PRIORITV CREATE$SEGMENT DELETE$SEGMENT GET$SIZE CREA TE$MAI LBOX DELETE$MAILBOX SEND$MESSAGE RECEIVE$MESSAGE CREATE$SEMAPHORE DELETE$SEMAPHORE RECEIVE$UNITS SEND$UNITS CATALOG$OBJECT UNCATALOG$OBJECT LOOKUP$OBJECT ENABLE$DELETION - DISABLE$DELETION .' List of tasks waiting for objects FORCE$DELETE SEMAPHORES GET$TYPE . Semaphore unit value List of tasks waiting for units REGIONS USER OBJECTS ,"1' list of tasks waiting for critical section CREATE$REGION DELETE$REGION RECEIVE$CONTROL '. ACCEPT$CONTROL SEND$CONTROL License rights to a given extension type -New object template -I -; 4·16 CREATE$EXTENSION DELETE$EXTENSION CREA TE$COM POSITE DELETE$COMPOSITE INSPECT$COMPOSITE ALTER$COM POSITE AFN-0152BA iRMX 86 tween. 0 and 64K, is used to signal another task when processing has been· completed or when resources are available. A semaphore provides a low overhead signalling mechanism. Priority Levels Handling an interrupt with respect to other work in the system can be completely' user controlled. iRMX 86 external interrupt levels are directly related to task priorities. The priority of the executing task determines which interrupts are masked. Generally, software background tasks will be assigned a lower priority than interrupt tasks to avoid blocking interrupts. Controls access to critical sections. Regions allow only one task at any given time to access a portion of code. Examples are a ncinreentrant procedure or code for controlling a peripheral device that can 'only service one request at a time. In addition, regions can also be used to protect data structures from being manipulated by more than one procedure at a time. REGION - NUCLEUS SCHEDULING Features TASK - Software modules that execute sequentially. Each task in the system has the characteristics of a processor. It has its own code, priority level, stack area, data area, and status. Software priority levels determine the task's eligibility to execute; there are 255 levels. Task execution is based on an event·driven priority-oriented scheduling algorithm. • Real-time priority-oriented • Timed wait for system resources • Dynamic control of task execution Overview The iRMX 86 scheduler executes tasks on the basis of three criteria: relative importance of the task, elapsed tiine,and task state. Permits isolation of application tasks, objects, and memory, providing a multiprogramming environment. Jobs encapsulate an application and limit the degree of interaction between one set of tasks and another. JOB - ReaHime Priority Scheduling The iRMX 86 Nucleus offers apriority-oriented event·driven scheduling mechanism'. The scheduler uses the task priority to determine which task receives CPU time. The scheduler ensures that the highe.st priority task ready to execute is given system control. That task will continue to run until a higher priority interrupt occurs, or until the running task requests resources that are not available. Priority scheduling allows the system to be responsive to the external environment while still devoting resources only totasks that have work to be performed. System programmer's facility for creating objects not found in the iRMX 86 system. These new objects appear to other facilities in the iRMX 86 system as if part of the original operating system. This means that the system calls that manipulate system objects also manipulate user defined objects. USER OBJECTS - NUCLEUS INTERRUPT MANAGEMENT Features Timed Wait • Two levels of interrupt management • User selectable priority for interrupt response A task can specify the time it will wait for an event to occur or wait for system resources to become available. A task can limit the time it will wait to receive an obje.ct at a mailbox, to receive units from .a semaphore, or to look·up an object in the directory. In addition, a task can specify how long it will remain dormant before executing any further instructions. This allows the user to more finely control the execution of the task and guard against possible system deadlock. Overview The iRMX 86 Operating System is responsive to external events occurring asynchronously in real time. Interrupt Management The iRMX 86 Operating System provides two levels of interrupt management; an' interrupt handler or an interrupt task. One provides speed, the other power. The interrupt task permits all iRMX 86 system calls to be issued and masks only lower priority interrupts. The interrupt handler permits only iRMX 86 interrupt system calls to be issued and masks all interrupts. AFN·01528A Dynamic Control of Task Execution Dynamic control over task execution can be completely user controlled. Often, it is important to temporarily halt the execution of a task. (This is known as suspending a task.) If a task has been suspended N times, then it must be resumed N 4-17 iRMX 86 times before it will be permitted to run. The !lystem is thus protected against a suspended task executing before it has been resumed the proper number of times. tasks running under the iRMX 86 Nucleus. It is intended for use in applications which require only limited 1/0 through a terminal and is generally used in applications that do not include an iRMX 86 1/0 Subsystem. An output-only version oUhe Terminal Handler is for use in applications that send output to a terminal but do not receive input. ERROR MANAGEMENT Features • Hierarchical error handling • Selective error processing Line Buffering and Character Echoing The Terminal Handler provides a line buffer which stores ASCII characters as they are input to the console. Special editing characters are not placed in the line buffer. Characters are echoed to the terminal when they are stored .in the line buffer. Overview When a task issues an iRMX 86 system call the results may not be what the task is trying to achieve. For example, the task may request memory that is not available, or it may use an invalid parameter. When these conditions occur, they are reported by the iRMX 86 error management system. Keystroke Control The Terminal Handler supports operator control over both input and output. A table of special characters is shown. Hierarchical Error Handling There is a hierarchy of error handlers within the iRMX 86 system. If errors are to be handled uniformly, then a system error handler is used. If a job has need of a different error handling facility, then the job's errors are handled at the job level. In addition, if a task has need for a unique error handier, then an error handler can be specified for that task. This flexible error handling means global error handlers can be created for the majorityof the errors, reducing the amount of application software to be written. Yet; jobs or tasks with specific needs can trap and handle errprs in a mariner unique to them. Terminal Handler Editing Characters Special Character Rubout Carriage Return Line Feed Escape control·C control·Q control·Q control·R control·S control·X control-Z Selective Error Processing Errors can be processed according to two failure modes: programmer errors and environmental conditions. "Insufficient memory" for example would be classified as an environmental condition. An invalid parameter in a system call would be classified as 'a programmer error. Whether a programmer error or an environmental condition, errors of a given category can be serviced in-line or cause the system to vector to the specified error handler. Effect Deletes previously entered character. Signals end of line. Signals end of line. Signals end of line. Aborts an application program. Ki lis or restarts output. Resumes suspended output. Displays current line with editing. Suspends output. Deletes the current line. Sends empty message. Debugging Subsystem Features • Object-oriented debugger • User-oriented interactive on-line debugging facility • Task execution breakpoint facility Terminal Handler Overview Features A powerful Debugging Subsystem which is both object-oriented and interactive is provided to ease the chore of debugging application systems. • Line buffering and character echoing • Keystroke control for line editing Overview Object-Oriented Debugger The. Terminal Handler supports real-time, asyn-. chronous 1/0 between the operator's terminal and The iRMX 86 Operating System provides a special debugger that recognizes iRMX 86 objects. Both 4-18 ....0-..... --... AFN·01528A _ .- _ iRMX 86 system objects and user objects can be viewed using the debugger. f\\.E. DRIVER INTERFACE' Interactive On-Line Facilities The Debugging Subsystem's own terminal handier includes all the features available in the stand-alone Terminal Handler. Interactive system checkout allows the user to view iRMX 86 system lists including the lists of the jobs, the ready tasks, the suspended tasks, the tasks queued at mailboxes, semaphores, regions, and the objects queued at mailboxes. BIOS-Application Code Interface Task Execution Breakpoint Facility Overview The Debugging Subsystem allows the application programmer to debug several tasks while the balance of the application system continues to run in real time using the task breakpoint facility. Task breakpoints can be set, viewed and changed. All 1/0 requests are performed on "files". Files can be created, deleted, opened, closed, read, and written. The system provides two file manager support options, named file support and physical file support. These file managers offer different 1/0 support and I/O-application interfaces. 1/0 requests to a device can be issued using the file managers supported by the actual driver. Basic 1/0 Subsystem FEATURES Named File Manager • Device-independent file driver interface • Device driver interface FEATURES • Hierarchical directory support for' mass storage devices • File access protection and control • Control over file fragmentation OVERVIEW The Basic InputlOutput Subsystem, BIOS, is an optional subsystem that provides input and output facilities for mass storage devices and communication with 1/0 devices in a device-independent manner. For example, the BIOS translates a READ request into device-specific instructions, freeing the application programmer from these details. Because the BIOS provides a standard interface for all 110 requests, programmers need not rewrite application code when adding or changing 1/0 devices. To incorporate application-specific peripheral devices in an iRMX 86 system only a small amount of code, a device driver, needs to be written. OVERVIEW - The named file manager provides support for mass storage devices_ Appl ication programs reference data through a directory rather than by physical track and block location, thus allowing data to be given a name and referenced by that name. HIERARCHICAL DIRECTORY SUPPORT - The BIOS supports a hierarchical directory structure, allowing data to be grouped logically and allowing quick directory lookup. An example is shown. The BIOS has two interfaces: one for performing device-independent application 1/0 requests (file driver interface) and one for adding device drivers (device driver interface). DEVICE-INDEPENDENT FILE DRIVER INTERFACE Features • Two file manager support options • Logical device naming for constant 1/0 application interface AFN·01528A Hierarchical Directory Example 4-19 iRMX 86 converters are typical kinds of devices that use the physical file manager. FILE ACCESS PROTECTION AND CONTROL Besides logical data grouping and naming, both access mode and password protection are supported to ensure file integrity. When a file is created the creator determines access rights: read, write, update, and append. The file is also password protected and only the creator of a file can grant another user access rights. These rights may be different from the creator's. For example, a creator who can "read" or "write" a file has the ability to grant "read-only" access to another user. Logical Device Naming Logical names are used when specifying a particular device rather than a physical address, causing physical device changes not to require a rewrite of application code. DEVICE DRIVER INTERFACE Features • Mass storage device drivers • Support for custom device drivers • Run-time device driver binding CONTROL OVER FILE FRAGMENTA TlON - Applicaton programs specify file granularity at the time a file is created. Because files are stored on random locations on the disk, wasted space is eliminated by using small file granularity. When file granularity is increased, access time for data retrieval is improved. The BIOS allows the user to decide whether time or space is more important. Overview The iRMX 86 system offers extensive device driver support, enabling users to easily add device drivers to the system. The same device driver code can be used for more than one physical device. Physical File Manager Mass Storage Device Drivers A direct interface to the device driver support facilities is provided via the physical file manager. No file directory structure is associated with the physical iile manager. Line printers, AID and DIA The iRMX 86 system includes two mass storage device drivers. The iSBC 204 Universal F.lexible Diskette Controller for standard flexible diskette BIOS-Application System Call Interface Universal File Calls ATTACH$FILE File Management Options Named • Hierarchical Directories • Access Mode Protection • Password Protection File Types Named Data DELETE$CONNECTION Named Directory GET$FILE$STATUS GET$CON NECTlON$ST ATUS Physical • Direct Device Driver Support Interface None 4-20 File Specific Calls CREATE$FILE DELETE$FILE OPEN CLOSE ·READ WRITE SEEK RENAME$FILE CHANGE$ACCESS GET$PATH$COMPONENT CREATE$DIRECTORY DELETE$FILE GET$DIRECTORY$ENTRY RENAME$FILE CHANGE$ACCESS GET$PATH$COM PON ENT CREATE$FILE OPEN CLOSE READ WRITE SEEK Access Mode Protection Delete Read Write Update Append Change Entry Delete Display Add Entry , None AFN·01528A iRMX 86 drives is supported. For larger mass storage reo quirements, the iSBC 206 Hard Disk Controller offers 10 MB on·line storage. lishes the binding and thereby the type of file sup· port used for a given device. Run-Time Device Driver Binding NAMED FILE DRIVER~ . PHYSICAL$ATTACH$DEVICE---... PHVSICAL/· . ~~~~~~. . FILE DRIVER 'Provldes code for READ, WRITE, SEEK, OPEN, CLOSE. iRMX 86 System Calls Device Driver Interface NUCLEUS OBJECT MANAGEMENT SYSTEM CALLS· Support for Custom Device Drivers Custom drivers can also be added to. the iRMX 86 system. There are three levels of device driver support: random access device driver support, common device driver support, and custom device driver support. Regardless of the driver support option and the file management option, only four routines need to be written for the driver. Also, an interrupt routine must be written for common and random access dri·vers. The semantics of these routines differ according to the device driver support option used. These are: CATALOG$OBJECT Catalogs the specified object in the given job's object directory. UNCATALOG$OBJECT Uncatalogs object from the directory. LOOKUP$OBJECT Returns access to the specified object. ENABLE$DELETION Enables an object to be deleted based on the disable-deletion depth. Highlevel support for random access devices. Assumptions for its use are: deblocking of requests is necessary, one interrupt level is sufficient, and random·seek must be supported. RANDOM ACCESS DRIVER SUPPORT - DISABLE$DELETION Disables an object from being deleted by incrementing the disable-deletion depth. FORCE$DELETE Decrements disable-deletion depth by one, then proceeds to delete the object . High-level support for common devices. Common driver support assumes no deblocking of requests is necessary, FIFO 1/0 requests are sufficient, and one interrupt level is sufficient. COMMON DRIVER SUPPORT - GET$TYPE Returns the specified object's type code: CREATE$JOB Creates the job with an initial task, memory pool, an empty object directory, and an exception handler. Complete flexibility to the device driver writer. No 1/0 request scheduling is provided, giving complete 1/0 request queuing responsibility to the device driver. No assumptions are made regarding interrupt levels or blocking or deblocking of requests. CUSTOM DRIVER SUPPORT - DELETE$JOB Deletes the specified job. SET$POOL$MIN Defines new minimum for the given job's memory pool. Run·Time Device Driver Binding The application program specifies the file management system and device driver; device drivers are attached to the system at run-time. The PHYSICAL$ATTACH$DEVICE system call estab· AFN·01528A GET$POOL$ATTRIB Returns information regarding the given job's memory pool. 4-21 iRMX86 OFFSPRING Returns the children jobs ofthe specified job. CREATE$SEMAPHORE Creates 'an integer semaphore with an initial value. CREATE$TASK Creates a task ilith a specified priority, stack, code location, and the job's exception handler. DELETE$SEMAPHORE Deletes the specified semaphore. DELETE$TASK Deletes the specified task. RECEIVE$UN ITS Receives the number of units requested from the semaphore. SUS PEN D$TASK Suspends the specified task or, if already sus· pended, increments suspension depth by one. SEND$UNITS Sends to the given semaphore the specified number of units. RESUME$TASK Decrements the suspension depth by one, and if zero resumes the task. CREATE$REGION Creates an access mechanism which controls code that is only to be accessed by one task at a time. G ET$EXCEPTION$HAN DLER Returns task's exception handler information. DELETE$REGION Deletes the specified region. SET$EXCEPTION$HANDLER Sets task's exception handler to the specified location and mode. The mode determines which classes of errors will be sent to the exception handler. RECEIVE$CONTROL Gains access to the mutually exclusive code even if it involves waiting. SLEEP Places the caller task in the asleep state for a specified numberof milliseconds. ACCEPT$CONTROL Gains access to the mutually exclusive code only ifit is immediately available. GET$TASK$TOKENS Returns requested system information. SEND$CONTROL Relinquishe,s the region when finished using it. GET$PRIORITY Returns the priority of the calling task. CREATE$EXTENSION Creates the license rights to a specified extension type. a SET$PRIORITY Dynamically alters the specified task's priority. DELETE$EXTENSION Deletes all objects of the extension type specified. CREATE$SEGMENT Creates a segment with a specified length. DELETE$SEGMENT Deletes the specified segment. CREATE$COMPOSITE Creates anew object template under the specified e'~tension object type. GET$SIZE Returns the segment size. DELETE$COMPOSITE Deletes the specified composite object. CREATE$MAI LBOX Creates a.mailbox for objects.to be sent and reo ceived. INSPECT$COM POSITE Inspects the specified composite.object's template. DELETE$MAI LBOX Deletes the specified mailbox. ALTER$COM POSITE Changes the composite object'stemplate. SEND$MESSAGE Sends the specified object's access to the given mailbox. INTERRUPT MANAGEMENT SYSTEM CALLS RECEIVE$MESSAGE Receives an object's acces§ fromthespecified mailbox. SET$INTERRUPT ASSigns an interrupt handler and,if desired, an i nterru pt task. 4-22 .1::=4. AFN,01528A == iRMX 86 RESET$INTERRUPT Voids the SET$INTERRUPT call. DELETE$FILE Deletes the file from the directory after all connections to the file have been deleted. GET$LEVEL Returns interrupt level of executing interrupt handler. RENAME$FILE Renames the file in the directory. EXIT$I NTERRU PT Interrupt handler's "END OF INTERRUPT" statement. CHANGE$ACCESS Changes access rights to a given file. User rights may.be added or changed. SIGNAL$INTERRUPT Used within interrupt handler to invoke interrupt task. TRUNCATE Truncates the file at the present file pointer. GET$PATH$COM PON ENT Returns the hierarchical directory tree traversal from the root to the file. WAIT$INTERRUPT Puts calling interrupt task in suspension until reinvoked by the interrupt handler. GET$DIRECTORY$ENTRY Returns the file's directory name. ENABLE Enables an external interrupt level. CREATE$DIRECTORY Creates a directory file. DISABLE Disables an external interrupt level. Supported Hardware SINGLE BOARD COMPUTERS BASIC 1/0 SUBSYSTEM CALLS iSBC 86/12A Single Board Computer CREATE$FILE Creates a file and establishes an I/O line or connection. If named, it also establishes access mode. Complete computer system on a single 6.75 x 12inch printed circuit board; includes an iAPX 86 (8086) CPU, system clock, 32K bytes of dual port RAM, sockets for 4K bytes (using Intel 2758), 8K bytes (using Intel 2716 or 2316E) or 16K bytes (using Intel 2732) of read only memory, multimaster MULTIBUS™ arbitration logic, 9-level programmable vectored interrupt control, 2 programmable BCD binary timers/counters, 24 programmable I/O lines with sockets for I/O line drivers and terminators, and a USART 8251A with associated RS232C drivers and receivers. ATTACH$FILE Establishes an I/O connection to an existing file. DELETE$CONNECTION Deletes an I/O connection to the specified file. GET$CONNECTION$STATUS Returns I/O connection status. GET$FILE$STATUS Returns file status. MASS STORAGE CONTROLLERS iSBC 204 Diskette Controller PHYSICAL$A TT ACH$DEVICE Binds file driver to device driver. Universal Flexible Diskette Controller; plugs into one MULTIBUS system slot. Controls most single density standard flexible diskette drives and minidrives. OPEN Opens a file for I/O. The file pointer is set to the beginning of the file. iSBC 206 Disk Controller CLOSE Undoes an OPEN. Disk Controller for 5440-type disk drives with 10M bytes per drive and up to four drives per controller; adapts to industry standard drives. READ Initiates an 110 read starting at the file pointer. WRITE Initiates an I/O write starting at the file pointer. USER iAPX 86 (8086)-BASED SYSTEMS The iRMX 86 system runs on user designed boards with the following components: SEEK Moves the file pointer. AFN·01528A • iAPX 86 (8086) -16-Bit Microprocessor 4-23 iRMX 86 • 8253 - Programmable Interval Timer (counter 0 mapped to I/O .locationODOH) • 8259A- Programmable Interrupt Controller (base port mapped to I/O location OCOH c;onnecting INT 2 to counter 0 of the 8253) . • 8251A - USART (base port mapped to I/O location OD8H when using the Terminal Handler) Documentation Package including: • Introduction toiRMX 86 Operating System (9803124-01 ) • iRMX 86 Nucleus, Terminal Handler, and Debugger Reference Manual (9803122-01) • iRMX 86 I/O System Reference Manual (9803123-01) iRMX 86 Shipping Package • iRMX 86 System Programmer's Reference Manual (142721-001) ISIS-II compatible diskettes containing: • • • • • iRMX 86 Nucleus iRMX 86 Terminal Handler iRMX 86 Debugging Subsystem iRMX 86 Basic Input/Output Subsystem· iSBC 204 Universal Flexible Diskette Device Driver • iSBC 206 Hard Disk Device Driver . • Preconfigured iRMX 86 System • iRMX 86 Installation Guide for ISIS-II Users (9803125-01 ) • iRMX 86.Configuration Guide for ISIS-II Users (9803126-01) . Registration Form Software Problem Reports One year of updates One man-week of training at any Intel Training Center offering iRMX 86 training. (G.ood for .6 months.) iSBC 957A Intellec-iSBC 86/12A Interface and Execution Package ORDERING INFORMATION Part Number Description RMX86 Operating System 4-24 AFN·01528A iRMX 88 REAL·TIME MULTITASKING EXECUTIVE • Performance-oriented nucleus • Designed for iAPX 88, iAPX 86-based applications • Easy-to-use interfaces • EPROM or RAM based • Systems tailored through Interactive Configuration Utility • Real-time priority-oriented scheduling • Effective system debugger • Disk file system software The iRMX 88 Real-Time Multitasking Executive is a small, performance-oriented executive system which can be used on Intel's 16-bit single board computers, iAPX 88 and iAPX 86-based boards. Based on the iRMX 80 Executive's field-proven and reliable architecture, the iRMX 88 Executive supports upgrading 8-bit based applications and helps the firsHime microcomputer customer with simple, easy-to-use interfaces for both the iSBC and component-based applications. The iRMX 88 Executive Software provides the innermost, software control layer for the CPU that supports real-time application requirements for intertask communication, asynchronous 110 control, priority-based resource allocation, and standard iSBC disk controller interfaces. The iRMX 88 Executive offers features that are suitable for reliable, performance-critical process control applications, production test stand units, sophisticated laboratory analysis, instrumentation, or specialized data acquisition and monitoring stations. Now, previous iRMX 80-based designs can upgrade to small size and high performance solution using the iRMX 88 Executive. The application wili be easily tailored using the Interactive Configuration Utility. Diagram 1_ Module Representation 4-25 .i iRMX 88 FUNCTIONAL DESCRIPTION The iRMX 88 Executive provides users of Intel Single Board Computers and user-designed boards utilizing iAPX 86, iAPX 88 CPUs, with facilities for executing concurrently, managing resources, and servicing asynchronous events. The iRMX 88 Executive provides simple, easy-to-use tools for creating a range of reliable high quality application systems. The foundation modules include support for real-time facilities including priority-based task scheduling, provide the means to concurrently monitor and control multiple events, provide real-time clock control, manage interrupts, and dispatch tasks. By staying within the 64K byte code and 64K data segment model, the operating system can maintain performance and minimize memory requirements; However, user tasks can access the full megabyte of data memory. The iRMX 88 Executive, as shown .in Diagram 1, contains the following modules: a Nucleus, Terminal Handler, Free Space Manager, Disk File System, Bootstrap Loader, Analog Handlers, Interactive System Debugger, and a Command Line Interpreter. Diagram 2. Consistent Structure User Configurable The iRMX 88-based applications can utilize a wide range of features or select only those which meet the specific requirements of the application system. The resultant system contains only the modules necessary for its use, allowing the iRMX 88 application system to be tailored to the application demands. The iRMX 88 Executive is constructed in a thoroughly modular manner with the full range of facilities being offered in library modules, allowing easy selection of the exact features required. Overhead for unused features is then eliminated, minimizing memory requirements. Because of the modularity and variety of services available with the iRMX 88 product, the user selects only those features needed for an effective application-specific operating system. This process of feature selection for a custom operating system is aided by a development tool, the Interactive Configuration Utility. After the user responds to a set of feature and configuration questions, the Interactive Configuration Utility integrates and configures the system readily from its library of quality, tested system features. An interactive configuration development tool provides an easy-to-use method of configuring the iRMX 88-based application. Responding to questions from the utility program executing on the Intellec Microcomputer Development System, the user quickly tailors the operating system features to. meet specific application needs. Task Interfaces FEATURE OVERVIEW The iRMX 88 Executive utilizes a simple, straightforward programmer interface for user tasks. This consistent interface reduces the complexity and number of concepts which must be learned. The iRMX 88 Executive products provide users with simple, easy-to-use, quality software tools for ceating a wide range of application systems. The most important features are: Structured Application Environment EPROM or RAM Based The iRMX 88 Executive provides a consistent structure from application to application, CPU to CPU, thus allowing experience gained on one system to be easily transferred to others. Often, entire tasks may be ported from one application to another. As shown in Diagram 2, the Executive manages the hardware interface and provides a standard interface to the application. When the Executive supports future hardware, the Executive may have new control software, but the application layer interface remains the same. The iRMX 88 Executive system can be totally EPROM resident or bootstrap loaded from a mass storage device into RAM, depending upon application requirements. Being able to place all of the software in EPROM offers two benefits. First, it does not require a disk for bootstrap loading. This is convenient when mass storage devices cannot be used because of the danger of contamination. Second, the overhead expense of mass storage devices is eliminated when the application can be prommed. 4-26 iRMX88 Nucleus signed a lower priority than interrupt task priori· ties, to avoid blocking interrupts. The iRMX 88 Executive provides control software for operation on various iSBC 16·bit Single Board Computers, and can be used f.or user iAPX 86, iAPX 88·based boards. The iRMX 88 Nucleus pro· vides a foundation upon which a variety of applica· tion systems can be built. Table 1. Nucleus Primitives Operands Return Value ROACPT exch·addr addr Accept a message from speci· fled exchange. Returns message address if available. zero otherwise. ROCTSK STD·addr none Create task by building new Task Descriptor based on specified Static Task Descriptor. ROCXCH RAM·addr none Create exchange at specified RAM address. RODLVL level none Disable specified level. RODTSK TD·addr none Delete task specified by Task Descriptor. RODXCH exch·addr byte Delete specified exchange. ROELVL level none Initialize message portion of the fnterrupt Exchange De· scriptor associated with the specified interrupt level (the first time called only). and en· able specified interrupt level. ROENOI none none Signals end-ot·interrupt in user· supplied interrupt service routine. ROISND IED·addr none Send an inter~upt message to Ihe specified interrupl ex· change. RORESM TD·addr none Resume a task that has previ· ou:;;,ly been suspended. ROSEND exch·addr. msg·addr none Send the message located at "msg'addr" to the exchange specified by "exch·addr." ROSETV addr. level none Set interrupt vector. Interrupts at the specified level are serviced by the user-supplied routine starting at "addr." Ihus by· passing Nucleus interrupt soft~ ware. ROSUSP TD·addr none Suspend execution of the task ·specified by the Task Descrip· tor. ROWAIT exch·addr. time·limit add, Wait at the specified exchange until a message is available or time limit expires ..Return address of system time-out mes-. sage or user message. Name The iRMX ""3 Nucleus is the heart of an iRMX 88·based operating system. All other subsystems require the Nucleus. Embedded in the Nucleus are two main facilities: first, the facility for concurrent program execu· tion; second, the facility for handling simultane· ous asynchronous events. The typical iRMX 88· based application solution requires real·time reo sponse. For example, interrupts (samples per sec· ond) coming from specialized peripheral devices must be serviced in an efficient manner. Since the concepts are portable from CPU to CPU, iRMX 88· based systems allow the hardware and software to be used by more than one application, thus reo ducing the overall system and hardware costs. Designed toward performance'oriented solutions, the multitasking architecture provides the power necessary to solve the complex problems of today and tomorrow. The system comprises uniform system calls ensuring that the Nucleus is both easy to learn and easy to extend. Only two con· cepts must be mastered to learn the system: the user·task requests to the Nucleus for service; and the definition of the system configuration. These concepts require the understanding of the terms: task, messages, and exchanges. These three items can be created and deleted dynamically. The Nucleus provides two levels of interrupt management, an interrupt handler and an interrupt task. One provides speed for high performance samples per second requirements and the other provides flexibility. The interrupt handler permits only Nucleus interrupt system calls to be issued and masks all interrupts. The interrupt task per· mits all Nucleus system calls to be issued and masks only lower priority interrupts; this is very effective for interrupt management at a lower fre· quency. Function interrupt Free Space Manager The iRMX 88 Free Space Manager provides the capability of dynamically allocating RAM space based upon user requests. The Free Space Manager allows efficient use of RAM in the iRMX 88·based system by reclaiming RAM space that is no longer needed by a task, thereby making it available for use by other tasks. This allows RAM space to be treated as a common resource, shared dynamically by a number of tasks. Priority Levels Handling an interrupt with respect to other work in the system can be completely user controlled. Nucleus external interrupt levels are directly reo lated to task priorities. The priority of the execut· ing task determines which interrupts are masked. Generally, software background tasks will be as· 4·27 iRMX88 Table 2. Disk File System Services System Debugger The iRMX 88 product provides an interactive software debugger. The System Debugger has two capabilities that greatly simplify the process of debugging a multitasking system. First, the Debugger allows examination of the task while the system continues to operate. Second, the Debugger lets the programmer interactively view and modify system constructs and RAM data space. Service Function Data Transfer Services Prepare a file for processing. OPEN Transfer data from an open file to memREAD ory. Transfer data from memory to an open WRITE file. Set or return value of disk file marker. SEEK Terminate processing of an open file. CLOSE Directory Maintenance Services Remove a file from the directory ·and re-, DELETE lease its space. RENAME Change the nameof a file in the directory. Change an attribute of a file in the direcATTRIB tory. Other Services FORMAT Initialize a new disk. I· LOAD Read a file of executable code, into memory. DISKIO Perform fundamental disk sector operations. Comprehensive 1/0 Support The iRMX 88 software libraries contain support for a wide range of iSBC 110 boards manufactured by Intel. This support simplifies· the' addition of peripherals to MULTIBUS-compatible application systems. For applications which require custom boards the iRMX 88 architecture allows easy addition of user~written device handlers. The iRMX 88 Disk File System (DFS) provides disk access capabi lities to i RMX 88 operating systems. The term "disk" will refer generally to both hard disk and floppy disk products. The services operate in the real-time environment supported by the Nucleus. Files may be created, deleted or changed. Data may be accessed sequentially and directly ("randomly"). Bootstrap Loader The iRMX 88 Bootstrap Loader is an extension to the operating system that adds considerable flexibility toiSBC disk controller-based systems. The Bootstrap Loader allows those applications using disk to create essentially a "soft" system that may be loaded into RAM from disk rather than being permanently EPROM resident. This offers greater flexibility in building and maintaining an applicationthat is disk-based. Many applications do not need all the services which DFS offers. The modular design of the system allows DFS functions to be implemented selectively, thereby keeping memory requirements consistent with the needs of the application. DFS performs most of the activities required to manage real-time disk operations. (See Table 1.) The user does not have to be concerned with scheduling and coordinating the multiple and sometimes conflicting requests that typify realtime operation. By taking responsibility for these activities, and for the maintenance of system integrity, DFS encourages the user to concentrate on solving the application problem at hand. - Since application software is stored on disk rather than in ROM, changes are easier to implement. A mod'ificationto application software entails changing the contents of the disk rather than replacing the ROM. -Because the disk has a much larger storage capacity than does the ROM, multiple tasks can be stored on disk with the Bootstrap Loader • bringing them into. RAM on demand. This feature allows a singleiSBC-based, solution to be used for more than one application. In addition to presenting a complex control situation, real-time applications often have demanding performance requirements. DFS helps maximize system throughput by allowing user tasks to overlap disk operations with processor operations and by allowing multiple disk operations to proceed in parallel. For example,files can be "double buffered" so that while DFS is filling (or emptying) one buffer, the user task can be processing the data in the other, reducing the time the task spends waiting for 110. Terminal Handler The iRMX 88 product includes aTerminal Handler module that provides real-time asynchronous 110 between an operator's terminal and tasks executing under the iRMX88 Nucleus. User tasks can utilize. input data obtained from the Terminal Handler. Output may be at the level of a Single character, a logical line, or a set of lines. 4-28 iRMX 88 for the CLI, thus satisfying a demand for unique input command requests. Command Line Interpreter The iRMX 88 Command Line Interpreter (CLI) is a task that provides a powerful man-machine interface for interactive control of system resources and utilities. The CLI can be readily ~ configured with the iRMX 88 Terminal Handler. Examining an input message, the CLI will pass the message to the appropriate utility task. The utility tasks provided with the system include. FORMAT, DIR(ectory), and COPY. Analog Handlers The iRMX 88 Executive offers Analog Handlers which provide. a convenient mechanism for performing AID and.o/A conversions, utilizying Intel's iSBC Analog Boards. The Analog Handlers perform repetitive, sequential, single or variable gain, random channel input and random channel output. The input and output modules are individually configurable, allowing greater application flexibility for minimum size systems. In addition, a greater degree of flexibility for tailored application is available; the user can add application-oriented commands to the vocabulary .!::.: iSBC iAPX 88 and iAPX 86 Memory Requirements Memory Requirements·· (Bytes) Module Minimal Free Nucleus Terminal Space Handler Manager PROM' 3.5K 1.2K 2K RAM 270 140 500 Minimum Development System Requirements Disk File System Disk 1/0 Analog 1/0 Bootstrap Loader & Initializer Operating System Memory Size (Bytes) Minimum Diskette Drives 11K 1.4K 1.6K 1.2K ISIS-II 64K RAM 2 ·Indicates amount of code which can be configured in PROM . •• All figures are approximate for education purposes only. SPECIFICATIONS iSBC 724/724A iSBC 732/732A iSBC Supported Hardware MULTIMODULE Boards iSBX 337 numerical data processor iSBX 351 serial 1/0 Single Board Computers iSBC 88/40 iSBC 86/05 iSBC 86/12A User iAPX 86 and iAPX 88- Based Systems Mass Storage iSBC 208 flexible disk controller iSBC 215A/215B 8-inch Winchester disk controller iSBC 220 SMD disk controller The iRMX 88 system runs on user-designed boards with the following components: • 8253-Programmable Interval Timer (counter 0) • 8259A-Programmable Interrupt Controller (INT1 to counter 0 of 8253) • 8251A-USART or iSBX 351 when using Terminal Handler Analog Boards iSBX 311 iSBX 328 iSBC 711/711A 4-29 iRMX 88 ORDERING INFORMATION Part Number Description iRMX 88 NUCLEUS, Terminal Handler, Free Space Manager for iAPX 88 (8088), iAPX 86 (8086) support including iSBC 86/12A, iSBC 88/40. Package also includes Interactive Configuration Utility program for execution on an Intellec Microcomputer Development System. Not Available Not Available The modules which include the debugger, CLI, and utility software modules COPY., DIR, and FORMAT. Not Available Analog Handler modules for support of iSBC 711/711A, iSBC 724/724A, iSBC 732/732A, iSBX 311, iSBX 328. iRMX 88 DOC Documentation Package including • Introduction to the iRMX 88 Executive • iRMX 88 Systems Reference Manual • iRMX 88 Installation Guide • iRMX 88 Configuration Utility Guide • iRMX 88 Application Guide Not Available Disk File System, modules for iSBC 208, iSBC 215A/215B, iSBC 220 disk controllers, and supports user-defined controllers. Not Available 4·30 = =.0. iSBC 957A INTELLEC® -iSBC 86/12A INTERFACE AND EXECUTION PACKAGE • Establishes communication between the iSBC 86/12A board and the Intellec® Development Systems to aid in iAPX 86/8086 software development • Offers "virtual terminal" capability which permits the Intellec® console to access the iSBC 86/12A monitor • Allows full speed execution of iAPX 86/8086 programs • Provides powerful console commands for software debug . • Includes EPROM resident system monitor for iSBC 86/12A Single Board Computer • Allows ac::cess to all iSBC 86/12A memory, registers, flags and. 110 ports· • Allows Intellec® ISIS·II files to be trans· ferred between iSBC 86/12A board and Intellec® Microcomputer Development System • Includes all necessary hardware, software and documentation The Intel®iSBC 957A Intellec® -iSBC 86/12A Interface and Execution Package contains all the necessary hardware, software, cables and documentation required to interface an iSBC 86/12ASingie Board Computer to an Intel lee Micro· computer Development System for software development and full·speed execution. 4·31 ~--::--" .-_.... ~. iSBC957A FUNCTIONAL DESCRIPTION registers and memory, perform port 1/0, move a block of 'memory, compare blocks of memory, search for a wordl byte value, and perform hex arithmetic. In addition, the monitor provides for the recognition of interrupts via a user-defined table. The program on, the diskette contains communication software which passes appropriate console commands to the iSBC 86/12A resident monitor and also interfaces with the ISIS-II operating system to transfer files between the development system diskettes and the iSBC 86/12A board. Overview The iSBC 957A Intellec-iSBC 86/12A Interface and Execution Package' extends, the software development capabilities of the Intellec Microcomputer Development Systems to the iSBC 86/12 and iSBC 86/12A Single Board Computers. It allows software modules developed under the Intellec resident ISIS-II ,Operating Systems to be down-Ioa,ded to the iSBC 86/12A board for full-speed execution and debug. In addition, the iSBC 957A package allows segments of iSBC 86/12A memory to be saved on floppy disk files. Special communication software allows transparent access to the powerful debug commands, in the iSBC 86/12A monitor. from the Intellec console terminal. ' " ' System Interfacing, The physical interface between the Intellec Microcomputer Development System and the iSBC 86/12A board is accomplished with cables supplied ",iththe iSBC 975A package. The cabling arrangement varies depending on whether the system is a member of the Intellec MDS-800 family or one of the Intellec Series II family. Software Capabilities Intellec Series II Interface - For Intellec Series II Development Systems the connection between it and the iSBC 86/12A board is accomplished with either a Single serial lineintercorinecting the iSBC 86/12A serial port with serial port 1 on the Intellec system, or a parallel cable from ttie UPP port to the parallel port on the iSBC 86/12A board. ·AII communication including' command and data transfer occurs over this line. The software included in the iSBC 957A package consists of the iSBC 86/12A monitor residing on jour intel EPROMs which are inserted into sockets,on the iSBC 86/12A board. A diskette is also included which contains the Intellec resident communications software that links the iSBC 86/12A board with the Intellec Microcomputer Development System. The EPROM resident software creates an execution environment in which object modules may be loaded into the iSBC 86/12A memory, executed at full speed, modified if necessary and saved on the Intel lei: system floppy disk. The monitor provides the ability to execute selected program segments with breakpoints or by single stepping, examine and modify Intellec® Environment An Intellec Microcomputer Development System to be used in conjunction with the iSBC 957A package and an iSBC 86/12A board must have the following necessary INTELLEC' SERIES II MODEL 220, 230 ISBC86112 OR SERIAL 110 iSBC 86112A " r" , PORT ~, ',' )), . OEM RS232,C CABLE .", . Figure 1. IntelleC® Series Models 220, 230 Serial Connection AFN-01529A 4-32 iSBC957A PARALLEL 110 -.......~.-r~PORT ISBC 86112A BOARD Figure 2. Intellec® Series Models 220, 230, 240 Parallel Connection functionality to support program development and stor· age: should include the following components for effective utilization: 1. Intellec Development System with 64K bytes of RAM. 2. Console CRT or TTY terminal. 3. Intellec MDS·DDS Dual Double Density Diskette Drive and ISIS·II Operating System or Intellec MDS· 2DS Dual Single Density Diskette Drive and ISIS·II Operating System. 4. User·selected language translators. 1. An iSBC 86/12A Single Board Computer. 2. An iSBC 957A Intellec-iSBC 86/12A Interface and Execution Package. 3. An iSBC 655 or iSBC 660 System Chassis for' power and MULTIBUS expansion. 4. One or more iSBC 032, 048, or 064 RAM boards for programs requiring more than 32K bytes of RAM. Note: The iSBC 86/12A cannot be mounted in the Intellee system and requires a separate operating environment. Note: The Intellee Series II Model 230 Microcomputer Development System and the Intel lee MDS·800 Microcomputer Development Center con· tain all necessary hardware and operating system software to be used with the iSBC 957A package and the iSBC 86/12A board. Additional memory boards, analog and digital 1/0 boards, and peripheral controllers can be included in the iSBC 660 System Chassis with the iSBC 86/12A to allow the execution environment to be equivalent to the expected final product configuration. Execution Environment A full capability iSBC 86/12A execution environment Drivers and terminators needed when parallel load cable is required SPECIFICATIONS Hardware Interface Adapters (1) iSBC 530 TTY adapter - Used when serial 1/0 line connects with TTY port on Intellec system (1) Parallel port status adapter - Mounts on iSBC 86/12A when parallel load cable is required Cables (1) OEM RS232-C cable - Mates with serial 1/0 port on iSBC 86/12A (1) RS232-C port cable - Mates with RS232-C port on Intellec system (1) TTY port cable - Mates with TTY port on Intellec system (1) Parallel load cable - Mates with UPP port on Intellec system and parallel 1/0 port on iSBC 86/12A Miscellaneous Attachment mounted connectors for Intellec Software (4) EPROMs with iSBC 86/12A system monitor (1) Single density floppy diskette with iSBC 86/12A ISIS· II communication software (1) Double density floppy diskette with iSBC 86/12A ISIS-II communication software All cables allow separation of Intellec system and iSBC 86/12A of up to 6 feet. 110 (1) (4) (4) screws Drivers and Terminators 7437 48 mA open collector drivers iSBC 901 220D/330D terminator packs iSBC 902 1 kD terminator packs System Monitor Addresses: RAM: 00000-006FFH; ROM: FEOOO-FFFFFH 4-33 AFN-01529A iSBC957A Transfer Rates Commarids Command L Load G Go Function Loaas absolute object liIe from Intellec into ISBC 86/12A memory. Transfers control of the 8086 CPU to the user program. X Examine Loads absolute object liIe from Intellec into ISBC 86/12A memory and begins execution. Loads a blo~k of iSBC 86112A memory Into an Intellec file. Displays and executes one Instruction at a time. Displays or modifies 8086 registers. R Load and Go T Upload N Single Step D Display Displays contents of a memory block. S Substitute Displays/modifies memory locations. M Mov.e F Find C Compare I Input Moves the contents of a memory block. Searches a memory block or a constant. o Outputs data to output port. Prints values of literals. Output P Print E Exit Comment Compares two memory blocks. Inputs and displays data from Input port. Exits the loader program and returns to ISIS·II. Rest of line is a comment. ORDERING iNFORMATION Part Number Description sac 957A Intellec-iSaC B6/12A Interfacing and Execution Package. Intellec MDS·BOO Family Serial transfer: 37K byteslminute Parallel transfer: 96K byteslmlnute Intellec Series II Family Serial transfer: 37K byteslminute Parallel transfer: 29K byteslmlnute Reference Manuals Isac B6/12A Hardware Reference Manual 142849·01 - iSaC 957A Intellec-iSaC B6/12 Interface and Execution Package User's Guide 9800640 - BOB6 Assembly Language Manual Peripheral Controllers 5 iSBC 202 DOUBLE DENSITY DISKETTE CONTROLLER • iSBC 80, iSBC 86 and iSBC 88 compatible interface, control and DMA logic for high speed, high capacity random access bulk storage • DMA channel allows single board computer to process in parallel with block transfer between diskettes and memory • Provides control of up to four single sided flexible diskette drives • Complete CRC data checking • Soft·sectored format allows SOOK·byte data storage capacity per double density. diskette • Compatible with Shugart SA 800·1 and other similar double density diskette drives The iSBC 202 Double Density Diskette Controller is an interface between the MULTIBUS system bus and double density flexible diskette drives via a direct bus interface. Designed with Intel's powerful 3000 Series of microprogrammabie bit-slice microprocessors, the iSBC·202 provides a high speed, efficient, and easy to use high capacity random access bulk storage interface to Intel's family of single board computers. Software support for the iSBC 80 Series of 8-bitsingle board computers is provided through RMX/80, the Real-Time Multitasking Executive. 5-1 __ • .:..-:.. c..:::. "-_ _ .!.:......I iSBC 202 FUNCTIONAL DESCRIPTION loaded (i.e., to come in contact with the diskette platter), cause the head to move to the proper track and verify successful operation. The interface board accepts the data being read off the diskette, interprets synchronizing bit patterns, checks the validity of the data using a cyclic redundancy check (CRC) polynomial, and then transfers the data to the channel board. The diskette controller is capable of performing seven different operations: recalibrate, seek, format track, write data, write deleted data, read data, and verify CDC. The iSBC 202 Double Density Diskette Controller provides an easy to use interface for OEM use of Intel single board computers and other manufacturers' flexible diskette drives. All DMA logic is provided so no additional boards or circuitry are required, and up to four double density flexible diskette drives may be interfaced with each iSBC 202. The controller facilitates recording of all data.in soft-sector format. The controller consists of two. boards which may reside, in System Chassis, the iSBC 604 or 614 Modular Cardcage/Backplane, or in an OEM custom designed iSBC 80 buscompatible with a majority of double density specified flexible diskette drives. The microprogrammed track format consists of 52 sectors with 128 bytes per sector. The Shugart SA 800-1 drive is fully compatible with this dense track format due to its "straddle-erase" magnetic head. Use of other manufacturers' flexible disk drives is accommodated also, with the limitation that after any "write data" operation, the CPU must delay 500 P.s before issuing another read or write command (due to the "delayed-erase" magnetic head). Therefore, use of multi-sector "write data" commands is only possible with the SA 800-1 drive. Write Operations - During write operations, the interface board outputs the data and clock bits to. the selected drive at the proper times, and generates the CRC characters' which are then appended to the data_ Memory Operations - When the diskette controller requires access to the system memory, the interface board requests and maintains DMA transfer control of the system bus, and generates the appropriate memory command. The interface board also acknowledges I/O commands as required by the MULTI BUS system bus. Programming Capability 10PB Function - The I/O Parameter Block (IOPB) has been designed to allow simplified I/O programming where necessary, and to facilitate a high level of sophistication in system-level I/O drivers in more complex systems. All diskette operations are initiated by an Intel single board computer with standard 110 commands. Once initiated, however,the diskette controller completes the specified operation without further intervention on the part of the CPU. Only three general steps are performed by the CPU to complete any diskette operation: Channel Board Channel Board Function - The channel board is the primary control module within the diskette controller. It receives, decodes, and responds to channel commands from the central processor unit (CPU) on the Intel iSBC Single board computer. The channel board can access a block of system memory to determine the particular diskette operations to be performed and fetch the parameters required for the successful completion of the specified operation. 1. The CPU must prepare and store in system memory an 10PB for each operation to be performed. Control Function - The control functions of the channel board have been achieved with an 8-bit micropro' grammed processor, designed with Intel's Series 3000 Bipolar Microcomputer Set. This 8-bit 'processor includes four 3002 central processing elements (2-bit slice per CPE), a 3001 microprogram control.unit, and 512 x 32 bits of3604A programmable read-only-memory (PROM) which stores the microprogram'. It is the execution of the microprogram by the microcomputer set which actually effects the control capability of the channel board. 2. The CPU then passes the memory address of the 10PB to the diskette controller. . 3. The CPU., must process the resultant information from the diskette controller upon ,completion of the operation. IOPB Format ....,.In preparing the IOPB, the CPU requires nCl interaction with the diskette controller. The IOPB is prepared as any block of data in memory would be prepared, utilizing the following formal for the 7-byte parameter block: < Interface Board Byte 1 2 3 4 5 6 7 Interface Board Function - The interface board provides the iSBC 202 Double Density Diskette Controller with a means of communicating with the diskette drives, as well as with the system bus. Under control of the microprogram being executed on the channel board, the interface board generates those signals which cause the read/write head on the selected drive to be 5-2 . "'" Command Channel word Diskette instruction Number of sectors Track address Sector address Buffer address (lower) Buffer address (upper) iSBC 202 Environmental Characteristics SPECI FICATIONS Temperature Operating: O·C to 55·C Non·Operating: - 55·C to + 85·C Media Flexible diskette One recording surface 77 tracks/diskette 52 sectors/track 128 bytes/sector 512,512 bytes/diskette Humidity Operating: Up to 90% relative humidity without conden· sation Non·Operating: All conditions without condensation of water or frost Physical Characteristics Equipment Supplied Mounting - Occupies two slots of System 80 chassis or iSBC 604/614 cardcage, uses P2 connectors for Inter· board communication. Height (ea) - 6.75 in. (17.15 mm) Width (ea) - 12.00 In. (30.48 mm) Depth (ea) - 0.50 In. (1.27 mm) Weight (ea) - DDFDC channel board DDFDC interface board Dual auxiliary board connector (P2 socket) Reference Manuals 9800420 - iSBC 202 Hardware Reference Manual (NOT SUPPLIED) Electrical Characteristics Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051 DC Power Requirements Channel Board: 5V @ 3.75A typ, 5A max I nterface Board: 5V @ 1.5A typ, 2.5A max; - 5V @ 0.1 A typ, 0.2A max ORDERING INFORMATION Part Number Description SBC 202 Double Density Diskette Controller 5·3 ·iSBC 204 SINGLE DENSITY FLEXIBLE DISKETTE CONTROLLER • Full compatibility with iSBC 80, iSBC 86, and iSBC 88 Single Board Computers ' , • DMA input/output allows single board computers to process in parallel With diskette transfer ()perations .' • Direct compatibility with most single-. density" soft-sectored standard- (8") and mini-size (51A1") flexible diskette drives • Software supported by RMXl80 and" RMXl86 Real-Time Multitasking ExecutiVE!, disk file system . • Programmable track-to-track access, head-settling, and. head-load tim~s ' • On-board data separation logic • Read, write, verify, and search on single or multiple sectors; • Single + 5V supply The Intel iSBC 204 Single Density Flexible Diskette Controller is a single board universal·diskette controller capable of supporting virtually any software-sectored, single density diskette drive. The standard iSBC 204 Controller can control two drive surfaces (two single-sided drives or one double-sided drive). With the addition'of asecorid (optional) ·Iritel 8271 component, up to four drives can be supported. In addition to the standard IBM 3740 formats, the controller supports sector lengths of up to 4096 bytes plus mini-size drive formats. The iSBC 204's wide range of drive compatibility is achieved without compromising performance. The operating characteristics (track-to-track access, head-load, and head-settling times) are specified under user program control. The controller can' read, write, verify, and search either single or multiple sectors. . ..,. iSBC 204 FUNCTIONAL DESCRIPTION Interface Characteristics Intel's 8271 Floppy Disk Controller (FDC) circuit is the heart of the iSBC 204 Controller. On-board data separation logic performs standard FM encoding and decoding, obviating external separation circuitry at the drive. Diskette data transfers are DMA (direct memory access) through an on-board intel 8257 DMA controller circuit which manages DMA transfers and signals the master iSBC processor on completion of the transfer. A block diagram of the iSBC 204 Controller is shown in Figure 1. Expandability - Each standard iSBC 204 Controller includes a single 8271 FDC circuit capable of supporting two drive surfaces. Optionally the iSBC 204 may be expanded to support four single-sided (or two doublesided) drives with the insertion of a second 8271 component into an on-board socket. Simplified Interface - The cables between the iSBC 204 Controller and the drivels) may be either low cost, flat ribbon cable with mass termination connectors or twisted pair conductors with individually wired conp.ecttors. An on-board, cross-connect matrix allows optional drive control and status signals to be connected while maintaining pin-to-pin compatibility. Universal Drive and MULTIBUS Compatib,lity Because the iSBC 204 Controller has universal drive compatibility, it can be used to control virtually any standard- or mini-sized single density diskette drive. Moreover, the iSBC 204 Controller fully supports the microcomputer industry standard' MULTIBUS system bus and can be used with. any single board computer or system compatible with Intel's bus. Because the iSBC 204 Controller is programmable, its performance is not compromised by its universal drive compatibility. The track-to-track access, head-load, and head-settling characteristics of the selected drive model are program specified. Data may be organized in a fully compatible IBM 3740 sector format, in sectors up to' 4096 bytes in length, or in formats compatible with the mini-sized diskette drives. Programming The powerful 8271 FDC circuit is capable of executing high-level commands that simplify system software development. The device can read, write, and verify both single and multiple sectors. CRC characters are generated and checked automatically. Up to two tracks on each surface may be designated "bad" and logically removed from the diskette. Sector Scanning - Scan commands permit sectors to be searched for a specified data pattern or "key". During scan operations the pattern image from memory is continuously compared with a sector or multiple sectors J1 BUS CONTROLLER 8257 DMA CONTROLLER AD, A1 8271· FDC 13 TO DRIVE 1 MULTIBUS P1 J2 ADDRESS REGISTER AD-A7 DRIVERS ADRo/·AD131 13 TO : DRIVE AO,A1 IN~~~:~:T I - - - - - - - - - - - - - - - - - - - - - - - - - - - - j '-----' Figure 1. iSBC 204 Single Density Diskette Controller Block Diagram 5-5 iSBC204 read from the diskette. No CPU intervention is required until a match is found or all specified sectors have been searched. ing systems. Files are named symbolically and may be created, deleted, or changed. Program Initiation - All diskette operations are in· itiated by standard input/output (I/O) port operations through an iSBC single board computer. System software first initializes the controller with the operating characteristics of the ·selected drive. The diskette is then formatted under program control. For subsequent transfers,. the starting memory address and transfer mode are specified for the DMA controller. Data transfers occur in response to.commands output by the CPU. Data may be accessed sequentially or directly. An un· limited number of files can be open simultaneously and multiple tasks may read the same file concurrently. A listing of service functions included under RMX/BO and RMX/86 is shown In Table 1. Table 1. Services Available Under RMXJ80 and RMXJ86 Operation Funcllon Open Read Write Seek Close Delete Data Transfer - Once a diskette transfer operation has been initiated, the controller acts as a bus master and transfers data over the MULTIBUS at high speed .. No CPU intervention Is required until the transfer is complete as indicated either by the generation of an Interrupt on the bus or by examination of a "done" bit by the CPU. RMX/80 and RMX/86 Real·Time Executive Software Support Rename Format Load The iSBC 204 Controller is supported by the disk file system of RMX/BO and RMX/B6, Intel's real-time operat· Disk I/O Prepares a file for processing. Transfers data from open file to memory. Transfers data from memory to open file. Enables direct access. Terminates processing of file. Removes file from directory, releases its space. Changes name of file. Initializes a new disk. Reads a file of executable code into memory. Performs basic I/O operations. Data Organization and Capacity SPECI FICATIONS (Standard Size Drives) IBM Format Compatibility CPU - Any iSBC MULTI BUS computer or system mainframe. Drive - Bytes per sector 128 Sectors per track 26 Non·IBM Format 1024 4 I I 2048 2 I I Up to 255 Bytes per diskette (77 tracks) 256,256 (128·byte sector) 295,680 . (256·byte sector) 315,392 (512-byte sector) 315,392 4096 '1 Drive Characteristics Standard Size Transfer rate (KBfsec) Disk speed (RPM) CDC 9404 GSI110 MEMOREX 550 MEMOREX 552 (dual·sided) SHUGART 800 SHUGART 850 (dual·slded) WANGCO 765 PERTEC 650 (SOlDO, DBL. Head) 15 I 512 I 8 77 Single density, standard- (B") and mini-sized Standard Size 256 Tracks per diskette (51/4") diskette drives. The standard iSBC 204 Controller supports two single·sided drives or one double-sided drive. By adding an (optional) 8271 FDC, four single· sided or two double·sided drives may be supported. The following drives are known to be compatible: I I Track-to·track access (programmable) Mini Size PERTEC FD200 SHUGART SA400 WANGC082 Mini Size 250 125 360 1 to 255 ms in 1 ms steps 300 o to 255 ms 2 to 510 ms In 2 ms steps Head settling time (programmable) in 1 ms steps Ot0510ma in 2 ms steps Head load time (programmable) o to 60 ms In 4 ms steps Oto 120ms In 8 ms steps Equipment Supplied ISBC 204 Controller Reference Schemallc Controller-to-drive cabling arid connectors are not supplied with the iSBC 204 Controller. Cables can be fabricated easily using either flat ribbon cable or twisted pair conductors with commercially available connectors as described in the iSBC 204 Hardware . Reference Manual. Diskette - Unformatted IBM Diskette 1 (or equivalent single-sided); unformatted IBM Diskette 2 (or equivalent double-sided); unformatted Shugart SA104 Diskette (or equivalent mini). 5-6 iSBC204 Optional Equipment Environmental Characteristics 8271 Flexible Diskette Controller Component - Addi ng a second 8271 device to the fully tested circuit on the iSBC 204 Controller allows four drive surfaces to be sup· ported. Temperature - O°C to 55°C (operating); - 55°C to + 85°C (non·operating) Humidity - Up to 90% relative humidity without con· densation (operating); all conditions without condensa· tion or frost (non·operating) Physical Characteristics Reference Manuals Width - 6.75 in. (17.15 em) Height - 0.5 in. (1.27 em) Length - 12.0 in. (30.48 em) Shipping Weight - 1.75 Ib (0.80 kg) Mounting - Occupies one slot of iSBC system chassis or iSBC 604/614 cardcage. 9800568 - iSBC 204 Diskette Controller Hardware Ref· erence Manual (NOT SUPPLIED). 9800522 - RMX/80 User's Guide (NOT SUPPLIED). Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature' Department, 3065 Bowers Avenue, Santa Clara, California 95051. Electrical Characteristics Power Requirements - 5.0V (± 5%), 2.5A max ORDERING INFORMATION Part Number Description SBC 204 Universal Flexible Diskette Controller 5·7 ')SBC 208 FLEXIBLE DISK CONTROLLER • Compatible with: all iSBC 80,iSBe 86, and iSBC. ,88 Single . .Board Computers .. ' . ' • Phase lock loop data separator assures maximum data integrity. ' . , • Cor,trols most si,rlgle anddou~le densi~y • Read, write, verify, and search on single or multiple sectors .... diskette drives • On-board iSBX' bus for additional functions • Single + 5V Supply • User-programmable drive parameters allow wide choice of drives • Capable of addressing 16M bytes of system memory , The Intel iSBC 208 Flexible Disk Controller is a diskette controller capable of supporting virtually any softsectored, double density or single density diskette drive. The standard controller can control up to four drives with up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats, the controller supports sector lengths of up to 8192 bytes. The iSBC 208 board's wide range of drive compatibility is achieved without compromising performance. The operating characteristics are specified under user program control. The controller can read, write, verify, and search either single or multiple sectors. Additional capability such as parallel or serial 1/0 or special math functions can be placed on the iSBC208 board by utilizing the iSBX bus connection. 5-8 iSBC208 Universal Drives and the iSBC 208 Controller FUNCTIONAL DESCRIPTION Because the iSBC 208 Controller has universal drive compatibility, it can be used to control virtu· ally any standard· ormini·sized diskette drive. More· over, the iSBC 208 Controller fully supports the iSBX bus and can be used with any iSBX module compatible with this bus. Because the iSBC 208 Controller is programmable, its performance is not compromised by its universal drive compatibility. The track·to·track access, head·load, and head· unload characteristics of the selected drive model are program specified. Data may be organized in sectors up to 8192 bytes in length. Intel's 8272 Floppy Disk Controller (FDG) circuit is the heart of the iSBC 208 Controller. On·board data separation logic performs standard MFM (double density) and FM (single density) encoding and decoding, eliminating the need for external separation circuitry at the drive. Data transfers between the controller and memory are managed by a DMA device which completely controls trans· fers over the MULTIBUS system bus. A block dia· gram of the iSBC 208 Controller is shown in Figure 1. STANDARD DRIVES (B") MINI·DRIVES (5%") .~ i J2 CONNECTOR Jl CONNECTOR i I f-----+ ISBX CONNECTOR f! i DATA BUS(B) JI - I I AUX PORT TIMING PLL ~ i 0 1 U (16) f-----+ l- B272 FDC .-- '0 - t SEGMENT REGISTER U I B21B BUS CONTROLLER 1 ADDER (20) . I I (16) ./ ADDRESS BUFFER (24) .A I U - B237 DMAC I- ft r 10 DECODE DATA BUFFER I ADDRESS BUS (B) DATA BUS ... MULTIBUS SYSTEM BUS Pl ... Figure 1. iSBC 208 Flexible Disk Controller Block Diagram 5·9 iSBC 208 Interface Characteristics The standard iSBC 208 Controller includes an Intel 8272 Floppy Disk Controller chip which supports up to four drives, single or double sided. SIMPLIFIED INTERFACE-The cables between the iSBC 208 Controller and the drive(s) may below cost, flat ribbon cable with mass termination connectors. The mechanical interface to the board is a right-angle header with locking tabs for security of connection. PROGRAMMING-The powerful 8272 FDC circuit is capable of executing high-level commands that simpl ify system software development. The device can read, write, and verify both single and multiple sectors. CRC characters are generated and checked automatically. Recording density is selected at each Read and Write to support the industry standard technique of recording basic media information on Track 0 of Side 0 in single density, and then switching to double density (if necessary) for operations on other tracks. Program Initiation-All diskette operations are initiated by standard inputloutput (1/0) port operations through an iSBC single board computer. System software first initializes the controller with the operating characteristics of the selected drive. The diskette is then formatted under program control. For subsequent transfers, the starting memory address and transfer mode are specified for the DMA controller. Data transfers occur in response to commands output by the CPU. Data Transfer-Once a diskette transfer operation has been initiated, the controller acts as a bus master and transfers data over the MULTIBUS at high speed. No CPU intervention is required until the transfer is complete as indicated either by th.e generation of an interrupt on the bus or by examination of a "done" bit by the CPU. iSBX BUS SUPPORT - One connector is available on the iSBC 208 board which supports the iSBX system bus. This connector supports single-byte transfer as well as higher-speed transfers supervised by the DMA controller. Transfers may take place in polled or interrupt modes, user-selected. The presence of the iSBX bus allows many different functions to be added to the board. Serial 1/0, parallel 1/0 and various special-purpose math functions are only a few of the c'apabilities available on iSBX MULTIMODULE boards. Equipment Supplied SPECIFICATIONS iSBC 208 Controller Reference Schematic Controller-to-drive cabling and connectors are not supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 208 Hardware Reference Manual Compatibility CPU-Any iSBC MULTIBUS computer or system . main frame Devices-Double or single density standard (8") and mini (51/4") flexible disk drives. The drives may be single or double sided. Drives known to be compatible are: Physical Characteristics Standard (8") 143M Caldisk RFD4000 Remex Memorex 550 MFE 700 Siemens FDD200-8 Shugart SA 850 Pertee FD650 Mini (5V2") Shugart SA Mieropolis Pertee Siemens Tandon Width-6.75 inches (17.15 cm) Height-0.5 inches (1.27 cm) Length-12.0 inches (30.48 cm) Shipping Weight-i. 75 pounds (0_80 Kg) Mounting-Occupies one slot of iSBC system chassis or iSBC 604/614 Cardcage/Backplane. With an iSBX MULTIMODULE board mounted, vertical height increases to 1.13 inches (2.87 cm). 450 SA 400 1015-IV 250 200-5 TM-100 Diskette-Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted IBM Diskette 20 (or equivalent double-sided). Electrical Characteristics Power Requirements- + 5 VDC @ 3.0A 5-10 iSBC 208 Data Organization and Capacity Standard Size Drives Double Density IBM System 34 Single Density Non·IBM IBM System 3740 Non·IBM Bytes per Sector 2§6 512 1024 2048 4096 8192 128 256 512 1024 2048 4096 Sectors per Track 26 15 8 4 2 1 26 15 8 4 2 1 Tracks per Diskette 77 Bytes per Diskette (Formatted, per diskette surface) 512,512 (256 bytes/sector) 591,360 (512 bytes/sector) 630,784 (1024 bytes/sector) Drive Characteristics 77 77 630,784 77 256,256 (128 byte/sector) 295,680 (256 bytes/sector) 315,392 (512 bytes/sector) 315,392 Standard Size Mini Size Double/Single Density Double/Single Density 62.5/31.25 31.25/15.63 Disk Speed (RPM) 360 300 Step Rate Time (Programmable) 1 to 16 msec/track in 1 msec increments 2 to 32 msec/track in 2 msec increments Head Load Time (Programmable) 2 to 254 msec in 2 msec increments 4 t0508 msec in 4 msec increments Head Unload Time (Programmable) 16t0240msec in 16 msec increments 32 to 480 msec in 32 msec increments Transfer Rate (K bytes/sec) Environmental Characteristics Reference Manual Temperature-O°C to 55°C (operating); - 55"C to + 85°C (non·operating) Humidity-Up to 90% Relative Humidity without condensation (operating); all conditions with· out condensation or frost (non·operating) 143078·001-iSBC 208 Flexible Disk Controller Hardware Reference Manual (NOT SUPPLIED). Reference manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051. ORDERING INFORMATION Part Number SBC208 Description Flexible Disk Controller 5·11 inter iSBC 215A1iSBC 215B WINCHESTER DISK CONTROLLER • Intel 8089 1/0 Processor provides DMA channels plus user-programmable intelligence • Controls up to four 8" or 14" Winchester disk drives • Over 100 MB of storage per controller • On-board diagnostics and ECC • Two iSBXconnectors on-board • Full sector buffering on-board • Removable back-up storage available through the iSBX 218 Flexible Disk Controller • iSBC 215A board controls open-loop drives; iSBC215B board controls closed-loop drives • Will provide proposed X3T9_3 ANSI • Capable of addressing 1 MB of system memory standard interface The iSSC215 Winchester Disk Controller will enhance the mass storage capabilities of any iSSC 80, iSSC 88, or iSSC 86-based MULTISUS system. The controller will interface to industry standard 8" Winchester disk drives currently available in formatted capacity from 4.5 to 26.7 MS. Recording densities are expected to increase rapidly in the near future and the iSSC 215 controller has been designed to accommodate these increases. The iSSC 215 board will control up to four 8" 0(14" drives and is designed to conform to the proposed X3T9.3 ANSI standard (currently in the final definition phase). . Two iSSX connectors are provided on the board to interface with the iSSX 218 Flexible Disk Controller, providing upto 4 MS of removable storage. Increased computing power made available in the iSSC board products has led to a requirement for larger, more reliable mass storage subsystems. The Winchester disk controller provides a high capacity, low cost disk solution that is well matched to single boai'd computer applications. 5-12 iSBC 215A/iSBC 215B FUNCTIONAL DESCRIPTION iSBX Interface The software interface and data bufferingcapabilities used for Winchester drives are also available for both iSBX MULTI MODULE interfaces. Software developed for the iSBC 215 controller can also be used to transfer data to and from an iSBXcompatible 1/0 device. Programming Programming the iSBC 215 controller is simplified by the use of memory-based parameter blocks. A linked list technique is used, allowing the user to perform multiple disk operations. Full On-Board Buffer Expanded 110 Capability The iSBC 215 controller contains enough on-board RAM for buffering one full data sector. The controller is designed to make use of this buffer in all transfers. The on-board sector buffer prevents data overrun errors and allows the iSBC 215 Winchester Disk Controller to occupy any priority slot on the MULTIBUS. The iSBC 215 controller allows the user to execute user-written 8089 programs located in on-board or MULTIBUS system RAM. Thus the full capability of the 8089 1/0 processor can be utilized for customer 1/0 requirements. ECC High data integrity is provided by on-board Error Checking Code (ECC) logic. When writing sector 10 or data fields, a 32-bit Fire code, for burst error correction, is appended to the field by the controller. During a Read operation, the same logic regenerates the ECC polynomial and compares. this second polynomial to the appended ECC. The ECC logic can detect an erroneous data burst up to 32 bits in length and using an 8089 algorithm can correct an erroneous burst up to 11 bits in length. 1-----------------------I I I I I I .... I I I I lOP lOP J1 INTERFACE I I LOCAL BU. INTERFACE MULTIBUS I I MUlTIBUS I i I SYSTEM MEMORY 110 COMMUNICA· TIONS BLOCKS I I I I I . I L _________ 1!~~ .!I~~S.!!:~I~~N~O..!:!:~ __________ J ROM Block Diagram of iSBC 215 Winchester Disk Controller 5-13 RAM iSBC. 215A/iSBC.215B J2 J1 Isec 215A CONTROLLER INTERFACE WITH SHUGART/QUANTUM DRIVES INTERFACE WITH MEMOREXISHUGART DRIVES L-_ _~~_""" CONTROL AND .....- - " " " ' - - - - - ' READIWRITE READ/WRITE CONTROL INTERFACE WITH PERTEC AND PRIAM DRIVES Controller to Drive Interfacing 5·14 iSBC 215A/iSBC 215B MULTIBUS Isac 215A121S8 , 8" WINCHESTER DISK CONTROLLER REMOVABLE BACKUP :~-=-.::~==.::--=== _.=--=.::: __ r __ - _ _ _-=:..(°-fPTlNALI i iSBX BUS CONNECTOR I iSBX 218 DOUBLE DENSITY DISKETTE CONTROLLER System Configuration (with Optional Diskette Backup) Controller-to-drive cabling and connectors are not supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 215 Hardware Reference Manual. SPECIFICATIONS Compatibility CPU - Any iSBC MULTIBUS computer or system mainframe Disk Drives - Winchester Disk Drives; both openloop and closed-loop head positioner types_ The following drives are .known to be compatible: Physical Characteristics Width- 6.75 in. (17.15 em) Height - 0.5 in. (1.27 cm) Length - 12.0 in. (30.48 cm) Shipping Weight - 19 oz (54 kg) Mounting - Occupies one slot of iSBC system chassis or eardcage/backplane With an iSBX MUL TIMODULE board mounted, vertical height increases to 1.13 in. (2.87 cm). Open-Loop (iSBC 215A) Shugart SA 1000 Series Shugart SA 4000 Series Memorex 100 Series Quantum Q2000 Series Closed-Loop (iSBC 215B) Pertee 08000 Series Priam 8" and 14" Drive Series iSBX MULTIMODULE Boards Electrical Characteristics iSBX 218 Flexible Disk Controller iSBX 350 Parallel 1/0 iSBX 351 Serial 1/0 iSBX 311 Analog Input iSBX 328 Analog Output Power Requirements + 5 VDC @ 3.25A max -5 VDC @ 0.15A max1 + 12 VDC @ 0.15A max 2 - 12 VDC @ 0.03A max 2 Notes: 1. On·board regulator and jumper allows - 12 VDC usage from MULTIBUS. 2. Required for some iSBX MUL TIMODULE boards. Equipment Supplied iSBC 215 Winchester Disk Controller Reference Schematic 5-15 iSBC 215A/iSBC 2158 Data Organization and Capacity Sectors/Track 1 Bytes/Sector Priam 8" Priam 14" Shugart/Quantum Memorex Pertec 128 256 512 1024 70 42 23 12 104 62 34 18 54 31 17 9 68 39 21 11 73 44 24 13 Nole 1. Maximum allowable for corresponding selection of bytes per seclor. Formatted Capacity/Drive 2 Bytes/Sector Shugart Quantum Pertec Priam Memorex 128 256 512 1024 7.08 MB 8.12 8.91 9.43 7.08 MB 8.12 8.91 9.43 13.05 MB 15.74 17.17 18.60 23.29 MB 27.94 30.62 31.95 8.49 MB 9.74 10.49 10.98 Nole 2. Shugart SA 1004. Ouantum 02010. Priam 3450. Pertec D8000. Memorex 101. Humidity - Up to 90% relative humidity without condensation (operating); all conditions without condensation or frost (non-operating) Drives per Controller 8" Winchester Disk Drives - Up to four Shugart, Pertec, Quantum or Priam drives; up to two Memorex drives. 14" Winchester Disk Drives - Up to four Priam drivers; up to two Shugart drives. Flexible Disk Drives - Up to four drives through the optional iSBX 218 Flexible Disk Controller connected to the iSBC 215 board's iSBX connector. Reference Manual 1215193 - iSBC 215 Winchester Disk Controller Hardware Reference Manual (NOT SUPPLIED) Reference manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051 Environmental Characteristics Temperature - 0° to 55°C (operating); - 55°C to + 85°C (non-operating) ORDERING INFORMATION Part Number Description SBC 215A Winchester Disk Controller (open-loop) Winchester Disk Controller (closed-loop) SBC 215B 5-16 iSBX 218 FLEXIBLE DISK CONTROLLER • iSBX MULTIMODULE controller provides flexibility at low cost • Controls most single and double density diskette drives • User-programmable drive parameters allow wide choice of drives • Phase lock loop data separator assures maximum data integrity • Read, write, verify, and search on single or multiple sectors • Single + 5V supply The Intel iSBX 218 Flexible Disk Controller is a double-wide iSBX board diskette control.ler capable of supporting virtually any soft-sectored, double density or single density diskette drive. The standard controller can control up to four drives with up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats, the controller supports sector lengths of up to 8192 bytes. The iSBX 218 board's wide range of drive compatibility is achieved without compromising performance. The operating characteristics are specified under user program control. The controller can read, write, verify, and search either single or multiple sectors. iSBX 218 FUNCTIONAL DESCRIPTION Interface Characteristics Intel's 8272 Floppy Disk Controller (FDC) chip is the heart of the iSBX 218 Controller. On·board data separation logic performs standard MFM (double density) and FM (single density) encoding and decoding, eliminating the need for external separation circuitry at the drive. Data transfers between the controller and memory are managed by the intelligent device (usually an Intel 8·bit or 16-bit CPU chip) on the host board. A block diagram of the ISBX 218 Controller is shown In Figure 1. The standard iSBX 218 Controller includes an Intel 8272 Floppy Disk Controller chip which supports up to four drives, single or double sided. Universal Drive and iSBX 218 Controller Because the iSBX 218 Controller has universal drive compatibility, it can be used to control virtually any standard- or mini-sized diskette drive. Moreover, the iSBX 218 Controller fully supports the iSBX bus and can be used with any single board computer which furnishes this bus. Because the iSBX 218 Controller is programmable, its performance is not compromised by its universal drive compatibility. The track-to-track access, head-load, and head-unload characteristics of the selected drive model are program specified. Data may be organized in sectors up to 8192 bytes in length. . SIMPLIFIED INTERFACE-The cables between the iSBX 218 Controller and the drive(s) may be low cost, flat ribbon cable with mass termination connectors. The mechanical interface to the board is a right-angle header with loc~ing tabs for security of connection. PROGRAMMING-The powerful 8272 FDC circuit is capable of executing high-level commands that simplify system software development. The device can read, write, and verify both single and multiple sectors. CRC characters are generated and checked automatically. Recording density is selected at each Read and Write to support the industry standard technique of recording basic media information on Track 0 of Side 0 in single density, and then switching to double density (if necessary) for operations on other tracks. SECTOR SCANNING-Scan commands permit sectors to be searched for a specified data pattern or "key." During scan operations the pattern image from memory is continuously compared with a sector or multiple sectors read from the diskette. '5' t ~ RESET RD WR CS AD RESET 10RDI IOWRI MCSOI MAO MOROT MDACKI BUS OPTO MFM MODE yeo READ DATAl CIRCUIT RD DATA PRE·SHIFTD 8272 FDC DACK TC PRE-SHIFT1 CHIP .: PAE·COMP WAITE DATAl we DATA' .. MDO- --------- we PROT 12 SIDED WRITE PROTECT I FAULTITAACKO TWO-SIDEDI FAULTI TRACK 01 FL T RESET/STEP DATAI-7 MD' .. DATA RECOVERY SYNC INT ORO MINTR1 Isax DATA WINDOW LOW CURRENT/DIR MUX STEP} lOW CURRENTI DIRECTION BUHz OSC FLT RESETI RiWfSEEK • READYI WRITE ENABLEI INDEXI HEAD LOADI 1 WAITE SIDE SELECT CLOCK OEN ~ US. US, J, ~ MUX Figure 1. Block Diagram of iSBX 218 Board 5-18 ~ ~ FLEXIBLE DISK DRIVE iSBX 218 require a data transfer every 13 microseconds (double density) or 26 microseconds (single density). Most CPUs will operate in a polled mode, checking controller status and transferring bytes when the controller is ready. Boards utilizing the Intel 8080 chip, such as the iSBC 80/10B board, will be restricted to single density operation with the ISBX 218 Controller, due to these speed requirements. A programming example illustrating the iSBC 80/10B handler Is contained in the Hardware Reference Manual. PROGRAM INITIATION-All diskette operations are initiated by standard iSBX bus input/output (\/0) operations through the host iSBC single board computer. System software first initializes the controller with the operating characteristics of the selected drive. The diskette is then formatted under program control. Data transfers occur In response to commands output by the CPU. DATA TRANSFER-Once a diskette transfer operation has been initiated, the controller will SPECIFICATIONS Diskette-Unformatted IBM Diskette 1 (or equivalent single~sided media); unformatted IBM Diskette 2D (or equivalent double-sided). Compatibility CPU-Any iSBC single board computer or I/O board compatible with the MULTIBUS system bus and implementing the iSBX bus and connector. Devices-Double or single density standard (8") and mini (5V4") flexible disk drives. The drives may be single or double sided. Drives known to be compatible are: Equipment Supplied iSBX 218 Controller Reference Schematic Controller-to-drive cabling and connectors are not supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described In the iSBX 218 Hardware Reference Manual. Nylon Mounting Bolts Physical Characteristics Standard (8") Caldisk Remex Memorex MFE Siemens Shugart Pertec Mini (5V2 ") 143M RFD4000 550 700 FDD 200·8 SA 850 FD650 Width-2.85 inches (7.24 cm) Height-0.5 Inches (1.27 cm) Length-7~5 inches (19.05 cm) Shipping Weight-1 pound (0.46 Kg) Mounting-Occupies one double-wide iSBX MULTIMODULE position on boards; increases board height (host plus iSBX board) to 1.13 inches (2.87 cm). 450 Shugart Data Organization and Capacity Standard Size Drives Double Density IBM System 34 Single Density Non-IBM IBM System 3740 Non-IBM Bytes per Sector 256 512 1024 2048 4096 8192 128 256 512 1024 2048 4096 Sectors per Track 26 15 8 4 2 1 26 15 8 4 2 1 Tracks per Diskette 77 Bytes per Diskette (Formatted, per diskette surface) 512,512 (256 bytes/sector) 591,360 (512 bytes/sector) 630,784 (1024 bytes/sector) 77 630,784 5-19 77 256,256 (128 byte/sector) 295,680 (256 bytes/sector) 315,392 (512 bytes/sector) 77 315,392 iSBX 218 Drive Characteristics Standard Size Mini Size Double/Single Density Double/Single Density 62.5/31.25 31.25/15.63 Disk Speed (RPM) 360 300 Step Rate Time (Programmable) 1 t016 msec/track in 1 msec increments 2 to 32 msec/track in 2 msec increments Head Load Time (Programmable) 2 to 256 msec in 2 msec increments 4 to 512 msec in 4 msec increments Head Unload Time (Programmable) oto 240 msec in 16 msec increments oto 480 msec in 32 msec increments Transfer Rate (K bytes/sec) Electrical Characteristic·s Power Requirements- + 5 VDC Reference Manual @ 0.81 A 121S83·001-iSBX 218 Flexible Disk Controller Hardware Reference Manual (NOT SUPPLIED). Environmental Characteristics Temperature'-:O°C to 55°C (operating); - 55°C to + 85°C (non·operating). Humidity~Up to 90% Relative Humidity without condensation (operating); all conditions without condensation or frost (non-operati ng). Reference manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051. ORDERING INFORMATION Part Number SBX 218 Description Flexible Disk Controller 5-20 iSBC 220 SMD DISK CONTROLLER • Controls up to four SMD interface . compatible disk drives • 12 MB to 2.4 GB per controller • On·board diagnostic and ECC • Full sector buffering on·board • Compatible with all iSBC 80, iSBC 88, and iSBC 86 Single Board Computers • Capable of addressing 1 MB of system memory • Intel 8089 1/0 Processor provides two high speed DMA channe.ls as well as controller intelligence • SMDinterface available on 14" Winchester, CMD,SMD and large fixed, media drives The iSBC 220 SMD Disk Controller brings very large mass storage capabilities to any iSBC 80, iSBC 88, or iSBC 86 MULTIBUS system. The controller will interfaceto any disk drive conforming to the industry standard SMD interface. Using simplified cable connections, up to four drives may be connected to the iSBC 220 Controller Board to give a total maximum capacity of 2.4 gigabytes. The Intel 8089 I/O Processor simplifies programming through the use of memory-based parameter blocks. A linked list technique allows the user to perform multiple disk operations. iSBC 220 to 32 bits in length and using an 8089 alrogithm can correct an erroneous burst up to 11 bits in length. FUNCTIONAL DESCRIPTION Full On-Board Buffer The iSBC 220 SMD Controller contains enough onboard RAM for one full sector buffering_ The controller is designed to make use of this buffer in all transfers. The on-board sector buffer prevents data overrun errors and allows the iSBC 220 SMD Controller to occupy any priority slot on the MULTIBUS. SMD Interface High speed, reliable data transfers are a major benefit of using the SMD interface. A data transfer rate of 1.2 MB is accomplished by using separate (radial) differential data line cabling for each drive. Control signals are daisy-chained from drive to drive. ECC Defective Track Handling High data integrity is provided by on-board Error Checking Code (ECG) logic. When writing sector ID or data fields, a 32-bit Fire code, for burst error correction, is appended to the field by the controller. During a Read operation, the same logic regenerates the ECC polynomial and compares this second polynomial to the appended ECC. The ECC logic can detect an erroneous data burst up When a track is deemed defective, the host processor reformats the track, giving it a defective track code and enters the address of the next available alternate track. When the controller accesses a track previously marked defective, the controller automatically seeks to the assigned alternate track. The alternate track seek is totally automatic and invisible to the user. r-------------------------l I I I I I I I I I 8089 lOP I I I lOP MULTI BUS INTERFACE LOCAL BUS INTERFACE I I SYSTEM MEMORY 110 COMMUNICA· TIONS BLOCKS I I I I L ___________is.!.cE~M~~~~L~~A~ _ _ _ _ _ _ _ _ _ _ _'J Simplified Block Diagram of iSBC 22 SMD Disk Controller. 5-22 iSBC 220 TERMINATOR DRIVE 0 DRIVE 3 DRIVE 2 DRIVEl READ/WRITE CABLE CONTROL CABLE ,------ --I I ~"""'--::-;:":;"""", I I I I I I P2 (NOT USEDI I L ________ _ I I I I MULTIBUS Typical Multiple Drive System SPECIFICATIONS Electrical Characteristics Power Requirements + 5 VDC @ 3.25A max -5 VDC @ 0.75A max 1 Compatibility CPU - Any iSSC MUL TISUS computer or system mainframe Disk Drive - Any SMD interface-compatible disk drive Note 1: On·board voltage regulator allows optional - 12 VDC usage from MULTIBUS. Equipment Supplied Data Organization and Capacity iSSC 220 SMD Disk Controller Reference schematic Bytes per Sector2 - 128 256 521 1024 Sectors per Track2 - 108 64 35 18 Note 2: Software selectable. Controller-to-drive cabling and connectors are not supplied with the controller. Cables can be fabri'cated with flat c~ble and commercially-available connectors as described in the iSSC 220 SMD Disk Controller Hardware Reference Manual. Table 1. Drive Characteristics (Typical) Physical Characteristics Width - 6.75 in. (17.15 cm) Height - 0.5 in. (1.27 cm) Length - 12.0 in. (30.48 cm) Shipping Weight - 19 oz (0.54 kg) Mounting - Occupies one slot of iSSC system chassis or cardcage/backplane 5-23 Disk (spindle) Speed 3600 rpm Tracks per Surface 823 Head Positioning Closed loop servo type, track following Access Time Track to Track Average Maximum Data Transfer Rate 1.2 megabytes/second Storage Capacity 12 to 2.4 gigabytes 6 ms 30 ms 55 ms iSBC 220 Environmental Characteristics Reference Manual Temperature - O°C to 55°C (operating); - 55°C to iSBC 220 SMD Disk Controller Hardware Reference Manual (NOT SUPPLIED) + 85°C (non-operating) Up to 90% relative humidity without condensation (operating); all conditions without condensation or frost (non-operating) Humidity - ORDERING INFORMATION Part Number Description SBC 220 SMD Disk Controller 12159 - Re'ference manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051. Memory Expansion Boards 6 uSBC 016 16K·BVllE RAM MEMORY BOARD II!l iSBC 80 RAM memory expansion through the MUlTIBUS interface • Jumper selectable starting address for 16K contiguous addresses 51 16K-byte read/write memory capacity • Read/write data buffers !ill On-board hardware regresh for all dynamic memory elements • TTl compatible data, address, and command signal interface The iSBC 016 16K-Byte RAM Memory Board is a member of Intel's complete line of iSBC memory and I/O expansion boards. The iSBC 016 interfaces directly to any iSBC 80 single board computer via the system bus to expand RAM memory capacity. The board contains 16K bytes of read/write memory, implemented using 2107 dynamic RAM memory components. On-board refresh hardware refreshes 64 bit positions of all 32 RAM elements every 14 microseconds. Each refresh cycle utilizes memory for 735 nanoseconds. If a read or write cycle is in progress when a refresh cycle is scheduled to begin, the refresh cycle is postponed until the end of the cycle. The iSBC 016 contains a jumper used to select contiguous 16K-byte address segments starting in locations 0000, 4000, 8000, or COOO. Read/Write buffers reside on the board to buffer all data written into or read from the memory array. All data, address, and command signals on the bus interface are TTL compatible. 6-1 iSBC 016 MEMORY ARRAY 16K! 8 ¢ ::==j::======~==========================~=====A~DD~RE~SS~B~US===== I DATA BUS CONTROL BUS :~i~~~~E Figure 1. iSBC 016 16K RAM Memory Expansion Board Block Diagram SPECIFICATIONS Physical Characteristics Word Size Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 1202 (415. 2 gm) 8 bits Memory Size 16,384 bytes Electrical Characteristics DC Power Requirements Vee = +5V DC ±5% Icc = 1.2A typ; 1.5A max Voo = +12VDC ±5% 100 = 0.7A typ; 1.0A max V BB -5V DC ±5% IBB = 0.2 mA typ; 3.2 mA max Cycle Times Read Cycle - 735 ns max Write Cycle - 1360 ns max Refresh Cycle - 735 ns max = Interface All address, data, and command signals are TTL compatible. Environmental Characteristics Operating Temperature - Address Selection Jumper selection of base address of 16K contiguous memory block to reside in locations 0000, 4000, 8000, or COOO. Reference Manual 9800279A - iSBC 016 Hardware Reference Manual (NOT SUPPLIED) Connectors Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Depart· ment, 3065 Bowers Avenue, Santa Clara, California 95051. Edge Connector -86·pin double-sided PC edge con· nector with 0.156-in. contact centers. Mating Connector - Viking 3KH43/9AMK12 ORDERING INFORMATION Part Number Description SBC 016 16K-Byte RAM Memory Board O°C to 55°C 6·2 iSBC 032/048/064 RAM MEMORY BOARDS • iSBC 80 and iSBC 86 RAM memory expansion through direct MULTIBUS interface • Auxiliary power bus and memory protect control logic provided for battery backup RAM requirements • 32K, 48K, 64K bytes of read/write memory (iSBC 032, iSBC 048, iSBC 064 boards, respectively) • Jumper selectable starting address for independent 16K·byte memory segments • On·board hardware for refresh ola" dynamic memory elements • TTL compatible data, address, and command signal interface • Read/write data buffers The iSBC 032, iSBC 048, and iSBC 064 RAM Memory Boards are members of Intel's complete line of iSBC memory and I/O expansion boards. Each board interfaces directly to any Intel iSBC 80 or iSBC 86 single board computer via the MULTIBUS interface to expand RAM memory capacity. The iSBC 032 contains 32K, the iSBC 048, 48K, and the iSBC 064, 64K bytes of read/write memory implemented using dynamic RAM memory components. On·board refresh hiHd· ware refreshes a portion of RAM memory every 14 microseconds. Each refresh cycle utilizes memory for 585 nano· seconds. If a read or write cycle is in progress when a refresh cycle is scheduled to begin, the refresh cycle is post· poned until the end of the cycle. The iSBC 032 contains jumpers used to individually select two independent 16·byte memory segments, and the iSBC 048 contains jumpers used to individually select three independent 16K·byte memory segments starting on 16K·byte boundaries in one of sixteen 64K·byte pages. Read/write buffers reside on each board to buffer all data written into or read from the memory array. All data, address, and command signals on the bus inter· face are TTL compatible. 6·3 iSBC 0321048/064 - READ/ WRITE ADDRESS BLOCK SELECT DATA BUFFERS JUMPERS 2,3,OR4 MEMORY ARRAYS (16K x 8 EACH) CONTROL (BUS HANDSHAKE & REFRESH LOGIC) ADDRESS ADDRESS DeCODe ADDRESS BUS DATA BUS CONTROL BUS }i \ MULTIBUS L-j'NTERFACE Figure 1. RAM Memory Expansion Boerds Block Diagram SPECIFICATIONS Memory Protect An active·low TTL compatible memory protect signal is brought out on the auxiliary connector which, when asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system power·down sequences. Word Size 8 bits and 16 bits Memory Size 32,768 bytes (iSBC 032), 49,152 bytes (iSBC 048), 65,536 bytes (iSBC 064) Physical Characteristics Access Time Width - 12.00 in. (30.48 cm) Height - 6.76 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 14 oz (415.2 gm) 450 ns max Cycle Times " Electrical Characteristics Read Cycle - 700 ns max Write Cycle - 600/1240 ns max Refresh Cycle ....,. 700 ns max DC Power Requirements Voltage Interface vee= +5V ±5% All address, data, and command signals TTL compati· ble. Voo= +,12V ± 5% VBS = -5V ±5% Normal System Operation (max)' Icc=3,2A 100=600 rnA leB= 10 rnA AUX Power RAM Access (max)2 AUX Power No RAM Access (max) 1,7A 600 rnA 10mA 1.7,11 120 rnA 3 rnA Address Selection Notes Jumper selection for independent 16K·byte, memory blocks starting on 16K·byte boundaries in one of sixteen 64K·byte pages. ' 1. All current values apply to the iSBC 032, iSBC 048 or ISBC064 boards and include AUX power. 2. RAM chips and RAM control logic powered via auxiliary,power bus. 3. Power necessary ~o refresh RAMs and maintain data, as after system power f a i l u r e . ' . , Connectors Environmental Characteristics + 55 'C Edge Connectors - 86-pin double·sided PC edge con· nector with 0.156-in. contact centers: Mating Connector - Operating Temperature - 0 'C to Reference Manual Viking 3KH43/9AMK12 9800488B - iSBC 032/048/064 Hardware Reference Manual (NOT SUPPLIED) Auxiliary Power An auxiliary power, bus is' provided to allciw separate power to RAM for syst'ems requiring battery back up of read/write memory. ,Selection of this auxiliary RAM power bus is made' via jumpers on the board. Manuals may be ordered from'any Intel sales represe!)· tative, distributor office or from Intel Literature Depart· men't, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number Description SBC 032 SBC 048 SBe 064 32K'Byte RAM Board 48K·Byte RAM Board 64K·Byte RAM Board 6·4 iSBC 090™ MEMORY SYSTEM • 128K, 256K, 384K, 512K, 768K or 1024 K·byte Capacities • Error Correcting Circuitry (ECC) Provides Single Bit Correction and Double Bit Detection Error Logger and Display Isolates • Single Bit Errors to the Memory Device Level Selectable Starting Address • Switch on any 4K Byte Boundary • Field Expandability • 8·Bit or 16·Bit Word Transfer The Intel® iSBC 090 Memory System is a random·access dynamic memory system to be used with Intel's MULTIBUS™ System and iSBC 80/86™ product line. The iSBC 090 Memory System can provide up to 1 Megabyte of memory in 256K·byte increments or up to 512K·bytes in 128K·byte increments. It consists of a MULTIBUS Interface Board and a Series 90 Random Access Dynamic Memory. The Interface Board plugs directly into the MULTIBUS backplane, and through four ten·foot cables interfaces the MULTIBUS system and the memory. The Interface Board is a 12.0 inch. by 6.75 inch printed circuit board that occupies anyone slot in the MULTI BUS backplane. It allows the user to select the beginning and ending addresses to which the iSBC 090 Memory System will respond; it permits either 8·bit or 16·bit bus masters, or mixes of both, as well as supporting the normal read, write, refresh, and inhibit RAM cycles of the MULTI BUS system. Operating power for the interface is supplied by the MULTIBUS chassis and is not affected by increases in memory capacity. The memory is a self·contained unit measuring 5.21 inches by 19.00 inches by 19.5 inches. It includes a memory storage area, which provides up to 1 Megabyte of memory. In addition, its control interface provides sjngle·bit error detection and correction, double:bit error detection, and refresh arbitration. The memory also includes an error logger and error display, as well as its own power supplies and blower assembly. It is available as a rack mount system or a table top system with either 115 or 220 VAC input power. The fOllowing are trademarks of Inlel Corporation and may be used only to describe Intel products: Index, Intel, InSile, Intellec. Library Manager, Megachassis, Micromap, MULTIBUS. PROMPT, RMX, UPI, J.lScope, Promware, MeS, ICE, ISeC, ISeX, MULTIMODULE and ICS, and the combination of MeS, RMX, ICE, iSSe, iSeX or ieS and a numerical suffix. Intel Corporation assumes no responsibility for the use of any Circuitry other than Circuitry embodied In an Intel product. No other circuit patent licenses are Implied. © INTELCORPORATION,1980 Jun~i~;:~ 6.5 iSBC 090™ Interface Board. The switches allow the memory to be any size, ranging from 4K-bytes to one megabyte,'starting and ending on any 4K boundary. FUNCTIONAL DESCRIPTION The memory portion of the iSBC 090 Memory System (Figure 1) provides the memory storage area and the error detection and correction functions for the system. Error Logger and Display The MULTIBUS Interface Board provides address compatibility between the MULTIBUS system and the memory; supports the four types of data transfer across the MULTIBUS interface; and generates the required control and status signals. Interface Board address circuits permit ,the iSBC 090 System to fit any. addres~ space from 4K-bytes to one megabyte, starting at any 4K boundary. The Error Logger is a random-access memory which stores (logs) ECC syndrome bits that identify the failing bit and its location. The logger memory can store a maximum of 4096 single and double-bit errors. A display panel shows error information for user reference.' The error logger operates in three modes: log (write), scan (read), and clear. In normal system operation, the logger is operated in log mode and accessed only when one or more of the syndrome bits go active, indicating an error condition. The syndrome pattern identifying the error and the address of the error location are stored in the logger memory. The Error Logger and Display records error, syndrome, and status Signals, then on request displays them for quick location of memory errors. Capacity To look at the stored error information; the logger is placed in scan mode, taking it off-line. The logger memory is sequentially scanned until error information is reached. Scanning stops and the memory card identification, the card JOW, the data byte and the data bit are displayed on the logger display panel. The scan can be resumed using a scan control button. The' iSBC 090 Memory System provides up to one megabyte of memory in 256K increments, or up to 512K-bytes in 128K increments. Each 128K-byte or 256K-byte incre, ment is provided by adding one memory module in the memory. Five standard system cap'acities are offered: 128K, 256K,384K, 512K, 768K and 1024K-bytes. The 128K system can be expanded to 512K in 128K increments; the 256K and larger systems to 1024K-bytes in 256K-byte increments. INSTALLATION The MULTIBUS Interface Board plugs directly into the MULTIBUS backplane. All operating power is furnished through the MULTIBUS connectors. Interface to the memory portion of the iSBC 090 Memory System is made using four 50-pin flat-ribbon cables, supplied with the System. Addressability The address space which the iSBC 090 Memory System will occupy in the MULTIBUS addressing scheme is, determined by two eight-position DIP switches on the MULTIBUSTII INTERFACE ,BOARD Figure 1. iSBC 090™ Memory System; Block Diagram 6-6 iSBC 090™ The iSBC 090 is available as a 19·inch rack·mounted unit with slide attachments or as a table top configuration with side covers instead of slides. Depending on the configuration selected, the memory is connected to either 115 VAC, 50/60 Hz, single·phase, or 220 VAC, 50/60 Hz, single·phase power. SPECIFICATIONS Logic Levels Output Storage Capacity Logic High - +2.5V to +5.25V at 0.1 mA Logic Low - O.OV to +0.5V at 16.0 mA 128K, 256K, 384K, 512K, 768K, 1024K bytes Physical Characteristics Word Length iSBC Interface Board 8/16 bits plus 6 bits for ECC Height Width Thickness Weight Operating Cycles Read Cycle Write Cycle Inhibit RAM Cycle Refresh Cycle - 6.75 in. (17.15 cm) 12.0 in. (30.48 cm) 0.5 in. (1.27 cm) 3 Ibs. (1.4 Kg) (with interface cables) Series 90 Memory System Height Width Depth Weight Mounting Read Access Time (8- or 16·8it Transfer) 450 nsec max (MRDC* to XACK*) - 5.21 in. (13.2 cm) 19.0 in. (48.25 cm) 19.5 in. (49.53 cm) 30 Ibs. (13.5 Kg) max. 19-inch rack/table top (optional) Electrical Characteristics Write Access Time MULTI BUS Interface Board 8·Bit Transfer - 485 nsec max (MWTC* to XACK*) 16·Bit Transfer - 150 nsec max (MWTC* to XACK*) +5V±6.0% 2 Amps typical 3 Amps worst case * MWTC = Memory Write Command XACK = Transfer Acknowledge MRDC= Memory Read Command Series 90 Memory System 115 VAC, 50/60 Hz, 2.8A 220 VAC, 50/60 Hz, 1.6A (Reference MULTIBUS Manual 9800683) Read Cycle Time (8· or 16·8it Transfer) Environmental Requirements 485 nsec max Ambient Operating Temperature - O°C to 50°C Relative Humidity - 10 to 90% without condensation Write Cycle Time REFERENCE MANUAL 8-Bit Transfer - 700 nsec max 16·Bit Transfer - 400 nsec max The iSBC 090 Memory System is supported by a full line of documentation, as listed below: Refresh Cycle Time (8· or 16·8it Transfer) Logic Levels Input 111710, Technical Manual for iSBC 090™ Memory System 111784, Technical Manual for Series 90 Random Access Memory Systems with CI-9000 Control Interface Logic High - +2.0V to 5.25V Logic Low - - 0.5V to ± 0.80V 111764, Technical Manual for Series 90, CM-90 Dynamic Memory Module 450 nsec max 6-7 iSBC 090™ ORDERING INFORMATION Model Number Description SBC-090-x*3F 128K Byte Multibus-compatible dynamic RAM memory system with ECC. Expandable to 512K Bytes using CM-90200-F22 memory module (below). NOTE: "x" in model no. must be specified per table below to define input voltage and chassis configuration. SBC-090-x*1H 256K Byte Multibus-compatible dynamic RAM memory system with ECC. Expandable to 1024K Bytes using CM-90100-H22 memory module (below). NOTE: "x" in model no. must be specified per table below to define input voltage and chassis config uration. SBC-090-x*3H 256K Byte memory system. Otherwise identical to above SBC-090-x*3F. SBC-090-x* 1K 512K Byte memory system. Otherwise identical to above SBC·090-x* 1H. SBC-090-x *3J 384K Byte memory system. Otherwise identical to above SBC-090-x*3F. SBC-090-x*1 L 768K Byte memory system. Otherwise identical to above SBC-090·x*1 H. SBC-090-x*3K 512K Byte memory system. Not expandable. Otherwis!l identical to above SBC-090-x*3F. SBC-090-x* 1M 1024K Byte memory system. Not expandable. Otherwise identical to above SBC-090-x*1 H. CM-90200-F22 128K Byte memory module for expansion of SBC·090-x*3F, H, or J. CM-90100-H22 256K Byte memory module for expansion of SBC-090-x*1 H, K, or L. NOTE To order SBC 090, the "x" in model no. must be specified per the following table to define input voltage and chassis configuration. x=o for x = 1 for X= 2 for x = 3 for 6-8 rack mount unit, 110 VAC rack mount unit, 220 VAC table-top unit, 110 VAC table-top unit, 220 VAC iSBC 094 4K·BYTE CMOS RAM MEMORY BATTIERY BACKUP BOARD I!i:I iSBC 80 and iSBC 86 nonvolatile RAM memory expansion through the MULllBUS [] Base address selectable to start on any 41( memory address boundary c 4K bytes of low power static CMOS RAM memory o On· board rechargeable batteries and charging circuitry for S6·hour data retention • On·board power·fail interface logic [l Single + 5V power requirement The iSBC 094 4K-Byte CMOS RAM Memory/Battery Backup Board is a member of Intel's complete Iine of iSBC memory and I/O expansion boards. The ISBC 094 interfaces directly to iSBC single board computer via the system bus to expand RAM memory capacity. The board contains 4K bytes of read/write memory, implemented using 32 Intel 5101 CMOS RAM memory components. an-board rechargeable batteries and charging circuitry insure that data contained In RAM will be retained for at least 96 hours after system bus power (+ 5V) is removed. Critical system parameters stored in the ISBC 094 RAM will thus be saved during temporary system powerf!illures. Full power-fail interface logic is provided on the board to generate a CPU Interrupt when system power fails. Orderly system shutdown procedures may then be executed and critical system parameters may be retrieved and stored. The use of CMOS RAM on the iSBC 094 also reduces power dissipation during normal system operation. The iSBC 094 contains jumpers for use in selectIng a contiguous 4K-byte address segment beginning on any 4K memory address boundary (OOOOH, 1000H, 2000H, etc.). Read/write buffers reside on the board to buffer all data written into or read from the memory array. All address, data, and command signals on the bus Interface are TTL compatible. 6-9 iSBC 094 BATTERIES MEMORY ~ ON-BOARD BATTERY CHARGER I- +5V ., ARRAY 4K X 8 RAM SELECT ADDRESS ADDRESS BLOCK SELECT JUMPERS DECODE t ! '------ POWER-FAIL INTERRUPT LOGIC ACLOW (FROM I - POWER SUPPLY) i\ Y ADDRESS BUS I DATA BUS CONTROL BUS MULTIBUS I NTERFACE Figure 1. iSBC 094 Memory Backup Board Block Diagram vided for the protection of RAM contents during system power·down sequences. This signal is automatically asserted by the power·fail interface logic 3.6 ms after the AC low signal is received from the system power supply to signify that system power is beginning to fail. SPECIFICATIONS Word Size 8 bits and 16 bits Memory Size Address Selection 4096 bytes 4K segments starting at any jumper selectable base ad· dress on a 4K·byte boundary (e.g., OOOOH, 1000H, ... FOOO H). The memory will appear in every 64K·byte memo ory page. Memory Response Time Operation Access (ns, max) Cycle (ns, max) Read 750 900 Write - 900 Mating Connectors Pins (qty) Centers (In.) Mating Connectors Bus' 86 0.156 Viking 3KH43/9AM K12 Auxiliary' 60 0.1 AMP PE5·14559 or TI H311130 Intorfaco Interface All address, data, and command signals are TTL com· patible. Note 1. Connector Dimensions vary from vendor to vendor. Review vendor specifications to ensure that connector heights and wire-wrap pin lengths to conform to your system packaging requirements. Power Fail Interrupt Control logic is also included for generation of a power· fail interrupt to the MULTIBUS interface, which works in conjunction with the AC low signal from the Intel iSBC 635 Power Supply or equivalent. Data Retention 96 hours minimum aiter + 5V bus power is removed. Battery Characteristics Memory Protect Type - Nickel·Cadmium, rechargeable Capacity - 150 mA hr Voltage - 3.6V nominal An on·board memory protect signal disables read/write access to RAM memory on the board. This input is pro- 6·10 is Be 094 Battery Charger Characteristics Environmental Characteristics Charge Time 14 hours for full charge (150 rnA hr) Full overcharge protection Full short·circuit protection Operating Temperature - O·C to 55·C Physical Characteristics Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cni) Depth - 0.60 in. (1.27 cm) Weight - 12 OZ (340.5 gm) Reference Manual 98004498 - iSBC 094 Hardware Reference Manual (NOT SUPPLIED) Electrical Characteristics Manuals may be ordered from any Intel sales represen· tative, distributor office or from Intel Literature Depart· ment, 3065 Bowers Avenue, Santa Clara, California 95051. Average DC Current Vee = +5VDC±5% lec=0.8A typ, 1.7A max ORDERING INFORMATION Part Number Description SBC 094 4K·Byte CMOS RAM Memory Battery Backup Board 6·11 inter iSBC 250™ 1 Megabit Bubble Memory Board • Completely Assembled 1 Megabit Bubble Memory System • Average Access time 48 ms • Automatic Error Correction • Direct MULTIBUS™ Interface • Power Fail Circuit Protects Bubble Memory and Stored Data • Fully Compatible with iSBC-80™ and iSBC-86™ Single Board Computers • Standard 6,75 x 12-inch SBC Printed Circuit Board • Non-Volatile Solid-State Memory The iSBC 250 is a completely assembled 128K byte non-volatile memory utilizing the Intel Magnetics 7110 one megabit bubble memory, 7230 current pulse generator, 7242 dual formatter/sense amplifier, and 7250.and 7254 coil drivers. Designed for interface with MULTIBUS systems, the iSBC 250 can be plugged into Intellec® Microcomputer Development Systems. Software provided on single- and double-density diskettes enables the user to perform maintenance fu nctions or to perform reliability evaluation. Source code in 8080 Assembler Language for sample driver routine is supplied on each diskette. Error correction and power fail protection capabilities enable the iSBC 250 to be used in OEM systems as well as in development applications. 6-12 inter iSBC250™ written into the 7242 during system initialization. The 7242 uses the bootloop map to gate the data to insure that bad loops are not written into and that data from these loops are not read out. iSBC 250™ FUNCTIONS The iSBC 2S0 megabit Bubble Memory Board consists of a one megabit bubble memory cell and a bubble memory controller based on integrated circuits. SOFTWARE A set of object programs for exercising and maintaining the iSBC 2S0 is supplied on diskettes. These programs can be used on any Intellec® Microcomputer Development System with ISIS-II ... The controller for the iSBC board is made up of an BOBSA microprocessor, PROMs and EPROMs .. The BOBSA communicates with the host CPU through a set of registers on the board via I/O commands. By interpreting these registers, the BOBSA microprocessor controls timing and analog circuits to access the bubble memory. Data are passed via a FIFO on the board. An on-board clock generator (a crystalcontrolled oscillator and driver) allows the board to function independently of the host CPU clock. The programs are: 1. MASK-To create a bad loop map in a format suitable for writing to a bubble memory chip. 2. UNMASK-To determine the correspondence between a given bit in an input/output buffer and the physical minor loop, given a bad loop .map. The iSBC 2S0 board is address-decoded by an B20S decoder. The controller address is selected by a jumper option. Normal jumper configurations provide compatibility with MULTIBUS structures. The host addressable registers are a 16 x B RAM, and the addresses are controlled either by the host bus or the BOBSA microprocessor. 3. VERIFY-To write bubble memory bootloop. 4. BUBBLE-To transfer data between bubble, RAM or other devices in the system. S. SEED-To regenerate seeds on the bubble. 6. TEST-To check the operation of the board. It enables the user to perform device evaluations by writing data in the 7110, reading the stored data and indicating errors. The bubble memory cell operates as follows: The 72S0 coil predriver translates SV signals to 12V, to drive the 72S4 quad transistor packs. These transistors in turn, drive the X and Y coils at the 7110 bubble memory. In addition, a stand alone monitor is provided in sou rce code form. It aliolNs the user to execute a set of commands, such as, INITIALIZE, READ, WRITE, ABORT AND SEEK for the purpose of demonstrating the functions of the iSBC 2S0 in a Single Board Computer or an Intellec® Microcomputer Development System environment. The 7230 cu rrent pu Ise generator provides pu Ises to the 7110 bubble memory and serves as a voltage supply monitor. The 7230 device issues a POWERFAIL signal if either +SV or +12V power falls below a preset safe operating threshold value. Since the monitor software is in source code form, it may be modified by the user to reside on any SBC processor board or may be used as a model for the user's OEM application software. The 7242 dual formatter/sense amplifier communicates with the BOBSA-based controller, the 7230 current pulse generator and the711 0 bubble memory. The 7242 formatter also provides internal errOr correction by means of a 14-bit Fire code. This code can correct burst errors up to S bits in length, in each .page. This error correction system significantly improves the· read error rate. A zero-suppression and filter system is also incorporated between the· 7242 inputs and the 7110 detector outputs to further minimize errors. SYSTEM PROGRAMMING The iSBC 2S0 appears as a peripheral device to the processor. The processor communicates with the iSBC 2S0 through two ports. The command, address and status information through one of the ports, and data is passed in the second port. Data is organized as 204Blogical pages with 64 bytes per page. Bubble addressing is done by page number. The board includes circuits to recreate seed bu.bbles in the 711 0 bubble memory as needed. The iSBC 2S0 is designed to utilize the transparent redundancy inherent in the 7110 magnetic bubble memory de~· vice. The bootioop map information of the 7110 is Data istrEmsferred in byte mode. Interrupt can be set on completion of command or on encountering error conditions. 6-13 AFN·Ol438A iSBC250™ SPECIFICATIONS Connector Memory Size Mating Connector: Control Data VPB01 E43DOOA 1 or Viking 2VH43/1AV5. 86-pin double-sided PC edge connector with 0.40 cm (0.156 inch) contact centers. 128K bytes. Interface All address, data and control signals are Intel MULTIBUS. compatible. Electrical Characteristics D.C. +5 +12 -12 Power (Max) Volts D.C. ±5%, 3.0A Max. Volts D.C. ±5%, 0.5A Max. Volts D.C. ±5%, 0.1A Max. Physical Characteristics Length: Height: Depth: Weight: 30.48 cm (12 inches) 17.15 cin (6.75 inches) 1.45 cm (0.57 inch) 447g (16 ounces) Environment Operating Temperatlire: 'O-50·C for iSBC-250 10-50·C for iSBC-250-2 Performance Equipment Supplied Rotating Rate Field: 50kHz Maximum Data Rate: 100K bits/sec Nominal Data Rate: Read 35K bits/sec, Write 41 K bits/sec Average Access Time: 48 ms iSBC 250 Bubble Memory Board iSBC 250 Operation Manual iSBC 250 Software (single and double density diskettes). Error Rates Typical Without Correction Calculated With Correction Read 10-' Data 10- 11 10- 1• 10-20 SYSCK X, eLK OUT I-t+lf----+.rl ADO-AD7 CONTROL BOSSA Figure 1. Block Diagram AFN·01438A " iSBC 254™ BUBBLE MEMORY BOARD • Non-Volatile Storage • 128K Byte to 512K Byte Capacity on Single iSBC™ Board • Multiple I/O Modes, Including DMA • 48MS Average Access Time • Driver Software for Operation with RMX 80/86 • Low Power Consumption 35 Watts for 512 KB Version The iSBC 254™ is a non-volatile memory utilizing the Intel 7110 one-megabit bubble memory element. The board is offered in three capacities: 128K, 256K, or 512K bytes. The iSBC 254 can be operatedin three I/O modes: polled status, interrupt-driven, or DMA. The 128K byte version can operate at a maximum transfer rate of 12.5K bytes per second. The multiple bubble elements of the 256K byte and 512K byte versions can be accessed in parallel to achieve maximum transfer rates of 25K and 50K bytes per second, respectively. The physical outline of the iSBC 254 is the standard 12 inch by 6.75 inch iSBC card format. The depth of the board, however, is 0.62 inches, requiring two normally spaced card slots for adequate mechanical clearance. Power requirements for the iSBC 254 are 4 Amps at +5 volts and 1.2 Amps at + 12 volts, maximum. 6-15 inter iSBC 416 16K EPROM EXPANSION BOARD • Allows iSBC 80 EPROM/ROM expansion through the MULTIBUS interface • Switches enable or disable each memory block • Jumper selectable addresses for each 8K block • Sockets for up to 16K bytes of Intel 2708 programmable and erasable . PROM • Buffered address and data lines The iSBC 416 16K EPROM Expanslqn Board Is a member of Intel's complete line of iSBC memory and I/O expansion boards. The iSBC 416 interfaces directly to any ISBC 80 single board computer via the system bus to expand EPROM memory capacity. The board contains 16 sockets that can house Intel 2708 programmable and erasable EPROMs. EPROM memory can be added in 1K-byte increments. The ISBC 416 contains a set of jumpers allowing the selection of the base address of Independent 8K memory blocks, to begin on any 8K boundary. Switches are used to enable onboard memory in 1K block Increments. 6-16 iSBC 416 TIMING CONTROL ~ ~ PROM READ REQUEST SELECTED ADDRESS ~ ADDRESS CONTROL BLOCK -V SOCKETS FOR 16K BYTES OF EPROM MEMORY UDATA DATA LINE BUFFERS ADDRESS BUS I ! DATA BUS COMMAND BUS ~MULTIBUS Ly/INTERFACE Flgur/11. ISBC 416 PROM Expansion Board Block Diagram . Physical Characteristics SPECIFICATIONS Width - 12.00 in. (30.40 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 12 oz (340.5 gm) Word Size 8 bits Memory Size Electrical Characteristics Sockets for up to 16K bytes. Memory may be added in 1K·byte increments. DC Power Requirements With 2608 Without Compatible Intel Memory +5V -5V + 12V EPROM - 2708 With 2708 Memory Typ Max Typ Max O.75A O,77A O.OO1A O:5BA " O.79A O,010A O.9GA O.B5A O.4BA O.BOA O.91A O.75A 1.04A - Interface All address, data, and com'mand signals are TTL compatible and iSSC 80 bus compatible. ,Environmental Characteristics Operating Temperature - 0 'C to 55 'C Address Selection a Switches and jumpers allowing the selection of base address for each independent 8K block of memory, on any 8K'boundaries' Reference Manuals Connectors Manuals may be, ordered from any Intel sales represen· tatlve, distributor office or from Intel Literature Depart· ment, 3065 Bowers Avenue, Santa Clar~, California 95051. 9800265A - iSSC 416 Hardware Reference Manual (NOT SUPPLIED) Edge Connector - 86·pin double·sidedPC edge con· nettor,withO.156·in. (0.40 cm) contact centers. Matlng'Connector - Viking 3KH43/9AMK12 ORDERING INFORMATION Part Number Description SBC 416 16K EPROM Expansion Soard 6·17 iSBC 464 or (pSBC 464*) 64K·BYTEEPROM EXPANSION BOARD • Switch selectable base address on 4K·byte boundaries for each memory bank • Provides EPROM/ROM expansion of iSBC 80 and iSBC 86 systems via direct MULTIBUS interface • Assignable anywhere within a 1 megabyte address space • Sockets for up to 64K bytes of EPROM/ROM . • EPROM/ROM components which are not enabled are placed in standby power mode • Compatible with Intel 2758, 2716 or 2732 erasable PROMs and 2136E masked ROMs • Requires a single + 5V power supply The iSBC 464 64K-Byte EPROM Expansion Board is a member of Intel's complete line of iSBCrnemoryand I/O expansion boards. The iSBC 464 board interfaces directly to the iSBC 80 or iSBC 86 single board computers via the MULTIBUS system bus, to expand system EPROM/ROM memory capacity. . . • Same product, manufactured by Intel Puerto Rico, Inc. 6-18 iSBC 464 FUNCTIONAL DESCRIPTION Memory Configuration Memory Banks - When used in the 8 bit mode,the iSBC 464 board is organized into four banks (labeled A-D) of four sockets each. Depending on the type of memory components used, each bank may contain a maximum of 4K, 8K or 16K bytes of memory. Unused memory sockets may be deselected by bank or individually in bank D. Peselecting a bank or individual socket frees that address space for use elsewhere in the system. In the 16/8 bit mode, banks A & Band C & D are paired together to form two banks (labeled AB, CD) which are 16 bits wide. Each of these banks has four socket pairs. Bank AB may be deselected as a single unit. Socket pairs in bank CD may be deselected individually. Thus, board configurations using fewer than 16 memory components do not fill memory address space with unused sockets. Selection/ deselection is accomplished by setting switches on the board. The iSBC 464 board contains sixteen sockets which provide a maximum of 64K bytes of memory expansion. The actual capacity of the board is determined by the type and quantity of EPROM/ROM components installed by the user. The board is compatible with three different sizes of Inte.1 EPROM/ROM devices. These are the 1K byte 2758 EPROM, the 2K byte 2716 EPROM/2316E ROM and the 4K byte 2732 EPROM/2332 ROM. Although only one device size may be used, EPROM and ROM may be mixed on the same board. Mode of Operation - The iSBC 464 board can operate in one of two modes: the 8 bit only mode or the 16/8 bit mode. The 8 bit mode provides the most efficient memory configuration for systems handling 8 bit data. The 16/8 bit mode allows 16 bit words to be accessed by 16 bit processors. In the 16/8 bit mode, 16 bit and 8 bit microprocessors may also access either the high order byte or the low order byte of a 16 bit word. The mode of operation is selected by placing two option jumper blocks in the appropriate sockets. 20 ADDRESS SELECTION LOGIC Memory Access Time - The iSBC 464 board operates with one of 15 switch selectable memory access times ranging from 35 to 1435 nanoseconds. This feature allows the board to be tailored to the performance of the installed components and the system CPU. SOCKETS FOR 16K/32K/64K bytes of EPROM/ROM MEMORY 16 EVEN ADDRESS DATA BYTES II I I-----.....J'-.I MULTIBUS INTERFACE LOGIC I I CONTROL LOGIC I I I I I I 1 L_ ADDRESS LINES ODD ADDRESS DATA BYTES ---l I I 1 I I 1 I 1 1 1 1 _J OATS. DATF MULTIBUSTM Figure 1. iSBC 464 Block Diagram 6-19 iSBC 464 Memory Addresses Switch selectable options on the iSBC 464 board allow the board-to be assigned anywhere'within a 1 megabyte address space. In either operating mode, the base' ad· dress of each memory bank may' beset,to any 4K byte boundary within a 64Kbyte memory page. There is one exception. If the 4K byte devices' are used in the 16/8 bit mode,' then base addresses are restricted to 8K byte boundaries. If the board is used in' a system with an address range greater than 64K· bytes, memory on the iSBC 464 board may reside in'one or two 64K bytemem· ory pages. Any two pages out of a'possible 16 may be chosen by setting switches on the board .. Standby Power Operation The iSBC 464 board. takes advantage of. the standby modes of the Intel 2758, 2716, 2332, and 2732. When they are not enabled,' these components draw as little as SPECIFICATIONS 25% of their active level power with no degradation in access time. The iSBC 464 board is designed so that only two memory components are enabled during a read operation. ' . RAM Overlap Memory banks ofthe iSBC 464 board can be overlapped with the addresses of system RAM by setting on·board switches. The process of addreSSing a memory bank will'drive the inhibit RAM (INH1/) signal true. Thissigrial is issued to the MULTIBUS system bus in order to pre· vent any MULTIBUS accessableRAM in the system from responding to the current address. If an EPROM/ROM is addressed which has its corresponding RAM overlap switch on, an access time of 15 clock cycles is impose<;l. This allows overl,appeddynamic RAM to refreSh before the addressor! the rviULTIBUS is changed. The RAM overlap feat Li re does not apply to RAM which is not on the MULTIBUSsystem bus. ., ' Mating Connector - Viking 3KH43/9AMK12 or compati· ble connector Word Size 8 bits or 16 and 8 bits Physical Characteristics Memory Size Length Height Depth Weight - Sockets are provided for up t6 16K bytes in 1K incre· ments or 32K bytes in 2K increments or 64K bytes in 4K increments Compatible Intel Memory ROM - 2316E or 2332 EPROM -2758 or 2716 or 2732 30.48 Cm (12 in.) 17.15 crn (6.75 in.) 1.27cm (0.5 in.) 294 gm (10.5 oz) without EPROM/ROM Environment Operating Temperature - O·C to + 55·C Relative Humidity Limits - < 90% non·condensing Interface - All 20 address, 16 data, and 6 control sig· nals are TTL compatible and Intel MULTIBUS compati· ble Reference Manual Electrical Characteristics 9800643A - iSBC 464 Memory Expansion Board Hard· ware Reference Manual (NOT SUPPLIED) DC Power (max) Vcc: +5V DC ±5"10 Icc: 1,1 amps without EPROM/ROMs Icc: 1,6 amps with (16) ?716sor 2758s Icc: 1.3 amps with (16) 2732s Icc: 1.35 amps with (16) 2332s Icc: 3.0 amps with (16) 2316s Manuals may be ordered from any Intel sales represen· tative, distributor office or from Intel Literature Depart· ment, 3065 Bowers Avenue, Santa Clara, California 95051. ' ORDERING INFORMATION Connectors Bus - 86·pin double·sided PC edge cOnnector with 0.40 cm (0.156 in.) contact centers Part Number Description SBC 464 64K EPROM Expansion Board inter iSBC 108A/116A COMBINATION MEMORY AND I/O EXPANSION BOARDS • 8Kor 16K bytes of readlwrite memory (iSBC 108A, iSBC 116A boards, respectively) .48 programmable 1/0 lines with sockets for interchangeable line drivers and terminators • Sockets for up to 32K bytes of EPROM • Synchronous/asynchronous communi· cations interface with RS232C drivers and receivers • Auxiliary power bus and memory protect control logic provided for , battery backup RAM requirements • Eight maskable interrupt request lines with a pending interrupt register • RAM and EPROM assignable anywhere within a 1 megabyte address space • 1 msec interval timer The iSBC 108A and iSBC 116A Combination Memory and 1/0 Boards are members of Intel's complete line of iSBC memory and 1/0 expansionboards. Both boards interface directly with any iSBC 80™ or iSBC 86™ single board computer via the MULTIBUSTM interface to expand RAM, EPROM, serial 1/0 and parallel 1/0 capacity. This mixture makes the iSBC 108A and 116A combination boards ideal for 'small microcomputer systems where the on-board resources of a single board computer are insufficient, or for incrementing the memory and 1/0 capacities of larger multiple board systems. 6·21 iSBC 108A/116A FUNCTIONAL DESCRIPTION Memory Capabilities The iSBC 108A board contains 8K bytes and the iSBC 116A board contains 16K bytes of RAM implemented with eight dynamic RAM components. An .intel® 8202A dynamic RAM controller is used to provide all timing, control and refresh signals. Starting on a 4K-byte boundary, RAM may be located anywhere in the MULTIBUS 1 megabyte memory address space. Both combination boards contain four 28-pin sockets for adding up to 4K bytes (using Intel® 2708 or 2758 EPROMs), 8K bytes (using Intel® 2716 EPROMs), 16K bytes (using Intel® 2732 or 2732A EPROMs) or 32K bytes (using Intel® 2764 EPROMs) of non-volatile read-pnly-memory. The boards have been designed to also be compatible with the forthcoming 64K EPROMs. Parallel I/O Interface Each combination board contains 48 programmable I/O lines implemented using two Intel 8255A programmable peripheral interfaces. The system software is used to configure the I/O lines in any combination of unidirectional input/output, and bidirectional ports indicated in Table 1. Therefore, the I/O interface may be customized to meet specified peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable I/O line drivers and terminators. Hence, the flexibility of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity, and drive/termination characteristics for each application. The 48 programmable I/O lines and signal ground lines are brought out to two 50-pin edge connectors that mate with flat, round, or woven cable. Communications Interface A programmable communications interface using Intel's .8251 A Universal Synchronous/Asynchronous Receiver/Transmitter (USART)is contained on each board. A jumper selectable baud rate generator provides the USART with all common communications frequencies between 75 Hz and 38.4 kHz. The USART can be programmed by the system software to select the desired asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). The mode of operation (i.e., synchronous or asynchronous). data format, control character format, parity, and asynchronous serial transmission rate are all under program con- USER OESIGNATED PERIPHERALS .U. I~ ~ ~ ~·T D n 4B PROGRAMMABLE 1'0 LINES LINES r---->"-----, t. INTERAUPTSQRIGINATING FROM THE PROGRAMMABLE COMMUNICATIONS INTERFACE AND PROGRAMMABLE PERIPHERAL INTERFACE ARE JUMPER SELECTABLE Figure 1. iSBC 108A1116A Combination Memory and 1/0 Expansion Board Block Diagram 6·22 iSBC 108A/116A trol. The 8251A provides full duplex, double· buffered transmit and receive capability. Parity, overrun, and framing error detection are all incorporated in the USART. The inclusion of a comprehensive RS232C interface on the boards in conjunction with the USART provides a direct interface to CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems. The RS232C, serial data lines, and signal ground lines are brought out to a 26-pin edge connector which mates with RS232C compatible flat or round cables. Optically Isolated Interface - The iSBC 530 Teletypewriter Adapter provides an optically isolated interface for those systems requiring a 20 mA current loop. The iSBC 530 may be used to interface the iSBC 108A/116A combination boards to teletypewriters and other 20 mA currant loop equipment. is full) or a character has been transmitted (i.e., output data buffer is empty). Two jumper selectable interrupt requests can be automatically generated by the USART when a character is ready to be transferred to the CPU (i.e., receive buffer is full) or a character has been transmitted (transmit buffer is empty). Two interrupt request lines may be interfaced directly from user designated peripheral devices via the 1/0 edge connector. An on'board register contains the status of all eight interrupt request lines, and may be interrogated by the CPU. Each interrupt request line is maskable under program control. Routing for the eight interrupt request lines is jumper selectable. They may be ORed to provide a single interrupt request line for theiSBC 80/10B, or they may be individually provided to the MULTIBUS interface for use by the other iSBC single board computers. Interrupt Request Lines Interval Timer Interrupt requests may originate from eight sources. Four jumper selectable interrupt requests can be automatically generated by the programmable peripheral interfaces when a byte of information is ready to be transferred to the CPU (i.e., input buffer Each board contains a jumper selectable 1 ms interval timer. The timer is enabled by jumpering one of the interrupt request lines from the I/O edge connectorto a 1 ms interval interrupt request signal originating from the baud rate generator. Table 1. Input/Output Port Modes of Operation Mode of Operation Unidirectional Port r-· Lines (qty) Input Output Unlatched Latched & Strobed Latched Latched & Strobed X X X X X X X 1 8 2 8 X 3 4 X X 4 X X 8 X X X 4 Bidirectional Control X X' X' X X X X X 5 8 X 6 4 X X X2 4 X X X2 Notes, 1. Part of port 3 must be used as a control port when efther port 1 or port 2 are used as a latched and strobed input or a latched and strobed output or port 1 is used as a bidi rectional port. 2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output or port 4 is used as a bidirectional port. 6·23 iSBC 108A/116A SPECIFICATIONS Serial Communications Characteristics Memory Word Size Synchronous - 5 - 8 bit characters; internal or external character synchronization; automatic sync insertion. 8bits only. 16-bit single board computers may use this memory only for the storage of 8-bit data. Asynbhronous - 5- 8 bit characters; break characters generation; 1, 1v" or 2 stop bits; false start bit detectors. Memory Addressing EPROM - Up to 4K, 8K, 16K, or 32K bytes of readonly-memory may be located anywhere within a.1 . megabyte address range. The base address must be locatedona 4K-byte boundary. EPROM addresses may not cross 32K-byte boundaries. Interrupts RAM - 8K .(iSBC .108A) or 16K (iSBC 116A) bytes of .RAM may be located anywhere in a one megabyte address range. The base address must be located on a 4K byte boundary. RAM .addresses may not cross 32K byte boundaries. Interrupt· Register Addresses XX11nterrupt mask register XXO Interrupt status regi.ster Note XX is any two hex digits assigned by jumper selection. Memory Response Time Memory Access (ns) Cycle (ns) RAM 450 max' 580 max' EPROM/ROM 450 max 635 max Timer Interval 1.003 ms ±0.1 % when 110 baud rate is selected. 1.042 ms ±0.1 % for all other baud rates. • Without refresh contention. Interfaces Bus - All signals TTL compatible Parallel I/O - All signals TTL compatible Serial I/O' - RS232C Interrupt Requests - All TTL compatible 1/0 Transfer Rate Parallel- Read or write acknowledge time 575 ns max .. Serial - (USART) Connectors Baud Rate (Hz) Frequency (kHz) (Jumper Selectable) Synchronous Interface Asynchronous (Program Selectable) Bus (PI) + 16 19200 9600 4800 2400 1200 600 300 - 307.2 153.6 76.8 38.4 19.2 9.6 4.8 6.98 . Eight interrupt request lines may originate from the programmable peripheral interface (4 lines), the USART (2 lines) or user specified devices via the I/O edge connector (2 lines), or interval timer. - 38400 19200 9600 4800 6980 - +64 4800 2400 1200 600 300 150 75 110 No. of Pins Centers (In.) 86 0.)56 Viking 3KH43/9AMK12 MaUng Connectors Parallel 1/0 50 0.1 3M 3415-000 or TI H312125 Serial 110 26 0.1 3M 3462-000 or TI H312113 Aux. Power (P2) 60 ·0.1 AMP PE5-14559 or TI H311130 NOTE: Connector heights and wire-wrap pin lengths are not guaranteed to conform to Intel OEM packaging. 1/0 Addressing Port 1 2 3 4 Address XX4 XX5 XX6 XX8 5 . XX9 6 8255A No.1 Control 8255A No.2 Control USART Data USART Control XXA XX7 XXB XXC or XXE XXD or XXF Nofe XX is any· two hex digits assigned by Jumper .election .. e'24 iSBC 108A/116A Bus Drivers Auxiliary Power An auxiliary power bus is provided to allow separate power to RAM for systems requiring battery backup of read/write memory. Selection of this auxiliary RAM power bus is made via jumpers on the board. Function Data Commands Memory Protect An active-low TTL compatible memory protect signal is brought out on the auxiliary connector which, when asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system powerdown sequences. Physical Width Height Depth Weight - I/O Drivers - The following line drivers and terminators are all compatible with the liD driver sockets on the iSBC 108A/116A board. Ports 1 and 4 have 25 mA totem-pole drivers and 1 kO terminators. Characteristic 7438 7437 7432 7426 7409 7408 7403 7400 Nole· i inverting: NI = Sink Current (mA) I.OC I NI I.OC NI.OC NI I.OC I = non-inverting: 48 48 16 16 16 16 16 16 OC = open OPTION --,--_.rvv,....---------00 -12tS% No EPROM or Terminators 250 mA 2.9 A - 70 mA 427085 and 8 Terminators 520 mA 3.6 A 180 mA 70 mA 4 27165 and No Terminators 250 mA 3.3 A - 70 mA 4 27325 and No Terminators 250 mA 3.5 A - 70 mA 175 mA 0.45 A 3 mA - 20 mA 0.45 A '3 mA - SBC 902 OPTION ORDERING INFORMATION Part Number SBC 108A Description Combination Memory and liD Expansion Board with 8K bytes RAM SBC 116A Combination Memory and liD Expansion Board with 16K bytes RAM VA. Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, Cal ifQrn ia 95051. 1klJ +5 VaB = -stSCfo Reference Manuals 9800862 - iSBC 108A/116A Board Hardware Reference Manual (NOT SUPPLIED) -------------------------~------1 kU Vee = +5:5% Environmental Characteristics Operating Temperature - O°C to +55°C. '5~~ sac 101 = VDD = +12t5% Aux. Power No RAM Access collector. 3 3 D U " - - - - -.....----cc 32 32 Characteristics 12.00 in. (30.48 cm) 6.75 in. (17.15 cm) 0.50 in. (1.27 cm) 14 oz (397.3 gm) Aux. Power .. RAM Accessed 1/0 Terminators - 2200/3300 divider or 1 kO pullup. 220 U J330H [ Sink Current (mA) Tri-S!at. Tri-Stste Electrical Characteristics Average DC Current Line Drivers and Terminators Driver Characteristic 6·25 0. iSBC3()0 or (pSBC 300*) 32K·BYTE RAM EXPANSION MODULE iSBC340 ()r (pSBC 340*) 16K·BYTE EPROM EXPANSION MODULE • On·board memory expansion for iSBC 86/12A Single Board Computer: • On·board memory expansion . eliminates MULTIBUS system bus latency and increases· system . throughput • iSBC 300 module provi'des 32K bytes of dual port dynamic RAM and plugs directly into the iSBC 86/12Aboard • Low power requirements • iSBC 340 module provides sockets for up to 16K bytes of additional EPROM and plugs directly into the iSBC 86/12A board • Simple, reUable mechanical and electrical Interconnection The iSBC 300 32K·byte RAM e~pansion module arid the iSBC 340 16K-byte EPROM expansion module provide si~ple, low cost expansion of the memory complement available on the iSBC 86/12A single board computer. Each module utilized .individually o'r together can double the.iSBC 86/12A board's on-board RAM and EPROM memory capacity. The (SBC 300 32K-byte RAM expansion module and the iSBC 340 16K-byte EPROM expansion module options for the iSBC 86/t2A board offersystem designers a new level ofJlexibility in defining'and implementing Intel@ single board computer systems. These options allow the systems designer to double the memory complement of an iSBC 86/12Aboard with"a.minimum of system implications. Because they expand the memory configuration o.n-board, they can be accessed as quickly as the existing iSBC 86/12A memory by eliminating the need for accessing the additional memory via the MULTIBUS system bus. With the iSBC,8'6/1;!Aboard mounted.in the top slot of an iSBC604 or iSBC 614 cardcage, sufficient clearance exists for mounting both the iSBC 300 and/or the iSBC 340 expansion module option(s). If the iSBC 86/12A board is inserted into some other slot, the combination of boards will physically (but not electrically) occupy two cardcage slots. Incremental power required by the options is minimal; for instance, only 305 mW is needed for the iSBC 300 RAM expansion niodule. ... , 'Same product, manufactured by Intel Puerto Rico, Inc. 6·26 iSBC 300/340 FUNCTIONAL DESCRIPTION iSBC 300 32K·Byte MULTIMODULE RAM The iSBC 300 module contains sixteen 16K-byte dynamic RAM devices, sockets for the Intel@ 8202A Dynamic computer. It expands the iSBC 86/12A board's on-board dual port RAM capacity from 32K bytes to 64K bytes. The iSBC 300 module contains sixteen 16K-byte dynamic RAM devices, sockets for the Intel'" 8202 Dynamic RAM Controller and memory interface latching. To install the iSBC 300 module, the latches and controller from the iSBC 86/12A board are removed and inserted into the sockets on the iSBC 300 module. The add-on board is then mounted onto the iSBC 86/12A board. Pins extending from the controller's and latches' sockets mate with the devices' sockets underneath (see Figure 1). Additional pins mate to supply power and other signals to complete the electrical interface. The module is then secured at three additional pOints'with nylon hardware to insure the mechanical security of the assembly. To complete the installation, two socketed PROMs are replaced on the iSBC 86/12A board with those supplied with the iSBC 300 kit. These are the on-board memory and MUL TIBUS address decode PROMs which allow the iSBC 86/12A board logic to recognize its expanded on-board memory complement. iSBC 340 16K·byte MULTIMODULE EPROM The iSBC 340 module expands the iSBC 86/12A Single Board Computer's on-board EPROM capacity from 16K bytes to 32K bytes. It measures 3.3" by 2.8" and consists of a PC board with six 24-pin special sockets. Two of the sockets have extended pins which mate with two of the EPROM sockets on the iSBC 86/12A board. Two of the EPROMs which would have been inserted on the iSBC 86/12A board are then reinserted in the iSBC 340 module. Additional pins also mate for bringing chip selects for the remairiingEPROM devices (see Figure 2). The mechanical interface is similar to that used on the iSBC 300 RAM module and consists of two additional mounting holes and the necessary mounting hardware. The iSBC 340 module supports Intel® 2732 EPROM. One section of the iSBC 86/12A on-board memory and MULTIBUS address decode PROMs (the same decode PROMs mentioned for the iSBC 300 module) is already preprogrammed to support the iSBC 340 module with Intel® 2732 EPROMs. This section is selected through the EPROM configuration switches on the iSBC 86/12A board. The iSBC 340 board can optionally be configured by the user to support Intel® 2758 or 2761 EPROMs by programming new iSBC 86/12A decode PROMs to support these devices. Necessary documentation and PROM map listings are in the iSBC 86/12A Hardware Reference Manual (order number 9803074-01). MEMORY LATCHES (FROM Isac 86112A) Isec 86/12A REPLACEMENT MEMORY ADDRESS DECODE PROMS (SUPPLIED WITH Isac 300 OPTION) NYLON MOUNTING HARDWARE (3 PLACES) (SUPPLIED WITH isac 300 OPTION) Figure 1_ Installation of IS'BC 300 MULTIMODULE RAM on ISBC 86/12A Single Board Computer 6-27. iSBC300/340 iSBC 86/12A board +, iSBC 340 module (321< bytes FEOOO-FFFFFH (using 2758 EPROMs); max) FCOOO-FFFFFH{using 2716 EPROMs); F8000., FFFFFH (using 2732 EPROMs). ' " SPECIFICATIONS' Word Size 8 or 16 bits (16-bit data paths) , Memory Size On-board EPROM/ROM is not accessible via the MULTIBUS interface. iSBC 300 ModulI!:'" 32,7,68 bytes of RAM iSBC 340 Module:'" 16,384 bytes (max) of EPROM AuxiliaryPower/Memory Pr(itection Access Time' iSBC 300 Module - Read: 1 ILsec, write: 1.2 ILsec iSBC 340 Module - Standard EPROMs (450 nsec): 1 ILsec, fast EPROMs (350 or 390 nsec):800 nsec . The ,low power memory protection'option 'included on the iSBC 86/12/i boards supports the iSBC 300 RAM module. .' .' " "Local Only" Memory Protection The iSBC 86/12A Single Boa'rd Computer supports dedication of on-board RAM for on-board CPU access only in 8K, 16K, 24K, or 32K-bytesegements. Installation of the iSBC 300 option allows protection of 16K, 32K, 48K, or 64K-byte segments. Interface The interface for the iSBC 300 and iSBC 340 module options is designed only for Intel's iSBC 86/12A Single Board Computer. M~mory Addressing Physical Characteristics On-board RAM CPU Access . ISBC 86/12A boa,rd only (32K bytes) - 00000-07FFFH. . ISBC 86/12A board + ISBC 31i0 module'(64K bytes) OOOOO-OFFFFH. MULTIBUS, Access - Jumper selectable for any8Kbyte boundaiy, but not crossing a 128K-byteb9undary. ISBC 300 'ISBC340 Width 5.75" 3.3" Length 2.35" 2.8" Height of iSBC8,6/12A plus mounted option On-board EPROM ISBC 86/12A board only (16K-bytes max.) ~' FFOOOFFFFFH (using 2758 EPROMs); FEOOO-FFFFFH (using 2316E ROMs or 2716 EPROMs); and FCOOO-FFFFFH (using 2332A ROMs or 2732 EPROMs). ~Includes· .718 .13 oz. Weight .71/i· ,5 oz. EPRO.Ms All necessary mounting hardware (nylon, screws, spacers, ,nuts) are supplied with each kit. Figure 2_ Installation of ISBC 340 MULTIMODULE EPROM Option on ISBC86/12A Single Board'Computer 6-28 ISBC 300/340 Electrical Characteristics Environmental Characteristics DC power requirements: Operating Temperature - 00 to +55 0 C Relative Humidity - to 90% (without condensation) Voltage +5 ±5% Isec 300 Isec 340 1 rnA 120 rnA' +12 ±5% 24 rnA -12 ±5% 1 rnA - Noto: 1. Loaded with Inlel 2732 EPROMs. Reference Manuals All necessary documentation for the iSBC 300 MUL TIMODULE RAM and iSBC 340 MULTlMODULE EPROM! ROM is included inthe iSBC 86!12A Hardware Reference Manual; order #9803074-01. (NOT SUPPLIED) Manuals may be ordered from any Intel sales representative distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051. ORDERING INFORMATION Part Number Description SBC 300 32K byte MUL TIMODULE RAM SBC 340 16K byte MUL TIMODULE EPROM 6-29 . iSBC 301 4K·BYTE RAM MULTIMODULE BOARD • On-board memory expansion for iSBC 80/24 Single Board Computer to 8K bytes • Provides 4K bytes of static RAM directly on the iSBC 80/24 board • Uses 5 MHz (8185-2) RAMs • Single + 5V supply • 0.5 watts incremental power dissipation • On-board memory expansion eliminates MULTIBUS system bus latency and increases system throughput • Reliable mechanical and electrical interconnection The Intel® iSBC 301 4K-Byte RAM MULTIMODULE Board provides Simple, low cost expansion to double the RAM capacity on the iSBC 80/24 Single Board Computer to 8K bytes. This offers system designers a new level of flexibility in defining and implementing system memory requirements. Because memory is configured on-board, it can be accessed as quickly as the existing iSBC 80/24 memory, eliminating the need for accessing the additional memory via the MULTI BUS system bus. As a result, the iSBC 301 board provides a high speed, cost effective solution for systems requiring incremental RAM expansion. Incremental power required by the iSBC 301 module is minimal, dissipating only 0.5 watts. iSBC 301 FUNCTIONAL DESCRIPTION The iSBC 301 board measures 3.95" by 1.20" and mounts above the RAM area on the iSBC 80/24 single board con'iputer: It expands the iSBC 80/24 on·board RAM capacity from 4K bytes to 8K bytes. The iSBC 301 MULTIMODULE board contains four 1K byte static RAM devices and a socket for one of the RAM devices on the iSBC 80/24 board. To install the iSBC 301 MUL TlMODULE board, one of the RAMs is removed from the iSBC 80/24 board and inserted into the socket on the iSBC 301 board. The add·on board is then mounted into the vacated RAM socket on the iSBC 80/24 board. Pins extending from the RAM socket mate with the device's socket underneath (see Figure 1). Additional pins mate to the power supply and chip select lines to complete the electrical interface. The MULTIMODULE board is then secured at two additional points with nylon hardware to insure mechanical security of the assembly. With the iSBC 80/24 board mounted in the top slot of an iSBC 604 or iSBC 614 cardcage, sufficient Clearance exists for mounting the iSBC 301 option. If the iSBC 80/24 board is inserted into some other slot, the combination of boards will physically (but not electrically) occupy two.cardcage slots. RAM DEVICE (FROM iSBC 80/24) BOARD / i S B C 301 OPTION ~ ~HARDWARE(2 - - - -__ NYLON MOUNTING PLACES) (SUPPLIED WITH iSBC 301 OPTION) Figure 1. Installation of iSBC 301 4K·Byte RAM MULTIMODULE Board on the iSBC 80/24 Single Board Computer 6·31 . ' ...::.. '--:.. iSBC 301 SPECIFICATIONS Physical Characteristics Word Size Width - 1.20 in. (3.05 cm) Length - 3.95 in. (10.03 cm) 8 bits Height -.44 in. (1.12 cm) iSBC 301 Board .56 in. (1.42 cm) iSBC 301 Board + iSBC80/24 Board Weight - .69 oz (19 gm) Memory Size 4096 bytes of RAM Electrical Characteristics DC Power Requirements: 10 mA at + 5 Volts incremental power Access Time Read: 140 200 Write: 150 190 ns ns ns ns (from (from (from (from READ command) ALE) READ command) ALE) Environmental Characteristics Operating Temperature - 0 to + 55 C 0 Relative Humidity - to 90% (without condensa· tion) Memory Addressing Memory addressing for the iSBC 301 MULTIMODULE board is controlled by the host board via the address and chip select signal lines. Reference Manuals All necessary documentation for the iSBC 301 MULTIMODULE board is included in the iSBC 80/24 Hardware Reference Manual; Order #142648·001. (NOT SUPPLIED) Manuals may be ordered from any Intel sales representive, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. With the iSBC 80/24 board: The 4K bytes of RAM on the iSBC 301 board oc· cupy the 4K byte address space immediately preceding that of the iSBC 80/24 boards 4K RAM (i.e., default configuration iSBC 301 board's RAM 2000·2FFF iSBC 80/24 board's RAM 3000·3FFF) SPECIFICATIONS Part Number Description SBC 301 4K Byte RAM MUL TIMODULE Board 0 6·32 Digital 110 Expansion and Signal Conditioning Boards 7 CJ_ inter iSBC 337 MULTIMODULE NUMERIC DATA PROCESSOR • Extends host CPU instruction set with arithmetic, logarithmic, transcendental and trigonometric instructions • High speed fixed and floating point functions for iSBC 86, 88 and iAPX 86, 88 systems • MULTIMODULE option containing 8087 Numeric Data Processor • 50 x performance improvements in Whetstone benchmarks over iAPX 86/10 performance • Supports seven data types including single and double precision integer and floating point • Software support through ASM·86/88 Assembly Language and High Level Languages • Implements proposed IEEE Floating Point Standard for high accuracy The Intel iSBC 337 MUL TIMODULE Numeric Data Processor offers high performance numerics support for iSBC 86 and iSBC 88 Single Board Computer users, for applications including simulation, instrument automation, graphics, signal processing and business systems. The coprocessor interface between the 8087 and the host CPU provides a simple means of extending the instruction set with over 60 additional numeric instructions supporting six additional data types. The data formats conform to the proposed IEEE Floating Point Standard insuring highly accurate results. The MULTI MODULE implementation allows the iSBC 337 module to be used on all iSBC 86 and iSBC 88 Microcomputers·and can be added as an option to custom iAPX 86 and iAPX 88 board designs. 7-1 iSBC 337 socket, installing the iSBC337 processor into the host's CPU socket, and reinstalling the host CPU chip into the socket provided for it on the iSBC 337 processor (see Figure 1). All synchronization and timing· signals are provided via the. coprocessor interface with the host CPU. The two processors also share a common address/data bus. (See Figure 2.) The 8087 Numeric Data Processor (NDP) component is capable of recognizing and executing 8087 numeric instructions as they are fetched by the host CPU. This interface allows concurrent processing by the host CPU and the 8087. It also allows 8087 and host CPU instnictions to be intermixed in any fashion to provide the maximum overlapped operation and the highest aggregate performance. OVERVIEW The iSBC 337 MULTIMODULE Numeric Data Processor provides arithmetic and logical instruction extensions to the 8086 and 8088 CPU's of the iAPX 86 and iAPX88 families, to provide iAPX 86/20 and iAPX 88/20 Numeric DataProcessors. The instruction set consists of arithmetic, transcendental, logical, trigonometric and exponential instructions which can all operate .on seven different data types. Thedata types are 16, 32, and 64 bit integer, 32 and 64 bit floating point, 18 digit packed BCD and 80 bit temporary. Coprocessor Interface The coprocessor interface between the host CPU (8086 and 8088) and the iSBC "337 processor provides easy to use and high performance math processing. Installation of the iSBC 337 processor is . simply a matter.of remQving the host CPU from its High Performance and Accuracy The 80-bit wide internal registers and data paths contribute significantly to high performance and Isec 337 MODULE CONNECTOR FOR INTERRUPT REQUEST FROM iSeC 337 MODULE iSBC or iAPX 86 or 88 BOARD Figure 1. iSBC 337 Module Installation 7·2 AFN-01654A iSCB 337 CPU overhead. Once started, the 8087 can process in parallel with and independent of the host CPU. For resynchronization, the NDP's BUSY signal informs the CPU that the NDP is executing an instruction and the CPU WAIT instruction tests this signal to insure that the NDP is ready to execute subsequent instructions. The NDP can interrupt the CPU when it detects an error or exception. The interrupt request line is routed to the CPU through an 8259A Programmable Interrupt Controller. This interrupt request signal is brought down from the iSBC 337 module to the iSBC 86, 88 Single Board Computer through a single pin connector (see Figure 1). The signal is then routed to the interrupt matrix for jumper connection to the 8259A Interrupt Controller. Other iAPX 86 and 88 designs may use a similar arrangement, or by masking off the 8086's "READ" pin from the iSBC 337 socket, provisions are made to allow the now vacated pin of the host's CPU socket to be used to bring down minimizes the execution time difference between single and double precision floating point formats. This 80-bit architecture, in conjunction with the use of the proposed IEI;OE Floating Point Standard provides 'very high resolution and accuracy. This precision is complemented by extensive exception detection and handling. Six different types of exceptions can be reported and handled by the 8087. The user also has control over internal precision, infinity control and rounding control. SYSTEM CONFIGURATION As a coprocessor to an 8086 or 8088, the 8087 is wired in parallel with the CPU as shown in Figure 2. The CPU's status and queue status lines enable the NDP to monitor and decode instructions in synchronization with the CPU and without any ADDRESSJDA TA BUS. ADDRIDATA 8086 OR 6088 HOST CPU eLK (5 MHz) 6284A CLOCK GEN. READY STATUS LINES RESET STATUS TEST ,- - - --- ROJGT OS - - - ---, I I I ------ BUSY OS ROJGT I STATUS I I ADDRIDATA 8087 NDP I I I I I I L I I I I I I L _ _ _ _ -, isec 337 MODULE I I I _____________________ ERROR OR EXCEPTiON iNTERRUPT (To 8259A Interr upt Controller) I ~ Figure 2. iSBC 337 System Configuration 7-3 AFN·01654A iSBC337 Table 1. 8087 Datatypes Data Formats Range Preci· . sion Most Significant Byte 7 07 104 16 Bits 115 Short Integer 109 32 Bits 131 Long Integer 1019 64 Bits 163 Packed BCO 1018 18 Digits s] Short Real 10±38 24 Bits S Long Real 10±308 53 Bits S IE10 Temporary Real 10±4932 64 Bits S IE14 Sign: S BCD Digit (4 07 07 07 07 io] Word Integer Note: Integer: I Fraction: F Exponent: E 07 o7 ~ 07 Two's Complement 101 ]E7 0 Two's Complement 10J -J017 07 Two's Complement 101 oJ 016J Eo]F1 Fo Implicit F23J ~IF1 F5J Eo I Fo Fo Implicit F631 Bias = 127 for Short Real 1023 for Long Real 16i383 for Temp Real Bits): D the interrupt request signal for connection to the base board and then to the 8259A. Another alter· native is to use a wire toestablish this connection. Table 2. Execution Time for Selected 8087 Actual and Emulated Instructions Approximate Execution Time (ms) Floating Point Instruction 8087 8086 (5 MHz Clock) Emulation PROGRAMMING INTERFACE Table 1 lists the seven data types the 8087 sup· ports and presents the format for each type. Internally, the 8087 holds all numbers in the tem· porary real format. Load and store instructions automatically convert operands represented in memory as 16·, 32·, or 64·bit integers, 32· or 64·bit floating point numbers or 18·digit packed BCD numbers into temporary real format and vice versa. Add/Subtract Magnitude Multiply (single precision) Multiply (extended precision) Divide Compare Load (double precision) Store (double precision) Square Root Tangent Exponentiation 14/18 19 27 39 9 10 21 36 90 100 1,600 1,600 2,100 3,200 1,300 1,700 1,200 19,600 13,000 17.100 FUNCTIONAL DESCRIPTION Computations in the 8087 use the processor's register stack. These eight 80·bit registers provide the equivalent capacity of 40 16·bit registers. The 8087 register set can be accessed as a stack, with instructions operating on the top stack element, or as a fixed register set, with instructions operating on explicitly designated registers. The NDP is internally divided into two processing elements, the control unit (CU) and the numeric execution unit (NEU), providing concurrent operation of the two units. The NEU executes all numeric instructions, while the CU receives and decodes instructions, reads and writes memory operands and executes processor control instructions. Table 3 lists the 8087's instructions by class. As· sembly language programs are written in ASM 86/88, the iAPX 86, 88 assembly language. Table 2 gives the execution times of some typical numeric instructions and their equivalent time on a5 MHz 8086. Control Unit The CU keeps the 8087 operating in synchronization with its host CPU. 8087 instructions are intermixed with CPU instructions in a single instruc7-4 AFN-01654A iSBC 337 Table 3. 8087 Instruction Set Data Transfer Instructions Arithmetic Instructions Real Transfers Addition load real FLD FST FSTP FXCH Store real Store feal and pop FADD FADDP FIADD Disable interrupts Add real and pop FENIIFNENI Enable interrupts Integer add FLDCW Load control word FSTCW/FNSTCW Store control word Subtraction Integer Transfers 1nleger load Integer store Integer store and pop Packed Decimal Transfers FBLD FBSTP FSUB cSUBP FISUB FSUBR FSUBRP FISUBR Subtract real Subtract real and pop Integer subtract Subtract real reversed Subtract real reversed and pop Integer subtract reversed Multiplication Packed decimal (BCD) load Packed decimal (BCD) store and pop FMUL FMULP FIMUL Multiply real Multiply real and pop Integer multiply FDIV FDIVP FIDIV FDIVR FDIVRP FIDIVR Divide real Divide real and pop Integer divide Divide real reversed Divide real reversed and pop Integer divide reversed FSQRT FSCALE FPREM FRNDINT FXTRACT FABS FCHS Square root Scale Partial reminder Round to integer Extract exponent and significand Absolute value Change sign Comparison Instructions Division FCOM FCOMP FCOMPP FICOM FICOMP FTST FXAM Compare real Compare real and pop Compare real and pop twice Integer compare Integer compare and pop Test Examine Initialize processor FDISI/FNDISI Add real Exchange registers FILD' FIST FISTP Processor Control Instructions FINIT/FNINIT FSTSW/FNSTSW Store status word FCLEXlFNCLEX Clear exceptions FSTENV/FNSTENV Store environment FLDENV Load environment FSAVEfFNSAVE Save state FRSTOR Restore state FINCSTP Increment stack pointer FDECSTP Decrement stack pointer FFREE Free register FNOP " FWAiT No operation CPU wait Other Operations Transcendental Instructions FPTAN FPATAN F2XM1 FYL2X FYL2XP1 Partial tangent Partial arctangent 2x-1 Y- lo 9 2X Y-log 2(X + 1) tion stream. The CPU fetches all instructions from memory; by monitoring the status signals emitted by the CPU, the NDP control unit determines when an 8086 instruction is being fetched. The CU taps the bus in parallel with the CPU and obtains that portion of the data stream. instruction is a load, the CU additionally captures the data word when it becomes available on the local data bus. If data required is longer than one word, the CU immediately obtains the bus from the CPU using the request/grant protocol and reads the rest of the information in consecutive bus cycles. In a store operation, the CU captures and saves the store address as in a load, and ignores the data word that follows in the "dummy read" cycle. When the 8087 is ready to perform thestore, the CU obtains the bus from the CPU and writes the operand starting at the specified address. After decoding the instruction, the host executes all opcodes but ESCAPE (ESC), while the 8087 executes only the ESCAPE class instructions. (The first five bits of all ESCAPE instructions are identi· cal). The CPU does provide addressing for ESC instructions, however. Numeric Execution Unit An 8087 instruction either will not reference memory, will require loading one or more operands from memory into the 8087, or will require storing one or more operands from the 8087 into memory. In the first case a non-memory reference escape is used to start 8087 operation. In the last two cases, the CU makes use of a "dummy read" cycle initiated by the CPU, in which the CPU calculates the operand address and initiates a bus cycle, but does not cap· ture the data. Instead, the CPU captures and saves the address which the CPU places on the bus. If the The NEU executes all instructions that involve the register stack; these include arithmetic, logical, transcendental, constant and data transfer instructions. The data path in the NEU is 80 bits wide (64 fraction bits, 15 exponent bits and a sign bit) which allows internal operand transfers to be performed at very high speeds. When the NEU begins executing an instruction, it activates the 8087 BUSY signal. This signal is 7·5 AFN-01654A iSBC 337 Status Word used in conjunction with the CPU WAIT instruc· tion to resynchronize both processors when the NEU has completed its cUrrent instruction. The.status word shown in Figure 4 reflects the over· all state of the 8087; it may be stored in memory and then inspected by CPU code. The status word is a 16·bit register divided into fields as shown in Figure 4. The busy bit (bit 15) indicates whether the NEU is executing an instruction (B =1) or is idle (B = 0). Several instructions which store and manipulate the status word are executed exclusively by the CU, and these do not set the busy bit themselves. Register Set The 8087 register set is shown in Figure 3. Each of the eight data registers in the 8087's register stack is 80 bits wide and is divided into "fields" corre· sponding to the NDP's temporary real data type. The register set may be addressed as a push down stack, through.a top of stack pointer or any register may be addressed explicitly relative to the top of ~~k .. ' DATA FIELD SIGN TAG FIELD r-- SIGNIFICAND EXPONENT . The four numeric condition code bits (CO·C3) are similar to the flags in a CPU:various instructions up· date these bits to reflect the outcome of NDP opera· tions . I-I-I-I-I-- r-- I-'----- 15 Bits 14·12 of the status word point to the 8087 register that is the currenttop·of·stack (TOP). Bit 7 is the interrupt request bit. This bit is set if any unmasked exception bit is set and cleared otherwise. Bits 5·0 are set to indicate thatthe NEU has detect· ed an exception while executing an instruction. 0 CONTROL REGISTER Tag Word STATUS REGISTER INSTRUCTION POINTER The tag word marks the content of each register as shown in Figure 5. The principal function of the tag word is to optimize the NDP's performance. The tag word can be used, however, to interpret the contents of 8087 registers. DATA POINTER Figure 3. 8087 Register Set 15 1 "I c, 1 TOP 1 1c,1 c, C, I I R l x l PE I~EloElzE1DEJ IEJ I EXCEPTION FLAGS (1 =EXCEPTION HAS OCCURRED) INVALID OPERATION DENORMALIZED OPERAND ZERO DIVIDE OVERFLOW UNDERFLOW PRECISION (RESERVED) INTERRUPT REQUEST. (1) CONDITION CODE TOP OF STACK POINTER NEU BUSY (1) (2) IR is set if any unmasked exception bit Is set, cleared otherwise. Top Values: 000 Regi.ster-O Is Top of Stack. 001 = Register! Is Top of Stack . = . 111 = Register 7 Is Top of Stack. Figure 4. 8087 Status Word (2) iSBC 337 Exception Handling The 8087 detects six different exception conditions that can occur during instruction execution. Any or all exceptions will cause an interrupt if unmasked and interrupts are enabled. TAG VALUES: 00 = VALID 01 = ZERO 10 = SPECIAL 11 = EMPTY If interrupts are disabled the 8087 will simply suspend execution until the host clears the exception. If a specific exception class is masked and that exception occurs, however, the 8087 will post the exception in the status register and perform an on-chip default exception handling procedure, thereby allowing processing to continue. The exceptions that the 8087 detects are the following: Figure 5. 8087 Tag Word Instruction and Data Pointers The instruction and data pointers (see Figure 6) are provided for user-written error handlers. Whenever the 8087 executes an N EU instruction, the CU saves the instruction address, the operand address (if present) and the instruction opcode. The 8087 can then store this data in memory. 15 1. INVALID OPERATION: Stack overflow, stack underflow, indeterminate form (010, - , etc.) or the use of a Non-Number (NAN) as an operand. An exponent value is reserved and any bit pattern with this value in the exponent field is termed a Non-Number and causes this exception. If this exception is masked, the 8087's default response is to generate a specific NAN called INDEFINITE, or to propagate already existing NANs as the calculation result. 0 INSTRUCTION POINTER (15·0) INSTRUCTION POINTER I 0 I (19·16) INSTRUCTION OPCODE (10·0) DATA POINTER (15·0) DATA POINTER (19·16) I 0 Figure 6. 8087 Instruction and Data Pointers Control Word The NDP provides several processing options which are selected by loading a word from memory into the control word. Figure 7 shows the format and encoding of the fields in the control word. 2. OVERFLOW: The result is too large in magnitude to fit the specified format. The 8087 will generate the code for infinity if this exception is masked. 15 I x x X II C I R C I P C J M I x J 1 PM UMj o~ ZMj DMJ 1M J I EXCEPTION MASKS 1.1 = EXCEPTION IS MASKED) INVALID OPERATION DENORMALIZED OPERAND ZERO DIVIDE OVERFLOW UNDERFLOW PRECISION (RESERVED) INTERRUPT MASK (1 = INTERRUPTS ARE MASKED) PRECISION CONTROL (I) ROUNDING CONTROL (21 INFINITY CONTROL (0 = PROJECTIVE, 1 =AFFINE) (RESERVED) II) Precision Control 00=24 bits 01 = Reserved 10=53 bits 11 =64 bits 12) Rounding Control 00 = Round to Nearest or Even 01 = Round Down (toward· ) 10 = Round Up (toward + ) 11 Chop (truncate toward zero) = Figure 7. 8087 Control Word 7-7 iSBC 337 3. ZERO DIVISOR: The divisor is zero .while the dividend -is a non-infinite, non-zero number. Again, the 8087 will generate the code for infini· ty if this exception is masked. 6. INEXACT RESULT: If the true result is not exactly representable in the specified format, the result is rounded according to the rounding mode, and this flag is set. If this exception is masked, processing will simply continue. SOFTWARE SUPPORT 4. UNDERFLOW: The result is non·zero but too small in magnitude to fit in the specified for· mat. If this exception is masked the 8087 will denormalize (shift right) the fraction until the exponent is in range. This process is called gradual underflow. 5. DENORMALIZED OPERAND: At least one of the operands or the result is denormalized; it has the smallest exponent but a non-zero significand. Normal processing continues if this exception is masked off. The iSBC 337 module is supported by Intel's ASM·86/88 Assembly Language and PUM·86/88 Systems Implementation Language. In addition to the instructions provided in the languages to sup· port the additional math functions, a software emulator is also available to allow the execution of iAPX 86/20 instructions without the need for the iSBC 337 module. This allows for the development of software in an environment without the iAPX 86/20 processor and then transporting the code to its final run time environment with no change in mathematical results. SPECI FICATIONS Environmental Characteristics Operating Temperature - Physical Characteristics 0 °C to 55°C Width - 5.33 cm (2.100 ") Free air moving across base board and iSBC337 module. Length - 5.08 cm (2.000 ") Height - 1.82cm( .718") iSBC 337 board + host board Relative Humidity - Up to 90% R.H. without con· densation. Weight - 17.33 grams (.576 oz.) Reference Manual Electrical Characteristics 142887·001 - iSBC 337 MULTIMODULE Numeric Data Processor Hardware Reference Manual (NOT SUPPLIED) Manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. DC Power Requirements (8087 only) Vee = 5V ± 5% Icc = 475 mA max. ORDERING INFORMATION Part Number SBC 337 Description MULTIMODULE Numeric Data Processor 7·8 inter iSBC 501 DIRECT MEMORY ACCESS CONTROLLER • Transfers initialized via software • Directly compatible with Intel iSBC 80 and iSBC 86 Single Board Computers • Transfers data up to 330K words per second for interleaved transfers • Block length up to 65,536 words • Directly addresses up to 65,536 memory locations • Software selectable/maskable interrupt operations • Transfer rate up to 1 million words per second for block transfers The iSBC 501 The iSBC 501 speed, direct 16 peripheral • Interrupt priority switch selectable Direct Memory Access Controller is a member of Intel's complete line of iSBC OEM computer systems. interfaces directly with any iSBC single board computer-based system via the MULTIBUS interface. High memory access control and interfacing for transfers between iSBC expansion board memory and up to devices is provided. 7-9 iSBC 501 FUNCTIONAL DESCRIPTION the shared bus mode. Either mode may be used with the other iSBG single board computers. Four timing strobes are provided for the control of data input transfers and four timing strobes are provided for output transfer operations. strobes are initiated and selected via sys· tem softwar~, .and strobe pulses .are jumper selectable to 100, 200, 400, 800, or 1600 ns widths. Transfer Capability Block lengths up tp 65,536 bytes long may be trans· ferred directly to or from RAM memory in iSBG systems at rates of up to 1 million words per second. The iSBG 50116·bit addressing capability allows transfers to tilke place at any location within memory. It is designed to control the direct transfer of data to or from Intel iSBG memory expansion or combination memory and I/O boards. Two transfer modes of operation are included. System software is used to select the desired mode. Transfer rates up to 330K words per second may be achieved in the shared bus mode, wherein the iSBG 501. request access to the system bus for 600 ns to perform a transfer of one word to or from memory. The second mode, the override mode, establishes the DMA control· ler as the only master which may access the system bus during the transfer period, thereby providing rapid block transfer capability. This mode provides transferrates up to 1 million words per second. The iSBG 80/10B single board computer may only .interact with the iSBG 501 in Interrupt Requests Interrupt requests originating from the DMA controller are software maskable, active·low, and switch selec· table to anyone of eight priority levels. User selected DMA interrupt requests may originate automatically upon completion of a transfer operation, from an exter· nal DMA device, or from a software command to the DMA controller (for system testi ng purposes). Peripheral Interface A 4·bit tag register is provided which may be used as a device select port to provide selection for four (up to 16 with external decoding) high speed peripheral devices interfacing through theiSBG 501. INTERRUPT 1----- EXTERNAL INTERRUPT REQUEST CONTROL L--,r--J - - - - - EXTERNAL INTERRUPT MASK ADDA E5S/COMMAND DECODE INPUT COMMAND STROBES (4) ADDRESS OUJPUT COMMANP STROBES (4) CONTAOL 'v---:-- DATA IN DATA OUT sus INTERFACE 'v-----:DATA STATUS/CONTROL IN TAG REGISTER MUL TIBUS SYSTEM BUS Figure 1. iSBC 501 DMA Controller Block Diagram 7·10 iSBC 501 SPECIFICATIONS Tag Register (4 bits) - The contents of the tag register are used as control/select lines to the external periph· eral devices being interfaced by the iSBC 501 (e.g., as the "go" command line to each of four devices), or the tag register outputs may be used with external decoding to expand the maximum number of DMA peripherals to 16. Word Size 8 bits Block Size 65,536 words, max Status Register (8·blts) - Provides 4 bits of DMA con· troller status: software interrupt, memory read/write operation requested, external/end·of·transfer interrupt, and DMA controller busy. The status register also pro· vldes four status/control bits directly from user periph· eral devices. Address Capability 65,536 words Transfer Rates Transfer Rates (K bytes/sec)1 Mode Memory Read Operations Address Selection Memory Wrlle iSBC 501 registers are located in a jumber selectable block starting at any 16·word boundary in the I/O ad· dress space. Operations Typical Worst Case3 Shared bus!! CPU hailed 330 270 330 270 Shared bus, CPU executing code 2 180 160 180 160 1000 660 1000 660 Typical Worst Case3 Register Locations Address l 110 Operalion Interrupts XO XI X2 X3 X4 X8 X9 XA XB XC XD XE XF Output Output Output Output Output Output Output Output Output Output Output Output Output Interrupt requests originating from the DMA controller are software maskable, active·low, and switch select· able to anyone of eight priority levelS. User selectable DMA interrupt requests may originate automatically upon completion of a transfer operation, from an exter· nal DMA device, or from a software command to the DMA controller (for system testing purposes). XO XI X2 X3 X4 X5 X6 X7 Input Input Input Input Input Input Input Input Override Noles: 1. Transfer rates given are to and from RAM memory on iSBC 108A com· bination memory and 110 board. 2. Shared bus mode may be used with Intel iSBC 80/10B. 3. Assumes every OMA transfer must wall for RAM refresh cycle to be completed, worst case memory cycle times. Function Output strobe 0 Output strobe 1 Output strobe 2 Output strobe 3 Output tag strobe Set interrupt Reset interrupt Load control register Load tag register Load LSB length register Load MSB length register Load LSB memory address register Load MSB m~mory address register Input command strobe 0 Input comma no strobe 1 Input command strobe 2 Input command strobe 3 Read LSB length register Read MSB length register Read DMA status Invalid command Note Key Registers 1. X is any hex digit, assigned by iumbers. Control Register (6 bits) - The contents of the control register specify the busy status of the DMA board, the type of operation to be performed (transfer or non· transfer), the transfer direction (to or from memory), the interrupt condition (enabled or disabled), and the means by which the DMA board is using the system bus (shared mode or override mode). Connectors Double·Sided Pins (qly) Cenlers (In.) Mallng Connectors Bus 86 0.156 Viking 3KH4319AMKI2 110 100 0.100 Intel MDS 990 Viking 3VH50/1JN5 Inlerface Memory Address Register (16 bits) - Contains the ad· dress of the next memory location to be accessed by the iSBC 501. Loaded from the CPU, prior to a transfer operation, with the address of the first memory location to be accessed. The address is gated onto the system address bus during each transfer, and incremented by one for each word transferred. Interface Characteristics flO Line Driver Sink Current - 48 mA flO Line Terminator Load - 15012 pullup Input - Data positive relative to data bus Output - Data positive relative to data bus Output Strobes - Jumper selectable to 100, 200, 400, 800, or 1600 ns pulse widths. All flO interface data and control signals are TTL com· patible and MULTIBUS interface compatible. Length Register (16 bits) - Contents of this register specify the total number of words to be transferred. This word count is decremented by one after each word is transferred. The transfer stops when the word count equals zero. 7·11 iSBC501 Physical Characteristics Equipment Supplied Width -12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth- 0.50 in. (1.27 cm) Weight ~ 12 oz (340.5gm) iSBC 501 DMA Controller Board Electrical Characteristics DC Power Requirements Vee = 5V ±5% ICC = 3,35A max; 2.70A typ Envlron~ental Characteristics Operating Temperature - O·C to 55·C ORDERING INFORMATION Part Number SBC 501 Description . Direct Memory Acce.ss Controller Reference Manuals 9800294A - iSBC 501 Hardware Reference Manual (NOT SUPPLIED) iSBC 501 Schematic (SUPPLIED) Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. iSBC 508 1/0 EXPANSION BOARD • iSBC 1/0 expansion via direct MULTIBUS interface • Selectable latched or unlatched input ports • Four 8·bit terminated input ports • Latched outputs with selectable width strobes • Four 8·bit output ports with buffered TTL drivers • Switch selectable 1/0 port addresses The iSBC 5081/0 Expansion Board is a member of Intel's complete line of iSBC memory and 1/0 expansion boards. The iSBC 508 interfaces directly to any iSBC single board computer via the system bus to expand input and output port capacity. Four 8·bit terminated input ports are contained on the board. Data is gated into the port while the strobe is present and latched if the strobe is removed. The iSBC 508 contains four 8·bit output ports. All output lines are driven by TTL level buffer drivers residing on the board. Output data is latched. A strobe signal of jumper selectable width is sent to the peripheral device during an output operation. Address selection is accomplished using two resident rotary switches to select one of 64 unique base addresses for all input and output ports. The board operates with a single + 5V power supply. 7·13 iSBC 508 [ 8 BITS IN STBO [ PERIPHERAL DEVICES 8 BITS INSTB' l 8.BITS 1 INPUT PORTO ~ INPUT PORT' ~ .. INPUT PORT 2 ,I !I IN STB 3 J I ~ -.I I ADDRESS L DECODE I J r+I. .I OUTPUT [ PORT 0 INPUT PORT 3 I J J-::.- ~ II CONTROL (BUS EI HANDSHAKE LOGICI I J +I ~ 8 BITS j\ OUT STB 0 OUTPUT PORT' [ 8 BITS ... IN STB 2 L 8 BITS I j..:... OUTSTB' ~ PERIPHERAL DEVICES OUTPUT. [ 8 BITS PORT2· l O U T STB 2 OUTPUT PORT 3 I [ 8 BITS .1\ l O U T STB 3 ADDRESS BUS OATA BUS CONTROL BUS I MU LTiBUS IN TERFACE Figure 1. ISBC 508110 Expansion Board Block Diagram SPECI FICATIONS Connectors Bus Edge Connector - 86-pin double-sized PC edge connector with 0.156-ln. contact centers Mating Connector - Control Data VPB01 E43AOOA 1 Word Size 8 bits Capacity 110 Edge Connector - 100-pin double-sided PC edge connector with 0.1 in. contact centers Mating Connector - Viking 3i} . . ~~i~~~~E iSBC 517 Table 1. InputlOutput Port Modes of Operation Mode of Operation Unidirectional Lines (qty) Ports Input Bidirectional Output Control Unlatched Latched & Strobed Latched Latched & Strobed 8 X X X X 8 X X X X 4 X X X1 4 X X X1 4 8 X X X X 5 8 X X X X 2 3 X ~---- X ~------+--------r----.----~------~--------+-------~----------~----~ 6 4 X X X2 4 X X X2 r------~- Notes 1. Part of port 3 must be used as control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output port or port 1 is used as a bidirectional port. 2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output port or port 4 is used as a bidirectional port. . Interval Timer maskable under program control. Routing for the eight interrupt request lines is jumper selectable. They may be ORed to provide a single interrupt request line for the iSBC 80/10B, or they may be individually provided to the system bus for use by other iSBC single board computers. Each board contains a jumper selectable 1 ms interval timer. The timer is enabled by jumpering one of the interrupt request lines from the 1/0 edge connector to a 1 ms interval interrupt request signal originating from the baud rate generator. SPECIFICATIONS Serial Communications Characteristics I/O Addressing· Synchronous - 5-8 bit characters; internal or external character synchronization; automatic sync insertion. Asynchronous - 5-8 bit characters; peak characters generation; 1, 1';', or 2 stop bits; false start bit detectors. Port Address 1 2 3 4 5 8255 8255 USART USART No.2 No.1 Data Control Control Control 6 X4 X5 X6 X8 X9 XA X7 XB XC XD Note Interrupts X is any hex digit assigned by jumper selection. Eight interrupt request lines may originate from the programmable peripheral interface (4 lines), the USART (2 lines), or user specified devices via the 1/0 edge connec· tor (2 lines) or interval timer. I/O Transfer Rate Parallel - Read or write cycle time 760 ns max Serial - (USART) Baud Rate (Hz) Frequency (kHz) (Jumper Selectable) 153.6 76.8 38.4 19.2 9.6 4.8 6.98 Synchronous Interrupt Register Address Asynchronous X1 (Program Selectable) 38400 19200 9600 4800 6980 716 764 9600 4800 2400 1200 600 300 2400 1200 600 300 150 75 110 - XO Interrupt mask register Interrupt status register Note X is any hex digit assigned by jumber selection. Timer Interval 1.003 ms ±0.1% when 110 baud rate is selected 1.042 ms ± 0.1 % for all other baud rates 7-17 iSBC 517 , Bus Drivers Interfaces 8us - All signals TTL compatible Parallel 110 - All signals TTL compatible Serial I/O - RS232C Interrupt Requests ,"- All TTL compatible Characteristic Sink Current (rnA) Data Tri·state 50 Commands Tri·state 25 Function Connectors Pins (qty) Ceriters (in.) Bus 86 0.156 CDC VPBOl E43AOOA 1 Parallel 110 50 0.1 3M 3415·000 or TI H312125 Serial 110 26 0.1 3M 3462·000 or TI H312113 Auxiliary 1 60 0.1 AMP PE5·14559 or TI H311130 Interface Mating Connectors Physical Characteristics Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 14 oz (397. 3 gin) Note Electrical Characteristics 1. Connector heights and wire·wrap pin lengths are not guaranteed to , conform to Intel OEM or system packaging. Auxiliary connector is used for test purposes only. Average DC Current Vcc= +5V ±5% V DD = +12V ±5% VAA = -12V ±5% Icc= 2.4 mA max IDD= 40mA max IAA = 60 mA max Line Drivers and Terminators I/O Drivers - The following line drivers and terminators are compatible with all the 110 driver sockets on the iSBC 517: Driver Characteristic Sink Current (rnA) 7438 7437 7432 7426 7409 7408 7403 7400 I.DC I NI I.DC NI.DC NI I.DC I 48 48 16 16 16 16 16 16 Note Does not include power required for optional 110 drivers and 110 terminators. With eight 220Q/330Q input terminators installed, all terminator inputs low. Environmental Characteristics Note Operating Temperature - I :;;: inverting: NI :;;: non·inverting; DC :;;: open·collector. O·C to + 55·C Ports 1 and 4 have 25 mA totem-pole drivers and 1 kQ terminators. I/O Terminators - Reference Manual 220Q/330Q divider or 1 kQ pullup 98003888 - iSBC 517 hardware Reference Manual (NOT SUPPLIED) +~---------'~~:,:-~------~--~ 220QI330QJ..r--------~~ 0 ISBC 901 OPTION Manuals may be ordered from any'lntel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. 1 kQ 1 kQ + 5V - - - - - - - - " " " '.....------------~o ISBC 902 OPTION ORDERING INFORMATION Part Number Description SBC 517 Combination 110 Expansion Board 7-18 iSBC 519 or (pSBC 519*) PROGRAMMABLE 1/0 EXPANSION BOARD • Jumper selectable 0.5,1.0,2.0, or 4.0 ms interval timer • iSBC 1/0 expansion via direct MULTIBUS Interface • 72 programmable 1/0 lines with sockets for interchangeable line drivers and terminators • Eight maskable interrupt request lines with priority encoded and program· mabie interrupt algorithms • Jumper selectable 1/0 port addresses The iSBC 519 Programmable I/O Expansion Board is a member of Intel's complete line of iSBC memory and I/O expansion boards. The iSBC 519 interfaces directly to any iSBC single board computer via the system bus to expand input and output port capacity. The iSBC 519 provides 72 programmable I/O lines. The system software is used to configure the I/O lines to meet a wide variety of peripheral requirements. The flexibility of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity, and drive/termination characteristics for each application. Address selection is accomplished by using wire-wrap jumpers to select one of 16 unique base addresses for the input and output ports. The board operates with a single + 5V power supply. ·Same product, manufactured by Intel Puerto Rico, Inc. 7-19 iSBC 519 The interval timer provided on the iSBC 519 may be used to generate real time clocking in systems requiring the periodic monitoring of 1/0 functions. The time interval is derived from the iSBC 80 constant clock (BUS CCLK) and the timing interval is jumper selectable. Intervals of 0.5, 1.0, 2.0, and 4.0 milliseconds may be selected when an iSBC 80 single board computer is used to generate the clock. Other timing intervals may be generated if the user provides a separate constant clock reference in the system. FUNCTIONAL DESCRIPTION The 72 programmable 1/0 lines on the iSBC 519 are im· plemented utilizing three Intel 8255 programmable peripheral interfaces. The system software is used to configure the 1/0 lines in any combination of unidirec· tional inputloutput and bidirectional ports indicated in Table 1. In order to take full advantage of the large number of possible 1/0 configurations, sockets are pro· vided for interchangeable 1/0 line drivers and ter· minator.s. The 72 programmable 1/0 lines and signal ground lines are brought out to three 50·pin edge con· nectors that mate with flat, round, or woven cable. Eight-Level Vectored Interrupt An Intel 8259 programmable interrupt controller (PIC) provides vectoring for eight interrupt levels. As shown in Table 2, a selection of three priority processing algo· rithms is available to the system designer so that the Interval Timer Typical 1/0 read access time is 350 nanoseconds. Typical 1/0 readlwrite cycle time is 450 nanoseconds. Table 1. Input/Output Port Modes of Operation Mode of Operation Unidirectional Lines (qty) Ports Input Latched & Strobed Output Latched & Strobed Unlatched Bidirectional Control Latched 1,4,7 8 X X X X X X X 2,5,8 8 X x: 3,6,9 4 X X Xl,2,3 4 X X Xl,2,3 NOles 1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output port or port 1 is used as a bidirectional port. 2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output port or port 4 is used as a bidirectional port. 3. Part of port 9 must be used as a control port when either port 7 or port 8 are used as a latched and strobed input or a latched and strobed output port or port 7 is used as 'a bidirectional port. USER DESIGNATED PERIPHERALS nil PROGRAMMABLE I!O LINES 3 INTERRUPT REQUEST LINES 1 -I I I INTERVAL TIMER [ 11 6 1 INTERRUPT REQUEST LINE DRIVER! TERMINATOR INTERFACE I I INTERRUPT CONTROLLER I I I INTERRUPT REQUEST LINES J I PROGRAMMABLE PERIPHERAL INTERFACE I ADDRESS BUS DATA BUS CONTROL BUS CONSTANT CLOCK (CCLKl I I BUS INTERFACE I I iSBC 80 BUS Figure 1. iSBC 519 Programmable 110 ExpanSion Board Block Diagram 7-20 [ 1 1 iSBC 519 incoming requests is of the highest priority, determines whether this request is of higher priority than the level currently being serviced, and if appropriate, issues an interrupt to the system master. Any combination of interrupt levels may be masked through storage, via software, of a single byte to the interrupt mask register of the PIC. Table 2. Interrupt Priority Options Operation Algorithm Fully nested Interrupt request line priorities fixed at as highest, 7 as lowest. Auto·rotating Equal priority. Each level, after receiving service, becomes the lowest priority level until next interrupt occurs. ° Specific priority Interrupt Request Generation - Interrupt requests may originate from 10 sources. Six jumper selectable inter· rupt requests can be automatically generated by the programmable peripheral interfaces when a byte of in· formation is ready to be transferred to the system master (i.e., input buffefis full) or a character has been transmitted (i.e., output data buffer is empty). Three interrupt request lines may be interfaced to the PIC directly from user designated peripheral devices via the 1/0 edge connectors. One interrupt request may be gen· erated by the interval timer. System software assigns lowest priority level. Priority of all other levels are based in se· quence numerically on this assignment. manner in which requests are serviced may be config· ured to match system requirements. Priority assign· ments may be reconfigured dynamically via software at any time during system operation. The PIC accepts interrupt requests from the programmable parallel 1/0 interfaces, the interval timer, or direct from peripheral equipment. The PIC then determines which of the Bus Line Drivers - The PIC interrupt request output line may be jumper selected to drive any of the nine in· terrupt lines on the MULTIBUS. Any of the on·board reo quest lines may also drive any interface interrupt line directly via jumpers and buffers on the board. SPECIFICATIONS Interfaces Addressing Bus - All signals TTL compatible Parallel 1/0 - All signals TTL compatible Interrupt Requests - All TTL compatible 8255 Port 1 2 3 Address XO XI X2 8255 No.1 4 Control X3 5 6 X4 X5 X6 No.2 Control X7 8255 7 8 9 X8 X9 XA No.3 Control Connectors XB Interface Interrupts Bus Register Addresses (hex notation, 1/0 address space) XD Interrupt request register XC In·service register XD Mask register XC Command register XD Block address register XC Status (polling register) Note Several registers have the same physical address; sequence of access and one dala bit 01 control word determines which register will respond. Ten interrupt request lines may originate from the pro· grammable peripheral interface (6 lines), or user specified devices via the 1/0 edge connector (3 lines), or interval timer (1 line). Interval Timer Output Register - Timer interrupt register output is cleared by an output instruction to 1/0 address XE or XF1. Timing Intervals - 500, 1,000, 2,000, and 4,000 ms ± 1 %; jumper selectable 2 . Pins (qty) Centers (in.) Mating Connectors 86 0.156 Viking 3KH43/9AMK12 -- Parallel 1/0 50 0.1 3M 3415·000 or TI H312125 Serial 1/0 26 0.1 3M 3462·000 or TI H312113 Auxiliary 1 60 0.1 AMP PE5·14559 or TI H311130 Note 1. Connector heights and wirewrap pin lengths are not guaranteed to conform to Intel OEM or System packaging. Line Drivers and Terminators 1/0 Drivers - The following line drivers and terminators are compatible with all the 1/0 driver sockets on the iSBC 519: Driver Characteristic Sink Current (rnA) 7438 7437 7432 7426 7409 7408 7403 7400 I,OC I NI I,OC NI,OC NI I,OC I 48 48 16 16 16 16 16 16 Notes 1. X is any hex digit assigned by jumper selection. 2. Assumes constant clock (CCLK) frequency of 9.216 MHz ± 1 % . - - 7·21 Note I ;:;; inverting; NI ;:;; non·inverting; OC ;:;; open-collector. iSBC 519 1/0 Terminators - 2201"2/3301"2 divider or 1k1"2 pullup Physical Characteristics Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 14 oz (397.3 gm) +5V-------->;:: 220Q/330Q~_ ~I,--- - - - ' - - - - - < 0 Isec 901 OPTION 1 kQ 1 kQ + 5V ----~'NI~.- - - - - - - 0 Isec 902 OPTION Electrical Characteristics Average DC Current Ports 1, 4, and 7 may use any of the drivers or terminators shown above for unidirectional (input or output) port con· figurations. Either terminator and the following bidirec· tional drivers and terminators may be used for ports 1,4, and 7 when these ports are used as bidirectional ports. Voltage Without Termtnatlon 1 With Termlnallon2 VCC= +5V ±5% ICC= 1.5A max 3.5A max Note Bidirectional Drivers 1. Does not include power required for optional 110 drivers and 110 ter· minators. Sink Current (rnA) Characteristic NI, TS 25 I, TS 50 2. With 18 220QI330Q Input terminators installed, all terminator inputs low. Note I ::: Inverting; NI ::: non-inverting; TS ;;;. three-state. Environmental Characteristics Terminators (for ports 1, 4, and 7 w.hen used as bidi rec· tional ports) Operating Temperature - Supplier Product Series CTS 760· Dale LDP14k·02 Beckman 699·1 Reference Manual 9800385B - iSBC 519 hardware Reference Manual (NOT SUPPLIED) Bus Drivers Characteristic Sink Current (rnA) Tri-state 50 Trj·state 25 Manuals may be ordered from any Intel sales represen· tative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number Description SBC 519 Programmable I/O Expansion Board 0 'C to + 55 'C 7·22 iSBC 530 TELETYPEWRITER ADAPTER • Compact, easily mounted package with standard connectors • General purpose RS232C to 20 rnA current loop interface • Compatiblity with iSBC 80 and iSBC 86 Single Board Computers • Jumper selectable RS232C data set or data terminal configuration • Compatibility with iSBC 80 combination boards • Interface opto·isolator for high noise immunity The iSBC 530 Teletypwriter Adapter provides a compact and flexible means for interfacing Intel iSBC 80 and iSBC 86 Single Board Computers, iSBC combination memory and 1/0 expansion boards, and most RS232C compatible equip· ment to teletypewriters and other 20 mA current loop equipment. The iSBC 530 converts RS232C signal levels to an op· tically isolated 20 mA current loop interface. The iSBC 530 provides signal translation for transmitted data (Txd), received data (RcD), and a teletypewriter paper tape reader relay. The RS232C interfaces are jumper selectable, and may be configured to accept signals from an RS232C data terminal or data set. Threaded holes have been incorporated in the iSBC 530 for ease In system chassis design and multiple units may be mounted together to support multiple serial channels. The units are mountable in any of three planes. When used with an iSBC Single Board Computer, power is provided to the iSBC 530 directly through its RS232C connector. Power may also be provided through either of two auxiliary power connectors for standard current loop Interfacing. The noise immunity benefits of total inter· system power isolation may be achieved through the use of both auxiliary power connectors on the iSBC 530. 7·23 iSBC530 I 3 :~: +L-I_EEl_I_/_:_EEl_I ~50 0.512 ---L 'I; [ "'""-1=:U M g iSBC 530 TTY ADAPTER lid ffi IlLo85_~.'30~1 - - 0,92 lTI ~ 3 . 0 - -I 0.92 ~ .. -4.84--~ NOTES: 1. ALL DIMENSIONS IN INCHES ·2 ALL FOUR MOUNTING HOLES THREADED FOR 6·32 MACHINE SCREWS 3 CUTOUTS FOR AUXILIARY POWER CONNECTORS Figure 1. isec 530 Dimensions SPECI FICATIONS Physical Characteristics Width Height Depth Weight - Interface Characteristics RS232C Side RS232C signal levels inlout 1 Electrical Characteristics TTY Side 20 mA optically isolated current loop Power connectors for ground, + 12V and -12V, are jumper selectable. Power may be provided via 25·pin RS232C connector or via two separate auxiliary power connectors. Auxiliary connectors allow total power system isolation at iSBC 530 opto-coupler interface. Power Requirements Voo = + 12V ±5% VAA = -12V ±5% 100 = 98 mA max IAA = 98 mA max Note 1. RS232C data set ready line controls 20 rnA paper tape reader relay driver line. Mating Connectors RS232C 20 rnA (nV) 2.876 in. max (7.31 cm) 4.850 in. max (12.32 cm) 0.920 in. max (2.34 cm) 9 oz (255.4 gm) Cinch OB·25S In Cannon OB·25S Cinch OB·25P Environmental Characteristics lIT Cannon OB·25P Operating Temperature - AMP Auxiliary power Molex Connector 87159·7 Pin 87023·1 Polarizing key 87116·2 Connector 09·50·7071 Pin 08·50·0106 Polarizing key 15·04·0219 Reference Manuals None supplied. Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office· or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California. 95051. Note 1. Pins from a given vendor may only be used with connectors from the same vendor. ORDERING INFORMATION Part Number Description SBC 530 Teletypewriter adapter O'C to 55'C 7-24 iSBC 556 OPTICALLY ISOLATED 1/0 BOARD • iSBC 80 and MULTIBUS compatible • Provisions for plug·in, optically isolated receivers, drivers, and terminators • Up to 48 digital optically isolated input/output data lines • Voltate/current levels - Input up to 48V - Output up to 30V, 60 rnA • Choice of - 24 fixed input lines - 16 fixed output lines - 8 programmable lines • Com-mon interrupt for up to 8 sources • + 5V supply only The iSBC 556 Optically Isolated I/O Board provides 48 digital input/output lines with isolation between process application or peripheral device and the iSBC 80 series single board computers_ The iSBC 556 conta'instwo 8255A programmable interface devices, and sockets for user supplied optically isolated drivers, receivers, and input resistor terminators, together with common interrupt logic and iSBC 80 bus interface logic. Input signals can be single-ended or differential types with user defined input range (resistor terminator and opto-isolated 'receiver selection), allowing flexibility in design of voltage and threshold levels. The output allows user selection of Opto-Isolated Darlington Pair which can be used as an output driver either as an open collector or current swiich; . 7-25 -_._- -- ~. ~ iSBC 556 Table 1. I/O Ports Opto·lsolator Receivers, Drivers, and Terminators Port No. X=I/O Base Address Type of I/O Lines (qty) Input Output Input/ Control " Input Output Input/ } Output Control 8 8 8 X+O X+1 X+2 X+4 X+5 X+6 X+7 Dual Resistor Opto·lsolator Terminator Dual Darlington Opto·lsolator Pair' Driver Pac Rp 16·Pin DIP 8·Pin Dip 6·Pin DIP 7438 Bourns Monsanto Monsanto or Equivalent 4116R·00 MCT66 4N29,30 or Equivalent or Equivalent 31,32 or Equivalent - 4 1 1 8 8 SPECI FICATIONS - 8 - 8 2 if output - 4 ' 1if input 8 - 8 8 1 Pull·Up iSBC 902 2 if input Connectors Number of Lines Inierf.ce 24 input,lines 16 .output lines 8 programmable lines: 4 input - Pins (qty) PI iSBC bus '86 Jl 16 fixed input & ' 50 8 fixed output lines J2 8 fixed output, 8 50 fixed output, & 8 programmable input/output lines 4 .output 1/0 Interface Characteristics Line·to·Line Iselation - 235V DC or peak AC Input/Output Isolatien - 500V DC or peak AC Centers In. Mating Connectors em 0.156 0,1 0,1 Viking 3K'H4319AMK12 3M 3415'()00 or TI M312125 3M 34'15·000 or TI M312125 TERMINATOR PAC USER-SUPPLIED D DUAL OPlO·ISOLATOR r -,- - -r--<>--'~----' : Physical Characteristics i - -I USER·SUPPLIED ___ Rp RESISTOR 1'6-PIN DIP (+) iSBC '---9---+--oI----I--+--~H D-*~I*---+----+--~: Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 12 oz (397.3 gm) Electrical Characteristics L _____ --' Average DC Current Rp DETERMINES VOLTAGE AND CUR~~N! RAN~E. Vcc= + 5V ± 5%, 1~OA witheut user supplied isolated receiver/driver Icc'" 1.6A max with user supplied iselator receiver/driver Bus Interface Characteristics All data address and control commands are iSBC 80 bus compatible. , 110 Addressing 8255'1 Port A I B J 825H2 Control C Address x+ol X+ll X+2 A X+.:i J B I Control C X+4I X + 5 I X + 6 ORDERING INFORMATION Part Number Description Optically Iselated I/O Beard Temperat'ure -O·C te 55·C , Relative Humidity - 0 to 90%, non·condensing X+7 Where: base address is from OOH to 1FH (jumper selectable) SBC 556 , Environmental Characteristics Reference Manual 9800489·02 - ,iSsC 556 Hardware Reference Manual (NOT SUPPLIED) Reference manuals are shipped with each product .only if deSignated SUPPLIED (see abeve). Manuals may be ordered frem any ,Intel sales representative, distributer office or from Intel Literature, Department, 3065 Bowers Avenue, Santa Ciara, California 95051. iSBC 569 INTELLIGENT DIGITAL CONTROLLER • Single board digital I/O controller with up to four microprocessors to share the digital input/output signal processing • 2K bytes of dual port static read/write memory • Sockets for up to 8K bytes of Intel 2758, 2716,2732 erasable programmable read only memory • 3 MHz 8085A central control processor • Three sockets for 8041/8741 A Universal Peripheral Interface (UPI·41A) for dis· tributed digital I/O processing, such as: - .. 48 programmable parallel 110 lines with sockets for interchangeable line drivers or terminators Industrial signal processor (iSBC 941) Custom programmed 8041A18741A • Three programmable counters • 12 levels of programmable interrupt control . • Single + 5V supply • MULTIBUS standai'dcontrol logic compatible with optional iSBC 80 and iSBC 86 CPU, memory, and I/O expansion boards • Three operational modes - Stand·along digital controller - MULTIBUS master - Intelligent slave (slave to MULTIBUS master) The Intel iSBC 569 Intelligent Digital Controller is a single board computer (BOB5A based) with sockets for three B041A1B741A Universal Peripheral Interface chips (UPI-41A). The I/O processing algorithm may betailored to application requirements using designer selected combinations of standard Intel industrial signal processors (e.g., iSBC 941) or user programmed UPI-41A processors. These devices may be used to offload the BOB5A processor from time consuming tasks such as pulse counting, event sensing, and parallel or serial digital I/O data formatting with error checking and handshaking. The iSBC 569 board is acomplete digital controller with up tofourIJrocessors on asingle 6.75 inches x 12.00 inches (17.15cm x 30.4Bcm) printed circuit board. The BOB5A CPU, system clock, read/write memory, non-volatile memory, priority interrupt logic, programmable timers, MUL TIBUS control and interface logic, optional UPI processors and optional line driver and terminators all reside on one board. 7·27 iSBC 569 work on the more important application programming of machine or process optimization. Controlling the Intel UPI-41A processors becomes a simple task of reading or writing command and data bytes to or from the data bus buffer register on the UPI device. Programming the iSBC 941 Industrial Digital Processor to produce a pulse output, for example, is as simple as sending command and parameter bytes indicating initialization, pulse output selection, period and delay parameters, followed by a command to begin execution. FUNCTIONAL DESCRIPTION Intelligent Digital Controller Three modes of operation - the iSBC 569 Intelligent Digital Controller is capable of operating in one of three modes; stand alone controller, bus master, or intelligent slave. Stand alone controller - the iSBC 569 board may function as a stand alone, single board controller with CPU, memory, and I/O elements on a single board. Five volt (+5VDC) only operation allows configuration of low cost controllers with only a single power supply voltage. The on-board 2K bytes RAM and upto 16K bytes ROM/EPROM, as well as the assistance of three UPI-41A processors, allow significant digital I/O control from a single board. Central Processing Unit A powerful Intel 8085A 8-bit CPU, fabricated on a single LSI chip, is the central processor for the iSBC 569 ™ controller. The six general purpose 8-bit registers may be addressed individually or in pairs, providing both single and double precision operations. The program counter can address up to 64K bytes of memory using iSBC expansion boards. The 16-.bit stack pointer controls the addressing of an external stack. This stack provides sub-routine nesting bounded only by memory size. The minimum instruction execution time is 1.30 microseconds. The 8085A CPU is software compatible with the Intel 8080A CPU. Bus master - in this mode of operation,. the iSBC 569 controller may interface with and control iSBC expansion memory and I/O boards; or even other iSBC 569 Intelligent Digital Controllers configured as. intelligent slaves (but no additional bus masters) .. Intelligent slave - the iSBC 569 controller can perform as an intelligent slave to any 8- or 16-bit MUL TIBUS master CPU by offloading the master of digital control related tasks. Preprocessing of data forthe master is controlled by the on-board 8085A CPU which coordinates upto three UPI-41A processors.' Using the iSBC 569 board as an intelligent slave, multi-channel digital control can be managed entirely on-board, freeing a system master to perform other system functions. The dual port RAM memory allows the iSBC 569 controller to process and store data without MULTI BUS memory contention. Bus Structure The iSBC 569 Intelligent Digital Controller utilizes a triple bus architecture concept. An internal bus is used for onboard memory and I/O operations. A MUL TlBUS interface is available to provide access for all external memory and I/O operations. A dual port bus with controller enables access via the third bus to 2K bytes of static RAM from either the on-board CPU or a system master. Hence, common data may be stored in on-board memory and may be accessed either by the on-board CPU or by system masters. A block diagram of the iSBC 569 functional components is shown in Figure 1.. Simplified Programming By using Intel UPI-41A processors for common tasks such as counting, sensing change of state, printer control and keyboard scanning/debouncing, the user .frees up time to MULTIBUS Figure 1. iSBC 569 Intelligent Digital Controller Block Diagram 7·28 iSBC 569 RAM Capacity Programmable Timers The iSBC 569 board contains 2K bytes of read/write memory using Intel 2114 static RAMs. RAM accesses may occur from either the iSBC 569 controller or from any other bus master interfaced via the MUL TIBUS system bus. The iSBC 569 board provides addressing jumpers to allow the on-board RAM to reside within a one megabyte address space when accessed via the system bus. In addition, a switch is provided which allows the user to reserve a 1K byte segment of on-board RAM for use by the SOS5A CPU. This reserved RAM space is not accessible via the system bus and does not occupy any system address space. The iSBC 569 Intelligent Digital Controller board provides three independently programmable interval timer/ counters utilizing one Intel S253 Programmable Interval Timer (PIT). The Intel S253 PIT provides three 16-bit BCD or binary interval timer/counters. Each timer may be used to provide a time reference for each UPITM processor or for a group of UPI processors. The output of each timer also connects to the 8259A Programmable Interrupt Controller (PIC) providing the capability of timed interrupts. All gate inputs, clock inputs, and timer outputs of the 8253 PIT are available at the I/O ports for external access. EPROM/ROM Capacity Two sockets for up to 16K bytes of nonvolatile read only memory are provided on the iSBC 569 board. Nonvolatile memory may be added in 1K-byte increments up to a maximum of 2K bytes using Intel 275S erasable and electrically reprogram mabie ROMs (EPROMs); in 2K-byte increments up to a maximum of 4K bytes using Intel 2316 ROMs or 2716 EPROMs; in 4K byte increments up to SK bytes maximum using Intel 2732 EPROMs; or in SK-byte increments up to 16K bytes maximum using Intel 2364 ROMs (both sockets must contain same type ROM/EPROM). All on-board ROM/EPROM operations are performed at maximum processor speed. Timer Functions -In utilizing the iSBC 569 controller, the systems designer simply configures, via software, each timer to meet systems requirements. The S253 PIT modes are listed in Table 1. The contents of each counter may be read at any time during system operation with simple read operations for event counting applications. The contents of each counter can be read "on-the-fly" for time stamping events or time clock referenced program initiations. Table 1. 8253 Programmable Timer Functions Universal Peripheral Interfaces (UPI-41A) The iSBC 569 Intelligent Digital Controller board provides three sockets for user supplied Intel S041A/S741A Universal Peripheral Interface (UPI-41A) chips. Sockets are also provided for the associated line drivers and terminators for the UPII/O ports. The UPI-41A processor is a single chip microcomputer containing a CPU, 1K bytes of ROM (S041A) or EPROM (S741A), 64 bytes of RAM, 16 programmable I/O lines, and an S-bit timer/event counter. Special interface registers included in the chip allow the UPI-41A processor to function as a slave processor to the iSBC 569 controller board's SOS5A CPU. The UPI processor allows the user to specify algorithms for controlling peripherals directly thereby freeing the SOS5A for other system functions. For additional information, including UPI-41A instructions, refer to the UPI-41 User's Manual (Manual No. 9S00504). Function Operation I nterrupt on terminal count When terminal count is reached, an interrupt request is generated. Programmable one·shot Output goes' low upon receipt of an external trigger edge or software command and returns high when terminal count is reached. This function is retriggerable. Rate generator Divide by N counter. The output will go low for one input clock cy· cle, and the period from one low· going pulse to the next is N times the input clock period. Square·wave rate generator Output will remain high until one· half the count has been com· pleted, and go low for the other half of the count. Software triggered strobe Output remains high until software loads count (N). N counts after count is loaded, output goes low for one input clock period. Hardware triggered strobe Output goes low for one clock pe· riod N counts after rising edge on counter trigger input. The counter is retriggerable. Event counter On a jumper selectable basis, the clock input becomes an input from the external system. CPU may read the number of events oc· curring after the counting "win· dow" has been enabled or an in· terrupt may be generated after N counts occur in the system. Industrial Digital Processor (iSBC 941) The iSBC 941 Industrial Digital Processor is a 40-pin DIP device which provides the user with easy-to-use processing of digital input and output signals desired in many industrial automation environments. One of nine digital I/O functions can be selected at anyone time for measuring, counting, or controlling up to 16 separate I/O lines. An additional eight utility commands allow reading or setting the condition of unused I/O lines. Simplex serial input and output modes can assemble or disassemble bytes transmitted asynchronously over TTL lines, including insertion and deletion of start/stop bits. The iSBC 941 processor plugs into any of the three UPI-41A sockets on the iSBC 569 board. Simple programming commands from the master SOS5A processor can .thus implement up to 4S lines of preprocessed digital I/O signals. For specific commands and further information, refer to the iSBC 941 Data Sheet in this document. 7-29 iSBC 569 Interrupt Capability expanded system using one iSBC 569 Intelligent Digital Controller as the system master and additional controllers as intelligent slaves, The iSBC 569 Intelligent Digital Controller provides interrupt service for up to 12 interrupt sources, Any of the 12 sources may interrupt the on-board processor, Four interrupt levels are handled directly by the SOS5A CPU and eight levels are serviced from an Intel S259A Programmable Interrupt Controller (PIC) routing an interrupt request output to the INTR input of the SOS5A. Intelligent Slave Programming When used as an intelligent slave, the iSBC 569 controller appears as an additional RAM memory module, System bus masters communicate with the iSBC 569 board as if it were just an extension of system memory, To simplify this communication, the user has been given some specific tools: 8085A Interrupt - Each of four direct SOS5A interrupt inputs has a unique vector memory address, An SOS5A jump instruction at each of these addresses then provides software linkage to interrupt service routines located independently anywhere in the memory, Flag Interrupt - The Flag Interrupt is generated any time a write command is performed by an off-board CPU to the first location of iSBC 569 RAM, This interrupt provides a means for the master CPU to notify the iSBC 569 controller that it wished to establish a communications sequence, The flag interrupt is cleared when the onboard processor reads the first location of its RAM. In systems with more than one intelligent slave, the flag interrupt provides a unique interrupt to each slave outside the normal MUL TIBUS interrupt lines (INTOI-INn/), 8259A Interrupts - The eight interrupt sources originate from both on-board controller functions and the system bus: UPI-41A Processors - one interrupt from each of three UPI processor sockets, S253 PIT - one interrupt from each of three timer outputs, MUL TIBUS System Bus - one of eight MUL TIBUS interrupt lines may be jumpered to either of two S259A PIC interrupt inputs, RAM - The on-board 2K byte RAM area that is accessible to both an off-board CPU and the on-board SOS5A may be configured for system access on any 2K boundary, Programmable Reset - The iSBC 569 Intelligent Digital Controller board has a programmable output latch used to control on-board functions, Three of the outputs are connected to separate UPI.-41A RESET inputs, Thus, the user can reset any or all of the UPI-41A processors under software control. A fourth latch output may be used to generate an interrupt request onto the MUL TIBUS interrupt lines, A fifth latch output is connected to a lightemitting diode which may be used for diagnostic purposes, MULTIBUS Interrupts - The third tool to improve system operation as an intelligent slave is access to the MUL TIBUS interrupt lines. The iSBC 569 controller can both respond to interrupt signals from an off-board CPU, and generate an interrupt to the off-board CPU .via the system bus. System Development Capability Software development for the iSBC 569 Intelligent Digital Controller board is supported by the Intellec® Microcomputer Development System including a resident macroassembler, text editor, system monitor, a linker, object code locator, and Library Manager. In addition, both PLiM and FORTRAN language programs can be compiled to run on the iSBC 569 board, A unique incircuit emulator (ICE-S5™) option provides the capability of developing and debugging software directly on the iSBC 569 board. This greatly simplifies the design, development, and debug of iSBC 569 system software, Expansion Capabilities When the iSBC 569 controller is used as a single board digital controller, memory and 1/0 capacity may be expanded using Intel MUL TIBUS compatible expansion boards, In this mode, no other bus masters may be in the system, Memory may be expanded to a64K byte capacity by adding user specified combinations of RAM boards, EPROM boards, or combination boards, Input/output capacity may be increased by adding 1/0 expansion boards, Multiple iSBC 569 boards may be included in an 8013;;(\ accessible from on-board SOS5A. Separately addressable from system bus. Off-board expansion - up to 64K bytes of EPROMIROM or RAM capacity, CP~) Word Si7.(;. - 8, 10 cr;:?t '::,its Cycle Time - 1,30 1l80C ::'c ..:% ~:1' 'estest executable instruction; i.e" fou~ clock cyclns. Clock Rate - 3,07 MHz ± ,1% I/O Capacity Memory Capacity Parallel-Timers - Three timers, with independent gate input, clock input, and timer output user-accessible, Clock inputs can be strapped to an external source or to an on-board 1.3S24 MHz reference, Each timer is '/}'1nected to a S259A Programmable Interrupt Controller CI"( • 8y also be optionally connected to UPI processors, On-board ROM/EPROM - 2K, 4K, 3V;, 0' 16K by!es flf user installed ROM or EPROM On-board RAM - 2K bytes of static RAM. Fully UPI-I/Q - Three UPI-41A interfaces, each with two S-bit I/O ports plus the two UPI Test Inputs, TheS-bit ports are user-configurable (as inputs or outputs) in groups offour, System Access Thr.e Ou",1 port memory - i25 nsec 7-30 isec 569 Serlal-1 TTL compatibleserial channel utilizing SID and SOD lines of on-board 8085A CPU Depth - 17.15 cm (6.75 inches) Thickness - 1.27 cm (0.50 inch) Weight - 3.97 gm (14 ounces) On-Board Addressing Electrical Characteristics DC Power Requirements - + 5V All communications to the UPI-41A processors, to the programmable reset latch, to the timers, and to the interrupt controller are via read and write commands from the on-board 8085A CPU. @ 2.58A with no op· tional devices installed. Foreach8741Aadd 135 mAo For each 220/330 resistor network, add 60 mAo Add the fol· lowing for each EPROM/ROM Installed. Memory Addressing On-board ROM/EPROM - 0-07FF (using 2758 EPROMs); O-OFFF (using 2716 EPROMs or 2316 ROMs); 0-1 FFF (using 2732 EPROMs); D-3FFF (using the 2364 ROMs) On-board RAM - 8000-87FF System access - any 2K increment 00000-FF800 (switch selectable); 1K bytes may be disabled from bus access by switch selection. +S.OV Current Requirement Type 1ROM I/O Addressing Source 8253 UPIO UPI1 UPI2 PROGRAMMABLE RESET 8259A Driver 7438 7437 7432 7426 7409 7408 7403 7400 Input frequencies - jumper selectable reference Internal: 1.3824 MHz ± .1 % (.723 I'sec, nominal) External: User supplied (2 MHz maximum) Output Frequencies (at 1.3824 MHz) Real-time interrupt interval Rate Generator (frequency) Max' 1.45 /-lsec 47.4 msec 21.09 Hz 691.2 KHz 125 125 240 55 55 rnA rnA rnA rnA rnA I/O Drivers - The following line drivers are all compatible with the I/O driver sockets on the iSBC 569 Intelligent Digital Controller. Timer Specifications Min' 2ROMS rnA rnA rnA rnA rnA Line Drivers and Terminators Addresses OEOH-OE3H OE4H-OE5H OE6H-OE7H OE8H-OE9H OEAH-OEBH OECH-OEDH Function 100 100 120 40 40 2758 2716 2316E 2732 2364 Nots I = inverting; Characteristic Sink Current (mA) I,OC I NI I,OC NI,OC NI I,OC I 48 48 16 16 16 16 16 16 NI = non-inverHng; OC = open collector. I/O Terminators - 2200/3300 divider or 1 kO pullup 220Q +5V----~::~---_, 220QI330QL 1. Single 16-bit binary count ~~.- - -_______ 0 Isec 901 OPTION Interfaces 1 kQ MUL TlBUSTM Interface - All signals compatible with iSBC and MUL TIBUS architecture Parallel I/O - All signals TTL compatible Interrupt Requests - All TTL compatible Timer - All signals TTL compatible Serial I/O - All signals TTL compatible 1 kQ + 5V iSBC 902 OPTION Environmental Characteristics Operating Temperature - O°C to 55°C (32°F to 131°F) Relative Humidity - To 90% without condensation Reference Manuals Connectors Pins (qty) Centers (In.) Bus 86 0.156 Viking 3KH43/9AMK12 Parallel 1/0 50 0.1 3M 3415-000 or TI H312125 Interface -----'\N',~------o 9800845·01 - iSBC 569 Intelligent Digital Controller Board Hardware Reference Manual (NOT SUPPLIED) 9803077 - iSBC 941 Digital Signal Processor User's Guide (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Mating Connectors PhYSical Characteristics Width - 30.48 cm (12.00 inches) ORDERING INFORMATION Part Number Description SBC 569 Intelligent Digital Controller 7·31 Communication Controllers 8 _~.c::::::".. _ .. iSBC 534 or (pSBC 534*) FOUR CHANNEL COMMUNICATION EXPANSION BOARD • iSBC 80 serial 110' expansion through four programmable synchronous and asynchronous communications channels • Jumper selectable interface register addresses • 16·bit parallel 110 interface compatible with Bell 801 automatic calling unit • Individual software programmable baud rate generation for each serial 110 channel • RS232C/CCITT V.24 interfaces plus 20 mA optically isolated current loop interfaces (sockets) • Two independent programmable 16·bit interval timers • Programmable digital loopback for diagnostics • Sixteen maskable interrupt request lines with priority encoded and programmable interrupt algorithms • Interface control for auto answer and auto originate modems The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of iSBC 80 memory and 1/0 expansion boards. The iSBC 534 interfaces directly to anyiSBC 80 single board computer via the system bus to provide expansion of system serial communications capability. Four fully programmable synchronous and asynchronous serial channels with RS232C buffering and provision for 20 mA optically isolated current loop buffering are provided. Baud rates, data formats, and interrupt priorities for each channel are individually software selectable. In addition to the extensive complement 0'1 EIA Standard RS232C signals provided, the iSBC 534 provides 16 lines of RS232C buffered programmable parallel 1/0. This interface is configured to be directly compatible with the Bell Model 801 automatic calling unit. These capabilities provide a flexible and easy means for interfacing iSBC 80 and System 80 based systems to RS232C and optically isolated current loop compatible terminals, cassettes, asynchronous and . . . synchronous modems, and distributed processing netwOrks. 'Same product, manufactured by Intel Puerto Rico, Inc. 8·1 iSBC 534 FUNCTIONAL DESCRIPTION lime delay is needed, software commands to the programmable timers select the desired function. Three : functions of these timers are supported on the iSBC 534, as shown in Table 1. The,contents of each counter may be read at any time during system operation. Communications Interface Four programmable communications interfaces using Intel's 8251 Universal" SynchroriousiAsynchronous Receiver/Transmitter (USART) are contained on the board.' Each USART can be programmed by the system software tc;>individually select the desired asynchronous or synchronous serial datfltransmission technique (including IBM Bi-Sync). The mode of operation, (i.e. synchronous. or asyncl:lronous), data format, control character format, parity, and baud rate are all under program control. Each 8251 provides full duplex, double buffered transmit and receive capability. Parity, overrun, and framing error detection are all incorporated 'i.ri :each USART. Each set of RS232C command lines, serial data lines', arid signal ground lines are brought out to 26-pin edge connectors that mate with RS232C flat or round cables. Table 1. Programmable Timer Functions CURRENT RS232C DEVICE COMPATIBLE DEVICE coo, , IIIIhen terminal count, is reached an interrupt request is generaled. This function is used for the generation of real-time clocks. Divide by N counter; The output will go low for one input clock cycle and high for N - 1 Input clock periods. Square wave rate Output wil,l remain high for onehalf the count and low for the generator other half of the count. 16·Bitlnterval Timers DEVICE Operation Interrupt on terminal count Rate generator' The iSBC 534 provides six fully programmable and independent BCD and binary 16-bit interval timers utilizing two Intel 8253 programmable interval timers.· Four timers are available to the systems designer to generate baud rates for the USARTS under software control. Routing for the outputs from the other two counters is jumper selectable. Each may be independently routed to'the programmable interrupt controller to provide real. time clocking or to the USARTs (feii applicationsrequir, irig different transmit and receive bilUd rajes). 'In utilizing the iSBC 534,the systems, designer simply configures, via s'?ftware, each timer independently to meet system requirements. Whenever ag,i~en !:laud. rate or RS232C COMPATIBLE Function Interrupt Request Lines Two independent Intel 8259 programmable interrupt controllers (PIC's) provide ,,!ectoring for 16 interrupt levels. ·'As shown in Table 2, a selection of three pri'ority processing algorithms is available to the system designer. The manner in which requests are serviced may thus be config!lred to match system requirements. Priority assignments may be reconfigured dynamically via, software at any time during system operation. Any combination of interrupt levels may be masked through storage, via software, ofa single byte to the interrupt mask register of each PIC. Each PIC's interrupt request CURRENT LOOP' . DEVICE AS232C CURRENT RS232C CURRENT COMPATIBLE DEVICE DEVICE COMPATIBLE DEVICE LOOP DEVice . 6 INTERRUPT"' I,IITERRUPT REOUEST , LINES IFRDMUSARTSj Figure 1_ iSBC 534,Four coo, AEQUEST LINES Channel~ommunications 8-2 2 PROGRAMMABLE TIMERS Expansion Board Block.Diagram iSBC 534 Table 3_ Interrupt Assignments eutput line may be jumper selected to. drive any of the nine interrupt lines en the iSBC 80 bus. Table 2. Interrupt Priority Options Algorithm Operation Fully nested Interrupt request line priorities fixed at 0 as highest, 7 as lewest. Auto.retating Equal priority. Each level, after receiving service, becomes the lew est prierity level until next interrupt eccurs. System seftware assigns lewest prlerity level. Prierity ef all other levels based in sequence numerically en this assignment. Specific prierity The iSBC 534 prevides 16 RS232C buffered parallel 1/0 lines implemented utilizing an Intel 8255 programmable SPECIFICATIONS PIT 1 counter 1 PIT 2 ceunter 2 Ring indicater (all perts) Present next digit Carrier detect pert 0 Carrier detect pert 1 Carrier detect pert 2 Carrier detect pert 3 Single Timer Function Real·Time Interrupt Interval Sample Baud Rates 1 Baud Rate (Hz) Rate Generator (Frequency) Asynchronous + 16 .,. 64 9600 4800 2400 1200 600 300 2400 1200 600 300 150 75 110 - PORT 0 Rx' ROY PORT 0 Tx ROY PORT 1 Rx ROY PORT 1 Tx ROY PORT 2 Rx ROY PORT 2 Tx ROY PORT 3 Rx ROY PORT 3 Tx ROY Input Frequency (On-Board Crystal Oscillater) MHz ± 10% (0.813I's peried, nominal) Synchronous - 5·8 bit characters; internal er external character synchrenizatien; autematic sync insertien. Asynchronous - 5·8 bit characters; break character generation; 1, 1 y" or 2 step bits; false start bit detectien. 38400 19200 9600 4800 6980 0 1 2 3 4 5 6 7 Interval Timer and Baud Rate Generator Frequencies Serial Communications Characteristics - PIC 1 -Complete operational details on the Intel 8251 USART, the Intel 8253 Programmable Interval Timer, the Intel 8255 Programmable Peripheral Interface, and the Intel 8259 Programmable Interrupt controller are con· tained in the Intel 8080 Microcomput~r Syslem User's Manual and 8085 Microcomputer System User's Manual. Systems Compatibility 153.6 76.8 38.4 19.2 9.6 4.8 6.98 PIC 0 peripheral inteirface (PPI) cenfigured to. eperate i"h mode O. * Tl)ese lines are configured to be directly cempatible with the Bell 801 automatic calling unit (ACU). This capability allews the iSBC 534 to. interface iSBC 80 and System 80-based systems t6 Bell 801 type ACUs and up to feur modems or other serial cemmunicatiens devices. Fer systems net requiring interface to. an ACU, the parallel 1/0 lines may also be used as general purpes.e .RS232C compatible control lines in syst.em implementation. Interrupt Request Generation - As shewn i.n Table 3, interrupt requests may originate from 16 sources. Two. jumper selectable interrupt requests (8 total) can be automatically generated by each USART when a character is ready to. be transferred to the iSBC 80 system bus (I.e., receive buffer is full) er a character has been transmitted (transmit buffer is empty). Jumper selectable requests can be generated by two. of the programmable timers (PITs), and six lines are. reuted directly from peripherals to accept carrier detect (4 lines), ring indicater, and the Bell 801 present next digit request lines. Frequency2 (kHz, Software Selectable) Synchronous Interrupt Request Line 1.2288 Dual/Timer Counter (Two Timers Cascaded) Min Ma. Min 1.63~s 53.3ms 3.26~s 18.75 Hz 614.4 kHz 0.0029 Hz M•• 58.25 minutes 307.2 kHz Interfaces - RS232C Interfaces EIA Standard RS232C Signals provided and supported: Carrier detect Receive data Clear to. send Ring indicater Secendary receive data Oata set ready Secondary transmit data Oata terminal ready Request to. send Transmit cleck Transmit data Receive clock Notes: 1. Baud rates shown here are only a sample subset of possible software-programmable rates available.Any frequency from 18.75 Hz to 614.4 kHz may be generated utilizing on·board crystal oscillator and 16·bit programmable interval timer (used here as frequency divider). 2. Frequency selected by 110 writes of appropriate 16·bit frequency factor to Baud Rate Register. Parallel 110 - 8 input lines, 8 output lines, all Signals RS232C cempatible Bus - All signals iSBC 80 bus compatible 8-3 iSBC 534 I/O Addressing Physical Characteristics The USART, interval timer, Interrupt controller, and parallel interface registers of the iSBC 534 are can· figured as a block of 16110 address locations. The loca· tion of this block is jumper selectable to begin at any 16·byte 1/0 address boundary (i.e., OOH, 10H, 20H, etc.). Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 14 oz (398 gm) I/O Access Time Average DC Current Electrical Characteristics 400 400 400 400 ns ns ns ns USART registers Parallel 1/0 registers Interval timer registers Interrupt controller registers Voltage Compatible' Connectors/Cable Interface Bus Serial and paralielliO Pins (qty) Centers (In.) 86 0.156 26 0.1 Mating Connectors Viking 3KH43/9AMK12 3M 3462·000 or TI H312113 Without Opto·lsolators With Opto·lsolators' Vee = +5V 1.9 A, max 1.9 AI max VOO= +12V VAA= -12V 275 mA, max 420 mAo max 250 mA, max 400 rnA, max Note Cable 1. With four 4N33 and four 4N37 opto·isolator packages installed in sockets provided to implement four 20 mA current loop interfaces. N/A Intel ISBC955 Environmental Characteristics Operating Temperature - 0 'C to + 55 'C Compatible Opto·lsolators Function Supplier Reference Manual 9800450·12 - iSBC 534 Hardware Reference Manual (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Part Number Driver, Fairchild General Electric Monsanto 4N33 Receiver Fairchild General Electric Monsanto 4N37 ORDERING INFORMATION Part Number Description SBC 534 Four Channel Communication Ex· pansion Board 8·4 iSBC 544 INTELLIGENT COMMUNICATIONS CONTROLLER • iSBC Communications Controller acting as a single board communications computer or an intelligent slave for communications expansion • Ten programmable parallel I/O lines compatible with Bell 801 Automatic Calling Unit • On·board dedicated 808SA Micro· processor providing communications control and buffer management for four programmable synchronousl asynchronous channels • Twelve levels of programmable interrupt control • Sockets for up to 8K bytes of read only memory • 16K bytes of dual port dynamic readl write memory with on·board refresh • Extended MULTIBUS addressing permits iSBC 544 board partitioning into 16K·byte segments in a 1·megabyte address space • Individual software programmable baud rate generation for each serial 1/0 channel • Three independent programmable interval timerlcounters • Interface control for auto answer and auto originate modem The iSBC 544 Intelligent Communications Controller is a member of Intel's family of single-board computers, memory, I/O, and peripheral controller boards. The iSBC 544 board is a complete communications controller on a single 6.75x 12.00 inch printed circuit card. The on-board 8085A CPU may perform local communications processing by directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous serial I/O ports, RS366 compatible parallel I/O, programmable timers, and programmable interrupt~. 8·5 = - iSBC 544 to coordinate up to four serial channels. Using the iSBC 544 as an intelligent slave, multichannel serial transfers can be managed entirely on-board, freeing the bus master to perform other system functions. FUNCTIONAL DESCRIPTION Intelligent Communications Controller Two Mode Operation - The iSBC 544 board is capable of operating in one of two modes: 1) as a single board communications computer with all computer and communications interface hardware on a single board; 2) as an "intelligent bus slave" that can perform communications related tasks as a peripheral processor to one or more bus masters_ The iSBC 544 may be configured to operate as a stand-alone single board communications computer with all MPU, memory and I/Oelements on a single board. In this mode of operation, the iSBC 544 may also interface with expansion memory and 1/0 boards (but no additional bus masters). The iSBC 544 performs as an intelligent slave to the bus master by performing all communications related tasks. Complete synchronous and asynchronous 1/0 and data management are controlled by the on-board 8085A CPU , II I I SERIAL I/O Architecture - The iSBC 544 board is functionally partitioned into three major sections: 1/0, central computer, and shared dual port RAM memory (Figure 1). The 1/0 hardware is centered around the four Intel 8251A USART devices providing fully programmable serial interfacing. Included here as well is a 10-bit parallel interface compatible with the Bell 801 automatic calling unit, or equivalent. The 1/0 is under full control of the on-board CPU and is protected from access by system bus masters. The second major segment of the intelligent communications controller is a central computer, with an 8085A CPU providing powerful processing capability. The 8085A together with on-board EPROM I ROM, static RAM, programmable timerslcounters, and program- SEAIALIIQ SERIALI/O - SERIALI/O PARAUECil6 - I I I I I I I I I I I PROGRAMMABLE 1/0 I -r------- I-- I I I I I I I I I I I I I I I I I I I I I I I L "I I CENTRAL COMPUTER MULTIBUS Figure 1_ iSBC 544 Intelligent Communications Controller Block Diagram 8-6 16K x8 DYNAMIC RAM iSBC 544 mabie interrupt control provide the intelligence to manage sophisticated communications operations on-board the iSBC 544 board. The timer/counters and interrupt control are also common to the I/O area providing pro· grammable baud rates to the USARTs and prioritizing interrupts generated from the USARTs. The central computer functions are protected for access only by the on· board 8085A. Likewise, the on·board 8085A may not gain access to the system bus when being used as an in· telligent slave. When the iSBC 544 is used as a bus master, the on-board 8085A CPU controls complete system operation accessing on·board functions as well as memory and I/O expansion. The third major segment, dual port RAM memory, is the key link between the iSBC 544 intelligent slave and bus masters managing the system functions. The dual port concept allows a common block of dynamic memory to be accessed by the on·board 8085A CPU and off-board bus masters. The system program can, therefore, utilize the shared dual port RAM to pass command and status information between the bus masters and on·board CPU. In addition, the dual port concept permits blocks of data transmitted or received to accumulate in the on-board shared RAM, minimizing the need for 'a dedicated memory board. Central Processing Unit Intel's powerful 8·bit n·channel 8085A CPU, fabricated on a single, LSI chip, is the central processor for the iSBC 544. The 8085A CPU, is directly software compatible with the Intel 8080A CPU. The 8085A contains six 8·bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs, providing both single and double precision operators. The minimum instruction execution time is 1.45 microseconds. The 8085A CPU has a 16·bit program counter. An external stack, located within any portion of iSBC 544 read/write memory, may be used as a last·in/ first·out storage area for the contents of the program counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls the addreSSing of thi's external stack. This stack provides sub· routine nesting bounded only by memory size. EPROM/ROM Capacity Sockets for up to 8K bytes of nonvolatile read only memo ory are provided on the iSBC 544 board. Read only memo ory may be added in 2K·byte increments up to a maximum of 4K bytes using Intel 2716 EPROMs or Intel 2316E masked ROMS; or in 4K-byte increments up to 8K bytes maximum using Intel 2732 EPROMs. All on·board EPROM/ROM operations are, performed at maximum processor speed. Serial I/O Four programmable communications interfaces using Intel's 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) are contained on the board and controlled by the on·board CPU in combination with the ,on·board interval timer/counters to provide all common communication frequencies. Each USART can be programmed by the system software to individually select the desired asynchronous or synchronous serial data transmission technique (including IBM Bi. Sync.). The mode of operation (i.e., synchronous or asynchronous), data format, control character format, parity, and baud rate are all under program control. Each 8251A pro· vides full duplex, double·buffered, transmit and receive capability. Parity, overrun, and framing error detection are all incorporated in each USART. Each channel is fully buffered to provide a direct interface to RS232C compatible terminals, peripherals, or synchronous/asynchronous modems. Each channel of RS232C command lines, serial data lines, and signal ground lines are brought out to 26·pin edge connectors that mate with RS232C flat or round cable. An optional iSBC 530 teletypewriter adapter provides an optically isolated inter· face for those systems requiring a 20mA current loop. RAM Capacity The iSBC 544 contains 16K bytes of dynamic read/write memory using Intel 2117 RAMs. Power for the on·board RAM may be provided on an auxiliary power bus, and memory protect logic is included for RAM battery backup requirements. The iSBC 544 contains a dual port controller, which 'provides dual port capability for the on· board RAM memory. RAM accesses may occur from either the on·board 8085A CPU or from another bus master, when used as an intelligent slave. Since onboard RAM accesses do not require the MULTIBUS, the bus is available for concurrent bus master use; Dynamic RAM refresh is accomplished automatically by the iSBC 544 for accesses originating from either the CPU or from the MULTIBUS: AddreSSing - On board RAM, as seen by the on-board 8085A CPU, resides at address 8000·BFFF. On ·board RAM, as seen by an off-board CPU, may be placed on any 4K·byte address boundary. The iSBC 544 provides extended addressing jumpers to allow the on·board RAM to reside within a one megabyte address space when accessed via the MULTIBUS. In ~ddition, jumper options are provided which allow the user to protect 8K· or 12K·bytes of on-board RAM for use by the on-board 8085 CPU only. This reserved RAM space is not acces· sible via the MULTIBUS and does not occupy any system address space. Parallel 110 Port The iSBC 544 provides a 10·bit parallel I/O interface controlled by an Intel 8155 Programmable Interface (PPI) chip. The parallel I/O port is directly compatible with an Automatic Calling Unit (ACU) such as the Bell" Model 801, or equivalent, and can also be used for auxiliary fun· ctions. All signals are RS232C compatible, and the interface cable signal aSSignments meet RS366 specifications. For systems not requiring an ACU interface, the parallel I/O port can be used for any general purpose inierface requiring RS232C compatibility. Stalic RAM - The iSBC 544 board also has 256 bytes of static RAM located on the Intel 8155 PPI. This memory is only accessible to the -on·board 1i085A CPU and is located address 7FOOH·7FFF H. 8-7 iSBC 544 Programmable Timers Table 1_ Programmable Timer Functions The iSBC 544 board provides seven fully programmable and independent interval timer/counters utilizing two Intel 8253 Programmable Interval Timers (PIT), and the Intel 8155. The two Intel 8253 PITs provide six independent BCD or binary 16-bit interval timer/counters and the 8155 provides one 14-bit binary timer/counter. Four of the PIT timers (BDGO-3) are dedicated to the USARTs providing fully independent programmable baud rates. Function Three General U·se Timers - The fifth timer (BDG4) may be used as an auxiliary baud rate to any of the four USARTs or may alternatively be cascaded with timer six to provide extended interrupt intervals .. The sixth PIT timer/counter (TINT1) can be used to generate interrupt intervals to the on-board 8085A. In addition to the timer/ counters on the 8253 PITs, the iSBC 544 has a 14-bit timer available on the 8155 PPI providing a third general use timer/counter (TINTO). This timer output is jumper selectable to the interrupt structure of the on-board 8085A CPU to provide additional timer/counter capability. Timer Functions - In utilizing the iSBC 544 board, the systems designer simply configures, via software, each timer independently to meet systems requirements. Whenever a given baud rate or interrupt interval is needed, software commands to the programmable timers select the desired function. The on-board PIT together with the 8155 provide a total of seven timer/counters and six operating modes. Mode 3 of the 8253 is the primary operating mode of the four dedicated USART baud rate generators. The timer/counters and useful modes of operation for the general use timer/counters are shown in Table 1. Interrupt Capability The iSBC 544 board provides interrupt service for up to 21 interrupt sources. Any of the 21 sources may interrupt the intelligent controller, and all are brought through the interrupt logic to 12 interrupt levels. Four interrupt levels are handled directly by the interrupt processing capability of the 8085A CPU and eight levels are serviced from an Intel 8259 Programmable Interrupt Controller (PIC) routing an interrupt request output to the INTR input of the 8085A (see Table 2). Operation Counter Interrupt on When terminal count Terminal Count is reached, an inter(ModeO) rupt request is generated. This function is useful for generation of real-time clocks. 8253 TINT1 Rate Generator Divide by N Counter. (Mode2) The output will go low for one input clock cycle and high for N-1 input clock periods. 8253 BDG4* Square-Wave I Output will remain Rate Generator high until one-half the (Mode 3) TC has been completed, and go low for the other half of the count. This isthe primary operating mode used for generating Baud rate clocked to the USARTs. 8253 BDGO-4 TINT1 Software Triggered Strobe (Mode4) When the TC is loaded, the counter will begin. On TC the output will goe low for one input clock period. 8253 BDG4* TINT1 Single Pulse Single pulse when TC reached. 8155 TINTO Repetitive Single Pulse Repetitive Single pulse each-time TC is reached until a new command is loaded. 8155 TINTO • BDG4 is jumper selectable as an auxiliary baud rate generator to the USARTs or as a cascaded output to TI NT1. BDG4 may be used in modes 2 and 4 only when configured as a cascaded output. Table 2_ Interrupt Vector Memory Locations Vector Location Interrupt Source Interrupt Sources - The 21 interrupt sources originate from both on-board communications functions and the Multibus. Two interrupts are routed from each of the four USARTs (8 interrupts total) to indicate that the transmitter and receiver are ready to move a data byte to or from the on-board CPU. The PIC is dedicated to accepting these 8 interrupts to optimize USART service request. One of eight interrupt request lines are jumper selectable for direct interface from a bus master via the system bus. Two auxiliary timers (TINTO from 8155 and TINT1 from 8253) are jumper selectable to provide general purpose counter/timer interrupts. A jumper selectable Flag Interrupt is generated to allow any bus master to interrupt the iSBC 544 by writing into the base address of the shared dual port memory accessable to the system. The Flag Interrupt is then cleared by the iSBC 544 when the on-board processor reads the base address. This interrupt provides an interrupi link between Interrupt Level Power Fail TRAP 8253 TINT1 8255TINTO RST7.5 24H 3C H 2 Ring Indicator (1) Carrier Detect RST6.5 34 H 3 RST5.5 Flag Interrupt INTO/-INT7/ (1 of 8) 34 H 4 Programmabie 5-12 RXRDYO TXRDYO RXRDY1 TXRDY1 RXRDY 2 TXRDY2 RXRDY3 TXRDY3 INTR 1 (1) Four ring indicator interrupts and four carrier detect· interrupts are summed to the RST 6.5 input. The 8155 may be interrogated to inspect anyone of the eight Signals. 8-8 iSBC 544 a bus master and intelligent slave (See System Programming). Eight inputs from the serial ports are monitored to detect a ring indicatorand carrier detect from each of the four channels. These eight interrupt sources are summed to a single interrupt level of the 8085A CPU. If one of these eight interrupts occur, the 8155 PPI can then be interrogated to determine which port caused the interrupt. Finally, a jumper selectable Power Fail Interrupt is available from the Multibus to detect a power down condition. mode, no other bus masters may be configured in the system. Memory may be expanded to a 65K byte capacity by adding user specified combinations of RAM boards, EPROM boards, or combination boards. Input! output capacity may be increased by adding digital I/O and analog I/O expansion boards. Furthermore, multiple iSBC 544 boards may be included in an expanded system using one iSBC 544 board as a single board communications computer and additional controllers as intelligent slaves. 8085 Interrupt - Thirteen of the twenty-one interrupt sources are available directly to four interrupt inputs of the on-board 8085A CPU. Requests routed to the 8085A interrupt inputs, TRAP, RST 7.5, RST 6.5 and RST 5.5 have a unique vector memory address. An 8085A jump instruction at each of these addresses then provides software linkage to interrupt service routines located independently anywhere in the Memory. All interrupt inputs with the exception of the TRAP may be masked via software. System Programming In the system programming environment, the iSBC 544 board appears as an additional RAM memory module when used as an intelligent slave. The master CPU communicates with the iSBC 544 board as if it were just an extension of system memory. Because the iSBC 544 board is treated as memory by the system, the user is able to program into it a command structure which will allow the iSBC 544 board to control its own I/O and memory operation. To enhance the programming of the iSBC 544 board, the user has been given some specific tools. The tools are: 1) the flag interrupt, 2) an on-board RAM memory area that is accessible to both an offboard CPU and the on-board 8085A through which a communications path can exist, and 3) access to the bus interrupt line. 8259 Interrupts - Eight interrupt sources signaling transmitter and receiver ready from the four USARTs are channeled directly to the Intel 8259 PIC. The PIC then provides vectoring for the next eight interrupt levels. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC accepts transmitter and receiver interrupts from the four USARTs. It then determines which of the incoming requests is of highest priority, determines whether this request is of higher priority than the level currently being serviced, and, if appropriate, issues an interrupt to the CPU. The output of the PIC is applied directly to the INTR input of the 8085A. Any combination of interrupt levels may be masked, via software, by storing a single byte in the interrupt mask register of the PIC. When the 8085A responds to a PIC interrupt, the PIC will generate a CALL instruction for each interrupt level. These addressses are equally spaced at intervals of 4 or 8 (software selectable) bytes. Interrupt response to the PIC is software programmable to a 32- or 64-byte block of memory. Interrupt sequences may be expanded from this block with a single 8085A jump instruction at each of these addresses. Flag Interrupt - The Flag Interrupt is generated anytime a write command is performed by an off-board CPU to the base address of the iSBC 544 board's RAM. This interrupt provides a means for the master CPU to notify the iSBC 544 board that it wishes to establ ish a communicationssequence. In systems with more than one intelligent slave, the flag interrupt provides a unique interrupt to each slave outside the normal eight MULTI BUS interrupt lines (INTO/·INT7/). On-Board RAM - The on-board 16K byte RAM area that is accessible to both an off-board CPU and the on-board 8085A can be located on any 4K boundary in the system. The selected base address of the iSBC 544 RAM will cause a flag interrupt when written into by an off-board CPU. Bus Access - The third tool to improve system operation as an intelligent slave is access to the Multibus interrupt lines. The iSBC 544 board can both respond to interrupt signals from an off-board CPU, and generate an interrupt to the off-board CPU via the MULTIBUS. Interrupt Output - In addition, the iSBC 544 board may be jumper selected to generate an interrupt from the onboard serial output data (SOD) of the 8085A. The SOD signal may be jumpered to anyone of the 8 MULTI BUS interrupt lines (INTO/-INT7/) to provide an interrupt signal directly to a bus master. System Development Capability Power· Fail Control The development cycle of iSBC 544 board based products may be significantly reduced using the Intellec series microcomputer development systems. The Intellec resident macroassembler, text editor, and system monitor greatly simplify the deSign, development and debug of iSBC 544 system software. An optional ISIS-II diskette operating system provides a linker, object code locater, and library manager. A unique in-circuit emulator (ICE-85) option provides the capability of developing and debugging software directly on the iSBC 544 board. . Control logic is also included to accept a power-fail interrupt in conjunction with the AC-Iow signal from the iSBC 635 Power Supply or equivalent. Expansion Capabilities When the iSBC 544 board is used as a single board communications controller, memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS™ compatible expansion boards. In this 8-9 iSBC 544 On:BoardDynamic RAM (MULTIBUS access) - any 4K increment OOOOO·FFOOO which .is switch and jumper selectable. 4K· 8K· or 16K·bytes can be made available tothe bus by switch selection. . SPECIFICATIONS Serial Communications Characteristics Synchronous - . 5·8 bit characters; automatic sync insertion; parity. Asynchronous - .110 Capacity 5·8 bit characters; break character generation; 1, 1V2, or 2 stop bits; false start bit detection; break character detection. Serial - 4 programmable channels using f.our 8251A USARTs. Parallel - 10 programmable lines available fer Bell 801 ACU, .or equivalent use. Two auxiliary jumper selectable signals. Baud Rates Frequency (KHz)~ (Software Seleclable) 307.2 153.6 76.8 55.8 . 38.4 19.2 9.6 .. 4.8 6.98. 110 Addressing Baud Rale (Hz)2 Synchronous Asynchronous -55800 38400 19200 9600 4800 6980 ... 16 19200 9600 4800 3500 2400 1200 600 300 -- On· Board Programmable 110 ... 64 4800 2400 1200 870 600 300 150 75. 110 Port USARTO USART1 USART2 USART3 8155 PPI Nole.: 1) Frequency selected by 110 writes of appropriate 16.bit frequency factor to Baud Rate Register. . DO 02 04 . 06 E9(PorlA) EA(Porl B) EB (Port C) Conlrol 01 03 05 07 E8 Interrupts Addresses for 8259 Registers (Hex netation, 1/0 address space) 2) Baud rates shown here are only a sample subset of possible software programmable rates available.' Any frequency from 18:75 Hz to 614.4 KHz may be generated utilizing on·board crystal oscillator and 16·bit Programmable Interval Timer (used .here as a frequen.cy dlvld~r). E6 1:6 E7 E6 E7 E6 8085ACPU Word Size - Dala 8, .16 or 24 .bits/instruction; 8 bits of data Cycle Time -1.45/usec £.1 % for fastest executable instruciion; i.e. four clock cycles. Clock Rate - 2.76 MHz ± .1% Interrupt request register In·service register Mask register' Command register Block address register Status (polling register) Note: Several registers have the same physical address: Sequence of access and one data bit of the control word determines which register will respond. .' . . .. . Interrupt levels routed te the 8085 CPU automatically vector the processor to unique memory locatlens: 24 TRAP 3C RST7.5 34 RST6.5 2C RST5.5 System Access Time Dual port memory - 740 nsec Nota: Assu"mes no refresh contention Memory Capacity Timers On·Board ROM/PROM - 4K, or 8K bytes of user Installed ROM.or PROM. Addresses for 8253 Registers (Hex'notation, 1/0 address space) On· Board Static RAM - 256 bytes on 8155. On·Board Dynamic RAM (on·board access) - 16K bytes. Integrity maintained during power failure with user· furnished batteries (optional). . Programmable Interrupt Timer One D8 Tinier 0 BDGO D9 Timer 1 BDG1 DA Timer 2 BDG2 DB Control register On·BoardDyanmic.RAM (MULTIBUS access) -4K, 8K, or 16K·bytes available to bus by switch selection. Programmable Interrupt Timer Two :. DC Timer 0 BDG3 DD Timer 1 BDG4 DE Timer2 TINT1 DF Control register'.. ' Memory Addressing On·Board ROM/PROM ...,... O·OFFF (using 2716 EPROMs or 2316E.ROMs); 0·1 FFF (using 2732 EPROMs) Address for 8155 Programmable Timer E8 Control EC Timer(MSB) TINTO ED Timer (LSB) TINTO On·Board Static Ram -256 bytes: 7FOO·7FFF On·Board Dynamic RAM (on·board access) - 16K bytes: 8000·BFFF. - 8·10 iSBC 544 Memory Protect Input frequencies - Jumper selectable reference 1.22BB MHz±.1% (.B14 usec period nominal) or 1.B43 MHz±.1 % crystal (0.542 usec period, nominal) An active-low TTL compatible memory protect signal is brought out on the auxiliary connector which, when asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during the system power-down sequences. Output Frequencies (at 1.2288 MHz) Dual tlmerlcounter (two timers cascaded) Single tlmerlcounter Function Min Ma. Min Ma. Real·time Interrupt Interval 1.63 usee 53.3 usee 3.26 usee 58.25 min Rate Generator (frequency) 18.75 Hz 614.4 KHz 0.00029 Hz 307.2 KHz Bus Drivers Characteristic Sink Current (mA) Data Tri-state 50 Address Trj-state 15 Commands Tri-state 32 Function Interfaces Note: Used as a master in the single board communications computer mode. Serial 1/0 - EIA Standard RS232C signals provided and supported: Receive Data Carrier Detect Ring Indicator Clear to Send Secondary Receive Data' Data Set Ready Secondary Transmit Data * Data Terminal Ready Transmit Clock Request to Send Transmit Data Receive Clock DTE Transmit Clock Physical Characteristics Width: Depth: Thickness: Weight: 30.4B cm (12.00 inches) 17.15 cm (6.75 inches) 1.27 cm (0.50 inch) 3.97 gm (14 ounces) Electrical Characteristics • Optional if parallel 1/0 port Is not used as Automatic Calling Unit. DC Power Requirements Parallel 1/0 - Four inputs and eight outputs (includes two jumper selectable auxiliary outputs). All signals compatible with EIA Standard RS232C. Directly compatible with Bell Model B01 Automatic Calling Unit, or equivalent. MULTIBUS - Compatible with iSBC MULTI BUS. Current Requirements Configuration Vee= +5V +5% (max) VDD= "12VI Voo= -SV131 VAA=-12V ±S% (max) :!: 5% (max) + 5% (max) With4K EPROM (using 2716) Without On· Board Addressing EPROM RAM only(1) All communications to the parallel and serial 1/0 ports, to the timers, and to the interrupt controller, are via read and write commands from the on-board BOB5A CPU. RAM(2) refresh only ICC= 3Arnax max 100 =350mA max IBB=5mAmax IAA= 200mA max 3.3A max 350mA max 5mAmax 200mA max 390mA max 176 rnA max 5mAmax - 390 rnA max 20 rnA max 5mAmax Noles: 1. For operational RAM only. for AUX power supply rating. 2. ForAAM refresh only. Used for battery backup requirements. No RAM accessed. Auxiliary Power 3. Ves is normally derived on· board from V AA. eliminating the need for a Vee supply. If it is desired to supply Ves from the bus. Ihe current requirement is as shown. An auxiliary power bus is provided to allow separate power to RAM for systems requiring battery backup of readlwrite memory. Selection of this auxiliary RAM power bus is made via jumpers on the board_ Environmental Characteristics Connectors Operating Temperature: O°C to 55°C (32°F to 131°F) Relative Humidity: To 90% without condensation Interlace Pins (qty) Center. (In.) Reference Manual Mating Connectors Bus 86 0.156 Viking 3KH43/9AMK12 Parallel 1/0 50 0.1 3M 3415·000 or TI H312125 Serial 110 26 0.1 3M 3462-000 or TI H312113 9800616B - iSBC 544 Intelligent Communication Controller Board Hardware Reference Manual (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number Description iSBC544 Intelligent Communications Controller 8-11 ....... -.::..- Analog I/O Expansion and Signal Conditioning Boards 9 inter iSBX 311 ANALOG INPUT MULTIMODUlE BOARD • Low cost analog input for iSBX MULTIMODULE compatible iSBC boards • 12·bit resolution analog·to·digital converter • 8 differentiall16 single·ended, fault. protected inputs • 0.035% full scale accuracy (11 bits) at 25°C • 20 mV to 5V full scale input range, resistor gain selectable • 18 kHz samples per second through· put to memory • Unipolar (0 to + 5V) or bipolar ( - 5V to + 5V) input, jumper selectable • Connector compatible with iCS 910 Analog Termination Panel The Intel iSBX 311 Analog Input MULTI MODULE board provides simple interfacing of non-isolated analog signals to any iSBC board which has an iSBX compatible bus and connectors .. The single-wide iSBX 311 plugs directly onto the. iSBC board, providing data acquisitionof analog signals from eight differential or sixteen single-ended voltage inputs, jumper selectable. The iSBX 311 MULTIMODULE is connector and pinout compatible with the Intel iCS 910 Analog Signal Conditioning/Termination panel so that field wiring can easily be terminated and current loop-to-voltageconversion resistors can be mounted for current loop analog signal monitoring. Resistor gain selection is provided for both low level (20mv full scale range) and high level (5 volt FSR) signals. Incorporating the latest high quality IC components, the iSBX 311 MULTIMODULE board provides 12 bit resolution, 11 bit accuracy, and a simple programming interface, all on a low cost iSBX MULTIMODULE board. 9-1 iSBX 311 ground. For noisier environments, differential input mode can be configured to achieve 8 separate differential signal inputs, or .16 pseudo-differential inputs. FUNCTIONAL DESCRIPTION The iSBX 311 Analog Input MULTIMODULE board is a member of Intel's. growing family of MULTIMODULE expansion boards, designed to allow quick, easy, and inexpensive expansion for the Intel single board computer product line. The iSBX 311 Analog Input MULTlMODULE Board shown in figure 1, is designed to plug onto any host iSBC microcomputer that contains an iSBX bus connector (P1). The board provides 8 differential or 16single-ended analog input channels that may be jumper-selected as the application requires. The MULTIMODULE board includes a user-configurable gain, and a user-selectable voltage input range (0 to + 5 volts, or - 5 to + 5 volts). The MULTIMODULE board receives all power and control signals through the iSBX bus connector to initiate channel selection, sample and hold operation, and analog-to-digital conversion. Resolution The iSBX 311 MULTIMODULES provide 12-bit resolution with a successive approximation analog-to-digital converter. For bipolar operation ( - 5 to + 5 volts) it provides 11 bits plus sign. Speed The A-to-D converter conversion speed is 35 microseconds (28KHZ samples per second). Combined with the sample and hold, settling times and the programming interface, maximum throughput via the iSBX bus and into memory will be 54 microseconds per sample, or 18 KHZ samples per second, for a single channel, a random channel, or a sequential channel scan. A-to-D conversion is initiated via the ·iSBX connector and programmed command from the iSBC base board. Interrupt on end-of-conversion is a standard feature to ease programming and timing constraints. Input Capacity Sixteen separate analog signals may be randomly or sequentially sampled in single-ended mode with the sixteen input multiplexers and a common HIGH IMPEDANCE BUFFEA AMP GAIN RESISTOR DIFFERENTIAL - TO SINGLE ENDED .--.....J...-..., AMP ANALOG INPUT SIGNALS SIGNAL GROUND ---'"1'---_ GAIN SElECT & DATA LINES OFFSET ADJUST START CONVERSION AND CHANNEl SELECTOR LOGIC Figure 1. iSBX 311 Analog Input MULTIMODULE Board 9·2 AFN·0162BA iSBX 311 Accuracy OUTput Command start conversion. High quality components are used to achieve 12 bits resolution and accuracy of .035% full scale range ± V2 LSB. Offset and gain are adjustable to ± 0.024% FSR ± 1/2 LSB accuracy at any fixed temperature between OOG (gain = 1). See specifications for other gain accuracies. Select input channel and 7654320 Bit Position I C31 Input Channel C21 C1 I CO I INput Data - Read converted data and status (low byte) or Read converted data (high byte). Reads can be with or without reset of interrupt request line (INTRO/). Gain To allow sampling of millivolt level signals such as strain gauges and thermocouples, gain is made configurable via user inserted gain resistors up to 250 x (20 millivolts, full scale input range). User can select any other gain range from 1 to 250 to match his application. Bit Position 7 Low/status Byte I 6 3 5. 4 031 021 01 I DO I 2 0 Istart IEOC lintroll OPERATIONAL DESCRIPTION High Byte The host iSBG microcomputer addresses the iSBX 311 MULTI MODULE board by executing IN or OUT instructions to the iSBX 311 MULTIMODULE as one of the legal port addresses. Analog-to-digital conversions can be programmed in either of two modes: 1. start conversion and poll for end-of-conversion (EOG), or 2. start conversion and wait for interrupt (INTRO/) at end of conversion. When conversion is complete as signaled by one of the above techniques, INput instructions read two bytes (low and high bytes) containing the 12 bit data word plus status information as shown below. Fastest data conversion and transfer to memory can be obtained by dedicating the microcomputer to setting the channel address/starting conversion, polling the status byte for Intra/, and when it comes true, read the two bytes of the conversion and send the start conversion/next channel address command. For multitasking situations it may be more convenient to use the interrupt mode, reading in data only after an interrupt signals end of conversion. SPECIFICATIONS Accuracy - Inputs - 8 differential. 16 single-ended. Jumper selectable. Gain 1 5 50 250 Full Scale Input Voltage Range - - 5 to + 5 volts (bipolar). 0 to + 5 volts (unipolar). Jumper selectable. 101110101091081071061051041 Accuracy at 25°C ± 0.035% ± 0.035 % ±0.035% ±0.035% ± ± ± ± '12 '12 '12 '12 LSB LSB LSB LSB Accuracy at 0 ° to 60°C ±0.23% ±0.28% ±0.76% ±2.70% ± ± ± ± V2 V2 1/2 V2 LSB LSB LSB LSB NOTE: Figures are in percent of full scale reading. At any fixed tern· perature between 0' and SO'C, the accuracy is adjustable to ± 0.035% of full scale. Gain - User-configurable through installation of two resistors. Factory-configured for gain of X1; gain about 250 not recommended. Dynamic Error- ± 0.015% FSR for transitions Gain TC (at Gain tigrade. Resolution - 12 bits over full scale range (1.22 mv at 0-5 v, 5}.1v at 0-20 mv) 9-3 = 1)-54 PPM per degree cen- AFN·01628A iSBX311 Physical Characteristics Offset TC (in percent of FCRI °C)_ 0.0016%. Gain Width - 6.35 cm (2.5 inches) Offset' 1 5 50 250 Height - 2.03 cm (0.80 inch) MULTIMODULE board only 2.82 cm (1.13 inches) MULTIMODULE and iSBC board 0.0016% 0.0022% 0.016% 0.08% Depth - 9.40 cm (3.7 inches) 'Offset is measured in PPM/C 0 with user·supplied gain resis· tors installed. Weight - Input Protection - 30 volts. Electrical Characteristics (from iSBX connector) Input Impedance - Vcc = ± 5 volts (± 0.25V), Icc = 250 mAmax 20 megohms (minimum). Vdd = + 12 volts (± 0.6V), Idd = 50 mAmax Vss = - 12 volts ( ± 0.6V), Iss = 55 mAmax Conversion Speed - 50 microseconds (nominal). Common Mode Rejection Ratio mum). Sample and hold microseconds. 60 db (mini- Environmental Characteristics Operating Temperature (32 ° to 140°C) sample time 15 Shock Tested At - Connectors - Class B Specification Reference Manuals Interface Pins Centers (Qty) in em Mating Connectors P1 iSBX Bus 36 0.1 0.254 iSBC iSBX connector 0.1 3m 3415-000 or 0.254 T1 H312125 or iCS 910 cable J1 8/16 50 142913-001 - iSBX 311 Analog Input MULTIMODULE Board Hardware Reference Manual (NOT SUPPLIED) Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number SBX 311 0 ° to 60°C Relative Humidity - to 90% (without condensation) Aperature - hold aperature time: 120 nanoseconds. channels analog 68.05 gm (2.4 ounces) Description Analog Input MULTIMODULE Board 9-4 iSBX 328 ANALOG OUTPUT MULTIMODULE EXPANSION BOARD • Low cost analog output foriSBX MULTI· MODULE compatible iSBC Boards • 0.035% full scale volage accuracy @ 25°C • 8 channels output, current loop or voltage in any mix • Connector compatible with iCS 910 Analog Termination Panel • Intel design based on UPI control for high density and low cost • 4-20 rnA current loop; 5V unipolar or bipolar voltage output • Programmable offset adjust in current . loop mode. • 12·bit resolution The Intel iSBX 328 MULTIMODULE board provides analog signal output for any iSBC board which has an iSBX compatible bus and connectors. The single-wide iSBX 328 plugs directly onto the iSBC board, providing eight independent output channels of analog voltage for meters, CRT control, programmable power supplies, etc. Voltage output can be mixed with current loop output for control of popular 4-20ma industrial control elements. By using an Intel single chip computer LSI (8041) for refreshing separate sample-hold amplifiers through a single 12 bit DAC, eight channels can be contained on a single MULTIMODULE board, for high density and low cost per channel. High quality analog components provide 12 bit resolution, 11 bit accuracy, and slew rates per channel of 0.1 volt per microsecond. Programming the iSBX 328 MULTlMODULE board is done via a simple two byte protocol over the iSBX bus. Maximum channel update rates are 5KHZ on a single channel to 1 KHZ on all eight channels. Outputs are compatable for screw termination of field wiring on the iCS 910 Analog Signal Conditioning/Termination Panel. 9-5 iSBX 328 FUNCTIONAL DESCRIPTION TIMODULE board status is available via the iSBX bus connector, to determine if the UPI is ready to receive updates to analog output channels. The iSBX 328 MULTIMODULE board, shown in figure 1 is designed to plug onto any host iSBC microcomputer that contains an iSBX bus connector. The board uses an 8041 UPI device to control eight analog output channels that may be user· configured through jumpers to operate in either bipolar voltage output mode (- 5 to + 5 volts), unipolar voltage output mode (0 to + 5 volts), or current loop output mode (4 to 20 mAl applica· tions. Channels may be individually wired for simultaneous operation in both current loop output and voltage output applications. The outputs from 50-pin edge connector J1 on the MULTI· MODULE board are pin-compatible with the iCS 910 Signal Conditioning/Termination Panel. OPERATIONAL DESCRIPTION The host iSBC microcomputer addresses the MULTIMODULE board by executing IN or OUT instructions specifying the iSBX 328 MULTIMODULE as a port address. The UPI on the iSBX 328 is initialized to select whether software or hardware offset is to be used and how many channels will be active. Then a 2 byte transfer to each active channel sets the 12 bit output value, the channel sel.ected and the current or voltage mode. Commands OUTput Command - Interfacing Through the Intel iSBX Bus Initialization of UPI/ISBX 328 7 All data to be output through the MULTIMODULE board is transferred from the host iSBC microcomputer to the MULTIMODULE board via the iSBX bus connector. The UPI device on the MULTIMODULE board accepts the binary digital data and generates a 12-bit data word for the Digital-toAnalog Converter (DAC) and a four bit channel decode/enable for selecting the output channel. The DAC transforms the data into analog signal outputs for either.voltage output mode or current loop output mode. Offsetting of the DAC voltage in current output mode may be performed by the UPI software offset routine or by the hardware offset adjustments included on the board. The MUL- OUTput Command - Data Bytes OBit 7 High Byte 011 010 09 08 Low Byte 00 A3 A2 A1 VIC 1'- 03 02 01 07 06 05 04 . . DAC Data 0= UPI g e·nerates offset. ) 1 SBC generates offset In cu rrent loop mode . DAC 'channel to receive data J = BUFFER AMPLIFIER CURRENT·TO·VOLTAGE AMP r-----, ~ o ~ . }8g~1~~tL DIGITAL·TO ANALOG INTELll 8041A VOLTAGE TO CURRENT CONVERTER 12·81T J1 RESOLUTION ~t-f- UPI" SAMPLE/HOLD CAPACITOR MULTIPLEXER CONTROL OFFSET ITEMP ADJUST MULTI· PLEXER Figure 1. ISBC 328 Analog Output MULTIMODULE Board Block Diagram 9·6 AFN·01627A iSBX 328 INput Command - Status Buller Read Interrupts No interrupts are issued from the iSBX 328 to the host iSBC microcomputer. Data coordination is handled via iSBC software polls of the status buffer. SPECIFICATIONS Outputs - 8 non-isolated channels, each independently jumpered for voltage output or current loop output mode. Output Impedance - 0.1 ohm. Drives capacitive loads up to 0.05 microfarads. (approx. 1000 foot cable) Voltage Ranges - 0 to + 5 volts (unipolar operation) - 5 to + 5 volts (bipolar operation) Temperature Coefficient - 0.005 %/OC Connectors - Current Loop Range-4 to 20 mA (unipolar operation only) Output Current- ± 5 mA mode-bipolar operation) maximum (voltage Pins Centers Interface (Qty) in em P1 iSBX Bus 36 0.1 0.254 50 0.1 0.254 J18/16 channels analog Load Resistance-O to 250 ohms with on-board iSBX power. 1000 ohms minimum with 30 VDC max. external supply Compliance Voltage -12 V using on-board iSBX power. If supplied by user, up to 30 VDC max Width - Slew Rate-0.1 volt per microsecond minimum Eight Channel Update Rate -1 KHz Accuracy- 1.4 cm (0.56 inch) MULTIMODULE board only Depth - 2.82 cm (1.13 inches) MULTIMODULE and iSBC board. Depth - 9.40 cm (3.7 inches) ± ± ± ± 0.025% FSR 0.035% FSR 0.11% FSR 0.22% FSR @25'C @25'C @O't060'C @0' to 60'C Voltage·Bipolar, typical Voltage·Bipolar, maximum Voltage·Bipolar, typical Voltage·Bipolar, maximum ± ± ± ± 0.025% FSR 0.035% FSR 0.10% FSR 0.17% FSR @25'C @25'C @0' to 60'C @O't060'C Current Loop, typical Current Loop, maximum Current Loop, typical Current Loop, maximum ± ± ± ± 0.07% FSR 0.08% FSR 0.25% FSR 0.36% FSR Weight-85.06 gm (3.0 ounces) Ambient Temp Voltage·Unipolar, typical Voltage·Unlpolar, maximum Voltage·Unipolar, typical Voltage·Unipolar, maximum 6.35 cm (2.5 inches) Height - Single Channel Update Rate - 5KHz Accuracy 3m 3415·000 or T1 H312125 or iCS 910 cable Physical Characteristics Resolution -12 bits bipolar or unipolar Mode Mating Connectors iSSC iSSX connector Electrical Characteristics Vcc = ± 5 volts (± 0.25V), Icc = 140 ma max Vdd = 45 ma max = 200 ma max ± 12 volts (± 0.6V), Idd (voltage mode) (current loop mode) @25'C @25'C @O't060'C @O't060'C Vss 9·7 - 12 volts (± 0.6V), Iss = 55 ma max iSBX328 Environmental Characteristics Reference Manuals Operating Temperature _0° 1660 °C (32 ° to 140°C) 142914·001 - iSBX 328 Analog Output MULTI· MODULE Board Hardware Reference Manual (NOT SUPPLIED) Manuals may, be ordered from any Intel sales representative, distributor ,office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051 Relative Humidity-to 90% (without condensation) Shock Tested At - Class B specifications ORDERING INFORMATION Part Number SBX 328 Description Analog Output MULTIMODULE Board 9·8 iSBC 711 ANALOG INPUT BOARD • iSBC 80 and MULTIBUS compatible • Programmable gain amplifier • Up to 16 differential/32 single-ended non-isolated inputs • 12-bit AID converter • Fault protection on all inputs • Memory mapped 1/0 • Voltage or current loop input • Single + 5V supply The iSBC 711 Analog Input Board is a complete single board Input subsystem which allows easy interfacing of high level analog input signals to Intel's complete line of iSBC 80 single board computers. The iSBC 711 performs the basic functions of data acquisition of analog input signals under microprocessor control. The ISBC 711 consists of 8 differential/16 single ended channel multiplexer, input protection circuits, programmable gain amplifier, sample and hold amplifer, 12·bit AID converter, DC to DC converter, memory mapped interface, and control logic. 9-9 iSBC 711 FUNCTIONAL DESCRIPTION 12-Bit AID Converter The AID converter is a 12-bit 35 JAS successive approximation device with sample and hold amplifier which can be jumper selected for 0 \0 + 5V, 0 to + 10V, ± 5V, and ± 10V input ranges. AID conversion can be initiated by external trigger, pacer clock, or programmed I/O. Interrupt on conversion or end of scan is a standard feature. The external trigger is useful when the AID conversion is to be synchronized to some external event. The internal pacer clock (10 ranges jumper selectable from 976 ,..s to 1 sec) allows precise, evenly spaced AID conversions where signal reconstruction is required. The iSBC 711 is electrically and mechanically compatible with the iSBC 80 series single board computers. Programming compatibility is also maintained with the iSBC 732 Analog Combination I/O Board. A block diagram of the iSBC 711 Analog Input Board is shown in Figure 1. Input Capacity The iSBC 711 contains an 8 differential or 16 single ended analog input multiplexer. Optionally, the iSBC 711 can be expanded up to 16 differential or 32 single ended, non-isolated input channels via two plug-in multiplexers (Part No. Harris H1818A). OPERATIONAL DESCRIPTION Analog Input Fault Protection The iSBC 711 has three modes of operation for acquisi: tion of analog inputs. These are: All input channels are protected up to ± 28V via diode clamping, together with fusible current limit resistors, limiting potentially destructive overloads under fault conditions. 1. Repetitive single channel input 2. Sequential input scan 3. Random channel input Current Loop Input Repetitive Single Channel Input..,... The channel is selected by a write to the multiplexer address register (MAR). The initiation·ol the first conversion is stated by a write to the command register (CR). Setting the appropriate bits in the command register allows stop/start, pacing, external trigger. Subsequent conversions are initiated by read of the AID register (ADCR), or by another write to the command register. The differential input channels have provisions for up to 16 user supplied 250-ohm resistors to apcept 4 to 20 mA current loop inputs. Programmable Gain Amplifier The programmable gain amplifier allows gains of 1,2,4, and 8 to be specified under program control. PROVISION FOR CUSTOMER SUPPLIED CURRENT LOOP RESISTORS MULTIBUS '5V Figure 1. iSBC 711 Analog Input Board Block Diagram 9-10 iSBC711 the 8080's 16-bit memory reference instructions can be used. The AID converter is addressed as memory: base plus specific address. The base address is factory set at F700H and is jumper selectable. Table 1 shows ad· dress: Sequential Input Scan - This mode is initiated in the same manner as the repetitive single channel, except bit 1 of the command register (CR) is set to a "1" on the write command. Random Input Scan - This mode is initiated in the same manner as repetitive single channel input; subse· quent channels are selected by a write to the multi· plexer address register (MAR) before a read of the cur· rent converted value from the ADCR register. Address Base Base Base Base Base Base Base Base Addressing +0 +0 +1 +1 +2 +3 +4 +5 Function Command Write Read Write Read Write Write Read Read Write to command register Read status register Write to multiplexer address register Read multiplexer addres,s register Write to last channel register Clear interrupts Read LS byte of AID data Read MS byte of AID data The iSBC 711 utilizes a memory mapping techniCjJue which simplifies programming in transferring 12-bit data. Since the iSBC 711 interfaces as memory, any of Table 1. Address Commands and Functions SPECI FICATIONS Status Register (Read Base Multiplexer Address Register (MAR) (Write Base + 1) 6 Bit Bit 7 6 Gain selo.lIon End-ol-conversion status End-of-scan status - - - - - ' End of conversion interrrupt enable End of scan interrupt enable - - - - - ' Board busy - - - - - - - - - - - - ' External trigger enabled - - - - - - : - - - - - - - ' AutO-increment enabled - - - - - - - - - - - ' Conversion enabled - - - ' - - - - - - - - - - - - - - - ' Xl I:XG2!100i1i----.l X4 1 XB 1 + 0) Not used + 3) Clear Interrrupt (Write Base AID Converter Register (ADCR) I Clear EOC interrupt Clear EOS· interrupt _ _ _ _ _ _ _...J 2 I Clear RTC interrupt - - - - - - - - - - - - - ' . 6 o 3 Last Address Register (LAR) (Write Base + 2) I I I I I ~ Select channel 1 of 32 Command Register (CR) (Write Base ----.~~. Analog Input + 0) Number 01 Input Channels - 8 differential or 16 single· ended (jumber selectable); expandable from 8/16 to 16/32 using two plug·in multiplexers (Part No. Harris H1818A). I I End-of-conversion interrupt End of scan interrupt Clear busy - - - - - - - - - - - - ' External trigger enable _ _ _ _ _ _ _ _........J Resolution - 12 bit bipolar or unipolar Sample and Hold Aperture Time - <20 ns Sample and Hold Uncertainty - 5 ns Multiplexer Input Voltage Ranges Auto-increment enable - - - - - - - - - - - - - ' Enable - - - - - - - - - - - - - - - - - - ' 9-11 iSBC711 X 1 2 4 8 Connectors AID Input Range Gain +5V +10V +5V +2.5V 1.25V 0.625V + 10V +5V +2.5V + 1.25V ±5V ±10V ±5V ± 10V ±2.5V ± 1.25V ± 0.625V ±5V ±2.5V ± 1.25V . Jumper .electable I "", 100M ohms Input Current Range - 0-20 mA using 250'ohm user installed resistors .~t~ . Interface Pins: (qty) PI iSBC Bus 86 0.156 P2 ± 15V Auxiliary power 60 0.1 Jl Not used 50 0.1 3M3415-000 or TIH312125 J2 1st 8/16 input channels 50 0.1 3M3415-000 or TIH312125 J3 Expander 8/16 input channels 50 0.1 3M3415-000 or TIH312125 In. Viking 3KH43/9AMK12 Compatible Boards and Systems iSBC 80105 iSBC 80/10 iSBC 80/20 System 80/10, and System 80/20-4 Source Impedance Balanced: <5000 ohms Unbalanced: <1000 ohms Overall Accuracy @ 25°C 0.05% FSR ± V2 LSB (gain x 1) 0.07% FSR ± V2 LSB (gain x 2, x 4, x 8) Physical Characteristics (Includes 3 sigma noise, linearity, offset gain, and dynamic response errors.) Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15cm) Depth - 0.5 in. (1.27 cm) Weight - 1 Ib (454 gm) Temperature Coefficient 0.0025% FSR/oC (gain x 1) 0.0030% FSR/oC (gain x 2, x 4, x 8) Electrical Characteristics AID Conversion Speed - Mating Connectors em Power supply - +5V±5%, 1.7A max 28 kHz Environmental Characteristics Throughput Reference Sample Rate (Single Channel) - 17 kHz Channel to Channel Rate - 16kHz Common Mode Rejection (CMR) - 60 dB differential input Common Mode Voltage (CMV) ± 10.24V (signal and common mode) Input Over-Voltage Protection - ± 28V DC, peak AC continuous External Trigger - TTL compatible, 1.5 ,..s (min) better than 50 ns riselime Operating Conditions Temperature DC supply o to 95% exceed upper limit 40°C dewpoint + 5V± 5% + 5V±5% N/A Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. n = 0 through 10 ORDERING INFORMATION Description - 25 to 85°C Reference Manuals 2n Analog Input Board Transportation and Storage Limits 9800485A - iSBC 711 Hardware Reference Manual (NOT SUPLlED) Divider gives range of 1000 ms Part Number o to 55°C o to 95% not to Relative humidity Pacer Clock Crystal controlled accuracy 0.05% SBC 711 25± 0.2°C Operative Limits 9-12 iSBC 724 ANALOG OUTPUT BOARD • Compatible with iSBC 80 series and MULTIBUS bus • Memory Mapped 110 • Four independent 12-bit D/A converters • Unipolar or bipolar with 0 to + 10V, o to + 5V, ± 10V ranges • Accuracy: 0.05% FSR • Short circuit protection on voltage output • Single + 5V supply The iSBC 724 Analog Output Board is a complete single board analog output subsystem which allows easy interfacing of analog outputs from Intel's complete line of iSBC 80 series single board computers to voltage actuated devices or control elements. The iSBC 724 board contains four independent 12-bit digital to analog (D/A) converters and associated voltage output amplifiers, 8-bit holder register, DC to DC converter, memory mapped interface, and controillogic. 9-13 iSBC 724 FUNCTIONAL DESCRIPTION Addressing The iSBC 724 utilizes a memory mapping technique which simplifies programming in transferring 12-bit data. Since the iSBC 724 interfaces as memory, any of the 8080's memory reference instructions can be used. Each independent D/A converter is addressed as memory; base plus specific address. The base address is factory set at F708H which is jumper selectable. Table 1 shows addressing: The iSBC 724 is electrically and mechanically compati; ble with the iSBC 80 series single board computers. Programming compatibility is also maintained with the analog output provided on the iSBC 732 analog 1/0 board. Each individual D/A converter can be jumper selected for a to + 5V, a to + 10V, ± 5V, ± 10V. Short circuit protection for voltage outputs is a standard feature suitable for many display and control applications. A block diagram of the iSBC 724 analog output board is shown in Figure 1. Table 1. Address Commands and Functions OPERATIONAL DESCRIPTION Data Transfer Data transfer to a 12-bit D/A converter is accomplished by a write of the least significant 4 bits to the holding register. When the 8 remaining bits of the upper byte are transferred, the 12 bits of data are immediately loaded into the specific D/A converter channel. Address Command Function Base + 0 Base + 1 Base + 2 Base + 3 Base+4 Base+5 Base+6 Base+7 Write Write Write Write Write Write Write Write Write to DAC holding register Write to DAC a Write to DAC holding register Write to DAC 1 Write to DAC holding register Write to DAC 2 Write to DAC holding register Write to DAC 3 MULTIBUS Figure 1. iSBC 724 Analog Output Board Block Diagram 9-14 isec 724 SPECI FICATIONS Compatible Boards and Systems iSBC 80/05 iSBC 80/10 ISBC 80/20 System 80/10 System 80/20-4 Registers o LSB LS byte 01 data Physical Characteristics o LSB Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 1 Ib, 2 oz (511 gm) Write +1 (high byle) ';;:::::::;;:~:;;:~~~v~:;;;::~~~~~:::~ Sign MSB 8 dala bits (high byle) Analog Output Electrical Characteristics + 5V ± 5%, 2.0A max Number of Channels - 4 non-isolated Resolution - 12 bits bipolar or unipolar (switch selectable) Voltage Output Characteristics Voltage Output Ranges - 0 to + 5V, 0 to + 10V, Power Supply - Environmental Characteristics Reference Operating Conditions ± 5V, ± 10V (jumper selectable) Output Current - Temperature Relative humidity ± 5. mA @ ± 10V Output Impedance - 0.2 ohm Slew Rage - 25± 2.0'C DC supply a to 55'C o to 95% Transportation and Storage - 25 to 85'C a to 95% not to exceed upper limit 40'C dewpoint 10V/p.s Accuracy @ 25°C - 0.05% FSR (includes linearity and noise) Operative Limits +5±S% +5V±5% N/A Temperature Coefficient - 0.005/°C Reference Manuals Connectors Pin. (qty) In. em PI iSBC Bus 86 0.156 0.396 P2 ±.15V auxiliary power 60 0.1 0.254 Jl 4 channels of analog output 50 0.1 0.254 Inlerlace Centers 9800486A - iSBC 724 Hardware Reference Manual (NOT SUPPLIED) Mating Connectors Viking 3KH43/9AMK12 Reference manuals are shipped with each product only if deSignated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. 3M 3415-000 or TI H312125 ORDERING INFORMATION Part Number Description SBC 724 Analog Output Board 9-15 iSBC 732 ANALOG COMBINATION 110 BOARD • iSBC 80 and MULTIBUS compatible • Programmable gain amplifier • 12'bit, 28kHz AID converter • Up to 16 differential/32 single ended non· isolated inputs • Two 12·bit D/A converter output channels • Fault protection on all inputs • Memory mapped I/O • Voltage or current loop input/output . • Single + 5V supply The iSBC 732 is a complete single board analog input/output subsystem which allows easy interfacing of high level analog input and output signals to Intel's complete line of iSBC 80 series single board computers. The iSBC 732 performs the basic functions of data acquisition of analog inputs and controlled analog output signals under microprocessor control. 9-16 iSBC732 FUNCTIONAL DESCRIPTION Programmable Gain Amplifier The iSBC 732 is electrically and mechanically compatible with the iSBC 80 series single board computers. Programming compatibility is also maintained with the iSBC 711 Analog Input Board and the iSBC 724 Analog Output Card. A block diagram of the iSBC 732 Combination Analog 1/0 Board is shown in Figure 1. The programmable gain amplifier allows gains of 1, 2, 4, and 8, to be specified under program control. Input Capacity ISBC 732 contains an 8 differential or 16 single ended analog Input multiplexer. Optionally, the iSBC 732 can be expanded up to 16 differential or 32 single ended, non-isolated input channels via two plug-In multiplexers (Part No. Harris H1818A). Fault Protection All input channels are protected up to ± 28V via diode clamping, together with fusible current limit resistors, limiting potentially destructive overloads under fault conditions. Current Loop Input The differential input channels have provisions for up to 16 user supplied 250-ohm resistors to accept 4 to 20 mA current loop inputs. 12·Bit AID Converter The AID converter is a: 12-bit, 34 ",s successive approximation device with sample and hold amplifier which can be jumper selected for 0 to + 5V, 0 to + 10V,"± 5V and ± 10V input ranges. AID conversion can be initiated by external trigger, pacer clock, or programmed 1/0. Interrupt on conversion or end of scan is a standard feature. The external trigger is useful when the AID con: version is to be synchronized to some external event. The internal pacer clock (10 ranges jumper selectable from 976 to 1 sec) allows precise, evenly spaced AID conversions where signal reconstruction is required. "'S D/A Converter The dual 12-bit non-isolated D/A converter can be configured for voltage or current loop outpout. Each D/A converter voltage output can be juniper selected for 0 to + 5V, 0 to + 10V, ± 5V; ± 10V, or optionally 0 to 20 mA current loop output. Short circuit protection for voltage outputs is a standard feature and user supplied compliance voltage of up to 30V make the current loop output suitable for many control applications. J1 PROVISION FOR CUSTOMER SUPPLIED CURRENT LOOP RESISTORS +5V Figure 1. ISBC 732 Analog Comblnallon I/O Board Block Diagram 9·17 iSBC732 OPERATIONAL DESCRIPTION Analog Output Analog Input Data transfer to a D/A converter is accomplished by a write command of the least significant 4 bits to the holding register. When the upper byte is transferred, the 12 bits of data are immediately loaded to the specific D/A channel. The iSBC 732 has three modes of operation for acquisi: tion of analog inputs. These are: 1. Repetitive single channel input 2. Sequential input scan 3. Random channel input Addressing The iSBC 732 utilizes a memory mapping technique which simplifies programming in transferring 12,bit data. Since the iSBC 732 interfaces as memory, any of the 8080's memory reference instructions can be used. The AID and independent D/A converters are addressed as memory: base plus specific address. The base address is set at F700H which is jumper selectable. Table 1 shows addressing. Repetitive Single Channel Input - The channel is selected by a write to the multiplexer address register' (MAR). The initiation of the first conversion is started by a write command to the command register (CR). Setting the appropriate bits in the command register allow stop/start, pacing, external trigger. Subsequent conversions are initiated by a read command of the AID register (ADCR). Table 1_ Address Commands and Functions Address Sequential Input Scan - This mode is initiated in the same manner as the repetitive single channel, except bit 1 of the command register (CR) is set to a "1" on the write command. Base Base Base Base Base Base Base Base Base Base Random Input Scan - This mode is initiated in the same manner as repetitive single channel input. Subsequent channels are selected by a write command to the multiplexer address register (MAR) before a read command of the current converted value from the ADCR register. Base Base +0 +0 +1 +1 +2 +3 +4 +5 +8 +9 +A +B Function Command Write Read Write Read Write Write Read Read Write Write Write Write Write to command register Read status register Write to multiplexer address register Read multiplexer address register Write to last channel register Clear interrupts Read LS byte of AiD data Read MS byte of AID data Write to DAC holding register (low byte) Write to DAC 0 (high byte) Write to DAC holding register (low byte) Write to DAC 1 (high byte) o LSB SPECIFICATIONS Write +9 Multiplexer Address Register (MAR) Write Bit 7 Gain selection (high byte) Bit 6 Sign MSB 8 data bits (high byte) X1 X2 0 channels X4 X8 Command Register (CR) (Write Base + 0) Not used o LSB Ir--T"I--r-----, 11r--r1-..----, 11---'-1---'1 AID Converter Register (ADCR) o 6 Read base (low byte) +4 Read base (high byte) +5 .:r. External trigger enable - - - - , . - - - - - - - ' Auto-increment enable - - - - - - - - - - - - - ' Enable conversion _ _ _ _ _ _ _ _-...:_ _-...:_...J Status Register (Read Base 5 + 0) o LSB I 1 1 1 1 1 1 1 1 I End-of-conv ersion status j End-of-scan status End of conv ersion interrrupt enabled End of scan interrupt enabled Board busy External trig ger enabled Auto-increm ent enabled Conversion enabled D/A Hold Register o LSB Write +8 (low byte) II End-of-conversion interrupt _ _ _ _ End of scan interrupt Clear busy _ _ _ _ _ _ _ _ _ _ _---l I I I --,,- DIA31 DIA21 DIA1 DIAO LS byte of data 9-18 J iSBC732 Clear Interrrupt (Write Base + 3) -'1 I Clear EOC interrupt _ _ _ _ _ _ _ Clear EOS interrupt . Clear RTC interrupt - - - - - - - - - ' Common Mode Voltage (CMV) common mode) ± 10.24V (signal and Input Over-Voltage Protection continuous ± 28V DC, peak AC External Trigger - TIL compatible, 1.5 ,..s (min) better than 50 ns risetime Last Address Register (LAR) (Write Base + 2) Pacer Clock Crystal controlled accuracy 0.05% I Divider gives range of 1000 ms Select channel I 01 32 n = 0 through 10 Analog Input Number of Input Channels - 8 differential or 16 single ended (jumper selectable); expandable from 8/16 to 16/32 using two plug-in multiplexers (Part No. Harris H1818A). Analog Output Number of Channels - 2 Non-isolated Resolution - 12 bits bipolar or unipolar (switch selectable) Resolution - 12-bit bipolar or unipolar Sample and Hold Aperture Time - <20 ns Sample and Hold Uncertainty - 5 ns Multiplexer Input Voltage Ranges AID Input Range Gain X 1 2 4 8 +5V +10V ±5V ±10V +5V +2.5V 1.25V 0.625V +IOV +5V +2.5V +1.25V ±5V ±2.5V ±1.25V ±0.625V ±10V ±5V ±2.5V ± 1.25V Voltage Output Characteristics Jumper selectable Voltage Output Ranges - 0 to + 5V, 0 to + 10V, ± 5V, ± 10V (jumper seleciable) Output Current - ± 5 mA @ ± 10V Output Impedance - 0.2 ohm Slew Rate - 10V/,..s with no external capacitance Accuracy @ 2SoC - 0.05% FSR (includes linearity and noise) Temperature Coefficient - 0.005·C } Software programmable Input Impedance Power Off: 680 ohms Power On: >100M ohms Input Current Range installed resistors 0 to 20 mA using 250-ohm user Current Loop Characteristics Current Output - 0 to 20 mA Load Resistance - 0 to 500 ohms Compliance Voltage - Up to 30V DC (provided by u.ser) Accuracy @ 2SoC - 0.075% FSR (includes linearity and noise) Temperature Coefficient - 0.005/·C: Source Impedance Balanced: <5000 ohms Unbalanced: <1000 ohms Overall Accuracy @ 2SoC 0.05% FSR ± V2 LSB (gain x 1) 0.07% FSR ± V2 LSB (gain x 2, x 4, x 8) (Includes 3 sigma noise, linearity, offset gain, and dynamic response errors) Connectors Temperature Coefficient 0.0025% FSR/·C (gain x 1) 0.0030% FSR/·C (gain x 2, x 4, x 8) AID Conversion Speed - Intarlaea PI ISBC Bus Pins (qty) In. Cantars em 86 0.156 0.396 28 kHz Throughput Sample Rate (Single Channel) - 17 kHz Channel to Channel Rate - 16 kHz Common Mode Rejection (CMR) - 60 dB differential input 9·19 Mating Connectors Viking 3KH43/9AMKI2 P2 ± 15V auxiliary power 60 0.1 0.254 Jl 2 channels of analog output J2 1st 8116 input channels 50 0.1 0.254 3M 3415.(J00 or TI H312125 50 0.1 0.254 3M 3415·000 or TI H312125 J3 Expander 8116 input channels 50 0.1 0.254 3M 3425·000 or TI H312125 iSBC,732 Environmental Characteristics Compatible Boards and Systems,' iSBC 80/05 iSBC 80/10 iSBC'80/20 System 80/10 System 80/20-4 Reference 'Operating Conditions Temperature 25± 0,2'C Relative humidity DC supply Physical Characteristics Width - 12,00 in, (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.5 in. (1.27 cm) Weight - 1 Ib 4 oz (568 gm) Description Analog Combination 1/0 Board + 5V± 5% and Storage Limits -25toB5'C 010.95% N/A 9800487·02 - iSBG 732 Hardware Reference Manual (NOT SUPPLIED)' Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor ciffice or from Ihiel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ' ORDERING INFORMATION Part Number Ot055'C Ot095% notto exceed upper Iimit40'C dewpoinl Transportation Reference Manuals Electrical Characteristics Power Supply - + 5V ± 5 %, 2.3A max SBC 732 "T5,V±5~/o Operative Limits 9-20 System Packaging and Power Supplies 10 iSBC 604/614 or (pSBC 604/614*) MODULAR CARDCAGE/BACKPLANE • Interconnection on MULTIBUS system bus and housing for up to four Intel iSBC boards • Cardcage mounting holes facilitate interconnection of units • Strong cardcage structure helps protect installed iSBC single board computers and expansion boards against warping and physical damage • Compatible with 3.5·inch RETMA rack mount increments • Dual backplane power supply connectors and signal line termination circuits on iSBC 604 Cardcagel Backplane • Connectors allow interconnection of two or more cardcage/backplane assemblies The iSBC 604 and iSBC 614 Modular Cardcage/Backplane units provide low-cost, off-the-shelf housing for OEM products using two or more Intel single board computers. Each unit interconnects and houses up to four boards. The base unit, the iSBC 604 Cardcage/Backplane, contains a male backplane PC edge connector and bus signal termination cir· cuits, plus power supply connectors. It is suitable for applications requiring a single unit, or may be interconnected with the iSBC 614 Cardcage/Backplane when more then one cardcage/backplane unit is needed. iSBC 614 Card· cage/Backplane contains both male and female backplane connectors, and may be interconnected with iSBC 604/614 Cardcage/Backplane units. Both units are identical, with the exception of the power connectors and bus signal termi· nator features. A single unit may be packaged in a 3.5-inch RETMA rack enclosure, and two interconnected units may be packaged in a 7-inch enclosure. The units are mountable in any of three planes. The 'Same product, manufactured by Intel Puerto Rico, Inc. 10-1 iSBC 604/614 .660-1 .188 01A. THRU, 3 ~ 1....- - - - 12 .875 I - t +--~. - t I 5500 ~. - . ---f''=-'" I 2.60 J_ 1 8j~ ~II~S8C"'ON~LY~I , IS8C,,'ONLY ~2.85~-B.500.~ I II 2.750 .300~~, SIDE VIEW END VIEW BOTTOM VIEW Figure 1. iSBC 604/614 Modular Backplane and Cardcage Dimensions Physical Dimensions SPECIFICATIONS Backplane Characteristics Bus Lines - All MULTIBUS system bus address, data, and command bus lines are bussed to all four connec· tors on the printed circuit backplane Height - 8.5 in. (21.59 cm) Width - 14.2 in. (36.07 cm) Depth - 3.34 in. (8,48 cm) Weight - 35 oz (992.23 gm) Power Connectors - for ground, + 5V, - 5V, + 12V, - 12V, - 10V power supply lines iSBC 604 - Bus signal terminators, backplane male PC edge connector only, and power supply headers iSBC 614 - Backplane male and female connectors Environmental Characteristics Mating Power Connectors AMP Molex Operating Temperature - Connector 87159-7 Pin 87023-1 Polarizing key 87116-2 Connector 09-50-7071 Pin 08-50-0106 Polarizing key 15-04-0219 O°C to 55°C Reference Manual Note 1. Pins from a given vendor may only be used with connectors from the same vendor. 9800708 - iSBC 604/614 Cardcage Hardware Reference Manual (NOT SUPPLIED) ORDERING INFORMATION Part number Description Part Number SBC 604 Modular Cardcage/Backplane (Base Unit) SBC 614 10·2 Description Modular Cardcage/Backplane (Expansion Unit) iSBC 655 SYSTEM CHASSIS • A rack-mountable package for Intel microcomputer systems • Attractive front panel with control switches and indicator lights • Provides the Intel MULTIBUS structure used on the single board computers • 110V or 220V operation at 50/60 Hz • Compact single chassis power supply with all standard iSBC board voltages • 19-inch rack mountable • Parallel 110 connectors and RS232C cable included • Forced-air cooling The iSBC 655 System Chassis is an attractive 3.5" high unit designed for use in Intel Microcomputer Systems. The Chassis' four slots accommodate both single board computers and expansion boards which provide additional 1/0, memory, or peripheral controller functions. The iSBC 655 System Chassis will accept all Intel boards using the Multibus architecture. DC power is provided at ±.5VDC and ± 12VDC levels, at current levels commensurate with typical combinations of four boards. The chassis is designed to provide adequate cooling to both power supply and circuit boards over external temperatures ranging from DOC to 5DoC. Current limiting and over-voltage protection are provided on all outputs. The power supply recognizes an AC power failure condition and provides a TTL signal sufficiently in advance of DC power failure to allow orderly system shut-down. For user convenience, system RESET and INTERRUPT switches are provided on the front panel to facilitate system restarts and provide for operator intervention. RUN and HALT LED indicators are driven to indicate the operational status of the single board computer. 10-3 iSBC 655 Width - 19 inches (48.3 cm) at Front Panel, 17 inches (43.2 cm) behind Front Panel Depth - 20 inches (50.8 cm) with all protrusions Weight - 37 pounds (17 Kg) SPECIFICATIONS Electrical Characteristics Input Power - Frequency: 47 - 63 Hz. Voltage (Nominal) (Single Phase): 100, 115,215, or 230 VAC +10% Output Power: Nominal Current Current Limit Max Short Voltage (AMPS)(MAX) Range (AMPS) Circuit (AMPS) +12 + 5 - 5 -12 2.0 14.0 0.9 0.8 2.1-3.0 14.7-21.0 0.9-1.4 0.8-1.2 1.0 (Foldback) 7.0'(Foldback) 1.4 1.2 Environmental Characteristics Over-Voltage Protection Temperature - Operating: O°C to 50°C. Non-Operating: -40 o e to 85°C Relative Humidity - Up to 90%, non-condensing +14 to +16 V +5.8 to +6.6 V -5.8 to -6.6 V -14 to -16 V Equipment Supplied iSBC 655 System Chassis with iSBe 635 Power Supply, iSBC Cardcage/Backplane, dual fans, pop-off front panel Connector Pack with RS232C Cable (terminal/modem interface to Single Board Computers), Two 50-pin parallel I/O connectors for Single Board Computers Schematics for Cardcage/Backplane, Chassis Outline Drawing Combined Line/Load Regulation - ±1% at ±10% static line change and ±50% static load change, measured at the output connector (±0.2% measured at the power supply under the same conditions). Remote Sensing - Provided for+5 VDC outputline regulation. Output Ripple and Noise -1 0 mv peak-to-peak maximum (DC to 500 KHz) Output Transient Response - Less than 50 p.sec for ±50% load change Output Transient Deviation - Less than ±5% of initial voltage for ±50% load change. Power Failure Indication (AC Low) - A TTL open collector high signal is provided when the input voltage drops below 90% of its nominal value. DC voltages will remain within 5% of their nominal values for 3.0 milliseconds (minimum, 7.5 ms typical) after AC LOW goes true. Reference Manuals (Not Supplied) 9800709 - iSBC 655 System Chassis Hardware Reference Manual 9800298 - iSBC 635 Power Supply Hardware Reference Manual 9800708 - iSBC 604/614 Card cage Hardware Reference Manual Manuals may be ordered from any Intel Sales Representative, Distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, CA 95051 Physical Characteristics Height - 3.5 inches (8.9cm) 1 - - - - 16100------~1- _ l_ _ ,... ° 1 10 -~- ,-, '::./ I :0 o I I Figure 1. iSeC 655 Dimensions (inches) ORDERING INFORMATION Part Number Description SBC 655 iSBC 655 System Chassis 10·4 0 DO q inter iSBC 660 SYSTEM CHASSIS • Eight-slot cardcage and backplane for iSBC computers ·and expansion boards • Attractive, versatile pop-off front panel • 19-inch wide rack mountable chassis • Heavy duty power supply with all standard iSBC voltages • Horizontal board mounting for compactness • Compatible with all Intel single board computers • Forced-air cooling • 110/220V, 50/60 Hz operation The iSBC 660 System Chassis is an attractive, 7·inch high system chassis designed for use with Intel OEM computers. It has eight slots for single board computers, memory, 110, or other expansion modules. The iSBC 660 is ideal for appli· cations requiring multiple board solutions. DC power output is provided at + 12V, + 5V, -12V, and - 5V levels. The current capabilities of each of these output levels have been chosen to provide power over a O·C to 50·C temperature range for the majority of applications requiring combinations of computers, memories, peripherals, and other 110 capabilities. Current limiting and over·voltage protection is provided at all outputs. Standard logic recognizes a system AC power failure and generates a TTL signal for use in power·down control. For user convenience, a reset switch is provided on the front panel. The reset signal generated and sent to the system bus can be used for external system control. 10·5 iSBC 660 FRONT VIEW 19 00 - -----/'1 1_ - - . 11.38 1 ~_i_'~~l 1-1-mI I I 2.10. q'95~ 1 . I '45 . -1~~8TOP VIEW I 1 o o 18.9 ~ I2.--I37 Ll.25==::J ,,:l.'-,o,J I -':-1 . 3.00 L 0 ,to U. 1 . 16.9 i------,--(CHASSIS DIMENSIONS} Figure 1. iSBC System Chassis Dimensions Provided for + 5 VDC output line SPECIFICATIONS Remote Sensing regulation. Electrical Characteristics Output Ripple and Noise mum (DC to 500 kHz). Input Power Frequency: 50 Hz ± 5%,60 Hz ± 5% Voltage: 115V ± 10%, 230V ± 10%, 215 VAC ± 10%, 100 VAC ± 10% via user configured wiring options Output Transient Response ± 50% load change. Output Current (Max) Current Limit (Amps) Over·Voltage Protection + 12V +5V -5V -12V 4.5A 30A 1.75A 1.75A 504 3.6 2.1 2.1 15V ± 1V 6.2V ",OAV -6.2V ± O.4V -15V ± 1V Less than 50 I'S for Output Transient Deviation - Less than ± 5% of linitial voltage for ± 50% load change. Output Power Power 10 mV peak·to·peak maxi· Power Failure Indication (AC Low) - A TTL open collec· tor high signal is provided when the input voltage drops below 90% of its nominal value. DC voltages will remain within 5% of their nominal values for 3.0 milliseconds (minimum, 7.5 ms typical) after AC Low goes true. The "AC Low" signal will reset to a TTL low level when the AC input voltage is restored and after all output volt· ages are within specified regulation. The "AC Low" threshold is adjustable for optimum power·down performance at other input combinations (I.e. 100 VAC, 215 VAC, 50 Hz). Combined Line/Load Regulation - ± 1% at ± 10% static line change and ± 50% static load change, meas· ured at the output connector (± 0.2% measured at the power supply under the same conditions). 10-6 iSBC 660 Humidity - Up to 90% relative, non-condensing I/O connectors for single board computers Schematics for cardcage/backplane, chassis Outline drawing Physical Characteristics Height - 7 in. (17_8 cm) Width At Front Panel: 19 in. (48.3 cm) Behind Front Panel: 17 in. (43.2 cm) Depth - 20 in. (50.8 cm) with all protrusions Reference Manuals 9800505A - iSBC 660 Hardware Reference Manual (NOT SUPPLIED) Equipment Supplied 9800505 - iSBC 660 System Chassis Hardware Reference Manual (NOT SUPPLIED) 9800803 - iSBC 640 Power Supply Hardware Reference Manual (NOT SUPPLIED) 9800708 - iSBC 604/614 Card cage Hardware Reference Manual (NOT SUPPLIED) iSBC 660 System Chassis with iSBC 640 Power Supply, iSBC 604/614 CardcagelBackplane, dual fans, pop-off front panel Connector pack with RS232C cable (terminal/modem interface to single board computers), two 50-pin parallel Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Environmental Characteristics Temperature Operating: O°C to 50°C Non-Operating: - 40°C to + 85°C ORDERING INFORMATION Part Number Description SBC 660 iSBC 660 system chassis 10-7 iSBC 635 POWER SUPPLY • Compact single chassis • DC power cables and connectors mate directly to iSBC 604 Modular Cardcage/ Backplane assembly • ± 5V and ±12V iSBC 80 and iSBC 86 system power • "AC low" power failure TTL logic level output provided for system power· down control • Sufficient power for one fully loaded Intel single board computer plus residual power for up to three Intel iSBC expansion boards • 100V, 115V, 215V, and 230V AC operation • Current limiting and overvoltage protection on all outputs • 50 Hz or 60 Hz input The iSSC 635 Power Supply provides low cost, off-the·shelf, single chassis power generation for OEM Products using Intel single board computers. The iSSC 635 supply provides regulated DC output power at + 12V, + 5V, - 5V, and -12V levels. The current capabilities of each of these output levels have been chosen to provide power over a O'C to + 55'C temperature range for one Intel single board computer fully loaded with I/O line terminators and drivers and EPROMs, plus residual capability for most combinations of up to three iSSC memory, I/O, or combination expansion boards. Current limiting and overvoltage protection is provided on all outputs. Access for AC input is provided via a standard 4-pin keyed connector. DC output power levels are provided on cables with keyed connectors directly compatible with the iSSC 604 Modular Cardcage/Sackplane assembly. The iSSC 635 supply includes logic whose purpose is to sense system AC power failure and generate a TTL signal for clean system power-down contro\. 10-8 iSBC635 CD HARNESS LENGTHS ARE FADM CENTER OF SURFACE "A" TO CONNECTOR a, DC OUTPUT 24 'Q.SINCHES TO 1'6 CONN b. DC OUTPut 16 '0.5 INCHES TO 1'8 CONN. c. AC INPUT 12 . 0.5 INCHES TO P2CONN. @ LOCATION OF "AC LOW" SIGNAL CONfl:ECTOA IS WITHIN CROSS-HATCHED VOLUME, ORIENTATION MAV VARY. @) ALL FOUR MOUNTING HOLES THREADED FOR 10·24 MACHINE SCREWS ' _ 3 . " MAX $-------------I l I 5,000 Figure 1. iSeC 635 Mounting Information SPECIFICATIONS Electrical Characteristics Mating Connectors 1 Input Power - Frequency: 47 - 63 Hz. Voltage (Nominal) (Single Phase): 100, 115,215, or 230 VAC +10% AC Input 03-09-1042 or equivalent Output Power: 02-09-1118 or equivalent (18 to 22 gauge wire) Current Current Limit Max Short Nominal Over-Voltage Voltage (AMPS)(MAX) Range (AMPS) Circuit (AMPS) Protection DC Output 2 I Header Molex 09·66·1071 AMP 87194·6 Molex 09·50·7071 AMP 87159·7 +12 + 5 - 5 -12 "AC Low" Control Connector Polarizing key I Pin Molex 15·04·0219 AMP 87116·2 Molex 08-50-0106 (18 to 22 gauge wire) AMP 67023·1 (18 to 22 gauge wire) 2.0 14.0 0.9 0.8 2.1-3.0 14.7-21.0 0.9-1.4 0.8-1.2 1.0 (Foldback) +14 to +16 V 7.0 (Foldback) +5.8 to +6.6 V 1.4 -5.8 to -6.6 V 1.2 -14 to -16V Combined Line/Load Regulation - ±1% at ±10% static line change and ±50% static load change, measured at the output connector (±0.2% measured at the power supply under the same conditions). Remote Sensing - Provided for +5VDC output line regulation. Output Ripple and Noise -10 mV peak-to-peak maximum (DC to 500 KHz) Output Transient Response - Less than 50 !,sec for ±50% load change Output Transient Deviation - Less than ±5% of initial voltage for ±50% load change. Power Failure Indication (AC Low) - A TTL open collector high signal is provided when the input voltage drops below 90% of its nominal value. DC voltages will remain within 5% of their nominal values for 3.0 milliseconds (minimum, 7.5 ms typical) after AC Low goes true. Notes 1. Pins from a given vendor may only be used with connectors from the same vendor. 2. iSBC 635 DC output connectors are directly compatible with power input power connectors on iSBC 604 Modular Cardcage/Backplane assembly. Two connectors are provided. Physical Characteristics Height - 3.19 in. max (8.11 cm) Width - 6.03 in. max (15.32 cm) Depth - 12.65 in. max (32.12 cm) Weight - 13 Ib (5.90 kgm) 10-9 iSBC635 The "AC Low" signal will reset to a TTL low level when the AC input voltage is restored and after all output voltages are within specified regulation. Equipment Supplied The "AC Low" threshold is adjustable for optimum powerdown performance at other input combinations (Le. 100 VAC, 215 VAC, 50 Hz). Environmental Characteristics O·C to + 55·C with 35 CFM Operating Temperature moving air Non-Operating - - 40·C to + 85·C ORDERING INFORMATION Part Number Description SBC 635 Power supply 10-10 iSBC 635 Power Supply with AC and DC cables and connectors attached as shown in Figure 1. Reference Manual 9800298C - iSBC 635 Power Supply Hardware Reference Manual (includes schematics) (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. inter iSBC 640 POWER SUPPLY • ± 5V and ± 12V iSBC 80/86 power • Compact single chassis/slide rail mounts in iCS 80 Industrial Chassis or OEM environments • Sufficient power for 8-12 MULTIBUS computer, memory, and peripheral boards • DC power cables and connectors mate iSBC 604 Modular. Cardcage/ directly Backplane assembly to • Current limiting and overvoltage protection on all outputs • "AC low" power failure TTL logic level output provided for system power-down control • 100, 115, 215, and 230V AC operation • 50 Hz or 60 Hz input The iSBC 640 Power Supply provides low cost, ·off-the-shelf, single chassis power generation for OEM and industrial system products using Intel single board computers. The iSBC640 supply provides regulated DC output power at +12V, +SV, -SV and -12V levels. The current capabilities of each of these output levels have been chosen to provide power over a O°C to +SsoC temperature range for one fully loaded Intel single board computer, plus residual capability for most combinations of up to eleven iSBC memory, 1/0, or combination expansion boards. Current limiting and overv?ltage protection is provided on all outputs. Access for AC input is provided via a standard 4-pin keyed connector. DC output power levels are provided on cables with keyed connectors directly compatible ·with the iSBC 604 Modular Backplane/Cardcage assembly. The iSBC 640 supply includes logic whose purpose is to sense system AC power failure and generate a TTL signal for clean system power-down control. 10·11 iSBC 640 SPECIFICATIONS Mating Connectors 1 AC Input Electrical Characteristics 03-09-1042 or equivalent Input Power 02-09-1118 or equivalent (18 to 22 gauge wire) Frequency: 50 Hz±5%, 60 Hz±5% Voltage: 115V ± 10%, 230V ± 10%, 215VAC ± 10%, DC Output 2 100VAC±10.% I Via user configured wiring options Output Power Nominal Voltage Current Limit Short Circuit Range (Amps) (Amps) (Mao) 5V -12V 09-66-10n 87194-6 1. Pins from given vendor may only be used with connectors from the same vendor. Overvoltage Protection 2. iSBC 640 DC outp'ut connectors are directly compatible with input power connectors Ion iSBC 604 Modular Cardcage/Backplane assembly. Four connectors are provided. "-'~r-' - Moleo AMP Notes Current (Amps)(Mao) + 12V + 5V Header 4.5A 30A U5A U5A 4.7- 6.8 31.5-45.0 1.8- 3.2 1.8- 3.2 2.3 15.0 0.9 0.9 15V '" IV 6.2V '" O.4V -6.2V",0.4V -15V '" IV Physical Characteristics Combined Line/Load Regulation - ±1% at ±10% static line change and ±50% static load change, measured atthe output connector (±0.2% measured at the power supply under the same conditions). Remote Sensing regulation. Height Width Depth Weight - Provided for +5 VDC output line 6.66 in_ max. (16.92 cm) 8.19 in_ max. (20.80 cm) 12_65 in. max. (32.12 cm) 30 Ibs. max (13.63 kg) Environmental Characteristics Output Rippleand Noise ..;.10 mV peak-to-peak maximum (DC to 500 KHz) , Temperature - O·C to 55·C with 55' CFM moving air Non-Operating - - 40·C to + 85·C Output Transient Response - Less than 50 J.lsec for ±50% load change. EqL!ipment Supplied Output Transient Deviation - Less than ± 10% of initial voltage for ± 50% load change. iSBC 640 Power Supply with AC and DC cables with keyed connectors. Power Failure Indication (AC Low) - A TTL open collector high signal is provided when the input voltage drops below 90% of its nominal value. DC voltages will remain within 5% of their nominal values for 3.0 milliseconds (minimum, 7.5 ms typical) after AC Lowgoes true. 9800803 - iSBC 640 Power Supply Hardware Reference Manual (includes sphematic and assembly drawings) (SUPPLIED) The "AC Low" signal will reset to a TTL low level when the AC input voltage is restored and after all output voltages are within specified regulation. The "AC Low" threshold is adjustable for optimum powerdown performance at other input combinations (i.e. 100 VAC, 215 VAC, 50 Hz); Reference Manuals 9800798 - iCS 80 Systems Site Planning and InstallationManual (for installation of iSBC 640 supply into iCS 80 Industrial Chassis (NOT SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number Description SBC 640 Power Supply 10·12 Microcomputer Development Systems 11 intel' New dimensions in development solutions. Solutions that deliver the support you need to develop microcomputer based products successfully and economically. No other development system product line supports such a broad range of microprocessor and support chip functionality. No other development system offers such a broad selection of high-level software support and de-bug tools. And no other development system today delivers state-of-the-art development support without obsolescence of previous systems. Evolutionary Growth Every Intellec@developmentsystem delivered since 1975 can easily be upgraded to current standards. Including resident support for 16-bit product development and distributed development solutions. Ease of Entry The new Series II/Model 120 Microcomputer DevelopmentSystem delivers full entry level support at the lowest entry price, while maintaining full upgradability: Unprecedented 16-bit Support The newly introduced Intellec Series III/Model 286 Microcomputer Development System features a resident iAPX 86 16-bit CPU for direct execution of 16-bit Intel software AND a resident 8c bit CPU for execution of all Intel 8-bit microprocessor software. Distributed Development Solutions For larger development projects, Intel delivers NDS-1-the Networked Development System-with up to eight development systems sharing hard disk speed and centralized file resources. Software. Key to Programmer Productivity High level languages and powerful macro assemblers produce linkabl.e and relocatable object modules, allowing the designer to match software strengths to project requirements for optimal development speed and product performance. New introductions include PWM, PASCAL and FORTRAN compilers forthe iAPX family of 16-bit microprocessors. ICE™ Emulation. For Every Processor Intel's family of microprocessors is supported by ICE in-circuit emulation modules for integration of system hardware and software throughout the design cycle. ICE modules feature real-time and single-step trace and debugging. The Development Investment Intellec development tools provide the support you need to manage the complexity of microcomputer product development over the next decade. You invest in a family of support tools that supports, in turn, a comprehensive and cohesive family of processors and peripherals-from digital. signal processors to 8-bit microcontrollers to 16-bit microsystems operating in a multiprocessing environment. And Intel's record of product revolution through product evolution means your development dollars are an investment in today's technology AND tomorrow's technology. 11-1 8080/8085 PERFORMANCE, GUIDE For developing 8080/8085 programs on an 8·blt based Intellec® development system. ~T UPGRADE OPTIONS DEVELOPMENT SYSTEM TODAY'S PERFORMANCE ASM 80/85 V3.0 MODEL 800 SERIES II MODELS 120.220.230 SERIES' , II M~.l6EL . SERiEs 11/85 ' MODELS 225.235 ' SERIES 11/85 ',' MODEL 245 1X 1X 1,4X 1,3X 1,8X ADD NEW ASM SO/85 V4.0 1,7X 1,7X 2.3)( 2.0X· 3.0X ADD MODEL 505 ASM 80/85 V4.0 N/A 2.3X * ADD MODEL 740 ASM 80/85 V4.0 2.0X 2.0X, 3.0X ADD MODEL 505 & MODEL 740 e~ 80/85 .0 N/A I 3.0X , " ... ,. ." '*' 3.0X ' 'I' *The current ,system .Includes this ,option. IAPX 86/88 PERFOR""ANCE GUIDE . For developing IAPX ,86 or 88 programs on ,either an 8"blt or 16·blt based Intellee® development system~ , , DEVELOPMENT ~T SYSTEM UPGRADE OPTIONS ASM ~/88 'TODAY'S PERFORMANCE PL/M 86/88 ADD MODEL 505 ADD MODEL 556 ADD MODEL,556.1 ADD MODEL 740 MODEL 800 1X SERIES II MODELS 120.220.230 SERIES 11/85 MODELS 225.235 SERIES II MODEL 240 SERIES 11/85 ' MODEL .245 1X 1,2X 1.5X 2.1X 1.3X: 1,4X . 2.0X 2.1X ,. . 1X 1X ASM 86/88 N/A 1,2X PLIM 86/88 N/A 1.3X 1,6X 1,6X • ASM 86/88 PL/M 86/88 , ASM 86/88 PL/M 86/88 . ASM 86/88 ., • ·2.7X· 3.1X 2.3X 2.3X 2.4X 3.7X 4.0X N/A 1.7X N/A ' ' . 3.1X .- N/A 2.4X N/A 4.0X . 1,5X 1,5X· 2.1X 1.4X 1.4X 2.0X ASM86/88 N/A 2.1X " PLIM 86/88 N/A 2.0X · ASM 86/88 2.7X 2.7X 3.1X PL/M 86/88 3.7X 3.7X 4.0X ASM 86/88 ADD MODEL 556 I & MODEL 740 PL/M 86/88 N/A 3.1X N/A 4.0X ADD MODEL 556 & MODEL 740 · 2.0X 1,7X' PL/M 86/88 ADD MODEL 505 & MODEL 740 : · · · · ·,. · · . · ! " ·., · · · · "The current system Includes this option. ~h~~~I~~~~r~~~~~f~~=~~~r~o~~~7!:' ~~~Cv~~vC~:~~~:~~~nv:~~~g~~li~~I~~ware, The 11·2 MODEL 120 INTELLEC® SERIES II MICROCOMPUTER DEVELOPMENT SYSTEM • Built·in interfaces for high speed paper tape reader/punch, printer and Universal PROM Programmer • Complete microcomputer development system in one package for MCS®·48 and MCS·80/85 microprocessor families • Integral 250K·byte floppy disk with total storage capacity expandable to over 2M bytes • Single LSI electronics board with CPU, 32K bytes RAM memory, and 4K bytes ROM memory • Available with user's choice of MCS~48 or 8080/8085 macroassembler • Self·test diagnostic capability • Software compatible with previous Intellec®systems • ISIS·II disk operating system The Model 120 Intellec Series II Microcomputer Development System is a complete microcomputer development systemintegrated into one compact package. It includes a CPU with 32K bytes of RAM memory, 4K bytes of ROM memory, a 2000-character CRT, detachable full ASCII keyboard with cursor controls and upperllower case capability, and a 250K-byte floppy diskette drive. Powerful ISIS-II Operating System software allows the Model 120 to be used quickly and efficiently for assembling, compiling and debugging programs for Intel's MCS-48, MCS-80/85 and all other currently supported Intel microprocessor families. ISIS-II performs all file handling operations for the user, leaving him free to concentrate on the details of his own application. When used in conjunction with an optional in-circuit eniula::' tor (ICE™) module or the HSE-49™ High-Speed Emulator, the Model 120 provides all the hardware and software development tools necessary for the rapid development of a microcomputer-based product. 11-3 MODEL 120 FUNCTIONAL DESCRIPTION Input/Output Hardware Components IPB Serial Channels - The 110 subsystem in the Model 120 consists of two parts: the 10C.card and two serial channels on the IPB itself. Each serial channel is RS232 compatible and is capable of running asynchronously from 110 to 9600 baud or synchronously from 150 to 56K baud. Both may be connected to a user defined data set or data terminal. One channel contains current loop adapters. Both ,channels are implemented using Intel's 8251 USART. They can .be programmatically. selected to perform a variety of 110 functions. Baud rate selection is accomplished programmatically through an Intel 8253 interval timer. The 8253 also serves as a real-time clock for the entire system .. 110 activity through both serial channels is signaled· to the system through a second 8259 interrupt controller, operating in a polled mode, nested to the primary 8259. The Intellec Series II Model 120 is a packaged, highly integrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, single floppy diskette drive, and two printed circuit cards. A separate, full ASCII keyboard is connected with a cable. CPU Cards - The master CPU card contains its own microprocessor, memory, 110, interrupt, and bus interface circuitry, f.ashioned from Intel's high-technology LSI components. Known as the integrated processor board (IPB), it occupies the firsi slot in the cardcage. A second, slave CPU card, is responsible for all remaining 110 control, including the CRT and keyboard interface and floppy disk control. This card, mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and 110 interface, thus in effect creating a dual processor environment. Known as the 110 con: troller (IOC), the slave CPU card communicates with the IPB over an 8-bit bidirectional data bus, thus leaving the remaining 5 slots in the cardcage available for system expansion. A block diagram of the 10C is shown in Figure 1. ' . 10C Interface - The remainder of system ilo activity takes place in the 10C. The 10C provides interfaces for the CRT, keyboard, integral floppy disk and other peri ph: erals, including a printer, high speed paper tape readerl punch, and Intel's Universal PROM Programmer. The 10C contains its own independent microprocessor, also an 8080A-2. This CPU controls all 110 operations, as well as supervising communications with the.IPB. 8K bytes of ROM contain al.1 110 control firmware. 8K bytes of RAM are used for CRT screen refresh storage and the floppy disk buffer. These do .not occupy any space in Intellec Series II main memory since thelOC.is a totally independent microcomputer subsystem. System Components The heart of the IPB Is an Intel NMOS 8-blt microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM memory are provided on the board using Intel 16K RA¥s. 4K 6f ROM Is provided, preprog~ammed with system bootstrap "self-test" diagnostics and the Intellec Series II System Monitor. The eight-level vectored priority Interrupt system allows Interrupts to be Individually masked. Using Intel's versatile 8259A Interrupt controller, the interrupt system may be user programmed to respond to individual needs. Integral CRT Display - The CRT is a 12-inch raster scan-type monitor with a 50/60 Hz vertical scan rate and 15.5 kHz horizontal scan rate. Controls are provided for brightness and contrast adjustments. The interface to the CRT is provided through an Intel 8275 single-chip, programmable CRT controller. The master processor on CABLE BUS TO IPB Figure 1. 1/0 Controller (IOC) Block Diagram for the Model 120 Intellec'" Series II Microcomputer Development System 11-4 AFN·01388 ~ MODEL 120 Programmer. Communication between the IPB and 10C is maintained over a separate, 8-bit bidirectional data bus. Connectors for the devices named above, as well as the two serial channels, are mounted directly on the 10C itself. . the IPB transfers a character for display to the 10C, where it is stored in RAM. The CRT controller reads a line at a time into its line buffer through an Intel 8257 DMA controller and then feeds one character at a time to the character generator to produce the video signal. Timing for the CRT control is provided by an Intel 8253 interval timer. The screen display is formatted as 25 rows of 80 characters. The full set of ASCII characters are displayed, including 10wer,cCise. alphas. Control User control is maintained through a front. panel consisting of a power switch and Indicator; reset/boot switch, run/halt light, and eight Interrupt switches and Indicators. The front-panel circuit board Is 'attached directly to the IPB, allowing the eight Interrupt switches to connect to the primary 8259A, as well as to the In' tellec Series II bus. Keyboard - The keyboard interfaces directly to the 10C processor via an 8·bit data bus. The keyboard contains an Intel UPI_41™ Universal Peripheral Interface, which scans the keyboard, encodes the characters, and buf· fers the characters to provide N-key rollover. The key· board itself is.a high quality typewriter-style keyboard containing the full ASCII character set. An upper/lower case switch allows the system to be used for document preparation. Cursor control keys are also provided. MULTIBUS™ Interface Capability All Intellec Series II models implement the industrystandard MULTlBUS protocol. The MULTIBUS protocol enables several bus masters, such as CPU and DMA devices, to share the bus and memory by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock signal derived independently from processor clocks. Read/write transfers may take place at rates up to 5 MHz. The bus structure is suitable for use with any Intel microcomputer family. Floppy Disk Drive The floppy disk drive is controlled by an Intel 8271 single·chip, programmable floppy disk controller. It transfers data via an Intel 8257 DMA controller between an 10C RAM buffer and the diskette. The 8271 handles reading and writing of data, formatting diskettes, and reading status, all upon appropriate commands from the Ibc microprocessor. ' . Expansion Peripheral Interface The Model 120 may be expanded up to 2.25M bytes of on-line floppy diskette storage, plus 7.3M bytes of online hard-disk storage capacity; system RAM may be ex, panded beyond the 32K bytes provided by adding iSBC memory expansion boards. AUPI'41 Universal Peripheral Interface on the 10C board provides interface for other peripheral devices, including a printer, high speed paper tape reader, high speed paper tape punch, and Intel's Universal PROM SPECIFICATIONS Direct Memory Access (DMA) Host Processor (IPB) Standard capability on MULTIBUS bus; implemented for user selected DMA devices through optional DMA module - maximum transfer rate of 5 MHz. 8080A·2 based, operating at 2.600 MHz. RAM - 32K, expandable to 641< with iSBC 032 RAM boards (system monitor occupies 62K through 64K) ROM - 4K (2K in monitor, 2K in boot/diagnostic) Bus - MULTIBUS architecture, maximum transfer rate of 5 MHz Clocks - Host processor, crystal controlled at 2.6 MHz; bus clock, crystal controlled at 9.8304 MHz. Memory Access Time RAM - 585 ns max PROM - 450 ns max Diskette Diskette System Capacity - 250K bytes (formatted) Diskette System Transfer Rate - 160K bits/sec Diskette System Access Time Track-to-Track: 10 ms max Average Random Positioning: 260 ms max Rotational Speed: 360 rpm' . Average Rotational Latency: 83 ms max Recording Mode: FM 110 Interfaces 2 Serial 110 Channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates and serial format fully programmable using Intel 8251A USARTs. Serial Channel 1 additionally provided with 20 rnA current loop. Parallel 110 interfaces provided for paper tape punch, paper tape reader, printer, and UPP-103 Universal PROM Programmer. Physical Characteristics Width Height Depth Weight - Interrupts 8-level, maskable, nested priority interrupt network initiated from front panel or user selected devices. 11-5 17.37 in. (44.12 cm) 15.81 in. (40.16 cm) 19.13 in. (48.59 cm) 73 Ib (33 kg) AFN·01388 MODEL 120 Keyboard Width - 17.37 in. (44.12 cm) Height - 3.0 in. (7.62 cm) Depth - 9.0 in. (22.0 cm) Weight - 6 Ib (3 kg) ROM resident'system monitor ISIS-II system diskette MCS-48 macroassembler diskette (supplied with MCI120/48-Kit) MCS-80/MCS-85 macroassembler diskette (supplied with DS-120/80·Kit) Electrical Characteristics DC Power Supply Volt~. Reference Manuals , Amps Supplied Typical System Requirements 30.0 2.5 0.3 1.5 1.5 1.7 7.5 0.2 0.05 0.15 1.3· 1.2· Equipment Supplied 9800558 - A Guide to Microcomputer Development Systems (SUPPLIED) 9800559 - Intellec Series II Instalfation and Service Manual (SUPPLIED) 9800306 - .ISIS-II System User's Guide (SUPPLIED) 9800556 -Intellec Series II Hardware Reference Manual (SUPPLIED) 9800555 - Intellec Series II Hardware Interface Manual (SUPPLIED) 9800605 - Intellec Series II System Monitor Source Listing (SUPPLIED) 9800554 - Intellec Series II Schematic Drawing (SUPPLIED) 9800255 - MCS-48 and UPI-41 Assembly Language Programming Manual (SUPPLIED with MCI-120/48-Kit) 9800301 - 8080/8085 Assembly Language Programming Manual (SUPPLIED with DS-120/80-Kit) Model 120 chassis Integrated processor board (IPS) I/O controller" board (IOC) CRT and keyboard 250K-byte floppy disk drive Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Sowers Avenue, Santa Clara, California 95051. Supplied + 5 :1:5% +.12 :1:5% -12 :1:5% -10 :1:5% +15 :1:5% +24 :1:5% ·Not available on bus. AC ReCjuirements 110V, 60Hz - 5.9 Amp 220V, 50 Hz - 3.0 Amp Environmental Characteristics Operating TemperatiJre - 16'C to 32'C (61 'F to 90'F) Operating Humidity....:. 20% to 80% relative humidity ORDERING INFORMATION Part Number Des'cription MCI-120/48-Kit (110V/60 Hz) Intellec Series II Model 120 microcomputer'development system with MCS-48 macroassembler Intellec Series II Model 120 micro; computer development system with MCS-80/MCS-85 macroassembler Intellec Series II Model 120 microcomputer development system .. Intellec Series II Model 121 microcomputer development system DS-120/BO-Kit (110V/60 Hz) MDS-120* (110V/60 Hz) MDS-121* (220V/50 Hz) ·"MOS" Is an ordering code orilY,"and is not used as a product name or trademark. MOS· Is a registered trademark of Mohawk Data Sciences Corp. 11-6 MODEL225 INTELLEC@SERIES 11/85 MICROCOMPUTER DEVELOPMENT SYSTEM • Complete microcomputer development system for MCS'-86, MCS" -85, MCS"-80, and MCS'-48 microprocessor families • High performance 8085A-2 CPU, 64K bytes RAM memory, and 4K bytes ROM memory II Self-test diagnostic capability • Built-in interfaces for high speed paper tape reader/punch, printer, and universal PROM programmer • Integral 250K byte floppy disk drive with total storage capacity expandable to over 2M bytes. of floppy disk storage and 7,3M bytes of hard disk storage is Powerful ISIS-II Disk Operating System with relocating macroassembler, linker, locater, and CRT based editor CREDIT • Supports PL/M, FORTRAN, BASIC, PASCAL and COBOL high level languages • Software compatible with previous Intellec'" systems The Intellec Series 11/85 Model 225 Microcomputer Development System is a performance enhanced, complete microcomputer development system integrated into one compact package. The Model 225 includes a CPU with 64K bytes of RAM, 4K bytes of ROM, a 2000-character CRT, detachable full ASCII keyboard with cursor controls and upperllower case capability, and a 250K-byte floppy disk drive. Powerful ISIS-II Disk Operating System software allows the Model 225 to be used quickly and efficiently for assembling and debugging programs for Intel's MCS-86, MCS-85, MCS-80, or MCS-48 microprocessor families. ISIS-II performs all file handling operations for the· user, leaving him free to concentrate on the details of his own application. When used with an optional in-circuit emulator (lCPM) module, the Model 225 provides all of the hardware and software development tools necessary for the rapid development of a microcomputerbased product. Optional storage peripherals provide over 2 million bytes of floppy disk, and 7.3 million of hard disk storage capacity. 11-7 in1:el MODEL225 FUNCTIONAL DESCRIPTION high technology LSI components. Known as the integrated processor card (IPC), it occupies the first slot in the cardcage. A second slave CPU card is responsible for all remaining 1/0 control including the CRT and keyboard interface. This card, mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and 1/0 interface logic, thus, in effect, creating a dual processor environment. Known as the 1/0 controller (IOC), the slave CPU card communicates with the IPC over an 8-bit bidirectional data bus. Hardware Components The Intellec Series 11/85 Model 225 is a highlyintegrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, single floppy disk drive, and two printed circuit cards. A separate, full ASCII keyboard is connected with a cable. A block diagram of the Model 225 is shown in Figure 1. Expansion - Five remaining slots in the cardcage are available for system expansion. Additional expansion of 4 slots can be achieved through the addition of an Intellec Series II expansion chassis. CPU Cards - The master CPU card contains its own microprocessor, memory, 1/0, interrupt and bus interface circuitry implemented with Intel's LOCAL INTERRUPT CONTROL 8259A 64K BYTES RAM 4K BYTES ROM k? 8·LEVEL PRIORITY INTERRUPT 8259A PANEL CONTROL ~ + I t I - SERIAL CHANNELO 8251A SERIAL CHANNELl 8251A I I I I 8085A·2 CPU BIDIRECTIONAL DRIVER BAUD RATE GENERATOR & REAL·TlMECLOCK 8253A ,J INTELLEC BUS BUS CONTROLLER 8219 PRIORITY RESOLUTION SYSTEM CLOCKS 8080A·2 CPU Y 9 DMA ? I ... "" ... ,. 8271 FLOPPY CONTROLLER ... ... "" ... .. ,. 8275 CRT CONTROLLER KEYBOARD ... 8228 SYSTEM CONTROLLER 8KRAM l II ! ... 8253 INTERVAL TIMER CABLE BUS t ~ 8Q41A IOC BUS T CPU t ',; ... ".. ! -! I TAPE PUNCH TAPE READER ,; PIO BUS 8 ! PRINTER r Figure 1. Intellec' Series 11/85 Model 225 Microcomputer Development System Block Diagram 11-8 AFN-014248 inter MODEL225 System Components The heart of the IPC is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K bytes of RAM memory are provided on the board using 16K RAMs. 4K· of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec Series 11/85 System Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually masked. Using Intel's versatile 8259A interrupt controller, the interrupt system may be user programmed to respond to individual needs. Input/Output IPC Serial Channels - The I/O subsystem in the Model 225 consists of two parts: the lac card and two serial channels on the IPC itself. Each serial channel is RS232 compatible and is capable of running asynchronously from 110 to 9600 baud or synchronously from 150 to 56K baud. Both may be connected to a user defined data set or terminal. One channel contains current loop adapters. Both channels are implemented using Intel's 8251A USART. They can be programmed to perform a variety of I/O functions. Baud rate selection is accomplished through an Intel 8253 interval timer. The 8253 also serves as a real-time clock for the entire system. I/O activity through both serial channels is signaled to the system through a second 8259A interrupt controller, operating in a polled mode nested to the primary 8259A. troller. The master processor on the IPC transfers a character for display to the laC, where it is stored in RAM. The CRT controller reads a line at a time into its line buffer through an Intel 8257 DMA controller and then feeds one character at a time to the character generator to produce the video signal. Timing for the CRT control is provided by an Intel 8253 interval timer. The screen display is formatted as 25 rows of 80 characters. The full set of ASCII characters is displayed, including lower case alphas. Keyboard - The keyboard interfaces directly to the lac processor via an 8-bit data bus. The keyboard contains an Intel UPI_41™ Universal Peripheral Interface, which scans the keyboard, encodes the characters, and buffers the characters to provide N-key rollover. The keyboard itself is a high quality typewriter style keyboard containing the full ASCII character set. An upper/lower case switch allows the system to be used for document preparation. Cursor control keys are also provided. Peripheral Interface A UPI-41 Universal Peripheral Interface on the lac board provides interface for other standard Intellec peripherals including a printer, high speed paper tape reader, high speed paper tape punch, and universal PROM programmer. Communication between the IPC and lac is maintained over a separate 8-bit bidirectional data bus. Connectors for the four devices named above, as well as the two serial channels, are mounted directly on the lac itself. lac Interface - The remainder of system I/O activity takes place in the lac. The lac provides interface for the CRT, keyboard, and standard Intellec peripherals including printer, high speed paper tape reader/punch, and universal PROM programmer. The lac contains its own independent microprocessor, an 8080A"2. The CPU controls all I/O operations as well as supervising communications with the IPC. 8K bytes of ROM contain all I/O control firmware. 8K bytes of RAM are used for CRT screen refresh storage. These do not occupy space in Intellec Series II main memory since the lac is a totally independent microcomputer subsystem. Control User control is maintained through a front panel, consisting of a power switch and indicator, reset/boot switch, run/halt light, and eight interrupt switches and indicators. The front panel circuit board is attached directly to the IPC, allowing the eight interrupt switches to connect to the primary 8259A, as well as to the Intellec Series II bus. Integral Floppy Disk Drive Integral CRT The integral floppy disk is controlled by an Intel 8271 single chip, programmable floppy disk controller. It transfers data via an Intel 8257 DMA controller between an lac RAM buffer and the diskette. The 8271 handles reading and writing of data, formatting diskettes, and reading status, all upon appropriate commands from the lac m ic rap rocessor. Display - The CRT is a 12-inch raster scan type monitor with a 50/60 Hz vertical scan rate and 15.5kHz horizontal scan rate. Controls are provided for brightness and contrast adjustments. The interface to the CRT is provided through an Intel 8275 single-chip programmable CRT con11-9 AFN-014248 inter MODEL225 MULTIBUS™ Interface Capability All Intellec Series 11/85 models implement the industry standard MULTIBUS protocol. The MULTIBUS protocol enables several bus masters, such as CPU and DMA devices, to share the bus and memory by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock signal derived independently from processor clocks. Read/write transfers may take place at rates up to 5 MHz. The bus structure is suitable for use with any Intel microcomputer family. SPECIFICATIONS Memory Access Time Host Processor (lPC) RAM - 470 ns max PROM - 540 ns max 8085A-2 based, operating at 4.0 MHz. RAM - 64K on the CPU card ROM - 4K (2K in monitor, 2K in boot/diagnostic) Bus - MULTIBUS™ bus, maximum transfer rate of 5 MHz Clocks - Host processor, crystal controlled at 4.0 MHz, bus clock, crystal controlled at 9.8304 MHz I/O Interfaces Two Serial I/O Channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates and serial format fully programmable using Intel 8251 A USARTs. Serial Channel 1 additionally provided with 20 mA current loop. Parallel I/O interfaces provided for paper tape punch, paper tape reader, printer, and UPP-103 Universal PROM Programmer. Integral Floppy Disk Drive Floppy Disk System Capacity 250K bytes (formatted) Floppy Disk System Transfer Rate160K bits/sec Floppy Disk System Access Time Track to Track: 10 ms max Average Random Positioning: 260 ms Rotational Speed: 360 rpm Average Rotational Latency: 83 ms Recording Mode: FM Physical Characteristics Interrupts CHASSIS 8-level, maskable, nested priority interrupt network initiated from front panel or user selected devices. Width -17.37 in. (44.12 cm) Height -, 15.81 in. (40.16 em) Depth -19.13 in. (48.59 cm) Weight - 73 lb. (33 kg) Direct Memory Access (DMA) KEYBOARD Standard capability on M ULTIBUS interface; implemented for user selected DMA devices through optional DMA module-maximum transfer rate of 5 MHz. Width -17.37 in. (44.12 cm) Height - 3.0 in. (7.62 em) Depth - 9.0 in. (22.86 em) Weight - 6 lb. (3 kg) 11-10 AFN·014248 inter MODEL225 Electrical Characteristics Equipment Supplied Model 225 Chassis including: Integrated Processor Card (IPC) 1/0 Controller Board (lOC) CRT ROM-Resident System Monitor Detachable keyboard ISIS-II System Diskette with MCS-80/MCS-85 Macroassembler ISIS-II CREDIT Diskette CRT-Based Text Editor DC POWER SUPPLY Volts Supplied Amps Supplied Typical System Requirements + 5±5% +12 ± 5% -12 ± 5% -10 ± 5% +15±5%* + 24 ± 5%* 30.0 2.5 0.3 1.0 1.5 1.7 17.0 1.1 0.1 0.08 1.5 1.7 Documentation Supplied A Guide to Microcomputer Development Systems, 9800558 *Not available on bus. Intellec® Series II Model 22X/23X Installation Manual, 9800559 ISIS-II System User's Guide, 9800306 Intellec® Series II Hardware Reference Manual, 9800556 AC REQUIREMENTS FOR MAINFRAME 8080/8085 Assembly Manual, 9800301 110V, 60 Hz - 5.9 Amp 220V, 50 Hz - 3.0 Amp Language Programming ISIS-II 8080/8085 Assembler Operator's Manual, 9800292 Intellec~ Series Listing, 9800605 II Systems Monitor Source Intellec@ Series II Schematic Drawings, 9800554 ISIS-II CREDIT (CRT-Based Text Editor) User's Guide, 9800902 Environmental Characteristics Additional manuals may be ordered from any Intel sales representative or distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Operating Temperature _16°C to 32°C (61°F to 90°F) Humidity - 20% to 80% ORDERING INFORMATION Part Number Description MDS-225* Intellec® Series 11/85 Model 225 Microcomputer Development System (110V 160 Hz) MDS-226* Intellec® Series 11/85 Model 226 Microcomputer Development System (220V 150 Hz) '''MOS'' is an ordering code only, and is not used as a product name or trademark. MDS'" is a registered trademark of Mohawk Data Sciences Corp. 11-11 AFN·014248 MODEL 286 INTELLEC® SERIES III MICROCOMPUTER DEVELOPMENT SYSTEM • Complete 16-bit High Performace, Microcomputer Development Solution for Intel iAPX 88/86 Applications. Also Supports MCS-85™, MCS-80™ and MCS-48™ Families • Upgradeable from Intellec® Model 800, Series 11/80 and Series 11/85 • Compatible with Intellec® Distributed Development Systems • Software Compatible with Previous Intellec® Systems • Full Range of iAPX 88/86-resident, High-level Languages: PL/M-88/86, PASCAL-88/86, and FORTRAN-88/86 • Software Applications Debugger for User iAPX 88/86 Programs • 2 Host CPUs-iAPX 86 and 8085A-for Enhanced System Performance and Two Native Execution Environments • Integral 250K Byte Floppy Disk Drive with Total Storage Capacity Expandable to Over 2M Bytes of Floppy Disk Storage and 7.3 M Bytes of Hard Disk Storage (formatted) • 96K Bytes of User Program RAM Memory Available for iAPX 88/86 Programs The Intellec® Series-III Microcomputer Development System is a high performance system solution designed specifically for iAPX 88/86 microprocessor development. It contains two host CPUs, and iAPX 86 and an 8085, that provide two native execution environments for optimum performance and compatibility with the Intellec software packages for both CPUs. The basic system includes 96K bytes of iAPX 88/86 user RAM memory, a 2000-character CRT, detachable full ASCII keyboard with cursor controls and upper/lower case capability, and a 250K byte floppy disk drive. The powerful Disk Operating System maximizes system processing by utilizing the power of both host processors. Standard software includes a full range of iAPX 88/86 resident software and the high-level languages PL/M-88/86, PASCAL-88/86, and FORTRAN-88/86 are also available. A ROM resident software debugger not only provides self-test diagnostic capability, but also gives the user a powerful iAPX 88/86 applications debugger. 11-12 AFN·01588A 121670-001 Rev. A inter MODEL 286 FUNCTIONAL DESCRIPTION contains Intel's 16-bit HMOS microprocessor. These CPUs provide the dual processor environment. Hardware Components A third CPU card performs all remaining I/O including interface to the CRT, integral floppy disk, and keyboard. This card, mounted on the rear panel, contains its own microprocessors, RAM and ROM memory, and I/O interface logic. Known as the I/O controller (IOC), this slave CPU card communicates with the IPC-85 over an 8-bit bidirectional data bus.A 64K byte RAM expansion memory board is also included. The Intellec Series III is contained in a single package consisting of a CRT chassis with a 6-slot card cage, power supply, fans, cables, single floppy disk drive, detachable upper/lower case full ASCII keyboard, and four printed circuit cards. A block diagram of the system is shown in Figure 1. System Components Expansion Two CPU cards reside on the Intellec MULTIBUS™ bus, each containing its own microprocessor, memory, I/O, interrupt and bus interface circuitry implemented with Intel's high technology LSI components. The integrated processor card (IPC-85), occupies the first slot in the cardcage.A second CPU card, the resident processor board (RPB-86) Two additional slots in the system cardcage are available for system expansion. The Intellec expansion chassis Model 201 is available to provide 4 additional expansion slots for either memory or I/O expansion. Figure 1. INTELLEC® Series III Block Diagram 11-13 AFN-01588A MODEL 286 and standard Intellec-compatable peripherals including printer, high speed paper tape reader/ punch, and universal PROM programmer. The 10C contains its own independent microprocessor, an 8080A-2. This CPU issues commands, receives status, and controls all I/O operations as well as supervising communications with the IPC-85. The 10C contains interval timers, its own 10C bus system controller, and 8K bytes of ROM for all I/O control firmware. The 8K bytes of RAM are used for CRT screen refresh storage. Neither the ROM nor the RAM occupy space in the Intellec Series III main memory address range because the 10C is a totally independent microcomputer subsystem. CPU Cards IPc-a5 The heart of the IPC-85 is an IntelNMbs 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K bytes of RAM memory are provided on the board using 16K dynamic RAMs. 4K of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec System Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually masked. Using Intel's versatile 8259A interrupt controller, the interrupt system may be user programmed to respond to individual needs. RPB-as The heart of the RPB-.86 is an Intel HMOS 16-bit microprocessor, the iAPX 86 (8086), running at 5.0 MHz. 64K bytes of RAM memory are provided on the board. 16K of ROM is provided on board, preprogrammed with an iAPX 88/86 applications debugger which provides features necessary to debug and execute application software for the iAPX 88/86 microprocessors. Integral CRT The 8085A-2 and iAPX 86 access two independent memory spaces. This allows the two processors to execute concurrently when an iAPX 88/86 program is run. In this mode, the IPC-85 becomes an intellegent I/O processor board to the RPB-86. Input/Output IPc-a5 SERIAL CHANNELS The I/O subsystem in the Series III consists of two parts: the 10C card and two serial channels on the IPC-85 itself. Each serial channel is independently configurable. Both are RS232-compatible and is capable of running asynchronously from 110 to 9600 baud or synchronously from 150 to 56K baud. Both may be connected to a user defined data set or terminal. One channel contains current loop adapters. Both channels are implemented using Intel's 825.1 A USART. They can be programmed to perform a variety of I/O functions. Baud rate selection is accomplished through an Intel 8253 interval timer. The 8253 also serves as a real-time clock for the entire system. I/O activity through each serial channel is independently signaled to the system through a second 8259A (slave) interrupt controller, operating in a polled mode nested to the master 8259A. IOC INTERFACE The remainder of the system I/O activity is handled by the 10C. The 10C provides the interface and control forthe keyboard, CRT, integral floppy disk drive, DISPLAY TheGRT is a 12-inch raster scan type monitor with a 50/60 Hz vertical scan rate and 15.5 kHz horizontal scan rate. Controls are provided for brightness and contrast adjustments. The interface to the CRT is provided through an Intel 8275 single chip programmable CRT controller. The master processor on the IPC-85 transfers a character for display to the 10C, where. it is stored in RAM. The CRT controller reads aline at a time into its line buffer through an Intel 8257 DMA Controller. It then feeds one character ata time to the character generator to produce the video Signal. Timing for the CRT control is provided by an Intel 8253 programmable interval timer. The screen display is formatted as 25 rows of 80 characters. The full set of ASCII characters are displayed, including lower case alphas. KEYBOARD The keyboard interfaces directly to the 10C processor via an 8-bit data bus. The keyboard contains an Intel UPI-41A Universal Peripheral Interface, which scans the keyboard and encodes the characters to provide N-key roll over. The keyboard itself is a typewriter style keyboard containing the full ASCII character set. An upper/lower case switch allows the system to be used for dor.l"nent preparation. Cursor control keys are also provided. Peripheral Interface A UPI-41A Universal Peripheral Interface on the 10C board provides built-in interface for standard Intellec-compatable peripherals including a printer, high speed paper tape reader, high speed paper tape punch, and universal PROM programmer. Communication between the IPC-85 and 10C is 11-14 AFN·01588A MODEL 286 FLOPPY DISK CONTROLLER BOARDS The diskette controller consists of two boards, the channel board and the interface board. These two PC boards reside in the Intellec Series III system chassis. The channel board receives, decodes and responds to channel commands from the 8085A-2 CPU on the IPC-85. The interface board provides the diskette controller with a means of communication with the disk drives and with the Intellec system bus. The interface board validates data during reads using a cyclic redundancy check (CRC) polynomial and generates CRC data during write operations. When the diskette controller requires access to the Intellec system memory, the interface board requests and maintains DMA master control of the system bus, and generates the appropriate memory command. maintained over a separate 8-bit bidirectional data bus. Connectors for the four devices named above, as well as the two serial channels, are mounted directly on the IOC itself. Control User control is maintained through a front panel, consisting of a power switch and indicator,reset/ boot switch, run/halt light and eight interrupt switches and LED indicators. The front panel circuit board is attached directly to the IPC-85, allowing the eight interrupt switches to connect the master 8259A, as well as to the Intellec Series III bus. User program control in the iAPX 88/86 environment of the Intellec Series III is also directed through keyboard control sequences to transfer control to the iAPX 88/86 applications debugger, abort a user program or translator and returning control to the IPC-85. DISK SYSTEM Integral Floppy Disk Drive The integral floppy disk is controlled by an Intel 8271 single chip, programmable floppy disk controller. The disk provides capacity of 250K bytes. It transfers data via an Intel 8257 DMA Controller between an IOC RAM buffer and the diskette. The 8271 handles reading and writing of data, formatting diskettes, and reading status, all upon appropriate commands from the IOC microprocessor. Hard Disk System (Option) The Intellec Series III Hard Disk System provides direct access bulk storage, intelligent controller and a disk drive containing one fixed platter and one removable cartridge. Each provides approximately 3.65 million bytes of storage with a data transfer rate of 2.5 Mbits/second. The controller is implemented with Intel's Series 3000 Bipolar Microcomputer Set. The controller provides an interface to the Intellec Series III system bus, as well as supporting up to 2 disk drives. The disk system records all data in Double Frequency (FM) on 2 surfaces per platter. Each platter can be write protected by a front panel switch. Dual Drive Floppy Disk System (Option) The Intellec Series III Double Density Diskette System provides direct access bulk storage, intelligent controller and two diskette drives. Each drive provides 1/2 million bytes of storage with a data transfer of 500,000 bits/second. The controller is implemented with Intel's powerful Series 3000 Bipolar Microcomputer Set. The controller provides an interface to the Intellec Series III system bus, as well as supporting up to four diskette drives to allow more than 2 million bytes of on-line storage. An additional cable and connectors are also supplied to optionally convert the integral floppy disk from single density to double density. 11-15 HARD DISK CONTROLLER BOARDS The disk controller consists of two boards which reside in the Intellec Series III system chassis. The disk system is capable of performing six operations: recalibrate, seek, format track, write data, read data, and verify CRC: In addition to supporting a second drive, the disk controller may co-exist with the double-density diskette controller to allow up to 17 million bytes of on-line storage. MULTIBUS™ Interface Capability All models of the Intellec Series III implement the industry standard MULTIBUS protocol. The MULTIBUS architecture allows several bus masters, such as CPU and DMA devices, to share the bus and memory by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock signal derived independently from processor clocks. Read/write transfers may take place at rates up to 5 MHz. The bus structure is suitable for use with any Intel microcomputer family. AFN·01588A inter MODEL, 286 SPECIFICATIONS' , Hard Disk Drive Option Host Processor Boards DIRECT MEMORY ACCESS -(DMA) Standard capability on the MULTIBUS bus; implemented for us'erselected DMA devices through optional DMA module -Maximum transfer rate of 2 MHz Type-5440 top loading cartridge .and one fixed platter Tracks per Inch-200 Mechanical Sectors per Track-12 Recording Technique-double frequency (FM) Tracks per Surface-400 Density-2,200 bits/inch Bits 'per Track-62,500 Recording Surfaces per Platter-2 Capacity'Per Surface-15M bits Per Platter-29M bits Per Drive-59M bits Per Drive"':"'7.3M bytes (formatted) Transfer Rate-2.5M bits/sec Access TimeTrackto Track: 13 ms max Full Stroke: 100 ms Rotational Speed: 2,400 rpm Integral Floppy Disk '. Physical Characteristics Capacity-250K bytes (forniatted) Transfer Rate-160K bits/sec Access Time- . Track to Track: '10 ms max, Average Random Positioning: 260 ns Rotational Speed: 360 rpm. ,Average flotational Latency: 83 ms Recording Mode: FM Width-17.37 in. (44.12 cm) Height-15.81 in. (40.16 cm) Depth-19.13 in. (48.59 cm) Weight-81 lb. (37 kg) INTEGRATED PROCESSOR CARD -(IPC-85) 8085A-2 based, operating at 4 MHz -64K RAM, 4K ROM (2K in monitor and 2K in boot! diagnostic)' , RESIDENT PROCESSOR BOARD -(RPB-86) 8086 based, operating at 5 MHz, 64K RAM, 16K ROM (applications debugger) , BUS -MULTIBUS bus, maximum transfer rate of 5 MHz Dual Floppy Disk Option CapacityP~r Disk: 4,1 megabits (formatted) Per Track: 53,2 kilobits (formatted) Transfe,r Rate-500 kilobits/sec Access TimeTrack to Track: 10 ms Head Setting Time: 1,0 ills Average Random Positioning Time-260 ms Rotational Speed-360 rpm Average Rotational Latency: 83 ms Recording Mode: M2 FM KEYBOARD Width-'17.37 in. (44.12 cm) Height-3.0 in. (7.6 cm) Depth-9.0 in. (22.86 cm) Weight-6 lb. (3 kg) DUAL FLOPPY DRIVE SYSTEM (OPTION) Width-16.88 in. (42.88 cm) Height-12.08 in. (30.68 cm) Depth-1.0 in. (48.26 cm) Weight-64 lb. (29 kg) HARD DISK DRIVE SYSTEM (OPTiON) Width-18.5 in. (47.0 cm) Height-34.0 in. (86.4 cm) Pepth-29.75 in, (75,6 cm) Weight-202 lb. (92 kg) 11-16 AFN-Ql588A inter MODEL 286 Intellec Series III Microcomputer Development System Console Operating Instructions, 121609 ELECTRICAL CHARACTERISTICS DC Power Supply Intellec Series III Microcomputer Development System Pocket Reference, 121610 Intellec Series III Microcomputer Development System Programmer's Reference, 121618 Typical System Requirements Volts Supplied Amps Supplied + 5 ± 5% 30.0 17.0 +12 ± 5% 2.5 1.1 -12 ± 5% 0.3 0.1 -10 ± 5% 1.0 0.08 +15±5%' 1.5 1.5 +24 ± 5%' 1.7 1.7 iAPX 88186 Family Utilities User's Guide for 8086Based Development Systems, 121616 80861808718088 Macro Assembly Language Refer· ence Manual for 8086-Based Development Systems, 121627 . 80861808718088 Macro ASSembly Language. Pocket Reference, 9800749 80861808718088 Macro Assembler Operating Instructions for 8086-Based Development Systems, 121628 Not available on bus AC Requirements for Mainframe Intellec Series III Microcomputer Development System Installation and Checkout Manual, 121612 110V, 60 Hz-5.9 Amp 220V, 50 Hz-3.0 Amp Intellec Series III Microcomputer Development System Schematic Drawings, 121642 ENVIRONMENAL CHARACTERISTICS ISIS-II CREDIT (CRT-Based Text Editor) User's Guide, 9800902 ISIS-II CREDIT (CRT-Based Text Editor) Pocket Reference, 9800903 System Operating Temperature-O°C to 35°C (32°F to 95°F) The 8086 Family User's Manual, 9800722 Humidity-20% to 80% The 8086 Family User's Manual, Numeric Supplement, 121586 DOCUMENTATION SUPPLIED For Series III Plus Hard Disk Systems Only: Intellec Series III Microcomputer Development System Product Overview, 121575 Model 740 Hard Disk Subsystem Operation and Checkout, 9800943 ORDERING INFORMATION DS287FD KIT Part Number Description D8286 KIT Intellec Series III Model 286 Microcomputer Development System (110V/60Hz) DS287 KIT DS286FD KIT Intellec Series III Model 287 Microcomputer Development System (220V/50Hz) Intellec Series III Model 286 Microcomputer Development System with Dual Double Density Flexible Disk System (110V/60Hz) 11-17 Intellec Series III Model 287 Microcomputer Development System with Dual Double Density Flexible Disk System (220V/50Hz) DS286HD KIT Intellec Series III Model 286 Microcomputer Development System with Pedestal Mounted Hard Disk. (110V/60Hz) DS287HD KIT Intellec Series III Model 287 Microcomputer Development System with Pedestal Mounted Hard Disk. (220V/50Hz) Requires Software License AFN·01588A MODEL 290 NETWORK MANAGER INTELLEC® NETWORK DEVELOPMENT SYSTEM-I (NOS-I) • Provides a distributed development system environment for Intellec® microcomputer development system users ill Supports up to 8 workstations operating • Supports all existing Intellec® development systems as workstations: Intellec® Model 800, Series 11/80, Series 11/85, and Series III models • Provides substantial performance enhancement for floppy disk-based systems concurrently • Files stored on central hard disk shared among workstations • Functions as a Project Management tool to increase programmer productivity and coordinate large program development • Shared background line printer • Distributes the costs of central mass storage among workstations • Network Manager upgradeable from either Intellec® Model 240 or Intellec® Model 245 The Intellec® Network Development System-I (NDS-I) is designed to provide the user with tools necessary to support a distributed development system environment. NDS-I enables up to eight Intellec development systems to share both a common line printer and disk storage. Disk files may reside on either one or two central hard disks, providing up to fifteen megabytes of storage capacity. The major component of NDS-I is the Network Manager which controls all communications between the workstations and the shared disk. The powerful multitasking operating system of the Network Manager provides public/private file control for all files resident on the hard disk and printer sharing. As a project management tool, NDS-I helps coordinate the numerous program modules common to large multi-man projects. Productivity is increased and development time is shortened. An upgrade package is available to convert an existing Model 240 or 245 into a Network Manager. 11-18 121670·001RA MODEL 290 FUNCTIONAL DESCRIPTION Hardware Compon~nts The NDS-I Network Manager consists of CRTchassis with a 6-slot card cage, power supply, fans, cables, single floppy diskette drive, a detachable full ASCII keyboard and five printed circu it cards. A free standing pedestal houses the hard disk drive along with power supply, fans, and cables for connection to the main chassis. A block diagram of the Network Manager is shown in Figure 1. CPU The master CPU card is bu ilt arou nd the 8085A-2 and incl udes 64K bytes of on board memory, I/O, interrupt and bus interface circuiting fashioned from Intel's high technology components. Known as the integrated processor card (IPC), it occupies the first slot in the cardcage. A second slave CPU card is responsible for the CRTand keyboard interface. This card, mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and I/O interface logic. Known as the input/output controller (IOC), .the slave CPU card communicates with the IPC over an a-bit bidirectional data bus. DISK CONTROLLER The hard disk controller consists of two boards, the channel board and the interface board, mounted in the system cardcage. The channel board receives, decodes and responds to channel commands from the 8085A-2 in the Network Manager. The interface board provides the disk controller with a means of communication with the disk drives and with the Intellec system bus. The interface board generates a cyclical redundancy check polynomial and validates data during reads using a CRC polynomial. When the disk controller requires access to Intellec system memory, the channel board requests and maintains DMA master control of the system bus, and generates the appropriate memory command. The channel board also acknowledges I/O commands as required by the Intellec bus. The disk controller supports one or two hard disk drives. INTERCONNECT COMMUNICATION An Interconnect Board (ICB), which occupies one slot in each workstation and the Network Manager cardcage, provides the communications interface between the workstations and the Network Manager. The ICB is a MULTIBUS™ bus compatible board with an 8085 microprocessor, 1.25 kbytes of RAM,4 kbytas of ROM and seven I/O ports. The ICB accepts a command from the master CPU, executes the command without intervention by the master CPU, and signals completion by setting a flag and generating a MULTIBUS™ bus interrupt. The ICB moves data between the workstations and the Network Manager with a burst of data transfer rate of 40 kbytes per second. TO WORKSTAnON INTERCONNECT BOARD TOPIO BUS Figure 1. Intellec NDS-I Network Manager Block Diagram 11-19 AFN·01595A inter MODEL 290 INTEGRAL CRT The CRT is a 12·inch raster scan type monitor with a 50/60Hz vertical scan rate and 15.5kHz horizontal scan rate. Controls are prov'ided for brightness and contrast adjustments. The interface to the CRT is provided through an Intel 8275 single·chip program· mabie CRT controller. The master processor on the IPC transfers a character for display to the IOC. where it is stored in RAM. The CRT controller reads a line at a time into its line buffer through an Intel 8257 DMA controller and then feeds one character at a time to the character generator to produce the video signal. Timing for the CRT control is provided by an Intel 8253 interval timer. The screen display is for· matted as 25 rows of 80 characters. The full set of ASCII characters is displayed, including lower case letters. FLOPPY DISK DRIVE The integral single density floppy disk drive is controlled by an Intel 8271 single·chip, program· mabie floppy disk controller. The 8271 transfers data via an Intel 8257 DMA controller between an IOC RAM buffer and the diskette. The 8271 performs reading and writing of data, formatting diskettes, and reading status commands from the IOC processor. Software Components KEYBOARD The keyboard interfaces directly to the IOC proces· sor via an 8·bit data bus. The keyboard contains an Intel UPI·41 Universal Peripheral Interface, which scans the keyboard, encodes the characters, buf· fers the characters and provides N·key rollover. The keyboard itself is a typewriter style keyboard containing the full ASCII character set. An up· per/lower case switch allows the system to be used for document preparation. Cursor control keys are also provided. Included with theModel290 is the Network Manager operating system that controls all communications between the workstations and the shared hard disk. The operating system software provides concurrent disk input/output, communications, and file manage· ment, and offers substantial workstation per· formance enhancements compared to standalone, floppy disk·based development systems. The Net· work Manager operating system provides public/private file control for all files resident on the hard disk. The public/private file control provides a useful project management tool to help coordinate the numerous programmers and modules common to large development projects. SPECIFICATIONS Disk Performance Disk Drive Type-5440 top loading cartridge and one fixed platter Tracks per inch-200 Mechanical Sectors per Track-12 Recording Technique-double frequency (FM) Tracks per Surface-400 Density-2,200 bitslinch Bits per Track-62,500 Recording Surfaces per Platter-2 Disk Transfer Rate-2.5M bits/sec Disk System Access Time Track to Track: 13 ms max Full Stroke: 100 ms Rotational Speed: 2,400 rpm Diskette Diskette System Capacity-250K bytes (formatted) Diskette System Transfer Rate-160K bits/sec Diskette System Access Time Track to Track: 10 ms max Average Random Positioning: 260ms Rotational Speed: 360 rpm Average Rotational Latency: 83 ms Recording Mode: FM Disk System Capacity Per Per Per Per Surface-15M bits Platter-29M bits Drive-59M bits Drive-7.3M bytes (formatted) 11·20 AFN·01595A intel· MODEL 290 Physical Characteristics Environmental Characteristics Width-17.37 in. (44.12 cm) Height-15.81 in. (40.1.6 cm) Depth-19.13 in. (48.59 cm) Weight-73 lb. (33 kg) Operating Temperature-16°C to 32°C (90°F) Humidity-20% to 80% Equipment Supplied Model 225 Chassis Integrated Processor Card I/O Controller Board CRTand Keyboard Model 740 Hard Disk Drive Two Hard Disk Controller Boards with Cables Disk Cartridge NDS-I Interconnect Board with Cable Two NDS-I Line Terminators ROM Resident System Monitor Network Manager Operating System Network Manager Diagnostics KEYBOARD Width-17.37 in. (44.12 cm) Height-3.0 in. (7.62 cm) Depth:-9.0 in. (22.86 cm) Weight-6 lb. (3 kg) DISK DRIVE ON PEDESTAL Width-18.5 in. (47.0 cm) Height-34.0 in. (86.4 cm) Depth-29.75 in (75.6 cm) Weight-202 lb. (92 kg) Reference Manuals Electrical Characteristics D.C. POWER SUPPLY Supply Voltage Amps Supplied Typical System Requirements + 5 ±5% +12±5% -12±5% -10±5% +15±5%* +24±5%" 30 2.5 0.3 1.0 1.5 1.7 17.0 1.1 0.1 0.08 1.5 1.7 "Not available on bus Hard Disk Subsystem Operation and Checkout Manual, 9800943. Network Manager Console Operating Instructions, 121645. Optional Equipment Model 595 NDS-I Workstation Interconnect Package: Includes Interconnect board and workstation software to convert any Model 800, Series 11180, Series 11/85, or Series III to a NDS-I workstation. Model 596 NDS-110 ft. Interconnect Cable Model 597 NDS-I 20 ft. Interconnect Cable A.C. REQUIREMENTS FOR MAINFRAME AND 2 DRIVES 110V, 60Hz-16 Amp (Mainframe =5.9 Amp) (Drive =5.0 Amp) 220V, 50Hz-8.6 Amp (Mainframe =3.1 Amp) (Drive =3.0 Amp) Model 743 (110V) Add on hard disk unit with cables and disk cartridge. Model 744 (220V) Add on hard disk unit with cables and disk cartridge. Model 746 Box of 5 blank hard disk cartridges. ORDERING INFORMATION Part Number Description DS-290 (11 OV) NDS-I Network Manager: Includes DS-291 (220V) network console with hard disk subsystem, interconnect board, internal cable, and Network Manager software. 11·21 AFN'()1595A Microcomputer Development Systems Options 12 EXPANSION CHASSIS INTELLEC® SERIES II MICROCOMPUTER DEVELOPMENT SYSTEM • Four Expansion Slots for Intellec® Series II Systems • Cable Connectable to Main Intellec® Bus • Internal Power Supply • Standard Intellec MULTIBUS™ with Multi-Processor and DMA Capability • Snug Fit Beneath All Intellec® Series II Units • Compatible with Standard Intellect iSBC™ Expansion Modules The Intellec Series II Expansion Chassis provides four expansion slots for use with Intellec Series II microcomputer development systems. With its own separate power supply, the expansion chassis may be fully loaded with any boards needed to expand a user's Intellec Series II system. With the addition of the expansion chassis, Intellec Series II Models 220 and 230 contain a total of ten slots, sufficient for any configuration Intellec Series II system. The Intellec Series II Expansion Chassis is a compact chassis with a four slot cardcage, power supply, fans, and cable assemblies. It is designed to fit under any Intellec Series II system, connect directly to the system bus through an opening in the top of the chassis, and provide additional slots for the system users. The power supply is linked directly to the main chassis power supply, allowing power to flow to both chassis when the main power is turned on. 12-1 AFN·00822A EXPANSION CHASSIS SPECI FICATIONS Environmental Characteristics Physical Characteristics Operating Temperature - Width - 17.37 In. (44.12 cm) Height - 4.81 in. (17.22 cm) Depth - 19.13 in. (48.59 cm) Weight - 42 lb. (19 kg) 0° to 35°C (95°F) Equipment Supplied Expansion chassis Cables Reference Manuals 9800550 - Intellec Series II Installation and Service Guide (SUPPLIED) 9800554 - Intellec Series II Schematic Drawings (SUPPLIED) Electrical Characteristics DC Power Supply Volt. Supplied 'Amps Supplied R~qulrements + S±5% + 12:!:5% 24 2.0 0.3 1.0 None None None None -12:1:5% -10:1:5% AC Requirements - System Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. 50·60 Hz, 115/230V AC. ORDERING INFORMATION Part Number Description MDS-201* Intellec® Series II Expansion Chassis 'MOS is an ordering code only and is not used asa product name or trademark. MOS" is a registered trademark of Mohawk Data Science. 12-2 AFN-QOB22A intel~ MODEL 503 DOUBLE DENSITY UPGRADE KIT FOR INTELLEC® MICROCOMPUTER DEVELOPMENT SYSTEM • Converts integral single density drive of Model 220 or Model 240 system to double density, doubling the data capacity from 114 to 112 million bytes • Associated software and hardware supports up to three double density drives, providing up to 1112 million bytes in one system • Data recorded on double density flexi· ble disk is in soft sectored format which allows 112 million bytes data capacity with up to 200 files per flexible disk • Provides total data compability with other Intellec® Double Density Flexible Disk Systems The Double Density Upgrade Kit Model 503 provides an easy, cost effective method to convert the integral single density drive of Model 220 or Model 240 system to double density. In addition to doubling the data capacity, the upgrade kit maximizes the ease of data transportability between Intellec® Double Density Flexible Disk Systems. 12-3 MODEL 503 DOUBLE DENSITY UPGRADE KIT SPECIFICATIONS Electrical Characteristics Equipment Supplied Channel Board 5V @ 3.75 (typ), 5A (max) - Floppy Disk Controller Channel Board Interface Board - Double Density Floppy Disk Interface Board Dual Auxiliary Board Connector Double Density Controller Cable Double Density Integral Drive Cable ISIS-II Double Density System Disk 5V @ 1.5A (typ), 2.5A (max) -10V @ 0.1A (typ), 0.2A (max) Environmental Characteristics Controller Boards Hardware Double Density Specified Flexible Disk One Recording Surface Soft Sector Format M2FM 77 TrackslDiskette 52 SectorslTrack 128 Bytes/Sector Temperature: Operating: 0 to 55°C Non-Operating: -55°C to 85°C Humidity: Operating: Up to 95% relative humidity without condensation Non-Operating: All conditions without condensation of water or frost. Physical Characteristics Mounting-Requires two slots of system card cage Reference Manuals Height- 6.75 in. (17.15mm) Width -12.00 in. (30.48mm) Depth - 0.50 in. (1.27mm) DOS Hardware Reference Manual Reference Schematics Installation Instructions ORDERING INFORMATION Part Number Description MDS-503* Integral drive Single density to . double density upgrade kit . ·"MDS" is an ordering code only, and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corp. 12-4 9800422 9800425 121505 MODEL 505 INTEGRATED PROCESSOR CARD • High Performance 8085A-2 Based Integrated Processor Card Upgrades Intellec® Series II Microcomputer Development Systems to the Performance of Series 11/85 Systems • Single Electronic Board with 8085A-2 CPU, 64K Bytes RAM and 4K Bytes ROM • Increases Card Slot Availability on the Intellec® Series II Microcomputer Development System • Additional Functions Available Through MULTIBUS™ Interface-' - Local Interrupt Controller - Programmable Interval Timer - Two Channels of USARTs • Fully Software Compatible with the 8080-Based Integrated Processor Board The Intellec'" Series 11/85 Model-505lntegrated Processor Card (lPC) is a single board upgrade for all 8080based Intellec Series II Microcomputer Development Systems. The IPC is an 8085A-2 based CPU board which contains 64K bytes of RAM, 4K bytes of ROM, two 8259 interrupt controllers, two 8251 USARTs, al'l 8253 interval timer, MULTIBUS™ compatible interface, and special interfaces to the Intellec Series II Microcomputer Development System. The IPC is fully software compatible with the8080-based integrated processor board. " 12-5 01530A MODEL 505 Higher Speed-The IPB uses an 8080A-2 microprocessor with a 23.4000 MHz crystal to derive a clock cycle time of 384.6nsec, and executes with one wait state on memory read cycles, and 2 wait states on memory write cycles. The IPC uses an 8085A-2 microprocessor with an 8.0000 MHz crystal to derive a clock cycle time of 250nsec, and runs with the same number of wait states as the IPB. The IPC thus provides an increase in processing speed of approximately 54% over the IPB. The overall system throughput improves correspondingly. However, the amount of improvement is a function of the type and the length of the programs being executed, as well as the type of storage devices attached to the system. FUNCTIONAL DESCRIPTION Hardware Components The heart of the IPC is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K bytes of RAM memory are provided on the board using 16K RAM chips. 4K of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec Series 11185 System Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually masked. Using Intel's versatile 8259A interrupt controller, the interrupt system may be user programmed to respond to individual needs. SYSTEM IMPROVEMENTS The IPC provides two main advantages over its predecessor, the 8080-based Integrated Processor Board (IPB). The first advantage is the higher processing speed. The second advantage is that it provides twice the memory. Saves One Card Slot Space-The IPC contains an additional 32K bytes of RAM over the IPB, to provide a total of 64K bytes of system memory on one card. The increased on-board RAM size frees up . one slot in the card cage of the Series II. For a typical user of ICE-86™ or ICE-88™ emulators, this additional slot will eliminate the need to purchase an expansion chassis. SPECIFICATIONS Interrupts Host Processor (I PC) Eight-level, maskable, nested priority interrupt network initiated from front panel or user selected devices. Processor-8085A-2 based, operating at 4.0 MHz. RAM-64K on the CPU card. ROM-4K (2K in monitor, 2K in boot/diagnostic) Bus-,,,MULTIBUS™ bus, maximum .transfer rate of 5MHz. Clocks-Host processor crystal controlled at 4.0 MHz; bus clock, crystal controlled at 9.8304 MHz. Direct Memory Access (DMA) Standard capability on MULTIBUS™ interface; implemented for user selected DMAdevices through optional DMA module-maximum transfer rate of 5 MHz. I/O Interfaces Two Serial 110 Channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates and serial format fully programmable using Intel 8251A USARTs. Serial Channel 1 additionally provided with 20 mA current loop. Parallel 110 interfaces provided for paper tape punch, paper tape reader, printer, and UPP-103 Universal PROM Programmer. Memory Access Time RAM-470 ns max PROM-540 ns max 12·6 inter MODEL 505 ELECTRICAL CHARACTERISTICS EQUIPMENT SUPPLIED DC Power Supply 8085 Based Integrated Processor Card (lPC) Voltage Requirements (Volts) Worst Case Current Requirements (Amperes) + 5±5% + 12 ± 5% -12 ± 5% -10 ± 5% 4.2 0.5 0.2 0.02 DOCUMENTATION SUPPLIED Intellec® Series II Model 22X123X Installation Manual, 9800559 Intellec® Series II Hardware Reference Manual, 9800556 ENVIRONMENTAL CHARACTERISTICS Operating Temp.: Board Level System Level Humidity: Intellec® Series Monitor Source Listing, 9800605 50 - 55°C (41°F-131°F) 16 0 -32°C (61 OF - 90°F) Additional manuals may be ordered from any Intel sales representative or distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. 20% to 80% ORDERING INFORMATION Part No. Description MDS-505* Integrated Processor Card upgrade package for Intellec® Series II Microcomputer Development System (110V 160Hz or 220V 150Hz). Upgrades Models 220,221,230,231, 240, and 241 to the performance of the 8085A-2 based systems. "'MOS" is an ordering code only, and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corp. 12·7 . MODEL 556 , iAPX 86 RESIDENT PROCESSOR BOARD PACKAGE • High Performance 8086·Based CPU Board for Increased Intellec® Development System Performance and iAPX 86188 Development Environment· • Software Applications Debugger for iAPX 86/88 User Programs • Supports Full Range of iAPX 86/88· resident, High·level Languages: PL/M·86/88, PASCAL·86/88, and FO RTRAN·86/88 • Upgrades Intellec® Series 11180, Series 1I/85,Model 800 Microcomputer Development Systems to the Functionality of Series III Systems • Includes iAPX 86/88 Resident Relocating Macro Assembler, Linker, Locater and Librarian • 96K Bytes of ,User Program RAM Memory Available for iAPX 86188 User Programs • Dual·Processor Disk Operating System Software with CRT·based Editor· The Model 556 is a performance enhancement package for Intellec® Series 11/80, Series 11/85 and Model 800 (requires Model 556E) Development Systems, specifically designed for iAPX 86/88 microprocessor development. The Model 556 includes two printed circuit boards (an iAPX 86-based CPU board and a 64K memory board), dual-processor disk operating system software, CRT-based editor, iAPX 86/88 Resident Relocating Macro Assembler, Linker, Locater and Librarian; software applications debugger for iAPX 86/88 user programs; and complete user documentation., 12-8 AFN·01721A MODEL 556 FUNCTIONAL DESCRIPTION Hardware Components When the 8086 is executing a program, the 8-bit CPU offloads all 1/0 activity and operates as an intelligent 1/0 controller to double buffer data to and from the 8086. The 8086 also provides an execution vehicle for 8086 and 8088 object code. An added benefit of two host microprocessors is that 8-bit translations and applications are handled by the 8-bit CPU, and 16-bit translations and applications are handled by the 8086. This feature provides complete compatibility for current systems and means that software running on current Intellec Development Systems will run on the new system. Resident Processor Board (RPB-86)- The heart of the RPB-86 is an Intel 8086 16-bit HMOS microprocessor, running at 5.0 MHz. 64K bytes of RAM memory is provided on the board with transparent refresh from the Intel 8202 dynamic RAM controller. 16K bytes of ROM is on board, preprogrammed with an iAPX 86/88 applications debugger. The debugger provides features necessary to debug and control execution of application software for the iAPX 86/88 microprocesors. The RPB-86 occupies two card slots in an Intellec cardcage. The processors use interrupts for interprocessor communications. High-Level Languages for iAPX 86/88- The Model 556 allows the current Intellec system user to take advantage of a breadth of new resident iAPX 86/88 high-level languages: PUM 86/88, PASCAL 86/88, and FORTRAN 86/88. The iAPX 86/88· Resident Macro Assembler and these high-level language compilers execute on the 8086 host CPU, thereby increasing system performance. RAM Memory Board-The memory board contains 64K bytes of read/write RAM memory and interfaces directly to the Intellec system bus. Ref~esh hardware is provided onboard for all the dynamic memory elements. Data buffering occurs for all data written to or read from the 64K memory array. Expanded Program Memory-By adding a Model 556 to an existing Intellec Development System, 96K bytes of user program RAM memory are made available for iAPX 86/88 programs. System memory is expandable by adding additional RAM memory modules. This, combined with the two host CPU system architecture, dramatically increases the processing power of the system. SYSTEM FEATURES The Model 556 offers many key advantages for iAPX 86/88 applications and Intellec Development Systems: enhanced system performance through a dual host CPU environment, a full spectrum of iAPX 86/88-resident high-level languages, expanded user program space for iAPX 86/88 programs, and a powerful high-level software applications debugger for iAPX 86/88 microprocessor software. Software Applications Debugger- The RPB-86 contains the applications debugger which allows iAPX 86/88 programs to be developed, tested, and debugged within the Intellec system. The debugger provides a subset of InCircuit Emulator commands such as symbolic debugging, control structures and compound commands specifically oriented toward software debug needs. Dual Host CPU-The addition of a 16-bit 8086 to the existing 8-bit host CPU increases iAPX 86/88 compilation speeds and provides for iAPX 86/88 code execution. SPECIFICATIONS Environmental Characteristics Resident Processor Board (RPB-86): 8086 based, operating at 5.0 MHz 2 RAM - 64K bytes on the CPU board ROM - 16K bytes (applications debugger) Bus - MULTIBUS architecture; 5 MHz maximum transfer rate Operating Temperature: 0° to 35°C (32°F to 95°F) Relative Humidity: To 90% without condensation Equipment Supplied Electrical Characteristics iAPX 86 Resident Processor Board (RPB-86) 64K Byte RAM Memory Board iAPX 86/88 Applications Debugger Self-test Diagnostics iAPX 86/88 Resident Macro Assembler and Utilities Dual Processor Disk Operating System Software CREDIT™ CRT-based text editor DC POWER SUPPLY Voltage Requirements Current Requirements (Amperes Max.) +5±5% Volts +12±5%Volts -12±5% Volts 8.6 A 1.0 A 0.05 A 12-9 AFN.Q1721A MODEL 556 Documentation Supplied Intel/ec Series 1/1 Microcomputer Development System Product Overview, 1 2 1 5 7 5 · . Intel/ec Series III Microcomputer Development System Installation and Checkout Manual, 121612 Intel/ec Series III Microcomputer Development System Console Operating Instructions, 121609 Intellec Series 11/ Microcomputer Development System Schematic Drawings, 121642 Intellec Series III Microcomputer Development System Pocket Reference, 121610 ISIS-II CREDIT (CRT-Based Text Editor) User's Guide, 9800902 Intellec Series 1/1 Microcomputer Development System Programmer's Reference, 121618 ISIS-II CREDIT (CRT-Based Text Editor) Pocket Reference,9800903 iAPX 86/88 Family Utilities User's Guide for 8086-Based Development Systems, 121616 The 8086 Family User's Manual, 9800722 B086/8087/80B8 Macro Assembly Language Reference Manual for BOB6-Based Development Systems, 121627 B086/8087/B088 Macro Assembly Language Reference, 9800749 Pocket 8086/8087/8088 Macro Assembler Operating Instructions for B086-Based Development Systems, 121628 The 8086 Family USfir's Manual, Numerics Supplement, 121586 Additional manuals may be ordered from any Intel sales representative or distributor office, or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number MDS-556* DS5561 KIT essor board (IPC-85). This upgrade package is for Intel.lec Series 11/80 Development Systems (110V/60 Hz or 220V/50 Hz) and upgrades all Intellec Series 11/80 Models to the full performance and functionality of an Intellec Series III Development System. Description Model 556 performance upgrade package forlntellec Series 11/80, Series 11/85 Microcomputer Development Systems (110V/60 Hz or 220V/50 Hz). Spe· cifically designed for iAPX 86/88 microprocessor development. Upgrades all Intellec Series 11/80 and Series 11/85 models to the functionality of an Intellec Series III Development System. Performance package for Intellec Series 11/80 Microcomputer Development Systems. Specifically designed for iAPX 86/88 microprocessor development. The 5561 package consists of the Model 556 software and hardware performance package, and the integrated 8085 proc- 12-10 MDS-556E* Performance package for Intellec Model 800 Microcomputer Development Systems. Specifically designed for iAPX 86/88 microprocessor development. Upgrades Model 800 to the functionality of an Intellec Series III. *"MDS" is an ordering code only, and is not used as a product name or trademark. MDS is a registered trademark of Mohawk Data Sciences Corp. AFN-01721A MODEL 590 NETWORK MANAGER UPGRADE PACKAGE INTELLEC® NETWORK DEVELOPMENT SYSTEM-I (NDS-I) • Upgrades either Intellec® Model 240 or Intellec® Model 245 to a NOS-I Network Manager • Provides a distributed development system environment for Intellec® microcomputer development system users • Supports all existing Intellec® development systems as workstations: Intellec® Model 800, Series 11/80, Series 11/85, and Series III models • Shared background line printer • Functions as a Project Management tool to increase programmer productivity and coordinate large program development • Supports up to 8 workstations operating concurrently • Files stored on central hard disk shared among workstations • Provides substantial performance enhancement for floppy disk-based systems • Distributes the cost of central mass storage among workstations The Intellec® Network Oevelopment System (NOS-I) is designed to provide the user with tools necessary to support a distributed development system environment. NOS-I enables up to eight Intellec development systems to share both a common line printer and disk storage. Oisk files may reside on either one or two central hard disks, providing up to fifteen megabytes of storage capacity. The major component of NOS-I is the Network Manager which controls all communications between the workstations and the shared disk. The powerful multitasking operating system of the Network Manager provides public/private file control for all files resident on the hard disk. Printer sharing operates as a background task concurrent with other NOS-I operations. As a project management tool, NOS-I helps coordinate the numerous program modules common to large mUlti-man projects. Productivity is increased and development time is shortened. This upgrade package converts an existing Model 240 or 245 into a NOS-I Network Manager. 12·11 12167().OOlRA MODEL 590 ICB moves data between the workstations and the Network Manager with a burst of data transfer rate of 40 kbytes per second. COMPONENTS The NDS-I Network Manager upgrade package consists of an interconnect board, internal cable, line terminators, and Network Manager software. A block diagram of the Network Manager is shown in Figure 1. Software Components Included with the Model 590 is the Network Manager operating system which controls all communications between the workstations and the shared hard disk. The operating system software provides concurrent disk input/output, communications, and file management. It offers substantial workstation performance enhancement compared to standalone, floppy disk-based development systems. The Network Manager operating system provides public/private file control for all files resident on the hard disk. The public/private file control is a useful project management tool to help coordinate the numerous programmers and modules common to large development projects. Interconnect Communications An Interconnect Board (ICB), which occupies one slot in the Network Manager and each workstation, provides the communications interface between the workstations and the Network Manager. The ICB is a MULTIBUS™ compatible board with an 8085 microprocessor, 1.25 kbytes of RAM and 4 kbytes of ROM. The ICB accepts a command from the master CPU, executes the command without intervention by the master CPU, and signals completion by setting a flag and generating a Multibus interrupt. The TO WORKSTATION INTERCONNECT BOARD INTERCONNECT BOARD HARD DISK CONTROLLER 80SSA CPU 64K RAM 4K ROM C A B L E B U S MULTIBUS'" BUS TOPIO BUS Figure 1. Inteliec® NDS-I Network Manager Block Diagram 12-12 AFN.Q1S94A intel' MODEL 590 SPECIFICATIONS Model 596 NOS-I 10 ft. Interconnect Cable Model 597 NOS-I 20 ft. Interconnect Cable Equipment Supplied Interconnect Board Internal Cable Two NOS-I Line Terminators Network Manager Operating System Network Manager Oiagnostics Optional Equipment Model 595 NOS-I Workstation Interconnect Package: Includes Interconnect board and workstation software to convert any Model BOO, Series II/BO, Series 11/85, or Series III to a NOS-I workstation. Model 743 (11 OV) Add on hard disk unit with cables and disk cartridge. Model 744 (220V) Add on hard disk unit with cables and disk cartridge. Model 746 Box of 5 blank hard disk cartridges. Reference Manuals Network Manager Console Operating Instructions, 121645. ORDERING INFORMATION Part Number Description MOS'-590 NOS-I Network Manager Upgrade Package: Includes interconnect board, internal cable, and Network Manager software . • MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark of Mohawk Data Sciences Corp. 12·13 AFN·D1594A inter MODEL 810 SOFTWARE DEVELOPMENT MODULE • Adds text entry, assembly, and debug to iSBC™ configurations. • ROM-based Editor, Assembler, and Monitor provide resident software development and debugging. • User selects standard chassis and Intel CPU board to host development software module. • Symbolic Assembler produces absolute code for immediate loading and execution. • Low-cost, software development capability for Intel iSBC™ 80/1 OB, 80/24, and 80/30 Single Board Computers. • Development software fits easily into user-defined Intel 8080/8085 iSBC™ configuration by residing on standard iSBC™ 464 Memory Expansion Board. • Monitor debugger modifies and dumps memory and registers; sets breakpoints. The Model 810 Software Development Module provides complete software development capability for Intel single board computers. By inserting the standard iSBC™ memory expansion board into an Intel 8080/8085 user-defined iSBC system, you gain text entry, assembly and debug capability in your application system. (See figure 1.) After using the Model 810 to develop and debug your application, the board may be left in the system to be re-used or removed to give a complete, self-contained single board computer application. The 8080/8085 Symbolic Assembler is a subset of Intel's full 8080/8085 Assembler used on Intellec® Microcomputer Development Systems. Source code is entered from a user-supplied console (ASR 33 Teletype or equivalent), and debugging is done by a ROM-based Monitor for either the iSBC 80/1 DB, 80/20-4,80/24, or 80/30 Single Board Computer. After assembly and execution, completed programs may be punched to paper tape for archiving and later programmed into PROM. 12·14 121599-001 Rev. A inter MODEL 810 FUNCTIONAL DESCRIPTION SOFTWARE COMPONENTS System Environment. The Model 810 has three software components: The Software Development Module lets you put together your own single-board-computer-based development system with standard off-the-shelf Intel products: an Intel CPU board, chassis and the Model 810 Software Development Module. The system is ideal for low-cost editing, assembling and debugging of small program modules. Text Editor allows you to enter and update your programs from the TTY terminal; and when you have completed your editing session, your program may be saved on paper tape. All Editor commands are single character to save typing time. Assembler allows symbolic program development. The Assembler translates the source code into object code for execution. The object code may be stored on paper tape or in RAM for intermediate testing. HARDWARE COMPONENTS Debug Monitor controls input and. output and provides you with debugging capability. It allows you to examine register and memory locations and interrupt the program at userspecified breakpoints. The three monitor variants are: 1) iSBC 80/10B (8080 CPU), 2) iSBC 80/20-4 (8080 CPU), iSBC 80/24 (8085 CPU), 3) iSBC 80/30 (8085 CPU) Single Board Computers. The Model 810 is a modified iSBC 464 Memory Expansion Board that includes nine 2K-byte ROM's containing the Text Editor and 8080/8085 Assembler. Also supplied are three separate 2K-byte ROM's, each containing a debug monitor for one of the three variants of CPU boards supported. The three Monitor ROM's are included to allow selection of the appropriate monitor for the processor board in the user's system. The user must also provide'a chassis, 16K RAM (iSBC 016 or on-board 80/30 memory), an ASR 33 Teletype or equivalent, an iSBC 530 Teletype Adapter (for iSBC 80/20-4, 80/24, and 80/30 Single Board Computers), and an iSBC 955 (or equivalent) RS232C Serial I/O Cable Set. INPUT /OUTPUT The standard interface enables input/ouput of data from the TTY keyboard, printer, and paper tape read/punch. "NOT REaUIRED WITH iSBC80/10A OR 80/10B PROCESSOR SYSTEM CHASSIS PROCESSOR BOARD 16K RAM MEMORY BOARD" • "NOT REQUIRED WITH iSBC 80/30 PROCESSOR o InciudedinModel810 Figure 1. Model810 Software Development Module in Target System 12·15 AFN-01386A inter MODEL810 MEMORY MONITOR COMMANDS The user must provide a minimum of 16K of RAM (iSBC 016 RAM Board. or on-board iSBC 80/30 RAM). All 110 requests are serviced through a common RAM-board jump table stored in RAM. The user may redefine symbol table buffer lengths in RAM to fit a specific application. Command Operation Memory Conlrol: Display Prints contents of specified range of memory. Insert Inserts n'ew data into memory. Move Copies contents of specified portions of memory into designated RAM locations. Substitute Modifies RAM on a byte-by·byte basis. Register Control: X Prints and allows you to modify contents of specified register(s}. Paper Tape ItO Commands: SYSTEM TEST A Confidence Test is provided to perform a checksum test of Monitor, Editor, and Assembler ROM's, and a read Iwrite test of system RAM. Read Reads paper tape from reader and loads data into memory at specified location. Write Punches on tape the contents of specified memory area. Program Execution Command: Execute (Go) Transfers control to your program at a specified address. One or two breakpOints may optionally be set. SPECIFICATIONS I/O INTERFACES ROM: 20K (2K Monitor, 4K Editor, 14K Assembler) iSBC 80/10A and iSBC 80/10B boards provide 20 mA current loop for TTY. iSBC 80/20-4, iSBC 80/24, and iSBC 80/30 boards require iSBC 530 TTY Adapter to convert RS232C to 20 mA current loop. Bus: Multibus interface compatible PHYSICAL CHARACTERISTICS HARDWARE REQUIRED Choice of iSBC single board computer and iSBC chassis as follows: Single Board Computer iSBC 660 iSBC 655 iCSSO Chassis Chassis Chassis iSBC80/10B X X X iSBC 80/20-4 X X X iSBC 80/24 X X X iSBC 80/30 X X X Also required: iSBC 016 RAM Expansion Board (not required with iSBC 80/30 Single Board Computer) iSBC 955 RS232C Serial 1/0 Cable Set (or equivalent) iSBC 530 Teletype Adapter Weight 294 gm (10.7 oz) Length 30.48cm (12 in) Height 17.15cm (6.75 in) 1.27cm (0.5 in) Depth ELECTRICAL CHARACTERISTICS DC Power (max.) Voltage: +5V DC ±5% Current: 2.0 amps max. EQUIPMENT SUPPLIED Model 810: iSBC 464 board with nine ROM's containing the Text Editor and Assembler, and three loose ROM's containing the Monitors (one ROM for each CPU board monitor variant). REFERENCE MANUALS The following material is shipped with the product: OPTIONAL HARDWARE SUPPORTED 121581 Model 810 Software Development Module User's Guide 121582 Model 810 Software Development Module Installation Manual 9800301 808018085 Assembly Language Programming Manual iSBC 80/10A Single Board Computer-interchangeable with iSBC 80/10B Single Board Computer iSBC 032 RAM Expansion Board (32K RAM) 12-16 AFN-01386A MODEL 810 The following manuals for the single board computers and chassis used in the target system can be ordered from Intel Corporation Literature Department. 9800488 iSBC 032™ Random Access Memory Board Hardware Reference Manual 9800643 iSBC 464™ PROM/ROM Board Hardware Reference Manual 9800708 iSBC 604/614™ Cardcage Hardware Reference Manual 9800298 iSBC 635™ Power Supply Hardware Reference Manual 9800803 iSBC 640™ Power Supply Hardware Reference Manual 9800709 iSBC 655™ System Chassis Hardware Reference Manual 9800505 iSBC 660™ System Chassis Hardware Reference Manual 9800799 iCS 80™ Industrial Chassis Hardware Reference Manual 9800798 iCS 80™ Industrial System and Installation Guide 9800230 iSBC 80/10A'M Single Board Computer Hardware Reference Manual 9803119 iSBC 80/10B n , Single Board Computer Hardware Reference Manual 9800317 iSBC 80/20-4TM Single Board Computer Hardware Reference Manual 142648 iSBC 80/24™ Single Board Computer Hardware Reference Manual 9800611 iSBC 80/30TM Single Board Computer Hardware Reference Manual 9800279 iSBC 016™ 16K RAM Expansion Board Hardware Reference Manual ORDERING INFORMATION Part No. MDS-810* Description Software Development Module. ROM based editor, symbolic assembler, and debug monitor provide complete development support when combined with user's target iSBC 8080/8085 system . • "MOS" is an ordering code only, and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corp. 12·17 AFN-01386A inter MAINFRAME LINK FOR DISTRIBUTED DEVELOPMENT • Integrates user mainframe resources with Intellec® Development Systems. • Software runs under ISIS-II on any Intellec® Development System. • Communicates with remote systems on dedicated or switched (dial-up) telephone lines. • Uses IBM 2780/3780 standard BISYNC protocol supported by a majority of mainframes and minicomputers. • Package also includes tests and a connector for loop-back self-test capability. • Protocol supports full error detection with automatic retry. The Mainframe Link consists of software, modem cable to connect the development system to the modem and a loopback connector for diagnostic testing. The software runs under ISIS-lion Intellec Development Systems. It emulates the operation of an IBM 2780 or 3780 Remote Job Entry (RJE)terminal to (1) transmit ISIS-II files to a remote system or (2) receive files from a remote system using standard BISYNC 2780/3780 protocol. The remote system can be any mainframe or minicomputer which supports the IBM 2780 or 3780 communications interface standard. Files may contain ASCII or binary data so that either program source files (ASCII) or program object files (binary) may be transmitted. The Mainframe Link allows the user to integrate in-house mainframe resources with Intellec Microcomputer Development resources. The mainframe can be used for storage, maintenance and management of program source and object files. The program source can be downloaded to a development system for compilation, assembly, linkage, and/or location. The linked modules can be transmitted and saved on the mainframe to be shared by all programmers. The linked program can then be downloaded to a development system for debugging using ICE emulation. 12·18 121633-Q1A intel' MAINFRAME LINK FEATURES Automatic translation from ASCII to EBCDIC and vice versa • Runs under ISIS-II on any Intellec® Microcomputer Development System. • Communicates with a remote system using IBM 2780/3780 standard BISYNC protocol, which is supported by a majority of minicomputers and mainframes, on dedicated or switched (dial-up) telephone lines. • The modem cable supplied with the package can be used to connect the Intellec® Development System to the modem (or modem eliminator) using the standard RS232C port. • Supports user selectable data transmission rates of up to 9600 baud. • Package includes diagnostic tests used to verify the operation of the Intellec® Development System using the loop-back connector supplied and data transmission up to the modem using the analog loop-back feature. • System can be configured to match the requirements of the installation, i.e., using modem eliminators for connections up to fifty (50) feet, or by using modems and telephone lines. • Software can be configured from several configuration options such as: 2780, 3780 or Intel Mode Receive chaining for receiving multiple files • Intel mode is used mainly for file transfers between two Intellec® Development Systems. The files are duplicated exactly. • Console commands support all standard features including: SEND data in Transparent or Non-transparent mode, with or without translation to EBCDIC RECEIVE in Transparent or Non-transparent mode, with or without translation to EBCDIC. Supportfor an IBM RJE console (such as HASP) • Special utility programs are provided. STRZ strips extra binary zero's from the end of object files. CONSOl assigns system console input to an ISISII disk file. • Can process commands interactively from the console or sequentially from an ISIS-II file under the SUBMIT facility for semi-automatic batch operation. • Error detection in line transmission and error recovery by automatic retransmission. • A special command such as DIAGNOSE, allows logging of all data activity on the line, during transmission and reception. • When not used for communicating with the mainframe, the Intellec® Development System is available as a complete, stand-alone system. Transparent mode for binary data Non-transparent mode for ASCII data BENEFITS • Allows the customer to use an in-house mainframe or minicomputer for program sourcepreparation, editing, back-up and maintenance using inexpensive CRT's and multi-terminal access. The common files may be shared and others protected. • Many programmers can use and share the highperformance devices normally available on large computer systems, e.g., fast printers to reduce listing time, the large capacity disks with their fast access time to store large program files. • The source files can be downloaded using the Mainframe Link to an Intellec Development System (e.g., Model 240 or 245) for compilation, linking and locating. 12-19 • The compiled and/or linked object files may be transmitted back to the remote for storage. Updates and version numbers and dates can be tracked to ensure that the latest version is always used and back-up files are available. Binary object files can be later downloaded to an Intellec Development System for debugging using an ICE emulator. • In short, provides a powerful and flexible tool combining the best of both. micro and mainframe worlds, i.e., powerful CPU with large disk capacity, file sharing, multi-terminal access, etc., from a mainframe or minicomputer with Intel's versatile and compatible software support systems (including PLlM, PASCAL, FORTRAN, Assembler, R & l) and sophisticated debugging tools such as ICE emulators. AFN·Ol549A intel' MAINFRAME LINK SPECIFICATIONS Remote System Requirements Operating Environment • IBM 2780/3780 BISYNC protocol as supported by a majority of mainframes and minicomputers including: all IBM-360/370 Systems, PDP-11/70, VAX-11/780, Data General ECLIPSE. Required Hardware: Intellec® Microcomputer Development System Model 800 Models 220, 225, 230, 235, 240 or 245 64KB of Memory One Diskette Drive Single or Double Density • Users should purchase this standard software package from the remote system vendor and any additional required hardware such as a synchronous communications interface. • The operating system at the remote must be configured (SYSGEN'ed) with correct options such as line address, 2780 or 3780, ... Communication Equipment Requirements System Console Intel CRT or non-Intel CRT The Inteliec Development System may be connected to the remote system using anyone of the following methods: Recommended Hardware for Compilation: • For short distances (up to 50 feet), use a synchronous modem eliminator (e.g.,SPECTRON ME-81 FS-2). Hard Disk (Models 240, 245, or Model 740 Upgrade) Additional Hardware Required for Model 800 iSBC-955™, iSBC-534™ • For distances up to four miles, use short haul synchronous modems and telephone lines. Required Software: • For distances greater than four miles, use synchronous modems and telephone lines. The following BELL modems or their equivalents are recommended: ISIS-II Diskette Operating System Single or Double Density BELL 201 C 2400 bits/second (half duplex, switched line) BELL 208A 4800 bits/second (full duplex, leased line) BELL 208B 4800 bits/second (half duplex, switchedline) BELL 209A 9600 bits/second (full duplex, leased line) Documentation Package Mainframe Link. User's Guide (121565-001 ) Shipping Media Flexible Diskettes Single and Double Density • Modems at either end must be compatible. ORDERING INFORMATION Part Number Description *MDS-384 Kit Mainframe Link for Distributed Development *MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation. 12-20 AFN·01549A CREDIT™ CRT-BASED TEXT EDITOR MICROCOMPUTER DEVELOPMENT SYSTEMS • Provides Interactive Editing of ASCII Text Files • Displays Full Page of Text • CRT Screen Display with Cursor-Based Editing Using Single Character Commands for Insertion, Deletion, Page Forward and Backward • Dynamic Macro Command Definition • Command Line Editing with String Search, Deletion, Insertion and Move • Operates Under the ISIS-II Operating System on Intellec® and Intellec® Series II Microcomputer Development Systems CREDIT is a CRT-based text editor that aids in the creation and editing of ASCII text files on Intellec Microcomputer Development Systems. Once the text has been edited to the programmer's satisfaction, it can be directed to the appropriate language processor for compilation, assembly or interpretation. CREDIT features are easy to use and simplify the change or rearrangement of text files. CREDIT runs under ISIS-II on any Intellec or Intellec Series II Microcomputer Development System with an Intel supplied CRT, disk drive(s) and 64K bytes of memory. Alternatively, it may be configured to run with non-Intel CRTs supporting cursor controls. There are two editing modes in CREDIT: a screen mode and a command line mode. The screen mode makes full use of the display characteristics of the CRT. The cursor position is visible on the screen and can be positioned by use of the cursor control keys. Display text can be corrected in two ways-either by simply retyping the text, or by using the single-stroke control keys. Specifically, the single-character control keys are used for change, deletion, insertion and paging forward and page backward. ·In addition to screen editing, there is command line editing, whiQh includes commands for more powerful and complex editing tasks. Some examples of functions available in the command line mode are search, block move and copy, macro definition and manipulation of external files. These easily used, high-level commands facilitate complex editing and speed microcomputer development. 12-21 9800926·02 Rev. B intJ CREDIT™ EDITOR CREDIT™ EDITOR FEATURES • Change CREDIT features with ALTER command • Two editing· m.odes: cursor-driven ·screen editing and command line context editing • Conditional iteration • Use'r~defined tab settings • Symbolic tag positions • Automatic disk full warning CRT Editing Includes: • Displays full page of text • Single control. key c.ommands for insertion, deletion, page forward and backward • Type~over correction and replacement· . • Immediate feedback of the results of each operation • The current state of the text ·is always represented on the display Command Line Editing Includes: • String search and substitute • String delete, change or insert • • • • Block move Block copy. User-defined macros' External file handling • Runs under ISIS-IISUBM.IT facility • Option to exit at any time with original file intact • HELP command BENEFITS OF CREDIT™ EDITOR. • Speeds source program creation and editing-lowers the cost ofthese functions • Easy to learn and use":": -source text isclearly displayed' -single command keys used for CRT editing -HELP command is available' for easy reference when needed . • Complements existing software - source text us.ed for PLlM, pASCAL, FORTRAN, BASIC, and Assemblers • Aids in the management of source file libraries • Offers full use of Intel supplied' CRT cursor functions' ISIS-II LOADER DEBUG VIA MONITOR OPTIONAL ICE'· IN-CIRCUIT EMULATOR PROM PROGRAMMER Figure 1. Microcomputer Program Development AFN-Ol083B CREDIT™ EDITOR SCREEN MODE COMMANDS MOVE CU RSOR: Use the directional arrow keys on the keyboard. REPLACE: Type over existing text with replacement new text. INSERT: Insert one character. Insert more character. DELETE: than one Delete one character. Set boundaries and delete all text between them. PAGE: Next Page: Get next screenful of text. Previous Page: Get previous screenful. View Page: Rewrite current page with possible reframing. COMMAND MODE COMMANDS HELP: Display summary commands. PRINT: Print n lines or up to tag. JUMP: Move cursor position characters or to tag. TAGS: of EXIT: any INSERT: Insert before CP between delimiters. text DELETE: Delete n characters, characters up to tag. or Delete n lines backward. or n Transfer Copy block of text from tag1, for n lines or through tag2, to cursor position. MACROS: all forward FIND: Search for text; move pointer if found. SUBST: newtext replaces oldtext if oldtext is found. (Optional query to user before replacement.) FILES: Open file "filename" Reading or Writing. Transfer move: like Transfer Copy but the old copy is deleted. ADVANCED EDITING COMMANDS Normal exit. Exit Quit: Abandon changes to edit file. Move cursor position n lines forward or backward. MOVE: Set tag n, n = 0-9. Tag n is referenced as Tn. Close the current Read (Write) file. Define a macro. Delete a macro, or all macros if name=*. for external Go to beginning of current Read file. Expand and execute macro contents, command mode. Read and insert n lines from the Read file. Expand and execute macro contents, screen mode. Write n lines to the external Write file. Print names and definitions of all macros. 12-23 AFN·01083B GET: Get contents command li.ne. of file into QUERY: Query User: set Query Flag accordingly. Do command only if Query Flag is True. Do command .only if Query Flag is False. YES: Do command only if (Search) Flag .is False. . Yes Do command only if (Search) Flag is False. Yes LOOP: Exit current iteration loop. ALTER: Configure the command input keys to work with alternative CRTs. USER: Copy text to the console. HELP: Display summary commands. . SPECIFICATIONS Required Software Operating Environment ISIS-II Diskette Operating System -Single or double density of Required Hardware Intellec® Microcomputer Development System -Model 800 or Series II with 64k bytes of RAM memory -Series III Documentation Package CREDIT® (CRT-Based Text Editor) User's Guide (9800902) CREDIT® Pocket Reference (9800903) Diskette Drive(s) -Single or double density System Console -Intel supplied CRT or alternative CRT supporting cursor controls Shipping Media Flexible Diskettes -Single or double density Optional Hardwar.e Line Printer Additional diskette drivels) ORDERING INFORMATION Part Number. Description MDS-360* ISIS-II CREDIT CRT-Based Text Editor Requires Software License *MDS is an ordering code only, and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation. 12·24 1:~;~~;~;~;;f:~~;~;;;mmmt~tft~ttrmmttj~1tffttfttttt~::::::}~?)::::::::::::::::~:~:>:::::<::::::: Flexible and Hard Disk Systems 13 INTELLEC® SINGLE/DOUBLE DENSITY FLEXIBLE DISK SYSTEM Flexible Disk System Providing High Speed Input/Output and Data Storage for Intellec® Microcomputer Development Systems II Data Recorded on Double Density Flexible Disk is in Soft-Sectored Format Which Allows Y2 Million Byte Data Capacity with Up to 200 Files Per Flexible Disk II Available in Both Single Density and Double Density Systems II II Data Recorded on Single Density Flexible Disk Is in IBM Soft-Sectored Format Which Allows 1f4 Million Byte Data Capacity with Up to 200 Files Per Flexible Disk Associated Software Supports Up to Four Double Density Drives and Two Single Density Drives, Providing Up to 2.5 Megabytes of Storage in One System II Dynamic Allocation and Deallocation of Flexible Disk Sectors for Variable Length Files 11 The Intellec Flexible Disk System is a sophisticated, general purpose, bulk storage peripheral for use with the Intellec Microcomputer Development System. The use of a flexible disk operating system significantly reduces program development time. The software system known as ISIS-11 (Intel System Implementation Supervisor), provides the ability to edit, assemble, compile, link, relocate, execute and debug programs, and performs all file management tasks for the user. I 13-1 FLEXIBLE DISK SYSTEM puter Set. This 8·bit processor includes four 3002 Cen· tral Processing Elements (2·bit slice per CPE), a 3001 Microprogram Control Unit, and 512x32 bits of 3604 programmable·read·only·memory (PROM) which stores the microprogram. It is the execution of the microprogram by the microcomputer set which actually effects the control capability of the Channel Board. HARDWARE The Intellec® flexible disk system provides direct access bulk storage, intelligent controller, and two flex· ible disk drives. Each single density drive provides million bytes of storage with a data transfer rate of 250,000 bits/second. The double density drive provides '/2 million bytes of storage with a data transfer rate of 500,000 bits/second. The controllers are implemented with Intel's powerful Series 3000 Bipolar Microcomputer Set. The controllers provide interface to the Intellec System bus. Each single density controller will support two drives. Each double density controller will support up to four drives. The flexible disk system records all data in soft sector format. 1/; This board is the same for either single or double density drives, except that the Series 3000 microcode is dif· ferent. INTERFACE BOARD The Interface Board provides the flexible disk controller with a means of communication with the flexible disk drives, as well as with the Intellec system bus. Under control of the microprogram being executed on the Channel Board, the Interface Board generates those signals which cause the read/write head on the selected drive to be loaded (i.e., to come in contact with the flex· ible disk platter), cause the head to move to the proper track and verify successful operation. The Interface Board accepts the data being read off the flexible disk, interprets synchronizing bit patterns, checks the valid· ity of the data using a cyclic redundancy check (CRG) polynomial, and then transfers the data to the Channel Board. The single/double density flexible disk controllers each consists of two boards, the Channel Board and the Inter· face Board. These two printed circuit boards reside in the Intellec System chassis. The boards are shown in the photograph, and are described in more detail in the following paragraphs. During write operations, the Interface Board outputs the data and clock bits to the selected drive at the proper times, and generates the CRC characters which are then appended to the data. When the flexible disk controller requires access to Intellec system memory, the Interface Board requests the DMA master control of the system bus, and gener· ates the appropriate memory command. The Interface Board also acknowledges I/O commands as required by the I ntellec bus. SINGLEIDOUBLE DENSITY CHANNEL BOARD The Flexible Disk System is capable of performing seven different operations: recalibrate, seek, format track, write data, write deleted data, read data, and verify CRC. The channel board is different for single and double den· sity drives, due to the different recording techniques used. The single density controller boards support one set of dual single density drives. The double density controller boards support up to two sets of dual double density drives (four drives total). DOUBLE DENSITY INTERFACE BOARD ·(SINGLE DENSITY INTERFACE BOARD IS SIMILAR TO THE ONE SHOWN ABOVE) The double density controller may co·reside with the Intel single density controller to allow conversion of single density flexible disk to double density format, and provide up to 205M bytes of storage. CHANNEL BOARD The Channel Board is the primary control module within the flexible disk system. The Channel Board receives, decodes,and responds to channel commands from the Central Processor Unit (CPU) in the Intellec system. The Channel Board can access a block of Intellec system memory to determine the particular flexible disk opera· tions to be performed and fetch the parameters required for the successful completion of the specified opera· tion. FLEXIBLE DISK DRIVE MODULES Each flexible disk drive consisis of read/write and con· trol electronics, drive mechanisms, read/write head, track positioning mechanism, and the removable flexible disk platter. These components interact to perform the following functions: • Interpret and generate control signals • Move read/write head to selected track • Read and write data The control functions of the Channel Board have been achieved with an 8·bit microprogrammed processor, designed with Intel's Series 3000 Bipolar Microcom· 13-2 FLEXIBLE DISK SYSTEM ASSOCIATED SOFTWARE - INTEL SYSTEMS IMPLEMENTATION SUPERVISOR (1515·11) The Flexible Disk Drive System is to be used in conjunction with the ISIS-II Operating System. ISIS-II provides total file management capabilities, file editing, 1515·11 OPERATIONAL ENVIRONMENTAL ISIS-II 32K bytes RAM memory 48K bytes when using Assembler Macro feature 64K bytes when using PUM or Fortran System Console Single or Double density Flexible Disk Drive HARDWARE SPECIFICATIONS MEDIA Single Density Flexible Disk One Recording Surface IBM Soft Sector Format 77 TrackslDiskette 26 Sectors/Track 128 Bytes/Sector Double Density Double Density Specified Flexible Disk One Recording Surface Soft Sector Format 77 TrackslDiskette 52 Sectors/Track 128 Bytes/Sector PHYSICAL CHARACTERISTICS CHASSIS AND DRIVES Mounting: Height: Width: Depth: Weight: Table-Top 5.7 in. (14.5 cm) 17.6 in. (44.7 cm) 19.4 in. (49.3 cm) 43.0 lb. (19.5 kg) library management, run-time supports, and utility management. ISIS-II provides automatic implementation of random access disk files. Up to 200 files may be stored on each '14 million byte flexible disk for single density system or on each '12 million byte flexible disk for double density system. For more information, see the ISIS-II data specification sheet. FLEXIBLE DISK DRIVE PERFORMANCE SPECIFICATION Single Density Capacity (Unformatted): Per Disk Per Track Capacity (Formatted): Per Disk Per Track Data Transfer Rate Access Time: Track-to-Track Head Settling Time Average Random Positioning Time Rotational Speed Average Latency Recording Mode MEDIA CHASSIS DC Power Supplies Supplied Internal to the Cabinet AC Power Requirements 3-wire input with center conductor (earth ground) tied to chassis Single-phase, 115 VAC; 60 Hz; 1.2 Amp Maximum (For a Typical Unit) 230 VAC; 50 Hz; 0.7 Amp Maximum (For a Typical Un)t) Temperature: Operating: Non-Operating: Humidity: Operating: Non-Operating: flEXIBLE DISK OPERATING SYSTEM CONTROLLER DC Power Requirements (All power supplied by Intel/ec Development System) 5V @ 3.75A (typ), 5A (max) INTERFACE BOARD Single Density 5V @ 1.5A (typ), 2.5A (max) 3.1 megabits 41 kilobits 6.2 megabits 82 kilobits 2.05M bits 26.6K bits 250 kilobits/ sec 4.10 megabits 53.2 kilobits 500 kilobits/ sec 10 ms 10 ms 10 ms 10 ms 260 ms 360 rpm 83 ms Frequency Modulation 260 ms 360 rpm 83 ms M2FM ENVIRONMENTAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS CHANNEL BOARD Single Density Double Density Double Density 5V @ 3.75A (typ), 5A (max) Double Density 5V @ 1.5A (typ), 2.5A (max) -10V @ O.lA (typ), 0.2A (max) 15.6'C to 51.7'C 5'C to 55'C 8 to 80% (Wet bulb 29.4 'c) 8 to 90% DRIVES AND CHASSIS Temperature: 10'C to 38'C Operating: Non-Operating: - 35 'C to 65 'C Humidity: 20% to 80% (Wet bulb 26.7'C) Operating: Non-Operating: 5% to 95% CONTROLLER BOARDS Temperature: o to 55'C Operating: Non-Operating: -55'C to 85'C Humidity: Up to 95% relative humidity without Operating: condensation Non-Operating: AI/ conditions without condensation of water or frost 13·3 FLEXIBLE DISK SYSTEM EQUIPMENT SUPPLIED SINGLE DENSITY DOUBLE DENSITY Cabinet, Power Supplies, Line Cord, Two Drives Single Density FDC Channel Board Single Density FDC Interface Board Dual Auxiliary Board Connector Flexible Disk Controller Cable Flexible Disk Peripheral Cable Hardware Reference "Manual ReferenceSchematfcs ISIS-II Single Density System Disk ISIS-II System User's Guide Cabinet, Power Supplies, Line Cord, Two Drives Double Density FDC Channel Board Double Density FDC Interface Board Dual Auxiliary Board Connector Flexible Disk Controller Cable Flexible Disk Peripheral Cable Hardware Reference Manual Reference Schematics ISIS-II Double Density System Disk ISIS-II System User's Guide OPTIONAL EQUIPMENT MDS-BLD' MDS'730/731' 10 Blank Flexible Disks Second Drive Cabinet with two additional drives ORDERING INFORMATION Part Number MDS-71 0/11 OV' 711/220V M DS-720-11 OV' 721/220V MDS-730/110V' 731/220V Description Flexible Disk drive unit with drives, single density drive troller, software, and cables_ Flexible Disk drive unit with drives, double density drive troller, software, and cables_ two contwo con"- Add-on drive unit with two drives and double density cable, without controller and software_ Can be used with double density controller_ • MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation. MODEL 740 INTELLEC® HARD DISK SUBSYSTEM • 7.3 million bytes of on-line hard disk storage • Fixed and removable mass storage in one drive • 5440-type disk cartridge • Separate write protect switch for each disk platter • Enhanced development system performance • Intelligent 2-board controller The Intellec Model 740 Hard Disk Subsystem is a flexible, high capacity, mass storage peripheral for use with Intellec Microcomputer Development Systems. In addition to providing a large fixed and removeable storage component; the 740 can significantly improve throughput and reduce development time. 13·5 intJ MODEL 740 FUNCTIONAL DESCRIPTION cyclic redundancy check (CRC) polynomial and generates CRC data during write operations. When the disk controller requires access to Intellec system memory, the channel board requests and maintains DMA master control of the system bus, and generates the appropriate memory command. The channel board also acknowledges I/O commands as required by the Intellec bus. Hardware Components The Intellec Hard Disk Subsystem consists of an intelligent controller and disk drive with one removeable cartridge and one fixed platter. Each provides 3.6 million bytes of storage (7.3 M total) with a data transfer rate of 2.5 MBits/second. The disk controller is implemented with Intel's powerful Series 3000 Bipolar Microcomputer Set. The controller provides an interface to the Intellec system bus, as well as the disk drive. Data is, recorded in FM format on each surface (2 per platter). Each platter may be separately write protected via a front panel switch. The disk subsystem wil,l perform six specific operations: recalibrate, seek, format track, write data, read data, and verify CRC. Channel Board The Channel Board is the primary control module within the hard disk subsystem. The Channel Board receives, decodes and responds to channel commands from the Central Processor Unit (CPU) in the Intellec system. The Channel Board can access a block of Intellec system memory to determine the particular disk operations to be performed and fetch the parameters required for the successful completion oj the specified operation. Disk Controller Boards Th'e diskcontroll,er consists' of two boards, the channel board and the interface board. These two PC boards reside in the ,I ntellec Series II system chassis and constitute the disk controller. The channel board receives, decodes and responds to channel commands from the processor. The interface board provides the disk controller with a means of communication with the disk drive. The interface board validates data during reads using a The ,control functions of the Channel Board have been achieved with an 8-bit microprogrammed processor, designed with Intel's Series 3000 Bipolar Microcomputer Set. This 8-bit processor includes four 3002 Central Processing Elements (2-bit slice per CPE), a 3001 Microprogram Control Unit, and 1K x 32 bits of 3628 programmable-read-onlymemory (PROM) which stores the microprogram. It 13-6 MODEL 740 is the execution of the microprogram by the microcomputer set which actually effects the control capability of the Channel Board. verify successful operation. The I nterface Board accepts the data being read off the disk, interprets synchronizing bit patterns, checks the validity of the data using a cyclic redundancy check (CRC) polynomial, and then transfers the data to the Channel Board. When the disk controller requires access to Intellec system memory, the Channel Board requests the DMA master control of the system bus, and generates the appropriate memory command. The Channel Board also acknowledges I/O commands as required by the Intellec bus. During write operations, the Interface Board outputs the data and clock bits to the selected drive at the proper times, and generates the CRC characters which are then appended to the data. Interiace Board Associated Software The Interface Board provides the 740 disk controller with a means of communication with the disk drives, as well as with the Intellec system bus. Under control of the microprogram being executed on the Channel Board, the I nterface Board generates those signals which cause the read/write head on the selected drive to move to the proper track and Intel Systems Implementation Supervisor (ISIS-II) - The Hard Disk Subsystem is to be used in conjunction with the ISIS-II Operating System. ISIS-II provides total file management capabilities, file editing, library management, run-time support, and utility management. SPECIFiCATIONS Physical Characteristics Hardware Disk Drive on Pedestal Width - 18.5 in. (47.0 cm) Height - 34.0 in. (86.4 cm) Depth - 29.75 in. (75.6 em) Weight - 202 lb. (92 kg) Disk Drive Type - 5440 top loading cartridge and one fixed platter Tracks per Inch - 200 Mechanical Sectors per Track - 12 Recording Technique - double frequency (FM) Tracks per Surface - 400 Density - 2,200 bits/inch Bits per Track - 62,500 Recording Surfaces per Platter - 2 Electrical Characteristics Chassis DC Power Supplies - Internal to Cabinet AC Power Requirements 110 VAC; 60 Hz; 5A (max) 220 VAC: 50 Hz; 3A (max) Controiler Boards 5V @ 5.5A (typ). 6.5A (max) Disk System Capacity Per Per Per Per Environmental Characteristics Surface - 15M bits Platter - 29M bits Drive - 59M bits Drive - 7.3M bytes (formatted) Media, Drive and Chassis Temperature: Operating: 16°C to 32°C Non-operating: -10°C to 60°C Humidity: 20% to 80% non-condensing Controller Boards Temperature: Operating: DoC to 55°C Non-operating: -55°C to 85°C Humidity: Up to 90% non-condensing Disk Performance Disk Transfer Rate - 2.5M bits/sec Disk System Access Time Track to Track: 13 ms max. Full Stroke: 100 ms Rotational Speed: 2,400 rpm 13-7 MODEL 740 Equipment Supplied Optional Equipment Hard disk drive pedestal mounted H.ard disk controller (2 boards) Cables Disk Cartridge ISIS-II System Diskette 9800306 - Isis-II System User's Guide 9800943 - Hard Disk Subsystem Operation arid Checkout Manual MDS-746 Box of 5 blank cartridges specified for use on Model 240/241, 740/741 ORDERING INFORMATION Part Number Description MDS-740/110V 741/220V. Hard disk unit with cables, controller, ·and disk cartridge 13·8 MCS-80/85™ Development Systems and Options 14 FORTRAN 80 8080/8085 ANS FORTRAN 77 INTELLEC® RESIDENT COMPILER • Meets ANS FORTRAN 77 Subset Language Specification plus adds Intel' microprocessor extensions • Supports full symbolic debugging with ICE-80™ and ICE-85™ • Produces relocatable and linkable object code compatible with resident PL/M 80 and 8080/8085 Macro Assembler • Supports Intel" Floating Point Standard with the FORTRAN 80 software routines, the iSBC-310™High Speed Mathematics Board, or the iSBC-332™ math multimodule • Provides optional run-time library to execute in RMX-80™ environment • Executes on Intellec" Microcomputer Development System and Intellec" Series II MicrQcomputer Development System • Has well defined I/O interface for configuration with user-supplied drivers FORTRAN 80 is a computer industry-standard, high-level programming language and compiler thiJ.t ImnsliJ.tes FORTRAN statements into relocatable object modules. When the object modules are linked together and 10ciJ.ted into iJ.bsolute program modules, they are suitable for execution on Intel 8080/8085 Microprocessors, iSBC-80 OEM Computer Systems, and Intellec Microcomputer Development Systems. FORTRAN 80 meets the ANS FORTRAN 77 Language Subset Specification ~. In addition, extensions designed specifically for microprocessor applications are included. The compiler operates on the Intellec Microcomputer Development System under the ISIS-II Disk Operating Systems and produces efficient relocatable object modules that are compatible for linkage .with PLlM80 and 8080/8085 Macro Assembler modules. The ANS FORTRAN 77 language specification offers many powerful extensions to the FORTRAN language .that are especially well suited to Intel 8080/8085 Microprocessor software development. Because FORTRAN 80 conforms to the ANS FORTRAN 77 standard, the user is assured of compatibility with existing FORTRAN software that meets the standard as well as a guarantee of upward compatibility to other computer systems supporting an.ANS' FORTRAN 77 Compiler. 1ANSI X3J3/90 14·1 9800668-03 Rev. C FORTRAN 80 FORTRAN 80 LANGUAGE FEATURES Major ANS FORTRAN 77 features supported by the Intel@ FORTRAN 80 Programming Language include: o Structured Programming is supported with the IF ... THEN ... ELSE IF ... ELSE ... END IF constructs. o CHARACTER data type permits alphanumeric data to be handled as strings rather than characters stored in array elements. o Full 110 capabilities include: Sequential and Direct Access files Error handling facilities Formatted, Free·formatted, and Unformatted data representation Internal (in-memory) file units provide capa· bilityto format and reformat data in internal memory buffers List Directed Formatting o Supports arrays of up to seven dimensions. o Supports logical operators .EQV. - Logical equivalence .NEQV. - Logical nonequivalence o The INCLUDE control permits specified source files to be combined into a compilation unit at com· pile time. o Transparent interface for software and hardware floating point support, allowing either to be chosen at time of linking. FORTRAN 80 BENEFITS FORTRAN 80 provides a means of developing applica· tion software for Intel~ MCS·80185 products in a familiar, widely accepted, and computer industry· standardized programming language. FORTRAN 80 will greatly enhance the user's ability to provide cost· effective solutions to software development for Intel microprocessors as illustrated by the following: o Completely Complementary to EXisting Intel Software Design Tools - Object modules are linkable with new or existing Assembly Language and PUM Modules. o Incremental Runtime Library Support Runtime overhead is limited only to facilities required by the program. Major extensions to FORTRAN 77 in Intel FORTRAN·80 include: o o Direct 8080/8085 port 110 supported by intrinsic subroutines. Binary and Hexadecimal integer constants. Well defined interface to FORTRAN-80 110 statements (READ, OPEN, etc.), allowing easy use of , user-supplied 110 drivers. o User·defined INTEGER storage lengths of 1, 2 or 4 bytes. o User-defined LOGICAL storage lengths of 1, 2 or 4 bytes; o REAL STORAGE lengths of 4 bytes. o Low Learning Effort - FORTRAN 80, like PL/M, is easy to learn and use. Existing FORTRAN software can be ported to FORTRAN·80, and programs developed in FORTRAN 80 can be run on any other computer with ANS FORTRAN 77. o Earlier Project Completion - Critical projects are completed earlier than otherwise possible because FORTRAN 80 will substantially increase programmer productivity, and ,is complementary to PUM Modules by providing comprehensive arithmetic, 110 formatting; and data management' support in the'language. o Lower Development Cost - Increases in program· mer productivity translates into lower software development costs because less programming resources are required for a given function. Increased Reliability - The nature of high:level languages, including FORTAN 80, is that they lend themselves to simple statements of the program algorithm. This substantially reduces the risk of Costly errors in systems that have already reached production status. o 0, o Bitwise Boolean operations using logical operators on integer values. Hollerith data constants. o Implicit extension of the length of an integer or logical expression to the lerigth of the left·hand side in an assignment statement. o A format descriptor to suppress carriage return on a terminal output device at the end of the record. , o , o FORTRAN 80 COMPILER FEATURES o o o o o Supports multiple compilation units in single source file. Optional Assembly Language code listing. Comprehensive cross·reference, symbol attribute and error listing. Compiler controls ar:ld directives are compatible with other Intel language translators. Optional Reentrancy. o User-defined default storage lengths. o Optional FORTRAN 66 Do Loop semantics. o Source files may be prepared in free format. o 14-2 Easier Enhan2ementsand Maintenance - Like PUM, program modules written in FORTRAN 80 are easier to read and understand than assembly language. This means it, is easier to enhance and maintain FORTRAN 80 programs as system capabilities expand and future products are developed. Comprehensive, Yet Simple Project Development - The Intellec Microcomputer Development Sys· tern; with the 808018085 Macro Assembler, PUM 80 and FORTRAN 80 is the most comprehensive software design facility available for the Intel MCS·80185 Microprocessor family. This reduces development time and cost because expensive (and remote) timesharing or large computers are not required. AFN·00241B FORTRAN 80 SAMPLE FORTRAN·80 SOURCE PROGRAM LISTING *lI ** THIS PROGRAM IS AN EXAMPLE OF ISIS-II FORTRAN-BO THAT CONVERTS TEMPERATURE BETWEEN CELSIUS AND FARENHEIT PROGRAM CONVRT CHARACTER*l CHOICE, SCALE PRINT 100 ** ENTER CONVERSION SCALE (C OR F) PRINT 200 READ (5,300) SCALE * 10 IF (SCALE .EQ. 'C' ) THEN PRINT 400 *It ENTER THE NUMBER OF DEGREES FARENHEIT READ (5,*) DEGF DEGC = 5./9.*(DEGF-32) ** PRINT THE ANSWER WRITE (6,500) DEGF,DEGC ** RUN AGAIN? PRINT 600 READ (5,300) CHOICE IF (CHOICE .EQ. 'Y' ) THEN + GOTO 10 ELSE IF (CHOICE .EQ. 'N' ) THEN + CALL EXIT ELSE GO TO 20 END IF ELSE IF (SCALE .EQ. 'F') + THEN ** CONVERT FROM FARENHEIT TO CELSIUS PRINT 700 READ (5,*) DEGC DEGF = 9./5.*DEGC+32. ** PRINT THE ANSWER WRITE (6,BOO) DEGC,DEGF GO TO 20 ELSE lIli NOT A VALID ENTRY FOR THE SCALE WRITE (6,900) SCALE GOTO 10 END IF FORMAT(' TEMPERATURE CONVERSION PROGRAM' ,II, +' TYPE C FOR FARENHEIT TO CELSIUS OR' ,I, +' TYPE F FOR CELSIUS TO FARENHEIT' ,II) FORMAT(/,' CONVERSION? ',$) FORMAT(A 1) FORMAT(/,'ENTER DEGREES FARENHEIT: ',$) FORMAT(/,F7.2,' DEGREES FARENHEIT = ',F7.2,' DEGREES CELSIUS') FORMAT(/,' AGAIN (Y OR N)? ',$) FORMAT(/,' ENTER DEGREES CELSIUS: ',$) FORMAT(/,F7.2,' DEGREES CELSIUS = ',F7.2,' DEGREES FARENHEIT' ,I) FORMAT(/,lH ,Al,' NOT A VALID CHOICE - TRY AGAIN I ',I) END + * * * 20 * * * 100 200 300 400 500 600 700 BOO 900 14·3 AFN-002418 FORTRAN 80 The FORTRAN 80 Compiler is an efficient, multiphase compiler that accepts source programs, translates them into relocatable object code, and produces requested listings. After compilation, the object program may be linked to other modules, located to a specific area of memory, then executed. The diagram shown below illustrates a program development cycle where the program consists of modules created by FORTRAN 80, PLfM 80 and the 8080/8085 Macro Assembler. 1515·11 TEXT EDITOR FORTRAN 80 SOURCE 1515·11 TEXT EDITOR r-- 1515·11 LOADER r-- DEBUG VIA MONITOR RELOCATABLE OBJECT MODULE PLfM 80 SOURCE 1515·11 TEXT EDITOR OPTIONAL Ice·aolM ICE-85™ IN·CIRCUIT EMULATOR ASSEMBLY LANGUAGE SOURCE - PROM PROGRAMMER Required Software: ISIS-II Diskette Operating System - Single or Double Density SPECI FICATIONS OPERATING ENVIRONMENT Optional Software: iSBC-801 FORTRAN-80 Run-Time Software Package for RMX-80 Required Hardware: Intellec® Microcomputer Development System - MDS-800, MDS-888 - Series II Model 220, Model 230 DOCUMENTATION PACKAGE 64K bytes of RAM memory FORTRAN-80 Programming Manual (9800481) Dual diskette drives - Single or Double Density ISIS-lI FORTRAN-80 Compiler Operator's Manual (9800480) System console - CRT or hardcopy interactive device FORTRAN-80 Programming Reference Card (9800547) SHIPPING MEDIA Optional Hardware: Line Printer ICE-80™,ICE-85TM Flexible Diskettes - Single and Double Density ORDERING INFORMATION PART NO. DESCRIPTION *MDS-301 FORTRAN 80 Compiler for IntellecMicrocomputer Development Systems ·"MDS" is an ordering code only, and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corp. 14-4 BASIC-80 EXTENDED ANS 1978 BASIC INTELLEC® RESIDENT INTERPRETER • Supports the Intel® Floating Point Standard and Provides Integer and String Data Types • Meets ANS 1970 Standard for Minimal BASIC and Adds Many Powerful Extensions • Operates Under the ISIS-II Operating System on Intellec® and Intellec® Series~1I Microcomputer Development Systems • Can Call User Subroutines Written in FORTRAN 00, PL/M 00, and 0000/05 Macro Assembler that are Resident in the Intellec® Memory • Full Sequential and Random Disk File I/O with ISIS-II • Applications Range from Prototyping Microcomputer Software to Inexpensive Engineering and Management Problem Solving on the Intellec® Systems • Easily Learned Language and Interactive Environment Combine to Provide a Flexible and Powerful Facility for Developing Programs to Run on the Intellec® Microcomputer Development Systems BASIC is an industry standard, high·level programming language which is designed to be easily learned and used by novices and experienced programmers alike. The interpreter provides an interactive environment which allows fast and easy program development, testing, and debugging. BASIC is widely used for problem solving in engineering and management; extensive software exists for business applications such as order entry, accounts receivable, accounts payable, and inventory control, and engineering applications such as numeric and statistical analysis. Intel's BASIC·80 meets the standards of ANS 1978 BASIC and extends them to take advantage of the software devel· opment capabilities of the Intellec Microcomputer Development Systems. The matching of these resources with the ease of programming in BASIC·80 provides a very effective tool for both microprocessor systems development and inexpensive applications programming and problem solving on the Intellec systems. 14·5 AFN·Ol186A BASIC·SO BASIC·SO LANGUAGE FEATURES • Formatted print statement with the PRINT USING function. Standard ANS 78 BASIC features, all supported by BASIC-80, include: • ELSE clause for IF ... THEN statements. • Matrices with upto 110 dimensions. • String and numeric constants, variables, and arrays. • Extensive string manipulation functions. • FOR ... TO ... STEP ... NEXT statements for loOp execution. • Boolean operators. • Type conversion and 'character. . • IF, .. THEN statements for conditional execution. functions~lnteger,. floating point, ' • ON ... GOTO statements for computed branching. • GOSUBIRETURN subroutine calls and returns. • Built in scientific functions: ABS EXP INT LOG RND SGN SOR ATN BENEFITS OF BASIC-SO· TAN COS SIN • Added Value to'the,iritellec Systems'C""with.BASIC·80 the Intellec Microcomputer Development Systems can be effectively used in many engineering and management applications. , • User defined single statement functions. • Inexpensive and Accessible Computational Facilitythe ease of use and flexibility inherent in BASIC·80 and its interpretive envirbnment fit well with the "at hand" computational resources of the Intellec sys· tems. The combination is a pa(ticularlyuseful tool for obtaining fast and accurate results. Major extensions toANS78 BASIC which BASIC·80 pro· vides include: • Support for the Intel single and .. double precision . floating point standard. • Disk file ·I/O,supporting both random sequential access files. acces~ and • Easy to Learn-the language is designed to be easily understood and learned. Results are obtained faster and people who may benefit from using the system can do so easily. • Direct read and write to CPU 110 ports through the INP and OUT functions. • Direct memory read and write throlJgh the PEEK and· POKE functions. . • Aid in Microcomputer Software'Design-microcomputer software can be prototypedin BASIC·80 to inexpensively develop and test program logic. • Calls to user-supplied external subroutines, which may have been written in FORTRAN'80, PUM-80, or 8080/8085 Assembly Language and have been located at absolute memory locations using the ISIS·II facilities. • Complemented by ExistingSoffware-subroutines written in PUM·80, FORTRAN·80, and ASM 8080/85 can be called from BASIC·80programs. • Program execution trace command. • Easy to Enhance. and Maintain-BASIC,80, being straightforward and easily understood, provides for programs that are easy to maintain and modify in the future. SPECIFICATIONS Optional Hardware: • User directed error trapping and handling functions. Line printer Additional diskette drive Operating Environment Required Software: ISIS-II Diskette Operating System - Single or double density Required Hardware: Intellec Microcomputer Development System - Models 800 and 888 - Series·1I Model 220, Model 230 Documentation Package: Basic-80 Reference Manual (9800758A) Basic-80 Programming Reference Card (9800774) 48K bytes of RAM memory Diskette drive - Single or double density Shipping Media: System console - CRT or hard copy interactive device Flexible diskettes - Single and double dElr;sity 14·6 AFN·011a6A BASIC·80 EXAMPLE BASIC·80 PROGRAM list 10 PRINT "THIS PROGRAI'I CALCULATES THE MEAN AND STAl'llDARD" 20 PRINT " DEVIATION OF INPUT DATA" 30 S=0:V=0 40 INPUT "NUMBER OF VALUES"~N 50 FOR 1=1 TO N ()0 INPUT A(I) 70 S=S+A(I) 130 NEXT 90 S=S/N 100 REM CALCULATION OF VARIANCE 110 FOR 1=1 TO N 120 V=V+(A(I)-S)"2/N 130 NEXT 140 SD=SQR(V) 150 PRINT "MEAN="~S 160 PRINT "STANDARD DEVIATION IS="~SD Ok run THIS PROGRAM CALCULATES THE MEAN AND DEVIATION OF INPUT DATA NUMBER OF VALUES? 6 ? 34.7 ? 32.9 ? 38.2 ? 35 ? 37.6 ? 40.9 MEAN= 36,55 STANDARD DEVIATION IS= 2.642442 Ok STANDA~D ORDERING INFORMATION Product Code Description MDS-320' 1515:11 BASIC-80 Disk-Based Interpreter • MDS is an ordering code only and is not used as a product name or trademark. MDS" il a regiltered trademark of Mohawk Data Science Corporation. 14-7 AFN-IIl186A intel~ 8080/8085 FUNDAMENTAL SUPPORT PACKAGE (FSP) • Comprehensive Extension of the 8080 CPU Performance Features Through Standardized Software Building Blocks • library Routines Provide Extended Math Capabilities of ASM 80, PL/M 80, and FORTRAN 80 • Hardware-Independent Modules Selectable by the User for a Wide Variety of Frequently Needed Program Functions • Available on Diskette as an ISIS-II Library.File • Efficient Integration with the User's Program Using the ISIS Utility Programs LINK and LOCATE • High Standard of Reliability Achieved Through Use of Proven Algorithms and Meticulous Testing of All Functions • Lowers Software Development Costs FSP is a mathematical and technical applications library. It is a comprehensive collection of frequently needed program functions that complement and augment the capabilities of the 8080/8085 microprocessor. The inciusion of these functions eliminates the need to code and debug complicated math routines and P!lrmits the user to concentrate on his own application. The use of FSPfunctions thus. makes a noteworthy contribution to the economy of software development. FSP consists of a collection of subroutines stored as relocatable modules on a diskette. These modules can, with the help of ISIS utilities, LINK and LOCATE, be linked to user programs in assembly language, PL/M or FORTRAN. 14-8 121526-001 8080/8085 FUNDAMENTAL SUPPORT PACKAGE (FSP) PACKAGE FEATURES DESCRIPTION OF THE LIBRARIES The Fundamental Support Package consists of nine individual libraries that lie in a hierarchical structure. as shown in figure 1. These nine sections are: FSP Machine (FSLMCH.LlB) The routines in this library, together with the 8080/8085 hardware, constitute the FSP Machine. The routines fall into two categories: the first comprises a group of pselldo-operations that complement and augment the 8080/8085 instruction set. These pseudo-operations are accessible only from assembly language programs'and resemble assembler commands. Tile second category consists of a set of routines that work on variable-length operands; the integer and decimal arithmetic and string-handling capabilities of the FSP are based on this foundatiol'. • The FSP Machine (primitive subroutine) package performs fast string handling and binary and decimal integer arithmetic without error reporting. • The binary integer arithmetic routines provide operations on signed and unsigned integers of various formats in binary representation. • The floating-point arithmetic section provides operations on iloating-point (real) numbers in four formats: single precision, single-precision extended, double precision, and double-precision extended. The routines in the FSP Machine do not return messages in the event of an erro'r; they are optimized for speed of execution. • The decimal arithmetic routines provide integer and fixed-point arithmetic on numbers in decimal representation-i.e., stored as strings of ASCII characters. String Handling (FSLSTR.LlB) This library contains routines for manipulating strings and for the processing of character input and output. The string manipulation routines fall into two groups. The first is, character-oriented, while the second handles groups of string variables. 'In both groups, there are functions necessary for retrieval and manipulation of data. • The string handling section contains routines to transform strings and to extract and insert substrings. A routine for scanning of general input and one for formatting of general output are included. • The routines for number conversion and numeric I/O do transformation of numeric data from one internal format to another, input scanning of numeric strings and formatting of numeric strings for output. The input scanner recognizes simple symbols like alphabetic names, numbers, boundaries, and gaps in input strings. The routines work with one of the userdefined tables and returns as a result an operand that can bp, utilized by the other string manipulation routines. • The floating-point transcendental function section provides trigonometric, exponential, and other transcendental functions for single precision, singleprecision extended, double precision, and doubleprecision extended floating-point arguments. • The statistics routines compute the mean, variance, and standard deviation of one group of statistical data, and the covariance and correlation factor of two groups of data. ' • The P. I. D. process control routines direct the production of an appropriate output signal in response to an input signal, using a formula with proportional, integral, and lor derivative terms, for realtime process control applications. In linking modules to an application program, the user must note the hierarchical structure of FSP and specify in order the lower level packages on which a higher level package must rely. Figure 1 shows the required subordination of subroutines; for example, the statistical package relies on the floating-point library, which in turn relies on the FSP machine. FSLMCH All FSP routines are reentrant; that is, all local data used by each routine is stored on the stack, These routines may thus be interrupted, and during the interrupt the same routine or other ;ou!;r.es mily be callp.d, ,,,,ithout affecting the results of the interrupted routine. 14-9 FSPMACHINE Figure 1. Hierarchy of FSP Modules 8080/8085 FUNDAMENTAL SUPPORT PACKAGE (FSP) The output formatter arranges data into a form required for further manipulation. For example, it permits: Floating-Point (FSLFLP.LlB) The routines in this library provide an extensive range of floating-point arithmetic functions. In addition to addition, subtraction, multiplication, and division, there is a module function, a square root function and a routine to compare two floating' point operands. Floating-point operands can be represented in any of four formats: • Copying a character from the input string into the output buffer • Including a literal in a given position in the output string • Collapsing leading blanks FORMAT • Inserting the sign (i.e., of a number) in a given position in the output string Single Precision Exlended Single Precision Double Precision Extended Double Precision STORAGE MANilSSA EXPONENT 4 Byle 6 Byle 24 bits 32 bits 53 bits 64 bits 15 bits 11 bits 15 bits BByte 10 Byte Bbits Additional functions provide for truncation, rounding and conversion of floating-point operands from one of the above formats to another. Decimal Arithmetic (FSLDEC.LlB) The routines available in this library operate directly on signed decimal numbers without converting them internally into binary. Only integer operands are permitted. These are represented as ASCII strings up to 32 characters long. Addition, subtraction, and multiplication are accomplished by means of one operation each. For division there are two functions; one to calculate the integer quotient, one to calculate a remainder. Additional functions allow for negation, absolute value, and comparison of operands. Also available are utilities to limit the length of operands and to scale decimal variables. Conversion and 1/0 (FSLCNV.LlB) This library consists of routines for input and output of floating-point numbers and for the conversion of numeric data between different internal formats. There is an input scanner to read numeric data; there is an output formatter that writes output data to a buffer. There are various possible formats for input and output data; numeric data are handled as ASCII strings, as follows: • Integers (single, decimal mantissa) • Scaled integers (sign, decimal mantissa, decimal pOint) • Floating pOint numbers (sign, decimal mantissa, decimal pOint, decimal exponent) There are also other routines necessary for conversion of binary, decimal and floating point numbers. By means of the transformation of decimal into floatingpoint numbers and vice-versa, single and double precision are achieved. Integer Arithmetic (FSLlNT.LlB) In this library there are routines for unsigned (8- and 16bit) and signed (8-, 16-, and 32-bit) decimal arithmetic. For each of the fundamental operations-addition, subtraction, multiplication and division, as well as for the comparison of two integer operands-there is one routine. Additional functions provide for manipulation of the signs of operands and conversion of operands between different internal storage formats. Statistics (FSLSTA.LlB) This library makes available routines that provide elementary statistical functions. The calculation of means, variance, and standard deviation employs onedimensional arrays of data, whereas the calculation of covariance and correlations presumes two-dimensional arrays. In both cases, data are supplied as single precision floating-point numbers; the statistical routines make use of the floating-point library. Results of calculations are returned as single precision floating point numbers. For signed integer operands, the following formats are possible: FORMAT RANGE 1 byte, Including sign 2 bytes, including sign 4 bytes, including sign 8 bytes, including sign -2 7 to 27_1 -2 15 10215_1 _2 31 10231 _1 -263 10 26L l Process Control (FSLPID.LlB) For unsigned operands, there are three possible formats: . 1 byte, without sign 2bytes, without sign 4 bytes, without sign The routines in this library support digital process control using the 8080/8085. The PID algorithm 0102 6-1 0101 1Ll 0102 32-1 The 8-byte signed format and the 4-byte unsigned format are limited to retrieval of results. 1 4·10 M(t) = B + ~oo (E(t) + ~SE(S) ds + D ~;) to 8080/8085 FUNDAMENTAL SUPPORT PACKAGE (FSP) calculates an output signa! M(t) as a function of an input signal E(t). The input quantity is a measure of the deviation of a controlled variable from a set point. The parameters B, P, R, and D are supplied by the user. The implementation is such that the user can select to exclude or include any combination of the terms in the PID equation (i.e., the proportional term, the integral term~ the derivative term). ,There are also routines to initialize the control function and to change the measurement interval. Transcendental Functions (FSL TRN.LlB) This library includes routines to calculate elementary mathematical functions in single, extended single, pouble, and extended double precision. The following functions are available: • sin, cos, tan • exp, In, 10gw Yx • sinh, cosh, tanh • arc sin, arc cos, arc tan, arctan (yjx) Required Software: SPECIFICATIONS ISIS-II Diskette Operating System DEVELOPMENT ENVIRONMENT LINK, LOC Utilities Required Hardware: ASM80, FORTRAN-80, PLlM-80 Intellec Microcomputer Development System -Model 800 -Series,1I Model 220, 230, or '240 DOCUMENTATION PACKAGE 8080/8085 Fundamental Support Package (FSP) Reference and Operating Instructions for ISIS-II Users Order Number 9800887 64KB of Memory -Single or double density diskette drive Shipping Media System Console -Intel or Non-Intel CRT Flexible Diskettes -Single and double density ORDERING INFORMATION: Product Code MDS-318' Description 8080/8085 Fundamental Support Package (FSP) "'MDS" is an ordering code only, and is not used as a product name or trademark. MDS'" is a registered trademark of Mohawk Data Sciences Corp. 14·11 iCIS-COBOL SOFTWARE PACKAGE • Meets and Exceeds Minimum ANSI Level 1 Standard for COBOL (X3.23-1974) • Can Link/Call Routines Written in PLlM80, FORTRAN 80 and 8080/8085 Assembly Language • Runs Under ISIS-II on Intellec® or Intellec® Series II Microcomputer Development Systems • FORMS Utility Program Allows the User ~o Design and Test CRT Screen Format Input by Generating COBOL. Source Code for the Data Descriptions Defining that CRT Screen Format • Compiler Compiles COBOL Source Programs into an Intermediate Code Which is Optimized for Speed and Memory Space • Compile-Time Option Available to Flag Any Non-ANSI Standard Features for Portability • Includes Execution Run~Time Interpreter and an Interactive Debugger • Powerful Extensions for Interactive Programming • Tested Using U.S. Dept. of Navy COBOL Validation System iCIS-COBOL, an acronym for Intel's Compact Interactive Standard COBOL, is a package designed to provide a powerful interactive business language to users of Intel's Intellec and Intellec Series II Microcomputer Development Systems_ iCIS-COBOL contains the most relevant parts of the ANSI 74 standard plus extra extensions to make this product especially useful to Intellec users_ The compiler provides a feature to optionally disallow the iCIS-COBOL extensions and rigidly enforce the ANSI 74 specification_ This will prove beneficial to users who may need to port COBOL programs from the Intellec system to any other ANS Level 1 COBOL compiler. iCIS-COBOL Compiler generates object code for a COBOL "virtual rnachine_" This code is designed for optimum representation of COBOL verbs and data types_ The code generated is interpreted by. a Run-Time System_ This consists of an interpreter which emulates the COBOL virtual machine and interfaces to the ISIS-II operating system and the CRT_ After an application program has been tested and is ready for production use, it is possible to link it permanently to the Run-Time System to form a free-standing ISIS-II load able program_ 14·12 iCIS·COBOL When data is being keyed in, the operator has full cursor manipulation facilities, each variable acting as a tab stop. Non·numeric digits may not be keyed into fields defined as PIC 9. Finally, when the operator has checked that the data is correct, the RETURN key is pressed and processing continues. LANGUAGE FEATURES COBOL consists of twelve different modules imple· mented either to Level 1 or Level 2 as defined in the ANSI specification X3.23. iCIS·COBOL includes the following modules implemented to Level 1: Nucleus Table Handling Sequential 1/0 Relative 1/0 IndexEJd 1/0 Library Interprogram Communication SCREEN LAYOUT AND FORMAT FACILITIES CURSOR CONTROL FACILITIES Screen as a record HOME 10 the slarl of Ihe firsl dala field on Ihe screen descripllon FILLER Extensions to ANSI Specification: REDEFINES • Advanced screen formatting and data entry facilities. These include protected and unprotected data, cursor manipulation, and numeric vet. Ch a rac I er hi 9 h I i 9 h lin 9 Clear screen • Run time input of filenames. The actual value of the external filename may be moved to a file identi· fier location prior to OPENing the file, avoiding the need for an external linking mechanism. Numeric vel lor PIC fields Backward space I Forward field Backward field CIR Release Ihe screen of dala LlF Left Fill numeric field (The actual keys used vary according to CRT keyboard) • Line sequential files. Variable length records sep· arated by carriage returnlline feed saves space on disk and allows iCIS·COBOL programs to process files output by a text editor. FORMS UTILITY A majority (up to 80%) of debugging timecan be spent in designing, coding and testing the screen form inputloutput of a COBOL program. The FORMS utility included in the iCIS·COBOL package significantly reduces this debugging time. • Hexadecimal literals. These may be used to defin," control characters to output to special peripheral devices. • Rapid development facilities. During development, compiled programs may be loaded directly by the Run·Time System "fast load" facility, thus avoiding the time otherwise spent in linking. Using the FORMS program, the user may: • Interactive debugging. Interactive debugging per· mits the setting of breakpoints, examination and modification of store, etc., at run time. Each COBOL statement is identified by a four·digit hexadecimal number. o line:column .~T Forward space - o Store an image copy on disk of the form he has de· fined for subsequent use. o Generate iCIS·COBOL source code for the data descriptions required to define the form just created. This may then be included in an iCIS· COBOL program using COPY. o Choose to generate a checkout program which allows duplication of the many machine conversa· tions which would take place during a run of the application which is being designed. Lower case. This is permitted in COBOL words and comments, thus helping to produce easy to read documentation in the program. INTERACTIVE CRT HANDLING Intel has taken COBOL traditionally a batch processing language - ,md extended it to become interactive. iCIS·COBOL offers many facilities for automatically formatting a CRT screen and facilitating input keying. COMPILE TIME DIRECTIVES o ANS If specified. the Compiler will accept only those iCIS·COBOL language statements that conform to the ANS 74 standard. The user can format the screen of any system console (CRT) into protected and unprotected fields by using standard COBOL statements. The screen layout may be defined in the DATA DIVISION. An ACCEPT statement nominates a record description which permits input to the character positions corresponding to variables identified by data·names. These may be separated by FILLERs to position them on the screen. ConverselY, a DISPLAY outputs only from non·FILLER fields in the record description which it nominates. The programmer can easily build up complex conversations for data entry and transaction processing. o RESEQ If specified, the Compiler generates COBOL sequence numbers, renumbering each line in incre· ments of 10. o NOINT No intermediate code file is output. The Compiler is, in effect, used for syntax checking only. o NOLIST No list file is produced; used for fast compilation of "clean" programs. 14-13 iCIS·COBOL - Most COBOL programs are self·documenting. - Conversational verbs and phrases and common business terminology make COBOL easy to learn, use and maintain. - More business and application programs are written in COBOL than any other language. • COPYLIST The contents of the file(s) nominated in COPY statements are listed. • NOFORM No form feed or page headings are to be output by the Compiler in the list file. • Meets and exceeds ANS Level 1 COBOL standard. - Assures portability to and from all computers supporting ANS Level 1 COBOL. - Extensive testing and validation using U.S. NAVY COBOL VALIDATION SYSTEM assures functionality for all Level 1 features. • ERRLlST The listing is limited to those COBOL lines contain· ing syntax errors together with the associated error. message(s). • INT (external·file·name) Specifies the file to which the intermediate code is to be directed. • iCIS·COBOL software package provides an easy to use, efficient and friendly environment for COBOL program development. - CONFIGURATOR program allows the user to reconfigure the software for any non'standard, non·lntel CRT. - Interactive debugger provides features aimed at a CRT based system (rather than batch· oriented). - FORMS utility program reduces total program development time by 30%. - All iCIS·COBOL utilities make use of CRT cursor control. • LIST (external-file·name) Specifies the file to which the listing is to be directed. • FORM (integer) Specifies the number of COBOL lines per page of listing. • NOECHO Error lines are echoed on the console unless this directive is specified. BENEFITS • Adds value to an Intellec development system. - COBOL applications programs developed using iCIS·COBOL software package will increase utilization of Intellec development systems. • Brings COBOL to Intellec Microcomputer Develop· ment Systems. - COBOL is the industry standard high·level language for business·oriented applications. ~~~~~~ !~~~n~~~t~l~~og:~:t~~:~"_H. ~~~; ~~~~~~ ~~~:~~~~~~;~~t~~C'j'lOft. 0001 O"UO'l~ Ii~JtCI_~Ii .. f"H~. OQOO~O 11'~V'j'-O"u~t ~iC'lION. OOM' ~~~~!~ :~~~~~~IJ:~~~~l~~g~N. The source program Is created on diskllle wllh the ISIS·II editor. O"~O'O rlL&_~O~UO~. ol:.Lt:Ci n"n. r lL~ ASSI~~ OJI~AI,IUno~ 1I<~oH~ ACC"~S HI O THEN DO; NUMCH = NUMCH + 1; DIGITS(NUMCH) = C; C= DIGITS(NUMCH)/10; DIGITS(NUMCH)= DIGITS(NUMCH) - 10*C; END END; 24 2 7 9 END FACTORIAL; 25 END; Table 1. PL/M·80 Compiler Sample Factorial Generator Procedure SPECIFICATIONS Operating Environment Required Hardware Intellec microcomputer development system 65K bytes of memory Dual diskette drives System console - teletype Optional Hardware CRT as system console Line printer Required Software - ISIS-II diskette operating system ORDERING INFORMATION Shipping Media Diskette Reference Manuals 980026 - PUM 80 Programming Manual (SUPPLIED) 9800300 - ISIS·II PUM 80 Compiler Operator's Manual (SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Requires software license Product Code Description MDS-PLM* PLiM 80 High level language compiler *MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation. 14.18 PASCAL 80 SOFTWARE PACKAGE • Offers a Superset of· Standard Pascal • Can Call Routines Written in PLIM 80, FORTRAN 80, or 8080/8085 Macro Assembler • Provides Highly Structured Language with Powerful Data Type Definitions to Suit Applications • Includes Data Types and Procedures Consistent with RMX-80™ Environment for Optional RMX-80 Run-Time Interpreter (iSBC 803™) • Compiles Pascal Source Code into Intermediate Code to Optimize Execution Speed and Storage • Executes Compiler and Interprets the Intermediate Code on Intellec® Microcomputer Development Systems ill • Allows Modular Breakdown of Large Programs and Separate Compilation of Individual Modules Provides a Utility to Produce Relocatable Object Modules Compatible with Other Intel® Languages • Gives Application Control Over Run-Time Errors by Providing User-Declared Error Procedures PASCAL 80 Software Package consists of a compiler and an interactive Run-Time System designed to provide the Pascal programming language as.a software development tool for Intellec Development System Users. Pascal is a highly-structured, block-oriented programming language that is now gaining wide acceptance as a powerful software development tool. Its rigid structure encourages and enforces good programming techniques, which, combined with a high level of readability, helps produce more reliable software. Standard Intel development \0015, such as CREDIT editor can be .used to create and modify Pascal source programs. The compiler compiles this source and creates a P-Code file. The Run-Time System executes this P-Code in an interpretive manner under ISIS-II or optionally under RMX-80. 'Pascal language as defined in PASCAL User Manual and Report, Second Edition, Kathleen Jenson and Niklaus Wirth. 14·19 121515-002 Rev. B PASCAL 80 LANGUAGE FEATURES Data Structures Pascal allows the user to define labels, constants, data types, variables, procedures, and functions. Variable Types Variables can be defined according to the following system-defined data types: boolean, integer, real, character, array, record, string, set, file, and pointer. PROGRAM TRACING FACILITY The PASCAL 80 System incorporates a program tracing facility which allows for selectively monitoring the execution of a Pascal program. When the TRACE flag is set, the line number of each program statement being executed is output to the console. The TRACE flag may be manipulated in two ways: -The TRACEON command (of the Run-Time System) will set the flag, and the TRACEOFF command will reset the flag. User-Defined Types -Pressing the Interrupt4 switch on the Intellec System front panel will toggle the TRACE flag; i.e., the flag will be set if it was reset, and vice-versa. New types can be defined by the user for added flexibility. COMPILER DIRECTIVES (PARTIAL LIST) File Handling Pr()cedures Compiler Command Line Directives Pascal provides procedures to allow a user's program to interface with the ISIS-II file manager. Routines provided are: RESET, 8EWRITE, CLOSE, PUT, GET, SEEK, and PAGE. NOLIST No list file is produced; used for fast compilation of "clean" programs. Input/Output Procedures NOCODE No code file is produced; used for syntax error checking. Routines are provided to interact with the console or an ISIS file. These procedures are: READ, WRITE, READLN, WRITELN, plus BUFFER and BLOCK Read and Write. ERRLlST List file is limited to only those Pascal lines that contain errors, along with the error messages produced. Dynamic Memory Allocation LIST (file-name) Specifies the name of the list file. The procedures NEW, MARK, and RELEASE allow the user to obtai n and release memory space at ru ntime for dynamically allocating variable storage. CODE (file-name) Specifies the name of the code file. String Handling NOECHO Error lines are echoed on the console unless this directiveis specified. Pascal provides powerful toolS. for defining and manipulating strings and character arrays. These facilities enable concatenation of strings, character and pattern scans, insertion, deletion, and pointer manipulation. . Embedded Compiler Directives $C text Causes text to. appear in code file (allows for comments, copyrights, etc.). Recursion $1+ Pascal allows a PROCEDURE definition to include a call to 'itself, a powerful construct in many mathematical algorithms. Causes checking for I/O completion after each I/O transfer. Failure results in a run-time error. ($1causes no checking, and no errors on I/O failure.) 14-20 AFN·01233B PASCAL 80 -Pascal is being acclaimed as the programming language of the future; it is being taught in many colleges and universities around the country. $R+ Causes Range Checking to occur, so that an out-ofrange value causes a Run-Time error. ($R- suppresses generation of code for Range Checking.) -PASCAL 80 Run-Time System provides great ease in programming formatted I/O operations. $0+ Causes the compiler to operate in overlay mode. Overlays allow less source code to reside in memory. ($0- causes no overlays, which decreases compile time, since there are fewer disk accesses.) PASCAL 80 provides a portable language for application programs running under ISIS-II. PASCAL 80 can be used to evaluate complicated algorithms using a natural language. $T+ PASCAL 80 compiler generates intermediate Pseudo-code. Causes the compiler to generate tracing instructions to be used by the TRACE facility. ($Tsuppresses tracing instructions.) -P-code is optimized for speed and storage space. -P-code is approximately 50% to 70% smaller than corresponding machine code. BENEFITS -P-code is machine independent, providing code portability to any CPU. Brings Pascal to Intellec Microcomputer DeV€lopment Systems: -Pascal is a block-structured, highly-readable programming language, suitable for a wide-range of applications. Makes the Intellec Development System a more valuable tool. Extension of software support to include Pascal makes software development and resource management more flexible. The source program is created on diskette with the ISIS-II text editor. -PASCAL ... Loads the Run-Time System which executes compiled PASCAL programs. COMP PROG .. ... Loads the compiler to convert the source program into an interpreted object form known as intermediate code, or P-code. ·PROG ... ... Loads the Run-Time System which executes compiled Pascal programs. Figure 1. Program Development Cycle 14-21 AFN-01233B PASCAL 80 Table 1. Sample Program Listing Showing Nesting Levels BUFFER.PAS Program Listing Line Seg 1 2 3 4 5 6 7 8 .. 1 9 10 11 12 13 . 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Proc Lev Disp program example; { Example using bufferread and builerwrite with break characters 44 64 65 67 108 f 1 1 1 .1 1 ? 2 2 2 , 0 27 68 87 109 109 116 132 179 197 208 208 226 262 292 331 378 378 388 I var buffer: string; disk storage: Iile; break: char; new len, len: integer; buff array: packed array[0 .. 80) 01 char; begin rewrite (disk. storage, 'data'); writeln('lnput a line 01 text: '); readln (buffer); len := bufferwrite(disk . storage, buffer[1], length(buffer)); repeat" . reset(disk_ storage);' writeln; writeln; write('lnput break char [cntrlZ to stop): '); readln(break); il not eol(input) then begin new_len:= bufferread(disk_storage, bulL_array, len, ord(break)); writeln('The buffer read: '); writeln(copy(buffer, 1, abs(new_len))); writeln('Length: ',abs(new_len):O); if ~.ew.._len< 0 then writeln('(Break char not found)'); end; untileof(input); end. SPECI FICATIONS OPTIONAL SOFTWARE ISIS-II CREDlpM (CRT-Based Text Editor) Operating Environment REQUIRED HARDWARE Intellec® Microcomputer Development System -Model 800 -Series II Model 220, Model 230, Model 240 64KB of Memory Dual-Diskette Drives -Single- or Double-Density' System Console -Intel® CRT or non-Intel® CRT "Recommended. Documentation Package PASCAL 80 User's Guide (9801015-01) PASCAL User Manual and Report, Second Edition, Kathleen Jensen and Niklaus Wirth Shipping Media Flexible Diskettes -Single- and Double-Density REQUIRED SOFTWARE ISIS-II Diskette Operating System -Single-or Double-Density 14·22 AFN.()1233B intel' PASCAL 80 ORDERING INFORMATION Part Number Description MDS-381* PASCAL 80 Software Package Requires Software License 'MDS is an ordering code only and is not used as a product name or trademark. MDS'" is a registered trademark of Mohawk Data Sciences Corporation. Intel Corporation has carefully reviewed this product and believes that the product will operate and perform according to its published user manuals. HOWEVER, INTEL MAKES NO WARRANTIES WITH RESPECT TO THE OPERATION AND USE OF THIS VENDOR SUPPLIED PRODUCT. Successful use depends solely on customer's ability to install and use this product. This Vendor Supplied Product is licensed on an "as is" basis and Intel Corporation does not guarantee any future enhancements or extensions to this product. The existence of this product does not imply its adaptation in any form as an Intel standard nor its compatibility with any other Intel product except as specifically stated in the published user manuals. Inlel will provide limited telephone assistance to the customer in the underst'anding of the operation of the product. In addition, if a problem is encountered which the user diagnosis indicates Is caused by a defect in this VendorSupplied Product, the user is requested to fill outa Problem Report form and mail it to: Intel Corporation MCSO, Marketing 3065 Bowers Avenue Santa Clara, CA 95051 Intel will use its best efforts to respond to Problem Reports in one of the following ways: 1) release information to correct the problem, 2) offer a new reVision, when available with corrected code to fix the problem, or 3) Issue a notice of availability of a new revision with corrE:lcted code. 14-23 AFN-01233B SP80 SUPPORT PACKAGE' • Programs Writtenin'PUM, FORTRAN, and Assembly Language can be Linked Together and Relocated • Development Support for 8080 Microprocessor Designs, Including: • PL/M 80 Structured High-Level Programming Language Compiler for System Software Development • ICE-80™Emulation Connects hltellec® System Resources to a User's Prototype • ANS 77 FORTRAN 80 Compiler for Mathematically Oriented Software .Development. • ICE-80™ In-Circuit Emulator . .;, ,'. '". " .• Full Symbolic Debugging is Available for Program Labels or Variables . .: 8080 softw~re development begins using the 8080 macroassembler, PL/M 80, FORTRAN 80 high71evel languages and compilers. The compilers operate on Intellec microcomputer development systems under ISIS-II disk operating systems and produces efficient relocatable object modules compatible for linkage with PL/M 80, FORTRAN 80 and 8085 macroassembler modules. After compilation, the object program may be linked to other modules, then located to an in-circuit emulator module (ICE-80) for software execution and rlebugging in the Intellec environment. 14-24 SP80 SUPPORT PACKAGE SP80 SUPPORT PACKAGE SPECIFICATIONS Environmental Characteristics Operating Temperature - Operating Environment OOto 40°C Operating Humidity - Up to 95% relative humidity with· out condensation. Required Hardware DS002 System Package or equivalent is required Reference Manuals (supplied) DS003 System Package is recommended FORTRAN·80 Programming Manual (9800481) 1515·11 FORTRAN·80 Compiler Operator's Manual (9800480) FORTRAN·80 Programming Reference Card (9800547) PLlM·80 Programming Manual (980026) 1515·11 PLlM·80 Compiler Operator's Manual (9800300) ICE·80 Operator's Manual (9800185) Emulation Clock User's system clock or ICE·80 adaptor socket. Electrical Characteristics DC Power Requirements Vcc= +5V±5% Icc = 10A max; 7A typ Voo= + 12V±5% 100 = 80 mA max; 45 mA typ Vss=,-10V±5% Iss = 1 mA max; 1 "A typ ORDERING INFORMATION Part Number SP80·KIT Description SP80 Support Package Includes ICE·80 In·circuit emulator (MDS·80·ICE), PLlM·80 High·Level Pro· gramming Language (MDS·PLM), and FORTRAN·80 Compiler (MDS·301) 14·25 SP8S SUPPORT PACKAGE • Deve'lopment Support for 8085 Microprocessor Designs, Including: • Programs Written in Pl/M, FORTRAN, and Assembly Language can be Linked Together and Relocated • PL/M 80 Structured High-Level Programming Language Compiler for System Software Development • ICE-858™ Emulation Connects intellec® System Resources to a User's Prototype • Full Symbolic Debugging Is Available for Program Labels or Variables • ANS 77 FORTRAN 80 Compiler for Mathematically Oriented Software Development • External Trace Module Extends Emulation Capability to Prototype System Peripheral Activity • ICE-858™ In-Circuit Emulator 8085 software development begins using the 8085 macroassembler, PLIM 80, FORTRAN 80 high-level languages and compilers. The compilers operate on Intellec microcomputer development systems under ISIS-II disk operating systems and produces efficient relocatable object modules compatible for linkage with PLIM 80, FORTRAN 80 and 8085 macroassembler modules. After compilation, the object program may be linked to other modules, then located to an in-circuit emulator module (ICE-858) for software execution and . debugging in the Intellec environment. ~4-26 SP85 SUPPORT PACKAGE SP85 SUPPORT PACKAGE SPECIFICATIONS Voo= +12V±5% 100 = 80 mA max; 60 mA typ Vss= -10V±5% Iss = 30 mA max; 10 ,..A typ Operating Environment Required Hardware Environmental Characteristics OS002 System Package or equivalent is required. Operating Temperature - OS003 System Package is recommended. O·to 40·C Operating Humidity - Up to 95% relative humidity without condensation. Emulation Clock User's system clock or ICE-85B adaptor socket (6.144 MHz crystal) Reference Manuals (supplied) FORTRAN-80 Programming Manual (9800481) ISIS-II FORTRAN-80 Compiler Operator's Manual (9800480) FORTRAN-80 Programming Reference Card (9800547) PUM-80 Programming Manual (980026) ISIS-II PUM-80 Compiler Operator's Manual (9800300) ICE-85 Operator's Manual (9800463) . Electrical Characteristics DC Power Requirements Vce= +5V±5% Icc = 12A max; 10A typ ORDERING INFORMATION Part Number SP85·KIT Description SP85 Support Package Includes: ICE-85B'" In-circuit emulator (MOS-85B-ICE) PLIM 80 High-Level Programming Language (MOS-PLM)* and FORTRAN 80 Compiler (MOS-301) Requires software license • MDS is an ordering code only and Is not used as a product name or trademark. MDS" is a registered trademark of Mohawk Data Sciences Corporation. 14-27 inter ICE-80™ 8080 IN-CIRCUIT EMULATOR • Connects Intellec® System to User Configured System Via an External Cable and 40-pin Plug, Replacing the User System 8080 • Eliminates Need for Extraneous Debugging Tools Residing in User Sy~em .. • Allows Rei3I-Time (2 MHz) .Emulation of User System 8080 . • Provides Address, Data, and 8080 Status Information onLast44 Machine Cycles Emulated • Shares Intellec® RAM, ROM, and PROM Memory and Intellec®I/O Facilities with User System • Provides Capability to Examine and Alter CPU Registers, MainMemory, Pin, and Flag Values • Checks for Up to Three Hardware and Four Software Break Conditions • Integrates Hardware. and Software Development Efforts • Offers Full Symbolic Debugging . Capabilities • Available in Diskette or Paper Tape . Versions The Intellec ICE-80 8080 In-Circuit Emulator is an Intellec resident module designed to interface with any user configured 8080 system. With ICE-80 as a replacement for a prototype system 8080, the designer may emUlate the system's 8080 in real time, single step the system's program, and substitute Intellec memory and I/O for user system equivalents. Powerful Intellec debug functions are extended into the user system. For the first time the designer may examine and modify his system with symbolic references instead of absolute values. © Intel Corporation 1980 14·28 ICE·80™ IN·CIRCUIT EMULATOR during system debugging. By referring to symbolic memory addresses, the user may be assured of examining, changing, or breaking at the intended location. FUNCTIONAL DESCRIPTION Integrated Hardware/Software Development Use of the ICE-80 module enables the system integration phase, which can be so costly and frustrating when attempting to mesh completed hardware and software products, to become a convenient two·way debug tool when begun early in the design cycle. The user prototype need consist of no more than an 8080 CPU socket and a user bus to begin integration of software and hardware development efforts. With the ICE-80 mapping capabilities, system resources may be accessed for missing prototype hardware. Hardware designs may be tested using system software to drive the final product. A functional block diagram of the ICE-80 module is shown in Figure 1. Symbolic Debugging Capability ICE-80 provides for user-defined symbolic references to program memory addresses and data. Symbols may be substituted for numeric values in any of the.ICE-80 commands. The user is thus relieved from looking up addresses of variables or program subroutines. Symbol Table - The user symbol table generated along with the object file during a PUM-80 compilation or a MAC80 or resident assembly, is loaded to memory along with the user program to be emulated. The user may add to this symbol table any additional symbolic values for memory addresses, constants, or variables found useful Symbolic Relerence - ICE-80 provides symbolic definition of all 8080 registers, flags, and selected pins. The following symbolic references are also provided for user convenience: TIMER, a 16-bit register containing the number of ~2 clock pulses elapsed during emulation; ADDRESS, the address of the last instruction emulated; INTERRUPTENABLED, the user 8080 interrupt mechanism status; and UPPERLIMIT, the highest RAM address occupied by user memory. Debug Capability Inside User System ICE-80 provides for user debugging of full prototype or production systems without introducing extraneous hardware or software test tools. ICE-80 connects to the user system through the socket provided for the user 8080 in the user system (See Figure 2). Intellec memory is used for the execution of the ICE-80 software, while 110 provides the user with the ability to communicate with ICE-80 and receive information on the generation of the user system. A sample ICE-80 debug session is shown in Figure 3. I/O Mapping and Memory Memory and 110 for the user system may be resident in the user system or "borrowed" from the Intellec system through ICE-80's mapping capability. 16 ADDRESS B DATA OUT a DATA IN CONTROL r-----~-----------l I I I I I I I I I I I I I I I I L_ ICE-SO TRACE BOARD -----------_ ..... CONTROL} B DATA "SITS INTELL.EC BUS 16 ADDRESS BITS Figure 1. Functional Block Diagram 01 ICE-SO Module 14·29 ICE·80™ IN·CIRCUIT EMULATOR ICE-80 trace board. ICE-80 and the system also commu· nicate through a control block resident in the Intellec main memory, which contains. detailed configuration arid status information transmitted at an emula.tion break. ICE-80 hardware consists of two PC boards - the processor and trace boards residing in the Intellec chassis - and a 6-foo!. cable interfaCing to the user system, The trace and processor boards communicate with the system on the bus, and also with each other on a separate ICE-80 bus. ICE-80 connects to the user system through a cable that plugs directly into the socket provided for the user's 8080. trace Board The trace board .talks to the' system as a peripheral device. It receives commands to ICE-80 and returns ICE-80. responses. While ICE-80 is executing the user program, the trace board collects data for each machine cycle emulated (snap data). The information is continuously stored in high-speed bipolar memory. Figure 2. ICE·aO Module Installed in User System Memory Blocking- ICE·80 separates user memory into 16 4K blocks. User I/O is divided into 16 16·port blocks. Each block of memory or I/O may be defined independ· ently. The user may assign system equivalents to take the place of devices not yet designed for the user system during prototyping. In addition, memory or I/O may be accessed in place of user system devices during prototype or production checkout. Error Messages - The user may also designate a block of memory or I/O as nonexistent. ICE-80 issues error messages when rilemoryor I/O designated as nonexisting is accessed by the user program. Real-Time Trace ICE-80 captures valuable trace information while the user is executing programs in real time. The 8080 status, the user memory or port addressed, and the data read or written (snap data), is stored for the last 44 machine cycles executed. This provides ample data for determining how the user system was reacting prior to emulation break. It is available whether the break was user initiated or the result of an error condition. For detailed information on the actions of CPU registers, flags, or other system operations, the user may operate in single or multiple step sequences tailored to system debug needs. Hardware The heart of the ICE-80 is a microcomputer system utilizing Intel's 8080 microprocessor as its nucleus. This system communicates with the Intellec host processor via .I/O commands .. Host processor .commands and ICE-80 status are interchanged through registers on the Breakpoint - The trace board also contains two 24-bit hardware breakpoint registers which can be loaded by the user. While in emulation mode, a hardware compari' tor is constantly monitoring address and status lines for a match to terminate an emulation. A user probe is also available for attachment to any user signal. When this signal goes true a break condition is recognized. Interrogation - The trace board signals the processor board when a comma.nd to ICE-80 or break condition has been detected. The ICE-80 CPU then sends data stored on the trace board to the control block in memory. Snap data, along with information on 8080 registers and pin status and the reason for the emulation break, are then available for access during interrogation mode. Error conditions, if present, are transmitted and automatically displayed for the user. Processor Board An 8080 CPU resides on the processor board. During emulation it executes instructions from the user's program. At all other times it executes instructions from the control program in the trace module's ROM. Timing - ,The processor board contains an internal clock generator to provide clocks to the user emulation CPU at 2 MHz. The CPU can alternately be driven by a clock derived from user system signal lines. The clock source is selected by a jumper option on the board. A timer on .the trace board counts the ~2 clock pulses during emulation and can provide the user with the exact timing of the emulation. On/Off Control - The processor board turns on an emulation when ICE-80 has received a run command from the system. It terminates emulation when a break condition is detected on the trace board, or the user's program attempts to access memory or I/O ports designated as nonexistent in the user system, or the user 8080 is inactive for a quarter of a second. Status Storage - The address map located on the processor board stores the assigned location of each user memory or I/O . block. During emulation the processor board determines whether to send/receive information 14-30 ICE·80™ IN·CIRCUIT EMULATOR ISIS BOBO MACROASSEMBLER, V1.0 PAGE I ;USER PROGRAM TO OUTPUT A SERIES OF ;CHARACTERS TO SDK·BO CONSOLE DEVICE 1320 0lE3 13200601 13223A3613 1354F 1326 CDE301 132979 132A 93 132B 323713 132E FE40 1330 C22513 1333 C32013 13365A 1337 0000 CO START: LOOP: DAn: RSLT: ORG EOU 1320H IE3H MVI LOA MDV CALL MOV SBB STA CPI JNZ JMP B,I DAn C,A CO A,C B RSLT 40H LOOP START DB OS END 5AH I ;SDK·BO CONSOLE OUT DRIVER ;SET UP B VALUE ;LOAD A WITH DATI VALUE ;SEND C VALUE TO CONSOLE ;RESTORE A ;SUBTRACT B FROM A ;STORE RESULT IN RSLT ;LAST VALUE TO PRINT ;LOOP AGAIN IF A>40H ;ELSE RESTART WHOLE PROCEDURE ISIS, VI.O INITIALICE·BO SESSION ·ICE80 (Nole: The SDK·BO Monitor has already been used to initialize the SDK·BO Board) ISIS ICE·BO, VI.O ""XFORM MEMORY 0 TO I U "XFORM 10 OFH U CD @ "LOAD PROG. HEX ERR = 067 STAT = IIH TYPE = 06H CMND = 07H ADDR = 1320H GOOD = 06H BAD =04H ·CHANGE MEMORY 1321H FFH ERR = 067 STAT=IIH TYPE=06H CMND=07H ADDR=I32IH GOOD=FFH BAD=FDH "LOAD PROG. HEX "GO FROM START UNTIL RSL T WRITTEN EMULATION BEGUN ERR=067 STAT=IIH TYPE=07H CMND=02H "DISPLAY CYCLES 5 = @ o ® ® (j) ® STAT = A2H ADDR = 1326H DATA = CDH STAT=B2H ADDR=1327H DATA=E3H STAT=62H ADDR=1326H DATA=OIH STAT=04H ADDR=FFFFH DATA=13H STAT=04H ADDR=FFFEH DATA=29H "CHANGE DOUBLE REGISTER SP=13FFH "BASE HEX "EOUATE STOP =.1333H "GO FROM START UNTIL STOP EXECUTED THEN DUMP EMULATION BEGUN B =OIH C = 41H D=OOH E= OOH H = OOH L= OOH F = 56H A=40H P= 1320H "= 1333H S= 13FFH EMULATION TERMINATED AT 1333H "EXIT "FFFF Notes 1. Set up user memory and 1/0. The program is set up to execute in block 1 (1000H-1FFFH) of user memory, and requires access to the SDK·eO monitor (block 0) and 110 ports in block OFH. Bolh porls and memory are defined as available 10 Ihe user syslem. All other memory and 110 Is Initialized by ICE·aO as nonexislenl (guarded). 2. A load command generates an error. The type' and command numbers indicate that a data mismatch occurred on a write to memory command. The data to be wrillen to address 1320H should have been aSH. When ICE-aO read the data after writing It, a 04H was detected. A change command 10 a differenl memory address hlnls thai bill does nol go to 1 anywhere In Ihis memory block. Examlnallon Indicates that a pin was shorted on Ihe RAM localed a11300H-13FFH in Ihe prololype syslem. The problem is fixed and a subsequenlload succeeds. 3. A real-lime emulalion is begun. The program Is executed from 'START' (1320H) and continues until 'RSLT' Is wrltlen [in location 132aH, Ihe conlenls of Ihe accumulalor is slored in (wrillen Inlo) 'RSLT']. 4. An error condilion resulls: TYPE 07, CMND 02 Indicate Ihe program accessed Is a guarded area. 5. The lasl5 machine cycles executed are displayed. The last Inslruction executed was a call (CDH). The fourth and fifth cycles are a push'operalion (designaled by slalus 04H) 10 slore Ihe program counler before execuling Ihe call. The slack pOinter was nollnltlallzed In the program and is ac-, cessing memory location FFFFH. S. After making a note to inilialize Ihe Slack poinler in the nexl assembly, a temporary fix is effected by seiling the stack pointer 10 the top of user available memory. 7. After seiling the base for displays to hex and adding Ihe symbol 'STOP' to the symbol table, emulation is started which wlilierminate when the instruction al1333H ('STOP') is executed. When emulation terminates, a dump of the contents of user 80aO registers Is requested. One can see that the value of the accumulator is set at 40H, the stack pOinter Is set at 13FFH, the last address executed (") Is 1333H, and the program counter has been sel to 1320H. a. Exit returns conlrol to the MDS monitor. Figure 3" Sample ICE·SO Debug Session 14·31 ICE·80™ IN·CIRCUIT EMULATOR on the Intellec or user bus by consulting the address map. The processor board allows the ICE-80 CPU to gain access to the bus as a master to "borrow" Intellec facilities. At an emulation break, the processor board stores the status of specified 8080 input and output signals, disables all interaction with the user bus, and commands the trace board to send stored information to a control block in Intellec memory for access during interrogation mode. a broad range of modifiers to provide the user with maximum flexibility in describing the operation to be performed. Listings of emulation commands, interrogation commands, and utility commands are provided in Table 1, Table 2, and Table 3, respectively. Command Base Cable Card Display Prints contents of memory, 8080 registers, input ports, 8080 flags, 8080 pins, snap data, symbol table, or other diagnostic data on list device. May also be used for base-to-base conversion, or for addition or subtraction in any base. Change Alters contents of memory, register, output port, or 8080 flag. XFORM Defines memory and 110 status. Search Looks through memory range for speci· fied value. The cable card is included for cable driving. It transmits address and data bus information to the user system through a 40'pin connector that plugs into the user system in the socket designed for the 8080 when enabled by the processor module's user bus control logic. Software The ICE-80 software driver is a RAM-based program providing easy to use English language commands for defining breakpoints, initiating emulation, and interrogating and altering the user system status recorded during emulation. ICE-80 commands are configured with Command Operation Establishes mode of display for output data. Tabie 2. ICE-80 Interrogation Commands Operation Initiates real-time emulation and allows user to specify breakpoints, data retrieval, and conditions under which emulation should be reinitiated. Command Operation Load Fetches user symbol table and object code from input device. Save Sends user symbol table and object code to output device. Initiates emulation in single or multiple instruction increments. User may specify register dump or tailor diagnostic activity to his needs following each step, and define conditions under which stepping should continue. Equate Enters symbol name and value to user symbol table. Fill Fills memory range with specified value. Move Moves block of memory data to another area of memory. Range Delimits blocks of instructions for which register dump or tailored diagnostics are to occur. Timeout Enables/disables user CPU 1/4 second wait state timeout. List Continue Resumes real·time emulation. Defines list device (diskette-based version only). Call Emulates user system interrupt. Exit Returns program control to monitor. Go Step Table 1. ICE-80 Emulation Commands Table 3. ICE·80 Utility Commands SPECIFICATIONS Diskette·Based Operating Environment Paper Tape·Based Operating Environment Required Hardware Intellec system 32K bytes RAM memory System console Inteilec diskette operating system ICE-80 module Required Hardware Intellec system System console Reader device Punch device ICE-80 module Required Software System monitor Required Software System monitor 1515-/1 14·32 ICE·80lM IN·CIRCUIT EMULATOR System Clock 100= 79 rnA max; 45 rnA typ Vee= -9V, ±5% lee= 1 rnA max; 1"A typ Crystal controlled 2.185 MHz±0.01%. May be replaced by user clock through jumper selection. Physical Characteristics Width - 12.00 in. (30.48 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 8.00 Ib (3.64 kg) Electrical Characteristics DC Power Requirements Vee= +5V, ±5% lee= 9.81A max; 6.90A typ Voo = + 12V, ± 5% Environmental Characteristics Operating Temperature - O·C to 40·C Operating Humidity - Up to 95% relative humidity without condensation Equipment Supplied Printed circuit modules (2) Interface cables and buffer board ICE·80 software driver, paper tape version (lCE-80 software driver, diskette-based version is supplied with diskette operating systems) Operator's Manual ORDERING INFORMATION Part Number Description MDS-80-ICE· 8080 CPU in-circuit emulator, .cable assembly and interactive software included • MDS is an ordering code only and is not used as a product name or trademark. MDS~ is a registered trademark of Mohawk Data Sciences Corporation. . 14-33 intel' ICE-858™ MCS-85™ IN-CIRCUIT EMULATOR WITH MULTI-ICE™ SOFTWARE • Offers full symbolic debugging capability for both assembly language and Intel's high-level compiler languages PL/M-80 and FORTRAN-80 • Connects the Intellec® system resources to the user-configured system via a 40-pin adaptor plug • Executes user system software in real-time (5 MHz clock) • The Multi-ICETM software provides: -for two In-Circuit Emulators to operate simultaneously in a single Intellec Microcomputer Development System. -support for ICE 85/85™, 85/49™, and 85/41A™ Emulator combinations -enhanced software features: symbolic display of addresses, macro commands, compound commands, software synchronization of processes, and INCLUDE file capability. • Allows user-configured system to share Intellec® memory and I/O facilities • Provides 1023 states of 8085 trace data • Displays trace data from the user's 8085 in assembler mnemonics and allows personality groupings of data sampled by the external 18-channel trace module The ICE-8S8™ module resides in the Intellec® Microcomputer Development System and interfaces to the user system's 8085. It provides the ability to examine and alter MCS-8S™ registers, memory, flag values, interrupt bits and I/O ports. Using the ICE-8S8 module, the designer can execute prototype software in real-time or single-step mode and can substitute Intellec® system memory and I/O for user system equivalent. ICE capability can be extended to the rest of the user system peripheral circuitry by allowing the user to create and execute a library of user-defined peripheral chip analyzer routines. Multi-ICE In-Circuit Emulator is a software product which allows two Intel In-Circuit Emulators to run simultaneously in a single Intellec Microcomputer Development System. Multi-ICE software used in lieu of the standard ICE software gives users full control of the two ICE modules for debugging of multi-processor systems. ©INTEL CORPORATION. 1980. 14-34 «> AFN·01557A - ICE-8SBTM IN-CIRCUIT EMULATOR SYMBOLIC DEBUGGING CAPABILITY to provide ready acknowledge when accessing resources mapped to the Intellec. ICE-858 allows the user to make symbolic references to I/O ports, memory addresses and data in his program. Symbols and PUM-80 statement number may be substituted for numeric values in any of the ICE-85 commands. The user is relieved from looking up addresses of variables or program subroutines. The user symbol table generated along with the object file during a PUM-80 or FORTRAN-80 compilation or by the ISIS-II 8080/8085 Macro Assembler is loaded into the Intellec® System memory along with the user program which is to be emulated. The user may add to this symbol table any additional symbolic values for memory addresses, constants, or variables that are found useful during system debugging. 8y referring to symbolic memory addresses, the user can examine, change or break at the intended location. ICE-858 provides symbolic definition of all 8085 registers, interrupt bits and flags. The following symbolic references are also provided for user convenience: TIMER, the low-order 16 bits of a register containing the number of 2 MHz clock pulses elapsed during emulation; HTIMER, the high-order 16 bits of the timer counter; PPC, the address of the last instruction emulated; 8UFFERSIZE, the number of frames of valid trace data (between 0 and 1022). The user can also designate a block of memory or I/O as nonexistent. ICE-858 issues' error messages when memory or I/O designated as nonexistent is accessed by the user program. INTEGRATED HARDWARE/SOFTWARE DEVELOPMENT The user prototype need consist of no more than an 8085 CPU socket and a user bus to begin integration of software and hardware development efforts. Through ICE-858 mapping capabilities, Intellec® System equivalents can be accessed for missing prototype hardware. Hardware designs can be tested using the system software which will drive the final product. The system integration phase, which can be so costly when attempting to mesh completed hardWare and software products, becomes a convenient two-way debug tool when begun early in the design cycle. . PERSONALITY GROUPED DISPLAYS Trace data in the 1023 by 42-channel real-time trace memory buffer is displayed in easy to read format. The user has the option to specify trace data displays in actual 8085 assembler instruction mnemonics. The data collected from the External Trace Module can be grouped and symbolically named according to user specifications and displayed in the appropriate number base designation. Simple ICE-858 commands allow the user to select any portion of the 42-bit trace buffer for immediate display. MEMORY AND I/O MAPPING INTERROGATION AND UTILITY COMMANDS DISPLAY/ CHANGE Display/Changes the values of symbols and the contents of 8085 registers, pseudo-registers, status flags, interrupt bits, I/O ports and memory. EVALUATE Displays the value of an expression in the bihary, octal, decimal or hexadecimal. Memory and I/Ofor the user system can be resident in the user system or "borrowed" from the Intellec® System through ICE-858's mapping capability. SEARCH Searches user memory between locations in a user program for specified contents. ICE-858 separates user memory into 32 2K blocks. Each block of memory can be defined independently. The user may assign Intellec® System equivalents to take the place of devices not yet designed for the user system during prototyping. Ih addition, Intellec® System memory or I/O can be accessed in place of suspect user system devices during prototyping qr production checkout. CALL Emulates a procedure starting at a specified memory address in user memory. ICALL Executes a user-supplied procedure starting at a specified memory address in the Intellec(!) System memory. EXECUTE Saves emulated program registers and emulates a user-supplied subroutine to access peripheral chips in the user's system. User ready synchronization-resource borrowing from the Intellec System is (at user option) independent of the user system; the user does not need 14-35 ...!~--- ICE-8SBTM IN-CIRCUIT EMULATOR REALTIME TRACE EXTERNAL TRACE MODULE. ICE-858 captures valuable trace information from the emulating CPU and the External Trace Module while the user is.executing.prClgrams in real time. The 8085 status, the user memory or port addressed, the data read or written, .theserial data lines and data from 18 external signals, is stored for the last 1023 machine states executed (511 machine cycles).This provides ample data for determining how the user system was reacting prior to emulation break. It is available whether the break was user-initiated or the result of an error condition. TTL level signals from 18 points in the user system may be synchronously sampled by the External Trace Module and collected in ICE-858's trace buffer. The signals can be collected from a single peripheral chip via the supplied 40-pin DIP clip or may be placed by the user on up to 18 separate signal nodes using the supplied 18 individual probe clips. These signals are included in the 42-channel breakpoint comparisons and clock qualifiers. Also,data from these 18 channels may be displayed in meaningful, user-defined groupings. For detailed information on the actions of CPU registers,flags, or other system operations, the user may operate in single or mUlti-step sequences tailored to system debug needs. SYNCHRONOUS OPERATION WITH OTHER DESIGN AIDS ICE-858 can be synchronized with other Intellec® design aids by means of two external synchronization lines. These lines are used to enable and disable ICE-858 trace data collection and to cause break conditions based on an external signal which may not be included in the ICE-858 breakpoint registers. In addition, ICE-858 can generate signals on these lines which may be used to ·controlother design aids. BREAK REGISTERS/ TRACE MEMORY ICE-858 has two breakpoint registers which are used to break emulation, and two trace qualifier registers which are used to control the collection of trace data during emulation. Each register is 42 entries wide, one entry for each channel and each entry can take anyone of the three values 0, 1 or "don't care." EMULATION CONTROLS AND COMMANDS GROUP Defines into a symbolically named group, a channel or combination of channels from the 8085 Microprocessor and/or the External Trace Module. GO Initiates real-time emulation and controls emulation break conditions. STEP Initiates emulation in single instruction steps. User may specify the type and amount of information displayed following each step, and define conditions under which stepping should continue. PRINT The trace buffer, alsp.42 entries wide, collects. data sampled from 248085 processor channels and 18 external channels sampled by the External Trace Module. The signals collected from the 8085 include address lines, data lines, status lines and serial input and output lines. The 18 channels extending from the External Trace Module synchronously sample and collect into the trace buffer any user-specified TTL compatible signal from the rest of the prototype system. "8re.ak" and "trace qualification" may therefore occur as a result of a match of any combination of up to 42 channels of CPU and external circuitry signals. . Prints the user.-specified portion of the trace memory to the selected list device. MULTI-ICE™OPERATION Multi-ICE software is a debug tool which allows two ICE emulators to begin and stop in sequence. Once started, two ICE emulators emUlate simultaneously and independently. Thus, Multi-ICE software permits the debugging of asynchronous or synchronous. multi-processor systems. 14·36 -.. -~ ICE-8S8™ IN-CIRCUIT EMULATOR A conceptual model for the Multi-ICE software can be illustrated with the following block diagram. Macro Command A macro isaset of commands which is given a name. Thus, a group of commands which is executed frequently may be defined as a macro. Each time the user wants to execute that group of commands, he may just invoke the macro by typing a colon followed by the macro name. Up to ten parameters may be passed to the macro. Block Diagram of Multi-ICE™ Operation There are three processes in the Multi-ICE environment: the Host process and the two ICE processes to control the two ICE hardware modules. The processor for these three processes is the microcomputer in the Intellec Microcomputer Development System. Only the Host process is active when MultiICE software is invoked. The Parser interfaces with the console, receives commands from the console or from a file, translates them into intermediate code, and loads the code into the Host command code buffer or ICE command code buffers. The Host process executes commands from its command code buffer using the execution software and hardware of the Host's current environment, either environment 1 or environment 2 (EN1 or EN2), as required. EN1 and EN2 are the operating environments of the two In-Circuit Emulators. The user can change the execution environment (from EN1 to EN2 or vice versa) with the SWITCH command. Once the environment is selected, ICE operation is the same as with standard ICE software. In addition, the enhanced software capabilities are available to the user. The two ICE processes (PR1 and PR2) execute commands from their command code buffers in their own environments (PR1 in EN1 and PR2 in EN2). The main functions of the two ICE execution processes are to control the operations of the two ICE hardware sets. The ACTIVATE command controls the execution of the ICE processes. Commands are passed on to each ICE unit to initiate the desired ICE functions. The two ICE hardware units accept commands from the Host process or ICE processes. Once emulations start, the two ICE hardware sets will operate until a break condition is met or processing is interrupted by commands from the ICE execution processes. Macro commands may be defined at the beginning of a debug session and then can be used throughout the whole session. If the user wants to save the macros for later use, he may use the PUT command to save the macro on diskette, or the user may edit the macro file off-line using the Intellec text editor. Later, the user may use the INCLUDE command to bring in the macro definition file that he created. Example: 'DEFINE MACRO INITMEM .. SWITCH = EN1 .. BYTE 0 TO 100=0 "LOAD:F1 :DRIVER .. SWITCH = EN2 "LOAD:F1 :DR2 .. EM ;This macro clears the memory and then loads the programs. ;Select environment 1 (ICE Module 1) ;Initialize memory to O. ;Load user program into memory for ICE Module 1. ;Select environment 2 (ICE Module 2) ;Load user program into memory for ICE Module 2 ;End of Macro ;To execute this Macro, user types :INITMEM Compound Command Compound commands provide conditional execution of commands (IF Command) and execution of commands repeatedly until certain conditions are met (COUNT, REPEAT Commands). Compound commands and Macro commands may be nested any number of times. Example: 'DEFINE .1 = 0 'COUNT 100H .. IF .1 AND 1 THEN ... BYT.I = .1 ;Define symbol .I to 0 ;Repeat the following commands 100H times ;Check if .1 is odd ;Fill the memory at location .1 to value .1 ... END ".1 = .1 + 1 .. END ;Increment .1 by 1 ;Command executes upon carriage-return after END Symbolic Display of Addresses INCLUDE File Capability The user has the option of displayi ng a 16-bit address in the form of a symbol name or line number plus a hex number offset. The INCLUDE command causes input to be taken from the file specified until the end of the file is encountered, at which point, input continues to be 14-37 ICE-85BTM.IN-CIRCUIT EMULATOR taken from the previous source. Nesting of INCLUDES is permitted. Since the command code file can be complex, the ability to edit offline becornes desirable. The INCLUDE command allows the user to pull in command code files and Macro commands created offline which can then be used for the particular debugging session: Example: 'INCLUDE :F1.:PROG1 'MAP 0 lENGTH 64K =USER· 'MAP 100 TO FF =USER 'SWITCH = EN2 'lOAD :F2:lED.HEX 'sWITcH = EN1 . PROCESSOR 1 PROCESSOR' DORMAHT ;Cause input to be taken from file PROG1 ;Contents of the file PROG1 are listed on screen as they are executed. Softwar, Synchronization of Processes Up to three processes (Host, PR1 and PR2) can be active simultaneously in the system. An ICE process can be activated (ACTIVATE), suspended (SUSPEND), kiiled (Kill), or continued (CONTINUE). The Host process. can wait for other processes to become dormant before it becomes active again. Through these synchronization commands; the user can create a system test file off-line yet be able to synchronize the three processes when the actual system test is executed. Example: The capability of the software synchronization commands is demonstrated by the. foll,owing example. The flowchart shows the synchronization requirements. The program steps show the actual implementation. ;End of the file PROG1 ;After the end. of file is reached, control is returned to console. HOST PROCESSOR PROCESSOR 2 ACTIVE I I --TAC~- ACTIVATE PROCESSOR I I PROCESSOR 2 " I. I eQUANT ' 'ACTIVATE PRl ;Activate PRt .'GO FROM 800 ;Slart ICE Module 1 ;End 01 Activate block ,"END PRl EMULATION BeGUN 'SWI",EN2 ~REPEAT PC ,'WHILE' < > ,LOOP .'ICT PR2 ..'GO TILL .lOOP OR .END ..'REQISTER ,,"END .·WAIT·PR2 .'IF PC=.LOOP THEN .. ·SUSPEND PRl . ~-~-- ,,"END ,'END ;Swltch execution Environment 10 EN2 ;Repeat·the following block of commands whirs PC Is nol aquallD .LOOp ;~ctlv8te PR2 . ;Go till instruction at location. Loop or at location .END Is executed . ;Dlsplay the registers ;End of Activate block ;Walt u.ntll PR2 Is dormant :End of IF block :End of REPEAT block I PROCESSOIII I DO«.....NT Flowchart of the Example for Demonstrating Multi-ICETM Synchronization Capability 14-38 ICE-858™ IN-CIRCUIT EMULATOR SPECIFICATIONS Emulation Clock ICE-SSB T " Operating Environment User's system clock or ICE-85B adaptor socket (10.0 MHz Crystal) Required Hardware: Intellec® Microcomputer Development System (64K bytes RAM for Multi-ICE software) (32K bytes RAM single ICE software) System Console Intellec® Diskette Operating System ICE-85B Module Required Software: System Monitor ISIS-II ICE-85B or Multi-ICE Software Physical Characteristics Printed Circuit Boards: Width: 12.00 in. (30.48 cm) Height: 6.75 in. (1715 cm) Depth: 0.50 in. (1.27 cm) Packaged Weight: 6.00 Ib (2.73 kg) Electrical Characteristics DC Power: Vcc=+5V±5% Icc = 12A maximum; 10A typical Voo = + 12V±.5% 100 = 80 mA maximum; 60 mA typical V BB = - 10V ± 5% IBB= 1 mAmaximum; 10 p.A typical Equipment Supplied 18-Channel External Trace Module Printed Circuit Boards (2) Interface Cable and Emulation Buffer Module Operator's Manuals ICE-85B Software Multi-ICE Software Contains software that supports 85/85 Emulators, 85/49 Emulators and 85/41A Emulators L _________ _ Environmental Characteristics Operating Temperatu re: 0° to 40°C Operating Humidity: Up to 95% relative humidity without condensation. ~--- 1---------- ~---- r--~'---,-~ SYNC 0 I I TRACE MEMOR¥ I AND QUALIFIER REGISTERS CHIP DATA I CONTROL ADDRESS I J TO USER'S SOCKET I I t=~~I=======:!:::=;;;;=::::!-----_1oSYNC 1 L ____________________ _~ ICE 8S TRACE BOARD ~ B085 CHIP CONTROLLER ,.----------, K====J ~:~:~~ I SIGNAL BUFFERS l __________ J 18 EXTERNAL TRACE BUFFER ICE-85BTM BLOCK DIAGRAM 14·39 TRACE ICE-8SBTM IN-CIRCUIT EMULATOR Ordering Information Part Number Description MDS*-85S-ICE 8085 CPU In-Circuit Emulator, 18-Channel External Trace Module and Multi-ICE software MDS*-85U-ICE Upgrade kit to convert ICE-85 or ICE-85A to ICE-85S functionality. Consists of Multi-ICE software and 5MHz Hardware "'MDS" is an ordering code only. and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corp. 14·40 iAPX 86/88 Support Options 15 SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES • CONY 86/88 Converter for Conversion of 8080/8085 Assembly Language Source Code to 8086/8088 Assembly Language Source Code • PL/M 86/88 High Level Programming Language • ASM 86/88 Macro Assembler for 8086/8088 Assembly Language Programming • OH 86/88 Object-to-Hexadecimal Converter • LINK 86/88 and LOC 86/88 Linkage and Relocation Utilities • LIB 86/88 Library Manager The Series II 8086/8088 software development packages provide a set of software development tools for the 8086 and the 8088 microprocessors and iSBC 86/12A single board computer. The package operates under the ISIS-II operating system on InteHec Microcomputer Development Systems-Model 800 or Series II-thus minimizing requirements for additional hardware or training for Intel Microcomputer Development System users. These packages permit' 8080/8085 users to efficiently upgrade existing programs into 8086/8088 code from either 8080/8085 assembly language source code or PLIM 80 source code. . For the new Intel Microcomputer Development System user, the packages operating on an Intellec Series II, such as a Model 235, provide total 8086/8088 software development capability. 15·1 9800757-04 intJ SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES SERIES II PL/M 86/88 COMPILER • Language is Upward Compatible from PL/M 80, Assuring MCS-80/85™ Design Portability • Supports 16-.bit Signed Integer and 32-bit Floating Point Arithmetic in Accordlilnce with IEEE Proposed Standard • Produces Relocatable Object Code Which is Linkable to All Other 8086 Object Modules • Supports Full Extended Addressing Features of the 8086 and the 8088· Microprocessors (Up to 1 Mbyte) • Code Optimization Assures Efficient Code Generation and Minimum Application Memory Utilization • Easy-to-Learn,.Block-Structured Language Encourages Program Modularity Like its counterpart for MCS-80/85 program development, PLIM 86/88 is an advanced, structured ~igh-Ieliel programming language. The PLIM 86/88 compiler was created specifically for performing software development for the Intel 8086 and 8088 Microprocessors. PLIM 86/88 has significant neW capabilities over PLIM 80 that take advantage of the new facilities provided by the 8086 and the 8088 microprocessors, yet the PLIM 86/88 language remains compatible with PLIM 80. With the exception of hardware-dependent modules, such as interrupt handlers, PLIM 80 applications may be recompiled with PLIM 86/88 with little need for modification. PLIM 86/88, like PLIM 80, is easy to learn, facilitates rapid program development, and reduces program maintenance costs. PLIM is a powerful, structured, high-level system implementation language in which program statements can naturally express the program algorithm. This frees the programmer to concentrate on the logic of the program without concern for burdensome details of machine or assembly language programming (such as register allocation, meanings of assembler mnemonics, etc.). The PLIM 86/88 compiler efficiently converts free-form PLIM language statements into equivalent 8088/8086 machine instructions. Substantially fewer PLIM statements are necessary for a given application than if it were programmed at the assembly language or machine code level. The use of PLIM high-level language for system programming, instead of assembly language, results in a high degree of engineering productivity during project development. This translates into significant reductions in initial software development and follow"on maintenance costs for the user. FEATURES structure allows the use of REENTRANT which is especially useful in system design. Major features of the Intel PLIM 86/88 compiler and programming language include: Language Compatibility PLIM 86/88 object modules are compatible with object modules generated by all other 86/88 translators. This means that PLlMprograms may be linked to programs written in any other 86/88 languages. Block Structure PLIM source code is developed in a series of modules, procedures, and blocks. Encouraging program modularity in this manner makes programs more readable, and easier to maintain and debug. The language becomes more flexible by clearly defining the scope of user variables (local to a private procedure, global to a public module, for example). Object modules are compatible with ICE-88 and ICE-86 units; DEBUG compiler control provides the In-Circuit Emulators with symbolic debugging capabilities. The use of procedures to break down a large problem is paramount to productive software development. The PLIM 86/88 implementation of a block PLIM 86/88 Language is upward-compatible with PLIM 80, so that application programs may be easily ported to run on the iAPX 86 or 88. 15-2 AFN-01239B SERIES 118086/8088 SOFTWARE DEVELOPMENT PACKAGES Supports Five Data Types Interrupt Handling PUM makes use of five data types for various applications. These data types range from one to four bytes, and facilitate various arithmetic, logic, and addressing functions: PUM has the facility for generating interrupts to the iAPX 86 or 88 via software. A procedure may be defined with the INTERRUPT attribute, and the compiler will automatically initialize an interrupt vector at the appropriate memory location. The compiler will also generate. code to same and restore the processor status, for execution of the user-defined interrupt handler routine. The procedure SET$INTERRUPT, the function retuning an INTERRUPT$PTR, and the PLIM statement CAUSE$INTERRUPT all add flexibility to user programs involving interrupt handling. -Byte: -Word: -Integer: -Real: -Pointer: 8-bit unsigned number 16-bit unsigned number 16-bit signed number 32-bit floating point number 16-bit or 32-bit memory address indicator Another powerful facility allows the use of BASED variables that map more than one variable to the same memory location. This is especially useful for passing parameters, relative and absolute addressing, and memory allocation. Segmentation Control The PUM 86/88 compiler takes full advantage of program addressing with the SMALL, COMPACT, MEDIUM, and LARGE segmentation controls. Programs with less than 64KB total code space can exploit the most efficient memory addressing schemes, which lowers total memory requirements. Larger programs can exploit the flexibility of extended one-megabyte addressing. Two Data Structuring Facilities In addition to the five data types and based variables, PUM supports two data structuring facilities. These add flexibility to the referencing of data stored in large groups. -Array: -Structure: Code Optimization The PUM 86/88 compiler offers four levels of optimization for significantly reducing overall program size. Indexed list of same type data elements Named collection of same or different type data elements -Combinations of Each: Arrays of structures structures of arrays -Combination or "folding" of constant expressions; and short-circuit evaluation of Boolean expressions. -"Strength reductions" (such as a shift left rather than multiply by 2); and elimination of common sUb-expressions within the same block. -Machine code optimizations; elimination of superfluous branches; re-use of duplicate code; removal of unreadable code. -Byte comparisons (rather than 20-bit address calculations) for pointer variables; optimization of based-variable operations. or 8087 Numerics Support PL/M programs that use 32-bit REAL data may be executed using the Numeric Data Processor for improved performance. All floating-point operations supported by PUM may be executed on the 8087 NDP, or the 8087 Emulator (a software module) provided with the package. Determination of use of the chip or emulator takes place at link-time, allowing compilations to be run-time independent. Compiler Controls Built-In String Handling Facilities The PUM 86/88 compiler offers more than 25 controls that facilitate such features as: The PUM 86/88 language contains built-in functions for string manipulaiton. These byte and word functions perform the following operations on character strings: MOVE, COMPARE, TRANSLATE, SEARCH, SKIP, and SET. -Conditional compilation -Intra- and Inter-module cross reference -Corresponding assembly language code in the . listing file -Setting overflow conditions for run-time handling 15-3 AFN.()12398 inter .SERIES II BOB6/80BB.S.OFTWARE DEVELOPMENT PACKAGES BENEFITS because less programming resources are required for a given programmed function. PL/M86/88 is designed to be an efficient, costeffective solution to the special requirements of iAPX 86 oreE! Microsystem Software Development, as illustrated by the following benefits of PLIM use: Increased Reliability PLIM 86/88 is designed to aid in the development of reliable software (PLIM 86/88 programs are simple statements of the program algorithm). This substantially reduces th~ risk of costly correction of errors in systems that have already reached full production status, as the more simply stated the program is, the more likely it is to perform its intended function. Low Learning Effort PLIM 86/88 is easy to learn and to use, even for the novice programmer. Earlier Project Completion Critical projects are completed much earlier than otherwise possible because PL/M 86/88" a structured high-level language, increases programmer productivity. Easier Enhancements and Maintenance Programs written in PL/M tend to be selfdocumenting, thus easier to read and understand. This means it is easier to enhance and maintain PLIM programs as the system capabilities expand and future products are developed. Lower Development Cost· Increases in programmer productivity translate immediately into lower software development costs SERIES II 8086/8088 MACRO ASSEMBLER • Powerful and Flexible Text Macro Facility with Three Macro Listing. Options to Aid Debugging • High-Level Data Structuring Facilities Such as "STRUCTUREs" and "RECORDs" • Highly Mnemonic and Compact Language, Most Mnemonics Represent Several Distinct Machine .Instructions • Over 120 Detailed and Fully Documented Error Messages • "Strongly Typed" Assembler Helps • Produces Relocatable and Linkable Detect Errors at Assembly Time Object Code. . ASM 86/88 is the "high-level" macro assembler for the 8086/8088 assembly language. ASM 86/88 translates symbolic 8086/8088 assembly language mne'monics into 8086/8088 relocatable object code. ASM 86/88 should be used where maximum code efficiency and hardware control is needed. The 8086/8088 assembly language includes approximately.JOO instruction mnemonics. From these few mnemonics the assembler can generate over 3,800 distinct machine instructions. Therefore, the software development task is simplified, as the programmer need.know only 100 mnemonics to generate all possible 8086/8088 machine instructions. ASM 86/88 will generate the shortest machine instruction possible given no forward referencing or given explicit information as to the characteristics of forward referenced symbols. ASM 86/88 offers many features normally ·found only in high-level languages. The 8086/8088 assembly language is strongly typed. The assembler performs extensive' checks on the usage of variables and labels: The assembler uses the attributes which are derived explicitly when a variable or label is first defined, then makes sure that each use of the symbol in later· instructions conforms to the usage defined for that symbol. This means that many programming errorswHlbe detected when the program is assembled, long before it is being debugged on hardware. 15-4 AFN·DI239B SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES FEATURES Over 120 Detailed Error Messages Major features of the Intel 8086/8088 assembler and assembly language include: - Powerful and Flexible Text Macro Facility - - Macro calls may appear anywhere Allows user to define the syntax of each macro Built-in functions conditional assembly (IF-THEN-ELSE, WHILE) repetition (REPEAT) string processing functions (MATCH) support of assembly time I/O to console (IN, OUT) Three Macro Listing Options include a GEN mode which provides a complete trace of all macro calls and expansions Support for ICE-86™ Emulation and Symbolic Debugging - High-Level Data Structuring Capability - - Appear both in regular list file and error print file. User documentation fully explains the occurrence of each error and suggests a method to correct it. STRUCTURES: Defined to be a template and then used to allocate storage. The familiar dot notation may be used to form instruction addresses with structure fields. ARRAYS: Indexed list of same type data elements. RECORDS: Allows bit-templates to be defined and used as instruction operands and/or to allocate storage. Debug options for inclusion of symbol table in object modules for In-Circuit Emulation with symbolic debugging. Generates Relocatable and Linkable Object Code-Fully Compatible with LINK 86/88, LOC 86/88 and LIB 86/88 - Permits ASM 86/88 programs to be developed and debugged in small modules. These modules can be easily linked with other ASM 86/88 or PL/M 86/88 object modules and/or library routines to form a complete application system. Fully Supports 8086/8088 Addressing Modes - - Provides for complex address expressions involving base and indexing registers and (structure) field offsets. Powerful EQU facility allows complicated expressions to be named and the name can be used as a synonym for the expression throughout the module. Powerful STRING MANIPULATION INSTRUCTIONS - Permit direct transfers to or from memory or the accumulator. Can be prefixed with a repeat operator for repetitive execution with a count-down and a condition test. 15·5 BENEFITS The 8086/8088 macro assembler allows the extensive capabilities of the 8086/8088 to be fully exploited. In any application, time and space critical routines can be effectively written in ASM 86/88. The 8086/88 assembleroutputs relocatable and linkable object modules. These object modules may be easily combined with object modules written in PLIM 86/88-lntel's structured, high-level programming language. ASM 86/88 compliments PUM 86/88 as the programmer may choose to write each module in the language most appropriate to the task and then combine the modules into the complete applications program using the 8086/8088 relocation and linkage utilities. AFN·01239B SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES CONV 86 MCS-80/85™ to 86/88 ASSEMBLY LANGUAGE CONVERTER UTILITY PROGRAM • Automatically Generates Proper ASM 86/88 Directives to Set Up a "Virtual 8080" Environment that is Compatible with PL/M 86/88 • Translates 8080/8085 Assembly Language Source Code to 8086/8088 Assembly Language Source Code • Provides a Fast and Accurate Means to Convert 8080/8085 Programs to the 8086 and the 8088, Facilitating Program Portability In support of Intel's commitment to software portability, CONV 86/88 is offered as a tool to move 8080/8085 programs to the 8086 and the 8088. A comprehensive manual, "MCS-86 Assembly Language Converter Operating Instructions for ISIS-II Users" (9800642). covers the entire conversion process. Detailed methodology of the conversion process is fully described therein. - CONV 86/88 will accept as input an error-free 8080/8085 assembly-language source file and optional controls, and produce as output, optional PRINT and OUTPUT files. - The PRINT file is a formatted copy of the 8080/ 8085 source and the 8086/8088 source file with embedded caution messages. Because CONV 86/88 is a transliteration process, there is the possibility of as much as a 15%-20% code expansion over the 8080/8085 code. For compactness and efficiency it is recommended that critical portions of programs be re-coded in 8086/8088 assembly language. - The OUTPUT file is an 8086/8088 source file. Also, as a consequence of the transliteration, some manual editing may be required for converting instruction sequences dependent on: - CONV 86/88 issues a caution message when it detects a potential problem in the converted 8086/8088 code. -instruction length, timing, or encoding ~interrupt processing* -PL/M parameter passing conventions* - A transliteration of the 8080/8085 programs occurs, with each 8080/8085 construct mapped to its exact 8086/8088 counterpart: *Mechanical editing procedures for these are suggested in the converter manual. Registers Condition flags Instruction Operands Assembler directives Assembler control lines Macros The accompanying figure illustrates the flow of the conversion process. Initially, the abstract program may be represented in 8080/8085 or 8086/8088 assembly language to execute on that respective target machine. The conversion process is porting a source destined for the 8080/8085 to the 8086 or the 8088 via CONV 86/88. 15-6 .0 AFN-012398 ..• intel· SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES ABSTRACT PROGRAM SOURCE CODE IN 8080/8085 ASSEMBLY LANG ~,~ FOR 8080/8085 EXECUTE ON 8080/8085 SOURCE CODE IN 8088/8088 ASSEMBLY LANG ------ALGORITHM ASSEMBLE FOR 8088/8088 . CONV 88/88 ----------- EQUIVALENT FUNCTION ----------- ----------------------- EXECUTE ON 8088/8088 Figure 1. Porting 8080/8085 Source Code to the 8086/8088 LINK 86 • Automatic Combination of Separately Compiled or Assembled 8086/8088 Programs Into a Relocatable Module • Automatic Generation of a Summary Map Giving Results of the LINK 86/88 Process • Automatic Selection of Required Modules from Specified Librari.es to Satisfy Symbolic References • Abbrev.iated Control Syntax. • Relocatable Modules may be Merged into a Single Module Suitable for Inclusion in a Library • Supports "Incremental" Linking • Supports Type Checking of. Public and External Symbols • Extensive Debug Symbol Manipulation, Allowing Line Numbers, Local Symbols, and Public Symbols to be Purged and Listed Selectively LINK 86/88 combines object modules specified in the LINK 86/88 input list into a single output module. LINK 86/88 combines segments from the input modules according to the order in which the modules are listed. LINK 86/88 will accept libraries and object modules built from PLIM 86/88, ASM 86/88, or any other translator generating Intel's 8086 Relocatable Object Modules. . . . .support for incremental linking is provided since an output module produced by LINK 86/88 can be aninput to another link.At each stage in the incremental linking proces!i,. unneeded public symbols may be purged. LINK 86/88 supports type checking of PUBLIC and EXTERNAL symbols reporting an error iftheirtypes are not consistent. LINK 86/88 will link any valid setof input modules without any controls. However,'controls are available to control the output of diagnostic information in the LINK 86/88 process and to control the content of the output module. LINK 86/88 allows the user to create a large program as the combination of several smaller, separately compiled modules. After development and debugging of these component modules the user can link them together, locate them using LOC 86/88 and enter final testing with much' of the work accomplished. 15-7 AFN-01239B inter SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES LIB 86/88 •. Libraries Can be Used as Input to LINK 86/88 Which Will Automatically Link Modules from the Library that Satisfy External References in the Modules Being Linked • LIB a6/88 Is a Library Manager Program which Allows You to: ~reate Specially Formatted Files to ¢ontain Libraries of Object Modules Maintain These Libraries by Adding or Dele.ting Modules Print a Listing of the Modules and Public Symbols in a Library File ! • " • Abbreviated Control Syntax Libraries aid in the job of building programs. The library manager program LIB 86/88 creates and maintains files containing object modules. The operation ,of LIB 86/88 is controlled by commands to indicate which operation LIB 86/88 is to perform. The commands are: CREATE: ADD: DELETE: LIST: EXIT: creates an empty library file adds object modules to a library file qel~tes modules from a library file lists the module directory of .library files terminates the LIB 86 program and returns control to ISIS-II When using object libraries, the linker will call only those object modules that are required to satisfy external " references, thus saving memory space. Loe 86/88 • Automatic Generation of II Summary Map Giving Starting Address, Segment Addresses and Lengths, and Debug Symbols and their Addresses • Automatic and Independent Relocation of Segments. Segments May Be Relocated to Best Match Users Memory Configuration • Extensive Capability to Manipulate the Order and Placement of Segments in 8086/8088 Memory • Extensive Debug Symbol Manipulation, Allowing Line Numbers, Local Symbols, and Public Symbols to be Purged and Listed Selectively • Abbreviated Control Syntax Relocatability allows the programmer to code programs or sections of programs without having to. know the final arrangement of the object code in memory. " LOC 86/88 converts relative addresses in an input module to absolute addresses. LOC 86/88 orders the segments in the input module and' assigns absolute addresses to the segments. The sequence in which the segments in the input modu'le are assigned absolute addresses is determined by their order in the input module and the controls supplied with the command. LOC 86/88 will relocate any valid input module without any controls. However, controls are available to control the output of diagnostic information in the LOC 86/88 process, to control the content of the output module, or both. The program you are developing will almost certainly use some mix of random access memory (RAM), readonly memory (ROM); andlor programmable read-only memory (PROM). Therefore, the locationot your program affects ti6th cost and performance in your application. The relocation feature allows you todevelop your program on the Intellec development system and then simply relocate the object code to suit your application. AFN·01239B .Q .• SERIES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES OH 86/88 • Converts an Absolute Module to a More Readable Format that can be Displayed on a CRT or Printed for Debugging • Converts an 8086/8088 Absolute Object Module to Symbolic Hexadecimal Format • Facilitates Preparing a File for Later Loading by a Symbolic Hexadecimal Loader, such as the iSBC™ Monitor SDK-86 Loader, or Universal PROM Mapper The OH 86/88 command converts an 8086/8088 absolute object module to the hexadecimal format. This conversion may be necessary to format a module for later loading by a hexadecimal loader such as the iSBC 86/12 monitor or.Universal Prom Mapper. The conversion may also be made to put the module in a more readable format that can be displayed or printed. The module to be converted must be in absolute format; the output from LaC 86/88 is in absolute format. Figure 2. 8086/8088 Software Development Cycle 15·9 I-::-::':·" _ _ ~_a_. AFN-01239B SERI ES II 8086/8088 SOFTWARE DEVELOPMENT PACKAGES SPECIFICATIONS Operating Environment Documentation PL/M-86 Prograr(lming Manual (9800466) REQUIRED HARDWARE Intellec® Microcomputer' Development System - Model 800 . - Series II 1515-1/ PL/M-86 Compiler Operator's Mariual .. (9800478) MCS-86 User's Manual (9800722) 64K Bytes of RAM Memory MCS~86 Software Development Utilities .Operating Instructions for 1515-1/ Users (9800639) Dual Diskette Drives - Single or Double-Density MCS-86 Macro Assembly Language Reference Manual (9800640) System Console - CRT or Hardcopy Interactive Device MCS-86 Macro Assembler Operating Instructions for 1515-1/ Users (9800641) OPTIONAL HARDWARE MCS-86 Assembly Language Converter Operating Instructions for 1515-1/ Users (9800642) Universal PROM Programmer ICE-86™ Emulator Universal PROM Programmer User's Manual (9800819A) REQUIRED SOFTWARE Shipping Media ISIS-II Diskette Operating System - ORDERING INFORMATION The PL/M Compiler, Assembler, and Utilities Package is also available in the following development support packages: Series II 8086/8088 Sof~w~re Development Packages: Part No~ MDS-308* Single- and Double-Density Diskettes SP86A-KIT Description Includes ICE-86™ In-Circuit Emulator (MDS-86 ICE) and 8086/8088' Software Development Package (MDS-3t1) Assembler and Utilities Package SP86B-KIT MDS-309* MDS-311* SP86A Support Package (for Intellec® Model 800) PUM compiler and Utilities. Package SP86B Support Package (for Series II) IncludesICE-86™ln-Circuit Emulator (MDS-86-ICE), 8086/8088 Software Development Package (MDS-311), and Series II Expansion Chassis (MDS-201) PUM compiler, Assembler, and Utilities Package All Packages and Kits Require Software Licenses *MDS is an ordering code only and is not used as a.product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences. Corporation. 15-10 AFN'()1239B PL/M 86/88 SOFTWARE PACKAGE • Executes on Series III iAPX 86 Processor for Fastest Compilations • Language Is Upward Compatible from PL/M 80, Assuring MCS-80/8S Design Portability • Supports 16-Bit Signed Integer and 32-Bit Floating Point Arithmetic in Accordance with IEEE Proposed Standard • Easy-To-Learn Block-Structured Language Encourages Program Modularity • Improved Compiler Performance Now Supports More User Symbols and Faster Compilation Speeds • Produces Relocatable Object Code Which Is Linkable to All Other 8086 Object Modules • Code Optimization Assures Efficient Code Generation and Minimum Application Memory Utilization • Built-In Syntax Checker Doubles Performance for Compiling Programs Containing Errors Like its counterpart for MCS-80/85 program development, PL!M 86/88 is an advanced, structured high-level programming language. The PLiM 86/88 compiler was created specifically for performing software development for the Intel 8086 and 8088 Microprocessors. PLiM is a powerful, structured, high-level system implementation language in which program statements can naturally express the program algorithm. This frees the programmer to concentrate on the logic of the program without concern for burdensome details of machine or assembly language programming (such as register allocation, meanings of assembler mnemonics, etc.). The PLiM 86/88 compiler efficiently converts free-form PLiM language statements into equivalent 8088/8086 machine instructions. Substantially fewer PLiM statements are necessary for a given application than if it were programmed at the assembly language or machine code level. The use of PLiM high-level language for system programming, instead of assembly language, results in a high degree of engineering productivity during project development. Tl:1is translates into significant reductions in initial software development and follow-on maintenance costs for the user. NOTE: The Intellec' Microcomputer Development System pictured hero is not included with the PL/M 86/88 Software Package but 'merely depicts a language in its operating environment. 15-11 • a September 1980 PL/M 86/88 SOFTWARE PACKAGE FEATURES Another powerful facility allows the use of BASED variables that map more than one variable to the same memory location. This is especially useful for passing parameters, relative and absolute addressing, and memory allocation. Major features of the Intel PL/M 86/88 compiler and programming language include: Block Structure Two Data Structuring Facilities PL/M source code is developed in a series of modules, procedures, and blocks. Encouraging program modularity in this manner makes programs more readable, and easier to. maintain and debug. The language becomes more flexible, by clearly defining the scope of user variables (local to a private procedure, global to a public procedure, for example). In addition to the five data types and based variables, PL/M supports two data structuring facilities. These add flexibility to the referencing of data stored in large groups. . - Array: Indexed list of same type data elell1ents - Structure: Named collection of same or different type data elements· - Combinations of Each: Arrays of structures or structu res of arrays The use of procedures to break down a large problem is paramount to productive software development. The PL/M 86/88 implementation of a block structure allows the use of REENTRANT (recursive) procedures, which are especially useful in system design. 8087 Numerics Support PL/M programs that use 32-bit REAL data may be executed 'Using the Numeric Data Processor for improved performance. All floating-point operations supported by PL/M may be executed on the iAPX 86/20 or 88/20 NDP, orthe 8087 Emulator (a software module) provided with the package. Determination of use of the chip or Emulator takes place at linktime, allowing compilations to be run-time independent. Language Compatibility PL/M 86/88 object modules are compatible with objectmodules generated by all other 86/88 translators. This means that PL/M programs may be linked to programs written in any other 86/88 language. Built-In String Handling Facilities Object modules are compatible with ICE-88 and ICE-86 units; DEBUG compiler control provides the In-Circuit Emulators with symbolic debugging capabilities. The PL/M 86/88 language contains built-in functions for string manipulation. These byte and word functions perform the following operations on character strings: MOVE, COMPARE, TRANSLATE, SEARCH, SKIP, and SET. PL/M 86/88 Language is upward-compatible with PL/M 80, so that application programs may be easily ported to run on the iAPX 86 or 88. Interrupt Handling Supports Five Data Types PL/M has the facility for generating interrupts to the iAPX 86 or 88 via software. A procedure may be defined with the INTERRUPT attribute, and the compiler will automatically initialize an interrupt vector at the appropriate memory location. The compiler will also generate code to same and restore the processor status, for execution of the user-defined interrupt handler routine. The procedure SET$INTERRUPT, the function retuning an INTERRUPT$PTR, and the PL/M statement CAUSE$INTERRUPT all add flexibility to user programs involving interrupt and handling. PL/M makes use of five data types for various applications. These data types range from one to four bytes, and facilitate various arithmetic, logic, and addressi ng functions: - Byte: 8-bit unsigned number - Word: 16-bit unsigned number - Integer: 16-bit signed number - Real: 32-bit floating point number - Pointer: 16-bit or 32-bit memory address indicator 15-12 '" .. AFN·01661A -----= PL/M 86/88 SOFTWARE PACKAGE Including several that have been mentioned, the PL/M 86/88 com piler offers more than 25 controls that facilitate such features as: - Conditional compilation - Including additional PLiM source files from disk - Intra- and Inter-module cross reference - Corresponding assembly language code in the listing file - Setting overflow conditions for run-time handling Segmentation Control The PL/M 86/88 compiler takes full advantage of program addressing with the SMALL, COMPACT, MEDIUM, and LARGE segmentation controls. Programs with less than 64KB total code space can exploit the most efficient memory addressing schemes, which lowers total memory requirements. Larger programs can exploit the flexibility of extended one-megabyte addressing. Code Optimization The PL/M 86/88 compiler offers four levels of optimization for significantly reducing overall program size. - "Strength reductions" (such as a shift left rather than multiply by 2); and elimination of common sUb-expressions within the same block. - Mach.ine code optimizations; elimination of superfluous branches; re-use of duplicate code; removal of unreadable code. - Byte comparisons (rather than 20-bit address calculations) for pointer variables; optimization of based-variable operations. - Compiler Controls Combination or "folding" of constant expressions; and short-circuit evaluation of Boolean expressions. Error Checking The PL/M 86/88 compiler has a very powerful feature to speed up compilations. If a syntax or program error is detected, the compiler will skip the code generation and optimization passes. This usually yields a 2X performance increase for compilation of programs with errors. A fully detailed set of programming and compilation errors is provided by the compiler. Compiler Performance Performance benchmarks may provide valuable information in estimating compile times for various programs. It is extremely important to understand, however, the effect of varying conditions on compiler performance. Storage media, coding style, program length, and the use of INCLUDE files significantly change the compiler's overall performance. We tested typical PL/M programs of varying lengths. The resu Its are listed in Table 1. Table 1. PL/M Program Compile Times Program Size Compile Time(Sec) Lines/Minute SMALL (71) 20 213 MEDIUM (610) 54 678 LARGE (1710) 128 802 LARGE (1403) 129 653 (with very dense code, plus include file) NOTE:. These programs were run on a Series III with ISIS 4.1 and a hard disk. The lines per minute figures reflect fifteen percent blank lines and comments. . The compiler allows approximately 1000 ten-character user symbols. 15·13 AFN-01661A intJ PL/M 86/88 SOFTWARE PACKAGE M:DD: /' Beginning of module '/ ~ PUBLIC and EXTERNAL attributes promote SORTPROC: PROCEDUREtpTR, COUNT, RECSIZE, KEYINDEX)~; " I program modularity,' ' ' DECLARE PTR POINTER, (COUNT, RECSIZE, KEYINDEX) INTEGER, /* Parameters: PTR is pointer to first record. COUNT is number of records to be sorted, RECSIZE is number of bytes in each record-max is 128. KEY1NDEX is byte position within each record of a BYTE scalar to be used as sort key, '/ DECLARE RECORD BASED PTR (1) BYTE, CURRENT (128) BYTE, (I, JIINTEGER: SORT: FIND: "Based" Variables allow manipulation of,external data by passing the base of the data structure (a pointer), This minimizes tt1e STACK space' used for parame~er passing, and the execution time to perform many STACK operations. , DO J= 1 TO COUNT-1: CALL MOVB(@RECORD(J'RECSIZE),,-,,,.:::..:.:..:.:..::;:c:.;-<.:.,' I=J: DO WHILE I ',0 AND RECORD((I-1)'RECSIZE+KEYINDEXI 'CURRENT(KEYINDEX): CALL MOVB(@RECORD((I-,1),RECSIZE), @RECORD(I'RECSIZE), RECSIZE): 1=1 .. 1: END FIND: The "AT" operator returns the address of a . variable, instead of its contents. This is very useful in passing pOinters for based variabJes. . One ofseve'ral PUM built-in procedures for string manipulation", END M: Figure 1. Sample PUM 86/88 Program BENEFITS because less programming resources are required for a given programmed function. PL/M 86/88 is designed to be an efficient, costeffective solution to the special requirements of iAPX 86 or 88 Microsystem Software Development, as illustrated by the following benefits of PL/M use: Increased Reliability ,PL/M 86/88 is designed to aid in the development of reliable software (PL/M 86/88 programs are simple statements of the program algorithm), This substantially reduces the risk of costly correction of errors in systems that have already reached full production status, as the more simply stated the program is. the more likely it is to perform its intended function. Low Learning Effort PL/M 86/88 is easy to learn and to use, even for the novice programmer. Earlier Project Completion Critical projects are completed much earlier than otherwise possible because PL/M 86/88, a structured high-level language, increases programmer productivity. Easier Enhancements and Maintenance Progranis written in PL/M tend to be self-do,cumenting, thus easier to read and understand, This means it is easier to enhance and maintain PL/M programs as the system capabilities expand and future products are developed. Lower Development Cost Increases in programmer productivity translate immediately into lower software development costs 15-14 "" - AFN-01661A PL/M 86/88 SOFTWARE PACKAGE REQUIRED SOFTWARE: ISIS-II Diskette Operating System, V4.1 or later Series III Operating System SPECIFICATIONS Operating Environment REQUIRED HARDWARE: Intellec® Microcomputer Development System - Series III or equivalent Dual Diskette Drives - Single- or Double-Density System Console. - CRT or Hardcopy Interactive Device Documentation Package PL/M-86 User's Guide for 8086-based Development Systems (121636) OPTIONAL HARDWARE: Universal PROM Programmer Line Printer ICE-86™ ORDERING INFORMATION Part Number Description MDS-313* PL/M 86/88 Software Package Requires Software License *MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences ·Corporation. 15-15 AFN-01661A PASCAL 86/88 SOFTWARE PACKAGE • Resident on iAPX 86 Based I ntellec® Series III Microcomputer Development System for Optimal Performance • Object Compatible and Linkable with PL/M 86/88, ASM 86/88 and FORTRAN 86/88 • Supports iAPX86/20, 88/20 N.umeric Data Processors • Strict Implementation of ISO Standard Pascal • Useful Extensions Essential for Microcomputer Applications • ICE™ Symbolic Debugging Fully Supported • Implements REALMATH for Consistent and Reliable Results • Separate Compilation with TypeChecking Enforced Between Pascal Modules • Compiler Option to Support Full RunTime Range-Checking PASCAL 86/88 conforms to and implements the ISO Draft Proposed Pascal standard. The lariguage is enhanced to support microcomputer applications with special features, such as separate compilation, interrupt handling and direct port I/O. To assist the development of portable software, the compiler can be directed to flag all non-standard features. The PASCAL 86/88 compiler runs on the iAPX 86 Resident Intellec® Series III Microcomputer Development System. A well-defined I/O interface is provided for run-time support. This allows a user-written operating system to support application programs as an alternate to the development system environment. Program modules compiled under PASCAL 86/88 are compatible and linkable with modules written in PUM 86/88, ASM 86/88 or FORTRAN 86/88. With a complete family of compatible programming languages for the iAPX 86,88 one can implement each module in the language most appropriate to the task at hand. PASCAL 86/88 object modules contain symbol and type information for program debugging using ICE-86™ emulator. For final production version, the compiler can remove this extra information and code. Note: The Inlellecoo microcomputer development system pictured here is not included with the Pascal 86/88 Software Package but merely depicts the language in Its operating environment. 15·16 12168().001 Rev, A inter PASCAL 86/88 FEATURES Supports numerous compiler options to control the compilation process, to INCLUDE files, flag nonstandard Pascal statements and others to control program listings and object modules. Includes all the language features of Jensen & Wirth Pascal as defined in the ISO Draft Proposed Pascal· Standard. Utilizes the IEEE standard for Floating-Point Arithmetic (the Intel REALMATH standard) for arithmetic operations. Supports required extensions for microcomputer applications. -Interrupt handling -Direct port I/O Well-defined and documented run-time operating system interfaces allow the user to execute the applications under user-designed operating systems. Separate compilation extensions allow: -Modular decomposition of large programs -Linkage with other Pascal modules as well as PUM 86/88, ASM 86/88 and FORTRAN 86/88. -Enforcement of type-checking at LINK-time Provides run-time support for co-processors. All real-type arithmetic is performed on the 86/20 numeric data processor unit or software emulator. Run-time library routines, common between Pascal and other Intel languages (such as FORTRAN), permit efficient and consistently accurate results. BENEFITS Provides a standard Pascal for iAPX 86, 88 based applications. -Pascal has gained wide acceptance as the portable application language for microcomputer applications -It is being taught in many colleges and universities around the world -It is easy to learn, originally intended as a vehicle for teaching computer programming -Improves maintainability: Type mechanism is both strictly enforced and user extendable Extended relocation and linkage support allows the user to link Pascal program modules with routines written in other languages for certain parts of the program. For example, real-time or hardware dependent routines written in ASM 86/88 or PUM 86/88 can be linked to Pascal routines, further extending the user's ability to write structured and modular programs. -Few machine specific language constructs Strict implementation of the proposed ISO standard for Pascal aids portability of application programs. A compile time option checks conformance to the standard making it easy to write conforming programs. PASCAL 86/88 extensions via predefined procedures for interrupt handling and direct port I/O make it possible to code an entire application in Pascal without compromising portability. Standard Intel REALMATH is easy to use and provides reliable results, consistent with other Intel languages and other implementations of the IEEE proposed Floating-Point standard. PASCAL 86/88 programs "talk" to the resident operating system using Intel's standard interface for translated programs. This allows users to replace the development operating system by their own operating systems in the final application. PASCAL 86/88 takes full advantage of iAPX 86, 88 high level language architecture to generate efficient machine code without using timeconsuming optimization algorithms. Compiler options can be used to control the program listings and object modules. While debugging, the user may generate additional information such as the symbol record information required and useful for debugging using ICE emulation. After debugging, the production version may be streamlined by removing this additional information. 15-17 AFN-01652A PASCAL 86/88 SPECIFICATIONS Operating Environment REQUIRED HARDWARE Intellec® Series III Microcomputer Development System -System Console -Double Density Dual Diskette Drive OR Hard Disk REQUIRED SOFTWARE ISIS-II Diskette Operating System V4.1 or later Documentation Package PASCAL 86 User's Guide (121539-001) Shipping Media Flexible Diskettes -Single and Double Density ORDERING INFORMATION Part Number Description MDS*-314 PASCAL 86/88 Software Package Requires software license . • MDS is an ordering code only and is·not used as·a product name or trademark. MDS" is a registered trademark of Mohawk DataScience. 15-18 AFN·01652A 8087 . SOFTWARE SUPPORT PACKAGE • Program Generation for the 8087 Numeric Data Processor on. the Intellec® Microcomputer Development System • 8087 Emulator Duplicates Each 8087 Floating-Point Instruction in Software, for Evaluation of Prototyping, or for Use in an End Product . • Consists of: 8086/8087/8088 Macro . Assembler, 808TSofhvare Emulator • Macro Assembler and 8087 Emulator are Fully Compatible with Other 8086/8088 Development Software • Implementation of the IEEE Proposed Floating-Point Standard (the Intel® Realmath Standard) • Macro Assembler Generates Code for 8087 Processor or Emulator, While Also Supporting the 8086/8088 Instruction Set . The 8087 Software Support Package is an optional extention of Intel's 8086/8088 Software Development Package that runs under ISIS-lion an Intellec or Series II Microcomputer Development System. The 8087 Software Support Package consists of the 8086/8087/8088 Macro Assembler, and. the Full 8087 Emulator. The assenibler is a functional superset of the 8086/8088 Macro Assembler, and includes instructions for over sixty new floating-point operations, plus new data types supported by the 8087. The 8087 Emulator is an 8086/8088 object module that simuiates the environment of the 8087, and executes each floating-point operation using software algorithms. This emulator functionally duplicates the operation of the 8087 Numeric Data Processor. Also included in this package are interface libraries to link with 8086/8087/8088 object modules, which are used for specifying whether the 8087 Processor or the 8087 Emulator is to be used. This enables the run-time . environment to be invisible to the programmer at assembly time: 15-19 121653~OOl Rev. A 8087 SOFTWARE SUPPORT PACKAGE FUNCTIONAL DESCRIPTION 8086/8087/8088 Macro Assembler The 8086/8087/8088 Macro Assembler translates symbolic macro assembly language instructions into appropriate machine instructions. It is an extended version of the 8086/8088 Macro Assembler, and therefore supports all of the same features and functions, such as limited type checking, conditional assembly, data structures, macros, etc. The extensions are the new instructions and data types to support floating-point operations. Realmath floating-point instructions (see Table 1) generate code capable of being converted to either 8087 instructions or interrupts for the 8087 Emulator. The Processor/Emulator selection is ,made via ·interface libraries at LINK-time. In addition to the new floating-point instructions, the macro assembler also introduces two new 8087 data types: aWORD (8 bytes) and TBYTE (ten bytes). These support the highest precision of data processed by the 8087. Full 8087 Emulator The Full 8087 Emulator is a 16-kilobyte object module that is linked to the application program for floating-point operations. Its functionality is identical to the 8087 chip, and is ideal for prototyping and debugging floating-point applicati,ons.· The Emulator is an alternative to the use of the 8087 chip, although thelatter.executes floating-point applications up to.1 00 times faster than an 8086 with the 8087 Emulator. Furthermore, since the 8087 is a "co-processor," use of the chip will allow many operations to be performed in parallel with the 8086. Table 1. 8087 Instructions Processor Control Instructions Arithmetic Instructions FADD FADDP FIADD FINIT/FNINIT FDISI/FNDISI Addition Add real Add real and pop Integer add FENl/FtilENI Subtraction FSUB FSUBP FISUB FSUBR FSUBRP FISUBR Subtract real Subtract real and pop Integer subtract Subtract real reversed Subtract real reversed and pop Integer subtract reversed Multlpilcatlon FMUL FMULP FIMUL Multiply real Multiply real and pop Integer multiply FDIV FDIVP FIDIV FDIVR FDIVRP FIDIVR Divide real Divide real and pop Integer divide Divide real reversed Divide real rev.ersed and pop Integer divide reversed FABS FCHS Load control word FSTCW/FNSTCW Store control word FSTSW/FNSTSW Store status weird FCLEX/FNCLEX FSTENV/FNSTENV Clear exceptions FLDENV Load environment FSAVE/FNSAVE Save state Store environment FRSTOR Restore state FINCSTP Increment stack painter Decrement stack pointer FFREE Free reg i ste r FNOP No operation FWAIT CPU wait Comparison Instructions Other Operations FSQRT FSCALE FPREM FRNDINT FXTRACT Disable interrupts Enable interrupts' FLDCW FDECSTP ,Division Initialize processor Square root Scale Partial remainder Round to integer Extract exponent and significand Absolute value Change sign FCOM Compare real FCOMP Compare real and pop Compare real and pop twice Integer compare FCOMPP FICOM 15·20 =- FICOMP Integer compare and pop FTST FXAM Test Examine AFN·OI574A 8087 SOFTWARE SUPPORT PACKAGE Table 1. 8087 Instructions (cont'd) Transcendental Instructions FPTAN FPATAN F2XM1 FYL2X FYL2XP1 Data Transfer Instructions Partial tangent Partial arctangent 2'-1 y. 10g,X y. log,(X+1) FLD FST FSTP FXCH FILD FIST FISTP Constant Instructions FLDZ FLD1 FLDPI FLDL2T FLDL2E FLDLG2 FLDLN2 Load. +0.0 Load +1.0 Load 1]' Load log,10 FBLD FBSTP Real Transfers Load real Store real Store real and pop Exchange registers Integer Transfers Integer load Integer store Integer store and pop Packed Decimal Transfers Packed decimal (BCD) load Packed decimal (BCD) store and pop Load log,e Load log,,2 Load log,2 SPECIFICATIONS REQUIRED SOFTWARE ISIS-II Diskette Operating System -Single or Double Density Operating Environment 8086/8088 Software Development Package REQUIRED HARDWARE Intellec® Microcomputer Development System -'-Model 800 -Series II (Models 220, 225 or equivalent) Documentation Package BOB6/BOB7/BOBB Macro Assembly Language Reference Manual for BOBO/BOB5-Based Development Systems (121623-001) 64K Bytes of RAM Memory Minimum One Diskette Drive -Single or Double' Density BOB6/BOB7/BOBB Macro Assembler Operating Instructions for BOBO/BOBS-Based Development Systems (121624-001) System Console -CRT or Hardcopyl.nteractive Device The BOB6 Family Users Manual Supplement for the BOB7 Numeric Data Processor (121586-001) OPTIONAL HARDWARE Universal PROM Programmer' Line Printer' . Shipping Media 'Recommended 1 Single and 1 Double Density Diskette ORDERING INFORMATION Part Number Description MDS'-38? 808? Software Support Package Requires Software License 'MDS is an ordering code only and is nol used as a product name or trademark. MDS'" is a registered trademark of Mohawk Data Sciences Corporation. 15·21 AFN·01574A inter 8089 lOP SOFTWARE SUPPORT PACKAGE • Program Generation for the 8089 I/O Processor on the Intellec® Microcomputer Development System • Supports 8089-Based Addressing Modes with a Structure Facility that Enables Easy Access to Based Data • Contains 8089 Macro Assembler, plus Relocation and Linkage Utilities • Powerful Macro Capabilities • Relocatable Object Module Compatible with All iAPX 86 and iAPX 88 Object Modules • Provides Timing Information in Assembly Listing • Fully Detailed Setof Error Messages • Fully Supports Symbolic Debugging with the RBF-89 Software Debugger The lOP Software Support Package extends Intellec Microcomputer Development System support to the 8089 I/O Processor. The macro assembler translates symbolic 8089 macro assembly language instructions into relocatable machine code. The relocation and linkage utilities provide compatibility with iAPX 86, iAPX 88, and 8089 modules, and make structured, modular programming easier. The macro assembler also provides symbolic debugging capability when used with the RBF-89 software debugger. 8089 program modularity is supported with inter-segment jumps and calls. The macro assembler also provides instruction cycle counts inthe listing file, for giving the programmer executiontiming information. The programs in the 8089 Software Support Package run on any Intellec Series II or Model 800 with 64K bytes of memory. 15-22 9800999-02 Rov. B 8089 lOP SOFTWARE SUPPORT PACKAGE FUNCTIONAL DESCRIPTION so that any changes to that sequence need to be made in only one place in the program. Common code sequences that differ only slightly can also be referred to with a macro call, and the differences can be substituted with macro parameters. The lOP Software S'upport Package contains: ASM89 -The 8089 Macro Assembler. LlNK86 - Resolves control transfer references between 8089 object modules, and data references in 8086, 8088, and 8089 modulras. LOC86 -Assigns absolute memory addresses to 8089 object modules. OH86 -Converts absolute object modules to hexadecimal format. UPM - Thfl Universal PROM Mapper, which supports PROM programming in all iAPX 86./11 and iAPX 88/11 applications. ASM89 translates symbolic 8089 macro assembly language i'nstructions into the appropriate machine codes. Thl3 ability to refer to both program and data addresses with symbolic names makes it easier to develop find modify programs, and avoids the errors of hand 'translation. ASM89 provides symbolic debugging information in the object file. The RBF-89 debugger makes use of this information, so the programmer can symbolically debug 8089 programs. ASM89 also provides cycle counts for each instruction in the assembly listing file (see Table 1). These cycle counts help the programmer determine how long a particular routine or code sequence will take to execute on the 8089. ASM89 provides relocatable object module compatibility with the 8086 and 8088 microprocessors. This object module compatibility, along with the 8086/8088 relocation and linkage utilities, facilitates the designing of iAPX 86/11 and iAPX 88/11 systems. The powerful macro facility allows frequently used code sl3quences to be referred to by a single name, ASM89 fully supports the based addressing modes of the 8089. A structure facility allows the user to define a template that enables accessing of based data symbolically. SPECIFICATIONS Documentation Package 8089 Macro Assembler User's Guide (9800938) Op'erating Environment 8089 Macro Assembler Pocket Reference (9800936) RE.QUIRED HARDWARE Intellec® Microcomputer Development System -·ModeI800 --Series II (Models 220, 225 or equivalent) 64K Bytes of RAM Memory MCS-86 Software Development Utilities Operating Instructions for ISIS-I/ Users (9800639) Universal PROM Programmer User's Manual (9800819) Minimum One Diskette Drive -Single or Double' Density System Console -CRT or Hardcopy Interactive Device Shipping Media -Single and Double Density Diskettes OPTIONAL HARDWARE Universal PROM Programmer' Line Printer' ORDERING INFORMATION REQUIRED SOFTWARE ISIS-II Diskette Operating System -Single or Double Density MDS'-312 Part Number Description 808910P Software Support Package Requires Software License "MDS is an ordering code only and is not used as a product name or trademark. MDS'" is a registered trademark of Mohawk Data Sciences Corporation. "Recommended 15-23 AFN·OOB40B inter 8089 lOP SOFTWARE SUPPORT PACKAGE: Table 1. Sample Program Listing 8SH "ACRO ASSEI!8J.:ER ISIS-II eU9 !'IACRO IISSEI1BL£:f: 10;105 IlSSEPIBlY OF "ODULE TASK OBJECT !tIJOltLE PLACED PI :f'1 TASK OBJ ~SSE"BLER IHIIOKED BV! us,,"':! :t'ltosk a.g, geon I'Ia.c:o de-bioi; pagewidth(132) pr-;nt. BUI 11118 HUBBall BBI' 3138 aBD2 aUA BBlI '118 IUBlIBI 6182 8812 8816 1.,8 BBeD 1138 8818 2138 Bl1II 413C aBle 484a F3 " " <7 77 '17 ... '" 173 1138 88CB 191. 812.3 1138 BiC8 8827 l\ 38 BIIZ 5t18 BBlBBlBB 6882 '" Baa Load r'gl.tel' CA WI th oddre.s' of 80U burrer "0"'; gb.bufrel'iB889 gc.y bcdgc] 1 Ito..,e burrel' oddl'e •• Into CD , LOGd pOinter to count Into CC , Ito..,. byh count into Be 39 l~op8BI Ito..,b 411 Inc 41 %Plocro.2( gb. gc) 42 43 gb 44 dec 4S ge , J nz 47 gc.%LOOP 49 LOOPBB [gb]d go] go , , In' 58 TWO; 51 52 :;;",ocro 1 go. dototlp,or-t~9251 go. cOI'I"Gndllp0l'tI!8251 33' 53 gb.burfer-I!.8889 'ge,y bcdgcl 71 . 20' " 23. .,., .,., 4' 386. leaA FD BUt Bace BIll! 21138 aBle 4B3C aBlE 4848 F2 '"'77 B'B4! 2848 3H BBU .. '37 '" '2 .,., '2 Ipdi "o..,b 37 3S ., .. . I " ., ". .,., ,.. 34 %"ocro 35 .,.,., .,., ., 28' '", .., .,. '" ." ., '" ,." .,., 22i' 2(.2 aa:J6 lII:!l go.buff.rIl8B86 " ,., '" '24 '" aUF BUI Ipd i 32,OHEI 33 "" Itove byte fro" a8a6 to al89 bur,rer Incre"ent pOinter Into 8886 burf',r %PARAM.l 1 Incl'e"en\; poi nte-r Into %PARAM.2 J DecrePlent byte count %PARAM.2 J ",j loop bock; I' byte count) II .1 ,lood CA II I th .oddl'u, of 92:51 DP lood ce II I th address of 82'1 ep I !'love buffel' ,Qddresii into C8 Load po Int.r to count Into CC !'Io..,. bvte count Into 8C 'IQopBI= jnbt [g!;"l.B.tQopU loop until 82'1 trons" It ready S8 I'IQllb [go],[gbl "essog' Into buff,r'59 :-;~Qcr-D.2( gb, gc:) 68 ~PARAPI.l " gb ) Incr-el'lent po; nter Into source 62 dec :':PARAPI_2 '~91C I Decrel'lent byte count 64 jn;! :':PARAI'I_2 65 gc.:-:LOLIP J Loop bock if byte count> 8 H LOOP!!! "" ,,0..,. 69 tASK 7B hit ends EHD ASSf"IBL,' COMPLETE. NO ERRORS FOUUv 15·24 = -. AFN·OOS40B --=- SP86A/SP868 SUPPORT PACKAGE • Full Development Support for 8086 Microprocessor Des';igns, Including: • Programs Written inPL/M and Assembly Language can be Linked Together and Relocated • 8086/8088 Software Development Package for High-Level Language or Assembly Language Programming • ICE-86™ In-Circuit Emulation • Programs Written in 8080/8085 Assembly Language can be Converted to 8086/8088 Assembly Language • Expansion Chassis for Development Support on Intellec® Ser.:es " Microcomputer Development System • ICE-86™ Emulation Provides Fully Symbolic Debugging for Program Labels or Variables The SP86A and SP86B Support Pac.l\ages combine the software and hardware components required for 8086 development using an Intellec Microcomputer Development System. The basic components are an 8086 Software Development Package and ICE-86 in-circuit emulator. The SP86B version of the kit includes an expansion chassis to provide additional board slots and power for the Intellec Series II. 15-25 SP86A/SP868 SUPPORT PACKAGE SP86A AND SP868 SUPPORT PACKAGE SPECI FICATIONS MCS-86 Assembly (9800640) Operating Environment MCS-86 Assembler Operating Instructions for ISIS-II Users (9800641) Required Hardware Language Reference Manual MCS-86 Assembly Language Converter Operating Instructions for ISIS-Ii Users (9800642) DS003 System Package or equivalent. MCS-86 Absolute Object File Formats (9800821) Environmental Characteristics Universal PROM Programmer User's Manual (9800819A) ICE-86 Operating Instructions (9800714A) Operating Temperature: O·C to 40·C Operating Humidity: Up to 95% relative humidity with- out condensation_ Electrical Characteris;tics DC Power Supply Expansion Chassis Dimensions Width - 17_37 in. (44.12 cm) Height - 4_81 in. (11.22 cm) Depth - 19.13 in. (48.59 cm) Voltage Reference Manuals (supplied) Expansion Chass'is Amps Suppl.ied ICE-86 In·Circuit Emulator Amps Required Maximum Typical +5+5% -4% ;24 15 11 PUM-86 Programming Manual (9800466) +12±5% 2.0 0.12 0.08 ISIS-II PLlM·86 Compiler Operator's Manual (9800478) MCSTM-86 User's Manual (9800694) -12±5% 0.3 none none -10±5% 1.0 0.015 0.012 MCS-86 Software Development Utilities Operating Instructions for ISIS-II Users (9800639) AC Requirements - ORDERING INFORMATION Part Number Description SP86A-KIT SP86A Support Package for Intellec Model 800 Includes ICE·86 In-Circuit Emulator (MDS-86ICE) and 808618088 Software Development Package (MDS-311). SP868-KIT SP868 Support Package for Intellec Series II Includes ICE-86 In-Circuit Emulator (MDS·86ICE), 808618088 Software Development Package (MDS:311), and Series II Expansion Chassis (MDS-201) .. 15-26 = ~ 50- 60 Hz, 115/230 VAC SP 88 SUPPORT PACKAGE • Development Support for iAPX 88 Microprocessor Designs • Utility Program for Conversion of 8080/8085 Source Program into 8088 Source Program • iAPX 88 Macro Assembler for 8088 Assembly Language Programming • ICE·88™-iAPX 88 CPU In·Circuit Emulator for Real·Time Emulation and Full Symbolic Debugging • Object Code Converter Which Translates 8088 Absolute Module to Symbolic H EX Format for Easler Debugging • Link and Locate Utilities Program for Combination of Separately Assembled 8088 Programs into a Relocatable Module • Library Manager Program for Creation and Maintenance of Object Files The SP 88 support package provides both iAPX 88 assembler and ICE·88 emulation which may be combined with the Series II Intellec Microcomputer Development System. The iAPX 88 assembler outputs relocatable and linkable object modules. iAPX 88 programs can be developed and debugged in 'small modules. These modules can be easily linked with other iAPX 88 assembler or PLIM 88 object modules or library routines to form a complete application system. The assembler translates symbolic assembly language instructions into the appropriate machine code, which can be loaded to an ICE·88 in·circuit emulator module for software execution and symbolic debugging. 15·27 AFN 01667A SP 88 The ICE-88 emulator allows hardware and software development to proceed concurrently and interactively. This is more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-88 module, prototype hardware can. be added to. the system it is designed. Software and hardware testing occurs while the product is being developed. The ICE-88 module provides in-circuit emulation for the 8088 microprocessor. It includes three circuit boards which reside in Intellec Microcomputer Development Systems. A cable and buffer box connect the Intellec System to the user system in replace of the user's 8088. Powerful debug functions are thus extended into the user system. Using the ICE-88 module, the desginer can execute software on prototype hardware in real-time or single-step mode. Breakpoints allow the user to halt emulation on user-specified conditions. Trace capability gives 1023 frames of the 8088 programexectuion status prior to the halt. User access to the prototype system software is facilitated with the symbolic debugging feature which alows reference to the source program variables and labels. ISIS·II TEXT EDITOR In addition, the SP 88 support package contains a utility program to translate 8080/8085 assembly or PLiM 80 language source code to 8088 assembly language source code. A comprehensive manual, "MCS-86 Assembly Language Converter Operating. Instructions for ISIS-II Users" (9800642), covers the entire conversion process. Detailed methodology of the conversion process is fully described therein. PLiM 88 SOURCE RELOCATABLE OBJECT MODULE USER SYSTEM RELOCATABLE OBJECT MODULE ICE·aa Figure 1. iAPX 88 Microprocessor Development Cycle 15·28 =- AFN 01667A --.-~--..:::.=:::,. SP 88 SPECIFICATIONS Electrical Characteristics OPERATING ENVIRONMENT DC Power Vcc=+5V+5%-1% Icc = 15A maximum; 11 A typical Voo= +12V±5% 100= 120mA maximum; 80mA typical Ves= -10'v±5%or -12V±5% optional Iss=25mA maximum; 12mA typical Required Hardware Intellec microcomputer development system Models 800, 225, 235, 245 with: 1. Three adjacent slots for the ICE·88 module. (Series 11·220, ·230, ·240 require Model 201 Expansion Chassis.) 2. 64K bytes of Intellec memory. If user prototype program memory is desired, additional memory above the basic 64K is required. System Console Intellec diskette operating system with Dual Diskette Drives - single or double density ICE·88 module Environmental Characteristics Operating Temperature: O· to 40·C Operating Humidity: Up to 95% relative humidity without condensation DOCUMENTATION SUPPLIED PLIM 86 Programming Manual (9800466) Required Software IS/S·II PLIM 86 Compiler Operator's Manual (9800478) System monitor ISIS·II, version 3.4 or subsequent ICE·88 software MCS·86 Software Development Utilities Instructions for IS/S·II Users (9800639) Equipment Supplied MCS·86 Assembly Language Reference Manual (9800640) Printed circuit boards (3) Interface cable and emulation buffer module Operator's Manual ICE·88 software, diskette·based ASM 88 software, diskette·based MCS·86 Assembler Operating Instructions for IS/S·II Users (9800641) MCSTM·86 User's Manual (9800694) MCS·86 Assembly Language Converter Instructions for IS/S·II Users (9800642) Operating Operating MCS·86 Absolute Object File Formats (9800821) ICE-88 Emulator Operating Instructions (9800714A) Emulation Clock User system clock up to 5MHz or 2 MHz ICE·88 emulator internal clock in stand·alone mode Physical Characteristics Printed circuit boards: Width: Height: Depth: Packaged Weight: 12.00 in. (30.48 cm) 6.75 in. (17.15 cm) 0.50 in. (1.27 cm) 9.00 lb. (4.10 kg) ORDERING INFORMATION Part Number: SP 88·KIT Description: SP 88 Support Package includes ICE·88 In·Circuit Emulator (MDS·88* ICE) and 8088 Software Development Package (MDS·308*). REQUIRES SOFTWARE LICENSE. *"MDS" is an ordering code only, and is not used as a product name or trademark. MOS·' is a registered trademark of Mohawk Data Sciences Corp. 15·29 AFN 01667A ICE-86™ 8086 IN-CIRCUIT EMULATOR • Full Symbolic Debugging • 2K Bytes. of High Speed ICE-86™ Mapped Memory • Breakpoints to Halt Emulation on a Wide Variety of Conditions· •. Software Debugging with or without User System • Comprehensive Trace of Program Execution, Both Conditional and Unconditional • Handles Full 1 Megabyte Addressability of 8086 • Hardware In-Circuit Emulation • Disassembly of Trace or Memory from Object Code into Assembler Mnemonics • Compound Commands • Command Macros The ICE-86 module provides In-Circuit Emulation for the 8086 microprocessor and the iSBC 86/12 Single Board Computer. It includes three circuit boards which reside in Intellec® Microcomputer Development Systems. A cable and buffer box connect the Intellec system to the user system by replacing the user's 8086. Powerfullntellec debug functions are thus extended into the user system. Using the ICE-86 module, the designer can execute prototype software in continuous or single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints allow the user to stop emulation on user-specified conditions, and the trace capabilitygives a detailed history of the program execution prior to the break. All user access to the prototype system software may be done symbolically by referring to the source program variables and labels. 15-30 ICE-86™ IN-CIRCUIT EMULATOR SYMBOLIC DEBUGGING INTEGRATED HARDWARE/SOFTWARE DEVELOPMENT Symbols and PLiM statement numbers may be substituted for numeric values in any of the ICE-86 com· mands. This allows the user to make symbolic refer· ences to 1/0 ports, memory addresses, and data in the user program. Thus the user need not remember the ad· dresses of variables or program subroutines. The ICE-86 emulator allows hardware and software development to proceed interactively. This is more ef· fective than the traditional method of independent hard· ware and software development followed by system in· tegration. With the ICE·86 module, prototype hardware can be added to the system as it is designed. Software and hardware testing occurs while the product is being developed. Symbols can be used to reference variables, proce· dures, program labels, and source statements. A vari· able can be displayed or changed by referring to it by name rather than by its absolute location in memory. Using symbols for statement labels, program labels, and procedure names simplifies both tracing and breakpoint setting. Disassembly of a section of code from either trace or program memory into its assembly mnemonics is readily accomplished. Conceptually, the ICE-86 emulator assists three stages of development: 1. It can be operated without being connected to the user's system, so ICE-86 debugging capabilities can be used to facilitate program development before any of the user's hardware is available. 2. Integration of software and hardware can begin when any functional element of the user system hardware is connected to the 8086 socket. Through ICE-86 mapping capabilities, Intellec memory, ICE memory, or diskette memory can be substituted for missing prototype memory. Time·critical program modules are debugged before hardware implementation by us· ing the 2K·bytes of high·speed ICE·resident memory. As each section of the user's hardware is completed, it is added to the prototype. Thus each section of the hardware and software is "system" tested as it becomes available. 3. When the user's prototype is complete, it is tested with the final version of the user system software. The ICE-86 module is then used for real time emula· tion of the 8086 to debug the system as a completed unit. Thus the ICE-86 module provides the user with the abil· ity to debug a prototype or production system at any stage in its development without introducing extraneous hardware or software test tools. Furthermore, each symbol may have associated with it one of the data types BYTE, WORD, INTEGER, SINTEGER (for short, 8-bit integer) or POINTER. Thus the user need not remember the type of a source pro· gram variable when examining or modifying it. For example, the command "!VAR" displays the value in memory of variable VAR in a format appropriate to its type, while the command "!VAR = !VAR + 1" increments the value of the variable. The user symbol table generated along with the object file during a PLlM-86 compilation or an ASM-86 assembly is loaded into memory along with the user pro· gram which is to be emulated. The user may add to this symbol table any additional symbolic values for memory addresses, constants, or variables that are found useful during system debugging. The ICE-86 module provides access through symbolic definition to all of the 8086 registers and flags. The READY, NMI, TEST, HOLD, RESET, INTR, and MN/MX pins of the 8086 can also be read. Symbolic references to key ICE-86 emulation information are also provided. PLUG INTO USER 8086 SOCKET r------------r- _ _ _ _ .., I I I I I I I I I IN~~~\EC I I I I I I I I L _____ ~ I I I I L ____ -l I ________________________ Figure 1. ICE-86 T" Emulator Block Diagram 15-31 I I ~ I -~ T·CABLE ~ I I I I I ------------------------ ~ I ICE-86™ IN-CIRCUIT EMULATOR A typical ICE·S6 development configuration. It is based on a Model 230 Development System, which also includes a Double Density Diskette Operating System and a Model 201 Expansion Chassis (which holds the ICE·S6 emulator). The ICE·S6 module is shown connected to a user prototype system, in this case an SDK·S6. MACROS AND COMPOUND COMMANDS Description Command The ICE·86 module provides a programmable diagnostic facility which allows the user to tailor its operation us· ing macro commands and compound commands. GO A macro is a set of ICE·86 commands which is given a single name. Thus, a sequence of commands which is executed frequently may be invoked simply by typing in a single command. The user first defines the macro by entering the entire sequence of commands which he wants to execute. He then names the macro and store~ it for future use. He executes the macro by typing its name and passing up to ten parameters to the com· mands in the macro. Macros may be saved on a disk file foruse in subsequent debugging sessions. Compound commands provide conditional execution of commands(IF), and execution of commands until a con· dition is met or until they have been executed a specified number of times (COUNT, REPEAT). Compound commands and macros may be nested any number of times. MEMORY MAPPING Memory for the user system can be resident in the user system or "borrowed" from the Intellec System through ICE·86's mapping capability. The ICE·86 emulator allows the memory which is addressed by the 8086 to be mapped in 1K-byte blocks to: 1. Physical memory in the user's system, 2. Either of two 1K-byte blocks of ICE-86 high speed memory, Initializes emulation and allows the user to specify the starting point and breakpoints. Example: GO .FROM .START TILL .DELAY EXECUTED where START and DELAY are statement labels. STEP Allows the user to through the program. Single-step Table 1. Summary of ICE-86™ Emulation Commands OPERATION MODES The ICE-B6 software is a RAM-based program that provides the user with easy-to·use commands for initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters. ICE-B6 commands are configured with a broad range of modifiers which provide the user with maximum flexibility in describing the operation to be performed. Emulation Emulation commands to the ICE-B6 emulator control the process of setting up, running and halting an emulation of the user's 80B6. Breakpoints and tracepoints enable ICE-B6 to halt emulation and provide a detailed trace of execution in any part of the user's program. A summary of the emulation commands is shown in Table 1. 3. Intellec memory, 4. A random·access diskette file. The user can also designate a block of memory as nonexistent. The ICE·86 module issues an error message when any such "guarded" memory is addressed by the user program. 15·32 Breakpoints - The ICE-86 module has two breakpoint registers that allow the user to halt emulation when a specified condition is met. The breakpoint registers may be set up for execution or non-execution breaking. An execution breakpoint consists of a single address which causes a break whenever the BOB6 executes from its queue an instruction byte which was obtained from ICE·86™ IN·CIRCUIT EMULATOR the address. A non·execution breakpoint causes an emulation break when a specified condition other than an instruction execution occurs. A non·execution breakpOint condition, using one or both breakpoint registers, may be specified by anyone of or a combination of: Memory/Register Commands Display or change the contents of: • Memory • 8086 Registers • 8086 Status flags • 8086 Input pins' • 8086 110 ports • ICE·86 Pseudo·Reglsters (e.g. emulation timer) 1. A set of address values. Break on a set of address values has three valuable features: a. Break on a single address. Memory Mapping Commands b. The ability to set any number of breakpoints within a limited range (1024 bytes maximum) of memory. Display, declare, set, or reset the fCE·86 memory mapping. Symbol Manipulation Commands c. The ability to break in an unlimited range. Execution is halted on any memory access to an address greater than (or less than) any 20·bit breakpoint address. Display any or all symbols, program modules, and program line 'numbers and their associated values (locations in memory). Set the domain (choose the particular program module) for the line numbers. 2. A particular status of the 8086 bus (one or more of: memory or 1/0 read or write, instruction fetch, halt, or interrupt acknowledge). Define new symbols as they are needed in Remove any statements. 3. A set of data values (features comparable to break on a set of address values, explained in point one). or all symbols, debug~lng. modules, and program Change the value of any symbol: TYPE 4. A segment register (break occurs when the register is used in an effective address calculation). Assign or change the type of any symbol in the symbol table. ASM An external breakpoint match output for user access is provided on the buffer box. This allows synchronization of other test equipment when a break occurs. Disassemble user program memory into ASM·86 Assembler mnemonics. PRINT Tracepoints - The ICE-86 module has two tracepoint registers which establish match conditions to conditionally start and stop trace collection. The trl;lce Information is gathered at least twice per bus cycle, first when the address signals are valid and second when the data signals are valid. If the 8086 execution queue is otherwise active, additional frames of trace are collected. Display the specified portion of the trace memory. LOAD Fetch user symbol.table and object code from the input file. SAVE Send user symbol table and obiect code to the output file. LIST Send a copy of all output (including prompts, input line echos, and error messages) to the chosen output device (e.g. disk, printer) as well as the console. Each trace frame contains the 20 addressldata lines and detailed information on the status of the 8086. The trace memory can store 1,023 frames, or an average of about 300 bus cycles, providing ample data for determining how the 8086 was reacting prior to emulation break. The trace memory contains the last 1,023 frames of trace data collected, even if this spans several separate emulations. The user has the option of displaying each frame of the trace data or displaying by instruction in actual ASM·86 Assembler mnemonics. Unless the user chooses to disable trace, the trace information is always available after an emulation. EVALUATE Display the value of an expression in binary, octal, decimal, hexadecimal, and ASCII. SUFFIX/BASE Establish the default base for numeric values in' input text/output display (binary, octal, decimal, or hexadecimal). CLOCK Select the internal (ICE·86 provided, for stand·alone mode only) or an external (user·provided) system clock. RWTIMEOUT Allows the user to time out READ/WRITE command signals based on the time taken by the 8086 to access Intellec memory or diskette memory. Interrogation and Utility Interrogation and utility commands give the user con· venient access to detailed information about the user program and the state of the 8086 that is useful in debugging hardware and software. Changes can be made in both memory and the 8086 registers, flags, input pins, and I/O ports. Commands are also provided for various utility operations such as loading and saving program files, defining symbols and macros, displaying trace data, setting up the memory map, and returning control to ISIS-II. A summary of the basic interrogation and utility commands is shown in Table 2. ./ 15-33 ENABLEfDlSABLE ROY Enable or disable logical AND of ICE·86 Ready with the user Ready signal for accessing Intellec memory, ICE memory, or diskette memory. Table 2. Summary of Basic ICE-86™ Interrogation and Utility Commands ICE;.86™IN-CIRCUIT EMULATOR DIFFERENCES BETWEEN ICE-86™ EMULATION AND THE 8086 MICROPROCESSOR DC CHARACTERISTICS OF ICE-86™ USER CABLE 1. Output Low Voltages [VodMax)= O.4V] 10L (Min) The ICE-86 module emulates the actual operation of the 8086 microprocessor with the following ,exceptions: The ICE-86 module will not respond to a user system NMI or RESET signal when it is out of emulation. • Trap is ignored in'single step mode and on the first instruction step of an emulation. ADO-AD15 B mA (24 mA @ 0.5V) A16/S3-A19/S7, SHE/S7, RD, ' LOCK, OSO, OS1, SO, S1, S2, WR, M/iB, DT/R, DEN, ALE, . INTA BmA (16 mA @ 0.5V) 7mA HLDA • The MIN/MAX line, which chooses the "minimum" or "maximum" configuration of the 8086, must not change dynamically in the user system. MATCHO OR MATCH1 (on buffer box) • In the "minimum" mode, the user HOLD signal must remain active until HLDA is output by the ICE-86 emulator. 16mA 2. Output High Voltages [V OH (Min) = 2.4V] IOH(Min) • The RO/GT lines in the "maximum" configuration are not supported. The speed of run emulation by the ICE-86 module depends on where the user has mapped his memory. As the user prototype progresses to include memory, emulation becomes real time. ADO-AD15 - 2 mA A16/S3-A19/S7, SHE/S7, RD, LOCK, OSO; OS1, SO, S1, S2, WR, M/iB, DT/A, DEN, ALE, INTA, HLDA -1 mA MATCHO OR MATCH1 (on buffer box) - O.B mA 3. Input Low Voltages [VIL(Max) = O.BV] IlL (Max) Memory Mapped To ADO-AD15 NMI, CLK READY INTR,HOLD,TEST,RESET MN/MX (0.1I'f to GND) Estimated Speed -0.2 -0.4 -O.B -1.4 -3.3 User System 100% of real time*, up to 4 MHz clock ICE 2 wait states per 80B6-controlled bus cycle 4. Input High Voltages [VIH(Min) = 2.0V] Intellec Approximately 0.02% of real time at 4 MHz clock Diskette ** ADO·AD15 NMI, CLK READY INTR, HOLD,TEST, RESET MN/MX (0.1 I'F to GND) IIH(Max) * 100% of real time is emulation at the user system clock rate with no wait states. * :*The emulation speed from diskette is comparable to Intellee memory, but emulation must wait when a new page is accessed on the diskette. mA mA mA rnA mA BOI'A 20l'A 40l'A -0.4 mA -1.1 mA 5. RO/GTO, RO/GT1 are pulled up to + 5V through a 5.6K ohm resistor. No current is taken from user circuit at Vee, pin. 15-34 -.--.~ ICE-86 1M IN-CIRCUIT EMULATOR SPECIFICATIONS Emulation Clock Operating Environment User system clock up to 4 MHz or 2 MHz ICE-86 internal clock in stand-alone mode Required Hardware Intellec microcomputer development system with: 1. Three adjacent slots for the ICE·86 module (Series II requires Model 201 Expansion Chassis.) 2. 64K bytes of Intellec memory. If user prototype program memory is desired, additional memory above the basic 64K is required. System console Intellec diskette operating system ICE·86 module Physical Characteristics Printed Circuit Boards Width: 12.00 in (30.48 cm) Height: 6.75 in (17.15 cm) Depth: 0.50 in (1.27 cm) Packaged Weight: 9.00 Ib (4.10 kg) Electrical Characteristics DC Power Vcc = +5V +5% -1% Icc = 15A maximum; 11A typical Voo = + 12V ± 5% 100 120 mA maximum; 80 mA typical V BB = - 10V ± 5% or - 12V ± 5% (optional) IBB 15 mA maximum; 12 mA typical Required Software System monitor ISIS-II, version 3.4 or subsequent ICE-86 software = = Equipment Supplied Printed circuit boards (3) Interface cable and emulation buffer module Operator's manual ICE-86 software, diskette-based Environmental Characteristics Operating Temperature: 0' to 40 'C Operating Humidity: Up to 95% relative humidity without condensation. ORDERING INFORMATION Part Numb~r MDS-86-ICE' Description 8086 CPU in-circuit emulator, cable assembly and interactive diskette software. 'MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Science Corporation. 15-35 inter ICE-88™ 8088 IN-CIRCUIT EMULATOR . • Hardware In-Circuit Emulation , • Full Symbolic Debugging • 2K Bytes of High Speed ICE-88™ Mapped Memory • Breakpoints to Halt Emulation on a Wide Variety of Conditions • Software Debugging with or without User System • Comprehensive Trace of Program Execution, Both Conditional and . Unconditional • Handles Full 1 Megabyte Addressability of 8088 • Disassembly of Trace or Memory from Object Code into Assembler Mnemonics • Compound Commands • Command Macros The ICE-88 module provides In-Circuit Emulation for the 8088 microprocessor. It includes three circuit boards which reside in Intellec® Microcomputer Development Systems. A cable and buffer box connect the Intellec system to the user system by replacing the user's 8088. Powerful Intellec debug functions are thus extended into the user system. Using the ICE-88 module, the designer can execute prototype software in continuous or single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints allow the user to stop emulation on user-specified conditions, and the trace capability gives a detailed history of the program execution prior to the break. All user access to the prototype system software may be done symbolically by referring to the source program variables and labels. 15·36 AFN-0145A ICE-88™ IN-CIRCUIT EMULATOR INTEGRATED HARDWARE/SOFTWARE DEVELOPMENT SYMBOLIC DEBUGGING Symbols and PLiM statement numbers may be substi· tuted for numeric values in any of the ICE·88 com· mands. This allows the user to make symbolic refer· ences to 110 ports, memory addresses, and data in the user program. Thus the user need not remember the addresses of variables or program subroutines. The ICE·88 emulator allows hardware and software development to proceed interactively. This is more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE·88 module, prototype hardware can be added to the system as it is designed. Software and hardware testing occurs while the product is being developed. Symbols can be used to reference variables, proce· dures, program labels, and source statements. A vari· able can be displayed or changed by referring to it by name rather than by its absolute location in memory. Using symbols for statement labels, program labels, and procedure names simplifies both tracing and break· point setting. Disassembly of a section of code from either trace or program memory into its assembly mnemonics is readily accomplished. Conceptually, the ICE·88 emulator assists three stages of development: 1. It can be operated without being connected to the user's system, so ICE·88 debugging capabilities can be used to facilitate program development before any of the user's hardware is available. 2. Integration of software and hardware can begin when any functional element of the user system hardware is connected to the 8088 socket. Through ICE·88 mapping capabilities, Intellec memory, ICE memory, or diskette memory can be substituted for missing prototype memory. Time·crltical program modules are debugged before hardware implementa· tion by using the 2K·bytes of high·speed ICE·resident memory. As each section of the user's hardware is completed, it is added to the prototype. Thus each section of the hardware and software is "system" tested as it becomes available. Furthermore, each symbol may have associated with it one of the data types BYTE, WORD, INTEGER, SINTEGER (for short, 8·bit integer) or POINTER. Thus the user need not remember the type of a source pro· gram variable when examining or modifying it. For example, the command "!VAR" displays the value in memory of variable VAR in a format appropriate to its type, while the command "!VAR = !VAR + 1" increments the value of the variable. The user symbol table generated along with the object file during a PLlM·86 compilation or an ASM·86 assem· bly is loaded into memory along with the user program which is to be emulated. The user may add to this symbol table any additional symbolic values for memory addresses, constants, or variables that are found useful during system debugging. 3. When the user's prototype is complete, it is tested with the final version of the user system software. The ICE·88 module is then used for real time emula· tion of the 8088 to debug the system as a completed unit. The ICE·88 module provides access through symbolic definition to all of the 8088 registers and flags. The READY, NMI, TEST, HOLD, RESET, INTR, and MNIMX pins of the 8088 can also be read. Symbolic references to key ICE·88 emulation information are also provided. Thus the ICE·88 module provides the user with the ability to debug a prototype or production system at any stage in its development without introducing extrane· ous hardware or software test tools. Y·CABLE BUFFER BOX ~PLUGINTO USER 8088 SOCKET ,-----r-----, I I I I' I I [BLE ----- ---------------- - ---, I , I Nr"E~k¥C' I, FIRMWARE CONTROLLER BOARD TRACE BOARD I 88·CONTROLLER BOARO 1 I 0 I I' , L ___ -l,< L ___________________________ 'I ,, T·CABLE I MULTI BUS AUXllIARY·CON N ECTOR Figure 1. ICE-88™ Emulator Block Diagram 15·37 , ,I I I ~~~ AFN·0145A ICE~88T1~IN-CIRCUIT EMULATOR DIFFERENCES BETWEEN ICE-88 n " EMULATION AND THE 8088 MICROPROCESSOR DC CHARACTERISTICS OF ICE-88™, USER CABLE 1_ Output Low Voltages (VOL(Max)= 0_4VI , 'lodMin) The ICE-BB module emulates the actual operation, of the BOBB microprocessor with the following exceptions: ,ADO-AD7, AB-A15,. 550, A16/S3-A19/S7, RD, LOCK, 050, 05< SO, 51, 52, WR, M/iO, DT/R, DEN, ALE, INTA - The ICE-BB module willnot respond to a user system NMI or,RESET signal when it is out of emulation .• ', - Trap is ignored in single step mode and' on the Hrst instruction step of an emulation. -The MINIMAX line, which chooses the "minimum" or "maximum" configuration of the BOBB, mUl!t not change dynamically, in the user system. BmA (16mA @ 0.5V) HLDA MATCHO OR MATCH1 (on buffer box) 5mA 16mA 2. Output High Voltages (VoH(Min) = 2_4V) 10H(Mln) - In the "minimum" mode, the user HOLD signal must remain active until HLDA is output by the ICE-BB emulator. ADO-AD7, AB-A15 A16/S3-A19/S7, 550, RD, ' LOCK, 050, 051, So, 51, 52, WR, MilO, DT/R, DEN, ALE, INTA ,HLDA - The RO/GT lines inthe "maximum"configuration are ' not supported. The speed of run emulation by the ICE-SB module depends Oli where the user has mapped his rriei)1ory. As the user prototype progresses to include memory, ' emulation becomes reill time., MATCHO OR MATCH1 (on buffer box) -2.0mA -3.0mA '-O.BmA a.lnput Low Voltages (V ldMax)=O.8V) Memory Mapped To User System ICE Intellec Diskette ADO-AD7 " NMI, CLK READY INTR, HOLD, TEST,RESET MN/MX (0.1"f to GND) " Estimated Speed 100% of real time*; up to 5 MHz clock 2 wait states per BOBB-controlled bus cyCle Approximateiy 0.02% olreal time at 5 MHz clock ** 4_ Input High Voltages (VIH(Mln) = 2.0V) IIH(Max) ADO-AD7 NMI, CLK READY INTR, HOLD, TEST, RESET, MN/MX (0.1"F to GND) .• 100% of real time is emulation at the user system clock. rate with no walt states, •• The emulation speed from diskette is comparable to Inteliec memory, but emulation must walt when a ne~ page is accessed on the diskette. IldMax) -0.2mA -0.4mA -O.BmA -1AmA '-3.3mA BO"A 20"A 60"A -OAmA -1.1 mA 5. RO/GTO, RO/GT1 are pulled up to +5V through a 5.6K ohm resistor. No current is taken from user circuit at Vee pin. 15-38 AFN·0145A intel ICE·88™ IN·CIRCUIT EMULATOR A typical ICE-88 development configuration. It is based on a Model 230 Development System, which also includes a Double Density Diskette Operating System and a Model 201 Expansion Chassis (which holds the ICE-88 emulator). The ICE-88 module is shown connected to a user prototype system. MACROS AND COMPOUND COMMANDS The ICE·88 module provides a programmable diagnostic facility which allows the user to tailor its operation using macro commands and compound commands. The user can also deSignate a block of memory as non· existent. The ICE·88 module issues an error message when any such "guarded" memory is addressed by the user program. Compound commands provide conditional execution of commands (IF), and execution of commands until a con· dition is met or until they have been executed a speci· fied number of times (COUNT, REPEAT). Compound commands and macros may be nested any number of times. . MEMORY MAPPING Memory for the user system can be resident in the user system or "borrowed" from the Intellec System through ICE·88's mapping capability. The ICE·88 emulator allows the memory Which is addressed by the 8088 to be mapped in 1K·byte blocks to: 1. Physical memory in the user's system, 2. Either of two 1K·byte blocks of ICE·88 high·speed memory, 3. Intellec memory, 4. A random·access diskette file. Description Command A macro is a set of ICE·88 commands which is given a Single name. Thus, a sequence of commands which is executed frequently may be invoked simply by typing in a single command. The user first defines the macro by entering the entire sequence of commands which he wants to execute. He then names the macro and stores it for future use. He executes the macro by typing its name and passing up to ten parameters to the com· mands in the macro. Macros may be saved on a disk file for use in subsequent debugging sessions. GO Initializes emulation and allows the user to specify the starting point and breakpoints. Example: GO FROM .START TILL .DELAY EXECUTED where START and DELAY are state· ment labels. STEP Allows the· user to through the program. single·step Table 1. Summary,of ICE·88 Emulation Commands. OPERATION MODES The ICE·88 software is a RAM·based program that pro· vides the user with easy·to·use commands for initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system para· meters. ICE·88 commands are configured with a broad range of modifiers which provide the user with maximum flexibility in describing the operation to be performed. Emulation Emulation commands to the ICE·88 emulator control the process of setting up, running and halting an emula· tion of the user's 8088. Breakpoints and tracepoints enable ICE·88 to halt emulation and provide a detailed trace of execution in any part of the user's program. A summary of the.emulation commands is shown in Table 1. Breakpoints -TheICE·88 module has two breakpoint registers that allow the user to halt emulation when a 15·39 AFN0145A inter ICE·88™ IN·CIRCUIT EMULATOR specified condition is met. The breakpoint registers may be set up for execution or non-execution breaking_ An execution breakpoint consists of a single address which causes a break whenever the 8088 executes from its queue an instruction byte which was obtained from the address_ A non-execution breakpoint causes an emulation break when a specified condition other than an instruction execution occurs_ A non-execution breakpoint condition, using one or both breakpoint registers, may be specified by anyone of or a combination of: program files, defining symbols and macros, displaying trace data, setting up the memory map, and returning control to the ISIS·II operating system. A summary of the basic interrogation and utility commands is shown in Table 2. Memory/Register Commands Dis'play or change the contents of: • Memory • 8088 Registers • 8088 Status flags o 8088 Input pins o 8088 1/0 ports • ICE·BS Pseudo-Registers (e.g. emulation timer) 1. A set of address values. Break on a set of address values has three valuable features: a. Break on a single address. b. The ability to set any number of breakpoints within a limited range (1024 bytes maximum) of memory. Memory Mapping Commands Display, declare, set, or reset the ICE-B8 memory mapping. c. The abilityto break in an unlimited range. Execu, tion is halted on any memory access to an address greater than (or less than) any .20-bit breakpoint address. Symbol Manipulation Commands Display,any or all symbols, program modules, and program line numbers. and their associated values (locations in memory). 2. A particular status of the 8088 bus (one or more of: memory or 1/0 read or write, instruction fetch, halt, or interrupt acknowledge). Set the domain (choose the particula'r program module) for the line numbers. 3. A set of data values (features comparable to break on a set of address values, explained in point one). Remove any or all symbols, modules, and program statements. Define new symbols as thE?Y are needed in ,debugging. Change the value of any symbol. 4. A segment register (break occurs when the register is used in an effective address calculation). TYPE An external breakpoint match output for user access is provided on the buffer box. This allows synchronization of other test equipment when a break occurs. ASM Assign or change the type of any symbol in the symbol table. Disassemble user program memory into ASM-86 Assembler mnemonics. Tracepoints - The ICE-88 module has two tracepoint registers which establish match conditions to conditionally start and stop trace collection. The trace information is gathered at least twice. per bus cycle, first when the address signals are valid and second when the data signals are valid. If the 8088 execution queue is otherwise active, additional frames of trace are collected. PRINT Display the specified portion of the trace memory. LOAD . Fetch user symbol table and. object code from the input file. SAVE Send user symbol table and object code to the output file. LIST Each trace frame contains the 20 addressldata lines and detailed information on the status of the 8088. The trace memory can store 1,023 frames, or an average of about 300 bus cycles, providing ample data for determining how the 8088 was reacting prior to emulation break. The trace memory contains the last 1,023 frames of trace data collected, even if this spans several separate emulations. The user has the option of displaying each frame of the trace data or displaying by instruction in actual ASM-86 Assembler mnemonics. Unless the user chooses to disable trace, the trace information is always available after an emulation. Send a·. copy of all output (including prompts, input line echos, and error messages) to the chosen output device (e.g. disk, printer) as well as the console. EVALUATE Display the value of an expression in binary, octal, decimal, hexadecimal. and ASCII. SUFFIX/BASE Establish the default base for numeric values in input textfoutput display (binary, octal, decimal, or hexadec·imal). CLOCK Select the· internal .(lCE-88 provided, for stand-alone mode only) or an external (user-provided) system clock. RWTIMEOUT Allows the user to time out READIWRITE command Signals based on the time taken by the 8088 to access Intellec memory or diskette memory. Interrogation and Utility Interrogation and utility commands give the user con· venient access to detailed information about the user program and the state of the 8088 that is useful in debugging hardware and software. Changes can be made in both memory and the 8088 registers, flags, inputpins,and 1/0 ports. Commands are also provided for various utility operations such as loading and saving ENABLEIDISABLE RDY Enable or disable logical AND of ICE·88. Ready with the user Ready signal for accessing Intellec memory, ICE memory, or di skette memory. - Table 2. Summary of Basic ICE·88 Interrogation and Utility Commands. 15-40 = -. AFN0145A ICE-88™ IN-CIRCUIT EMULATOR SPECI FICATIONS Emulation Clock Operating Environment User system clock up to 5 MHz or 2 MHz ICE-88 internal clock in stand-alone mode Required Hardware Intellec microcomputer development system with: 1. Three adjacent slots for the ICE·88 module. (Series II requires Model 201 Expansion Chassis). 2. 64K bytes of Intellec memory. If user prototype pro· gram memory is desired. additional memory above the basic 64K is required. System console Intellec diskette operating system ICE·88 module Required Software System monitor ISIS·II, version 3.4 or subsequent ICE·88 software Physical Characteristics Printed Circuit Boards Width: 12.00 in (30.48 cm) Height: 6.75 in (17.15 cm) Depth: 0.50 in (1.27 cm) Packaged Weight: 9.00 Ib (4.10 kg) Electrical Characteristics DC Power Vcc= +5V +5%-1% Icc = 15A maximum; 11 A typical Voo = + 12V ±5% 100 = 120mA maximum; 80mA typical VBB = -10V±5% or -12V±5% (optional) IBB = 25mA maximum; 12mA typical Equipment Supplied Environmental Characteristics Printed circuit boards (3) Interface cable and emulation buffer module Operator's manual ICE-88 software, diskette-based Operating Temperature: 0 to 40°C Operating Humidity: Up to 95% relative humidity with' out condensation. 0 ORDERING INFORMATION Part Number Description MDS-88-ICE' 8088 CPU in-circuit emulator 'MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Science Corporation. 15-41 ---".:..:..:.:::.. Prototype Microcomputer Kits 16 SDK-8S MCS-8S™ SYSTEM DESIGN KIT • Complete Single Board Microcomputer System Including CPU, Memory, and I/O • Easy to Assemble, Low Cost, Kit Form • Popular SOSOA Instruction Set • Interfaces Directly with TTY • Extensive System Monitor Software in ROM • High Performance 3 MHz SOSSA CPU (1.3 J-tS Instruction Cycle) • Interactive LED Display and Keyboard • Comprehensive Design Library Included • Large Wire-Wrap Area for Custom Interfaces The SDK-85 MCS-85 System Design Kit is a complete single board microcomputer system in kit form. It contains all components required to complete construction of the kit, including LED display, keyboard, resistors, caps, crystal, and miscellaneous hardware. Included is a preprogrammed ROM containing a system monitor for general software utilities and system diagnostics. The complete kit includes a 6-digit LED display and a 24-key keyboard for a direct insertion, examination, and execution of a user's program. In addition, it can be directly interfaced with a teletype terminal. The SDK-85 is an inexpensive, high performance prototype system that has designed-in flexibility for simple interface to the user's application. 16-1 SDK·8S FUNCTIONAL DESCRIPTION The SDK·85 is a complete 8085A microcomputer system on a single board, in kit form. It contains all necessary components to build a useful, functional system. Such items as resistors, capacitors, and sockets are included. Assembly time varies from three to five hours, depend· ,ng on the skill of the user. The S~K·85 functional block diagram is shown 'n Figure 1. 808SA Processor ADDRESS DECODER ROMIIO (8355) EPROM/IO (8755) Addressing - The 8085A uses a multiplexed data bus. The 16·bit address is split between the 8·bit address bus and the 8·bit address/data bus. The on·chip address latches of 8155/8156/8355/8755 memory products allows a direct interface with the 8085A. System Monitor The SDK·85 is designed around Intel's 8085A microproc· essor. The Intel 8085A is a new generation, complete 8·bit parallel central processing unit (CPU). Its instruc· tion set is 100% software upward compatible with the 8080A microprocessor, and it is deSigned to improve the present 8080A's performance by higher system speed. Its high level of system integration allows a minimum system of three IC's: 8085A (CPU), 8156 (RAM), and 8355/8755 (ROM/PROM). A block diagram of the 8085A microprocessor is shown in Figure 2. CPU System Integration - The 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (sys· tem controller) provided for the 8080A, thereby offering a high level of system integration. A compact but powerful system monitor is supplied with the SDK·85 to provide general software utilities and system diagnostics. It comes in a pre·programmed ROM. Communications Interface The SDK·85 communicates with the outside world through either the on·board LED display/keyboard com· bination, or the user's TTY terminal (jumper selectable). KEYBOARD/DISPLAY RAM/IO/COUNTER . _---- FOR BUS EXPANSION DATA FIELD r-~:6--'} L _____ .J .. B DATA BUS r----' INTERRUPT INPUTS I 8216 I '- -----..1 [~ ~ J I OPTIONAL '6gic~£'~~~~~~~:U~EV~DED ON THE PC BOARD FOR THE DEVICE BUT THE Figure 1. SDK·aS System Design Kit Functional Block Diagram 16·2 SDK·8S INSIDE THE 8085: POWER{_ +5V SUPPLY _ GND TIMING AND CONTROL A 1S"A e A07·ADo ADDRESS/DATA SUS ADDRESS BUS • • SEVEN a-BIT REGISTERS_ SIX OF THEM CAN BE LINKED IN REGISTER PAIRS FOR CERTAIN OPERATIONS, ' a-BIT ALU_ , • • 16-BIT STACK POINTER (STACK IS MAINTAINED OFFBOARDIN SYSTEM RAM MEMORY), 16-BIT PROGRAM COUNTER. Figure 2. SOSSA Microprocessor Block Diagram Both memory and 1/0 can be easily expanded by simply soldering in additional devices in locations provided for this purpose. A large area of the board (45 sq. in.) is laid out as general purpose wire·wrap for the user's custom interfaces. Commands - Keyboard monitor commands and teletype monitor commands are provided in Table 1 and Table 2 respectively. Command Assembly Display memory Only a few simple tools 'are required for assembly; soldering iron, cutters, screwdriver, etc. The SDK·85 user's manual contains step-by-step instructions for easy assembly without mistakes. Once construction is complete, the user connects his kit to a power supply and the SDK-85 is ready to go. The monitor starts immediately upon power-on or reset. Command Substitute memory Insert instructions Move memory Operation Examine register Reset Go Starts monitor. Allows user to execute user program. Single step Allows user to execute user program one instruction at a timeuseful for debugging. Substitute memory Allows user to examine and modify memory locations. Examine register Allows user to examine and modify 8085A's register contents. Vector interrupt Serves as user interrupt button. I Go Operation Displays multiple memory locations. Allows user to examine and modify memory locations one at a time. Allows user to store multiple bytes in memory. Allows user to move blocks of data in memory, Allows user to examine and modify the 8085A's register contents. Allows user to execute user programs. Table 2. Teletype Monitor Commands I Documentation In addition to detailed information on using the monitors, the SDK-85 user's manual provides circuit diagrams, a monitor listing, and a description of how the system works. The complete design library for the SDK-85 is shown in Figure 7-11 and listed in the Specifications section under Reference Manuals. Table 1_ Keyboard Monitor Commands 16-3 Figure 3. SDK·8S Design Library 8085A INSTRUCTION SET Table 3 contains a summary of processor instructions used for the BOBSA microprocessor. Mnemonlc 1 1 Description, Instruction Code 2 I 1Clock 3 07 06 0 5 04 03 0201 DO Cycles 1 MOVE. LOAD. AND STORE MOVr1r2 Move register to register 0 1 0 0 0 S S S Mnemonlc 1 1 Descrlpllon Instrucllon Code2 1 01 Clock 3 07 06 05 04 03 02 0, DO Cycles LXI SP Load immediate stack pointer 0 0 1 1 0 0 0 1 10 Increment slack pOinter 0 0 1 1 0 0 1 1 6 Decrement slack pOinter 0 0 1 1 1 0 1 1 6 4 MOV M.r Move register to memory 0 1 1 1 0 S S S 7 INX SP MOV r.M Move memory to fegister 0 1 0 0 0 1 1 0 7 OCXSP MVI r Move immediate register 0 0 0 0 0 1 1 0 7 MVI M Move immediate memory 0 0 1 1 0 1 1 0 10 JUMP LXI B Load immediate register Pair B & C 0 0 0 0 0 0 0 1 10 JMP Jump unconditional 1 1 0 0 0 0 1 1 10 JC Jump on carry 1 1 0 1 1 0 1 0 7/10 LXI D Load immediate register 0 0 0 1 0 0 0 1 10 JNC Jump on no carry 1 1 0 1 0 0 1 0 7/10 JZ Jump on zero 1 1 0 0 1 0 1 0 7/10 Pair D & E LXI H load immediate register Pair H & L 0 0 1 0 0 0 0 1 10 STAX B Store A Indirect 0 0 0 0 0 0 1 0 7 JNZ ; Jump on no zero 1 1 0 0 0 0 1 0 7110 JP / Jump on positive 1 1 1 1 0 0 1 0 7fl0 Jump on minus 1 1 1 1 1 0 7/10 STAX 0 Store A Indirect 0 0 0 1 0 0 1 0 7 JM 1 0 LDAX B Load A Indirect 0 0 0 0 1 0 1 0 7 JPE Jump on parity even 1 1 1 0 1 0 1 0 7110 J~O Jump on parity odd 1 1 1 0 0 0 1 0 7110 PCHL H !i L to program counter 1 1 1 0 1 0 0 1 6 LOA X 0 Load A indirect 0 0 0 STA Store A direct 0 0 LOA Load A direct 0 0 SHLO Store H & L direct 0 LHLD Load H & L direct 0 XCHG Exchange D & E, H & L registers 1 PUSH B Push register pair B & C on stack . PUSH D 0 7 1 0 13 1 0 13 0 1 0 16 0 1 0 16 CAll Call unconditional 1 1 0 0 1 1 0 1 18 0 1 1 4 CC Call on carry 1 1 0 1 1 1 0 0 9118 CNC Callan no carry 1 1 0 1 0 1 0 0 9118 1 0 0 1 1 9118 1 0 0 0 CZ 1 1 12 Call on zero 0 0 1 0 1 12 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 0 1 1 1 0 0 Push register pair D & E on stack 1 1 0 1 Push register pair H & L on stack 1 0 1 0 0 1 0 CALL STACK OPS PUSH H 1 1 0 0 1 0 1 12 PUSH PSW Push A and-flags on stack 1 1 1 1 0 1 0 1 12 POP B Pop register pair B & C off stack 1 1 0 0 0 0 0 1 10 CNZ Call on no zero 1 1 0 0 0 1 0 0 9/18 CP Callan positive 1 1 1 1 0 1 0 0 9118 CM Call on minus 1 1 1 1 1 1 0 0 9118 CPE Call on parity even 1 1 1 0 1 1 0 0 9/18 CPO Call on parity odd 1 1 1 0 0 1 0 0 9/18 Return 1 1 0 0 1 0 0 1 10 Return on carry 1 1 0 1 1 0 0 0 6/12 RNC Return on no carry 1 1 0 1 0 0 0 0 6/12 RZ Return on zero 1 1 0 0 1 0 0 0 6112 RETURN RET RC POP D Pop register pair 0 & E off stack 1 1 0 1 0 0 0 1 10 POP H Pop register pair H & L off stack 1 1 1 0 '0 0 0 1 10 POP PSW Pop A and flags off stack 1 1 1 1 0 0 0 1 10 XTHL Exchange top of stack. H&L 1 1 1 0 0 0 1 1 16 SPHL H & L to stack pointer 1 1 1 1 1 0 0 1 6 RNZ Return on no zero 1 1 0 0 0 0 0 0 6/12 RP Return on positive 1 1 1 1 0 0 0 0 6112 RM Return on minus 1 1 1 1 1 0 0 0 6112 contmued 16·4 SDK·a5 Mnemonlc 1 J Description I I Clock 3 Instruction Code 2 I Cycles ) 07 06 Os 04 03 02 01 DO Mnemonlc 1 RPE Return on parity even 1 1 1 0 1 0 0 0 6112 lOGICAL RPO Return on parity odd 1 1 1 0 0 0 0 0 6112 ANA r XRA r RESTART RST L And register with A 1 0 1 0 0 S S S 4 Exclusive Or register 1 0 1 0 1 S S S 4 4 I 107 Instruction Code 2 Os 05 04 03 02 0, Dol Cycles with A 1 Restart 1 A A A 1 1 1 12 ORA r Or register with A 1 0 1 1 0 S S S CMPr Compare register with A 1 0 1 1 1 S S S 4 4 ANA M And memory with A 1 0 1 0 0 1 1 0 7 XRA M Exclusive Or memory 1 0 1 0 1 1 1 0 7 INCREMENT AND DECREMENT INR r I Clock 3 Description Increment register 0 0 D D D 1 0 DCRr Decrement register 0 0 D D D 1 0 1 4 INA M Increment memory 0 0 1 1 0 1 0 0 10 DCA M Decrement memory 0 0 1 1 0 1 0 1 10 ORA M Or memory with A 1 0 1 1 0 1 1 0 7 INX B Increment B & C registers 0 0 0 0 0 0 1 1 6 CMP M Compare memory with A 1 0 1 1 1 1 1 0 7 INX D Increment 0 & E 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 7 6 ANI And immediate with A 0 XRI Exclusive Or immediate 1 1 1 0 1 1 1 0 7 0 with A registers lNX H Increment H & L registers 0 0 1 0 0 0 1 1 6 DCX B Decrement B & C 0 0 0 0 1 0 1 1 6 DCX 0 Decrement 0 & E 0 0 0 1 1 0 6 DCX H Decrement H & L 0 0 1 0 1 0 , 1 1 6 ADD r Add register to A 1 0 0 0 0 S S S 4 ADC r Add register to A with carry 1 0 0 0 1 S S S 4 ADD M Add memory to A 1 0 0 0 0 1 1 0 7 ADC M Add memory to A with carry 1 0 0 0 1 1 1 0 7 ADI Add immediate to A 1 1 0 0 0 1 1 0 7 . ACI Add immediate to A with carry 1 1 0 0 1 1 1 0 7 DAD B Add 8 & C to H & L 0 0 0 0 1 0 0 1 DAD D Add D & E to H & L 0 0 0 1 1 0 0 DAD H Add H & L to H & L 0 0 1 0 1 0 DAD SP Add stack painter to 0 0 1 1 1 0 1 with A ORI Or immediate with A 1 1 1 1 0 1 1 0 7 CPI Compare immediate 1 1 1 1 1 1 1 0 7 with A ROTATE RlC Rotate A left 0 0 0 0 0 1 1 1 4 RRC Rotate A right 0 0 0 0 1 1 1 1 4 RAl Rotate A left through carry 0 0 0 1 0 1 1 1 4 RAR Rotate A right through carry 0 0 0 1 1 1 1 1 4 CMA Complement A 0 0 1 0 1 1 1 1 4 STC Set carry 0 0 1 1 0 1 1 1 4 10 CMC Complement carry 0 0 1 1 1 1 1 1 4 1 10 DAA Decimal adjust A 0 0 1 0 0 1 1 1 4 0 1 10 0 1 10 ADO SPECIALS INPUT/OUTPUT H&l IN Input 1 1 0 1 1 0 1 1 10 OUT Output 1 1 0 1 0 0 1 1 10 EI Enable interrupts 1 1 1 0 1 1 4 Disable interrupts 1 1 , 1 DI 1 0 0 1 1 4 NOP No·operation 0 0 0 0 0 0 0 0 4 HlT Halt 0 1 1 0 1 1 0 5 SUBTRACT SUB r Subtract repister from A 1 0 0 1 0 S S S 4 SBB r Subtract register from A with borrow 1 0 0 1 1 S S S 4 SUB M Subtract memory from A 1 0 0 1 0 1 1 0 7 SBB M Subtract memory from A with borrow 1 0 0 1 1 1 1 0 7 SUI Subtract immediate from A 1 1 0 1 0 1 1 0 7 SBI Subtract immediate from A with borrow 1 1 0 1 1 1 1 0 7 CONTROL 1 , RIM Read interrupt mask 0 0 , 0 0 0 0 0 4 SIM Set interrupt mask 0 0 1 1 0 0 0 0 4 NEW 8085 INSTRUCTIONS Notes 1. All mnemonics copyright © Intel Corporation 1977. 2. DDD or SSS: 8=000, C=001, D=010, E=011, H=100, L= 101, Memory = 110, A= 111. 3. Two possible cycle times. (6/12) indicates instruction cycles dependent on condition flags. Table 3. Summary of 8085A Processor Instructions SPECIFICATIONS Addressing Central Processor ROM - 0000-07FF (expendable to OFFF with an additional 8355/8755A) RAM - 2000-20FF (2800-28FF available with an additional8155) CPU - 8085A Instruction Cycle Tcy - 330 ns 1.3 I's Memory Note The wire-wrap area of the SDK·85 PC board may be used for additional ROM - 2K bytes (expandable to 4K bytes) 8355/8755A RAM - 256 bytes (expandable to 512 bytes) 8155 custom memory expansion up to the 64K·byte addressing limit of the 8085A. 16·5 SDK·as Input/Output Physical Characteristics Parallel - 38 lines (expandable to 76 lines) Serial - Through SID/SOD ports of 8085A. Software generated baud rate. Baud Rate - 110 Width Height Depth Weight - Interfaces DC Power Requirement (power supply not included in kit) 12.0 in. (30.5 cm) 10 in. (25.4 cm) 0.50 in. (1.27 cm) approx. 12 oz Electrical Characteristics Bus - All signals TTL compatible Parallel 110 - All signals TTL compatible Serial 110 - 20 mA current loop TTY Voltage 1.3A ' 0.3A VTTY -lOY ± 10% (VTTY required only if teletype is connected) Environmental Characteristics Interrupts Operating Temperature - Three Levels (RST 7.5) - Keyboard interrupt (RST 6.5) - TTL input (INTR) - TTL input Reference Manuals Jumper selectable. TTL compatible Software System Monitor - Pre·programmed 8755A or 8355 ROM Addresses - 0000-07FF Monitor 110 - Keyboard/display or TTY (serial 110) ORDERING INFORMATION Part Number Description SDK-85 MCS-85 system design kit 0-55°C 9800451 - SDK-85 User's Manual (SUPPLIED) 9800366 - MCS-85 User's Manual (SUPPLIED) 9800301 - 8080/8085 Assembly Language Programming Manual (SUPPLIED) 8085/8080 Assembly Language Reference Card (SUP· PLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. DMA Hold Request input. Current Vee 5V ±5% Note By populating the buffer area of the board, the user has access to all bus signals that enable him to design custom system expansions into the kit's wire-wrap area. 16·6 SDK-86 MCS-86™ SYSTEM DESIGN KIT • Wire Wrap Area for Custom Interfaces • Complete Single Board Microcomputer System Including CPU, Memory, and 1/0 • Extensive System Monitor Software in ROM • Easy to Assemble Kit Form • High Performance 808616-Bit CPU • Comprehensive Design Library Included • Interfaces Directly with TTY or CRT • Interactive LED Display and Keyboard The SDK-86 MCS-86 System Design Kit is a complete single board 8086 microcomputer system in kit form. It contains all necessary components to complete construction of the kit, including LED display, keyboard, resistors, caps, crystal, and miscellaneous hardware. Included are preprogrammed ROMs containing a system monitor for general software utilities and system diagnostics. The complete kit includes an 8-digit LED display and a mnemonic 24-key keyboard for direct insertion, examination, and execution of a user's program. In addition, it can be directly interfaced with a teletype terminal, CRT terminal, or the serial port of an Intellec system. The SDK-86 is a high performance prototype system with designed-in flexibility for simple interface to the user's application. 16-7 SDK·86 FUNCTIONAL DESCRIPTION A block aiagram of the 8086 microprocessor isshown in Figure 2. The SDK-86 is a complete MCS-86 microcomputer system on a single board, in kit form. It contains all necessary components to build a useful, functional system. Such items as resistors, caps, and sockets are included. Assembly time varies from 4 to 10 hours, depending on the skill of the user. The SDK-86 functional block diagram is shown in Figure 1. System Monitor A compact but powerful system monitor is supplied with the SDK-86 to provide general software utilities and system diagnostics. It comes in preprogrammed read only memories (ROMs). Communications Interface 8086 Processor The SDK-86is designed around Intel's 8086 microprocessor. The Intel 8086 is a new generation, high performance microprocessor implemented in N-channel, deple- . tion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor features attributes of both 8-bit and 16-bit microprocessors in that it addresses memory asa sequence of 8-bit bytes, but has a 16-bitwide physical path to memory for high performance. Additional features of the 8086 include the following: • Direct addressing capability to one megabyte of memory • Assembly language compatibility with 8080/8085 • 14 word x 16-bit register set with symmetrical operations • 24 operand addressing modes • Bit, byte, word, and block operations • 8 and 16-byte signed and unsigned arithmetic in binary or decimal mode, including multiply and divide • 4 or 5 or 8 MHz clock rate The SDK-86 communicates with the outside world through either the on-board light emitting diode (LED) display/keyboard combination or the user's TTY or CRT terminal (jumper selectable), or by means of a special mode in which an Intellec development system transports finished programs to and from the SDK-86. Memory may be easily expanded by simply soldering in additional devices in locations provided for this purpose. A large area of the board (22 square inches) is laid out as general purpose wire-wrap for the user's custom interfaces. Assembly Only a few simple tools are required for assembly: soldering iron, cutters, screwdriver; etc. The SDK-86 assembly manual contains step-by-step instructions for easy assembly with a minimum of mistakes. Once construction is complete, the user connects his kit to a power supply and the SDK-86 is ready to go. The monitor starts immediately upon power-on or reset. Commands - Keyboard mode commands, serial port commands, and Intellec slave mode commands are summarized in Table 1, Table 2, and Table 3, respectively. The SDK-86 keyboard is shown in Figure 3. CONTROL LINES CONNECTOR ADDRESS BUS EXPANSION CONNECTOR LED DISPLAY Figure 1. SDK-S6 System Design Kit Functional Block Diagram 16-8 AFN-Ol012A SDK·8S Documentation In addition to detailed Information on using the monitors, the SDK-86 user's manual provides circuit diagrams, a monitor listing, and a description of how the system works_ The complete design library for the SDK-86 is shown in Figure 4 and listed In the specifications section under Reference Manuals. EXECUTION UNIT REGISTER FilE BUS INTERFACE UNIT I R~~~~it.iI~~E I DATA, POINTER. AND INDEX REGS (8WOR.DS) Figure 4. SDK-B6 Design Library '-"':::"'''-"''1-_iiHlrIS, Al~S. AI~S3 Command Reset Starts monitor. Go Allows user to execute user program, and causes It to'halt iO!t predetermined program stop. Useful for debugging. Single step Allows user to execute user program, one instruction at ,a time. Useful for debugging. Substitute memory Allows user to examine and modify memory locations in byte or word mode. Examine register Allows user to examine and modify 8086 register contents. Block move Allows user to relocate program and data portions In memory. Input or output Allows direct control of SDK-86 I/O facilities hi byte or mode. B·BYTE INSTRUCTION QUEUE· i~ __-J--------~--------' INT-_ NMI-- RCIGTO.1W HOLD HLDA--..-r__....,.__""T"__....,.__~ elK Vee RESET READY GND Figure 2. 8086 Microprocessor Block Diagram Operation Table 1_ Keyboard Mode Commands RESET 8 + IWfCS REG 9 OWfDS A flSS Command Operation Dump memory Allows user to print or display large blocks of memory information in hex format than amount visible on terminal's CRT display. Start/continue display Allows user to display blocks of memory Information larger than amount visible on terminal's CRT display. Punch/read paper tape Allows user to transmit finished programs into and out of SDK-86 via TTY paper tape punch. B fES 4 5 6 7 IBfSP OB/BP MV/SI EW/DI 0 1 EB/AX ER/BX 2 GO/CS 3 ST/DX Figure 3. SDK-B6 Keyboard Table 2. Serial Mode Commands 16-9 ' AFN-Dl012A SDK·86 8086 INSTRUCTION SET Table 4 contains a summary of processor instructions used for the 8086 microprocessor. Mnemonic and Description Mnemonic and Description Instiuction Code I Instruction Code Data Transfer MOV ~ Moy.: 715432'10 7un'rlD Aegislerlmemory lollrom re!lister 11 DO 0 1 0 d w,1 mod Immediate 10 regisleflmemory 11 reg 7&&43210 Immediale 10 register Memory 10 accumulator 10 10 0 00 w dala adelr-high adelr-Iow rIm addr-tllgll 11 11 0" 0 0 0 1w I 000 1 1 10 Imod 0 reg Segment register 10 register/memory 11 000 1 100 Imod 0 reg CMP I datailw-l data ilw.l addr-Iow Accumulalor to memory Reoislerlmemory to segmenl:register 715.0%10 rim I 1 0 0 0 1 1 w moa 0 0 0 rim 1011'11 reg dala I I 11 1111 Register 01010 reg 000regl10 Segmenlregister POP = mod 110 rim 711543210 100000 s \If modI I' rim 00111 10 \If adjusllor subtract DAS·Decimal adjusl lor subtracl rIm 71543110 00 1 1 1 0 d \If mod reg AIII~ASCIl Pap: Register/memory CGmptrl: tmmediate wl,h regIster/memory Immediate wllh accumulalor PUSH,. PUlh: Register/memOry ~ Regislerlmemoryand register 71543210 71643210 rim dala dala!!w-l data II s:\If-OI 001111,' 00101111 MUL·Mutlipty (unsigned) 1 1 1 1 0 1 1 w mod I 0 0 rIm IMUL-Inleger multiply (Signed) 11,'011 w mod 101 rim AAM-ASCII adjust lor multiply 11 0 1 0 100 DIY-Oivlde(unsigned) 1 I 1 1011 w mod 1 10 rim 00001010 IDIY·lnleger divide (Signed] 11110" .loAD-ASCII adjusl tor divide caW-Convert byte to word 11 0 1 0" 0 1 w mati 1 11 rim CWO·Canvert word 10 double word 100'100 I Logic 1I0T·lnvert 1111011'11 modO 1 0 rim 00001010 1 0 0 1 tOO 0 10 0 0 11 I 1 modO 0 0 rim 0101 1 reg Register 1000reglli I Segment register leNS,. behIRg.: Reglslerlmemoryw,ilh register Aegislerwilh accumulaior 1100001 I'll Imod reg 110010 reg rim I I SHl/SAl·Shilt logicallarithmetic leU , SHR,Shilllogicalright IfiI,.lnpul Fludporl III Varrable porI 11110110'11 OUT = Output !" , Fixed port I byte to AL BAR-Shill arithmelic rillht port I pori 0 0 1 I \If 1 1110111'11 Variable port XLU~Translate 10010 'II EAto rellisler 11010111 1000 I 101 mod reg rim 11000101 mod r!{l rim LEI~Load 11000100 mod rell pointer to ES lJ.Hf40ad AHwith !lags 1100111111 UHf·Slore AH into lIags 1100111101 PUIKF-Push lIags 10011100 POPf-Popllags 10011101 ~ Add: Reg.lmemory Wllh register to eilher 000000 d 'II mod reg 100000 s w modO 0 0 rim Immedialeto accumulator 0000010'11 ~ Add with mry: Reg.lmemory wilh register to eilher Immediate to regislerlmemory Immediate to accumulator ,.C rIm data I~ 0 0 1 0 lOw I dala 11 I 1 1 I 1 w mod 000 rim Register 01000 reg AlA-ASCII adjust lor add 0011 0111 data i!s:w-Ol ::::::::: IBI :~:: ~:i~:~~;:~ory = IubltlCl Immediate Irom accumulator ~ 1 I 0 1 0 D v w modO 1 1 F.'~'~'~'~'!'~' ~.~m~"~'1J"~'cttt1=::J~~r=~~TI ~ 0 0 0 0 0 0 'II mod 1 0 0 rim dala dala if 'II-I DOlO 0 lOw data OR· Or: Reg.lrnemory and r!{llSler to eilher 100001 0 d w Imod reg~ Immediate to regislerlmemory 11000000'11 ImodO D 1 rim Immediate 10 accumutator 10 0 0 0 lID w ~ I data if 'II-I dala datailw-l data il w~1 data helullvlor: Rell./memoryandregistertoeilher 001100 d 'II mod reg Immediale10 registerlmemory 10 D 0 0 0 0 'II modl1 0 rim rim Immediate 10 accumulator 0011 DID w data dala dalailw·l data 1/'11·1 100100111 Siring Manipulation IIEP-Repeat MOVS= Move bytelword I f:'",'",'",',:.'",':.'~.¥m;;;:.~'~"~"~lm9---,;::::--r-==""" f;:':::'::~';:'::~.;.~.;.:;;.:¥m;;;:':."~':,;,:=,:;;;lm9~,:",.,;!:a~i;a~,.",",-t--""'' :::''",if5",'"",",,-,' II 1 1 1001 z I. 101001 0 'II CMPS = Compare bytelword 10 10 0 1 I w SCAS::: Scan byte/word 10 101 1 1w LODS::: Load byte/wd to AUAX I 0 1 0 1 lOw STDS=5tor byte/wd Irm AUA 1010'0 I w wlttl bern. Rq./memory reoisterto either tmmediate fromandregisterlmemory DEC 110 I 00 v w modO 1 D rim IICH-Rotate through carry righl dala if '11-1 SUB ~ Subll'lct: Reg.lmemory and register to either 110100 v w modO 0 0 rim 110'00 v w modO 0 1 rim ~Io~'~'~'~'~'I':::'~Im~"~'~,,~,:'~Imq-----c-'--_r-=c.-c--:::-l ~Il~'~'~'~'±'t'~'tlm="="='~'~"mj=§'~'''~J''':':::'':::'',-,il5",.'",-',,-,'I Registerlmemory DAA·Decimal adjust lor add mod 111 rim ROR·Rotate right XOR dala dala ilw-l 'ner,mlnl: ~ modI 0 1 rim V'll 00 kDl-Rolate Ie!! Immediate to accumulator Immediate loregister/memory ADC mod I DO rim V'll I IICl·Rotate through carry lIag lell Reg,/memory and reglsler to eilher Immediale 10 registerlmemory Arithmetic ADD 'II 110100 AND· And: LDI-Load pOinter to DS LU~Load 1 1.0 1 00 v 110 ~~'~'~'~'~'~'~'Em~",~"~'~'~lmg=~~I:p~~~ 1 0 0 000 s w mod 0 1 1 rim 000 , 1 lOw clata 25 Dlieramlnl: Reglsterlmemory data dala It w-1 11 I I l i t I W ImodO 0 1 rim dala II 5:w-Ol Control Transfer CALL £ Call: Direct within segment 11101000 Indireclwllhinsegmenl '1111111 Direct ~il\ersegmenl Q011010 Indirectinlersegment t i l l ' 111 dlsp-Iow mod 0 1 0 rim ollsel·low 1 Register 10'1001 reg lIES-Change sign 11111011 w lmodO 11 tim seg·hlgh mati 0 1 I rim contInued AFN-01012A 16·10 SDK·a6 Mnemonic and Description JMp· UnCDndlllonl1 Jump: Oueel wlIl'lin segment 711543210711&.(32101850210 ) 1 1 10 1 00 1 Dorect wllh,n segmen1-Shor, 11101011 Indirect wl\hlnsegmenl 1 111 1 1 1 1 dlsp-Iow I dlsp-hl~11 o!1sel·h'gh 111543210 JIIS·Jumpon not slon 1011110011 loOp·loopCX limes ~]dISP LOOPZlLDOP('loop while zero/equal lOOPIIZlLoOPIIE·Loopl'ohllenot zero/equal JCXl·Jump on CX zero mod 1 0 a rim ollsel-Iow Instruction Code 7115 43 210 I I ~~77~IF~~"~o'~I'W~+-~ dlsp 11100001 dlsp 11100000 dlsp 11100011 dlsp Typespeclheo 11001101 Iype Type 3 11001100 )1 1 1 1 I 1 1 1 !mod 101 11m IndutClmtersegment = Rllurn I 11 1 1 0 1010 r Direct Inlersegment RET Mnemonic and Description Instruction Code I Iram CALL' Within segment Within seg. adding Immed 10 SP ! 1 10000' 1 I In!ersegment 11 1001011 I Inlersegment. addmg Immediate 10 SP I~'~'~'~'~'!'~1O~1~:Jj~~+=::J:~iE::J JE/JZ·Jumpon equal/zero 101110100 I Jl/JIIIIE~~Ue~~a~n less/not greater IIH·lntarrupl IF.,~,~,~,~,~,~1O!ci1f------::=-:--,-------;=~.., IIITO·IMerrupton overflow IRET·lnterruplrelurn \1001110 1110011111 I~'~'~'~'~'~'~oo~IF~~9 JlE/JIIG~~~~~ron less arequal/no! ~'~'~'~'~'~'~10~~~~'9 JI/JIIAE~~~~ea~n below/not above ~'~'~'~'~'~'~10~~~~'9 Processor Control Jl£/JIIA~~~~goov~ below or equal/ Fi'..,',,;,',,;,'.;.'~'",1O;+~"';;"""'-=I CLC·Cle3rcarry JP/JP(-Jump on parity/parity even F.'=;'=;'=;'~'~'::,,10~=~~'9 CMC·Complemenl carry 11110101 STC'Setcarry 1 1 1 11 001 1~,~,~,~,~,~,~oo~1~~~'9 JO·Jumponover!low JS-Jump on sion JIIEWIZ-JumponnoteQuallnotzero JllL/m~~u~ea~n not less/greater JIILE/JBg~~~~ron not less or equal/ 11 1 1 11 0 a0 10 t I l l 000 1 ClD,Cleardlrectlon 1 1 11 1 100 I~'~'~'~'~'~'t'~'~II ~~~~ STD'SetdlrectlOn 11 1 1 1 101 CLI,Clearlnlerrupt 1111 1010 I~'~'~'~'~'~'~'~'FI~~~'9 ~ 1111111 1111 101 1 ST!,Setlnterrupt JItB/J.U~1ue~eayn nOI below/above 10 1 1 1 00 1 1 1,1,10,00 10 1 1 1 0 1 1 1 I I HLT'Halt JIIBE/JA;~~~8ao~0~~t below or WAIT'Walt 110011 0 11 JItP/JPO·Jumpon nol par/par odd 101 1 11 a 1 1 I· ESC·Escape (to external JIIO·Jump on nolover!low 101110001 I I de~lcel LOCK-Sus lOCk prelix I I 111011 x x x Imod X)(X rim '111 1 0000 , Notes Al ,,8-bitaccumulator AX" 16-bit accumulator CX" Count register OS" Data segment ES" Extra segment Abovelbelow refers to unsigned value. Greater" more positive: Less" less positive (more negative) signed values it s:w = 01 then 16 bits of immediate data form the operand. if s:w=11 then an immediate data byte is sign extended 10 form the 16-btI operand. it v = 0 then "count" = 1; If v = 0 then "count" In (Cl) x=don't care. II v=O then "counl"=1: II v=1then "count" In (Cl) register. z is used lor string primitives for comparison with ZF FLAG Ild=1 then "to" reg; Ild=Othen "from" reg if w" 1 then word instruction: it w" Othen byte Instruction SEGMENT OVERRfDE PREFIX Q01reg110 REG is assigned according to the lollowing table: if mod'" if mod" if mod" if mod'" 11 then 00 then 01 then 10 then if rIm" 000 then il rIm = 001 then if rIm" 010 then il rim ~ 011 then il rIm" 100 then If rIm" 101 then il rIm", 110 then if rIm" 111 then DISP follows 2nd rIm is treated as a REG field DISP" 0·, disp-Iow and dlsp-high are absent DISP " disp-Iow sign-extended to 16-bits, disp-hlgh is absent DISP.o disp-high: disp-Iow I~Blt (w 000 001 010 011 100 101 110 111 EA " (BX) -t- (51) .. DISP EA " (BX) -t- (01) -t- DISP EA " (BP) -t- (SI) -t- OISP EA ~ (BP) • (01) • OISP EA " (51) -t- DISP EA ,,(01) -t- OISP EA " (BP) -t- DISp· EA" (BX) -t- DISP byte of instrlittion (before data if required) ~ 1) AX CX OX BX SP BP SI 01 8-BII (w ~ 000 001 010 011 100 101 110 111 AL CL OL BL AH CH OH eH 0) Segment 00 ES 01 CS 10 SS 11 OS Instructions which reference the flag register fite as a 16-bit object use the symbol FLAGS to represent the file: FLAGS '"except If mod.,. 00 and rIm" 110 then EA" disp-high: dlsp-Iow. ~ X:XX:X:(OF):IOF):IIFI:ITf):ISFIIZF):X:IAF):X:tpFIXICFI Mnemonics 'c' Intei, 1978 Table 4. 8086 Instruction Set Summary SPECIFICATIONS Addressing Central Processor ROM - FEOOO-FFFFF RAM - 0-7FF (800-FFF available with additional 2142's) CPU - 8086 (5 MHz clock rate) Note May be operated at 2.5 MHz or 5 MHz, iumper selectable, for use with 8086. Note The wire-wrap area of the SDK·86 PC board may be used lor additional custom memory expansion_ Input/Output Memory Parallel - 48 lines (two 8255A's) Serial - RS232 or current loop (8251A) Baud Rate - selectable from 110 to 4800 baud ROM - 8K bytes 2316/2716 RAM - 2K bytes (expandable to 4K bytes) 2142 16-11 AFN-Ol012A SDK·B6 Interfaces Electrical Characteristics Bus - All signals TTL compatible Parallel 110 - All signals TTL compatible Serial 110 - 20 mA current loop TTY or RS232 DC Power Requirement (Power supply not included in kit) Note The user has access to all bus signals which enable him to design custom system expansions into the kit's wire-wrap area. Voltage 3.5A VTTy-12V± 10% O.3A Interrupts (256 vectored) Maskable Non·maskable TRAP (VTTY required only -'if teletype is connected) Environmental Characteristics Operating Temperature - 0-50 'C DMA Hold Request input. Current VCC5V± 5% Jumper selectable. TTL compatible Reference Manuals Software System Monitor - Preprogrammed 2716 or 2316 ROMs Addresses - FEOOO-FFFFF Monitor 110 - Keyboard/display or TTY or CRT (serial I/O) . Physical Characteristics Width - 13.5 in. (34.3 cm) Height - 12 in. (30.5 cm) Depth - 1.75 in. (4.45 cm) Weight - approx. 24 oz. (3.3 kg) 9800697A SDK·86 MCS·86 System Design Kit Assembly Manual 9800722 - MCS·86 User's Manual 9800640A - 8086 Assembly Language Programming Manual 8086 Assembly Language Reference Card Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. ORDERING INFORMATION Part Number Description SDK·86 MCS·86 system design kit 16·12 =- inter SDK-C86 MCS-86™ SYSTEM DESIGN KIT SOFTWARE AND CABLE INTERFACE TO INTELLEC® DEVELOPMENT SYSTEM • Provides the Software and Hardware Communications Link Between an Intellec® Development System and the SDK-86 • Enhances and Extends the Power and Usefulness of the SDK-86 • Intellec® System Files can be Accessed and Down-Loaded to the SDK-86 Resident Memory • Allows the SDK-86 to Become an Execution Vehicle for ISIS-II Developed 8086 Object Code Using the Series II 8086/8088 Software Development Packages • Data in SDK-86 Memory can be Uploaded and Saved in Intellec® System Files • All SDK-86 Serial Port Mode Commands Become Available at Console of the Intellec® System The SDK-C86 product provides the software and hardware link for using the SDK-86 monitor in conjunction with an Intellec® Development System while adding features of data transfer between SDK-86 memory and Intellec® System files. The user may enter programs and data into the SDK-86 and then save them on a diskette. Also, programs and data may be created on the IntelleC® System using the Series 118086/8088 Software Development Packages, then loaded into the SDK-86 for testing and checkout. This provides a real time execution environment of the SDK-86 as a peripheral to the Intellec® System. 16-13 -= L:..::..... •. O ._ SDK-C86 HARDWARE • Upload/Download: In this mode the SDK-C86 software, in the Intellec®, recognizes the mnemonic for Upload or Download from the terminal. It "translates" the Download command to an R (Read hexadecimal tapel command and the Upload command to a W (Write hexadecimal tape). The Rand W commands are then passed on to the SDK-86 monitor. Using these paper tape commands allows for a checksummed transfer of data between the Intellec® and the SDK-86 memory. There are two serial ports on the Intellec® System back panel, TTY and CRT. Assuming that one of the ports is used for the Intellec® console, the SDK-C86 cable can plug into the unused port. The SDK-86 is jumper selectable to accept either the CRT (RS232) or TTY (20mA current loop I signals. The edge connector on the SDK-86 has the MUL TIBUS'· form factor. No signals are connected to. the fingers except the power supply traces. Therefore, the SDK-86 can plug directly into the Intellec® motherboard to obtain power while using the SDK-C86 cable as the communication link. COMMAND SUMMARY • Reset - • Execute with Breakpoint (G) Allows you to execute a user program and cause it to halt at a predetermined program step - useful for debugging. SOFTWARE Two programs must be invoked to operate in the SDK-86 slave mode. One program runs on the SDK-86, and another runs in any ISIS-II environment that includes a diskette drive. The serial I/O monitor is installed on the SDK-86 and operates as though it was talking to a terminal. The software in the I ntellec® allows the I ntellec®, with a console. device, to behave as if it were a terminal to the SDK-86. The SDK-C86 software program in the Intellec reads the console input device, then passes the character to the SDK-86 through the serial port. It also receives the characters from the SDK-86 and displays them at the console output device. Besides the basic transfer function, this program also recognizes and performs the Upload and Download functions. starts the SDK-86. monitor. • Single Step (N I - allows you to execute a user program one instruction at a time - useful for debugging. • Substitute Memory (S, SW) - allows you to examine and modify memory locations in byte or word mode. • Examine Register (X) - allows you to examine and modify the8086's register contents. • Block Move (M) --, allows you to relocate program and data portions in memory. • Input or Output (I, IW, 0, OW) -allows direct control of the SDK-86's I/O facilities in byte or word mode. • Display Memory (DI - allows you to print or display large blocks of memory information in HEX format. COMMAND MODES • Transparent: In this mode, the SDK-C86 software passes all characters through without any processing. All the commands of the SDK-86 monitor (except paper tape commands) are available and will function in exactly the same manner as if the terminal were attached directly to the serial port of the SDK-86. • Load IL) - allows you to load hex format object files into SDK-86 memory from an Intellec. • Transfer (T) - allows you to save contents of SDK-86 memory in a hex format object file in the Intellec. SERIAL~ PORTS CABLE ~ ,.....,..~====:::::::::::====~~ _ _ _-'-~ INTELLEC® DEVELOPMENT SYSTEM G",,,,m SDK-86/lnlellec® Slave Mode Configuration 16·14 =- - SERIAL PORT SDK-86 MCS-48™ Development Systems 17 MCS·48 DISKETTE·BASED SOFTWARE SUPPORT PACKAGE Extends Intellec microcomputer development system to support MCS-48 development Takes advantage of powerful ISIS-II file handling and storage capabilities MCS-48 assembler provides conditional assembly and macro capability Provides assembler output in standard Intel hex format The MCS·48 assembler translates symbolic 8048 assembly language instructions into the appropriate machine opera· tion codes, and provides both conditional and macroassembler programming. Output may be loaded either to an ICE·49 module for debugging or into a Universal PROM Programmer for 8748 PROM programming. The MCS·48 assembler operates under the ISIS·II operati.ng system on Intellec Microcomputer Development systems. 17-1 MCS·48™ DISKETTE·BASED SOFTWARE SUPPORT PACKAGE FUNCTIONAL DESCRIPTION ISIS.II 6048 MACROASSEMBLER, VI ,0 LOC The MCS-48 assembler. translates symbolic 8048 assembly language instructions into the appropriate machine operation codes. The ability to refer to program addresses with symbolic names eliminates the errors of hand translation and makes it easier to modify programs when adding or deleting instructions. Conditional assembly permits the programmer to specify which portions of the master source document should be included or deleted in variations on a basic system deSign, such as the code required to handle optional external devices. Macro capability allows the programmer use of a single label to define a routine. The MCS-48 assembler will assemble the code required by the reserved routine whenever the macro label is inserted in the text. Output from the assembler is in standard Intel hex format. It may be either loaded directly to an in-circuit emulator (ICE-49) module for integrated hardware/software debugging, or loaded into a Universal PROM Programmer for 8748 PROM programming. A sample assembly listing is shown in Table 1. Q8J 1 2 ;DECIMAL ADDITION ROUTINE, ADD BCD NUMBER ;AT LOCATION 'BETA' TO BCD NUMBER AT 'ALPHA' WITH 3 ,RESULT IN 'ALPHA: LENGTH OF NUMBER IS 'COUNT' DIGIT 4 5 6 7 ;PAIRS. (ASSUME BOTH BETA AND ALPHA ARE SAME LENGTH :AND HAVE EVEN NUMBER OF DIGITS OR MSD IS 0 IF :000) AUGNQ,ADONQ,CNT INIT RO, UUGND 8 9 "" :; OO"'E 0028 0032 0100 0102 0104 R2 .• CNT ALPHA EOU 14 BETA Eau 15 COUNT EQU "" B81E 8928 ,,. " £JA32 010697 22 0107 FO 010871 010957 OIDA 0108 OlOG R1, ~AODND U' Al 18 19 10CH ALPHA, BETA. COUNT RO.8ALPHA Al,8BETA R2,IICOUNT LP C A,@RO "" " A,@Al A 28 R2. LP 28 " 0100 EAD7 30 ," @RO,A "" USER SYMBOLS ALPHA ~OOlE Ll 0102 ASSEMBLY COMPLETE. NO ERRORS ISIS-II ASSEMBLER SYMBOL CROSS REFERENCE. V, 0 ALPHA 13_ BETA 10 COUNT 158 1NIT 7~ L1 '9~ LP 22~ 17 17 17 17 28 Table 1. Sample MCS-48 Diskette·Based Assembly Listing SPECI FICATlONS Shipping Media Operating Environment Diskette Required Hardware Intellec Microcomputer Development System 32K RAM (non-macro use) 48K RAM (use of macro facility) One or two Floppy disk drives - Single or Double density System Console - CRT or interactive.hardcopy device Reference Manuals 9800255 - MCS-48 and UPI-41 Assembly Language Programming Manual (SUPPLIED) Required Software ISIS-II Diskette Operating System 9800236 - Universal PROM Mapper Operator's Manual 9800306 - ISIS-II User's Guide Reference manuals are shipped with each product only if .designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051. Optional Hardware ICE-49 In-Circuit Emulator Line Printer Universal PROM Programmer with 8748 personality card ORDERING INFORMATION Product Code Description MDS-D48 Diskette-based assembler for MCS-48 family .of microprocessors. 17-2 00819A ICE·49 MCS·48 IN·CIRCUIT EMULATOR Emulates 8049, 8048, 8748, 8039, 8035, and 8021* MIcrocomputers Extends Intellec microcomputer develop· ment system debug power to user con· figured system via external cable and 40·pin plug, replacing system MCS·48 device Emulates user system MCS·48 device in real time . Eliminates need for extraneous debug· ging tools residing in user system Collects bus, register, and MCS·48 status information on instructions emulated Shares static RAM memory with user system for program debug Provides capability to examine and alter MCS·48 registers, memory, and flag values, and to examine pin and port values Provides hardware comparators for user designated break conditions Integrates hardware and software efforts early to save development time The ICE·49 MCS·48 In·Circuit Emulator module is an Intellec·resident module that interfaces with any MCS·48 system. The MCS·48 family consists of the 8049, 8048, 8748, 8039, 8035, and 8021 microcomputers. The ICE·49 module inter· faces with an MCS·48 system through a cable terminating in an MCS·48 pin·compatible plug which replaces the MCS·48 device in the sytem. With the ICE·49 plug in place, the designer has the capability to execute the system in. real time while collecting up to 255 instruction cycles of real·time trace data. In addition, he can single step the system program to monitor more closely the program logic during execution. Static RAM memory is available through the ICE·49 module to emulate MCS·48. program and data memory. The designer can display and alter the contents of data and replacement RAM control memory, internal MCS·48 registers and flags and I/O ports. Powerful debug capability is extended into the MCS·48 system while ICE·49 debug hardware and software remain inside the Intellec system. Sym· bolic reference capability allows the designer to use meaningful symbols rather than absolute values when examining and modifying memory, registers, flags, and I/O ports in this system. *EM1 emulator board is also required. 17·3 AFN·Ol103A·Ol ICE·49 FUNCTIONAL DESCRIPTION Integrated Hardware/Software Development The user prototype need consist of no more than an MCS·48 socket and timing logic to begin integration of software and hardware development efforts. Through the ICE·49 module mapping capabilities, Intellec system resources can be accessed to replace prototype memo ory. Hardware designs can be tested using the system software to drive the final product. Thus, the system in· tegration phase, which can be costly when attempting to mesh completed hardware and software products, becomes a convenient two·way debug tool when begun early in the design cycle. Debug Capability Inside User System The ICE·49 module provides the user with the ability to debug a full prototype or production system without introducing extraneous hardware or software test tools. The module connects to the user system through the socket provided for the MCS·48 device in the user system. Intellec memory is used for the execution of the ICE·49 software. The Intellec console and file handling capabilities provide the designer with the ability to com· municate with the ICE·49 module and display informa· tion on the operation of the prototype system. The ICE·49 module block diagram is shown in Figure 1. Real· Time Trace The ICE·49 module captures trace information while the designer is executing programs in real time. The instruc· tions executed, program counter, port values for bus 0, port 1 and port 2, and the values of selected MCS·48 status lines are stored for the last 255 instruction cycles executed. When retrieved for display, code is disassem· bled for user convenience. This provides data for deter· mining how the user system was reacting prior to emu· lation break, and is available whether the break was user initiated or the result of an error condition. For more detailed information on the actions of internal registers, flags, or other system operations, the user may operate in single or multiple step sequences tailored to system debug needs. Batch Testing In conjunction with the ISIS·II diskette operating system, 'the ICE·49 module can run extensive system diagnostics without operator intervention. The designer or test engineer can define a complete diagnostic exer· cise, which is stored in a file on the diskette. When actio vated with an ISIS·II submit command, this file can instruct the ICE·49 module to execute the diagnostic routine and store the results in another file on the diskette. Results are available to the designer at his con· venience. In this way, routine diagnostics and long term testing may be done without tying up valuable man· power. ----"-- ----------,I EMULATOR BOARD USER SOCKET I I SYNC 0 --- CONTROL PROCESSOR BOARD II r-~~~JI~-----~ II ~--~~~' I I CONTROL PROGRAM 8080 CONTROL PROCESSOR P1 P2A 8049 OR 8048 W/INTERNAL MONITORP~~r-_ _ _ _ _ _~~_~ I I I I I I I INTERNAL TIMER II II I I I I I II II II CABLE BUFFER SYNC 1 ' L __ _ I w ~ I ~ I ~ I ~ I ...~ I ~ I I I II I _'- _____ -.J L____________ .-J Figure 1. ICE·49 Module Block Diagram 17·4 AFN-Ol103A-02 ICE·49 Memory Mapping The 8049, 8748 and 8048 contain Internal program and data memory. Both program and data memory can be expanded using external memory devices. Internal Memory - When the MCS·48 microcomputer is replaced by the ICE·49 socket in a system, the ICE·49 module supplies static RAM memory as a replacement for the Internal microcomputer memory. The ICE-49 module has enough RAM memory available to emulate up to the total 4K control memory capability of the system. The ICE·49 module also provides for up to 384 bytes of data memory. External Memory - The ICE-49 module separates replacement control memory into sixteen 256·byte blocks. Replacement external data memory consists of one 256-byte block. Each block of memory can be de· fined separately as supplied by the user system or supplied by the ICE-49 module. The user may assign ICE·49 equivalent memory to take the place of external memory not yet supplied in his system. Symbolic· Debugging ICE·49 software provides symbolic definition of all MCS-48 registers, flags, and selected MCS-48 pins. Symbolically defined pseudo registers provide access to the sense of MCS-48 flip flops which enable time, counter, interrupt, and flag-0Illag·1 options. In addition, the user may reference locations in program and data memory, or their contents, symbolically. The user sym· bol table generated along with the object file during a program assembly may be loaded to Intellec memory for access during emulation. The user is encouraged to add to this symbol table any additional symbolic values for memory addresses, constants, or variables he may find useful during system debugging. Symbols may be substituted for numeric values in any of the ICE·49 com· mands. Symbolic reference is a great advantage to the system designer. He is no longer burdened with the need to recall or look up those addresses of key loca· tions in his program that can change with each assembly. Meaningful symbols from his source program may be used instead. For example, the command: GO FROM .START TILL XDATA. RSLT WRITTEN begins execution of the program at the address refer· enced by the label START in the designers assembly program. A breakpoint is set to occur the first time the microprocessor writes to the external data memory location referenced by RSLT. The designer does not have to be concerned with the physical locations of START and RSLT. The ICE-49 software driver supplies them automatically from information stored in the symbol table. Intel 8080 to communicate with the Intellec host pro· cessor via a common memory space. The 8080 also con· trois an internallCE·49 bus for intramodule communication. ICE·49 hardware consists of two PC boards, the controller board, and the emulator board, all of which reside in the Intellec chassis. A cable interfaces the ICE·49 boards to the MCS·48 system. The cable ter· minates in a MCS-48 pin compatible plug which replaces any MCS·48 device in the user system. The ICE·49 module block diagram is shown in Figure 1. Real· Time Trace Trace Buffer - While the ICE·49 module is executing the user program, it is monitoring port, program counter, data, and status lines. Values for each instruc· tion cycle executed are stored in a 255 x 44real·time RAM trace buffer. A resetable timer resident on the controller board counts instruction cycles. Controller Board The ICE-49 module talks to the Intellec system as a peripheral device. The controller board receives commands from the Intellec system and responds through the parameter block. Three 15·bit hardware breakpoint registers are available for loading by the user. While in emulation mode, a hardware comparator is constantly monitoring address and status lines for a match to ter· minate an emulation. The breakpoint registers provide a signal when a match is detected. The user may disable the emulation break capability and use the signal to syn· chronize other debug tools. The controller board returns real-time trace data, MCS·48 register, flag, and pin values, andlCE·49 status information, to a control block in the Intellec system when emulation is terminated. This information is available to the user through the ICE-49 interrogation commands. Error conditions, when present, are automatically displayed on the Intellec system console. The controller board also contai ns static RAM memory, which can be used to emulate MCS·48 program and data memory in real time. 4K of memory is available in sixteen 256·byte pages to emulate MCS-48 PROM or PROM program memory. A 256byte page of data memory is available to access in place of MCS·48 external data memory. The controller board address map directs the ICE·49 module to access either replacement ICE·49 memory or actual user system ex· ternal memory in 256·byte segments based on informa· tion provided by the user. Emulator Board The emulator board contains the 8049* and peripheral logic required to emulate the MCS·48 device in the user system. A software selectable 6 MHz or 3 MHz clock drives the emulated MCS·48 device. This clock can be disabled and replaced with a user supplied TTL clock in the user system. Hardware The ICE·49 module is a microcomputer system utilizing Intel's 8049 or 8048/8748 microcomputer as its nucleus. The 8049 provides the 8049, 8039 emulation character· istics. The 8048/8748 provides the 8748/8048/8035/8021 emulation characteristics. The ICE·49 module uses an 17-5 'Use 8048 with internal monitor program when emulating 8748180481 803518021. AFN-01103A-03 ICE·49 Cable Card The cable card Is Included for cable driving. It transmits address and data, bus information to the user system through a 40-pin connector which plugs into the user system in the socket designed forJhe MCS-48 device. Command Operation' Display Prints contents of memorY, MCS-48 device registers, 1/0 ports, flags; pins, real-time trace data, symbol table, or other diagnostic data on list device. Alters' contents, of memory, register, outp'ut port, or flag. Sets or alters breakpOints and display registers. Defines memory 'status. Establishes mode of display for output data. Establishes mode of display input data., Change Software The ICE-49 software driver Is a RAM-based program which provides the user with an easy to use command language (see Table 1, Table 2, and Table 3) for defining breakpoints, Initiating real-time emulation or single step operation, and Interrogating and altering user system status recorded during emulation. The ICE-49 command language contains a broad range of modifiers to provide the user with maximum flexibility In defining the operation to be performed. The ICE-49 software driver is available on diskette and operates In 32K of Intellec RAM memory. Command Enable Go Step Interrupt Map Base Suffix Table 2_ ICE-49 Interrogation Commands Command Load Save Operation Activates breakpoint and display regls-, ters for. use with go and step commands. Initiates real-time emulation and allows user to specify breakpoints and data retrieval. Initiates emulationin single instruction Increments. Each step Is followed by register dump. User may optionally tailor other diagnostic activity to his needs. Emulates user system Interrupt. Define Move List Exit Evaluate Remove Reset Table 1. ICE-49 Emulation Commands Operation Fetches user symbol table and object code from input device. Sends user symbol table and object code to output device. Enters symbol name an,d value to user symbol table. Moves block 'of memory data to another area of memory. Defines list device. Returns program control to ISIS-II. Converts expression to equivalent values in binary, octal, decimal, and hex. Deletes symbols from symbol table. Reinltlallzes IC,E-49 hardware. Table 3_ ICE-49 Utility Commands SPECIFICATIONS System Clock ICE·49 Operating Environment Crystal controlled 6.0 MHz internal, 3.0 MHZ: internal or user supplied TIL external: software selectable: Required Hardware Intellec microcomputer development system .' System console Intellec diskette operating system ICE-49 Module Required Software System monitor ISIS-II Equipment Supplied Printed circuit boards (control board, emulator board) Interface cables and buffer module iCE-49 software, diskette-based version (single density or double density) 8048 with Internal monitor program Physical Characteristics Width Height Depth Weight - 12.00 in. (30.48 cm) 6.75 in. (17.15 cm) 0.50 In. (1.27 cm) 8.00 lb. (3.64 kg) Electrical, Characteristics DC Power Requirements Vcc = +5V :1:5% Icc = 10A max; 7.0A typ Voo +12V :1:5% 100 = 79.mA max; 45 mA typ Vee -10V :1:5% lee 20 mA max = = = 17-6 AFN-Oll03A-04 HSE·49 HIGH·SPEED EMULATOR • Single-board execution and debugging vehicle with integral keypad and display • Real-time 11 MHz emulation of user system • System monitor firmware in ROM • Breakpoints on user program and external data addresses • Wire-wrap area for prototyping • Examine and alter MCS® -48 registers, memory and status values • Intellec®..system compatible power pick-up card and serial-link cable • No-break triggering of oscilloscope or logic analyzer The HSE-49™ emulator is a fully-assembled stand-alone development tool with on-board 33-key keypad, 8-character display, two 8039 mlcrocontrollers, 2K bytes of user-program RAM, a serial port and cable, and a ROM-based monitor which supervises ttie emulator operation and user interface. The emulator provides a means for executing and debugging programs for the 8048/8049 family of microcontrollers at speeds up to 11 MHz. It interfaces to a user~designed system through an emulation cable and 40-pin plug, which replaces the MCS-48™device in the user's system. Using the HSE-49 keypad, a designer can run programs in real-time or single-step modes, set up to 8000 breakpoint flags, and display or change the contents of user program memory, internal and external data memory, and internal MCS-48 hardware registers. When linked to a host Intellec® development system, the HSE-49 emulator system-debugging capabilities, with the development system program assembly and storage facilities, provide, the tools required for total product development. 17-7 HSE·49 HIGH·SPEED EMULATOR using the emulator's capabilities to break emulation and to examine and change the user program and processor status values. The completed system may be final tested prior to ROM-code entry by replacing the HSE-49 emulation plug with a programmed 874X device in the user-system MCS-48 device socket, and running the system (with crystal input and power supplied) at full speed. Figure 1 shows a typical development configuration utilizing a host Intellec development system and the HSE-49 emulator, with the emulation cable interface to a user-designed system. For enhanced system debugging capabilities the designer may elect to use Intel's ICE-49™ incircuit emulator. The ICE-49 module permits realtime emulation of the user system up to 6 MHz, and offers the added benefits of symbolic debugging, 255 instruction-cycle real-time trace, and full emulation without the stack, interrupt or I/O limitations to which the HSE-49 emulator is sLibject (see discussion under "Limitations" heading). For further information on the ICE-49 emulator, refer to the ICE-49™ In-Circuit Emulator Data Sheet (order number 305200). FUNCTIONAL DESCRIPTION The HSE-49 High-Speed Emulator Is a stand-alone execution and debugging tool for 8048/8049 family microcontroller-based systems which are designed to run at speeds up to 11 MHz. It may be used alone or with other Intel microcomputer development system products to facilitate system int!lgration early in the product development cycle, in parallel with hardware and software development. The convenient two-way debugging which early integration permits results in reduced total development time and cost. System Development SOFTWARE DEVELOPMENT After an application program has been written In MCS-48 assembly language, the HSE-49 emulator may be used to debug software even if prototype hardware is not yet available. Stand-alone Mode The designer first hand assembles the source code from ASM-48 mnemonics into hex code, and then loads the program Into the HSE-49 emulator user-program RAM through the on-board hex keypad, or through the serial port from a hex file stored on a user-supplied peripheral device. The emulator may then be used to execute the user program in a variety of debugging modes, and to alter the program as necessary. The altered program may then be uploaded to a user-supplied storage device. Development System Mode With an Intellec development system, the designer assembles the source code using the MCS-48 macroassembler and. downloads the resulting hex file through the serial port and cable to the HSE-49 emulator user-program RAM. The emulator Is then used to execute and debug the program as above. Finally, the resulting program is uploaded to the development system and stored in a disk file. Figure 1_ Intellec®. System Based HSE-49 Emulator Connected to User Prototype System . Emulator Overview EMULATION AND MASTER PROCESSORS The user's program is emulated by an 8039 microprocessor, the emulation processor (EP), which executes code that is stored in 2K bytes of external RAM for ease of prog-ram development. Additional RAM may be added by the user in the provided sockets to expand program and external data memory to 4K bytes each. HARDWARE/SOFTWARE INTEGRATION Prototype hardware may be developed off-board or on the wire-wrap area provided on the HSE-49 emulator board. The HSE-49 emulator interfaces to the user-system hardware through the supplied emulation cable, which plugs Into the MCS-48 device socket in the user system. With the plug In place, the emulator executes code from the userprogram memory ahd exercises the prototype hardware. Additional hardware is added as it becomes available, and the system is debugged A second microcontroller - an 8039 with off-cHip ROM program memory - is used to scan the onboard keypad and display, interpret and imp Ie17-8 AFN·0165BA inter HSE·49 HIGH·SPEED EMULATOR USER SYSTEM PROTOTYPE D Figure 2. HSE·49 Figure 3. HSE·49 Emulator Signal Flow Diagram Emulator Command Keypad Organization ment commands, drive serial interfaces, etc. In general, this master processor (MP) is used to in· terface the emulatiori processor's memory spaces with the outside world and control the operation of the EP. Figure 2 shows how the two processors interrelate with the rest of the system. Figure 3 shows the layout of the 33-key keypad through which the user interfaces to the emulator. data RAM, accumulator, PSW, PC, timer/counter, working registers, and internal RAM; executing the user's program ·fromarbitrary addresses in var· ious debugging modes; and uploading or down· loading object or data files from diskettes using a host development system. No special software is needed for the Intellec system other than ISIS II Version 3.4 or later. The data format is compatible with the standard Intel hex file format produced by ASM·48; the baud rate may be altered from 110 baud (default state) up to 1200 baud from the on· board keypad. Blocks of data may be transmitted to a CRT or printer and displayed in a tabular for· mat. MP MONITOR The monitor program executed by the MP in· cludes commarids for filling, reading, or writing the various memory spaces, including theexecu· tion processor's program RAM, external ("MOVX") 17-9 ,......... .... AFN-01656A HSE·49HIGH·SPEED EMULATOR INTERPROCESSOR COMMUNICATION An 8212 8-bit latch is used to communicate data and commands between the master and emulation processors. Under control of the MP, this register, call the "Link" register, may be logically mapped into either the program or data RAM address spaces. When this is done, the RAM in the respective memory space is disabled and the link responds to all accesses regardless of address. When the M P detects that the EP has been halted by the breakpoint hardware, or when the operator presses a key while the program is executing, the program break sequence is initiated. The loworder 23 bytes of user-program memory is read into a buffer within the internal RAM of the MP. A short program· for reading .and transmitting internal EP status is written into the low-order userprogram memory. (This is one of several "minimonitors" overlayed on the user-program area.) The link register is mapped logically into the userprogram memory, and loaded with the 8049 machine code for a "CALL" instruction to the minimonitor program area. The EP is then allowed to fetch a single instruction from the link, forcing the "CALL" to the mini-monitor onto the EP data bus. The link register is then mapped to the external data RAM address space. A block diagram of the system at this point is shown in Figure 4. From this point on, the EP executes code contained in the mini-monitor which makes the EP accumulator, timer/counter and PSW values available to the MP (through "MOVX" instructions to the link register) so that the EP internal status may be saved in the .MP internal data RAM. The MP then loads a different mini-monitor into the same EP program RAM area which allows it to read and save the internal RAM of the EP. At this point, the HSE-49 emulator may be interro' gated or given instructions by the operator from the hex keypad. The emulator operation remains transparent to the user, who need not be concerned, for example, with the actual (altered) location of the EP low-order program RAM or internal data RAM. In order to resume. user-program execution, a status restoration mini-monitor is overlayed. This rel?tores th.e EPinternal status using a scheme analogous to the one in which the status was originally saved. Th,e final step of the last mini-monitor is an "RETR" instruction, after which the EP is again halted. The low-order program memory saved earlier is rewritten into the appropriate area, the break logic is configured for the desired exe- cution mode, and the EP is released to run at full speed until the next break situation is encountered. Operation Modes The HSE-49 firmware is a ROM-based program that provides the user with simple key-stroke commands for initiating emulation, defining break-. points, and displaying and controlling system parameters. A summary of the HSE-49 emulator commands is given in Table 1. SIX EMULATION MODES are provided by the HSE-49 emulator to aid in hardware and software debugging. The user may single-step through a program or have the emulator automatically step through the program with a user-defined idle time between steps. Three real-time emulation commands allow 1) real-time emulation with breakpoints not enabled (a user-accessible pulse is generated each time a breakpoint is encountered, however, facilitating user-defined logic analysis), 2) real-time emulation with breakpoints enabled, and 3) real-time emulation with automatic breakpointing, whereby the emulator executes in real time between breakpoints, and pauses at each breakpoint for a user-defined time before automatically reSuming real-time emulation. A final command initiates real-time execution, beginning emulation at user-program location OOOH, from the Emulator Processor hardware reset state. BREAKPOINTS may be set at any combination of program memory and external data memory address locations from OOOH to FFFH. This unlimited capability to specify breakpoints for all possible combinations' of addresses complements the somewhat different breakpointing features available with the ICE-49 emulator. The ICE-49 emulator permits the symbolic specification of breakpoints on program memqry and external data memory addresses, or external data memory address reads or writes individually, and upon the input of an external synchronization signal. ., , INTERROGATION AND UTILITY.commands are provided by the HSE-49 emulator which allow the user to examine, change or fill the various emulator memory spaces. Additional commands are provided to upload or download the contents of the memory spaces to or from a hostlntellec de-, velopment system, or .. other peripheral device, through the HSE-49 emulator serial port. 17-10 c...• ~ AFN·0165BA HSE·49 HIGH·SPEED EMULATOR EXECUTION PROCESSOR MASTER PROCESSOR Figure 4. Communication between EP and MP Table 1. HSE·49 Emulator Command Description COmmand Modifier Command Description Begins emulation: GO NO BRK Real·time breakpoints not enabled W/BRK Real·time breakpoints enabled SING STP Steps program one instruction AUTO STP Automatically steps/pauses/steps/... AUTO BRK Automatically emulates real·time/pauses at breakpoint/emulates real· time/ ... GO/RESET (NONE) Begins real·time emulation from EP hardware reset state, beginning at program location OOOH B,C (PROG MEM, DATA MEM) Sets (B) or Clears (C) breakpoint at specified address within Program or External Data memory SYS RST (NONE) Resets emulation and master processors and clears all breakpoints · EXAM/CHA · ·· · FILL LIST DNLOAD UPLOAD PROG MEM · Examine/Change memory location Fill range of memory addresses with a single data value List memory to output device through HSE·49 serial port Download hex·file format memory to HSE-49 emulator through HSE·49 serial port Upload memory within a range of addresses through HSE-49 serial port to Intellec Development System or external peripheral device • = Memory types allowed for above commands: User-program memory DATA MEM External data memory (if installed) PROG BRK User-program breakpoint memory DATA BRK External data breakpoint memory REGISTER Register memory and internal data memory HARD REG Hardware registers/system control parameters 17-11 AFN·0165BA inter HSE·49 HIGH·SPEED EMULATOR dress within an interrupt servicing routine; if it is, the EP may incorrectly recognize an interrupt request which should be ignored. Limitations The HSE-49 emulator was not designed to have the same capabilities that Intel's ICE7M in-circuit emulators have, and certain features have been deleted to keep the circuitry relatively simple. As a result, the following limitations exist and should be taken into account when using the system. 1. As explained previously, user-program execution is terminated by forcing the EP to execute a "CALL" instruction to the mini-monitor. Because this requires one level of the EP subroutine stack, the user program can be using a maximum of seven levels of stack when a break is initiated. 2. Because program execution is initiated by forcing the EP to execute an "RETR" instruction, the EP interrupt-in-progress flip-flop will be cleared. Therefore, if interrupts are enabled, emulation should not be resumed from an ad- 3. The 110 status of ports PO and P22-P23 with respect to user-supplied hardware is determined by the HSE-49 emulator hardware configuration rather than by software. Therefore the 110 modes of these ports may not be altered while a program is executing. These ports may be configured as is inputs, latched outputs or bidirectional ports by changing socketed HSE-49 emulator hardware. 4. The "ANL BUS, #nn" and "ORLBUS, #nn" instructions may not be used in the user program, as external hardware cannot properly restore these functions. Several other minor limitations with the HSE-49 emulator operation are explained in the Operating Instructions. SPECIFICATIONS Physical Characteristics Equipment Supplied Width: 14.0 in (35.6 cm) Length: 10.0 in. (25.4 cm) Height: 0.5 in. (1.27 cm) Packaged Weight: 4.0 Ib (1.8 kg) Printed Circuit Board with Integral Keypad, Display, ROM Monitor, (2) 8039 microprocessors and 2K bytes user program RAM Emulation Cable and Plug Serial-Link Cable Power Pick-up Card with Cable Power Cable D.C. Electrical Characteristics vcc = +5V ±5% Icc =2.0A max; 1.5A typical VRS232= + 12V ± 5%; -12V ±.5% IRS232 = 0.020A max; 0.015A typical (VRS232 required only if using RS232 mode of serial port) Emulation Clock 11 MHz supplied, or user supplied crystal for 3.6 MHz to 11 MHz clock Environmental Characteristics Operating Temperature: 0° to 55°C Serial 110 Operating Humidity: Up to 90% relative humidity without condensation 20 mA Current Loop or RS232 (jumper selectable) ORDERING INFORMATION Part Number Description MCI-49-HSE 8048/8049 family CPU high- speed (11 MHz) emulator, cable assembly and ROM firmware 17-12 EM1 8021 EMULATION BOARD EPROM functional equivalent of 8021 single component 8·bit microcomputer Based on 8748 - user programmablel erasable EPROM 8·bit computer Operates with ICE·49™ module to provide full in·circuit debugging of 8021 prototype system Connects to prototype system through 8021 pin compatible plug On·card 3.0 MHz or external TTL driven clock Portable 4" x 7" microcomputer circuit assembly The EM1 emulator board is a ready-to-use 4" x 7" microcomputer circuit assembly that emulates the Intel 8021 microcomputer_ A 12-inch flat-cable assembly connects the board to the 8021 socket in a prototype system. The board is designed so that it can be mounted either as a stand-alone unit, or within the prototype assembly. The 8021 microcomputer has 1K x 8 mask-programmable ROM program memory and 64 by 8 RAM data memory. The EM1 is controlled by an Intel 8748, with 1K of EPROM program memory and a 64 byte data memory. The EPROM can be programmed and erased repeatedly during hardware and software development. The EM1 has several ancillary circuits that perform the following functions which are specific to the 8021: Zero crossing detector Crystal controlled clock/buffer Port 0 simulator For prototype debugging, the 8748 cali be removed from its socket and replaced with a cable to an ICE-49 module. When used with the EM1,ICE-49 module emulates the 8021 in real-time, or single-steps the 8021 program at the user's command. A full range of capabilities for examining and modifying 8021 memory and status are supplied through ICE-49 module. 17-13 AFN-OOB01A-01 EM1 Zero Cross Detection Simulator HARDWARE The EM1 emulation board uses the 8748 to perform the emulation. PO Simulator Port 0 of the 8021 is a quasl*-bldlrectional port. The PO simulator converts the data bus of the 8748 into a quasibidirectional port. Crystal Control Clock Buffer The EM1 allows user to select an on-board oscillator ora TTL clock driven from the 8021 user's prototype system via a Cambion Suitcase jumper. Jumper W1 Position State A-B On-Board External TTL Clock C-D *A bidirectional port which serves as an input port, output port, or both even though outputs are statically latched. . . The zero cross detection simulator enables the 8748's T1 Input to detect zero-crossings. The circuitry provides a high level signal on a positive crossing and a low level signal on a negative crossing of zero to the T1 Input of the 8748. Reset Buffer The 8021 resets on a logic HIGH level signal. However, the 8748 resets on a logic LOW level, thus an inverter is provided on the EM1 to make the two chips compatible. Optional Pull·Ups Resistors are provided to simulate the optional pull-up resistors on T11nput and Port 0 of the 8021. A removable resistor pack is used on Port O. The T1 Input pull up can be installed by soldering in a50K resistor. Software .. . When emulating the 8021 with EM1, the user must observe the 8021 Instruction set. r- - - - , I OPTIONAL I LPULL~...J DB0- DB7 P10 - P17 P20- P28 ALE 8748 OR 40·PIN PLUG 40 LINES 8021 CABLE PLUG PROG CABLE TO ICE-49 MODULE 12 INCHES FLAT CABLE XTAL1 T1r-~------'------; r--------------,--;T1 RESET t---,.......;--~------'--'----------'---_o< r - - - - - t - - - f RESET RESET BUFFER r I 28 LINES I r--..., O'NCIAiiD'" CLOCK· 28·PIN SOCKET IL o~~~~~u~L _ _ ....JI I L2!:!I~ ~ 17·14 AFN-oDS01A-02 EM1 SPECIFICATIONS Operating Environment Stand·Alone Required Hardware: EM1 emulation board In·Circuit Emulation Required Hardware: EM1 emulation board Intellec Microcomputer Development System con· figurated with ICE-49 module Equipment Supplied System Clock Crystal controlled 3.0 MHz on board or user supplied TTL external clock: hardware jumper selectable. Physical Characteristics Width: 7.0 in (17.78 cm) Height: 4.0 in. (10.16 cm) Depth: 0.75 in. (1.91 cm) Weight: < 1.0 Ibs. (0.45 kg) Electrical Characteristics DC Power: Vcc5V ±5% Icc 300 mA (max.) EM1 printed circuit board Environmental Characteristics 12" long flat cable terminating in 28-pin plug, pin com· patible with 8021 Operating Temperature: 0 - EM1 Operator's Manual 55°C Operating Humidity: up to 95% without condensation relative humidity ORDERING INFORMATION PART NUMBER Description MDS·EM1 8021 Emulation Board 17-15 AFN-OOB01A-03 EM2 . 8022 EMULATION BOARD Portable 4.25" x 2.75" microcomputer circuit assembly Provides Intel® 8755A -2K )( 8 EPROM Connects directly into prototype system through Intel® 8022* pin compatible socket EPROM functional and electrical equivalent of Intel® 8022 - single component 8·bit computer ." The EM2 emulator board Is a ready-to-use-4.25" x 2.75" microcomputer circuit assembly that emulates the Intel" 8022 single chip microcomputer. The emulator board. is designed to plug directly into the 8022 socket. No interfacing and hiterconnection cables are nec;:essa,y. Power is obtained from the user's system. The EM2 emulator board provides the user a full EPROM functional and electrical equivalent of the 8022 single component 8-bit microcomputer. The EM2 emulator board consists of an Intel" 8022 emulator chip and an Intel" 8755A, providing the EM2 emulator board with a 2K x 8 EPROM program memory which can be programmed and erased repeatedly during hardware and . software development. The 8022E emulator chip is a modified version of the 8022 intended for use in design support systems; Instead of using resident ROM memory as the 8022, the 8022E uses an external 2K EPROM 8755A memory. for program storage; allowing easy program modification. ' ·See IntelO 8022 Data Sheet. EM2 EM2 BLOCK DIAGRAM 40·PIN SOCKET CONFIGURATION P2B Vee P27 P25 AVec P24 PROG VAREF P23 ANl ANa P22 AVss P21 TO P20 VTH P17 POO P16 pal P15 P02 P14 P03 P13 P04 P12 P05 Pll POB Pl0 P07 RESET ALE XTAL2 Tl XTALl vss SUSST D 204B EPROM . - - - . ' MEMORY B022 EMULATOR CHIP D PIN 1 SQUARE SOLDER PAD PIN DESCRIPTION Desig· nation Pin II Deslg· nation Function Vss 20 Vee 40 + 5V circuit power supply. PROG 37 Output strobe for Intel 8243 I/O ex· pander. 9 Pin II Function RESET 24 Input used to initialize the processor by clearing status flip·flops and setting the program counter to zero. AVss 7 A/D converter GND potential. Also establishes the lower limit of the con· version range. AVec 3 AID + 5V power supply. SUBST 21 Substrate pin used with a bypass capacitor to stabilize the substrate voltage and improve AID accuracy. VAREF 4 A/D converter reference voltage. Establishes the upper limit of the conversion range. ANO, AN1 6,5 Analog inputs to AID converter. Software selectable on-Chip via SEL ANO and SEL AN1 instructions. ALE 18 Address Latch Enable. Signal occurring once every 30 Input Input clocks (once every single cycle instruction), used as an output clock. XTAL1 22 One side of crystal, Inductor, or resistor input for internal oscillator. Also input for external frequency source. (Not TTL compatible.) XTAL2 23 Other side of timing control element. This pin is not connected when an external frequency source is used. Circuit GND potential. POO-P07 10-17 8·bit open·draln port with comparator Port 0 inputs. The switching threshold is set externally by VTH • Optional pull·up resistors may be added via ROM mask selection. (The emulator board has switch selection of this option.) VTH B755A 40·PIN SOCKET Port 0 threshold reference, pin. P10-P17 25~32 8-bit quasi-bidirectional port. Port 1 P20-P27 33-36 8·bit quasi-bidirectional port. Port 2 TO T1 38-39 P20-P23 also serve as a 4-bit I/O ex1-2 pander for Intel 8243. 8 19 Interrupt input and input pin testable using the conditional transfer Instructions JTO and JNTO. Initiates an Interrupt following a low level Input if interrupt Is enabled. Interrupt Is disabled after a reset. Input pin testable using the JT1 and JNT1 conditional transfer Instructions. Can be designated the timer/event counter input using the STRT CNT Instructlon. Also serves as the zero-cross detection input to allow zero-crossover sensing of slowly moving AC inputs. Optional pull-up resistor may be added via ROM mask selection. 17·17 .0:...... .:> ~ 0.:.::::. __ •. __ AFN-00BOOA-02 EM2 On the EM2 Board: The Intel® 8755A EPROM can be programmed using any of the modules listed in Table 1. Module Description UPP·103 Universal PROM Programmer. Requires UPP·955, which in· cludes 8755A Personality Card with 40-pin adapter socket. PROMPT-48 Intellec® MCS-48 Microcomputer Design Aid. Requires PROMPT-475 Programming Adapter. The 8755A EPROM is erased when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). Sunlight and certain fluorescent lamps have wavelengths in the 3000A to 4000A range. If the 8755A is to be exposed to sunlight or room fluorescent lighting for extended periods, then opaque labels should be placed over the window to prevent unintentional erasure. Table 1_ 8755A Proramming Module The recommended erasure procedure is exposure to ultraviolet light which has a wavelength of 2537 A. The integrated dose (UV intensity multiplied by exposure time) for erasure should be a minimum of 15W-sec/cm. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,0001' W/em 2 power rating. Place the 8755A within one inch of the lamp during erasure. Some lamps include a filter which should be removed before erasure. SPECIFICATIONS Physical Characteristics PROMPT-80/85 Intellec® 8080/8085 Microcomputer Design Aid. Requires PROMPT-975 Programming Adapter. Operating Environment Intel® 8755A EPROM Programming UPP-103 PROMPT-48 PROMPT-80/85 Width: 2.75 in. (6.98 cm) Height: 4.25 in. (10.79 cm) Depth: 1.5 in. (3.81 cm) Weight: 0.5 Ib (0.23 kg) Electrical Characteristics Intellec Microcomputer Development System DC Power Vcc=5V ±5% Icc=300 mA (maximum) Software 8048 Assembler ISIS-II Diskette Operating System Environmental Characteristics Equipment Supplied Operating Temperature - 0 to 55·C EM2 Printed Circuit Board EM2 Reference Manual Operating Humidity without condensation Up to 95% relative humidity ORDERING INFORMATION Part Number Description MDS-EM2 8022 Emulation Board 17-18 AFN-00800A-03 ICE·22™ 8022 IN·CIRCUIT EMULATOR • Single·line assembler allows mnemonic program instruction changes • Full symbolic debugging • 500 instruction cycle trace conditionally triggered - 16 user·definable trace probes - symbolic groupings and display • ICE™·resident user·program RAM for real·time execution • 32·bit half·microsecond emulation timer • Examine and alter 8022 registers, memory, and digital port values, and examine analog port data • HELP facility summarizes ICE·22™ command syntax at the console • User confidence test of ICE·22™ • Two user·specified breakpoint registers hardware The ICE-22 module resides in the Intellec® Microcomputer Development System and interfaces to any user-designed 8022 system through a cable terminating in an 8022 emulator microprocessor and a pincompatible plug. The emulator processor, together with 2K bytes of user-program RAM located in the ICE-22 buffer box, replaces the 8022 device in the user system while maintaining the 8022 electrical and timing characteristics. Powerful Intellec debugging functions are thus extended into the user system. Using the ICE-22 module, the designer can emulate the system's 8022, including full AID converter function, in real-time or single-step mode. Breakpoints allow the user to stop emulation on user-specified conditions, and a trace qualifier feature allows the conditional collection of 500 instruction cycles of trace data. The ICE-22 trace includes 8022 status information and, through ICE-22 external logic probes, can provide daia on up to 16 signal nodes in the user-system peripheral circuitry. For the first time in any ICE module, the designer may alter program memory using ASM-48 mnemonics and symbolic references without returning to ISIS II control. In addition, user-created peripheral chip analyzer routines may be applied to the logic probe data, thereby expanding the in-circuit emulation function to the entire system. 17·19 intJ ICE·22™ IN·CIRCUIT EMULATOR For each symbol that is used for memory reference in an ICE-22 emulator command, the emulator supplies the symbol value location as stored In the ICE-22 emulator symbol table. This table can be loaded with the symbol table produced by the assembler during application program assembly. Furthermore, the user can interactively modify the emulator symbol table by adding new symbols or changing or deleting old ones. This feature provides great flexibility in debugging and minimizes the need to work with hexadecimal values. FUNCTIONAL DESCRIPTION Integrated Hardware/Software Development The ICE-22 emul.ator allows hardw~re and software development to proceed interactively. This is more effective than the traditional method of independent hardware and software development followed by system integration; With the ICE-22 module, prototype hardware can be added to the system as it is designed. Software and hardware testing occur while the product is being developed. Through symbolic references in combination with other features 0.1 the emulator, the user can easily: • Disassemble program memory to mnemonics • Assemble mnemonic instructions into executable code. • Examine or modify 8022 internal registers, data memory, or digital port contents. • Examine analog port data • Symbolically define groups of usei' probes, and use these groups to symbolically specify breakpoints and trace qualifiers, or to format external trace data output. Conceptually, the ICE-22 emulator assists three stages of development: It can be operated without being connected to the user's.system, so ICE-22 debugging capabilities can be used in conjunction with the Intellec text editor and MCS-48™ macroassembler· to facilitate program development before any of the user's hardware is available. Integration of software and hardware can begin when ·any functional element of the user sys- . tem hardware is connected to the 8022 socket. As each section of theuser'shardware is completed, it is added to the prototype. Thus, each section of the hardware and software is "system" tested as it becomes available. . When the user's prototype is complete, it is . tested with the final version of the user system software. The ICE-22 module is then used for real-time emulation of the 8022 to debug the system as a completed unit, and verify system performance before any ROM codes are entered. A final product verification test may be performed prior to ROM code entry by using the separately available EM-2 8022 emulation board (8022 EPROM equivalent) within the eventual product package. Thus, the ICE-22 module provides the user with the ability to debug a prototype or production system at any stage in its development without introducing extraneous hardware or software test tools. Symbolic Debugging The ICE-22 emulator permits the user to define and use symbolic rather than absolute references to program and data memory addresses; additional symbols are predefined by the ICE-22 software for referencing registers, flags, and inputl output ports. Thus, the user.need not become involved with niach·ine code, or recall or look up the addresses of key locations in his program as they change with each assembly. Operation Modes The ICE-22 software is a RAM-based program that provides the user with easy-to-use commands for initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters. ICE-22 commands are configured with a broad range of modifiers which provide the user with maximum flexibility in describing the operation to be performed. EMULATION The ICE-22 module can emUlate the operation of a prototype 8022system,including full emulation of the 8022 analog to digital converter, at real-time speed (0.6 to 3.6 MHz) or in Single or multiple steps. Emulation commands to the ICE-22 module • control the process of ·setting up, running, and . halting an emulation of the user's 8022-based system. Breakpoints, comparison registers, and tracepoints en.ablethe ICE-22 emulator to halt emulation and provide a detailed trace of execution in any part of the user's program. A summary of the emulation commands is shown in Table 1. 17-20 Breakpoints TheICE-22 hardware includes two breakpoint registers that allow the user to halt emulation when specified conditions are met. The emulator continuously compares the values stored on the breakpoint registers with the status of specified AFN·01586A ICE·22™ IN·CIRCUIT EMULATOR tion to the = condition, 2) more 8022 and ICE varibles may be compared, and 3) the comparators themselves may be variables. data, addresses, andlor external logic probes, and halts emulation when this comparison is satisfied_ When an instruction initiates a break, that instruction is executed completely before the break takes place. The ICE-22 emulator then regains control of the console and enters the Interrogation Mode. With the breakpoint feature, the user can request an emulation break when his program: Trace and Tracepoints Tracing is used with both real-time and singlestep emulation to record diagnostic information in the trace buffer as a program is executed. The in~ formation collected includes opcodes executed, program counter and Port 2 values, and 16 logic probe values for the last 500 instruction cycles. (There are one or two cycles per instruction, depending on the particular instruction.) This information can be displayed as assembler instruction mnemonics, if desired, for analysis during Interrogation or Single-Step Mode. The trace-collection facility may be set to run conditionally or unconditionally. One unique trace qualifier, specified in the same way as a breakpoint, governs conditional trace activity. It can be used to condition trace data collection to take place as follows: • Executes an instruction at a specific address or within a range of addresses • Executes a particular opcode • Receives a specific signal on a logic probe, digital port pin, or group of probes or pins • Fetches a particular data value from the user program memory Breakpoints can be composed of conditions on 22 channels which reflect internal 8022 activities, plus the 16 external logic probe channels; all but one of the channels may be specified as "Don't Care" channels. Address ranges must be specified as a range of pages (rOOH) to sFFH), a range of 16-byte paragraphs within a page (prOH) to psFH), or a range of bytes within a paragraph (pqrH to pqsH) where, in each case, s is a digit greater than or equal to the digit r. • Under all conditions (constantly occurring) • Only while the trace qualifier is satisfied • For the 500 instruction cycles preceding the time when a trace qualifier is first satisfied (pretriggered trace) Table 1. Major Emulation Commands Description Command GO BRa, BR1, BR STEP CRO, CR1, CR2, CR3, CR TR • For the next 500 instruction cycles after a trace qualifier is first satisfied (post triggered trace). Begins real·time emulation and optionally specifies break conditions. Sets or displays either or both Breakpoint Registers used for stopping real-time emulation. Begins single-step emulation and optionally specifies terminating conditions. Sets or displays comparison criteria in all or individual Comparison Registers used for stopping automatic single-step emulation. Specifies or displays trace-data collection conditions, and optionally sets Qualifier Register (QR). INTERROGATION AND UTILITY Interrogation and utility commands give the user convenient access to detailed information about the user program and the state of the 8022 that is useful in debugging hardware and software_ Changes can be made in both memory and the 8022 registers, flags, and digital port values. Commands are also provided for various utility operations such as loading and saving program files, defining symbols and logic probe groups, displaying trace data, controlling system synchronization and returning control to ISIS-II. A summary of the basic interrogation and utility commands is shown in Table 2. Two new emulator features are discussed below_ The single-line assembler (ASM command) is a new in-circuit emulation feature that permits the designer to examine and alter program memory using assembly language mnemonics, without leaving emulation mode or requiring time-consuming program· reassembly. When assembling new mnemonic instructions into program memory, previously deSINGLE-LINE ASSEMBLER - Comparison Registers Four comparison registers are provided that allow the user to halt single step emulation when the single condition specified in anyone of these registers is satisfied. The comparison registers differ from the breakpoint registers in that, 1) the comparisons <, s, >, ~,and *- are permitted in addiAFN·015B6A 17-21 inter ICE·22™ IN·CIRCUIT EMULATOR The HELP file is a new ICE feature that allows the designer to display ICE-22 command syntax information at the Intellec console. By typing "HELP~', a listing of all items for which help messages are available is displayed; typing "HELP - " then displays relevant information about the item requested, including typical usage examples. The "HELP" listing and a"HELP ASM" message for the ASM command are shown in Table 3. fined symbolic references (from the original program assembly, or subsequently defined during the emulation session) may be used in the instruction operand field, and the emulator will supply the absolute address or data values as stored in the emulator symbol table. These features greatly reduce the .designer's time spent translating to and from machine code and searching for, absolute addresses, with a corresponding reduction in transcription errors. HELP - Table 2. Major Interrogation and Utility Commands Description Command LOAD Loads user object program (8022 code) into user-program memorY, and user symbols into ICE-22 emulator symbol t a b l e . ' . . DEFINE/REMOVE Defines/removes symbols in ICE-22 emulator symbol table. SAVE Saves ICE-22 emulator symbol table a(ld/or user object program in ISIS·II hexadecimal file. LIST Copies all emulator console input and output to ISIS·II file. Change/Display Commands Change or display value of symbolic reference in ICE-22 emulator symbol table, or contents of key-word references (including registers, I/O ports, and status flags), or memory references. Group Commands Define, change, remove, or display user-defined logic probe channel groups. Trace Commands Position trace buffer pointer; select and format trace output; enable or disable automatic display of trace data and register contents during single-step emulation. PRINT Displays trace data pOinted to by trace buffer pOinter. Synchronization Line Commands Set and display enabled/disabled status of SYNCO and SYNC1 synchronization iine outputs or latched inputs (used to allow real-time emulation or tracing to start and stop synchronous~ Iy with external events). . ASM Assembles mnemonic Instructions into user-program memory, 'or disassembles and displays user-program memory contents. INTERRUPT Simulates external or timer interrupt sequence. EVALUATE Evaluates expression and displays resulting value. SECONDS HELP , EXIT Displays contents of emulation timer, in microseconds. Displays help messages for ICE-22 emulator command-entry assistance. Terminates ICE-22 emulator operation. 17-22 AFN·01586A intJ ICE·22™ IN·CIRCUIT EMULATOR Table 3. HELP Command -HELP Help is available for the following items. Type HeLP followed by the item name. (For more information about HELP. type HELP HELP.) Real-Time Emulation: GO GR SYO BR BRO SRI
Change/Display/Define/Remove: ASM REGISTER DEFINE CBY'l'E STACK REMOVE DBYTE SECONDS GROUP SYl~BOLIC SYNC (PRIMARYSIO) (STRING> (SYSTEMSGROUP> TO/LENGTH EnD (Change several locations and perform range checking or repetition. If the instructions require mor ... memory than the size of the range. an error occurs. If the instructions require less memory. then the data is repeated Ilntil the range is filled.) - Standard 8022 instructions typed one per line. The operand ". " can be used where "'data" is reqllired. and the operand "" can be used where "addr" is r~quired. A continuation ~ prompt •••• is issued after each carriage return is typed. AFN·01586A 17·23 intJ ICE·22T/o1IN·CIRCUIT EMULATOR SPECIFICATIONS Environmental Characteristics ICE·22 Operating Requirements Operating Temperature: O· to 40,·C Operating Humidity: Up to 95% relative humidity ' without condensation., Intellec® Microcomputer Development System (32K RAM required) System console Intellec® Diskette Operating System (single or double density) ISIS-II v_ 3.4 or later Equipment Supplied • Printed circuit boards (2) • Emulation buffer box, Intellec interfaqe cables, and user-interface cable with 8022 emulation processor • 16 external trace probes • Synchronization cables • Crystal power accessory • Operating instructions manual • Diskette-based ICE-22 software (single and double density) Emulation Clock User's system clock (0_6 to 3.6 MHz) or ICE-22 crystal power accessory (3.0 MHz) Physical Characteristics Printed Circuit Boards Width: 12.00 in. (30.48 cm) Height: 6.75 in. (17.15 cm) Depth: 0.50 in. (1.27 cm) Buffer Box Width: Uin, (11.43 cm) Length: 10.0 .in. (25.40 cm) Depth: 1.25 in, (3.18 cm) Packaged Weight: 8.0 Ib (3.63 kg) Electrical Characteristics DC Power Requirements Vcc = + 5V, + 5%, - 1% Icc = 13.2A max; 11.0A typical Voo= + 12V, ±5% 100 = 0.1A max; 0.05A typical VBB= -10V, ±5% IBB =0.05A max; 0.01 A typical ORDERING INFORMATION Part Number Description MCI-22-ICE 8022 Microcontroller In-Circuit Emulator, cable assembly and interactive diskette software 17-24 MCS-S1™ Development Systems 18 8051 SOFTWARE DEVELOPMENT PACKAGE • CONV51 Converter for translation of 8048 assembly language source code to 8051 assembly language source code • Symbolic assembly language programming for 8051 microcontrollers • Extends Intellec® Microcomputer Development System to support 8051 program development • Provides upward compability from the MCS-48™ family of single-chip microcontrollers • Provides assembler output in standard Intel hex format • Supports conversion of ASM48 source code macro definitions • Macro Assembler features conditional assembly and macro capabilities The 8051 software development package provides development system support for the powerful 8051 family of single chip microcomputers. The package contains a symbolic macro assembler and MCS-48 source code converter. The assembler produces absolute machine code from 8051 macro assembly language instructions. This object code may be used to program the 8751 EPROM version of the chip. The assembler output may also be debugged using the ICE-51TM in-circuit emulator. The converter translates 8048 assembly language instructions into 8051 source instructions to provide software compatibility between the two families of microcontrollers. This diskette-based software package runs under ISIS-II on an Intellec Microcomputer Development System with 64K bytes of memory. MCa-61'"6tl4,11...0Qt5, ASSlONaL Y l,.ANUUAat: CQHI(lI;RT"'''OP£RATINOi fHSTflUt:;rrIOH$ I'OR ISIS.II USER$ 18-1 8051 SOFTWARE DEVELOPMENT PACKAGE 8051 MACRO ASSEMBLER • Provides software support for many addressing and data allocation capabilities • Supports 8051 family program development onlntellec® Microcomputer Devel. opment Systems • Gives symbolic access to powerful 8051 hardware features • Symbolic Assembler supports symbol table, cross-reference, macro . capabilities, and conditional assembly • Produces object file, listing file and error diagnostics The 8051 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language instructions into machine executable object code. These assembly language mnemonics are easier to program and are more readable than binary or hexadecimal machine instructions. Also, by allowing the programmer to give symbolic names to memory locations rather than absolute addresses, software design and debug are performed more quickly and reliably. The assembler supports macro definitions and calls. This is a convenient way to program a frequently used code sequence only once. The assembler also provides conditional assembly capabilities. Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was defined and referenced. ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These features include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic. The assembler also provides symbolic access to hardware registers, 1/0 ports, control bits, and RAM addresses. Math routines are enhanced by the MUltiply and DIVide instructions. If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which are included in the assembly listing or on another file. Program testing may be performed by using the Universal PROM Programmer and 8751 personality card to program the 8751 EPROM version of the chip, or by using the ICE-51 in-circuit emulator. IItS-51 "MIlO USU.UR IllS-II IICS-51 UCRO ftSSEII8LER DUEeT MODULE PLAUD 1M tFI:CONVRT.HEIt ASSUaLER INVOkED BYI I FI t lIS", I I Fit COHI'RT. 51 i\'llBOlS XREf LOt OB" LIME ...,,,. , J Th'5l"Ololtinlconnrts BCD to. binll.ry ond·binor." to BCD . . . e lUI ... 8 liB ,£1 Qllt ?5FIIA 1114 41111 11I'554FI !lOY 9.1111 14 o III~ " C? liB', :541F 018027 11I[.F7 OIlF 2:! , 1111884 11111 C4 1112 45F1 BlUf? 1115"22 IICS-51 IIACRO ASSEMBLER TVPE 8 . . . II OSEe: 8CD8IN. l CSEG IIMICD. L CIEG COIIYRT" l esEC. Lood B hI" diVision Dr lIultlpllcdlCln"by ' I J.nQSk out lou ordll" digit h,gl'l dllilit Into. \0.\1 order nibb\. :.no". f "UHIP~~Ld~:lt 11111 IB . """ ..""" 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" 1" AU£lt8l't CDKFl£lE, HO ERRORS f!HJHII- Sample ASM51 Listing 18·2 8051 SOFTWARE DEVELOPMENT PACKAGE CONV51 8048 TO 8051 ASSEMBLY LANGUAGE CONVERTER UTILITY PROGRAM • Preserves comments; translates 8048 macro definitions and calls • Enables software written for the MCS-48™ family to be upgraded to run on the 8051 • Provides diagnostic information and warning messages embedded in the output listing • Maps each 8048 instruction to a corresponding 8051 instruction The 8048 to 8051 Assembly Language Converter is a utility to help users of the MCS-48 family of microcomputers upgrade their designs with the high performance 8051 architecture. By converting 8048 source code to 8051 source code, the software investment developed for the 8048 is maintained when the system is upgraded. The goal of the converter (CONV51) is to attain functional equivalence with the 8048 code by mapping each 8048 instruction to a corresponding 8051 instruction. In some cases a different instruction is produced because of the enhanced instruction set (e.g., bit CLR instead of ANL). Although CONV51 tries to attain functional equivalence with each instruction, certain 8048 code sequences cannot be automatically converted. For example, a delay routine which depends on 8048 execution speed would require manual adjustment. A few instructions, in fact, have no 8051 equivalent (such as those involving P4-P7). Finally, there are a few areas of possible intervention such as PSW manipulation and interrupt processing, which at least require the user to confirm proper translation. The converter always warns the user when it cannot guarantee complete conversion. CONV51 produces two files. The output file contains the ASM51 source program produced from the 8048 instructions. The listing file produces correlated listings of the input and output files, with warning messages in the output file to point out areas that may require users' intervention in the conversion. Optional Hardware: SPECIFICATIONS Universal PROM Programmer Line Printer ICE-51 In-Circuit Emulator OPERATING ENVIRONMENT Required Software: Required Hardware: ISIS-II Diskette Operating System (V3.4 or later) Intellec Microcomputer Development System with Documentation Package: 64K Bytes of RAM MCS-51 Macro Assembler User's Guide Flexible Disk Drive(s) MCS-51 Macro Assembly Language Pocket Reference System Console MCS-51 8048-to-8051 Assembly Language Converter Operating Instructions for ISIS-II Users -CRT or hard copy device ORDERING INFORMATION Part Number Description MCI-51-ASM 8051 Software Development Package 18-3 UPI-41ATM Development Systems 19 ICE·41A™ UPI·41A IN·CIRCUIT EMULATOR Extends Intellec microcomputer develop· ment system debug power to user con· figured system via external cable and 40·pin plug, replacing user UPI·41A™ devices Em.ulates user system UPI·41A™dEwices in real time Eliminates need for extraneous debug· ging tools residing in user system Collects address, data, and UPI·41A™ status information on machine cycles emulated Provides capability to examine and alter UPI·41A™ registers, memory, and flag values, and to examine pin and port values Allows user configured system to use static RAM memory for program debug Integrates hardware and software efforts early in engineering cycle to save devel· opment time Provides hardware comparators for user designated break conditions The !CE-41A UPI-41A In-Circuit Emulator module is an Intellec system reside.nt. module that interfaces to any user configured UPI-41A system. The.ICE-41A module. interfaces with a UPI-41A pin-compatible plug which replaces the UPI41A device In the system. With the ICE-41A plug In place, the designer has the capability to execute the system In real ilme while collecting up to 255 Instruction cycles of real time trace data. In addition, he can single step the system program during execution. Static RAM memory is available through thelCE-41Amodule to store UPI·41A programs. The designer may display and alter the contents of program memory, internal UPI-41A registers and flags, and 1/0 ports. Powerful debug capability is extended into the UPI-41A system while ICE-41A debug hardware and software remain inside the Intellec system. Symbolic reference capability allows the designer to use symbols rather than absolute values when examining and modifying memory, registers, flags, and 1/0 ports in the system. 19-1 00804A L"'--:,_ .• _-· .. ICE·41A™ GO FROM .START TILL CODE. RSLT FUNCTIONAL DESCRIPTION begins execution of the program at the address referenced by the I.abel START in the designer's assembly program. A breakpoint is set to occur the first time the microprocessor executes the program memory location referenced by RSLT. The designer does not have to be concerned with the physical locations of START and RSLT. The ICE-41A software driver supplies them automatically from information stClred in the symbol table. Debug Capability Inside User System Intellec memory is used for the execution of the ICE·41A software. The Intellec CRT console and the file handling capabilities provide the designer with the ability to com· municate with the ICE-41A module and display informa· tion on the operation of the prototype system. The ICE· 41A module block diagram is shown in Figure 1. Symbolic Debugging Memory Replacement Symbol Table - ICE·41A software allows the user to make symbolic references to I/O ports, memory ad· dresses, and data in his program. The user symbol table which is generated along with the object file during a program assembly can be loaded to Intellec memory for access during emulation. The user may add to this symbol table any additional symbolic values for memory ad· dresses, constants, or variables that he may find useful during system debugging. By referring to symbol memory addresses, the user can examine, change or break at the intended location. In addition, ICE-41A pro· vides symbolic definition of all UPI·41A registers and flags. The 8741/8741A and 8041/8041A contain internal program and data memory. When the UPI·41A microcomputer is replaced by the ICE-41A socket in a system, the ICE-41A module supplies static RAM memory as a replacement for the internal microcomputer memory. The ICE·41A module has enough RAM memory available to emulate upto the total 1K control memory capability of the system. Real· Time Trace The ICE·41A module captures trace information while the designer is executing programs in real time. The instructions executed, program counter, port values for port 1 and port 2, and the values of selected UPI-41A status lines are stored for the last 255 instruction cycles executed. When retrieved for display, code is dis· assembled for user convenience. This provides data for determining how the user system was reacting prior to emulating break. Symbolic Reference - Symbolic reference is a great advantage to the system designer. He is no longer burdened with the need to recall or look up addresses of key locations in his program which can change with each assembly. Meaningful symbols from his source program can be used instead. For example, the com· mand: USER SOCKET SYNO INTERNAL TIMER CABLE SYN1 BUFFER CONTROL PROGRAM 8080A P1 CONTROL PROCESSOR P2 8741A wllNTERNAL MONITOR PGM Figure 1. ICE·41A Module Block Diagram 19-2 00804/\ ICE·41A™ vide the user with maximum flexibility in defining the operation to be performed. The ICE-41A software driver is available on diskette and operates in 32K of Intellec RAM memory. Integrated Hardware/Software Development The user prototype systems need no more than a UPI41A socket and timing logic to begin integration of software and hardware development efforts. Through the ICE-41A module, Intellec system resources can be accessed to replace the prototype system. UPI-41A software development can proceed without the prototype hardware. Hardware designs can be tested using previously tested system software. Command Hardware The ICE-41A module is a microcomputer system utilizing Intel's UPI-41A microprocessor as its nucleus. This system communicates with the Intellec system 8080A processor via direct memory access. Host processor commands and ICE-41A status are interchanged through a DMA channel. ICE-41A hardware consists of two printed circuit boards, the controller board and the emulator board, which reside in the Intellec system chassis. A cable assembly interfaces the ICE-41A module to the user's UPI-41A system. The cable terminates in a UPI-41A pin-compatible plug which replaces any UPI-41A device in the user system. Operation Enable Activates breakpoint and display registers for use with go and step commands. Go Initiates real-time emulation and allows user to specify breakpoints and data retrieval. Step Initiates emulation in single instruction increments. Each step is followed by register dump. User may optionally tailor other diagnostiC activity to his needs. Interrupt Emulates user system interrupt Table 1. ICE·41A Emulation Commands Controller Board Command The ICE-41A module interfaces to the Intellec systems as a peripheral device. The controller board receives commands from the Intellec system and responds through a DMA port. Three 10-bit hardware breakpoint registers are available which can be loaded by the user. While in emulation mode, a hardware comparator is constantly monitoring address lines for a match which will terminate an emulation. The controller board returns real-time trace data, UPI-41A registers, flag and port values, and status information to a control block in the Intellec system when emulation is terminated. This information is available to the user through the ICE-41A interrogation commands. Error conditions, when detected, are automatically displayed on the Intellec system console. Display Prints contents of memory, UPI-41A device registers, 1/0 ports, flags, pins, real-time trace data, symbol table, or other diagnostiC data on list device. Change Alters contents of memory, register, output port, or flag. Sets or alters breakpoints and display registers. Base Establishes mode of display for output data. Suffix Establishes mode of display for input data. Operation Table 2. ICE·41A Interrogation Commands Emulator Board Command The emulator board contains the 8741A and peripheral logic required to emulate the UPI-41A device in the user system. A 6 MHz clock drives the emulated UPI-41A device. This clock can be replaced with a user supplied TTL clock in the user system or can be strapped internally for 3 MHz operation. Load Fetches user symbol table and object code from input device. Save Sends user symbol table and object code to output device. Define Enters symbol name and value to user symbol table. Move Moves block of memory data to another area of memory. Print Prints user specified portion of trace memory to selected list device. Cable Card The cable card is included for cable driving. It transmits address and data bus information to the user system through a 40-pin connector which plugs into the user system in the socket designed for the UPI-41A device. Software The ICE-41A software driver is a RAM-based program which provides the user with command language (see Table 1, Table 2, and Table 3) for defining breakpoints, initiating real-time emulation or single step operation, and interrogation and altering user system status recorded during emulation. The ICE-41A command language contains a broad range of modifiers which pro- Operation List Defines list device. Exit Returns program control to ISIS-II. Evaluate Converts expression to equivalent values in binary, octal, decimal, and hex. Remove Deletes symbols from symbol table. Reset Reinitializes ICE-41A hardware. Table 3_ ICE-41A Utility Commands 19-3 OOB04A ICE·41A™ Voo= + 12V, ±5% 100= 100 rnA max; 60 rnA typ V BB = -10V IBB c=30 rnA SPECIFICATIONS ICE·41A Operating Environment Required Hardware Intellec microcomputer development system System console lntellec diskette operating system ICE·41A module Input Impedance @ ICE·41A user socket pins: V IL =0.8V max; 1,,:.= 1.6 rnA VIH=2.0V min; IIH=40 ~ @ Bus: VIL = 0.8V max; IlL = 250,..A V IH = 2.0V min; V IH = 20 ~ Required Software System monitor ISIS·II ICE·41A diskette·based software Output Imp!!dance @ P1, P2: VOL =O.5V max; IOL = 16 rnA VOH=V CC (10K pullup). System Clock Crystal controlled 6.0 MHz or 3',0 MHz internal or user supplied TTL external @ Bus: VoL =0.5V max; IOL=25 rnA VOH = 3.65V min; IOH = 1 rnA Others VOL = 0.5V max; IOL;;' 16 rnA VO H = 2.4V max; IOH = 400~. Physical Characteristics Printed Circuit Boards Width: 12.00 in. (30.48 cm) Height: 6.75 in. (17.15 cm) Depth: 0.50 in. (1.27 cm) Weight: 8.00 Ib (3.64 kg) Equipment Supplied Controller board Emulator board Interface cables and buffer module Operator's manual ICE·41A diskette based software Cable Buffer Box Width: 8.00 in. (20.32 cm) Height: 4.00 in. (10.16 cm) Depth: 1.25 in. (3.17 cm) Flat Cable: 4.00 ft (121.92 cm) User Cable: 15.00 in. (38.10 cm) Reference Manuals 9800465 - ICE·41A Operator's Manual (SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or fromlritel Literature Department, 3065 Bowers .. Avenue, Santa Clara,.California 95051. Electrical Characteristics DC Power Requirements Vcc= + 5V, ± 5% Icc= 10A max; 8A typ ORDERING INFORMATION Part Number Description MDS·41A·ICE UPI~41A (8741, 8041, 8741A, 8041A) CPU . In,circuit emulator, cable assembly and interactive diskette software included 19·4 •.. ..:::. 00004A 2920 Signal Processor Development Systems 20 2920 SOFTWARE SUPPORT PACKAGE • Complete software design development support for the 2920 • Extends Intellec® Microcomputer Development System to support 2920 software development The 2920 Software Support Package furnishes a 2920 Signal Processing Applications Software/Compiler, 2920 Assembler, and 2920 Software Simulator. These three software design and. development tools run on the Intellec@ Microcomputer Development System. The 2920 Signal Processing Application Software/Compiler is an interactive tool for designing software to be executed on the 2920 Signal Processor. The compiler accepts English·like statements from the user and generates 2920 assembly language code. The assembler translates symbolic 2920 assembly language programs into the machine operation·code. The user can load the code into the simulator for 2920 simulation or to the Universal PROM Programmer for 2920 EPROM programming. The simulator, operating entirely in software, allows the user to test and symbolically debug 2920 programs. The user can specify input signals, simulate program execution, set up breakpoints, display input and output, and display and alter th.e contents of the 2920 registers and memory locations. The simulator can also stop or trace the program and constructively give the user access to the key elements inside a 2920 for analyzing his program. The compiler, assembler, and simulator enable the designer to develop and tesf an entire program without a complete prototype design. The 2920 designer works on the Intellec@ Microcomputer Development System rather than on a breadboard. ThedevelopmEmt system can program, store and recall programs or routines and aid in 2920 program design. 2920 Software Support Package 20·1 inter 2920 SOFTWARE SUPPORT PACKAGE 2920 SIGNAL PROCESSING APPLICATIONS SOFTWARE/COMPILER • Interactive software support tool for 2920 Signal Processor • Compiler generates 2920 Assembly Language Code • Extensive command set for designing electrical filters • Extends Intellec® Microcomputer Development System support of the 2920 • Graphics capability enhances analysis of filter response or piecewise linear function approximations • Contains MACRO library for several standard filters and signal processing functions • Powerful MACRO capability for executing frequently used routines The 2920 Signal Processing Applications Software/Compiler (SPAS20) is an interactive tool for designing software to execute on the 2920 Signal Processor. The SPAS20 package can be visualized as being comprised of four inter-related sections: A compiler section, a filter design section, a curve fitting section, and a MACRO section. Among the abilities of SPAS20 are: ability to generate 2920 assembly language code directly from specifications of signal processing building blocks such as filters and waveform generators; ability to generate 2920 assembly language code for several classes of algebraic equations such as Y = C·X, Y = C'Y, and Y = C· X + Y where X, Yare variables and C is a constant; ability to generate 2920 assembly language code for one variable function Y(X) = F(X); ability to examine time and frequency responses of filter sections specified by continuous or sampled poles and zeroes; ability to examine piecewise linear approximation of specific function; ability for users to implement more complex commands by grouping sets of commonly, used commands into a MACRO. The SPAS20 package runs under ISIS-II on any Intellec® Microcomputer Development System with 64K RAM. The output of SPAS20 can be assembled with the 2920 assembler, tested with the 2920 Simulator, and programmed into the 2920 chip with the Universal PROM Programmer for prototyping. 20-2 AFN·01386A inter 2920 SOFTWARE SUPPORT PACKAGE FUNCTIONAL DESCRIPTION DATA The 2920 Signal Processing Applications Software! Compiler gives the analog designer a "high level language" for his 2920 applications-it decreases the need to code 2920 assembly language. Furthermore, the compiler Is interactive. This feature enables the designer to define a filter, or transfer function, graph their response, and change their parameters many times, without having to program and test in an actual 2920 implementation. This command allows for specification of a set of vertices (i.e. X - Y coordinate pairs) which determine a piecewise linear approximation of some defined function, filter response characteristics, etc. HOLD Command to correct attenuation due to sample-and-hold distortion: if ON, it corrects absolute gain by sin(x)!x and phase by adding x, where x=TS*FREQ*n. It corrects group delay by subtracting n*TS. EVALUATE Gives the decimal numeric value of any expression. CODE Creates 2920 assembly language code for giveri poles; and zeros, equations, and user defined functions. Once a filter is realized by moving poles and zeros in the continuous and sampled planes, the filter may be coded and written onto an ISIS file. Similarly, after a function Y = F(X) has been defined, the code for a piecewise linear approximation can be stored onto an ISIS file. Several other file commands are available to store and retrieve command sequences for SPAS20 sessions. The SPAS20 compiler also recognizes the following commands for file h?ndling: SPAS20 Command Language DEFINE This command defines a pole or zero by associating it with a number (i.e., POLE 3), and with real and imaginary coordinates in the continuous or sampled plane. This command also defines a symbol by associating a name with a numeric value, or a MACRO by providing a pOinter to a specified command sequence. GRAPH! OGRAPH MOVE This command graphically displays the values of object(s) specified. For example, GRAPH GAIN and GRAPH PHASE are used to display filter response. The OGRAPH command will "overgraph" the new response over the old response, after any changes have been made. (You may also graph Group Delay, Step, and Impulse.) Deletes the definition of a pole, zero, symbol, or macro. HELP Types an explanatory message on the console, pertaining to a command or its attributes. FIT This command performs curve fitting, i.e. it approximates an arbitrary user supplied function with a piecewise linear function. Writes out objects (commands) to a specified file, either creating a new one or appending an existing one. This enables the user to store all or part of a SPAS20 session on a diskette to be brought back later with .the INCLUDE command. DISPLAY Copies the console. INCLUDE Executes a sequence of instructions from a diskette file as if they were typed in from the console. LIST Creates a file containing console interactions. cont~nts of a file to the all In addition to naming macros for specific command sequences, compound and conditional commands may be formed using all of the above statements. These compound commands are: Allows the definition of a pole or zero to be changed-its coordinates, its plane, or both. REMOVE PUT! APPEND 20-3 IF Establishes conditional flow of control within a block of commands. REPEAT Used for repetition of a block of commands; executes indefinitely or until a condition is met (using WHILE, UNTIL, and END statements). COUNT Establishes the number of times a command sequence is to be executed, in a looping fashion. AFN·013B6A 2920 SOFTWARE SUPPORT PACKAGE Intel also supplies several MACRO library files corvtaining the following commonly needed MACROs: SPAS20 MACRO Facility A macro is a sequence of commands that is stored on a temporary diskette file. The command sequence is executed when the macro name is entered as a command. This saves repetitive entry of the sequence, and permits alogorithms to be saved on diskette for future use. This SPAS20 facility allows you to do the following: • Filter design MACROS - Butterworth filter - Chebyshev filter - Bilinear transform - Evaluate gain or phase of digital filter in parallel form - Time response simulatiori Function design MACROs - Code and error optimization - Calculate instertitial error MACROs for generation of 2920 code - Code for all-POLE filter - Input and AID conversion - Multiplication - Division - Logarithm functions - Square-root functions - Sinewave oscillator Display the text of any macro. Define a macro, specifying its name and any parameters that are to be used by the block. This definition is followed by the contents of the macro (commands) and the EM statement to end its definition. • Invoke a macro by entering its name and appropriate values for any parameters. • List the names of all defined macros. • Remove any or all macros. SAMPLE SPAS20 FILTER DESIGN SESSION -: FI : SPAS20 • SFT ISIS-II 2920 SIGNAL PROCESSING APPLICATIONS COMPILER. •'DEFINE POLE 1 .fZ POLE I • J n.o CREATE A POLE IN CONTINUOUS S-PLANE ; LIST ALL POLES AND ZEROS •oFSCALE. •'V'CALi. •'CRAPH = -707.707 ~707.00000.707.00000.CONTINUOUS 100.10000 , ESTABLISHES FREQUENC' RANGE OF INTEREST -45.1 J CAIN ESTABLISHES "AGNITUDE RESPONSE RANGE OF INTEREST PLOT "AGNITUDE RESPONSE OF POLE PAIR !. . . , .• ""' ......... '" "' ................... _ .......... .................................. ! GA IN 1. 0 ,-------------------------- •.•• -i. :( -"l. { -:i. to -? a: -11). I) -IZ. ! -1 ~ ~.~ -1';.5 -I~. , -2Q.~ -2 •• ! -2'5.3 -27. ·5 -2~. ,. -31. , -H.O -305..2 -33.4 - 41). t, -41.S -45,0 DB I HZ .. ~ ••••• A ........... A ,100 150 200 ••• A. " ..... 300 400 500 " A •• , • A. •• ... .................................... 700 1000 1400 2000 3000 5000 ! 10000 0, THE UNITS USED IN GRAPHING GAIN ARE SHOWN IN THE LOVER LEFT CORNER, ., GAIN IN DECIBELS IS GRAPHED YERSES FREQUENC' IN HERTZ, 0, PREPARE TO "OYE TO THE DIGITAL DO"AIN, 0' SA"PLE RATE "UST BE SPECIfiED, • -OTS TS = U13020 = 7,'805004/10,'5 J RATE fOR 192 INSTRUCTION PROGRA" AND 10"HZ CLOCK 20-4 AFN·01386A 2920 SOFTWARE SUPPORT PACKAGE SAMPLE SPAS20 FILTER DESIGN SESSION (Cont'd.) OHQVE POLE TO Z 1 POLES/ZEROES "DYED I CONYERT FILTER TO DIGITAL YIA "ATCHED-Z TRANSFOR"ATION o op LIST TRAHSFOR"ED POLE POLE 1 ·0.710'2836,O.3411836',Z o 0, COHPARE RisPOHSES OF THE ANALOG AHD DIGITAL FILTERS BY GRAPHING THE OJ HEW RESPONSE OYER THE OLP. o .OI:P/\PH CAl H G~:II , ............ " . . . . . . . . . . . . . . . . . . . . . . . . "' • • • • ~' . . . . . . . . . . . . . . . . . . . . A • ' . ' • • • "" . . . . . . . . . . . . .. ! -3, • -~ -7. i t-. +-. -11).0 +'.• -!l.1 -H.3 -I·L 5 t' • t't ' ~. -H., -20. ~ -21.1 t -. ++ ' .. - •• ++ ' ,, ++ -2~.:l -2",'5 -2i.~ -Jl.~ +t ++ + -3~.O -3'.2 +t ++ -3~.~ -4~.' + -4Z.S -4 ~. ~ liB I HZ A....... ... ,. 100' i 50' 200' •• 30 0 • 400 . 500' . 70 0 • i 000 . i 400 . 2000' . iooo .... 5000 ..... i DO 00 1 ... A ......." I II. 0; PLUS SIGNS INP ICATE OLD CURYE . • ; HOTE THAT THE DIGITAL FILTER RESPONSE 8EGINS TO IHCREASE AGAIN OJ AT HALF THE SA"PLE RATE ( 6510 HZ ). o 0; THE PHASE CHARACTERISTICS OF THIS FILTER CAN BE EXA"INED. o OYSCttLE • -PI,PI I ESTABLISHES RANGE OF INTEREST. o oCRAPH PHASE PH~SE I . '0' ."" . . . . . . . . . . . . "" ••• "" . . . . . . . . . . . . . . . . . "' . . . . . . . . . . . A . . . . . . . . . . . . . . . . . "' • • • • • ~ • • • I 3.14 2.94 2.54 2.24 1.94 1.6S 1.35 1.05 0.75 0.45 O.! 5 -0.15 -0.45 -0.75 -1.05 -1.35 ."",-------""-- "_- -1.65 -I." -2.24 -2.54 -2.84 -3,14 RAD 1HZ PO •'PUT o ! ..... "" ... A ••••• A 100 150 200 'FIIPOLE PZ ••• A ...... " ..... A ..... " 300 400 500 I ~ " ......... " ••••••• A ••••• " 5000 ••• ! 10000 SAYE THE POLE LOCATION IN A DISK FILE BACKUP PULE I 11181<11 : ~ENERA'IE B!=I 33'8"'0 B20-0.50541'14 oC·)UE •••• A ••• ·700 1000 1400 2000 ·3000 ~~~u 20:5. ·ASSE~i;L·( I~ODE FUR THIS flLHR AFN.(l1388A 2920 SOFTWARE SUPPORT PACKAGE SAMPLE SPAS20 FILTER DESIGN SESSION (Cont'd.) OPTlnlZED 2'20 CODE IS NOW GENERA1ED. 10 SAVE SPACE, SOnE OF TNE SCREEH OUTPUT HAS BEEN DELE1ED. HORnALLY ALL A1TEnPTS BY THE CO"PILER TO GENERAiE CODE ARE ECHOED ON 1HE SCREEN. INS1=10 POLE 1 = 0.71089458,0.34116779,Z BEST: PERROR 3.3795874/10"5,1.58846567/10"5 = , HOTE: nAKE SURE SIGNAL IS <0.74635571 LD~ ~UT2_PI,OUTI_PI,ROO ; OU12_PI-I.0000000000UTI_PI LOA OUTI_PI,OUTO_PI,ROO ; OUTI_PI=I.00000000·OU10_PI SUB OUTO_PI,OUTI_PI,R05 ; OU10_PI=I.00000000oOU10_PI-0.031250000'OUTI_PI ADO OUTO_PI,OU10_PI,R03 : OUTO_PI-I.1250000000UTO_PI-0.035156250'OUTI_PI ADD OUTO_PI,OU11_PI,R02 ; OUTO_PI-I.12500000*OU10_PI+0.21484375*OU11_'1 SUB OUTO_PI,OUT2_PI,ROI ; OUTO_PI-I. 1250000000U10_PI+0.21484375*OUTI_PI-0.50000000*OUT2_PI SUB OUTO_PI,OUT2_PI,R08 ; OUTO_PI=I.12500000*OU10_PI+0.21484375*OUTI_PI-0.50390625.0UT2_PI ADO OUTO_PI,OUT2_PI:RII : OU10_PI=I.12500000.0U10_PI+0.21484375'OU11_PI-0.503417'6'OUT2_PI SUB OUTO_PI,OUTZ_PI,R09 : OUTO_PI=I.1250000000UTO_PI'0.214B4375'OU11_PI-0.50537109.0UT2_PI ADD OUTO_PI,IHO_PI,ROO ; OU10_PI-I.12500000.0U10_PI+0.21484375.0U11_PI-0.5053710'.OUT2_PI+1 .OOOOOOOO R. ._-Doilv_ERs~ 'Jr-:---liir---:-""--:-L" ",~L~OO~IC:,.J ~ PARITY 1(;::1\, I _ ECC . . - ' ~.M"EQii (READ AND WAITE DATAl 21·20 I BUF:R ,: Figure 1. In·5160 NOVA·3 Add·ln Memory Simplified Block Diagram ~ ADDRf-ESS----'M"EMBBUSTRANSCEIVERS 2 ~l I' ~I--r-TA----l ! i ~ A ClV~ IlL... ~r- ~ I ;:.. in·5160 Operating Modes Parity The in·5160 emulates all of the operating modes sup· ported by Data General on the NOVA 3 series com· puters. In normal operation, the in·5160 performs read, read·hold, write, and read·modlfy·wrlte processor con· trolled cycles. Refresh cycles are timed out internally and use chip row addresses generated by a counter on the board. The in·5160 offers the largest storage capac· ity that can be handled by existing software and has a higher effective speed than the NOVA 3 semiconductor memories. Read or write operations required 500 nano· seconds and the read·modify·write operation is com· pleted in 1100 nanoseconds, whether Initiated when the memory is Idle or Immediately following a preceding cycle. On consecutive memory cycles, the Data General NOVA 3 memory requires 500 nanoseconds for read cycles, 1200 nanoseconds for write cycles and 2200 nanoseconds for read·modlfy·wrlte. Since consecutive memory cycles occur frequently, the Intel memory can provide significantly faster throughput. The data valid time Is extended during the read·hold cycle by the proc· essor pulling the hold input low. The longer data valid time is required during defer cycles, console Initiated read cycles (the examine switch), or during data channel read cycles. For data channel memory cycles, the memory operates in either write or read·hold modes. All read, write, or read·modlfy·wrlte cycles can be per· formed with or without single bit error correction, map, memory protection, or parity error reset or Interrupt. The parity feature is standard on all in·5160 memory boards. During write operations, the parity logic gener· ates a parity bit for the 16·bit data word. Data and parity bit are then stored in the memory. During read opera· tions, 16 bits of data and one parity bit are read out from the memory and checked for a parity error. If a parity error is detected, the address and parity bit are latched in the parity error address register, and either a reset or interrupt signal (jumper selectable) is returned to the processor. The CPU reads the contents of the parity er· ror address register by using standard 1/0 instructions. The parity feature services not only the in·5160, but all 17·bit memories in the same system. On boards with the ECC option, the parity logic still functions for other 17·bit memories in the system and reports multiple bit errors detected by the ECC logic to the CPU as parity errors. Memory Management and Protection Unit (MMPU) Memory expansion - The MMPU provides the capabll· ity to use a memory of up to 128K words and supplies the hardware necessary to make use of the NOVA 3 soft· ware protection . features. The expansion of memory capacity is accomplished by replacing the five highest order address bits (the logical address) with seven bits from a location In the translation memory (the physical address). Each logical address is 'mapped' (or .trans· lated) to one, and only one, physical address, which may be anywhere within the 128K physical address field. The contents of the translation memory (the map) may be set up using ordinary 1/0 instructions. Memory protection - The memory protection function of the MMPU provides detection capability for five types of software violations: Error Correction and Error Logger The in·5160 error correction circuitry (ECC) provides on· board capability to correct any single bit error and detect any double bit error in the read data. Many errors of more than 2 bits will also be detected. ECC greatly Increases memory reliability and minimizes non· recoverable system failures. The multiple bit errors are flagged to the processor as parity errors. All errors are logged as they occur and are simultaneously displayed on the in·5160's control panel. The error correction func· tion can be disabled by a switch on the control panel; however, the error logger will continue to monitor and store error information. The chip location of single bit errors and row location of double bit and multiple bit errors are stored in the error logger memory and displayed on LEOs on the control panel as they occur. The error logger .controls and indicators are shown in Figure 2. ERR BIT - THESE INDICATORS SHOW FAULTY DATA BIT (BINARY CODED), 16,8,4,2,1 EXAMPLE: INDICATORS 1 AND 4 ON, INDICATES BIT 5 IN ERROR. SK (SEEK) - PUSHBunON SWITCH. WHEN PUSHED AND HELD, PERFORMS LED TEST. WHEN RELEASED, EnROR LOGGING MEMORY IS SEARCHED FOR ERROR INFORMATION. eLR (CLEAR) - PUSHBUTTON SWITCH. CLEARS ERROR LOGGING MEMORY. • Write protect tected 1K page prevents writing into a write pro· INH (INHIBIl) - TOGGLE SWITCH. IN ON POSITION INHIBITS ERROR CORRECTION FUNCTION. DOES NOT INHIBIT ERROR LOGGER. • Validity - prevents accessing, in any manner, a page declared invalid • Defer • 1/0 - protects against runaway defer cycles Loa - THIS INDICATOR COMES ON TO INDICATE ERROR LOGGING IN PROGRESS. enables 1/0 violation detection in the CPU • Auto Index - ROW - THESE INDICATORS SHOW ROW LOCATION OF FAULTY RAM 4,2,1,'12 (BINARY CODED). ERR -INDICATES ERROR IS DETECTED; SINGLE BIT OR DOUBLE BIT/MULTIPLE BIT Prevents auto·indexing operations. When a violation is detected, the MMPU initiates a map interrupt routine in the processor. 21·21 Figure 2. Error Logger Control Panel and Indicators in·5160 the 128K in-5160 dissipates 170 Btu/hr; in battery backup (standby) mode, it dissipates 55 Btu/hr. This results in a cooler running system,an increased margin for power supply operation, and improved system reliability. Every card is fully tested ,in a temperature cycling environment for eight hours and in a NOVA 3 computer to test all options with the NOVA software. Because of the 100% burn-in performed on each card, the user is assured of receiving Intel's proven quality and reliability. In addition, all Data General compatible products manufactured by Intel are covered by a on year warranty. INSTALLATION The installation of the in-5160 on a NOVA 3 system is covered in detail by the technical manual which accompanies the product. The main pOints of consideration during installation are address selection and parity error actiori(RESET or interrupt). The location of these switches arid jumpers are illustrated in the manual for easy location. RELIABILITY The in-5160 is designed for low power dissipation. When operating with all options, and at full speed in a NOVA 3, Memory Data Input/Output - 16 bidirectional lines 1/0 Data InputlOutput - 16 bidirectional lines Control Inputs - 36 lines Control Outputs - 14 lines SPECIFICATIONS Storage Capacity 32K, 64K, 96K, or 128K words Word Length Physical Characteristics Standard - 16 data bits and one parity bit With ECC - 16 data bits and six ECC check bits Width - 15 in, (38.1 cm) Length - 15 in. (38.1 cm) Height - 0.4 in. (1.02 cm) Weight - Less than 3 Ib (1.36 kg) Cycle Time Read or Write Cycle - 500 ns RMW"- 1100 ns Electrical Characteristics Access Time DC Power Pequirements (128K, all options) Voltage 300 ns (access and cycle times are extended 100 ns if error correction takes place) Processor - Read, read-hold, write, read-modify-write Data Channel - Read-hold, write MMPU - Translation enabled/disabled Parity - Disabled/generate even parity, generate odd parity Interface - NOVA-3 backplane compatible, one card slot required Note: If Ihe in"5160 is equipped wllh MMPU opllon, backplane sial 2 Is required. . Address Input DS 0-5: 6 lines MADR 1-15: 15 Lines; ALU 0-6: 7 lines; Address Input/Output -'MADR 1-15 (Generated in MMPU) X MADR 0-2 Current Battery Backup 6.8A 890mA 5mA +5V +15V 5V Operating Modes for Memory Interface Characteristics Active (±S%) 2.2A 350mA Environmental Characteristics Temperature -'- O·C to 50·C operating ambient; -40·C to 120·C non-operating ambient Relative Humidity Altitude operating Up to 90% with no condensation 10,000 ft max operating; 50,000ft max non- Reference Manuals TM-5160-000 - in-5160 Technical· Manual, Number 111768 (SUPPLIED) Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative. 21-22 in·5160 ORDERING INFORMATION Model CM-5160A-032 CM-5160A-064 CM-5160A-096 CM-5160A-128 CM-5160B-032 CM-5160B-064 CM-5160B-096 CM-5160B-128 CM-5160C-032 CM-5160C-064 CM-5160C-096 CM-5160C-128 CM-5160D-032 CM-5160D-064 CM-5160D-096 CM-5160D-128 Capacity Description 32Kx 17·bit 64K x 17·bit 96Kx 17·bit 128K x 17·bit 32Kx 22·bit 64Kx 22·bit 96Kx 22·bit 128K x 22·bit 32Kx 17·bit 64K x 17·bit 96K x 17·bit 128K x 17-bit 32Kx 22·bit 64Kx 22·bit 96Kx 22·bit 128K x 22·bit 32K memory with parity 64K memory with parity 96K memory with parity 128K memory with parity 32K memory with ECC· 64K memory with ECC 96K memory with ECC 128K memory with ECC 32K memory with parity and MMPU 64K memory with parity and MMPU 96K memory with parity and MMPU 128K memory with parity and MMPU 32K memory with ECC and MMPU 64K memory with ECC and MMPU 96K memory with ECC and MMPU 128K memory with ECC and MMPU 21·23 MU-S7S0 VAX*-11/7S0 ADD-IN MEMORY CARD • 512KB or 1024KB Capacity (Equivalent to 2 or 4 DEC M8210 Memory Modules) • Replaces DEC* MS 780-DB or MS 780-DC • Spare Memory Devices On-Board • Complete Hardware and Software Compatibility The Intel® MU-5780 is a 512KB or 1024KB plug-in memory card designed for use in any DEC VAX-11/780 computer. Organized as 64K or 128K words of 72 bits each, the MU-5780 operates at speeds controlled by the VAX11/780 memory controller. Typical READ cycle and access times are 530 ns and 250 ns, respectively. The MU-5780 may be used to expand the MS 780-C or MS 780-CC basic VAX-11/780 memories up to 4096K Bytes (four megabytes). The MU-5780 is available only as double or quadruple the capacity of the DEC M8210 memory module. Because VAX-11/780 memorybackplane slots are prewired as 256K Bytes each, the 512KB MU-5780 must be installed in every other backplane slot and the 1024KB MU-5780 must be installed in every fourth slot. Two pre-tested memory devices are plugged into sockets on the MU-5780 to provide on-board spares. These devices may be used to replace any failing memory devices in the field. 'VAX, DEC are registered trademarks of Digital Equipment Corporation. 0000000000000000 ~DooD~ DDDDDDDDDDDDDDDD 0000000000000000 ~ ~ DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD ~DD DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD ~OO~ DDDDDDDDDDDDDDDD 0000000000000000 ~DD~ 0000000000000000 DDDDDDDDDDDDDDDD ~ 00~ DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD ~DD~ DDDDDDDDDDDDDDDD 0000000000000000 ~OO~ 0000000000000000 DDDDDDDDDODDDDDD~~~~~DDDDDDDDDDDDDDDD o0 0 0 0 ODD DO 000000 0 0 0 0 DOD DO The following are trademarks of Intel Corporation and may be used only to identify Intel products: i, Intel, INTEL, INTELLEC. MeS, im, ies, ICE, UP1, BXP, iSBC, iS8X, INSITE, iRMX, CREDIT, RMXJ80, p,Scope, Multibus, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE, ssc, RMX or ieS and a numerical suffix; e.g., isee-eO. © Intel Corporation 1980 21-24 AFN-01734A Insite™ User's Program Library 22 intel° INSITE™ USER'S PROGRAM LIBRARY • Hundreds of Programs • Programs for 8008,8048,8080,8085, 8088 and 8086 Processors • For Each Accepted Program Submittal, Insite™ Library Will Provide Either a One-Year Free Membership, Five Free Paper Tapes, or Three Programs on Diskette • Updates of New Programs Sent Bi-Monthly • Diskettes, Paper Tapes, and Listings Available for Library Programs Insite Intel's Software Index and Technology Exchange, is a collection of programs, subroutines, procedures, and macros written by users of Intel's microcomputers, single-board computers, and Intellec development systems. Thanks to customer contributions to Insite, Intel is able to make these programs available to all users of Intel microcomputers. By taking advantage of the availability of these general- purpose routines, the microcomputer design engineer and programmer can save many hours of programming and debugging time. The library of programs also serves as a good learning tool for those unfamiliar with Intel assembly language or the high-level languages for Intel's family of microcomputers. LIBRARY PROGRAMS AVAILABLE ON PAPER TAPE AND SINGLE OR DOUBLE DENSITY DISKETTE The following are trademarks of Intel Corporation and may be used only to identify Intel products: exp, CREDIT, Intellec, Multlbus, i, ISeC, Multimodule, ICE, iSeX, PROMPT, iCS, Library Manager, Promware,lnsite, MeS, RMX, Intel, Megachassis, UPI, Intelevision. Micromap, JoIScope and the combination of ICE, iCS, ISeC, ISeX, MeS, or RMX and a ~U~f~:~~~~~~~i'on 1980 22·1 9800033G inter INSITE™ USER'S PROGRAM LIBRARY MEMBERSHIP INSITE™ PROGRAM LIBRARY CATALOG Membership in Insite is available on an annual basis. Intel customers may become members through an accepted program contribution or membership fee. New members should use the membership form on the back of this data sheet. Each member will be sent the Program Library Catalog consisting of an abstract for each program indicating the function of the routine, required hardware and software, and memory requirements. PROGRAM LIBRARY SERVicE PAPER TAPES, DISKETTES OR SOURCE LISTINGS are available for every program in Insite. Diskettes are available on single or double density. Membership is not required to purchase or submit programs. PROGRAM SUBMITTAL Programs submitted for our revi~w must follow the guidelines listed below: 1. Programs must be written in a standard Intel Assembly Language or PLiM 80. These languages are documented in the following manuals: a. 8008iMCS~8 Assembly Programming' Manual #98-0198 b. 8080/8085, Assembly, Language Programming Manual #9800301C c. 8080/8085 Floating-Point Arithmetic Library User's Manual #98004528 d. PL/M-80 Programming Manual '#~8-2688 e. MCS-48 and UPI-41 Assembly Language Manual #9800255C I. FORTRAN-80 Programming #9800481 A Manual ,g. ,8086 Assembly Language Reference Manuai#9800640A" '" h. PLlM-86 Programming Manual #9800466A 2. A source listing of the program must be included. This must be the output listing of a compile or assembly. All accepted programs must be capable of compilation or assembly by Intel standard compilers or assemblers. No consideration will be given to partial programs or duplication of existing programs. 3. A test program which assures the validity of the contributed program must be included. This must show the correct operation of the program. 4. A source paper tape or diskette of the contributed program is required. This will be used for the reproduction of tapes for other members. User's Library members will be updated quarterly with abstracts of new programs submitted to Insite during the subscription period. For catalog and yearly subscription fee please refer to the Intel OEM Price List or contact the nearest Intel Sales Office. Complete the Submittal Form as follows: (please type or print) 1. Processor (check appropriate box). 2. Program Title: Name and brief description of program function. 3. Function: Detailed description .of operations performed by the program. Attach, additional pages if necessary. 4. Required Hardware: For example: TTY or Ports 0 and 1 Interrupt Circuitry 1/0 Interface Machine line and configuration for cross prod ucts 5. Required Software: For example: TTY Drive Floating Point Package Support s.oftware required for cross .prod ucts 6. Input Parameters: Description of register values, memory areas or values accepted from input ports. 7. Output Results: Values to be expected in registers, memory areas or on output ports. 8. Program Details: (for resident products only) a. Register modified b. RAM required (bytes) c. ROM required (bytes) d. Maximum subroutine nesting level 9 Assembler/Compiler Used: For example: PLiM 80 Intellec Macro Assembler FORTRAN 80 10. Programmer, Company and Address. AFN-Ol'40" insiteM'INTEL® USER'S LIBRARY SUBMITTAL FORM o 8008 0 8048 0 8080/8085 0 8086/8088 0 Other (Use additional sheets If necessary) Program Title Function Required Hardware Required Software Input Parameters Output Results Registers Modified: Programmer: RAM Required: Company: ROM Required: Address: Maximum Subroutine Nesting Level: City: State: Assembler/Compiler Used: Phone: © Intel Corporation, 1978 22·3 9800034·F AFN·OI446B insi~'USER'S LIBRARY MEMBERSHIP FORM I am interested in becoming a member of InsiteTM Enclosed is D Check D Money Order D Program Submittal NAME: COMPANY: ______________________________________________ SHIPTO: SEND TO NEAREST LOCATION: North America Europe Orient Intel Corporation User's Library 6·5000 Microcomputer Systems 3065 Bowers Avenue Santa Clara, California 95051 Ph. 408·987·8080 Intel International Corp. S.A. User's Library Rue du Moulin a Papier 51 Boite 1 B·1160 Brussels, Belgium Ph. 02·660·3010 Intel Japan K. K. User's Library Flowerhill·Shinmachi, East Bldg. 1·23·9 Shinmachi, Setagaya·ku Tokyo 154, Japan Ph. 813·426·9261 (PME & FSE) 813·426·9267 (CS & Fin.) Please refer to Intel OEM Price List for membership fee. 22·4 Microcomputer Workshops 23 Intel Mlcrocomputeli' Workshops Why Intel Training? EXPERIENCE Intel has been training engineers in the application of microprocessors and the development of microcomputer systems since the early 70's, and there are now many thousands of engineers creating the most advanced microcomputer systems as a direct result of successful training with us. Training in Microcomputers Whether your present involvement with microcomputers is a result of long-term planning or simply an exploratory project undertaken by your company in response to external circumstances, there exists an obvious and urgent need for you to familiarize yourself with this exciting new technology as quickly and painlessly as possible. If the microcomputer is, or is destined to become, a part of your working scene (and there is no field of manufacturing or data processing it will not touch sooner or later) then the importance of carefully planned training cannot be over-emphasized. A modest outlay in time and money now can save many weeks of self-study and could well prevent some very expensive mistakes during the initial development of your systems. VARIETY OF COURSES Intel Microcomputer Workshops offer training at three levels - introductory, intermediate and advanced. Your particular training requirement may involve just one or several courses, so we have taken care to ensure that each Workshop is a high quality training module that can either stand independently or integrate with other modules to form a complete coverage of our subject. The Workshops are constantly being updated to include the latest developmentsin devices and support software, and course materials are similarly reviewed on a regular basis - both for clarity ondcontent. PRODUCT KNOWLEDGE As the designers and manufacturers of the most widely accepted microcomputer products in the world, our lmowledge is both comprehensive and topical. Remember the saying about 'the horse's mouth'! EXTENSIVE MATERIAL Teaching aids include slide and video tape equipment. student notebooks and a wide range of printed materials which are designed to provide post-training assimilation and act as practical reference manuals in your own laboratory. "HANDS-ON" EXPERIENCE We believe that stUdents learn better by doing than by listening, so a sizeable proportion of course time is devoted to dynamic training via the Intellec MDS development system, appropriate single board computers, InCircuit Emulators (ICE), I/O units for programming exercises, and computer kits for design and debugging sessions. Each student therefore receives valuable 'hands-on' experience of the principles and techniques featured in the lecture sessions. 'Where is Intel Training? TRAINING CENTERS Workshops are scheduled nearly every week of the year in our three regional training centers: 23-1 AFN'01608A WhIch Workshops Should You Attend? BOSTON AREA Intel Customer Training 27 Industrial Ave. Chelmsford, MA 0 1824 (617) 256-1374 CHICAGO AREA Intel Customer Training Gould Center, East Tower 2550 Golf Rd" Suite 815 Rolling Meadows, IL 60008 (312) 981-7250 SAN FRANCISCO AREA Intel Customer Training 1350 Bordeaux Dr" SV3-1 Sunnyvale, CA 94086 ( 408) 734-8102 ADDITIONAL LOCATIONS Courses have been scheduled in 35 additional locations across the U.S" Canada, and Mexico. These cities include Los Angeles, Washington, Dallas, Minneapolis, New York, Atlanta, and Ottawa. Intel Workshops are also available in major European cities and Japan. (See local workshop brochure) CUSTOMER-SITE WORKSHOPS All workshops detailed in the following pages can, by special arrangement be presented with full laboratory equipment by Intel instructors at your facility. Considering the transportation and lodging savings, the breakeven point is typically 5-7 attendees. For further information about onsite training, please contact your nearest regional training center. EVENING WORKSHOPS If you cannot find time to attend our day-time workshops, check the schedule for our evening workshops. AFN:01608A Which Workshops Should You Attend? Recommended Sequence of Workshops As a DESIGN ENGINEER or SYSTEM ENGINEER with a good understanding of digital electronics, you might start with the MCS-48/49, MCS-51. MCS-80/85, or iSBC Workshops. If you lack the digital electronics background, start with the Introduction to Microcomputers Workshop. Unless you have working experience with microprocessor-based design and assembly language programming, you should attend the MCS-80/85 Workshop prior to attending the iAPX86,88 Workshops. As a PROGRAMMER. you may be ready to start with the iSBC, PASCAL, or PL/M Workshops: however, if you intend to use assembly language the MCS48/49, MCS-51. MCS-80/85, or iAPX86,88 Workshops should be attended first. We suggest that you also consider the Introduction to Microcomputers Workshop to gain basic knowledge of digital electronics and machine language, since these topics are usually much more important to the microcomputer programmer than to the minicomputer or large computer programmer. As a MANAGER. ADMINISTRATOR. or PROJECT MANAGER wishing an overview of this new field, the Microcomputer Concepts for Managers Workshop would be suitable: or if you want more details, the Introduction to Microcomputers Workshop is recommended. If you have sufficient working experience with microcom- - 23·2 puter hardware and software you might attend any of the Intel Workshops without first attending a prerequisite workshop: however, since microcomputers are new to many people, we recommend the sequence indicated in the chart for those who want to advance their microcomputer education. Announcing .... New MCS-5PM Microcontroller Workshop This new 4-day workshop will give a boost to your first 8051 based project or allow you to evaluate the 8051 , The workshop covers the architectture, instruction set. and software development package of this new single chip microcontrolier, (See page 18) New Data Communication Chips DeSign Workshop This new workshop focuses on bit-serial synchronous communication modes and devices, and provides both an overview and hands-on lab for data communications, (See page 19) NewIEEE-488 GPIB Workshop This course introduces the concepts and specifications of the IEEE-488 General Purpose Interface Bus by deSign and implementation with the Intel IEEE-488 chip set. (See page 19) New ICE-85 ™ User's Workshop This 3-day workshop provides intensive and comprehensive training on the ICE-85 InCircuit Emulator hardware/ software debug tool through lecture and hands-on laboratory, (See page 21 ) New Training Center FaCilities and Labs Responding to your request. we have significantly increased the number of Inteliec Microcomputer Development Systems and other lab 23-3 equipment in our training centers, We had to move to new facilities to accomplish this, but our goal is to deliver the best training you can get your hands-on, New Workshop Vans for More Hands-On at Your Site We have outfitted three vans with new Inteliec Microcomputer Development Systems and ICE In-Circuit Emulators, so we can easily bring our extensive workshop lab equipment to your facility, New Video Tape Library ICE CONCEPTS Intended for users of an InCircuit EmUlator, this 22-minute color video tape demonstrates the unique capabilities of ICE debug tooL including the debugging of an actual traffic control application, INTELLEC® MICROCOMPUTER DEVELOPMENT SYSTEM OPERATION Intended for users of an Inteliec 220, 225, 230, 235, 240, or 245 system. This 20-minute color video tape shows how to power-on the system, handle the floppy disk, edit a file with the CRT editor CREDIT, and use simple ISIS-II commands like COPY, DELETE, and DIRECTORY Both are available in 3/4" and 1/2" video tape cassette formats at $250,00 per copy, Order from the San Francisco Area Training Center, (408) 734-8102, AFN:01608A Microcomputer Concepts for Managers Workshop Course Description • Microcomputer terminology. buzzwords. and fUndamental programming concepts explained • Hardware/software development process outlined • Microcomputer appl1calions reviewed • Lab sessions on SDK-85 and in programming in BASIC on the Intellec Series II MIcrocomputer Development System Attendees • Project leader. manager. or administrative person who needs overview of microprocessor and microcomputer concepts Length: 2 Days Tuition: $395 $325 (Group rate) Introductory 23-4 Course OUtUne DAY 1 Terminology Microcomputer System Organization MemolY Computer Selection Lab: Using SDK-85 DAY 2 Introduction to Software Development System Overview Single Board Computer OverView Rel1ablllty, Testing, Timing Project Chronology Appl1catton Topics Lab: Programming In BASIC IntroducHonto Mlcrocomputen Workshop Course Description • Fundamental computer concepts and terminology introduced • Operation oj the Intel 8085 microprocessor explained • 8085 assembly language programming • Stacks, subroutines, interrupts and I/O interlacing introduced • Lab sessions on SDK-85 System Design K1t • An SDK-85 K1t (valued at $300) is yours to keep Attendees Course OuWne DAY I Introduction to MicroelectrOnics Computer Concepts Computer Languages Using the SDK-85 Lab: Kit Operation and Programming Moving Data DAY 2 Delay Loops Lab: Audio Oscillator using Digital Techniques Subroutines Stq:ck Operation Lab: Using Subroutines DAY 3 LOgic Instructions Engineers, scientists, or other Lab: Handshaking Techniques technical people with limited Addition computer or digital electronics Lab: Multi·Function Programs background Microprocessor Operation Included in the price of the course is an SDK·85 kit which includes: 3 MHz 8085 CPU (enhanced 8080) Keyboard - 24 keys Display - 6 digits Monitor ROM 2048 bytes RAM Memory 256 bytes 38 I/O lines Teletype interface Complete documentation Length: 4 Days Tuition: $895 (includes SDK-85K1t) $750 (Group rate) Introductory 23·5 DAY 4 Interrupts Memory Operation and Address Decoding Programmable Peripheral Chips Lab: Chip Programming Excercises Introduction to the Development System, ICE, Assembler, and Higher Level Languages Course Summary and Review MCS®-80/85 System Design Workshop Course Description • 8085 arChitecture explained . indetail • Assembly language programming for 8080/8085 • Design and development of ' I t 18080 systems usmg n e . •8085 chips • Interfacing and programming techniques • Lab sessions "hanciS~on" using the Intellec Series Ii' , . IDlcrocomputer development system . •. ICE-85 In-Circuit Emulator used to debug programs Attendees • Design engineer or programmer who is familiar . with binary numbers and l~gic functions • Prior attendance at Introduction to Microcomputers Workshop or equivalent knowledge is recommended Length: 5 Days Tuition: $895 $725 (Group rate) Course- Outline DAY 1 Introduction to Microprocessors Assembly Language InstructiOns Programmed Input and Output Microcomputer Development System Monitor Lab: Using System Monitor DAY 2 Microcomputer Development System Disk Operating System CREDIT Text Editor and Macro Assembler The Processors Lab: Using Text Editor and Assembler D=-A=Y==3===------Stacks and Subroutines Interrupts Input and Output Techniques Programming Techniques Lab: In-Circuit Emulator Introduction DAY 4 In-Circuit Emulator 8155, 8355,8185 Peripherals Memory Interfacing Lab: USing 8085 In-Circuit Emulator . DAYS 8255 and 8251A Peripherals Tools for Modular Program Development Chips vs, Boards Preview 018088 8080/8085 23-6 AFN:01608A ISBC ™ Single Board Computer Workshop Course Description Course OUtline • Covers state of the art microprocessors and single board computer systems • Explains operation and programming of selected SBC products including: iSBC80/30, iSBC80/24, iSBC86/ l2A • Describes design, configuration and implementation of single board computer systems for industrial applications • Intel Development System used in laboratory sessions • Laboratory sessions also implement a variety of iSBC system configurations. • ICE In-Circuit Emulator used to aid system debugging • Includes field service, fault location, and maintenance topics DAY] Survey of Intel Single Board Computers, Languages, and Operating Systems Overview of the Intel ISBC 80/30 Processor Board and Associated Peripheral Interface Chips The 80S5A Microprocessor Fundamentals and Assembly Language Programming Techniques Designing with the Intel 8255 Programmable Peripheral Interface Chip Lab: iSBC Monitor and Parallel I/O Capability of iSBC 80/30 Processor Board DAY 2 Intellec Development System Credit.- CRT Based Text Editor ASM 80 Assembler/PLM-80 Programming Tools for Modular Programming - (link, locate, include and submit) ICE-85, In-Circuit Emulator Lab: Development of Programs for iSBC Processor Boards via Development System DAY 3 DeSign and implementation of a Serial CommunicationSystem iSBC 544 Intelligent Communication Controller iSBC 80/24 Single Board Computer and Multimodule Expansion Boards Multibus Specifications and Architecture Lab: Development Programs to operate on iSBC Processor Boards, Multimodule I/O Expansion and Memory Boards DAY 4 iSBC 86/ 12A Single Board Computer iSBC Memory Boards, RAM, PROM, EPROM, and Bubble Memory Boards Attendees • System engineer or programmer who will be using iSBC Products • Some programming experience is required, preferably 8085 assembly language; PL/M workshop is helpful, but not required Length: 5 Days Tuition: S895 S725 (Group rate) AFN O]608A 23·7 iSBC Parallel I/O Expansion Boards, iSBC 519, iSBC 569 iSBC Analog I/O Boards, iSBC 711,724, and 732 iCS Industrial Control System and Signal Conditioning/ Terminator Panels Lab: iSBC 544 CommunicationLab DAYS FSP and Model 810 Software Development Modules RMX/80 Real-Time Multitasking Executive Service and Maintenance of iSBC, iCS Systems Future iSBC Products Lab: iSBC 544, iSBC 80/30 Multitasking Lab 8080/8085,Perlpheral~ps PL/M-SO Language/ ~ftwale Design Workshop Course Description Course OuWne DAYl • Learn PL/M programming PL!M Overview for 8080 and 8085 microDeclaration Statements processors Sequential Statements • Design, implement, and Conditional Statements debug PL/M-80 modular Loop Statements software Program Preparation • LINK multi-modules using Lab: Microcomputer Development libraries . Systems Introduction • Develop software for disk DAY 2 file handling .Intellec Series II Development • "Hands-on"Jaboratory sesSystem sions using the Intellec Series ISIS-II Commands II microcomputer develSystem MOnitor opment system CREDIT Editor Lab: Implement Program for • In-Circuit Emulator used for Oven Control system debugging Attendees • Design engineer orpro-· grammer • Prior programming experience will assist in obtaining maximum benefit from the course • Introduction to Microcomputers or MCS-80/85 System Workshops recommended Length: 5 Days Tuition: $895 $725 (Group rate) DAY 3 Procedures Compiler Controls Linking Modules Locating Submit Command Lab: Design and Implement OnLine Editor DAY 4 In-Circuit Emulation Libraries Lab: Use ICE-85 Module on SDK85 Kit DAYS System Calls Interrupts Reentrancy Lab: Design and Implement File Handling Program SOSO/SOS5 23-8 AFN:01608A RMX/80™ Operating System Workshop Course Description • Operation and implementation of Intel RMX/80 RealTime Multi, Tasking Executive • Basic concepts of multitasking are explained • Concurrency of tasks, asynchronous events, priorities, scheduling, resource sharing, interrupts, and inter-task communication discussed • Lab sessions on task writing and system generation using iSBC Processor Boards • In-Circuit Emulator used to aid system debugging Course Outline DAYl Introduction to Multi-Tasking What is RMX/80? Review 01 Development Process Lab: RMX/80 Operation DAY 2 RMX/80 Model Implementing RMX/80 Tasks Configuring a System Lab: Writing Tasks and Configuring System DAY 3 RMX/80 Extensions: Terminal Handler Task Priorities Lab: Implementing a Terminal Handler Task Attendees DAY 4 • System engineer or programmer who will be using RMX/80 in iSBC system application • PL/M-80 Language/Software Design Workshop or equivalent knowledge is required ( ego based variables, structures, and declare literally) • Familiarity with Intellec Microprocessor Development System is required RMX/80 Extensions: The Debugger and The Free Space Manager Lab: Implementing RMX Extensions DAYS RMX/80 Extensions: The Disk System Lab: Implementing RMX Extensions Length: 5 Days Tuition: S895 S725 (Group rate) 8080/808-5 AFN:01608A 23-9 IAPX 86,88 System Design Workshop Course Description Attendees • Design systems lor 8086/8088 • Develop programs using 8086 assembly langUage • Lectures cover CPU, addressing modes, Interrupt system, timing, I/O • Laboratory "hands-on" uses Intellec Series II Microcomputer Development System and SDK-86 Kit • ICE-86 In-Circuit Emulator introduced as soltware debug tool • Workshop lor design . engineer or programmer who will use or evaluate 8086, 8088, or iSBC 86/ 12A • Prior experience with microcomputers and a working knowledge 01 assembly language is required, and the MCS-85 workshop is recommended Length: 5 Days Tuition: $895 $725 (Group rate) Course OuWne DAYl Introduction to Assembly Language Instructlon 8086/8088 CPU's I/O Operations System Design Kit (SDK-86) . Lab: Using the SDK-86 and the Serial Monitor DAY 2 Development System Addressing Modes Programming Exercises Lab: Using the 8086 Assembler and the Development System DAY 3 Procedures String Operators Interrupt System Lab: Programrn1ngwith Procedures and the String Operators DAY 4 Programming for Large Systems CPU Timing 8086/8088 Support Chips Lab: Programming with Multlple Segments DAY 5 Programrn1ng with Multlple Modules Introduction to ICE-86 Introductlon to Multlprocessing and the Multlbus 8086/8088 23-10 AFN:Q1608A ICE-86/88™ and IAPX 86/21 Worksh@~ Course Description Course OUtline • Detailed discussions on assembler directives, segmentation, library • The design and programming 01 large systems • 8089 I/O Controller explained . • "Hands-on" lab sessions use Intellec Series II Development System and iSBC 86/ l2A Single Board Computers • ICE-86 In-Circuit Emulator used to debug programs DAY 1 Attendees • Programmer or system designer who needs complete understanding 01 8086 assembly language programming and ICE-86 debugging techniques • Knowledge 01 tntellec Development System assumed • Prior attendance at MCS86/88 Workshop required Length: 5 Days Tuition: $895 $725 (Group rate) ArN U1608/\ Review of the 8086/8088 Advanced Programming Topics Linkage . The Software Development Process Lab: PL/M-86 Linkage DAY 2 Execution Vehicle Considerations 15BC 86/1 2A Board 8259A Peripheral Chip Programming Introduction 10 ICE-86 Emulator Module . Lab: Interrupt Handling DAY 3 Advanced ICE·86 Module Features Interrupt Structures Multiprocessor Topics Lab: ICE-86 Introduction DAY 4 .. 8086 Component Family Review . Multibus Arbitration Logic Inlroductionlo Input/Output Processors Lab: ICE-86 DAYS Advanced 8089 Topics Application Topics 23·11 8086/8088 PL/Y-86 Language/Software Design Workshop Course Description • Learn PL/M programming jor 8086 microprocessor • Design, implement. and debug PL/M-86 modular software • LINK multi-modules using libraries • "Hands-on" laboratory sessions using Intellec Series II Microcomputer Development System and SDK-86 Design Kit • ICE-86 In-Circuit Emulator is introduced as software debugging tool Attendees • Design engineer or programmer who is ready to use high level language with Intel 8086 or iSBC 86/12A • MCS-86/88 workshop recommended as prerequisite jor understanding the underlying structure oj 8086 microprocessor Length: 5 Days Tuition: $895 $725 (Group rate) Course OUtline DAYl Introduction Declaration Statements Data Elements Data Types Operators, Operations, and Priorities Execution Statements Lab: Microcomputer Development System and SDK-86 DAY 2 Procedures ISIS-II Disk Operating System CREDIT Editor PL/M-86 Compiler Options Lab: Impiement Console I/O Routines DAY 3 Data References Blocks Link and Locate Programs Built-In Facilities Lab: Design and Implement Modular Line Editor DAY 4 Using Libraries Character String Handling Interrupt Procedures Reentrant Procedures Lab: Design and Implement Command Line Interpreter DAYS ICE-86 Module Discussion of Selected Programs 8086/8088 23-12 AFN:01608A lRMX 86™ OperaHng System Workshop Course Description • Introduction to iRMX 86 Real-Time Mulll-Tasking Executive principles and implementation • Basic concepts of multitasking me explained • Concurrency of tasks, asynchronous events, priorities, scheduling, resource sharing, interrupts, andinter-task communication discussed • Lab sessions on task writing and system generation using iSBC Processor Boards • In-Circuit Emulator used to aid system debugging Attendees • System engineer or programmer who will be using iRMX 86 on an iSBC 86/ l2A Single Board Computer. • PL/M 86 Language/Software Design Workshop or equivalent knowledge is required (eg. based variables, structures, and declare literally) • Familiarity with Intellec Series II Microcomputer Development System is required Course Outline DAYl Real-Time Concepts The iRMX 86 Model OVerview of iRMX 86 Nucleus The Software Development Process Lab: Write a single task for a system DAY 2 The IRMX 86 Nucleus The Terminal Handler Lab: Write multiple tasks for a system which uses the Terminal Handler DAY 3 Interrupts The Debugger Lab: Write Interrupt task DAY 4 The Configuration Process Installing IRMX 86 Lab: Write configuration modules DAYS OVerview of I/O System Future iRMX 86 Features Lab: Write task for tile I/O Length: 5 Days Tuition: $895 $725 (Group rate) --------====-============= 8086/8088 AI'N,OI608A 23-13 PASCAL Programming Workshop Course Description • Learn PASCAL programming on Intellec Development Systems • Design, implement. and debug PASCAL modular software II Learn Structured Programming Concepts • "Hands-on" laboratory using the Intellec Series II microcomputer development system and PASCAL-SO or PASCAL-86 software Attendees • Design engineer, scientist. or programmer • No prior programming experience necessary Length: 5 DaYs Tuition: $895 $725 (Group rate) Course OUWne DAY] PASCAL Overview Block Structuring Lab: Microcomputer Develop' ment System Introduction Data Storage PASCAL Standard Data Types Program Construction in PASCAL Assignment Statements DAY 2 ISIS-II Disk Operating System Credit Editor PASCAL-80 Run Time System Lab: DeSign and implement PASCAL Program Conditional Statements Iteration·Loops Procedures and Functions Lab: PASCAL Program using Procedures DAY 3 Scalar Data Types Structured.Data Types: 1. Sets 2. Arrays 3. Strings 4. Records Lab: PASCAL Program using Structured Data Types DAY 4 Files File Type Built·in Procedures and Functions to Manipulate Files Textfiles Interactive Files Untyped Files Lab: PASCAL program using File Data Structures DAYS Dynamic Data Structures Advanced Programming Topics Advanced Design Topics Lab: PASCAL Program using Dynamic Data Structures PASCAL·86 Compiler 8080/8085,8086/8088 23-14 AFN:01608A 2920 Signal Processor Workshop Course Description • Design systems using 2920 • Develop programs using 2920 assembly language • Use Microcomputer Development Systems software support tools for program assembly and simulation • Investigate applications for 2920 signal processor Attendees • Design engineer who is familiar with analog filter design. frequency domain analysis and S-Plane representation • Prior digital design or digital filter experience recommended Length: 4 Days Tuition: 5795 $625 (Group rate) Course OUtline DAYl Overview of 2920 Instruction Set Binary Arithmetic Simulator Lab: Sawtooth Generator VCO DAY 2 Constant Scaling 2920 Assembler Constant Multiplication Simulator Output Lab: Low Pass Filter and Two Pole Filter DAY 3 Variable Multiplication Variable Division Signal Processing Application Compiler Lab: USing the Compiler DAY 4 Review Sample Techniques Noise Aliasing Application Discussion Lab: Open Single Chip 23-15 OO~CfJJ® c~/~/GJ® ~iem. [Q)®ffiQ~ ~@f(~OP Course Description o Design and develop a system using Intel MCS-48/49 single chip microcomputers o Programming in 8048 assembly language o Explanation of Intel 8048 architecture, system timing and input/output design o Lab sessions provide "hands-on" experience using PROMPT-48 and Intellec Series II microcomputer development system to develop 8048 programs o ICE-49 In-Circuit Emulator used for system debugging o Intel 802 L 8022, and 8041 chips are discussed Attendees o Design engineer or programmer who is familiar with binary numbers and digital logic o Prior attendance at Introduction to Microcomputers Workshop or equivalent knowledge recommended Length: 5 Days Tuition: $895 Course Outline DAYl Microprocessor System 8048 Overview Assembly Language Instructions PROMPT-48 DeSign Aid Lab: Software Development USing PROMPT-48 Design Aid DAY 2 Assembly Language Instructions Subroutines Development System Text Editor and Macro Assembler Lab: Development System Introduction DAY 3 System Timing Interrupts Expanding I/O Lab: Programming Using Timer and Interrupts DAY 4 Expanding Memory Peripheral Interfacing Using 8279,8251,8255,8355,8155 In-Circuit Emulator Lab: Debugging USing ICE-49 Module DAY 5 8021, 8041A, 8022 Analog Interfacing $725 (Group rate) 23-16 AFN OI608A MCS®·51 Mlcrocontroller Workshop Course Description • Program in 8051 Assembly Language and discuss system design with 8051 components • Explanation of MCS-51 Architecture including: - Boolean Processor - I/O Port Structure - Timers - Serial Port - Interrupts - Memory Types and Memory Spaces • "Hands-on" Lab sessions covering the MDS Development System. the ISIS Operating System. the CREDIT text editor. the MCS51 Assembler. and execution vehicle. • Review of some 8048 concepts. Attendees This course is designed for the design engineer who wants to become familiar with the 8051 family of components. Prior knowledge of Intel components is not required. The attendee should be familiar with digital logic functions and have some programming experience. The Introduction to Microcomputer Workshop is recommended. Course OuWne DAYl Introduction Programming and Instruction Set Representation Internal Data Memory Lab Program Sequencing Immediate Data Lab: Tra1flc Light Control using Delays DAY 2 ISIS-II CREDIT MCS-51 Assembler Lab: 7-segment display Subroutines Lab: Tral1lc Light Controller Revisited using Subroutines DAY 3 Port Structure Register Addressing Boolean Processor Lab: Multiplexing 7-segment display Indirect Addressing Lab: Using Table Look-up Techniques DAY 4 Interrupts 8051 Timers Serial Port Lab: Setting up and using the Serial Port to communicate with a CRT Arithmetic Instructions Accessing External Memory Application Topics Length: 4 Days Tuition: $795 $625 (Group rate) Single Chip AFN:0 160BA 23-17 Data Communication Chips Workshop Course Description • Reviews data communication fundamentals • Describes Asynchronous and Synchronous bit serial communication protocols: Bi-Synch, HDLC/SDLC, X,25 • ut1l1ze Intel chips in laboratory: 8251 USART 8273 HDLC/SDLC Controller • Explain new Intel chips for data communication: 8256 and 8274 • Discusses RS232, Local network and ether net Attendees • Intended for the design engineer, service engineer, or programmer who needs to understand how serial data communication is used in a distributed system, • The Introduction to Microcomputer Workshop or equivalent knowledge is required, IIIE-488 GPIB Chips Workshop Length: 4 Days Tuition: $795 $625 (Group rate) Course OUtline DAYl History 01 Data Comm, Communication Hierarchy Non-standards Asynch Lab: USing Intellec DAY 2 Byte Synch, Comm, BI-synch RS232 Lab: Using SBC 544 DAY 3 Bit Synchronous HDLC/SDLC LOOp mode X25 Protocol Laboratory Demonstration DAY 4 Local networks Ether-net Star Con1iguratlons Application discussion Course Description • Describes the General Purpose Interface Bus char• The Introduction to Microacteristics including protocol, computer Workshop or equivalent knowledge is electrical, and mechanical specifications required, The Intellec • Explains systems application Development System Operexamples and implemenation Workshop is recomtation guidelines mended, • Includes programming and Length: 4 Days use of: Tuition: $795 8291 GPIB Talker/Listener $625 (Group rate) 8292 GPIB Controller 8293, 8296, 8297 Transceiver Topics and Interface IEEE-488/GPIB OVerview iSBC 80/24 and IEEE 488 Intel Chip Set OVerview Multi-module Hardware Considerations Attendees Peripheral Chips • Design engineer or programmer who has prior assembly language or PL/M programming experience 23-18 Programming Examples Bus Functions Message Protocols Interrupt and DMA Operation Servicing Requests ISBC Intedace Considerations Intellec® Development System Workshop Course Description • Comprehensive coverage of ROM based system monitor. ISIS-II Diskette Operating System. and CREDIT text editor • Introduction to FORTRAN-80. LINK/LOCATE. system monitor debugging techniques. In-Circuit Emulation (ICE-85 used as an example ). and Universal PROM Programmer • System installation and checkout Attendees • Programmer or design engineer who will be using Intellec Series II Development System to develop. debug. and integrate hardware/software • Managerwhowantsto understand how this tool can help get a project completed faster Course OUtline DAYl Introduction System Overview System Installation Introduction to ISIS-II Using CREDIT Text Editor DAY 2 Introduction to FORTRAN-80 Compiling a Program Introduction to LINK/LOCATE System Monitor ICE-85 DAY 3 ICE-85 (Continued) User Maintenance Programming Aids Universal PROM Programmer Course Review Length: 3 Days Tuition: $595 $475 (Group rate) Development System ArN,OI608A 23-19 ICE-as™ Users Workshop Course Description Topics • Comprehensive coverage 01 In-Circuit Emulation using ICE-85 • Debugging 01 Assembly and PL/M Programs .. • Extensive Hands-on Laboratory practice with instructor's guidance. ICE Concept Installation Use of ICE Manuals Documentation Command Language Memory Mapping Emulation Control with BreakpOints Trace Data Collection Modes Data Display Formats Debugging Strategies Multi-ICE Comparison of ICE-48, ICE-41, and ICE-85 Attendees • Programmer or design engineer who will be using an ICE Product (lCE-48, ICE: 4 L or ICE-85) and who needs to develop expertise· • Prior programming experience with 8085, and use 01 a development system is assumed. Introduction to Microcomputer Workshop or equivalent is required Length: 3 Days Tuition: 5595 5475 (Group rate) Development System 23-20 AFN:01608A Training Center Information SAN FRANCISCO AREA 1350 Bordeaux Drive, Sunnyvale, CA 94086 408-734-8102 INTEL HOTELS n.ar training center: €) Sundownsr ® Captains Cove Motel Sunnyvale, CA Sunnyvale, CA 408·734·9900 408·735·7800 © Holiday @ Marriott Hotel Inn Sunnyvale, ·CA 408·245·5330 800·238·8000 Santa Clara, CA 40B·988·1500 800·228·9290 CHICAGO AREA Gould Center, East Tower 2550 Golf Road, Suite 815, Rolling Meadows, IL 60008 312-981-7250 BOSTON AREA 27 Industrial Avenue, Chelmsford, MA 01824 617-256-1374 TO MILWAUKEE ROLLING MEADOWS ® 1 ® EUCLID AVE. O'HAREAIRPORT HOTELS nelr training center: ® Arlington Park Hilton Arlington Heights, IL 312·394·2000 ® Howard ~ohnson's Palatlne,IL 312·359·6900 800·654·2000 TaCHICAGO HOTELS near training center: Howard Johnson's CD Town House Motor Inn Chelmsford, MA Lowell, MA 617·256·7511 617·455·5606 800·654·2000 ® ® Holiday Inn Rolling Meadows, IL 312·259·5000 BOO·238·BooO 23·21 o Howard Johnson Burlington, MA 617·272·6550 800·654·2000 Registration To enroll in a scheduled workshop, call the appropriate Intel Training Center between the (5) San Francisco (C) Chicago (B) Boston hours of 8-12 and 1-5, and ask for Customer Training. (408) 734-8102 (312) 981-7250 (617) 256-1374 ( also for other West Coast locations) ( also for other Mid West locations) ( also for other East Coast locations) Confirmation Group Rate Tuition Policy A confirmation letterwill be sent to you specifying details of workshop time, location, directions, and lodging. Tuition is at the group rate when an organization enrolls 3 or more people in the same . course, one person in 3 or more courses, or some combination thereof. Groups are eligible for this discount only when enrollment and pre-payment are made together. Payment DUE BEFORE THE WORKSHOP BEGINS, Tuition and schedule subject to change. Since enrollment is limited, registration 4-8 weeks in advance is recommended. Product Service 2~.it i~C;} .• INTEL PRODUCT SERVICE Today, it's essential to have dependable data processing and information storage equipment. If there should be an equipment problem, customers contact the nearest Intel service location. If the customer location is within Intel's service area, an Intel Customer Engineer is dispatched to the site as quickly as possible. Once there, using advanced diagnostic tools and sophisticated test equipment, the Customer Engineer will determine the trouble and the replacement parts needed. With Intel's vast inventory of replacement parts, the right part is always available on the shortest notice, and the Customer Engineer is able to make repairs quickly and verify performance. To insure trouble-free performance, every Intel product is engineered and manufactured to exacting standards. But sometimes, even the finest components may malfunction. It's then that Intel Product Service delivers fast, economical, quality maintenance and service support to keep vital projects on schedule. Intel is committed to providing a total service support package through a wide variety of service offerings available from Intel Product Service. Intel Product Service takes pride in its capabilities and in the entire Intel systems product line, and is dedicated.to total customer satisfaction. Product Service Alternatives Intel offers customers a number of service alternatives ... all at reasonable prices and featuring the quality expected of the industry leader. First, there's the Maintenance Agreement, which guarantees maintenance at the customer's site plus parts replacement and labor at no extra charge beyond an easy-to-budget, fixed monthly rate--all billed against one purchase order. The Maintenance Agreement features preventive maintenance which helps keep emergencies at a minimum. But should an emergency arise, a Customer Engineer is sent to the site immediately. Customer Is Assured Maximum Equipment Performance The Intel Product Service team is a skilled group capable of solving any problem, either by phone or on-site. All service needs (including emergency service and preventive maintenance) are handled quickly and efficiently by Intel's Customer Engineers, supported by district, regional and factory specialists. This assures the customer of minimum downtime and maximum equipment performance. Immediate Availability of Service and Parts Working from field service offices throughout the United States, Canada and abroad, Intel's Customer Engineers provide maintenance agreement customers with equipment installation and regularly scheduled preventive maintenance, including automatic installation of engineering changes as they occur. 24·1 Toll· Free Service Hotline Of course Intel provides service for every system it sells. Thus,site service, parts replacement and repair are also available without a Maintenance Agreement. However, the.site must be within a reasonable distance of an Intel field service location, and all charges are paid as they are incurred. In the United States, Intel's toll-free service Hotline is a direct connection to service support specialists who can help immediately. If on·site service is available, they direct the customer to the nearest Intel field service location. If not, Hotline For customers not located in an Intel service area, or for those who prefer direct factory service, an Intel Direct Return Authorization enables the customer to return parts direct to Intel for repair, refurbishing and upgrade services by its factory experts. This service is offered with or without contract. (With contract, one purchase order covers all returns. Without contract, a separate purchase order is needed for each individual return.) specialists can usually help locate the trouble ... and in· dicate how to make the necessary repairs. Whichever service alternative is chosen, the customer is assured fast, affordable service. Intel offers customers the total service they need··that is one of the most important benefits of buying Intel products. When distance from an Intel field location is too great, the Before Return Replacement contract is the logical solu· tion for customers. To allow them to save valuable time and make repairs as soon as possible should trouble strike, a call via Intel's Hotline puts the customer in direct contact with support specialists who can determine which part is needed to repair the system. The part is then sent immediately··before the return of the old part to Intel. This service is also available with or without contract. 24·2 intel· U.S. AND CANADIAN SERVICE OFFICES 3065 Bowers Avenue Santa Clara, California 95051 Tel: (408) 987·8080 TWX: 910·338·0026 TELEX: 34·6372 800-528-0595 TOLL-FREE U.S. HOT-LINE NUMBER For service in Arizona and Canada call (602)869-4600 CALIFORNIA MARYLAND OREGON CANADA Intel Corp. 1601 Old Bayshore Hwy. Suite 345 Burlingame 94010 Tel: (415) 692·4762 TWX: 910·375·3310 Intel Corp. 7257 Parkway Drive Hanover 21076 Tel: (301) 796-7500 TWX: 710-862-1944 Intel Corp. 10700 S.W. Beaverton·Hilisdale Hwy. Suite 22 Beaverton 97005 Tel: (503)641·8086 TWX: 910-467·8741 Intel Corp. 50 Galaxy Blvd. Unit 12 Aexdale, Ontario M9W4Y5 Tel: (416) 675·2105 Telex: 069·89278 PENNSYLVANIA Intel Corp. 39 Hwy. 7, Bell Corners Ottawa, Ontario K2H8R2 Tel: (613) 829·9714 Telex:053-4115 Intel Corp. 2000 E. 4th Street Suite110 Santa Ana 92705 Tel: (714) 835·2670 TWX: 910·595·2475 Intel Corp. 7670 Opportunity Road San Diego 92111 Tel: (714) 268·3563 Intel Corp. 3375 Scott Blvd. Santa Clara 95051 Tel: (408) 987·8068 Intel Corp. 5530 N. Corbin Tarzana 91356 Tel: (213) 708·0333 COLORADO Intel Corp. 650 South Cherry Suite 720 Denver 80222 Tel: (303) 321-8086 TWX: 910·931·2289 FLORIDA Intel Corp. 1001 N.W. 62nd Street Suite 406 FI. Lauderdale 33309 Tel: (305) 771-0600 TWX: 510·956·9407 Intel Corp. 5151 Adamson SI. Orlando 32804 Tel: (305) 628-2393 GEORGIA Intel Corp. 3300 Holcombe Bridge Rd. Suite 225 Norcross 30092 Tel: (404)449·0541 ILLINOIS Intel Corp. 2550 Gall Road Suite815 Aolling Meadows 60008 Tel: (312) 981-7230 TWX: 910·253·1825 MASSACHUSETTS Intel Corp. 27 Industrial Avenue Chelmsford 01 824 Tel: (617) 667-8126 TWX: 710·343·6333 MICHIGAN Intel Corp. 26500 Northwestern Hwy. Suite 401 Southfield 48075 Tel: (313) 353·0920 TWX: 810·224-4915 Intel Corp. 510 Pennsylvania Ave. 3rd Floor Fort Washington 19034 Tel: (215)641·1000 TWX: 510-661·2077 TEXAS MINNESOTA Intel Corp. 313 E. Anderson Lane Suite 314 Austin 78752 Tel: (512) 454·3628 TWX: 910-874-1347 Intel Corp. 7401 Metro Blvd. Suite 355 Edina 55435 Tel: (612) 835·6722 TWX: 910·576·2867 Intel Corp. 2925 L.B.J. Freeway' Suite 175 Dallas 75234 Tel: (214)241-2820 TWX: 910-860·5617 MISSOURI Intel Corp. 502 Earth City Plaza S'uite121 Earth City 63045 Tel: (314)291-1990 Intel Corp. 6420 Aichmond Avenue Suite 280 Houston 77057 Tel: (713) 784·1300 TWX: 910·881·2490 VIRGINIA NEW JERSEY Intel Corp. 2460 Lemoine Avenue . Ft. Lee 07024 Tel: (201) 947·6267 TWX: 710·991·8593 Intel Corp. 7700 Leesburg Pike Suite412 Falls Church 22043 Tel: (703) 734·9707 TWX: 710·931·0625 OHIO WASHINGTON Intel Corp. Chagrin-Brainard Bldg. 300 28001 Chagrin Blvd. Cleveland 44122 Tel: (216) 464·2736 TWX: 810·427-9298 Intel Corp. 1603116th Ave. N.E. Suite114 Bellevue 98005 Tel: (206) 232·7823 TWX: 910·443·3002 Intel Corp. 6500 Poe Avenue Dayton 45414 Tel: (513) 890·5350 TWX: 810·450·2528 WISCONSIN Intel Corp. 150 S. Sunnyslope Road Suite 148 Brookfield 53005 Tel: (414) 784-9060 KANSAS Intel Corp. 9393 W. 110th Street Suite 265 Overland Park 66210 Tel: (913) 642-8080 This list of service offices is accurate as of the date of printing. However, new offices are being added as required. 24-3 intJ u.s. AND CANADIAN SALES OFFICES 3065 Bowers Avenue Santa Clara, California 95051 Tel: (408) 987·8080 TWX: 910·338-0026 TELEX: 3~·6372. . ALABAMA Intel Corp. aDa Williams Avenue, S.W. Suite 1422 Huntsville 35801 . T.~I:,~~O~L~3~.~.~~~ ARIZONA Intel Corp. 10210 N. 25th Avenue, Suile 11 Phoenix 85021 Tel: (602) 997-9695 BFA 4426 North Saddle Bag Trail Scottsdale 85251 Tel: (802) 994-5400 CALIFORNIA Intel Corp. 7670 Opportunity Rd. Suite 135 San Diego 92111 Tel: (714) 268·3563 Intel Corp,' 2000 East 4th Street Suite 100 Santa Ana 92705 Tel: (714) 835·9842 TWX: 910·595·1114 Intel Corp.' 6530 Corbin Ave. Suite 120 Tarzana 91356 Tel: (213) 708·0333 TWX: 910·496·2045 Intel Corp.' 3375 Scott Blvd. Santa Clara 95051 Tel: (40B) 987·808e TWX: 910·339·9279 910,338·0255 Earle Associates, Inc. 4617 Ruffner Street Suite 202 San Diego 92111 Tel: (714) 278·5441 Mac·1 P.O. Box 1420 Cupertino 95014 Tel: (406) 257·9660 Mac·1 558 Valley Way Calaveras Business Park Milpitas 95035 Tel: (408) 946·6665 Mac·1 P.O. Box 8763 Fountain Valley 92708 Tel: (714) 839·3341 Mac·1 1321 Centinela Avenue Suite 1 Santa Monica 90404 Tel: (213) 829-4797 Mac-I 20121 Ventura Blvd., Suite 240E Woodland Hills 91364 Tel: (213) 347-5900 COLORADO Intel Corp." 650 S. Cherry Street Suite 720 Denver 80222 Tel: (303) 321·6086 TWX: 910·931·2289 CONNECTICUT Intel Corp. Peacock Alley 36 Padanaram Road Danbury 06810 Tel: (203) 792·8366 TWX: 710-456-1199 EMC Corp. 48 Purnell Place Manchester 06040 Tel: (203) 646·8085 FLORIDA. Intel Corp. 1001 N.W. 62nd Street, Suite 406 Ft. Lauderdale 33309 Tel: (305) 77H1600 TW)C: 510·~.~.~·9497 FLORIDA (coni.) Intel Corp: 5151 Adanson Street, Suite 203 Orlando 32804 Tel: (305) 628·2393 TWX: ~110~~53.921.9 GEORGIA Inlel Corp. 3300 Holcomb Bridge Rd. Norcross 30092 Tel: (404) 4~9;0541 ILLINOIS Intel Corp. 2550 Gall Road, Suite 815 Rolling Meadows 60006 Tel: (312) 981·7200 TWX: 910-651·5661 Technical Representatives 1502 North Linde Street Bloomington 61701 Tel: (309) 629-8060 INDIANA Intel Corp. 9101 Wesleyen Road Suite 204 Indianapolis 46268 Tel: (317) 299·0823 IOWA Technical Representatives, Inc. St. Andrews Building 1930 St. Andrews Drive N.E. Cedar Rapids 52405 Tel: (319) 393·6510 KANSAS Intel Corp. 9393 W. 110th St., Ste. 285 Overland Park 66210 Tel: (913) 842·8080 Technical Representativee, Inc. 8245 Nieman Road, Suite 100 Lenexa 86214 Tel: (913) 888-0212, 3 & 4 TWX: 910·749·6412 Technical Representatives, Inc. 360 N, Rock Road Suite 4 Wichita 67206 Tel: (316) 681-0242 MARYLAND Intel Corp." 7257 Parkway Drive Hanover 21076 Tel: (301) 796-7500 TWX: 710'862-1944 Mesa Inc. 16201 Industrial Dr, Gaithersburg 20760 Tel: (301) 948·4350 MASSACHUSETTS Intel Corp." 27 Induslrial Ave. Chelmsford 01824 Tel: (617) 667-8126 TWX: 710·343·6333 EMC Corp, 381 Elliot Street Newton 02164 Tel: (617) 244·4740 TWX: 922631 MICHIGAN Intel Corp." 26500 Northwestern Hwy, Suite 401 Southfield 48075 Tel: (313) 353·0920 TWX: 810-244·4915 .' MINNESOTA Intel Corp. 7401 Metro Blvd. Suite 356 Edina 55435 Tel: (612) 835·6722 TWX: 910·576·2867 MISSOURI Intel Corp. 502 Earth City Plaza Suite 121 Earth City 60345 · Tel: (314) 2,91-.199.0 Technical Representatives, Inc.· 502 Earth City Plaza Suite 201 Earth City 63045 Tel: (314) 291·0001 Technical Representatives,' InC?" VSW Bldg. Suite 660 406 W. 31st Sireet Kansas City 64111 Tel: (816) 756·3576 TWX: 910·771·0026 NEW JERSEY Intel Corp,· Raritan Plaza 2nd Floor Raritan Center Edison 08817 Tel: (201) 225·3000 TWX: 710·480·6238 ,NEW MEXICO BFA Corporation 1704 Moon N.E., Suite 7 Las Cruces 87112 Tel: (505) 523·0S01 TWX: 910-983·0543 BFA Corporation · .3705 Westerfield, N,E. Albuquerque 87111 Tel: (505) 292·1212 'TWX: 910-989·1157 NEWVORK Intel Corp.' 300 Motor Pkwy. Hauppauge 11787 . Tel: (516) 231-3300 'J"WX: 610·227·6236 Intel Corp. 80 Washington St, Poughkeepsie 12601 Tel: (914) 473-2303 TWX: 610·248·0060 Inlel Corp.' 2255 Lyell Avenue Lower Floor East Suite . Rochester 14606 Tel: (716) 264-6120 TWX: 610·253·7391 Measurement Technology, Inc. · 159 Northern Boulevard Great Neck 11021 .Tel: (516) 462·3500 T·Squared 4054 Newcourt Avenue Syracuse 13206 Tel: (315) 463·8592 TWX: 710·541-0554 T·Squared 2E. Main Victor 14564 Tel: (718) 924·9101 TWX: 510-254·8542 NORTH CAROLINA Intel Corp. 154 Huffman Mill Rd, Burlington 27216 Tel: (919) 584-3631 OHIO Intel Corp." 6500 Poe Avenue Dayton 45415 Tel: (513) 890·5350 TWX: 810·450·2628 Intel Corp.' . Chagrin·Brainard Bldg., No. 300 '28001 Chagrin Blvd. Cleveland 44122 Tel: (218) 464-2736 TWX: 810·427·9298 OREGON Intel Corp, 10700 S.W. Beaverton Hillsdale Highway Suite 324 Beaverton 97006 'rei: (503) 641·8086' TWX: 910·467·8741 PENNSYLVANIA Intel Corp." 510 Pennsylvania Avenue Fort Washington 19034 Tel: (215) 641-1000 TWX: 510·661·2077 Intel Corp.' . 201 Penn Center Boulevard Suite 301W Pittsburgh 15235 ,.Tel: (412) 823·4970 O,E,D. Electronics 300 N. York Road Hatboro 19040 Tel: (215) 674·9600 TEXAS Intel Corp." 2926 L,B,J. FreewJlY Suite 175 Dallas 75234 Tel: (214) 241-9521 TWX: 910·860·5617 Intel Corp.' 8420 Richmond Ave. Suite 280 Houston 77057 Tel: (713) 784·3400 TWX: 910·881·2490 fndustrial Digital Systems Corp. 5925 Sovereign Suite 101 Houston 77038 .Tel: (713) 988·9421 Intel Corp. 313 E. Anderson Lene Suite 314 Austin 78752 Tel: (512) 464·3628 WASHINGTON Intel Corp. Suite 114, Bldg. 3 1803 116th Ave. N.E. Bellevue 98005 Tel: (206) 453·8086 TWX: 910·443·3002 WISCONSIN Il'!tel Corp. 150 S. Sunnyslope Rd. Brookfield 53005 Tel: (414) 784-9060 CANADA Intel Semiconductor Corp. " Suite 233, Bell Mews 39 Highway 7, Bells Comers Oltawa, Ontario K2H 8R2 Tel: (613) 829·9714 TELEX: 053·4116 Inlel Semiconductor Corp. 60 Galaxy Blvd. Unit 12 Rexdale, Ontario M9W 4Y5 Tel: (416) 676·2t06 TELEX: 06983574 Multilek, Inc.' 15 Grenlell Crescent Ottawa, Ontario K2G OG3 Tel: (613) 228-2365 . TELEX: 053·4585 Multilek,lnc.' Toronto Tel: (416) 246·4622 Multllek, Inc. Montreal . Tel: (514) 481·1350 "Field Application'Location U.S. AND CANADIAN DISTRIBUTORS 3065 Bowers Avenue Santa Clara, California 95051 Tel: (408) 987·8080 TWX: 910·338·0026 TELEX: 34·6372 ALABAMA tHamillon/Avnet Electronics 4812 Commercial Drive N.W. Huntsville 35805 . Tel: (205) 837·7210 tPioneer IHuntsville 1207 Putman Drive N.W. Huntsville 35605 Tel: (205) 837·9033 TWX: 810·726·2197 ARIZONA tHamillon/Avnet Electronics 2615 S. 21st Street Phoenix 85034 Tel: (602) 275·7851 tWyle Distribution Group 8155 N. 24th Avenue Phoenix 85021 Tel: (602) 995·9185 TWX: 910·951·4282 CALIFORNIA Arrow Electronics. Inc. 9511 Ridge Haven Court San Diego 92123 Tel: (714) 585·4800 Arrow Electronics, Inc. 720 Palomar Avenue Sunnyvale California 94088 Tel: (406) 739·3011 TWX: 910·339·9371 t Avnet Electonics 350 McCormick Avenue Costa Mesa 92626 Tel: (714) 754·6051 TWX: 910·595·1928 Hamilton/Avne! Electronics 1175 Bordeaux Dr. Sunnyvale 94086 Tal; (408) 743·3300 TWX: 910·339·9332 tHamiltonl Avnet Eleclonics 8917 Complex Drive San Diego 92123 Tel: (714) 571·7923 TWX: 910·335·1216 tHamilton I Avnel Electronics 10912 W. Washington Blvd. Culver City 90230 Tel: (213) 558·2193 TWX: 910·340·6364 or 7073 tHamilton Electro Sales 3170 Pullman Street Costa Mesa 92628 Tel: (714) 641·4100 TWX: 910·595·2638 tWyle Distribution Group 124 Maryland Street EI Segundo 90245 Tel: (213) 322·3826 TWX: 910·348·7140 or 7111 tWyJa Distribution Group 9525 Chesapeake Dr. San Diego 92123 Tel: (714) 565·9171 TWX: 910·335·1590 tWyle Distribution Group 3000 Bowers Avenue Santa Clara 95052 Tel: (406) 727·2500 TWX: 910·338·0451 or 0296 Wyle Distribution Group 17872 Cowan Avenue Irvine 92714 Tel: (714) 841·1611 COLORADO tWyle Distribution Group 6777 E. 50th Avenue Commerce City 60022 Tel: (303) 267·9611 TWX: 910·931·0510 COLORADO IConl.) tHamillon/Avnet Electronics 8765 E. Orchard Road Suite 706 Englewood 80111 Tel: (303) 534·1212 TWX: 910'931-0510 Wyle Dlatrlbution Group 451 E. 124th Avenue Thornlon 80241 Tel: (303) 457·WYLE TWX: 910-931-0510 CONNECTICUT tArrow Eleclonics 12 Beaumont Road Wallingford 06512 Tel: (203) 265·7741 TWX: 710-478-0182 tHamillonl Avnet Electronics CommerCe Induatrial Park Commerce Drive Danbury 08810 Tel: (203) 797-2800 TWX: 710·456-9974 tHarvey Electronics 112 Main Street Norwalk 08851 Tel: (203) 853·1515 TWX: 710·488-3373 TWX: 710-393-6770 FLORIDA tArrow Electronics 1001 N.W. 82nd Street Suile 108 Ft. Lauderdale 33309 Tel: (305) 776·7790 TWX: 510-955·9458 tArrow Electronics 115 Palm Bay Road, N.W. Suite 10, Bldg. 200 Palm Bay 32905 Tel: (305) 725·1480 TWX: 510·959-6337 tHamillon/Avnet Electronics 6800 Northweat 20th Ave. Ft. Lauderdale 33309 Tel: (305) 971-2900 TWX: 510·955·3097 Hamilton I Avnel Electronics 3197 Tech. Drive North St. Peteraburg 33702 Tel: (813) 576·3930 TWX: 810·883·0374 tPloneer I Orlando 6220 S. Orange Blossom Trail Suite 412 Orlando 32809 Tel: (305) 659·3600 TWX: 810·850·0177 GEORGIA Arrow Electronics 2979 Pacific Drive Norcrosa 30071 Tel: (404) 449·8252 TWX: 610-757·4213 tHamiltonl Avnet Electronica 6700 1-85 Access Road. No. 11 Suite IE Norcross 30071 Tel: (404) 448·0800 ILLINOIS Arrow Electronics 492 Lunt Avenue P.O. Box 94248 Schaumburg 60172 Tel: (312) 893·9420 TWX: 910·222·1807 tHamillon I Avnet Electronica 3901 No. 25th Avenue Schiller Park 60176 Tel: (312) 678·8310 TWX: 910·227·0060 Pioneer/Chicago 1551 Carmen Drive Elk Grove 60007 Tel: (312) 437·9680 TWX: 910'222-1834 INDIANA tHamilton I Avnet Electronics 485 Gradle Drive Carmel 46032 Tel: (317) 844-9333 Pioneer Iindiana 6408 Caslleplace Drive Indianapolis 46250 Tel: (317) 849·7300 TWX: 810'260-1794 KANSAS tHamiltonl Avnet Electronics 9219 Ouivira Road Overland Park 66215 Tel: (913) 888-8900 tComponent Specialties, Inc. 8369 Nieman Road Lenexa 66214 Tel: (913) 492·3555 MARYLAND Arrow ElectroniCS, Inc. .4801 Benson Avenue Baltimore 21227 Tel: (301) 247-5200 tHamiiton/Avnet Eleclronlca 7235 Standard Drive Hanover 21076 Tel: (301) 796·5684 TWX: 710'862-1861 tPioneer/Washington 9100 Gaither Road Gaithersburg 20760 Tel: (301) 948·0710 TWX: 710·828·0545 MASSACHUSETTS tHamiltonl Avnet Electronics 50 Tower Office Park Woburn 01801 Tel: (817) 273·7500 TWX: 710·393-0382 t Arrow Electronics 96D Commerce Way Woburn 01801 Tel: (617) 933·8130 Harvey I Boaton 4 Hartwell Ave. Lexington 02173 Tel: (617) 881·9200 TWX: 710·326-6617 MICHIGAN t Arrow Electronica 3810 Varsity Drive Ann Arbor 48104 Tel: (313) 971·8220 TWX: 810·223·6020 tPloneer I Michigan 13485 Stamford Livonia 48150 Tel: (313) 525·1800 TWX: 810·242-3271 tHamiltonl Avnet Electronics 32487 Schoolcraft Road Livonia 48150 Tel: (313) 522-4700 TWX: 810'242-8775 MINNESOTA t Arrow Electronlca 5230 W. 73rd Street Edina 55435 Tel: (612) 830·1800 TWX: 910'758-2728 tlndustrial Componenla 5229 Edina Industrial Blvd. Minneapolia 55435 Tel: (612) 831·2668 TWX: 910'756-3153 tHamiltonl Avnet Electronics 7449 Cahill Road Edina 55435 Tel: (612) 941·3801 TWX: 910'576-2720 MISSOURI tHamiltonl Avnet Electronics 13743 Shorline Ct. Earth City 63045 Tel: (314) 344·1200 TWX: 910·762·0606 NEW HAMPSHIRE tArrow Electronics 1 Perimeter Drive Manchester 03103 Tel: (603) 666·6968 TWX: 710·220·1684 NEW JERSEY tArrow Electronics Pleasant Valley Avenue Moorestown 08057 Tel: (215) 928·1800 TWX: 710·897·0829 tArrow Electronics 285 Midland Avenue Saddle Brook 07662 Tel: (201) 797·5800 TWX: 710·998·2206 tHamllton / Avnet Electronics 1 Keystone Ave. Bldg. 36 Cherry Hili 08003 Tel: (609) 424·0100 TWX: 710·897·1405 Hamilton I Avnet Electronica 10 Industrial Road Fairfield 07006 Tel: (201) 575·3390 ,TWX: 710·734·4438 tHarvey Electronics 45 Route 46 Pine brook 07058 Tel: (201) 227·1262 TWX: 710·734·4382 NEW MEXICO tAlliance Electronics Inc. 11030 Cochiti S.E. Albuquerque 87123 Tel: (505) 292·3360 TWX: 910·989·1151 tHamillonl Avnet Electronics 2524 Baylor Drive S.E. Albuquerque 87119 Tel: (505) 765·1500 NEW YORK t Arrow Electronics 3000 South Winton Road Rochester 14623 Tel: (716) 275·0300 TWX: 510·253·4766 tArrow Electronics 7705 Malttage Drive Liverpool 13088 Tel: (315) 652·1000 TWX: 710·545·0230 Arrow Electronics 20 Osor Avenue Hauppauge 11787 Tel: (516) 231·1000 TWX: 510·227·6623 tHamiltonl Avnet Electronics 333 Metro Park Rochester 14623 Tel: (716) 475~9130 TWX: 510·253·5470 tHamiltonl Avnet Electronics 16 Corporate Circle E. Syracuse 13057 Tel: (315) 437·2641 tHamiiton/ Avnet Electronics 5 Hub Drive Melville. Long Island 11746 Tel: (516) 454·6000 TWX: 510·252·0893 tMicrocomputer System Technical Demonstrator Centers inter u.s. AND CANADIAN DISTRIBUTORS 3065 Bowers Avenue Sanla Clara, California 95051 Tel: (408) 987·8080 TWX: 910-338-0026 TELEX: 34·6372 NEW YORK (Cant.) Harvey Electronics P.O. Box 1208 Binghampton 13902 Tel: (607) 748·8211 TWX: 510·252·0893 tHarvey Electronics 60 Crossways Park West Woodbury 11797 Tel: (516) 921·8700 TWX: 510·221·2184 Harvey/Rochester 840 Fairport Park Fairport 14450 Tel: (7IS) 381·7070 TWX: 510·253· 700 1 NORTH CAROLINA Arrow Electronics 938 Burke Sireet Winston-Salem 27102 Tel: (919) 725·8711 TWX: 510-922·4765 tHamilton I Avne! Electronics 2603 Industrial Drive Raleigh 27609 Tel: (919) 829·8030 Pioneer I Carolina 106 Industrial Ave. Greensboro 27406 Tel: (919) 273·4441 TWX: 510·925·1114 OHIO Arrow Electronics 7620 McEwen Road Centerville 45459 Tel: (513) 435·5563 TWX: 810·459·1611 Arrow Electronics 6238 Cochran Rd. Solon 44139 Tel: (216) 248·3990 TWX: 810·427·9409 Arrow Electronics 10 Knollcrest Or. Cincinnati 45237 Tel: (513) 761·5432 TWX: 810·461·2670 tHamiltonl Avnet Electronics 954 Senate Drive Dayton 45459 Tel: (513) 433·0610 TWX: 910·340·2531 tHamiltonl Avnet Electronics 4588 Emery Industrial Parkway Warrensville Heights 44128 Tel: (216) 831·3500 TWX: 810'427·9452 tPioneer I Dayton 1900 Troy Street Dayton 45404 Tel: (513) 236·9900 TWX: 810·459·1622 tPioneer I Cleveland 4800 E. 131 st Street Cleveland 44105 Tel: (216) 587·3600 TWX: 810·422·2210 OKLAHOMA tComponents Specialties, Inc. 7920 E. 40th Street Tulsa 74145 Tel: (SI8) 664·2820 TWX: 910·845·2215 OREGON tAlamc/Slroum Electronics 8022 S.W. Nimbus, Bldg. 7 Beaverton 97005 Tel: (503) 641·9070 tHamilton I Avnet Electronics 6024 S.W. Jean Rd. Bldg. C, Suite 10 Lake Oswego 97034 Tel: (503) 635·7848 PENNSVLVANIA tArrow Electronics 4297 Greensburg Pike Suite 3114 Pittsburgh 15221 Tel: (412) 351·4000 Pioneer/Pittsburgh 259 Kappa Drive Pittsburgh 15238 Tel: (412) 782·2300 TWX: 710·795·3122 Pioneer/Delaware Valley 261 Gibralter Road Horsham 19044 Tel: (215) 674·4000 TWX: 510·665·6778 TEXAS Arrow Electronics 13715 Gamma Road Dallas 75234 Tel: (214) 386·7500 TWX: 910·661·5495 Arrow Electronics, Inc. 10700 Corporate Drive, Suite 100 Stafford 77477 Tel: (713) 491·4100 Component Specialties, Inc. 8222 Jamestown Drive Suite 115 Austin 76758 Tel: (512) 837·8922 TWX: 910·874·1320 tComponent Specialties, Inc. 10607 Shady Trail, Suite 101 Dallas 75220 Tel: (214) 357·6511 TWX: 910·861·4999 tComponent Specialties, Inc. 8585 Commerce Park Drive, Suite 590 Houston 77036 Tel: (713) 771·7237 TWX: 910-881·2422 Hamilton I Avnet Electronics 10508A Boyer Blvd. Austin 78757 Tel: (512) 837·8911 tHamiiton I Avnet Electronics 2111 W. Walnut Hill Lane Iving 75062 Tel: (214) 661·4111 TWX: 910·860·5371 tHamilton I Avnet Electronics 3939 Ann Arbor Drive Houston 77063 Tel: (713) 780·1771 UTAH tHamilton / Avnet Electronics 1585 West 2100 South Salt Lake City 84119 Tel: (801) 972·2800 WASHINGTON tAlmac/Stroum Electronics 5811 Sixth Ave. South Seattle 98108 Tel: (206) 763·2300 TWX: 910·444,2067 Arrow Electronics, Inc. Electronics Distribution Division 1059 Andover Park East .. Tukwila 98188 Tel: (206) 575·0907 tHamiltonl Avnet Electronics 14212 N.E. 21 st Street Bellevue 98005 Tel: (206) 453·5844 WASHINGTON (Coni.) tWyle Distribution Group 1750 132nd Avenue N.E. Bellevue 98005 Tel: (206) 453·6300 TWX: 910·443·2526 WISCONSIN t Arrow Electronics 430 W. Rawson Avenue Oak Creek 53154 Tel: (414) 764·6600 TWX: 910,338·0026 QUEBEC tHamliton I Avnet Electronics . 2670 Sabourin Street SI. Laurent H4S 1M2 Tel: (514) 331-6443 TWX: 610·421·3731 Zentronica 5010 Pare Street Montreal H4P lP3 Tel: (514) 735-5361 TWX: 05-827-535 tHamiltonl Avnet Electronics 2975 Moorland Road New Berlin 53151 Tel: (414) 784·4510 TWX: 910·262·1182 CANADA ALBERTA tL.A. Varah Ltd. 4742 14th Street N.E. Calgary T2D 6L7 Tel: (403) 230·1235 TWX: 018-258·97 Zentronics 9224 27th Avenue Edmonton T6N 182 Tel: (403) 463·3014 .Zentronics , 3651 21st N.E. Calgary T2E 6T6 Tel: (403) 230·1422 BRITISH COLUMBIA tL.A. Varah Ltd. • ,2077 Alberta Street Vancouver V5V lC4 Tel: (604) 873-3211 TWX: 610·929-1068 Zenlronics 550 Cambie St. Vancouver V6B 2N7 Tel: (604) 688·2533 TWX: 04-5077-89 MANITOBA L.A. Varah 1-1832 King Edward Street Winnipeg R2R ON 1 Tel: (204) 633-6190 TWX: 07-55·365 Zentronics 590 Serry St. Winnipeg R3H OS 1 Tel: (204) 775·8661 ONTARIO tHamilton I Avnet Electronics 3688 Rexwood Road, Units G & H . Mississauga L4V 1M5 Tel: (416) 677-4732 TWX: 610·492,8860 tHamiiton I Avnet Electronics 1735 Courlwood Cresent Ottawa K2C 3J2 Tel: (613) 226·1700 TWX: 053-4971 tL.A. Varah, Ltd .. 605 Kenora Avenue Hamilton L8E 3P2 Tel: (416) 561-9311 TWX: 061·8349 tZentronics 141 Catherine Slreet Ottawa K2P 1C3 Tel: (613) 238·6411 TWX: 053-3636 tZentronics 1355 Meyerside Drive Mississauga, Ontario L5T 1C9 . Tel: (416) 676-9000 Telex: 06-983-667 t~icrocomputer System Technical Demonstrator Centera INTERNATIONAL SALES AND MARKETING OFFICES 3065 Bowers Avenue Santa Clara, California 95051 Tel: (408) 987·8080 TWX: 910·338·0026 TELEX, 34·6372 INTERNATIONAL DISTRIBUTORS/REPRESENTATIVES ARGENTINA Micro Sistemas S. A. 9 De Julio 561 Cordoba Tel: 54·51·32·880 TELEX: 51837 BICeO AUSTRALIA A.J.F. Systems & Components Ply. Ltd. 310 Queen Street Melbourne Victoria 3000 Tel: 679-702 TELEX: AA 31261 Warburton Franki Corporale Headquarters 372 Eastern Valley Way Chalswood, New South Wales 2067 Tel: 407·3261 TELEX: AA 21299 AUSTRIA Bacher Eleklronische Geraela GmbH Rotenmulgasse 28 A 1120 Vienna Tal: (0222) 83 63 96 TELEX: (O1) 1532 Aekirsch Eleklronik Goraela GmbH Lichtensteinslrasse 97 A 1000 Vienna Tel: (222) 347648 TELEX: 74759 FINLAND Oy Finlronic AB Melkonkatu 24 A SF-00210 Helsinki 21 Tel: 0·692 6022 TELEX: 124224 Flron SF FRANCE Celdis S.A.' 53, Rue Charlas Frerot F-94250 Gentilly Tel: (1) 581 0020 TELEX: 200 485 Feulrier Rue des Trois Glorieuses F·42270 SI. Priest·en-Jarez Tel: (77) 74 67 33 TELEX: 300021 Metrologie' la Tour d' Asnieres 4, Avenue Leurent Cely 92606-Asnieres Tel: 791 4444 TELEX: 611 448 Tekelec Airtronic' Cite des Bruyeres Rue Carle Vernet F·92310 Sevres Tel: (1) 534 75 35 TELEX: 204552 Av. Vic. Mc kenna 204 Casille 6055 Sentiago Tel: 227 564 TELEX: 3520003 GERMANY Electronic 2000 Vertriebs GmbH Neumarkler Strasse 75 0·6000 Munich 80 Tel: (089) 434061 TELEX: 522561 Jermyn GmbH Posifach 1180 0·6077 Camberg Tel: (06434) 231 TELEX: 484426 Kontron Elektronik GmbH Breslauerstrasse 2 8057 Eching B 0-8000 Munich Tel: (89) 319011 TELEX: 522122 Neye Enatechnik GmbH Schillerstrasse 14 0-2085 Quickborn·Hamburg Tel: (04106) 6121 TELEX: 02·13590 CHINA C.M. Technologies 525 University Avenue Suite A·40 Pato Allo, CA 94301 Tel: (415) 326·9150 GREECE American Technical Enterprises P.O. Box 156 Athans Tel: 30·1·8811271 30-1·8219470 COLOMBIA International Computer Machines Carrera 7 No. 72·34 Apdo. Aereo 19403 Bogota 1 Tel: 211-7282 TELEX: 413141NCO HONG KONG Schmidt & Co. 28/F Wing on Centar Connaught Road Hong Kong Tel: 5·455·644 TELEX: 74766 Schmc Hx CYPRUS Cyprus Eltrom Electronics P.O. Box 5393 Nicosia Tel: 21·27982 INDIA Micronic Devices 104/109C, Nirmallndustrial Eetate Sion (E) Bombay 400022, India Tel: 486-170 TELEX: 011·5947 MDEV IN BELGIUM Inoleo Belgium SA Ave. des Croix de Guerre 94 B 1120 Brussels Tel: (02) 216 01 60 TELEX: 25441 BRAZIL Icotron S.A. 0511 Av. Mutinga 3650 6 Andar Pirituba Sao Paulo Tel: 261-0211 TELEX: (011) 222 ICO BR CHILE DIN DENMARK STL-Lyngso Komponenl AlS Oslmarken 4 OK·2860 Soborg Tel: (01) 67 00 77 TELEX: 22990 Scandinavian Semiconductor Supply AIS Nannasgade 18 OK-2200 Copenhagen Tel: (01) 83 50 90 TELEX: 19037 ISRAEL Easlronics Ltd.' 11 Rozanis Street P.O. Box 39300 Tel Aviv 61390 Tel: 475151 TELEX: 33636 ITALY Eledra 3S S.P.A.' Viale Elvezia, 18 120154 Milan Tel: (02) 34.93.041-31.85.441 TELEX: 332332 JAPAN Asahi Electronics Co. ltd. KMM Bldg. Room 407 2·14·1 Asano, Kokura Klla-Ku, Kltokyushu City 802 Tel: (093) 511·6471 TELEX: AECKY 7126-16 Hamilton-Avnet Electronics Japan Ltd. YU and YOU Bldg. 1-4 Horidome·Cho Nihonbashi Tel: (03) 662·9911 TELEX: 2523774 Ryoyo Electric Corp. Konwa Bldg. 1-12·22, Tsukiji, I-Chrome Chuo-Ku, Tokyo 104 Tel: (03) 543-7711 Tokyo Electron Ltd. No.1 Higashikata-Machi Midori·Ku, Yokohama 226 Tel; (045)471-8811 TELEX: 781-4473 KOREA Koram Digital Room 909 Woonam Bldg. 7, I·KA Bongre-oong Chung-Ku Seoul Tel: 238-123 TELEX: K23542 HANSINT Leewood International, Inc. C.P.O. Box 4046 112·25 Sokong-Dong Chung-Ku, Seoul 100 Tel: 285·927 TELEX: MOCNDM K23231 CABLE: "LEEWOOD" Seoul MEXICO Proveedora Electronica, S.A. (Proesa) Prot. Moclezuma Ote. 24 Col. Romero de Terreros Apdo. Postal 21-139 Mexico 21, D.F. Tel: 554·8300 TELEX: 017·72402 SAULME NETHERLANDS Inelco Nether. Compo Sys. BV Turfstekerstraat 63 Aalsmeer 1431 0 Tel: (2977) 26655 TELEX: 14693 Koning & Hartman Koperwerl 30 2544 EN Den Haag Tel: (70) 210.101 TELEX: 31528 NEW ZEALAND W. K. McLean Ltd. P.O. Box 18-065 Glenn innes, Auckland, 6 Tel: 587·037 TELEX: NZ2763 KOSFY NORWAY Nordisk Elektronic (Norge) AIS Postoffice Box 122 Smedsvingen 4 1364 Hvalstad Tel: 02 78 62 10 TELEX; 17546 PORTUGAL Ditram Componentes E Electronica LOA Av. Miguel Bombarda, 133 Lisboa 1 Tel; (19) 545313 TELEX: 14347 GESPIC SINGAPORE General Engineers Associates Blk 3, 1003-1008, 10th Floor P.S.A. Multi·Storey Complex Telok Btangah/Pasir Panjang Singapore 5 Tel: 271-3163 TELEX: RS23987 GENERCO SOUTH AFRICA Electronic Building Elements Pine Square 18th Street Hazelwood, Pratoria 000 t Tel: 011-27·12·46-9221 TELEX: 30181SA SPAIN Interface S.A. Ronda Ssn Pedro 22. 3' Barcelona 10 Tel: 301 78 51 TWX: 51508 ITT SESA Miguel Angel 16 Madrid 10 Tel: (1) 4190957 TELEX: 27707/27461 SWEDEN AB Gosta Backstrom Box 12009 10221 Stockholm Tel: (08) 541 080 TELEX: 10135 Nordisk Electronik AB Box 27301 8-10254 Stockholm Tel: (08) 635040 TELEX: 10547 SWITZERLAND Industrade AG Gemsenstrassa 2 Postcheck 80 - 21190 CH·8021 Zurich Tel: (01) 60 22 30 TELEX: 56788 TAIWAN Taiwan Automation Co.' 3d Floor #75, Section 4 Nanking East Road Taipei Tel: 771·0940 TELEX: 11942 TAIAUTO TURKEY Turkelek Electronics Apapurk Boulevard 169 Ankara Tel: 189483 UNITED KINGDOM Comway Microsystems Ltd. Market Street 68-Bracknell, Berkshire Tel: (344) 51654 TELEX: 847201 G.E.C. Semiconductors Ltd. East Lane North Wembley Middlesex HA9 7PP Tel: (01) 904-9303/908-4111 TELEX: 28817 Jermyn Industries Vestry Estate Seven oaks, Kent Tel: (0732) 501.44 TELEX: 95142 Rapid Recall, ltd. 6 Soho Mills Ind. Park Wooburn Green Bucks, England Tel: (6285) 24961 TELEX: 849439 Sintrom Electronics ltd.' Arkwright Road 2 Reading, Berkshire RG2 OlS Tel: (0734) 85464 TELEX: 847395 VENEZUELA Componentes y Circuitos Electronicos TTLCA C.A. Apartado 3223 Caracas 101 Tel: 718-100 TELEX: 21795 TELETIPCS "Field Application location INTERNATIONAL SALES AND MARKETING OFFICES 3065 Bowers Avenue Santa Clara, California 95051 Tel: (408) 987-8080 TWX: 910-338-0026 TELEX: 34·6372 INTEL® MARKETING OFFICES AUSTRALIA Inlel Semiconductor Ply. Ltd. Suite 2, Level 15, North Point 100 Miller Street North Sydney, NSW, 2060 Tel: 450-847 TELEX: AA 20097 BELGIUM Intel Corporation S.A. Rue du Moulin a Papier 51 Boite 1 B·1160 Brussels Tel: (02) 660 30 10 TELEX: 24814 DENMARK Inlel Denmark A/S' lyngbyvei 32 2nd Floor OK-2IDO Copenhagen East Tel: (01) 182000 TELEX: 19567 FINLAND Intel Finland OY Sentnerikuja 3 SF • 00400 Helsinki 40 Tel: (0) 558531 TELEX: 123332 FRANCE Inlel Corporation, S.A.R.L.· 5 Place de Ie Balance Silic 223 94528 Rungia Cedax Tel: (01) 687 22 21 TELEX: 270475 GERMANY Intel Semiconductor GmbH· Seidlstrasse 27 8000 Muenchen 2 Tel: (089) 53 891 TELEX: 523 177 Intel Semiconductor GmbH Mainzer Strasse 75 6200 Wiesbaden 1 Tel: (06121) 700874 TELEX: 04186183 Intel Semiconductor GmbH Wernerstresse 67 P.O. Box 1460 7012 Fellbach Tel: (0711) 580082 TELEX: 7254826 Intel Semiconductor GmbH Hohenzollern Strasse 5 '3000 Hannover 1 Tel: (0511) 327081 TELEX: 923825 Intel Semiconductor GmbH Oberrathstrasse 2 4000 Duesseldorf 30 Tel: (0211) 651054·6 TELEX: 8S86977 HONG KONG Intel Semiconductor Ltd, 99·105 Des Voeux Rd" Central ISF, Unit B Hong Kong Tel: 5·450·847 TELEX: 63869 ITALY Intel Corporation Italia, S.p.A. Corso Sempione 39 1·20145 Milano Tel: 2/34.93287 TELEX: 311271 JAPAN Intel Japan K.K .• Flower HiII·Shinmachi East Bldg. 1·23·9 Shinmachl, Setagaya·ku Tokyo 154 Tel: (03) 426·9261 TELEX: 781·28426 NETHERLANDS Intel Semiconductor B. V. Cometongebouw Westblaak 106 3012 Km Rotterdam Tel: (10) 149122 TELEX: 22283 NORWAY Intel Norway AI S P.O. Box 92 Hvamveien 4 N·2013 Skjetten Tel: (2) 742 420 TELEX: 18018 SWEDEN Intel Sweden A,B.· Box 20092 Alpvagen 17 S·16120 Bromma Tel: (08) 98 53 90 TELEX: 12261 SWITZERLAND Inlel Semiconductor A,G. Forchstrasae 95 CH 8032 Zurich Tel: 1·554502 TELEX: 557 89 ich ch UNITED KINGDOM Inlel Corporation (U.K,) Lid.' 5 Hospital Street Nantwich, Cheshire CWS SRE Tel: (0270) 62 65 60 TELEX: 36820 Intel Corporation (U.K.) Ltd. Dorcan House Eldine Drive Swindon. Wiltshire SN3 3TU Tel: (0793) 26101 TELEX: 444447 INT SWN ISRAEL Intel Semiconductor Ltd,· P.O, Box 2404 Haifa Tel: 972/452 4261 TELEX: 92246511 'Fleld Application Location
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Producer : Adobe Acrobat 9.2 Paper Capture Plug-in Modify Date : 2009:12:17 21:51:08-08:00 Create Date : 2009:12:17 21:51:08-08:00 Metadata Date : 2009:12:17 21:51:08-08:00 Format : application/pdf Document ID : uuid:870f610d-9767-4716-8d43-31ae044789eb Instance ID : uuid:f2c0b9b6-4f6b-41db-b1e4-e96e9c4fd20f Page Layout : SinglePage Page Mode : UseNone Page Count : 578EXIF Metadata provided by EXIF.tools