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The Engineering Staff of

TEXAS INSTRUMENTS INCORPORATED
Semiconductor Group

The
TTL

Data Book
for

Design Engineers

Second Edition

TEXAS INSTRUMENTS
I NCOR POR ATEO

INDEXES
Alphanumeric. Functional/Selection Guide

INTERCHANGEABILITY GUIDE

GENERAL INFORMATION

ORDERING INSTRUCTIONS AND MECHANICAL DATA

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS

54/74 FAMILY SSI CIRCUITS

54/74 FAMILY MSI/LSI CIRCUITS

JAN MIL-M-38510 INTEGRATED CIRCUITS

38510/MACH IV PROCUREMENT SPECIFICATION

IC SOCKETS AND INTERCONNECTION PANELS

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E

TEXAS INSTRUMENTS
Printed in U.S.A

G

INCORPORATED

The

TTL

Data Book
for

Design Engineers .

Second Edition

TEXAS INSTRUMENTS
INCORPORATED

LCC4112
74062-116 -AI

Printed in U.S.A.

IMPORTANT NOTICES
Texas Instruments reserves the right to make changes
at any time in order to improve design and to supply
the best product possible.
TI cannot assume any responsibility for any circuits
shown or represent that they are free from patent
infringement.
Information contained herein supercedes previously
published data on TTL products including data books
CC-411 and CC-416.

Copyright © 1981
Texas Instruments Incorporated

Third Printing

THE TTL DATA BOOK

Second Edition
In this 832-page data book, Texas Instruments is pleased to present important technical
information on the industry's broadest and most advanced families of TTL integrated
circuits.
You'll find complete specifications on standard-technology TTL circuits (Series 54/74,
Series 54H/74H, Series 54L/74L) and on Tl's high-technology TTL circuits such as the
Schottky-clamped t Series 54LS/74LS and Series 54S/74S. Information on radiationhardened and beam-lead circuits has not been included in this book, but TI has a broad
line of these devices, and information is available upon request.
The indexes are designed for ease of circuit selection with margin tabs to guide you
quickly to general circuit catagories, and the alphanumeric and functional indexes will let
you locate specific circuit types quickly. In addition, a section showing pin assignments,
package availability, and a brief description of the circuit type arranged in type-number
order is included for quick reference. Whenever practical, the MSI functions are arranged
in sequence by type number to further simplify the task of locating a particular function.
High-reliability TTL IC's are covered in a section devoted to the latest revision of the
MACH IV Procurement Specification in accordance with MIL-M-38510, a program
initiated by TI to ensure that quality and reliability are built into, not tested into, integrated circuits. Another section is devoted to JAN IC's and provides a table of recommended usage and cross-references from TI type number to 38510 slash sheet and 38510
slash sheet to T I type number.
Another handy reference for the design engineer is the section on IC sockets and interconnection panels from TI.
Although this volume offers design and specification data only for TTL integrated circuits,
complete technical data for any TI semiconductor/component products are available
from your nearest TI field sales office, local authorized TI distributor, or by writing
direct to: Marketing Information Services, Texas Instruments Incorporated, P. O. Box
225012, MS 308, Dallas, Texas 75265.
We sincerely hope you will find the new TTL Data Book for Design Engineers a meaningful addition to your technical library.

tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments. U.S. Patent Number 3,463,975.

II

Indexes
Alphanutneric
· Functional/Selection Guide

o

1·1

ALPHANUMERIC INDEX

TYPE NUMBERS

•

ELECTRICAL
PAGEt

PIN
TYPE NUMBERS

ASSIGNMENTS

ELECTRICAL

PIN
ASSIGNMENTS
PAGEt

PAGEt

FP54ALS16R4

FP74ALS16R4

S-297

S-297

SN54ALS09

SN74ALS09

S-235

FP54ALS16R6

FP74ALS16R6

S-297

S-297

SN54LS09

5-235

SN74LS09

6-12

FP54ALS16L8

FP74ALS16L8

S-297

S-297

5-8

SN54S09

SN74S09

6-12

FP54ALS16R8

FP74ALS16R8

S-297

5-8

S-297

SN5410

SN7410

FP54LS333

FP74LS333

S-306

S-306

SN54ALS10

SN74ALS10

FP54LS335
FP54AS839

FP74LS335
FP74AS839

S-306

S-306

SN54Hl0

S-310

S-310

SN54L10

FP54AS840

FP74AS840

SN5400

SN7400

S-310
6-2

S-310
5.{j

SN54ALSOO

SN74ALSOO

S-228

S-228

6-2

5-8

S-236

5-236

SN74Hl0

6-2

5-8

SN74L10'

6-2

5-8

SN54LS10

SN74LS10

6-2

5-8

SN54S10

SN74S10

6-2

5-8

SN54ALSll

SN74ALSll

S-237

5-237

SN54HOO

SN74HOO

6-2

5.{j

SN54Hll

SN74Hl1

6-10

5-9

SN54LOO

SN74LOO*

6-2

5.{j

SN54LSll

SN74LS11

6-10

5-9

SN54LSOO

SN74LSOO

6-2

5.{j

SN54S11

SN74S11

6-10

5-9

SN54S00

SN74S00

6-2

5.{j

SN5412

SN7412

64

5-9

SN5401

SN7401

64

5.{j

SN54ALS12

SN74ALS12

S-238

5-238

SN54ALSOl

SN74ALSOl

S-229

S-229

SN54LS12

SN74LS12

64

5-9

SN54HOl

SN74HOl

5.{j

SN5413

SN7413

6-14

5-9

5.{j

SN54LS13

SN74LS13

6-14

5-9

5.{j

SN5414

SN7414

6-14

5-9

SN54LS14

SN74LS14

6-14

5-9

SN54ALS15

SN74ALS15

S-239

5-239

SN54LSOl

SN74LSOl

64
64
64

SN5402

SN7402

6-8

5.{j

SN54ALS02

SN74ALS02

S-230

S-230

SN54L02

SN74L02*

6-8

5.{j

SN54H15

SN74H15

6-12

5-10

SN54LS02

SN74LS02

6-8

5.{j

SN54LS15

SN74LS15

6-12

5-10

SN54S02

SN74S02

6-8

5.{j

SN54S15

5N74S15

6-12

5-10

SN5403

SN7403

64

5-7

SN5416

SN7416

6-24

5-10

SN54ALS03

SN74ALS03

S-231

S-231

SN5417

SN7417

6-24

5-10

SN54L03

SN74L03'

5-7

SN54LS18

SN74LS18

5-17

5-17

5-7

SN54LS19

SN74LS19

5-17

S-17

5-7

SN5420

SN7420

SN54ALS20

SN74ALS20

SN54LOl

SN54LS03

SN74LS03

SN54S03

SN74S03

64
64
64

SN5404

SN7404

6-2

5-7

SN54ALS04

SN74ALS04

S-232

S-232

SN54H20

SN54H04

SN74H04

6-2

5-7

SN54L20

SN54L04

SN74L04'

6-2

5-7

SN54LS04

SN74LS04

6-2

SN54S04

SN74S04

6-2

SN5405

SN7405

SN54ALS05

SN74ALS05

SN54H05

SN74H05

SN54LS05

SN74LS05

SN54S05

SN74S05

SN5406

6-2

5-10

5-240

S-240

SN74H20

6-2

5-10

SN74L20*

6-2

5-10

SN54LS20

SN74LS20

6-2

5-10

5-7

SN54S20

SN74S20

6-2

5-10

5-7

SN54ALS21

SN74ALS21

S-241

5-241

SN54H21

SN74H21

6-10

5-11

SN54LS21

SN74LS21

6-10

5-11

64

5-7

S-233

S-233

64
64
64

5-7

SN5422

SN7422

5-7

SN54ALS22

SN74ALS22

5-7

SN54H22

SN74H22

SN7406

6-24

5-7

SN54LS22

5N74L522

SN5407

SN7407

6-24

5-8

SN54S22

SN74S22

SN5408

SN7408

6-10

5-8

SN5423

SN54ALS08

SN74ALS08

S-234

S-234

SN54LS08

SN74LS08

6-10

5-8

SN54S08

SN74S08

6-10

SN5409

SN7409

6-12

64

5-11

5-242

S-242

64
64
64

5-11

5N7423

6-39

5-11

SN54LS24

5N74LS24

5-17

5-17

SN5425

5N7425

6-8

5-11

5-8

SN5426

5N7426

6-24

5-12

5-8

SN54LS26

SN74L526

6-26

5-12

5-11
5-11

r Page numbers without "5·" preceding them refer to pages in this data book; those with "5·" refer to pages in 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772.

*Contact the factory for availabilitY.
1·2

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

ALPHANUMERIC INDEX

TYPE NUMBERS
SN5427

SN7427

SN54ALS27

SN74ALS27

SN54LS27

SN74LS27

SN5428
SN54ALS28

SN7428
SN74ALS28

SN54LS28

SN74LS28

SN5430

SN7430

SN54ALS30

SN74ALS30

ELECTRltCAL
PAGE

PIN
ASSIGNMENTS

TYPE NUMBERS

ELECTRICAL

PIN
ASSIGNMENTS
PAGEt

6·8

5·12

S-243

S·243

6·8

5·12

6·20
S·244

5·12
S-244

6·20
6·2
S-245

S·245

SN54LS49

SN74LS49

7·22

7·22

SN5450

SN7450

6·39

5·16

SN54H50

SN74H50

6·39

5·16

SN5451

SN7451

6·30

5·16

SN54H51

SN74H51

6·30

5·16

5·12

SN54L51

SN74L51*

6·30

5-16

5·12

SN54LS51

SN74LS51

6·30

5·16

SN54S51

SN74S51

6·30

5-16

SN54H30

SN74H30

6·2

5·12

SN54H52

SN74H52

6-39

5-17

SN54L30

SN74L30*

6·2

5-12

SN5453

SN7453

6-39

5-17

SN54LS30

SN74LS30

6·2

5·12

SN54H53

SN74H53

6-39

5-17

SN54S30

SN74S30

6·2

5·12

SN5454

SN7454

6-30

5-18

SN5432

SN7432

SN54ALS32

SN74ALS32

SN54LS32
SN54S32

6·28

5·13

SN54H54

SN74H54

6-30

5-18

S·246

S·246

SN54L54

SN74L54*

6-30

5-18

SN74LS32

6·28

5·13

SN54LS54

SN74LS54

6-30

5·18

SN74S32

6·28

5·13

SN54H55

SN74H55

6-39

5-19

SN5433.

SN7433

6·24

5·13

SN54L55

SN74L55*

6·30

5-19

SN54ALS33

SN74ALS33

S·247

S·247

SN54LS55

SN74LS55

6-30

5·19

SN54LS33

SN74LS33

6·26

5·13

SN5460

SN7460

6-43

5·19

SN5437

SN7437

6·20

5-13

SN54H60

SN74H60

6-44

5·19

SN54ALS37

SN74ALS37

S·248

S·248

SN54H61

SN74H61

6-45

5·19

SN54LS37

SN74LS37

6·20

5-13

SN54H62

SN74H62

6-44

5·20

SN54S37

SN74S37

6·20

5·13

SN54LS63

SN74LS63

6·62

5·20

6·24
S-249

5·13

SN54S64

SN74S64

6-30

5·20

S·249

SN54S65

SN74S65

6·32

5·20

6·26

5·13

SN5470

SN7470

6-46

5·21

SN5438

SN7438

SN54ALS38

SN74ALS38

SN54LS38

SN74LS38

SN54S38

SN74S38

6·26

5·13

SN54H71

SN74H71

6-50

5·21

SN5440
SN54ALS40

SN7440
SN74ALS40

6·20

5·14

SN54L71

SN74L71*

6·54

5-21

S·248

S·248

SN5472

SN7472

6-46

5·22

SN54H40

SN74H40

6·20

5·14

SN54H72

SN74H72

6·50

5·22

SN54LS40

SN74LS40

6·20

5-14

SN54L72

SN74L72*

6·54

5·22

SN54S40

SN74S40

6·20

5·14

SN5473

SN7473

6-46

5·22

SN5442A

SN7442A

7·15

7·15

SN54H73

SN74H73

6·50

5·22

SN54L42

SN74L42*

7·15

7·15

SN54L73

SN74L73*

6·54

5·22

SN54LS42

SN74LS42

7·15

7-15

SN54LS73A

SN74LS73A

6·56

5-22

SN5443A

SN7443A

7·15

7·15

SN74L43 1

SN5474

SN7474

SN54L43

7·15

7·15

SN54ALS74

SN74ALS74

6-46

5·22

S·250

S·250

SN5444A

SN7444A

7·15

7·15

SN54H74

SN74H74

6-50

SN74L44 1

5·22

SN54L44

7·15

7·15

SN54L74

SN74L74*

6·54

5·22

SN5445

SN7445

7·20

7·20

SN54LS74A

SN74LS74A

6·56

5-22

SN5446A

SN7446A

7·22

7·22

SN54S74

SN74S74

6·58

5-22

SN54L46

SN74L46 1

7·22

7·22

SN5475

SN7475

7-35

7·35

SN5447A

SN7447A

7·22

7·22

SN54L75

SN74L75*

7-35

7·35

SN54L47

SN74L47 i

7·22

7·22

SN54LS75

SN74LS75

7·35

7·35

SN54LS47

SN74LS47

7·22

7·22

SN5476

SN7476

6-46

5·23

SN5448

SN7448

7·22

7·22

SN54H76

SN74H76

6·50

5·23

SN54LS48

SN74LS48

7·22

7·22

SN74LS76A

7·22

7·22

SN54LS76A
SN5477

6·56
7·35

5·23
7·35

SN5449

•

t Page numbers without "5·" preceding them refer to pages in this data book; those with "5·" refer to pages in 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772.
t Contact the factory for availability.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

1·3

ALPHANUMERIC INDEX

TYPE NUMBERS

•

ELECTRICAL

PIN
ASSIGNMENTS

PAGEt

PAGEt

TYPE NUMBERS

ELECTRICAL

PIN
ASSIGNMENTS

PAGEt

PAGEt

SN54L77

7·35

7·35

SN54Hl06

SN74Hl06

6·52

5·32

SN54LS77

7·35

7·35

SN54107

SN74107

6-46

5·32

SN54H78

SN74H78

6·50

5·24

SN54LS107A

SN74LS107A

6·56

5·32

SN54L78

SN74L78'

6·54

5·24

SN54Hl08

SN74Hl08

6·52

5·32

SN54LS78A

SN74LS78A

6·56

5·24

SN54109

SN74109

6-46

5·33

SN5480

SN7480

7-41

7-41

SN54ALS109

SN74ALS109

5·251

S·251

SN5481A

SN7481A

7-44

7-44

SN54LS109A

SN74LS109A

6·56

5·33

SN5482

SN7482

7-49

7-49

SN54110

SN74110

6-46

5·33

SN5483A

SN7483A

7·53

7·53

SN54111

SN74111

6-46

5·33

SN54LS83A

SN74LS83A

7·53

7·53

SN54ALSl12

SN74ALSl12

5·252

5·252

SN5484A

SN7484A

7-44

7-44

SN54LSl12A

SN74LSl12A

6·56

5·34

SN5485

SN7485

7·57

7·57

SN54S112

SN74S112

6·58

5·34

SN54L85

SN74L85:f

7·57

7·57

SN54ALSl13

SN74ALSl13

S·253

S·253

SN54LS85

SN74LS85

7·57

SN74LSl13A

6·56

5·34

SN74S85

7·57

7·57
7·57

SN54LSl13A

SN54S85

SN54S113

SN74S113

6·58

5·34

SN5486

SN7486

Hi5

7-65

SN54ALSl14

SN74ALSl14

5·254

S·254

SN54L86

SN74L86'

7-65

7·65

SN54LSl14A

SN74LSl14A

6·56

5·34

SN54LS86

SN74LS86

7-65

7-65

SN54S114

SN74S114

6·58

5·34

SN54S86

SN74S86

7-65.

Hi5

SN54116

SN74116

7·115

SN54H87

7·115

SN74H87

7·70

7·70

SN54120

SN74120

7·118

SN7488A

7·118

§

5·27

SN54121

SN74121

6-64

5·35

5·27

SN54L121

SN74L121 t

6-64

5·35

SN5488A

SN7489
SN5490A

SN7490A

7·72

7·72

SN54122

SN74122

6·76

SN54L90

SN74L90'

5·36

7·72

7·72

SN54L122

SN74L122'

6·76

SN54LS90

SN74LS90

5·36

7·72

7·72

SN54LS122

SN74LS122

SN5491A

6·76

SN7491A

5·36

7·81

7·81

SN54123

SN74123

SN74L91,

6·76

SN54L91

5·36

7·81

7·81

SN54L123

SN74L123'

6·76

SN54LS91

SN74LS91

5·36

7·81

7·81

SN54LSI23

SN74LS123

SN5492A

SN7492A

7·72

7·72

SN54S124

SN74S124

SN54LS92

SN74LS92

7·72

7·72

SN54125

SN74125

6·33

5·37

SN5493A

SN7493A

7·72

7·72

SN54LS125A

SN74LS125A

6·33

5·37

6·76

5·36

7·123

7·123

SN54L93

SN74L93'

7·72

7·72

SN54126

SN74126

6·33

5·37

SN54LS93

SN74LS93

7·72

7·72

SN54LS126A

SN74LS126A

6·33

5·37

SN5494

SN7494

7·86

7·86

SN54128

SN74128

6·22

5·37

SN5495A

SN7495A

7·89

7·89

SN74132

6·14

5·37

SN54L95

SN74L95'

7·89

7·89

SN?4 132
SN54LS132

SN74LS132

6·14

5·37

SN54LS95B

SN74LS95B

7·89

7·89

SN54S132

SN74S132

6·14

5·37

SN5496

SN7496

7·95

7·95

SN54ALS133

SN74ALS133

S·255

S·255

SN54L96

SN74L96'

7·95

7·95

SN54S133

SN74S133

6·2

SN54LS96

5·38

SN74LS96

7·95

7·95

SN54S134

SN74S134

6·33

5·38

SN5497

SN7497

7·102

7·102

SN54S135

SN74S135

7·129

SN54L98

7·129

SN74L98'

7·107

7·107

SN54136

SN74L99 1

SN74136

SN54L99

7·131

7·131

7·109

7·109

SN54LS136

SN74LS136

SN54100

7·131

SN74100

7·113

7·131

7·113

SN54LS137

SN54Hl0l

SN74LS137

SN74Hl0l

S·19

6·52

S·19

5·31

SN54LS138

SN54Hl02

SN74LS138

SN74Hl02

7·134

6·52

7·134

5·31

SN54S138

SN74S138

SN74Hl03

7·134

6·52

5·31

SN54LS139

SN74LS139

7·134

7·134
7.134
t Page numbers without "5·" preceding them refer to pages In this data book; those with "5·" refer to pages In 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772.

SN54Hl03

I Contact the factory for availability.

§ For more information on these devices contact the factory.

1-4

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

ALPHANUMERIC INDEX

TYPE NUMBERS

ELECTRICAL

PIN
TYPE NUMBERS

ASSIGNMENTS

ELECTRICAL

PIN
ASSIGNMENTS
PAGEt

PAGEt
SN54LS164

SN74LS164

7-206

7-206

SN54165

SN74165

7-212

7-212

7-138

SN54LS165

SN74LS165

7-212

7-212

7-140
7-143

7-140
7-143

SN54166
SN54LS166

SN74166
SN74LS166

7-217
7-217

7-217
7-217

SN74144

7-143

7-143

SN54167

SN74167

7-222

7-222

SN54145

SN74145

7-148

7-148

SN54S168

SN74S168

7-226

7-226

SN54LS145

SN74LS145

7-148

7-148

SN54LS169A

SN74LS169A

7-226

7-226

SN54147

SN74147

7-151

7-151

SN54S169

SN74S169

7-226

7-226

SN54LS147

SN74LS147

7-151

7-151

SN54170

SN74170

7-237

7-237

SN54148

SN74148

7-151

7-151

SN54LS170

SN74LS170

7-237

7-237

SN54LS148

SN74LS148

7-151

7-151

SN74172

7-245

7-245

SN54150

SN74150

7-157

7-157

SN54173

SN74173

7-249

7-249

SN54151A

SN74151A

7-157

7-157

SN54LS173A

SN74LS173A

7-249

7-249

SN54LS151

SN74LS151

7-157

7-157

SN54174

SN74174

7-253

7-253

SN54S151

SN74S151

SN54S139

SN74S139

7-134

7-134

SN54S140

SN74S140

6-22

5-39

SN74141

7-138

SN54143

SN74142
SN74143

SN54144

7-157

7-157

SN54LS174

SN74LS174

7-253

7-253

SN54152A

7-157

7-157

SN54S174

SN74S174

7-253

7-253

SN54LS152

7-157

7-157

SN54175

SN74175

7-253

7-253

SN54153

SN74153

7-165

7-165

SN54LS175

SN74LS175

7-253

7-253

SN54L 153

SN74L153*

7-165

7-165

SN54S175

SN74S175

7-253

7-253

SN54LS153

SN74LS153

7-165

7-165

SN54176

SN74176

7-259

7-259

SN54S153

SN74S153

7-165

7-165

SN54177

SN74177

7-259

7-259
7-265

SN54154

SN74154

7-171

7-171

SN54178

SN74178

7-265'

SN54Ll54

SN74L154*

7-171

7-171

SN54179

SN74179

7-265

7-265

SN54155

SN74155

7-175

7-175

SN54180

SN74180

7-269

7-269

SN54LS155

SN74LS155

7-175

7-175

SN54181

SN74181

7-271

7-271

SN54156

SN74156

7-175

7-175

SN54AS181

SN74AS181

S-268

S-270

SN54LSl56

SN74LSl56

7-175

7-175

SN54LS181

SN74LS181

7-271

7-271

SN54157

SN74157

7-181

7-181

SN54S181

SN74S181

7-271

7-271

SN54L157

SN74L157 1

7-181

7-181

SN54182

SN74182

7-282

7-282

SN54LS157

SN74LS157

7-181

7-181

SN54S182

SN74S182

7-282

7-282

SN54S157

SN74S157

7-181

7-181

SN54LS183

SN74LS183

7-287

7-287

SN54LS158

SN74LS158

7-181

7-181

SN54H183

SN74H183

7-287

7-287

SN54S158

SN74S158

7-181

7-181

SN54184

SN74184

7-290

7-290

SN54159

SN74159

7-188

7-188

SN54185A

SN74185A

7-290

7-290

SN54160

SN74160

7-190

7-190

SN54186

SN74186

§

5-49

SN54LS160A

SN74LS160A

7-190

7-190

SN54187

SN74187

5-49

SN54161

SN74161

7-190

7-190

SN54LS161A

SN74LS161A

7-190

7-190

SN54S188

SN74S188

5-49

SN54162

SN74162

7-190

7-190

SN54S189

SN74S189

SN54LS162A

SN74LS162A

7-190

7-190

SN54190

SN74190

7-296

7-296

SN54S162

SN74S162

7-190

7-190

SN54LS190

SN74LS190

7-296

7-296

SN54163

SN74163

7-190

7-190

SN54191

SN74191

7-296

7-296

SN54LS163A

SN74LS163A

7-190

7-190

SN54LS191

SN74LS191

7-296

7-296

SN54S163

SN74S163

7-190

7-190

SN54192

SN74192

7-306

7-306

SN54164

SN74164

7-206

7-206

SN54L192

SN74L192 1

7-306

7-306

SN54L164

SN74L164 1

7-206

7-206

SN54LS192

SN74LS192

•

5-49

7-306
7-306
t Page numbers without "5-" preceding them refer to pages in this data book; those with "5-" refer to pages in 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772_
t Contact the factory for availability_
§ For more information on these devices contact the factory_
11 See Bipolar Microcomputer Components Data Book, second edition, or its successor,

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

1·5

ALPHANUMERIC INDEX

TYPE NUMBERS

ELECTRICAL

PIN
ASSIGNMENTS

TYPE NUMBERS

ELECTRICAL

PAGEt

•

PIN
ASSIGNMENTS
PAGEt

SN54193

SN74193

7-306

7-306

SN54LS258A

SN74LS258A

7-372

7-372

SN54L193

SN74L193*

7-306

7-306

SN54S258

SN74S258

7-372

7-372

SN54LS193

SN74LS193

7-306

7-306

SN54259

SN74259

7-376

7-376

SN54194

SN74194

7-316

7-316

SN54LS194A

SN74LS194A

7-316

7-316

SN54LS259
SN54S260

SN74LS259
SN74S260

7-376
6-8

7-376
5-57

SN54S194

SN74S194

7-316

7-316

SN54LS261

SN74LS261

7-380

7-380

SN54195

SN74195

7-324

7-324

SN54265

SN74265

SN54LS195A

SN74LS195A

7-324

7-324

SN54LS266

SN74LS266

SN54S195

SN74S195

7-324

7-324

SN54S270

SN74S270

SN54196

SN74196

7-331

7-331

SN54S271

SN74S271

SN54LSl96

SN74LS196

7-331

7-331

SN54273

SN74273

SN54S196

SN74S196

7-331

7-331

SN54LS273

SN54197

SN74197

7-331

7-331

SN54S274

SN54LS197

SN74LS197

7-331

7-331

SN54LS275

6-89

5-57

7-386

7-386

§

5-58

7-388

7-388

SN74LS273

7-388

7-388

SN74S274

7-391

7-391

SN74LS275

7-391

7-391
7-391

5-58

SN54S197

SN74S197

7-331

7-331

SN54S275

SN74S275

7-391

SN54198

SN74198

7-338

7-338

SN54276

SN74276

7-401

7-401

SN54199

SN74199

7-338

7-338

SN54278

SN74278

7-403

7-403

SN54S201

SN74S201

SN54221

SN74221

~

5-52

SN54279

SN74279

6-{)0

5-59

6-68

5-53

SN54LS279

SN74LS279

6-{)0

5-59

SN54LS221

SN74LS221

6-68

5-53

SN54LS280

SN74LS280

7-406

7-406

SN54LS222

SN74LS222

S-23

S-23

SN54S280

SN74S280

7-406

7-406

SN54LS224

SN74LS224

S-23

S-23

SN54S281

SN74S281

7-410

7-410

SN74S225

~

5-53

SN54283

SN74283

7-415

7-415

SN54S226

SN74S226

7-345

7-345

SN54LS283

SN74LS283

7-415

7-415

SN54LS227

SN74LS227

S-23

S-23

SN54S283

SN74S283

7-415

7-415

SN54LS228

SN74LS228

S-23

S-23

SN54284

SN74284

7-420

7-420

SN54LS240

SN74LS240

6-83

5-53

SN54285

SN74285

7-420

7-420

SN54S240

SN74S240

6-83

5-53

SN54S287

SN74S287

1)

5-{)1

SN54LS241

SN74LS241

6-83

5-54

SN54S288

SN74S288

5-{)1

SN54S241

SN74S241

6-83

5-54

SN54S289

SN74S289

5-61

SN54LS242

SN74LS242

6-87

5-54

SN54290

SN74290

7-423

7-423

SN54LS243

SN74LS243

6-87

5-54

SN54LS290

SN74LS290

7-423

7-423

SN54LS244

SN74LS244

6-83

5-54

SN54LS292

SN74LS292

S-31

S-31

SN54LS245

SN74LS245

7-349

7-349

SN54293

SN74293

7-423

7-423

SN54246

SN74246

7-351

7-351

SN54LS293

SN74LS293

7-423

7-423

SN54247

SN74247

7-351

7-351

SN54LS294

SN74LS294

S-31

S-31

SN54LS247

SN74LS247

7-351

7-351

SN54LS295B

SN74LS295B

7-429

7-429

SN54248

SN74248

7-351

7-351

SN54LS297

SN74LS297

S-38

S-38

SN54LS248

SN74LS248

7-351

7-351

SN54298

SN74298

7-432

7-432

SN54249

SN74249

7-351

7-351

SN54LS298

SN74LS298

7-432

7-432

SN54LS249

SN74LS249

7-351

7-351

SN54LS299

SN74LS299

7-437

7-437

SN54251

SN74251

7-362

7-362

SN54S299

SN74S299

7-431

7-437

SN54LS251

SN74LS251

7-362

7-362

SN54S301

SN74S301

1)

5-63

SN54S251

SN74S251

7-362

7-362

SN54LS320

SN74LS320

S-44

S-44

SN54LS253

SN74LS253

7-369

7-369

SN54LS321

SN74LS321

S-44

S-44

SN54LS257A

SN74LS257A

7-372

7-372

SN54LS322A

SN74LS322A

S-47

S-47

SN54S257

SN74S257

7-372

7-372

SN54LS323

SN74LS323

7-443

7-443

t Page numbers without "S-" preceding them refer to pages in this data book; those with "S-" refer to pages in 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772.

!i For more information on these devices contact the factory.
1) See Bipolar Microcomputer Components Data Book, second edition, or its successor.

1·6

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

ALPHANUMERIC INDEX
TYPE NUMBERS

ELECTRICAL
PAGEt

PIN
TYPE NUMBERS

ASSIGNMENTS
PAGEt

ELECTRICAL
PAGEt

PIN
ASSIGNMENTS
PAGEt

SN54S340

SN74S340

7-445

7-445

SN54LS422

SN74LS422

S-73

S-73

SN54S341

SN74S341

7-445

7-445

SN54LS423

SN74LS423

S-73

S-73

SN54S344

SN74S344

7-445

7-445

SN54425

SN74425

6-33

5-71

SN54LS347
SN54LS348

SN74LS347
SN74LS348

S-51
7-448

S-51
7-448

SN54426

SN74426
5N74S428

6-33
7-514

5-72
7-514
S-77

SN74351

7-451

7-451

SN54S436

SN74S436

S-77

SN54LS352

SN74LS352

7-454

7-454

SN54S437

SN54S437

S-77

S-77

SN54LS353

SN74LS353

7-457

7-457

SN74S438

7-514

7-514

SN54LS354

SN74LS354

S-53

S-53

SN54LS440

SN74L5440

S-81

S-81

SN54LS355

SN74LS355

S-53

S-53

SN54LS441

SN74L5441

S-81

S-81

SN54LS356

SN74LS356

S-53

S-53

SN54LS442

SN74LS442

S-81

S-81

SN54LS357

SN74LS357

5-53

5-53

SN54LS443

SN74LS443

S-81

S-81

SN54365A

SN74365A

6-36

5-66

SN54LS444

SN74LS444

S-81

S-81

SN54LS365A

SN74LS365A

6-36

5-66

SN54LS445

SN74LS445

S-87

S-87

SN54366A

SN74366A

6-36

5-66

SN54LS446

SN74LS446

S-89

S-89

SN54LS366A

SN74LS366A

6-36

5-66

SN54LS447

SN74LS447

S-93

S-93

SN54367A

SN74367A

6-36

5-66

SN54LS448

SN74LS448

S-81

S-81

SN54LS367A

SN74LS367A

6-36

5-66

5N54LS449

5N74L5449

S-89

S-89

SN54368A

SN74368A

6-36

5-66

SN54LS465

SN74LS465

S-95

S-95

SN54LS368A

SN74LS368A

6-36

5-66

SN54LS466

SN74LS466

S-95

S-95

SN54S370

SN74S370

5-67

SN54LS467

5N74LS467

S-95

S-95

SN54S371

SN74S371

SN54LS468

SN74LS468

S-95

S-95

SN54LS373

SN74LS373

7-471

7-471

SN54S470

SN74S470

5-73

SN54S373

SN74S373

7-441

7-471

SN54S471

SN74S471

11
11

SN54LS374

SN74LS374

7-471

7-471

SN54S472

SN74S472

5-73

SN54S374

SN74S374

7-471

7-471

SN54S473

SN74S473

5-73

SN54LS375

SN74LS375

7-478

7-478

SN54S474

SN74S474

5-73

SN54376

SN74376

7-479

7-479

SN54S475

SN74S475

5-73

SN54LS377

SN74LS377

7-481

7-481

SN54S481

SN74S481

5-74

SN54LS378

SN74LS378

7-481

7-481

SN54LS481

SN74LS481

5-74

SN54LS379

SN74LS379

7-481

7-481

SN54S482

SN74S482

SN54S381

SN74S381

7-484

7-484

SN54490

SN74490

7-520

7-520

SN54LS381

SN74LS381

S-60

S-60

SN54LS490

SN74LS490

7-520

7-520

SN54LS382

SN74LS382

S-60

SN54LS540

SN74LS540

S-98

S-98

SN54LS384

SN74LS384

S-60
S-65

5-65

SN54LS541

SN74LS541

S-98

S-98

SN54LS385

SN74LS385

S-69

5-69

SN54ALS573

SN74ALS573

S-256

S-256

SN54LS386

SN74LS386

7-487

7-487

SN54ALS574

SN74ALS574

S-257

S-257

SN54S387

SN74S387

11

5-69

SN54ALS576

SN74ALS576

S-258

S-258

SN54390

SN74390

7-489

7-489

SN54ALS580

SN74ALS580

S-259

S-259

SN54LS390

SN74LS390

7-489

7-489

SN54LS590

SN74LS590

S-101

S-101

SN54393

SN74393

7-489

7-489

SN54LS591

S-101

SN74LS393

7-489

7-489

SN54LS592

SN74LS591
SN74LS592

S-101

SN54LS393

S-105

S-105

SN54LS395A

SN74LS395A

7-496

7-496

5N54LS593

SN74LS593

S-105

S-105

SN54LS396

SN74LS396

S-71

S-71

SN54LS595

SN74LS595

S-110

S-110

SN54LS398

SN74LS398

7-499

7-499

SN54LS596

SN74LS596

S-110

S-110

SN54LS399

SN74LS399

7-499

7-499

SN54LS597

SN74LS597

S-114

S-114

SN54S412

SN74S412

7-502

7-502

SN54LS598

SN74LS598

S-114

S-114

5-67

--

5-73

5-74

t Page numbers without "5-" preceding them refer to pages in this data book; those with "S-" refer to pages in 1981 Supplement to The TTL
Data Book far Design Engineers, LCC5772_
§ For more information on these devices contact the factory_
11 See Bipolar Microcomputer Components Data Book, second edition, or its successor.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

1-7

ALPHANUMERIC INDEX

TYPE NUMBERS

•

ELECTRICAL
PAGEt

PIN
ASSIGNMENTS

TYPE NUMBERS

PAGEt

ELECTRICAL
PAGEt

PIN
ASSIGNMENTS
PAGEt

SN54LS600

SN74LS600

S-119

5-119

5N54L5683

5N74L5683

5-203

5-203

SN54LS601

SN74LS601

S-119

5-119

5N54L5684

5N74L5684

5-203

5-203

SN54LS602

SN74LS602

S-119

5-119

5N54L5685

5N74L5685

S-203

5-203

SN54LS603

SN74LS603

S-119

5-119

5N54L5686

5N74L5686

5-203

5-203

SN54LS604

SN74LS604

S-124

SN54L5687

5N74L5687

5-203

5-203

SN54LS605

SN74LS605

S-124

5-124
S-124

SN54LS688

SN74LS688

S-203

S-203

SN54LS606

SN74 LS606

5-124

5-124

SN54L5689

5N74L5689

5-203

S-203

SN54LS607

SN74LS607

5-124

5-124

SN54L5690

5N74L5690

5-211

5-211

SN54LS608

SN74LS608

5-128

S-128

SN54L5691

5N74L5691

5-211

5-211

SN54LS610

SN74LS610

5-133

5-133

5N54L5692

5N74L5692

5-211

5-211

SN54LS611

SN74LS611

5-133

5-133

5N54L5693

5N74L5693

5-211

5-211

SN54LS612

SN74LS612

5-133

S-133

5N54L5696

SN74L5696

S-217

5-217

SN54LS613

SN74LS613

5-133

S-133

SN54L5697

5N74L5697

5-217

5-217

SN54LS620

SN74LS620

5-141

5-141

SN54L5698

5N74L5698

5-217

5-217

SN54LS621

SN74LS621

5-141

S-141

5N54L5699

SN74L5699

5-217

5-217

SN54LS622

SN74LS622

5-141

5-141

SN54A5800

5N74A5800

5-273

5-273

SN54LS623

SN74LS623

5-141

5-141

SN54A5802

5N74A5802

S-274

5-274

SN54LS624

SN74LS624

5-145

5-145

5N54A5804

5N74A5804

5-275

5-275

SN54LS625

SN74LS625

5-14,5

5-145

5N54A5805

5N74A5805

5-276

5-276

SN54LS626

SN74LS626

5-145

S-145

SN54A5808

5N74A5808

5-277

5-277

SN54LS627

SN74LS627

5-145

5-145

SN54A5832

SN74AS832

5-278

5-278

SN54LS628

SN74LS628

5-145

5-145

5N54A5857

5N74A5857

5-279

5-279

SN54LS629

SN74LS629

5-145

5-145

SN54A5867

5N74A5867

5-280

5-280

SN54LS630

SN74LS630

5-151

5-151

5N54A5869

5N74A5869

5-280

5-280

SN54LS631

SN74LS631

5-151

5-151

SN54A5870

5N74A5870

5-281

5-281

SN54LS638

SN74LS638

5-157

5-157

SN54A5871

5N74A5871

5-281

5-281

SN54LS639

SN74LS639

5-157

S-157

SN54AL5873

5N74AL5873

5-260

5-260

SN54LS640

SN74LS640

5-161

5-161

SN54A5873

5N74A5873

5-283

5-283

SN54LS641

SN74LS641

5-161

5-161

5N54AL5874

5N74AL5874

5-261

5-261

SN54LS642

SN74LS642

5-161

S-161

5N54A5874

5N74A5874

5-284

5-284

SN54LS643

SN74LS643

5-161

5-161

5N54AL5876

5N74ALS876

5-262

S-262

SN54LS644

SN74LS644

5-161

5-161

5N54A5876

5N74A5876

5-285

5-285

SN54LS645

SN74LS645

5-161

5-161

5N54A5877

5N74A5877

5-286

5-286

SN54LS646

SN74LS646

5-168

5-168

5N54AL5880

5N74AL5880

S-263

5-263

SN54LS647

SN74LS647

S-168

5-168

SN54A5880

5N74A5880

5-287

5-287

SN54LS648

SN74LS648

5-168

5-168

5N54A5881

5N74A5881

5-288

5-288

SN54LS649

SN74LS649

5-168

S-168

5N54A5882

5N74A5882

5-291

5-291

SN54LS651

SN74LS651

5-175

5-175

5N54A5885

5N74A5885

5-293

5-293

SN54LS652

SN74LS652

5-175

S-175

5N54A5894

5N74A5894

5-294

SN54LS668

SN74LS668

5-179

5-179

5N54AL51000

5N74AL51000

5264

5-294
5-264

SN54LS669

SN74LS669

5-179

S-179

SN54AL51002

5N74AL51002

5-265

5-265

SN54LS670

SN74LS670

7-526

7-526

SN54AL51003

5N74AL51003

5-266

S-266

SN54LS671

SN74LS671

5-187

5-187

SN54AL51020

5N74AL51020

5-266

5-266

SN54LS672

SN74LS672

S-187

5-187

TIM8228

7-514

7-514

SN54LS673

SN74LS673

5-193

5-193

TlM8238

7-514

7-514

SN54LS674

SN74LS674

5-193

5-193

TlM9905

7-362

7-362

7-376
7-151

7-376
7-151

SN54LS681

SN74LS681

5-197

5-197

TIM9906

5N54L5682

5N74L5682

5-203

S-203

TIM9907

TlM9908
7448
7448
t Page numbers without "S-" preceding them refer to pages in this data book; those with "S-" refer to pages In 1981 Supplement to The TTL
Data Book for Design Engineers, LCC5772,

1-8

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

fUNCTIONAL INDEX/SELECTION GUIDE
The following pages contain functional indexes and selection guides designed to simplify the choit:e of a particular
function to fit a specific application. Essential characteristics of similar or like functions are grouped for comparative
analysis, and the electrical specifications are referenced by page number. The following categories of functions are
covered:
Page

SSI FUNCTIONS
Positive·NAND gates and inverters with totem-pole outputs .
Positive·NAND gates and inverters with open-collector outputs
Positive·NOR gates with totem-pole outputs . . . . . . .
Positive·AND gates with totem-pole outputs . • . . . . •
•••..•.•..
Positive·AND gates with open-collector outputs
Schmitt·trigger positive·NAND gates and inverters with totem-pole outputs
Buffers/clock drivers with totem-pole outputs . • . . • .
50-ohm/75-ohm line drivers . • . • . . . • • . . • • .
Buffer and interface gates with open-collector outputs . • • .
Gates, buffers, drivers and bus transceivers with 3·state outputs
Positive-OR gates with totem-pole outputs
.•.
AND.QR-I NVERT gates with totem-pole outputs .
AND·OR-INVERT gates with open-collector outputs
Expandable gates
...•..
Expanders . . . . . . • . .
Dual j-K edge-triggered flip-flops
Single J·K edge·triggered flip-flops
Pulse-triggered dual flip-flops . •
Pulse·triggered single flip-flops . .
Dual J·K flip-flops with data lockout
Single J·K flip-flops with data lockout
Q~I D·type flip-flops
..... .
S-R latches . • . . . . . . . • .
Current-sensing gates . . . . . . . . . . . .
Monostable multivibrators with Schmitt-trigger inputs
Retriggerable monostable multivibrators
Clock generator circuits . . . . . . . . . . . .

1·10
1·10
1·11
1·11
1·11
1-11
1-12
1-12
1·12
1-13
1-14
1-14
1-14
1-14
1-14
1-15
1·15
1-16
1·16
1·16
1-16
1-16
1·17
1-17
1·17
1-17
1-17

•

MSI/LSI FUNCTIONS
Adders
..................... .
Accumulators, arithmetic logic units, look-ahead carry generators
Multipliers . . . . . .
Comparators . . . . . .
Parity generators/checkers .
Other arithmetic operators
Quad,hex, and octal flip-flops
Register files . . . .
Shift registers . . . •
Other registers
Latches . . . . . .
Clock generator circuits
Code converters . . . .
Priority encoders/registers
Data selectors/multiplexers
.......•.....
Decoders/demultiplexers
Open-collector display decoders/drivers with counters/latches
Open-collector display decoders/drivers . . . . . . . . .
.........,...
Bus transceivers and drivers
Asynchronous counters (ripple clock)-negative-edge triggered
Synchronous counters-Positive-edge triggered
Bipolar bit-slice processor elements
First-in first-out memories (FI FO's) . . . .
Random-access read/write memories (RAM's)
Read-only memories (ROM's)
•.....
Programmable-read-only memories (PROM's)
Microprocessor controllers and support functions
Error detection and correction circuits . . . .

1·18
1·18
1-18
1·18
1·19
1·19
1·19
1·19
1-20
1-20
1·21
1-21
1-21
1-22
1·22
1·23
1·23
1-24
1·25
1·25
1·26
1·26
1·26
1·27
1·27
]·28
1·28
1·28

181

TEXAS INSTRUMENTS
I NCOR PORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

1·9

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
ELECTRICAL TABLES - PAGE
DESCRIPTION

HEX INVERTERS

--

QUADRUPLE 2·INPUT
POSITlVE·NAND GATES

TYPICAL
TYPPOWER
PROPAGATION DISSIPATION
DELAY TIME
PER GATE

POSITIVE·NAND GATES

DUAL 4-INPUT
POSITIVE-NAND GATES

S-INPUT
POSITlVE·NAND GATES

13-INPUT POSITIVE-NAND GATES

DEVICE TYPE
AND PACKAGE
-55°C to 125°C
O°Cto 70°C

3 ns

19mW

SN54S04

J,W

SN74S04

J, N

6 ns

22mW

SN54H04

J,W

SN74H04

J, N

9.5ns

2mW

10 ns

10mW

SN54LS04

J,W

SN74LS04

J, N

SN5404

J,W

SN7404

33ns

lmW

SN54L04

J, T

SN74L04

J, N
J,N

3 ns

19mW

SN54S00

J,W

SN74S00

J, N

6 ns

22mW

SN54HOO

J,W

SN74HOO

J, N

9.5 ns

2mW

SN54LSOO

J,W

SN74LSOO

J, N

10 ns

10mW

SN5400

J,W
J, T

SN7400

J, N
J, N

33ns

TRIPLE 3-INPUT

6-2

1 mW

SN54LOO

3ns

19mW

SN54S10

J,W

SN74S10

J, N

6ns

22mW

SN54Hl0

J,W

SN74Hl0

J,N

9.5 ns

2mW

SN54LS10

J,W

SN74LS10

J, N

10 ns

10mW

SN5410

SN7410

33 ns

lmW

J,W
J, T

SN74Ll0

J, N
J,N'
J, N

SN54Ll0

SN74LOO

3ns

19mW

SN54S20

J,W

SN74S20

6 ns

22mW

SN54H20

J,W

SN74H20

J, N

9.5 ns

2mW

SN54LS20

J,W

SN74LS20

J, N

10 ns

10mW

SN5420

J,W

SN7420

J, N
J,N

33ns

lmW

SN54L20

J, T

SN74L20

3ns

19mW

SN54S30

J,W

SN74S30

J, N

6 ns

22mW

SN54H30

J,W

SN74H30

J, N

17 ns

2.4 mW

SN54LS30

J,W

SN74LS30

J, N

SN5430

SN7430

10 ns

10mW

33ns

lmW

SN54L30

J,W
J, T

SN74L30

J, N
J, N

3ns

19mW

SN54S133

J,W

SN74S133

J, N

PIN
ASSIGNMENTS
PAGE NO_

5-7

5-6

5-10

5-12

5-38

POSITIVE-NAND GATES AND INVERTERS WITH OPEN-COLLECTOR OUTPUTS
ELECTRICAL TABLES - PAGE 6-4
DESCRIPTION

HEX INVERTERS

QUAD'~UPLE 2-INPUT
POSITIVE-NAND GATES

TYPICAL
TYPPOWER
PROPAGATION DISSIPATION
DELAY TIME
PER GATE

DEVICE TYPE
AND PACKAGE
_55°C to 125°C
O°C to 70°C

5 ns

17.5mW

SN54S05

J,W

SN74S05

J, N

8 ns

22mW

SN54H05

J,W

SN74H05

J, N

16 ns
24 ns

SN54LS05

J,W

SN74LS05

J, N

10mW

SN5405

J,W

SN7405

J, N

2mW

5 ns

17.5mW

SN54S03

J,W

SN74S03

J, N

5-7

8 ns

22mW

SN54HOI

J,W

SN74HOI

J, N

5-6

2mW

SN54LSOI

J,W

SN74LSOI

J, N

5-6
5-7
5-6

16ns

2mW

SN54LS03

J,W

SN74LS03

J, N

22 ns

10mW

SN5401

J,W

SN7401

J, N

22 ns
46 ns

10mW

SN5403

J

SN7403

J, N

lmW

SN54LOI

5-7
5-6

~

1 mW

SN54L03

SN74L03

J, N

TRIPLE 3-INPUT

16 ns

2mW

SN54LSI2

J,W

SN74LS12

J, N

POSITIVE-NAND GATES

22 ns

10mW

SN5412

J,W

SN7412

J, N

5 ns

17.5mW

SN54S22

J,W

SN74S22

J, N

DUAL 4-INPUT

5-7

16ns

T
J

POSITIVE-NAND GATES

PIN
ASSIGNMENTS
PAGE NO.

8 ns

22mW

SN54H22

J,W

SN74H22

J, N

16 ns

2mW

SN54LS22

J,W

SN74LS22

J, N

22 ns

10mW

SN5422

J,W

SN7422

J,N

5-7
5-9

5-11

107

1-10

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
POSITIVE-NOR GATES WITH TOTEM-POLE OUTPUTS
ELECTRICAL TABLES - PAGE 6-8
TYPICAL

TYPPOWER

PROPAGATION DISSIPATION

DESCRIPTION

DELAY TIME

29mW

QUADRUPLE 2-INPUT

10 ns

2.75 mW

POSITIVE-NOR GATES

10 ns

14mW

33 ns

1.5mW

B.5 ns
10 ns
10.5 ns
4ns

TRIPLE 3-INPUT
POSITIVE-NOR GATES
DUAL 4-INPUT POSITIVE-NOR
GATES WITH STROBE
DUAL 5-INPUT
POSITIVE-NOR GATES

PIN
ASSIGNMENTS

-55'C to 125'C

PER GATE

3_5 ns

DEVICE TYPE
AND PACKAGE
O'Cto70'C

PAGE NO.

SN54S02

J,W

SN74S02

J, N

SN54LS02

J,W

SN74LS02

J, N

SN5402

SN7402

SN54L02

J,W
J, T

SN74L02

J, N
J, N

22mW

SN5427

J,W

SN7427

J, N

4.5mW

SN54LS27

J,W

SN74LS27

J, N

23mW

SN5425

J,W

SN7425

J, N

5-11

54mW

SN54S260

J,W

SN74S260

J, N

5-5B

5-6

5-12

POSITIVE-AND GATES WITH TOTEM-POLE OUTPUTS

•

ELECTRICAL TABLES - PAGE 6-10
TYPICAL
DESCRIPTION

TYPPOWER

PROPAGATION DISSIPATION
DELAY TIME

QUADRUPLE 2-INPUT
POSITIVE-AND GATES
TR IPLE 3-1 NPUT
POSITIVE-AND GATES
DUAL 4-INPUT

PIN
ASSIGNMENTS

O'Cto 70'C

SN54S0B

J,W

SN74S0B

J, N

SN54LSOB

J,W

SN74LSOB

J, N

19mW

SN540B

J,W

SN740B

J, N

31 mW

SN54S11

J,W

SN74S11

J, N

B.2 ns

40mW

SN54Hll

J,W

SN74Hll

J, N

12 ns

4.25mW

SN54LSll

J,W

SN74LSll

J, N

4.75 ns

32mW

12 ns

4.25 mW

15 ns
4.75 ns

40mW·

B.2 ns

POSITIVE-AND GATES

DEVICE TYPE
AND PACKAGE
-55'C to 125'C

PER GATE

12 ns

4.25 mW

SN54H21

J, W

SN74H21

J, N

SN54LS21

J.W

SN74LS21

J, N

PAGE NO.

5-8

5·9

5-11

POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS
ELECTRICAL TABLES - PAGE 6-12
TYPPOWER

DEVICE TYPE

PIN

PROPAGATION DISSIPATION

AND PACKAGE

ASSIGNMENTS

TYPICAL
DESCRIPTION

QUADRUPLE 2-INPUT
POSITIVE-AND GATES
TRIPLE 3-INPUT
POSITIVE-AND GATES

-55'C to 125°C

O'Cto 70'C

DELAY TIME

PER GATE

6.5 ns
lB.5 ns

32mW
19.4mW

SN54S09

J.W

SN5409

J,W

SN7409

J, N

20 ns

4.25 mW

SN54LS09

J,W

SN74LS09

J. N

SN74S09

PAGE NO.

J. N

6 ns

2BmW

SN54S15

J,W

SN74S15

J, N

10.5 ns

3BmW

SN54H15

J,W

SN74H15

J, N

20 ns

4.25mW

SN54LS15

J,W

SN74LS15

J, N

5-8

5-10

SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
ELECTRICAL TABLES - PAGE 6-14

DESCRIPTION

HEX SCHMITT TRIGGER INVERTERS
QUADRUPLE 2-INPUT
POSITIVE-NAND SCHMITT TRIGGERS

TYPICAL
HYSTERESIS

TYPICAL

DEVICE TYPE

PIN

DELAY

AND PACKAGE

ASSIGNMENTS

-55'C to 125°C

TIME

O.BV

15 ns

SN5414

O.BV

15 ns

0.55 V

B ns
15 ns

O.BV

O'C to 70'C

J,W

SN7414

J, N

SN54LS14

J,W

SN74LS14

J, N

SN54S132

J,W

SN74S132

J, N

SN74132

J, N

SN54132

J,W

O.BV

15 ns

SN54LS132

J,W

SN74LS132

J, N

DUAL 4-INPUT POSITIVE-NAND

O.BV

16.5 ns

SN5413

J,W

SN7413

J, N

SCHMITT TRIGGERS

O.BV

16.5 ns

SN54LS13

J,W

SN74LS13

J, N

PAGE NO.
5·9

5·37

5·9

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

1·11

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
BUFFERS/CLOCK DRIVERS WITH TOTEM-POLE OUTPUTS
(ALSO SEE 3-STATE BUFFERS AND DRIVERS ON PAGE 1-13)
ELECTRICAL TABLES - PAGE 6-20
LOW-LEVEL HIGH-LEVEL TYPICAL TYPPOWER
DESCRIPTION
QUADRUPLE
2·INPUT
POSITIVE·NOR
BUFFERS

•

OUTPUT

OUTPUT

DELAY

PER

CURRENT

CURRENT

TIME

GATE

48mA

-2.4 mA

7 ns

28mW

24mA

-1.2mA

12 ns

5.5mW

12mA

-1.2mA

12 ns

5.5mW

DEVICE TYPE

PIN

AND PACKAGE

ASSIGNMENTS

_55°C to 125°C
SN5428

J,W

SN54LS28

J,W

O°Cto 70°C
SN7428

J, N

SN74LS28

J, N

QUADRUPLE

60mA

-3mA

4 ns

41mW

SN54S37

J,W

SN74S37

J, N

2·INPUT

48mA

-1.2mA

10.5 ns

27mW

SN5437

J,W

SN7437

J, N

POSITIVE-NAND

24mA

-1.2mA

12 ns

4.3mW

SN74LS37

J, N

BUFFERS

12mA

-1.2mA

12 ns

4.3mW

SN54LS37

J,W

60mA

-3mA

4 ns

44mW

SN54S40

J,W

SN74S40

J, N

DUAL 4-INPUT

60mA

-1.5mA

7.5 ns

44mW

SN54H40

J,W

SN74H40

J, N

POSITIVE-NAND

48mA

-1.2mA

10.5 ns

26mW

SN5440

J,W

SN7440

J,N

BUFFERS

24mA

-1.2mA

12 ns

4.3mW

SN74LS40

J, N

12mA

-1.2mA

12 ns

4.3mW

SN54LS40

PAGE NO_

5-12

5-13

5-14

J,W

SO-OHM/7S-0HM LINE DRIVERS
ELECTRICAL TABLES - PAGE 6-22
LOW-LEVEL HIGH·LEVEL TYPICAL TYPPOWER
DESCRIPTION

OUTPUT

OUTPUT

DELAY

PER

CURRENT

CURRENT

TIME

GATE

DEVICE TYPE

PIN

AND PACKAGE

ASSIGNMENTS

_55°C to 125°C

O°Cto 70°C

PAGE NO.

DUAL 4-INPUT
POSITIVE-NAND

SOmA

-40mA

4 ns

44mV'J

2·INPUT

48mA

-42.4 mA

7 ns

28mW

POSITIVE· NOR

48mA

-29mA

7 ns

28mW

SN54S140

J,W

SN54128

J,W

SN74S140

J, N

SN74128

J,N

5-39

LINE DRIVERS
QUADRUPLE
5-37

LINE DRIVERS

BUFFER AND INTERFACE GATES WITH OPEN-COLLECTOR OUTPUTS
ELECTRICAL TABLES - PAGES 6-24 AND 6-26
HIGH·LEVEL LOW·LEVEL TYPICAL TYPPOWER
DESCRIPTION

OUTPUT

OUTPUT

DELAY

PER

VOLTAGE

CURRENT

TIME

GATE

30V

40 mA

13 ns

21 mW

HEX

30V

30 mA

13 ns

21 mW

BUFFERS/DRIVERS

15V

40mA

13 ns

21 mW

DEVICE TYPE

PIN

AND PACKAGE

ASSIGNMENTS

_55°C to 125°C
SN5407

15V

30 mA

13 ns

21 mW

40 mA

12.5 ns

26mW

HEX INVERTER

30V

30 mA

12.5 ns

26mW

8UFFERS/DRIVERS

15V

40 mA

12.5 ns

26mW

15V

30 mA

12.5 ns

26mW

SN5416

J,W

15 V

16mA

13.5 ns

10mW

SN5426

J

2·INPUT
POSITIVE-NAND
BUFFERS

15 V

8mA

16 ns

2mW

15V

4 mA

16 ns

2mW

5.5V

60mA

6.5 ns

41 mW

5.5 V

48mA

12.5 ns

24.4rnW

5.5V

24 mA

19 ns

4.3mW

5.5V

12mA

19 ns

4.3mW

QUADRUPLE

5.5V

48mA

11 ns

28mW

2-INPUT POSITIVE-

5.5V

24 mA

19 ns

5.45mW

NOR BUFFERS

5.5V

12mA

19 ns

5.45mW

SN5406

SN7417

J,N

SN7406

J, N

5·7

SN7416

J, N

5-7
5-10

SN7426

J, N

5-12

SN74LS26

J, N

5-8
5.8
5-10

J,W

5·10

J,W

5-10
5-12
5-12

SN54LS26

J,W

SN54S38

J,W

SN74S38

J, N

SN5438

J,W

SN7438

J,N

SN74LS38

J, N

SN54LS38

J,W

SN5433

J,W

SN7433

J, N

SN74LS33

J, N

SN54LS33

PAGE NO.

J, N

J,W

30V

QUADRUPLE

SN5417

O°Cto 70°C
SN7407

5-13
-

G-13
5-13
5-1.3
5-13

J,W

1071

1-12

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
GATES, BUFFERS, DRIVERS, AND BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
MAXIMUM MAXIMUM

TYPICAL
DESCRIPTION

12-INPUT NAND GATE

QUADRUPLE
BUS BUFFERS/DRIVERS

PROPAGATION

SOURCE

SINK

DELAY TIME

CURRENT

CURRENT

4.5 os

-6.5mA

4.5 os

-2mA

20mA

8 oS

-2.6 mA

24mA

8 os

-lmA

12mA

8.5 os

-2.6 mA

24mA

8.5 oS

-lmA

12mA

10 oS

-5.2mA

16mA

10 os

-2mA

16mA

10 os

-5.2mA

16mA

OUTPUT CONTROLS

10 os

-2mA

16mA

10 os

-5.2 mA

16mA

10 oS

-2mA

16mA

10 os

-5.2mA

16mA

BUFFERS/DRIVERS

_55°C to 125"C

20mA

WITH INDEPENDENT

HEX BUS

DEVICE TYPE

10 oS

-2mA

16mA

9.5 oS

-2.6mA

24mA

9.5 os

-lmA

12mA

9.5 oS

-2.6 mA

24mA

9.5 os

-lmA

12mA

9.5 oS

-2.6 mA

24mA

9.5 oS

-lmA

12mA

9_5 os

-2.6mA

24mA

9.5 oS

-lmA

12mA

11 oS

-5.2mA

32mA

11 oS

-2mA

32mA

11 os

-5.2 mA

32 mA

11 oS

-2mA

32mA

12 oS

-5.2mA

32 mA

12 oS

-2mA

32mA

12 os

-5.2 mA

32 mA

PIN

AND PACKAGE
O°C to 70"C
SN74S134
SN54S134

J, N

J,W
SN74LS125A J, N

SN54LS125A J,W
SN54LS126A J,W
SN54125

J,W
J,W

SN54425

J,W

SN54426

J,N

SN74126

J,N

5-74

SN74426

J, N

5-75
5-75

SN74LS365A J,N

5-68

SN74LS366,o J, N

5-68

SN74LS367A J, N

5-69

:;N74LS368,o J, N

5-69

5-68
5-68
5-69
5-69
J, N

SN74368A

J.N

SN74365A

~,

N

5-68

SN74367A

J, N

5-69

SN74S240

J, N

J,W

5-69

-2mA

32 mA

-15mA

64mA

5 os

-12mA

4BmA

5 os

-15mA

64mA

5 oS

-12mA

4BmA

OCTAL BUS

10 os

-15mA

24mA

BUFFERS/DRIVERS

10 oS

-12mA

12mA

10 os

-15mA

24mA

10 os

-12mA

12mA

10 oS

-15mA

24 mA

10 os

-12mA

12mA

-lmA

10mA

SN74S428

N
N

CONTROLLER AND BUS DRIVER

J, N

J, N

10mA

SN74S43B

24mA

SN74LS242 J, N

-12mA

12mA

-15mA

24mA

12 oS

-12mA

12mA

QUADRUPLE TRANSCEIVERS

10 os

-10.3 mA

20mA

WITH STORAGE (MSIl

10 oS

-6.5 mA

20mA

12 oS

15mA

24mA

12 os

-12mA

12mA

5-55
5-55

J

-lmA
11 os

6-83

5-55
5-55

J
SN74LS244 J,N

SN54LS244

5-54
5-54

J
SN74LS241

SN54LS241

5-55
5-55

SN74LS240 J, N

-15mA

12 oS

OCTAL TRANSCEIVERS (MSIl

SN74S241

SN54LS240

5-54
5-54

11 oS

FOR 8080A SYSTEMS (MSIl

QUADRUPLE TRANSCEIVERS

J

5-69

5-6B

5 os

SN54S241

6-36

5-69

12 os

J

5-68
5-68

J,W

SN54S240

6-33

5-74

SN74366A

SN54367A

5-37

J,N

SN54LS368A J,W

SN54365A

•

5-37

SN74425

SN54LS367A J,W

J,W

5-37

5-37

SN54LS366A J,W

SN54368A

6-33

5-37

5-37

SN54LS365A J,W

J,W

PAGE NO.

5-38

5-37
SN74125

J,W

SN54366A

PAGE NO.

5-37
SN74LS126A J,N

SN54126

ELECTRICAL

ASSIGNMENTS CHARACTERISTICS

SN54LS242 J,W
SN74LS243 J, N

7-514

7-514

5-55

6-B7

7-345

7-345

7-349

7-349

SN54LS243 J,W
SN74S226
SN54S226

J, N

J,W
!

SN54LS245

J

J, N

H7

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

1·13

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
POSITIVE·OR GATES WITH TOTEM·POLE OUTPUTS
ELECTRICAL TABLES - PAGE 6·28
TYPICAL
DESCRIPTION

TYPPOWER

DEVICE TYPE

PROPAGATION DISSIPATION
DELAY TIME

QUADRUPLE 2-INPUT
POSITIVE-OR GATES

PER GATE

4 ns

35mW

12 ns

24mW

12 ns

5mW

PIN

AND PACKAGE
oOeto 70°C
_55°C to 125°C
SN54S32
SN5432

I

SN54LS32

J, W
J, W

SN74S32
SN7432

J, W

SN74LS32

I

J, N
J, N

ASSIGNMENTS
PAGE NO.
5-13

J, N

AND·OR·INVERT GATES WITH TOTEM·POLE OUTPUTS
ELECTRICAL TABLES - PAGE 6·30
TYPICAL

II

TYPPOWER

DEVICE TYPE
AND PACKAGE

PROPAGATION DISSIPATION

DESCRIPTION

2-WIDE 4-INPUT
4-WIDE 4-2-3-2-INPUT
4-WIDE 2-2-3-2-1 NPUT

DELAY TIME

PER GATE

12_5 ns

2_75 mW

_55°C to 125°C
SN54LS55

PIN
ASSIGNMENTS

O°Cto 70°C
SN74LS55

PAGE NO_

43 ns

1.5mW

SN54L55

J,W
J, T

SN74L55

J, N
J, N

3_5 ns

29mW

SN54S64

J,W

SN74S64

J, N

5-20
5·18
5·18

5·19

6_6ns

41 mW

SN54H54

J,W

SN74H54

J, N

4-WIDE 2-INPUT

10_5 ns

23mW

SN5454

J,W

SN7454

J, N

4-WIDE 2-3-3-2-1 NPUT

12_5 ns

4_5mW

SN54LS54

J, N

5·18

43 ns

1_5mW

SN54L54

J,W
J, T

SN74LS54

4-WIDE 2-3-3-2-INPUT

SN74L54

J, N

5·18

DUAL 2-WIDE 2-INPUT

3_5 ns

28mW

SN54S51

J,W

SN74S51

J, N

6_5 ns

29mW

SN54H51

J,W

SN74H51

J, N

10_5 ns

14mW

SN5451

J,W

SN7451

J, N

12.5 ns

2_75mW

SN54LS51

1_5mW

J,W
J, T

SN74LS51

43 ns

SN74L51

J, N
J, N

SN54L51

5-16

AND·OR·INVERT GATES WITH OPEN·COLLECTOR OUTPUTS
ELECTRICAL TABLES - PAGE 6·32
TYPICAL
DESCRIPTION

TYPPOWER

PROPAGATION DISSIPATION
DELAY TIME

PER GATE

5_5 ns

4-WIDE 4-2-3-2-INPUT

36mW

DEVICE TYPE

PIN

AND PACKAGE

ASSIGNMENTS

_55°C to 125°C
SN54S65

I

O°C to 70°C

I J, W ISN74S65 I J, N

PAGE NO_
5·20

EXPANDABLE GATES
ELECTRICAL TABLE - PAGE 6·39
TYPICAL
DESCRIPTION

TYPPOWER

DEVICE TYPE

DELAY TIME
DUAL 4-INPUT POSITIVE-NOR GATES
WITH STR08E
4-WIDE AND-OR GATES
4-WIDE AND-OR-INVERT GATES

PIN

AND PACKAGE
oOe to 70°C
_55°C to 125°C

PROPAGATION DISSIPATION
PER GATE

PAGE NO.

10.5 ns

23mW

SN5423

J,W

SN7423

J, N

5·11

9.9 ns

88mW

SN54H52

J,W

SN74H52

J, N

5-17

6.6 ns

41mW

SN54H53

J,W

SN74H53

J, N

10.5 ns

23mW

SN5453

J,W

SN7453

J, N

2-WIDE AND·OR-INVERT GATES

6.8 ns

30mW

SN54H55

J,W

SN74H55

J, N

DUAL 2-WI DE AND-OR·INVERT

6.5 ns

29mW

SN54H50

J,W

SN74H50

J, N

14mW

SN5450

J,W

SN7450

J, N

GATES

ASSIGNMENTS

10.5 ns

5·17
5-19
5·16

EXPANDERS
ELECTRICAL TABLES - PAGES 6·43, 6·44, AND 6-45
TYPPOWER
DESCRIPTION

DISSIPATION

DEVICE TYPE

PIN

AND PACKAGE

ASSIGNMENTS

_55°C to 125°C

PER GATE

O°C to 70°C

PAGE NO,

4mW

SN5460

J,W

SN7460

J, N

6mW

SN54H60

J,W

SN74H60

J, N

TRIPLE 3-INPUT EXPANDERS

13mW

SN54H61

J,W

SN74H61

J, N

5·19

3-2-2-3-INPUT AND-OR EXPANDERS

25mW

SN54H62

J,W

SN74H62

J, N

5-20

DUAL 4-1 NPUT EXPANDERS

5·19

107

1·14

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
DUAL J-K EDGE-TRIGGERED FLIP-FLOPS

A

c

B
PRESET

o
TO

OTHER

D

R

E

H

T

O

~

.

_____

~

F-F

a

E

SINGLE J-K EDGE-TRIGGERED FLIP-FLOPS

F

DWG
REF.

A

B

C

0

E

t.j, The

H

G

TYPICAL CHARACTERISTICS

DATA TIMES

f max

Pwr/F-F

SETUP

HOLD

(MHz)

(mW)

(ns)

(ns)

DEVICE TYPE

PAGE REFERENCES

AND PACKAGE
-55"C to 125°C

PIN

O°C to 70°C

ASSIGNMENTS

125

75

3~

01

SN54S112

J,W

SN74S112

J, N

50

100

131

01

SN54Hl06

J,W

45

10

201

01

45

10

201

01

SN54LS76A J,W
SN54LSl12A J,W

SN74Hl06
SN74LS76A
SN74LS112A

125

75

3~

01

SN54S114

J,W

50

100

131

01

SN54Hl08

J,W

45

10

201

01

SN54LS78A J,W

SN74LS78A

J, N

45

10

201

01

SN54LSl14A J,W

SN74LS114A

J, N

125

75

3~

01

SN54S113

SN74S113

45

10-

201

01

ELECTRICAL

J, N

5-34
5-32

6-58
6-52

J, N

5-23

6-58

J, N

5-34

6-56

SN74S114

J, N

5-34

SN74Hl08

J, N

5-32
5-24

6-58
6-52
6-56
6-56

5-34

J, N

5-34

6-58

SN54LS113A J,W

SN74LSl13A

J, N

5-34

6-56

5-31
5-22
5-32

6-52
6-56
6-56
6-56
6-46

J,W

50

100

131

01

SN54Hl03

SN74Hl03

J, N

45

10

201

01

10

201

01

SN74LS73A
SN74LS107A

J, N

45

SN54LS73A J,W
SN54LS107A J

J N

33

10

20t

5t

SN54LS109A J,W

SN74LS109A

J, N

5-33

33

45

lOt

6t

SN54109

J,W

SN74109

J, N

5-33

J,W

F

50

100

131

01

SN54Hl0l

J,W

SN74Hl01

J, N

5-31

6-52

G

50

100

131

01

SN54Hl02

J,W

SN74Hl02

J, N

5-31

6-52

H

35

65

20t

5t

SN5470

J,W

SN7470

J, N

5-21

6-46

arrow indicates the edge of the clock pulse used for reference: t for the rising edge, .j, for the falling edge_

877

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

1·15

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PULSE;·TRIGGERED DUAL FLlp·FLOPS

K

J

TO
OTHER

F·F

PULSE·TRIGGERED SINGLE FLIP·FLOPS

M

L

a

DWG.
REF.

I

J
K
L
M
N

TYPICAL CHARACTERISTICS
f max

(MHz)

Pwr/F-F
(mW)

N

DATA TIMES

DEVICE TYPE

SETUP HOLD

AND PACKAGE

(ns)

(ns)

_55°C to 125°C

PAGE REFERENCES
PIN

O°C to 70°C

DWG,
REF,

80

Ot

01

SN54H73

J,W

SN74H73

J, N

5-22

6-50

20

50

Ot

01

SN5473

J,W

SN7473

J, N

5-22

6-46

20

50

Ot

01

SN54107

6-46

Ot

01

SN54173

SN74L73

J, N
J,N

5-32

3.8

J
J, T

SN74107

3

5-22

6·54

30

80

Ot

01

SN54H76

J,W

SN74H76

J, N

5-23

20

50

Ot

01

SN5476

J,W

SN7476

J, N

5-23

6·50
6-46

30

80

ot

01

SN54H78

6-50

ot

01

SN5417B

SN74L7B

J, N
J, N

5-24

3.8

J,W
J, T

SN74H78

3

5·24

6·54

30

BO

Ot

01

SN54H71

J,W

SN74H71

J, N

5·21

6-50

30

BO

Ot

01

SN54H72

J,W

SN74H72

J, N

5-22

20

50

Ot

01

SN5472

SN7472

6-50
6-46

3.B

ot

01

SN54L72

J, N
J, N

5-22

3

J,W
J;-T SN74L72

5·22

6-54

3

3.B

Ot

01

SN54171

J, T

SN74171

J,N

5·21

6·54

TYPICAL CHARACTERISTICS
f max
(MHz)

Pwr/F-F
(mW)

DATA TIMES
(ns)

Q

DEVICE TYPE

SETUP HOLD
(ns)

D·TYPE FLlP·FLOPS
DUAL

PAGE REFERENCES
PIN

AND PACKAGE
_55°C to 125°C

O°Cto 70°C

ASSIGNMENTS

ELECTRICAL

0

25

70

Ot

30t

SN54111

J,W

SN74111

J, N

5-33

6-46

P

25

100

20t

5t

SN54110

J,W

SN74110

J, N

5-33

6-46

110

75

3t

2t

SN54S74

J,W

SN74S74

J, N

5-22

6-58

43

75

15t

5t

SN54H74

J,W

SN74H74

J, N

6-50

33

10

25t

5t

SN54 LS14A

J,W

SN74LS74A· J, N

5-22
5-22

25

43

20t

5t

SN5474

J,W

SN7474

6-46

3

4

50t

15t

.l,T

SN74174

5:22
5:22

a

t ~ The arrow

ELECTRICAL

30

J·K FLIp· FLOPS WITH DATA LOCKOUT
DUAL
SINGLE
P

o

ASSIGNMENTS

SN54L74

indicates the edge of the clock pulse used for reference:

t

J, N

-J, N

6-56
6-54

for the rising edge, ~ for the falling edge.

1076

1·16

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

SSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
~-R LATCHES

ELECTRICAL TABLES - PAGE 6-60
DESCRIPTION

QUADRUPLE

S·R

TYPICAL

TYPTOTAL

DEVICE TYPE

PIN

PROPAGATION

POWER

AND PACKAGE

ASSIGNMENTS

DELAY TIME

DISSIPATION

I

PAGE NO.

LATCHES

12 ns

19mW

12 ns

90mW

_55°C to 125°C

0°Cto70°C

SN54LS279I J, W I SN74LS279I J, N
SN54279
J, W SN74279
J, N

5-60

CURRENT-SENSING-GATES
ELECTRICAL TABLES - PAGE 6-62
DESCRIPTION

TYPICAL

TYPPOWER

DEVICE TYPE

PIN

PROPAGATION

DISSIPATION

AND PACKAGES

ASSIGNMENTS

DELAY TIME

PER GATE

HEX

21 ns

_55°C to 125°C

3.3mW

I

SN54LS63

J, W

I

I

O°C to 70°C
SN74LS63

I

II

PAGE NO.
J, N

5·20

MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
ELECTRICAL TABLES - PAGES 6-64 ANO 6-68
NO. OF INPUTS

DESCRIPTION

POSITIVE NEGATIVE
SINGLE

DUAL

OUTPUT

TYPTOTAL

DEVICE TYPE

PIN

PULSE

POWER

AND PACKAGE

ASSIGNMENTS

RANGE

DISSIPATION

_55°C to 125°C

1

2

40 ns-28 s

90mW

SN54121

J,W

1

2

40 n,-28 5

40mW

SN54L121

J, T

1

1

20 ns-70 5

23mW

1

1

20 n5-49 5

23mW

1

1

20 n5-28 5

130mW

1

1

20 n5-21 5

130mW

SN54LS221

J,W

SN54221

J,W

O°Cto 70°C
SN74121

J, N

SN74L121

J, N

SN74LS221

J, N

SN74221

J, N

PAGE NO.
5-~5

5-54

RETRIGGERABLE MONOSTABLE MUL TIVIBRATORS
ELECTRICAL TABLES - PAGE 6-76
DESCRIPTION

NO. OF INPUTS
POSITIVE NEGATIVE

SINGLE

DUAL

DIRECT
CLEAR
Ve5

OUTPUT

TYP

DEVICE TYPE

PIN

PULSE

TOTAL

AND PACKAGE

ASSIGNMENTS

RANGE

POWER

_55°C to 125°C

2

2

45n5- 00 115mW SN54122

2

2

Yes

90 n5- 00

2

2

Ves

45ns- 00

1

1

Ves

45ns- 00 230mW SN54123

1

1

Ves

90n5- 00 115mW SN54L123

1

1

Ve5

45 n5- 00

O°Cto 70°C

J,W

SN74122

J, N

55mW SN54L122

J, T

SN74L122

30mW SN54LS122

J,W

SN74LS122

J, N
J, N

J,W

SN74123

J, N

60mW SN54LS123

J

SN74L123

J, N

J,W

SN74LS123

J, N

PAGE NO.
5-36

5-36

CLOCK GENERATOR CIRCUITS

ELECTRICAL TABLES - PAGES 6-89 AND 7-123
TYPTOTAL
DESCRIPTION

AND PACKAGE
Oa Cto 70°C
_55°C to 125°C

DISSIPATION
QUADRUPLE COMPLEMENTARV-OUTPUT
LOGIC ELEMENTS
DUAL VOLTAGE-CONTROLLED OSCILLATORS (MSI)

PIN

DEVICE TYPE

POWER

ASSIGNMENTS
PAGE NO.

125mW

SN54265

J,W

SN74265

J, N

5-58

525mW

SN54S124

J,W

SN74S124

J, N

7-123

181

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

1·17

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
ADDERS
TYPICAL

TYPICAL

TYP POWER

DEVICE TYPE

CARRY

ADD'

DISSIPATION

AND PACKAGE

TIME

TIME

PER BIT

SINGLE 1-BIT GATED FULL ADDERS

10.5 ns

52 ns

105mW

SN5480

SINGLE 2-BIT FULL ADDERS

14.5 ns

25 ns

87mW

10 ns

15 ns

24mW

10 ns

15 ns

24mW

11 ns

7 ns

124mW

SN54S283

10 ns

16 ns

76mW

SN5483A

10 ns

16 ns

76mW

SN54283

J,W

11 ns

11 ns

110mW

15 ns

15 ns

23mW

DESCRIPTION

SINGLE 4-BIT FULL ADDERS

II

DUAL 1-BIT CARRY·SAVE FULL ADDERS

_55°C to 125°C

PAGE

O°C to 70°C

J,W

SN7480

SN5482

J,W

SN54LS83A

J,W

SN54LS283

J,W

NO.

J, N

7-41

SN7482

J, N

7-49

SN74LS83A

J, N

7·53

SN74LS283

J, N

7-415

J

SN74S283

J, N

7-415

J,W

SN7483A

J, N

7-53

SN74283

J, N

7-415

SN54H183

J,W

SN74H183

J, N

7-287

SN54LS183

J,W

SN74LS183

J, N

7-287

ACCUMULATORS, ARITHMETIC LOGIC UNITS, LOOK-AHEAD CARRY GENERATORS
TYPICAL TYPICAL
DESCRIPTION
4-BIT PARALLEL
BINARY ACCUMULATORS
4-BIT ARITHMETIC LOGIC UNITS!
FUNCTION GENERATORS

LOOK·AHEAD CARRY GENERATORS

TYP TOTAL

DEVICE TYPE

CARRY

ADD

POWER

AND PACKAGE

TIME

TIME

DISSIPATION

10 ns

20 ns

720mW

11 ns

20 ns

525mW

7 ns

11 ns

600mW

SN54S181

12.5 ns

24 ns

455mW

16 ns

24 ns

102mW

7 ns
13 ns

_55°C to 125°C
SN54S281

J,W

PAGE
NO.

O°C to 70°C
SN74S281

J, N

SN74S381

N

7-484

J,W

SN74S181

J, N

SN54181

J,W

SN74181

J, N

7-271
7·271

SN54LS181

J,W

SN74LS181

J, N

260mW

SN54S182

J,W

SN74S182

J, N

180mW

SN54182

J,W

SN74182

J, N

7-410

7-271
7-282

MUL TIPLIERS
DEVICE TYPE AND PACKAGE

DESCRIPTION

_55°C to 125°C

PAGE

O°C to 70°C

NO.

2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

SN54LS261

J,W

SN74LS261

4-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

SN54284, SN54285
SN54S274

J,W
J

SN74284, SN74285

J, N

7-420

SN74S274

J, N

7-391

7-BIT-SLICE WALLACE TREES

J, N

SN54LS275

J

SN74LS275

J, N

SN54S275

J

SN74S275

J, N

7-380

7-391

25-MHz 6-BIT-BINARY RATE MULTIPLIERS

SN5497

J,W

SN7497

J, N

7-102

25-MHz DECADE RATE MULTIPLIERS

SN54167

J,W

SN74167

J, N

7·222

COMPARATORS

DESCRIPTION

4-BIT MAGNITUDE COMPARATORS

TYPICAL

TYPTOTAL

DEVICE TYPE

COMPARE

POWER

AND PACKAGE

TIME

DISSIPATION

_55°C to 125°C

PAGE
NO.

O°C to 70°C

11.5 ns

365mW

SN54S85

J,W

SN74S85

J, N

21 ns

275mW

SN5485

J,W

SN7485

J, N

23.5ns

52mW

SN54LS85

J,W

SN74LS85

J, N

82 ns

20mW

SN54L85

SN74L85

J, N

J

7-57

877

1·18

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PARITY GENERATORS/CHECKERS

DESCRIPTION

9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
8·BIT ODD/EVEN PARITY GENERATORS/CHECKERS

TYPICAL

TYP TOTAL

DELAY

POWER

TIME

DISSIPATION

DEVICE TYPE

1

_55°C to 125°C

31 ns

80mW

13 ns

335mW

SN54LS280
SN54S280

35 ns

170mW

SN54180

J, W
J, W

1 J,W

PAGE

O°C to 70°C
SN74LS280
SN74S280
SN74180

NO.

I

J, N
J, N

7-406

I J, N

7·269

OTHER ARITHMETIC OPERATORS
TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

DESCRIPTION

QUADRUPLE 2·INPUT EXCLUSIVE·OR
GATES WITH TOTEM·POLE OUTPUTS

7 ns

250mW

10 ns
10 ns
14 ns

150mW

-55°C to 125°C

O°C to 70°C

NO •

SN54S86

J,W

SN74S86

30mW

SN54LS86

J,W

SN74LS86

J, N

7·65

30mW

SN54LS386

J,W

SN74LS386

J, N

7-487

SN5486

SN7486

J, N
,J, N

7·65
7-65

J, N

7·65

55 ns

15mW

SN54L86

J,W
J, T

QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES

18 ns

30mW

SN54LS136

J,W

SN74LS136

J, N

WITH OPEN·COLLECTOR OUTPUTS

27 ns

150mW

SN54136

J,W

SN74136

J, N

QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES

18 ns

40mW

SN54LS266

J,W

SN74LS266

J, N

7·386

8 ns

325mW

SN54S135

J,W

SN74S135

J, N

7·129

14 ns

270mW

SN54H87

J,W

SN74H87

J, N

7·70

QUADRUPLE EXCLUSIVE OR/NOR GATES
4-BIT TRUE/COMPLEMENT, ZERO/ONE ELEMENT

SN74L86

•

PAGE

7·131

QUAD, HEX, AND OCTAL FLlP·FLOPS
POWER

F·F
DESCRIPTION

FREQ

PER
PKG

o TYPE 3·STATE WITH
o TYPE WITH

ENABLE

ENABLE

DEVICE TYPE

SETUP

HOLD

FLlp·FLOP

ns

ns

PAGE

AND PACKAGE
_55°C to 125°C

O°C to 70°C

NO.

50 MHz

17mW

20t

Ot

SN54LS374

J

SN74LS374

J, N

100 MHz

56mW

5t

2t

SN54S374

J

SN74S374

J, N

7-471

8

40 MHz

10.6mW

20t

5t

SN54LS377

J

SN74LS377

J, N

7-481

6

40 MHz

10.6mW

20t

5t

SN54LS378

J,W

SN74LS378

J, N

7-481

4

40 MHz

10.6mW

20t

5t

SN54LS379

J

SN74LS379

J, N

7-481

40MHz

39mW

20t

5t

SN54273

J

SN74273

J, N,

40MHz

10.6mW

20t

5t

SN54LS273

J

SN74LS273

J, N

35 MHz

38mW

20t

5t

SN54174

J,W

SN74174

J, N

40 MHz

10.6mW

20t

5t

SN54LS174

J,W

SN74LS174

J, N

110 MHz

75mW

5t

3t

SN54S174

J,W

SN74S174

J, N

8

8

o TYPE WITH CLEAR

DATA TIMES

PER

6

35 MHz

38mW

20t

5t

SN54175

J,W

SN74175

J, N

40 MHz

10.6mW

20t

5t

SN54LS175

J,W

SN74LS175

J, N

110 MHz

75mW

5t

3t

SN54S175

J,W

SN74S175

J, N

4

7-471

7·388

7·253

7·253

J·K TYPE WITH SEPARATE CLOCK

4

50 MHz

75mW

3~

10~

SN54276

J

SN74276

J, N

7-401

J·K TYPE WITH COMMON CLOCK

4

45 MHz

65mW

ot

20t

SN54376

J,W

SN74376

J, N

7-479

REGISTER FILES

DESCRIPTION
EIGHT WORDS OF TWO BITS
FOUR WORDS OF FOUR BITS
FOUR WORDS OF FOUR BITS
(3-STATE OUTPUTS)

TYPICAL

TYP READ

DATA

TYPTOTAL

DEVICE TYPE

ADDRESS

ENABLE

INPUT

POWER

AND PACKAGE

TIME

TIME

RATE

DISSIPATION

33 ns

15 ns

20 MHz

560mW

-55°C to 125°C

PAGE

O°C to 70°C
SN74172

J, N

27 ns

15 ns

SN54LS170

J,W

SN74LS170

J, N

15 ns

20 MHz
20 MHz

125mW

30 ns

635mW

SN54170

J,W

SN74170

J, N

24 ns

19 ns

20 MHz

135mW

SN54LS670

J,W

SN74LS670

J, N

NO.
7·245
7·237
7·526

181

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

1·19

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
SHIFT REGISTERS
NO.
DESCRIPTION

SHIFT

OF
BITS

8

PARALLEL-IN,
PARALLEL-OUT
(BIDIRECTIONAL)

a

4

V8
5

PARALLEL·IN,
PARALLEL·OUT
4

SERIAL-IN,
PARALLEL-OUT

PARALLEL·IN,

8

8

SERIAL-OUT
4
SERIAL·IN,
SERIAL·OUT

FREQ

SERIAL
DATA
INPUT

50 MHz

D

Low

35 MHz

D

Low

35 MHz

D

25 MHz

D

Low

70 MHz

D

25 MHz

D

25 MHz

D

25 MHz
/ 10MHz

MODES

~
o
ril ril ..I

++ ++

a:

..I

90

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

-55°C to 125°C
J: DISSIPATION
X X X X
750mW
SN54S299
J,W
X X X X
SN54LS299*
175mW
J

Sync L X X X X

PAGE

O°C to 70°C
J, N

7-437

J, N

7-437

SN74LS323*

J, N

7-443
7-338

SN54LS323*

X X X X

360mW

SN54198

J,W

SN74198

J N

Low

X X X X

450mW

SN54S194

J,W

SN74S194

J, N

Low

X X X X

75mW

SN54LS194A

J,W

SN74LS194A

J, N

Low

X X X X

195mW

SN54194

J,W

SN74194

J N

J-K

Low

X

X X

360mW

SN54199

J,W

SN74199

J, N

D

Low

X

X

60mW

SN54LS96

J,W

SN74LS96

J, N

J,W

J

NO.

SN74S299
SN74LS299*

175mW

10MHz

D

Low

X

X

240mW

SN5496

SN7496

J, N

5 MHz

D

Low

X

X

120mW

SN54L96

J

SN74L96

J N

7-316
7-338
7-95

70 MHz

J·K

Low

X

X

375mW

SN54S195

J,W

SN74S195

J, N

7·324

30 MHz

J·K

Low

X

X

195mW

SN54195

J,W

SN74195

J, N

7·324

30MHz

D

Low

X

X

75mW

SN54LS395A

J,W SN74LS395A

J, N

7-496

25 MHz

D

None

X

X

195mW

SN5495A

J,W

SN7495A

J, N

7·89

25 MHz

D

Low

X

X X

230mW

SN54179

J,W

SN74179

J, N

7·265

25 MHz

D
J·K

None

X

X X

230mW

SN54178

J,W

SN74178

J, N

7·265

30 MHz

Low

X

X

70mW

SN54LS195A

J,W

SN74LS195A

J, N

7·324

30MHz

D

None

X

X

65mW

SN54LS95B

J,W

SN74LS95B

J, N

7·89

30MHz

D

None

X

X

70mW

J,W

SN74LS295B

J, N

7-429

3 MHz

J-K

None

X

X

19mW

SN54LS295B
SN54L99

None

X

X

19mW

SN54L95

SN74L95

J, N
J, N

7·109

D

J
J,T

SN74L99

3 MHz

25 MHz Gated D

Low

X

80mW

SN54LS164

J,W

SN74LSl64

J, N

25 MHz Gated D

Low

X

167mW

SN74164

Low

X

84mW

J, N
J, N

7-206

12 MHz Gated D

7·212

SN54164

J,W
,J, T

SN54L164

SN74L164

7-89

25 MHz

D

None

X

X X

210mW

SN54165

J,W

SN74165

J, N

35 MHz

D

None

X

X X

105mW

SN54LS165

J,W

SN74LS165

J, N

7-212

20 MHz

D

Low

X

X X

360mW

SN54166

J,W

SN74166

7-217

35 MHz

D

Low

X

X X

110mW

SN54LS166

J,W

SN74LS166

J, N
J, N

10MHz

D

High

X

X

175mW

SN5494

J,W

SN7494

J, N

7-86

None

X

60mW

SN54LS91

J,W

SN74LS91

J, N

25 MHz Gated D
8

ASYNC
CLEAR

10MHz Gated D

None

X

175mW

SN5491A

J,W

SN7491A

J, N

3 MHz Gated D

None

X

17.5mW

SN54L91

J, T

SN74L91

J, N

7-217

7·81

*S-R =shift right, S·L = shift,left

OTHER REGISTERS

DESCRIPTION

QUADRUPLE MULTIPLEXERS

FREQ

ASYNC
CLEAR

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

DISSIPATION

_55°C to 125°C

PAGE

O°C to 70°C

NO.

30MHz

None

36.5 mW

SN54LS398

J

SN74LS398

J, N

7-499

30 MHz

None

36.5 mW

SN54LS399

J,W

SN74LS399

J, N

7-499

25 MHz

None

65mW

SN54LS298

J,W

SN74LS298

J, N

7-432

25 MHz

None

195mW

SN54298

J,W

SN74298

J, N

7-432

3 MHz

None

25mW

SN54L98

J

SN74L98

J, N

7-107

8-BIT UNIVERSAL SHIFT/STORAGE

35 MHz

Low

175mW

J

SN74LS299

REGISTERS

50MHz

Low

750mW

SN54LS299
SN54S299

7-437

25 MHz

High

250mW

50 MHz

High

85mW

WITH STORAGE

QUADRUPLE BUS·BUFFER REGISTERS

SN54173
SN54LS173A

J,W

SN74S299

J, N
J, N

J,W

SN74173

J, N

J,W

SN74LS173A

J, N

7-249

181

1·20

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
LATCHES
NO.
DESCRIPTION

OF

CLEAR

OUTPUTS

TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

11 ns

410mW

SN54S412

BITS
MULTI-MODE BUFFERED

8

ADDRESSABLE

8

TRANSPARENT

8

DUAL 4-BIT WITH
INDEPENDENT ENABLE

DUAL 2-BIT WITH
INDEPENDENT ENABLE

aUAD S-R (SSI)

8

4

4

Low

a

-55°C to 125°C

PAGE

O°C to 70°C

J

SN74S412

J, N

NO.
7-502

Low

a

12 ns

300mW

SN54259

J,W

SN74259

J, N

Low

a

17 ns

110mW

J,W

SN74LS259

J, N

None

Q

19 ns

120mW

SN54LS259
SN54LS373

J

SN74LS373

J, N

7-471

None

a

7 ns

525 mW

SN54S373

J

SN74S373

J, N

7-471

Low

a

11 ns

250mW

SN54116

J,W

SN74116

J, N

7-115

None

a

15 ns

320mW

SN541 00

J,W

SN74100

J, N

7-113

None

a,a

15 ns

160mW

SN5475

J,W

SN7475

J, N

7-35

None

a,a

30 ns

80mW

J

SN74L75

J, N

7-35

J,W

SN74LS75

J, N

7-35

None

a,a

11 ns

32mW

None

a

15 ns

160mW

None

a

30 ns

None

a

None

a,a

SN54L75
SN54LS75

7-376

SN5477

W

7-35

80 mW

SN54L77

T

7-35

10 ns

35mW

SN54LS77

W

12 ns

32 mW

SN54LS375

J,W

a

7-35
SN74LS375

J, N

None

a

12 ns

90mW

SN54279

J,W

SN74279

J, N

None

Q

12 ns

19mW

SN54LS279

J,W

SN74LS279

J, N

7-478
6-60

VOLTAGE-CONTROLLED OSCILLATORS
CLOCK GENERATOR CIRCUITS
ENABLE COMPLEMENTARY
INPUT
OUTPUTS

DESCR IPTION

SINGLE VCO

DUAL VCO

DUAL PULSE
SYNCHRONIZER

TYPICAL
POWER
DISSIPATION

FREaUENCY
RANGE

DEVICE TYPE AND PACKAGE
_55°C to 125°C

O°C to 70°C

PAGE
NO.

YES
YES

YES
YES

1 Hz to 20 MHz
1 Hz to 20 MHz

100 mW
100 mW

SN54LS624
SN54LS628

J,W
J,W

SN74LS624
SN74LS628

J,N
J,N

7-460
7-460

YES
NO
YES
NO
YES

NO
YES
YES
NO
NO

1
1
1
1
1

525
175
175
175
175

SN54S124
SN54LS625
SN54LS626
SN54LS627
SN54LS629

J,W
J,W
J,W
J,W
J,W

SN74S124
SN74LS625
SN74LS626
SN74LS627
SN74LS629

J,N
J,N
J,N
J,N
J,N

7-123
7-460
7-460
7-460
7-460

YES

YES

SN54120

J,W

SN74120

J,N

7-118

Hz
Hz
Hz
Hz
Hz

to
to
to
to
to

60
20
20
20
20

MHz
MHz
MHz
'MHz
MHz

DC to 30 MHz

mW
mW
mW
mW
mW

255 mW

CODE CONVERTERS
TYPICAL
DELAY TIME

DESCRIPTION

PER PACKAGE
LEVEL

TYPICAL

DEVICE TYPE

TOTAL POWER

AND PACKAGE

DISSIPATION

-55°C to 125°C

PAGE
NO.

O°C to 70°C

6-LlNE-BCD TO 6-LlNE
BINARY, OR 4-LlNE TO 4-LlNE

25 ns

280mW

SN54184

J,W

SN74184

J, N

7-290

25 ns

280mW

SN54185A

J,W

SN74185A

J, N

7-290

BCD 9's/BCD 1 O's CONVERTERS
6-BIT-BI NARY TO 6-BIT-BCD CONVERTERS

181

TEXAS INSTRUMENTS
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1-21

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PRIORITY ENCODERS/REGISTERS

DESCRIPTION

FULL BCD PRIORITY ENCODERS
CASCADABLE OCTAL PRIORITY ENCODERS

•

CASCADABLE OCTAL PRIORITY ENCODERS
WITH 3-STATE OUTPUTS
4-BIT CASCADABLE PRIORITY REGISTERS

TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

10 ns

225mW

15 ns

60mW

-55°C to 125°C

PAGE
NO.

O°C to 70°C

SN54147

J,W

SN74147

J, N

SN54LS147

J,W

SN74LS147

J, N

7-151

12 ns

190mW

SN54148

J,W

SN74148

J, N

15 ns

60mW

SN54LS148

J,W

SN74LS148

J, N

16 ns

63mW

SN54LS348

J,W SN74LS348

J, N

7-448

35 ns

275mW

SN54278

J,W

J, N

7-403

SN74278

7-151

DATA SELECTORS/MULTIPLEXERS
TYPE
DESCRIPTION

OF
OUTPUT

16-L1NE-TO-1-L1NE
DUAL
8-L1NE-TO-1-L1NE

8-L1NE-TO-1-L1NE

2-State

TYPICAL DELAY TIMES
DATA TO

DATA TO

INV

NON-INV

OUTPUT

OUTPUT

11 ns

4-L1NE-TO-1-L1NE

DEVICE TYPE

POWER

AND PACKAGE

ENABLE

DISSIPATION

18 ns

200mW

_55°C to 125°C
SN54150

J,W

SN74150

3-State

10 ns

17 ns

220mW

4.5 ns

8 ns

14 ns

275mW

SN54S251

J,W

SN74S251

3-State

17 ns

21 ns

21 ns

250mW

SN54251

J,W

3-State

17 ns

21 ns

21 ns

35mW

SN54LS251

J,W

2-State

4.5 ns

8ns

9 ns

225mW

SN54S151

2-State

8 ns

16 ns

22 ns

145mW

SN54151A

130mW

SN54152A

W

18 ns

27 ns

30mW

SN54LS151

J,W

18 ns

28mW

SN54LS152

W

16 ns

35mW

SN54LS253

2-State

8 ns

2-State

11 ns

2-State

11 ns
12 ns

2-State

15 ns

3-State

12 ns

I

PAGE
NO.

O°C to 70°C

3-State

3-State

DUAL

TYP TOTAL

FROM

SN74351

J, N

7-157

N

7-451

J, N

7-362

SN74251

J, N

7-362

SN74LS251

J, N

7-362

J,W

SN74S151

J, N

7-157

J,W

SN74151A

J, N

7·157

SN74LS151

J, N

7-157

J,W

SN74LS253

J, N

7-369

7-157
7-157

22 ns

31 mW

SN54LS352

J,W

SN74LS352

J, N

7-454

21 ns

43mW

SN54LS353

J,W

SN74LS353

J, N.

7-457
7-165

2-State

6 ns

9.5 ns

225mW

SN54S153

J,W

SN74S153

J, N

2-State

14 ns

17 ns

180mW

SN54153

J,W

SN74153.

J, N

7=.165

2-State

14 ns

17 ns

31 mW

SN54LS153

J,W

SN74LS153

J, N

7-165

2-State

27 ns

34 ns

90mW

SN54L153

J

SN74L153

J, N

7-165

2-State

20 nst
20nst
20n$t
20nst

65mW

SN54LS298

J,W

SN74LS298

J, N

7-432

SN54298

J,W

7-432

QUADRUPLE

2-State

2-L1NE-TO-1-L1NE

2-State

WITH STORAGE

2-State
2-State
3-State

20 nst

5 ns
4 ns
5 ns

2-State
QUADRUPLE

3-State

2-L1NE-TO-1-L1NE

3-State
2-State
2-State

12 ns
12 ns
7 ns
9 ns

SN74298

J, N

32mW

SN54LS398

J

SN74 LS398

J, N

7-499

37mW

J,W
J
J,W

SN74LS399
SN74L98
SN74S258

J, N
J. N
J, N

7-499
7-107
7-372
7-372

14 ns.

25mW
280mW

SN54LS399
SN54L98
SN54S258

14 ns

320mW

SN54S257

J,W

SN74S257

J, N

7 ns

195mW

SN54S158

J,W

SN74S158

J, N

7-181

8 ns

250mW

SN54S157

J,W

SN74S157

J, N

7-181

20 ns

60mW

SN54LS258A

J, N

7-372

20 ns

60mW

J, N

7-372

12 ns

24mW

SN54LS257A
SN54LS158

14 ns

49mW

120 nst
4 ns

3-State
2-State

195mW

2-State

9 ns

14 ns

150mW

2-State

18 ns

27 ns

75mW

J,W SN74LS258A
J,W SN74LS257A
J,W

SN74LS158

J, N

7-181

SN54LS157

J,W

SN74LS157

J, N

7-181

SN54157

J,W

SN74157

J, N

7-181

SN74L157

J, N

7-181

SN54L157

J

tFrom clock.

181

1-22

TEXAS INSTRUM·ENTS
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MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

DECODERSIDEMUL TIPLEXERS

DESCRIPTION

4-LINE-T0-16-L1NE

4-LINE-TO-10-L1NE,
BCD-TO-DECIMAL

TYPICAL TYPICAL

TYPE OF
OUTPUT

TYPTOTAL

DEVICE TYPE

SELECT

ENABLE

POWER

AND PACKAGE

TIME

TIME

DISSIPATION

Totem-Pole

23 ns

19 ns

170mW

Totem-Pole

46 ns

38 ns

85mW

Open-Collector

24 ns

19 ns

170mW

Totem-Pole

17 ns

Totem-Pole

17 ns

Totem-Pole

34 ns

J,W

SN54L154

J

35mW

SN54LS42

J,W

SN54LS42

SN5442A

J,W

SN7442A

70mW

SN54L42

J

SN74L42

17 ns

140mW

SN5443A

34 ns

70mW

SN54L43

J

Totem-Pole

17 ns

140mW

SN5444A

Totem-Pole

34 ns

70mW

SN54L44

DUAL 2-L1NE-TO-4-L1 NE

7-171
7·188

140mW

Totem-Pole

3-L1NE-T0-8-LlNE

7-171

J,
J,
J,
J,
J,
J,

SN74159

Totem-Pole

TO-DECIMAL

J, N

SN74L154

J,W

EXCESS-3-TO-D ECI MA L
EXCESS-3-GRAY-

SN74154

SN54159

4-LINE-TO-10-L1NE,
4-LINE-TO-10-LINE

O°C to 70·C

-55°C to 125°C
SN54154

PAGE
NO.

J,W' SN7443A

N
N
N
N

7·15

N
N

7-15

SN74L43

J, N

J,W

SN7444A

J

SN74L44

J, N
J, N

7-15

SN54S138

J,W

SN74S138

J, N

7-134

SN54LS138

J,W

SN74LS138

J, N

7-134

SN54S139

J,W

SN74S139

J, N

7-134

Totem-Pole

8 ns

7 ns

245mW

Totem-Pole

22 ns

21 ns

31 mW

Totem-Pole

7.5 ns

6 ns

300mW

Totem-Pole

22 ns

19 ns

34mW

SN54LS139

J,W

SN74LS139

J, N

7-134

Totem-Pole

18 ns

15 ns

30mW

SN54LS155

J,W

SN74LS155

J, N

7-175

Totem-Pole

21 ns

16 ns

125mW

SN54155

J,W

SN74155

J, N

7-175

Open-Collector

23 ns

18 ns

125mW

SN54156

J,W

SN74156

J,N

7-175

Open-Collector

33 ns

26 ns

31 mW

SN54LS156

J,W

SN74LS156

J, N

7-175

•

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS WITH COUNTERS/LATCHES

DESCRIPTION

OUTPUT

OFF-STATE

TYPTOTAL

SINK

OUTPUT

POWER

DEVICE TYPE

CURRENT

VOLTAGE

DISSIPATION

55V

340mW

7V

280mW

Ripple

SN54143

J,W

20mA

15V

280mW

Ripple

SN54144

J,W

25mA

15V

280mW

Ripple

BLANKING

PAGE

AND PACKAGE
-55°C to 125°C

O°C to 70°C

NO.

BCD COUNTER/
4-BIT LATCH!

7mA

BCD-TO-DECIMAL

SN74142

J, N

7-140

SN74143

J, N

7-143

SN74144

J, N

DECODER!DRIVER
BCD COUNTER!
4-BIT LATCH!

Constant
Current

BCD-TO-SEVENSEGMENT DECODE~!

15mA

LED DRIVER
BCD COUNTER!
4-BIT LATCH!
BCD-TO-SEVENSEGMENT DECODER!

7-143

LAMP DRIVER

RESULTANT DISPLAYS USING '143, '144

o

2

3

4

5.

6

8

9

)76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

1-23

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS

DESCRIPTION

BCD-TO-DECIMAL

•

DECODERS/DRIVERS

OUTPUT

OFF-STATE

TYPTOTAL

SINK

OUTPUT

POWER

CURRENT

VOLTAGE

DISSIPATION

80mA

30V

21SmW

80mA

15V

35mW

12mA

15V

35mW

80mA

15V

215mW

DEVICE TYPE
BLANKING

AND PACKAGE
-SSoC to 12SoC
O°C to 70°C

Invalid Codes SN5445

J,W

Invalid Codes
Invalid Codes SN54LS145

J,W

Invlaid Codes SN54145

J,W

PAGE
NO_

SN7445

J, N

SN74LS145

J, N

7-20
7-148

SN74145

J, N

7-148
7-138

7-148

7mA

60V

80mW

Invalid Codes

SN74141

J, N

40mA

30V

320mW

Ripple

SN5446A

J,W

SN7446A

J, N

7-22

40mA

30V

320mW

Ripple

SN54246

J,W

SN74246

J, N

40mA

15V

320mW

Ripple

SN5447A

J,W

SN7447A

J, N

7-22
7-22

40mA

15V

320mW

Ripple

SN54247

J,W

SN74247

J, N

7-351

24mA

15V

35mW

Ripple

SN74LS47

J, N

7-22

24 mA

15V

35mW

Ripple

SN74LS247

J, N

7-351

12mA

15V

35mW

Ripple

SN54LS47

J,W

7-22

12mA

15V

35mW

Ripple

SN54LS247

J,W

7-351

20mA

30V

133mW

Ripple

SN54L46

J

SN74L46

J, N

BCD-TO-

20mA

15V

133mW

Ripple

SN54L47

J

SN74L47

J, N

SEVEN-SEGMENT

6.4 mA
6.4 mA

5.5V

265mW

Ripple

SN5448

J,W

SN7448

J, N

7-22

5.5V

265mW

Ripple

SN54248

J,W

SN74248

J, N

7-351

6mA

5.5V

125mW

Ripple

SN74LS48

J, N

7-22

6mA

5.5V

125mW

Ripple

SN74LS248

J, N

7-351

2mA

5.5V

125mW

Ripple

SN54LS48

J,W

7-22

2mA

5.5V

125mW

Ripple

SN54LS248

J,W

7-351

DECODERS/DRIVERS

7-22
7-22

7-22

10mA

5.5V

165mW

Direct

SN5449

10 mA

S.5V

265mW

Direct

SN54249

W

8mA

5.SV

40mW

8mA

40mW

4mA

5..sV
S.SV

40mW

Direct

SN54LS49

J,W

7-22

4~A

.5.5 V

40mW

Direct

SN54LS249

J,W

7-351

SN74249

J, N

7-351

Direct

SN74LS249

J, N

7-351

Direct

SN74LS49

J, N

J,W

7-22

RESULTANT DISPLAYS USING '46A, '47A, '48, '49, 'L46, 'L47, 'LS47, 'LS48, 'LS49

RESULTANT DISPLAYS USING '246, '247, '248, '249, 'LS247, 'LS248, 'LS249

10

1-24

TEXAS INCORPORATED
INSTRUMENTS
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•

DALLAS. TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
BUS TRANSCEIVERS AND DRIVERS
TYPICAL
DESCRIPTION

MAXIMUM MAXIMUM

PROPAGATION

SOURCE

SINK

DELAY TIMES

CURRENT

CURRENT

DEVICE TYPE

PAGE

AND PACKAGE
-55°C to 125°C

NO.

O°C to 70°C

CONTROLLER AND BUS DRIVER

-lmA

10mA

SN74S428

N

FOR 8080A SYSTEMS

-lmA

10mA

SN74S438

N

J

SN74LS245

J, N

7-349

J,W

SN74S226

J, N

7-345

OCTAL BUS T-RANSCEIVERS
4-BIT BUS TRANSCEIVERS
WITH STORAGE

8 ns

-12mA

12mA

SN54LS245

10 ns

-6.5 mA

20mA

SN54S226

7-514

ASYNCHRONOUS COUNTERS (RIPPLE CLOCK)-NEGATIVE-EDGE TRIGGERED

DESCRIPTION

DECADE

DUAL 4·BIT BINARY

PAGE

LqAD

50 MHz

Yes

Low

240mW

SN54196

J,W

SN74196

J, N

100 MHz

Yes

Low

375mW

SN54S196

J,W

SN74S196

J, N

7-331

35 MHz

Yes

Low

150mW

SN54176

J,W

SN74176

J, N

7-259

32 MHz

Set-to-9

High

40mW

SN54LS90

J,W

SN74LS90

J, N

7-72

32 MHz

Set·to-9

High

40mW

SN54LS290

J,W

SN74LS290

J, N

7423

32 MHz

Set-to-9

High

160mW

SN5490A

J,W

SN7490A

J, N

7-72

32 MHz

Set-to-9

High

160mW

SN54290

J,W

SN74290

J, N

7423
7-331

CLEAR

DISSIPATION

-55°C to 125°e

0

oOe to 70 e

NO.

Yes

Low

60mW

SN54LS196

J,W

SN74LS196

J, N

High

20mW

SN54L90

J, T

SN74L90

J, N

7-72

50 MHz

Yes

Low

240mW

SN54197

J,W

SN74197

J, N

7-331

100 MHz

Yes

Low

375mW

SN54S197

J,W

SN74S197

J, N

7-331

35 MHz

Yes

Low

150mW

SN54177

J,W

SN74177

J, N

7-259

32 MHz

None

High

39mW

SN54LS93

J,W

SN74LS93

J, N

7-72

32 MHz

None

High

39mW

SN54LS293

J,W

SN74LS293

J, N

7423

32 MHz

None

High

160mW

SN5493A

J,W

SN7493A

J, N

7-72

32 MHz

None

High

160mW

SN54293

J,W

SN74293

J, N

7423
7-331

Yes

Low

60mW

SN54LS197

J,W

SN74LS197

J, N

3 MHz

None

High

20mW

SN54L93

J, T

SN74L93

J, N

32 MHz

None

High

39mW

SN54LS92

J,W

SN74LS92

J, N
J, N

7-72
7-72

32 MHz

None

High

160mW

SN5492A

J,W

SN7492A

25 MHz

None

High

210mW

SN54390

J,W

SN74390

J, N

7489

35 MHz

None

High

75mW

SN54LS390

J,W

SN74LS390

J, N

7489

25 MHz

Set-to-9

High

225mW

35 MHz

Set-to-9

High

75mW

25 MHz

None

High

190mW

35 MHz

None

High

75mW

•

7-331

Set-to-9

30MHz

DUAL DECADE

AND PACKAGE

FREQ

3MHz

DIVIDE-BY-12

DEVICE TYPE

POWER

PARALLEL

30 MHz

4-BIT BINARY

TYP TOTAL

COUNT

SN54490

J,W

SN74490

J, N

7·520

SN54LS490

J,W

SN74LS490

J, N

7-520

SN54393

J,W

SN74393

J, N

7489

SN54LS393

J,W

SN74LS393

J, N

7489

77

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

1-25

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
SYNCHRONOUS COUNTERS-POSITIVE-EDGE TRIGGERED

DESCRIPTION

DECADE

•

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

COUNT

PARALLEL

FREQ

LOAD

40MHz

Sync

Sync-L

475mW

25 MHz

Sync

Sync-L

25 MHz

Sync

25 MHz

Sync

Async-L
Sync-L

305mW

CLEAR

DISSIPATION

-55°C to 125°C

PAGE
NO_

O°C to 70°C

SN54S162

J,W

SN74S162

J, N

93mW

SN54LS162A

J,W

SN74LS162A

J, N

93mW

SN54LS160A

J,W

SN74LS160A

J, N

SN54162

J,W

SN74162

J, N

7-190

25 MHz

Sync

Async-L

305mW

SN54160

J,W

SN74160

J N

40 MHz

Sync

None

500mW

SN54S168

J,W

SN74S168

J, N

7-226

25 MHz

Async

Async-H

85mW

SN54LS192

J,W

SN74LS192

J, N

7-306

DECADE

25 MHz

Async

Async-H

325mW

SN54192

J,W

SN74192

J, N

7-306

UP/DOWN

20 MHz

Async

None

100mW

SN54LS190

J,W

SN74LS190

J, N

7-296

20 MHz

Async

None

325 mW

SN54190

J,W

SN74190

J, N

7-296

3 MHz

Async

Async-H

42mW

SN74L192

J, N

7-306

25 MHz

Set-to-9

Async-H

270mW

SN54167

J,W

SN74167

J, N

7-222

40 MHz

Sync

Sync-L

475mW

SN54S163

J,W

SN74S163

J, N

25 MHz

Sync

Sync-L

93mW

SN54LS163A

J,W

SN74LS163A

J, N

25 MHz

Sync

Async-L

93mW

SN54LS161A

J,W

SN74LS161A

J, N

25 MHz

Sync

Sync-L

305mW

SN54163

J,W

SN74163

J, N
J, N

DECADE

1
RATE MULTIPLlER,N;O"

4-BIT BINARY

4-BIT BINARY
UP/DOWN

6-BIT BINARY

1
RATE MULTIPLlER,N2

SN54L192

J

7-190

25 MHz

Sync

Async-L

305 mW

SN54161

J,W

SN74161

40 MHz

Sync

None

500mW

SN54S169

J,W

SN74S169

J, N

7-226

25 MHz

Sync

None

100mW

SN54LS169A

J,W

SN74LS169A

J, N

7-226
7-306

25 MHz

Async

Async-H

85mW

25 MHz

Async

Async-H

325mW

20 MHz

Async

None

90mW

20 MHz

Async

None

325mW

3 MHz

Async

Async-H

42mW

Async-H

345 mW

25 MHz

SN54LS193

J,W

SN74LS193

J, N

SN54193

J,W

SN74193

J, N

7-300

SN54LS191

J,W

SN74LS191

J, N

7-296

SN54191

J,W

SN54L193

J

SN5497

J,W

SN74191

J, N

7-296

SN74L193

J, N

7-306

SN7497

J, N

7-102

BIPOLAR BIT-SLICE PROCESSOR ELEMENTSt
CASCADABLE
DESCRIPTION

4-BIT SLICE

TO

TYPICAL
",-OPERATION

N-BITS

TIME

Yes

100 ns
120 ns

Yes

DEVICE TYPE
TECHNOLOGY

AND PACKAGE
_55°C to 125°C

STTL
STTL

I

O°C to 70°C

I~N74S481
I

SN74LS481

IJ, N
J, N

FIRST-IN FIRST-OUT MEMORIES (FIFO'Slt

DESCRIPTION
ASYNCHRONOUS 16 X 5

TYPE

DELAY TIME

TYP TOTAL

DEVICE TYPE

OF

FROM

POWER

AND PACKAGE

OUTPUT

CLOCK

DISSIPATION

_55°C to 125°C 10°C to 70°C

3-State

50 ns

400mW

1 I

SN74S225

I

J

tSee Bipolar Microcomputer Components Data Book, LCC4440_

18

1-26

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
RANDOM-ACCESS READ-WRITE MEMORIES (RAM'SI

DESCRIPTION

256-BIT ARRAYS

ORGANIZATION

TYPE

TYPICAL TYPICAL

OF

TYP POWER

DEVICE TYPE

ADDRESS ENABLE DISSIPATION

PAGE

AND PACKAGE

OUTPUT

TIME

TIME

256 X 1

3-State

42 ns

17 ns

1.9mW

SN54S201

J,W

SN74S201

256 Xl

O-C

42 ns

13 ns

1.9mW

SN54S301

J,W

SN74S301

64-BIT ARRAYS

16-BIT ARRAYS
16-BIT MULTIPLE-PORT
REGISTER FILE
16-BIT REGISTER FILE

PER BIT

_55°C to 125°C

O°C to 70°C
J, N
J, N

NO_
t
t

16X4

3-State

25 ns

12 ns

5.9 mW

SN54S189

J,W

SN74S189

J. N

t

16X4

O-C

25 ns

12 ns

5.9mW

SN54S289

J,W

SN74S289

J, N

t

16X4

O-C

32 ns

30 ns

5.9mW

SN7489

J, N

t

16 X 1

O-C

15 ns

15 ns

14mW

SN5481A

J,W

SN7481A

J. N

t

16X 1

O-C

15 ns

15 ns

14mW

SN5484A

J,W

SN7484A

J N

t

8X2

3-State

33 ns

15 ns

35mW

SN74172

J, N

7-245

4X4

O-C

27 ns

15 ns

7.8 mW

SN54LS170

J,W

SN74LS170

J. N

7-237

4X4

O-C

30 ns

15 ns

40mW

SN54170

J,W

SN74170

J. N

7-237

4X4

3-State

24 ns

19 ns

9.3mW

SN54LS670

J,W

SN74LS670

J, N

7-526

a

READ-ONLY MEMORIES (ROM'slt

DESCRIPTION

ORGANIZATION
512 X4

2048-BIT ARRAYS

TYPE
OF

TYPICAL TYPICAL

TYP POWER

ADDRESS ENABLE DISSIPATION

DEVICE TYPE
AND PACKAGE

OUTPUT

TIME

TIME

PER BIT

_55°C to 125°C

O-C

45 ns

15 ns

0.26 mW

SN54S270

O°C to 70°C

J

SN74S270 J, N

256 X 8

O-C

45 ns

15 ns

0.26 mW

SN54S271

J

SN74S271

512X4

3-State

45 ns

15 ns

0.26 mW

SN54S370

J

SN74S370 J. N
SN74S371 J. N

J, N

256 X 8

3-State

45 ns

15 ns

0.26 mW

SN54S371

1024-BIT ARRAYS

256 X 4

O-C

40 ns

20 ns

0.46 mW

SN54187

J.W SN74187

J. N

256-BIT ARRAYS

32 X 8

O-C

26 ns

22 ns

1.1mW

SN5488A

J,W SN7488A

J, N

J

tFor more information contact the factory.

181

TEXAS (NSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

1·27

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PROGRAMMABLE READ-ONLY MEMORIES (PROM'slt

DESCRIPTION

ORGANIZATION
512 X 8

4096-BIT ARRAYS

204B-BIT ARRAYS

II

1024-BIT ARRAYS
512-BIT ARRAYS
256-BIT ARRAYS

TYPE
OF

TYPICAL TYPICAL

TYP POWER

DEVICE TYPE

ADDRESS ENABLE DISSIPATION

AND PACKAGE

OUTPUT

TIME

TIME

PER BIT

-55°C to 125°C

3-State

55 ns

20 ns

0_14mW

SN54S472

J

SN74S472 J, N

J

SN74S473 J, N

O°C to 70°C

512 X 8

O-C

55 ns

20 ns

0.14mW

SN54S473

512 X 8

3-State

55 ns

20 ns

0.14mW

SN54S474 J,W SN74S474 J, N

512 X 8

O-C

55 ns

20 ns

0.14mW

SN54S475 J,W SN74S475 J, N

256 X 8

O-C

50 ns

20 ns

0.24mW

SN54S470

J

SN74S470 J, N

256 X 8

3-State

50 ns

20 ns

0.27 mW

SN54S471

J

SN74S471

256 X 4

3-State

40 ns

15 ns

0.49 mW

SN54S287 J,W SN74S287 J, N

256 X4

O-C

40 ns

15 ns

0.49 mW

SN54S387 J,W SN74S387 J, N

64 X 8

O-C

50 ns

47 ns

0.6mW

SN54186

32 X8

O-C

29 ns

28 ns

1_3mW

SN54188A J,W SN74188A J, N

32 X 8

O-C

25 ns

12 ns

1.56mW

SN54S188 J,W SN74S188 J, N

32 X 8

3-State

25 ns

12 ns

1.56mW

SN54S288 J,W SN74S288 J, N

J, N

J, N

J,W SN74186

MICROPROCESSOR CONTROI.LERS AND SUPPORT FUNCTIONS
SYSTEM

DESCRIPTION

APPLICATION

SYSTEM CONTROLLERS
REGISTERS
MULTI-MODE LATCHES

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

DISSIPATION

_55°C to 125°C

PAGE
NO_

O°C to 70°C

8080A

700mW

SN74S428 (TIM82281

N

7-514

8080A

700mW

SN74S438 (TIM82381

N

7-514

Universal

450mW

SN54S482

TMS 9900

110mW

SN54LS259

J

SN74S482

J, N

t

J,W

SN74LS259 (TIM99061

J, N

7-376

410mW

SN54S412

J,W

SN74S412 (TIM82121

J, N

7-502

TRANSCEIVERS AND

625mW

SN54S226

J,W

SN74S226

J, N

7-345

BUS DRIVERS

207mW

SN54LS245

J

SN74LS245

J, N

7-349

98mW

SN54LS240

J

SN74LS240

J, N

6-83

450mW

SN54S240

J

SN74S240

J, N

6-83

100mW

SN54LS241

J

SN74LS241

J, N

6-83

538mW

SN54S241

J

SN74S241

J, N

6-83

128mW

SN54LS242

J,W

SN74LS242

J, N

6-87

128mW

SN54LS243

J,W

SN74LS243

J, N

6-87

100mW

SN54LS244

J

190mW

SN54148

8080A

TRANSCEIVERS AND
BUS DRIVERS (SSI)

TMS9900
LOGIC ELEMENTS

SN74 LS244

J, N

6-83

J,W

SN74148 (TIM99071

J, N

7-151

TMS 9900

35mW

SN54LS251

J,W

SN74LS251 (TIM99051

J, N

7-362

TMS9900

63mW

SN54LS348

J,W

SN74LS348 (TIM99081

J, N

7-448

ERROR DETECTION AND CORRECTION CIRCUITS
DEVICE TYPE
AND PACKAGE

TYPE
OF
OUTPUTS

MEMORY
OVERHEAD

FLAGGED

ERRORS
CORRECTED

16-BIT PARALLEL

3-STATE

6 BITS

2-BIT

1-BIT

SN54LS630

J

SN74LS630

N.J

7465

16-BIT PARALLEL

O-C

6 BITS

2-BIT

1-BIT

SN54LS631

J

SN74LS631

N.J

7465

DESCRIPTION

ERRORS

-55°C to 125°C

PAGE
NO.

O°Cto 70°C

tSee Bipolar Microcomputer Components Data Book, LCC4440.

181

1-28

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

•
Interchangeability
Guide

2·1

TTL INTERCHANGEABILITY GUIDE
Direct Replacements were selected as pin-for-pin equivalent circuits based on similarity of electrical and mechanical
characteristics as sho'wn in currently published data_ Interchangability in any particular application is not necessarily
guaranteed_ Before using a substitute, the user should compare the specifications of the substitute device with the
detailed specifications of the original device.
TI makes no warranty as to the information furnished and buyer assumes all risk in the use thereof. No liability is
assumed for damages resulting from the use of the information contained in this list.

•

Recommendation for New Designs lists devices performing a similar (sometimes identical) function. Most are
pin-for-pin equivalents for the competitor's part. However, the recommended part may have different pin-outs or
organizations, as later technologies are listed in some cases to ensure that current high-performance components are
recommended .
Only the basic circuit numbers are cross referenced. As the pin-out sometimes varies between a flat-package part and
the equivalent DIP part, it is recommended that the manufacturer's specifications be consulted prior to specifying a
direct replacement. Other than parts offered only in a flat package, the dual-in-line pin-outs were used as a guide in
preparing the following cross references.
This list is intended to give TI replacements for competitors' parts not using the 54/74 numbering system. For a
complete listing of P:lrts in the 54 and 74 families, see the functional index, pages 1-9 through 1-28.

ADVANCED MICRO DEVICES
Example of AMD ordering code:
AM

2700

A

59

Iprlfix I
AMD

TI DIRECT

RECOMMENDED

AMD

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGN

TYPE

REPLACEMENT

FOR NEW DESIGN

2501
2505

27S09

'sN54S288/SN74S288

27S10

SN54S387/SN74S387

SN54S288/SN74S288
SN54S387/SN74S387

SN54285/SN74285

27S11

SN54S287/SN74S287

SN 54S287 /S N74S287
SN7489

SN54S181/SN74S181

3101

SN7489

25LS07

SN 54 LS378/SN74 LS378

SN54LS378/SN74 LS378

3101A

SN54S289/SN74S289

SN54S289 /SN 74S289

25LS08

SN54LS379/SN74LS379

SN54LS379/SN74LS379

9300

SN54195/SN74195

SN54195/SN74195

25LS09

SN54LS399/SN74LS399

SN54LS399/SN74LS399

9301

SN29301/SN39301

SN5442A/SN7442A

25LS22

SN54 LS322/SN 74 LS322

SN54LS322/SN74LS322

930S

SN2930S/SN39308

SN54116/SN74116

25LS23

SN54LS323/SN74LS323

2506

SN54LS323/SN74LS323

9309

SN29309/SN39309

SN54153/SN74153

2600

SN54121/SN74121

9310

SN54160/SN74160

SN54160/SN74160

2602

SN54123/SN74123

9311

SN54154/SN74154

SN54154/SN74154

SN54123/SN74123

9312

SN29312/SN39312

SN54151A/SN74151A

SN54S200A/SN74S200A

SN54S200A/SN74S200A

9316

SN54161/SN74161

SN54161/SN74161

SN54S201/SN74S201

SN54S201/SN74S201

9318

SN54148/SN74148

SN54148/SN74148
SN54157/SN74167

26123
2700
27LSOO
2701

2-2

SN54192/SN74191
SN54284/SN74284

SN54123/SN74123

SN54 LS200A/SN 74LS200A

SN54 LS200A/SN7 4 LS200A

9322

SN54157/SN74157

SN54S300A/SN74S300A

SN 54S300A/S N 74S300A

9334

SN54259/SN74259

SN54259/SN74259

SN54S301/SN74S301

SN54S301/SN74S301

9341

SN54181/SN74181

SN54181/SN74181
SN54182/SN74182

27S02

SN 54S289 /S N7 4S289

SN54S289/SN74S289

9342

SN54182/SN74182

27S03

SN54S189/SN74S189

SN54S189/SN74S189

9601

SN29601

27S08

SN54S188/SN74S188

SN54S188/SN74S188

93415

SN54S314/SN74S314

SN54S314/SN74S314

FAIRCHILD
Example of order code:
9310

D

C

Package

= C-DIP
F = Flat Pack
P = Plastic DIP
D

FSC

TI DIRECT

RECDMMENDED

FSC

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGN

TYPE

REPLACEMENT

FOR NEW DESIGN

9000

SN29000

SN54276/SN74276

9014

9HOO

SN54HOO/SN74HOO

SN54S00/SN74S00

9N14

SN54S135/SN74S135

9LOO

SN54LSOO/SN74LSOO

SN54LSOO/SN74LSOO

9015

9NOO

SN5400/SN7400

SN5400/SN7400

9S15

9S00

SN54S00/SN74S00

SN54S00/SN74S00

9016

SN29016/SN7404, SN5404

SN54S240/SN74S240

SN54276/SN74276

9N16

SN5416/SN7416

SN5416/SN7416

SN54376/SN74376

9017

SN5405/SN7405

SN54S241/SN74S241

SN54171SN7417

SN5417/SN7417

SN5414/SN7414

SN5414/SN7414

SN54S15/SN74S15

SN54S15/SN74S15

SN5402/SN7402

9001

SN29001

9HOl

SN54H01/SN74HOl

SN54S03/SN74S03

9N17

9NOl

SN5401/SN7401

SN5403/SN7403

9020

9002

SN29002/SN7400, SN5400

SN5400/SN7400

9H20

SN54H20/SN74H20

SN54S20/SN74S20

9N02

SN5402/SN7402

SN5402/SN7402

9N20

SN5420/SN7420

SN5420/SN7420

9S02

SN54S02/SN74S02

SN54S02/SN74S02

9S20

SN54S20/SN74S20

SN54S20/SN74S20

9003

SN29003/SN7410, SN5410

SN5410/SN7410

9H21

SN54H21/SN74H21

SN54S15/SN74S15

9N03

SN5403/SN7403

SN5403/SN7403

9022

9S03

SN54S03/SN74S03

SN 54S03/S N 74S03

9H22

SN54H22/SN74H22

SN54S22/SN74S22

90,04

SN29004/SN7420, SN5420

SN5420/SN7420

9S22

SN54S22/SN74S22

SN54S22/SN74S22

9N23

SN5423/SN7423

•

SN74276

SN74376

9H04

SN54H04/SN74H04

SN54S04/SN74S04

9L04

SN54LS04/SN74LS04

SN54LS04/SN74LS04

9N04

SN5404/SN7404

SN5404/SN7404

9024

SN29024/SN741 09, SN541 09

9S04

SN54S04/SN74S04

SN54S04/SN74S04

9L24

SN54LS109A/SN74LS109A

9005

SN29005/SN7450, SN5450

SN5450/SN7450

9N25

SN5425/SN7425

SN54LSl 09A/SN74LS1. 09A
SN5425/SN7425

9H05

SN54S05/SN74S05

SN54S05/SN74S05

9N26

SN5426/SN7426

SN5426/SN7426

9S05

SN54S05/SN74S05

SN54S05/SN74S05

9N27

SN5427/SN7427

SN5427/SN7427

9006

SN5460/SN7460

SN5460/SN7460

9H30

SN54H30/SN74H30

SN54S30/SN74S30

9N06

SN5406/SN7406

SN5406/SN7406

9N30

SN5430/SN7430

SN5430/SN7430

9007

SN29007

SN54S133/SN74S133

9S30

SN54S30/SN74S30

SN54S30/SN74S30

9N07

SN5407/SN7407

SN5407/SN7407

9N32

SN5432/SN7432

SN5432/SN7432

9008

SN29008

SN54S65/SN74S65

9S32

SN54S32/SN74S32

SN54S32/SN74S32

9N08

SN5408/SN7408

SN5408/SN7408

9033

SN83433, SN93433

SN54S189/SN74S189

9S08

SN54S08/SN74S08

SN54S08/SN74S08

9034

SN5488A/SN7488A

SN54S371/SN74S371

9009

SN29009/SN7440, SN5440

SN54S140/SN74S140

9N37

SN5437/SN7437

SN5437/SN7437

9N09

SN5409/SN7409

SN5409/SN7409

9N38

SN5438/SN7438

SN5438/SN7438

9S09

SN54S09/SN74S09

SN54S09/SN74S09

9H40

SN54H40/SN74H40

SN54S40/SN74S40

9Hl0

SN54H 10/SN74H 10

SN54S1 0/SN74S1 0

9N40

SN5440/SN7440

SN5440/SN7440

9Nl0

SN5410/SN7410

SN5410/SN7410

9S40

SN54S40/SN74S40

SN54S40/SN74S40

9S10

SN54S1 0/SN74S1 0

SN54S10/SN74S10

9H50

SN54H50/SN74H50

SN54S51/SN74S51

9Hll

SN54Hll/SN74Hll

SN54S11/SN74S11

9N50

SN5450/SN7450

SN5450/SN7450

9S11

SN54S11/SN74S11

SN54S11/SN74S11

9H51

SN54H51/SN74H51

SN54S51/SN74S51

9012

SN2901 /SN7403, SN5403

SN5403/SN7403

9N51

SN5451/SN7451

SN5451/SN7451

9N12

SN5412/SN7412

SN5412/SN7412

9S51

SN54S51/SN74S51

SN54S51/SN74S51

9N13

SN5413/SN7413

SN5413/SN7413

9H52

SN54H52/SN74H52

SN54S51/SN74S51

SN5423/SN7423
SN54276/SN74276
SN54376/SN74376

H7

2·3

FAIRCHILD

II

FSC

TI DIRECT

RECOMMENDED

FSC

TI DIRECT

RECOMMENDED

~

REPLACEMENT

FOR NEW DESIGN

TYPE

REPLACEMENT

FOR NEW DESIGN

SN54H53/SN74H53

SN54H53/SN74H53

93LOO

SN54LS195A/SN 74 LS195A

9N53

SN5453/SN7453

SN5453/SN7453

93S00

SN54S195/SN74S195

SN54S195/SN74S195

9H54

SN54H54/SN74H54

SN54H54/SN74H54

9301

SN39301/SN29301

SN5442A/SN7442A

9L54

SN54L54/SN74L54

SN54LS54/SN74LS54

93L01

9N54

SN5454/SN7454

SN5454/SN7454

9302

SN5442A/SN7442A

9H55

SN54H55/SN74H55

SN54S65/SN74S65

9304

SN54H 183/SN74H 183

9H60

SN54H60/SN74H60

SN54S11/SN74S11

9305

SN54S169/SN74S169

9N60

SN5460/SN7460

SN5460/SN7460

93S05

9H61

SN54H61/SN74H61

SN54S11/SN74S11

9307

SN54L42/SN74 L42

SN54S169/SN74S169
SN5448A/SN7448A

SN54H62/SN74H62

SN54H62/SN74H62

9S64

SN54S64/SN74S64

SN54S64/SN74S64

9S65

SN54S65/SN74S65

SN54S65/SN74S65

9309

9N70

SN5470/SN7470

SN54 70/SN74 70

93L09

9H71

SN54H71/SN74H71

SN54S112/SN74S112

9H72

SN54H72/SN74H72

SN54S112/SN74S112

9N72

SN5472/SN7472

SN5472/SN7472

9H73

SN54H73/SN74H73

SN54S113/SN74S113

9N73

SN5473/SN7473

SN5473/SN7473

9H74

SN54H74/SN74H74

SN54S74/SN74S74

93L11

SN54L 154/SN74L 154

SN54L 154/SN74L 154

9N74

SN5474/SN7474

SN5474/SN7474

9312

SN39312/SN29312

SN54151 A/SN74151 A

9S74

SN54S74/SN74S74

SN54S74/SN74S74

93S12

SN54S151/SN74S151

9N75

SN5475/SN7475

SN5475/SN7475

9313

SN54251/SN74251

9H76

SN54H76/SN74H76

SN54S112/SN74S112

9314

SN54273/SN74273

9N76

SN5476/SN7476

SN5476/SN7476

93L14

9H78

SN54H78/SN74H78

SN54S114/SN74S114

9315

9L86

SN54L86/SN74L86

SN54LS86/SN74LS86

9N86

SN5486/SN7486

SN5486/SN7486

9S86

SN54S86/SN74S86

SN54S86/SN74S86

93S1'6

9H101

SN54H101/SN74H101

SN54S112/SN74S112

93178

9H102

SN54H102/SN74H102

SN54S112/SN74S112

9317C

9H103

SN54H 103/SN74H 103

SN54S113/SN74S113

9H106

SN54H106/SN76H106

SN54S112/SN74S112

9H107

SN541 07/SN741 07

SN54107/SN74107

93L21

SN54LS139/SN74LS139

9N107

SN54107/SN74107

SN54107/SN74107

9321

SN54S139/SN74S139

9H108

SN54H1 08/SN74H 108

SN54S114/SN74S114

9308

9310

SN39308/SN54116

SN5448A/SN7448A

9H62

SN29308/SN74116
SN39309/SN29309

SN29310/SN74160

9316

9318

9322

SN39311/SN54154
SN29311/SN74154

SN39316/SN54161
SN29316/SN74161

SN5446A/SN7446A
SN39318/SN54148
SN29318/SN74148

SN39322/SN54157

SN54S112/SN74S112

SN54S113/SN74S113

SN54S113/SN74S113

93L22

SN54L 157/SN74L 157

9S114

SN54S114/SN74S114

SN54S114/SN74S114

93S22

SN54S157/SN74S157

9N122

SN54122/SN74122

SN54122/SN74122

9324

SN54123/SN74123

SN54123/SN74123

93L24

SN54132/SN74132

SN54132/SN74132

9325

9S132

SN54S132/SN74S132

SN54S132/SN74S132

9328

SN74141
SN54S163/SN74S163
SN54S163/SN74S163

SN5446A!SN7446A

SN54S112/SN74S112

9N123

SN54154/SN74154

SN54L75/SN74L75
SN54141

9S112

9N132

SN54S162/SN74S162
SN54S162/SN74S162

93S10
9311

SN54116/SN74116
SN54153/SN74153
SN54L 153/SN74L 153

SN39310/SN54160

9S113

SN29322/SN74157

SN5446A/SN7446A
SN5446A/SN7446A
SN54148/SN74148
SN54LS139/SN74LS139
SN54S139/SN74S139
SN54157/SN74157
SN54L157/SN74L 157
SN54S157/SN74S157
SN54S85/SN74S85
SN54L85/SN74L85

SN74141

SN74141
SN5491 AlSN7491 A

9S133

SN54S133/SN74S133

SN94S133/SN74S133

93L28

9S134

SN54S134/SN74S 134

SN54S134/SN74S134

9334

9S135

SN54S135/SN74S135

SN54S135/SN74S135

9338

9S140

SN54S140/SN74S140

SN54S140/SN74S140

9340

SN54S281/SN74S281

9N279

SN54279/SN74279

SN54279/SN74279

93L40

SN54LS181/SN74LS181

9300
93HOO

2·4

SN54LS195A/SN74LS195A

9H53

SN39300/SN54195
SN29300/SN74195
SN54S195/SN74S195

SN54S299/SN74S299
SN54S195/SN74S195

SN54L91/SN74L91
SN54259/SN74259

SN54259/SN74259
SN74172

9341

SN54181/SN74181

SN54S181/SN74S181

93S41

SN54S181/SN74S181

SN54S181/SN74S181

9342

SN54182/SN74182

SN54S182/SN74S182

FAIRCHILD
FSC

TI DIR ECT

RECOMMENDED

FSC

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGN

TYPE

REPLACEMENT

FOR NEW DESIGN

SN54S182/SN74S182

93155

SN54155/SN74155

SN54155/SN74155

93543

SN74S274

93156

SN54156/SN74156

SN54156/SN74156

9344

SN74S274

93157

SN54157/SN74157

SN54157/SN74157

SN5445/SN7445

93S157

SN54S157/SN74S157

SN54S157/SN74S157

93S46

SN54S85/SN74S85

93S158

SN54S158/SN74S158

SN54S158/SN74S158

93547

SN54S85/SN74S85

93160

SN54160/SN74160

SN54160/SN74160

9348

SN54S280/SN74S280

93161

SN54161/SN74161

SN54161/SN74161

93S42

9345

SN54S182/SN74S182

SN5445/SN7445

9349

SN54180/SN74180

SN54180/SN74180

93162

SN54162/SN74162

SN54162/SN74162

9350

SN54290/SN74290

SN54290/SN74290

93163

SN54163/SN74163

SN54163/SN74163

9352

SN5442A/SN7442A

SN5442A/SN7442A

93164

SN54164/SN74164

SN54164/SN74164

9353

SN5443A/SN7443A

SN5443A/SN7443A

93165

SN54165/SN74165

SN54165/SN74165

9354

SN5444A/SN7444A

SN5444A/SN7444A

93166

SN54166/SN74166

SN54166/SN74166

9356

SN54293/SN74293

SN54293/SN74293

93170

SN54170/SN74170

SN54170/SN74170

9357 A

SN5446A/SN7446A

SN5446A/SN7446A

93174

SN54174/SN74174

SN54174/SN74174

93578

SN5447A/SN7447A

SN5447A/SN7447A

93175

SN54175/SN74175

SN54175/SN74175

9358

SN5448/SN7448

SN5448/SN7448

93S175

SN54S175/SN74S175

SN54S175/SN74S175

9359

SN5449/SN7449

SN5449/SN7449

93176

SN54176/SN74176

SN54176/SN74176

9360

SN54192/SN74192

93S62

SN54192/SN74192

93177

SN54177/SN74177

SN54177/SN74177

SN54S280/SN74S280

93178

SN54178/SN74178

SN54178/SN74178

SN54193/SN74193

93179

SN54179/SN74179

SN54179/SN74179

9368C

SN54143/SN74143

93180

SN54180/SN74180

SN54180/SN74180

9370C

SN54144/SN74144

93H183

SN54H183/SN74H183

SN54H183/SN7~H183

93H72

SN54S194/SN74S194

93190

SN54190/SN74190

SN54190/SN74190

9374C

SN54143/SN74143

93191

SN54191/SN74191

SN54191/SN74191

9366

SN54193/SN74193

•

9375

SN5475/SN7475

SN54175/SN74175

93194

SN54194/SN74194

SN54194/SN74194

9377

SN5477/SN7477

SN54175/SN74175

93S194

SN54S194/SN74S194

SN54S194/SN74S194

9380

SN5480/SN7480

SN5480/SN7480

93195

SN54195/SN74195

SN54195/SN74195

9382

SN5482/SN7482

SN 5482/S N 7482

93196

SN54196/SN74196

SN54196/SN74196

9383

SN5483A/SN7483A

SN54283/SN74283

93197

SN54197/SN74197

SN54197/SN74197

9386

SN54LS266/SN74LS266

SN54LS266/SN74LS266

93198

SN54198/SN74198

SN54198/SN74198

93H87

SN54H87/SN74H87

SN54H87/SN74H87

93199

SN54199/SN74199

SN54199/SN74199

9390

SN5490A/SN7490A

SN54290/SN74290

93S251

SN54S251/SN74S251

SN54S251/SN74S251

9391

SN5491 A/SN7491 A

SN5491 A/SN7491 A

93S257

SN54S257/SN74S257

SN54S257/SN74S257

9392

SN5492A/SN7492A

SN5492A1SN7492A

93S258

SN54S258/SN74S258

SN54S258/SN74S258

9393

SN5493A/SN7493A

SN54293/SN74293

93400

9394

SN5494/SN7494

SN5494/SN7494

93403

9395

SN5495A/SN7495A

SN5495A/SN7495A

93404

9396

SN5496/SN7496

SN5496/SN7496

93405

SN54S138/SN74S138

93406

SN54187/SN74187

93407

SN5481 A/SN7481 A

SN5481 A/SN7481 A

SN54S300A/SN74S300A

SN54S300A/SN74S300A

SN54S301/SN74S301

SN54S301/SN74S301

SN54S200A/SN74S200A

SN54S200A/SN74S200A

SN54S201/SN74S201

SN54S201/SN74S201

93S137

SN54S201/SN74S201
SN54S289/SN74S289

SN54S289/SN74S289
SN54S289 /S N 74S289
SN54S189/SN74S189
SN54187/SN74187

93S138

SN54S138/SN74S138

SN54S138/SN74S138

93S139

SN54S139/SN74S139

SN54S139/SN74S139

93141C

SN74141

SN74141

93145

SN54145/SN74145

SN54145/SN74145

93150

SN54150/SN74150

SN54150/SN74150

93151

SN54151/SN74151

SN54151 A/SN74151 A

93412

SN54S214/SN74S214

SN54S214/SN74S214

93S151

SN54S139/SN74S139

SN54S139/SN74S139

93415A

SN54S314/SN74S314

SN54S314/SN74S314

93152

SN54152/SN74152

SN54151A/SN74151 A

93415

SN54S314/SN74S314

SN54S314/SN74S314

93153

SN54153/SN74153

SN54153/SN74153

93416

SN54S387/SN74S387

SN54S387/SN74S387

93S153

SN54S153/SN74S153

SN54S153/SN74S153

93417

SN54S387/SN74S387

SN54S387/SN74S378

93410
93411

2·5

FAIRCHILD
FSC

TI DIRECT

RECOMMENDED

FSC

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGN

TYPE

REPLACEMENT

FOR NEW DESIGN

SN54S200A/SN74S200A

SN54S200A/SN74S200A

93436

SN54S270/SN74S270

SN54S201/SN74S201

SN54S201/SN74S201

93438

SN54S475/SN74S475

93425A

SN54S214/SN74S214

SN54S214/SN74S214

93446

93425

SN54S214/SN74S214

SN54S214/SN74S214

93448

93426

SN54S287/SN74S287

SN54S287/SN74S287

9600

93427

SN54S287/SN74S287

SN54S287/SN74S287

9601

93421

•

93433

SN83433, SN93433

SN5481 A/SN7481 A

9602

93434

SN5488A/SN7488A

SN5488A/SN7488A

9603

93435

SN7489

SN7489

SN54S4 75/SN74S475
SN54S472/SN74S472

SN54S474/SN74S474

SN54S4 74/SN74S4 74

SN29601

SN54122/StlJ74122

SN54121/SN74121

SN54221/SN74221

SN54221/SN?4221
SN54123/SN74123

HARRIS
Example of Harris order code:
H

RAM

0064

2

B

Iprtixi

HARRIS

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

HARRIS

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

M 7602

SN54S188/SN74S188

SN54S188/SN74S188

M7640

SN54S475/SN74S475

M 7603

SN54S288/SN74S288

SN 54S288/S N7 4S288

M 7641

SN54S474/SN74S474

SN54S474/SN74S474

M 7610

SN54S387/SN74S387

SN 54S387/S N7 4S387

RAM 1-0064

SN7489

SN7489

M 7611

SN54S287/SN74S287

SN54S287/SN74S287

PROM 1-0512

SN54186/SN74186

SN54S470/SN74S470

SN54S470/SN74S470

PROM 1-1024

SN54S287/SN74S287

SN54S287/SN74S287

SN54S473/SN74S473

PROM 1-1024A

SN54S387/SN74S387

SN54S387/SN74S387

SN54S471/SN74S471

ROM 1-1024

SN54187/SN74187

SN54187/SN74187

SN54S472/SN74S472

PROM 1-8256

SN54S188/SN74S188

SN54S188/SN74S188

M 7620
M 7621

2·6

SN54S270/SN74S270

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

SN54S475/SN74S475

INTEL
Example of Intel order code:
3301 A

P

INTEL

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

INTEL

TI DIRECT

TYPE

REPLACEMENT

3101

SN54S289/SN74S289

SN54S289 /S N7 4S289

3301A

3101A

SN54S289/SN74S289

SN54S289/SN74S289

3304

3107A
3110

SN54S373/SN74S373

SN54S200A/SN74S200A

SN54S200A/SN74S200A 3601

SN54S387/SN74S387

SN54S387/SN74S387

SN54S201/SN74S201

SN54S201/SN74S201

3604

SN54S475/SN74S475

SN54S475/SN74S475

SN54S300A/SN74S300A

SN 54S300A/S N 74S300A 3621

SN54S287/SN74S287

SN54S287/SN74S287

SN54S301/SN74S301

SN54S301/SN74S301

3624

SN54S4 74/SN74S4 74

SN54S474/SN74S474

SN74S214, SN74S314

SN74S214/SN74S314

8212

SN54S412/SN74S412

SN54S412/SN74S412

SN54S138/SN74S138

8224

SN74LS424 (TIM8224)

SN74LS424 (TIM8224)

SN54S412/SN74S412

SN54S412/SN74S412

8228

SN74S428 (TIM8228)

SN74S428 (TIM8228)

8338

SN74S438 (TIM8238)

SN74S438 (TIM8238)

3205
3212

SN54187/SN74187
SN54S473/SN74S473

SN 54S200A/S N 74S200A 3404A

3102
3106A

SN54187/SN74187

RECOMMENDED
FOR NEW DESIGNS

•

INTERSIL
Example of Intersil ordering code:
1M

DE

C

5600

IpLiX I

INTERSIL

TI DIRECT

~

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

INTERSIL

TI DIRECT

~

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

5501

SN54S289/SN74S289

SN 54S289/S N 74S289

5502

SN5481 A/SN7481 A

SN5481 A/SN7481 A

SN54S300A/SN74S300A

SN54S300AlSN74S300A

5553

SN54S301/SN74S301

SN54S301/SN74S301

5600

SN54S188/SN74S188

SN54S188/SN74S188

SN54S214/SN74S214

SN54S214/SN74S214

5602

SN54S475/SN74S475

SN54S475/SN74S475

SN54S387/SN74S387

SN54S387/SN74S387

5503
5508

5543

SN54S300A/SN74S300A

SN54S300A/SN74S300A

SN54S301/SN74S301

SN54S301/SN74S301

SN54S200A/SN74S200A

SN54S200A/SN74S200A

SN54S314/SN74S314

SN54S314/SN74S314

5603

55S08

SN54S314/SN74S314

SN54S314/SN74S314

5604

5512

SN5481 A/SN7481 A

SN5481 A/SN7481 A

5610

SN54S288/SN74S288

SN54S288/SN74S288

55S18

SN54S214/SN74S214

SN54S214/SN74S214

5623

SN54S287/SN74S287

SN54S287/SN74S287

5523
5533

SN54S470/SN74S470

SN54S200A/SN74S200A

SN54S200A/SN74S200A

5624

SN54S370/SN74S370

SN54S370/SN74S370

SN54S201/SN74S201

SN54S201/SN74S201

5625

SN54S474/SN74S474

SN54S4 74/SN74S4 74

SN 54S300A/S N 74S300A

SN54S300A/SN74S300A

SN54S301/SN74S301

SN54S301/SN74S301

2·7

MONOLITHIC MEMORIES
Example of Monolithic Memories ordering code:
MM

N

6300

Ipr!ixl
MONOLITHIC

MONOLITHIC

•

MEMORIES

TI DIRECT

TYPE

REPLACEMENT

FOR NEW DESIGNS

MEMORIES

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

A5200

SN54S473/SN74S473

5335

A5240

SN54S473/SN74S473

5340

SN54S475/SN74S475

SN54S475/SN74S475

A5241

SN54S472/SN74S472

5341

SN54S4 74/SN74S4 74

SN54S474/SN74S474

A5280

SN54S473/SN74S473

5348

SN54S473/SN74S473

SN54S4 73/SN74S4 73

A5281

SN54S472/SN74S472

5349

SN54S472/SN74S472

SN54S472/SN74S472

A6240

SN54S4 73/SN74S473

5530

SN54S301/SN74S301

SN54S301/SN74S301

A6241

SN54S472/SN74S472

5531

SN54S201/SN74S201

SN54S201/SN74S201

A6280

SN54S473/SN74S473

5560

SN54S289/SN74S289

SN54S289/SN74S289

A6281

SN54S472/SN74S472

5561

SN54S189/SN74S189

SN54S189/SN74S189

SN54S470/SN74S470

H5200

SN54187/SN74187

SN54187/SN74187

6200

SN54187/SN74187

SN54187/SN74187

H5201

SN54S287/SN74S287

SN54S287/SN74S287

6201

SN54S387/SN74S387

SN54S387/SN74S387

H5240

SN54S473/SN74S473

6205

SN54S270/SN 74S270

SN54S270/SN74S270

H5241

SN54S4 72/SN74S472

6206

SN54S370/SN74S370

SN54S370/SN74S370

SN54S473/SN74S473

6210

SN54S287/SN74S287

6225

SN54S473/SN74S473

6230

H6200
H6201

SN 54S287/S N7 4S287

H6240
H6241

SN54S470/SN74S470
SN54S473/SN74S473
SN5488A/SN7488A

SN5488A/SN7488A

SN54S472/SN74S472

6231

SN54S4 73/SN74S4 73

5200

SN54187/SN74187

SN54187/SN74187

6235

SN54S470/SN74S470

5201

SN54S387/SN74S387

SN54S387/SN74S387

6260

5205

SN54S270/SN74S270

SN54S270/SN74S270

6300

SN54S387/SN74S387

5206

SN54S370/SN74S370

SN54S370/SN74S370

6301

SN54S287/SN74S287

SN54S470/SN74S470

6305

5210
5225

2·8

RECOMMENDED

SN54S473/SN74S473
SN54S387/SN74S387
SN54S287/SN74S287
SN54S470/SN74S470

SN54S470/SN74S470

6306

5230

SN5488A/SN7488A

SN5488A/SN7488A

6308

SN54S470/SN74S470

SN54S470/SN74S470

5231

SN54S188A/SN74S188A

SN54S188A/SN74S188A

6309

SN54S471/SN74S471

SN54S471/SN74S471

5235

SN54S470/SN74S470

6330

SN54S188A/SN74S188A

SN54S188A/SN74S188A

5255

SN54S473/SN74S473

6331

SN54S288/SN74S288

5260

SN54S473/SN74S473

6335

SN54S471/SN74S471

SN54S288/SN74S288
SN54S4 70/SN74S4 70

5300

SN54S387/SN74S387

SN54S387/SN74S387

6340

SN54S475/SN74S475

5301

SN54S287/SN74S287

SN54S287/SN74S287

6341

SN54S474/SN74S474

SN54S4 74/SN74S4 74

5305

SN54S270/SN74S270

SN54S270/SN74S270

6348

SN54S4 73/SN74S4 73

SN54S4 73/SN74S473

SN54S4 75/SN74S4 75

5306

SN54S370/SN74S370

SN54S370/SN74S370

6349

SN54S472/SN74S472

SN54S472/SN74S472

5308

SN54S470/SN74S470

SN54S470/SN74S470

6530

SN54S301/SN74S301

SN54S301/SN74S301

5309

SN54S471/SN74S471

SN54S471/SN74S471

6531

SN54S201/SN74S201

SN54S201/SN74S201

5330

SN54S188A!SN74S188A

SN54S188A/SN74S188A

6560

SN54S289/SN74S289

SN54S289/SN74S289

5331

SN54S288/SN74S288

SN54S288/SN74S288

6561

SN54S189/SN74S189

SN54S189/SN74S189

MOTOROLA
Example of Motorola order code:
MC

--,001

3

Type Number
Different numbers
are used for variations
in operating temperature

MOTOROLA

TIDIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

Package

= Flat Package
L = CDIP
P = Plastic DIP
F

MOTOROLA

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS
SN54S15

MC3000

SN74HOO

SN74S00

MC3107

MC3001

SN7408

SN74S11

MC3108

SN54H04

SN54S04

SN74S02

MC3109

SN54H05

SN54S05

MC3002
MC3003

SN7432

SN7432

MC3110

SN54H20

SN54S20

MC3004

SN74HOl

SN74S03

MC3111

SN54H21

SN54S11

MC3005

SN74Hl0

SN74S10

MC3112

SN54H22

MC3006

SN74Hll

SN74S11

MC3115

SN54S22
SN54S133. SN54S134

SN74S15

MC3116

SN54H30

SN54S133

MC3008

SN74H04

SN74S04

MC3118

SN54H62

SN54S11

MC3009

SN74H05

SN74S05

MC3119

SN54H61

SN54S11

MC3010

SN74H20

SN74S20

MC3120

SN54H50

SN54S51

MC3011

SN74H21

SN74S11

MC3121

SN54S86

MC3012

SN74H22

SN74S22

MC3122

MC3007

MC3015

SN54S86
SN54S135

SN74S133. SN74S134

MC3123

SN54H51

SN54S51

MC3016

SN74H30

SN74S133

MC3124

SN54H40

SN54S40

MC3018

SN74H62

SN74S11

MC3125

SN54H40

MC3019

SN74H61

SN74S11

MC3126

SN54S37. SN54S38
SN54S37. SN54S38

SN54S40

MC3020

SN74H50

SN74S51

MC3128

MC3021

SN74S86

SN74S86

MC3129

SN74S135

MC3130

SN54H60

SN54S11

MC3022

SN54S37. SN54S38

MC3023

SN74H51

SN74S51

MC3131

SN54H52

SN54S64

MC3024

SN74H40

SN74S40

MC3132

SN54H53

SN54S64

MC3025

SN74H40

SN74S40

MC3133

SN54H54

SN54S64

MC3026

SN74S140

MC3134

SN54H55

MC3028

SN74S240. SN74S241

MC3150

SN54S373. SN54S374
SN54S373. SN54S374

MC3029

SN54S64

SN74S240. SN74S241

MC3151

MC3030

SN74H60

SN74S11

MC3152

MC3031

SN74H52

SN74S64

MC3154

SN54H71

SN54S112

MC3032

SN74H53

SN74S64

MC3155

SN54H72

SN54S112

MC3033

SN74H54

SN74S64

MC3160

SN54H74

SN54S74

MC3034

SN74H55

SN74S64

MC3161

SN54S114

SN54S114
SN54S113

SN54S373. SN54S374

MC3050

SN74S373. SN74S374

MC3162

SN54S113

MC3051

SN74S373. SN74S374

MC3163

SN54H73

MC3052

SN74S373. SN74S374

MC4000

SN74S139
SN74184/SN74185A

SN54S112

SN74S374

MC4001

MC3054

SN74H71

SN74S112

MC4002

MC3055

SN74H72

SN74S112

MC4004

SN7481A

MC3060

SN74H74

SN74S74

MC4005

SN7481A

MC3061

SN74S114

SN74S114

MC4006

MC3062

SN74S113

SN74S113

MC4007

SN74S139

MC3063

SN74H73

SN74S112

MC4008

SN74S280

MC3053

•

SN74S139
SN7481A
SN7481A
SN74S138

2·9

MOTOROLA
MOTOROLA

TIDIRECT

RECOMMENDED

MOTOROLA

TI DIRECT

TYPE

REPLACEMENT

FOR NEW DESIGNS

TYPE

REPLACEMENT

MC3100

SN54HOO

SN54S00

MC4010

SN74S135

MC3101

S~5408

SN54S11

MC4012

SN74S299

SN54S02

MC4015

SN74S195

MC3103

SN5432

SN5432

MC4016

SN74S168

MC31 04

SN54H01

SN54S03

MC4017

SN74S168

MC3105

SN54H10

SN54S10

MC4018

SN74S169

MC3106
MC4021

SN54H11

SN54S11
SN74S85

MC4019
MC4306

SN74S169
SN54S138

MC3102

II

2·10

RECOMMENDED
FOR NEW DESIGNS

MC4022

SN74S85

MC4307

SN54S138, SN54S139

MC4023

SN74S260

MC4308

SN54S280

MC4025

SN74S124

MC4310

SN54S280

MC4026

SN74S381

MC4316

SN54S168

MC4027

SN74S381

MC4317

SN54S168

MC4028

SN74S281

MC4318

SN54S169

MC4029

SN74S281

MC4319

SN54S169

MC4029

SN74S281

MC4324

SN54S124

MC4030

SN74S281

MC4326

SN54S381

MC4031

SN74S281

MC4327

SN54S381

MC4032

SN74S182

MC4328

SN54S281

MC4035

SN74S373, SN74S374

MC4329

SN54S281, SN54S281

MC4037

SN74S373, SN74S374

rv~C4330

SI'J54S281, SN71\S381

MC4038

SN74S138

MC4331

SN54S281

MC4039

SN74S143, SN74S144

MC4332

SN54S182

MC4040

SN74S139

MC4335

SN54S373, SN54S374

MC4042

SN74S240, SN74S241

MC4337

SN54S373, SN54S374

MC4043

SN74S240, SN74S241

MC4350

SN54143

MC4048

SN74S138

MC9310

SN54160

MC4050

SN74143

MC9311

SN54154

SN54154

MC4051

SN74144

MC9316

SN54161

SN54161

MC4062

SN74S64

MCM4002

SN7488A

SN7488A

MC4300

SN54S139

MCM4004

SN7481A

SN7481A

SN54160

MC4304

SN5481A

SN5481A

MCM4005

SN7481A

SN7481A

MC4305

SN5481A

SN5481A

MCM4006

SN74S387

SN74S387

NATIONAL
Example of National order code:
DM

8

093 .

N

N - Plastic DIP
W = Flat Pack

NATIONAL

TI DIRECT

TYPE

REPLACEMENT

7091

RECOMMENDED
FOR NEW DESIGNS

NATIONAL

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

SN5437

7553

7093

SN54125

SN54125

7554

SN54S373, SN54S374

7094

SN54126

SN54126

7555

SN54S168

7095

SN54365

SN54365

7556

7096

SN54366

SN54366

7560

SN54192

SN54192

75L60

SN54L192

SN54L192
SN54193

SN54S169

7097

SN54367

SN54367

7098

SN54368

SN54368

7563

SN54193

7121

SN54251

SN54251

75L63

SN54L193

SN54L193

71 L22

SN54L157

SN54L157

7570

SN54164

SN54164

7123

SN54S257

SN54S257

7573

SN54S387

SN54S387

7130

SN54S85

7574

SN54S188

SN54S188

7131

SN54S85

7577

SN54S188

SN54S188

7136

SN5485

7578

SN54S288

SN54S288

7160

SN54S85

7582

SN54S301

SN54S301

7200

SN54S85

7588

SN54S188

SN54S188

7210

SN54151A, SN54351

7590

SN54165

SN54165

7211

SN54151A, SN54351

7594
SN54S473

SN54S473

SN54S287, SN54S370

SN54S287, SN54S370

SN54S189

SN54S189

7213

SN54154

SN54154

7595

7214

SN54LS253

SN54LS253

7596

7219

SN54150

7597

7220

SN54S280

7598

7223

SN54S139

7599

7230

SN54S257

7600

7280

SN54176

SN54176

7613

7281

SN54177

SN54177

76L70

7283

SN5483A

SN5483A

7795

SN5492A

7796

7288
7290

SN54196

SN54196

7810

7291

SN54197

SN54197

7811

SN54S200A
SN54S472
SN54S471
SN54194
SN54376
SN54L164

SN54L164
SN54S473
SN54S472

5426

5426
SN5426

7511

SN54376

7812

7512

SN54376

7819

SN54S240, SN54S241

7520

SN5497

7853

SN54221

7544

SN54265

7875A

SN54284

SN54173

SN54173

78758

SN54285

SN54S162

8091

8093

SN74125

SN74125

8551

7551
7552

•

SN54S163

SN5416

SN5416

SN74S240, SN74S241
SN74173

SN74173
SN74S162

8094

SN74126

SN74126

8552

8095

SN74365

SN74365

8553

SN74S163

8096

SN74366

SN74366

8554

SN74S373, SN74S374

8097

SN74367

SN74367

8555

SN74S168

8098

SN74368

SN74368

8556

SN74S169

2·11

NATIONAL

•

NATIONAL

TI DIRECT

RECOMMENDED

NATIONAL

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGNS

TYPE

REPLACEMENT

FOR NEW DESIGNS

8121

SN74251

SN74251

8560

SN74192

81L22

SN74L157

SN74L157

85L60

SN74L192

SN74LS192

8123

SN74S257

SN74S257

8~63

SN74193

SN74193

SN74192

8130

SN74S85

£5L63

SN74L193

SN74LS193

8131

SN74S85

8570

SN74164

SN74164

8136

SN7485

8573

SN74S387

SN74S387

8160

SN74S85

8574

SN74S287

SN74S287

8200

SN74S85

8577

SN74S188

SN74S188

8210

SN74151A, SN74351

8578

SN74S288

SN74S288

8211

SN74151 A, SN74351

8579

SN74164

SN74164
SN7495A

8213

SN74154

SN74154

8580

SN7495A

8214

SN74LS253

SN74LS253

8582

SN74S301

SN74S301

8219

SN74150

8588

SN7488A

SN7488A

8220

SN74S280

8590

SN74165

SN74165

8223

SN74S139

8597

SN74S287, SN74S370

8230

SN74S257

8598

SN74S287, SN74S370
SN7488A

8280

SN74176

SN74176

8599

SN74S189

SN74S189

8281

SN74177

SN74177

8640

SN74141

SN74141

8283

SN7483A

SN7483A

86L70

SN74L164

SN74L164

SN7492A

8810

SN7426

SN7426

8288
8290

SN74196

SN74196

8811

8291

SN74197

SN74197

8812

SN7416

8296

SN74196

SN74196

8819

SN7426

8500

SN7476

SN7476

8842

SN7442A

SN7442A

8501

SN7473

SN7473

8846

SN7446A

SN7446A

8510

SN7474

SN7426

SN7474

8847

SN7447A

SN7447A

8511

SN74276

8848

SN7448

SN7448

8512

SN74276

8853

SN74221

8520

SN7497

8875A

SN74S274

88758

SN74S274

8530

SN7490A

SN7490A

8532

SN7492A

SN7492A

8533

SN7493A

SN7493A

8544

SN74265

SIGNETICS
Example of Signetics order code:
N

B

8290

Package

E, F, Y = C-DiP
A, B, N = Plastic DIP

J,

P, R

= Flat Pack

SIGNETICS

TI DIRECT

RECOMMENDED

SIGNETICS

TI DIRECT

RECOMMENDED

~

REPLACEMENT

FOR NEW DESIGNS

~

REPLACEMENT

FOR NEW DESIGNS
SN54174/SN74174

8201

8H16

SN54S20/SN74S20

8H20

SN54S112/SN74S112

8202

SN54174/SN74174

8H21

SN54S112/SN74S112

8203

SN54174/SN74174

SN54S112/SN74S112

8204

SN54S471/SN74S471

SN54S11/SN74S11

8205

SN54S472/SN74S472

8H22
8H70

2-12

Q,

SN54H11/SN74H11

SIGNETICS
SIGNETICS

TIDIRECT

RECOMMENDED

SIGNETICS

TI DIRECT

RECOMMENDED

TYPE

REPLACEMENT

FOR NEW DESIGNS

TYPE

REPLACEMENT

FOR NEW DESIGNS

8H80

SN54HOO/SN74HOO

SN54S00/SN74S00

8H90

SN54H04/SN74H04

SN54S04/SN74S04

8T01

SN74141

8T04

SN547A/SN7447A

8T05

SN5448/SN7448

8T06

SN54143/SN74143

8T09

SN54128/SN74128

8T10

SN54173/SN74173

SN74173

8206
82S06
8207
82S07

SN54S200A/SN74S200A SN 54S200A/S N7 4S200A
SN54S201/SN74S201

SN54S201/SN74S201

SN54S200A/SN74S200A SN54S200A/SN74S200A
SN54S201/SN74S201

SN54S201/SN74S201

SN54S300A/SN74S300A SN54S300A/SN74S300A
SN54S301/SN74S301

SN54S301/SN74S301

SN54S300A/SN74S300A SN54S300A/SN74S300A
SN54S301/SN74S301

SN54S301/SN74S301

8T13

SN54128/SN74128

82S08

SN54S314/SN74S314

SN54S314/SN74S314

8T18

SN5426/SN5426

82S10

SN54S314/SN74S314

SN54S314/SN74S314

SN54121/SN74121

82S11

SN54S214/SN74S214

SN54S214/SN74S214

8T20
8T22
8T23

SN54122/SN74122

SN54122/SN74122
SN54128/SN74128

8T24
8T26
8T28
8T51
8T54
8T59
8T71
8T74
8T75
8T79

82S16
82S17

SN54S200A/SN74S200A SN54S200A/SN74S200P
SN54S201/SN74S201

SN54S201/SN74S201

SN54S300A/SN74S300A SN54S300A/SN74S300A
SN54S301/SN74S301

SN54S301/SN74S301

SN54S240/SN74S240

8223

SN54S188/SN74S188

SN54S188/SN74S188

SN54S241/SN74S241

8224

SN5488A/SN7488A

SN5488A/SN7488A

SN54143/SN74143

8225

SN54S289/SN74S289

SN54S289/SN74S289

SN54144/SN74144

82S25

SN 54S289 /SN7 4S289

SN54S289/SN74S289

SN54143/SN74143

82S26

SN54S387/SN74S387

SN54144/SN74144

8228

SN54143/SN74143

82S29

SN54S287/SN74S287

SN54144/SN74144

8230

SN39312/SN29312

SN54143/SN74143

82S30

SN54S151A/SN74S151 A

SN54144/SN74144

8231

SN54S251/SN74S251

SN54143/SN74143

82S31

SN54S151/SN74S151

SN54g4/SN74144

8232

SN54151A/SN74151A

SN54143/SN74143

82S32

SN54S151/SN74S151

SN54125/SN74125

SN54S387/SN74S387
SN545471/SN74S471
SN54S287 /SN 74S287
SN54151A/SN74151A

SN54144/SN74144

8233

SN54157/SN74157

SN54143/SN74143

82S33

SN54S157/SN74S157

SN54144/SN74144

8234

SN54S258/SN74S258

8T80

SN5426/SN7426

82S34

SN 54S258/SN 74S258

8T90

SN5406/SN7406

8235

SN4H87/SN74H87

SN54125/SN74125

8241

SN5486/SN7486

SN54425/SN74425

82S41

SN54S86/SN74S86

SN54125/SN74125

8242

SN54425/SN74425

82542

SN54S135/SN74S135

8T95

SN54365/SN74365

8243

SN54198/SN74198

8T96

SN54366/SN74366

8250

SN5442A/SN7442A

8T97

SN54367/SN74367

82S50

8T98

SN54368/SN74368

8252

8162

SN54121/SN74121

82S52

8200

SN54174/SN74174

8255

SN54S289/SN74S289

SN54S289/SN74S289

8260

SN54S281/SN74S281

82147

SN54147/SN74147

SN54147/SN74147

8261

SN54S182/SN74S182

82148

SN54148/SN74148

SN54148/SN74148

8262

SN54180/SN74180

8415

SN5420/SN7420

82S63

SN54S280/SN74S280

8416

SN5420/SN7420

8263

SN54153/SN74153

8417

SN5410/SN7410

8264

SN54153/SN74153

8424

SN54111/SN74111

8266

SN54157/SN74157

8425

SN54111/SN74111

82S66

SN54S157/SN74S157

8440

SN5450/SN7450

8T93
8T94

•

SN54 LS266/SN74 LS266 SN54LS266/SN74LS266

SN54138/SN74138
SN39301/SN29301

SN5442A/SN7442A
SN 54S280/SN 74S280

2-13

SIGNETICS
SIGNETICS

TI DIRECT

TYPE

REPLACEMENT

8267
8268

SN5480/SN7480

8269
8270

SN54178/SN74178

82S70
8271

•

SIGNETICS

TI DIRECT

TYPE

REPLACEMENT

RECOMMENDED
FOR NEW DESIGNS

SN54157/SN74157

8455

SN5440/SN7440

SN5440/SN7440

SN54181/SN74181

8470

SN541 0/SN741 0

SN5410/SN7410

SN5485/SN7485

8471

SN5412/SN7412

SN5412/SN7412

SN54194/SN74194

8480

SN5400/SN7400

SN5400/SN7400

SN54S299/SN74S299

8481

SN5403/SN7403

SN5403/SN7403

SN54194/SN74194

8490

SN5404/SN7404

SN5404/SN7404

82S71

SN54S299/SN74S299

8706

8273

SN54198/SN74198

8731

8274

SN54198/SN74198

8806

8275

SN54174/SN74174

8276

SN5491 A/SN7491 A

8277

SN5491 A/SN7491 A

8816

SN5460/SN7460
SN5460/SN7460
SN5460/SN7460

SN5460/SN7460

8808

SN5430/SN7430

SN5430/SN7430

8815

SN5425/SN7425

SN5425/SN7425
SN5420/SN7420

8280

SN54176/SN74176

SN54176/SN74176

8821

SN5476/SN7476

8281

SN54177/SN74177

SN54117/SN74177

8822

SN54107/SN74107

8283

SN54S169/SN74S169

8824

SN5476/SN7476

8284

SN54S169/SN74S169

8825

SN5470/SN7470

8285

SN54S168/SN74S169

8826

SN54107/SN74107

8288

SN54163/SN74163

8827

SN5476/SN7476

8290

SN54196/SN74196

SN54196/SN74196

8828

SN5474/SN7474

SN5474/SN7474

82S90

SN54S196/SN74S196

SN54S196/SN74S196

8829

SN54110/SN74110

SN54110/SN74110

8291

SN54197/S1'J74197

SI'J5'1LSI97/SI'J7'1LSI97

8840

SN5450/SN7450

SN5450/5N7450

82591

SN54S197/SN74S197

SN54S197/SN74S197

8848

SN54H54/SN74H74

SN54S64/SN74S64

8292

SN54LSI96/SN74S196

SN54LSI96/SN74LSI96

8855

8293

SN54LS197/SN74LS197

SN54LS197/SN74LS197

8859

SN5450/SN7450

SN5450/SN7450

82S110

SN54S314/SN74S314

SN54S314/SN74S314

8870

82S111

SN54S214/SN74S214

SN54S214/SN74S214

8875

SN5427/SN7427

SN5427/SN7427

SN54S200A/SN74S200A

SN54S200A/SN74S200A

8879

SN5410/SN7410

SN541 0/SN741 0

SN5401/SN7401

SN5401/SN7401

82S116
82S117

2·14

SN54179/SN74179

RECOMMENDED
FOR NEW DESIGNS

SN54S201/SN74S201

SN54S201/SN74S201

8880

SN 54S300A/SN74S300A

SN54S300A/SN74S300A

8881

SN5440/SN7440
SN5410/SN7410

SN5400/SN7400
SN5402/SN7402

SN54S301/SN74S301

SN54S301/SN74S301

8885

82S123

SN54S288/SN74S288

SN54S288/SN74S288

8889

82S124

SN54S387/SN74S387

SN54S387/SN74S387

8890

SN5404/SN7404

SN5404/SN7404

8891

SN5405/SN7405

SN5405/SN7405

82S126

SN54S387/SN74S387

SN54S387/SN74S387

82S129

SN54S287/SN74S287

SN54S287/SN74S287

82S130

SN54170/SN74170

SN54170/SN74170

SN5401/SN7401

•
General Information

3·1

•

3·2

GLOSSARY
TTL TERMS AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council of the
Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (lEC)
for international use.

PART I - OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)

Clock Frequency
Maximum clock frequency, f max
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence while
maintaining stable transistions of logic level at the output with input conditions established that should cause changes
of output logic level in accordance with the specification.

Current
High-level input current, IIH
The current into * an input when a high-level voltage is applied to that input.
High-level output current, 10H
The current into* an output with input conditions applied that according to the product specification will establish a
high level at the output.

•

low-level input current, III
The current into* an input when a low·level voltage is applied to that input.
low-level output current, 10l
The current into * an output with input conditions applied that according to the product specification will establish a
low level at the output.
Off-state output current, 10(off)
The current flowing into * an output with input conditions applied that according to the product specification will cause
the output switching element to be in the off state.
Note: This parameter is usually specified for open-collector outputs intended to drive devices other than logic circuits.
Off-state (high-impedance-state) output current (of a three-state output), 10Z
The current into* an output having three-state capability with input conditions applied that according to the product
specification will establish the high-impedance state at the output.
Short-circuit output current, lOS
The current into * an output when that output is short-circuited to ground (or other specified potential) with input
conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
Supply current, ICC
The current into * the V CC supply terminal of an integrated circuit.

·Current out of a terminal is given as a negative value.

)76

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

3-3

GLOSSARY
TTL TERMS AND DEFINITIONS
Hold Time
Hold time, th
The interval duripg which a signal is retained at a specified input terminal after an active transition occurs at another
specified input terminal.
NOTES: 1. The hold time is the actual time between two events and may be insufficient to accomplish the intended
result. A minimum value is specified that is the shortest interval for which correct operation of the logic
element is guaranteed.
2. The hold time may have a negative value in which case the minimum limit defines the longest interval
(between the release of data and the active transition) for which correct operation of the logic element is
guaranteed.

Output Enable and Disable Time
Output enable time (of a three-state output) to high level, tpZH {or low level, tPzLlt
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three·state output changing from a high·impedance (off) state to the defined high (or low) level.

•

Output enable time (of a three·state output) to high or low level, tPzx t
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three·state output changing from a high·impedance (off) state to either of the defined active levels (high or low).
Output disable time (of a three·state output) from high level, tPHZ {or low level, tPLZ)t
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three·state output changing from the defined high (or low) level to a high·impedance (off) state.
Output disable time (of a thr~e·state output) from high or low level, tPxz t
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three·state output changing from either of the defined active levels (high or low) to a high·impedance (off) state.

Propagation Time
Propagation delay time, tPD
The time between the specified reference points on the input and output voltage waveforms with the output changing
from one defined level (high or low) to the other defined level.
Propagation delay time, low·to·high-Ievel output, tPLH
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the defined low level to the defined high level.
Propagation delay time, high·to·low·level output, tpHL
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the defined high level to the defined low level.

tOn older data sheets. similar svmbols without the P subscript were used; i.e. tZH. tZL. tHZ. and tLZ.

H

3·4

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

GLOSSARY
TTL TERMS AND DEFINITIONS
Pulse Width
Pulse width, tw
The time interval between specified reference points on the leading and trailing edges of the pulse waveform.

Recovery Time
Sense recovery time, tSR
The time interval needed to switch a memory from a write mode to a read mode and to obtain valid data signals at the
output.

Release Time
Release time, trelease
The time interval between the release from a specified input terminal of data intended to be recognized and the
occurrence of an active transition at another specified input terminal.
Note: When specified, the interval designated "release time" falls within the setup interval and constitutes, in effect, a
negative hold time.

Setup Time

•

Setup time, tsu
The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive
active transition at another specified input terminal.
NOTES: 1. The setup time is the actual time between two events and may be insufficient to accomplish the setup. A
minimum value is specified that is the shortest interval for which correct operation of the logic element is
guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines the longest interval
(between the active transition and the application of the other signal) for which correct operation of the
logic element is guaranteed.

Transition Time
Transition time, low-to-high-Ievel, tTLH
The time between a specified low-level voltage and a specified high-level voltage on a waveform that is changing from
the defined low level to the defined high level.
Transition time, high·to-Iow-Ievel, tTHL
The time between a specified high-level voltage and a specified low-level voltage on a waveform that is changing from
the defined high level to the defined low level.

1076

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3-5

GLOSSARY
TTL TERMS AND DEFINITIONS
Voltage
High-level input voltage, VIH
An input voltage within the more positive (less negative) of the two ranges of values used to represent the binary
variables.
NOTE: A minimum is specified that is the least positive value of high-level input voltage for which operation of the
logic element within specification limits is guaranteed.
High-level output voltage, VOH
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a high level at the output.
Input clamp voltage, VIK
An input voltage in a region of relatively low differential resistance that serves to limit the input voltage swing.

•

Low-level input voltage, VIL
An input voltage level within the less positive (more negative) of the two ranges of values used to represent the binary
variables.
NOTE: A maximum is specified that is the most positive value of low-level input voltage for which operation of the
logic element within specification limits is guaranteed.
Low-level output voltage, VOL
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a low level at the output.
Negative-going threshold voltage, VTThe voltage level at anlinput that causes operation of the logic element according to specification as the input voltage
falls from a level above the positive-going threshold voltage, VT +.
Off-state output voltage, Va (off)
The voltage at an output terminal with input conditions applied that according to the product specification will cause
the output switching element to be in the off state.
Note: This characteristic is usually specified only for outputs not having internal pull·up elements.
On-state output voltage, VO(on)
The voltage at an output terminal with input conditions applied that according to the product specification will cause
the output switching element to be in the on state.
Note: This characteristic is usually specified only for outputs not having internal pull·up elements.
Positive-going threshold voltage, VT+
The voltage level at an'input that causes operation of the logic element according to specification as the input voltage
rises from a level below the negativei]oing threshold voltage, V _.
T

18'

3·6

TEXAS INSTRUMENTS
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GLOSSARY
TTL TERMS AND DEFINITIONS
PART 1\ - CLASSIFICATION OF CIRCUIT COMPLEXITY
Gate Equivalent Circuit
A basic unit-of-measure of relative digital-circuit complexity. The number of gate equivalent circuits is that number of
individual logic gates that would have to be interconnected to perform the same function.

Large-Scale Integration, LSI
A concept whereby a complete major subsystem or system function is fabricated as a single microcircuit. In this
context a major subsystem or system, whether digital or linear, is considered to be one that contains 100 or more
equivalent gates or circuitry of similar complexity.

Medium-Scale Integration, MSI
A concept whereby a' complete subsystem or system function is fabricated as a single microcircuit. The subsystem or
system is smaller than for LSI, but whether digital or linear, is considered to be one that contains 12 or more equivalent
gates or circuitry of similar complexity.

Small-Scale Integration, SSI
Integrated circuits of less complexity than medium-scale integration (MSI).

•

Very-Large-Scale Integration, VLSI
A concept whereby a complete system function is fabricated as a single microcircuit. In this context, a system, whether
digital or linear, is considered to be one that contains 1000 or more gates or circuitry of similar complexity.

1076

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3-7

TTL
EXPLANATION OF FUNCTION TABLES
EXPLANATION OF FUNCTION TABLES
The following symbols are now being used in function tables on TI data sheets:
H

high level (steady state)

L

low level (steady state)

t

transition from low to high level

+

transition from high to low level

X

irrelevant (any input, including transitions)

Z

a .. h

•

off (high-impedance) state of a 3-state output
=

the level of steady-state inputs at inputs A through H respectively

00

level of 0 before the indicated steady-state input conditions were establsihed

00

complement of 00 or level of

On

level of 0 before the most recent active transition indicated by

n

one high-level pulse

lJ

one low-level pulse

TOGGLE

a before the indicated steady-state input conditions were established
~

or t

each output changes to the complement of its previous level on each active transition indicated by +or t.

If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid
whenever the input configuration is achieved and regardless of the sequence in which it is achieved_ The output persists
so long as the input configuration is maintained_
If, in the input columns, a row contains H, L, and/or X together with t and/or +, this means the output is valid
whenever the input configuration is achieved but the transition(s) must occur following the achievement of the
steady-state levels_ If the output is shown as a level (H, L, 00, or 001. it persists so long as the steady-state input levels
and the levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the
opposite direction to those shown have no effect at the output. (If the output is shown as a pulse,
or LS, the
pulse follows the indicated input transition and persists for an interval dependent on the circuit.)

n

1071

3-8

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TTL
EXPLANATION OF FUNCTION TABLES
Among the most complex function tables in this book are those of the shift registers. These embody most of the
symbols used in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal
shift register, e.g., type 5N74194.

FUNCTION TABLE
OUTPUTS

INPUTS
CLEAR

MODE

CLOCK

PARALLEL

SERIAL

S1

SO

A

B

C

0

aA

aB

ac

aD

L

X

X

X

X

X

X

X

X

X

L

L

L

L

H

X

X

L

X

X

X

X

X

X

QAO

QBO

H
H
H
H

H

H
H
H

X

X

a

b

c

d

a

b

QCO QDO
c
d

X

H

X

X

X

X

H

QAn

QBn QCn

X

L

X

X

X

X

L

QAn

QBn

H

X

X

X

X

X

QBn

QCn

QDn

QCn
H

L

X

X

X

X

X

QBn

QCn

QDn

L

X

X

X

X

X

X

QAO

QBO

QCO QDO

H
H

H
H

L
L

t
t
t
t
t

L

L

X

L
L

LEFT RIGHT

•

The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high). no other input has any effect
and the outputs maintain the levels they assumed before the steady-state combination of clear high and clock low was
established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second line
implicitly shows that no further change in the outputs will occur while the clock remains high or on the high-to-Iow
transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if 51 and 50 are both
high then, without regard to the serial input, the data entered at A will be at output OA, data entered at B will be at
OS, and so forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low·level data, respectively, from the shift-right serial input
and the shifting of previously entered data one bit; data previously at OA is now at OS, the previous levels of Os and
Oc are now at Oc and OD respectively, and the data previously at OD is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when 51 is low and 50 is high and the levels at
inputs A through D have no effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial input
and the shifting of previously entered data one bit; data previously at Os is now at OA, the previous levels of Oc and
0D are now at Os and OC, respectively, and the data previously at OA is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when 51 is high and 50 is low and the levels at
inputs A through D have no effect.i
The last line shows that as long as both mode inputs are low, no other input has any effect and, as in the second line,
the outputs maintain the levels they assumed before the steady·state combination of clear high and both mode inputs
low was established.

77

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3-9

SERIES 54/74, 54.H/74H, 54S/74S, AND SPECIFIEDt SERIES 54L174L DEVICES
PARAMETER MEASUREMENT INFORMATION

Vee
L
FROM OUTPUT+ TEST
UNDER TEST
POINT

eL

T
=

LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS

•

NOTES;

(See Note AI

A. CL includes probe and jig capacitance.
B. All diodes are lN916 or lN3064.

_----3 V

------'1'~

TIMING
INPUT

---./f~
.."
-i'--

HIGH·LEVEL
PULSE

V______ 0 V

k- tsetup..r- thold....,

I

~

DATA
INPUT

-f'.5

--/i .

OV

-3 V

-

OV

!--tPHL

~

IN'PHAS~I
I
: -:--VOH

l

OUTPUT

1.5 V

I

,.-tPHL....
I

OUT·OF·PHASE
OUTPUT

~ 1.5 V

I
I

I

1.5 V

1.5 V

1.5 V
VOL

'3V,

OUTPUT~

CONTROL

1.5 V

1'",-------

(Low-level
enabling)

I

r--- tpZL--t
S2 open

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

I

I

Sl and
S2 closed

1---i.
""
,----VOL

1.5 V

~tPHZ~ 0.5 VO.5 V

~I VOH
WAVEFORM 2

-VOL

~PLZl
:

I

I 1.5 V

--4~"~--------OV

clo~ed,

I-tPLH--t

,

~

--+-----t---"" 4.5 V I
Sl
1.5 V

WAVEFORM 1
(See Note C)

Sl open,

(See Note_C_}_ _..;S;;,;2;;.,C;;,;I,;;,os;;,;e;;;;d....J.

- - - - - . . . . : ' ..i-----VOH
"\,
"" 1.5V
Sl and
S2 closed

(See Note FI

NOTES:

.. " v

VOLTAGE WAVEFORMS
PULSE WIDTHS

l '

:-tPLH4I

v

~

LOW·LEVEL
PULSE

1.5 V

~.;V -

V

_tw_

:--tw--!

-:----3V

1.5 V

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS

LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS

C. Waveform 1 is for an output with internal conditions such that the output Is low except whEin disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR";; 1 MHz, Zout "" 50 nand:
For Series 54/74 and 54H/74H, tr .,;; 7 ns, tf .,;; 7 ns;
For 5pecified t 5eries 54L/74L devices: tr";; 10 ns, tf";; 10 ns;
For Series 545/745, tr .,;; 2.5 ns, tf ";;'2.5 ns.
F. When measuring propagation delay times of 3-state outputs, switches ·Sl and S2 are closed.

t'L42, 'L43, 'L44, 'L46, 'L47, 'L75, 'L77, 'L96, 'L 121, 'L 122, 'L 123, 'L 153, 'L 154, 'L 157, 'L 164

8

3-10

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SERIES 54LS/74LS AND MOSTt SERIES 54L/74L DEVICES
PARAMETER MEASUREMENT INFORMATION

TEST
POINT
TEST
POINT

VCC

VCC

~~~~RO~;:t'n:~;-';;;;~
Cl
(See Note A)

T

T

;~:::
I
-,:

LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
NOTES

5kf!

LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS

II

A. CL includes probe and jig capacitance.
B. All diodes are 1 N916 or 1 N3064.
C. C1 (30 pFf is used for testing Series 54L174L devices only.

,.._----3V
TIMING
INPUT

x5:"--- ___

-----'

I

HIGH'LEVE~1.3V
1.3V

PULSE

oV

DATA
INPUT

~
1.3 V

OV

-3V

I-- tPHL ~
: -: - -

I
1.3 V

VOH

1.3 V

I

I
I

I

VOL

t- tplH-4o\

r-tPHL -1

:

~

OUT·OF·PHASE
OUTPUT

1.3 V

1

1.3V

1.3 V

VOLTAGE WAVEFORMS
PULSE WIDTHS

'~OV

:- tpLH -.I
IN.PHAS
I
OUTPUT:

I

--J

~

LOW·LEVEl
PULSE

1.3V

~~.3~ - -

-7:"~v

I

I

&.--- tw

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

I

_tw_

... tsetup..t-- 'hold....,
I
-:----3V

iVOH
1.3 V

- - -VOL

(See Note G)

~3V

OUTPUT~

CONTROL

UV

1'-.--------'l=~"'~--- -----0 V
I

(Low-level
enabling)

WAVEFORM 1
(See Note D)

r--tPZL----t
rtPLzi Sl and
-t----"'4.5V
:
I S2 closed
S1 closed,
1.3 V
1.5 V
:
S2 open
- -....
: _ ....... --,----VOl

:
I

I

.Jt'---L

'"

,..tPHZ~ 0.5 VO.5 V
I--tPZH---1
I
- - - - - . . , . : ' .i-----VOH
I
WAVEFORM 2
S1 open,
,,\-r
"'1.5V
(See Note D)
Sl and
S2 closed
----=...;;.;;=.,;;...-,/.- - - - - - '" 0 V
S2 closed

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES:

51
(See Note B)

Cl
(See Note A)

=

.L

-=

......._ _ _ _~.....

T

C1
(See Note C)

-=

~~~~RO~;:~T _

FROM OUTPUT_h TEST
UNDER TEST
POINT

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE·STATE O.UTPUTS

D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
E. In the examples above, the phase relationships between inp~ts and outputs have been chosen arbitrarily.
F. All input pulses are supplied by generators having the following characteristics: PRR';;; 1 MHz, Zout '" 5011 and:
For Series 54L/74L gates and inverters, tr = 60 ns, tf = 60 ns;
For Series 54L174L flip-flops and MSI. tr .;;; 25 ns, tf .;;; 25 ns;
For Series 54LS/74LS, tr .;;; 15 ns, tf .;;; 6 ns.
G. When measuring propagation delay times of 3-state outputs, switches Sl and S2 are closed.

t Except 'L42, 'L43, 'L44, 'L46, 'L47, 'L75, 'L77, 'L96, 'L 121,

'L 122, 'L 123, 'L 153,

'L 154, 'L 157, 'L 164

377

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3·11

•

3·12

Ordering Instructions
and
Mechanical Data

•

4-1

•

4-2

TTL INTEGRATED CIRCUITS MECHANICAL DATA
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for circuit type(s) listed in the page
heading regardless of package. The availability of a circuit function in a particular package is denoted by an alphabetical
reference above the pin-connection diagram(s). These alphabetical references refer to mechanical outline drawings
shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained in the
following example.
EXAMPLE: 4N 54LS75 J

-00

( 1. Prefix)
MUST CONTAIN TWO OR THREE LETTERS
(From Individual Data Sheet)
RSN
SN
SNM
SNC
SNH
SNJ

Radiation-Hardened Circuit
Standard Prefix
Mach IV, Levell
Mach IV, Level III
Mach IV, Level IV
JAN Processed

/-----.( 4. Instructions (Dash No.)
MUST CONTAIN TWO NUMBERS
(From Dash No. Column of Following Table)

Examples:

•

METAL FLAT PACKAGES

2. Unique Circuit Description
MUST CONTAIN FOUR TO EIGHT CHARACTERS
(From Individual Data Sheet)
5410
74H10
54S112
54L78
74LS295A
74188A

J,JD,N,T,W
(From Pin-Connection Diagram on Individual Data Sheet)

T

No

No

No

t

00

T

Yes

No

Yes

t

01

T

No

No

No

Mech-Pak

02

T

No

No

Yes

Mech-Pak

03

T
T

Yes

No

No

Mech-Pak

04

Yes

No

Yes

Mech-Pak

05

T

No

No

Yes

t

06

T

Yes

No

No

t

07

T

No

Yes

No

t

10

T
T

Yes

Yes

Yes

t

11

No

Yes

No

Mech-Pak

12

T

No

Yes

Yes

Mech-Pak

13

T

Yes

Yes

No

Mech-Pak

14

T

Yes

Yes

Yes

Mech-Pak

15

T

No

Yes

Yes

t

16

T

Yes

Yes

No

t

17

CERAMIC FLAT PACKAGES

I
I

W
W

I
I

No
No

I

No

N/A

Yes

N/A

00
10

No

N/A

00

Yes

N/A

10

DUAL-IN-LiNE PACKAGES
J, JD, N

N

No
No

I

tThese circuits are shipped in one of the carriers shown below. Unless a specific method of shipment is specified by the customer (With possible additional posts), circuits will be shipped in the most practical carrier. Please contact your TI sales representative for the method that
will best suit your particular needs.

Flat (T, W)
-Barnes Carrier
-Milton Ross Carrier

Dual-in-line «J, JD, N)
-Slide Magazines
-A-Channel Plastic Tubing
-Barnes Carrier (N only)
-Sectioned Cardboard Box
-Individual Plastic Box

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TTL INTEGRATED CIRCUITS MECHANICAL DATA
J ceramic dual-in-line package
These hermetically sealed dual-in-Iine packages consist of a ceramic base, ceramic cap, and a 14-, 16-,20-, or 24-lead
frame. Hermetic sealing is accomplished with glass. The packages are intended for insertion in mounting-hole rows on
0.300 (7,62) or 0.600 (15,24) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads (-00) require
no additional cleaning or processing when used in soldered assembly.
14-PIN J CERAMIC

•

-1

0.070 (1,78) MAX 14 PLACES
0.050
(1,27) NOM

ffi 8

...,.....

~..,."""I!'iIII~~

0.200 (5,08)
MAX

lOS'

- SEATING PLANE

LO.030(O,76)MIN
14 PLACES

9li'"

I

0.130 (3,30)
MIN

-+j

~

14 PLACES,.-II0.014 (0.356)
0008 (0 203)
;4 PLACES

GLASS
SEALANT

r-

0.100 (2,54)
0.070 (1,77)

PIN SPACING 0.100 (2,54) T.P.

4 PLACES

(See Nota b)

0.023 (0,584) 14 PLACES
0.015 (0,381)

Falls within JEDEC TO-116 and MO-001 AA dimensions

16-PIN J CERAMIC

1i.§1i.°'~:;!~:~:~::

ba
"1

~----~~--"~~~S~~~~T

- SEATING PLANE ---.-l'----~~ 1,/

1I~ft--++--Ht0.030 (0.76) MIN

90'

16 PLACES

00000@00

0.050 (1,27) NOM

f.f\
105'

280 (711).
0.245 (6,22)

II

jL.

0.014 (0,356)

~ ~0.008 (0,203)

12 PLACES
0.023 (0 584) 16 PLACES

-11~0.015 (0,381)

16 PLACES

~:~~~ :~:~~:

4 PLACES

+For memories of 64 bits and up and a few MSIILSI products in Series 54/74 and Series 54S/74S that
are derived from memory circuit bars, this maximum is 0.300 (7,62). All other dimensions apply
without modification.

87i

4-4

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TTL INTEGRATED CIRCUITS MECHANICAL DATA
J ceramic dual-in-line packages (continued)
2()'PIN J CERAMIC
0.975 (24,8)

I0Il
1
. 1 - - - - 0.930 (23,6)

'M'''U'".'M{!~~~~~~~J

~g'~~~~:
1

000000000@

0.020 (0,51)
MIN

OOSO (1,27) NOM

~
0

\I

r'
I

+ ~
'1.------"

0.130 (3,30) ,
MIN
0.014 (O,356)

.-.\14-0.00S (0.203)
20 PLACES

0.070 (1,78) MAX 20 PLACES

II'r:;:~~;;;;;;;;::;~;;;~tY

0200 (5,OS)

--SEATING PLANE __----L*_M,A_X_ _--.--_

1050
90
20 PLACES

-----t-I

0.012 (0,304) MIN.Ji
4 PLACES

l

U

GLASS
SEALANT

llit'll-tt---tl-ttt- 0'OJO (0,76) MIN
16 PLACES

~:~~~ :~,~:

20 PLACES

~:~~ :~:~: 4 PLACES

PIN SPACING 0.100 (2,54) T. P.
(See Note b)

24-PIN J CERAMIC

•

~-----::~~~:~~\.--------­

@@@@@@@@@@@@

0.025 (0,63) R
NOM

CD000®®0®®@@@
0.075 (1,91)

Lo:o5Oi1.m
J.:.!:.:

0.070 (1.78) MAX 24 PLACES-H

I I

GLASS SEALANT

-SEATING PLANEr-

~:~;~ :~:~~: II ~
(0,254 ± 0,051)
24 PLACES

1 r-

O.D1S ± 0.002
(0,457 ± 0,051)
24 PLACES

PIN SPACING 0.100 (2,54) T.P.
(S.. Not. b)

Falls within JEDEC MO-015AA dimensions

NOTES:

a.

All dimensions are shown in inches (and parenthetically In millimeters for reference only). Inch dimensions govern.

b. Each pin centerline is located within 0.010 (0,26) of its true longitudinal position.

877

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4-5

TTL INTEGRATED CIRCUITS MECHANICAL DATA
N plastic dual-in-line packages
These dual-in-line packages consist of a circuit mounted on a 14-, 16-,20-, or 28-lead frame and encapsulated within an
electrically nonconductive plastic compound. The compound will withstand soldering temperature with no deformation and circuit performance characteristics remain stable when operated in high-humidity conditions. The packages are
intended for insertion in mounting hole rows on 0.300 (7,62) or 0.600 (15,24) centers. Once the leads are compressed
and inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional cleaning or processing when used in soldered assembly.
14-PIN N PLASTIC

~~~

1l.[B1'.~"".

':,:,~:;:': : ~
~®:: @:~ ®:~I
@:: ®::

17,62<0,261

~:,~~~~~!~
--I
a aBO 12,031 NOM
I.J.

•

--t?i

,

0000000

~S

;tt'

0'020I0'511~1

lO.010 10,251 NOM 0.200 15,OBI MAX

-

SEATING PLANE

--"""+'---.---.--

105"
IiO'

14 PLACES

..i-.-

~ ~ -II-

J \..- 0 011 < 0.003

10'~;:~:c~:1

0,12513,171 MIN

ISe. Notes c and dl

~ 1~~ ; ~:~~~

003310,831
14
PLACES MIN
0018 < 0.003
10,457 < 0,0761

IS~~:~:~~~d dl

4 PLACES

PIN SPACING 0.100 12,541 T.P.
ISee Not. bl

Falls Within JEDEC TO-116 and MO-001AA Dimensions

16-PIN N PLASTIC

~0'870122'" MAX~

"11 tt': :,: '. ·:.~~==f:0:VVVI
:b.- LUr
f51
01.~:I~~:16~OM

00000000

-L

0'02010'5;-'~io07011'7BIMAXI6PLACES

t

0010 10,251 NOM 0.200 15,081 MAX~

-SEATING PLANE--....I.'---.-----r----1

W;
90

16 PLACES-\

.

~ I~~~!:
~:~~~I
16 PLACES

+11+

0.12513,171 MIN

ISee Notes c and dl

~:~: :~:~~~.....
4 PLACES

PIN SPACING 0.100 12,541
ISee Nota bl

003310,831 MIN
16 PLACES

0 01B < 0003
10,457 < 0,0761

T.p.I~: ~~.~~~nd dl

ALTERNATE SIDE VIEW
Package configuration of
16-pin N package h..
litemativllideviews) is
at the option of TI.

-.j
,
0.200 15,08~ MAX

1--0.070 11,7BI MAX 16 PLACES

0'02~1~'5tl~1
~

~

.

0.12513,171 MIN

~:~:
:~:~~f4 PLACES

L

-.j

~

0.0331O,B31MIN
12 PLACES

--l j..

PIN SPACING 0.100 12,541
ISee Not. bl

O.Q1B ±0.003
10.457 ± 0,0761

T.P.Is.:~:t::;~~d dl

87

4-6

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TTL INTEGRATED CIRCUITS MECHANICAL DATA
N plastic dual-in-line packages (continued)
20-PIN N PLASTIC

!+-----~~ :~~:~f------.j

1+-_ _1+-_0.250, 0.010
16,35' 0,261

--1

-.t a OSO 12,031 NOM
-

-'::0010 10,251 NOM

-SEATING PLANE 020015 OSIMAX

j

i

f

~

-\~100021719±.00,0007361

~I

~
012513,171

20 PLACES
(See Notes c and d)

-L
J

r - 0 070 11,7S1 MAX 20 PLACES

002010'511~O

+

007511,91)

0.009 10,221
4 PLACES

~

f--003310S31MIN
20 PLACES

~

001S
-.If.-- 10,457'0,0761
'0003
20 PLACES

PIN SPACING 0100 (2.541 T P

(See Notes c and d)

lSee Not. bl

•

ALTERNATE SIDE VIEW

Package configurationaf

20-pin N package (see
alternativesidevieW1) is
at the option ofTI.

24-PIN N PLASTIC
1------1,310133,3) M A X - - - - . . . j

@@@@@@@@@@@@

055~6:;'97)1


..

''':

,

..6e page 6-10

SN54H11 (J)
SN54LS11 (J, W)
SN54S11 (J, W)

SN74H11 (J, N)
SN74LS11 (J, N)
SN74S11 (J, N)

28

SN54H11 (W)

TRIPLE 3-INPUT
POSITIVE-NAND GATES
WITH OPEN-COLLECTOR OUTPUTS

12
positive logic:
Y=ABC

2A

28

SN5412 (J, W)
SN54LS12 (J, W)

2C

SN7412 (J, N)
SN74LS12 (J, N)

See page 6-4

•
I

20

2C

NC

28

DUAL 4-INPUT
POSITIVE-NAND
SCHMITT TRIGGERS

13
positive logic:
Y= ABCD
SN5413 (J, W)
SN54LS13 (J, W)

See page 6-14

SN7413 (J, N)
SN74LS13 (J, N)

NC-No internal connection

HEX SCHMITT-TRIGGER
INVERTERS

14
positive logic:

Y=A
SN5414 IJ, W)
SN54LS14 (J, W)

SN7414 (J, N)
SN74LS14 (J, N)

See page 6-14

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

OALLAS. TEXAS 75222

5-9

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
TRIPLE 3·INPUT
POSITIVE·AND GATES
WITH OPEN·COLLECTOR OUTPUTS

15
positive logic:
Y= ABC
SN54H15 (J, W)
SN54LS15 (J, W)
SN54S15 (J, W)

See page 6·12

SN74H15 (J, N)
SN74LS15 (J, N)
SN74S15 (J, N)

HEX INVERTER BUFFERS/DRIVERS
WITH OPEN·COLLECTOR
HIGH·VOLTAGE OUTPUTS

16 '
positive logic:
Y=A

II

SN5416 (J, W)

SN7416 (J, N)

SN5417 (J, W)

SN7417 (J, N)

See page 6·24

HEX BUFFERS/DRIVERS
WITH OPEN·COLLECTOR
HIGH·VOLTAGE OUTPUTS

17
positive logic:

Y=A

See page 6·24

DUAL 4·INPUT
POSITlVE·NAND GATES

20
positive logic:

Y = ABCD

See page 6·2

18

Vcc

GNO

1C

SN5420 (J)
SN54H20 (J)
SN54L20 (J)
SN54LS20 (J, W)
SN54S20 (J, W)

SN7420 (J, N)
SN74H20 (J, N)
SN74L20 (J, N)
SN74LS20 (J, N)
SN74S20 (J, N)

SN5420 (W)
SN54H20 (W)
SN54L20 (T)
NC-No internal connection

107E

5·10

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
DUAL 4-INPUT
POSITIVE-AND GATES

21
positive logic:
Y

= ABCD
GNO

See page 6-10

SN54H21 (JI
SN54LS21 (J. WI

SN74H21 (J. NI
SN74LS21 (J. NI

Ne

Vee

NC

2B

SN54H21 (WI
NC-No internal connection

DUAL 4-INPUT
POSITIVE-NAND GATES
WITH OPEN-COLLECTOR OUTPUTS

22
positive logic:
Y

= ABCD

See page 6-4

1e

SN5422 (J. WI
SN54H22 (JI
SN54LS22 (J. WI
SN54S22 (J. WI

Vee

GNO

SN7422 (J. NI
SN74H22 (J. NI
SN74LS22 (J. NI
SN74S22 (J. NI

•

SN54H22 (WI

NC-No internal connection

EXPANDABLE DUAL 4-INPUT
POSITIVE-NOR GATES
WITH STROBE

23
positive logic:
1Y
2Y

= 1G(1A+1B+1C+1DI+X
= 2G(2A+2B+2C+2DI
X = output of SN5460/SN7460

See page 6-39

SN5423 (J. WI

SN7423 (J. NI

SN5425 (J. WI

SN7425 (J. NI

DUAL 4-INPUT
POSITIVE-NOR GATES
WITH STROBE

25
positive logic:
Y

= G(A+B+C+DI

See page 6-8

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE SOX 5012

•

DALLAS. TEXAS 75222

5·11

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
QUADRUPLE 2-INPUT
HIGH-VOLTAGE INTERFACE
POSITIVE-NAND GATES

26
positive logic:
Y;AB
See pages 6-24 and 6-26

SN5426 (J)
SN54LS26 (J, W)

SN7426 (J, N)
SN74LS26 (J, N)

SN5427 (J, W)
SN54LS27 (J, W)

SN7427 (J, N)
SN74LS27 (J, N)

SN5428 (J, W)
SN54LS28 (J, W)

SN7428 (J, N)
SN74LS28 (J, N)

.
Q-

TRIPLE 3-INPUT
POs)IVE_NOR GATES

\27
~.,.....

positive logic:
Y; A+B+C

See page 6-8

II

QUADRUPLE 2-INPUT
POSITIVE-NOR BUFFERS

28
positive logic:
Y; A+B

See page 6-20

8-INPUT
POSITIVE-NAND GATES

30
positive logic:
Y; ABCDEFGH

See page 6-2

SN5430 (J)
SN54H30 (J)
SN54L30 (J)
SN54LS30 (J, W)
SN54S30 (J, W)

SN7430 (J, N)
SN74H30 (J, N)
SN74L30 (J, N)
SN74LS30 (J, N)
SN74S30 (J, N)

SN5430 (W)
SN54H30(W)
SN54L30 (T)
NC-No internal connection

107€

5-12

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
QUADRUPLE 2·INPUT
POSITlVE·OR GATES

32
positive logic:
Y=A+B

See page 6·28

SN5432 (J, WI
SN54LS32 (J, WI
SN54S32 (J, WI

SN7432 (J, NI
SN74LS32 (J, NI
SN74S32 (J, NI

SN5433 (J, WI
SN54LS33 (J, WI

SN7433 (J, NI
SN74LS33 (J, NI

QUADRUPLE 2·INPUT
POSITlVE·NOR BUFFERS
WITH OPEN·COLLECTOR OUTPUTS

33
positive logic:
Y=A+B

See pages 6·24 and 6·26

QUADRUPLE 2·INPUT
POSITIVE·NAND BUFFERS

•

37
positive logic:
Y=AB
GND

SN5437 (J, WI
SN54LS37 (J, WI
SN54S37 (J, WI

See page 6·20

SN7437 (J, NI
SN74LS37 (J, NI
SN74S37 (J, NI

QUADRUPLE 2·INPUT
POSITIVE·NAND BUFFERS
WITH OPEN·COLLECTOR OUTPUTS

38
positive logic:
Y=AB
SN5438 (J, WI
SN54LS38 (J, WI
SN54S38 (J, WI
See pages 6-24 and 6-26

SN7438 (J, NI
SN74LS38 (J, NI
SN74S38 (J, NI'

I'

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

5-13

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VI EWS)
DUAL 4-INPUT
POSITIVE-NAND BUFFERS

40
positive logic:
Y= ABCD

See page 6-20

Vcc

1C

1B

SN5440 (J)
SN54H40 (J)
SN54LS40 (J,W)
SN54S40 (J, W)

SN7440 (J, N)
SN74H40 (J, N)
SN74LS40 (J, N)
SN74S40 (J, N)

SN5440 (W)
SN54H40 (W)
NC-No internal connection

INPUTS

42

BCD-TO-DECIMAL

43

EXCESS-3-TO-DECIMAL

44

EXCESS-3-GRAY -TO-DECIMAL

OUTPUTS

vcc~~

4 LINE-TO-10-LlNE DECODERS

II
See page 7-15

SN5442A (J, W)
SN54L42 (J)
SN54LS42 (J, W)
SN5443A (J, W)
SN54L43 (J)
SN5444A (J, W)
SN54L44 (J)

SN7442A (J, N)
SN74L42 (J, N)
SN74LS42 (J, N)
SN7443A (J, N)
SN74L43 (J, N)
SN7444A (J, N)
SN74L44 (J, N)

SN5445 (J, W)

SN7445 (J, N)

BCD-TO-DECIMAL DECODER/DRIVER

45

LAMP, RELAY, OR MOS DRIVER
aO-mA CURRENT SINK
OUTPUTS OFF FOR INVALID CODES

See page 7-20

107

5-14

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VI EWS)
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

46

ACTIVE-LOW, OPEN-COLLECTOR, 30-V OUTPUTS

47

ACTIVE-LOW, OPEN-COLLECTOR, 15-V OUTPUTS

See page 7-22

SI'.I5446A (J, W)
SN54L46 (J)
SN5447A (J, W)
SN54L47 (J)
SN54LS47 (J, W)

SN7446A (J, N)
SN74L46 (J, N)
SN7447A (J, N)
SN74L47 (J, N)
SN74LS47 (J, N)

SN5448 (J, W)
SN54LS48 (J, W)

SN7448 (J, N)
SN74LS48 (J, N)

BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

48

INTERNAL PULL-UP OUTPUTS

See page 7-22

BCD-TO-SEVEN-SEGMENT'DECODERS/DRIVERS

49

OPEN-COLLECTOR OUTPUTS

SN5449 (W)
SN54LS49 (J, W)

See page 7-22

SN74LS49 (J, N)

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

5·15

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
DUAL 2-WIDE 2-INPUT
AND-OR-INVERT GATES
(ONE GATE EXPANDABLEI

50
positive logic:
Y = AB+CD+X
'50: X = output of SN5460/SN7460
'H50: X = output of SN54H60/SN74H60
or SN54H62/SN74H62
See page 6-39

SN7450 (J, NI
SN74H50(J, NI

SN5450 (JI
SN54H50 (JI

SN5450 (WI
SN54H50 (WI

MAKE NO EXTERNAL CONNECTION

AND-OR-INVERT GATES

r----"----..

51
'51, 'H51, 'S51
DUAL 2-WIDE 2-INPUT
positive logic:
Y

~

AB+CD

II

MAKE NO EXTERNAL CONNECTION

SN5451 (JI
SN54H51 (JI
SN54S51 (J. WI

SN7451 (J. NI
SN74H51 (J. NI
SN74S51 (J. NI

SN5451 (WI
SN54H51 (WI

SN54L51 (JI
SN54LS51 (J, WI

SN74L51 (J. N)
SN74LS51 (J, NI

SN54L51 (T)

'L51, 'LS51
2-WIDE 3-INPUT,
2-WIDE 2-INPUT
positive logic:
1Y = (1A'1B'1C)+(1 D'1E'1FI
2Y = (2A'2B)+(2C'2D)

See page 6-30

10'

5-16

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
EXPANDABLE 4-WIDE
AND-OR GATES

52
'H52(J, N)
positive logic:

Y = AB+CDE+FG+HI+X
X

= output of SN54H61/SN74H61
SN54H52 (J)

SN74H52 (J, N)

'H52(W)
positive logic:

Y = AB+CD+EF+GHI+X
X

= output

of SN54H61/SN74H61
D

Vee

E

SN54H52 (W)

See page 6-39
NC-No internal connect jon

EXPANDABLE 4-WIDE
AND-OR-INVERT GATES

53
'53
positive logic:

Y = AB+CD+EF+GH+X
X

= output of SN5460/SN7460

SN5453 (J)

SN7453 (J, N)

A

Vee

B

A

vee

B

SN5453 (W)

'H53
positive logic:

Y = AB+CD+EFG+HI+X
X

= output of SN54H60/SN74H60
or SN54H62/SN74H62

SN54H531J)

SN74H53 (J,N)

SN54H53 (W)

See page 6-39
NC-No internal connection

81

TEXAS INSTRUMENTS
INCORPORATED'

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

5-17

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
4-WIDE
AND-OR-INVERT GATES

'54
positive logic:

Y - AB+CD+EF+GH
NC

SN5454 (JI

SN7454 (J, NI

SN5454 (WI

'H54
positive logic:

Y = AB+CD+EFG+HI
I

•

G

SN54H54 (JI

GNO

SN74H54 (J, NI

'---.r--' A
Vee
MAKE NO EXTERNAL CONNECTION

B

SN54H54 (WI

'L54(J. NI, 'LS54
positive logic:

Y = AB+CDE+FGH+IJ

SN54L54 (JI
SN54LS54 (J, WI

SN74L54 (J, NI
SN74LS54 (J, NI

'L54(T)
positive logic:

Y = ABC+DE+FG+HIJ

SN54L54 (TI

See page 6-30
NC-No internal connection

10]

5·18

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)

2-WIDE 4-INPUT
AND-OR-INVERT GATES

55
'H55 (EXPANDABLE)
positive logic:
Y

= ABCD+EFGH+X
X = output of SN54H60/SN74H60

Vcc

E

Vcc

E

or SN54H62/SN74H62
SN74H55 (J, N)

SN54H55 (J)

SN54H55(W)

See page 6-39

'L55, 'LS55
positive logic:
Y

= ABCD+EFGH

See page 6-30

SN74L55 (J, N)
SN74LS55 (J, N)

SN54L55 (J)
SN54LS55 (J, W)

SN54L55 (T)
NC-No internal connection

II

DUAL 4-INPUT EXPANDERS

I

60
positive logic:
X

= ABCD when connected to X and X inputs

of SN5423/SN7423, SN5450/SN7450, or
SN5453/SN7453
'H60
positive logic:
X

= ABCD when connecte'd to X and X
inputs of SN54H50/SN74H50,
SN54H53/SN74H53, or
SN54H55/SN74H55

2A

28

GNO

SN7460 (J, N)
SN74H60 (J, N)

SN5460 (J)
SN54H60 (J)

See pages 6-43 and 6-44

SN5460 (W)
SN54H60 (W)

NC-No internal connection

TRIPLE 3-INPUT
EXPANDERS

61
positive logic:
X

= ABC when connected to X input of
SN54H52/SN74H52
SN54H61 (J)

SN74H61 (J, N)

SN54H61 (W)

See page 6-45

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

5·19

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
4·WIDE AND-OR EXPANDERS

62
'H62(J, NI (2·3·3·2 INPUT!
positive logic:
X = AB+CDE+FGH+IJ when connected
to X and X inputs of SN54H50/SN74H50,
SN54H53/SN74H53, or SN54H55/SN74H55
SN54H62 (JI

SN74H62 (J, NI

'H62(WI (3·2·2·3 INPUT!
positive logic:
X

•

= ABC+DE+FG+HIJ when connected to
X and X inputs of SN54H50/SN74H50,
SN54H53/SN74H53, or SN54H55/SN74H55

SN54H62 (WI

See page 6-44

HEX CURRENT-SENSING INTERFACE GATES

63

TRANSLATES LOW·LEVEL I NPUT CUR RENT TO LOW·LEVEL VOLTAGE
AND
HIGH·LEVEL CURRENTTO HIGH·LEVEL VOLTAGE

SN54LS63(J,WI SN74LS63(J,NI
See page 6-62

4·2·3·2 INPUT AND·OR·INVERT GATES

64

TOTEM·POLE OUTPUT

65

OPEN-COLLECTOR OUTPUT

positive logic: Y

= ABCD+EF+GHI+JK
SN54S64 (J, WI
SN54S65 (J, WI

SN74S64 (J, NI
SN74S65 (J, NI

See pages 6·30 and 6-32

1071

5·20

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE

eox

5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

70

FUNCTION TABLE
INPUTS

OUTPUTS

PRESET CLEAR CLOCK

J

K

a

L

H

L

X

X

H

L

H

L

L

X

X

L

H

a

L

L

X

X

X

L*

L*

H

H

t

L

L

ao

H

H

t

H

L

H

00
L

H

H

t

L

H

L

H

H

H

t

H

H

TOGGLE

H

H

L

x

X

ao

SNS470 (J)

SN7470 (J, N)

SNS470 (W)

00

positive logic: J = J1·J2·J
K = K1·K2·j(
If inputs J and j( are not used, they must be grounded.
See page 6-46~ Preset or clear function can occur only when the clock input·.is low.

NC-No internal connection

AND.OR:GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET

H71
FUNCTION TABLE
INPUTS

OUTPUTS

L
H
H
H

x
.n.
.n.
.n.

a

K

PRESET CLOCK J

a

X

X

H

L

L

L

H

L

00
H

00
L

L

H

L

H

H
H
TOGGLE
IL
positive logic: J = (J1A·J1 B)+(J2A·J2B)

H

K

SNS4H71 (J)

SN74H71 (J, N)

•

SNS4H71 (W)

= (K1A·K1B)+(K2A·K2B)

See page 6-S0

AND-GATED R-S MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR

L71

FUNCTION TABLE
INPUTS

OUTPUTS

PRESET CLEAR CLOCK

S

R

a

L

H

X

X

X

H

L

H

L

X

X

X

L

H

0

L

L

X

X

X

H*

H*

H

H

L

L

ao

H

H

H

L

H

00
L

H

H

.n.
.n.
.n.

L

H

IL
H
H
H
..
positive logic: R = R1· R2· R3
S = Sl·S2·53

H

NC

L
H
INDETERMINATE

CLR

51

SNS4L71 (J)

52

SN74L71 (J, N)

See page 6-S4

R1

CK

Vee

CLR

SNS4L71 (T)

NC-No internal connection

See explanation of function tables on page 3-8.

·This~~nfiguratioll is nonstable; t~hat is, U:·will not persist when preset and clear inputs return to their inactive (high) level.

076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

OALLAS, TEXAS 75222

5-21

I

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR

72

FUNCTION TABLE
OUTPUTS

INPUTS
PRESET CLEAR CLOCK

J

K

a

L

H

X

X

X

H

a
L

H

L

X

X

X

L

H

L

L

X

X

X

H·

H·

H

H

..I1..
..I1..
..I1..
..I1..

L

L

ao

H

L

H

00
L

L

H

L

H

H

H

H

H

H

H

H
H
..
posItIve logIc: J

SN5472 (JI
SN54H72 (JI
SN54L72 (JI

TOGGLE

= Jl·J2·J3; Kl·K2·K3

SN7472 (J, NI
SN74H72 (J, NI
SN74L72 (J, NI

See pages 6-46, 6-50, and 6-54

SN5472 (WI
SN54H72 (WI
SN54L72 (T)
NC-No internal connection

DUAL J-K FLIP-FLOPS WITH CLEAR

73
'73, 'H73, 'L73
FUNCTION TABLE
OUTPUTS

IN!'UTS

•

CLEAR CLOCK

'LS73A
FUNCTION TABLE
K

a

X

X

L

~

L

L

~

H

L

00
H

H
00
L

L

H

a

X

L

H

L

x

00
H

00
L

H
H

L

H

x

X

H

..n

L

L

H

..n..

H

L

H

.n..

L

H

H

.IL

H

H

a

J

K

L

OUTPUTS

IN!'UTS

J

CLEAR CLOCK

TOGGLE

a

H

~

L

H

H

~

H

H

TOGGLE

H

H

X

X

00

lCK

1
CLR

lK

VCC

SN5473 (J, WI
SN54H73 (J, WI
SN54L73 (J, TI
SN54LS73A (J, WI

00

2CK

2
CLR

SN7473 (J, NI
SN74H73 (J, NI
SN74L73 (J, NI
SN74LS73A (J, NI

See pages 6-46, 6-50,6-54, and 6-56
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

74.
FUNCTION TABLE
INPUTS

OUTPUTS

PRESET CLEAR CLOCK

0

a

a

L

H

X

X

H

L

H

L

X

X

L

H
H·

L

L

X

X

H·

H

H

t

H

H

L

H

H

t

L

L

H

H

H

L

X

00

60

See pages 6-46, 6-50, 6-54, and 6-56

1
CLR

10

lCK

SN5474 (JI
SN54H74 (JI
SN54L74 (JI
SN54LS74A (J, WI
SN54S74 (J, WI

GNO

lCK

1
CLR

VCC

2
CLR

20

2CK

SN7474 (J, NI
SN5474 (WI
SN74H74 (J, NI
SN54H74 (WI
SN74L74 (J, NI
SN54L74 (TI
SN74LS74A (J, NI
SN74S74 (J, NI

See explanation of function tables on page 3-8.
'This configuration is nonstable; that is, it will not persist when preset or clear inputs return to their Inactive (high) level. Furthermore, the
output levels of the 'LS74A in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are
near VIL maximum.

5-22

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INCORPORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
4-BIT BISTABLE LATCHES

75
FUNCTION TABLE
(Each Latch)
OUTPUTS

INPUTS
D

G

Q

a

L

H

L

H

H

H

H

L

X

L

00

00

SN5475 (J, WI
SN54L75 (J)
SN54LS75 (J, W)

SN7475 (J, N)
SN74L75 (J, N)
SN74LS75 (J, N)

H high level, L = low level, X irrelevant
00 the level of 0 before the high-to-Iow transistion of G
Q

Q

Q

See page 7-35

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR

76
'LS76A
FUNCTION TABLE

76, 'H76
FUNCTION TABLE

L

H

H

L

OUTPUTS

INPUTS

OUTPUTS

INPUTS

J

K

a

a

X
X

X
X

X

H

L

L

H

X

L

H

H

L

X
X

PRESET CLEAR CLOCK

PRESET CLEAR CLOCK

J

K

a

X
X

X

H

L

X

L

H

a

L

L

X

X

X

H'

H'

L

L

X

X

X

H'

H'

H

H

.n.
.n.
.n.
.n.

L

L

00

00

H

H

~

L

L

00

00

H

L

H

H

~

H

L

H

L

L

H

H

H

~

L

H

L

H

H

H

~

H

H

TOGGLE

H

H

H

X

X

00

H

H

H

H

H

H

H

L

L

H

H

H

TOGGLE

SN5476 (J, W)
SN7476 (J, N)
SN54H76 (J, WI
SN74H76 (J, N)
SN54LS76A (J, WI SN74LS76A (J, NI

•

00

See pages 6-46, 6-50, and 6-56

4-BIT BISTABLE LATCHES

77
FUNCTION TABLE
(Each Latchl
INPUTS

OUTPUTS

D

G

a

a

i.

H

L

H

H

H

H

L

X

L

00

00

H high level, L low level, X irrelevant
00 the level of 0 before the high-to-Iow transistion of G
Q

Q

SN5477 (W)
SN54L77 (T)
SN54LS77 (WI

Q

Q

See page 7-35
See explanation of function tables on page 3-8.
"This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactIve (high) level.

TEXAS INSTRUMENTS
INCORPORATEb

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

5-23

I

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VI EWS)
DUAL J-K FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

78

'H78, 'L78
FUNCTION TABLE
INPUTS

OUTPUTS

PRESET CLEAR CLOCK

J

K

a

a

L

H

X

X

X

H

H.

L

X

X

X

L

H

L

L

X

X

X

H'

H'

H

H

Jl..

L

L

00

00

H

H

H

L

H

L

H

H

Jl..
Jl..

L

H

L

H

H

H

J1..

H

H

L

GND

SN54H78(J,W) SN74H7B(J,N)

TOGGLE

See pages 6-50 and 6-54
'LS78A
FUNCTION TABLE
INPUTS

•

OUTPUTS

a

PRESET CLEAR CLOCK

J

K

a

L

H

X

X

X

H

H

L

X

X

X

L

H
H'

00

L

L

L

X

X

H'

H

H

I

L

L

00

H

H

I

H

L

H

L

H

H

I

L

H

L

H

H

H

I

H

H

TOGGLE

H

H

H

X

X

00

X

vcc
SN54L78(J,T) SN74L78(J,N)
·SN54LS78A(J,W) SN74LS78A1J,N)

00

See page 6-56
GATED FULL ADDERS

80

GATED COMPLEMENTARY INPUTS
COMPLEMENTARY SUM OUTPUTS

FUNCTION TABLE
(See Notes 1, 2, and 3)

INPUTS

en

B

L
L L
L H
L H
H L
H L
H H
H H
H = high
L

OUTPUTS

A

Cn +1

1:

L

H

H

L

H
L
H

H
H
L
H
L
L
L

L
L
H

H

1:

SN5480(J) SN74BO(J,N)

H

L
L H
L
H L
H
L
H L
H
L H
level. L - low level

NOTES: 1, A = Ac + A*+ A1'A2, B = Bc + B* + B1'B2_
2_ When A* is used as an input, A1 or A2 must be low. When B* is
used as an input, B1 or B2 must be low.
3_ When A 1 and A2 or B1 and B2 are used as Inputs, A* or B*,
respectively, must be open or used to perform dot-AND logic.
SN5480(W)

See page 7-41

See explanation of function tables on page 3-8_
·Thls configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.

8

5·24

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VI EWS)
16-BIT RANDOM-ACCESS MEMORIES

ADDRESS WRITE
X4

1

SENSE
WRITE ADDRESS
~ GND
0
V4

81

~Vcc~
ADDRESS

ADDRESS

See page 7-44
SN5481A (J. W) SN7481A (J. N)

2-BIT BINARY FULL ADDERS

82

SN5482 (J. W) SN7482 (J. N)

See page 7-49

NC-No internal connection

4-BIT BINARY FULL ADDERS WITH FAST CARRY

GNO

B1

Vee

12

III

83

SN5483A (J. W)
SN54LS83A (J. W)

See page 7-53

WRITE

16-BIT RANDOM-ACCESS MEMORIES

SENSE

SN74 83A (J. N)
SN74LS83A (J. N)

WRITE

~~GND~

84

~VCCY1~

ADDRESS

See page 7-44

SN5484A (J. W)

ADDRESS

SN7484A (J. N)

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

5-25

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
4-BIT MAGNITUDE COMPARATORS

INPUTS

OUTPUTS

INPUTS

VCC~~.~

85

82
A2
A-B
A>B A B"A> B A:B A-sfil74181 (J, NI

See page 7-271

SN54LS181 (J, WI
SN54S181 (J, WI

SN74lS181 (J, NI
SN74S181 (J, NI

LOOK-AHEAD CARRY GENERATORS

182

I

SN54182 (J, WI
SN54S182 (J, WI

See page 7-282

SN74182 (J, NI
SN74S182 (J, NI

DUALCARRY~AVEFULLADDERS

183

See page 7-287

SN54lS183 (J, WI
SN54H183 (J, WI

SN74LS183 (J. NI
SN74H183 (J, NI

CODE CONVERTERS
CASCADEABLE TO N-BITS

184

BCD-TO-BINARY

185

BINARY-TO-BCD

See page 7-290

SN54184 (J, WI
SN54185A (J, WI

SN74184 (J, NI
SN74185A (J, NI

1076

5-4B

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE nL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
512·BIT PROGRAMMABLE READ-ONLY MEMORIES

186

648·BITWORDS
OPEN-COLLECTOR OUTPUTS

SN54186 (J, WI

For more information contact the factory

SN74186 (J, NI

NC - No internal connection

1024·BIT READ·ONLY MEMORIES

187

256 4-BIT WORDS
OPEN-COLLECTOR OUTPUTS

SN54187 (J, WI

For more information contact the factory

SN74187 (J, NI

•
I

256·BIT PROGRAMMABLE READ-ONLY MEMORIES

188

32 8·BIT WORDS
OPEN-COLLECTOR OUTPUTS

SN54S188 (J, WI

SN74S188 (J, NI

(Redesignated TBP18SA0301

See Bipolar Microcomputer Components Data Book, second edition.

64·BIT RANDOM·ACCESS MEMORIES

189

164-BIT WORDS
THREE-STATE OUTPUTS

See Bipolar Microcomputer Components Data Book, second edition.

SN54S189 (J, WI

SN74S189 (J, NI

181

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

5·49

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
SYNCHRONOUSU~DOWNCOUNTERS

i?:1~2S '---D'''''T'-O-'T--'
A

190

BCD

191

BINARY

DB

CLOCK CLOCK

0A

8

C

ENABLE DOWN/
G
UI'

0

Uc

=~~~
See page 7 ·296

SN54190 (J, WI
SN54LS190 (J, WI
SN54191 (J, WI
SN54LS191 IJ, WI

SN74190 (J, NI
SN74LS190 (J, NI
SN74191 (J, NI
SN74LS191 (J, NI

SN54192 (J, WI
SN54L 192 (JI
SN54LS192 (J, WI
SN54193 (J, WI
SN54L 193 (JI
SN54LS193 (J, WI

SN74192 (J, NI
SN74L 192 (J,NI
SN74LS192 (J, NI
SN74193 (J, NI
SN74L 193 (J, NI
SN74LS193 (J, NI

SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS

•

192

BCD WITH CLEAR

193

BI NARY WITH CLEAR

See page 7·306

4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
VCC

194

QA

as

Oc

SN54194 (J, WI
SN54LS194A (J, WI
SN54S194 (J, WI

See page 7·316

00 CLOCK

S1

SO

SN74194 (J, NI
SN74LS194A (J, NI
SN74S194 (J, NI

B,

5·50

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

54n4 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENTS (TOP VIEWS)
4-BIT PARALLEL-ACCESS SHIFT REGISTERS

195

Q.A,

08

ac

00

aD

CLOCK

\3

~~
SERIAL INPUTS

PARALLEl INPUTS

SN54195 (J, WI
SN54LS195A (J, WI
SN54S195 (J, WI

See page 7-324

SN74195 (J, NI
SN74LS195A (J, NI
SN74S195 (J, NI

PRESETABLE COUNTERS/LATCHES

196

DECADE/BI-QUINARY

197

BINARY

I
ac

~

QA

DATA INPUTS

SN54196 (J, WI
SN54LS196 (J, WI
SN54S196 (J, WI
SN54197 (J, WI
SN54LS197 (J, WI
SN54S197 (J, WI

See page 7-331

SN74196 (J, NI
SN74LS196 (J, NI
SN74S196 (J, NI
SN74197 (J, NI
SN74LS197 (J, NI
SN74S197 (J, NI

8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

198

lEFT

SERIAL INPUT
S1

See page 7-338

INPUT

H

<

:x>

(J)

PARAMETER

m o Z_

~8z
~~(J)

TEST

SERIES 54

SERIES 54H

SERIES54L

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74H

SERIES 74L

SERIES 74LS

SERIES 74S

'00, '04,

'HOO, 'H04,

'LOO, 'L04,

'10, '20, '30

'Hl0, 'H20, 'H30

'L 10, 'L2O, 'L30

TEST eONDITIONSt

FIGURE

'LSOO,

'SOO, 'S04,

'LS04, 'LS10,

'S10, 'S20,

'LS20, 'LS30

'S30, 'S133

VIH

High-level input voltage

1,2

~C

VIL

Low-level input voltage

1,2

;;0
03::

VIK

I nput clamp voltage

[TI

VOH

High-level output voltage

Z
-i

VOL

(J)

2

IUNIT

IIH

maximum input voltage
High-level input current

I

I

154 Family

0.8

0.8

0.7

0.7

0.8

74 Family

0.8

0.8

0.7

0.8

0.8

-1.5

-1.5

-1.5

2.4

3.4

2.4

3.5

2.4

3.3

2.5

3.4

2.5

3.4

IOH = MAX

74 Family

2.4

3.4

2.4

3.5

2.4

3.2

2.7

3.4

2.7

3.4

Vee = MAX

0.2

0.4

0.2

0.4

0.15

0.3

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.2

0.4

0.25

0.5

0.51

Series 74LS

Low-level input current

IVee= MAX

m

ICC

output current.
Supply current

T

1vee = MAX

20

-2

I

50

-55

-40

-100

-3

-15

-20

-100

-40

-100

74 Family

-18

-55

-40

-100

-3

-15

-20

-100

-40

-100

mA

= 5 V, T A = 25°C,

§ I, = -12 mA for SN54'/SN74', -8 mA for SN54H'/SN74H', and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S',
+Not more than one output should be shorted at a time, and for SN54H'/SN74H', SN54LS'/SN74LS', and SN54S'/SN74S', duration of short-circuit should not exceed 1 second,

o

-.J

o
~

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee

rC

-2
-20

See table on next page

o

m

I mA

-0.4

54 Family
Vee- MAX

3:
I

Jl.A

-0.18
-1.6

o

.."

VIH = 2.7 V

IVIL=O.4V

=i

=
~

V

mA

VIL = 0.5V
Short-circuit
lOS

:E

10

50

=
m

V

0.1
40

VIH = 2.4 V

z
<

m

~

0.1

VI = 7V
Vee= MAX

en

=
en

0.4

VI = 5.5 V

C')

!i
m

V

V

54 Family
IOL = MAX

VIL = 0.3 V
IlL

-1.2

II = ~

a

~

V

2

VIL - VIL max, 54 Family

10L =4 mA
II

2

Vee = MIN,

VIH = 2 V
Input current at

2

Vee= MIN,

Vee = MIN,

Low-level output voltage

2

>
Z

a

MIN Typi MAX MIN TYP+ MAX MIN TYPt MAX MIN TYP+ MAX MIN TYP+ MAX

0-i

Z

>
z

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

-J

[TI

In

16

<
m

UNIT

.."

C

~

en

~

m

supply current~

switching characteristics_at Vee

= 5 V, TA = 25°e

ICC (rnA)
TYPE

ICCH ImA)

ICCllmA)

Total with outputs high

Total with outputs low

TYP

MAX

TYP

Average per gate
150% duty cycle)

MAX

TYP

4

8

12

22

2

'00, '10

'04

6

12

18

33

2

'04, '20

'10

3

6

9

16.5

2

'20

11

'HOO

2

'H04

26

40

58

4.5

19.5

30

4.5

'H2O

5

8.4

13

20

4.5

'H30

2.5

4.2

6.5

10

4.5

'LOO

0.44

0.8

1.16

2.04

0.20

0.66

1.2

1.74

3.06

0.20

. . ><

'L10

0.33

0.6

0.87

1.53

0.20

'L20

0.22

0.4

0.58

1.02

0.20

SN54L30

0.11

0.33

0_29

0.51

0.20

SN74L30
'LSOO

0.11

0_2

0.29

0_51

0_20

~

>
(J)

~
o'" -z_

~8z
~~(J)

. 0....,

0_8

1.6

2.4

4.4

0.4

'LS04

1.2

2.4

3.6

6_6

0.4

'LS10

0.6

1.2

1.8

3.3

0.4

;;0

'LS20

0.4

0.8

1.2

2.2

0.4

'LS30

0.35

0_5

0.6

1.1

0.48

'SOO

10

16

20

36

3.75

o~

'504

15

24

30

54

3_75
3.75

~c:

5.9

2

'L04

[TI

15

4.5

,,-1
g

8

6

12.6

[TI

'510

7.5

12

15

27

Z
....,

'520

5

8

10

18

3.75

'S30

3

5

5.5

10

4.25

(J)

'S133

3

5

5_5

10

4_25

MAX

22

40

16

TYP

13

3

7.5

MIN

'30

26

'Hl0

MAX

22

2

'H04

TYP

22

16.8

6

~

high-to-Iow-Ievel output

low-to-high-Ieveloutput
11

1

4

tPHL Ins)
Propagation delay time,

12

10

2

'30

CONDITIONS#

tpLH Ins)
Propagation delay time,
MIN

'00

'HOO

TEST

TYPE

CL=15pF,

RL=400n

15
15

10

62

10

10

a5

10

10

~

10

o
en
~

<
m
I

'Hl0

CL=25pF,

RL=280n

5.9

'H2O
'H30
'LOO, 'L04,
'L10, L20

CL=50pF, RL=4kH

'L30

10

7

10

6.8

10

&9

12

35

60

31

W

35

60

m

100

15

10

15

15

13

~

'LSOO, 'LS04
'LS10, 'LS20

CL=15pF, RL=2kn

'LS30
'SOO, 'S04

CL=15pF,

RL=280n

'S10, 'S20

CL = 50 pF,

RL = 280 n

'S30, 'S133

CL=15pF,

RL=280n

CL=50pF,

RL=280n

4.5

Z

=
C")

!i
m
en

z>

=

4.5
~5

z

~5

5.5

Z
l>

<
m

#Load circuits and voltage waveforms are shown on pages 3-10 and 3-11 .

=
.....
m
=
en
:IE

~-

~ Maximum values of I CC are over the recommended operating ranges of V CC and T A; typical values are at V CC = 5 V, T A = 25° c_

==
.....

schematics (each gate)

o

.....
m

3:

~--------

I

tt~-=====::
-t-l-ti----"*-r
I

I

~

o

.m

,

-t~-ti:---,..1

...!.....l- ... -I--I-~--II-1

ti-tti-t..~J

'00. '04. '10. '20. '3D

'00, '04, '10, '20, '30
'LOO, 'L04, 'L 10, 'L20, 'L30, CIRCUITS
Input clamp diodes not on
SN54L'/SN74L' circuits.

'HOO, 'H04, 'H10, 'H20, 'H30 CIRCUITS

The 12-k!1 resistor is not on 'LS30.
Resistor values shown are nominal and in ohms.

C"I

W

•

'LSOO, 'LS04, 'LS10, 'LS20,
'LS30 CIRCUITS

11

M-1iiHiHiiin

I1

'SOO, 'S04, 'S10, 'S20,
'S30, 'S133 CIRCUITS

o

C

.....
~

C

.....
en

•

en
J:,.

recommended operating conditions
54 FAMILY
74 FAMILY

T

=e-a

SERIES 54

SERIES 54H

SERIES 54L

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74H

SERIES 74L

SERIES 74LS

SERIES 74S

'01, '03,

'HOI,

'LS01, 'LS03,

'SOl,

'OS, '12, '22

Supply voltage, Vee

NOM

'HOS, 'H22
MAX

MIN

54 Family

4.5

5.5

4.5

74 Family

4.75

5.25

4.75

MIN

I
I

High·level outpUt voltage, VOH

I
I

Low-level output current, IOL

I

Operating free-air temperature. TA

'L01, 'L03

54 Family
74 Family

NOM

MAX

MIN

NOM

5.5

4.5

5

5.25

4.75

5

'LS05, 'LS12, 'LS22
MAX

MIN

NOM

5.5

4.5

5

5.25

4.75

5.5

5.5

5.5

16

20

2

16

20

I UNIT

'S05, 'SZ2

MAX

MIN

NOM

MAX

5.5

4.5

5.5

5.25

4.75

5.25

-55

125

-55

125

-55

125

0

70

0

70

0

70

V

~~
~ mA

5.5

3.6

54 Family
74 Family

e
-4 en

20

-55

125

I

-55

125

701

'c

70

-i
"0 !TI
~

><
):-

~ (J)
m o z_

PARAMETER

~8z
~~(J)
'0-l

TEST

TEST eONDITIONSt

FIGURE

MIN
High·level
VIH

input voltage
Low-level

g~;o

VIL

E ~c:

~o~

VI'K

!TI
~
... Z
-l
'"'" (J)

IOH

input voltage
Input clamp

voltage
High·level

)(

UI

output current
Low-level

VOL

ou tpu t vol tage

I

1,2

input current
Low-level

IlL

input current

SERIES 54L

SERIES 74H

SERIES 74L

'01, '03,

'HOI,

'05, '12, '22

'HOS, 'H22

TYPt

MAX

MIN

TYPt

'L01, 'L03
MAX

MIN

TYPt

0.8

Vee: MIN,

II: §
VIL: VIL max,

Vee: MIN,

IIOL: MAX

VIH=2V

IIOL=4mA

VOH:5.5V

0.8

0.6

0.8

0.8

0.6

-1.5

-1.5

Supply current

SERIES 74S
'SOl,

'LS05, 'LS12, 'LS22

'S05, 'SZ2

MIN

TYPt

MAX

MIN

TYPt

I UNIT
MAX

250

250

0.7
0.8

50

0.81
0.8

-1.5

-1.2 I

I

100

250

0.2

0.4

0.2

0.4

0.15

0.3

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.2

0.4

0.35

0.5

0.5 I

0.25

0.4

Series 74LS

VIH =2.4V

Vee = MAX

V
"A

V

0.1
40

50

10

VIH: 2.7 V

20J

VIL: 0.3 V
Vee = MAX

V

mA
VI =7 V

Vee' MAX

V

0.1

VI·5.5V
Vee ·MAX

VIL=0.4V

"A

50

-0.18
-1.6

-2

-0.41

I
See table on next page

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°e.
§ II = -12 rnA for SN54'/SN74', -8 rnA for SN54H'/SN74H', and -18 rnA for SN54LS'/SN74LS' and SN54S'/SN74S'.

~

SERIES 54S

SERIES 74LS
'LS01, 'LS03,

54 Family

VIL = 0.5 V
ICC

MAX

SERIES 54LS

I
54 Family
74 Family

Vee: MIN,

High·level
IIH

SERIES 54H

SERIES 74

n>

Z
e~CI

~
me')

n>
-4-4
em

e>

1,2

Input current

at maximum
input voltage

SERIES 54

Z
'
.Z

:a en

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
~

:z::e~
-a<
mm

mA

-2
I

mA

Z
c-4C1
-a Z
C
-4<
enm
:a
-4
m

:a
en

~

schematics (each gate)

supply current~

TYPE Total with outputs high
TYP
'01

a

-1
!T1
><

~

~

n
m
OJ

>

_(J)

o z
x
~

n0
~ (J)

z

~
~ ~ ..;
~ >;:0

:: ~ c:::

~ c, ~
~

G;
U1

'"

m

U1

!T1

Z
..;

(J)

4

MAX
8

Total with outputs low

(50% duty cycle)
TYP

12

22

2

22

2

'03

4

8

12

'05

6

12

18

33

2

'12

3

6

9

16.5

2

'22

2

4

6

11

2

'HOl

10

16.8

26

40

4.1

'H05

16

26

40

58

4.67

OUTPUT Y
OUTPUT V

:t •

--

5

8.4

13

20

4.1

'LOl

0.44

0.8

1.16

2.04

0.20

INPUTS

'L03

B

0.44

0.8

1.16

2.04

0.20

'LSOl

0.8

1.6

2.4

4.4

0.4

'LS03

0.8

1.6

2.4

4.4

0.4

'LS05

1.2

3.6

6.6

0.4

'LS12
'LS22

0.7
0.4

2.4
1.4
0.8

1.8
1.2

3.3
2.2

0.42

OA

6

13.2

20

36

3.25

'S05

9

19.8

30

54

3.25

'S22

3

6.6

10

18

3.25

'OS
'12, '22

""foff--...L ...

I
I
I

1 I
I I
1 I
II
II
II
I I
II
1 I
*1

•

I

*_

I
I

*1

I~

I" i

v

."

o
en
=t

-m
-I

1

::z:z

'LS05 CI RCUITS

0>

."Z
tPLH (ns)

tpHL (ns)
Propagation delay time,

low·to-high-Ievel output

400 n for tPHL

TYP

MAX

TYP

MAX

35

45

8

15

40

55

8

15

35

45

8

15

10

15

7.5

12

60

90

33

60

CL = 15 pF, RL = 2 kn

17

32

15

28

5

7.5

4.5

7

CL=50pF, RL=280n

2

7

7.5

-----

Vee

high-to-Iow-Ieveloutput
MIN

CL=50pF, RL=4kn

2

m=
ZC')

I

Propagation delay time,

CL=15pF, RL=4knfortpLH,

CL=15pF, RL=280n

OUTPUT

V--

GND

CL=25pF, RL=280n

'S03, 'S05, 'S22

J.

=E<

•

'L01, 'L03
'LS05, 'LS12, 'LS22

:

GND

'H01, 'H05, 'H22
'LS01, 'LS03,

OUT UT

.....

:*

•

Vee

20k! tk

'LS01, 'LS03, 'LS12, 'LS22 CI RCUITS

MIN

--

--

OUTPUT
y

e D -

'>

n-l

Om
~en

m>
~z

0=

=O~

em
'S03, 'S05, 'S22 CIRCUITS
Resist.,r values shown are nominal and in ohms.

-1=
"'-1
em
-1=

en en

#Load circuits and voltage waveforms ara shown on pages 3-10 and 3-11,

en

u..

.,-,.....-:
II

e-

switching characteristics at Vee = 5 V, TA = 25°e

'01, '03

'L01, 'L03 CIRCUITS

vee

17k

values of lee are over the recommended operating ranges of Vee
and T A; typical values are at Vee = 5 V, T A = 25°e.

TEST CONDITIONS#

GND

A-

11 Maximum

TYPE

GND

'01, '03, '05, '12, '22, 'H01, 'H05, 'H22 CI RCUITS

'H22

'S03

Vee

- .
>

Average per Gate

MAX

TYP

Vce

ICC (rnA)

ICCL (rnA)

ICCH (rnA)

II

OPEN-COLLECTOR OUTPUT APPLICATION DATA
APPLICATION DATA
combined fan-out and wire-AND capabilities
The open-collector TTL gate, when supplied with a proper load resistor (RU, may be paralleled with other similar TTL
gates to perform the wire-AND function, and simultaneously, will drive from one to nine standard loads of its own
series. When no other open-collector gates are paralleled, this gate may be used to drive ten loads. For any of these
conditions an appropriate load resistor value must be determined for the desired circuit configuration. A maximum
resistor value must be determined which will ensure that sufficient load current (to TTL loads) and off current (through
paralleled outputs) will be available while the output is high. A minimum resistor value must be determined which will
ensure that current through this resistor and sink current from the TTL loads will not cause the output voltage to rise
above the low level even if only one of the paralleled outputs is sinking all the currents.
In both conditions (low and high level) the value of RL is determined by:
RL

= VRL
IRL

where VR L is the voltage drop in volts, and I R L is the current in amperes.

high-level (off-state) circuit calculations (see figure A)
The allowable voltage drop across the load resistor (VRL) is the difference between Vee applied and the VOH level
required at the load:
VRL

= Vee - VOH min

The total current through the load resistor (I R L) is the sum of the load currents (II H) and off-state reverse currents
(lOH) through each of the wire-AND-connected outputs:
IRL

II

= 1). IOH + N • IIH to TTL loads

Therefore, calculations for the maximum value of RL would be:
Vee - VOH min
RL(max)

= 1). IOH + N ·IIH

where 71 = number of gates wire-AND-connected, and N = number of standard loads.

TTL LOADS

Calculation:

IIH

'-v--'

Vcc - VOH min
IOH + N - IIH

RL(max)

= 11 -

RL(max)

=

5 - 2.4

2.6

0.001 + 0.00012

n = Q.(i(i1"i2 n =

2321

n

Values shown are for Series 54174 standard inputs and outputs. For
devices in other series, substitute appropriate values.

N=3

N • II H

= 3 • 40 j.tA

'OH

'-v--'
1)=4

11 • IOH

= 4· 250·j.tA

FIGURE A-HIGH-LEVEL CIRCUIT CONDITIONS

107

6-6

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

OPEN-COLLECTOR OUTPUT APPLICATION DATA
APPLICATION DATA
low-level (on-state) circuit calculations (see figure B)
The current through the resistor must be limited to the maximum sink current of one output transistor. Note that if
several output transistors are wire·AND connected, the current through R L may be shared by those paralleled
transistors. However, unless it can be absolutely guaranteed that more than one transistor will be on during low-level
periods, the current must be limited to the recommended maximum IOL, the maximum current which will ensure that
the low-level output voltage, VOL, will be below VOL max.
Also, fan-out must be considered. Part of IOL will be supplied from the inputs which are being driven. This reduces the
amount of current which can be allowed through R L.
Therefore, the equation used to determine the minimum value of R L would be:
R

. _
VCC-VOLmax
L(mln) - IOL capability - N • II L

Calculation:

VCC-VOL max
RL(min)

IOL capability -

5 - 0.4
RL(min) = 0.016 _ 0.0048

N • IlL

n

=

4.6
0.0112

n

=

410

n

Values shown are for Series 54/74 standard inputs and outputs. For
IlL

~

devices in other series, substitute the appropriate values.

II'
I

N=3

'N • II L

= 3 • 1.6 mA

~
MAXIMUM IOL CAPABILITY
OF ONE OUTPUT = 16 mA

tCurrent into OFF outputs is negligible at the low logic level.

FIGURE B-LOW-LEVEL CIRCUIT CONDITIONS

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXA.S 75222

6-7

II

en

Co

."
Q

recommended operating conditions
54 FAMILY

SERIES 54

SERIES 54L

SERIES 54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74L

SERIES 74LS

SERIES 74S

'02

Supply voltage, Vee
High-level output current, 10H
. Low-level output current, 10L
Operating free-air temperature, T A
'-

---

--

-

MIN

NOM

54 Family

4.5

5

74 Family

4.75

5

'25, '27
MAX MIN
5.5

NOM

4.5

5

5.25 4.75

5

'L02
MAX MIN
5.5

5

5.25 4.75

5

'S02, 'S260

'LS02, 'LS27

NOM

4.5

MAX MIN

NOM

4.5

5

5.25 4.75

5

5.5

en

UNIT

MAX MIN

NOM

MAX

4.5

5

5.5

5.25 4.75

5

5.5

5.25

54 Family

-400

-800

-100

-400

-1000

74 Family

-400

-800

-200

-400

-1000

54 Family

16

16

2

4

20

74 Family

16

16

3.6

8

20

54 Family

-55

74 Family

0

125 -55
70

125 -55

0

70

125 -55

0

70

125

-55

125

70

0

70

0

~

;:
m
I

V

Z
Q

"A

:::D
C')

mA

~

°e

en

m

~

~

=i

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

:

[TI

><

'"

III

>

-

TEST

PARAMETER

TEST eONDITIONSt

FIGURE

(J1

o z_

SERIES 54

SERIES 54L

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74L

SERIES 74LS

SERIES 74S

'02, '25, '27

'L02

'LS02 'LS27

'S02, 'S260

MIN TYP~

~8Z
~~(J1
. 0-l

;;0
~c

as:;:

VIH

High-level input voltage

1,2

VIL

Low-level input voltage

1,2

VIK

Input clamp voltage

3

VOH High-level output voltage

1

[TI

Z

VOL

Low-level output voltage

2

-l

2

Input current at

II

4

maximum input voltage
High-level

IIH

input current

Low-level
IlL

4

0.8

-1.5

Vee = MAX

Vee = MAX

3.2

2.7

3.4
3.4

-1.2
2.5

3.4

2.7

3.4

0.3

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.35

0.5

0.5

0.25

0.4

Series 74LS
VI = 5.5 V

1

1

0.1

VI = 7 V

0.1
40

VIH = 2.4 V

Supply current

6

Vee = MAX

7

Vee = MAX

m
~

V

."

I

V

160
50

-0.18
-0-4

-1.6

VIL = 0.4 V

mA

-6.4
-2

54 Family

-20

-55

-3

-15

-20

-100

-40

-100

74 Family

-18

-55

-3

-15 -20

-100

-40

-100

See table on nex t page

mA
mAl

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC

§ II

=5

V, T A

= 26°C_

= -12 mA for SN54'/SN74' and -18 mA for SN54LS'/SN74LS' and SN54S/SN74S'.

+Not more than one output should be shorted at a time, and for SN54LS'/SN74LS' and SN54S'/SN74S', duration of output short-cIrcuit should not exceed one second.

8

~

m
Q

-t

."

C

mA

"A
20

Q

C

V

10

VIL = 0.5 V

output current·

V

V

0.15

VIL=0.3V
5

2.5

0.4

All inputs
Data inputs

2.4

3.3

0.2

VIH=2.7V

input current Strobe of '25

-1.5
2.4

54 Family

All inputs

Short-circuit

lee

0.8

0.8

3.4

All inputs
lOS

0.7

0.7

2.4

Data inputs
Strobe of '25

0.7

0.8

74 Family

/IOL = 4 mA

2

0.8

3.4

Vee = MAX

2

UNIT

MAX

74 Family
2.4

10H = MAX

MAX MIN TYP~

54 Family

Vee = MIN, VIL = VIL max, 54 Family

Vee = MIN,IIOL = MAX

MAX MIN TYP~

2

Vee = MIN, 11= §

VIH = 2 V

(J1

MAX MIN TYP~

-t
Q
-t

-t

en

~

supply current~
TYPE

-i

C5

~

tTl

><
3
n >
_00

schematics (each gate)

ICCH (mAl

ICCL (mAl

Total with outputs high

Total with outputs low

MAX

TYP

MAX

8

16

14

27

2.75

'25

8

16

10

19

2.25

'27

10

16

16

26

4.34

0.8

1.6

1.4

2.6

0.275

1.6

3.2

2.8

5.4

0.55

'LS27

2.0

4

3.4

6.8

0.9

'S02

17

29

26

45

5.38

Z

'02

:>

'25

CONDITlONS#

~

(;,

'"
'"'"

tTl

Z
..;
00

CL=15pF,

RL = 400.11

CL=50pF, RL=4k.l1

'LS02, 'LS27 CL=15pF,
'S02
'S260

tpLH (nsl

tpHL (nsl
Propagation delay time,

TYP

MIN

TYP

12

22

8

15

13
10

22

8

15

15

7

11

31

60

35

60

10

15

10

15

3.5

5.5

3.5

5.5

CL=50pF,

RL = 280.11

5

RL:- 280.11

4

15 pF,

-=mZ,

MAX

RL = 280.11

RL=2k.l1

~

high-to-Iow-Ievel output

MAX

CL=15pF,
~-

"U
Q
U)

'25 CIRCUITS

low-to-high-Ieveloutput

'27
'L02

'02, '27 CIRCUITS

Propagation delay time,
MIN

~ ~ ..;

~ ~
.(;, c ~

The portion of the schematic within the dashed
lines is repeated for the e input of the '27.

= 5 V, T A = 25° C

TEST

TYPE

Z

tJ
c:::

OUTPUT
y

'S260
17
29
45
10.75
26
~Maximum values of lee are over the recommended operating ranges of Vee
and T A; typical values are at V CC = 5 V, T A = 25° c.

§ ~ 00

i:

y

'LS02

("j_

::3 0

OUTPUT

'L02

switching characteristics at Vee

Vee

TYP

TYP

m

x

Vee

(50% duty cyclel

'02

CD

0

ICC (mAl
Average per gate

Resistor values are nominal and in ohms.

4

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.
The portion of the schematic within the dashed
lines applies only to the 'LS27

C")

U)

Vcc

,jlf

~

~

=

6
A

-4

V,"-c
OUTPUT

Y

IN~JTS

:II

!t
m

5
5.5

Q

Q

-4
m

:I:
,

t:

"U
Q

L---,__

~

OU~UT

~~-----~-~---GND

m
Q

GND

'L02 CIRCUITS

'LS02, 'LS27 CIRCUITS

C'l

cb

II

The portion of the schematic within the dashed
lines is repeated for each additional input of the
'S260, and the 0.9-k.l1 resistor is changed to
0.6 k.l1.

C

-4
"U

C

-4

'S02, 'S260 CIRCUITS

U)

•

~

CI

recommended operating conditions

-a
en
::=i

Q

54 FAMILY

SERIES 54

SERIES54H

SERIES54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74H

SERIES 74LS

SERIES 74S

'O.S,

'LSOS,

'H11, 'H21

UNIT

'SO.S, 'S11

'LS11, 'LS21

54 Family

4.5

5

5.5

4.5

5

174 Family

4.75

5

5.25

4.75

5

. Operating free-air temperature, T A

C3

~

~
~

5

5.5

5

5.25

5.5

-50.0.

-40.0.

-10.0.0.

20.

4

20.

74 Family

16

20.

8

20.

54 Family

-55

125

-55

125

-55

125

-55

125

74 Family

0.

70.

0.

70.

0.

70.

0.

70.

>
(J)

PARAMETER

V
JJA
mA
°e

TEST

SERIES 54H

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74H

SERIES 74LS

SERIES 74S

'O.S

'H11, 'H21

TEST CONDITIONSt

'LSOS, 'LS11,

UNIT

'SDS, 'S11

~ ~-l

1,2

::

1,2

~ >;0

c:

~
~ c ~

VIL

Low-level input voltage

VIK

Input clamp voltage

3

~
~

VOH

High-level output voltage

1

VOL

Low-level output voltage

2

tTl

Z

-l

2

Vee= MIN,

II = §

Vee= MIN,

VIH = 2 V,

10H = MAX
Vee = MIN, I'0L = MAX

(J)

VIH = 2V
Input current at
II
IIH
IlL

maximum input voltage
High-level input current
Low-level input current
Short circuit

lOS

output current.

4
4
5
6

Vee = MAX
Vee= MAX
Vee = MAX
Vee = MAX

tlOL =4 mA

2

2

2

O..S

0..8

0..7

0..8

74 Family

0..8

0..8

0..8

0..8

-1.5

-1.5

-1.2

54 Family

2.4

3.4

2.4

3.4

2.5

3.4

2.5

3.4

74 Family

2.4

3.4

2.4

3.4

2.7

3.4

2.7

3.4

54 Family

0..2

0..4

0..15

0..3

0..25

0..4

0..5

74 Family

0..2

0..4

0..2

0..4

0..35

0..5

0..5

0..25

0..4

Series 74LS
VI = 5.5 V

1

1

1

0..1

VI = 7V
VIH=2.4V

40.

50.

-1.6

-2

20.

VIH = 2.7 V
VIL = 0..4 V

50.

-0..4

-2

VIL=0.5V
54 Family

-20.

-55

-40.

-10.0.

-20.

-10.0.

-40.

-10.0.

74 Family

-18

-55

-40.

-100.

-20.

-10.0

-40.

-100

Supply current
7
See table on next page
Vee = MAX
lee
tFor conditions shown as MI N or MAX, use the appropriate values specified under reconmended operating conditions.
:j:AII typical values are at VCC = 25°C.
§ II = -12 mA for SN54'/SN74', -8 mA for SN54H'/SN74H', and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S'•
• Not more than one output should be shorted at a time, and for SN54H'/SN74H', SN54LS'/SN74LS' and SN54S'/SN74S',
duration of output short circuit should not exceed one second.

00

V

154 Family

-1.5

~

-t
Q
-t
m
~
I

MIN TYP:j: MAX MIN TYP:j: MAX MIN TYP:j: MAX MIN TYP:j: MAX
High-level input voltage

~

m

en

=

'LS21
VIH

CJ

m

=i

SERIES 54

FIGURE

~ ~ (J)

~

4.5

5.25 4.75

16

!TI

~ ~­
:::l 0 Z

u:

5

-80.0.

><

_

5

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

....,

~

5.5

54 Family

High-level output current, 10H
Low-level output current" IOL

4.5

5.25 4.75

m
I

>
iZ

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply Voltage, Vee

;:

V
V

-a
Q

r-

m
Q

c:

V

-t

V

c:
-t
en

mA
IJA
mA
mA
mA

-a

o-.J

en

supply current~

TYPE

schematics (each gate)

ICCH (rnA)
Total with outputs high
TYP

,,~
[TI

g
-t

~

~

><

ICCl (rnA)
Total with outputs low

MAX

(50% duty cycle)

TYP

MAX

TYP

'08

11

21

20

33

3.88

'H11

18

30

30

48

8

'H21

12

20

20

32

8

'LS08
'LS11

2.4

4.8
3.6

4.4

8.8

0.85

3.3

6.6

0.85

'lS21

1.2

2.2

4.4

0.85

'508

18

2.4
32

32

57

6.25

'Sll

13.5

24

42

6.25

1.8

24

-

- -

Vee

ICC lmA )
Average per gate

OUTPUT
Y

'08 CIRCUITS
vee

~ Maximum values of ICC are over the recommended operating ranges of. V CC
INPUTS

and T A; typical values are at V CC = 5 V, T A = 25° C.

A

OUTPUT

'III

Y

I~

>
switching characteristics at Vee

~c:

TYPE

o~

Z
"'"'I
(f1

m

'H11, 'H21 CIRCUITS

;;0
rT1

C)

en
=i

:;:

(f1

am -z_

~8Z
~;(f1
• 0"'"'1

""D

TEST
CONDITlONS#

Vee

= 5 V, TA = 25°e
tplH Ins)
Propagation delay time,

C

tpHL Ins)
Propagation delay time,

low-to-high-Ievel output
MIN

C")
IN~UTS

high-to-Iow·level output

TYP

MAX

MIN

TYP

MAX

'08

CL=15pF,

RL = 400 n

17.5

19

CL=25pF,

RL = 280 n

7.6

27
12

12

'H11, 'H21

8.8

12

'LS08, 'LS11
'LS21

CL=15pF,

RL=2kn

8

15

10

20

4.5

7

5

7.5

'S08, '511

CL=15pF, RL=280n
CL=50pF,

RL = 280 n

7.5

6

#Load circuit and voltage waveforms are shown on pages 3-10 and 3·11.

>
Z

.,~

+
oN •

OU~UT

~

m

en

:e
=i
:::c
-I

'LS08, 'LS11, 'LS21 CIRCUITS

-"--"--J:__

Vee

C)

-I

m

3:
I

OUTPUT

y

""D
C)
p-

m

Q

'508, '511 CIRCUITS
Resistor values shown are nominal and in ohms.

~

.....

II

C
-I
""D
C
-I

en

II

~

N

."

recommended operating conditions

Q

54 FAMILY

SERIES 54

SERIES54H

SERIES54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74H

SERIES 74LS

SERIES 74S

'09

'H15

'LS09, 'LS15

'S09, 'S15

en

=t

<
m
,

UNIT

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply Voltage, Vee

54 Family

4.5

5

5.5

4.5

5

74 Family

4.75

5

5.25

4.75

5

High·level output voltage, VOH

,,~
[TI

g

(J)

PARAMETER

ID -

o

5

5.5

5

5.25

5.5

5.5

5.5

20

4

20

16

20

20

8

-55

125

-55

125

-55

125

-55

125

74 Family

0

70

0

70

0

70

0

70

:z:-

z

V

a

=

V

!i
m

rnA

en
~

°e

=i

SERIES 54

SERIES54H

SERIES54LS

SERIES 54S

=

SERIES 74

SERIES74H

SERIES 74LS

SERIES 74S

."

'09

'H15

'LS09, 'LS15

'S09, 'S15

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

S :>
~

4.5
4.75

54 Family

><

-t

5.5
5.25

16

74 Family

Operating free·air temperature, T A

5
5

5.5

5.5
54 Family

Low·level output current, IOL

4.5

5.25 4.75

Z_

:8z

TEST

TEST CONDITIONSt

FIGURE

Q

m

UNI'

Z,

MIN TYP+ MAX MIN TYP+ MAX MIN TYP+ MAX MIN TYP+ MAX

~~(J)
• 0-1
~;o
~c:

VIH

High·level input voltage

1,2

VIL

Low·level input voltage

o~

VIK

Input clamp voltage

3

1TI

IOH

High·level output current

1

1,2

Z

-I

(J)

VOL

Low-level output voltage

2

4

maximum input voltage

IIH

Vee= MIN,

11- §

Vee- MIN,

VIH - 2 V,

High·level input current

2

VCC= MIN,

Vee = MAX

IOL =MAX

0.7

0.8

74 Family

0.8

0.8

0.8

0.8

-1.5

-1.5

-1.5

~1.2

250

250

100

250

54 FamilY

0.2

0.4

0.15

0.3

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.35

0.5

0.5

0.25

0.4

IOL=4mA Series 74LS
VI = 5.5 V

1

0.1

4

Vce= MAX

Low·level input current

5

Vee = MAX

IcC

Supply current

7

Vee= MAX

VIH - 2.4 V

40

50

-1.6

-2

VIL=O.4V

20

o

~

12 mA for SN54'/SN74', -8 mA for SN54H'/SN74H', and -18 mA for SN54LS'/SN74LS'.

50

-0.4
-2

VIL=0.5V

tFor conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
.

=-

1

See table on next page

Q
;

V
V
!LA

rr-

m

n
.....
Q

:a
Q

V

rnA

0.1

VIH = 2.7 V

n

V

2

0.8

VI = 7V

IlL

§ II

2

0.8

VOH = 5.5 V,

VIH =2V
I nput current at

II

2
54 Family

!LA
mA
rnA

c

.....
."
C
.....
en

o-.J

ClI

supply current~

schematics (each gate)
ICC (rnA)

TYPE

ICCH (rnA)

ICCl (rnA)

Total with outputs high

Total with outputs low

Average per gate
(50% duty cycle)

OUTPUT
Y

MAX

TYP

TYP

MAX
33

TYP
3.88

'09

11

21

20

'H15

15

25

30

48

7.5

'lS09

2.4

4.8

4.4

8.8

0.85

'lS15

1.8

3.6

3.3

6.6

0.85

'S09

18

32

32

57

6.25

42

5.75

'09 CIRCUITS
Vee

'515

24

19.5

10.5

."
Q

'-4)

~ Maximum values of ICC are over the recommended operating ranges of V CC

and T A; typical values are at V CC

=5

V, T A

INP~~

= 25" C.

=4

OUTPUT
y

<:
m

".....:j
~

[TI

. . ><

~

~

l>

;I>

m -

o z_

:8z

switching characteristics at Vee

. 0-i

TYPE

g~;o
~~c:

;;l

~

-i
(IJ

a

= 5 V, TA = 25°e

C)

~~(IJ

:03::
~ [TI
~ Z

z

'H15 CIRCUITS

(IJ

tplH (ns)

tpHl (ns)

TEST

Propagation delay time,

Propagation delay time,

CONDITIONS#

low-to-high-Ievel output

high-to-Iow-Ievel output

MIN

TYP

MAX

MIN

A,

INPUTS

TYP

MAX

'09

CL=15pF, RL=400n

21

32

16

24

'H15

CL=25pF, RL=280n

12

18

9

13

'lS09, 'LS15 CL=15pF, RL=2kn
'S09
'S15

CL=15pF, RL=280n

20

35

17

35

6.5

10

6.5

10

CL = 50 pF, RL = 280 n

9

CL=15pF, RL=280n

5.5

CL=50pF,

8.5

RL = 280 n

9
8.5

6

!f
m

j4.
r........---- OUr,:UT

I

~

=i

=
Q
."

m
Z

'lS09, 'lS15 CIRCUITS
9

I

n

8

'-------

en

Q

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

rrm

OUTPUT
y

n

-4

Q

='

c:;
C

-4

'509, '515 CIRCUITS
Resistor values shown are nominal and in ohms.

~.

w

II

."

C
-4

en

II
1

~
~

recommended operating conditions

SERIES 54

l54 FAMILY
74 FAMILY

SERIES 74
'14, '132

'13

T 54 Family

Supply voltage, Vee

I

74 Family

MIN

NOM

MAX

MIN

NOM

I
I

MAX

MIN

NOM

MAX

UNIT

'S132
NOM

MIN

MAX

5

5.5

4.5

5

5.5

4.5

5

5.5

4.5

5

5.5

5.25

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

-400

-800

16

54 Family

1 74 Family

Operating free-air temperature, TA

SERIES 74S

5

74 Family
54 Family

SERIES 74LS
'LS13, 'LS14, 'LS132

4.5

-800

I

SERIES 54S

4.75

Hig, level output current, 10H
Low-l evel ou tpu t cu rren t. I 0 L

SERIES 54LS

16

16

-1000

4

16

20

8

20

-55

125

-55

125

-55

125

-55

125

0

70

0

70

0

70

0

70

V
IlA

....,

2l
~

PARAMETER

IT!

><
3
n
>
_(J)

VT+
VT_

m
OJ

0

x

1"\

'" oZ

~(J)
~ 0-i

0

~;:o

~ ~c:::

.r;, o
.....
m

x

~

Z

'"0>

(J)

'"

I nput clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage
Input current at

IT+

I'TI

r;,

Negative-going threshold voltage

VIK

IT_

-i

positive-going threshold
Input current at
negative-going threshold

Input current at
maximum input voltage

IIH

t

High-level input current

SERIES 74

TEST eONDITloNst

'13

Vee = 5V

POSitive-going threshold voltage

Hysteresis (VT+-VT_)

z

TEST
FIGURE

8,9
3

MIN

TYP:j:

1.5

1.7

'14, '132
MAX

MIN

TYP:j:

1.5

1.7

1.1

0.6

0.9

0.4

0.8

MAX
1.1

SERIES 54LS

SERIES 54S

SERIES 74LS

SERIES 74S

'LS13, 'LS14, 'LS132
TYP:j:
MAX
MIN
1.9

MIN

'S132
TYP:j:

s::a

°e

;;ge')

1.6

1.77

1.9

1.1

1.22

1.4

0.4

0.8

0.2

0.55

0.9

0.4

0.8

54 Family

2.4

3.4

2.4

3.4

2.5

3.4

2.5

3.4

74 Family

2.4

3.4

2.4

3.4

2.7

3.4

2.7

3.4

11= §

Vee - MIN,

10H - MAX,

VI = VT_ min
Vee = MIN,

IIOL = MAX

VI = VT+ max

I 10L = 4 mA

-1.5

-1.5

-1.5

V
V

54 Family

0.2

0.4

0.2

0.4

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.35

0.5

0.5

0.25

0.4

Series 74LS

V
V
V

-1.2

VI = VT+

-0.65

-0.43

-0.14

-0.9

mA

Vee = 5 V.

VI = VT_

-0.85

-0.56

-0.18

-1.1

mA

Vee = MAX
Vee = MAX

IlL

Low-level input current

Vee = MAX

lOS

Short-circuit output current·

Vee - MAX

VI -5.5V
VI - 7 V

mA

0.1

VI = 2.4 V

40

40

VI - 2.7 V

20
-1

VIL-O.4V

-1.6

-0.8

50

-0.4

-1.2

VIL-0.5V

-2
-18

-55

-18

-55

-20

-100

-40

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

§II; -12 mA forSN54'/SN74' and -18 mA for 'LS13, 'LS14, 'LS132, and 'S132.
+Not more than one output should be shorted at a time, and for SN54LS'/SN74LS' and 'S132, duration of output short-circuit should not exceed one second.

Ie')

r-m
m:a

-100

..... en
-a c:::::!
..... <
enm
I

Z

:I>
Z
C

e')
V

Vee=5V,

fAil typical values are at Vee; 5 V, T A; 25°e.

§

MAX

1.6
0.8

0.6

Vee = MIN,

UNIT

1.4

Vee = 5 V

I

C-a
C:C

0.5

Vee = 5V

..... =t
C .....
.....
m .....

mA

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SERIES 54

:een
_C"')
..... ::c
::cs:

IlA
mA
mAo

:I>

.....
m

en

:I>

Z
C
Z

<
m

:a

.....
m

:a
en

o
.....
en

supply current~

TYPE

-i

~
[TI

><

ICCL (mA)

outputs high

Total with
outputs low

TYP

TYP

'13
'14

..~

switching characteristics, Vee =5 V, T A =25°e

ICCH (mA)
Total with
MAX

ICC (mA)
Average per gate
(50% duty cycle)

MAX

TYP

tpLH (ns)
Propagation delay time,

TEST

TYPE

CONDITIONS

14

23

20

32

8.5

'13

36
24

39

60

5.1

'132

22
15

26

40

5.1

'14, '132
'LS13

'LS13

2.9

4.1

'LS14

8.6

6
16

12

7
21

1.75
1.72

'LS132

5.9

11

8.2

14

1.76

'S132

28

44

44

68

9

'LS14

CL = 15 pF,

RL =400 n

15
CL=15pF,

'LS132
'S132

low-to·high-Ieveloutput
MIN
TYP
MAX
18
27
15
22
15
15

RL = 2 kn

CL = 15 pF,

RL=280n

7

tpHL (ns)
Propagation delay time,
high-to-Iow-Ievel output
MIN
TYP
MAX
15
22
15

22

18
15

27
22

22

15

22

10.5

8.5

13

22
22

en
~

=
31:

-

:I..!.t

1) Maximum values of ICC are over the recommended operating

ranges of V CC and
TA

T A:

typical values are at VCC =

5

-=

V,

= 25°C.

C ')
C')

~ ;>

~ (J1
III o z_

~8z
~;(J1

TEST
POINT

00-1

~;o
~c::

03:
[TI

z

m

=
-a
o

PARAMETER MEASUREMENT INFORMATION

FROM
OUTPUT
UNDER

VCC

1 1

RL
(See Note AI

14

en

-------3V
INPUT

,(VlreflHI

' \ V'ref(L)

-./i

tal ~I ~I

I

!-tPHL-I

TEST

I-tPLH-.t
I

~
-

OUTPUT

-I

0V

VOref

-

VOH

___ VOL

(See Note CI

(J1

LOAD CIRCUIT

=i

<
m
~~
-z

=
O~
...-tCl

...-tC')

VOLTAGE WAVEFORMS

...-tm

men
NOTES:

Generator Characteristics
SN54'/SN74'
SN54LS'/SN74LS'
'S132

Zout
50n
50n
50n

PRR
1 MHz
1 MHz

tf
10 ns

1 MHz

2.5 ns

2.5 ns

II

-az

OCI
~

m-

Reference Voltages

tr
10 ns
15 ns

~

U1

~~

A. All diodes are 1N916 or 1N3064.
B. CL includes probe and irg capacitance.
C. Generator characteristics and reference voltages are:

6 ns

VI ref(H)
1.7V
1.6V

VI refILl
0.9 V
0.8 V

1.8 V

1.2V

VOref
1.5V
1.3 V
1.5V

:z
0<
em
...-t=
-a...-t

em
...-t=
en en

II

~

en

~en

_n

schematics (each gate)

• ·'---'T·'I

Vee
6 kl!
NOM

Vee

INPUTS

14

A ,

INPUTS

I =,

: I I.
. . -i
[TI
. . ><

•

•

14,.1

OUTPUT
y

B--;-.--l4- J

Y

••

•

•

I
•

GND

••

•

•

GND

l:.

(J1

ID -

o Z_

a

~8z
~~(J1
0°-1

,

,

,

,

,

120n
NOM

20 kn
NOM

g~;:o

, ,

Vee

G)

•

Vee

E ~c:
~

~

r::

~
m

en

:03::
l;

.,,-t
c
-t<

z
z

~ ;1>
~

e'"

en,:"

'14, '132 CIRCUITS

'13 CIRCUITS

m:a

~• G)
"'G)
em
~ :a
m
c~
-t._

*
I
I

•

g

A,

OUTPUT

-t=
=~
-t9
e
.
-t-t

[TI

z

l:.

INPUTS
A
,

z

141 • I

B-I-f---.r..,

~

(J1

eD -

INPUTS

y

--:-T-~
-1- ~ ...
I

I

I

I

I

I

•

•

•

OUTPUT
y

: -+-1----,
~ ~T~

:a
-t

,*~:f

m

•
. "

'LS13, 'LS14, 'LS132 CIRCUITS

o

;:;!

-I

POSITIVE·GOING THRESHOLO VOLTAGE

NEGATIVE·GOING THRESHOLO VOLTAGE

HYSTERESIS

FREE·AIR TEMPERATURE

FREE·AIR TEMPERATURE

FREE·AIR TEMPERATURE

Vee' 5 V

1.69

~

1.68

>

"~

1.67

F

1.65

"0

g-

0.88

""0

0.87

l
i

'13

1

V""-

0.85

..........

--

>

E
~

..........

l - I'--

830
820

i

810

.!.

790

;:

780

I

>I

0.83

>

800

0.82

.!.

0.81

760

0.80
-75 -50 -25

750
-75 -50 -25

>

1.60 L--L..--'-_.L...-L----'_-'-----'----'
-75 -50 -25 0
25· 50
75 100 125

770

0

25

50

75

100 125

0

25

50

75

100 125

lA-Free-Air Temperature-OC

lA-Free-Air Temperature-°c

FIGURE 1

FIGURE 2

FIGURE 3

'14, '132
DISTRI8UTION OF UNITS
FOR HYSTERESIS
Vee = 5 V
TA = 25°e

( \

(

r

I

\

~V
720 740 760

\

/

\

1/
j

73f jV

1/

~ I'--

~

780 800 820 840 860 880

\

V

V

I

~

VT+-VT _-Hysteresis-mV

FIGURE4

FIGURE 5

HYSTERESIS
vs
SUPPLY VOLTAGE

YS

SUPPLY VOLTAGE
2.0

2.0

1.8

1.8

1.6

1.6

OUTPUT VOLTAGE
vs
INPUT VOLTAGE

TA = 25°e

>

~
.~

1.4
1.2

~
I

1.0

:c

1.0

";;;"0

0.8

>

0.8

F

0.6

;:

0.6

.!.
I

>

0.4

Vee = 5 V
TA - 25°e

r-tr

r-- r-- f-lT+ i -

I'

>I

1.4
1.2

II

r-

740 760 780 800 820 840 860 680 900

VT+-VT _-Hysteresis-mV

THRESHOLD VOLTAGES

~

r--..

lA-Free-Air Temperature-°c

99%ARE
ABOVE

J

. . . . . t-.- 1-=
'-,

z

Vee - 5 V
TA = 25°e

~

r---...
'1:i""' '-,

I

1.61

'13
DISTRIBUTION OF UNITS
FOR HYSTERESIS

>I

'14, '132

r--

.~

V .....

0.84

g>

1.62

640

0.86

'0

1.63

Vee = 5 V

Vee - 5 V

>

'0 1.64

~
>

0.89

"0

t

~

--

1.66

~

>I

../'
'14, '132

"

850

0.90

J:

~

'14

'13 /'13;

~

1
'5

r--

,
,

o
I
o

'13

I

> 1

I

0.4

I

0.2

0.2

4.5

4.75

5.25

5.5

4.5

vee-Supply Voltage-V

.

FIGURE 6

tData for temperatures below Oa e and 70
and SN54132 only.

0

e

4.75

5.25

5.5

o
o

0.4

0.8

1.2

Vee-Supply Voltage-V

VI-Input Voltage-V

FIGURE 7

FIGURE 8

1.6

and supply voltages below 4.75V and above 5.25 V are applicable for SN5413, SN5414,

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-17

SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS
WITH TOTEM-POLE OUTPUTS
TYPICAL CHARACTERISTICS OF 'LS13, 'LS14, AND 'LS132 CIRCUITS t
NEGATIVE-GOING THRESHOLD VOLTAGE

POSITIVE-GOING THRESHOLD VOLTAGE

FREE-AIR TEMPERATURE

FREE-AIR TEMPERATURE
1_70

>

~
a

>

J

I

>I

1_69 f-V ee = 5V

1_67

j

1_66

a

>

0.88

~..~

0.87
::. 0.86

./
I--

~

0.85

1_64

~

0.84

.~

1.63

.~

~

1.62

f- 1_65
en
c:

·0

1 T

~ 0.89 I- Vee = 5 V

1_68

-0

0.90

l:)

VI?

V

/""

I---"'

L

......-

d>

t

0.83
0.82

I

.fI 1.61

~ 0.81

>

1.60
-75 -50 -25

25

50

75

100 125

0.80
-75 -50 -25

25

50

75'

100

125

T A -Free-Air Temperature-Oe

T A -Free-Air Temperature-Oe
HYSTERESIS

DISTRIBUTION OF UNITS
FREE-AIR TEMPERATURE
850

I

FOR HYSTERESIS

I

1

840 r--Vee = 5 V

>

830

c:

E

--

J, 820

(

810

J:
I

800

I

780

+

~

u

............

'0

...........
.............

I

f--

>

.~

770

a;
0:

760
750
-75 -50 -25

/"

:>

o

I
~ 790

II

_I

Vee = 5 V
-T = 25°e
A

25

50

75

\
99% ARE
ABOVE

or:

\

J

V

""

r--

720 740 760 780 800 820 840 860 880

100 125

VT+-V _ -Hysteresis-mV
T

T A -Free-Air Temperature-Oe

OUTPUT VOLTAGE

THRESHOLD VOLTAGES AND HYSTERESIS

INPUT VOLTAGE

SUPPLY VOLTAGE
2.0 r------.,,..----,----.--.,....----,---,----,

>

Vee - 5 V

1.b ~:...:....r-_r_--1-+-+--I--.,b--'

TA = 25"e

t: :

J:

]

1.2

~ 1.0

bd:=~;:;f:;::=:t::~~:±=::;:;±===1

a

0.8

"

0.6 1--+-+----1--+--+--+--+-----1

>

~~

0.4

f-

0.2 1---4--+---4--+--I---4--+----I

o

~_L_~~_~_L-_L_~~

4.5

4.75

5.25

OL-J--L~~~_L~

o

5.5

0.4

0.8

__L_J--L~

1.2

1.6

VI-Input Voltage-V

vee-Supply Voltage-V

tOata for temperatures below O°C and above 70°C and supply voltages below 4.75 V and above 5.25 are applicable for SN54LS13, SN54LS14,
and SN54LS132 only_

10n

6-18

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS
WITH TOTEM-POLE OUTPUTS
TYPICAL APPLICATION DATA

I
I

-

~
I

~OS.
CMOS,

@-Dn..
-I TTL SYSTEM

t-----

etc.

--------

I

~
~--

SINE-WAVE
OSCILLATOR

I
I
TTL SYSTEM INTERFACE
FOR SLOW INPUT WAVEFORMS

PULSE SHAPER

0.1 Hz to 10 MHz
330.n

INPUT

II
THRESHOLD DETECTOR

MUL TIVI BRATOR

Open·collector
output

1----,
INPUT

----1I

I

I

)
1--.....
--I

TPUT
r-l - F o U-n..-I

I

I

l-"lJ

I
PULSE STRETCHER

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALL.AS. TEXAS 7!i222

6-19

II

en
N
c

CD

recommended operating conditions

C
54 FAMILY

SERIES 54

SERIES 54H

SERIES 54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74H

SERIES 74LS

SERIES 74S

'28

Supply voltage, Vee

74 Family

4.75

5

74 Family
54 Family

- - - - -

- - - -

-

UNIT

'S37, 'S40

'LS40

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
4.5
5
5.5
4.5
5
5.5
4.5
5.5 . 4.5
5
5
5.5
4.5
5.5
5

54 Family

Operating free-air temperature, T A

'H40

54 Family

High-level output current, IOH
Low-level output current, IOL

'37, '40

"'"'m""

'LS28, 'LS37

_ c.2.4 Fam~y

5.25

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

4.75

5

-1.2

-1.5

-1.2

-3

48

48

60

12

60

48

48

60

24

60

-55

125

-55

125

-55

125

-55

125

-55

125

0

70

0

70

0

70

0

70

0

70

-

n

V

5.25

-2.4

mA

c
:a

°e

>
(IJ

0

'o"
[II

PARAMETER

-

z_

~8Z
~~(J)
0-l
~;o

TEST

TEST eONDITIONSt

SERIES 54

SERIES 54H

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74H

SERIES 74LS

SERIES 74S

'28

FIGURE

:IE
=i

IUNIT

'LS28, 'LS37,

'H40

'37, '40

'S37, 'S40

'LS40

;;;c:
c~

IT!

High·level Input voltage

1.2

VIL

Low-level input VOltage

1.2

VIK

Input clamp voltage

VOH

High-level output voltage

Z

-l

VOL

en

~

74 Family

Input current at

lOS

0.8

0.8

0.8

0.8

0.8

-1.5

-1.5

-1.5

-1.5

-1.2

Vee=MIN.

VIL ::VIL max. 54 Family

2.4

3.4

2.4

3.3

2.4

3.4

2.5

3.4

2.5

3.4

10H= MAX

74 Family

2.4

2.4

3.3

2.4

3.4

2.7

3.4

2.7

3.4

54 FamIly

3.4
0.2

0.4

0.2

0.4

0.15

0.3

0.25

0.4

0.5

74 Family

0.2

0.4

0.2

0.4

0.2

0.4

0.35

0.5

0.5 I

0.25

0.4

2V

Vee=MAX

High-level Input current

Vee=MAX
VCC: MAX

Low-level Input currenl
Short-CirCUit

ICC

0.8

0.7

t

lOL = MAX

output current·
Supply current

6·
Vee =MAX

IIOL""12mA Sefles 74LS
VI= 5.5 V

01

=

3:

V

-a
o
rm

I

V

40

40

mA

20
-1.6

VIL=04V

-1,6

-4

100

-0.4

IVIL=05V

-4

54 Family

-70

-180

-20

-70

74 Family

-70

-180

-18

-70

-40

-125

-30

-130

-50

-225

-40

-125

-30

-130 -50

-225

Se~

"A
mA
mA

table on next page

t For conditions shown as M IN or MAX. use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25"C.
= -12 mA for SN54'/SN74', -8 mA for SN54H'/SN74H', and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S'.

§"

t Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second for all of these circuits except 'S37 and 'S40, or 100 milliseconds for 'S37 and 'S40_

~

-a

c

~

100

VIH-2.7V

o

C

~

I

01

VI
7V
VIH =2.4 V

~

m

V

V

A

maXimum mput voltage

"L

V

2

0.8

0.8

11':0 §

VIH

IIH

0.8

Vee= MIN.

Vee: MIN.

Low-level output voltage

2

2

2
154 Family

:::c

o

MIN TYPJ: MAX MIN TYP+ MAX MIN TYPt MAX MIN TYPt MAX MIN TYPt MAX
VIH

<:

m
:a
en

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

><

n

:::-:::

g .....:J
[TI
of

r-

o

mA

...

~

:a

en
-.....

en

o

-.J

en

supply currentll
TYPE

ICCL (rnA)

Total with outputs high

Total with outputs low

TYP

~
~
~

><

>
(Jl

MAX

Average per gate

TEST

TYPE

(50",{, duty cycle)

CONDITIONS#

= 5 V, T A = 25°e

12

21

33

57

5.63

'37

9

15.5

34

54

5.38

'40

4

8

17

27

5.25

tpLH (ns)

tpHL (ns)

Propagation delay time,

Propagation delay time,

MIN
CL; 50 pF,

high·to·lowoutput

low·to·high·level output

TYP

MAX

TYP

'28

TYP

MAX

MIN

MAX
12

6

9

8

CL;150pF,RL;13311

10

15

12

18

'37

CL-45pF,

RL-13311

13

22

8

15

10.4

16

25

40

8.85

'40

CL-15pF,

RL-13311

13

22

8

15

1.8

3.6

6.9

13.8

1.09

'H40

CL-25pF,

RL-9311

8.5

12

6.5

'LS37

0.9

2

6

12

0.86

'LS28

12

24

12

12
24

'LS40

12
12

24
24

12
12

24
24

6.5

4

6.5

0.45

1

3

6

0.86

'S37

20

36

46

80

8.25

'S40

10

18

25

44

8.75

--=LS37

CL;45pF,

RL;66711

'537,

CL;50pF,

RL;9311

4

'540

CL;150pF,RL;9311

6

~

I

~ Maximum values of ICC are. over the recommended operating ranges of
Vee and T A; typical values are at Vee = 5 V, T A = 25°C.

schematics (each gate)

m

:=
en

ICC

vce

:8Z
~~en

INPUTS

OUTPUT

o~

A

• I .. 1111

Rl
R2
R3
R4
R5

OUTPUT
Y

Y

~;o
~c

aJ

c:

"TI
"TI

6

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

.,oz_
•

TYP

R L ; 133 11

'28

'LS28

'H40

... ~
lil !TI

switching characteristics, Vee
ICC (rnA)

ICCH (rnA)

'37
4k
600
100
400
4k

'40 'H40
4k 1.4 k
600
390
100
45
400
250
4k
2k

03:

C")
----ro
C")

::::-::

c
:=

;;:
m

:=
en

!TI

z
~
en

'28 CIRCUITS

'37, '40, 'H40 CIRCUITS

Vee

:E
=t
%

Vee

vee

-4

o

-4

m

s:
•

oN

•

OUTPUT

OUT~UT

~

..*--"

.JIII

~

y

OUT~UT

-~--i L_"'+ __ ~

**

_}--,-.~*_ -l

I

."

o

r-

m

o
c:

:

~_* __ ..J

-4

."
'LS28 CIRCUITS

'LS37, 'LS40 CIRCUITS

Resistor values shown are nominal and in ohms.
C')

.~

II

'S37, 'S40 CIRCUITS

c:
-4
en

II

en

N
N

recommended operating conditions

U'I
SERIES 54

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74S

'128

'S140

MIN
Supply voltage. Vee

High·level output current. 10H

NOM

MAX

MIN

NOM

I

Q

~
~

MAX

4.5

5

5.5

4.5

5

5.5

74 Family

4.75

5

5.25

4.75

5

5.25

54 Family

29

40

74 Family

-42.4

40

48

60

54 Family

55

125

55

125

1 74 Family

0

70

0

70

-<

~
g

><

PARAMETER

>
~ z_

TEST

TEST CONDITIONSt

FIGURE

(Jl

:sz
~~(/)
. 0-i
~;o
~c:

High·level input voltage

1.2

I

mA
mA
"e

VIL

Low·level input voltage

1.2

VIK

Input clamp voltage

3

SERIES 74

SERIES 74S

'128

'S140

03::
['TI

VOH

z

High·level output voltage

1

-i

(/)

Vee = MIN.

VIL = 0.8 V.

10H = -2.4 mA

Vee = MIN.

VIL = 0.4 V,

10H = -13.2 mA

Vee - MIN,

VIL = 0.4 V,

10H - MAX

Vee = MIN,

VIL = 0.8 V,

10H = -3 mA

Vee= MIN,

VIL = 0.5 V,

RO = 50

VIH = 2 V,

10L = MAX

Low·level output voltage

2

Vee = MIN.

II

Input current at maximum input voltage

4

Vee = MAX, VI = 5.5 V

IIH

High·level input current

4

Vee = M.AX

IlL

Low-level input current

5

Vee = MAX

lOS

Short-circuit output current.

6

Vee = MAX

lee

Supply current

I Total, outputs low
I Average per gate

7

n

54 Family

2.4

3.4

74 Family

2.4

3.4

MIN

0.8

V

-1.5

-1.2

V

V
2.5

3.4

74 Family

2.7

3.4

to GND

2
0.4

0.5

1

1
100

-1.6

VIL=O.4V

-4

VIL-0.5V
-70

50% duty cycle

V
rnA

40

VIH=2.7V

-180
12

21

33

57

-50

5.63

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.

tNot more than one output should be shorted at 'a time. and duration of short circuit should not exceed one second for '128 or 100 milliseconds for 'S 140.

8

V

0.8

+AII typical values are at Vee = 5 V, T A = 25°e.
§ II = -12 rnA for '128 and -18 rnA for '5140.

en

MAX

2

Vee = MAX

_:!e_c~~V.

TYP+

54 Family

VIH = 2.4 V

!:
z
m

-225
10

18

25

44

8.75

m

:a

en

2.4

0.26

~

;:
UNIT

2

11= §

VOL

I Total, outputs high

MAX

2

Vee = MIN.

::z:

~

SERIES 54S

TYP+

I

Q

:a

SERIES 54

MIN
VIH

U'I

V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
,,~
g ['TI

::z:

UNIT

54 Family

Low·level output current. 10L
Operating free·air temperature. T A

e

54 FAMILY

/lA
rnA
rnA
rnA

o

-.J

m

switching characteristics, Vee

TYPE

'128
'5140

= 5 V, TA = 25°e
tpLH (ns)

tpHL (ns)

TEST

Propagation delay time,

Propagation delay time,

CONDITIONS#

low-to-high-Ieveloutput

h igh-to-Iow-Ievel output

MIN

MIN

CL = 50pF,

TYP

MAX

TYP

MAX

RL=133!1

6

9

8

12

CL = 150 pF, RL = 133!1

10

15

12

18

RL = 93!1

4

6_5

4

6.5

CL = 150 pF, R L = 93 !1

6

CL=50pF,

I
I

6

#Load circuit and voltage waveforms are shown on page 3-10_

g"-1
fT'I

><

-t

~

>
(JJ

~
o z_

m -

~8z
~~(JJ
•

schematics (each driver)

o~

~~

4k~

03::
fT'I

z

~
(JJ

vee

- ,
I

~c::

~4k

Vee

30

600

1.4 k

380

25

CIt

INPUTS

Q
I

A~

C»

::
OUTPUT
V

B~

OUTPUT
V

B

~ --+-1+-e--'II
!

~
...,

.........
CIt

!

I

C»

::
~

!::
•

••

•

•

GND
'5140 CIRCUITS

'128 CIRCUITS

z

"'
a
:a

-=

:a
"'en

Resistor values shown are norninal and in ohms.

en

N
Co.)

GND

II

II

9'1
~

01::0

ca

recommended operating conditions
54 FAMILY

SERIES 54'

74 FAMILY

SERIES 74'
'06, '07
MIN

Supply voltage, Vee

'16, '17

54 Family

4.5

5

74 Family

4.75

5

74 Family

Operating free·air temperature, T A

74 Family

,

- - - - - -

.~
-i

- - -

- - -

-

4.5

5

5.25 4.75

5

5.5

54 Family
54 Family

5.5

UNITI

'33, '38

5
5

4.5

5

5.5

5.25 4.75

5.5

5

5.25

15

15

5.5

30

30

16

48

40

125 -55

0

4.5

5.25 4.75

30
40
-55
-

'26

NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

High·level output voltage, VOH
Low·level output current, IOL

I

70

16

125 -55

0

70

48

125 -55

0

70

125
70

0

V

-=

=(1)

I

>U"I

/

CJ-...I

z~
.......
~

V

Z
-t

mA

m

I

°e

(I)

em
~
~
mm

=
>
~

n
m

~

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

(TI

><

~ (J)
>

C")

>
-t

SERIES 54'

~

o'" -z_

TEST

PARAMETER

~8Z
~~(J)

FIGURE

'06, '07
MIN TYP

High·level

. 0-1
~;o

VIH

~c::

1,2

input voltage
Low-level

VIL

"3::
(TI

VIK

-I

IOH

z

Input clamp voltage

3

High-level

(J)

1

output current
Low·level

VOL
II

output voltage
Input current at
maximum input voltage
High·level

IIH

input current
Low-level

IlL
ICC

'16, '17
MAX MIN TYP

2

input current
Supply current

II =-12mA

-1.5

!:l

(I)

V

=4

=e

-1.5

0.8
-1.5

V
V

Vee = MIN,

VOH = 12 V

VI ='"

VOH = MAX

250

250

1000

0.4

0.4

0.4

0.7

0.7

0.4

0.4

1

1

1

1

mA

50
250

/J A

Vee = MIN,

IOL = 16 mA

2

VI = '"

IOL - MAX

4

Vee = MAX,

VI=5.5V

4

Vee ~ MAX,

VIH = 2.4 V

40

40

40

40

/J A

5

Vee = MAX,

VIL=O.4V

-1.6

-1.6

-1.6

-1.6

mA

7

Vee = MAX

V

:z::
Q
~

m
Z
I

n
Q

rr-

m
n

-t

mA

See table on next page

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

=2

0.8

-1.5

UNIT

MAX MIN TYP MAX
2

0.8

---

"'The input voltage is V I H

MAX MIN TYP

'33, '38

2

0.8
Vee = MIN,

'26

2

1,2

input voltage

m

SERIES 74'

TEST CONDITIONSt

Vor V I L = V I L max, as appropriate. See tables with test figures 1 and 2.

- -

-

---

Q

=

Q

e

-t
~

e

....en

j

supply current 11

TYPE

ICCH (rnA)

ICCl (rnA)

ICC (rnA)

Total with

Total with

Average per gate

outputs high

outputs low

(50% duty cycle)

TYP
'06, '16
'07, '17

switching characteristics, Vee

30
29

MAX

TYP

48
41

MAX

TYPE

. . ><

tpHl (ns)

Propagation delay time,

Propagation delay time,

CONDITIONS#

low-tcrhigh-Ievel output

high-tcrlow-Ievel output

TYP

32
21

51

5.17

30

4.17

~ CL=15pF,
'07, '17

'26

4

8

12

22

2.00

'26

'33

12

21

33

57

'38

5

8.5

34

54

5.63
4.88

'33

ranges of VCC and TA; typical values are at VCC = 5 V, T A = 25°C.

~

tplH (ns)
TEST

TYP

11 Maximum values of ICC shown are over the recommended operating

"....,
g IT!

= 5 V, TA = 25°e

I

'38

CL=15pF,

10
6

RL = 110n

MAX
15
10

TYP

MAX-

15
20

23
30

16

24

11

Hi

15

12

RL = 133 n

15

22

16

24

RL=133n

14

22

11

18

CL=50pF,

RL = 1 kn
RL = 133 n

CL = 150 pF,
CL =45 pF,

17
18

co

C

.."
.."

m

=
>
Z

CJ

Z

-t

#Load circuit and voltage waveforms are shown on ,page 3-10.

m

=
.."

>
n

schematics (each gate)

>
(JJ

m

~
o z_

m -

C')

~8Z
~~(JJ

-t

>

m

• 0-1

en

~~c:

:E

g~;:c
~03::
~

~

=i

IT!

Z

'06, '16 CIRCUITS

:z:

'07, '17 CIRCUITS

0

-I

(JJ

•

""C

vee

m

Z

R2

I

n

INPUTS

:~

vee

n

-ten

Om

~~------4---~~--GND

'38

R2

R3

4kn

1.6kn

.1 kn

4 kn

600n

Rl

==
Q

I
, •

•

400n
- -

'33 CIRCUITS

'26, '38 CIRCUITS

en

N

U1

r-

rm

INPUTS
A

CIRCUITS
'26

0

II

GND

ron

cen
-tU'l

""C~
C
__
-t ......

en

~

II

c;n
N
g)

=cn

recommended operating conditions

em
54 FAMILY

SERIES 54LS'

SERIES54S'

74 FAMILY

SERIES 74LS'

SERIES 74S'

'LS26
MIN
Supply voltage, VCC

4.5

5

74 Family

4.75

5

54 Family
74 Family

Operating free-air temperature, T A

5.5

4.5

5

5.25 4.75

5

-55

74 Family

0

5.5

4.5

5

5.25 4.75

5

4.5

5

5.5

5.25 4.75

5.5

5

5.25

15

5.5

5.5

5.5

4

12

12

60

8

54 Family

-

UNIT

'538

NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

54 Family

High·level output voltage, VOH
Low-level output current, IOL

'L538

'LS33

~=

24

125 -55
70

24

125 -55

0

70

60

125 -55

0

70

125

0

70

~
mm
=en
>U'I

2~

V
V
mA
°c

e~
""'z ......
-t~
men
~>
>Z

ne

-1

C3
~

IT!

~

nm

><

SERIES 54LS'

>

_W

PARAMETER

'"0 z
x

,,-

oZ
~ ~rn
N
N

TEST

TEST eONDITIONSt

FIGURE

V

- ""'en
-t

SERIES 54S'

SERIES 74LS'
'LS26

SERIES 74S'

'LS33

'S38

'LS38

::e~

MIN TVP± MAX MIN TVP+ MAX MIN TYP+ MAX MIN TYP+ MAX

. ;t;l

N

UNIT

m en
C')m
>=
-tmm
en en

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

High-level

o~

VIH

F ~c:

VIL

;:;1
x

VIK

input voltage

1,2

2

2

2

2

0

!f,

~


2
C
i2

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

-I

1I-i
g [TI
-I

><

~

(fJ

m

::a

schematics (each gate)
Vee

~ ;l>

Vee

m

INPUTS

m -

o z_

:sz
~~(fJ

0-1
~iO

TPI: TJ

C')en
»m
-1=
m_
en m
:een

1.. 1 • •1,1

Alii

: T. 1:

"TI

»

n

y

,/Clear.,

B

~c:

03:

•

[TI

z

••

GND

•

'LS26 CIRCUITS

-I

•

•

GND

'LS33 CIRCUITS

(fJ

g,

-I~

:,...
en
C -"'a
......

mf!
Zen
n»
I

Vee

Vee
17 k
INPUTS

Cz

~c

1

~ ~T-,-:
.............~-o-ITJ

A

OUTPUT

B

y

men
-I::a
C_
::am
en

n m·

Qg,

o

••

c:~
-len
"'a
__

GND

'LS38 CIRCUITS

'S38 CIRCUITS

Cl

N
......

II

\,

c: ......
-I~
en en

•

en

N

=

."
Q

en
=t

recommended operating conditions

Supply voltage, Vee

54 FAMILY

SERIES 54

SERIES 54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74LS

SERIES 74S

'32

'LS32

'S32

MIN

NOM

MAX

MIN

NOM

MAX

MIN

NOM

54 Family

4.5

5

5.5

4.5

5

5.5

4.5

5

74 Family

4.75

5

5.25

4.75

5

5.25

4.75

5

Operating free-air temperature, T A
- - -

2l
~

~

n
m
tIl

54 Family

16

4

20

74 Family

16

8

20

'"

.

0

;:ri
X

~
...,

'"en'"

'"

-55

125

74 Family

0

70

0

70

--

TEST

PARAMETER

TEST CONDITIONSt

FIGURE

-55

-'-

125

0

70

G')

!i
m

mA
"e

en
~

=t

- -

~(JJ

VIH

~;o

VIL

Low-level input voltage

VIK

Input clamp voltage

3

VOH

High·level output voltage

1

VOL

Low-level output voltage

2

o~

03:

High·level input voltage

1,2

,~
(JJ

II
IIH
IlL
lOS

lee

Input current at maximum input voltage
Hig,·level input current

4

Low-level input current

5

Short~ircuit output current-

Supply current

I
I
I

4

6

Average per gate

7

SERIES 54S

SERIES 74

SERIES74LS

SERIES 74S

TYP:j:

'LS32
MAX

Vee = MIN,

11= §

Vee - MIN,

VIH - 2V,

10H = MAX
Vee = MIN,

IIOL = MAX

VIL = VIL max

tlOL = 4 mA

MIN

TYP:!:

0.8

0.7

0.8

0.8

0.8

0.8

-1.5

-1.5

-1.2

54 Family

2.4

3.4

2.5

3.4

2.5

3.4

74 Family

2.4

3.4

2.7

3.4

2.7

3.4

54 Family

0.2

0.4

0.25

0.4

0.5

0.2

0.4

0.35

0.5

0.5

0.25

0.4
1
0.1

40
20

VIL=O.4V

-1.6

50

-0.4
-2

VIL = 0.5V

Vee = MAX

54 Family

-20

74 Family

-18

Vee= MAX

50% duty cvc~

-55

-20

-55

-20

-100

-40

-100

-40

-100
-100

15

22

3.1

6.2

18

32

23

38

4.9

9.8

38

68

4.75

1.0

7

t For conditions shown as MIN or MAX, use the appropriate value specified undeJ recommended operating conditions.

:j: All typical values are at Vee

=5

V. T A

= 25 0 C.

§ II = -12 mA for SN54'/SN74' and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S',
·Not more than one output should be shorted at a time, and for SN54LS'/SN74LS' and SN54S'/SN74S', duration of the short-circuit should be less than one second,

cD

."

s:
I

,...
m
Q

V
V

Q

C

-4

V

."

C

-4

1

VIH - 2.7 V

V

V

74 Family
Series 74LS

UNIT

-4
m

MAX

2

VI = 7V

Vee= MAX

'S32
MAX

74 Family

VIH - 2.4 V

Vee= MAX

Vee- 5V ,

TYP:j:

2

VI = 5.5V

Vee= MAX

MIN

Q

54 Family

Total, outputs hig,
Total, outputs low

SERIES 54LS

2

1,2

rr1

Z

-4

SERIES 54
'32
MIN

~ ~c:::

!f,

125

><

z_

~

-55

V
/lA

electrical characteristics over recommended free-air temperature range (unless otherwise noted)

>
_(JJ

8z

x

5.25
-1000

:::c

~

rr1

0

Q
5.5

-400

54 Family

m
I

::D

MAX

-800

Hig,·level output current, 10H
Low·level output current, 10L

;:
UNIT

en

mA
/lA
mA
mA

mA

o

'-I

(l)

switching characteristics at Vee

= 5 V, TA = 25°e
tpLH (ns)

TYPE

TEST

Propagation delay time,

tpHL (ns)
Propagation delay time,

CONDITIONS#

low-to-high-Ievel output

high-to-Iow-Ieveloutput

MIN
'32

TYP

MAX

TYP

MAX

10

15

14

22

14

22

14

22

CL=15pF, RL=280n

4

7

4

7

CL = 50pF, RL =280n

5

CL = 15pF, RL = 400 n

'LS32 CL-15pF,
'S32

schematics (each gate)

RL - 2 kn

MIN

Vee
130
INPUTS
A

5
OUTPUT Y

.. -i
. . ><

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11,

."
Q

£ !T1

~
~

>
(J)

,

,

GND

-=m,

m -

o z_

:8z

'32 CIRCUITS

~~(J)
• 0""i
g~;o
~~c

Q

Vee
11 k

20k S20k

Bk

Vee

·120
2.B k

:o~
~

~
~
~

!T1

Z

en
=i

INPUTS
A

141

,

2.Bk

50

;;>2k <-900

=
!i
m
C')

en

• [

:e

-of

(J)
~

•

Wo

•

OUTPUT Y

A

=i

•

OUTPUTY

:

-t
Q
-t

m

3:
I

•
•

•

• •

GND

."
Q

.m

GND

'S32 CIRCUITS

'LS32 CIRCUITS

•

o

C

-t

."

Resistor values shown are nominal and in ohms.

C

-t

en
en

N

CD

II

II

en

W

c

l>

recommended operating conditions
54 FAMILY

SERIES 54

SERIES 54H

SERIES 54L

SERIES 54LS

SERIES 54S

74 FAMILY

SERIES 74

SERIES 74H

SERIES 74L

SERIES 74LS

SERIES 74S

'L51, 'L54,

'LS51, 'LS54,

'51, '54
MIN
Supply voltage.

Vee

High-level output current, IOH

Low-level output current, IOl

54 Family

4.5

74 Family

4.75

'H51, 'H54
MAX I MIN
5.25

'L55
5.5

4.5

I 4.75
I
I

5.25

4.75

-500

100

- 400

-1000

-500

-200

-400

-1000

-400

54 Family

16

20

74 Family

16

20

125 I -55

NOM

MAX

MIN

5.5

4.5

5.25

4.75

MAX

MIN

5.5

4.5

5.25

4.75

NOM

MAX

20

125 I -55

125

70

I

<
m

5.25

3.6

70

:2

5.5

20

125 I - 55

70

NOM

::::a
I

4.5

-400

I -55

'S51, 'S64

'LS55

MIN

54 Family

74 Family

I

C

UNIT

MAX

5.5 I

NOM

74 Family

54 Famdy

Operating free-air temperature, TA

NOM

:2
CJ

-55

"A

mA

-I

C')

l>
-I
m

125

70

::::a

70

en
."

-;

--i

!TI

~

~

><

~
ro

o z

~

>
(J1

PARAMETER

8z

High-level

VIH

(J)
0"";

VIL

~ ;C

~ ; c:
~
'"en
'"

(f)

input voltage
Low-level

VIK

J;, " ~
~

TEST

TEST CONOITIONSt

FIGURE

input voltage
Input clamp voltage

High-level

VOH

output voltage

IT!

Z

VOL

....;

rn

input current

input current

SERIES 54LS

SERIES 54S

SERIES 74

SERIES 74H

SERIES 74L

SERIES 74LS

SERIES 74S

'L51, 'L54,

'LS51, 'LS54,

TYPt

'H51, 'H54
MAX

I MIN

Typj

0.8

54 Famdy
74 Family

Vee = MIN,

II =

~

Vee = MIN,
VIL

~

'L55
MAX

I

MIN

TYP;

'S51, 'S64

'LS55
MAX

I

MIN

TYP±

MAX

MIN

54 Family

2.4

3.4

2.4

3.4

0.8

0.7

lOS
ICC

output current.
Supply current

TYPO;

0.8

0.8

0.7

-1.5

-1.5
2.4

3.4

2.4

3.4

2.4

3.3

2.4

3.2

0.8

0.8

-1.5

-1.2

74 Famdy

Vee = MAX
Vee = MAX

TIOL=MAX
rlOL = 4 mA

I

I

I

25

3.4

2.5

3.4

2.7

3.4

2.7

3.4

s:
I

""CI

C

r-

Vee = MAX
Vee = MAX

m

Series 74LS

I

0.25

-I

0.1

VI = 5.5 V

mA

0.1

VI = 7 V
40

VIH = 2.4 V

50

C

c:

0.4

10
20

VIH=2.7V

50

"A

-0.18
-0.4

-2

-1.6

VIL = 0.4 V

mA

-2

54 Family

-20

-55

I -40

-100

74 Family

-18

-55 I -40

-100

-3
-3

I -20
-15 I -20
-15

I -40

-100

-100 I -40

-100

-100

See table on nex t page

:\: All typical values are at V CC = 5 V, T A = 25° C.
§ II = -12 mA for SN54'/SN74', -8 mA for SN54H'/SN74H', and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S'.
+Not more than one O'Jtput should be shorted at a time, and for.SN54LS'/SN74LS', SN54H'/SN74H', and SN54S'/SN74S', duration of the short-circuit should not exceed

~

-I

~~~--~----~--~~----~~~~r---~~--~~----~~--~+---------~~~::~
I

VIL = 0.3 V
Vee = MAX

I

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

one second.

-I
C

MAX

0.8

0.7

VIL = 0.5 V
Short-circuit

-I

:::c
UNIT

VIL max,

10H = MAX

VIH = 2V

Low-level

IlL

1,2

Vee = MIN,

Hig,-Ievel

IIH

SERIES 54L

m

I

Low-level

Input current at

SERIES 54H

1,2

output voltage

maximum input voltage

SERIES 54

'51, '54
MIN

§ ~
o

:E

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

mA

""CI

c:
-I
en

o

-.j
(I)

supply current~
TYPE

....,
[TI

g
-i

><

~

(J)

~

>

ICCL (mA)
Total with outputs low

ICCH (mAl
Total with outputs high

= 5 V, TA = 25°e

Average per AOI gate

TYPE

tpLH (ns)

tpHL (ns)

TEST

Propagation delay time,

Propagation delay time,

(50% duty cycle)

CONDITIONS#

low·to-high-Ievel output

high-to-Iow-Ievel output

MIN

MIN

TYP

MAX

TYP

MAX

TVP

MAX

TYP

MAX

TYP

'51

4

8

7.4

14

2.85

'51, '54

CL=15pF,

RL=400n

13

22

'54

4

8

5.1

9.5

4.55

'H51

C L = 25 pF,

R L = 280 n

6.8

11

6.2

8.2

12.8

15.2

24

~.85

'H54

CL=25pF, RL=280n

11

~

'H51

..

switching characteristics.at Vee
ICC (mA)

'H54

7.1

11

9.4

14

8.25

'L51, 'L54,

'L51

0.44

0.8

0.76

1.3

0.30

'L55

'L54

0.39

0.8

0.60

0.99

0.50

'L55

50

90

RL = 2 kn
RL = 2 kn

12

20

12

20

3.5

5.5

CL=50pF, RL=4kn

0.22

0.4

0.38

0.65

0.30

'LS51, 'LS55 CL = 15pF,
CL = 15pF,
'LS54

'LS51

0.8

1.6

1.4

2.8

0.55

CL=15pF,

RL=280n

'LS54

0.8

1.6

1.0

2

0.9

CL=50pF,

RL=280n

'LS55

0.4

0.8

0.7

1.3

0.55

'S51

8.2

17.8

13.6

22

5.45

'S64

7

12.5

8.5

16

7.75

'551, 'S64

15

35

11

60

~
~
3.5
5.5
-5.-5---

C
I

Vee

I

z
<
m

Z_

~8Z
~~(f)

schematics (each gate)

OUTPUT
y

• 0"';

~;c

Os:
[TI

Z

>

OUTPUT
y

-4

m

en

:e

Resistor values shown are nominal and in ohms.

...;

=
-4
C')

The portion of the circuits within the dashed
lines is repeated (with as many emitters or
input diodes as applicable) for each additional
AND section.

~c:

Q

=

~ Maximum values of lee are over the recommended operating ranges
of Vee and T A; typical values are at Vee = 5 V, T A = 25°e.

ID -

o

>

Z

#Load circuit and voltage waveforms are shown on pages 3-10 and 3-11,

'51, '54 CIRCUITS

(f)

=i

'H51, 'H54 CIRCUITS

::
-4
Q

-4

m

r------ ---,
I
)

I

I"""¢

4Ok~

V

• . Pi

i

3:

OlJT';UT

I

OUTPUT
y

I

I

rm

I

:---1::
I
l~~~~~ ____ J

."
Q

OUTPUT
Y

Q

C

-4

."

__ ~______ J

C

-4

'L51, 'L54, 'L55 CIRCUITS

'LS51, 'LS54, 'LS55 CIRCUITS

en

~

II

'S51, 'S64 CIRCUITS

en

II

en

W

N

recommended operating conditions
SN54S65
MIN
Supply voltage, Vee

4.5

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

5_5

V

20

mA

70

°e

5.5

Low-level output current, IOL

20
-55

125

0

a

UNIT

NOM

High-level output voltage, VOH
Operating free-air temperature, T A

l:.
Z

SN74S65

I

Q

electrical characteristics over operating free-air temperature range
(unless otherwise noted)

:::D
.!..
Z

<

:::D
"'
-4
C')

schematic
vee

TEST
PARAMETER

.g

~

!TI

><
~~ (JJ
>
-i

FIGURE

VIH

High-level input voltage

1,2

VIL

Low-level input voltage

1,2

VIK

Input clamp voltage

3

IOH

High-level output current

1

VOL

Low-level output voltage

2

om z
_

~8Z
~~(JJ
• 0""'1
g ~;o
~~c:

Input current at
II

High-level input

:03::
~ !TI
~ Z
~
::l

maximum input voltage

IIH

current
Low-level input

IlL

""'I

(JJ

current

TE;ST eONDITIONSt

'S65
MIN

TYP:j:

MAX
0.8

Vee= MIN,

II = -18mA

Vee = MIN,

VIH -0.8V,

VOH = 5.5 V
Vee = MIN,

VIL=2V,

IOL = 20mA

-1.2

V

250

IJA

0.5

V

1

mA

4

Vee = MAX, VI = 2.7 V

50

IJA

5

Vec = MAX, VI = 0.5 V

-2

mA

7

Vec= MAX

7

Vec= MA~

=

Q

~

Z
"'
I

Vee = MAX, VI = 5.5 V

ICCL Supply current, output low

=i

V

4

ICCH Supply current, output high

~

V

2

!i
en
"'

UNIT

--

6

11

mA

8.5

16

mA

n

Q

....-

n
"'
=
-4
Q
Q

C
-4

- -

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating
conditions.
0
:j:AII typical values are at V CC = 5 V. T A = 25 C.

~

C

-4

en
switching characteristics, Vee
PARAMETER

= 5 V, T A = 25°e
TEST CONDITIONS#

Propagation delay time,

eL=15pF,

tpLH low-to-high-Ievel output

eL = 50pF,

Propagation delay time,

CL = 15pF,

high-to-Iow-Ievel output

eL=50pF,

tpHL

#Load circuit and voltage waveforms are shown on page 3-10.

o

-.I

n.
RL = 280 n.
RL = 280 n.
RL = 280 n.
RL = 280

Resistor values shown are nominal and in ohms.

'S65
MIN

TYP

2

5

MAX
7.5

5.5
6.5

ns
ns

8
2

UNIT

8.5

ns
ns

""
recommended operating conditions
54 FAMILY

SERIES 54

SERIES 54LS

SERIES54S

74 FAMILY

SERIES 74

SER!ES74LS

SERIES74S

'125,'126,

'LS125A, 'LS126A

'425, '426

Supply voltage, Vee
High·level oUlput current, IOH

..
g -i
rrI
-I

~
~

MIN

NOM

MAX

MIN

NOM

MAX

MIN

NOM

54 Family

4.5

5

5.5

4.5

5

5.5

4.5

5

5,5

74 Family

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

-2

-1

-2

74 Family

-5.2

-2.6

-6.5

54 Family

16

12

20

74 Family

>
PARAMETER

m o z_

TEST

125

-55

125

-55

125

74 Family

0

70

0

70

0

70

SERIES 54

SERIES54LS

SERIES54S

SERIES 74

SERIES 74LS

SERIES74S

'125,'126,

Hig,-Ievel input voltage

1,2

V,L

Low-level input voltage

1,2

03::

V,K

In pu t cI amp vol tage

VOH

High-level output voltage

mA
De

Vee- MIN,
V,L = V,L max,

VOL

Low-level output voltage

IOZ

II

Off-state (high-impedance
state) output current

V'H=2V,

Input current at

I'H

High-level input current

',L

Low-level input current

4

TYP:):

MAX

MIN

TYP:):

MAX

0.8

0.8

0.8
0.8

-1.5

-1.5

-1.2

V'H-2V,

" = §
54 Family

2.4

IOH =MAX

74 Family

2.4

I'OL =MAX

lOS

Short~ircuit output current·

Vee = MAX

lee

Supply current

Vee= MAX

3.4

3.1

2.4

3.2

0.4

Vo = 0.5 V

Vee=MAX

2.4

74 Family

V,L = V,L max

Vee = MAX

2.4
2.4
0.4

VO=0.4V

0.7

3.3

54 Family

V,H = 2 V,

Vee= MAX

maximum input voltage

MIN

0.8

V,L = V,L max I'OL = 12 mA Series 74LS
Vee= MAX,
VO=2.4V
19

MAX

54 Family
74 Family

Vee = MIN,

(J)

TYP:):

IUNIT

'S134

V

I
Vee = MIN,

Z

'LS125A, 'LS126A

'425, '426
MIN

V,H

-I

mA

20

-55

TEST eONDITIONst

FIGURE

0-1
~;o
rrI

V

electrical characteristics over recommended operatin.g free-air temperature range (unless otherwise noted)

(J)

~c:

24

16

54 Family

><

~8z
~~(J)

MAX

54 Family

Low·level oulput current, IOL
Operating free·air temperature, T A

UNIT

'S134

V
V
V

0.25

0.4

0.5

0.35

0.5

0.5 I

0.25

0.4

40

20

-40

-20

V

50

I

V,=5.5V

jjA

mA

0.1

V,H = 2.4 V

-1.6

jjA

50

20

V'L=0.4V

0.4

mA

-2

V'L-0.5V
54 Family

-30

-70

74 Familv

-28

-70

-40

-225

-40

-100

-40
-225 -40
See table on next page

-100

mA

I

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions,
tAli typical values are at Vee = 5 V, TA = 25°e,

§ " = -12 mA for SN54'/SN74' and -18 mA for SN54LS'/SN74LS' and SN54S'/SN74S',
+Not more than one output should be shorted at a time, and for SN54LS'/SN74LS' and SN54S'/SN74S', duration of the short circuit should not exceed one second,
C)

w
w

II

:e

=i
=
W

40

V,H = 2.7 V

~

m

(I)

-50

V,-7V

C')

I

(I)

.....
>
.....
m
o
C
.....
~

C

.....
(I)

II

CO)

w
-'="

C')

supply current~
TEST CONDITIONS
TYPE

>
-I

schematics (each gate)

DATA

OUTPUT

INPUTS

CONTROLS

'125, '425

OV

'126, '426
'LS125A

Icc (mA)
MIN

,

,

m

Vee

en

:e

TYP

MAX

4.5V

32

54

OV

OV

36

62

OV

4.5V

11

20

CONTROL
INPUT

'LS126A

OV

OV

12

22

e

OV

OV

7

13

'5134

5V

OV

9

16

5V

5V

14

25

-I

::z:

OUTPUT

y

11 Maximum

-i
IT!
><

"'0

0

~

~

OJ

>
_00

x

('1-

nm
0

DATA
IN~Ul

wI
en

-I

>
-I

_ _ _ _ _ _ _ _- '

m

'125, '425 CIRCUITS

o

values of ICC are over the recommended operating

ranges of Vee and T A; typical values are at
TA = 25°C.

Vee =

5

V,
•

•

C
-I

Vee

~

C
-I

en

Z

'"'" oZ
~oo
~ 0-1
0
~;c

CONTROL

OUTPUT

INPUT

Y

e

~ ~c:::

DATA
INPUT
A

.~ c~
-I

m
X

tTl

'"en

-l
00

~
(J1

'126,426 CIRCUITS

Z

Resistor values shown are nominal and in ohms.

switching characteristics, Vee

= 5 V, TA = 25°e
SERIES 54/74

PARAMETER

TEST

'125, '425

SERIES 54S/74S

SERIES 54LS/74LS
'126, '426

TEST

'LS125A

'LS126A

CONDITIONS# TYP MAX TYP MAX CONDITIONS# TYP MAX TYP MAX
Propagation delay time,
tPLH

8

low-to-high-Ievel output

Propagation delay time,
tpHL
.
high-to-Iow-Ieveloutput

CL=50pF,

13

8

13

9
CL=45pF,

15

9

15

12

18

12

18

7

18

8

18

tPZH Output enable time to high level

11

17

11

18

12

20

16

25

tPZL Output enable time to low level

16

25

16

25

15

25

21

35

RL =400n

tPHZ Output disable time from high level

CL-5pF,

5

8

10

tPLZ Output disable time from low level

RL=400n

7

12

12

16

CL=5pF,

18

RL =667 n

- -

#Load circuit and vOltage waveforms are shown on page 3-10 and·3-11.

RL =667 n

20

25

20

25

- - - - - - - -

TEST

'S134

CONDITIONS#

TYP MAX

CL=15pF, RL=280n

4

CL = 50pF, RL = 280n

5.5

CL=15pF, RL=280n

5

CL = 50 pF, RL = 280n
CL = 50 pF, RL = 280 n
CL = 5 pF,
-

RL = 280n
----

UNIT
6

7.5

7

ns
ns

13

19.5

ns

14

21

ns

5.5

8.5

ns

9

14

ns

GATES WITH 3-STATE OUTPUTS

en

I-

:5
CJ
c:

U


~

f-

::>

z

"

"

0

1;;
.~

a:

l77

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

6-35

I

I

en

W
en

=
><

recommended operating conditions

Supply voltage, Vee
High~evel

output current, IOH

low-level output current, 10l
Operating free·air temperature, T A

"II

~

-t

~
~

54 FAMilY

SERIES 54

74 FAMilY

SERIES 74

MAX

MIN

NOM

MAX

54 Family

4.5

5

5.5

4.5

5

5.5

74 Family

4.75

5

5.25
-2

4.75

5

5.25

54 Family
74 Family

-5.2

54 Family

32

12

74 Family

32

24

UNIT

-1

54 Family

-55

125

-55

125

0

70

0

70

SERIES 54

><

»
(J)

TEST

PARAMETER

TEST CONDITIONSt

FIGURE

mA
mA
°e

~~(J)

VIH

• O~

Vil

low-level input voltage

1,2

g~;c
~~c:

~C3:

VIK

Input clamp voltage

VOH

High~evel

output voltage

Val

low-level output voltage

10Z

IIH

19

output current

-1.5
3.3

10H = MAX

74 Family

2.4

3.1

Vee =MAX,

Vee=MAX

Either

Short-circuit output current·

ICC

Supply current

6

2.4

3.1
0.4

74 Family

0.4

0.35

0.5

0.25

0.4

VO=2.4V

40

20

Va - 0.4 V

-40

-20

VI- 5.5V
0.1

VI-7V
VIH - 2.4 V

40

VIH=2.7V

20

VI = 0.5 V,
VI = 0.4

-40

VI = 0.4 V,

Vee= MAX

-40

Vee- MAX

-0.4

I

-0.4

ta~le

I

-40

on next page

-225

V

JlA
mA
JlA

T mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
;AII typical values are at Vee

§ II

=5

= -12 mA for SN54'/SN74'

V, TA = 25°e.

and -18 mA for SN54LS'/SN74LS', SN54S/SN74S'.

·Not more than one output should be shorted at a time, and for SN54LS'/SN74LS' and SN54S'/SN74S', duration of output short-cIrcuit should not exceed one second.

00.

>
-I
m

C
-I

I mA

I

-I

V

IJA

-1.6
-130
See

I

en

Q

-20

-1.6

V.

:e
~
=

V

V

0.25

II0l - 12 mA Series 74lS
VIH = 2V,

3.3

0.4

G inputs at 0.4 V

Vee =MAX,

-1.5
2.4

54 Family

G input at 2 V

Vee = MAX,
Both

lOS

II0l = MAX

Vil = Vil max

High-level input current

G inputs

0.7
0.8

2.4

Vee = MAX

I A inputs

V

0.8

54 Family

Input current at maximum input voltage

low-level input current

I UNIT

MAX

0.8

11= §

Vee - MAX,
III

TYP+

54 Family

VIH-2V,

Vil = Vil max
Off-state (high-impedance state I

MIN

m

:a
en

I

74 Family
Vee - MIN,

VIH=2V,

~

(J)

MAX

Vee - MIN,

Vee-MIN,

... Z

'lS365A, 'lS366A
'lS367A, 'lS368A

TYP+

=
:a
-<
W

SERIES74lS

'365A, '366A

2

Vil = Vil max,

!TI

SERIES54lS

SERIES 74
'367A, '368A
MIN

1,2

=
c
en

V

-2.6

74 Family

!TI

High-level input voltage

UI

'lS367 A, 'lS368A

NOM

111-

....

'367A, '368A
MIN

o z_

x
~

'365A, '366A

SERIES 74lS
'lS365A, 'LS366A

electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)

-i

:8z

m

SERIES54lS

~

C
-I

en

......w
supply curren~ 11

switching characteristics, Vee

DATA

OUTPUT

INPUTS

CONTROLS

'365A, '367A

OV

4.5V

65

85

'366A, '368A

OV

4.5V

59

77

tPLH

'LS365A, 'LS367 A

OV

4.5V

14

24

tpHL

~A,'LS368A

OV

4.5V

12

21

tPZH

TYPE

ICC (mA)
TYP
MAX

PARAMETER·

..

,

('T1

><

g~

MAX

TYP

'366A, '368A
TYP

MAX

SERIES 54LSI74LS

TEST
CONDITIONS

16

17

CL = 50pF,

22

16

CL = 45 pF,

RL=400n

35

35

RL = 667 n

37

37

'LS365A, 'LS367A

'LS366A, 'LS368A

TYP

MAX

TYP

MAX

10

16

7

15

9

22

12

18

19

35

18

35

24

40

28

45

tPHZ

CL - 5 pF,

11

11

CL - 5 pF,

30

32

tPLZ

RL=400n

27

27

RL =667 n

35

35

tpZL = Output enable time to low level
*tPLH = Propagation delay time, low-to-high-Ievel output
tpHL = Propagation delay time, high-to-Iow-Ievel output
tpHZ = Output disable time from high level
tpLZ = Output disable time from low level
tpZH = Output enable time to high level
NOTE 1: Load circuits and voltage waveforms are shown on pages 3-10 and 3-11.

~

~

SERIES 54174
'365A, '367A

-

schematics

-t

CONDITIONS

= 5 V, T A = 25°e, see note 1

tPZL

~ Maximum values of ICC are over the recommended
operating ranges of Vee and T A; typical values are
atVee=5V,TA=25°e.

TEST

J

II

- - -,

' ,

Vee

~LI~ICI
~~~~--1:
,

.1

~

::z:

>
(J)

m -

o z_

~8z
~~(J)

m
CONTROL
INPUT
OUTPUT

V

CONTROL

INPUT

INPUT

03:

DATA
INPUT

en

c
:a

(;2

DATA
IN';:'T

II

A

II

.I

<

m

('T1

:a

z

-I

i

CONTROL
INPUT

vee

,

I

en

Vee

:e
....
::z:

CONTROL
OUTPUT

G10RG1

V

DATA

OUTPUT

V

t R is 600

III

Resistor values shown are nominal and in ohms.

en

II

I

....
>
....
m
Q

....

C

n

for the control
section associated with 01
and 900 n fOT the control
section associated with 02.

'367A CIRCUITS

W

en

IN~JT

n

for the control
section associated with 01
and 900 n for the control
section associated with 02.

INPUT
01DR02

DATA

III

INP~T

t R is 600

I,

1 OF 6 DRIVERS

1 OF 2 CONTROL SECTIONS

r---------I

(J)

W
.....

m

c

V

CONTROL

a2

OUTPUT

Gl

00-1

~;o
~c:

><

CONTROL
INPUT

al

'368A CIRCUITS

""CI

C

....
en

•

C)

w

co

::c
m

><
aI
C

, ,

•I ,

,I

Vee

*I

,I ,

en

Vee

C

::a

<

m
OUTPUT

OUTPUT

Y

Y

::a

en

INPUT

G2

-I

~
~

•

DATA

'1J~
[TI

g

• I I Ii'

•,

•I

:IE
, "

GND

I

I

'I

• ,

-t

GND

::c

INPUT

><

DATA
INPUT------------=:::J

A

W
I

en

)-

(J)
aIII -z _

'LS365A CIRCUITS

-t

'LS366A CIRCUITS

>

-t

~8z

m

~~(J)
. 0-l
~;o
~c:

o
C

-t

03:
[TI

"

z

, ,

,I, I

,,

vee

"

-l

,I ,

OUTPUT

GI.G2

Y

14'

. , ill' I •

•

,

'!

CONTROL
INPUTS
G"1.~2

I

, , III

INPUT

t R is 5 kn for the control
section associated with G1
and 8 kn for the control
section associated with G2.

'

I

Vee

I I

section associated with <31
and 8 kn for the control
section associated with (;2.

C

-t

en

• ,

I'

t R is 5 kn for the control
'LS367A CIRCUITS

Resistor values shown are nominal and in ohms

~

I

OUTPUT
Y

, .1.'

GND

r-------

I

1'8k

(J)

INPUTS

""'CI

I OF 6 DRIVERS

'LS368A CIRCUITS

I

GND

!3

a>

recommended operating conditions
54 FAMILY

SERIES 54

74 FAMILY

SERIES 74
'23

Operating free-air temperature range, T A

1J~
[TI

><
:;: :>

.,a~ -zC/l_

MAX

MIN

MAX

MIN

NOM

5.5

4.5

5

5.5

4.5

5

5.5

74 Family

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

-400

-500

16

16

20

16

16

20

54 Family

-55

125

-55

125

-55

125

74 Family

0

70

0

70

0

70

V
}.LA
mA
°e

The '23, '50, and '53 are designed for use with up to four '60 expanders.
The 'H50, 'H53, and 'H55 are designed for use with up to four 'H60 expanders or one 'H62 expander.
The 'H52 is designed for use with up to six 'H61 expanders.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

• 0"""'1
~;o
~c:

TEST

PARAMETER

FIGURE

TEST CONDITIONSt

Os:
VIH

High-level input voltage

1,2

Z

VIL

Low-level input voltage

1,2

VIK

Input clamp voltage

Vee = MIN,

1

Vee- MIN,

IVI="',

Ii0H - MAX

VOL Low-level output voltage

2

Vee- MIN,

VI="',

Ii0L = MAX

Input current at maximum input voltage
High-level input current

IlL

Low-level input current

Data input
Strobe of '23
Data inputs
Strobe of '23

SERIES 74H

TYP+

MAX

MIN

TYP+

4

Vee- MAX,

iVI = 5.5 V

4

Vee = MAX,

VIH = 2.4 V

5

Vee = MAX,

VIL = 0.4 V

lOS

Short-circuit output current.

6

Vee= MAX

lee

Supply current

7

Vee= MAX

MAX

0.2

MIN

TYP+ MAX
V

2
0.8

-1.5
3.4

0.8

-1.5
2.4

0.4

UNIT

'H53, 'H55

2

II = §
2.4

'H50, 'H52

'50, '53

0.8

3

II

SERIES 54H

SERIES 74

2

VOH High-level output voltage

IIH

SERIES 54

'23
MIN

[TI

3.4
0.2

2.4
0.4

0.2

V

0.4

V
V

1

1

1

40

40

50

160
-1.6

-1.6

-2

-6.4
154 Family

-20

-55

-20

-55

-40

-100

174 Family

-18

-55

-18

-55

-40

-100

See table on next page

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§ II = -12 mA for SN54'/SN74' and -8 mA for SN54H'/SN74H'.
"'The input voltage is V I H = 2 V or V I L = V I L max, as appropriate. See tables with test figures 1 and 2.
.Not more than one output should be shorted at a time, and for the SN54H'/SN74H', duration of short-circuit should not exceed one second.

en

W

I

I
I

mA
}.LA

m
I

mA
I
I
mA
mA

--

i

V

-1.5
3.4

- - -

tc

MAX

54 Family

~;CJ)

CJ)

NOM

74 Family

~8Z

"""'I

UNIT

'H53, 'H55

5

NOM

-800

Low-level output current, 10L

'H50, 'H52,

4.5

High-level output current, 10H

g
~

SERIES 74H
'50, '53

54 Family

MIN
Supply voltage, Vee

SERIES 54H

><
"'a

>
Z
C

>

CCI

r-

""
C')

!i
m
en

I

en

J:,.

CI

electrical cnaracterlStlCS uSing expanaer mputS,

vee = lVIII\!,

IX (rnA)
TYPE

I

A

= IVIII\!

VBE{Q) (V)

(Ix for 'H52)

Base-emitter voltage of

Expander current

output transistor Q

m

\UnleSS OtnerWlse nOteo}

><

."
~

VOH{V)

VOL (V)

High-level output Ifoltage

Low-level output voltage

Z

TEST CONDITIONS MIN TYP+MAX TEST CONDITIONS MIN TYP+ MAX TEST CONDITIONS MIN TYP+ MAX TEST CONDITIONS MIN TYP+ MAX
SN5423

VXX = 0.4 V,

-3_5

SN5450

IOL = 16mA,

-2_9

IX + IX= 410/lA,
RXX = 0,

1-1

IOL = 16 rnA,

><

-I

»

~

~ (J)
a z_

m -

~8z
~~(J)

Os::

(J)

3.4

RXX = 114n'"
IOL = 16mA,

-2.9

See Figure 11

See Figure 12

See Figure 11

VXX = 0.4 V,

-3.8

IX + IX = 620/lA,

IX = 270/lA,

IX + IX = 430 /lA,

RXX =0,

IX= -270/lA,

RXX = 105 n'"

SN54H50,
SN54H53,
SN54H55
SN74H50,
SN74H53,
SN74H55

IOL = 16 rnA,

-3.1

See Figure 10

-3.1

= 1.4 V,

Vx

1

IOL = 16 rnA,

IX=O,
IOL =0,

See Figure 12

IX + IX = 700/lA,

IX = 320 /lA,
IX = -320 /lA,
1.1

IOL = 20 rnA,

3.4

IOL = 16mA,

3.4

RXX = 68n,
IOL = 20 rnA,

IX+IX=1.1mA,

IX = 570/lA,

IX + IX = 600 /lA,

IX=O,

RXX = 0,

IX = -570/lA,

RXX = 63 n,

-6.3

IOL = 0,

SN74H52

See Figure 13

See Figure 12

1

IOL = 20 rnA,
See Figure 11

-2.7

-4.5

-2.9

-5.35

+AII typical values are at Vee

5 v, T A

=

3.4

2.4

25° e.

for ·SN5423, 138 n-fo-r SN5450 and SN5453, 105 n for SN7423, and 130 n for SN7450lind SN7453.

ICC (rnA)

ICCH (rnA)

IceL (rnA)

Total with outputs high

Total with outputs low

Average per gate
(50% duty cycle)

TYP

MAX

TYP

MAX

'23

8

16

10

19

4.5

'50

4

8

7.4

14

2.85

TYP

4

8

5.1

9.5

4.55

'H50

8.2

12.8

15.2

24

5.85

'H52

20

31

15.2

24

17.6

'H53

7.1

11

9.4

14

8.25

'H55

4.5

6.4

7.5

12

6.00

~ Maximum values of ICC are over the recommended operating ranges of Vee
and T A; typical values are at Vee = 5 V, T A = 25° e.

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

IX = -300/lA,

See Figure 13

supply current~

IOL = 20 rnA,

3.4

IOL = 20 rnA,
TA = MAX,
See Figure 14

m

!i
m

See Figure 11

VX= 1 V,
IOH = -500 /lA,

=

2.4

~

G)

See Figure 11

See Figure 12

IOH = -500 /lA,

·RXX equals 114 n

IOH = -500/lA,

0.4

IX+IX=470/lA,
2.4

Vx = 1.4 V,

See Figure 10

0.2

See Figure 11

See Figure 11

VX= 1 V,

'53

IOH = -500 /lA,

2.4

See Figure 10

SN54H52

TYPE

IOH = -400 /lA,

See Figure 11
RXX= 0,

-5.85

!TI

Z
-I

2.4

See Figure 10

00-1

~;o
~c

IOH = -400 /lA,

SN7423

SN7453
,,~
[TI

IX= -150/lA,

IX + IX = 300 /lA,

SN5453

SN:7450

£

IX= 150/lA,

a

m
,...

en

IV

....

I\l

switching characteristics, Vee
TYPE

= 5 V, TA = 25°e

TEST CONDITIONS#

tpHL (ns)

Propagation delay time,

Propagation delay time,

low-to-high-Ieveloutput

high-to-Iow-Ievel output

MAX

TYP
'23, '50, '53

CL= 15pF, RL=400n,
Expander pins open
CL-15pF,

'50

RL-400n,

From input of '60 expander

'H50
'H52

CL=25pF,

'H53

Expander pins open

RL=280n,

'H55

,,~
~ [TI

. . ><

~

~
ID
o

»

(f1
-

'H50

CL=25pF,

schematics (each gate)

tpLH (nsl

RL=280n,

X of

TYP

vec

22

8

15

15

30

10

20

6.8

11

6.2

11

10.6

15

9.2

15

7

11

6.2

11

7

11

6.5

11

7.4

'H52

C = 15 pF (GND to

14.8

9.8

'H53

'H50, 'H53, or 'H55; or

11.4

7.4

'H55

to X of 'H521

11.4

7.7

,

vce
100

MAX

13

11

,

OUTPUT
y

STROBE

-------+-!4-,

If expander is not used,
leave X and X open.

#Load circuit and voltage waveforms are shown on page 3-10,

Z_

~8z
~~en

'23 CIRCUITS

.O....j

~;o
~c:

TYPICAL ADDED PROPAGATION DELAY TIME vs EXPANDER-NODE CAPACITANCE

o~

10

rr1

Z

....j

en

CL=25pF
RL = 280 n
TA = 25°C

t

~

t

"

::l

~

7

~

; 6
.~ 0
~ w

"
~'" 1

0..

4

'"

°
I °
I...J

~

~

.;:;

i

/

2
1

0

/

'"
Qi

g g!

.t ~

2.0

m

1.5

""CJ

><

>

~ ...J

6
~.:::

"0

SN54H50,
SN54H52,
SN54H53.
SN54H55.

10

2.5

c.
"
o ...J

~

/V

L
o

I

~

5.
g;
"g ~
o

/

~ ~ 3
"0

I- OJ>
".c

L

'" >

n

t

/

~ t

4.0 '~-~---y-----'r--"'---'-I
CL = 25 pF
3.5
R L = 280
---t---+--I-----J
TA=25°C

15

20

SN74H50
SN74H52
SN74H53
SN74H55
25

Z

1.0

CJ

I'"

~I


DaI

I

,...

...,..=

o

15

10

25

m

30

CX: or CX-Expander.Node Capacitance-pF

en

~

20

I

G')

>

If expander is not used, leave X and X open.
'50, '53 CIRCUITS

-4

Resistor values shown are nominal and in ohms.

(I)

m

I

c;n
01:0

N

•

m

Vee

><
-,:,

58

~

Z

INPUTS

Vee
1k

OUTPUT Y

a

~

....m

m

~58

S 760

INPUTS

C')

~
~

m

en
GND

,,~

~

-i

~

If expander is not used,
leave X and X open.

fT1

><

4k

>
i:i (Jl
~ z_

'H50, 'H55 CI RCUITS

,

~gz

,

~~(Jl

Vee
58
OUTPUT

.0-l

;;0

INPUTS

~c:

03::
fT1

z

OUTPUT Y

-l

••

(Jl

If expander is not
used, leave X and
open.

x:

x----------------------~

X--------------------------~
'H53 CIRCUITS

470
•

GND

'H52 CI RCUITS
Resistor values shown are nominal and in ohms.

C!

GND

;;j
-..J

schematic (each gate)

recommended operating conditions
SN5460
MIN
Supply voltage, Vee

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

125

0

70

°e

-55

Vee

UNIT!

NOM

4.5

Operating free-air temperature, T A

SN7460

OUTPUT j(
(See Note 2}

OUTPUT x
ISeeNote 1)

The '23, '50, and '53 are designed for use with up to four '60 expanders.

'60 CIRCUITS
NOTES: 1. Connect to X input of '23, '50, or '53 circuit.
2. Connect to X inout of '23, '50, or '53 circuit.
Resistor value shown is nominal and in ohms.

..

~

g tTl

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

. . ><

~
~

PARAMETER

);-

TEST
FIGURE

(J)

VIH

High-level input voltage

15

~8z
~~(J)
0°-1

VIL

Low-level input voltage

16

~

z_

;;0

On-state voltage between
VXX(on) expander outputs

15

On-state expander current

15

16

Vx = 1.1 V,

Vx = 1.1 V,

0.4

IX= 3.5 mA,

IX=O,

VX=4.5V,

Input current at
maximum input voltage

UNIT
V

0.8

V

0.4

V

Vee = 4_75 V, VIH = 2 V,
Vx = 1 V,
TA = oOe

IX= 3.8 mA,

Vee = 4_75 V, VIH = 2 V,
-0.3

VX= 1 V,

IX = 0,

mA

-0.43

TA = oOe
VCC = 4.75 V, VIL = 0.8 V,

RX = 1.2 kn,

150

VX=4.5V,

RX = 1.2 kn,

270

p.A

TA = oOe

TA=-55°e
II

TYPt MAX

2

Vce = 4.5 V, VIL = 0.8 V,
Off-state expander current

MIN

0.8

TA = -55°C

IX(off)

TEST CONDITIONS

2

Vee=4.5V, VIH = 2 V,
IX(on)

z

-I

TYPt MAX

TA = -55°C

tTl

(J)

MIN

Vee = 4.5 V, VIH = 2 V,

~c:

03:

SN7460

SN5460
TEST CONDITIONS

4

Vee=5.5V, VI=5.5V

l'

1 Vee = 5.25 V, VI = 5.5 V

mA

IIH

High-level input current

4

Vee = 5.5 V, VI = 2.4 V

40

Vee = 5.25 V, VI = 2.4 V

40

p.A

IlL

Low-level input current

5

Vee = 5.5 V, VI = 0.4 V

-1.6

Vee = 5.25 V, VI = 0.4 V

-1.6

mA

lee(on)

Supply current, expander on

7

1.2

2.5

mA

ICe(off)

Supply current, expander off

7

2

4

mA

tAli typical values are at

Vee

=

Vee=5.5V, VI=4.5V,
Vx= 0.85 V, IX=O
Vee=5.5V, VI=O,
Vx = 0.85 V, Ix = 0

5 V, T A = 25°C.

1.2

2.5

2

4

Vee = 5.25 V, VI = 4.5 V,
Vx = 0.85 V,

IX=O

Vee = 5.25 V, VI = 0,
Vx = 0.85 V,

IX= 0

m

><
-a

:1>
Z

=
m
:D

en
q')
01:=0

c...I

II

•

en

J:,.

.j::o

recommended operating conditions·

MIN
Supply voltage, Vee
Operating free·air temperature, T A

SN54H60

SN74H60

SN54H62

SN74H62

UNIT

NOM

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

125

0

70

°e

4.5
-55

m

><
~

:J:.
Z

=
m

See schematics
next page

:z:II

en

I

The 'H50, 'H53, and 'H55 are designed for use with up to four 'H60 expanders or one
'H62 expander.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST

PARAMETER

-1
[T1
><

»

FIGURE

VIH

High-level input voltage

15

VIL

Low-level input voltage

16

SN54H60, SN54H62
TEST CONDITIONS

MIN

SN74H60, SN74H62
TYP:j:

MAX

2

VX=l.lV,

a z_

:sz

On-state voltage between
VXX(on) expander outputs

~~CJ)

15

o0....j

0.4

On-state expander current

15

Vee= 5.5V, VIH = 2V,

[T1

Vx = 1.1 V,

z

0.4

IX(off)

Off-state expander current

16

VX=4.5V,

IX=O,

Input current at
maximum input voltage

IX = 6.3 rnA,

0.4

Vx= 1 V,

V
0.4

IX = 7.4 rnA,

VX= 1 V,

IX=O,

-600

JJA

TA = oOe
Vee = 4.75 V, VIL = 0.8 V,

RX=575!1,

320

4

Vee = 5.5 V, VI = 5.5 V

VX=4.5V,

RX=575!1,

570

JJA

1

rnA

TA = oOe
1

Vee = 5.25 V, VI = 5.5 V

IIH

High-level input current

4

Vee=5.5V, VI=2.4V

50

Vee = 5.25 V, VI = 2.4 V

50

JJA

IlL

Low-level input current

5

Vee=5.5V, VI=O.4V

-2

Vee = 5.25 V, VI = 0.4 V

-2

rnA

Supply current,
lee(on)

expander on
Supply current,

lee(ott)

expander off
Expander output

eX

capacitance

'H60
- 'H62
'H60

~

7
7

'H60

~

:j:AII typical values are at Vec = 5 V (except Cx), T A = 25°C.

g

Vx= 1 V,

Vee = 4.75 V, VIH = 2 V,
-470

TA = -55°e
II

V

TA=70oe

Vee = 4.5 V, VIL = 0.8 V,

en

V
0.8

Vee = 5.25 V, VIH = 2 V,

IX= 7.85 rnA,

TA = -55°e

....j

UNIT

TA = oOe

Vee = 4.5 V, VIH = 2 V,
IX(on)

MAX

Vee = 4.75 V, VIH = 2 V,

IX= 5.85 rnA,

TA=125°e

03::

TYP:j:

2

TA=-55°e
Vx= 1 V,

~;o
~c:

MIN

0.8
Vee=4.5V, VIH=2V,

'" en

ID -

TEST CONDITIONS

Vee = 5.5 V, VI = 4.5 V,

1.9

3.5

VX=0.85V, IX=O,

3.8

7

Vee=5.5V, VI=O,

3

4.5

VX=0.85V, IX=O

6

9

Vee = 5.25 V, VI = 4.5 V,

1.9

3.5

Vx = 0.85 V,

IX=O

3.8

7

Vee = 5.25 V, VI = 0,

3

4.5

Vx = 0.85 V,

6

9

IX=O

Vee, inputs, and X open;

5.4

Vee, inputs, and X open;

5.4

f= 1 MHz

6.0

f = 1 MHz

6.0 - - - -

rnA
rnA
pF
-

-.J

~

recommended operating conditions

schematics (each gate)
SN54H61

SN74H61

vcc

!

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

125

0

UNIT
OUTPUT X

(SeeNote2!

Supply voltage, Vee
Operating free-air temperature, T A

-55

70

V
De
OUTPUT X

(See Note 1)

The 'H52 is designed for use with up to six 'H61 expanders.

'H60 CIRCUITS

electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)

vee

..,
tTl

><

"'m -

>
(J)

PARAMETER
VIH

High-level input voltage

17

VIL

Low-level input voltage

18

•

o~

;fO
~c:
Os:
tTl

Z

~
(J)

TEST CONDITIONS

On-state expanderVX(on)

output voltage

17

MIN

TYP+

MAX UNIT

2

V
0.8

Vec= MIN,

o z_

~8z
~~(J)

TEST
FIGURE

V

INPUTS

OUTPUT

VIH = 2 V,

X

IX = 4.5 mA forSN54H61,

1

5.35 mA for SN74H61,

V

TA = MIN
IX(off)

Off-state expander current
Input current at

II
IIH

maximum input voltage
High-level input current

18

Vec= MIN,

VIL = 0.8 V,

VX=2.2V,

TA = MAX

50

IJ.A

4

Vee=5.5V, VI=5.5V

1

mA

4

VCC = 5.5 V, VI = 2.4 V

50

IJ.A

-2

mA

'H61 CIRCUITS

vec

IlL

Low-level input current

5

Vee=5.5V, VI=O.4V

lee(on)

Supply current, expander on

7

Vee=5.5V, VI=4.5V

lec(oft)

Supply current, expander off

7

Vec=5.5V, VI=O

eX

Expander output capacitance

Vee and inputs open,

11

16

mA

5

7

mA

5.4

f = 1 MHz

pF
OUTPUT X

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V (except CX). T A = 25 DC.

(See Note2)

' , , - - * - - OUTPUT

x

(See Note 1)

m

~GND

'H62 CIRCUITS
NOTES: 1. Connect to X input of 'H50, 'H53, or 'H55 circuit.
2. Connect to X input of 'H50, 'H53, or 'H55 circuit.
Resistor values shown are nominal and in ohms.

en
,i:.
U'1

I

><

-a
>
z

=
=
m

en

I

C'>

,i..
en

recommended operating conditions

en

I

m

'72, '73,

'70

SERIES 54/74

'109

'74

'76, '107

'111

'110

=

UNIT

m

en

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vcc

I Series 54

4.5

5

I Series 74

4.75

5

High·level output current, IOH

5.25

4.75

5

5.5

4.5

5

5.25

4.75

5

-400

IClock low
IPreset or clear low

Input hold time, th
Operating free-air temperature, T A

5.5

4.5

5

5.25

4.75

5

5.5

4.5

5

5.25

4.75

5

-sao

-400
16

16
20

20

Input setup time, tsu

.. ....,

5

16

IClock high

g
~

4.5

-400

Low·level output current, IOL
Pulse width, tw

5.5

20

4.5

5

5.25 4.75

5

-soo
16

16

30

5.5

25

5.5
5.25

V

-SOO

p.A

16

mA

U"I

-~

I

~

25

30

47

37

20

25

25

ns

25

30

20

201

25
01

20t

lOt

25
20t

25
ot

ns

51

O.

5t

6t

51

30t

ns

"'1"1

~
."

I Series 54

-55

125

-55

125

-55

125

-55

125

-55

125

-55

125

I Series 74

0

70

0

70

0

70

0

70

0

70

0

70

I

,...
"'1"1

Q
°e

I

t J,The arrow indicates the edge of the clock pulse used for reference: t for the rising edge, J, for the falling edge .

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

[TI

><

:: >

~ (J1
m o z_

72,73,

'70

TEST CONDITIONSt

PARAMETER

'109

'74

'76, '107

'111

'110

UNITI

MIN TYP:j: MAX MIN TYP:j: MAX MIN TYP:j: MAX MIN TYP:j: MAX MIN TYp:j: MAX MIN TYP:j: MAX

:8z
~~(J1
0°-1
~;o
~c:

VIH

High-level input voltage

VIL
V IK

Low-level input voltage
I nput clamp voltage

03:
VOL Low-level output voltage

[TI

Input current at
II

-I

(J1

Vce= MIN,

II = -12 mA

Vce= MIN,

VIH = 2 V,

VIL = O.S V,

10H = MAX

Vee= MIN,

VIH=2V,

VIL = O.SV,

10L = 16 mA

0.2

D, J, K, or K
IIH

High-level

Clear

input current

Preset

VCC = MAX, VI

= 2.4 V

Clock
D,J, K,or
input current

*
Preset *

Short-circuit

Series 54

Low-level
IlL

Clear

R
Vce = MAX, VI

= 0.4 V

output current· Series 74
Supply current

ICC

(Average per flip-flop)

Vce = MAX
VCC = MAX, See Note 1

2.4
0.4

0.2

-1.5

-1.5
2.4

3.4
0.4

3.4
0.2

2.4
0.4

3.4
0.2

2.4
0.4

O.S

V

-1.5

V

0.2

0.4

1

1

1

1

1

1

40

40

40

40

40

SO

SO

120

160

160

SO

SO

SO

SO

80

160

80

40

80

80

80

40

120

-1.6

-1.6

-1.6

-1.6

-1.6

-1.6

-3.2

-3.2

-3.2

-4.8

-3.2

-3.2

-3.2

-3.2

-1.6

-3.2

-3.2

-3.2

-3.2

-3.2

-3.2

-1.6

-57

-20

-57

-20

-57

-30

-85

-20

-57

-20

-57

-18

-57

-lS

-57

-lS

-57

-30

-85

-18

-57

-18

-57

26

10

20

8.5

15

9

15

20

34

V
mA

p.A

I

mA

-4.8

-20

13

14

20.5

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
+Not more than one output should be shorted at a time.
Clear is tested with preset high and preset is tested with clear high.

*

NOTE1: With a" outputs open, ICC Is measured with the
is grounded for all the others.

~

Q

and

Q outputs high

i

V

3.4

40

-1.6

Clock
lOS

0.2

0.4

VCC = MAX, VI' = 5.5 V

maximum input voltage

3.4

V

O.S

O.S

-1.5

-1.5
2.4

3.4

2

O.S

O.S

-1.5
2.4

2

2

O.S

VOH High-level output voltage

z

2

2

2

in turn. At the time of measurement, the clock input is at 4.5 V for the '70, '110, and '111; and

."

en

8
(ll

switching characteristics, Vee

= 5 V, TA = 25°e

FROM

TO

TEST

(INPUT)

(OUTPUT)

CONDITIONS

tpLH

Preset

Q

tpHL

(as applicable)

Q

tPLH

Clear

Q

tpHL

(as applicable)

Q

See Note 2

PARAMETER~

tPLH

MIN
20

f max

Clock

'74

'76, '107
TYP MAX MIN

TYP MAX MIN
35

15

15

20

-t

~

~
~

25

25

'109

'110

'111

TYP MAX MIN

TYP MAX MIN

TYP MAX

33

20

25

20

UNIT
MHz

25

16

25

25

10

15

12

20

12

18

CL = 15pF,

50

25

40

40

23

35

18

25

21

30

RL=400n,

50

16

25

25

10

15

12

20

12

18

QorQ

50

25

40

40

17

25

18

25

21

30

27

50

16

25

14

25

10

16

20

30

12

17

18

50

25

40

20

40

18

28

13

20

20

30

=

~ f max
maximum clock frequency; tpLH
propagation delay time, low-to-h igh-Ievel output; tpH L
NOTE 2: Load circuit and voltage waveforms are shown on page 3-10.

1J~
~ [TI

TYP MAX MIN

50

tPHL

=

'72, '73

'70

ns
ns
ns

=propagation delay time, high-to-Iow-Ievel output.

functional block diagrams

><

»
(IJ

z_

~8z
~;en

0°-1
~;o
~c

Os:
fTI
:z:
-I

en

< b--.---+--d

a

b

•

d

~

Q

Q

CLEAR

PRESET

~Jl

Kl~

J2

K2

CLEAR
Jl
J2

PRESET
Kl
K2

J3

K3
CLOCK

(I)

m

=

m

(I)

en

CLOCK

'72-GATED J-K WITH CLEAR AND PRESET

'7O-GATED J-K WITH CLEAR AND PRESET

See following pages for:

'73-DUAL J-K WITH CLEAR
'74-DUAL D WITH CLEAR AND PRESET
'76-DUAL J-K WITH CLEAR AND PRESET
'107-DUAL J-K WITH CLEAR

'109-DUAL J-K WITH CLEAR AND PRESET
'l10-GATED J-K WITH CLEAR AND PRESET
'lll-DUAL J-K WITH CLEAR AND PRESET

~
-....

'~
""'-'

"'"

!::
."
I

"'"
r-

Q
."
(I)

C')

~
.....

II

I

m

J:"

ClQ

en
m
:::a

functional block diagrams (continued)

0.1

at I:

m

-I

b

I.

en
(1

en

~

PRESET

~

~
CLEAR

,I

o

"'"

~
-,:,
I

"'Q"

rCLEAR

1 t

L------I

I •

1

PRESET

CLOCK

1

Q

I.

.. .....:J
£ [TI
-f

><

~

(Jl

~ :x>

r===

O-----i

K

ID -

o

Z_

~8z
~~en

CLOCK

• O....f
g~;o
~

~
~

i:!

'14-DUAL D WITH CLEAR AND PRESET

'13-DUAL J-K WITH CLEAR
'76-DUAL J-K WITH CLEAR AND PRESET
'107-DUAL J-K WITH CLEAR

~~c:

~03::
[TI

Z

-i
en
PRESET

t

CLOCK

a
•

(1

K
CLEAR

-+-1••- - - - - - - - - - - - - - - '

'lOg-DUAL

~

J-K WITH CLEAR

AND PRESET

-,:,

en

('76)

~

I\.l

functional block diagrams (continued)
0:
0:

Q

,,~
['T1

g

K

K1

J1
J2~
J3

~K2

K3

. . ><

~

>-

CLOCK

~ (JJ
om z_

:sz
~~(JJ
'0"""'1
~;o
~c:

Os:
IT!

Z

'111-DUAL J-K WITH CLEAR AND PRESET

'110-GATED J-K WITH CLEAR AND PRESET

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

"""'I

en

VCC3--

en

Req

INPUT

m

=
m

--

en
OUTPUT

IlL MAX
-1.6 rnA

-3.2 rnA
-4.8 rnA

U"I

~
-...
.....

Req NOM
4k.l1

~

.."
,...

2k.l1
1.3 k.l1

."
I

,...

.."

Q
."

~

C'l

.J;,.
CD

II

-

•

u,
c

recommended operating conditions -

:1>(1)

~SER IES 54Hn4H

'H72, 'H73,

'H71

'H74

'H76

'H78

2m
a:a
mm

UNIT

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

ISeries 54H
ISeries 74H

Supply voltage, VCC

4.5

5

4.75

5

High-level output current, 10H
Low-level output current, 10L

~

>

~

5

4.5

5

5.5

5.25 4.75
-1000

5.5

5

5.25
-500

20

20

20
15

12

Clock low
Clear or preset low

28

28
16
ot

13.5
25
lOt

28
16

16
ot

High-level data
Low·level data

ot
OJ,

LSeries 54H
I Series 74H

Operating free·air temperature, T A
j,

5

12

(TI

><

5.5 4.5
5.25 4.75
-500

12

Hold time, th

-i

5

Clock high

Setup time, tsu

'1I......:J

5

20

Pulse width, tw

g

5.5
4.5
5.25 4.75
-500

t The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

ot
OJ,

-55
j,

-55

125

0
70
for the falling edge.

0

70

IJA
mA:

I

0

ns

125

-55

125

70

0

70

0c

:8z

TEST CONDITIONSt

PARAMETER

~~(JJ
o0""'l
~;:o
~c
o~

High·level input voltage

VIL
VIK

Low-level input voltage

2

'H78

UNIT

Input clamp voltage

VOH High-level output voltage

(TI

Z

""'l

VOL Low-level output voltage

(JJ

II

VCC; MIN,

II ;-8mA

VCC= MIN,

VIH=2V,

VIL = 0.8 V,
VCC= MIN,

10H = MAX
VIH = 2V,

2.4

0.2

VIL = 0.8 V, 10L = 20mA
VCC = MAX, VI - 5.5 V

Input current at maximum input voltage
D,J, or K

IIH

Clear

High-level input current

VCC = MAX, VI

Preset

= 2.4 V

Clock
D,J,orK
Clear *
Preset *
Clock

VCC = MAX, VI

= 0.4 V

IlL

Low-level input current

lOS

Short-circuit output current.

VCC = MAX

ICC

Supply current
(Average per flip-flop)

V CC = MAX, Series 54H
Series 74H
See Note 1

-

-

-

-

0.4

3.4
0.2

2.4
0.4

3.4
0.2

a

2.4
0.4

0.2

V
mA

1
50

150

100
100

150
100

200
100

100
-2

50
-2

100
-2

100

-4

-4
-2

-8

-4
-2
-100

-40

-4
-100

-40

V
V

0.4

1
50

-4
-100

m

~.!.t

-t:a

IJA

-2
-4
-4
-100

-40

19

30

16

25

15

21

16

25

19

30

16

25

15

25

16

25

~m

~a
1

V

3.4

1
50

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
• Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
*Clear is tested with preset high and preset is tested with clear high,
NOTE1: With all outputs open, ICC is measured with the Q and outputs high in turn. At the time of measurement, the clock input is grounded,

9

0.8
-1.5

0.8
-1.5

1
50

-6
-40

I

0.8
-1.5
2.4

3.4

(I)

~~

V

2

2

2
0.8
-1.5

a

m

'H74

MIN TVP+ MAX MIN TVP+ MAX MIN TVP+ MAX MIN TVP+ MAX
VIH

I

m r-

~:a

'H72, 'H73,
'H76

'H71

I

~

:ac

-<-

--

o z_

I

m

~C")
mC")

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

(JJ

III -

:a .....
C")

I

ot
OJ,

5t
-55

m ~
I:
-t-..

-~
C"):

ns

ns

(I)

C")cn

ot

15t

125

a

V

mA

mA
mA

r-

1

c::-=
~

(I)

""
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

FROM
(INPUT)

TO

Preset

a

tPHL

(as applicable)

0

tpLH

Clear

tpHL
tPLH

TEST

(OUTPUT) CONDITIONS

f max
tpLH

schematics of input and outputs
'H71, 'H72,
TYP

25

30

MAX

~

~

43

VCC3--

MHz
20

CL = 25pF,

12

24

30

a

RL = 280 n,

6

13

20

(as applicable)

a

See Note 2

12

24

Clock

aorO

14

21

8.5

15

22

27

13

20

30

== propagation delay time,

Req

ns

INPUT

»

(JJ

z_

--

ns
ns
IlL MAX
-2mA
-4mA
-6 mA
-BmA

high·

~

~8Z
~~(JJ
•

35

EQUIVALENT OF EACH INPUT

UNIT
MAX

['TI

. . ><

~

TYP

13

~fmax == maximum clock frequency; tpLH == propagation delay time, low·to·high·level output; tpHL
to·low·level output.
NOTE 2: Load circuit and voltage waveforms are shown on page 3·10.

..

MIN

6

tpHL

g

'H74

'H73, 'H76, 'H78
MIN

functional block diagrams

Req NOM
2.B kn
1.4 kn
933 n
700 n

TYPICAL OF ALL OUTPUTS

Q~

):J

11

------VCC

Same functional block diagram
as for '74, see page 6-48,

PRESET-IJ..I-----..

o~

~;;o
~c:

03:
['TI

OUTPUT

JIA

KIA

JIB
KIB

'H74-DUAL D WITH CLEAR AND PRESET

J2B

K2B

z

~

U"I

=~
--...,

C') .....
Q

n

m

C
C')en
I

'H71-GATED J·K WITH PRESET

Q

m=

-4~

CLOCK

~
(JJ

Zen
C m

m

J2A

K2A

>

~Q

n

~~

~11
....---_.-+I-CLEAR

C')~

m~

~."

CC
rCen

1m

;!.!.t

PRESET-II-<'t-----.

.,,=
m -C')

KI

"'"C')

K2
K3

TO OTHER
F-F ('H78)

'H73-DUAL J·K WITH CLEAR
'H76-DUAL J·K WITH CLEAR AND PRESET
'H78-DUAL J·K WITH PRESET, COMMON CLEAR,
AND COMMON CLOCK

CLOCK

'H72-GATED J·K WITH CLEAR AND PRESET
C)

~

II

r-m
-::a
:'m
"'"c
ro~

."

I

en~

•

C)

U,
N

recommended operating conditions

ISERIES 54HI74H

'H101

'H102, 'H106

'H108

'H103

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

ISeries 54H
ISeries 74H

Supply voltage, VCC

5

4.75

5

5.5

4.5

5

5.25

4.75

5

5.5

4.5

5

5.25 4.75

.5

-PI

20

20

20

mA

.........

ns

::z:

Clock high

10

10

10

10

Clock low

15

15

15

15

Clear or preset low

16

16

16

16

High-level data

10~

10~

10~

10~

Low-level data

13~

13~

13~

13~

O~

O~

O~

O~

125

-55

125

-55

125

I Series 74H
arrow indicates that the falling edge of the clock pulse is used for reference.

0

70

0

70

0

70

0

70

TEST CONDITlONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VCC= MIN,

11=-8mA

VCC= MIN,

VIH = 2V,

[TJ

VIL = 0.8 V, ·IOH =-500IlA

Z

VCC= MIN,

VIH = 2V,

VIL = 0.8 V,

IOL = 20mA

VOL Low-level output voltage
Input current at maximum input voltage

IIH

High-level input current

'H102, 'H106

2.4

0.2

Preset

0

Clear

VCC = MAX,

VI = 0.4 V

IlL

Low-level input current

lOS

Short-circuit output current.

VCC= MAX

ICC

Supply current (Average per flip-flop)

VCC = MAX, See Note 1

Preset

V

-1.5

-1.5

-1.5

-1.5

V

0.2

0.4

-1
-1

-2

-1

-2

-40

-100
20

38

0.4

3.4
0.2

0.4

3.4
0.2

1

0.4
1

50

50

50

100

200

-1

0

V

100

-1

0

-1

0

-1

-2

-1

-2

-1

-2

-1

-2

-1

-2

-2

-4

-1

-2

-1

-2

-3 -4.8
-40

-100
20

38

V
mA
JlA

100

-3 -4.8
-100

-40
20

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
+AII typical values are at Vee = 5 V, T A = 25°C .
• Not more than one output should be shorted at a time, and duration of short-circuit sho'uld not exceed one second.
NOTE 1: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.

c;

2.4

100

-3 -4.8

Clock

2.4

1

100

Any J or K

1

38

mA

mA

-6 -9.6
-40
20

-100

mA

38

mA

c..
I

V

2
0.8

3.4

:a
m
a

UNIT

0.8

50
VCC = MAX, VI = 2.4 V

Clock

'H108

2

1

Any J or K

C')
C')

0.8

2.4

:a

°c

0.8

3.4

VCC = MAX, VI = 5.5 V
Clear

'H103

2

m
~

m

MIN TYP+ MAX MIN TVP+ MAX MIN TYP+ MAX MIN TVP+ MAX
2

VOH High-level output voltage

II

'H101

aC')

ns

-55

PARAMETER

~

m

125

UlOZ

......

ns

-55

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

::z:

-PI

ISeries 54H

»

en

U"I

20

~

03:

5.25

Low-level output current, 10L

Operating free-air temperature, T A

~;C
fT1C:

5

IlA

~ The

. ~~

4.75

m

en
V

-500

[TJ

~;(f)

5.25

5.5

-500

~

~_(J)
ox,.,z

5

-500

Hold time, th

><

4.5

-500

Setup time, tsu

~

5.5

UNIT

High-level output current,lOH

Pulse width, tw

~-i

4.5

en
m
:a

=-=

."'"
-,:,
I

l

I

."'"
o
-,:,

en

~

(l)

switching characteristics, Vee

= 5 V, TA = 25°e
TO

FROM

PARAMETER~

(INPUT)

schematics of inputs and outputs
TEST

(OUTPUT) CONDITIONS

f max

tPLH

QorQ

Preset or clear
Preset or clear !clock high)

tpHL
tpLH

Preset or clear (clock low)
Clock

CorQ

MIN

TYP

40

50

See Note 2
QorQ

tpHL

MHz

8

12

15

20

23

35

10

15

16

20

CL = 25pF,
RL=280n,

MAX UNIT

ns
ns

EQUIVALENT OF EACH INPUT

veea-Req

INPUT

-'-

ns

~fmax

== maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel
tpH L == propagation delay time, high-to-Iow-Ievel

output
output
Load circuit and voltage waveforms are shown on page 3-10_

NOTE 2:

g"-1
[T1

functional block diagrams

Req NOM
1.3 kn

-9.6 mA

650

4kn

n

en
m

TYPICAL OF ALL OUTPUTS

.. ><
~

IlL MAX
-2 mA

-4.8 mA

a+---<

»

=:I

Vee

~Q

~ (IJ
o z_

m

en

m -

U'I

:8Z

~

~~(IJ

:::c
-..
--.I

J1A

. 0-1

J1B

~C

J2A

!iC
K2B

o~
[T1

OUTPUT

~

:::c

J2B

m

CI

CLOCK

C')

Z

-I

m
I

'H101-GATED J-K WITH PRESET

(IJ

a

-4
=:I
Q

Q

C')
C')

m
m

=:I
CLEAR

Kl

Jl

K2

J2

PRESET
I'Hl06, 'Hl08)

CLEAR I

CI
~
I

=-=

J3

.."

!::

CLOCK
CLOCK

."

'H103-DUAL J-K WITH CLEAR
'H106-DUAL J-K WITH CLEAR AND PRESET
'H108-DUAL J-K WITH PRESET, COMMON CLEAR,
AND COMMON CLOCK

.."

I

'H102-GATED J-K WITH CLEAR AND PRESET

en
U,

w

II

r-

Q

."

en

II

C)

U.

recommended operating conditions

01:>0

SERIES 54L/74L

'L71

'L72, 'L73

en

'L78

'L74

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, VCC
High·level output current, 10H

Low·level output current, 10L

Series 54L

4.5

5

5.5

4.5

5

5.5

4.5

5

5.5

4.5

5

5.5

Series 74L

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

4.75

5

5.25

Series 54L

-100

-100

'-100

-100

Series 74L

-200

-200

-200

-200

Series 54L

2

2

2

2

Series 74L

Pulse width, tw

r Clear or preset low

..

Operating free·air temperature, T A

....,

><

-I

~

o

-

200

200

200

200

200

200

100

100

100

100

ot
o~

-55

125

-55

125

-55

125

-55

125

Series 74L

0

70

0

70

0

70

0

70

~

r.n

TEST CONDITIONSt

PARAMETER

Z_

°c

for the falling edge.

~8z

~~r.n
'0-1
~;:c
~c:::
o~

VIH

High·level input voltage

VIL

Low·level input voltage

VOH High·level output voltage

rr1

VOL Low-level output voltage

Z

-I

'L71
2

All other inputs
VIH; 2 V,

Series 74L

VIL; VIL max, 10H; MAX

Series 54L

VCC; MIN,

Series 74L

VIL; VIL max, 10L; MAX

2.4
2.4

VIH; 2 V,

3.3

II

Input current at

Clear

maximum input voltage

Preset

VCC; MAX,

3.2
0.15
0.2

VI; 5.5 V

Clock

IIH

IlL

High-level input current

Low-level input current

2.4

3.3
0.15

0.4

0.2

2.4

3.3
3.2

0.3

0.15

0.4

0.2

2.4

3.3
0.15

0.4

0.2

0.3
0.4

100

100

100
400

200

200

300

200

200

200

200

200

200

200

400

10

10

10

10

20

20

30

40

Preset

VCC; MAX,

VI; 2.4 V

20

20

20

20

Clock

-200

-200

20

-400

R, S, J, K, or 0

-0.18

-0.18

-0.18

-0.18

Clear

-0.36

-0.36

-0.36

-0.72

-0.36

-0.36

-0.18

-0.36

-0.36

-0.36

-0.36

-0.72

Preset

VCC; MAX,

VI;0.3V

Short-circuit output current

-3

VCC; MAX
VCC; MAX,

See Note 1

-15
0.76

1.44

-3

-15
0.76

1.44

-3

-15
0.8

1.5

-3
0.76

V
V

3.2

0.3

100

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditiOns.
tAli typical' values are at VCC ; 5 V, T A = 25° C.
NOTE1: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.

o

2.4

R, S, J, K, or 0

~_ Supply curr~~(Average per flip-flop)

-..I

0.7

0.7
2.4

3.2

0.3

0.6

Clear

Clock
lOS

2.4

UNIT
V

2
0.7

0.7

0.7
VCC; MIN,

'L78

2
0.6

0.6

Series 54L

'L74

2

Clock input

R, S, J, K, or 0

r.n

'L72, 'L73

MIN TYPt MAX MIN TYpt MAX MIN TYPt MAX MIN TYPt MAX

m

=
m
en

U'I
~

r-..
--..
~

r-

ns

Series 54L

t ~ The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

mA

ns

o~

15t

Il A

ns

ot

50t

V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

;l>

~
ID

200

o~

Hold time, th

g rr1

200

ot

Setup time, tsu

3.6

3.6

3.6

3.6

I Clock high
I Clock low

UNIT

V

/lA

IlA

mA

-15

mA

1.44

mA

.."

~
."
I
.."

r-

Q

."

en

o....
Cll

switching characteristics, Vee = 5 V, TA = 25°e
FROM

PARAMETER~

TO

(INPUT)

(OUTPUT) CONDITIONS

OorQ

Preset or clear
Preset or clear (clock high)

tPHL

Preset or clear (clock low)

tPLH

OorO

MIN

CL = 50 pF,
RL=4kn,
See Note 2

OorO

Clock

'L74

'L73, 'L78
TYP

2.5

f max
tpLH

schematics of inputs and outputs

'L71, 'L72,

TEST

tpHL

MAX

MIN

3

TYP

UNIT
MHz

35

75

50

75

60

150

80

150

200

80

150

15

65

100

15

65

150

10

35

75

10

60

150

EQUIVALENT OF
EACH INPUT

MAX

3

2.5

vee~--

ns

Req

ns

INPUT·

-

~fmax

=::; maximum clock frequency
tpLH =::; propagation delay time, low-to-high-Ievel output
tpH L =::; propagation delay time, high-to-Iow-Ievel output
NOTE 2: Load circuit and voltage waveforms are shown on page 3-11.

g""-1
['TI

. . ><
~ >
~ (J)
~ z....
~8z
~~(J)
0-i

~iC

~c:

03:
['TI

z

--

ns

IlL MAX

Req NOM

-0.18 mA
-0.36 mA

40 kn

-0.72 mA

10 kn

20 kn

PRESET~

TYPICALOF
ALL OUTPUTS

functional block diagrams
CLEAR~

Q

Vee

,"m~

~"M
CLOCK

Rl

SI

~

~

(j

I II

U

~

CLOCK

-i

'L71-GATED R-S WITH CLEAR AND PRESET

(J)

en

'L74-DUAL D WITH CLEAR AND PRESET

m

=
en
m

UI

,"m~

,,~~:,:

m,

~"M
TO OTHER
F-F ('L7B)

K1

Jl

u

n

CLOCK

CLOCK

,...

J

~

TO OTHER

."

F-F ('L7B)

,...
Q
I

."

'L72-GATED J-K WITH CLEAR AND PRESET

'L73-DUAL J-K WITH CLEAR
'L78-DUAL J-K WITH PRESET, COMMON CLEAR,
AND COMMON CLOCK

en
U,
U1

~

.....
~

."

K

n

~

,...
-..

II

."

en

II

C)

u,

C)

en

recommended operating conditions
L-~~~~--+-~~~~~~~~~~~~~~~~~~~~~~~~~~UNIT

I Series 54LS
I Series 74LS

Supply voltage, Vee

4.5

5

5.5

4.5

5.5

4.5

5.5

4.75

5

5.25

4.75

5.25

4.75

5.25

High-Ievel'output current, 10H

~ 1

1Series
54LS
Senes 74LS

Low-level output current. IOL

I Preset or clear low

~

3
~

~ 1 rnA

-I
25

~

20t

20

~

20~

35t

20~

20 t

20

~

20

~

25t

o~

5 t

,--55

The arrow indicates the edge of the clock pulse used for reference:

251 MHz

30

25
25

20

I Low-level data

30

20

125

t

20

25

o~

I-55

en

§ ~ en

70

1251-55

0

~·C

1251-55

70

70

70

.....
~

"'"

!::
"a

for the rising edge, l for the falling edge.

I

"'"
~

TEST eONDITIONSt

"a

I

2

I V

Vi H

High·level input voltage
Low-level

Series 54LS

VIL

input voltage

Series 74LS

VIK

Input clamp voltage

Vec = MIN,

11=-1SmA

High-level

Series 54LS

Vee= MIN,

VIH= 2V,

2.5

3.4

2.5

3.4

2.5

3.4

2.5

3.4

2.5

output voltage

Series 74LS

VIL = VIL max,

10H = -400 "A I

2.7

3.4

I 2.7

3.4

I 2.7

3.4

I 2_7

3.4

I 2.7

VOH

0.7

0.7

0.7

0.7

0.7

O.S

O.S

O.S

O.S

O.S

-1.5

-1.5

-1.5

-1.5

-1.5

'" 0";

~ ~ ;0
~ ~ c::

[;; c ~
l'T1
~
Z

3.4

V
V
V

3.4
0.25
0.35
0.25

VOL Low-level
output voltage

0.4
0.5
0.4

V

0.1

~

Input current

at maximum

~:;":""'_--1Vee=MAX,

Vl

z

0.2
0.2

7V

input voltage

mA

0.1

..;

on

'"enon

~

en
-...

C)

PARAMETER

13 z _
~ 8z

CJ)

U'I

~

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

-l
l'T1
><
:>

m

en

en

5t

01

1251-55

70

2l

--400 I "A

25
25

25

LHigh-level data

Hold time, th

tl

-I

25

20

Operating free·air temperature. T A

--400

~

I Clock high

Setup time, tsu

--400

~1

30

Clock frequency. 'clock
Pulse width, tw

--400

--400

V

m

:II

20

(IJ

High-level
IIH

input current

1-------1 Vee = MAX,

40
40

VI = 2.7 V

"A

20
-0.4
Low-level
IlL

input current

~=------1 Vee = MAX,

=~::

VI = 0.4 V

mA

-0.4
lOS
Supply current

ICC

(Total)

Vce = MAX,

See Note 1

Vce = MAX,

See Note 2

-20

-20

tFor conditions shown 8S MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical valuelare at Vee = 5 V. T A = 25°c.
·Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
NOTES:

;;

1. For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed with Va = 2.25 V and
2.125 V for the 54 family and the 74 family, respectively. with the minimum and maximum limits reduced to one half of their Stated values.
2. With all outputs open, ICC is measured witH the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.

-100
-100

mA

SI mA

en

~

switching characteristics, Vee
PARAMETER II

TO

TEST

(INPUT)

(OUTPUT)

CONDITIONS

Clear, preset, or

tpHL

I

clock (as appropriate)

~fmax

'LS107A:LSl12A,

I

I
I

CL:15pF,
Oar Q

schematics of 'LS74A and 'LS109A

'LS73A:LS76A:LS78A,

FROM

tPLH

f max

= 5 V, TA = 25°e
'LS74A, 'LS109A

'LSl13A:LSl14A
MIN

TYP

30

45

MAX

MIN

TYP

25

33

,

IUNIT

Vee

MAX

I

RL = 2 kll,

15

20

13

25

See Note 2

15

20

25

40

MHz

== maximum

clock frequency
time, low-to-high-Ievel output
high-to-Iow-Ievel output
NOTE 2: Load circuit and voltage waveforms are shown On page 3-11.
tpLH
tpH L

== propagation delay

== propagation delay time,

functional block diagrams and schematics of inputs and outputs
~
tTl

25
~

~

nm

>

OJ

_(J)

0

Z

ov

oZ

x

.
~

~rn

.~

03::

x
~
ov
en

'"

;- - -

';
-----------4--------,
I

tTl

(J)

'LS74A-DUAL D WITH CLEAR AND PRESET

I

~

CLOCK

~c:

Z
..;

fgtE~T 'LS113AI

I

0";

~;o

-;

PRESET

n-

0

~

Q

><

TO OTHER F·F

,

('LS78A,'LS114AI

'LS76A, 'LS112A-DUAL J-K WITH CLEAR AND PRESET

en
m
:::a
m
en

'LS78A, 'LS114A-DUAL J-K WITH PRESET, COMMON CLEAR,
AND COMMON CLOCK

o

'LS113A-DUAL J-K WITH PRESET
'LS73A, 'LS76A, 'LS78A, 'LS107A, 'LS112A, 'LS113A, 'LS114A
EQUIVALENT OF
EACH INPUT

vec

Req

INPUT

TYPICAL OF
ALL OUTPUTS
120

n

U"I
~
~

Vee

en
-....
.....

NOM

oI=b

--

IlL MAX

Req NOM

-0.4 mA

17 kn

-0.8 mA
-1.6 mA

8,25 kn

~

en
~

OUTPUT

t:
~
I

~
~

o

~

4.1 kn
'LS109A-DUAL J-K WITH CLEAR AND PRESET

C'l

....

Vee

'LS73A, 'LS107A-DUAL J-K WITH CLEAR

U.

II

en

II

C1

U,
CO

recommended operating conditions

I SERIES 54S174S

'S74

'S112

'S113

I

'S114

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

I Series 54S
I Series 74S

Supply volt\lge, VCC

~
~

5.5

4.5

5

5.5

4.5

5

5.5

5

5.25

4.75

5

5.25

4.75

5

5.25

V
rnA

Low·level output current, 10L

20

20

20

20

rnA

Clock high

6

6

6

6

Clock low

7.3

6.5

6.5

6.5

Clear or preset low

7

8

8

8

High-level data

3t

31-

3j.

3j.

3t

3j.

3j.

3j.

Low-level data

2t

I Series 54S
I Series 74S

OJ.

OJ.

125

-55

125

-55

125

0

70

0

70

0

70

r-

ns
ns
125

0

70

°c

--

for the falling edge.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

oED z
_

~8z
~~(J)
0°-1
~;o
~c:

TEST CONDITIONSt

PARAMETER

03:
(TI

VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH High-level output voltage

z

-I

II

lOS

Short·circuit output current.

0.8

V

-1.2

-1.2

-1.2

-1.2

V

VIH = 2 V,

2.5

3.4

2.5

3.4

2.5

3.4

2.5

3.4

Series 74S

VIL = 0.8 V,

10H = -1 rnA

2.7

3.4

2.7

3.4

2.7

3.4

2.7

3.4

VCC - MIN,

VIH = 2V,

VIL = 0.8 V,

10L = 20 rnA

VCC = MAX,

0.5

VI = 5.5 V

Clear
Preset

VCC = MAX,

VI = 2.7 V

Clear *
Preset *

VCC = MAX,

VI = 0.5 V

VCC= MAX
VCC = MAX, See Note 1

-40

0.5

1
50

1

1

1

50

50

50

150

100

100

100

o

0.5

200
100

100

100

100

100

200

-2

-1.6

-1.6

-1.6

-6

-7

-4

-7

-7

-7

-4

-4

-4

-8

-100
15

V

0.5

25

-40

-100
15

25

V
rnA

J.lA

-14

-40

-100
15

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
+AII typical values are at V CC = 5 V, T A = 25° C.
·Not more than one output should be shorted at a time, and duration of short-circuit should not exceed one second.
*Clear is tested with preset high and preset is tested with clear high.
NOTE1: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.

;;:

V

0.8

VCC= MIN,

Clock
~c::_~pply current (average per flip-flop)

2

0.8

Series 54S

Clock

Low-level input current

2

UNIT

0.8
II =-18mA

J, K,or 0
IlL

'S114

VCC = MIN,

Input current at maximum input voltage

High-level input current

'S113

2

J, K, or 0
IIH

'S112

MIN TYP+ MAX MIN TYP+ MAX MIN TYP+ MAX MIN TYP+ MAX
2

VOL Low-level output voltage

(J)

'S74

25

-c:n
.....,
~
c:n
-ft

-55
----

j.

ns

OJ.

-55

U'I
~

-1

t j. The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

»

5

4.75

-1

Operating free-air temperature, T A

(J)

4.5

5.25

-1

Input hold time, th

><

5.5

5

-1

Input setup time, tsu

-i

5

High·level output current, 10H

Pulse width, tw

,,~
~ [TI

4.5
4.75

UNIT

c:n
m
:a
m
c:n

-40
15

rnA

-100

rnA

25

rnA

-a
,
-ft

r-

Q

-a

c:n

s
Cll

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e
TO

TEST

(INPUT)

(OUTPUT)

CONDITIONS

'S74

f max
Preset or clear

tPLH

Preset or clear !clock high)
tpHL

Preset or clear (clock low)

tPLH

Clock

QorQ
QorQ

MIN

TYP

75

110

CL=15pF,
RL=280n,
See Note 2

QorQ

tpHL

'Sl12, 'Sl13, 'Sl14
MAX

MIN

TYP

80

125

4

MAX

UNIT
MHz

4

6

9

13.5

5

7

5

8

5

7

6

9

4

7

6

9

5

7

7

ns
ns
ns

tpLH '" propagation delay time, low-to-high-Ievel output
tpH L '" propagation delay time, high-to-Iow-Ievel output
NOTE 2: Load circuit and voltage waveforms are shown on page 3-10.

-i
[TI

><

'"
~

z...

~8z
~~(J)

0-1
~;o

EQUIVALENT OF EACH INPUT

v cc

c
Req

INPUT

IlL MAX
-1.6 mA
-2 mA
-4mA
-6 mA
-7 mA
-8 mA
-14mA

~fmax '" maximum clock frequency

>
(J)

-

schematics of inputs and outputs

FROM

--

Req NOM
4kn
2.8 kn
1.4 kn
940 n
900 n
700 n
450 n

TYPICAL OF ALL OUTPUTS

functional block diagrams

------<_-v CC

PRESET~

OUTPUT

~c:

03:

CLEAR

-+-----l

[TI

z

PRESET

-I

(J)

CLOCK

1 I.
CLOCK

en
m

=
m
en

U'I
~

'S74-DUAL D WITH CLEAR AND PRESET

'S112-DUAL J-K WITH CLEAR AND PRESET
'Sl13-DUAL J-K WITH PRESET
'Sl14-DUAL J-K WITH PRESET, COMMON CLEAR,
.l\.ND COMMON CLOCK

en

......
--.pa
en
~

~
"'a
I

~

r-

o

"'a

en

C'l

U,

cc

II

11

~
Q

enl
I
:1:11

recommended operating conditions

Supply voltage, Vee

54 FAMILY

SN54279

SN54LS279

74 FAMILY

SN74279

SN74LS279

MIN

NOM

MAX

MIN

NOM

MAX

54 Family

4.5

5

5.5

4.5

5

5.5

74 Family

4.75

5

5.25

4.75

5

5.25

High-level output current, IOH
54 Family

Low-level output current, 10L

74 Family

Operating free-air temperatu re, T A

;g
~

~

nm

CD

0

x

'"

~

.
c

X

~

"'"
m
'"
'"

-800

-400

16

4
8

16

~

54 Family

-55

125

-55

125

74 Family

0

70

0

70

n
:::c
m
en

V
IJA
mA
°e

electrical characteristics over recommended free-air operating temperature range (unless otherwise noted)

-;
('T1

SN54LS279

SN54279

><

»

TEST eONDITIONSt

PARAMETER

MIN

z_

VIH

8z

VIL

~;o

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

LOW-level output voltage

o~

03::

Low-level output voltage

~

MIN

V

2
0.8

0.7

74 Family

0.8

0.8
-1.5

-1.5

II = §
VIH=2V,

54 Family

2.4

3.4

2.5

3.4

VIL = VIL max,

10H =MAX

74 Family

2.4

3.4

2.7

3.4

/IOL = MAX

VIL = VIL max,

I~

Input current at maximum input voltage

Vee=MAX

IIH

High-level input current

Vee=MAX

IlL

Low-level input current

Vee = MAX,

lOS

Short-circuit output current.

Vee = MAX

lee

Supply current

Vee = MAX,

\IOL=4mA

0.2

0.4

0.25

0.4

74 Family

0.2

0.4

0.35

0.5

0.35

0.4

Series 74LS
VI = 5.5 V

1
0.1
40

VI = 2.4 V

20

VI=2.7V

-0.4

-1.6

VI = 0.4 V
54 Family

-18

-55

-20

-100

74 Family

-18

-57

-20

-100

18

30

- - -

3.8

V
V
V

54 Family

VI =7V

See note 1

UNIT

MAX

54 Family

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°e.
§II = -12 rnA forSN54'/SN74' and -18 rnA forSN54LS'/SN74LS' •
• Not more than one output should be shorted at a time, and for SN54LS'/SN74LS', duration of the output short circuit should not exceed one second.
NOTE1: lee is measured with all R Inputs grounded, all S inputs at 4.5 V, and all outputs open.

;;;

TYP+

Vee = MIN,

VIH =2V

C/l

MAX

Vee = MIN,

Vee = MIN,

f'1"J

Z

TYP+

2

High-level output voltage

~C/l

SN74LS279

SN74279

_C/l

~ ~c:::

.~
;;l

,...

UNIT

7

V

mA
IJA
mA
mA
mA

I

""

switching characteristics, Vee

=5 V, TA = 25°e

PARAMETER
tPLH

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output from S input

tPHL Propagation delay time, high-to-Iow-Ievel output from S input
tPHL

Propagation delay time, high-to-Iow-Ievel output from R input

'279

'LS279

MIN TYP MAX MIN TYP MAX
12

eL;15pF,
See Notes 2 and 3

22

12

UNIT

22

9

15

13

21

15

27

15

27

ns

NOTE 2: Load circuit and voltage waveforms are shown onpages 3-10 and 3-11.
NOTE 3: RL; 400 n for '279, RL ; 2 kn for 'LS279.

schematics of inputs and outputs

,,-i
g IT!

-<
><
~~ (f1
>

'279 CIRCUITS
EaUIVALENT OF EACH INPUT

I

'LS279 CIRCUITS

TYPICAL OF ALL OUTPUTS

EaUIVALENT OF

R INPUTS I

EQUIVALENT OF ~ INPUTS

TYPICAL OF ALL OUTPUTS

oCD z_

:8z
~~(f1
0°-1
~;:o
~c:

03::
IT!

z

120 n
NOM

Vee
Vee
Vee

INPUT~

~-- I

, 17kn

I

•
OUTPUT

!,

Vee

NOM

INPUT ,

H

__

INPUT ,

~

f

Vee

17 kn

~O~

OUTPUT

-I
(f1

enl
I

::a 1
r-

~

-4

n

=
m
en

~

~

II

SN54LS63, SN74LS63
HEX CURRENT·SENSING INTERFACE GATES
WITH TOTEM·POLE OUTPUTS

•

Translates low-level input current to
low-level output voltage

•

Translates high-level input current to
high-level output voltage

•

Interfaces to PLA's or other logic
elements that source current but do
not sink current

•

Operates from a single 5 V supply

•

TTL compatible

•

Low power dissipation ...40 mW
typical

SN54LS63 ••• J OR W PACKAGE
SN74LS63 ••• J OR N PACKAGE

Vcc

6A

6Y

5Y

5A

4A

4Y

lA

1Y

2Y

2A

3A

3Y

GNO

description
Each of these Schotty-clamped interface gates is able
to discriminate between low·level (~ 50 llA) and
high·level (;;;. 20011A) input currents.
logic: Y = A

The outputs are fabricated with standard Low·Power
Schottky design rules and are compatible with all
TTL families.

schematic (each gate)

•

.----.--------~~---Vee

Bk

8k

120

L-.-_-"__ Y
A

-~

__- - _ f

12 k

~--~--'-~~--~~--GND

Resistor values shown are nominal and in ohms.

recommended operating conditions
SN54LS63
Supply voltage,

Vee

SN74LS63

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V
J1A

High·level output current, IOH

-400

-400

Low·level output current, IOL

4

8

rnA

I nput current, II

1

1

rnA

Operating free·air temperature, T A

-55

125

0

70

°e

1076

6-62

TEXAS

(NSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SNS4LS63, SN74LS63
HEX CURRENT·SENSING INTERFACE GATES
WITH TOTEM·POLE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

SN54LS63

TEST CONDITlONSt
II = 50/lA,

Vce= MIN

II = 200/lA,

Vee = MAX

VI

Input voltage

VOH

Hig,-Ievel output voltage

Vee=MAX

II = 2oo/lA

VOL

Low-level output voltage

Vee = MIN,

II =50/lA

lOS

Short-circuit output current §

Vee = MAX

11=6oo/lA

ICC

Supply current

Vee = MAX,

See Note 1

I

MIN TYP~

MAX

0.35

1.05

1.75

0.6

1.05

1.6

0.6

1.30

2

0.85

1.30

1.8

3.5

10H = -400/lA,

I

SN74LS63

MIN TYp:j: MAX

3.2

3.4
0.25

10L =4 mA

0.4

0.35

10L = 8 mA
-20

-100
8

-20

16

8

V
V

3.4
0.25

UNIT

0.4
0.5

V

-100

mA

16

mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:j:AII typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of output short circuit should not exceed One second.
NOTE l' ICC is measured with inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e
TEST CONDITIONS MIN

PARAMETER
tPLH Propogation delay time,low-to-high-level output
tPHL Propogation delay time, high-to-Iow-Ievel output

TYP MAX UNIT

eL= 15pF,

27

45

ns

RL = 2 kU

15

25

ns

PARAMETER MEASUREMENT INFORMATION

•
I

Vee

OUTPUT

Vee

INPUT~~----. .~--~

8kU

.-----...-----4.-- GND
NOTES:

B. CL includes probe and jig capacitance
b. Alidiodesare1N9160r1N3064

TEST CIRCUIT

VOLTAGE WAVEFORMS

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BQ_X 5012 •

DALLAS. TEXAS 75222

6·63

TYPES SN54121, SN54L121, SN74121, SN74L121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
•

Programmable Output Pulse Width
With R int ... 35 ns Typ
With Rext/Cext ... 40 ns to 28 Seconds

•

Internal Compensation for Virtual
Temperature Independence

•

Jitter-Free Operation up to 90%
Duty Cycle

•

Inhibit Capability

SN54121 ••• J'OR WPACKAGE
SN54L 121 ••• J OR T PACKAGE
SN74121,SN74L121 ••• J OR N PACKAGE
VCC

NC

NC

Rextl
Cext

Cext

Rint

NC

FUNCTION TABLE
OUTPUTS

INPUTS
A1

A2

B

Q

Q

L

X

H

L

H

X

L

H

L

H

X

X

L

L

H

H

H

X

L

..n.

H

..n..

U

..n..

L.f
LS

H

~

H

~

H

H

~

~

H

L

X

x

L

t
t

positive logic: See function table
NC-No internal connection

..Jl.. l....S

..n..

-NOTES: 1. An external capacitor may be connected between
Cext (positive) and Rext/Cext.
2. To use the Internal timing resistor, connect Rlnt
to VCC' For Improved pulse width accuracy and
repeatability, connect an external resistor between
Rext/Cext and VCC with Rlnt open-circuited.

L.f

For explanation of function table
symbols, see page 3-8.

description

II

These multivibrators feature dual negative·transition-triggered inputs and a single positive-transition-triggered input
which can be used as an inhibit input. Complementary output pulses are provided.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse.
Schmitt-trigger input circuitry (TTL hysteresis) for the B input allows jitter-free triggering from inputs with transition
rates as slow as 1 volt/second, providing the circuit with an excellent noise immunity of typically 1.2 volts. A high
immunity to VCC noise of typically 1.5 volts is also provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the inputs and are a function only of the timing
components. Input pulses may be of any duration relative to the output pulse. Output pulse length may be varied from
40 nanoseconds to 28 seconds by choosing appropriate timing components. With no external timing components
(i.e., Rint connected to VCC, Cext and Rext/Cext open), an output pulse of typically 30 or 35 nanoseconds is achieved
which may be used as a doc triggered reset signal. Output rise and fall times are TTL compatible and independent of
pulse length.
Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature.
In most applications, pulse stability will only be limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 JlF) and more than one decade of timing resistance (2 kn to 30 kn for the
SN54121/SN54L121 and 2 kn to 40 kn for the SN74121/SN74L121). Throughout these ranges, pulse width is
defined by the relationship tw(out) = CextRTln2 ~ 0.7 CextRT. In circuits where pulse cutoff is not critical, timing
capacitance up to 1000 Jl F and timing resistance as low as 1.4 kn may be used. Also, the range of jitter-free output
pulse widths is extended if Vee is held to 5 volts and free-air temperature is 25°e. Duty cycles as high as 90% are
'achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pUlse-width
jitter is allowed.
1076

6·64

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54121, SN54L121, SN74121, SN74L121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER- INPUTS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF BOTH OUTPUTS
--~....- - - - Vce

Vce------~.------

Req
Req

INPUT

....- - - - - OUTPUT

Req NOM

INPUT
A1
A2
B

'121
4kn
4kn
2 kn

'L121
8kn
8kn
4kn

'121: Req
'L121 : Req

~
~

130 n NOM
260 n NOM

recommended operating conditions
154 FAMILY
74 FAMILY

Supply voltage, Vce

SN54L121

SN74121

SN74L121

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.5

5

5.5

174 Family

4.75

5

5.25

4.75

5

5.25

16

Low-level output current, IOL

I

Rate of rise or fall of input pulse, dv/dt 1

Logic inputs, A1, A2

Input pulse width,twOn)
External timing resistance, Rext

I

1

1

50

100

1.4

40

1.4

40

0

1000

0

1000

174 Family

67

RT - 2 kn

1 RT ~ MAX R ext

Operating free-air temperature, T A

30

67

90

p,A
mA

ns

1.4

1.4

V

VIs
V/p,s

30

154 Family

External timing capacitance, Cext

8
1

1

Schmitt input, B

MAX

-200

-400

•
I

UNIT

154 Family

High-level output current, IOH

Duty cycle

SN54121

90

154 Family

-55

125

-55

125

174 Family

0

70

0

70

kn
p,F

%
°e

1076

TEXAS INCORPORATED
(NSTRUMENTS
POST OFFICE BOX 5012 •

OAL.L.AS. TEXAS 75222

6-65

TYPES SN54121, SN54L121, SN74121, SN74L121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TR-IGGER -INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L 121

SN54121
TEST CONDITIONSt

PARAMETER

SN74121
SN74L 121
UNIT
MIN TYp:j: MAX MIN TYp:j: MAX
1.4

1.4

2

2

VT+

Positive-going threshold voltage at A input Vee = MIN

VT-

Negative-going threshold voltage at A input Vee= MIN

VT+

Positive-going threshold voltage at B input

VT-

Negative-going threshold voltage at B input Vee = MIN

VIK

Input clamp voltage

Vee = MIN,

11=-12mA

VOH

High-level output voltage

Vee = MIN,

10H = MAX

VOL

Low-level output voltage

Vee = MIN,

10L = MAX

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5V

High-level input current

Vee = MAX,

A10rA2

40

20

IIH

VI = 2.4 V

B

80

40

Vee= MAX,

A10rA2

-1.6

-0.8

VI = 0.4 V

B

-3.2

-1.6

IlL
lOS
ICC

Low-level input current
Short-circuit output current.

0_8

1_55

Vee = MIN
0.8

Vee = MAX

Supply current

Vee = MAX

0_8

1.4
2

1.55
0.8

1.35

2.4

0.2

0.4

0.2

0.4
1

54 Family

-20

-55 -10

74 Family

-18

-55

-27

-9

V
V

3.4

1

V
V

-1.5
2.4

3.4

2

1.35

-1.5

V
V

1.4

-27

Quiescent

13

25

7

12

Triggered

23

40

9

20

V
mA
IJA
mA
mA
mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e •
• Not more than one output should be shorted at a time.

switching characteristics, Vee

II

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-hightPLH

level Q output from either A input
Propagation delay time, low-to-high-

tPLH

level Q output from B input

eext = 80 pF,

tpHL

Propagation delay time, high-to-Iowlevel Q output from either A input

Rint to Vec

Propagation delay time, high-to-Iowlevel Q output from B input

CL= 15pF,

tpHL

Pulse width obtained using

RL = 800 n for 'L 121, Cext = 80 pF,
See Note 3
Rint to Vee
Cext = 0,

tw(outl

internal timing resistor
Pulse width obtained with

tw(out)

RL = 400

n

for '121,

zero timing capacitance

70

Rint to VCC
Cext - 100pF,
600
RT= 10 kn

Pulse width obtained using
tw(outl

eext = 1IJ F ,
RT= 10 kn

external timing resistor

'L 121

'121
MIN

6

TYP MAX MIN

TYP MAX

UNIT

45

70

140

ns

35

55

110

ns

50

80

160

ns

40

65

130

ns

110

150

225

260

ns

30

50

35

70

ns

700

800

600

700

850

ns

7

8

6

7

8

ms

70

NOTE 3: Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

1076

6-66

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54121, SN54L121, SN74121, SN74L121
MONOSTABLEMULTIVIBRATORS
WitH SCHMITT--TRIGGER INPUTS
TYPICAL CHARACTERISTICS§
VARIATION IN INTERNAL TIMING RESISTOR VALUE

DISTRIBUTION OF UNITS
for
OUTPUT PULSE WIDTH

i
l:l

~~~ :~~~
10 kn
(External)

~

+--+--+--\--+----1

pF

+1.0,----,-----r---r-----,

+20%

+0.51---+--+--11------1

RT =

! +10%

I---t--+--t-

/v

1

+5%

!

!

~~

~

691

694

SUPPLY VOL TAGE

~+30%

Vee' 5 V

o

o

VARIATION IN OUTPUT PULSE WIOTH

v.

FREE-AIR TEMPERATURE

697

700

703

-50 -25

0

25

50

75

vec-Supply Voltage-V

FIGURE 3
VARIATION IN OUTPUT PULSE WIDTH
FREE-AIR TEMPERATURE
'0

>I

;:

I---+-->'+-+-

1.0%

~

~

"0

>
~ 1.6 f-+--+----'>k---+--II---+--+-l

~

RT'" 10 kn (External
TA=25°C
----"1r---(
-1.0 L-_ _L--I_ _..L1_-1-_----1
4.5
4.75
5.25
5.5
5.0

FREE-AIR TEMPERATURE

1.7

Cext '" 60pF

100 125

SCHMITT TRIGGER THRESHOLD VOLTAGE

~

Vee= 5V

~ +O.5o/tn - Cr"'60pF
AT= 10kfl

a

~

1.5 f--+-~-+---l---1f:::=.-l--+---J

~

1.4

g

~

...

>I

f--+---+----'''k--+--II---+--+---I

J

1.3

<1

>
1.2 '---'-----'---'---'-----'--'---'----"
-75 -50 -25

0

25

50

75

100

./

0%

~ -0.5%

!

r7

V

125

-75 -50 -25

~

'"

S'"
a
~
J

10 ms

.....

I~

.r:

",0.'\ \lor
I-- ~t_1 I 1.1
lOOps

"3
c..

10 ps
lps

0

100 ns
10 ns

1

2

~

.........

50

75

•

100 125

E===-====

1 ms

'"

.....

'"

a.

10~s

~

a

~
J

.....

1 ~s

0

11111

~

-t-H See Note 4
7 10

100~s

"3
c..

CeJlt

3 4

25

'0

~",o.o'\\lor
I---~-I 11.1
~",,\ooor;>r
~~t
1
~",,\oor;>r
I-- ~-I I I I ",\Or;>r
Vcc = 5 V
T A = 25°C

0

OUTPUT PULSE WIDTH
vs
EXTERNAL CAPACITANCE

10 ms

1 ms

l

FIGURE 5

OUTPUT PULSE WIDTH
vs
TIMING RESISTOR VALUE

'0

420 ns
25oc

tw(out) '"

"'I TA =1

TA-Free-Air Temperature- °c

FIGURE 4

t===:=:==J= '" '\ \lor
~~t

7~

-1.0%

T A-Free-Air Temperature-°c

.r:

I

g -0.5

J
<1

FIGURE 2

FIGURE 1

'w(ou,) = 420 n.

I

TA-Free-Air Temperature- °c

tw(outl-Output Pulse Width-ns

""

I-V--::;~=!---..JI- @Vec'5V

"

>

-5%

~ -10~75

706

...-

v

..

V

./

20

40

100 ns
10ns
10-11 10-10 10-9

70100

10-B

10-7

10- 6

RT-Timing Resistor Value-kn

c ext -Timing Capacitance-F

FIGURE 6

FIGURE 7

10- 5

NOTE 4: These values of resistance exceed the maximum recommended for use over the full temperature range of the SN54L 121_

§ Data for temperatures below OOC and above 70°C are applicable for SN54121 and SN54L 121.
076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

6-67

TYPES SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMIIT-TRIGGER INPUTS

•

SN54221, SN54LS221 ••• J OR W PACKAGE
SN74221, SN74LS221 .•• J OR N PACKAGE
(TOPVIEW)-------- --

SN54221,SN54LS221,SN74221 and
SN74LS221 Are Dual Versions of Highly
Stable SN54121, SN74121 One-Shots on
a Monolithic Chip

•

SN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical
to the SN54121, SN74121 One-Shots

•

Pin-Out Is Identical to the SN54123
SN74123,SN54LS123,SN74LS123

•

Overriding Clear Terminates
Output Pulse
TYPICAL
POWER
DISSIPATION
130mW
SN54221
130mW
SN74221
SN54LS221
23mW
SN74LS221
23mW
TYPE

MAXIMUM
OUTPUT PULSE
LENGTH
21 s
28 s
49 s
70 s

vcc

1 Rextl
Cext

1
Cext

1A

1B

1
CLR

10

2
CLR

2B

2A

2 Rextl
Cext

GND

Cext

20

positive logic: Low input to clear resets Q low and
0: high regardless of doc levels at A
or B inputs_

description
The '221 and 'LS221 are monolithic dual multivibrators with performance characteristics virtually identical to those of
the '121. Each multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either
of which can be used as an inhibit input.

II

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse.
Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates
as slow as 1 Volt/second, providing the circuit with excellent noise immunity of typically 1.2 volts_ A high immunity to
VCC noise of typically 1.5 volts is also provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration
relative to the output pulse. Output pulse length may be varied from 35 nanoseconds to the maximums shown in the
above table by choosing appropriate timing components. With Rext = 2 kn and Cext = 0, an output pulse of typically
30 nanoseconds is achieved which may be used as a doc-triggered reset signal. Output rise and fall times are TTL
compatible and independent of pulse length. Typical triggering and clearing sequences are illustrated as a part of the
switch ing characteristics waveforms.
FUNCTION TABLE

Pulse
width stability is achieved through internal
compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability will only be
limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature
and VCC ranges for more than six decades of timing
capacitance (10 pF to 10JlF) and more than one decade of
timing resistance (2 kn to 30 kn for the SN54221, 2 kn to
40 kn for the SN74221, 2 kn to 70 kn for the SN54LS221,
and 2 kn to 100 kn for the SN74LS221). Throughout these
ranges, pulse width is defined by the relationship:
tw(out) = CextRext In2 ~ 0.7 CextRext. In circuits where
pulse cutoff is not critical, timing capacitance up to 1000 JlF
and timing resistance as low as 1.4 kn may be used. Also, the
range of jitter-free output pu Ise widths is extended if V CC is

(EACH MONOSTABLE)
OUTPUTS

INPUTS

0:

CLEAR

A

B

Q

L

X

X

L

H

X

H

X

L

H

X

X

L

L

H

H
H

L

t

J'L

-U-

~

H
H

JlJl-

-U-U-

t

L

Also see description and switching
characteristics
See explanation of fUnction tables on page 3-8.

1076

6-68

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
description (continued)
held to 5 volts and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum
recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device is typically less than ±0.5% for given external timing
components. An example of this distribution for the '221 is shown in Figure 2. Variations in output pulse width versus
supply voltage and temperature for the '221 are shown in Figure 3-and 4, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that
the '221 or 'LS221 can be substituted for those products in systems not using the retrigger by merely changing the
value of Rext and/or Cext.
VCC

To Cext

To Rext/Cext

Terminal

Terminal

TIMING COMPONENT CONNECTIONS

schematics of inputs and outputs
'221
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

-------vcc

VCC------~-----

INPUT

OUTPUT

Input A:

Req

Input B, Clear:

Req

= 4 kn
= 2 kn

NOM
NOM

'LS221
EQUIVALENT OF
EACH INPUT

TYPICAL OFALLOUTPUTS

v CC ------111------

I NPUT .....-i4H~-.-

Input A: Req
Input B: Req

Clear: Req

= 25 kn NOM
= 15.4 kn NOM
= 12.5 kn NOM

877

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-69

TYPES SN54221, SN74221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMm-TRIGGER INPUTS
recommended operating conditions
MIN
Supply voltage, VCC

SN54221
NOM MAX

4.5

5

5.5
-800

High-level output current, 10H
Low-level output current, 10L

MIN
4.75

SN74221
UNIT
NOM MAX
5

16
Schmitt input, B
Logic input, A

Rate of rise or fall of input pulse, dv/dt
Input pulse width

A or B, tw(in)

1
1
50

Clear, tw(clearl

20

20
15

15

ns

30

1.4

40

0

1000

0

1000
67

R ext = 2 kn

67
90

Rext = MAX R ext

125

-55

Operating free-air temperature, T A

VIs
V//ls

1.4

External timing capacitance, Cext
Output duty cycle

V
/lA
rnA

16

1
1
50

Clear-inactive-state setup time, tsu
External timing resistance, R ext

5.25
-800

90
70

0

ns
kn
/IF
%

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VT+
VTVT+
VT_
VIK

PARAMETER
Positive-going threshold voltage at A input
Negative-going threshold voltage at A input

TEST CONDITIONSt
VCC = MIN
VCC = MIN
VCC = MIN
VCC= MIN
VCC = MIN,
VCC= MIN,

Positive-going threshold voltage at B input
Negative-going threshold voltage at B input
Input clamp voltage

0.8
0.8

High-level output voltage
Low-level output voltage
Input current at maximum input voltage

VCC= MIN, 10L = 16 rnA
VCC= MAX, VI = 5.5V

IIH

High-level input current

VCC = MAX, VI = 2.4 V

IlL

Low-level input current

VCC = MAX, VI = 0.4 V

Short-circuit output current§

VCC = MAX

ICC

Supply current

VCC= MAX

TYP+ MAX UNIT
1.4
1.4
1.55
1.35

11=-12mA

VOH
VOL
II

lOS

MIN

10H = -800/lA

2.4

3.4
0.2

Input A

-1.5

V
V

0.4
1
40

Input B, Clear
Input A
Input B,Clear
SN54221
SN74221
ouiescent

2

V
V
V

2

80
-1.6
-3.2
-20

-55

-18
26

-55
50

46

80

Triggered

V
V
rnA
/lA
rnA
rnA
rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25°C_
§ Not more than one output should be shorted at a time_

switching characteristics, Vee
PARAMETER 11

= 5 V, TA = 25°e

FROM
(INPUT)

TO
(OUTPUT)

A

tpHL

A
B
Clear

tPLH

Clear

a
a
a
a
a
a

tw(out)

Aor B

ooro

tPLH
tpHL

B

MIN

TEST CONDITIONS

Cext = 80 pF, Rext
Rext
Cext = 0,
Cext = 100 pF,R ext
Cext = 1/lF, Rext

= 2 kn
= 2 kn
= 10 kn
= 10 kn

MAX UNIT

45

70

35

55

50
40

Cext = 80 pF, Rext = 2 kn
CL=15pF,
RL=400n,
See Figure 1
and Note 2

TYP

80
65
27
40

70
20

110
.30

150
50

650

700

750

6.5

7

7.5

ns
ns
ns
ns
ns
ms

~ tp LH

== Propagation delay time, low-to-high-Ievel output
tpHL == Propagation delay time, high-to-Iow-Ievel output
tw(out) == Output pulse width
NOTE 2: Load circuit is shown on page 3-10.
1076

6-70

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMm-TRIGGER INPUTS
recommended operating conditions
SN74LS221

SN54LS221
NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-400

/loA

Supply voltage, Vee

-400

High-level output current, 10H
Low-level output current, 10L

4
Schmitt, B

Rate of rise or fall of input pulse, dvldt
Input pulse width

1

8

Logic input, A

1

1

40

40

Clear, tw(clear)

40

40

External timing capacitance, eext

ns
ns

15

15

External timing resistance, R ext

1.4

70

1.4

100

kn

0

1000

0

1000

/-IF

50

RT = 2 kn

50

90

RT = MAX R ext

Operating free-air temperature, T A

mA

VIs
VI/-Is

1

A or B, tw(jn)

elear-inactive-state setup time, tsu

Output duty cycle

UNIT

MIN

125

-55

90
0

70

%
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

Positive-going threshold
VT+

Negative-going threshold
VTVIK

0.7

0.7

Vee = MIN

voltage at B input
Input clamp voltage

Vee = MIN,

11= -18 mA

VOH High-level output voltage

Vee= MIN,

10H = -400 /-I A

VOL Low-level output voltage

Vee= MIN

Input current at
II
IIH
IlL

High-level input current
Low-level input current

Input B

2.5

ICC

Short-circuit output current§
Supply current

MAX

1.0

2

1.0
1.0

2
0.8

L10L = 4 mA

3.4
0.25

2.7
0.4

Vee= MAX

ITriggered

V
V

0.4
0.5

mA
/-I A

20

20

-0.4

-0.4

-0.8

-0.8
-0.8

mA

-100

mA

4.7

11

4.7

11

19

27

19

27

II

V

0.1

-100 -20

-20
I Quiescent

V

0.1

-0.8
Vee= MAX

V

V

3.4
0.35

Vee= MAX, VI = 0.4 V

2

0.9

0.25

UNIT

V

-1.5

IIOL = 8 mA

Clear

lOS

0.8

TYP:j:

-1.5

Vee = MAX, VI = 2.7 V

~

MIN

2

0.9

Vee = MAX, VI = 7 V

maximum input voltage

SN74LS221

MAX

1.0
1.0

Vee= MIN

voltage at B input

TYP:j:
1.0

Vee= MIN

voltage at A input
Positive=going threshold

VT+

MIN

Vee = MIN

voltage at A input
Negative-going threshold

VT-

·SN54LS221

TEST CONDITIONSt

PARAMETER

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, TA = 25°e
§Not more than one output should be shorted at a .time and duration of the short-circuit should not exceed one second.

877

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

6-71

TYPES SN54LS221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMm-TRIGGER INPUTS

switching characteristics, Vee
PARAMETER~

tpLH
tpHL

= 5 V, TA = 25° e

FROM

TO

(INPUT)

(OUTPUT)

A

a

45

70

B

a

35

55

A

a

B

a

tpHL

Clear

a

tPLH

Clear

a

tw(out)

AorB

TEST CONDITIONS

Cext = 80 pF, R ext

MIN

= 2 kn

= 15 pF,
RL = 2 kn,·

CL

See Figure 1
and Note 3

aorO

= 2 kn
= 2 kn
Cext = 100 pF ,R ext = 10 kn
Cext = 1 IJF, Rext = 10 kn

Cext = 80 pF, Rext
Cext = 0,
Rext

70

TVP

MAX UNIT
ns

50

80

40

65

35

55

ns

44

65

ns

120

150

20

47

70

600

670

750

6

6.9

7.5

ns

ns
ms

~ tpLH '" Propagation delay time, low-to-high-Ievel output
tpH L == Propagation delay time, high-to-Iow-Ievel output
tw(out) '" Output pulse width
NOTE 3: Load circuit Is shown on page 3-11.

II

877

6·72

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION
! 4 - tw ( i n ) - - j

BINPUT~

\------ ---------3V

ov

I .
r---;;'60 n s - . . j
----~----------~,

I'-------------

V---- _________

l

CLEAR

~tPHL

r---rtPLH

_,JI

~::

Q OUTPU_T_--+-:

~tPHL

I+---+I-tPLH

,,.----------------------------- ~::

'\

QOUTPUT
A input is low.

3V
OV

TRIGGER FROM B, THEN CLEAR-CONDITION 1

\\..-----------_: ~

BINPUTJ,

1+---;;'60 ns ~

--------~'___L-----------:~

CLEAR

\'--------------------------------~::

---

QOUTPUT

/

A input is low

TRIGGER FROM B, THEN CLEAR-CONDITION 2

n

BINPUT

I---

,;;'50ns

---.!

r\-----:~
' I-

~ ~;;'O

f

CLEAR~•

,

-, tsetup

3V

_ _ _ _ _ _ _ _ _ _ _ _ _ OV

TRIGGERED
----,\
-NOT- TRIGGERED
- - - ----------------------

QOUTPUT

A input is low

CLEAR OVERRIDING B, THEN TRIGGER FROM B
B INPUT

- - - - - -- OV
3V
!\'--_____________

f.,------..,.~

_ _ _ _ _ _ _ _-.JI

,

I.--- ;;'50 ns~
CLEAR ,

j-- ;;.50 ns---.!
I

I __________

3V
0V

_ _ _ _ _-----1/
QOUTPUT

A input is low
TRIGGERING FROM POSITIVE TRANSITION OF CLEAR
FIGURE l-SWITCHING CHARACTERISTICS

73

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

6·73

TYPES SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION

r--

twlin

AINPU~

)---!

3V

I ____________ ov

~ ;;>60 ns----,

W ______

I

CLEAR

tPLH --.I.....--

-I'

QOUTPUT

3 V

OV

~ tPHL

I+--------VOH

If: "

VOL

~tPLH

QOUTPUT

~~__________J)(r----_---_--_--_--_-~::

:

tpHl.:-""",I.t---·~1
B input is high

TRIGGER FROM A, THEN CLEAR
~

A

INPU~,-_ _ _ _...J/ __________ 0 V

QOUTPUT

I

_ _ _-oJ

_

•

_________________ 3 V

'\

14--- tw(out)-----~.I'-----

_ _ _-,.I4I.-----tw(out)~

VOH
VOL
VOH

~ VOL

QOUTPUT"\
B and clear inputs are high

TRIGGER FROM A

NOTES:

A. Input pulses are supplied by generators having the following characteristics: PRR':;; 1 MHz, Zout "" 50 11; for '221, tr':;; 7 ns,
tf .:;; 7 ns, for' LS221 , tr .:;; 15 ns, tf .:;; 6 ns.
B. All measurements are made between the 1.5 V points of the indicated transitions for the '221 or between the 1.3 V points for the
'LS221.

FIGURE 1-SWITCHING CHARACTERISTICS (CONTINUED)

37

6·74

TEXAS INSTRUMENTS.
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54221, SN74221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMm-TRIGGER INPUTS
TYPICAL CHARACTERISTICS ('221 ONL y)t
DISTRIBUTION OF UNITS
for
OUTPUT PU LSE WI DTH

Cl.)

u

VARIATION IN OUTPUT PULSE WIDTH
vs
SUPPLY VOL TAG.E
1%

Vcc = 5 V
TA = 25°C

.----Jr----.----.----,
Cext = 60 pF

r- Rext = 10 k S l - - + - - - - t - - - - - - i

c

TA = 25°C
0.5% I-----+-----+-----!~---~

t

:J

u
u

o
0%
c
o

'';::;

t

-

_

I- MEDIAN_ -

./

'- 1

-0.5%

I 11
I

___

tw(out) "'" 420 ns

-0.5%

I-V-:7'~--+-----t----+-----\

:J

o

J

+0.5'1

MEDIAN

I-

-

/

/

.~

r-- MEDIAN

f-----+---~/

1--___~7~~---ratVCC=5V



::J

1 J.LS

t--~I

100 ns

-/1

0

-0.5%

J

:J

0

~"'\II-lC~ I II

filii
~
",0.\11r----- Ce')(.'I. ........r
100J.Ls r-~ I I Ll
1 ms

==-- '"
-c')(.'I.

\

I

J JI

~,.

-- ~v

00?l-

111_\O?l- _f--"

Vee = 5 V _Ce')(.'1.

J

 1000 pF,
the output pulse width (tw) is defined as:
tw = K • RT • Cext

0.7)

(

1 +RT

To Cext
terminal

where

To Rext/Cext
terminal

TIMING COMPONENT CONNECTIONS
FIGURE 3

K is 0.32 for '122, 0.28 for '123,
0.37 for 'L122, 0.33 for 'L123

'122, '123
TYPICAL OUTPUT PULSE WIDTH
vs
EXTERNAL TIMING CAPACITANCE

RT is in kS1 (internal or external timing resistance.
Cext is in pF

10000
7000

tw is in nanoseconds

Vee = 5 V
TA 25°e
'122
- - - '123

4000

~

2000

To prevent reverse voltage across Cext, it is recommended that the . method shown in Figure 2 be
employed when using electrolytic capacitors and in
applications utilizing the clear function. In all applications using the diode, the pulse width is:

~

;;:

~

~

';'

tw = KD • RT • Cext 1 + 0.7)
RT
(

J

fI'

~ ~~

1000
700
400

~

200

- ....

100
70

""'l...,..o""

..6
(fI"

/'"

K:~:~~~~~
RT; 20 kH
Rt;1O kH

~Tly[llTI

40

KD is 0.28 for '122, 0.25 for '123,
0.33 for 'L 122,0.29 for 'L 123

11

20

Ull

10

t

10

20

40

100

200

400

tooo

Cext-External Timing Capacltance-pF

FIGURE 4
'L122
TYPICAL OUTPUT PULSE WIDTH
vs
EXTERNAL TIMING CAPACITANCE

R ext .;; 0.6 Rextmax.
(See recommended operating
conditions for Rextmax.l

10 000
7000

vcc TA

5V
25°C

4000
c:

Any silicon switching diode
such as 1N916, 1 N3064, etc.

To Cext
terminal

~

~
~

'""
"
0"
I

Q.

ToRextlCext
terminal

.}

TIMING COMPONENT CONNECTIONS WHEN
Cext > 1000 pF f'ND CLEAR IS USED

r~

V .....

2000

~

1000
700
400
200

I.1--1.-

100
70

~

....

~~

= 5() knt
= 3() knt
~ Rext = 2() kn
Rext = 1() kn
Rext = 5 kn
Rext
~ Rext

40

FIGURE 2

Io'y

20

IIIII

10
1

10

20

40

100 200 400

1000

Cext-External Timing Capacitance-pF

Applications requiring more precise pulse widths (up
to 28 seconds) and not requiring the clear feature can
best be satisfied with the '121 or'L 121.

FIGURE 5
tThese values of resistance exceed the maxim-urn recommended for use
over the full temperature range of the SN54' and SN54L' circuits.

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

6·81

TYPES SN54LS122, SN74LS122, SN54LS123, SN74LS123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
TYPICAL APPLICATION DATA FOR 'LS122, 'LS123
The basic output pulse width is essentially determined by the values of external capacitance and
timing resistance. For pulse widths when Cext <
1000 pF, see Figure 7.
When Cext
defined as:

>

1000 pF, the output pulse width is

tw = 0.45 • RT • Cext
where
RT is in kil (internal or external timing resistance.)
Cext is in pF

To Cext
terminal

1w is in nanoseconds

To Rext/Cext
terminal

TIMING COMPONENT CONNECTIONS

For best results, system ground should be applied to
the Cext terminal. The switching diode is not needed
for electrolytic capacitance applications.

FIGURE 6

'LS122, 'LS123
TYPICAL OUTPUT PULSE WIDTH
vs
EXTERNAL TIMING CAPACITANCE

•

100000
RT
RT
I

10000

-

;S
'C

~

5l
:;
c...

...

= .....
1000

'"""

~

'L f' /~

VI

r:::

260 kilt
160 kil

L
i.oo"

I-- "'~

""
V

L

~

1/ . . . .

::J

B::J
0
I

}

r-100

i"""'~

./'

~

r- ~K

= 80 kil
= 40 kil
RT = 20"kn'
t::RT = 10 kil
RT = 5 kil
RT

~RT

I

10

100

1111II
1000

Cext-External Timing Capacitance-pF
tThis value of resistance exceeds the maximum recommended for use over
the full temperature range of the SN54LS circuits.

FIGURE 7

10

6-82

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN 54LS240,SN 54LS241, SN54LS244,S N54S 240,S N54S241,
SN74LS240,SN74LS241,SN74LS244,SN74S240,SN74S241
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54LS'
SN74LS'
SN54S'
SN74S'

Typical

Typical

10L
(Sink
Current)
12mA
24 mA
48mA
64 mA

10H
(Source
Current)
-12mA
-15mA
-12mA
-15mA

•

3-State Outputs Drive Bus Lines
or Buffer Memory Address Registers

o

P-N-P Inputs Reduce D-C Loading

•

Hysteresis at Inputs Improves
Noise Margins

Typical Propagation
Delay Times
Inverting
10.5 ns
10.5 ns
4.5 ns
4.5 ns

Noninverting
12 ns
12 ns
6 ns
6 ns

Typical
Enable!
Disable
Times
18 ns
18 ns
9 ns
9 ns

Typical Power
Dissipation
(Enabled)
Inverting
130mW
130mW
450 mW
450 mW

Noninverting
135mW
135mW
538mW
538 mW

SN54LS240, SN54S240 ... J
SN74LS240, SN74S240 ... J OR N
(TOP VIEW)

description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of three·state memory address drivers, clock
drivers, and bus·oriented receivers and transmitters.
The designer has a choice of selected combinations of
inverting and noninverting outputs, symmetrical G
(active-low output control) inputs, and complementary G and G inputs. These devices feature high
fan-out, improved fan-in, and 400-mV noise·margin.
The SN74LS' and SN74S' can be used to drive
terminated lines down to 133 ohms.

SN54LS241, SN54S241 ••• J
SN74LS241, SN74S241 ... J OR N
(TOP VIEW)

schematics of inputs and outputs
'LS240, 'LS241, 'LS244
EQUIVALENT OF
EACH INPUT

VCC:Jl---

INPUT

TYPICAL OF ALL
OUTPUTS

t:j:t

SN54LS244 .•• J
SN74LS244 ... J OR N
(TOP VIEW)
'S240'S241
EQUIVALENT OF
EACH INPUT

VCCh--INPUTf4}---

'LS240, 'LS241, 'LS244;
R = 50 n NOM
'S240, 'S241:
R =25 n NOM

2Y4

1A2

2Y3

77

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

6-83

TYPES SN54LS240,SN54LS241,SN54LS244,
SN74LS240,SN74LS241,SN74LS244
BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

recommended operating conditions
SN74LS'

SN54LS'

PARAMETER

MIN
4.5

Supply voltage, Vee (see Note 1)
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, T A

NOM
5

55

MAX
5.5
12
12
125

MIN
4.75

NOM
5

0

MAX
5.25
15
24
70

UNIT
V
mA
mA
e

NOTE 1: . Voltage values are with respect to network ground terminal.

electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
VIL
VIK

VOH

VOL

Vee = MIN,
Vee = MIN
Vee = MIN,
VIL = VIL max,
Vee = MIN,
VIL = 0.5 V,
Vee - MIN,
VIH = 2 V,
VIL = VILmax

High-level output voltage

Low-level output voltage

IIH

Off-state output current,
high-level voltage applied
Off-state output current,
low-level voltage applied
Input current at maximum
input voltage
High-level input current, any input

IlL

Low-level input current

10ZH
10ZL

•

TEST eONDITloNst

High-level input voltage
Low-level input voltage
Input clamp voltage
Hysteresis \VT + - VT-)

II

Short-circuit output current·
Outputs high

MIN
2

SN54LS'
TYP+ MAX

= 2 V,
= -3 mA
- 2 V,
= MAX

SN74LS'
TYPt MAX

0.7
1.5

11- -18 mA
VIH
10H
VIH
10H

MIN
2

0.8
-1.5

0.2

0.4

0.2

0.4

2.4

3.4

2.4

3.4

switching characteristics, Vee

2

IOL=12mA

0.4

0.4

10L = 24 mA

0.5

tpHL
tpZL
tPZH
tPLZ
tpHZ

V

Vee = MAX,
VIH = 2 V,
VIL = VILmax

Vo = 2.7 V

20

20

Vo = 0.4 V

-20

-20

Vee = MAX,

VI =7V

0.1

0.1

mA

Vee = MAX,

VI - 2.7 V

20

20

'{ee = MAX,
Vee - MAX

V.ll = 0.4 V

-0.2

-0.2

J.lA
mA

J.lA

Vee = MAX

17
26
27
29
32

-225
27
44
46
50

mA
mA

54

= 5 V, TA = 25°e

PARAMETER
tpLH

V
V
V
V

V
2

-40
-225 -40
All
17
27
'LS240
26
44
Outputs low
Supply current
'LS241, 'LS244
27
46
Ice
Outputs open
All outputs
'LS240
50
29
disabled
'LS241, 'LS244
32
54
.
.
tFor conditions shown as MI N or MAX, usa the appropriate value specified under recommended operating conditions .
tAli typical values are at VCC = 5 V, T A = 25°C.
+Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
lOS

UNIT

TEST CONDITIONS

Propagation delay time,
low-to-high-Ieveloutput
Propagation delay time,
high-to-Iow-Ievel output
Output enable time to low level
Output enable time to high level
Output disable time from low level
Output disable time from high level

eL=45pF,
See Note 2

eL - 5pF,
See Note 2

MIN

RL=667n,

RL = 667 n,

'LS240
TYP MAX
9

14

12

18

20
15
15
10

30
23
25
18

'LS241 'LS244
MIN
TYP MAX
12

UNIT

18

ns

12

18

ns

20
15
15
10

30
23
25
18

ns
ns
ns
ns

NOTE 2: Load circuit and voltage waveforms are shown on page 3-11.

8'

6·84

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES S154S240, S154S241, S114S240, SI14S241
BUFFERS/LINE DRIVERS/LINE RECEIVERS WITH 3-STATE OUTPUTS
REVISED AUGUST 1979

recommended operating conditions
SN54S'
NOM MAX
5
5.5
-12
48
40
125
55

PARAMETER

MIN
4.5

Supply voltage, Vee (see Note 1)
High·level output current, 10H
Low·level output current, 10L
External resistance between any input or Vee and ground
Operating free·air temperature, T A (see Note 3)

SN74S'
NOM MAX
5
5.25
-15

MIN
4.75

64
40
70

0

UNIT
V
mA
mA
kn
e

NOTES: 1. Voltage values are with respect to network ground termInal.
3. An S~54S241J operating at free-air Jemperature above 116°e requires a heat sink that provides a thermal resistance from case to
free·a .. , ROCA, of not more than 40 C/W.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONst

PARAMETER
VIH

High·level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

Vee = MIN,

Hysteresis (VT+ - VT-)

Vee = MIN

VOL

High·level output voltage

10H = -1 mA
VIH=2V,

SN74S'

VIL=0.8V,

10H = -3 mA

SN54S' and

Vee'" MIN,

VIH.= 2 V,

SN74S'

VIL=0.5V,

10H = MAX

Vee = MIN,

VIH=2V,

VIL=0.8V,

10L = MAX

Vee = MAX,

Low·level output voltage

high·level voltage applied

MAX

UNIT
V

0.8

0.8

V

-1.2

-1.2

V

0.4

0.2

2.7
2.4

TYP;

0.4

V

3.4

V

2.7
3.4

2.4
2

2
0.55

0.55

VO=2.4V

50

50

VIL=0.8V

Vo = 0.5 V

-50

-50

Vee = MAX,

VI=5.5V

1

1

Vee = MAX,

VI=2.7V

Vee = MAX,

VI=0.5V

V

I

low·level voltage applied
input voltage
High·level input current, any input

IlL

Low·level input current

lOS

Short-<:ircuit output current.

Anv A
Any G

Vee

Il A

= MAX

-50
SN54S'

Outputs high
Supply current

MIN

VIH = 2 V,

IIH

lee

VIH = 2 V,

VIL = 0.8 V,

Input current at maximum
II

Vee = MIN,

0.2

Vee = MIN,

Off·state output current,
10ZL

MAX

2

11= -18 mA

SN54S' and

Off·state output current,
10ZH

TYP:t:

2

SN74S'

VOH

'S241

'S240
MIN

50

50

-400

-400

IlA

-2

-2

mA

-225

mA

-225
80

123

-50
95

147

SN74S'

80

135

95

160

Vee = MAX,

SN54S'

100

145

120

170

Outputs open

SN74S'

100

150

120

180

Outputs

SN54S'

100

145

120

170

disabled

SN74S'

100

150

120

180

'S241
TYP

MAX

Outputs low

II

mA
IlA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC = 5 V, T A - 25°C.
·Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER
tPLH
tpHL
tpZL
tpZH
tpLZ
tpHZ

TEST CONDITIONS

Propagation delay time,
low·to·high·level output
Propagation delay time,
high·to·low·level output
Output enable time to low level
Uutput enable time to high level
Output disable time from low level
Output disable tIme from high level

eL=50pF,
See Note 4

eL = 5pF,
See Note 4

MIN

RL = 90n,

RL = 90 n,

'S240
TYP MAX
4.5

7

4.5

7

10
6.5
10
6

15
10
15
9

MIN

6

UNIT

9

ns

6

9

ns

10
8
10
6

15
12
15
9

ns
ns
ns
ns

NOTE 4: Load CirCUIt and voltage waveforms are shown on page 3-10.
379

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

6-85

TYPES SN54LS240.SN54LS241,
SN54LS244,SN54S240,SN54S241.SN74LS240.
SN74LS241,SN74LS244.SN74S240.SN74S241
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
'j

DRIVER
1/8 'LS241/'S241,

LONG LINE
REPEATER

REPEATER

IIRECEIVER
1/8 'LS241, 'S241

REPEATER

1~~S~~~Sr1"S~t
~

~OUTPUT

IT,

+

•
+
..:=t- -~.::..:=t'¥J-- '"':1.::..:=t.-J - -\'-j.::..:=':;::""--'--:).::..:=touTPuT -INPUT - mrTPUT - "iNPUT- OihPuT - iNPUT - - OUTPuT - iNpUT OUTPUT'
~

~::~:-~--'~-A~--~M~-A----~--~-A-- --~=-::-A~=~;:=~-A~1.2V·W-_"""-j.::

0.3 V- INPUT _.

""-L-

'LS241, '5241 USED AS REPEATER/LEVEL RESTORER

OUTPUT {
CONTROL

_ _ _ _ _ .J
V
SYSTEM ANDIOR MEMORY·ADDRESS BUS

'LS241,'S240 USED AS SYSTEM AND/OR MEMORY BUS DRIVER-4.BIT
ORGANIZATION CAN BE APPLIED TO HANDLE BINARY OR BCD

•

1/4 'LS241 'S241
PARTY·LlNE
I
MUL TlPLE·INPUT/OUTPUT BUS 1 6;1~:~' 'S241
DRIVER

r----...,

r----..,'

l.cr
I

I

INPUT B

I
I

~
BUS
CONTROL
-H--HH
L
L
H

TO
DATA
BUS

L
L
H
L

RECEIVERS
INPUT OUTPUT
-B- - A B
A
A
NONE

B
B
A
NONE

BUS
CONTROL
-L--LH
H
L
L

L
H
H
H

PARTY·LINE BUS SYSTEM
WITH MULTIPLE INPUTS, OUTPUTS, AND RECEIVERS

~

L __ --1

External resistance between any Input of the 'S240 or 'S241
and ground or Vec must not exceed 40 kil.
}

INPUT·PORT
CONTROL

INDEPENDENT 4·BIT BUS DRIVERS/RECEIVERS
IN A SINGLE PACKAGE

6-86

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54LS242, SN54LS243, SN74LS242, SN74LS243
QUADRUPLE BUS TRANSCEIVERS
•

Two-Way Asynchronous Communication
Between Data Buses

•

P-N-P Inputs Reduce D-C Loading

•

Hysteresis (Typically 400 mV) at Inputs
Improves Noise Margin

SN54LS242 ••• J OR W
SN74LS242 ••• J OR N
(TOP VIEW)
Vcc

GBA

NC

1B

2B

3B

4B

GAB

NC

1A

2A

3A

4A

GND

description
These four-data·line transceivers are designed for
asynchromous two·way communications between
data buses. The SN74LS' can be used to drive term·
inated lines down to 133 ohms.
FUNCTION TABLE (EACH TRANSCEIVER)
'LS242

CONTROL
INPUTS

'LS243

DATA PORT

DATA PORT

STATUS

STATUS

GAB

GBA

A

B

A

B

H

H

0

I

0

I

L

H

*

*

*

*

H

L

ISOLATED

L

L

(5

I

SN54LS243 ••• J OR W
SN74LS243 ••• J OR N
(TOP VIEW)

ISOLATED

0

I

VCC

GBA

NC

1B

2B

3B

4B

GAB

NC

1A

2A

3A

4A

GND

·Possibly destructive oscillation may occur if the
transceivers are enabled in both directions at once.
= Input, 0 = Output, 0 = Inverting Output.

I

schematics of inputs and outputs
EQUIVALENT
OF EACH iNPUT

vee~
__ 17 kn
INPUT

TYPICAL OF
ALL OUTPUTS

~
~~nNOM

Vee

OUTPUT

GND

NC-No internal connection

recommended operating conditions
SN54LS'
MIN
Supply voltage, Vee (see Note 1)

4.5

NOM
5

SN74LS'
MIN

NOM

MAX

5.5

4.75

5

5.25

V

-15

mA

24

mA

70

°c

-12

Hi!t1·level output current, IOH

12

Low-level output current, IOL
-55

Operating free-air temperature, T A

UNIT

MAX

125

0

NOTE1: Voltage values are with respect to network ground terminal.

176

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6·87

TYPES SN54LS242, SN54LS243, SN74LS242, SN74LS243
QUADRUPLE BUS TRANSCEIVERS
REVISED DECEMBER 1980

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

Vee = MIN,

Hysteresis (VT+ - VT-)

Vee = MIN

VOL

Vee = MIN,

Low-level output voltage

II

high-level voltage applied

IIH

Input current at maximum

AorB
GAB orGBA

High-level input current. any input
A inputs
input current

B inputs

•

-1.5

V

0.4

0.2

0.4

3.1

2.4

3.1

V

V
2

2
0.25

0.4

0.25

0.4

0.35

0.5

V

VIL = VIL max
Vee = MAX,

VO=2.7V

40

40

IJA

VO= 0.4 V

-200

-200

IJA

VI = 5.5 V

0.1

0.1

VI = 7 V

0.1

0.1

Vee = MAX,

VI=2.7V

20

20

Vee - MAX,

VI - 0.4 V,

-0.2

-0,2

-0.2

-0,2

Vee = MAX,

VI = 0.4 V,

Vee = MAX,

Outputs low
All outputs

Vee = MAX,
Outputs open,
See Note 2

-0.2

VI=O.4V
-40

Vee = MAX

disabled

mA
J.lA

mA

GAB and GBA at 4.5 V

Short-circuit output current·

Supply current

V

-1.5

10L = 24 mA

Vee = MAX,

Outputs high
ICC

V
0.8

2.4

GAB and GBA at 0 V

GAB orGBA
lOS

10L = 12 mA

VIL = VIL max

Low-level
IlL

10H = MAX

Vee = MIN,

UNIT

0.7
0.2

VIH = 2 V,

VIL = 0.5 V,

MAX

VIH = 2 V,

low-level voltage applied
input voltage

VIH = 2 V,

TYP:j:

MIN

VIH = 2 V,

Off-state output current,
10ZL

SN74LS'
MAX

2

11=-18mA

VIL = VIL max, 10H = -3mA

High-level output voltage

Off-state output current,
10ZH

TYP+

2

Vee = MIN,
VOH

SN54LS'
MIN

'LS242, 'LS243

-225

-0.2
-40

-225

22

38

22

38

'LS242, 'LS243

29

50

'LS242

29

50

29
29

50

'LS243

32

54

32

54

50

mA

mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V, TA = 25 c C.

·Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: I CC is measured with transceivers enabled in one direction only, or with all transceivers disabled.

switching characteristics, Vee

=5 V, TA = 25°e

PARAMETER

'LS242

TEST CONDITIONS

MIN

Propagation delay time,
tPLH

low-to-high-Ieveloutput
Propagation delay time,

eL=45pF,

high-to-Iow-Ievel output

See Note 3

RL = 667

n,

'LS243

TYP

MAX

9

14

MIN

UNIT

TYP

MAX

12

18

ns

12

18

12

18

ns

tPZL

Output enable time to low level

20

30

20

30

ns

tPZH

Output enable time to high level

15

23

15

23

ns

tPLZ

Output disable time from low level

eL=5pF,

15

25

15

25

ns

tpHZ

Output disable time from high level

See Note 3

10

18

10

18

ns

tPHL

RL = 667

n,

NOTE 3: Load circuit and waveforms are shown on page 3-11.

12

6-88

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54265, SN74265
QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS
•

FOR SYMMETRICAL GENERATION OF COMPLEMENTARY TTL SIGNALS
Switching Time Skew of the Complementary
SN54265 ••• J OR W PACKAGE
Outputs Is Typically 0.5 ns ... Guaranteed
SN74265 ••• J OR N PACKAGE
to be No More than 3 ns at Rated Loading
(TOP VIEW)

•

Full Fan·Out to 20 High-Level and 10
Low-Level 54/74 Loads

•

Active Pull-Down Provides Square
Transfer Characteristic

description
The SN54265 and SN74265 circuits feature complementary outputs from each logic element, which have
virtually symmetrical switching time delays from the
triggering input. They are designed 'specifically for use
in applications such as:
•

Symmetrical clock/clock generators

•

Complementary input circuit for decoders and
code converters

•

Switch debouncing

•

Differential line driver

positive logic:
ELEMENTS 1 AND 4 ELEMENTS 2 AND 3
Y =AB
Y=A
W=AB
W=A

Examples of these four functions are illustrated in the
typical application data.
The SN54265 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74265 is characterized for operation from O°C
to 70°C.

schematics of inputs and outputs
EaUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

6 kO

OUTPUT

174

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

6-89

TYPES SN54265, SN74265
QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS

recommended operating conditions
SN54265
MIN
Supply voltage, Vee

4.5

NOM

SN74265
MAX

MIN

NOM

5.5

4.75

5

5

High.level output current, 10H

-800

Low-level output current, 10L

16

Operating free-air temperature, T A

-55

125

0

MAX

UNIT

5.25

V

-800

J1.A

16

rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

Vee= MIN,

II = -12 rnA

VOH

High-level output voltage

Vee= MIN,

10H = -800 1lA

VOL

Low-level output voltage

Vee= MIN,

10L = 16 rnA

MIN

TVPt

MAX

2

2.4

UNIT
V

0.8

V

-1.5

V

0.4

V

3:4
0.2

V

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5V

1

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

40

J1.A

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-1.6

rnA

lOS

Short-circuit output current§

Vee = MAX,

I SN74265

lee

Supply current

Vee = MAX,

See Note 3

I SN54265

-20

-57

-18

-57
25

34

rnA

rnA
rnA,

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with all outputs open and all inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e
FROM

TO

(INPUT)

(OUTPUT)

tPLH(W)

Aor B

W

tpHLiV)

(as applicable)

V

tpHL(W)

AorB

W

tPLH(V)

(as applicable)

V

tPLH(W)-tpHLiV)

A or B

Wwith

tpH LlW)-tPLH (V)

(as applicable)

respect to V

PARAMETER~

TEST CONDITIONS

RL = 400.n,
eL=15pF,
See Note 4

MIN

TVP

MAX

11.6

18

11.3

18

9.8

18

10.2

18

+0.3

±3

-0.4

±3

UNIT
ns
ns
ns

tpLH == Propagation delay time, low-to-high-Ievel output.
tpH L '" Propagation delay time, high-to-Iow-Ievel output.
tPXX(W)-tpXX(Y) '" Difference in indicated propagation delay times at the Wand Y outputs, respectively.
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

11

6-90

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54265, SN74265
QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS
TYPICAL CHARACTERISTICSt

PROPAGATION DELAY TIME DIFFERENCE
vs
SUPPLY VOLTAGE

PROPAGATION DELAY TIME DIFFERENCE
vs
FREE-AIR TEMPERATURE
2

5
II>

c
I
Q)

u

c

~

~

VCC = 5 V
4 - RL = 400 n
_ CL = 15 pF

>co

Qj

0

c
0

'oJ

Cll

,
..............

E
0

y.~'1

'-.....

;"'/

-1

,/

\,plL
/~

Cll

~

is

~

0.5

--

tPLH (W)-tPH L(Y)

(l)

E

i=

~I.(W~~

~
c

1.J..t(Y~

-2

0

>co

.~

co
co

-

~

--

-0.5 -tPHL(W) tPLH(Y)
-1

C>

c. -3

e

I

c

C>

a...

1.5

u

2

Q)

TA = 25°C
RL = 400 n
CL = 15 pF

II>

3

0

i=

T

co

C.

~ -1.5

-4

-2

-5
-75 -50 -25

0

25

50

75

100

4.5

125

4.75

T A-Free-Air Temperature-OC

5.25

5

5.5

VCC-Supply Voltage-V
FIGURE 2

FIGURE 1

II

PROPAGATION DELAY TIME DIFFERENCE vs LOAD CAPACITANCE
2

2

C

B
c

VCC = 5 V
1.5 TA = 25°C

~

~
~

E

~

~

(l)

0~

c

.............

~is

~n

--

~

r-!!.L.;..!...OO,Q
-

---

0

E

1:5 -0.5

-

t---

-----

f\L~400~

0.5

E

-1

V

V

....

a...

1S

:J

:5-1.5

I

e-

e-

-1

RL

V--

-

4kn

I

-1.5

-2

-2
15

VCC = 5 V
1.5 TA = 25°C

u

(l)

a...

~

T

0.5

~-0.5

1

II>

20

25

30

35

40

45

50

15

20

25

30

35

40

CL -Load Capacitance-pF

CL -Load Capacitance-pF

FIGURE 3

FIGURE 4

45

50

t Data for temperatures below 0° C and above 70° C and for supply voltages below 4.75 V and above 5.25 V are applicable for SN54265 only.
374

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-91

TYPES SN54265, SN74265
QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS
TYPICAL APPLICATION DATA

r----------------CLOCK
CLOCK

1/4 SN74265
CLOCK
~
CLOCK
-G-E-N-E-R-A-T-O-R-""""'tAS'------ CLOCK

;;:>----- CLOCK

FIGURE A - TYPICAL CLOCK/CLOCK GENERATOR CIRCUIT

FIGURE B - SKEWlESS CLOCK/CLOCK GENERATOR CIRCUIT

o

0
INPUT A

•

INPUT B

3

LINPUT

!--INPUT

I

INPUT A , - - - -

-- -

-

INPUT~--

---:

------H

-

L
INPUTB , - - - - - - -

---t
INPUT.{

2

INPUT~-

--:

!+- DECODER SKEW

--- - -

OUTPUT 2

U _________

--:

H

-------L

GATE

_H

2

B

-------H

H

r ~------------------L

L

-------"--'--------------------- H
OUTPUT 2
____ l

L
.-- DECODER SPIKE

----- -

INPUT{~A1

Ir---_-:------------------ L

I
~B------il

-

I--- SYMMETR ICAl DECODE

H

_A_ _ _.........

1

GATE

-- -

NO DECODE SPIKE

FIGURE C - TYPICAL DECODER/CODE CONVERTER

FIGURE D - SYMMETRICAL DECODER/CODE CONVERTER

37·

6·92

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54265, SN74265
QUADRUPLE COMPLEMENTARY-OUTPUT ELEMENTS
TYPICAL APPLICATION DATA
390 !1

1/4 SN74265

,......,,-------w
I./C>-------y

5V

~

W OUTPUT

YOUTPUT

-

~----VOH

_ _ _---I

rvu

W OUTPUT
-

---VOL

~---'VOH

\

----VOL
----VOH

----VOH
Y OUTPUT
L-----VOL
WITH FEEDBACK TO
STABILIZE INPUT

WITHOUT FEEDBACK
FIGURE E - SWITCH DEBOUNCER

•
Noise immunity typically 3 V

for either high level or low level data
FIGURE F - DIFFERENTIAL LINE DRIVER

74

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-93

SERIES 54/74. 54H/74H. 54L/74L. 54.LS/74LS. 54S/74S
TRANSISTOR-TRANSISTOR LOGIC
PARAMETER MEASUREMENT INFORMATION
Vee

TEST TABLE
OPEN-

FUNCTION

INPUT CONDITIONS

NAND

Input under test at VIL max, all others at 4.5 V

COLLECTOR
IOH
r-~O~U~T~P~U~T~S~__~4---~~(+) VOH
INPUTf
CONDITIONS
(See Test Table
and Note)

TOTEM-POLE
OUTPUTS

AND

All inputs at VIH min

NOR

All inputs at VI L max

OR

Input under test at VIH min, all others at GND

AND-ORINVERT
AND-OR

Inputs under test (a set including one input of each
AND gate) at VIL max, all others at 4.5 V
All inputs of AND gate under test
at VIH min, all others at GND

NOTE: For functions having three-state outputs, input conditions
are maintained which will cause the outputs to be enabled
(low-impedance).

TEST TABLE

Vee
FUNCTION
INPUT
CONDITIONS
(See Test Table
and Note)

t

NAND

Input under test at V I L max, all others at 4.5 V

AND

Input under test at VIH min, others at GND

NOR
OR

All inputs at VIL max

AND-OR-

All inputs of AND gate under test

INVERT

at VIH min, all others at GND

AND-OR

NOTE: For functions having three-state outputs, input conditions
are maintained which will cause the outputs to be enabled
(low-impedance ).

•

INPUT CONDITIONS
All inputs at VIH min

Inputs under test (a set including one input of each
AND gate) at VIH min, all others at 4.5 V

Vee

11

OUTPUT(S)
OPEN

REMAINING
INPUTS
(See Note B)

OUTPUT(S)
OPEN

REMAINING{
V
INPUTS

0'"
NOTES:

NOTE: Each input is tested separately.

A. Each input is tested separately.
B. When testing AND-OR-INVERT or AND-OR gates,
each AND gate is tested separately with inputs of
AND gates not under test open when testing II and
grounded when testing IIH'
FIGURE 4-11, IIH

FIGURE 3-VI

4.5V

REMAINING
INPUTS
IlL
VI_4--_____(_-_)______~

Vee

OUTPUT(S)
OPEN

NOTES: A. Each input is tested separately_
B. When testing AND-OR-INVERT or AND-OR gates, each AND gate
is tested separately with inputs of AN D gates not under test open.

FIGURE 5-IIL
12

6-94

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SERIES 54/74, 54H174H, 54L/74L, 54LS/74LS, 54S/74S
TRANSISTOR-TRANSISTOR LOGIC
PARAMETER MEASUREMENT INFORMATION

INPUT
CONDITIONS
(See Test Table
and Note)

t

TEST TABLE

VCC

(-)

llOS

FUNCTION

INPUT CONDITIONS

NAND

All inputs at GND

AND

All inputs at 4.5 V

NOR

All inputs at GND

OR

All inputs at 4.5 V

AND·OR·INVERT

All inputs at GND

AND·OR

All inputs at 4.5 V

NOTE: For

functions

having three-state

outputs, input conditions are main-

tained which will cause the outputs
to be enabled (low-impedance).
FIGURE 6-IOS

Vce
TEST TABLE
FUNCTION

INPUT
CONDITIONS
(See Test Table
and Note)

t

INPUT CONDITIONS FOR ICCH INPUT CONDITIONS FOR ICCl

NAND

All inputs at GND

All inputs at 4.5 V

AND

All inputs at 4_5 V

All inputs at GND

NOR

All inputs at GND

OUTPUT(S)
OPEN

One input at 4.5 V,

OR

all others at GND

AND·OR·INVERT

All inputs at GND
All inputs of one AND gate

AND·OR

at 4.5 V, all others at GND

One input at 4.5 V,
all others at GND
All inputs at GND
All inputs of one AND gate
at 4.5 V, all others at GN D
All inputs at GND

NOTE: ICC is measured simultaneously for all functions in a package. The average-per-gate values are calculated from
the appropriate one of the following equations:

II

total ICC, ICCH, or ICCL

ICC, leCH, or ICCL (average per gate or flip-flop)

ICC (average per gate, 50% duty cycle)

=

= --------------'-(number of gates or flip-flops in package)

ICCH + ICCL
2 (number of gates in packagel

FIGURE 7-ICC

Vec

FIGURE 9-VT _, IT _, VOH (FOR NAND SCHMITT TRIGGERS)

FIGURE 8-VT+' IT+' VOL (FOR NAND SCHMITT TRIGGERS)
1272

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6·95

SERIES 54/74, 54H/74H, 54L/74L, 54LS/74LS, 54S/74S
TRANSISTOR-TRANSISTOR LOGIC
PARAMETER MEASUREMENT INFORMATION
Vee
NOTES:
OPEN
IOL
4-(+)

02

A. Switches are In position 1 for SN54'/SN74', position
2 for SN54H'/SN74H'.
B. The IX limit for SN54' and SN74' circuits may be
verified by an alternate equ iva lent procedure. The
VXX source Is replaced by a resistor (see table below)
In parallel with a voltmeter between the X and X pins,
If the measured voltage, VXX, Is less than 0.4, the
specified limit for IX Is met.

RESISTANCE VALUE TABLE
SN5423

114 .n

SN5450, SN5453

138.n

SN7423

105.n

SN7450, SN7453

130.n

FIGURE 10-15( (FOR EXPANDABLE GATES)

Vee

Vee

IOH

~(+)

(-)~

VOL

~

II
RXX

VSE(Q)
":'

-!-

":'

~

1

FIGURE 11-VBE(Q) (FOR EXPANDABLE GATES)

"" 27 kn
(Adjust Ix)

RGURE12-VOH(FOREXPANDABLEGATEm

Vee

Vee

4.5 V

IOL

+-

Vx - .....
--(_....)

(+)

4--(-)

IX

IX

FIGURE 13-VOH (FOR EXPANDABLE GATES)

FIGURE 14-VOL (FOR EXPANDABLE GATES)
18'

6·96

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

SERIES 54/74, 54H/74H, 54L/74L, 54LS/74LS, 54S/74S
TRANSISTOR-TRANSISTOR LOGIC
PARAMETER MEASUREMENT INFORMATION

Vee

Vee
IX
+--(+)

VIH

Ix
-(+)

Vx

Vx
VIL

AX

i

':"

V5(

-=

':"

FIGURE 16-0FF-STATE CHARACTERISTICS
FOR EXPANDERS

FIGURE 15-0N-STATE CHARACTERISTICS
FOR EXPANDERS

Vee
Vee

IX
+--(+)
VIL------I

Vx

•

FIGURE 18-0FF-STATE CHARACTERISTICS
FOR EXPANDERS

FIGURE 17-0N-STATE CHARACTERISTICS
FOR EXPANDERS

Vee

" •• No'." "e' 31 {

OTHER
INPUTS

IO(oft)
-

(+)

(-) -+

(See Note 2)
(See Note 3)

Vo
To VIH or V I L {
(See Note 1)

NOTES:

OUTPUT
CONTROL
INPUTS

1. Input conditions are maintained which will ensure that the three-state output(s) is (are) disabled to the high-impedance state. See
function table or logic for the particular device.
2. When testing for current into the output with a high-level output voltage, input conditions are applied that would cause the
output to be low if it were enabled.
3. When testing for current out of the output with a low-level output voltage, input conditions are applied that would cause the
output to be high if it were enabled .

. FIGURE 19-IO(0ff) (THREE-STATE OUTPUTS)

1272

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-97

SERIES 54114
TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
HIGH-LEVEL OUTPUT VOLTAGE

OUTPUT VOLTAGE

vs

vs
4.0

3.5

HIGH-LEVEL OUTPUT CURRENT

INPUT VOLTAGE

TA~125lc

3.5

3.0 TA __ 55°C

~

~

~ 3.0

~,

>
I

~ 2.5

~

g

~ 2.0

9 1.5 r-- r-~

0.5

00

\ \
\11
TA~1251c- 1

~

~

TA - _55°C

\

0

1

1.2

1.4 1.6

"

TA - -55°C

~ 1.5
:i
~ 1.0

1\
1\ \

____ TA

i

VCC - 5 V
VI-0.4V
25°C

'"
" ' TA - 125°C

~

l

0.6 0.8

2.5

~
~

02.0

TAj 25 C

0.2 0.4

4.0

VCC - 5 V
Rl - 400 n

"''\.
'\

0.5

1.8

15

10

2

'OH-High-Level Output Current-mA

FIGURE A1

FIGURE A2

vs

VCC' 5 V
VI - 2.4 V

I

~

a

~

> 0.1

~
V/

.-!~

e::-:...-

35

~

30

"

25

~
£

A ~p.'~~

5

E

i=

~'"

00.3

02

40

TAI._55t

g 0.4

!

FREE-AIR TEMPERATURE

LOW-LEVEL OUTPUT CURRENT

s

VCC' 5 V
Rl -400 n

Cl - 150 pF

20

cl- l
c~ -

1:5

./

50 PF

I

!r:'

1
15 pF

~75

20
25
30
35
IOL -Low-Level·Output Current-mA

-50

25
50
75
-25
T A-Free-Air Temperature-OC

FIGURE A3

vs

FREE-AIR TEMPERATURE

40

VCC- 5V
Rl -400 n

35

35

30

30

25
~

Cl' 150 pF

I---10

Cl' 50 pF

rr--

I

I

:t=t=
Ci"

15

r

I--

-

--

FREE-AIR TEMPERATURE
VCC' 5 V
Rl -400n

25

V

20

:...-

15

....--'

.............
10

~

----

I---

~e-

ci-

-75 -50

-25
25
50
75
TA-Free-Air Temperature-Dc

100

125

FIGURE A5

T-

1

5
0
-75

150 pF

Cl - 50 pF

cr

o

125

PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT

vs

20

100

FIGURE A4

PROPAGATION DELAY TIME,
LOW-TO-HIGH LEVEL OUTPUT
40

30

AVERAGE PROPAGATION DELAY TIME,

vs

r

~ 25

20

V,-Input Vohage-V

LOW-LEVEL OUTPUT VOLTAGE.

0.6

:\.
~

-50 -25

0
25
50
75
TA-Free-Air Temperature-OC

~

100

125

FIGURE AS

tData for temperatures below oOe and above 70°C are applicable for Series 54 circuits only.
§ Data as shown are applicable specifically for the NAN D gates with totem-pole outputs.

1071

6-98

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SERIES 54H/74H
HIGH-SPEED TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT

PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs

vs

FREE-AIR TEMPERATURE

20

FREE-AIR TEMPERATURE

20

VCC = 5 V
18 RL = 280 n

VCC= 5 V
18 RL = 280 n
16

E-

CL=100pF

--

~

~
CL = 25 pF

-------

--

.!.:::l

i=

~

CL = 150 pF

1:

~

V ....- /
./

.g
~

0

~ 10

-1

~ ~

~

e ...J
'T...Ji:.B
J:

8

~ ...........

.. ~- r---

.

~

CL=100pF

-r-. t---

6

----

CL=150pF

I--I--I---

CL=25pF

Cl

P:- I

2

~75

14

~ S12

4

--

-

-

r---

2
-50

-25
0
25
50
75
T A-Free-Air Temperature-OC

100

275

125

-25
o 25 50 75
T A-Free-Air Temperature-O C

-50

FIGURE B1

100

125

FIGURE B2

I

AVERAGE PROPAGATION DELAY TIME

II

vs

FREE-AIR TEMPERATURE

20

I'E

18

i=

16

~

Q;

o
c

.g

~

c.

e
a...

I

.I

~ VCC =5V

RL=280n

------

14
12

...

10

8

...

6

--

CL=150pF
• CL = 100 pF
CL = 25 pF

4

--

--

2

o

-75 -50

o 25 50 75
TA-Free-Air Temperature-OC

-25

100

125

FIGURE B3
0

tO ata for temperatures below oOe and above 70 e are applicable for Series 54H circuits only.

§ Data as shown are applicable specifically for the NAN 0 gates with totem-pole outputs.
1272

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

CALL.AS. TEXAS 75222

6-99

SERIES 54L/74L
LOW-POWER TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
OUTPUT VOLTAGE

OUTPUT VOLTAGE

vs

vs

INPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

0
5
0

-

51-0

5~
- ve~·
Rl·4kll- I--

-"

~

f"-

I\~'

, '\

~

0

~

TA • 125'e",,\

"'-

V-

TA -25'C

~

TA" -5S"C

,

0
5
0

0.5

t
>

o 1

I

I

1.5

o

2.5

''""

V-

~/
\. ~

'1

~

'\

~

1

o

-2

TA· 125'e

. / TA·25'e

f- TA· -55'C .../ ~

VI-Input Voltage-V

~~

~
-3

-4

-5

-6

-7

IOH-Hlgh·Level Output Current-mA

FIGURE C1

FIGURE C2

OUTPUT VOLTAGE

CLOCK INPUT CURRENT PER FLIP-FLOP

LOW-LEVEL OUTPUT CURRENT
0.5

2

r

o. 1

4

INPUT VOLTAGE

0

~

~ 0.3

;g

rIi'-

1

0;

~ 0.21-+-+~~~+-+---i.,,-c.T-+-t

II

-

I

5

5

~~~;~~

i

2

~ 0.11-'"-+""""=-1-+-+-,

V

3

d
v

I- ~

~-

~

ETBl,INr

TS

Vee· 5 V
J. K ·ov

ISOLATE SLAVE
F ~OM ~ASTE A

I

Tl2T
-0. 4

o

0.5

IOl -Low-Level Output Current-rnA

1

1.5

2.2.5

5

5.5

FIGURE C4

POWER DISSIPATION PER FLIP-FLOP

9
::

VS

FREE-AIR TEMPERATURE

~~leC~O~kv.;;03 V ~

VIH clock

8

_

~ 2.4 V

5.0 r--r-.,----;---;----,---;--,---,

;:

Rl! 4 kiz
CL ,. 50 pF

~

Ij

I

~~t~ ~~~~ '" 50% ~fH----+-""'I>a+J+++++t

6 1---l-H+t-ttlH---,../yo<+-t+H-H

I 5~~~~~~~/~~~
~ _ . . . . Rl·~

o

R~.4kU

r-3

4.5
4.0

f--t--+---+--t---t--+--t--!

~ 3.5~-=F=;::::::f=+--.d--l--1--:l
~
"--V

2

1

4.5

AVERAGE TOTAL D-C POWER DISSIPATION
PER FLIP-FLOP

VS

~

4

FIGURE C3

FREQUENCY

t

3.5

VI-Input Voltage-V

10~~~~~~~-r_~~rn~

~

3

~

.;!!

el·o

&

3.0 f--t--+---+--t---t--+--t--!

2.51--+-.l..---'---+--4--+--f--~

~

C L = 30 pF

~ 2.0 -

2I---l-H+t-t+It--+--+-H-t-H-ti

1-

~'.5-

0 0.1

0.2

0.4

0.7 1

.r
710

1.0

:"75 -50

f-Frequency-MHz

Vee'" 5 V
Vil clock = 0.3 V

VIH clock

=

2.4 V +--4--+--I-~

PTIH) + PTll)
PTlav) - - - 2 - - - - - l - - t - - i

I I I I
-25
25
50
75
TA-Free-Alr Temperature- °c

100

125

FIGURE C6

FIGURE C5

tData for temperatures below O°C and above 70°C are applicable for Series 54L circuits only.
§ Unless otherwise noted. data as shown are applicable specifically for the NAND gates with totem-pole outputs.

127

6-100

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SERIES 54L/74L
LOW-POWER TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
PROPAGATION DELAY TIMES
vs
LOAD CAPACITANCE
50

I

vCC = 5 V
RL = 40 kn
40 TA = 25°C tPLH--...
~~
I
35

45
'"
r:::

J,

E

I

i=

30

~

25

.~

20

>
co

r:::

Cl

co

C-

~

?

c
~

.,V

---

>
co
~

I--'"

g'
Co

tPHL·...J

20

«

15

10

45
40

E 35

N

::r:
...J

10

20

30 40 50

60

70

80

~75

e-

90 100

-50 -25

o

50

25

75

100

CL -Load Capacitance-pF

T A-Free-Air Temperature-OC

FIGURE C7

FIGURE C8

PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE

PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE

".......

tpLH-

.....

45

1\

~~

\

~~

--r--.-

-

#

~

tpHL

V

r:::
'"

40

E

35

J,

~

i= 30
>

tpLH

" ...........

:='\

~

""r----.. r--

tPH~J

co

~

25

r:::

125

II

25

--- V-

r:::
0

20

.~

Cl

g'
c-

co

c- 15
o

a:

5

50

i= 30

.~

25

10

::r:

e+

50

0

~

I

...J

o

~

...............

30

a:
~
>

15

o

J,

... ~

VCC = 5 V
RL = 4 kn
CL = 50 pF

.~

5

r:::
'"

40

§ 35

o

a:

50

E

i= 45

V

.-----~ f-(

AVERAGE PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE

o

a:

10 I- VCC = 5 V
RL = 40

kn

5 I- CL = 50 pF

~75

I

I

-50 -25

0

25

50

75

100

20
15
10 f- VCC = 5 V
f- RL = 4 kn
5
CL=50pF

~75

125

r,

I

-50 -25" 0

25

50

75

100 125

T A-Free-Air Temperature-OC

.T A-Free-Air Temperature-°c
FIGURE C9

FIGURE C10

t Data for temperatures below 0° C and above 70° C are applicable for Series 54L circuits only.
§ Data as shown are applicable specifically for the NAN D gates with totem-pole outputs.
127:'

TEXAS INCOHPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6-101

54LS/74LS
SCHOTTKY-CLAMPED LOW-POWER TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
HIGH-LEVEL OUTPUT VOLTAGE

OUTPUT VOLTAGE

VS

VS

INPUT VOLTAGE

4.0

r-

3.5

-

VCC - 5 V
RL -2kn

:--1\.

3.0

TA -125°C
2.0

0

1.5

~

2.5

0

2.0

!

1\ \ TA--55°C

1.5

J:

1.0

!.:0

l

I~

1.0

> 0.5

0.5

o

o

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

-2

2

-4

-6

-8

-

I~

r-----

'~

-10 -12 -14 -16

'OH-High·Level Output Current-rnA

VI-Input Voltage-V

FIGURE 01

FIGURE 02

LOW-LEVEL OUTPUT VOLTAGE

POWER DISSIPATION PER GATE
vs
FREQUENCY

VS

LOW-LEVEL OUTPUT CURRENT
0.5 ,..----,.---,----r-"T---,-,-,..--,

25

VCC - 5 V
TA-25°C

>

~
!3

VCC - 5 V
VI-0.7 V
TA-125,'C
~
TA - 25·C-·-r-----

~~
TA·-55·d~,

\

I

0

>

'"----- ~
--.....

3.0

"0

>

2.5

~

---...

3.5

~

1\" TA - 25°C

>I

~

>

-I

\,\

HIGH-LEVEL OUTPUT CURRENT

4.0

0.4

1--+--+--+--+---+---I'-'---1-t"7"+-:71

0.3

1-+-+-+-+-+7'fS>1.L...t--+--1

0.2

I-h..f"-:~+-+-+-1-t--+--1

Duty Cycle = 50%

/

"0

>

<5

5
~

II

o~ 0.1
>

CL'50 PF ' j
RL -2 kn
CL - 15 pF
RL-2kP."

i«,L+-+--+--+--+-+--I-r-t----1

I

./

Illl--t:

.... CL· 0
RL _00

IIIII
o

1

2

3

4

5

6

7

8

9

10

0.1

0.4

IOl -Low-Level Output Current-rnA

14

20

..,o

;!!

16

~

14

i=

12

~

10

.Q

8

'.;;

i

6

0..

4

o
25

50

75

VCC - 5 V
RL - 2 kn
TA - 25'C

100 125

L.

V
tPHL

[

e

0

PROPAGATION DELAY TIMES
vs
LOAD CAPACITANCE

18

-+---+---1-+--+---1

-75 -50 -25

40

FIGURE 04

PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE
VCC - 5 V
CL - 15 pF
RL' 2 kn

10
f-Frequency-MHz

FIGURE 03

16

J

V

--

o

lA-free-Air Temperature-OC

...----:: V V

10 20

30 40 50

V

VI--'" ......

tPLH

-

60 70 80 90 100

CL-Load Capacitance-pF

FIGURE 06

FIGURE 05

tData for temperatures below OOC and above 70°C are applicable for Series 54LS circuits only.
§ Data as shown are applicable specifically for the NAND gates with totem-pole outputs.

127:

6-102

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALL.AS, TEXAS 75222

SERIES 54S/74S
SCHOTTKY-CLAMPED TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§

INPUT-CLAMPING-DIODE
FORWARD VOLTAGE
vs
FREE-AI R TEMPERATURE

OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4.0 r--..,.---r---r----r-r--r---r---.------r-,
VCC - 5 V
RL' 280 n

-1.00

VCC' 5 V

-0.96
-0.92

TA' -55°C-+--+-+-H_-\+-'-+--+---l

\

--.....,

-0.88

2.5 1----t--+--+---+-f--\-1\-+--+--+---l

-.... r:- ............

-0.84

2.0 f-+--+--+-+-+4+\+--1I--+-+---1

-0.80

---

tOL--1Bm0

-0.76

-0.72
1.0 f-+--+--+-+-l--!II--1-a--+-+---l
-0.68
-0.64

IOL - -25 rnA

.::::r-J.

~

r--. 'OL i

o

0.2 0.4

0.6 0.8

1.0 1.2

1.4 1.6

-0.6!l.75

1.8 2.0

-50 -25

0

FIGURE E1

125

1.0

. .--- J '1~5°C

0.9

A

VCC· 5 V
,

>

~ 0.8

Ii'

~

TA =2S C

0.7

~ 0.6

~

0.5

~

0.4

~

TA - _55°C

-10

100

LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT

0

°0

75

FIGURE E2

HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT

I
~~
~k
~l'-.
~
r~

50

'i'A

TA-Free-Air Temperature-OC

VI-Input Voltage-V

~

25

-10

r-+-

o~~~~~-~~~~~~

~

TA~-55°Cl

I "~
,.k ~

~ 0.2 /

O. 1~

~

- 20 -30 -40 -SO -60 -70
IOH-High-Levei Output Current-mA

,

TA- 25° c l

~ 0.3

I\.

./

o

-80

o

I

II

~~

"--TA-125°C

15

20

25

30

35

40

IOL -Low-Level Output Current-mA

FIGURE E4

FIGURE E3

HIGH-LEVEL INPUT CURRENT
vs
FREE-AIR TEMPERATURE

INPUT CURRENT
vs
INPUT VOLTAGE

~

VCC 5 V
TA - 25°C
-2

,/"

{

0.7~~
0.4~

-6
-8

m

0.2f---+-+----t--1------+-:.,."-/'-t---l--l

0.1~~/

-12

0.07

-14

0.04

-16

0.02f--+-/-----''f---+--+--+--+--+----l

-18
-2

0.02::75,........,-5:':-0--,~--:':---::2:':-5--::5:':-0--::7:':-5-""10""'0----:-:'125
T A-F ree-Air Temperature-<> C

VI-Input Voltage-V

F-IG"URE E5

FIGURE E6

0

tO ata for temperatures below oOe and above 70 e are applicable for Series 54S circuits only.
§ Data as shown are applicable specifically for the NAN 0 gates with totem-pole outputs.
1272

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

6·103

SERIES 54S/74S
SCHOTTKY-CLAMPED TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICSt§
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT

PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs

vs

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

10

10

~

---

VCC 5 V
RL - 280 n
CL - 150 pF

~

L-- ~

1
r---

.....

CL"" 15 pF

L-- ~

I

C;:L

-50

-25

0

25

50

75

100

o

125

~

50 pF

15 pF

I
I
I

1

o

-75

-t---

CL' 150pF

c!.

--

CLI. 50plF

RL' 280!l
6
TA" 25 C

I

4.5

TA-Free-Air Temperature- °c

4.75

5.25

vee-Supply VOltage-V

FIGURE E7

FIGURE E8
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVE L OUTPUT

PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs

vs

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

10

~

......... f-.

•

I"~

-

...... i""- "'-

RL' 280

VCC' 5 V
RL" 280 n

n

\----\----\---4TA - 25"C

~c 8~~-===~==C;L~.~15~0~PF~-=T=~=---=i

CL' 150 pF

~~

7~--+_--+_--+--~

05

6~--+_--+_--+--~
CL '" 50 pF

~~
c ~

CL' 50 pF

Ii :\----\----\---+--~

~~ 3~====t==C~L='=15~P=F====*-___~

CL' 15pF

J:",
.'!-J:

1

o

-75

0L-_ _L-____L-____
25

-50

50

75

100

125

4.5

T A-free-Air Temperature-OC

vs

vs

FREE-AIR TEMPERATURE

FREQUENCY

VCC

I---+"'---+--+-J+--J+---+ RL

,:

I ~

_____
5.5

POWER DISSIPATION PER GATE

AVERAGE PROPAGATION DELAY TIME

I

~

5.25

FIGURE E10

FIGURE E9

E

5.0

Vcc-Supp!v VOltage-V

=

80 r----,--,r-r"'T""T"T'TT,.----,--,r-r"T"TTT'T'I

~5V

VCC = 5 V
CL = 15 pF
TA = 25'C
Duty Cycle = 50%

280 !l

CL=150 pF_f--;;;::p-'

Oi

"
~

++I+---jH-+-++t++l

50

~

£

40

j

30

I;

Vl---

I

20

!IN

2

I---I--t---+-I---+-t----t---

10

__L--L__L--L__L-~~

0

O~-L

-75

-25

0

1

TA-free-AirTemperature-OC

40

70 100

f-Frequency-MHz

FIGURE E11

FIGURE E12

t Data for temperatures below OoC and above 70° C are applicable for Series 54S circuits only.
§ Data as shown are applicable specifically for the NAND gates with totem-pole outputs.
127:

6-104

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SERIES 54S/74S
SCHOTTKY-CLAMPED TRANSISTOR-TRANSISTOR LOGIC
TYPICAL CHARACTERISTICS FOR FLlP-FLOPSt
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT

-=T~'

..........."

~K
~~

LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.0
0.9

Jc

I

~ 0.8

Ii

g 0.7

T A' 25°C

~

~~

TA'-55°C~

:I:
I
1:

~

1

-20

-30

TA/,-wCl

~

-40

~

~

TA - 25°Cl

~
-60 -70

-50

o. 3

~o 2 " -

r\.

o

" - T A - 125°C

o

15

IOH-High-Leliel Output Current-rnA

35

FREE-AIR TEMPERATURE
10
7 VCC - 5 V
V,-2.7V

"-<;".f

«

~

INPUTS
/ 1//
/1/ '-PRESET/CLEAR INPUTS

a

(l~cLOc~ INP0T

1
0.7
0.4

3

-10

./

/'

0.2

:If
VCC'5VTA-25°C_

-16

1

-18
-2

0.0 7

30.04

V

0.02

I

./

/'

0.0 1

I

-75 -50

VI-Input Voltage-V

100

125

TA-Free-AirTemperature-OC

FIGURE E15

FIGURE E16

'5112, '5113. '5114
AVERAGE'PROPAGATION DELAY TIME,
CLOCK TO OUTPUT
. vs
FREE-AIR TEMPERATURE

'5112, '5113, '5114
AVERAGE PROPAGATION DELAY TIME,
CLOCK TO OUTPUT
vs
LOAD CAPACITANCE
16

14

VCC' 5 V
RL • 280 n

I

-t--+-t--+-t--t

.:

0;

0;

o

o

I--",...-=I:_::--+__C..l:

I

15~ pF_

-7

T

-

C~. 50 pF
CL- 15 pF

I

:f-+--4---+-l--+-+---l--l
-75 -50 -25

25

50

75

100

125

T A-Free-Air Temperature-OC

I
t

V~C·

5'V
C-RL-2Bon
TA" 2SOC

E

I-

10

•
I

LV

~ O. 1

-12

t
~IN

30

HIGH-LEVEL INPUT CURRENT

" - J/K

I

25

FIGURE E14

'5112, '5113
INPUT CURRENT
vs
INPUT VOLTAGE

-8

20

IOL -LoVl/-level Output Current-mA

FIGURE E13

-2

"

~P"

o. 1~

-80

./

I..., ~
..1 ~

~

-' 0 4

o

-10

06

~ a5

>

00

VCC' 5/V

>

12

B

r

/'

V

....--V

V V

0
50

75

100

125

150

175

200

Cl-Load Capacit8nce-pF

FIGURE E18

FIGURE E17
tData for temperatures below OOC and above 70°C are applicable for Series 54S circuits only.
1272

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX S012 •

DALLAS. TEXAS 7S222

6-105

•

6-106

54/74 Family
MSI/LSI Circuits

•
I

7-1

a-

7·2

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

The following pages contain functional indexes and selection guides designed to simplify the choit:e of a particular
function to fit a specific application. Essential characteristics of similar or like functions are grouped for comparative
analysis, and the electrical specifications are referenced by page number. The following categories of functions are
covered:
Page
Adders
..................... .
Accumulators, arithmetic logic units, look·ahead carry generators
Multipliers . . . . . .
Comparators . . . . . .
Parity generators/checkers .
Other arithmetic operators
Quad,hex, and octal flip-flops
Register files . . . .
Shift registers . . . .
Other registers
Latches . . . . . .
Clock generator circuits
Code converters . . . .
Priority encoders/registers
Data selectors/multiplexers
Decoders/demultiplexers
............ .
Open-collector display decoders/drivers with counters/latches
Open-collector display decoders/drivers . . . . . . . . .
............ .
Bus transceivers and drivers
Asynchronous counters (ripple clock) -negative-edge triggered
Synchronous counters-Positive-edge triggered
Bipolar bit-slice processor elements
First·in first-
~

H

H

L

H

L

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H = high level, L = low level
,076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-15

•

~

C)

......

:D~c:n~

!::
:l

-

~,:..Z-a
U'I

~ ~z~rn

i

g'

~ rn

C"

00 N

~ ~.!.t

en
en
Z

U'I

m.!..en~
:DC
0. <0'
Z,p.
_. "r- .....
N

g"

til

~

Olzt>
mN-4

-

Dl

-

a =
>::
m-4=
Dl

5.
~

::T
CD

~

,,~

g
-I

~

(TI

::t,

>

o
......
:i'

><

~

~ (J1
III o z_

-g

~8Z
~;(J1
. 0-i
~;o
~c:

::it
Dl

:l

0.

o

.g

03::

!::

'43A, 'L43
EXCESS-3-TO-DECIMAL DECODERS

'42A, 'L42, 'LS42
BCD-TO-DECIMAL DECODERS

(TI

z

-i
(J1

'42A THRU '44A
'L42 THRU 'L44

'LS42

EQUIVALENT OF
EACH INPUT

EQUIVALENT OF
EACH INPUT

vee3--

Vee

--

'42A THRU '44A
'L42 THRU 'L44
TYPICAL OF
ALL OUTPUTS

-.---Vee

'LS42
TYPICAL OF
ALL OUTPUTS

--,::-:;,;;-nT

U'I

- .....

5a~en
.!..~z

CenU'l
-

Z

~~

r-N

~-4

-4::
::=
=C
Cen
en 2

..... ~

~~

Vee

~~

Z

,.l1li •
OUTPUT

~

r-

~
N
'42A THRU '44A: Req

=4

kSl. NOM

'L42 THRU 'L44: Req = 8 kSl. NOM

!:l

'42A THRU '44A: R

= 130 Sl.

NOM

'L42 THRU 'L44: R = 260 Sl. NOM

~

.........

-en
OUTPUT

~

-~>
'~-

zU'I

17 kSl. NOM
INPUT

r+

1/1

= en
=
m c:z
=
en en
Z t
0

~

Req

INPUT

'44A, 'L44
EXCESS-3-GRAY-TO-DECIMAL DECODERS

n::c

TYPES SN5442A, SN5443A, SN5444A, SN7442A, SN7443A, SN7444A
4-UNE-TO-10-UNE DECODERS (1-0F-10)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
...... .
Input voltage . . . . . . .
...... .
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to netyvork ground terminal.

recommended operating conditions
SN7442A

SN5442A

MIN
Supply voltage, Vee

SN5443A

SN7443A

SN5444A

SN7444A

NOM

4.5

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM

UNIT
MAX

5

-800

Low-level output current, 10L

16

Operating free-air temperature, T A

-55

125

0

5.25

V

800

JJA

16

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONSt

PARAMETER

VIH

High-level input voltage
Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

SN7443A

Vee= MIN,

II = -12mA

Vee= MIN,

VIH=2V,

VIL=0.8V,

10H = -800 JJA

Vee= MIN,

VIH=2V,

VIL=0.8V,

10L = 16 mA

UNIT

SN7444A

TYPt MAX

MIN

TYP:f MAX

2

2

Low-level output voltage

VOL

SN7442A

SN5443A
SN5444A
MIN

VIL

SN5442A

2.4

0.8

-1.5

-1.5

3.4
0.2

V

0.8

2.4
0.4

V
V

3.4
0.2

V

0.4

V

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

1

1

IIH

High-level input current

Vee = MAX, VI = 2.4 V

40

40

JJA

IlL

Low level input current

Vee = MAX,

VI = 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output current §

Vee = MAX

-55

mA

lee

Supply current

Vee = MAX, See Note 2

56

mA

t For conditions

-20

-55
28

-18

41

28

mA

•
I

shown as M IN or MAX, use the appropriate values specified under recommended operating conditions.

:fAil typical values are at Vee = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time.
NOTE 2:

ICC is measured with all outputs open and all inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

-

TEST CONDITIONS

PARAMETER
Propagation delay time, high-to-Iow-Ievel
tpHL

output from A, B, e, or D through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel

tpHL

eL=15pF,

output from A, B, e, or D through 3 levels of logic

RL = 400

Propagation delay time, low-to-high-Ievel
tpLH
tPLH
NOTE 3:

output from A, B, e, and D through 3 levels of logic

TYP

MAX UNIT

14

25

ns

17

30

ns

10

25

ns

17

30

ns

n,

See Note 3

output from A, B, e, and D through 2 levels of logic
Propagation delay time, low-to-high-Ievel

MIN

Load circuits and waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7·17

TYPES SN54L42, SN54L43, SN54L44, SN74L42, SN74L43, SN74L44
4-UNE-TO-10-UNE DECODERS (1-0F-10)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
....... .
I nput voltage . . . . . . .
....... .
Operating free-air temperature range: SN54L' Circuits.
SN74L' Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54L42

MIN

SN74L43

SN54L44

SN74L44

NOM

4.5

Supply voltage, Vee

SN74L42

SN54L43

5

MAX

MIN

5.5

4.75

NOM
5

-400

High·level output current, 10H

8

Low·level output current, 10L
Operating free-air temperature, T A

-55

125

0

UNIT
MAX
5.25

V

-400

pA

8

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER

•

VIH

High·level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

VOH

High·level output voltage

VOL

Low-level output voltage

II

MIN

TYPt

MAX UNIT
V

2
Vee- MIN,

11=-12mA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -400 JlA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10L = 8mA

Input current at maximum input voltage

Vee = MAX,

VI = 5.5 V

2.4

0.8

V

-1.5

V
V

3.4
0.2

0.4
1

V
mA

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

20

JlA

IlL

Low·level input current

Vee= MAX,

VI = 0.4 V

-0.8

mA

lOS

Short·circuit output currentS

Vee= MAX

-28

mA

ICC

-9

I

Vee - MAX,

Supply Current

SN54L'

14
14

I SN74L'

See Note 2

22
28

mA

tFor conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
tAil typical values are at Vee = 5 V, TA = 25°e.
§Not more than one output should be shorted at a time.
NOTE 2: lec is measured with all outputs open and inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e
TEST CONDITIONS

PARAMETER
Propagation delay time, high·to·low-Ievel
tPHL

MIN
10

output from A, B, C, or D through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel

tpHL

CL=15pF,

output from A, B, C, or D through 3 levels of logic

See Note 3

output from A, B, C, and D through 2 levels of logic
Propagation delay time, low-to-high-Ievel

tPLH

MAX UNIT

44

60

ns

46

70

ns

J4

50

ns

52

70

ns

RL = 800 .0.,

Propagation delay time, low·to-high-Ievel
tPLH

TYP

output from A, B, C, and D through 3 levels of logic

10

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1071

7-18

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS42, SN74LS42
4-LlNE-TO-1O-LiNE DECODERS (1-0F-1O)
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS42
SN74LS42
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS42
Supply voltage, Vee

MIN

NOM

4.5

5

SN74LS42

MAX

MIN

NOM

5.5

4.75

5

-400

High-level output current, 10H

MAX
5.25

V

-400

J.LA

S

mA

70

°e

4

Low-level output current, IOL
-55

Operating free-air temperature, T A

125

UNIT

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER
V,H

High-level input voltage

V,L
V,K

Low-level input voltage

VOH

output voltage

VOL Low-level output voltage
Input current at
"

maximum input voltage

TYP+

SN74LS42

MAX

Vee = MIN,

1,=-1SmA

Vee= MIN,

V'H=2V,

V,L = V,L max, 10H = -400 J.LA
Vee= MIN,

V,H = 2 V,

V,L = V,L max

2_5

-1.5

-1.5
2.7

0.4

V, = 7V

UNIT
V

O.S

I'OL = SmA

Vee= MAX,

TYP+ MAX

0.7

3.5
0_25

I'OL = 4 mA

MIN
2

2

Input clamp voltage
Hig~-Ievel

SN54LS42
MIN

3_5

V
V

0.25

0.4

0.35

0.5

0.1

V

0.1

V
mA

"H

High-level input current

Vee = MAX,

V, = 2.7 V

20

20

J.LA

',L

Low-level input current

Vee = MAX,

V, = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee= MAX

lee

Supply current

Vee= MAX,

-100

-20
See Note 2

7

-20

13

7

-100

mA

13

mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V r.r. = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

•

NOTE 2. ICC is measured with all outputs open and inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e
TEST CONDITIONS

PARAMETER

MIN

TYP

Propagation delay time, high-to-Iow-Ievel
tpHL

output from A, B, e, or 0 through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel

tpHL

eL

output from A, B, e, or 0 through 3 levels of logic
Propagation delay time, low-to-high-Ievel

tpLH

= 15pF,

RL = 2 kn,
See Note 4

output from A, B, e, and 0 through 2 levels of logic
Propagation delay time, low-to-high-Ievel

tPLH

output from A, B, e, and 0 through 3 levels of logic

MAX UNIT

15

25

ns

20

30

ns

15

25

ns

20

30

ns

NOTE 4: Load circuit and voltage waveforms are shown on page 3·11.

)76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-19

TIL

TYPES SN5445, SN7445
BCD-TO-DECIMAL DECODERS/DRIVERS

MSI

BULLETIN NO. DL-S 7211816, DECEMBER 1972

FOR USE AS LAMP, RELAY, OR MOS DRIVERS
SN5445 ••• J OR W PACKAGE
SN7445 ••• J OR N PACKAGE
(TOP VIEW)

featuring
•

Full Decoding of Input Logic

•

80-mA Sink-Current Capability

•

All Outputs Are Off for Invalid
BCD Input Conditions

logic
FUNCTION TABLE
NO.

D

C

B

A

0

1

0

L

L

L

L

L

H

1

L

L

H

L

L

L

L
H

H

2

L

H

H

3

L

L

H

H

H

H

4

L

H

L

H

L

H

L

L
H

H

5

H

H

6
7
8

L

H

H

L

H

H

L

H

H

H

H

H

H

L

L

L

H

H

9

H

L

L

H

H

H

H

L

H

L

H

H

0

H

L

H

H

H

H

:J

H
H

H
H

L

L

H

H

L

H

H

H

H

H

H

H

H

L
H

H

H

H

H
H

~

>
~

•

OUTPUTS

INPUTS

2 3
H H
H H
L H
H L
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H

4

5

6

7

8

9

H
H

H

H

H

H

H

H

H

H

H

H

H

H
H

H

H
H

H

H

H

H
H

L

H

H

H

H
H

H

L

H

H

H

H

H

H
H

L

H

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H
H
H

H

H
H
H

H
H

H

H
H

H
H
H

H

H

H

H

H

H

H

H
H

H
H

H
H

H

H

H

.

OUTPUTS

~ositive

logic: see function table

functional block diagram

H
H

H = high level (off), L = low level (on)

description
These monolithic BCD·to·decimal decoders/drivers
consist of eight inverters and ten four·input NAND
gates. The inverters are connected in pairs to make
BCD input data available for decoding by the NAND
gates. Full decoding of valid BCD input logic ensures
that all outputs remain off for all invalid binary input
conditions. These decoders feature TTL inputs and
high-performance, n·p·n output transistors designed
for use as indicator/relay drivers or as open·collector
logic-circuit drivers. Each of the high·breakdown
output transistors (30 volts) will sink up to 80
milliamperes of current. Each input is one normalized
Series 54/74 load. Inputs and outputs are entirely
compatible for use with TTL or DTL logic circuits,
and the outputs are compatible for interfacing with
most MOS integrated circuits. Power dissipation is
typically 215 milliwatts.

1076

7-20

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN5445. SN7445
BCD-TO-DECIMAL DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . .
Maximum current into any output (off-state)
Operating free-air temperature range: SN5445 Circuits
SN7445 Circuits
Storage temperature range

7V

5.5 V
lmA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN7445

SN5445
MIN
4.5

Supply voltage, V CC

NOM
5

Off-state output voltage

MAX

MIN

5.5

4.75

NOM
5

30
-55

Operating free-air temperature, T A

125

0

MAX
5.25

UNIT
V

30

V

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VO(on)

MIN

TYP+

MAX

2
VCC~

II

MIN,

VCC~ MIN,

On-state output voltage

~

I
I

VIL ~ 0.8 V
VCC

Off-state output current

~

V

-12 rnA

VIH ~ 2 V,

MIN, VIH~2V,

10(on) ~ 80 rnA

UNIT

0.5

10(on) ~ 20 rnA

0.8

V

-1.5

V

0.9
0.4

V

VIL ~ 0.8 V,

VO(off) ~ 30 V

250

J1.A

II

Input current at maximum input voltage

VCC~

MAX,

VI

~

5.5 V

1

rnA

IIH

High-level input current

VCC~

MAX,

VI

~

2.4 V

40

J1.A

IlL

Low-level input current

VCC - MAX,

VI - 0.4 V

-1.6

rnA

ICC

Supply current

Vee ~ MAX, See Note 2

10(off)

I
I

SN5445

43

62

SN7445

43

70

rnA

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type .
+AII typical values are at Vce ~ 5 V. T A ~ 25°C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.

switching characteristics, Vee

= 5 V, T A = 25° C

I

TEST CONDITIONS

PARAMETER
Propagation delay time, low-to-high-Ievel output
tpHL
NOTE 3:

Propagation delay time, high-to-Iow·level output

•

CL ~ 15 pF,

RL ~ 100

n,

MIN

TYP

See Note 3

MAX
50
50

Load circuit and waveforms are shown on page 3-10.

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ALL INPUTS
Vee ______-.~--__

INPUT

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-21

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
BULLETIN NO. DL-S 7611811, MARCH 1974-REVISED OCTOBER 1976

'48, 'LS48
feature

'46A, '47A, 'L46, 'L47, 'LS47
feature

'49, 'LS49
feature

Open-Collector Outputs
Drive Indicators Directly

•

•

Lamp·Test Provision

•

Lamp·Test Provision

•

Leading/Trailing Zero
Suppression

•

Leading/Trailing Zero
Suppression

•

•

Internal Pull·Ups Eliminate
Need for External Resistors

•

Open·Collector Outputs

•

Blanking Input

All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS

TYPE

•

TYPICAL

ACTIVE

OUTPUT

SINK

MAX

POWER

LEVEL

CONFIGURATION

CURRENT

VOLTAGE

DISSIPATION

PACKAGES

SN5446A

low

open-collector

40mA

30 V

320mW

J,W

SN5447A

low

open-collector

40mA

15 V

320mW

J,W

SN5448

high

2-kl1 pull-up

6.4 mA

5.5 V

265mW

J,W

SN5449

high

open-collector

10mA

5.5 V

165mW

W
J

SN54L46

low

open-collector

20 mA

30 V

160mW

SN54L47

low

open-collector

20mA

15V

160mW

SN54LS47

low

open-collector

12mA

15 V

35mW

J,W
J,W

J

SN54LS48

high

2-kl1 pull-up

2mA

5.5 V

125mW

SN54LS49

high

open-collector

4mA

5.5 V

40mW

J,W

SN7446A

low

open-collector

40mA

30 V

320mW

J, N

SN7447A

low

open-collector

40mA

15V

320mW

J, N

SN7448

high

2-kl1 pull-up

6.4 mA

5.5 V

265mW

J, N

SN74L46

low

open-collector

20mA

30V

160mW

J, N

SN74L47

low

open-collector

20mA

15V

160mW

J, N

SN74LS47

low

open-collector

24mA

15 V

35mW

J, N

SN74LS48

high

2-kl1 pull-up

6mA

5.5 V

125mW

J, N

SN74LS49

high

open-collector

8mA

5.5 V

40mW

J, N

'48, 'LS48
(TOP VIEW)

'46A, '47A, 'L46, 'L47, 'LS47
(TOP VIEW)

LAMP

RS

RS

TEST

~f·

pl~T

'49, 'LS49
(TOP VIEW)

~
INPUTS

positive logic: see function tables

107(

7·22

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description
The '46A, 'L46, '47A, 'L47, and 'LS47 feature active-low outputs designed for driving common-anode VLEDs or
incandescent indicators directly, and the '48, '49, 'LS48, 'LS49 feature active-high outputs for driving lamp buffers or
common-cathode VLEDs. All of the circuits except '49 and 'LS49 have full ripple-blanking input/output controls and a
lamp test input. The '49 and 'LS49 circuits incorporate a direct blanking input. Segment identification and resultant
displays are shown below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input
conditions.
The '46A, '47A, '48, 'L46, 'L47, 'LS47, and 'LS48 circuits incorporate automatic leading and/or trailing-edge
zero-blanking control (RBI and RBO). Lamp test (LT) of these types may be performed at any time when the BI/RBO
node is at a high level. All types (including the '49 and 'LS49) contain an overriding blanking input (BI) which can be
used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for
use with TTL or DTL logic outputs.
The SN54246/SN74246 through '249 and the SN54LS247/SN74LS247 through 'LS249 compose the 5 and
the 9 with tails and have been designed to offer the designer a choice between two indicator fonts. The
SN54249/SN74249 and SN54LS249/SN74LS249 are 16-pin versions of the 14-pin SN5449 and 'LS49. Included in the
'249 circuit and 'LS249 circuits are the full functional capability for lamp test and ripple blanking, which is
not available in the '49 or 'LS49 circuit.

f-:-Ib

el-Ic

2

7
NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS

-d-

SEGMENT
IDENTIFICATION
'46A, '47A, 'L46, 'L47, 'LS47 FUNCTION TABLE
DECIMAL

INPUTS

OR
FUNCTION

LT

RBI

0

H

H

1

H

X

2

H

X

3

H

4
5

D

OUTPUTS

Bl/RBOt

NOTE

b

c

ON

ON

ON

ON

ON

ON

9
OFf

OFF

ON

ON

OFF

OFF

,OFF

OFF

ON

ON

OFF

ON

ON

OFF

ON

H

ON

ON

ON

ON

OFF

OFF

ON

L

H

OFF

ON

ON

OFF

OFF

ON

ON

H

H

ON

OFF

ON

ON

OFF

ON

ON

a

C

B

A

L

L

L

L

H

L

L

L

H

H

L

L

H

L

H

X

L

L

H

H

H

X

L

H

L

H

X

L

H

L

d

e

f

6

H

X

L

H

H

L

H

OFF

OFF

ON

ON

ON

ON

ON

7

H

X

L

H

H

H

H

ON

ON

ON

OFF

OFF

OFF

OFF

8

H

X

H

L

L

L

H

ON

ON

ON

ON

ON

ON

ON

9

H

X

H

L

L

H

H

ON

ON

ON

OFF

OFF

ON

ON

10

H

X

H

L

H

L

H

OFF

OFF

OFF

ON

ON

OFF

ON

11

H

X

H

L

H

H

H

OFF

OFF

ON

ON

OFF

OFF

ON

12

H

X

H

H

L

L

H

OFF

ON

OFF

OFF

OFF

ON

ON

13

H

X

H

H

L

H

H

ON

OFF

OFF

ON

OFF

ON

ON

14

H

X

H

H

H

L

H

OFF

OFF

OFF

ON

ON

ON

ON

15

H

X

H

H

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

•
I

1

BI

X

X

X

X

X

X

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

2

RBI

H

L

L

L

L

L

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

3

LT

L

X

X

X

X

X

H

ON

ON

ON

ON

ON

ON

ON

4

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (ABI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any
other input.
3. When ripple-blanking input (ABI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go off and the ripple-blanking output (A BO) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BI/ABO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are on.
tBI/ABO is wire·AND logic serving as blanking input (BI) and/or ripple-blanking output (ABO).
076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-23

TYPES SN5446A, '47A, '48, '49, SN54l46, 'l47, SN54lS47, 'lS48, 'lS49,
SN7446A, '47A, '48, SN74l46, 'l47, SN74lS47, 'lS48, 'lS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
'48, 'LS48
FUNCTION TABLE
DECIMAL
OR
FUNCTION
0
1
2
3
4
5

6
7

8
9
10
11
12
13
14
15
BI
RBI
LT

INPUTS
LT
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L

RBI
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X

D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
X

C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
X

OUTPUTS

BI/RBOt

a

A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
L
X

B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L
X

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H

c

b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
L
H

H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L
L
H

NOTE

e

d
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
L
H

H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H

f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L
L
H

H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H

9
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
H

1

2
3
4

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high, if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are low regardless of the level of any
other input.

3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp-test input high, all segment outputs
go low and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple-blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

•

'49, 'LS49
FUNCTION TABLE
DECIMAL
OR
FUNCTION
0
1
2
3
4
5

6
7

8
9
10
11
12
13
14
15
BI

OUTPUTS

INPUTS
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X

C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X

B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X

NOTE
A
L
H
L
H
L
H
L
H
L
H
L
H
L

H
L
H
X

BI
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

a
H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L

b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L

c
H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L

d
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L

e
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L

f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L

9
L
L

H
H
H
H
H
L
H
H
H
H
H
H
H
L
L

1

2

level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired.
2. When a low logic level is applied directly to the blanking input (BI). all segment outputs are low regardless of the level of any
other input.

H

= high

3~

7-24

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48. 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
functional block diagrams
'46A, '47A, 'L46, 'L47, 'LS47

'48, 'LS48

INPUT (11
B

INPUT (2)

c

BLANKING
INPUT OR
RIPPLE·BLANKING
OUTPUT

-t===---____

RIPPLE;~~~~KING..!;{5,,-)

~~~

'49, 'LS49

•
I

74

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-25

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47,
SN7446A, '47A, '48, SN74L46, 'L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'46A, '47A, '48

'L46, 'L47 .

EQUIVALENT OF BI/RBO

EQUIVALENT OF BI/RBO

'46A, '47A, '48, '49, 'L46, 'L47

Q

EQUIVALENT OF EACH INPUT
EXCEPT BI/RBO

vee

2.4 kfl
NOM

Req

INPUT

Vee

Vee
6 kfl
NOM

--

SN54'/SN74': Req
SN54L'/SN74L': Req

=6
=8

kfl NOM
kfl NOM

'46A, '47A

'L46, 'L47

TYPICAL OF OUTPUTS
a THRU 9

TYPICAL OF OUTPUTS
a THRU 9

----------~~-.------Vee

-----------a--------~Vee

OUTPUT

OUTPUT

•
'48

'49
TYPICAL OF ALL OUTPUTS

TYPICAL OF OUTPUTS
a THRU 9

------------~-----Vee

------------e_----._Vee
2 kfl
NOM

OUTPUT

OUTPUT

3

7·26

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES ,SN54LS47, 'LS48, 'LS49, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'LS47, 'LS48, 'LS49

'LS47, 'LS48, 'LS49

_-

EQUIVALENT OF EACH INPUT
EXCEPT BI/RBO

vee

q

Req

INPUT

LT and RBI ('LS47, 'LS48): Req

EQUIVALENT OF BI/RBO

Vee

10 kn

__

NOM

= 20 kn

NOM

BI ('LS49): Req = 20 kn NOM
A, B,

e,

and 0: Req

= 25

kn NOM

'LS47

'LS48

TYPICAL OF OUTPUTS
a THRU 9

TYPICAL OF OUTPUTS
a THRU 9

----------~~--~~----vee

OUTPUT

•
I

'LS49
TYPICAL OF OUTPUTS
a THRU 9

------------.---- Vee

OUTPUT

174

TEXAS INCOHPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TeXAS 75222

7·27

TYPES SN5446A, SN5447A, SN7446A. SN7447A
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
1 mA
_55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

Supply voltage, Vcc (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Current forced into any output in the off state
Operating free-air temperature range: SN5446A, SN5447 A
SN7446A, SN7447 A
Storage temperature range
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

4.5

Supply voltage, Vee

NOM MAX
5

MIN

5.5

4.5

NOM MAX
5

SN7447A

SN7446A

SN5447A

SN5446A
MIN

MIN

NOM MAX

5.5 4.75

MIN

5.25 4.75

5

NOM MAX
5

5.25

UNIT
V

Oft-state output voltage, VO(oft)

a thru g

30

15

30

15

V

On-state output current, 10(on)

a thru g

40

40

40

40

mA

High-level output current, 10H

BI/RBO

-200

-200

-200

-200

j.lA

Low-level output current, 10L

BI/RBO

8

8

8

8

mA

70

°e

-55

Operating free-air temperature, T A

125

-55

125

0

70

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER

•

MIN

TYP:!: MAX UNIT
V

2

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

BI/RBO

VOL

Low-level output voltage

BI/RBO

10 (oft) Off-state output current

a thru g

VO(on) On-state output voltage

a thru g

II

I nput current at maximum input voltage

IIH

High-level input current

Any input
except B I/R BO
Any input
except BI/RBO

Vee= MIN,

II = -12 mA

Vee - MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -200j.lA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = 8mA

2.4

VO(off) = MAX

Vee - MIN,

VIH - 2 V,

VIL=0.8V,

10(on) = 40 mA

0.27

0.3

except BI/RBO

Low-level input current
Short-circuit output current

lee

Supply current

BI/RBO

V
0.4

V

250

j.lA

0.4

V

1

mA

Vee = MAX, VI = 2.4 V

40

j.lA

-1.6
mA

Vee= MAX, VI = 0.4 V

-4
-4

BI/RBO
lOS

V

Vee = MAX, VI=5.5V

Any input
IlL

V

-1.5
3.7

Vee - MAX, VIH = 2V,
VIL = 0.8 V,

0.8

Vee= MAX
Vee = MAX,
See Note 2

I

r

SN54'

64
64

SN74'

85
103

mA
mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee

= 5 V, TA = 25° C
TEST eONDITIONS

PARAMETER
Turn-off time from A input

ton

Turn-on time from A input

eL=15pF,

Turn-off time from RBI input

See Note 3

taft
ton

MIN

TYP

MAX UNIT
100

toff

RL = 120.0,

100
100
100

Turn-on time from RBI input

ns
ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toff corresponds to tpLH and ton 'corresponds to tpHL'

12

7-28

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54L46, SN54L47, SN74L46, SN74L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
...... .
I nput voltage . . . . . . .
...... .
Peak output current (tw';;;; 1 ms, duty cycle';;;; 10%)
Current forced into any output in the off state
Operating free-air temperature range: SN54L46, SN54L47
SN74L46, SN74L47
Storage temperature range

7V

5.5 V
200mA
1 mA
-55°C to 125°C
aOc to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54L46
MIN
Supply voltage, Vee

4.5

SN54L47

NOM MAX
5

5.5

MIN

SN74L46

NOM MAX

MIN

5.5

4.75

4.5

5

SN74L47

NOM MAX
5

5.25

MIN
4.75

NOM MAX
5

5.25

UNIT
V

Off-state output voltage, VO(off)

a thru g

30

15

30

15

V

On-state output current, 10(on)

a thru g

20

20

20

20

rnA

High-level output current, 10H

BI/RBO

-100

-100

-100

-100

JlA

Low-level output current, 10L

BI/RBO

4

4

4

4

rnA

70

°e

Operating free·air temperature, T A

-55

125

-55

125

0

70

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

BI/RBO

VOL

Low·level output voltage

BI/RBO

10 (off)
VO(on)

MIN

TYP+ MAX UNIT
V

2
Any input
except BI/RBO

Off-state output current

a thru g

On·state output voltage

a thru g

II

Input current at maximum input voltage

IIH

High-level input current

IlL

Low-level input current

Any input
except BI/RBO
Any input
except BI/RBO

VCC = MIN,

II = -12mA

Vce = MIN,

VIH-2V,

VIL = 0.8 V,

10H = -100JlA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = 4 rnA

2.4

VO(off) = MAX

Vee - MIN,

VIH-2V,

VIL = 0.8 V,

10(on) = 20 rnA

0.2

0.3

Short-circuit output current
Supply current

0.4

V

250

JlA

0.4

V
rnA

Vee = MAX, VI = 2.4 V

20

JlA

-0.8

except BI/RBO Vce = MAX, VI = 0.4 V
BI/RBO

V

1

BI/RBO
lOS

V

Vee = MAX, VI = 5.5 V

Any input

lee

V

-1.5
3.4

Vee - MAX, VIH=2V,
VIL = 0.8 V,

0.8

•

I

rnA

-2
-2

Vee = MAX
Vee = MAX,

ISN54L'

32

43

See Note 2

ISN74L'

32

52

rnA
rnA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5

switching characteristics, Vee

v.

=5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

toft

Turn-off time from A input

ton

Turn-on time from A input

CL=15pF,

toff

Turn-off time from RBI input

See Note 3

ton

Turn-on time from RBI input

MIN

TYP

MAX UNIT
200

RL=280n,

200
200
200

ns
ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toff corresponds to tpLH and ton corresponds to tpHL'

280

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

7-29

TYPES SN54LS47, SN74LS47
BCD -TO -S EVE N-S EGM ENT DECO DERS/D RIVE RS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . .

7V
7V

Input voltage . . . . . . . . . . . . . . .
Peak output current (tw ~ 1 ms, duty cycle ~ 10%)
Current forced into any output in the off state
Operating free-air temperature range: SN54LS47
SN74LS47
Storage temperature range

200mA
. . . . 1 mA
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS47
MIN

NOM

4_5

Supply voltage, Vee

SN74LS47

MAX

MIN

NOM

5.5

4.75

5

5

MAX
5.25

UNIT
V

Off-state output voltage, VO(otf)

a thru g

15

15

V

On-state output current, 10(on)

a thru g

12

24

mA

High-level output current, 10H

BI/RBO

-50

-50

J.lA

Low-level output current, 10L

BI/RBO

1.6

3.2

mA

70

°e

Operating free-air temperature, T A

-55

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

SN54LS47

TEST CONDITIONSt

MIN

•

a

I (oft)

High-level output voltage BI/RBO

Vee = MIN,

II = -18 mA

Vee= MIN,

VIH=2V,

2.4

VIL = VIL max, IOH = -50J.lA

Vee = MAX,

a thru g

On-state output voltage

VIH=2V,

II

Input current at maximum input voltage

Vee= MAX,

VI = 7V

High-level input current

Vee = MAX,

VI=2.7V

0.25

except BI/RBO Vee = MAX,

VI = 0.4 V

Low-level input current

BI/RBO
Short-circuit
lOS
ICC

output current

BI/RBO

-0.3

Vee = MAX

Supply current

Vee= MAX,

V
V

-1.5

-1.5

V

2.4
0.4

4.2

V

0.25

0.4

0.35

0.5
250

0.4

0.25

0.4

0.35

0.5

J.lA

V

Any input
IlL

UNIT

0.8

250

110(on) = 12 mA
VIH = 2 V,
VIL = VIL max 110(on) = 24 mA

IIH

MAX

0.7

4.2

VIL = VIL max, VO(off) = 15 V

a thru g

TYP+

V

Vee- MIN,

VO(on)

MIN
2

0.25

IIOL = 1.6 mA
VIH = 2 V,
VIL = VIL max IIOL = 3.2 mA

Low-level output voltage BI/RBO

Off-state output current

SN74LS47

MAX

2

Vee = MIN,

VOL

TYP+

See Note 2

0.1

0.1.

mA

20

20

J.lA

-0.4

-0.4

-1.2

-1.2

-2
7

-0.3

13

7

mA

-2

mA

13

mA

tFor CO~ditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+AII tYPical values are at V CC = 5 V, T A = 25 C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
toff

TEST CONDITIONS

MIN

TVP

Turn-off time from A input

MAX
100

ton

Turn-on time from A input

eL=15pF, RL = 665

toff

Turn-off time from RBI input

See Note 4

ton

Turn-on time from RBI input

n,

100
100
100

UNIT
ns
ns

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11; toft corresponds to tpLH and ton corresponds to tpHL'

12

7-30

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN5448, SN7448
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Supply voltage, Vee (see Note 1)
.... .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN5448
SN7448
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN5448
MIN
Supply voltage, Vee

4.5

High-level output current, 10H
Low-level output current, 10L

SN7448

NOM MAX

MIN

5.5 4.75

5

NOM MAX
5

5.25

a thru g

-400

-400

BI/RBO

-200

-200

a thru g

6.4

6.4

BI/RBO

8
-55

Operating free-air temperature, T A

8
0

125

70

UNIT
V
J.lA
mA
De

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

Output current

VOL

Low-level output voltage

TEST CONDITIONSt

MIN

TYP+ MAX UNIT

2
Vec = MIN,

II = -12 mA

a thru g

Vee = MIN,

VIH=2V,

2.4

4.2

BI/RBO

VIL = 0.8 V,

10H = MAX

2.4

3.7

Vee - MIN,

Vo = 0.85 V,

-1.3

-2

a thru g

II

Input current at maximum input voltage

IIH

High-level input current

V

Input conditions as for VOH

Any input
except BI/RBO
Any input
except BI/RBO

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = MAX

0.27

LOW-level input current

lOS

Short-circuit output current
Supply current

-1.5

V
V
mA

0.4

V

1

mA

Vee= MAX, VI = 2.4 V

40

J.lA

-1.6

except BI/RBO Vee= MAX, VI = 0.4 V

•

mA

-4

BI/RBO

lee

V

Vee = MAX, VI = 5.5 V

Any input
IlL

0.8

BI/RBO

-4

Vee= MAX
Vee - MIN,
See Note 2

I SN5448

I SN7448

53

76

53

90

mA
mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
D
:):AII typical values are at Vee = 5 V, T A = 25 e.
NOTE 2: ICC is measured with all outputs 0Pfiln and all inputs at 4.5 V.

switching characteristics, Vee

= 5 V, TA =25°e

PARAMETER

TEST CONDITIONS

tpHL

Propagation delay time, high-to-Iow-Ievel output from A input

tpLH

Propagation delay time, low-to-high-Ievel output from A·input

eL=15pF,

tpHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

See Note 5

tpLH

Propagation delay time, low-to-high-Ievel output from RBI input

MIN

TYP

MAX UNIT
100

RL = 1 kn,

100
100
100

ns
ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

)76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-31

I

TYPES SN54LS48, SN74LS48
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
7V
-55°C to 125°C
. aOe to 7aoe
-65°C to 15aoe

Supply voltage, Vee (see Note 1)
.... ..
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS48
SN74LS48
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74LS48

SN54LS48
MIN

NOM

4.5

Supply voltage. Vee
High-level output current, 10H
Low-level output current, 10L

MAX

MIN

NOM

5.5

4.75

5

5

MAX
5.25

a thru g

-100

-100

BI/RBO

-50

-50

a thru g

2

6

BI/RBO

1.6

3.2

-55

Operating free-air temperature, T A

125

0

70

UNIT
V
IJA
mA
°e

electrical characterIStics over recommended operating free-air temperature range (unless otherWise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

Output current

Vee = MIN,

11=-18mA

a thru g and

Vee = MIN,

VIH=2V,

BI/RBO

VIL = VIL max, 10H = MAX
Vee= MIN,

a thru g

Vo = 0.85 V,

Input conditions as for VOH

a thru g

•

Any input
except BI/BRO

V

2
0.8

V

-1.5

-1.5

V

4.2

2.4

4.2

V

-1.3

-2

-1.3

-2

mA

0.25

0.4

0.25

10L = 1.6 mA

0.4

0.25

0.4

0.35

0.5

0.25

0.4

0.35

0.5

V
10L = 3.2 mA

Vee = MAX,

VI = 7V

Vee= MAX,

VI = 2.7 V

except BI/RBO Vee = MAX,

VI = 0.4 V

Any input
except BI/RBO

BI/RBO
Short-circuit

ICC

output current

BI/RBO

-0.3

Vee= MAX

Supply current

Vee = MAX,

UNIT

0.7

0.1

0.1

rnA

20

20

IJA

Any input

lOS

MAX

VIH=2V,

maximum input voltage

Low-level input current

TYP+

V

Vee= MIN,

Input current at

IlL

MIN

10L = 6 mA

VIL = VIL max

High-level input current

MAX

2.4

10L = 2 mA

VIL = VIL max

Low-level output voltage

IIH

TYP:j:

VIH=2V,

BI/RBO

II

MIN
2

Vee= MIN,

VOL

SN74LS48

SN54LS48

TEST CONDITIONSt

See Note 2

-0.4

-0.4

-1.2

-1.2

-2
25

-0.3
25

38

mA

-2

mA

38

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee

= 5 V, T A = 25°e

PARAMETER

TEST CONDITIONS

tpHL

Propagation delay time, high-to-Iow-Ievel output from A input

eL=15pF,

tpLH

Propagation delay time, low-to-high-Ievel output from A input

See Note 6

tpHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

eL=15pF,

tpLH

Propagation delay time,low-to-high-level output from RBI input

See Note 6

MIN

TYP

MAX

RL=4kn,

100

RL=6kn,

100

100
100

UNIT
ns
ns

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1(

7-32

TEXAS INSTRUMENTS
TED
I NeOfl PORA

POST OFFICE BOX 5012

•

O.A.LLAS. TEXAS 75222

TYPE SN5449
BCD-TO-SEVEN-SEGMENT DECODER/DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage
....... .
Current forced into any output in the off state
Operating free-air temperature range
Storage temperature range

7V

5.5 V
1 mA

-55°C to 125°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN5449
Supply voltage, Vee

MIN

NOM

MAX

4.5

5

5.5

UNIT
V

High-level output voltage, VOH

5.5

V

Low·level output current, IOL

10

mA

Operating free·air temperature, T A

-55

125

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

High-level output current

SN5449

TEST CONDITIONSt

MIN

TYP+

MAX

V

2

VOL

Low-level output voltage

II

Input current at maximum input voltage

Vee - MIN,

11= -10 rnA

Vee- MIN,

VIH - 2 V,

VIL = 0.8 V,

VOH = 5.5 V

Vee = MIN,

VIH=2V,

VIL=0.8V,

IOL = 10 mA

Vee = MAX,

VI = 5.5 V

UNIT

0.27

0.6

V

-1.5

V

250

!loA

0.4
1

V
mA

IIH

High-level input current

Vee - MAX,

VI = 2.4 V

40

!loA

IlL

Low-level input current

Vee = MAX,

VI=O.4V

-1.6

mA

lee

Supply current

Vee - MAX, See Note 2

33

47

mA

TYP

MAX

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V. T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee

= 5 V, T A = 25°e

PARAMETER

TEST CONDITIONS

tPHL

Propagation delay time, high·to-Iow-Ievel output from A input

MIN

100

tPLH

Propagation delay time, low-to-high-Ievel output from A input

eL=15pF,

tPHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

See Note 5

tPLH

Propagation delay time, low-to-high-Ievel output from RB I input

RL = 667

n,

100
100
100

•

UNIT
ns
ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-33

TYPES SN54LS49, SN74LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . . .
Current forced into any output in the off state
Operating free·air temperature range: SN54LS49
SN74LS49
Storage temperature range

....

7V
7V
1 rnA

-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS49
MIN
Supply voltage, Vee

NOM

4.5

SN74LS49

MAX

MIN

NOM

5.5

4.75

5

5

High-level output voltage, VOH
-55

5.25

UNIT
V

5.5

5.5

4

8

mA

70

°e

Low-level output current, IOL
Operating free-air temperature, T A

MAX

125

0

V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

,

PARAMETER

•

SN54LS49

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

IOH

High-level output current

VOL

Low-level output voltage

MIN

TYP+

SN74LS49

MAX

2
Vee = MIN,

II =-18mA

Vee = MIN,

VIH = 2 V,

I

TYP+

MAX

0.25

UNIT
V

2

VIL = VIL max, VOH = 5.5 V
Vee = MIN,
IOL = 4 mA
VIH=2V,
VIL=VILmax IIOL=8mA

MIN

V

0.7

0.8

-1.5

-1.5

V

250

250

/lA

0.4

0.25

0.4

0.35

0.5

V

II

Input current at maximum input voltage

Vee = MAX,

VI = 7 V

0.1

0.1

IIH

High-level input current

Vee = MAX,

VI = 2.7 V

20

20

/lA

IlL

Low-level input current

Vee= MAX,

VI = 0.4 V

-0.4

-0.4

mA

ICC

Supply current

Vee= MAX,

See Note 2

15

mA

8

8

15

mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

tpHL

Propagation delay time, high-to-Iow-Ievel output from A input

eL=15pF,

tpLH

Propagation delay time, low-to-high-Ievel output from A input

See Note 6

100

tpHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

eL = 15pF, RL =6 kn,

100

tpLH

Propagation delay time, low-to-high-Ievel output from RB I input

See Note 6

100

RL=2kn,

100

UNIT
ns
ns

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

107

7·34

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5475, SN5477, SN54L75, SN54L77, SN54LS75, SN54LS77,
SN7475, SN74L75, SN74L77,SN74LS75
4-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7611851, MARCH 1974-REVISED OCTOBER 1976

TTL
MSI

SN5475, SN54LS75 ••• J OR W PACKAGE
SN54L75 •.• JPACKAGE
SN7475, SN74L75, SN74LS75 ••. J OR N PACKAGE
(TOP VIEW)

logic
FUNCTION TABLE
(Each Latch)
INPUTS

OUTPUTS

0

a

a
H

G

L

H

L

H

H

H

L

X

L

ao

00

10

20

20

10

10

20

ENABLE
1-2

GNO

30

30

4Q

vee

3D

40

40

H = high level, L = low level, X = irrelevant
= the level of Q before the high-to-Iow transition of G

QO

description
These latches are ideally suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Information present at a data (0) input is transferred to the Q
output when the enable (G) is high and the Q output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the time
the transition occurred) is retained at the Q output
until the enable is permitted to go high.

ENABLE
3-4

logic: see function table
SN5477, SN54LS77 ••. W PACKAGE
SN54L77, SN74L77 •.. T PACKAGE
10

20-

ENABLE
1-2

GNO

NC

30

40

The '75, 'L75, and 'LS75 feature complementary Q
and Q outputs from a 4-bit latch, and are available in
various 16·pin packages. For higher component
density applications, the '77, 'L77, and 'LS77 4-bit
latches are available in 14-pin flat packages.

•

These circuits are completely compatible with all
popular TTL or OTL families. All inputs are diodeclamped to minimize transmission-line effects and
simplify system design. Series 54, 54L, and 54LS
devices are characterized for operation over the full
military temperature range of -55°C to 125°C;
Series 74, 74L, and 74LS devices are characterized
for operation from O°C to 70°C.

10

20

ENABLE
3-4

VCC

30

40

NC

logic: see function table
NC-No internal connection

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '75, 'L75, '77, 'L77
'LS75, 'LS77
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54', SN54L', SN54LS' Circuits
SN74', SN74L', SN74LS' Circuits
Storage temperature range
NOTES:

7V
5.5 V
7V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor and is not applicable to the 'LS75 and 'LS77.

176

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-35

TYPES Sr~5475, SN5477, SN54L75, SN54L77, SN54LS75, SN54LS77,
SN7475, SN74L75, SN74L77, SN74LS75
4-BIT BISTABLE lATCH ESREVISED OCTOBER 1976

functional block diagrams (each latch)
'75, '77, 'L75, 'L77



w
w

r - LOAD CiRCUlT2 --,

CI)

(Same as load circuit 1)
L _________
JI

(SeeNoteC)

TEST CIRCUIT
14-100ns~

I~
~ I I
";10ns

I

~ I ~";10ns

! ~90%
~

ADDRESS
INPUT

1.SV

/

! 14-

~

1'4-";10 ns

10_~%~~
19~% 9~~~1:'- - - - -

___

Wo INPUT

'-..
""""-_ _ _ _ _ _ 0 V

1.SV -{10%

~

tsu .......
";10 ns~

3V

90%;X~

/4-20

-

-- ----- -

ns~

";10

ns~

I

10%}

I

~

•

~tSR

I

' ..

(See Note 0)

 BIIA> B A:B A< B, GNO
INPUT CASCADE INPUTS

OUTPUTS

positive logic: see function tables

positive logic: see function tables

description
These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three
fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These
devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by
connecting comparators in cascade. The A> B, A
B, and A = B outputs of a stage handling less-significant bits are
connected to the corresponding A> B, A
B, and A = B inputs of the next stage handling more-significant bits. The
stage handling the least-significant bits must have a high-level voltage applied to the A = B input and in addition for the
'L85, low-level voltages applied to the A> B and A < B inputs. The cascading paths of the '85, 'LS85, and 'S85 are
implemented with only a two-gate-Ievel delay to reduce overall comparison times for long words. An alternate method
of cascading which further reduces the comparison time is shown in the typical application data.

<

<

•

FUNCTION TABLES
COMPARING

CASCADING

INPUTS

OUTPUTS

INPUTS

A3, B3

A2, B2

Al,Bl

AO, BO

A>B

AB

A B3

X

X

X

X

X

X

H

L

L

A3 < B3

X

X

X

X

X

X

L

H

L

A3 = B3

A2 > B2

X

X

X

X

X

H

L

L

A3= B3

A2 < B2

X

X

X

X

X

L

H

L

A3 = B2

A2= B2

AI> Bl

X

X

X

X

H

L

L

X

X

X

X

L

H

L

L

L

A3= B3

A2= B2

Al < Bl

A3 = B3

A2= B2

Al = Bl

AO> BO

X

X

X

H

A3= B3

A2= B2

Al = Bl

AO < BO

X

X

X

L

H

L

A3= B3

A2= B2

Al = Bl

AO = BO

H

L

L

H

L

L

A3= B3

A2 = B2

Al = Bl

AO= BO

L

H

L

L

H

L

A3= B3

A2 = B2

Al = Bl

AO = BO

L

L

H

L

L

H

X

X

H

H

H

I

'85, 'LS85, 'S85
H

L
H

H

L

'L85
A3 = B3

A2= B2

Al = Bl

AO = BO

L

H

H

L

H

H

A3 = B3

A2= B2

Al = Bl

AO= BO

H

L

H

H

L

H

A3 = B3

A2= B2

Al = 81

AO = BO

H

H

H

H

H

H

A3= B3

A2= B2

Al = Bl

AO = BO

H

H

L

H

H

L

A3= B3

A2= B2

Al = Bl

AO = BO

L

L

L

L

L

L

H = high level, L = low level, X = irrelevant
1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7·57

TYPES SN5485, SN54l85, SN54lS85, SN54S85,
SN7485, SN74l85, SN74lS85, SN74S85
4-81T MAGNITUDE COMPARATORS
functional block diagrams

•
~
!2 :;!

-

E ; - "''''
~ ~

~

 B, A
B:

<

Req = 4 kf!. f'J~~_

INPUT

Any A or B:
Req = 16.7 kf!. NOM
A = B, A > B, A
B:
Req = 40 kf!. NOM

TYPICAL OF ALL OUTPUTS
FOR '85, 'L85

-----4.---Vcc

A = B, Any A or B:
Req = 933 f!. NOM
A> B, A
B:
Req =2.8 kf!. NOM

<

<

TYPICAL OF ALL OUTPUTS
FOR'LS85

TYPICAL OF ALL OUTPUTS
FOR'S85

------.---Vcc

-----~----Vcc

~-~----OUTPUT

OUTPUT

II

OUTPUT

I

'85: Req = 100 f!. NOM
'L85: Req = 500 f!. NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54'
SN74'
SN54L' SN54LS'
SN74L' SN74LS' UNIT
SN54S'
SN74S'
Supply voltage, Vce (see Note 1)
Input voltage (see Note 2)
Interemitter voltage (see Note 3)

NOTES:

7

8

7

7

5.5
5.5

5.5

7

5.5
5.5

Operating free-air temperature range

-55 to 125

Storage temperature range

-65 to 150

8
5.5

o to 70
-65 to 150

7
7

V
V
V
°e
°e

1. Voltage values, except .interemitter voltage, are with respect to network ground terminal.
2. Input voltages for 'L85 must be zero or positive with respect to network ground terminal.
3. This is the voltage between two emitters of a multiple-emitter input transistor. This rating applies to each A input in conjunction
with its respective B input of the '85 and 'S85.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-59

TYPES SN5485, SN7485
4-81T MAGNITUDE COMPARATORS
recommended operating conditions
SN5485
MIN
4.5

Supply voltage, Vee

NOM

SN7485
MAX

MIN

NOM

5.5

4.75

5

5

-400

High·level output current, 10H
Low·level output current, 10L

16

Operating free·air temperature, T A

-55

125

0

MAX

UNIT

5.25

V

-400

/loA

16

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

High-level output voltage

MIN TVP:t MAX UNIT
2

VOL

Low-level output voltage

II

I nput current at maximum input voltage

IIH

High-level input current

IlL

•

TEST eONDITloNst

A

< B, A

> B inputs

all other inputs
A < B, A > B inputs

Low-level input current

all other inputs

Vee = MIN,

II = -12mA

Vee = MIN,

VIH = 2V,

VIL = 0.8 V,

10H = -400 /loA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16 mA

Vee = MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.4 V

Vee = MAX,

2.4

V

Vee = MAX,

Vo = 0

lee

Supply current

Vee = MAX,

See Note 4

V

0.2

V
0.4
1
40
120
-1.6
-4.8

I SN5485
I SN7485

Short·circuit output current§

V

-1.5
3.4

VI = 0.4 V

lOS

0.8

-55

-20

-55

-18
55

88

V
mA
/loA
mA
mA
mA

tFor condition~-shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAli typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at a time.
NOTE 4: I ee is measured with outputs open, A = B grounded, and all other inputs at 4.5 V .

switching characteristics, Vee
PARAMETER~

tpLH

tpHL

=5 V, T A = 25°e

FROM

TO

NUMBER OF

INPUT

OUTPUT

GATE LEVELS
1

7

A < B, A>B

2

12

Any A or B data input

Any A or B data input

TEST CONDITIONS

MIN

TVP MAX

3

17

26

A=B

4

23

35

1

11

A < B, A>B

2

15

3
A=B

4

CL= 15pF,
RL = 400
See Note 5

.n,

20

30

20

30

UNIT

ns

ns

tPLH

A < B or A = B

A>B

1

7

11

ns

tpHL

A < B or A = B

A>B

1

11

17

ns

tpLH

A-B

A-B

2

13

20

ns

tpHL

A=B

A=B

2

11

17

ns

tpLH

A> BorA = B

A B or A = B

A B, or A = B

B, A

<

B, or A = B

A or B inputs
A

Low-level input current

IlL

TYP+

2

High-level input current

IIH

MIN

<

B, A > B, or A = B

A or B inputs

3.3

Vee = MIN,

VIH=2V,

SN54L85

2.4

VIL = 0.7 V,

10H = MAX

SN74L85

2.4

Vee= MIN,

VIH=2V,

SN54L85

0.15

0.3

VIL = 0.7 V,

10L = MAX

SN74L85

0.2

0.4

Vee = MAX,

VI = 5.5 V

VCC = MAX,

VI = 2.4 V

Vce = MAX,

lOS

Short-circuit output current §

Vce = MAX

ICC

Supply current

Vee = MAX,

V
V

3.2

V

100

IJ.A

300
10

IJ.A

30
-0.18

VI = 0.3 V

rnA

-0.54
-3

See Note 6

-15

Condition A

4.0

7.7

Condition B

3.2

7.2

rnA
rnA

tfor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.

§ Not more than one output should be shorted at a time.
NOTE 6: With all outputs open, ICC is measured for Condition A with all inputs at 4.5 V, and for Condition B with all inputs grounded.

switching characteristics, Vee

II

= 5 V, TA = 25°e

I

PARAMETER~

tPLH

FROM

TO

(INPUT)

(OUTPUT)

Any A or B

Any

CL = 50 pF,

tpHL
tpLH
tpHL

~ tpLH

A> B,A

< B,

orA= B

TEST CONDITIONS

See Note 7

Any

RL = 4 kn,

MIN

TYP

MAX

90

150

75

150

75

150

55

100

UNIT

ns
ns

=

propagation delay time, low-to-high-Ievel output
tpH L propagation delay time, high-to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

=

374

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7·61

TYPES SN54LS85, SN74LS85
4-81T MAGNITUDE COMPARATORS
REVISED DECEMBER 1980

recommended operating conditions
SN54lS85
MIN
Supply voltage, Vee

NOM

4.5

MIN

NOM

5.5

4.75

5

5

High-level output current, IOH

SN74lS85

MAX
-400

low-level output current, IOl

MAX

V

-400

IlA

8

mA

70

°e

4

Operating free-air temperature, T A

-55

125

0

UNIT

5.25

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

V Il

low·1 evel input voltage

V IK

I nput clamp voltage

TEST eONDITIONSt

SN74lS85
TYP+ MAX

Vil = Vil max, IOH = -400 IlA

3.4

2.7

0.7

V

-1.5

V
V

3.4

Vee = MIN,
IIOl = 4 mA
0.25
0.4
0.25
0.4
VIH = 2 V,
,t------+-------+---------1
Vil = Vil max IOl = 8 mA
0.35
0.5

A < B, A > B inputs

0.1
Vee = MAX,

VI = 7 V

input current

A < B, A > B inputs
I-a-I-Io-t-he-r~in-p-u-ts-'----1 Vee = MAX,

low·level
input current

l-a~lI:-o-t:-he-r~in-p-u-ts-'----1 Vee = MAX,

A < B, A > B inputs

lOS

Short-circuit output current§

Vee = MAX

lee

Supply current

Vee= MAX,

UNIT

V

-1.5
2.5

V

0.1

t-------------~--------------~

all other inputs

High·level

MIN

2

II = -18mA

Vee= MIN,
Vee= MIN,

at maximum
input voltage

•

MAX
0.7

VOL low-level output voltage
Input current

TYP+

2

VOH High·leveloutputvoltage

II

SN54lS85
MIN

0.3

0.3

20

20

-0.4

-0.4

mA

VI=2.7V

t-------6-0-r------60~ IlA

VI = 0.4 V

I--------------~r_------------~ mA

-1.2

-20
See Note 4

-100
10.4

-1.2

-20

20

-100

mA

10.4

20

mA

TYP

MAX

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C .
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 4: I CC is measured with outputs open, A

= B grounded, and

all other inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

FROM

TO

NUMBER OF

INPUT

OUTPUT

GATE lEVelS

TEST eONDITIONS

tpLH

Any A or B data input

A < B, A > B
A=B

tpHl

Any A or B data input

A < B. A > B

MIN

2

19

3

24

36

4

27

45

1

11

2
3

UNIT

14

1

el = 15 pF,
Rl = 2 kil.

15
20

30

ns

ns

23

45

14

22

1

11

17

ns

A=B

2

13

20

ns

A=B

4

tplH

A < B or A = B

A>B

1

tPHl

A < B or A = B

A>B

tPlH

A=B

See Note 7

ns

tpHl

A-B

A=B

2

13

26

ns

tplH

A> B or A = B

ABorA=B

A B inputs
all other inputs
A < B. A > B inputs
all other inputs

Vce= MIN.

II = -18mA

Vee = MIN.

VIH = 2V.

VIL = 0.8 V.

10H =-1 mA

Vee = MIN.

VIH=2V.

VIL = 0.8 V.

IOL=20mA

Vee - MAX.

VI- 5.5V

Vee= MAX.

VI = 2.7 V

Vee = MAX.

I SN54S85

ISN74S85

MAX UNIT

Supply current

V

2.5

3.4

2.7

3.4

V

-1.2

V
V

1
50
150
-2

VI =0.5 V

-6
-40

See Note 4

Vee = MAX. TA = 125°e.
See Note 4

0.8

0.5

Vee = MAX
Vee = MAX.

lee

TYP:j:

2

High-level output voltage

IlL

MIN

-100
73

ISN54S85W

V
mA
}JA
mA
mA

115
110

mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V. T A = 25° C.
§ Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A = B grounded, and all other inputs at 4.5 V.

switching characteristics, Vee
PARAMETER~

= 5 V, T A = 25° C

FROM

TO

NUMBER OF

INPUT

OUTPUT

GATE LEVELS

TEST CONDITIONS

Any A or B data input

A < B. A> B
A=B

tpHL

Any A or B data input

MAX

2

7.5
10.5

16

4

12

18

1

5.5

3
A=B

4

tpLH

A < BorA = B

A>B

1

tpHL

A < BorA - B

A>B

tpLH

A-B

UNIT

5

3

2

A < B. A> B

TYP

•
I

1
tpLH

MIN

eL=15pF,
RL = 280.n.
See Note 5

7
11

16.5

11

16.5

ns

ns

5

7.5

1

5.5

8.5

ns
ns

A-B

2

7

10.5

ns

tpHL

A-B

A-B

2

5

7.5

ns

tpLH

A> B or A - B

A B or A - B

AB
B3
A3
82
A2
Bl
Al

so
AO
AB
B3
A3
82
A2
Bl
Al
80
AO

B8
AS
B7
A7
B6
A6
B5
AS
B4

•

NC

'85, 'L85,
'LSS5, 'SS5

AB

NC

/

'85, 'L85,
'LS85, 'S85

AB
'85, 'L85,
'LS85, 'S85

A9

B3
A3
82
A2
81
Al

OUTPUTS
A<8
A-B
A>B

so

AO
A<8
A-8
A>B

'85, 'L85,
'LSS5, 'SS5

AB
'85, 'L85,
'LS85, 'S85

A4
B3
A3
B2
A2
Bl
Al
(LSB) BO
AO

AB

B3
A3
B2
A2
Bl
Al

so

AO
AB

AB
'85, 'L85
'LSS5, 'SS5

COMPARISON OF TWO 24·BIT WORDS

37·

7-64

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5486, SN54L86, SN 54LS86, SN54S86,
SN7486, SN74L86, SN74LS86, SN74S86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

TTL
MSI

BULLETIN NO. DL-S 7611825, DECEMBER 1972-REVISED OCTOBER 1976

D

SN54', SN54LS', SN54S' ••• J OR W PACKAGE
SN74', SN74LS', SN74S' ••• J OR N PACKAGE
(TOP VIEW)

schematics of inputs and outputs
'86
TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT
VCC

VCC

4 kn NOM

INPUT

--

OUTPUT

positive logic: Y

=A

 B = AB + As

FUNCTION TABLE
INPUTS

'S86
EQUIVALENT OF
EACH INPUT

TYPICAL OF
ALL OUTPUTS
- - - - . - - - VCC

OUTPUT

--

TYPE
'86
'L86
'LS86
'S86

Y

B

L

L

L

L

H

H

H

L

H
H
H = high level, L

VCC1
2.8
3
kn
- NOM
INPUT

OUTPUT

A

H
L
= low level

TYPICAL AVERAGE
PROPAGATION
DELAY TIME
14 ns
55 ns
10 ns
7 ns

TYPICAL
TOTAL POWER
DISSIPATION
150mW
15mW
30.5 mW
250 mW

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-65

TYPES SN5486, SN7486
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.....
Input voltage . . . . . . . . . . . . .
Operating free·air temperature range: SN5486
SN7486
Storage temperature range

7V
5.5V
_55°C to 125°C
DoC to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN5486
MIN
4.5

Supply voltage, Vee

NOM
5

High-level output current, 10H

SN7486
MAX

MIN

5.5

4.75

NOM
5

-800

Low-level output current, 10L

16

Operating free-air temperature, T A

-55

125

0

UNIT
MAX
5.25

V

-800

/lA

16

rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

SN5486

TEST CONDITIONSt

PARAMETER

MIN

TYP+

SN7486
MAX

2
Vee = MIN,

11=-BrnA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10H

Vee- MIN,

VIH

VOL

Low-level output voltage

II

Input current at maximum input voltage

Vee

IIH

High-level input current

Vee - MAX, VI - 2.4 V

IlL

Low-level input current

Vee

lOS

Short-circuit output current§

Vee - MAX

lee

Supply current

Vee = MAX, See Note 2

VIL

= 0.8 V,
= MAX,
= MAX,

2.4

= -BOO/lA
=2V

TYP+

MAX

0.8

0.8

V

-1.5

-1.5

V

3.4

2.4
0.4

= 5.5V

3.4
0.2

1

VI = 0.4 V
-20

UNIT
V

2

0.2

10L = 16 rnA
VI

MIN

V
0.4
1

V
rnA

40

40

/lA

-1.6

-1.6

rnA

-55

rnA

50

rnA

-55
30

-18

43

30

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25° C.

§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25°e
FROM

TEST CONDITIONS

(INPUT)
A orB

Other input low

tpHL
tpLH

eL=15pF,
RL =400 11,

AorB

Other input high

tpHL

See Note 3

MIN

TYP

MAX UNIT

15

23

11

17

18

30

13

22

ns
ns

~ tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

107f

7-66

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54L86, SN74L86
QUADRUPLE 2~INPUT EXCLUSIVE-OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage (see Note 4)
Operating free-air temperature range: SN54L86
SN74L86
Storage temperature range
NOTES:

7V
5.5 V

-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

1. Voltage values are with respect to network ground terminal.
4. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L86
MIN
Supply voltage, Vee

4.5

NOM
5

High-level output current, IOH

SN74L86
MAX

MIN

5.5

4.75

NOM
5

-100

Low-level output current, 10L

2

Operating free-air temperature, T A

125

-55

0

MAX

UNIT

5.25

V

-200

/lA

3.6

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

low-level output voltage

II

Input current at maximum input voltage

VCC = MAX, VI = 5.5V

IIH

High-level input current

Vce = MAX, VI=2.4V

IlL

Low-level input current

Vee - MAX, VI- 0.3 V

lOS

Short-circuit output current

VCC = MAX

leCH Supply current, all outputs high
leCl Supply current, all outputs low

SN54L86

TEST CONDITIONSt

MIN

TYP:j:

MAX

MIN

2

SN74L86
UNIT
TYP:j: MAX

2

V

0.7
Vec= MIN,

VIH = 2 V,

VIL = 0.7 V,

10H = MAX

VCC= MIN,

VIH = 2 V,

VIL = 0.7 V,

IOL = MAX

2.4

3.3

0.7
2.4

3.2
0.2

V
V

0.4

V

200

200

/lA

20

20

/lA

-0.36

-0.36

rnA

0.15

0.3

-15

rnA

VCC = MAX, See Note 5

2.2

-15
4.4

2.2

4.4

rnA

Vce = MAX, See Note 6

3.8

6.68

3.8

6.68

rnA

-3

-3

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
NOTES: 5. ICCH is measured with all outputs open, one input of each gate at 4.5 V, and the other inputs grounded.
6. ICCL is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25°e
FROM
TEST CONDITIONS

(INPUT)
A or B

Other input low

tpHL
tPLH
tpHL

•

eL=50pF,
RL = 4 kO,

A or B

Other input high

See Note 7

MIN

TYP

MAX UNIT

75

150

60

150

50

90

35

60

ns
ns

~ tpLH '" propagation delay time, low-to·high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE B~X 5012

•

CALLAS. TEXAS 75222

7-67

TYPES SN 54LS86, SN74LS86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54LS86
SN74LS86
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS86
MIN
4.5

Supply voltage, Vee

NOM

SN74LS86

MAX

MIN

5.5

4.75

5

NOM
5

-400

High-level output current, 10H

MAX

V

-400

/lA

8

mA

70

°e

4

Low-level output current, 10L

125

-5G

Operating free-air temperature, T A

UNIT

5.25

0

_L.OM

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

MIN

TYP+

SN74LS86

MAX

High-level output voltage

Vee - MIN,

11- -18mA

Vee= MIN,

VIH = 2V,

VIL = VIL max, 10H = -400 /lA

VOL Low-level output voltage

2.5

10L = 4 mA

MIN

TYP+

V
0.8

V

-1.5

-1.5

V

3.4
0.25

UNIT

0.7

2.7
0.4

V

3.4
0.25

0.4

0.35

0.5

VIH = 2 V,
VIL =VILmax

MAX

2

2

Vee = MIN,

•

SN54LS86

TEST CONOlTlONSt

PARAMETER

V
10L = 8 mA

mA

II

Input current at maximum input voltage

Vee = MAX,

VI =7 V

0.2

0.2

IIH

High-level input current

Vee - MAX,

VI - 2.7 V

40

40

/lA

IlL

Low-level input current

Vee = MAX,

VI=O.4V

Short-circuit output currentS

Vee - MAX

-0.8
-42

mA

lOS

-0.8
-40

lee

Supply current

Vee = MAX,

10

mA

-6
See Note 2

6.1

-5

10

6.1

mA

t For conditions shown as MIN or MAX, use the appropriate val ue specified under recommended operating conditions for the applicable type.
+AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25°e
FROM

A orB

Other input low

tpHL
tpLH

TEST CONDITIONS

(INPUT)

eL=15pF,
RL = 2 k!1,

A or B

Other input high

tpHL

See Note 7

MIN

TYP

MAX

12

23

10

17

20
13

30

UNIT
ns
ns

22

~ tpLH "" propagation delay time, low-to·high-Ievel output
tpH L "" propagation delay time, high-to-Iow-Ievel output
NOTE 7: Load circuit and voltllge waveforms are shown on page 3-11,

128

7·68

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54S86, SN74S86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.....
Input voltage . . . . . . . . . . . . .
Operating free·air temperature range: SN54S86
SN74S86
Storage temperature range

7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S86
MIN
Supply voltage, Vee

4.5

NOM
5

High-level output current, IOH

SN74S86
MAX

MIN

5.5

4.75

NOM

MAX

5

-1

Low-level output current, IOL

20

Operating free-air temperature, T A

-55

125

0

UNIT

5.25

V

-1

mA

20

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

VOH
VOL

SN54S86

TEST CONDITIONSt

MIN

TYP:t:

SN74S86
MAX

High·level output voltage
Low·level output voltage

11=-18mA

Vee- MIN,

VIH - 2 V,

VIL = 0.8 V,

IOH = -1 mA

Vee- MIN,

VIH - 2 V

VIL = 0.8 V,

101. =20 mA

2.5

TYP:f

MAX

2

2
Vee= MIN,

MIN

UNIT
V

0.8

0.8

V

-1.2

-1.2

V

3.4

2.7

3.4

0.5

V
0.5

V

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5 V

1

1

IIH

High·level input current

Vee = MAX,

VI = 2.7 V

50

50

p.A

IlL

Low·level input current

Vee - MAX,

VI - 0.5 V

-2

-2

mA

lOS

Short-circuit output current!l

Vee= MAX

-100

mA

lee

Supply current

Vee = MAX, See Note 2

75

mA

-100

-40
50

-40

75

50

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at VCC = 5 V. T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

•
I

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

tpLH

FROM

TEST CONDITIONS

(INPUT)
A orB

tpHL
tpLH

A orB

tpHL

Other input low

eL=15pF,

Other input high

RL = 280.11,
See Note 3

MIN

TYP

MAX UNIT

7

10.5

6.5

10

7

10.5

6.5

10

ns
ns

=
=

~tpLH propagation delay time, low-to-high-Ievel output
tpH L
propagation delay time, h igh-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-69

TTL
MSI

TYPES SN54H87, SN74H87
4-81T TRUE/COMPLEMENT, ZERO/ONE ELEMENTS
BULLETIN NO. DL-S 7211837, DECEMBER 1972

SN54H87 •• '. J OR W PACKAGE
SN74H87 ••• J OR N PACKAGE
(TOP VIEW)

description
A4

Y4

NC

A3

Y3

A1

Y1

NC

A2

Y2

Operation of these monolithic 4-bit true/complement
elements is controlled by the Band C inputs. With
the B input low, the 4-bit binary input (A) is
transferred to the output (V) in either complementary form (with C low) or true form (with C high).
When the B input is high, the output will be at the
complementary level of the C input regardless of the
levels of the data inputs.
These circuits are fully compatible for use with other
TTL or DTL circuits. Input clamping diodes are
provided to minimize transmission line effects and
thereby simplify system design. Each input represents
only one normalized series 54H/74H load, and full
fan-out to 10 series 54H/74H loads is available from
each of the outputs in the low-level condition.

GND

positive logic: see function table
NC-No internal connection
FUNCTION TABLE

Power dissipation is 270 mW typically with an
average propagation delay of 14 ns from data inputs
to output.

•

The SN54H87 is characterized for operation over the
full military temperature range of -55°C to 125°C,
and the SN74H87 is characterized for operation from
O°C to 70°C.

CONTROL

OUTPUTS

INPUTS
B

C

Vl

V2

V3

V4

L

L

A1

A2 A3

ALi

L

H

Al

A2

A3

A4

H

L

H

H

H

H

H

H

L

L

L

L

H = high level, L = low level
A1, A2, A3, A4 = the level of the respective A input .

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
........ .
Input voltage . . . . . . . . . . . . . . . . .
Operating free·air temperature range: SN54H87 Circuits
SN74H87 Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74H87

SN54H87
MIN
4.5

Supply VOltage, Vee

NOM
5

MAX

MIN

NOM

5.5

4.75

5

-1

High-level output current, IOH

20

Low-level output current, IOL
-55

Operating free-air temperature, T A

125

0

MAX

UNIT

5.25

V

-1

mA

20

mA

70

°e

1076

7·70

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54H87, SN74H87
4-81T TRUE/COMPLEMENT, ZERO/ONE ELEMENTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONOITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

VIL = 0.8 V,

10L = 20mA

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5V

MIN

TYP+

MAX UNIT

2

V
0.8

Vee= MIN,

II =-8mA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10H = -1 mA

VCC= MIN,

VIH = 2 V,

-1.5
3.5

2.4

0.2

V
V
V

0.4
1

V
mA

IIH

High-level input current

Vee= MAX,

VI = 2.4 V

50

JJA

IlL

Low-level input current

Vee - MAX,

VI- 0.4 V

-2

mA

lOS

Short-circuit output currentS

Vee = MAX

-100

mA

ICC

Supply current

Vee= MAX,
See Note 2

-40

I SN54H87
1SN74H87

54

78

54

89

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed 1 second.
NOTE 2: ICC is measured for the following conditions:
a. All A inputs are at 4.5 V, Band C inputs are grounded, and all outputs are open.
b. Band C inputs are at 4.5 V, all A inputs are grounded, and all outputs are open.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

MIN

Propagation delay time, low-to-hightPLH

level output from any A input
Propagation delay time, high-to-Iow-

tpHL
tpLH

level output from any A input

eL = 25 pF,

Propagation delay time, low-to-high-

See Note 3

MAX

14

20

ns

13

19

ns

17

25

ns

17

25

ns

MAX

RL=280n,

level output from B or e inputs
Propagation delay time, high-to-Iow-

tpHL

TYP

level output from B or e inputs

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

functional block diagram and schematics of inputs and outputs

•
I

TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

L-~~_

OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

7-71

TYPES SN5490A, SN5492A, SN5493A, SN54L90,SN54L93,
SN54LS90, SN54LS92, SN54LS93, SN7490A, SN7492A, SN7493A~
SN74L90, SN74L93, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS

TTL
MSI

BULLETIN NO. DL-S 7611807, MARCH 1974-REVISED OCTOBER 1976

SN54', SN54LS' ..• J OR W PACKAGE
SN54L' ••• J OR T PACKAGE
SN54', SN74L', SN74LS' ••• J OR N PACKAGE

'90A, 'L90, 'LS90 ... DECADE COUNTERS
'92A, 'LS92 ... DIVIDE-BY-TWELVE
COUNTERS

'9(':A: 'L90, 'LS90

(rop VIEW)

'93A, 'L93, 'LS93 ... 4-BIT BINARY
COUNTERS
TYPES
'90A

TYPICAL
POWER DISSIPATION
145mW

'L90

20mW

'LS90

45mW

'92A, '93A

130mW

'LS92, 'LS93

45mW

'L93

16mW

'92A, , LS92, (TOP VIEW)

description
Each of these monolithic counters contains four
master·slave flip-flops and additional gating to
provide a divide-by-two counter and a three-stage
binary counter for which the count cycle length is
divide-by-five for the '90A, 'L90, and 'LS90,
divide-by-six for the '92A
and 'LS92, and
divide-by-eight for the '93A, 'L93, and 'LS93.
All of these counters have a gated zero reset and the
'90A, 'L90, and 'LS90 also have gated set-to-nine
inputs for use in BCD nine's complement
applications .

•

'93A, 'LS93 (TOP VIEW)

To use their maximum count length (decade, divideby·twelve, or four-bit binary) of these counters, the B
input is connected to the GA output. The input
count pulses are applied to input A and the outputs
are as described in the appropriate function table. A
symmetrical divide-by-ten count can be obtained
from the '90A, 'L90, or 'LS90 counters by
connecting the GD output to the A input and
applying the input count to the B input which gives a
divide-by-ten square wave at output GA.

'L93 (TOP VIEW)

positive logic: see function tables
NC-No internal connection

1076

7·72

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5490A, '92A, '93A, SN54L90, 'L93, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74L90, 'L93, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
'90A, 'L90, 'LS90

'90A, 'L90, 'LS90

BCD COUNT SEQUENCE
(See Note A)

BI-QUINARY (5-2)
(See Note B)

OUTPUT

COUNT

COUNT

Qo QC QB QA

'92A, 'LS92

'93A, 'L93, 'LS93
COUNT SEQUENCE

COUNT SEQUENCE

OUTPUT

ISee Note C)

ISee Note C)

QA Qo QC QB

0

L

L

L

L

0

L

L

L

L

1

L

L

L

H

1

L

L

L

H

2

L

L

H

L

2

L

L

H

L

3

L

L

H

H

3

L

L

H

4

L

H

L

L

4

L

H

L

OUTPUT

COUNT

OUTPUT

COUNT

QB

QA

0

L

L

L

L

0

1

L

L

L

H

1

L

L

L

H

2

L

L

H

L

2

L

L

H

L

L

3

L

L

H

H

3

L

L

H

H

Qo QC

Qo QC °B
L
L
L

QA
L
H

5

L

H

L

H

5

H

L

L

L

4

L

H

L

L

4

L

H

L

L

6

L

H

H

L

6

H

L

L

H

5

L

H

L

H

5

L

H

L

H

H

H

6
7

H

L

L

L

6

L

H

H

L

H

L

L

H

7

L

H

H

H

7

L

H

7

H

L

H

L

8

H

L

L

L

8

H

L

H

H

9

H

L

L

H

9

H

H

L

L

'90A, 'L90, 'LS90
RESET/COUNT FUNCTION TABLE

NOTES: A_
B_

C.
D_

H

L

H

L

8

H

L

L

L

H

L

H

H

9

H

L

L

H

10

H

H

L

L

10

H

L

H

L

11

H

H

L

H

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

14

H

H

H

L

15

H

H

H

H

OUTPUT

RESET INPUTS
R911l
L

8

9

R9121 Qo QC QB QA
L
L
L
L
X

ROIl)
H

RO(21
H

H

H

X

L

L

L

L

L

X

X

H

H

H

L

L

H

X

L

X

L

COUNT

L

X

L

X

COUNT

L

X

X

L

COUNT

X

L

L

X

COUNT

'92A, 'LS92, '93A, 'L93, 'LS93
RESET/COUNT FUNCTION TABLE

ROil)

R O(2)

Qo

QC

QB

QA

H

H

L

L

L

L

L

X

COUNT

X

L

COUNT

Output QA is connected to input B for BCD count_
Output QD is connected to input A for bi-quinary

count.
Output QA is connected to input B.
H

=

high level, L = low level, X

=

OUTPUT

RESET INPUTS

irrelevant

functional block diagrams
'90A, 'L90, 'LS90

'92A, 'LS92

'93A, 'L93, 'LS93

(,93A) ['L93)

INPUT A ~1_14~)~[1_4),--_--<:>p

•
I

INPUT B ...cl1'-'-)->..:[S"-)_ _--t--

RO(l) (2))1)
RO(2) (3)[2)

The J and K inputs shown without connection are for reference only and are functionally at a high level.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-73

TYPES Sr~5490A, '92A, '93A, SN54L90, 'L93, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74L90, 'L93, SN74LS90, 'LS92, 'LS93
DECADE,
DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED AUGUST 1977
schematics of inputs and outputs
'90A, '92A, '93A
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

V C CReq
3-INPUT

--

INPUT
A
B ('90A, '92A)
B ('93A)
All resets

Req NOM
2.5 k!l
1.25 k!l
2.5 k!l
6kU

'L90, 'L93
EQUIVALENT OF EACH INPUT
EXCEPT A AND B OF 'L93

VCC~-Req

VCC--50-k-U~-----'-3-5-k-!l---NOM

INPUT

•

INPUT
A ('L90)
B ('L90)
All resets

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF A AND B
INPUTS OF 'L93

NOM

--

Req NOM
13.3 kU
6.67 kU
40 kU

'LS90, 'LS92, 'LS93
EQUIVALENT OF EACH RESET INPUT

EQUIVALENT OF A AND B INPUTS

vctS

VCC---.__-

R1 R2 R3

20 k!l NOM
IN P UT

--..::IiI-"---'-

TYPICAL OF ALL OUTPUTS

INPUT

-

NOMINAL VALUES
R1
R2
R3
10kU 10kU
10kU
A
5 kU
B ('LS90, 'LS92) 6.7 kU 6.7 kU
B ('LS93)
15 kU
15 kU 10 kU
INPUT

87

7·74

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5490A, SN5492A, SN5493A, SN7490A, SN7492A, SN7493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN5490A, SN5492A, SN5493A
SN7490A, SN7492A, SN7493A
Storage temperature range
NOTES:

7V

5.5 V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two RO
inputs, and for the 'gOA circuit, it also applies between the two Rg inputs.

recommended operating conditions
SN5490A, SN5492A SN7490A, SN7492A
SN7493A

SN5493A
MIN
Supply voltage, Vee

4.5

NOM
5

MAX

MIN

5.5

4.75

NOM
5

-800

High-level output current, 10H

16

Low-level output current, 10L
A input

Count frequency, fcount (see Figure 11

Pulse width, tw

0

32
16

16
0

16

0
15

15

B input

30

30

Reset inputs

15

15

25
-55

V
JolA

32

B input

Operating free-air temperature, T A

5.25
-800

0

A input

Reset inactive-state setup time, tsu

UNIT
MAX

ns

25
125

mA
MHz

ns

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL
V IK

Low-level input voltage
Input clamp voltage

VOH High-level output voltage
VOL Low-level output voltage
Input current at
II

maximum input voltage

A input

input current
Low-level

IlL

ICC

TYP:!:

VCC= MIN,

II = -12 mA

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V, 10H = -800 JolA
Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16 mAlI

2.4

0.2

Vee = MAX, VI = 2.4 V

Vee = MAX, VI = 0.4 V

Supply current

Vee= MAX

I SN54'
I SN74'

MAX

MIN

TYP+

MAX

2

V
0.8

V

-1.5

-1.5

-1.5

V

2.4

0_2

0.4

2.4

3.4

3.4
0.2

0.4

0.4

1

1

40

40

40

80

80

80

120

120

80

-1.6

-1.6

-1.6

-3.2

-3.2

-3.2

-4.8

-4.8

-3.2

-57

-20

-57

-20

-57

-18

-57

-18

-57

-18

-57

29

42

26

39

26

a

V

-20

Vee = MAX, See Note 3

UNIT

0.8

1

Vee = MAX, VI = 5.5 V

B input

output current §

TYP:!:

0.8

3.4

,Any reset
A input

MIN
2

B input

input current

'93A

'92A
MAX

2

Short-circuit
lOS

'90A
MIN

Any reset

High-level
IIH

TEST CONDITIONSt

39

I

V
mA

JolA

mA

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time.
11 QA outputs are tested at IOL = 16 mA plus the limit value for II L for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-75

TYPES SN5490A, SN5492A, SN5493A, SN7490A, SN7492A, SN7493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

switching characteristics, Vee
PARAMETER~

f max
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tpLH
tpHL
tpHL
tpLH
tpHL

= 5 V, T A = 25°e

FROM

TO

(INPUT)

(OUTPUT)

A

QA

32

B

QS

16

A
A
B

QA
QD
CL=15pF,

. QB

B

QC

B

QD

Set-ta-O
Set-ta-9

TEST CONDITIONS

MIN

'gOA

'92A

'93A

TYP MAX MIN

TYP MAX MIN

TYP MAX

42

32

42

32

16
10

16

12

42

MHz

16
10

16

18

12

UNIT

10

16

18

12

18
70

32

48

32

48

46

34

50

34

50

46

70

10

16

10

16

10

16

RL=400n,

14

21

14

21

14

21

See Figure 1

21

32

10

16

21

32

23

35

14

21

23

35
51

21

32

21

32

34

23

35

23

35

34

51

Any

26

40

26

40

26

40

QA,QD

20

30

Q8,QC

26

40

ns
ns
ns
ns
ns
ns
ns

~fmax

== maximum count frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

•

1071

7-76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54L90, SN54L93, SN74L90, SN74L93
DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4) . . . . . . . . .
Input voltage (see Note 5)
. . . . . . . . .
Operating free-air temperature range: SN54L90, SN54L93
SN74L90, SN74L93
Storage temperature range

8V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTES: 4. Voltage values are with respect to network ground terminal.
5. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L90, SN54L93
MIN
Supply voltage, Vee

4.5

eount frequency, fcount

NOM
5

0

SN74L90, SN74L93

MAX

MIN

5.5

4.75

3

0

NOM
5

MAX
5.25
3

UNIT
V
MHz

High-level output current, 10H

-100

-200

J.l.A

Low-level output current, 10L

2

3.6

mA

Width of input count pulse, tw(count)

200

200

Width of reset pulse, tw(reset)

200

200

Operating free-air temperature, T A

-55

125

ns
ns

0

70

°e

-

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

maximum input voltage
High-level input

IIH

current

TVPt

current

'L93
MAX

MIN

TVPt

SN54L'
ISN74L'

Vee= MIN,

SN54L'

SN74L'

I---

VIH = 2 V,

2.4

VIL = 0.7 V,

10H = MAX

2.4

Vee= MIN,

VIH=2V,

VIL = 0.7 V,

10L =

MAX~

0.15

0.2

0.4

0.2

100

Any reset input
Vee = MAX, VI = 2.4 V

Any reset input
Vee = MAX, VI = 0,3 V

B input
Vee = MAX

Ice

Supply current

Vee= MAX,

See Note 3

4

0.4

300

200

600

200

10

10

30

20

60

20

-0.18

-0.18

-0.54

-0.36

-15

-3

0.3

V

100

-1.08

lOS

Short-circuit output current§

V
V

3.2

0.3

Vee = MAX, VI = 5.5V

A input

3.3

0.15

B input
A input

2.4

3.2

UNIT
V

0.7
2.4

3.3

Any reset input
A input

MAX

2
0.7

B input

Low-level input
IlL

'L90
MIN
2

Low-level output voltage
I nput current at

II

TEST eONDITIONSt

J.l.A

J.l.A

•

I

mA

-0.36
-3

7.2

3.2

-15

mA

6.6

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V. T A = 25° C.
§Not more than one output should be shorted at a time.
~QA outputs are tested at IOL = MAX plus the limit value for IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee

= 5 V, TA = 25°e
'L90

TEST CONDITIONS

PARAMETER

MIN
f max

3

Maximum count frequency
Propagation delay time, low-to-high-Ievel QD

tpLH
tpHL

output from input A

eL=50pF,

Propagation delay time, high-to-Iow-Ievel QD

See Figure 1

RL=4kn,

output from input A

TVP

'L93
MAX

MIN
3

6

TYP

UNIT
MAX

6

MHz

230

340

280

450

ns

230

340

280

450

ns

'4

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-77

TYPES SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 4)
Input voltage: R inputs
A and B inputs
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range

7V
7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 4: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS90

SN74LS90

SN54LS92

SN74LS92

SN54LS93
MIN
Supply voltage, Vee

4.5

NOM
5

High-level output current, 10H

MIN

5.5

4.75

NOM

Low-level output current, 10L

MAX

5

-400

5.25
.-400

4
A input

Count frequency, fcount (see Figure 11

Pulse width, tw

0

32
16

S
0

32

0

16

B input

0

A input

15

15

B input

30

30

Reset inputs

15

15

Reset inactive-state setup time, tsu

25

Operating free-air temperature, T A

-55

UNIT

SN74LS93

MAX

mA
MHz

ns

25
125

V
IlA

ns

0

70

"e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST eONDITIONSt
MIN

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH High-level output voltage
VOL Low-level output volt3ge

II

Input current

Any reset

at maximum

A input

input voltage

B input

High-level
IIH

input current
Low-level

IlL

input current

SN54LS90

SN74LS90

SN54LS92

SN74LS92

TYP:j:

2

Vee = MIN,

11=-lSmA

Vec = MIN,

VIH = 2 V,

VIL = VILmax,

10H = -4001lA

Vee = MIN,

VIH=2V,

2.5
IIOL =4 mA~

Vee = MAX,

VI = 7 V

Vee= MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.7 V

0.25

Any reset
Vee = MAX,

VI = 0.4 V

B input

lOS

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee = MAX,

-20
See Note 3

UNIT

MAX
V
O.S

V

-1.5

-1.5

V

2.7
0.4

IIOL = S mA~

VIL = VIL max,

TYP:j:

0.7

3.4

B input
A input

MIN
2

Any reset
A input

MAX

V

3.4
0.25

0.4

0.35

0.5

0.1

0.1

0.2

0.2

0.4
20

0.4

40

40

SO

SO

-0.4

-0.4
-2.4

-3.2

-3.2
-20

-100

I 'LS90

9

15

9

15

I

9

15

9

15

'LS92

mA

20

-2.4
-100

V

IlA

mA
mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

~ QA outputs are tested at specified 10 L plus the limit value of II L for the B input. This permits driving the B input while maintaining full fanout capability.
NOTE 3:

ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
9r ounded.
8~

7-78

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS90. SN54LS92. SN54LS93,
SN74LS90. SN74LS92. SN74LS93
DECADE. DIVIDE-BY-TWELVE. AND BINARY
COUNTERS
REVISED OCTOBER 1976
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vil

Low-level input voltage

VIK

Input clamp voltage

II = -18 mA

Vee= MIN,

VIH = 2 V,

2.5

VIL = VIL max, 10H = -400jJA
VIH = 2 V,

SN74lS93

MAX

MIN

llOL = 4 mA~

TYP;

MAX

2
0.8

-1.5

-1.5

3.4

2.7

0.25

3.4

0.4

V
V
V

0.25

0.4

0.35

0.5

Any reset

Vee= MAX,

VI = 7 V

0.1

0.1

A or B input

Vee = MAX,

VI=5.5V

0.2

0.2

Vee = MAX,

VI = 2.7 V

V

mA

High-level

Any reset
A or B input

input current

UNIT
V

0.7

IIOL=8mA~

VIL = VIL max

input current
Low-level

IlL

TYP;

at maximum
input voltage

IIH

Vee= MIN,

Vee= MIN,

VOL Low-level output voltage

II

MIN
2

VOH High-level output voltage

Input current

SN54lS93

TEST CONOITIONSt

Any reset
A input

Vee= MAX,

VI=O.4V

B input

lOS

Short-circuit output current§ Vee = MAX

lee

Supply current

Vee= MAX,

-20

20

20

40

80

-0.4

-0.4

-2.4

-2.4

-1.6

-1.6
-20

-100
9

See Note 3

9

15

jJA

mA

-100

mA

15

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
;AII typical values are at V CC = 5 V, T A = 25° C.

§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
~ 0A outputs are tested at specified IOL plus the limit value for II L for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to.4.5 V, and all other inputs
grounded.

switching characteristics,
PARAMETER~
f max

tpLH

TO

(INPUT)

(OUTPUT)

A

aA

32

B

aB

16

A

tPHL
tPLH

A

tPHL
tpLH

tPLH

tPLH
tPHL

aD

B

aC

B

tpHL
tPHL

aA

aB

tpHL

Set-to·O
5et-to-9

TEST CONDITIONS

'lS90
MIN

'lS93

'lS92

TYP MAX MIN
42

32

TYP MAX MIN
42

32

16
10

B

tPHL
tpLH

Vee = 5 V, T A = 25° e

FROM

16

TYP MAX
42

MHz

16
10

16

10

16

12

18

12

18

12

18

32

48

32

48

46

70
70

34

50

34

50

46

CL=15pF,

10

16

10

16

10

16

RL = 2 kn

14

21

14

21

14

21

See Figure 1

21

32

10

16

21

32

23

35

14

21

23

35

21

32

21

32

34

51

23

35

23

35

34

51

26

40

26

40

aD
Any

26

40

aA,QO

20

30

QB,QC

26

40

UNIT

ns
ns

•

ns
ns
ns
ns
ns

~ f max ;; maximum count frequency
tpLH;; propagation delay time, low-to-high-Ievel output
tpH L ;; propagation delay time, h igh-to-Iow-Ievel output

377

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-79

TYPES SN5490A, SN5492A, SN5493A, SN54L90, SN54L93,
SN54LS90, SN54LS92, SN54LS93, SN7490A, SN7492A, SN7493A,
SN74L90, SN74L93, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION

TEST
POINT

FROM OUTPUT
UNDER TEST

elI
-=

(See Note B)

LOAD CIRCUIT

=

•
VOLTAGE WAVEFORMS

NOTES:

A. Input pulses are supplied by a generator having the following characteristics:
for '90A, '92A, '93A, tr";;; 5 ns, tf";;; 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout '" 50 ohms;
for 'L90, 'L93, tr";;; 15 ns, tf";;; 15 ns, PRR = 500 kHz, dutY cycle = 50%, Zout '" 50 ohms;
for 'LS90, 'lS92, 'LS93, tr";;; 15 ns, tf";;; 5 ns, PRR = 1 MHz, dutY cycle = 50%, Zout '" 50 ohms.
B. CL includes probe and jig capacitance.
C. C1 (30 pF) is applicable for testing 'L90 and 'L93.
D. All diodes are 1N916 or 1N3064.
E. Each reset input is tested separately with the other reset at 4.5 V.
F. Reference waveforms are shown with dashed lines.
G. For '90A, '92A, and '93A; Vref = 1.5 V. For 'l90, 'L93, 'LS90, 'LS92, and 'LS93; Vref = 1.3 V.

FIGURE 1

7-80

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

107

TTL
MSI

TYPES SN5491A, SN54L91, SN54LS91, SN7491A, SN74L91, SN74LS91
8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 7611854, MARCH 1974-REVISEDOCTOBER 1976

M

for applications in
•

Digital Computer Systems

•

Data-Handling Systems

SN5491A, SN54LS91 •.• W PACKAGE
SN54L91, SN74L91 ••• T PACKAGE
FLAT PACKAGE (TOP VIEW)

SN5491A, SN54LS91 " • J PACKAGE
SN54L91, SN7491A, SN74L91, SN74LS91 , •• J OR N PACKAGE
DUAL-IN-LINE PACKAGE (TOP VIEW)

FUNCTION TABLE
INPUTS
ATtn

INPUT

INPUT

A

B

Control Systems

•

OUTPUTS
AT tn+8

A

B

QH

H

H

H

L

X

H

X

L

H

OH
L

H = high, L = low,
X = irrelevant

tn = Reference bit time,
t n +8

clock low
= Bit time after 8
low-to-high
clock transitions.

Vee

positive logic: see function table
NC-No internal connection

TYPICAL
TYPE

MAXIMUM
CLOCK
FREQUENCY

schematics of inputs and outputs

TYPICAL

'91A, 'L91

POWER

'LS91

EQUIVALENT OF EACH INPUT

EQUIVALENT OF EACH INPUT

DISSIPATION

'91A

18 MHz

175mW

'L91

6.5 MHz

17.5mW

'LS91

18MHz

60mW

vcc~-Req

INPUT

__

vee5--

17 kn NOM
INPUT

description
These monolithic serial-in, serial-out, 8·bit shift registers utilize transistor-transistor logic (TTL) circuits
and are composed of eight R-S master-slave flip-flops,
input gating, and a clock driver. Single·rail data and
input control are gated through inputs A and Band
an internal inverter to form the complementary
inputs to the first bit of the shift register. Drive for
the internal common clock line is provided by an
inverting clock driver. This clock pulse inverter/driver
causes these circuits to shift information one bit on
the positive edge of an input clock pulse.

--

'91A:R eq = 4 kn NOM
'L91: Req = 40 kn NOM

'91A, 'L91

'LS91

Vee

TYPICAL OF BOTH OUTPUTS

vee

TYPICAL OF BOTH OUTPUTS

•
I

OUTPUT

functional block diagram

n

'91A:

R = 130

'L91:

R = 500 n NOM

NOM

(OUAL·IN·LINE) [FLAT PACKAGE I
A

(12) (10)

Q

(13) (13) QH

a

(14) (141 OH

(11) (12)

CK

CLOCK

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE B~X 5012

•

DALLAS, TEXAS 75222

7-81

TYPES SN5491A, SN7491A
8-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage (see Note 2)
Operating free-air temperature range: SN5491A
SN7491A
Storage temperature range
NOTES:

7V

5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. Input signals must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN5491A
MIN
Supply voltage, Vee

NOM

4.5

5

High-level output current, 10H

SN7491A
MAX

MIN

5.5

4.75

NOM

-400

Low-level output current, 10L

MAX

5

UNIT

5.25

V

-400

Il A
mA

16

16

Width of clock input pulse, tw

25

25

ns

Setup time, tsu (see Figure 1)

25

25

ns

0

0

Hold time, th (see Figure 1)
Operating free-air temperature, T A

-55

125

ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

Low-level output voltage

SN5491A

TEST CONDITIONSt

MIN

NOM

SN7491A
MAX

2

MIN

NOM

VIL

VIH =2 V,

= 0.8 V,

10H

= -4001lA

Vee= MIN,

VIH=2V,
10L = 16mA

2.4

3.5
0.2

2.4
0.4

UNIT
V

0.8

0.8
Vee= MIN,

MAX

2

3.5
0.2

V
V

0.4

V

II

Input current at maximum input voltage

= 0.8 V,
Vee = MAX,

VI = 5.5 V

1

1

IIH

High-level input current

Vee - MAX,

VI - 2.4 V

40

40

IlA

IlL

Low·level input current

Vee = MAX,

VI = 0.4 V

-1.6

-1.6

mA

los

Short-circuit output currentS

Vce - MAX

-57

mA

lee

Supply current

Vee - MAX,

58

mA

VIL

-20
See Note 3

-57
35

-18

50

35

mA

tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°e.
§ Not more than one output should be shorted at a time.
NOTE 3: lec is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

MIN

TYP

f max

Maximum clock frequency

eL = 15 pF,

10

18

tpLH

Propagation delay time, low-to-high-Ievel output

RL

tpHL Propagation delay time, high-to-Iow-Ievel output

MAX

UNIT
MHz

= 400 n,

24

40

ns

See Figure 1

27

40

ns

1071

1·82

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54L91, SN74L91
8-BIT SH 1FT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage (see Note 2)
Operating free-air temperature range: SN54L91
SN74L91
Storage temperature range
NOTES:

8V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
Input signals must be zero or positive with respect to network ground terminal.

~-

recommended operating conditions
SN74L91

SN54L91
MIN
Supply voltage, Vee

4.5

NOM
5

High-level output current, 10H

MAX

MIN

5.5
-100

4.75

Low-level output current, 10L

(~ee

MAX

5

2

I High logic level

Width of clock input pulse, tw(clockl
Setup time, tsu

NOM

I Low logic level

Figure 1 I

Hold time, th (see Figure 1)
Operating free-air temperature, T A

UNIT

5.25
-200

V
p.A

3_6

mA

100

100

ns

150

150

ns

120

120

ns

0
-55

0
0

125

70

ns
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

SN54L91

TEST CONDITIONSt

MIN

TYP+

SN74L91
MAX

2

MIN

TYP+ MAX

0.7
Vee- MIN,

VIH-2V,

VIL; 0.7 V,

10H; MAX

Vee- MIN,

VOL

Low-level output voltage

VIL; 0.7 V,

VIH - 2 V
10L; MAX

II

Input current at maximum input voltage

Vee - MAX,

VI- 5.5 V

IIH

High-level input current

Vee - MAX,

VI; 2.4 V

IlL

Low-level input current

Vee - MAX,

VI - 0.3 V

lOS

Short-circuit output current

Vee - MAX

lee

Supply current

Vee - MAX,

2.4

0.7
2.4

3.3
0.3

V
V

3.2
0.4

V

p.A

10

100
10

p.A

-0.18

-0.18

mA

-15

mA

6.6

mA

0.15

0.2

100

-15

-3
See Note 3

UNIT
V

2

3.5

-3

6.6

3.5

•

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee; 5 V, TA; 25°e.
NOTE 3: lee is measured after the eighth clock pulse with the outputs open and A and B inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

~ Maximum clock frequency
tpLH
tpHL

MIN
3

Propagation delay time,

eL; 50pF,
See Figure 1

low-to-high-Ievel output
Propagation delay time,

RL;4 kil,

high-to-Iow-Ievel output

TYP

MAX UNIT

6.5

MHz

55

100

ns

100

150

ns

)76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-83

TYPES SN54LS91, SN74LS91
8-BIT SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free·air temperature range: SN54LS91
SN74LS91
Storage temperature range
NOTES:

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS91
MIN
Supply voltage, Vee

NOM

4.5

MIN

5.5

4.75

5

High-level output current, 10H

SN74LS91

MAX

NOM
5

-400

Low-level output current, 10L

MAX

UNIT

5.25

V

-400

/lA

8

mA

4

Width of clock input pulse, tw

25

25

ns

Setup time, tsu (see Figure 1)

25

25

ns

0

0

Hold time, th (see Figure 1)
Operating free-air temperature, T A

-55

ns

0

125

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS91

SN54LS91
TEST eONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK I nput clamp voltage
VOH High-level output voltage
VOL Low-level output voltage

•

Input current at
II

maximum input voltage

MIN

TYP:!: MAX

MIN

2
Vee= MIN,

11=-18mA

Vee = MIN,

VIH = 2 V,

2.5

VIL = VIL max, 10H = -400 /lA
Vee = MIN,

VIH = 2 V,

VIL = VIL max

0.7

0.8

V

-1.5

-1.5

V

3.5

2.7
0.4

VI = 7V

V

3.5
0.25
0.35

\IOL = 8 mA

Vee = MAX,

UNIT
V

2

0.25

\IOL = 4 mA

TYP:!: MAX

0.4
0.5
0.1

0.1

V
mA

IIH

High-level input current

Vee = MAX,

VI =2.7V

20

20

/lA

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

-100

mA

lee

Supply current

Vee = MAX,

20

mA

-100 -20

-20
See Note 3

12

20

12

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and du ration of the short*circuit should not exceed one second.

NOTE 3: ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee:: 5 V, TA :: 25°e
PARAMETER

7·84

TEST CONDITIONS

MIN

TYP

f max

Maximum clock frequency

eL=15pF,

10

18

tPLH

Propagation delay time, low-to-high-Ievel output

RL = 2 kil,

24

40

ns

tpHL

Propagation delay time, high-to-Iow-Ievel output

See Figure 1

27

40

ns

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

MAX UNIT
MHz

10'

TYPES SN5491A, SN54L91, SN54LS91, SN7491A, SN74L91, SN74LS91
8-BIT SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
VCC

=5

V OUTPUT

-

LoADCII:lcLJlTl VCC

=5

-- - -,

I
I
I
I

V

RL

I
I
I
IL ____________
Note B -=
-:;:- Note D
_
--1I

PULSE
GENERATOR r------------T--~I>--~~l>
(See Note A)
INPUT A

C

se;T

2.4 V

TEST CIRCUIT

1

CLOCK·PULSE
INPUT

INPUTA

2

thru

7

8

9

thru

15

16

17

18

19 thru 23

24

25

26

27

n n----n n n----n n n n n----n n n n n
I U L__ J U U L __ J U U U U L __ J U U U U L

L____

OUTPUTQH _ _ _ _ _ _ _

____ ~ ______________
SL____
____ ~
TYPICAL INPUT/OUTPUT WAVEFORMS

-"...---3 V

CLOCK
INPUT

II

INPUT

I

-1-- -

-OV

1
1
1

I

~-------3V

I
I
I

t PH L

INPUT
AOR B

I

----i----.!

tPLH~

I

VOL
VOH

-1- th

-

-; -

-

-----OV

-.I.--

-

-

-

-

-

-

3V

INPUT
'-------- 0 V

SWITCHING TIMES VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
NOTES:

n.

A. The generator has the following characteristics: tw(clock) = 500 ns, PRR '" 1 MHz, Zout '" 50
For SN5491A/SN7491A,
t r '" 10 ns and tf '" 10 ns; for SN54L91/SN74L91, tr '" 15 ns and tf '" 15 ns; and for SN54LS91/SN74LS91, tr = 15 ns, and
tf = 6 ns.
B.
C.
D.
E.

CL includes probe and jig capacitance.
All diodes are 1 N3064 or 1 N916.
Cl = 30 pF and is used for SN54L91/SN74L91 only.
For SN5491A/SN7491A, Vref = 1.5 V; for SN54L91/SN74L91 and SN54LS91/SN74LS91, Vref

=

1.3 V.

FIGURE 1-SWITCHING TIMES

1076

TEXAS INCOHPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-85

TYPES SN5494, SN7494
4-81T SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7211812. DECEMBER 1972

•

TTL MSI PARALLEL-IN SERIAL-OUT REGISTERS
for application as
Dual-Source, Parallel-To-Serial Converter
• Serial-In Serial-Out Register

description
SN5494 ••• J OR W PACKAGE
SN7494 ••• J OR N PACKAGE
(TOP VIEW)

These monolithic shift registers which utilize transistor-transistor logic (TTL) circuits in the familiar
Series 54/74 configuration, are composed of four R-S
master-slave flip-flops, four ANO·OR-INVERT gates,
and four inverter-drivers. Internal interconnections of
these functions provide a versatile register which
performs right-shift operations as a serial-in, serial-out
register or as a dual-source, parallel-to-serial converter. A number of these registers may be connected in
series to form an n-bit register.

P2A

All flip-flops are simultaneously set to a low output
level by applying a high-level voltage to the clear
input while the internal presets are inactive (high).
See the preset function table below. Clearing is
independent of the level of the clock input.
The register may be parallel loaded by using the clear
input in conjunction with the preset inputs. After
clearing all stages to low output levels, data to be
loaded is applied to either the Pl or P2 inputs of each
register stage (A, B, C, and 0) with the corresponding
preset enable input, PE 1 or PE2, high. Presetting. like
clearing, is independent of the level of the clock
input.

P1A

P1B

pm

P1C

Vcc

PEl

SER.

CLOCK

IN

positive logic: see function tables

Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be setup at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input
provides this information for the first flip·flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be at a low level and the internal presets must be inactive (high) when
clocking occurs.

•

PRESET FUNCTION TABLE

REGISTER FUNCTION TABLE

(BIT A TYPICAL OF ALL)
PRESET INPUTS

INTERNAL

INPUTS

INTERNAL PRESETS

INTERNAL OUTPUTS

A

B

C

D

X

H (inactive)

H

H

H

H

H

X

L
H

L
H

L

L
H

L
L

X

X

H

H

H

L
L
t
t

X

QBO

X

QAO
H

QBO

Qeo
H

H

H

L

L

°An
OAn

°Bn
OBn

L

X

L

CLEAR CLOCK SERIAL

Oc

PE1 P1A PE2 P2A PRESET A
L

X

X

L

H (inactive)

X

L

L

X

H (inactive)

X

L

X

L

H (inactive)

L

H

L

H

X

X

L (active)

H

H

L
H

H

H

H

X

X

H

H

L (active)

H

H

H

H

L
L

X

°A
L

°B
L

L
H

OUTPUT
aD
L
H
QDO
aDO
°Cn
°Cn

H = high level (steady state). L = low level (steady state). X = irrelevant. t = transition from low to high level
QAO. QBO. QCO. QOO = the level of QA. QB. QC. or QO. respectively. before the indicated steady-state input conditions were establlshed_
QAn. QBn. QCn = the level of QA. QB. or QC. respectively. before the most-recent t transition of the clock.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
. . . . 5.5V
_55°C to 125°C
. O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 1)
....... .
Input voltage (see Note 2)
. . . . . . . .
Operating free-air temperature range: SN5494 Circuits
SN7494 Circuits
Storage temperature range
NOTES:

1. Voltage values are with respect to network ground terminal.
2. Input voltage must be zero or positive with respect to network ground terminal.
1076

7·86

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE

sox

5012 •

DALLAS. TEXAS 75222

TYPES SN5494, SN7494
4-BIT SHIFT REGISTERS
functional block diagram
PRESETS
r -__________________--JI\~------------------~

/

\
P2A
(16)

P1A
(1)

P1B

P2B

(2)

(14)

P2C

P1C

(13)

(3)

PlD
(4)

P20
(11)

PRESET {PE2 (15)

EI~~~~;

PE1.....;(...;6)~--+~~_+_+--+. .- + + - - + _...__if_+_-+_.

.-----IS

S

QB
CK

CK
; 0 -....-_+--1 R

CK

R
CLEAR

s

S

(9) OUTPUT

CK

R

R
CLEAR

QO

CLEAR

CLEAR

(8)

CLOCK

•

CLEAR

I

--

- - - - INPUT INPUT Preset enable All others Req NOM 800 .!1 4 k.!1 'L96 'L96 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT - .......- - V C C 260 V CC ----1~-- n NOM INPUT OUTPUT INPUT Preset enable All others • Req NOM 1.6 k.!1 8 k.!1 I 'LS96 'LS96 EQUIVALENT OF EACH INPUT TYPICAL OFALL OUTPUTS -----111~- V CC VCC Req INPUT - [\d U'" ' - - -.....-OUTPUT ~, ~~ ~~ INPUT Req NOM Serial Clock, Clear Preset enable 25 k.!1 17 k.!1 3.4 kn 1i7 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-97 TYPES SN5496, SN7496 5-81T SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage (see Note 2). . . Operating free·air temperature range: SN549S SN749S Storage temperature range 7V 5.5 V -55°C to 125°C oOe to 70°C -S5°e to 150°C NOTES: 1. Voltage values are with respect to network ground terminal. 2. I nput voltages must be zero or positive with respect to network ground terminal. recommended operating conditions SN5496 MIN Supply voltage, Vee SN7496 NOM 4.5 MIN NOM MAX 5.5 4.75 5 5.25 V -400 16 IJA mA 10 MHz 5 High·level output current, 10H -400 Low·level output current, 10L 16 10 0 Clock frequency, fclock UNIT MAX 0 Width of clock input pulse, tw(clock) 35 35 ns Width of preset and clear input pulse, tw 30 30 ns Serial input setup time, tsu (see Figure 1) 30 30 ns 0 0 Serial input hold time, th (see Figure 1) Operating free-air temperature, T A -55 125 ns 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • VIH High·level input voltage VIL Low·level input voltage VOH TEST eONDITIONSt MIN SN5496 TYPt MAX 2 Vee - MIN, High·level output voltage Low·level output voltage II Input current at maximum input voltage IIH High·level input current 2 VIH - 2V, VIL = 0.8 V, 10H = -4001JA Vee - MIN, VIH - 2V, 2.4 3.4 V 10L = 16 mA Vee = MAX, VI = 5.5V preset enable 40 40 200 200 -1.6 -1.6 -8 -8 Vee = MAX, VI = 2.4 V preset enable any input except preset enable Vee = MAX, VI = 0.4 V preset enable lOS Short·circuit output current§ Vee = MAX lee Supply current Vee - MAX, See Note 3 0.4 1 1 -20 -57 48 -18 48 68 V V 3.4 0.2 0.4 0.2 VIL = 0.8 V, 0.8 2.4 any input except Low·level input current SN7496 UNIT TYPt MAX 0.8 VOL IlL MIN V mA IJA mA -57 mA 79 mA tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time. NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS tpLH Propagation delay time, low-to-high-Ievel output from clock tpHL Propagation delay time, high-to-Iow·level output from clock eL tpLH Propagation delay time, low·to-high·level output from preset or preset enable tpHL Propagation delay time, high·to-Iow-Ievel output from clear 7-98 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • = 15pF, RL = 400 n, See Figure 1 DALLAS. TEXAS 75222 MIN TYP MAX UNIT 25 40 ns 25 28 40 ns 35 ns 55 ns TYPES SN54L96, SN74L96 5-811 SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage (see Note 2) Operating free-air temperature range: SN54L96 SN74L96 Storage temperature range NOTES: 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. Input voltage must be zero or positive with respect to network ground terminal. recommended operating conditions SN54L96 MIN Supply voltage, Vee 4.5 NOM SN74L96 MAX MIN 5.5 4.75 5 High-level output current, 10H NOM MAX 5 -200 5.25 V -200 IlA S Low-level output current, 10L 0 Clock frequency, fclock 5 UNIT 0 S mA 5 MHz Width of clock, preset, or clear input pulse, tw 100 100 Serial input setup time, tsu (see Figure 1) 100 100 ns 0 0 ns Serial input hold time, th (see Figure 1) Operating free-air temperature, T A -55 125 ns 70 0 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage SN74L96 SN54L96 MIN TYP:j: MAX Vee= MIN, II Input current at maximum input voltage VIH=2V, VIL = O.S V, 10H = -200 IlA Vee= MIN, VIH=2V, VIL = O.S V, 10L = 8 mA Vee = MAX, VI = 5.5 V 2.4 Vee= MAX, 0.2 VI=2.4V preset enable any input except IlL Low-level input current preset enable Vee = MAX, VI = 0.4 V preset enable lOS Short-circuit output current § Vee= MAX Ice Supply current Vee = MAX, 24 V V 3.2 0.4 1 1 20 20 100 100 -O.S -0.8 -4 -4 V mA Il A II mA -29 mA 24 40 mA TYP MAX UNIT 50 ns 50 SO SO 56 70 ns 110 ns -9 34 UNIT V 0.2 0.4 -29 -10 See Note 3 2.4 3.2 any input except preset enable MAX O.S 0.8 Low-level output voltage High-level input current TYP:j: 2 2 VOL IIH MIN IFor co~ditions shown at MIN or MAX, use t~e appropriate value specified under recommended operating conditions. All tYPIcal values are at V CC = 5 V, T A = 25 C. §Not more than one output should be shorted at a time. NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open. switching characteristics, Vee = 5 V, T A = 25° e PARAMETER TEST CONDITIONS tpLH Propagation delay time, low-to-high-Ievel output from clock tpHL Propagation delay time, high-to-Iow-Ievel output from clock tpLH Propagation delay time, low-to-high-Ievel output from preset or preset enable tpHL Propagation delay time, high-to-Iow-Ievel output from clear eL = 15pF, RL=soon, See Figure 1 MIN ns 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-99 TYPES SN54LS96, SN74LS96 5-81T SHIFT REGISTERS REVISED AUGUST 1977 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . Operating free-air temperature range: SN54LS96SN74LS96. Storage temperature range 7V 7V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74LS96 SN54LS96 MIN Supply voltage, VCC NOM 45 MAX MIN 55 4_75 5 High-level output current, 10H MAX 5 5_25 V -400 IJA -400 Low-level output current, 10L 4 Clock frequency, fclock 25 0 UNIT NOM 0 8 mA 25 MHz Width of clock input pulse, tw(clockl 20 20 ns Width of preset and clear input pulse, tw 30 30 ns Serial input setup time, tsetup (see Figure 1 I 30 30 ns 0 0 Serial input hold time, thold (see Figure 11 Operating free-air temperature, T A -55 125 ns °c 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ,SN54LS96: TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VOH High-level outP.Jt voltage Vee= MIN, II = -18mA Vee= MIN, VIH = 2V, 2_5 input voltage TVP+ MAX UNIT V 2 Vee= MIN, VIH = 2V, 0.7 0.8 V -1.5 -1.5 V 3_5 VIL = VIL max 0.25 IIOL =4mA 2.7 Preset enable Vee = MAX, V 3_5 Preset enable Low-level IlL input current Preset enable Vee = MAX; 0-4 0.35 0_5 0_5 0.5 0.1 0.1 100 100 20 20 V mA VI = 2.7 V All others Vee = MAX, 0_25 VI =7 V All others High-level IIH input current 0.4 IIOL =8 mA Input current at maximum MIN VI L = VI L max, 10H = -400 IJA VOL Low-level output voltage II SN74LS96 TVP+ MAX 2 VIK Input clamp voltage II MIN VI = 0,4 V All others IJA -2 -2 -0,4 -0-4 -100 -20 -100 mA 20 mA mA --~-- lOS Short-circuit output current ~ Vee = MAX lee Supply current Vee = MAX, -20 12 See Note 3 12 20 fFor co~ditions shown at MIN or MAX, use t~e appropriate value specified under recommended operating conditions. All typIcal values are at V CC = 5 V, T A = 25 C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second_ NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER tpLH TEST CONDITIONS Propagation delay time, low-to-high-Ievel output from clock eL=15pF, tpHL Propagation delay time, high-to-Iow-Ievel output from clock tPLH Propagation delay time, low-to-high-Ievel output from preset or preset enable tPHL Propagation delay time, high-to-Iow-Ievel output from clear ~L = 2 kn, ' See Figure 1 MIN TVP MAX UNIT 25 40 ns 25 40 ns 28 35 ns 55 ns 877 7-100 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN5496, SN54L96, SN54LS96, SN7496, SN74L96, SN74LS96 5-81T SHIFT REGISTERS PARAMETER MEASUREMENT INFORMATION OUTPUT VCC (See Note C) FROM OUTPUT UNDER TEST l' = 15 pF (See Note B) CL = LOAD CIRCUIT ~ r- tw(clear) CLEAR INPUT PRR"; 1 MHz 1 V I ref ! ~---------(S rS--------------------J -; Vref --------------------------oV 1 I iI 1 I PRESET INPUT PRR';; 1 MHz I (See Note 0) --I11---------------~5 I __ -111-___..... I CLOCK INPUT PRR';;; 1 MHz ! 1--1 V '" PRR';;1MHz -l I I I 1 I : l- t--------t- tpH L - - -..... : (See Note F) OA OUTPUT (See Note E) \v", tsu J V aV \'-V_re_f_ _ 1 I .JI~~ ___ ~------ JV OV J-- th II - - - - 1" - - - - - - - ' 1 Vref I r-tw(preset)-.I t--tw(clock)--t I 55-\) 1 \v", )c Vref 'rS_ _ _ _ _ _ _ _ _ _ _ _..J. tW(Clockril ,.._ _ _~ I SERIAL INPUT V /--1 1 .>---0'1-1- I Vref ~' -' ,.! r-----~-------3V I - tp LH 1 - - - - '!0~5-------1--~... tpHL -r - - - - - - aV I-----t- tp LH • I \v",!v~ __ ::: tv,,, VOLTAGE WAVEFORMS NOTES: A. Input pulses are supplied by pulse gen~rators having the following characteristics: duty cycle';;; 50%, Zout "" 50 n; for '96 and 'L96, tr';; 10 ns, tf';;; 10 ns, and for 'LS96 tr = 15 ns, tf = 6 ns. B. CL includes probe and jig capacitance. C. Alidiodesare1N30640r1N916. D. Preset may be tested by applying a high-level voltage to the individual preset inputs and pulsing the preset enable or by applying a high-level voltage to the preset enable and pulsing the individual preset inputs. E. QA output is illustrated. Relationship of serial input to other 0 outputs is illustrated in the typical shift sequence. F. Outputs are set to the high level prior to the measurement of tpH L from the clear input. G. For '96 and 'L96, Vref = 1.5 V; for 'LS96 Vref = 1.3 V. FIGURE 1-SWITCHING TIMES TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 7·101 TTL MSI TYPES SN5497, SN7497 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS BULLETIN NO. DL-S 7611802, DECEMBER 1972-REVISED OCTOBER 1976 SN5497 ••• J OR W PACKAGE SN7497 ••• J OR N PACKAGE (TOP VIEW) • Perform Fixed-Rate or Variable-Rate Frequency Division • For Applications in Arithmetic, Radar, Digital-to-Analog (0/ A), Analog-to-Digital (A/D), and other Conversion Operations • Typical Maximum Clock Frequency ... 32 Megahertz RATE INPUTS ~ Vee o C UNITY! ENABLE CLEAR CASCADE INPUT description These monolithic, fully synchronous, programmable counters utilize Series 54/74 TTL circuitry to achieve 32·megahertz typical maximum operating frequencies. These six-bit serial binary counters feature buffered clock, clear, and enable inputs to control the operation of the counter, and a strobe input to enable or inhibit the rate input/decoding AND·OR-INVERT gates. The outputs have additional gating for cascading and transferring unity·count rates. positive logic: see description The counter is enabled when the clear, strobe, and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64, ie.: f out = M'fin 64 where: M = F'2 5 + E'2 4 + 0'2 3 + C'2 2 + B'2 1 + A'2 0 When the rate input is binary 0 (all rate inputs lowl. Z remains high. In order to cascade devices to perform 12-bit rate multiplication, the enable output is connected to the enable and strobe inputs of the next stage, the Z output of each stage is connected to the unity/cascade input of the other stage, and the sub·multiple frequency is taken from the Y output. II The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS - - -....- - V C C VCC------~__- - - - - - INPUT OUTPUT Clock input: Req Other inputs: Req =2 =4 kS1 NOM kS1 NOM 1076 7-102 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN5497, SN7497 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS description (continued) STATE AND/OR RATE FUNCTION TABLE (See Note Al OUTPUTS INPUTS LOGIC LEVEL OR NUMBER OF PULSES BINARY RATE NUMBER OF UNITY/ CLEAR ENABLE STROBE F E D C B A CLOCK PULSES CASCADE NOTES: Y Z ENABLE X H L H H B H L H 1 C H 64 64 H 1 1 1 C L H L 64 H 2 2 1 C H X H X X X X X X L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H L L L L L L H L L L L L H L L L L H L L L L L L L L • NOTES L 64 H 4 4 1 C L L 64 H 8 8 1 C L L L 64 H 16 16 1 C L L L H 32 32 1 C H H H H H H 64 64 H 63 63 1 L H H H H H H 64 L H 63 1 C D L H L H L 64 H 40 40 1 E L L L A. H = high level, L .. low level, X = irrelevant. All remaining entries are numeric counts. B. This is a simplified illustration of the clear function. The states of clock and strobe can affect the logic level of Y and Z. A low unity/cascade will cause output Y to remain high. C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable·rate inputs. D. Unity/cascade is used to inhibit output Y. E. f out = M'fin 64 = (8 + 32) fin --6-4-- 40 fin = -;;-- = 0.625 fin· functional block diagram • I I 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·103 TYPES SN5497, SN7497 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ......... . Input voltage . . . . . . . . . . . . . . . . . . Operating free air temperature range: SN5497 (see Note 2) SN7497 Storage temperature range 7V 5.5 V -55°C to 125°C aOe to 7aoe -65°C to 15aoe recommended operating conditions SN5497 MIN NOM Supply voltage, VCC 4.5 SN7494 MAX 5 MIN NOM 5.5 4.75 5.25 -400 16 High-level output current, 10H Low·level output current, 10L 0 Clock frequency, fclock 25 UNIT MAX 5 V -400 IJA 16 mA 25 MHz 0 Width of clock pulse, tw(clockl 20 20 ns Width of clear pulse, tw(c1earl 15 15 ns (See Figure 11 Enable setup time, tsu: Before positive·going transition of clock pulse Before negative·going transition of previous clock pulse t w (clockl- 1O 25 0 20 t w (c1ockl- 1O t cp -10 20 -55 125 0 25 0 ns t w (c1ockl- 1O (See Figure 11 Enable hold time, th: After positive'going transition of clock pulse 0 After negative·going transition of previous clock pulse Operating free·air temperature, T A (See Note 21 0 t w (clockl- 1O t cp -10 ns 70 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER II VIH High·level input voltage VIL VIK Low·level input voltage VOH High-level output voltage VOL Low·level output voltage II Input current at maximum input voltage IIH High-level input current Low·level input current lOS Short circuit output current § TYP+ MAX UNIT 2 Input clamp voltage IlL MIN clock input' other inputs clock input other inputs VCC- MIN, 11- -12 mA VCC= MIN, VIH=2V, VIL = 0.8 V, 10H = -4001JA VCC= MIN, VIH = 2 V, VIL = 0.8 V, 10L = 16 mA VCC = MAX, VI = 5.5 V VCC= MAX, VI=2.4V VCC= MAX, V -1.5 V 3.4 0.2 V 0.4 1 80 40 -3.2 VI = 0.4 V -1.6 -55 -18 VCC = MAX ICCH Supply current, outputs high ICCL Supply current, outputs low 2.4 V 0.8 VCC = MAX, See Note 3 58 VCC= MAX, See Note 4 80 V mA IJA mA mA mA 120 mA tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. NOTES: 1. Voltage values are with respet to network ground terminal. 2. An SN5497 in the W package operating at free·air temperatures above 11SoC requires a heat sink that provides a thermal resistance from case to free'air, ROCA, of not more than 55°C/W. 3. ICCH is measured with outputs open and all inputs grounded. 4. ICCL is measured with outputs open and all inputs at 4.5 V. 1076 7-104 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN5497, SN7497 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS REVISED OCTOB'E R 1976 switching characteristics, VCC PARAMETERS~ = 5 V, T A = 25°C, N = 10 FROM TO INPUT OUTPUT Enable Enable TEST CONOITIONS f max tPLH tpHL tpLH tpHL tpLH tpHL tpLH Strobe Clock 25 32 Clock Z Rate Z Unity/Cascade tpHL tpLH Clock tpLH Clear tpHL tPLH Any Rate Input 30 18 17 26 CL~15pF, 6 10 n, 9 14 See Figure 1 9 14 6 10 400 19 30 22 33 19 30 22 33 Y 24 36 Z 15 23 15 23 15 23 Y tpHL ~fmax tpLH tpH L == maximum clock frequency. == propagation delay time, low-to-high-Ievel == propagation delay time, high-to-Iow-Ievel 18 12 Enable tpHL 21 12 20 Y Strobe 14 23 tpHL tpLH 20 39 ~ UNIT MHz 13 15 RL Y MAX 26 Y tPHL tpLH TYP Z tpHL tpLH MIN ns ns ns ns ns ns ns ns ns ns output. output. TYPICAL APPLICATION DATA • This application demonstrates how the '97 can be cascaded to perform 18-bit rate multiplication. This scheme is expandable to n-bits by extending the pattern illustrated, 18-BIT RATE INPUT CLEAR ENABLE (LOW) DISABLE (HIGH) ENABLE (LOW) DISABLE (HIGH) CLOCK_~------t--1~~~~::::::::~~:1---t::~::::::::~~==~1r~ INPUT 11 INVERTED OUTPUT NONINVERTED OUTPUT As illustrated, two of the 6-bit multipliers can be cascaded by connecting the Z output of unit A to the unity cascade input of unit B, in which case, a two-input NOR gate is used to cascade the remaining multipliers. Alternatively, all three Y outputs can b~ cascaded with a 3-input NOR gate. The three unused unity cascade inputs can be conveniently terminated by connecting each to its Z output. 1076 TEXAS INCOI{POI{ATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-105 TYPES SN5497, SN7497 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS PARAMETER MEASUREMENT INFORMATION ~ l...-..t- VCC ENABLE INPUT ~ LOAD CIRCUIT :--'''''CIOCkl~ I I I I I 1.5 V I I 3V CLOCK OR STROBE INPUT ~:: ..-.r-tpLH I 1.... l su 1,.->10ns OUTPUT Z L......-1f>HL I ~~~~-VOH -1f'5_~ . II ~ ,- -I L-.......L. IPHL j\--------- OUTPUT Y VOH PROPAGATION DELAY TIMES, CLOCK TO Z AND Y, AND STROBE INPUT TO Z AND Y ENABLING FROM POSITIVE-GOING TRANSITION OF CLOCK PULSE ' Fl __ RATE INPUT I.'wlclockl,"--'cp---.l I • I CLOCK INPUT 15 V . I I I : I ----3V I I. u ----.I 1.5 OUTPUTZ 'PHL I h OV 'PLH lC VOH L-L~~~ ----VOL t-- I Flip-flops are at a count so that all other inputs to the gate under test are high and all other Inputs, Including other rate Inputs, are low. 3V 1.5 V _ - f..--.t- ~._.. OV I~Ih ~ ~:pAUBTLE v ~3V I 1.5 V 1.5 V ~VOH L-L~'~~ ----VOL Unity/cascade and rate inputs are high, other Inputs are low, and flip-flops are at any count other than maximum. --------~.'-. - - - - - VOL -DISABLED\~ENABLED--,,;--DISABLED VOL r---ot- IPLH ~._ .. OUTPUT Y VOH 1.5 V ___ VOL PROPAGATION DELAY TIMES, ENABLE INPUT TO ENABLE OUTPUT ~ENABLED~,-DISABLED-- ~''''IcIOCkl~ OV IPLH I Flip-flops are at the maximum count. Other inputs are low. All three outputs are loaded during testing I JV 1.5 V I-_____ i -.-fiIII............Dh ENABLE OUTPUT CLOCK 1.5 V I.---et-"'H L OUTPUT OF DEVICE UNDER TEST I - - _ - - - - _ - - - _ _ - - - Ov PROPAGATION DELAY TIMES, RATE INPUT TO Z OUTPUT Y UN'TY/CASCA~'5V ENABLING FROM NEGATIVE-GOING TRANSITION OF PREVIOUS CLOCK PULSE INPUT t----t- 1. Unity/Cascade and pin 2 (rate input) are high, other inputs are low. Clear the counter and apply clock and enable pulse as illustrated. OUTPUT Y 2. Setup and hold times are illustrated for enabling a single clock pulse (count!. Continued application of the enable function will enable subsequent clock pulse (counts) until disabling occurs (enable goes high). The total number of counts will be determined by the total number of positive-going clock transition enabled. NOTES: ~3V ~~·~~---OV k'PHL -I---VOH ~ 15 VIS V VOL Output Z is high. PROPAGATION DELAY TIMES, UNITY/CASCADE INPUT TO Y A. The input pulse generator has the following characteristics: tw(clock) = 20 ns, tTLH .;; 10 ns, tTHL <: 10 ns, PRR = 1 MHz, Zout '" 50 n.. B. CL includes probe and jig capacitance. C. All diodes are 1 N3064. FIGURE 1-SWITCHING TIMES 1076 7-106 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54L98, SN74L98 4-81T DATA SELECTORS/STORAGE REGISTERS BULLETIN NO. DL-S 7211822, DECEMBER 1972 SN54L98 ••• J PACKAGE SN74L98 ••• J OR N PACKAGE (TOP VIEW) description These monolithic data selectors/storage registers are composed of four S-R master-slave flip-flops, four AND-DR-INVERT gates, one buffer, and six inverter/drivers. 0A 0B D1 CLOCK WORD SELECT ~ When the word select input is low, word 1 (A 1, 81, C1, D 1) is applied to the flip-flops. A high input to word select will cause the selection of word 2 (A2, 82, C2, D2). The selected word is shifted to the output terminals on the negative-going edge of the clock pulse. A1 Typical power dissipation is 25 mW. The SN54L98 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74L98 o is characterized for operation ftom O°C to 70 e. B2 C2 02 positive logic: word select low for word 1, word select high for word 2, see description functional block diagram and schematics of inputs and outputs EQUIVALENT OF EACH INPUT v CC - - - - - - . - - - - - - CK INPUT Bl~--------~~-r~ (14) OB OB ac (13)ac CK Cl~--------~~~~ CK TYPICAL OF ALL OUTPUTS ---4..---VCC Dl~~-------r-r-r~ aD (111 aD CK CLDCK_(~10~)__________________~ OUTPUT ~__________~ I ~ ... dynamic input activated by transition from a high level to a low level. I 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54L98, SN74L98 4-81T DATA SELECTORS/STORAGE REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... Input voltage (see Note 2) . . . . . Operating free-air temperature range: SN54L98 SN74L98 Storage temperature range NOTES: 8V 5.5 V _55°C to 125°C oOe to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. Input voltages must be zero or positive with respect to network ground terminal. recommended operating conditions SN54L98 MIN 4.5 Supply voltage, Vee NOM SN74L98 MAX MIN 5.5 4.75 5 V -200 IJ.A 3_6 mA 2 Low-level output current, 10L 200 200 at A, B, e, or D 100 100 at word select 150 150 at A, B, e, or D 120 120 at word select 100 Width of clock pulse, tw(clock) Setup time for high-level data, tsu(H) Setup time for low-level data, tsu(L) ns ns ns 100 -55 Operating free-air temperature, T A 125 UNIT 5.25 5 -100 High-level output current, 10H MAX NOM 70 0 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) II VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage SN54L98 TEST CONDITIONSt PARAMETER MIN SN74L98 TYP+ MAX 2 MIN TYP+ MAX 0.7 Vee; MIN, VIH; 2V, VIL; 0.7 V, 10H; MAX Vee; MIN, VIH; 2V VIL; 0.7 V, 10L; MAX VOL Low-level output voltage II Input current at maximum input voltage Vee - MAX, VI- 5.5 V IIH High-level input current Vee - MAX, VI - 2.4 V IlL Low-level input current Vee; MAX, VI - 0.3 V lOS Short-circuit output currentS Vee; MAX lee Supply current Vee - MAX, 2.4 3.3 V V 3.2 0.4 V 100 100 IJ.A 10 10 IJ.A -0.18 -0.18 mA -15 mA 9 mA 0.15 0.3 -3 See Note 3 0.7 2.4 UNIT V 2 -15 5 0.2 -3 9 5 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC; 5 V, T A; 25°C. § Not more than one output should be shorted at a time. NOTE 3: ICC is measured with all inputs grounded and all outputs open. switching characteristics, Vee = 5 V, TA = 25°e TEST CONDITIONS PARAMETER f max Propagation delay time, low-totpLH eL;50pF, high-level output from clock input RL;4kn, TYP MAX UNIT MHz 5 115 200 ns 125 200 ns See Note 4 Propagation delay time, high-totpHL MIN 3 Maximum clock frequency low-level output from clock input NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1076 7·108 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54L99, SN74L99 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS TTL MSI BULLETIN NO. DL·S 7211871, DECEMBER 1972 • N-Bit Serial-to-Parallel Converter • N-Bit Parallel-to-Serial Converter • N-Bit Storage Register • J-j( Serial Input SN54L99 ••• J PACKAGE SN74L99 ••• J OR N PACKAGE (TOP VIEW) description These 4-bit registers feature parallel inputs, parallel outputs, J.j( serial inputs, mode control, and two clock inputs. The registers have three modes of operation: Parallel (Broadside) load Shift right (the direction GA toward GO) Shift left (the direction GO toward GA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flop and appears at the outputs after the high-to-Iow transition of the clock-2 input. During loading, the entry of serial data is inhibited. A B C VCC D M CLOCK 1 positive logic: see function table Shift right is accomplished on a high-to-Iow transition of clock 1 when the mode control is low. Serial data for the right-shift mode is entered at the J-j( inputs. These inputs permit the first stage to perform as a J.j(, a O·type, or T-type flip-flop as shown in the function table. Shift left is accomplished on the high-to-Iow transition of clock 2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous fI ip-flop (GO to input C, etc.). Serial data for this mode is entered at the 0 input. The clock input may be applied commonly to clock 1 and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected. FUNCTION TABLE INPUTS MODE CLOCKS H H ~ PARALLEL OD aD J K A B C D °A °B Oc X X X X X X X OAO X X X a b c d a OSO b OCO °DO QOO c d d CONTROL 2 (L) 1 (R) H OUTPUTS SERIAL d H ~ X X X Qst Qct QDt d QBn QCn QO n L L H X X X X X X QAO QBO QCO QOO 000 L X ~ L H X X X X QCn DCn X ~ L L X X X X QBn QCn DCn L X ~ H H X X X X QAO QAO L QAn H QAn QBn L QBn QCn DCn L X ~ H L X X X X DAn QAn QBn QCn DCn t L L X X X X X X QAO QBO QCO QOO DOO ~ L L X X X X X X QAO QBO QCO QOO DOO ~ L H X X X X X X QAO QBO QCO QOO DOO t t H L X X X X X X QAO QBO QCO QOO DOO H H X X X X X X QAO QBO QCO QOO DOO d • I tShifting left requires external connection of QB to A, QC to B, and QD to C. Serial data is entered at input D. level (steady state), L = low level (steady state) (any input, including transitions) • = transition from high to lov.. level, t = transition from low to high level. a, b, c, d = the level of steady·state input at inputs A, B, C, or D, respectively. QAO, QBO, QCO, QDO = the level of QA. QB. QC. or QD. respectively. before the indicated steady·state input conditions were established. QAn' QBn. QCn. QDn = the level of QA, QB. QC, or QD, respectively. hefore the most·recent • transition of the clock. H X = high = irrelevant 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·109 TYPES SN54L99, SN74L99 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS functional block diagram J (2) SERIAL INPUTS (15) OA { R (16) s (3) (14) as M PARALLEL INPUTS (12) Oc C (4) t--_....;(c.;.;10,,-) 00 o (6) (11) M~OE no (7) CONTROL Rlg~~CS~:FT-,-(8::':')_-+-~F-----i.-~ • I --4>. dynamic Input activated by transition from a high level to a low level. I schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ----..-----v CC vcc--------~------- INPUT OUTPUT Input A and M: Req All other: Req = 20 = 40 k!l NOM k!l NOM 1272 7-11.0 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54L99, SN74L99 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ........ . Input voltage (see Note 2) . . . . . . . . . Operating free·air temperature range: SN54L99 Circuits SN74L99 Circuits Storage temperature range NOTES: 8V 5.5 V -55°C to 125°C . aOc to 7aoC -65°C to 15aoC 1. Voltage values are with respect to network ground terminal. 2. Input voltages must be zero or positive with respect to network ground terminal. recommended operating c~nditions SN54L99 MIN Supply voltage, Vee 4.5 NOM SN74L99 MAX MIN 5.5 4.75 5 High·level output current, IOH NOM -100 Low·level output current, IOL MAX 5 UNIT 5.25 V -200 ).LA 3.6 mA 2 Width of clock pulse, tw(clock) 200 200 ns Setup time for high·level data at J, K, A, B, e, or D inputs, tsu(H) 100 100 ns Setup time for low·level data at J, K, A, B, e, or D inputs, tsu (L) 120 120 ns 0 0 ns Time to enable clock 1, tenable 1 (see Figure 1) 225 225 ns Time to enable clock 2, tenable 2 (see Figure 1) 200 200 ns Time to inhibit clock 1, tinhibit 1 (see Figure 1) 100 100 ns Time to inhibit clock 2, tinhibit 2 (see Figure 1) 0 0 ns Hold time at J, K, A, B, e, or D inputs, th Operating free·air temperature, T A -55 125 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low·level input voltage VOH VOL II IIH IlL TEST eONDITIONSt SN54L99 MIN TYP+ SN74L99 MAX 2 MIN TYP+ High·level output voltage Low·level output voltage Input current at J, K, B, e, or D maximum input voltage MorA High·level J, K, B, e, or D input current MorA Low-level J, K, B, e, or D input current MorA VIH - 2 V, VIL = 0.7 V, IOH = MAX Vee- MIN, VIH - 2V VIL = 0.7 V, IOL = MAX Vee = MAX, VI = 5.5V Vee= MAX, Short·circuit output current§ Vee = MAX lee Supply current Vee - MAX, 3.3 0.15 VI = 0.3 V 0.7 2.4 100 100 200 200 10 10 20 20 -0.18 -0.36 See Note 3 0.4 -0.18 -15 -3 3.8 -0.36 -3 3.8 9 V V 3.2 0.2 0.3 VI = 2.4 V Vee = MAX, lOS 2.4 UNIT V 0.7 Vee - MIN, MAX 2 II V ).LA ).LA mA -15 mA 9 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be .!.horted at a time. NOTE 3: With all outputs and J and K inputs open, mode control at 4.5 V, inputs A through D grounded, ICC is measured after a momentary 3 V, then ground, is applied to both clock inputs. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS f max Maximum clock frequency tPLH Propagation delay time, low·to-high·level output from either clock tpHL Propagation delay time, high-to-Iow·level output from either clock eL = 50 pF, See Figure 2 RL = 4 k!1, MIN 3 TYP MAX UNIT MHz 5 115 200 ns 125 200 ns 1076 TEXASINCOHPOHATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-111 TYPES SN54L99, SN74L99 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS PARAMETER MEASUREMENT INFORMATION OUTPUT VCC FROM OUTPUT UNDER TEST CL 50 pF = (See Note B) J LOAD CIRCUIT J JendK INPUTS MINPUT \----- \'-------J/ t,.3V CLOCK 1 INPUT - - V IH ' - - - - - - - - - - V IL ~1.3V ten8ble 1 l,'---.":"'I----' "'1'----'- IH / _ _ _ _ _ _ _ VV '-------' IL - I I - - - - - V IH I ' - - - - - - - - - - V IL tinhibit 2 CLOCK 2 INPUT 1\. -_-_-_-_-_ . -te----- ' - -_ _ _ _ _ _..J. - V V IH IL C ::: -II~----"""\\.____..J/ QAOUTPUT _ _ _ _ _ _ _ NOTE: A input is at the low level. VOLTAGE WAVEFORMS FIGURE 1-CLOCK ENABLE/INHIBIT TIMES II I- ~ ;;'90% 00%\ <15 n.--I DATA INPUT : 10% 1.3 V \-';15n. 1.3 V \:V------ I ~ i1.3V 10% ~ tsulL) I -l I ~th I CLOCK INPUT ..l I ~th ~ l- I I I OUTPUT ISee Note D) / I I I I I I I OV 1+------+1-- tw Iclock I I I I I OV 1+ t.uIH) I 1 ';15 ns 3V I I \13V 1 1 -.j tpHLI- I I I -l tpLH t~,-----I- VOH VOL VOLTAGE WAVEFORMS FIGURE 2-SWITCHINU TIMES NOTES: A. The input waveforms are supplied by pulse generators having the following characteristics: Zout'" 50 il. For data pulse generator: tw;;;' 150 ns, PRR';;; 500 kHz, tsetup(L) = 120 ns, and tsetup(H) = 100 ns. For clock pulse generator: tw;;;' 200 ns and PRR';; 1 MHz. When testing f max , vary PRR. B. CL includes probe and jig capacitance. C. All diodes are 1 N916. D. When data input is applied to J and K inputs, the output waveform applies only to output QA' 1076 7-112 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54100, SN74100 8-BIT BISTABLE LATCHES BULLETIN NO. DL-S 7211830, DECEMBER 1972 SN54100 ••• J OR W PACKAGE SN54100 ••• J OR N PACKAGE (TOP VIEW logic FUNCTION TABLE (Each Latch) INPUTS OUTPUTS D G Q Q L H L H H H H L X L 00 00 H = high level, X = Irrelevant 0 0 = the level of 0 before the high-to-Iow transition of G description ENABLE 2G These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Qoutput will follow the data input as long as the enable remains high. When the enable goes low, the information (that was setup at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. These circuits are completely compatible with all popular TTL or DTL families. All inputs are diodeclamped to minimize transmission-line effects and simplify system design. Typical power dissipation is 40 milliwatts per latch. The SN541 00 is characterized for operation over the full military temperature range 0 of _55 to 125°C; the SN74100 is characterized for operation from oOe to 70°C. positive logic: see function table NC-No internal connection functional block diagram (each latch) T:~ ENABLE DATA schematic (each latch) • a I ENABLF DATA Resistor values shown are nominal and in ohms. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . Intermitter voltage (see Note 2) Operating free-air temperature range: SN54100 SN74100 Storage temperature range NOTES: 7V 5.5 V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter input transistor. For this circuit, this rating applies between the enable and D inputs of any latch. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 7-113 TYPES SN54100, SN74100 8-BIT BISTABLE LATCHES REVISED OCTOBER 1976 recommended operating conditions SN54100 MIN Supply voltage, Vee NOM 4.5 SN74100 MAX MIN 5.5 4.75 5 High·level output current, 10H NOM 5 -400 Low·level output current, 10L 16 MAX UNIT 5.25 V -400 /JA 16 rnA Width of enabling pulse, tw 20 20 ns Setup time, tsu 20 20 ns 5 -55 5 Hold time, th Operating free-air temperature, T A 125 ns 70 0 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage Low-level output voltage II Input current at maximum input voltage IIH High-level input current lOS ICC MIN TYPt MAX UNIT V 2 VOL IlL • TEST eONDITIONSt D input G input D input Low-level input current G input Short-circuit output current§ Vee = MIN, II = -12 rnA Vee = MIN, VIH=2V, VIL = 0_8 V, 10H = -400/JA Vee = MIN, VIH = 2 V, VIL = 0.8 V, IOL=16mA Vee= MAX, VI = 5.5 V Vee = MAX, VI=2.4V Vee = MAX, V -1.5 V 3.4 0_2 V 0.4 1 80 320 -3.2 VI=O.4V Vee = MAX Supply current 2.4 0.8 -12.8 SN54100 -20 SN74100 -18 -57 -57 Vee = MAX, SN54100 64 92 See Note 3 SN74100 64 106 V rnA /JA rnA rnA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAil typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time. NOTE 3: ICC is tested with all inputs grounded and all outputs open. switching characteristics, Vee PARAMETER~ tpLH tpHL tpLH tpHL = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) D Q TEST CONDITIONS eL=15pF, RL = 400 G MIN Q n, See Note 4 TYP 16 MAX UNIT 30 14 25 16 30 7 15 ns ns = = ~tpLH propagation delay time, low·to·high-Ievel output tpHL propagation delay time, high-to-Iow·level output NOTE 4: Test circuit and voltage waveforms are the same as those shown for the '75, '77, 'L 75, and 'L 77 on page 7-40. 1076 7-114 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CAL.LAS. TEXAS 75222 TTL TYPES SN54116, SN74116 DUAL 4-81T LATCHES WITH CLEAR MSI BULLETIN NO. DL·S 7211849, DECEMBER 1972 • Two Independent 4-Bit Latches in a Single Package • Separate Clear Inputs Provide One-Step Clearing Operation • Dual Gated Enable Inputs Simplify Cascading and Register Implementations • Compatible for Use with TTL and DTL Circuits • Input Clamping Diodes Simplify System Design SN54116 ••• J OR W PACKAGE SN74116 ••• J OR N PACKAGE (TOP VIEW) ~2 2C2 2el CLEAR description These monolithic TTL circuits utilize Ootype bistables to implement two independent four-bit latches in a single package. Each four-bit latch has an independent asynchronous clear input and a gated two-input enable circuit. When both enable inputs are low, the output levels will follow the data input levels. When either or both of the enable inputs are taken high, the outputs remain at the last levels setup at the inputs prior to the low-to-high-Ievel transition at the enable input(s). After this, the data inputs are locked out. positive logic: see function table functional block diagram (each 4-bit latch) The clear input is overriding and when taken low will reset all four outputs low regardless of the levels of the enable inputs. • The SN54116 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74116 is characterized for operation from O°C to 70°C. FUNCTION TABLE (EACH LATCH) INPUTS CLEAR H = high level, L 0 0 = the level of ENABLE OUTPUT DATA a G1 G2 H L L L L H L L H H H X H X H H X X 00 00 L X X X L = low level, X = Irrelevant a before these input conditions were established. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) _ _ _ . _ . . . Input voltage . . . . . . . . . _ . _ . . . . Operating free-air temperature range: SN54116 Circuits SN74116 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 7-115 TYPES SN54116, SN74116 DUAL 4-81T LATCHES WITH CLEAR recommended operating conditions SN74116 SN54116 MIN Supply voltage, VCC NOM 4.5 MAX MIN 5.5 4.75 5 NOM 5 -800 High-level output current, 10H Low-level output current, 10L 16 Input pulse width, tw Data setup time, ts\,J Enable 18 18 Clear 18 18 High logic level 8 8 Low logic level 14 14 8 8 Clear inactive-state setup time, tsu Data release time, high-level data, trelease Data hold time, low-level data, th 8 5.25 V -800 /lA 16 mA ns ns 2 8 -55 125 UNIT ns 2 Operating free-air temperature, T A MAX 70 0 ns °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER • VIH High-level input voltage VIL VIK Low-level input voltage Input clamp voltage VOH High-level output voltage TYPt MAX UNIT V 2 VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current IlL MIN G1, G2, or clear Any D G1, G2, or clear Any D, initial peak Low-level input current VCC= MIN, II = -12 mA VCC= MIN, VIH = 2 V, VIL = 0.8 V, 10H = -800 /lA VCC= MIN, VIH = 2 V, VIL = 0.8 V, 10L = 16 mA Vee= MAX, VI = 5.5 V VCC VI = 2.4 V = MAX, 2.4 Short-circuit output current§ ICC Supply current V -1.5 V 3.4 0.2 V 0.4 1 40 60 V mA /lA -1.6 VCC = MAX, VI = 0.4 V -2.4 mA -1.6 Any D, steady-state lOS 0.8 Vee= MAX SN54116 -20 -57 SN74116 -18 -57 Vec = MAX, Condition A 60 100 See Note 2 Condition B 40 70 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. tAli typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time. NOTE 2: With outputs open, ICC is measured for the following conditions: A. All inputs grounded. B. All G inputs are grounded and all other inputs are at 4.5 V. switching characteristics, Vee PARAMETER~ tPLH = 5 V, TA =25°e FROM TO (INPUT) (OUTPUT) Enable AnyQ Data Q Clear AnyQ TEST CONDITIONS tpHL tpLH tpHL tpHL MIN TYP MAX UNIT 19 30 CL = 15 pF, 15 22 RL=400n, 10 15 See Figure 1 12 18 15 22 ns ns ns ~ tpLH "" propagation delay time, low-to-high-Ievel output tpH L "" propagation delay time, high-to-Iow-Ievel output 107E 7-116 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54116. SN74116 4-81T LATCH ES WITH CLEAR schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF DATA INPUTS EQUIVALENT OF CLEAR. G1. AND G2 INPUTS VCC V C CReq 3-- VCC1 4 3 k.!1 NOM INPUT -- 'NeUT -- OUTPUT Initial Req = 3 k.!1 NOM Steady-state Req = 6 k.!1 NOM PARAMETER MEASUREMENT INFORMATION VCC LOAD CIRCUIT ~ 15V 1.5 V CLEAR INPUT I· r-- I ~ Iw 3V _________________ OV -.I :: ~Isu \'-------'/~-------- DATA 1'"---.. ., t+- ENABLE (see~~I:~~ _ _...;..._ _ _ _...... 1.5 V 14- I OUTPUT ~ T IPHL 1 5V . v--:-- I 3V r1~V _ ov 14-- IPLH I / --I Iw 1'1.5 V -.I ,.-------. \1.5 V r-- --I ,1.5V I. IPH L-..I - - - -.... I Iw • --.j I ~VOH T~"--VOL \1.5 V SWITCHING TIMES FROM CLEAR AND ENABLE INPUTS 3V DATA INPUT (See Note EI I ENABLE I I'--_ _J (see~~:'UDTI I ~ 14- I,elease , Isu -+j -i!i-___-:. ~___ _ _ _ _ _ _ _...Jf1.5V __ : . . Isu -+J I+- Ih .,j 3V ~ ov I IPLH~ I4-IPHL1 OUTPuT_ _ _ _...J11.5 V \'-1_.5_V_ _ _- . . / SWITCHING TIMES FROM DATA INPUTS NOTES: A. Input pulses are supplied by generators having the following characteristics: tr';; 10 ns. tf';; 10 ns. PRR Zout'" 50 .11_ B. CL includes probe and jig capacitance. C. All diodes are 1 N3064_ D. The other enable input is low. E. Clear input is high. =1 MHz. duty cycle';; 50%, FIGURE 1 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-117 TTL MSI TYPES SN54120, SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS BULLETIN NO. DL-S 7211537, SEPTEMBER 1971-REVISED DECEMBER 1972 • Generates Either a Single Pulse or Train of Pulses Synchronized with Control Functions • Ideal for Implementing Sync-Control Circuits Similar to those Used in Oscilloscopes • Latched Operation Ensures that Output Pulses Are Not Clipped • High-Fan-Out Complementary Outputs Drive System Clock Lines Directly • Internal Input Pull-Up Resistors Eliminate Need for External Components • Diode-Clamped Inputs Simplify System Design • Typical Propagation Delays: SN54120 ••• J ORW PACKAGE SN74120 ••• J OR N PACKAGE (TOP VIEW) INPUTS 1\ V INPUTS 9 Nanoseconds through One Level 16 Nanoseconds through Two Levels logic: see description and function table description These monolithic pulse synchronizers are designed to synchronize an asynchronous or manual signal with a system clock. Reliable response is ensured as the input signals are latched up; therefore duration of logic input is not critical and the adverse effects of contact-bounce of a manual input are eliminated. The ability to pass output pulses is started and stopped by the levels or pulses applied to the latch inputs 81, 82, or R in accordance with the function table. High-speed circuitry is utilized throughout the clock paths to minimize skew with respect to the system clock. • After initiation, the mode control (M) input determines whether a series of pulses or only one pulse is passed. In the absence of a stop command, the clock driver will continue to pass clock pulses as long as the mode control input is low (see Figures 2 through 4). If the mode ~ontrol input is high only a single clock pulse will be passed (see Figure 5). When the mode control is set to pass a series of pulses, the last pulse out is determined by two general rules: a. When pulses are terminated by the S or R inputs, conditions meeting the setup times (specified under recommended operating conditions) will dominate. FUNCTION TABLE INPUTS FUNCTION R S1 S2 X X L X Pass Output Pulses X L Pass Output Pulses L H H Inhibit Output Pulses H ~ H Start Output Pulses H H ~ Start Output Pulses ~ H H Stop Output Pulses H H H Continue t H = high level (steady state) L = low level (steady state) ~ = transition from H to L X = irrelevant tOperation initiated by last ~ transition continues. b. Low-to-high-Ievel transitions at the mode control input should be avoided during the 20-nanosecond period immediately following the negative transition of the input clock pulse as transitions during this time period mayor may not allow the next pulse to pass (see Figures 4 and 5). When pulses are terminated by th~ mode control input, a positive transition at the mode control input meeting the high-level setup time, tsu (H), (specified under recommended operating conditions) will pass that positive clock pulse then inhibit remaining clock pulses. The clock input (e) is latch-controlled ensuring that once initiated the output pulse will not be terminated until the full pulse has been passed. 1076 7-118 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54120, SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS 'description (continued) This clock driver circuit is entirely compatible for use with either digital logic circuits or mechanical switches for input controls since all inputs, except the clock, have internal pull-up resistors. This eliminates the requirement to supply an external resistor to prevent the input from floating when the control switch is open. The internal resistor also means that these inputs may be left disconnected if unused. Typical propagation delay time is 9 nanoseconds to the Y output and 16 nanoseconds to the Y output from the clock input. The outputs will drive 60 Series 54/74 loads at a high logic level and 30 loads at a low logic level. Typical power dissipation is 127 milliwatts per driver. The SN54120 is characterized for operation from -55°C to 125°C; the SN74120 is characterized for operation from O°C to 70°C. functional block diagram (each driver) SI S2 INPUTS :}OUT~~ C M • schematics of inputs and outputs EQUIVALENT OF EACH C INPUT Vee - - - + - - - - EQUIVALENT OF EACH M, R, OR S INPUT Vee~~-+---- TYPICAL OF ALL OUTPUTS - - - - -.....- - Vee 15 kn NOM INPUT INPUT L..-_'-__ OUTPUT 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·119 TYPES SN54120. SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) Input voltage . . . . . . . . . I nteremitter voltage (see Note 2) Operating free-air temperature range: SN54120 Circuits SN74120 Circuits Storage temperature range . . . . 7V 5.5 V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the S1 and S2 inputs. recommended operating conditions SN54120 MIN MAX MIN NOM 5 5.5 4.75 5 4.5 Supply voltage, Vee SN74120 NOM High-level output current, IOH V -2.4 rnA 48 48 rnA 12 12 tsu(H or Ll Setup time (see Figures 2 thru 5) Mode control II tsu(H) tsu(Ll Any input except mode control, 0 0 12 12 3 3 20 20 th(H or L) Hold time (see Figures 3 and 5) Mode control, th(H or L) Operating free-air temperature, T A UNIT -2.4 Low-level output current, IOL Any input except mode control, MAX 5.25 -55 125 ns ns 0 °e 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER • VIH High-level input voltage VIL Low-level input voltage VIK I nput clamp voltage VOH VOL MIN TYP+ MAX 2 H.igh·level output voltage Vee - MIN, 11- -12 mA Vee- MIN, VIH - 2 V, VIL LOW-level output voltage = 0.8 V, VIL = 0.8 V, 10L = 48 rnA II I nput current at max imum input voltage High-level input current IlL Low-level input current lOS Short-circuit output current§ Vee = MAX lee Supply current Vee= MAX, Other inputs Clock input Other inputs = -2.4 rnA VIH = 2 V, IIH elock input 10H Vee= MIN, Vee = MAX, VI = 5.5 V Vee= MAX, VI = 2.4 V Vee= MAX, VI = 0.4 V 2.4 V 0.8 V -1.5 V 3.4 0.2 V 0.4 1 -0.12 -0.2 rnA /-LA -0.36 rnA -2.1 -35 V 80 -3.2 See Note 3 UNIT rnA -90 rnA 51 90 rnA TYP MAX 14 22 17 25 10 16 8 13 t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions_ +AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time. NOTE 3: lec is measured with ground applied to all inputs except R which is at 4.5 V and all outputs open. switching characteristics, Vee PARAMETER~ tPLH = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) e TEST eONDITIONl:i Y tPHL tPLH eL = 45 pF, RL = 133 y e See Figure 1 tPHL ~ tpLH tpH L == Propagation == Propagation n, MIN UNIT ns ns delay time, low-to-high-Ievel output delay time, high-to-Iow-Ievel output 1076 7·120 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54120, SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS PARAMETER MEASUREMENT INFORMATION t VCC OUTPUT FROM OUTPUT UNDERTEST NOTES: RL rl'1 ~ = 133 51 ~ ~ A. The clock input pulse in figures 2 through 5 is supplied by a generator having the following characteristics: tw(clock);;' 15 ns, PRR '" 1 MHz, and Zout"" 50 51. B. CL includes probe and jig capacitance. C. All diodes are 1 N3064. CL =45pF FIGURE 1-LOAD CIRCUIT FOR SWITCHING TESTS tw(cIOCk)--\..----~---~ CLOCK INPUT I OV ~tsu(H) 3V !1.5V '---=I---.....;...---------J (See Note) - --- - - - -- OV tPHL--! I ,----------------VOH '(OUTPUT VOH Y OUTPUT ' -_____________ VOL NOTE: Mode control and R Inputs are low unused S input is high. FIGURE 2-INITIATING AND TERMINATING PULSE TRAIN FROM S INPUTS • CLOCK INPUT I ~tsu(L) tn(U 1.5V INPUT I II ~ S1orS2 OV I a-.... I 3V I 1.5 V I -:----4 - - - - - - - - - - - _ _ _ _ _ _ 1_ _ _ _ _ - tsu(L) ----------------------------------~ OV thlu I 3V R INPUT _---------------- VOH '{OUTPUT - - - - - - - - - - . VOL NOTE: Mode control input is low and unused S input is high. FIGURE 3-INITIATING PULSE TRAIN FROM S AND TERMINATING WITH R INPUTS 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-121 TYPES SN54120. SN74120 DUAL PULSE SYNCHRONIZERS/DRIVERS PARAMETER MEASUREMENT INFORMATION CLOCK INPUT "'1'-1----1* MODE CONTROL INPUT OV t s u ( L ) I....I----I*" tsu(H) ~~.5__ V __________________ --J~'1.-5-~-_--_-_-_--_-_--_-_-_--_-_--_-_-_--_--_ 3V OV \-----.J/ ~------------- Y OUTPUT VOH VOL NOTE: At least one of the S inputs is low. FIGURE 4-INITIATING AND TERMINATING PULSE TRAIN WITH MODE CONTROL INPUT • CLOCK INPUT I I I OV \4- th(L)~ tsu(H) ~ _ 3V f·5V! MODE CONTROL INPUT ;j - - - OV ~~~_V 3V --------+-----th-(-H-)- - - S1 or S2 -r - - - - - -- -- - - - - - - - - - - - I. __ ~_t~(~) __________________ _ ________________________________ INPUT OV ~~~----------- ? OUTPUT VOH VOL NOTE: Input R is low and the unused S input is high. FIGURE 5-ENABLING SINGLE PULSE 107 7·122 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S124, SN74S124 DUAL VOLTAGE-CONTROLLED OSCILLATORS TTL MSI BULLETIN NO. DL·S 12025, MARCH 1974-REVISED DECEMBER 1980 SN54S124 ... J OR • Two Independent VCO's in a 16-Pin Package • Output Frequency Set by Single External Component: Crystal for High-Stability Fixed-Frequency Operation Capacitor for Fixed- or Variable-Frequency Operation • Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Output Circuitry • Highly Stable Operation over Specified Temperature and/or Supply Voltage Ranges • Typical f max .................. 85 MHz Typical Power Dissipation ........ 525 mW • Frequency Spectrum ... 1 Hz to 60 MHz PACKAGE SN74S124 .•• J OR N PACKAGE (TOP VIEW) logic: While the enable input is low, the output is enabled. While the enable input is high, the output is high. description The 'S124 features two independent voltage-controlled oscillators (VCO) in a single monolithic chip. The output frequency of each VCO is established by a single external component, either a capacitor or a crystal, in combination with two voltage-sensitive inputs, one for frequency range and one for frequency control. These inputs can be used to vary the output frequency as shown under typical characteristics. These highly stable oscillators can be set to operate at any frequency typically between 0.12 hertz and 85 megahertz. Under the conditions used in Figure 3, the output frequency can be approximated as follows: a fo = 5 X 10-4 Cext where: fo = output frequency in hertz I Cext = external capacitance in farads. These devices can operate from a single 5-volt supply. However, one set of supply·voltage and ground pins (VCC and GND) is provided for the enable, synchronization-gating, and output sections, and a separate set eVCC and GND) is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. e The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal oscillator of the 'S124 is started and stopped by the enable input. The enable input is one standard load; it and the buffered output operate at standard Schottky-clamped TTL levels. The pulse synchronization·gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle of the square-wave output is fixed at approximately 50 percent. The SN54S124 is characterized for operation over the full military temperature range of _55°C to 125°C; the SN74S124 is characterized for operation from O°C to 70°C. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7·123 TYPES SN54S124, SN74S124 DUAL VOLTAGE-CONTROLLED OSCILLATORS schematics of inputs and outputs EaUIVALENT OF EACH ENABLE INPUT Vce---------.-------- EaUIVALENT OF EACH FREQUENCY CONTROL OR RANGE INPUT Vee------------4----- TYPICAL OF BOTH OUTPUTS -------+----- Vee 114 n NOM INPUT INPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (See Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free·air temperature range: SN54S124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C SN74S124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70°C Storage tem peratu re range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65° e to 150° e • NOTES: 1. Voltage values are with respect to the appropriate ground terminal. 2. Throughout this data sheet, the symbol Vee is used for the voltage applied to both the Vee and8vee terminals, unless other· wise noted. 128( 7·124 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS124, SN74LS124 DUAL VOLTAGE-CONTROLLED OSCILLATORS The SN54LS124 and SN74LS124 have been replaced by the SN54LS629 and SN74LS629. See 1981 Supplement to the TTL Data Book for Design Engineers, Second Edition. • I 1280 TEXAS INSTRUMENTS INCORPO~ATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-125 TYPES SN54S124, SN74S124 DUAL VOLTAGE-CONTROLLED OSCILLATORS recommended operating conditions SN54S124 MIN Supply voltage, Vee (see Note 1) SN74S124 MAX MIN NOM MAX 5 5.5 4.75 5 5.25 V 5 1 5 V 4.5 1 Input voltage at frequency control or range input, VI (freq) or VI (rng) UNIT NOM High-level output current, 10H -1 -1 mA Low-level output current, 10L 20 20 mA 60 MHz 70 °c 1 Output frequency (enabled), fo Hz 1 60 Operating free-air temperature, T A -55 125 0 NOTE 1: Throughout this data sheet, the symbol V CC is used for the voltage applied to both pins 15 and 16. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage at enable VIL Low-level input voltage at enable VIK Input clamp voltage at enable TEST CONDITIONSt II Vee = MIN, 11=-18mA Vee - MIN, VIH = 2 V, l SN54S' I SN74S' IOH = -1 mA Vee= MIN, Low-level output voltage Input current MAX or range 2.5 3.4 2_7 3.4 VIL = 0.8 V, 0.8 V -1.2 V V 0.5 l VI - Vee = MAX 5 V UNIT V IOL = 20mA Freq control I nput current at 10 50 1 15 1 VI-l V V JlA Enable Vee = MAX, VI = 5.5 V 1 IIH High-level input current Enable Vee - MAX, VI = 2.7 V 50 JlA IlL Low-level input current Enable Vee - MAX, VI - 0.5 V -2 mA lOS Short-circuit output current§ -100 mA II • TYP+ 2 VOH High-level output voltage VOL MIN maximum input voltage lee -40 Vee - MAX Vee= MAX, See Note 2 Supply current, total into Vee pins 15and 16 = MAX, TA=125°C, See Note 2 105 I W package only mA 150 110 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25°C. §Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured with the outputs disabled and open. switching characteristics, Vee = 5 V, RL = 280 n, eL = 15 pF, TA = 25°e PARAMETER fo tPHL TEST CONDITIONS MIN l Vl(freq) = 4 V, VI(rng) = 1 V 60 1 V, VI(rng) = 5 V 25 Output frequency eext = 2 pF Output duty cycle eext - 8.3 pF to 500 JlF Propagation delay time, fo = 1 Hz to 20 MHz I VI(freq) - high-to-Iow-Ievel output from enable fo> 20 MHz TYP 85 40 MAX UNIT MHz 50% 1.4 fo(Hz) 70 s ns 1071 7·126 TEXAS INCOHPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S124, SN74S124 DUAL VOLTAGE-CONTROLLED OSCILLATORS TYPICAL APPLICATION DATA free-running oscillator Free-running oscillators can be implemented for most systems by setting the output frequency of the veo with either a capacitor or a crystal. If excitation is provided with a capacitor the frequency control and/or range inputs can be used to vary the output frequency. When the 'S124 is excited with a crystal, low-frequency response (';;;; 1 MHz) can be improved if a relatively smaIJ capacitor (5 to 15 pF) is paraIJeled with the crystal. When operated at the fundamental frequency of a crystal, the frequency control input should be high (~ 5 V) and the range input should be low (grounded) for maximum stability over temperature and supply voltage variations. phase-locked loops A basic crystal-controlJed phase-locked loop is illustrated in Figure 1. This application can be used for implementation of: a. A highly stable fixed-frequency clock generator. b. A highly stable fixed- or variable-frequency synthesizer. c. A highly efficient "slave-clock" system for synchronizing off-card, remote, or data-interfacing clock systems N With fixed division rates for both M and N, the output frequency (fol wiIJ be stable at fo = 'fiji fl. Obviously, either M or N, or both, could be programmable counters in which case the output frequency (fo) wiIJ be a variable frequency dependent on the instantaneous value ofij-f1' The crystal-controlled veo can be operated up to 60 MHz with an accuracy that is dependent on the crystal. At the higher frequencies, response of the phase comparator can become a limiting factor and one of the folJowing approaches may be necessary to extend the operating frequency range. if a_ Frequencies ttand can be divided equally by the same constant (K) also shown in Figure 1. The constant can be any value greater than unity (K> 1), and should be selected to yield frequency ranges that can be handled adequately by the phase-comparator and filter. The output frequency (fo) retains the same relationship as previously explained because now: • I fo = ~ KM it * f1 = l:! f1 M and can be performed with either an SN54LS85/SN74LS85 or b. In another method, the comparison of SN54S85/SN74S85. The resultant A> B and A < B outputs from the 'LS85 or 'S85 permit the detector to be simplified to a charge-pump circuit_ See Figure 2. 280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-127 TYPES SN 54S124, SN74S124 DUAL VOLTAGE-CONTROLLED OSCILLATORS TYPICAL APPLICATION DATA FIGURE 2-HIGH·FREQUENCY PHASE·LOCKED LOOP I AGURE 1-PHASE·LOCKED LOOP TYPICAL CHARACTERISTICS BASE OUTPUT FREQUENCY • NORMALIZED OUTPUT FREQUENCY vs vs EXTERNAL CAPACITANCE INPUT VOLTAGE 1.2 1G N 100M J: I > u c: Q) ::I cQ) 10M --~ '" 1M U:: 100 k ....::I e VCC = 5 V VI(freql=VI(rngl=2V TA=25°C _ 10 k ~ co CD I ~ co ..c Q) ~ LL ~ ....::I e I'\. ::I 0 "f\.- 1k "0 Q) .~ '\ '" 100 10 ;§ 0.1 10- 12 10- 10 1.1 c: ::I C- ::I 0 > 0 10- 8 10- 6 ~ 0 z "'1'\ I .:=- "I\. '" 10-4 10-2 VI(freql-lnput Voltage-V Cext-External Capacitance-F FIGURE 4 AGURE3 NOTE: fa = fn X fo(base). 128 7·128 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54S135, SN74S135 QUADRUPLE EXCLUSIVE-OR/NOR GATES TTL MSI BULLETIN NO. DL-S 7211826. DECEMBER 1972 SN54S135 ••• J OR W PACKAGE SN74S135 •.• J OR N PACKAGE (TOP VIEW) • Fully Compatible with Most TTL and TTL MSI Circuits • Fully Schottky Clamping Reduces Delay Times ... 8 ns Typical • Can Operate as Exclusive-OR Gate (C Input Low) or as Exclusive-NOR Gate (C Input High) FUNCTION TABLE OUTPUT INPUTS H Y A B C L L L L L H L H H L L H H H L L L L H H L L H H H L H L H H H H = high 1A 11;1 1Y positive logic: Y 1C.2C 2A 2B 2Y GND = (A(±)B)(±)C = ABC + ABC + ABC + ABC level. L = low level schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ----------.---VCC VCC--------~~-------- a 2.8 kn NOM I INPUT OUTPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. Vee (see Note 1) . . . . . . Input voltage . . : . . . . . . . . . . . Operating free-air temperature range: SN54S135 SN74S135 Storage temperature range . . . . . . . . . 7V 5.5 V -55°C to 125°C .. oOe to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-129 TYPES SN54S135, SN74S135 QUADRUPLE EXCLUSIVE-OR/NOR GATES recommended operating conditions SN54S135 MIN Supply voltage, Vee NOM 4.5 SN74S135 MAX MIN 5.5 4.75 5 High-level output current, 10H NOM 5 -1 Low-level output current, 10L 20 Operating free-air temperature, T A -55 125 0 MAX UNIT 5.25 V -1 mA 20 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage Vee = MAX, VI = 5.5 V IIH High-level input current Vee = MAX, VI = 2.7 V 50 IlA IlL Low-level input current Vee = MAX, VI =0.5V -2 mA lOS Short-circuit output current§ Vee= MAX -100 mA ICC Supply current Vee= MAX, See Note 2 99 mA V 2 Vee= MIN, II = -18 mA Vee = MIN, VIH=2V, VIL = 0.8 V, 10H = -1 mA Vee= MIN, VIH=2V, VIL = 0.8 V, 10L = 20mA l SN54S' I SN74S' 2.5 3.4 2.7 3.4 0.8 V -1.2 V V 0.5 1 -40 65 V mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with the inputs grounded and the outputs open. switching characteristics, Vee • PARAMETER~ tPLH tpHL tpLH tpHL tpLH = 5 V, TA = 25°e FROM TEST CONDITIONS (INPUT) A or B BorA = L, e = L A orB BorA = H, e = L Aor B B or A = L, e = H tPHL tpLH tpHL tpLH tpHL tpLH tpHL MIN eL= 15pF, RL = 280 AorB BorA = H, e = H A=B e A ;6B e n, See Note 3 TYP MAX UNIT 8.5 13 11 15 8 12 9 13.5 10 15 6.5 10 8.5 12 7 11 8 12 9.5 14.5 7.5 11.5 8 12 ns ns ns ns ns ns ~ tpLH '" propagation delay time, low-to-high-Ievel output tpH L '" propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-130 TEXAS)NSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54136, SN54LS136, SN74136, SN74LS136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS TTL MSI BULLETIN NO. DL-S 7611827, DECEMBER 1972-REVISED OCTOBER 1976 SN54136, SN54LS136 ••• J OR W PACKAGE SN74136, SN74LS136 ••• J OR N PACKAGE (TOP VIEW) VCC 48 4A 4V 38 3A 3V 1A 18 1V 2A 28 2Y GND FUNCTION TABLE INPUTS OUTPUT A B L L L L H H H L H H H L V H = high level, L = low level positive logic: V = A(f)B = AB + AS schematics of inputs and outputs EQUIVALENT OF EACH INPUT OF'136 TYPICAL OF ALL OUTPUTS OF '136 Vcc---+-_ _ ~OUT>UT INPUT • I EQUIVALENT OF EACH INPUT OF'LS136 TYPICAL OF ALL OUTPUTS OF'LS136 VCC 12.5 kn NOM INPUT _ _ ~OU"UT n.o ...... ~~ V ~, "'7 1076 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·131 TYPES SN54136, SN14136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54136 SN74136 Storage temperature range 7V 5.5 V -55°e to 125°e oOe to 700e -65°e to 150°0 NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54136 MIN NOM 4.5 Supply voltage, Vee 5 SN74136 MAX MIN 5.5 4.75 NOM 5 MAX UNIT V 5.25 High-level output voltage, VOH 5.5 5.5 V Low-level output current, IOL 16 16 mA 70 e Operating free-air temperature, T A -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH • TEST CONDITIONS·t MIN TVP* MAX UNIT V 2 High-level output current Vee = MIN, II = -8 mA Vee= MIN, VIH=2V, VIL = 0.8 V, VOH = 5.5 V Vee = MIN, VIH=2V, 0.8 V -1.5 V 250 IJ.A 0.4 V VOL Low-level output voltage VIL = 0.8 V, IOL = 16 mA II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 IIH High-level input current Vee = MAX, VI = 2.4 V 40 IJ.A IlL Low-level input current Vee = MAX, VI=O.4V -1.6 mA lee Supply current, high-level output Vee= MAX, See Note 2 0.2 I SN54136 ISN74136 30 43 30 50 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. *AII typical values are at Vee = 5 V, TA = 25°C. NOTE 2: ICC is measured with one input of each gate at 4_5 V, the other inputs grounded, and the outputs open. switching characteristics, Vee PARAMETER~ tpLH =5 V, TA = 25°e FROM (INPUT) TEST CONDITIONS A or B Other input low CL=15pF, RL = 400 n, A orB Other input high See Note 3 tpHL tpLH tPHL MIN TVP MAX UNIT 12 18 39 50 14 22 42 55 ns ns ~tpLH := propagation delay time, low-to-high-Ievel output tpH L:= propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10._ 107 7-132 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS136, SN74LS136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Su pply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS136 SN74LS136 Storage temperature range 7V 7V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS136 MIN 4.5 Supply voltage, Vee NOM SN74LS136 MAX MIN 5.5 4.75 5 NOM 5 MAX V 5.5 V 5.5 High·level output voltage, VOH 4 Low·level output current, IOL 125 -55 Operating free-air temperature, T A UNIT 5.25 0 8 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH SN74LS136 SN54LS136 TEST CONDITIONSt PARAMETER MIN TYP+ MAX High-level output current II = -18mA Vee= MIN, VIH - 2V, TYP+ MAX 2 2 Vee= MIN, MIN UNIT V 0.7 0.8 V -1.5 -1.5 V 100 100 /-LA VIL = VIL max, VOH = 5.5 V Vee= MIN, IIOL=4mA VIH = 2 V, VIL=VILmaxI I OL=8mA VOL Low-level output voltage 0.25 0.4 0.25 0.4 0.35 0.5 V II Input current at maximum input voltage Vee = MAX, VI = 7V 0.2 0.2 IIH High·level input current Vee = MAX, VI = 2.7 V 40 40 /-LA IlL Low·level input current Vee = MAX, VI=0.4V -0.8 -0.8 mA lee Supply current Vee = MAX, See Note 2 10 mA 6.1 6.1 10 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for th~ applicable type. +AII typical values are at VCC = 5 V, T A = 25°C. NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open. switching characteristics, Vee PARAMETER~ tpLH = 5 V, TA = 25°e FROM TEST CONDITIONS (INPUT) Other input low A or B tpHL tpLH a eL=15pF, RL = 2 kn, A or B Other input high tpHL See Note 4 MIN TYP MAX UNIT 18 30 18 30 18 30 18 30 ns ns ~ tpLH = propagation delay time, low·to·high·level output tpH L propagation delay time, high·to·low·level output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. = 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-133 TYPES SN54LS138, SN54LS139. SN54S138, 8N54S139, SN74LS138, SN74LS139. SN74S138. SN74S139 DECO DERS/DEMU LTIPLEXERS TTL MSI BULLETIN NO. DL-S 7611804, DECEMBER 1972-REVISED OCTOBER 1976 • Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems • 'S138 and 'LS138 3-to-8-Line Decoders Incorporate 3 Enable Inputs to Simplify Cascading and!or Data Reception SN54LS138, SN54S138 ••• J OR W PACKAGE SN74LS138, SN74S138 ••• J OR N PACKAGE (TOP VIEW) DATA OUTPUTS r -________ • 'S139 and 'LS139 Contain Two Fully Independent 2-to-4-Line Decoders! Demultiplexers • Schottky Clamped for High Performance TYPICAL TYPE PROPAGATION DELAY (3 LEVELS OF LOGIC) 'LS138 'S138 ~A~ __________ TYPICAL POWER DISSIPATION 22 ns 32mW 8 ns 245mW 'LS139 22 ns 34mW 'S139 7.5 ns 300mW positive logic: see function table description • These Schottky-clamped TTL MSI circuits are designed to be used in high·performance memorydecoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fastenable circuit the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. SN54LS139, SN54S139 ••• J OR W PACKAGE SN74LS139, SN74S139 ••• J OR N PACKAGE (TOP VIEW) The 'LS138 and 'S138 decode one-of-eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. EN!~LE~ ~ SE LEeT GND DATA OUTPUTS positive logic: see function table The 'LS139 and 'S139 comprise two individual two-line-to-four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs each of which represents only one normalized Series 54LS/74LS load ('LS138, 'LS139) or one normalized Series 54S/74S load ('S138, 'S139) to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. Series 54LS and 54S devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74LS and 74S devices are characterized for O°C to 70."C industrial systems. ~07€ 7·134 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS138, SN54S138, SN54LS139, SN54S139 SN74LS138, SN74S138, SN74LS139, SN74S139 DECODERS/DEMULTIPLEXERS functional block diagrams and logic 'LS138, 'S138 FUNCTION TABLE 'LS138, 'S138 INPUTS ENABLE DATA OUTPUTS OUTPUTS SELECT YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2* C B A X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H H H H H H H H H L L H L H L H L H H H H H L L H H H H H L H H H H H L H L H H H H H H L H L H H H H L H H H L H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L 'G2 = G2A + G2B H = high level. L = low level, X = irrelevant \I I 'LS139, 'S139 f:-~ I 'LS139,'S139 (EACH DECODER/DEMULTIPLEXER) FUNCTION TABLE INPUTS ENABLE DATA B OUTPUTS H L H OUTPUTS SELECT G A YO Yl Y2 Y3 X X H H H H L L H H H L L H L H L H H L H L H H L H L H H H H H L level, L = low = high level, X = irrelevant • schematics of inputs and outputs EaUIVALEfNT OF EACH INPUT OF 'LS138, 'LS139 vcc----.. .-- 20 kS1 NOM I N PUT ~r.+lIl-+--.- TYPICAL OF OUTPUTS OF 'LS138, 'LS139 EaUIVALENT OF EACH INPUT OF 'S138, 'S139 ------vcc vcc=a-- TYPICAL OF OUTPUTS OF 'S138, 'S139 -----vcc 2.8 kS1 NOM INPUT -- 1..-4-- OUTPUT OUTPUT 1272 TEXAS INCORPORATED INSTRUMENTS' POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-135 TYPES SN54LS138, SN54LS139, SN74LS138, SN74LS139, DEC 0 DE RS/ DE M ULT I PLEXERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) Input voltage . . . . . . . . . . . . . . . . . . . . . . . Operating free·air temperature range: SN54LS138, SN54LS139 Circuits SN74LS138, SN74LS139 Circuits Storage temperature range 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS138 SN74LS138 SN74LS139 SN54LS139 NOM MIN 4.5 Supply voltage, Vee 5 MAX MIN NOM 5.5 4.75 5 -400 High-level output current, IOH UNIT MAX 5.25 V -400 jJ.A 8 mA 70 °e 4 Low-level output current, 10L 125 -55 Operating free·air temperature, T A 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS138 TEST eONDITIONSt PARAMETER MIN VIH High·level input voltage Low·level input voltage Input clamp voltage Vee = MIN. II = -18mA Vee = MIN, VIH = 2 V, 2 V VIH = 2 V, Input current at maximum input voltage 0.8 -1.5 2.5 VIL = VIL max, 10H = -400 jJ.A Vee = MIN, 3.4 0.25 10L =4 mA -1.5 2.7 0.4 10L = 8mA VIL = VIL max Vee = MAX, VI = 7V 0.25 0.4 0.35 0.5 0.1 0.1 High-level input current Vee= MAX, VI = 2.7 V 20 20 IlL Low·level input current Vee = MAX, VI = 0.4 V -0,4 -0,4 lOS Short circuit output current § Vee=MAX lOS Supply current 'LS138 -20 'LS139 ~ -100 -20 -40 Vee = MAX, 'LS138 6.3 Outputs enabled and open 'LS139 6.8 -100 -5 V V V 3.4 IIH V mA IlA mA rnA -42 10 6.3 10 11 6.8 11 rnA tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. :j: All typical values are at Vee = 5 V, T A = 25° C. tiNot more than one output should be shorted at a time. switching characteristics, Vee PARAMETER~ = 5 V, TA =25°e FROM TO LEVELS (INPUT) (OUTPUT) OF DELAY tpLH tpHL Binary tpLH Select 3 tpLH eL=15pF, RL = 2 kU, 2 Enable See Note 2 Any 3 tpHL ~tpLH SN54LS138 SN54LS139 SN74LS138 SN74LS139 MIN Any tpLH tPHL TEST CONDITIONS 2 tpHL TYP MAX MIN TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYP UNIT MAX 13 20 13 20 ns 27 41 22 33 ns 18 27 18 29 ns 26 39 25 38 ns 12 18 16 24 ns 21 32 21 32 ns 17 26 ns 25 38 ns =propagation delay time. low·to·high·level output; tpHL =propagation delay time. high·to·low-Ievel output. NOTE 2: Load circuits and waveforms are shown on page 3-11. 7-136 UNIT TYP:j: MAX 0.7 VOL Low-level output voltage • MIN 2 VOH High·level output voltage II SN74LS139 TYP:j: MAX VIL VIK SN74LS138 SN54LS139 TYPES SN54S138, SN54S139, SN74S138, SN74S139 DECODERS/DEMULTIPLEXERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ............. . Input voltage . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54S138, SN54S139 Circuits SN74S138, SN74S139 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C DoC to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S138 SN74S138 MIN NOM 4_5 Supply voltage, Vee MAX MIN 5.5 4.75 5 High-level output current, 10H NOM 5 -1 Low-level output current, 10L 20 Operating free-air temperature, T A -55 UNIT SN74S139 SN54S139 125 0 MAX 5.25 V -1 rnA 20 rnA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST eONDITIONSt SN54S138 SN54S139 SN74S138 SN74S139 UNIT MIN TYP:j: MAX MIN TYP:j: MAX VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage 2 VOH High-level output voltage VOL Low-level output voltage Vee = MIN, II = -18mA Vee = MIN, VIH = 2 V, VIL = 0.8 V, I 10H = -1 rnA I Vee = MIN, VIH = 2 V, VIL = 0.8 V, 10L = 20mA II Input current at maximum input voltage Vee = MAX, VI = 5.5 V V 2 0.8 0.8 V -1.2 -1.2 V SN54S' 2.5 3.4 2.5 3.4 SN74S' 2.7 3.4 2.7 3.4 V 0.5 0.5 1 1 V rnA IIH High-level input current Vee = MAX, VI = 2.7 V 50 50 JlA IlL Low-level input current Vee = MAX, VI = 0.5 V -2 -2 rnA lOS Short-circuit output current§ Vee = MAX -100 rnA lee Supply current Vee = MAX, 90 rnA -40 Outputs enabled and open -100 -40 49 74 60 t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. fAil typical values are at V CC = 5 V, T A = 25" C. ~Not more than one output should be shorted at a time, and duration of the short-circuit test should not exceed one second. switching characteristics, Vee PARAMETER'I = 5 V, TA = 25°e FROM TO LEVELS TEST (INPUT) (OUTPUT) OF DELAY CONDITIONS tPLH tpHL Binary tPLH select 2 Any 3 tpHL eL=15pF, RL = 280 tpLH tpHL 2 Enable n, See Note 3 Any tPLH 3 tpHL ~ tpLH tpH L == propagation delay == propagation delay • SN54S138, SN54S139 SN74S138 SN74S139 MIN TYP MAX MIN UNIT TYP MAX 4.5 7 5 7 10.5 6.5 7.5 10 7.5 12 7 12 8 12 8 12 5 8 5 8 7 11 6.5 10 7 11 7 11 ns ns ns ns time, low-to-high-Ievel output time, high-to-Iow-Ievel output NOTE 3: Load circuits and waveforms are shown on page 3-10. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-137 TTL MSI TYPE SN74141 BCD-TO-DECIMAL DECODER/DRIVER BULLETIN NO. DL-S 7211801, DECEMBER 1972 • Drives gas-filled cold-cathode indicator tubes directly • Fully decoded inputs ensure all outputs are off for invalid codes • Input clamping diodes minimize transmission-line effects J OR N PACKAGE (TOP VIEW) FUNCTION TABLE INPUT OUTPUTS OUTPUT o C B A ONt L L L L 0 L L L H 1 L L H L 2 L L H H L H L L L H L H 3 4 5 L H H L 6 L H H H 7 8 9 H L L L H L L H H L H L NONE H L H H NONE H H L L NONE H H L H NONE H H H L NONE H H H H NONE o 1 5 4 GND ~ ~ Vee OUTPUTS INPUTS ~ 6 7 3 B C ~ 2 OUTPUT positive logic: see truth table functional block diagram H = high level. L = low level t All other outputs are off • OUTPUTS ,..----.I'-,. A (3) (16) 0 description (15) 1 The SN74141 is a second-generation BCD-to-decimal decoder designed specifically to drive cold-cathode indicator tubes. This decoder demonstrates an improved capability to minimize switching transients in order to maintain a stable display. B Full decoding is provided for all possible input states. For binary inputs 10 through 15, all the outputs are off. Therefore the SN74141, combined with a minimum of external circuitry, can use these invalid codes in blanking leading- and/or trailing-edge zeros in a display. The ten high-performance, n-p-n output transistors have a maximum reverse current of 50 microamperes at 55 volts. (8) 2 (9) 3 (11) 6 (6) C (7) Low-forward-impedance diodes are also provided for each input to clamp negative-voltage transitions in order to minimize transmission-line effects. Power dissipation is typically 80 milliwatts. The SN74141 is characterized for operation over the temperature range of 0° C to 70° C. ~7 D (4) 1076 7-138 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPE SN74141 BCD-TO-DECIMAL DECODER/DRIVER absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, vee (see Note 1) Input voltage . . . . . . . . Current into any output (off-state) Operating free-air temperature range Storage temperature range 7V 5.5V 2mA oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, Vee . . . . . Off-state output voltage Operating free·air temperature, T A MIN 4.75 . NOM 5 o MAX UNIT 5.25 V 60 V 70°C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage TEST CONDITIONSt Input clamp voltage Vec; MIN, II; -5 mA VO(on) On-state output voltage Vee; MIN, 10; 7 mA Off-state output voltage IOloft) 1010ft) TYP+ MAX 2 VIK VO(off) MIN Vce; MAX, 10; 0.5mA for input counts 0 thru 9 V 0.8 V -1.5 V 2.5 V 50 fJ.A 60 V Off-state reverse current Vee; MAX, Va; 55 V Off-state reverse current Vee = MAX" TA = 55°C 5 for input counts 10 thru 15 ,TA -70 C Va'" 30 V Vcc; MAX, VI ;5.5V 15 II Input current at maximum input voltage IIH High-level input current IlL Low-level input current ICC Supply current A input B, e, or D input A input B, e, or D input 1 40 Vee; MAX, VI; 2.4 V 80 -1.6 Vee; MAX, VI;O.4V -3.2 Vee; MAX, See Note 2 UNIT 16 25 fJ.A mA fJ.A • I mA mA I t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +This typical value is at V CC =5 V. T A = 25° C. NOTE 2: ICC is measured with all inputs grounded and outputs open. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC---------G~--------- ---",-OUTPUT , - -....-OUTPUT Input A: Req; 6 kn NOM Inputs B. C. D: Req = 2 kn NOM 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 7-139 TTL MSI TYPE SN74142 BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER BULLETIN NO. DL·S 7211719, MAY 1972-REVISED DECEMBER 1972 JOR N DUAL-IN-LiNE PACKAGE (TOP VIEW) FUNCTION TABLE INPUTS COUNT PULSE (CLOCK) CLOCK/ LATCH DRIVER OUTPUTS COUNT 00 STROBE;-----I'---.. VCC INPUTOUTPUTINPUT 9 8 0 1 OUTPUTS CLEAR LATCH STROBE ONt QD X L L H L 0 1 H 1 2 H L 2 H 3 H L 3 H 4 H L 4 H H 5 H L 5 H 6 H L 6 H 7 H L 7 H 8 H L L 9 10 11 H L H L H H 8 9 0 0 L H H V DRIVER OUTPUTS t All other outputs are off. = high H level, L = low level, X = irrelevant positive logic: see function table and description description The SN74142 contains a divide·by-ten (BCD) counter, a four·bit latch, and a decoder/Nixie+ tube driver on a monolithic chip and is packaged in popular 16-pin packages. This single MSI function can replace the equivalent of three separately packaged MSI circuits to reduce printed-circuit board area and the number of system interconnections, resulting in reduced costs and improved reliability. • Four master-slave flip-flops are fully decoded to provide a divide·by·ten counter. A direct clear input will, when taken low, reset and hold the counter at zero (all Q outputs low, GO output high). While the clear input is inactive (high), each positive·going transition of the clock will increment the counter. The GO output is made available externally for cascading to n·bit counters. The Q outputs of the counter are routed to the data inputs of the four-bit latch. While the latch strobe input is low, the internal latch outputs will follow the respective Q outputs of the counter. When the latch strobe input is taken high, the latch stores the data which has been setup by the counter outputs prior to the low·to-high level transition of the latch strobe input. The GO output from the counter is not stored by the latch since it is intended for clocking the next counter stage. This means that the system counter can continuously acquire new data. Since all outputs of the latch and Q outputs of the counter drive low-capacitance on-chip loads, the circuitry is considerably simplified with respect to the number of components required. This results in a highly efficient function which typically reduces power requirements 15% when compared to systems using the three separate packages. The SN74142 counter/latch/driver features fully buffered inputs to reduce drive requirements to one normalized Series 74 load per input, and diode-clamping of all inputs to minimize transmission line effects. The counter will accept input clock frequencies up to 20 MHz and is entirely compatible for use with all popular TTL and OTl logic circuits. The high-performance n·p·n driver outputs are identical to the SN74141 and have a maximum off-state reverse current of 50 microamperes at 55 volts. :t.Nixie is a registered trademark of the Burroughs Corporation. 572 7-140 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 'tYPE SN74142 BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Off-state current into outputs 0 thru 9 Operating free-air temperature range Storage temperature range 7V 5.5 V 1 mA oOe to 70 e 0 0 -65°e to 150 e NOTE 1: All voltage values are with respect to the network ground terminal. recommended operating conditions Supply Voltage, Vec High-level output current from Low-level output current from MIN "JOM MAX 4.75 5 5.25 V -400 p.A aD. 10H aD. 10L Input clock frequency. fclock I High logic level Clock pulse width. tw(clock) (see Figure 1) I Low logic level 0 UNIT 8 mA 20 MHz 15 ns 35 Clear pulse width, tw(c1earl (see Figure 1) 25 ns Strobe pulse width, tw(strobe) (see Figure 1) 20 ns Clear inactive-state setup time. tsu (see Figure 1) 25 Strobe time, tstrobe (s,ee Figure 1) 45 Operating free-air temperature, T A 0 ns tw(clock) +10 70 ns °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONOITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level VOL Low-level VO(on) VO(off) 10(oft) MIN TYP+ MAX Vec= MIN, 11=-12mA VCC= MIN. 10H = -400p.A VCC= MIN, 10L = 8 mA On-state voltage, outputs 0 thru 9 VCC= MIN, 10 = 7 mA Off-state voltage. outputs 0 thru 9 Vce- MAX. 10 - 0.5 mA Off-state current. outputs 0 thru 9 Vce = MAX, Vo = 55V aD output voltage aD output voltage 2.4 UNIT V 2 0.8 V -1.5 V 0.4 V 2.5 V 50 p.A V 3.4 0.2 V 60 II Input current at maximum input voltage Vce = MAX, VI = 5.5 V 1 mA IIH High-level input current Vee = MAX, VI = 2.4 V 40 p.A IlL Low-level input current Vee = MAX. VI = 0.4 V -1.6 mA lOS Short-circuit -55 mA ICC Supply current 68 102 mA TYP MAX UNIT 35 55 30 45 30 45 aD output current -18 Vce = MAX Vec= MAX. All outputs open • tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, T A = 25°C. switching characteristics, Vee =-5 V, TA = 25°e PARAMETER tpLH tpHL tpLH TEST CONDITIONS MIN Propagation delay time, low-to-high-Ievel AD output from clock CL= 15pF. Propagation delay time, high-to-Iow-Ievel AD output from RL = 800.11. clock ns See Figure 1 Propagation delay time. low-to-high-Ievel aD output from clear ns 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DAL.L.AS. TEXAS 75222 7-141 TYPE SN74142 BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER schematics of inputs and outputs OUTPUT EQUIVALENT OF EACH INPUT Q TYPICAL OF OUTPUTS 0 THRU 9 -~""--VCC OUTPUT VCC------.------ INPUT OUTPUT PARAMETER MEASUREMENT INFORMATION OUTPUT VCC FROM OUTPUT --~--~~~-i~~~~--~ QD LOAD CIRCUIT tA tw(clear) ~tsu -+I·-----·~; INPUT I _ _"",:,1" CLOCK INPUT I I I I I I I '-----' I tw(clock)L LATCH STROBE (See Note B) ~ OUTPUT 3V 1.5V.r-:\. I II;, II tw(strobe) ----~I~--------~I~~'----11 I 11.5V 1.5V I.----.t-tPLH I _________..,1" I I-- 1.5V.r::'\--- }-IiI . '-5Pi'--: I ~1_1._------...:I••--__:_..I+I-tW(clOCk)H I 00 : I ~~~------~-- __s~------~\---------------:: CLEAR • tB I I I I I -.I tpHL ~ S~''''\I (See Note B) 3V I 1---------;------ tstrobe 0V -I------OV ~ tpLH ~VOH Ys----L ~~ _ V Voe VOLTAGE WAVEFORMS NOTES: A. This typical abbreviated sequence illustrates clearing from count 8 or 9 and counting through ten clock pulses. Clock pulses 3 through 7 and 9 are omitted for brevity. B. Strobe input can go low at any time; however, the positive transition to store data from any given clock transition (tA) must occur a minimum of 45 ns after tA and prior to 10 ns after the next positive-going clock transition (tB + 10 ns). C. Input pulses are supplied by generators having the following characteristics: tr .;;;; 7 ns, tf .;;;; 7 ns, PR R = 1 MHz, and Zout "" 50 .n. D. CL includes probe and jig capacitance. E. All diodes are 1 N3064. FIGURE 1 1076 7·142 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54143, SN54144, SN74143, SN74144 4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS TTL MSI BULLETIN NO. DL-S 7211538, NOVEMBER 1971-REVISED DECEMBER 1972 SN54143, SN54144 ••• J OR W PACKAGE SN74143, SN74144 ••• J OR N PACKAGE (TOP VIEW) LATCH MAX STROBE COUNT INPUT VCC ~ LATCH OUTPUTS ______JA~______~ ~ LED/LAMP DRIVER OUTPUTS ________-JA~________~ QA \ , b 21 SCEI CLOCK CLEAR RBI BI RBO DECIMAL dp e / NODE POINT' LED/LAMP DRIVER OUTPUTS v,--------- GND logic: see description o Choice of Driver Outputs: SN54143 and SN74143 have 15-mA Constant-Current Outputs for Driving Common-Anode LED's such as TIL302 or TI L303 without Series Resistors SN54144 and SN74144 Drive High·Current Lamps, Numitrons t, or LED's from Saturated Open·Coliector Outputs • • Universal Logic Capabilities Ripple Blanking of Extraneous Zeros Latch Outputs Can Drive Logic Processors Simultaneously Decimal Point Driver Is Included • Synchronous BCD Counter Capability Includes: Cascadable to N-Bits Look·Ahead-Enable Techniques Minimize Speed Degradation When Cascaded for Large-Word Display Direct Clear Input description These TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completely TTL/OTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of the input transistors to lower drive·current requirements to one·half of that required for a standard Series 54/74 TTL input. The serial-count-enable, actually two internal emitters, is rated as one standard series 54/74 load. The logic outputs, except RBO, have active pull-ups. The SN54143 and SN74143 driver outputs are designed specifically to maintain a relatively constant on-level sink current of approximately 15 milliamperes from outputs "a" through "g" and seven milliamperes from output "dp" over a voltage range from one to five volts. Any number of LED's in series may be driven as long as the output voltage rating is not exceeded. tTrademark of RCA 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-143 TYPES ~~54143, SN54144, SN74143, SN74144 4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS description (continued) The SN54144 and SN74144 drivers have high-sink-current saturated outputs for driving indicators having voltage ratings up to 15 volts or requiring up to 25 milliamperes drive_ The SN54144 sinks 20 milliamperes and the SN74144 sinks 25 milliamperes at an on-level voltage of 0.6 volts across their respective operating temperature ranges. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Maximum clock frequency is typically 18 megahertz and power dissipation is typically 280 milliwatts. The SN54143 and SN54144 are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74143 and SN74144 are characterized for operation from O°C to 70°C. Functions of the inputs and outputs of these devices are as follows: FUNCTION CLEAR INPUT PIN NO. 3 CLOCK INPUT 2 Each positive-going transition will increment the counter provided that the circuit is in the normal counting mode (serial and parallel count enable inputs low, clear input high). PARALLEL COUNT ENABLE INPUT (PCEI) 23 Must be low for normal counting mode. When high, counter will be inhibited. Logic level must not be changed when the clock is low. SERIAL COUNT ENABLE INPUT (SCEI) II DESCRIPTION When low, resets and holds counter at O. Must be high for normal counting. Must be low for normal counting mode, also must be low to enable maximum count output to go low. When high, counter will be inhibited and maximum count output will be driven high. Logic level must not be changed when the clock is low. MAXIMUM COUNT OUTPUT 22 Will go low when the counter is at 9 and serial count enable input is low. Will return high when the counter changes to 0 and will remain high during counts 1 through 8. Will remain high (inhibited) as long as serial count enable input is high. LATCH STROBE INPUT 21 When low, data in latches follow the data in the counter. When high, the data in the latches are held constant, and the counter may be operated independently. LATCH OUTPUTS (OA, 0B, OC, 0D) 17,18,19,20 The BCD data that drives the decoder can be stored in the 4-bit latch and is available at these outputs for driving other logic and/or processors. The binary weights of the outputs are: OA = 1, OB = 2, Oc = 4, OD = 8. DECIMAL POINT INPUT 7 Must be high to display decimal point. The decimal point is not displayed when this input is low or when the display is blanked. BLANKING INPUT (BI) 5 When high, will blank (turn off) the entire display and force RBO low. Must be low for normal display. May be pulsed to implement intensity control of the display. RIPPLE-BLANKING INPUT (RBI) 4 When the data in the latches is BCD 0, a low input will blank the entire display and force the RBO low. This input has no effect if the data in the latches is other than O. RIPPLE-BLANKING OUTPUT (RBO) 6 Supplies ripple blanking information for the ripple blanking input of the next decade. Provides a low if BI is high, or if RBI is low and the data in the latches in BCD 0; otherwise, this output is high. This pin has a resistive pull-up circuit suitable for performing a wire-AND function with any open-collector output. Whenever this pin is low the entire display will be blanked; therefore, this pin may be used as an active-low blanking input. LED/LAMP DRIVER OUTPUTS (a, b, c, d, e, f, g, dp) 15,16,14,9 11,10,13,8 Outputs for driving seven-segment LED's or lamps and their decimal points. See segment identification and resultant displays on following page. 1171 7-144 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54143, SN54144, SN74143, SN74144 4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS o SEGMENT IDENTIFICATION 2 3 4 5 6 7 9 8 NUMERICAL DESIGNATIONS-RESULTANT DISPLAYS schematics of inputs and outputs Q '143, '144 '143, '144 '143 '144 EQUIVALENT OF EACH INPUT EXCEPT BI/RBO EQUIVALENT OF BI/RBO TYPICAL OF ALL OUTPUTS EXCEPT BI/RBO TYPICAL OF ALL OUTPUTS EXCEPT BI/RBO VCC OUTPUT/INPUT Req INPUT _ _ ~OUTeUT -- SCEI: Req = 4 kn NOM Other inputs: Req = a kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . Input voltage . . . . . . . . . . . . . . . . . Off-state voltage at outputs "a" thru "g" and "dp", '144 Off-state current at outputs "a" thru "g" and "dp", '143 Continuous total power dissipation at (or below) 70°C free-air temperature (see Note 2) Operating free-air temperature range: SN54' Circuits SN74' Circuits Storage temperature range . . . . . . . . . . . 7V 5.5 V 15 V 250 p.A 1.4 W _55°C to 125°C . . O°C to 70°C -65°C to 150°C NOTES: 1. Voltage values are with respect to network ground terminal. 2. For the SN54143 and SN54144 in the Nand W packages. this rating applies at (or below) ao°c free-air temperature. For operation above this temperature, derate linearly at the rate of 11.7 mW/C for the W package and 14.7 mW/oC for the N package. No derating is required for these devices in the J package. • recommended operating conditions SN54143, SN54144 SN74143, SN74144 MIN MAX MIN NOM MAX 5.5 4.75 5 5.25 V 5 1 5 V 4.5 Supply voltage, VCC On-state voltage at outputs a thru g and dp ('143 only) High-level output current, IOH Low-level output current, 10L Clock pulse width, tw(clock) 1 5 -240 Maximum count -560 -560 RSO -120 -120 0A, aS, Oc, aD, RBO Maximum count 4.8 4.8 11.2 11.2 High logic level 25 25 Low logic level 55 55 25 25 30t 30t Serial and parallel carry 60t Clear inactive state Operating free-air temperature, T A -55 0 IJA mA ns ns ns 60t 125 UNIT -240 QA, QS, Oc, aD Clear pulse width, tw(clear) Setup time, tsu NOM 70 DC tThe arrow indicates that the rising edge of the clock pulse is used for reference. 1076 TEXAS INCOI{POI{ATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-145 TYPES SN54143, SN54144, SN74143, SN74144 4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK VOL Maximum count VIH=2V, 10L = MAX Outputs a thru g, dp Vee = MAX, 10H = 250jJ.A Outputs a thru g, dp Vee = MIN, See Note 3 Vee = MIN, Va = 1 V Vee = 5 V, Va = 2V output voltage output voltage On-state Vee = MAX, Va = 5V output current Vee = MIN, Va = 1 V Vee = 5 V, Va RBO node input current • ICC MIN TYP+ -1.5 -1.5 V V 0.4 15 7 V 0.6 15 Vee = MAX, Va = 5 V 7 Vee = MAX, VI = 5.5 V -0.12 22 mA 7 4.5 12 1 1 mA 40 40 jJ.A 20 jJ.A -0.5 -0.12 -0.5 -1.6 GA, GB, Ge, GO output current Maximum count -1.5 -1.5 -9 -27.5 -9 -55 -15 56 -2.4 mA -0.8 -15 Vee = MAX, See Note 5 mA -1.6 -2.4 -0.8 Vee = MAX V 15 Vee = MAX, VI = 0.4 V, Short-circuit V 15 9 See Note 4 Other inputs Supply current V V 20 RBO node UNIT 0.8 0.4 7 Vee = MAX, VI=2.4V MAX 2.4 2V = TYP+ 0.8 2.4 Serial carry input current MAX 2 Other inputs Low-level lOS SN54144, SN74144 MIN Serial carry High-level IlL 10H = MAX VIL=0.8V, I nput current at maximum input voltage IIH VIH=2V, VIL = 0.8 V, Maximum count Output dp II Vee = MIN, GA, GB, Ge, GO, RBO Vee = MIN, Outputs a thru g 10 (on) II = -12mA Low-level output On-State Va (on) Vee = MIN, voltage Off-state Va (off) RBO GA, GB, Ge, GO voltage SN54143, SN74143 2 Input clamp voltage High-level output VOH TEST CONDITIONSt 93 -27.5 -55 56 93 mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical NOTES: 3. 4. 5. values are at Vee = 5 V, T A = 25°e. For SN54144, IOL = 20 mA; for SN74144, IOL = 25 mAo II L at R BO node is tested with B I grounded and RBI at 4.5 V. lee is measured after the following conditions are established: a) Strobe = RBI = OP = 4.5 V b) Parallel count enable = serial count enable = BI = GNO c) elear(L..I")then clock until all outputs are on d) For '143, outputs "a" through "g" and "dp" = 2.5 V, all other outputs open. For '144, all outputs are open. U=:) switching characteristics, Vee PARAMETER § =5 V, T A =25°e FROM TO (INPUT) (OUTPUT) Serial look-ahead Maximum count TEST CONDITIONS f max tPLH tpHL tPLH Clock Maximum count Clock GA, GB, Ge, GO tpHL tpHL Clear 12 18 MAX eL=15pF,RL=560n, 23 35 See Note 6 26 40 29 45 See Note 6 UNIT MHz 20 eL = 15 pF, RL = 1.2 kn, GA, 0B, Ge, GO TYP 12 tpHL tpLH MIN 28 45 38 60 57 90 ns ns ns ns §fmax == Maximum clock frequency, tpLH == Propagation delay time, low-to-high-Ievel output, tpHL == Propagation delay time, high-to-Iow-Ievel output NOTE 6: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-146 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54143, SN54144, SN74143, SN74144 4-811 COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS functional block diagram OUTPUTS dp I I -q> ... Dynamic input activated by a transition from a high level to a low level. I TYPICAL APPLICATION DATA This application demonstrates how the drivers may be cascaded for N-bit display applications. It features: Synchronous, look-ahead counting Ripple blanking of leading zeros; blanking of trailing zeros (not illustrated) can also be implemented Overriding bianking -for total suppression or intensity modulation of display Direct parallel clear Latch strobe permits counter to acquire next display while viewing current display RIPPLE BLANKINGINPUT CLOCK INPUT MOST·SIGNIFICANT DIGIT 'I III I III LED/LAMP DRIVER OUTPUTS II I I II I I I I I I I I II II LEAST·SIGNIFICANT DIGIT I I I I I II I' LATCH STROBE INPUT TO NEXT MORE SIGNIFICANT DIGIT V LATCH LOGIC OUTPUTS tThe serial count-enable Input of the least-significant digit is normally grounded; however, it may be used as a count-enable control for the entire counter (high to disable, low to count) provided the logic level on this pin is not changed while the clock line is low or false counting may result. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-147 TIL TYPES SN54145, SN54LS145, SN74145, SN74LS145 BCD-TO-DECIMAL DECODERS/DRIVERS MSI BULLETIN NO. DL-S 7611815. MARCH 1974-REVISED OCTOBER 1976 FOR USE AS LAMP, RELAY, OR MOS DRIVERS • Full Decoding of Input Logic • SN54145, SN74145, and SN74LS145 Have aO-mA Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Conditions • Low Power Dissipation of 'LS145 ... 35 mW Typical SN54145, SN54LS145 ••• J OR W PACKAGE SN74145, SN74LS145 ••• J OR N PACKAGE (TOPVIEW) INPUTS II logic FUNCTION TABLE NO.' C B A 0 1 2 3 4 5 6 7 8 9 0 L L L L L H H H H H H H H H l' L L L H H L H H H H H H H H 2 3 L L H L H H L H H H H H H H L L H H H H H L H H H H H H 4 L H L L H H H H L H H H H H 5 L H L H H H H H H L H H H H 6 L H H L H H H H H H L H H H 7 L H H H H H H H H H H L H H 8 H L L L H H H H H H H H L H 9 H L L H H H H H H H H H H L H L H L H H H H H H H H H H H 0 H L H H H H H H H H H H H :::i H H L L H H H H H H H H H H > H H L H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H ~ • OUTPUTS 0 ~ H INPUTS = high level (off), L = low or OUTPUTS positive logic: see function table functional block diagram level (on) description These monilithic BCD-to-decimal decoder/drivers consist of eight inverters and ten four-input NAN D gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outputs remain off for all invalid binary input conditions. These decoders feature high-performance, n-p-n output transistors designed for use as indicator/ relay drivers or as open-collector logic-circuit drivers. Each of the high-breakdown output transistors (15 volts) of the SN54145, SN74145, or SN74LS145 will sink up to 80 milliamperes of current. Each input is one Series 54/74 or Series 54LS/74LS standard load, respectively. Inputs and outputs are entirely compatible for use with TTL or DTL logic circuits, and the outputs are compatible for interfacing with most MOS integrated circuits. Power dissipation is typically 215 milliwatts for the '145 and 35 milliwatts for the 'LS145. 1076 7-148 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54145, SN74145 BCD-TO-DECIMAL DECODERS/DRIVERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Maximum current into any output (off-state) Operating free-air temperature range: SN54145 SN74145 Storage temperature range 7V 5.5 V 1 rnA -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54145 MIN 4.5 Supply voltage, Vee Off-state output voltage, VO(off) SN74145 NOM MAX MIN 5 5.5 4.75 NOM 5 15 Operating free-air temperature, T A -55 125 a MAX 5.25 UNIT V 15 V 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage 10(0ff) VO(on) TEST CONDITIONSt MIN TYP+ MAX Off-state output current On-state output voltage Vee = MIN, 11= -12 mA Vee= MIN, VIH=2V, VIL = 0.8 V, VO(off) = 15 V Vee = MIN, VIH=2V, 0.5 110(on) = 80 mA VIL = 0.8 V UNIT V 2 0.8 V -1.5 V 250 /-IA 0.9 0.4 110(on) - 20 mA V II Input current at maximum input voltage Vee" MAX, VI = 5.5 V 1 IIH High-level input current Vee = MAX, VI = 2.4 V 40 /-IA IlL Low-level input current Vee - MAX, VI - 0.4 V -1.6 mA lee Supply current Vee= MAX, See Note 2 ISN54145 43 62 ISN74145 43 70 mA mA II tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. NOTE 2: ICC is measured with all inputs grounded and outputs open. switching characteristics, Vee = 5 V, T A = 25°C PARAMETER TEST CONDITIONS Propagation delay time, low-to-high-Ievel output Propagation delay time, high-to-Iow-Ievel output CL = 15 pF, MIN See Note 3 R L = 100 n, MAX 50 50 NOTE 3: Load circuit and waveforms are shown on page 3-10. schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT Vcc _ _ _ _- OUTPUT INPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-149 TYPES SN54LS145, SN74LS145 BCD-lO-DECIMAL DECODERS/DRIVERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. Vee (see Note 1) ..... . Input voltage . . . . . . . . .... . Operating free·air temperature range: SN54LS145 SN74LS145 Storage temperature range 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS145 Supply voltage, Vee Off·state output voltage, VO(off) SN74LS145 MIN NOM MAX MIN 4.5 5 5.5 4.75 NOM 5 MAX 5.25 15 Operating free·air temperature, T A -55 125 0 UNIT '! 15 V 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IO(off) VO(on) • TEST CONDITIONSt SN54LS145 TYPt MIN SN74LS145 MAX 2 Off-state output current On-state output voltage Vee = MIN, 11=-1SmA Vee = MIN, VIH = 2 V, VIL = VIL max, VOH=15V Vee = MIN, tlOL = 12 mA MIN TYPt MAX 2 V 0.7 O.S V -1.5 -1.5 V 250 j.lA 250 0.25 UNIT 0.4 0.25 0.4 0.5 VIH=2V, IIOL - 24 mA 0.35 VIL = VIL max POL = SO mA 2.3 V 3 II Input current at maximum input voltage Vee - MAX, VI = 7V 0.1 0.1 IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 j.lA IlL Low-level input current Vee= MAX, VI = 0.4 V -0.4 -0.4 mA lee Supply current Vee - MAX, See Note 2 13 mA 7 13 7 mA tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at VCC = 5 V, T A = 25°C. NOTE 2: ICC is measured with all Inputs grounded and outputs open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS j---:tP..:L:.:.H..:-_P_r_op;...a...;;g_at_io_n_de_l_ay;...t....,i_m_e;....I...,O...,W...,-t_O_-h,...:ig:;..h_-I_ev_e_l_o_ut....;.p_u-lt eL = 45 pF, tpHL Propagation delay time, high-to-Iow-Ievel output RL=665n, MIN See Note 4 MAX 50 50 NOTE 4: Load circuit and waveforms are shown on page 3-11. q schematic of inputs and outputs EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL OUTPUTS 17 kn NOM INPUT -- 107E 7·150 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 TYPES SN54147, SN54148, SN54LS147, SN54LS148, TTL SN74147, SN74148 (TIM9907),SN74LS147, SN74LS148 MSI 10-LlNE-TO-4-LlNE AND 8~LlNE-TO-3-LlNE PRIORITY ENCODERS BULLETIN NO. OL-S 7711727;OCTOBER 1976-REVISED AUGUST 1977 '147, 'LS147 • Encodes 10-Line Decimal to 4-Line BCD • Applications Include: SN54147, SN54LS147 • _. J OR W PACKAGE SN74147,SN74LS147 ••• J OR N PACKAGE (TOP VIEW) INPUTS NC OU1"UT~OU~UT Keyboard Encoding Range Selection '148, 'LS148 • Encodes 8 Data Lines to 3-Line Binary (Octal) • Applications Include: N-Bit Encoding Code Converters and Generators TYPICAL TYPE TYPICAL DATA POWER DELAY DISSIPATION '147 10 ns 225mW '148 10 ns 190mW 'LS147 15 ns 60mW 'LS148 15 ns 60mW positive logic: see function table NC-No internal connection SN54148, SN54LS148. ,. J OR W PACKAGE SN74148, SN74LS148 ••• J OR N PACKAGE (TOP VIEW) description OUTPUTS These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level. The '148 and 'LS148 encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54LS/74LS load, resp·ectively. VCC INPUTS ~ ~OU~~UT • positive logic: see function table '147, 'LS147 H '148, 'LS148 1 2 3 FUNCTION TABLE INPUTS 6 7 4 5 B 9 H H H H X X X X X X X X L X X X X X X X X X X X X X X X L H = ,high OUTPUTS A C B EI 0 1 H H X X H L L H H H H H H H H H H H H L H H L L L L H L X L L L H L L H L H L X X X X X X H X X X L L L H H L H L L H H L L X X L H H H L H H L H L H H L X X X X X X X L X L H H H H H L L L H H H L L L X X X X X X X L H H H H H H L H L H H H L H L X L H H H H H H H H L L H H H H L L L H H H H H H H H H H L H 0 H H H H H H H X X X X X X X L L L H H L H L H H H L L H H H H L L H H H H H L L H H H H H H L H H H H H H H H H H H H H H H H H H H X X X X X X logic level, L H = low logic level, X FUNCTION TABLE OUTPUTS INPUTS 3 4 5 6 7 A2 A1 AO GS EO 2 H H H X H H X X X X X H = irrelevant 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALL.AS, TEXAS 75222 7-151 TYPES SN54147, SN54148, SN54LS147,- S-N54LS148, SN74147, SN74148 (TIM9907), SN74LS147, SN74tS148 10-LlNE-TO-4-LlNE AND 8-LlNE~TO-3-LlNE PRIORITY ENCODERS functional block, diagrams • 1071 7·152 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54147, SN54148, SN54LS147, SN54LS148, SN74147. SN74148 (TIM9907) SN74LS147, SN74LS148 10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS schematics of inputs and outputs '147, '148 EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS --e---vcc V C C - - -.....- - - INPUT OUTPUT o input ('148): Req All other inputs: Req = 2 kU = NOM 4 kU NOM 'LS147, 'LS148 EaUIVALENT OF ALL INPUTS TYPICAL OF ALL OUTPUTS Vee---e--- - - - - - - . . - - Vee Req INPUT -.-:+GH"--..~[)I.l.+--- 'LS148 inputs 1 thru 7: Req All other inputs: Req OUTPUT = 9 kU NOM = 18 kU NOM II absolute maximum ratings over operating free·air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage: '147, '148 'LS147, 'LS148 Interemitter voltage: '148 only (see Note 2) Operating free-air temperature range: SN54', SN54LS Circuits SN74', SN74LS Circuits Storage temperature range NOTES: I . 7V 5.5 V . 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C 1. Voltage values, except intermitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For '148 circuits, this rating applies between any two of the eight data lines, 0 through 7. recommended operating conditions MIN Supply voltage, Vee 4.5 High-level output current, IOH MIN 5.5 4.75 5 -800 Low-level output current, IOL Operating free-air temperature, T A SN54' NOM MAX MIN 5.25 4.5 5 -800 16 -55 125 SN54LS' SN74' NOM MAX 70 5 SN74LS' MAX MIN NOM 5.5 4.75 5 -400 16 0 NOM 4 -55 125 0 MAX UNIT 5.25 V -400 J.lA mA 8 70 °e 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-153 TYPES SN54147, SN54148, SN74147, SN74148(TIM9907), 10-LlNE-TO-4-LlNE AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) '148 '147 PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage TEST eONDITIONst 2 Vee- MIN, II = -12 rnA Vee= MIN, VIH = 2V, 10H = -800IlA VIL = 0.8 V, VCC- MIN, Low-level output voltage II Input current at maximum input voltage IIH High-level input current o input Any input except 0 o input Low-level input current Any input except 0 lOS Short-circuit output current§ ICC Supply current VIL = 0.8 V, VIH=2V, 10L = 16 rnA VCC= MAX, VI = 5.5 V Vce = MAX, VI = 2.4 V VCC= MAX, VI = 0.4 V -1.5 2.4 3.3 2.4 0.2 0_8 V -1.5 V 3.3 0.2 0.4 UNIT V 2 0_8 VOL IlL MIN TYPt MAX MIN TYP+ MAX V 0.4 1 1 40 40 80 -1.6 -1.6 -3.2 V rnA Il A rnA -85 rnA VCC = MAX, ICondition 1 50 70 40 60 rnA See Note 3 42 62 35 55 rnA -35 Vce = MAX ICondition 2 -85 -35 NOTE 3: For '147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) Is measured with all inputs and outputs open. For '148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (condition 2) is measured with all inputs and outputs open. t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions_ tAil tYpical values are at Vee = 5 V, T A = 25°C. ~ Not more than one output should be shorted at a time. SN54147, SN74147 switching characteristics, Vee PARAMETER~ • tPLH tpHL tPLH tPHL FROM (INPUT) Any Any TO (OUTPUT) Any Any SN54148, SN74148 switching characteristics, Vee PARAMETER~ FROM (INPUT) TO (OUTPUT) tPLH tpHL 1 thru 7 AO, Al, or A2 tPLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL 1 thru 7 AO,Al,orA2 o thru 7 EO o thru 7 GS EI AO, Al, or A2, EI GS EI EO = 5 V, T A = 25°e WAVEFORM In-phase output Out-ot-phase output TEST CONDITIONS MIN CL=15pF, RL=400n, See Note 4 TYP MAX UNIT 9 14 7 11 13 19 12 19 ns ns = 5 V, T A = 25°e WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT In-phase 10 15 output Out-ot-phase 9 13 19 output Out-ot-phase 12 6 19 10 14 25 30 output In-phase output CL=15pF, RL = 400 n, See Note 4 18 10 25 15 output 10 15 In-phase 8 12 output 10 15 In-phase 10 15 output 17 30 In-phase 14 14 ns ns ns ns ns ns ns ~ tPLH == propagation delay tim'e, low-to-high-Ievel output tPH L '" propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuits and waveforms are shown on page 3-10. 181 7-154 TEXAS INSTRUMENTS INCORPORATE:D POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS147, SN54LS148, SN74LS147, SN74LS148 10-LlNE-TO-4-LlNE AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS REVISED DECEMBER 1980 electrical characteristics over recommended operating free·air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage SN54LS' TEST CONDITIONSt SN74LS' MIN TYP:j: MAX ~N TYP:j: MAX 2 Vec= MIN, 11=-18mA Vee = MIN, VIH = 2 V VIL = 0.8 V, VOL Low-level output voltage 2.5 3.4 0.25 llOL = 4 mA 0.4 V 3.4 0.25 0.4 0.35 0.5 V VIH=2V, Input current at 'LS148 inputs 1 thru 7 maximum input voltage All other inputs Vee= MAX, 'LS148 inputs 1 thru 7 High-level input current All other inputs Vee = MAX, 'LS148 inputs 1 thru 7 IlL Low-level input current lOS Short·circuit output current§ ICC V -1.5 2.7 VIL = VILmaxllOL =8 mA IIH V 0.8 -1.5 10H = -400 /lA Vee = MIN, II V 0.7 VOH High-level output voltage UNIT 2 Vee = MAX, All other inputs VI.= 7V VI = 2.7 V VI = 0.4 V VCC = MAX Supply current See Note 5 0.2 0.1 0.1 40 40 20 20 -0.8 -0.8 -0.4 -20 VCC = MAX, 0.2 I Condition 1 I Condition 2 -0.4 -100 -20 mA /lA mA -100 mA 12 20 12 20 mA 10 17 10 17 mA NOTE 5: For 'LS147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured with all inputs and outputs open. For 'LS148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open, ICC (condition 2) is measured with all inputs and outputs open. tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions. :j:AII typical values are at V CC = 5 V, T A = 25° C. ~ Not more than one output should be shorted at a time. SN54LS147, SN74LS147 switching characteristics, Vee PARAMETER1i tPLH FROM TO (INPUT) (OUTPUT) Any = 5 V, TA = 25°e WAVEFORM Any tPHL output tPLH Out·of·phase Any Any SN54LS148, SN74LS148 switching characteristics, Vee tpLH tpHL tPLH tpHL tPLH tpHL tPLH tPHL tPLH tpHL tpLH tPHL tpLH FROM TO (INPUT) (OUTPUT) 1 thru 7 AO, AI, or A2 1 thru 7 AO,Al,orA2 o thru 7 EO o thru 7 EI EI EO See Note 4 WAVEFORM 12 18 12 18 21 33 15 23 TEST CONDITIONS MIN ns ns &I TYP MAX UNIT In·phase 14 18 output 15 25 Out·of-phase 20 36 output 16 29 Out-of-phase 7 18 25 40 35 55 output tpHL TYP MAX UNIT = 5 V, TA = 25°e output AO, AI, or A2 GS RL = 2 kn, In-phase GS EI CL = 15 pF, output tpHL PARAMETER1i TEST CONDITIONS MIN In-phase In-phase CL=15pF, RL = 2 kn, See Note 6 9 21 16 25 output 12 25 In·phase 12 17 output 14 36 In-phase 12 21 output 23 35 ns ns ns ns ns ns ns 11 tPLH '" propagation delay time. low·to·high·level output tPHL '" propagation delay time. high·to·low·level output NOTE 6: Load circuits and waveforms are shown on page 3-11. 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-155 TYPES SN54147, SN54148 (TIM9907), SN54LS147, SN54LS148, SN74147, SN74148, SN74LS147, SN74LS148 10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS TYPICAL APPLICATION DATA ~ 16-LlNE DATA __________________________ ______________________ -JI\~ ~ / ENABLE o 2 3 4 5 6 7 o EI SN54148/SN74148, SN54LS148/SN74LS148 EO 2 3 4 5 6 7 EI SN54148/SN74148, SN54 LS148/SN74LS148 EO GS GS SN5400/SN7400 SN54LSOO/SN74LSOO • PRIORITY FLAG Full 4-bit binary 16-line-to-4-line encoding can be implemented as shown above. The enable input must be low to enable the function. Decoding with 2-input NAND gates produces true (active-high) data for the 4-line binary outputs. If active-low data is required, the SN5408/SN7408 or SN54LS08/SN74LS08 AND gate may be used, respectively. 1076 7-156 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54150, SN54151A, SN54152A, SN54LS151, SN54LS152, SN54S151, SN74150, SN74151A, SN74LS151, SN74S151 DATA SELECTORS/MULTIPLEXERS BULLETIN NO. DL-S 7611819, DECEMBER 1972-REVISED OCTOBER 1976 SN54150 ••• J OR W PACKAGE SN74150 ••• J OR N PACKAGE (TOP VIEW) • '150 Selects One-of-Sixteen Data Sources • Others Select One-of-Eight Data Sources • Performs Parallel-to-Serial Conversion • Permits Multiplexing from N Lines to One Line • Also For Use as Boolean Function Generator • Input-Clamping Diodes Simplify System Design • Fully Compatible with Most TTL and DTL Circuits positive logic: see function table TYPICAL AVERAGE TYPE TYPICAL PROPAGATION DELAY TIME POWER DATA INPUT TO W OUTPUT DISSIPATION '150 11 ns 200mW '151A 8 ns 145mW '152A 8 ns 130mW 'LS151 11 nst 30mW 'LS152 11 nst 'S151 4.5 ns SN54151A, SN54LS151, SN54S151 ••• J OR W PACKAGE SN74151A SN74LS151, SN74S151 ••• J OR N PACKAGE (TOP VIEW) 28mW 225mW tTentative data description I These monolithic data selectors/multiplexers contain full on-chip binary decoding to select the desired data source. The '150 selects one-of-sixteen data sources; the '151A, '152A, 'LS151, 'LS152, and 'S151 select one-of-eight data sources. The '150, '151A, 'LS151, and 'S151 have a strobe input which must be at a low logic level to enable these devices. A high level at the strobe forces the W output high, and the Y output (as applicable) low. II positive logic: see function table I SN54152A, SN54LS152 ••• W PACKAGE (TOP VIEW) DATA INPUTS· DATA SELECT vcc~~ The '151A, 'LS151, and 'S151 feature complementary Wand Y outputs whereas the '150, '152A, and 'LS152 have an inverted (W) output only. The '151A and '152A incorporate address buffers which have symmetrical propagation delay times through the complementary paths. This reduces the possibility of transients occurring at the output(s) due to changes made at the select inputs, even when the '151A outputs are enabled (i.e., strobe low). ~ .. ~2_.~ W ~OUTPUT positive logic: see function table 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-157 TYPES SN54150, SN54151A, SN54152A, SN54LS151, SN54LS152, SN54S151, SN74150, SN74151A SN74LS151, SN74S151 DATA SELECTORS/MULTIPLEXERS REVISED OCTOBER 1976 logic '150 '151A, 'LS151, 'S151 '152A, 'LS152 FUNCTION TABLE FUNCTION TABLE FUNCTION TABLE INPUTS INPUTS SELECT D C B A S X X X X H L L L L L L L L H L L L H L L L H H L H L L L L l L L L OUTPUT STROBE SELECT W H EO El E2 E3 E4 A S X X X H L H L L L L L L L 00 H L H L H H L L 02 L H L L L 04 H L H L 05 L L 07 Do 51 52 03 54 05 56 OJ L H L E5 H L E6 H H L H L L H H H H H L L L L H L L H L E7 E8 E9 El0 H L H L L H L H H L H H L L L E12 H H L H L E13 W B H H V C H SELECT OUTPUTS STROBE 01 03 06 OUTPUT INPUTS W C B A L L 00 L L L H 51 L H L L H" H 52 03 54 H L L H L H 05 H H L 56 H H H OJ = high level, L = low level, X = irrelevant E 15 = the complement of the level of the respective E input DO, 01 .•• 07 = the level of the 0 respective input H Eo, E1 ... ffi - H H H L L E14 H H H H L E15 '151A, 'LS151, 'S151 functional block diagrams '150 "v E 19! o (Bl ;== • i==fLJ F=='jaJ ,171 F= ,OJ f= F~ ,OJ F= '" '" '" '" F=='FL-JF=='fL)F=~ Ffi...)FFL.JL ~ 1231 1"1 - '152A, 'LS152 00'51 POt OUTPUT " 1211 02 ('2'Ot 2' 1191 ] I'!!! ..,..!.!"LI----t-J.-I--I--1L--r-.. 05'1]1 FL-J- MI'l) ~ 07'11 1 FU 1161 PSI r-.. (14) ~ "" :::. "" 'N'"" ~ (111 131 03'2 1 fL)-, D1'41 ~ ~ FL-J- ~ V EL.J ,::--1. , ::--!' , , ADDRESS BUFFERS FOR' 151A, '152A " .-{5 ADDRESS BUFFERS FOR 'LS151, 'S151, 'LS152 ij 1076 7·158 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A DATA SELECTORS/MULTIPLEXERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwisenoted) Supply voltage, V CC (see Note 1) Input voltage (see Note 2). . . . Operating free·air temperature range: SN54' Circuits SN74' Circuits Storage temperature range: 7V 5.5V -55°C to 125°C aOc to 70°C -65°C to 150°C NOTES: 1. Voltage values are with respect to network ground terminal. 2. For the '150, input voltages must be zero or positive with respect to network ground terminal. recommended operating conditions SN54' MIN Supply voltage, Vee 4.5 NOM 5 High-level output current, 10H SN74' MAX MIN 5.5 4.75 NOM 5 -800 Low-level output current, 10 L UNIT MAX 5.25 V -800 /lA 16 rnA 70 °e 16 Operating free-air temperature, T A -55 a 125 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL '151A, '152A '150 PARAMETER TEST eONDITIONSt MIN TYP+ MAX MIN 2 TYP+ Low-level output voltage II = -8 mA Vee= MIN, VIH = 2V, VIL ~ 0.8 V, 10H = -800/lA Vee= MIN, VIH = 2V, VIL = 0.8 V, 10L = 16mA 2.4 3.4 0.2 2.4 0.8 V -1.5 V 3.4 0.2 0.4 UNIT V 0.8 Vee= MIN, MAX 2 V 0.4 V II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 IIH High-level input current Vee- MAX, VI=2.4V 40 40 /lA IlL Low-level input current Vee= MAX, VI = 0.4 V -1.6 -1.6 mA lOS Short·circuit output current§ Vee= MAX lee Supply current SN54' -20 -55 -20 -55 SN74' -18 -55 -18 -55 '150 Vee = MAX, See Note 3 40 mA II mA 68 '151A 29 48 '152A 26 43 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. +AII typical values at V CC = 5 V, T A = 25° C. ~ Not more than one output of the '151 A should be shorted at a time. NOTE 3: ICC is measured with the strobe and data select inputs at 4.5 V, all other inputs and outputs open. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-159 TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A DATA SELECTORS/MULTIPLEXERS REVISED DECEMBER 1980 switching characteristics, Vee PARAMETER~ TO TEST (INPUT) (OUTPUT) CONDITIONS tpLH A, B, orC tpHL (4 levels) tpLH A, B, C, or D tpHL (3 levels) tpLH = 5 V, T A = 25°e FROM W Y CL=15pF, Strobe W RL = 400 n, See Note 4 DO thru D7 Y Strobe tpHL tpLH TYP '151A, '152A MAX MIN TYP MAX 25 38 Y tpHL tpLH '150 MIN EO thru E15, or tpHL DO thru D7 W 38 23 35 17 26 22 33 19 30 21 33 22 33 15.5 24 14 21 21 30 15 23 tpHL tpLH 25 13 20 18 27 8.5 14 8 14 13 20, 8 14 UNIT ns ns ns ns ns ns ~ tpLH '" propagation delay time, low·to-high-Ievel output tpH L '" propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-10. schematics of inputs and outputs EQUIVALENT OF EACH INPUT OF '150 Vee _ _ _ ~~ EQUIVALENT OF EACH INPUT OF '151A, '152A Vee _ _ _ _ __ INPUT ~.- _ __ INPUT II TYPICAL OF ALL OUTPUTS OF '150, '151A, '152A 1B1 7-160 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS151, SN54LS152, SN74LS151 DATA SELECTORS/MULTIPLEXERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . . . Input voltage . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS' Circuits SN74LS' Circuits Storage temperature range 7V 7V -55°e to 125°e 0 O°C to 70 e 0 -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. recommend~d operating conditions SN54LS' I \MIN NOM MAX MIN Supply voltage, Vee ! 4.75 High-level output current, 10H I Low-level output current, 10L I I-55 Operating free-air temperature, T A 4.5 5 5.5 SN74LS' NOM MAX 5 -400 5.25 V -400 p.A S mA 70 °e 4 125 UNIT 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54LS' TEST eONDITIONSt MI[\I VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage I nput current at TYP+ SN74LS' MAX MIN 2 Vee= MIN, II = -1SmA Vee= MIN, VIH = 2V, 2.5 VIL = VIL max, 10H = -400 p.A Vee- MIN, VIH - 2 V, VIL = VIL max MAX UNIT V 2 0.7 O.S V -1.5 -1.5 V 3.4 0.25 IIOL - 4 mA TYP~ 2.7 0.4 3.4 0.25 0.35 POL = SmA V 0.4 0.5 V Vee = MAX, VJ =7 V 0.1 0.1 IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 v.A IlL Low-level input current Vee = MAX, VI - 0.4 V -0.4 -0.4 mA lOS Short-circuit output currentS Vee = MAX -100 mA ICC Supply current II maximum input voltage Vee= MAX, -100 -20 Outputs open, I 'LS151 6.0 10 I 'LS152 5.6 9 All inputs at 4.5 V -20 6.0 10 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. +AII typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second. 1076 TEXASINCORPORATED INSTRUMENTS POST OFFICE sox 5012 • DALLAS. TEXAS 75222 7-161 TYPES SN54LS151, SN54LS152, SN74LS151 DATA SELECTO RS/M ULTIPLEXERS switching characteristics, Vee PARAMETER~ =5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) tPLH A, B,orC tPHL (4 levels) tPLH A,B,orC tPHL (3 levels) tPLH Y CL Strobe W MAX 27 43 18 30 14 23 = 15 pF, = 2 kn, See Note 5 tPHL 20 32 26 42 20 32 15 24 18 30 20 32 tPHL 16 26 tPLH 13 21 12 20 tpLH Y Any 0 Any 0 W tPHL ~ tPLH TYP W RL tpLH MIN Y Strobe tpHL SN54LS', SN74LS' TEST CONDITIONS UNIT ns ns ns ns ns ns == Propagation delay == Propagation delay time, low-to-high-Ievel output time, high-to-Iow-Ievel output NOTE 5: See load circuits and waveforms on page 3-11. tPH L schematics of inputs and outputs TYPICAL OF ALL OUTPUTS OF 'LS151, 'LS152 EQUIVALENT OF EACH INPUT OF 'LS151, 'LS152 ------.---- V CC 120 VCC------~~-------- • n NOM Req r........... .... INPUT--.....,.-I4 -----4I~.- 1.--_ _,..._ Data select and strobe: Req Data inputs: Req = 20 = 17 OUTPUT kn NOM kn NOM 1076 7-162 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S151, SN74S151 DATA SELECTORS/MULTIPLEXERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ........ . Input voltage . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54S151 Circuits SN74S151 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S151 MIN Supply voltage, Vee 4.5 High-level output current, IOH NOM 5 SN74S151 MAX MIN 5.5 4.75 NOM 5 -1 Low-level output current, IOL 20 Operating free-air temperature, T A -55 125 0 MAX UNIT 5.25 V -1 mA 20 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH VOL MIN TYPt MAX 2 High-level output voltage Vee= MIN, 11=-18mA Vee= MIN, VIH = 2 V, VIL = 0.8 V, IOH = -1 mA Vee= MIN, VIH=2V, VIL = 0.8 V, IOL = 20mA Low-Isvel. output voltage I SN54S' I SN74S' UNIT V 2.5 3.4 2.7 3.4 0.8 V -1.2 V V 0.5 V II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 IIH High-level input current Vee - MAX, VI - 2.7 V 50 IJA IlL Low-level input current Vee = MAX, VI = 0.5 V -2 mA lOS Short-circuit output current § Vee= MAX -100 mA lee Supply current 70 mA -40 Vee = MAX, All inputs at 4.5 V, All outputs open 45 mA I & I tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. tAil typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-163 TYPES SN54S151, SN74S151 DATA SELECTORS/MULTIPLEXERS switching characteristics, Vee PARAMETER~ =5 V, TA =25°e TO (OUTPUT) tpLH A, B, or C tpHL (4 levels) tpLH A, B,orC tpHL (3 levels) tpLH SN54S151, SN74S151 FROM (INPUT) Y Any D tpLH Strobe Y Strobe W tpHL n, See Note 4 W tpHL tpHL MAX 12 18 12 18 10 15 9 13.5 8 12 8 12 4.5 7 CL=15pF, RL = 280 tpLH TYP W Any D tPLH UNIT MIN Y tpHL ~ tp LH TEST CONDITIONS 4.5 7 11 16.5 12 18 9 13 8.5 12 ns ns ns ns ns ns = = Propagation delay time, low·to·high·level output tpH L Propagation delay time, high·to·low·level output NOTE 4: See load circuits and waveforms on pag" 3-10. schematics of inputs and outputs TYPICAL OF ALL OUTPUTS OF'S151 EQUIVALENT OF EACH INPUT OF'S151 ------~---Vee 50 Vee - - - -....- - - • n NOM INPUT OUTPUT 1272 7·164 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54153, SN54L153, SN54LS153, SN54S153, SN74153, SN74L153, SN74LS153, SN74S153 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS TTL MSI BULLETIN NO. DL-S 7611852, DECEMBER 1972 - REVISED OCTOBER 1976 SN54153, SN54LS153, SN54S153 ••• J OR W PACKAGE SN54L 153 ••• J PACKAGE SN74153, SN74L153, SN74LS153, SN74S153 ••• J OR N PACKAGE (TOP VIEW) • Permits Multiplexing from N lines to 1 line • Performs Parallel-to-Serial Conversion • Strobe (Enable) Line Provided for Cascading (N lines to n lines) • High-Fan-Out, Low-Impedance, Totem-Pole Outputs • Fully Compatible with most TTL and DTL Circuits positive logic: see function table TYPICAL AVERAGE TYPE PROPAGATION DELAY TIMES FROM DATA FROM STROBE TYPICAL POWER FROM SELECT DISSIPATION '153 14 ns 17 ns 22 ns 180mW 'L153 27 ns 34 ns 44 ns 90mW 'LS153 14 ns 19 ns 22 ns 31 mW 6 ns 9.5 ns 12 ns 225mW 'S153 FUNCTION TABLE SELECT DATA INPUTS STROBE OUTPUT B A CO C1 C2 C3 G Y X X X X X X H L L L X X X L L L L H \"eX X X L H L" H X X L L ',X X L H INPUTS description Each of these monolithic, data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs are provided for each of the two four-line sections. '. X L L H L X X H X L H L. H L L L H H H X X X H H X X X Select inputs A and B are common to both sections. H = high level, L = low level, X = irrelevant absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage: '153, 'L 153, 'S153 . . . . . . . . . . . . . . . . . . 'LS153 . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits SN74', SN74L', SN74LS', SN74S' Circuits Storage temperature range . . . . . . . . . . . . . 7V 5.5 V 7V -55°C to 125°C aOc to 7aoC -65°C to 15aoC NOTE 1: Voltage values are with respect to network ground terminal. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-165 TYPES SN54153, SN54L153, SN54LS153, SN54S153, SN74153, SN74L153, SN74LS153, SN74S153 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED DECEMBER 19BO functional block diagram STROBE 1G (ENABLE) lCO lCl (11 16) (5) DATA 1 (4) lC2 lC3 (3) 2CO (10) 2Cl (111 2C2 (121 2C3 (13) DATA 2 STROBE 2G (ENABLE) (151 schematics of inputs and outputs EQUIVALENT OF INPUTS OF '153, 'L153 • vcc3-- EQUIVALENT OF INPUTS OF 'LS153 Vec .1 ,. 'U_N:" Req INPUT -- INPUT ... vec o 2.8 kn NOM INPUT , , ~~ r. - EQUIVALENT OF INPUTS OF '5153 -- '153: Req = 4 kn NOM 'L 153: Req = 8 kn NOM TYPICAL OF OUTPUTS OF '153, 'L 153 -..--Vee TYPICAL OF OUTPUTS OF 'LS153 TYPICAL OF OUTPUTS OF 'S153 ---~-Vce R = 120 n NOM ' - -......-OUTPUT OUTPUT '153: R 'L 153: R = 130 n = 260 n NOM NOM 1280 7·166 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54153, SN74153 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS recommended operating conditions SN74153 SN54153 MIN Supply voltage, Vee 4.5 NOM MAX MIN 5.5 4.75 5 NOM 5.25 V pA 16 mA 70 °e 16 Low-level output current, IOL Operating free-air temperature, T A 125 -55 UNIT -800 5 -800 High-level output current, IOH MAX 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH SN74153 SN54153 TEST CONDITIONSt PARAMETER MIN TYPt MAX High-level output voltage 11- -12mA Vee - MIN, VIH - 2 V, VIL 2.4 = 0.8 V, IOH = -800pA Vee- MIN, VIH - 2V, VIL = 0.8 V, IOL = 16mA TYPt MAX UNIT V 2 2 Vee- MIN, MIN 0.8 0.8 V -1.5 -1.5 V 2.4 3.4 0.2 3.4 0.2 0.4 V 0.4 V VOL Low-level output voltage II Input current at maximum input v:::~3ge Vee - MAX, VI- 5.5V IIH High-level input current Vee = MAX, VI = 2.4 V 40 40 pA IlL Low-level input current Vee - MAX, VI- 0.4 V -1.6 -1.6 mA lOS Short-circuit output current!? Vee = MAX -55 -20 Vec- MAX, See Note 2 leCL Supply current, output low 1 1 36 -18 36 52 mA -57 mA 60 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at V CC = 5 V, T A = 25°C. §Not more than one output should be shorted at a time. NOTE 2: ICCL is measured with the outputs open and all inputs grounded. switching characteristics, Vee PARAMETER~ tpLH = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Data Y TEST CONDITIONS MIN TYP MAX UNIT • I 12 18 ns 15 23 ns 22 34 ns 22 34 ns Y 19 30 ns Y 15 23 ns tpHL Data Y tPLH Select Y CL tpHL Y See Note 3 tpLH Select Strobe tpHL Strobe = 30 pF, RL=400n, ~ tp LH = propagation delay time, low·to·high·level output tpHL = propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75:;!:22 7-167 TYPES SN54L153, SN74L153 DUAL 4-LlNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS recommended operating conditions SN54l153 MIN Supply voltage, Vee NOM 4.5 SN74L153 MAX MIN 5.5 4.75 5 High·level output current, 10H NOM 5 -400 MAX 5.25 V -400 j.lA 8 mA 70 °e 8 Low·level output current, 10L Operating free·air temperature, T A -55 125 UNIT 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH SN54l153 TEST CONDITIONSt MIN TVP+ SN74L153 MAX 2 High-level output voltage Vee= MIN, 11=-12mA Vee- MIN, VIH - 2V, VIL = 0.8 V, 10H = -400j.lA Vee= MIN, VIH = 2 V, VIL = 0.8V, 10L =8 mA MIN TVP+ MAX V 2 2.4 UNIT 0.8 0.8 V -1.5 -1.5 V 3.4 2.4 0.2 0.4 VOL Low·level output voltage II Input current at maximum input voltage Vee - MAX, VI - 5.5 V IIH High-level input current Vee = MAX, VI = 2.4 V 20 20 j.lA IlL Low·level input current Vee - MAX, VI - 0.4 V -0.8 -0.8 mA Short·circuit output currentS lOS leeL Supply current, output low 0.2 V 3.4 0.4 1 -10 Vee = MAX -28 18 Vee= MAX, See Note 2 1 -9 26 18 V mA -30 mA 30 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. NOTE 2: ICCL is measured with the outputs open and all inputs grounded . • switching characteristics, Vee =5 V, TA = 25°e FROM TO INPUT OUTPUT tpLH Data V 24 36 ns tpHL Data Y 30 46 ns tpLH Select Y eL=30pF, 44 68 ns tpHL Select Y See Note 3 44 68 ns tpLH Strobe V 38 60 ns tpHL Strobe Y 30 46 ns PARAMETER~ TEST CONDITIONS RL = 400 n, MIN TYP MAX UNIT ~ tp LH == propagation delay time, low·to·high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-168 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS153, SN74LS153 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED OCTOBER 1976 recommended operating conditions SN54LS153 MIN Supply voltage, Vee 4.5 SN74LS153 NOM MAX 5 5.5 MIN 4.75 NOM MAX 5 -400 High-level output current, IOH Low-level output current, IOL 5.25 V -400 p.A 8 mA 70 °c 4 Operating free-air temperature, T A -55 125 UNIT 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt SN54LS153 MIN VIH High-level input voltage Low-level input voltage SN74LS153 TYP:j: MAX MIN 2 VOH High-level output voltage Vee= MIN, 11=-18mA Vee= MIN, VIH = 2V, 2.5 VIL = VIL max, 10H = -400 p.A Vee= MIN, VOL Low-level output voltage VIH = 2 V, VIL = VIL max I nput current at 0.7 0.8 V -1.5 -1.5 V 3.4 0.25 IIOL =4mA UNIT V 2 VIL VIK Input clamp voltage TYP:j: MAX 2.7 0.4 IIOL = 8mA V 3.4 0.25 0.4 0.35 0.5 V Vee = MAX, VI =7 V 0.1 0.1 IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 p.A IlL Low-level input current Vee= MAX, VI = 0.4 V -0.4 -0.4 mA lOS Short-circuit output current § leeL Supply current, output low Vee= MAX -100 mA II maximum input voltage Vee = MAX, -100 -20 -20 See Note 2 6.2 10 6.2 mA 10 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second. NOTE 2: ICCL is measured with the outputs open and all inputs grounded. switching characteristics, Vee PARAMETER 11 tpLH =5 V, TA =25°e FROM TO (INPUT) (OUTPUT) Data Y tpHL Data Y tpLH Select Y tPHL Select Y tPLH Strobe Y tPHL Strobe Y TEST CONDITIONS MIN TYP 10 eL=15pF, RL = 2 kn, See Note 4 MAX UNIT 15 ns 17 26 ns 19 29 ns 25 38 ns 16 24 ns 21 32 ns • I == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuits and voltage waveforms are shown on page 3-11. 11 tPLH 1076 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·169 TYPES SN54S153. SN74S153 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS recommended operating conditions SN54S153 Supply voltage, Vee SN74S153 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 -1 High·level output current, 10H Low-level output current, 10L 20 Operating free-air temperature, T A -55 125 0 UNIT V -1 mA 20 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL VIK Low-level input voltage I nput clamp voltage VOH High-level output voltage TEST CONDITIONSt TYPt MAX UNIT V 2 Vee = MIN, 11= -18 mA Vee = MIN, VIH=2V, LSeries 54S 2.5 VIL = 0.8 V, 10H = -1 mA Series 74S 2.7 Vee = MIN, VIH = 2 V, VIL = 0.8 V, 10L = 20mA I 0.8 V -1.2 V 3.4 3.4 V VOL Low-level output voltage II I nput current at maximum input voltage 0.5 IIH High-level input current Vee = MAX, VI = 2.7 V 50 JJA IlL Low-level input current Vee = MAX, VI = 0.5V -2 mA -100 mA 70 mA Vee = MAX, VI = 5.5 V Short-circuit output current § lOS leeL Supply current, low-level output • MIN 1 -40 Vee = MAX Vee= MAX, See Note 2 45 V mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second. NOTE 2: ICCL is measured with the outputs open and all inputs grounded . switching characteristics, Vee PARAMETER~ =5 V, TA =25°C FROM TO (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tpLH Data Y tpHL Data Y tpLH Select Y eL=15pF, tpHL Select Y See Note 3 tpLH Strobe Y 10 15 ns tpHL Strobe Y 9 13.5 ns RL = 280 n, 6 6 9 9 11.5 18 ns 12 18 ns ns ns ~ tpLH := propagation delay time, low-to-high-Ievel output tpH L == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7·170 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222- TTL MSI TYPES SN54154, SN54L154, SN74154, SN74L154 4-LlNE-TO-16-UNE DECODERS/ DEMULTIPLEXERS BULLETIN NO. DL·S 7211805, DECEMBER 1972 SN54154 •.• J OR W PACKAGE SN54L154 ••• J PACKAGE SN74154, SN74L 154 ••• J OR N PACKAGE (TOP VIEW) • '154 is Ideal for High-Performance Memory Decoding • 'L 154 is Designed for Power-Critical Applications • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs Performs the Demultiplexing Function by Distributing ,Data From One Input Line to Any One of 16 Outputs o • Input Clamping Diodes Simplify System Design • High Fan-Out, Low-Impedance, Totem-Pole Outputs • Fully Compatible with Most TTL, DTL, and MSI Circuits TYPE '154 'L154 positive logic: see function table TYPICAL AVERAGE PROPAGATION DELAY 3 LEVELS OF LOGIC STROBE 23 ns 46 ns TYPICAL POWER DISSIPATION 19 ns 38 ns • 170mW 85mW description Each of these monolithic, 4·line·to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G 1 and G2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for implementing high-performance memory decoders. For ultra-high-speed systems, SN54S138/SN74S138 and SN54S139/ SN74S139 are recommended. These circuits are fully compatible for use with most other TTL and DTL circuits. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design. Series 54 and 54L devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and 74L devices are characterized for operation from O°C to 70°C. 076 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-171 TYPES SN54154, SN54L154, SN74154, SN74L154 4-U NE-TO-16-UN E DECO DERS/D EM ULTIPLEXERS logic FUNCTION TABLE INPUTS H OUTPUTS G1 G2 0 C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L L L L L L L H H H H H H H H H H H H H H H L L L L L H H L H H H H H H H H H H H H H H L L L L H L H H L H H H H H H H H H H H H H L L L L H H H H H L H H H H H H H H H H H H L L L H L L H H H H L H H H H H H H H H H H L L L H L H H H H H H L H H H H H H H H H H L L L H H L H H H H H H L H H H H H H H H H L L L H H H H H H H H H H L H H H H H H H H L L H L L L H H H H H H H H L H H H H H H H L L H L L H H H H H H H H H H L H H H H H H L L H L H L H H H H H H H H H H L H H H H H L L H L H H H H H H H H H H H H H L H H H H L L H H L L H H H H H H H H H H H H L H H H L L H H L H H H H H H H H H H H H H H L H H L L H H H L H H H H H H H H H H H H H H L H L L H H H H H H H H H H H H H H H H H H H ·L L H X X X X H H H H H H H H H H H H H H H H H L X X X X H H H H H H H H H H H H H H H H H H X X X H H H H H H H H H H H H H H H H = high level, L = low X level, X = Irrelevant functional block diagram and schematics of inputs and outputs • EQUIVALENT OF EACH INPUT vccx-W-- 'N'UT '154: R 'L154: R =4 =8 kn NOM kn NOM OUTPUTS TYPICAL OF ALL OUTPUTS Vee OUTPUT ABC '154: R 'L154: R = 130 n = 260 n NOM NOM 1272 7-172 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54154, SN74154 4-U NE-TO-16-UN E DECO DERS/ DEM ULTIPLEXERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ....... . I nput voltage. . . . . . . . ....... . Operating free·air temperature range: SN54154 Circuits SN74154 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74154 SN54154 MIN Supply voltage, Vee 4.5 NOM MAX MIN 5.5 4.75 5 High-level output current, IOH NOM 5.25 V pA 16 mA 70 °e 16 Operating free-air temperature, T A -55 125 UNIT -800 5 -800 Low·level output current, 10L MAX 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II TEST CONDITIONSt SN54154 MIN TYP SN74154 MAX 2 MIN TYp:j: 11;-12mA Vee; MIN, VIH; 2 V, VIL; 0.8 V, 10H; -800/J.A Vee; MIN, VIH; 2 V, VIL; 0.8 V, IOL; 16 mA Input current at maximum input voltage Vee; MAX, VI; 5.5V -1.5 2.4 2.4 3.4 0.2 0.4 UNIT V 0.8 Vee; MIN, MAX 2 0.8 V -1.5 V V 3.4 0.2 1 0.4 1 V mA IIH High-level input current Vee; MAX, VI; 2.4 V 40 40 pA IlL Low-level input current Vee; MAX, VI; 0.4 V -1.6 -1.6 mA lOS Short-circuit output current S Vee; MAX -57 mA lee Supply current Vee; MAX, 56 mA -20 See Note 2 -55 -18 49 34 34 t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. :j:AII typical values are at Vee; 5 V, TA; 25°e. § Not more than one output should be shorted at a time. NOTE 2: lee is measured with all inputs grounded and all outputs open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS MIN Propagation delay time, low-to-high-Ievel output, tpLH from A, B, e, or 0 inputs through 3 levels of logic Propagation delay time, high-to-Iow-Ievel output, tpHL tpLH from A, B, e, or D inputs through 3 levels of logic eL;15pF, Propagation delay time, low-to-high-Ievel output, See Note 3 RL; 400 from either strobe input Propagation delay time, high·to-Iow-Ievel output, tpHL from either strobe input NOTE 3: • n, TYP MAX UNIT 24 36 ns 22 33 ns 20 30 ns 18 27 ns Load circuit and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·173 TYPES SN54L154, SN74J.15~ 4-UN E-TO-16-UN E DECO 0 ERS/ OEM ULTIPLEXERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ........ . Input voltage. . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54L 154 Circuits SN74L 154 Circuits Storage temperature range 7V 5.5V _55°C to 125°C O°C to 70°C _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54Ll54 MIN Supply voltage, Vee 4.5 High-level output current, 10H NOM SN74Ll54 MAX MIN 5.5 4.75 5 NOM 5 -400 Low-level output current, 10L 8 Operating free-air temperature, T A -55 125 0 UNIT MAX 5.25 V -400 ).LA 8 mA 70 °e electrical c.haracteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH H igh·level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High·level output voltage VOL • MIN TVPt MAX UNIT 2 Low·level output voltage Vee = MIN, II = -12mA Vee - MIN, VIH - 2 V, VIL = 0.8 V, 10H = -400).LA Vee - MIN, VIH - 2 V, VIL = 0.8 V, 10L = 8 mA 2.4 V 0.8 V -1.5 V V 3.4 0.2 0.4 V II Input current at maximum input voltage Vee - MAX, VI - 5.5 V 1 IIH High·level input current Vee = MAX, VI - 2.4 V 20 IJA IlL Low·level input current Vee';·MAX, VI; 0.4 V -0.8 mA lOS Short·circuit output current § Vee = MAX -29 mA lee Supply current -9 Vee = MAX, I SN54L154 17 25 See Note 2 17 28 ISN74Ll54 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. t Ali typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time. NOTE 2: lee is measured with all inputs grounded and ali outputs open. switching characteristics, Vee = 5 V, TA = 25°e TEST eONDITIONS PARAMETER Propagation delay time, low-to·high·level output, tpLH tPLH from A, B, e, or D inputs through 3 levels of logic eL=15pF, Propagation delay time, low-to-high·level output, MAX UNIT 48 72 ns 44 66 ns See Note 3 40 60 ns 36 54 ns RL=800n, from either strobe input Propagation delay time, high-to·low·level output, tPHL TVP from A, B, e, or D inputs through 3 levels of logic Propagation delay time, high·to-Iow-Ievel output, tpHL MIN from either strobe input NOTE 3: Load circuit and voltage waveforms are shown on page' 3-10. 1076 7·174 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54155, SN54156, SN54LS155, SN54LS156, SN74155, SN74156, SN74LS155, SN74LS156 DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS TTL MSI BULLETIN NO. DL-S 7711850, MARCH 1974-REVISED AUGUST 1977 • Applications: Dual 2-to-4-Line Decoder Dual l-to-4-Line Demultiplexer 3-to-8-Line Decoder l-to-8-Line Demultiplexer • Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words Input Clamping Diodes Simplify System Design • • SN54155, SN54156, SN54LS155, SN54LS156 ••• J OR W PACKAGE SN74155, SN74156, SN74LS155, SN74LS156 ___ J OR N PACKAGE (TOP VIEW) Choice of Outputs: Totem Pole ('155, 'LS155) Open-Collector ('156, 'LS156) TYPES '155, '156 'LS155 'LS156 TYPICAL AVERAGE PROPAGATION DELAY 3 GATE LEVELS 21 ns 18 ns 32 ns TYPICAL POWER DISSIPATION 125mW 31 mW 31 mW positive logic: see function table description These monolithic transistor-transistor-Iogic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both,sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section_ The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design. Series 54 and 54LS are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and 74LS are characterized for operation from O°C to 70°C. schematics of inputs and outputs '155, '156 '155 EQUIVALENT OF EACH INPUT vee TYPICAL OF ALL OUTPUTS vee=Q-- 4 kn. NOM INPUT • '156 TYPICAL OF ALL OUTPUTS _ _ ~OUT>UT -OUTPUT 'LS155, 'LS156 'LS155 'LS156 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS Vcc VCC---..--20 kn. NOM INPUT_~-+-~~ '----+-- 0 UTPUT 877 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-175 TYPES SN54155, SN54156, SN54LS155, SN54LS156, SN74155, SN74156, SN74LS155, SN74LS156 DUAL 2-UNE-TO-4-UNE DECODERS/DEMULTIPLEXERS functional block diagram and logic FUNCTION TABLES 2·LlNE·T0-4·LlNE DECODER OR '·LlNE·TO-4·LlNE DEMULTIPLEXER INPUTS SELECT ST~gBE _ _ _ _----. DATA lC OUTPUTS STROBE DATA B A lG lC 1Y2 lY3 X X H X H H H H L L L H L H H H L H L H H L H H H L L H H H L H H H L H H H H L X X X L H H H H 2YO 2Yl lYO 1Yl INPUTS SELECT SELECT B SELECT OUTPUTS STROBE DATA B A 2G 2C 2Y2 2Y3 X X H X H H H H L L L L L H H H L H L L H L H H H L L L H H L H H H L L H H H L X X X H H H H H A FUNCTION TABLE 3·LlNE·TO·8·LINE DECODER OR '·LlNE·TO·8·LlNE DEMULTIPLEXER INPUTS ct II OUTPUTS STROBE SELECT OR DATA (0) (1) (2) (3) (4) (5) (6) (7) B A X X X G* H H H H H H H H H L L L L L H H H H H H H L L H L H L H H H H H H L H L L H H L H H H H H L H H L H H H L H H H H H L L L H H H H L H H H H L H L H H H H H L H H H H L L H H H H H H L H H H H L H H H H H H H L 2YO 2Yl 2Y2 2Y3 lYO lYl 1Y2 lY3 tC = tG = inputs 1 G and 2G connected together = high level, L = low level, X = irrelevant H inputs 1 C and 2C connected together absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage: '155, '156 'LS155, 'LS156 Off·state output voltage: '156 'LS156 Operating free·air temperature range: SN54', SN54LS' Circuits SN74', SN74LS' Circuits Storage temperature range 7V 5.5V 7V 5.5 V 7V -55°C to 125°C . O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 181 7-176 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54155, SN74155 DUAL 2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS REVISED AUGUST 1977 recommended operating conditions SN54155 MIN Supply voltage, Vee NOM 4.5 SN74155 MIN NOM MAX 5.5 4.75 5 5.25 V -800 j.lA 16 mA 70 °e 5 High·level output current, 10H -800 Low·level output current, 10L 16 Operating free-air temperature, T A UNIT MAX -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54155 PARAMETER' SN74155 TEST CONDITIONSt MIN VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High·level output voltage TYP+ UNIT MAX V 2 VOL Low-level output voltage II Input current at maximum input voltage Vee= MIN, II = -8 mA Vee = MIN, VIH = 2V, VIL = 0.8 V, 10H = -800 j.lA Vee= MIN, VIH=2V, VIL = 0.8 V, 10L = 16 mA Vee = MAX, VI = 5.5 V 2.4 0.8 V -1.5 V 3.4 0.2 V 0.4 1 V mA IIH High·level input current Vee = MAX, VI = 2.4 V 40 j.lA IlL Low-level input current Vee = MAX, VI=O.4V -1.6 mA lOS Short-circuit output current § Vee = MAX lee Supply current SN54155 -20 -55 SN74155 -18 -57 Vee = MAX, SN54155 25 35 See Note 2 SN74155 25 40 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time. NOTE 2: I CC is measured with outputs open, A, B, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded. switching characteristics, Vee = 5 V, TA PARAMETER~ FROM TO LEVELS (INPUT) (OUTPUT) OF LOGIC y 2 A, B, 2e, tpLH = 25°e 1G,or2G A, B, 2C, TEST CONDITIONS MIN TYP 13 MAX UNIT 20 ns ns Y 2 tpLH AorB Y 3 tpHL AorB Y 3 tPLH 1C 16 24 ns 1e Y y 3 tpHL 3 20 30 ns tpHL 1G,or2G eL = 15 pF, RL=400n, See Note 3 18 27 21 32 ns 21 32 ns ~ tp LH "" propagation delay time, low-to-high·level output tpH L "" propagation delay time, high·to-Iow-Ievel output NOTE 3: Lo~ circuit andlvoltage waveforms are shown on page 3-10. 877 TEXASINCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 7-177 TYPES SN54LS155, SN74LS155 DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS REVISED OCTOBER 1976 recommended operating conditions SN54LS155 MIN NOM 4.5 Supply voltage, Vee 5 High-level output current, 10H SN74LS155 MAX MIN 5.5 4.75 NOM 5 -400 MAX V -400 J.lA 8 mA °e 4 Low-level output current, 10L Operating free-air temperature, T A -55 125 UNIT 5.25 0 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS155 TEST CONDITIONSt PARAMETER MIN VIH High-level input voltage Low-level input voltage SN74LS155 TYPt MAX MIN 2 VOH High-level output voltage = -18mA VCC- MIN, II Vee- MIN, VIH - 2V, 2.5 0.7 0.8 V -1.5 -1.5 V 3.4 2.7 VIL = VIL max, 10H = -400 J.lA Vee- MIN, VOL Low-level output voltage VIH = 2 V, 0.25 0.4 IIOL =8mA VIL = VIL max I nput current at IIOL - 4 mA UNIT V 2 VIL VIK I nput clamp voltage TYPt MAX 3.4 V 0.25 0.4 0.35 0.5 V Vee= MAX, VI = 7V 0.1 0.1 IIH High-level input current Vee= MAX, VI=2.7V 20 20 J.lA IlL Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA lOS Short-circuit output current!? ICC Supply current Vce = MAX -42 mA II maximum input voltage Vee = MAX, -6 See Note 2 -40 6.1 -5 10 mA 10 mA 6.1 tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time. NOTE 2: ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G Inputs grounded. II switching characteristics, Vee PARAMETER1f FROM TO LEVELS (INPUT) (OUTPUT) OF LOGIC Y 2 Y 2 A, B, 2e, tpLH tpHL = 5 V, TA = 25°e lG,or2G A, B, 2e, lG,or2G SN54LS155 TEST CONDITIONS SN74LS155 MIN eL = 15 pF, RL=2kn, TYP UNIT MAX 10 15 ns 19 30 ns 17 26 ns 19 30 ns tpLH AorB Y 3 tpHL A orB Y 3 tpLH le Y 3 18 27 ns tpHL le Y 3 18 27 ns See Note 4 ~ tpLH == propagation delay time, low-to-high-Ievel output tpH L == propagation delay time, hlgh-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1076 7-178 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54156, SN74156 DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS REVISED AUGUST 1917 recommended operating conditions SN54156 MIN Supply voltage, VCC NOM 4.5 SN74156 MAX MIN 5.5 4.75 5 High-level output voltage; VOH NOM 5 5.5 Low-level output current, IOL 16 Operating free-air temperature, T A -55 125 0 MAX UNIT 5.25 V 5.5 V 16 mA 70 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54156 PARAMETER TEST CONDITIONSt SN74156 MIN VIH High-level input voltage VIL Low-level input voltage VIK I"put clamp voltage IOH High-level output current VOL Low-level output voltage II TYPf UNIT MAX 2 V 0.8 Vee = MIN, II = -8 mA Vee= MIN, VIH=2V, VIL = 0.8 V, VOH = 5.5V Vee= MIN, VIH = 2 V, VIL = 0.8 V, IOL" 16mA Input current at maximum input voltage Vee= MAX, VI = 5.5 V 0.2 V -1.5 V 250 JJ.A 0.4 1 V mA IIW High-level input current Vee = MAX, VI = 2.4 V 40 JJ.A IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA ICC Supply current Vee = MAX, See Note 2 ISN54156 ISN74156 25 35 25 40 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. fAil typical values are at V CC = 5 V, T A = 25° c. NOTE 2: I CC is measured with outputs open, A, B, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded. switching characteristics, Vee PARAMETERl1 =5 V, TA = 25°e FROM TO LEVELS (INPUT) (OUTPUT) OF LOGIC Y 2 TEST CONDITIONS MIN TYP MAX UNIT 15 23 ns 20 30 ns 23 34 ns 23 34 ns • I A, B, 2e, tpLH tpHL lG,or2G A, B, 2e, y 2 3 lG,or2G CL" 15 pF, RL=400n, tpLH AorB tpHL AorB Y Y tpLH 1e Y 3 18 27 ns tpHL 1C Y 3 22 3~ ns See Note 3 3 11 tpLH == propagation delay time, low·to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-179 TYPES SN54LS156, SN74LS156 DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS recommended operating conditions SN54LS156 Supply voltage, VCC NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 High-level output voltage, VOH Low-level output current, IOL Operating free-air temperature, T A SN74LS156 MIN -55 UNIT V 5.5 5.5 4 8 mA 70 °c 125 0 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH High-level output current VOL SN54LS156 TEST CONDITIONSt PARAMETER MIN TYP+ SN74LS156 MAX 2 Vce~ II MIN, Vec= MIN, Low-level output voltage ~ VIH = 2 V, VOH=5.5V VCC= MIN, VIH = 2 V, VIL = VIL max Input current at TYP+ MAX 2 -18 mA VIL = VIL max, MIN V 0.7 0.8 V -1.5 -1.5 V 100 IIOL = 4 inA 0.25 UNIT 100 0.4 IloL = 8 mA 0.25 0.4 0.35 0.5 pA V Vee = MAX, VI =7 V 0.1 0.1 IIH High-level input current Vce = MAX, VI = 2.7 V 20 20 pA IlL Low-level input current Vee- MAX, VI - 0.4 V -0.4 -0.4 mA Ice Supply current Vec= MAX, See Note 2 10 mA II maximum input voltage 6.1 10 6.1 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° c. NOTE 2: ICC is measured with outputs open, A, B, and 1 C inputs at4.5 V, and 2C, 1 G, and 2G inputs grounded. • switching characteristics, Vee PARAMETER~ FROM TO LEVELS (INPUT) (OUTPUT) OF LOGIC Y 2 A, B,2C tPLH = 5 V, TA = 25°e 1G,or2G A, B,2C, SN54LS15G TEST CONDITIONS SN74LS156 MIN UNIT TYP MAX 25 40 ns 34 51 ns 31 46 ns 34 51 ns Y 2 tPLH Aor B Y 3 tpHL A or B Y 3 tPLH 1C Y 3 32 48 ns tpHL 1C Y 3 32 48 ns tpHL 1G,or2G CL = 15 pF, RL=2kr!, See Note4 ~ tp LH == propagation delay time, low·to-high-Ievel output tpH L == propagation delay time, h igh-to·low-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1076 7-180 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54157, SN54L157, SN54LS157, SN54LS158, SN54S157, SN54S158, SN74157, SN74L157, SN74LS157, SN74LS158, SN74S157, SN74S158 ·QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS BULLETIN NO, features • • o LoS 7711847 MARCH 1974-REVISED AUGUST 1977 SN54157, SN54LS157, SN54S157 ••• J OR W PACKAGE SN54U57 ___ J PACKAGE Buffered Inputs and Outputs SN74157, SN74L157, SN74LS157, SN74S157 •• , J OR N PACKAGE (TOP VIEW) Three Speed/Power Ranges Available INPUTS TYPICAL TYPES PROPAGATION TIME '157 VCC STR08E 4A INPUTS OUTPUT r---"---.. 48 4Y 3A 3B 3Y POWER DISSIPATION 150mW 9 ns 18ns 75mW 'LS157 9 ns 49mW 'S157 5 ns 250mW 'U57 OUTPUT ~ TYPICAL AVERAGE 'LS158 7 ns 24mW 'S158 4 ns 195mW 3Y applications • Expand Any Data Input Point SELECT 1A 1B '-.,r---J INPUTS • Multiplex Dual Data Buses • Generate Four Functions of Two Variables (One Variable Is Common) • Source Programmable Counters 1Y 2A 2B 2Y '-.,r---J OUTPUT INPUTS GND OUTPUT positive logic: Low level at S selects A inputs High level at S selects B inputs SN54LS158, SN54S158, •• J OR W PACKAGE SN74LS158, SN74S158 • , ,J OR N PACKAGE (TOPVIEW) descrip~ion These monolithic data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided, A 4-bit word is selected from one of two sources and is routed to the four outputs. The '157, 'L 157, 'LS157, and 'S157 present true data whereas the 'LS158 and 'S158 present inverted data to minimize propagation delay time. INPUTS OUTPUT ~ Vee STROBE 4A 48 INPUTS OUTPUT r---"---.. 4Y 3A 38 3Y II FUNCTION TABLE INPUTS STROBE SELECT OUTPUT Y A B '157, 'L157, 'LS158 'LS157:S157 'S158 H X X X L H L L L X L H L L H X H L L H X L L H L H X H H L SELECT 1A 1B '-.,r---J INPUTS 1Y 2A 28 '-v---' OUTPUT INPUTS 2Y GND OUTPUT positive logic: Low level at S selects A inputs High level at S selects B inputs H = high level, L = low level, X = irrelevant absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) Input voltage: '157, 'L157, 'S158 'LS157, 'LS158 Operating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits SN74', SN74L', SN74LS', SN74S' Circuits Storage temperature range 7V 5_5 V 7V -55°C to 125°C O°C to 70°C _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 877 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-181 TYPES SN54157, SN54L157, SN74157, SN74L157, QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS functional block diagram '157, 'L157 1A 1B 2A 2B 3A 3B 4A 4B SELECT STROBE • (15) schematics of inputs and outputs '157, 'L157 '157, 'L 157 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ------vee Vee---.--- INPUT OUTPUT '157: Req 'L157: Req = 4 kn = 8 kn NOM NOM '157: R 'L157: R = 100 n = 200 n NOM NOM 374 7·182 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS157, SN54LS158, SN54S157, SN54S158, SN74LS157, SN74LS158, SN74S157, SN74S158 QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS functional block diagrams 'LS157, 'LS158 (2) EQUIVALENT OF EACH INPUT lA ,vee , , Req (3) lB 2A o schematics of inputs and outputs 'LS157, 'S157 INPUT (5) (6) 2B (11) 3A -- = 8.5 kn NOM kn NOM S or G inputs: Req A or B inputs: Req = 17 TYPICAL OF ALL OUTPUTS 3B (10) ---~-vee (14) 4A OUTPUT (13) 4B STROBE G SELECT S (15) (1) 'LS158, 'S158 'S157, 'S158 (2) lA lB (3) v cc o Req (5) 2A 2B - EQUIVALENT OF EACH INPUT INPUT, (61 (11) 3A S or G inputs: Req A or B inputs: Req I -- = 1.4 kn NOM = 2.8 kn NOM TYPICAL OF ALL OUTPUTS (10) 3B Vee (14) 4A (13) OUTPUT 4B STROBE G (15) (1) SELECT S 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-183 TYPES SN54157, SN74157 QUADRUPLE 2-UNE-TO-1-UNE DATA .SELECTORS/MULTIPLEXERS recommended operating conditions SN74157 SN54157 MIN NOM 4.5 Supply voltage, Vee MAX MIN 5.5 4.75 5 NOM 5 -800 High·level output current, IOH MAX 5.25 V -800 j.lA 16 mA 70 °e 16 Low-level output current, IOL -55 Operating free-air temperature, T A 125 UNIT 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL VIK Low-level input voltage VOH VOL SN54157 TEST eONDITIONSt PARAMETER MIN TVPt SN74157 MAX 2 I nput clamp voltage High-level output voltage Low-level output voltage Vee = MIN, 11=-12mA Vee = MIN, VIH = 2 V, VIL = 0.8 V, IOH = -800 /-LA Vee = MIN, VIH = 2 V, VIL = 0.8 V, 10L = 16 mA 2.4 MIN TVPt MAX V 2 0.8 0.8 V -1.5 -1.5 V 2.4 3.4 0.2 UNIT 0.2 0.4 V 3.4 0.4 1 1 V mA II Input current at maximum input voltage Vee= MAX, VI - 5.5 V IIH High-level input current Vee= MAX, VI = 2.4 V 40 40 /-LA IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 -1.6 mA lOS Short-circuit output currentli Vee = MAX -55 mA Ice Supply current Vee = MAX, 48 mA -20 See Note 2 -55 30 -18 48 30 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a t·ime and duration of short-circuit should not exceed one second. NOTE 2: lee is measured with 4.5 V applied to all Inputs and all outputs open. • switching characteristics, Vee PARAMETERlI tPLH = 5 V, TA =25°e TEST CONDITIONS FROM (INPUT) Data tPHL tPLH eL=15pF, Strobe RL = 400 tpHL tPLH Select tpHL , tpLH tpHL == propagation delay time, == propagation delay time, n, See Note 3 MIN TVP MAX UNIT 9 14 9 14 13 20 14 21 15 23 18 27 ns ns ns low-to-high-Ievel output high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-184 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54L157, SN74L157 QUADRUPLE 2-LlNE-TO-l-LiNE DATA SELECTORS/MULTIPLEXERS recommended operating conditions SN54L157 MIN Supply voltage, Vee 4.5 NOM SN74L157 MAX MIN NOM 5.5 4.75 5 5 High-level output current, IOH 5.25 -400 Low-level output current, IOL 8 Operating free·air temperature, T A -55 125 MAX 0 UNIT V -400 p.A 8 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low·level input voltage VIK Input clamp voltage TEST eONDITIONSt TYP+ MAX UNIT 2 VOH High-level output voltage VOL MIN Low·level output voltage Vee; MIN, II; -12mA Vee; MIN, VIH;2V, VIL; 0.8 V, IOH; -400p.A Vee; MIN, VIH;2V, VIL; 0.8 V, IOL;8mA 2.4 V 0.8 V -1.5 V 3.4 0.2 V 0.4 V II Input current at maximum input voltage Vee; MAX, VI; 5.5 V 1 IIH High·level input current Vee - MAX, VI - 2.4 V 20 p.A IlL Low·level input current Vee; MAX, VI; 0.4 V -0.8 mA lOS Short·circuit output current§ Vee; MAX -28 mA ICC Supply current Vee; MAX, 24 mA -9 See Note 2 15 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee; 5 V, T A; 25°e. §Not more than one output should be shorted at a time. NOTE 2: IcC is measured with 4.5 V applied to all inputs and all outputs open. switching characteristics, Vee PARAMETER~ tPLH I = 5 V, T A = 25°e FROM (INPUT) TEST CONDITIONS tpHL tpLH eL;15pF, Strobe RL;800n, tPHL tPLH See Note 3 Select tpHL ~ tpLH tpHL MIN TYP 18 Data MAX UNIT 28 18 28 26 40 28 42 30 46 36 54 ns ns ns == propagation delay time, low·to-high-Ievel output == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load cirCuit and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-185 TYPESSN54LS157, SN54LS158, SN74LS157, SN74LS158 QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED DECEMBER 1980 recommended operating conditions SN54LS' Supply voltage, Vee SN74LS' NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -400 IJA 8 mA 70 °e High-level output current, IOH -400 Low-level output current, IOL 4 Operating free·air temperature, T A UNIT MIN -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage Input current input voltage IIH IlL Vee = MIN, II = -18mA Vee = MIN, VIH=2V, VIL = MAX, IOH = -4001JA Vee = MIN, VIH = 2 V, VIL = MAX Vee= MAX, High-level S or G input input current A or B input Low-level S or G input input current A or B input Vee = MAX, Vee = MAX, 2.5 MIN TYPt MAX V 0.8 V -1.5 -1.5 V 2.7 0.4 IIOL = 8mA 3.4 V 0.25 0.4 0.35 0.5 0.2 0.2 0.1 0.1 40 40 VI = 7V V mA VI = 2.7 V VI = 0.4 V 20 20 -0.8 -0.8 -0.4 -100 -20 See Note 2 UNIT 0.7 3.4 0.25 IIOL = 4mA Vec = MAX Vee = MAX, II SN74LS' MAX 2 A or B input Supply cu rrent ICC TYPt S or G input Short-circuit output current § lOS MIN 2 at maximum II SN54LS' TEST CONDITIONSt -0.4 -20 -100' 'LS157 9.7 16 9.7 16 'LS158 4.8 8 4.8 8 'LS158 6.5 11 6.5 11 IJA mA mA mA Vec = MAX, All A inputs at 4.5 V, All other inputs at 0 V tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAil typical values are at Vee = 5 V, T A = 25°C~ § Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second. NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open. switching characteristics, Vee PARAMETER~ tPLH = 5 V, TA = 25°e FROM (INPUT) CL=15pF, Strobe tPHL tPLH 'LS157 MIN Data tpHL tPLH TEST CONDITIONS RL = 2 k!l, See Note 4 Select tpHL TYP 'LS158 MAX MIN TYP MAX 9 14 7 12 9 14 10 15 13 20 11 17 14 21 18 24 15 23 13 20 18 27 16 24 UNIT ns ns ns ~ tp LH == propagation delay time, low-to-high-Ievel output tp H L == propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1280 7-186 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54S157, SN54S158, ,SN74S157, SN74S158 QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED AUGUST 1977 recommended operating conditions SN54S157 SN74S1'57 SN54S158 MIN NOM MIN 5.5 4.75 5 4.5 Supply voltage, Vee SN74S158 MAX NOM 5 UNIT MAX 5.25 V -1 mA 20 mA "e -1 High-level output current, 10H 20 Low-level output current, 10L 125 -55 Operating free-air temperature, T A 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER SN54S157 SN54S158 SN74S157 SN74S158 UNIT MIN TYP+ MAX MIN TYP+ MAX VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage 2.5 3.4 2.5 3.4 VIL = 0.8 V, 10H = -1 mA Series 745 2.7 3.4 2.7 3.4 Vee = MIN, VIH=2V, VIL = 0.8 V, IOL = 20mA I High-level input current IlL Low-level input current los Short-circuit ouput current § Vee = MAX, VI = 2.7 V Vee = MAX, VI = 0.5 V -40 Vee = MAX Vee = MAX, All inputs at 4_5 V, 50 V 0.5 0.5 1 1 100 100 50 50 -4 -4 -2 -2 -100 See Note 2 Supply current V ISeries 545 IIH lee -1.2 VIH=2V, Input current at maximum input voltage Vee = MAX, VI = 5.5 V A or B input V -1.2 Vee= MIN, II S or G input 0.8 11=-18mA Low-level output voltage A or B input 0.8 Vee= MIN, VOL S or G input V 2 2 -40 -100 39 78 IlA mA mA 61 mA Vee = MAX, A inputs at 4.5 V, B,G,S, inputs at 0 V, V mA 81 See Note 2 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Note 2: lee is measured with all outputs open. switching characteristics, Vee =5 V, TA = 25°C PARAMETERl1 tPLH tPHL tPLH FROM TEST CONDITIONS (lNPUTI SN54S158 SN74S157 SN74S158 MIN Data eL = 15pF, RL = 280 Strobe tpHL tpLH SN54S157 n, See Note 3 Select tPHL TYP MAX MIN TYP • UNIT MAX 5 7.5 4 6 4.5 6.5 4 6 8.5 12.5 6.5 11.5 7.5 12 7 12 9.5 15 8 12 9.5 15 8 12 ns ns ns 11 tpLH == propagation delay time, 10w-tO-high-level output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 877 TEXAS INSTRUMENTS INCORPOR~TED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-187 TTL MSI TYPES SN54159, SN74159 4-UN E-TO-16-UN E DECO DERS/D EMU LTI PLEXERS WITH OPEN-COLLECTOR OUTPUTS BULLETIN NO. DL·S 7211800, DECEMBER 1972 • Open-Collector Outputs for Interfacing with MOS or Memory Decoders/Drivers • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data from One I nput Line to Any One of 16 Outputs • Typical Average Propagation Delay Times: 24 ns through 3 Levels of Logic 19 ns from Strobe Input • Output Off-State Current is Less Than 50l1A • Fully Compatible with Most TTL, DTL, and MSI Circuits SN54159 ••• J OR W PACKAGE SN74159 ••• J OR N PACKAGE (TOP VIEW) positive logic: see function table description Each of these monolithic, 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive open-collector outputs when both the strobe inputs, G1 and G2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for implementing MOS memory decoding or for interfacing with discrete memory address drivers. For ultra-high-speed applications, the SN54S138/SNi4S138 or SN54S139/SN74S139 is recommended. • These circuits are fully compatible for use with most other TTL and DTL circuits. Input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design. Input buffers are used to lower the fan-in requirement to only one normalized Series 54/74 load. A fan-out to 10 normalized Series 54/74 loads in the low-level state is available from each of the sixteen outputs. Typical power dissipation is 170 mW . The SN54159 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74159 is characterized for operation from O°C to 70°C. function table Same as SN54154, SN74154. See page 7-172. functional block diagram Same as SN54154, SN74154. See page 7-172. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage . . . . . . . . Off-state output voltage Operating free-air temperature range: SN54159 Circuits SN74159 Circuits Storage temperature range 7V 5.5 V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal 1076 7·188 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 15222 TYPES SN54159, SN74159 4-UNE-TO-16-UNE DECODERS/DEMULTIPLEXERS WITH OPEN-COLLECTOR OUTPUTS recommended operating conditions SN54159 MIN NOM 4.5 Supply voltage, Vee 5 SN74159 MAX MIN NOM MAX 5.5 4.75 5 5.25 16 Low-level output current, IOL 55 Operating free-air temperature, T A 125 0 UNIT V 16 rnA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH High-level output current VOL Low-level output voltage II Input current at maximum input voltage Vee = MAX, VI = 5.5 V MIN TYP+ MAX UNIT V 2 Vee = MIN, 11= -12 rnA Vee = MIN, VIH = 2 V, VIL = 0.8 V, VOH = 5.5 V Vee= MIN, VIH = 2V, VIL = 0.8 V, IOL = 16mA 0.8 V -1.5 V 50 0.4 1 p.A V rnA IIH High-level input current Vee = MAX, VI = 2.4 V 40 p.A IlL Low-level input current Vee= MAX, VI = 0.4 V -1.6 rnA ICC Supply current Vee= MAX, 56 rnA All inputs grounded 34 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at Vee = 5 V, T A = 25° e. switching characteristics, Vee =5 V, TA = 25°e TEST CONDITIONS PARAMETER Propagation delay time, low-to-high-Ievel output, tpLH from A, B, e, or D inputs through 3 levels of logic Propagation delay time, low-to-high-Ievel output, tPLH eL=15pF, RL = 400 n, MAX UNIT 23 36 ns 24 36 ns 15 25 ns 22 36 ns See Note 2 from either strobe input Propagation delay time, high-to-Iow-Ievel output, tPHL TYP from A, B, e, or D inputs through 3 levels of logic Propagation delay time, high-to-Iow-Ievel output, tpHL MIN from either strobe input NOTE 2: See load circuit and waveforms shown on page 3-10. • schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT Vee ----+---4 kn NOM __ ~OU'PU' INPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·189 I TTL MSI TYPES SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-81T COUNTERS 'BULLETIN NO DL-57711385 '160, '161,'LS160A, 'LS161A, "SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163", FULLY SYNCHRONOUS COUNTERS • Internal Look-Ahead for Fast Counting • Carry Output for n-Bit Cascading • Synchronous Counting • Synchronously Programmable • Load Control Line • Diode-Clamped Inputs TYPE TYPICAL PROPAGATION TIME, CLOCK TO Q OUTPUT '160 thru '163 'LS160A thru 'LS163A 'S162 and 'S163 14 ns 14 ns 9 ns SERIES 54', 54LS', 54S' ••• J OR W PACKAGE SERIES 74', 74LS', 745' • , • J OR N PACKAGE (TOP VIEW) TYPICAL TYPICAL MAXIMUM POWER CLOCK DISSIPATION FREQUENCY 32MHz 305mW 32MHz 93mW 70MHz 475mW CLEAR CLOCK ABC D ENABLE GND ~P DATA INPUTS logic: see description description These synchronous, presettable counters feature an internal carry look·ahead for application in high·speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. • These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163 . The clear function for the '160, '161, 'LS160A, and 'LS161 A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low·to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow·level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or clear) that will' modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The 'LS160A thru 'LS163A are completely new designs. Compared to the original 'LS160 thru 'LS163, they feature O-nanosecond'minimum hold time and reduced input currents II H and II L. , 877 7·190 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 Col ..... ~ c ::s SN54160, SN74160 SYNCHRONOUS DECADE COUNTERS SN54163, SN74163 SYNCHRONOUS BINARY COUNTERS SN54162, SN74162 synchronous decade counters are similar; however, the clear is synchronous as shown for the SN54163, SN74163 binary counters at right. SN54161, . SN74161 synchronous binary counters are similar; however, the clear is asynchronous as shown for the SN54160, SN74160 decade counters at left. n .... 0' ::s !!a. C- O n ;:; a. iii' ce @ LOAD :rJ 191 LOAD 191 A~--~------ri~ ~~ 3 ~~ en (14) (14) OA DA;A(3) II DA ..... < ""C ~ m "...., g [T1 >< -! ~ > (f1 ~ Z_ ~8Z ~~(f1 DABTA t II ID - o (13) (13) DB 141 D~TA(4) ~ CL~ CLOCK III DB (12) -= U"I (2) ..... (12) Dc [T1 IIII D~TAI51 D~TA(5J l~cL~ Dc ::c ::::leI ~c:: o~ 2 +=a en ~~ . 0-1 ;;0 en en IIII C ~ en en <2 2U"1 Z -I C"")+=a (f1 (11) II DA~AI61 I (11) DO CLEAR 171 T 1101 !ll IIIII I 0~ 2 en 0 2 C ....... en~ .=..... +=am ENABLE p ::CC; ::::IeI W DA~AI6J I~ DO 1- ~~::~~ OUTPUT ~ ..... :1: C"")::::IeI OC cen 22 ............ m+=a ::::IeI- en~ ~ ~ II II :!:! CQ N .... « o· n c: SN54LS160A, SN74LS160A SYNCHRONOUS DECADE COUNTERS SN54LS163A, SN74LS163A SYNCHRONOUS BINARY COUNTERS SN54LS162A, SN74LS162A synchronous decade counters are similar; however the clear is synchronous as shown for the SN54LS163A, SN74LS163A binary counters at right. SN54LS161A, SN74LS161A synchronous binary counters are similar; however, the clear is asynchronous as shown for the SN54LS160A, SN74LS160A decade counters at left. en ::l ~ ::l !!!. c- O' n ';:;' Co --I 2~ m =en ~en 22 oc.n C~ iii' enren 3 cae ce @ ~.en ::;> n-t o::C ." 0 ~ ~ i:i CO 0 x c= 2 C ~ tTl -t men en c.n =2 >< > OATAA..!!!. _(J) I I I J I I I ~ DATA A (3J r- z_ en § 8Z ~(J) OJ en w ]> . 0.., ~t:J OJ 0 DATA Bill ~ ~c:: .e, ;;1 x e, (11 OJ m (11 I I. J I I I DATA B 141 en 2 ..... ~ o~ tT'J Z r- (J) en e .., - en > DATA CiS) I I I J I I I I I I ~ DATAC~f--tI-1If--tI-1II-----+--..-J -t = = C en 2 ..... ~ r- DATAD~ I _ L------===========lU ., (Xl o en DATAD 161 115) RIPPLE g~~~T en w ~ L.=f"l (151~~;jT > TYPES SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-81T COUNTERS REVISED OCTOBER 1976 functional block diagrams Ul a: w IZ :J ·0 U > a: ex: z iii Ul :J o Z oa: :x: u z > Ul M (Q en .: "Z ~ Ul Ul ;g Z Ul • Ul a: w I- Z :J o U w ex: u o w o Ul :J o Z o a: :x: u z > Ul N (Q en ;:!: z Ul N(Q en ;g zUl 1076 TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-193 TYPES SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162, SN74160, SN74162, SN74LS160A, SN74LS162A, SN74S162 SYNCHRONOUS 4-81T COUNTERS '160, '162, 'LS160A, 'LS162A, 'S162 DECADE COUNTERS typical clear, preset, count, and inhibit sequences Illustrated below is the following sequence: 1. Clear outputs to zero ('160 and 'LS160A are asynchronous; '162, 'LS162A,and 'S162 are synchronous) 2. Preset to BCD seven 3. Count to eight, nine, zero, one, two, and three 4. Inhibit CLEAR-U U LOAD c= L= A~ B~ DATA INPUTS c= c~ , - 1-- 0 CLOCK I ENABLE P • :I :I 1 ENABLE T I I OA I, ---I I I I I I I I I I I -~-. - --, . r---1I~_ _ _ _ _ _ .-..! _,----1 OB _ OUTPUTS __I - ~ ~ -I r-----iI~____________________~------------------_,----1 I - -, --II 1;.-----, 00 _ _, I Oc_ 1 I RIPPLE.CARRY OUTPUT I 1 I I Iii I i .---, ----+I--~I---;I----I~--II I I !7 i8 I I~ 9 ____________~_____________________ 0 2 3: ..I · - - - - C O U N T - - -........I...·- - - I N H I B I T - - - - SYNC PRESET ASYNC CLEAR CLEAR 1076 7-194 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALL.AS, TEXAS 75222 TYPES SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163, SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163 SYNCHRONOUS 4-81T COUNTERS '161, 'LS161A, '163, 'LS163A, 'S163 BINARY COUNTERS typical clear, preset, count, and inhibit sequences Illustrated below is the following sequence: 1. Clear outputs to zero ('161 and 'LS161A are asynchronous; '163, 'LS163A, and 'S163 are synchronous) 2. Preset to binary twelve 3. Count to thirteen, fourteen fifteen, zero, one, and two 4. Inhibit u LOAD A ____ B DATA INPUTS - ,-- ~---------~I 1-- 1_- -----~-------~I c ...Jr---i------., . .1 ' _- - D ...J~---.,.---- CLOCK • ENABLE P I 1 ENABLE T 1 I OA _ OB - OUTPUTS I --,-, -2 _ I ___......;~~ --, - , I---......;~--------' _, - --, Oc_ --1 -, _~~ I I OD-;;~ --1-1 I I r---l 1 RIPPLE-CARRY 1 I J I OUTPUT --~I-~I-~'----14-~15 O~----2~-------------- I I I f2 .ll~........ ___ COUNT _ _ _---+tII..•____ INHIBIT _ _ __ SYNC PRESET CLEAR ASYNC CLEAR 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 ·7-195 TYPES SN54160 THRU SN54163, SN74160 THRU SN74163 SYNCHRONOUS 4-81T COUNTERS schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC------------~----------- INPUT Clock: Enable T: Clear, Enable P: A, B, C, D: Req = 2.8 kU NOM Req = 2 kU NOM Req = 4 kU NOM Req = 6 kU NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) • Supply voltage, VCC (see Note 1) Input voltage . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature range: SN54' Circuits SN74' Circuits Storage temperature range NOTES: 7V 5.5 V 5.5 V D D -55 C to 125 C ODC to 70DC D D -65 C to 150 C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the count enable inputs P and T. recommended operating conditions Supply voltage, VCC SN54160, SN54161 SN74160, SN74161 SN54162, SN54163 MAX SN74162, SN74163 UNIT MIN NOM MAX 5.5 4.75 MIN NOM 4.5 5 High-level output current, IOH Low-level output current, IOL -800 16 Clock frequency, fclock 0 25 0 5 5.25 -800 V 16 /-LA mA 25 MHz Width of clock pulse, tw(clock) 25 25 ns Width of clear pulse, tw(clearl 20 20 20 20 ns 20 25 20 25 20 Data inputs A, B, C, D Setup time, tsu (s.ee Figures 1 and 2) Enable P Load Clearo 20 Hold time at any input, th 0 -55 Operating free·air temperature, T A ns 0 125 0 ns 70 °c -OTh,s applies only for '162 and '163, which have synchronous clear inputs. 1076 7-196 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54160 THRU SN54163. SN74160 THRU SN74163 SYNCHRONOUS 4-81T COUNTERS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL VIK Low-level input voltage VOH High-level output voltage TEST CONDITIONSt Input clamp voltage Low-level output voltage II Input current at maximum input voltage High-level IlL lOS SN74160, SN74161 SN54162, SN54163 SN74162, SN74163 UNIT MIN MIN TYP:j: MAX 2 VOL IIH SN54160, SN54161 Clock or enable T input current Other inputs Low-level Clock or enable T input 'current Other inputs Short-circuit output current § VCC= MIN, II = -12 mA VCC = MIN, VIH = 2 V, VIL = 0.8 V, 10H = -800,uA VCC = MIN, VIH =2V, VIL = 0.8 V, IOL=16mA VCC = MAX, VI = MAX 0.2 VCC = MAX, VI = 2.4 V VCC = MAX, VI = 0.4 V V 0_8 0.8 V -1.5 -1.5 V 3.4 5.5 V 2.4 0.4 3.4 0.2 V 0.4 1 1 80 80 40 40 -3.2 -3.2 -1.6 -20 VCC = MAX ICCH Supply current, all outputs high ICCL Supply current, all outputs low 2.4 TYP:j: 2 -57 -1.6 -18 V mA ,uA mA -57 mA VCC = MAX, See Note 3 59 85 59 94 mA VCC = MAX, See Note 4 63 91 63 101 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC = 5 V, T A = 25°C. §Not more than one output should be shorted at a time. NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. 4_ ICCl is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open_ switching characteristics, Vee PARAMETER~ = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) TEST CONDITIONS f max tPLH 25 Ripple Clock carry tPHL tPLH Clock tpHL (load input high) tPLH Clock tpHL (load input low) tPLH Enable T tPHL tpHL MIN Clear TYP MAX 32 ns 23 35 23 35 Any Q CL=15pF, 13 20 n, 15 23 Any Q See Figures 1 and 2 17 25 and Notes 5 and 6 19 29 Ripple 11 16 carry 11 16 AnyQ 26 38 RL = 400 UNIT ns ns • ns ns ns ~fmax "" Maximum clock frequency tpLH "" propagation delay time, low-to-high-Ievel output tpHl "" propagation delay time, high-to-Iow-Ievel output NOTES: 5. Load circuit is shown on page 3-10. 6. Propagation delay for clearing is measured from the clear input for the '160 and '161 or from the clock input transition for the '162 and '163. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·197 TYPES SN54LS160A, THRU SN54LS163A, SN74LS160A, THRU SN74LS163A, SYNCHRONOUS 4-81T COUNTERS schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT VCC - - - - - -. .-VCC -------4.---- 120 n NOM Req INPUT - ....4.--41~...- - L---~-OUTPUT Data: Enable T, Load: Clock, Enable P: Clear ('LS160A, 'LS161A): Clear ('LS162A, 'LS163A): Req Req Req Req Req = 2.5 kn NOM = 10 kn NOM a 20 kn NOM = 20 kn NOM = 10 kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C Supply voltage, VCC (see Note 7) . . . . . , . . Input voltage . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS' Circuits SN74LS' Circuits Storage temperature range • NOTE 7: Voltage values are with respect to network ground terminal • recommended operating ~onditions SN54LS' Supply voltage, VCC MIN NOM 4.5 5 High-level output current, IOH Low-level output current, IOL SN74LS' MAX 5.5 MIN 4.75 -400. .4 Clock frequency, fclock 0 25 0 NOM 5 UNIT MAX 5.25 V '-400 8 IJA mA 25 MHz Width of clock pulse, tw(clock) 25 25 ns Width of clear pulse, tW(clearl 20 20 ns Data inputs A,B, C, 0 20 20 Enable PorT 20 20 Load 20 20 Clear O 20 20 Setup time, tsu (see Figures 1 and 2) Hold time at any input, th 0 Operating free-air temperature, T A o This applies only for -55 ns 0 125 0 ns 70 °c 'LS162 and 'LS163, which have synchronous clear inputs. 877 7-198 TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS160A THRU SN54LS163A, SN74LS160A THRU SN74LS163A SYNCHRONOUS 4-BIT COUNTERS electrical characteristics over recommended operating free·air temperature range (unless otherwise noted) VI H High·level input voltage VI L Low·level input voltage VIK Input clamp voltage. High-level input current VCC= MIN, II = -18 mA VCC= MIN, VIH = 2V, TYPt 2.5 VIL = VIL max, 10H = -400 JJA VCC = MI N, IIOL = 4 mA VIH = 2 V, VIL=VILmax IOL=8mA MAX 0.8 -1.5 -1.5 2.7 0.25 0.4 0.25 0.4 0.35 0.5 Data or enable P 0.1 0.1 0.2 0.2 0.1 0.1 Clear( 'LS 162A, 'LS 163A) 0.2 0.2 Data or enable P 20 20 Load, clock, or enable T Clear('LS160A, 'LS161A) VCC = MAX, 40 40 20 20 Load, clock, or enable T Clear('LS160A, 'LS161A) VCC = MAX, VI = 0.4 V Clear( 'LS 162A, 'LS 163A) 40 40 -0.4 -0.4 -0.8 -0.8 -0.4 -0.4 -0.8 -0.8 V rnA mA VCC= MAX VCC = MAX, -100 mA See Note 3 18 31 18 31 rnA ICCL Supply current, all outputs low VCC = MAX, See Note 4 19 32 19 32 mA Short-circuit output current§ -20 -20 V ICCH Supply current, all outputs high lOS -100 V V 3.4 Load, clock, or enable T VCC = MAX, Clear('LS160A, 'LS161A) VI = 2.7 V UNIT V 0.7 3.4 Data or enable P Low-level SN74LS' TYPt MAX 2 Clear('LS162A, 'LS163A) input current MIN rl------4---------+.--------I VOL Low-level output voltage at maximum input voltage MIN 2 VOH High·level output voltage Input current SN54LS' TEST CONDITIONSt PARAMETER tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTES: 3. leCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. 4. leCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open . switching characteristics, Vee = 5 V, T A = 25 C 0 FROM (INPUT) PARAMETER~ TO TEST CONDITIONS (OUTPUT) f max tPLH tpHL Clock carry Any Clock (load input high) tpLH Clock Any tpHL (load input low) Q tpLH tpHL tpHL Enable T Clear TYP 25 32 Ripple tpHL tpLH MIN CL=15pF, RL = 2 kn, See Figures Q 1 and 2 and Notes 8 and 9 Ripple carry Any Q 1------- MAX UNIT MHz 20 35 18 13 35 18 27 13 24 18 9 9 27 14 14" 20 28 24 • ns ns ns ns ns' ~fmax;= Maximum clock frequency tpLH ;= propagation delay time, low-to-high-Ievel output. tpHL propagation delay time, high-to-Iow-Ievel output. NOTES: 8. Load circuit is shown on page 3·11. 9, Propagation delay for clearing is measured from the clear input for the 'LS160A and 'LS161 A or from the clock transition for the 'LS162A and 'LS163A. = 877 TEXAS INSTRUMENTS INCOHPOHATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·199 TYPESSN54S162, SN54S163,SN74S162, SN74S163 SYNCHRONOUS 4-811 COUNTERS REVISED DECEMBER 1980 schematics of inputs and outputs TYPICAl OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ------------__~----VCC 50 n NOM vCC--e-------~.---------I 20 kn NOM ~ (OPEN FOR CLOCK ~ AND DATA INPUTS) I I INPUT - -......--' OUTPUT Enable P or T inputs: Req Other inputs: Req = = 1.4 kn NOM 2.8 kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature range: SN54S162, SN54S163 (see Note 10) SN74S162,SN74S163 Storage temperature range • 7V 5.5 V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C recommended operating conditions Supply voltage, VCC SN54S162, SN54S163 SN74S162, SN74S163 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -1 mA -1 High-level output current, IOH 20 Low-level output current, IOL 0 Clock frequency, fclock' 40 0 UNIT 20 mA 40 MHz Width of clock pulse, tw(clock) (high or low) 10 10 ns Width of clear pulse, tw(clead 10 10 ns 4 12 4 12 Clear 14 14 14 Load inactive-state 12 12 Clear inactive-state 12 Data inputs, A, B, C, D Enable P or T Load Setup time, tsu (see Figure 4) 4 Enable P or T 4 3 3 Hold time, th (see Figure 4) Data inputs A, B, C! D Load 0 0 Clear 0 0 -55 ns 12 Release time, trelease (see Figure 4) Operating free-air temperature, T A .(see Note 10) NOTES: 14 125 0 ns ns 70 "c 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the count enable inputs P and T. 0 10. An SN54S 162 or SN54S 163 in the W package operating at free·air temperatures above 91 C requ ires a heat sink that provides a thermal resistance from case to free-air, ROCA, of not more than 26°C/W. 1280 7-200 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-811 COUNTERS REVISED DECEMBER 1980 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54S162 TEST CONDITIONSt PARAMETER MIN VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage SN74S162 SN54S163 TVP+ SN74S163 rv'!AX 2 VOH High·level output voltage VOL Low·level output voltage II Input current at maximum input voltage IIH High·level input current Clock and data inputs Other inputs Enable T VCC = MIN, 11=-18mA VCC = MIN, VIH=2V, VIL = 0.8 V, 10H = -1 mA VCC = MIN, VIH = 2 V, VIL = 0.8 V, 10L = 20 mA VCC - MAX, VI - 5.5 V VCC = MAX, VI = 2.7 V IlL Low·level input current VCC = MAX, lOS Short·circuit output current ~ VCC = MAX ICC Supply current VCC - MAX Other inputs 2.5 MIN TVP+ UNIT MAX 2 V 0.8 0.8 V -1.2 -1.2 V 3.4 2.7 3.4 0.5 -10 -40 1 50 50 -10 -200 -4 -4 -2 -2 -100 95 0.5 1 -200 VI = 0.5V V -40 V mA J1.A mA -100 mA 95 160 mA MIN TVP MAX 40 70 160 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at V CC = 5 V, T A = 25"C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER~ FROM TO (INPUT) (OUTPUT) TEST CONDITIONS f max tpLH Ripple Clock tpHL tpLH carry Clock Anya CL=15pF, RL = 280.n, MHz 14 25 17 25 8 15 15 tpHL See Figures 1, 3, and 4 and 10 tpLH Note 5 10 15 10 15 Ripple Enable T tpHL carry ~fmax =maximum clock frequency tpLH = propagation delay time, low·to·high·level output tp H L = propagation delay time, high·to·low·level output UNIT ns ns ns • NOTE 5: Load circuit is shown on page 3-10. 1280 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-201 TYPES SN54160 THRU SN54163, SN54LS160A,THRU Sr~54LS163A SN54S162, SN54S163, SN74160 THRU SN74163, , SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-811 COUNTERS PARAMETER MEASUREMENT INFORMATION ..I I....tw(clock) I I I 3V CLOCK INPUT l.-.I-tPLH (measure at t n +1) I I I 1 I I.--a-tPHL (measure at t n +2) I I OUTPUT QA _ _ _ _oJ Vref I I ~S~-_/ I ~tPHL I I (measure at t n +4) ~tpLH I (measure I at t n +2) I ~\-S_ _~l~'f OUTPUT QB I...--ttpHL I I (measure at t OUTPUT Q • C I I' n +8) I -I I 1t4.--lot-l- (measure at t n +10 or t n +16) V(::~ Note B) I QD r---+l tPLH l RIPPLE CARRY_ _ _ _ _--' OUTPUT . I I Vref - VOL VOH ___ _ - - - VOL tp LH (measure at t n +8) lv: ______ ·~.,.s_____ OUTPUT - I ""I.t----e.ot-\- tpH L '\ - tPLH (measure at t n +4) ~rs____~i__~V~f I ___ _ I VOH VOL 1 .... ·-_·t-I-tPHL I I I (measure at t n +10 or t n +16) (See Note B) \S~)--------------------------- ~:~ VOLTAGE WAVEFORMS NOTES: n; A. The input pulses are supplied by a generator having the following characteristics: PRR .;;; 1 MHz, duty cycle';;; 50%, Zout '" 50 for '160 thru '163, tr';;; 10 ns, tf .;;; 10 ns; for 'LS160A thru"' LS163A,t r .;;; 15 ns, tf .;;; 6 ns; and for 'S162, 'S163, tr "2.5 ns, tf';;; 2.5 ns. Vary PRR to measure f max . B. Outputs 00 and carry are tested at tn+10 for'160,'162,'LS160A,'LS162A.and'S162, and at tn+16 for '161, '163,'LS161A 'LS163A, and 'S163, where tn is the bit time when all outputs are low. C. For"'160"thru '163. 'S162, and 'S163.V re f = 1.5 V; for'LS160A thru 'LS163A, Vref= 1.3 V. FIGURE 1-SWITCHING TIMES 1076 7-202 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A SYNCHRONOUS 4-81T COUNTERS PARAMETER MEASUREMENT INFORMATION CLOCKINPU~T------------------------~~, :~:~::~~~~~~ ~r---------------------------------- !~:- l\Vref ___________ --- 3V OV -tw(Clock)-I l CLEAR INPUT 1 3V ~V: ______ j __ _ ..... tw(clear)..,.J ________________________ I 1_ I ~I t su OV - '1 U~,~---- ---------- LOAD INPUT 1'- 3V OV tsu - : ~:--------------- DATA INPUTS A, B, C, and 0 -----_--I=-t-P-H-L-I---------------.J g7i~ikUTPUTS i ~ 0B and Oc OUTPUTS '160, 'LS160A 3V OV _I tPLH I+-- .:.i---Jl~,: __________ _ VOH \'"v_re_f______________________ I. tpHL ' - \vrel : VOL ,I tPLH (measure at tn+2 or t n+4) ,~,~~~~~~-_-_-_-~~~ VOH VOL 3V ENABLE P or ENABLE T Vref 1 tPLH~ 1c'i-v~_,--Vref RIPPLE CARRY OUTPUT I ------~I------------------------------I--------------~ 1- tsu ~~r:~:~f\ -I f,v rel 01 _______________....:..1__ ~ ~3~::S~~~A OA and 00 OUTPUTS '162,'LS162A :: VOH • I VOL 3V II:: ______________ OV \:rel I+I I- - I tPLH I ~ \L"-v_r_ef____________ r------------------------ ~:,---'!f T Vrel ~t;L~(~a;;:;re~t~+~r~+~ --!tPHLI- I 0B and Oc OUTPUTS '162, 'LS162A ~ I ______-+1I tpH L \vrel I -- - r - - - - -- - - - - -- - - /-~,: ____________ VOLTAGE WAVEFORMS NOTES: OV ·l--l-tPHL VOH VOL VOH VOL A. The input pulses are supplied by generators having the foliQ';'ing ch~racteristics: PRR .;; 1 MHz, duty cycle <;; 50%, Zout "" 50 for '160 thru '163, tr';; 10 ns, tf .;; 10 n~ and for 'LS160A thru 'LS163A, tr .;; 15 ns, tf .;; 6 ns, B. Enable P and enable T setup times are measured at tn+O' C. For '160 thru '163, Vref = 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V. n; FIGURE 2-SWITCHING TIMES 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-203 TYPES SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-81T COUNTERS PARAMETER MEASUREMENT INFORMATION ENABLE T INPUT ~~V----------:: J5V I I t.CARRY OUTPUT I- tpLH ----: tPHL--1 I 1 ________-J~.5V \'.5v--- "".-----VOL VOLTAGE WAVEFORMS NOTES: VOH A. The input pulse is supplied by a generator having the following characteristics: tr';; 2.5 ns, tf .;; 2.5 ns, PRR .;; 1 MHz, duty cycle';; 50%, Zout '" 50 !1. B. tpLH and tpHL from enable T input to carry output assume that the counter is at the maximum count (OA and 0D high for 'S162, all ° outputs high for 'S163). FIGURE 3-PROPAGATION DELAY TIMES FROM ENABLE T INPUT TO CARRY OUTPUT I-- tw(clock) f4- tw(Clockl CLOCK INPUT I 1 I 1 • 3V 1 I I '-----I , . - tsu --.I I (active state) I+- CLEAR INPUT -.., I ----1 1 1 th -,'-1._5_V_____ I+-- tw(clear) I t---- tsu ---., (inactive state) 1 ~ .J4'~V____ ~--------~---:: ~ : - - tsu ~ I (active state) ... th I I \5V LOAD INPUT . l- tsu t5V ! . --l I : 3V ------------oV 1 I. .1 I --I!:1.5V OATA INPUTS_______________________________ A, B, C, and D ~ tsu ~ ..I (,nact,ve state) I 1 \'V . I-1 --J,:1.5V ENABLEPor _______________________________________________ ENABLE T 1 th _______ • J ____ 3V ! I OV ·1 ~trelease \5~---:: VOLTAGE WAVEFORMS NOTE A: The input pulses are supplied by generators having the following characteristics: tr';; 2.5 ns, tf .;; 2.5 ns, PRR .;; 1 MHz, duty cycle';; 50%, Zout '" 50 n. FIGURE 4-PULSE WIDTHS, SETUP TIMES, HOLD TIMES, AND RELEASE TIME 1076 7·204 TEXAS INCORPORATED INSTRUMENTS POST. OFFICE BOX 5012 • DALLAS, TEXAS 75222 I\.l 0) o N~ITSYNCHRONOUSCOUNTERS This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter_ The '160, '162, 'LS160A, 'LS162A, or 'S162 will count in BCD and the '161, '163, 'LS161A, 'LS163A or 'S163 will count in binary. Virtually any count mode (modulo-N, Nl-to-N2, Nl-to-maximum) can be used with this fast look-ahead circuit. -I < "'C m en en 2 U'1 ~ en 2 ...... INPUTS ~ 2l ~ 0 ~ ,.----A-----.. ,..----J'--.. ,..----J'--.. > ! IIII ! IIII ! IIII !IIII LD A B C LD A B C LD A B C (Jl ~ 8z ;;j ;0 (Jl ~-i ~ ~;c ~ -l c::: LD A B C H = COUNT L = DISABLE ----. EN T rr1 Z -i r--I>CK '"'" Cl '" D H =COUNT L = DISABLE....o..t EN P ~ b~ ;;1 x l; .... INPUTS ,..----J'--.. '"o -z_ !!:l INPUTS rr1 >< ~ INPUTS (Jl RIPPLE CARRY t----IEN T OUTPUT CLOCK ..... ~ UI D a.....-; EN P '-IENP RIPPLE CARRY OUTPUT t-----I EN T RIPPLE CAR RY OUTPUT CLR 0A 0B 0c 0D ii I I I I II I I I III I I I III I .. ;c , J '---v---J ~ OUTPUTS OUTPUTS OUTPUTS II ~en -I~2 ""r- ::::cenU'1 0 2U'1 en en ...... ~z n » -; TO MORESIGNIFICANT Z STAGES 0 :aN~ c:;"C;; en2~ 2" '---v---J .. l>U'1 ...... = oen.p.:I> OUTPUTS .. enen:a =2c: C:2--I ~ .. -I <~~U'1 ~ 2enen~ C"")-Wr» ::::c en " en :aWenO:l>2en r-----P CK CLR 0A 0B 0c 0D C!.-R 0A 0B 0c 0D x , , , , r - ::::c ~ » RIPPLE L...".,. CARRY OUTPUT r-----t EN T ~ - r- n ):> r- D en = -; -< '----I EN P r---I>CK r-J>CK CLR 0A 0B 0c 0D CLEAR D ~ en""" en_ .p.=f'~-I:a ~ =cn::::cc: C"")" c:2 en U'1 °2en~ c: ...... 2r2~ ...... en -Ien~­ m_-cn :acn cnw enwWl> .... =tN:acn TTL TYPES SN54164. SN54L164. SN54LS164. SN74164. SN74L164. SN74LS164 MSI 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS BULLETIN NO. DL-S 7611835, MARCH 1974-REVISED OCTOBER 1976 • Gated (Enable/Disable) Serial Inputs • Fully Buffered Clock and Serial Inputs • Asynchronous Clear SN54164. SN54LS164 ••. J OR W PACKAGE SN54L 164, SN74L 164 •.• J, N, OR T PACKAGE SN74164, SN74LS164 ••. J OR N PACKAGE (TOP VIEW) OUTPUTS TYPICAL MAXIMUM TYPE Vcc TYPICAL CLOCK FREQUENCY ~CLEARCLOCK POWER DISSIPATION '164 36 MHz 21 mW per bit 'L164 18MHz 'LSl64 36 MHz 11 mWperbit 10 mW per bit CLEAR CK description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the positive logic: see function table other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-Ievel transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. Series 54, 54L, and 54LS devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74, 74L, and 74LS devices are characterized for operation from O°C to 70°C. FUNCTION TABLE INPUTS • OUTPUTS CLEAR CLOCK A B QA L X X X L QB ••• QH L L H L X X H t t t H H QAO H QAn QGn L X L QAn QGn X L L QAn QGn H H QBO QHO H X = high level = irrelevant (steady state), L = low level (steady state) (any input, including transitions) t = transition from low to high level. 0AO, 0BO, 0HO = the level of 0A, 0B, or 0H, respectively, before the indicated steady-state input conditions were established. level of 0A or 0G before the most-recent t transition of the clock; indicates a one-bit shift. = the 0An, 0Gn schematics of inputs and outputs '164, 'L164 EQUIVALENT OF EACH INPUT 'LS164 TYPICAL OF ALL OUTPUTS - EQUIVALENT OF EACH INPUT ......- - V CC V Cc-------0 U TP UT OUTPUT '164: 'L164: Req = 4 kn NOM Req = 8 kn NOM '164: R = 200 n NOM 'L 164: R ~ 400 n NOM Clear, clock: 17 kn NOM Serial In: 25 kn NOM 1076 7-206 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS REVISED OCTOBER 1976 typical clear, shift, and clear sequences u CLEAR-U I I L-Jl~ SERIAL { INPUTS A ____________+-_______________ -----~------------~ I CLOCK 1 ---, I ~~---------~------------­ ~~------~-----------­ ---, ____________________________ °C ___ ~~---~-------­ OD===~J__________________________~ ~~-------------°E ---, ___ ______________________________________ LJlL..--_____ 0A _ ......1_______________________---' ---, °S __ ~I~ _________________________ ~ ~I~ OUTPUTS ~ ~I~ I ---, _________________________________________ ---, _______________________________________________ °F ____ °G ~ I~ ~I~ OH=--.~l~ I I ~ ~ ________________________________________ I I ~r_J~ _____________ I CLEAR CLEAR • functional block diagram CLEAR~19~1--------~ ~O-~~------.--------~--------~------~~------~~------_.--------, CLOCK~18~1____~ ~o.---~---~---4----~--+---._---~_1~_+---_.---_r---~--+___, 1101 1111 1121 1131 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT °A Os °c 00 °E OF °G 131 141 151 161 OH 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE sox 5012 • DALLAS. TEXAS 75222 7-207 TYPES SN54164, SN74164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) .... . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54164 SN74164 Storage temperature range 7V 5.5 V _55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74164 SN54164 MIN 4.5 Supply voltage, VCC NOM MAX MIN NOM 5.5 4.75 5 5 MAX -400 High-level output current, IOH Low-level output current, IOL 5.25 V -400 /lA 8 mA 8 25 0 Clock frequency, fclock UNIT 25 MHz 0 Width of clock or clear input pulse, tw 20 20 ns Data setup time, tsu (see Figure 1) 15 15 ns 5 5 Data hold time, th (see Figure 1) 125 -55 Operating free-air temperature, T A ns 0 70 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage TYP+ SN74164 MAX VOL Low-level output voltage II Input current at maximum input voltage VCC = MIN, II = -12 mA VCC- MIN, VIH-2V, VIL = 0.8 V, IOH = -400 /lA VCC - MIN, VIH-2V, VIL = 0.8 V, IOL = 8mA 2.4 MIN TYP+ MAX 2 2 VOH High-level output voltage • SN54164 MIN 0.8 V -1.5 -1.5 V 2.4 0.2 V 0.8 3.2 0.4 V 3.2 0.2 0.4 1 VCC = MAX, VI = 5.5 V, UNIT 1 V mA IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 /lA IlL Low-level input current VCC = MAX, VI-O.4V -1.6 -1.6 mA lOS Short-circuit output current§ VCC = MAX -27.5 mA ICC Supply current -10 I -27.5 VCC - MAX, VI(clock) = 0.4 V 30 IVI(clock) = 2.4 V 37 See Note 2 -9 30 54 37 54 mA tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°C. §Not more than two outputs should be shorted at a time. NOTE 2: ICC is measured with outputs open, serial inp,uts grounded, and a momentary ground, then 4_5 V, applied to clear. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS f max Maximum clock frequency CL=15pF Propagation delay time, high-to-Iow-Ievel tpHL Q outputs from clear input tpHL TYP 25 36 CL - 15 pF MAX 36 28 42 8 17 27 CL = 50 pF 10 20 30 Propagation delay time, high-to-Iow-Ievel CL -15pF 10 21 32 Q outputs from the clock input CL = 50 pF 10 25 37 Q outputs from clock input RL=800n, See Figure 1 CL = 50 pF UNIT MHz 24 CL = 15pF Propagation delay time, low-to-high-Ievel tpLH MIN ns ns ns 1076 7-208 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 TYPES SN54L164, SN74L164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free·air temperature range: SN54L 164 SN74L 164 Storage temperature range 7V 5.5V -55°C to 125°C aOc to 7aoe -65°C to 15aoe NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74L 164 SN54L164 MIN NOM 4.5 SupplV voltage. Vee MAX MIN NOM 5.5 4.75 5 5 -200 High-level output current, 10H Low-level output current, 10L MAX 5.25 V -200 p.A 4 mA 4 12 0 Clock frequency, fclock UNIT 12 MHz 0 Width of clock or clear input pulse, tw 40 40 ns Data setup time, tsu (see Figure 1) 30 30 ns 10 -55 10 Data hold time, th (see Figure 1) Operating free-air temperature, T A 125 ns 70 0 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input vol tage VIL Low-level input voltage VIK Input clamp voltage TEST CONDITIONSt SN54L164 MIN TYP+ SN74L 164 MAX 2 VOH High-level output voltage VOL Low-level output voltage VCC = MIN, II = -12 mA VCC= MIN, VIH=2V, VIL = 0.8 V, 10H = -200 p.A, VCC= MIN, VIH = 2 V, VIL = 0.8 V, 10L =4 mA 2.4 MIN TYP+ MAX 0.8 0.8 V -1.5 -1.5 V 3.2 0.2 UNIT V 2 2.4 0.4 3.2 0.2 V 0.4 V II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA IIH High-level input current VCC - MAX, VI-2.4V 20 20 p.A IlL Low-level input current VCC = MAX, VI = 0.4 V -0.8 -0.8 mA lOS Short-circuit output current§ VCC = MAX -20 mA ICC Supply current VCC = MAX, See Note 3 27 mA -5 -20 19 -4 19 27 II I tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°e §Not more than two outputs should be shorted at a time. NOTE 3: lee is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V, applied to clear_ switching characteristics, Vee = 5 V, T A = 25° C PARAMETER TEST CONDITIONS f max Maximum clock frequency tPHL CL-15pF Propagation delay time, high-to-Iow-Ievel . Q outputs from clear input Propagation delay time, low-to-high-Ievel tPLH tpHL Q outputs from clock input MIN TYP 12 18 CL -15pF RL =800 n, See Figure 1 MAX MHz 48 72 56 84 CL = 15 pF 8 34 54 CL = 50 pF 10 20 60 CL = 50 pF UNIT Propagation delay time, high-to-Iow-Ievel CL = 15pF 10 42 64 Q outputs from the clock input CL - 50 pF 10 50 74 ns ns ns 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-209 TYPES SN54LS164, SN74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 7V _55°e to 125°e oOe to 700e -65°C to 150°C Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS164 SN74LS164 Storage. temperature range NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS164 SN74LS164 UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -400 /lA 8 rnA Supply voltage, Vee -400 High-level output current, IOH 4 Low-level output current, IOL 25 0 Clock frequency, fclock 0 25 MHz Width of clock or clear input pulse, tw 20 20 ns Data setup time, tsu (see Figure 1) 15 15 ns Data hold time, th (see Figure 11 5 ns 5 -55 Operating free-air temperature, T A 125 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) • VIH High-level input voltage VIL Low-level input voltage VIK Input cI amp vol tage VOH High-level output voltage VOL Low-level output voltage MIN TYP+ SN74LS164 MAX MIN TYP+ 11--18mA Vee = MIN, VIH=2V, VIL = VIL max, 10H = -400 /lA Vce = MIN, VIH = 2 V, VIL = VIL max maximum input voltage 0.8 -1.5 2.5 3.5 0.25 IIOL = 4 mA -1.5 2.7 0.4 IIOL = 8 mA Vce = MAX, VI =7 V UNIT V 0.7 Vee - MIN, MAX 2 2 Input current at II SN54LS164 TEST eONDITIONSt PARAMETER V V 3.5 0.25 0.4 0.35 0.5 0.1 V 0.1 V rnA IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 /lA IlL Low-level input current VCC- MAX, VI- 0.4 V -0.4 -0.4 rnA lOS Short-circuit output current§ Vee = MAX -100 rnA ICC Supply current Vec= MAX, 27 rnA -20 -100 16 See Note 3 -20 16 27 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, T A = 25°C. §Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V applied to clear. switch ing characteristics, Vee = 5 V, T A = 25° C PARAMETER TEST CONDITIONS f max Maximum clock frequency tpHL Propagation delay time, high-to-Iow-Ievel Q outputs from clear input eL=15pF, tpLH Propagation delay time,low-to-high-level Q outputs from clock input See Figure 1 tpHL Propagation delay time, high-to-Iow-Ievel Q outputs from clock input RL=2kn, MIN TYP 25 36 MAX UNIT MHz 24 36 ns 17 27 ns 21 32 ns 1076 7-210 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS PARAMETER MEASUREMENT INFORMATION AANOB PULSE GENERATOR OUTPUT VCC A °A °B °c 00 °E OF °G °H B CLOCK PULSE GENERATOR CLOCK I CLEAR PULSE GENERATOR CL (See Note B) TEST CIRCUIT CLEAR PULSE ~ I """"'--j ~ I I GENERATOR (PRR .. 1 MHz) V .., / 3V .., I ------- -- - - - - ------OV , - - - - - - 3V CLOCK PULSE GENERATOR (PRR" 1 MHz) I I ---{ t-- SERIAL INPUTS A AND B PULSE GENERATOR (PRR" MHz) 3V I ------1.1---- ~ --t II th ---II I I I 0 V ~tPHL~ tpLH r---JJf-------_~ VOH 0A OUTPUT (See NOleD) VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generators have the following characteristics: duty cycle';; 50%, Zout "" 50.11; for '164 and 'L164, tr';; 10 ns, tf';; 10 ns, and for 'LS164, tr';; 15 ns, tf';; 6 ns. B. CL includes probe and jig capacitance. C. All diodes are 1 N3064 or 1 N916. O. QA output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the typical shift sequence. E. Outputs are set to the high level prior to the measurement of tpH L from the clear input. F. For '164 and 'L164, Vref = 1.5 V; for 'LS164, Vref = 1.3 V. FIGURE l-SWITCHING TIMES 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-211 TYPES SN54165, SN54LS165, SN74165, SN74LS165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS TTL MSI BULLETIN NO. DL-S 7611375. OCTOBER 1976 SN54165, SN54LS165 ••. J OR W PACKAGE SN74165, SN74LS165 " . J OR N PACKAGE (TOP VIEW) • Complementary Outputs • Direct Overriding Load (Data) Inputs • Gated Clock Inputs Vcc CLOCK INHIBIT P AALLEL INPUTS ~ SEAIALOUTPUT INPUT QH • Parallel-to-Serial Data Conversion TYPICAL MAXIMUM TYPICAL CLOCK FREQUENCY POWER DISSIPATION '165 26 MHz 210mW 'LS165 35 MHz 105mW TYPE description ~~~"[jCLOCK ~ OUKHUT GND PARALLEL INPUTS The '165 and 'LS165 are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All in puts a re diode-clamped to minimize transmission-line effects, thereby simplifying system design. \ positive logic: see description Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift/load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-Iow transition of the shift/load input independently of the levels of the clock, clock inhibit, or serial inputs . • FUNCTION TABLE INPUTS SHIFTI CLOCK INTERNAL CLOCK SERIAL LOAD INHIBIT L X X H L H L H H PARALLEL a ... h a L X X QBO QHO H QGn L X X QAn L t t QAO H L QAn QGn H X X X QAO QBO QHO '165 EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPt,JTS INPUT QB b h o 'LS165 EQUIVALENT OF EACH INPUT TYPlqALOF BOTH OUTPUTS vcc -~VCC Req 100 {l NOM INPUT -_ QH X schematic of inputs and output Req OUTPUT QA See explanation of function tables on page 3-8. VCC3-- OUTPUTS A ... H OUTPUT -- OUTPUT Clock, clock inhibit: Req = 17 k{l NOM Parallel inputs, serial inp~t: Req "" 24 kn NOM Shift/load: Req = 5.7 kO NOM Shift/load: Req 3 k{l NOM Other inputs: Req'" 6 kfl NOM S 1076 7-212 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54165, SN54LS165, SN74165, SN74LS165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS functional block diagram ~ _________________________________ _________________________________ INPUTS ~A~ ~ (91 OUTPUT OH OUTPUT QH typical shift, load, and inhibit sequences ---.:=---___+-_________________ -v SERIALINPUT _ _ SHIFT/LOAD A~ I L ~---r------------------ i C~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ IL I I E~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ I I L I I -r__________________ G~~_ _ I H~~_~_ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ OUTPurOH I I OUTPUTOH L I I- -1------ SEA'ALSH'FT -------- absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage: SN54165, SN74165 . SN54LS165, SN74LS165 Interemitter voltage (see Note 2) Operating free·air temperature range: SN54165, SN54LS165 SN74165,SN74LS165 Storage temperature range NOTES: 7V 5.5V . 7V 5.5 V . -55°C to 125°C oDe to 70°C . -65°C to 150°C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple.... mitter transistor. This rating applies tor the '165 to the shift/load input on conjunction with the clock·inhibit Inputs. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-213 TYPES SN54165, SN74165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS recommended operating conditions SN54165 MIN NOM 4.5 Supply voltage, VCC SN74165 MAX MIN 5.5 4.75 5 NOM 5 -800 High-level output current, 10H MAX V -800 /J- A 16 Low-level output current, 10L 0 Clock frequency, fclock 20 UNIT 5.25 0 16 rnA 20 MHz Width of clock input pulse, tw(clock) 25 25 ns Width of load input pulse, tw(ioad) 15 15 ns Clock-enable setup time, tsu (s.ee Figure 1) 30 30 ns Parallel input setup time, tsu (see Figure 1) 10 10 ns Serial input setup time, tsu (see Figure 2) 20 20 ns Shift setup time, tsu (see Figure 21 45 45 ns 0 0 'ns Hold time at any input, th Operating free-air temperature, T A -55 125 70 0 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER I VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current Low-level input current lOS Short-circuit output ICC Supply current MIN SN74165 TYP:t MAX 2 = MIN, VCC IlL SN54165 TEST CONDITIONSt VIH - 2 V, VIL = 0.8 V, 10H VCC - MIN, VIH - 2 V, VIL Shift/load Other inputs Shift/load Other inputs current~ = 0.8 V, = -800/J-A VI - 5.5 V = MAX, VI = 2.4 V VCC = MAX, VCC - MAX, V 0.8 V -1.5 -1.5 V 3.4 2.4 0.4 VI=O.4V 3.4 0.2 See Note 3 V 0.4 1 1 80 80 40 40 -3.2 -3.2 -1.6 -20 VCC = MAX UNIT 0_8 0_2 10L = 16 rnA VCC - MAX, VCC 2.4 TYP+ MAX 2 II = -12 rnA VCC - MIN, MIN -55 42 -1.6 -18 42 63 V rnA /J- A rnA -55 rnA 63 rnA NOTE 3: With the outputs open, clock inhibit and clock at 4_5 V, and a clock pulse applied to the shift/load input, lee is measured first with the parallel inputs at 4,5 V, then with the parallel inputs grounded, t For conditions shown as M IN or MA X, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time. switching characteristics, Vee PARAMETER~ = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) Load Any TEST CONDITIONS f max tPLH tpHL tpLH Any Clock C L = 15 p F, R L = 400 tpHL tPLH See figures 1 thru 3 H QH tPHL tPLH H OH tPHL n, MIN TYP 20 26 MAX UNIT MHz 21 31 27 40 16 24 21 31 11 17 24 36 18 27 18 27 ns ns ns ns ~fmax:::::: maximum cloc·k frequency tpLH "" propagation delay time, low-to-high-Ievel output tpHL "" propagation delay time, high-to-Iow-Ievel output 1076 7-214 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS165, SN74LS165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS recommended operating conditions SN74LS165 SN54LS165 NOM MIN 4.5 Supply voltage, VCC MAX MIN 5.5 4.75 5 NOM 5 -400 High-level output current, 10H Low-level output current, 10L MAX V -400 itA 8 rnA 25 MHz 4 0 Clock frequency, fclock 25 UNIT 5.25 0 Width of clock input pulse, tw(clock) 25 25 ns Width of load input pulse, tw(ioad) 15 15 ns Clock-enable setup time, tsu .!see Figure 1) 30 30 ns Parallel input setup time, tsu (see Figure 1) 10 10 ns Serial input setup time, tsu (see Figure 2) 20 20 ns Shift setup time, tsu (see Figure 2) 45 45 ns 0 0 Hold time at any input, th 125 -55 Operating free-air temperature, T A ns 70 0 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage Low-level output voltage I nput current at II IIH maximum input voltage Low-level input current MIN TYP* SN74LS165 MAX MIN TYP:j: 2 VCC= MIN, II = -18 rnA VCC= MIN, VIH =2 V, VIL = VILmax, 10H = -400 itA I VCC = MIN, VOL SN54LS165 TEST CONDITIONSt VIH = 2 V, Shift/load Other inputs Shift/load Other inputs Shift/load Other inputs 10L =4 rnA VIL = VILmax,1 10L = 8 rnA VCC = MAX, VI =7 V VCC = MAX, IlL Low-level input current lOS Short-circuit output current§ VCC = MAX ICC Supply current VCC = MAX, 2.5 V -1.5 -1.5 V 2.7 0.25 -20 See Note 3 V 0.8 3.5 VI=O.4V UNIT 0.7 0.4 3.5 V 0.25 0.4 0.35 0.5 0.3 0.1 0.3 60 20 60 20 -1.2 -1'.2 -0.4 -0.4 V I =2.7V VCC = MAX, MAX 2 -100 21 0.1 -20 21 36 V rnA itA rnA -100 rnA 36 rnA II I NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, ICC is measured first with the parallel inputs at 4.5 V, then with the parallel inputs grounded. t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions. *AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER~ FROM TO (INPUT) (OUTPUT) TEST CONDITIONS f max tPLH Load Any tPHL tPLH Clock Any CL = 15 pF, RL = 2 kn, tPHL tPLH See figures 1 thru 3 H QH tPHL tPLH H QH tPHL MIN TYP 25 35 MAX UNIT MHz 22 35 22 35 27 40 28 40 14 25 21 30 21 30 16 25 ns ns ns ns ~fmax;: maximum clock frequency tpLH;: propagation delay time, low-to-high-Ievel output tpHL;: propagation delay time. high-to-Iow-Ievel output 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 7-215 II .... ~ ! ~ CLOCK INHIBIT INPUT \- ------- -- -~(DiS:b~e while Vref I tsu \ CLOCK INPUT t+--- iN~~~SH ~Vref -'V"-r-e-f---'L (SeeNotesAandB)~ v V"' I I ov I I ~------------------- 3 V I I I I ---I------t----OV ~tpHL tPLH---..I , I 1-, VOH SHIFT/ LOAD I , , tPHL~ -i ['T1 >< OUTPUT QH > (J) z_ I Vref ~tpHL I I tPLH--++-+i .00 NOT-E-S-:-A-. 0-l ;;0 I I -T..J!.~:::,o, ,J:::',o,"" m"L:::,.,. QH ~(J) ~tpHL I ~. OUTPUT tPLH~ Vref , tPLH~ 8z I I, j+--.t-tPHL , 'ow ~c: Vref' D. For '165, Vref -l SHIFT/ LOAD (J) ---.i I for 'LS165, Vref = 1.3 V. s: - ~ ~ n; for VOL '165, tr <; 10 ns, tf <; 10 ns; ~ m ~ Z -I "T1 _ ' V - -, tsu TEST POINT OV I o s: JJ VCC l> 3V ~ Vref -I RL ~~~~RO~~:~T • MIl. (5 ., ~ ~ I. CLOCK INPUT '----------'" OV tn NOTES: A. The eight data inputs and the clock·inhibit input are low. Results are monitored at output QH at t n +7' B. The input pulse generators have the following characteristics; PRR <; 1 MHz, duty cycle <; 50%, Zout'" 50 f!; for '165, tr <; 10 ns, tf <; 10 ns; for 'LS165, tr <; 15 ns, tf <; 6 ns. C. For '165, Vref = 1.5 V; for 'LS165, Vref = 1.3 v. FIGURE 2-VOLTAGE WAVEFORMS ~ JJ l> ::::. ~tPHL - FIGURE l-VOL TAGE WAVEFORMS ~tsu a> ~ Z - -Vref ---.::.... SERIAL INPUT = 1.5 V; =.?" I cam =4z ,---VOH tpLH~ -- for 'LS165, tr <; 15 ns, tf <; 6 ns. ['T1 > Cen m JJ ~ C. The input pulse generators have the following characteristics: PRR <; 1 MHz, duty cycle <; 50% Zout '" 50 Z r-U'I Q~ VOL I , Iv'" \V'of B. Prior to test, high-level data is loaded into H input. Os::: r;-Z I -: - - - - - - : - - --- 'V I '\ rr- rn mrn W f.'reT . . tW(CIOCk)~ i ", >m OV ----J..--.I _v;;:-\~·----OV Iv", . -----.j tsu "'-f l>< =." clock is high NOTES; A. CL includes probe and jig capacitance. B. All diodes are IN3064. FIGURE 3-LOAD CIRCUIT FOR SWITCHING TESTS Z rnU'l -=~ r~~ en :DU'I m .. C')rn -2 en...., -f~ m_ :Den en"U'I rn Z ...., ~ r- rn en U'I TYPES SN54166, SN54LS166, SN74166, SN74LS166 8-BIT SHIFT REGISTERS TTL MSI BULLETIN NO. DL-S7711808, OCTOBER 1976-REVISED AUGUST 1977 SN54166, SN54LS166 ••• J OR W PACKAGE SN74166, SN74LS166 ••• J OR N PACKAGE (TOP VIEW) • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion PARALL L PARALLEL INPUTS INPUT OUTPUT,....--...J'-. H QH G F E CLEAR TYPICAL MAXIMUM TYPICAL CLOCK FREQUENCY POWER DISSIPATION '166 35 MHz 360mW 'LS166 35 MHz 110mW TYPE functional block diagram SERIAL A B C 0 CLOCK CLOCK GND INPUT ' - . . . - ' INHIBIT PARALLEL INPUTS positive logic: see description description The '166 and 'LS166 a·bit shift registers are compatible with most other TTL and DTL logic families. All '166 and 'LS166 inputs are buffered to lower the drive requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input clamping diodes minimize switching transients and simplify system design. -c:J>- ... dynamic input activated by transition from a high levul to a low lovel. II These parallel-in or serial-in, serial-out shift registers have a complexity of 77 equivalent gates on a monolithic chip. They feature gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-Ievel edge of the clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free-running and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. I 877 TEXAS INCORPORATED INSTRUMENTS POST o,."cr:: DOX 5012 • DALLAS. TEXAS 7!5222 7·217 TYPES SN54166, SN54LS166, SN74166, SN74LS166 8-BIT SHIFT REGISTERS typical clear, shift, load, inhibit, and shift sequences CLOCK CLOCKINHIBIT~~__~________________________-7______~r-----l~~ CLEAR~I I __________________________ I I I SERIAL INPUT ~~____________________- .______~____~__~_________________________ I U SHIFT/LOAO I A __ ~~--------------------------~--~~L----~-,--------------------------, L, C __ ~~--------------------------~--~~L----~~--------------------------­ I I PARALLEL INPUTS O____~--------------------------~-----L~:--------~-------------------------__~~--------------------------~--~~L----~~--------------------------I L G --~~----------------------~--~ H OUTPUT 0H I --~~--------------------------~--~ ===,:_~______________________.,.-----' 1 - - - - - SE R I A L S H I FT --------------1 LOAD CLEAR FUNCTION TABLE INTERNAL INPUTS CLEAR II SHIFTI CLOCK CLOCK SERIAL PARALLEL A ••• H OUTPUTS LOAD INHIBIT L X X X X X °A L °B L H X L L X X °AO t t t t H L L H H L H H L H X H OUTPUT °H L GHO h X a ... h a GBO b H X H GAn GGn L X L GAn X X GAO GBO °Gn GHO See explanation of function tables on page 3-8. schematics of inputs and outputs _ Q 'LS166 '166 EQUIVALENT OF EACH INPUT OUTPUT EOUIVALENT OF EACH INPUT OUTPUT VCC--~~-- VCC INPUT~~~~-1- 4 kn NOM INPUT -- Parallel and serial inputs: Req Others: Req = 24 kn NOM = 17 kn NOM 1076 7-218 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54166, SN74166 8-BIT SHIFT REGISTERS REVISED AUGUST 1977 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 5.5 V ....,.55°e to 125°C aOe to 7aoe _65°C to 15aoe Supply voltage, Vee (see Note 1) ......... . Input voltage . . . . . . . ......... . Operating free·air temperature range: SN54166 (see Note 2) SN74166 Storage temperature range recommended operating conditions SN74166 SN54166 MIN Supply voltage, Vee NOM MAX 4.5 5 High-level output current, 10H Low·level output current, 10L 5.5 -BOO MIN NOM 4.75 5 MAX 5.25 -BOO 16 Clock frequency, fclock Width of clock or clear pulse, tw (see Figure 1) 0 Mode-control setup time, tsu Data setup time, tsu (see Figure 1) Hold time at any input, th (see Figure 1) 25 V pA mA MHz 20 30 20 ns 30 ns 20 20 ns 0 0 ns °e -55 Operating free-air temperature, T A (see Note 2) 16 25 0 UNIT 125 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL VIK Low-level input voltage MIN SN54166 TYP:j: MAX SN74166 MIN 2 Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II IIH Input current at maximum input voltage High-level input current IlL Low-level input current ~ Vee~ MIN, Vee- MIN, VIH-2V, VIL ~ O.B V, 10H Vee - MIN, VIH-2V, VIL ~ II 2.4 -BOOpA 3.4 0.2 O.B V, IOL=16mA Vee = MAX, VI-5.5V 2.4 0.4 O.B V -1.5 V 3.4 0.2 V 0.4 1 mA J.1.A mA 40 40 Vee - MAX, VI- 0.4 V -1.6 -1.6 los Short-circuit output current~ Vee = MAX Supply current Vee = MAX, See Note 3 -20 90 -57 127 -18 90 V 1 Vee - MAX, VI = 2.4 V ICC UNIT V O.B -1.5 -12mA ~ TYP:j: MAX 2 -57 mA 127 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at V CC = 5 V, T A ~ 25°C. § Not more than one output should be shorted at a time. NOTES: 1. Voltage values are with respect to network ground terminal. 2. An SN54166 in the W package operating at free-air temperatures above 113°C' requires a heat-sink that provides a thermal resistance from Case to free air, ReCA, of not more than 48°C/W. 3. With all outputs open, 4.5 V applied to the serial input, all other inputs except the clock grounded, ICC is measured after a momentary ground, then 4.5 V, is applied to the clock. switching characteristics, Vee = 5 V, T A = 25 e 0 PARAMETER TEST CONDITIONS f max Maximum clock frequency Propagation delay time, high-totPHL low-level output from clear eL=15pF, See Figure 1 Propagation delay time, high-totpHL tpLH low-level output from clock Propagation delay time, low-to- MIN TYP 25 35 MAX UNIT MHz 23 35 ns 20 30 ns 17 26 ns RL = 400 n, high-level output from clock 887 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-219 TYPES SN54lS166,SN74lS166 8·BIT SHIFT REGISTERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . Input voltage . . . . . . . . . . . . . . Operating free·air temperature range: SN54LS166 SN74LS166 Storage temperature range ..••. 7 V . • . . . 7V _55°C to 125°C oOe to 70°C _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74LS166 SN54LS166 MIN NOM 4.5 Supply voltage, Vee 5 MAX MIN NOM 5.5 4.75 5 -400 High·level output current, 10H MAX 5.25 V -400 IJA 4 Low../evel output current, IOL 25 0 Clock frequency, fclock UNIT 0 8 rnA 25 MHz Width of clock or clear pulse, tw (see Figure 1) 30 30 ns Mode-control setup time, tsu 30 30 ns Data setup time, tsu (see Figure 1) 20 20 ns Hold time at any input, lh (see Figure 1) 15 15 ns -55 Operating free·air temperature, TA 125 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage 2 VOH High-level output voltage • Vee= MIN, II =-18mA Vee= MIN, VIH-2V, 2.5 VIL = VIL max, 10H = -400IJA Vee = MIN, VOL Low-level output voltage VIH=2V, Input current at maximum 0.8 V -1.5 -1.5 V 3.4 2.7 0.4 3.4 IIH Vee = MAX, VI=2.7V IlL Low-level input current Vee = MAX, VI 0.4 V lOS Short-circuit output current§ Vee = MAX ICC Supply current -20 See Note 3 0_25 0.4 0.5 0.1 V mA 20 20 IJA -0.4 -0.4 mA -100 -20 22 V 0.35 0.1 VI = 7V Vee = MAX, V 0.7 IIOL =8 mA Vee= MAX, input voltage 2 0.25 IIOL=4mA VIL = VIL max High-level input current II SN54LS166 SN74LS166 UNIT MIN TYp:j: MAX MIN TYP:j: MAX TEST CONDITIONSt 38 -100 mA 38 mA 22 tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC = 5 V, TA = 25°C. . § Not more than one output should be shorted at a time, and duration of short-circuit should not exceed one second. NOTE 3: With all outputs open, 4_5 V applied to the serial input and all other inputs except the clock grounded, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, Vee = 5 V, TA = 25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency MJN TYP 25 35 Propagation delay time, high-totPHL low-level output from clear Propagation delay time, high-to- tpHL eL = 15 pF, UNIT MHz 19 30 ns 8 23 35 ns 8 24 35 ns RL = 2 kn, See Figure 1 low-level output from clock Propagation delay time, low-to- tPLH MAX high-level output from clock 1280 7-220 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DAL.LAS, TEXAS 75222' TYPES SN54166. SN54LS166. SN74166. SN74LS166 8-BIT SHIFT REGISTERS PARAMETER MEASUREMENT INFORMATION TEST VCC POINT TEST TABLE FOR SYNCHRONOUS INPUTS FROM ~~6~~T --~~a-~~~~~~--, TEST OATAINPUT (See Note 0 OUTPUT TESTEO SHIFT/LOAD (SEE NOTE F) FOR TEST ~CL=15PF H ...L (See Note C) Serial Input OV QH at tn+l 4.5V QH at tn+8 LOAD FOR OUTPUT UNDER TEST _ _ _--1"'"\ CLEAR INPUT Vref tw(clear) Ir----------------------- U~re~ ___ _ - r-tn+1 tn (See Note G) ~ -~---3V CLOCK INPUT r----Li -~th '-- 0 V 4tsu~3V Vref ~~ef_ _ _ _ I -.l tpHL (clear-Q) OUTPUT Q - - OV tn+1 tn Ir---~ DATA INPUT (SEE TEST TABLE) 3 V OV I r- - - - - - - - - . . \ Vref I -1 tPLH I.(CLK-~l --lIPHLt-(CLK-Q) Vref VOLTAGE WAVEFORMS NOTE: A. All pulse generators have the following characteristics: Zout '" 50 n; I for '166, Ir .;; 7 ns and tf';; 7 ns; for 'LS166, tr';; 15 ns and tf .;; 6 ns. B. The clock pulse has the following characteristics: tw(clock) .;; 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tw(clear) ;;;, 20 ns and thold = 0 ns. When testing f max , vary the clock PRR. C. C L includes probe and jig capacitance. D. All diodes are 1 N3064 or 1 N916. E. A clear pulse is applied prior to each test. F. Propagation delay times (tpLH and tpH L) are measured at t n +1' Proper shifting of data is verified at t n +8 with a functional test. G. tn = bit time before clocking transition tn+1 = bit time after one clocking transition tn+8 = bit time after eight clocking transitions H. For '166 Vref = 1.5 V; for 'LS166 Vref = 1.3 V. FIGURE 1 7-221 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TTL MSI TYPES SN54167, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS BULLETIN NO DL-S 7211813, DECEMBER 1972 • Perform Fixed-Rate or Variable-Rate Frequency Division • For Applications in Arithmetic, Radar, Digital-to-Analog (D/A), Analog-to-Digital (AID), and other Conversion Operations • Typical Maximum Clock Frequency ... 32 Megahertz SN54167 ••• J OR W PACKAGE SN74167 ••• J OR N PACKAGE (Top VIEW) RATE INPUTS Vee ~ UNITYI ENABLE CLEAR CASCADE INPUT STROBE description These monolithic, fully synchronous, programmable counters utilize Series 54/74 TTL circuitry to achieve 32-megahertz typical maximum operating frequencies. These decade counters feature buffered clock, clear, enable and set-to-nine inputs to control the operation of the counter, and a strobe input to enable or inhibit the rate input/decoding AND-ORINVERT gates. The outputs have additional gating for cascading and transferring unity-count rates. ~ RATE INPUTS SET TOg ~ OUTPUTS ENABLE OUTPUT positive logic: see description NC-No internal connection The counter is enabled when the clear, strobe set-to-nine, and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 10, ie.: M·fin fout = -;0where: M = D'23 + C'2 2 + B'2 1 + A'2 0 for decimal zero through nine. II When the rate input is binary 0 (all rate inputs low), Z remains high. In order to cascade devices to perform two-decade rate mUltiplication (0-99), the enable output is connected to the enable and strobe inputs of the next stage, the Z output of each stage is connected to the unity/cascade input of the other stage, and the SUb-mUltiple frequency is taken from the Y output. For longer words, see typical application data, Figure 1. The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output. All of the inputs of these counters are diode-clamped, and each input, except the clock input, represents one normalized Series 54/74 load. The buffered clock input, used with the strobe gate, is only two Series 54/74 loads. Full fan·out to 10 Series 54/74 loads is available from each of the output. These devices are completely compatible with most TTL and DTL families. Typical dissipation is 270 milliwatts. The SN54167 is characterized for operation over the full military temperature range of -55°C to 125°C, and the SN74167 is characterized for operation from oDe to 70°C. 1076 7-222 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 TYPES SN54167, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS STATE AND/OR RATE FUNCTION TABLE (See Note AI OUTPUTS INPUTS LOGIC LEVEL OR NUMBER OF BCD RATE NUMBER OF PULSES 0 C B A Y Z ENABLE H X H X X X X X H L H H B L L L L L L L 10 H L H 1 C CLEAR ENABLE STROBE NOTES: UNITY/ CLOCK PULSES CASCADE NOTES L L L L L L H 10 H 1 1 1 C L L L L L H L 10 H 2 3 1 C 1 C 1 C L L L L L H H 10 H 2 3 L L L L H L L 10 H 4 4 5 1 C 6 7 1 C 1 C 8 1 C L L L L H L H 10 H L L L L H H L 10 H L L L L H H H 10 H L L L H L L L 10 H 5 6 7 8 L L L H L L H 10 H 9 9 1 C L L L H L H L 10 H 8 8 1 C,D L L L H L H H 10 H 9 9 1 C,D L L L H H L L 10 H 8 8 1 C,D L L L H H L H 10 H 9 9 1 C,D L L L H H H L 10 H 8 8 1 C,D L L L H H H H 10 H 9 9 1 C,D L L L H L L H 10 L H 9 1 E A. H = high level, L = low level, X = irrelevant. All remaining entries are numeric counts. B. This is a simplified illustration of the clear function. The states of clock and strobe can affect the logic level of Y and Z. A low unity/cascade will cause output Y to remain high. C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs. D. These input conditions exceed the range of the decimal rate inputs. E. Unity/cascade can be used to inhibit output Y. functional block diagram and schematics of inputs and outputs EQUIVALENT OF EACH INPUT VCC--~_-- II I INPUT Clock: Req = 2 k.l1 NOM All others: Req = 4 k.l1 NOM TYPICAL OF ALL OUTPUTS VCC OUTPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-223 TYPES SN54167, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) .... . Input voltage . . . . . . . . . . . . . Operating free·air temperature range: SN54167 SN74167 Storage temperature range 7V 5.5V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54167 MIN NOM 4.5 Supply voltage, VCC SN74167 MAX MIN NOM 5.5 4.75 5 MAX V -400 p.A 16 mA -400 16 High·level output current, 10H Low·level output current, 10L 0 Clock frequency, fclock 25 UNIT 5.25 5 0 25 MHz 20 ns Width of clear pulse, tw(clearl 20 15 15 ns Width of set·to·nine pulse t w (set.to-9) 15 15 ns Width of clock pulse, tw(clock) (See Note 2) Enable setup time, tsu: From positive'going transition of clock pulse 25 From negative·going transition of previous clock pulse ns 25 0 t w (clock)-10 0 t w (clock)-10 ns 0 t w (clock)-10 t cp -10 0 20 t w (clock)-10 t cp -10 ns 20 -55 125 0 70 (See Note 2) Enable hold time, th: From positive'going transition of clock pulse From negative'going transition of previous clock pulse Operating free·air temperature, T A ns °c NOTE 2: tw(clock) is the interval in which the clock is high. tcp is the total clock cycle starting with a negative transition. See Figure 1 on SN5497, SN7497 data sheet. • electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL VI Low-level input voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current Low-level input current lOS Short circuit output current§ TYP+ MAX UNIT 2 Input clamp voltage IlL MIN clock input other inputs clock inputs i other inputs VCC- MIN, 11--12mA Vec= MIN, VIH = 2 V, VIL = 0.8 V, 10H = -400Jlfl Vce- MIN, VIH-2V, VIL = 0.8 V, 10L = 16 mA Vee= MAX, VI = 5.5V Vce = MAX, VI = 2.4 V Vee= MAX, Vec- MAX,' 2.4 3.4 0.2 See Note 4 V 1 80 mA -1.6 43 65 V 0.4 40 -18 See Note 3 V V -3.2 VI = 0.4 V Vee= MAX, Vee= MAX leCH Supply current, output high leeL Supply current, output low V 0.8 -1.5 JlA mA -55 mA 99 mA mA NOTES: 3. ICCH is measured with outputs open and all inputs low. 4. ICCL is measured with outputs open and all inputs high except the set·to-nine input which is low. tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. +AII typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time. 1076 7-224 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54167, SN74167 SYNCHRONOUS DECADE RATE MULTIPLIERS switching characteristics, Vec PARAMETERS~ f max tpLH = 5 V, TA = 25°e FROM TO INPUT OUTPUT Enable Enable Strobe Z TEST CONDITIONS MIN TYP 25 32 tpHL tpLH tpHL tpLH Clock Y Clock Z tpHL MAX UNIT MHz 13 20 14 21 12 18 15 23 26 39 20 30 12 18 tpHL 17 26 tpLH 9 14 6 10 9 14 tpLH Z Rate tpHL CL RL tpLH Unity/Cascade Y See Note 5 tpHL tpLH tpHL Strobe Y Clock Enable tpLH = 15pF, = 400 n, Clear tpLH 30 22 33 19 30 33 Y 24 36 Z 15 23 Set-to-9 Enable 18 27 Any Rate Input y 15 23 15 23 tpHL tpHL 10 19 22 tpHL tpLH 6 tpHL ns ns ns ns ns ns ns ns ns ns ns ~fmax is maximum clock frequency. tpLH is propagation delay time, low-to-high-Ievel output. tpH L is propagation delay time, high·to-Iow-Ievel output. NOTE 5: Load circuit, voltage waveforms, and input conditions for measuring switching characteristics are the same as those for the SN5497 and SN7497, page 7-106. TYPICAL APPLICATION DATA This application demonstrates how the decimal-rate multipliers may be cascaded for longer words. Three decades are illustrated (0.999 to 999) although longer words can be implemented by using the pattern shown. The output is decoded either from output Y with a NOR gate or from output Z with a NAND gate. Either method of decoding produces the complement of the output used. ~ I ______________________ -JA~ ~ RATE INPUT______________________ (M) L----------~~~~----~~------_r~~~------e_------_+_r_r_r------~ ,IL-------e--~4_4_4_----~~---e~~~~4_------+_--~ NC OUTPUT .n. OUTPUT"tI FIGURE 1 1076 TEXASINCORPORATED INSTRUMENTS POST OFFICE SOX 5012 • CALLAS. TEXAS 75222 7-225 TYPES SN54LS169A, SN54S168, SN54S169 SN74LS169A, SN74S168, SN74S169 SYNCHRONOUS 4-81T UP/DOWN COUNTERS TTL MSI BULLETIN NO. DL-S 12068, OCTOBER 1976 - REVISED DECEMBER 1980 'S168 ... SYNCHRONOUS UP/DOWN DECADE COUNTERS 'LS169A, 'S169 ... SYNCHRONOUS UP/DOWN BINARY COUNTERS SERIES SN54LS', SN54S' ••• J OR W PACKAGE SERIES SN74LS', SN74S' " • J OR N PACKAGE (TOP VIEW) Programmable Look-Ahead Up/Down Binary/Decade Counters • Fully Synchronous Operation for Counting and Programming • Internal Look-Ahead for Fast Counting • Carry Output for n-Bit Cascading • Fully Independent Clock Circuit TYPICAL MAXIMUM TYPE 'LS169A 'S168, 'S169 CLOCK FREQUENCY COUNTING COUNTING OUTPUTS A TYPICAL POWER DISSIPATION UP DOWN 35MHz 35MHz 100mW 70MHz 55 MHz 500mW V DATA INPUTS positive logic: see description description II These synchronous presettable counters feature an internal carry look·ahead for cascading in high-speed counting applications. The 'S168 is a decade counter and the 'LS169A and 'S169 are 4·bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple·clock) counters. A buffered clock input triggers the four master-slave flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Both count enable inputs (P and f) must be low to count. The direction of the count is determined by the level of the up/down input. When the input is high, the counter counts up; when low, it counts down. Input f is fed forward to enable the carry output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up and approximately equal to the low portion of the QA output when counting down. This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. Changes at control inputs (enable P, enableT, load, up/down) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting)will be dictated solely by the conditions meeting the stable setup and hold times., 1280 7-226 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS169A, SN74LS169A SYNCHRONOUS 4-81T UP/DOWN COUNTERS REVISED DECEMBER 1980 functional block diagrams • I DATAC_(5_)~~~4-----~4-~-------------+--~r---~ DATADl(6~)--~-'-r-----lrttlr-----------------------~ RIPPLE 10----------------------------.....;.,;.;;.; CARRY OUTPUT (15) L...-----------t-- 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-227 TYPES SN54S168, SN54S169, SN74S168, SN74S169 SYNCHRONOUS 4-81T UP/DOWN COUNTERS functional block diagrams CI) a: w I2: :::l o U > a: « 2: co ~ iii '--- 0 UTPUT 10 kn. NOM = 25 kn. NOM UfO: Req = 20 kn. NOM' absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ...... . Input voltage . . . . . . . ...... . Operating free-air temperature range: SN54L.S169A .. SN74L.S169A, Storage temperature range 7V 7V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. • recommended operating conditions SN54LS169A MIN Supply voltage, Vec 4.5 NOM 5 MAX MIN NOM 5.5 4.75 5 -400 High-level output current, IOH 4 Low·level output current, IOL 0 Clock frequency, f clock 25 0 25 25 20 20 Enable P or T 20 20 Load 25 25 Up/Down 30 30 Width of clock pulse, tw(clockl (high or lowl (see Figure 11 Data inputs A, B, C, D Setup time, tsu (see Figure 11 SN74LS169A -55 Operating free·air temperature, T A 5.25 V -400 J.lA 8 mA 25 MHz ns ns 0 0 Hold time at any input with respect to clock, th (see Figure 1) UNIT MAX 125 0 ns 70 °c 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-231 TYPES SN54LS169A, SN74LS169A SYNCHRONOUS 4-81T UP/DOWN COUNTERS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS169A TEST CONDITIONSt PARAMETER MIN VIH High-level input voltage VIL VIK Low-level input voltage Input clamp voltage Vee - MIN, 11--18mA VCC- MIN, VIH-2V, A, B, C, D, P, U/D Clock, T input voltage Load High·level input current Low-level IlL input current VCC= MAX, V 0.4 0.25 0.4 0.35 0.5 0.1 0.1 VI = 7 V 0.1 0.1 A, B, C, 0, P, U/D VCC = MAX, VI = 0.4 V Load lOS Short·circuit output current§ VCC= MAX ICC Supply current VCC= MAX, -20 See Note 2 20 20 40 40 -0.4 -0.4 -0.4 -0.4 -0.8 -0.8 -100 20 mA 0.2 20 20 VI=2.7V Load Clock, T V V A, B, C, 0, P, U/D VCC = MAX, V V 3.4 0.2 Clock, T UNIT MAX 0.8 -1.5 2.7 3.4 0.25 IIOL =4 mA VIH = 2V, VIL=VILmax IIOL=8mA Input current TYP+ 2 2.5 VCC - MIN, at maximum MIN 0.7 -1.5 VIL = VIL max, 10H = -400 p,A VOL Low-level output voltage IIH SN74LS169A MAX 2 VOH High-level output voltage II TYP+ -20 20 34 p,A mA -100 mA 34 mA tFor co~ditlons shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions. +AII typical values are at Vec = 5 V, T A = 25 C. §Not more than one output should be shorted at a time, and duration of the short-cIrcuit should not exceed one second. NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other Inputs grounded and the outputs open. • switching characteristics, Vee = 5 V, T A = 25°e PARAMETERlI FROM (INPUT) TO (OUTPUT) TEST CONDITIONS f max tpLH tpHL tPLH tPHL tpLH tpHL tpLHO tpHLO Clock Clock Enable T Up/Down Ripple carry Any Q Ripple CL=15pF, RL=2kn, See Figures 2 and 3 MIN TYP 25 32 MAX UNIT MHz 23 35 23 35 13 20 15 23 10 14 10 14 Ripple 17 25 carry 19 29 carry and Note 3 ns ns ns ns lIf max :;Maximum clock frequency tpLH :; propagation delay time, low-to-high-Ievel output. tPHL:; propagation delay time, hlgh-to-Iow-Ievel output. 0propagatlon delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase. NOTE 3: Load circuit Is shown on page 3-11. 1280 7-232 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S168, SN54S169, SN74S168, SN74S169 SYNCHRONOUS 4-81T UP/DOWN COUNTERS REVISED AUGUST 1977 schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT - - - - - -....---VCC VCC--~----~'------- 50n NOM 20 kn NOM (LOAD INPUT ONLY) INPUT--o--o-OUTPUT Enable P or T inputs: Req = 1.4 kn NOM Other inputs: Req = 2.8 kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 5.5V 5.5V -55°C to 125°C oOe to 70°C -65°C to 150°C Supply voltage, Vee (see Note 4) Input voltage . . . . . . . . Interemitter voltage (see Note 5) Operating free·air temperature range: SN54S168, SN54S169 (see Note 6) SN74S168,SN74S169 Storage temperature range recommended operating conditions SN54S168 SN74S168 SN54S169 SN74S169 MIN Supply voltage, VCC 4.5 MAX MIN NOM MAX 5 5.5 4.75 5 5.25 V mA High·level output current, IOH -1 -1 Low·level output current, IOL 20 20 mA 40 MHz Clock frequency, fclock 0 Width of clock pulse, tw(clock)(high or low) (see Figure 1) Enable P or T Setup time, tsu (see Figure 1) 10 4 14 14 6 6 20 20 Hold time at any input with respect to clock, th (see Figure 1) 1 -55 Operating free·air temperature, T A (see Note 6) 0 4 Load Up/Down 40 10 Data inputs A, B, C, D NOTES: UNIT NOM 0 I ns ns ns 1 125 • 70 °c 4. Voltage values, except interemitter voltage, are with respect to network ground terminal. 5. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the count enable inputs P and T. 6. An SN54S~68 or SN54S169 in the W package operating at free-ai~ temperatures above 91°C requires a heat sink that provides a thermal resistance from case to free-air. ReCA, of not more than 26 C/W. 817 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-233 TYPES SN54S168, SN54S169, SN74S168, SN74S169 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS REVISED DECEMBER 1980 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54S168 SN54S169 TEST eONDITIONst PARAMETER MIN VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage TYP:!: MAX 2 VOH High·level output voltage VOL Low·level output voltage Vec = MIN, II = -18mA VCC = MIN, VIH = 2V, VIL = 0.8 V, 10H =-1 mA VCC = MIN, VIH = 2 V, 2.5 Input current at maximum input voltage IIH High-level input current 10L = 20mA VCC = M~X, VI = 5.5 V VCC = MAX, VI=2.7V -10 V -1.2 -1.2 V 2.7 3.4 Enable T Other inputs 0.5 1 1 Short·circuit output current§ VCC = MAX Supply cureent VCC= MAX, See Note 2 -40 100 IlA 50 -4 -4 -2 -2 -100 V mA 100 -200 50 VCC = MAX, VI = 0.5 V V 0.5 -200 -10 Other inputs lOS ICC V 0.8 100 Load UNIT TYP:!: MAX 0.8 3.4 Enable T Low·level input current MIN 2 VIL = 0.8 V, II IlL SN74S168 SN74S169 -40 160 100 mA -100 mA 160 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :t:AII tYpical values are at VCC = 5 V, T A = 25°C. § Not I.,u, .. lhan un .. OUtput shouid be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs open. switching characteristics, Vee = 5 V, TA • PARAMETER~ f max tPLH tpHL tPLH tpHL tPLH tpHL tPLHO tPHLO FROM (INPUT) Clock = 25°e TO (OUTPUT) UP/DOWN MIN TYP 40 70 Ripple carry Clock AnyQ Enable T Ripple Up/Down TEST CONDITIONS CL=15pF, RL=280n, See Figures 2 and 3 = HIGH MAX UP/DOWN MIN TYP 40 55 = LOW MAX MHz 14 21 14 20 28 20 21 .28 8 15 8 15 11 15 11 15 12 7.5 11 6 15 22 15 25 Ripple 9 15 8 ,15 carry 10 15 16 22 carry and Note 7 UNIT ns ns ns ns 1f max "" maximum clock frequency tpLH "" propagation delay time, low·to·high·level output tpHL"" propagation delay time, high·to·low·level output 0propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum (9 for 'S168 or 15 for 'S169), the ripple carry output will be out of phase. NOTE 7: Load circuit Is shown on page 3-10. 1280 7-234 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS169A, SN54S168, SN54S169, SN74LS169A, SN74S168, SN74S169 SYNCHRONOUS 4-81T UP/DOWN COUNTERS PARAMETER MEASUREMENT INFORMATION t-- tw(clock) I I ----t I I I CLOCK INPUT ----t \4- tw(clock) I ~ Vref I I I I.- ..I tsu th tsu (inactive state) ----.J I --t.- t h ref I I I 3V i I T--------~---ov I I I I -t INPUTs~1, . V - - - - - - - i - - A,B,C,andD T - - - oV ---.I /4"- \vref 1 Vre~ ----.l--...J .. LOAD INPUT I I --J I+- tsu I (active state) DATA _ _ _ 3V I - - -1- - - - - - - -1-- ,Vref ____________ ~. I ~ ______________________ I i 1 ___________________________----J I --,.-I :C : r- ~th V ref \::~ tsu UP/DOWN INPUT th : I -3V _______ OV I ......I ENABLEP or ENABLE f I ~ I I- ~ I OV T_V:f_ 3V I tsu ~th I I 3V F:0V ":ref VOLTAGE WAVEFORMS NOTES: A. The input pulses are supplied bV a generator having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%, Zout "" 50 for!'LS169A, tr';; 15 ns, tf';; 6 ns, and for 'S168 and 'S169, tr';; 2.5 ns, tf';; 2.5 ns. B. For 'LS169A, Vref = 1.3 V; for 'S168 and 'S169, Vref = 1.5 V. n; FIGURE 1-PULSE WIDTHS, SETUP TIMES, HOLD TIMES ENABLE INPUT f ~, l'~v_re_f 3V _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J,(V'" _ _ _ _ _ _ _ 0 V !--tPHL - . , J RIPPLE CARRY OUTPUT NOTES: • I : . - - tPLH----.I I -----------_... I I 'Vref VOLTAGE WAVEFORMS VOL fref ---VOH A. The input -pulse is supplied by a generator having the following characteristics: PRR·';; 1 MHz, dutY cycle';; 50%, Zout "" 50 n; for I'LS169A, tr .;; 15 ns, tf .;; 6 ns; and for 'S168 and 'S169, tr .;; 2.5 ns, tf';; 2.5 ns. B. tpLH and tpH L from enable T input to ripple carry output assume that the counter is at the maximum count (aA and aD high for \'S168, all a outputs high for 'LS169A and 'S169). C. For'LS169A, Vref = 1.3 V; for 'S168 and 'S'169, Vref = 1.5 V. O. Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down Input is changed, the ripple carry output will follow. If the count is minimum (0) the ripple carry output transition will be in phase. If the count is maximum (9 for 'S168 or 15 for 'LS169A and 'S169), the ripple carry output will be out of phase. FIGURE 2-PROPAGATION DELAY TIMES TO CARRY OUTPUT 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7·235 TYPES SN54LS169A, SN54S168, SN54S169, SN74LS169A, SN74S168, SN74S169 SYNCHRONOUS 4-81T UP/DOWN COUNTERS PARAMETER MEASUREMENT INFORMATION I..tW(c\OCkl.l I 1 I 3V CLOCK INPUT I..-....a-tPLH 1 I OUTPUT 0A _ _ _ _ _ I \......-....a..tPHL 1 (measure at tn+ll 1 I I Vref (measure at tn+21 I \L~f / Y5p---, I ~tPHL I 1 ~tPLH (measure at tn+41 I I (measure at tn+21 I r------------------- ~\-S_ _ _l~f ____ __ I OUTPUT °B I.--.....L- tpHL I. '1 l I I OU;;UT-----------------------~~~~s------i--J~V~~ I (measure at tn+8 l - • I· el tpHL I _____ re f ,\V - - VOL __ I (measure at tn+81 VOH 1 __ __ __ _ _ _ VOL tPLH pi 1 I RIPPLE CARRY OUTPUT (measure at t n +l0 I or tn+16 1 '\.v~::e Note B) 1.>---'+-1 ... I I VOL ,..,.-~'~I~ tpLH ·~s'J--------lV: OUTPUT 00 - (measure at tn+41 - I - tPLH 'I 114'1>---'t-I- tpH L I -----------', - VOH (measure at t n +l0 or tn+161 (See Note Bl - - - VOH - - - - - - - - - - - - - VOL UP-COUNT VOLTAGE WAVEFORMS NOTE5: A. The input pulses are supplied by a generator having the following characteristics: PRR .-; 1 MHz, duty cycle'-; 50%, Zout "" 50 U; for 'L5169A, tr'-; 15 ns, tf'-; 6 ns; and for '5168 and '5169, tr'-; 2.5 ns, tf'-; 2.5 ns. Vary PRR to measure f max • B. Outputs QD and carry are tested at t n +10 for the '5168 and at t n +16 for the 'L5169A and '5169, where tn is the bit-time when ,all outputs. are low, C, For 'L5169A, Vref = 1.3 V; for '5168 and '5169,V re f = 1.5 V. FIGURE 3-PROPAGATION DELAY TIMES FROM CLOCK 1280 7-236 TEXAS INCOI{PORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54170, SN54LS170, SN74170, SN74LS170 4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS BULLETIN NO. DL-S 7611349, MARCH 1974-REVISED OCTOBER 1976 • Separate Read/Write Addressing Permits Simultaneous Reading and Writing • Fast Access Times ... Typically 20 ns WRITE SELECT Vcc • Organized as 4 Words of 4 Bits • Expandable to 1024 Words of n·Bits • For Use as: Scratch·Pad Memory Buffer Storage between Processors Bit Storage in Fast Multiplication Designs • Open-Collector Outputs with Low Maximum Off-State Current: '170 ... 30 ~A 'LS170 ... 20llA • SN54LS670 and SN74LS670 Are Similar But Have 3-State Outputs SN54170, SN54LS170 ••• J OR W PACKAGE SN74170, SN74LS170 ••• J OR N PACKAGE (TOP VIEW) D't~A 'W';"""W;" ENABLE WRITE READ OUTPUTS "Q"i'"Ci2' 02 02 03 04 04 03 ~~~GND DATA READ SELECT OUTPUTS positive logic: see description description The '170 and 'LS170 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The registerfile is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and 8 in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, G R, is high, the data outputs are inhibited and remain high. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. This arrangement-data-entry addressing separate from data-read addressing and individual sense line-eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (30 nanoseconds typical) and the read time (25 nanoseconds typical). The register file has a nondestructive readout in that data is not lost when addressed. All '170 inputs and all inputs except the read enable and write enable of the 'LS170 are buffered to lower the drive requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input-clamping diodes minimize switching transients to simplify system design. High-speed, double-ended AND-DR-INVERT gates are employed for the read-address function and drive high-sink-current, open-collector outputs. Up to 256 of these outputs may be wire-AND connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide n-bit word length. The SN54170 and SN54LS170 are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74170 and SN74LS170 are characterized for operation from O°C to 70°C. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-237 TYPES SN54170. SN54LS170. SN74170. SN74LS170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS logic READ FUNCTION TABLE (SEE NOTES A AND 01 WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI WRITE INPUTS WB NOTES: WORD L WA L GW L L H L H L H L H L X X H GR 01 02 03 04 L RA L L WOB1 WOB2 WOB3 WOB4 0 1 2 3 RB 0=0 00 00 00 00 O=D 00 00 00 O=D 00 00 00 00 00 L H L W1B1 W1B2 W1B3 W1B4 H L L W2B1 W2B2 W2B3 W2B4 00 00 O=D H H L W381 W382 W383 W3B4 00 00 X X H H H H H A. H = high level, L = low level, X = irrelevant. B. (a = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. c. a O = the level of a before the indicated input conditions were established. D. WOBl = The first bit of word 0, etc. functional block diagram • OUTPUTS READ INPUTS '170 DATA INPUTS 141 ~ lSI IIII ~ WRITE INPUT READ INPUT 374 7·238 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54170, SN54LS170, SN74170, SN74LS170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS REVISED OCTOBER 1976 functional block diagram 'LS170 DATA INPUTS OUTPUTS II I WRITE INPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage:'170 'LS170 Off-state output voltage: '170 'LS170 Operating free-air temperature range: SN54170, SN54LS170 (see Note 2) SN74170,SN74LS170 Storage temperature range NOTES: 7V 5.5V 7V 5.5V . _ .. 7V -55°C to 125°C _ oOe to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. An SN54170 in the W package operating at free-air temperatures above 105°C requires a heat sink that provides a thermal resistance from case to free-air, ROCA, of not more than·38°c/W 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-239 TYPES SN54170, SN74170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS recommended operating conditions SN54170 SN74170 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V 5.5 V 16 mA Supply voltage, Vee High-level output voltage, VOH 5.5 16 Low-level output current, IOL Width of write-enable or read-enable pulse, tw Data input with respect to Setup times, high- or low-level data write enable, tsu(D) (see Figure 2) Write select with respect to write enable, tsu(W) Data input with respect to Hold times, high- or low-level data write enable, th(D) (see Note 3 and Figure 2) Write select with respect to 25 25 ns 10 '10 ns 15 15 ns 15 15 ns 5 5 ns write enable, th(W) NOTES: 25 25 Latch time for new data, tlatch (see Note 4) Operating free-air temperature range, T A (see Note 2) UNIT MIN -55 125 ns 0 70 °e 2. An SN54170 in the W package operating at free-air temperatures above 105°C requires a heat sink that provides a thermal resistance from case to free-air, ROCA, of not more than 3SoC/W. 3. Write select setup time will protect the data written into the previous address. If protection of data in the previous address is not required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W) will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into. 4. Latch time is the time allowed for the Internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location immediately after that location has received new data. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER • VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH High-level output current MIN TYPt MAX 2 V 0.8 VOL Low-level output voltage UNIT V Vee = MIN, 11= -12 mA Vee - MIN, VOH - 5.5 V, VIH=2V, VIL = 0.8 V Vee = MIN, VIH=2V, VIL = 0.8 V, IOL=16mA VI = 5.5 V VI = 2.4 V 40 j.lA VI = 0.4 V -1.6 mA II I nput current at maximum input voltage IIH High-level input current = MAX, Vee = MAX, IlL Low-level input current Vee = MAX, lee Supply current Vee -1.5 V 30 0.2 0.4 1 Vee = MAX, ISN54170 127§ 140 See Note 5 127§ 150 ISN74170 j.lA V mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAil typical values are at Vee = 5 V, T A = 25°C. §Typical supply current shown is an average for 50% duty cycle. NOTE 5: Maximum ICC is guaranteed for the following worst-case conditions: 4.5 V is applied to all data inputs and both enable inputs, all address inputs are grounded, and all outputs are open. 1076 7-240 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54170, SN74170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS switching characteristics, Vee = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) Read enable AnyQ PARAMETER~ tPLH TEST CONDITIONS CL=15pF, tpHL RL = 400 n, tpLH Read Select AnyQ See Figures 1 and 2 Write enable AnyQ CL=15pF, tpHL tpLH tpHL RL=400n, tPLH AnyQ Data See Figures 1 and 3 tpHL MIN TYP MAX UNIT 10 15 20 30 23 35 30 40 25 40 34 45 20 30 30 45 ns ns ns ns ~tpLH "" propagation delay time, low-to-high-Ievel output tpH L "" propagation delay time, high-to-Iow-Ievel output schematics of inputs and outputs '170 '170 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT VCC----------4~------OUTPUT 4kn NOM • INPUT 74 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-241 I TYPES SN54LS170, SN74LS170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS REVISED DECEMBER 1980 recommended operating conditions SN54LS170 Supply voltage, Vee MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V 5.5 V 5.5 Low·level output current, IOL 8 4 Width of write-enable or read·enable pulse, tw Data input with respect to Setup times, high- or low-level data write enable, tsu(D) (see Figure 2) Write select with respect to write enable, tsu(WL Data input with respect to Hold times, high- or low-level data write enable, th(D) (see Note 3 and Figure 2) Write select with respect to Latch time for new data, tlatch (see Note 4) mA 25 25 ns 10 10 ns 15 15 ns 15 15 ns 5 5 ns write enable, th(W) 25 Operating free-air temperature range, T A UNIT NOM High·level output voltage, VOH NOTES: SN74LS170 MIN 25 -55 125 ns 0 70 °e 3. Write·select setup time will protect the data written into the previous address. If protection of data in the previous address is not required, tsu(W) Can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W) will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into. 4. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location ImmediatelY after that location has received new data. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • VI H High-level input voltage VI L Low-level input voltage VI K Input clamp voltage IOH TEST CONDITIONSt Input current at Any D, R, or W, maximum input voltage GR orGW Any D, R,orW Low-level input current Supply current MAX 2 = -18 mA Vee = MIN, II Vee= MIN, VOH = 5.5 V, SN74LS170 MIN TYP:!= MAX UNIT V 0.7 0.8 V -1.5 -1.5 V 100 100 Vee = MIN, \IOL = 4 mA 0.25 0.4 0.25 0.4 VIH = 2 V, I~-=----+--------I--------l VIL = VIL max IOL = 8 mA 0.35 0.5 VOL Low-level output voltage lee TYP:!= 2 High-level output current High-level input current SN54LS170 MIN GR or GW Any D, R, orW GR orGW VI = 7V Vee = MAX, VI = 2.7 V Vee= MAX, Vee = MAX, VI = 0.4 V Vee = MAX, See Note 6 0.1 0.1 0.2 0.2 20 20 40 40 -0.4 -0.4 -0.8 25 40 25 -0.8 40 JJ.A V mA JJ.A mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at VCC = 5 V, T A = 25°C. NOTE 6: ICC is measured under the following worst-case conditions: 4.5 V is applied to ali data inputs and both enable inputs, all address inputs are grounded, and all outputs are open. 128( 7·242 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS170. SN74LS170 4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS switching characteristics, Vee PARAMETER~ tPLH =5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Read enable Any Q TEST CONDITIONS CL=15pF, tpHL RL = 2 kn, tPLH Read select Any Q Write enable AnyQ See Figures 1 and 2 tpHL tPLH CL=15pF, tpHL RL = 2 kn, tPLH AnyQ Data See Figures 1 and 3 tpHL ~tpLH tpHL == propagation delay time, == propagation delay time, MIN TYP MAX 20 30 20 30 25 40 24 40 30 45 26 40 30 45 22 35 UNIT ns ns ns ns low-to-high-Ievel output high-to-Iow-Ievel output schematics of inputs and outputs 'LS170 'LS170 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS Vee - - - -....- - - INPUT - -_a- .................... __ ~OU"UT • I Any D, R, or W: Req = 20 kn NOM GR or GW: Req =10 kn NOM 374 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-243 TYPES SN54170, SN54LS170, SN74170, SN74LS170 4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS REVISED MARCH 1974 PARAMETER MEASUREMENT INFORMATION Vcc -tJCL L FROM OUTPUT UNDER TEST TEST POINT CL includes probe and jig capacitance LOAD CIRt:UIT FIGURE 1 \ : : : , - - - - - _ _ _ _ _ 3V :-:'~~;~~L:,C;. ~v", I (s.. Note AI ~ :- tSU(~ I OV : - th(WI 3V Dl'D2.D30rD~ i I (SHNO!eAI WAITE·ENABLE INPUTGW ~ I 'W---i lire' ~IPLH 3V OUTPUT Vrel _ _ _ _ _ _ _ _ _ _ _ _ OV ~tl'lCh---'" : INPUT GW ~thiDi-------_OV ~l1U(01 I Ql,Q2,Q30rQ4 • ______ r., _______ I \V", ref ref VOL VOLTAGE WAVEFORM 1 : ,--_ _ _ 0 V i\ DATA INPUT \ . V READ'ENABLE~Vref IN'UTGR : OUTPUT I--+.,HLI !+-oj 01,02, D3 or 04 3V I INPUTGW IIIVDH I Vre' I .... I Vrel tPHL~ _ _ _--.J r--------, _----':I--""i ___-JI "HL -I----VOL I / reI ~ I OV fPLH ~ 01,02,03,or04 NOTES: ___ i~ ~_·=- I OV "\. V re , to--'w--T-j I 3V ~tPHL ____ ______ 3V If V -'1 IS.. Note BI -----------311 ' -_ _ _ _ _ _ _ __ ----~IV I~----VOH ~ INPUT AA or AS \ -ref II ~I I Vrel I IIrel DATA'N'UT 01,02,03, or D4 -1v OATA INPUT OUTPUT j....-...l-tPLH I Vrel 01,02,03,orQ4 _ _ _ _ _ _ '---_ _ _ _ _ _ _ _.J VOLTAGE WAVEFORMS VOLTAGE WAVEFORM 2 FIGURE 2 FIGURE 3 A. High-level input pulses at the select and data inputs are illustrated in Figure 2; however, times associated with low-level pulses are measured from the same reference points. B. When measuring delay times from a read-select input, the read-enable input is low. When measuring delay times from the read-enable input, both read-select inputs have been established at steady states. C. In Figure 3, each select address is tested. Prior to the start of each of the above tests, both write and read address inputs are stablized with WA = RA and WB = RB. During the test G R is low. D. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz, Zout '" 50 fl, duty cycle';; 50%, tr .;; 10 ns and tf .;; 10 ns for' 170, and tr .;; 15 ns and tf .;; 6 ns for' LS 170. D. For '170, Vref = 1.5 V; for 'LS170, Vref = 1.3 V. 1076 7·244 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TTL LSI TYPE SN74172 16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS BULLETIN NO. DL·S 7211744, MAY 1972 - • Independent Read/Write Addressing Permits Simultaneous Reading and Writing • Organized as Eight Words of Two Bits Each J OR N DUAL·IN·LlNE PACKAGE (TOP VIEW) WRITE • Fast Access Times: From Read Enable ... 15 ns Typical From Read Select ... 33 ns Typical o Three·State Outputs Simplify Use in Bus·Organized Systems • Applications: Stacked Data Registers Scratch·Pad Memory Buffer Storage Between Processors Fast Multiplication Schemes REVISED DECEMBER 1972 DATA INPUTS WRITE WRITE/READ ADDRESS READ ENABLE OUTPUTS VCCADf~E~E~~LE~~~ ~Wl~I*E ~CLOCK~~ WRITE ADDRESS ENABLE description DATA INPUTS READ ADDRESS GND OUTPUTS positive logic: see description The SN74172, containing the equivalent of 201 gates on a monolithic chip, is a high-performance 16-bit register file organized as eight words of two bits each. I. WRITE ADDRESS Multiple address decoding circuitry is used so that the read and write operation can be performed independently on two word locations. This provides a true simultaneous read/write capability. Basically, the file consists of two distinct sections (see Figure A). ENABLE lGW (31 ~ --, r-- ! I p-J.L-I-I...L..... I I I I I I I : 1 lOA Section 1 permits the writing of data into any two-bit word location while reading two bits of data from another location simultaneously. To provide this flexibility, independent decoding is incorporated. 12111 I II I 8~~~;~~ixL~~E DUAL , LINE l08t1NE DEMULTIPLEXER :114. ,OA I I 1411 I r--~~H;~t ----I I I I I I I Section 2 of the register file is similar to section with the exception that common read/write address circuitry is employed. This means that section 2 can be utilized in one of three modes: lOA (211, 20B 1511 2811 STORAGE REGISTE~ I I I 1) Writing new data into two bits 2) Reading from two bits 3) Writing into and simultaneously reading from the same two bits. Regardless of the mode, the operation of section 2 is entirely independent of section 1. FIGURE A 1272 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·245 TYPE SN74172 16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS description (continued) The three-state outputs of this register file permit connection of up to 129 compatible outputs and one Series 54/74 high-logic-level load to a common system bus_ The outputs are controlled by the read-enable circuitry so that they operate as standard TTL totem-pole outputs when the appropriate read-enable input is low or they are placed in a high-impedance state when the associated read-enable input is at a high logic level. To minimize the possibility that two outputs from separate register files will attempt to take a common bus to opposite logic levels, the read-enable circuitry is designed such that disable times are shorter than enable times_ All inputs are buffered to lower the drive requirements of the clock, read/write address, and write-enable inputs to one normalized Series 54/74 load, and of all other inputs to one-half of one normalized Series 54/74 load. Functions of the inputs and outputs of the SN74172 are as shown in the following table. FUNCTION SECTION 2 DESCRIPTION Write Address 1WO, 1W1, 1W2 2W/RO, 2W/R1, 2W/R2 Binary write address selects one of eight two-bit word locations. Write Enable 1GW 2GW When low, permits the writing of new data into the selected word location on a positive transition of the clock input. lOA,lOB 2DA,2DB Data at these inputs is entered on a positive transition of the clock input into the location selected by the write address inputs if the write enable input is low. Since the two sections are independent, it is possible for both write functions to be activated with both write addresses selecting the same word location. If this occurs and the information at the data inputs is not the same for both sections (i.e., and/or 1DA*-2DA 1 DB *- 2DB) the low-level data will predominate in each bit and be stored. Read Address 1RO,1R1,1R2 Common with write address Binary write address selects one of eight two-bit word locations. Read Enable 1GR 2GR Data Outputs 1QA, 1QB 2QA,2QB Data Inputs • SECTION 1 Clock When read enable is low, the outputs assume the levels of the data stored in the location selected by read address inputs. When read enable is high, the associated outputs remain in the high-impedance state and neither significantly load nor drive the lines to which they are connected. The positive-going transition of the clock input will enter new data into the addressed location if the write enable input is low. The clock is common to both sections_ CK 572 7·246 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPE SN74172 16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note 1) Input voltage . . . . . Output voltage (see Note 2) Operating free·air temperature range ..... . Storage temperature NOTES: 7V 5.5 V 5.5 V oOe to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. This is the maximum voltage which should be applied to any output when it is in the high-impedance state. recommended operating conditions Supply voltage, Vee MIN NOM 4.75 5 MAX UNIT High-level output current, 10H Low-level output current, 10L Clock frequency, f clock Width of clock pulse, t w (c1ock) 0 5.25 V -5.2 16 mA mA 20 MHz 25 Write select High-level data Setup time, tsu(see Figure 1) Hold time, th(see Figure 1) ns t w (clock)+10 30 Low-level data 45 Write enable 35 Write select 0 Write enable 0 ns ns High-level data Data release time, trelease (see Rgure 1) 10 Low-level data Operating free-air temperature, T A 10 70 0 ns °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage MIN TYP:j: MAX UNIT V 2 0.8 VOL Low-level output voltage 10(0ft) Off-state (high-impedance state) output current Vee- MIN, 11- -12 mA Vec- MIN, VIH - 2 V, VIL; 0.8 V, 10H; -5.2 mA Vee- MIN, VIH - 2 V, -1.5 2.4 0.4 10L; 16 mA Vo - 2.4 V 40 Vee; MAX, Vo; 0.4 V -40 II Input current at maximum input voltage Vee- MAX, IIH High-level input current Vee; MAX, VI- 5.5V VI; 2.4 V Vee; MAX, VI; 0.4 V lOS ICC Low·level input current • I 0.2 Vee - MAX, IlL V V 3 VIL; 0.8 V, 12W/RO, 2W/R1, 2WIR2, 1 GW, 2GW, or clock V 1 40 -1.6 I Any other input V j.lA mA j.lA mA -0.8 Short-circuit output current S Vee; MAX Supply current Vee- MAX, Outputs open -18 All inputs at 4.5 V, 112 -55 mA 170 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. fAil typical values are at VCC; 5 V, T A; 25°C. § Not more than one output should be shorted at a time. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·247 TYPE SN74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS switching characteristics, Vee = 5 V, TA =25°e, RL =400 n TEST PARAMETER MIN CONDITIONS f max Maximum clock frequency tpLH Propagation delay time, low-to-high-Ievel output from read select TYP MAX UNIT 20 tpHL Propagation delay time, high-to-Iow-Ievel output from read select tpLH Propagation delay time, low-to-high-Ievel output from clock tpHL Propagation delay time, high-to-Iow-Ievel output from clock CL MHz = 50 pF, See Figure 1 33 45 30 45 35 50 35 50 tZH Output enable time to high level 14 30 tZL Output enable time to low level 16 30 tHZ Output disable time from high level CL 6 20 tLZ Output disable time from low level See Figure 1 11 20 = 5 pF, ns ns ns ns PARAMETER MEASUREMENT INFORMATION r-' w -----: 3v V,5V 1-"10m_~~:""------Ov CLOCK INPUT ......---(Soo Note CI.j.-.f-'h ----,~~::---3V WRITE SELECT INPUTS ~!::~ _________ L~ , ov I WRITE ~~~~~i 1.5 V " ' tsu II I DATA INPUT (LOW·LEVELDATAI WAVEFORM I ISeeNote BI ~~I!.~_---3V ~. I Y. WAVEFORM 2 (See Note BI 0V -------t ~tr.18ase ~5V ~ I ~:: i---'ZL----, . ~-.;u-~ DATA INPUT (HIGH·LEVEL DATAl-.-./' 1.5 V I-'LZ-1 : -t ---- ~ 4.5 v:I ISlclosed, '"\l.1.5V :S2open ~ : - - - tZH----i ~;;t:':d :~! :~O~ed ~"1.5V ~==~--~VOl ~ tHZ-: 0.5 v 0.5 V ~~VOH L~~~_~ov Sland ==1.5V 52 closed 3V 1.5VjY ~ ENABLE AND DISABLE TIMES FROM READ ENABLE J.------- OV ~'h 'su 'I ~3V NOTES: ~~:.::.---OV ____________________-+r:__ I 1.5~ . "\......VDL f.-'PLH-+t l/:-:-I VOH /"1.5 V OUTPUT --------------------------' A. Input waveforms are supplied by pulse generators having the following characteristics: tr';; 7 ns, tf';; 7 ns, PRR = 1 MHz, Zout '" 50 n. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled. Waveform 2 is for an output with internal conditions such that the output is high except when disabled. C. Write select setup 'time, as specified, will protect data .P_LH~~--VOH i OUTPUT • ~5V READ ENABLE INPUT "L 1.5V -VOL written into previous address. D. Load circuit is shOwn on page 3-10. SWITCHING TIMES FROM CLOCK INPUT VOLTAGE WAVEFORMS FIGURE 1 schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC------.------ VCC INPUT OUTPUT 2W/RO, 2W/Rl, 2W/R2, lGW, 2GW, or Clock: Req = 4 kn NOM Other inputs: Req = B kn NOM 1076 7·248 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS, TEXAS 75222 TYPES SN54173, SN54LS173A, SN74173, SN74LS173A 4-81T D-TYPE REGISTERS WITH 3-STATE OUTPUTS TTL MSI BULLETIN NO. DL·S 11721, OCTOBER 1976-REVISED JANUARY 1981 • Three-State Outputs Interface Directly with System Bus • Gated Output-Control Lines for Enabling or Disabling the Outputs • SN54173, SN54LS173A •.. J OR W PACKAGE SN74173, SN74LS173A ••• JaR N PACKAGE (TOP VIEW) Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: DATA INPUTS A Parallel Load Do Nothing (Hold) For Application as Bus Buffer Registers • TYPICAL MAXIMUM PROPAGATION CLOCK POWER DELAY TIME FREQUENCY DISSIPATION '173 23 ns 35 MHz 250mW 'LS173A 18 ns 50 MHz 95mW TYPE TYPICAL description OUTPUTS The '173 and 'LS173A four-bit registers include D-type flip-flops featuring totem-pole three-state o\Jtputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs may be connnected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. positive logic: see function table FUNCTION TABLE INPUTS DATA ENABLE DATA OUTPUT CLEAR CLOCK G1 G2 D H X X X X L L L X X X 00 L t t t t H X X 00 X H X L L L 00 L L L H H L L L Q 11 I When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential operation of the flilJ"flops is not affected. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. Copyright © 1981 by Texas Instruments Incorporated 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-249 TYPES SN54173, SN54LS173A, SN74173, SN74LS173A 4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input voltage: '173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V 'LS173A 7V Off-state output voltage ...................................................... " 5.5 V Operating free-air temperature range: SN54173, SN54LS173A . . . . . . . . . . . . . . . . . . . . . . . _55°e to 125° e SN74173,SN74LS173A . . . . . . . . . . . . . . . . . . . . . . . . . . 00eto700e Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65° e to 150° e NOTE 1: Voltage values are with respect to network ground terminals. functional block diagram and schematics of inputs and outputs '173 EQUIVALENT OF EACH INPUT VCC3-- 4 kfl NOM INPUT M (1) OUTPUT CONTROL { N -- (2) TYPICAL OF ALL OUTPUTS • 'LS173A EQUIVALENT OF EACH INPUT VCC---......- 20 kfl NOM I NPUT -'~"""---1'- ~~A~(1~1)______4-____~~ TYPICAL OF ALL OUTPUTS -----....--VCC 4Q CLEAR (15) OUTPUT 181 7-250 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54173, SN74173 4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS recommended operating conditions SN54173 MIN Supply voltage, Vee SN74173 NOM MAX 4.5 5 5.5 MIN 4.75 NOM MAX 5 -2 High-level output current, 10H 16 Low-level output current, 10L 0 Input clock frequency, fclock Width of clock or clear pulse, tw Setup time, tsu 20 20 17 17 Data 10 10 elear inactive state 10 10 Data 2 2 10 10 -55 Operating free-air temperature, T A 125 V -5.2 mA 16 mA 25 MHz 0 Data enable Data enable Hold time, th 25 UNIT 5.25 ns ns ns 70 0 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage MIN TYP:j: MAX UNIT V 2 VOL Low-level output voltage IO(off) Off-state (high-impedance state) output current VCC- MIN, II = -12 mA Vee = MIN, VIH=2V, VIL = 0.8 V, 10H = MAX Vce = MIN, VIH~2V, VIL = 0.8 V, 10L = 16 mA 0.8 V -1.5 V V 2.4 0.4 Vee = MAX, I Vo = 2.4 V 40 VIH =2 V I Vo = 0.4 V -40 V JJA II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 IIH High-level input current Vee = MAX, VI = 2.4 V 40 JJA IlL Low-level input current Vee - MAX, VI-0.4V -1.6 mA lOS Short-circuit output currentS Vee = MAX -70 mA lee Supply current Vee = MAX, 72 mA -30 See Note 2 50 mA tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time. NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G1, G2, and all data inputs grounded; and the clock input and M at 4.5 V. switching characteristics, Vee = 5 V, TA = 25°e, RL = 400 • n PARAMETER TEST CONDITIONS f max Maximum clock frequency tPHL Propagation delay time, high·to-Iow-Ievel output from clear input tPLH Propagation delay time, low-to-high·level output from clock input eL = 50 pF, See Note 3 MIN TYP 25 MAX 18 27 28 43 tPHL Propagation delay time, high·to-Iow-Ievel output from clock input 19 31 tpZH Output enable time to high level 7 16 30 tpZL Output enable time to low level 7 21 30 14 20 tPHZ Output disable time from high level eL=5pF, 3 5 tpLZ Output disable time from low level See Note 3 3 11 UNIT MHz 35 ns ns ns ns NOTE 3: Load circuits and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE B ... dynamic input activated by transition from a high level to a low level. I I 1272 7·254 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN748175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR REVISED OCTOBER 1976 schematics of inputs and outputs SN54174,SN54175,SN74174,SN74175 ~--------------------------------, EaUIVALENT OF ALL INPUTS r---------------------------------~ TYPICAL OF ALL OUTPUTS ---VCC VCC--""--- INPUT OUTPUT Clock,D: Req; 8 kn NOM Clear: Req; 4 kn NOM SN54LS174,SN54LS175,SN74LS174,SN74LS175 ~-------E-a-U-IV-A-L-E-NT-O-F-A-L-L-I-NP-U-T-S--------' r---------T-Y-P-IC-A-L-O~F-A-LL-O-U-T~P-UT-S--------~ - - - - - - - . - - Vec V C C - -........- - - - - 120 n NOM I NPUT ---..~Llr~ ....- ........ - - ~-+--OUTPUT 117 Clock: Req; 17 kn NOM Clear, D: Req; 20 kn NOM SN54S174, SN54S175, SN74S174, SN74S175" ~------------------------------~ EaUIVALENT OF ALL INPUTS ~--------------------------------~ TYPICAL OF ALL OUTPUTS ----=-:::-+-V ce VCC----- INPUT ~-+-- OUTPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-255 TYPES SN54174. SN54175. SN74174. SN74175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ............ . Input voltage . . . . . . . ............ . Operating free·air temperature range: SN54174, SN54175 Circuits SN74174, SN74175 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, Vee SN54174, SN54175 SN74174, SN74175 MIN MAX MIN NOM MAX 5 5.5 4.75 5 5.25 V -SOO /lA 4.5 'High-Ievel output current, 10H -SOO Low·level output current, 10L 16 Clock frequency, fclock 0 Width of clock or clear pulse, tw I Data input I Clear inactive·state Setup time, tsu 25 0 16 mA 25 MHz 20 20 ns 20 20 ns 25 25 ns 5 5 Data hold time, th Operating free·air temperature, T A UNIT NOM -55 125 ns 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage II TYP+ MAX 2 VOH High·level output voltage VOL MIN Low-level output voltage Vee= MIN, II = -12 mA Vee= MIN, VIH=2V, VIL=O.SV, 10H = -SOO/lA Vee- MIN, VIH - 2 V, VIL = O.S V, 10L = 16 mA 2.4 UNIT V O.S V -1.5 V 3.4 0.2 V 0.4 V II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 IIH High·level input current Vee = MAX, VI = 2.4 V 40 /lA IlL Low·level input current Vee = MAX, VI = 0.4 V -1.6 mA lOS Short-circuit output current§ Vee = MAX ICC Supply current Vee = MAX, See Note 2 SN54' -20 SN74' -lS -57 -57 '174 45 65 '175 30 45 mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for ·the applicable device type. tAli typical values are at V CC = 5 V. T A = 25° C. §Not more than one output should be shorted at a time. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER f max TEST CONDITIONS Maximum clock frequency Propagation delay time, low·to·high-Ievel output from clear tpLH (SN54175, SN74175 only) tpHL Propagation delay time, high·to-Iow-Ievel output from clear tpLH Propagation delay time, low-to·high·level output from clock CL=15pF, RL = 400 n, See Note 3 tpHL Propagation delay time, high·to-Iow·level output from clock MIN TYP 25 35 MAX UNIT MHz 16 25 ns 23 35 ns 20 30 ns 24 35 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-256 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS174, SN54LS175, SN74LS174, SN74LS175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ............... . Input voltage . . . . . . . ............... . Operating free·air temperature range: SN54LS174, SN54LS175 Circuits SN74LS174, SN74LS175 Circuits Storage temperature range 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS174 SN74LS174 SN74LS175 SN54LS175 Supply voltage, VCC MI!'I 4.5 NOM MAX 0 30 5 High-level output current, IOH Low-level output current, IOL Clock frequency, fclock Width of clock or clear pulse, tw [ Data input Clear inactive·state Setup time, tsu l 5.5 4.75 -400 4 UNIT NOM MAX 5 5.25 -400 8 V j.lA rnA 30 MHz 0 20 20 ns 20 25 20 25 ns 5 5 Data hold time, th Operating free-air temperature, T A MIN -55 125 ns 70 0 ns °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL VIK Low-level input voltage Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage TEST CONDITIONSt SN54LS174 SN54LS175 MIN TVP:j: MAX 2 SN74LS174 SN74LS175 UNIT MIN TVP:j: MAX 2 V 0.7 VCC; MIN, II; -18mA Vec; MIN, VIH;2V, -1.5 VIL; VILmax, IOH; -400 j.lA VCC; MIN, VIH; 2 V, VIL; VIL max VI;7 V VI; 2.7 V VI;O.4V High·level input current IlL Low-level input current Vee; MAX, Vec; MAX, lOS Short-circuit output current § Vce; MAX 3.5 0.25 \IOL; 4 rnA 2.7 0.4 IIOL; 8mA Vec; MAX, IIH 2.5 -20 0.8 V -1.5 V 3.5 V 0.25 0.4 0.35 0.5 V 0.1 0.1 rnA 20 20 j.lA -0.4 -0.4 rnA -100 -20 -100 rnA 16 26 16 26 rnA 18 18 11 11 t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at V CC = 5 V. T A = 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. ICC Supply current Vce; MAX, switching characteristics, Vee See Note 2 I 'LS174 I'LS175 = 5 V, T A = 25° C PARAMETER TEST CONDITIONS f max Maximum clock frequency 'LS174 MIN TVP 30 40 'LS175 MAX tpLH Propagation delay time, low-to-high-Ievel output from clear tpHL Propagation delay time, high-to-Iow-Ievel output from clear CL; 15pF, RL; 2k~l 23 35 tPLH Propagation delay time, low-to-high-Ievel output from clock tpH L Propagation delay time, high-to-Iow-Ievel output from clock See Note 4 20 21 MIN TVP 30 40 MAX 20 20 30 30 30 13 30 16 25 25 UNIT MHz ns ns ns ns NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-257 TYPES SN54S174. SN54S175. SN74S174. SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . Input voltage . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54S174, SN54S175 Circuits SN74S174, SN74S175 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C . O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S174, SN54S175 Supply voltage, VCC SN74S174, SN74S175 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -1 mA -1 High·level output current, 10H 20 Low-level output current, 10L a Clock frequency, fclock Pulse width, tw Setup time, tsu 75 a Clock 7 7 Clear 10 10 Data input 5 5 Clear inactive·state 5 5 3 3 Data hold time, th Operating free·air temperature, T A UNIT MIN 125 -55 20 rnA 75 MHz ns ns ns a °c 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL VIK Low·level input voltage TYP:j: MAX UNIT V 2 Input clamp voltage VOH High-level output voltage I MIN VCC = MIN, II = -18mA VCC= MIN, VIH = 2 V, LSN54S' 2.5 3.4 VIL = 0.8 V, 10H =-1 rnA ISN74S' 2.7 3.4 VCC= MIN, VIH=2V, VIL = 0.8 V, 10L = 20 rnA 0.8 V -1.2 V V VOL Low-level output voltage II I nput current at maximum input voltage VCC= MAX, VI = 5.5 V 1 IIH High-level input current VCC = MAX, VI = 2.7 V 50 JJA IlL Low-level input current VCC = MAX, VI = 0.5 V -2 rnA lOS Short-circuit output current§ VCC= MAX -100 rnA ICC Supply current 0.5 -40 VCC = MAX, See Note 2 1'174 90 144 1'175 60 96 V rnA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. :tAli typical values are at V CC = 5 V, T A = 25° C. §Not more than one output sh'ould be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, Vee =5 V, TA = 25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency Propagation delay time, low-to-high-Ievel Q' output from clear tpLH CL = 15pF, (SN54S175, SN74S175 only) RL = 280 tpHL Propagation delay time, high-to·low-Ievel Q output from clear tPLH Propagation delay time, low-to-high-Ievel output from clock n, See Note 3 tpHL Propagation time, high-to-Iow-Ievel output from clock MIN TYP 75 110 MAX UNIT MHz 10 15 ns 13 22 ns 8 11.5 12 ns 17 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-258 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54176, SN54177, SN74176, SN74177 35-MHz PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES TIL MSI BULLETIN NO. DL-S 7211478, MAY 1971-REVISED DECEMBER 1972 SN54176, SN54177 ••• J OR W PACKAGE SN74176, SN74177 ••• J OR N PACKAGE __ (TOP VI EW) Vec CLEAR 0D • Reduced-Power Versions of SN54196, SN54197, SN74196, and SN74197 50·MHz Counters • D-C Coupled Counters Designed to Replace Signetics 8280,8281,8290, and 8291 Counters in Most App Iications • Performs BCD, Bi-Quinary, or Binary Counting • Fully Programmable • Fully Independent Clear Input • Guaranteed to Count at Input Frequencies from 0 to 35 MHz • Input Clamping Diodes Simplify System Design asynchronous input: 0B CLOCK 1 Low input to clear sets 0A, 0B, 0e, and 0D low. description These high·speed monolithic counters consist of four doc coupled master-slave flip-flops which are internally interconnected to provide either a divide-by-two and a divide-by-five counter (SN54176, SN74176) or a divide-by-two and a divide-by-eight counter (SN54177, SN74177). These counters are fully programmable; that is, the outputs may be preset to any state by placing a low on the count/load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independent of the state of the clocks. These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged when the count/load is high and the clock inputs are inactive. These high-speed counters will accept count frequencies of 0 to 35 megahertz at the clock-1 input and 0 to 17.5 megahertz at the clock-2 input. During the count operation, transfer of information to the outputs occurs on the negative-going edge of the clock pulse. The counters feature a direct clear which when taken low sets all outputs low regardless of the states of the clocks. All inputs are diode-clamped to minimize transmission-line effects and simplify system design. The circuits are compatible with most TTL and DTL logic families. Typical power dissipation is 150 milliwatts. The SN54176 and SN54177 circuits are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74176 and SN74177 circuits are characterized for operation from O°C to 70°C. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-259 TYPES SN54176, SN541n, S1\I74176, SN74177 35-MHz PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES typical count configurations SN54176 and SN74176 ·SN54176, SN74176 FUNCTION TABLES The output of flip-flop A is not internally connected to the succeeding flip-flops; therefore, the count may be operated in three independent modes: DECADE (BCDI BI-OUINARY (5-21 (See Note AI 1_ When used as a binary-coded-decimal decade counter, the clock-2 input must be externally connected to the OA output_ The clock-1 input receives the incoming count, and a count sequence is obtained in accordance with the BCD count sequence function table shown at right_ COUNT 0 2_ If a symmetrical divide-by-ten count is desired for frequency synthesizers (or other applications requiring division of a binary count by a power of ten), the OD output must be externally connected to the clock-1 input_ The input count is then applied at the clock-2 input and a divide-by-ten square wave is obtained at output OA in accordance with the bi-quinary function' table. H = (See Note BI . OUTPUT 00 Oc °B °A L L L L COUNT 0 OUTPUT OA 00 Oc °B L L L L 1 L L L H 1 L L L 2 L L L 2 L L H L 3 L L H H H 3 L L H H 4 L L L 4 L H L L 5 L L H 5 H L L L 6 L H H L 6 H L L H H 7 H L H L L L H L H H L H 8 9 H H L L 7 L H H H H 8 H L 9 H L high level, L = H low level NOTES: A. Output QA connected to clock-2 Input. B. Output QO connected to clock-1 Input. 3. For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are required. Flip-flop A is used as a binary element for the divide-by-two function. The clock-2 input is used to obtain binary divide-by·five operation at the 0B, OC, and OD outputs. In this mode, the two counters operate independently; however, all four flip-flops are loaded and cleared simultaneously. SN54177, SN74177 SN54177 and SN74177 II FUNCTION TABLE (See Note AI The output of flip-flop A is not internally connected to the succeeding flip-flops, therefore the counter may be operated in two independent modes: 1. When used as a high-speed 4-bit ripple·through counter, output OA must be externally connected to the clock-2 input. The input count pulses are applied to the cI~ck-1 input. Simultaneous divisions by 2,4,8, and 16 are performed at the 0A, 0B, OC, and 0D outputs as shown in the function table at right. 2. When used as a 3-bit ripple-through counter, the input count pulses are applied to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are available at the 0B, OC, and OD outputs. Independent use of flip-flop A is available if the load and clear functions coincide with those of the 3-bit ripple-through counter. COUNT 0 OUTPUT °DOC °B OA L L L L 1 L L L 2 L L H L 3 L L H H H 4 L H L L 5 L H L H 6 L H H L 7 L H H H 8 9 H L L L H L L H 10 H L H L 11 H L H H 12 H H L L 13 H H L H 14 H H H L 15 H H H H H = high level, L = low level NOTE A: Output QA connected to clock-2 input. 1272 7·260 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54176, SN54m, SN74176, SN74177 35-MHz PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES functional block diagrams c IX> o o § § .: '" ~ d 8g C C U ~ ~ o 0 j ~ § ~ '" c IX> o 0 c 10 B II 1 I .c '" :c'" u E ,g § :! > .0 e ·1 :J .Su l 1J § ~ ~ '"U d § - U C ~ ~ < » ~ ~tW(Clearl (J1 - a z_ mA' ~8Z ~~(J1 1 ~.'~ -i .,,,,,,1OUTPUT °A I I I--th---...l\ ___.:-._ _ _ _ _ _ _ ___.. I CLOCK ENABLE TIME VOLTAGE WAVEFORMS --I 3.5V II I \ 'I 1'----'_____ I!-1- -~ I I I 1 (J1 INPUT : 1 I - - - - 3.5 V I I m >~ » c :c o :c V » -I s: o;;::: 1.5 V CLEAR AND LOAD VOLTAGE WAVEFORMS FIGURE 1 NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR .:;; 1 MHz. duty cycle':;; 50%. tr specified. tf 5 ns. When testing f max • vary PRR. B. CL includes probe and jig capacitance. C. All diodes are 1 N3064. D. Unless otherwise specified. QA is connected to clock 2. m ;;::: -I ;;::: OV OH <5 ns. and unless >m:: ~=:::t Mm .. :c "T1 --!tPHL:- o-.J m - OV cn>Z ......... ca _ r- rcn =Mcn m>Z cn e ...... s: I < s: m -I m m ' - - th ~tw(IOadl_4 1.5 V » :c » C/) I OUTPUTS 0A. 0B. OC. AND 00 :a~cn '"C COUNT/LOAD -i ~mc:n m~ .. VO" VOL z I Zcn~ ____________________________ ------oV tsu , . - - - . , ['T'J I cm~ s: \:1.5V "3:: C:acn OV 3.5 V DATA INPUTS A. B. C. AND 0 ~c: I -+j ,.... tsu 0-i ~~ I INPUT ['T'J ~ CJ : 1.5 V CLOCK-MODE VOLTAGE WAVEFORMS ,,~ g ~ M-aZ _ _ _ _ _ _ 3.5V CLOC~Kl I --VOL - >3: m :a=cn ONLY) . . . Denotes input activated bV a transition from a high level to a low level. I I schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ----4~-- Vec VC C- - - - - - - . - - - - - - INPUT OUTPUT 1272 7·266 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54178, SN54179, SN7417B, SN74179 4-81T PARALLEL-ACCESS SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage,. Vcc (see Note 1) ............ . Input voltage . . . . . . . ............ . Operating free·air temperature range: SN54178, SN54179 Circuits SN74178, SN74179 Circuits Storage temperature range 7V 5.5 V -55°C to 125°C aOc to 7aoC -65°C to 15aoC NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, Vee SN54178, SN54179 SN74178, SN74179 MIN 4.5 NOM MAX MIN NOM 5 5.5 4.75 5 -800 High·level output current, 10H low-level output current, 10l 16 0 elocl< frequency, f clock Width of clock or clear pulse, tw (see Figure 1) Setup time, tsu (see Figure 1) 25 0 20 20 Shift (H or l) or load 35 35 Data 30 30 15 15 elear-inactive-state (SN54179 and SN74179) Hold time at any input, th 5 Operating free-air temperature, T A MAX V -800 IJA 16 rnA 25 MHz ns ns 5 -55 125 UNIT 5.25 70 0 ns DC electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input vo Itage Vil low-level input voltage VIK I nput clamp voltage VOH High-level output voltage VOL Low-level output voltage II SN54178, SN54179 SN74178, SN74179 MIN MIN TYP+ MAX 2 Vee = MIN, 11=-12mA Vee = MIN, VIH=2V, Vil = 0.8 V, 10H = -800 IJA Vee - MIN, VIH = 2 V, VIL = 0.8 V, 10L= 16mA I nput current at maximum input voltage Vee - MAX, VI- 5.5 V 2.4 TYP+ MAX 2 V 0.8 0.8 V -1.5 -1.5 V 3.4 0.2 UNIT 2.4 0.4 V 3.4 0.2 0.4 1 1 V mA IIH High-level input current Vee= MAX, VI = 2.4 V 40 40 IJA IlL Low-level input current Vee - MAX, VI - 0.4 V -1.6 -1.6 mA lOS Short-circu it output current § Vee= MAX -57 mA ICC Supply current Vee = MAX, 75 mA -20 See Note 2 -57 46 70 -18 46 t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type_ +AII typical values are at Vee =5 V, T A = 25°e_ § Not more than one output should be shorted at a time. NOTE 2: lee is measured as follows: a) 4.5 V is applied to serial inputs, load, shift, and clear, b) Parallel inputs A through 0 are gounded, c) 4.5 V is momentarily applied to clock which is then grounded. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-267 TYPES SN54178, SN54179, SN74178, SN74179 4-81T PARALLEL-ACCESS SHIFT REGISTERS switching characteristics, Vee PARAMETERlI =5 V, TA =25°e FROM TO (lNPun (OUTPUT) TEST CONOITIONS f max tPLH. OD 0A, 0B, 0C, 0D Clear tpHL tPLH Clock CL=15pF, RL = 400 MIN TYP 25 39 n, See Figure 1 Any output tPHL MAX UNIT MHz 15 23 24 17 36 26 23 35 ns ns lIf max "" Maximum clock frequency tpHL"" Propagation delay time, high-to-Iow-Ievel output tpLH ""Propagation delay time, low-to-high-Ievel output PARAMETER MEASUREMENT INFORMATION OUTPUT VCC RL = 400 n FROM OUTPUT_..._ ....t--4__-I.-I.-IIN-.., UNDER TEST '1"' CL = 15 pF (See Note C) -4- LOAD CI RCUIT ~tw(clear)~ CLEAR SHIFT II LOAD ~ ,1.5V I )11.5 V .+--- I I+----!- ~1.5V I J..- : /1.5V --~If--' j...DATA (See Note B) I I I I ! tsu . tsu %,1.5V ---fl--'I CLOCK _------------------ 3 V t-- tsu _________ tsu --l (~~ ________ :~ I l\k~~!-----------3V ---t I 0V -, &.-~_l. _____ ------ 3V \"'1.5V : --l ' ~----:,~-----:-------- ..;I:' th I 1.5 V r 1.5 V ~ 1.5 V 0V tsu ,----, ---+-./ J.. tw(clock)-et ' - - - - , !.-tPHL-I Iot---...I- tPLH o OUTPUT oV I ----I--- 0 V !.-tPHL..... )c,.1-.5-V-------l-.5-V~ ~:: (See Note B) VOLTAGE WAVEFORMS NOTES: A. Input pulses are supplied by generators having the following characteristics: tTLH';; 10 ns, tTHL';; 10 ns, PRR';; 1 MHz, Zout "" 50 n. B. Data input and Q output are any related pair. Serial and other data inputs are at GND. Serial data input is tested in conjunction with Q A output in the shift mode. C. CL includes probe and jig capacitance. D. All diodes are 1 N3064. FIGURE 1-SWITCHING TIMES 1076 7·268 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54180, SN74180 9-81T ODD/EVEN PARITY GENERATORS/CHECKERS BULLETIN NO. DL-S 7211814, DECEMBER 1972 SN54180 • _. JaR W PACKAGE SN74180. _. J OR N PACKAGE (TOP VIEW) logic FUNCTION TABLE INPUTS ~ OF H's AT ATHRU H = high ~ ~ EVEN ODD EVEN H L H L ODD H L L H EVEN L H L H ODD L H H L X H H L L L H H X H OUTPUTS EVEN ODD level, L = low L level, X = irrelevant '---"--~EVEN INPUT ODD 1 EVEN r-ODD INPUT OUTPUT OUTPUT ----v---INPUTS positive logic: see function table description These universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generators/checkers, utilize familiar Series 54/74 TTL circuitry and feature odd/even outputs and control inputs to facilitate operation in either odd- or even-parity applications. Depending on whether even or odd parity is being generated or checked, the even or odd inputs can be utilized as the parity or 9th-bit input. The word-length capability is easily expanded by cascading. The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level to facilitate the connection of unused inputs to used inputs. Typical power dissipation is 170 mW. The SN54180 is characterized for operation over the full military temperature range of _55°C to 125°C; and the SN74180 is characterized for operation from O°C to 70°C. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V Supply voltage, VCC (see Note 1) ....... . Input voltage . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54180 Circuits SN74180 Circuits Storage temperature range 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54180 MIN 4.5 Supply voltage, Vee NOM 5 SN74180 MAX MIN 5.5 4.75 -800 High-level output current, IOH 16 Low-level output current, IOL -55 Operating free-air temperature, T A 125 0 NOM 5 MAX UNIT 5.25 V -800 IlA 16 rnA 70 °e 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·269 TYPES SN54180, SN74180 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH VOL SN54180 MIN TYPt SN74180 MAX 2 High-level output voltage Low·level output voltage II Input current at maximum input voltage IIH High-level input current Any data input Even or odd input Vee = MIN, 11=-12mA Vee - MIN, VIH = 2V, VIL = 0.8 V, 10H = -8001lA Vee- MIN, VIH = 2 V, VIL = 0.8 V, 10L = 16mA Vee = MAX, VI = 5.5V Vee = MAX, VI = 2.4 V Any data input IlL Low·level input current lOS Short·circuit output current § lee Supply current Even or odd input VI Vee = MAX, = MAX Vee = MAX, 2.4 MIN TYPt 0.2 V 0.8 V -1.5 -1.5 V 2.4 0.4 3.3 0.2 See Note 2 0.4 1 1 40 80 80 -1.6 -1.6 -55 34 V 40 -3.2 -20 UNIT 0.8 3.3 = 0.4 V Vee MAX 2 -3.2 -18 49 34 V mA IlA mA -55 mA 56 mA NOTE 2: ICC is measured with even and odd inputs at 4.5 V, all other inputs and outputs open. tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. :j:AII typical values are at Vee = 5 V, T A = 25°C. §Not more than one output should be shorted at a time. switching characteristics, Vee PARAMETER~ tpLH = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Data ~ Data L Odd TEST CONDITIONS Even eL=15pF, tpHL tpLH Odd input grounded, See Note 3 TYP MAX UNIT 40 60 45 68 32 48 tpHL 25 38 tpLH 32 48 25 38 Data LEven Data L Odd eL=15pF, tpHL tpLH II RL=400n, MIN RL=400n, Even input grounded, See Note 3 tpHL tpLH Even or Odd L Even or L Odd tpHL CL = 15 pF, See Note 3 RL = 400 n, 40 60 45 68 13 20 7 10 ns ns ns ns ns NOTE 3: Load circuits and waveforms are shown on page 3-10. ~ tp LH == Propagation delay time, low-to-high-Ievel output tPH-L,== Propagation delay time, high-to-Iow-Ievel output functional block diagram and schematics of inputs and outputs TYPICAL OF BOTH OUTPUTS EQUIVALENT OF EACH INPUT VCC3-Req INPUT -- Data inputs: Req = 4 k.fl. Even and odd: Req = 2 kn 1076 7-270 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS, TEXAS 75222 TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS TTL MSI BULLETIN NO. DL-S 7611B31, DECEMBER 1972 - REVISED OCTOBER 1976 SN54181, SN54LS181, SN54S181 '" J OR W PACKAGE SN74181, SN74LS181, SN74S181 •• , J OR N PACKAGE (TOP VIEW) • Full Look-Ahead for High-Speed Operations on Long Words • Input Clamping Diodes Minimize Transmission-Line Effects • Darlington Outputs Reduce Turn-Off Time • Arithmetic Operating Modes: Addition Subtraction Shift Operand A One Position Magnitude Comparison Plus Twelve Other Arithmetic Operations • Logic Function Modes: Exclusive-OR Comparator AND, NAND, OR, NOR Plus Ten Other Logic Operations logic: see tables 1 and 2 TYPICAL ADDITION TIMES PACKAGE COUNT ADDITION TIMES NUMBER CARRY METHOD OF USING '181 USING'LS181 USING'S181 ARITHMETICI LOOK-AHEAD BITS AND '182 AND '182 AND'S182 LOGIC UNITS CARRY GENERATORS BETWEEN 1 to 4 24 ns 24 ns 11 ns 1 NONE 5 to 8 36 ns 40ns 18 ns 2 RIPPLE 9 to 16 36ns 44 ns 19 ns 30r4 1 FULL LOOK-AHEAD 17 to 64 60 ns 68 ns 28 ns 5 to 16 2 to 5 FULL LOOK-AHEAD ALU's I I description I The '181, 'LS181, and 'S181 are arithmetic logic units (ALU)/function generators that have a complexity of 75 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select lines (SO, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in conjunction with the SN54182, SN54S182, SN74182, or SN74S182, full carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown above illustrate the little additional time required for addition of longer wprds when full carry look-ahead is employed. The method of cascading '182 or 'S182 circuits with these ALU's to provide multi-level full carry look-ahead is illustrated under typical applications data for the '182 and'S182. If high speed is not of importance, a ripple-carry input (C n ) and a ripple-carry output (C n +4) are available. However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without external circu itry. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-271 TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS description (continued) The '181, 'LS181, and 'S181 will accommodate active-high or active-low data if the pin designations are interpreted as follows: 1 l l PIN NUMBER 2 Active-low data (Table 1) AO Active-high data (Table 2) AO 1 BO BO 23 Al Al 22 Bl Bl 21 A2 A2 20 B2 B2 19 A3 A3 18 B3 B3 9 Fa Fa 101111131 7 J 16 115117J F 1 1 F2 11=3 1Cn 1Cn+4 1 PIG 1 Fl 1 F2 1 F3 1 Cn 1 Cn+41 X 1 Y J Subtraction is accomplished by 1's complement addition where the 1's complement of the subtrahend is generated internally. The resultant output is A-B-l, which requires an end-around or forced carry to provide A-B. The '181, 'LS181, or 'S181 can also be utilized as a comparator. The A = B output is internally decoded from the function outputs (Fa, Fl, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicate equality (A = B). The ALU should be in the subtract mode with C n = H when performing this comparison. The A = B output is open-collector so that is can be wire-AND connected to give a comparison for more than four bits. The carry output (C n +4) can also be used to supply relative magnitude information. Again, the ALU should be placed in the subtract mode by placing the function select inputs S3, S2, Sl, SO at L, H, H, L, respectively. INPUT Cn OUTPUT Cn +4 ACTIVE-LOW DATA ACTIVE·HIGH DATA (FIGURE 1) (FIGURE 2) H H A;;.B A<:;;B H L AB L H A>B A---Vcc A= B OUTPUT • I INPUT L--_~- Mode control: Req Any A or S: Req Any S: Req Cn: Req OUTPUT = 4 kn NOM = 2 kn NOM = 1.3 kn NOM = 1 kn NOM 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·275 TYPES SN54LS181, SN74LS181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature range: SN54LS181 SN74LS181 . . . . . . Storage temperature range NOTES: 7V . . . . 5.5 V . . . . 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each A input in conjunction with inputs S2 or S3, and to each B input in conjunction with inputs SO or S3. recommended operating conditions SN54LS181 SN74LS181 UNIT MIN Supply voltage, Vee NOM 4.5 5 MAX MIN NOM 5.5 4.75 5 -400 High-level output current, IOH (All outputs except A = B) I Low-level output current, IOL MAX 5.25 pA B mA 70 °e 4 Operating free-air temperature, T A -55 125 V -400 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage Low-level input voltage VIK I nput clamp voltage Vee= MIN, 11--1BmA High-level output voltage, Vee= MIN, VIH=2V, any output except A = B VIL = VIL max, IOH = -400 pA High-level output current, Vee = MIN, A = B output only VIL = VIL max, VOH = 5.5 V 10H low-level II MIN VIL VOH Val output voltage II 2.5 TYP:j: V O.B V -1.5 -1.5 V 3.4 0.25 2.7 3.4 Vil = Vil max V 100 0.4 10l = BmA Output p- 0.25 0.4 0.35 0.5 10l = 16 mA 0.47 0.7 0.47 0.7 Ial = BmA 0.35 0.6 0.35 0.5 Mode input 0.1 Any A or B input 0.3 0.3 max. input Any S input 0.4 0.4 voltage earry input 0.5 0.5 input low-level input current Vee= MAX, VI = 5.5V Mode input 20 20 60 60 Any S input Vee = MAX, VI = 2.7 V 80 BO 100 100 Mode input -0.4 -0.4 Any A or B input -1.2 -1.2 -1.6 -1.6 -2 -2 Any S input Vee = MAX, VI=O.4V earry input /J.A V 0.1 Any A or B input earry input UNIT 0.7 100 VIH = 2 V, MAX 2 VIH-2V, IOl=4mA Vee = MIN, MIN Input current III SN74LS181 MAX current at High-level IIH TYP:j: 2 All outputs Output G SN54LS181 TEST eONDITIONSt PARAMETER mA /J.A mA Short-circuit output current, lOS ICC any output except A = B § Supply current -6 VCC= MAX VCC= MAX, See Note 3 -40 -5 -42 Condition A 20 32 20 34 Condition B 21 35 21 37 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°C. §Not more than one output should be shorted at a time. NOTE 3: With outputs open, ICC is measured for the following conditions: A. SO through S3, M, and A inputs are at 4.5 V, all other inputs are grounded. B. SO through S3 and M are at 4.5 V, all other inputs are grounded. 1076 7-276 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS181, SN74LS181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS REVISED OCTOBER 1976 = 5 V, TA = 25°C, switching characteristics, VCC PARAMETERl1 FROM TO (INPUT) (OUTPUT) Cn Cn +4 tpLH tpHL tpLH tPHL tPLH Any tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH TYP MAX UNIT 18 27 13 20 v, so = S3 = 4.5 V, 25 38 25 38 27 41 B Cn +4 S1 = S2 = 4.5 V (DIFF mode) 27 41 M=OV 17 26 (SUM or DIFF mode) 13 20 so = S3 = 4.5 V, 19 29 S1 = S2 = 0 V (SUM model 15 23 21 32 21 32 Any A or M - 0 V, en AnyF Any A or B G Any A or B G Any A or B P Any A orB Ajor Bj P Fj AjorBj Fj AjorBj Fj tpHL tpLH MIN S1 = S2 = 0 V (SUM mode) tpHL tpLH TEST CONDITIONS M=0 tpHL tPLH see note 4) Cn +4 tpHL tpLH = 15 pF, RL = 2 kn, A or B tpHL tpLH (CL Any A or B A=B tpHL M = 0 V, M = 0 V, so = S3 - -- 0 V so - S3 = 0 V, S1 = S2 = 4.5 V M = 0 V, (5i"FF mode) so = S3 = 4.5 V, S1 = S2 = 0 V, (SUM mode) M = 0 V, so = S3 = 0 V, 20 30 20 30 20 30 S1 = S2 = 4.5 V (DIFF mode) 22 33 M - 0 V, SO - S3 - 4.5 V, 21 32 S1 = S2 = 0 V (SUM mode) 13 20 M = 0 V, SO = S3 = 0 V, 21 32 S1 = S2 = 4.5 V (DIFF model 21 32 M = 4.5 V (logjc model M - 0 V, so - S3 - S1 = S2 = 4.5 V 0 V. (i5'iFF mode) 22 33 26 38 33 50 41 62 ns ns ns ns ns ns ns ns ns ns ns ns 11 tpLH = propagation delay time, low-to·hlgh-Ievel output tPHL == propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. • schematics of inputs and outputs EQUIVALENT OF EACH INPUT Vcc - - - . - - - A= B OUTPUT TYPICAL OF ALL OUTPUTS EXCEPT A = B I ----~,...--Vcc Vcc INPUT L -____~- Mode control: Any A or B: Any S: cn: OUTPUT OUTPUT Req = 17 kn NOM Req = 5.67 kn NOM Req = 4.25 kn NOM Req = 2.86 kn NOM 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-277 TYPES SN54S181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature: SN54S181 SN74S181 Storage temperature range NOTES: 7V 5.5 V 5.5 V _55°C to 125°C aOe to 7aoe -65°C to 15aoe 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2_ This is the voltage between two emitters of a multiple-emitter transistor. For this circuit. this rating applies to each conjunction with inputs S2 or S3, and to each B input in conjunction with inputs SO or S3. A input in recommended operating conditions SN54S181 MIN 4.5 Supply voltage, Vee NOM 5 SN74S181 MAX MIN 5.5 4.75 MAX NOM 5 -1 High-level output current, 10H (All outputs except A = B) Low-level output current, 10L 20 Operating free-air temperature, T A -55 125 0 UNIT 5.25 V -1 rnA 20 rnA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage Vee= MIN, 11=-1SmA VIH - 2 V, VOH 10H • High-level output voltage, Vee - MIN, VIL = O.S V, 10H =-1 rnA High-level output current, Vee = MIN, VIH = 2V, A = B output only VIL = O.S V, VOH = 5.5 V Vee= MIN, VIH=2V, VIL = O.S V, 10L = 20mA II Vee = MAX, VI = 5.5 V Vee= MAX, VI = 2.5 V Input current at maximum input voltage High-level IIH input current - Low-level IlL input current SN74S181 MAX MIN 2.5 TYP+ MAX 2 V O.S V -1.2 -1.2 V 3.4 2.7 3.4 V 250 250 J.LA 0.5 0.5 V 1 1 50 50 150 200 200 earry input 250 250 Mode input -2 -2 -6 -6 -S -S Any S input Any A or B input Any S input VJ=0.5V Vee = MAX, earry input any output except A = B § -10 I Vee = MAX Supply current -40 ~ TA = 125°e, I See Note 3 I All packages See Note 3 Vee - MAX, -100 195 120 220 rnA J.LA rnA -10 -100 --40 W package only UNIT O.S 150 Vee = MAX, ICC TYP+ Mode input Any A or B input Short-circuit output current, lOS MIN 2 any output except A = B VOL Low-level output voltage SN54S181 TEST eONDITIONst rnA rnA 120 220 t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time. NOTE 3: ICC is measured for the following conditions (the typical and maximum values apply to both): A. SO through S3, M, and A inputs are at 4.5 V. all other inputs are grounded, and all outputs are open. B. SO through S3 and M are at 4.5 V. all other inputs grounded. and all outputs are open. 1076 7-278 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS switching characteristics, VCC :::: 5 V, T A:::: 25°C (CL :::: 15 pF, RL :::: 280 PARAMETER~ FROM (INPUT) tPLH Cn tpHL tPLH Any tpHL tpLH A orB Any A orB tPLH Any A or tpHL tpLH Any tpHL tPLH B A orB l' AiorBi Fj AjorBj Fj tpLH tpHL tpLH Aj OrBj Fj ~ tpLH tpH L 18.5 23 S1 = S2 = 4.5 V (DIFF mode) 15.5 23 = OV 7 12 (SUM or DIFF mode) 7 12 = 0 V, so = S3 = 4.5 V, = S2 = 0 V (SUM mode) 8 12 7.5 12 M - 0 V, S1 so = S3 = 0 = S2 = 4.5 V M - 0 V, S1 so - = S2 = 0 M - 0 V, Any A orB A=B V, (DIFF mode) S3 - 4.5 V, V (SUM mode) so - S3 - 0 V, S1 = S2 = 4.5 V (DIFF mode) M = 0 V, SO S1 S1 = S2 = S3 = 4.5 V, = 0 V (SUM mode) = S3 = 0 = S2 = 4.5 V M = 4.5 V, (DIFF mode) V (logic mode) M = 0 V, S1 = S2 tpHL 10.5 15.5 V (SUM mode) M = 0 V, SO tPLH tpHL 10.5 7 M-OV,SO=S3=OV, S1 tpHL MAX UNIT 7 18.5 M G 4.5 V, TYP 12.5 =0 M G Any A orB tpHL tpLH MIN 12.5 F - P v, so = S3 - S1 = S2 C n +4 Any A orB tpHL tpLH M - 0 C n+4 Any Cn tpLH TEST CONDITIONS C n +4 tpHL tpHL TO (OUTPUT) n, see note 4) so = S3 = 0 = 4.5 V, V (DIFF mode) 10.5 15 10.5 15 7.5 12 7.5 12 10.5 15 10.5 15 11 16.5 11 16.5 14 20 14 22 14 20 14 22 15 23 20 30 ns ns ns ns ns ns ns ns ns ns ns ns == propagation delay time, low-to-high-Ievel output == propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-10. • schematics of inputs and outputs EQUIVALENT OF EACH INPUT Vee - - - . - - - TYPICAL OF ALL OUTPUTS EXCEPT A = B - - - - - - - . - - Vee A= B OUTPUT I Vee OUTPUT INPUT ' - - -......- - OUTPUT Mode control: Req Any A or B: Req Any S: Req en: Req = 2.8 k11 NOM = 940 11 NOM = 700 11 NOM 11 NOM = 560 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-279 TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS functional block diagram ~~ S3 (3) S2 (4) S1 (5) SO~ 83 or B3 ~ ~ (19) A30r A3 ~~~ .....,~ ~ r~~ H> ~~ II • (22) H> (16) ./ (15) P orX (13) F3 or F3 ~~ I (21) A2 or A2 81 or B1 - GorY ,........" J~./ " (20) 82 or B2~--< (17) " ./ ~v I :~ (11) F2 or F2 (14) A=B (23) A10rA 1 11 ) (1) 60 or Bu, - >-<{) ~ ~ I AOorAO M :~ " .~ (2) (10) (9) F1 or F1 o or FO ~~ (8) (7) n 1076 7·280 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS PARAMETER MEASUREMENT INFORMATION SUM MODE TEST TABLE FUNCTION INPUTS: SO = S3 = 4.5 V. S1 = S2 INPUT PARAMETER OTHER INPUT =M =0 V OUTPUT SAME BIT UNDER r-:A-P"":PL"'-y"'T-=A"'-P'"="P:-CLyc:--1r-A-:PC::P:-C L y-,--,-----:-A-=-=PPC":"L-y-f UN DE R TEST TEST 4.5 V GND 4.5 V GND Bi Ai None OTHER DATA INPUTS Remaining Bi None None None None None Bi Ai Ai None Bi Ai Bi None Ai None None None None Ai Fi Aand B Remaining Remaining B A,C n Remaining In-Phase All Any F or C n +4 A B Remaining Remaining B A,C n Remaining Remaining None Ai Bi Ai None Bi Ai Out-at-Phase B =M =0 V OTHER DATA INPUTS Remaining Remaining Remaining Remaining None Bi Ai None None Bi None None None Ai None None Bi Ai None None None Bi Bi None In·Phase Remaining Out·ol·Phase A andB, Cn Remaining In-Phase A andB,C n Out·ol·Phase A andB, Cn B,C n Remaining A All AandS None None None None None • I Remaining Remaining (See Note 41 Out-cf·Phase AandS,C n Ii: OUTPUT WAVEFORM In-Phase B,C n Remaining Remaining Remaining In·Phase Out·ol·Phase OUTPUT SAME BIT UNDER I - - - - - . r - - - t - - - - - - r - - - - - i UNDER APPLY APPLY APPLY APPLY TEST TEST 4.5 V GND 4.5 V GND INPUT PARAMETER In-Phase B All DIFF MODE TEST TABLE FUNCTION INPUTS: S1 = S2 = 4.5 V. SO = S3 OTHER INPUT In-Phase AandS,C n Remaining In-Phase In·Phase A and B, Cn Remaining Remaining (See Note 41 In-Phase AandB Remaining Ai OUTPUT WAVEFORM A = B In-Phase A=B Out·ol Phase Cn +4 orany F Remaining A,S,C n Remaining In·Phase Out-ot-Phase In -Phase A,B,C n LOGIC MODE TEST TABLE FUNCTION INPUTS: S1 = S2 = M = 4.5 V. SO = S3 = 0 V OTHER INPUT INPUT PARAMETER UNDER TEST OTHER DATA INPUTS OUTPUT SAME BIT f-,A:-::P-=-P:'-:Ly-:-T---:-Ap::":P"-L""'Y-+-AP=-=P-'-L::-:Cy-'--A-"P=CpL-:-y,..-l UNDE R TEST 4.5 V GND 4.5 V GND Ai tpHL Ai None None None None Remaining A andB,C n Remaining A and B, Cn OUTPUT WAVE FO RM (See Note 41 Ou toot-Phase Out-af-Phase NOTE 4: Load circuit and voltage waveforms are shown on pages 3-10 and 3-11. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-281 TYPES SN54182, SN54S182, SN74182, SN74S182 LOOK-AHEAD CARRY GENERATORS TTL MSI BULLETIN NO. DL-S 7611823, DECEMBER 1972-REVISED OCTOBER 1976 • Directly Compatible for Use With: SN54181/SN74181, SN54LS181/SN74LS181, SN54S281/SN74S281, SN54S381, SN74S381, SN54S481/SN74S481 SN54182, SN54S182 ••• J OR W PACKAGE SN74182, SN74S182 ••• J OR N PACKAGE (TOP VIEW) PIN DESIGNATIONS ALTERNATIVE DESIGNATIONSt PIN NOS. FUNCTION GO, G1, G2, G3 GO, Gl, G2, G3 3,1,14,5 CARRY GENERATE INPUTS PO,Pl,P2,P3 PO, PI, P2, P3 4,2,15,6 CARRY PROPAGATE INPUTS Cn Cn 13 CARRY INPUT Cn + x , Cn+y , Cn+x,C n +y , C n +z Cn+z 12,11,9 CARRY OUTPUTS G Y 10 CARRY GENERATE OUTPUT P X 7 CARRY PROPAGATE OUTPUT 16 SUPPLY VOLTAGE 8 GROUND VCC GND logic: see description and function tables t Interpretations are illustrated on page 7-273 description The SN54182, SN54S182, SN74182, and SN74S182 are high·speed,look·ahead carry generators capable of anticipating a carry across four binary adders or group of adders. They are cascadable to perform full look-ahead across n-bit adders. Carry, generate·carry, and propagate-carry functions are provided as enumerated in the pin designation table above. When used in conjunction with the '181, 'LS181, or 'S181 arithmetic logic unit (ALU), these generators provide high·speed carry look-ahead capability for any word length. Each '182 or 'S182 generates the look-ahead (anticipated carry) across a group of four ALU's and, in addition, other carry look-ahead circuits may be employed to anticipate carry across sections of four look-ahead packages up to n-bits. The method of cascading '182 or 'S182 circuits to perform multi-level look-ahead is illustrated under typical application data. • The carry functions (inputs, outputs, generate, and propagate) of the look-ahead generators are implemented in the compatible forms for direct connection to the ALU. Reinterpretations of carry functions as explained on the '181, 'LS181, and 'S181 data sheet are also applicable to and compatible with the look-ahead generator. Logic equations for the '182 and 'S182 are: C n+x = GO + PO Cn C n+y = Gl + Pl GO + Pl PO Cn Cn+z = G2 + P2 Gl + P2 Pl GO + P2 P1 PO C n G = G3 + P3 G2 + P3 P2 Gl + P3 P2 Pl GO P = P3 P2 Pl PO or Cn +x = YO (XO + Cn) Cn +y = Yl [Xl + YO (XO + Cn)] Cn +z = Y2 {X2 + Y1 [Xl + YO (XO + Cn)]} Y = Y3 (X3 + Y2) (X3 + X2 + Yll (X3 + X2 + Xl + YO) X = X3 + X2 + Xl + XO logic FUNCTION TABLE FOR G OUTPUT INPUTS FUNCTION TABLE FOR OUTPUT P OUTPUT G3 G2 G1 GO P3 P2 P1 G L X X X X X X L P3 P2 P1 PO X L X X L X X L L L L L X X L X L L X L All other X X X L L L L L combinations All other combinations INPUTS OUTPUT P L H H H = high level, L = low level, X = irrelevant Any inputs not shown in a given table are irrelevant with respect to that output. 1076 7-282 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54182, SN54S182, SN74182, SN74S182 LOOK-AHEAD CARRY GENERATORS logic functional block diagram FUNCTION TABLE FOR C n+x OUTPUT INPUTS OUTPUT GO PO Cn Cn+x L X X H X L H H All other L combinations - (6) ~30rX3~(5~)~~~~-+~~ G30rY3~~-+~--~-+~~~ FUNCTION TABLE FOR Cn+y OUTPUT INPUTS G1 OUTPUT X X PO Cn X X X L L X X H X X L L H H L GO P1 Cn+y H All other P2orX27(1~5~)+-~--~r1-+~ ... ~ L combinations G2orY2~(1~4~)+-~--~~-+~ FUNCTION TABLE FOR C n+z OUTPUT INPUTS OUTPUT G2 G1 GO P2 P1 PO Cn L X X X X X X Cn+z H X L X L X X X H X X L L L X X H X X X L L L H H All other combinations - (2) ~1orX17(1~)-+~--~-+--~~~ G1orY1~~----~~--~ • L H = high level, L = low level, X = irrelevant Any inputs not shown in a given table are irrelevant with respect.to that output. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free·air temperature range: SN54', SN54S' Circuits. SN74', SN74S' Circuits. Storage temperature range NOTES: 7V 5.5 V . . . . 5.5 V -55°C to 125°C . oOe to 70°C -65°C to 150°C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter input transistor. For these circuits, this rating applies to each input in conjunction with any other G input or in conjunction with any P input. G 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-283 • TYPES SN54182, SN74182 LOOK-AHEAD CARRY GENERATORS recommended operating conditions SN74182 SN54182 MIN Supply voltage, Vee 4.5 NOM 5 High·level output current, 10H MAX MIN 5.5 4.75 NOM 5 -SOO Low-level output current, 10L MAX 5.25 V -SOO /-IA 16 rnA 70 °e 16 Operating free-air temperature, T A -55 125 UNIT 0 electrical characteristics over recommended operating free·air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH TYPt High-level output voltage Low-level output voltage II Input current at maximum input voltage Vee- MIN, 11- -12mA Vee = MIN, VIH =2V, VIL = O.SV, 10H = -Soo/-lA Vee= MIN, VIH = 2 V, VIL=O.SV, IOL=16mA 2.4 TYPt MAX V O.S V -1.5 -1.5 V 2.4 0.2 3.4 0.2 0.4 1 Vee= MAX, VI = 5.5V V 0.4 1 en input SO SO 'P3 input 120 120 High-level P2 input input current 'PO, P1, or G3 input Vee=MAX, VI=2.4V 160 160 200 200 360 360 01 input 400 400 en input -3.2 -3.2 P3 input -4.S -4.S Low-level P2 input -6.4 -6.4 input current "'PO, P1, or G3 input Vee= MAX, VI = 0.4 V -S -8 -14.4 -14.4 -16 G1 input Short-circuit output current§ -40 Vee= MAX leeH Supply current, all outputs high leeL Supply current, all outputs low 27 Vee- MAX, See Note 4 45 V rnA I-IA rnA -16 -100 See Note 3 Vee = 5V, UNIT O.S 3.4 GO or G2 input lOS MIN 2 GO or G2 input IlL SN74182 MAX 2 VOL IIH SN54182 MIN -40 -100 rnA 72 rnA 27 65 45 rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at V CC = 5 V, T A = 25° C. §Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second. NOTES: 3. ICCH is measured with all outputs open, inputs P3 and G3 at 4.5 V. and all other inputs grounded. 4. ICCL is measured with all outputs open; inputs GO, G1, and G2 at 4.5 V; and all other inputs grounded. switching characteristics, Vee I I I =5 V, TA = 25°e I PARAMETER tpLH Propagation delay time, low-to-high-Ievel output tpHL Propagation delay time, high-to-Iow-Ievel output I I TEST CONDITIONS eL = 15pF, RL =400 MIN n, See Note 5 TYP MAX UNIT 11 17 ns 15 22 ns I I I NOTE 5: Load circuit and voltage waveforms are shown on page 3.10. \ 1076 7·284 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S182, SN74S182 LOOK-AHEAD CARRY GENERATORS recommended operating conditions MIN Supply voltage, VCC 4.5 SN54S182 NOM MAX 5 5.5 -1 High-level output current, 10H Low-level output current, 10L MIN SN74S182 UNIT NOM MAX 5 4.75 5.25 V -1 mA 20 mA °c 20 Operating free-air temperature, T A -55 125 0 70 electrical characteristics over rec,ommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage IIH IlL SN54S182 TEST CONDITIONSt MIN TYP+ SN74S182 MAX 2 VCC = MIN, 11=-lSmA VCC- MIN, VIH = 2V, VIL =O.SV, 10H=-1 mA VCC- MIN, VIH=2V, VIL = O.S V, 10L = 20mA 2.5 MIN TYP+ MAX V 2 O.S O.S V -1.2 -1.2 V 3.4 2.7 VCC - MAX, VI-5.5V 3.4 V 0.5 0.5 1 1 C n input 50 50 P3 input 100 100 l:Iigh-level P2 input input current PO, Pl, or G3 input 150 150 200 200 GO or G2 input 350 350 Gl input 400 400 Cn input -2 -2 1>3 input -4 -4 -6 -6 Low-level P2 input input current PO, Pl, or G3 input VCC = MAX, VI = 2.7 V VCC= MAX, VI = 0.5V GO or G2 input Gl input -S -S -14 -14 -16 VCC = MAX VCC- 5V, Short·circuit output current § ICCH Supply current, all outputs high ICCL Supply current, all outputs low lOS -40 See Note 3 -100 35 69 VCC - MAX, See Note 4 UNIT V mA /lA mA -16 -40 -100 35 99 69 mA mA 109 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. • +AII typical values are at V CC = 5 V, T A = 25°C. _ § Not more than one output shouldbe shorted at a time and duration of the short-circuit test should not exceed one second. NOTES: 3. ICCH is measured with all outputs open, inputs P3 and 03 at 4.5 V, and all other inputs grounded. 4. leCL is measured with ;III outputs open; inputs GO, G1, and G2 at 4.5 V; and all other inputs grounded. switching characteristics, Vee PARAMETER~ = 5 V, TA = 25°e FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH tpHL GO, Gl, G2, G3, C n +x , Cn+y, 4.5 PO, Pl, P2, or P3 or C n +z 4.5 7 tpLH GO, Gl, G2, n3, 5 7.5 tpHL Pl, P2, or P3 7 10.5 4.5 6.5 6.5 10 6.5 10 7 10.5 tpLH tpHL tpLH tpHL PO, Pl, P2, or P3 Cn G RL = 2S0 n, CL=15pF, See Note 5 P Cn +x , C n +y , or C n+z 7 ns ns ns ns ~tpLH == propagation delay time, low-to-high-Ievel output tpH L == propagation delay time, high-to-Iow-Ievel output NOTE 5: Load circuit and voltage waveforms are shown on page 3-10: 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-285 TYPES SN54182, SN54S182, SN74182, SN74S182 LOOK-AHEAD CARRY GENERATORS schematics of inputs and outputs '182 TYPICAL OF ALL OUTPUTS EaUIVALENT OF EACH INPUT ---------------~--VCC vcc---------e--------- 58 n NOM INPUT Cn 15"3 152 PO,1S1,cb 130,134 01 INPUT Req NOM 2.8 kn 1.4 kn 940 n 700 n 400 n 350 n OUTPUT 'S182 EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS ---------------~--VCC 50 n NOM VCC--------~~------- INPUT • INPUT Req NOM Cn P3 P2 PO, P1, (33 GO, 04 131 2.8 kn 1.4 kn 940 n 700 n 400 n 350 n ' - - -.....-OUTPUT TYPICAL APPLICATION DATA 64-BIT ALU, FULL-CARRY LOOK-AHEAD IN THREE LEVELS Remaining inputs and outputs of '181, 'LS181, 'S181 'S281 , 'S381, and 'S481 are not shown. 877 7·286 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54H183, SN54LS183, SN74H183, SN74LS183 DUAL CARRY-SAVE FULL ADDERS TTL MSI BULLETIN NO. DL-S 77118 OCTOBER 1976-REVISED AUGUST 1977 SN54H183, SN54LS183 •. ,J OR W PACKAGE SN74H183, SN74LS183 . , . J OR N PACKAGE (TOP VIEW) o For Use in High-Speed Wallace-Tree Summing Networks • High-Speed, High-Fan-Out Darlington Outputs OUTPUT ~---''-----.. o Input Clamping Diodes Simplify System Design TYPICAL AVERAGE PROPAGATION DELAY TIME TYPICAL POWER DISSIPATION 'H183 11 ns 110 mW per bit 'LS183 15 ns 23 mWper bit TYPES ~~GND functional block diagram (each adder) INPUTS OUTPUTS positive logic: see function table c n (4,11) NC-No internal connection FUNCTION TABLE (EACH ADDER) (3,12) INPUTS Cn L A (1,13) H A 1:: L L L Cn +1 L L L H H L L H L H L L H H L H H L L H L H L H L H H H L L H H H H H H = high schematics of inputs and outputs 'H183 EaUIVALENT OF EACH INPUT VCC -NOM o k n -INPUT level, L = low OUTPUTS VCC 58n --~VCC NOM o INPUT OUTPUT 6 kn • level ,I 'LS183 EaUIVALENT OF EACH INPUT TYPICAL OF ALL __ OUTPUTS B TYPICAL OF ALL OUTPUTS NOM -- description These dual full adders feature an individual carry output from each bit for use in multiple·input, carry-save techniques to produce the true sum and true carry outputs with no more than two gate delays. The circuits utilize high-speed, high·fan-out, transistor-transistor logic (TTL), but are compatible with both DTL and TTL families. Series 54H and 54LS devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74H and 74LS devices are characterized for operation from oOe to 70°C. 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·287 TYPES SN54H183, SN74H183 DUAL CARRY-SAVE FULL ADDERS REVISED AUGUST 1977 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Vcc (see Note 1) Input voltage. . . . . . . . Interemitter voltage (see Note 2) Operating free·air temperature range: SN54H183 Circuits SN74H183 Circuits Storage temperature range NOTES: 7V 5.5V 5.5V -55°C to 125°C O°C to 70°C -65°C to 150°C 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters bf a multiple·emitter transistor. For this circuit, this rating applies between any two inputs to the same adder. recommended operating conditions SN54H183 MIN Supply voltage, Vee NOM 4.5 SN74H183 MAX MIN 5.5 4.75 5 High·level output current, IOH NOM 5 -1 Low-level output current, IOL 20 Operating free-air temperature, T A -55 125 0 MAX UNIT 5.25 V -1 mA 20 mA °e 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High·level output voltage VOL • TEST CONDITIONSt MIN TVPt MAX UNIT 2 Vee~ Vee VIL Low-level output voltage ~ ~ ~ MIN, II MIN, VIH = 2V, 0.8 V, V -8 mA IOH =-1 mA Vee = MIN, VIH =2 V, VIL = 0.8 V, IOL ~ 2.4 V -1.5 V 3.5 0.2 20mA 0.8 V 0.4 V II Input current at maximum input voltage Vee~ MAX, VI ~ 5.5V 1 mA IIH High-level input current Vee~ MAX, VI ~ 2.4 V 150 IlL Low-level input current Vee~ MAX, VI ~ 0.4 V -6 /JA mA lOS Short-circuit output current§ Vee~ MAX -100 mA -40 I leeL Supply current, all outputs low leeH Supply current, all outputs high 69 Vee = MAX, SN54H183 48 See Note 3 ISN74H183 48 75 See Note 4 40 65 Vee = MAX, mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. tAlI typical values are at V CC ~ 5 V, T A ~ 25° C. §Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. NOTES: 3. 'CCL is measured with a" outputs open and a" inputs grounded. 4. ICCH is measured with all outputs open and all inputs at 4,5 V. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER tPLH TEST CONDITIONS Propagation delay time, low-to-high-Ievel output eL tpHL Propagation delay time, high-to-Iow-Ievel output ~ 25pF, See Note 5 RL = 280n, MIN TVP MAX 10 15 12 18 NOTE 5: Load circuit and waveforms are shown on page 3.10. 877 7-288 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS183, SN14LS183 DUAL CARRY-SAVE FULL ADDERS REVISED AUGUST 1977 absolute maximum ratings over operating free-air temperature range (unleu otherwise noted) Supply voltage VCC (see Note 1) Input voltage . Operating free-air temperature range: SN54LS183 Circuits SN74LS183 Circuits Storage temperature range : . 7V . 7V -55°C to 125°C . . aOc to 7aoC -65°C to 15aoC NOTE 1: Voltage values, except interemltter voltage, are with respect to network ground terminal. recommended operating conditions SN54LS183 MIN 4.5 Supply voltage, VCC NOM 5 High-level output current, 10H MAX 5.5 -400 SN74LS183 UNIT MIN NOM MAX 4.75 5 4 Low-level output current, 10L Operating free-air temperature, T A -55 5.25 -400 8 125 70 0 V J.lA mA °c electrical characteristics over recommended operation free·air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH TEST eONDITloNst TVPt MAX 2 High-level output voltage Vee - MIN, 11- -18 mA Vce = MIN, VIH = 2 V, VIL = VILmax, 10H = -400J.lA Vee - MIN, VOL MIN Low-level output voltage 2.5 TVPt MAX 2 UNIT V 0_7 0.8 V -1.5 -1.5 V 3.4 2.7 0.25 IIOL =4 mA MIN 0.4 3.4 V 0.25 0.4 0.35 0.5 V VIH = 2 V, VIL = VILrnax, IIOL = 8 mA II Input current}}t maximum input voltage Vee = MAX, VI =7 V 0.3 0.3 mA IIH High-level input current Vee = MAX, VI =2.7 V 60 IlL Low-level input current Vee - MAX, VI - 0.4 V -1.2 60 -1.2 J.lA mA lOS Short-circuit output current§ Vee = MAX -100 mA leeL Supply current, all outputs low Vee - MAX, See Note 3 10 17 10 17 mA ICCH Supply current, all outputs high Vee - MAX, See Note 4 8 14 8 14 mA -20 -100 -20 • t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. tAli typical values are at V CC = 5 V, T A = 25° C. §Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. NOTES: 3. ICCL is measured with all outputs open and all inputs grounded. 4. IICCH is measured with all outputs open and all inputs at 4.5 V. switching characteristics, Vee =5 V, TA = 25°e PARAMETER TEST CONDITIONS tpLH Propagation delay time, low-to-high-Ievel output CL=15pF, tpHL Propagation delay time, high-to-Iow-Ievel output See Note 6 NOTE 6: RL=2k!l, MIN TVP MAX 9 15 20 33 Load circuit and waveforms are shown on page 3-11. B77 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-289 TTL MSI TYPES SN54184, SN54185A, SN74184, SN74185A BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS BULL~TIN NO. DL-S 7211392, FEBRUARY 1971 - REVISED DECEMBER 1972 SN54184, SN74184 BCD-TO-BINARY CONVERTERS SN54185A, SN74185A BINARY-TO-BCD CONVERTERS SN54184, SN54185A .. _J OR W PACKAGE SN74184, SN74185A .• _J OR N PACKAGE (TOP VIEW) description These monolithic converters are derived from the custom MSI 256-bit read-only memories SN5488 and SN7488. Emitter connections are made to provide direct read-out of converted codes at outputs Y8 through Y1 as shown in the function tables. These converters demonstrate the versatility of a read-only memory in that an unlimited number of reference tables or conversion tables may be built into a system using economical, customized read-only memories. Both of these converters comprehend that the least significant bits (LSB) of the binary and BCD codes are logically equal, and in each case the LSB bypasses the converter as illustrated in the typical applications. This means that a 6-bit converter is produced in each case. Both devices are cascadable to N bits. positive logic: see function table An overriding enable input is provided on each converter which, when taken high, inhibits the function, causing all outputs to go high_ For this reason, and to minimize power consumption, unused outputs Y7 and Y8 of the '185A and all "don't care" conditions of the '184 are programmed high. The outputs are of the open-collector type . • The SN54184 and SN54185A are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74184 and SN74185A are characterized for operation from O°C to 70°C. SN54184 and SN74184 BCD-to-binary converters TABLE I SN54184, SN74184 The 6-bit BCD-to-binary function of the SN54184 and SN74184 is analogous to the algorithm: PACKAGE COUNT AND DELAY TIMES FOR BCD-TO-BINARY CONVERSION a. Shift BCD number right one bit and examine each decade. Subtract thre.e from each 4-bit decade containing a binary value greater than seven. b. Shift right, examine, and correct after each shift until the least significant decade contains a number smaller than eight and all other converted decades contain zeros. INPUT PACKAGES (DECADES) REQUIRED TOTAL DELAY TIMES (ns) TYP MAX 2 2 56 80 3 6 140 200 4 11 196 280 5 19 280 400 6 28 364 520 1076 7-290 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54184, SN54185A, SN74184, SN74185A BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS SN54184 and SN74184 BCD-to-binary converters (continued) BCD 10'S COMPLEMENT CONVERTER BCD9'S COMPLEMENT CONVERTER 6-BIT CONVERTER ,......-/'-.. ~ DeB ~ ~ 6-BIT BINARY OUTPUT BCD 0 C B ~ FUNCTION TABLE BCD 9'S OR BCD 10'S COMPLEMENT CONVERTER INPUTS OUTPUTS ISee Note AI ISee Note BI BCD WORD Y5 Y4 YJ Y2 Yl L L L L L E 0 L B L G L C L A 0-' 2-3 L L L L L L H L L L L L 4-5 L L L H L L L L L 6-7 L L L H H L L L 8-9 L L H L L L L L Et INPUTS OUTPUTS ISee Note CI ISee Note 01 C L A G L 0 L B a L L L YB Y7 Y6 H L H 1 L L L L H L H L L H L 2 L L L H L L L H H L H H 3 L L L H H L L H L H L L 4 L L H L L L L H H H L H H 10-" 12-13 L H L L L L L H H 5 L L H L L L H L H L L H L L L H H L 6 L L H H L L L L 14-15 L H L H L L L L H H H 7 L L H H H L L L L 16-17 L H L H H L L H L L L 8 L H L L L L L L H 18-19 L H H L L L L H L L H 9 L H L L H L L L L 20-21 H L L L L L L H L H L a H L L L L L L L L L A BCD 10'S COMPLEMENT BCD 9'$ COMPLEMENT FUNCTION TABLE BCD-TO-BINARY CONVERTER WORDS 5V A L 22-23 H L L L H L L H L H H 1 H L L L H L H L L 24-25 H L L H L L L H H L L 2 H L L H L L H L L 26-27 H L L H H L L H H L H 3 H L L H H L L H H 28-29 30-31 H L H L L L L H H H L 4 H L H L L L L H H H H L L L L L H H H H 5 H L H L H L L H L 32-33 H H L L H L H L L L L 6 H L H H L L L H L 34-35 H H L H L L H L L L H 7 H L H H H L L L H 36-37 H H L H H L H L L H L 8 H H L L L L L L H 38-39 ANY H H H L L L H L L H H H L L H L L L L X X X X H H H H H H 9 ANY H X X X X X X H H H H a I H = high level, L = low level, X = irrelevant NOTES: C. Input conditions other than those shown produce highs at outputs Y6, Y7, and YB. D. Outputs Yl through Y5 are not used "for BCD 9's or BCD 10's complement conversion. H = high level, L = low level, X = irrelevant NOTES: A. Input conditions other than those shown produce highs at outputs Yl through Y5. B. Outputs Y6, Y7, and YB are not used for BCD·to· binary conversion. tWhen these devices are used as complement converters, input E is used as a mode control. With this input low, the BCD 9's complement is generated; when it is high, the BCD 10's complement is generated. In addition to BCD-to-binary conversion, the SN54184 and SN74184 are programmed to generate BCD 9's complement or BCD 10's complement. Again, in each case, one bit of the complement code is logically equal to one of the BCD bits; therefore, these complements can be produced on three lines. As outputs Y6, Y7, and Y8 are not required in the BCD-to-binary conversion, they are utilized to provide these complement codes as specified in the function table (above, right) when the devices are connected as shown above the function table. 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-291 TYPES SN54184, SN54185A, SN74184, SN74185A BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS 6-BIT CONVERTER SN54185A and SN74185A binary-to-BCD converters The function performed by these 6-bit binary-to-BCD converters is analogous to the algorithm: a. Examine the three most significant bits. If the sum is greater than four, add three and shift left one bit. b. Examine each BCD decade. If the sum is greater than four, add three and shift left one bit. c. Repeat step b until the least-significant binary bit is in the least-significant BCD location. FUNCTION BINARV WORDS o· TABLE II BINARV SELECT E D C B OUTPUTS ENABLE A G VB V7 Y6 V5 V4 V3 V2 VI 1 L L L L L L H H L L L L L L 2·3 L L L L H L H H L L L L L H 4·5 L L L H L L H H L L L L H L 6·7 L L L H H L H H L L L L H H 8·9 L L H L L L H H L L L L H 10· 11 L L H L H L H H L L H L L L PACKAGE COUNT AND DELAY TIMES 12· 13 L L H H L L H H L L H L L H FOR BINARY-TO-BCD CONVERSION 14· 15 L L H H H L H H L L H L H L 16· 17 L H L L L L H H L L H L H H H L SN54185A, SN74185A INPUT PACKAGES (BITS) REQUIRED TOTAL DELAY TIME (ns) L 18· 19 L H L L H H L L H H TYP MAX 20· 21 L H L H L L H H L H L L L L 1 25 40 22· 23 L H L H H L H H L H L L L H 7 or 8 3 50 80 24· 25 L H H L L L H H L H L L H L 9 4 75 120 26· 27 L H H L H L H H L H L L H H H 4 to 6 • TABLE INPUTS L 10 L H H H L L H H 6 100 L L H 160 L 30· 31 L H H H H L H H L H H L L L 11 7 125 200 32· 33 H L L L L L H H L H H L L H 12 8 125 200 34· 35 H L L L H L H H L H H L H L 36· 37 H L L H L L H H L H H L H H 38· 39 13 10 150 240 28· 29 L L 14 12 175 280 H L L H H L H H L H H H L L 40· 41 H L H L 15 14 L L H H H 175 L L L L L 280 42· 43 H L H L L H H H L L L L H 16 16 200 320 44· 45 H L H H L L H H H L L L H L 360 46· 47 H L H H H L H H H L L L H H 48· 49 H H L L L L H H H L L H L L 50· 51 H H L L H L H H H L H L L L 52·53 H H L H L L H H H L H L L H 54·55 H H L H H L H H H L H L H L 56· 57 H H H L L L H H H L H L H H 58· 59 H H H L H L H H H L H H L L 17 19 225 18 21 225 360 19 24 250 400 20 27 275 440 H 60· 61 H H H H L L H H H H L L L L 62· 63 H H H H H L H H H H L L L H ALL X X X X X H H H H H H H H H H =- high lever, L :. low level, X = irrelevant absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) ......... . fnput voltage. . . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54184, SN54185A SN74184,SN74185A Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1272 7-292 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54184, SN54185A, SN74184, SN74185A BCD-TO·-BINARY AND BINARY-TO-BCD CONVERTERS REVISED DECEMBER 1980 recommended operating conditions SN54184. SN54185A SN74184. SN74185A NOM MIN 4.5 Supply voltage. Vee MAX MIN 5.5 4.75 5 Low-level output current. IOL NOM 5 12 -55 Operating free·air temperature. T A 125 0 MAX 5.25 UNIT V 12 rnA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage IOH MIN TYPj: MAX UNIT V 2 High·level output current Vec~ MIN. II ~-12mA Vec~ MIN. VIH~2V. VIL ~ 0.8 V. VOH ~ 5.5 V Vec~ VIH~2V. MIN. 0.8 V -1.5 V 100 J.lA VOL Low·level output voltage VIL; 0.8 V. IOL ~ 12 rnA II Input current at maximum input voltage VCC ~ MAX. VI- 5.5 V IIH High·level input current VCC MAX. VI ~ 2.4 V 40 J.lA IlL Low·level input current VCC; MAX. VI ~ 0.4 V -1 rnA ICCH Supply current. all outputs high ICCL Supply current. all programmed outputs low ~ 0.4 1 50 Vcc; MAX 62 99 V rnA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 5 V, T A; 25°C. +AII typical values are at V CC ; switching characteristics, Vee =5 V, TA = 25°e TEST CONDITIONS PARAMETER Propagation delay time. low·to·high·level output from enable G MIN TYP MAX UNIT 30 ns tpHL Propagation delay time. high·to·low·level output from enable G tpLH Propagation delay time. low·to·high·level output from binary select RL1 n. RL2 ~ 600 n, 22 35 ns 27 40 ns tpHL Propagation delay time. high·to·low·level output from binary select See Figure 1 and Note 2 23 40 ns tpLH ~ 30pF. ~ 300 19 schematics of inputs and outputs PARAMETER MEASUREMENT INFORMATION EQUIVALENT OF ALL INPUTS 1 VCC CL TYPICAL OF ALL OUTPUTS VCC------e------- 30 pF FROM OUTPUT UNDER TEST _~OUTPUT -----.-----1 RL2 600 n CL INPUT .-= CL includes probe and jig capacitance. LOAD CIRCUIT FIGURE 1 NOTE 2: Voltage waveforms are shown on page 3·10. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-293 TYPES SN54184, SN54185A, SN74184, SN74185A BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS TYPICAL APPLICATION DATA SN54184,SN74184 . BCD FIGURE 1-BCD·TO·BINARY CONVERTER FOR TWO BCD DECADES . BCD • FIGURE 2-BCD·TO·BINARY CONVERTER FOR THREE BCD DECADES FIGURE 3-BCD·TO·BINARY CONVERTER FOR SIX BCD DECADES MSD-most significant decade LSD-least significant decade Each rectangle represents an SN54184 or SN74184. 1272 7·294 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54184, SN54185A, SN74184, SN74185A BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS TYPICAL APPLICATION DATA SN54185A,SN74185A BlNAFly ~ FIGURE 4-6-BIT BINARY-TO-BCD CONVERTER '-.r-'~~~ \ MSD LSD Ii BCD FIGURE 7-12-BIT BINARY-TO-BCD CONVERTER (SEE NOTE B) \ MSD v BCD FIGURE 5-8-BIT BINARY-TO-BCD CONVERTER ~'--v---' \ MSD ISO t V BCD FIGURE 6-9-BIT BINARY-TO-BCD CONVERTER FIGURE 8-16-BIT BINARY-TO-BCD CONVERTER (SEE NOTE B) MSD-Most significant decade LSD-Least significant decade NOTES: A_ Each rectangle represents an SN54185A or an SN74185A_ B_ All unused E inputs are grounded_ 1272 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-295 TYPES SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL BULLETIN NO. DL·S 11865, DECEMBER 1972 - • Counts 8-4-2-1 BCD or Binary • Single Down/Up Count Control Line • Count Enable Control Input INPUTS Ripple Clock Output for Cascading Asynchronously Presettable with Load Control • Parallel Outputs • Cascadable for n-Bit Applications AVERAGE DELAY INPUTS ,.---"---. DATA RIPPLE MAX! A I CLOCK ,CLOCK LOAD • PROPAGATION QUTPUTS, r--"--~ • TYPE REVISED DECEMBER 1980 SN54', SN54LS' ••• J OR W PACKAGE SN74', SN74LS' ••• J OR N PACKAGE (TOP VIEW) TYPICAL TYPICAL MAXIMUM CLOCK POWER DISSIPATION FREQUENCY '190, '191 20 ns 25 MHz 325mW 'LS190, 'LS191 20 ns 25 MHz 100mW description 08 0A B ' - - ' '-.,--J INPUT OUTPUTS ENABLE DOWNI UP 0c DO ' - . r - - ' '-.t--' INPUTS OUTPUTS asynchronous inputs: Low input to load sets QA=A, aS = s, Oc = C, and aD = D The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58 equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output ,counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high-Ievel transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry may occur if both the clock and enable are low and the down/up input is high during a load pulse. • These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo·N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a lOW-level output pulse equal in width to the low·level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. Series 54' and 54LS' are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74' and 74LS' are characterized for operation from.O°C to 70°C. 1280 7-296 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL functional block diagrams 61 ;;1 "1 i~ ~ ~a ::: ~~ El . Q Q ~ ~ _LC - - ~o (J~ t~ ~ ~2 (I) a:: w -, I:2 ::> ou >a:: , 1 « ~ .... 0 l r- a5 lOa: i~; ~a TC L;' m :2 ~ ~ 11 ~ ~ ~ L~ L~ 'i 0 - ~~ C 'i L~ a; =1 II (I) a:: I w I:2 ::> o u w c « u w C I oC') (i; :-I :l .5o O~ C') .~ !'"" > o .u - ~i § .0 ~~ ? 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·297 TYPES SN54190, SN54LS190, SN74190, SN74LS190 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL '190, 'LS190 DECADE COUNTERS typical load, count, and inhibit sequences Illustrated below is the following sequence: 1. 2. 3. 4. Load (preset) to BCD seven. Count up to eight, nine (maximum). zero, one, and two. Inhibit. Count down to one, zero (minimum). nine, eight, and seven. LOAD~ A DATA INPUTS I I I I ~i IL_ ...J BJ\T1I L- - I C r-;---'j1 -- ...J: 'L_ r- D ---~~, -- CLOCK DOWN/UP • IL,.......;..._:---__________. . . . ENABLE IL...-;..-....:....;......;..._ _ _ _ _ _ _----' I I OB:::~r--n~I- - - - - - - - 'II !. °c ----rTl I ---~ ___ , I ~I--------------~---~--7_---------~ II °D ____ LiJ L- :::J :: r_l~____~____~~~r-l~------- II MAX/MIN I I I I RIPPLE CLOCK ----I I I : I I 7 I I ---....I u 8 9 I I J.-- U 0 1 ·2 COUNT UP - I - I N H I B I T - I ~ 2 I---- COUNT DOWN - - -... LOAD 1272 7·298 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54191, SN54LS191, SN74191, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL '191, 'LS191 BINARY COUNTERS typical load, count, and inhibit sequences Illustrated below is the following sequence: 1. 2. 3. 4. Load (preset) to binary thirteen. Count up to fourteen, fifteen (maximum), zero, one, and two. Inhibit. Count down to one, zero (minimum), fifteen, fourteen, and thirteen. LOA0-U A st-h.: = I B DATA INPUTS : I I { I :r- I-- I CJTTl':= I OJ"!--TL":= CLOCK ENABLE IL.-+-~';-_ _ _ _ _ _---! aa:':l...JJ Dc::] MAXIMIN:-=: L '--_ _....1 : I • n ...___-:-__~:___:_---'nL...----- J U RIPPLE CLOCK: - ] : 13 I 14 15 U 0 1 2, 2 j.---COUNT UP--_!--INHIBIT-I 2 15 14 13 I--COUNT O O W N - - I ~ I LOAO absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) . . . . Input voltage: SN54', SN74' Circuits. . . SN54LS', SN74LS' Circuits. Operating free-air temperature range: SN54', SN74', Storage temperature range 7V . . . . . . . . SN54LS' SN74LS' . . . . . . . . Circuits. Circuits. 5.5 V 7V · -55°C to 125°C · . O°C to 70°C · -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-299 TYPES SN54190, SN54191, SN74190, SN74191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL recommended operating conditions SN54190, SN54191 MIN Supply voltage, Vee 4.5 SN74190, SN74191 NOM MAX 5 High-level output current, 10H 5.5 MIN 4.75 NOM MAX 5 -800 Low-level output current, 10l 16 0 Input dock frequency, fclock 20 0 UNIT 5.25 V -800 /lA 16 rnA 20 MHz Width of clock input pulse, tw(clock) 25 25 Width of load input pulse, twlioad) 35 35 ns Data setup time, tsetup (See Figures 1 and 2) 20 20 ns Data hold time, thold 0 Operating free-air temperature, T A ns 0 -55 125 ns 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage Vee = MIN VIL Low-level input voltage Vee= MIN VIK Input clamp voltage Vee = MIN, 11=-12mA VOH High-level output voltage Vee= MIN, VIH=2V, VOL Low-level output voltage High-level input current at • TEST eONDITIONSt II maximum input voltage SN54190, SN54191 SN74190, SN74191 MIN MIN TYP:j: MAX 2 VIL = O.S V, 10H = -SOO/lA Vee= MIN, VIH = 2V, VIL = 0.8 V, IOL=16mA Vee = MAX, VI = 5.5V Vee = MAX, VI=2.4V 2.4 at any input except enable High-level input current IIH 9. 2 at enable input Low:level input current IlL at any input except enable Low-level input current IlL Vee = MAX, O.S -1.5 -1.5 2.4 304 0_2 0.4 Vee = MAX lee Supply current Vee = MAX, V V 0.4 V 1 1 mA 40 40 /lA 120 120 /lA -1.6 -1.6 mA -4.8 mA -65 mA 105 mA -4.8 Short-circuit output current§ V VI=Oo4V at enable input lOS UNIT V 0.8 3.4 High-level input current IIH TYP:j: MAX 2 -20 See Note 2 -65 65 99 -18 65 tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time. NOTE 2: lee is measured with all inputs grounded and all outputs open. 1076 7-300 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54190, SN54191, SN74190, SN74191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL switching characteristics, Vee PARAMETER~ f max tpLH tpHL tPLH tpHL = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) '190. '191 TEST CONDITIONS MIN TYP 20 Load 0A. OS. 0C. 0D Data A. S. C. D 0A. OS. 0C. 0D Clock Ripple Clock MAX 25 MHz 22 33 33 50 14 22 35 50 13 20 16 24 16 24 24 36 28 42 37 52 30 45 tpHL 30 45 tPLH 21 33 22 33 tpLH CL;15pF. tpHL tPLH Clock Clock Max/Min tpHL tPLH n. 0A. OS. 0C. 0D tpHL tpLH RL; 400 See Figures 1 and 3 thru 7 Ripple Clock Down/Up Down/Up Max/Min tpHL UNIT ns ns ns ns ns ns ns ~fmax "" maximum clock frequency tpLH == propagation delay time, low-to-high-Ievel output tpH L "" propagation delay time, high-to-Iow-Ievel output schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EOUIVALENT OF EACH INPUT VCC--------~------- ---.....---vcc Req • INPUT ....---OUTPUT Enable input: Req; 1.3 kn NOM All other inputs: Req; 4 kn NOM 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-301 TYPES SN54LS190, SN54LS191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL REVISED DECEMBER 1980 recommended operating conditions SN54LS190 SN74LS190 SN54LS191 MIN Supply voltage, VCC High·level output current, 10H 4.5 NOM 5 MIN 5.5 -400 4.75 Low·level output current, 10L 4 20 0 Clock frequency, fclock Width of clock input pulse, tw(clock) SN74LS191 MAX NOM 5 UNIT MAX 5.25 -400 8 20 0 V Il A mA MHz Width of load input pulse, tw(ioad) 25 35 25 35 ns Data setup time, tsetup (See Figures 1 and 2) 20 20 ns Data hold time, thold Count enable time, tenable (see Note 3)) Operating free·air temperature, T A 5 40 5 ns ns ns 40 -55 125 0 70 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS190 PARAMETER TEST eONDITIONSt V,H High·level input voltage V,L Low·level input voltage V,K Input clamp voltage 2 VOL Low·level output voltage II High·level input " input voltage I'H input current ',L Low·level High-level lOS ICC SN74LS191 UNIT MIN TYP:j: MAX 2 V 0.7 VOH High·level output voltage current at maximum SN74LS190 SN54LS191 MIN TYP:j: MAX VCC= MIN, 1,=-18mA Vee = MIN, V,H - 2V, -1.5 2.5 V,L = V,L max, 10H = -4001lA Vce= MIN, V'H=2V, V,L = V,L max 3.4 0.25 I'OL=4mA Vee = MAX, Enable Others Enable I Others input current Short-circuit output current§ Supply current Vee = MAX, Vce= MAX, Vce = MAX, Vee = MAX, 3.4 V V V 0.25 0.4 0.35 0.5 0.3 0.3 0.1 0.1 60 60 V, = 7 V V mA Others r--- 2.7 0.4 I'OL=8mA Enable r--- 0.8 -1.5 V, = 2.7 V V, = 0.4 V -20 See Note 2 20 20 20 -1.2 -0.4 -100 -1.2 -0.4 -100 35 -20 20 35 IlA mA mA mA tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions for the applicable device type. :j: All typical values are. at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTES: 2. ICC is measured with all inputs grounded and all outputs open. 3. Minimum count enable time is the interval immediately preceeding the rising edge of the clock pulse during which interval the count enable input must be low to ensure counting. 1280 7-302 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • OALLAS. TEXAS 75265 TYPES SN54LS190, SN54LS191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL REVISED OCTOBER 1976 switching characteristics, Vee PARAMETER~ = 5 V, T A = 25°e ·LS190. 'LS191 FROM TO (lNPUTI (OUTPUT! TEST CONOITIONS f max tpLH Load tpLH Data A, B, C, D tpHL tpLH Clock QA. QB. QC. QD CL=15pF,RL=2kn, Ripple Clock tpHL tPLH See Figures 1 and 3 thru 7 Clock QA, QB, QC, QD tPHL tPLH Clock TYP 20 25 22 QA. QB. QC. QD tPHL MIN Max/Min MAX MHz 33 33 50 20 32 27 40 13 20 16 24 16 24 24 36 28 42 tpHL 37 52 tPLH 30 45 tPHL 30 45 tpLH 21 33 tpHL tPLH tpHL Ripple Clock Down/Up Down/Up Max/Min Ripple Clock Enable UNIT 22 33 21 33 22 33 ns ns ns ns ns ns ns ns ~ f max := maximum clock frequency tpLH := propagation delay time, low-to-high-Ievel output tpH L := propagation delay time, high-to-Iow-Ievel output schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS --~...-VCC 120 U NOM VCC----~----- II I INPUT--~~~e--~~ "---"'-OUTPUT Enable input: Req = 8_33 kn NOM Load input: Req = 25 kn NOM All other inputs: Req = 17 kU NOM 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-303 TYPES SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL PARAMETER MEASUREMENT INFORMATION OUTPUT Vee ~"'0n' -.J ~""-"""'9""0%,,,1__ : ___ - - - -- 3V Vr.f (SEE NOTE B) MAX/MIN, : : RIPPLEeLoeK,,------~~_M 10% __~~,.*___~~D+~ 0A, 0B, 0c, OR 00 eL;15pF (SEE NOTE A) FIGURE l-LOAO CIRCUIT FOR SWITCHING TIME MEASUREMENT ~ I OATA : ~ ........ 10nl I I ~tsu LOAD t.- .. l0nl I L.i<-::::90%::---------,9""O,;'::-.i~ :~:~~~Vref T -I ·'i\k'0% i I I ~tlU i n - - -- - -- See waveform sequences in figures 4 through 7 for propaga- 3V tion times from a specific input to a specific output_ For OV I simplification, pulse rise times, reference levels, etc_, have .=",..---- not been shown in figures 4 through 7_ INPUT (SEE NOTE e) FIGURE 3-GENERAL VOLTAGE WAVEFORMS FOR ____--.J/ PROPAGATION TIMES FIGURE 2-DATA SETUP TIME VOLTAGE WAVEFORMS NOTES: A. B. C. D. CL includes probe and jig capacitance. All diodes are 1 N3064. The input pulses are supplied by generators having the following characteristics: Zout; 50 Vref; 1.5 V for '190 and '191; 1.3 V for 'LS190 and 'LS191. LOAD LJ 50%, PRR .;; 1 MHz. LJ I I I I ANY DATA INPUT II .n, duty cycle';; ----- -, I I CORRE~~~~~~~ _ _ _ _ _ _ , ! I tPLH~ I I 1 'I - I I I I ..-l I I I -I I 1 1 : - tPHL tPLH--l I I I 1 'I - I 1 I I -'I I 1 :-tPHL NOTE E: Conditions on other inputs are irrelevant. FIGURE 4-LOAD TO OUTPUT AND DATA TO OUTPUT LOADl..j L- DOWN/UP I I CLOCK ENABLEG -: RIPPLE CLOCK MAX/MIN NOTE F: All data inputs are low. FIGURE 5-ENABLE TO RIPPLE CLOCK, CLOCK TO RIPPLE CLOCK, DOWN/UP TO RIPPLE CLOCK, AND DOWN/UP TO MAX/MIN 1076 7-304 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL PARAMETER MEASUREMENT INFORMATION switching characteristics (continued) u LOAD-U -I DATA INPUTS- ISEE NOTESG TO 11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--' _ _ _ _ DOWN/UP UI WI ~ --,:....____________~I~----------------------~~L _______________ COUNT -:, : - tPLH :-tPHL OUTPUT lSI UNDER TEST_ _ _ I _ ENABLE = LOW NOTES: G. to test QA' QB, and Q C outputs of '190 and 'LS190: Data inputs A, B, and C are shown by the solid line. Data input D is shown by the dashed line. H. To test QD output of '190 and 'LS190: Data inputs A and D are shown by the solid line. Data inputs Band C are held at the low logic level. I. To test QA' QB, QC, and QD outputs of '191 and 'LS191: All four data inputs are shown by the solid line. FIGURE 6-CLOCK TO OUTPUT u LOAD~ DATA A ~~~AN~T~·J~NDD_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____II _____ _ DOWN/UP u-: COUNT U U U I l--l l-~ -..j -"'i-I-----:....-;I. . __________~Ii------.:.--;l.__ tPLH tpHL --: tpLH l-tPHL MAX/MIN_ _ _ _ _ _ ENABLE ~ LOW NOTE J: Data inputs Band C are shown by the dashed line for the '190 and 'LS190 and the solid line for the '191 and 'LS191: Data input D is shown by the solid line for both devices. FIGURE 7-CLOCK TO MAX/MIN 1272 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-305 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193 SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193 SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) BULLETIN NO. DL-S 7711828, DECEMBER 1972-REVISED AUGUST 1977 • • • • SN54', SN54LS' ••• J OR W PACKAGE SN54L' ••• J PACKAGE SN74', SN74L', SN74LS' ••• J OR N PACKAGE (TOP VIEW) Cascading Circuitry Provided Internally Synchronous Operation Individual Preset to Each Flip-Flop Fully Independent Clear Input TYPICAL MAXIMUM TYPICAL COUNT FREQUENCY POWER DISSIPATION 32MHz 325mW '192, '193 7MHz 43mW 'L192, 'L193 32 MHz 'LS192, 'LS193 95mW TYPES description These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192, 'L192, and 'LS192 logic: Low ini>ut to load sets Q = A, A circuits are BCD counters and the '193, 'L 193 and Q = S, Q = C, and Q = 0 'LS193 are 4-bit binary counters. Synchronous operaC D S tion is provided by having all flip-flops clocked simultaneously so that the outputs change coinci· dently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple·clock) counters. The outputs of the four master·slave flip-flops are triggered by a low-to·high·level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo·N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive require· ments. This reduces the number of clock drivers, etc., required for long words . • These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up· and down·counting functions. The borrow output produces a pulse equal in width to the count·down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count·down and count·up inputs respectively of the succeeding counter. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage Operating free-air temperature range Storage temperature range SN54'1 SN54L' ISN54LS' 8 7 J I 7 5.5 I 5.5 I 7 -55 to 125 -65 to 150 SN74' I SN74L' ISN74LS' UNIT 7 J 8 V I 7 5.5 I 5.5 V I 7 Vc Oto 70 -65 to 150 °c NOTE 1: Voltage values are with respect to network ground terminal. 877 7·306 TEXASINCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193, SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193 SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) functional block diagrams => .... o=> ~ .... => o=> 0 0 .... ~~ ~~ O=> 0:>0 uO 2 ~ o~ => 2 8 0. .... 2 =>~ => U g 0:> 0 0 .... .... .... ~ .... => => .... => => => 0 0 0 B 5 .... => .... o=> o=> o .... 2 .... o o .... => .... => => .... g 0:> o .... o .... .... .... § a: 0 .... 0 1 § ;: E ~ III B II ~ J: :c'" E ~ c: 0 ';:: '~ III > .0 l .~ :l 0. c: u .... 0. .... 2 =>2 => => o u 0 u 0:> .... u o ~ g .... ~ 1 0 o------+--+--____1>----+1H--~--____1>--___1H--~--~--_1H--~--__, 1'1) DB DC DD CD V~------------------------------/ PARALLEL OUTPUTS tThis connection is made on '195 only. typical clear, shift, and load sequences • I CLOCK I CLEAR __ ____ ~ J SERIAL INPUTS { K ____ ~ I I ~r--r-1~ ____ I ~~L ______________________ ____ _____________________ ~ ________________________ I ____ ~I ~ ~ ______________________ I l.!..-J I SHIFT'LOAD -----~---------~------------------------------~~~~------------------------------I PARALLEL{ : DATA INPUTS C L ----~--------~----------------------~~~--~--------------------I L D A OUTPUTS f I I I --------ooooo!jr---IL._ _ _ _ _ _ _ _ _ _ _ _ _ _ _...... ---~ - - ....•... 1 °B ---, --- ; I I Oc ---, I OD ---., ---~:------------~I------------~ I 1 100II11.....----------- SE R I A L SHI F T CLEAR I -------------.-j t----- SERIAL S H I F T _ LOAD 374 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-325 TYPES SN54195, SN54LS195A, SN54S195, SN74195, SN74LS195A, SN74S195 4-81T PARALLEL-ACCESS SHIFT REGISTERS REVISED OCTOBER 1976 schematics of inputs and outputs '195 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS -~'-----VCC Vcc---------~------- INPUT OUTPUT Clock input: Req =4 kn NOM All other Inputs: Req = 6 kn NOM 'LS195A K. EQUIVALENT OF CLEAR, CLOCK, EQUIVALENT OF J, A, B, C, AND D INPUTS TYPICAL OF ALL OUTPUTS AND SHIFT/LOAD INPUTS -------------~----VCC VCC---------~------- VCC-------~------- 17 kn 15 kn NOM INPUT--H.~--- INPUT-~~~---__- L...-_.,..__ __- OUTPUT • 'S195 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ------~~--VCC 50 n NOM VCC-----~--- INPUT '---*----- OUTPUT Clear, shift/load: Req All other inputs: Req = 4 kn NOM = 2.8 kn NOM 1076 7·326 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54195, SN74195 4-81T PARALLEL-ACCESS SHIFT REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. Vee (see Note 1) Input voltage . . . . . . . . Operating free·air temperature range: SN54195 SN74195 Storage temperature range 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54195 MIN 4.5 Supply voltage, VCC NOM SN74195 MAX MIN NOM 5.5 4.75 5 5 -800 High·level output current, 10H 16 Low-level output current, 10L 30 0 Clock frequency, fclock 0 UNIT MAX 5.25 V -800 j.!A 16 rnA 30 MHz Width of clock input pulse, tw(clock) 16 16 ns Width of clear input pulse, tw(clear) 12 12 ns I Shift/load 25 25 I Serial and parallel data 20 20 I Clear inactive-state 25 25 Setup time, tsu (see Figure 1) ns 10 Shift/load release time, trelease (see Figure 1) -55 Operating free-air temperature, T A 10 ns 70 °e 0 0 Serial and parallel data hold time, th (see Figure 1) 125 ns 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Lo.w-Ievel input voltage VIK Input clamp voltage VOH TEST CONDITIONSt MIN TYP+ MAX UNIT 2 High-level output voltage Vee; MIN, II; -12 rnA Vee; MIN, VIH; 2 V, VIL; 0.8 V, 10H ; -800 j.!A Vee - MIN, VIH; 2 V, VIL;0.8V, 10L; 16 rnA 2.4 V 0.8 V -1.5 V 3.4 V Low-level output voltage II Input current at maximum input voltage Vce; MAX, VI; 5.5 V 1 IIH High-level input current Vce; MAX, VI; 2.4 V 40 j.!A IlL Low-level input current Vce; MAX, VI;0.4V -1.6 mA lOS Short-circuit output current§ Vee; MAX ICC Supply current Vee; MAX, I • I 0.2 VOL 0.4 SN54195 -20 -57 I SN74195 -18 -57 See Note 2 39 63 V mA mA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC ; 5 V, T A ; 25° C. § Not more than one output should be shorted at a time. NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS f max Maximum clock frequency eL;15pF, tPHL Propagation delay time, high-to-Iow-Ievel output from clear RL =400 tPLH Propagation delay time, low-to-high-Ievel output from clock n, See Figure 1 tpHL Propagation delay time, high-to-Iow-Ievel output from clock MIN 30 TYP MAX 39 UNIT MHz 19 30 ns 14 22 ns 17 26 ns 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-327 TYPES SN54LS195A r SN74LS195A 4-81T PARALLEL-ACCESS SHIFT REGISTERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . ..... . Operating free·air temperature range: SN54LS195A SN74LS195A Storage temperature range 7V 7V _55°C to 125°e oOe to 700e 0 -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74LS195A SN54LS195A MIN NOM 4.5 Supply voltage, Vee MAX MIN 5.5 4.75 5 High·level output current, 10H NOM 5 -400 MAX V -400 IlA 4 Low-level output current, 10L 0 Clock frequency, fclock 30 UNIT 5.25 0 8 mA 30 MHz Width of clock or clear pulse, tw(clockl 16 16 ns Width of clear input pulse, tw(clearl 12 12 ns 25 25 Setup time, tsu (see Figure 11 I Shift/load t Serial and parallel data 15 15 I Clear inactive-state 25 25 ns 10 Shift/load release time, trelease (see Figure 11 Serial and parallel data hold time, th (see Figure 11 0 Operating free-air temperature, T A 10 ns 70 °e 0 -55 125 ns 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) • VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage SN54LS195A TEST eONDITIONSt PARAMETER TYP:t: MIN SN74LS195A MAX 2 VOH High-level output voltage Vee = MIN, II = -18 rnA Vee = MIN, VIH=2V, MIN VOL Low-level output voltage 2.5 Input current at UNIT V 0_8 V -1.5 -1.5 V 3.4 2.7 0.25 VIH=2V,[IOL=4mA VIL=VILmax MAX 0.7 VIL = VIL max, 10H = -400 IlA Vee = MIN, TYP:t: 2 0.4 tlOL = 8 rnA V 3.4 0.25 0.4 0.35 0.5 V rnA Vee = MAX, VI =7 V 0.1 0.1 IIH High-level input current Vee = MAX, VI=2.7V 20 20 IlA IlL Low-level input current Vee= MAX, VI = 0.4 V -0.4 -0.4 rnA lOS Short-circuit output current§ Vee = MAX -100 rnA ICC Supply current Vee = MAX, 21 rnA II maximum input voltage -20 -100 See Note 2 14 -20 21 14 tFor conditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions. fAil typical values are at Vee = 5 V. T A = 25 e. ~ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second, NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock. switching characteristics, Vee = 5 V, TA = 25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency tpH L Propagation delay time, high-to-Iow-Ievel output from clear tpLH Propagation delay time, low-to-high-Ievel output from clock CL = 15 pF, RL=2kn, See Figure 1 tpHL Propagation delay time, high-to-Iow-Ievel output from clock MIN TYP 30 39 MAX UNIT MHz ns 19 30 14 22 ns 17 26 ns 1076 7-328 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 TYPES SN54S195, SN74S195 4-81T PARALLEL-ACCESS SHIFT REGISTERS REVISED MARCH 1974 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . Operating free·air temperature range: 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C SN54S195 SN74S195 Storage temperature range NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S195 MIN Supply voltage, Vee 4.5 NOM SN74S195 MAX MIN 5.5 -1 4.75 5 High·level output current, 10H Low-level output current, 10L NOM 5 20 Clock frequency, fClock 0 70 0 UNIT MAX 5.25 -1 V mA 20 mA 70 MHz Width of clock input pulse, tw(clockl 7 7 ns Width of clear input pulse, tw(clearl 12 12 ns 11 11 L Shift/load l Setup time, tsu (see Figure 11 Serial and parallel data I Clear inactive·state Shift/load release time, trelease (see Figure 11 Serial and parallel data hold time, th (see Figure 11 5 5 9 9 ns 6 3 -55 Operating free-air temperature, T A 125 3 0 6 ns 70 ns °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage TEST eONDITIONSt MIN TYP+ MAX UNIT 2 VOH High·level output voltage Vee= MIN, II = -18 mA Vee= MIN, VIL = 0.8 V, VIH = 2 V, 10H = -1 mA Vee= MIN, VIH = 2 V, VOL Low-level output voltage VIL = 0.8 y, 10L = 20mA II Input current at maximum input voltage Vee = MAX, VI = 5.5V IIH High-level input current Vee = MAX, IlL Low·level input current Vee = MAX, lOS Short·circuit output current§ Vee = MAX ICC Supply current I SN54S195 I SN74S195 2.5 2.7 V V -1.2 V 3.4 0.5 V mA VI=2.7V 50 VI = 0.5 V -2 /lA mA -40 I SN54S195 I SN74S195 -100 70 70 • V 3.4 1 See Note 2 Vee = MAX, 0.8 99 109 I mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, followed by 4.5 V, to clear, and then applying a momentary ground, followed by 4.5 V, to clock. switching characteristics, Vee =5 V, TA = 25°e PARAMETER TEST CONDITIONS f max Maximum clock frequency eL=15pF, tPHL Propagation delay time, high-to·low-Ievel output from clear tPLH Propagation delay time, low-to-high-Ievel output from clock RL=280n, See Figure 1 tPHL Propagation delay time, high-to-Iow·level output from clock MIN TYP 70 105 MAX UNIT MHz 12.5 18.5 ns 8 11 12 16.5 ns ns 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·329 TYPES SN54195, SN54LS195A, SN54S195, SN74195, SN74LS195A, SN74S195 4-81T PARALLEL-ACCESS SHIFT REGISTERS PARAMETER MEASUREMENT INFORMATION OUTPUT VCC FROM OUTPU_T_...-M........--t........M-. .if-1 UNDER TEST CL=15pF (See Note B) LOAD FOR OUTPUT UNDER TEST II _ _ ___,.1 " tw(clearl I ~~~ CLEAR I I I 3V _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV --.j ~ tn+1 tsu I- t n +1 tn~ tn+-j V~ CLOCK ----3V V~ I ~::~ote tw(clock) !-t- th ,.. tsetup-l 1 G) _ _ _ _ _; -_ _ _ _ _, t-- tsu 1 V"f i~~ ----I 1-'1 -----+---,.~ v __<.l I SHIFT/LOAD ~ Vref: • I4---tPHL ---.I ASSOCIATED OUTPUTQ /4- trelease !1 tsu V"f !1v,~ ----.j I'I :: n-trelease < ,Vref 3V OV !--tPHL-, ~2:i--I )L J __ ~ OV th tsu 2~.. ~~~i------- !-tPLH-i -------_1 I ...r-tI 1 ,--_ _ _ __ Vref VOH ~ VOL VOLTAGE WAVEFORMS NOTES: A. The clock pulse generator has the following characteristics: Zout '" 50.n and PRR .;;; 1 MHz. For '195, tr .;;; 7 ns and tf .;;; 7 ns. For 'LS195A, tr';; 15 ns and tf';;; 6 ns. For '5195, tr = 2.5 ns and tf = 2.5 ns. When testing f max , vary the clock PRR. B. CL includes probe and jig capacitance. C. All diodes are 1 N3064. D. A clear pulse is applied prior to each test. E. For '195 and '5195, Vref = 1.5 V; for 'L5195A, Vref = 1.3 V. F. Propagation delay times (tPLH and tpH L) are measured at t n +1' Proper shifting of data is verified at tn+4 with a functional test. G. J and K inputs are tested the same as data A, B, C, and 0 inputs except that shiftlload input remains high. H. tn = bit time before clocking transition. tn+1 = bit time after one clocking transition. tn+4 = bit time after four clocking transitions. FIGURE 1-SWITCHING TIMES 1076 7·330 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54196, SN54197, SN54LS196, SN54LS197,SN54S196, SN54S197, SN74196, SN74197, SN74LS196, SN74LS197, SN14S196, SN74S197 50/30/100 -MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES BULLETIN NO. DL·S 7711806, OCTOBER 1976-REVISED AUGUST 1977 • Performs BCD, Bi-Quinary, or'Binary Counting • Fully Programmable • Fully Independent Clear Input • Input Clamping Diodes Simplify System Design • Output QA Maintains Full Fan-out Capability In Addition to Driving Clock-2 Input TYPES '196, '197 GUARANTEED TYPICAL COUNT FREQUENCY CLOCK 1 CLOCK 2 POWER DISSIPATION 0-50 MHz 0-25 MHz 240mW 'LS196, 'LS197 0-30 MHz 0-15 MHz 80mW 0-100 MHz 0-50 MHz 375mW 'S196, 'S197 KAGE SN74', SN74LS', SN74S' ••• J OR N PACKAGE (TOP VIEW) DATA INPUTS CLOCK VCC CLEAR CD ~OB , rg~~TI Cc ~ CA CL~CK GND DATA INPUTS asynchronous input: Low input to clear sets CA, CB, CC, and CD low. description These high-speed monolithic counters consist of four doc coupled, master-slave flip·flops. which are internally interconnected to provide either a divide-by-two and a divide·by-five counter ('196, 'LS196, 'S196) or a divide-by-two and a divide-by-eight counter ('197, 'LS197, 'S197). These four counters are fully programmable; that is, the outputs may be preset to any state by placing a low on the count/load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independent of the state of the clocks. During the count operation, transfer of information to the outputs occurs on the negative-going edge of the clock pulse. These counters feature a direct clear which when taken low sets all outputs low regardless of the states of the clocks. These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged when the count/load is high and the clock inputs are inactive. All inputs are diode-clamped to minimize transmission-line effects and simplify system design. These circuits are compatible with most TTL and DTL logic families. Series 54, 54LS, and 54S circuits are characterized for operation over the full military temperature range of -550 C to 1250 C; Series 74, 74LS, and 74S circu its are characterized for operation from 0 0 C to 700 C. typical count configurations '196, 'LS196, and 'S196 typical count configurations and function tables are the same as those for '176. See page 7-260. '197, 'LS197, and 'S197 typical count configurations and function tables are the same as those for '177. See page 7-260. functional block diagrams '196, 'LS196, and 'S196 functional block diagram is the same as that for '176. See page 7-261. '197, 'LS197, and 'S197 functional block diagram is the same as that for '177. See page 7-261. 877 TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-331 TYPES SN54196, SN54197, SN74196, SN74197 50-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES REVISED AUGUST 1977 schematics of inputs and outputs EaUIVALENT OF COUNT/LOAD, CLEAR, AND DATA INPUTS EaUIVALENT OF CLOCK INPUTS TYPICAL OF ALL OUTPUTS VCC--------~------- Req INPUT Countlload, Data: Req Clear: Req = 4 kn NOM = 2 kn NOM INPUT Clock 1 Clock 2 NOMINAL VALUES OF R1, R2, and R3 '196 '197 4 kn 4 kn 3 kn 6 kn absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature range: SN54196, SN54197 Circuits SN.74196, SN74197 Circuits Storage temperature range NOTES: • 7V 5.5V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and count/load inputs . recommended operating conditions SN54196, SN54197 MIN 4.5 Supply voltage, VCC High-level output current, IOH MAX MIN NOM MAX 5 5.5 4.75 5 5.25 -800 Low-level output current, IOL Count frequency Pulse width, tw Input hold time, th Input setup time, tsu SN74196, SN74197 NOM -800 16 16 Clock-1 input 0 50 25 0 50 0 25 Clock-2 input 0 Clock-1 input 10 Clock-2 input 20 20 Clear 15 15 Load 20 20 tw(ioad) tw(ioad) Low-level data tw(ioad) 10 tw(load) 10 Low-level data Count enable time, tenable (See Note 3) Operating free-air temperature, T A V jlA mA MHz 10 High-level data High-level data UNIT 15 15 20 -55 20 125 0 ns ns ns ns 70 °c NOTE 3: Minimum count enable time is the Interval immediately preceding the negative-going edge of the clock pulse during which interval the count/load and clear inputs must both be high to ensure counting. 877 7·332 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54196, SN54197, SN74196, SN74197 50-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage TEST eONDITloNst SN54196,SN74196 SN54197,SN74197 MIN TVP+ MAX MIN V O.S VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current VCC= MIN, II = -12mA VCC= MIN, VIH=2V, VIL = O.S V, 10H = -SOOJ.lA VCC = MIN, VIH-2V, VIL = O.S V, 10L = 16mA~ -1.5 2.4 2.4 3.4 0.4 0.2 VCC = MAX, VI = 2.4 V clock 2 data, count/load clear IlL Low-level input current lOS Short-circuit output current § VCC = MAX ICC Supply current VCC = MAX, See Note 4 VCC = MAX, VI = 0.4 V clock 1 clock 2 V -1.5 V V 3.4 0.2 1 40 40 SO SO 120 SO -1.6 -1.6 -3.2 -3.2 -4.S -4.S mA J.lA mA -3.2 -20 -57 -20 -57 -18 -57 -18 -57 48 V 0.4 -6.4 I SN54' I SN74' O.S 1 Vce = MAX, VI = 5.5 V data, count/load clear, clock 1 UNIT TVP+ MAX 2 2 48 59 mA 59 mA NOTE 4: lee is measured with all inputs grounded and all outputs open. tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°e. outputs are tested at IOL = 16 mA plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning out to 10 Series 54/74 loads. § Not more than one output should be shorted at a time. 11 Q A switching characteristics, Vee PARAMETERO f max tpLH tpHL tpLH tpHL tpLH TO (OUTPUT) Clock 1 QA Clock 1 QA Clock 2 QB Clock 2 QC tpHL tpLH TEST CONDITIONS Clock 2 MIN TVP 50 70 CL = 15 pF, QD A, B, C, 0 See Note 5 QA, QB, QC, QD Load Any Clear Any tpHL tpHL Ofmax == SN54197 SN74196 RL = 400.n, tpHL tpLH SN54196 FROM (lNPUTi tpHL tpLH = 5 V, TA = 25°e SN74197 MAX MIN TYP 50 70 UNIT MAX MHz 7 12 7 12 10 15 10 15 12 1S 12 18 14 21 14 21 24 36 24 36 28 42 2S 42 14 21 36 54 12 18 42 63 16 24 16 24 25 38 25 38 22 33 22 33 24 36 24 36 25 37 25 37 • I ns ns ns ns ns ns ns maximum count frequency. tpLH == propagation delay time, low-to-high-Ievel output. tpHL == propagation delay time, high-to-Iow-Ievel output. NOTE 5: Load circuit, Input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that testing f max , VI L = 0.3 V. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE SOX 5012 • DALLAS, TEXAS 75222 7-333 TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197 30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES REVISED AUGUST 1977 schematics of inputs and outputs ~------------------------~ EQUIVALENT OF COUNT/LOAD AND CLEAR INPUTS EQUIVALENT OF CLOCK INPUTS EQUIVALENT OF DATA INPUTS TYPICAL OF ALL OUTPUTS VCC VCC - - - . - - - - - 25 kn NOM INPUT INPUT n. ~ 'V ~~ Count/Load: Req = 17 kn NOM Clear: Req = 9.2 kn NOM INPUT Clock 1 Clock 2 ~r NOMINAL VALUES OF R1, R2, and R3 'LS196 'LS197 8 kn 8 kn 6 kn 15 kn /i7 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2). Operating free·air temperature range: SN54LS196, SN54LS197 Circuits SN74LS196, SN74LS197 Circuits Storage temperature range NOTES: • 7V 5.5 V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C 1. Voltage values are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and count/load inputs • recommended operating conditions SN54LS196, SN54LS197 MIN Supply voltage, Vce High-level output current, IOH MIN NOM MAX 5 5.5 -400 4.75 5 5.25 -400 IlA 8 mA 4.5 Pulse width, tw 4 0 30 Clock-2 input 0 15 Clock-1 input Clock-2 input 20 30 30 Clear 15 15 Clock-1 input Load Input hold time, th Input setup time, tsu 0 30 0 15 20 tw(ioad) Low-level data tw(ioad) 10 tw(ioad) 10 Low-level data Operating free-air temperature, T A MHz ns 20 tw(ioadl Count enable time, tenable (See Note 3) V 20 High-level data High-level data UNIT MAX Low-level output current, IOL Count frequency SN74LS196, SN74LS197 NOM 15 15 30 -55 30 0 125 ns ns ns 70 °c NOTE 3: Minimum count enable time Is the interval immediately preceding the negative-going edge of the clock pulse during which interval the count/load and clear inputs must both be high to ensure counting, - 877 7-334 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197 30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES REVISED OCTOBER 1976 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt SN54LS196 SN74LS196 SN54LS197 SN74LS197 MIN VIH High-level input voltage VIL Low-level input voltage TYP:j: MAX 2 VIK Input clamp voltage VOH High-level output voltage VCC= MIN, 11=-18mA VCC= MIN, VIH = 2V, VCC= MIN, VOL Low-level output voltage VIH=2V, 2.5 2 Input current input voltage High-level IIH input current V -1.5 -1.5 V 3.4 2.7 0.4 0.25 Input current 0.4 0.5 0.1 0.1 0.2 0.4 0.2 0.4 Clock 2 of'LS197 0.2 0.2 Data, count/load 20 20 40 40 80 80 Clear, clock 1 Clock 2 of 'LS196 Clear, clock 1 Clock 2 of 'LS196 VCC = MAX, VCC= MAX, VI = 5.5V VI = 2.7 V Clock 2 of 'LS197 Low-level V 3.4 0.25 0.35 Data, count/load Data, count/load IlL V 0.8 IIOL =8mAlI VIL = VIL max at maximum IIOL=4mAlI UNIT TYP:j: MAX 0.7 VIL = VIL max' 10H = -400 IJA II MIN Clear Clock 1 VCC = MAX, .. VI = 0.4 V Clock 2 of 'LS196 Clock 2 of 'LS197 40 40 -0.4 -0.4 -0.8 -0.8 -2.4 -2.4 -2.8 -2.8 -1.3 lOS Short-circuit output current§ VCC = MAX ICC Supply current VCC= MAX, -100 -20 See Note 4 16 V mA IJA mA -1.3 -20 -100 mA 27 mA 16 27 t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-<:ircuit should not exceed one second. 11 QA outputs are tested at specified 10 L plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while maintaining full fan-out capability. NOTE 4: ICC is measured with all inputs grounded and all outputs open. switching characteristics, Vee PARAMETERO f max tpLH TO (OUTPUT) Clock 1 QA Clock 1 Clock 2 QB Clock 2 QC tpHL tpLH TEST CONDITIONS MIN 30 CL=15pF, RL Clock 2 =2 kil, See Note 6 QD tPHL tpLH A,B,C,D QA,QB,QCQD Load Any Clear Any tPHL tPLH tPHL tpHL ot max == maximum count frequency SN54LS197 SN74LS196 QA tPHL tpLH SN54LS196 FROM (INPUT) tpHL tpLH = 5 V, TA = 25°e TVP SN74LS197 MAX 40 MIN 30 TYP UNIT MAX 40 • I I MHz 8 15 8 15 13 20 14 21 16 24 12 19 22 33 23 35 38 57 34 51 41 62 42 63 12 18 55 78 30 45 63 95 20 30 18 27 29 44 29 44 ns ns ns ns 27 41 26 39 30 45 30 45 34 51 34 51 ns ns ns = tpLH == propagation delay time, low-to-high-Ievel output, tpH L propagation delay time, high-to-Iow-Ievel output NOTE 6: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that tr';; 15 ns, tf';; 6 ns, and Vref = 1.3 V (as opposed to 1.5 V) 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-335 TYPES SN54S196, SN54S197, SN74S196, SN74S197 100-MHZ PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES schematics of inputs and outputs EQUIVALENT OF COUNT/LOAD, EQUIVALENT OF CLOCK INPUT CLEAR,AND DATA INPUTS Vce VCC ----4J-- TYPICAL OF ALL OUTPUTS -~...-- -----~--VCC 50n /"""------41 NOM INPUT Clock 1 Req Count/Load, Clear: Req = 2.3 kn NOM Data: Req = 2.8 kn NOM = 1.2 kn NOM Clock 2 'S196 Req = 700 n NOM Clock 2 'S197 Req = 1.4 kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply Voltage, VCC (see Note 1) Input voltage Operating free-air temperature range: SN54S196, SN54S197 Circuits SN74S196, SN74S197 Circuits Storage temperature range 7V 5.5 V _55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. • recommended operating conditions SN54S196, SN54S197 Supply voltage, VCC NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 -1 High-level output current, IOH Low-level output current, IOL Clock frequency Pulse width, tw Input hold time, th Input setup time, tsu SN74S196, SN74S197 MIN -1 20 20 Clock-l input 0 100 0 100 Clock-2 input 0 50 0 50 Clock-l input 5 Clock-2 input 10 10 30 30 Load 5 5 High-level data 3t 3t Low·level data 3t 3t High-level data 6t st Low-level data at st 12 12 Operating free-air temperature, T A -55 V rnA mA MHz 5 Clear Count enable time, tenable (see Note 3) UNIT 125 0 ns ns ns ns 70 "c NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the count/load and clear inputs are both high to permit counting. 1076 7-336 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S196, SN54S197, SN74S196, SN74S197 100-MHZ PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt VIH High-level input voltage VIL VIK Low-level input voltage Input clamp voltage VOH High-level output voltage VOL Low-level output voltage SN74S197 MIN TYP:j: MAX High-level input current VCC= MIN, II = -18 mA VCC = MIN, VIH=2V, VIL = 0.8 V, VCC = MIN, VIH=2V, VIL = 0.8 V, 10L = 20 mA~ VCC= MAX, VI = 5.5 V VCC = MAX, VI=2.7V I 2.5 3.4 2.5 3.4 2.7 3.4 2.7 3.4 data, count/load IlL Low-level input clear current clock 1 VCC = MAX, Short-circuit output current§ Vce = MAX ICC Supply current VCC = MAX, See Note 4 \54S 174s V V 0.5 0.5 1 1 V mA 50 50 }J.A 0.75 mA -8 -8 mA -10 -6 mA -110 mA VI = 0.5 V -30 V 0.75 clock 2 lOS 0.8 -1.2 -1.2 \54S 10H = -1 mA 74S UNIT V 2 0.8 input voltage IIH SN54S197, SN74S196 MIN TYP:j: MAX 2 Input current at maximum II SN54S196, -110 -30 75 110 75 110 75 120 75 120 mA NOTE 4: ICC is measured with all inputs grounded and all outputs open. tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j: All typical values are at VCC = 5 V, T A = 25° C. 'I QA outputs are tested at IOL = 20 mA plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning out to 10 Series 545/745 loads. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. switching characteristics, Vee PARAMETERo f max tpLH tpHL tpLH tpHL tPLH tpHL tpLH tpHL tpLH tpHL tpHL SN54S196, FROM (INPUT) TO (OUTPUT) Clock 1 °A Clock 1 5 °A 6 °a Clock 2 Clock 2 TEST CONDITIONS CL=15pF, °c RL = 280 Clock 2 tpHL tpLH = 5 V, T A = 25° C A,a,C,O See Note 7 00 0A, 0B, 0C, 00 Load Any Clear Any n, SN54S197, SN74S197 SN74S196 MIN TYP 100 140 MAX MIN UNIT TYP 140 MAX 10 5 10 10 6 10 5 8 10 12 5 8 10 12 12 18 12 18 16 24 15 22 100 MHz 5 10 18 27 8 12 22 33 7 12 7 12 12 18 12 18 10 18 10 18 12 18 12 18 26 37 26 37 • ns ns ns ns ns ns ns Of max;; maximum input county frequency. tpLH ;; propagation delay time, low-to-high-Ievel output. tpHL;; propagation delay time, high-to-Iow-Ievel output. NOTE 7: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 on page 7-264. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-337 TTL MSI TYPES SN54198, SN54199, SN74198, SN74199 8-BIT SHIFT REGISTERS BULLETIN NO. DL-S 7711841, DECEMBER 1972-REVISED AUGUST 1977 descri ption SN54198 _•. J OR W PACKAGE SN74198 ••• J OR N PACKAGE (TOP VIEW) These 8-bit shift registers are compatible with most other TTL, DTL, and MSI logic families. All inputs are buffered to lower the drive requirements to one normalized Series 54/74 load, and input clamping diodes minimize switching transients to simplify system design. Maximum input clock frequency is typically 35 megahertz and power dissipation is typically 360 mW. SHIFT LEFT SERIAL INPUT Vee 81 INPUT H INPUT INPUT 0H F G INPUT E Series 54 devices are characterized for operation over the full military temperature range of -55°C to 125° C; Series 74 devices are characterized for operation from O°C to 70°C. SO SHIFT INPUT RIGHT SERIAL INPUT SN54198 and SN74198 0A A These bidirectional registers are designed to incorpopositive logic: see function table rate virtually all of the features a system designer may want in a shift register. These circuits contain 87 equivalent gates and feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-modecontrol inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (Broadside) Load Shift Right (In the direction GA toward GH) Shift Left (In the direction GH toward GA) Inhibit Clock (Do nothing) Synchronous parallel loading is accomplished by applying the eight bits of data and taking both mode control inputs, SO and S1, high. The data is loaded into the associated flip-flop and appears at the outPUtS after the positive transition of the clock input. During loading, serial data flow is inhibited. • Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and S1 is low. Serial data for this mode is entered at the shift-right data input. Wh~n SO is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode cont only while the clock input is high. inputs are low. The mode controls should be changed '198 FUNCTION TABLE OUTPUTS INPUTS SERIAL PARALLEL LEFT RIGHT A ... H °A °B X X L L MODE CLEAR c - - - CLOCK S1 So X X L X H X t H X X L H H H H L H H L H H H L H H L t t t t t H L L X X X X X X X X X H X X X L X H L a ... h X X X X X OAO aBO a b .. , °G OH L L QGO QHO h 9 H QAn QFn QGn L QAn QBn QCn QFn QGn QHn H QBn QCn QHn QAO QBO QGO QHO L = high level (steady state), L = low level (steady state) = irrelevant (any input, including transitions) transition from low to high level a ..• h = the level of steady-state input at inputs A thru H, respectively. 0AO, aBO, aGO, 0HO = the level of 0A, 0B, 0G, or 0H, respectively, before the indicated steady-state input conditions were established. 0An, 0Bn' etc. = the level of 0A, 0B, etc., respectively, before the most-recent t transition of the clock. = 87"1 7-338 TEXAS INSTRUMENTS . INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54199, SN74199 8-BIT SHIFT REGISTERS SN54199 ___ J OR W PACKAGE SN74199 ___ J OR N PACKAGE SN54199 and SN74199 These registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, a direct overriding clear line, and gated clock inputs_ The register has three modes of operation: V hop VIEW) INPUT F SHIfT/INPUT CC LOAD H OF I INPUT E Parallel (Broadside) Load Shift (In the direction OA toward 0H) Inhibit Clock (Do nothing) Parallel loading is accomplished by applying the eight bits of data and taking the shift/load control input low when the clock input is not inhibited_ The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input_ During loading, serial data flow is inhibited_ SERIAL ',NPUTS positive logic: see function table Shifting is accomplished synchronously when shift/load is high and the clock input is not inhibited_ Serial data for this mode is entered at the J-K inputs_ See the function table for levels required to enter serial data into the first flip-flop. Both of the clock inputs are identical in function and may be used interchangeably to serve as clock or clock-inhibit inputs. Holding either high inhibits clocking, but when one is held low, a clock input applied to the other input is passed to the eight flip-flops of the re~ister. The clock-inhibit input should be changed to the high level only while the clock input is high. These shift registers contain the equivalent of 79 TTL gates. Average power dissipation per gate is typically 4_55 mW. '199 FUNCTION TABLE INPUTS CLEAR H X SHIFTI CLOCK CLOCK OUTPUTS SERIAL PARALLEL --- LOAD INHIBIT J K A ... H QA QB Qc L X X X X X X L L L L H X L L X X X QAO QBO QCO H L L X X a. _. h a b c QHO h H H L L H X L L X H H X H H L H H L t t t t H H L t H L X QAO QAO QBn L QAn QBn H QAn QBn QAn QAn QBn H X H t X X X QAO QBO = high level = irrelevant QBO QH QGn • QGn QGn QGn QHO (steady state), L = low level (steady state) (any input, including transitions) t = transition from low to high level a ... h = the level of steady-state input at inputs A thru H, respectively. 0AO, 0BO, 0eo ... 0HO = the level of 0A, 0B, or 0e thru 0H, respectively, before the indicated steady-state input conditions were established. 0An, 0Bn ... 0Gn = the level of 0A or 0B thru 0G, respectively, before the most-recent t transition of the clock. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-339 TYPES SN54198, SN54199, SN74198, SN74199 8-BIT SHIFT REGISTERS functional block diagrams '198 CLOCK..!.1:..c"'--_-II>..., '199 SO---;::'--4-A 13 r-----H-_~~14) OA B IS) 16) OB C 17) 18) o Dc 19) 110) 00 EllS) 114) aE F 117) • 116) OF G 119) 118) OG H 121) SE~~~~~~~~~ -,,12~2)'--_ _ _ _+-Il......J -t-_ _ _ _---l CLEAR .:.;ll;.:::31_<\..)o--_ _ ~_ _ _ _ _ _-+~12~O) OH schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT V C C - - -....- - INPUT Clear, A thru H: Req = 6 kn. NOM All others: Req = 4 kn. NOM 1076 7-340 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54198, SN74198 8-BIT SHIFT REGISTERS SN54198, SN74198 typical clear, load, right-shift, left-shift, inhibit, and clear sequences • IJ: t!l a: r 1 c -g _a: :.:: U 9u 0 '" en a: ~ u a: « '-v-I oJ '" ~~~ ~c~ al u C t!l J: y oJ W j '" ««Ia:I-::J ~~~ g c w 0 0 y u. 0 ~u t!l 0 J: o I '"I~ I::J 0 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-341 I TYPES SN54199, SN74199 8-BIT SHIFT REGISTERS SN54199, SN74199 typical clear, shift, load, and inhibit sequences ------:r :r :r • ------------ __1 II: -~ ..J U :.: :.: ..J o..J g U u U II: ~ .., I:': U 1272 7-342 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54198, SN54199, SN74198, SN74199 8-BIT SHIFT REGISTERS REVISED AUGUST 1977 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V Supply voltage, Vcc (see Note 1) . . . . . . . Input voltage . . . . . . . . . . . . . . . Operating free·air temperature range: SN54' Circuits SN74' Circuits Storage temperature range 5.5 V -55°C to 125°C aOc to 7aoC -65°C to 15aoC NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54198 SN7419B SN54199 MIN Supply voltage, V CC 4.5 5 High-level output current, 10H MIN NOM MAX 4.75 5.5 5 -800 Low-level output current, 10L 5.25 V -800 V-A 16 0 UNIT SN74199 NOM MAX 25 0 16 mA 25 MHz Clock frequency, fclock Width of clock or clear pulse, tw (see Figure 1) 20 20 ns Mode-control setup time, tsu 30 30 ns Data setup time, tsu (see Figure 1) 20 20 ns 0 0 ns Hold time at any input, th (see Figure 1) -55 Operating free-air temperature, T A 0 125 °c 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74198 SN54198 MIN VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage TYP+ MAX 2 VOH High-level output voltage VCC = MIN, II =-12mA VCC= MIN, VIH=2V, VIL = 0.8 V, 10H = -800v- A VCC- MIN, VIH-2V, VIL = 0.8 V, 10L= 16mA 2.4 UNIT SN74199 SN54199 TEST CONDITIONSt PARAMETER MIN TYP~ MAX 2 V 0.8 0.8 V -1.5 -1.5 V 2.4 3.4 3.4 V VOL Low-level output voltage II Input current at maximum input voltage VCC - MAX, VI-5.5V 1 1 mA IIH High-level input current VCC = MAX, VI- 2.4 V 40 40 IlL Low-level input current VCC - MAX, VI - 0.4 V -1.6 -1.6 V-A mA lOS Short-circuit output current§ VCC - MAX -57 mA ICC Supply current VCC = MAX, See Table Below 127 mA 0.2 -20 0.4 -57 90 0.2 -18 127 90 0.4 V • tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ~AII typical values are at VCC = 5 V, T A = 25°C. Ii Not more than one output should be shorted at a time_ TEST CONDITIONS FOR ICC (ALL OUTPUTS ARE OPEN) TYPE APPLY4.5V FIRST GROUND, GROUND THEN APPLY 4.5 V SN54198, SN74198 Serial I nput, SO, Sl Clock Clear, Inputs A thru H SN54199, SN74199 J, K, Inputs A thru H Clock Clock inhibit, Clear, Shift/Load 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-343 TYPES SN54198, SN54199, SN74198, SN74199 8-BIT SHIFT REGISTERS switching characteristics, Vee =5 V, TA =25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency MIN TYP 25 35 Propagation delay time, high-totpHL low-level output from clear CL=15pF, Propagation delay time, high-totpHL RL = 400 Propagation delay time, low-totpLH MHz 23 35 ns 20 30 ns 17 26 ns n, See Figure 1 low-level output from clock MAX UNIT high-level output from clock PARAMETER MEASUREMENT INFORMATION SN54198, SN74198 SN54199, SN74199 TEST TABLE FOR SYNCHRONOUS INPUTS TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT • OUTPUT TESTED DATA INPUT (SEE NOTE E) FOR TEST 4.5 V 0A at tn+1 A OV 0A at tn+l 4.5V 4.5V Os at tn+1 S OV 0B at tn+l Sl SO A 4.5V S FOR TEST OUTPUT TESTED SHIFT/LOAD (SEE NOTE E) C 4.5V 4.5V 0c at tn+1 C OV 0cat tn+l D 4.5V 4.5V 0D at tn+1 D OV 0D attn+l E 4.5V 4.5 V 0E at tn+1 E OV 0E at tn+l F 4.5V 4.5 V OF at tn+1 F OV OF at tn+l G 4.5V 4.5V 0G at tn+1 G OV 0G at tn+l H 4.5V 4.5V 0H at tn+1 H OV 0H at t n +l L Serial Input 4.5V OV 0A at tn+8 4.5V 0H at tn+8 R Serial Input OV 4.5 V 0H at tn+8 R J and Ir--------------------~~5~ ..... tw(cl •• r) CLEAR INPUT ___ 3 V _ - - - OV OUTPUT tn VCC RL - 400 FROM ~~b~~T ~ (See Nota F) CLOCK INPUT - ...-MHH.....f-II..-...., ~ ' -_ _- , - - J DATA INPUT (SEE TEST _ _ _---: _ _ _ _ _...J , TABLE) LOAD FOR OUTPUT UNDER TEST tpHL -..l (clear-O) OUTPUT 0 ";": th "-- 0 V ~Sf'U-~3V (5 •• Note C) TEST ~ -~---3V I n tn 1.5V~1~V_ _ _ _ ov I r- --l tPHL,.- I --1 tPLH I.(CLK-O) (CLK'O)~~---VOH -------.\1.5 V 11.5 V 1.5V VOL VOLTAGE WAVEFORMS NOTES: A. The clock pulse has the following characteristics: tw(clock) ;;. 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tw(clear) ;;. 20 ns and thold = 0 ns. When testing f max , vary the clock PRR. B. C. D. E. F. CL includes probe and jig capacitance. All diodes are 1 N3064. A clear pulse is applied prior to each test. Propagation delay times (tpLH and tpHL) are measured at t n +1' Proper shifting of data is verified at t n +8 with a functional test. tn = bit time before clocking transition tn+1 = t n +8 = bit time bit time after one clocking transition after eight clocking transitions FIGURE 1 1076 7-344 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TTL MSI TYPES SN54S226, SN74S226 4-BIT PARALLEL LATCHED BUS TRANSCEIVERS BUl_L.ETIN NO_ DL.-S 12477, OCTOBER 1976-REVISED AUGUST 1979 SN54S226 ••• J PACKAGE SN74S226 ."•• J OR N PACKAGE (TOP VIEW) • Universal Transceivers for Implementing System Bus Controllers • Dual-Rank 4-Bit Transparent Latches Provide: - Exchange of Data Between 2 Buses In One Clock Pulse - Bus-to-Bus Isolation - Rapid Data Transfer - Full Storage Capability Vee STROBE GBA STROBE GAB S1 SEL I/O • Hysteresis at Data Inputs Enhances Noise Rejection f' Bj A2 BUSA • Separate Output-Control Inputs Provide Independent Enable/Disable for Either Bus Output S2SEL A3 A4 BUS B oeAB GND description I/O B3 B4 OeBA • 3-State Outputs Drive Bus Lines Directly B2 These high-performance Schottkyt TTL quadruple bus transceivers employ dual-rank bidirectional four-bit transparent latches and feature three-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The bus-management functions implemented and the high-impedance controls offered provide the designer with a controllerltransceiver that interfaces and drives system bus-organized lines directly. They are particularly attractive for implementing: Bidirectional bus transceivers Data-bus controllers The bus-management functions, under control of the function-select (S1, S2) inputs, provide complete data integrity for each of the four modes described in the function table. Directional transparency provides for routing data from or to either bus, and the dual store and dual readout capabilities can be used to perform the exchange of data between the two bus lines in the equivalent of a single clock pulse. Storage of data is accomplished by selecting the latch function, setting up the data, and taking the appropriate strobe input low. As long as the strobe is held high, the data is latched for the selected function. Further control is offered through the availability of independent output controls that can be used to enable or disable the outputs as shown in the output-control function table, regardless of the latch function in process. Store operations can be performed with the outputs disabled to a high impedance (Hi-Z). In the Hi-Z state the inputs/outputs neither load nor drive the bus lines significantly. The p-n-p inputs feature typically 400 millivolts of hysteresis to enhance noise rejection. • BUS-MANAGEMENT FUNCTION TABLE MODE CONTROLS STROBES GBA GAB Latch Trans X Latch Trans L H X Trans Latch Trans Trans L Trans Trans Lat!:h Latch L Trans Latch Read out stored data Read in both buses H H Latch Latch Latch Latch Store bus data L L X L H X L H H = high level L H L = low level X = irrelevant 1 OPERATION 2 S1 H B-TO-A LATCHES 1 S2 H A-TO-B LATCHES Trans 2 Trans Pass B to A Latch Trans Read out stored data Latch Trans Latch = latched Read out stored data Pass A to B Trans = transparent Copyright © 1979 by Texas Instruments Incorporated 879 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 tlntegrated SchottkY-Barrier diodeclamped transistor is patented by Texas Instruments. U.S. Patent Number 3,463,975. 7 345 • TYPES SN54S226, SN74S226 4-BIT PARALLEL LATCHED BUS TRANSCEIVERS logic symbol t S1 (2) S2 (14) functional block diagram (positive logic) O}M£ 1 3 OCBA A1 GAB A2 GBA OCAB OCBA tThls symbol Is In accordance with IEEE Std 91/ANSI Y32.14 and current discussions In IEC and IEEE. (15) (1) (9) (7) 1--i--i2D A-.:-+.-t-l C2 2DI-.-i--i I 10 C11---4--l-... C2 L _________________ _ \----------~V~--------~/ TO THREE OTHER TRANSCEIVERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage Off-state output voltage Operating free-air temperature range: SN54S226 (see Note 2) SN74S226 Stt>rage temperature range 7V .5.5V .5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTES: 1. Voltage values are with respect to network ground terminal. 2. An SN54S226 in th\J ,J package operating at temperatures above 113°C n.quires a heat-sink that provides a thermal resistance from case to free air, ReCA, of not more than 48°C/W. 1280 7-346 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54S226, SN74S226 4-BIT PARALLEL LATCHED BUS TRANSCEIVERS REVISED DECEMBER 1980 recommended operating conditions MIN SN54S226 NOM MAX 4.5 Supply voltage, VCC 5 SN74S226 UNIT NOM MAX 4.75 5 5.5 High-level output voltage, VOH High-level output current, 10H -6.5 Width of strobe pulse To Strobe Setup time, tsu To Select To Strobe To Select Hold time, th Operating free·air temperature, T A 5.5 MIN (see Note 2) V 5.5 V -10.3 30 30t 20 20t 30 Ot 0 -55 20 ot 0 125 5.25 mA ns ns ns 70 0 °c t The arrow Indicates that tha low-ta-hlgh transition of the strobe Input II used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH VIL VIK High-level input voltage VOH High-level output voltage VOL Low·level output voltage 10ZH 10ZL II SN54S226 SN74S226 IlL lOS Short-circuit output current§ Supply current Vcc" MIN, II =-18mA VIH = 2V, VIL - 0.8 V, 10H =MAX Vee" MIN, VIH = 2 V, VIL" 0.8 V, 10L= 15mA Vee= MAX, VIH"2V, Vo a 2.4 V 0.8 -1.2 2.4 2.4 3.3 2.9 Vee = MAX, VIH=2V, VO" 0.5 V Vee= MAX, VI" 5.5V Vee = MAX, VI = 2.7 V low-level voltage applied Input current at maximum input voltage High·level input current lee Vce = MIN, I I Off-state output current, high-level voltage applied Off-stata output current, Low-Ieval input current TYP:j: MAX UNIT 2 Low·level input voltage Input clamp voltage IIH MIN lOeAB,OeBA J All other inputs Vee = MAX, VI =0.5 V Vee" MAX Vce = MAX, See Note 3 -50 125 V V V V 0.5 V 100 IJA -250 IJA 1 mA 100 IJA -0.38 -1.6 -180 185 • mA mA mA t For condltlonl shown al MIN or MAX, use the appropriate value specified under recommendad operating conditions. :j:AII tYpical values are at VCC" 5 V, T A 25°C. § Not more than one output should be shorted at a time and duration of the short-circuit should ·not excaed one second. NOTES: 2. An SN54S226 In the J package operating at temperatures above 113° C requires a heat-sink that provides a thermal resistance from case to free air. ReCA. of not more than 48°CIW. 3. ICC Is measured with all Inputs (and outputs) grounded. & 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7·347 TYPES SN54S226, SN74S226 4-BIT PARALLEL LATCHED BUS TRANSCEIVERS switching characteristics, Vee = 5 V, TA = 25°e PARAMETER tPLH FROM TO (INPUT) (OUTPUT) A or B tPHL tPLH Select tpHL Strobe GBA tPLH tpHL orGAB tpZH Output Control tpZL OCBA or OCAB tpHZ Output Control tpLZ OCBA or OCAB TEST CONDITIONS MIN TYP MAX 20 30 B or A Any CL = 50 pF, A or B RL= 280n, See Note 4 A or B CL=5pF, AorB RL=280n, See Note 4 15 30 25 37 UNIT ns ns 19 30 25 37 19 30 12 20 12 20 10 15 10 15 ns ns ns tPLH = propagation delay time, iow-to-high-Ievel output tPH L = propagation delay time, high-to-Iow level tpZH tpZL tPHZ tpLZ = output enable time to high level = output enable time to low level =output disable time from high level = output disable time from low level NOTE 4: Load circuits and voltage waveforms are shown on page 3-11_ applications The following examples demonstrate four fundamental bus-management functions that can be performed with the 'S226. Exchange of data on the two bus lines can be accomplished with a single high-to-Iow transition at S2 when S1 is high . • 'S226 'S226 ~ "------v---J CONTROL BUS B ... BUSA CONTROL BUSA . . BUSB 'S226 'S226 L-y-J '-.(----J CONTROL READOUT A AND B CONTROL STORE A AND/OR B - - - - - - - VIH VIL CONTROL {S2 S1 ______________________________________ VIH ~ - - - - - - - - - - - - - - - - - - VIL 1280 7-348 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SNS4LS24S, SN74LS24S OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS TTL MSI BULLETIN NO. DL·S 12471, OCTOBER 1976-REVISED FEBRUARY 1979 oBi-directional Bus Transceiver in a High-Density 20-Pin Package SN54LS245 • , • J PACKAGE SN74LS245 ••• J OR N PACKAGE (TOP VIEW) o 3-State Outputs Drive Bus Lines Directly o P-N-P Inputs Reduce D-C Loading on Bus Lines ENABLE Vee o Hysteresis at Bus Inputs Improve Noise Margins o Typical Propagation Delay Times, Port-to-Port ... 8 ns • Typical Enable/Disable Times ... 17 ns TYPE IOL (SINK IOH (SOURCE CURRENT) CURRENT) SN54LS245 12mA -12mA SN74LS245 24mA -15mA G B1 B2 B3 B4 B5 B6 B7 B8 A5 AS A7 A8 GND positive logic: see function table description These octal bus transceivers are designed for asynchronous two·way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DI R) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated. The SN54LS245 is characterized for operation over the full military temperature range of _55°C to 125°e. The o SN74LS245 is characterized for operation from O°C to 70 e. schematics of inputs and outputs EQUIVALENT OF EACH INPUT VCCftf--- FUNCTION TABLE TYPICAL OF ALL OUTPUTS ENABLE ---~-VCC G 9 kn NOM INPUT OUTPUT H DIRECTION CONTROL OPERATION DIR L L B data to A bus L H A data to B bus H X = high level, L = low level, Isolation X = irrelevant absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ............................................ . . . . . . . 7V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°e to 125°e Operating free-air temperature range: SN54LS' 0 SN74LS' .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .. O°C to 70 e 0 Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. Copyright © 1979 by Texas Instruments Incorporated 279 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 '7·349 • TYPES SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS REVISED FEBRUARY 1979 recommended operating conditions SN54LS245 PARAMETER Supply voltage, Vee MIN NOM 4.5 5 SN74LS245 MIN NOM MAX 5.5 4.75 5 5.25 V -15 mA 24 mA 70 °e High-level output current, 10H -12 Low-level output current, 10L 12 Operating free-air temperature, TA UNIT MAX -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage Vee = MIN, Hysteresis (VT+ - VT_~A or B input Vee = MIN VOL High-level output voltage II Low-level output voltage • MIN TYPt MAX 2 V 0.8 V -1.5 -1.5 V 0.2 0.4 0.2 0.4 2.4 3.4 2.4 3.4 V V Vee = MIN, IOL=12mA Off-state output current, G at2V low-level voltage applied I AorB I DIR or G Vee = MAX, UNIT 0.7 2 2 0.4 0.4 V VIH = 2V, Vee = MAX, I nput current at 10H = -3 mA 10H = MAX high-level voltage applied maximum input voltage SN74LS245 MAX VIH=2V, Off-state output current, 10ZL TYPt II = -18 mA VIL = VIL max VIL = VIL max 10ZH MIN 2 Vee = MIN, VOH SN54LS245 TEST eONDITIONSt IOL=24mA 0.5 VO=2.7V 20 20 Vo = 0.4 V -200 -200 VI - 5.5 V 0.1 0.1 VI = 7 V 0.1 0.1 /J.A mA IIH High-level input current Vee = MAX, VIH = 2.7 V 20 20 /J.A IlL Low-level input current Vee - MAX, VIL = 0.4 V -0.2 -0.2 mA lOS Short-circuit output current~ Vee = MAX -225 mA ICC Supply current I Total, outputs low I Outputs at Hi-Z -225 -40 I Total, outputs high 48 Vee= MAX, Outputs open -40 70 48 70 62 90 62 90 64 95 64 95 TYP MAX S 12 ns mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at Vee = 5 V, TA = 25°e. 11 Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, T A = 25 0 C TEST CONDITIONS PARAMETER Propagation delay time, tPLH low-tcrhigh-Ievel output Propagation delay time, n, 8 12 ns tPZL 27 40 ns tpZH Output enable time to high level 25 40 ns tPLZ Output disable time from low level 15 25 ns tpHZ Output disable time from high level 15 25 ns high-tcrlow-Ievel output eL=5pF, RL = 667 RL = 667 n, See Note 2 UNIT Output enable time to low level tpHL eL=45pF, MIN See Note 2 NOTE 2: Load circuit and waveforms are shown on page 1-15. TEXAS INSTRUMENTS 7-350 INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 279 TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249, SN74246 THRU SN74249, SN74LS247THRU SN74LS249 BCD-TO- SEVEN-SEGMENT DECODERS/DRJVE~S TTL MSI BULLETIN NO. DL-S 7612078, MARCH 1974- REVISED OCTOBER 1976 '246, '247, 'LS247 feature '248, 'LS248 feature '249, 'LS249 feature • Open-Collector Outputs Drive Indicators Directly • Internal Pull-Ups Eliminate Need for External Resistors • • Lamp-Test Provision • Lamp-Test Provision Leading/Trailing Zero Suppression • Leading/Trailing Zero Suppression • • • • Open-Collector Outputs Lamp-Test Provision Leading/Trailing Zero Suppression All Circuit Types Feature Lamp Intensity Modulation Capability DRIVER OUTPUTS TYPICAL ACTIVE OUTPUT SINK MAX POWER LEVEL CONFIGURATION CURRENT VOLTAGE DISSIPATION SN54246 low open-collector 40mA 30V 320mW J,W SN54247 low open-collector 40mA 15V 320mW J,W SN54248 high 2-kn. pull-up 6,4 rnA 5.5V 265mW J,W SN54249 high open-collector 10mA 5.5V 265mW J,W SN54LS247 low open-collector 12mA 15V 35mW J,W SN54LS248 high 2-kn. pull-up 2mA 5.5 V 125mW J,W SN54LS249 high open-collector 4mA 5.5 V 40mW J,W SN74246 low open-collector 40 rnA 30V 320mW J, N J, N TYPE PACKAGES SN74247 low open-collector 40mA 15V 320mW SN74248 high 2-kn. pull-up 6,4 rnA 5.5 V 265mW J, N SN74249 high open-collector 10mA 5.5 V 265mW J, N J, N SN74LS247 low open-collector 24 rnA 15V 35mW SN74LS248 high 2-kn. pull-up 6mA 5.5V 125mW J, N SN74LS249 high open-collector 8mA 5.5V 40mW J, N '246, '247, 'LS247 '248, '249, 'LS248, 'LS249 (TOP VIEW) (TOP VIEW) II I LAMP RS RB TEST ~~~ ~~T LAMP TEST AS OUT PUT .. ~ ~ PUT INPUTS positive logic: see function tables description The '246 through '248 are electrically and functionally identical to the SN5446A/SN7446A, SN5447A/SN7447A, and SN5448/SN7448, respectively, and have the same pin assignments as their equivalents. Also the 'LS247 and 'LS248 are electrically and functionally identical to the SN54LS47/SN74LS47 and SN54LS48/SN74LS48, respectively, and have the same pin assignments as their equivalents. They can be used interchangeably in present or future designs to offer designers a choice between two indicator fonts. The '249 and 'LS249 are 16-pin versions of the 14-pin SN5449 and SN54LS49/SN74LS49, respectively. Included in the '249 and 'LS249 circuits is the full functional capability for lamp test and ripple blanking, which is not available in the '49 and 'LS49 circuits. The '46A, '47A, '4-8, '49, 'LS47, 'LS48, and 'LS49 compose the b and the '=t without tails and the '246 through '249 and 'LS247, 'LS248, and 'LS249 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·351 TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249, SN74246 THRU SN74249, SN74LS247 THRU SN74LS249 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS description (continued) compose the 5 and the '9 with tails. Composition of all other characters, including display patterns for BCD inputs above nine, is identical. The '246, '247, and 'LS247 feature active-low outputs designed for driving indicators directly, and the '248, '249, 'LS248, and 'LS249 feature active-high outputs for driving lamp buffers. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions. All of these circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI and RBO). Lamp test (L T) of these types may be performed at any time when the BI/RBO node is at a high level. All types contain an overriding blanking input (B I) which can be used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for use with TTL or DTL logic outputs. Series 54 and Series 54LS devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and Series 74LS devices are characterized for operation from aOc to 70°C. fl-:-Ib el-Ie -d- NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS SEGMENT IDENTIFICATION '246, '247, 'LS247 FUNCTION TABLE DECIMAL INPUTS OR • OUTPUTS BI/RBOt a FUNCTION LT RBI D C B A 0 H H L L L L H 1 H L L L H H 2 H X X L L H L H 3 4 H X L L H H H X L H L 5 H X L H L 6 H X L H H 7 H X L H H NOTE f 9 ON ON OFF OFF OFF OFF b c ON ON ON ON OFF ON ON OFF ON ON OFF ON ON OFF ON H ON ON ON ON OFF OFF ON L H OFF ON ON OFF OFF ON ON H H ON OFF ON ON OFF ON ON L H ON OFF ON ON ON ON ON H H ON ON ON OFF OFF OFF OFF d e 8 H X H L L L H ON ON ON ON ON ON ON 9 H X H L L H H ON ON ON ON OFF ON ON 10 H X H L H L H OFF OFF OFF ON ON OFF ON 11 H X H L H H H OFF OFF ON ON OFF OFF ON 12 H X H H L L H OFF ON OFF OFF OFF ON ON 13 H X H H L H H ON OFF OFF ON OFF ON ON 14 H X H H H L H OFF OFF OFF ON ON ON ON 15 H X H H H H H OFF OFF OFF OFF OFF OFF OFF 1 BI X X X X X X L OFF OFF OFF OFF OFF OFF OFF 2 RBI H L L L L L L OFF OFF OFF OFF OFF OFF OFF 3 LT L X X X X X H ON ON ON ON ON ON ON 4 H = high level, L = low level, X = irrelevant NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired. 2. When a low logic level is applied directly to the blanking input (BI). all segment outputs are off regardless of the level of any other input. 3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs go off and the ripple-blanking output (RBO) goes to a low level (response condition). 4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all segment outputs are on. tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). 374 7-352 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249, SN74246 THRU SN74249, SN74LS247 THRU SN74LS249 BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS '248, '249, 'LS248, 'LS249 FUNCTION TABLE DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT INPUTS LT H H H H H H H H H H H H H H H H X H L RBI D L L L L L L L L C L L L L H X X X X X X X X X X X X X X X X H H H H H H H H X H H H H X L L X X H H H H L L L L OUTPUTS BI/RBOt B L L A L H H L H L L H H H H H L L L L L H H H H L L H H H X H X L L X X L L a H H H H H H H H H H H H H H H H H L H H L H H H H H L L L H H H H H H L L H H H L L H L L L L L L L L L L L L X H H H L c H H L H H H H H H H L H L L L L L L H b d H L H H L H H L H H H H L H H L L L H e H L H L L L H L H L H L L L H L L L H NOTE f H L L L H H H L H H L L H H H l L L H Jl L L H H H H H L H H H H H H H L L L H 1 1 1 2 3 4 H = high level, L = low level. X = irrelevant NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired. 2. When a low logic level is applied directly to the blanking inp~t (BI), all segment outputs are low regardless of the level of any other input. 3. When ripple-blanking input (R BI) and inputs A, B. C, and D are at a low level with the lamp test input high, all segment outputs go low and the ripple-blanking output (RBO) goes to a low level (response condition). 4. When the blanking input/ripple-blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all segment outputs are high. tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). '248, '249, 'LS248, 'LS249 '246, '247, 'LS247 • I INPUTc::I6I'--i:-t.>o--tt--t1tttttt::=::. BLANKING R'PP~i:~l:~~~'NG~"'-'-j--~ 374 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-353 TYPES SN54246 THRU SN54249, SN74246 THRU SN74249 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS schematics of inputs and outputs '246, '247, '248, '249 '246, '247, '248, '249 Q EQUIVALENT OF EACH INPUT EXCEPT BI/RBO vee EQUIVALENT OF BI/RBO Vee 6 k!l NOM INPUT 2.4 k!l 6 k!l NOM' NOM -- '246, '247 '248 TYPICAL OF OUTPUTS a THRU 9 TYPICAL OF OUTPUTS a THRU 9 ----------~~~----vee -----------.----~-vee OUTPUT 2k!l NOM • OUTPUT '249 TYPICAL OF ALL OUTPUTS -----------.-----vee OUTPUT 374 7·354 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS247 THRU SN54LS249, SN74LS247 THRU SN74LS249 BCO-TO-SEVEN-SEGMENT DECODERS/DRIVERS schematics of inputs and outputs 'LS247, 'LS248, 'LS249 'LS247, 'LS248, 'LS249 - EQUIVALENT OF BI/RBO EQUIVALENT OF EACH INPUT EXCEPT BI/RBO q vee Req INPUT L T and RBI: A, B, e, and 0: Req Req Vee -- = 20 kn = 25 kn NOM NOM 'LS247 'LS248 TYPICAL OF OUTPUTS a THRU 9 TYPICAL OF OUTPUTS a THRU 9 ----------~~---------vee ----------~~--~~vee 2kn NOM OUTPUT OUTPUT I 'LS249 TYPICAL OF OUTPUTS a THRU 9 -----------.-----vee OUTPUT 374 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·355 TYPES SN54246, SN54247, SN74246, SN74247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS REVISED MARCH 1974 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vce (see Note 1) . . . . . Input voltage . . . . . . . . . . . . . Current forced into any output in the off state Operating free-air temperature range: SN54246, SN54247 SN74246, SN74247 Storage temperature range 7V 5.5V 1 mA -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54247 SN54246 MIN Supply voltage, Vee 4.5 NOM MAX 5 MIN 5.5 SN74246 NOM MAX 4.5 5 5.5 MIN 4.75 SN74247 NOM MAX MIN 5.25 4.75 5 NOM MAX 5 5.25 UNIT V Off-state output voltage, VO(off) a thru g 30 15 30 15 V On-state output current, 10(on) a thru g 40 40 40 40 rnA High-level output current, 10H BI/RBO -200 -200 -200 -200 /JA Low-level output current, 10L BI/RBO 8 8 8 8 rnA 70 °e Operating free·air temperature, T A -55 125 -55 125 0 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL 10(0ff) VO(on) I MIN TVP+ MAX UNIT 2 BI/RBO Low-level output voltage BI/RBO Off-state output current a thru g On-state output voltage a thru g II Input current at maximum input voltage IIH High-level input current Any input except BI/RBO Any input except BI/RBO Vee = MIN, 11= -12 rnA Vee= MIN, VIH = 2V, VIL = 0.8 V, 10H = -200/JA Vee- MIN, VIH - 2 V, VIL = 0.8 V, 10L = 8mA 2.4 V VO(off) = MAX Vee= MIN, VIH = 2V, VIL =-0.8 V, 10(on) = 40 rnA 0.27 0.3 Low-level input current Short-circuit output current Supply current 0.4 V 250 /JA 0.4 V rnA Vee = MAX, VI = 2.4 V 40 /JA -1.6 except BI/RBO Vee = MAX, VI = 0.4 V BI/RBO V 1 BI/RBO lOS ICC V Vee = MAX, VI = 5.5V Any input IlL V 1.5V 3.7 Vee - MAX, VIH - 2 V, VIL = 0.8 V, 0.8 rnA -4 Vee= MAX Vee=MAX, See Note 2 64 -4 rnA 103 rnA tFor CO~ditions shown as MIN or MAX, use othe appropriate value specified under recommended operating conditions. +AII typIcal values are at VCC = 5 V, T A = 25 C. NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V. switching characteristics, Vee = 5 V, T A = 25° e TEST CONDITIONS PARAMETER MIN TVP MAX UNIT 100 toft Turn-off time from A input ton Turn-on time from A input eL=15pF, toff Turn-off time from RBI input See Note 3 ton Turn-on time from RBI input RL = 120.n, 100 100 100 ns ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toff corresponds to tpLH and ton corresponds to tpHL' 1280 7-356 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS247, SN74LS247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) . . . . . . . Input voltage . . . . . . . . . . . . . . . Peak output current (tw < 1 ms, duty cycle < 10%) Current forced into any output in the off state Operating free·air temperature range: SN54LS247 SN74LS247 Storage temperature range 7V 7V 200mA . . . . " 1 mA -55°C to 125°C . O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54 LS247 MIN 4.5 Supply Voltage, Vee Off-state output voltage, VO(off) a thru g NOM SN74LS247 MAX MIN NOM 5.5 4.75 5 5 MAX 15 UNIT 5.25 V 15 V rnA On-state output current, 10(on) a thru g 12 24 High-level output current, 10H BI/RBO -50 -50 /-lA Low-level output current, 10L BI/RBO 1.6 3.2 rnA 70 "e Operating free-air temperature, T A -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH SN54LS247 TEST eONDITIONSt PARAMETER MIN 10(0ft) High·level output voltage BI/RBO Vee - MIN, II - -18 rnA Vee = MIN, VIH -2V, 2.4 VIL = VIL max, 10H = -50/-lA Low-level output voltage Off-state output current Vee = MAX, a thru g On-state output voltage Input current at maximum input voltage Vee = MAX, VI = 7 V High·level input current Vee - MAX, VI = 2.7 V IlL Low-level input current except BI/RBO Vee = MAX, VI=O.4V 0.25 BI/RBO Short-circuit ICC output current BI/RBO Vee= MAX, -1.5 -1.5 V 2.4 0.4 4.2 V 0.25 0.4 0.35 0.5 250 0.4 0.25 0.4 0.35 0.5 /-lA See Note 2 0.1 0.1 rnA 20 20 jJA -0.4 -0.4 -1.2 -1.2 -2 -0.3 Vee = MAX Supply current V V V Any input lOS UNIT 0.8 250 110(on) = 12 rnA VIH = 2 V, VIL = VIL max 110(on) = 24 rnA II MAX V VIH=2V, IIH TYP+ 0.7 4.2 VIL = VIL max, VO(off) = 15 V a thru g MIN 2 0.25 Ii0L = 1.6mA VIH =2 V, VIL = VIL max /IOL = 3.2 rnA BI/RBO Vee - MIN, VO(on) SN74 LS247 MAX 2 Vee = MIN, VOL TYP+ 7 -0.3 7 13 • rnA -2 rnA 13 rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v. switching characteristics, Vee = 5 V, T A = 25° C TEST CONDITIONS PARAMETER MIN TYP MAX UNIT toft Turn-off time from A input ton Turn-on time from A input eL=15pF, RL = 665.n, 100 toft Turn-off time from RBI input See Note 4 100 ton Turn-on time from RBI input 100 100 ns ns NOTE 4: Load circuit and voltage waveforms are shown on page 3-11; toff corresponds to tpLH and ton corresponds to tpH L. 12BO TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-357 TYPES SN54248, SN74248 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS REVISED MARCH 1974 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) .... . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54248 SN74248 Storage temperature range 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminals. recommended operating conditions SN54248 MIN 4.5 Supply voltage, Vee High-level output current, 10H Low-level output current, 10L SN74248 NOM MAX MIN 5.5 4.75 5 NOM MAX 5 5.25 a thru g -400 -400 BI/RBO -200 -200 a thru g 6.4 6.4 BI/RBO Operating free-air temperature, T A 8 -55 8 125 0 70 UNIT V /.I.A mA °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH • VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current V Vee = MIN, II = -12 mA a thru g Vee = MIN, VIH=2V, 2.4 4.2 BI/RBO VIL = 0.8 V, 10H = MAX 2.4 3.7 Vee = MIN, Vo = 0.85 V, -1.3 -2 a thru g Output current TYP+ MAX UNIT 2 High-level output voltage 10 MIN Input conditions as for VOH Any input except BI/RBO Any input except BI/RBO lOS Short-circuit output current Supply current V V mA VIH-2V, 10L = MAX Vee = MAX, VI = 5.5 V 1 mA Vee = MAX, VI = 2.4 V 40 /.I.A 0.27 0.4 -1.6 VI = 0.4 V V mA -4 BI/RBO lee -1.5 VIL = 0.8 V, except BI/RBO Vee = MAX, Low-level input current V Vee = MIN, Any input IlL 0.8 BI/RBO Vee = MAX .. .. Vee - MAX, See Note 2 . . 53 -4 mA 90 mA tFor condItIons shown as MIN or MAX. use the approproate value specIfIed under recommended operatong condItIons • +AII typical values are at VCC = 5 V, T A = 25°C. NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS tpHL Propagation delay time, high-to-Iow-Ievel output from A input tpLH Propagation delay time, low-to-high-Ievel output from A input eL=15pF, tpHL Propagation delay time, high-to-Iow-Ievel output from RBI input See Note 5 tpLH Propagation delay time,low-to-high-level output from RBI input MIN TYP MAX UNIT 100 RL = 1 kn, 100 100 100 ns ns NOTE 5. Load CirCUIt and voltage waveforms are shown on page 3-10. 1076 7-358 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS248, SN74LS248 BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS248 SN74LS248 Storage temperature range 7V .. " 7V -55°C to 125°C . oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS248 MIN 4.5 Supply voltage, Vee High-level output current, 10H Low-level output current, 10L NOM SN74LS248 MAX MIN NOM 5.5 4.75 5 5 MAX 5.25 a thru g -100 -100 BI/RBO -50 -50 a thru g 2 6 BI/RBO 1.6 3.2 Operating free-air temperature, T A 125 -55 70 0 UNIT V p.A mA °e electrical characteristics over recommended operatmg free-air temperature range (unless otherwise noted) VIH High·level input voltage VIL Low·level input voltage VIK I nput clamp voltage VOH 10 High-level output voltage Output current Vee = MIN, 11=-18mA a thru g and Vee- MIN, VIH=2V, BI/RBO VIL = VIL max, 10H = MAX Vee= MIN, a thru g Va = 0.85 V, Input conditions as for VOH Vee = MIN, Any input except BI/BRO Short-circuit ICC output current V 0.7 0.8 V -1.5 -1.5 V 2.4 4.2 V -1.3 -2 -1.3 -2 mA 0.25 0.25 10L = 1.6 mA 0.4 0.4 0.25 0.4 0.35 0.5 0.25 0.4 0.35 0.5 V 10L =3.2 mA Vee = MAX, VI =7 V Vee = MAX, VI = 2.7 V except BI/RBO Vee = MAX, BI/RBO VI = 0.4V Any input except BI/RBO BI/RBO -0.3 Vee = MAX Supply current Vee = MAX, UNIT 4.2 Any input lOS MAX VIH=2V, maximum input voltage Low-level input current TYP:t: 2 V Vee - MIN, Input current at IlL MIN 10L =6mA VIL = VIL max High-level input current SN74LS248 MAX 2.4 10L = 2 mA VIL = VIL max Low-level output voltage IIH TYP:t: VIH = 2V, BI/RBO II MIN 2 a thru g VOL SN54LS248 TEST eONDITloNst PARAMETER See Note 2 0.1 0.1 mA 20 20 p.A -0.4 -0.4 -1.2 -1.2 -2 25 -0.3 25 38 • I mA -2 mA 38 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :t:AII typical values are at V CC = 5 V, T A 25° C. NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER TEST CONDITIONS MIN TVP MAX tpHL Propagation delay time, high-to-Iow-Ievel output from A input eL=15pF, RL =4 kn, 100 tPLH Propagation delay time, low-to-high-Ievel output from A input See Note 6 100 tpHL Propagation delay time, high-to-Iow-Ievel output from RBI input eL-15pF, RL=6kn, 100 tpLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100 UNIT ns ns NOTE 6: Load circuit and voltage waveforms are shown on page 3·11. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-359 TYPES SN54249, SN74249 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) .... . Input voltage . . . . . . . . . . . . . Current forced into any output in the off state Operating free-air temperature range: SN54249 SN74249 Storage temperature range 7V 5.5 V 1 mA -55°C to 125°C O°C to 70°C _65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54249 MIN Supply voltage, Vee 4.5 MIN 5.5 4.75 5 Low-level output current, IOL NOM MAX UNIT 5.25 V IBI/RBO 5.5 5.5 V -200 -200 I a thru g 10 10 High-level output voltage, VOH High·level output current, IOH SN74249 NOM MAX I BI/RBO Operating free-air temperature, T A 5 8 -55 125 8 0 70 /JA mA °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL VIK Low-level input voltage • High-level output voltage IOH High-level output current VOL Low-level output voltage TYPt MAX UNIT 2 Input clamp voltage VOH MIN BI/RBO a thru g II Input current at maximum input voltage IIH High-level input current Any input except BI/RBO Any input except BI/RBO Vee = MIN, 11- -12 mA Vee = MIN, VIH = 2 V, 2.4 V Low-level input current except BI/RBO Short-circuit output current lOS Supply current .. conditions BI/RBO V 3.7 V IOH = MAX Vee= MIN, VIH = 2V, VIL = 0.8 V, VOH = 5.5 V Vee= MIN, VIH = 2V, VIL = 0.8 V, 10L = MAX Vee = MAX, VI=5.5V 1 mA Vee = MAX, VI = 2.4 V 40 /JA 0.27 250 /JA 0.4 V -1.6 Vee = MAX, VI = 0.4 V BI/RBO lee V -1.5 VIL = 0.8 V, Any input IlL 0.8 mA -4 Vee = MAX Vee = MAX, See Note 2 .. or MAX, use the appropriate value speCified under recommended operating conditions . 53 -4 mA 90 mA tFor shown as MIN tAli typical values are at VCC = 5 V, TA = 25°C. NOTE 2: ICC is measured with all outputs open and all inpIJts at 4.5 V. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS tpHL Propagation delay time, high-to-Iow·level output from A input tpLH Propagation delay time, low-to-high-Ievel output from A input CL=15pF, tpHL Propagation delay time, high-to-Iow·level output from RBI input See Note 5 tpLH Propagation delay time, low-to-high·level output from RBI input MIN TYP MAX UNIT 100 RL=6670, 100 100 100 ns ns NOTE 5: Load CirCUit and voltage waveforms are shown on page 3·10. 1280 7-360 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS249, SN74LS249 BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 7V . . . . 1 mA -55°C to 125°C . aOc to 7aoC -65°C to 15aoC Supply voltage, Vcc (see Note 1) Input voltage . . . . . . . . . . . . . . Current forced into any output in the offstate Operating free-air temperature range: SN54LS249 SN74LS249 Storage temperature range NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54 LS249 MIN 4.5 Supply voltage, VCC NOM SN74LS249 MAX MIN NOM 5.5 4.75 5 5 MAX 5.25 UNIT V High-level output voltage, VOH a thru g 5.5 5.5 V High-level output current, IOH BI/RBO -50 -50 JlA Low-level output current, IOL a thru g 4 8 BI/RBO 1.6 3.2 Operating free-air temperature, T A -55 125 0 70 rnA °c electncal characterIStics over recommended operatmg free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage BI/RBO IOH High-level output current a thru g VCC = MIN, II = -18 rnA Vee = MIN, VIH=2V, VIL = VIL max, IOH = -50 JlA Vee = MIN, 2.4 0.25 Input current at Any input except BI/RBO Short-circuit lec V -1.5 -1.5 V 2.4 4.2 V 250 0.4 0.25 0.4 0.35 0.5 JlA V 0.25 IOL = 4 rnA 0.4 0.25 0.4 0.35 0.5 V IOL = 8 rnA Vee = MAX, VI = 7V 0.1 0.1 rnA Vee = MAX, VI = 2.7 V 20 20 JlA except BI/RBO Vee = MAX, VI = 0.4 V II Any input except BI/RBO BI/RBO output current V VIH=2V, maximum input voltage UNIT 0.8 4.2 Any input lOS MAX 0.7 IOL = 3.2 rnA Vce = MIN, Low-level input current TYP+ 250 IOL = 1.6 rnA VIL = VIL max IlL MIN 2 VIH = 2 V, VIL = VIL max Low-level output voltage High-level input current SN74LS249 MAX VIH = 2 V, a thru g IIH TYP+ VIL = VIL max, VOH = 5.5 V BI/RBO II MIN 2 Vee = MIN, VOL SN54LS249 TEST CONDITIONSt BI/RBO -0.3 Vee = MAX Supply current Vce= MAX, See Note 2 -0.4 -0.4 -1.2 -1.2 -2 8 -0.3 15 8 rnA -2 rnA 15 rnA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vce = 5 V, TA = 25°e. NOTE 2: lee is measured with all outputs open and inputs at 4.5 V. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER TEST CONDITIONS MIN TYP MAX tpHL Propagation delay time, high-to-Iow-Ievel output from A input CL=15pF, RL=2kn, 100 tPLH Propagation delay time, low-to-high-Ievel output from A input See Note 6 100 tPHL Propagation delay time, high-to-Iow-Ievel output from RBI input CL - 15pF, RL = 6 kn, 100 tPLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100 UNIT ns ns NOTE 6: Load circuit and voltage waveforms are shown on page 3·11. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·361 TYPES Sr~54251, Sr~54LS251, SN54S251, SN74251, SN74LS251 (TIM9905). SN74S251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS TTL MSI BULLETIN NO. DL-S 7611 • Three-State Versions of '151, 'LS151, 'S151 • Three-State Outputs Interface Directly with System Bus • Perform Parallel-to-Serial Conversion • Permit Multiplexing from N-lines to One Line • Complementary Outputs Provide True and Inverted Data • Fully Compatible with Most TTL and DTL Circuits DECEMBER 1972-REVISED OCTOBER 1976 SN54251, SN54LS251, SN54S251 ••• J OR W PACKAGE SN74251, SN74LS251, SN54S251 ••• J OR N PACKAGE (TOP VIEW) ~~STROBE OAT A INPUTS MAX NO. TYPICAL AVG PROP OF COMMON DELAY TIME POWER OUTPUTS (OTOY) DISSIPATION SN54251 49 17 ns 250mW SN74251 TYPE TYPICAL functional block diagram 129 17 ns 250mW SN54LS251 49 17 ns 35mW STROBE...!',,-" SN74LS251 129 17 ns 35mW DO 141 SN54S251 39 8 ns 275mW 01 <31 SN74S251 129 8 ns 275mW 02 m ---,D----""""T----;---, description 04 These monolithic data selectors/multiplexers contain full on-chip binary decoding to select one-of-eight data sources and feature a strobe·controlled threestate output. The strobe must be at a low logic level to enable these devices. The three-state outputs permit a number of outputs to be connected to a common bus. When the strobe input is high, both outputs are in a high-impedance state in which both the upper and lower transistors of each totem-pole output are off, and the output neither drives nor loads the bus significantly. When the strobe is low, the outputs are activated and operate as standard TTL totem-pole outputs. I OUTPUTS positive logic: see function table 1151 D6 1131 07 021 FUNCTION TABLE INPUTS SELECT To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the 'average output disable time is shorter than the average output enable time. The SN54251 and SN74251 have output clamp diodes to attenuate reflections on the bus line. OUTPUTS STROBE Y C B A S X x X H Z L L L L DO L L H L 01 L H H L L 02 H L 03 L L L 04 L H L 05 H H L L 06 H L 07 L H H H H W Z DO 01 52 03 04 55 06 07 H = high logic level, L = low logic level X = irrelevant, Z = high impedance (off) DO. D1 ... D7 = the level of the respective D input 1076 7-362 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222 TYPES SN54251. SN74251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Off-state output voltage Operating free-air temperature range: SN54251 SN74251 Storage temperature range 7V 5.5V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54251 MIN Supply voltage, Vee NOM 4.5 5 SN74251 MAX MIN 5.5 4.75 NOM 5 -2 High-level output current, 10H 16 Low-level output current, 10L -55 Operating free-air temperature, T A 125 0 MAX UNIT 5.25 V -5.2 mA 16 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH VOL 10Z TEST eONDITIONSt MIN TYP+ MAX UNIT V 2 0.8 High-level output voltage Low-level output voltage Vee~ MIN, II Vee~ MIN, VIH=2V, 10H = MAX Vee~ VIH=2V, MIN, Vee~ VIH ~ Vee~ -1.5 -12mA VIL = 0.8 V, VIL = 0.8 V. Off·state (high-impedance-statel output current ~ 2.4 Vo ~ 2.4 V 2V VO~ 0.4 V MAX, 10=-12mA V V 3.2 0.2 10L = 16 mA MAX, V 0.4 40 -40 -1.5 V /lA Vo Output clamp voltage II Input current at maximum input voltage Vee = MAX, VI = 5.5 V IIH High-level input current Vee - MAX, VI- 2.4 V 40 /lA IlL Low-level input current Vee- MAX, VI - 0.4 V -1.6 mA lOS Short-circuit output current!i Vee = MAX -55 mA ICC Supply current 62 mA VIH ~ 4.5 V Vee = MAX, Vee+ 1. 5 10=12mA 1 -18 All inputs at 4.5 V, All outputs open 38 V mA • t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at V CC ~ 5 V, T A ~ 25°C. §Not more than one output should be shorted at a time. 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-363 TYPES SN54251, SN14251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS switching characteristics, Vee PARAMETERlI =5 V, TA =25°e FROM TO (INPUT) (OUTPUT) tpLH A, B, orC tpHL (4 levels) tPLH A,B,orC tpHL (3 levels) tPLH TEST CONDITIONS MIN Y W Any 0 Y CL = 50pF, tpHL RL =400 n, tpLH Any D W Strobe Y See Note 2 tpHL TYP MAX UNIT 29 45 28 45 20 33 21 33 17 28 18 28 10 15 9 15 17 27 tZL 26 40 tZH 17 27 24 40 tZH Strobe W Strobe Y tZL tHZ CL = 5 pF, tLZ RL=400n, tHZ Strobe See Note 2 W tLZ 5 8 15 23 5 8 15 23 ns ns ns ns ns ns ns ns 11 tpLH == Propagation delay time, low-to-high-Ievel output tpH L == Propagation delay time, high-to-Iow-Ievel output tZH == Output enable time to high level tZL == Output enable time to low level tHZ == Output disable time from high level tLZ == Output disable time from low level NOTE 2: See load circuits and waveforms on page 3-10_ schematics of inputs and outputs • EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS ------------e-~._ Vee-------4------ 100 n Vee NOM INPUT OUTPUT Select: Req = 6 kn NOM Other inputs: Req = 4 kn NOM 1272 7-364 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS251, SN74LS251 (TIM9905) DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Off-state output voltage Operating free-air temperature range: SN54LS251 SN74LS251 Storage temperature range 7V 7V 5.5 V 55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS251 MIN Supply voltage, Vee 4.5 NOM SN74LS251 MIN NOM MAX 5.5 4.75 5 5.25 V -2.6 mA 8 mA 70 °e 5 -1 High-level output current, 10H Low-level output current, 10L 4 Operating free-air temperature, T A UNIT MAX -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level voltage 102 TEST eONDITIONSt SN54LS251 MIN SN74LS251 TYP+ MAX Vee= MIN, II =-18 mA VIH = 2 V, VIL = MAX, 10H = MAX 2.4 TYP+ MAX 2 2 Vec= MIN, MIN V 0.7 0.8 V -1.5 -1.5 V 3.4 2.4 3.1 V VCC = MIN, IOL=4mA VIH = 2 V, VIL = VIL max 10L =8 mA Off-state (high-impedance-state) Vee = MAX, Vo = 2.7 V 20 20 output current VIH = 2 V Vo = 0.4 V -20 -20 0.25 UNIT 0.4 0.25 0.4 0.35 0.5 V /lA II Input current at maximum input voltage VCC = MAX, VI = 7 V 0.1 0.1 IIH High-level input current Vec = MAX, VI = 2.7 V 20 20 /lA IlL Low-level input current VCC - MAX, VI - 0.4 V -0.4 -0.4 mA lOS Short-circuit output current§ VCC = MAX ICC Supply current -130 -30 -130 -30 VCC - MAX, Condition A 6.1 10 6.1 10 See Note 3 Condition B 7.1 12 7.1 12 I mA mA mA t For conditions shown as 11(11 N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at V"'C = 5 V,_T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 3: ICC is measured with the outputs open and all data and select inputs at 4.5 V under the following conditions: A. Strobe grounded. B. Strobe at 4.5 V. 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-365 TYPES. SN54LS2~J, SN74LS251 (TIM9905) DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS switching characteristics, Vee = 5 V, TA PARAMETER~ TO (INPUT) (OUTPUT) tpLH A, B, or C tpHL (4 levels) tPLH A, B,orC tpHL (3 levels) tpLH =25°e FROM TEST CONDITIONS MIN Y W Y Any D tpHL CL=15pF, RL=2kn, tpLH Any 0 W See Note 4 TYP 29 45 28 45 20 33 21 33 17 18 28 28 10 15 9 15 30 26 45 tpHL tZH Strobe Y Strobe W tZL tZH tZL tHZ Y Strobe tLZ CL = 5 pF, RL=2kn, tHZ W Strobe tLZ 11 tpLH == Propagation delay time, low-to-high-Ievel tpH L == Propagation delay time, high-to-Iow-Ievel tZH == Output enable time to high level tZL == Output enable time to low level tHZ == Output disable time from high level tLZ == Output disable time from low level See Note 4 MAX UNIT ns ns ns ns ns 40 17 27 24 40 30 45 15 25 37 55 15 25 ns ns ns output output NOTE 4: See load circuits and waveforms on page 3-11. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS Vee 100 II --'--Vee n NOM Req INPUT - no. ........ ~~ OUTPUT ~~ ~~ 1".7 A, B, e,s: Req = 20 kn NOM DO thru 07: Req = 17 kn NOM 1076 7·366 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54S251, SN74S251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Off-state output voltage Operating free-air temperature range: SN54S251 SN74S251 Storage temperature range 7V 5_5V 5.5 V -55°C to 125°C DoC to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74S251, SN54S251 MIN Supply voltage, Vee NOM 4.5 5 High-level output current, IOH MAX MIN 5.5 4.75 NOM 5 -2 Low-level output current, 10L 20 Operating free-air temperature, T A -55 125 0 MAX UNIT 5.25 V -6.5 mA 20 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) 'TEST eONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage MIN TYP+ MAX UNIT V 2 = MIN, Vee = MIN, VIL = 0.8 V, Vee = MIN, VIL = 0.8 V, Vee = MAX, VIH = 2 V Vee II = -18 rnA = 2 V, 10H = MAX VIH = 2 V, 10L = 20 rnA l Vo = 2.4 VIH [ SN54S' 2.4 3.4 I SN74S' 2.4 3_2 0.8 V -1.2 V V 0.5 V 50 = 0.5 V -50 V 10Z Off-state (high-impedance-state) output current II Input current at maximum input voltage Vee- MAX, VI- 5.5V 1 rnA IIH High-level input current Vee - MAX, VI - 2.7 V 50 JlA IlL Low-level input current Vee - MAX, VI- 0.5V -2 rnA. lOS Short-circuit output current ~ Vee - MAX lee Supply current I Vo -40 Vee - MAX, All inputs at 4.5 V, All outputs open 55 JlA -100 rnA 95 rnA I t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at VCr. = 5 V, T A = 25°C. § Not more than one output should be .shorted at a time, and duration of the short-circuit should not exceed one second. 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-367 TYPES SN54S251, SN74S251 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS switching characteristics, Vee = 5 V, TA PARAMETER1I FROM TO (INPUT) (OUTPUT) tPLH A,B,orC tpHL (4Ievels) tpLH A, B" orC (3Ievels) tpHL tpLH = 25° C TEST CONDITIONS Any D Y Any D W TYP 18 13 19.5 CL=15pF, 10 15 RL = 280.n, 9 13.5 See Note 2 8 12 8 12 4.5 7 tpHL tpLH MAX UNIT 12 Y W MIN tpHL 4.5 7 tZH 13 19.5 14 21 13 19.5 Y Strobe CL = 50pF, tZL RL = 280.n, tZH Strobe See Note 2 W tZL 14 21 tHZ 5.5 8.5 9 14 5.5 8.5 9 14 Y Strobe CL = 5 pF, tLZ RL = 280.n, tHZ Strobe See Note 2 W tLZ ns ns ns ns ns ns ns ns 11 tpLH ;: Propagation delay time, low·to-high-Ievel output tpHL;: Propagation delay time, high·to-Iow·level output tZH ;: Output enable time to high level tZL;: Output enable time to low level tHZ;: Output disable time from high level tLZ;: Output disable time from low level NOTE 2: See load circuits and waveforms on page 3-10. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS ------.--vcc vcc---.....- - - I INPUT OUTPUT 1272 7·368 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS253, SN74LS253 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS TTL MSI BULLETIN NO. DL-S 7611790, SEPTEMBER 1972-REVISED OCTOBER 1976 • • • • • SN54LS253 ••• J OR W PACKAGE SN74LS253 ••• J OR N PACKAGE (TOP VIEW) Three-State Version of SN54LS153/SN74LS153 Schottky-Diode-Clamped Transistors Permits Multiplexing from N Lines to 1 Line Performs Parallel-to-Serial Conversion Typical Average Propagation Delay Times: Data Input to Output ... 12 ns Control Input to Output ... 16 ns Select Input to Output ... 21 ns Fully Compatible with Most TTL and DTL Circuits Low Power Dissipation ... 35 mW Typical (Enabled) • • DATA INPUTS ~ ____ ~A~ ______ ~ ~----~vr--------J DATA INPUTS logic: see function table description Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections. The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus line to a high or low logic level. logic functional block diagram FUNCTION TABLE SELECT INPUTS B A X X L L L L H L H L H L H L H H H H DATA INPUTS co C1 C2 C3 X X X X X X X X X L H X X X X X X X X X L H L H X X X X X X L H X X X X OUTPUT OUTPUT CONTRO! G Y z H L L L H L L L H L L L H L L L H Ie' -"''':....'---+-f-+l=r:<---' 1C 3 ~ 3) SELECT{B A .!!:"A"-{'>-tol.>-~ OATA'{':::::: Address inputs A and B are common to both sections. H = high level, L = low level, X = irrelevant, Z = high • O"A'{'::~::: ,e,-,-,,'12"-.'---i::I::::=l±:r, impedance (off) 20'-"''''''-.'---!:::I::=±r-, absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . . Off-state output voltage . . . . . Operating free-air temperature range: SN54LS253 SN74LS253 Storage temperature range . . . . NOTE 7V 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C 1: Voltage values are with respect to network ground terminal. 1076 TEXASINCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-369 TYPES SN54LS253, SN74LS253 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/ MULTIPLEXERS WITH 3-STATE OUTPUTS REVISED OCTOBER 1976 recommended operating conditions SN54LS253 MIN NOM MAX Supply voltage, Vee High-level output current, 10H I Low-level output current, 10L 4.5 5 SN74LS253 UNIT MIN NOM MAX 5.5 4.75 -1 5 4 Operating free-air temperature, T A -55 125 0 5.25 V -2.6 B 70 mA mA °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIL VIK High-level input voltage Low-level input voltage I nput clamp voltage VOH High-level output voltage VIH VOL 10Z II SN54LS253 SN74LS253 UNIT MIN TYP:t: MAX MIN TYP:t: MAX 2 V 2 0.7 O.B V -1.5 -1.5 V TEST CONDITIONSt Vee = MIN, Vee = MIN, 11= -1BmA VIH=2V, VIL = VILmax, 10H = MAX Vee = MIN, VIH = 2V, VI'L = VIL max Low-level output voltage Off·State (high-impedance state) output current Input current at maximum input voltage High·level input current Low-level input current Vee = MAX, VIH = 2 V Vee= MAX, VI = 7V Vee = MAX, Vee = MAX, VI = 2.7 V VI = 0.4 V IIH IlL lOS Short-circu it output current § VCC= MAX ICC Supply current VCC = MAX, 2.4 3.4 0.25 10L = 4 mA 10L =BmA Vo = 2.7V Vo = 0.4 V Condition A Condition B 20 -20 0.4 0.5 20 -20 0.1 0.1 20 -0.4 -130 -30 7 8.5 V 3.1 0.25 0.25 -30 See Note 2 2.4 0.4 12 14 V IlA mA 7 8.5 20 IlA -0.4 mA -130 mA 12 mA 14 TYP MAX UNIT tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. • :t:AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time, and duration for the.short·circuit should exceed one second . NOTE 2: ICC is measured with the outputs open under the following conditions: A. All inputs grounded. B. Output control at 4.5 V, all Inputs grounded. switching characteristics, Vee PARAMETER~ tpLH tpHL tpLH tpHL = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Data Y Select TEST CONDITIONS MIN 17 13 CL=15pF, See Note 3 Y Output Control Output Control tZH Y tZL tHZ Y tLZ ~tPLH a Propagation delay time, low·to-high·level output tpHL a Propagation delay time, hlgh·to·low·level output tZH a Output enable time to high level tz L a Output enable time to low level tHZ a Output disable time fromhigh level tLZ a Output disable time from low level CL = 5 pF, See Note 3 RL = 2 kfl, RL = 2 kfl, 25 30 21 20 45 32 15 15 27 28 23 41 18 27 ns ns ns ns NOTE 3: Load circuit and waveforms are shown on page 3-11. 1280 7·370 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS253, SN7~LS253 DUAL. 4-LlN.f.~lO-1~LlNE DATA SELECTQRS/ MULTIPLEXERS WITH 3-STATE OUTPUTS schematic (each selector/multiplexer, and the common select section) • ~VCC TO OTHER SELECTOR/MULTIPLEXER (SEE FUNCTIONAL BLOCK OIAGRAM) w... M l [JGNO Vee bus Resistor values shown are nominal and in ohms. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-371 SN54LS258A, Sr~54S257, SN54S258, SN74LS257A, SN74LS258A, SN74S257, SN74S258 QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS TYPES TTL MSI Sr~54LS257A, BULLETI N NO. DL-S 7711734, OCTOBER 1976-REVISED AUGUST 1977 • Three-State Outputs Interface Directly with System Bus • 'LS257 A and 'LS258A Offer Three Times the Sink-Current Capability of the Original 'LS257 and 'LS258 • SN54LS257A, SN54S257 ••• J OR W PACKAGE SN74LS257A, SN74S257 ••• J OR N PACKAGE (TOP VIEW) INPUTS INPUTS OUTPUT ~ OUTPUT VCCCONTROL 4A 4B 4Y 3A 3B r---"'-.. OUTPUT Same Pin Assignments as SN54LS157, SN74LS157,SN54S157,SN74S157,and SN54LS158,SN74LS158,SN54S158, SN74S158 4A 4B 4Y 3A 3Y 3B 3Y • Provides Bus Interface from Multiple Sources in High-Performance Systems AVERAGE PROPAGATION 'LS257A TYPICAL DELAY FROM POWER DATA INPUT DlSSIPATIONO 12 ns 60mW 12 ns 60mW 'S257 4.8 ns 320 mW 'S258 4 ns 280mW 'LS258A SELECT ~ lY ~ 2Y GND INPUTS OUTPUT INPUTS OUTPUT positive logic: see function table SN54LS258A, SN54S258 ••• J OR W PACKAGE 00ft state (worst case) SN74LS258A, SN74S258 ••• J OR N PACKAGE (TOP VIEW) description INPUTS INPUTS OUTPUT OUTPUT OUTPUT VCCCONTROL 4A 48 4Y 3A 38 3Y r---"'--. • These Schottky-clamped high·performance multiplexers feature three-state outputs that can interface directly with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the low impedance of the single enabled output will drive the bus line to a high or low logic level. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the outputenable circuitry is designed such that the· output disable times are shorter than the output enable times. SELECT r---"'-.. ~ OUi~UT ~ 0 2~ INPUTS This three-state output feature means that n-bit (paralleled) data selectors with up to 258 sources can be implemented for data buses. It also permits the use of standard TTL registers for data retention throughout the system. INPUTS GND UT UT positive logic: see function table -FUNCTION TABLE OUTPUTY INPUTS OUTPUT Series 54LS and 54S are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74LS and 74S are characterized for operation from O°C to 70°C. 'LS258A 'S257 'S258 SELECT A B H X X X Z Z L L L X L H L L H X H L L H X L L H CONTROL L H 'LS257A = high H level, L = low X level, X H H = irrelevant, Z = high L impedance,(oft) 877 7-372 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS. TEXAS 75222 TYPES SN54LS257A. SN54LS258A. SN54S257. SN54S258. SN74LS257A. SN74LS258A. SN74S251l SN74S258 QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS functional block diagrams 'LS257 A, 'S257 'LS258A, 'S258 CONTROL 1A ~~-- __________ 1A ~ 1Y 16 ~~----~-------~ 1Y 16 2A 2A 2Y 26 2Y 26 3A 3A 3Y 36 3Y 36 4A 4A 46 46 SELECT SELECT 4Y schematics of inputs and outputs q 'LS257A, 'LS258A EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL OUTPUTS ---...--vcc VCC Select: All other inputs: TYPICAL OF ALL OUTPUTS ------VCC Reo Reo INPUT a 'S257, 'S258 EQUIVALENT OF EACH INPUT -- INPUT OUTPUT Reo ~ 9.5 kn NOM Req = 19 kfl NOM -- Select: All other inputs: Reo ~ 1.4 Req = 2.8 kn kn OUTPUT • NOM NOM i absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage: 'LS257 A, 'LS258A Circuits 'S257, 'S258 Circuits Off-state output voltage . . . . . . . Operating free-air temperature range: SN54LS', SN54S' Circuits SN74LS', SN74S' Circuits Storage temperature range 7V 7V 5.5 V 5.5 V -55°C to 125°C aOc to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-373 TYPES SN54LS257A, SN54LS258A, SN74LS257A, SN74LS258A QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED AUGUST 1977 recommended operating conditions SN54LS' Supply voltage, VCC SN74LS' NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -2.6 mA 24 mA DC -1 High-level output current, 10H 12 Low-level output current, 10L -55 Operating free-air temperature, T A UNIT MIN 70 0 125 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VCC= MIN, II = -18 mA VCC = MIN, VIH=2V, low-level output voltage 10Zl IIH III lOS VCC= MAX, Vo = 2_7 V VIH = 2 V, high-level voltage applied Off-state output current, VCC= MAX, VIH=2V, low-level voltage applied Vo = 0.4 V • S input maximum input voltage Any other High-level S input input current Any other low-level S input input current Any other VCC= MAX, VCC = MAX, VCC = MAX, Short-circuit output current§ TVP+ MAX 2 V 0.8 V -1.5 -1.5 V 2.4 0.4 VI=2.7V VI = 0.4 V V 3.1 0.25 0.4 0_35 0.5 'lS257A All outputs low 20 IJA -20 -20 IJA 0.2 0.2 0.1 0.1 40 40 20 20 -0.8 -0.8 -130 10 10 16 10 16 19 7 12 4.5 19 7 8.8 14 8.8 14 12 19 12 19 4. 'lS258A All outputs off -0.4 -130 -30 6.2 10 12 VCC= MAX, See Note 2 All outputs high 20 -0.4 -30 6.2 All outputs off UNIT 0.7 3.4 VI = 7 V VCC= MAX All outputs low Supply current MIN V VIL = Vil max All outputs high ICC MAX 0.25 10L =12 mA 10l = 24 mA Input current at II SN74LS' TVP+ VIH = 2 V, Off-state output current, 10ZH 2.4 VIL = VIL max, 10H = MAX VCC = MIN, VOL MIN 2 High-level output voltage VOH SN54LS' TEST CONDITIONSt PARAMETER mA IJA mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°C. §Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions. switching characteristics, Vee = 5 V, T A = 25° C, R L = 667 n PARAMETER~ tpLH tpHL tpLH tpHL FROM (INPUT) TO (OUTPUT) 'LS257A TEST CONDITIONS MIN I Data Select tpZH Output tpZL Control tpHZ Output tplZ Control Any Any CL = 45 pF, See Note 3 Any Any ~tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output tpZH == output enable time to high level NOTE 3: Load circuit and waveforms are shown on page 3-11. 'LS258A TVP MAX 12 12 14 TVP MAX 18 12 18 18 12 18 14 14 21 14 21 21 21 20 30 20 30 20 30 20 30 CL=5pF, 18 30 18 30 See Note 3 16 25 16 25 tpZL tpHZ tpLZ 7·374 UNIT ns ns ns ns == output enable time to low level == output disable time from high level == output disable time from low level DESIGN GOAL This page provides tentative information on a product In the developmental stage. Texas I nstruments reserves the right to change or discontinue this product without notice. MIN 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALL.AS, TEXAS 7~222 TYPES SN54S257, SN54S258, SN74S257, SN74S258 QUADRUPLE 2-LlNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS REVISED DECEMBER 1980 recommended operating conditions SN54S' MIN Supply voltage, Vee SN74S' MAX MIN NOM MAX 5 5.5 4.75 5 5.25 V -6.5 mA 20 mA 70 °e 4.5 High·level output current, IOH -2 Low·level output current, IOL 20 Operating free·air temperature, T A UNIT NOM -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage ~ Vee VOL 10ZH 10ZL High-level output voltage Low-level output voltage II IlL lOS VIH~2V, input current Any other Short-circuit output current§ Supply current All outputs low -1.2 V 2.4 3.4 2.4 3.4 VIL ~ 0.8 V, IOH ~ MAX SN74S' 2.4 3.2 2.4 3.2 Vee ~ MIN, VIH ~ 2 V, ~ 0.8 V, ~ IOL ~ 2.7 20 mA MAX, VIH~2V, 0.5 V VCC ~ MAX, VI ~ 5.5 V Vec ~ MAX, VI ~ 2.7 V Vec ~ MAX VI ~ 0.5V Vee ~ MAX -40 Vee ~ MAX, See Note 2 All outputs off V 0.5 0.5 V 50 50 J.l.A -50 -50 J.l.A 1 1 mA 100 100 50 50 -4 -4 -2 -2 -100 All outputs high lee V -1.2 2.7 VO~ S input 0.8 SN74S' Vec ~ MAX, VIH~2V, Low-level V 2 SN54S' VIL UNIT MAX 0.8 IOH~-1mA Off-state output current, Any other TYP:j: VIH~2V, low-level voltage applied S input MIN Vec ~ MIN, VO~2.4V High-level MAX VIL ~ 0.8 V, high-level voltage applied input current TYP:j: -18 mA Vee input voltage IIH ~ II MIN, Off-state output current, Input current at maximum MIN 2 VCC ~ MIN, VOH 'S258 'S257 TEST CONDITIONSt PARAMETER 44 68 60 64 -40 J.l.A mA mA -100 36 56 93 52 81 99 56 87 mA • I tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC ~ 5 V, T A ~ 25°C. §Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions. switching characteristics, Vee = 5V, TA = 25°e, RL = 280 n PARAMETER~ tpLH FROM TO TEST (INPUT) (OUTPUT) CONDITIONS Data Any Select Any tpHL tpZH Output tpZL Control tPHZ Output tpLZ Control tpHL "" propagation delay time, high·to-Iow-Ievel output tpZH "" output enable time to high level NOTE 4:. Load circuit and waveforms are shown on pages 3-10. MIN TYP MAX 6 7.5 4 6.5 4 6 eL~15pF, 8.5 15 8 12 See Note 4 8.5 15 7.5 12 13 19.5 13 19.5 14 21 14 21 5pF, 5.5 8.5 5.5 8.5 See Note 4 9 14 9 14 eL ~ tp LH "" propagation delay time, low-to-high-Ievel output MAX 5 Any Any TYP 4.5 tpHL tpLH 'S258 'S257 MIN ~ UNIT ns ns ns ns tpZL == output enable time to low level tpHZ "" output disable time from high level tpLZ "" output disable time from low level 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-375 TTL MSI TYPES SN54259, SN54LS259, SN74259, SN74LS259 (TIM9906l 8-BIT ADDRESSABLE LATCHES BULLETIN NO. DL-S 7612347, OCTOBER 1976 • • • • • • • • • • 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active High Decoder Enable/Disable Input Simplifies Expansion Direct Replacement for Fairchild 9334 Expandable for N-Bit Applications Four Distinct Functional Modes Typical Propagation Delay Times: '259 'lS259 Enable-to-Output . .. 12 17 18 Data-to-Output .... 12 20 Address-to-Output .. 16 Clear-to-Output 16 20 Fan-Out IOl (Sink Current) '259 ............. 16 rnA SN54lS259 ....... 4 rnA SN74lS259 ....... 8 rnA IOH (Source Current) '259 ............. -0.8 rnA 'lS259 ........... -0.4 mA Typicallcc '259 ............. 60 rnA 'lS259 ......... " 22 rnA SN54259, SN54LS259 _ • _J OR W PACKAGE SN74259, SN74LS259 ••• J OR N PACKAGE (TOP VIEW) ----- 01 03 Q2 GND ~ LATCH SEL OUTPUTS logic: see function table description FUNCTION TABLE These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific. uses include working registers, serialholding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. • ao ABC INPUTS Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the 0 input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. OUTPUT OF EACH ADDRESSED OTHER FUNCTION CLEAR G H L H D aiO H QiO QjQ L L D L 8·Line Demultiplexer L H L L Clear OUTPUT LATCH Addressable Latch Memory LATCH SELECTION TABLE SELECT INPUTS C B LATCH A ADDRESSED 0 L L L L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 H'" high level, L '" low level 0== the level at the data input 0iQ'" the level of 0i (i = 0,1, ..• 7, as appropriate) before the indicated steady-state input conditions were established. 1076 7-376 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54259, SN54LS259, SN74259, SN74LS259 (TIM9906) 8-BIT ADDRESSABLE LATCHES schematic of inputs and outputs '2~9 '259 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS ----~~--Vee 100 Vee---....- - - n NOM INPUT ' - - -......--OUTPUT Latch select, data in, or clear: Req Enable: Req = 4 kn NOM = 2.2 kn NOM 'LS259 'LS259 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS ----~~--Vee Vee Req INPUT = 17 - n-L ..root ~~ kn NOM ' - - _....._ _ OUTPUT • ~~ ~~ r.'7 I absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note 1) Input voltage: SN54259, SN74259 , . SN54LS259,SN74LS259 Operating free-air temperature range: SN54259, SN54LS259 SN74259,SN74LS259 Storage temperature range . 7V 5.5 V . 7V -55°C to 125°C aOe to 7aoe . -65°C to 15aoe NOTE 1: Voltage values are with respect to network ground terminal. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-377 TYPES SN54259,SN74259 8-BIT ADDRESSABLE LATCHES recommended operating conditions SN54259 SN74259 MIN NOM MAX Supply voltage, Vee 4.5 5.5 5 High·level output current, 10H MIN NOM MAX 4.75 -800 Low·level output current, 10L Width of clear or enable pulse, tw V -800 IJ.A 16 mA ns 16 Data Setup time, tsu Hold time, th 15 15 15i 15t Address 5t 5t Data ot ot 20t 20t Address -55 Operating free-air temperature, T A 125 UNIT 5.25 5 ns ns 70 0 °e tThe arrow indicates that the rising edge of the enable pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH • High-level output voltage Low-level output voltage II Input current at maximum input voltage IlL High-level input Enable current Other inputs Low-level input Enable current Other inputs Vee = MIN, II = 12 mA Vee= MIN, VIH=2V, VIL = 0.8 V, 10H = -8001J.A Vee= MIN, VIH = 2 V, VIL = 0.8 V, IOL = 16mA Vee= MAX, VI = 5.5 V Vee= MAX, VI = 2.4 V Vee= MAX, lOS Short-circuit output current§ Vee = MAX ICC Supply current Vee = MAX, t For TYPt MAX MIN 2 VOL IIH SN74259 SN54259 TEST CONDITIONSt 2.4 TYPt MAX 2 V 0.8 0.8 V -1.5 -1.5 V 2.4 3.4 0.2 0.4 V 3.4 0.4 0.2 1 1 VI = 0.4 V 80 80 40 40 -3.2 -3.2 -1.6 -1.6 -18 See Note 2 UNIT -57 60 -18 90 V mA IJ.A mA -57 mA 90 mA 60 CO~dltions shown as MIN or MAX, use th: appropriate value specified under recommended operating conditions. tAli typIcal values are at V CC = 5 V, T A = 25 C. § Not more than one output should be shorted at a time. NOTE 2: ICC is measured with the inputs grounded and the outputs open. switching characteristics, Vee PARAMETER tPHL tpLH tpHL tPLH tpHL tpLH tPHL = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Clear Any Q Data Any Q Address Any Q Enable Any Q TEST CONDITIONS MIN TYP MAX 16 25 14 24 eL=15pF, 11 20 RL=400n, 15 28 See Note 3 17 28 12 20 11 20 UNIT ns ns ns ns tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit is shown on page 3·10. 1076 7-378 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012". DALLAS, TEXAS 75222 TYPES SN54LS259, SN74LS259 (TIM9906) 8-BIT ADDRESSABLE LATCHES REVISED DECEMBER 1980 recommended operating conditions Supply voltage, Vee High-level output current, 10H SN54lS259 SN74lS259 MIN NOM MAX 4.5 5 5.5 -400 MIN NOM MAX 4.75 5 5.25 -400 low-level output current, lOt Width of clear or enable pulse, tw 15 15t 15t 5t 15t -55 15t 5t 15t Data Setup time, tsu Address Data Address Hold time, th 8 4 15 15t Operating free-air temperature, T A 125 UNIT V p.A rnA ns ns ns 70 0 °e tThe arrow indicates that the rising edge of the enable pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High level input voltage Vil VIK low level input voltage Input clamp voltage VOH High-level output voltage Val SN54lS259 SN74lS259 UNIT MIN TYPt MAX MIN TYP+ MAX TEST CONDITIONSt 2 low-level output voltage Input current at maximum II; -18 rnA Vee; MIN, Vee; MIN, Vll; Vil max, VIH;2 V 10H; -0.4 rnA Vee; MIN, VIH; 2 V, Vil = Vil max. V 2 0.7 -1.5 2.5 3.4 0.25 IIOl;4 rnA 0.8 -1.5 2.7 0.4 II0l-SmA V V V 3.4 0.25 0.4 0.35 0.5 V Vee = MAX, VI =7 V 0.1 0.1 rnA IIH input voltage High-level input current Vee = MAX, VI = 2.7 V 20 III low-level input current Vee = MAX, VI = 0.4 V -0.4 20 -0.4 rnA lOS Short·circuit output current§ Vee = MAX ICC Supply current Vee = MAX, II -20 ~2 See Note 2 -100 -20 36 22 -100 36 p.A rnA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration short-circuit should not exceed one second. NOTE 2: ICC Is measured with the Inputs grounded and the outputs open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER FROM (INPUT) TO (OUTPUT) tpHl Clear Any Q tplH tpHl Data Any Q el=15pF, Any Q Rl = 2 kn, See Note 3 tPLH Address tPHl tPlH Enable TEST CONDITIONS MIN TYP 27 13 24 21 38 29 35 24 18 22 15 AnyQ tPHl MAX 17 20 32 • UNIT ns ns ns ns tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagatiOn delay time, hlgh-to-Iow-Ievel output NOTE 3: Load circuit is shown on paae 3-11. TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-379 TTL MSI TYPES SN54LS261, SN74LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS . BULLETIN NO. DL-S 7612123, MARCH 1974-REVISED OCTOBER 1976 • Fast Multiplication ... 5-Bit Product in 26 ns Typ • Power Dissipation ... 110 mW Typical • Latch Outputs for Synchronous Operation SN54LS261 ••• J OR W PACKAGE SN74LS261 ••• J OR N PACKAGE (TOPVIEWI OUTPUTS VCC • Expandable for m-Bit-by-n-Bit Applications • Fully Compatible with Most TTL and Other Saturated Low-Level Logic Families • Diode-Clamped Inputs Simplify System Design B2 BO Bl r--"'-\ 00 01 MO Ml G Q1 description These low-power Schottky circuits are designed to be used in parallel multiplication applications. They perform binary multiplication in two's-complement form, two bits at a time. B4 B3 FUNCTION TABLE LATCH CONTROL EQUIVALENT OF EACH INPUT Vcc--+--- OUTPUTS MULTIPLIER M2 M1 MO L X X X H L L L G The leading (most-significant) bit of the product is inverted for ease in extending the sign to square (left justify) the partial-product bits. schematics of inputs and outputs GND OUTPUTS INPUTS The outputs represent partial products in one'scomplement form generated as a result of multiplication. A simple rounding scheme using two additional gates is needed for each partial product to generate two's complement. The SN54LS261 is characterized for operation over the full military temperature range of -55°e to 125°e; the SN74LS261 for operation from oOe to o 70 e. M2~ positive logic: see description The M inputs are for the multiplier bits and theB inputs are for the multiplicand. The Q outputs represent the partial product as a recoded base-4 number. This recoding effectively reduces the Wallace-tree hardware requirements by a factor of two. • LATCH CONTROL G 04 Q3 02 Q1 QO 04 0 030 020 01 0 QOo H L L L L 84 B3 82 81 84 83 82 81 H B4 B4 B4 83 82 81 80 L 84 B3 B2 61 60 L H 84 B4 62 61 H H L 84 84 B3 B3 62 i61 H H H H L L L L H L L H H L H L H L H H H L H H H H H = high level, L = low level, X = irrelevant Q40 ••• aoO = The logic level of the same output before the high-to-Iow transition of G. B4 ••• BO = The logic level of the indicated multiplicand (B) input. TYPICAL OF QO, 01, Q2, Q3 OUTPUTS ---~P--VCC TYPICAL OF 04 OUTPUT VCC-.......- - -----VCC 17 kn NOM I N PUT......,~_---4~ OUTPUT OUTPUT G: Req = 17 kn NOM 8 or M2:' Req = 20 kn NOM MO or MI:Re = 10 kn NOM 1076 7·380 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS261, SN74LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS functional block diagr~m_ BO (13) • MO M 1 ______"-----_ 374 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-381 TYPES SN54LS261, SN14LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free·air temperature range: SN54LS261 SN74LS261 Storage temperature range 7V 7V -55°C to 125°e oOe to 700e 0 -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS261 SN74LS261 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -400 j.lA 8 mA Supply voltage, Vee High·level output current, 10H -400 Low-level output current, 10L 4 Width of enable pulse, tw Setup time, tsu Hold time, th 25 25 Any M input 17~ 17~ Any B input 15~ 15~ Any M input O~ O~ Any B input O~ Operating free-air temperature, T A ~ The UNIT MIN ns ns ns O~ -55 125 70 0 °e arrow Indicates that the failing edge of the enable pulse Is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage • MIN TYP+ MAX SN74LS261 TYP+ MAX MIN 2 2 VOL Low·level output voltage Vee = MIN, II = -18 mA Vee = MIN, VIH=2V, VIL = VIL max, 10H =-400j.lA Vec= MIN, VIH = 2 V, VIL Input current at = VIL 10L - 4 mA 2.7 3.4 ,0.25 0.4 10L = 8mA max Vee = MAX, maximum input voltage 0.8 -1.5 -1.5 2.5 VI = 7 V IIH High-level input current Vee = MAX, VI = 2.7 V IlL Low-level input current Vee = MAX, VI = 0.4 V lOS Short-circuit output current§ Vee = MAX lee Supply current Vee = MAX, Outputs operi. UNIT V 0.7 VOH High-level output voltage II SN54LS261 TEST CONDITIONSt PARAMETER 3.4 V V V 0.25 0.4 ,0.35 0.5 V MOorMI All others 0.2 0.2 0.1 0.1 MO orMI 40 40 All others 20 20 MOorMI -0.8 -0.4 -0.8 -0.4 mA All others -100 mA 40 mA -20 All inputs at 0 V, -100 20 -20 38 20 mA j.lA +AII typical values are at VCC = 5 V, T A = 25°C. §Not more than one output should be shorted at a time and duration of the output short-circuit should not exceed one second. switching characteristics, Vee PARAMETER~ tpLH =5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Enable G AnyQ tpHL tpLH MIN = 15 pF, RL = 2 kn, eL Any M input AnyQ Any B input AnyQ tpHL tpLH TEST CONDITIONS See Note 2 tPHL ~ tpLH TYP MAX UNIT 22 35 ns 20 30 . ns 25 40 ns 22 35 ns 27 42 ns 24 37 ns == propagation delay time, low-to-high-Ievel output; tpH L ... propagation delay time, high-to-Iowlevel output. NOTE 2: Load circuit and voltage waveforms are shown on page 3-11. 1080 7-382 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS261, SN74LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS TYPICAL APPLICATION DATA Multiplication of the numbers 26 (multiplicand) by 29 (multiplier) in decimal, binary, and 2-bit-at-a-time-binary is shown here: BINARY DECIMAL 2-BIT-AT-A-TIME BINARY Sign Bit Sign Bit B M 26 ~ 234 R 754 • 011010 011101 011010 000000 011010 } 011010 011010 000000 01011110010 • Partial 6 Products t~ 011010 (+2) (-1) (+1). 00000011010 }, Partial 3 111100110 0110100 Products t~1~100101 Sign Product Bit Sign Product Bit Two points should be noted in the two-bit-at-a-time-binary example above_ First, in positioning the partial products beneath each other for final addition, each partial product is shifted two places to the left of the partial products above it instead of one place as is done in regular multiplication. Second, the msb of the partial product (the sign bit) is extended to the sign-bit column of the final answer. A substantial reduction of multiplication time, cost, and power is obtained by implementing a parallel partial-product-generation scheme using a 2-bit-at-a-time algorithm, followed by a Wallace Tree summation. Partial-product-generation rules of the algorithm are: • I 1. Examine two bits of multiplier M plus the next lower bit. For the first partial product (PP1) the next lower bit is zero. 374 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-383 TYPES SN54LS261, SN74LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS TYPICAL APPLICATION DATA 2. Generate partial product (PPi) as shown in the following table: MUL TIPLIER BITS FROM OPERATOR STEP 1 TO OBTAIN PARTIAL PRODUCT SYMBOL 221-2 2 21 - 3 0 0 0 0 0 1 0 +1 B 0 1 0 +1 B Copy multiplicand 0 1 1 +2 B Shift multiplicand left one bit 1 0 0 -2B Shift two's complement of multiplicand left one bit 1 0 1 -1 B Replace multiplicand by two's complement 1 1 1 1 0 1 -1 B Replace multiplicand by two's complement Replace multiplicand by zero 2 21 - 1 Replace multiplicand by zero Copy multiplicand 0 3. Weight the partial products by indexing each two places left relative to the next-less-significant product. 4. Extend the most-significant bit of the partial product to the sign-bit place value of the final product. EXAMPLE OF ALGORITHM M 29 Operator Symbol 011101 yjota +1 B +110 • -1B 011 +2 B B=26=011010 00000011010 111100110 0110100 The summation of these partial products was shown in the 2-bit-at-a-time binary mUltiplication example above. The 'LS261 generates partial products according to this algorithm with two exceptions: 1. The one's complement is generated for the cases requiring the two's complement. The two's complement can be obtained by adding one to the one's complement; this rounding can be done by using one NAND gate and one AND gate as shown in Figure B. 2. The most-significant bit is complemented to reduce the hardware required to extend the sign bit. This extension can be accomplished by adding a hard-wired logic 1 in bit position 2 2i+15 of each partial product and also in bit position 2 16 of the first partial product (PP1). 374 7-384 TEXAS INCORPORATED INSTRUMENTS POST OFFICE sox 5012 • DALLAS. TEXAS 75222 TYPES SN54LS261, SN74LS261 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS LATCH CONTROL 20 INPUTS TO ~AlLACE TREE FIGURE A-FIRST PARTIAL PRODUCT, PP1 LATCH CONTROL 2 2;-2 ~--------------------~V~------------~----~-J 19 INPUTS TO WALLACE TREE FIGURE B-OTHER PARTIAL PRODUCTS, PPi • FIGURE C-MANIPULATION OF PARTIAL PRODUCTS FOR ENTRY INTO WALLACE TREE In general, the 4 x 2 bit 'LS261 can be expanded for use in 4m x 2n bit multipliers. Partial-product generation uses m x n 'LS261s m x n -;- 16 'LSOOs, and m x n -;- 16 'LS08s. The size of the Wallace tree and ALU requ'irements vary depending on the size of the problem. The count for the 16 x 16 bit mUltiplier is: 32 2 2 56 7 2 SN54LS261/SN74LS261 SN54LSOO/SN74LSOO SN54LS08/SN74LS08 SN54LS183/SN74 LS183 SN54LS181/SN74LS181 SN54S182/SN74S182 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·385 TYPES SN54LS266, SN74LS266 QUADRUPLE 2-INPUT EXCLUS'IVE-NOR GATES WITH OP'EN-COLLECTOR OUTPUTS TTL MSI BULLETIN NO. DL-S 7611843, DECEMBER 1972-REVISED OCTOBER 1976 • Can Be Used as a 4-Bit Digital Comparator • Input Clamping Diodes Simplify System Design • Fully Compatible with Most TTL and DTL Circuits SN54LS266 ••• J OR W;"ACKAGE SN74LS266 ••• J OR N PACKAGE (TOP VIEW) Vcc 48 4A 4Y 3Y 39 3A 1A 18 1Y 2Y 2A 29 GND FUNCTION TABLE INPUTS OUTPUT -A B Y L L H L H L H L L H H H H = high level, L = low level description positive logic: Y = A(l)S = AS + AS The 'LS266 is comprised of four independent 2-input exclusive-NOR gates with open-collector outputs. The opencollector outputs permit tying outputs together for multiple-bit comparisons. schematics of inputs and outputs • TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT VCC --~~---VCC 12.5 kn. NOM INPUT ~~ OUTPUT - 0.. u~ ~, -' ~, -' rJ7 1076 7·386 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS, TEXAS 75222 TYPES SN54LS266, SN74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COLLECTOR OUTPUTS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS266 SN74LS266 Storage temperature range 7V 7V -55°C to 125°C oOe to 70°C _65° e to' 150° e NOTE1: Voltage values are with respect to network ground terminal. recomrnende~ operating conditions SN54LS266 MIN 4.5 Supply voltage, Vee NOM SN74 LS266 MAX MIN 5.5 4.75 5 High-level output voltage, VOH -55 5 MAX 5.25 UNIT V 5.5 5.5 4 8 mA 70 °e Low-level output current, IOL Operating free-air temperature, T A NOM 125 0 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IOH High-level output current MIN TYP+ SN74LS266 MAX Vce = MIN, 11=-18mA Vce= MIN, VIH=2V, MIN TYP+ MAX 2 2 UNIT V 0.7 0.8 -1.5 -1.5 100 100 V V /lA VIL = VIL max, VOH = 5.5 V Vee= MIN, VOL SN54LS266 TEST CONDITIONSt PARAMETER IIOL =4 mA 0.25 0.4 0.25 0.4 0.35 0.5 VIH=2V, Low-level output voltage V VIL = VIL max IIOL = 8 mA II Input current at maximum input voltage Vee = MAX, VI = 7V 0.2 0.2 IIH High-level input current Vee = MAX, VI = 2.7 V 40 40 IlL Low-level input current Vee - MAX, VI - 0.4 V -0.8 Ice Supply current Vee - MAX, See Note 2 8 8 13 -0.8 13 mA /lA mA rnA t For conditions shown as MIN or M AX. use the appropriate value specified under recommended operating conditions for the applicable type. +AII typical values are at V CC = 5 V, T A = 25" C. NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open. switching characteristics, Vee PARAMETER~ tpLH =5 V, TA = 25°e FROM TEST CONDITIONS (INPUT) A orB Other input low tpHL tpLH • eL=15pF, RL = 2 kn, A or B Other input high tpHL See Note 3 MIN TYP MAX UNIT 18 30 18 30 18 30 18 30 ns ns ~ tpLH '" propagation delay time, low·to-high·level output tpH L '" propagation delay time, high-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-387 I TYPES SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR TTL MSI BULLETIN NO. DL·S 7612091, OCTOBER 1976 SN54273, SN54LS273 • _ • J PACKAGE SN74273, SN74LS273 •.• J OR N PACKAGE • Contains Eight Flip-Flops with Single-Rail Outputs • Buffered Clock and Direct Clear Inputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators CLOCK 60 VCC description These monolithic, positive·edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. CLEAR 10 Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse_ When the clock input is at either the high or low level, the D input signal has no effect at the output. (EACH FLIP-FlOP) INPUTS V C C =Req a-INPUT -- a L x X L H t H H H t L L H L X 00 See explanation of function tables on page 3-8. a 'LS273 EQUIVALENT OF EACH INPUT l-00~VCC VCC NOM 20 kn NOM INPUT _ OUTPUT CLEAR CLOCK 0 '273 TYPICAL OF ALL OUTPUTS 40 FUNCTION TABLE schematics of inputs and output EQUIVALENT OF EACH INPUT 3D positive logic: see function table These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the '273 and 10 milliwatts for the 'LS273 . • 30 10 OUTPUT Clear: Req = 3 kn NOM Clock: Ffeq = 6 kn NOM All other inputs: Req = 8 kn NOM -- TYPICAL OF ALL OUTPUTS ~~on --~VCC NOM OUTPUT functional block diagram' 1076 7-388 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54273, SN74273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54273 SN74273 Storage temperature range ..... 7 V . . . . 5.5 V _55°C to 125°C oOe to 70°C _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54273 Supply voltage, VCC SN74273 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -800 16 IlA mA 30 MHz High·level output current, 10H -800 Low·level output current, 10L Clock frequency, fclock Width of clock or clear pulse, tw 16 30 0 I I Set-up time, tsu 0 16.5 Data input 16.5 20t Clear inactive state 25t 25t 5t 5t Data hold time, th Operating free·air temperature, T A UNIT MIN ns 20t -55 125 ns ns 0 °c 70 tThe arrow indicates that the rising edge of the clock pu Ise is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL VIK Low·level input voltage MIN TVP:I: MAX UNIT V 2 Input clamp voltage VOH High-level output voltage VCC; MIN, 11;-12mA VCC; MIN, VIH;2V, VIL; 0.8 V, 10H; -800J.!A 0.8 -1.5 2.4 VIH-2V, VIL; 0.8 V, IOL;16mA VOL Low-level output voltage II Input current at maximum input voltage IIH High·level input current 0.4 VCC; MAX, VI - 5.5 V Clear Clock or D Clear 80 40 -3.2 VCC; MAX, VI; 0.4 V IlL Low·level input current lOS Short-circuit output current§ VCC; MAX ICC Supply current VCC; MAX, See Note 2 Clock or D 1 VCC; MAX, VI; 2.4 V -1.6 -18 62 V V 3.4 VCC - MIN, V V rnA Il A rnA -57 rnA 94 rnA tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. :t:AII typical values are at V CC ; 5 V, T A; 25°C. §Not more than one output should be shorted at a time. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock_ switching characteristics, Vee = 5 V, TA = 25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency tpHL Propagation delay time, high-to-Iow-Ievel output from clear tpLH Propagation delay time, low-to-high-Ievel output from clock tpHL Propagation delay time, high-to-Iow-Ievel output from clock CL;15pF, RL; 400 .11, See Note 3 MIN TVP 30 40 MAX UNIT MHz 18 27 ns 17 27 ns 18 27 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-389 TYPES SN54LS273. SN74LS273 OCTAL O-TYPE FLIP-FLOP WITH CLEAR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range:SN54LS273 SN74LS273 Storage temperature range . . . . . 7V ..... 7 V -55°C to 125°C oOe to 70°C 65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal recommended operating conditions SN54LS273 SN74LS273 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -400 p.A Supply voltage, Vee High-level output current, 10H -400 Low-level output current, 10L 4 elock frequency, fclock 30 0 Width of clock or clear pulse. tw I I Set-up time, tsu UNIT MIN 0 20 20 Data input 20t 20t elear inactive state 25t 25t 5t 5t Data hold time, th -55 Operating free-air temperature, T A 125 8 mA 30 MHz ns ns ns 70 0 °e tThe arrow indicates that the rising edge of the clock pulse Is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • SN54LS273 TEST CONDITIONSt VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High·level output voltage VOL Low·level output voltage II Input current at maximum input voltage IIH High-level input current Vee MAX, VI = 2.7 V IlL Low-level input current Vee = MAX, VI = -0.4 V lOS Short-circuit output current § Vce = MAX lee Supply current Vee - MAX, MIN TYP:(: SN74LS273 MAX MIN TYP:(: 2 Vee = MIN, 11=-18mA Vee - MIN, VIH - 2 V, 2.5 VIL = VILmax, 10H = -400p.A Vee - MIN, VIH - 2 V,POL -4 mA VIL = VILmax Vee = MAX, 0.8 -1.5 -1.5 3.4 0.25 2.7 0.4 0.25 0.1 17 0.4 0.5 0.1 V V mA 20 20 J-lA -0.4 -0.4 mA -100 mA 27 mA -100 -20 -20 V V 3.4 0.35 VI =7 V UNIT V 0.7 POL = 8 mA See Note 2 MAX 2 27 17 t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions. :(:AII typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shortad at a time and duration of short circuit should not exceed one second. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs. ICC is measured after a momentary ground. then 4.5 V is applied to clock. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS MIN TYP 30 40 MAX UNIT f max Maximum clock frequency tpHL Propagation delay time, high-to-Iow-Ievel output from clear! eL = 15 pF, 18 27 ns tpLH Propagation delay time, low-to-high-Ievel output from clock RL = 2 kn, 17 27 ns tpHL Propagation delay time, high-to-Iow-Ievel output from clock See Note 4 18 27 ns MHz NOTE 4: Load circuit and voltage wavaforms are shown on page 3-11. 1076 7-390 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TTL LSI TYPES SN54LS275, SN54S274, SN54S275, SN74LS275, SN74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS BULLETIN NO. DL-S 7612121, OCTOBER 1976 SN54S274 ••• J PACKAGE SN74S274 ••• J OR N PACKAGE (TOP VIEW) • '5274 Provides 8-Bit Product in Typically 45 ns • 'S274 Can Provide Sub-Multiple Products for n-Bit-by-n-Bit Binary Numbers • 'LS275 and 'S275 Accept 7 Bit-Slice Inputs and 2 Carry Inputs for Reduction to 4 Lines in Typically 45 ns • These High-Complexity Functions Can Reduce Package Count by Nearly 50% in Most Parallel Multiplier Designs • When SN74S274 is Combined With SN74H183 (or SN74LS183) and Schottky Look-Ahead Adders, Multiplication Times are Typically: positive logic: When either (or both) G input(s) is (are) high, all eight outputs are off. 16-Bit Product in 75 ns (79 ns) 32-Bit Product in 116 ns (132 ns) SN54LS275, SN54S275 ••• J PACKAGE SN74LS275, SN74S275 ••• J OR N PACKAGE (TOP VIEW) description These high-complexity Schottky-clamped TTL circuits are designed specifically to reduce the delay time required to perform high-speed parallel binary multiplication and significantly reduce package count. The 'S274 is a basic 4-bit-by-4-bit parallel multiplier in a single package, and as such, no additional components are required to obtain an 8-bit product. For word lengths longer than 4 bits, a number of 'S274 multipliers can be combined to generate sub-multiple partial products. These partial products can then be combined in Wallace trees to obtain the final product. See Typical Application Data. SLICE AND CARRY OUTPUTS SLICE INPUTS • 2" -r' 2" ~ 2n C2"C2n ~~ SLICE INPUTS The 'LS275 and 'S275 expandable bit-slice Wallace trees have been designed to accept up to seven bit-slice inputs and two carry inputs from previous slices for reduction to four lines. positive logic: When CARRY IN G is high, all 2" GND SLICE INPUT four outputs are off. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-391 I TYPES SN54LS275,SN54S274,SN54S275, SN74LS275, SN74S274·, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS functional block diagram 'LS275, 'S275 . BIT·SlICE INPUTS OF 2" C2"+1 2"+() NOTE: When one of of the C2 n carry inputs is not used, it must be grounded. If neither C2 n carry input is used, both C2 n inputs are grounded and the C2 n + 1 output is normally left open. schematics of inputs and outputs 'S274, 'S275 'LS275 EQUIVALENT OF • EACH INPUT vCC--"--- EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS ---~~-vcc TYPICAL OF ALL OUTPUTS vcc-----~~-_~ - - -__-vcc INPUT~.-+-----;~ y~-+- OUTPUT INPUT-~--:!.....- - t - - - l OUTPUT Enable G: Req = 18 kf! NOM Others: Req = 6 kf! NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage: 'LS275 . . . . 'S274, 'S275 Off-state output voltage: 'LS275 'S274, 'S275 Operating free-air temperature range: SN54LS, SN54S Circuits SN74LS, SN74S Circuits Storage temperature range · 7V · 7V 5.5V · 7V 5.5V _55°C to 125°C O°C to 70°C _65°C to 150°C NOTE 1: Voitage values are with respect to network ground terminal. 877 7-392 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS275. SN74LS275 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS REVISED AUGUST 1977 recommended operating conditions SN54LS275 SN74LS275 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -2.6 mA 24 mA 70 °e Supply voltage, Vee High·level output current, 10H -1 Low-level output current, 10L 12 Operating free-air temperature, T A UNIT MIN -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54LS275 TEST eONDITIONSt MIN VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage SN74LS275 MAX 2 Vee = MIN, 11=-18mA Vee = MIN, VIH = 2 V, Low-level output voltage 2.4 10H = MAX VIL = VILmax Vee = MIN, VOL TYP:j: 10ZL II IIH IlL MAX 2 -1.5 -1.5 3.2 2.4 0.4 3.1 Off-state output current, Vee = MAX, Va = 2.7 V Off-state output current, Vee = MAX, VIH = 2 V, VIH = 2 V, Va = 0.4 V Enable G maximum input voltage All others High·level Enable G input current All others Low-level Enable G input current All others V 0.25 0.4 0.35 0.5 V high·level voltage applied Input current at V V VIH=2V, low-level voltage applied UNIT V 0.8 VIL = VILmax IIOL = 24 mA 10ZH TYP:j: 0.7 0.25 IIOL = 12 mA MIN Vee = MAX, VI =7V VI = 2_7 V Vee = MAX, Vee = MAX, lOS Short-circuit output current § Vee = MAX lee Supply current Vee = MAX VI=O.4V 20 20 IJ.A -20 -20 IJ.A 0.1 0.1 0.3 0.3 20 20 60 60 -0.4 -0.4 -1.2 -30 -130 25 -1.2 -30 40 mA IJ.A mA -130 mA 25 40 mA TYP MAX t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER~ tPLH FROM TO (INPUT) (OUTPUT) Any Slice or earry Any tpHL See Note 2 tpZH CL=45pF, tpZL tpHZ Enable G RL = 667 .11, RL = 667.11, See Note 2 Any CL = 5 pF, See Note 2 tpLZ ~ TEST CONDITIONS CL =45 pF, RL = 667 .11, MIN 35 62 42 66 8 23 13 23 10 15 10 15 UNIT ns ns ns tpLH == Propagation delay time, low-to-high-Ievel output tpH L == Propagation delay time, high-to-Iow-Ievel output tpZH == Output enable time to high level tpZL == Output enable time to low level tpHZ == Output disable time from high level tpLZ == Output disable time from low level NOTE 2: Load circuit and voltage waveforms are shown on page 3-11. 871 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-393 TYPES SN54S274, SN54S275, SN74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS recommended operating conditions Supply voltage, Vee SN54S274 SN74S274 SN54S275 SN74S275 MIN NOM MAX MIN NOM 4.5 5 5.5 4.75 5 High-level output current, 10H -2 Low-level output current, 10L 12 Operating free-air temperature, T A -55 125 UNIT MAX 0 5.25 V -6.5 mA 12 mA 70 "e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74S274 SN54S274 PARAMETER TEST CONDITIONSt MIN VIH High-level input voltage VIL Low-level input voltage VIK I nput clamp voltage TYP+ MAX 2 VOH High-level output voltage VOL Low-level output voltage Off-state output current, 10ZH high-level voltage applied Vee = MIN, 11=-18mA Vee- MIN, VIH-2V, VIL = 0.8 V, 10H = MAX Vee= MIN, VIH = 2 V, VIL = 0.8 V, 10L= 12mA Vee = MAX, VIH = 2V, 2.4 Vee= MAX, TYP+ UNIT MAX 2 V 0.8 0.8 V -1.2 -1.2 V 3.4 2.4 Vo = 2.4 V, Off-state output current, MIN VIH=2V, V 3.2 0.5 0.5 V 50 50 IJA low-level voltage applied Vo = 0.5 V -50 -50 IJA II Input current at maximum input voltage Vee- MAX, VI - 5.5 V 1 1 mA IIH High-level input current Vec= MAX, VI=2.7V 25 25 IJA IlL Low-level input current Vee= MAX, VI = 0.5 V -0.25 -0.25 mA lOS Short-circuit output current § Vee= MAX -100 mA lee Supply current Vee = MAX 155 mA 10ZL • SN74S275 SN54S275 105 switching characteristics over recommended ranges of T A and PARAMETER~ tPHL tpLH FROM TO '(INPUT) (OUTPUT) TEST CONDITIONS Any Any Slice or earry ('5275) tpZL MIN eL=5pF, Any Enable Any tpHZ RL=400n, See Note 3 tPLZ 105 SN54S274 SN74S274 SN54S275 SN74S275 TYP+ MAX 50 50 MIN UNIT TYP+ MAX 95 50 70 95 50 70 15 45 15 30 15 45 15 30 10 40 10 25 10 40 10 25 RL = 400 n, See Note 3 tpZH -30 155 Vee (unless otherwise noted) eL=30pF, Any A or B ('S274), or -100 -30 ns ns ns t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, TA = 25°e. / § Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. ~ tPLH tPHL == Propagation delay time, low-to-high-Ievel == Propagation delay time, high-to-Iow-Ievel tpZH == Output enable time to high level tpZL == Output enable time to low level tpHZ == Output disable time from high level tpLZ == Output disable time from low level output output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-394 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS275, SN54S274,SN54S275"SN74LS275, SN74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS TYPICAL APPLICATION DATA 1'.ub-multip'epartialproductbits that contribute tothe;zn+O product (See Note AI ~1Ub-multiplepartialproductbits that contribute to the 2n+O product ISee Note AI ~ ~ r---t--t-H-t-+-:I---.., :07n~n:p~c:-':';~::on delay time : ..r 7-INPUT ADOER 2"+'carrybittotha;zn+'tret 'LS27S/,S275 • 3-INPUT : ADDER I I I I ,..~.'"': ;zn+2carrybittothe:zn+2tr.. c;;7inputsperbit-slica _ --, ~~;; :~c::.:r;:~~~~c:alfY time r-::.--=-=-=-=~~ 1 package per bit-sliCl ~2carrybittothe2""2tree 2"+' carry bitta the 2"+1 tree ~:ca;'71~!=~~~i~~es +t----' ~:.ca~71b~::~~:::~teI this carry bit and the 2"+1 product output (from tha n+l thi.carry bit and tha 2"+1 product output (fromthen+1 Wallacetreel.refadintoa Wallacttree) .... fedinto. summing adder. summing adder. FIGURE 2-HIGH-SPEED BIT-SLICE WALLACE TREE FIGURE 1-BASIC BIT-SLICE WALLACE TREE .. 7 inputs per bit-slice 61 ns typical propagation delay time 11/4 packages per bit-slice BIT SLICE BIT SLICE BIT SLICE See NoteA To next CO To n+2 tree • BIT SLICE ~--------------------------~vr-------------------------J To final summing adder FIGURE 3-MODERATE-SPEED BIT-SLiCE WALLACE TREE NOTE A: All unused inputs must be grounded. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-395 TYPES SN54LS275,SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS TYPICAL APPLICATION DATA " 15 inputs per bit·slice 101 nl typical propagation delay time 31/2packages 135 ns typical propagation delay time 3packagas ISeeNotoAI 2 ..20U 'puts fromn-2tree 1 2"+' outputs 'ramn-ltre. Note A ,-------r... From n-2Tree From n-l Tree I See NoteC I L ________ _ '-.,---J To Final Summing Adder NOTES: A. Ground unused inputs. B. These outputs from preceeding trees may go to any of the inputs of the 'LS275/'S275. C. The circuit within the dotted lines may be either the basic bit·slice Wallace tree or the high·speed Wallace tree. In the latter case both carry inputs of the 'LS2751'S275 must be grounded. FIGURE 4-15·BIT·SLICE WALLACE TREE FOR 32·BIT X 32·BIT MULTIPLIER • 'LS275! ._._._. fiiii:riiii.iI i i i i i i i i tree 2"+1 bit to 2"t'tree i 2" bit from 2"-2 tree 2" bit from 2"-1 ._._._. tree L. r~ ., (23 Bits) i i i i i DETAIL A DETAIL A __________________ i DETAIL A i .J ._.j 'S275 (31 Bits) i i i 2"+2 bit to 2"+2 'LS275! ·S27S- . . ! I 'j ~ 1 ~---------'i !L._._._._._._._._. DETAIL A 2"+2 bit from 2"-2 tree 2"+' bit from 2"-1 tree 2"+2 bitta 2"+2 tree 2"'+' bit to 2"+1 tree To final summing adder NOTES: A. Ground unused inputs. B. The number of bits in parentheses is the maximum number of bits this tree can combine if the remaining 'LS2751'S275 (all having a higher number in the parentheses) were not connected. FIGURE 5-7-TO-31-BIT~LlCE WALLACE TREE FOR UP TO 64-BIT X 64-BIT MULTIPLIERS 1076 7·396 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS275, SN54S274, SN54S275,:SN74LS275, SN74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS TYPICAL APPLICATION DATA ,'-'-'-'-'-'-'-'-1 . 2upper half of n X iower half of n . ~~;;'~h.li :;t~~~-;;;~e-;h~;;;i -;;T' 2i~;;' 'h,;jj'.;t~ ;t21;;;';;haii~f~-'! ._._._.,._._._ .....l._._._._.,._._._._.l Ll~~ ~If ~n25..2~~~~f:... j NOTE A: The left·hand half of each rectangle is the portion of word one used to obtain the product shown within the rectangle. Similarly. the right-hand half of each rectangle is the portion of word two used. FIGURE 6-UNIVERSAL METHOD OF I 1 ADDING ~ -BIT PRODUCTS TO OBTAIN AN n-BIT PRODUCT I 1 I 1 1 I I 1 I I 1 1 1 I I~I 111 I 1 1 1 I"J I~I 1 1 1 1 1 1 1 1 1 1 I~I I~I I 1 I 1 1 I 1 1 1 1 1 1 1 I~I 1< ~ ;l> -I 12 16 12 -< 4 ~ n » r» "tI ~ (J) o z _ ID ~8z "tI ~~CIJ '0-l ~;o ~c: C n ~ 20 0 Cl~ Z 0 [TI z 'S274 'S274 -l 'S274 'S274 (J) » -I » ta~en - IN ..... =-....1 I_~ en ....... !::=en n_Z mZU"l oCl>~ C:J:Ien l>-l>-....I 28 .......... ~ mm'Cn OOZ CC-....I .......... ~ 231 ..... 230 2 29 2 28 227 2 26 225 2 23 222 221 2 20 219 2 18 FIGURE 10-16-BIT X 16-BIT MULTIPLIER (SHEET 2 OF 3-OUTPUT CONNECTIONS) w CO CO 224 II 217 2 16 -a-aen CCN .......... -....1 en en U"I TYPES Sr~54LS275,Sr~54S274, Sr~54S275, Sr~74LS275, Sr~74S274, SN74S275 4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS TYPICAL APPLICATION DATA ,,, ," ," ," II *Each starred block may be either a basic bit-slice Wallace tree('LS275 or 'S275 only) or a high-speed bit-slice Wallace tree ('LS275 plus 1/2 'LS183 or 'S275 plus 1/2 'H183). In either case the function of the terminal is the same as the similarly located terminal of the basic bit-slice (Figure 1) or high-speed bit-slice Wallace tree (Figure 2). Also for either tree, when only five inputs of the seven-input adder of the 'LS275/'S275 are used, the remaining two inputs must be grounded. When the high-speed adder is used, the C2 n inputs of the 'LS275/'S275 must be grounded. tFor improved performance SN74LS181/SN74S181 ALUs with SN74S182 look-ahead generators can be substituted SN74283/SN74LS283/SN74S283 adders. Typically, the multiplication time will be reduced by 18 to 32 nanoseconds. for the FIGURE 10-16-BIT X 16-BIT MULTIPLIER (SHEET 3 OF 3-SUMMING PARTIAL PRODUCTS) 1076 74DO TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS BULLETIN NO. DL·S 7612460, OCTOBER 1976 SN54276 ... J PACKAGE SN74276 ••• J OR N PACKAGE (TOP VIEW) features • Four J-K Flip-Flops in a Single Package ... Can Reduce FF Package Count by 50% • Separate Negative-Edge-Triggered Clocks with Hysteresis ... Typically 200 mV • Typical Clock Input Frequency ... 50 MHz • Fully Buffered Outputs VCC 4J 4CK 4K 40 30 3K 3CK 3J PRESET CLEAR lJ lCK lK 10 20 2K 2CK 2J GND description These quadruple TTL J-K flip·flops incorporate a number of third-generation Ie features that can simplify system design and r~duce flip·flop package count by up to 50%. They feature hysteresis at each clock input, fully buffered outputs, and direct clear capability, and are presettable through a buffer that also features an input hysteresis loop. The negativeedge-triggering clocks are directly compatible with earlier Series 54/74 single and dual pulse-triggered flip-flops. These circuits can be used to emulate D- or T-type flip-flops by hard-wiring the inputs, or to implement asychronous sequential functions. schematics of inl?uts and outputs EOUIVALENT OF EACH INPUT vce------ INPUT The SN54276 is characterized for operation over the full military temperature range of _55°C to 125°C; the SN74726 is characterized for operation from oOe to 70°C. Clear, J, FUNCTION TABLE (EACH FLIP-FLOP) INPUTS COMMON INPUTS K: = 4 kn NOM = 10.2 kn NOM Req = 11.6 kn NOM Req Clock: Req Preset: OUTPUT PRESET CLEAR CLOCK J K Q • TYPICAL OF ALL OUTPUTS vee L H X X X H H L X X X L L X X X L Ht H H 1- L H 00 H H 1- H H H H H 1- L L L H H 1- H L TOGGLE H H H X X 00 Q tThis configuration is nonstable; that is, it may not persist when preset and clear return to their inactive (high) level. See explanation of function tables on page 3-8. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) .... . I nput voltage ............ . Operating free-air temperature range: SN54276 SN74276 Storage temperature range . .... 7 V . . . . 5.5 V . _55°C to 125°C oOe to 70°C . -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-401 TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS recommended operating conditions SN54276 SN74276 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -800 J.lA Supply voltage, VCC -800 High-level output current, 10H 16 Low-level output current, 10L Clock frequency 0 Clock high 13.5 13.5 Clock low 15 15 Preset or clear low 12 12 J, K inputs Setup time, tsu Clear and preset inactive state Input hold time, th 3~ 3~ 10~ 10~ 10~ 10~ -55 Operating free-air temperature, T A ~ 35 0 Pulse width, tw UNIT MIN 125 16 mA 35 MHz ns ns ns °c 70 0 The arrow indicates that the falling edge of the clock pulse is used for reference_ electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH • MIN TYPt MAX UNIT 2 High-level output voltage VCC = MIN, 11=-12mA VCC - MIN, VIH - 2 V, VIL = 0.8 V, 10H = -800J.lA VCC = MIN, VIH = 2 V, VIL = 0.8 V, 10L = 16mA 2.4 V 0.8 V -1.5 V 3.4 V VOL Low-level output voltage II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 IIH High-level input current VCC = MAX, VI = 2.4 V 40 J.lA IlL Low-level input current VCC= MAX, VI = 0.4 V -1.6 mA lOS Short-circuit output current Ii VCC = MAX -85 mA Ice Supply current Vee = MAX 81 mA 0.2 0.4 -30 60 V mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at Vee = 5 V, T A = 25° C. §Not more than one output should be shorted at a time. switching characteristics, Vee = 5 V, T A =25° C PARAMETER TEST 'CONDITIONS MIN TYP 35 50 MAX UNIT f max Maximum clock frequency tpLH Propagation delay time, low-to-high-Ievel output from preset eL=15pF, 15 25 tpHL Propagation delay time, high-to-Iow-Ievel output from clear RL=400n, 18 30 ns tpLH Propagation delay time, low-to-high-Ievel output from clock See Note 2 17 30 ns tpHL Propagation delay time, high-to-Iow-Ievel output from clock 20 30 ns MHz ns NOTE 2: Load circuit and voltage waveforms are shown on page 3-10. 1076 7-402 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS BULLETIN NO. DL-S 7211729, MAY 1972-REVISED DECEMBER 1972 • SN54278 ••• J OR W PACKAGE SN74278 ••• J OR N PACKAGE ITOP VIEW) Latched Data Inputs Serve as Buffer Register and Can also: Synchronize Data Acquisition "Debounce" Mechanical Switch Input • Cascading Input PO and Output P1 Provides "Busy"Signal Inhibiting All Lower-Order Bits • Full TTL Compatibility • Use for: Priority Interrupt Synchronous Priority Line Selection OUTPUTS INPUTS vcc~ NC~ ~~GNO INPUTS description OUTPUTS positive logic: see function table The SN54278 and SN74278 each consist of four data latches, full priority output gating, and a cascading gate. The highes,t-order data applied at a D latch input is transferred to the appropriate Y output while the strobe input is high, and when the strobe goes low all data is latched. The cascading input PO is fully overriding and on the highest-order package this input must be held at a low logic level. The P1 output is intended for connection to the PO input of the next lower-order package and will provide a "busy" (high-level) signal to inhibit all subsequent lowerorder packages. NC-No internal connection FUNCTION TABLE PO G 01 02 03 04 01 02 03 04 V1 V2 V3 V4 P1 L H H X X X L X X X H L L L H L H L H X X H L X X L H L L H L H L L H X H H L X L L H L H L H L L L H H H H L L L L H H L H L L L L H H H H L L L L L L L X H L X H OUTPUT PI OUTPUT V4 X X Latched when H = high X X level, L = low level, X 03 OUTPUT OUTPUT V2 V3 L L L L H L L L L H II = irrelevant INPUT INPUT 02 INPUT nodes as on 1st 5 lines X Internal Q levels are same function of 0 inputs as on first 5 lines functional block diagram INPUT 04 X G goes low H STROBE G OUTPUTS LATCH NODES Same function of 0 After the overriding PO input, the order of priority is D1, D2, D3, and D4, respectively, within the package. INPUT PO INTERNAL INPUTS 01 OUTPUT VI 1272 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 7-403 TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) Input voltage . . . . . . . . Interemitter voltage (see Note 2) Operating free-air temperature range: SN54278 Circuits SN74278 Circuits Storage temperature range NOTES: 7V 5.5 V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C 1. Voltage values. except interemitter voltage. are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit. this rating applies between the strobe input and any of the four data inputs. recommended operating conditions SN54278 MIN Supply voltage, Vee 4.5 5 High-level output current, 10H 5.5 -800 Low-level output current, 10L Data setup time, tsu SN74278 NOM MAX MIN NOM MAX 4.75 5 16 (see Figure 11 Operating free-air temperature, T A V /JA 16 mA 20 20 ns 5 5 ns 20 20 Data hold time, th (see Figure 1) Strobe pulse width, tw (see Figure 11 UNIT 5.25 -800 -55 125 ns 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • TEST CONDITIONSt VIH High-level input voltage VIL VIK Low-level input voltage Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage IIH High-level input current MIN TYP MAX UNIT 2 Vee= MAX, 11=-12mA Vee= MIN, VIH = 2 V, VIL = 0.8 V, 10H = -800/JA Vee= MIN, VIH = 2 V, VIL = 0.8 V, IOL=16mA Vee = MAX, VI = 5.5 V Vee= MAX, VI = 2.4 V 2.4 V 0.2 lee Supply current 0.4 200 V /JA 320 -3.2 PO input Vee = MAX, -8 mA VI = 0.4 V G input Short-circuit output current§ V 80 PO input Any D input lOS V 1 mA G input Low-level input current V -1.5 3.4 Any D input IlL 0.8 l SN54278 Vee = MAX I SN74278 Vee = MAX, See Note 3 -12.8 -18 -55 -18 -57 55 mA 80 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. :j:AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time. NOTE 3: lee is measured with the PO input grounded, all other inputs at 4.5 V, and outputs open. 1076 7-404 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS switching characteristics, Vee = 5 V, TA = 25°e FROM (INPUT) PARAMETER~ tpLH WAVEFORMS Data Y A andC (with strobe high) Data Y tpHL tpLH tpHL tpLH tpLH tpLH tpHL tpLH tpHL MIN CONDITIONS TYP MAX UNIT 30 A and D 38 (with strobe high) 31 A and E 46 CL= 15pF. Band C P1 Band E PO P1 F and G ns ns 39 RL = 400.n. See Figure 1 or Band D Strobe ns 39 (with strobe high) AnyY Strobe tpHL ~tpLH tpHL P1 Data tpHL TEST TO (OUTPUT) 30 ns 31 38 ns 42 23 ns 30 == propagation delay time. low-to-high-Ievel output == propagation delay time. high-to-Iow-Ievel output schematics of inputs and outputs PARAMETER MEASUREMENT INFORMATION Vee EQUIVALENT OF EACH INPUT VCC---4II---_ ~CL-15PF C L includes probe and jig capacitance. INPUT All diodes are 1 N3064. LOAD CIRCUIT r : STROBE INPUT G (WAVEFORM 8) I00--.I-'. ~ t •• I I r--l,u I r--"'---1 iWAVEFORM C) I :--"'-- .......--.;-tpLH I I 1.S~ I ! ~~~~~~ERTING I ~,-.S_V_ _ _ _..; ~:;:EI~~~ ~I ~.5 v Any 0: Req = 2.5 k.n NOM PO: Req = 1 k.n NOM G: Req = 0.6 k.n NOM ........---.,-IfHl r---7---:'-"""~;:v----- --f"--,----J I TYPICAL OF ALL OUTPUTS INVERTING OUTPUT (WAVEFORM 01 -~'--VCC I ~IPHl I I I QUTPUTPl IWAVEFORM EI VOH I 1.SV ~~HL~ '----:-\.--tP-L-:H;..-'--J.'-1-- - - - - I ; ~tpLH--i I I ' /'.5 V : t..-tPLH~ :~~~TE~~AMfI~SV OUTPUTPl IWAVEFORMGI _ _ _ _ _ - VOL to--tPHL"'" 4 - - - - - - - VOH ~ l..--tPHL-----l VOL ~s~-------- ~tPlH~ OUTPUT VOH VOL t.-tpLH~ I , ,.....tpHl...., lr.r-----~~,_5V ..J/'sv - ~ VOH VOL VOLTAGE WAVEFORMS NOTE: Input pulses are supplied by a generator having the following characteristics: tr';; 7 ns. tf';; 7 ns. PRR .;; 1 MHz. Zout "" 50 .n. FIGURE 1-SWITCHING TIMES 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-405 TYPES SN54LS280, SN54S280, SN74LS280, SN74S280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS TTL MSI BULLETIN NO. DL-S 7611829, DECEMBER 1972-REVISED OCTOBER 1976 SN54LS280, SN54S280 ••• J OR W PACKAGE SN74LS280, SN74S280 ••• J OR N PACKAGE (TOP VIEW) • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits • Can Be Used to Upgrade Existing Systems using MSI Parity Circuits • Typical Data-to-Output Delay of Only 14 ns for 'S280 and 33 ns for 'LS280 • Typical Power Dissipation: 'LS280 ... 80 mW 'S280 ... 335 mW FUNCTION TABLE NUMBER OF INPUTS A ~ OUTPUTS THRU I THAT ARE HIGH LEVEN L ODD 0,2,4,6,8 H L L H 1,3,5,7,9 H = high level, L = low NC I ~ ~ GND ;NPUT~ INPUTS OUTPUTS logic: see function table level NC-No internal connection description These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading as shown under typical application data. Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the corresponding function is provided by the availability of an input,at pin 4 and the absence of any internal connection at pin 3. This permits the 'LS280 and 'S280 to be substituted for the '180 in existing designs to produce an identical function even if 'LS280's and 'S280's are mixed with existing '180's. II These devices are fully compatible with most other TTL and DTL circuits. All 'LS280 and 'S280 inputs are buffered to lower the drive requirements to one Series 54LS/74LS or Series 54S/74S standard load, respectively. schematics of inputs and outputs o 'LS280 EQUIVALENT OF INPUTS VCC INPUT 'S280 TYPICAL OF OUTPUTS EQUIVALENT OF INPUTS TYPICAL OF OUTPUTS -----VCC ---""",-Vcc VCC1 3k!l - -NOM 2.8 20 k!l NOM __ INPUT OUTPUT -- OUTPUT 1076 7-4D6 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS280, SN74LS280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note 1) Input voltage . . . . . . ...... . Operating free·air temperature range: SN54LS280 SN74LS280 Storage temperature range NOTE1: 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS280 MIN Supply voltage, Vee 4.5 NOM MIN 5.5 4.75 5 High·level output current, 10H SN74LS280 MAX NOM 5 MAX 5.25 -0.4 Low-level output current, 10L -55 125 0 V .4 rnA 8 rnA 70 °e 4 Operating free-air temperature, T A UNIT electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS280 PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage TEST eONDITIONSt MIN TYP+ SN74LS2BO MAX MIN 11= -18 rnA Vee = MIN, VIH-2V, VIL = MAX, 10H = -0.4 rnA Vee - MIN, VIH-2V, VOL Low-level output voltage II Input current at maximum input voltage Vee = MAX, VI = 7 V IIH High-level input current Vee = MAX, VI = 2.7 V IlL Low-level input current Short-circuit output current!? Vee = MAX, Vee= MAX VI = 0.4 V lOS ICC Supply current Vee = MAX, See Note 2 2.5 UNIT MAX V 2 2 Vee = MIN, TYP+ 0.7 0.8 V -1.5 -1.5 V 2.7 3.4 0.25 3.4 0.25 0.4 VIL = MAX 0.35 -20 0.4 0.5 V 0.1 0.1 mA 20 -0.4 20 IJA -0.4 rnA -100 rnA rnA -100 16 V -20 27 16 27 TYP MAX 33 50 29 45 23 35 31 50 I tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII tYpical values are at V CC ~ 5 V, T A = 25° C. §Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with all inputs grounded and all outputs open. switching characteristics, Vee PARAMETERl1 tpLH tpHL tpLH tpHL = 5 V, T A = 25°e FROM TO (INPUT) (OUTPUT) Data ~ Even TEST CONDITIONS MIN eL=15pF,RL=2kn., I nputs not under test at 0 V, Data ~ Odd See Note 3 UNIT ns ns 11 tpLH ;; propagation delay time, low-to-high-Ievel output; tpH L ;; propagation delay time, high-to·low-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-407 TYPES SN54S280, SN14S280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS REVISED DECEMBER 19BO absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (see Note 1) ....... . Input voltage . . . . . ....... . Operating free·air temperature range: SN54S280 SN74S280 Storage temperature range 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S280 MIN Supply voltage, Vee NOM 4.5 SN74S280 MAX MIN 5.5 4.75 5 High·level output current, 10H NOM 5 -1 Low-level output current, 10L 20 Operating free·air temperature, T A -55 125 0 MAX UNIT 5.25 V -1 mA 20 mA 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER II VIH High·level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage TEST eONDITIONSt MIN TVPt MAX 2 Vee = MIN, II = -18mA Vee = MIN, VIH = 2 V, l SN54S' VIL = 0.8 V, 10H = -1 mA Vee - MIN, VIH-2V, VIL = 0.8 V, 10L = 20mA J SN74S' UNIT V 2.5 3.4 2.7 3.4 0.8 V -1.2 V V VOL Low-level output voltage II Input current at maximum input voltage Vee= MAX, VI = 5.5V 1 IIH High·level input current Vee = MAX, VI = 2.7 V 50 J.LA IlL Low-level input current Vee = MAX, VI=0.5V -2 mA lOS Short·circuit output current§ Vee= MAX -100 mA -40 Vee = MAX, See Note 2 ICC Supply current 0.5 Vee - MAX, TA = 125°C, See Note 2 SN54S280 67 99 SN74S280 67 105 94 SN54S280N V mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAil typical values lire at V CC = 5 V, T A = 25° C. §Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with all inputs grounded and all outputs open. switching characteristics, PARAMETERlI tpLH tpHL tpLH Vee = 5 V, TA = 25° e FROM TO (INPUT) (OUTPUT) Data l: Even Data l:Odd TEST CONDITIONS eL = 15pF, RL = 280 MIN n, See Note 4 tPHL TVP MAX UNIT 14 21 11.5 18 14 21 11.5 18 ns ns lI tPLH == propagation delay time, low-to-high-Ievel output; tpHL == propagation delay time, high·to·low·level output NOTE 4: Load circuit and voltage waveforms are shown on page 3·10. 1280 7-408 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS280, SN54S280, SN74LS280, SN74S280 9-81T ODD/EVEN PARITY GENERATORS/CHECKERS functional block diagram ~ EVEN l: ODD TYPICAL APPLICATION DATA 81-LlNE PARITY/GENERATOR CHECKER 25·LlNE PARITY/GENERATOR CHECKER Three 'LS280's or 'S280's can be Longer word lengths can be imple- used to implement a 25-line paritY mented generator/checker_ This arrangement 'S280's_ As shown here, parity can be will provide paritY in typically 75 or A B C 25 nanoseconds respectively_ 'LS280's or I bits in tYpically 75 or 25 nano- ); l: D E EVEN seconds respectively_ F G 'LS280/ 'S280 A B C D E F G H cascading generated for word lengths up to 81 A EVEN A B C D E F G by H I ~ EVEN A B C D H = EVEN L=ODD 'LS280/ '5280 A B l: EVEN ); D E E l: ODD 'LS280/ 'S280 H =ODD L = EVEN F G F G 'LS280/ '5280 EVEN ); ODD 'LS280/ '5280 H = EVEN L=ODD H = EVEN L=ODD A l: EVEN ); As an alternative, the outputs of two or EVEN three paritY generators/checkers ~ can be decoded with a 2-input ('S86 'LS280/ 'S28 0 'LS86) 3-input ('S135) 'LS280/ 'S280 exclusive-OR gate for 18- or 27-line TO OTHER 'LS280/ 'S280 parity applications. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·409 TYPES SN54S281, SN74S281 4-BIT PARALLEL BINARY ACCUMULATORS TTL LSI BULLETIN NO. DL-S 7612065, FEBRUARY 1974 - REVISED OCTOBER 1976 • Full 4-Bit Binary Accumulator in a Single Package • 15 Arithmetic/Logic-Type Operations: -Add Subtract (B-A or A-B) -Complement -Increment Transfer Plus 10 Other Functions SN54S281 •.• J OR W PACKAGE SN74S281 ••• J OR N PACKAGE (TOP VIEW) Vee (OAT~J ~AV CLOCK CO~~~~L RINI ~M~ OATAOU1PUTS lOUT • Full Shifting Capabilities: \., ,,( Logic Shift (Left or Right) Arithmetic Shift (Left or Right) for Sign Bit Protection Hold Parallel Load • • Expandable to Handle n-Bit Words with Full Carry Look-Ahead logic: see description and function tables Logic Mode Operation Provides Seven Boolean Functions of the Two Variables description These Schottky-clamped four-bit accumulators integrate high-performance versions of an arithmetic logic unit/function generator and a shift/storage matrix on a single monolithic circuit bar. The arithmetic logic unit (ALU) portion, similar to the SN54S181/SN74S181 circuit, incorporates the capability to perform 16 arithmetic/logic-type operations as detailed in Table 1. The accumulator includes an exchange of subtract operands by which either A-8 or 8-A can be accomplished directly. The ALU is controlled by three function-select inputs (ASO, AS1, AS2) and a mode-control input (M). When the mode-control input is hi.9h, the ALU is placed in a logic mode that performs any of seven logic functions on two binary variables as detailed in Table 2. Full carry look-ahead is provided for fast, simultaneous carry generation for the full four binary bits. The carry input (C n ) and propagate and generate outputs ('P, (3) are implemented for direct use with the SN54S182/SN74S182 look-ahead carry generators. This permits systems to be Implemented with the added advantage of full look-ahead across any word length to minimize the accumulator delay times. Once data is loaded into the accumulator, the typical add time with full look-ahead is 29 nanoseconds for 16-bit words. I The shift/storage matrix is analogous in its capabilities to the SN54S194/SN74S194 universal bidirectional shift register with the added advantages of multiplexed input/output (I/O) cascading lines that cbmprehend arithmetic shift functions having a sign bit, such as 2's complements. The matrix can be used to perform either logic or arithmetic shifts in either direction (left or right). parallel load, or hold. Control of the register is accomplished with three inputs: register control (RC) and register selection (RSO, RS1). The cascading input/output lines incorporate three-state outputs multiplexed with an input. The least-significant cascading bit is combined with the AO, FO circuitry to provide the shift·right input and the shift-left output (R I/LO), and the most significant bit is coupled with the A3, F3 circuitry to provide the shift-left input and the shift-right output (L1/RO). Series 54S circuits are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74S circuits are characterized for operation from O°C to 70°C. 1076 7·410 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S281, SN74S281 4-BI1 PARALLEL BINARY ACCUMULATORS FUNCTION TABLES TABLE 1-ARITHMETIC FUNCTIONS TABLE 2-LOGIC FUNCTIONS Mode Control (M) = Low ALU ACTIVE-HIGH OATA SELECTION Cn=H AS2 AS1 ASO (with carry) L Mode Control (M) = High Carry Input (C n ) = X !Irrelevant) = L, Cn = L (no carry) = F2 = F3 = H ALU L L L L H F = B MINUS A F = B MINUS A MINUS 1 L L L L H L F = A MINUS S F = A MINUS S MINUS 1 L X H L Fa Fl ACTIVE-HIGH SELECTION Fn = H AS2 AS1 ASO = A PLUS~6") q '"J.. DATA FUNCTION ~:. = An 0 Sn Fn = An <±> Sn Qn=-L;, Fn L H H F = A PLUS B PLUS 1 F L H H L L F = S PLUS 1 Fn = Bn H L L H L ,H F = S PLUS 1 H L H H H L ' F~.A ~LuSi-:::-O\"1 Fn = Sn F.n = ~n H H L Fn H H H H H H Fn = An F = A PLUS 1 Fn = An' ~,~~= A~B~-~ __ , ~ Fn = An + Sn = AnSn + Sn TABLE 3 - SHIFT-MODE FUNCTIONS C n = M = ASO = AS1 = L, and AS2 = H IFn = Bn) INPUTS BEFORE t FUNCTION REGISTER SELECTION RSO RS1 REGISTER INPUTI CONTROL OUTPUT OUTPUTS AFTER t INPUTI SHIFT-MATRIX OUTPUT INPUTS CLOCK INPUT SHIFT-MATRIX INPUTI INPUTI OUTPUTS OUTPUT OUTPUT (ALU B INPUTS) INPUT RI/LO FO F1 F2 F3 QD L L X Z to f1 f2 f3 Z t Z to QB. f1 QC LOAD f2 f3 Z '-LSL:--- L H L QA QA QS QC QO Ii t QS n QCn QDn Ii Ii ~-, QS n L H H QA QS QC QO Ii t 000 Ii L L QA Os QC QO 00 t °Sn ri Ii H QS n ri °Cn RSL QA ri °An °sn °Cn QCn ri QS n ~.-- I ,-RSA"--HOLD Ll/RO ' RI/LO QA Ll/RO H L H ri 00 QC t ri °An °Sn QOO H X X °A QS QA Os QC H QC QO t Z QAO °SO Qco QOO Z X X X X QA °c 00 X X L RI/LO °AO °SO nCo 000 Li/RO Os II H = high level (steady state) L = low level (steady state) = irrelevant (any input, including transitions) = high impedance (output off) t = transition from low to high level X Z fO, f1, f2, f3, ri, Ii = the level of'steady-state conditions at FO, F1, F2, F3, RI/LO, or LI/RO respectively 0AO. 0SO, 0eo, 0 0 0 = the level of 0A, OS. 0e, or 00. respectively, before the indicated steady-state input conditions were established 0An. 0Sn' 0en' 00n = the level of 0A. 0B, 0e, or 0 , respectively. before the most recent transition of the clock See explanation of function tables on page 3-8. ° absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage ••••••...•• •••••••..•.•. • • . . • • Operating free-air temperature range: SN54S281 (see Note 2) SN74S281 Storage temperature range NOTES: 7V 5.5V -55°C'to 125°e aOe to 7aoe -65°e to 15aoe 1, Voltage values are with respect to network ground terminal. 2. An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal o resistance from case to free-air, RaCA' of not more than 20 C/W. 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-411 TYPES SN54S281, SN74S281 4-BIT PARALLEL BINARY ACCUMULATORS recommended operating conditions SN54S281 Supply voltage, Vee SN74S281 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 Any output except LI/RO and RI/LO High-level output current, 10H Low-level output current, 10L -1 -1 LI/RO and RI/LO -2 -2 Any output except LI/RO and RI/LO 20 20 LI/RO and RI/LO 10 Clock frequency, fclock (for shifting) 0 50 10 0 50 UNIT V mA mA MHz Width of clock pulse, tw(clock) 8 8 ns Data setup time with respect to clock, tsu ot ot ns 18t 18t Data hold time with respect to clock, th Operating free-air temperature, T A (see Note 2) -55 125 ns 0 70 °e tThe arrow indicates that the rising edge of the clock pulse is used for reference. NOTE 2: An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal resistance from case to free-air, ReCA' of not more than 20°C/W. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage High-level VOH I output voltage Any input except LI/RO and RI/LO Any output except LI/RO, RIILO II Input current at maximum input voltage input current TYP:j: input current ICC V 0.8 V -1.2 -1.2 V Vee; MIN, VIH;2V, 2.5 3.4 2.7 3.4 VIL; 0.8 V, 10H; MAX 2.4 3.4 2.4 3.4 Vee; MIN, VIH; 2 V, VIL; 0.8 V, 10L; MAX V Vee; MAX, VI;5.5V 0.5 0.5 1 1 RSO, RSl 50 50 M, Clock 150 150 LI/RO, RI/LO AS2 RI/LO M, Clock ASO,ASl UNIT 0.8 Vee; MIN, Vee; MAX, VI;2.7V, See Note 3 Vee; MAX, VI ;0.5V See Note 3 All others lOS TYP:j: MAX II; -18mA All others IlL MIN 2 RSO, RS1, LI/RO Low-level SN74S281 MAX LI/RO and RI/LO Low-level output voltage IIH SN54S281 MIN 2 VOL High-level TEST CONDITIONSt 200 200 300 300 250 250 -2 -2 -3 -3 -4 -4 -6 -6 -8 Short-circuit output current§ Vee; MAX Supply current Vee; MAX,' W package TA; 125°C only -40 Vee; MAXi All packages -110 230 /LA mA -8 -40 -110 190 144 V mA mA mA 144 230 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC ; 5 V, T A ; 25° C. § N ot more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. NOTE 3. When testing input current at the RI/LO or Ll/RO terminals, the output under test must be in the high-impedance (off) state. 1076 7·412 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S281, SN74S281 4-BIT PARALLEL BINARY ACCUMULATORS switching characteristics, Vee PARAMETER~ tpLH tpHL tpLH =5 V, T A = 25° C FROM TO (INPUT) (OUTPUT) Cn Cn+4 Any A Cn +4 tpHL tpLH Cn tpHL TYP Any F - MAX UNIT 10 20 10 20 18 30 18 30 10 20 10 20 14 24 14 24 tpLH 12 20 12 20 20 35 Any A G Any A P Ai Fi tpHL tPLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH AO RI/LO A3 LlIRO FO RI/LO F3 Ll/RO Any AS tpHL tpLH Any AS tpHL tpLH Clock tpLH 35 30 45 1/0 outputs: R L = 560 30 45 Other outputs: 30 45 30 45 7 11 7 11 CL=15pF, n, RL = 280 n, See Figure 1 7 11 7 11 Any F or 28 45 Cn+4 28 45 Any F Clock tpHL == Propagation delay == Propagation delay 20 PorG tpHL tpHL MIN tpHL tpLH ~tpLH TEST CONDITIONS 20 33 20 33 30 45 30 45 RI/LOor 35 55 Ll/RO 35 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns I time, low-to-high-Ievel output time, high-to-Iow-Ievel output PARAMETER MEASUREMENT INFORMATION INPUT ~.;:V-- -I"f'.JV -3V ~OV :'-tPLH-.I !-tPHL""1 IN.PHAS~I I : -:--VOH OUTPUT i 1.5 V I I I 1.5 V VOL I t-tPLH~ r-tPHL-t : ~ OUT·OF·PHASE OUTPUT iVOH 1.5 V 1.5 V - - -VOL LOAD CIRCUIT VOLTAGE WAVEFORMS NOTES: A. Input pulse is supplied by a generator having the following characteristics: tr';;; 2.5 ns, tf';;; 2.5 ns, PRR .;;; 1 MHz, Zout '" 50 B. CL inlcudes probe and jig capacitance. C. All diodes are 1N916 or 1N3064_ n. FIGURE 1 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·413 TYPES SN54S281, SN74S281 4-BIT PARALLEL BINARY ACCUMULATORS TYPICAL APPLICATION DATA RIGHT DATA IN CARRY INPUT RI/LO L1/RO RI/LO L1/RO RI/LO C n+4 Cn Cn+4 Cn Cn +4 L1/RO Cn Cn+4 'S281 'S281 'S281 'S281 RI/LO L1/RO LEFT DATA IN CARRY OUTPUT ENTER AND STORE TIME: 38 ns typical EACH SUCCESSIVE ADDITION TO STORED DATA: 44 ns typical FIGURE A-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS IN RIPPLE-CARRY MODE RIGHT DATA IN CARRY INPUT RI/LO RI/LO L1/RO Cn 'S281 Cn G P C n +x L1/RO RI/LO L1/RO 'S281 RI/LO Cn L1/RO 'S281 Cn+4 LEFT DATA IN CARRY OUT P Cn+y 'S182 ENTER AND STORE TIME: 37 ns typical EACH SUCCESSIVE ADDITION TO STORED DATA: 29 ns typical FIGURE B-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS AND ONE SN54S182/SN74S182 IN FULL LOOK-AHEAD CARRY MODE I RIGHT DATA IN CARRY INPUT RI/LO Cn L1/RO 4 'S281s RI/LO Cn 4 'S281s RI/LO L1/RO Cn 4 'S281s 'S182 G P L1/RO 4 'S281s Cn+4 LEFT DATA IN CARRY OUT 'S182 G P C n +y 'S182 ENTER AND STORE TIME: 42 ns typical EACH SUCCESSIVE ADDITION TO STORED DATA: 34 ns typical FIGURE C-64-BIT BINARY ACCUMULATOR USING 16 SN54S281/SN74S281 CIRCUITS AND FIVE SN54S182/SN74S182 CIRCUITS FOR FULL CARRY LOOK-AHEAD A inputs and F outputs of '5281 are not shown. 877 7-414 TYPES SN54283, SN54LS283, SN54S283, SN74283, SN74LS283, SN74S283 4-BIT BINARY FULL ADDERS WITH FAST CARRY TTL MSI BULLETIN NO. DL-S 7611832, OCTOBER 1976 • Full-Carry Look-Ahead Across the Four Bits • Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry • SN54283, SN54LS283 ••• J OR W PACKAGE SN54S283 ••• J PACKAGE SN74283, SN74LS283, SN74S283 ••• J OR N PACKAGE (TOP VIEW) Vee 83 A3 t3 A4 54 t2 82 A2 t1 A1 B1 e4 Supply Voltage and Ground on Corner Pins to Simplify P-C Board Layout TYPICAL ADD TIMES TYPE TWO TWO TYPICAL POWER 8-BIT 16·BIT DISSIPATION WORDS WORDS PER ADDER '283 23ns 43ns 310 mW 'LS283 25ns 45ns 95 mW 'S283 15ns 30ns 510 mW eo GNO positive logic: see function table description The '283 and 'LS283 adders are electrically and functionally identical to the '83A and 'LS283 , respectively; only the arrangement of the terminals has been changed. The 'S283 high performance versions are also functionally identical. FUNCTION TABLE OUTPUT % l74 % %l% % %E6:r% l% E%: % co- L INPUT co- H WHEN These improved full adders perform the addition of two 4-bit binary words. The sum (~) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look-ahead across all four bits generating the carry term in ten nanoseconds, typically, for the '283 and 'LS283, and 7.5 nanoseconds for the 'S283. This capability provides the system designer with partial look-ahead performance at the economy and reduced package count of ripple-carry implementation. A<1 83 L The adder logic, including the carry, is implemented in its true form. End around carry can be accomplished without the need for logic or level inversion. Series 54, Series 54LS, and Series 54S circuits are characterized for operation over the full temperature range of -55°C to 125°C. Series 74, Series 74LS, and Series 74S circuits are characterized for O°C to 70°C operation. WHEN •. C"L L L 84 1:3 C .... U 1:4 L L L L H L L H L L L H L L L H L L H L L H L L L H L H H L L L H L H H L L L H L L H L H H L H L H L H H L L L H L H H L H H L L L H H H H L L L H H L L L L H L H L H H L H L L H H H L L L H I H L H L H H H L L L H H H L H L L H H L H L L H H L L H H L H H L H H H L H L H H L H H H H L H L H H H H H H L H H H H H hivel, L = low level NOTE: Input conditions at A1, B1. A2, B2, and CO are used to determine outputs ~1 and ~2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs l:3, ~4, and C4. H = high 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • CALLAS. TEXAS 75222 7-415 TYPES SN54283, SN54LS283, SN54S283, SN74283, SN74LS283, SN74S283 4-BIT BINARY FULL ADDERS WITH FAST CARRY functional block diagram and schematics of inputs and outputs '283 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT ------VCC V C CReq 3-INPUT -OUTPUT CO input: Req Any A or 8: Req = 4 kn NOM = 3.5 kn NOM C4 output: R = 100 n NOM Any ~: A = 120 n NOM 'LS283 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC--.....- - ----~-VCC Req I NPUT_,....-+-_>_ OUTPUT CO input: Req = 17 kn NOM Any A or 8: ReQ = 8.5 kn NOM 'S283 EQUIVALENT OF EACH INPUT I TYPICAL OF ALL OUTPUTS ------4'--VCC VCC1 2.83 kn- NOM INPUT -- OUTPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage: '283, 'S283 'LS283 . . . . Interemitter voltage (see Note 2) Operating free-air temperature range; SN54283, SN54LS283, SN54S283 _ SN74283, SN74LS283, SN74S283 . Storage temperature range NOTES: 7V 5.5V 7V 5.5V __55°C to 125°C oOe to 70°C _-65°e to 150°C 1. Voltage values, except interemitter voltage,.are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '283 and '5283 only between the following pairs: Aland 81, A2 and 82, A3 and 83, A4 and 84. 1076 7-416 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX !5012 • DALLAS, TEXAS 75222 TYPES SN54283. SN74283 4-BIT BINARY FULL ADDERS WITH FAST CARRY recommended operating conditions SN54283 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 Supply Voltage, VCC High·level output current, IOH SN74283 MIN Any output except C4 -800 -800 Output C4 -400 -400 16 16 Any output except C4 Low-level output current, IOL Output C4 8 Operating free·air temperature, T A -55 125 8 0 70 UNIT V J.1.A mA °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low·level output voltage SN54283 TEST CONDITIONSt MIN TYP+ SN74283 MAX 2 VCC = MIN, 11=-12mA VCC = MIN, VIH VIL = 0.8 V, 10H Vee Input current at maximum = MIN, = 2 V, = MAX 2.4 VIH = 2 V, VIL = 0.8 V, IOL TYP+ MAX UNIT V 2 0.8 0.8 V -1.5 -1.5 V 3.6 2.4 0.2 = MAX MIN 0.4 3.6 0.2 V 0.4 V VCC = MAX, VI = 5.5 V 1 1 IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 J.1.A IlL Low-level input current VCC = MAX, VI = 0.4 V -1.6 -1.6 mA II input voltage Short·circuit lOS output current§ LAny output except e4 I Output C4 Vce = MAX -20 -55 -18 -55 -20 -70 -18 -70 All B low, other ICC VCC Supply current = MAX, 56 inputs at 4.5 V mA mA 56 mA Outputs open All inputs at 66 4.5 V 99 66 110 I tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5. V, T A = 25°e. §Only one output should be shorted at a time. switching characteristics, Vee PARAMETER~ tpLH =5 V, T A = 25°e FROM (INPUT) CO TO (OUTPUT) Any ~ TEST CONDITIONS tpHL CL=15pF, tpLH See Note 3 Ai orBi ~i CO C4 RL=400n, tpHL CL=15pF, tpLH See Note 3 tpHL Ai or Bi MIN TYP MAX 14 21 12 21 16 24 16 24 9 14 UNIT ns ns tpHL tPLH I C4 RL = 780 n, ns 11 16 9 14 11 16 ns ~ tpLH ;= Propagation delay time, low-to-high·level output tpH L ;= Propagation delay time, high-to-Iow·level output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7417 TYPES SN54LS283, SN74LS283 4-BIT BINARY FULL ADDERS WITH FAST CARRY recommended operating conditions SN54LS283 Supply voltage, Vee MIN NOM 4.5 5 High-level output current,lOH SN74LS283 MAX MIN NOM 5.5 4.75 5 -400 Low-level output current, 10L MAX 5.25 V -400 /JA S mA 70 °e 4 Operating free-air temperature, T A -55 125 UNIT 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage IIH IlL lOS II = -1SmA Vee= MIN, VIH = 2V, VIL = VIL max, VIH = 2 V, 10L =4mA Vee= MIN, 10L VIL = VIL max 2.5 SN74LS283 MAX Vee= MAX, Any A or B input current eo Low-level Any A or B input current eo Short-circuit output current§ Vee= MAX, Vee= MAX, MAX UNIT V 2 O.S V -1.5 -1.5 V 3.4 2.7 0.25 0.4 3.4 V 0.25 0.4 0.35 0.5 0.2 0.2 0.1 0.1 40 40 V mA VI = 7V VI = 2.7 V VI = 0.4 V 20 20 -O.S -O.S -0.4 Vee= MAX -100 -20 grounded Supply current TYP:j: 0.7 eo High-level MIN = SmA All inputs lee TYP:j: Any A or B at maximum input voltage Vee= MIN, 10H = -400/JA VOL Low-level output voltage II MIN 2 VOH High-level output voltage Input current SN54 LS283 TEST CONDITIONSt PARAMETER Vee= MAX, All B low, other Outputs open inputs at 4.5 V All inputs at I 4.5V -0.4 -100 -20 22 39 22 39 19 34 19 34 19 34 19 34 /JA mA mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°e. §Only one output should be shorted at a time and duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER~ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT 16 24 tPHL 15 24 tPLH 15 24 15 24 tpLH eo Any I: Aj or Bi I:j eo e4 eL=15pF, tPHL tPLH tpHL tPLH tpHL Ajor Bi See Note 4 C4 RL=2kn, 11 17 11 22 11 17 12 17 ns ns ns ns ~tpLH '" Propagation delay time. low·to-high-Ievel output tPHL '" Propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are shown on page 3-11. 1076 7-418 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 'TYPES SN54S283, SN74S283 4-BIT BINARY FULL ADDERS WITH FAST CARRY REVISED DECEMBER 1980 recommended operating conditions SN54S283 Supply voltage, Vee High·level output current, 10H Low-level output current, 10L SN74S283 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 Any output except C4 Output C4 Any output except C4 Output C4 5.25 V -1 -1 mA -500 -500 J.lA 20 20 10 mA 70 °c 10 Operating free-air temperature, T A -55 UNIT 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage TYPt MAX Vee = MIN, 11=-18mA LSN54S283 V~=MIN, VIH = 2 V, 2.5 3.4 ISN74S283 VIL = O.B V, IOH = MAX 2.7 3.4 Vce = MIN, VIH = 2 V, VIL = O.B V, 10L = MAX Vee = MAX, VI = 5.5 V input voltage UNIT V 2 Input current at maximum II MIN 0.8 V -1.2 V V 0.5 1 V mA IIH High-level input current Vee = MAX, VI = 2.7 V 50 J.lA IlL Low-level input current Vec - MAX, VI - 0.5 V mA -40 -2 -100 -20 -100 l Short-circuit lOS output current§ I Any output except C4 VCC = MAX Output C4 mA All B low, other ICC Supply current Vce = MAX, inputs at 4.5 V Outputs open All inputs at 80 mA 95 4.5V 160 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 1All II I 25 0 e. typical values are at Vee = 5 V, T A = § Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER~ tPLH FROM (INPUT) TO (OUTPUT) CO Any l; Ai or Bi l:i eL = 15 pF, RL = 280 tpHL tPLH tpHL tPLH tpHL MIN n, See Note 3 CO C4 Ai or Bi C4 CL=15pF, RL = 660 tpHL tPLH TEST CONDITIONS See Note 3 n, TYP MAX 11 18 12 18 12 1B 11.5 1B 6 11 7.5 11 7.5 12 8.5 12 UNIT ns ns ns ns ~ tpLH = Propagation delay time, low-to-high-Ievel output tpH L = Propagation delay time, hlgh-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-419 TTL LSI TYPES SN54284, SN54285, SN74284, SN74285 4-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS BULLETIN NO. DL-S 7211741, MAY 1972-REVISED DECEMBER 1972 • Fast Multiplication of Two Binary Numbers 8-Bit Product in 40 ns Typical • Expandable for N-Bit-by-n-Bit Applications: 16-Bit Product in 70 ns Typical 32-Bit Product in 103 ns Typical • Fully Compatible with Most DTL and TTL Circuits • Diode-Clamped Inputs Simplify System Design SN54284 ..• J OR W PACKAGE SN74284 •.• J OR N PACKAGE (TOP VIEW) OUTPUTS ~:---:-:::~/\,-----, description These high-speed TTL circuits are designed to be used in high-performance parallel mUltiplication applications. When connected as shown in Figure A, these circuits perform the positive-logic multiplication of two 4-bit binary words. The eight-bit binary product is generated with typically only 40 nanoseconds delay. ~~GND WORD INPUTS positive logic: see descri ption SN54285 •.• J OR W PACKAGE SN74285 .•. J OR N PACKAGE (TOP VIEW) This basic four-by-four multiplier can be utilized as a fundamental building block for implementing larger multipliers. For example, the four-by-four building blocks can be connected as shown in Figure B to generate submultiple partial products. These results can then be summed in a Wallace tree, and, as illustrated, will produce a 16-bit product for the two eight-bit words typically in 70 nanoseconds. carry-save adders and SN54H 183/SN74H 183 SN54S181/SN74S181 arithmetic logic units with the SN54S182/SN74S182 look-ahead generator are used to achieve this high performance. The scheme is expandable for implementing N X M bit mUltipliers. I Q WORD INPUTS WORD ENABLE OUTPUTS VCCIN:~T~~ schematics of inputs and outputs EQUIVALENT OF EACH INPUT VCC 6 k.!1 NOM INPUT r-------------------------~ TYPICAL OF ALL OUTPUTS '----....,vr--~ WORD INPUTS ~~OUT>UT positive logic: see description -- The SN54284 and SN54285 are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74284 and SN74285 are characterized for operation from oOe to 70°C. 1076 7-420 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54284, SN54285, SN74284, SN74285 4-BIT-BY-4-.BIT PARALLEL BINARY MULTIPLIERS [] : : ~~~------------------~--~ ffi ~ ~~ ~ al ~ 5 -< 'Noet N~.______ ~i ~ ~ ~~§ ~ g .- ct:-----------------------'I, co :--------------------'l. II « ~~~---------------~ 'N 'l. 'I, N ~ :l ; -!-IJ JH---t~:fl.---------"I. 0 .J II ~ 1-----"1. r." 0 Ul ..J" en "I.. ..J" N [] "I. ~~ 5! ~ 'N~! Ul :. to ~_ 0;. ~ .. ~ ~ a: w :::i c.. a ~.~--.>,..4.-->,< N i= ...J ;:, :;: co 'N~N~ N >< co I tQ W N a: ;:, r." M Ul ~ ~ :e '" I 8 • C!l u: :, « 00 ..J N N ~ N ~ ~ iii N en ;:! z I ~ 00 N en .: L!l z Ul ~~ ''"" .: '" 1: :~ 1 ~ ] ~£ 1: 0 ,J &! ~ ~ ~ '" §] 1: 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-421 TYPES SN54284, SN54285, SN74284, SN74285 4-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) ...... . Input voltage . . . . . . . ...... . Operating free-air temperature range: SN54' Circuits SN74' Circuits Storage temperature range 7V 5.5 V -55°C to 125°C O°C to 70°C -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54284 SN74284 SN74285 SN54285 MIN Supply voltage, Vee NOM 4.5 MAX MIN 5.5 4.75 5 High·level output voltage, VOH Low-level output current, IOL Operating free·air temperature, T A -55 NOM 5 UNIT MAX 5.25 V 5.5 5.5 V 16 16 mA 70 °e 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER High·level input voltage VIL Low-level input voltage TYP:j: MAX UNIT VI Input clamp voltage IOH High·level output current V 0.8 Vee- MIN, '1- Vee- MIN, VIH - 2V, VIL = 0.8 V, VOH = 5.5 V Vee- MIN, VOL Low-level output voltage -1.5 -12mA 40 IOL= 12mA 0.4 IOL= 16mA 0.45 V V j.lA V VIH = 2V, VIL=0.8V • MIN 2 VIH II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 IIH High-level input current Vee = MAX, VI = 2.4 V 40 j.lA IlL Low-level input current Vee - MAX, -1 mA Vee - MAX, TA = 125°C, Ice See Note 2 Supply current VI - 0.4 V SN54284, SN54285 mA 99 N package only mA Vee = MAX, SN54284, SN54285 92 110 See Note 2 92 130 SN74284, SN74285 tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. :j:AII typical values are at V CC = 5 V, T A = 25°C. NOTE 2: With outputs open and both enable inputs grounded, ICC is measured first by selecting an output product which contains three or more high-level bits, then by selecting an outPpt product which contains four low-level bits. switching characteristics, Vee = 5 V, TA ="25°e TEST CONDITIONS PARAMETER MIN TYP MAX UNIT tpLH Propagation delay time, low-to-high·level output from enable eL = 30 pF to GND, 20 30 tpHL Propagation delay time, high-to-Iow-Ievel output from enable to Vee, 20 30 tpLH Propagation delay time, low-to-high-Ievel output from word inputs n RL2 = 600 n to GND, 40 60 tpHL Propagation delay time, high-to-Iow-Ievel output from word inputs See Note 3 40 60 RL1 = 300 ns ns NOTE 3: Load circuit is as described above; waveforms are shown on page 3-10. 1076 7-422 TEXAS INSTRUM ENTS Ir-.( OHI'OHI\II I> TYPES SN54290, SN54293, SN54LS290, SN54LS293 SN74290, SN74293, SN74LS290, SN74LS293 DECADE AND 4-BIT BINARY COUNTERS TTL MSI BULL.ETIN NO. DL-S 7611833, MARCH 1974-REVISED OCTOBER 1976 SN54290, SN54LS290 .•• J OR W PACKAGE SN74290, SN74LS290 •.• J OR N PACKAGE (TOPVIEW) '290, 'LS290 ... DECADE COUNTERS '293, 'LS293 ... 4-BIT BINARY COUNTERS • GND and VCC on Corner Pins (Pins 7 and 14 Respectively) description aD The SN54290/SN74290, SN54LS290/SN74LS290, SN54293/SN74293, and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5490AlSN7490A, SN54LS90/SN74LS90, SN5493A/SN7493A, and SN54LS93/SN74LS93, respectively. Only the arrangement of the terminals has been changed for the '290, 'LS290, '293, and 'LS293. R9(11 ~ OUTPUTS NC positive logic: GNO see function tables SN54293, SN54LS293 •.. J OR W PACKAGE SN74293, SN74LS293 .•• J OR N PACKAGE (TOP VIEW) Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divideby-five for the '290 and 'LS290 and divide-by·eight for the '293 and 'LS293. OUTPUTS VCC INPUT INPUT B A RO(2) ~ A All of these counters have a gated zero reset and the '290 and 'LS290 also have gated set-to·nine inputs for use in BCD nine's complement applications. aD To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the GA output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. A symmetrical divide-byten count can be obtained from the '290 and 'LS290 counters by connecting the GO output to the A input and applying the input count ,to the B input which gives a divide·by-ten square wave at output GA. • I NC NC NC ~ NC GNO OUTPUTS positive logic: see function tables NC-No internal connection 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·423 TYPES SN54290, SN54293, SN54LS290, SN54LS293, SN74290, SN74293, SN74LS290, SN74LS293 DECADE AND 4-BIT BINARY COUNTERS '290, 'LS290 BI-QUINARY (5-2) (See Note B) '290, 'LS290 BCD COUNT SEQUENCE (See Note A) COUNT OUTPUT 00 0c 0B °A COUNT '293, 'LS293 COUNT SEQUENCE (See Note C) '290, 'LS290 RESET/COUNT FUNCTION TABLE OUTPUT RESET INPUTS 0A 00 0c 0B OUTPUT 0 L L L L 0 L L L L 1 L L L H 1 L L L H H H X L L H OUTPUT COUNT ROlli ROl21 R9Ill R9121 00 0c 0B 0A H L X L L L L H L L L L L H 00 °c °B °A 0 L L L L 1 L L L H 2 L L H L 2 L L H L X X H H 2 L L H L 3 L L H H 3 L L H H X L X L COUNT 3 L L H H 4 L H L L 4 L H L L L X L X COUNT 4 L H L L 5 6 L H L H 5 H L L L L X X L COUNT 5 L H L H L H H L H L L H X L L X COUNT H H L L H H H H L H L 6 7 L 7 6 7 L H H H 8 H L L L 8 H L H H 8 H L L L 9 H L L H 9 H H L L H '293, 'LS293 RESET/COUNT FUNCTION TABLE RESET INPUTS NOTES: A. Output QA is connected to input B for BCD count. B. Output QD is connected to input A for bi-quinary ROl11 H count. C. Output QA is connected to input B. D. H = high level, L = low level, X = irrelevant ROl21 OUTPUT 00 °c L H L 9 H L L 10 H L H L 11 H L H H °B °A 12 H H L L L L 13 H H L H L X COUNT 14 H H H L X L COUNT 15 H H H H functional block diagrams '290, 'LS290 '293, 'LS293 (9) OA INPUT A ..:.(..;..;'O~)_ _ _ _--<)[> INPUT A ...;.('_O...;.)_ _ _4-_ _-- • (5) OB (5) OB INPUT B .:...;(';...:.',,-)-----+~ INPUT B -('-'-)--+++----- 00 (8) 00 The J and K inputs shown without connection are for reference only and are functionally at a high level. 1076 7-424 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54290, SN54293, SN74290, SN74293 DECADE AND 4-BIT BINARY COUNTERS schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EaUIVALENT OF EACH INPUT Vee vee3-Req INPUT -- OUTPUT INPUT A B ('290) B ('293) All resets Req NOM 2.5 kn. 1.25 kn. 2.5 kn. 6kU absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 5.5 V 5.5 V D D -55 C to 125 C D ODC to 70 C D D -65 C to 150 C Supply voltage, VCC (see Note 1) Input voltage . . . . . . . Interemitter voltage (see Note 2) Operating free·air temperature range: SN54' Circuits SN74' Circuits Storage temperature range NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2, This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the two RO inputs, and for the '290 circuit, it also applies between the two R9 inputs. II I recommended operating conditions --~~ SN54' MIN Supply voltage, VCC 4.5 NOM 5 SN74' MAX MIN NOM 5.5 4.75 5 -800 High·level output current, IOH 16 Low-level output current, IOL Count frequency, 'count Pulse width, tw a a B input a a A input 15 15 B input 30 30 Reset inputs 15 15 A input Reset inactive-state setup time, tsu 25 Operating free-air temperature, T A -55 32 16 MAX 5.25 V -800 IJA 16 mA 32 16 a MHz ns ns 25 125 UNIT 70 °c 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-425 TYPES SN54290, SN54293, SN74290, SN74293 DECADE AND 4-BIT BINARY COUNTERS REVISED AUGUST 1977 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH TEST CONDITIONSt '290 MIN TYP:j: 2 High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage Vee = MIN, 11=-12mA Vee = MIN, VIH = 2 V, VIL = 0.8 V, 10H = -800 itA Vee = MIN, VIH VIL = 0.8 V, 10L = 16 mA~ '= 2.4 2 V, High-level input current 0.2 Vee = MAX, VI = 2.4 V Any reset A input Low-level input current Vee = MAX, VI = 0.4 V B input MAX V V -1.5 -1.5 V 2.4 3.4 0.2 0.4 V 0.4 1 1 40 40 80 80 120 80 -1.6 -1.6 -3.2 -3.2 -4.8 -3.2 I SN54' -20 -57 -20 -57 J SN74' -18 -57 -18 -57 lOS Short-circuit output current § Vee = MAX ICC Supply current Vee = MAX, See Note 3 29 UNIT 0.8 3.4 B input IlL TYP:j: 0.8 Vee = MAX, VI = 5.5 V A input MIN 2 Any reset IIH '293 MAX 42 26 39 V mA itA mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°e. §Not more than one output should be shorted at a time. ~OA outputs are tested at IOL = 16 mA plus the limit value of IlL for the B Input. This permits driving the B Input while maintaining full fan-out capability. NOTE 3: lee is measured with all outputs open, both RO Inputs grounded following momentary connection to 4.5 V, and ell other inputs grounded. switching characteristics, Vee • PARAMETERO f max tpLH FROM TO (INPUT) (OUTPUT) A B A tpHL tpLH A tpHL tpLH tpHL tpLH S tPLH tpHL TYP °A 32 42 °B 16 °A °D RL = 400 n, S °e MAX MIN TYP 32 42 MAX MHz 16 10 Os '293 UNIT MIN See Note 4 16 10 16 18 12 18 12 32 48 46 70 34 50 46 70 10 16 10 16 14 21 14 21 21 32 21 32 23 35 23 35 21 32 34 51 S °D 23 35 34 51 Set-to-O Any 26 40 26 40 °A,OD 20 30 °S,OC 26 40 tpHL tPHL '290 TEST CONDITIONS eL=15pF, tpHL tpLH = 5 V, TA = 25°e Set-to-9 ns ns ns ns ns ns ns Of max "" maximum count frequency tpLH "" propagation delay time, low-to-high-Ievel output tpH L "" propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit and voltage waveforms are the same as those shown for the '90A and '93A, page 3-10. 877 7-426 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293 DECADE AND 4-BIT BINARY COUNTERS REVISED OCTOBER 1976 schematics of inputs and outputs - EQUIVALENT OF EACH RESET INPUT VCC o -- -----VCC VC~ 120 R1 R2 R3 20 kH NOM INPUT TYPICAL OF ALL OUTPUTS EQUIVALENT OF A AND B INPUTS INPUT n NOM OUTPUT INPUT NOMINAL VALUES R1 R2 R3 A 10 kn B ('LS290) 6.7 kn IB ('LS293) 15 kn 10 kn 6.7 kn 15 kn 10 kn 5 kn 10 kn absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 7V 5.5 V -55°e to 125°C oOe to 70°C -65°C to 150°C Supply voltage, Vee (see Note 5) Input voltage: R inputs A and B inputs Operating free-air temperature range: SN54LS290, SN54LS293 SN74LS290,SN74LS293 Storage temperature range • NOTE 5: Voltage values are with respect to network ground terminal. I recommended operating conditions SN74LS' SN54LS' MIN Supply voltage, VCC 4.5 High-level output current, IOH NOM 5 MAX MIN 5.5 4.75 -400 low·level output current, IOL 4 A input Count frequency, fcount Pulse width, tw 0 32 16 B input 30 30 Reset inputs 15 15 25 V jJA 8 rnA 16 15 -55 5.25 0 0 15 0 MHz ns 25 125 UNIT -400 32 B input Reset inactive-state setup time, tsu 5 MAX 0 A input Operating free·air temperature, T A NOM ns 70 °c 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-427 TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293 DECADE AND 4-BIT BINARY COUNTERS REVISED OCTOBER 1976 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK I nput clamp voltage VOL Low-level output voltage I nput current at maximum input voltage MIN TYP+ Any reset Vee= MIN, 11=-18mA Vee= MIN, VIH=2V, VIL = VIL max, IOH =-4OOp,A Vee= MIN, VIH = 2 V, 2.5 tlOL = 4 mA~ A input inl'lut current B of 'LS290 0.25 Low-level A input B of 'LS290 -1.5 2.7 3.4 0.4 0.25 0.4 0.35 0.5 0.2 0.2 Vee = MAX, VI = 5.5 V 0.4 0.4 0.2 0.2 VI = 2.7 V Vee = MAX, VI=OAV B of 'LS293 lOS Short-circuit output current§ Vee= MAX lee Supply current Vee= MAX, I 'LS290 I 'LS293 See Note 3 V V 0.1 20 20 40 40 80 80 40 40 -0.4 -0.4 -2.4 -2.4 -3.2 -3.2 -1.6 -100 -20 V V 0.1 Any reset input current -1.5 VI = 7 V Vee = MAX, UNIT V Vee= MAX, B of 'LS293 IlL MAX 0.8 IIOL = 8 mA~ VIL = VIL max B of 'LS293 High-level TYP+ 0.7 3.4 A input B of 'LS290 MIN 2 Any reset IIH SN74LS' MAX 2 VOH High-level output voltage II SN54LS' TEST eONDITIONst mA j.lA mA -1.6 -20 -100 9 15 9 15 9 15 9 15 mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII tvpical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. ~QA outputs are tested at specified IOL plus the limit value of IlL for the B input. This permits drivin9 the B input while maintaining full fan-out capabilitv. NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs grounded . • switching characteristics, Vee = 5 V, TA = 25°e PARAMETER¢ f max tpLH tpHL tpLH tpHL tpLH tpHL tpLH FROM TO (INPUT) (OUTPUn tpHL tpHL tpLH =::; 42 °A S °B 16 A °A °D S Os RL = 2 kn, See Note 6 MAX MIN TYP 32 42 UNIT MAX MHz 16 10 eL=15pF. 16 10 16 12 18 12 18 32 48 46 70 34 50 46 70 10 16 10 16 14 21 14 21 21 32 21 32 23 35 23 35 51 S °e S 21 32 34 °D 23 35 34 51 Set-to-O Any 26 40 26 40 °A.OD 20 30 °s,Oe 26 40 Set-to-9 tpHL <'>f max TYP 32 tPHL tpLH MIN A A 'LS293 'LS290 TEST CONDITIONS ns ns ns ns ns ns ns maximum count frequency tpLH"" propagation delay time. low to-high-Ievel output tpH L "" propagation delay time, high-to-Iow-Ievel output NOTE 6: Load circuit and voltage waveforms are the same as those shown for the 'LS90 and 'LS93, pages 7-80. B77 7·428 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • CALLAS. TEXAS 75222 TYPES SN54LS2958, SN74LS2958 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-STATE OUTPUTS TTL MSI BULLETIN NO. OL·S 7711780, OCTOBER 1976-REVISEO AUGUST 1977 • 'LS295B Offers Three Times the Sink-Current Capability of 'LS295A • Schottky-Diode·Clamped Transistors • Low Power Dissipation ... 80 mW Typical (Enabled) • Applications: N-Bit Serial-To-Parallel Converter N-Bit Parallel-To-Serial Converter N-Bit Storage Register SN54LS295B ••• J OR W PACKAGE SN74LS295B ••• J OR N PACKAGE (TOP VIEW) OUTPUTS Vee ~ClOCKC~~-r.:~ciL description These 4-bit registers feature parallel inputs, parallel outputs, and clock, serial, mode, and output control inputs. The registers have three modes of operation: S,~~i ~C~~.fREol GND INPUTS Parallel (broadside) load Shift right (the direction GA toward GD) Shift left (the direction GD toward GA) logic: see fu netion table Parallel loading is accomplished by applying the four bits of data and taking the mode control input high_ The data is loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition of the clock input. During parallel loading, the entry of serial data is inhibited_ Shift right is accomplished when the mode control is low; shift left is accomplished when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (GD to input e,etc.) and serial data is entered at input D. When the output control is high, the normal logic levels of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a low logic level at the output control input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation of the registers is not affected. The SN54LS295B is characterized for operation over the full military temperature range of -55°e to 125°e; the o SN74LS295B is characterized for operation from oOe to 70 e. FUNCTION TABLE INPUTS MODE CLOCK SERIAL H H H j. H 1- X X X L H X L 1- H L 1- L CONTROL OUTPUTS PARALLEL QA QB - QC QBO d QAO a d QBn QCn X X X QAO QBO H QAn L QAn A B C D X a X X X b e QBt X X X Qct QDt X X X X X X b QD QCO QDO e d QDn d QCO QDO QBn QCn QBn QCn When the output control is low, the outputs are disabled to the high-impedance state; however. sequential operation of the registers is not affected. tShifting left requires external connection of 0B to A. 0c to B, and 00 to C. Serial data is entered at input O. H = high level (steady state), L = low level (steady state), X = irrelevant (any input. including transitions) j. = transition from high to low level. a, b, c, d = the level of steady-state input at inputs A, B, C, or 0, respectively. 0AO, 0BO. 0CO, 000 = the level of 0A. 0B' DC, or 00. respectively. before the indicated steady-state input conditions were established. 0An' 0Bn. 0Cn. 00n = the level of 0A' 0B, DC. or 00, respectively, before the most-recent j, transition of the clock. See explanation of function tables on page 3-8. 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7429 TYPES SN54LS295B:, SN74LS295B 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-SlATE OUTPUTS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . . Input voltage . . . . . . . . . . . . . . . Operating free·air temperature range: SN54LS2958 SN74LS2958 Storage temperature range .7V 7V -55°C to 125°C aOe to 7aoe -65°C to 15aoe NOTE 1: Voltage values are with respect to natwork ground terminal. recommended operating conditions SN54LS295B MIN NOM MAX Supply voltage, Vee 4.5 5 High-level output current, 10H 5.5 -1 Low-level output current, 10L Clock frequency, fclock 12 30 0 Width of clock pulse, twlclockl Setup time, high-level or low-level data, tsu 16 Hold time, high-level or low-level data, th Operating free-air temperature, T A SN74LS295B UNIT NOM MAX MIN 4.75 0 20 16 20 20 -55 20 0 125 5 5.25 -2.6 V mA 24 mA 30 MHz ns ns 70 ns °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER VIH VIL VIK High-level input voltage Low-level input voltage Input clamp voltage VOH High-level output voltage • VOL Low-level output voltage Off-state output current, 10ZH high-level voltage applied Off-state outpu,t current, 10ZL II IIH IlL low-level voltage applied Input current at maximum input voltage High-level input current lOS Low-level input current Short-circuit output current§ lee Supply current SN54LS295B MIN TVPt MAX 2 Vee = MIN, Vee = MIN, VIL = VIL max, Vee = MIN, VIL = VIL max Vce = MAX, VO= 2_7 V, 0.7 -1.5 II = -18 mA VIH-2V, 2.4 10H = MAX VIH-2V, 1I0L=12mA IIOL =24 mA VIL - VIL max, VCC = MAX, VO=·O.4 V VIH-2V, VCC = MAX, VI = 7 V VCC = MAX, Vee = MAX, VI = 2.7 V VI = 0.4 V Vee = MAX Vee = MAX, -30 See Note 2 ICondition A ICondition B 2.4 3.4 0.25 20 22 SN74LS295B UNIT MIN TVPt MAX 2 V V 0.8 -1.5 V 0.4 3.1 V 0.25 0.4 0.35 0.5 V 20 20 jlA -20 -:-20 jlA 0.1 0.1 mA 20 -0.4 20 jlA -0.4 mA mA -130 29 33 -30 20 22 -130 29 33 mA tFor cO~ditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions. tAli typical values are at VCC = 5 V, T A = 25 C. § Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second. NOTE 2: Ice is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following conditions: A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input. B. Output control and clock input grounded. 1280 7-430 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS295B SN74LS295B 4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-STATE OUTPUTS . REVISED AUGUST 1977 switching characteristics, Vee = 5 V, TA = 25 e, RL = 667.n PARAMETER TEST CONDITIONS f max Maximum clock frequency tpLH Propagation delay time, low-to-high-Ievel output CL=45pF, See Note 3 tpHL Propagation delay time, high-to-Iow-Ievel output tpZH Output enable time to high level tpZL Output enable time to low level tpHZ Output disable time from high level CL=5pF, tpLZ Output disable time from low level See Note 3 MIN TYP 30 45 MAX UNIT MHz 14 20 ns 19 18 30 ns 26 ns 20 30 ns 13 13 20 ns 20 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. functional block diagram DATA INPUTS r -__________________ __________________ ~A~ c B A (3) (2) ~ D (4) (5) MODE CONTROL ~~~~i~---~~~,-II~------~~r-IIt-------~;-r-IIt-------~;-l OUTPUT CONTROL • ~---------------------------~vr---------~---------------~~ OUTPUTS schematics of inputs and outputs EQUIVALENT OF SERIAL AND DATA INPUTS EQUIVALENT OF CLOCK, TYPICAL OF ALL OUTPUTS MODE CONTROL, AND OUTPUT CONTROL INPUTS Vee --------<_---- I NPUT --<~~~--1"'" ------------.---Vcc ! Vee - - -......---- - - ~ INPUT ... 'OknNOM OUTPUT n7 Serial: Req = 30 kS1 NOM A, B, C, 0: Req = 20 kS1 NOM 877 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-431 TTL MSI TYPES SN54298, SN54LS298, SN74298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE BULLETIN NO. DL-S 7611747, MARCH 1974-REVISED OCTOBER 1976 • • Selects One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock SN54298, SN54LS298 ••• J OR W PACKAGE SN74298, SN74LS298 , •• J OR N PACKAGE (TOPVIEWI Applications: Dual Source for Operands and Constants in Arithmetic Processor; Can Release Processor Register Files for Acquiring New Data OUTPUTS DATA WORD INPUT 00 CLOCKSELECT Cl ,.------I\----VCC oA oB Dc 13 Implement Separate Registers Capable of Parallel Exchange of Contents Yet Retain External Load Capability CK 82 Cl Universal Type Register for Implementing Various Shift Patterns; Even Has Compound Left-Right Capabilities description These monolithic quadruple two-input multiplexers with storage provide essentially the equivalent functional capabilities of two separate MSI functions (SN54157/SN74157 or SN54LS157/SN74LS157 and SN54175/SN74175 or SN54LS175/SN74LS175) in a single 16-pin package. • V DATA INPUTS logic: see function table functional block diagram When the word·select input is low, word 1 (A 1, B1, C1, D1) is applies to the flip-flops. A high input to word select will cause the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the negative-going edge of the clock pulse. Typical power dissipation is 195 milliwatts for the '298 and 65 milliwatts for the 'LS298. SN54298 and SN54LS298 are characterized for operation over the full military temperature range of -55°C to 125°C; SN74298 and SN74LS298 are characterized for operation from O°C to 70°C. c,---'-'"'-----+--+-r, FUNCTION TABLE INPUTS OUTPUTS WORD SELECT CLOCK °A °B °c °D L ~ a1 b1 c1 d1 H ~ a2 b2 c2 d2 X H OAO 0BO °CO 000 CLOCK ...:.11:..:.1I'---_ _ _ _ _ _- - l H = high level (steady state) L = low level (steady state) X = irrelevant (any input, including transitions) ~ = transition from high to low level a1, a2, etc. = the level of steadY'state input at A 1, A2, etc. QAO, QBO. etc. = the level of QA. QB. etc. entered on the most-recent ~ transition of the clock input. -J, ... I ">-_ _ _ _...J Dynamic input activated by a transition from a high level to a low level 1076 7-432 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54298, SN54LS298, SN74298,' SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE REVISED OCTOBER 1976 schematics of inputs and outputs '298 EQUIVALENT OF EACH INPUT '298 TYPICAL OF ALL OUTPUTS --'--VCC INPUT OUTPUT Clock: All other inputs: Req Req =4 = kn NOM 6 kn NOM 'LS298 'LS298 EQUIVALENT OF OTHER INPUTS TYPICAL OF ALL OUTPUTS 'LS298 EQUIVALENT OF DATA INPUTS V C C - -.......- - - - - -.......- - V c e 120 n NOM Vce 15 kn NOM 17 kn NOM INPUT .,.. 0.1-' OUTPUT • ~, ~~ -l ~~ ,.,7 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-433 I TYPES SN54298, SN74298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) .... . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54298 SN74298 Storage temperature 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54298 MIN NOM 4.5 5 Supply voltage, Vee SN74298 MAX MIN NOM 5.5 4.75 5 -800 High·level output current, 10H 16 Low-level output current, 10L 20 20 Data 15 15 Word select Width of clock pulse, high or low level, tw Setup time, tsu Hold time, th 25 25 Data 5 5 Word select 0 0 -55 Operating free·air temperature, T A 125 MAX UNIT 5.25 V -800 IJA 16 mA ns ns ns 70 0 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage TYP:!= MAX VOL Low·level output voltage Vee = MIN, 11= -12 mA Vee = MIN, VIH=2V, VIL = 0.8 V, 10H = -800 IJA Vee = MIN, VIH=2V, VIL = 0.8 V, 10L = 16 mA 2.4 UNIT V 2 VOH High·level output voltage • MIN 0.8 V -1.5 V V 3.2 0.4 V mA II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 IIH High·level input current Vee = MAX, VI = 2.4 V 40 IJA IlL Low·level input current Vee = MAX, VI = 0.4 V -1.6 mA lOS Short-circuit output current§ Vee = MAX lee Supply current Vee = MAX, See Note 2 1 SN54298 I SN74298 -20 -57 -18 -57 39 65 mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :!=AII tvpical values are at Vee = 5 V, T A = 25°C. §Not more than one output should be shorted at a time. NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to the clock input. switching characteristics, Vee = 5 V, T A = 25°e PARAMETER TEST CONDITIONS I---'tp,-,L""H,-,-P_r_o:...,pa...:g:...a_ti_on_d_el_aY:..-ti_m_e:..."l_o_w_.t_o_.h....:i9::..h_.I_ev_e_l_o_ut..:.p_u_t_ _ _ _ _ _ _-l eL = 15 pF, tpHL Propagation delay time, high·to·low·level output See Note 3 RL = 400 n, MIN TYP MAX 18 27 21 32 NOTE 3: Load circuit and waveforms are shown on page 3-10. 1076 7·434 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE REVISED OCTOBER 1976 absolute maximum ratings ov·er operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS298 SN74LS298 Storage temperature range 7V 7V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS298 Supply voltage, SN74LS298 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 Vee High-level output current, 10H -400 Low-level output current, 10L -400 V )lA 8 rnA 4 Width of clock pulse, high or low level, tw Setup time, tsu Hold time, th 20 20 Data 15 15 Word select 25 25 Data 5 5 Word select a a Operating free·air temperature, T A 125 -55 UNIT ns ns ns 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage MIN TYP+ SN74LS298 MAX 2 VOH High-level output voltage VOL Low-level output voltage II SN54LS298 TEST eONDITIONSt Vee= MIN, 11=-18mA Vee= MIN, VIL = VIL max, VIH=2V, 10H = -400)lA Vee = MIN, VIH ';'2V, maximum input voltage VI = 7 V MAX 2 UNIT V 0.8 V -1.5 -1.5 V 3.4 2.7 0.4 IIOL = 8 rnA Vee = MAX, TYP+ 0.7 0.25 IIOL = 4 rnA VIL = VIL max Input current at 2.5 MIN 3.4 V 0.25 0.4 0.35 0.5 0.1 V 0.1 rnA IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 )lA IlL Low-level input current Vee = MAX, VI = 0.4 V Short-circuit output current § Vee = MAX -0.4 -100 rnA lOS -0.4 -100 lee Supply current Vee = MAX, -20 See Note 2 13 -20 21 13 21 rnA • I rnA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to the clock input. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-Ievel output eL=15pF, tPHL Propagation delay time, high-to-Iow-Ievel output See Note 4 RL=2kn, MIN TYP MAX 18 27 21 32 NOTE 4: Load circuit and waveforms are shown on page 3-11. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-435 TYPES SN54298, SN54LS298, SN74298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE TYPICAL APPLICATION DATA This versatile multiplexer/register can be connected to operate as a shift register that can shift N-places in a single clock pulse. The following figure illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse. PARALLEL LOAD Ir--------------------JA~ A1 I WS l A1 OAf-- A2 - or 0BB2 'LS298 ' - - C1 REG 1 Oc~ C2 CLOCK -- D1 D2 I T WS '---- ~ OD l A1 - OA A2 '- B1 '298 - __________________~\ I A2 B1 '298 B1 '298 or OB B2'LS298 ' - - C1 REG 3 Oc C2 ~ ....., '--- D1 ~ ~ OA - or OB B2'LS298 C1 REG 2 Oc C2 D2 WORD SELECT T WS OD D1 D2 ~ OD y ~ ~ ~ ~ DIGIT2 DIGIT 1 DIGIT3 When the word-select input is high and the registers are clocked, the contents of register 1 is transferred (shifted) to register 2 and etc. In effect, the 'BCD digits are shifted one position. In addition, this application retains a parallel-load capability which means that new BCD data can be entered in the entire register with one clock pulse. This arrangement can be modified to perform the shifting of binary data for any number of bit locations, • Another function that can be implemented with the '298 or 'LS298 is a register that can be designed specifically for supporting multiplier or division operations. The example below is a one place/two-place shift register . '181, 'LS181, or 'S181 (ALU) FO F1 F2 F3 '181, 'LS1S1, or 'S181 (ALU) FO F1 F2 F3 A 1 A2 B1 B2 C1 C2 D1 D2 A1 A2 B1 B2 C1 C2 D1 D2 WS CLOCK~~==t===~==~==~==~J WORD '-----+----+----+----+---4~SELECT When word select is low and the register is clocked, the outputs of the arithmetic/logic units (ALU's) are shifted one place, When word select is high and the registers are clocked, the data is shifted two places. 374 7436 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DAL.LAS. TEXAS 75222 TYPES SN54LS299, SN54S299, SN74LS299, SN74S299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS TTL LSI BULLETIN NO. DL-S 12115, MARCH 1974-REVISED DECEMBER 1980 • Multiplexed Inputs/Outputs Provide Improved Bit Density • Four Modes of Operation: Hold (Store) Shift Left Shift Right Load Data • Operates with Outputs Enabled or at High Z • 3-State Outputs Drive Bus Lines Directly • Can Be Cascaded for N-Bit Word Lengths • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear SN54LS299, SN54S299 ••• J PACKAG E SN74LS299, SN74S299 ••• J N PACKAGE (TOP VIEW) cm SHIFT SHIFT RIGHT LEFT SL VCC DiaD BlaB CLOCK SR SR Appl ications: Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers • TYPICAL GUARANTEED TYPE so SHIFT (CLOCK) POWER FREOUENCY DISSIPATION 'LS299 25 MHz 175mW 'S299 50 MHz 700mW ~GIOG C/Oc EIOE A/QA OA' CLEAR GND OUTPUT CONTROLS logic: see description and function table description These Schottkyt TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, SO and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off. • FUNCTION TABLE I NPUTSIOUTPUTS INPUTS MODE Clear Hold Shift Right Shift Left Load FUNCTION CLEAR SELECT OUTPUTS OUTPUT SERIAL CONTROL CLOCK A/OA BlOB C/Oc G1t G2 t SL SR S1 SO L L X L L X L L L L t t X X 0/°0 E/OE F/OF G/~ H/OH °A' °H' X L L L L L L L L L L X L L L L L L L L L X X X X X L L QDO QEO QFO QGO QHO QAO QHO L H H X X t X X X X L X H L L L L X X X °AO °BO QCO H X X L L L X X QCO QDO QEO QFO QGO QHO L H L L t X H QAO H QBO H QAn QBn Ocn QDn QEn QFn QGn QAO QHO H QGn H L H L L t X L L QAn QBn QCn QDn QEn QFn H H L L L t H X QBn QCn QDn QEn QFn QGn QHn QGn H QBn H H L L L t L X QBn QCn QDn QEn QFn QGn QHn L QBn L H H H X X t X X a b c d e f g h a h L QGn H tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance stat~; however, sequential operation or clearing of the register is not affected. a ... h = the level of the steady·state input at inputs A through H. respectively. These data are loaded into the flip·flops while the flip·flop outputs are isolated from the input/output terminals. See explanation of function tables on page 3·8. (Copyright © 1980 by Texas Instruments Incorporated 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 tlntegrated SchottkY·Barrier diode· clamped transistor is patented by Texas Instruments. U.S. Patent Number 3,463,975. 7-437 TYPES SN54LS299, SN54S299, SN74LS299, SN74S299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS functional block diagram iD H----r;:>--~...::.= ~ • M H+--r::>--+-~-=-= ~ 879 7-433 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS299, SN74LS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS REVISED DECEMBER 1980 o schematics of inputs and outputs EOUIVALENT OF EACH INPUT VCC TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS 0A' THRU 0H' 0A THRU 0H ---~-VCC ----.--vcc Req INPUT __ OUTPUT OUTPUT SO, Sl: Req= 9 k!l NOM All other inputs: R eq =18 k!l NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . Off-state output voltage Operating free-air temperature range: SN54LS299 SN74LS299 Storage temperature . 7V . 7V 5.5 V -55°C to 125°C oOe to 700 e 0 -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS299 Supply voltage, VCC High-level output current, IOH NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 QA thru QH QA' or QH' Low-level output current, IOL QA thru QH QA' or QH' Clock frequency, fclock Width of clock pulse, tw(clock) Width of clear pulse, tw(clear) Setup time, tsu Hold time, th SN74LS299 MIN 0 Clock high -1 -2.6 -0.4 -0.4 12 24 4 8 25 0 Clock low 10 10 Clear low 20 20 Select 35t 35t High-level data O 20t 20t Low-level data O 20t 20t Clear inactive-state 20t 20t Select lOt lOt Data O ot Operating free-air temperature, T A -55 25 30 30 0 V mA mA MHz • ns ns ns ns ot '125 UNIT 70 °c °Data includes the two serial Inputs and the eight input/output data lines. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-439 TYPES SN54LS299, SN74LS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS REVISED DECEMBER 1980 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER f--. VIH High-level input voltage VIL Low-level input voltage VIK I nput clamp voltage VOH High-level output voltage Off-state output current, VIH-2V, 2.4 3.2 2.4 10H = MAX 2.5 3.4 2.7 VCC = MIN, VCC = MAX, VCC= MAX, VCC = MAX A thru H, SO, Sl High-level input current Any other SO, Sl IlL Low-level input current lOS Short-circuit output current § ICC Supply current Any other QA thru QH QA' or Ow 0.25 0.35 0.5 0.25 0.4 0.25 0.4 0.35 0.5 10L - 24 mA 10L =4 mA VCC = MAX, VCC = MAX, V 3.4 0.4 10L -8 mA VIH-2V, VIH = 2 V, 0.4 40 IJA IJA -400 -400 200 200 VI = 5.5V 100 100 VI =7V 100 100 40 40 20 20 -0.8 -0.8 -0.4 -0.4 -30 -130 -30 -130 -20 -100 -20 VI =2.7V VI = 0.4 V VCC = MAX 33 VCC = MAX V 40 VI =7V Va = 0.4 V Any other 3.1 0.25 Va = 2.7 V A thru H input voltage IIH VIL = VILmax SO, Sl Input current at maximum II V VIL = VILmax, QA thru 0H low-level voltage applied -1.5 VCC = MIN, QA thru QH high-level voltage applied V -1.5 0A'or 0H' VIH = 2 V, V 0.8 0A thru 0H 10L = 12 mA UNIT 0.7 II = -18 mA Low-level output voltage Off-state output current, 10ZL 2 VCC = MIN, QA'or QW 10ZH SN74LS299 2 QA thru QH VOL SN54LS299 MIN TYP+ MAX MIN TYP+ MAX -100 53 33 53 IJA IJA mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, T A = 25° C. §Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. switching characteristics, Vee II PARAMETERlI = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) f max tPLH Clock QA' or QH' Clear QA' or QH' tpHL tPHL tPLH tPZH QA thru QH Clear QA thru 0H G1, G2 QA thru QH tPZL tpHZ tPLZ Gl,G2 CL = 15 pF, RL=2k.n, See Note 2 Clock tPHL tPHL TEST CONDITIONS See Note 2 QA thru QH CL=45pF, RL = 665.n, See Note 2 CL-5pF, RL - 665.n, See Note 2 MIN TYP 25 35 22 MAX UNIT MHz 33 26 39 27 40 17 25 26 39 26 40 13 21 19 30 10 15 10 15 ns ns ns ns ns ns == maximum clock frequency tPLH == propagation delay time, low-to·high·level output. tPH L == propagation delay time, h igh-to-Iow-Ievel output tpZH == output enable time to high level tpZL == output enable time to low level tPHZ == output disable time from high level tpLZ == output disable time from low level NOTE 2: For testing f max , all outputs are loaded simultaneously, each with CL and RL as specified for the propagation times. See load circuits and waveforms on page 3-11. 11 f max 1280 7·440 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54S299, SN74S299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS a schematics of inputs and outputs EQUIVALENT OF CLOCK AND CLEAR INPUTS EQUIVALENT OF G1 AND G21NPUTS v cc 2.8 kn vcc~-NOM -- Req INPUT EQUIVALENT OF A THRU Ht, SO, Sl, SHIFT RIGHT, AND SHIFT LEFT INPUTS -- vcc~"n NOM INPUT INPUT Clock: Req = 2.8 kn NOM Clear: Req = 3.5 kn NOM -- tWhen 3·state outputs are disabled. TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS QA THRU QH QA' AND QW - - - - 1 - - V CC ---""--VCC OUTPUT OUTPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) I nput voltage . . . . . . . . Off-state output voltage Operating free-air temperature range: SN54S299 (see Note 2) SN74S299 Storage temperature . 7V 5.5 V 5.5 V -55°e to 125°e oOe to 700e _65° e to 150°C NOTES 1: Voltage values are with respect to network ground terminal. II recommended operating conditions SN54S299 Supply voltage, VCC High-level output current, IOH Low-level output current, IOL Width of clear pulse, tw(clear) NOM MAX MIN NOM 4.5 5 5.5 4.75 5 MAX UNIT 5.25 V -2 -0.5 -6.5 -0.5 mA QA thru QH 20 20 QA' or QH' 6 QA thru QH QA' or QH' 0 Clock frequency, fclock Width of clock pulse, tw(clock) SN74S299 MIN 50 0 Clock high 10 10 Clo<;k low Clear low 10 10 10 10 Select 15t 15t 7t 5t 7t 5t lOt lOt 5t 5t -55 5t 5t Setup time, tsu High-level data O Low-level data O Hold time, th Select DataO Clear inactive-state Operating free-air temperature, T A 125 0 6 50 mA MHz ns ns ns ns 70 °c °Data includes the two serial inputs and the eight input/output data lines. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-441 TYPES SN54S299, SN74S299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS REVISED DECEMBER 1980 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage Vil low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL low-level output voltage TEST CONDITIONSt VCC = MIN, 11=-18mA VCC = MIN, VIH =2 V, 2.4 3.2 0A' or 0H' Vil = 0.8 V, IOH = MAX 2.7 3.4 VCC = MIN, VIH - 2 V, QA thru QH low-level voltage applied Input current at maximum input voltage IIH High-level input current VIL = 0.8 V, IOL = MAX VCC = MAX, VIH = 2 V, -1.2 Vo = 2.4 V VCC = MAX, VIH = 2 V, Va = 0.5 V VCC = MAX, VI = 5.5 V VCC = MAX, VI = 2.7 V A thru H, SO, S1 Any other SO, S1 VCC = MAX, VI = 0.5 V Any other lOS Short-circuit output current § ICC Supply current QA thru QH QA' or QH' -40 V 100 j,lA -250 j,lA 1 100 mA j,lA -2 mA -400 pA -100 -20 VCC = MAX V 0.5 -250 VCC = MAX V V 50 Clock or clear low-level input current UNIT V QA thru QH QA thru QH high-level voltage applied II III MAX 0.8 Off-state output current, IOZl TVPt 2 Off-state output current, 10ZH MIN -100 140 225 TVP MAX j,lA mA mA t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vec = 5 V, T A = 25°e. § Not more than one output should be shorted at a time and duration of the short-circuit should not el(ceed one second. switching characteristics, Vee PARAMETER~ II = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) Clock QA' or QH' Clear QA' or QH' f max tPLH tPLH Clock QA thru QH Clear QA thru QH G1,G2 QA thru QH tPHL tpHL tPZH tpZL tPHZ tPLZ G1,G2 QA thru QH CL=15pF, RL = 1 kn, See Note 2 CL =45 pF, RL=280n, See Note 2 CL - 5 pF, See Note 3 MIN 50 See Note 2 tpHL tpHL TEST CONDITIONS RL = 1280n, 70 UNIT MHz 12 20 13 20 14 21 15 21 15 21 16 24 10 18 12 18 7 12 7 12 ns ns ns ns ns ns ~ fmal( == maximum clock frequency tpLH == propagation delay time, low-to-high-Ievel output. tpH L == propagation delay time, h igh-to-Iow-Ievel output tpZH == output enable time to high level tpZL == output enable time to low level tpHZ == output disable time from high level tpLZ == output disable time from low level NOTE 3: For testing fmal(' all outputs are loaded simultaneously, each with CL and RL as specified for the propagation times. See load circuits and waveforms on page 3-10. 1280 7-442 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEX-AS 75265 TTL LSI TYPES SN54LS323, SN74LS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS BULLETIN NO. DL-S 12462, OCTOBER 1976 - REVISED DECEMBER 1980 • Multiplexed Inputs/Outputs Provide Improved Bit Density • Four Modes of Operation: Hold (Store) Shift Left Shift Right Load Data SN54LS323 ••• J PACKAGE SN74LS323 ••• J OR N PACKAGE (TOPVIEWI SHIFT vCC • LEFT SL SI SHIFT OH' HIOH floF 0/00 BlOB ~G/OG EIOE c/Oc AIOA 0A' CLOCK RIGHT SR Operates with Outputs Enabled or at High Z • 3-State Outputs Drive Bus Lines Directly • Can Be Cascaded for N·Bit Word Lengths • Typical Power Dissipation ... 175 mW • Guaranteed Shift (Clock) Frequency ... 25 MHz • Applications: Stacked or Push·Down Registers, Buffer Storage, and Accumulator Registers • SN54LS299 and SN74LS299 Are Similar But Have Direct Overriding Clear' CLEAR OUTPUT CONTROLS logic: see description and function table description These Low-Power Schottkyt eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, SO and Sl, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock. • FUNCTION TABLE INPUTS MODE Clear Hold Shift Right Shift Left Load FUNCTION CLEAR SELECT S1 SO L L X L L L H INPUTS/OUTPUTS OUTPUT SERIAL CONTROL CLOCK G1t G2 t SL X L L L L t t H X X t H L L L L X H X X L L L H L H L L t H L H L L t X X X X X X X H H L L L t H H H L L L t H H H X X t OUTPUTS A/OA BlOB C/Oc O/Qo E/OE F/OF G/---VCC TYPICAL OF OUTPUTS EO,ES -----'t---- Vee I NPUT--:iiIII-+-....OUTPUT "\..---41_- OUTPUT Inputs 1 thru 7: Req = 9 kn NOM All others: Req = 18 kn NOM 877 7-448 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS348, SN74LS348 (TIM9908) 8-UNE-TO-3-UNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS REVISED AUGUST 1977 absolute maximum ratings ·over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS348 SN74 LS348 Storage temperature range . . . . . 7V . . . . . 7V _55°C to 125°C oOe to 70°C _65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS348 MIN Supply voltage, Vee 4.5 5 AO,Al,A2 High·level output current, 10H SN74LS348 NOM MAX MIN EO,GS 5.5 4.75 V -1 -2.6 mA -400 -400 /lA 12 24 mA 8 mA EO,GS Operating free·air temperature, T A 5 4 -55 UNIT 5.25 AO, Al, A2 Low-level output current, 10L NOM MAX 125 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage AO, Al, A2 output voltage Low-level VOL II IIH IlL ·state) output current 10H = -1 mA 10H = -2.6 mA VIL = VI Lmax 10H = -400/lA AO,Al,A2 Vec= MIN, VIL = VILmax AO, Al, A2 Input current at maximum Inputs 1 thru 7 input voltage All other inputs High-level input current Low-level input current lOS Short·drcuit output current§ ICC Supply current NOTE 2: Vee= MIN, EO,GS EO,GS Off·State (high-impedance IOZ SN74LS348 Inputs 1 thru 7 Outputs EO, GS 2.5 3.4 0.25 10L = 12 mA V -1.5 -1.5 V 2.4 3.1 2.7 3.4 0.4 10L = 24 mA 0.25 10L =4 mA 0.4 10L =8 mA 0.25 V 0.4 0.35 0.5 0.25 0.4 0.35 0.5 VO=2.7V 20 20 VO=O.4V -20 -20 0.2 0.2 0.1 0.1 40 40 Vec = MAX, All other inputs Outputs AO, A 1, A2 3.1 V 0.8 VIH = 2 V Vec= MAX, All other inputs 2.4 VI = 7 V VI = 2.7 V VI = 0.4 V VCC= MAX UNIT 0.7 Vec = MAX, Vec = MAX, Inputs 1 thru 7 2 11= -18 mA VIH=2V, VIH=2V, Output voltage SN54LS348 MIN TYPt MAX MIN TYPt MAX 2 Vee = MIN, High-level VOH TEST eONDITloNSt 20 20 -0.8 -0.8 -0.4 -0.4 -30 -130 -30 -130 -20 -100 -20 -100 Vee = MAX, Condition 1 13 25 13 25 See Note 2 Condition 2 12 23 12 23 V /lA mA /lA mA mA mA ICC (condition 1) is measured with inputs 7 and EI grounded. other inputs and outputs open. ICC (condition 2) is measured with· all inputs and outputs open. tFor conditions shown as MI N or MAX, USe the appropriate value specified under recommended operating conditions. tAli typical values are at Vee § Not = 5 V, T A = 25°C. more than one output should be shorted at a time. 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-449 TYPES SN54LS348, SN74LS348 (TIM9908) 8-LlNE-TO-3-LlNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS REVISED JANUARY 1981 switching characteristics, VCC = 5 V, TA = 25°C FROM (INPUT) PARAMETERlI tpLH 1 thru 7 tpHL tPLH tpHL tPZH tPZL tpLH TO (OUTPUT) WAVEFORM AO, A1, orA2 In-phase output 1 thru 7 AO, A1, or A2 EI AO, A1, orA2 o thru 7 o thru 7 tPLH tpHL EI GS tPLH tpHL EI EO In-phase output In-phase output In-phase output GS EI MIN TYP MAX UNIT 11 20 CL = 45 pF, RL = 667 .n, See Note 3 23 23 25 24 11 Out-ot-phase output EO tPHL tPLH tpHL tPHZ tPLZ Out-ot-phase output TEST CONDITIONS 26 38 CL = 15 pF CL - 5 pF AO, A1,orA2 RL = 667.n 18 14 17 40 55 21 17 36 21 25 18 23 40 27 35 9 11 RL = 2 k.n, See Note 3 17 30 35 35 39 41 ns ns ns ns ns ns ns ns 11 tpLH = propagation delay time, low-to-high-Ievel output tpHL = propagation delay time, hlgh-to-Iow-Ievel output tpZH = output enable time to high level tpZL = output enable time to low level tpHZ = output disable time from high level tpLZ = output disable time from low level NOTE 3: Load circuits and waveforms are shown on page 3-11. TYPICAL APPLICATION DATA II EO AO EI 'LS348 A1 A2 GS EO EI 'LS348 A2 EO GS 'LS348 EI ENABLE INPUT GS LSB FIGURE 1-PRIORITY ENCODER WITH UP TO 64 INPUTS. 181 7-450 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPE SN74351 DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS TTL MSI BULLETIN NO. DL-S 7712116, MARCH 1974-REVISED AUGUST 1977 • N OUAL-IN-L1NE PACKAGE (TOP VIEW) Dual 8-Line-to-1-Line Multiplexer That, Can Replace Two SN54151, SN74151 Multiplexers in Some Applications • Four Common Data Lines Permit Simultaneous Interdigitation with Parallel-to-Serial Conversion • 4-Bit Organization Is Easily Adapted to Handle Binary or BCD • Three-State Outputs Can Be Connected Directly to System Bus Lines • Enable Input Controls Impedance Levels of the 12 Data Inputs and Two Outputs r-__________DATA INPUTS __________ --JA~ ~ ABC '--y-----/ description SELECT INPUTS The SN74351 comprises two 8-line-to-l-line data selectors/multiplexers with full decoding on one monolithic chip. Symmetrically switching, complementary decode generators minimize decoder skew during changes at the select inputs and ensure that potentially erroneous effects are minimized at the data outputs. Four data inputs are exclusive to each multiplexer and four are common to both_ A common enable input is provided which, when high, causes both outputs to assume the high-impedance (off) state and simultaneously diverts the majority of the input current, which reduces the load significantly on the data input drivers. A low logic level at the enable input activates both outputs so that each will assume the complement of the level of the selected input. DATA INPUTS logic: see function table functional block diagram ENABLE 11..!!",,-1~)___- - - - - . . -_ _ _~ ,oo~"~I----~===±~~ 101 103 DATA INPUTS 0. 05 06 m 181 102 191 1141 1131 1121 11 A131 SELECT INPUTS { B (oil C (5) FUNCTION TABLE INPUTS ENABLE SELECT OUTPUTS G c B A 1Y 2Y H X X X L L L L L L L H Z 100 101 Z 200 201 L L H L L L H H L H L L 102 202 103 203 54 04 L H L H 05 05 L H H L 06 L H H H De 07 - 07 DATA {2:,:::: INPUTS -----t-'=f=t=!==L..J 201,-"I17.c.1 ,oo~I"~I----~====~J H = high level, L = low level, X = irrelevant Z = high impedance (off) iDa, 'fiST, __ .07 = The complement of the level of the respective o input 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-451 TYPE SN74351 DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS REVISED OCTOBER 1976 vcex-W-- schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUT_PUTS --~P--VCC 'N'UT Enable, DO thru 03: Req 04 thru 07: Req A, B, or C: Req ~ ~ ~ OUTPUT 4 k!l NOM 2 k!l NOM 6.5 k!l NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) I nput voltage . . . . . . . . Operating free-air temperature range Storage temperature range 7V 5.5V oOe to 70 0 e 0 -65°e to 150 e NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions NOM 5 MIN 4.75 Supply voltage, Vee High·level output current, IOH Low-level output current, IOL Operating free-air temperature, T A MAX 5.25 -0.8 16 70 0 UNIT V mA mA °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • VIH High·level input voltage Vil VIK low-level input voltage Input clamp voltage VOH High·level output voltage Val TEST CONDITIONS TVP:j: Vee~ Vee Vil Vee low·level output voltage Vil ~ ~ ~ ~ ~ MIN, II MIN, VIH~2V, 0.8 V, MIN, 0.8 V, 10H ~-0.8 10l ~ 10Zl Off state output current, low level voltage applied Vee ~ MAX, Va ~ 0.4 V VIH~2V, ~ MAX, VI ~ 5.5 V Vee~ MAX, VI ~ 2.4 V Vee 2.4 Enable, any select, High·level input current any DO thru 03 V V 0.4 V 40 JlA -40 JlA 1 mA JlA 80 Enable, any select, any DO thru 03 low-level input current V -1.5 40 D4 thru 07 III 0.8 3.4 0.2 16 mA VIH~2V, Input current at maximum input voltage mA VIH~2V, UNIT V -12 mA Vee ~ MAX, Va ~ 2.4 V IIH MAX 2 10ZH Off-state output current, high-level voltage applied II MIN Vee ~ MAX, VI -1.6 ~O.4V 04 thru 07 mA -3.2 Vee~ AnyO MAX, VI lOS Short-circuit output current§ Vl(enable) ~ 2 V Vee ~ MAX lee Supply current Vee ~ MAX, ~O.5, -40 -18 See Note 2 44 JlA -55 mA 66 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC ~ 5 V, T A ~ 25°C. §Not more than one output should be shorted at a ti(T1e. NOTE 2: ICC is measured with the enable input grounded, other inputs and both outputs open. 1076 7-452 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPE SN74351 DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS REVISED AUGUST 1977 switching characteristics, VCC PARAMETER~ tpLH tpHL =5 V, TA = 25°C FROM TO (INPUT) (OUTPUT) A, B, orC V Any D V tpLH CL=50pF, See Note 3 tpHL tZH tZL tHZ tLZ G V G V MIN TEST CONDITIONS CL = 5 pF, TVP RL=400n, RL = 400 n, See Note 3 MAX UNIT 20 30 20 30 10 22 10 22 18 20 33 33 6 20 10 20 ns ns ns ns ~ tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output tZH == output enable time to high level tZL == output enable time to low level tHZ == output disable time from high level tLZ == output disable time from low level NOTE 3: Load circu it and voltage waveforms are shown on page 3-10. TYPICAL APPLICATION DATA This application illustrates how common data can be interdigitated onto two serial data lines. It is useful for transmitting prefixes, suffixes, addresses, or similar functions. to t1 t2 t3 t4 t5 t6 t7 A~ B~ SELECT { _ _ _ _ _ _ _---. INPUTS C rO1~====== 100'.. 101 .. 1D2~r~0~---------------1D3'~~1 ________________ to t1 t2 t3 t4 t5 t6 t7 ------1103 9 (NEGATIVE LOGIC) D4 1V OUTPUT~ 1V D5 0 1 ' 5 D ~ .J D4 D6 _______________ D6'~~::::::::::::::: II VARIABLE{ 101 DATA ------1102 "-v---'~ 9 6 (POSITIVE LOGIC) D7 Cg~~~N { D7 .J"O ---++a SN74351 ---+++-o--ID7 6(NEGATIVE LOGIC) D6 D5 D4 2D3~r~0~--""'''''''''''--'''''-- 2D2.J 0 2D1~r~0~-------------- -------t2D3 VARIABLE DATA 2DO'~----------------8 (NEGATIVE LOGIC) { to t1 t2 t3 t4 t5 t6 t7 2V OUTPUT~ 2V 2D2 -------t2D1 \ 8 " 6 , vA~~~~~vIE ~~~~ON 2DO G DATA DATA ENABLE _ _ _ _ _ _ _---J G PRINTED IN USA. 877 TI ,annol assume any responsibilily lor any circuits shown or represenl Ihal Ihey ore Ir" Irom palenl inlringemenl. TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME IN ORDER TO IMPROVf DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS, TEXAS 75222 7-453 TTL MSI TYPES SN54LS352, SN74LS352 DUAL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS BULLETIN NO. DL·S 7612463, OCTOBER 1976 • Inverting Versions of SN54LS153, SN74LS153 • Schottky-Diode-Clamped Transistors • Permits Multiplexing from N lines to 1 line • Performs Parallel-to-Serial Conversion • Typical Average Propagation Delay Times: Data I nput to Output ... 15 ns Strobe Input to Output ... 19 ns Select Input to Output ... 22 ns o Fully Compatible with most TTL and DTL Circuits • Low PO\l\er Dissipation ... 31 mW Typical (Enabled) • I nverted Data SN54LS352 •.. J OR W PACKAGE SN74LS352 •.• J OR N PACKAGE (TOPVIEvyl logic: see function table FUNCTION TABLE SELECT DATA INPUTS STROBE OUTPUT B A CO C1 C2 C3 G V X X X X X X H H L L L X X X L H L L H X X X L L L H X L X X L H L H X H X X L L H L X X L X L H INPUTS description Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-DR-invert gates. Separate strobe inputs are provided for each of the two four-line sections. • H L X X H X L L H H X X X L L H H H X X X H L L Select inputs A and B are common to both sections. H = high level, L = low level, X = irrelevant absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . Input voltage . . . . . . . . . . . . . Operating free-air temperature range: SN54LS352 SN74LS352 Storage temperature range . . . . 7V . . . . 7V -55°C to 125°C oOe to 70°C . _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 1076 7-454 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS352, SN14LS352 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS functional block diagram STROBE lG (ENABLE) (1) lCO - - - - - - - - + - + - i H (5) lCl...;"..;...------l-+--H-L..J DATA 1 (4) lC2-----+-+-+-+-I-L~ lC3 (3) 2CO (10) 2Cl (11) 2C2 (12) 2C3 (13) DATA 2 STROBE 2G (ENABLE) (15) schematics of inputs and outputs EQUIVALENT OF EACH INPUT II TYPICAL OF BOTH OUTPUTS ----------~----VCC f20 VCC-------4~------ n I NOM 20 kn NOM INPUT--__. .-4~--eOUTPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7·455 TYPES SN54LS352, SN74LS352 DUAL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS recommended operating conditions SN54LS352 MIN 4.5 Supply voltage. Vee SN74LS352 NOM MAX MIN 5.5 4.75 5 NOM MAX 5 -400 High-level output current. 10H 5.25 V -400 p.A 8 mA DC 4 Low-level output current. IOL -55 Operating free-air temperature. T A 125 UNIT 0 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONSt PARAMETER SN54LS352 MIN VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage Vee= MIN. II = -18mA Vee = MIN. VIH = 2 V. VIL = VIL max. 10H Vee= MIN. VOL Low-level output voltage = -400 p.A VIH = 2 V. VIL = VIL max Input current at 2.5 TYP+ MAX UNIT V 0.7 0.8 V -1.5 -1.5 V 3.4 0.25 IIOL =4mA MIN 2 2 VIK Input clamp voltage 2.7 0.4 IIOL =8mA V 3.4 0.25 0.4 0.35 0.5 V Vee = MAX. VI =7 V 0.1 0.1 IIH High-level input current Vee= MAX. VI = 2.7 V 20 20 p.A IlL Low-level input current Vee= MAX. VI = 0.4 V -0.4 -0,4 mA lOS Short-circuit output current § leeL Supply current, output low Vee= MAX II • SN74LS352 TYP+ MAX maximum input voltage Vee= MAX. -100 -20 See Note 2 6.2 6.2 -100 mA 10 mA TYP MAX UNIT -20 10 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating. D +AII typical values are at VCC = 5 V, TA = 25 C. . § Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second. NOTE 2: ICCL is measured with the outputs open and all inputs grounded . switching characteristics, Vee = 5 V, TA = 25°e FROM TO (lNPUTI (OUTPUT! tpLH Data Y 13 20 ns tpHL Data Y 17 26 ns tPLH Select Y 19 29 ns tpHL Select Y 25 38 ns tPLH Strobe Y 16 24 ns tPHL Strobe Y 21 32 ns PARAMETER~ TEST CONDITIONS eL = 15pF. RL=2kn. See Note 3 MIN ~ tPLH == propagation delay tlrne, low-to-high-Ievel output tpHL == propagation delay tima, high-to-Iow-Ievel output NOTE 3: Load circuits and voltage waveforms are shown on page 3-11. 1076 7·456 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54LS353, SN74LS353 DUAL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS BULLETIN NO. DL-S 12464, OCTOBER 1976 • Inverting Versions of SN54LS253, SN74LS253 • Schottky-Diode-Clamped Transistors • Permits Multiplexing from N Lines to 1 Line • • Performs Parallel-to-Serial Conversion Typical Average Propagation Delay Times: Data Input to Output ... 12 ns Control Input to Output ... 16 ns Select Input to Output ... 21 ns • Fully Compatible with Most TTL and DTL Circuits • Low Power Dissipation ... 35 mW Typical (Enabled) • Inverted Data SN54LS353 .•• J OR W PACKAGE SN74LS353. " J OR N PACKAGE (TOP VIEW) DATA INPUTS , -____-JA~____~ '------___.v,....----J DATA INPUTS logic: see function table description Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate output control inputs are provided for each of the two four-line sections. The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus line to a high or low logic level. logic FUNCTION TABLE SELECT INPUTS A B CO C1 C2 C3 X X X L L L L H H H H L L H H L L H H L H X X X X X X X X L H X X X X X X X X X L H DATA INPUTS X X X X X X L H X X X X OUTPUT OUTPUT CONTROL G V H Z L H L L L H L L L H L L L H L L II Select inputs A and Bare comm,on to. both sections. H = high level. L = low level. X = irrelevant. Z = high impedance (off) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . . Off-state output voltage . . . . . Operating free-air temperature range: SN54LS353 SN74LS353 Storage temperature range . . . . NOTE 7V 7V 5.5 V -55°C to 125°C aOe to 7aoe -65°C to 15aoe 1: Voltage values are with respect to network ground terminal. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-457 TYPES SN54LS353, SN74LS353 DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS functional block diagram OUTPUT CONTROL IG 1CO~(~6)-------------------------+~~~ 1C1J(~5)---------------------+~~=t~ DATA 1 B SELECT{ (2) A (14) DATA 2 OUTPUT 2Y I OUTPUT (15) CONTROL 2G schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS ----i.....--VCC VCC 20 kn NOM INPUT -- Dol u .... ~ii' OUTPUT' " " "7 1076 7·458 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DAL.L.AS, TEXAS 75222 TYPES SN54LS353, SN74LS353 DUAL 4-UNE-TO-l-UNE DATA SELECTORS/ MULTIPLEXERS WITH 3-STATE OUTPUTS recommended operating conditions SN74LS353 SN54LS353 MIN 4.5 Supply voltage, VCC NOM MAX 5 5.5 -1 High·level output current, IOH Low-level output current, IOL MIN 4.75 NOM MAX 5 V -2.6 8 mA mA 70 °c 4 -55 Operating free-air temperature, T A 125 UNIT 5.25 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL VIK Low-level input voltage I nput clamp voltage VOH High-level output voltage VOL Low-level output voltage SN54LS353 TEST CONDITIONSt PARAMETER MIN 2 VCC = MIN, 11=-18mA VCC = MIN, VIH=2V, VCC = MIN, VIH = 2 V, 2.4 10L = 4 mA VIL = VIL max Off-State (high-impedance state) output current Input current at MIN 2 3.4 0.25 2.4 0.4 10L = 8 mA VCC = MAX, VIH = 2 V TYP+ MAX UNIT V 0.7 -1.5 VIL = VIL max, IOH = MAX 10Z SN74LS353 TYP+ MAX 0.8 V -1.5 V V 3.1 0.25 0.4 0,35 0.5 Vo = 2.7 V 20 20 Vo = 0.4 V -20 -20 V /lA VCC = MAX, VI = 7 V 0.1 0.1 mA IIH High-level input current VCC = MAX, VI=2.7V 20 20 IlL Low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 /lA mA lOS Short-circuit output current § VCC = MAX -130 mA ICC Supply current VCC = MAX, II maximum input voltage -130 -30 -30 See Note 2 Condition A 7 12 7 12 Condition B 8.5 14 8.5 14 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured with the outputs open under the following conditions: 1.1 A. All inputs grounded. B. Output control at 4.5 V, all inputs grounded. switching characteristics, Vee PARAMETER~ tpLH I = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) TEST CONDITIONS Data Y tpHL tpLH tPHL tPZH Select Output tPZL tpHZ Control tpLZ Control Output CL=15pF, Y RL=2k!!, See Note 3 Y CL=5pF, Y RL = 2 kH, See Note 3 MIN TYP MAX UNIT 11 25 13 20 20 45 21 32 11 23 15 23 27 12 41 27 ns ns ns ns ~ tpLH == Propagation delay time, low-to-high-Ievel output tpHL == Propagation delay time, high-to-Iow·level output tpZH == Output enable time to high level tpZL == Output enable time to low level tpHZ == Output disable time from high level tpLZ == Output disable time from low level NOTE 3: Load circuit and waveforms are shown on page 3·11. 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-459 THRU Sr~54LS629, SN74LS624 THRU SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS TYPES TTL MSI Sr~54LS624 02501, JANUARY 1980 - REVISED OCT08ER 1980 • Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from Output Circuitry • Highly Stable Operation over Specified Temperature and/or Supply Voltage Ranges SN54lS' ••• J OR W PACKAGE SN74lS' ••. J OR N PACKAGE 'LS624 (TOP VIEW) RANGE DEVICE SIMilAR NUMBER COMP'l ENABLE Rext VCO's ZOUT INPUT TYPE TO yes yes yes no 'lS624 'lS324 single yes no no 'lS625 'lS325 no dual yes no yes no 'lS626 'lS326 dual 'lS628 'lS327 'lS324 dual single no yes yes no yes no yes 'lS629 'lS124 dual no yes yes no 'lS627 no logic: see description description 'lS625 (TOP VIEW) These voltage-controlled oscillators (VeO's) are improved versions of the original veo family: SN54LS124, SN54LS324 thru SN54LS327, SN74LS124, and SN74LS324 thru SN74LS327. These new devices feature improved voltage-tofrequency linearity, range, and compensation. With the exception of the 'LS624 and 'LS628, all of these devices feature two independent veo's in a single monolithic chip. The 'LS624, 'LS625, 'LS626 and 'LS628 have complementary Z outputs. The output frequency for each veo is established by a single external component (either a capacitor or a crystal). in combination with voltage-sensitive inputs used for frequency control and frequency range. Each device has a voltage-sensitive input for frequency control; however, the 'LS624, 'LS628, and 'LS629 devices also have one for frequency range. (See Figures 1 thru 6). I logic: see description 'lS626 (TOP VIEW) The 'LS628 features two Rexternal pins that can offer more precise temperature compensation than its 'LS624 counterpart. 12 lY 1 leXl OUTPUT OUTPUT ENABLE logic: see description 'lS627 (TOP VIEW) 'lS628 (TOP VIEW) 'lS629 (TOP VIEW) e:l RANGE leXl z 2Y 2CX2 ENABLE OUTPUT GND ~ R~E leXl lex:z Vee Vee ENA~U ~:UT G~D FREQUENCY CONTROL logic: see description logic: see description logic: see description NC-No internal connection Copyright © 1980 by Texas Instruments Incorporated 7-460 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 281 TYPES SN54LS624 THRU SN54LS629, SN14LS624 THRU SN14LS629 VOLTAGE-CONTROLLED OSCILLATORS Figure 3 and Figure 6 contain the necessary information to choose the proper capacitor value to obtain the desired operating frequency. The devices can also be operated from a crystal by connecting a fundamental series resonant crystal across the Cext pins. (Fundamental frequency ';;;;20 MHz.) The frequency control should be connected to 5 volts and, where applicable, the range control should also be connected to 5 volts. A single 5·volt supply can be used; however, one set 'of supply voltage and ground pins (VCC and Gnd) is provided for the enable, synchronization·gating, and output sections, and a separate set (eVCC and eGnd) is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. For operation of frequencies greater than 10 MHz, it is recommended that two independent supplies be used. Oi!;abling either VCO of the 'LS625 and 'LS627 can be achieved by removing the appropriate8Vcc. An enable input is provided on the 'LS624, 'LS626, 'LS628 and 'LS629. When the enable input is low the output is enabled: when the enable input is high, the internal oscillator is disabled, Y is high, and Z is low. Caution! Crosstalk may occur in the dual devices ('LS625, 'LS626, 'LS627, and 'LS629) when both VCO's are operated simultaneously. The pulse-synchronization-gating section ensures that the first output pulse is neither clipped nor extended. The duty cycle of the square-w~ve output is fixed at approximately 50 percent. The SN54LS624 thru SN54LS629 are characterized for operation over the full military temperature range of -55°C to 125°C; the SN74LS624 thru SN74LS629 are characterized for operation from O°C to 70°C. functional block diagram (positive logic) G cx~------~~--~ -flfL }-----z FC --------~--~FC RC ----~--i'_--_IRC ('LS624, 'LS628, 'LS629 only) EN . ,.......- y I EN ~.-------~----~ absolute maximum ratings over operating free-air temperature range (unless otherwise noted) . 7V . 7V VCC . -55°C to 125°C O°C to 70°C . -65°C to 150°C Supply voltage, VCC (see Notes 1 and 2) Input voltage: Enable input. . . . . Frequency control or range inpu~ Operating free-air temperature range: SN54LS' Circuits SN74LS' Circuits Storage temperature range +The enable input i. provided only on the 'LS624, 'LS626, 'LS628, and 'LS629. "'The range input I. provided only on 'LS624, 'LS628, and 'LS629. NOTES: 1. Voltage values are with respect to the appropriate ground terminal. 2. Throughout this data sheet, the symbol otherwise noted. Vee is used for the voltage applied to both the Vee and e Vee terminals, unless 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-461 TYPES SN54LS624 THRU SN54LS629, SN74LS624 THRU SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS recommended operating conditions SN54LS' Supply voltage, Vee SN74LS' NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V 5 0 5 V 0 Input voltage at frequency control or range input, Vl(freq) or Vl(rng)& UNIT MIN High-level output current, 10H 1.2 1.2 mA Low-level output current, 10L 12 24 mA 20 MHz 70 °e 1 Output frequency, fo Hz 1 20 Operating free-air temperature, T A -55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54LS' TEST CONOITIONSt MIN TYP+ SN74LS' MAX MIN TYP+ MAX UNIT High-level input VIH 2 voltage at enable. 2 V Low-level input VIL voltage at enable. VIK Input clamp voltage at enable. VOH High-level output voltage VOL Low-level output voltage II Input current Freq control or range" Vee~ MIN, II =-18mA Vee= MIN, EN at VIL max, 10H = -1.2 mA, See Note 3 Vee = MIN, EN at VIL max, 2.5 Vee = MAX 0.8 V -1.5 -1.5 V 3.4 0.25 10L= 12mA See Note 3 0.7 2.7 0.4 10L = 24 mA 3.4 V 0.25 0.4 0.35 0.5 VI = 5 V 50 250 50 250 VI = 1 V 10 50 10 50 V p.A Input current II at maximum Enable· Vee= MAX, VI = 7V 0.2 0.2 mA Enable· Vee= MAX, VI = 2.7 V 40 40 p.A Vee= MAX, VI = 0.4 V -0.8 mA -225 mA input voltage High-level I IIH input current Low-level IlL lOS input current Enable· Short-circuit output current § Supply current; total into lee Vee and e Vee pins -0.8 -40 Vee = MAX Vee= MAX, Enable· = 4.5 V See Note 4 -225 'LS624 20 35 -40 20 35 'LS625 35 55 35 55 'LS626 35 55 35 55 'LS627 35 55 35 55 'LS628 20 35 20 35 'LS629 35 55 35 55 mA t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°C. § Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. "The range input is provided onlv on the 'LS624, 'LS628, and 'LS629 . • The enable input is provided onlv on the 'LS624, 'LS626, 'LS628, and 'LS629. NOTES: 3. VOH for Y outputs and VOL for Z outputs are measured while enable inputs are connected to ground, with individual resistors connected from eX1 to Vee and from eX2 to ground. The resistor connections are reversed for testing VOH for Z outputs and VOL for Y outputs. 4. For 'LS624, 'LS626, 'LS628, and 'LS629, I ee is measured with the outputs disabled and open. For 'LS625 and 'LS627, ICC is Vee = MAX, and with the other Vee and outputs open. measured with one G 7-462 e 281 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS624 THRU SN54LS629, SN74LS624 THRU SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS switching characteristics, VCC = 5 V (unless otherwise noted), RL = 667 n, CL = 45 pF, TA = 25°C PARAMETER Output frequency Cext = 50 pF 'LS625, 'LS626, 'LS627 MIN TYP MAX Vl(freq) = 5 V 7 9.5 12 Vl(freq) = 0 V 0.9 1.2 1.5 v, Vl(rng) Vl(freq) = 0 v, Vl(rng) Vl(freq) = 5 fO 'LS624, 'LS62B, 'LS629 TEST CONDITIONS MIN TYP MAX =0 V 15 20 25 =5V 0.7 1 1.3 UNIT MHz schematics of inputs and outputs EQUIVALENT OF EACH ENABLE INPUT ('LS624, 'LS626, 'LS62B, AND 'LS629) EQUIVALENT OF EACH FREQUENCY CONTROL OR ('LS624, 'LS628, AND 'LS629) RANGE INPUT TYPICAL OF ALL OUTPUTS --------~~-VCC VCC--------~._- VCC------~----- 25 kn NOM 9 kn NOM '----+--OUTPUT INPUT~~__~---'- INPUT-.,.,.......--1 20kn NOM TYPICAL CHARACTERISTICS I 30 25 'LS624, 'LS628, 'LS629 'LS624, 'LS628, 'LS629 OUTPUT FREQUENCY OUTPUT FREQUENCY 'LS624, 'LS628, 'LS629 OUTPUT FREQUENCY EXTERNAL CAPACITANCE FREQUENCY-CONTROL INPUT VOLTAGE VCC' 5 V c.xt· 50 pF 600 (,LS6281 TA-25°C n r- Rext • l~ ~\\,~~ V y ./ V k:: :..-::f-""" V /'V i..--' ~ ~ V. / /' V~ ~ ......~ ~ fS 100 M.----,--,----,----.-,----. 25 :I: :I: :; ~20~+-+-~~_+~~' jI5~+-+-~~~~~ ! ~ ~ ~10r-+-+79r.~-7~-~kf\ 1 M I-="-d----"'-~~ I ~ l00kr------r-... - o '0 10 kf---t--t----'" 1k~-l--+-_+~ 100r---f--+---+---+~+~ 10r---t--+--t---+--t-~ o~ o 1 2 3 4 VI(f,eql-F,equency-Cont,ollnput Voltage-V FIGURE 1 1~~~~~~~~~~~ 10- 11 10- 10 10-9 VI(f,eql-F,equency-Cont,ollnput Voltage-V FIGURE 2 10-8 10-7 10-6 10-5 Cext-External Capacitance-F FIGURE 3 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7·463 TYPES SN54LS624 THRU SN54LS629, SN74LS624 THUR SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS TYPICAL CHARACTERISTICS 'LS625, 'LS626, 'LS627 'LS625, 'LS626, 'LS627 10 OUTPUT FREQUENCY OUTPUT FREQUENCY FREQUENCY·CONTROL INPUT VOLTAGE FREQUENCY·CONTROL INPUT VOLTAGE 30 r-V~C =IS) Jccls J L Cext • SO pi 2S -Cut" 1SpF TA" 2S·C -TA = 2S·C / ./ / V / V / V . . . .V- ...... V V o ./ V o o V V- o 1 Vl(lreql-Frequency·Control Input Voltage-V V1(freq)-Frequency-Controllnput Voltage-V FIGURE 5 FIGURE 4 'LS625, 'LS626, 'LS627 OUTPUT FREQUENCY ENABLE TIME EXTERNAL CAPACITANCE FREQUENCY looom~3 VCC" 5 V TA' 2S·C X I lM~~~~~-+--~--~--4 ~1OOkr-~--~~~--~~-r--4 ! 10kr-~--~--~~~--~--4 ; o lk~~--~---+~~~~--4 ~ I" I E ~100E==i=i~~~~~~~t$~ ~ I j 100 ~ 3V 1.3V ' O V : : : -.... _1 . _ _ __ t ~~t.n 10r-~--~---+---r--~~ I 1~~ __ ~ __ ~ __- L__ 10- 11 10-10 10-9 10-8 10-7 :::J 1.3 ~==t.Jl.J f- ~~ 10-6 10-S Cext-External Capacitance-F 7 10 20 40 'o-Output Frequency-MHz FIGURE 6 FIGURE 7 70 100 TYPICAL APPLICATIONS DATA <:ext FREO CONT VCO RNGA EN. N fO=-;:1f1 AThe range input is provided only on the 'LS624, 'LS628, and 'LS629. +The enable input is provided only on the 'LS624, 'LS626, 'LS628, and 'LS629. FREO CONT VCO FIGURE A-PHASE-LOCKED LOOP 7-464 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS630,SN54LS631,SN74LS630,SN74LS631 .16-8IT PARALLEL ERROR DETECTION AND CORRECTION'0255CIRCUIT • Detects and Corrects Single·Bit Errors M99630, TIM99631 • Detects and Flags Dual-Bit Errors • Fast Processing Times: Write Cycle: Generates Check Word in 45 ns Typical Flags Errors in 27 ns Typical Read Cycle: • Power Dissipation 600 mW Typical • Choice of Output Configurations: 'LS630 ... 3-State 'LS631 ... Open-Collector SN54LS' ... J.PACKAGE SN74LS' ... N PACKAGE (TOP VIEW) DATA BITS description T.he 'LS630 and 'LS631 devices are 16-bit parallel error detection and correction circuits (EDACs) in 28-pin, 600-mil packages. They use a modified Hamming code to generate a 6-bit check word from a 16-bit data word. This check word is stored along with the data word during the memory write cycle. During the memory read cycle, the 22-bit words from memory are processed by the EDACs to determine if errors have occurred in memory. DEF Vce DBa SEF DBl Sl DB2 so }CONTROL DB3 CBO DB4 CBl DBS CB2 DB6 CB3 DB7 CB4 DBB CBS CHECK BITS DB9 DB10 DB1S} DB14 DATA DBll DB13 GND DB12 BITS Single-bit errors in the 16-bit data word are flagged and corrected. Single-bit errors in the 6-bit check word are flagged, and the CPU sends the EDAC through the correction cycle even though the 16-bit word is not in error. The correction cycle will simply pass along the original 16-bit word in this case and produce error syndrome bits to pinpoint the error-generating location. Dual-bit errors are flagged but not corrected. These dual errors may occur in any two bits of the 22-bit word from memory (two errors in the 16-bit data word, two errors in the 6-bit check word, or one error in each word). • The gross-error condition of all lows or all highs from memory will be detected. Otherwise, errors in three or more bits of the 22-bit word are I:l"eyond the capabilities of these devices to detect. CONTROL FUNCTION TABLE Memory Control EDAC Function Data I/O Check Word I/O Error Flags I I Cycle Sl SO WRITE L L Generate Check Word Input Data Output Check Word L READ L H Read Data & Check Word Input Data Input Check Word L READ H H Latch & Flag Errors Latch Data Latch Check Word Enabled READ H L Output Corrected Data OutPl!t Syndrome Bits Enabled Correct Data Word & Generate Syndrome Bits SEF DEF 1 L L Copyright © 1980 by Texas Instruments Incorporated 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-465 TYPES SN54LS630,SN54LS631,SN14LS630,SN14lS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS functional block diagram so .... S1 . 51 so FUNCTIO SELECTO" sO-S1 SO-S1 ... - r.- ~ ,6/ LATCH ~C PARITY GENERATOR ~ CHECK BIT I/~~ CBOTHRU CB5 ~ / 12 ~ -+ - BUFFER OE - +- LATCH - 12 ,6/ , ... , 16/ / OE ERROR DETECTOR ~ SEF ~ DEF J2 +-C DATA BIT II DBO THRU 0 ~15~ ~ 16/ , ~ BUFFER ERROR CORRECTOR ~ ERROR DECODER OE • ERROR FUNCTION TABLE Total Number of Errors 16-Bit Data Error Rags 6-Bit Checkword SEF DEF Data Correction 0 0 L L 1 0 H L Correction 0 1 H L Correction 1 2 0 1 H H Interrupt 0 2 H H Interrupt H H Interrupt Not Applicable In order to be able to determine whether the data from the memory is acceptable to use as presented to the bus, the EDAC must be strobed to enable the error flags and the flags will have to be tested for the zero condition. The first case in the error function table represents the normal, no-error condition. The CPU sees lows on both flags. The next two cases of single-bit errors require data correction. Although the EDAC can discern the single check bit error and ignore it, the error flags are identical to the single error in the 16-bit data word. The CPU will ask for data correction in both cases. An interrupt condition to the CPU results in each of the last three cases, where dual errors occur.' error detection and correction details During a memory write cycle, six check bits (CBO-CB5) are generated by eight-input parity generators using the data bits as defined below. During a memory read cycle, the 6-bit check word is retrieved along with the actual data. 380 7-466 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS630,SN54LS631,SN74LS630,SN74LS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS 16-BIT DATA WORD CHECKWORO BIT 0 1 CBO x x CB1 x CB2 CB3 x 2 x x x x x CB4 3 4 x x 5 x x x x x 6 8 9 10 x x x x x x x x 12 13 x 14 15 x x x CB5 11 x x x x x x 7 x x x x x x x x x x x x x x The Ilx check bits are parity bits derived from the matrix of data bits as Indicated by "x" for each bit. Error detection is accomplished as the 6-bit check word and the 16-bit data word from memory are applied to internal parity generators/checkers. If the parity of all six groupings of data and check bits are correct, it is assumed that no error has occurred and both error flags will be low. (It should be noted that the sense of two of the check bits, bits CBa and CB 1, is inverted to ensure that the gross-error condition of all lows and all highs is detected.) If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error flag or flags will be set high. Any single error in the 16-bit data word will change the sense of exactly three bits of the 6-bit check word. Any single error in the 6-bit check word changes the sense of only that one bit. In either case, the single error flag will be set high while the dual error flag will remain low. Any two-bit error will change the sense of an even number of check bits. The two-bit error is not correctable since the parity tree can only identify single-bit errors. Both error flags are set high when any two-bit error is detected. Three or more simultaneous bit errors can fool the EDAC into believing that no error, a correctable error, or an uncorrectable error has occurred and produce erroneous results in all three cases. Error correction is accomplished by identifying the bad bit and inverting it. Identification of the erroneous bit is ach ieved by comparing the 16-bit data word and 6-bit check word from memory with the new check word with one (check word error) or three (data word error) inverted bits. As the corrected word is made available on the dataword I/O port, the check word I/O port presents a 6-bit syndrome error code. This syndrome code can be used to identify the bad memory chip. ERROR SYNDROME TABLE ERROR LOCATION DBa DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBB DB9 DB10 DB11 DB12 DB13 DB14 DB15 CBO CB1 CB2 CB3 CB4 CB5 NO ERROR CBO L L H L L H H H L L L H H L H H L H H H H H H CB1 L H L L H L L H L H H L H H L H H L H H H H H SYNDROME ERROR CODE CB2 CB3 CB4 H H L H L L H L L H H L H L L H L L H L L L L L H H H L H H H L H H L H L L H H H L H H L L H L H H H H H H L H H H H L H H L H H H H H H CB5 H H H H H H H H L • I L L L L l L L H H H H H L H 380 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-467 TYPES SN54LS630,SN54LS631,SN74LS630,SN74LS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF DEF AND SEF OUTPUTS ----~--VCC VCC--~~ INPUT. '-t~~-OUTPUT TYPICAL OF CB AND DB ('LS630) TYPICAL OF CB AND DB ('LS631) __ ~OUTPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input voltage: SO and S1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V eB and DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . _ ... _ . . . . . . . . . . . . . . . _ . . . . . . . . . . _ .. 5.5 V Operating free-air temperature range: SN54LS630, SN54LS631 . . . . . . . . . . . . . . . . _ . . . .. _55°C to 125°C SN74LS630, SN74LS631 ....................... " oOe to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . __ . . . . . . . .. _65°C to 150°C a NOTE 1: Voltage Values are with respect to network ground terminal. recommended operating conditions Supply voltage, VCC High-level output current, IOH High-level output voltage, VOH Low-level output current, IOL SN54LS630 SN74LS630 SN54LS631 SN74LS631 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 CB or DB, 'LS630 only DEF or SEF CB or DB, 'LS631 only CB or DB DEF or SEF -1 -1 -0.4 -0.4 5.5 5.5 12 24 4 t Setup time, tsu CB or DB to S1 Hold time, th CB or DB after S1 t Operating free-air temperature, T A UNIT MIN 8 10 10 15 15 -55 125 0 V mA V mA ns ns 70 °c tThe upward-pointing arrow Indicates a transition from low to high. 181 7-468 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265. TYPES SN54LS630,SN54LS631,SN74LS630,SN74LS631 18-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST eONDITIONst PARAMETERS VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH eB or DB High-level output voltage DEF or SEF eB or DB VOL Low-level output voltage Vee - MIN, VIH = 2 V, VIL = VIL min Vee = MIN, VIH = 2 V, DEF or SEF VIL=VILmax Off-state output current, 10ZH eB or DB high-level voltage applied Off-state output current, 10ZL II eB or DB Vee - MAX, TYPt MAX 11=-1BmA V O_B V -1.5 -1.5 V 10H = MAX 2.4 3.3 2.4 3.2 10H = -400/lA 2.5 3.4 2.7 3.4 0.25 IOL=12mA 0.25 0.4 10L = B mA VO=2.7V, VO=O.4V, V 0.25 0.4 IOL-24mA 10L =4 mA 0.4 0.35 0.5 0.25 0.4 0.35 0.5 20 /lA /lA -20 -20 eB or DB Vee = MAX, VI=5.5V 0.1 0.1 input voltage SO or S1 VIH=4.5V VI = 7 V 0.1 0.1 SO and S1 at 2 V V 20 Input current at maximum low-level voltage applied UNIT 0_7 SO and S1 at 2 V Vee= MAX, MIN 2 2 Vee= MIN, SN74LS630 SN54LS630 MIN TYPt MAX mA IIH High-level input current Vee = MAX, VI - 2.7 V 20 20 /lA IlL Low-level input current Vee = MAX, VI =0.4 V -0.2 -0.2 mA lOS Short-circuit output eB or DB current~ DEF or SEF Vee = MAX, -30 -130 -30 -130 -20 -100 -20 -100 mA Vee = MAX, SO and S1 at 4.5 V, lee Supply current All eB and DB pins grounded, 143 230 143 230 mA DEF and SEF open .electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage 10H High-level output current TEST eONDITIONst SN74LS631 TYPt MAX MIN TYPt MAX 2 DEF or SEF Vee = MIN, II =-18mA Vee= MIN, V'IH = 2 V, 10H = -400 /lA, Vee= MIN, VIH = 2 V, eB or DB Vee= MIN, Low-level output voltage VIH=2V, DEF or SEF VIL = VILmax I nput current at eB or DB Vee= MAX, maximum input voltage SO or S1 VIL = VILmax O.B -1.5 2.5 3.4 VOH = 5.5 V, -1.5 2.7 3.4 100 VIL = VIL max 10L = 12mA IOL=4mA 100 0.4 0.25 0.35 0.5 0.25 0.4 0.25 0.4 10L -8mA 0.35 V V V 0.25 10L = 24mA /lA 0.4 V 0.5 VIH=4.5V VI=5.5V i VI = 7 V ! IIH High-level input current Vee = MAX VI = 2.7 V 20 20 IlL Low-level input current Vee = MAX, VI = 0.4 V -0.2 -0.2 mA -100 mA 180 mA II lOS Short-circuit output current~ DEF or SEF Vee = MAX, -20 100 100 100 100 -100 • UNIT V 2 0.7 eB or DB VOL SN54LS631 MIN -20 /lA /lA. Vee = MAX, SO and S1 at 4.5 V, lee Supply current All eB and DB grounded, 113 180 113 SEF and DEF open tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli tYPical values are at Vee = 5 V, T A = 25°e. ~ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-469 TYPES SN54LS630.SN 54LS631.SN74LS630.SN74LS631 16-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS switching characteristics, Vee = 5 V, TA = 25°e, eL FROM (INPUT) PARAMETER TO (OUTPUT) tpLH Propagation delay time, low-to-high-Ievel output O tpHL Propagation delay time, high-to-Iow-Ievel output O DB CB tPLH Propagation delay time, low-to-high-Ievel output* S1t DEF SEF tpZH Output enable time to high level# SO~ CB, DB TEST CONDITIONS MIN SO atO V, S1 atO V, R L = 667 n, See Figure 1 SOat3V, RL = 2 kn, See Figure 1 S1 at3 V, RL = 667 See Figure 2 S1 at3 V, RL = 667 See Figure 1 n, n, tpZL Output enable time to low level# SO~ CB,DB tpHZ Output disable time from high level· SOt CB,DB S1 at3 V, RL = 667 See Figure 2 n, CB, DB S1 at3 V, RL = 667 See Figure 1 n, tpLZ Output disable time from low level· SOt switching characteristics, Vee = 5 V, TA = 25°e, eL 'LS630 TYP MAX 31 45 45 65 27 40 20 30 UNIT ns ns ns 24 40 ns 30 45 ns 43 65 ns 31 45 ns =45 pF, see Figure 1 FROM (INPUT) TO (OUTPUT) tPLH Propagation delay time, low-to-high level output O tPHL Propagation delay time, high-to-Iow-Ievel output O DB CB tpLH Propagation delay time, low-to-high-Ievel output* S1t tPHL Propagation delay time, high-to-Iow-Ievel output# tPLH Propagation delay time, low-to-high-Ievel output· SOl Sot PARAMETER • = 45 pF DEF SEF CB,DB CB,DB TEST CONDITIONS SO at 0 V, RL = 667 MIN S1 at OV, 38 45 n kn SO at 3 V, RL = 2 S1 at 3 V, S1at3V, RL = 667 RL = 667 'LS631 TYP MAX kn kn 27 20 28 33 55 65 40 30 45 50 UNIT ns ns ns ns ns ns 0These parameters describe the time Intervals taken to generate the check word during the memory write cycle . *These parameters describe the time Intervals taken to flag errors during the memory read cycle. #These parameters describe the time Intervals taken to correct and output the data word and to generate and output the syndrome error code during the memory read cycle. ·These parameters describe the time Interva'is taken to disable the CB and DB buses In preparation for a new data word during the memory read cvcle. PARAMETER MEASUREMENT INFORMATION VCC = 5 V ~1 OUTPUT ,... OF CIRCUIT 0-----....----------, RL OUTPUT OF CIRCUIT C L = 45 pF;:~ - C L =45pF FIGURE 1-0UTPUT LOAD CIRCUIT RL = 667 12 FIGURE 2-0UTPUT LOAD CIRCUIT 181 7470 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL n-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS TTL MSI BULLETIN NO. DL·S 12350 OCTOBER 1975 - • Choice of 8 Latches or 8 D-Type Flip-Flops In a Single Package • 3-State Bus-Driving Outputs • Full Parallel-Access for Loading • Buffered Control Inputs • Clock/Enable Input Has Hysteresis to Improve Noise Rejection • P-N-P Inputs Reduce D-C Loading on Data Lines (,S373 and 'S374) REVISED JUNE 1979 SN54LS373, SN54S373 ••• J PACKAGE SN74LS373, SN74S373 ••• J OR N PACKAGE (TOP VIEW) ENABLE LATCH Vee • SN54LS363 and SN74LS364 Are Similar But Have Higher V OH For MOS Interface OUTPUT CONTROL 1Q 'LS373, 'S373 FUNCTION TABLE OUTPUT ENABLE ENABLE LATCH L L logic: see function table D OUTPUT H H H H L L L L X X X 00 H SN54LS374, SN54S374 •.. J PACKAGE SN74LS374, SN74S374 ••. J OR N PACKAGE (TOP VIEW) Z Vee 'LS374, 'S374 FUNCTION TABLE OUTPUT CLOCK D OUTPUT t t H H L L L L L 00 H X X X ENABLE L • Z logic: see function table See explanation of function tables on page 1-13. description These 8-bit registers feature totem-pole three-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines ~in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 'L8373 and '8373 are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up. Copyright © 1979 by Texas I nstruments Incorporated 679 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-471 TYPES SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS description (continued) The eight flip-flops of the 'LS374 and 'S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip·flops. That is, the old data can be retained or new data can be entered even while the outputs are off. 'LS374, 'S374 POSITIVE·EDGE-TRIGGERED FLIP-FLOPS 'LS373, 'S373 TRANSPARENT LATCHES OUTPUT _1_1.;...1- - - - - 0 CONTROL • OUTPUT _11_1- - - - - 0 CONTROL 3D 30 40 40 50 50 50 60 60 60 60 70 70 70 70 CLOCK 1076 7-472 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS373, SN54LS374, SN74LS373, SN74LS374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED fLIP-FLOPS - REVISED DECEMBER 1980 schematic of inputs and outputs 'LS373 EQUIVALENT OF DATA INPUTS vec Req INPUT EQUIVALENT OF ENABLE AND OUTPUT CONTROL INPUTS ----..--Vee Vee---_-- = 20 k.l1 NOM o -INPUT a 'LS374 EQUIVALENT OF CLOCK AND OUTPUT CONTROL INPUTS EQUIVALENT OF DATA INPUTS vee TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS ------VCC V c c - - -......- - 30 k.l1 NOM INPUT -- INPUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage Off-state output voltage Operating free-air temperature range: SN54LS' SN74LS' Storage temperature range 7V 7V 7V -55°C to 125°C O°C to 70°C -65°C to 150°C II NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN74LS' SN54LS' Supply voltage, Vee NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V 5.5 V High-level output voltage, VOH 5.5 High-level output current, 10H Width of clock/enable pulse, tw Data setup time, tsu Data hold time, th Operating free-air temperature, T A t +The arrow indicates the transition UNIT MIN -1 -2.6 High 15 15 Low 15 15 'LS373 5+ 5+ 'LS374 20t 20t 'LS373 20+ 20+ 'LS374 °t -55 of the clock/enable input used for reference: ns ns ns Ot 125 t 0 for the low-to-high transition, rnA 70 °e +for the high-to-Iow transi- tion. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-473 TYPES SN54LS373, SN54LS374, SN74LS373, SN74LS374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS REylSED AUGUST 1977 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage 10ZH 10ZL II Vce = MIN, 11=-18mA VCC - MIN, VIH=2V, 2.4 VIL = VILmax,lOH = MAX VCC = MIN, Off-state output current, VCC = MAX, high-level voltage applied VO=2.7V Off-state output current, VCC = MAX, low-level voltage appl ied Va = 0.4 V maximum input voltage MIN TYP:j: SN74LS' MAX MIN 2 VIH=2V, VIL = VILmax Input current at SN54LS' TEST eONDITIONst V V -1.5 -1.5 V 2.4 3.4 0.4 VIH - 2 V, VIH - 2 V, VI =7 V UNIT 0.8 IIOL - 24 mA VCC = MAX, MAX 0.7 0.25 IIOL=12mA TYP:j: 2 3.1 V 0.25 0.4 0.35 0.5 V 20 20 /.lA -20 -20 /JA 0.1 0.1 mA IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 /JA IlL Low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 mA lOS Short-circuit output current§ VCC = MAX ICC Supply current VCC= MAX, Output control at 4.5 V -30 -130 -30 -130 ,'LS373 24 40 24 40 I'LS374 27 40 27 40 mA mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°e. § Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. switching characteristics, Vee = 5 V, T A = 25°C PARAMETER • FROM (INPUT) TO TEST CONDITIONS (OUTPUT) 'LS373 'LS374 MIN TYP MAX MIN TYP MAX 35 50 f max tPLH Data tPHL tpLH Clock or tpHL enable tpZH Output tpZL Control tpHZ Output tpLZ Control NOTES: Any Q CL=45pF, RL=667!l, Any Q See Notes 2 and 3 Any Q Any Q C~ = 5 pF, RL = 667 !l , See Note 3 12 18 12 18 UNIT MHz ns 20 30 15 28 18 30 19 28 15 28 25 28 28' 36 20 21 12 20 12 20 15 25 14 25 ns ns ns 2. Maximum clock frequency is tested with all outputs loaded. 3. See load circuits and waveforms on page 3-11. f max '" maximum clock frequancy tpLH '" propagation delay time, low-to-high-Ievel output tpH L '" propagation delay tima, high-to-Iow-Ievel output tpZH '" output enabla time to high level tpZL '" output enable time to low level tpHZ '" output disabla time from high level tpLZ '" output disable time from low level 877 7-474 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S373, SN54S374, SN74S373, SN74S374 OCTAL O-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS schematic of inputs and outputs TYPICAL OF ALL OUTPUTS eQUIVALENT OF EACH INPUT ---------------~~----Vee 50n NOM vee------------------~-------- 2.8 kn NOM INPUT - .....- OUTPUT ....----4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . • . . . . Off-state output voltage Operating free-air temperature range: SN54S' SN74S' Storage temperature range • 7V 5.5 V 5.5 V _55°C to 125°C OoC to 70°C _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. • recommended operating conditions SN74S' SN54S' Supply voltage, Vee MIN NOM MAX MIN 4.5 5 5.5 4.75 NOM MAX 5 5.25 High·level output voltage, VOH 5.5 5.5 High-level output current, IOH -2 -6.5 Width of clock/enable pulse, tw Data setup time, tlU Data hold time, th Operating free-air temperature, T A High 6 6 Low 7.3 7.3 'S373 O.j. O.j. 'S374 5t 10,," 5t 10,," 2t -55 2t 0 'S373 'S374 125 UNIT V V mA ns ns ns 70 DC t"" The arrow Indicates the transition of the clock/enable Input used for reference: t for the low-to-hlgh transition, "" for the high-to-Iow transition. 679 TEXAS INSTRUMENTS INCORPORATED POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265 7-475 TYPES SN54S373, SN54S374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER High-level input voltage VIH V,L V,K Input clamp voltage VOH High-level output voltage TEST CONDITIONSt MIN TYPt MAX UNIT 2 Low-level input voltage I I SN54S' SN74S' Vee = MIN. II = -18 mA VCC= MIN. V,L = 0.8 V. V,H = 2V. VCC= MIN. V,L = 0.8 V. V'H=2V, 10L = 20 mA V'H=2V. 10H 0.8 -1.2 2.4 = MAX VOL Low-level output voltage 10ZH Off-state output current. high-level voltage applied VCC = MAX, 10Zl Off-state output current. low-level voltage applied VCC = MAX. Vo = 0.5 V V'H=2V. VCC = MAX, " Input current at maximum input voltage High-level input current VCC = MAX, V, = 5.5 V V, = 2.7 V VCC = MAX, V, = 0.5 V 3.4 3.1 2.4 Low-level input current Short-circuit output current§ VCC = MAX ICC Supply current VCC = MAX -40 I I 'S373 'S374 V V Vo = 2.4 V "H ',L lOS V V 0.5 V 50 IJA -50 IJA 1 mA 50 -250 -100 IJA 105 IJA mA 160 140 90 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 1All typical values are at Vee = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. switching characteristics, Vee PARAMETER FROM (INPUT) = 5 V, T A = 25°e TO (OUTPUT) TEST CONDITIONS '5373 '5374 MIN TYP MAX MIN TYP MAX 75 100 f max • tpLH tpHL tpLH Clock or tPHl enable tPZH tpZL Output Data tPHZ Control Output tPLZ Control NOTES: Any Q Any Q CL = 15 pF. RL = 280 n, See Notes 2 and 4 Any Q Any Q CL = 5 pF. See Note 3 RL = 280 n. 7 12 7 7 12 12 14 8 11 15 18 6 8 9 12 18 UNIT MHz ns 8 11 15 8 17 15 11 18 5 9 12 7 ns ns ns 2. Maximum clock frequency is tested with all outputs loaded. 4. See load circuits and waveforms on page 3-10. f max ~ maximum clock frequency tpLH '" propagation delay time, low-to·high-Ievel output tpHL '" propagation delay time, high-to-Iow-Ievel output tpZH '" output enable time to high level tpZL '" output enable time to low level tpHZ'" output disable time from high level tpLZ '" output disable time from low level 67! 7-476 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • OALLAS, TEXAS 75265 TYPES SN54LS374, SN54S374, SN74LS374, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS TYPICAL APPLICATION DATA BIDIRECTIDNAL OUTPUT CONTROL 1 B~ DIIIVEII ~ A 1D 10 2Q 2D 30 'LS374 OR 'S374 4D BIDIRECTIONAL DATA BUS 1 10 3D 4Q BIDIRECTIONAL DATA BUS 2 60 80 7D 70 ~ D 80 ) CLOCK 1 CLOCK 2 ( V '-- 10 CK ' - - 2Q '---- 1D t-20 3D 3D 'LS374 OR 'S374 ' - - - 4Q ' - - - riO 80 40 50 r-t--tt--- 80 70 70 80 A 80 L CLOCK 1 H s L r ::HANOELI CLOCK CLOCK 2 OUTPUT CONTROL 2 LF H CLOCK CIRCUIT FOil BUI EXCHANOE EX'ANDABLE 4-WORO.. V.... IT OENERAL REGIITER FILE 'LS374 OR 'S374 • 1/2 SN74LS139 OR SN74S139 o VO 'LS374 OR 'S374 V1 ENABLE SELECT ( A V2 B V3 'LS374 OR 'S374 'LS374 OR 'S374 1/2 SN74LS139 OR SN74S139 ~ SELECT l.S CLOCK 1076 TEXAS INCORPORATED INSTRUMENTS POST O.FFICE BOX 5012 • DALLAS, TEXAS 75222 7-477 TTL MSI TYPES SN54LS375, SN74LS375 4-BIT BISTABLE LATCHES BULLETIN NO. DL-S 7612131, OCTOBER 1976 • Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout logic SN54LS375 ••• J OR W PACKAGE SN74LS375 ••• J OR N PACKAGE (TOP VIEW) FUNCTION TABLE (EACH LATCH) INPUTS OUTPUTS Q 0 G Q L H L H H H H L X L 00 vcc 40 411 10 1il 10 4Q ENABLE 3-4 30 ENABLE 1-2 20 20 3D 00 H = high level, L = low level, X = Irrelevant 00 = the level of a before the high-to-Iow transition of G. functional block diagram (each latch) Dm~ TOOTH'" LATCH -~: ENABLE 20 GNO logic: see function table description The SN54LS375 and SN74LS375 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals has been changed in the SN54LS375 and SN74LS375. These . latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. I nformation present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable goes high. • These circJits are completely compatible with all popular nL or DTL families. All inputs are diodeclamped to minimize transmission-line effects and simplify system design. The SN54LS375 is characterized for operation over the full military temperature range of -55°C to 125°C; SN74LS375 is characterized for operation from oOe to 70°C. schematics of inputs and outputs r-------------, EQUIVALENT OF EACH INPUT vcc I TYPICAL OF ALL OUTPUTS -- Req INPUT ..""' ~~ -- , , OUTPUT r. Data: Req=17k.l1 Enable: Req = 4.2 k.l1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) _...... Input voltage . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS375 SN74LS375 Storage temperature range 7V . . .. 7V -55°C to 125°C . oOe to 70~e -65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. recommended operating conditions, electrical characteristics, and switching characteristics Same as SN54LS75 and SN74LS75, see page 7-39. 1076 7·478 TEXASINCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54376, SN74376 QUADRUPLE J-K FLIP-FLOPS TTL MSI BULLETIN NO. DL·S 7612461, OCTOBER 1976 • Four J-K Flip-Flops in a Single Package ... Can Reduce F F Package Count by 50% • Common Positive-Edge-Triggered Clocks with Hysteresis ... Typically 200 mV • Fully Buffered Outputs • Typical Clock Input Frequency ... 45 MHz SN54376 ••. J OR W PACKAGE SN74376 ••. J OR N PACKAGE (TOP VIEW) 4K 40 30 10 20 3]( 3J CLOCK 2J GND description These quadruple TTL J-K flip-flops incorporate a number of third-generation IC features that can simplify system design and reduce flip-flop package count by as much as 50"10. They feature hysteresis at the clock input, fully buffered outputs, and direct clear capability. The positive-edge-triggered SN54376 and SN74376 are directly compatible with most Series 54/74 MSI registers. CLEAR 1J logic: see function table schematics of inputs and outputs EQUIVALENT OF EACH INPUT The SN 54376 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74376 is characterized for operation from O°C to 70°C. TYPICAL OF ALL OUTPUTS VCC---"--- FUNCTION TABLE (EACH FLIP-FLOP) COMMON INPUTS INPUTS CLEAR CLOCK J • Q OUTPUT Q K L X X X L H t L H 00 H t H H H H t L L L H t H L TOGGLE H L X X 00 I Clear, J, K: Req Clock: Req See explanation of function tables on page 3-8. = 4 kn NOM = 11.6 kn NOM Resistor values shown are nominal and in ohms absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Input voltage . . . . . . . . Operating free-air temperature range: SN54376 SN74376 Storage temperature range ..... 7 V . . . . 5.5 V _55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1:· Voltage values are with respect to network ground terminal. 1076 TEXAS INCORPORATED [NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-479 TYPES SN54376, SN74376 QUADRUPLE J-K FLIP-FLOPS recommended operating conditions SN54376 MIN NOM 4.5 5 Supply voltage, VCC SN74376 MAX MIN NOM 5.5 4.75 5 -SOO High-level output current, 10H 0 Pulse width, tw V IlA 0 30 Clock high 22 Clock low 12 12 Preset or clear low 12 12 J, K inputs Setup time, tsu 5.25 -SOO 16 Low-level output current, 10L Clock frequency Clear inactive state Ot ot lOt Input hold time, th 20t 55 16 mA 30 MHz 22 lOt Operating free-air temperature, T A UNIT MAX ns ns 20t 125 t ~ The arrow indicates the edge of the clock pulse used for reference: t for the rising edge, ~ ns DC 70 0 for the failing edge. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH VOL • MIN TEST CONDITIONSt VIH TYP+ UNIT MAX V 2 High-level output voltage Low-level output voltage VCC = MIN, II = -12 mA VCC = MIN, VIH = 2 V, VIL = O.S V, 10H = -SOOJ.tA VCC = MIN, VIH = 2 V, VIL = O.S V, IOL=16mA 2.4 O.S V -1.5 V V 3.4 0.4 0.2 V II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 IIH High-level input current VCC - MAX, VI - 2.4 V 40 IlA IlL Low-level input current VCC = MAX, VI = 0.4 V -1.6 mA lOS Short-circuit output currentS VCC - MAX ICC Supply current VCC = MAX -30 52 mA -S5 mA 74 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25 e. §Not more than one output should be shorted at a time. D switching characteristics, Vee = 5 V, T A = 25°e TEST CONDITIONS PARAMETER f max Maximum clock frequency tpHL Propagation delay time, high-to-Iow-Ievel output from clear tPLH Propagation delay time, low-to-high-Ievel output from clock tpHL Propagation delay time, high-to-Iow-Ievel output from clock CL=15pF, RL = 400n, See Note 2 MIN TYP 30 45 MAX UNIT MHz 17 30 22 35 ns 24 35 ns ns NOTE 2: Load circuit and voltage waveforms are shown on page 3-1 O. 1076 7·480 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE BULLETIN NO. DL-S 7612474, OCTOBER 1976 • 'LS377 and 'LS378 Contain Eight and Six Flip-Flops, Respectively, with SingleRail Outputs • 'LS379 Contains Four Flip-Flops with Double-Rail Outputs • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators SN54LS377 .•• J PACKAGE SN74LS377 ••• J OR N PACKAGE (TOP VIEW) description SO so 70 70 60 60 50 50 ENABLE 10 10 20 20 30 30 40 40 CLOCK G These monolithic, positive·edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. logic: see function table SN54LS378 •.. J OR W PACKAGE SN74LS378 .•. J OR N PACKAGE (TOP VIEW) Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outpuf. The circuits are designed to prevent false clocking by transitions at the G input. 10 ENABLE 20 20 3D 30 • GNO G These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop. logic: see function table SN54LS379 ••. J OR W PACKAGE SN74LS379 ... J OR N PACKAGE (TOP VIEW) Vce 40 4'iJ 40 3D 30 30 CLOCK FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OUTPUTS G CLOCK DATA 0 0 H X X 00 00 L t t H H L L L L H X L X 00 00 See explanation of function tables on page 3-8. logic: see function table 076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-481 TYPES SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPEFLIP-FLOPS WITH ENABLE ~unctional block diagram D CLOCK----I D CK a Q a Q TO 7 5 3 OTHER ('LS377) ('LS378) ('LS379) FLIP-FLOPS ENABLE G --"""--..II ('LS379 ONLY) schematics of inputs and outputs EQUIVALENT OF DATA INPUT EQUIVALENT OF CLOCK OR ENABLE INPUT TYPICAL OF ALL OUTPUTS ------1>---vcc V C C - - - - -__ 25 kn. VCC----20 kn. NOM I NPUT~-_:fIIt_-... NOM I NPUT-...,.....---' - - - . . . - OUTPUT • absolute maximum rating over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) _ _ _ , _ Input voltage _ _ . . . . . _ . _ . _ . Operating free-air temperature range: SN54LS' SN74LS' Storage temperature range . . . . . 7V . _ . _ .7V . -55°C to 125°C aOe to 7aoe _ -65°C to 15aoe NOTE 1: Voltage values are with respect to network ground terminal. 1C 7-482 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • OAL.L.AS. TEXAS 75222 TYPES SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE recommended operating conditions SN54LS' Supply voltage, VCC High-level output current, 10H Low-level output current, fOL SN74LS' MIN NOM MAX MIN 4.5 5 5.5 4.75 -400 4 0 20 Clock frequency, fclock Width of clock or clear pulse, tw Data input Enable active-state Enable inactive-state Setup time, tsu 20t 25t 5.25 -400 8 0 20 30 125 UNIT V J.lA mA MHz ns ns 5t -55 Operating free-air temperature, T A 5 20t 25t 10t 10t 5t Data and enable Hold time, th 30 NOM MAX 70 0 ns °c t The arrow indicates that the rising edge of the clock pu Ise is used for reference. electrical. characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II IIH IlL lOS Low-level input current Short-circuit output current§ lee Vee = MIN Vee = MIN, VIL = VIL max, Vee = MIN, 0.7 -1.5 II = -18mA VIH = 2 V, 10H = -400p.A VIH=2V, Supply current 3.5 0.8 -1.5 2.7 0.25 VI =7 V Vee = MAX, VI=2.7V Vee = MAX, Vee - MAX VI = 0.4 V 0.4 0.5 V 0.1 mA 20 -0.4 -100 J.lA mA mA 13 28 22 mA mA 9 15 mA 0.35 0.1 20 -0.4 -100 -20 -20 See Note 2 ,'LS377 I'LS378 17 13 I'LS379 9 28 22 15 V V V 3.5 0.25 0.4 IIOL =8 mA Vee = MAX, Vee = MAX, 2.5 IIOL =4 mA VIL = VIL max Input cu rrent at maximum input voltage High-level input current SN54LS' SN74LS' UNIT MIN TYp:j: MAX MIN TYP:j: MAX V 2 2 TEST CONDITIONSt PARAMETER 17 t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j: All typical values are at Vee = 5 V, T A = 25°e. § Note more than one input should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 2: With all outputs open and ground applied to all data and enable inputs, lee is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, Vee = 5 V, TA = 25°e TEST CONDITIONS MIN PARAMETER f max Maximum clock frequency eL = 15 pF, tpLH Propagation delay time, low-to-high-Ievel output from clock RL = 2 k.l1 See Note 3 tPHL Propagation delay time, high-to-Iow-Ievel output from clock 30 TYP MAX UNIT 40 17 27 MHz ns 18 27 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-483 TTL MSI TYPES SN54S381, SN74S381 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR BULLETIN NO. DL-S 7712124, MARCH 1974-REVISED AUGUST 1977 SN54S381 ••• J PACKAGE SN74S3B1 •.• J OR N PACKAGE PIN DESIGNATIONS (TOP VIEW) DESIGNATION PIN NOS. A3, A2, Al, AO 17,19,1,3 B3, B2, Bl, BO S2, Sl, SO 16,18,2,4 7,6,5 FUNCTION WORD A INPUTS WORD B INPUTS FUNCTION·SELECT INPUTS CARRY INPUT FOR Cn 15 ADDITION, INVERTED CARRY INPUT FOR F2 SUBTRACTION F3, F2, Fl, FO INVERTED CARRY 14 G 13 VCC GND 20 SUPPLY VOLTAGE 10 GROUND PROPAGATE OUTPUT INVERTED CARRY GENERATE OUTPUT • A Fully Parallel 4-Bit ALU in 20-Pin Package for O.300-lnch Row Spacing • Ideally Suited for High-Density Economical Processors • Parallel Inputs and Outputs and Full Look-Ahead Provide System Flexibility • • 12,11,9,8 FUNCTION OUTPUTS P • ~--------~v~--------~ INPUTS logic: see function table FUNCTION TABLE SELECTION Arithmetic and Logic Operations Selected Specifically to Simplify System Implementation: A Minus B B Minus A A Plus B and Five Other Functions Schottky-Clamped for High Performance 16-Bit Add Time ... 26 ns Typ Using Look-Ahead 32-Bit Add Time ... 34 ns Typ Using Look-Ahead ARITHMETIC/LOGIC S2 S1 SO L L L OPERATION L L H BMINUSA L H L A MINUSB L H H A PLUS B H L L AGB CLEAR H L H A + B H H L AB H H H = high level. H PRESET L = low level description The 'S381 is a Schottky TTL arithmetic logic unit (ALU)/function generator that performs eight binary arithmetic/ logic operations on two 4-bit words as shown in the function table. These operations are selected by the three function-select lines (SO, S1, S2). A full carry look-ahead circuit is provided for fast, simultaneous carry generation by means of two cascade outputs (p and G) for the four bits in the package. The method of cascading SN54182/ SN74182 or SN54S182/SN74S182 look-ahead carry generators with these ALU's to provide multi-level full carry look-ahead is illustrated under typical applications data for the '182 and 'S182. The typical addition times shown above illustrate the short delay time required for addition of longer words when full look-ahead is employed. The exclusive-OR, AND, or OR function of two Boolean variables is provided without the use of external circuitry. Also, the outputs can be either cleared (low) or preset (high) as desired. 877 7-484 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222' TYPES SN54S381, SN74S381 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR REVISED DECEMBER 19BO functional block diagram and schematics of inputs and outputs EQUIVALENT OF EACH INPUT Vec---.....- - INPUT = 1 kn Any A or B: Req cn: Req = 800 Any S: Req = 6 kn n TYPICAL OF ALL OUTPUTS Vce ""'--~""'--OUTPUT • 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-485 TYPES SN54S381, SN74S381 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see !\Jote 1) Input voltage . . . . . . . . . . . . . . •.•••• Interemitter voltage (see Note 2) Operating free-air temperature range: SN54S381 SN74S381 Storage free-air temperature range NOTES: . 7V 5.5V 5.5 V _55°C to 125°C oOe to 70°C _65°C to 150°C 1. Voltsoe values, except interemltter voltage, are with respect to network ground terminal. 2. This Is the voltage between two emitters of a multiple-emittef' transistor. For this circuit, this rating applies to each A input in conjunction with its respective B input; for example AO with BO, etc. recommended operating conditions SN74S381 SN54S381 MIN 4.5 Supply voltage, Vee High-level output current, 10H Low·level output current, 10L Operating free·air temperature', T A NOM 5 -55 MAX 5.5 -1 20 125 NOM 5 MIN 4.75 UNIT MAX 5.25 -1 20 V mA mA °e 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL High·level input voltage Low·level input voltage VIK Input clamp voltage VOH TEST eONDITIONSt MIN TYP:j: SN54S381 SN74S381 High·level output voltage VOL Low·level output voltage II Input current at maximum input voltage IIH High·level input current Vee= MIN, II = -18 mA Vee = MIN, VIH = 2 V, 2.4 10H =-1 mA 2.7 VIL = 0.8 V, Vee= MIN, VIL = 0.8 V, Vee - MAX, VIH = 2 V, 10L =20mA VI- 5.5 V • en All others Vee = MAX, VI = 2.7 V lOS Icc en Ali others V V -1.2 V V 0.5 1 V mA 50 250 IJA 200 -2 Any S input Low-level input current UNIT 0.8 3.4 3.4 Any S input IlL MAX 2 Vee = MAX, -8 VI = 0.5 V mA -6 Short-circuit output current§ Vee = MAX Supply current Vee = MAX -40 105 -100 mA 160 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:Aii typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER1J tPLH tpHL tpLH tPHL tpLH FROM (INPUT) tPLH tpHL TEST CONDITIONS Any F en Any A or B Any A or B tpHL tPLH tpHL TO (OUTPUT) AiorBi Any S G P eL=15pF, See Note 3 Fi Any RL = 280 n, MIN TYP MAX UNIT 10 17 10 12 20 12 11 20 18 11 18 '16 18 27 25 18 30 18 30 17 ns ns ns ns ns 1JtPLH == propagation delay time, iow-to-high·level output tpHL == propagation delay time, high·to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3·10. 107( 7-486 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL MSI TYPES SN54LS386, SN74LS386 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES BULLETIN NO. DL-S 7612118, MARCH 1974-REVISED OCTOBER 1976 SN54LS386 ... J OR W PACKAGE SN74LS386 •.• J OR N PACKAGE (TOP VIEW) • Vce 48 4A 4Y 3Y 38 3A 1A 18 1Y 2Y 2A 28 GND Electrically Identical to SN54 LS86/SN7 4 LS86 • Mechanically Identical to SN54 L86/SN7 4 L86 • Total Average Propagation Delay Times ... 10 ns • Typical Total Power Dissipation ... 30.5 mW positive logic: Y = A 0 B = AS + AS FUNCTION TABLE (EACH GATE) INPUTS OUTPUT A B L L L L H H H L H H H L • H = high level L = low level schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS ----------~.-----Vcc 250 vcc------~.------ n NOM 12.5 kn NOM I NPUT--~:-MII--4t--. . .L . . - - -. . . .-----OUTPUT 1076· TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-487 I TYPES SN54LS386, SN74LS386 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES REVISED OCTOBER 1976 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ..... . Input voltage . . . . . " ..... . Operating free-air temperature range: SN54LS386 SN74LS386 Storage temperature range 7V 7V -55°e to 125°e oOe to 700e -65°e to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS386 MIN Supply voltage, Vee 4.5 NOM MIN NOM 5.5 4.75 5 5 High-level output current, 10H SN74LS386 MAX -400 Low-level output current, 10L MAX 5.25 V -400 /loA 8 mA De 4 Operating free-air temperature, T A -55 125 UNIT 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low-level input voltage VIK I nput clamp voltage MIN TYP:!: SN74 LS386 MAX 2 MIN TYP:!: Vee - MIN, II =-18mA Vee= MIN, VIH=2V, VIL - VIL max, 10H Vee= MIN. = -400/loA 3.4 2.7 0.25 10L = 4 mA 0.4 0.8 V -1.5 V 3.4 V 0.25 0.4 0.35 0.5 VIH=2V, VOL Low-level output voltage UNIT V -1.5 2.5 MAX 2 0.7 VOH High-level output voltage • SN54LS386 TEST CONDITIONSt V 10L = 8 mA VIL = VIL max II Input current at maximum input voltage Vee = MAX, VI = 7V 0.2 0.2 IIH High-level input current Vee = MAX, VI = 2.7 V 40 40 /loA IlL Low-level input current Vee = MAX, VI =0.4V -0.8 -0.8 mA lOS Short-circuit output current§ Vee = MAX -42 mA lee Supply current Vee = MAX, 10 mA -6 See Note 2 -40 , -5 10 6.1 6.1 mA tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. D :tAli typical values are at V CC = 5 V, T A = 25 C. §Not more than one output should be shorted at a time. NOTE 2: ICC is measured with the Inputs grounded and the outputs open. switching characteristics, Vee PARAMETER~ tPLH = 5 V, TA = 25°e FROM TEST CONDITIONS !INPUT) AorB Other input low eL=15pF, tpHL tpLH RL AorB = 2 kil, Other input high See Note 3 tpHL MIN TYP MAX UNIT 12 23 10 17 20 30 13 22 ns ns ~tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, hlgh-to-Iow-Ievel output NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. 1071 7-488 TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TTL TYPES SN54390, SN54LS390" SN54393, SN54LS393, SN74390, SN74LS390, SN74393, SN74LS393 DUAL 4-BIT DECADE . AND BINARY COUNTERS . EA 1976 SN54390. SN54LS390 ••• JaR W PACKAGE • Dual Versions of the Popular '90A, 'LS90 and '93A, 'LS93 • '390, 'LS390 •• .Individual Clocks for A and B Flip-Flops Provide Dual +2 and +5 Counters SN74390, SN74LS390 • _ • J OR N PACKAGE (TOP VIEWI • '393, 'LS393 ••.Dual 4-Bit Binary Counter with Individual Clocks • All Have Direct Clear for Each 4-Bit Counter • Dual4-Bit Versions Can Significantly Improve System Densities by Reducing Counter Package Count by 50% • Typical Maximum Count Frequency ••• 35 MHz • Buffered Outputs Reduce Possibility of Collector Commutation OUTPUTS 2A 1A CLE~R O~~:UT CL~AR OJ~t"UT 1B 2B ~ ~ GND OUTPUTS positive logic: High input to clear resets all four outputs low description SN54393, SN54LS393 _ • _J OR W PACKAGE Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement. two individual four-bit counters in a single package. The '390 and 'LS390 incorporate dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-l00. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final SN74393, SN54LS393 ___ J OR N PACKAGE (TOPVIEWI OUTPUTS • I output stage. The '393 and 'LS393 each comprise two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The '390, 'LS390, '393, and 'LS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals. ~------~v~------~ Series 54 and Series 54LS circuits are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and Series 74LS circuits are characterized for operation from O°C to 70°C. OUTPUTS positive logic: High input to clear resets all four outputs low 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 1-489 TYPES SN54390, SN54LS390, SN54393, SN54LS393, SN74390, SN74LS390, SN74393, SN74LS393 DUAL 4-BIT DECADE AND BINARY COUNTERS FUNCTION TABLES '390, 'LS390 BCD COUNT SEQUENCE (EACH COUNTER) (See Note A) '390, 'LS390 BI-QUINARY (5-2) (EACH COUNTER) (See Note B) OUTPUT COUNT COUNT QD QC QB QA L L L L 0 '393, 'LS393 COUNT SEQUENCE (EACH COUNTER) OUTPUT OUTPUT COUNT QA QD QC QB QD QC QB QA L L L L 0 L L L L 1 L L L H 1 L L L H 1 L L L 2 L L H L 2 L L H L 2 L H L 3 L L H H 3 L L H H 3 H H 4 L H L L 4 L H L L 4 L L L L H L L 5 L H L H 5 H L L L 5 H L H H L 6 H L L H 6 7 L H H H H L H L 7 L H 8 H L L L 7 8 L H H H 6 L L H L H H 8 H L L L 9 H L L H 9 H H L L 9 H H L H H 10 L L 11 H L H H 12 H H L L 13 H H L H L H NOTES: 0 A_ Output QA is connected to Input B for BCD count_ B. Output QD is connected to Input A for bi-quinary count. C. H = high level, L = low level. H 14 H H H 15 H H H H L H L functional block diagrams • (1.151 INPUT A ---'-------------d> (3.111 OUTPUT INPUT A ....:..:.(1.:....:1.::;:31_ _-d> (5. 111 INPUT B °A OUTPUT °B (4.121 -.:.---'--+------...... .,-...... (6. 101 OUTPUT Oc OUTPUT 00 (2. CLEAR 141 INPUT '390, 'LS390 '393, 'LS393 1076 7·490 TEXAS INSTRUMENTS INCORPORATED POST OFFIC~ BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54390, SN54LS390, SN54393, SN54LS393, SN74390, SN74LS390, SN74393, SN74LS393 DUAL 4-BIT DECADE AND BINARY COUNTERS schematics of inputs and outputs '390, '393 VCC3-- EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS Req INPUT -- INPUT Req NOM A ('390)...... 3 kn B ('390) ...... 1.5 kn A ('393)...... 3 kn Any clear. . . . .. 8 kn 'LS390, 'LS393 EQUIVALENT OF EACH AAND B INPUT EQUIVALENT OF EACH CLEAR INPUT VCC1 3-Req VCC1 185 kn-NOM INPUT INPUT -- INPUT Req NOM TYPICAL OF ALL OUTPUTS -- II A ('LS3901. ........ 4.3 kn B ('LS390) ......... 2.7 kn A ('LS3931. ........ 4.3 kn 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-491 ~PES SN54390, SN54393, SN74390, SN74393 DUAL 4-BIT DECADE AND BINARY COUNTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 7V 5.5 V -55°e to 125°e oOe to 700e 0 -65°e to 150 e Supply voltage, Vee (see Note 1) . . . . . . . . . Input voltage . . . . . . . . . . . . . . . . . Operating free-air temperature range: SN54390, SN54393 SN74390, SN74393 Storage temperature range NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54390 SN74390 SN54393 SN74393 MIN 4.5 Supply voltage, VCC NOM 5 MAX MIN NOM 5.5 4.75 5 -800 High-level output current, 10H Low-level output current, 10L 16 A input Count frequency, fcount B input Pulse width, tw 0 25 0 20 16 0 20 20 B input high or low 25 25 Clear high 20 20 25t V p.A 25 20 Clear" inactive-state setup time, tsu 5.25 -800 0 A input high or low 125 rnA MHz ns 25t -55 Operating free-air temperature, T A UNIT MAX ns 70 0 °c t The arrow indicates that the falling edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER • VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage TYP+ maximum input voltage High-level input current Low-level input current TYP+ VCC = MIN, 11=-12mA VCC = MIN, VIH=2V, VIL = 0.8 V, 10H = -800 p.A -~ Input B ~ 2.4 3.4 0.8 V -1.5 V 3.4 V VCC = MIN, VIH=2V, VIL = 0.8 V, 10L = 16 mAl1 VCC = MAX, VI = 5.5V 1 1 40 40 VCC = MAX, VI=2.4V 80 80 0.2 0.2 0.4 UNIT V -1.5 2.4 MAX 2 0.4 V rnA p.A 120 Clear IlL MIN 0.8 Clear IIH '393 MAX 2 Input current at II '390 MIN VCC = MAX, VI = 0.4 V ~ -1 -1 -3.2 -3.2 rnA -4.8 ISN54' -20 -57 -20 -57 ISN74' -18 -57 -18 -57 lOS Short-circuit output current§ VCC = MAX ICC Supply current VCC = MAX, See Note 2 42 69 38 64 rnA rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, T A = 25°e. 11 The QA outputs of the '390 are tested at IOL = 16 mA plus the limit value for II L for the B input. This permits driving the B input while maintaining full fan-out capability. § Not more than one output should be shorted at a time. NOTE 2: lee is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs grounded. 1076 7492 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54390, SN54393, SN74390, SN74393 DUAL 4-BIT DECADE AND BINARY COUNTERS switching characteristics, Vee PARAMETER~ f max tpLH = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) A S A tpHL tpLH tpLH tpLH tPLH tpHL tpHL QA 25 35 QS 20 30 MAX MIN TYP 25 35 MAX 12 20 13 20 13 20 20 37 60 40 60 QD of '393 RL=400n, 39 60 40 60 See Note 3 13 21 and 14 21 24 39 26 39 13 21 QS Figure 1 QC S aD Clear Any 14 21 24 39 UNIT MHz 12 CL=15pF, S tpHL TYP QC of '390 S tpHL MIN QA A tpHL '393 '390 TEST CONDITIONS ns ns ns ns ns 24 39 ns ~fmax == maximum count frequency tpLH == propagation delay time, low-to-high-Ievel tpH L == propagation delay time, high-to-Iow-Ievel output output NOTE 3: Load circuit is shown on page 3-10. PARAMETER MEASUREMENT INFORMATION CLEAR \~~ fsv INPUT I' ~ ___ I' I I I I ~ 'I r---rOUTPUTQA~I'l. I I : • I tPHL ~---- 3V 1 1.5V .•s,v 1.SV !.---.t-tPLH-Measure I at tn+1 I 1.---.1- tPHL-Measure i - -II 1 r-----r- r-----t-tPHL - - ~I l ----~I----~\~--------------~frl----~-------', - I OUTPUTQB l-l.SV - - - II I tPLH-Measure at tn+2 I i : ____-+~----~\_------------~IS:r-----I~--.:-1 +1.5 V tPLH-Measureattn+4 I r f1.5V \4---.t-tPHL II ~: ~~1._5_V OUTPUT QD__________ \ r----1- ________________f f-f II VOL tpHL -Measure at tn+4 -VOH ~1.5V ~VOL ~}tPHL-Measureattn+s -----:I~""'\-I--voH I I I I '\::V I VOL ~I tPLH-Measure at tn+S ~ tPHL-Measure at tn+l0 for '390 ifr---------:jJrJf-______i_I____~ __"\\:1VOH ortn+16 for '393 --J ___ I I (f'I- I 1-!1} -"\1 I r~----VOH I ~ f1.5V htPHL OUTPUTQC I l\lo5V ov I I attn+2 ~rf" 1 SV . • loS V I t \1.5 V ov tw(clock) I ~.'1 ~:'Y '3~~~ H I I+- tsu IN~T: INPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3V r-__________---I!1.5 V 1.5 V SS' VOL VOLTAGE WAVEFORMS NOTE A: Input pulses are supplied by a generator having the following characteristics tr';; 5 ns, tf .;; 5 ns, PR R Zout'" 50 ohms. =1 MHz, duty cycle = 50%, FIGURE 1 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-493 TYPES SN54LS390, SN54LS393, SN74LS390, SN74LS393 DUAL 4-BIT DECADE AND BINARY COUNTERS REVISED DECEMBER 19BO absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) Clear input voltage . . . . . . Any A or B clock input voltage Operating free-air temperature range: SN54LS390, SN54LS393 SN74LS390,SN74LS393 Storage temperature range . 7V . 7V 5.5V _55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS390 SN54LS393 MIN Supply voltage, VCC NOM 4.5 MAX MIN NOM 5.5 4.75 5 5 High-level output current, 10H SN74LS390 SN74LS393 5.25 -400 Low-level output current, 10L Count frequency, fcount B input Pulse width, tw 0 25 JlA 8 mA 0 12.5 0 25 0 12.5 A input high or low 20 20 B input high or low 40 40 Clear high 20 20 25~ elear inactive·state setup time, tsu Operating free·air temperature, T A 125 MHz ns 25~ -55 V -400 4 A input UNIT MAX ns 0 70 °e ~ The arrow indicates that the falling edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) • High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage Input current at maximum input voltage MIN TYP:j: MAX MIN TYP:j: 2 VIH II Vee= MIN, II = -18 mA Vee = MIN, VIH=2V, 2.5 VIL = VILmax, VOH = -400 JlA Vee= MIN, VIH=2V, ~ ~ 10L =4 mA~ VI-7 V Vec= MAX VI = 5.5 V Input B IlL High-level input current Low-level input current t--- ~ Input B ~ ~ Vec = MAX, Vec= MAX, VI = 2.7 V VI = 0.4 V Input B lOS lee Short·circuit output current§ Supply current -20 VCC = MAX V 0.8 V -1.5 -1.5 V 3.4 0.25 UNIT 0.7 2.7 0.4 10L =8 mA~1 VIL = 0.8 V, MAX 2 Clear IIH SN74LS' SN54LS' TEST CONDITIONSt PARAMETER 3.4 V 0.25 0.4 0.35 0.5 0.1 0.1 0.2 0.2 0.4 0.4 20 20 100 100 200 200 -0.4 -0.4 -1.6 -1.6 -2.4 -2.4 -100 -20 -100 Vee - MAX, 'LS390 15 26 15 26 See Note 2 'LS393 15 26 15 26 V mA JlA mA mA mA t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operatin9 conditions. :j:AII typical values are at VCC = 5 V, T A = 25°C. ~The QA outputs of the 'LS390 are tested at IOL = MAX plus the limit value for IlL for the clock B input. This permits driving the clock B input while maintaining full fan-out capability. § Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second. NOTE 2: Icc is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs grounded. 7·494 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 1280 TYPES SN54LS390. SN54LS393. SN14LS390. SN14LS393 DUAL 4-BIT DECADE AND BINARY COUNTERS REVISED DECEMBER 1980 switching characteristics, Vee PARAMETER~ = 5 V, TA = 25°e FROM TO (INPUT) (OUTPUT) f max tPLH tpLH QA 25 35 QB 12.5 20 A tpHL tpLH tpHL tPLH QA 'LS393 MAX MIN TVP 25 35 MAX 20 12 20 13 20 13 20 QC of 'LS390 CL;15pF, 37 60 40 60 RL = 2 kil, 39 60 40 60 See Note 4 and Figure 2 13 21 14 21 24 39 26 39 13 21 14 21 24 39 B QB B QC B QD Clear Any UNIT MHz 12 QD of 'LS393 tpHL tpHL TVP B tPHL tPLH MIN A A tpHL 'LS390 TEST CONDITIONS ns ns ns ns ns 24 39 ns ~fmax == maximum count frequency tpLH == propagation delay time, low·to-high-Ievel tpH L == propagation delay time, high-to-Iow-Ievel output output NOTE 4: Load circuit is shown on page 3-11. PARAMETER MEASUREMENT INFORMATION .f3V \~~~: ~:;:----~,-----------~!--------- I I+- tsu 1 1- -I tpHL i1 \1.3 ---=-"'""" B INPUT 1 V 1.3 V I - - - i V-U t 1 3V . r---tl 11.3 --'\ I H ~1.3V : \ I4---.,-tPHL I ~} tPLH-Measureat tn+4 I 1 I 1 I_ If f·3V I I" I VOH VOL r---t-tPHL -Measure at tn+4 -VOH \,:VVOL ,e IS I V ~tPLH-Measureattn+8 1 \ f---I"\- - - : ~ I _ _ _ """""\: -\-1.3V r ff-I- 1 \1.3V I tpLH-Measure at tn+2 htPHL I I \1.3V OV I I - - --"'\1 OUTPUTOC 1.3V 1 I !.---.t-tPLH-Measure ~tpLH-Measure I I att n+11 attn+2 ~tPHL OUTPUTOB twlclock) ~---- 3V 1 1.3V 1.3V ~ 'L~~~ -, I IN~UT: OUTPUT OA I. --t if !1.3V I I , ~}tPHL-Measureattn+8 \:v I-I--VOH I I 1- I I ~} VOL tpHL-Measureattn+10for'LS390 VOH or tn+16 for 'LS393 ~1.3V \:..VOL VOLTAGE WAVEFORMS NOTE A: Input pulses are supplied by a generator having the following characteristics tr';; 15 ns, tf .;; 6 ns, PR R ; 1 MHz, duty cycle; 50%, Zout"" 50 ohms. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-495 TTL MSI TYPES SN54LS395A, SN74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS BULLETIN NO. DL-S 7712114, OCTOBER 1976-REVISED AUGUST 1977 SN54LS395A .•• J OR W PACKAGE SN74LS395A .•• J OR N PACKAGE (TOP VIEW) • Three-State, 4 Bit, Cascadable, Parallel-In, Parallel-Out Registers • 'LS395A Offers Three Times the Sink-Current Capability of 'LS395 • Low Power Dissipation ... 75 mW Typical (Enabled) • Applications: N-Bit Serial-To-Parallel Converter N-Bit Parallel-To-Serial Converter N-Bit Storage Register . OUTPUTS description These 4·bit registers feature parallel inputs, parallel outputs, and clock, serial, load/shift, output control and direct overriding clear inputs. . PARALLEL INPUTS Shifting is accomplished when the load/shift control is low. Parallel loading is accomplished by applying logic: see functional table the four bits of data and taking the load/shift control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition of the clock input. During parallel loading, the entry of serial data is inhibited. When the output control is low, the normal logic levels of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at the output control input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation of the registers is not affected. During the high-impedance mode, the output at QD' is still available for cascading. FUNCTION TABLE II 3·STATE OUTPUTS INPUTS CLEAR LOAD/SHIFT CONTROL CLOCK SERIAL A B C 0 X °A OB Oc OD L L L L L X X X X X X H H H X X X X X OAO 0BO Oco 0DO a c H H ~ X a b c H L H X X X X X 0AO 0BO Oco ODO H L ~ H X X X X H H L ~ l.- X X X L X d CASCADE OUTPUT PARALLEL b d 0An 0Bn °Cn 0An 0Bn 0Cn 00' L °DO d °DO °Cn °Cn When the output control is high, the 3·state outputs are disabled to the high·impedance state; however, sequential operation of the registers and the output at aD' are not affected. See explanation of function tables on page 3-8. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) ...... . Input voltage . . . . . . . . . . . . . . . Operating free-air temperature range: SN54LS395A SN74LS395A Storage temperature range 7V 7V _55°C to 125°C oOe to 70°C _65°C to 150°C NOTE1: Voltage values are with respect to network ground terminal. 877 7·496 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS395A, SN74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS REVISED DECEMBER 1980 recommended operating conditions SN54LS395A Supply voltage, VCC NOM MAX MIN NOM 4.5 5 5.5 4.75 5 QO 5.25 V mA -400 -400 IJA 12 24 mA 4 QO Clock frequency, fclock 0 Width of clock pulse, tw(c/ock) Setup time, high-level or low·level data, tsu 30 0 16 16 Load/Shift input 40 40 All other inputs 20 20 10 10 Hold time, high·level or low·level data, th Operating free-air temperature, T A UNIT -2.6 QA, QB, Cle, QO Low·level output current, 10L MAX -1 QA,QB,Cle,Qo High-level output current, IOH SN74LS395A MIN -55 125 8 mA 30 MHz ns ns ns 0 70 °c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage VOH High·level output voltage 10ZH 10ZL Low·level output voltage VCC = MIN, II VCC = MIN, VIH=2V, VIL = VIL max, IOH = MAX VIL = VIL max, QO QC,QO IOL = 24 mA VCC = MAX, VIH=2V, high·level voltage applied Va = 2.7 V Off-state output current, VCC = MAX, low-level voltage applied VO=O.4V 2.4 MIN TYP+ MAX UNIT V 0.7 0.8 V -1.5 -1.5 V 3.4 2.4 V 3.1 Cle,Qo IOL -12 mA Off-state output current, VCC = MAX, QA,OB, QA,QB, QO maximum input voltage MAX 2 11=-18mA VIH = 2 V Input current at TYP:j: 2 VCC = MIN, VOL SN74LS395A SN54LS395A MIN 2.5 0.25 IOL -4 mA 2.7 3.4 0.25 0.4 0.4 IOL = 8 mA QA,QB, V 3.4 0.25 0.4 0.35 0.5 0.25 0.4 0.35 0.5 V V 20 20 IJA -20 -20 IJA 0.1 0.1 mA Cle, QO VIH=2V, QA,OB, Cle, QO VI = 7V IIH High·level input current VCC = MAX, VI = 2.7 V 20 20 fJ.A IlL Low·level input current VCC = MAX, VI =O.4V -0.4 -0.4 mA lOS Short·circuit output current§ VCC = MAX OA,OB. QO ICC Supply current Vce = MAX, -30 -130 -30 -130 mA -100 -20 -100 mA Cle, QO See Note 2 -20 Condition A 22 34 22 34 Condition B 21 31 21 31 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second. NOTE 2: ICC is measured with the outputs open, the serial input and mode control at4.5 V, and the data inputs grounded under the following conditions: A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input. B. Output control and clock input grounded. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7-497 TYPES SN54LS395A, SN74LS395A 4-BIT CASCAnABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS REVISED AUGUST 1977 switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS f max Maximum clock frequency tpHL Propagation delay time. high-to-Iow-Ievel output from clear tPLH Propagation delay time. !ow-to-high-Ievel output tpHL Propagation delay time. high-to-Iow-Ievel output tpZH Output enable time to high level MIN See Note 3. 0A. 0B. TYP MAX 45 30 Dc. 0D outputs: RL = 667 n. CL = 45 pF 0D' output: RL = 2 kn. CL = 15 pF UNIT MHz 22 35 ns 15 30 ns 20 30 ns 15 25 ns tpZL Output enable time to low level 17 25 ns tpHZ Output disable time from high level CL=5pF. 11 17 ns tpLZ Output disable time from low level See Note 3 12 20 ns NOTE 3: Load circuit and voltage waveforms are shown on page 3-11. functional block diagram DATA INPUTS B A o C (4) (3) (5) (6) CLEAR OUTPUT CONTROL (14) QB II 3-STATE (13) Oc ~UTPUTS (12) QD (11) , QD' CASCADE OUTPUT schematics of inputs and outputs EQUIVALENT OF SERIAL AND DATA INPUTS o EOUIVALENT OF OTHER INPUTS Vee --..._-vee 20 k I NPUT-..........._ ........ INPUT- Serial: Req = 30 kn NOM A. B. C. D: Req = 20 kn NOM n TYPICAL OF 0A. OS. 0C. 0D OUTPUTS ----....--vee TYPICAL OF 0D' OUTPUTS ------vee NOM -OUTPUT OUTPUT 877 7-498 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS. TEXAS 75222 TYPES SN54LS398. SN54LS399 SN74LS398. SN74LS399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE TTL MSI BULLETIN NO. DL-5 7712465, OCTOBER 1976-REVISED AUGUST 1977 • Double-Rail Outputs on 'LS398 SN54LS39B ••• J OR W PACKAGE SN74LS39B .•. J OR N PACKAGE (TOP VIEW) • Single-Rail Outputs on 'LS399 • 'LS398 is Similar to 'LS298, Which Has Inverted Clock • Selects One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock • Applications: Dual Source for Operands and Constants in Arithmetic Processor; Can Release Processor Register Files for Acquiring New Data Implement Separate Registers Capable of Parallel Exchange of Contents Yet Retain External Load Capability logic: see function table Universal Type Register for Implementing Various Shift Patterns; Even Has Compound Left-Right Capabilities SN54LS399 •.• J OR W PACKAGE SN74LS399 ••• J OR N PACKAGE (TOP VIEW) 00 01 02 C2 Cl 0c A2 B2 BlOB CLOCK description These monolithic quadruple two-input multiplexers with storage provide essentially the equivalent functional capabilities of two separate MSI functions SN54LS175/ (SN54LS157/SN74LS157 and SN74LS175) in a single 16-pin or 20-pin package. II When the word-select input is low, word 1 (A 1, 81, C1, D1) is applied to the flip-flops. A high input to word select will cause the selection of word 2 (A2, 82, C2, D2). The selected word is clocked to the output terminals on the positive-going edge of the clock pulse. GNO I logic: see function table Typical power dissipation is 37 milliwatts. SN54LS398 and SN54LS399 are characterized for operation over the full military range of -55°C to 125°C, SN74LS398 and SN74LS399 are characterize·d for operation from O°C to 70°C. FUNCTION TABLE INPUTS WORD OUTPUTS CLOCK aA aB Qc al bl cl dl H t t a2 b2 c2 d2 X L GAO GBO Geo GDO SELECT L aD See explanation of function tables on page 3-8. 877 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-499 TYPES SN54LS398, SN54LS399, SN74LS398, SN74LS399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE functional block diagram A1--------/-"'" WORD SELECT A2---+--+-+-~~ B1-----l-ir-l'-"'" B2-----~f-l._,/ C1-----+-+-,-~ C2-----~~~_,/ *OC aD * 0'0 CLOCK----------~ I ~~----~ I - .... Dynamic input activated by a transition from a high level to a low level I * .... 'LS398 Only schematics of inputs and outputs EQUIVALENT OF EACH DATA INPUT EQUIVALENT OF OTHER INPUTS Vcc---+-_ _ TYPICAL OF ALL OUTPUTS - - - - - ...... VCC VCC--.....- Req 30kn NOM INPUT -.-,.........- - . INPUT.....-:........- ........ OUTPUT Clock: Req = 17 kn NOM Word select: Req = 25 kn NOM 1076 7·500 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS398, SN54LS399, SN74LS398, SN74LS399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE REVISED JANUARY 1981 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. Vee (see Note 1) . . . . . Input voltage . . . . . . . . . . . . . Operating free·air temperature range: SN54LS' SN74LS' Storage temperature range ...•. 7 V . .••. 7 V _55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS' Supply voltage, Vee SN74LS' NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -400 J.lA 8 rnA High·level output current, 10H -400 Low·level output current, 10L 4 Width of clock pulse., high or low level, tw Setup time, tsu 20 20 Data 25 25 Word select 45 45 0 0 Data Hold time, th Word select 0 Operating free·air temperature, T A UNIT MIN ns ns ns 0 -55 125 0 70 °e electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High·level input voltage VIL Low·level input voltage VIK Input clamp voltage VOH VOL High·level output voltage Low·level output voltage SN54LS' TEST CONDITIONSt MIN TYP+ SN74LS' MAX MIN 2 Vee = MIN, II = -18 rnA Vee = MIN, VIH = 2 V, VIL = VILmax 10H = -400p.A Vee = MIN, VIH = 2 V, VIL = VILmax 2.5 I 10L =4 rnA I 10L -8 rnA TYP+ MAX 2 V 0.7 0.8 V -1.5 -1.5 V 3.4 0.25 UNIT 2.7 0.4 3.4 V 0.25 0.4 0.35 0.5 V Input current at II maximum input voltage • I Vee = MAX, VI = 7 V 0.1 0.1 rnA IIH High·level input current Vee = MAX, VI = 2.7 V 20 20 J.lA IlL Low·level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 rnA lOS Short·circuit output current!i Vee =MAX' -100 rnA ICC Supply current Vee = MAX, 13 rnA -20 See Note 2 -100 7.3 -20 13 7.3 t For conditions shown as MI N or MAX, uSe the eppropriate value specified under recommended operating conditions. *AII typical values are at Vee = 5 V, T A = 25°C. §Not more than one output should be shorted at a time, duration of the short·circuit should not exceed one second. NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to the clock input. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER TEST CONDITIONS tPLH Propagation delay time, low·to·high·level output eL=15pF, tPHL Propagation delay time, high·to·low·level output See Note 3 AL = 2 kU, MIN TYP MAX 18 27 21 32 UNIT ns NOTE 3: Load circuit and waveforms are shown on page 3-11. 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 1-501 TYPES SN54S412, SN74S412 (TIM8212) MULTI-MODE BUFFERED LATCHES TTL MSI BULLETIN NO. DL- S 12351. OCTOBER 1975 • P-N-P Inputs and 3-State Outputs Maximize I/O and Data Bus Capabilities SN54S412 ••• J PACKAGE SN74S412 ••• J OR N PACKAGE (TOP VIEW) • Data Latch Transparency Permits Asynchronous or Latched Receiver Modes DATA INPUTS fNO OUTPUTS • Mode and Select Inputs Permit Storing With Outputs Enabled or Disabled • Strobe-Controlled Flag Flip-Flop Indicates Status or Interrupt • Asynchronous Clear Sets All Eight Data Lines Low and Initializes Status Flag • High-Level Output Voltage, Typically 4 V, Drives Most MOS Functions Directly • Direct Replacement for Intel 3212 or 8212 S2 logic: see function table description This high-performance eight-bit parallel expandable buffer register incorporates package and mode selection lnputs and an edge-triggered status flip-flop designed specifically for implementing bus-organized input/output ports. The three-state data outputs can be connected to a common data bus and controlled from the appropriate select inputs to receive or transmit data. An integral status fl ip-flop provides package busy or request interrupt commands. The outputs, with a 4-volt typical high-level voltage, are compatible for driving low-threshold MOS directly. DATA LATCHES • The eight data latches are fully transparent when the internal gate enable, G, input is high and the outputs are enabled (OE = HI. Latch transparency is selected by the mode control (M), select (Sl and S2), and the' strobe (STB) inputs and during transparency each data output (OOi) follows its respective data input (Oli)' This mode of operation can be terminated by clearing, de-selecting, or holding the data latches. See data latches function table. MODE SELECTION An input mode or an output mode is selectable from this single input line. In the input mode, MO = L, the eight data latch inputs are enabled when the strobe is high regardless of device selection. If selected during an input mode, the outputs will follow the data inputs. When the strobe input is taken low, the latches will store the most-recently setup data. In the output mode, M = H, the output buffers are enabled regardless of any other control input. During the output mode the content of the register is under control of the select (51 and S2) inputs. See data latches function table. STATUS FLIP-FLOP The status flip-flop provides a low-level output signal when: a. the packagp is selected b. a strobe input is received. This status signal can be used to indicate that the register is busy or to initiate an interrupt type command. 279 7-502 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54S412, SN74S412 (TIM8212) MULTI-MODE BUFFERED LATCHES functional block diagram r---- - - -- ---- - - ----- -----, PRESET o STB M Q 1111 121 51 1231 52 011 012 013 131 41 iNT 001 (5) 161 002 171 003 014 015 016 191 1101 1181 (15) 1181 004 005 (17) 006 017 1201 018 1221 CLii (14) 1191 007 (21) 008 • ________________________ -1 schematics of inputs and outputs EQUIVALENT OF CLEAR, STROBE, MODE, S1, AND S2 INPUTS VCC _______. -__ EQUIVALENT OF EACH D1 INPUT VCC------------~--------._ TYPICAL OF ALL OUTPUTS ---f---VCC ~ OUTPUT INPUT I NPUT---.-:MIH----t 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-503 TYPES SN54S412, SN7~S412 (TIM8212) MULTI-MODE BUFFERED LATCHES DATA LATCHES FUNCTION TABLE FUNCTION CLEAR M S1 S2 STB DATA IN DATA OUT L H H X X X L L L L H L X L X L X L X X Z X L H X X X Z H H H L X X H L L H L X 00 00 H H L H X L L H H L H X H H H L L H H L L H L L H H H H Clear De-select Hold Data Bus Data Bus STATUS FLIP-FLOP FUNCTION TABLE CLEAR S1 S2 STB -INT L H X X H L X L X H H X -l- L H L X H X L H == high level (steady state) L == low level (steady state) X ==irrelevant (any Input, including transitions) Z == high Impedance (off) -l- "'transition from low to high level absolute maximum ratings over operating free-air temperature range (unless otherwise noted) • _ 7V Supply voltage, Vee (see Note 1) Input voltage _ Operating free-air temperature range: SN54S412 SN74S412 Storage temperature range. . _ 5.5V _ -55°C to 125°C _ oOe to 70°C . _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54S412 MIN 4_5 Supply voltage, VCC Pulse width, tw (see Figures 1, 2, and 4) I I SN74S412 NOM MAX 5_5 5 MIN 4_75 STB or S"1 • S2 25 25 Clear low 25 25 15-l- 15-l- 20t -55 20t Setup time, tsu (see Figure 3) Hold time, th (see Figures 1 and 3) Operating free-air temperature, T A 125 0 NOM MAX 5 5.25 UNIT V ns ns ns 70 °c t The arrow indicates that the falling edge of the clock pulse Is used for reference. 1075 7-504 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54S412, SN74S412 (TIM8212) MULTI-MODE BUFFERED LATCHES REVISED FEBRUARY 1979 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONSt VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL 10ZL Vee = MIN; II = -18mA Vee = MIN, VIH = 2 V, VIL = 0.8 V, Vee = MIN, . VIH = 2 V, Low-level output voltage Off-state output current, DO 1 thru high-level voltage applied DO 8 Off-state output current, DO 1 thru low-level voltage applied DO 8 Input current at II maximum input voltage High-level input current IIH TVPt Low-level input current M TVPt MAX I UNIT V 0.85 0.85 V -1.2 -1.2 V 4 3.4 10H = -1 mA MIN 2 V 4 3.65 10L = 15 mA 0.45 0.45 IIOL = 20mA 0.5 0.5 Vee = MAX, VO=2.4V 50 50 IJA Vee = MAX, Vo =0.5 V -50 -50 IJA Vee = MAX, VI = 5.5 V Vee = MAX, VI = 5.25 V S1 IlL SN74S412 MAX 2 VIL = 0.8 V 10ZH SN54S412 MIN Vee = MAX, VI=O.4V 1 1 mA 20 10 IJA -1 -1 -0.75 -0.75 ~.25 All others lOS Short-circuit output current§ Vee = MAX ICC Supply current Vee = MAX, -20 see Note 2 V -65 -0.25 -20 82 82 mA -65 mA 130 mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. f All typical values are at Vee =5 V, T A = 25° e. § Not more than one output should be shorted at a time. NOTE 2: ICC is measured with all outputs open, clear input at 4.5 V, and all other inputs grounded. switching characteristics, Vee PARAMETER tpLH FROM STB, S1, or S2 tpHL tpHL tpLH CLR = 5 V, TO Any T A = 25°e FIGURE TEST CONDITIONS 1 DO Any DO 2 eL = 30 pF, See Note 3 MIN TVP MAX 18 27 15 25 18 27 12 20 10 20 20 Dli DOi 3 tPLH S1orS2 INT 4 eL=30pF, 12 tpHL STB INT 4 See Note 3 16 25 eL=30pF, 21 35 See Note 3 25 40 eL=5pF, 9 20 See Note 3 12 20 tpHL tpZH 51,S2,or M Any DO tpZL tpHZ tpLZ 51,S2, or M Any DO 5 5 UNIT I ns ns ns ns ns ns tpLH == propagation delay time, low-to-high-Ievel output tpH L == propagation delay time, high-to-Iow·level output tpZH == output enable time to high level tpZL == output enable time to low level tpHZ == output disable time from high level tpLZ == output disable time from low level NOTE 3: Load circuit and voltage waveforms are shown on page 3-10. 279 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-505 TYPES SN54S412, SN74S412 (TIM8212) MULTI-MODE BUFFERED LATCHES PARAMETER MEASUREMENT INFORMATION ___ ~.=-VJ\ ---- -- - DATA INPUT ~ STBOR S1·S2 J~.:.." ~_ _ _~~ tw 1.5 V I . __ 2.5 V OV __ _ 2.5 V \'1.5 V -------------' I.- tpHL ~;-- ~--_-_-_-_- OV VOH DATA OUTPUT __ _ _ _ __ __ _ _ _ } \.....1_.5_V _ _ _ _ _ __ FIGURE 1 - STROBE OR SELECT TO DATA OUTPUT k -------___. \4- tw(clr)' ,. 5V CLEAR INPUT -+I ,...------t.5~ _ _ _ _ _ _ _ _ _ _ _ _ _ _tP_H_L~ ____ _ OV - -- \,~;- DATA OUTPUT 2.5 V VOH FIGURE 2 - CLEAR INPUT TO DATA OUTPUT 1.5V~ DATA INPUT - -- - 2.5 V - ---- - :-'W J STB OR S1·S2 t..-. --' rr-r DATA OUTPUT - - 1.,.5V ===:::;.j'- ____ ~,~;h __ n OV 25V ___ OV tpHL --------=--...,.~;---------- VOH _____ -J. VOL FIGURE 3 - DATA INPUT TO DATA OUTPUT r\~5~-- STROBE _____JI_ I - --- 2.5 V ~I~tw~(-st~b)~---------- OV 2.5 V i ---------.L..,-----tw-(-se . .~ I.. ~I"~I ° vr-l) tPLH I \ _ _ _ _ _ _----JT ~tPHL INTERRUPT OUTPUT V VOH ~~ VOL FIGURE 4 - STROBE OR SELECT TO INTERRUPT OUTPUT !1.5V \-;-5~ --- _ _---J, 2.5V OV I --.j -.J L -I tPZH ~ DATA OUTPUT (HIGH STORED) I-I ! )!',-:-~V-----I--,~ I -------I--~ ~ --l tPZL ' - - I rDATA OUTPUT (LOW STORED) tpHZ \ ~ 0.5 V f r+- tpLZ I '4.5V L5V C F _ _ _ _ _ _ _---J CO. 5V + FIGURE 5 - SELECT TO DATA OUTPUT 279 7·506 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS440 THRU SN54LS444. SN54LS448. SN74LS440 THRU SN74LS444. SN74LS448 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS TTL MSI 02425, AUGUST 1979 • 3-Way Asynchronous Communication o On-Chip Bus Selection Decoding SN54LS' ••••• J PACKAGE SN74LS' ••••• J OR N PACKAGE (TOP VIEW) • Input Hysteresis Improves Noise Margin o Choice of Open-Collector or 3-State Outputs CS VCC 81 GC C1 G8 These bus transceivers are designed for asynchronous three-way communication between four-line data buses_ They give the designer a choice of selecting inverting, noninverting, or a combination of inverting and noninverting data paths with either 3-state or open-collector outputs_ C2 GA 82 A1 83 A2 C3 A3 The SO and S1 inputs select the bus from which data are to be transferred_ The G inputs enable the bus or buses to which data are to be transferred_ The port for any bus selected for input and any other bus not enabled for output will be at high impedance including those of the open-collector devices_ C4 A4 84 S1 GND SO description The SN54LS440 through SN54LS444 and SN54 LS448 are characterized for operation over the full military temperature range of -55°C to 125°C_ The SN74LS44a through SN74LS444 and SN74 LS448 are characterized for operation from aOc to 7aoC_ DEVICE OUTPUT LOGIC 'LS440 Open-Collector True 'LS441 Open-Collector Inverting 'LS442 3-State True 'LS443 3-State Inverting 'LS444 3-State 'LS448 Open-Collector True/Inverting Truell nverting II FUNCTION TABLE TRANSFERS BETWEEN BUSES INPUTS CS S1 SO GA GB GC 'LS440 'LS441 'LS444 'LS442 'LS443 'LS448 H X X X X X None None None X H H X X X None None None X X X H H H None None None X L L X H H None None None X L H H X H None None None X H L H H X None None None L L L X L L A -> B, A -> C A -> B, A -> C A -> B, A -> C L L H L X L B -> C, B -> A S -> C, S -> A B -> C, S -> A L H L L L X C -> A, C -> B L L L X L H A->B A->B L L H H X L B->C S->C B+C L H L L H X C->A C->A C->A C-> A,C -> B C' A,C -> B A+B L L L X H L A+C A->C A->C L L H L X H Bc>A S+A S->A L H L H L X C+B C+B C->B Copyright © 1979 by Texas I nstruments Incorporated 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-507 TYPES SI54LS440 THRU SN64LS444, SN54LS448, SN74LS440 THRU SN74LS444, SN741S448 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS logic symbols 'LS440 'LS441 'LS443 'LS444 'LS448 • A4 (131 B4 (9) C4 (81 181 7·508 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS440 THRU SN54LS444, SN54LS448, SN74LS440 THRU SN74LS444, SN74LS448 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS functional block diagram (composite showing one of four transceivers from each type, positive logic) so SI GA GB COMMON CIRCUITRY ac r- -- ---------------------, I I I I .-~ I I l___ ~~~,;.~~;;:~; ,; ,;,; ~ ~ ~ j I r - - - --::------~-- ~ A ---l I I I ;J )---, T- ~ - I I I I I I I L ______________________ ...JI r - _ A I I I I: I ! ~~O.:.F~U~~~!!'~2.T~A~S~I~~ ~, T- ~~~ T H--:-i- } - __ - - - - , ~ I I -.dr--, - I I ~ II I ~ ! IL _______________________ T~ ..J i ---- - - - l ONE OF FOUR 'LS4441'LS448 TRANSCEIVERS ;:.: ------------~ A :~.J I I I: I I L T ~-:h T- _ ~ ---=---I I r JT-1 ~ I ~ II I I rr--I :I Cl ")-, ------ I : I ------------------J--l7'-:,-...J absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage. Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Off-state output voltage ...................................................... " 5.5 V Operating free·air temperature range: SN54LS' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , _55°C to 125°C SN74LS' ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. 979 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7·509 TYPES SN54LS440, SN54LS441, SN54LS448, SN74LS440, SN74LS441, SN74LS448 QUAD TRIDIRECTIONAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS recommended operating conditions SN54LS440 SN54LS441 SN54LS448 MIN NOM 4.5 Supply voltage, Vee (see Note 1I SN74LS440 SN74LS441 SN74LS448 MAX 5 5.5 UNIT MIN NOM MAX 5 5.25 4.75 V High-level output voltage, VOH 5.5 5.5 V Low-level output current, IOL 12 24 rnA 70 e 125 -55 Operating free-air temperature, T A 0 NOTE 1: Voltage values are with respect to the network ground terminal. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage • VIK Vec= MIN, Vee = MIN High-level output current VOL Low-level output voltage MIN TYP:j: MAX 0.6 Vee= MIN, VOH - 5.5 V, VIH=2V, VIL=VILmax -1.5 -1.5 0.1 0.4 0.2 0.25 0.4 V V V 0.4 100 IOL = 12 rnA UNIT V 2 II = -18mA VCC= MIN, 100 jJA 0.25 0.4 V 0.35 0.5 V VIH = 2 V, IOL = 24 rnA VIL =VILmax I SN74LS' TYP:j: MAX 0.5 Input clamp voltage IOH II MIN 2 Hysteresis (VT+ - VT _II A,B,C input Input current at SN54LS' TEST CONDITIONSt I A,B,e input I maximum input voltage All others Vee = MAX VI-5.5V 0.1 0.1 VI = 7V 0.1 0.1 rnA IIH High-level input current VCC= MAX, VI=2.7V 20 20 jJA IlL Low-level input current VCC= MAX, VI= 0.4 V -0.4 -0.4 rnA ICC Supply current Vee = MAX, Outputs open I Outputs low I Outputs disabled 62 90 62 90 64 95 64 95 rnA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°e. switching characteristics at Vee PARAMETER Propagation delay tPLH time,low-to-high level output Propagation delay tPHL time, high-to-Iow level output tPLH FROM TO (lNPUTI (OUTPUTI 'LS441 'LS440 MIN TYP MAX MIN TYP 'LS448 MAX MIN TYP MAX A B 24 35 21 30 21 30 A C 24 35 21 30 21 30 B A 24 35 21 30 21 30 B C 24 35 21 30 24 35 C A 24 35 21 30 21 30 C B 24 35 21 30 24 35 A B 20 30 9 15 9 15 A C 20 30 9 15 9 15 B A 20 30 9 15 9 15 B e 20 30 9 15 20 30 C A 20 30 9 15 9 15 C B 20 30 9 15 20 30 Propagation delay any G A,B,C 29 45 23 35 25 40 time,low-to-high • SO,S1 A,B,C 33 50 27 40 26 40 CS A,B,C 31 45 26 40 25 40 Propagation delay any G A,B,C 27 40 20 30 22 35 time, high-to-Iow SO,S1 A,B,C 32 50 26 40 27 40 CS A,B,C 28 45 21 30 22 35 level output tPHL = 5 V, RL = 667 il, eL = 45 pF, TA = 25°e, see Note 2 level output UNIT ns ns ns ns NOTE 2: Load circuit and voltage waveforms are shown on page 3-11. 181 7·510 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS442. SN54LS443. SN54LS444. SN74LS442. SN74LS443. SN74LS444 QUAD TRIDIRECTIONAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS recommended operating conditions Supply voltage, Vee (see Note 1) SN54LS442 SN74LS442 SN54LS443 SN74LS443 SN54LS444 SN74LS444 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V -15 mA 24 mA 70 °e -12 High-level output current, 10H 12 Low-level output current, 10L 125 -55 Operating free-air temperature, T A UNIT 0 NOTE 1: Voltage values are with respect to the network ground terminal. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONSt PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage Vee= MIN, Vee- MIN, VOL High-level output voltage Low-level output voltage 10H = MAX Vee- MIN, 10L = 12mA Vee= MAX, Off-state output current, low-level ~at2V voltage applied lA, B,e maximum input voltage I Others Vee = MAX UNIT V 0.5 0.6 V -1.5 -1.5 V 0.1 0.4 0.2 0.4 2.4 3.4 2.4 3.4 V 2 2 0.25 0.4 0.25 0.4 0.35 0.5 V VIH =2 V, voltage applied Input cu rrent at II MAX V VIL = VI Lmax Off-state output current, high-level 10ZL TYP:j: 2 II =-18mA 10H = -3 mA MIN VIH=2V, VIL = VILmax 10ZH MAX 2 Hysteresis (VT+ - VT _)IA,B,e input Vee = MIN VOH SN74LS' SN54LS' MIN TYP:j: 10L = 24mA Vo = 2.7 V 20 20 Vo = 0.4 V -400 -400 VI=5.5V 0.1 0.1 VI =7 V 0.1 0.1 J.l.A mA IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 J.l.A IlL Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA lOS Short circuit output current'll Vee= MAX -225 mA lee Supply current I Outputs low I Outputs at Hi-Z Vee= MAX, -225 -40 Outputs open -40 62 90 62 90 64 95 64 95 I mA t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at Vee = 5 V, T A = 25°C. 'v Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 181 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 7·511 I I TYPES SN54LS442, SN54LS443, SN54LS444, SN74LS442, SN74LS443, SN74LS444 QUAD TRIDIRECTIONAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS switching characteristics, Vee PARAMETER FROM TO TEST (INPUT) (OUTPUT) CONDITIONS A tpLH tPHL MAX 10 B 'LS444 'LS443 TYP MIN TYP MAX 9 9 9 14 14 14· 14 10 14 9 14 14 10 14 13 TYP MAX 14 9 14 A C 10 14 delay time, B A 10 14 low-to-high B C 10 14 level output C A 10 14 C B 10 14 9 9 9 9 9 MIN 14 14 14 A B 13 20 7 13 7 Propagation A C 13 20 7 13 7 13 delay time, B A 13 20 7 13 7 13 13 20 7 13 13 20 13 CL =45 pF, UNIT ns ns high-to-Iow B C level output C A 13 20 7 13 7 C B 13 20 7 13 13 20 Any G A,B,C 22 33 22 33 22 33 SOorS1 A,B,C 28 42 28 42 28 42 CS A,B,C 23 36 24 36 23 36 A,B,C 21 32 20 32 24 32 ns 14 25 15 25 14 25 ns 14 25 15 25 14 25 ns time to low level Output enable tPZH 'LS442 MIN Propagation Output enable tPZL = 5 V, TA = 25°e, see Note 2 time to high level G,S, CS RL=667n ns Output disable tPLZ time from low level Output disable tPHZ time from high level G,S, CS G,S, CS A,B,C CL.= 5 pF, RL=667il A,B,C NOTE 2: Load circuit and voltage waveforms are shown on page 3-11. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF 3-STATE OUTPUTS TYPICAL OF OPEN-COLLECTOR OUTPUTS VCC---~----_ - _...._VCC Req 50.0 NOM _ _ ~OUTPUT INPUT OUTPUT Req: GA, GS, GC = 9 kn NOM kn NOM All others = 5 181 7·512 TEXAS)NSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 • 7·513 TYPES SN74S428(TIM8228), SN74S438(TIM8238) CONTROLLER AND BUS DRIVER FOR S080A SYSTEMS TTL LSI BULLETI N NO. DL-S 12468, OCTOBER 1976 • N PACKAGE Designed to Be Interchangeable with Intel 8228 and 8238 (TOP VIEW) PIN DESIGNATIONS i75W Vee DESIGNATION DO thru 07 DBO thru DB7 I/OR 10/W MEMR PIN NOS. '~D"'.--I11111111111""""""'!'--~D""O\ INTA i70A MEMW MEMR BUSEN FUNCTION 15, 17, 12, 10, BIDIRECTIONAL DATA PORT 6, 19,21,8 (TO TMS 8080A) 13, 16, 11,9, BIDIRECTIONAL DATA PORT 5, 18, 20, 7 25 27 24 MEMW 26 DBIN 4 (TO SYSTEM BUS) READ OUTPUT TO I/O (ACTIVE LOW) DB' OBIN ''-_ _ _ _ _ _vv''------GN..,DI WRITE OUTPUT TO I/O BIDIRECTIONAL DATA PORTS (ACTIVE LOW) logic: see description READ OUTPUT TO MEMORY (ACTIVE LOW) WRITE OUTPUT TO MEMORY (ACTIVE LOW) functional block diagram INPUT TO INDICATE TMS 8080A IS IN INPUT INTA 23 HLDA 2 01 INTERRUPT ACKNOWLEDGE OUTPUT (ACTIVE LOW) HOLD ACKNOWLEDGE TMS 8080A 1/0 DATA PORT INPUT (ACTIVE HIGH) FROM TMS 8080A INPUT TO INDICATE WR 3 TMS 8080A IS IN WRITE MODE (ACTIVE LOW) • SYSTEM DATA PORT Ei1JSEj\j 22 DB~ DO MODE (ACTIVE HIGH) OBI DB2 02 03 DB3 f SY~J;M 04 05 DB4 DATA PORT DB5 06 07 DB6 DB7 STATUS (1) STROBE INPUT ENABLE INPUT (ACTIVE LOW) SYNCHRONIZING STATUS STSTB 1 STROBE INPUT FROM SN74LS424 (TIM8224) VCC GND 28 SUPPLY VOLTAGE (5V) 14 GROUND Vcc = PIN (28). GND = PIN (14) description These monolithic Schottky-clamped tTTL system controllers are designed specifically to provide bus-driving and peripheral-control capabilities for interfacing memory and I/O devices with the 80aOA in small to medium-large micro· computer systems. A bidirectional eight·bit parallel bus driver is provided that isolates the 8080A bus from the memory and I/O data bus allowing the system designed to utilize cost-effective memory and peripheral devices while obtaining the maximum efficiency from the microprocessor. T.he TTL system drivers also provide increased fan-out with a lower impedance that enhances noise margins on the system bus. Implementation of the status latches and control decoding array of the SN74S428/SN74S438 provides for using either a single·level interrupt vector RST7 for small systems, or multiple·byte call instructions for systems needing unlimited interrupt levels. 879 7-514 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 t Integrated Schottky-Barrier diodeclamped transistor is patented by Texas U.S. Patent Number Instruments. 3,463,975. TYPES SN74S42B(TIMB22B), SN74S43B(TIM823B) CONTROLLER AND BUS DRIVER FOR BDBDA SYSTEMS description (continued) With respect to the system clocks, the SN74S43S is configured to generate an advanced response for I/O or memory write output signals to further simplify peripheral control implementation of complex systems. See Figure 3. 8-bit parrallel bus transceiver The 8-bit parallel bus transceiver buffers the SOSOA data bus from the memory and I/O system bus by providing one port (DO through 07) to interface with the 80S0A and another port (DBa through DB7) to interface with the system devices. The SOSOA side of the transceiver is designed specifically to interface with the microprocessor data bus ensuring not only that the processor output drive capabilities are adequate, but also that the inputs are driven with enhanced noise margins. The system bus side features high fan-out buffers designed to drive a number of system devices simultaneously and directly. The system port is rated to sink ten milliamperes of current and to source one milliampere of current at standard low-threshold voltage levels. Status lines from the S080A instruction-status decoder and the system bus enable input (BUSEN) provide complete transceiver directional and enable control to ensure integrity of both the processor data and the system bus data. status latches During the beginning of each machine cycle, the six status latches receive status information from the 80S0A data bus indicating the type of operation that will be performed. When the STSTB input goes low, the latches store the status data and generate the signals needed to enable and sequence the memory and I/O control outputs. The status words and types of machine cycles are enumerated in Table A. TABLE A - STATUS WORDS 8080A STATUS WORD TYPE OF STATUS OUTPUT MACHINE CYCLE 'S4281'S438 COMMAND DO 01 02 03 04 05 06 07 1 L H L L L H L H I nstructi on fetch MEMR 2 L H L L L L L H Memory read ME'MR GENERATED 3 L L L L L L L L Memory write MEMW 4 L H H L L L L H Stack read ME'MR 5 L L H L L L L L Stack write MEMW 6 L H L L L L H L Input read 7 L L L L H L L L Output write 8 9 H H L L L H L L Interrupt acknowledge iNTA L H L H L L L H Halt acknowledge NONE H H L H L H L L Interrupt acknowledge at halt INTA « I- I~ ~ « I- l::l i c. ~ a:: :2: w :2: 10 ~ u « l- (/) ....J I: 0 II IIOR TTOW STATUS INFORMATION decoding array The decoding array receives enabling commands from the status latches and sequencing commands from the 8080A and generates memory and I/O read/write commands and an interrupt acknowledgement. 1076 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-515 TYPES SN74S42B(TIMB22B), SN74S43B(TIM823B) CONTROLLER AND BUS DRIVER FOR BDBDA SYSTEMS description (continued) The read commands (M"E'M"R, I/O R) and the interrupt acknowledgement (I NT A) are derived from the status bit(s) and the data bus input mode (DBIN) signal. The write commands (MEMW, i7QW) are derived from the status bit(s) and the write mode (WR) signal. (See Table A.) All control commands are active low to simplify interfacing with memory and I/O controllers. The interrupt acknowledgement (lNTA) command output is actually a dual function pin. As an output, its function is to provide the ii\iTA command to the memory and I/O peripherals as decoded from the status inputs and latches. When CALL is used as an interrupt instruction, the SN74S428/SN74S428 generates the proper sequence of control signals. Additionally, the terminal includes high-threshold decoding logic that permits it to be biased through a onekilohm series resistor to the 12-volt supply to implement an interrupt structure that automatically inserts an RST7 instruction on the bus when the DBIN input is active and an interrupt is acknowledged. This capability provides a single-level interrupt vector with minimal hardware. The asynchronous bus enable (BUSEN) input to the decoding array is a control signal that protects the system bus. The system bus can be accessed and driven' from the SN74S428/SN74S428 controller only when the BTISEi\i input is at a low voltage level. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ... 7 V 7V O°C to 70°C -65°C to 150°C Supply voltage, VCC (see Note 1) Input voltage ....... . Operating free-air temperature range Storage temperature range NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions • Supply voltage, Vee MIN NOM MAX 4.75 5 5.25 -10 DO thru 07 High-level output current, IOH -1 All others DO thru 07 Low-level output current, IOL 2 All others Status strobe pulse width, tw(STSTB) (see Figure 3) Status inputs DO thru 07 Setup time, tsu (see Figure 3) System bus inputs to HLDA Status inputs DO thru 07 Hold time, th (see Figure 3) System bus inputs to HLDA Operating free-air temperature, T A 10 22 8 10 5 20 0 UNIT V IlA rnA rnA ns ns ns 70 °e 1076 7-516 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN74S42B(TIMB22B), SN74S43B(TIMB23B) CONTROLLER AND BUS DRIVER FOR BOBOA SYSTEMS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK I nput clamp voltage VOH VOL TEST CONDITIONS DO thru D7 High-level output voltage Low-level output voltage high-level voltage applied low-level voltage applied INTA High-level input current IIH Vce - MIN, II - -5 mA Vee = MIN, VIH=2V, 3.6 10H = MAX 2.4 All other outputs VIL = 0.8 V, Off-state output current, 10ZL TYP+ DO thru D7 All other inputs Vee = MIN, VIH=2V, VIL = 0.8 V, 10l = MAX Vee = MAX, Low-level input current UNIT V 0_8 V -1 V 4 V 0.45 V VO=5.25V 100 JJA Vce = MAX, Vo = 0.45 V -100 JJA Vee= MIN, See Figure 1 5 mA Vee = MAX, VI = 5.25 V 20 100 D2 or D6 IlL MAX 2 Off-state output current, 10ZH MIN JJA -750 STSTB -500 VI =0.45 V Vee = MAX, All other inputs JJA -250 lOS Short-circuit output current§ Vee = MAX Ice Supply current Vee = MAX -15 140 -90 mA 190 mA t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions. +AII typical values are at Vee = 5 V, TA = 25°e. § Not mOre than one output should be shorted at a time. switching characteristics, Vee = 5 V, TA =25°e, see figure 3 FROM TO (INPUT) (OUTPUT) tPD DO thru 07 DBO thru DB7 tPD DBO thru DB7 DO thru D7 PARAMETER~ tPHL tPD STSTB WR TEST CONDITIONS eL=100pF, See Figure 2 el - 25 pF, See Figure 2 CL= 100pF, See Figure 2 INTA,"ilOR, MEMR, flOW, MEMW I/OW,MEMW MIN 5 TYP MAX UNIT 40 ns 30 ns 20 60 ns 5 45 ns tPlH DBIN INTA,"ilOR, MEMR 30 ns tPlH HLDA INTA, ITOR, MEMR 25 ns 45 ns tpzx DBIN DO thru D7 tpxz DBIN DO thru D7 tpzx STSTB,BUSEN DBO thru DB7 tpxz I3mm DBO thru DB7 CL=25pF, See Figure 2 eL = 100pF, See Figure 2 45 ns 30 ns 30 ns • ~ tpc == propagation delay time tpH L == propagation delay time, high-to-Iow-Ievel output tpLH == propagation delay time, low-to-high-Ievel output tpzx == output enable time from high-impedance state tpxz == output disable time to high-impedance state 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-517 TYPES SN74S428(TIM8228), SN74S438(TIM8238) CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS PARAMETER MEASUREMENT INFORMATION FIGURE 2-SWITCHING CHARACTERISTICS LOAD CIRCUIT FIGURE 1-INTA INPUT CURRENT TEST CIRCUIT INPUT HLDA INPUT II tpzxWRINPUT tPHL--1....... /DWORMEMW----------------~:41--~I~.S4=28~O~nl~YJ--------~~ OUTPUT 15~ .... '-l-I ('S438 only, see Note A) TMS ~~~~~~RII~~UT DOthruD7 • D~:~~~r:~~;E ! - - ~-rtP::..D---------------------- --J*. . - - - -----"'-1,..:.;0..:;..8V'--_ _ _ _ _ _ _ BUSEN INPUT T A tpzx"'1 .:;-V - ~ ~rt~PD~_____ 1...__________...JJL1.5V VIr " 1 . 5 - V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ _ _ _ _ _ _ _ ......... ....+ SYSTEM BUS OUTPUT I!SVt i \1.5V 1.5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ f1.5V 11..._ _ _ _ _- - ' 1 SYSTEMBUS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _ ; f 3 V OUTPUTS I ~0.8V ~tPzx~ DBO thru DB7 I 3V+ i 0.8VJL----------ii=='*-tpxz NOTE A: Advanced response of IIOW or MEMW for the SN74S438 is indicated by the dashed line. FIGURE 3-VOL TAGE WAVEFORMS 1076 7·518 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 TYPES SN74S42B(TIMB22B), SN74S43B(TIM823B) CONTROLLER AND BUS DRIVER FOR BOBOA SYSTEMS TYPICAL APPLICATION DATA VDD ( 1 2 V ) - - - - - - - - . - - - - - - - - - - - - - , VCC - (5V ) - \(16) (9) V DD VCC ~ XTAL ~ TANK~ ~ OSC L T V BB (-5V ) TANK OSC ~1 ~ RESIN RDYIN ~ RDYIN (22) ~1 (10) (15) S080A CPU TIMS224 ~2 1-'-"""-+----1 ~2 CLOCK GENERATOR DRIVER ~2TTL ~ ~2TTL RESIN VCC (11) SYNCI-(;.;.5:...)_~ ...._(:...19-'-t) SYNC RESET (I) ~ (IS) DO (10) DO r (17) (9) Dl (S) ~ ~ (12) D2 (7) ~ --" (10) D3 (3) (6) D4 D4 (4) ..oL ~ (19) D5 D5 (5) ~ :- (21) D6 D6 (S) (6) ~ :: D7 D7 Dl D2 D3 . DBIN (17) WR (IS) • HLDA 1"""(21) (23) READY STsTB pQ! GND VCC DBO '542S/'5438 (TlMS22SI TlMS238) DBI DB2 BIDIRECTIONAL BUS TRANSCEIVER ~!f- --t-i!~; (13) (16) 11 (9) --A. ~ (4) DBIN (3Jr WR ~ ...... ~ (2) 22) ~ ~ DECODING ARRAY HLDA BUSEN BUSEN INTA (23) MEMR 1'""J.24)--" [:>(~26~) STSTB OMA BUS - INTA} - __ . . ._ _ : : : : MEMW ~ 125) I/OR I/OR ~ (27) ~ I/OW rI/OW (I) WAIT --=. .. ~ DB3 (5) ~ ~ DB4 t-;';,:::-.--t_DB4 (IS) ..oL DB5 """',.,.-.....-t_DB5 (20) ~ ~ DB6 h ; t - . - t _ DB6 (7) ....... DB7 DB7 t---=;:,:--- (12) RESET READY (4) I,m (28) V DD CONTROL BUS ,~ 1 GND ~14) AD - Al A2 A3 (13) SYSTEM DMA REQUEST---+-__""';';''''i HOLD A4 (14) INT SYSTEM INTERRUPT REQUEST----+-....-.:.:-'-'t A5 A6 A7 AS A9 AID (16) INTE INTERRUPT ENABLE ---+--4"":';'''''1 (25) (26) Jo (27) ~ r (29) (3D) (31) : . (32) _. (33) ~ (34) ~ . (35) (1 ADDRESS BUS • I (40) • (37) ~ (3S) A13 (39) A14 (36) A15 All A12 Vss ~) FIGURE 4-SYSTEM INTERFACING WITH CENTRAL PROCESSING UNIT 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • OALLAS, TEXAS 75265 7·519 TYPES SN54490, SN54LS490, SN74490, SN74LS490 DUAL 4-81T DECADE COUNTERS TTL MSI BULLETIN NO. OL·S 7612089, OCTOBER 1976 • Dual Versions of Popular SN5490A, SN54LS90, SN7490A, and SN74LS90 Counters • Individual Clock, Direct Clear, and Set-to-9 Inputs for Each Decade Counter SN54490 ... J OR W PACKAGE SN74490 ••. J OR N PACKAGE (TOP VIEW) 2 VCC • 2 CLOCK CLEAR 20A OUT· PUT 2 OUTPUTS ~~T9~ Dual Counters Can Significantly Improve System Densities as Package Count Can Be Reduced by 50% o Maximum Count Frequency ... 35 MHz Typical • Buffered Outputs Reduce Possibility of Collector Commutation 1 1 CLOCK CLEAR description lOA OUT· PUT positive logic: High input to clear resets all four outputs low; Each of these monolithic circuits contains eight high input to set-to-9 sets 0A and QD high, QB master-slave flip-flops and additional gating to impleand Oc low. ment two individual 4-bit decade counters in a single package. Each decade counter has individual clock, clear, and set-to-9 inputs. BeD count sequences of any length up to divide-by-l00 may be impleme~ted with a single '490 or 'LS490. Buffering on each output is provided to ensure that susceptibility to collector cummutation is reduced significantly. All inputs are diode-clamped to reduce the effects of line ringing. The counters have parallel outputs from each counter stage so that submultiples of the input count frequency are available for system timing signals. • The SN54490 and SN54LS490 are characterized for operation over the full military temperature range of -55°e to o 125°e; the SN74490 and SN74LS490 are characterized for use in industrial systems operating from oOe to 70 e . BCD COUNT SEQUENCE (EACH COUNTER) COUNT 0 OUTPUT CLEAR/SET-TO-9 00 Oc °B °A L L L L FUNCTION TABLE (EACH COUNTER) INPUTS 1 L L L H 2 L L H L 3 L L H H 4 L .H L L L H 5' L H L H L L 6 L H H L 7 L H H H 8 H L L L 9 H L L H OUTPUTS CLEAR SET-TO-9 QA 0B Oc 00 H L L L L L H = high level, H L L H COUNT L = low level 1076 7·520 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54490, SN54LS490, SN74490, SN74LS490 DUAL 4-811 DECADE COUNTERS schematics of inputs and outputs '490 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS vee3-Req INPUT -- Req NOM 3kH CLEAR, SET·TO-9 8 kH 'LS490 EQUIVALENT OF EACH CLOCK INPUT EQUIVALENT OF EACH CLEAR AND SET-TO-NINE INPUT vee __. . . ___ TYPICAL OF ALL OUTPUTS ----.. . .-vee Vee -----4,.....--- OUTPUT functional block diagram (each counter) • I 16,101 OUTPUT ac f--t-t-'--'-'- OUTPUT aD 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-521 TYPES SN54490, SN74490 DUAL 4-81T DECADE COUNTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) . . . . . Input voltage . . . . . . . . . . . . . Operating free·air temperature range: SN54490 SN74490 Storage temperature range . . . . . 7V . . . . 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54490 Supply voltage, VCC MIN NOM 4.5 5 High·level output current, 10H SN74490 MAX MIN NOM 5.5 4.75 5 -800 Low·level output current, 10L 16 0 Count frequency, fcount 25 0 20 Pulse width, tw (any input) Operating free-air temperature, T A V -800 p,A 16 mA 25 MHz ns 25~ -55 125 UNIT 5.25 20 25~ Clear or set·to-9 inactive·state setup time, tsu MAX ns 0 70 °c l The arrow indicates that the falling edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) • TEST CONDITIONSt PARAMETER VIH High·level input voltage VIL VIK Low·level input voltage Input clamp voltage VCC = MIN, 11=-12mA VCC= MIN, VIH = 2 V, VIL = O.B V, 10H = -BOO p,A VOL Low·level output voltage II Input current at maximum input voltage IIH High·level input current Low-level input current TYPt MAX UNIT V 2 VOH High·leIIel output voltage IlL MIN VCC = MIN, VIH=2V, VIL=O.BV 10L= 16mA O.B -1.5 2.4 Clock Clear, set-to-9 Clock 40 VCC = MAX, VI = 2.4 V BO -1 VCC = MAX, VI = 0.4 V lOS Short·circuit output current§ lSN54490 VCC = MAX [SN74490 ICC Supply current Vee = MAX, See Note 2 0.4 1 VCC= MAX, VI = 5.5 V Clem, set-to-9 V 3.4 0.2 -3.2 -57 -20 -18 -57 45 V V 70 V mA p,A mA mA mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. tAli typical values are at V CC = 5 V, T A = 25° C. § Not more than one output should be shorted at a time. NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V. and all other inputs grounded. 1076 7-522 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54490, SN74490 DUAL 4-811 DECADE COUNTERS switching characteristics, Vee PARAMETER~ f max Clock tPlH tpHl ~fmax tpLH tpH L = 5 V, T A =25°e FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX 25 35 12 20 13 24 26 39 39 °A Clock °A MHz 20 tplH tpHl Clock °B,OD tplH tpHl Clock 32 36 54 °c tpHl Clear Any 24 tPlH tpHl Set-to-9 °A,OD °B,OC 24 39 39 20 36 == maximum count frequency == propagation delay time, low-to-high-Ievel == propagation delay time, high-to-Iow-Ievel Cl=15pF, Rl=400n, See Figure 1 and Note 3 UNIT 54 ns ns ns ns ns output output NOTE 3: Load circuit is shown on page 3-10. S~~~~~9 J.=l\~;-------- -~s- - - - - - ~S f4---- - - - - - - --:: ~I tsu ~1;v---I-------------------- CLEAR 3V INPUT --i-----..J I I I , -I - -:-"""\ : , ~1.SV I \ ~IPHL I I I \ 1.SV , : ' \ 1-5 V 1.SV i all n +2 l1.5V I ! I I I \ 0 IpHL -Measure all n +2 \.f-;_V_ _ _ r.J 1.SV IpLH-Measure 01'n+4 -4- 1.SV \ If PHL 1 IpLH-Measureall n +8 ' \ 1.SV i ~I f 1.SV I VOH '1.1.SV '--- VOL VOH I VOL ~ ~ • IpHL-Measurealln +8 :~ 1-SV IpHL-Measureall n +10 l 'ri ~--- / ' 1.SV ~.---------~{J VvOoHL IPHL-Measure all n +4 I -I I -- 1.-...-1 I ---.!..r I I ~ ~_,JIr-I.--..I I I IS. I~IPHL ~ I I I I ~ IPLH-Measure~ !4--+I--IPHL 4 ~ , -,-"\ I I \1.SV ~IPLH 1,..------, OUTPUT Co pi , IpHL IpLH-Measure n all +1 -1-' I --,-, I OUTPUTCc I : ~----3V ~1.SV rI _.- - ~ I v I ~IPHL OUTPUTCS I+---+t-- : I r---..:.I-."""",\~I jJ1.SV 0v 1.SV I ,- Sf ~ Iwlclockl ~ --:--------:-1---......1 ~ IpLH OUTPUTCA IS I I+- tsu --+t : I CLOCK INPUT I VOH 1.SV VOL VOLTAGE WAVEFORMS NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr ..;; 5 ns, tf ..;; 5 ns, PRR = 50%, Zout ". 50 ohms. = 1 MHz, duty cycle FIGURE 1 )76 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·523 TYPES SN54LS490 SN74LS490 DUAL 4-81T DECADE COUNTERS REVISED DECEMBER 1980 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vcc (see Note 1) Clear and set·to·9 input voltage Clock input voltage . . . . . . Operating free·air temperature range: SN54LS490 SN74LS490 Storage temperature range .7V .7V 5.5 V _55°C to 125°C O°C to 70°C -65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS490 MIN NOM MAX 4.5 5 5.5 Supply voltage, Vee High·level output current, 10H SN74LS490 UNIT MIN NOM MAX 4.75 5 5.25 V -400 4 Low·level output current, 10L Count frequency, fcount 0 8 25 IJA mA MHz 70 -400 25 0 Pulse width, tw (any input) 20 20 ns Clear or set-to-9 inactive-state setup time, tsu Operating free-air temperature, T A 25, 25, ns °e -55 125 0 ,The arrow indicates that the falling edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER • TEST CONDITIONSt VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage Input current at SN54LS490 TYP:j: MAX 2 VCC =MIN, VCC = MIN, VIL = VILmax Vee - MIN, VIH II 2.5 3.4 0.25 10L =4 mA 0.4 Clear, set-to·9 VCC = MAX, maximum input voltage Clock - High-level input current set·to·9 VCC = MAX, V 3.4 0.25 0.4 0.35 0.5 VI =7 V 0.1 0.1 VI = 5.5 V 0.2 0.2 20 20 100 100 VI=2.7V Clear, Low·level input current set·to·9 VCC = MAX, ~ lOS Short-circuit output current§ Vee = MAX lee Supply current VCC = MAX, V V V 10L =8 mA ~ IlL -1.5 2.7 UNIT V 0.8 0.7 -1.5 Clear, IIH SN74LS490 TYP:j: MAX 2 = -18mA VIH = 2 V, MIN =2 V, VIL = VILmax II MIN VI =0.4 V -20 See Note 2 -0.4 -0.4 -1.6 -1.6 -100 15 26 -20 15 mA IJA mA -100 mA 26 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at V CC = 5 V, T A = 25°C. § Not more than one output should be shorted at a time, and duration of the short-cIrcuit should not exceed one second, NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs grounded. 121 7-524 TEXAS (NSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS490, SN74LS490 DUAL 4-81T DECADE COUNTERS switching characteristics, Vee PARAMETERlI f max tPLH = 5 V, TA =25°e FROM TO (INPUT) (OUTPUT) Clock °A Clock °A Clock °B,OD tpHL tpLH tPHL tpLH Clock TYP 25 35 RL= 2 k!l CL=15pF, Oc Clear tpLH MIN See Figure 2 and Note 4 Set-to-9 UNIT MHz 12 20 13 20 24 39 26 39 32 54 54 24 39 °A,OO 24 39 °B,OC 20 36 Any tpHL MAX 36 tpHL tpHL TEST CONDITIONS ns ns ns ns ns lIf max == maximum count frequency tpLH == propagation delay time, low-to-high-Ievel output tpHL == propagation delay time, high-to-Iow-Ievel output NOTE 4: Load circuit is shown on page 3-11. S~~~~~9 ~~3~------f4-----CLEAR INPUT 14- 1 ~S - - ~tw(clockl~ -+I - - - - - - --:: .l'1.3V --:-':+ I I \ 1.3 V I --1-' I ~ \1.3V' I I' I t r' 1.3V . I \ : 11.3v tPLH-M.asur. .t' n +4 1.3 V If \ t tPHL ~I f r ~---------~~iff------J '---I i1.3V : I - at tn+4 VOH ' ( 1.3V 1..-..-1 I I Tl 1 1 1 I I - ~ asur.attn+a \ . 1.3 V • VvOoHL / I 1.3 V ~ Me PLH- r- attn+2 1.3V v ~'I----~-.1 I.--..-- tpHl -Measur. ~ I~ tPHL + I: I~ 0 tpHL -Measure ! f . \ -,-, I I 1 tpLH-M.a.ur. ~ .ttn+2 I ~l 1.3 V 1 1_3V ~ ~ 1 I ~ tpHL ~ tpLH I ~,.____I_t_-I ~ tpHl ' \ 1.3V tPLH-M.asu.. n att +l -1-""'\1 :'-':-tPHL I : t-l' . ~ - :: ~----3V ~13V 1+----+ : 1,.___...:.I_t""",\-1 i -L.J ~tPHL OUTPUT CD - : : : I I OUTPUTCc tsu --:--------..:-1-----' I OUTPUTCB - --i-------'n'~·---!--~~------~--------I4---+t- tplH OUTPUTCA -~\- - - -I tsu I CLOCK INPUT - VOL tpHL-M.asur.attn+a -- VOH X, 1.3 V ~ VOL ~ tPHL -Measur.at tn+l0 ~I _ _ _ VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr .;; 15 ns, tf';; 6 ns, PRR = 50%, Zout '" 50 ohms. = 1 MHz, duty cycle FIGURE 2 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-525 TTL MSI TYPES SN54LS670, SN74LS670 4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS BULLETIN NO. DL-S 7612122, MARCH 1974-REVISED OCTOBER Hi76 • SN54LS670 ••• J OR W PACKAGE SN74LS670 ••• J OR N PACKAGE (TOP VIEW) Separate ReadIWrite Addressing Permits Simultaneous Reading and Writing • Fast Access Times ... Typically 20 ns • Organized as 4 Words of 4 Bits • Expandable to 512 Words of n-Bits • For Use as: Scratch-Pad Memory Buffer Storage between Processors Bit Storage in Fast Multiplication Designs • 3-State Outputs • SN54LS170 and SN74LS170 Are Similar But Have Open-Collector Outputs 02 Q2 positive logic: see description description The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized as 4 words of 14 bits each and separate on-chip decoding is provided for addressing the four word locations to either write·in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When thewrite-enable input,Gw, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and go into the high-impedance state. • The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. This arrangement-data-entry addressing separate from data-read addressing and individual sense line-eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in that data is not lost when addressed. All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS standard load, and input-clamping diodes minimize switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the read-address function and have high-sink-current, three-state outputs. Up to 128 of these outputs may be wire-AND connected for increasing the capacity up to 512 words. Any number of these registers may be paralleled to provide n-bit word length. The SN54LS670 characterized for operation over the full military temperature range of -55°C to 125°C; the SN74LS670 is characterized for operation from O°C to 70°C. 107! 7-526 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 TYPES SN54LS670, SN74LS670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS REVISED OCTOBER 1976 logic READ FUNCTION TABLE (SEE NOTES A AND 01 WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI WRITE INPUTS NOTES: WORD WB WA L L GW L READ INPUTS 1 2 3 RB RA GR Q1 Q2 Q3 Q4 Q=D QO QO QO L L L WOB1 WOB2 WOB3 WOB4 L H L QO Q=D H L L QO QO QO Q=D H H L QO 00 X X H QO QO A. B. C. D. OUTPUTS 0 QO L H L W1B1 W1B2 W1B3 W1B4 H L L W2B1 W2B2 W2B3 W2B4 QO QO Q=D H H L W3Bl W3B2 W3B3 W3B4 QO QO X X H Z Z Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) (0 = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. 00 = the level of 0 before the indicated input conditions were established. WOB 1 = The first bit of word 0, etc_ functional block diagram 02 DATA INPUTS OUTPUTS • 1121 Gw Ws 1141 WA '----v----' WRITE INPUT 1076 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7·527 TYPES SN54LS670, SN74LS670 4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS schematics of inputs and outputs TYPICAL OF ALL OUTPUTS EaUIVALENT OF EACH INPUT Vee-----------__~-------- -----------------~t_------- Vee n 100 NOM INPUT--~~~~------~- L------t--------OUTPUT Any D, R, or W: Req GR: Req GW: Req = 20 kn NOM = 6.67 kn NOM = 10 kn NOM absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, Vee (see Note 1) Input voltage . . . . . . . . Off·state output voltage Operating free·air temperature range: SN54LS670 SN74LS670 Storage temperature range • 7V 7V 5.5 V -55°C to 125°C oOe to 70°C -65°C to 150°C recommended operating conditions SN74LS670 SN54LS670 MIN 4.5 Supply voltage, Vee 5 MAX MIN NOM 5.5 4.75 5 -1 High·level output current, IOH 4 Low-level output current, IOL Width of write-enable or read-enable pulse, tw Data input with respect to write enable, t su ( D) Write select with respect to Setup times, high- or low-level data (see Figure 2) write enable, th(W) Data input with respect to write enable, th(D) i Hold times, high- or low-level data Write select with respect to (see Note 2 and Figure 2) write enable,:h(W) Latch time for new data, tlatch (see Note 3) MAX UNIT 5.25 V -2.6 rnA 8 rnA 25 25 ns 10 10 ns 15 15 ns 15 15 ns 5 5 ns 25 25 -55 Operating free·air temperature range, T A NOTES: NOM 125 0 ns 70 °e 1. Voltage values are with respect to network ground terminal. 2. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W) will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into., 3. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important only when attempting to read from a location immediately 'after that location has received new data. 1280 7·528 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 TYPES SN54LS670, SN74LS670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS REVISED DECEMBER 1980 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage Off-state output current, 10ZH high-level voltage applied Off-state output current, 10ZL II low-level voltage applied Vee; MIN, II; -18 mA Vee - MIN, VIH - 2 V, 10H; -1 mA 10H; -2.6mA VIH; 2 V, 10L; 4 mA VIL; VIL max Vee; MIN, IlL MIN 2 2 2.4 V 0.7 0.8 -1.5 -1.5 3.4 2.4 0.25 0.4 UNIT V V V 3.1 0.25 0.4 0.35 0.5 V Vee; MAX, VIH; 2V, VO;2.7V 20 20 Jl.A Vee; MAX, VIH; 2 V, Vo;O.4V -20 -20 Jl.A 0.1 0.1 GW 0.2 0.2 GR Any D, R, orW 0.3 0.3 Input current at Vee; MAX, maximum input voltage VI; 7 V High·level input current VI; 2.7 V Low-level input current SN74LS670 TYP:j: MAX MIN IOL;8 mA VIL; VIL max Vee; MAX, IIH SN54LS670 TYP:j: MAX TEST CONDITIONSt Vee; MAX, VI; 0.4 V lOS Short-circuit output current§ Vee; MAX lee Supply current Vee- MAX, Any D, R, orW 20 20 GW 40 40 GR Any D, R, orW 60 60 -0.4 -0.4 GW -0.8 -0.8 GR -1.2 -1.2 -130 -30 See Note 4 30 -30 30 50 mA Jl.A mA -130 mA 50 mA tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. :j:AII typical values are at VCC ; 5 V, T A ; 25° C. § Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. NOTE 4: Maximum ICC is guaranteed for the following worst-case conditions: 4.5 V is applied to all data inputs and both enable inputs, all address inputs are grounded and all outputs are open. switching characteristics, Vee = 5 V, TA = 25°e PARAMETER~ tpLH tpHL tpLH tpHL tPLH FROM (INPUT) TO (OUTPUT) Read select AnyQ Write enable AnyQ Data Any Q Read enable AnyQ TEST CONDITIONS eL;15pF, RL; 2 kn, See Figures 1 and 2 eL;15pF, RL; 2 kn, See Figures 1 and 3 tPHL tpZH tPZL tpHZ tpLZ MIN TYP MAX 23 40 25 45 26 45 28 50 25 45 23 40 eL;15pF, RL;2kn, 15 35 See Figures 1 and 4 eL; 5 pF, RL;2kn, 22 40 30 50 See Figures 1 and 4 16 35 UNIT ns • ns ns ns ns ~tpLH '" propagation delay time. low-to-high-Ievel output tpH L '" propagation delay time, h igh-to-Iow-Ievel output tpZH '" output enable time to high level tpz L '" output enable ti me to low level tpH Z '" output disable time from high level tpLZ '" output disable time from low level 130 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 7-529 I TYPES SN54LS670, SN74LS670 4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION TEST POINT 51 FROM OUTPUT UNDER TEST NOTES: --+----.-....... A. CL includes probe and jig capacitance. B. All diodes",re 1N916 or 1N3064. ISee Note BI LOAD CIRCUIT FIGURE 1 WRITE-SELECT INPUT WA or WB (See Note A) ~ I --I \-----------3V I 1.3 V r- tsu(W) ____+1_'" DATA INPUT 01,02,03, or 04 (See Note A) • --I 3v \. I 1.3 V \.._______________ oV I t j4- h(W) 11.3~ l I \+--I- tsu(D) I----.!- th(D) ________ ~ tw---+l WR ITE-ENAB LE INPUT GW ~1.3V l~~ __ _____ 3V oV 3V --OV I---- tlatch - - , READ-SELECT INPUT RA or RB (See Note B) ),.3V -----_----1 ~\.1-.3-V---------_: 1 1 !.- f-tPHL-J OUTPUT 01,02,03, or 04 tPLH : 1 I '--___...,1,·0:. __ VOH \1.3V VOL VOLTAGE WAVEFORMS (S1 AND S2 ARE CLOSED) NOTES: A. High-level input pulses at the select and data inputs are illustrated; however, times associated with low-level pulses are measured from the same reference points. B. When measuring delay times from a read-select input, the read-enable input is low. C. I nput waveforms are supplied by generators having the following characteristics: P R R .;; 2 MHz, Zout "" 50 n, duty cycle';; 50%, tr .;; 15 ns, tr .;; 6 ns. FIGURE 2 10· 7-530 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TYPES SN54LS670, SN74LS670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION '\----------- DATA INPUT D1, D2, D3, or D4 :~ WRITE-ENABLE INPUTGW OUTPUT 01,02,03, or 04 VOLTAGE WAVEFORM 1 IS1 AND S2 ARE CLOSED) 3V DATA INPUT D1, D2, D3, or D4 ~\.....--:3V_1-___________ _ OV WRITE-ENABLE INPUTGW ~-:~ ----- :: --.. . .;_____--11 Ir-----+ tpLH !-----+tPH L OUTPUT 01,02,03, or 04 I ----\j. _____ \'"~._3_V ____________ 3V __"I': ___ 0V VOLTAGE WAVEFORM 2 IS1 AND S2 ARE CLOSED) NOTES: A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with WA = RA and WB = RB' During the test GR is low. B. Input waveforms are supplied by generators having the following characteristics: PRR ..;; 1 MHz, Zout '" 50 .0., duty cycle";; 50%, tr ..;; 15 ns, tr ..;; 6 ns. FIGURE 3 READ~ ENABLE I '-------I WAVEFORM 1 (See Note A) I ----4" ~.>~--- tpz L - - t t----~4.5V Sl closed, ~ 1.3 V S2 open I. Sl open, S2 closed rtPLzi i I "---- ~ 1.3 V _ -- -- - 0V Sl and ¥___L I S2 closed ~ 1.5 V . : ' ,----VOL r--tPHZ-': 0.5 VO.5 V :--tPZH---! WAVEFORM 2 (See Note A) I ~3V 1.3V l\.: I--- • -----..,,:' ~0V ..J-----VOH '" r Sl and S2 closed '" 1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS NOTES: A. Waveforms 1 is for an output with internal conditions such that the output is low except when disabled by the read-enable input. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the read-enable input. B. When m""suring delay times from the read-enable input, both read-select inputs have been established at steady states. C. Input waveforms are supplied by generators having the following characteristics: PRR ..;; 1 MHz, Zout '" 50 .0., duty cycle";; 50%, tr ..;; 15 ns, tr ..;; 6 ns. FIGURE 4 877 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 7-531 • 7·532 JAN MIL-M-38S10 Integrated Circuits • 8·1 I MILITARY PRODUCTS MIL-M-38S10 AND MIL-STD-883 Military High-Reliability Integrated Circuits The Texas Instruments MIL-M-38SlO and MIL-STD-883 programs offer several options designed to meet system cost, reliability, lead time, and contract requirements. The following are the key features of the options available for MIL-M-38S1 0 and MIL-STD-883 Class B applications: SNC/MACH-IV (8838) JAN-Processed TI SNJ • Cost effective - approximately onethird the cost of JAN-Qualified IC"s • Produced under MIL-M-38510 guidelines with all chips manufactured in a DESC-certified front end facility • Tested per MIL-STD-883 method 5004 Class Band TI 38510/MACH-IV specification, Section 9 of this catalog • Produced under MIL-M-3851 0 guidelines with all chips manufactured in a DESC-certified front end facility • Fully tested per MIL-STD-883 method 5004 Class B • Includes device types covered hy MIL-M-3851O part numhers and circuits not yet covered hy MIL numhers • Electrical and mechanical characteristics per TI data sheets • Marked with 38510 part numhers where applicahle • Each lot includes Certificate of Conformance and Group A Summary Report • Approximately one-half the cost of JAN-Qualified IC"s -- • Tested per MIL-STD-883 method 5004 Class Band TI 38510/MACH-IV specification, Section 9 of this catalog • Electrical and mechanical characteristics per TI data sheets • Available in broad product spectrum including SSI, MSI, and LSI, both bipolar and MOS JAN -Qualified • Qualified per MIL-M-38510 Class B • Produced per MIL-STD-883 and MIL-M-38510 Class B and appropriate slash sheets • Produced in DESC-certified domestic production facility • Applicable devices and packages PRODUCT SERIES 54 TTL SERIES 54H TTL SERIES 54L TTL· SERIES 54LS TTL SERIES 54S TTL LINEAR CONTROL SERIES 55 INTERFACE MOS LSI LEAD FINISH B LEAD FINISH CID A CD E F G I J L T V W X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X • PER MIL·M-0038510B. Class S. 8-2 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 MILITARY PRODUCTS How to Order See Tables I, II and III for device, package and lead-finish cross-reference. • JAN-Processed/TI SNJ Device type covered by 38510 part number: Device SN5400J 883 Class B Order SNJ5400J SNJ5400J Marking { 385101001 04BCB Device type not covered by 38510 part number: Device SN54LS298J 883 Class B SNJ54LS298J Marking {SNJ54LS298J 38510B • SNC/MACH-IV Device Order Marking SNC5400J SNC5400J SNC5400J 883 Class B • JAN-Qualified Device Order Marking SN5400J 883 Class B JM38510100104BCB JM38510100104BCB Table I Part Numbers EXAMPLE: 5400 TIL NAND gate in ceramic dual-in-Iine package to 883 Class Bwith standard tin-plated leads. • JAN QUALIFIED • JAN PROCESSED/TI SNJ • SNC/MACH-IV SN t SN LEAD FINISH CASE OUTLINE JAN PACKAGE SNJ SHC/MACH ·IV 1/4" x 1/4" FLAT·14 1/4" x 1/8" FLAT·14 DIP-14 C 1/4" x 3/8" FLAT-14 0 E DIP-16 F 1/4" x 3/8" FLAT-16 G TO-99 H 1/4" x 1/4" FLAT-10 I TO·100 J DIP-24 K 3/8" x SIS" FLAT-24 L 3/8" x 1/2" FLAT·24 V DIP·18 W DIP-22 X TO-S Y TO·3 Z 1/4" X 3/S" FLAT-24 A BIT' MIL-M-38510 SLASH SHEET AND DEVICE TYPE SEE TABLE II & III • Per M I L-M-003851 OB, Class S. •• Finish Bar Cat TI's option. Devices will be marked Bar C as applicable. tpreflx designation for MOS/LSI is "SMC." § R denotes temperature range. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 u/FB T J W J W/SB L U L J W W JR § JR §- JAH C/O, SNJ TYPE SHC/MACH·IV SOLDER DIP 10 TIN-PLATE 00 GOLD-PLATE 00' OPTIONAL •• • 8-3 MILITARY PRODUCTS Screening - Class B SNJ JAN PROCESSED JAN QUALIFIED METHOD ROMT METHOD 2010.2 Cond B and38S10 1008.1 24 hrs min test Gond C 100% 2010.2 Cond B and 38510 1008.1 24 hrs min test Cond G SCREEN Internal Visual (Precap) Stabilization Bake Temperature Cycling Constant Acceleration Seal (a) Fine (bj Gross Interim Electrical • ROMT METHOD ROMT 2010.2 Cond B and 38510 1008.1 24 hrs min test Gond C 100% 1010.1CondC 2001.1 Gond E (min) in V, plane 100% 100% 100% 100% 1010.1 Cond C 2001.1 Gond E (min) in V, plane 100% 1014.1 100% 1014.1 100% 1014.1 (condC,) 100% JAN slash-sheet electrical specifications As applicable TI data sheet electrical specifications As applicable TI data sheet electrical specifications As applicable 101S.1 160hrs@ 12SoC min Burn-in test 100% SNC MACH-IV JAN slash-sheet electrical specifications 100% 100% 1010.ICondG 2001.1 Gond E (min) in V, plane 100% lOIS. 1 160hrs@ 12SoCmin 100% TI data sheet electrical specificalions Final Electrical Tests (a) Static tests (1) 2SoC (Subgroup 1. table 1. SOOS.3) (2) Max and min rated op. temperature (subgroups 2 and 3. table 1. 5005.3) (b) Dynamictests and switching tests 2SoC (subgroup 4 and 9. table 1. SODS. 3) (c) Functional test 2SoC (subgroup 7. table 1. SOOS.31 Qualification or quality conformance inspection SOOS.3 Class B per 38S1O SOOS3 Class B External Visual 2009.1 100% 2009.1 100% 100% 100% 100% 100% 100% 100% 100% 100% per 38S10 Note2 100% lOIS. 1 160hrs@ 12S"C mm TI data sheet electrical specifications 100% 100% 100% 100% Note 1 100% SOOS.3 Class B 2009.1 per 38S10 Note 2 100% NOTES: 1. Temperature guardband test may be used In lieu of 100% test for digital bipolar only. 2. Group A per 5005.3. Generic data available for groups S, C, and D. For MIL-M-38510/MIL-STD-883 Class A/S For critical space and satellite applications, SAMSO Class SIAN-Qualified TTL flat pack devices are available per MIL-M-00385 JOB including: CIRCUIT TYPE SN54LOOT SN54LOH SN54L02T SN54L04T SN54L 10T SN54L20T SN54L30T SN54L5H 8-4 JAN NO. JM38510/02004STO JM38510/02006STD JM38510/02701STD JM38510/02005STO JM38510/02003STD JM38510/02002STD JM38510/02001STD JM38510/04101 STD CIRCUIT CIRCUIT TYPE SN54L54T SN54L71T SN54L74T SN54L78T SN54L86T SN54L91T SN54L95T SN54L 121T SN54L 122T SN54L 164T SN5400T SN5401T TEXAS JAN NO. TYPE JAN NO. JM3851 0/041 04STD JM3851 0/021 01 STD JM38510/02105STD JM38510/02104STD JM3851 0/02601 STD JM3851 0/02806STD JM38510/02801STD JM38510/04201STD JM38510/04202STD JM38510/02802STD JM38510/00104STD JM38510/00107STD SN5402T SN5404T SN5410T SN5420T SN5440T SN5472T SN5473T SN5474T SN5493T SN5495T SN54121T SN54HOOT JM38510/00401STD JM3851 0/001 05STD JM3851 0/001 03STD JM38510/00102STD JM38510/00301STD JM3851 0/00201 STD JM38510/00202STD JM38510/00205STO JM3851 % 1302STO. JM38510/00901STD JM38510/01201 STD JM38510/02304STD INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 MILITARY PRODUCTS TABLE I. JAN INTEGRATED CIRCUITS AND CIRCUIT·TYPE CROSS-REFERENCE JAN INO. 00101 00102 00103 00104 00105 00106 00107 00108 00109 00201 00202 00203 00204 00205 00206 00207 00301 00302 00303 00401 00402 00403 00404 00501 00502 00503 00504 00601 00602 00603 00604 00701 00801 00802 00803 00804 00805 00901 00902 00903 00904 00905 00906 00907t 00908t 00909t 00910t 01001 01002 01003 01004 01005 01006 01007 01008 01009 01101 01102 01201 01202 01203 01204 01205 01301 01302 01303 01304 01305 01306 CKT TYPE 5430 5420 5410 5400 5404 5412 5401 5405 5403 5472 5473 54107 5476 5474 5470 5479:j: 5440 5437 5438 5402 5423 5425 5427 5450 5451 5453 5454 5482 5483 9304:j: 5480 5486 5406 5416 5407 5417 5426 5495 5496 54164 54165 54194 54195 9300:j: 9328 54198 54166 5442 5443 5444 5445 54145 5446 5447 5448 5449 54181 54182 54121 54122 54123 9601 9602 5492 5493 54160 54163 54162 54161 JAN INO. CKT TYPE 01307 01308 01309 01310t 01311t 01312t 01401 01402 01403 01404 01405 01406 01501 01502 01503 01504 01601 01602 01701 01702 01703t 01801 01901 02001 02002 02003 02004 02005 02006 02101 02102 02103 02104 02105 02201 02202 02203 02204 02205 02206 02301 02302 02303 02304 02305 02306 02307 02401 02501 02502 02503 02504 02505 02601 02701 02801 02802 02803 02804 02805 02806+ 02901 02902 02903 02904 02905 02906 02907 5490 54192 54193 54196 54197 54177 54150 9312:j: 54153 9309 54157 54151 5475 5477 54116 9314:j: 5408 5409 54174 54175 54173 54170 54180 54L30 54L20 54Ll0 54LOO 54L04 54 LO 1/54 L03 54L71 54L72 54L73 54L78 54L74 54H72 54H73 54H74 54H76 54Hl0l 54Hl03 54H30 54H20 54Hl0 54HOO 54H04 54HOl 54H22 54H40 54L90 54L93 54L193 93Ll0 93L16 54L86 54L02 54L95 54L164 93L28:j: 93LOO 76L70 54L91 54L42 54L43 54L44 54L46 54L47 76L42A 93LOl JAN INO. CKT TYPE JAN INO. 03001 03002 03003 03004 03005 03101 03102 03103 03104 03105 03201 03301 03302 03303 03304 03501 04001 04002 04003 04004 04005 04101 04102 04103 04104+ 04201 04202 04301 04401 04501t 04502t 04601 04602 04603 05001 05002 05003 05101 05102 05201 05202 05203 05204 05301 05302 05303 05401 05501 05502 05503 05504 05505 05601 05602 05603 05604 05605 05701 05702 05703 05704 05705 05706 05801t 06001 06002 06003 06004 15930 15935 15936 15946 15962 15932 15944 15957 15958 15933 15951 15945 15948 15950 9094 MH0026 54H50 54H51 54H53 54H54 54H55 54L51 54L54 54L55 54L54 54L121 54L122 93L18 93L24 93L14 93L08 93L09 93L12 93L22 4011A 4012A 4023A 4013A 4027A 4000A 4001A 4002A 4025A 4007A 4019A 4030A 4008A 4009A 4010A 4049A 4050A 4041A 4017A 4018A 4020A 4022A 4024A 4006A 4014A 4015A 4021A 4031A 4034A 4016A 10501:j: 10502:j: 10505:j: 10506:j: 06005 06006 06101 06102 06103 06104 06201 06202 07001 07002 07003 07004 07005 07006 07007 07008 07009 07010 07101 07102 07103 07104 07105 07106 07201 07301 07401 07402 07403 07501 07502 07601 t 07602t 07701t 07702t 07703t 07801 07802 07901 07902 07903 07904 07905 07906 07907 08001 08002 08003t 08004t 08101 08201 10101 10102 10103 10104 10105 10106 10107 10201 10202t 10203t 10301 10302 10303 10304 10305t 10401 10402 CKT TYPE 10507:j: 10509:j: 10531 :j: 10631 :j: 10576:j: 10535:j: 10504 10597 54S00 54S03 54S04 54S05 54S10 54S20 54S22 54S30 54S133 54S134 54S74 54S112 54S113 54S114 54S174 54S175 54S40 54S02 54S51 54S64 54S65 54S86 54S135 54S194 54S195 54S138 54S139 54S280 54S181 54S182 54S151 54S153 54S157 54S158 54S251 54S257 54S258 54S11 54S15 54S08 54S09 54S140 54S85 uA741 uA747 LM101A LM108A LH2101A LH2108A LMl18 uA723 LM104 LM105 uA710 uA711 LM106 LMlll LM2111 55107 55108 • NOTE: Only the basic JAN and commercial numbers are shown. t Slash sheets not released as of date of this publication. :j: Not recommended for new designs. + Class S only. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • OALLAS. TEXAS 75222 8-5 MILITARY PRODUCTS TABLE I. JAN INTEGRATED CIRCUITS AND CIRCUIT·TYPE CROSS·REFERENCE JAN. INO. 10403 10404 10405 10406 10407 10501t 10601 10602 10603t 10701 10702t 10703t 10704t 10801 10802 10901t 10902t 15001 15101 15102 15103 15201 15202 15203 15204 15205 15206 15301 15302 15401t 15501 15502 15503 15601 15602 15603 15701 15801 CKT TYPE 55114 55115 55113 7831 7832 uA733 LM102:j: LMll0 LM2110 LM109 LM140·12 LM140·15 LM140-24 3018A 3045 SE555 SE556 5485 5413 5414 54132 54154 54155 54156 8250 8251 8252 54125 54126 54120 54H08 54Hll 54H21 54147 54148 9318:j: 9338 9321 JAN. INO. 15802 15901 15902 16001 16101 16201 20101 20102 20103t 20201t 20202t 20301t 20302t 20401t 20402t 20501t 20502t 20601 t 20602t 23001t 23002t 23003t 23501 23502 23503 23504 30001 30002 30003 30004 30005 30006 30007 30008 30009 30101 30102 30103 CKT TYPE JAN. 9317 9300 9328 9334 5432 5428 54186 (PROM 512) MCM5304:j: IM5603A IM5603 (PROM 1024) IM5623 AM27S10 AM27S11 IM5604 IM5624 HHX7620-8 HMX7621·8 HMX7640-8 HMX7641-8 93410 (256 RAM) 93411 (256 RAM) 93421 TMS4060 (4K RAM) TMS4050 (4K RAM) TMS4060 (4K RAM) TMS4050 (4K RAM) 54LSOO 54LS03 54LS04 54LS05 54LS10 54LS12 54LS20 54LS22 54LS30 54LS73 54LS74 54LSl12 CKT TYPE JAN. INO. 30104 30105 30106 30107 30108 30109 30110 30201 30202 30203 30204 30301 30302 30303 30401 30402 30501 30502 30601t 30602t 30603t 30604t 30605t 30606t 30607t 30701t 30702t 30703t 30704t 30801 30901t 30902t 30903t 30904t 30905t 30906t 30907t 30908t 54LSl13 54LSl14 54LS174 54LS175 54LS107 54LS109 54LS76 54 LS40 54LS37 54LS38 54LS28 54 LS02 54LS27 54LS266 54LS51 54LS54 54LS32 54LS86 54LS194 54LS195 54 LS95 54LS96 54LSl64 54LS295 54LS395 54LS138 54LS139 54LS42 54LS47 54LS181 54LS151 54LS153 54LS157 54LS158 54LS251 54LS257 54LS258 54LS253 31001 31002 31003 31004 31101 31201t 31202t 31301 31302 31303 31401t 31402t 31403t 31501t 31502t 31503t 31504t 31505t 31506t 31507t 31508t 31509t 31510t 31511t 31512t 31513t 31601t 31602t 31701 t 31702t 31801t 31901t 32001 t 32002t 32003t 32004t 32102t • NOTE: Only the basic JAN and commercial numbers are shown. t Slash sheets not released as of date of this publication. :j: Not recommended for new designs. B·6 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 INO. CKT TYPE 54LSll 54LS15 54LS21 54LS08 54LS85 54LS83A 54LS283 54LS13 54LS14 54LS132 54LS123 54LS221 54LS122 54LS90 54LS93 54LS160 54LS161 54LS168 54LS169 54LS192 54LS193 54LS191 54LS92 54LS162 54LS163 54LS190 54LS75 54LS279 54LS124 54 LS324 54LS261 54LS670 54LS196 54LS197 54 LS290 54LS293 54LS26 MILITARY PRODUCTS TABLE II. CIRCUIT·TYPE AND JAN INTEGRATED CIRCUITS CROSS·REFERENCE TTL 54 SERIES CKT JAN TYPE IND. 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5412 5413 5414 5416 5417 5420 5423 5425 5426 5427 5428 5430 5432 5437 5438 5440 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5453 5454 5470 5472 5473 5474 5475 5476 5477 5480 5482 5483 5485 5486 5490 5492 5493 5495 5496 54107 54116 54120 54121 54122 54123 54125 54126 00104 00107 00401 00109 00105 00108 00801 00803 01601 01602 00103 00106 15101 15102 00802 00804 00102 00402 00403 00805 00404 16201 00101 16101 00302 00303 00301 01001 01002 01003 01004 01006 01007 01008 01009 00501 00502 00503 00504 00206 00201 00202 00205 01501 00204 01502 00604 00601 00602 15001 00701 01307 01301 01302 00901 00902 00203 01503 15401t 01201 01202 01203 15301 15302 JAN CKT TYPE IND. 15103 01005 15601 15602 01401 01406 01403 15201 15202 15203 01405 01303 01306 01305 01304 00903 00904 00910t 01703t 01701 01702 01312t 01901 01101 01102 20101 01308 01309 00905 00906 01310t 0131lt 00909t 54132 54145 54147 54148 54150 54151 54153 54154 54155 54156 54157 54160 54161 54162 54163 54164 54165 54166 54173 54174 54175 54177 54180 54181 54182 54186 54192 54193 54194 54195 54196 54197 54198 TTL 54H SERIES CKT JAN TYPE IND. 54HOO 54HOl 54H04 54H08 54Hl0 54Hll 54H20 54H21 54H22 54H30 54H40 54H50 54H51 54H53 54H54 54H55 54H72 54H73 54H74 54H76 54Hl0l 54Hl03 02304 02306 02305 15501 02303 15502 02302 15503 02307 02301 02401 04001 04002 04003 04004 04005 02201 02202 02203 02204 02205 02206 TTL 54LSEAIES CKT JAN TYPE IND. 54LOO 54LOl 54L02 54L03 54L04 54L10 54L20 54L30 54L42 54L43 54L44 54L46 54L47 54L51 54L54 54L54 54L55 54L7l 54L72 54L73 54L74 54L78 54L86 54L90 54L91 54L93 54L95 54L121 54L122 54Ll64 54L193 02004 02006 02701 02006 02005 02003 02002 02001 02901 02902 02903 02904 02905 04101 04102 04104. 04103 02101 02102 02103 02105 02104 02601 02501 02806. 02502 02801 04201 04202 02802 02503 TTL 54LSSERIES CKT JAN TYPE IND. 54LSOO 54LS02 54 LS03 54 LS04 54LS05 54 LS08 54LS10 54LSll 54LS12 54LS13 54LS14 54LS15 54 LS20 54LS21 54 LS22 54LS26 54LS27 54LS28 54LS30 30001 30301 30002 30003 30004 31004 30005 31001 30006 30301 31302 31002 30007 31003 30008 32102t 30302 30204 30009 CKT TYPE JAN 54 LS32 54 LS37 54LS38 54 LS40 54 LS42 54LS47 54LS51 54LS54 54LS73 54 LS74 54LS75 54 LS76 54 LS83A 54 LS85 54 LS86 54 LS90 54 LS92 54 LS93 54LS95 54 LS96 54LS107 54LS109 54LSl12 54LS113 54LSl14 54LS122 54LS123 54LS132 54LS138 54LS139 54LS151 54LS153 54LS157 54LS158 54LS160 54LS161 54LS162 54LS163 54LSl64 54LS169 54LS174 54LS175 54LS181 54LS190 54LS191 54LS192 54LS193 54LS194 54LS195 54LS196 54LS197 54LS221 54LS251 54LS253 54LS257 54LS258 54LS261 54SL266 54LS279 54LS283 54LS290 54LS293 54LS295 54 LS324 54LS395 54LS670 30501 30202 30203 30201 30703t 30704t 30401 30402 30101 30102 31601t 30110 31201 31101 30502 3150lt 3151lt 31502t 30603t 30604t 30108 30109 30103 30104 30105 31403t 31401t 31303 30701t 30702t 30901t 30902t 30903t 30904t 31503t 31504t 31510t 31512t 30605t 31506t 30106 30107 30801 31509t 31513t 31507t 31508t 30601t 30602t 32001 t 32002t 31402t 30905t 30908t 30906t 30907t 31801t 30303 31602t 31202t 32003t 32004t 30606t 31702t 30607t 31901t IND. • NOTE: Only the basic JAN and commercial numbers are shown. tSlash sheets not released as of the date of this publication. tNot recommended for new designs• • Class S only. 1280 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 8·7 MILITARY PRODUCTS TABLE II. CIRCUIT·TYPE AND JAN INTEGRATED CIRCUITS CROSS·REFERENCE TTL 54S SERIES CKT JAN TYPE INO. • 54S00 54502 54503 54504 54505 54508 54509 54510 54511 54515 54520 54522 54530 54540 54551 54564 54565 54574 54585 54586 545112 545113 545114 545133 545134 545135 545138 54S139 54S140 54S151 545153 545157 545158 54S174 545175 54S181 545182 545194 545195 545251 54S257 545258 545280 07001 07301 07002 07003 07004 08003t 08004t 07005 08001 08002 07006 07007 07008 07201 07401 07402 07403 07101 08201 07501 07102 07103 07104 07009 07010 07502 07701t 07702t 08101 07901 07902 07903 07904 07105 07106 07801 07802 07601t 07602t 07905 07906 07907 07703t LINEAR CONTROL SERIES JAN CKT TYPE INO. MOS LSI CKT TYPE TM54050 TM54050 TM54060 TM54060 JAN INO. 23502 23504 23501 23503 (4K (4K (4K (4K RAM) RAM) RAM) RAM) LM101A LM104 LM105 LM106 LM108A LM109 LMlll LMl18 LM140·12 LM140·15 LM140·21 5E555 5E556 uA710 uA711 uA723 uA733 uA741 uA747 10103 10202t 10203t 10303 10104 10701 10304 10107 10702t 10703t 10704t 10901t 10902t 10301 10302 10201 1050lt 10101 10102 LINEAR INTERFACE SERIES JAN CKT TYPE INO. 55107 55108 55113 55114 55115 10401 10402 10405 10403 10404 NOTE: Only the basic JAN and commercial numbers are shown. tSlash sheets not released as of date of this publication. 128 8·8 TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 38510/MACH IV High-Reliability Microelectronics Procurement Specifications MIL-STD-883 • 9-1 CONTENTS PAGE SECTION 1.0 2.0 3.0 4.0 5.0 6.0 • 9·2 SCOPE APPLICABLE DOCUMENTS GENERAL REQUIREMENTS QUALITY ASSURANCE PROVISIONS PREPARATION FOR DELIVERY NOTES. 9-4 9-4 9-6 9-16 9-29 9-29 J REVISIONS CLASSIFICATION (MAJOR/MINOR) • DATE CODE EFFECTIVITY LTR DATE DESCRIPTION Major 7040 A Incorporate MI L-M-38510 and Revision Notice 2 of MIL-STD-883 Major 7239 B Incorporate Revision Notice 3 and 4 of M I L-STD-883 and Revision A of M I L-STD-3851 0 Major 7401 C Incorporate revised Level IV (SNH) processing with inclusion of recorded electrical data with delta requirements; incorporate technological criteria in Table III for precap of complex circuits. APPROVED 8/15/70 ~.Jf.!o.s ~~ 1/1/74 r.v/ t:.~;rJJ 'fI~ 1"'- 1--, ~} f:\ Minor 7518 4/15175 Incorporate Revision A of M I L-STD-883 and provisions for MOS LSI and CMOS devices 0 .. w~ it L/,,\'... '--j;. i) ( "),), . ~ rXUt! Minor 7628 E Incorporate Revision C of MI L-M-3851 0 and MI L-STD-883 Revision A, Notice 2 6/15176 ~~l~ :;rr ~'.f V-<" ,") ...~ ~ I II TOLERANCES 0 ANGLES! 1 3 PLACE DECIMAL i.DID 2 PLACE DECIMAL i.D2 ~ TEXAS INSTRUMENTS INCORPORATED SEMICONDUCTOR CIRCUITS DIVISION DALLAS, TEXAS TITLE INTERPRET DWG. IN ACCORDANCE WITH STD. DESCRIBED IN MIL·STD-IDD MICROELECTRONICS, HIGH RELIABILITY PROCUREMENT SPECIFICATION (MIL-STD 38510/883) MATERIAL: CIRCUITS 01 I,ISION, MANAGER "/ ~~~ AI SCALE I REV 0 I SHEET 9-3 385l0/MACH IV PROCUREMENT SPECIFICATION 38510/MACH IV PROGRAM 1.0 SCOPE 1.1 This specification establishes standards for materials, workmanship, performance capabilities, identification, and processing of high-reliability monolithic integrated circuits. 1.2 Intent The intent of this document is such as to recognize that quality and reliability are built into, not tested into, a product. There is no specification or screening procedure that can substitute for inherent, built-in reliability. However, it must be realized that irrespective of lot quality, there will always be some small percentage of devices that are subject to early failure (infant mortality). A well engineered screening procedure will eliminate most, if not all, of these early failures. Secondly, the screening and acceptance testing described herein will also serve to demonstrate, with a high degree of statistical confidence, that the required levels of quality and reliability have, in fact, been built into the product. 2.0 APPLICABLE DOCUMENTS 2.1 The following specifications and standards, of the issue in effect on the date of invitation for bids or request for proposal, form a part of this specification to the extent specified herein: 2.2 Specifications Military M I L-M-55565 MIL-M-38510 9-4 Microcircuits, Packaging of Microcircuits devices, general specification for TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION 2.3 Standards Military MIL·STD-105 Sampling Procedures and Tables for Inspection by Attributes MI L-STD-883 Test Methods and Procedures for Microelectronics MI L-STD-790 Reliability Assurance Program for Electronic Parts Specification MIL-STD-1276 Leads, Weldable, for Electronic Components Parts MIL-STD-1313 Microelectronics Terms and Definitions Detail Specifications SNXXXX (Bipolar) TMSXXXX (MOS LSI) TFXXXX (CMOS) 2.4 Detail Specification for a Particular Part Type (e.g., Manufacturer's Data Sheet) Precedence of Documents For the purpose of interpretation, in case of any conflicts, the following order of precedence shall apply: 2.5 a) Purchase Order -The purchase order shall have precedence over any referenced specification. b) Detail Specification -The detail specification shall have precedence over this specification and other referenced specifications. c) This Specification - This specification shall have precedence over all referenced specifications. d) Referenced Specifications -Referenced Specifications shall apply to the extent specified herein. II I Federal and/or military specifications and standards required shall be obtained from the usual government sources. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9-5 38510/MACH IV PROCUREMENT SPECIFICATION 3.0 GENERAL REQUIREMENTS The individual item requirements shall be as specified herein and in accordance with the applicable detail specification. In the event of any conflict between the requirements of this specification and the detail specification, the latter shall govern. The static and dynamic electrical performance requirements of the integrated circuits plus absolute maximum ratings and test methods shall be as specified in the detail specifications. 3.1.1 3.1.2 Definitions a) LTPD Lot Tolerance Percent Defective shall be as defined by MIL-M-38510. b) A Lambda, stated in percent per 1000 hours as defined by MIL-M-38510. c) MRN Minimum reject number as defined by MI L-M-38510. d) Production Lot For the purpose of this specification, a production lot shall be defined per MIL-M-38510. e) Inspection Lot An inspection lot shall be as defined in MIL-M-38510. f) C Acceptance number as defined by M I L-M-3851 O. Terms and Definitions Terms and definitions shall be as defined in MIL-STD-1313. 3.1.3 Classification of Requirements The requirements for the integrated circuits are classified herein as follows: II 9·6 Requirement Paragraph Process Conditioning, Testing and Screening 3.2 Qualification 3.3 Design and Construction 3.4 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 385l0/MACH IV PROCUREMENT SPECIFICATION Marking of Integrated Circuits 3.2 3.5 Product Assurance 3.6 Workmanship 3.7 Performance Capabilities 3.8 Quality and Reliability Assurance Program Plan 3.9 Process Conditioning, Testing and Screening Three levels of screening and quality assurance for integrated circuits are provided for in this specification. Process conditioning, testing and screening shall be as specified in 4.3 and the applicable figure for the appropriate quality assurance level stated on the purchase order and defined as follows: SCREENING LEVEL 38510/883 Class A (Level IV) 38510/883 Class B (Level III) 38510/883 Class C (Level I) 3.3 PART NUMBER PREFIX BIPOLAR CMOS MOS LSI Not Avail. SNH Not Avail. TFC SNC SMC SNM TFM Not Avail. APPLICABLE FLOWCHART Figure 4 Figure 3 Figure 2 Figure 1 Qualification Vendor qualification for delivery of integrated circuits to this specification shall be as specified in paragraph 4.2. 3.4 Design and Construction Integrated circuit design and construction shall be in accordance with the requirements specified herein and in the applicable detail specification. 3.4.1 Topography Integrated circuits furnished under this specification shall have topography information available for review by procuring activity. The information made available shall provide sufficient data for thorough circuit design, application, performance, and failure analysis studies. 3.4.1.1 II Monolithic Die Topography An enlarged photograph or drawing (to scale) with a minimum magnification of 80 times the die (chip) size showing the topography of elements formed on the silicon monolithic die shall be available for review. This shall be identified with the specific detail integrated circuit part-type in which it is used and the applicable detail specification. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 15222 9·7 II CQ Co w CO ---U1 Q OPERATIOfl 3: APPLICABLE PARAGRAPH l> OPERATION C"") :: <: ~ :IJ Q C"") C :IJ m ~ 3: [TI m »>< (JJ m Z ..... en m - o z_ ~8Z ~~(IJ . 0-i ~;C ~ m SHIP C"") "'" ~c: C"") l> 03:: ..... [TI Q z Z -i (IJ SHIP FIGURE 1-FLOW CHART FOR 38510 CLASS C LEVEL I FIGURE 2-FLOW CHART FOR MOS LSI 38510 CLASS B (LEVEL III SMC) OPERATION APPLICABLE PAR'AGRAPH OPERATION APPLICABLE PARAGRAPH ,.~ g rr1 -< ~ w >< > ~ (J) ~ z_ CO -= U"I -... ~8Z ~~(J) 3: > . 0-i ~;o ~c::: n :::c <: 03:: rr1 ""C z = o c = 3: SHIP -i n (J) m m SHIP Z ..... en ""C m n .." n FIGURE 3-FLOW CHART FOR 38510 CLASS B LEVEL III FIGURE 4-FLOW CHART FOR 38510 CLASs A LEVEL IV > ..... o z co cD II 38510/MACH IV PROCUREMENT SPECIFICATION 3.4.1.2 Die Intraconnection Pattern An enlarged photograph or drawing (to scale) with a minimum magnification of 80 times the die (chip) size showing the specific intraconnection pattern utilized to intraconnect the elements in the circuit. This shall be in the same scale as the die topography 3.4.1.1 so that the elements utilized and those not being used can easily be determined. 3.4.2 Materials Materials shall be inherently non-nutrient to fungus and shall not blister, crack, outgas, soften, flow or exhibit other immediate or latent defects that adversely affect storage, operation or environmental capabilities of integrated circuits. 3.4.2.1 Material Selection Materials selected for use in the construction of the integrated circuits shall be chosen for maximum suitability for the application. This shall include consideration of the best balance for: 3.4.2.2 a) Electrical performance b) Thermal compatibility and conductivity c) Chemical stability including resistance to deleterious interactions with other materials d) Metallurgical stability with respect to adjacent materials and change in crystal configuration e) Maximum stability with regard to continued uniform performance through the specified environmental conditions and life. Foreign Materials No lacquer, grease, paste, desiccant or other similar foreign encapsulant or coating material shall be included in the circuit enclosure nor applied to any part of the internal circuit assembly. II 3.4.3 Mechanical 3.4.3.1 Case Each integrated circuit shall be securely mounted and hermetically sealed within a case designed and constructed to conform to the outline and physical dimensions shown in the detailed specification. 9·10 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION 3.4.3.2 Interconnections Interconnections within the integrated circuit case shall be minimized and there shall be no wire crossovers. Circuit intraconnections by means of wire jumpers shall not be used. (See Note 6.2) 3.4.3.3 Leads Lead material, construction, and outline shall be as specified on the detail specification and shall be capable of meeting the solderability test of MI L-STD-883, Method 2003. (See note 6.4). 3.4.3.3.1 Lead Size Lead outline and dimensions shall be as specified in the detail specification. 3.4.3.3.2 Lead Surface Condition Leads shall be free of the following defects over their entire length when inspected under a minimum of 4X magnification: a) Foreign materials adhering to the leads such as paint, film, deposits and dust. Where adherence of such foreign materials is in question, leads may be subjected to a clean, contaminant-free (e.g., oil, dust, etc.), filtered air stream (suction or expulsion) of 88 feet per second maximum, or a wash/rinse as necessary and reinspected. b) Nicks, cuts, scratches or other surface defacing defects which expose the base metal. 3.4.3.3.3 Lead Straightness Leads shall be aligned within a O.050-inch diameter; O.050-inch length cylinder concentric to the point of lead emergence from the case and the X-axis (the axis parallel to the lead axis). Along the remaining lead length, there shall be no unspecified bend whose radius is less than 0.10 inch and no twist whose angle is greater than 30° (ribbon leads, only). II I 3.4.3.3.4 Preformed Leads Preformed leads, when specified, shall be in accordance with the detail specification. The part number of the integrated circuit shall remain as specified in the applicable detail specification or purchase order, the applicabte suffix designation shall appear on the purchase order but shall not be marked on the device. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9-11 385l0/MACH IV PROCUREMENT SPECIFICAT~ON 3.4.3.3.5 Carriers (Mech-Pak Carrier) Carrier-matrix assemblies consisting of individually mounted integrated circuits shall be furnished when so specified by purchase order. The individual carriers shall have provisions for use with automatic test equipment contacts. Devices supplied "clipped-out" of the Mech-Pak Carrier shall be supplied in the Barnes Carrier type 029-188 or equivalent. (Applicable to Flat Packs only.) 3.5 Marking of Integrated Circuits 3.5.1 Legibility All marking shall be permanent in nature and remain legible when subjected to specified operating, storage, and environmental requirements. All markings shall be insoluble in standard solvents such as trichlorethylene, water and xylene. 3.5.2 Marking Details Marking of the integrated circuits shall be located as follows unless otherwise specified in the detail specification: 3.5.3 a) TO-99, TO-100, and similar "can" cases shall be marked on the top of the case. Where space limitations exist, the side of the case may be used. b) Flat Packs shall be marked on the top of the case. Where space limitation exists, the bottom of the package may be utilized as necessary. As a minimum the top of the package shall show the manufacturer's identification mark or symbol, the device part number, date code, and pin 1 orientation mark (where applicable). c) Dual-in-line plug-in packages shall be marked in the same manner as flat packs. Required Device Marking a) Index point indicating the starting point for numbering of leads shall be as indicated in the detail specification. The indexing point may be a tab, color dot, or other suitable indicator. b) Manufacturer's identification mark or symbol. c) A lot date code indicating the week of initial submission for screening or inspection. The date code shall be as follows: II 1) 9·12 EIA four-digit date code, the first two numbers shall be the last two digits of the year, the last two numbers shall indicate the calendar week. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • CALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION 2) d) EIA three-digit date code (when limited by space available), the first number shall be the last digit of th~ year, the last two numbers shall indicate the calendar week. Manufacturer's part number defining circuit type and applicable MIL-STO-883 screening level and MIL-M-38510 product assurance level as defined in paragraph 3.2. e) Individual device serial number is required for Class A (SNH). f) A dot to indicate acceptance by Radiographic inspection. NOTE: When a color dot is used to identify pin one, the radiographic inspection acceptance dot shall be placed on the bottom of the package. g) 3.6 Country of origin shall be per U.S. Customs codes. Product Assurance The manufacturer shall establish and maintain a reliability assurance program that complies with the basic intent of MIL-STD· 790. Furthermore, it is intended that each integrated circuit delivered shall be free of any defect in design, material, manufacturing process, testing and handling, which would degrade or otherwise limit its performance when used within the specified limits. 3.6.1 Visual and Mechanical Examination Integrated circuits shall be examined to verify that material, design, construction, physical dimensions, marking and workmanship are in accordance with the specified acceptance criteriu. 3.6.2 Test Equipment The manufacturer shall prepare and maintain a current list, by name and drawing number or other unique identification, of test. equipment used in the manufacturing and testing of devices submitted for acceptance inspection under this specification. This list shall be made available to the procuring activity representative upon request. 3.6.3 II Process Controls Each integrated circuit shall be constructed by manufacturing processes which are under the surveillance of the manufacturer's Quality Control department. The processes shall be monitored and controlled by use of statistical techniques in accordance with published specifications and procedures. The manufacturer shall prepare and maintain suitable documentation (such as quality control manuals, inspection instructions, control charts, etc.) covering all phases. of incoming part and material inspection and in-process inspections required to assure that product quality meets the requirements of this specification. The TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9·13 385l0/MACH IV PROCUREMENT SPECIFICATION procuring activity may verify, with the permission of and in the company of the manufacturer's designated representative, that suitable documentation exists and is being applied. Information designated as proprietary by the manufacturer will be made available to the procuring activity or its representative only with the written permission of the manufacturer. Process control is recognized as being vital to the concept of "built-in" quality. The process control program shall include a scanning electron microscope (SEM) monitor program for evaluating the metal integrity over oxide step and oxide step contour. The SEM analysis will be defined in a Quality & Reliability Assurance document. 3.6.4 Production Changes The manufacturer shall advise the procuring activity of the time at which any major change(s) in production or QC methods or documentation become effective during the period of device production for delivery against any given purchase order referencing this specification. 3.7 Workmanship Integrated circuits shall be manufactured and processed in a careful and workmanlike manner, in accordance with the production processes, workmanship instructions, inspection and test procedures, and training aids prepared by the manufacturer in fulfillment of the reliability assurance program established by paragraph 3.6. 3.7.1 Personnel Certification The manufacturer shall be responsible for training, testing and certification of personnel involved in producing integrated circuits. Training shall be commensurate and consistent with the requirements of this specification and in conformance to the basic intent of MI L-STD-790. Training aids in the form of satisfactory criteria shall be available for operator and inspector review at any time. 3.7.2 Personnel Evaluation The supplier shall maintain a continuous evaluation of the proficiency of personnel concerned with production and inspection. Retraining of an operator or inspector shall be required when this evaluation establishes that a degree of proficiency necessary to meet the requirements of this specification is not being exercised. 9-14 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 385l0/MACH IV PROCUREMENT SPECIFICATION 3.7.3 Rework provisions 3.7.3.1 Rework All rework on micorcircuits manufactured under this specification shall be accomplished in accordance with paragraph 3.7.1 of MI L-M-3851 a as defined herein. 3.7.3.2 Rebonding Rebonding shall be in accordance with MI L-M-38510, as defined herein (see Note 6.5) 3.8 Performance Capabilities The integrated circuits delivered to this specification shall be designed to be capable of meeting the environmental requirements specified in Table II. The manufacturer need not perform these tests specifically for the contract or specification, but shall provide data which demonstrates the ability of the integrated circuits to pass the environmental tests. The data shall have been generated on devices from the same generic family as the circuits being supplied to this specification, and the package configuration shall be the same as for the delivered parts (i.e., Flat Pack, TO-100, etc.). 3.9 Quality and Reliability Assurance Program Plan The manufacturer shall establish and implement a Quality and Reliability Assurance Program Plan that meets the intent of M I L-M-3851 0, Appendix A. Submission of the program plan to the procuring activity shall not be a requirement of this specification; however, the program plan shall be maintained by the manufacturer and shall be available for review by the procuring activity. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9·15 385l0/MACH IV PROCUREMENT SPECIFICATION 4.0 QUALITY ASSURANCE PROVISIONS 4.1 Responsibility for Inspection Unless otherwise specified in the contract or purchase order, the manufacturer is responsible for the performance of all inspection requirements specified herein. Except as otherwise specified, the manufacturer may utilize his own facilities or any commercial laboratory acceptable to the procuring activity. The procuring activity may, at its discretion, perform any of the inspections set forth in the specification where such inspections are deem~ necessary to assure supplies and services conform to prescribed requirements. 4.1.1 Inspection and Testing Procedures Coverage Inspection and testing processes and procedures prepared in fulfillment of the reliability assurance program established per paragraph 3.6 shall be prescribed by clear, complete and current instructions. These instructions shall assure inspection and test of materials, work in process and completed integrated circuits as required by this specification. In addition, criteria for approval and rejection of materials and integrated circuits shall be included. 4.1.2 Inspection at Point of Delivery The procuring activity may, at its discretion, reinspect any or all of the delivered parts excluding Groups B, C-; and D destructive samples as defined 'by MI L-STD-883. All parts found to be defective, excluding devices exhibiting damage from use, may be returned to the manufacturer at the manufacturer's expense. 4.1.3 Inspection Records The manufacturer shall maintain a reliability data and records library. This library shall have on file, for review by the procuring activity, records of examination, qualification test results, variables data (when required) and all other pertinent data generated on devices manufactured to this specification. I 4.1.4 Control of Procurement Sources The manufacturer shall be responsible for assuring that all supplies and services conform to this specification, the detail specification and the manufacturer's procurement requirements. 9-16 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION 4.1.4.1 Manufacturer's Receiving Inspection Purchased supplies shall be sUbjected to inspection after receipt as necessary to ensure conformance to contract requirements. In selecting sampling plans, consideration shall be given to the controls exercised by the procurement source and evidence of sustained quality conformance. 4.1.4.2 The manufacturer shall provide procedures for withholding from use all incoming supplies pending completion of required tests or receipt of necessary certification or test records and their evaluation. 4.1.4.3 The manufacturer shall initiate corrective action with the procurement source depending upon the nature and frequency of receipt of nonconforming supplies. 4.1.5 Procuring Activity Quality Assurance Representative The procuring activity, may, at its discretion, place quality assurance representatives in the manufacturer's plant as deemed necessary to assure conformance to contract requirements in any non·proprietary phase of design, fabrication, processing, inspection, and testing of the integrated circuits being produced. The manufacturer shall provide reasonable facilities and assistance for the safety and convenience of such personnel in the performance of their duties. Inspection and test procedures shall be made available for review by the quality assurance representative. 4.2 Qualification and Quality Conformance Inspection 4.2.1 Qualification When specifically called out and funded on the purchase order or contract, the manufacturer's specific device qualification shall be based on compliance with the quality conformance test per Table III for MOS LSI devices. Qualification for other technologies shall be per Table I except that the testing will be to one LTPD level tighter than as defined in Table 8-1 of MIL-M-38510. For 38510 Class A (Level IV), qualification shall be per M I L-STD-883, Method 5005, Table Ila. 4.2.1.2 I Procedures and Definitions 4.2.1.2.1 Sampl ing Procedure Device selection for the qualification procedure of 4.2.1 shall be based on a random sampling technique and will be selected from a generic family. TEXAS INCORPORATED INSTRUMENTS POST OFFICE sox 5012 • DALLAS. TEXAS 75222 9-17 38510/MACH IV PROCUREMENT SPECIFICATION 4.2.1.2.2 Generic Family Electrically and structurally similar devices shall be said to comprise a generic family (e.g., TTL) if they meet the following criteria: 4.2.2 a) Are designed with the same basic circuit-element configuration such as TTL, TTL Schottky, DTL, CMOS, MOS metal-gate, or MOS silicon-gate, and differ only in the number or complexity of specified circuits that they contain. Generic family for linear circuits is defined by circuit function (e.g.,op amp, comparator, etc.). b) Are designed for the same supply, bias and signal voltage, and for input/output capability with each other under an established set of loading rules. c) Are enclosed in housings (packages) of the same basic construction (e.g., hermetically sealed flat packages, dual-in-line ceramic, dual-in-line plastic) and outline, differing only in the number of active housing terminals included and/or utilized. Quality Conformance Inspection Quality conformance inspections (Groups B,'C, and D) are per Tables I and II. Table II shall apply to MOS LSI and Table I to other technologies. a) When specifically called out and funded on the purchase order or contract, the manufacturer shall perform the quality conformance inspections (Groups B, C, and D) on a lot-by-Iot basis. b) The manufacturer shall, upon request, make available for review the following generic quality conformance inspection and data: Group B - To be performed every six weeks on each package type (a different number of pins constitutes a different package) at each assembly location. Group C - To be performed every three months on each generic family as defined in 4.2.1.2.2a and b. I Group D - To be performed every six months on each package type (a different number of pins constitutes a different package) at each assembly location. 4.2.2.1 Lot Acceptance Sampling Statistical sampling for quality conformance inspections shall be in accordance with MI L-M-38510 Table B-1. Group B samples shall be selected from sublots that have successfully completed all of the 100% processing steps specified on the applicable process flow chart. 9-18 TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 385l0/MACH IV PROCUREMENT SPECIFICATION 4.2.2.2 Resubmission of Failed Lots When any lot (paragraph 4.2.2.a) submitted for quality conformanca inspection fails any subgroup requirement, it may be resubmitted a maximum of one time for that particular subgroup. This additional submission is permitted, provided an analysis is performed to determine the failure mechanism for each reject device in the subgroup, and that it is determined that .the failures are due to one of the following: 4.2.2.3 a) Testing error resulting in electrical damage to devices b) A defect that can effectively be removed by rescreening the lot c) Random defects that do not reflect poor basic device designs or poor workmanship. Early Shipments When quality conformance inspection is being performed for a specific contract or purchase order, the accepted Group A devices that are awaiting shipment pending successful completion of Groups B, C, and D shall be stored and controlled by Quality Assurance. Under no circumstances shall such parts be shipped prior to the successful completion of the Group B tests. 4.2.2.4 Groups B, C, and D Test Data All lot-by-Iot data generated by Groups B, C, and D testing when specifically called out and funded on the purchase order, shall accompany the initial shipment of devices. This data shall consist, at a minimum, of the following: 4.2.2.5 a) Attributes data for Group B. Endpoints for the subgroups are visual per the applicable MI L-STD-883 test method. b) Attributes data for Groups C and D. Endpoints for each subgroup are electrical test parameters as defined in Tables I and II. Precedure in Case of Test Equipment Failure or Operator Error Where an integrated circuit is believed to have failed as a result of faulty test equipment or operator error, the failure shall be entered in the test record which shall be retained for review along with a complete explanation verifying why the failure is believed to be invalid. If it is determined that the failure is invalid, a replacement integrated circuit from the same inspection lot may be added to the sample. The replacement integrated circuit shall be subjected to all those tests to which the discarded integrated circuit was submitted prior to its failure, and any remaining specified test to which the discarded integrated ,circuit was not subjected prior to its failure. 4.3 Quality Assurance Processing, Methods and Procedures This section establishes the test methods and conditions to be used for the 100010 processing (screening) requirements specified by the applicable process flow chart. 4.3.1 Precap Visual Inspection Each microcircuit shall be required to pass the appropriate precap visual inspection defined as follows. Precap Lot Acceptance shall be per paragraph 4.6. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9-19 38510/MACH IV PROCUREMENT SPECIFICATION 4.3.1.1 38510 Class C (Level I) and 38510 Class B (Level III) devices shall be visually inspected in accordance with MI L-STD-883, Method 2010, Condition B. 4.3.1.2 38510A Class A (Level IV) devices (designated for NASA type applications) shall be visually inspe'cted in accordance with MIL-STD-883, Method 2010, Condition A. (See notes 6.1.1.1 and 6.1.1.2.) (See notes under 6.1.2 for MOS LSI devices.) 4.3.1.3 Complex MSI and LSI circuits as defined in M I L-STD-883, Method 5004, paragraph 3.3 may be precap inspected per MIL-STD-883, Method 5004, paragraph 3.3.1 for ,38510 Class B (Level III) and paragraph 3.3.2 for 38510 Class C (Levell). 4.3.2 Stabilization Bake The purpose of this test is to determine the effect' on microelectronic devices of baking at elevated temperatures without electrical stress applied. Test shall be performed in accordance with MI L-STD·883, Method 1008, Condition C. 4.3.3 Thermal Shock The purpose of this test is to determine the resistance of the device to sudden exposure to extreme changes in temperature. Test shall be performed in accordance with MI L-STD-883, Method 1011, Condition A. 4.3.4 Temperature Cycle This test is conducted for the purpose of determining the resistance of a part to exposures to extremes of high and low temperatures, and to the effect of alternate exposures to these extremes, such as would be experienced when equipment or parts are transferred to and from heated shelters in arctic areas. Test shall be performed in accordance with MI L-STD-883, Method 1010, Condition C, for a minimum of 10 cycles. For MSI and LSI comples devices as defined in MI L-STD-883, Method 5004, paragraph 3.3, 50 cycles may be used in lieu of alternate pre-cap visual inspection criteria. 4.3.5 (Deleted) 4.3.6 Centrifuge (Constant Acceleration) The centrifuge test is used to determine the effects on microelectronics devices of a centrifugal force. This test is designed to indicate structural and mechanical weaknesses not necessarily detected in shock and vibration tests. Test shall be performed in accordance with MI L-STD-883, Method 2002, Condition E for devices having 20 or less pins and Condition D for those having more than 20 pins. 9-20 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION 4.3.7 Fine Leak Test Each integrated circuit for 38510 Class C (Level I), 38510 Class B (Level III), and 38510 Class A (Level IV) screens shall be subject to a fine leak test in accordance with paragraph 4.3.7.1 or 4.3.7.2. The method shall be optional providing it is consistent with and capable of detecting the specified leak rate of the applicable process flow chart. 4.3.7.1 Helium Leak Test Helium leak test shall be Method 1014, Condition A. 4.3.7.2 performed in accordance with MI L-STD-883, Radiflo Leak Test Radiflo leak test shall be performed in accordance with M IL-STD-883, Method 1014, Condition B. Krypton 85 bomb pressure and dwell time are a function of the radioactivity level and shall be selected so as to conform to the equations given in Condition B. 4.3.8 Gross-Leak Test Each integrated circuit for 38510 ClassC (Levell), 38510 ClassB, (Level II!) and 38510 Class A (Level IV) screens shall be subjected to the appropriate gross-leak test of paragraph 4.3.8.1 or 4.3.8.2, or an approved equivalent. The manufacturer may, at his option, perform gross-leak testing after the Set I Electrical Tests of paragraph 4.3.9. 4.3.8.1 When specifically called out and funded on the purchase order or contract, units will be bombed 2 hours minimum at 30 psig in FC-78, or equivalent. Units will then be immersed in FC-40 or equivalent at +125°C ±5°C for 30 seconds minimum and observed for for a definite stream of bubbles, more than two large bubbles, or an attached bubble that grows in size, per MIL-STD-883, Method 1014, Condition C2. 4.3.8.2 Units will be immersed in FC-40 or equivalent at +125°C ± 5°C for 30 seconds minimum and observed for a definite stream of bubbles, or more than two large bubbles per MI L-STD-883, Method 1014, Condition C1. 4.3.9 II Final Electrical Test (Set I) I Each integrated circuit shall be required to pass the electrical requirements of the data sheet. The manufacturer shall also perform such additional testing necessary to assure the parts will meet the temperature extreme limits. MOS LSI memory devices will be 100% tested both at 25°C and at high temperature. Linear circuits will be 100% dc tested at high and low temperatures and 25°C. When specifically called out and funded on the purchase order or contract, the manufacturer shall perform subgroups 2, 3, and 4 of paragraph 4.4 in accordance with Method 5004 of M I L-STD-883. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9-21 38S10/MACH IV PROCUREMENT SPECIFICATION 4.3.10 Burn-I n The burn-in screen is performed for the purpose of eliminating'marginal devices and early-life failures. Device biasing shall be in accordance with MI L-STD-883 Method 1015, Conditions A, D, or E for Digital Circuits and Conditions B, C, or D for Linear Circuits. For 38510 Class B (Level III) devices, equivalent test conditions using the time/temperature acceleration factor of Condition F between the temperature range of 125°C to 150°C may be used. For 38510 Class B (Level III) MSI and LSI complex devices as defined in MI L-STD-883 paragraph 3.3.1, a 240 hour burn-in in lieu of alternate pre-cap visual inspection criteria per MI L-STD-883, Method 5004, paragraph 3.3.1 may be used. 4.3.11 Final Electrical Test (Set II) Each 38510 Class A (Level IV) integrated circuit shall be required to pass the electrical requirements of the detail specifications. The following tests shall be performed as a minimum: dc parameters at maximum and minimum rated temperatures, and switching parameters at 25 D C. In addition, each bipolar device shall have critical 25°C, dc electrical parameters read and recorded by serial number and shall pass the following delta requirements: DELTA LIMIT PARAMETER ±10% of detail ± 10% of detail ± 10% of detail ±10% of detail VOL VOH IlL IIH specification specification specification specification limit limit limit limit CMOS recorded parameters and delta limits will be defined by the manufacturer as required. One copy of the pre-burn-in and post-burn-in recorded data with delta calculations shall be shipped with each lot. Data will not be available for the metal flat pack (T). See MIL-M-0038510, Class S. The manufacturer may, when deemed necessary, elect to perform additional electrical testing over and above the requirements stated herein. II 4.3.12 Radiographic Inspection (X-Ray) Test shall be performed in accordance with MI L-STD-883, Method 2012. X-ray may be performed at any point after serialization at the manufacturer's option (see note 6.3). 4.3.13 External Visual Inspection 4.3.13.1 The purpose of this examination is to verify that materials, construction, marking, and general workmanship are as specified. Examination shall be in accordance with MIL-STD-883, Method 2009. 9·22 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 385l0/MACH IV PROCUREMENT SPECIFICATION 4.3.13.2 Visual inspection will be performed for catastrophic failures. Catastrophic failures are defined as missing leads, broken packages, and damaged lids. 4.3.14 Voltage Stress Selected n-channel MOS LSI devices will be voltage stressed for 40 hours minimum at 25°C min per MIL-STD-883 Method 1015, Condition D. 4.4 Group A Conformance Group A conformance shall consist of the electrical parameters in the manufacturer's data sheet. If an inspection lot is made up of a collection of sublots, each sublot shall conform to Group A, as specified. SUBGROUP LEVEL I 38510C Subgroup 1 LTPD LEVEL II ,%) LEVEL III 38510B 5 5 LEVEL IV 38510A 5 25"C. de Subgroup 2 High Temperature. de 10 10 5 Subgroup 3 10 10 5 10 10 5 Low Temperature. de Subgroup 4 Dynamic and Switching Tests @ 25"C NOTES: Functional tests included in dc tests. MOS LSI devices will be lot accepted at 2SoC and high temperature. The LTPO's of subgroups 1 and 2 will apply. 4.5 Certification The manufacturer shall include a certificate of compliance with each shipment of parts if requested on the purchase order. This certificate shall indicate that all specified tests and requirements of this specification have been made.or met, and that the lot of devices (identified by lot and/or batch number) is acceptable. The certificate shall bear the name and signature of the manufacturer's Quality Control representative, the date of acceptance or signing, and any pertinent notes as applicable. 4.6 I II Precap Lot Acceptance After each precap inspection the lot of devices shall be sampled by quality control and inspected for the specified visual criteria. TEXASINCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 9-23 38510/MACH IV PROCUREMENT SPECIFICATION TABLE 1 QUALITY CONFORMANCE TEST (GROUPS B, C, D) MIL-STD-883 TEST CONDITION GROUP B1I Subgroup 1 Physical dimensions 2016 2 devices (no failures) Subgroup 2 a. Resistance to solvents 2015 3 devices (no failures) 1 device (no failures) 15 b. I nternal visual and mechanical c. Bond strengthY (1) Thermocompression (2) Ultrasonic or wedge Subgroup 3 Solderabil ity;V 2014 Failure criteria from design and construction requirements of applicable procurement document. 2011 (1) Test condition D (2) Test condition D 2003 Soldering temperature of 260 ± 1QoC. 15 1. Electrical reject devices from the same insp.ection lot may be used for all subgroups when end-point measurements are not required. 2. Test samples for bond strength may, at the manufacturer's option unless otherwise specified,be randomly selected following internal visual (precap) inspection specified in method 5004, prior to sealing. 3. All devices submitted for solderability test must have been through the temperature/time exposure specified for burn-in. The L TPD for solderability test applies to the number of leads inspected except in no case shall less than 3 devices be used to provide the number of leads required. GROUP C (Die Related Tests) Subgroup 1 Operating life test End point electrical parameters Subgroup 2 Temperature cycling Constant acceleration Seal II (a) Fine 1005 Test condition to be specified (1000 hours) As specified in the applicable device specification 5 1010 2001 Test condition C Test condition E min. (see 3) Yl axis followed by one other axis X or Z. As applicable 15 1014 (b) GrossV' Visual examination ~~~irlt_electrical 11 As specified in the applicable device specification parameters 1. Visual examination shall be in accordance with method 1010. 2. When fluorocarbon gross-leak testing is utilized, test condition C2 shall apply as minimum. 9-24 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 38510/MACH IV PROCUREMENT SPECIFICATION TABLE 1 QUALITY CONFORMANCE TEST (GROUPS B, C, 01 (continuedl MIL-STD-883 TEST CONDITION METHODI CLASSES B, C LTPD GROUP 0 (Package Related Testl Subgroup 1 Physical dimensions Subgroup 211 Lead integrity Seal (al Fine Y (bIGross'J./ Subgroup 31/ Thermal shock Temperature cycling Moisture resistance Seal (al Fine Y (bl Gros~;V Visual examination End point electrical parameters Subgroup 441 Mechanical shock Vibration variable frequency Constant acceleration Seal (al Fine Y (bl GrossY Visual examination End point electrical parameters Subgroup 511 Salt atmosphere Visual examination 2016 15 2004 1014 Test condition 82 (lead fatiguel As applicable 15 1011 1010 1004 1014 Test condition 8 as a minimum, 15 cycles minimum. Test condition C, 100 cycles minimum. 15 As applicable ~ As specified in the applicable device specification. 2002 2007 2001 1014 Test condition 8 Test condition A Test condition E (see 3) As appl icable 15 W 5005 Subgroups 1,2,3, and 7. 1009 Test condition A. Omit initial conditioning 15 J./ 1. 2. 3. 4. Electrical reject devices from the same production lot may be used for samples. Condition A or B per paragraph 3.7 herein. When fluorocarbon gross leak testing is utilized; test condition C2 shall apply as minimum. Devices used in subgroup 3, "Thermal and Moisture Resistance", may be used in subgroup 4, "Mechanical". 5. Visual examination shall be in accordance with method 1010 or 1011 at a magnification of 5X to lOX. 6. Visual examination shall be performed in accordance with method 2007 f6r evidence of defects or damage to case, leads, or seals resulting from testing (not fixturing). Such damages shall cohstitute a failure. 7. Visual examination shall be in accordance with paragraph 3.3.1 of method 1009. TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 II 9-25 38510/MACH IV PROCUREMENT SPECIFICATION TABLE II QUALITY CONFORMANCE TEST MOS LSI CIRCUIT MIL-STD-883 TEST CONDITIONS METHOD LTPD Subgroup 1 Temperature Cycle 1010 Condition C Constant Acceleration Electrical End Points 2001 5005 Condition 0 1 , Y 1 Plane Subgroup 1 15 Subgroup 2 Operating Life 1005 Condition D, 500 Hrs_ Minimum Electrical End Points 5005 Subgroup 1 1_ Condition 0 for packages with more than 20 pins_ Condition E for packages with 20 pins or less_ • 9·26 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 10 38510/MACH IV PROCUREMENT SPECIFICATION TABLE III MANUFACTURER'S QUALIFICATION PROCEDURE MOS LSI CIRCUITS TEST MIL·STD·883 CONDITION CLASSES B, C . LTPD GROUP B Subgroup 1 Physical dimensions 2016 2 devices (no failures) ~stance to solvents 2015 b. I nternal visual and mechanical 2014 3 devices (no failures) 1 device (no failures) c. Bond strengthY (1) Thermocompression (2) Ultrasonic or wedge 2011 Subgroup 2 Subgroup 3 Solderabi IityJl Failure criteria from design and construction requirements of applicable procurement document. 15 (1) Test condition D (2) Test condition D 2003 Soldering temperature of 260 ±lOoC. 15 1. Electrical reject devices from the same inspection lot may be used for all subgroups when end-point measurements are not required. 2. Test samples for bond strength may, at the manufacturer's option unless otherwise specified, be randomly selected following internal visual (precap) inspection specified in method 5004, prior to sealing. 3. All devices submitted for solderability test must have been through the temperature/tim~ exposure specified for burn·in. The LTPD for solderability test applies to the number of leads inspected except in no case shall less than 3 devices be used to provide the number of leads required. GROUP C (Die Related Tests) Subgroup 1 Operating life test End point electrical parameters Subgroups 1,2,3, and 7 Subgroup 2 Temperature cycling Constant acceleration = 85°C, 1000 hours minimum 1005 5005 TA 1010 2001 Test condition C Test condition E for package with <20 pins Test condition D for packages with ;;:;'20 pins Yl axis followed by one other axis X or Z. 1014 As applicable 5 15 • I Seal (a) Fine (b) GrossV Visual examination End-point electrical parameters 11 As specified in the applicable device specification 1. Visual examination shall be in accordance with method 1010. 2. When fluorocarbon gross-leak testing is utilized, test condition C2 shall apply as minimum. TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 9-27 38510/MACH IV PROCUREMENT SPECIFICATION TABLE III MANUFACTURER'S QUALIFICATION PROCEDURE MOS LSI CI RCUITS (continued) TEST MIL·STD·883 CONDITION GROUP D (Package Related Test) Subgroup 1 Physical dimensions Subgroup 211 Lead integrity Seal (a) FineY (b) Gross;U Subgroup 341 Thermal shock Temperature cycling Moisture resistance Seal (a) Fine~ (b) Gross;!' Visual examination End point electrical parameters Subgroup 411 Mechanical shock Vibration variable frequency Constant acceleration Seal (a) FineY (b) Gross;U Visual examination End point electrical parameters • 9·28 Subgroup 51/ Salt atmosphere Visual examination 2016 15 2004 1014 Test condition B2 (lead fatigue) As applicable 15 1011 1010 1004 1014 Test condition B as a minimum,15 cycles minimum Test condition C, 100 cycles minimum. 15 As applicable l/li/ As specified in the applicable device specifications. 2002 2007 2001 1014 Test condition B Test condition A Test condition E (see 3) As applicable 15 :b!Y 5005 Subgroups 1,2,3, and 7. 1009 Test condition A. Omit initial conditioning fVu 1. 2. 3. 4. 5. Electrical reject devices from the same production lot may be used for samples. Condition A or B per paragraph 3.7 herein. When fluorocarbon gross leak testing is utilized; test condition C2 shall apply as minimum. Devices used in subgroup 3, "Thermal and Moisture Resistance", may be used in subgroup 4, "Mechanical". Visual examination shall be in accordance WitH mathod 1010 or 1011 at a magnification of 5X to 10X. 6. Visual examination shall be performed in accordance with method 2007 for evidence of defects or damage to case, leads, or seals resulting from testing (not fixturing). Such damages shall constitute a failure. 7. Visual examination shall be in accordance with paragraph 3.3.1 of method 1009. TEXAS INCORPORATED (NSTRUMENTS POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 15 38510/MACH IV PROCUREMENT SPECIFICATION 5.0' PREPARATION FOR DELIVERY 5.1 Final Visual Shipping Inspection Each lot of microcircuits and its associated documentation shall be sampled by Quality Control and visually inspected for the following: 5.2 a) Scratched, nicked or bent leads b) Damaged header (packages) c) All test data specified in section 4.0 d) Certificate of Compliance as specified in section 4.0 e) All other pertinent documentation required and specified by this specification. Packing Requirements Parts shall be packed in containers of the type, size, and kind commonly used which will ensure acceptance by common carriers and safe delivery at the destination and in accordance with MI L-M-55565, Level C, bulk pack. The containers shall be clearly marked with manufacturer's name or symbol. 5.3 Preservation and Package Identification The package shall be marked with the following: The country of origin if other than U.S.A. Procuring activity parts number Purchase order number Material nomenclature Quantity Lot number II Date code This information shall appear on the label or shall be directly marked on each container. Method is optional. 6.0 NOTES 6.1 Precap Visual Method 2010 The following criteria may be in conflict with the circuit design topology and construction techniques of some microcircuit manufacturers. Where such a conflict does exist, the inspection criteria listed herein may be waived. (Reference paragraph 3.0 of MIL-STO-883, Method 2010). TEXAS INSTRUMENTS INCORPORATED POST OFFICE BOX 5012 • DALLAS, TEXAS 75222 9-29 38510/MACH IV PROCUREMENT SPECIFICATION 6.1.1 Preseal Visual Inspection, Test Condition B [38510 Class B (Level III) and 38510 Class C (Levell)]. 6.1.1.1 Paragraph 3.2: a 20·PSI minimum blow-off prior to seal will be performed to meet the intent of a controlled environment. 6.1.1.2 For titanium-tungsten, gold, titanium-tungsten multilayered systems, the underlying metal is defined as the bottom titanium tungsten and the top layer is defined as gold. 6.1.2 Preseal Visual Inspection for MaS LSI devices (38510 Class B, level III SMC). When the alternate screening option of paragraph 3.3 of Method 5004 is applied, the following additional items are applicable: 6.1.2.1 Internal visual, Method 2010, Condition B: In addition to the changes indicated by paragraph 3.3.1 of Method 5004, the following additional clarifications and deletions are applicable as reflected in MIL-M-3851 0/235: 6.2 a) Metallization inspection shall be applicable to the top layer metal conductor (i.e., AI) and need not include "underlying conductors" such as poly-silicon. b) Omit paragraphs 3.2.1.1 (b) through 3.2.1.1 (e), 3.2.1.2 (b) through 3.2.1.2 (e) and 3.2.3 (e) (Items 3.2.1.1 (f) and 3.2.3 (g) do not apply). Interconnections Circuit interconnections (metallization pattern) shall be designed so that no properly fabricated connection shall experience a current density greater than 5 X 105 amperes/cm 2 , including allowances for worst-case conductor composition, normal production tolerances on design dimensions, and nominal thickness at critical areas such as contact windows. 6.3 X-Ray Method 2012 Paragraph 3.9.2.2a(2) and (3) delete and replace with: "Cause for rejection shall be a single void in the bar attachment material opening two adjacent sides and exceeding 50% of the length of one side and 100010 of the length of the other side." II 6.4 Salt Atmosphere Test, Method 1009 Where package design considerations necessitate (such as 0.75-inch tip-to-tip metal flat packs), there may be a conformal coating applied prior to the salt atmosphere test. 6.5 Rebonding Attempts to bond where only impressions have been made in the metal and where the bond did not make a physical attachment to the pad or post shall not be considered evidence of rebonding. 9-30 TEXAS INCORPORATED INSTRUMENTS POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 Ie Sockets and Interconnection Panels II 10-1 IC SOCKETS AND INTERCONNECTION PANELS Texas Instruments lines of off-the-shelf interconnection products are designed specifically to meet the performance needs of volume commercial applications_ They provide both the economy of a standard product line and performance features developed after many year's experience with custom designs. Foremost among these is our ability to selectively bond a wrought gold stripe at the contact point. No waste. Reduced cost. Reliable contacts. Wrought Gold Contact Plate a contact with gold and you get a better contact. More reliable, longer lasting. Increase the gold, you improve the contact. But gold is precious, so improved performance has to be costly - right? Wrong. Because now you can get the gold only where it is needed - at the point of contact. How? With selective metallurgical bonding; a gold stripe inlay. Not porous plating, but durable wrought gold bonded to the contact by the same technology used to produce clad coins and thermostat metals. Texas Instruments, Attleboro, Massachusetts, is the world's largest producer of these multimetal systems. We also know our way around electronics. The result? A full line of reliable, low cost, interconnection systems featuring an extra measure of gold where it's needed. Premium performance at no premium in price. IC Sockets Texas Instruments family of IC sockets includes every type and size in common use today, and as wide a choice of contact materials as you'll find anywhere_ Choose from open or closed entry wire-wrapped t sockets, standard or low profile solder tail sockets, cable plugs, and component platforms. Sizes from 8 to 40 pins. IC Panels To match the industry's broadest line of IC sockets TI offers one of the industry's widest selections of off-the-shelf socket panel products. Logic panels. Logic cards_ Accessories. Add TI's custom design capability and wire wrapping for full service. Additional information including pricing and delivery quotations may be obtained from your nearest TI Distributor, TI Representative, or: • 10-2 Texas Instru ments Incorporated Connector Systems Department MS 2-16 Attleboro, Massachusetts 02703 Telephone: (617) 222-2800 TELEX: ABORA927708 t Registered trademark of Gardner-Denver LOW PROFILE SOCKETS SOLDER TAIL C-93 SERIES GOLD-CLAD CONTACTS C-83 SERIES TIN-PLATED CONTACTS • Universal mounting and packaging • Anti-wicking wafer • Stand-off tabs on base for solder flush • Redundant contact points for low contact resistance, high reliability and repetitive insertion • Closed entry construction MATERIAL: A. Body-glass filled nylon (GFN) B. Contact-copper nickel alloy C. Finish·see part number schedule IDENTIFICATION NOTCH 1[:: f:'~Nn TOLERANCE ~ NON-CUMULATIVE 100 1--.TYP. PART NO. SCHEDULE NOTES: A. Sockets meet requirements of Te~as Instruments test specification TS-OOOS and test report TR·0003 B. Operating temperature -6SoC to ±lS0°C C. Contacts have redundant spring elements D. Accommodates standard.IC leads up to .024" square, rectangular, or .024" diameter E. Contact is designed and oriented in the plastic body to generate maximum possible contact pressure F. Socket is designed to achieve maximum density on boards G. Sockets may be mounted end to end on .100" centers continuous line or on AOO" centers row to row H. Socket is designed to prevent IC leads from contacting P.C. board I. Closed entry feature provided to facilitate automatic IC insertion and protects the IC leads against damage rl=W~ ~~ .007 ,- I-- X --l NOMEX ANTI-WICKING WAFER Pins C·93 SERIES -C-83 SERIES 8 C930810 C830810 14 C931410 C831410 16 C931610 C831610 18 C931810 C831810 20 C932010 C832010 22 C932210 C832210 24 C932410 C832410 28 C932810 C832810 40 C934010 C934010 CONTACT FINISH C-93 SEAlES: 100 mlcroinch minimum gold stripe inlay C-83 SEAlES: 200 microinch minimum bright tin plate .JOMAX .150 MAX , BLACK BODY :m IC LEAD GUARD 8 Pin 14 Pin 16 Pin 18 Pin 20 Pin 22 Pin 24Pin 28 Pin Dimension X ±.OOS .300 .300 .300 .300 .300 0400 .600 .600 .600 Dimension V ±.01O 0400 .700 .800 .900 1.000 1.1 00 1.200 10400 2.000 Dimension W (max) 0400 0400 0400 .400 0400 .SOO .700 .700 .700 II 40 Pin 10·3 STANDARD PROFILE SOCKET SOLDER TAIL C-82 SERIES PLATED CONTACTS • C-92 SERIES GOLD CLAD CONTACTS WIRE WRAP C-S1 SERIES PLATED CONTACTS • C-91 SERIES GOLD CLAD CONTACTS • • • • Designed for low cost, reliable, high density production packaging Universal mounting and packaging capabilities S to 40 pin lead configur~tions Contacts accommodate _015" through _024" rectangular or round dual-in-line leads • Wire wrap posts held to true position of _015" providing a true position of _020" on boards for efficient automatic wire wrapping WIRE WRAP IDENTIFICATION FOOPINNO.~ frE1;~rr I§I_~I§I 1§I~ I . .6. Tot.. -.[1001- SOLDER TAIL -T·1I~®®.8 I 8 81 • • 18 8 • aja 8 w ·NON·CUMULATIVE ITYP I III -1.100 - _.. iTYP . MATERIAL: NOTES: A. Body-glass filled nylon (GFN) B. Contact-phosphor bronze per 00-B-750 (C-811 copper nickel alloy (C-91) C. Finish-see part number schedule A. Sockets meet requirements of Texas Instruments test specification TS-0003 and test report TR-0001 B. Contacts are replaceable C. Contacts have redundant spring elements D. Cover is removeable E. Contact is designed and oriented in the plastic body to generate maximum possible contact pressure F. Operating temperature -65°C to +150°C 8 Pin Dimension V ±0.10 Dimension W (max) Dimension X ±.005 Dimension Y ±0.1 0 Dimension Z ±.005 10-4 ala .465 .400 .300 NA .280 14 Pin .765 .400 .300 .400 .280 16 Pin .865 .400 .300 .400 .280 G. Sockets are designed to achieve maximum density on boards and may be mounted .400" row to row centers H. Closed entry cover is provided to facilitate automatic insertion and protect IC leads against damage I. Accommodates standard Ie leads up to .024" square, rectangular or .024" dia. J. Contact retention - 7 Ibs. min. K. Sockets are capable of being automatically or semiautomatically wire wrapped 18 Pin 20Pin .965 .400 .. 300 1.065 .400 .300 .400 .280 .400 .280 24 Pin 1.280 .700 .600 .500 .280 28 Pin 1.480 .700 .600 .500 .280 36 Pin 1.845 .700 .600 .800 .325 40 Pin 2.045 .700 .600 1.000 .325 WIRE WRAP PART SCHEDULE Finish Series C-81 200-400 microinch min tin per MIL-T-l0727 Pins C-91 50.microinch min gold stripe inlay PART Black Contact Cover Finish 8 C810854 C810804 14 C811454 C811404 16 C811654 C811604 18 C811854 C811804 20 C812054 C812004 24 C812454 C812404 28 C812854 C812804 36 Series C-82 30 microinch min gold per MIL-G-45204 over 50 microinch min nickel per QQ-N-290 C813604 C814004 8 C910850 C910800 14 C911450 C911400 16 C911650 C911600 18 C911450 C911400 20 C912050 C911800 24 C912450 C912000 28 C912850 C912800 8 C820850 14 C821450 C821400 16 C821650 C821600 18 C821850 C821800 24 C822450 C822400 28 C822850 C822800 SCHEDULE Body Series C-82 50 microinch min gold per MIL-G-45204 over 100 microinch min nickel per QQ-N-290 Pins Black Body 36 C913600 Series C914000 C-82 200-400 microinch min tin per MIL-T-l0727 C823600 C824000 8 C820852 C820802 14 C821452 C821402 16 C821652 C821602 18 C821852 C821802 24 C822452 C822402 28 C822852 C822802 C823602 36 C824002 C820854 C820804 14 C821454 C821404 16 C821654 C821604 18 C821854 C821604 24 C822454 C822404 28 C822854 C822804 8 C823604 36 C-92 100-microinch min gold stripe inlay C820800 40 40 Series Black Cover 36 40 40 CLOSED ENTRY '" NUMBER Black 40 Series OPEN ENTRY CLOSED ENTRY II II NUMBER Contact ., SOLDER TAIL OPEN ENTRY C824004 8 C920850 C920800 14 C921450 C921400 16 C921650 C921600 18 C921850 C921800 24 C922450 C922400 28 C922850 C922800 36 C923600 40 C924000 10-5 SOCKET PANELS STANDARD 04 SERIES • 180 position panel or multiples of 30 position with 14 or 16 position socket pattern • I/O - 4 rows with 13 pins per row or 3 - 14 pin sockets • Low cost standard hardware • Available in 98 standard series • Off-the-shelf availability t------------16.175 (180 PATTEHN) t--------------15.800 -----------t --------------i t - - - - - - - - - - - - 1 3 . 1 0 0 ----------~ 1---------10.400 PIC BOARD MATERIAL lIB th ick Glass Epoxy, 2 oz. Copper Circuitry both sides, Tin Plated ---------l fr .290 MAX. ,.125 . i .187 l-l lAs I SO. I I, I 6.875 IGRPI.II.III) I 7.475 IGRPIV) Ie ~ .~5REF. SEATING PLANE THRU HOLE FOR VCC PLANE CONNECTION TYP. 6 PLACES (WRAP SIDE) NOTE: Dimensions shown are nominal. Detail information and tolerances available on request (indicate series and group number!. STANDARD SOCKETS C·Bl or C·91 series, 14 pin or 16 pin, closed entry sockets as designated in the Part No. Schedule at right. See pages 7 and B for complete socket information. 10-6 ca1 SERIES SOCKETS Body ••••.•••• Glass filled nylon Contact .... Phosphor bronze per QQ·B·750 Finish ....... 30.microinch min. gold per MIL·G-45204 over 50 microinch min. nickel per QQ·N·290 C·Sl SERIES SOCKETS Body ......... Glass filled nylon Contact .... Copper nickel alloy Finish ....... 50 microinch min. gold stripe inl~y STANDARD PANEL PART NO. SCHEDULE -04 Series Group No. 110 Option ~~ ~~ ca1 Sockets C·91 Sockets 30 60 90 120 150 180 0411211 0411212 0411213 0411214 0411215 0411216 0411231 0411232 0411233 0411234 0411235 0411236 30 60 90 120 150 180 0411411 0411431 0411412 0411432 0411413 0411433 0411414 0411434 0411415 0411435 0411416 0411436 30 60 90 120 150 180 0434211 0434231 0434212 0434232 0434213 0434233 0434214 0434234 0434215 0434235 0434216 0434236 30 60 90 120 150 180 0434411 0434412 0434413 0434414 0434415 0434416 0434431 0434432 0434433 0434434 0434435 0434436 30 60 90 120 150 180 0423211 0423212 0423213 0423214 0423215 0423216 0423231 0423232 0423233 0423234 0423235 h423236 30 0423411 60 0423412 90 0423413 120 0423414 150 0423415 180 0423416 0423431 0423432 0423433 0423434 0423435 0423436 30 60 90 120 150 180 0444211 0444212 0444213 0444214 0444215 0444216 0444231 0444232 0444233 0444234 0444235 0444236 30 60 90 120 150 180 0444411 0444412 0444413 0444414 0444415 0444416 0444431 0444432 0444433 0444434 0444435 0444436 ,j~ Group I 14 Pin PIN 14 .... vee PIN 7 ...... GRD ~:: •'~• • 12 11 • 10 II 2 • 3 • FEED·THRU PINS 5 • II II •• •• • • • -- SOCKETS 7 , Group II 14 Pin PIN V .....• vee PIN G ...... GRO ~': G~ •• •• •• •• • • • 13 • 12 • 11 • 10 1 2 3 • 5 • 7 • Group III 16Pin P,IN 16 .•.. vee PIN 8 ...... GRO ~:: • I. • • 13 12 • J1 • 10 •• ,...., II IS I. 13 • 11 12 III III SOCKETS II II II • 5 7 • 16Pin GK!> I • 2 • 3 • 5 '-" FEED-THRU PINS • ~t~ 3 •• • • •• • •• •• 10 II FEED-THRU PINS 2 PIN V ...... vee PIN G ...... GRO ~ • • - SOCKETS •• •• • •• 1 Group IV ~v II II 7 • .~ II II SOCKETS II FEED-THRU PINS • 10-7 SOCKET CARDS STANDARD D02 SERIES • Low Cost • 14 - 16 pin socket pattern 60 position • Standard ground and power pin commitment • 8 standard designs o Mates with dual 60 position edge connector 002 Series PIC BOARO MATERIAL 1/16 and 1/8 thick Glass Epoxy. 2 oz. Copper Circuitry both sides. Tin Plated STANDARD CARD PART NO. SCHEDULE Group No. PIN 14 .... vec PIN 7 ..... GRO , .02' sa. I I ~".~ ·."..... • • 11 II 2 , • II I. Group II I IlL .&40 REF. NOTE: Oimensions shown are nominal. Oetail information and tolerances available on request (indicate series and group numberl. 00 Series ~ ~1.500~ 10-8 Z501201 (1/16") 1/8" 0021110 0021130 1/16" 0022310 0022330 14 Pin .... ~ ~ ~" • U MULTIPURPOSE CARD PART NO. SCHEDULE I/O - II Board Thk. Part No. 1/16" 2012510 1/8" 2011510 I • • 11 J • n 4 • • ·. . ." • I EJECTOR KEYS Material: Nylon Part no. Z501200 (1/8") 1/16" 0022110 0022130 • • PIN V ..... VCC PIN G ..... GRO I ADAPTER Part no. Z501300 C-91 Sockets • • , i I III C-81 Sockets 14 Pin Group I OI-t Board Thk. I I , Group III ~.11....•~ • II • ,. • 1) Group IV II • • II I 0021210 0021230 1/16" 0022410 0022430 , 16 Pin 1 • 2. .11 .• • 1/8" • • ~"Po ·.11,. ..J. I. " II 0022210 0022230 •• I PIN V ..... vec PIN G ..... GRO • • 1/16" 2 • J ·.. .., " 0021310 0021330 16 Pin PIN 16 .... vee PIN 8 ...... GRO .11 1/8" • • '~ '. 1/8" 0021410 0021430


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