1981_Western_Digital_Product_Handbook 1981 Western Digital Product Handbook

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1981 PRODUCT
HANDBOOK

WESTERN DIGITAl.
CORPORATION

WESTERN DIG6TAl
PRODUCT HANDBOOK

Making The leading Edge Work For You
This is our first complete Product Handbook and, naturally, we're
proud of it. We're proud of the products detailed in these pages. We're
proud of our people, who have taken these products from concept to
market. And we're proud of the hundreds of Western Digital customers
who have used these products to achieve a competitive advantage in
their own markets.
The rate of innovation in this industry is breathtaking. And Western
Digital has played an important role in the microelectronic revolution.
Our guiding principle though, goes beyond extending the limits of the
leading edge; we're dedicated to making the leading edge work. The
proof is in our products.
And like our products, this handbook has been designed with you in
mind. We've gone to great lengths to make it complete, accurate and
useful. Now we would like your critical appraisal, to help us improve it.
And our products. Let me hear from you directly. Or use the postcard
at the back at this handbook.

/~
---::/? ~//
7

//d'

L--~

~~ __

-----.,.

Charles W. Missler
Chairman of the Board
President and Chief Executive Officer

lEDGE HNDEX
TELECOMMUNICATIONS DIVISION

COMPUTER PRODUCTS DIVISION

ADVANCED SYSTEMS DIVISION

CONTROL SYSTEMS DIVISION

GENERAL INFORMATION
Quality Assurance
Package Data
Representatives and Distributors
Terms of Sale

FUNCTIONAL INDEX

TELECOMMUNICATIONS DIVISION
Part Number

Description

TR1402

Programmable UART

Page

TR1602

Programmable UART

17
17

TR1863

Programmable UART

TR1865

Programmable UART

PR1472

Programmable SAR

PR1482

Programmable SAT

FR1502

39
55
67

UC1671

FIFO Buffer Register
ASTRO-Full Duplex Synch or Asynch

WD1931

ASTRO-Compatible with SDLC

WD1933

SDLC-Parallel to Synch Serial

BR1941

Dual Baud Rate Generator

115

WD1983

Programmable BOART

123

WD1984

Multi-Character Synch ronous/ Asynchronous Transmitter/Receiver

189

WD1993

ARINC 429-1 ASART Controller

171

WD2123

Deuce Dual Channel BOART

151

WD2501

Packet Switching Controller, CCITT X.25 -LAP

291

WD2511

Packet Switching Controller, CCITT X.25-LAPB

291

WD25001XC

Pac-Kit

WD2001

Single Port Data Encryption Device

303
261

WD2002

Dual Port Data Encryption Device

261

WD20001XA

Cryptographic Primer Kit

273

WD5869

Shift Register

WD8250

ACE Async Communications Element

63
135

COMPUTER PRODUCTS DIVISION
Page

Part Number

Description

WD1000

Winchester Controller Board

327

WD1100
WD1510

Winchester Controller Chip Set
LIFO/FIFO Buffer Register

329
425

WD1691

Floppy Support Logic

399

FD1771

Floppy Disk Controller-Single Density

371

FD1791

FDC-Single/Dual Density, Inverted Data Bus

331

FD1792

FDC-Single Density, Inverted Data Bus

331

FD1793

FDC-Single/Dual Density, True Data Bus

331

FD1794

FDC-Single Density, True Data Bus

331

FD1795

FDC-Dual Density/Side Select, Inverted Data Bus

331

FD1797

FDC-Dual Density/Side Select, True Data Bus

DM1883

Direct Memory Access Controller

331
407

WD2143

Four Phase Clock Generator

419

ADVANCED SYSTEMS DIVISION
Part Number

Description

WD0090

Pascal MICROENGINE Computer System

Page

WD0900

Pascal MICROENGINE Single Board Computer

437

WD9000

Microprocessor Chip Set

441

WD9810
WD9810

Pascal System Software
Pascal Compiler

443
445

ME1600

Modular MICROENGINE

447

433

CONTROL SYSTEMS DIVISION
Part Number

Description

WD51

Irrigation Controller

463

WD55

Industrial Timer/Controller

471

WD4020

ROMless version of WD4200

487

WD4200/4210

Single Chip 4-Bit Microcontroller, COPS Family

495

Page

DII11l:rrocilucltion to

The Telecommunications Division of Western Digital has established a strong
market leadership position by developing state-of-the-art standard and custom
products which provide cost effective solutions for the complex needs of its
customers in the rapidly growing field of digital communications.

GENERAL DATA
COMMUNICA nONS
In the General Data Communications product line, our product offerings have
been expanded to cover more advanced protocols such as the WD1933 for
SDLC/HDLC and the WD1993 for the ARINC 429 which is for avionic use
onboard aircraft. With these offerings, Western Digital now has the broadest line
of protocol controllers in the industry. Future editions of this catalog will
introduce dual devices with multiple system functions per package as well as
complete board products.

SECURITY PRODUCTS
Western Digital has introduced the WD2001/2002, the first high-speed LSI
implementation of the data encryption algorithm which has been standardized
by the National Bureau of Standards. Because of this early market entry the
WD2001 has been chosen by companies all over the world for use in their new
deSigns. Future product offerings will include more advanced LSI devices with
increased functionality as well as encryption system products.

NETWORK PRODUCTS
One of the most strategic products announced in this catalog is the X.25
Packet Switching Controller, the WD2501. Packet switching is an advanced
form of digital network technology that is being heralded as one of the most
strategic technologies of the 1980's, and Western Digital's visible leadership in
this field will lead to significant growth opportunities in both public networks and
"local network" markets such as the "office of the future" and advanced
manufacturing applications. The Division is developing both standard proprietary
products and custom versions.

Table of Contents

TELECOMMUNICATIONS DIVISION
Page
CROSS REFERENCE, PIN COMPATIBLE AND FUNCTIONAL

PRODUCT SELECTION CHART

GENERAL DATA COMMUNICATIONS PRODUCTS

15
16

Family and Protocol Definitions
Data Sheets

UARTS

TR1402/1602/1863/1865

PSAR

PR1472

PSAT

PT1482

FIFO

FR1502

SHIFT REGISTER

WD5869

ASTRO

UC1671

USART
HDLC

WD1931

81
99

WD1933

DUAL BAUD RATE GENERATOR

BR1941

115

BOART

WD1983

123

ACE

WD8250

135

DEUCE

WD2123

151

ARINC 429-1 Controller

WD1993

171

MULTI-CHARACTER USART

WD1984

189

Technical Note

205

Using the new Data Link Control Chips

207

Data Link Control Chip supports all three bit oriented protocols.

215

Applications Notes

221

Asynchronous Receiver/Transmitter-TR1602/1863

223

WD1931/1933 Compatibility Application Note

235

Page

SECURiTY PRODUCTS

259

Data Sheets
Data Encryption Devices

WD2001/2

261

Cryptographic Primer Kit

WDK20001 -XA

Technical Note

273
275

Cipher Feedback Cryptography
Applications Note

279

One Bit Cipher Feedback in a Synchronous System

281

277

NETWORK PRODUCTS

289

Data Sheets
-WD2501/11
-WDK25001-XC

Packet Network Interface Devices
Pac-Kit

291

303

Technical Note

305

Chip opens door to Packet Switching

307

BOARD PRODUCT NUMBERING SYSTEM

319

321

Board Product Numbering

FUNCTIONALITY COMPATIBILITY GUIDE (PARTIAL LIST)
WD
WD1931

WD1933

SIGNETICS FAIRCHILD

INTEL

MOTOROLA

AMI

SMC

HARRIS ZILOG MOSTEK

2651
2661

6852

8251A

6852

8251A

SIO

3884

2652

6854
6856

8273

6854

5025

SIO

3884

9414 1

8294

6859

6894

WD1993

429

WD2001
FR1502

33512

PLEASE CONTACT FACTORY FOR APPLICATIONS ASSISTANCE.
NOTES:

1. Four chip set.

PIN COMPATIBLE REPLACEMENT GUIDE
WD
TR1402

TR1602
TR1863

TR1865

SMC

AMI

COM2502 AY-5-1013A
COM2502H AY-6-1013

TMS6010 4 S1757

COM2017
COM2017H

TMS6011 4

COM1863
COM8017

AY-3-1014A

COM8018

AY-3-1015D

PR1472

AY-3-1472B 4

PT1482

AY-3-1482B 4

UC1671

NAT

COM1671

INTEL SIGNETICS HARRIS INTERSIL

2536

HM6402

IM6402

INS1671

WD8250

INS8250

WD1983 1

INS8251A

8251A

BR1941 2 COM5016
COM5036 3
PLEASE CONSULT FACTORY FOR MAXIMUM OPERATING FREQUENCIES AND HIGH-RELIABILITY
SCREENING.
NOTES:

1. WD1983 is ASYNC only.
2. Many frequency selections available. Consult factory for details.
Frequency selection is mask programmable-consult factory for details.
3. Pin 10 on BR1941 is a "no connection".
4. Discontinued product.

PRODUCT SELECTION CHART
ARINC UARTS

GENERAL DATA
COMMUNICATIONS
PRODUCTS

PROTOCOL

FEATURES

wwww

9
9
3

6
0
2

8
6

D D
2
9 1
8 2
3 3

ARINC 429
ASYNCH
ISOCH
SYNCH (BI-SYNC)
SDLC
HDLC
ADCCP

FULL DUPLEX
MAXIMUM 100
320
500
640
1000
1500
2500
3500

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

SELECTABLE CLOCK
BOTH TRANSMIT AND
RECEIVE
INDEPENDENT TRANSMIT
AND RECEIVE
lX
4X
16X
32X
64X
128X
256X
WORD LENGTH SELECT
5,6,7,8 BIT

0
0

MATCH/SYN GENERATE
MATCH/SYN DETECT
BREAK DETECT
DOUBLE BUFFERING
TTL COMPATIBLE

3/5

D
8
2
5
0

D
1
9
8
4

P
R
1

P
T
1

U W
C D

7
2

8
2

6
7

.
..
".

9
3

w
D
1
9
3
3

0
0

.
.

0
0

.
.
.
0

.
.

.
•

. .
• .

. . ..
.
. .
. .
.
.. .
.
. •
.
.
.
. . . . .
. . . . . ..
. . .. . . .
. • .
. .
. . •
. . • . . •
• . . . . .

•
•

.
•

.
.

.. . . .
. . . .
. . .
II

. .
. . . •
• . . .

STOP BIT SELECT 1,1.5,2
PARITY SELECT ODDI
EVEN

PSAR/PSAT USART OLC

BOARTS

W
D

.
.
0

•

PRODUCT SELECTION CHART
GENERAL DATA
COMMUNICATIONS
PRODUCTS

ERROR CHECKING
FRAMING
OVERRUN
UNDERRUN
CRC GENERATE AND
CHECK

WWWW
D D D D
1 2 8 1
9 1 2 9
8 2 5 8

4
7

•

W
D
1

T
R
1

9
9
3

6
0 6
2 31s

•
"

PSARIPSAT USART OLC

BOARTS

ARINC UARTS

T
R
1
8

P
R

P
T

U W
C D
1 1

W
D
1

4
8
2

6
7
1

9
3
1

9
3
3

• •

•

"
" • •
"

PROCESSOR INTERFACE
UNIDIRECTIONAL
BIDIRECTIONAL

CONTROL
PROGRAMMING
DEVICE PINS
BIDIRECTIONAL BUS

·.

•

0
0

•

• •

MODEM INTERFACE
NUMBER OF SIGNALS 8

SPECIAL
FEATURES

NAZI OPTION
DIGITAL PHASE LOCK
LOOP
ON BOARD BAUD RATE
GENERATOR
EXTENDED WORD SIZE
TWO FULL DUPLEX
CHANNELS

•

SELF LOOP TEST

• •

•

6
4

•

"
0

General Data
Communications Products

DATA COMMUNICATION fAMILIES
Universal Asynchronous Receiver-Transmitter
Programmable Synchronous/Asynchronous Transmitter
Programmable Synchronous/Asynchronous Receiver
Universal Synchronous/Asynchronous Receiver-Transmitter
Bus Oriented Asynchronous Receiver-Transmitter
Data Link Controller

UART
PSAT
PSAR
USART
BOART
DLC

PROTOCOL DEFINITIONS
Marking

Line)

Start Bit

fr-L-,Il,--_ _ _ _,,,,,pf ss

Asynchronous
(Character Oriented)

L-I

• START and STOP Bits
• 5, 6, 7, 8 Bits/Character
• Plus option of Parity (Even or Odd)

'\.-

Data Bits

Parity

2 eight btl characters woth start STop bIts and pa"Ty

SlOp Bil(s)

~
L

P,mly outSide daTa Character
01 programmed

line Marking

P,ogrammed stop

1___
Previous Fill or
Data Characters

Data or Fill Character
• No 5T ART and STOP Bits
• 5,6, 7, 8 Bits/Character
• Plus option of Parity Bit
(Even or Odd)

SOH
SYN
STX
ETX
Bce

Bisync Character (Byte)
Transmission

Start 01 Header
Synchronization Character
Start Text
End of Text
Block Check Character

~_N_"'..I.'

_0..1...-+_.L...._"-jeader

Data or
Fill Characters

Data or Fill Character

L-+...J...-----_

Texs:'_ _

BGC Field _ _ _ _ _+!

Synchronous Data link Control (SOLe)

Flag

Packet Switching (X.2S)
Data link Control
(8it Oriented)

Markmg Ime or

2nd 8 bIt CharacTer

1st 8 bIICh3'..._-

CONTROL REGISTER LOAD CYCLE

'RR, RR, ARE DISCONNECTED AT
TRANSITION OF RRD FROM O.8V TO 2.0V

'OUTPUTS PE, FE, OE, OR, THRE ARE DISCONNECTED AT TRANSITION OF SFD
FADM a.BV TO 2.av

DATA OUTPUT DELAYS

STATUS FLAG OUTPUT DELAYS

TRANSMITTER FLOW CHART

RECEIVER FLOW CHART

ABSOLUTE MAXIMUM RATINGS
NOTE: These voltages are measured with respect to GND
Storage Temperature
-55°C to +125°C (Plastic) -65°C to +150°C (Ceramic)
VCC Supply Voltage
-0.3V to "7.0V
Input Voltage at any pin
-0.3V to '7.0V
Operating Free-Air Temperature
T A Range
0° C to 70 0 C
Lead Temperature (Soldering, 10 sec.)
300 D C
ELECTRICAL CHARACTERIST'CS
(VCC = 5V ± 5%, VDD =
SYMBOL

av,

VGG = - 12V ± 5%, TR1602/TR1402)
TR1602/TR1402

PARAMETER

MIN

OPERATING CURRENT
ICC
IGG

Substrate Supply Current
Gate Supply Current

VIH
VIL

LOGIC LEVELS
Logic High
Logic Low

VOH
VOL
IOC
IlL
IIH

OUTPUT LOGIC LEVELS
Logic High
VSS Logic Low
Output Leakage
Low Level Input Current
High level Input Current

MAX

TR1863/5
MIN

MAX

CONDITIONS

35 ma VCC = 5.25V

60 ma
-10 ma
VSS -

(V cc = 5V ± 5% TR 1863/5)

VGG = -12.6V
2AV

1.5V
0.8V

0.6V VCC = 4.75V
2AV

1.0V
OAV
10/Ja
-1.6 mE,

VSS = 4.75V, IOH = 100 lJa
OAV VSS = 5.25V, I OL = 1.6 ma
10ua VOUT = av, SFD = RRD = VIH
"'-1.6ma VIN =OAV
1Ol"a ",N = 3.75V, TR1865 only

SWITCHING CHARACTERISTICS
(See "Switching Waveforms")
SYMBOL

PARAMETER

tpdO
tpd1
tpdO
tpd1

Clock Frequency
TR1402
TR1602
TR1863-00
TR1863-02
TR1863-04
TR1865-00
TR1865-02
TR1865-04
Pulse Widths
CRL
THRL
DRR
MR
COinCidence Time
Hold Time
Set Time
OUTPUT PROPAGATION
DELAYS
To Low State 1602/1402
To High State 1602/1402
To Low State 1863/1865
To High State 1863/1865

Cin
Co

CAPACITANCE
Inputs
Outputs

fclock

tpw

tc
thold
tset

MIN

MAX
320
320
1.0
2.5
3.5
1.0
2.5
3.5

DC
DC
DC
DC
DC
DC
DC
DC
200
200
200
500
200
20
0

KHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz

CONDITIONS
Vee = 4.75V
with internal pull-ups on all inputs
with internal pull-ups on all inputs

with internal pull-ups on all inputs
with internal pull-ups on all inputs
with inlernal pull-ups on all inputs

ns
ns
ns
ns
ns
ns

650 ns
650 ns
250 ns
250 ns
20 pi
20 pi

CL = 20 pi, pi us one TTL load
CL = 20 pi, plus one TTL load
1= 1 MHz, VIN = 5V
f = 1 MHz, VIN = 5V

~J : : :

:0::: ::]

"' ' (::::: :0::::::]

001

•

TR1602B, TR1402B, TR1863B, TR1865B

TR1602A,TR1402A,TR1863A, TR1865A
CERAMIC (HERMETIC) PACKAGE

PLASTIC PACKAGE

TR1602P, TR1402P, TR1863P,
TR1865P PLASTIC PACKAGE

Information furnished by Western Digital Corporatton is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result trom its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said circuitry at any time without notice.

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

WESTERN DIGITAL
c

PR1472-01 (PSAR)
Programmable Synchronous & Asynchronous Receiver
!lii-+MifA ,

. ,;

, "4 'S & \. if

" , & &,.

FEATURES

GENERAL DESCRIPTION

• SYNCHRONOUS, ASYNCHRONOUS OR
ISOCHRONOUS OPERATION
• DC TO 640K BITS/SEC (1X CLOCK) PR1472-01;
DC TO 100K BITS/SEC PR1472
• PROGRAMMABLE MATCH (FILL)CHARACTER
WITH MATCH DETECT FLAG.
• INTERNAL OR EXTERNAL CHARACTER SYN·
CH RON IZATION
• NINE BIT WIDE RECEIVER HOLDING REGISTER
• SELECTABLE 5, 6, 7 OR 8 BITS PER CHARACTER
• EVEN/ODD OR NO PARITY SELECT
• PROGRAMMABLE CLOCK RATE; 1X, 16X, 32X
OR64X
• AUTOMATIC START AND STOP BIT STRIPPING
• AUTOMATIC CHARACTER STATUS AND FLAG
GENERATION
• THREE STATE OUTPUTS - BUS STRUCTURE
CAPABILITY
• DOUBLE BUFFERED
o TTL & DTL COMPATIBLE - INTERNAL ACTIVE
PULLUP
• COMPATIBLE TRANSMITTER, PT1482

The Western Digital PR1472 (PSAR) is a program·
mabie receiver that interfaces variable length serial
data to a parallel data channel. The receiver con·
verts a serial data stream into parallel characters
with a format compatible with all standard Synchronous, Asynchronous, or Isochronous data
communications media.

Contiguous synchronous serial characters are
compared to a programmable Match-Character
Holding Register, character synchronized and
assembled. Programming the Asynchronous or
Isochronous Mode provides assembly of characters
with start and stop bit(s) which are stripped from
the data. Four internal registers, in conjunction
with Three-State Outputs provide full system
versatility.
The PSAR is a TTL compatible device. The use of
internal active pull-up devices and push-pull output
drivers, provides direct compatibility with all forms
of current sinking logic. Western Digital also offers
a Compatible Transmitter, PT1482.

WLS2 RMS2

MR----~~~--------------~
CD

-----++-+_.
MDET

PR1472 BLOCK DIAGRAM
&liWWWW4AA

PS#!iMSMffl*lf _ @ii'!1' I

NUMBER
1
37,39,2

1/0 NAME

+ 5 Volt Supply

V ss POWER SUPPLY
RECEIVER MODE
SELECT

FUNCTION

SYMBOL

RMS., RMS"
RMS,

A low-level input voltage, VIL, applied to CD (pin
6) enables RMS., RMS" and RMS3 inputs. The
Receiver Mode Select Inputs, in conjunction with
the Control Register load and Chip Disable,
select the Receiver operating mode. RMS., RMS2,
and RMS3 may be strobed or hard-wired to the
appropriate input voltage.
RMS,

RMS,

RMS.

Selected Operating Mode
ASYNCH OR ISOCH,
1X CLOCK
ASYNCH OR ISOCH,
16XCLOCK
ASYNCH OR ISOCH,
32X CLOCK
ASYNCH OR ISOCH,
64X CLOCK
SYNCH·EXTERNAL
CHARACTER
SYNCHRONIZATION
SYNCH·INTERNAL
CHARACTER
SYNCHRONIZATION

NOTE: When operating in asynchronous or
isochronous mode with 1X clock there is
no protection against false start bits.
A high·level input voltage, V'H, applied to CD dis·
abres RMS., RMS, and RMS,.

18,22
MATCH·CHARACTER
17,36,3, HOLDING REGISTER
38,4,40 DATA

5,23

WORD LENGTH
SELECT

MHR"
MHR.,
MHR.,
MHR.

A low-level input voltage, VIL, applied to CD (pin
6) enables the inputs to the Match-Character
Holding Register Load, MHRL. Parallel 8-bit characters are input into the Match-Character Holding
Register with the MHRL Strobe (pin 34). If a character of less than 8 bits has been selected (by
WLS, and WLS,), only the least significant bits are
accepted. These inputs may be strobed or hardwired to the appropriate input voltage. A highlevel input voltage, VIL, applied to CD disables
MHR. and MHR•.

WLS., WLS,

A low-level input voltage, VIL, applied to CD (pin 6)
enables the inputs of the Control Register Load,
CRL. Parallel 8-bit characters are input into the
Control Register with the CRL Strobe
(pin 4),
WLS, and WLS, select the transmitted character
length from five (5) to eight (8) bits defined by the
Truth Table below:

MHR.,
MHR"
MHR.,
MHR"

WlS,

Selected Word length

V'l
V'l
5 BITS
V'l
V'H
6 BITS
V'H
V'l
7 BITS
V'H
V'H
8 BITS
WlS. and WlS, may be strobed or hard·wired to
the appropriate input voltage. A high·level input
voltage, V'H, applied to CD disables WlS. and
WlS,.

PIN
NUMBER
6

1/0 NAME

CHIP DISABLE

SYMBOL

FUNCTION
This line controls the disable associated with busable inputs and Three-State outputs. A high-level
input voltage, V ,H, applied to this line disables
inputs and removes drive from push-pull output
buffers causing them to float. Drivers of disables
outputs are not required to sink or source current. The 110 Lines controlled by Chip Disable are
defined below:

Input Lines
CRL
EPE
PI
WLS,WLS,
RMS,-RMS,

Three-State Output Lines

DRR
SFR
MHRL
MHR,-MHR.

PE
FE
OE

RR,-RR.

7-15

RECEIVER HOLDINGREGISTER DATA
OUTPUT

RR,-RR,

VGG POWER SUPPLY

VGG

-12VoltsSupply.

PARITY INHIBIT

A low-level input voltage, V,L, applied to CD (pin
6) enables the EPE and PI inputs.

EVEN PARITY ENABLE

EPE

The Even Parity Enable Input and the Parity
Inhibit Input to the Control Register, in conjunction with the Control Register Load and Chip Disable, select even, odd or no parity to be verified by
the receiver. A high-level input voltage, V,H, applied to EPE selects even parity and a low-level
input voltage, V,L, select odd parity if a low-level
input voltage is applied to Parity Inhibit and Chip
Disable. PI and EPE may be strobed or hard-wired
to the appropriate input voltage.

A low-level input voltage, V,L, applied to CD (pin
6) enables the Receiver Holding Register outputs, RR,·RR,. The parallel data character, including parity (RR,), appears on these lines.
Program control selection of a word length less
than eight (8) bits will cause the most significant
bits of the character to be forced to a low-level
output voltage, VOL' The character will be right
justified. RR, (pin 15) is the least significant bit
of the character. A high-level input voltage, V ,H ,
applied to CD disables RR,-RR,.

EPE

Selected Parity
Odd
Even
None

Comments
CD = V'L
CD
V'L
CD
V'L

=
=

NOTE: If CD = V,H, no programming is performed
since inputs are disabled.

X - either V'L or V,H. When programmed, the
appropriate parity is verified following the last
data bit of a character, immediately preceding
the stop element of asynchronous and isochronous characters.
A high-level input voltage, V,H, applied to CD disables EPE, PI, and CRL.

PARITY ENABLE

A high-level input VIH enables parity. A low level
input V I H disables parity.

PIN
NUMBER

1/0 NAME

STATUS FLAG RESET

DATA RECEIVED
RESET

SYMBOL
SFR

FUNCTION
A low-level in~ voltage, V,L, applied to CD (pin 6)
enables the SFR input. A low-level input voltage,
V,L, applied to this line resets the PE, FE and
OE Status Flags.
A low-level input voltage, V,L, applied to CD (pin
6) enables the DRR input. A low-level input volt-

age, V,L, applied to this line resets the DR Flag.
A high-level input voltage, V,H , applied to CD disables DRR.
26

DATA RECEIVED
FLAG

A high-level output voltage, V OH , indicates that
an entire character has been received and transferred to the Receiver Holding Register. When
operating in the synchronous mode, the first
SYN character, when located and transferred to
the Receiver Holding Register, will not cause DR
to go to a high-level output voltage, VOH , but
will cause MDET to go 10 a high-level output
voltage_ Character transfer to the Receiver Holding Register occurs in the center of the last bit
of a synchronous character or the center of the
first STOP element of an asynchronous or isochronous character at which time this flag is
updated.

OVERRUN ERROR
FLAG

A low-level input voltage, V,L, applied to CD (pin
6) enables the OE input. A high-level output
voltage, VOH , indicates that the prevously received
character was not read (DR line not reset) and
was, therefore, lost before the present character
was transferred to the Receiver Holding Register.
This transfer occurs in the center of the last bit
of a received synchronous character or in the
center of the first STOP element of an asynchronous or isochronous character at which
time this flag is updated_
A high-level input voltage, V OH , applied to CD
disables OE.

FRAMING ERROR/
SYN SEARCH

FE/SS

FE/SS is a two-way (I/O) bus. If programmed for
the ASYNCHRONOUS or ISOCHRONOUS MODE,
a low-level input voltage, V,L, applied to CD (pin
6) enables the FRAMING ERROR FLAG output
which indicates the status of the STOP BIT
detection circuit. A high-level output voltage,
VOH , indicates that the character transferred to
the Receiver Holding Register has no valid STOP
BIT; i.e., the bit following the PARITY BIT is not
a high-level input voltage, V ,H . This transfer
occurs in the center of the first stop element at
which time this flag is updated.
When programmed for the SYNCHRONOUS
MODE, this line is an input and is not under
control of CD. This line should be driven by a
tri-state or an open collector device.
If programmed for INTERNAL CHARACTER
SYNCHRONIZATION, a transition from a lowlevel input voltage, V,L, to a high-level input
voltage, V ,H , initiates the automatic internal
"SYN" CHARACTER search operation.

PIN
NUMBER

1/0 NAME

FRAMING ERRORI
SYN SEARCH

SYMBOL

FUNCTION

FE/SS

Prior to initiation of this operation, the Receiver
Holding Register is "transparent" so that its contents are identical to that of the RECEIVER REGISTER. Upon receipt of a SYN character, (previously loaded into the Match-Character Holding
Register during initialization), the Receiver Holding Register becomes non-transparent, the
MATCH DETECT output (MDET) goes to a highlevel output voltage_ V OH ' but, the Data Received
(DR) FLAG does not assume a high-level output
voltage, V OH - The P/SAR is now in character
synchronization_ Subsequent SYN or data character wilt be transferred to the RECEIVER HOLDING REGISTER as they are assembled (at the
center of the last bit) and the DR FLAG will be
raised_ A transition lrom a high-level input voltage, V,H , to a low-level input voltage, V,L, causes
the P/SAR to lose character synchronization
and forces the Receiver Holding Register to
become "transparent."
If programmed for EXTERNAL CHARACTER SYNCHRONIZATION, the system external to the
P/SAR examines the data stream for "SYN"
characters when SYN SEARCH is a lOW-level
input voltage, V'L- The Receiver Holding Register
is "transparent" which allows the contents of
the RECEIVER REGISTER tc\ be monitored as it
ripples through the shift register. When the external logic locates a "SYN" CHARACTER, indicated by a high-level input voltage, V OH ' on
MDET, the SYN SEARCH line is externally raised
to a high-level input voltage, V ,H - This high-level
input voltage causes character synchronization
to be initiated, returns the Receiver Holding
Register to a "non-transparent" condition, causing subsequent characters to be transferred to
the RECEIVER HOLDING REGISTER (when the
center of the last bit of a character is recognized)
and raises the DR FLAG_

MATCH DETECT
FLAG

MDET

A high-level output voltage, V OH , indicates that
the contents of the Transmitter Register are
identical to the contents of the Match-Character
Holding Register. This flag is set to a high-level
output voltage, VOH , at the center of the first
STOP ELEMENT of an asynchronous or isochronous character_

RECEIVER REGISTER
CLOCK

RRC

This fifty (50) percent duty cycle clock provides
the basic receiver timing_ The negative transition
from a high-level input voltage, V'H, to a low-level
input voltage, V'L, shifts data into the RECEIVER
REGISTER at a rate determined by RMS"
RMS, and RMS,_ Synchronous operation requires that this negative transition occur at
the center of each data bit.

PIN
NUMBER

I/O NAME

SYMBOL

FUNCTION

MASTER RESET

A high-level input voltage, V'H, applied to this line
resets timing and control logic to an idle state,
sets the contents of the Receiver Holding Register
to a high-level output voltage, VOH, resets the
contents of the Match-Character Holding Reg·
ister, the MDET, DR, PE, FE, and OE outputs to
a low·level output voltage, VOL, but does not
effect the contents of the control register.

CONTROL REGISTER
lOAD

CRl

A lOW-level input voltage, V'L, applied to CD (pin
6) enables the CRl input. A low-level input volt·
age, V'L, applied to this line enables inputs to
DC "0 Type" latches of the Control Register
and loads it with Control Bits (EPE, PI, RMS"
RMS" RMS., WlS" WlS,). A high·level input
voltage, V'H, applied to this line disables the
Control Register. This line may be strobed or
hard-wired to a low-level input voltage, V'L' A highlevel input voltage, V'H, applied-to CD disables
CRl.

MATCH CHARACTER
HOLDING REGISTER
lOAD

MHRl

A low-level input voltage, V'L, applied to CD (pin
6) enables the MHRl input. A low·level input
voltage, V'L, applied to this line enables input
to DC "0 Type" latches of the Match-Character
Holding Register and loads it with the MatchCharacter Holding Register. This line may be
strobed or hard-wired to a low·level input voltage,
V'L'
A high-level input voltage, V'H, applied to CD dis·
abies MHRl.

RECEIVER INPUT

The serial input data stream received on this
line enters the Receiver Register determined by
the character length, parity and the number of
stop bits programmed. A high·level input voltage,
V'H, must be present when no ASYNCHRONOUS
data is being received.

ORGANIZATION
PR1472 block diagram is illustrated on page 1.

receiver register to establish character synchronization.

Control Register - Programming of the PSAR is
accomplished by loading the 7 Bit Control register.
Mode selection, clock division, word length, and
parity are selected when the Control Register load
(CRl) signal is activated.

Timing & Control - The Timing and Control logic
generates the required control signals to assemble
characters, match comparison, bit stripping, and
generation of status/flag signals.
SYNCHRONOUS MODE OPERATION

RQl:eiver Register - The Receiver Register is used
to store the incoming data stream. The contents
of this register can be gated to the Holding register
during the transparent mode, or compared with
the Match Holding Register. When a character is
assembled it is transferred to the Receiver Holding Register.
Receiver Holding Register - The Receiver Holding
Register, a buffer register, is used to store the
assembled character.

Synchronous data appears as a continuous bit
stream of contiguous characters at the input to
the receiver with no Start or Stop bits. Character
synchronization (the "framing" of this continuous
bit stream into characters of a predetermined fixed
length), must be accomplished by a comparison
of this bit stream and a synchronization sequence.
The P/SAR is deSigned to accommodate ir.ternal
or external character synchronization by program
control.

Match Holding Register - The Match Holding
Register is used to store the match character. The
contents of this register are compared with the

Referring to the Block Diagram of the Receiver, the
Chip Disable (CD) enables ordisconnects various in-

puts and outputs of the PfSAR. This feature pro·
vides the device with the capability of being dis·
connected from the system bus. The inputs to the
Control Register and Match·Character HOlcJ.i..r2fl
Register and their respective load strobes, CRL
and MHRL are under CD control. In addition, DRR,
SFR, PE, and OE and the outputs of the Receiver
Holding Register, are also controlled by CD. It is
necessary that CD enable these lines to allow strob·
ing information in these registers and to allow
examination of these output flags and data.
Device operation is programmed subsequent to
being forced into its "idle" state. The PISAR will
enter a defined "idle" state when the Master Reset
(MR) line is strobed to a high·level input voltage.
In this state, all timing and control logic are reset,
the contents of the Receiver Holding Register is
set to a high·level output voltage and all output
flags are reset to a low·level output voltage. The
Master Reset also causes the contents of the Match·
Character Holding Register to be reset to a low·
level output voltage.
Enabled ~D, the Control Register is loaded by
strobing CRL to a low·level input voltage which
defines mode of operation and clock rate selection,
character length and selected parity if required.
Table 1 illustrates all programmable synchronous
formats.
Character synchronization from the data stream
requires Receiver recognition of specific bit pat·
tern(s) which define the relative position of syn·
chronous characters in the data stream and sub·
sequent character assembly. The PISAR program·
mably accommodates internal or external character
synchronization.
Programmed for internal character synchroniza·
tion, a high·level input voltage on the Sync Search
line, the Receiver Holding Register is "trans·
parent" and its contents are identical to the Re·
ceiver Holding Register. The data stream, gated
into the Receiver Input (RI) by the negative
transition of the Receiver Register Clock (RRC),
shifts through the Receiver Register and is com·
pared with the preprogrammed character in the
Match·Character Holding Register. A match, in·
dicated by a high·level output voltage on Match
Detect (MDEl), returns the Receiver Holding register
to its non·transparent state and initializes timing
and control logic but does not set the Data Received
Flag to a high·level output voltage. The character
following the match will be transferred to the Re·
ceiver Holding Register at the receipt of the center
of its last bit and the Data Received Flag is set to
a high·level output voltage. Depending on line dis·
cipline, this last character may also be a synchroni·
zing character, in which case, Match Detect will
continue to be a high·level output voltage when
the Data Received Flag is set. Therefore, sequence
verification can be performed by the system (ad·
ditional hardware or software as desired).

Parity, if programmed, is verified upon receipt of
the center of the parity bit which is the last bit of a
synchronous character. If a parity error exists, the
associated PE register is set to a high·level output
voltage.
Transfer of a character to the Receiver Holding
Register sets the associated Data Received Register
Flag (DR) to a high· level output voltage. The transfer
of a character to the Receiver Holding Register, if
the Data Received Register Flag had already been
set to a high·level output voltage, causes the pre·
vious character to be lost (written over) and is alerted
by an Overrun Error Flag which is a high·level out·
put voltage. In normal operation, the Data Received
Flag is reset by DRR when the Receiver Holding
Register is serviced (unloaded). The Status Flags,
PE and OE, are also provided with an external reset
SFR so that block status and character status may
be (accumulated) verified. A low·level input voltage
on Sync Search causes character synchronization
to be lost and initiates transparency of the Receiver
Holding Register.
External character synchronization, programmed
by the Control Register, is similar to the descrip·
tion above with the exception that the Sync Search
line controls the nontransparency of the Receiver
Holding Register directly and comparison is done
externally. Upon recognition of the appropriate
synchronizing pattern, the Sync Search line is set
to a high·level input voltage prior to the end of the
last bit. Raising the Sync Search line to a high·
level input voltage causes the buffer to go "nontrans·
parent", initializing timing and control circuitry to
"frame" characters. The first bit received after a
high-level input voltage is applied to Sync Search.
defines the start of the "frame". Character length
defined by the Control Register defines the end of
the "frame".
Table 1. SYNC MODE CONTROL DEFINITION
CONTROL WORD
R W W

M L

CHARACTER FORMAT

L
S

E
P

DATA

PARITY BIT

BITS

CHECKED

0
0

5
5

EVEN

0
0

ODD
NONE

0
0

ODD

EVEN

0
0

X
0

NONE

7
7
8
8

EVEN

X
0

1
1
1 1 X
Sets to SYNC Mode

ODD
NONE

If RMS, = 1, the receiver operates in the internal
character SYNC mode.

If RMS,

= 0, character SYNC must be externally

provided.

ss
MA

CAL

-Il~

______________________________________________________

---Il~

____________________________________________________

CHARACTER NO 1 CHARACTER NO 2 CHARACTER NO 3 CHARACTER NO 4

MOET

____________________________--I--------~________r__JL
-------------------------,u~----~LJ~--~~

~~______~------~____~----~L_I

u
·CLOCK SHOWN IS BIT RATE CLOCK {1Xj

(INTERNAL SYNCHRON IZATION)
MA----Il~

________________________________________________

RAC·

II I I I I

I I

ss
oA

------------~~~---------

oAA --------------------~~r---------------

CD
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I I I I I I I I I I I I I I I I I t I I I I I I I II I

CONTENTS OF
RECEIVER REGISTER CHARACTER
SYNCHRONIZATION
ESTABLISHED

·CLOCK SHOWN IS BIT RATE CLOCK (lX)

(EXTERNAL SYNCHRONIZATION)
SYNCHRONOUS TIMING DETAIL

CONTENTS OF
CHARACTER
RECEIVER REGISTER
SYNCHRONIZATION
LOST

ASYCHRONOUS & ISOCHRONOUS MODE
The completed assembly of a parallel character, by
the PISAR, from a serial data stream and buffered
by its Receiver Holding Register is indicated by the
status of the Data Received (DR) Flag. The assembly
of character from a serial data stream consisting
of a start bit, data, parity (if programmed), and a
stop interval is initiated by the Start bit transition.
Verification of parity and receipt of a valid stop bit
is accomplished prior to the character transfer to
the Receiver Holding Register. Simultaneously,
this data is compared with a preprogrammed character in the Match·Character Holding Register.
Status Flags, Data Received, Parity Error, Framing
Error, Overrun Error and Match Detect are loaded
into status registers during character transfer to
the Receiver Holding Register.
Referring to the Block Diagram of the Receiver, the
Chip Disable enables or disconnects various inputs
and outputs of the PISAR. This feature provides
the device with the capability of being disconnected
from the system bus. The inputs to the Control
Register and Match-Character Holding RegiS~L
and their respective load strobes, Cl!h.an~H
are under CD control. In addition, ORR, SFR, PE,
FE, OE and the outputs of the Receiver Holding
Register are also controlled by CD. It is necess,:ry
that CD enable these lines to allow strobing Information into these registers and to allow examination of these output data and flags.
Device operation is programmed subequent to
being forced into its "idle" state. The PISAR will
enter a defined "idle" state when the Master Reset (MR) line is strobed to a high·level input
voltage. In this state, all timing and control logiC
are reset, the contents of the Receiver Holding
Register is set to a high-level output voltage, and
all output flags are reset to a low-level output voltage. The Master Reset also causes the contents of
the Match-Characer Holding Register to be reset
to a lOW-level output voltage.
When the Receiver is enabled by CD, loading the
Control Register by strobing the Control Register
Load (CRL) line to a lOW-level input voltage defines
the mode of operation and clock rate selection,
character length and selected parity if required.
Table 2 illustrates all the programmable asynchro·
nous formats.
A mark to space transition on the receiver input
initializes the clock counter causing it to count to
the theoretical center of the start bit. At this time,
the input is sampled. A high-level input voltage at
the Receiver Input causes the first mark to space
transition to be interpreted as a noise spike and
resets all timing and control logic. This provides
one-half data bit nOise immunity on all clock selec-

tion rates except 1X. A lOW-level input voltage at
the Receiver Input at the theoretical center of the
start bit causes timing and control circuitry to
sample the theoretical center of succeeding data
bits. This data is shifted through the Receiver
Register. When an entire character(as defined by
the Control Register) is assembled In the Receiver
Register, the line is "tested" for a valid stop bit at
its theoretical center. This character IS also compared with the contents of the Match·Character
Holding Register at the center of the stop bit
and its parity is verified. A parallel transfer occurs,
loading the contents of the Receiver Register (less
start and stop bits) into the Receiver Holding Register. The status of the parity verification, framing
error, and overrun error circuitry are also loaded
into their approriate registers to provide output
error flags when the Data Received Flag is set. If
the Data Received Flag had not been reset prior to
the assembly of the current character, the previous
character is lost and this is indicated by a high-level
output voltage on the Overrun Error Flag.
Table 2. ASYNCHRONOUS OR ISOCHRONOUS
MODE CONTROL DEFINITION
R W
M

S
3
0
0
0

S
2

0
0

°
1

°0
X
0 0
1 0 1
1

7
7
8
8

0, ,I ,,1 1 X
1
8,
'L-Set to ASYNC orlSOC Mode

Even
None
Odd
Even
None

Elements
10rmore
1 or more
lor mOre
lor more
lor more
tor more
1 or more
1 or more
lor more
10rmors
i ormore
1 or more

When RMS, is 0 (ASYNC or ISOC Mode), RMS, and
RMS, determine the clock frequency according to
the following table:

____________________________________________

---Il~

CRL

~r------------------------------------------------

MHRL

~r------------------------------------------------

RAC·
RI

n'--__
u

_ _ _ _--'il

u
-.J

CD
MOET

RR,-RRg

__-L~~~~~~~~~~~~~~______-Ef8~~~~~8~$8~0~$8~8~$8~0~~~8L-__Jr----l~____________

__~~~~~~~~~~~~~~8L-____-h~~~~~~~~~~~~~~~~~~~~~~~________~~

u----u---u·CLOCK SHOWN IS BAUD RATE CLOCK (1X)

ASYNCHRONOUS & ISOCHRONOUS TIMING EXAMPLE

EPE, PI, WLS1. WLS2. RMS,-AMS3
MHR,- MHR 8

\'---

, t J 1 ~'~m"
DR

JE,'""=j l,~

PE. FE. OE

~
TRESETJ

DATA INPUT LOAD CYCLE

RESET DELAY

SWITCHING WAVEFORMS

,------_ _ _ _ _ _ _~""'""O"""'"O".

, 5,,'<1

~1'NlO .~OPt~

'OS>

11QND'RECElvER"EGoSTER
8ASED ON 'ME sHECTEe

woAe UNGTH

' 'MOB''

.~O

•• "ITY

StOn ....CEIVEAAEGIS'lATO
O applied to this line resets the Data
Not Available Flag. A ~.Ievel Input, V1H,
applied to CD disables DA . This input is not
used during asynchronous operation.

TRANSMITTER
CLOCK OUTPUT

TCO

This output is a clock at the transmitted bit rate.
The negative going edge of this clock corre·
sponds to the center of each transmitted data
bit. The positive going edge corresponds to the
start of each data bit transmission. All wave·
forms in this specification are referenced to
TCO.

DATA NOT AVAILABLE
FLAG

A low· level input voltage, V1L, applied to CD (pin
22) enables the DA input. A high· level output
voltage, VOH , on this line indicates that a Fill·
Character has been transmitted, since a charac·
ter was not loaded into the Transmitter Holding
Register by the center of the last bit of a Syn·
chronous Character or the center of the Stop
Element of an Isochronous character. A high·
level input voltage, V1H , applied to CD disables
DA. This input is not used during asynchronous
operation.

DATA DELIMITI
END OF CHARACTER

DD/EOG

During asynchronous operation, a high·level
output voltage, VOH , indicates data is being
transmitted. A low·level output voltage, VOL,
indicates that a Start or Stop Element is being
transmitted.
\A low·level output voltage during synchronous
operation indicates that the last bit of a charac·
ter is being transmitted.

PIN
NUMBER

liD NAME

SYMBOL

FUNCTION

TRANSMITIER
HOLDING REGISTER
EMPTY

THRE

A low-level input voltage applied to CD (pin 22)
enables the THRE input. A high-level output
voltage, VOH , on this line indicates the Transmitter Holding Register is empty and has transferred its contents to the Transmitter Register
and may be loaded with a new character. This
line goes to a low-level output voltage, VOL,
when THRL goes to a low-level input voltage,
V 1L- A high-level input voltage, V 1H , applied to
CD disables THRE_

TRANSMITIER
REGISTER OUTPUT

TRO

The contents of the Transmitter Holding
Register are serially shifted out as an NRZ
waveform on this line provided that a character
was loaded into the Transmitter Holding Register prior to DA Flag (in Synchronous or Isochronous Modes). If a character was not loaded
prior to a DA Flag, the contents of the FillCharacter Register are transmitted as the next
character.

VGG POWER SUPPLY

VGG

- 12 Volts Supply.

CLEAR-TO-SEND

CTS

The Clear-To-Send Control initiates or disables
transmission as a function of the state of this
line. A high-level input voltage, V 1H , initiates
serial data transmission provided a character
has been loaded into the Transmitter Holding
Register. A low-level input voltage, V1L , applied
to this lin~ during transmission allows completion of that character only, after which the
output will continue to mark until a high-level
input voltage is applied.

MASTER RESET

The rising edge of a high-level input voltage,
V1H , applied to this line resets timing and
control logic to an idle state, sets TH RE, the
contents of the Fill-Character Holding Register,
and TRO to a high-level output voltage, VOH.

TRANSMITIER
HOLDING REGISTER
LOAD

A lOW-level input voltage, V'L, applied to CD (pin
22) enables the THRL input. A lOW-level input
voltage, V1L, applied to this line enables DC
Latches of the Transmitter Holding Register
and loads it with the Transmitter Holding
Register data and forces THRE to a low-level
output voltage, VOL' A high-level input voltage,
V'H, applied to this line disables the Transmitter
Holding Register. A high-level input voltage,
V'H, applied to CD disables THRL.

FILL-CHARACTER
HOLDING REGISTER
LOAD

A lOW-level input voltage, V'L, applied to CD (pin
22) enables the FHRL input. A low-level input
voltage, V'L, applied to this line enables DC
Latches of the Fill-Character Holding Register
and loads it with the Fill-Character Register
data FR,-FR B• A high-level inpu~tage, V1H ,
applied to this line disables the FHRL Register.
This line may be strobed or hard-wired to a low-

PIN
NUMBER

I/O NAME

FUNCTION

SYMBOL

level input voltage, V'L. This input is not used
during asynchronous operation.
A high-level input voltage, V'H, applied to CD
disables FHRL.
21

Voo POWER SUPPLY

Voo

Ground.

CHIP DISABLE

This line controls the disconnect associated
with busable inputs and Three-State outputs. A
high-level input voltage, V'H, applied to this line
removes drive from push-pull outputs causing
them to float. Drivers of disabled inputs are
required to sink or source current. The 110 Lines
controlled by Chip Disable are defined below:
INPUT LINES
TRI-STATE OUTPUT LINES
CRL
THRL
DA
EPE
FHRL
THRE
PI
FR,-FR s
CS ,-CS 2 TR,-TR,
MS , -MS2 WLS, WLS,
DAR

23,25
27,29
31,33
35,37

FILL-CHARACTER
HOLDING REGISTER
DATA INPUTS

A low-level input voltage, V'L, applied to CD (pin
22) enables the inputs of the Fill-Character
Holding Register and associat\ld Load Strobe,
FHRL. Parallel 8-bit characters are input into
the Fill-Character Holding Register with the
FHRL Strobe (pin 20). If a character of less than
8 bits has been selected (by WLS , and WLS 2)
only the least significant bits are accepted.
These lines may be strobed or hard-wired to the
appropriate input voltage. These inputs are not
used during asynchronous operation.

FR,-FRs

During Synchronous or Isochronous transmission, the Fill-Character is transmitted if a character was not loaded into the Transmitter Holding Register prior to a DA Flag; i.e., the Transmitter Holding Register did not contain a
character at the center of the last bit being
transmitted from the Transmitter Register. A
high-level input voltage, V'H, will cause a highlevel output voltage, VOH , to be transmitted,
Least Significant Bit (FR ,) to Most Significant
Bit (FRn) order.
A high-level input voltage, V'H, applied to CD
disables FR ,-FR s.
24,26
28,30
32,34
36,38

TRANSMITTER
HOLDING REGISTER
DATA INPUTS

A low-level input voltage, V'L, applied to CD (pin
22) enables the inputs to the Transmitter Holding Register and associated Load Strobe,
iFffil. If a character of less than 8 bits has been
selected (by WLS , and WLS 2), only the least
significant bits are accepted. A high-level input

TR,-TRs

PIN
NUMBER

I/O NAME

FUNCTION

SYMBOL

voltage, V 1H , will cause a high-level output
voltage to be transmitted, Least Significant Bit
(TR,) to Most Significant Bit (TRn) order_ A highlevel input voltage, V 1H , applied to CD disables
TR,-TR B•
39-40

WORD LENGTH

WLS,·WLS2

A low-level input voltage, V1L , applied to CD (pin
22) enables~ inputs of the Control Register
and Load, CRL. Parallel a-bit characters are
input into the Control Register with the CRL
Strobe (pin 4), WLS, and WLS 2 select the transmitted character length from five (5) to eight (8)
bits defined by the Truth Table below:
WLS2
V1L
V1L
V1H
V1H

WLS,
V1L
V1H
V1L
V1H

SELECTED WORD LENGTH
5 BITS
6BITS
7 BITS
8 BITS

A high-level input voltage, V1H • applied to CD
disables WLS, and WLS 2, forcing them to float.
ORGANIZATION
PT1482 block diagram is illustrated on page 1.
Control Register - Programming of the PSAT is
accomplished by loading the 8 Bit Control Register.
Mode selection, clock divisor, word length, and
parity are selected when the Control Register
Load signal is activated.
Transmitter Register - The Transmitter Register
is used to store the outgoing data stream. The
contents of this register are derived from either
the Transmitter Holding Register or the Fill
(Match) Character Holding Register with the
Control and Timing Logic automatically adding
the required start and stop bits during Asynchronous and Isoschronous Modes.
Transmitter Holding Register - The Transmitter
Holding Register, a buffer register, is used to
store the parallel character to be serially transmitted.
Fill Character Holding Register - The Fill Char·
acter Holding Register is used to store the Fill
(Match) Character which is transmitted during the
absence of characters in the Transmitter Holding
Register.
Timing and Control - The Timing and Control
Logie generates the required control signals to
transmit Data and Fill Characters. Character transmission status signals are also derived from this
logic.
SYNCHRONOUS MODE OPERATION
Synchronous transmission requires that characters

(programmably variable from 5 to 8 data bits plus
parity) are contiguous with no start or stop bits.
Since the requirement that characters are conti·
uous does not imply that the system servicing the
transmitter always has ample time to load the
Transmitter Holding Register, it is necessary that
a character be transmitted when data has not
been loaded into the Transmitter Holding Register.
This character is defined as the Fill or Idle Character and a separate register has been provided to
load this character upon initialization. The FillCharacter Holding Register is loaded by strobing
the Fill-Character Holding Register Load (FHRL)
line or hard-wiring it to a lOW-level input voltage.
Referring the Block Diagram of the Transmitter, it
can be seen that the Chip Disable (CD) enables or
disconnects various inputs and outputs of the
P/SAT. The inputs to the Control Register, Transmitter Holding Register, Fill-Character Holding
Register and their respective load strobes, CRL,
THRL, and FHRL are under CD control. In addition, the Transmitter Holding Register Empty
(THRE) Flag, Data Not Available (DA) Flag, and the
Data Not Available Reset (DAR) are also controlled
by CD. It is necessary that CD enable these lines
to allow strobing information into these registers
and to. allow examination of these output flags.
The P/SAT will enter a defined "idle" state when
the Master Reset (MR) is strobed to a high·level
input voltage. In this state, all timing and control
logic are reset, the Transmitter Register Output
continues 10 mark, the Transmitter Holding
Register Flag is set to a high-level output voltage,
the Data Delimit/End of Character (DD/EOC) Flag

is set to a low·level output voltage, and the
contents of the Fill·Character Holding Register
are forced to a high·level output voltage.
When the P/SAT is enabled by CD, loading the
Control Register by strobing the Control Register
Load (CRL) line to a low·level input voltage,
defines the mode of operation, character length,
selected parity if required, and the clock rate
selection. Table 1 illustrates all the programmable
synchronous character formats.
To initialize transmission the CTS signal must be
set to a high state and the transmitter holding
register must be loaded with a character to be
transmitted. The transmitter will remain in an idle
state until this is accomplished.
The character transferred into the Transmitter
Register (from the Transmitter Holding Register or
the FiII·Character Holding Register) is determined
at the center of the last bit of the character being
transmitted. If, at this time, no character has been
loaded into the Transmitter Holding Register, the
Fill·Character is loaded into the Transmitter
Register at the end of the bit being transmitted

Table 1. SYNC MODE CONTROL DEFINITION
CONTROL WORD
WW
M M L L
5 5 5 5

CHARACTER FORMAT

E
P

DATA

ADDED
PARITY

BIT5

BIT

1
1
1
1
1
1
1
1
1
1

0
0
0

0
0

0
0
0
1
1
1
0
0
0
1
1
1

0
0
1
0

0
1
X
0
1
X

5
5
5
6
6
6
7
7
7
B
B
8

ODD

1
1

a
a
a

a
0
0

1
1
1
1
1
1

a
1
0
0

1
0

a
1
X
0

EVEN
NONE
ODD
EVEN
NONE
ODD
EVEN
NONE
ODD
EVEN
NONE

t
Sets to 5YNC Mode

TCO

MA
CD
TA,-TAB

l l_______________________________________________________
~~

:::x:::::x~

__________________________________________

_________JX'_______..JX'___________
u

-------------------------.u.---------------------DD/EOC

------Ir------,Ur-------.Ur----------,Ur----------,L·CLOCK SHOWN IS BIT RATE CLOCK (lX)

NOTE

~ ~~6=~;r;G
PI::: V'L

MS, :: V1L
MS2 ::: V'H

WLS, ::: V1H
WlS2::: V1H

SYNCHRONOUS TIMING EXAMPLE

and a Data Not Available (DA) Flag is set to a highlevel output voltage. This Fill-Character will be
repeatedly transmitted until a character is loaded
into the Transmitter Holding Register, at which
time, the Data Not Available Flag is reset, the Fill·
Character will be completed and the newly loaded
synchronous character will follow contiguously.
A high-level output voltage, on the THRE Flag
indicates that the Transmitter Holding Register is
empty and may be loaded with a character. Data
on the inputs of the Transmitter Holding Register
is loaded when the Transmitter Holding Register
Load (THRL) line is strobed to a low-level input
voltage, forcing the THRE Flag to a low-level
output voltage. This data must be stable prior to
THRL going to a high-level input voltage since this
register is a set of DC latches which are enabled
byTHRl.
If the Clear-To-Send (CTS) line is at a low-level
input voltage, or if the Transmitter Register is in
the process of transmitting a character, the
character in the Transmitter Holding Register will
not be transferred down to the Transmitter Register and the THRE Flag will remain at a low-level
output voltage. Raising the CTS line to a high-level
input voltage or completion of transmission of a
character from the Transmitter Register causes
the automatic transfer of the character in the
Transmitter Holding Register to the Transmitter
Register which forces the THRE Flag to be set to
high-level output voltage. The selected parity is
added to the data during the transfer to the Transmitter Register and serial transmission is initiated
as an NRZ waveform. A low-level input voltage
applied to CTS during transmission allows
completion of that character only, after which the
device enters the idle state and the output will
continue to mark until a high-level input voltage is
applied.

disconnects various inputs and outputs of the
PIS AT. The inputs to the Control Register, Transmitter Holding Register, Fill-Character Holding
~ster and their respective load strobes, CRL,
THRL and FHRL are under CD control. In addition,
the Transmitter Holding Register Empty Flag
(THRE), the Data Not Available Flag (DA), and the
Data Not Available Reset (DAR) are also controlled
by CD. It is necessary that CD enable these lines
to allow strobing information into these registers
and to allow examination of these output flags. It
should be noted that the Fill-Character Holding
Register and its associated load strobe, FHRL,
the Data Not Available Flag and its associated
reset, DAR, play no role in asynchronous communications and are only mentioned here for
completeness.
The PISAT will enter a defined "idle" state when
the Master Reset (MR) line is strobed to a highlevel input voltage. In this state, all timing and
control logic are reset, the Transmitter Register
Output continues to mark, the Transmitter
Holding Register Empty Flag is set to a high-level
output voltage, VOH , and the Data DelimitlEnd of
Character (DD/EOG) Flag is reset to a low-level
output voltage.
When the transmitter is enabled by CD, loading
the Control Register by strobing the Control
Register Load (CRL) line to a low-level input
voltage, V'L, defines the mode of operation,
character length, selected parity if required and
the clock rate selection. Table 2 illustrates. all the
programmable asynchronous formats.
Continuous transmission, transmission of characters with the minimum number of stop bits programmed, is accomplished by loading the
Transmitter Holdir,g Register within a character
time of when its "Empty Flag" becomes a highlevel output voltage. A high-level output voltage,
VOH , on the Transmitter Holding Register Empty
(THRE) Flag indicates that the Transmitter Holding Register is empty and may be loaded with a
character. Data on the inputs of the Transmitter
Holding Register is loaded when the Transmitter
Holding Register Load (THRL) line is strobed to a
low-level input voltage, V'L, fOi ng the THRE Flag
to a low-level output voltage, VOL. This data must
be stable prior to THRL going to a high-level input
voltage since this register is a set of DC latches
which are enabled by THRL. If the Clear-To-Send
(CTS) line is at a low-level input volta.ge or if the
Transmitter Register is in the process of transmitting a character, the character in the Transmitter
Holding Register will not be transferred down to
the Transmitter Register and the THRE Flag will
remain at a low-level output voltage. RaiSing the
CTS line to a high-level input voltage or completion of transmission of a character from the Transmitter Register causes the automatic transfer of
the character in the Transmitter Holding Register
to the Transmitter Register and the THRE flag will
be set to a high-level output voltage.

The Data DelimitlEnd of Character Flag has been
provided to indicate the transmission of serial
data on the Transmitter Register Output. The Data
Delimit/End of Character Flag is defined as a lowlevel output voltage during transmission of the
last bit of a synchronous character and when the
PIS AT is in the "idle" state.
ASYNCHRONOUS MODE OPERATION
An asynchronous character consisting of a start
bit, followed by data (programmably variable from
5 to 8 data bits), parity (if so programmed), and a
stop "element" is serially transmitted, in that
order, as an NRZ waveform by the PISAT. The stop
interval is referred to as an "element" since its
minimum length is under program control and
may be 1 or 2 bits in length. When programmed for
2 stop bits, a 5-level (bit) code will be transmitted
with 1.5 stop bits.

Referring to the Block Diagram of the Transmitter,
it can be seen that the Chip Disable enables or

The start bit, selected parity and stop bit(s), deter·
mined by the Control Register programming, are
added to the data during the transfer to the Trans·
mitter Register and serial transmission is initiated
as an NRZ waveform.

Table 2. ASYNC MODE CONTROL DEFINITION
CONTROL WORD

CHARACTER FORMAT

A low·level input voltage, applied to CTS during
transmission, allows completion of that character
only, after which the output will continue to mark
until a high·level input voltage is applied.

M M L

S S S

2 1 2 1

o0
o1
o0
o1

E
p

START

BIT

ADDED

000 0
0 0 0 0
0 0 0 1
0 0 '0 1
o 000 1 x
.0 1 0 0 1 X
000 1 0 a
o1 0 10 0
000 1 0 1
o10 10 1
000 1 1 X
o1 0 1 1X
001 000
o 1 1 000
00100 1
0 1 1 001
001 0 1 X
o 1 1 0 1 X
o0 1 1 0 a
a 1 1 100
001 1 0 1
o 1 1 1 0.1
001 11'0:
a1 1 1

The Data Delimit/End of Character Flag has been
provided to indicate the transmission of serial
data on the Transmitter Register Output. Data
Delimit is a low·level output voltage during start
and stop bits and is a high·level output voltage
during transmission of data and parity. Neither
TRO, CTS nor DO/EOC is under control of Chip
Disable.
ISOCHRONOUS MODE OPERATION
In the Isochronous Mode of operation all (Syn·
chronous Mode) definitions apply with the excep·
tion of those for the Data Delimit/End of Character
(DO/EOG) Flag and the Data Not Available Flag
(DA).
This is the case since Isochronous Data Trans·
mission requires contiguous characters with the
addition of a start and a single stop bit added to
each character.

•

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

DATA
BITS

PARITY

5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7

ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE

8
8
8
8
8

BIT

STOP
ELEMENTS

1
1.5
1
1.5
1
1.5
1

2
1

2
1
2
1

2
1

Sets to ASYNCMode

TCO·

__________________________________________

MR
CD

TR,· TRB

~L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

==::X~

__...JX,-________~X::::::X~____________

----~~r-----------~~r-----------------

CTS
THRE

TRO

Cill

DOfEOC

·CLOCK SHOWN IS BAUD RATE CLOCK (1X)
NOTE:

~ ~~6:~(N~
PI ~VIL
MS 1
V1l
MS 2 = V1L
WLS 1 = V1l
WLS 2 = V 1H

ASYNCHRONOUS TIMING EXAMPLE

Table 3. ISOC MODE CONTROL DEFINITION

The Data Delimit/End of Character Flag is a lowlevel output voltage during start and stop bits and
is a high-level output voltage during transmission
of data and parity. The Data Not Available Flag
(DA) is set to a high-level output voltage at the end
of the stop bit if a character has not been loaded
into the Transmitter Holding Register at the
center of the stop bit. The contents of the FillCharacter Holding Register will be transferred
into the Transmitter Register and repeatedly
transmitted until a character is loaded into the
Transmitter Holding Register. At this time, the
Fill-Character will be completed and the newly
loaded isochronous character will follow contiguously.

CON TROl WORD

WW
M M L L
S S sSP P
2

1 2 1

START
BIT

DATA

0 0 0 0
000 1

0 Q 1 X

10100

6
6
6
7

Q 10 1

0 1 1 X

1
1

1 Q 0 0
1 0 01

BIT

ODD

EllEN
NONE

ODD

EVEN
NONE

ODD

EVEN
NONE

7
7
8

1 0 1 X

1
1

1 1 0 a
1 1 0 1

1 1 1 X

PARITY

BITS

1
1

Table 3 illustrates all the programmable isochronous character formats.

ODD

EVEN
NONE

Sets 10 ISOC Mode

TCOJl~

MR
CD
TA"TR,

_______________________________________________

____

~r---1L

_____________________________________________

=x=::::x________---Jx.""_____---Jx.'--__________

Tffirr

~---------,LJr----------'LJr-----------

CTS

~r-----------------------------------------L-

L -______~IlL_
TRO

1 1>l2/31 41*1 718Ipl

IFIIILILI IclHIAIAI

____

~r--

______

1*I314151617181pl

~r__

u
Do/EGC

LJ
·CLOCK SHOWN IS BIT RATE CLOCK (1Xl

NOTE:

~ ~~6:~i~G
=

PI
V1L
MS, = V1H
MS 2

= V 1H

WLS 1 = V1H
WLS 2 ::;: V1H

ISOCHRONOUS TIMING EXAMPLE

EPE, PI, CS" CS 2, MS" MS 2, WLS,. WLS 2
TR,-TAa

V,"
-------------

DATA INPUT LOAD CYCLE

TRQ

SKEW TIMES

SWITCHING WAVEFORMS

OUTPUT ENABLE DELAYS

, s("rT CO~T"Ol "",
'SfTC·"·D'S'.,f '"
\ ~U'SI C"~T.O, .!G"'f~ ,0'0

,.~( ~"O~'lI ,~T."~
O()"'~ !""<5"'O~D'

.. " '"
leo

PT1482 SYNCHRONOUS ASYNCHRONOUS TRANSMITTER FLOW CHART

TCO

- f--

>50Qns

"
I
I

-1 ~ns
LJ-+

__ J

CTS

THRE

~ns __

-- -500ns

I ----

--.
TRO

~ns

500ns

I+-;~,

-- --,

I
I

,I
~ons

TIMING DETAIL

Ipoons

500ns

- r-

500ns

11- ____
_I.::-0ns

I
I
~

~on

ABSOLUTE MAXIMUM RATINGS

+ 0_3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to

VGG Supply Voltage
Voo Supply Voltage
Clock Input Voltage·
Logic Input Voltage·
Logic Output Voltage·
Storage Temperature

Ceramic
Plastic
Operating Free-Air Temperature T A Range
Lead Temperature (Soldering, 10 sec_)

- 20V
- 20V
- 20V
- 20V
- 20V
-165°C to +150°C
-55°C to +125°C
O°C to + 70 0
300°C

·VGG = Voo = OV
NOTE: These voltages are measured
with respect to Vss (Substrate)

ELECTRICAL CHARACTERISTICS

(Vss
Vcc
5V ± 5%, Voo
unless otherwise specified)

SYMBOL

= OV,

VGG

-12V ± 5%, TA

PARAMETER

V'l
V,H

INPUT LOGIC LEVELS'
Low-level Input Voltage
High-level Input Voltage

Val

OUTPUT LOGIC LEVELS'
Low-level Output Voltage

VOH

High-level Output Voltage

MIN.

MAX.
0.8V

CONDITIONS

= 4.75V

vss

Vss-1.5V
0.5V
V ss-1.0V

INPUT CURRENTLow-level Input Current

I'l

ooe to + 70 e

-1.6mA

(each input)

Vss = 5.25V
-1.6mA
IOl
Vss = 4.75V
IOH
-1001'A

=
=

Vss
Y'N

5.25V

= OAV

•• Not more than one output should be shorted at a time.
NOTE: 1) Inputs under Chip Disable control when disabled (V'H applied to CD), are logically disabled and
appear as a single TTL load.
2) Outputs under Chip Disable control when disabled (V'H applied to CD) are logically and electrically disconnected and caused to float.
The Three-State Output has three states;
(1) Low impedance to Vcc (2) Low impedance to GND (3) High impedance OFF
10 Megohm.
Iss
35m A
IGG
10mA

SWITCHING CHARACTERISTICS
(Vss

= Vcc = 5V, Voo = ov, VGG = -12V, TA = 25', Cl = 20pf)

SYMBOL

PARAMETER

MIN.

Clock Frequency

THOlO
TCRl
TTHRl
T FHAL
T OAR
T MR
T pD
T sKEw
TR
TF

PULSE WIDTH
HoldTime
Control Register Load
Transmitter Holding Register Load
Fill-Character Holding RegisterLoad
Data Not Available Reset
Master Reset
Output Enable Delay
Skew Time
RiseTime
Fall Time

DC
DC

MAX.
100 KHz
640 KHz

20 nsec
250 nsec
250 nsec
250 nsec
200 nsec
500 nsec
500
250
150
150

nsec
nsec
nsec
nsec

CONDITIONS
1482B
1482B-Ol

'" C::::(;5::::]
PT1482A CERAMIC PACKAGE

PT1482B PLASTIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from Its use. No
license is granted by implication or othe~ise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said circuitry at any time without notice

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

Yr. k

·g'R"

FEATURES
o

40 CHARACTERS BY 9 BITS

EXPANDABLE CHARACTER AND BIT SIZE
(CASCADE CAPABILITY)

DC TO 1 MHz ASYNCHRONOUS 1/0 ACCESS

INPUTIOUTPUT READY STATUS FLAGS

THREE STATE OUTPUTS

SEPARATE INPUT AND OUTPUT ENABLES

DIRECTLY TTL COMPATIBLE

o MASTER RESET
o NO EXTERNAL CLOCKS REQUIRED
o 28-PIN DIP PLASTIC OR CERAMIC PACKAGE
APPLICATIONS
POINT OF SALE TERMINALS
DATA TRANSMISSION BUFFER
LINE PRINTER INPUT BUFFER
KEY-TO-T APEIKEY-TO-DISC EQU I PMENT
CARD/TAPE READERS
AUTO DIALERS
CRT BUFFER MEMORY
CONTROL STACK SILO ORIENTED MACHINES

--.§

'-1- •

"PM'

+•

GENERAL DESCRIPTION

ous memory organized in a nine-bit by forty-character stack. ~
Chara~ters are loaded at the top of the stack and then ·'sink" ~
to the bottom of the stack, or to the level of previously en- m
tered data, without external clocks being applied. As a char- ~
acter is taken from the bottom of the stack, all of the previollsly loaded characters will automatically propagate toward
the output (bottom of stack).
Data can be entered whenever the INPUT REGISTER
EMPTY line is high by strobing INPUT STROBE. The INPUT
ENABLE line must also be high while strobing. The INPUT
STROBE resets INPUT REGISTER EMPTY and latches the
input data. As soon as this data is latched, INPUT REGISTER EMPTY will again go high and additional data can be
loaded.
When data reaches the FIFO output, the OUTPUT DATA
READY line will go high. The data is then valid at the outputs
(providing the OUTPUT ENABLE line is high). The falling
edge of the OUTPUT STROBE causes the OUTPUT DATA
READY line to go low and to shift new data into the output
register. When the new data is available, the OUTPUT DATA
READY signal again goes high.
The FIFO output data lines are in high impedance state
whenever the OUTPUT ENABLE line is low.
The logic conventions and internal delays designed into the
FIFO allow direct expansion of the memory without external
hardware (Cascade Mode).

COMPUTERITERMINALS 1/0 INTERFACE
BUFFER
TELEPRINTER BUFFER

INTERFACE SIGNALS DESCRIPTIONS
PIN
NUMBER
SIGNAL NAME
SYMBOL
25-2B,
2-6

FUNCTION

INPUT REGISTER
FR1502-00
-01
-02

IROIRB

Input data lines. These are input (but not latched) to the FIFO
when the Input Enable and Input Strobe are active (high).

FR1502-10
-11
-12

IROIRB

Input data lines. These are input (but not latched) to the FIFO independently of the Input Enable or Input Strobe.

INPUT REGISTER
EMPTY
FR1502-00
-01
-02

IRE

When high, indicates that data can be loaded into the FIFO. It is
reset to a low by falling edge of the Input Strobe.

FR1502-10
-11
-12

IRE

When high, indicates that data can be loaded into the FIFO. It is
reset to a low by a rising edge of the Input Strobe.

INPUT STROBE

Latches input data in the FIFO on a falling edge.

FR1502-10
-11
-12

Latches input data in the FIFO on a rising edge.

MASTER RESET

When high, clears the FIFO control registers. This leaves the
OUTPUT REGISTER DATA (ORO-ORB) in an undefined state.
sets INPUT REGISTER EMPTY (IRE) to high and resets OUTPUT DATA READY (ODR) to low.

OUTPUT REGISTER
DATA

OROORB

Three state data outputs. When OE is low, the outputs are in the
high impedance state. When OE is high, these lines present the
previous latched data in a first-in/first-out manner.

OUTPUT DATA
READY

ODR

ODR is high when data is latched and available at the data output
lines. Is reset to low by the falling edge of OUTPUT STROBE
(OS) if OUTPUT ENABLE (OE) is high.

OUTPUT STROBE

A falling edge of this signal resets the OUTPUT DATA READY
(ODR) line and then shifts the data one step towards the output
if OUTPUT ENABLE (OE) is high.

INPUT ENABLE
FR1502-00
-01
-02

When high, enables the Input Register and Input Control logic.
When INPUT STROBE (IS) is high, the input data will be transferred into the FIFO. IS can then be used to latch the data.

FR1502-10
-11
-12

When high, enables the Input Control Logic. At any state of IE or
IS, the input data will be transferred into the FIFO, but can not be
latched unless IE is high.

OUTPUT ENABLE

When low, OE puts the output lines (ORO-ORB) in high impedance state. When high, the output lines present the output data.

Vss POWER
SUPPLY

Vss

+5VDC

Voo POWER
SUPPLY

Voo

OVolt-GND

VGG POWER
SUPPLY

VGG

-12VDC

FR1502-00
-01
-02

19-11

____ F00'$;0'

\'---

IRE

}ORO-

NEW DATA

OR8

OUTPUT
DETAIL

as
ODR

NOTE: FA1502-10, 11, 12 SHOWN
FR15D2-00, 01, 02 STROBES
ON FALLING EDGE OF 15

SWITCHING WAVE FORMS

ABSOLUTE MAXIMUM RATINGS

VGG Supply Voltage

+O.3V to -20V

VOO Supply Voltage

+O.3V to -20V

Clock Input Voltage'
Logic Input Voltage'

+O.3V to -20V
+O.3V to -20V

Logic Output Voltage'

+O.3V to -20V

Storage Temperature (Ceramic)
Storage Temperature (Plastic)

-55'C to +125'C

'VGG = VOO = OV
NOTE: These voltages are measured with respect to VSS (Substrate)

ELECTRICAL CHARACTERISTICS

(Vss

+5V ± 5%; VDD

SYMBOL

OV; VGG

~-12V ±

5%; TA

O°C to +70'C unless otherwise specified)

PARAMETER

MIN

Vss-l.5V

VOL

INPUT LOGIC LEVELS
Low-level Input Voltage
High-level Input Voltage
OUTPUT LOGIC LEVELS
Low-level Output Voltage

VOH

High-level Output Voltage

VSS-l.0V

Vil
VIH

MAX

CONDITIONS

O.BV

Vss ~ 4.75V
(NOTE 1)
(NOTE 2)
Vss ~ 5.25V
IOl ~ -1.6mA

OAV

Vss

IOH

ISS

INPUT CURRENT
Low-level Input Current
(each pin)
SUBSTRATE SUPPLY CURRENT

IGG

GATE SUPPLY CURRENT

III

4.75V

+200 uA

VSS ~ 5.25V
VIN ~ OAV
~ 5.25V
VGG ~ -12.6V
VIN ~ OAV

-1.6mA
65 mA

VSS

-30mA

NOTE 1: All inputs have pull-up resistors. This allows unloaded TTL outputs 01 2.0V to be connected and operate properly.
When connected, this voltage (2.0V) will become V SS -1.5V.
NOTE 2: VOL and VO H when OE ~ V IH (low impedance output). High impedance (OE ~ V III

10 Mohm.

SWITCHING CHARACTERISTICS (Vss

See "Switching Waveforms"

= +5V, VDD = OV, VGG = -12V, TA = O°C to +70'C, CLOAD = 10 pf)

SYMBOL

PARAMETER

MIN

MAX

TIES

Input Enable Setup Time

TIEH
T OIS

Input Enable Hold Time
Data Input Setup Time

o ns
o ns
o ns

TOIH

Data Input Hold Time

250 ns

TIRL

Input Register Load Time

250 ns

TIRE
TISL
T ISH

Input Register Empty Time

800 ns

TOES

Output Enable Setup Time

TOEH

Output Enable Hold Time

50 ns

TOSL

Output Strobe Low Time

150 ns

Input Strobe Low Time
Input Strobe High Time

CONDITIONS
.......

450 ns
150 ns
50 ns
(NOTE 1)

TO DR

Output Data Ready Time

200 ns

TOR

Data Reset Time

600 ns

TpO

Output Propagation Delay Time

250 ns

TOORL

Output Data Ready Low

600 ns

TOSH

Output Strobe High Time

TOOV

Output Data Valid Time

Maximum Ripple Time

10 flS

(NOTE 2)

Maximum Bubble Time

25 flS

(NOTE 3)

TMR

Master Reset Pulse Time

500 ns

Maximum Data Rate

250 kHz

1 MHz

(NOTE 4)

500 ns
200 ns

NOTE1:T r ise= Ttall = IOnS.
NOTE 2: Ripple Time-time required for a single data character to propagate from the input to the output of an empty FIFO (IS
strobing edge to ODR rising edge).
NOTE 3: Bubble Time- time required for a "hole·' to propagate from the output to the input of a full FIFO (falling edge of OS to
rising edge of IRE).
NOTE 4: The maximum data rates for a "single" FIFO (not cascaded) and for FIFO's cascaded together are the same.
GENERAL NOTE: All A.C. test points are at 0.8V or 2.0V.

ORDERING INFORMATION
TA

= O°C to

+70°C

PART NO.

PACKAGE
TYPE

CASCADABLE

FR1S02E-00
F-OO

CERAMIC
PLASTIC

NO
NO

E-01
F-01

CERAMIC
PLASTIC

NO
NO

E-02
F-02

CERAMIC
PLASTIC

E-10
F-10

CERAMIC
PLASTIC

NO
NO
YES

E-11
F-11

CERAMIC
PLASTIC
CERAMIC
PLASTIC

E-12
F-12

INPUT
STROBE
EDGE

MAX.
DATA
RATE

FALLING

1.0 MHz
1.0 MHz

FALLING
FALLING
FALLING
FALLING
FALLING
RISING

SOO kHz
SOO kHz
2S0 kHz
2S0 kHz
1.0 MHz

YES

RISING

1.0 MHz

YES
YES

RISING
RISING

YES
YES

RISING
RISING

500 kHz
SOO kHz
2S0 kHz

EXPANSION EXAMPLE

2S0 kHz_

FR1502F PLASTIC PACKAGE

FR1502E CERAMIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents orother rights of third parties which may result from it8use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Carpor·
ation reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550, TWX 910-595-1139

WESTERN
DIGITAL
p
o

WD5869 Dynamic Shift Register
'mMi

B M®&,fY

FEATURES
o
o

ii B

··"""'WI6,·

.AI'k

&4' ..

4 gs...!

GENERAL DESCRIPTION
The WD5869 Dual 640 Bit Dynamic Shift Register is a monolithic MOS integrated circuit designed for use in computer
display peripherals. The clocks and recirculate logic are internal to reduce system component count, and 3 state output
buffers provide bus interface. The WD5869 is available in a
16 pin molded plastic package, or a 16 pin ceramic package.

DUAL 640 BIT
ADDITIONAL TAPS AT 512 ON EACH REGISTER
INTERNAL CLOCKING
HIGH SPEED
3 STATE OUTPUT BUFFER

APPLICATIONS
CRT DISPLAYS
COMPUTER PERIPHERALS
CRYPTOGRAPHY

Figure 2 WD5869 TYPICAL APPLICATION BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS
Data and Clock Input Voltage and Supply
Voltages with respect to VSS

+0.3V to -20V

Power Dissipation

800mW at TA

Storage Temperature

-SS'C to + 12S'C (Plastic Package)
-65'C to + 150'C (Ceramic Package)

= 2S'C

ELECTRICAL CHARACTERISTICS (DC)
TA = O°C to + 50'C, Vss = +5V ± 5%, Voo = -5V + 5%, VGG = -12V ± 5%
SYMBOL
100

PARAMETER

MIN

MAX

POWER SUPPLY CURRENT

-SO

UNITS

CONDITIONS

rnA

DATA INPUT LEVELS
V,l

Logical Low Level

VsS-17.9

Vss-4.2

V,H

Logical High Level

VSS-1.7

VsS+0.3

V
V

I,l

DATA INPUT LEAKAGE

jJ.A

Cd;

DATA INPUT CAPACITANCE

V,N = -5V; All other Pins GND
V,N = OV; I = 1MHZ, All other Pins
GND

CLOCK INPUT LEVELS
VOH

Logical High Level

VSS-1.0

VsS+0.3

VOL

Logical Low Level

VSS-17.9

VSS-14.S

lel

CLOCK INPUT LEAKAGE

jJ.A

Vo = -17.9V; All other Pins GND

Cc ;

CLOCK INPUT CAPACITANCE

200

Vo = OV; 1= 1MHZ, All other Pins
GND

I Source = - 50mA

VSS-O.4

I Sink = 1.6 rnA

DATA OUTPUT LEVELS
VOH

Logical High Level

VOL

Logical Low Level

2.4

TABLE 1 D.C. PARAMETERS

VMBOL

MIN

PARAMETER

CLOCK FREQUENCY
JW

CLOCK PULSE WIDTH, In

MAX

2000

0.15

1.0

CONDITIONS

UNITS

KHz illr

¢If ~ 20 ns

uS 01f + 0pw + 01r '" 3.0 uS

pw oul

CLOCK PULSE WIDTH, Out

0pw in

CLOCK PHASE DELAY TIME,
from rising edge

CLOCK PHASE DELAY TIME,
from falling edge

CLOCK TRANSITION TIME,
rising edge

1.0

us 0tf + 0pw + ¢tr

;tf

CLOCK TRANSITION TIME,
falling edge

1.0

DATA INPUT SET-UP TIME

DATA INPUT HOLD TIME

pdl

DATA OUTPUT PROPAGATION DELAY,
to low level

200

pdh

DATA OUTPUT PROPAGATION DELAY,
to high level

200

TABLE 2 A.C. PARAMETERS

DATA INPUT/
LOAD INPUT

V55 -1'OV

CLOCK

Vss-14.5V

Opw

Vss - 1.0V
CLOCK

'""~

~{
DATA OUTPUT

1.5V

Figure 3 WD5869 TIMING DIAGRAM

3.0 uS

WD5869J CERAMIC PACKAGE

WD5869K PLASTIC PACKAGE

Information I1Jmlshed by Westem Digital Corporation Is believed to be accurate and reliable. However, no responsibility Is assumed by
Westem DIgHal Corporation lor Its use; nor any Infringements 01 patents or other rights 01 third parties which may resuH lrom Its use. No
license Is granted by Implication or otherwise uncler any patent or patent rights of Western Dlg"al Corporation. Western Dlg"al Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DISITAL

CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

WESTERN DIGITAl.
c

UC1671 Asynchronous/Synchronous Receiver/Transmitter
o
CD
en
BAUD RATE - DC TO 1M BAUD/SEC
8 SELECTABLE CLOCK RATES
W
• Accepts 1X Clock and Up to 4 Different 32X ~
Baud Rate Clock Inputs
..,
• Up to 47% Distortion Allowance with 32X Clock

...

FEATURES
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
SYNCHRONOUS MODE
• Selectable 5·8 Bit Characters
• Two Successive SYN Characters Sets
Synchronization
• Programmable SYN and DLE Character
Stripping
o Programmable SYN and DLE·SYN Fill
ASYNCHRONOUS MODE
• Selectable 5·8 Bit Characters
• Line Break Detection and Generation
o 1·,1'/2·, or 2·Stop Bit Selection
o False Start Bit Detection
Automatic Serial Echo Mode

APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS

GENERAL DESCRIPTION
The UC1671 B (ASTRO) is a MOS/LSI device which
performs the functions of interfacing a serial data
communication channel to a parallel digital sys·
tem. The device is capable of full duplex com·
munications (receiving and transmitting) with
synchronous or asynchronous systems. The
ASTRO is designed to operate on a multiplexed
bus with other bus·oriented devices. Its operation
is programmed by a processor or controller via the
bus and all parallel data transfers with these
machines are accomplished over the bus lines.

SYSTEM COMPATIBILITY
o Double Buffering of Data
• 8·Bit Bi·Directional Bus For Data, Status, and
Control Words
o All Inputs and Outputs TTL Compatible
• Up to 32 ASTROS Can Be Addressed On Bus
o On·Line Diagnostic Capability

The ASTRO is fabricated in n·channel silicon gate
MOS technology and is TTL compatible on all
inputs and outputs.

TRANSMISSION ERROR DETECTlON·PARITY
Overrun and Framing

Lr----lr.----,~ ~
CARR
~

5TR
iffiI

m
m

""i'Ni"R
R'iiL'¥
I~

I"iff!

Voo
Vss

UC1671 BLOCK DIAGRAM

WI'
>l

'-r-r-1r-r-,..--Ir--"
Iii 19

@Ie

PIN OUTS
The device is packaged in a 40-pin plastic or ceramic
cavity package. The interface signals are defined below with all input/output signals complemented to
facilitate bussing and interfacing with TTL. The
PIN
NUMBER

PIN NAME

SYMBOL

1
21
40
20

POWER SUPPLIES

MASTER RESET

VBB
VCC
VDD
VSS
MR

DATA ACCESS LINES

DALO-DAL7

8-15

17,22,24, SELECT CODE
25,26

107-103

CHIP SELECT

READ ENABLE

WRITE ENABLE

INTERRUPT

INTERRUPT
ACKNOWLEDGE IN

INTERRUPT
ACKNOWLEDGE OUT

30-33

Data Set controls and Status signals are also complemented to allow for an inversion when converting to EIA RS232C levels. The names and symbols
assigned to the Data Set interface signals follOWS
EIA standard nomenclature.

IACKO

CLOCK RATES

Rl-R4

TRANSMITTED DATA

TDATA
(BA)

FUNCTION
-5V
+5V
+ 12V
Ground
The Control and Status Registers and other
controls are cleared when this input is low.
Eight-bit bi-directional bus used for transfer of
data, control, status, and address information.
Five input pins which when hard-wired assign the
device a unique identification code used to select
the device when addressing and used as an identification when responding to interrupts.
The low logic transition of CS identifies a valid
address on the DAL bus during Read and Write
operations.
This signal, when low, gates the contents of an
addressed register from a selected ASTRO onto
the DAL.
This signal, when low, gates the contents of the
DAL bus into the addressed register of a selected
ASTRO.
This open drain output is made low when one of
the communication interrupt conditions occur.
This input becomes low when polling takes place
on the bus by the Controller to determine the
interrupting source. When this signal is received,
the ASTRO places its ID code on the DAL if it is
requesting interrupt, otherwise it makes IACKO a
low.
This output is made a logic low in response to a
low IACKI if the ASTRO receiving an IACKI input
is not the interrupting device.
This open drain output is made low when the
ASTRO is responding to being selected by an
address on the DAL during read or write operations or in affirming that it is the interrupting
source during interrupt polling.
These four inputs accept four different local 32X
data rate Transmit and Receive clocks. The input
on R4 may be divided down into a 32X clock from a
32X, 64X, 128X, or 256X clock input. The clock
used in the ASTRO is selected by the Control
Register.
This output is the transmitted serial data from the
ASTRO. This output is held in a Marking condition
when the transmitter section is not enabled.

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

RECEIVED DATA

RDATA
(BB)

This input receives serial data into the ASTRa.

REQUEST TO SEND

RTS
(CA)

CLEAR TO SEND

DATA SET READY

CTS
(CB)
DSR
(CG)

DATA TERMINAL READY DTR
(CD)
RING INDICATOR
RING
(CE)

This output is enabled by the Control Register and
remains in a low state during transmitted data
from the ASTRa.
This input, when low, enables the transmitter
section of the ASTRa.
This input generates an interrupt when going On
or Off while the Data Terminal Ready signal is On.
It appears as a bit in the Status Register.
This output is generated by a bit in the Control
Register and indicates Controller readiness.
This input from the Data Set generates an interrupt when made low with Data Terminal Ready in
the "Off" condition.
This input from the Data Set generates an interrupt when going On or Off if Data Terminal Ready
is On. It appears as a bit in the Status Register.
This input is the Transmitter 1X Data Rate Clock.
Its use is selected by the Control Register. The
transmitted data changes on the negative transition of this signal.
This input is the Receiver 1X Data Rate Clock. Its
use is selected by the Control Register. The
Received Data is sampled by the ASTRa on the
positive transition of this signal.
This output is controlled by a bit in the Control
Register and is used as an extra programmable
signal.

CARRIER DETECTOR

CARR
(CF)

TRANSMITTER TIMING

IXTC
(DB)

RECEIVER TIMING

IXRC
(DD)

MISCELLANEOUS

MISC

RECEIVER REGISTER - This 8·bit shift register
inputs the received data at a clock rate determined by the Control Register. The incoming data
is assembled to the selected character length and
then transferred to the Receiver Holding Register
with logic zeroes filling out any unused high-order
bit positions.
RECEIVER HOLDING REGISTER - This 8-bit
parallel buffer register presents assembled
receiver characters to the DAL bus lines when
requested through a Read operation.
COMPARATOR - The 8-bit comparator is used in
the Synchronous mode to compare the assembled
contents of the Receiver Register and the SYN
register or DLE register. A match between the
registers sets up stripping of the received character, when programmed, by preventing the data
from being loaded into the Receiver Holding
Register. A bit in the Status Register is set when
stripping is performed. The comparator output
also enables character synchronization of the
Receiver on two successive matches with the
SYN register_

SYN REGISTER - This 8-bit register is loaded
from the DAL lines by a Write operation and holds
the synchronization code used to establish
receiver character synchronization. It serves as a
fill character when no new data is available in the
Transmitter Holding Register during transmission. This register cannot be read onto the DAL
lines. It must be loaded with logic zeroes in all
unused high-order bits.
OLE REGISTER - This 8-bit register is loaded
from the DAL lines by a Write operation and holds
the "DLE" character used in the Transparent
mode of operation in which an idle transmit period
is filled with the combination DLE-SYN pair of
characters rather than a single SYN character. In
addition the ASTRO may be programmed to force
a single DLE character prior to any data character
transmission while in the transmitter transparent
mode.
TRANSMITTER HOLDING REGISTER - This 8-bit
parallel buffer register holds parallel transmitted
data transferred from the DAL lines by a Write
operation. This data is transferred to the Transmitter Register when the transmitter section is
enabled and the Transmitter Register is ready to
send new data.

TRANSMITTER REGISTER - This 8-blt shift
register is loaded from the Transmitter Holding
Register, SYN register, or DLE register. The purpose of this register is to serialize data and
present it to the transmitted Data output.

In the Asynchronous mode the character transmission occurs when information contained in the
Transmitter Holding Register is transferred to the
Transmitter Register. Transmission is initiated by
the Insertion of a Start bit, followed by the serial
output of the character least significant bit first
with parity, if enabled, following the most significant bit; then the insertion of a 1-, 1.5-, or 2-bit
length Stop condition. If the Transmitter Holding
Register is full, the next character transmission
starts after the transmission of the Stop bit of the
present character in the Transmitter Register.
Otherwise, the Mark (logic high) condition is continually transmitted until the Transmitter Holding
Register Is loaded.
In order to allow re-transmission of data received
at a slightly faster character rate, means are provided for shortening the Stop bit length to allow
transmission of characters to occur at the same
rate as the reception of characters. The Stop bit is
shortened by 1/16 of a oit period- for 1-Stop bit
selection and 3/16 of a ;;it period for 1.5-, or 2-Stop
bit selection, if the n' xt character is ready in the
Transmitter Holding Register.

CONTROL REGISTERS - There are two 8-bit
Control Registers which hold device programming
signals such as mode selection, clock selection,
interface signal control, and data format. Each of
the Control Registers can be loaded from the DAL
lines by a Write operation or read onto the DAL
lines by a Read operation. The registers are
cleared by a Master Reset.
STATUS REGISTER - This 8-bit register holds
information on communication errors, interface
data register status, match character conditions,
and communication equipment status. This
register may be read onto the DAL lines by a Read
operation.
DATA ACCESS LINES - The DAL Is an 8-bit bidirectional bus port over which all address, data,
control, and status transfers occur. In addition to
transferring data and control words the DAL lines
also transfer Information related to addressing of
the device, reading and writing requests, and
interrupting information.

SYNCHRONOUS MODE
Framing of characters Is carried out by a special
Synchronization Character Code (SYN) transmitted at the beginning of a block of characters.
The Receiver, when enabled, searches for two
continuous characters matching the bit pattern
contained in the SYN register. During the time the
Receiver is searching, data is not transferred to
the Receiver Holding Register, status bits are not
updated, and the Receiver interrupt is not activated. After the detection of the first SYN character, the Receiver assembles subsequent bits
into characters whose length is determined by
contents of the Control Register. If, after the first
SYN character detection, a second SYN character
is present, the Receiver enters the Synchronization mode until the Receiver Enable Bit is turned
off. If a second successive SYN character is not
found, the Receiver reverts back to the Search
mode.
In the Synchronous mode a continuous stream of
characters are transmitted once the Transmitter is
enabled. If the Transmitter Holding Register is not
loaded at the time the Transmitter Register has
completed transmission of a character, this idle
time will be filled by a transmission of the character contained in the SYN register in the Nontransparent mode, or the characters contained in
the DLE and SYN registers respectively while in
the Transparent mode of operation.

ASTRO OPERATION
ASYNCHRONOUS MODE
Framing of asynchronous characters is provided
by a Start bit (logic low) at the beginning of a character and a Stop bit (logic high) at the end of a
character. Reception of a character is initiated on
recognition of the first Start bit by a positive transition of the receiver cloc'k, after a preceding Stop
bit. The Start and Stop bits are stripped off while
assembling the serial input into a parallel
character.
The character assembly is completed by the
reception of the Stop bit after reception of the last
character bit. If this bit is a logic high, the character is determined to have correct framing and
the ASTRO is prepared to receive the next character. If the Stop bit is a logic low the Framing
Error Status flag Is set and the Receiver assumes
this bit to be the Start bit of the next character.
Character assembly continues from this point If
the Input is still a logic low when sampled at the
theoretical center of the assumed Start bit. As
long as the Receive input is spacing, all zero characters are assembled and error flags and data
received interrupts are generated so that line
breaks can be determined. After a character of all
zeroes is assembled along with a zero In the Stop
bit location, the first received logic high is determined as a Stop bit and this resets the Receiver
circuit to a Ready state for assembly of the next
character.

DETAILED OPERATION
Receiver - The Receiver Data input is clocked
into the Receiver Register by a lX Receiver Clock

input is a logic low. Information is normally transferred from the Transmitter Holding Register to
the Transmitter Register when the latter has completed transmission of a character. However,
information in the OLE register may be transferred
prior to the information contained in the Transmitter Holding Register if the Force OLE signal
condition is enabled (Bits 5 = Force OLE and 6 =
TX Transparent of Control Register 1 set to a logic
one). The control bit CR15 must be set prior to
loading of a new character in the transmitter hold·
ing register to insure forcing the OLE character
prior to transmission of the data character. The
Transmitter Register output passes through a flipflop which delays the output by one clock period.
When using the 1X clock generated by the Modem
Data Set, the output data changes state on the
negative clock transition and the delay is one bit
period. When using a local 32X clock the transmitter section selects one of the four selected
rate inputs and divides the clock down to the baud
rate. This clock is phased to the Transmitter Holding Register empty flag such that transmission of
characters occurs within two clock times of the
loading of the Transmitter Holding Register when
the Transmitter Register is empty.
When the Transmitter is enabled, a Transmitter
interrupt is generated each time the Transmitter
Holding Register is empty. If the Transmitter
Holding Register is empty when the Transmitter
Register is ready for a new character the Transmitter enters an idle state. During this idle time a
logic high will be presented to the Transmitted
Data output in the Asynchronous mode or the
contents of the SYN register will be presented in
the Synchronous Non-transparent mode
(CR16 =0). In the Synchronous Transmit Transparent mode (enabled by Bit 6 of Control Register
1 = Logic 1), the idle state will be filled by a OLE·
SYN character transmission in that order. When
entering the Transparent mode the DLE·SYN fill
will not occur until the first forced OLE.
If the Transmitter section is disabled by a reset of
the Request to Send, any partially transmitted
character is completed before the transmitter
section of the ASTRO is disabled. As soon as the
CTS goes high the transmitted data output will go
high.
When the Transmit parity is enabled, the selected
Odd or Even parity bit is inserted into the last bit
of the character in place of the last bit of the
Transmitted Register. This limits transfer of character information to a maximum of seven bits plus
parity or eight bits without parity. Parity cannot be
enabled in the Synchronous Transparency mode.

from a modem Data Set, or by a local 32X bit rate
clock selected from one of four externally supplied clock inputs. When using the 1X clock, the
Receiver Data is sampled on the positive transition of the clock in both the Asynchronous and
Synchronous modes. When using a 32X clock in
the Asynchronous mode, the Receive Sampling
Clock Is phased to the Mark-To-Space transition
of the Received Data Start bit and defines,
through clock counts, the center of each received
Data bit within + 0%, - 3% at the positive transition 16 clock periods later.
In the Synchronous mode the Sampling Clock is
phased to all Mark-To-Space transitions of the
Received Data inputs when using a 32X clock.
Each transition of the data causes an incremental
correction of the Sampling Clock by 1/32nd of a bit
period_ The Sampling Clock can be immediately
phased to every Mark-To-Space Data transition by
setting Bit 4 of Control Register 1 to a logic high,
while the Receiver is disabled.
When the complete character has been shifted
Into the Receiver Register it is then transferred to
the Receiver Holding Register; the unused, higher
number bits are filled with zeroes. At this time the
Receiver Status bits (Framing Error/Sync Detect,
Parity Error/OLE Detect, Overrun Error, and Data
Received) are updated in the Status Register and
the Data Received interrupt is activated_ Parity
Error is set, if encountered while the Receiver
parity check is enabled in the Control Register.
Overrun Error Is set if the Data Received status bit
Is not cleared through a Read operation by an
external device when a new character is ready to
be transferred to the Receiver Holding Register.
This error flag indicates that a character has been
lost, as new data Is lost and the old data and Its
status flags are saved.
The characters assembled in the Receiver
Register that match the contents of the SYN or
OLE register are not loaded into the Receiver
Holding Register, and the DR interrupt is not generated, if Bit 3 of Control Register 2 (CR23 = SYN
Strip) or Bit 4 of Control Register 1 (CR14 = OLE
Strip) are set respectively, the SYN-DET and OLE·
DET status bits are set with the next non SYN or
OLE character. When both CR23 and CR14 are set
(Transparent mode), the DLE-SYN combination is
stripped. The SYN comparison occurs only with
the character received after the OLE character. If
two successive OLE characters are received only
the first OLE character is stripped. No parity
check is made while in this mode.
Transmitter - I nformation is transferred to the
Transmitter Holding Register by a Write operation. Information can be loaded into this register
at any time, even when the Transmitter is not
enabled. Transmission of data is initiated only
when the Request To Send bit is set to a logiC one
In the Control Register and the Clear To send

DEVICE PROGRAMMING

The two 8-bit Control Registers of the ASTRO determine the operative conditions of the ASTRO chip.
Control Register 1 is shown in the following table.

CONTROL REGISTER 1
Control Register 1
Bit 7 - A logic 0 configures the ASTRO into an
Internal Data and Control Loop mode and disables
the Ring interrupt. In this diagnostic mode the following loops are connected internally:
a. The Transmit Data is connected to the Receive
Data with the TD pin held in a Mark condition
and the input to the RD pin disregarded.
b. With a 1X clock selected, the Transmitter
Clock also becomes the Receive Clock.
c. The Data Terminal Ready (5fR) Control bit is
connected to the Data Set Ready (DSR) input,
with the DTR output in held in an Off condition
(logic high), and the DSR input pin is
disregarded.
d. The Request to Send Control bit is connected
to the Clear To Send (CTS) and Carrier Detector
inputs, with the RTS output pin held in an Off
condition (logic high), and the CTS and Carrier
Detector input pins are disregarded.
e. The Miscellaneous pin is held in an Off (logic
high) condition.
A logic 1 on Bit 7 enables the Ring interrupt and
returns the ASTRO to the normal full duplex
configuration.
Bit 6 - In the Asychronous mode a logic 1 holds
the Transmitted Data output in a Spacing (Logic 0)
condition, starting at the end of any current transmitted character, when the Transmitter is
enabled. Normal Transmitter timing continues so
that this Break condition can be timed out after
the loading of new Gharacters into the Transmitter
Holding Register.
, In the Synchronous mode a logic 1 sets the TransI mitter in a transparent transmission which implies
: that idle transmitter time will be filled by DLE·SYN
i character transmission and a DLE can be forced
i ahead of any character in the Transmitter Holding

Register when CR15 is a logic one in the sync
mode.
Bit 5 - In the Asynchronous mode a logic 1, with
the Transmitter enabled, causes a single Stop bit
to be transmitted. A logic 0 causes 2·Stop bit
transmission for character lengths of 6,7, or 8 bits
and one·and·a·half Stop bits for a character length
of 5 bits.
With the Transmitter disabled this bit controls the
Miscellaneous output on Pin 19, which may be
used for Make Busy on 103 Data Sets, Secondary
Transmit on 202 Data Sets, or dialing on CBS Data
Couplers.
In the Synchronous mode a logic 1 combined with
a logic 0 on Bit 6 of Control Register 1 enables
Transmit parity; if CR15=0 or CR15= 1 no parity
is generated. When set to a logic 1 with Bit 6 also
a logic 1, the contents of the DLE register are
transmitted prior to the next character loaded in
the Transmitter Holding Register as part of the
Transmit Transparent mode.
Bit 4 - In the Asynchronous mode a logic 1
enables the Automatic Echo mode when the
receiver section is enabled. In this mode the
clocked regenerated data is presented to the
Transmit Data output in place of normal transmis·
sion through the Transmitter Register. This serial
method of echoing does not present any abnormal
restrictions on the transmit speed of the terminal.
Only the first character of a Break condition of all
zeroes (null character) is echoed when a Line
Break condition is detected. For all subsequent
null characters, with logic zero Stop bits, a steady
Marking condition is transmitted until normal
character reception resumes. Echoing does not
start until a character has been received and the
Transmitter is idle. The Transmitter does not have
to be enabled during the Echo mode.
In the Synchronous mode a logic 1, with the
Receiver enabled. does not allow assembled

Receiver data matching the DLE register contents
to be transferred to the Receiver Holding Register;
also, parity checking is disabled.
When the Receiver is not enabled this bit controls
the Miscellaneous output on Pin 19, which may be
used for New Sync on a 201 Data Set. When
operating with a 32X clock and a disabled
Receiver a logic 1 on this bit also causes the
Receiver timing to synchronize on Mark-To-Space
transitions.
Bit 3 - In the Asynchronous mode a logic 1
enables check of parity on received characters
and generation of parity for transmitted
characters.
In the Synchronous mode a logic 1 bit enables
check of parity on received characters only. Note:
Transmitter parity enable is controlled by CR15.
Bit 2 - A logic 1 enables the ASTRO to receive
data into the Receiver Holding Register, update
Receiver Status Bits 1,2, 3, and 4, and to generate
Data Received interrupts. A logic 0 disables the
Receiver and clears the Receiver Status bits.
Bit 1 - Controls the Request To Send output on
Pin 38 to control the CA circuit of the Data Set.
The RTS output is inverted from the state of CR11.
A logic 1 combined with a low logic Clear To Send
input enables the Transmitter and allows THRE
interrupts to be generated. A logic 0 disables the
Transmitter and turns off the external Request To
Send signal. Any character in the Transmitter
Register will be completely transmitted before the
Transmitter is turned off. The Request To Send
output may be used for other functions such as
"Make Busy" on 103 Data Sets.
Bit 0 - Controls the :D-a~ta~T-e-rm~in-a""I·R-e""'a"-d·y output
on Pin 16 to control the CD circuit of the Data Set.
A logic 1 enables the Carrier and Data Set Ready
interrupts. A logic 0 ena~ only the telephone
line Ring interrupt. The DTR output is inverted
from the state of CRlO.
Control Register 2
Control Register 2, unlike Control Register 1, cannot be changed at any time. This register should
be changed only while both the receiver and trans·
mitter sections of the ASTRO are in the idle state.

Bits 7·6- These bits select the character length
as follows:
Bits 7·6
Character Length
00
8 bits
01
7 bits
10
6 bits
11
5 bits
When parity is enabled it must be considered as a
bit when making character length selection, i.e. 5
character bits plus parity = 6 bits.
Bit 5 - A logic 1 selects the Synchronous Character mode. A logic 0 selects the Asynchronous
Character mode.
Bit 4 - A logic 1 selects odd parity and a logic 0
selects even parity, when parity is enabled by
CR13 and/or CR15.
Bit 3 - In the Asynchronous mode a logic 0
selects the rate 1-32X clock input (pin 30) as the
Receiver Clock rate and a logic 1 selects the same
clock rate for the Receiver as selected by Bits 2-0
for the Transmitter. This bit must be a logic 1 for
the IX clock selection by Bits 2-D.
In the SynChronous mode a logic 1 causes all DLESYN combination characters in the Transparent
mode when DLE strip CR14 is a logic 1. or all SYN
characters in the Non·transparent mode to be
stripped and no Data Received interrupt to be
generated. I he SYN Detect status bit is set with
reception of the next assembled character as it is
transferred to the Receiver Holding Register.
Bits 2·0 - These bits select the Transmit and
Receive clocks. The Input Clock to the Rate 4 pin
may be divided down to form the 32X clock from a
multiple clock as shown:
Bits 2·0
Clock
000
001

IX clock for Transmit and Receive
(Pins 35 and 34 respectively)
32X clock - Rate 1 input (Pin 30)

010

32X clock -

011

32X clock -

Rate 3 input (Pin 32)

100

32X clock -

Rate 4 input

101

32X clock 32X clock 32X clock -

Rate 4 input ~ 2 (Pin 33)
Rate 4 input _ 4 (pin 33)
Rate 4 input ~ 8 (pIn 33)

110
111

CONTROL REGISTER 2

Rate 2 input (Pin 31)
~

1 (Pin 33)

Status Register
The data contained in the Status Register define
Receiver and Transmitter data conditions and
status of the Data Set. The Status word is shown
and defined below.
Bit 7 - This bit is set to a logic 1 whenever there
is a change in state of the Data Set Ready or Car·
rier Detector inputs while Data Terminal Ready
IBg 0 {f Control Registe~ 1) is a logic 1 or the.~
n Ica or is turned on, with DTR a logic O. ThiS bit
is cleared when the Status Register is read onto
the Data Access Lines.
Bit 6 - This bit is the logic complement of the
Data Set Ready input on Pin 28. With 202·type
Data Sets it can be used for Secondary Receive.
Bit 5 - This bit is the logic complement of the
Carrier Detector input on Pin 29.
Bit 4 - In the Asynchronous mode a logic 1 indio
cates that received data contained a log 0 bit after
the last data bit of the character in the stop bit
slot while the Receiver was enabled. This indio
cat~s a Framing error. This bit is set to a logic 0 if
the proper logic 1 condition for the Stop bit was
detected.
In the Synchronous mode a logic 1 indicates that
the contents of the Receiver Register matched the
contents of the SYN Register. The condition of
this bit remains for a full character assembly time.
If SYN strip (CR23) is enabled this status bit is
updated with the character received after the SYN
character. In both modes the bit is cleared when
the Receiver is disabled.
Bit 3 - When the OLE Strip is enabled (Bit 4 of
Control Register 1) the Receiver parity check is
disabled and this bit is set to a logic 1 if the pre·
vious character to the presently assembled char·
acter matched the contents of the DLE register;
otherwise it is cleared. The DLE DET remains for
one character time and is rest on the next char·
acter transfer or on a Status Register Read. If DLE
Strip is not enabled this bit is set to a logic 1 when
the Receiver is enabled, Receiver parity (Bit 3 of
Control Register 1) is also enabled, and the last
received character has a Parity error. A logic 0 on
this bit indicates correct parity. This bit is cleared
in either of the above modes when the Receiver is
disabled.
Bit 2 - A logic 1 indicates an Overrun error which
occurs if the previous character in the Receiver
Holding Register has not been read and Data

Received is not reset, at the time a new character
is to be transferred to the Receiver Holding
Register. This bit is cleared when no Overrun condition is detected, i.e., the next character transfer
time or when the Receiver is disabled.
Blt1 - A logic 1 indicates that the Receiver Hold·
ing Register is loaded from the Receiver Register,
if the Receiver is enabled. It is cleared to a logic 0
when the Receiver Holding Register is read onto
the Data Access Lines, or the Receiver is
disabled.
Bit 0 - A logic 1 indicates that the Transmitter
Holding Register does not contain a character
while the Transmitter is enabled. It is set to a logic
1 when the contents of the Transmitter Holding
Register is transferred to the Transmitter
Register. It is cleared to a 0 bit when the Trans·
mitter Holding Register is loaded from the DAL, or
when the Transmitter is disabled.
INPUT/OUTPUT OPERATIONS
All Data Control, and Status words are transferred
over th~ Data Access Lines (DAL 0·7). Additional
input lines provide controls for addressing a par·
ticular unit, and regulating all input and outp~t
operations. Other lines provide interrupt capabll·
ity to indicate to a Controller that an input opera·
tion is requested by the ASTRa. All input/output
terminology below is referenced to the Controller
so that a Read or Input takes data from the ASTRa
and places it on tfle DAL lines, while a Write or
Output places data from the DAL lines into the
ASTRa.
Read
A Read Operation is initiated by the placement of
an eight-bit address on the DAL by the Controller.
When the Chip Select signal goes to a logic low
state, the ASTRa compares Bits 7·3 of the DAL
with its hard·wired ID code (Pins 17,22,24,25, and
26) and becomes selected on a Match condition.
The ASTRa then sets its REPLY line low to ack·
nowledge its readiness to transfer data. Bits 2·0 of
the address are used to select ASTRa registers to
read from as follows:
Bits 2·0
Selected Register
000
Control Register 1
010
Control Register 2
100
Status Register
110
Receiver Holding Register
When the Read Enable (RE) line is set to a logic
low condition by the Controller the ASTRa gates

STATUS REGISTER

4. Carrier Off - Indicates Carrier Detector input
goes high when DTR is on.

the contents of the addressed register onto the
OAL. The Read operation terminates, and the
devices becomes unselected, when both the Chip
Select and Read Enable return to a logic high con·
dition. Reading of the Receiver Holding Register
clears the DR Status bit. Bit 0 must be a logic low
in read or write operations.
Write
A Write operation is initiated by the placement of
an eight·bit address or the OAL by the Controller.
The ASTRa compares Bits 7·3 of the DAL with its
10 code when the Chip Select input goes to a logic
low state. If a Match condition exists, the device
is selected and makes it RPLY line low to ack·
nowledge its readiness to transfer data. Bits 2·0 of
the address are used to select ASTRa registers to
be written into as follows:
Bits 2-0
000
010
100
110

5. DSR On - Indicates the Data Set Ready input
goes low when DTR is on.
6. DSR Off - I ndicates the Data Set Ready input
goes high when DTR is on.
7. Ring On - Indicates the Ring Indicator input
goes low when DTR is off.
Each time an Interrupt condition exists the INTR
output from the ASTRa is made a logic low. The
following interrupt procedure is then carried out
even if the interrupt condition is removed.
The Controller acknowledges the Interrupt
request by setting the Chip Select (CS) and the
Interrupt Acknowledge Input (iACKl) to the
ASTRO to a Low state. On this transition all noninterrupting devices receiving the IACKI set their
Interrupt Acknowledge Output (IACKO) low, enabling lower priority daisy-chained devices to
respond to the Interrupt request. The highest
priority device that is interrupting will then set its
RPL Y low. This device places its 10 code on Bit
Positions 7-3 of the DAL when a low RE signal is
received. In addition Bit 2 is set to a logic one if
any of the interrupt numbers 1 and 3·7 above
occurred, and remains a logic low if the THRE has
caused the interrupt (see note).

Selected Register
Control Register 1
Control Register 2
SYN and OLE Register
Transmitter Holding Register

When the Write Enable (WE) line is set to a logic
low condition by the Controller the ASTRa gates
the data from the DAL into the addressed register.
If data is written into the Transmitter Holding
Register, the THRE Status bit is cleared to a logic
zero.
The 100 address loads both the SYN and OLE
registers. After writing into the SYN register the
device is conditioned to write into the OLE if followed by another Write pulse with the 100
address. Any intervening Read or Write operation
with other addresses resets this condition such
that the next 100 will address the SYN register.

To reset the Interrupt condition (INTR) Chip Select
(CS) and IACKI must be received.2Y the ASTRa. A
setup time must exist between CS and the ~ or
WE signals to allow chip selection prior to
read/write operations and deselection control
through the latter signals. The data is removed
from the DAL when the RE signal returns to the
logic high state.

Interrupts
The following conditions generate interrupts:

MAXIMUM RATINGS

1. Data Received (DR) - Indicates transfer of a
new character to the Receiver Holding Register
while the Receiver is enabled.
2. Transmitter Holding Register Empty (THRE) Indicates that the THR register is empty while
the Transmitter is enabled. The first interrupt
occurs when the Transmitter becomes enabled
if there is an empty THR, or after the character
is transferred to the Transmitter Register
making the THR empty.

VDO With Respect to VBB
(Ground)

+ 20 to - 0.3V

Max Voltage To Any Input With
Respect to VBB

+ 20 to - 0.3V

Operating Temperature
Storage Temperature

3. Carrier On - Indicates Carrier Detector input
goes low when DTR is on.

Power Dissipation

O·C to 70 ·C
Plastic

-55°C to +125°C

Ceramic

-65°C to +150°C
1000 mW

NOTE:
The UC1671-1 places Data Received on DAL 1 and THRE on DALOduring interrupt servicing. The UC1671-0 places the DAL 1 and DALO into
a Three State Mode during interrupt.

OPERATING CHARACTERISTICS
TA = o'e to 70 'e, VDD

= + 12.0V ±

.6V, Vss = - 5.0 ± .25V, Vss = OV, Vee = + 5V ± .25V

AC CHARACTERISTICS
TA = o'e to 70 'e, VDD = + 120V ± 0.6V, Vss = - 5.0V ± 0.25V, Vee = + 5.0 ± .25V, Vss = OV
eLMAX = 20 pi

~--,.",-)-----X
:.:;~~"h':::::::::~:::'~ ;;:,'.~:,~'::;::

"",0."

v.' ......,_," '"."'. 'Q"'" , ...

READ CYCLE TIMING DIAGRAM

WRITE CYCLE TIMING DIAGRAM

INTERRUPT
SYMBOL

CHARACTERISTIC

TCSRE

CS 10 IACKI Delay
CS to RE Delay

TCSREH

CS and RE Overlap

TRECS

RE to CS

TCSI

MIN

TYP

MAX

UNITS

0
250

Spacing

250

Tpi

IACKI Pu Ise Width

200

TIAD

lACK I to Valid 10
Code Delay

TRED
TIARL
TCSRLF

CS to RPLY OFF Delay

TIAIH

IACKI ON to INTR OFF
Delay

250

RE OFF to DAL Open Delay

160

lACK I to RPL Y Delay

250

CONDITIONS

250

300

IACKI to IACKO Delay

200

IACKO OFF Delay
From CS OFF. RE OFF. or
IACKI HIGH.

250

See Note 1.

See Note 2.

Note 1: If FIE goes low after IACKI goes low, the delay will be from the falling edge of RE.
Note 2: IACKO goes false after the last one of the following three signals go false: CS, RE and
lACK!. TIOFF is measured from the last signal going false.

Note 1

INTERRUPT CYCLE TIMING DIAGRAM

DALO must be a logic high during CS to form
an Interrupt Cycle Address during Daisy Chain
Interrupt Response.

RECEIVER SECTION

ASYNCHRONOUS

SYNCHRONOUS

TRANSMITTER SECTION

~:. C::::Er:::::J
UC1671A CERAMIC PACKAGE

UC1671B PLASTIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights 01 third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL
COR

ION

3128 REDHILL AVENUE,BOX 2180
CA 92663 (714) 557-3550, TWX 910-595-1139

1 NEWPORT BEACH,

WESTERN
DIGITAl.
p

WD1931 Asynchronous/Synchronous Receiver/Transmitter
FEATURES

BAUD RATE - DC TO 1M BAUD/SEC
8 SELECTABLE CLOCK RATES
o Accepts 1X Clock ad Up to Four Different
32X Baud Rate Clock Inputs
.. Up to 47% Distortion Allowance with 32X Clock
PINOUT COMPATIBLE TO SD1933 FOR
MULTI PROTOCOL BOARD APPLICATIONS

SYNCHRONOUS AND ASYNCHRONOUS
o Full Duplex Operations
SYNCHRONOUS MODE
Selectable 5- to 8-Bit Characters
It Two Successive SYN Characters Sets
Synchronization
• Programmable SYN and OLE Character
Detection and Stripping
o Programmable SYN and DLE-SYN Fill
o Transparent BI-SYNC Operation
It

APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS

ASYNCHRONOUS MODE
• Selectable 5- to 8-Bit Characters
" Line Break Detection and Generation
" 1-, 1'/,-, or 2-Stop Bit Selection
o False Start Bit Detection
It Automatic Serial Echo Mode
o Overrun and Framing Error Detection

GENERAL DESCRIPTIONS
The WD1931 is a MOS/LSI device which performs
the functions of interfacing a serial data communications channel to a parallel digital system. Thisdevice
is capable of full duplex communications with
asynchronous and/or synchronous systems. Western Digital has made device pin assignments for the
WD1931 to make it compatible with the WD1933
(Synchronous Data Link Controller). This pin out
allows the user to implement a one-board multiprotocol design. For character-oriented asynchronous
and/or synchronous (bi-sync) protocols, the
WD1931 is used, and for bit-oriented SOLe, HDLC
and ADCCP protocols the WD1933 is used (see
WD1933 data sheet).

SYSTEM COMPATIBILITY
Double Buffering of Data
o 8-Bit Bi-Directional Bus for Data, Status, and
Control Words
It
All Inputs and Outputs TTL Compatible
o Chip Select, RE, WE, AO, A1 Interface to CPU
.. On-Line Diagnostic Capability
• Data Set, Carrier Detect, and Ring Interrupts
G

vee 1'5)
CAR5
H4

iX'i'C
RSCLK

VDD

~'12V)

PIN CONNECTIONS

I" I, 15 I~

WD1931 BLOCK DIAGRAM

Illl

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

No connection; see Note 4.

No internal connection.

READ ENABLE

When this line is low the device, if selected, gates the
contents of the addressed register on the DAL.

CHIP SELECT

The chip is selected when this signal is low.

MISCELLANEOUS OUT

CS
MISCOUT

INTERRUPT

INTRQ'

This output is made high when one of the interrupt
conditions occurs. Reading the Status Register
resets this signal.

WRITE ENABLE

This output is controlled by Bit 5 of Control Register
1 when in the Asynchronous mode and by Bit 4 when
in the Synchronous mode. (See Note 1.)

When this line is low the device, if selected, accepts
the data on the DAL and gates it into the addressed
register.

DATA ADDRESS LINES

DALO-DAL7 Eight-bit Bi-directional bus for transfer of data, control and status information. Active low.

MASTER RESET

The Control and Status Registers and other controls
are cleared when this input is low.

DATA TERMINAL
READY

DTR

This output is controlled by Bit 0 of Control Register
1 and is intended to control Circuit CD of the data set.

DATA REQUEST OUT

DRQO'

This output is made high when the THR is empty
while the transmitter is enabled. Loading the THR
resets this signal.

DATA REQUEST IN

DRQI'

This output is made high when the RHR is full while
the receiver is enabled. Reading the RHR resets this
signal.

POWER SUPPL Y

VSS

Ground

No internal connection.

ADDRESS 0

This input is the low-order address bit for register
selection.

ADDRESS 1

Ai"

This input is the high-order address bit for register
selection,

8-15

POWER SUPPLY

VDD

+12V

TRANSMITTED DATA

This output is the transmit serial data, This output is
held in a MARKING condition when the transmitter is
not enabled, It is intended to control Circuit BA of the
data set.

RECEIVER TIMING

lXRC

This input is the receiver 1X clock, when used, It is intended to be derived from Circuit DC of the data set.
The Received Data is sampled on the positive transition of this signal.

RECEIVED DATA

This input is the receive serial data and is intended to
be derived from Circuit BB of the data set.

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

TRANSMITTER BYTE
OUTPUT COMPLETE

TBOC

This output goes high after the last bit of a byte is
transmitted including parity if enablap, and is valid for
one bit period. See Note 2.

CLEAR TO SEND

CTS

This input enables the transmitter when low and is
intended to be derived from Circuit CB of the data set.

RECEIVER CLOCK

RSCLK

This output goes high when the receiver data is
sampled, and is valid for one clock period. See Note 2.

TRANSMITTER TIMING

1XTC

This input is the transmitter 1X clock when used. It is
intended to be derived from Circuit DB of the data set.
The Transmitter changes on the negative transition of
this signal.

REQUEST TO SEND

RTS

This output is controlled by Bit 1 of Control Register 1
and is intended to control Circuit CA of the dataset. If
Bit 1 of Control Register 1 is reset during a transmission then RTS will go high on the falling edge of the
transmitter clock that follows the last bit of the current transmission character.

DATA SET READY

DSR

This input appears as Status Bit 6 and generates interrupts when going on or off if DTR is on. It is intended
to be derived from Circuit CC of the data· set.

RING INDICATOR

RING

This input generates an interrupt when made low with
DTR off. It is intended to be derived from Circuit CE of
the data set.

RATES

R1-R4

These four rate inputs are used for 32X-256X Local
Transmit and Receive clocks. The rate is selected by
the Control Register. (See Note 3.)

CARRIER DETECTOR

CARD

This input appears as Status Bit 5 and generates interrupts when going on or off if DTR is on. It is intended
to be derived from Circuit CF of the daa set.

POWER SUPPLY

VCC

+5V

35-38

• THE WD1931 OUTPUTS, INTRa, ORal, and DROO ARE TRUE HIGH (TRUE~ Vo H) OUTPUTS.
ON THE UC1671, THESE OUTPUTS ARE TRUE LOW (TRUE ~ VoLl AND OPEN DRAIN.

NOTE 1:

If the system design does not make use of MISC IN on theWD1933, the user may tie this to
+12V without harm or degradation to theWD1933. This has the same effect as a logic high
input. If the system design does make use of MISC IN, then provisions must be made to
select +12V when the WD1931 is in the socket or MISC IN when theWD1933 is in the socket.
This may be accomplished by a small switch or by jumpers.

NOTE 2:

The outputs TBOC and RSCLKon the WD1931 may be tied to ground or to +5 volts through a
10K pull-up without harm or degradation to the WD1931.

NOTE 3:

If R1-R4 are not selected by the command word in the WD1931, then anything may be on
these inputs. If AT and CD are tied high on the WD1933, then the inputs (pins35-38) may have
anything on them. When both the rate fields in the WD1931 and RI and CD on theWD1933 are
used, the system designer must make provisions by an external switch or jumpers.

NOTE 4:

Pin 1 of the device must not be connected in any way to any signal, poweror ground line. This
pin is the output of an internal Back Bias Generator, and is used for testing only.

ORGANIZATION

Receiver Register.

The WD1931 block diagram is illustrated on page 1.
The primary sections include the control, buffer, status, receiver, transmitter, comparison and sync
registers.

This 8-bit shift register inputs the received data at a
clock rate determined by the Control Register. This
incoming data is assembled to the selected character length and then transferred to the Receiver Holding Register with logic zeroes filling out any unused
high-order bit positions.

Control Registers.
There are two a-bit Control Registers which hold
device programming signals such as mode selection, clock selection, interface signal control, and
data format. Each of the Control Registers can be
loaded from the DAL lines by a Write operation or
read onto the DAL lines by a Read operation. The
registers are cleared by a Master Reset.
Receiver Holding Register.
This a-bit parallel buffer register presents assembled
receiver characters to the DAL bus lines when
requested through a Read operation.
Status Register.
This a-bit register holds information on communication errors, interface data register status, match
character conditions, and communication equipment status. This register may be read onto the DAL
lines by a Read operation.
OLE Register.
This 8-bit register is loaded from the DAL lines by a
Write operation and holds the OLE character used in
the Transparent mode of operation in which an idle
transmit period is filled with the combination DLESYN pair of characters rather than a single SYN
character. I n addition the WD1931 may be programmed to force a single OLE character priorto any
data character transmission while in the transmitter
transparent mode. This register cannot be read onto
the DAL lines. It must be loaded with logic zeroes in
all unused high-order bits.
SYN Register.
This 8-bit register is loaded from the DAL lines by a
Write operation and holds the synchronization code
used to establish receiver character synchronization. It serves as a fill character when no new data is
available in the Transmitter Holding register during
transmission. This register cannot be read onto the
DAL lines. It must be loaded with logic zeroes in all
unused high-order bits.
Transmitter Holding Register.
This 8-bit parallel buffer register holds parallel transmitted data transferred from the DAL lines by a Write
operation. This data is transferred to the Transmitter
Register when the transmitter section is enabled and
the Transmitter Register is ready to send new data.

Transmitter Register.
This 8-bit shift register is loaded from the Transmitter Holding Register, SYN register, or OLE register.
The purpose of this register is to serialize data and
present it to the transmitted Data output.
Comparator.
The 8-bit comparator is used in the Synchronous
mode to compare the assembled contents of ti',o
Receiver Register and the SYN registeror OLE register. A match between the registers sets up stripping
of the received character, when programmed, by
preventing the data from being loaded into the
Receiver Holding Register. A bit in the Status Register is set when stripping is performed. The comparator output also enables character synchronization of
the Receiver on two successive matches with the
SYN register.
Data Access Lines.
The DAL is an 8-bit bi-directional bus port over
which all data, control, and status transfers occur.
WD1931 OPERATION
Asynchronous Mode
Framing of asynchronous characters is provided by
a Start bit (logic zero) at the beginning of a character
and a Stop bit (logic one) at the end of a character.
Reception of a character is initiated on recognition
of the first Start bit after a preceding Stop bit. The
Start and Stop bits are stripped off while assembling
the serial input into a parallel character. If enabled,
the parity bit is checked and then stripped off.
The character assembly is completed by the reception of the Stop bit after reception of the last character bit. If this bit is a logic one the character is
determined to have correct framing and the WD1931
is prepared to receive the next character. If the Stop
bit is a logic zero the Framing Error Status flag is set
and the Receiver assumes this bit to be the Start bit
of the next character. Character assembly continues
from this point if the input is still a logic zero when
sampled at the theoretical center of the assumed
Start bit. As long as the Receive input is spacing, all
zero characters are assembled and error flags and
data received interrupts are generated so that line
breaks can be determined. After a character of all
zeroes is assembled along with a zero in the Stop bit
location, the first received logic one is determined as

enters the Synchronization mode until the Receiver
Enable Bit is turned off. If a second successive SYN
character is not found, the Receiver reverts back to
the Search mode.

a Stop bit and this resets the Receiver circuit to a
Ready state for assembly of the next character.
In the Asynchronous mode the character transmission occurs when information contained in the Tranmitter Holding Register is transferred to the
Transmitter Register. Transmission is initiated by
the insertion of a Start bit, followed by the serial output of the character (least significant bit first) with
parity, if enabled, following the most significant bit;
then the insertion of a 1-, 1.5-, or 2-bit length Stop
condition. If the Transmitter Holding Register is full
the next character transmission starts after the
transmission of the Stop bit(s) of the present character in the Transmitter Register. Otherwise, the Mark
(logic one) condition is continually transmitted until
the Transmitter Holding Register is loaded.

In the Synchronous mode a continuous stream of
characters are transmitted once me Transmitter is
enabled. If the Transmitter Holding Register is not
loaded at the time the Transmitter Register has
completed transmission of a character, this idle time
will be filled by a transmission of the character contained in the SYN register in the Non-transparent
mode, or the characters contained in the DLE and
SYN registers respectively while in the Transparent
mode of operation.
DETAILED OPERATION
Receiver

In order to allow re-transmission of data received at a
slightly faster character rate, means are provided for
shortening the Stop bit length to allow transmission
of characters to occur at the same rate as the reception of characters. The Stop bit may be shortened a
maximum of 1/16 of a bit period for 1-Stop bit selection and 3/16 of a bit period for 1.5-", or 2-Stop bit
selection. To shorten the Stop bit the user must load
the Transmitter Holding Register exactly (X+2) 16ths
of a bit period before the end of a stop bit transmission, where X= the number of 16ths the user wishes
to strip. If X+2 exceeds the maximum then no shortening occurs. This feature does not work in 1X
clocking mode.

The Receiver Data input is clocked into the Receiver
Register by a 1X Receiver Clock from a modem Data
Set, or by a local32X bit rate clock selected from one
of four externally supplied clock inputs. When using
the 1X clock, the Receiver Data is sampled on the
positive transition of the clock in both the Asynchronous and Synchronous modes. When using a 32X
clock in the Asynchronous mode, the Receive Sampling Clock is phased to the Mark-To-Space transition of the Received Data Start bit and defines,
through clock counts, the center of each received
Data bit within +0%, -3% at the positive transition 16
clock periods later.

"NOTE: As a special case, the 1.5 stop bit mode
can be shortened from 1/24 to 11/24 of the
whole period if the Transmitter Holding
Register is loaded (X + 2) 24ths (of the
whole period) before the end of the stop bit

In the Synchronous mode the Sampling Clock is
phased to all Mark-To-Space transitions of the
Received Data inputs when using a 32X cloCk. Each
transition of the data causes an incremental correction of the Sampling Clock by 1/32nd of a bit period.
The Sampling Clock can be immediately phased to
every Mark-To-Space Data transition by setting Bit
4 of Control Register 1 to a logic one while the
Receiver is disabled.

transmission.

When the complete character has been s"ifted into
the Receiver Register it is then transferred to the
Receiver Holding register. The unused higher
number bits are filled with zeroes. At this time the
Receiver Status bits (Framing Error/Syc Detect,
Parity Error/DLE Detect, Overrun Error, and Data
Received) are updated in the Status Register and
the Data Received interrupt is activated. Parity Error
is set, if encountered, if the Receiver parity check is
enabled in the Control Register. Overrun Error is set
if the Data Received status bit is not cleared through
a Read operation by an external device when a new
character is ready to be transferred to the Receiver
Holding Register. This error flag indicates that a
character has been lost. New data is lost and the old
data and its status flags are saved.

Synchronous Mode
Framing of characters is carried out by a special
Synchronization Character Code (SYN) transmitted
at the beginning of a block of characters. The
Receiver, when enabled, searches for two continuous characters matching the bit pattern contained
in the SYN register. During the time the Receiver is
searching, data is not transferred to the Receiver
Holding Register, status bits are not updated, and
the Receiver interrupt is not activated. After the
detection of the first SYN character, the Receiver
assembles subsequent bits into characters whose
length is determined by contents of the Control
Register. If, after the first SYN character detection, a
second SYN character is present, the Receiver

The characters assembled in the Receiver Register
that match the contents of the SYN or DLE registers
are not loaded into the Receiver Holding Register
and the DR interrupt is not generated if Bit 3 of Control Register 2 (CR23= SYN Strip) or Bit 4 of Control
Register 1 (CR14=DLE Strip) are set respectively.
The SYN-DET and DLE-DET status bits are set with
the next non-SYN or DLE character. When both
CR23 and CR14 are set (Transparent mode). the
DLE-SYN combination is stripped. The SYN comparison occurs only with the character received
after the DLE character. If two successive DLE characters are received only the first DLE character is
stripped. No parity check is made while in this
mode.
Transmitter
Information is transferred to the Transmitter Holding Register by a Write operation, Information can be
loaded into this register at any time, even when. the
Transmitter is not enabled, Transmission of data is
initiated only when the RequestTo Send bit is setto a
logic one in the Control Register and the Clear To
Send input is a logic zero. Information is normally
transferred from the Transmitter Holding Register to
the Transmitter Register when the latter has completed transmission of a character. However, information in the DLE register may be transferred prior
to the information contained in the Transmitter
Holding Register if the Force DLE signal condition is
enabled (Bits 5=Force DLE and 6=TX Transparent of
Control Register 1 set to a logic one). The control bit
CR1S must be set prior to loading of a new character
in the transmitter holding register to ensure forcing
the DLE character prior to transmission of the data
character. The Transmitter Register output passes
through a flip-flop which delays the output by one
clock period. When'using the lX clock generated by
the Modem Data Set the output data changes state
on the negative clock transition and the delay is one
bit period. When using a local32X clock the transmitter section selects one of the four selected rate
inputs and divides the clock down to the baud rate.
This clock is phased to the Transmitter Holding Register empty flag such that transmission of characters
occurs within two clock times of the loading of the
Transmitter Holding Register when the Transmitter
Register is empty.
When the Transmitter is enabled, a Transmitter
interrupt is generated each time the Transmitter
Holding Register is empty. If the Transmitter Holding Register is empty when the Transmitter Register·
is ready for a new character the Transmitter enters
an idle state. During this idle time a logic one will be
presented to the Transmitted Data output in the
Asynchronous mode or the contents of the SYN reg-

ister will be presented in the Synchronous Nontransparent mode (CR16=0). In the Synchronous
Transmit Transparent mode (enabled by Bit 6 of
Control Register 1=Logic 1), the idle state will be
filled by a DLE-SYN character transmission in that
order. When entering the Transparent mode the
DLE-SYN fill will not occur until the first forced DLE.
If the Transmitter section is disabled by a reset of the
Request to Send, any partially transmitted character
is completed before the transmitter section of the
WD1931 is disabled. As soon as the CTS goes high
the transmitted data output will go high.
When the Transmit parity is enabled, the selected
Odd or Even parity bit is inserted into the last bit of
the character in place of ttie last bit of the Transmitter Register. This limits transfer of character information to a maximum of seven bits plus parity or
eight bits without parity. Parity cannot be enabled in
the Synchronous Transparency mode.

CLOCKING
Two clocking schemes are used. In one case a 1X
Receiver Timing and Transmitter Timing are input
from a Data Set and are used to clock their respective
data. In the second case a local 32X clock is phased
to the data and used to clock the data. The device is
capable of selecting from four externally supplied
rates.
The use of the 1X clock is the same for the receiver
and the transmmitter in both the Synchronous and
Asynchronous Character modes.
The use of the 32X clock in the receiver differs
depending on mode. In the Asynchronous Character
mode the receive sampling clock is phased to the
mark-space transition of Received Data input at the
beginning of the Start bit, causing the Sampling
clock to be approximately in the middle of the bit.
The accuracy of sampling is +0%, -3%. I n the Synchronous Character mode the Receive Sampling
clock is phased to all the mark-space transitions on
the Received Data input. Each such transition of the
data causes an incremental cor rection of the Sampling clock of 1/32 of the bit reriod. The Sampling
clock can be immediately phased with the data transitions by setting Bit 4 of Control Register 1 to a 1 bit
with the receiver disabled. As long as this bit is a one
the Sampling clock is locked to every mark-space
data transition.
The transmitter divides the selected rate input down
to the baud rate. This clock is phased to the THRE
flag so that character transmission starts within two
clocks of the THR loading when the transmitter is
idling.

RECEIVER FLOW CHART

TRANSMITTER SECTION (ASYNCHRONOUS)

TRANSMITTER SECTION (SYNCHRONOUS)

TRANSMITTER FLOW CHART

data from the device and places it on the DAL, while a
Write or Output places data from the DAL into the
device.

AUTO ECHO FEATURE

The device is capable of serially echoing the
received data with a one bit delay when in the
Asynchronous mode and the Receiver on. This
causes the clocked regenerated received data to be
presented to the Transmit Data output rather than
the output of the Transmitter Register or a steady
marking. This serial method of echoing does not
present any abnormal restrictions on the transmit
speed of the terminal. Breaks are not echoed back.
When the device detects a Zero Stop bit and a character of all zeroes, the echoing stops and a steady
marking is transmitted until such time as normal
character reception resumes. Because echoing is
taking place during determination of a break condition, a single character of all zeroes (Null character)
is echoed when a break is initiated at the terminal.
The Echoing is enabled by setting Bit 4 of Control
Register 1 to a 1 bit. Echoing does not start until the
start of a receive character at a time when the transmitter is idle and CTS is zero. If the Transmitter is
forced out of the idle mode while a character is being
echoed transmission of that character is halted. The
Transmitter is idle when CR11 is a zero or the Transmitter is waiting for the THR to be loaded in the
Asynchronous mode.

READ

A read operation is initiated when CS and REgo low.
When the Read Enable (RE) line goes low, the device
gates the contents of the addressed register onto the
DAL. The device becomes unselected when the CS
and RE are both high. When the Receiver Holding
Register is read, the DR Status bit is cleared to zero.
WRITE

A Write operation is initiated when CS and WE go
low. When the Write Enable (WE) line goes low, the
device gates the data from the DAL into the
addressed register. When the CS and WE go high the
device becomes unselected. If the Transmitter Holding Register is written into, the THRE Status bit is
cleared to zero.
The 10 address is used to load both the SYN and OLE
Registers. After writing into SYN the device is conditioned to write into OLE if followed by another Write
to that address. Any intervening Read or Write to
other addresses reset this condition so that SYN will
be addressed with 10.

AD and A1 address device registers for ReadlWrite
operations are shown:

LOOP FEATURE

The device has on-line diagnostic capability. When
the Loop Control bit is a zero the data and data set
controls are appropriately looped as follows:

Transmit Data is connected to Receive Data,
with the TO output pin held in a MARK condition
and the RD input pin disregarded.
When a 1X clock is selected the TO clock
becomes the Receive clock.
o

•

The Data Terminal Ready Control bit is connected to the Data Set Ready input with the DTR
output pin held in an OFF condition and the DSR
input pin disregarded.
The Request To Send Control bit is connected to
the Clear To Send and Carrier inputs, with the
CTS output pin held in an OFF condition and the
CTS and CARD input pins disregarded.

Read

Control Register 1

Write

Control Register 1

Control Register 2

Status Register

8YN & OLE Register

Receiver Holding
Register

Transmitter Holding
Register

T=VILatpin
F~

VIH at pin

MISCELLANEOUS Pin is held in an OFF
condition.
DEVICE PROGRAMMING

INPUT/OUTPUT OPERATIONS

Programming of the WD1931 is done via two Control
Registers, one Status Register, a SYN/DLE Register,
and the Transmit and Receive Holding Registers.
The two Control Registers are referred to as CR1 and
CR2. The bits within CR1 are referred to as CR10
through CR17, and the bits within CR2 are referred
to as CR20 through CR27. For any register bit 0 is the
LSB.

All data, control, and status information is transferred to DAL pins. Control and address lines provide
for controlling the addressing, input and output
operations. In addition other lines provide interrupt
capability for alerting a controller that input/output
is required. Input/output terminology is referenced
to the controller; therefore, a Read or Input takes

Two general modes of operation exist for the
WD193l, Asynchronous and Synchronous. Both
modes of operation are discussed separately. BISYNC is a special case of Synchronous mode and is
not treated separately.

Figures 4 through 6 show CR1, CR2, and the Status
Register bit definitions. The meaning of each bit in
each register is described twice: once for Asynchronous mode and again for Synchronous mode. The
figures combine and summarize both modes.

ASYNCHRONOUS MODE
Control Register 1

.!IO

Control Register 2

Selects Transmit and Receive clock as

o ~ Transmit and Receive clock inPut
1~Ra\el (32X)
2-;- Rate 2 (32X)
3 - Rate.3(32X}
4- Rate 4 (32X)
5.--: Rate 4 +- 2'(32X) (64X)
6'- Rate 4.+ 4 (32X) (128X)
7 '-'-Rate 4 -+- 8 (32X) (256X)

SYNCHRONOUS MODE

Control Register 1

Control Register 1 (Sync Mode continued)
Bit

Name

Function

PARITY ENABLE

When set to a 1 bit, itenables check of parity on received characters
only.

DLE STRIP/MISCELLANEOUS

When set to a 1. bit andthereceiver is enabled, received charaoters
which match the contents of the DLE Register are stripped out. Also
parity checking is .disabled. When the receiver is not enabled this
bit controls the MISCELLANEOUS output onPin 5. to be used for
New Sync on a 201 Data Set. When operating with a 32X clock for
1 bit with the receiver not enabled causes the receiver bit timing to
synchronize onmark"space transitions.

TX PARITY ENABLE/FORCE DLE When set to a 1 bit with Bit6 of Control Register 1 a 0 bit Transmit
Parity is enabled, otherwise no parity is generated. When set toa 1
bit with Bit 6 a 1 bit, it causes the contents of the OLE Register to be
transmitted prior to the next character loaded in the Transmitter
Holding Register. (See description of Transparency below.)
When a 1 bit ofthe transmitter is conditioned fortransparenl trans,mission which implies thatidl.e filiWil1 be DLE-SYN and a DLE can
be forced ahead of any character in Ihe THR by use of Bit 5 .. (See
description o/Transparency.)
When.lhis bit is selloa Obit.the device is configured to provide~n
inlernal dalaandcontrol loop (see Loop feature) and the Ring
interrupt is disabled, When this bit is seUo a1 bit the device is in
normal.fulldlJplex conflgurationand the Ring interrupt is enabled.

Control Register 2

Bit

2-0

Name

Function
Selects Transmit and Receive clock as follows:
0---: Transmit and Receive clock input (1X)
1.,..-. Rate 1 (32X)
2--Rate2 (32X)
3,..- Rate 3 (32X)
4 -Rate 4 (32X)
5 ---: Rate 4 -7- 2 (32Xi (64X)
6 '-.Rate4 -7- 4 (32X) (128X)
7-Rate4 -7- 8 (32X) (256X)
When set toa,l bit and the receiver Isenabled. received characters
which match the contents ofJhe SYN Register are stripped out.
Also the SYN status bit is set with the next character. No SYN
stripping occurs with aO bit.
A 1 bitselects Odd Parity and aO bit selects Even Parity. when
parity is enabled.

A 0 bit selects Asynchronous Character Mode.
A 1 bUse.lects Synchronous Character Mode.

7-6

TRANSPARENCY

abled when Bit 6 is set to a 0 bit. When forcing transmission of a OLE, Bit 5 should be set to a 1 bit prior to
loading the Transmitter Holding Register, otherwise
the character in the Transmitter Holding Register
may be transferred to the Transmitter Register prior
to the setting of the Con'trol Bit.

The Transmit Transparency mode causes Idle Fill to
be the pair of characters OLE-SYN rather than a single SYN, and provides for preceding a character
loaded into the THR with a OLE without the possibility of an intervening OLE-SYN fill. Transparency is
enabled by Bit 6 of Control Register 1, which allows
force OLE to be controlled by Control Register 1, Bit
5, but the OLE-SYN fill is not activated until after the
first forced OLE. All aspects ofTransparency are dis-

STATUS
The Status Register contains the following status
information:

Name
TRANSMITTER HOLDING
REGISTER EMPTY (THRE)

Function
This bit is a 1. bit when the Transmitter Holding Register does not
contain a character and the transmitter is enabled. It isset to a 1 bit
when the contents of the Transmitter Holding Register is transferred
to the Transmitter Register. It is cleared to a 0 bit when the Transmitter Holding Register is loaded from the OAL, or when the transmitter is disabled.
This bit isseI toa 1 bit when the Receiver Holding Registeris loaded
from IheReceiver if the Receiver is enabled. It is cleared to a 0 bit
when li:le Re<;eiver Holding Register is read onto the DAL, or when
the receiver is disabled.
This bilis set to.a.l bit when the previous character in the.Receiver
Holding Reg ister has not been read, causing DR to not be reset, at
the timeanew c~iOIracter is re?dy to be transferred to the Receiver
Holdin!;) Register: otherwisethepit is cleared when a character is
tram;ferredtotheReceiverHolding Register. It is cleared when
the reGeiver is disabled.
This bit is set loa 1 bit when the receiver and Receive parity are
enabh3qll.pd the last received character has a parity error, and is
set tq a 9b.it,if 1i:lE\! chara.cter has correct parity. When the DLEstrip.
is enal:)led t~~Re~eive, parity check is disabled and this bilis set
toal, bitifthe previous character matched the contents Of the OLE
Register anq,wa? stripped, otherwise it is set to a 0 bit. This bit is
cleilre()~,:"ithOTR off, Tbis bit is cleared when the
Status RegistElr .isreaqontothe OAL
.

Controt Registers 1, 2 and STATUS Bit Assignments for
TRUE DATA BUS, Invert for FALSE DATA BUS.

•

7
SYNC/ASYNC

BIT

•

ASYNC

O-lOOP MODE
O-NON BREAK MODE
1- NORMAL MODE 1-8REAK MODE

•
ASYNC

lTRANS, ENABLED I

0- NON ECHO MODE
I-AUTO ECHO
MODE

0-1V, OR 2 STOP BIT
SELECTION

SYNC

1- SINGLE STOP BIT

SELECTION

O-NON TRANSMlnER
TRANSPARENT MODE

ASVNC
ITRANS. OISABlEDI

1- TRANSMIT

TRANSPARENT MODE

SYNC ICRl2 '" 11
O-OlE STRIPPING
NOT ENABLED
!-OLE STRIPPING

SYNC

ENABLED

0-, SETS

ASYNC

OUT ~ 1

I-SETS

m
a

OUT

O-SETS
OUT· ,
1- SETS 0i1i
OUT - 0

O-RECEIVER PARITY
CHECK IS DISABLED

1- RECEIVER PARITY
CHECK IS ENABLED

O-~OUT '" 1

O-NO PARITY GENERATED
I _ TRANSMIT PARITY
ENABLED

SYNC I

ASYNC

TRANSMITTER

SYNC (CR12 • 01

SYNC ICRlIl • 01

•

1
SYNC I

SYNC!
ASYNC

0- NO PARITY ENABLED
,-- PARITY CHECK
0- RECEIVER
ENABLED ON RECEIVER,
DISABLED
PARITY GENERATION
I-RECEIVER
ENABLED ON
ENABLED

O-~OUT" 1

l-mttOUT" 0

3
ASYNC

ASYNC

1-MiSt OUT" 0

SYNC ICRlI • 11
a-NO FORCE OLE
, -FORCE OLE

CONTROL REGISTER 1

BIT

•

MODE SELECT

SYNC/ASYNC

ASYNC

SVNC/ASYNC

CHARACTER LENGTH SELECT

a-ASYNCHRONOUS MODE
' - SYNCHRONOUS MODE

1-000 PARITY SELECT
O-EVEN PARITY SELECT

, - RECEIVER CLOCK DETERMINED
BY BITS 2-0
O-RECEIVER CLK = RATE I

CLOCK SELECT

00
01
10
11

"
=
=
=

8
7
6
5

BITS
BITS
BITS
BITS

SYNC
0- NO SYN STRIP
l-SYN STRIP

•

SYNC/ASYNC

000-lX CLOCK
001-RATE 1 CLOCK
OlO-RATE 2 CLOCK
0" -RATE 3 CLOCK
100- RATE" CLOCK
101-RATE 4 CLOCK - 2
"O-RATE" CLOCK - "
111-RATE 4 CLOCK - 8

CONTROL REGISTER 2

7
DATA SET CHANGE

OATil, SET READY

BIT

•

CARRIER DETECTOR

FRAMING ERROR

OLE OETECT

SYN DETECT

PARITY ERROR

DATA RECEIVER

TRANSMITTER HOLDING
REGISTER EMPTY

2
OVERRUN ERROR

STATUS REGISTER

WrltB

Reg

RBad

Control Register 1

Control RBglster 1

Control Register 2

Status Register

SYN & OLE Register

RBceiver Holding
Register

Transmitter Holding
Register

9-';

INTERRUPTS

Ring On

The following interrupts can be generated.

The Ring On interrupt occurs when the Ring input
goes low and DTR is off.

Carrier On

When an interrupt condition exists the INTR output is
made high. Reading the Status Register or MR will allow INTR to go high again.

The Carrier On interrupt occurs when the Carrier
Detector input goes low and DTR is on.
Carrier all

DATA BUS CONTROLS

The Carrier Off interrupt occurs when the Carrier
Detector input goes high and DTR is on.

The following Data Bus controls can be generated.

DSR On

Data Request Out

The DSR On interrupt occurs when the Data Set
Ready input goes low and DTR is on.

This control signal occurs when the THR is empty
while the transmitter is enabled.

DSR all

Data Request In

The DSR Off interrupt occurs when the Data Set
Ready input goes high and DTR is on.

This control signal occurs when the RHR is full while
the receiver is enabled.

VOL

VIH

AO.Ai.Cs
VIL

£-t

TOACC

TOOH

TCS

VIH

VIL

I-- TSET

TRE

THLO-

READ TIMING

VIL
TOS-

AD.Al.es

TOH

VIH

)

VIL
Tes
VIH

vlL

I--- TSET

TWE

WRITE TIMING

THLO-

MAXIMUM RATINGS
VDD with Respect to VSS (Ground)
+ 15 to - 0.3V
Max. Voltage to any Input with Respect to VSS + 20 to - 0.3V
Operating Temperature
ooe to 70 0 e
Power Dissipation
600 mW

Storage Temp Ceramic -65°C to +150'C
Plastic -55'C to ,125'C

OPERATING CHARACTERISTICS
TA

ooe to 70 o e, VDD

SYMBOL

= + 12.0V

± .6V, Vee = + 5.0V ± .25V, VSS

CHARACTERISTIC

MIN

= OV

TYP

MAX

UNITS

CONDITIONS

= VDD

III

Input Leakage

VIN

ILO

Output Leakage

VOUT = Vee

leeAVE

VecSupply eurrent

IODAVE

VOD Supply Current

VIH

Input High Voltage

VIL

Input Low Voltage (All Inputs)

2.4

VOH

Output High Voltage

VOL

Output Low Voltage

.8
2.S
.45

10= 1.6 mA

-100 uA

AC CHARACTERISTICS
TA

ooe to 70°C, VDD

SYMBOL

= + 12.0V

±0.6V, VSS

CHARACTERISTIC

THLD

AO, Al & CS Hold Time

Tes

AO, A1 & CS Width

+5.0 ± .25V

OV, VCC

MIN

TYP

MAX

UNITS

495

240

1000

TLOW

AO, Al & CS Low Time

250

TMR

MR Pulse Width

450

TSET

AO, Al & es Set·Up Time

TeYCLE

Cycle Time

CONDITIONS

TRE

RE Width

TOACC

Data Access from

TOOH

Data Hold from

RE
RE

ns
300

150

WRITE
TWE

WE Width

250

TOS

Data Set·Up Time

250

TDH

Data Hold Time

100

= 25 pI
= 25 pf

BUY/SELL
TRANSACTIONENTRY TERMINAL
(CRT)

DATA COMMUNICATIONS SYSTEMS FOR STOCK BROKERAGE FIRM

I
I

I
I
I

I
SOLC
PROTOCOL
LINK

_-"L-__-'

I
I
I
I
I
I

SYNCHRONOUS
BISYNC
~A:::;"'~--'
PROTOCOL
LINK

I
L

-1
TO REMOTE
TERMINAL

TO REMOTE
TERMINAL

DETAIL OF DATA COMMUNICATION CONTROLLER

DIGITAL COMMUNICATIONS SYSTEM
The diagrams above illustrate a typical digital system employing several processing levels and digital
protocols. It is flexible enough to satisfy several
applications. For example, the host processor and
remote terminals could be located respectively in
airline reservation offices and ticket counters, travel
centers and travel agencies, central bank offices and
branch banks, or department stores and individual

cash registers. The exploded diagram of the OataCommunications Controller exemplifies the use of
one common circuit board design with one 40-pin
socket. When the Port requires a character-oriented
protocol (synchronous, asynchronous, or
synchronous-bisync), the W01931 is plugged into
the socket. For SOLC, HOLC or AOCCP, theW01933
is used. I n addition to storing the design cycle, system flexibility and cost savings are achieved.

WD1931B PLASTIC PACKAGE

WD1931A CERAMIC PACKAGE

Information furnished by Western Digital Corporation IS believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any mfringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation Western DI91tai Corporation reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL

CORPORATION

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

WESTERN
DIGITAL
p

WD1933
Synchronous Data Link Controller
FEATURES

• STRAIGHT FORWARD CPU INTERRUPTS

.. HDLC, SDLC, ADCCP AND CCITT X.25 COMPATIBLE

.. PROGRAMMABLE MODEM CONTROL INTERRUPTS

..J

.. LOOP DATA LINK CAPABILITY

• DOUBLE BUFFERING OF DATA

o FULL OR HALF DUPLEX OPERATION

o DMA COMPATABILITY

.. DC TO 1.5 MBITS/SEC DATA RATE

.. END OF BLOCK OPTION

• DC TO 1.0 MBITS/SEC DATA RATE (SDLC LOOP MODE)

.. VARIABLE CHARACTER LENGTH (5, 6, 7 OR 8 BITS)

.. PROGRAMMABLE/AUTOMATIC FCS (CRC) GENERATION AND CHECKING

.. RESIDUAL CHARACTER CAPABILITY

.. PROGRAMMABLE NRZI ENCODE/DECODE

o GLOBAL ADDRESS RECOGNITION

.. FULL SET OF MODEM CONTROL SIGNALS

.. EXTENDABLE ADDRESS FIELD

.. DIGITAL PHASE LOCKED LOOP

o EXTENDABLE CONTROL FIELD

.. ADDRESS COMPARE

.. FULLY COMPATIBLE WITH MOST CPU'S

o AUTOMATIC ZERO INSERTION AND DELETION

.. MINIMUM CPU OVERHEAD

o MAINTENANCE MODE FOR SELF-TESTING

.. ASYNCHRONOUS/SYNCHRONOUS
MULTI-PROTOCOL BOARD CAPABILITY (PIN COMPATIBLE WITH WD
1931)

o 40-PIN PACKAGE

APPLICATIONS

o FULLY TTL COMPATIBLE
.. SINGLE +5V SUPPLY

.. COMPUTER COMMUNICATIONS

.. ERROR DETECTION: CRC, UNDERRUN, OVERRUN,
ABORTED OR INVALID FRAME ERRORS.

co TERMINAL COMMUNICATIONS
.. COMPUTER TO MODEM INTERFACING

lIT
D2
OJ

ATS

lX/32X

D6
D7

Mi'i
-D'fR
DRQO
DROI

vss (GND)

Figure 1 WD1933 PIN CONNECTIONS

Figure 2 WD1933 BLOCK DIAGRAM

Loop configuration. An End of Block option is supplied to
minimize CPU time. A full set of modem control signals are
supplied to minimize external hardware.

• LINE CONTROLLERS
• FRONT END COMMUNICATIONS
• NETWORK PROCESSORS
• TELECOMMUNICATION SWITCHING NETWORKS
o MESSAGE SWITCHING

A BRIEF DESCRIPTION OF HDLC, SDLC AND
ADCCP PROTOCOLS

• PACKET SWITCHING
o MULTIPLEXING SYSTEMS
• DATA CONCENTRATOR SYSTEMS
o LOOP DATA LINK SYSTEMS
• DMA APPLICATIONS
• COMMUNICATION TEST EQUIPMENT
• LOCAL NETWORKS
o MULTIDROP LINE SYSTEMS
GENERAL DESCRIPTION
The WD1933 is a MOS/LSI microcomputer peripheral device which performs the functioning of interfacing a parallel
digilal system to a synchronous serial data communication
channel employing ISO's HDLC, IBM's SDLC or ANSI's
ADCCP line protocol, These protocols are referred to as BitOriented Protocols (BOP).
The chip is fabricated in N-channel depletion load MOS
technology and is TIL compatible on all inputs and outputs.
This controller requires a minimum of CPU software by supporting a comprehensive frame-level instruction set and by
hardware implementation of the low level tasks associated
with frame assembly/disassembly and data integrity. It can
be programmed to encode/decode in NRZI code. The internal clock is then derived from the NRZI data using a digital
phase locked loop.
The receiver and transmitter logic operate as two total independent sections with a minimum of common logic. The
frames are automatically checked for errors during reception
by verifying the Frame Check Sequence (FCS). In transmit
mode, the FCS is automatically generated by this controller
and sent before the final Flag. It also continously checks for
other errors. In a case of an error, the CPU is interrupted.
The controller recognizes and can generate Flag, Abort,
Idle and GA characters. WD1933 can be used in a SDLC

The WD1933 is compatible with HDLC, SDLC and ADCCP
standard communication Link Protocols. These are bit-oriented, code independent, and ideal for full duplex communication. A single communication element is called a FRAME,
which can be used for both link control and data transfer
purposes.
The elements of a frame are the beginning eight bit FLAG
(F) consisting of one logical" 0 ," six 1's and a 0, an eight bit
ADDRESS-FIELD(A), an eight bit CONTROL-FIELD (C), a
variable (N bits) INFORMATION-FIELD, a sixteen bit FRAMECHECK-SEQUENCE (FCS), and an eight bit end FLAG (F),
having the same bit-pattern as the beginning flag.
In HDLC, the address (A) and control (C) characters are
extendable (more than one character). An important characteristic of a frame is that its contents are made code transparent by use of a zero bit insertion and deletion technique.
Thus, the user can adapt any format or code suitable for his
system. The frame is bit-oriented, meaning that, bits not
characters in each field have specific meanings. The Frame
Check Sequence (FCS) is an error detection scheme similar
to the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The frame format is shown
in Figure 4.

I '''"" I
Figure 4 WD1933 HDLC FRAME FORMAT
Where:
FLAG

= 01111110

Address field-One or more 8-bit characters defining the
particular station
Control field-One or two 8-bit characters

-ofR
DSR
RTS

-cs
RE
WE

MR
COMPUTER

TD
SOLe
WD1933

Information field-Any number of bits (may be zero bits)
Frame Check Sequence-16-bit error checking field

ii2

Ffc

EO-B

T
--,

Figure 3 WD1933 TYPICAL SYSTEM INTERFACE

The following features are also part of these protocols.
ZERO INSERTION/ZERO DELETION-Zero insertion/deletion is performed within the 2 Flags of a frame. If there are
more than five1's in a row, a 0 is automatically inserted after
the fifth 1 and it is deleted upon reception by the receiver.
FRAME CHECK SEQUENCE (FCS)-A 16 bit cyclic redundancy check (CRC) calculation is performed during transmission of the data in between the 2 flags of the frame. The
CRC is then transmitted after the I-field and before the final
FLAG. Upon reception the receiver also performs a CRC
calculation on the incoming data. If there were no transmission error, the Receiver CRC equals FO B8 (hex).

100

DESCRIPTION OF PIN FUNCTIONS
The WD1933 is packaged in a 40 pin DIP. The following is a functional description of each pin. A bar over a signal (SIGNAL),
means active Low.

Table 1 DESCRIPTION OF WD1933 PIN FUNCTIONS
PIN
NUMBER

PIN NAME

FUNCTION

SYMBOL
NC

No connection allowed to this pin. Used internally only.

End of Block

EOB

This input, when low, function as an FCS command. Is independent
of CS.

Read Enable

This input, when low (and CS is active), gates the content of addressed register onto the Data bus.

Chip Select

This input, when low, selects the WDl 933 for a read or write operation
to!from the Data bus.

Misc Output

MISC OUT

This output is an extra programmable output signal for the convenience of the user. Is controlled by the CR10 bit.

Interrupt
Request

INTRO

The output is high whenever any of the interrupt register bits, IR7-IR3
are set.

Write Enable

This input when low (and CS is active), gates the content of the Data
bus into the addressed register.

8-15

Data Bus

DO-07

Bidirectional three-state Data Bus. Bit 7 is MSB.

Master Reset

This input, when low, initializes all the registers, and forces the WD1933
into an idle state. The WD1933 will remain idle until a command is
issued by the CPU.

Data Terminal
Ready

DTR

Modern Control Signal. This output when low, indicates to the Data
Communication Equipment (DCE) that the WD1933 is ready to transmit or receive data.

Data Request
Output

DROO

This output, when high, indicates that the Transmitter Holding Register
(THR) is empty and ready to receive a data character from the Data
bus for a transmit operation.

Data Request
Input

DROI

This output, when high, indicates that Receiver Holding Register
(RHR) contains a newly received data character, available to be read
onto the Data bus.

Vss
A2,AQ,M

Vss

21,22,23

Address Lines

Misc
Input

MISC IN

This input is an extra input signal for the convenience of the user. The
state is shown by the SR4 bit.

Transmitted Data

This output transmits the serial data to the Data Communications
Equipment/Channel.

Receive Clock

This input is used to synchronize the received data.

Received Data

This input receives the serial data from the Data Communication
Equipment/Channel.

NRZI

This input, when low, sets the WD1933 in NRZI mode.

Clear to Send

CTS

Modem Control Signal. This input when low, indicates that the DCE
is ready to accept data from the WD1933.

DPLL Select

lX132X

This input controls the internal clock. When high (1 X clock), the external clock has the same frequency as the internal clock. When low
(32X clock), the external clock is 32 times laster than the internal clock
and the DPLL Logic is enabled.

Ground
These inputs are used to address the CPU interface registers for read!
write operations.

Transmit Clock

This input is used to synchronize the transmitted data.

Request to Send

RTS

Modem Control Signal. This output, when low, indicates to the DCE
that the WD1933 is ready to transmit data.

Data Set Ready

DSR

Modem Control Signal. This input, when low, indicates that the DCE
is ready to receive or transmit data.

101

PIN
NUMBER

PIN NAME

FUNCTION

SYMBOL

Ring Indicator

Modem Control Signal. This input, when low, indicates a ringing signal
being received on the communication channel.

35,36

Ring Indicator
Interrupt Control

R11, RIO

These inputs are used to program Ring Indicator interrupts.

37,38

Carrier Detect
Interrupt Control

CD1, CDO

These inputs are used to program Carrier Detect Interrupts.

Carrier Detect

Modem Control Signal. This input, when low, indicates there is a carrier signal received by the local DCE from a distant DCE.

Vee

+5VDC

Table 1 DESCRIPTION OF WD1933 PIN FUNCTIONS

TERMINOLOGY
TERM

DEFINITION/DESCRIPTION

BOP

Bit-oriented protocols: SDLC, HDLC, and ADCCP

ABORT

11111111 (seven or more contiguous 1's)

Go-ahead pattern. 01111111 (O(LSB) followed by seven 1's)

LSB

First transmitted bit and first received bit. (Least significant bit)

MSB

Last transmitted bit and last received bit. (Most significant bit)

IDLE

1111111111111111 (15 or more contiguous 1's)

FLAG

01111110. Starts and ends a Frame.

A-FIELD

Address-field in the Frame. Consists of one or more 8-bit characters. Defines the address
of a particular station.

C-FIELD

Control field in the Frame. Consists of one or two 8-bit characters.

I-FIELD

Information field in the Frame. Consists of any number of bits.

FCS

Frame Check Sequence. A 16-bit error checking field sequence.

FRAME

A communication element, consisting of a minimum of 32 bits, and is always delimited by
FLAGS.

GLOBAL ADDRESS

An A-field character of eight 1's. When this is compared and matched in the Address comparator, the DROI will be set, indicating a valid address

RESIDUAL
CHARACTER

The last I-field character, consisting of a lesser amount of bits than the other I-field characters in the Frame.

DATA SET

Data Communication Equipment (DCE). May be a modem.

BIT TIME

Length in time of a serial data bit.
Table 2 WD1933 TERMINOLOGY

102

HARDWARE ORGANIZATION

Various Internal Circuits

The WDI933 block diagram is illuslrated in Figure 2 and
described below.

ADDRESS COMPARATOR This B-bit comparator is used
to compare the contents of the Address Register with the first
address character of the incoming frame. This feature is enabled by a bit in the Command Register. If enabled and there
is a match, the received frame is valid and DROls are generated for every character received (including the A-field). If
enabled and there is not a match or there is no Global Address, the received frame is discarded. If not enabled, all received frames are valid and DROls are generated.
ZERO INSERTION The transmitted data stream is
continuously monitored by this logic. A zero is automatically
inserted following five contiguous I bits anywhere between
the beginning FLAG and the ending FLAG of a frame. The
insertion of the zero bit thus applies to the contents of the
Address, Control, Information Data, and the FCS field.
ZERO DELETION The received data stream is continuously monitored by this logic. Upon receiving five contiguous
1 bits, the sixth bit is inspected. If the sixth bit is a 0, it is
automatically deleted from the data stream. If the sixth bit is
a 1, the seventh bit inspected; if it is a 0, a FLAG is recognized; if it is a I an ABORT or GO AHEAD is recognized.
DATA BUS (D7-DO) This is an inverted B-bit bidirectional data bus.
SDLC LOOP-MODE CONTROL This logic supervises
the WDI933 running in SDLC Loop mode. It monitors the
received data for a GO-AHEAD pattern in the case when
SDLC LOOP MODE bit (CR22) and ACT TRAN bit (CRI6)
are set. When GO-AHEAD pattern is received, this logic suspends the repeater function and initiates the transmitter function. For more details, see functional description of SDLC
Loop Mode.
NRZI ENCODER/DECODER When this mode is selected, the NRZI Encoder encodes the "normal" transmitted
data to NRZI formatted data and the NRZI Decoder decodes
the received NRZI data to "normal" data.

CPU Interface Registers
All of these registers are addressable and to be read from
and/or written into by the CPU via the Data bus. These are
B-bit registers and have to be enabled via Chip Select (CS)
before any data transfer can be done.
CONTROL REGISTER 1,2,3 (CRI, 2, 3) Operations are
initiated by writing the appropriate commands into these registers. CRI should be programmed last.
RECEIVER HOLDING REGISTER (RHR) When Data
Request Input is set (DROI=I), contains received assembled character.
ADDRESS REGISTER (AR) Contains the address of this
WD1933, which is to be compared to the received address
character (A-field).
INTERRUPT REGISTER (IR) Contains the cause of the
current interrupt request.
TRANSMITIER HOLDING REGISTER (THR) Is to be
loaded with the next in line character to be transmitted, when
Data Request Output is set (DROO=I).
STATUS REGISTER (SR) Contains the overall status of
the WDI933, plus some information of the last received
frame.
Non-Addressable, Internal Registers
These registers are transparent to the user, but is mentioned in these data sheets to help the understanding of the
WD1933.
TRANSMITIER REGISTER (TR) This B-bit register
functions as a buffer between the THR and the TO output.
Is loaded from the THR (if Data Command) with the next
character to be transmitted. An ABORT or FLAG character
may also be loaded into this register under program control.
This character is automatically shifted out to the Transmit
Data output. When the last bit of the current transmitted character has left the TR register, a new character will be loaded
into this register, setting DROO (Data command) or INTRO
(Abort, Flag or FSC command). If at the time when only one
bit remains left in the TR register, the THR is not loaded or
a new command is not programmed (Data command), an
underrun error will occur.
RECEIVER REGISTER (RR) The received data is, via
the Zero-Deletion logic shifted into this B-bit register. The
data is here assembled to a 5, 6, 7 or B-bit character length
and then, under the right conditions, parallel transferred to
the RHR register.
FCS
RECEIVE
REGISTER
AND
FCS
XMIT
REGISTER The WDI933 contains a 16-bit CRC check register (FCS REC. REG.) and a 16-bit CRC generation register
(FCS XMIT REG.). The general polynomial is:
G(X) = X16 + X" + X' + I
The transmitter and receiver initialize the remainder value to
all ones before CRC accumulation starts. The polynomial is
multiplied by X16 and is divided by G(X). Inserted a's are not
included in the accumulation. Under program control, the
complement called the frame check sequence (FCS) is sent
with high order bit first.

103

A binary 1 for "normal data" is TO = high.
A binary 1 for NRZI data is TD

= no change.

A binary a for "norrnal data" is TO = low.
A binary a for NRZI data is TO = change of state.
COMPUTER INTERFACE CONTROL This logic interfaces the CPU, to the WD1933. It supervises the read and
write functions to the addressable registers, generates data
requests and interrupts, decodes and initiates commands,
monitors the status of WD1933 etc.
MODEM INTERFACE CONTROL This logic interfaces
and supervises the modem control signals to/from the
WD1933. It provides both dedicated (EIA Standard) and user
defined control functions.
CLOCK CONTROL This logic interfaces the transmit and
receive clocks to the WD1933. It converts the external clocks
to the necessary internal clocks.
FUNCTIONAL DESCRIPTION
SDLC Loop Mode
The diagram below shows an SDLC LOOP Data Link System. WD1933 can be used in any of these stations.

cycle is completed. The Primary Station may then transmit
or initiate another cycle as described above. As a repeater,
the transmitted data is delayed by 4 bits (NRZI~5 bits) relative to the received data.

Primary
~wn-!oop

1X/32X Clock Option

Secondary 2

Figure 5 WD1933 SDLC LOOP DATA LINK
Each secondary station is normally a repeater in Receive
mode. The primary station is the loop controller. Signals sent
out on the loop by the primary station are relayed from station
to station, then back to the Primary. Any secondary station
finding its address in the A-field captures the frame for action
at that station. All received frames are relayed to the next
station on the loop.
If anyone of the secondary stations wants to transmit a
message, it sets its ACT TRAN bit and waits for a GOAHEAD (GA) pattern. The WD1933 recognizes seven or
more contiguous logical 1's as a GO-AHEAD pattern. Until
GA pattern is received, this secondary station continues operating as a repeater. When primary station is done transmitting, it may send a continuous stream of GA patterns
down the Loop. This rnay be accomplished by going Idle.
When the first in turn secondary station, with the ACT TRAN
bit set, receives the GA pattern, it suspends the repeater
function and immediately goes into transmit mode. It transmits its message and when completed, it resets the ACT
TRAN bit. This converts the secondary station back to
repeater mode. The GA-patterns still transmitted by the Primary Station, gets relayed down the Loop to the next secondary station. The next down-loop secondary station has
the opportunity to transmit in the same manner. When the
primary station receives the GA-pattern, all the secondary
stations have been able to transmit their messages, and the

When 1X clock is selected, the data rate equals the external clock (receiver and transmitter).
When 32X clock is selected, the external clock rate is 32
times faster than the data rate.
Digital Phase Locked Loop (DPLL)
This feature is particularly useful in NRZI mode. The purpose of the DPLL is to synchronize the internal 1X clock to
the received data, thus insuring that this data is sampled in
the middle of the incoming serial bit. DPLL is automatically
in operation when 32X clock is selected.
The DPLL Logic initiates at the first received data transition
in a frame. Corrections, if needed, are then made for each
received data transition. A 32-counter is used for this operation. At the beginning of each frame and at the first received
data transition, this 32 counter is reset. From this time on,
the counter increments with one count for each external clock
pulse. At count 16 the internal 1X clock is forced to change
state to high (this transition ~ sampling time). At count 32,
the counter resets itself. This forces the internal 1X clock
again to change state back to low.
At each received data transition, if the internal clock and
the received data is out of synchronization, a correction is
automatically made by ± 1 external clock period. See DPLL
Timing Diagram in Figure 6.
End Of Block (EOB)
This is an FCS command. The main purpose of EOB is to
allow the user to initiate FCS and FLAG without the need of

INTERNAL CLOCK

SAMPLE

DATA

OATA

NOTE 1. FIRST DATA TRANSrrlON (FIRST FLAG) SETS THE DPLL COUNTER TO 01.
NOTE 2. DATA TRANSITION IN BETWEEN HERE. OR NO DATA TRANSITION AT ALL. CAUSES NO CORRECTION OF THE
DPLL COUNTER.
NOTE 3. DATA TRANSITION IN BETWEEN HERE. WILL INCREMENT ONE COUNT TO THE DPLL COUNTER (ADD 01 TO
WHAT IS SHOWN).
NOTE 4. DATA TRANSITION IN BETWEEN HERE, WILL DECREMENT ONE COUNT TO THE DPLL COUNTER (SUBTRACT 01
TO WHAT IS SHOWN).

Figure 6 WD1933 DPLL TIMING DIAGRAM

104

using extra computer time. This is particularly practical in
DMA applications. At the end of a frame, when the last information data character has already been loaded into the
THR and once again DRaO is set, either a regular FCS command is written into CR 1 Register, or EOB is to be activated.
~e end of FCS, when INTRa is set (XMIT OPCOM), the
EOB if activated is to be reset again.

PROGRAMMING
Contrail ing Operation

The serial data is synchronized by the externally supplied
Transmit Clock (TC) and Receive Clock (RC). When 1X clock
is selected, the falling edge of TC generates new transmitted
data and the rising edge of RC is used to sample the received
data. When 32X clock is selected, a 32-counter (in the DPLL
Logic) is used to synchronize the internal clock. At time 0,
when the counter is reset to 0, the new transrnitted data is
generated. At time 16 (counter ~ 16) the received data is
sampled, insuring that sampling is done in the middle of the
received serial bit. At count 32, the counter is reset to
again.

Prior to initiating data transmission or reception, CONTROL REGISTER 1-3 (CRI-3) must be loaded with control
information from the CPU. The contents of these registers
will configure the WD1933 for the user's specific data communication environment. These registers should be loaded
during power-on initialization and after a reset operation.
They can be changed at any time that the respective transmitter or receiver is deactivated. The CR1-3 dictate what the
transmitter will send: the type of character (DATA, ABORT,
FLAG or FCS), the number of bits per character, and the
number of bits in the residual character. Similarly, they tell
the receiver the types of frames to look for: the number of
bits per I-field character, whether to perform an address compare, and whether to watch for an extended address. The
Cont~egister also control Data Terminal Ready (DTR),
Misc Out and the activation of both the transmitter and the
receiver. For more detailed information, see Register Formats.

Self Test (Diagnostic) Mode

Monitoring Operation

This feature is a programmable Loop back of data, enabling the user to make a complete test of the WD1933 with
a minimum of external circuitry. In this mode, transmitted
data to the TD pin, is internally routed to the received data
input circuitry, thus allowing a CPU to send a message to
itself to verify proper operation of the WD1933. The modem
control signals DTR and RTS are deactivated (off) to insure
no interference to/from the Data Communication Equipment
(DCE). DSR and CTS are internally activated for proper input
conditions. TC and RC should be supplied by the same
source if 1X clock is selected.

Monitoring is done by use of the Interrupt Register (IR) and
Status Register (SR). The IR register indicates when a frame
is completed (transmitted or received), if there was an error
and if there is a Data Set Change. ft also monitors the states
of INTRa, DRaa and DRQI.
The SR register indicates if an error is recognized by IR
and what type of error. It also monitors the modem control
signals; Ring Indicator (RI), Carrier Detect (CD), Data Set
Ready (DSR) and Misc In.
Furthermore, the SR register monitors if the Receiver is
idle, and also if in receive mode if the user has programmed
the Receiver Character Length to be 8 bits per character, this
register indicates the number of residual bits received. For
more detailed information, see Register Formats.

Serial Data Synchronization

Auto Flag
If this is selected and Data Command is executed, continuous Flags will be sent between frames. This eliminates the
need to execute the Flag Command. In DMA applications in
particular, this is very practical.

Extended Addressing
This type of addressing means, that there is more than one
address character in the A-field. In receive mode, the first
address character is compared in the Address Comparator
of the WD1933. The other address character/s is to be compared by the CPU. The last address character is recognized
by the fact that the LSB (bit 2°) is a 1.

105

Read/Write Control Of CPU Interface Registers
These registers are directly accessible from the CPU bus
(D7-DO) by a read and/or write operation by the CPU.
_The CPU must set up the WD1933 register address (A2AO), Chip Select (CS), Write Enable (WE) or Read Enable
(RE) before each data bus transfer operation.
During a write operation, the falling edge of WE will initiate
a WD1933 write cycle. The addressed register will then be
loaded with the content of the Data Bus (D7-DO). During a
read operation, the falling edge of RE will initiate a WD1933
read cycle. The addressed register will then place its content

onto the Data Bus (07-00). The read/write operation is completed, when CS or RE/WE is brought high.
For more detailed information, timing, etc., see ReadIWrite
Timing diagram.
For read and write operation, the CRl-3 registers need no
external clock. To reset CRl-3, TC clock is required. The AR
and THR registers need no external clock, and can only be
written into. The RHR, IR and SR registers need Transmit

Clock (TC) or Receive Clock (RC) to set various bits, and are
read-only.
All these registers will get initialized by a Master Reset. A
read operation of RHR resets the ORal. A write operation
to THR, resets the DROO. A read operation of IR, resets IR
bits 0 and 3-7. A read operation of SR, resets SR bits 0-2.
For addressing and external clocks needed, see figure
below.

Read

Write

L
L
L
L
L
L
H

H
H
H
H
L
L
X

H
H
L
L
H
H
X

H
L
H
L
H
L
X

CRl
CR2
CR3
RHR
IR
SR
X

CRl
CR2
CR3
AR
THR

External Clock
None'
None'
None'
RHR=RC. AR=None
IR=TC". THR=None
SRO-3=RC. SR4-7=None.

L = VIL at pins
H = VIH at pins
X = Don't care

'Master Reset requires TC.

Below shows a short form register format.

CRI

20
CR2

CR'

RHR

THR

Figure 7 WD1933 BIT ASSIGNMENTS

106

A more detailed description is shown here of each bit location. It should be known, that because the Data Bus Lines
(07-00) has inverted logic, a logic 1 (set) means low state.
Also, a modem control signal which is inverted (example
DTR), is in on-state (set) when low.
Control Register 1 (CR1)
When initiating a transmiVreceive operation, this should be
the last register programmed.
Miscellaneous Output (CR10) This bit controls the Miscellaneous Output signal to the data set. When CR10 is a
logical 0, Misc Out is off, when it is a logical 1, Misc Out
is on.
OTR Command (CRll) This bit controls the data Terminal Ready (DTR) signal to the data set. When CRll is a
logical 0, DTR is off. When CRll is a logical 1, DTR is on.
When the Self-Test mode is selected, DTR signal is forced
to an off state.
Transmitter Character Length (CR13, 12) These bits
control the transmitted I-field data character length. The
data character may be 5, 6, 7 or 8 bits long.

CR13 (TCL1)

CR12 (TCLO)

0
0

0
1
0

Bits Per
Character
8
7
6
5

Transmitter Commands (CR15, 14) These bits control
the transmission of DATA (A-field, C-field and I-field), ABORT,
FLAG, and FCS (FCS pius FLAG). When these commands
are programmed, the previous command currently still in
progress, will complete the transmission of its character.
When this is done, a new character generated by this new
command, will be transmitted.
If DATA is programmed, the new character to be transmitted will be the character loaded (or still to be loaded) in
the THR register. If ABORT is programmed, the new character will be eight logical I's. If FLAG is programmed, the
new character will be 01111110. If FCS is programmed, three
new characters will be transmitted; first the 16-bit content of
the FCS XMIT REGISTER, then a FLAG. One serial data bit
time ahead of the first bit (LSB) of this new character ( ~
FLAG character when FCS command) being transmitted, the
CPU is signalled that the WD1933 is again ready to receive
a new command. This signal is an INTRO (XMIT OPCOM),
if the now current command is ABORT, FLAG or FCS. This
signal is a DROO, if the current command is DATA. However,
in this latter case (DATA), the user has two choices; 1.
Change the command. 2. Keep the DATA command and
load a new character into the THR register. For more information, please see the Transmission Timing diagram, Figure
8.
Programming, see figure below.

CR15 (TC1)

CR14 (TCO)

0
1
0
1

Activate Transmitter (CR 16) This bit when set, enables
the transmitter and sets RTS Signal. If in SDLC Loop Mode
(CR22 ~ set), the transmitter waits for a Go-Ahead pattern
before the transmitter is enabled.
Activate Receiver (CR 17) This bit when set activates
the receiver, which begins shifting in frames one character
at a time into RR register for inspection.
CONTROL REGISTER 2 (CR2)
Auto Flag (CR20) When set, Flags (without INTROs) will
be continuously transmitted in between frames, when otherwise the transmitter would be in idle state.
Self-Test Mode (CR21) When set, the Transmitter Data
Output is internally connected to the Receiver Data input
circuitry. The modem control output Signals are deactivated
(off state). The modem control input signals are internally
activated. This mode allows off-line diagnostic.
SDLC Loop Mode (CR22) When set, the WD1933 is
conditioned to operate in an SDLC Loop Data Link system
(see SDLC Loop Mode).
Receiver Character Length (CR24, 23) These bits indicate to the receiver how many bits per character there are
to assemble for the I-field. The I-field characters may be 5,
6, 7 or 8 bits long. The unused bits read from RHR will be
10gical0.
CR24
(RCLl)

CR23
(RCLO)

Bits Per
Character

0
0
1

0
1
0

8
7
6
5

Extended Address (CR25) When set, this bit indicates
to the receiver that there is more than one address character
in the A-field. The receiver will expect another address character if the LSB in the current address character is a logical
O. The purpose of this bit: If a non-8-bit I-field character
length is expected, the DROls will get out of synchronization
if the WD1933 does not know exactly when the I-field will
start. Not used in transmit mode.
Address Compare (CR26) When set, the first address
character will be inspected in the Address Comparator. If
there is a match with the AR register, or if the address compared is a Global Address (eight 1's) the frame is considered
valid, causing DROls to be generated. Otherwise, the receiver does not react, and will continue comparing for a new
valid address. If not set, all frames are considered valid.
Extended Control (CR27) When set, indicates that there
are two control characters per frame. If not set, there is only
one control character per frame. The purpose of this bit: If
a non-8-bit I-field character length is to be received, the
DROls will get out of synchronization if the WD1933 does
not know when the I-field will start. Not used in transmit
mode.

Command
DATA
ABORT
FLAG
FCS

107

Character/s Transmitted

Signal to CPU

Content of THR
1111 1111
0111 1110
FCS + 01111110

DROO
INTRO
INTRO
INTRO

CR32
(TRES 2)

CR31
(TRES 1)

CR30
(TRES 0)

a
a
a
a

a
a

1
1

CONTROL REGISTER (CR3)
Transmit Residual Character Length (CR32, 31,
30) These bits inform the transmitter what bit-length the
residual character will be. If no residual character is to be
sent, these bits must be set to logical O.
Unused (CR33-37)
always a logical O.

These bits are not used, and are

INTERRUPT REGISTER (IR)
This register contains the information why an interrupt
(INTRQ) was generated. An IR register read operation, will
reset bits 0, and 3-7.
Loading the THR register, will reset DRQO (bit 1). Reading
the RHR register, will reset DRQI (bit 2). A new interrupt will
occur if one is pending.
If a new interrupt is generated while the CPU is reading
the IR register, this new interrupt will set the respective bit
in the IR register one bit time later (this to avoid losing any
interrupt). The status of bits 3-7 will accumulate until the IR
register is read by CPU.
INTRQ (IRO) When set, indicates an interrupt and that
there are one or more bits set in positions 3 through 7 of this
register. This bit is a mirror image of INTRQ signal (pin 6).

CD1
LO
LO
HI
HI

COO
LO
HI
LO
HI

No residual char. sent
1 bit
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits

a
a

1
1

Residual Char. Length

a
1

DRQO (IR1) When set, indicates a Data request output.
This bit is a mirror image of DRQO signal (pin 18).
DRQI (IR2) When set, indicates a Data Request input.
This bit is a mirror image of DRQI signal (pin 19).
Data Set Change (IR3) When set. indicates a change of
state of the Data Set (Data Communication Equipment). This
is a change of state of DSR, CD orR!. The type of change
of CD andR! that this bit will react to, is programmed by use
of input signals CD11CDO andRf1IRIO and is shown below.
XMIT Operation Complete with Underrun Error
(IR4) When set, indicates that the transmitter command
has been completed and there was an Underrun error. An
Underrun error occurs when the Data Request Output
(DROO) is set, but THR register is not loaded in time.
XMIT Operation with No Error (IR5) When set, indicates that the transmitter command has been completed and
there was no error.

Received End of Message With Errors (IR6) When set,
indicates that a Received End of Message is detected, and
there was an error. Errors include CRC, Overrun, Invalid
Frame and Aborted Frame.
The SR Register bits 0-2 will indicate the exact type 9f
error.
Received End Of Message With No Error (IR7) When
set, indicates that a Received End of Message is detected,
and there was no error.

Interrupting edge of CD

Rl1

RT5

Interrupting edge of RI

Rising and falling
Falling
Rising
None

LO
LO
HI
HI

LO
HI
LO
HI

Rising and falling
Falling
Rising

108

None

STATUS REGISTER (SR)
This register contains the status of the receiver and some
modem control signals. It a'so indicates (if REOM w/Errors)
exactly what type of errors. If the Receiver Character Length
is 8 bits, this register indicates the amount of Residual bits
that was received. A read operation will reset bits 0-2.
Received ErrorlReceived Residual Character Length
(SR 2-0) If REOM wiNO ERROR (IR7) is set, and the
Receiver, Character Length (CR24, 23) is 8 bits, these bits
(SR 2-0), indicate the number of residual bits received.
tf REOM WITH ERROR (tR 6) is set, these bits indicate
the type of error that occurred, as shown in figure below.

Bit Set

Error

SRO
SR1
SR2

CRC
Overrun
Aborted or
Invalid frame

Receiver Idle (SR 3) When set, indicates that the receiver is currently IDLE.
Miscellaneous Input (SR4) This is a mirror image of
MISC IN signal. When this signal is set, SR4 bit is set.
Data Set Ready (SRS) This is mirror image of DSR signal. When this signal is set, SR5 bit is set.
Carrier Detect (SR6) This is a mirror image of CD signal.
When this signal is set, SRS bit is set.
Ring Indicator (SR7) This is a mirror image of Rl signal.
When this signal is set, SR7 bit is set.
TRANSMITTER OPERATION
Prior to this operation, the programmable inputs and the
transmit mode related register bits need to be programmed
according to the user's specific data communications environment. The last bit to be set is always the ACT TRAN
(CR1S) bit.
Before this, the INTRO has to be cleared, which can be
done by reading the IR register. For more detailed information how to program the WD1933, see Programming.
As an example of how to program the WD1933, let's assume a 24-bit information is to be transmitted. The I-field
would then consist of three B-bit characters with no residual
bits. CR3 should then be 00 (Hex).
If Auto Flag is selected, CR20 has to be set, CR21 and
CR22 should be logical O's, as this example is no Self-test
alld no SDLC Loop Mode.
Bits CR23-CR27 are for reception only (see Receiver
Operation). The last register to be programmed is CR1. If
MISC OUT is not used, this may be ignored. If a modem is
used, DTR (CR11) is to be set. CR14 and CR12 should be
logical O's (B-bit char. length). CR15 and CR14 should be
logical a's (Data Command). ACT TRAN (CR16) bit is to be
set. The ACT FlEC (CR17) is for reception only.
The DTR bit, when set, activates the OTR signal, indicating
to the modem to prepare for communication. When the modem is ready, it sends back a Data Set Ready (OSR) to the
W01933. This causes the DSC (IR3) bit to set, which in turn
activates INTRO. The IR register is now read. Simultaneously, when the ACT TRAN (CR1S) bit is set, this activates
the Request to Send (RTS) signal, instructing the modem to
enter into transmit mode. When the modem is ready to trans-

109

mit data, it responds by activating the Clear to Send (CTS)
signal.
The WD1933 is now conditioned to transmit. Now DROO
gets set, indicating to the CPU (or OMA) to load the first character (Address) into the THR. When this is done, OROO will
reset. As soon as the W01933 is ready to be loaded with the
next character to be transmitted, OROO is again set. When
the THR register is again loaded with a character, DROO will
again reset.
This same sequence continues until the last I-field character to be transmitted is loaded into the THR. Ii CRC checking is to be used, the next time when OROO is set, an FCS
command has to be programmed. This is accomplished bv
either setting CR15, 14 to both logical 1's or by activating the
EOB signal.
At the end of the FCS being transmitted, INTRO will set
indicating XMIT Operation Complete. The IR register is to be
read to find out whether the frame was sent with or without
error. Also the FCS Command which was used as described
above has to be changed. If CR15, 14 were set, these have
to be reset (to Data Command), or if EOB was activated, this
signal has to be deactivated. At this same time, the ACT
TRAN bit is allowed to be reset, causing the TO output to go
idle after the end Flag is sent. If the ACT TRAN bit is kept
set, continuous Flags will be sent following the FCS.
If a new frame is to be sent right after this first frame, only
one Flag is needed in between frames, meaning the frames
have one common Flag character. In this case, the second
frame Address character may be loaded at the same time
the FCS command is programmed during the first frame.
Also, the ACT TRAN bit should be kept set in between
frames. Every time OROO gets set, the user must load the
THR register before the last loaded character only has 1.5
bits left to be transmitted. In other words, when ORQO gets
set, the user may wait (if 8-bit characters) up to 7.5 serial
data bits before loading the THR. If THR is not loaded within
this time, an Underrun error will occur.
If Auto Flag is not selected (CR20 ~ logical 0) the sequence
will be a little different than described below. When the first
DROO is set, and after the Address character is loaded into
THR, a Flag command is also programmed (CR15. 14 ~ 10).
This will set an interrupt (INTRO), which indicates that the
IR register must be read. Now, the Data Command is reprogrammed (CR15, 14 ~OO).
For more information, see Transmission Timing diagram.
ABORT CONDITIONS
The function of prematurely terminating a data link is called
an "Abort." The transmitting station aborts by sending eight
consecutive 1·s. Unintentional Abort caused by I's in the AC- or I-field is prevented by zero insertion. Intentional Abort
may be sent by programming an Abort command. Abort will
also be sent in the case where THR is not loaded in time or
FCS command is not programmed in time (~underrun). This
means that after the ORWO is set, to avoid Abort; THR must
be loaded, EOB activated or FCS command programmed
before there is only 1.5 bits left of the last character to be
transmitted.
If this is not done, INTRO (XMIT OPCOM w/underrun) is
set and Aborts are transmitted until, either the command is
changed or the THR is loaded. If in this same case, Auto
Flag was programmed, one Abort (with INTRO) would be
generated, and thereafter continuous Flags (with no INTRQs)
will be sent.

RECEIVER OPERATION
Prior to this operation, the programmable inputs and the
receive mode related register bits have to be programmed
according to the user's specific data communication environ-

ment. Also, the INTRa has to be cleared. The last bit to be
set is always the ACT REC (CR17) bit.
For more detailed information how to program the WD1933,
see Programming. As an example, let's assume a 26-bit information is to be received, and the I-field is made up by
a-bit characters. The CR3 register is only for transmit mode,
and may be ignored here. CR20 and CR 12-16 bits are also
for transmit mode only, and therefore may also be ignored.
CR21 and CR22 are to be logical as (no Self-Test and no
SDLC Loop Mode). CR24, 23 are to be logical a's (8-bit
character I-field). If only one A-field and one C-field character
is expected, and this WD1933 has a specific address, CR25
should be a logical 0, CR26 should be a 1, and CR27 should
be a O. The address to which the A-field should compare
should be loaded into the AR register.
The status of the modem is monitored by the SR register,
and it may be useful to read it at this time. CR 1 is loaded as
the last register. CR10 (Misc In) bit is optionable to the user.
CR11 (DTR) is to be set if modem is used. CR17 (ACT REC)
is now set, starting the input of frame characters into the
Receiver Register (RR). When a Flag is detected, the next
a-bit character (address-character), when received, is compared to the character in the AR register. If these match, or
if the received character is a Global address, this frame is
valid, and the DROI gets set. If the Address Comparator
(CR26) bit is not set, all frames would be considered valid
and generate DROls. When the RHR register is read, DROI
will be reset. All characters in a valid frame which are input
into the RR register will set DROI, and every time RHR is
read by the CPU, DROI will be reset.
During reception, the receiver also performs a CRC calculation on the incoming data. When the end Flag is received,
INTRa will get set, indicating Received End of Message. If
the reception is completed with no error, IR7 (REaM wino
Error) bit will be set. When 8-bit characters are received SR
0-2 bits indicate the number of residual bits, in this case two.
If IR6 (REaM wlError) was set, SR 0-2 bits indicate the type

of errors (see Received Error Indication).
When all characters including the A-field and the FCS-field
are read, and when the RE interrupt is recognized, it is up
to the user to disassemble these mentioned characters from
the received data. If non-8-bit characters are received, the
amount of residual bits have to be calculated by the CPU
after masking out the part of the ending Flag showing up in
the last read character.
After end of frame, the receiver begins searching for a new
frame.
For more information, see Reception Timing diagram.
RECEIVER ERROR INDICATION
When a frame is received, and REaM wlError (IR6) is set,
the type of error is indicated by the SR bits 0-2.
CRC Error (SRO) If the CRC calculation performed on
the incoming data does not equal to FOB8 (HEX), this bit will
be set.
Overrun Error (SR1) After DRQI is set, if the RHR is not
read within one character minus one bit time, this bit will be
set.
Aborted or Invalid Frame Error (SR2) If the frame is
aborted, or it consists of less than 32 bits between flags, this
bit will be set.
NOTES

1. TC-command-If two or more contiguous ABORTS of
FLAGS are executed, the ACT TRAN (CR16) bit has to
be reset before DATA-command can be executed.
2. Master Reset (MR)-Needs no clock during activation of
MR. However, 2.5 clock pulses are required to reset the
WD1933 after the falling edge of MR.
3. IR-register-Immediately when IR register is read, bit a
will reset. Bits 3-7 are reset one bit time later.
4. SR-register-Bits 0-2 are reset one bit time after SR register being read.
5. SDLC Loop mode-Go-ahead pattern may be sent by
either sending IDLE or ABORT.

110

Tc"
(1)1; CLOCK)

AEAD

~------------------~--------------~~

_1_

NOTE 1. CR3

DOH, CR2

01H. CRl

02H (FOR THIS EXAMPLE ONLY)

NOTE 2. WRITE FCS COMMAND, OR ACTIVATE EOB.
NOTE 3. WRITE DATA COMMAND, OR DEACTIVATE EOB.
NOTE 4. INF. DATA MAY CONSIST OF ANY NUMBER OF BITS.

Figure 8 WD1933 TRANSMISSION TIMING DIAGRAM

ORQI

----1j-------------!

INTRQ

,~_ _ _ _ _ _ _ _ _ _.,_---___:_----_:_---____;----_:_----~IL

-----;-f,t
i

l
.~

I~~

~~~

NOTE 1. AR = 19H, CR2

-L -L -L

==:

40H. CRl

= 02H

i~~

lii~ffi

~~g

~~5

"0.

~~~

-L

~~~

g~~

~~5

(FOR THIS EXAMPLE ONLY)

NOTE 2. INF. DATA (I-FIELD) MAY CONSIST OF ANY AMOUNT OF BITS.
NOTE 3. CPU DOES NOT KNOW UNTIL RECEIVED END OF MESSAGE (REOM) THAT THIS IS AN FCS CHARACTER.

Figure 9 WD1933 RECEPTION TIMING DIAGRAM

111

,..

READ

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Storage Temperature
Storage Temperature
Voltage on any pin
with respect to GND (V 55)
Power Dissipation

-55'C to +125'C (plastic package)
-65'C to +150'C (ceramic package)
-0.3 to + 7.0V
tW

DC Characteristics
TA = O'C to +70'
Vss = OV, VCC =+5 ± 0.25V
Symbol
III
ILO
V,H
V,L
VOH
VOL
Icc

Parameter

Min

Input Leakage
Output leakage
Input High Voltage
Input low Voltage
Output High Voltage
Output low Voltage
Supply Current

Typ

Max

Conditions

Units
uA
uA
V
V
V
V
ma

10
to
2.4
0.8
2.4
0.4
40

VIN = Vee
Vout = Vee or Vss
All Inputs
10 = -100uA
10= 1.6mA

Table 3 WD1933 DC CHARACTERISTICS
AC Characteristics
TA = O'C to +70'C
Vss=OV,Vee= +5±0.25V
Symbol
TAS
TAH
Tess
TesH
TREO
Tov
TORQlR
T'NTRQR
TRE
Tos
TOH
TORQOR
TWE
Fe

Parameter

Min

READ AND WRITE
Address Set-up
Address Hold
Chip Select Set-up
Chip Select Hold
READ
Data Delay from RE
Data Valid from RE
DROI Reset Delay
INTRO Reset Delay
RE pulse width
WRITE
Data Set-up
Data Hold
DROO Reset delay
WE pulse width
Input Clock
32X
lX
32X

lX
32X

Typ

Max

Units

Conditions
CL = 50 pF

ns
ns
ns
ns

0
0
0
0

CL = 50pF
240
140
280
280
120
120
0
330
120
DC
DC
DC
DC
DC
DC
DC
DC

2.0
0.5
2.0
1.0
2.0
1.5
2.5
2.0

Table 4 WD1933 AC CHARACTERISTICS

112

ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

C L = 50pF
CL = 50pF

WDl 933-00/1 0
WDl 933-00/1 0
WD1933-01/11
WD1933-01/11
WD1933-02/12
WD1933-02/12

WD1933-03
WD1933-03

HIGH IMP. STATE

VALID

7\O,7\i.A2

-------.1:TORQIR_

ORal

INTRQ

TRE

- - -

- - - - - - 1E_QR_
Figure 10 WD1933 READ TIMING DIAGRAM

7\O.A1,A2

ORao

Figure 11 WD1933 WRITE TIMING DIAGRAM

113

ORDERING INFORMATION

Part No.
WD1933A-DD
WD1933A·1D
WD1933B·DO
WDt933B-1D
WD1933A-Dl
WD1933A-ll
WD1933B-Dl
WD1933B·ll
WD1933A·D2
WD1933A-12
WD1933B-D2
WD1933B-12
WD1933A·D3
WD1933B-D3

Package Type

Loop Mode

Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic

no
yes
no
yes

no
yes
no
yes
no
yes
no
yes
no
no

Maximum
Data Rate

Temp. Range

5DDKBPS
5DDKBPS
5DDKBPS
50DKBPS
1.DMBPS
1.DMBPS
1.DMBPS
1.DMBPS
t.5MBPS
1.5MBPS
1.5MBPS
l.5MBPS
2.DMBPS
2.DMBPS

DOC
DOC
D'C
DOC
DOC
DOC
DOC
DOC
DOC
DOC
DOC
DOC
DOC
DOC

to
to
to
to
to
to
to
to
to
to
to
to
to
to

+7DoC
+7DoC
+7DoC
+7D'C
+7D'C
+7D'C
+7DoC
+7DoC
+7DoC
+7D'C
+7D'C
+7D'C
+7DoC
+7DoC

Table 5 WD1933 ORDERING INFORMATION

J::::::O:: : :l+

DO'

2 OOQ REF

0115 MAX

~_~rr
0040

---l1---Ol00TYP

--!-O

!:o 010

-1
"5
- 0

WD19338 PLASTIC PACKAGE

WD1933A CERAMIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western
Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of Western Digital Corporalion. Western Digital Corporation reserves the right to change
said circuitry at any lime without notice.

WESTERN DIGITAL
CORPORArlON

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

114

WESTERN DIGITAL

BR1941

Dual Baud Rate Clock

FEATURES

GENERAL DESCRIPTION

16 SELECTABLE BAUD RATE CLOCK
FREQUENCIES

•

DUAL SELECTABLE 16 X CLOCK OUTPUTS
FOR FULL DUPLEX OPERATIONS

•

OPERATES WITH CRYSTAL OSCILLATOR OR
EXTERNALLY GENERATED FREQUENCY
INPUT

The BR1941 is a combination Baud Rate Clock Gen- ~
erator and Programmable Divider. It is manufactured in
N-channel MOS using silicon gate technology. This de- ~
vice is capable of generating 16 externally selected
clock rates whose frequency is determined by either a
single crystal or an externally generated input clock. The
BR1941 is a programmable counter capable of generating a division from 2 to (2 15 -1).

ROM MASKABLE FOR NON-STANDARD FREQUENCY SELECTIONS

.. INTERFACES EASILY WITH MICROCOMPUTERS
..

OUTPUTS A 50% DUTY CYCLE CLOCK WITH
0.01% ACCURACY

18 PIN CERAMIC DIP PACKAGE

o 3 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE

:.:II:

:li

The BR1941 is available programmed with the most
used frequencies in data communication. Each frequency is selectable by strobing or hard wiring each of
the two sets of four Rate Select inputs. Other frequencies/division rates can be generated by reprogramming
the internal ROM coding through a MOS mask change.
Additionally, further clock division may be accomplished
through cascading of devices. The frequency output is
fed into the XTAL/EXT input on a subsequent device.
The BR1941 can be driven by an external crystal or by
TIL logic.

TA
TB
TC

XTAl/EXT 1
+5V

XTAlIEXT 2

STT

STR

GND

+12V

NCRA
RB
RC
RD

-INTERNALLY BONDED. DO NOT CONNECT
ANYTHING TO THIS PIN.

PIN CONNECTIONS

BR1941

115

BLOCK DIAGRAM

PIN DESCRIPTION
PIN NUMBER
1

SYMBOL
XTAL/EXT 1

NAME

FUNCTION

Crystal or
External Input 1

This input receives one pin of the crystal package or
or one polarity of the external input.

VCC

Power Supply

+5 volt Supply

Receiver Output
Frequency

This output runs at a frequency selected by the
Receiver Address inputs.

RA. RB. RC. RD

Receiver Address The logic level on these inputs as shown in Table 1.
selects the receiver output frequency. fRo

STR

Strobe-Receiver
Address

A high-level input strobe loads the receiver address
(RA. RB. RC. RD) into the receiver address register
This input may be strobed or hard wired to +5V.

VDD
NC

Power Supply

+12 volt Supply

No Connection

Internally bonded.Do not connect anything to this pin.

GND

Ground

STT

Strobe-Transmitter A high-level input strobe loads the transmitter address
Address
(TA. TB. TC. TD) into the transmitter address register.
This input may be strobed or hard wired to +5V.

TO. TC. TB. TA

Transmitter
Address

The logic level on these inputs. as shown in Table 1.
selects the transmitter output frequency. fT'

Transmitter Output Frequency

This output runs at a frequency selected by the
Transmitter Address inputs.

XTAL/EXT 2

Crystal or
External Input 2

This input receives the other pin of the crystal package or the other polarity of the external input.

4-7

13-16

STROBE
,STRSTT'

CRYSTAL OPERATION
BR1941

EXTERNAL INPUT OPERATION
BR1941

\~:'
"ADDRESS NEED ONl ¥ Sf vAUO DURING THE LAST

Tf>W TIME Of THE INPUT STROBE

CONTROL TIMING

CRYSTAL/CLOCK OPTIONS

116

ABSOLUTE MAXIMUM RATINGS
+20.0V

Positive Voltage on any Pin, with respect to ground
Negative Voltage on any Pin, with respect to ground

-0.3V
(plastic "M" package) - 65°C to + 125°C
(ceramic "L" package) - 65°C to + 150°C

Storage Temperature
Lead Temperature (Soldering, 10 sec.)

+325°e

·Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and Functional Operation of the device at these or at any other condition
above those indicated in the operational sections of this specification are not implied.

ELECTRICAL CHARACTERISTICS
(TA =ooe to 70 oe, Vee =+5V ±5Ofa, Voo

PARAMETER

MIN

=+12V ± 50fa, unless otherwise noted)

TYP

MAl(

UNIT

COMMENTS

CtiARACTEAlSTICS

/'.,,-,

,:-' ,,-,

,1;ACCHARACTERISTICS

:/'CJ..OCKfREQUENCV
','7Rl.lLSE.iNIDTH(Tpwl
;:pIQck
;;;f\eeeiver; lItrobe

itter.strobet

NOTE1: Input set-up time can be decreased to >0 ns by increasing the minimum strobe width by 50 ns to a
total of 200 ns.
All inputs except XTALlEXT have internal pull-up resistors.

117

OPERATION
Standard Frequencies
Choose a Transmitter and receiver frequency from the table
below. Program the corresponding address into TA-TD and
RA-RD respectively using strobe pulses or by hard wiring the
strobe and address inputs.
Non-Standard Frequencies
To accomplish non-standard frequencies do one of the
following:
1. Choose a crystal that when divided by the BR1941 generates the desired frequency.
2. Cascade devices by using the frequency outputs as an input to the XTAL/EXT inputs of the subsequent BRl941.
3. Consult the factory for possible changes via ROM mask
reprogramming.
FREQUENCY OPTIONS

TABLE 1 CRYSTAL FREQUENCY = 5.0688 MHZ
Transmit/Receive
Address

Theoretical

Actual

Frequency
16X Clock

0.8 KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2

O.8KHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.83
115.2
153.6
316.8

Baud

Rate

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SO
75
110
134.5
ISO
300
600
1200
1800
2000
2400
3500
4800
7200
9600
19,200

Duty
Percent

Error

0.Q16

Cycle
%

Divisor

SO/SO
SO/SO
SO/SO
SO/SO
SO/SO
SO/SO

SO/SO

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88

SO/SO
SO/50
48/52
SO/SO

66
44
33
16

50/50

SO/SO

0.253

SO/SO
SO/SO

3.125

5OISO

BR1941-00
TABLE 2. CRYSTAL FREQUENCY = 4.9152 MHZ

D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Transmit/Receive
Address
C
B

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Baud

Theoretical
Frequency

Rate

16X Clock

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SO
75
110
134.5
ISO
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19,200

*When the duty cycle is not exactly 50% it is 50%

0.8 KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2

28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
.:!:

Duty

Actual

Frequency
16X Clock
0.8 KHz
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2

100/0

BR1941\-05

118

Percent

Error

Cycle
%

6144
4096
2793

5OISO
SO/SO

2284

-0.01

Divisor

SO/SO
60/60

5OISO

2048
1024
512
256
171
154
128
85
64

5OISO
50150

32
16

-0.19
-0.26

SO/SO

5OISO
SO/SO

0.39

-o.n

TABLE 3 CRYSTAL FREQUENCY
Transmit/Receive
Address

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

= 5.0688 MHZ

Theoretical

Actual

Baud
Rate

Frequency

32>< Clock

Frequency
32X Clock

50
75
110
134.5
1SO
200
300
600

1.6 KHz

2.4
3.52

4.304

4.303

.026

4.8
6.4
9.6
19.2

4.8
6.4
9.6
19.2
38.4
57.6

1200

38.4

1800
2400
3600
4800
7200
9600
19,200

57.6
76.8
115.2
153.6
230.4
307.2
614.4

·When the duty cycle IS nol exactly 50% It IS 50"/"

:!:

Duty
Percenl

Error

76.8
115.2

153.6
230.4
298.16
633.6

Cycle
%

SO/SO
SO/SO
SO/50
SO/SO
SO/50
SO/50
SO/SO
SO/SO
SO/50
SO/50
SO/SO
SO/50

SO/50

2.941
3.125

SO/SO

Divisor
3168
2112

1440
1178
1056

792
528
264
132
88
66
44
33
22
17
8

10''10

BR1941-06

APPLICATIONS INFORMATION
OPERATION WITH A CRYSTAL

The BR1941 Baud Rate Generator may be driven by either
a crystal or TTL level clock, When using a crystal, the waveform that appears at pins 1 (XTALlEXT 1) and 18 (XTALlEXT
2) does not conform to the normal TTL limits of V IL '" 0.8V
and VIH '" 2.0V. Figure 1 illustrates a typical crystal
waveform.
Since the D,C, level of the waveform causes the least positive point to typically be greaterthan 0.8V, the BR1941 is designed to look for an edge, as opposed to a TTL level. The
XTALlEXT logic triggers on a rising edge of typically 1V in
magnitude. This allows the use of a crystal without any additional components.

OPERATION WITH TTL LEVEL CLOCK

With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot can appear at pins 1 and/or 18.
The BR1941 may, at times, trigger on a rising edge of an
overshoot or undershoot waveform, causing the device to effectively "double-trigger". This phenomenon may result as a
twice expected baud rate, or as an apparent device failure,
Figure 2 shows a typical waveform that exhibits the "ringing"
problem.
The design methods required to minimize ringing include the
following:
1. Minimize the P.C. trace length. At 5 MHz, each inch of
trace can add significantly to overshoot and undershoot.

119

2. Match impedances at both ends of the trace. For example, a series resistor near the BR1941 may be helpful.
3. A uniform impedance is important. This can be accomplished through the use of:
a. parallel ground lines
b. evenly spaced ground lines crossing the trace on
the opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered
PC board.
In the event that ringing exists on an already finished board,
several techniques can be used to reduce it. These are:
1. Add a series resistor to match impedance as shown in
Figure 3.
2. Add pull-up/pull-down resistor to match impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in Figure 5.
The method that is easiest to implement in many systems is
method 1, the series resistor. ·The series resistor will cause
the D.C. level to shift up, but that does not cause a problem
since the BR 1941 is triggered by an edge, as opposed to a
TTL level.
The BR1941 Baud Rate Generator can save both board
space and cost in a communications system. By choosing
either a crystal or a TTL level clock, the user can minimize
the logic required to provide baud rate clocks in a given
design.

CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency-5.0688 MHz, or 4.9152 MHz
Temperature range O°C to 70°C
Series resistance 50n
Series resonant
Overall tolerance ± .01%

Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000
CAL Crystal
1142 N. Gilbert Street
Anaheim, California 92801
(Available in HC-18 small can)
(714) 991-1580

CRYSTAL MANUFACTURERS (Partial List)
Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591

CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786-8411

5.0

4.0

VOLTS

3.0
2.0
1.0

Time

Figure 1 TYPICAL CRYSTAL WAVEFORM

+5.0
+4.0

VOLTS

+3.0
+2.0
+1.0
0

-1.0

Time

Figure 2 TYPICAL "RINGING" WAVEFORM

120

Typical Values
R1 = R2=33fl

BR1941

Figure 3 SERIES RESISTOR TO MATCH IMPEDANCE

+5V
+5V

R1.

""
1

R4
18

R2
~

Typical Values
R1=R3=2.7K
R2 = R4=3.3K

BR1941

Figure 4 PULL-UP/PULL-DOWN RESISTORS TO MATCH IMPEDANCE

~
BR1941

Figure 5 HIGH-SPEED DIODE TO CLAMP UNDERSHOOT

121

°920

100'5

0'50~Mi'N
....i.

50
MAX.
0'

MAX.

I
QillE

--11:-

0021--1

--J
0035
0055

L 0090

0110

mmm

LI~,~2~1

MAX.---

00"--11:-

0125

002'--1

MIN

BR1941L CERAMIC PACKAGE

--J
0035
0055

Lo090

OliO

0125
MIN

0320

1
I

MAX 1

~~;~g-l

BR1941M PLASTIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliabJe. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may resuH from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

122

WESTERN
DIGITAL
p
c

WD1983 (BOART)
BUS ORIENTED ASYNCHRONOUS RECEIVER/TRANSMITTER
FEATURES
ASYNCHRONOUS MODE
•
•
•
•
•
•
•
•
•
•
•
•

BAUD RATE-DC TO 3BK BITS/SEC (lBX)
SELECTABLE CLOCK RATES

FULL DUPLEX OPERATION
SELECTABLE 5,B,7, & 8 BIT CHARACTERS
LINE BREAK DETECTION AND GENERATION
1, 1Y2, or 2 STOP BIT SELECTION
FALSE START BIT DETECTION
OVERRUN AND FRAMING ERROR DETECTION
DC TO 3BK BITS/SEC (lBX)
DC TO BOOK BITS/SEC (1 X)
8251/8251 A ASYNCHRONOUS ONLY REPLACEMENT
REQUIRES NO ASYNCHRONOUS SYSTEM CLOCK
28 PIN PLASTIC OR CERAMIC
+5 VOLT ONLY

• lX, lBX, 64X, BAUD RATE CLOCK INPUTS
• UP TO 47% DISTORTION ALLOWANCE
WITH 64X CLOCK

ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL INTERFACE

GENERAL DESCRIPTION
The WD 1983 is an N channel silicon gate MOs/LSI device
that interfaces a digital asynchronous channel with a parallel
channel. It is available in a ceramic or plastic standard 28 pin
dual in line package.
The WD1983 is a fully programmable microprocessor I/O peripheral with two control registers and a status register. It is
capable of fu II duplex operations.

D,
27

"
"
"

Vcd+SV)

(GNO)Vss

D,
D,
D,
D,

i'XC
WE

os
c/O'

DSA
MA

TXD

TXE
" -Ci'S
17

fiE
RXADY

Axe

DTA
RTs

BRKOET

TXADY

FIGURE 1 WD1983 PIN-OUT

III

APPLICATIONS

• DOUBLE BUFFERING OF DATA
• 8 BIT BI-DIRECTIONAL BUS FOR DATA, STATUS, AND
CONTROL WORDS
• ALL INPUTS AND OUTPUTS TTL COMPATIBLE
• CHIP SELECT, RE, WE, C/O INTERFACE TO CPU
• ON-LINE DIAGNOSTIC CAPABILITY
• THREE STATE DATA BUS

:::)

UJ
II-

SYSTEM COMPATIBILITY

AXD

>"
a:

FIGURE 2 WD1983 BLOCK DIAGRAM

123

PIN. NO.

PIN NAME

SYMBOL

FUNCTION

POWER GND

VSS

Ground

POWER SUPPLY

VCC

+5 Volts

CHIP SELECT

(jS

This input, when low, enables READ or WRITE operations.

READ ENABLE

This input, when low, accesses the contents of the addressed
register.

WRITE ENABLE

This input, when low, writes the data on the DATA BUS into the
addressed register.

MASTER RESET

This input, when high, initializes the device and clears the
COMMAND and MODE REGISTERS.

CONTROL/DATA

C/O

This input selects the CONTROL or DATA register. It is used in
conjunction with a READ or WRITE enable.

TRANSMIT DATA

TXD

This output is the transmit serial data. When no data is being
transmitted or after MASTER RESET, this output is high (a
marking condition). COMMAND CONTROL word bit 3 is used
to program a break cond ition by forcing the TXD output to a
low (spacing condition).

TRANSMIT CLOCK

'i'XC

This input is the source clock for transmission. MODE IN·
STRUCTION word bits MRO & MR1, control 1X, 16X, or 64X,
times the transmitted bit rate.

TRANSMIT EMPTY

TXE

This output is set high after MASTER RESET and is automatically reset when a character is written into the TRANSMITTER HOLDING REGISTER. It returns high at the end of a
transmitted character indicating the end of transmission if the
TRANSMIT HOLDING REGISTER has not been loaded.

TRANSMIT READY

TXRDY

This output is set high after MASTER RESET. It indicates that
the transmitter is ready to accept a character and is automatically reset whenever a character is written into the TRANSMITTER HOLDING REGISTER.

124

PIN NO.

PIN NAME

SYMBOL

FUNCTION

RECEIVE DATA

RXD

This input is the received serial data.

RECEIVE CLOCK

RXC

This input is the receiver clock. MODE INSTRUCTION word
bits MRO & MR1 control whether this input is 1X, 16X or 64X
limes the received bit rate.

RECEIVER READY

RXRDY

This output is set low after MASTER RESET. When set high
il indicates that the receiver has assembled a character and
transferred illo the RECEIVER HOLDING REGISTER. It is
automatically reset when the RECEIVER HOLDING REG·
ISTER is read.

BREAK DETECT

BRKDET

This output is reset after MASTER RESET. It is set high
when the receiver detects a string of zeros equal to the pro·
grammed character length including start, parity and stop
bits. Upon detecting a valid one data bit it's reset. Assembly
of the next character is begun after detecting a valid start bit.

CLEAR TO SEND

CTS

This input is sellow to enable Ihe Iransmitter. When set high
it disables transmission. If the transmitter is transmitting a
character, it will terminate transmission after the TRANSMIT·
TER REGISTER is empty.

DATA TERMINAL READY

DTR

This is a general purpose output which is set and cleared by
COMMAND word bit CR1. It is reset after MASTER RESET.

REQUEST TO SEND

RTS

This is a general purpose output which is set and cleared by
COMMAND word bit CRS. It is reset after MASTER RESET.

1,2,5,
6,7,8,
27,28

DATA BUS

DATA SET READY

DO
THRU
D7

-DSR

125

These are input/output pins. Dala on the DATA BUS is wril·
ten into Ihe selected register during a WRITE operation. Dur·
ing a READ operalion, Ihe DATA BUS is driven by data in
the selecled register. When nol selected, (CS high), these
pins are in a high impedance slate.

This is a general purpose input which is sensed in STATUS
REGISTER bit #7.

No internal connection, pin nol used.

ORGANIZATION

OPERATING DESCRIPTION

The WD1983 Block Diagram is illustrated on Page 1. The
WDI983 (BOART) is an eight bit bus-oriented device. Communication between the BOART and the controlling CPU occurs via the 8 bit DATA BUS. There are 2 accessible DATA
REGISTERS, which buffer Transmit and Receive DATA. They
are the TRANSMIT HOLDING REGISTER and the RECEIVE
HOLDING REGISTER. There is a parallel-to-serial shift register (the TRANSMIT REGISTER) and a serial-to-parallel shift
register (the RECEIVE REGISTER).

The WD1983 (BOART) is primarily designed to operate in an
8 bit microprocessor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, C/O, RE and WE) should be connected to the microprocessor's data bus and system control
bus. The appropriate TXC and RXC clock frequencies should
be selected for the particular application using a programmable baud rate generator such as the BR1941.

Operational control and monitoring of the BOART is performed by two CONTROL REGISTERS (the COMMAND INSTRUCTION REGISTER and the MODE INSTRUCTION
REGISTER) and the STATUS REGISTER.

For typical data communication applications, the RXD and
TXD inpuUoutputs can be connected to RS-232C interface circuits or a modem.

A READ/WRITE control circuit allows monitoring/programming or reading/loading in the CONTROL, STATUS or HOLDING REGISTERS by activating the appropriate control lines:
Chip Select (CS), Read Enable (RE), Write Enable (WE) and
Control or Data Select (C/O).
Internal Ctlntrol of the BOART is by means of two internal MICROCONTROLLERS; one for transmit and one for receive.
The CONTROL REGISTERS, MODEM CONTROL LOGIC,
READ/WRITE CONTROL LOGIC and various counters provide inputs to the MICROCONTROLLERS, which generate the
necessary control signals to send and receive serial data according to the programmed asynchronous format.

READ/WRITE OPERATIONS
The WD1983 must be initialized after a MASTER RESET
pulse by first writing the MODE INSTRUCTION word and then
the COMMAND INSTRUCTION word. Thereafter, every control write to the device is interpreted as a COMMAND word. If
it is desired to re-program the MODE REGISTER, a COMMAND REGISTER bit, INTERNAL RESET (CRG), allows the
next control write data to be entered into the MODE
REGISTER.

The TXRDY, RXRDY, TXE and BRKDET Flags may be connected to the microprocessor system as interrupt inputs or the
STATUS REGISTER can be periodically read in a polled environment to support BOART operations.
MODEM CONTROL SIGNALS can be configured several
ways as the DTR, RTS and DSR signals are controlled and
sensed by the CPU through the COMMAND and STATUS
REGISTERS. The CTS input is used to synchronize the transmitter to external events.
The SBRK bit of the COMMAND REGISTER (CR3) is used to
send a Break Character. (A break character is defined as a
start bit, and all zero data, parity and stop bits). When the CR3
bit is set to a "1", it causes the transmitter output, TXD, to be
forced low after the last word is transmitted.
The receiver is equipped with logic to look for a break character. When a break character is received, the BREAK DETECT (BRKDET) FLAG and STATUS bit are set to logic "1".
When the receiver input line goes high again for the least "one
data bit time," the receiver resets the BREAK DETECT FLAG
and resumes its search for a start bit.

The WD1983 registers are accessed according to the following table:

(
c/O'=-

CS C/O RE WE REGISTERS SELECTED
L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

H
L
H
L
X

C/O=; H

Read RECEIVE HOLDING REGISTER
Write TRANSMIT HOLDING REGISTER
Read STATUS REGISTER
Write CONTROL REGISTER
DATA BUS tri-stated

C/O== L

c/o=

MODE INSTRUCTION WORD
COMMAND INSTRUCTION WORD

DATA
CHARACTER(S)

COMMAND INSTRUCTION WORD
DATA
CHARACTER(S)

COMMAND INSTRUCTION WORD

TYPICAL DATA BLOCK TRANSFER

Note:

"L" means V IL at pins
"H" means V IH at pins
"X" means don't care

126

MODE INSTRUCTION CONTROL WORD FORMAT

MR4

MR7

EVEN

No. of STOP bits
00 = invalid

MRl

MRO

\~_--, _ _-JI''-_--r _ _-il

MR2

PARITY
GENERATIONI

PARITY
ENABLE:
1 = enable

check"

o = disable

1 bit

CHARACTER
LENGTH:

11 = 2 bits

FACTOR
00 == invalid

1 = even
a = odd

10'" lV2 bits

BAUD RATE

00 '" 5 blts
01 = 6 bits
10"" 7 bits
11 = 8 bits

10 = XI6

11 = X64

COMMAND INSTRUCTION CONTROL WORD FORMAT

CRG

CR7

I
DON'T
CARE

CRS

CR4

INTERNAL
RESET
(IR)

REQUEST

1 = returns
W0198310

1 = forces
output low

iAi'S),

word format

Ilags
o '" forces
RTS output
high

SEND
BREAK
CHARACTER
(SBRKI·

1 = resets PE,
DE & FE error 1 == forces TXD

mode instruction
o

= nonnal
operation

CRO

CRl

CR2

I
ERROR
RESET
(ERI

TO SEND

Ri"S

CR3

RECEIVE
ENABLE
(RXE)

READY

iDrRi,

t = enable
receiver

outpUllow
o

DATA
TERMINAL

DTR

1 = forces
oulpullow

disable

normal
operation

o == forces

I5"I'A

TRANSMIT
ENABLE
TXEN
1 = enable
transmitter

o = disable
transmitter

output

STATUS WORD FORMAT

SR4

SR3

SR2

SRl

OVERRUN
ERROR
(DE),

PARllY
ERROR
(PE),

TXE
(SEE NOTE)

RXRDY
(SEE NOTE)

1 = CPU

1 = parity error
detected

SR7

0sR
(SEE NOTEI

BRKDET
(SEE NOTE)

FRAMING
ERROR
(FE)"

1 '" invalid
stop bit detected

did not read

at the end

the character

of the character

before the

o = No

next one

Parity error

o '" No

became

detected

framing error
detected
(Reset by CR4)

available

(Reset by CR4)

SRO

TXADY
(SEE NOTE)

detected
(Reset by CR4)

FE, OE & PE FLAGS DO NOT INHIBIT OPERATION.
THESE FLAGS ARE STATUS ONLY.

127

NOTE:
SRO, SR1, SR2, SR6, and SR7
HAVE IDENTICAL MEANINGS AS THE
EXTERNAL OUTPUT PINS.

ABSOLUTE MAXIMUM RATINGS

VDD with Respect to VSS (Ground)
Max. Voltage to any
Input with Respect to VSS

15to-0.3V

Storage Temp.
Ceramic -65°C to + 150°C
Plastic -55°C to + 125°C

+ 20 to-0.3V

Power Dissipation

('E' Package)
('F' Package)

1000MW

OPERATING CHARACTERISTICS
TA

= O°C to 70o e, Vee = + 5.0V ± .25V,

SYMBOL

Vss = OV

CHARACTERISTIC

MIN

TYP

UNITS

MAX

CONDITIONS

III

Input Leakage

VIN

IDL

Data Bus Leakage

Data Bus is
in high impedence
state

ICCAVE

VCC Supply Current

5.25 VDC/fCLK =
600 kHz No Loads.

VIH

Input High Voltage

0.8

45
2.4

VIL

Input Low Voltage (All Inputs)

VOH

Output High Voltage

VOL

Output Low Voltage

Vcc

-0.3

2.4

= -

0.45

100jlA
(source)

1.6 mA
(sink)

TABLE 1 WD1983 DC CHARACTERISTICS

VO< - - - - - - - - -

x~:~

VOL _ _ _ _ _ _ _ _ _

TEST POINTS

~:~X'-

_______

FIGURE 3 INPUT WAVEFORMS FOR AC TESTS
NOTE: ALL WAVEFORMS ARE MEASURED AT 2.0V IF RISING EDGE, AND O.BV IF FALLING EDGE.

128

VOH

DATA BUS
Vac

CIO

V'H

VIC

VIii

VIC

FIGURE 4 READ TIMING

DATA BUS

V'H
VIC

XXXX7XXX(

T as

V'H

C/O

TWOH

VIC

V,"

WE
VIC

FIGURE 5 WRITE TIMING

NOTE:
8251A COMPATIBILITY

The WD1983 (BOART) is an asynchronous only device, which is compatible with the
8251A. However, in test evaluation and application, the following differences should be noted:
(1) The WD1983 utilizes the transmit and receive baud clocks in their respective internal logic sections instead of the system clock normally applied
to Pin 20 on the 8251A. This Pin on the WD1983 is not used.
(2) As a result of the above condition, timings referenced to the system clock
period in the 8251A specification are now specified in absolute time units
or with respect to the transmit or receive baud clock.

129

AC Electrical Characteristics
T A = DoC to + 70°C; Vcc = 5.0 V ± 5%; GND = 0 V

SYMBOL

PARAMETER

MIN

MAX

UNIT

TEST CONDITIONS

BUS PARAMETERS
READ CYCLE

tAR

Address Stable Before RE (CS,C(D)

tRA

Address Hold Time for RE (CS,C(iS)

tRE

RE Pulse Width

350

tRO

Data Delay from RE

200

CL = 50pF

tROH

RE to Data Floating

200

CL =

50pF
15pF

WRITE CYCLE

tAW

Address Stable Before WE

tWA

Address Hold Time for WE

tWE

WE Pulse Width

350

tos

Data Set-Up Time for WE

200

tWOH

Data Hold Time for WE

OTHER TIMINGS

CL = 100pF

200

CL = 100pF

RX Data Hold Time to Sampling Pulse

100

CL= 100pF

Transmitter Input Clock Frequency
1X Baud Rate
16X and 64X Baud Rate

DC
DC

Transmitter Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate

1.0
500

tOTX

TXD Delay from Falling Edge of TXC

tSRX

RX Data Set-Up Time to Sampling Pulse

tHRX
fTX

tTPW

200

130

500
600

kHz
kHz

P.s
ns

SYMBOL

tTPD

fRX

tRPW

tRPD

PARAMETER

MIN

Transmitter Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

1.0
800

Receiver Input Clock Frequency
1X Baud Rate
16X and 64X Baud Rate

DC
DC

Receiver Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate

1.0
500

/Ls
ns

Receiver Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

1.0
800

/Ls
ns

MAX

UNIT

/LS
ns

500
600

kHz
kHz

tTX

TXRDY Delay from Center of Data Bit

tRXC

tRX

RXRDY Delay from Center of Data Bit

1/2

tRXC

tiS

Internal BRKDET Delay from Center of
Data Bit

tRXC

tTRD

TXRDY Delay from Falling Edge of WE

tTXC

tTOD

TXD Output from Falling Edge of WE

tTXC

twc

Control Delay from Rising Edge of WE .
(DTR. RTS)

400

tCA

Control to RE Set-Up Time (DSR. CTS)

500

TABLE 2 WD1983 AC CHARACTERISTICS

At 1 TX (max), the duty cycle should be 50%. At less than 1TX
(max), the minimum pulse width for the high or low half is
1

201 TX(max)
Hence, at frequencies less than 1 TX (max), the required duty
cycle will be less stringout than 50%.

131

TEST CONDITION

= 50pF

(16X)

~lJ

WEU

T:EWt~RD

---J 1-

ITRD

~ ~~'m'
TXD

L______________~~~______________________________________~~
! ..,,,,,.,
.

START BIT

FIGURE 6
TRANSMITTER OUTPUT TIMINGS WITH RESPECT TO TRANSMIT CLOCK

132

READ
AND
WRITE
TIMING

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16 TXC PERIODS

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RECEIVER
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INTERNAL
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AND
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DATA BITS

__________________PA_"_'TY_B_'T_,_IRX_4
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WRITE 1 sl CHARACTER

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WRITE 2nd CHARACTER

~1-.._'S"TA"'RO!T_"B,,'T_L---!D"'AT.e:A'"'B""T__

START BIT

1...-.....- - - - - - - - 1 5 1 DATA CHARACTER ------_~}.-FIGURE 7 SYSTEM TIMING DIAGRAMS

133

r--

WRITE 3rd CHARACTER

-----.::-PA"R='TY=B'=-T-.-::S"TQ"'P"B:-:'T,---,I

2nd DATA CHARACTER

WD1983 E CERAMIC PACKAGE

WD1983 F PLASTIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may fesu" from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REOHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

134

WESTERN DIGITAL
c

WD8250 Asynchronous Communications Element
FEATURES
o Designed to be Easily Interfaced to Most Popular
Microprocessors (Z-80, BOBOA, 6800, etc.)

o Internal Diagnostic Capabilities

.. Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or
from Serial Data Stream
.. Full Double Buffering Eliminates
Precise Synchronization

.. Programmable Baud Rate Generator Allows
Division of Any Input Clock by 1 to (2 16 - 1) and
Generates the Internal 16x Clock
.. Independent Receiver Clock Input
.. Fully Programmable Serial-Interface Characteristics
- 5-, 6-, 7-, or 8-Bit Characters
- Even, Odd, or No-Parity Bit Generation and
Detection
- 1-, 1'/'-, or 2-Stop Bit Generation
- Baud Rate Generation (DC to 56K Baud)
.. False Start Bit Detector
.. Complete Status Reporting Capabilities
.. THREE-STATE TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection

o Full Prioritized Interrupt System Controls
o Single +5-Volt Power Supply

Need for

.. Independently Controlled Transmit, Receive,
Line Status, and Data Set Interrupts

Loopback Controls for Communications
Link Fault Isolation
Break, Parity, Overrun, Framing Error
Simulation

GENERAL DESCRIPTION
The WD8250 is a programmable Asynchronous
Communications (ACE) chip contained in a standard 40-pin dual-in-line package. The chip, which is
fabricated using N-channel silicon gate technology;
functions as a seial data input/output interface in a
microcomputer system. The functional configuration of the WD8250 is programmed by the system
software via a THREE-STATE 8-bit bidirectional
data bus.
The WDB250 performs serial-to-parallel conversion
on data characters received from a peripheral
device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The
CPU can read the complete status of the WDB250 at
any time during the functional operation. Status
information reported includes the type and condition of the transfer opertions being performed by
the WD8250, as well as any error conditions (parity,
overrun, framing, or break interrupt).

WD8250 GENERAL SYSTEM CONFIGURATION

135

...g:

In addition to providing control of asynchronous
data communications, the WD8250 includes a programmable Baud Generator that is capable of dividing the timing reference clock input by divisors of 1
to (2 16 -1), and producing a 16xclockfordrivingthe
internal transmitter logic. Provisions are also
included to use this 16x clock to drive the receiver
logic. Also included in the WD8250 is a complete
MODEM-control capability, and a processorinterrupt system that may be software tailored tothe
user's requirements to minimize the computing time
required to handle the communications link.

selected. Chip selection is complete when the
decoded chip select signal is latched with an active
(low) Address Strobe (ADS) input. This enables
communication between the WD8250 and the CPU.
Data Input Strobe (DISTR, DISTR), Pins 22 and 21:
When DISTR is high or DISTR is low while the chip
is selected, allows the CPU to read status information or data from a selected register of the WD8250.
NOTE
Only an active DISTR or DISTR input is required
to transfer data from the WD8250 during a read
operation. Therefore, tie either the DISTR input
permanently low or the i5TSTI1 input permanently high, if not used.

WD8250 FUNCTIONAL PIN DESCRIPTION
The following describes the function of all WD8250
input/output pins. Some of these descriptions reference internal circuits.
NOTE
In the following descriptions, a low represents a logic 0 (0 volt nominal) and a high
represents a logic 1 (+2.4 volts nominal).

Data Output Strobe (DOSTR, DOSTR), Pins 19 and
18: When DOSTR is high or DOSTR is low while the
chip is selected, allows the CPU to write data or control words into a selected register of the WD8250.
NOTE
Only an active DOSTR or DOSTR input is
required to transfer data to the WD8250 during a write operation. Therefore, tie either
the DOSTR input permanently low or the
DOSTR input permanently high, if not used.

Input Signals
Chip Select (CSO, CS1, CS2), Pins 12-14: When CSO
and CSl are high and CS2 is low, the chip is

WD8250 BLOCK DIAGRAM

136

WD8250. The DSR signal is a MODEM-control function input whose condition can be tested by theCPl:J
by reading bit 5 (DSR) of the MODEM Status Register. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has changed state
since the previous reading of the MODEM Status
Register.

Address Stobe (ADS), Pin 25: When low, provides
latching for the Register Select (AO, A 1, A2) and
Chip Select (CSO CS1, CS2) signals.
NOTE
An active ADS input is required when the
Register Select (AO, A 1, A2) signals are not
stable for the duration of a read or write
operation. 11 not required, tie the ADS input
permanently low.

NOTE
Whenever the DSR bit of the MODEM Status
Register changes state, an interrupt is generated if enabled.

Register Select (AO, A 1, A2), Pins 26-28: These three
inputs are used during a read or write operation to
select a WD8250 register to read from or write into
as indicated in the table below. Note that the state of
the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register,
affects the selection of certain WD8250 registers.
The DLAB is reset low when the Master Reset (MR)
input is active (low); the DLAB must be set high by
the system software to access the Baud Generator
Divisor Latches.

DLAB

A2 Al AD

NOTE
Whenever the RLSD bit of the MODE:,~ Status Register changes state, an interrupt'is
generated if enabled.

0 Receiver Buffer (read), Transmitter
Holding Register (write)

Interrupt Enable

Interrupt Identification (read only)

0
0

Line Control
0 MODEM Control
1 Line Status

0 MODEM Status

1 None

0
0

0 Divisor Latch (least significant byte)

Received Line Signal Detect (RLSD), Pin 38: When
low, indicates that the data carrier has been
detected by the MODEM or data set. The RLSD signal is a MODEM-control function input whose conditin can be tested by the CPU by reading bit 7
(RLSD) of the MODEM Status Register. Bit 3
(DR LSD) of the MODEM Status Register indicates
whether the RLSD input has changed state since the
previous reading of the MODEM Status Register.

Ring Indicator (Ai), Pin 39: When low, indicates that
a telephone ringing signal t:§.s been received by the
MODEM or data set. The RI signal is a MODEMcontrol function input whose condition can be
tested CPU by reading bit 6 (RI) of the MODEM Status
Register. Bit 2 (TERI) of the MODEM Status Register indicates whether the Ri input has changed from
a low to a high state since the previous reading of
the MODEM Status Register.

NOTE
Whenever the RI bit of the MODEM Status
Register changes from a high to a low state,
an interrupt is generated if enabled.

Divisor Latch (most significant byte)

Master Reset (MR), Pin 35: When high, clears all the
registers (except the Receiver Buffer, Transmitter
Holding, and Divisor Latches), and the control logic
of the WD8250. Also, the state of vari~u..!E0 signals (SOUT, INTRPT, OUT1, OUT2, RTS, DTR) are
affected by an active MR input. (Refer to table 1.)

VCC, Pin 40: +5-volt supply.
VSS, Pin 20: Ground (O-volt) reference.
Output Signals

Receiver Clock (RCLK), Pin 9: This input is the 16x
baud rate clock for the receiver section of the chip.

Data Terminal Ready (DTR), Pin 33: When low,
informs the MODEM or data set that the WD8250 is
ready to communicate. The DTR output signal can be
set to an active low by programming bit 0 (DTR) of
~MODEM Control Register to a high level. The
DTR signal is set high upon a Master Reset
operation.

Serial Input (SIN), Pin 10: Serial data input from the
communications link (peripheral device, MODEM,
or data set).
Clear to Send (CTS), Pin 36: The CTS Signal is a
MODEM control function input whose condition
can be tested by the CPU by reading bit 4 (CTS) of
the MODEM Status Register. Bit
(DCTS) of the
MODEM Status Register indicates whether the CTS
input has changed state since the previous reading
of the MODEM Status Register.

Request to Send (RTS), Pin 32: When low, informs
the MODEM or data set that the WD8250 is ready to
transmit data. The RTS output signal can be set to
an active low by programming bit 1 (RTS) of the
MODEM Control Register. The RTS signal is set
high upon a Master Reset operation.

NOTE
Whenever the CTS bit of the MODEM Status
Register changes state, an interrupt is generated if enabled.

Output 1 (OUT 1), Pin 34: User-designated output
that can be set to an active low by programming bit 2
(OUT 1) of the MODEM Control Register to a high
level. The OUT 1 signal is set high upon a Master
Reset operation.

Data Set Ready (DSR), Pin 37: When low, indicates
that the MODEM or data set is ready to establish the
communications link and transfer data with the

137

Output 2 (OUT 2), Pin 31: User-designated output
that can be set to an active low by programming bit 3
(OUT 2) of the MODEM Control Register to a high
level. The OUT 2 signal is set high upon a Master
Reset operation.
Chip Select Out (CSOUT), Pin 24: When high, indicates that the chip has been selected by active CSO,
CS1, and CS2 inputs. No data transfer can be
initiated until the CSOUT signal is a logic 1.
Driver Disable (OOIS), Pin 23: Goes low whenever
the CPU is reading data from the WD8250. A highlevel DDIS output can be used to disable an external
transceiver (if used between the CPU and WD8250
on the D7-DO Data Bus) at all times, except when the
CPU is reading data.
Baud Out (BAUOOUT), Pin 15: 16x clock signal for
the transmitter section of the WD8250. The clock
rate is equal to the main reference oscillator frequency divided by the specified divisor in the Baud
Generator Divisor Latches. The BAUDOUT may
also be used for the receiver section by tying this
output to the RCLK input of the chip.

Interrupt (INTRPT), Pin 30: Goes high whenever
anyone of the following interrupt sources has an
active high condition: Receiver Error Flag; Received
Data Available; Transmitter Holding Register
Empty; and MODEM Status. The INTRPT signal is
reset low upon a Master Reset operation.
Serial Output (SOUT), Pin 11: Compositeserial data
output to the communications link (peripheral,
MODEM or data set). The SOUT signal is set to the
Marking (logic 1) state upon a Master Reset
Operation.
Input/Output Signals
Data (07-00) Bus, Pins 1-8: This bus comprises
eight TRI-STATE input/output lines. The bus provides bidirectional communications between the
WD8250 and the CPU. Data, control words, and status information are transferred via the D7-DO Data
Bus.
External Clock Input/Output (XTAL 1, XTAL 2), Pins
16 and 17: These two pins connect the main timing
reference (crystal or signal clock) to the WD8250.

Table 1. Reset Control of Registers and Pinout Signals
Register/Signal

Reset Control

Reset State

Receiver Buffer Register

First Word Received

Data

Transmitter Holding Register

Writing into the
Transmitter Holding Register

Data

Interrupt Enable Register

Master Reset

Atl Bits Low
(0-3 forced and 4-7 permanent)

Interrupt Identification Register

Master Reset

Bit 0 is High and
Bits 1-7 Are Permanently Low
All Bits Low

Line Control Register

Master Reset

MODEM Control Register

Master Reset

All Bits Low

Line Status Register

Master Reset

All Bits Low.
Except Bits 5 and 6 Are High

Master Reset
Modem Status Register

MODEM Signal Inputs

Bits 0-3 Low
Bits 4-7 -

Input Signal

Divisor Latch (low order bits)

Writing into the Latch

Data

Divisor Latch (high order bits)

Writing into the Latch

Data

SOUT

Master Reset

High

BAUDOUT

Writing into either Divisor Latch

Low

CSOUT

ADS Strobe Signal and State of
Chip Select Lines

High/Low

DO IS

DDIS CSOUT • RCLK • DISTR
(At Master Reset. the CPU
sets RCLK and DISTR low.)

High

INTRPT

Master Reset

Low

OUT 2

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUT 1

Master Reset

High

07-00 Data Bus Lines

In THREE-STATE Mode.
Unless CSOUT • DISTR = High
or CSOUT • DOSTR = High

THREE-STATE
Data (ACE to CPU)
Data (CPU to ACE)

138

WD8250 ACCESSIBLE REGISTERS

the Line Control Register. In addition to controlling
the format, the programmer may retrieve the contents of the Line Control Register for inspection.
This feature simplifies system programming and
eliminates the need for separate storage in system
memory of the line characteristics. The contents of
the Line Control Register are indicated and are described below.

The system programmer may access or control any
of the WD8250 registers summarized in table 2 via
the CPU. These registers ae used to control WD8250
operations and to transmit and receive data.
WD8250 Line Control Register
The system programmer specifies the format of the
asynchronous data communications exchange via

Table 2. Summary 01 WD8250 Accessible Registers
Register Address
o OLABcO
Receiver
Buffer
Register
(Read
Only)

Bit
No

Data BitO'

Data Bit 1

o DLABcO
Holding
Register
(Wflte
Only)

Data Bit 0

Data 81t 1

10LABcO

OOLABcl

lDLAB=1

Line
Control
Register

MODEM
Control

Line
Status
Register

MODEM
Status

Divisor
Latch
(LS)

Divisor
Latch
(MS)

Data

Delta
Clear to

Bit 0

Bit 8

Bit 1

Bit 9

Interrupt

Interrupt
Enable
Register
Enable
Received
Data
Available
Interrupt
(ERBFI)

Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)

Identif,cation
Register

Word
Length
Select
Bit 0
(WLSO)

Terminal
Ready
(OTR)

Ready
(DR)

Interrupt

Word
Length

Request

Select

to Send

B,t (0)

Bit 1
WLSI)

(ATS)

Overrun
Error
(OA)

"0" if
Interrupt
Pending

Data

Registe~

Send
(OCTS)

Delta

Data Set
Ready
(OOSA)

Data Bit 2

Data Sit 2

Enable
Receiver
Line
Status
Interrupt
(ELSI)

Interrupt
10
B,t (I)

Number
of Stop
Bits
(STB)

Oul I

Parity
Error
(PE)

Trailing
Edge Ring
Indicator
(TERI)

B,t 2

Bit 10

Data Bit3

Data Sit 3

Enable
MODEM
Status
Interrupt
(EOSSI)

Parity
Enable
(PEN)

Out 2

Framing
Error
(FE)

Delta
Receive
Line Signal
Detect
(OSLSO)

Bit 3

Bit 11

Data Bit4

Data Bit 4

Even
Parity
Select
(EPS)

Loop

Break
Interrupt
(BI)

Clear to
Send
(CTS)

Bit 4

Bit 12

Data Bit 5

Stick
Parity

Transmitter
Holding
Register
Empty
(THAE)

Data
Set
Ready
(OSR)

Bit 5

Bit 13

Ring
Indicator
(RI)

Bit 6

Bit 14

Received
Line
Signal
Detect
(ALSO)

Bit 7

Bit 15

Data Bit6

Data Bit 6

Set Break

Transmitter
Shift
Register
Empty
(TSAE)

Data Bit 7

Divisor
Latch
Access
Bit
(DLAB)

*81t 0

the least significant bit. It

the first bit serially transmitted or received.

139

Bits 0 and 1: These two bits specify the number of
bits in each transmitted or received serial character.
The encoding of bits a and 1 is as follows:
Bit 1

Bit 0

Word Length

a
a

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2: This bit specifies the number of stop bits in
each transmitted or received serial character. If bit
2 is a logic 0, 1 Stop bit is generated or checked in
the transmit or receive data, respectively. If bit 2 is a
logic 1 when a 5-bit word length is selected via bits a
and 1, 1;', Stop bits are generated or checked. If bit 2
is a logic 1 when either a 6-,7-, or 8-bit word length is
selected, 2 Stop bits are generated or checked.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a
logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data word
bit and Stop bit of the serial data. (The Parity bit is
used to produce an even or odd number of 1s when
the data word bits and the Parity bit are summed.)
Bit 4: This bit is the Even Parity Select bit. When bit 3
is a logic 1 and bit 4 is a logic 0, an odd number of
logic 1s is transmitted or checked in the data word
bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a
logic 1, an even number of bits is transmitted or
checked.

Spacing (logic 0) state and remains there (until reset
by a low-lever bit 6) regardless of other transmitter
activity. This feature enables the CPU to alert a terminal in a computer communications system.
Bit7:This bit is the Divisor Latch Access Bit (DLAB).
It must be set high (logic 1) to access the Divisor
Latches of the Baud Rate Generator during a Read
or Write operation. It must be set low (logic 0) to
access the Receiver Buffer, the Transmitter Holding
Register, or the Interrupt Enable Register.

WD8250 Programmable Baud Rate Generator
The WD8250 contains a programmable Baud Rate
Generator that is capable of taking any clock input
(DC to 3.1 MHz) and dividing it by any divisor from 1
to (2'" - 1). The output frequency of the Baud Generator is 16x the Baud rate. Two 8-bit latches store the
divisor in a 16-bit binary format. These Divisor
Latches must be loaded during initialization in order
to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a
16-bit Baud counter is immediately loaded. This
prevents long counts on initial load.
Tables 3 and 4 illustrate the use of the Baud Generator with two different driving frequenCies. One is referenced to a 1.8432 MHz crystal. The other is a 3.072
MHz crystal.
NOTE
The maximum operating frequency of the
Baud Generator is 3.1 MHz. However, when
using divisors of 5 and below, the maximum
frequency is equal to the divisor in MHz. For
example, if the divisor is 1, then the maximum
frequency is 1 MHz. In no case should the data
rate be greater than 56K Baud.

Bit 5: This bit is the Stick Parity bit. When bit 3 is a
logic 1 and bit 5 is a logic 1, the Parity bit is transmitted and then detected by the receiver in the opposite
state indicated by bit 4.
Bit 6: This bit is the Set Break Control bit. When bit 6
is a logic 1, the serial output (SOUT) is forced to the

TaBle 4 Baud Rates Using 3.072 MHz Crystal.

Table 3 Baud Rates Using 1.8432 MHz Crystal.
Desired
Baud
Rate

Divisor Used
to Generate
16x Clock

Percent Error
Difference Between
Desired and Actual

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
NOTE: 1.8432 MHz

Desired
Baud
Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

0.026
0.058
-

069

2.86

the standard 8080 frequency divided by 10

140

Divisor Used
to Generate
16x Clock

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
3

Percent Error
Difference Between
Desired and Actual

0.026
0034
-

0.628

1.23
-

14.285

Line Status Register
This 8-bit register provides status information to the
CPU concerning the data transfer. The contents of
the Line Status Register are indicated in table 2 and
are described below.
Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete
incoming character has been received and transferred into the Receiver Buffer Register. Bit 0 may be
reset to a logic 0 either by the CPU reading the data
in the Receiver Buffer Register or by writing a logic 0
into it from the CPU.
Bitl: This bit is the Overrun Error (OE) indicator. Bit
1 indicates that data in the Receiver Buffer Register
was not read by the CPU before the next character
was transferred into the Receiver Buffer Register,
thereby destroying the previous character. The OE
indicator is reset whenever the CPU reads the contents of the Line Status Register.
Bit 2: This bit is the Parity Error (PE) indicator. Bit 2
indicates that the received data character does not
have the correct even or odd parity. as selected by
the even-parity-select bit. The PE bit is set to a logic
1 upon detection of a parity error and is reset to a
logic 0 whenever the CPU reads the contents of the
Line Status Register.
Bit3: This bit is the Framing Error (FE) indicator. Bit
3 indicates that the received character did not have a
valid Stop bit. Bit 3 is set to a logic 1 whenever the
Stop bit following the last data bit or parity bit is
detected as a zero bit (Spacing level).
Bit4:This bit is the Break Interrupt (BI) indicator. Bit
4 is set to a logic 1 whenever the received data input
is held in the Spacing (Logic 0) state for longer than
a full word transmission time (that is. the total time
of Start bit + data bits + Parity + Stop bits).
NOTE
Bits 1 through 4 are the error conditions that
produce a Receiver Line Status interrupt whenever any of the corresponding conditions are
detected.

Holding Register to the Transmitter Shift Register.
Bit 6 is a read-only bit.
Bit 7: This bit is permanently set to logic O.
Interrupt Identification Register
The WD8250 has an on chip interrupt capability that
allows for complete flexibility in interfacing to all
popular microprocessors presently available. In
order to provide minimum software overhead during data character transfers, the WD8250 prioritizes
interrupts into four levels. The four levels of interrupt conditions are as follows: Receiver Line Status
(priority 1); Received Data Ready (priority 2); Transmitter Holding Register Empty (priority 3); and
MODEM Status (priority 4).
Information indicating that a prioritized interrupt is
pending and source of that interrupt are stored in
the Interrupt Identification Register (refer to table
5). The Interrupt Identification Register (IIR), when
addressed during chip-select time, freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular
interrupt is serviced by the CPU. The contents of the
IIR are indicated in table 2 and are described below.
Bit 0: This bit can be used in either a hardwired
prioritized or polled environment to indicate
whether an interrupt is pending. When bit 0 is a logic
0, an interrupt is pending and the IIR contents may
be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is
pending and polling (if used) continues.
Bits 1 and 2: These two bits of the IIR are used to
identify the highest priority interrupt pending as
indicated in table 5.
Bits 3 through 7: These five bits of the II R are always
logic O.
Interrupt Enable Register

Bit 5: This bit is the Transmitter Holding Register
Empty (THRE) indicator. Bit 5 indicates that the
WD8250 is ready to accept a new character for
transmission. In addition, this bit causes the
WD8250 to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable
is set high. The THRE bit is set to a logic 1 when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The
bit is reset to logic Oconcurrently with the loading of
the Transmitter Holding Register by the CPU.

This 8-bit register enables the four interrupt sources
of the WD8250 to separately activate the chip Interrupt (I NTRPT) output signal. It is possible to totally
disable the interurpt system by resetting bits 0
through 3 of the Interrupt Enable Register. Similarly, by setting the appropriate bits of this register
to a logic 1, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt
Identification Register and the active (high) INTRPT
output from the chip. All other system functions
operate in their normal manner, including the setting of the Line Status and MODEM Status Registers. The contents of the. Interrupt Enable Register
are indicated in table 2 and are described below.

Bit6: This bit is the Transmitter Shift Register Empty
(TSRE) indicator. Bit 6 is set to a logic 1 whenever
the Transmitter Shift Register is idle. It is reset to
logic 0 upon a data transfer from the Transmitter

Bit 0: This bit enables the Received Data Available
Interrupt when set to logic 1. Bit 0 is reset to logic 0
upon completion of the associated interrupt service
routine.

141

Table 5

Interrupt Control Functions.

Interrupt Identification
Register
Bit 2

Bit 1

Bit 0

Interrupt Set and Reset Functions
Priority Interrupt
Level
Flag
-

None

Reading the
Line Status Register

Received
Data Available

Receiver
Data Available

Reading the
Receiver Buffer
Register

Transmitter
Holding Register
Empty

Reading the IIR
Register (if source
of interrupt) or
Writing into the
Transmitter Holding
Register

MODEM
Status

Clear to Send or
Data Set Ready or Reading the
Ring Indicator or
MODEM Status
Register
R ece i ved Li ne
Signal Detect

Highest Receiver
Line Status

Second

Third

Fourth

Interrupt
Reset Control

Overrun Error or
Parity Error or
Framing Error or
Break Interrupt

None

Interrupt
Source

Bit 1: This bit enables the Receiver Line Status Interrupt when set to logic 1. Bit 2 is reset to logic 0 upon
completion of the associated interrupt service
routine.
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1. Bit 3 is reset to logic 0 upon completion of the associated interrupt service routine.
Bits 4 through 7: These four bits are always logic O.
MODEM Control Register
This 8-bit register controls the interface with the
MODEM or data set (or a peripheral device emulating a MODEM). The content~ of the MODEM Control Register are indicated in table 2 and are
described below.
Bit 0: This bit controls the Data Terminal Ready
(DTR) output. When bit 0 is set to a logic 1, the DTR
output is forced to a logic O. When bit 0 is reset to a
logic 0, the DTR output is forced to a logic 1.
NOTE
The DTR output ofthe WD8250may be applied
to an EIA inverting line driver (such as the
DS1488) to obtain the proper'polarity input at
the succeeding MODEM or data set.

affects the OUT 1 output in a manner identical to
that described above for bit o.
Bit 3: This bit controls the Output 2 (OUT 2) signal,
which is an auxiliary user-designated output. Bit 3
affects the OUT 2 output in a manner identical to
that described above for bit O.
Bit 4: This bit provides a loopback feature for diagnostic testing of the WD8250. When bit 4 is set to
logic 1, the following occur: the transmitter Serial
Output (SOUT) is set to the Marking (logic 1) state;
the receiver Serial Input (SIN) is disconnected; the
output of the Transmitter Shift Register is "looped
back" into the Receiver Shift Register input; the four
MODEM Control inputs (CTS, DSR, RLSD, and AT)
are disconnected; and the four MODEM Control
outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four MODEM Control inputs.
In the diagnostic mode, data that is transmitted is
immediately received. This feature allows the processor to verify the transmit- and receive-data paths
of the WD8250.

Bit 1: This bit controls the Request to Send (RTS)
output. Bit 1 affects the RTS output in a manner
identical to that described above for bit o.

In the diagnostic mode, the receiver and transmitter
interrupts are fully operational. The MODEM Co.ntrol Interrupts are also operational but the interrupts' sources are now the lower four bits of the
MODEM Control Register instead of the four
MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.

Bit 2: This bit controls the Output 1 (OUT 1) signal,
which is an auxiliary 'user-designated output. Bit 2

The WD8250 interrupt system can be tested by writing into the lower six bits of the Line Status Register

142

and the lower four bits of the MODEM Status Register. Setting any of these bits to a logic 1 generates
the appropriate interrupt (if enabled). The resetting
of these interrupts is the same as in normal WD8250
operation. To return to this operation, the registers
must be reprogrammed for normal operation and
then bit 4 must be reset to logic O.
Bits 5 through 7: These bits are permanently set to
logic O.
MODEM Status Register

Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR input to the
chip has changed state since the last time it was
read by the CPU.
Bit 2: This bit is the Trailing Edge of Ring Indicator
(TERI) detector. Bit 2 indicates that the FIT input to
the chip has changed from an On (logic 1) to an Off
(logic 0) condition.
Bit 3: This bit is the Delta Received Line Signal
Detector (DRLSD) indicator. Bit 3 indicates that the
RLSD input to the chip has changed state.

This 8-bit register provides the current state of the
control lines from the MODEM (or peripheral
device) to the CPU. In addition to this current-state
information, four bits of the MODEM Status Register provide change information. These bits are set to
a logic 1 whenever a control input from the MODEM
changes state. They are reset to logic 0 whenever
the CPU reads the MODEM Status Register.

Bit 4: This bit is the complement of the Clear to Send
(CTS) input.

The contents of the MODEM Status Register are
indicated in table 2 and are described below.

Bit 5: This bit is the complement of the Data Set
Ready (DSR) input.

Bit 0: This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip
has changed state since the last time it was read by
the CPU.

Bit 6: This bit is the complement of the Ring Indicator CRT) input.

NOTE
Whenever bit 0, 1, 2, or 3 is set to logic 1, a
MODEM Status Interrupt is generated.

Bit 7: This bit is the complement of the Received
Line Signal Detect (RLSD) input.

Typical Applications
Figures 1 and 2 show how to use the WD8250 chip in an 8080A system and in a microcomputer system with
a high-capacity data bus.

~r~±:

I 1/
L _

OATI<.PORT

CONNECTOR

",-_v
DO.

1'~4-------C-""."1 OATA4

FIGURE 1 TYPICAL 8-BIT MICROPROCESSOR/RS·232 TERMINAL INTERFACE USING THE ACE.

143

~T.!LC~R~
IIS·212

8080A
MICROPROCESSOR

°7·°0

O-=-I

ALTERNATE

Typical Applicati0fls (continued)

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ...
O°C to +70°C
Storage Temperature -6SoC to +1S0°C (Ceramic)
-SO°C to +125°C (Plastic)
All Input or Output Voltages with
Respect to VSS .............. -0.5 V to +7.0 V
Power Dissipation .................... 750 mW
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended; operation
should be limited to those conditions specified
under DC Electrical Characteristics.

FIGURE 2 TYPICAL INTERFACE FOR A
HIGH-CAPACITY DATA BUS.
DC Electrical Characteristics

T A = 0° C to +70° C, VCC = +SV ± 5%, VSS = OV, unless otherwise specified.

Symbol

Parameter

VILX
VIHX
VIL
VIH
VOL
VOH
ICC(AV)

Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Avg Power Supply
Current (VCC)
Input Leakage
Clock Leakage

IlL
ICL

Min.

Typ.

-0.5
2.0
-O.S
2.0

Max.

Units

0.8

150

V
V
V
V
V
V
ma

±10
±1O

IlA
IlA

VCC
0.8
VCC
.45

2.4

Test Conditions

IIOL=1.6mA on all outputs
jlow-100 IlA

Capacitance
TA = 25°C, VCC = VSS = OV

Symbol

Typ.

Max.

Units

CXIN

Clock
Capacitance

Parameter

CIN

Input
Capacitance

COUT

Output
Capacitance

Test Conditions
fc=1 MHz
Unmeasured
pins returned
to VSS

Typical Supply Current va.
Temperature, Normalized

1.0t---

0.5
0

.25

r--

·50

AMBIENT TEMPERATURE ('C)

144

'75

AC Electrical Characteristic TA
Symbol
tAW
tAS
tAH
tcss
tOlD
tDIW
tRC
RC
too
tODD
tHZ
tDOD
tDOW
twc
WC

O°C to +70°C. VCC

+5V ± 5%

Parameter
Address Strobe Width
Address Setup Time
Address Hold Time
Chip Select Output Delay from Strobe
DISTR/DISTR Strobe Delay
DISTR/DISTR Strobe Width
Read Cycle Delay

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Read Cycie=tAW + tOlD + tDIW + tRC
DISTR/DISTR to Driver Disable Delay
Delay from DISTR/DISTR to Data
DISTR/DISTR to Floating Data Delay
DOSTR/DOSTR Strobe Delay
DOSTR/DOSTR Strobe Width
Write Cycle Delay

Write Cycie=tAW + tDOD + tDOW + twc
Data Setup Time
tDS
Data Hold Time
tDH
tcsc Chip Select Output Delay from Select
tDlC DISTR/DISTR Delay from Select
tDOC' DOSTR/DOSTR Delay from Select
'Applicable only when ADS input is not tied permanently low.
Symbol

Parameter

Baud Generator
N
Baud Rate Divisor
tBLO Baud Output Negative Edge Delay
tBHD Baud Output Positive Edge Delay
Baud Output Down Time
tLW
Baud Output Up Time
tHW
Receiver
tSCD Delay from RCLK to Sample Time
tSINT Delay from Stop to Set Interrupt
tRINT Delay from DISTR/DISTR (RD RBR) to Reset
Interrupt
Transmitter
Delay from DOSTR/DOSTR (WR THR) tn Reset
tHR
Interrupt
Delay from Initial INTR Reset to Transmit Start
tlRS
tSI
tss
tSTI

Min.

Max.

2 16-1
250 typ
250 typ

Delay from DISTR/DISTR (RD IIR) to Reset
Interrupt (THRE)
Modem Control
tMDO Delay from DOSTR/DOSTR (WR MCR) to Output
Delay to Set Interrupt from MODEM Input
tSIM
tRIM Delay to Reset Interrupt from DISTR/DISTR
(RD MSR)
TIR

145

Max

160
50
300
655
1000
200
300
60
20
175
685
1000
100
20
135
50
50

Units

Test
Conditions

lTTL Load
lTTL Load
1TTL Load
lTTL Load
lTTL Load
lTTL Load
lTTL Load
lTTL Load
lTTL Load
1TTL Load
lTTL Load
1TTL Load
1TTL Load
lTTL Load
lTTL Load
lTTL Load
lTTL Load
lTTL Load
1TTL Load
1TTL Load

Test
Conditions

ns
ns
ns
ns

100pF
100pF
100pF
100pF

.250

2 typ
2 typ
1 typ

/1S
/1S
/1S

100pF Load
100pF Load

.250

1 typ

/1S

100pF Load

16 typ

BAUDOUT
Cycles

24 typ

BAUDOUT
Cycles

.250

1 typ
8 typ

/1S
BAUDOUT
Cycles

.250

1 typ

/1s

100pF Load

.250
.250
.250

1 typ
1 typ
1 typ

/1S
/1S
IlS

100pF Load
100pF Load
100pF Load

425 Typ
330 Typ

Delay from Initial Write to Interrupt
Delay from Stop to Next Start
Delay from Stop to Interrupt (THRE)

Min
120
100
0

Load
Load
Load
Load

Vee

WD8250

EXTERNAL
CLOCK

osc CLOCK

BAUD GEN

LOGIC

OPTIONAL
CLOCK
OUTPUT

XTAL~
I-Timinl
tXH
tXl

'XL---j

Min
100
115

Units

EXTERNAL CLOCK INPUT (3.1 MHz MAX.)

WD8250

XTAL 1

DCrys!al

-;'

ose CLOCK TO

BAUD GEN

lOGIC

-;'

XTAl2

Crystal
3.1 MHz

A,
O.5M

O.5M

4O-60pF

o.Ot.uF

10030pF

TYPICAL CRYSTAL OSCILLATOR NETWORK

146

I--'AW----l ~-----------~

A5S~
AO.A •. A,.eso
es •. CS2
CSOUT

l~/

I- 'AS::j f-- 'AH
~,..-------------

I-- 'CSS-j

VALlD

>: -- -- -------

_J __ -' ___

t= 'Ise,~_: -'D-'W~-+--I-_-R~R-e~----l'1
1---1:

DISTR/DISTR

..Jxlr-A-eT-'V-E---X'-___--I: Il-I----~~

__________

DOSTR/OOSTR

-If-:=~

f---L'DD\ ,'DDj'DDD--! i-'HZ-j

ODIS

DATA

___ _

00-°7 -----------------<~

READ CYCLE TIMING

I-- 'AW ---j ~------------___j

A5S~
AO. A,. A,. eso

f--'AS-1

S~j

f-- 'AH

--v-::::;:-'V-------------

CS1.CS2~

eSOUT

f--'ess--j
_ _ _ _ --'\ ' __-___-__-___-___
-

I=--: 'ese---l

t----

+r------·1-

tooc---'

! - - - I D O O - i IOOW

IWC~

__________~x~__~x~I ____:::=====~
OR

DISTR/DISTR

_____________________

DATA

>--

I-'DS+'DH-1

00--°7

---------------«

VALID DATA

WRITE CYCLE TIMING

147

:I-:-----~

XTALl

BAUD OUT
(-7-1)

BAUD OUT
(-7-2)

BAUD OUT
[--;- 3)

BAUD OUT
(...;-. N. N >3)

--11'BLD-1I'BHDi~~LteyeLES

I-

·ltLwo2XTAl1CYCLES

BAUDOUT TIMING

RCLK

~j
I•

8eLKo-----=:j--J I-- 'seD

SAMPLECLK

SIN (RECEIVER
INPUT DATA)

SAMPLECLK

START

~ATABITS(5-81

~STARTr
~

_ ; . ._ _ _ _~

,I-t-I-~--'--'I--TI--rIJ~

-~~~~'

--j

'NTERRUPT

DISTR/DISTR'
(READ REC DATA
BUFFER)

I;='S'NT

---------------~!

--I

t-~

---------------t==

Noles:
'See Write Cycle Timmg
'See Read Cycle Timing

RECEIVER TIMING

148

~i~~AT~ OUT

PARITY

------\,STA_R.Ji'-__D_A_T_A_'5_-S_
1 _~TA_RT/...rj________

--l IIRS ~
~I

INTERRUPT (THRE)

DOSTRIDOSTR'
(WR THR)

DISTR/DISTR'
(AD IIR)

::::lI ISS!::=trJ:'-----__
t STI

jElHq

~~_ISI

:j ~IHR
~f\~____________~

_________________________

Notes:
'See Write Cycle Timing
-'See Read Cycle Timing

TRANSMITTER TIMING

DOSTA/DOSTR'
(WR MeR)

CTS, DSR, RLSO

INTR

D\STRiOISTR'
(RD MSR)

_'---JI.
--j 151M 1-

\'-------l

\ I 1\
1-= -i 'SIM I--

_______~r\RIM

~I--ISIM:j

r\~R_'M_:..I_______

----------~\
Notes:
'See Write Cycle Timing
'See Read Cycle Tunmg

MODEM CONTROLS TIMING

149

--j

l~---

'"O"J::::::

DO'

D::::::]

",. (::::::::0,::::::]

(lOI

•

WDB250 PLASTIC PACKAGE

WDB250 CERAMIC (HERMETIC)

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corpora·
tion reserves the right to change said circuitry at any time without notice.

';f'f~T~,!~ 1!'f3~Tl'~

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

150

WESTERN DIGITAL

o R A T / o N
we 2123 DEUCE
DUAL ENHANCED UNIVERSAL COMMUNICATIONS ELEMENT
'*

;,:
FEATURES

DIAGNOSTIC LOCAL LOOP-BACK MODE
~
e RXD INITIALIZATION UPON MASTER RESET
z
0

i'iTs1l

c-rs:B

RXRDY-B

TXE-B

BAKDET-B

+5V

28
INTRA

BAUD CLOCK A OUTPUT
BAUD CLOCK B OUTPUT

ADDRESS BUS

Figure 5 WD2123 MICROPROCESSOR APPLICATION

163

ABSOLUTE MAXIMUM RATINGS

V DO with respect to V ss ....... .

0.5V to +12V
... -0.5V to +7V
500Mw.

Voltage on Any Pin with Respect to Ground
Power Dissipation

........... .

STORAGE TEMPERATURE:
Ceramic: -65'C to + 150'C
Plastic: -55'C to + 125'C

Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under dc electrical characteristics.

DC ELECTRICAL CHARACTERISTICS
~

DoC to + 70'C; V ee

SYMBOL

5.0V ±5%; GND

PARAMETER

MIN

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

IDL

Data Bus Leakage
(High Impedance State)

IlL

Input Leakage

TYP

UNIT

0.8

Vee

0.45

IOL

1.6 mA

IOH

-100 uA

-50
10

uA
uA

VOUT ~ 0.45V
VOUT ~ Vee

VIN ~ Vee

Vee - 5.25V
No Load

MAX

UNIT

TEST CONDITIONS

2.4

Power Supply Current

lee

MAX

100

TEST CONDITIONS

Table 7 WD2123 D.C. PARAMETERS
CAPACITANCE
TA

25'C; Vee

SYMBOL

GND

PARAMETER

TYP

MIN

CIN

Input Capacitance

GIIO

1/0 Capacitance

Unmeasured pins
returned to
GND.

Table 8 WD2123 CAPACITANCE LEVELS

164

1MHz

\C ELECTRICAL CHARACTERISTICS

rA = O°C to + 70C; Vee = 5.0V 0:5%; GND = OV
SYMBOL

PARAMETER

MIN

MAX

UNITS

CONDITIONS

BUS PARAMETERS
Read Cycle
tAR

Address Stable Before READ (CS,C/D)

tRA

Address Hold Time for READ (CS,C/D)

tRE

READ Pulse Width

350

tRO

Data Delay from READ

200

CL = 50 pF

tROH

READ to Data Floating

200

CL = 50pF

CL=15pF

Write Cycle

tAW

Address Stable Before WRITE

tWA

Address Hold Time for WRITE

tWE

WRITE Pulse Width

350

tos

Data Set-Up Time for WRITE

100

tWOH

Data Hold Time for WRITE

100

tTxe

Transmit Clock Period

1.6

tOTX

TxD Delay from Falling Edge of TxC

tSRX

Rx Data Set-Up Time to Sampling Pulse

tHRX
fTX

OTHER TIMINGS

tTPW

tTPO

CL = 100 pF

200

CL = 100 pF

Rx Data Hold Time to Sampling Pu Ise

100

CL = 100 pF

Transmitter Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate

DC
DC

kHz
kHz

CL = 100 pF

Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

1.0
BOO

us
ns

Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

1.0
BOO

us
ns

200

500
600

Table 9 WD2123 A.C. PARAMETERS

165

SYMBOL

fRX

tRPW

tRPD

MIN

MAX

UNIT

Receiver Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate

DC
DC

500
600

kHz
kHz

Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

1.0
800

us
ns

Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

1.0
800

us
ns

PARAMETER

TEST
CONDITION

tTX

TxRDY Delay from Center of Stop Bit

tRX

RxRDY Delay from Center of Stop Bit

tiS

Internal BRKDET Delay from Center
of Data Bit

tTRD

tTaD

twc

tCR

tRXC
tRXC

RXC

TxRDY Delay from Falling Edge of
WRITE

450

TXD Output from Falling Edge of
WRITE

1V,

tTXC

Control Delay from Rising Edge of
WRITE (RTS)

200

Control to READ Set-Up Time (CTS)

tTXC

Table 9 WD2123 A.C. PARAMETERS

________________-J~~:_::____________~__

:_::~~~

:A_AC_C___________

Figure 6 A.C. TEST POINTS

166

_____________

50pF (16X)

DATA BUS

CS,

Figure 7 WD2123 READ TIMING

DATA BUS

CS,

Figure 8 WD2123 WRITE TIMING

-J

RTS

VHAC
__________________________________/Ir~-~V~l~A~C-----------------

t------

I
teR

Figure 9 WD2123 INTERFACE CONTROL TIMING

167

TXC (1

x CLOCK)

TXC (16

x CLOCK)

V,L

16 TXC PERIODS

TXD

Figure 10 WD2123 TRANSMITTER CLOCK AND DATA TIMING

RXD

RXC (1 x CLOCK)

STAAT BIT

RXD

1st DATA BIT

AXC (16 x CLOCK)

INTERNAL
SAMPLING PULSE

__________

~nL

_____________________

Figure 11 WD2123 RECEIVER CLOCK AND DATA TIMINGS

168

TXC

C$. ciD

TXRDY

TXD

r-------------~~~~------------~

DATA

Figure 12 WD2123 TRANSMITTER OUTPUT TIMINGS WITH RESPECT TO TRANSMIT CLOCK

!
RXD----,'--=ST~A_R_T
BIT

~~~~-------------L~~----~

___ k________ DA~ BITS

RXADY

RE------------------------------------------------------------~

Figure 13 WD2123 RXRDY TIMING

TXE,

fL-

TXRDY~L-----l
'n

VLAC

~~----uTXD

-----------,'-I-'~:...~:..A_RT____'___________D..."A{t BITS

1st DATA BYTE

PARITY

BIT

STOP
BITS

I ~~ART C

---+j+---,.I.I r
2nd DATA

BYTE

Figure 14 WD2123 TXRDY TIMING

169

".1::::0:::]
WD2123A CERAMIC PACKAGE

WD2123B PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is

completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no rosponsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may resuh from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

170

WESTERN DIGITAL
CORP

WD1993
ARINC 429 RECEIVER/TRANSMITTER
AND

MULTI-CHARACTER RECEIVER/TRANSMITTER
FEATURES

.. SINGLE +5 VOLT SUPPLY

• PRESENT UPON MASTER RESET FOR ARINC 429
PROTOCOL

• 28 PIN CERAMIC OR PLASTIC PACKAGE
o TEMPERATURE RANGES O'C to 70'C,
- 40'C to + 85'C, or - 55'C to + 125'C

o PROGRAMMABLE WORD LENGTH FROM 1 CHARACTER TO 8 CHARACTERS

INTRODUCTION

• PROGRAMMABLE CHARACTER LENGTH, 5, 6, 7, OR
8 BITS

The Western Digital WD1993 Avionic Receiver/Transmitter
is designed to handle digital data transmission, according to
the Avionic Arinc 429 protocol. Also, the word length is programmable from one to eight characters of 5, 6, 7, or 8 bits.
Parallel data is converted into a serial data stream during
transmission and serial to parallel during reception. The
WD1993 is packaged in a 28 pin plastic or ceramic package
and is available in three temperature ranges: Commercial,
Industrial and Military .

.. RETURN TO ZERO (RZ) OUTPUT
.. AUTO SPACE GENERATION
• DOUBLE BUFFERED RECEIVER AND TRANSMITTER
.. UNDERRUN ERROR DETECTION FOR TRANSMISSION
.. OVERRUN, FRAMING AND PARITY ERROR DETECTION ON RECEIVER

GENERAL DESCRIPTION
The WD1993 is a bus-orientated MOS/LSI device designed
to provide the Avionics Arinc 429 Data Communication Protocol, along with programmable character length capabilities.

.. WORD ERROR FLAG FOR COMPREHENSIVE ERROR
REPORTING
.. FIRST CHARACTER OF WORD FLAG FOR SINGLE INTERRUPT APPLICATIONS

Also, the WD1993 contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (LTE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low. The status and output flags operate normally.

.. DIAGNOSTIC LOCAL LOOP-BACK TEST MODE
• DC TO 200 KILOBITS PER SECOND OPERATION
• TTL COMPATIBLE INPUTS AND OUTPUTS

V55

WE'

ci1i

CTs

TXC

w£

N.C.

D7
D6
D5
D4
D3
D2
D1
DO

AXOl

vcc
"'AD,W""E

Figure 1 PIN DIAGRAM
Figure 2 WD1993 BLOCK DIAGRAM

171

PIN NO.

SYMBOL

FUNCTION

SIGNAL NAME

VSS

GROUND

Ground

VCC

POWER SUPPLY

+5V DC

CHIP SELECT

C/O

CONTROUDATA

READ ENABLE

When aclive (Vld, Ihe device is selecled. This enables
communicalion between the WD1993 and a microprocessor.
This inpul is used in conjunction with an active read or
write operation to determine register access via the DATA
BUS.
When active (V Id, allows the CPU 10 read data or status
information from the WD1993.

WRITE ENABLE

When active (V IL), allows the CPU to write into the selected register.

MASTER RESET

When active (V IH), presets the WD1993 mode and command registers to the ARINC protocol. Master Reset also
resets the data registers and places the WD1993 transmitter and receiver into idle states. After MR, the command
register is sel to 00100101 and the mode register is set to
00111100.

TXC

TRANSMIT CLOCK

This input is the source clock for transmission. The data
rate is a function of this clock frequency.
ARINC MODE ~ 4 x bit rate

RXC

RECEIVE CLOCK

This input is the source clock for reception. The data rate
characteristics are the same as the transmit clock.

CTS

CLEAR-TO-SEND

This input is activated (V I L) to enable the transmitter
logic.

RXD1

RECEIVE DATA ONE

The RXD1 input is driven by the VIZ line receiver. Each
time the VIZ circuit detects a logic one, a TTL level logic
one (active for one-half bit time) is provided to this input.

RXDO

RECEIVE DATA ZERO

RXDO is driven by the line VIZ receiver circuil. When the
VIZ circuit detects a logic zero, a TTL logic one (active for
one-half bit time) is provided to the WD1993.

TXD1

TRANSMIT DATA
ONE

This output drives the VIZ circuit when a logic one is to be
transmitted and is active for one-half bit time.

TXDO

TRANSMIT DATA
ZERO

This output drives the VIZ circuit when a logic zero is to be
transmitted and is active for one-half bit time.

172

PIN NO.

SYMBOL

SIGNAL NAME

FUNCTION

TXE

TRANSMITTER
EMPTY

This output goes high to indicate the end of a transmit operation. TXE is automatically reset after the Transmit Holding Register is loaded.

RXRDY

RECEIVER READY

This output, when high, alerts the CPU that the Receiver
Holding Register contains a data character that is ready
to be input. This output is automatically reset whenever a
character is read from the WD1993. RXRDY is enabled
unless inhibited by setting command bit CR3 (RXRDYIN)
to a logic "1". It is automatically enabled again after a receive sequence is completed.

TXRDY

TRANSMITTER
READY

This output, when high, alerts the CPU that the Transmit
Hold ing Register is ready to accept a data character. The
TXRDY output is automatically reset whenever a character
is written into the WD1993 and can be used as an interrupt
to the system.

FCR

FIRST CHARACTER
READY

This output goes high after the receiver has completed reception of the first character in a multi-character sequence.

WEF

WORD ERROR
FLAG

This pin is an output, which when active indicates an error
in either the transmitter or receiver has been detected. It reflects an underun, overrun, parity or framing (receive word)
error and is intended as an error interrupt. The Status Register should be read to determine the specific error.

DO
D1
D2
D3
D4
D5
D6
D7

DATA BUS

This is the bi-directional data bus. It is the means of communication between the WD1993 and the CPU. Control,
Mode, Data and Status Registers are accessed via this bus.

17
18
19
20
21
22
23
24
5

No Internal Connecticn

N.C.

173

ORGANIZATION
A block diagram of the WD1993 is shown in figure 2.
As mentioned, the WD1993 is an eight bit bus-oriented
device. Communication between the WD1993 and the controlling CPU occurs via the a bit data bus through the bus
transceivers. There are 2 accessible data registers, which
buffer transmit and receive data. They are the Transmit Holding Register and the Receive Holding Register. There is a
parallel-to-serial shift register (parallel in-serial out), the
transmit register and a serial-to-parallel shift register (serial
in-parallel out), the receive register.
Operational control and monitoring of the WD1993 is performed by two control registers (the command instruction
register and the mode instruction register) and the status
register.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the control, status or holding
registers by activating the appropriate control lines: Chip Select (CS), Read En~ble (RE), Write Enable (WE),and Control
or Data Select (C/D).
Internal control of the WD1993 is by means of two internal
microcontrollers; one for transmit and one for receive. The

control registers, null detect logic and various counters,
provide inputs to the microcontrollers which generate the
necessary control signals to send and receive serial data according to the Arinc 429-1 protocol, along with the programmable multicharacter capabilities.

OPERATION
Upon master reset (MR), the device is programmed to transmit and receive four a-bit contiguous characters with the
32nd bit odd parity. (ARINC protocol.)
A minimum four bit time space is automatically inserted after
the character transmission. Two receiver inputs, RXD1/RXDO
and two transmitter outputs, TXD1/TXDO, are provided to interface with voltage-impedance (VIZ) circuits to translate
± 10 volt ARINC line levels to 5 volt TTL logic levels. The
transmit clock (TXC) and receive clock (RXC), in ARINC
mode, are four times (4X) the bit rate desired.
The receiver monitors the received data input to detect a four
bit time nUll, which delimits the word. If the communications
link is broken during a word reception, the receiver will generate a word error flag to (WEF) to notify the CPU to request
retransmission. When a null is detected, the receiver logic is
reset and returned to an idle state awaiting the next word.

The WD1993 may also be programmed to support a multiple
character word consisting of from one to eight characters.
Also, the character length is programmable from 5 to a bits,
and the parity bit if parity is used, may be either inside or outside the word.
The Command Register is used to select features such as
parity options, loop test capability, RXRDY flag enabling,
transmitter and receiver enabling, and may also cause the
WD1993 to return to the Mode instruction.
The Mode Register is used to select features such as bitsl
character and characters/word.
The Status Register contains information such as Transmitter Ready, Transmitter Empty, Receiver Ready, error conditions, and First Character Ready.

OPERATING DESCRIPTION
The WD1993 is primarily designed to operate in an 8 bit
micro-processor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, RE, WE and C/D) should be
connected to the microprocessor's data bus and system control bus.
The appropriate TXC and RXC clock frequencies should be
selected for the particular application, using a programmable
baud rate generator such as a BR1941. A masterreset pulse
initializes the WD1993 and presets the control registers to
the ARINC protocol.
The RXD1/RXDO inputs are interfaced to the DITS data line
via external level translators that provide TTL (5V) logic levels to the WD1993. The TXD1/TXDO outputs are connected
to high voltage (± 10V) driver circuits. Figures 16 and 17
show some typical ± 10V translator and driver circuits.
The TXRDY, RXRDY, FCR and WEF Flags may be connected to the microprocessor system as interrupt inputs. The
status register can be period ically read in a polled environment to support WD1993 operations.
The CTS input can be used to synchronize the transmitter to
external events.
The WD1993 is designed such that a control register write
operation accesses the command instruction register.
The RXRDYIN bit of the command register is used to inhibit
the RXRDY output pin for ARINC operations.

174

MULTI-CHARACTER OPERATIONS

As discussed above, the WD1993 is equipped with a multicharacter option which provides the user with the means of
transmitting and receiving multiple contiguous characters
of data within one set of delimiters-4 bit nulls for ARINC
429. Since the WD1993 is an 8 bit bus-oriented device, the
controlling processor must read the WD1993 data from its
holding register before the subsequent characters are assembled. This situation also exists on the transmit side, i.e.,
the Transmit Holding Register must be loaded before the
previous 8 bits are completely shifted out of the transmit
register.
Several "flags" are provided for interrupt purposes so that
continuity is maintained and data integrity is preserved.
These flags are First Character Ready (FCR), Receiver Ready
(RXRDY), Transmitter Ready (TXRDY) and Transmitter
Empty (TXE).

e) The data is loaded into the transmit register and TXRDY
goes high. This indicates the first data word is being
sent and a character can be loaded into the holding
register. If the WD1993 is programmed for more than
one character (multi-character) then an underrun error
will be generated if the next character is not loaded before the previous word is completely shifted out, unless
the current character is the last character in a sequence.
f) If the last character is transmitted and no more new
data is to be sent, the transmitter will indicate its status
by raising the TXE flag. (No error is generated as a result of this condition.)
The Receiver operates similarly:
a) With the control registers suitably programmed, the receiver is enabled, REN (CR2) = "1 ".
b) The RXRDY and FCR flags are "0". (Inactive).

The Transmitter operates as follows:
a) With the mode and command registers programmed
as desired, the transmitter is enabled, TEN (CRO)
"1 ".

b) The TXE and TXRDY flags are "1" (active).
c) The external CTS signal

= "0".

d) The CPU loads data into the Transmitter Holding Register, TXE and TXRDY go Low.

175

c) The incoming data word activates the receive logic and
the data begins to be assembled in the receive register.
d) When the first character is completely assembled, the
data is loaded into the Receive Holding Register, the
FCR (First Character Ready) and RXRDY (Receiver
Ready) flags become active, "1". The CPU should
read the data prior to the reception of the next character or an overrun error will be generated as the receiver
will overwrite the old data with the new data character
just received.

The exception to this is in the ARINC mode, where the
first character in the ARINC protocol contains a label.
The FCR and RXRDY Flags become active to indicate
the reception of the first character of data. The CPU
reads the first character and decides whether or not it
wants to acquire the subsequent characters. If not,
then the CPU performs a "control write" to the COMMAND REGISTER, setting the RXRDYIN (CR3) bit to
a "1 ". This bit in ARINC mode, inhibits the RXRDY flag
from interrupting the CPU during the reception of the 3
remaining characters. The RXRDYIN bit is then automatically reset upon completion of the receive sequence and RXRDY is enabled again.

Airlines Electronic Engineering Committee April 11 ,1978. By
the adoption of this specification the foundation is set for a
standard protocol governing all intersystems equipment (Line
Replaceable Units).
MARK 33 DIGITAL INFORMATION TRANSFER
SYSTEM (DITS)
Basic Philosophy
Transmit from a deSignated output port over a single
twisted and shielded pair of wires to designated receiver.
Bidirectional data flow not permitted on a given pair.
Data Transfer
Numeric
Iso Alphabet # 5
Graphic

LOOP TEST MODE
As mentioned, the WD1993 is equipped with a diagnostic
test mode, local loop-back. This mode is activated by setting
the LTE command billo a "1". The TEN and REN bits should
be "1" and CTS should be "VIL". The receiver inputs are ignored and the transmitter outputs are sending nulls. The
transmitter is internally "looped-back" to the receiver and the
error and status flags operate normally.

Data Format
32 bits or less (unused bit positions should be filled with
binary zeros or valid data pad bits).
Bit #32 is assigned to parity.
Modulation
Return to Zero (RZ)

For basic testing, failing to reload the Transmit Holding Register in the middle of a data send sequence will cause an underrun error in the transmitter and a word error in the receiver. Failure to read the Receive Holding Register after a
FCR or RXRDY flag will cause an overrun error to be
generated.

Transmit Voltage Levels
high
+10
null
0
low
-10

±0.5V
±0.5V
±0.5V

Receiver Voltage Lellels:
(noisy
(in abse'lce
of noise)
environment)
high +6.0V to + lOV
+5.0V to + 13V
-5.0V to -13V
-6.0V to +10V
low
No damage to receiver up to 20 vac rms between A &
B; +28, A to Gnd; -28, B to Gnd.

For Loop-Back test operations, the user should be sure that
the TXC and RXC clock frequencies are the same. This is
normally implemented by placing the same clock signal on
both pins (TXC and RXC).
ARINC BACKGROUND

Data Rate
100 kilo bit per second ± 1%
Low speed 12 to 14.5 kilo bit per second ± 1%
Word Synchronization
All zero gap of a minimum of 4 bit times

Aeronautical Radio Inc. (ARINC) publishes the ARINC 429
speCification. This document defines the air transport industries standards for the transfer of digital data between avionics systems elements. This specification was adopted by The

176

The format and definition of the Command Register is shown below:

CR2

EPS

PEN

LTE

TEN

RXRDYIN

REN

PIA

TEN

Transmit ENable

1
0

Enabled
Disabled

PIA

Parity Inside or After
After the data word
Inside (the last data bit) of word

0
REN

Receive ENable

1
0

Enabled
Disabled

RXRDYIN

RXRDY Inhibit
Inhibit RXRDY output flag

Normal transmitter ODe ration
enable RXRDY output flag

LTE

Loop Test ENable

1
0

Local loop-back mode
Normal Operation

PEN

Parity ENable

1
0

Enabled
Disabled

Internal Reset

1
0

Returns WD1993 to mode instruction
format

-----

EPS

Even Parity Select

1
0

Even parity
Odd parity

177

The format and definition of the Mode Register is shown below:

MR7

MR6

MR5

MR4

MR3

MR2

MR1

CLS2

CLS1

MRO

CLS2

g,g

0
0
1
1

0
1
0
1

Characters Per Word Select

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
8 characters

Character Length Select
5 bits
6 bits
7 bits
8 bits

The WD1993 registers are addressed according to the following table:

L
H
X

C/O

L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

H
L
H
L
X

~
~

Registers Selected
Read Receive Holding Register
Write Transmit Holding Register
Read Status Register
Write Control Registers
Data Bus Tri-Stated

VILatpins
VIH at pins
don't care

178

The format of the Status Register is shown below:

SR?

SR6

SR5

SR4

SR3

SR2

FeR

WEF

TXE

TXRDY
1

SR1

RXRDY

SRO
TXRDY

Transmitter Ready
Active (THR can be reloaded)
Inactive (transmitter is busy)
Receiver Ready
Active (RHR should be read)

Inactive

TXE

Transmitter Empty

Transmitter idle
Transmitter active

o
PE

Parity Error

Error reported
No error

Overrun Error

o
WEF

RHR has been overwritten
No error
Word Error Flag
Indicates improper receive sequence (word error),
overrun error, parity error or underrun error.

o
FCR

No error
First Character Ready
This bit indicates the receiver has just completed assembly of the 1st character in a multi-character sequence and that the data is contained in the RHR.

o
UE

First character not ready.

Underrun Error
Indicates that the THR has not been loaded with a new
character in time for a contiguous data transmission
sequence.
No error

179

ABSOLUTE MAXIMUM RATINGS
Storage Temperature

-55'C to + 125'C (Plastic Package)
-65'C to +150'C (Ceramic Package)

Voltage on any Pin with Respect to Ground .. -0.3V to + 7V
. . 400 MW
Power Dissipation . .
Note:

Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended and should
be limited to those conditions specified under DC
Electrical Characteristics.

DC ELECTRICAL CHARACTERISTICS
TA~

O'Cto +70'C; VCC

SYMBOL

5.0V '" 5%;GND

PARAMETER

MIN

VIL

Input Low Voltage

-0.3

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

IlL

Input Leakage
Power Supply Current

TEST CONDITIONS

0.8

V
V

10L ~ 1.6mA

Data Bus Leakage

ICC

UNIT

VCC
0.45

V
V

10H ~ -100!,A

Data Bus is in
High Impedence
State

2.4

Output High Voltage

IDL

MAX

TYP

VIN ~ VCC
Vee ~ 5.25V
No Load

CAPACITANCE
TA

25'C; Vee

SYMBOL

GND

OV
MIN

PARAMETER

TYP

MAX

UNIT

TEST CONDITIONS

CIN

Input Capacitance

C'iO

I/O Capacitance

Unmeasured pins

lMHz

returned to GND

+20

"'-S>-

+10

<{
...J

0
f--

::J
D-

f--

::J

-10

--1

-20
-100

V
-50

SPEC.

+50

+100

tl CAPACITANCE (pF)

Figure 3 OUTPUT DELAY vs CAPACITANCE

180

A.C. TIMING PARAMETERS
SYMBOL

PARAMETER

MIN

MAX

UNIT

TEST CONDITIONS

BUS PARAMETERS
Read Cycle

(Reference Figure 6)

tAR

Address Stable before RE, (CS, C/D)

tRA

tRE

Address Hold Time for RE, (CS, C/D)
RE Pulse Width

tRD

Data Delay from RE

tRDH

RE to Data Floating

WRITE CYCLE

350

ns
200

C L = 50pF

200

CL = 50pF

CL=15pF

(Reference Figure 7)

tAW

Address Stable before WE

tWA

Address Hold Time for WE

tWE

WE Pulse Width

350

tDS

Data Set·Up Time for WE

200

tWDH

Data Hold Time for WE

OTHER TIMINGS

(Reference Figures S, 9)

tOTX

TXD Delay from Falling Edge of TXC

tSRX

Rx Data Set·up Time to Sampl ing Pulse

200

CL = 100pF

tNRX

Rx Data Hold Time to Sampling Pulse

100

CL=100pF

tTX

Transmitter Input Clock Frequency

tTPW

tTPD

tRX

tRPW

tRPD

500

1 x Baud Rate

500

kHz

4x. 16x Baud Rate

750

kHz

CL = 100pF

Transmitter Input Clock Pulse Width
1 x Baud Rate

1.0

16 x Baud Rate

500

1 x Baud Rate

1.0

16x Baud Rate

500

Transmitter Input Clock Pulse Delay

Receiver Input Clock Frequency
1 x Baud Rate

500

kHz

4x, 16x Baud Rate

750

kHz

Receiver Input Clock Pu Ise Width
1 x Baud Rate

1.0

16x Baud Rate

500

1 x Baud Rate

1.0

16x Baud Rate

500

Receiver Input Clock Pulse Delay

ns
tTX

TXRDY Delay from center of Data Bit

181

tTXC

(Ix or 16x)

A.C. TIMING PARAMETERS

SYMBOL

PARAMETER

MIN

MAX

UNIT

tTX

TXRDY Delay from Center of Data Bit

tTXC

tAX

RXRDY Delay from Center of Data Bit (FCR
Delay from Center of Data Bit)

RAXC

TXE Delay from Center of Data Bit

tTXC

200ns

_______:_:_~~~~~H_~_:________________~~~_________
Figure 4 TEST POINTS FOR A.C. TIMING

DATA
BUS

cs c/o

Figure 5 READ CYCLE TIMING

Note: AC timings measured at VOH

= 2.0V,

VOL

= 0.8V

DATA
BUS

Figure 6 WRITE CYCLE TIMING

182

and with test load circuil.

TEST CONDITION
(4x)

CL = 50 pF
(1 x Rate)

TXC
(1 x baud)
k-------~

- - - - 16 TXC periods

-------------l'>-j

TXC
(16 x baud)

~l-----

TXC
(4 x

"'I

4 TXC periods

----------1--;..,

b~Ud)l----------'r-

-T-X-D--~------~

\L-__

Figure 7 TRANSMITTER CLOCK AND DATA TIMINGS

-----4~-----tHRX

RXD

RXC

~-----tRPw-----~.~I'l------tRPD------4~~1
I

(1 x baud)

~-----------4

RXC periods -----------~

RXC
(4 x baud)

-----16

RXC periods - - - -

RXC
(16 x baud)

Figure 8 RECEIVER CLOCK AND DATA TIMINGS

183

TXC
(4

CS, C7B

TXADY - - - - - - ,

TIE _ _ _ _ _ _ _ _ _ _---,

TX01

--------------------f

TXDO

---------------------t---------;
Figure 9 TRANSMITTER TIMINGS (ARINC MODE)

RXD1,D
(Anne)

1st Data Character

null

4th Data Character

3rd Data Character

2nd Data Character

null

n
n

nXRDY

IL
U

Figure 10 RXRDY AND FCR TIMING

TXE~

~----------------------------------------------------------~

TXROY

~'-----_ _ _ __ _ ' n L_ _ _ __ _ ' n L_ _ _ _~

u
TXDt
1st Data Character

2nd Data Character

3rd Data Character

4th Data Character

NULL

Figure 11 TXRDY AND TXE TIMINGS (4 Character Sequence)

184

character with 4 bLt 1l111llmum spilce
01 last char,lcter 1$ pJrLty

~one trill1smlS5Lon reception conSists of four clgllt bLl ch,lfilcter ilild 4 bL\ (min I null
o1bLlSPiKeifluilii
Delll11lter

-,--.--,----1~

pa~ltY

~"ljDl D2 D3D'I~~2131~~16171±_I'o~'~!±'I26I~913Q~I£k_:;j .12131,1,

Elld 01 prevIous

4 bLI null tallowed
by nexl ctl------<.--+-+--...J'./V'--<~./V----__.

...._ RXDI

>---<~--

15K

LM3190
OR EOUIV

lOOK

SOD!!

15K

03
>'--<~---

__ RXDO

LOW

LF356

OR EOUIV

330K

47
,d

12V
01
"I

Note

1 01
2 All

IN4001

caps 35V

Figure 15 ARINC 429 LINE LEVEL TRANSLATOR (RECEIVER)

• 5V

47K

lOOK

50K

47K

lOOK

51!1
HIGH

TXDI

lOOK

OR EOUIV

LHOD02C

OR EQUIV
12V

lOOK

51!!

TXDO

:>-'--....--""""'-___-{>

!>___--_ _-"IV''-_ _.....-I
lOOK

- 12V

Figure 16 ARINC 429-1 LINE DRIVER

186

LOW

1~.575

620

WD1993E CERAMIC PACKAGE

WD1993F PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is
completed.
Informatkm fumished by Western Digital Corporation is believed to be accurate and reliable. However. no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
Ik:ense is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said drcuitry at anytime without notice.

WESTERN DIGITAL
CORPORArlON

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

187

188

WESTERN DIGITAL
c

WD1984 MULTI-CHARACTER
SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
FEATURES
o TWO OPERATING MODES: SYNCHRONOUS & ASYNCHRONOUS
• 1 TO 8 CHARACTERS OF 5,6,7, OR 8 BITS PER CHARACTER TRANSMISSION
It

SELECTABLE PARITY INSERTION IN OR AFTER LAST
BIT OF WORD

EVEN/ODD PARITY SELECT OR NO PARITY

.. DOUBLE BUFFERED RECEIVER & TRANSMITTER
.. ASYNCHRONOUS SELECTABLE CLOCK RATES (lx,16x)
.. UNDERRUN ERROR DETECTION FOR TRANSMISSION
.. OVERRUN, FRAMING AND PARITY ERROR DETECTION ON RECEIVER
.. LINE BREAK GENERATION AND DETECTION (ASYNC
MODE)
.. FIRST CHARACTER OF WORD FLAG FOR SINGLE INTERRUPT APPLICATIONS

o DIAGNOSTIC LOCAL LOOP-BACK TEST MODE

co
~

o DC TO 1M BITS/SEC (lx) OPERATION

:i
u
a:

o TTL COMPATIBLE INPUTS AND OUTPUTS

o SINGLE +5 VOLT SUPPLY
o 28 PIN CERAMIC OR PLASTIC PACKAGE

INTRODUCTION
The Western Digital WD1984 is designed to handle digital
data transmission, according to two protocols. These are the
Synchronous and Asynchronous protocols. Parallel data is
converted into a serial data stream during transmission and
serial to parallel during reception .
The device can be programmed to transmit and receive
words that are 1 to 8 characters in length; 5, 6, 7 or 8 bits
per character. Error flags and control signals have been
provided to broaden the application range of the device. The
WD1984 is packaged in a 28 pin plastic or ceramic package
and is available in two temperature ranges: Commercial and
Industrial.

FiE

VSS

c75

BDETISDET
CTS

TXC

N.C.

TXE

AXRDY

TXADY

N.C.

TXO

Axe

FCRfTIP

AXO

N.C.

vee

READlWRITE
CONTRO~

Figure 1 WD1984 PIN-OUT
N.C. No Internal Connection

Figure 2 WDl984 BLOCK DIAGRAM

t¥@§IWWP

189

PIN NO.

SYMBOL

SIGNAL NAME

FUNCTION

VSS

GROUND

Ground

BDETI
SDET

BREAK DETECTI
SYNC DETECT

This pin is a bi·directional port.
In ASYNC. it is an output. which goes high when the receiver
logic detects a break character.
In the SYNC mode, it is an input which causes the receiver to
begin assembling data bytes as programmed.

CTS

CLEAR· TO·SEND

This input is activated (Vld to enable the transmitter logic.

TXC

TRANSMIT CLOCK

This input is the source clock for transmission. The data rate
is a function of this clock frequency.
ASYNC MODE ~ 1 x or 16x bit rate
SYNC MODE ~ 16x bit rate

N.C.

MASTER RESET

When high (V IH), presets the WD1984. The command register
is set to 00100101 and the mode register is set to 00111100.

TXE

TRANSMITTER
EMPTY

This output goes high to indicate the end of a transmit operation. TXE is automatically reset after the Transmit Holding
Register is loaded.

RXRDY

RECEIVER READY

TXRDY

TRANSMITTER
READY

This output, when high, alerts the CPU that the Transmit Holding Register is ready to accept a data character. The TXRDY
output is automatically reset whenever a character is written
into the WD1984 and can be used as an interrupt to the
system.

No internal connection.

190

PIN NO.

SYMBOL

SIGNAL NAME

FUNCTION

N.C.

TXD

TRANSMIT DATA
ONE

This output is the serial data output.

RXC

RECEIVE CLOCK

This input is the source clock for reception. The data rate characteristics are the same as the transmit clock.

FCRlTIP

FIRST CHARACTER
READY/TRANSMISSION IN
PROGRESS

In the ASYNC mode. this output goes high after the receiver
has completed reception of the first character in a multi-character sequence.

N.C.

VCC

POWER SUPPLY

+5V DC

RXD

RECEIVE DATA ONE

This input is the serial data input.

17
18
19
20
21
22
23
24

DO
01
02
03
04
05
06
07

DATA BUS

This is the bi-directional data bus. It is the means of communication between the WD1984 and the CPU. Control, Mode,
Data and Status Registers are accessed via this bus.

WRITE ENABLE

When low (V Id, allows the CPU to write into the selected
register.

CHIP SELECT

When low (V I d, the device is selected. This enables communication between the WD1984 and a microprocessor.

C/D

CONTROL/DATA

This input is used in conjunction with an active read or write
operation to determine register access via the DATA BUS.

READ ENABLE

When low (V Id, allows the CPU to read data or status information from the WD1984.

191

GENERAL DESCRIPTION

The WD1984 is a bus-oriented MOS/LSI device designed to
provide two data communication protocols:
1. Asynchronous
2. Synchronous
The control registers are used to select the desired protocol
and provide programmable format options within each protocol, as outlined below.
The WD1984 contains two control registers needed to specify formal options within each protocol. These registers are
the command instruction register and the mode instruction
register.
The format options available to the user are:
1) Parity Enable (PEN)
2) Parity Position (PIA)
The Parity bit (when enabled) can either be appended to the data word After the data brts or
it can be Inside the data word in the last bit
position.
3) Odd or Even Parity Select (EPS)
4) Character Length Select 5, 6, 7 or 8 Bits/Character) (CLS2 and CLS2i)
The Asynchronous mode has file option of selecting the
number of contiguous characters per transmission and receive sequence. This multicharacter option may facilitate
data handling between peripheral devices with a non-standard number of data bits. Therefore, the user can change
the mode register to transmit and receive any combination
of one to eight char'lcters per word and 5, 6, 7 or 8 b~s per
character.
Additionally, the Asynchronous mode has two options which
determine the operational characteristics of the protocol:
1) Stop Bit Selection-(SPS)
This control bit selects 1 or 2 stop bits (1 or 1Y2 bits in 5
bit characters) at the end of the word, which is part of the
character delimiting definition.

2) Asynchronous clock rate select (1 x or 16x clock rate),
which describes resolution and bit rate characteristics.

The WD1984 also contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (L TE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low ("0"). The status and output flags
operate normally.

ORGANIZATION

A block diagram of the WD1984 is shown in figure 1.
As mentioned, the WD1984 is an eight bit bus-oriented
device. Communication between the WD1984 and the controlling CPU occurs via the 8 bit data bus through the bus
transceivers. There are 2 accessible data registers, which
buffer transmit and receive data. They are the Transmit Holding Register and the Receive Holding Register. There is a
parallel-ta-serial shift register (parallel in-serial out), the
transmit register and a serial-to-parallel shift register (serial
in-parallel out), the receive register.
Operational control and monitoring of the WD1984 is performed by two control registers (the command instruction
register and the mode instruction register) and the status
register.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the control, status or holding
registers by activating the appropriate control lines: Chip Select (CS), Read Enable (RE), Write Enable (WE) and Control
or Data Select (C75).
Internal control of the WD1984 is by means of two intemal
microcontrollers; one for transmit and one for receive. The
control registers, null detect logic and various counters,
provide inputs to the microcontrollers which generate the
necessary control signals to send and receive serial data according to the programmed protocols.

192

The format and definition of the Command Register is shown below:

CR7

CR6

CR5

CR4

CR3

CR2

EPS

PEN

LTE

TXSM

REN

TEN

PIA

TEN

Transmit ENable

Enabled
Disabled

o
PIA

Parity Inside or After

After the data word
Inside (the last data bit) of word

o
REN

Receive ENable

Enabled
Disabled

o
TXSM

Transmit Space or Mark

Send break character (force TXD low)
Normal transmitter operation

o
LTE

Loop Test ENable

Local loop-back mode
Normal Operation

o
PEN

Parity ENable

Enabled
Disabled

Internal Reset

Returns WD1984 to mode instruction format

o
EPS

Even Parity Select

Even parity
Odd parity

'Internally disabled in Synchronous mode.

193

The format of the Status Register is shown below:

SR?

SR6

SR5

SR4

SR3

SR2

BRKDET

TXE

TXRDY

o
RXRDY
1

Transmitter Ready

Receiver Ready
Active (RHR should be read)
Inactive
Transmitter Empty

Transmitter idle
Transmitter active

Parity Error

Error reported
No error

Overrun Error

RHA has been overwritten
No error

Framing Error

o
BRKDET

TXADY

Active (THR can be reloaded)
Inactive (transmitter is busy)

TXE

RXRDY

Indicates a framing error has been detected.
No error
Break Character Detect
In ASYNC mode, this bit indicates the receiver has detected
a break character.
Inactive
Underrun Error

In multi-character transmissions, indicates that the
THR has not been loaded with a new character in
time for a contiguous data transmission sequence.
No error

194

The format and definition of the Mode Register is shown below:

MR7

MR6

MR5

MR4

SBS

MS2

MSI

0
0

MR3

MR2

MRI

MRO

CLS2

CLSI

MS2

MSI

Mode Selected
Undefined
Asynchronous mode (16X)
Asynchronous mode (1 X)
Synchronous mode (16X)

1
X

CLS2

CLSI

0
0

1
1

Characters Per Word Select

0
0
0
0

0
0

1
1

1
1
1

0
0

1
1

1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
8 characters

Character Lenllth Select
5
6
7
8

SBS

bits
bits
bits
bits

1
1
1

Stop Bit Select

2 stop bits (1-1/2 bits in 5 bit characters)
1 stop bit

The WD1984 registers are addressed according to the following table:

L
H
X

C/O

L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

H
L
H
L
X

~
~

VILat pins
V~IH at pins
don't care

195

Registers Selected
Read Receive Holding Register
Write Transmit Holding Register
Read Status Register
Write Control Registers
Data Bus Tri-Stated

A.C. TIMING PARAMETERS

SYMBOL
IRX

PARAMETER

MIN

RxRDY Delay from Center of Data Bit (FCR
Delay from Center of Data Bit)
Internal BRKDET Delay from Center of Data Bit
External SynDet Set-up time before rising
edge of RXC

MAX

UNIT

RRxe

!Rxe
ns

200

TXEMPTY Delay from Center of Data Bit

tTxe

------~-:-~~~~~-~-:--------------~~~-------Figure 4 TEST POINTS FOR A.C. TIMING

DATA
BUS

c:!5

Figure 5 READ CYCLE TIMING

Note: AC timings measured at VOH

= 2.0V,

VOL

DATA
BUS

Figure 6 WRITE CYCLE TIMING

196

TEST CONDITION

= O.BV

CL = 50 pF
(1 x Rate)

\+----TXC
IX BAUD

tTPW

-----_~+_14f------

tTPo

....._ _ _ _ _ _ _ _ _ _ 16 Txe PERIODS _ _ _ _ _ _ _ _ _ _-+1

TXC
16X BAUD

...;TX~D_ _ _ _

tOTX

Figure 7 TRANSMITTER CLOCI( AND DATA TIMINGS

1-o-------tSRX

-------o-i-f----- tHRX -------1>1

RXD

1-o-_ _ _ _ _ _ tRPW _ _ _ _ _-P~-----tRPO _ _ _ _ _~

RXC
IX BAUD

1 - 0 - - - - - - - - - - - - 1 6 Rxe P E R I O D S - - - - - - - - - - - + j
RXC
16X BAUD

Figure 8 RECEIVER CLOCK AND DATA TIMINGS

197

Rxe
(16x)

SDET - - - - - - - - - - {

RXD _ _ _ _ _ _ _ _ _ _~)(~_______1_st_d_a_ta_B_it_ _ _ _ _ _ _ _ _ __

Txe
(16x)

es e7i5

tTX

TXRDY

TXE

TIP
TXD

L
/

U
U
~~
\

I
\

1st data bit

Fi9ure 9 SYNCHRONOUS MODE TIMINGS

198

tTX

Start Sit

RXD
(Async)

RXD

1st Data Character

(Synch)

1st Data Charnctcr

2nd Data Character

2nd Data ChariJctcr

3rd Data Character

I pi
I

Stop bits

4th Data Character

FCR

RXADY

Figure 10 RXRDY AND FCR TIMING

T~E ~L_ _ _ _ _ _ _ _ _ _ _ _ __

TXRDY - - u - l L_ _ _ _ _ _ _- '

TXD

1st Data Character

2nd Data Character

3rd Data Character

4th Data Character

Start bit

Figure 11 TXRDY AND TXE TIMINGS (4 CHARACTERS SEQUENCE)

2 eight bit characters With start'stop bits and panty

Parity outside data Character
II programmed

Start bit

Marking Ime or
end of prevIous
character

(programmed stop bits

I
next transmission
1sl 8 bit Character

2nd 8 bit Character

Figure 12 16 BIT ASYNCHRONOUS
4 Five bit characters With starl/stap
bits and parity (parity programmed inSide last data character)
Panty InSide the last bit
of the last CharaCler\

Single stop bit

Marking line or
next transmission

Figure 13 20 BIT ASYNCHRONOUS

199

ASYNCHRONOUS OPERATION

When the Asynchronous mode is selected, start, stop and
parity bits are inserted as programmed. The receiver and
transmitter clocks can be programmed as 1X or 16X. The
transmitter output, TXD line will mark or space after transmission depending on command register programming. A
line break condition can be programmed by setting the
TXSM bit (command register bit CR3) to a logic "I". The
TXD line will be forced to a low as long as this bit is logic "I".
When the receiver detects the input line (RXD) low for a period equal to the word length including start, parity and stop
bits, the break detect flag will become active.
The multi-character option is available to the Asynchronous
protocol. The user can select any combination of one to eight
characters per word and 5, 6, 7 or 8 bits per character. This
allows a minimum word length of 5 bits and a maximum of 64
bits, plus parity, if enabled.
SYNCHRONOUS OPERATION

When the Synchronous mode is selected, start and stop bits
are not transmitted. Parity is not available in Synchronous
mode. The multi-character option is not available; however,
the transmitter will continuously shift out data as long as the
transmit holding register is buffered by the CPU. Two I/O signals are provided for synchronization, TIP (transmission in
progress), an output which indicates that the transmitter is
actively sending data and SYNCDET (SYNC detect), an input which notifies the receiver logic when to begin assembl ing characters.
Synchronization is obtained when the TIP signal from the
transmitter is brought to the SYNCDET input of the associated receiver. Completion of a data transmission sequence
occurs when the last character in the transmit register is sent
and no further data is loaded into the transmit holding register. The TIP signal goes low. The receiver monitors the
SYNCDET line and assembles data characters until it goes
low, at which time it goes to an idle state.
PARITY MODES

The WD1984 is provided with some unique parity options as
discussed above. If parity is enabled and the word length is
eight bits, the parity is added to the transmitted word and
stripped from the received word. When programmed for 5, 6
or 7 bits per character, the reroiver checks and makes available the parity bit on the bus dxt to the MSB of data. Unused
bits in an assembled chara,;ter are zero when the receive
holding register is read.

For example, in Asynchronous mode when two a bit characters are programmed with parity after the Data Word and two
stop bits, 20 bits are transmitted. These are the Start bit, 16
Data bits, Parity and the 2 Stop bits. The Parity will be
stripped off at the receiver since the character length is 8.
In Synchronous mode, Parity is not available and it is suggested the user provide his own software CRC as the last
characters of his transmission.
OPERATING DESCRIPTION

The WDI984 is primarily designed to operate in an 8 bit
micro-processor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, RE, WE and c7i5) should be
connected to the microprocessor's data bus and system control bus. The appropriate TXC and RXC clock frequencies
should be selected for the particular application, using a programmable baud rate generator such as a BR1941. A master
reset pulse initializes the WD1984 and presets the control
registers to transmit and receive four a-bit contiguous characters with the 32nd bit odd parity. If other protocols are desired, then the mode and command registers should be programmed as discussed previously.
For typical data communication applications, the RXD and
TXD inpuVoutputs can be connected to RS-232C interface
ci rcuits or a modem.
The TXRDY, RXRDY, FCR and FEIBRKDET Flags may be
connected to the microprocessor system as interrupt inputs.
The status register can be periodically read in a polled environment to support operations.
The CTS input can be used to synchronize the transmitter to
extema I events.
The WDI984 is designed such that a control register write
operation accesses the command instruction register. The
mode instruction register is accessed by performing a control
write operation setting the intemal reset bit high, which allows the next control write operation to program the mode
register. Subsequent control write operations will again
access the command register until another internal reset is
performed. Internal reset commands should also disable the
receiver and transmitter until the new mode instruction is programmed. The next command should then reactivate the receiver and transmitter to resume operations. This minimizes
any errors that may be generated as a result of an active receive line during reprogramming.

200

The TXSM bit of the command register causes the transmitter output to be forced low after the last word is transmitted.
This is also used in Asynchronous mode to send a break
character (all zero data and parity bits).

by raising the TXE flag. (No error is generated as a result of this condition.)
The Receiver operates similarly:
a)

The receiver is equipped with logic to look for a break character in the Asynchronous mode. When a break character is
received, the receiver activates the break detect flag and status bit. When the receiver input line goes high again lor at
least "one bit time", the receiver resets the break detect flag
and resumes its search for a start bit.
MULTI-CHARACTER OPERATIONS
As discussed above, the WDI984 is equipped with a multicharacter option which provides the user with the means of
transmitting and receiving multiple contiguous characters of
data within one set 01 start and stop bits. Since the WDI984
is an 8 bit bus-oriented device, the controlling processor must
read the WDI984 data from its holding register before the
subsequent characters are assembled. This situation also
exists on the transmit side, Le., the Transmit Holding Register must be loaded before the previous 8 bits are completely shifted out of the transmit register.

The TXE and TXRDY flags are "I" (active).

The external CTS signal = "0".
The CPU loads data into the Transmitter Holding Register, TXE and TXRDY go Low.

The data is loaded into the transmit register and TXRDY
goes High. This indicates the first data word is being
sent and the character can be loaded into the holding
register. If the WDI984 is programmed for more than
one character (multi-character) then an underrun error
will be generated if the next character is not loaded before the previous word is completely shifted out, unless
the current character is the last character in a sequence.

When the first character is completely assembled, the
data is loaded into the Receive Holding Register, the
FCR (First Character Ready) and RXRDY (Receiver
Ready) flags become active, "I". The CPU should
read the data prior to the reception of the next character or an overrun error will be generated as the receiver
will overwrite the old data with the new data character
just received.

It is possible to program a test routine using the loop-back
mode so that one can simulate "line breaks" and parity errors. This can be done using the TXSM command to interrupt
a transmit sequence in "mid-stream", since setting the TXSM
bit to a "I" while the transmitter is currently sending data will
immed iately cause zeroes to be sent until the TXSM bit is reprogrammed to a "0". This can only be done when in the
loop-test mode, else the TXSM command is recognized only
after the current transmission is complete.

"I".

The RXRDY and FCR flags are "0". (Inactive).
The incoming data word activates the receive logic and
the data begins to be assembled in the receive register.

LOOP TEST MODE:

The Transmitter operates as follows:
With the mode and command registers programmed
as desired, the transmitter is enabled, TEN (CRO) =

b)
c)

As mentioned, the WDI984 is equipped with a diagnostic
test mode, local loop-back. This mode is activated by setting
the LTE command bit to a "I". The TEN and REN bits should
be "I" and CTS should be "0". The receiver inputs are ignored and the transmitter outputs are held high V OH. The
transmitter is internally "looped-back" to the receiver and the
error and status flags operate normally.

Several "flags" are provided for interrupt purposes so that
continuity is maintained and data integrity is preserved.
These flags are First Character Ready (FCR), Receiver Ready
(RXRDY), Transmitter Ready (TXRDY) and Transmitter
Empty (TXE).

With the control registers suitably programmed, the receiver is enabled, REN (CR2) = "I".

For multicharacter operations, failing to reload the Transmit
Holding Register in the middle of a data send sequence will
cause an underrun error in the transmitter and a word error
in the receiver. Failure to read the Receive Holding Register
after a FCR or RXRDY flag will cause an overrun error to be
generated.
For Loop-Back test operations, the user should be sure that
the TXC and RXC clock frequencies are the same. This is
normally implemented by placing the same clock signal on
both pins (TXC and RXe).

If the last character is transmitted and no more new
data is to be sent, the transmitter will indicate its status

201

ABSOLUTE MAXIMUM RATINGS

Absolute ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is
not intended and should be limited to those conditions specified under DC Electrical Characteristics.

Storage Temperature
Plastic ("F" package) ................ -55"C to + 125'C
Ceramic C'E" package) .............. - 65'C to + 150'C
Voltage on any Pin with respect to ground ... - 0.5V to + 7V
Power Dissipation ............................. .400MW

DC ELECTRICAL CHARACTERISTICS
T A=O"C to

+70"C;

Vee =5.0V ± 5%; GND= OV

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

TEST CONDITION

VIL

Input low Voltage

-0.5

.08

VIH

Input High Voltage

2.0

Val

Output low Voltage

VCC
0.45

10l = 1.6mA

VOH

Output High Voltage

10H = -1001LA

-50

VOUT = 0.45V

VOUT= V

VIN = VCC

rnA

IDl

2.4

Data Bus leakage

III

Input Leakage

ICC

Power Supply Current

CAPACITANCE
TA = 25"C: VCC = GND =
SYMBOL

OV
PARAMETER

TYP

MIN

MAX

UNIT

TEST CONDITION

CIN

Input Capacitance

fC= lMHz

CliO

1/0 Capacitance

Unmeasured pins
returned to GND

+20
Ui

+10

>«
..J

0
I-

:::>

11.
I-

:::>
0

-10

<:I

-20

-100

/
V
-50

SPEC.

+50

+100

li CAPACITANCE (pF)
Figure 3 OUTPUT DELAY VS CAPACITANCE

202

A.C. TIMING PARAMETERS
SYMBOL

PARAMETER

MIN

MAX

UNIT

CONDITIONS

BUS PARAMETERS
Read Cycle

(Reference Figure 5)

c7B)
c7B)

tAR

Address Stable before RE, (CS,

tRA

Address Hold Time forRE, (CS,

tRE

RE Pulse Width

tRD

Data Delay from RE

200

CL = 50pF

tRDH

RE to Data Floating

200

CL = 50pF

WRITE CYCLE

350

(Reference Figure 6)

tAW

Address Stable before WE

tWA

Address Hold Time for WE

tWE

WE Pulse Width

350

tDS

Data Set· Up Time for WE

200

tWDH

Data Hold Time for WE

OTHER TIMINGS

(Reference Figure 7, 8, 9)

toTX

TXD Delay from Falling Edge of TXC

tSRX

RX Data Set-Up Time to Sampling Pulse

200

CL = 100pF

tNRX

RX Data Hold Time to Sampling Pulse

100

CL=I00pF

tTX

Transmitter Input Clock Frequency

tTPW

tTPD

tRx

tRPW

tRPD

500

1 x Baud Rate

500

kHz

4x, 16x Baud Rate

750

kHz

CL = 100pF

Transmitter Input Clock Pu Ise Width
1 x Baud Rale

1.0

16x Baud Rate

500

1 x Baud Rate

1.0

16x Baud Rate

700

Transmitter Input Clock Pulse Delay

Receiver Input Clock Frequency
1 x Baud Rate

500

kHz

4x, 16x Baud Rate

750

kHz

Receiver Input Clock Pulse Width
1 x Baud Rate

1.0

16 x Baud Rate

500

1 x Baud Rate

1.0

16 x Baud Rate

700

Receiver Input Clock Pulse Delay
ns
ns

tTX

TXRDY Delay from center of Data Bit

203

200 ns

tTXC

(Ix or 16x)

A
1_

r--

575

620 -..,

WD1984E CERAMIC PACKAGE

WD1984F PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after finar product characterization is
completed.
Information furnished by Westem Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its USB. No
Ik:ense is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORAr,ON

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

204

General Data Communications
Technical Notes

205

WESTERN
DIGITAL
p
c

TECHNICAL NOTE
Using The New Data Link Control Chips
ex>

By Geary Leger

o A NEW GENERATION OF LSI DEVICES FOR DATA LINK
CONTROL HAS ARRIVED. WHAT ARE THE ADVANTAGES? PITFALLS? TRADE-OFFS?
• THE TECHNOLOGY OF LARGE-SCALE-INTEGRATION
(LSI) HAS BROUGHT ABOUT A VARIETY OF NEW
DATA COMMUNICATIONS DEVICES WHICH HANDLE
BOTH EXISTING CHARACTER-ORIENTED PROTOCOLS AND THE RELATIVELY NEW BIT-ORIENTED
PROTOCOLS. THE MOST WIDELY PUBLICIZED ARE
THE MULTI-PROTOCOL CHIPS, AND THEIR ADVANTAGES HAVE BEEN DOCUMENTED. HOWEVER,
THESE CHIPS MAY NOT OFFER THE OPTIMUM SOLUTION. A COMBINATION OF CHARACTER-ORIENTED AND BIT-ORIENTED PLUG-COMPATIBLE ICS
MAY OFFER PERFORMANCE ADVANTAGE AND A
COST-EFFECTIVE ALTERNATIVE TO THE MULTI-PROTOCOL CHIPS.

Character-oriented refers to the method whereby both control data and text data have a fixed character length. This ~
length is often 8 bits but may also appear as 5, 6, or 7 bits. ::;;
Two types of synchronization are used. These are character
synchronization, which resyncs at each character by the use
of starVstop bits, and bit synchronization, which maintains a
bit rate clock synchronized between transmitter and receiver.
Character synchronization is commonly referred to as "asYnchronous", and bit synchronization is usually called "synchronous".
In character-oriented protocol, control data and user information both have the same format and use the same character set, such as ASCII or EBCDIC. Therefore, it is necessary to have a means to distinguish the control data from the
user information.

The character-oriented protocols have been in existence
since the early 60's, which is considerably longer than the
bit-oriented versions, and thus have a more widespread
usage. The most popular has been "Bi-sync" (BSC):

BIT AND CHARACTER-ORIENTED PROTOCOLS

A data link is a communications channel established between two or more locations for the purpose of information
transfer. A protocol is a set of rules controlling the orderly
exchange of that information.
Data exchanged across a data link contains both user information and control data. Satisfying the need to exchange the
user information is the whole reason for the data link: the sole
justification for the existence of the data link. The control (or
supervisory) data assures the reliable and orderly information exchange. Insertion, separation, and interpretation of the
control data is the responsibility of the protocol. A protocol
must also provide link initialization, termination, and error recovery. Among the rather wide variety of protocols which

In the relatively new bit-oriented method, data are divided
into frames which are preceded and ended by a unique flag
pattern (Ot111110). Within the frame are all control and text
data, and a 0 is inserted after each sequence of five contiguous 1's which provides data transparency. The only type of
synchronization used is bit synchronization.
The bit-oriented protocols offer a number of improvements
as shown in TABLE II. The standards for the bit-oriented are
primarily High-Level Data Link Control (HDLC), Synchronous
Data Link Control (SDLC), and Advanced Data Communication Control Procedure (ADCCP).
Initial work on the bit-oriented protocols began about 1969,
with the first applications available in about 1974.

have been used, there are only two types: character-oriented

and bit-oriented.

• BSC

207

Binary Synchronous Communications

PARITY

CHARACTER-ORIENTED
CHARACTER SYNCHRONOUS
Each character is synchronized individually by start
and stop bits. Error control is by means of a parity bit.

STOP
BIT

START
BIT

DATA

BCC

CHARACTER-ORIENTED
BIT SYNCHRONOUS

This particular example is

Each bit is synchronized by a bit clock locked to the transmitter
clock. Character synchronization is achieved by a beginning
synchronizing (SYN) character. Error control is by a l6-bit block
check character (BCC) which is generated by a cyclic redundancy
check (CRG) polynominal X 16 + X 15 + X 2 + 1.

sse, transparent.

ADDRESS

CONTROL

INFORMATION (DATA)

FCS

1=1

FRAME

BIT-ORIENTED
BIT SYNCHRONOUS

Each bit is synchronized by a bit clock locked to the transmitter clock. Each frame is synchronized by a unique begInning
and trailing Flag (01111110). In between flags, all sequences of 5 contiguous l's are followed by a O. Since a Flag
contains 6 contiguous 1's, it is not possible to misinterpret a Flag or Data. Error control is by the Frame Check Sequence
(FCS) which is the 16 bits preced ing the trailing flag. The FCS is generated by CRC polynominal X16 + X 12 + X!> + 1.

206

CHARACTER ORIENTED

BIT ORIENTED

ASYNCHRONOUS

SYNCHRONOUS

Interactive
devices such
as teletypes
and keyboard
display devices
ASR-33, T1 Silent
700, GE Terminent,
etc.

BSC (BISYNC)
DDCMP

HDLC, SDLC,
ADCCP, CCITT X.25

Table I: APPLICATIONS OF CHARACTER-ORIENTED AND BIT-ORIENTED PROTOCOLS

CHARACTER ORIENTED
PROTOCOLS

BIT ORIENTED
PROTOCOLS

Code Set Shared Between Data And Control Functions
Transparency Achieved Only Through Use Of Escape
Mechanisms
Device, Message, And Link Control Intermixed

Use Of Fields For Control Frees Code Set For Data
Naturally Code Transparent
Unambiguous As To Link Control Separates Link From
Device And Message Control.
Error Checking On Text And Supervision
Two-Way Simultaneous Capability Provides Efficient Utilization Of Full Duplex Link.
Very Flexible And Modular. Provides For Wide Range Of
Application.

Error Checking On Text
Two-Way Alternate In Nature (i.e. half-duplex)
Relatively Rigid In Structure

Table II: COMPARISON OF CHARACTER AND BIT-ORIENTED PROTOCOLS.
IMPLEMENTATION PROBLEM
Since the character-oriented protocols have been in existence for some time, there is already a large amount of
equipment installed world-wide which are established as
character-oriented terminals. Herein also lies a problem that
manufacturers and users of data communication equipment
face with character-oriented terminals. The bit-oriented may
represent the protocols of the future, but the character-oriented styles will stay for some time because of the enormous
economic investment they represent. Thus, how does one
plan for the future by providing bit-oriented capability, without prematurely obsoleting character-oriented equipment?

One solution is to use a multi-protocol-style chip; such as the
Signetic 2652, the Zilog SIO orthe Fairchild 3846. Basically,
these chips provide both character-oriented and bit-oriented
capabilities on the same chip.

used throughout that particular application. Therefore, a cost
effective solution is to design a printed circuit (or socket) to
accept either a character-oriented or a bit-oriented chip. To
reach this end, Western Digital Corporation has developed a
pin-for-pin compatible family, the WD1931 and WDt933.
Therefore, a single PIC board could satisfy both existing
character-oriented protocols and the newer bit-oriented protocols without the expense of a multi-protocol-style chip.
The W01931 is a versatile character-oriented chip. This chip
has automatic idle fill for both transparent and non-transparent BSC. Idle-fill is one desirable feature of BSC for transmitter processors which are slow with respect to the data
rate. A SYN (non-transparent) or a OLE-SYN (transparent)
may be inserted without affecting the integrity of the data,
and the CS ASTRO may be programmed for either SYN fill
or OLE-SYN fill.

One application for the multi-protocol chips is CCITT Recommendation X.21. X.21 defines three levels of data link
control. Level 1 is the physical interface and specifies a mechanical connection of a 15-pin connector. Levels 2 and 3
are the link initialization and call establishment phases. The
call establishment is specified as character-oriented, and is
followed by the data transfer phase which the user is free to
define as either character- or bit-oriented, but is bit-oriented
in probably all applications.

The W01933 is a universal bit-oriented data link controller
which will handle HOLC, ADCCP, or SDLC. Bit rates up to
1.5M bps may be achieved. A digital phase locked-loop may
be used with a 32X clock to facilitate usage modems without
timing clocks. Also, the W01933 may be used for SOLC loop
applications such as the IBM 3650 Retail Stores System.

However, in non-X.21 applications, only one protocol will be

Figure I details the compatibility of the 193111933 pins.

Table III shows a comparison of the combination 193111933
with two popular multi-protocol chips.

209

Table III. COMPARISON OF 1931/1933 COMBINATION WITH TWO POPULAR MULTI·PROTOCOL CHIPS

FEATURE
Maximum Data Rate (bps)
Bit·Oriented Protocol
SDLC Loop Mode Operation (e.g. IBM 3650)
Bit·Oriented Short Frame Detection
Bit·Oriented NRZI
Digital Phase· Locked Loop
Character·Oriented Protocol Synchronous
Automatic SYN Fili/Strip on BSC
Automatic DLE·SYN Fill/Strip on BSC
Transparent
Asynchronous
Shortened STOP Bit Capability
Asynchronous AUTO ECHO
Loop Test Diagnostic Feature
CRC for HDLC
CRC for Bisync
CRC for DDCMp··
Miscellaneous 110 Pins
N. A.

WESTERN DIGITAL
1931
1933
1.5M
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes

No
No
OUT.ONLY

Yes

SIGNETICS
2652 or
SMC 5025

ZILOG
SIO

1M/2M
Yes
No
Yes
No
No
Yes
Yes

550Ki880K
Yes
No
No
No
No
Yes
Yes

No
No
NA
NA
Yes
Yes
No
Yes
No

~ Not Applicable
DDCMP is Digital Equipment Corporation's protocol, "Digital Data Communication Message Protocol".
Only if DMA is not used.

210

No
Yes
No
No
No
Yes
Yes·"
Yes
No

Figure 1. PIN ASSIGNMENTS FOR THE 1931/1933

PIN #

1931

1933

COMMENTS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

IC
NIC
RE
CS
MISC OUT
INTRQ
WE
DALO
DAL1
DAL2
DAL3
DAL4
DAL5
DAL6
DAL7
MR
DTR
DRQO
DRQI
GND
NIC
AO

IC
EOB
RE
CS
MISC OUT
INTRQ
WE
DALO
DALI
DAL2
DAL3
DAL4
DAL5
DAL6
DAL7
MR
DTR
DRQO
DRQl
GND

IC ~ Internal Connection
NIC ~ No Internal Connection
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
NIC ~ No Internal Connection
Same
Same
See Note 1
Same
Same
Same
See Note 2
Same
See Note 2
Same
Same
Same
Same
See Note 3
See Note 3
See Note 3
See Note 3
Same
Same

+12V

TD
IXRC
RD
TBOC
CTS
RSCLK
1XTC
RTS
DSR
RING
RI
R2
R3
R4
CARD
+5V

A2
Aci
MISC IN
TD
RC
RD
NRZI
CTS
1X/32X
TC
RTS
DSR

RIT
RIO
CD1
CDO
CD
+5V

Note 1: If the system design does not make use of MISC IN on the 1933, the user may tie this to + 12V without harm or degradation to the 1933. This has the same effect as a logic input. If the system design does make use of MISC IN, then
provisions must be made to select +12V when the 1931 is in the socket or MISC IN when the 1933 is in the socket.
This may be accomplished by a small switch or by jumpers.
Note 2: The outputs TBOC and RSCLK on the 1931 may be tied to ground or to + 5 volts through a 10K pull-up without harm or
degradation to the 1931.
Note 3: If R1-R4 are not selected by the command word in the 1931, then anything may be on these inputs. URI and CD are
tied high in the 1933, then the inputs (pins 35-38) may have anything on them. When both the rate fields in the 1931
andRl and CD in the 1933 are used, the system designer must make provisions by an external switch or jumpers.
Note 4: The reader should also consult the data sheets for the 1931 and 1933.

211

BI-SYNC'S CRC: AN INHERENT APPLICATION PITFALL

Thus. It IS clear as to why the BI-sync CRC is a problem.
ImplementatIOn of the CycliC Redundancy Check (CRC) for
the BSC (bl-sync) poses a problem with no easy solution. By
contrast. the CRC application In the bit-oriented styles IS

There are a number of solutions.

The Zitog SIO performs the bl-sync CRC and allows the user
to turn-on or turn-off the CRC for each character. This has
onty one draw-back in that this method cannot be easily used
with Orrect Memory Access (OMA).

more straightforward

ThIS IS why all the bit-oriented chips handle the CRC automatically. but the character-oriented chips have difficulty
with the bl-sync CRC.

Another popular solution is to perform the CRC in software.
Then the CRC IS turned on or off either by calling or not calling the CAe computation subroutine. Several routines are
available, but are too numerous to mention here. One example of bl-sync CRC routine is shown In Figure 2. uSing
the assembly language of the 8080 microprocessor. The disadvantage of any software CRC IS the time-consuming
software overhead. Higher bit rates can be achieved by computing CRC before transmission. or after reception. of a text
frame. However, a time delay is still present, and system
throughput could be Impaired.

TABLE IV shows the differences between the two computations. However. the most Significant problem with the bl-sync

CRC IS the lack of continuity of the computation throughout
the data stream. The bit-oriented CRC Includes all data between the opening flag and the Irrst bit of the Frame Check
Sequence (FCS) field which just precedes the closing flag.
However. the rule for the bl-sync (CRC-t6) IS: CRC IS rnltialIzed by. but does not Include. the beginning STX (Start of
Text) or SOH (Start of Heading) and Includes all data up to
and Including ETX (End of Text). except for OLEs (Data link
Escape) Inserted for transparency. and except for SYN's
(Synchronization character) if non-transparent. or except for
OLE-SYN sequences not preceded by an odd number of
OLEs If transparent.

A thrrd sot uti on IS to use a hardware CRC generator which is
externat to the data tlnk control chip. This can offer the advantage of speed over the software approach. but has the
disadvantage of added hardware costs.
To summarIZe. because of the nature of the bi-sync CRC.
there is no "clean" solution to the problem of bi-sync CRC

Also, bl-sync may use one of two other error checking codes:

CRC-t2 or LRC (Longitudinal Redundancy Check). but the
CRC- t 6 IS most wldety used.

Implementation.

Table fV. COMPARISON OF CRC'S

FOR BSC AND HOLC/SOLC
FUNCTION
--------_.

HOLCSOLC

BSC (CRC-16)

Length

t6 Bits-

16 Bits

Transmitted

High Order
Bit First

Polarity

Inverted

Non-Inverted

Pre-Set Value

All '-s

All O's

ERROR-Free
Detection Pattern

1111000010111000

All O's

Order
Transmitted

Include All
Contiguous Data
In Computation?

Pol nomial

YES
X 16 • X 12

'Some Federal Government products requrre a 32 bit FCS.

212

NO
X 16 + X1S + X2 + 1

r----

RANGE OF APPLICATIONS
OF WD1933 COVERS
OUTER PERIMETER

HDLC/ADCCP

I\/G~'~\1<>-+--- ~::~:ATIONS
"-

---

OF WD2501
IS ENHANCED
X.25

OUTER PERIMETER INCLUDES ALL PROTOCOLS
WITH FOLLOWING COMMON CHARACTERISTICS:
ZERO BIT INSERTIDELETE.
LEADING AND TRAILING FLAG (01111110).
16-BIT FCS (X" + X" + X' + 1)

Figure 2 THE "WORLD" OF BIT-ORIENTED PROTOCOLS_

213

A DATA LINK CONTROLLER FOR PACKET NETWORKS
In addition to the 1933, Western Digital manufactures an LSI
device for bit~oriented protocols used in Packet-Switching
Networks. The WD2501 is called the Micro Packet Network
Interface (uPAC) and is compatible' with CCITT X.25 with
programmable enhancements. The 2501 is mentioned here
only briefly, and the reader should consult the Data Sheet for
more detail.

Both the 1933 and 2501 are bit-oriented devices aimed at
different application areas. The 1933 handles the widest
possible range of bit-oriented protocols. The 2501 is limited
to applications at or near X.25, but does more work within
this area. Figures 2 and 3 are aids to assist a user in selecting the bit-oriented controller that best fits his particular
needs.

Fi9ure 3 COMPARISON OF 1933 AND 2501 BIT-ORIENTED CONTROLLER
2501

1933
Handles all bit-oriented protocols HDLC, ADCCP, SDLC
Complete modem control (DTR, DSR, RI, CD, RTS,
CTS, etc.)
Zero-bit insertion/deletion, Flag appending and detection,
and FCS included.
DMA compatible.
Retransmission control by external CPU decision.
link set-up and disconnect controlled by external CPU thru
1933.
40-pln package.

More specialized. Handles super-set of X.25, level 2.
limited modem control (RTS and CTS, only).
Zero-bit insertion/deletion, Flag appending and detection,
and FCS included.
DMA included.
Retransmission control included in the 2501.
link set-up and disconnect included in the 2501.
48-pin package.

REFERENCES
1. "General Purpose Interface Between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) for
Synchronous Operation Over Public Data Networks"; CCITT Recommendation X.21.
2. "Interface Between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) for Terminals Operating
in the Packet Mode on PubliC Data Networks"; CCITT Recommendation X.25.

Informabon furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Otgital Cofpofation tor its use: nor any infringements of patents or other rights 01 third parties which may resutt trom its use. No
license is granted by imp/icahon or otherwise under any palent or patent rights of Westem Digital Corporation Westem Digital Corporahon
reserves the right to change satd circuitry al anytime without notice

WESTERN DIGITAL

3128 REOHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

214

Reprinted from

Electronics

Data-link conlro~ chip supports
an three bit-oriented protocols
Ability to handle newer control procedures increases
flexibility in designing data-communications systems

D As with any form of communication. rules. whether
implicit or explicit. a[c necessary' if messages afC to be
received and interpreted properly. In the case of data
communications. the increasing capability and cOInplcxitl' of equipment and rapidly rising software costs have
called forth thc developmcnt of more efficient sets of
rules. or protocols. The recent protocols for data-link
control have therefore switched from a charactcr- to a
bit-oriented approach.
This approach uses position instead of control characters to dcflnc the various parts of a message. thereby
boo.sting throughput and greatly simplifying implementation. I n addition. the newer protocols provide advanced
error-checking techniques, data transparency, and fullduplex capability.
Western Digital Corp.'s SD 1933 (and the version soon
to be produced as a second source by National Semiconductor Corp.) is the lirst data-link control chip to fully
support all three bit-oriented protocols: IB\-f Corp.'s
Synchronous Data l.ink Control (SDl.C), the International Standards Organi/ation's High-Level Data Link
Control (HDl.C), and the American National Standards
Institutc's Advanced Data Communications Control
Procedure (..\DCCP), which is almost identical to HDl.C
(sec "l.ots of protocols." p. 142, and "Data-link control
chips: bringing order to data protocols," Electronics. June
8, p. 104).
The SDI933 generates modem-controlling signals for
total link control. It interfaces a parallel digital system
\\'ith a serial data·communications channel. To under·
stand how this is done. the basic unit of information
transfer for the three bit-oriented protocols - the
frame-has to be examined.

FLAG
(01111110)

ADDRESS
(lOR MORE
iAOCCP AND HOLC]
8-BIT BYTES)

CDNTRD L
(1 OR 2
]ADCCP AND HOLe]
8-BIT BYTES)

The fraille consists of an address lield, a control field,
the information lield, and a fraille-check sequence (rcs)
and is bounded at each end by a Ilag (Fig. I). The Ilag
sequence is 01111110.
Picturing the frame

There are two addressing modes: the basic 4.1ddress
mode, \vhich uses a single address byte (X bits) and may
be an individual. group, or global address: and the
extended address mode (ADCCP and HDLC protocols
only), in which the licld is one or Illore bytes. In the
latter, if the lirst (2°) bit of an address byte is a 0, then
the next byte is an extension of the address licld. The
field is ter~'inated by putting a I in the lirst bit of the
last byte. I n this way. the address Ileld may be extended
to any number of bytes.
The control field, for encoding commands and
responses rcquired to control the data link. is one (all
three protocols) or two (.\DCCP and IIDLC) bytes long.
Three types exist. They arc: supervisory. used to convey
ready or busy conditions and possibly to report frame
sequence errors: information transfer. used to send
sequenced information frames: and nonse4uenced (un·
numbered), for data-link management, which includes
initiali7ing or activating secondary stations. controlling
the response mode of secondary stations. and reporting
proced u ra I errors.
The frame·check sequence provides error detection. It
uses the CUTT's 16-bit error-checking algorithm to
perform a cyclic redundancy check on the address,
control. and information tlelds. The transmitter first
presets its 16-bit frame-check sequence to all Is. :-':ext,
the binary value of the transmission to be sent is multi·

INFOAMATION FIELD
(ANY LENGTHl

FRAME-CHECK
SEOUENCE (16 BITS)

FLAG
101111110)

'~----------------------~y-------------------------/
FRAME

1. Information tranafor. The frame is made up of groups. or fields. of bytes that contain all the required data control information. as well as
the dala Itself_ II is always bounded by llag sequences. The flags conlain no information. they acl as slart and slap signals.

215

Data-link control: a glossary
Abort

ADCCP

Address field

Asynch

Bisync

Control field

CRe

Extended address

FCS field

a sequence of 7 to 14 conseculive binary is that terminates a
frame and also the continuity of
the data link
Advanced Data Communications
Control Procedure: the American
National StandardS Institute's
version (BSR X3.66) of SOLC
the field that defines the source
or destination of a frame: it
follows the opening flag of a
frame
any asynchronous data-communications protocol: transmission
in which each character is individually synchronized by the use of
start and stop bits; the length of
the gap between characters is
not necessarily fixed
Binary Synchronous Communicalions: a character-oriented synchronous data-communications
protocol developed by IBM; the
predecessor of SOLC
a one- or two-byte (ADCCP and
HOLC only) field that follows the
address field and is used for
sending commands and responses required 10. control the
data link
cyclic redundancy check: an error-checking technique that uses
a sophisticated mathematical algorithm
feature of AOCCP and HOLC that
allows the address field to be
more than one byte long
frame-check sequence field: a
16-bit error-checking field to validate transmission accuracy; it
uses CRC

plied and divided by appropriate polynominals. The
integer quotient is then ignored and the complement of
the remainder is transmitted. The receiver performs a
similar computation on each incoming frame, including

Transmitter

Receiver

Zero insertion

Zero deletion

CRe generiltion

CRe check

Abort generation

Aborted frame detection

Residual byte transmission

Residual byte detection

Variable.byte-Iength transmission

Variable-byte-Iength reception

Go-ahead (loop} mode

Go-ahead {loop} mode

NRZI encoding

NRZI decoding

Flag generiJtion

Idle detection
Invalid frame detection

Address comparison
Address extension

Flag
Full-duplex

Global address

Go-ahead mode

Go-ahead pattern

HOLC

Idle

I-field
NRZI

SOLC

STR

Zero insertion
and deletion

a bit sequence (01111110) used
to delimit frames
simultaneous independent transmission of information in both
directions
an address of all 1s, indicating
that the frame is intended to be
received by all stations
a special SOLC mode in which
the link is configured as a loop
with one primary and n secondary stations
a bit pallern of one 0 followed by
seven 1s, which is recognized by
secondary stations as permission
to transmit
High-Level Data Link Control: the
International Standards Organization's (ISO 3309) version of SOLC
a sequence of 15 or more consecutive is, indicating that the
data link is to be idled
information field
nonreturn-to-zero-inverted coding: a coding method in which the
output remains in the same state
to send a binary 1 and changes
state to send a binary 0
Synchronous Data Link Control:
IBM's most recent synchronous
data-communications protocol
(GA27-3093)
Synchronous Transmit and Receive: IBM's earliest synchronous
data-communications protocol;
predecessor of Bisync
an encoding and decoding method used within a frame to guarantee that there are no more than
five is in a row, thereby ensuring
data transparency

the frame-check sequence. If there arc no errors, the
receiver's Fes equals FOB8 (hexadecimal).
The information field may be any length, including
zero. Thus the minimum frame, not counting flags, is 32
bits long. In SDLC, the information field length must be a
multiple of 8 bits; consequently, the SDI933 can generate and receive a, residual byte of I to 7 bits.
Aborting the frame

Besides flags, two other bit sequences have meaning,
and both arc important features of the three bit-oriented
protocols. ;\ transmitting station may end a frame by
sending an abort-a sequence of 7 to 14 Is. The receiving station will then ignore the frame, and it may not
send another frame until it receives a command from the
primary station.
The third bit sequence triggers the idle state provided
for by the three protocols. The data link is idled when a
station receives 15 or more Is in a row. It remains idle

until a 0 is detected.
Another attribute of these protocols is zero insertion

216

and deletion, which ensures data transparency. Within
the two nags of a frame, a 0 is automatically inserted
during transmission after live I s and deleted on recep-

tion. Therefore no bit sequence in a frame can be misinterpreted as a nag, an idle, or an abort.
In addition, SOLe features a loop mode, called goahead. In this mode, each secondary station becomes a
repeater. Transmissions from the primary arc relayed
from station to station and then back to the primary.
Any secondary station finding its address in the address

lield of a frame captures that frame for action. i\ll
received frames arc then relayed to the next station down
the loop.
\Vhcncvcr a secondary station receives the go-ahead
pattern (a 0 followed by seven or more consecutive Is), it
may, at its option, suspend rcpealing and put its own
transmission on the line. \Vhcn it is finished, it sends a
go-ahead puttcrn, deactivates its transmitter, and again
becomes a repeater.
Performing the functions

The SDI933 performs all the functions required by
the SOI.e, AOCCP, and IIDl.e protocols (sec the table).
Built with n-ehannel metal-oxide-semiconductor technology, it uses a single 5-\'0It supply and is transistor-

TRANSMIT
REGISTER

GYGLIG-REDUNDAN GYGrlECK REGISTER

GRG-GENERATloN
REGISTER

LOOP

ES
WE

COMPUTER
INTERFACE CONTROL

oRU1

oRUO

INTRQ

EOB

MODEM
INTERFACE CONTROL

CLOCK
CONTROL

MISCIN MISCoUT

2. Layout. The architecture of the 801933 data-link control chip is fabricated on a chip 300 mils by 300 mils (top) Internal interconnections
(bottom) use 40 external pins for interfacing a parallel digital system with a synchronous serial-data channel.

217

ACTIVATE
RECEIVER

ACTIVATE
TRANSMITTER

COMMAND
REGISTER
1

NUMBER OF
CONTROL
BYTES

26
ADDRESS
COMPARISON

25
EXTENDED
ADDRESS

24
RECEIVER
BYTE
LENGTH
1

TRANSMITTER TRANSMITTER
BYTE
BYTE
LENGTH
LENGTH

COMMAND
REGISTER

TRANSMITTER TRANSMITTER
COMMAND
COMMAND

DATA
TERMINAL
READY

MISCEL·
LANEOUS
OUT

RECEIVER
BYTE
LENGTH

GQ·AHEAD
MODE

SELF-TEST

AUTO
FLAG

NOT
USED

COMMAND
REGISTER

RING
INDICATOR

CARRIER
DETECTION

STATUS
REGISTER

DATA
SET
READY

MISGEL
LANEOUS
IN

RECEIVE
IDLE

TRANSMITTER TRANSMITTER
RESIDUAL
RESIDUAL
BYTE
BYTE
LENGTH
LENGTH

30
TRANSMITTER
RESIDUAL
BYTE
LENGTH

ABORTED
FRAME,
INVALID
FRAME, OR
RECEIVER
RESIDUAL
LENGTH

OVERRUN OR
RECEIVER
RESIDUAL
LENGTH

CRC
ERROR OR
RECEIVER
RESIDUAL
LENGTH

INTERRUPT
REGISTER

RECEIVE
END OF
MESSAGE,
NO
ERRORS

RECEIVE
END OF
MESSAG E.
ERRORS

TRANSMITTER TRANSMITTER
OPERATION
OPERATION
COMPLETE,
COMPLETE,
NO
ERRORS
ERRORS

DATA
SET
CHANGE

DATA
REaUEST
IN
(RECEIVERI

DATA
REQUEST
OUT
iTRANS'
MITTERI

INTERRUPT
REaUEST

3. Registers. The 8D1933 exercises system control through the command registers and monitoring through the status and interrupt registers.
Command-register functions include specifying the type of information to be transmitted and received and the number of bits per byte.

transistor-logic~compatible on all inputs and outputs. It
comes in a 40-pin dual in-line package.
The SD 1933 operates at 1.5 MHz in full-duplex operation, and the SD 1933-03 at 2.05 MHz. Its basic read and
write signals arc: chip select (CS), read enable (RE),
write enable (WE), register-address select (Ao~A2)' and
data-access (DALo~DAL7).
Read and write operations arc initiated by placing
signals on the appropriate lines. For example, a write

operation is initiated by placing a 3-bit address on the
A2~Ao lines. CS and WE must then be activated. The
data on the data-access lines arc then locked into the
registers when either CS or WE is deactivated. A read
operation is initiated by placing the register address on
the A2~Ao lines. Next, CS and RE must be activated.
Data is then valid on the data-access lines and remains
valid until either CS or RE is deactivated,
System control is done through the command regis-

218

DATA
CONCENTRATOR

HOST
PROCESSOR

LlNE
PRINTER

,.,

DISK

...
CATHODE·RAY·
TUBE
DISPLAY

DATA
COMMUNICATIONS
CONTROLLER
SHOWN IN
DETAIL IN
(b) BELOW

CARD
READER

BUY/SELL
TRANSACTION· ENTRY
TERMINAL

t
REMOTE STOCK
TRADING QUOTE
(CRT)

(CRT)

ACCOUNTING
INFORMATION TERMINAL
(TELETYPE)

(,)

DATA·CDMMU NICATI DNS CONTRD LLER

MI CROP RDCESSO R

~IIIIIIIIIIIIIIIIII

'-v--'

TO TERMINAL

'-r-'
TO TERMINAL

(b)

4. Location. A basic data-communications system for a stock brokerage firm (a) uses Western Digital's 801933 data-link control chip to
connect a microprocessor to each modem in the line (b). Other applications include tellers' terminals and cash register terminals.

219

ters, and monitoring is accomplished by usc of the status
and interrupt registers (Fig. 3). The command registers
dictate what the transmitter will send: the type of information (abort, flag, rcs, or data), the number or bits per
byte, and the number of bits in the residual byte. Similarly, they tell the receiver the types of rrames to look
ror, the number or bits per byte, whether to perrorm an
address comparison, and whether to watch ror an
extended address.

Lots of protocols
Since the advent of synChronous data communica-

tions, a wide variety of protocols has been developed
by various military agencies, universities, and compa-

nies. The most widely used have been those generated
by IBM Corp.
The earliest were the Synchronous Transmit and
Receive (STR) and Binary Synchronous Communications (Bisync) protocols. However, the increased
sophistication of processing equipment called for more

Monitoring the signals

eHicient procedures.

The status and interrupt registers perrorm monitoring.
The status register indicates ir an aborted or invalid
and so on. The interrupt register indicates ir end-of-

Synchronous Data Link Control (SDLC), announced
in 1973, was developed to permit accurate full-duplex
transmissions with a high throughput. Some of the
advantages of SDLC over STR and Bisync are indepen-

message signals have been received and if frame transmission is complete. It also monitors the status or the

dence of code structure, full information transparency
without the use of control characters, a single stan-

frame has been received, whether an idle \vas received.

dard-frame format, and full-duplex operation.
After the introduction 01 SDLC, several national and

interrupt signals.
Various modems arc readily accommodated. as the
SD 1933 has a rull complement or modem interrace
signals. These signals include data set ready (DSR), ring
indicator (RI), carrier detect (CD), clear to send (CTS),
request to send (R TS), and data terminal ready (DTR).
An interrupt is generated if DSR, RI, or CD changes
state (the latter two ir so programmed). RI and CD may

international organizations issued their own versions.

The International Standards Organization's High-Level
Data Link Control (HDLC) is described in the ISO 3309
specification. The American National Standards Institute's version, called Advanced Data Communications

Control Procedure (ADCCP), is described in ANSI BSR
X3.66. The ISO and the ANSI specs are very similar and
both are supersets of SDLC (except for its loop mode).

be programmed to interrupt on the rising edge. on the

falling edge, or on both edges. The interrupt source is
determined by reading the interrupt and status registers.
The DTR output is set by a bit in the command register

and RTS is set when the transmitter is activated.
Still more choices
When the nonreturn-to-zero-inverted code is chosen

(a data transition \vhcn a 0 is sent and no transition
when a 1 is scnt). the transmitter encodes the transmitted data with the NRZI code before shifting it out.
Similarly, the receiver expects NRzt-encoded data and
will decode it before assembling data bytes.
In the I X mode, the SD 1933 rcquires the clock and
data signals to be phase-synchronized in order to ensure
link integrity. In the 32X mode, it uses a digital phaselocked loop to provide the synchronization, thus allowing
connection to asynchronous modems as well. However,
the loop requires data transitions to do this. Zero insertion and deletion guarantees transitions for long strings
of Is within a frame. To provide transitions for long
strings of as, the nonreturn-lO-zero-inverted option
should be used.
The end-or-data-block (EOD) option allows easy transfer of blocks of memory by direct memory access. Activated at the end of the data block, it causes automatic
transmission of the frame-check sequence and a flag.

Putting the chip to work
In a typical data-communications application (Fig. 4)
such as might be found in a stock brokerage firm, the
host and its peripherals arc located at the main office.
Terminals arc also located in remote offices. with
connection to the host via data-communications controllers. The terminals provide up-to-the-minute stock
prices, entry of customers' buy and sell orders, and
companies' financial statements, as well as the firm's

accounting and billing information.
Such a system is general enough to be configured for a
widc variety of applications. For example, the host
processor and remote terminals could be located respectively in airline reservation omces and ticket counters,
travel centers and travel agencies, central bank oflices
and branch banks, or department stores and individual
cash registers.
The host processor performs high-level data-processing tasks such as accounting, bookkeeping, and input and
output to the cathode-ray-tube terminal, line printer,
card reader, or disk. Usually, a large portion of the data
processing is dedicated to sending or accepting data to or
from the data concentrator. Sending large blocks of data
to the remote terminals via the data concentrator relieves
the host or time-consuming t/O chores, rreeing it ror
other processing tasb.
The data concentrator processes and rormats data to
allow for more orderly and efikient information transfer
between the host and the data-communications controller. It is modified ror each application to enable it to
translate the data received rrom the controller into a
format acceptable to the host, and vice versa. Other
functions include setting priorities for the controller's
channels, processing interrupts, and holding data until
the host is ready to accept it.
The data-communications controllers interface remote
terminals via modems (if necessary) with the data
concentrator. Each controller uses a microprocessor to
manage eight serial data-communications ports. Each
port contains a printed-circuit board with a 40-pin socket
filled with the chip appropriate for SDLC or Bisync
communications. A DIP switch on each pc board
programs it to expect the right one.
0

220

Generra~

Data CommlUl!l1icat~ons
Applications Notes

221

WESTERN DIGITAl..

TR1602/TR1863 MOS/LSi APPLICATION NOTES
ASYNCHRONOUS RECEIVER/TRANSMITTER
eMU

INTRODUCTION

length) and synchronizing start and stop elements are
added to each character as shown in Figure 2.

The transfer of digital data over relatively long
distances is generally accomplished by sending the
data in serial form thru a single communications
channel using one of two general transmission techniques; asynchronous or synchronous. Synchronous
data transmission requires that a clock signal be
transmitted with the data in order to mark the
location of the data bits for receiver. A specified
clock transition (either rising or falling) marks the
start of each data bit interval as shown in Figure 1.
In addition, special synchronization data patterns are
added to the start of the transmission in order for the
receiver to locate the first bit of the message. With
synchronous transmission, each data bit must follow
contiguously after the sync word, since one data bit
is assumed for every clock period.

The start element is a single logic zero (space) data
bit that is added to the front of each character. The
stop element is a logic one (mark) that is added to
the end of each character. The stop element is maintained until the next data character is ready to be
transmitted. (Asynchronous transmission is often
referred to as start-stop transmission for obvious
reasons). Although there is no upper limit to the
length of the stop element, there is a lower limit that
depends on the system characteristics. Typical lower
limits are 1.0, 1.42 or 2.0 data bit intervals, although
most modern systems use 1.0 or 2.0. The negative
going transition of the start element defines the location of the data bits in one character. A clock source
at the receiver is reset by this transition and is used
to locate the center of each data bit.

With asynchronous transmission, a clock signal is not
transmitted with the data and the characters need
not be contiguous. In order for the receiver to
properly recover the message, the bits are grouped
into data characters (generally from 5 to 8 bits in

The rate at which asynchronous data is transmitted
is usually measured in baud, where a baud is defined
to be the reciprocal of the shortest signal element
(usually one data bit interval). It is interesting to note

ONE

DATA
BIT
INTERVAL

CLOCK SIGNAL

_ _IL.J

DATA SIGNAL

TYPICAL

a BIT

SYNC PATTERN

FIRST DATA

BIT

Figure 1 Synchronous Data

STOP ELEMENT

...
~

f' ---------------

ONE. lilT
CHARACTER
(11001000)

START
ELEMENT

ONE. BIT
CHARACTER
(00100000)

Figure 2 Asynchronous Data

223

a>
~

Asynchronous transmission over a simple twisted
wire pair can be accomplished at moderately high
baud rates (10K baud or higher depending on the
length of the wire, type of line drivers, etc.) while it
is generally limited to approximately 2K baud over the
telephone network. When operating over the telephone network, a modem is required to convert the
data pulses to tones that can be transmitted through
the network.

that the variable stop length is what makes the baud
rate differ from the bit rate. For synchronous trans·
mission, each element is one bit in length so that the
baud rate equals the bit rate. The same is true for
asychronous transmission if the stop element is
always one bit in duration (this is referred to as
isochronous transmission). However, when the stop
code is longer than one bit, as shown in Figure 3,
the baud rate differs from the bit rate.

One of the major limiting factors in the speed of
asynchronous transmission is the distortion of the
signal elements. Distortion is defined as the time displacement between the actual signal level transition
and the nominal transition (6 t), divided by the
nominal data bit interval (See Figure 4).

Each character in Figure 3 is 11 data bit intervals in
length, and if 15 characters are transmitted per
second, then the shortest signal element (one data
bit interval) is 66.6 mslll = 6.06 ms; giving a rate
of 1/6.06 ms = 165 baud. However, since only
10 bits of information (8 data bits, one start bit and
1 stop bit) are transmitted every 66.6 msec, the bit
rate is 150 bit/sec. (Even though the stop element
lasts for two data intervals, it still is only one bit of
information)

The nominal data bit interval is equal to the reciprocal of the nominal transmission baud rate and all data
transitions should ideally occur at an integer number
of intervals from the start bit negative going transi·
tion. Actual data transitions may not occur at these
nominal points in time as shown in the lower waveform of Figure 4. The distortion of any bit transition
is equal to 6t x NOMINAL BAUD RATE.

There are several reasons for using asychronous
transmission. The major reason is that since a clock
signal need not be transmitted with the data, transmission equipment requirements are greatly simplified. (Note, however, that an independent clock
source is still required at both the transmitter and
receiver). Another advantage of asynchronous transmission is that characters need not be contiguous in
time, but are transmitted as they become available.
This is a very valuable feature when transmitting
data from manual entry devices such as a keyboard.
The major disadvantage of asynchronous transmission is that it requires a very large portion of the
communication channel bandwidth for the synchronizing start and stop elements (a much smaller
portion of the bandwidth is required for the sync
words used in synchronous transmission).

This distortion is generally caused by frequency jitter
and frequency offset in the clock source used to
generate the actual waveform as- well as transmission
channel, noise, etc. Thus, the amount of distortion
that can be expected on any asynchronous signal
depends on the device used to generate the signal
and the characteristics of the communication channel
over which it was sent. Electronic signal generators
can be held to less than 1% distortion while electromechanical devices (such as a teletype) typically
generate up to 20% distortion. The transmission
channel may typically add an additional 5% to 15%
distortion.

START ELEMENT
(ONE DATA BIT INTERVAL)

STOP ELEMENT

~~= ~B~T~H~:~T~R====J
~

AT 15 CHARACTER/SEC

= 66.6

6.06 msec

Figure 3

224

NOMINAL DATA
BIT INTERVAL

Figure4A

START ELEMENT

STOP ELEMENT
START ELEMENT

~==~~~~===--==~==~~:~===--I
I

CHARACTER INTERVAL

Figure4B

The distortion previously described referred only to a
single character as all measurements were referenced
to the start element transition of that character.
However, there may also be distortion between
characters when operating at the maximum possible
baud rate (i.e., stop elements are of minimum
length). This type of distortion is usually measured by
the minimum character interval as shown in Figure

4B.
The minimum character interval distortion is generally
specified as the percentage of a nominal data bit
interval that any character interval may be shortened
from its nominal length. Since many of the same
parameters that cause distortion of the data bits are
also responsible for the character length distortion,
the two distortions are often equal. However, some
systems may exhibit character interval distortions of
up to 50% of a data bit interval. This parameter is
important when operating at the maximum baud rate
since the receiver must be prepared to detect the

225

next start bit transition after the minimum character
interval.
Asynchronous receivers operate by locating the
nominal center of the data bits as measured from
the start bit negative going transition. However, due
to receiver inaccuracies, the exact center may not be
properly located. In electromechanical devices such
as teletypes, the inaccuracy may be due to
mechanical tolerances or variations in the power line
frequency. With electronic receivers, the inaccuracies
are due to frequency offset, jitter and resolution of
the clock source used to find the bit centers. (The
bit centers are located by counting clock pulses). For
example, even if the receiver clock had no jitter or
offset, and it was 16 times the baud rate, then the
center of the bit could only be located within 1/16 of
a bit interval (or 6.25%) due to clock resolution.
However, by properly phasing the clock, this
tolerance can be adjusted so that the sample will
always be within ± 3.125% of the bit center. Thus,

signals with up to 46.875% distortion could be
received. This number (the allowable receiver input
distortion I is often referred to as the receiver distortion margin. Electromechani~al receivers have distortion margins of 25 to 30%. The receiver must also be
prepared to accept a new character after the minimum character interval. Most receivers are specified
to operate with a minimum character interval distortion of 50%.

TR1602 Operation**
The WDC TR 1602 is designed to transmit and receive
asynchronous data as shown in Figure 5. Both the
transmitter and the receiver are in one MOS CHIP,
packaged in a 40 lead ceramic DIP. The array is
capable of full duplex (simultaneous transmission and
reception I or half du plex operation.
The transmitter basically assembles parallel data
characters into a serial asynchronous data system.
Control lines are included so that the characters may
be 5, 6, 7 or 8 bits in length, have an even or odd
parity bit, and have either one or two' stop bits.
Furthermore, the baud rate can be set anywhere
between DC and 20K baud by providing a transmit
clock at 16 times the desired baud rate.
'1-1/2 with 5 bit code
•• All references to the TR1602 operation also apply
to the TR 1B63 operation.

The receiver disassembles the asynchronous characters into a parallel data character by searching for
the start bit of every character, finding the center of
every data bit, and outputing the characters in a
parallel format with the start, parity and stop bits
removed. Three error flags are also provided to indicate if the parity was in error, a valid stop bit was
not decoded or the last character was not unloaded
by the external device before the next character was
received (and therefore the last character was lostl.
The receiver clock is set at 16 times the transmitter
baud rate.
Both the transmitter and receiver have double
character buffering so that at least one complete
character interval is always available for exchange of
the characters with the external devices. This double
buffering is especially important if the external device
is a computer, since this provides a much longer
permissible interrupt latency time (the time required
for the computer to respond to the interrupti.
The status of the transmitter buffer and the receiver
buffer (empty or full I is also provided as an output.
Another feature of the TR 1602 is that the control
information can be strobed into the transmitter and
receiver and stored internally. This allows a common
bus from a computer to easily maintain the controls
for a large number of transmitter/receivers.

TRANSMITTER

RECEIVER

STATUS

DATA ERROR FLAGS

TRANS·
MITTER

r==-:---RECEIVER CLOCK

CLOCK
PARALLEL DATA

PARALLEL
DATA IN

OUT

i
I

CONTROL~~

______~

I ASYNCHRONOUS I
ISERIAL

IOATA

1-----..:...,.'-- CONTROL

PARALLEL DATA
IN

OUT

I
RECEIVER
CLOCK
---'---'

DATA
ERROR

TRANSMITTER

~----~----CLOCK

_____I

_..J
RECEIVER

TRANSMITTER
STATUS

STATUS

FLAGS

Figure 5

226

The TRl602 data and error flag outputs are designed
for direct compatibility with bus organized systems.
This feature is achieved by providing completely TIL
compatible Three-state outputs (no external components are required). Three-state outputs may be
set to a logic one or logic zero when enabled, or set
to an open circuit (very high impedance) when disabled. A separate control line is provided to enable
the data outputs and another one to enable the error
flags so that the data outputs can be tied to a
separate bus from the flag outputs.
The TR 1602 inputs are also directly compatible with
TIL logic elements without any external components.

TABLE 1

CONTROL DEFINITION
CONTROL WORD

W
L

a a a a a
a a a 0
0 a a
a
a a a
x a
a a
x
0 a
a
0 a a
a
0 0
a
a
0
a
a
x a
a
x
a
a a 0 a
a a 0
0 a
a
a a
x a
0

TR1602 Description
Figure 6 is a block diagram of the transmitter portion
of the TRl602. Data can be loaded into the Transmitter Holding Register whenever the Transmitter
Holding Register Empty (THRE) line is at a logic one,
indicating that the Transmitter Holding Register is
empty. The data is loaded in by strobing the Transmitter Holding Register Load (THRL) line to a logic
zero. The data is automatically transferred to the
Transmitter Register as soon as the Transmitter
Register becomes empty. The desired start, stop and
parity bits are then added to the data and serial
transmission is started. The number of stop bits and
the type of parity bit is under control of the Control
Register. The state of the control lines is loaded into
the Control Register when the Control Register Load
(CRL) line is strobed to a logic one. The 5 control
lines allow 24 different character formats as shown in
Table 1. These 24 formats cover almost all of the
transmission schemes presently in use.
A Master Reset (MR) input is provided which sets
the transmitter to the idle state whenever this line is
strobed to a logic one. In addition, a Status Flag
Disconnect (SFD) line is provided. When this signal
is at a logic one, the THRE output is disabled and
goes to a high impedance. This allows the THRE outputs of a number of arrays to be tied to the same
data bus.
Figure 7 illustrates the relative timing of the transmitter signals. After power turn-on, the master reset
should be strobed to set the circuits to the idle state.
The external device can then set the transmitter
register data inputs to the desired value and after the
data inputs are stable, the load pulse is applied. The
data is then automatically transferred to the Transmitter Register where the start, stop and parity (if
required) bits are added and transmission is started.
This process is then repeated for each subsequent
character as they become available. The only timing
requirement for the external device is that the data

227

,
,
,
,
,
,
,
,
,
,
,
,

CHARACTER FORMAT

,
,
,
,
,
,,
,,

,
,
,,
,
,
,
, ,
,

,
,

,
,,
,
a
,
, a
,,
a
,

START
BIT

DATA

PARITY

STOP

BITS

BIT

BITS

000

000
EVEN

NONE

ODD
EVEN

EVEN
NONE
NONE

ODD
ODD
EVEN
EVEN
NONE

NONE

ODD
ODD

, ,

NONE

,
,
,
,,

1.5

000

1.5

NONE

a
a
a
a

1.5

EVEN

EVEN
EVEN

inputs be stable during the load pulse (and 20 nsec
after).
The TRl602 Transmitter output will have less than
1% Distortion at baud rates of up to 10K baud
(assuming the Transmitter Register Clock is perfect)
and is, therefore, compatible with virtually all other
asynchronous receivers.
Figure 8 is a block diagram of the Receiver portion
of the TR 1602. Serial asynchronous data is provided
to the Receiver Input (RI). A start bit detect circuit
continually searches for a logic one to logic zero
transition while in the idle state. When this transition
is located, a counter is reset and allowed to count
until the center of the start bit is located. If the input
is still a logic zero at the center, the signal is
assumed to be a valid start bit and the counter continues to count to find the center of all subsequent

•
TRANSMITTER REGISTER OUT
(25) (TRO)

STATUS FL.AG DISCONNECT (16) (SF D)

H-"-----

TRANSMITTER
HOLDING REG·

MASTER RESET (2l) (MRl

ISTER EMPTY
(22) (THRE)

TRANSMITTER REGISTER
;'
DATA INPUTS
I
(2&·33) (TRl TO TR I )

•

TRANSMITTER REGISTER CLOCK (40) (TRC)
TRANSMITTER REGISTER EMPTY (24) (TRE)

TRANS

TRANS
HOLD
REG

REG
CD

DATA
PARITY INHISIT (35) (PI)

EVEN PARITY ENABLE (39)

4
TRANSMITTER HOLDING REG·

CONTROL

REG

STOP BIT(S) SELECT (3&)

•

i
Figure 6 Trensmitter Block Diagram

cnWUI--OZ

(EPE)

CONTROL.

ISTER LOAD (23) (THRL)

(SBS)

WORD LENGTH SEL.ECT (37.31)
2 (WL.Sl.WLS2)

CONTROL REGISTER LOAD (34)
(CRL)

(\j
(\j

--.-Jr II~_ _ _ _ _ __
MASTER RESET

____________________JX~___________JX~______

T_R_A_N
__
SM
__
'T_T_E_R__
R_E_G_'S_T_E_R__
D_A_T_A__
'N_._U_T_S_______________

TRANSMITTER HOLDING REGISTER LOAD

L....__________--IFRANSMITTER

1/2 EXTERNAL CLOCK

START

1/2 EXTERNAL CLOCK

START

---;1 j
i I~j
--j~' ",,"",c "om I1

HOLDING REGISTER EMPTY

DATA

1/2 EXTERNAL CLOCK

-if

.&....--1_DATA-----I

STOP

TRANSMITTER REGISTER OUTPUT

nL-.-_ _------I1

----"

TRANSMITTER REGISTER EMPTY

Figure 7 Transmitter TIming Diagram

data and stop bits. (Verification of the start bit prevents the receiver from assembling an erroneous data
character when a logic zero noise spike is presented
to the Receiver Input). The Receiver is under control
of the Control Register described in the previous
paragraph. This register controls the number of data
bits, number of stop bits, and the type of parity as
described in Table 1. The word length gating circuit
adjusts the length of the Receiver Register to match
the length of the data characters. A parity check
circuit checks for even or odd parity if parity was
added by the Transmitter. If parity does not check a
Parity Error signal will be set to a logic one and this
signal will be held until the next character is transferred to the Holding Register. A circuit is also provided that checks the first stop bit of each character.
If the stop bit is not a logic one, the Framing Error
line will be set to a logic one and held until the next

229

character is transferred to the Holding Register. This
feature permits easy detection of a break character
(null character with no stop element). As each
received character is transferred to the Holding
Register, the Data Received (DR) line is set to a logic
one indicating that the external device may sample
the data output. When the external device samples
the output, it should strobe the Data Received Reset
(ORR) line to a logic zero to reset the DR line. If"the
DR line is not reset before a new character is transferred to the Holding Register (i.e., a character is
lost) the Overrun Error line will be set to a logic one
and held until the next character is loaded into the
Holding Register. The timing for all of the Receiver
functions is obtained from the external Receiver
Register Clock which should be set at 16 times the
baud rate of the transmitter.

INTERNAL CONTROLS
FROM CONTROL REGISTER

RECEIVER REGISTER

CLOCK (RRC)

(17)

1
RE·
CEIVER

REG

RECEIVER REGISTER

DISCONNECT CRRo)

(20)

START/STOP

C')

----.

RE·
CEIVER

RECEIVER

HOLD·
ING

HOLDING REG

REG

RECEIVER INPUT

(Rl)

DATA

(RR1·RRa)

DETECT &
BiT COUNTER

(5-12)

(')

'"
FRAMING ERROR
(FE)

CI.)

DATA RECEIVED

RESET

(DR R)

(18)

PARITY ERROR
END OF

(PEl

CHARACTER

(13)

DATA RECE)VED
(DR)

(19)

OVERRUN ERROR (15)

CoE)
STATUS FLAG DISCONNECT
(SFO)

(IG)

Figure 8 Receiver Block Diagram

UlWUI--OZ

Figure 9 illustrates the relative timing of the Receiver
signals. A Master Reset strobe places the unit in the
idle mode and the Receiver then begins searching for
the first start bit. After a complete character has
been decoded, the data output and error flags are
set to the proper level and the Data Received (DRI
line is set to a logic one. Although it is not apparent
in Figure 9, the data outputs are set to the proper
level one half clock period before the DR and error
flags, which are set in the center of the first stop bit.
The Data Received Reset pulse resets the DR line to
a logic zero. Data can be strobed out at any time
before the next character has been disassembled.
The TRI602 Receiver uses a 16X clock for timing
purposes. Furthermore, the center of the start bit is
defined as clock count 7-112. Therefore, if the
receiver clock is a symmetrical square wave as shown
in Figure 10, the center of the bits will always be
located within ± 3.125% (assuming a perfect input
clock) thus giving a receiver margin of 46.875%.

In Figure 10, the start bit could have started as much
as one complete clock period before it was detected,
as indicated by the shaded area of the negative going
transition. Therefore, the exact center is also unknown by the shaded area around the sample point.
This turns out to be ± 1/32 = ± 3.125%.
If the receiver clock is not perfect, then the receiver
distortion margin must be further reduced. For
example, if the clock had 1.0% jitter, 0.1 % offset
and the positive clock pulse was only 40% of the
clock cycle; then, for a 10 element character, the
clock would add:
1.0% + 10.1% x 101 +
(Jitter)

(Offset)

0.1 11'161

2.3% Distortion

Clock)
(The frequency offset was multiplied by the number
of elements per character since the offset is cumulative on each element).

I~------------------------MASTER RESET

STOP

START

I~ I

DATA

RECEIVER DATA INPUT

DATA RECEIVED

(DR)

AND ERROR FLAGS

RECEIVER HOLDING REGISTER DATA OUT

DATA RECEIVED RESET

'NOTE,

(Non-symmetrical

DATA OUT AND OVER·
RUN ERROR PRECEDES
DR & ERROR FLAGS BY

liZ CLOCK

Figure 9 Receiver Timing Diagram

231

STOP

DETECT START INTERVAL

RECEIVER CLOCK (16XI

TRUE CENTER OF START

RECEIVER INPUT
SAMPLE POINT

Figure 10

Since a clock with these characteristics is very easy
to obtain, it is apparent that a receiver operating
margin of slightly over 45% is very easy to achieve
when using the TRl602. Furthermore, this margin is
sufficient for virtually all existing transmitters and
modems presently in use.
The TR 1602 also begins searching for the next start
bit exactly in the center of the first stop bit so that
minimum character distortions of up to 50% can be
accepted.
A break character (null character without a stop bit)
will lock the receiver up since it will not begin looking
for the next start bit until a stop bit has been
received.

TYPICAL TRl602 APPLICATION
The TRl602 is ideally suited for use in distributed
computer networks such as is illustrated in Figure 11.
One of the primary purposes of the communications
controller is to assemble and disassemble the asynchronous characters (required for communication
with the data terminals) into the parallel data format
required by the host computer. Often the communications controller is a minicomputer and character
assembly/disassembly is performed by the software.
When this is the case, the minicomputer must be
interrupted at a rate equal to 8 to 16 times the baud
rate of all terminals being handled by the controller.
(The actual interrupt rate depends on the amount of
distortion that can be experienced on the received
characters). When the number of terminals exceeds
8 to 16, even the most powerful minicomputers
become overloaded due to the high interrupt rate
and the complex algorithms required by the software.
The TRl602 greatly reduces this problem by performing the character assembly/disassembly functions in
external hardware as shown in a typical configuration
in Figure 12. This solution not only reduces the interrupt rate by a factor of up to 176, but it also greatly

reduces the minicomputer load, thus freeing it for
other functions.
Since the TRl602 inputs and outputs are TIL compatible, the TR 1602 interface directly with virtually all
minicomputer I/O busses. In Figure 12, the minicomputer Data Output Bus is connected to the Transmitter Register (TR) inputs and the Control Register
inputs. When the minicomputer has a character to
transmit, the character is placed on the Data Output
bus and the address of the appropriate TRl602 is
placed on the Device Address Bus. The Address
Decode circuit will output a THRL load pulse under
control of the Data Out Strobe from the mini. When
the control register should be changed, a new 5 bit
control word is placed on the Data Output. Bus and
along with an appropriate device address which is
converted to a CRL load pulse in the Address
Decode circuits, again under control of the Data Out
Strobe. A THRE Pulse to the Interrupt Request circuit will notify the mini when a new character may
be provided to the TRl602 for transmission.
When a character has been received, a DR signal to
the Interrupt Request circuit will request an interrupt
from the mini. The mini will respond by setting the
proper device address and provide a Data in Strobe
pulse. The Address-Decode circuit then sets the RRD
line and SFD line to the appropriate receiver to
enable the Data Outputs onto the mini Data Input
Bus. The Data in Strobe from the mini then resets
the DR signal with a ORR pulse from the Address
Decode circuit.
The TRl602 Transmitter Output (TRO) and Receiver
Input (RI) must generally be converted to RS232
levels if they interface with a modem as shown in
Figure 12. RS232 is a standard that has been established by the Electronic Industries Association for the
interface between data terminals and data communications equipment. RS232-C defines a space as
greater than 3 volts and a mark as less than negative
3 volts at the Receiver input. A transmitter output of

232

HOST
COMM

COMP

CON·

TROL

Figure 11

between 5 and 15 volts is a space while a level
between - 5 and - 15 is a mark. The input/output
impedances and signal rise and fali times' are also
specified by RS232. Fairly simple discrete level
translators can be used to convert from the TTL
levels to the RS232 levels, or monolithic IC's are also
available.

233

It should be noted that the typical application illustrated in Figure 12 is only one of many and it does
not take advantage of many of the TRl602 features.
For example, the Status Flags could be tied to a
separate interrupt request bus or the TRE output
could be used to implement half-duplex operation.

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Information furnished by Western Dignal Corporation is believed to be accurate and reliable. However. no responsibility is assumed by
Western DigHal Corporation for
use; nor any infringements of patents or other rights of third parties which may resuH from ns use. No
license is granted by impfication or otherwise under any patent or patent rights of Western OigHal Corporation. Western Oignal Corporation
reserves the right to change said circunry at anytime without notice.

WEST~RN
COli

POll

DIGITAL
A

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3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

234

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WESTERN DIGITAL
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WD1931/WD1933

COMPATIBILITY APPLICATION NOTES

By Jan E. Rorval!
NISEi

INTRODUCTION

and reception. The only work that the computer is required to ;;;
do is to initialize the WD1931 or WD1933, and the devices CJ)
take care of the serialization or deserialization of data, plus
control and timing.
~

The purpose of this document is to provide the reader with
information about the WD1931 and WD1933 devices, and
how to take advantage of their compatibility. Various applications examples are given showing flowcharts and timing
diagrams. As the devices are designed for use in a very large
range of applications, many different features are described
and illustrated for the benefit of the reader.

:x:

Some control signals on the computer side of the devices are
needed for read, write, and control purposes. Additional signals can also be used for special purposes or modes for the
convenience of the user. Typically, these other control signals are used to enable communication with a modem or
DCE (Data Communications Equipment).

For detailed product information such as A.C. and D.C. parameters, please refer to the respective data sheets.
GENERAL DESCRIPTION
The WD1931 and the WD1933 are MOS/LSI devices which
interface a parallel digital system to a serial data communication channel (and vice versa). Both circuits are capable of
simplex, duplex, and full duplex operation.

Interrupt outputs are provided to inform the microcomputer
when to retrieve from, or to provide data to the holding registers. Also, interrupts can be generated to provide status information such as changes in modem control lines, or that
events such as Transmission Complete or Received End of
Message have occurred.

The WD1931 is designed for character-oriented asynchronous and/or synchronous (BI-SYNC) protocols. The WD1933
is designed for bit-oriented SDLC, HDLC and ADCCP protocols. The devices are programmable and compatible to
most S-bit microcomputers on the market. The pin assignments of these two devices have been chosen to all ow the
user to implement a one-board multi protocol design. This
board may then be used for any of the above mentioned protocols, by choosing the proper device (WD1931 or WD1933)
and connecting some jumpers (see paragraph entitled "Multiprotocol Board Design"). The purpose of these circuits are
to convert parallel data from a computer or terminal to a serial data stream at one end of a communication channel. At
the other end of the channel, the data is converted back to
the original parallel data.

SYSTEM APPLICATIONS

Serial data communications minimizes the number of physical channels required to transfer data and therefore reduces
the cost to send data between two (or more) distant points.
A microcomputer could perform the same serial/parallel
conversion function as these devices, but at much slower
speeds. However, using the WD1931 and WD1933 devices
to do this function is much more efficient. This makes the
computer free to perform other tasks during transmission

X.25

WD193t/33 may be used in the following applications:
Switched network
Multipoint network
Non-switched point to paint network
Simplex, half-duplex, or full duplex
Asynchronous or synchronous communication
Message switching
Multiplexing systems
Data concentrator systems
Loop data link systems
DMA applications
Parallel to serial data conversion (and vice versa)
Local Networks
Packet Switching
Multidrop line systems
A typical block diagram of a data link is shown in Figure 1.
The communication media used could be a direct communication channel (such as a leased telephone line), a swnched
telephone line, or one of many other possibilities. Typically
these applications would require the use of a modem.

'"~--------,~------~
STATION B

STATION A

Figure 1 DATA LINK BLOCK DIAGRAM

•

eM@a'.@ •

235

,Ngg;

:li

between a zao microcomputer and a modem. This is called
a multiprotocol board, which is described later in this
document.

The applications that these devices could be used in would
be a combination of the previously mentioned. A modem'
would be needed for long distance communication lines. For
shorter distance, line drivers/receivers may be sufficient. In
some very well controlled environments, such as a laboratory, two devices may be connected without line drivers and
receivers.

Some examples of various WD1931/WD1933 systems are
shown here by use of block diagrams. The station shown in
Figure 3 consists of a computer or terminal, a multiprotocol
board, and a modem. A station may consist of only the computer or terminal, and one WD1931 or WD1933 device.
Whether the modem, line drivers and receivers, or CPU buffers are needed depends on the details of the particular design situation.

The WD1931 orWD1933 may be connected directly to a microcomputer bus, but buffers would normally be recommended. Figure 2 shows a typical schematic of an interface

E'A RS-422

LINE DRNEPJRECEIVER

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TO MODEM

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OROI

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COMPUTER

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Mffi't"OOf

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"

OTR
-6A[(i

RfV

COT (R3)
~

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Figure 2 WD1931/1933 AND MICROCOMPUTER. (MULTIPROTOCOL BOARD)

236

(OCE)

TELEPHONE/DATA COMM.
SWITCHING NE1WORK

SWITCHED NETWORK

STATION

~____A
____~'~------------~--------~'L_____B____~

L---------~·~IL___ST_A_~I_O_N ~
__

MULTIPOINT NETWORK

S_TA_~_'O_N ~I'~--------------------~'I~__S_TA_~_'O_N ~

L -__

NONSWITCHED POINT TO POINT NETWORK

Figure 3 TYPICAL NETWORKS

237

LOOP DATA LINK SYSTEM

DATA COMMUNICATIONS EXAMPLE NO.1

The Loop Mode is used in SDLC only. A loop data I ink system consists of one primary station (Loop Controller), and a
number of secondary stations all functioning normally as repeaters. Figure 4 illustrates a typical Loop Data Link system.

The diagrams below (Figures 5 and 6) illustrate a typical dig·
ital system employing several processing levels and digital
communications protocols. It is flexible enough to satisfy
several applications. For example, the host processor and
remote terminals could be located in airline reservation of·
fices and ticket counters, travel centers and travel agencies,
central bank offices and branch banks, or department stores
and individual cash registers. The exploded diagram 01 the
Data Communications Controller ex em pi if ies the use of one
common circuit board design with eight multiprotocol circuits. When one port requires a character-oriented protocol
(asynchronous, character oriented synchronous, or bisync),
the WD1931 is installed into the appropriate socket. For
SDLC, HDLC or ADCCP, the WD1933 is used.

Any secondary station finding its address in the address field
captures the frame for action at that station. All received
frames are relayed to the next station down the loop.
A secondary station is allowed to suspend the repeater function and initiate its transmission when a Go-Ahead pattern is
received.

PRIMARY

STATION

SEC.
STATION
A

SEC.

STATION

(

SEC

SEC.

STATION
B

STATION

SEC.

STATION
C

Figure 4 LOOP DATA LINK SYSTEM

238

SHOWN IN
DETAIL
BELOW
CONTROLLER
(EXPANDED
BELOW)

Figure 5. STOCK BROKERAGE SYSTEM

CENTRAL PROCESSOR BUS

-,
I

LINK

I
I

I
I
L

I
I

OATA COMMUNICATION
CONTROLLER

--.J
TO REMOTE
TERMINAL

TO REMOTE
TERMINAL

Figure 6 DATA COMMUNICATION CONTROLLER

239

DATA COMMUNICATIONS EXAMPLE NO.2

DATA COMMUNICATIONS EXAMPLE NO.3

Figure 7 illustrates a Host Computer that communicates
through modems to a multiprotocol board. This in tum collects information from many remote stations through a Data
Concentrator.

A simplified HDLC point to point connection is shown in Figure B. In this example, no buffers or line drivers and receivers
are used.
Figure 9 represents a more "real world" application with the
use of modems through a communications channel.

.. ,jOST CO,,","UT(R RECEIIIES AND STOAES DATA ~ROM VARIOuS DISTANT COMPUTEIlS

Willi

,0'

CONTROL

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"IOTE I
"101£2
"lorE 3
JUTSAIE UNUSED AND
NOT SHOWN CONNECT THESE TO • 5V

Figure 8 HDLC POINT TO POtNT

240

COMPUTER

OR
TERMINAL

COMPUTER

OR
TERMINAL

WDI933
(DTE)

f----13

Fif"N(';

fHS

i7TT

TBOC

1m
TO
VDO I l/VI

Ail

Figure 10 WD1931 PIN CONNECTIONS AND BLOCK DIAGRAM

Eoa

Dl
02

RTS

155
D6

-67
MR
OTR
ORaD
ORal
VSS (GNO)

16 '"

I~ I" 18

Is Iii

I~ I~

Figure 11 WD1933 PIN CONNECTIONS AND BLOCK DIAGRAM

242

;

ASYN(.

MODE

;

BREA~

LOOP
NORM
X"'IT

""~'~O, _0,,_

'"
ee'

TAAN
,~~

AsmC
MODE

ECHO

~Mlr

SY!-'C

MODE

,~,

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,C<

CH"'R
LENG

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SYNC

ASVfJC

SYNC
MODE

,,~

TRM,

,C<
en

,e<

STRIP

ASYNC

ce,

ce~

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"ee,

MODE

SYNC
MODE

I I

OVER
RUN

ORQO

DROI

,~~

I I I

I I I I I I I I I

SYNII. OLE

""~

I I'"~

I I I I I I I
WD1931 BIT ASSIGNMENTS

Ai"

READ

WRITE

CLOCK

CR1

NONE

CR2

SYN &
DLE

RHR

THR

NONE
SRD

SR~7,SYN,DLE ~

RHR ~

AG.

THR

WD1931 REG. ADDRESSES AND CLOCKS

Figure 12 WD1931 REGISTERS

243

TC. SRl-4
~

RC.
NONE
NONE

AC1
REC

AC1
TRAN

XMIT
OPCOM

OPCOM

ERROR

WD1933 BIT ASSIGNMENTS

READ

WRITE

CRl

NONE

CR2

NONE

CR3

NONE

RHR

RHR ~

THR

IR ~

CLOCK

Te.

SRO-3 ~

WD1933 ADDRESSES AND CLOCKS
Figure 13 WD1933 REGISTERS

244

l'iC.

Re.

NONE

THR

NONE

SR4-7

NONE

MULTI PROTOCOL BOARD DESIGN

28 and 30 may be connected to +5V via a 10K resistor, and
pins 35 through 38 may be connected directly to +5V.
TRANSMISSION AND RECEPTION EXAMPLES

The WD1931 and WD1933 pin assignments were chosen so
that a circuit board designer may use only one 40-pin socket,
but have the choice of using either device on that board. Depending on the application, a few jumper wires may be
needed, or perhaps none at all. Figure 2 shows a typical example of a multiprotocol board. This board may be designed
with even less components and jumpers, dependent on the
particular application it is intended for.

TRANSMISSION EXAMPLE 1 (ONE FRAME)
A typical sequence of events is shown here to transmit a
message from computer A to another computer (or terminal)
B. Through a switched network the message to be sent is a
synchronous SDLC protocol frame as shown below in Figure
14. For simplicity, the message sent in this example is very
straightforward and short.

Jumpers lA-7A are to be connected when WD1933 and all
its options are used. Jumpers 1B-7B are to be connected
when WD1931 and all its options are used.

line drivers and receivers are used, pemnitting transmission
to a remote DCE or modem (see schematic in Figure 2). As
the SDLC frame is sent, the WD1933 is used. The jumpers
required are lA-7A. Figure 15 illustrates the functional flow,
and Figure 16 details the timing of the transmitted frame.
Note that the device can be programmed in several d iflerent
ways to allow for various requirements.

For example, if the user does not need the NRZI signal
mode, the IX clock is only used, no Ring or Carrier Detect
indication is needed, TBOC, RSCLK and MISC IN are not
used, and then no jumpers are needed in the design. In this
case, pin 24 may be permanently connected to + 12V. Pins

FLAG

ADDR.

CONTR.

INF.
DATA

FCS

Figure 14 SDLC FRAME FORMAT

245

FLAG

FLOWCHART
INTERRUPT MODE
AUTO FLAG
INF. DATA ~ 8 BITS (8-BIT CHARACTER WITH NO RESIDUAL BITS)
TC COMMAND IS USED TO INITIATE FCS.
INITIATE
TRANSMIT MODE
DTE AND DCE IDLE
PORT A
PORT B

OUTPUT
INTERRUPT
INPUT

AUTO FLAG
DATA TERM. READY

PA,., ~ 01111111
PBO/PB1 (INTRO/DROO)

CR3,.,
CR2,.,
CR1,.,

0000 0000
0000 0001
00000010

COMPUTER DOING
OTHER TASKS
DATA SET READY
INTERRUPT NO.1

ERROR

DATA SET CHANGE

Figure 15 FLOW DIAGRAM OF FRAME TRANSMISSION

246

INTERRUPTS

ACTIVATE TRANSMITTER.
00
TRANSMIT COMMAND
(DATA).

CR1 1 -{l

0100 0010

COMPUTER
DOING OTHER
TASKS

TRANSMIT DATA
INTERRUPT NO. 2-N

YES

ERROR

RESET ACT
TRAN BIT
&

Te '" 00

ONE FLAG IS AUTOM. TRANSMITTED. THEN TO GOES IDLE

Figure 15 FLOW DIAGRAM OF FRAME TRANSMISSION

247

""""fC (lX CLOCK)

DRQO
NOTE 2
INTRQ

OTR
fiTS

,
Ht..I~I

NOTE 1 AND4

--.II.-

-1t

c ;"-,

rJ~!

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~~
LU

[

wu
"ow
w"

_ _ _ _~~_ _~_ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _~L_ _ _ _ _ _~~

NOTE 1

"
~

'w
8tr

NOTE 1, COMPUTER TIME MAINLY
NOTE 2. DATA SET READY RESPONSE TIME PLUS TIME TO NEXT
NEGATIVE TRANSITION OF'j"(;
NOTE 3, COMPUTER TIME PLUS TIME TO NEXT NEG, TRANS OF"""fC
NOTE., MODEMS WITH DSR PERMANENTLY ON, WILL NOT SET INTAO
HERE
NOTE 5, THIS TIME ~ 2 TC (2 CLOCK PULSES), IF CTS RESPONSE", '" Te

Figure 16 TIMING DIAGRAM OF FRAME TRANSMISSION

WD1933 TRANSMISSION EXAMPLE 2
(DMA APPLICATION)
The WD1933 is very efficient for DMA applications. The control registers are loaded to initiate the WD1933 for DMA
mode in the same way as in Transmission Sample 1. The
Auto Flag bit is set, and the Transmitter Command is "DATA"
(CR14 and CR15 bits = 00). The procedure to set up the
I ink (initiate transmit mode and data set ready) is the same
as in Transmission Sample 1. When INTRQ is set and the
Transmitter is activated, the DMA Controller Board takes
over control. From this time on, the DMA Controller Board responds on every DRQO (Data Request Out). When the last

character is transmitted, the INTRQ is recelvea, ana tne control is switched back over to the CPU.
A very important feature of the W01933 is the EOB (End of
Block) input. Instead of using the normal (time-consuming)
method of writing into a control register to start the FCS
(Frame Check Sequence). the EOB input is activated at this
time. At the next occurrence of INTRQ the EOB signal is
deactivated.
An example of a schematic/block diagram is shown in Figure
17, and a timing diagram is shown in Figures 18 through 20.

248

DATA BUS

TO
LINE
DRIVERS/
RECEIVERS

NOTE 1. IF ACTIVE HIGH (1· HIGH I TYPE DATA BUS
USE DATA BUS INVERTERS

Figure 17 BLOCK DIAGRAM OF DMA APPLICATION

1ST FRAME

'-------'I '------I

1~---------'I

Figure 18 DMA TIMING OF FIRST FRAME

249

FRAMES BETWEEN
1ST AND END FRAME

_ _ _ _ _

~~~,~~NTR

~n~_~nL

_ _ _ _ _ _ _ __

_________

I
I

Figure 19 DMA TIMING OF MIDDLE FRAMES

END FRAME

I
•

"'" I

·1,

,"com

------'"00

.J1.J--u- - -

.1.

-----+1,'-,-

I
~,~~~

---.11_-----'

___
I _

_______

~nL

Figure 20 DMA TIMING OF LAST FRAME

250

_ __

WD1933 RECEPTIDN EXAMPLE 1

character, and two residual bits. This example may not be a
typical frame, but it shows how the WD1933 works in a wide
range of frame structures.

A sequence of events is shown in illustrating how to receive
a message with the WD1933 device. For simplicity, the same
SDLe frame structure is used as in Transmission Example
1. Also, please refer to the same interface circuitry shown in
Figure 2.

The first FLAG and FCS are not shown in detail, and are not
critical to this example.
Figure 23 illustrates the functional flow, and Figure 24 contains the timing information.

Figure 21 illustrates the functional flow, and Figure 22 contains the timing information.

WD1933 LOOP DATA LINK EXAMPLE
WD1933 RECEPTION EXAMPLE 2

This example shows how to program a secondary station to
function in Loop mode. The functional flow is illustrated in
Figure 25, and the interface circuit is shown in Figure 2.

This example shows a frame with two ADDRESS characters,
two CONTROL characters, one 5-bit INFORMATION DATA

FLOWCHART
DATA SET READY
18T INTERRUPT

INITIATE
RECEIVE MODE

ACTIVATE
PORT A = OUTPUT
PORT B = INTERRUPT
INPUT

MAMOMENT.
CONFIGURE
Pia

ADDRESS_AR

PAro = 01111111
PBO/PB2 (INTAQIDAQI)

EXAMPLE: AR

INTERRUPT

33H
DATA SET READY

SET AD DR
DATA TERM. READY

COMPARE
AND OTR

CR2 = 01000000
GAl = 00000010

ACTIVATE RECEIVER

COMPUTER
DOING OTHER
TASKS

Figure 21

FLOW DIAGRAM OF FRAME
RECEPTION (EXAMPLE NO.1)

251

RECEIVE DATA
INTERRUPT NO. 2·N
(ADDRESS MATCH)

READ IR
ENABLE
INTERRUPT.

ORal
l'

READ

RHR
(ERROR)

READ SR REG.
BITS 0-2
TO FIND
OUT WHAT
TYPE OF
ERROR

COMPUTER
DOING OTHER
TASKS
REMOVE
LAST TWO
CHAR. RE·
CEIVED

YES

SAVE RESIDUAL
BITS, BUT
MASK OUT THE
OTHERS IN
LAST CHAR
NOT REMOVED

Figure 21 FLOW DIAGRAM OF FRAME RECEPTION

252

IDLE

,",

1""""1"""::1"""
"I""""I""""""""'I""""~
II
~DDA ----l ~O~15A. AG'
• I ,.
I I
I
I,
;~~~
r

res

____~I~I~I~I~I--L
NOIE 1 DATA SET CHANGE INTERRUPT
NOT SHOWN HERE
NOTE 2 PAOGAA",,,,(O ADDRESS I'N AR REG)

33H

Figure 22 TIMING DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.1)

253

FLOWCHART

INITIATE
RECEIVE MODE
PA,.o = 01111111
PBO/PB2 (INTAQlDRQI)

PORT A '" OUTPUT
PORT 8 = INTERRUPT
INPUT

INTERRUPTS

EXAMPLE: AR '" 1CH

ADDRESS 1 INTO AA

PROGRAM
EXTENDED CONTROL
ADDRESS COMPARE
EXTENDED ADDRESS
RECEIVE CHAR. LENGTH
= 5 BITS

DATA TERM. READY

CR2

11111000

ADDR AND
RCl = 5

SET
DTR

CAl = 00000010

COMPUTER
DOING OTHER
TASKS

DATA SET READY
18T INTERRUPT
(DATA SET CHANGE)

ACTIVATE
RECEIVER

COMPUTER
DOING OTHER
TASKS

SEE DATA SET
READY IN
RECEPTION EXAMPLE 1

Figure 23 FLOW DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.2)

254

RECEIVE DATA
INTERRUPT NO. 2·N
{ADDRESS MATCH)

READ IR
ENABLE
INTERRUPT

YES

NO
(INTRQ)

READ RHR

REOM'

NO
(ERROR)

EX.
IS
83H

BITS 0-2
(TYPE OF ERROR)

YES

RECONFIGURE
COMPUTER
PIO TO IGNORE
ORal (ADDR
2 MISMATCH)

LENGTH

CALCULATE
NO. OF RESIDUAL 81TS
(SEE RESIDUAL
BIT CALCU-

COMPUTER
DOING
OTHER
TASKS

Figure 23 FLOW DIAGRAM OF FRAME RECEPTION

255

~
SUBTRACT
THE FLAGBITS IN THE

RESIDUAL BIT CALCULATION
THIS CALCULATION
NEEDED ONLY WHEN
RESIDUAL BITS MAY BE
RECEIVED IN A
NON-8-BIT CHARACTER

lAST RECEIVED
CHARACTER

,
ADD THE

REMAINDER
OR SUM
WITH THE
CHARACTER

BIT LENGTH

«
;?-

16
?

SUBTRACT
16 FROM

THIS SUM

T
THIS RE-

MAINDER
IS THE NO. OF
RESIO. BITS

~
Figure 23 FLOW DIAGRAM OF FRAME RECEPTION

.11

,'.:'1""AuGfl'", 'I"
~

'"'

,0"
ADDR2

I ,",'

"I""""
CONT~' 'I"
J

I' , I ""
I I I

I I l

~~
~~

o~ ~

Figure 24 TIMING DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.2)

256

~~~

FLOWCHART
INITIATE LOOP
MODE

START

~
MOM.

PORT A = OUTPUT

PORT B

(

INTERRUPT

INPUT

:~CTlV.

Wi.

CONFIGURE
PIO.

WAITE ADDRESS
INTO AR REG.
SET ADDR. COMP,
LOOP MODE,
AUTO FLAG

ADDR ----.. AR

PA,_o '" 0111 1111
PB 20 = INTERRUPT (ORal, ORaD, INTRa)

AR = 00110011
CR3 = 00000000
CR2 = 01000101

t
SET OTR

DATA TERM READY

CRt = 00000010

BIT

COMPUTER
DOING OTHER
TASKS

(

~
WAIT

)

DATA SET READY
1ST INTERRUPT

RECEl'JE DATA

(

INTERRUPT 2-N
(ACT TRAN BIT = 0,

INTEA,UPT )

(

INTERRUPT )

ADDRESS COMPARED
AND MATCHED)
ACTIVATE
RECEIVER

COMPUTER

DOING OTHER
TASKS

SEE DATA SET
READY IN
RECEPTION EXAMPLE 1
FLOWCHART

c:b

SEE TIMING
DIAGRAM FIG. 22

CRt '" 10000010
SEE A.lEIVE DATA
IN RECEPTION EXAMPLE 1
FLOWCHART

REPEATER MODE

END OF AE- )
CEIVE DATA

Figure 25 FLOW DIAGRAM OF LOOP MODE OPERATION

257

TRANSMISSION REQUEST

CRt

ACTIVATE TRANSMITTER

11100010

(SECONDARY STATION IS STILL FUNCTIONING AS A REPEATER,
RECEIVING DATA WHEN ADDRESSED, BUT IT IS NOW ALSO
WAITING FOR A GO·AHEAD f¥.TTERN FROM PRIMARY
STATION TO BE ALLOWED TO TRANSMIT)

1ST INTERRUPT
AFTER ACT TRAN BIT
IS SET, OR AFTER
END OF RECEIVE/
XMIT DATA AND ACT
TRAN BIT IS SET.

YES
OROI

SEE RECEIVE DATA
FLOWCHART IN RE·
CEPTION EXAMPLE 1

NO
ERROR

GO·AHEAD PATIERN RECEIVED.
TRANSMIT DATA

Figure 25 FLOW DIAGRAM OF LOOP MODE OPERATION
CONCLUSION

APPENDIX

The WD1931 and WD1933 devices are highly compatible.
which allows the design of a multiprotocol communications
board. This compatibility allows the use of asynchronous.
character oriented synchronous. and bit oriented synchronous communications protocols with the same 40 pin socket.

RELATED DOCUMENTS
WD1931 Data Sheet. Western Digital Corporation
WD1933 Data Sheet. Western Digital Corporation

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
Hcense is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

258

Security Products
Data Sheets

259

C=~~~~==~~==~~~====~========~~======~======~O

FEATURES
• CERTIFIED BY NATIONAL BUREAU OF STANDARDS.
• TRANSFER RATE: 1.3M BITS/SEC (2 MHz CLOCK)
(HIGHER SPEEDS AVAILABLE)
• ENCRYPTS/ DECRYPTS 64 BIT DATA WORDS
USING 56 BIT KEY WORD
• SINGLE PORT 28 PIN PACKAGE WD2001 OR DUAL
PORT 40 PIN PACKAGE WD2002
• COMMAND BIT PROGRAMMING VIA DAL BUS OR
INPUT PINS
• DMA COMPATIBLE (SEE WESTERN DIGITAL
DM1883)
• PARITY CHECK ON KEY WORD LOADING
• STANDARD 8 BIT MICROPROCESSOR INTERFACE
• INPUTS AND OUTPUTS TTL COMPATIBLE
• KEY STORED ON CHIP IS NOT EXTERNALLY
ACCESSIBLE
• SEPARATE CLEAR AND CIPHER BUS STRUCTURE
ON WD2002
APPLICATIONS
• SECURE BROKERAGE TRANSACTIONS
• ELECTRONIC FUNDS TRANSFERS
• SECURE BANKING/BUSINESS ACCOUNTING
• MAINFRAME COMMUNICATIONS

• REMOTE
TIONS
• SECURE
• SECURE
• SECURE

AND HOST COMPUTER COMMUNICA- ~
A/D
DISK OR MAG TAPE DATA STORAGE
PACKET SWITCHING TRANSMISSION

GENERAL DESCRIPTION
The Western Digital WD2001 and WD2002 Data
Encryption / Decryption devices are designed to encrypt
and decrypt 54-bit blocks of data using the algorithm
specified in the Federal Information Processing Data
Encryption Standard (#46). These devices encrypt a
64-Bit clear text word using a 56-Bit user-specified key
to produce a 64-Bit cipher text word. When reversed,
the cipher text word is decrypted to produce the
original clear text word.
The DE2001/2 are fabricated in N-channel silicon gate
MOS technology and are TTL compatible on all inputs
and outputs.

WD2001/WD2002 BLOCK DIAGRAM

261

PIN OUTS
PIN NO.

PIN NAME

SYMBOL

FUNCTION

WD2001 WD 2002
11-18

17-24

DATA LINES

DAL ~....
DAL 7

Eight active true three-state bi-directional I/O lines
used for information transfer to and from the DES
chip's registers. During single port operation, all
COMMAND/STATUS, KEY WORD and DATA WORD
transfers are via this bus. During dual port operation,
all COMMAND/STATUS, KEY WORD and clear DATA
WORD transfers are via this bus. (Cipher DATA WORD
transfers are via the CIPHER DATAP6"FiT (CDP) bus.)

N/A

11-14
27-30

CIPHER DATA PORT

CDP ~ ....
CDP 7

Eight active true three-state bi-directional I/O lines
used only in dual port operation. Cipher DATA WORD
transfers are via this bus. These pins are available on
the WD2002 40 pin package version Q.Q..Iy.

+ 12v

POWER SUPPLY

VDD

POWER SUPPLY

VCC

GROUND

CLOCK

VSS
CLK

MASTER RESET

CHIP SELECT

CS is made low to access registers within the device.

READ ENABLE

The contents of the selected register are placed on the
DAL (or COP) bus lines when CS and RE are made low.

WRITE ENABLE

Information on the DAL (or CDP) bus lines is written
into the selected DES register when CS and WE are
made low.

KEY REQUEST

This output is active high when the DES chip is
requesting that a byte of the KEY WORD be written into
the KEY REGISTER. (The KEY REGISTER is automatically addressed when KR is active, unless
overriden by A(J.)

KEY ACKNOWLEDGE

This output is active low when WE is made low while
the KEY REGISTER is addressed. (Can be used for
handshake.)

DATA-IN REQUEST

DIR

This output is active high when the DES chip is
requesting that a byte of the DATA WORD be written
into the DATA REGISTER. (The DATA REGISTER is
automatically addressed when DIR is active, unless
overriden by All.)

DATA-IN

DIA

This output is active low when WE is made low while
the DATA REGISTER is addressed. (Can be used for
handshake.)

System clock input.
MR active low resets the COMMAND/STATUS
REGISTER and resets internal circuitry. (Requires
active clock for reset operation.)

When this input is active high (during CS active) the
COMMAND/STATUS REGISTER is addressed. (A~
active high will override internally generated addresSing of the KEY and DATA REGISTERS as described
on page 6.)This input is ignored whenCRPS is active.

ACKNOWLEDGE

262

PIN NO.

PIN NAME

SYMBOL

FUNCTION

WD2001 WD2002
28

DATA-OUT REQUEST

DOR

This output is active high when the DES chip is
requesting that a byte of the DATA WORD be read from
the DATA REGISTER. (The DATA REGISTER is
automatically addressed when the DOR is active,
unless overridden by A¢.)

DATA-OUT

DOA

This output is active low when RE is made low while
the DATA REGISTER is addressed. (Can be used for
handshake.)

ACKNOWLEDGE

KEY PARITY EP'.qOR

KPE

This output is active low when enabled via the
COMMAND/STATUS REGISTER BIT 2 (KEOE) and a
parity error has been detected during loading of the
KEY REGISTER.

COMMAND REGISTER
PIN SELECT

CRPS

This input selects DAL bus or input pin programming
of the COMMAND/STATUS REGISTER. CRPS high or
open selects DAL bus programming. CRPS low selects
input pin programming.

ACTIVATE

ACT

When CRPS is high or open, this pin is an output
reflecting the status of the ACTIVATE bit (bit 1) of the
COMMAND/STATUS REGISTER. When CRPS is low,
this pin is an input that overrides the ACTIVATE bit of
the COMMAND/STATUS REGISTER.

N/A

KEY ERROR
OUTPUT ENABLE

KEOE

This output indicates the status of the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/
STATUS REGISTER. This output is active when input
pin programming is selected (CRPS low). This pin is
available on the WD2002 40 pin package version only.

ENCRYPT / DECRYPT

E/D

When CRPS is high or open, this pin is an output
reflecting the status of the ENCRYPT/ DECRYPT bit
(bit 3) of the COMMAND/STATUS REGISTER. When
CRPS is low, this pin is an input pin that overrides the
ENCRYPT/DECRYPT bit of the COMMAND/STATUS
REGISTER.

N/A

DUAL PORT SELECT

DPS

When this input is high or open, single port operation
is selected and all DES chip transfers are via the DAL
bus. When DPS is low, dual port operation is selected
and both the DAL bus and the CDP bus are used
[separate busses for clear data (DAL bus) and cipher
data (CDP bus)). This pin is available on the WD2002 40
pin package version only.,

NOTE:

The WD2001 28 pin package version does not have the following pins:
The 8 CDP pins, the KEOE pin, and the DPS pin.

263

ORGANIZATION
The Data Encryption Standard chip consists of a 56-bit
KEY REGISTER, a 64-bit DATA REGISTER, an 8-bit
COMMAND/STATUS REGISTER, plus the necessary
logic to check KEY parity and implement the NBS
algorithm. A typical system implementation is shown
on page 10 and the block diagram is shown on page 1 .
Although the DES chip interfaces to a wide variety of
processors including mini-computers, the interface is
tailored to the 8080A class microprocessor.

BIT

BIT
0

I(EY REGISTER
(lOAD ONLY)

GENERAL OPERATING DESCRIPTION

Data Register

The user programs the DES chip for encryption or
decryption, and single or dual port operation." Data is
encrypted/decrypted with a 64-bit user defined KEY
WORD. Data encrytped with a given KEY WORD can be
decrypted only using that KEY WORD. The KEY
REGISTER is loaded by the computer with eight
successive 8-bit bytes. Parity is checked on each byte
'of the KEY WORD as it is loaded into the KEY
REGISTER (The 8th bit (DAL~) of each 8-bit byte is
reserved for odd parity for that byte and is not used in
the algorithm calculation.) Similarily the DATA
REGISTER is loaded with eight successive 8-bit bytes.
The DATA REGISTER is read by reading eight
successive 8-bit bytes.
When the DES chip is programmed for encryption, the
DATA REGISTER is loaded with eight bytes of plain or
clear text. The DES chip encrypts the data, then the
encrypted data may be read from the DATA REGISTER
(64-bits of encrypted text). When the DES chip is
programmed for decryption, the DATA REGISTER is
loaded with eight bytes of encrypted or cipher text. The
DES chip decrypts the data, then the plain text may be
read from the DATA REGISTER (64-bits of plain text).
Note that all transfers to and from the KEY REGISTER
and/or DATA REGISTER must occur in eight
successive 8-bit bytes.

This 64-bit register contains plain or cipher text. When
in the encrypt mode, the DATA REGISTER is loaded
with plain text, and when read contains cipher text.
When in the decrypt mode, the DATA REGISTER is
loaded with cipher text, and when read contains plain
text. The DATA REGISTER is always read or loaded
with eight successive byte transfers. The DATA
REGISTER can be loaded only when there is a DATA-IN
REQUEST (status bit and output); similarily the DATA
REGISTER can be read only when there is a DATA-OUT
REQUEST (status bit and output).

"Note: Dual port operation available with WD2002 40
pin package version only. (Single and dual port
operation is described in detail under PART V.
OPERATION.)

BIT
63

BIT
0

DATA REGISTER

Command/Status Register (C/S R)
This 8-bit register controls the operation of the DES
chip and monitors its status. Bits 7, 6, 5 and 4 are
status-only bits (read only). Bits 3, 2 and 1 are
COMMAND/STATUS bits (read/write). Bit ¢ is not
used. The COMMAND/STATUS bits (bits 3, 2, and 1)
are normally loaded only once for an entire encrypt or
decrypt process.

7
Key Register

DOR

This 56-bit register contains the KEY by which the
Data Encryption Algorithm operates. Eight successive
bytes are needed to load the KEY REGISTER. The KEY
REGISTER can be loaded only when there is a KEY
REQUEST (Status bit and output). THIS REGISTER IS
LOAD ONLY AND CANNOT BE READ.

6
DIR

KPE

E/D

STATUS BITS
(READ ONLY)

2
KEOE

ACT

N/U

COMMAND/STATUS
BITS [READ
WRITE

COMMAND/STATUS REGISTER

264

COMr,lAND/STATUS REGISTER (CIS R)
Nomo

Bit

CIS r,;1

Function

i ,;jOT USED

. ClS 111 "' ACTIVATE

._ _ ;1-_ _ _ _ _ _.
I\EY ERROR OUTPUT ENAGLE
(I(EOE)

'i/S Fl31

ENCRYPT/ DECRYPT

<'6/0)

·C.,
.•. ·.•. . •.l.S n,l '. I(E'I REqUEST (1m)

This bil must bo S:')\ from '0' to 'I' to initiate loodino tho I(EY
REGISTER. Thie bit must bo 'I' for encryptldocrypt operation. Thlo io
a reed/vJ(llo bit .
When '0" tilo I(EY PARITY ERROR output pin fiWE) romCllnn Innctivo
rc[JQrdloss of tllO stiltun of ths I(EV PARITY ERROR bit (bit 5). Whon
'1', tho KEv PARITY E"H1T6R output pin is activo when tho I(PE bit
(bit5) ie '1'. This bit 10 Got 10 'I' upon a t,lASTER RESET. This Is a
reed/\'J(lta bit.

WhOn '0' dnto Is to b::J encrypted. WI.lon '1' dala 10 to bo decrypted.
This 10 n reed/wilo bit.

th
progrcmm~cl from 'I' to '0' (i.o., Chip
decctivBted). This is a rond··
only bit.

lThlobltls sot upon eithor;
olc;ompletlon 01 ItEY REGISTER.lo:.ldinO· or·
b)Complotion of DATA REGISTER reading die, tho fcstDATi-\-9U'ti
REQUEST llosbC,lO sOfVlc~d by an8-byte read and tho[)~TA
REGISTER 10. nOl'1 omptyqnd ready lobe loaded· with' tho !\e.lt.f
DA~AWORD). . . . .
.! i
IfisreOGI uponlonding 01 the 81h and final byle oUhe DATA:;
~EGISTER. This Is a road only bit.
Thi"bll ie sat upon completion of the internnl encryPtldacl)lp\;c
.calculatlon of (I DATA WORD. It 1(1 resatupon reading of the 8th and
flnalbylo of tho DATA REGISTER. This is a raad only bit.

Noto: All bits of the COMMAND/STATUS REGISTER are reset to '0' upon MASTER RESET, except bit 2 (KEOE)
which is set to '1' and bit !i1(not usedlwhich will read 'I' by default during a COMMAND/STATUS REGISTER
read.

265

DETAILED OPERATING DESCRIPTION
The DES chip is initiated by programming a '1' in the
ACTIVATE bit of the COMMAND/STATUS REGISTER.
The DES chip will respond by activating the KEY
REQUEST (KR) bit (bit 4) of the STATUS REGISTER
and the KEY REQUEST output.
The user must deactivate A~ (allowing the chip to
internally address the KEY REGISTER), and load the
KEY REGISTER with the 64-bit KEY WORD. The KEY
REGISTER is loaded with 8 consecutive 8-bit bytes by
activating WE 8 times (with CS active).
When WE is made active, the DES chip deactivates the
KR output. When WE is deactivated, the KR output is
again activated. The DES chip will activate 8 KEY
REQUESTs in this fashion until the KEY REGISTER is
full.
Also, when WE is made active, the DES chip responds
by activating the KEY ACKNOWLEDGE (KA) output.
Thus, 8 KA activations will be made.
The KR and KA outputs can be used for asynchronous
handshaking (as in DMA control) or further activations
following the first KR can be ignored and the KEY
REGISTER can be loaded in a synchronous (programmed 110) manner via 8 successive activations of
WE.
Each byte of the KEY WORD is checked for odd parity
as it is loaded. If a parity error is found, the chip will
set the KEY PARITY ERROR (KPE) bit (bit 5) of the
COMMAND/STATUS REGISTER. If the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/
STATUS REGISTER has been set, the DES chip will
also activiate the KPE output. The KPE bit will be reset
when the ACTIVATE bit is re-programmed to a '0'.
After loading the last (8th) byte of the KEY WORD into
the KEY REGISTER, the DES chip will set the DATA-IN
REQUEST bit (bit 6) of the STATUS REGISTER and
activate the DATA-IN REQUEST (DIR) output. The
64-bit DATA WORD must then be loaded into the DATA
REGISTER. The DATA REGISTER is loaded in the same
manner as the KEY REGISTER via 8 successive
activations of DATA-IN REQUEST (DES output), WE
(DES input, and DATA-IN ACKNOWLEDGE (DES
output).
After the last (8th) byte of the DATA WORD has been
loaded, the chip begins the internal calculation of the
NBS algorithm. Upon completion of the calculation,
the new data is internally loaded into the DATA
REGISTER, and the DES chip sets the DATA-OUT
REQUEST bit (bit 7) of the STATUS REGISTER and
activates the DATA-OUT REQUEST (DOR) output. The
DATA WORD must then be read from the DATA
REGISTER. The DATA REGISTER is read in the same
manner as it was loaded via 8 successive activations of
DATA-OUT REQUEST (DES output), RE (DES input),
and DATA-OUT ACKNOWLEDGE (DES output).

Again, for both data-in and data-out, further
activations of the DIR, DOR and DIA, DOA outputs,
after the first request, can be ignored and the DATA
REGISTER loaded (read) by 8 successive activations
of WE (RE).
After the last (8th) byte of the DATA REGISTER has
been read, the DES chip will reactivate the DATA-IN
RECUEST. This cycle of loading the DATA REGISTER,
internal algorithm calculation, and reading the new
data from the DATA REGISTER can continue indefinitely until all desired data has been encrypted or
decrypted with the current KEY WORD.
After all desired data has been encrypted/decrypted
with the current KEY WORD, the ACTIVATE bit of the
COMMAND/STATUS REGISTER should be programmed to '0'. When the ACTIVATE bit has been reset to
'0', an unauthorized user will not have access to the
last KEY loaded into the DES chip since to resume
operation, the ACTIVATE bit must be programmed to
'1' which activates KEY REQUEST and a new KEY must
be loaded before access to the DATA REGISTER is
possible.
To encrypt plain data, plain data is loaded into the
DATA REGISTER, and encrypted data is read from the
DATA REGISTER. (The ENCRYPT/DECRYPT bit (bit 3
of the COMMAND/S,ATUS REGISTER) must have
been previously programmed to '0'.)
To decrypt encrypted data, encrypted data is loaded
into the DATA REGISTER, and plain data is read from
the DATA REGISTER. (The ENCRYPT/DECRYPT bit
must have been previously programmed to '1 '.)
Note: If it is desired to switch from encrypt to decrypt
(or vice versa) under the same KEY WORD, this
can be accomplished before a DATA WORD
transfer is initiated. By making A~ high, the
DES chip will override the internal addressing of
the DATA REGISTER, and address the COMMAND/STATUS REGISTER. The COMMAND/
STATUS REGISTER can be re-programmed.
When A~ is returned to a low state, the
DES chip will internally address the DATA
REGISTER awaiting loading of the next DATA
WORD.
DUAL PORT OPTION
(Available on WD2002 40 Pin Version Only)
When the DUAL PORT SELECT (DPS) input is high or
left open (ie., single port operation is selected), all
transfers to/from the DES chip are via the DAL bus.
The CDP bus is not used and remains three-stated.
When DPS is made low (ie., dual port operation is
selected), all transfers to/from the COMMAND/
STATUS REGISTER, and transfers to the KEY
REGISTER are still via the DAL bus. Clear DATA
WORDS are also transferred via the DAL bus. However,
cipher DATA WORDS are now transferred via the CDP
~This provides separate busses for clear and
ciphered text.

266

Encryption during dual port operation requires loading
clear data via the DAL bus, and reading cipher data via
the COP bus.
Decryption during dual port operation requires loading
cipher data via the COP bus, and reading clear data via
the DAL bus.

COMMAND SELECT OPTION
When the COMMAND REGISTER PIN SELECT (CRPS)
input is made low, the ACT and EfD pins are
enabled as inputs. These inputs override bits 1 and 3
(respectively) of the COMMANDfSTATUS REGISTER.
This allows input pin control of the DES chip. The
KEOE bit (bit 2) of the COMMANDfSTATUS REGISTER
will be held to '1 '.
Input A¢ will be disregarded in this mode of operation,
and the COMMANDfSTATUS REGISTER cannot be
accessed via the DAL lines.
Note that the ACT pin must be toggled from '1' to a '0'
to clear a parity error detection in this mode of
operation.
All other operation remains as described previously.

WD2001lWD2002 FLOW CHARTS

267

MAXIMUM RATINGS
Storage Temp. Ceramic-65'Cto +150'C
Plastic -55' C to + 125'C

VDD with Respect to VSS (Grou nd)
+15 to - 0.3V
Max. Voltage to any Input with Respect to VSS +15 to - 0.3V
Operating Temperature
O'C to 70'C
Power Dissipation
1W
OPERATING CHARACTERISTICS
TA
O'C to 70'C, VDD
+ 12.0V

SYMBOL

± .6V, VCC

CHARACTERISTIC

5.0V

± .25V, VSS

MIN.

TYP.

= OV
MAX.

UNITS

11..1
II..()

Input Leakage
Oulpull.eakllge

ICCAVE

VCC$upplYC\.Itronj

rnA

IOOAVE
VIH

VOO SupplyCurront
Input HlghVOl1ago

rnA
V

CONDITIONS

VIL

10= -100ull:

VOH

VOL

Output Lo\VVoftago

AC CHARACTERISTICS
TA
O'C to 70'C, VDD

= +12.0V ± 0.6V,

VSS

= OV, VCC = +5.0 ± .25V

NOTE: All output timing specifications reflect the following: High Output 2.0V
Low Output 0.8V

268

1.6lnA

KR(DIR)

:4- TOH
DALlCDPI

YPICAL KEY OR DATA REGISTER LOAD

DOR

cs
DALlCDPI _ _ _ _-'K

""
"

TYPICAL DATA REGISTER READ & TIMING

-<;
~
T ACS

OAL
(COP)

-fIo-l

T RD

---r.-j--«I
I

TRDV

--+-:

•

I :.- TACH

!~
I

l.- -.1:"--

----i

OAL
(COP)

--+--,-----~-4-TOH

ClK
+ 450 nsec from WE
into the DATA REGISTER.

MISCEllANEOUS TIMING
1. CLOCK INPUT
FREQUENCY: 2 MHZ (MAX); 100 KHZ (MIN).
PULSE WIDTH: 250 nsec MIN.
2. MASTER RESET PULSE WIDTH: 10 Clock Periods
3. Time between consecutive RE or WE pulses:
TSR = TSW = 2 CLOCK PERIODS MINIMUM
4. ACT, EID, KEOE OUTPUTS
These pins will be valid within 2 ClK
+ 450 nsec
from WE
of a COMMAND REGISTER write
operation.

5. KPE OUTPUT
This pin will be active within 2 ClK
+ 450 nsec
from WE
of a write of a KEY WORD byte that
results in a parity error.

6. CRPS, DPS, EID INPUTS require a 300 ns set-up
time.
7. The initial KR activation will be valid within

t
t

3 ClK
+ 450 nsec from WE
of a write
operation that programs a '1' into the COMMAND
REGISTER ACTIVATE bit (or 2 elK
+ 450 nsec
,if CRPS = 0).
from ACT input

8. The initial DIR activation will be vatid within 2
ClK
+ 450 nsec from WE
of the 8th write
into the KEY REGISTER.

9. The initial DOR activation will be valid within 49

10. When reading the DATA REGISTER (in response to
DOR), subsequent data bytes are made available
internally to the DAl (CDP) output buffers within
2 ClK
+ 450 nsec from RE •

NOTE: All output timings assume ClOAD

Shown below IS a block diagram for a floppy disk based
DES secure smart terminal. The Direct Memory Access
(DMA) controller optimizes data transfer operations for
not only the floppy but also for file encryption and
decryption operations. Secure features for the terminal
include: secure file storage on floppy disks, optical
clearl secure transmission via the communications 1/0
and battery backup of the Terminal 10 key.
Tampering with the Terminal by unauthorized persons
either through the key board power supply interrupt
interlock or attempting to open the service panel
results in memory scrambling and terminal 10 key
destruction. Finally, a hardware option was also
included to allow the use of the pin compatible
WD1933 device in place of the WD1931 for bit oriented
SDlC, HDlC, or ADCCP protocols.

DES

I
OM1883

DMA

cPU

PWR SUPPLY &
BATTERY

FD1791

SYSTEM
CLOCK

CRT
CONTROLLER

FOe

FLOPPY
DISK
DRIVE

WD1931

f------+

SYNC!ASYNC Ito
WD1933
SOLe/HOLe/ADcep

50 PF

TYPICAL APPLICATION

WD2001

MEMORY

of the 8th write

KEY BOARD

I
Block Diagram: Secure Smart Terminal

270

MODEM

---

WD2001E CERAMIC PACKAGE

2.025

LI:t(

MAX

WD2001F PLASTIC PACKAGE

" [::::0:::::]

.015
",

MIN

.200~
..
'I1:
r"--~ II H III1111 H I Hili· ...

%~~ ~.t:

.014

~r- :021

+1 ~ ~in

:,
MIN

WD2002A CERAMIC PACKAGE

WD2002B PLASTIC PACKAGE

EXPORT CONTROL: Cryptographic devices and technical data regarding them are subject to Federal Government export
controls as specified in Title 22, Code of Federal Regulations. Parts 121 through 128.

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

271

WESiiERN DIGITAL

WDK20001-XA CRYPTOGRAPHIC PRIMER Kn
FEATURES

.,
'"

NIQUES AND HOW TO IMPLEMENT THEM
o EXAMPLES TO HELP CHECK OUT USER SOFTWARE

o RS-232 COMPATIBLE CRYPTOGRAPHIC UNIT WITH:

..:

:;:

o WD2002 CERTIFIED IMPLEMENTATION OF
THE NATIONAL BUREAU OF STANDARDS
DATA ENCRYPTION STANDARD
GENERAL DESCRIPTION
o SELECTABLE
19.2KBPS)

BAUD

RATE

(50BPS

" CABLE TO HOOK DIRECTLY TO AN RS-232
COMPUTER PORT
o LED DISPLAY FOR CRYPTOGRAPHIC STATUS AND ERROR CONDITIONS
" CRYPTOGRAPHtC PROTOCOL
o USER MANUAL FOR HARDWARE
o MANUAL

DESCRIBING

CRYPTOGRAPHIC

TECH-

The WDK20001-XA provides a basic cryptographic unit
with a standard RS-232 1/0 interface. The user accesses the
cryptographic unit as a programmed I/O device operating at
a switch selectable baud rate between 50bps and 19.2Kbps.
Guidance for writing applications programs to communicate with the cryptographic unit through a cryptographic protocol and for using it to perform cipher feedback and other
cryptographic imptementations is included in the Cryptographic Primer manual. Specific examples of matched key,
plaintext and ciphertext are included to help debug the users
application programs.

JJ
LJ
Interface

CRYPTO~BUS

Power
Supply

Status
Display

Error
Display

WDK20001-XA
CRYPTOGRAPHIC PRIMER KIT BLOCK DIAGRAM

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

273

[5
a:

o THE "CODEBREAKERS" BY DAVID KAHN

& SWd

Security Products
Technical Notes

275

C~lP'lHIfE~ flElElOll8lAC~ CIFfVIPTOGIRlAfP>HV
TfECIHlNJ~CAl NOlIE

by Ken Cohen

1ii

CIPHER FEEDBACI< CRYPTOGRAPHY
The Uniled States Government in proposed Federal Standard 1026 describes three different approved ways of using
the National Bureau of Standard's Data Encryption Standard
(DES): Electronic Codebook; Cipher Feedback; and Cipher
Block Chaining. Western Digital's WD2001 and WD2002, as
delivered, implement the DES in Electronic Codebook Mode.
This Technical Note will describe how to build an "N" bit
Cipher Feedback (CFB) circuit using the WD2001.

WHAT IS CIPHER FEEDBACK?
Cipher feedback cryptography produces, as a function of
previous cipher text, a pseudorandom bit stream which is
added modulo 2 to the plain text to produce the next cipher
text.

DES IN CIPHER FEEDBACI< (CFB)
Obviously, both the receiver and transmitter must start their
cryptographic operation with the same cryptographic keys to
be able to acquire and maintain crytographic synchronization, i.e. produce the same pseudorandom bit stream at the
same point in time.
For DES this means that both the 64 bit cryptographic variable (56 bit key) and the initial input to the algorithm must be
identical at both ends. The initial input to DES in CFB is
called the Initializing Vector (IV). Its format and generation
are described in detail in Federal Standard 1026.
The functional description of using the WD2001 in CFB
mode below assumes that communication synchronization
has been achieved; that identical decrypted IV's and cryptographic keys are available to both the transmit and receive
ends of the linl<; that encryption is to be.a 1 bit cipher feedback; and that the plain text character size (1 in the example)
equals the transmitted character size (Method A in proposed
Federal Standard 1026).
ENCRYPTION
At time 0, the 64 bit cryptographic variable is loaded into the
WD2001 with the key load sequence. A 64 bit block consisting of not more than 16 leading O's and the 48 bit (or longer)
IV is loaded into a 64 bit shift register (R) and into the input
register, as if it were data, and encrypted. The WD2001 will
automatically encrypt the IV under control of the cryptovariable and present a 64 bit block, 8 bits at a time as output.

This output is stored in a shift register(S) with the most significant bit (MSB), to the left and the least significant bit on ~_
the right.

ii:
~

::>
0::

The MSB of S is added modulo 2 to the first bit of plain text
to produce the first cipher bit. The contents of R are shifted
1 bit to the left and the just created cipher bit is inserted as
the least significant bit (LSB) in R. The cipher bit is nowavailable for buffering, transmission, etc.
The new contents of R are now loaded into the WD2001 as
data, encrypted, and the new output placed in S.
The above procedure is repeated until the entire message
text is encrypted, one bit at a time.

DECRYPTION
Decryption is accomplished in a similar manner: the IV is
stored in R; loaded into the WD2001 as data; ENCRYPTED
(even though the operation on the message text is to be
decrypted); the results stored in S; and R shifted 1 bit to the
left. Now, because the unit is receiving cipher rather than
creating it, the first received bit is placed in the LSB of R. This
cipher bit is also added, modulo 2, to the leftmost bit in S to
reproduce the original plain text.

NOTES
Of particular significance is that the DES Chip is in the
ENCRYPT mode for CFB cryptography regardless whether
the operation is to be performed to create cipher text or to
recreate plain text. This is because the DES is being used to
generate a pseudorandom bit stream. It is the exclusive OR
operating on that bit stream and the received text which
accomplishes the actual encryption/decryption of data.
S was nominally defined to be 64 bits long. It need be no
longer than the number of text bits to be exclusive OR'd at
one setting of the pseudorandom stream. In the example it
was one bit. In reality it could be any character or block size
from 1 to 64 bits long.
The convention used in this note is to organize a shift register
with the MSB to the left. In practice, what is important is to
use the MSB of S for the MOD 2 addition and to shift the R
register content, so that the MSB is dropped and the cipher
bit becomes the LSB. It is also important to perform the shift
and generate a new pseudorandom block after each character has been encrypted or decrypted.

277

ffi

LL-

OTHER CIPHER FEEDBACK METHODS

APPLICATIONS OF CFB

Cipher Feedback can be done for any feedback size of 1
through 64 bits. One bit cipher feedback has the overall advantage of being transparent to the data being protected.

In the data communications world error extension and selfsynchronization are not important because of the excellent
conditions of the lines and the protocols and error correcting
codes used to insure proper receipt of data. In some appl ications, these properties of CFB cryptography can be tumed
to the user's benefit. This is especially true in situations
where the data stream contains highly redundant information, where an incorrect recovery of 64 bits is hardly
noticed-particularly when compared with the overall communications benefit of having the cryptography automatically
resynchronize itself.

CHARACTERISTICS OF CFB
CFB has two properties which must be considered when selecting it for data encryption: 1) error extension and 2) self
synchronization. Both of these properties exist because the
encryption process synchronizes on the received cipher to
produce the pseudorandom bit stream.

WD2001 CHARACTERISTICS IN CFB
In the case of DES in one bit CFB, a one bit error in the received cipher message will affect the next 64 pseudorandom
blocks-it will take 64 iterations to shift the one "bad" bit out
of the 64 bit register above. If 8 bit CFB is used, then only 8
blocks will be affected, but that will still represent 64 bits used
to decrypt incoming data.

In the same way, receiving 64 consecutive good bits of
cipher will have filled the data-in register on the receiver end
with the same 64 bits of data as in the transmit unit and
proper decryption can again take place, assuming both ends
have the same cryptographic key. This is what is meant by
self-synchronizing.

WESTERN DIGITAL
CORPORATION

The WD2001 is rated as having 1.304 megabits per second
throughput when driven by a 2 MHZ clock. This figure is
based on processing 64 bits of data at each operation. Using
the WD2001 in an 8 bit cipher feedback circuit will reduce
that to 163 kilobits per second. A 1 bit cipher feedback circuit
would further reduce effective throughput to 20.385 kilobits
per second. This is true of any DES implementation. The algorithm is designed to process 64 bits of plain (cipher) text at
a time to produce 64 bits of cipher (plain) text; cipher feedback is designed to operate on a basic character size and
shift after that character has been encrypted. In the 1 bit
case, the user "throws away" 63/64ths throughput capacity
for each encryption.

3128 REDHlll AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

278

Security Product:
AppUcations Note

279

W[D20!ll~/2 AL9J~U(cAT~OU\1S ~OT[E

&'OU\11E

l8J~T C~L9JH[E~ flElE[D)l8JAC~( ~U\1

SVU\1(c~~0U\10US

SVSTIEM"

By Michael D. Garvey

>="

II:

INTRODUCTION

WD2001/2 TIMING REQUIREMENTS

The WD2001/2 Data Encryption device interfaces easily to
both microcomputer and hard-wired logic circuits. This Applications Note provides suggestions for the implementation
of a synchronous circuit to perform system timing in a one bit
cipher feedback application.

The WD2001/2 may be operated from a 2 MHZ clock. This gj
provides a fundamental time period of 500 nSec that easily ~
fits into the timing requirements for the device. For example,
the minimum pulse width for a read (RD) or write (WR) pulse
is 450 nSec.

SYSTEM TIMING CONSIDERATIONS

Generation of the RD or WR pulse can be directly obtained
from a synchronous device that transitions at each edge of
the synchronous clock (SYNCLK). Figure 1 illustrates the
timing relationship between SYNCLK and RD or WR.

The synchronous operation of a digital circuit often leads to
both minimal hardware count and simple, easy to understand
timing relationships. In addition, the concern over individual
device characteristics become non-critical through the use
of a worst case design approach. Common problems such

Once the timing relationship is understood, the implementation becomes quite straightforward. The circuit of Figure 2
suggests a possible method of RD or WR generation.

as race conditions and temp,erature sensitivity can be vir-

tually eliminated by synchronizing all logical events to a well
defined clock edge.

500
NSEC

PERIOD

1_
I

(2MHZ)
SYNCLK

STATES

T2 _ _ _ _------'

T3--,L__________~,----,L

______

Figure 1 SYNCLK, RD, AND WR TIMING RELATIONSHIPS.

281

,5V

RIPPLE OUT
ENABLE T
ENABLE P

SYNCLK

CLOCK

2.2K

LOAD
SYNCHRONOUS
COUNTER

74163

QS
QC

CLEAR

T STATE

COUNTER STATE

RDORWR

Figure 2 RD AND WR TIMING GENERATION

FUNDAMENTAL TIMING SEQUENCES
Any cryptographic implementation using the Data Encryption
Standard (DES) can be broken down into four fundamental
timing sequences. First, the key is loaded into the WD2001/
2 (Load Key). Second, the data to be encrypted or decrypted
is loaded into the device (Load Data). Next, the DES is executed. Finally, the result of the DES is unloaded from the
WD2001/2 (Unload Data). Figure 3 lists the timing requirements for each timing sequence.

The Load Key, Load Data, and Unload Data sequences are
highly similar. Figure 4 shows the logical flow associated
with the Key Load or Data Load, or Data Unload. The Data
Encryption Algorithm sequence can be derived from the timing associated with the other three sequences. For simplicity,
the DES timing is accomplished by counting groups of three
clock periods in a fashion similar to the method shown in
Figure 4. The logical flow for the DES timing is shown in Figure 5.

TOTAL

SEQUENCE

NUMBER OF CLOCK PERIODS

Load Key

8 bytes x 3 clocks

Load Data

8 bytes x 3 clocks

DES

17 x 3 clocks

Unload Data

8 bytes x 3 clocks

Figure 3 FUNDAMENTAL TIMING SEQUENCES

282

) -_ _ _ _ _ DONE

DONE

Figure 4 KEY LOAD, DATA LOAD,
AND DATA UNLOAD FLOW

Figure 5 DES LOGICAL FLOW

and also highlights the three I/O operations. Note that the
Key Load sequence is outside of the tight loop.

SYSTEM TIMING OVERVIEW

The normal operation of a cryptographic system would require three classes of inpuVoutput (I/O) operations with the
WD2001/2. First, the key is loaded (Key Load) through eight
consecutive write cycles. Second, the data to be encrypted
or decrypted is loaded (Load Data) in a similar lashion. After
the Data Encryption standard is completed, the data is unloaded (Unload Data) through eight consecutive read cycles.
Typically, the Key Load sequence would occur much less
frequently than the Load Data or Unload Data sequences.

Using the four fundamental timing sequences as logical
building blocks, a functional block diagram of system timing
can be designed. Figure 7 illustrates the overall system timing functions.
An implementation of the functions shown in Figure 7 is suggested in Figure 8. Note that all timing transitions are synchronous with the rising edge of SYNCLK.
Figure 9 details the timing of the Load Key sequence, and is
similar to the Load Data, Unload Data, and DES, sequences
also.

The flow diagram of Figure.6 shows the relationship between
the four fundamental timing sequences defined previously,

283

110

I/O

DONE

YES

Figure 6 FUNDAMENTAL TIMING SEQUENCES INTERRELATIONS

CONTROL LOGIC

(8 x 3)

T1. T2, T3

STATE
GENERATOR

(17 x 3)

(8 x 3)

jI
AD

GENERATION

(

WA
GENERATION

I 11
DES
COUNTER

Figure 7 SYSTEM TIMING BLOCK DIAGRAM

284

1. KEYLOAD RQ AND DATA RQ DO NOT OCCUR
SIMULTANEOUSLY.
2. ALL J·K PRESETS TO ... 5V
3. ALL J·K CLEARS TO "RESET".
4. RESET SHOULD LOAD ALL 74LS163 COUNTERS

Figure 8 SYSTEM TIMING IMPLEMENTATION

"'~'t,~=""

fCLK)T1

11)

mco"~

IQ)

KEYON

12)

18)

~r-------------Ji(---------------,~1~

1<,

SYNCLK

Figure 9 SINGLE KEYLOAD SEQUENCE

285

ONE BIT CIPHER FEEDBACK
The one bit cipher feedback (OBCFB) architecture is widely
used in Data Communications. The WD2001/2 device, when
operated with a 2 MHZ clock, will run at an effective bit rate
of over 19,200 bits/second, which is the practical upper limit
of many communications links.
FUNDAMENTAL LOGICAL COMPONENTS OF OBCFB
A one bit cipher feedback system can be broken down into
nine logical components, as listed in Figure 10.

NAME

DESCRIPTION

KEY

56 bit number that maps INV to OV

Initialization Vector

INV

Input Vector

DES

Data Encryption Standard

Output Vector

SDI

Serial Data In

SDO

Serial Data Out

Shift Register (used with INV)

MOD2

Modulo 2 Adder

encryption process to be accomplished with discrete blocks
of data, and hence the WD2001/2 can be used in a multichannel communications environment.
In OBCFB, the WD2001/2 is always set to encrypt mode.
The selection of either the SDI as the feedback element to
the shift register, or the SDO as the feedback element, determines whether the incoming data is encrypted or
decrypted.
Another factor involved with OBCFB is the propagation of errors through a 64 bit block of data. Because of the 64 bit shift
register that feeds the INV, a Single bit error will cause the
following 63 bits to be in error also. After the last bit of the 64
erred bits, the data will become resynchronized and the effect of the shift register will no longer cause bad data.

msb

DES (WD2001/2)

Figure 10
NINE FUNDAMENTAL COMPONENTS OF OBCFB

______________-+__

Adder

Figure 11 OBCFB ENCRYPTION BLOCK DIAGRAM

msb

DES (WD200112)

To decrypt, the operation is changed in one way. Instead of
feeding the result of the modulo 2 adder to the shift register,
the unmodified serial data is used. All other operations are
identical. Figure 12 shows a circuit which supports both encryption and decryption.
Because the OBCFB algorithm uses a 64 bit shift register on
the INV, each SDO bit is a function of ~s corresponding SDI
bit and the 64 previous operations. This implies that the past
history of the encryption operation is necessary to initialize
a system. The IV is used to supply the history required to allow immediate use of the OV from the DEA. Typically, the IV
is either a predefined value, or the last 64 SDO bits from the
data stream being encrypted or decrypted. This allows the

SDO

Modulo 2

FUNCTIONAL DESCRIPTION OF OBCFB
The OBCFB algorithm operates on a one bit wide data input,
hence it is ideally suited to serial Data Communications applications. In encryption mode, the serial data in is added
modulo 2 with the most significant bit (msb) of the 64 bit output vector. The result of this operation is then fed into the
least significant bit (Isb) of a 64 bit shift register, and also is
used as the serial data output. The shift register is then
shifted from the Isb to the msb, and the result becomes the
next input vector. After the Data Encryption Standard is
completed, the process is repeated again for the next single
bit of serial input data. Because each serial data bit requires
an entire 64 bit INV and OV, the effective bit rate of this operation is 64 times less than that of a operation which uses
all 64 bits of the OV, such as Code Book. Figure 11 shows a
block diagram of a OBCFB circuit operating in encryption
mode.

SDr

SDO

SDO if ENCRYPT
SDr if DECRYPT

Figure 12
OBCFB ENCRYPTION/DECRYPTION BLOCK DIAGRAM

286

ONE BIT CIPHER FEEDBACK IMPLEMENTATION

Digital FR1502 FIFO and some common TTL logic.

Since the WD2001/2 is a byte input'output oriented device,
the implementation of a OBCFB circuit can be accomplished
without the 64 bit shift register shown in Figures 11 and 12.
Through the use of a 9 bit wide FIFO, a "virtual" 64 bit shift
register can be built. Figure 13 illustrates this with a Western

Once the modulo 2 adder, the encrypt'decrypt selector, and
the shift register are defined, the overall circuit can be generated by combining these pieces along with the logic shown
in Figure 8. The overall block diagram of the one bit cipher
feedback system is given in Figure 14.

WRON· T2

R-O-ON01

,"0

'"'
'"'
'"0

ORO

0"'

I
SR

ORO

C
D

OR5

IRe

ORG

IR'

0",

IRa

ORa

IR,
DEVICES

2' MUX

OR'

FR1S02

I"'

OTHER

500 ON WR,,7

74LS2S9

FIFO

WRON~'~

A
WRON

WRON. TI

-""-

OPERATION
UNLOAD SHIFT REG

(msb)

05 04

(Isb)

OPERATION

LOAD FIFO FROM W

NDQP

NDOP

LOAD SHIFT REG FROM FIFO

SHIFT RIGHT

WD2001/2

VIRTUAL" 64 BIT SHIFT REGISTER

Figure 13 "VIRTUAL" 64 BIT SHIFT REGISTER

287

ENCRYPT/DECRYPT

WR #7

2: 1
MUX

2: 1

MUX

SOl _ _ _.......~

SOD

FR1502
FIFO

07, MSB

T1
T2
T3

SYSTEM

RO #1 (MSS)

TIMING
WR #7 (LSS)

WD2001/2

Figure 14 OBCFB SYSTEM BLOCK DIAGRAM

CONCLUSION

RELATED DOCUMENTS

The WD2001/2 device lends itself readily to the most common of all Data Communications encryption techniques. The
one bit cipher feedback algorithm can be implemented easily
through the use 01 synchronous timing generation and circuit
design techniques.

WD2001/2 Data Sheet, Western Digital Corporation
FIPS 46
Federal Information Processing Standard
National Bureau Of Standard
Department of Commerce

EXPORT CONTROL: Cryptographic devices and technical data regarding them are subject to Federal Government export controls as specified
in Title 22. Code of Federal Regulations. Parts 121 through 128.

Inforrnatton furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by impltcation or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

288

~®'Ih0J(Q)rr~ ~rr@~OJJ©'[k~

[Q)©J'[k©J ~[h)®®'[k~

289

WESTERN
DIGITAl..
p
A
R
R
T

LSI PACKET NETWORK INTERFACE WD2501/11
SHORT FORM DATA SHEET
if

FEATURES
• Packet Switching Controller Compatible with CCITI
Recommendation X.2S, Level 2, LAP.
• Programmable Primary Timer (T1) And Retransmission Counter (N2)
• Programmable A-Field Which Provides A Wider
Range Of Applications Than Defined By X.25. These
Include: DTE-To-DTE Connection, Multipoint, And
Loop-Back Testing
• Direct Memory Access (DMA) Transfer: Two
Channels; One For Transmit And One For Receive.
Send I Receive Data Accessed By Indirect Addressing
Method. No External Address Latches Required.
Sixteen Output Address Lines.
• Zero Bit Insert And Delete
• Automatic Appending and Testing Of FCS Field
• Computer Bus Interface Structure: 8 Bit BiDirectional Data Bus. CS, WE, RE-Four Input
Address Lines
• DC To ·1.6M BitslSEC Baud Rate

• TTL Compatible
• 48 Pin Dual In-Line Packages
• Pin-for-pin compatible with WD2511 (LAPB.)
Higher Baud Rates Available By Special Order

:;;

.c
E

a..

APPLICATIONS
X.25 PACKET SWITCHING CONTROLLER
PART OF DTE OF DCE
PRIVATE PACKET NETWORKS
GENERAL DESCRIPTION
The WD2501 is a MOS I LSI device which handles
bit-oriented, full-duplex serial data communications
with DMA, which conforms to CCITT X.25 with
programmable enhancements.
The device is fabricated in N-Channel silicon gate MOS
technology and is TTL compatible on all inputs and
outputs.

·A detailed long form data sheet for this product is available from your local Western Digital Representative.

291

(/I

WD 2501 BLOCK DIAGRAM
•

INTERFACE SIGNAL DESCRIPTION

'PIN
NUMBER

SYMBOL

FUNCTION

NAME

VCC

Power Supply

+ 5VDC power supply input

VDD

Power Supply

+ 12VDC power supply input

VSS

Ground

ClK

Clock

Clock input used for internal timing. Must be square
wave from 1.0 to 3.0 mHz.

Master Reset

Initialize on active low. All registers reset to zero,
except control bits MDISC and LINK are set to 1. DACK
must be stable high before MR goes high.

Chip Select

Active low chip select for CPU control of 110 registers.

Data Access Lines

An 8 bit bi-directional three-state bus for CPU and DMA
controlled transfers.

Read Enable"

The contents of the selected register are placed on DAl
when CS and R E are low.

Write Enable

The data on the DAl are written into the selected
register when CS and WE are low. RE and WE must not
be low at the same time.

An active low output to indicate that either a CS·WE or
CSoWinput is present.

Interrupt Request

An active low interrupt service request output, and
returns high when Status Register #1 is read.

8-15

DALO-DAl7

47-44

IAO-IA3

Address Lines In

Four address inputs to the 2501 for CPU controlled
read/write operation with registers in the 2501. If ADRV
= 0, these may be tied to AO - A3.

26-41

AO-AI5

Address Lines Out

Sixteen address outputs from the
operation. If the control bit ADRV is 1,
TTL drives at all times. If ADRV is 0,
3-state, and are HI-Z whenever DACK
is in Control Register #1.)

DMA Request Read

2501 for DMA
the outputs are
the au puts are
is high. (ADRV

An active low output Signal to initiate CPU bus request
so the 2501 can output onto the bus.

292

·PIN
NUMBER

SYMBOL

PIN NAME

FUNCTION

DMA Request Write

An active low output signal to initiate CPU bus request
so that data may be written into the 2501. DROW and
DROR cannot be low at the same time.

DMA Acknowledge

An active low input from the CPU in response to DROR
or OROW. OACK must not be low if CS and RE are low
or if CS and WE are low.

Transmit Data

Transmitted serial data output

Receive Data

Receive serial data input

Transmit Clock

A 1X clock input. TO changes on the falling edge of TC.

Receive Clock

This is a 1X clock input, and RO is sampled on the
rising edge of RC.

Adjustment of the sample is by quadrant.
sampling may be monitored by the RCO output.

The

Request-To-Send

An open collector (drain) output which goes low when
the 2501 is ready to transmit either flags or data. May
be hard-wired to ground.

Clear-To-Send

An active low input which signals the 2501 that
transmission may begin. If high, the TO output is
forced high. May be hard-wired to ground .

• PIN NUMBERS ARE PRELIMINARY
•• Throughout this document, the term "read" refers to data out of the 2501 and "write" refers to data going
into the 2501.

293

MODEM
CONTAOLS

SYSTEM CONNECTION

I+----I.FIELO(PACKETOATAI-----+I

t,:::~:::'
WDB2~'

:1 ,,,emu ~AWU~"ON'OHW'"
•

OMA ACCESSED - - - - - - + I

According 10 tile X.25 protocol, there a,.. Ih''''' 'vpes 01 I,ames: su""IYlsory (s·rrame), unnumbered
(U·I .... m.J. and inlo,malion (I-Irame). All S· and U·'ramu ar. ger>eraled and lesled by 1he 2!!oOI. The
user's CPU handles only tile '·lleld of H,.me!. which
packel •.
NOTE: X.:ZS level 1 IS '1'>1 phy.lcallnt,<1_.

.r"

FRAME FORMAT CONTROL
The WD2501 is controlled and monitored by sixteen I/O registers.
Control, status, and error bits will be referred to as CA, SA, or EA, respectively, along with two digits. For example,
SA16 refers to status register #1 and bit 6, which is "XBA".
REG.#
0
1
2

4
5

IAJ
0
0
0
0
0
0

IA2
0
0
0
0
t
1

IAl
0
0
t
t
0
0

lAO
0
1
0
t
0
t

6
7

0
0

1
1

t
t

0
t

8
9

t
1

0
0

0
t

Tl
N2ITt

A
B
C
D

t
1
t
t

0
0
t
t

1
t
0
0

0
t
0
t

TLOOK Ht
TLOOK LO
CHAIN/LIMIT
(UNUSED)

E
F

t
t

0
t

XMT COMMAND "E"
XMT RESPONSE "F"

'CPU AEAD ONLY. (Write not possible)

294

RECEIVER
MONITOR
TIMER

DMA SET·UP

"A" FIELD

CONTROL,STATUS,ERROR REGISTERS
REGISTER

CRO

ACTIVEI
PASSIVE

LOOP
TEST

RECR

MOISC

CRl

ADRV

RRTl

SEND

SRO

NA2

NAl

NAO

RNRR

NB2

NBl

NBO

RNRX

SRl

lPKR

lXBA

NE2

NEl

NEO

SR2

TlOUT

IRTS

REC
IDLE

ERa

ER07

ER06

ER05

lERROR

ER04

-Causes Interrupt (lNTR Goes Low).

295

ER03

ER02

RANC

LINK

EROl

EROO

BIT

DESCRIPTION

R~T~"Wlil.cauS&tt\e 200,1t\>trarsrnlta6 .~,.'. (FlEcA=lfof RNA{AECFI:.6> . ofT1

int~rvalll ptoVldedllle2S01. Is
aCknowll!dgement.
.

nOlaendlng~

coMmand

or. waiting for."

TheS~"'O .bit(CA10)I~Ull8dto c~mmartdthe. 250t to llend .thenelltPacke{OfPacketa.

"SEND., 1,tIl1!2501wmraad'fI)mTLOOI< theBRilY blto! the ~lIt.aegmenU~r trans~
fIlISsi?ll.ffBRDY =0, the2501.wlllclaar.SEt.jPa!1dnoactlon occurs: ·'fBFlDY:::1,the
250twllIthenraadTS"DR .a.nd TQNT;foUowedby.thl! ltansmlsslol\ of thatbuflar. After
tralls.mISIlI?n,the25Q1Clear~.BRIlYOf thell!lg~nt Just tfanllfllitted, Bnd raadsBfjDY .9f
the next .lIOQment. 1ft, the nllxt$egment l~traMmlttl!d.tll a.the SEND bit Is 9'eared •. and
!ranamlllsionof packets 11,1 stoP~.
N~2cN~a.NextblockOf

transmilled data 10 be AcJ(oowledged.

RNRFI.An.RNRhall bOen received.

T~el'kR .bll·$tandsl.6r.f>aql

SEND
PACKET
#0

_TSADR #1

===========

~
\

SEND
PACKET
#2
RSADR #0

~RECEIVE
PACKET
#0
XFRI\OR

LIM

-.L

RECEIVE
PACKET
# 1
RECEIVE
PACKET
#2

MEMORY ACCESS SCHEME

298

SEND
PACKET

the occurrence of the defined event. However, the 2501
will not increment past 255 (all 1 's). The CPU has the
responsibility of clearing each counter. The first
counter past RlOOK is 111, etc.

"DEADLY EMBRACE" PREVENTION
A "deadly embrace" can occur when two processors
reach a state where each is waiting for the other. In this
case, the two processors are the user's CPU and the
micro-controller inside the 2501. Therefore, to prevent
the "deadly embrace", the following rule is obeyed by
the 2501 and should also be obeyed by the usar's CPU.
This rule applies to TlOOK, RlOOK, and to the 1/0
registers. The Error Counters do not apply to this rule.
RULE:

ERROR
COUNTER

If a bit is set by the CPU, it will not be
set by the 2501 , and vice versa. If a bit is
cleared by the 2501 , it will not be cleared
by the CPU, and vice versa.

As an example, the BRDY bit in the TlOOK segment is
set by the CPU, only, but cleared by the 2501, only.

Received Frames with FCS Error

Received Short Frames (less than 32 bits)

Number of times Tl ran-out (completed)

Number of I-Frame Retransmissions

REJ Frames Received

REJ Frames Transmitted

Invalid Commands Received

8
9

ERROR COUNTERS
Following continguously after RlOOK is ten 8 bit error
counters. The 2501 will increment each counter at

COUNT

Invalid Responses Received
Number of frames which I-field exceeded
total Limit.
Number of Null Packets Received

8YTE # IN
SEGMENT

ACK'ED

SPARE

BRDY

RESO

BLO

TSADR HI

TSADR lO
TCNT HI

SPARE

TCNT LO

5
6'
7
8

SBl2

SBL1

SBlO

Bll

RES2

SPARE FOR USER DEFINITION
SPARE

TlOOK SEGMENT

299

RESl

BYTE # IN
SEGMENT
1

7
FRCML

6
SPARE

5
SPARE

SPARE

RSADR HI

RSADR La

SPARE

0
REC
ROY

RCNT La

SPARE

RCNT HI

SBL2

SBL 1

SBLO

BLl

RES2

RESl

RESO

BLO

SPARE FOR USER DEFINITION
SPARE

• Byte #6 defines variable bit length and residual bits.
RLOOK SEGMENT

BRDY means that the transmit buffer is ready. The 2501
will send the block only after the CPU makes BRDY =
1. (BRDY is used in conjunction with the SEND bit.) At
the completion of the transmission, the 2501 will make
BROY = 0, and then read the BRDY of the next
segment.
After transmitting a packet, an acknowledgement must
be received from the remote device. The acknowledgement is contained in the received N (R) count of an
I-frame, RR frame, or RNR frame. Upon acknowledgement, the 2501 will make ACK'EO = 1, and generate a
block-acknowledged interrupt. Before assigning a new
block to a segment in TLOOK, the CPU must make sure
that the previous block which used that segment
number has been acknowledged.
REC ROY informs the 2501 that the receive buffer is
ready. The 2501 will not receive a packet into a buffer
referenced by a particular segment until REC RDY = 1.
If the 2501 progresses to a segment which has REC
RDY = 0, an error interrupt will be generated.
After receiving an error-free packet in proper sequence,
the 2501 will set FRCML, clear REC RDY, and generate
a Packet Received Interrupt. The 2501 will also write
the value of the binary length of the received packet in
RCNT HI and RCNT La. The NE count is advanced. The
2501 will acknowledge received packets at the first
opportunity. This will be in either the next transmitted
I-frame, or by an RR frame if RECR = 1, or by an RNR

frame if RECR = O. (RECR is in CRO.)
In the address bytes, H I represents the upper 8 bits and
LO represents the lower 8 bits. In the count bytes, HI
represents the upper 4 bytes.
TSAOR is the starting address of the buffer to transmit,
and TCNT is the binary count of the number of
characters in the I-field.
RSAOR is the starting address of the receive buffer.
After successfully receiving the packets, the 2501 will
write the value of RCNT which is the binary count of
the number of characters in the I-field.
Whether the 2501 accesses a look-up table or a memory
block, a OMA Cycle is required for each access.
TLOOK AND RLOOK POINTERS
There are three 3-bit counters for the status of the
segments in TLOOK and RLOOK. Status Register #0
(SRO) contains counters NA and NB which are used in
conjunction with TLOOK. NB is the segment number of
the next block to be transmitted, and is advanced at the
end of each OMA transmission. NA is the value of the
segment of the next block which will be acknowledged.
If all transmitted blocks have been acknowledged, then
NA = NB.
In SRI is a 3-bit counter, NE, used with RLOOK. NE
is the value of the segment number where the next
received packet will be placed.

300

PRELIMINARY TIMING SPECIFICATIONS
MIN.
(NS)

PARAMETER

SYMBOL

FiE

TAR

Input Address Valid to

TRD

Read Strobe (or DAC K Read)
to Data Valid

THO

Data Hold Time from Read Strobe

THA

Address Hold Time from Read Strobe

MAX.
(NS)
0

C IOALI
C IOAl)

200
375

~
~

50 pf
100 pf

80
80

TAW

Input Address Valid to Trailing Edge of WE

200

TWW

Minimum WE Pulse

200

TOW

Data Valid to Tr~Edge of WE or
Trailing Edge of DACK for DMA Write

100

TAHW

Address Hold Time alter WE

TDHW

Data Hold Time after WE or after

TDA1

Time from DROR (or DROW) to Output
Address Valid if ADRV ~ 1

TDAO

Time from DACK to Output Address
Valid if ADRV ~ 1

TOO

Time from Leading Edge of DACK to

TDAH

DACK for DMA Write

80
80

C (ADDRESS)

100 pf

360

C (ADDRESS)

100 pf

Trailing Edge of DROR (or DROW)

200

C IORO)

Output Address Hold Time from DACK

120

TDMW

Data Hold Time from DACK for DMA Read

T RP1

REPLY Response leading Edge
REPLY Response Trailing Edge

200
260

CPU READ TIMING (CS IS lOW)
r'cC+I~

50 pf

80
160
240

T RP2

COMMENT

= 50 pf
= 100 pf
ClOAD = 50 pf
ClOAD = 100pf
ClOAD

ClOAD

CPU WRITE TIMING (CS IS LOW)

_ _ __

'------r':../

--..::>....v ------~I--jl~'c."
DAC~

-I

'C"W

-----~~r---

1~"o~1

DMA READ TIMING

DMA WRITE (AO-A15 SAME AS DMA READ)

301

OUT

2400 REF

0'15 MAX

m-mmffiRtihfffihMJ
o

---11-0100TYP

15JOlO

~_OO

tIS"

WD2501 CERAMIC PACKAGE

This is a preliminary specification
characterization is completed

with tentative device parameters and

may be subJect to change after final product

Information furnished by Western Dig Ital Corporation IS believed to be accurate and reliable. However. no responsibility IS assumed
by Western DigItal Corporation for its use: nor any Infringements of patents or other rights of thud parties which may (esu!! from
its use. No license is granted by implication or otherwise under any palent or patent rights 01 Western Digital Corporation
Western Dlgllal Corporation reserves the fight to change said Circuitry at any tIme Without notice

WESTERN DIGITAL
COHPORA

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550, TWX 910-595-1139

302

WESTERN DIGITAL
c

WDK25001-XC PAC KIT
FEATURES

APPLICATIONS

• WD2501 X.25 PACKET NETWORK INTERFACE CHIP

• X.25 DEVELOPMENT

;,:II:

• RS-423 INTERFACE

• PACKET NETWORK EDUCATIONAL COURSES

• CRYSTAL AND BAUD RATE GENERATOR INCLUDED

• SYSTEM PROTOTYPING

«
::;)
II:

m
UJ

u..

DMA MEMORY INTERFACE

GENERAL DESCRIPTION

INCLUDES ASSEMBLY AND OPERATIONS MANUAL

The Western Digital Corporation WDK25001 XC PAC-KIT
is a X.25 development kit featuring the WD2501 Packet Network Interface chip. The PAC KIT provides for easy interface
to a local microcomputer or a Host System bus. along with
a RS-423 serial Communications interface.

RAM/ROM/EPROM SOCKETS PROVIDED
LARGE WIRE-WRAP
PROTOTYPING

BR1941
BAUD
RATE GEN

AREA

BOARD

FOR

WD2501
X.25 f¥.CKET NETWORK
INTERFACE

RS-423
INTERFACE

RIBBON
CONN

''(

RAM/ROM/EPROM
SOCKETS

PROTOTYPING AREA

WDK25001-XC BLOCK DIAGRAM

WESTERN DIGITAL
CORPOR"'TJON

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

303

[NJ ®~©[{'~ [p) [{'©~ (U] ©'lt~
U®©[h[[i}D©©J~ IN]©'lt®

305

, ·-Eleclroni
WD2511 LSI circuit simplifies
packet-network connection
by Geary L. Leger.

WestemDigftaICorp., Newport Beach. Calif.

307

lSI ready to make at mark
on packetm>$w~t({;hong networks
New chip's link-control capabilities
ease connection to terminals: Part I
by Geary L. Leger,

Western Digital Corp., Newport Beach, Calif.

Packet-switching networks are prime targets for the
application of large-scale-integrated circuit technology.
In fact, sometime during the first quarter of next year,
this useful and expanding approach to data communica-

This is the first of two articles. It deals with the overall
characteristics of packet-switching networks. Part 2, which
starts on page 95, describes an LSI chip being developed for
Level 2 control per the X. 25 protocol for packet networks.

tions will have its first dedicated LSI circuit, one
designed to take advantage of LSI's potential for lower
cost and greater reliability.
The circuit is the Micro Packet Interface chip, or
I'PAC, being developed by Western Digital. It will handle
Level 2 control of the link between a data terminal and a
network node as set forth in the X.25 protocol established by the Consultative Committee for International
Telephony and Telegraphy (CCITT). Because these

LEVEL 7

PROCESS
CONTROL

..oof------------~

PROCESS
CONTAOl

LEVEL 6

PRESENTATION
CONTROL

..... -----------+

PRESENTATION
CONTROL

LEVEL 5

SESSION
CONTROL

+--------------...

SESSION
CONTROL

LEVEL 4

TRANSPORT
END-TO-END
CONTRDL

~-----------~

TRANSPORT
END-TO-ENO
CONTROL

PEER-TO'PEER INTERFACES

LEVEL 3

NEnVORK
CONTROL

+-------------.
-----------

LEVEL-TO·
LEVEL
INTERFACE

NETWORK
CONTROL

...

LEVEL 2

.......

LEVEL 1

-011------------.-....

1. Layered architecturo. Independence among system levels allows changes to be made to one level without disrupting the operation of
other levels; and adjacent level is affected only if the changes affect the interface to that level. Standards apply to peer-to·peer interfaces.

308

..'

/..

··.······.'···.··.1' .., •....•:.•........

Recent efforts in
The security, survivability, and economic advantages of
packet-switching data-communications networks have not
gone unnoticed in either the military or the corporate

sectors. Though still in its infancy, this type of communication is growing rapidly.
According to Deiense Advanced Research Project
Agency director Eugene H. Kopf, the latest military packet
effort aims to find the optimum architecture for a

command and control network of 5,000 to 10,000 small
packet radio relay terminals whose purpose would be to
insure survivable control over strategic weapons. The
network voice and data-packet radios would provide line-

of-sight communications throughout the continental U. S.
after an attack.
The civilian sector has continued the development of
packet networks from their modest beginnings. In 1972,
Bolt Beranek & Newman Inc. founded Telenet, a public
packet-switching network taken over this year by General
Telephone & Electronics Corp. GTE Telenet Communications Corp., Vienna, Va., completed installation this month
oi a packet-switching exchange in San Juan, Puerto Rico,
ior ITT World Communications Inc. The new service allows
businesses and industrial organizations to link to the ITT
gateway and transmit and receive data over shared transmission lines to data terminals or computers on the U. S.
mainland.

Tymnet Inc., Cupertino, Calii., is the largest public packet-switching network in the U. S. It has so many customers
that it issues a 34-page directory describing 200 data
bases accessible through its network. Tymnet now serves

250 computers in the U. S.; it recently added New Zealand

networks are relatively new, familiarity with the Level 2
link control and other details of their operations is not
widespread. Yet the purpose of the I'PAC is intelligible
only in the context of such an understanding.
To date, most data-communications systems use
circuit-switching techniques. A physical circuit is
assigned either permanently (a private, leased line) or
for the duration of the call (a dial-up line). But of a
given line's total available time, only a small percentage
is actually taken up by data transmission. A system for
dynamic allocation of the physical circuits, in contrast to
static circuit-switching allocation, requires the logic and
memory capabilities of computers.
Prior to the late I 960s, static circuit allocation was
more economical than using computers in a dynamic
allocation system. The low cost of today's minicomputers
and micfOprocessors and the dramatic drop in the cost of
memory, however, make dynamic allocation more
economically feasible in many cases. It is most suitable
in multipurpose applications-digital communications
systems linking various types of data terminals such as
facsimile machines, computerized data bases, interactive
keyboard printers, or cathode-ray-tube terminals.
Historically, communications systems have been
developed to satisfy one application at a time. The wide
variety of computers, terminals, and technologies has led
to the development of many incompatible networks. A
time-sharing network may connect many asynchronous
interactive keyboard printers on dial-in lines at 110 or

309

pac~{et

switching

to its list of countries served, bringing the total to 26.

The Japanese have not been idle in adapting packet
technology to their needs. Nippon Telegraph and Telephone Public Corp. started work on its digital dataexchange system in 1971 and had installed packetnetwork equipment in seven cities by late 1978. This
commercial packet-switching network (called 050) is
expected to go into full service this year. 050 conforms
fu\\y to Recommendation X.25 of the Consultative

Committee for International Telephony and Telegraphy.
The packet network industry has come a long way since
the first operational system (Arpanet) was installed by the
Defense Advanced Research Projects Agency in 1969. In
1976, the CCITT adopted X.25 as a standard three-level
protocol for interfacing terminals to public packet
networks-a major step for the industry. Even though it
has been criticized as being too complicated, X.25 has
stimulated interest in packet networks.
However, packet switching is not the answer to a\\ data
and voice communications problems, as some have

claimed. Gino J. Coviello of the Defense Communications
Agency in Arlington, Va., concluded in a recent study that
the number of channels traversing a particular transmis-

sion link and the network topology and architecture have a
significant impact on the cost-effectiveness of a packet-

switching network. Ray W. Sanders, president of Computer Transmission Corp., says, "Packet switching will take
its rightful place alongside circuit switching." A hybrid
approach combining features of both circuit and packet
switching "provides the best of all possible worlds,"
according to Sanders.
-Harvey J. Hindin

300 bits per second. A clustered CRT application such as
18M's 3270 may operate synchronously at 1,200, 2,400,
or 4,800 b/s.
The incompatibility of different types of equipment
and the protocols they use for communicating greatly
reduces the reliability and efficiency of data communications as a whole. A single corporation may, for example,
use several incompatible networks.
Security and survivability

The technique of sending a digital data in short packets, rather than in a continuous stream, was first
suggested by Paul Baran of the Rand Corp. more than a
decade ago. The packets are transmitted between intermediate points in the network, calIed nodes, or DeES, for
data-circuit-terminating equipment (see table).
This dynamic-allocation technique has two major
inherent advantages over circuit-switching methods. It
increases data security, since the message is broken up:
all the packets would have to be picked up and combined
by an intruder before he could use the data. And system
survivability and reliability. are enhanced by the large
number of linked nodes. Alternate routes will get a
message through if some of the nodes or links are
malfunctioning or destroyed. The security and survivability are of great interest to the military. The commercial sector is also developing this type of system (see
"Recent efforts in packet switching," above).
The problem of equipment and communication-proto-

.";.•

.............
.. ::.'.....•
,.'. .
.'.,''.:.:

"',

col incompatibility is an international one, since data
communications is international. This question is
addressed at the global level by the CCITT (see "Setting
the standard," p. 93).
The difficulty of expanding, modifying, or upgrading
existing data-communications networks is another problem that is tackled by the new packet-switching systems.
Any communications system represents a large capital
investment, and down time can be disastrously expensive. A user cannot simply tear down an old network and
substitute a new one with the latest advances. New
terminals and technologies must be phased into the
existing structure without interrupting operation. This
calls for a degree of system flexibility.
Layered architecture
Packet-switching networks achieve this flexibility
through layered (or multilevel) architecture [Electronics
May 24, 1979, p. III J. Several standards organizations
have been working on the specifics of this concept.
The importance of layered structure is easy to understand. Suppose Mr. Jones, an executive, wishes to talk to
Ms. Smith, another executive. Jones (level 4) tells his
secretary (level 3) to get Smith on the line. Jones'
secretary dials the number (level 2). An electromechanical switching mechanism connects the two phones (level
I). Smith's phone rings (level 2). The two secretaries
converse (level 3) and pass on the information that the
call is ready to their bosses. Smith and Jones now
communicate (level 4).
Jones was never concerned with the electromechanical
switching mechanism, nor with Smith's telephone
number; he was primarily concerned with talking to
Smith (peer to peer) and secondarily with talking to his
secretary to get the call set up.
Multilevel communications systems are structured in a
similar fashion. The protocol standards are prepared for
connection in the peer-to-peer layer. Standards do not
define the interface between adjacent layers. This is
intentional: terminal manufacturers are thus left free to
design the adjacent-layer interface in their own way.
This enhances system flexibility. If a layer is changed or
upgraded, nonadjacent layers are not affected.
X.25 defines and standardizes three levels. There are
as many as four more definable levels (Fig_ I), but much
work remains to be done to standardize these higher
levels. Level I may be viewed as a data-exchange mechanism serving Level 2. Level 2 is a data-exchange mechanism serving Level 3, and so on.
Three standardized levels
Level 1 concerns itself with the link's physical interfaces. Level 2 deals with link control. It includes setting
up and disconnecting a link, the control of flow between
data generators and data receivers, and bit-oriented
frame structure. The I'PAC from Western Digital is
designed to perform the Level 2 functions. Level 3,
network control, includes the procedures for establishing
and disconnecting the virtual circuit and for controlling
the flow of data packets in the network.
In a packet network, the sender or receiver has a
terminal (commonly called DTE, for data-terminal equip-

~ACKET SWITCHING NETWORK TERMINOLOGY

ADCCP

Advanced Data·Communications Control Procedure
IANSI X3.661

ANSI

American National Standards Institute

ATOM

asynchronous time·division mUltiplexing

BOP

bit·oriented protocol

CCITT

Consultative Committee for International Telephony
and Telegraphy

OCE

data·circuit·terminating equipment (network node)

OTE

data· terminal equipment (user's terminal)

FCS

frame check sequence

HOLC

High·level Data·Link Control protocol (ISO 3309)

[SO

International Standards Organization

ITU
J

frame

LAP

International Telecommunications Union
information frame, known as a packet under X.25
Link·Access Procedure (X.25)

LAPS

Link-Access Procedure, Balanced (X.25)

Link
control

X.25 Level 2 control for linking OTE and DeE,
including link initialization, establishment, and
disconnection, and control of data flow on the link

Network
control

X.25 Level 3 control of virtual circuits in network,
including circuit establishment, disconnection, and
reset, and the control of packet flow

maximum number of bits in a packet

maximum number of command retransmissions

PAD

Packet Assembly/Disassembly facility (defined in
CCITT recommendations X.3, X.28, and X.29)

Physical
interface

X.25 Levell specifications for the physical connection
of OTE and DCE, including electrical parameters
and transmission rate

S frame

supervisory frame

SOLC

Synchronous Data·Link Control protocol

time minimum before retransmission of
unncknowledged command

U frame

unnumbered frame

X.25

CCITT recommendation for packet·switching network
protocols (others include X.3, X.28, and X.29)

ment) with a distinct address. Part of the gear at a
network node might also be called data-terminal equipment. The packets of data are transferred from node to
node and finally to the receiver's terminal.
When a node receives a packet, it stores the packet,
decides where and when to forward it on the basis of the
packet's destination and priority and the load conditions
of the network, and then does so. This store-and-forward
facility is the key to the network's ability to allocate
circuits dynamically. Packets going from terminal A to
terminal B" in Fig. 2 could follow the node path
7-12- 11-10, 7-5-3-1-10, or any of a number of others.
Dynamic routing within the network is transparent to
the users at their terminals. The path data takes is called
a virtual circuit between A and B: the terminals communica~e as if a dedicated circuit joined them. In order to

310

2. Many pooaible polho. The user of a packet·switching network at his terminal sees no difference between the virtual circuit and an ordinary

physical link. Network control may send the data packets through a changing series of nodes as system traffic conditions change.

establish a virtual circuit, terminal A transmits a callrequest packet that includes the caller's address and the
address of terminal B, the destination. Terminal B
accepts the request by returning a call-accepted packet
to A, and the virtual circuit is set up.
Circuit sharing

Several simultaneously active virtual circuits can be
set up by interleaving packets. This asynchronous timedivision multiplexing (ATOM) exploits the fact that a
typical virtual circuit carries data for only a small
percentage of the time it is set up. It differs from other
time-division multiplexing schemes in that a dedicated
NODE

TERMINAL
COMMAND

SECONDARY

PRIMARY

FUNCTION

FUNCTION
RESPONSE

COMMAND
PRIMARY
FUNCTION

SECONOARY
FUNCTION
RESPONSE

3. Addressablo functions. A terminal or node has a primary func·
tion that sends commands and receives responses. Its secondary
function, which has a different address, responds to received
commands. Arrows represent system logic, not phYSical wires.

311

time slot is not provided for each virtual circuit being
multiplexed.
In the multilevel packet-switching architecture, Level
2 (also known as the link level or the frame level)
involves the point of contact between the subscriber's
terminal and the network node it is linked to directly.
Each station, be it terminal or node, has two logical
functions needed for addressing and signal implementation, called primary and secondary (Fig. 3). The primary
function transmits commands and receives responses; the
secondary function does the reverse-it receives commands and transmits responses.
The structure of the data frames used for this communication is common to all bit-oriented protocols (BOPS)High-level Data-Link Control (HOLC), the essentially
similar Advanced Data-Communication Control Procedures (AOCCP), and the Synchronous Data-Link Control
(SOLC) protocol worked out by IBM [Electronics, Jan. 18,
1979, p. 137]. The Level 2 protocol defined by X.2S is an
outgrowth of HOLC.
The frame is simply a block of serial data exchanged
between two terminals or a terminal and a node. It
consists of a flag, an address field (or A field), a control
field (or C field), an information field (or I field), a
frame-check sequence (FCS), and another flag. Depending on the frame type, the information field mayor may
not be included.
There is a flag at either end of a frame; a single flag
may close one frame and open the next. Data transparency is provided within the frame by the transmitting
station: a logic 0 is inserted after all sequences of 5
contiguous logic I bits, so that no transmitted data is
inadvertently read as a flag, which has the binary form

Setting the standard
International interface standards are vital to the development and growth of packet-switching networks. Standards
lead to lower costs for equipment bought by network
users, since this equipment can be' manufactured in much
larger quantities. The user also benefits from the interchangeability of gear from different vendors. Manufacturers reap the rewards of a global market rather than a local
one, and network organization is made vastly easier.
A number of U. S. and international standards organizations are working together to set up interface rules. The
International Telecommunications Union (ITU), formed in
1865, operates under the auspices of the United Nations.
Under the ITU is the Consultative Committee for International Telegraphy and Telegraphy (CCITT), which is
primarily an organization of carriers.
Study Group VII is a CCITT organization that handles

public data networks. SG VII is responsible for publishing a
number of standards or recommendations for packetswitching networks. The best known of these is Recommendation X.25.
The International Standards Organization (ISO), which is
composed of representatives from the manufacturing and
user community, works closely with the CCITT; the ISO
also has a group under its wing with responsibility for

public data networks.
In the U. S., the American National Standards Institute
(ANSI) is a clearinghouse that coordinates activity for
voluntary standards. Its X3S37 committee, which has the
responsibility for public data networks, does liaison work
as well as coordination. This committee represents a cross
section of U. S. industry: manufacturers, users, and
carriers. It offers inputs to both the ISO and the CCITT.

INFORMATION FRAME (PACKET)

I'
FLAG

ADDRESS

PACKET
CONTROL

CONTROL

LEVEL 2

I_
FLAG

APPLICATION SOFTWARE

LEVEL 2 - - 1

UNNUMBERED FRAME (LEVEL 2)

ADDRESS

FLAG

(FCSI

,I·

----~-- LEVEL 3

FRAME
CHECK
SEQUENCE

USER DATA

INFORMATION

"'1.----

INFORMATION FIELD (PACKET DATA)

CONTROL l,mLD

FCS

FLAG

1"'·-----suPEHV,SORy FRAME (LEVEL 2l-----..j-1

FLAG

ADDRESS

CONTROL

FCS

FLAG

4. Standard fromoD. Three types of data frames may be sent over a packet network. All data except the user data in the information field of
an information frame is system overhead required for synchronization, data checking, verification, and bookkeeping functions.

01111110. The receiving station automatically deletes
the inserted Os from the data.
The frame-check sequence is the last 16 bits before the
closing flag. They are produced by a calculation that
checks all data between the opening flag and the first bit
of the FCS. The logic Os inserted for data transparency
are not checked.
A frame may be one of three types (Fig. 4); a supervisory frame (or S frame), an unnumbered frame (or U
frame), or an information frame (or I frame).
Level 2 control does not involve itself with the data
within the information field of an information frame. It

simply encloses the packet data in an HDLC frame and
sends it out onto the network.
Supervisory frames are used to perform supervisory
control of a link, such as acknowledging packets,

requesting retransmission of packets, and requesting
temporary suspension of transmission. Unnumbered
frames are used to set up, disconnect, and reset links.
The Level 2 protocol may take one of two forms:
Link-Access Procedure (LAP) and Link-Access Procedure, Balanced (LAPB). When it was originally written in
1976, Recommendation X.25 contained LAP only. LAPB
has been added since that time, offering some improve-

312

CENTRAL
PROCESSING
UNIT

,
\

X.3 I
X.29 I
I
I

TERMINAL
CONCENTRATOR
(PACKET
ASSEMBLY/
DISASSEMBLY
FACILITY)

X.25

PUBLIC
PACKET

NETWORK

X.75

1.1-"

CPU

PUBLIC
PACKET
NETWORK

5. MultitorminDI connoction. A Packet Assembly I Dissassembly
(PAD) facility allows various types of interactive terminals to communicate with each other using the interface standards indicated. PAD
equipment may belong to either the user or the network.

ments. Some changes in frame types were made, but the
primary differences between LAP and LAPB are in the
functions that set up, disconnect, and reset links. (Two
models of the I'PAC, the WD 2501 and the WD 2511, are
geared to the LAP and the LAPB, respectively.)
There are four system parameters defined by the X.25
Level 2 protocol: n, N2, Nt, and k. Tt is the time limit
set for the primary timer; when Tl runs out, an unacknowledged command may be retransmitted. N2 is the
limit set for a counter that is incremented each time a
command is retransmitted because time Tl ran out
without its being acknowledged. N 1 is the maximum
number of bits in a packet; it depends on the maximum
length of the information field. And k is the maximum
number of sequential packets that a terminal or node
may have outstanding (transmitted but unacknowledged) at any given time. In the I'PAC, TI, N2, and N 1
are programmable. The number k can never exceed
seven under X.25, and it is fixed at seven in the I'PAC.
Multiplelting terminals

Since each user of the packet network typically has
many different types of data generators and receivers,
multiplexers must connect the network to the existing
equipment. This multiplexer has been defined by the
CCITT as the Packet Assembly/Disassembly (PAD)
circuit (Fig. 5). The PAD is. specifically for use with
asynchronous terminals; it combines or separates the
multiple signals that are sent to or received from the
network.
CCITT protocol standards X.3, X.28, and X.29 are
used together to define a PAD interface. A PAD facility
may be viewed as a terminal concentrator that connects
several asynchronous terminals to a single X.25 link. The
PAD circuit is sometimes called an interactive-terminal
interface because in practice most terminals connected
to PAD interfaces require human interaction via
keyboards and CRT displays or printing equipment.

313

X.25
CPU

When a PAD interface is used between the packet
network and the terminals, two stations that are incompatible by themselves can communicate. They need only
be able to talk to the PAD. The I'PAC chips will allow
them to do this. Another advantage of this approach is
that new types of equipment added at a terminal are
transparent to the network.
On the other hand, changes and improvements within
the packet network are transparent to the user. These
improvements could include increasing node-to-node
communication speed, increasing the number of nodes,
and changing node-to-node connections to fiber optics.
Variations on the theme

Many packet systems are available; they vary according to the network organization. Several networks, such
as Montreal-based Bell Canada's Datapac, offer (in
addition to the standard virtual circuit) a permanent
virtual circuit that requires no call for link establishment
and is continually available.
Another possible service, Datagram, when made available, will not require the initial establishment of a virtual
circuit. In this approach a packet is merely put out on
the line-typically by users of so-called transactionbased networks. There is no call procedure, and duration
of connection is not of concern for billing purposes.
Users may, for example, pay a flat fee. Short, independent data bursts will ultimately work their way through
the network to their destinations.

A closed user group; available from Datapac and
others, is like a private network. Users in a group,
actually connected to a public network, can communicate with one another, but access is barred to and from
all other users of the network. AT&T'S proposed
Advanced Communications Service includes this feature;
the company calls it a virtual subnetwork.
0

WD2511 LSI circuit simplifies
packet-network connection
48-pin chip replaces entire board
and thousands of lines of software
by Geary L. Leger,

Western DigitafCorp., Newport Beach, Calif

Packet-switching data-communications technology
can now claim its first dedicated large-scale integrated
circuit. Called the Micro Packet Network Interface chip,
or I'PAC for short, it is a complete X.25 Level 2 controller with on-chip bidirectional direct-memory-access
facilities. This n-channel silicon-gate MOS chip in a
48-pin package replaces a board full of electronics.
The I'PAC goes way beyond the functions performed
by the bit-oriented-protocol (BOP) control chips currently in widespread use. It includes the circuitry of a BOP
chip. But it handles many other operations, eliminating
the need for separate OMA circuits and associated
address latches, timing chips, and the system software
(more than 1,000 lines of code) required until now to
perform Level 2 control of the link between a data
terminal and a node of a packet-switching network. It
has an II-K read-only memory and the equivalent of
three microprocessors: one to handle data-transmission
operations, another for dealing with received data, and a
third central processor to coordinate all chip functions.
Sample quantities of the controller will be available from

SYNCHRONOUS DATA-LINK

pPAC X 25
ENHANCEMENTS \

I
I
-PRo'rb5cOl - - . :

I
I
I
I
I

LINK SET·UP
AND DISCONNECTION,
DATA FLOW CONTROL

FRAME
{
STRUCTURE

pPAC AREA OF APPLICATION

I
I
I
I
I

Western Digital Corp. in the first quarter of 1980.
The data-link controllers already on the market
(Western Digital 1933, Signetics 2652, Intel 8273, Zilog
SIO, and others) handle BOP frame structure in a broad
range of applications. For example, the WD 1933 can be
used with the High-level Data Link Control (HOLC) and
Synchronous Data-Link Control (SOLC) protocols,
including the SOLC loop mode. This chip and others like
it handle zero-bit insertion and deletion, the frame-check
sequence (FCS), and the flags that define the beginning
and end of a data frame.
The I'PAC trades some of this protocol flexibility for
the sake of greatly enhanced usefulness within its area of
application (Fig. I). It is restricted to the Level 2 packetswitching protocol defined in Recommendation X.25
from the Consultative Committee for International Telephony and Telegraphy (CCITT), a protocol developed
from HOLC. But other BOP chips do not set up, disconnect, or reset the link; they do not automatically retransmit up to seven information frames (I frames); nor do
they have a timer for retransmission control. These are

CONTROl(SOlC) PROTOCOL ' \

I
I
I
I
I

I
I
I
I

1
I
I

HIGH-LEVEL DATA·lINK
CONTROl(HOlC) PROTOCOL

I
I
I
I

I
I

I
I
I SOle
I LINK
I MODE
I
I
I

LINK CONTROL

.1
I
I
I
I
I

APPLICATION AREA OF BIT-ORIENTED·PROTOCOL CHIPS

1. Targetod. The Micro Packet Interface (J.lPAC) chip is the first large-scale integrated circuit designed speGifically for packet-switching
applications. The application range of other chips that handle bit-oriented frame structure is wider, but the #PAC does much more in its area.

314

;

,1"

TABLE" COMPARISON OF FEATURES OF
HOle I AOCCP protocol feature

Basic bit-oriented frame structure

BIT'ORIENiEO:R.R:OT9C;o\6;Q.Hip~ ~':1 '~A"'~ "

X.Z5 LevelZ

Bit-oriented-protocol chips

MPAC

yes

yes
yes

Retransmission of up to 7 I frames (modulo 8)

yes

Asynchronous response mode

yes, LAP

yes. 2501

Asynchronous balanced node

yes, LAPB

yes. 2511

Control of 5, U frames

yes

Link set-up, disconnect, and reset procedures

yes

yes
yes. T1/N2

Time-out recovery

yes, T1 IN2

Multipoint operation

yes

Normal response mode (N RM)

Level 2 modulo 128

FS" item for further study by the CelTT

all features of the !LPAC chip (see Table I).
Two versions of the !LPAC will be made available. One,
the WD 2501, uses the Link-Access Procedure (LAP)
defined in the first version of X.25. The WD 2511 is for
networks using the Link-Access Procedure, Balanced
(LAPB) added to X.25 subsequently. The two chips ditTer
only in the program stored in ROM. They are pincompatible and interchangeable without hardware or
software modifications. Both may be used either in a
terminal (OTE, data-terminal equipment) or in a network
node (OCE, data-circuit-terminating equipment).

Direct memory access
Because of the HDLC feature that allows up to seven
packets (I frames) to be outstanding (transmitted but
unacknowledged) at any time, the !LPAC has information-field data (the I field of an information frame)
buffered for up to eight packets both when transmitting
and when receiving. In other words, the !LPAC may have
to retransmit up to seven packets. It must therefore be
able to retrace its steps through as many as seven of its
eight buffers.
DMA circuitry, included in the !LPAC, is the bes~ way to
achieve this. A number of other control chips (floppydisk controllers and data-link controllers) are OMAcompatible, but they do not actually include DMA.
General-purpose microprocessors that have their own
DMA, such as the Intel 8089, arc not in the same category as the !LPAC.
DMA control on the !LPAC is simple, requiring only
three pins (DRQW, DROR, and DACK) for handshaking
with the central processing unit's bus (Fig 2.). There are
16 address-output pins (AD through A15) that are separate from the eight data pins (DALO through DAL7).
This means that the DMA transfers are fast-they occur
in a single cycle. Unlike the !LPAC, OMA chips such as
Western Digital's 1883 or Intel's 8257 require external
address latches. This means that some or all of the
address must come through the data bus and two or
three cycles are required for data transfer.
In general, DMA control is either of the block-transfer
type or the transparent type. In block-transfer DMA
control, the DMA controller transfers several bytes of

315

data while the CPU is disabled from using the bus. If
transparent, the DMA control is imbedded in the CPU's
clock cycle in such a way that the transfers are invisible,
or transparent, to the CPU. Since the !LPAC must be able
to transmit and receive data on two DMA channels at
once (for full-duplex operation), the only logical choice
for the !LPAC is transparent DMA, since block-transfer
DMA would restrict operation to half-duplex.
All Level 2 data is appended and checked automatically by the !LPAC. The I-field data is accessed via OMA
channel. All supervisory frames (S frames) and unnumbered frames (U frames) are automatically transmitted
and checked by the !LPAC. The user's CPU operates only
on the I field of I frames.

Keeping track of packets
The DMA uses two lookup tables-one for transmitted
frames (TLOOK) and another for received frames
(RLOOK). These contain addresses and control bytes for
the individual packets. Thus packet data is addressed
indirectly. This method is best suited for most software
applications.
The 16-bit starting address for TLOOK is loaded into
the I'PAC by the CPU. RLOOK must follow immediately,
and both TLOOK and RLOOK are stored in random-access
memory external to the !LPAC.
There are a total of eight segmented control sections
for each table. Each section contains 8 bytes, 4 of which
are used for memory starting address and length. The
rest are for control.
In the transmit mode, the !LPAC reads (from TLOOK)
the starting address and length of the first packet to be
transmitted. The chip then automatically transmits the
flag, address, and control fields. Next, the informationfield data is transmitted using DMA and the memory
location called "send #0 packet." At the end of the
information field, the !LPAC automatically sends the FCS
and closing flag. It then moves on to the next packet.
If retransmission of one or more (up to seven) packets
becomes necessary, the chip automatically retraces the
previous transmissions through the TLOOK table. The
user's CPU software does not become involved in the
retransmission. An error counter is incremented.

a'BIT DATA ADDRESS LINE

es
WE --.
RE ----+
IAO-IA3 ~
INTR

+12 V

'5 V
GND
eLK

READI
WRITE
CONTROL

------j>

"
'
"
p-----

116 X a)

COUNTERS

------

CENTRAL
MICROCONTRDLLER

REG ISH RS
INTERNAL
REGISTERS
III X a)

READ·DNLY MEMORY

INPUT/OUTPUT

DIRECT
MEMORY
ACCESS

-+- 0
_DR
~D

DATA/CONTROL BUS

RECEIVER
MICRO CONTROLLER

~A O-A1S

TRANSMITIER
MICROCONTROllER

TRANSMITTER

RECEIVER

---

..-

LOOP TEST

2. Inaido tho ~PAC. The Level 2 controller has its own timer and direct-memory-access circuitry and is the logical equivalent of three
microprocessors. Routines stored on the chip allow it to relieve the network user's central processor of a large software overhead burden.

Each received frame is checked for correct address
and FCS fields and for type of control field. If the frame
is an I frame, the I field is placed in the assigned
memory location using a method similar to that used in
transmission. After the packet is received error-free and
in proper sequence, an interrupt is generated and the
!,PAC is ready for the next packet, which will be placed
in the next location.
Ten 8-bit error counters follow RLOOK in the external
RAM. These counters do not cause an error interrupt, but
maintain a running count of error activity. The contents
of the counters include: the number of frames received
with FCS error; the number of times TI (the time minimum set for a timer that allows retransmission of an
unacknowledged packet) ran out; and the number of
packet retransmissions.
Control bits are included in TLOOK, RLOOK, and the
!,PAC to ensure orderly transfer of data blocks. For
example, the control bits are designed to prevent what is
known as "deadly embrace," a situation in which the
!,PAC and the user's computer are waiting for one another to start.
Self-testing

Self-testing features are critical to proper operation.
The !,PAC does a comparison test, an internal RAM
register test, and a loop-back test. All three are suitable
for use during manufacturing and inspection. The internal RAM and loop-back tests are also useful for system
diagnostics and troubleshooting.
The comparison test requires a device known to be
good or a stored list of known good responses. The
program location counter (PLC) for the main ROM is
halted so it may be incremented under external contro!'

ABM

asynchronous balanced mode

ARM

asynchronous response mode

CMDR

command reject (U frame, LAP only)

DISC

disconnect (U framel

disconnect mode (U frame, LAPB only)

FRMR

frame reject (U frame, LAPS only)

REJ

reject {S frame}

RNR

receiver not ready (S frame)

receiver ready (S frame)

SABM

set asynchronous balanced mode {LAPS only}

SARM

set asynchronous response mode (LAP only)

unnumbered acknowledgement (V frame)

All jumps stored in ROM are disabled so that each
location of the PLC may be counted. As the PLC is
incremented, the responses of the output pins and status
registers are compared to the known good responses.
There are 11 8-bit registers in the !,PAC that are not
directly accessible by the user's CPU, which complicates
testing somewhat. The internal RAM register test
provides a means of checking these registers. The
contents of register A are placed in six even internal
registers and the contents of register B in five odd
internal registers. The 11 registers are then added
together without carry and the result is placed in status
registers. This test is initiated by a control bit in the
!,PAC. The loop-back test is discussed later.
For the purposes of discussing link establishment
procedures, it will be assumed that there is a 2501 !,PAC
at each end of the link. In practice, the 2501 can

316

TERMINAL A

L----I

--~=~)
THOUSAND
FEET

TERMINAL

3. Off tho notworl,. The p.PAC is also useful in non-network applications that use bit-oriented protocols. It provides full-duplex capability,

does error detection and recovery, and gives systems the option of hooking directly to a packet-switching network at some future date.

communicate with any device meeting X.25 Level 2
specifications.
When a link is set up, it is said to be in the information-transfer phase. This means that the terminal and
node will accept and transmit I and S frames. When a
link is logically disconnected, only U frames - DISC,
SARM, or UA (disconnect, set asynchronous response
mode, and unnumbered acknowledge; see Table 2)-will
be accepted or transmitted.
Linlc supervision

A link-connect frame is not the same as a link-reset
frame. A link in the information-transfer phase may be
reset in one direction by a SARM transmission. A link is
up after both ends send a SARM command and receive a
UA response.
Since a SARM can be either a command to reset or set
up a link, misinterpretation by the receiver of a SARM is
possible. This could happen when a link is established if
one end momentarily loses power. When that end tries to
bring the link up by sending a SARM, the other end may
interpret the command as a link-reset.
There arc two ways to get around this problem.
Suppose a terminal or node attempting to bring a link up
sends a SARM command and receives a UA. After time
Tl, if the station does not receive SARM, it assumes that
the other end considered the link up. It will then disconnect the link by sending DISC and receiving a UA, and
attempt to set up a link a second time.
The other way around the problem is the method used
by the 250l. The 2501 will always send DISC and receive
a UA before attempting to bring the link up. This will
assure a logically disconnected link so that it may

317

attempt to set one up. Immediately after the link is up,
the 2501 generates an interrupt.
It is possible to recover a single error on a packet with
,",PAC control. The error makes the received FCS bad, so
B docs not recognize A's first transmission of frame l.
When B receives frame 2, something is wrong since the
last successfully received packet was frame O. Thus, at
the next opportunity, B sends a REJ (reject-an S frame)
asking A to retransmit frame l. This opportunity comes
after B completes sending its frame 2.
When A receives the REJ frame, it is sending frame 3.
There is no need to continue with frame 3, so A aborts
transmission of frame 3 and goes back and retransmits
frame l. After retransmitting frame I, A will retransmit
frames 2 and 3. Finally, A will continue transmitting
other frames.
Loop-baclc

A loop-back condition exists when a station receives
the same serial information it has transmitted. In the
loop-back test, the serial-transmit output is connected to
the serial-receive input in order to test the transmitter
and receiver channels. Each station has both primary
and secondary functions, so there are two logical primary-to-secondary associations on a terminal-to-node link,
and each association is identified by a different address
field. This makes loop-back testing impossible when a
strict X.25 connection is made. Commands will have the
A field of a response and vice versa. One way around this
is to make the A fields of the two associations equal for
the duration of the loop-back test. (The A fields arc
programmable in the ,",PAC.)
Another problem with loop-back testing is the actual

detection of the condition and the detection of the condition's removal. There is no simple way around this
problem, and the IlPAC gives only limited assistance.
First, detecting the existence of a loop-back condition
is the responsibility of the CPU driving the IlPAC. If the
CPU sees that a link cannot be brought up, or if a link is
up and suddenly has excessive link resets and CMDRs
(command reject, a U frame), the CPU could assume the
presence of a loop-back condition. After making the two
A fields the same, if a disconnected link is successfully
brought up, then the loop-back condition exists.
To detect the removal of this condition, a particular
control bit (RRTl) in the IlPAC may be used. It causes
the IlPAC to send an RR (receiver ready, an S frame) or
an RNR (receiver not ready, also an S frame). These
frames are sent at Tl intervals as long as the IlPAC is not
commanded to send a packet. As long as the IlPAC
receives those S frames, the loop-back condition exists.
However, if the IlPAC fails to receive an S frame for a
time equal to TI x N2, an interrupt is generated, signalling that the loop-back condition has been removed.
Modified X.2S

The original design intention was to use the IlPAC in a
strict X.25 terminal-to-node application, the only application covered by X.25. However, by taking advantage
of the terminal-node symmetry of the IlPAC (the fact
that it can be used in both DTE and DCE), other applications are possible that use its built-in features.
For instance, the user does not need to develop the
software for error recovery since this is a IlPAC feature.
For another, using a IlPAC makes it possible to connect a
non-packet terminal to an X.25 link at a future time.
And lastly, the chip's protocol is bit-oriented. It has a
number of advantages over older, character-oriented
protocols, such as code transparency, full-duplex capability, flexibility, and modularity [Electronics, Jan. 18,
1979,p.137).
One possible application is the connection of two
terminals at Levels I and 2 (Fig. 3). How much of Level
3 is used would depend upon the individual application;
the more of Level 3 used, the better standardized the
interface is. One of the terminals in Fig. 3 could be a
terminal concentrator (a Packet Assembly/Disassembly
facility, or PAD, as defined by Recommendations X.3,
X.28, and X.29) on a factory floor, and the other could
be a host computer in a data-processing center.
Modified X.25 could also be used in a multipoint
system (Fig. 4). Idle terminals in this type of system
must transmit an "idle" sequence, not continuous flags.
The terminal addresses (AD3, AD5, AD7, and so on)
correspond to the transmitted response A field. The
transmitted command A field is the same for all terminals and is chosen to be hexadecimal 0 I in this case. All
A fields arc selected with odd values (least-significant bit
transmitted first) to conform to the extended-address
format of the Advanced Data-Communication Control
Procedures (ADCCP).
Two terminals on the multipoint line may establish
and discontinue communications by exercising X.25
procedures for setting up and disconnecting a link. But
only two terminals can communicate at anyone time.

TERMINALS

____________--,A~______________~,

AD3

AD5

C'" B·BIT HEXADECIMAL ADDRESS
FOR TRANSMITTED COMMAND
AND EXPECTED RECEIVED
RESPONSE

AD7

AD9

R" a'BIT HEXADECIMAL ADDRESS
FD~ TRANSMITTED RESPONSE
AND EXPECTED RECEIVED
COMMAND

4. Multipoint IinB. The programmed features of the pPAC chip enhance the flexibility of a system comprising one master terminal and
up to 128 slave terminals. Hardware and software savings are

possH

ble when the J(PAC is used in this off-network context.

Suppose that AD3 wishes to communicate with AD7.
AD3 will first make sure that its receiving line is idle (a
status bit in the IlPAC). Next, AD3 will change its
transmitted command and response A fields to be the
reverse of AD7 (command field is set to 07, response
field is set to 01). Then AD3 will initiate link establishment by setting a control bit, called "active," in the
IlPAC. Once the link has been established (the IlPAC
generates an interrupt when the link is first set up), AD3
and AD7 may exchange I frames. To discontinue the
session, either AD3 or AD7 will set the mandatorydisconnect control bit in its IlPAC. This will cause that
terminal to initiate a logical-disconnect procedure.
Contention and roll-call methods

The multipoint system may be implemented by either
contention or roll-call polling. In the roll-call method,
the master terminal will initiate link establishment with
one of the slave terminals, communicate with that slave,
discontinue the session (disconnecting the link), and go
on to the next slave. This process continues until all
slaves are polled and then starts over. One advantage of
the roll-call method is that the master has tight control
over the line for efficient operation.
A disadvantage is that slaves must be queried (polled)
before sending data, and the more slaves on the line, the
longer it takes for the master to poll them. Therefore it is
essential that each slave be designed to exchange a
relatively small amount of data with the master in a
single session, lest it tie up the line for long periods.
Large amounts of data should be broken up and
exchanged in more than one session. This method is
suited to applications where the multipoint line has a
high usage.
In the contention method, any terminal may initiate a
session at any time. This is similar to a party telephone
line and is suited to applications where line usage is low.
All sessions are between the master and one of the
slaves, but unlike the roll-call method, a slave may
initiate the session. The terminal that initiates a session
must send an I frame with its unique address immediately after the link is set up.
0

318

Board Product
NumberDng System

319

TELECOMMUNICATIONS
BOARD lEVEL PRODUCT NUMBERING
GENERAL DESCRIPTION: ~D

XXXXX

A A A
4

1. WD

WESTERN DIGITAL.

2. A

A letter to be designated. This field may be missing. Values assigned to
date: K - KIT.

3. XXXXX

An expanded version of the number of the featured WESTERN DIGITAL
LSI device on the board.

4. A

A letter designating BUS OPTION. This field will never be blank. Values
assigned to date:
A
B
D
E
X

5. A

A letter designating 110 Channel interface. This field will never be blank.
Values assigned to date:
A
B
C
D
E
X

6. A
EXAMPLES: WDK 2001-XA

WD 25001-AC -

UNIBUSTM
Q BUS™
MULTIBUS™
"STANDARD" BUS
No BUS interface

RS 232
RS 422
RS 423
RS 449
Fiber Optic
No 110 channel

A letter. function to be designated later.
WESTERN DIGITAL Cryptographic Kit using the WD2001. The board has
an RS 232 VO Channel interface.
WESTERN DIGITAL Packet Switching board using the WD 2501. The
board has a UNIBUS™ computer interface and an RS-423 110 Channel
interface.

321

Introduction to

COMPUTER PRODUCTS DDVDSHOIN
The Computer Products Division of Western Digital is an established leader in
File Management Devices. We are currently the leading supplier of floppy disk
and Winchester disk controller products. We provide our customers with a
standard line of MOS/LSI controller devices, support circuits, custom devices
and board level products.

Winchester Products
Western Digital recently announced and began shipping the WD1000 fixed
disk controller and WD11 00 chip set. These products dramatically reduce the
cost and circuit board area required to interface with the popular Winchester
technology devices.

Floppy Disk Products
The Computer Products Division is the world's leading supplier of MOS/LSI
floppy disk devices. Our 1700 Series Controllers support single and double
density, IBM compatible and non-standard 5% inch and 8 inch drives.

Specialty Products
The Computer Products Division supplies specialty devices and board level
products which support data management activities. These include standard,
semi-custom, and custom products, and a family of semi-custom logic arrays.

323

Table of Contents

COMPUTER PRODUCTS DIVISION
Page
WD1000

Winchester Controller Board

327

WD1100
WD179X-02

Winchester Controller Chip Set
IBM Compatible Double Density Floppy Disk Controller

329
331

WD179X

Application Notes

355

WD1771-01

IBM Compatible Single Density Controller

371

WD1771-01

Application Notes

391

WD1691

Floppy Disk Support Logic

399
407

DM1883

Direct Memory Access Controller

WD2143-01

Four Phase Clock Generator

419

WD1510

LIFO/FIFO Buffer

425

325

WESTERN DIGITAL
c

WD1000 WINCHESTIER CONTROLLER

FEATURES

SPECIFICATIONS

• ST500/SA1000 INTERFACE

INSTRUCTION SET

o 256 BYTE BUFFER

RESTORE
READ SECTOR
WRITE SECTOR
AUTO FORMAT
SEEK

o AUTOMATIC CRC CHECKING/VERIFICATION

o 5 MBITS/SEC TRANSFER RATE
II

DMA OR PROGRAMMED I/O TRANSFERS

o CONTROL UP TO 4 DRIVES
o CONTROL UP TO B R/W HEADS

POWER SUPPLY

o GENERAL PURPOSE B BIT INTERFACE

+5VDC

o SINGLE 5-VOLT SUPPLY

o MULTIPLE SECTOR READ AND WRITE COMMANDS
.. FORMATTING AND SECTOR INTERLEAVE CAPABILITY
.. BUILT IN DATA SEPARATOR/WRITE PRECOMPENSATION LOGIC
• SIX POWERFUL MACRO-COMMANDS
• "BAD BLOCK" MARK AND DETECTION

CONTROLLER/INTERFACE

B DATA LINES
3 ADDRESS LINES
MASTER RESET
DATA REQUEST
INTERRUPT REQUEST
READ ENABLE
WRITE ENABLE

GENERAL DESCRIPTION

The WD1000 WINCHESTER CONTROLLER BOARD provides the user with a low-cost alternative for interfacing any ST500 compatible Winchester disk drive to a host computer. The processor interface consists of an
a-bit bi-directional bus for data, status and control word transfers. The controller board includes data separation
and write precompensation circuitry. Data being written to or read from the drive is stored in an on-board buffer
memory, simplifying the DMA or programmed I/O interface. The controller will read or write MFM data at rates up
to 5M bits per second.
Reading and writing of sectors, along with motor control is accomplished via a powerful set of macro-commands. Programming the WD1000 controller board is similar to programming the Western Digital FD179X floppy
disk controller.
The WD1000 is based upon a proprietary Chip Set specifically designed for Winchester control. The WD1000
Chip Set is also available for OEM design.

327

INTERFACE DIAGRAM

·,8
:8

CONTROL, BUS

HOST
INTERFACE
BUS

HOST
COMPUTER

WD 1000

k=>

I~
<

DATA BUS

(

DRIVE 3

;

DRIVE 4

Host Interface Signals

Control Signals

Data Signals

Data Access 0
Data Access 1
Data Access 2
Data Access 3
Data Access 4
Data Access 5
Data Access 6
Data Access 7
Write Enable
Read Enable
Address 0
Address 1
Address 2
Interrupt Request
Data Request
Chip Select
Write Clock
Timing Clock

Reduce Write Current
Write Gate
Seek Complete
Track 000
Write Fault
Head Select 0
Head Select 1
Head Select 2
Index
Ready
Step
Direction
Drive Select 0
Drive Select 1
Drive Select 2
Drive Select 3

+ Write Data
- Write Data
+ Read Data
- Read Data
+ Timing Clock
- Timir)g Clock

WESTERN DIGITAL
COR

paR

13128 REDHILL AVENUE, BOX 2180

NEWPORT BEACH, CA 92663 (714) 557-3550, TWX 910-595-1139

328

WESTERN
DIGITAL
p
c

WD1100 WINCHESTER CONTROLLER CHIP SET

DESCRIPTION

FEATURES

The WDll00 Chip Set provides a low cost alternative for
developing a Winchester Controller. These five devices have
been designed to read and convert an MFM data stream into
a-bit parallel bytes. During a write operation, parallel data is
converted back into MFM to be written on the disk. Address
Marks are generated and detected while CRC bytes can be
appended on the data stream. The WDll00 is fabricated in
N-channel silicon gate and technology and is available in a
20 pin Dual-In-Line package.

•
•
•
•

:i"

•
•
•
•
•

WDll00-0l
WDll00-02
WDll00-03
WDll00-04
WDll00-05

::I:

Winchester Controliers For:
• Shugart Associates-SAl 004
• Seagate Technology-ST506
• Quantum Corp.-Q2000

VCC

APPLICATIONS

Ser/Parallel Converter
MFM Generator
AM Detector
CRC Generator/Checker
Par/Serial Converter

CLK

II:

SA1000/ST506 COMPATIBLE
SINGLE 5V SUPPLY
TRI-STATE DATA LINES
5 MBITS/SEC TRANSFER RATE

NRZ

VCC

SKPEN

BCLR

NRZ

WCLK

TEST

WCLK

RWC

DOO

DOUT

DOl

BDONE

D02

SHFCLK

D03

D07

INTCLK

D04

D06

D05

VSS

MFM

INTRQ

DRQCLK

DRQ
EARLY
LATE
NOM

WDll00-0l

WDll00-02

SERIAL/PARALLEL CONVERTER

MFM GENERATOR

RCLK
DIN

VCC
RST

RCLK
CLKIN

CP
NC

DOUT
NC

AMDET
AMDET

NC
TESTI

QOUT
NC

ENDET
VSS

DCLK
TEST2
WDll 00-03

WD1100-04

WD11 00-05

AM DETECTOR

CRC GENERATOR/CHECKER

PARALLEL/SERIAL CONVERTER

329

1100V PLASTIC PACKAGE

1100U CERAMIC PACKAGE

This is a preliminary specification wH:h tentative device parameters and may be subject to change after final product characterization is
completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western D;gital Corporation for its use; nor any infringements of patents or other rights of third parties which may resu" from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Westem Digital Corporatkm
reserves the righllo change said circuilry al anytime wijhout nOlice.

WESTERN DIGITAL
CORPORATION

3128 REDHlll AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

330

WESTERN
DIGITAL
p

FD 179X-02 floppy Disk Formatter/Controller Family
• TWO VFO CONTROL SIGNALS
It SOFT SECTOR FORMAT COMPATIBILITY
• AUTOMATIC TRACK SEEK WITH
VERIFICATION
.. ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
.. READ MODE
Single/Multiple Sector Read with Automatic
Search or Entire Track Read
Selectable 128 Byte or Variable length Sector
o WRITE MODE
Single/Multiple Sector Write with Automatic
Sector Search
Entire Track Write for Diskette Formatting

FEATURES
SinQle Density (FM)
Double Density (MFM)
True Data Bus
Inverted Data Bus
Write Precomp
Side Selection Output

o SYSTEM COMPATIBILITY

Double Buffering of Data 8 Bit Bi-Directional
Bus for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-Chip Track and Sector Registers/Comprehensive
Status Information

Wi'

39 1 INTRQ

"OALO

I RAW READ

STEP

X
X

RCLK

AGiSSQ

T
E
A
F
A
E

P
P
Y

WE
179X

10K

FLOPPY DISK
CONTROLLER
FORMA TTER

WG
WPRT

WFIVFOE
IP

TROD
10K

10K

READV
TG43

LATE

ORO

STEP

INTRO

DIRe

eLK

179517

X
X
X

EARlV

"'79317 TRUE BUS

X
X
X

=RG

X
X

1797

M
p
U
T

DIRe

'1791/3

X
X

r---------~-EAA~W~R~E~AO~~-----,

DATA (e)

I
N

1795

X
X
X

E
A

OAL 7

1793

X
X

FLOPPY DISK DRIVE INTERFACE
SINGLE OR MULTIPLE DRIVE CONTROLLER!
FORMATTER
NEW MINI-FLOPPY CONTROLLER

111'001.1211'1

J ORO

1791

APPLICATIONS

V
NC

.. PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
co WRITE PRECOMPENSATION
.. WINDOW EXTENSION
Q
INCORPORATES ENCODING/DECODING
AND ADDRESS MARK CIRCUITRY
" FD179214 IS SINGLE DENSITY ONLY
.. FD1795/7 HAS A SIDE SELECT OUTPUT
179X-02 FAMILY CHARACTERISTICS

FEATURES

T.~

=ssa

DDEN

PIN CONNECTIONS

HLO

Vss

Voo

GE
.......I

111.!v
+12

FD179X SYSTEM BLOCK DIAGRAM

331

Vee

+5V

SHOT

(IF USEO)

I
I

GENERAL DESCRIPTION
The FD179X are MOS LSI devices which perform the
functions of a Floppy Disk FormatterIControlier in
a single chip implementation. The FD179X, which
can be considered the end result of both the FDl771
and FD1781 designs, is IBM 3740 compatible in
single density mode (FM) and System 34 compatible
in Double Density Mode (MFM). The FD179X contains all the features of its predecessor the FDl771,
plus the added features necessary to read/write and
format a double density diskette. These include address mark detection, FM and MFM encode and decode logic, window extension, and write precompensation. In order to maintain compatibility, the FDl771,
FD1781, and FD179X designs were made as close as
possible with the computer interface, instruction set,
and I/O registers being identical. Also, head load

PIN OUTS
PIN
NUMBER

PIN NAME

NO CONNECTION

MASTER RESET

POWER SUPPLIES

21
40
COMPUTER INTERFACE:

control is identical. In each case, the actual pin assignments vary by only a few pins from anyone to
another.
The processor interface consists of an 8-bit bidirectional bus for data, status, and control word
transfers. The FD179X is set up to operate on a mUltiplexed bus with other bus-oriented devices.
The FD179X is fabricated in N-channel Silicon Gate
MOS technology and is TTL compatible on all inputs
and outputs. The 1793 is identical to the 1791 except
the DAL lines are TRUE for systems that utilize true
data busses.
The 1795/7 has a side select output for controlling double sided drives, and the 1792 and 1794 are "Single
Density Only" versions of the 1791 and 1793. On these
devices, DDEN must be left open.

SYMBOL
NC

FUNCTION
Pin 1 is internally connected to a back bias
generator and must be left open by the user.
A logic low on this input resets the device and
loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE.
When MR is brought to a logic high a RESTORE
Command is executed, regardless of the state of
the Ready signal from the drive. Also, HEX 01 is
loaded into sector register.

Vss

Ground

Vee

+5V±5%

Voo

+12V ±5%

WRITE ENABLE

A logic low on this input gates data on the DAL
into the selected register when CS is low.

CHIP SELECT

A logic low on this input selects the chip and enables computer communication with the device.

READ ENABLE

A logic low on this input controls the placement of
data from a selected register on the DAL when CS
is low.

5,6

AO, A1

These inputs select the register !2.... receivel
transfer data on the DAL lines under RE and WE
control:
WE
A1
AO
RE
Status Reg
Command Reg
0
0
Track Reg
1 Track Reg
0
Sector Reg
Sector Reg
1
0
Data Reg
Data Reg
1
1

7-14

DATA ACCESS LINES

DALe-DAL7

Eight bit inverted Bidirectional bus used for transfer of data, control, and status. This bus is receiver
enabled by WE or transmitter enabled by RE.

CLOCK

CLK

This input requires a free-running square wave
clock for internal timing reference, 2 MHz for 8"
drives, 1 MHz for mini-drives.

332

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

DATA REQUEST

DRQ

This open drain output indicates that the DR· contains assembled data in Read operations, or the
DR is empty in Write operations. This signal is
reset when serviced by the computer through
reading or loading the DR in Read or Write operations, respectively. Use 10K pull-up resistor to +5.

INTERRUPT
REQUEST

INTRQ

This open drain output is set at the completion of any
command and is reset when the STATUS register is
read or the command register is written to. Use 10K
pull-up resistor to +5.

FLOPPY DISK INTERFACE:

STEP

The step output contains a pulse for each step.

DIRECTION

DIRC

Direction Output is active high when stepping in,
active low when stepping out.

EARLY

Indicates that the WRITE DATA pulse occurring
while Early is active (high) should be shifted early
for write precompensation.

LATE

Indicates that the write data pulse occurring while
Late is active (high) should be shifted late for write
precompensation.

TEST

This input is used for testing purposes only and
should be tied to +5V or left open by the user unless interfacing to voice coil actuated motors.

HEAD LOAD TIMING

HLT

When a logic high is found on the HLT input the
head is assumed to be engaged.

READ GATE (1791/3)

A high level on this output indicates to the data
separator Circuitry that a field of zeros (or ones)
has been encountered, and is used for synchronization.

SIDE SELECT OUTPUT
(1795, 1797)

SSO

READ CLOCK

RCLK

RAW READ

The data input signal directly from the drive. This
input shall be a negative pulse for each recorded
flux transition.

HEAD LOAD

HLD

The HLD output controls the loading of the
Read-Write head against the media.

TRACK GREATER
THAN 43

TG43

This output informs the drive that the Read/Write
head is positioned between tracks 44-76. This output
is valid only during Read and Write Commands.

WRITE GATE

This output is made valid before writing is to be
performed on the diskette.

The logic level of the Side Select Output is directly
controlled by the 'S' flag in Type II or III commands.
When S = I, SSO is set to a logic 1. When S = 0,
SSO is set to a logic O. The Side Select Output is only
updated at the beginning of a Type II or III command.
It is forced to a logic 0 upon a MASTER RESET
condition.
A nominal square-wave clock signal derived from
the data stream must be provided to this input.
Phasing (Le. RCLK transitions) relative to RAW
READ is important but polarity (RCLK high or low)
is not.

333

PIN
NUMBER

PIN NAME

FUNCTION

SYMBOL

A 250 ns (MFM) or 500 ns (FM) pulse per flux
transition. WD contains the unique Address marks
as well as data and clock in both FM and MFM
formats.
This input indicates disk readiness and is sampled
for a logic high before Read or Write commands
are performed. If Ready is low the Read or Write
operation is not performed and an interrupt is
generated. Type I operations are performed regardless of the state of Ready. The Ready input
appears in inverted format as Status Register bit
7.
This is a bi-directional signal used to signify writing
faults at the drive, and to enable the external PLO
data separator. When WG = 1, Pin 33 functions as
a WF input. If WF = 0, any write command will immediately be terminated. When WG = 0, Pin 33 functions as a VFOE output. VFOE will go low during a
read operation after the head has loaded and settled
(HL T = 1). On the 1795/7, it will remain low until the
last bit of the second CRC byte in the ID field. VFOE
will then go high until 8 bytes (MFM) or 4 bytes (FM)
before the Address Mark. It will then go active until
the last bit of the second CRC byte of the Data Field.
On the 1791/3, VFOE will remain low until the end of
the Data Field.
This input informs the FD179X that the Read/Write
head is positioned over Track 00.

WRITE DATA

READY

WRITE FAULT
VFO ENABLE

TRACK 00

TROO

INDEX PULSE

II'

This input informs the FD179X when the index hole
is encountered on the diskette.

WRITE PROTECT

WPRT

This input is sampled whenever a Write Command
is received. A logic low terminates the command
and sets the Write Protect Status bit.

DOUBLE DENSITY

DDEN

This pin selects either single or double
eration. When DDEN = 0, double
selected. When DDEN = 1, single
selected. This line must be left open on

--WFNFOE

density opdensity is
density is
the 1792/4

ORGANIZATION
The Floppy Disk Formatter block diagram is illustrated on page 5. The primary sections include the
parallel processor interface and the Floppy Disk interface.
Data Shift Register-This 8-bit register assembles
serial data from the Read Data input (RAW READ)
during Read operations and transfers serial data to
the Write Data output during Write operations.
Data Register-This 8-bit register is used as a holding register during Disk Read and Write operations.
In Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations information is transferred in parallel from the Data Register
to the Data Shift Register.

When executing the Seek command the Data Register holds the address of the desired Track position.
This register is loaded from the DAL and gated onto
the DAL under processor control.
Track Registel'-This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents
of the register are compared with the recorded track
number in the ID field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAL. This Register should
not be loaded when the device is busy.

334

~N~~:~:~~

CONTROL

'NTERr"';:E
CONTR0\

CON1ROL

FD179X BLOCK DIAGRAM

The CRC includes all information starting with the
address mark and up to the CRC characters. The
CRC register is preset to ones prior to data being
shifted through the circuit.

Sector Register (SR)-This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector
number in the 10 field during disk Read or Write operations. The Sector Register contents can be loaded
from or transferred to the DAL. This register should
not be loaded when the device is busy.
Command Register (CR)-This 8-bit register holds
the command presently being executed. This register
should not be loaded when the device is busy unless
the new command is a force interrupt. The command
register can be loaded from the DAL, but not read
onto the DAL.
Status Register (STR)-This 8-bit register holds device Status information. The meaning of the Status
bits is a function of the type of command previously
executed. This register can be read onto the DAL,
but not loaded from the OAL.
CRC Logic-This logic is used to check or to generate the 16-bit Cyclic Redundancy Check (CRC). The
polynomial is: G(x) = x'· + x 12 + x 5 + 1.

Arithmetic/Logic Unit (ALU)-The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons with
the disk recorded 10 field.
Timing and Control-All computer and Floppy Disk
Interface controls are generated through this logic.
The internal device timing is generated from an external crystal clock.
The FD1791/3 has two different modes of~ation
according to the state of ODEN. WhenDDEN = 0
double density (MFM) is assumed. When !mEN 1,
single density (FM) is assumed.

AM Detector-The address mark detector detects
10, data and index address marks during read and
write operations.

335

PROCESSOR INTERFACE

HEAD POSITIONING

The interface to the processor is accomplished
through the eight Data Acces~nes (DAl) and associated control signals. The DAl are used to transfer Data, Status, and Control words out of, or into the
FDI79X. The DAl are three state buffers that are enabled as output drivers when Chip Select (CS) and
Read Enable (RE) are active (low logic state) or~t
as input receivers when CS and Write Enable (WE)
are active.
When transfer of data with the Floppy Disk Controller
is required by th~ost processor, the device address
is decoded and CS is made low. The address bits Al
and AO, combined with the signals RE during a Read
operation or WE during a Write operation are interpreted as selecting the following registers:

Five commands cause positioning of the Read-Write
head (see Command Section). The period of each
positioning step is specified by the r field in bits 1 and
a of the command word. After the last directional
step an additional 15 milliseconds of head settling
time takes place if the Verify flag is set in Type I
commands. Note that this time doubles to 30 ms for
a 1 MHz clock. If TEST = 0, there is zero settling
time. There is also a 15 ms head settling time if the E
flag is set in any Type II or III command.

Al-AO

READ (FiE)

a a
a

Status Register
Track Register
Sector Register
Data Register

WRITE (WE)
Command Register
Track Register
Sector Register
Data Register

During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD179X
and the processor, the Data Request (ORa) output is
used in Data Transfer control. This signal also appears as status bit 1 during Read and Write operations.
On Disk Read operations the Data Request is activated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after one or more
characters are lost, by having new data transferred
into the register prior to processor readout, the lost
Data bit is set in the Status Register. The Read operation continues until the end of sector is reached.
On Disk Write operations the data Request is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded
with new data by the processor. If new data is not
loaded at the time the next serial byte is required by
the Floppy Disk, a byte of zeroes is written on the
diskette and the lost Data bit is set in the Status Register.
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the
status register or by loading the command register
with a new command. In addition, INTRa is generated if a Force Interrupt command condition is met.

FLQPPY DISK INTERFACE
The 179X has two modes of 08DE~on according to the
= I, single density
state of tmE1iI (Pin 37). When
is selected. In either case, the ClK input (Pin 24) is at
2 MHz. However, when interfacing with the mini-floppy,
the ClK input is set at 1 MHz for both single density and
double density. When the clock is at 2 MHz, the stepping
rates of 3,6, la, and 15 ms are obtainable. When ClK
equals 1 .MHz these times are doubled.

The rates (shown in Table 1) can be applied to a
Step-Direction Motor through the device interface.
Step-A 2 /1S (MFM) or 4 /1S (FM) pulse is provided
as an output to the drive. For every step pulse issued, the drive moves one track location in a direction determined by the direction output.
Direction (D/RC)-The Direction signal is active high
when stepping in and low when stepping out. The Direction signal is valid 12 /1s before the first stepping
pulse is generated.
When a Seek, Step or Restore command is executed
an optional verification of Read-Write head position
can be performed by setting bit 2 (V 1) in the
command word to a logic 1. The verification operation
begins at the end of the 15 millisecond settling time
after the head is loaded against the media. The track
number from the first encountered ID Field is compared against the contents of the Track Register. If
the track numbers compare and the ID Field Cyclic
Redundancy Check (CRG) is correct, the verify operation is complete and an INTRa is generated with no
errors. The FD179X must find an ID field with correct
track number and correct CRC within 5 revolutions of
the media; otherwise the seek error is set and an
INTRa is generated.

Table 1. STEPPING RATES
2 MHz

2 MHz

1 MHz

, MHz

2 MHz

1 MHz

Rl RO TES.T=l

TEST=1

TEST=l

TEST~l

TEST=O

TEST =0

ClK

Di5EN
0 0

3 ms

6 ms

184J-15

6 ms

12 ms

190115

380P.5

1 0

10 ms

20 ms

198p.s

3 96115

15 ms

30 ms

2081-'5

416/-15

368115

The Head load (HlD) output controls the movement
of the read/write head against the media. HlD is activated at the beginning of a Type I command if the h
flag is set (h = 1). at the end of the Type I command
if the verify flag (V 1), or upon receipt of any Type
II or III command. Once HlD is active it remains active until either a Type I command is received with
(h = a and V = 0); or if the FD179X is in an idle state
(non-busy) and 15 index pulses have occurred.

336

Head Load Timing (HLT) is an input to the FD179X
which is used for the head engage time. When
HLT = 1. the FD179X assumes the head is completely engaged. The head engage time is typically
30 to 100 ms depending on drive. The low to high
transition on HLD is typically used to fire a one shot.
The output of the one shot is then used for HLT and
supplied as an input to the FDI79X.

HLD~
11---1

~50

i-I- - - -

TO lOOms--i

derived externally by Phase lock loops. one shots. or
counter techniques. In addition. a Read Gate Signal
is provided as an output (Pin 25) which can be used
to inform phase lock loops when to acquire synchronization. When reading from the media in FM. RG
is made true when 2 bytes of zeroes are detected.
The FD179X must find an address mark within the
next 10 bytes; otherwise RG is reset and the search
for 2 bytes of zeroes begins all over again. If an address mark is found within 10 bytes. RG remains true
as long as the FD179X is deriving any useful information from the data stream. Similarly for MFM. RG is
made active when 4 bytes of "00" or "FF" are detected. The FD179X must find an address mark
within the next 16 bytes. otherwise RG is reset and
search resumes.
During read operations (WG 0). the VFOE (Pin 33)
~vided for phase lock loop synchronization.
VFOE will go active when:
a) Both HLT and HLD are True
b) Settling Time. if programmed. has expired
c) The 179X is inspecting data off the disk
If WFIVFOE is not used, leave open or tie to a 10K
resistor to +5.

HL T lFROM ONE SHOT)

HEAD LOAD TIMING
When both HLD and HLT are true. the FD179X will
then read from or write to the media. The "and" of
HLD and HL T appears as a status bit in Type I
status.
In summary for the Type I commands: if h = a and
V = O. HLD is reset. If h = 1 and V = O. HLD is set at the
beginning of the command and HLT is not sampled nor
is there an internal 15 ms delay. If h a and V 1.
HLD is set near the end of the command. an internal
15 ms occurs. and the FD179X waits for HLT to be
true. If h = 1 and V = 1. HLD is set at the beginning
of the command. Near the end of the command. after
all the steps have been issued, an internal 15 ms
delay occurs and the FD179X then waits for HLT to
occur.

For Type II and III commands with E flag off. HLD is
made active and HLT is sampled until true. With E
flag on. HLD is made active, an internal 15 ms delay
occurs and then HLT is sampled until true.

DISK READ OPERATIONS
Sector lengths of 128. 256. 512 or 1024 are obtainable in either FM or MFM formats. For FM. DDEN
should be placed to logical "1." For MFM formats,
DDEN should be placed to a logical "a." Sector
lengths are determined at format time by a special
byte in the "ID" field. If this Sector length byte in the
ID field is zero. then the sector length is 128 bytes. If
01 then 256 bytes. If 02. then 512 bytes. If 03. then
the sector length is 1024 bytes. The number of sectors per track as far as the FD179X is concerned can
be from 1 to 255 sectors. The number of tracks as far
as the FD179X is concerned is from a to 255 tracks.
For IBM 3740 compatibility. sector lengths are 128
bytes with 26 sectors per track. For System 34 compatibility (MFM). sector lengths are 256 bytes/sector
with 26 sectors/track; or lengths of 1024 bytes/sector
with 8 sectors/track. (See Sector Length Table.)
For read operations. the FD179X requires RAW
READ Data (Pin 27) signal which is a 250 ns pulse
per flux transition and a Read clock (RCLK) signal to
indicate flux transition spacings. The RCLK (Pin 26)
signal is provided by some drives but if not it may be

DISK WRITE OPERATION
When writing is to take place on the diskette the
Write Gate (WG) output is activated. allowing current
to flow into the Read/Write head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in resp'Jnse to a Data Request
from the FD179X before the Write Gate signal can be
activated.
Writing is inhibited when the Write Protect input is a
logic low. in which case any Write command is immediately terminated. an interrupt is generated and
the Write Protect status bit is set. The Write Fault input. when activated. signifies a writing fault condition
detected in disk drive electronics such as failure to
detect write current flow when the Write Gate is activated. On detection of this fault the FD179X terminates the current command. and sets the Write Fault
bit (bit 5) in the Status Word. The Write Fault input
should be made inactive when the Write Gate output
becomes inactive.
For write operations. the FD179X provides Write
Gate (Pin 30) and Write Data (Pin 31) outputs. Write
data consists of a series of 500 ns pulses in FM
(DDEN 1) and 250 ns pulses in MFM (DDEN = 0).
Write Data provides the unique address marks in
both formats.
Also during write. two additional signals are provided
for write precompensation. These are EARLY (Pin
17) and LATE (Pin 18). EARLY is active true when
the WD pulse appearing on (Pin 30) is to be written
early. LATE is active true when the WD pulse is to be
written LATE. If both EARLY and LATE are low when
the WD pulse is present. the WD pulse is to be written at
nominal. Since write precompensation values vary from
disk manufacturer to disk manufacturer. the actual
value is determined by several one shots or delay lines
which are located external to the FD179X. The write
precompensation signals EARLY and LATE are valid
for the duration of WD in both FM and MFM formats.

337

Whenever a Read or Write command (Type II or III)
is received the FD179X samples the Ready input. If
this input is logic low the command is not executed
and an interrupt is generated. All Type I commands
are performed regardless of the state of the Ready
input. Also, whenever a Type II or IJI command is received, the TG43 signal output is updated.

Table 4 FLAG SUMMARY
TYPE II & III COMMANDS
m = Multiple Record flag (Bit 4)
m = 0, Single Record
m = 1, Multiple Records
ao = Data Address Mark (Bit 0)

ao = 0, FB (Data Mark)
ao = 1, Fa (Deleted Data Mark)

COMMAND DESCRIPTION
The FD179X will accept eleven commands. Command words should only be loaded in the Command
Register when the Busy status bit is off (Status bit 0).
The one exception is the Force Interrrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is reset. The Status Register indicates whether the completed command encountered an error or was fault
free. For ease of discussion, commands are divided
into four types. Commands and types are summarized in Table 2.

= 15 ms DelaY(2MHz)

E = 1, 15 ms delay
E = 0, no 15 ms delay
(F 2) S = Side Select Flag (1791/3 only)

S 0, Compare for Side 0
S = 'I~Coinpare for Side 1
(F,) C = Side Compare Flag
C
C

(1791/3 only)

= 0, disable side select compare
= 1, enable side select compare

(F,) S = Side Select Flag
(Bit 1, 1795/7 only)

Table 2 COMMAND SUMMARY

S = 0 Update SSO to 0

BITS
TYPE COMMAND
Restore
I
I
I
I
I
II
II
III
III
III
IV

Seek
Step
Step In
Step Out
Read Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrrupt

765 4 3
0 0 0 0 h
0 0 0 1 h
0 0 1 u h
0 1 o u h
0
1
1
1
1
1
1

2
V
V
V
V

S = 1 Update SSO to 1

1 0

r] ro

(F2) b

r, ro

= Sector Length

(Bit 3, 1975/7 only)

r] ro

1 1 u h V r, ro
0 m F2 E F, 0

0
0
1
1
1

1 m F2
000
1 0 0
1 1 o
1 0 1 I,

E
E
E
E
I,

Flag

F,
0
0
0
I,

Sector Length Field

ao
0
0
0

b=O

256

512

1024

128

b= 1

128

256

512

1024

Note: Bits shown in TRUE form.
Table 5 FLAG SUMMARY
Table 3 FLAG SUMMARY

TYPE IV COMMAND

TYPE I COMMANDS

Ii = Interrupt Condition flags (Bits 3-0)
10 = 1, Not-Ready to Ready TranSition
11 = 1, Ready to Not-Ready Transition
12 = 1, Index Pulse
13 = 1, Immediate Interrupt
13 -10 = 0, Terminate with no Interrupt

h = Head Load Flag (Bit 3)
h = 1, Load head at beginning
h = 0, Unload head at beginning
V = Verify flag (Bit 2)
V = 1, Verify on destination track
V = 0, No verify
r,ro = Stepping motor rate (Bits 1-0)

TYPE I COMMANDS

Refer to Table 1 for rate summary
u = Update flag (Bit 4)
u = 1, Update Track register
u = 0, No' update

The Type I Commands include the Restore, Seek,
Step, Step-In, and Step-Out commands. Each of the
Type I Commands contains a rate field (ron), which
determines the stepping, motor rate as defined in
Table 1.

338

10 field is then compared to the Track Register; if
there is a match and a valid 10 CRC, the verification
is complete, an interrupt is generated and the Busy
status bit is reset. If there is not a match but there is
valid 10 CRC, an interrupt is generated, and Seek
Error Status bit (Status bit 4) is set and the Busy
status bit is reset. If there is a match but not a valid
CRC, the CRC error status bit is set (Status bit 3),
and the next encountered 10 field is read from the
disk for the verification operation. If an 10 field with a
valid CRC cannot be found after four revolutions of
the disk, the FD179X terminates the operation and
sends an interrupt, (INTRQ).

The Type I Commands contain a head load flag (h)
which determines if the head is to be loaded at the
1, the head is
beginning of the command. If h
loaded at the beginning of the command (HLO output
is made active). If h = 0, HLO is deactivated. Once
the head is loaded, the head will remain engaged
until the F0179X receives a command that specifically disengages the head. If the F0179X is idle
(busy 0) for 15 revolutions of the disk, the head will
be automatically disengaged (HLD made inactive).

The Type I Commands also contain a verification (V)
flag which determines if a verification operation is to
take place on the destination track. If V 1, a verification is performed, if V = 0, no verification is performed.

During verification, the head is loaded and after an
internal 15 ms delay, the HL T input is sampled.
When HLT is active (logic true), the first encountered
10 field is read off the disk. The track address of the

The Step, Step-In, and Step-Out commands contain
an Update flag (U). When U 1, the track register is
updated by one for each step. When U 0, the track
register is not updated.

On the 1795/7 devices, the SSO output is not affected
during Type 1 commands, and an internal side compare does not take place when the (V) Verify Flag is
on.

COI,I~AND

SEEK

TYPE I COMMAND FLOW

339

RESTORE (SEEK TRACK 0)

SEEK

Upon receipt of this command the Track 00 (TROD)
input is sampled. If TROD is active low indicating the
Read-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is
generated. If TROD is not active low, stepping pulses
(pins 15 to 16) at a rate specified by the r,ro field are
issued until the fRl:iO input is activated. At this time the
Track Register is I~ with zeroes and an interrupt is
generated. If the TROD input does not go active low
after 255 stepping pulses, the FD 179X terminates operation, interrupts, and sets the Seek error status bit.
A verification operation takes place if the V flag is
set. The h bit allows the head to be loaded at the
start of command. Note that the Restore command is
executed when MR goes from an active to an inactive state.

This command assumes that the Track Register contains the track number of the current pOSition of the
Read-Write head and the Data Register contains the
desired track number. The FD179X will update the
Track register and issue stepping pulses in the appropriate direction until the contents of the Track register are equal to the contents of ihe Data Register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the command.
STEP
Upon receipt of this command, the FD179X issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the','o field, a
verification takes place if the V flag is on. If the u flag is
on, the Track Register is updated. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the command.
STEP-IN
Upon receipt of this command, the FD179X issues
one stepping pulse in the direction towards track 76.
If the u flag is on, the Track Register is incremented
by one. After a delay determined by the [1['0 field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the completion of the command.
STEP-OUT
Upon receipt of this command, the FD179X issues
one stepping pulse in the direction towards track O. If
the u flag is on, the Track Register is decremented by
one. After a delay determined by the r,ro field, a verification takes place if the V flag is on. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.

TYPE II COMMANDS

10 AM

The Type II Commands are the Read Sector and
Write Sector commands. Prior to loading the Type II
Command into the Command Register, the computer
must load the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
busy status Bit is set. If the E flag = 1 (this is the
normal case) HLD is made active and HLT is sampled after a 15 msec delay. If the E flag is 0, the
head is loaded and HLT sampled with no 15 msec
delay. The ID field and Data Field format are shown
on page 13.

6EE~

DETE~crED

00"

~-----=< A;;~E~~"g:IO
FIELD

NOTE IFnsT
if TEST

When an ID field is located on the disk, the FD179X
compares the Track Number on the ID field with the
Track Register. If there is not a match, the next en-

0 THEAE I$NO 19.1SDU"Y
1 AND elll
T !,AM, THER( 1<; ... 1OJ,I<., DtTAV

TYPE I COMMAND FLOW

340

countered 10 field is read and a comparison is again
made. If there was a match, the Sector Number of
the 10 field is compared with the Sector Register. If
there is not a Sector match, the next encountered 10
field is read off the disk and comparisons again
made. If the 10 field CRC is correct, the data field is
then located and will be either written into, or read
from depending upon the command. The F0179X
must find an 10 field with a Track number, Sector
number, side number, and CRC within four revolutions
of the disk; otherwise, the Record not found status bit is
set (Status bit3) and the command is terminated with an
interrupt.

·N01E

I'
If

fffi
rrsT

lHERf IS NO l~~""OH"Y
elll
I Mtil IHERE IS"lWS

, ANO

Sector Length Table
Sector Length
Number of Bytes
Field (hex)
in Sector (decimal)
128
00
01
256
512
02
1024
03

Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = 0, a single sector is read or written and an interrupt is generated at the completion of the command.
If m = 1, multiple records are read or written with the
sector register internally updated so that an address
verification can occur on the next record. The
F0179X will continue to read or write multiple records
and update the sector register until the sector regis-

OHAr

TYPE II COMMAND

341

ter exceeds the number of sectors on the track or
until the Force Interrupt command is loaded into the
Command Register, which terminates the command
and generates an interrupt.
If the Sector Register exceeds the number of sectors
on the track, the Record-Nat-Found status bit will be
set.
The Type II commands also contain side select compare flags. When C = 0, no side comparison is made.
When C = 1, the LSB of the side number is read off the
ID Field of the disk and compared with the contents of
the (S) flag. If the S flag compares with the side number
recorded in the ID field, the 179X continues with the
ID search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.
The 1795/7 READ SECTOR and WR ITE SECTOR commands include a 'b' flag. The 'b' flag, in conjunction with
the sector length byle of the ID Field, allows different
byle lengths to be implemented in each sector. For IBM
compatability, the 'b' flag should be set to a one. The

's' flag allows direct control over the 5'50 Una (Pin 25)
and is set or reset at the beginning of the command,
dependent upon the value of this flag.
READ SECTOR
Upon receipt of the Read Sector command, the head
is loaded, the Busy status bit set, and when an 10
field is encountered that has the correct track
number, correct sector number, correct side number,
and correct CRC, the data field is presented to the
computer. The Data Address Mark of the data field must
be found within 30 byles in single density and 43 byles in
double density of the last 10 field CRC byle; if not, the
Record Not Found status bit is set and the operation is
terminated.
When the first character or byle of the data field has
been shifted through the DSR, it is transferred to the
DR, and DRO is generated. When the next byle is
accumulated in the DSR, it is transferred to the DR
and another DRO is generated. If the Computer has
not read the previous contents of the DR before a
new character is transferred that character is lost and

>--''''--~~ INTRQ, RESEr BUSY

TYPE II COMMAND

342

the Lost Data Status bit is set. This sequence continues until the complete data field has been inputted
to the computer. If there is a CRC error at the end of
the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).

next encountered 10 field is then read in from the
disk, and the six data bytes of the 10 field are assembled and transferred to the DR, and a ORO is
generated for each byte. The six bytes of the 10 field
are shown below:

At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recorded in the Status Register (Bit 5) as shown below:
STATUS
BIT 5
1

Although the CRC characters are transferred to the
computer, the FD179X checks for validity and the
CRC error status bit is set if there is a CRG error.
The Track Address of the 10 field is written into the
sector register. At the end of the operation an interrupt is generated and the Busy Status is reset.

Deleted Data Mark
Data Mark

WRtTE SECTOR
Upon receipt of the Write Sector command, the head
is loaded (HLD active) and the Busy status bit is set.
When an 10 field is encountered that has the correct
track number, correct sector number, correct side number, and correct CRC, a ORO is generated. The FD179X
counts off 11 bytes in single density and 22 bytes in
double density from the CRC field and the Write Gate
(WG) output is made active if the ORO is serviced (i.e.,
the DR has been loaded by the computer). If ORO has
not been serviced, the command is terminated and the
Lost Data status bit is set. If the ORO has been serviced, the WG is made active and six bytes of zeros
in single densitv and 12 bytes in double density are
then written on Ine disk. At mis time the Data Address Mark is then written on the disk as determined
by the ao field of the command as shown below:
ao
1

Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark

The FD179X then writes the data field and generates
DRO's to the computer. If the ORO is not serviced in
time for continuous writing the Lost Data Status Bit is
set and a byte of zeros is written on the disk. The
command is not terminated. After the last data byte
has been written on the disk, the two-byte CRC is
computed internally and written on the disk followed
by one byte of logic ones in FM or in MFM. The WG
output is then deactivated.

TYPE III COMMANDS
READ ADDRESS
Upon receipt of the Read Address command, the
head is loaded and the Busy Status Bit is set. The

READ TRACK
Upon receipt of the Read Track command, the head
is loaded and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
Index pulse and continues until the next index pulse.
As each byte is assembled it is transferred to the
Data Register and the Data Request is generated for
each byte. No CRC checking is performed. Gaps are
included in the input data stream. The accumulation
of bytes is synchronized to each Address Mark encountered. Upon completion of the command, the interrupt is activated. RG is not activated during the
Read Track Command. An internal side compare is not
performed during a Read Track.
WRITE TRACK
Upon receipt of the Write Track command, the head
is loaded and the Busy Status bit is set. Writing
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse,
at which time the interrupt is activated. The Data Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the
DR has not been loaded by the time the index pulse
is encountered the operation is terminated making
the device Not Busy, the Lost Data Status Bit is set,
and the Interrupt is activated. If a byte is not present
in the DR when needed, a byte of zeros is substituted. Address Marks and CRC characters are written on the disk by detecting certain data byte patterns in the outgoing data stream as shown in the
table below. The CRC generator is initialized when
any data byte from FB to FE is about to be transferred from the DR to the DSR in FM or by receipt of
F5 in MFM.

ICRC I CRC
GAPT 1011 TRACK:I SIDE IISECTORIISECTORICRCICRCIGAPIDATA
III
AM NUMBER NUMBER NUMBER LENGTH 1
2
II
AM DATA FIELD
1
2
10 FIELD
DATA FIELD
In MFM only, lOAM and DATA AM are preceded by three bytes of AI with clock transition between bits 4 and 5
missing.

343

NOfFMI

DIS/(

'NTRO

REAOY

RESHBU$Y

,NOEK
PULSE

OCCUREO

."t·!'
f'",,·,,·

WP,.T

SET 1"'1"0

lOST OAT'"
RESET BUSY

TYPE III COMMAND WRITE TRACK
TYPE III COMMAND WRITE TRACK
CONTROL BYTES FOR INITIALIZATION
DATA PATIERN
IN DR (HEX)
00 thru F4
F5
F6
F7
Fa thru FB
FC
FD
FE
FF

FD179X INTERPRETATION
IN FM (DDEN
1)

FD1791/31NTERPRETATION
IN MFM (00I:fii
0)

=
Write 00 thru F4 with CLK = FF

Not Allowed
Not Allowed
Generate 2 CRC bytes
Write Fa thru FB, Clk ~ C7, Preset CRC
Write FC with Clk
07
FF
Write FD with elk
Write FE, elk C7, Preset CRe
Write FF with elk
FF

=
=
=
=

Write 00 thru F4, in MFM
Write A1' in MFM, Preset CRC
Write C2'* in MFM
Generate 2 CRCbytes
Write Fa thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM

., Missing clock transition between bits 3 & 4

'Missing clock transition· between bits 4 and 5

344

INTRQ
RESET BUSY

SET INTRQ
RESET BUSV

READ
ADDRESS

"It TEST= •. NO DElAY
If TEST." 1 and eLK= 1 MHZ. 30 MS OELA V

TYPE III COMMAND
Read Track/Address

345

TYPE IV COMMAND
FORCE INTERRUPT

RESET BUSY
SET INTRQ
SET RNF

This command can be loaded into the command register at any time. If there is a current command
under execution (Busy Status Bit set), the command
will be terminated and an interrupt will be generated
when the condition specified in ·the 10 through " field
is detected. The interrupt conditions are shown below:

= Not-Ready-To-Ready Transition
= Ready-To-Not-Ready Transition
" = Every Index Pulse
" = Immediate Interrupt (requires
10
I,

reset, see
Note)
NOTE: If 10 - " = 0, there is no interrupt generated but
the current command is terminated and busy is
reset. This is the only command that will enable
the immediate interrupt to clear on a subsequent Load Command Register or Read Status
Register.
STATUS DESCRIPTION
Upon receipt of any command, except the Force Interrupt command, the Busy Status bit is set and the
rest of the status bits are updated or cleared for the
new command. If the Force Interrupt Command is
received when there is a current commarid uOider
execution, the Busy status bit is reset, and the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there is not a current
command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or
cleared. In this case, Status reflects the Type I commands.

The format of the Status Register is shown belOW:

Status varies according to the type of command executed as shown in Table 6.

SET INTRQ
RESET BUSY

TYPE III COMMAND

Read Track/Address

346

FORMATTING THE DISK

IBM 3740 FORMAT-128 BYTES/SECTOR

(Refer to section on Type III commands for flow diagrams.)

Shown below is the IBM single-density format with
128 bytes/sector. In order to format a diskette, the
user must issue the Write Track command, and load
the data register with the following values. For ever)
byte to be written, there is one data request.

Formatting the disk is a relatively simple task when
operating programmed I/O or when operating under
Formatting the disk is accomplished by positioning
the R/W head over the desired track number and issuing the Write Track command. Upon receipt of the
Write Track command, the FD179X raises the Data
Request signal. At this point in time, the user loads
the data register with desired data to be written on
the disk. For every byte of information to be written
on the 'disk, a data request is generated. This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears
in the data register is written on the disk with a normal clock pattern. However, if the FD179X detects a
data pattern of F5 thru FE in the data register, this is
interpreted as data address marks with missing
clocks or CRC generation. For instance, in FM an FE
pattern will be interpreted as an 10 address mark
(DATA-FE, ClK-C7) and the CRC will be initialized.
An F7 pattern will generate two CRC characters in
FM or MFM. As a consequence, the patterns F5 thru
FE must not appear in the gaps, data fields, or 10
fields. Also, CRC's must be generated by an F7 pattern.
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128, 256, 512, or 1024
bytes.

NUMBER
OF BYTES
40
6
1
26
6
1
1
1
1
1

1
11

6
1
128
1
27
247"

HEX VALUE OF
BYTE WRIDEN
FF (or DO)'
00
FC (Index Mark)
FF (or 00)
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru lA)
00
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)
FF (or 00)

'Write bracketed field 26 times
"Continue writing until FD179X interrupts out.
Approx. 247 bytes.
I-Optional '00' on 1795/7 only .

.-""~

"·,,,,·,·H

IBM TRACK FORMAT

347

IBM SYSTEM 34 FORMAT·
256 BYTES/SECTOR

1. NON-IBM FORMATS
Variations in the IBM format are possible to a limited
exlent ~ the following requirements are met: sector
size must be a choice of 128, 256,512, or 1024 bytes;
gap size must be according to the following table. Note
that the Index Mark is not required by the 179X. The
minimum gap sizes shown are that which is required by
the 179X, with PLL lock-up time, motor speed variation,
etc., adding additional bytes.

Shown below is the IBM dual-density format with 256
bytes/sector. In order to format a diskette the user
must issue the Write Track command and load the
data register with the following values. For every byte
to be written, there is one data request.

NUMBER
OF BYTES
80
12
3
1
50·

3
1
1
1
1
1
1
22
12
3
1
256
1
54

's9a**

HEX VALUE OF
BYTE WRITTEN
4E
00
F6
FC (Index Mark)
4E
00
F5
FE (ID Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01
F7 (2 CRCs written)
4E
00
F5
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E

MFM

Gap I

16 bytes FF

32 bytes4E

Gap 1\

11 bytes FF

22 bytes4E

6 bytes 00

12 bytes 00
3 bytes A1

Gap 11\

10 bytes FF

24 bytes4E
3 bytes Al

4 bytes 00

8 bytes 00

16 bytes FF

16 bytes4E

**
Gap IV

• Write bracketed field 26 times

• Byte counts must be exact.
•• Byte counts are minimum, except exactly 3 bytes
of A1 must be written.

*. Continue writing until FD179X interrupts out.
Approx. 598 bytes.

ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Voo With Respect to Vss (Ground) =15 to -0.3V

Max. Voltage to Any Input With
Respect to Vss

=15 to -0.3V

VDD = ID ma Nominal

= 35 ma Nominal

VCC

DOC to 700 C
-550 C to +1250 C

Operating Temperature
Storage Temperature

OPERATING CHARACTERISTICS (DC)
TA

= O°C to 70°C, Voo = + 12V:±:
SYMBOL
III
IoL
V,H
VIL
VOH
VOL
Po

.6V, Vss

= OV,

CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation

Vee

= + 5V

MIN.

:±: .25V

MAX.
10
10

2.6
0.8
2.8
0.45
0.5

348

UNITS
/LA
/LA
V
V
V
V
W

CONDITIONS
V,N - Voo
VOUT Voo

10 = -100 /LA
10 = 1.6 mA

TIMING CHARACTERISTICS
TA = OOC to 70°C. Voo = + 12V

.BV. Vss = OV. Vee =+5V ± .25V

READ ENABLE TIMING
SYMBOL
TSET
THLD
TRE
TDRR
TIRR
TDACC
TDOH

CHARACTERISTIC

MIN.

Setup ADDR & CS to RE
Hold ADDR & CS from RE
RE Pulse Width
DRQ Reset from RE
INTRQ Reset from RE
Data Access from RE
Data Hold From RE

TYP.

MAX.

UNITS

500
3000
350
150

nsec
nsec
nsec
nsec
nsec
nsec
nsec

50
10
400
400
500
50

... - - t - . ,

,=---+--j
.. OTE 1

CS ...... y

liE F>ER ........ HHly TIEO lOW IF DESIRED

READ ENABLE TIMING

349

CONDITIONS

CL=50pf
See Note 5
CL=50pf
CL=50pf

WRITE ENABLE TIMING
SYMBOL

CHARACTERISTIC

TSET
THLD
TWE
TORR
TIRR
TOS
TDH

Setup ADDR & CS to WE
Hold ADDR & CS from WE
WE Pulse Width
ORO Reset from WE
INTRa Reset from WE
Data Setup to WE
Data Hold from WE

INPUT DATA TIMING'
SYMBOL
CHARACTERISTIC
Tpw

Raw Read Pulse Width

tbe

Raw Read Cycle Time

MIN.

TYP.

MAX.

UNITS

50
10
350
400
500

500
3000

MIN.

TYP.

MAX.

100

200

nsee

See Note 1

1500
1500

nsee

1800 ns @ 700 e
1800 ns @ 700 e

250
70

See Note 5

UNITS

RCLK Cycle Time

TXl

RCLK hold to Raw Read

nsee

TX2

Raw Read hold to RCLK

nsee

CONDITIONS

See Note 1

f---~'"'I

'".---1 I-RAW READ

-j '"

t==',,--j

[

ACllI

CONDITIONS

nsec
nsec
nsec
nsec
nsee
nsee
nsee

!--"

1•

" --I

--+-~

"" -----+--1

NOMINAL
DISKETTE
8"
8"

5"
5"

MODE
MFM
FM
MFM
FM

DDEN

,
,
0
0

elK
2 MHz
2 MHz
1 MHz
, MHz

350

2~s

4~s

2~s

4,..
8 ~s

INPUT DATA TIMING
WRITE ENABLE TIMING

1 ~s
2 ~s

2 ~s

WRITE DATA TIMING: (ALL TIMES DOUBLE WHEN eLK

= 1 MHz)

SYMBOL

CHARACTERISTICS

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Twp

Write Data Pulse Width

450
150

550
250

Twg

Write Gate to Write Data

Tbc
Ts
Th

nsec
nsec
f!sec
f!sec
f!sec
nsec

nsec

FM
MFM
FM
MFM
:!:ClK Error
MFM
MFM

Twf

Write data cycle Time
Early (late) to Write Data
Early (Late) From
Write Data
Write Gate off from WD

500
200
2
1
2,3,or4

f!sec
JLsec

FM
MFM

Twdl

WD Valid to Clk

Twd2

WD Valid after ClK

125
125
2
1

nsec
nsec
nsec
nsec

100
50
100
30

f--SOONS

eLK
(IMHZ)

I
~

TWdl--1

I ~o:;a
1 r-Twd2

r--125- ..·--i-1"--125-1

eLK
(2MHZ)

TWdl~

WRITE DATA/CLOCK RELATIONSHIP

(DDEN= 0)

WRITE DATA TIMING

351

Twd2

ClK=1
CLK=2
CLK=1
ClK=2

MHZ
MHZ
MHZ
MHZ

MISCELLANEOUS TIMING:
SYMBOL
TCD,
TCD2
TSTP
TDIR
TMR
TIP
TWF

CHARACTERISTIC
Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width

MIN.

TYP.

MAX.

230
200
20r4

250
250

20000
20000

12
50
10
to

UNITS

CONDITIONS

nsec
nsec
p'sec
p'sec
p'sec
p.sec
p'sec

See Note 5
±CLKERROR
See Note 5

.----JJ ".

;;; JI-----,

r--',e~-I

,
I~-'w'

" -----JJ , ..

-I

" -----J$ ,,,.

1-- 'M" .. -1

:;:

~ '"'""

J ~L--_

,- '"" -1',,,1---1'"'' f--

f- ',," -1""'1-

~~
MISCELLANEOUS TIMING

NOTES:
1. Pulse width on RAW READ (Pin 27) is normally
100-300 ns. However, pulse may be any width if
pulse is entirely within window. If pulse occurs in both
windows, then pulse width must be less than 300 ns
for MFM at ClK = 2 MHz and 600 ns for FM at 2
MHz. Times double for 1 MHz.
2. A PPL Data Separator is recommended for 8" MFM.

3. tbc should be 2 P.s, nominal in MFM and 4 P.s nominal
in FM. Times double when ClK = 1 MHz.
4. RCLK may be high or low during RAW READ (Polarity
is unimportant).
5. Times double when clock = 1 MHz.

352

Table 6 STATUS REGISTER SUMMARY
ALL TYPE I
READ
COMMANDS
ADDRESS
BIT
S7 NOT READY
NOT READY
0
S6 WRITE
PROTECT
0
S5 HEAD LOADED
S4 SEEK ERROR RNF
CRC ERROR
S3 CRC ERROR
S2
Sl

TRACK 0
INDEX

LOST DATA
DRO

BUSY

READ
SECTOR
NOT READY
0
RECORD TYPE
RNF
CRC ERROR
LOST DATA
DRO
BUSY

READ
TRACK
NOT READY
0
0
0
0
LOST DATA
DRO
BUSY

WRITE
TRACK

WRITE
SECTOR
NOT READY
WRITE
PROTECT

NOT READY
WRITE
PROTECT

WRITE FAULT

RNF
CRC ERROR
LOST DATA

0
0
LOST DATA

DRO
BUSY

STATUS FOR TYPE I COMMANDS
BIT NAME
S7 NOT READY

MEANING
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.

S6 PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.

S5 HEAD LOADED
S4 SEEK ERROR

When set, the desired track was not verified. This bit is reset to 0 when updated.

S3 CRC ERROR
S2 TRACK 00

CRC encountered in ID field.
When set, indicates Read/Write head is positioned to Tracl< O. This bit is an inverted
copy of the TROO input.
~hen set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.

S11,NDEX
SO BUSY

When set command is in progress. When reset no command is in progress.

STATUS FOR TYPE II AND III COMMANDS
BIT NAME
MEANING
S7 NOT READY

This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
S6 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
S5 RECORD TYPE/
WRITE FAULT

On Read Record: It indicates the record-type code from data field address mark.
1 Deleted Data Mark. 0 Data Mark. On any Write: It indicates a Write Fault. This bit
is reset when updated.

S4 RECORD NOT
FOUND (RNF)
S3 CRC ERROR

When set, it indicates that the desired track, sector, or side were not found. This bit is
reset when updated.
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in
data field. This bit is reset when updated.

S2 LOST DATA

When set, it indicates the computer did not respond to DRO in one byte time. This bit is
reset to zero when updated.

Sl DATA REOUEST This bit is a copy of the DRO output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when updated.
SO BUSY
When set, command is under execution. When reset, no command is under execution.

353

. J::::::O::::::J :;
00'

t~~

,." ~:::::: :0:::: :
OOT

200
MAX

L~J
r--~ I I ~~ I I ~~!~ ~ ~~ ~ ~~ ~~~-T
015
MIN

090

j:w --l

I-

055

-II--

--lI-- ~
021

125
MIN

FD179XA-02 CERAMIC PACKAGE

FD179XB-02 PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is
completed.
InformaUon furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by

Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

354

WESTERN DIGITAL
c

FD179X Application Notes
!fl

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -. . . 0

Ii
w

INTRODUCTION

Over the past several years, the Floppy Disk Drive has
become the most popular on-line storage device for
mini and microcomputer systems. Its fast access time,
reliability and low cost-per-bit ratio enables the Floppy
Disk Drive to be the solution in mass storage for microprocessor systems. The drive interface to the Host
system is standardized, allowing the OEM to substitute
one drive for another with minimum hardware/ software
modifications.
.
Since Floppy Disk Data is stored and retrieved as a
self-clocking serial data stream, some means of separating the clock from the data and assembling this
data in parallel form must be accomplished. Data is
stored on individual Tracks of the media, requiring control of a stepper motor to move the Read/Write head
to a predetermined Track. Byte sychronization must
also be accomplished to insure that the parallel data
is properly assembled. After all the design considerations are met, the final controller can consist of 40 or
more TTL packages.
To alleviate the burden of Floppy Disk Controller design, Western Digital has developed a Family of LSI
Floppy Disk controller devices. Through its own set of
macro commands, the FD179X Controller Family will
perform all the functions necessary to read and write
data to the drive. Both the 8" standard and 5%" minifloppy are supported with single or double density recording techniques. The FD179X is compatible with
the IBM 3740 (FM) data format, or the System 34
(MFM) standards. Provisions for non-standard formats
and variable sector lengths have been included to provide more storage capability per track. Requiring standard +5, +12 power supplies the FD179X is available
in a standard 40 pin dual-in-line package.
The FD179X Family consists of 6 devices. The
differences between these devices is summarized in
Figure 1. The 1792 and 1794 are "single density only"
devices, with the Double Density Enable pin (DDEN)
left open by the user. Both True and inverted Data bus
devices are available. Since the 179X can only drive
one TTL Load, a true data bus system may use the
1791 with external inverting buffers to arrive at a true
bus scheme. The 1795 and 1797 are identical to the
1791 and 1793, except a side select output has been
added that is controlled through the Command Register.

SYSTEM DESIGN

>
The first consideration in Floppy Disk Design is to de- ~
termine which type of drive to use. The choice ranges
from single-density single sided mini-floppy to the 8"
double-density double-sided drive. Figure 2 illustrates
the various drive and data capacities associated with
each type. Although the 8" double-density drive offers
twice as much storage, a more complex data separator
and the addition of Write Precornpensation circuits are
mandatory for reliable data transfers. Whether to go
with 8" double-density or not is dependent upon PC
board space and the additional circuitry needed to accurately recover data with extreme bit shifts. The byte
transfer time defines the nominal time required to
transfer one byte of data from the drive. If the CPU
used cannot service a byte in this time, then a DMA
scheme will probably be required. The 179X also needs
a few microseconds for overhead, which is subtracted
from the transfer time. Figure 3 shows the actual service times that the CPU must provide on a byte-by-byte
basis. If these times are not met, bytes of data will be
lost during a read or write operation. For each byte
transferred, the 179X generates a DRO (Data Request) signal on Pin 38. A bit is provided in the status
register which is also set upon receipt of a byte from
the Disk. The user has the option of reading the status
register through program control or using the DRO Line
with DMA or interrupt schemes. When the data register
is read, both the status register DRO bit and the DRO
Line are automatically reset. The next full byte will
again set the DRO and the process continues until the
sector(s) are read. The Write operation works exactly
the same way, except a WRITE to the Data Register
causes a reset of both DRQ's.

RECORDING FORMATS

The FD179X accepts data from the disk in a Frequency-Modulated (FM) or Modified-Frequency-Modulated (MFM) Format. Shown in Figures 4A and 4B are
both these Formats when writing a Hexidecimal byte
of 'D2'. In the FM mode, the 8 bits of data are broken
up into "bit cells." Each bit cell begins with a clock
pulse and the center 'of the bit cell defines the data. If
the data bit = 0, no pulse is written; if the data = 1,
a pulse is written in the center of the cell. For the 8"
drive, each clock is written 4 microseconds apart.

355

In the MFM mode, clocks are decoded into the data
stream. The byte is again broken up into bit cells, with
the data bit written in the center of the bit cell if data
= 1. Clocks are only written if both surrounding data
bits are zero. Figure 4B shows that this occurs only
once between Bit cell 4 and 5. Using this encoding
scheme, pulses can occur 2, 3 or 4 microseconds
apart. The bit cell time is now 2 microseconds; twice
as much data can be recorded without increasing the
Frequency rate due to this encoding scheme.
The 179X was designed to be compatible with the IBM
3740 (FM) and System 34 (MFM) Formats. Although
most users do not have a need for data exchange with
IBM mainframes, taking advantage of these well studied formats will insure a high degree of system
performance. The 179X will allow a change in gap
fields and sector lengths to increase usable storage
capacity, but variations away from these standards is
not recommended. Both IBM standards are soft-sector
format. Because of the wide variation in address marks,
the 179X can only support soft-sectored media. Hard
sectored diskettes have continued to lose popularity,
mainly due to the unavailability of a standard and the
limitation of sector lengths imposed by the physical
sector holes in the diskette.
PROCESSOR INTERFACE
The Interface of the 179X to the CPU consists of an
8-bit Bi-directional bus, read/write controls and optional
interrupt lines. By selecting the device via the CHIP
SELECT Line, each of the five internal registers can
be accessed.

Shown below are the registers and their addresses:
PIN 3 PIN 6 PIN 5
CS
A,
Ao

a
a
a
a
1

a
a
1
1
X

!a
1

a
1
X

PIN 4
RE=ff
STATUS REG
TRACK REG
SECTOR REG
DATA REG
Hl-Z

PIN 2
WE~

COMMAND
REG
TRACK REG
SECTOR REG
DATA REG
Hl-Z

The Ao, A" Lines used for register selections can be
configured at the CPU in a variety of ways. These lines
may actually tie to CPU address lines, in which case
the 179X will be memory-mapped and addressed like
RAM. They may also be used under Program Control
by tying to a port device such as the 8255, 6820, etc.
As a diagnostic tool when checking out the CPU interface, the Track and Sector registers should respond
like "RAM" when the 179X is idle (Busy = INTRa =
0).
Because of internal synchronization cycles, certain
time delays must be introduced when operating under
Programmed I/O. The worst case delays are:

OPERATION

NEXT
OPERATION

WRITE TO
COMMAND REG
WRITE TO
!ANY REGISTER

READ STATUS
MFM = 14f.Ls"
REGISTER
FM = 28f.Ls.
READ FROM A
NO DELAY
DIFFERENT REG

DELAY REa'D

"NOTE: Times Double when ClK = 1MHz (51f4" drive)
Other CPU interface lines are ClK, MR and DDEN.
The ClK line should be 2MHz (8" drive) or lMHz (51f4"
drive) with a 50% duty cycle. Accuracy should be ±1%
(crystal source) since all internal timing, including stepping rates, are based upon this clock.
The MR or Master Reset Line should be strobed a
minimum of 50 microseconds upon each power-on
condition. This line clears and initializes all internal registers and issues a restore command (Hex '03') on the
rising edge. A quicker steppin9....@.te can be written to
the command register after a MR, in which case the
remaining steps will occur at the faster programmed
rate. The 179X will issue a maximum of 255 stepping
pulses in an attempt to expect the TROO line to go
active low. This line should be connected to the drive's
TROO sensor.
The DDEN line causes selection of either single density (DDEN = 1) or double density operation. DDEN
should not be switched during a read or write operation.

Each time a command is issued to the 179X, the Busy
bit is set and the INTRa (Interrupt Request) Line is
reset. The "user has the option of checking the busy bit
or use the INTRa Line to denote command completion. The Busy bit will be reset whenever the 179X is
idle and awaiting a new command. The INTRa Line,
once set, can only be reset by a READ of the status
register or issuing a new command. The MR (Master
Reset) Line does not affect INTRa.

356

FLOPPY DISK INTERFACE
The Floppy Disk Interface can be divided into three
sections: Motor Control, Write Signals and Read Signals. All of these lines are capable of driving one TTL
load and not compatible for direct connection to the
drive. Most drives require an open-collector TTL interface with high current drive capability. This must be
done on all outputs from the 179X. Inputs to the 179X
may be buffered or tied to the Drives outputs, providing
the appropriate resistor termination networks are used.
Undershoot should not exceed -0.3 volts, while integrity of V, Hand VOH levels shou Id be kept within spec.
MOTOR CONTROL
Motor Control is accomplished by the STEP and DIRC
Lines. The STEP Line issues stepping pulses with a
period defined by the rate field in all Type I commands.
The DIRC Line defines the direction of steps (DIRC =
1 STEP IN/DIRC = a STEP OUT).
Other Control Lines include the iP or Index Pulse. This
Line is tied to the drives' Index L.ED. sensor and
makes an active transition for each revolution of the
diskette. The TROO Line is another L.E.D. sensor that
informs the 179X that the stepper motor is at its furthest position, over Track 00. The READY Line can be
used for a number of functions, such as sensing "door
open", Drive motor on, etc. Most drives provide a programmable READY Signal selected by option jumpers
on the drive. The 179X will look at the ready signal prior
to executing READ/WRITE commands. READY is not
inspected during any Type I commands. All Type I
commands will execute regardless of the Logic Level
on this Line.
WRITE SIGNALS
Writing of data is accomplished by the use of the WD,
WG, WF, TG43, EARLY and LATE Lines. The WG or
Write Gate Line is used to enable write current at the
drive's R/W head. It is made active prior to writing data
on the disk-, The WF or WRITE FAULT Line is used to
inform the 179X of a failure in drive electronics. This
signal is multiplexed with the VFOE Line and must be
logically separated if required. Figure 5 illustrates three
methods of demultiplexing.
The TG43 or "TrACK GREATER than 43" Line is
used to decrease the Write current on the inner tracks,
where bit densities are the highest. ~ not required on
the drive, TG43 may be left open.
WRITE PRECOMPENSATION
The 179X provides three signals for double density
Write Precompensation use. These signals are WRITE
DATA, EARLY and LATE. When using single density
drives (eighter 8" or 5'14"), Write Precompensation is
not necessary and the WRITE DATA line is generally
TTL Buffered and sent directly to -the drive. In this
mode, EARLY and LATE are left open.
For double density use, Write Precompensation is a
function of the drive. Some manufacturers recommend
Precompensating the 5%" drive, while others do not.
With the 8" drive, Precompensation may be specified
from TRACK 43 on, or in most cases, all TRACKS. If
the recommended Precompensation is not specified,

357

check with the manufacturer for the proper configuration required.
The amount of Precompensation time also varies. A
typical value will usually be specified from 100-300ns.
Regardless of the parameters used, Write Precompensation must be done external to the 179X. When
DDEN is tied low, EARLY or LATE will be activated at
least 125ns. before and after the Write Data pulse. An
Algorithm internal the 179X decides whether to raise
EARLY or LATE, depending upon the previous bit pattern sent. As an example, suppose the recommended
Precomp value has been specified at 150ns. The following action should be taken:
EARLY

LATE

a
a

1
a

ACTION TAKEN
delay WD by 150ns (nominal)
delay WD by 300ns (2X value)
do not delay WD

There are two methods of performing Write
Precompensation:
1) External Delay elements
2) Digitally
Shown in Figure 6 is a Precomp circuit using the Western Digital 2143 clock generator as the delay element.
The WD pulse from the 179X creates a strobe to the
2143, causing subsequent output pulses on the.61 ,.62
and .03 signals. The 5K Precomp adjust sets the desired Precomp value. Depending upon the condition of
EARLY and LATE,,O'1 will be used for EARLY,.ff2 for
nominal (EARLY = LATE = 0), and.ff3 for LATE. The
use of "one-shots" or delay line in a Write Precompensation scheme offers the user the ability to vary the
Precomp value. The .ff4 output resets the 74LS175
Latch in anticipation of the next WD pulse. Figure 7
shows the WD-EARLYlLATE relationship, while Figure
8 shows the timing of this write .Precomp scheme.
Another method of Precomp is to perform the function
digitally. Figure 9 illustrates a relationship between the
WD pulse and the CLK pin, allowing adigital Precomp
scheme. Figure 10 shows such a scheme with a preset Write Precompensation value of 250ns. The synchronous counter is used to generate 2M Hz and 4MHz
clock signals. The 2M Hz clock is sent to the CLK input
of the 179X and the 4MHz is used by the 4-bit shift
register. When a WD pulse is not present, the 4MHz
clock is shifting "ones" through the shift register and
maintaining Q D at a zero level. When a WD pulse is
present, a zero is loaded at either A, B, or C depending
upon the states of LATE, EN PRECOMP and EARLY.
The zero is then shifted by the 4MHz clock until it
reaches the Q D output. The number of shift operations
determines whether the WRITE DATA pulse is written
early, nominal or late. If both FM and MFM operations
is a system requirement, the output of this circuit should
be disabled and the WD pulse should be sent directly
to the drive.

DATA SEPARATION
The 179X has two inputs (RAW READ & RCLK) and
one output (VFOE) for use by an external data separator. The RAW READ input must present clock and
data pulses to the 179X, while the RCLK input provides
a "window" or strobe signal to clock each RAW READ
pulse into the device. An ideal Data Separator would
have the leading edge of the RAW READ pulse occur
in the exact center of the RCLK strobe.
Motor Speed Variation, Bit shifts and read amplifier
recovery circuits all cause the RAW READ pulses to
drift away from their nominal positions. As this occurs,
the RAW READ pulses will shift left or right with respect to RCLK. Eventually, a pulse will make its transition outside of its RCLK window, causing either a
CRC error or a Record-not-Found error at the 179X.
A Phase-Lock-Loop circuit is one method of achieving
synchronization between the RCLK and RAW READ
signals. As RAW READ pulses are fed to the PLL,
minor adjustments of the free-running RCLK frequency
can be made. If pulses are occurring too far apart, the
RCLK frequency is decreased to keep synchronization. If pulses begin to occur closer together, RCLK is
increased until this new higher frequency is achieved.
In normal read operations, RCLK will be constantly
adjusted in an attempt to match the incoming RAW
READ frequency.
Another method of Data Separation is the CounterSeparator technique. The RCLK signal is again freerunning at a nominal rate, until a RAW READ pulse
occurs. The Separator then denotes the pOsition of the
pulse with respect to RCLK (by the counter value), and
counts down to increase or decrease the current RCLK
window. The next RCLK window will occur at a nominal
rate and will continue to run at this frequency until another RAW READ pulse adjusts RCLK, but only the
present window is adjusted.
Both PPL and Counter/Separator are acceptable
methods of Data Separation. The PPL has the highest
reliability because of its "tracking" capability and is recommended for 8" double density designs.
As a final note, the term "Data Separator" may be
misleading, since the physical separation of clock and
data bits are not actually performed. This term is used
throughout the industry, and can better be described
as a "Data Recovery Circuit" rather than a Data
Separator.
The VFOE signal is an output from the 179X that signifies the head has been loaded and valid data pulses
are appearing on the RAW READ line. It can be used
to enable the Data Separator and to insure clean RCLK
transitions to the 179X. Since some drives will output
random pulses when the head is disengaged, VFOE
can prevent an erratic RCLK signal during this time. If
the Data Separator requires synchronization during a
known pattern of one's or zero's, then RG (READ
GATE) can be used. The RG signal will go active when
the 179X is currently over a field of zeros or ones. RG
is not available on the 1795/1797 devices, since this
signal was replaced with the SSO (Side Select Output)
line.

Shown in Figure 11 is a 2V2 IC Counter/Separator. The
74LS193 free runs at a frequency determined by the
CRYCLK input. When a RAW READ pulse occurs, the
counter is loaded with a starting count of '5'. When the
RAW READ line returns to a Logic 1, the counter
counts down to zero and again free runs. The 74LS74
insures a 50% duty cycle to the 179X and performs a
divide-by-two of the 00 output.
Figure 12 illustrates another Counter/Separator utilizing a PROM as the count generator. Depending upon
the RAW READ phase relationship to RCLK, the PROM
is addressed and its data output is used as the counter
value. A 16MHz clock is required for 8" double density,
while an 8MHz clock can be used for single density.
Figure 13 shows a Phase-Lock-Loop data recovery
circuit. The phase detector (U2, Figure 2) compares
the phase of the SHAPED DATA pulse to the phase
of VFO CLK .;. 2. If VFO CLK .;. 2 is lagging the
SHAPED DATA pulse an output pulse on #9, U2 is
generated. The filter/amplifier converts this pulse into
a DC signal which increases the frequency of the VCO.
If, correspondingly, CLK .;. 2 is leading the SHAPED
DATA pulse, an output pulse on #5, U2 is generated.
This pulse is converted into a DC signal which decreases the frequency of the VCO. These two actions
cause the VCO to track the frequency of the incoming
READ DATA pulses. This correction process to keep
the two signals in phase is constantly occurring because
of spindle speed variation and circuit parameter
variations.
The operating speCifications for this circuit are as
follows:
Free Running Frequency
Capture Range
Lock Up Time

2MHz
± 15%
50 microsec. "1111" or
"0000" Pattern
100 Microsec "1010" Pattern

The RAW READ pulses are generated from the falling
edge of the SHAPED DATA pulses. The pulses are
also reshaped to meet the 179X requirements. VFO
CLK .;. 2 OR 4 is divided by 2 once again to obtain
VFO CLK OUT whose frequency is that required by the
179X RCLK input. RCLK must be controlled by VFOE
so VFOE is sampled on each rising edge of VFO CLK
OUT. When VFOE goes active EN RCLK goes active
in synchronization with VFO CLK OUT preventing any
glitches on the RCLK output. When VFOE goes inactive EN RCLK goes inactive in synchronization with
VFO CLK OUT, again preventing any glitches on the
RCLK output.
Figure 14 illustrates a PPL data recovery circuit using
the Western Digital 1691 Floppy Support device. Both
data recovery and Write Precomp Logic is contained
within the 1691, allowing low chip count and PLL reliability. The 74S124 supplies the free'running VCO
output. The PUMP UP and PUMP DOWN signals from
the 1691 are used to control the 74S124's frequency.

358

COMMAND USAGE
Whenever a command is successfully or unsuccessfully completed, the busy bit of the status register is
reset and the INTRa line is forced high. Command termination may be detected either way. The INTRa can
be tied to the host processor's interrupt with an appropriate service routine to terminate commands. The
busy bit may be monitored with a user program and
will achieve the same results through software. Performing both an INTRa and a busy bit check is not
recommended because a read of the status register to
determine the condition of the busy bit will reset the
INTRa line. This can cause an INTRa from not
occurring.

FORCED INTERRUPT COMMAND
The Forced Interrupt command is generally used to
terminate a multiple sector command or to insure Type
I status in the status register. The lower four bits of the
command determine the conditional interrupt as follows:
10
1,
1,
1,

Regardless of the conditional interrupt set, any command that is currently being executed when the Forced
Interrupt command is loaded will immediately be terminated and the busy bit will be reset indicating an idle
condition.
Then, when the condition for interrupt is met, the INTRQ
line will go high signifying that the condition specified
has occurred.
The conditional interrupt is enabled when the corresponding bit positions of the command (I, -10) are set
to a 1. If I, -10 are all set to zero, no interrupt will occur,
but any command presently under execution will be
immediately terminated upon receipt of the Force Interrupt command (HEX DO).
As usual, to clear the interrupt a read of the status register or a write to the command register is required.
The exception is when using the immediate interrupt
condition (I, = 1). If this command is loaded into the
command register, an interrupt will be immediately
generated and the current command terminated.
Reading the status or writing to the command register
will not automatically clear the interrupt; another forced
interrupt command with 13 -10 = 0 must be loaded into
the command register in order to reset the INTRQ from
this condition.
More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (I, =
1) and the Every Index Pulse (I, = 1) are both set, the
resultant command would be HEX "DA". The "OR"
function is performed so that either a READY TO NOTREADY or the next Index Pulse will cause an interrupt
condition.

RESTORE COMMAND
On some disk drives, it is possible to position the R/W
head outward past Track 00 and prevent the TROO
line from going low unless a STEP IN is first performed.
If this condition exists in the drive used, the RESTORE
command will never detect a TROO. Issuing several
STEP IN pulses before a RESTORE command will
remedy this situation. The RESTORE and all other
Type I commands will execute even though the READY
bit indicates the drive is not ready (NOT READY = 1).
READ TRACK COMMAND
The READ TRACK command can be used to manually
inspect data on a hard copy printout. Gaps, address
marks and all data are broug ht into the data register
during this command. The READ TRACK command
may be used to inspect diskettes for valid formatting
and data fields as well as address marks. Since the
179X does not synchronize clock and data until the Index Address Mark is detected, data previous to this 10
mark will not be valid. READ GATE (RG) is not actuated during this command.
READ ADDRESS COMMAND
In systems that use either multiple drives or sides, the
read address command can be used to tell the host
processor which drive or side is selected. The current
position of the R/W head is also denoted in the six
bytes of data that are sent to the computer.
'TRACK SIDE

SECTOR ,

NOT-READY TO READY TRANSITION
READY TO NOT-READY TRANSITION
EVERY INDEX PULSE
IMMEDIATE INTERRUPT

LE~~;H IC~C' C~C I

The READ ADDRESS command as well as all other
Type 11 and Type 111 commands will riot execute if the
READY line is inactive (READY = 0). Instead, an interrupt will be generated and the NOT READY status
bit will be set to a 1.

DATA RECOVERY
Occasionally, the RlW head of the disk drive may get
"off track", and dust or dirt may get trapped on the
media. Both of these conditions will cause a RECORD
NOT FOUND and/or a CRC error to occur. This "soft
error" can usually be recovered by the following
procedure:
1. Issue the command again
2. Unload and load the head and repeat step
3. Issue a restore, seek the track, and repeat step 1
If RNF or CRC errors are still occurring after trying
these methods, a "hard error" may exist. This is usually caused by improper disk handling, exposure to
high magnetic fields, etc. and generally results in destroying portions or tracks of the diskette.

359

FIGURE 1
DEVICE

DEVICE CHARACTERISTICS
SNGL DENSITY DBLE DENSITY

X
X
X
X
X

1791
1792
1793
1794
1795
1797

INVERTED BUS

TRUE BUS

X
X

DOUBLE-SIDED

X
X

FIGURE 2 STORAGE CAPACITIES
UNFORMATTED
CAPACITY (NOMINAL)
SIZE

DENSITY

SIDES

PER TRACK

PER DISK

51/4"

SINGLE
DOUBLE
SINGLE
DOUBLE
SINGLE
DOUBLE
SINGLE
DOUBLE

1
1
2
2
1
1
2
2

3125
6250
3125
6250
5208
10,416
5208
10,416

109,375'
218,750
218,750
437,500
401,016
802,032
802,032
1,604,064

5V4"
51/4"
5'/4"
8"
8"
8"
8"

'Based on 35 Tracks/Side
"Based on 18 Sectors/Track (128 byte/sec)
'''Based on 18 Sectors/Track (256 bytes/sec)

360

BYTE
TRANSFER
TIME

64",s
32",s
64",s
32",5
32",5
16",5
32",s
16",s

FORMATTED
CAPACITY
PER TRACK

PER DISK

2304"
4608'"
2304
4608
3328
6656
3328
6656

80,640
161,280
161,280
322,560
256,256
512,512
512,512
1,025,024

FIGURE 3 NOMINAL VS. WORSE CASE SERVICE TIME

SIZE

DENSITY

NOMINAL TRANSFER
TIME

5V4"
5%"
8"
8"

SINGLE
DOUBLE
SINGLE
DOUBLE

641"5
321"5
321"5
161"5

WORST-CASE 179X SERVICE TIME
READ

WRITE

55.01"5
27.51"5
27.51"5
13.51"5

47.01"5
23.51"5
23.51"5
11.51"5

FIGURE 4A. FM RECORDING

BIT

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

81T 7

HEX
02

RULE
1) WRITE DATA BITS AT CENTER
OF BIT CELL IF A "1
2) WRITE CLOCK BITS AT LEADING
EDGE OF THE BIT CELL

FIGURE 4B. MFM RECORDING

BITO

HEX
02

BIT 1

BIT 2

BIT 4

BIT 3

BIT 5

BIT 6

BIT 7

________~R~______~~~____~~~______

RULE
1) WAITE DATA BITS AT CENTER
OF BIT CELL IF A "1
2) WRITE CLOCK BITS AT LEADING
EDGE OF BIT CELL IF
A) NO DATA BIT HAS BEEN WRITTEN LAST

-ANDa) NO DATA BIT WilL BE WRITTEN NEXT

361

FIGURE 5 WFNFOE DEMULTIPLEXING CIRCUITRY
+5
+5
10K

74LSOl
f--''''-~-lI'' (WG TO DRIVE)

•

(WF FROM DRIVE)

179X

VFOE
179X

30
74LS04

) 0 - - -. .

VFOE

74LS02

PIN 33 USED AS A VFOE SIGNAL ONLY

.. PIN 33 USED AS VFOE AND WF SIGNALS

WF (FROM DRIVE)

179X
30

•

f-------*---tII..

WG (TO DRIVE)

PIN 33 USED AS A WF SIGNAL ONLY

10K

7438
74lS175

C-EAALY

woro

WDf--'------~9~C~LK~3~D 2

DRIVE

5 20

C-LATE

ro~~~=-~
I~====~
4 10
15
C-NOMINAL

4Qf--'-------r+~_i

EARLY f--'-+-~:-"""
LATE

13 4DCl~Q 10

f---*----I.~./
74LS02

FD179X

W02143
11

)l'f
,(f2

.ro
5K

..d'4

+12>-~~~~--~-'~7L~~w~J
PRECOMP.
ADJUST

FIGURE 6 179X WRITE PRE-COMP

362

__I

------------------------~

EARLY
OR LATE

---------------------~

EARLY
OR LATE

250 NS MIN.

125 NS MIN. VALID
FOR DURATION OF
PULSE

DOUBLE TIMES FOR 5~ (MINI-FLOPPY)

DOUBLE TIMES FOR 5" (MINI-FLOPPY)

450 NS MIN.

VALID BEFORE LEADING EDGE OF

WRITE PRE-COMP TIMING FOR MFM

WRITE PRE-COMP TIMING FOR FM

FIGURE 7 WRITE PRE·COMP TIMING

BIT CELL 0

BIT CELL 4

BIT CELL 1

BIT CEllS

BIT ~Ell6

BIT CELL 8

BIT tEll 7

~
W[t5

EARLY

LATE

C-EARLY

C-LATE

n
II

jll

P3
I'
Wo

FIGURE 8 PRECOMP TIMING FOR CIRCUIT IN FIGURE 6

363

n
n

BIT CELL 9

eLK
@lMHz

WD
(DDEN'= 0)

~l00ns

"" 1DOns

eLK
@2MHz

250ns

125ns

•

WD
(DDEN

~50ns

;.30os

FIGURE 9 WD/CLK RELATIONSHIP FOR WRITE PRECOMP USE

, m>
,
,

,,
9

Q.~------------------------~D

IO
Q.

WRITE

DATE
(TO DRIVE)

Wij
(FROM 1791)

SHFTiCI'l'

WE
(FROM 1791)

T043 (EN PRECOMP)

EARLY
(FROM 1791)

FIGURE 10 DIGITAL WRITE PRECOMP CIRCUIT
(PROViDeD COURTESY OF MPI, OKLAHOMA CITY. 01( 73112

364

+5
R, C = 150 NS

74123

RAW READ
FROM DRIVE

~__~______________________________
2n7

RAW READ

1791/1793

N.U
74LS74

4 CD

'_4_

74LS193

CRYCLK

TYPE

CRYCLK

8" FM

8 MHz

5" MFM

8 MHz

5" FM

4 MHz

FIGURE 11 COUNTER/SEPARATOR

365

RClK

745288 PROGRAMMING TABLE
ADDRESS
()()

0'
OA

OF
OF

~
74lS04

RETARD BY 2 COUNTS

RAW READ

ADVANCE BY 2 COUNTS

READ DATA

FROM
DRIVE

ADVANCE BY 1 COUNT

12
13

a'J;

74lS/4

a'r'--~

FREE RUN

,S
179X-Ol

~~~----

07
08

0'
OA

r----.~-~-

lB
lC

DC
OD

R"ClK

;; lAo "'~

16
17

~
1A

NONE
RETARD BY 1 COUNT

ACTION TAKEN

OC
OE

DATA

FIGURE 12 179X DATA SEPARATOR
(PROVIDED COURTESY OF ANDROMEDA SYSTEMS. PANORAMA CITY, CA 91402)

UlWOI--OZ

CD
CD

..,

-12 10

VV\I-----]

R16
.5

10KO

R11
140n

R25
1600
R1B
2701}

1!2W
12o------'1.o,.'__-~---_,

R21
10Kn
1%

1/2W

VR2

S.6V
5%

R12
60SH
1%

TPl

R19
2.2KO

31 26802 16
CLR
i;, Ul

CR2
IN914

vW-----1

74811215

CLK
K
15 R

11 J
13 elK

SHAPED DATA

741C

R23
1.2KU

CRl

L...1,MHZ

8
R33
3.48Kn
1%

R32
2.2KO

12 K
14 R

VFO eLK
STEERING 2

VCO

IN914

C72
.1j.lF

ea3
047J.lF

9 150 NSEC

+5~

TP2

c.>

C82
1300",F

R35

R34

1.10Kn

.....

10K1I
1%

'"
R30
5.1KO

("ii)

-12

C89

82Jl.F

VFOCLK :20R4

RAWAEAD

(E> 1

EN PRE-COMP

(G) 1

VFOE

;S74S112

J
1..

2~LK

74LSQ4

lKO

<~)

i5iiEN

[£)

TG<3

FIGURE 13 PLL DATA RECOVERY CIRCUIT
(PROVIDED COURTESY OF MPI, OKLAHOMA CITY, OK 73112)

"";..

>""',

ZO--'iomcn

---+

.... 200 NS :': 25

-----u-

."I'IE hl\l()10MSDfLAY
1 AND eLK
1 "" • ., THERE 'o,A 20MS DELA~

For IBM 3740 compatibility, the b flag should equal1.
The numbers of bytes in the data field (sector) is then
128 x 2n where n = 0, 1, 2, 3.

TYPE I COMMAND FLOW

379

lOAM

10 Address Mark"" DATA

Data AM

Data Address Mark -

IFEJ,6 elK

DATA

(Cl)'6

'(F8. F9 FA, or FB), elK

(C7)16

For b
Sector Length
Field (Hexl

Number of Bytes
In Sector (DeCimal)

When the b flag equals zero, the sector length field
(n) multiplied by 16 determines the number of bytes
In the sector or data field as shown below"
For b

Sector Length
Field (Hex)

Number of Bytes
In Sector (DeCimal)

Each of the Type II commands also contain a (m) flag
which determines If the multiple records (sectors)
are to be read or wntten, depending upon the command" If m =0 a single sector IS read or written and an
interrupt IS generated at the completion of the command" If m=l, multiple records are read or written
with the sector register internally updated so that an
address venf,cation can occur on the next record
The FDl771 will continue to read or write multiple
records and update the sector register until the sector register exceeds the number of sectors on the
track or until the Force Interrupt command is loaded
into the command register, which terminated the
command and generates an interrupL

(HUH h NI) '0 M5IJEl

'ANllll~

'\\H/IHfRfl~"']OMSDEI"'V

READ COMMAND
Upon receipt of the Read command, the head is
loaded, the BUSY status bit set, and when an 10 field
IS encountered that has the correct track number,
correct sector number, and correct eRe, the data
field is presented to the computer" The Data Address
Mark of the data field must be found within 28 bytes
of the correct field; if noL the Record Not Found status bit is set and the operation is terminilted" When

TYPE II COMMAND FLOW
the first character or byte of the data field has been
shifted through the OSR, it is transferred to the DR,
and ORO is generated" When the next byte is accumulated in the OSR, it is transferred to the DR and
another ORO is generated" If the computer has not
read the previous contents of the DR before a new
character is transferred that character is lost and the

360

IO"1,j
II£EN

DETE;HD

DOES

1-------0::.---< A~~AE~~ ....OCfK,D
FIno

DOES

1-------=--< A~~Al;~~~~D

TYPE \I COMMAND FLOW

Lost Data status bit is set. This sequence continues
until the complete data field has been input to the
computer. If there is a CRC error at the end of the
data field, the CRC error status bit is set, and the
command is terminated (even if it is a mulltiple
record command).

WRITE

COIVI~JlAND

Upon receipt of the Write command, the head is
loaded (HLO a(:tive) and the BUSY status bit is set.
When an I D field is encountered that has the correct
track number, correct sector number, and correct
CRC, a ORO is generated. The FOl771 counts off 11
bytes from the CRC field and the Write Gate (WG)
output is made active if the ORO is serviced (i.e., the
DR has been loaded by the computer). If DRO has
not been serviced, the command is terminated and
the Lost Data status bit is set. If the DRO has been serviced, the WG is made active and six bytes of zeros
are then written on the disk. At this time the Data
Address Mark is then written on the disk as determined by the a, ao field of the command as shown
on next page.

At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recorded in the Status Register (Bits 5 and 6) as shown
below.

The FOl771 then writes the data field and generates
DROs to the computer. If the ORO is not serviced in

381

TYPE III COMMANDS
READ Address

time for continuous writing the Lost Data status bIt IS
set and a byte of zeros is written on the disk. The
command is not terminated. After the last data byte
has been written on the disk, the two-byte eRe is
computed internally and written on the disk followed
by one byte gap of logic ones. The WG output is then
deactivated.

Upon receipt of the Read Address command, the
head is loaded and the BUSY Status bit is set. The
next encountered ID field is then read in from the
disk, and the six data bytes of the I D field are
assembled and transferred to the DR, and a DRQ is
generated for each byte. The six bytes of the ID field
are shown below.

Although the eRe characters are transferred to the
computer, the FDI771 checks for validity and the
eRe error status bit is set if there is a eRe error.
The Sector Address of the I D field is written into the
Sector Register. At the end of the operation an interrupt is generated and the BUSY Status is reset.

READ TRACK

>':~_-1I"'lRQ

RESET BUSY

Upon receipt of the Read Track command, the head
is loaded and the BUSY status bit is set. Reading
starts with the leading edge of the first encountered
index mark and continues until the next index pulse.
As each byte is assembled it is transferred to the
Data Register and the Data Request is generated for
each byte. No eRe checking is performed. Gaps are
included in the input data stream. If bit O(S) of the
command is a 0, the accumulation of bytes is synchronized to each Address Mark encountered. Upon
completion of the command, the interrupt is
activated.

WRITE TRACK

HAVE

t -_ _ ~=< BE:~l::I~;iN

TYPE II COMMAND FLOW

Upon receipt of the Write Track command, the head
is loaded and the BUSY status bit is set. Writing
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse,
at which time the interrupt is activated. The Data
Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the
DR has not been loaded by the time the index pulse is
encountered the operation is terminated making the
device Not Busy, the Lost Data status bit is set. and
the Interrupt is activated. If a byte is not present in
the DR when needed, a byte of zeros is substituted.
Address Marks and eRe characters are written on
the disk by detecting certain data byte patterns in the
outgoing data stream as shown in the table below.
The eRe generator is initialized when any data byte
from F8 to FE is about to be transferred from the DR
to the DSR.

382

Ou[<"
ll<"f~

011('>

O<.,IlF8 ~?B II:

"'j

' '1

WP,TE
CLK

fe
('J/

WI'1II£,fO FE·
~8

- Fe Cu<

Dr:. BEfN
,0.0.0(0

TYPE III COMMAND WRITE TRACK

The Write Track Command will not execute if the
DINT input is grounded; instead, the Write Protect
status bit is set and the interrupt is activated. Note
that one F7 pattern generates two CRC characters.
TYPE IV COMMAND
Force Interrupt

This command can be loaded into the command register at any time. If there is a current command under
execution (BUSY status bit set), the command will
be terminated and an interrupt will be generated
when the condition specified in the 10 through 13
field is detected. The interrupt conditions are shown
below:

TYPE III COMMAND WRITE TRACK

CONTROL BYTES FOR INITIALIZATION

10= Not-Ready-To-Ready Transition
I, = Ready-To-Not-Ready TranSition
12 = Every Index Pulse
13 = I mmediate Interrupt (Requires reset,
see Note)
NOTE: If 10 - 13 -: 0, there is no interrupt generated but the current
command is terminated and busy is reset. This is the only
command that will clear the immediate interrupt.

383

STATUS DESCRIPTION
Upon "ecelpt of any command, except the Force
Interrupt command, the Busy Status bit is set and
the rest of the status bits are updated or cleared for
the new command. If the Force Interrupt Command
IS received when there IS a current command under
execution, the Busy status bit IS reset, and the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there IS not a current
command under execution, the Busy Status bit is

Table 6

reset and the rest of the status bits are updated or
cleared. In this case, Status reflects the Type I
commands
The format of the Status Register is shown below.

'1
$7
Status varies according to the type of command
executed as shown in Table 6.

STATUS REGISTER SUMMARY

STATUS FOR TYPE I COMMANDS

384

STATUS BITS FOR TYPE II AND III COMMANDS
MEANING
This bit when set indicates the drive is not ready. When reset, it
indicates that the drive is (eady. This bH is an inverledcopyof the
READY input and "ored"..with MR. The TYPE II and III Commands
wHlnotexecute unless the drive is ready.
TYPEIWRITE PROTECT

On Read. Record: It indicates the MSB of record-type code from
data field address marlc On Read Track: Not Used, On any Write
Track It indicates a Write Protect. This bil is reset when updated.
On Read Record: It indicates the LSB of record-type code from
data. field address mark. On Read Track: NolUsed: On any Write
Track: It indicates a Write Fault. This bit is reset when updated.
When set, it indicates that the deSired track and sector were not
found. This bit is reset when updated.
If S4 is set, an error is found in one or more 10 fields; otherwise it
indicates error in data field. This bit is reset when updated.
When set. it indicates .the computer did not resp()nd to ORO in
one byte time, This bit is reset to zero when updated:
This bit is a.copy of the DAO output. When set, itindicat~lheDR
isfuU on a Readoperation or the DRisempty on a Write?peralio!):
This bit is reset to zero When,updatec:l.
. ....
When set, command is ~nder execution When reset, no co~
. is under execution.
.

FORMATTING THE DISK (Refer to section on Type
III Commands for flow diagrams.)
Formatting the disk is a relatively simple task when
operaling programmed I/O or when operating under
DMA control With a large amount of memory. When
operating under DMA with limited amount of
memory. formatting IS a more diffitult task. This is
because gaps as well as data must be provided at the
computer interface.
Formatting the disk is accomplished by positioning
the R/W head over the deSired track number and
issuing the Write Track command. Upon receipt of
the Write Track command, the FDl771 raises the
Data Request signal. At this point in time, the user
loads the Data Register with desired data to be written on the disk. For every byte of information to be
written on the disk, a Data Request is generated. This
sequence continues from one index mark to the next
index mark. Normally, whatever data pattern
appears in the Data Register is written on the disk
with a clock mark of (FF)16. However, if the FDl771
detects a data pattern on F'1 through FE in the Data

385

Register, this is interpreted as data address marks
with missing clocks or CRC generation. For
instance, an FE pattern will be interpreted as an 10
address mark (DATA-FE, ClK-e7) and theCRC will
be Initialized. An F7 pattern will generate two CRC
characters. As a consequence, the patterns F7
through FE must not appear in the gaps, data fields.
or ID fields. Also, CRCs must be generated by an F7
pattern.
Disks may be formatted in IBM 3740 formats with sector lengths of 128,256,512, or 1024 bytes, or may be
formatted in non-IBM format with sector lengths of 16
to 4096 bytes in 16-byte increments. IBM 3740 at the
present time only defines two formats. One format
with 128 bytes/sector and the other with 256 bytes/sector. The next section deals with the IBM 3740 format with 128 bytes/sector followed by a section of
non-IBM formats.
IBM 3740 Formats -

128 Bytes/Sector

The IBM format with 128 bytes/sector is depicted in
the Track Format figure on the following page. In
order to create this format, the user must issue the

Write Track command, and load the data register with
the following values. For every byte to be written,
there is one data request.
Number
Hex Value of
of Bytes
Byte Written
40
6
1
26
6
1
1
1

1
11
6
1
128
1
27
247"

00 or FF
00
FC (Index Mark)
00 or FF
00
FE (10 Address Mark)
Track Number (0 through 4C)
00
Sector Number (1 through lA)
00
F7 (two CRCs written)
00 or FF
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (two CRCs written)
00 or FF
00 or FF

'Write bracketed field 26 times.
"Continue writing until FDI771 interrupts out.
Approximately 247 bytes.

Non-IBM Formats
Non-IBM formats are very similar to the IBM formats
except a different algorithm is used to ascertain the
sector length from the sector length byte in the 10
field. This permits a wide range of sector lengths
from 16 to 4096 bytes. Refer to Section V, Type II
commands with b flag equal to zero. Note that F7
through FE must not appear in the sector length byte
of the 10 field.
In formatting the FD1771 , only two requirements
regarding GAP sizes must be met. GAP 2 (i.e., the
gap between the 10 field and data field) must be 17
bytes of which the last 6 bytes must be zero and that
every address mark be preceded by at least one byte
of zeros. However, it is recommended that every
GAP be at least 17 bytes long with 6 bytes of zeros.
The FDI771 does not require the index address mark
(i.e., DATA = FC, ClK = 07) and need not be present.

References:
1) IBM Diskette OEM Information GA21-9190-1.
2) SA900 IBM Compatibility Reference Manual Shugart Associates.

00 OR FF

J
TRACK FORMAT

386

L-",,,,,--J

' - ~~'::E~~~ST~:iAO~~:gA UPDATE

OPERATING CHARACTERISTICS (DC)

ELECTRICAL CHARACTERISTICS
Maxium Ralings
VOO with respect to VBB (Ground)
Max Voltage to any input with
respect to VBB
Operating Temperature
Storage Temperature

+20 to -0.3V
+20 to -0.3V

TA =
VBB
I DO
I BB

0' e to 70' C

Characteristic

Min.

Input Leakage
Output Leakage
Input High Voltage

o'e to 70'e, VOO = +12.0V ± .6V,
= -5.0 ± .5V, VSS = OV, Vee = +5V ± .25V
= 10 ma Nominal, lee = 30 ma Nominal,
= G.4 J.l a Nominal

Typ.

Max.

Units

Conditions

/-I A

VIN" VOO

/-I A

VOUT =VOO

2.6

Input Low Voltage (All Inputs)

0.8

Output High Voltage

0.45

Output Low Voltage

TIMING CHARACTERISTICS

V
V
V
V

NOTE: Timings are given for 2 MHz Clock. For those
timings noted, values will double when chip is operated at 1 MHz. Use 1 MHz when using mini-floppy.

TA = G'C to 70'C, VDO = +12V ± .6V,
V BB = -5V ± .25V, VSS = OV, Vee = +5V ± .25V

Read Operations

Write Operations

Edernal Data Separation (XTDS = 0)

387

.. on

,~i~rl~i~'f~~~~:~~~~~~~~:~:i~T~~~1~~~;~~~.~f;·:~~I~~J~~R~: ~~;:7;o~~1~
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R .....

Bf PER ...... f .. " . ',fOlOW"OFSIRED

J ' ..... aWOf'ISTC.SE1 ... S£C

""Hf" nK ''''''1

. ""'! 00U8L(<; """("ClK

READ ENABLE TIMING

I ..... {

WRITE ENABLE TIMING

.. 01£
, .lEIOYE "",(S .. R£ OOU8lED "'HE .. CLK ,,,, .. {
; CO"'.C' WOC fOR £
CtOCK 0" T. S(~.R" TOR

"('1".,

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J fOClI' .."'O.OO.' ......... 8£R!VERSED fO"TI DECIDES W.... T IS ClOCI<. ."'OW ..... , '5 0 ......

READ TIMING (XTDS . 0)

Internal Data Separation (XTDS = 1)
Symbol

cha~ra~c~te~r~iS~ti~C~~~~~M~in~.~~~~M~a~x~.~u_n~it~s~~~_C_o~n~d~it_io_n_s__~~

Write Data Timing

388

~---il""

Jr::=;;-----11
'."",,
.h
I-' "~' "'I- -i "'i- 1-' ".~' "'l- -I' "'i1 , - - - ._

-JLSlr1~
READ TIMING (XTDS

= 1)

MISCELLANEOUS TIMING

~r------------II~

r-'

w'""4

, 'wW

--j

I--

-1 'l ~ ,wwl-

1= '","-1,

,w---r--' 'w

__(wI--

--j

-1 I--

~ I~/ Ll"~T

DATA 90T

TOBfWAOIIEN

WRITE DATA TIMING

389

1--' we"

f:":: I:: [:a:: ::[[[':::1
200
2.025
MAX

MAX I

L~J
r- ~ 090~ ~ -1~ ~ I~ ~ ~ ~ ~ ~ ~ 03~~I --1-~ I I! I : 'i
015
f
-11--

MIN

110

OS!>

Q'_4
021

125
MIN

610

MAX ---,

fr-~l

I-~~I

FD1771A CERAMIC PACKAGE

FD1771B PLASTIC PACKAGE

ThiS IS a prelimInary specIfication With tentative device parameters and may be subject to change after final product characterization IS
completed
Information furnished by Western DigItal Corporation is believed to be accurate and reliable. However, no responsIbility IS assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from rts use No
,license is granted by implication or otherwise under any patent or patent rights of Western Digital Corpora lion. Western Digital Corporahan reserves the right to change said CirCUItry at any time without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

390

WESTERN DIGITAL
c

1771-01 Application Notes
INTRODUCTION
The FDI771-01 Floppy Disk Formatter/Controller is
a MOS/LSI device designed to ease the task of interfacing the 8" or 5'1, (mini-floppy) disk drive to a host
processor. It is ideally suited for a wide range of
microprocessors, providing an 8-bit bi-directional
interface to the CPU for all control and data
transfers. Requiring standard + 12, :±5V power supplies, the 1771 is available in ceramic or plastic40 pin
dual-in-line packages.
The 1771 has been designed to be compatible with the
IBM 3740 standard. This single-density Frequency
Modulated (FM) recording technique, records a
clock bit between a data bit serially on each track.
Figure 1 illustrates how a HEX' "D2" is recorded.
Note that when the data bit to be written is zero, no
pulse or flux transition is recorded. For the 8" drive,
there are 77 tracks, with 26 sectors on each track.
Each sector contains 128 bytes of data. Although
there is no "standard" format for the mini-floppy,
most manufacturers utilize either 35 or40 tracks J;ler
side, wtih 16 sectors of 128 bytes each per track.
Both the 8" and 5'1," formats must be soft-sectored,
i.e., there are no physical holes to denote sector
locations. The hard-sectored disk has been losing
popularity, mainly due to the fact that tile sector
lengths cannot be increased.
Being soft-sector compatible, the 1771 must know
where each sector begins on the track. This is performed by using Address Marks. These bytes are
recorded on the disk with certain clock pulses missing, and are unique from all other data and gap bytes
recorded on the track. Six distinct Address Marks
can be used:

Description

Data

Clock
Pattern

Index Address Mark
ID Address Mark
Data Address Mark
User defined
User Defined
Deleted Address Mark

FC
FE
FB
FA
F9
F8

D7
C7
C7
C7
C7
C7

The two "User Defined" Address Marks are unique
to the 1771, and do not appear in the IBM 3740
standard. These Address Marks can be used to

define the type of data i.e., "object" or "text" data, ~
alternate sector data, or any other purpose the user CI)
chooses.

PROCESSOR INTERFACE
The 1771 contains five internal registers that can be
accessed via the 8-bit DAL lines by the CPU. These
registers are used to control the movement of the
head, read and write sectors, and perform all other
functions at the drive. Regardless of the operation
performed, it must be initiated through one or more
of these registers. They are selected by a proper
binary code on the AO, AI lines in conjunction with
the RE and WE lines when the device is selected.
The registers and their addresses are:
CS

RE = 0

WE=O

0
0
0
0
1

0
0
1
1
X

0
1
0
1
X

STATUS REG
TRACK REG
SECTOR REG
DATA REG
Deselected

COMMAND REG
TRACK REG
SECTOR REG
DATA REG
Deselected

Command Register. This is a write-only register
used to send all commands to the 1771.
Status Register. This is a read-only register that
must be read at the completion of every command to
determine whether execution was successful. It
may also be used to monitor command execution,
and to sense when data is required by the drive for
read or write operations.
Track Register. This R/W register holds the current
position of the R/W head.
Sector Register. This R/W register holds the desired
sector number for read and write commands.
Data Register: This R/W register contains the data
to be read or written to a particular sector.

INTERRUPTS
There are two INTERRUPT lines for CPU use. These
are the DRO (Data Request) and INTRa (Interrupt
Request). These are active high, open drain outputs
and require a pull-up resistor of 10K or greater to
+5V. Both of these signals also appear in the status
register as the Busy (INTRa) and the data request
(DRO) bits. The user has the option of utilizing these
hardware lines for system interrupts, or through

391

software by polling the status register. The choice is
dependent upon the particular microprocessor and
support hardware of the system.

INTRa: This line is used to signify the completion of
any command. It is reset low when a new command
is loaded into the command register, or when the
status register is read.
ORa: This line is active high whenever the data register requires servicing. During a read command, it
signifies that the data register contains a byte of
data from the disk and may be read by the CPU. During a write command, it signifies that the data register is empty and may be loaded with the next byte to
be written on the disk. The DRO line is reset whenever the data register is read or written to. I t is also
reset when a new command is loaded into the command register, providing the new command is not a
Forced Interrupt, and the 1771 is not busy (BusyBit~O).

WRITE SECTOR
With the use of the WRITE SECTOR command, the
CPU can access any desired sector(s) in a track.
Prior to loading this command, the R/W head of the
drive must be positioned over the specific track.
This can be first accomplished with the use of any of
the Type I commands. Once positioned, the CPU
must load the desired sector number into the sector
register, then issue the command. The .head will
load. and the 1771 will begin searching for the correct ID field. If the correct sector and track is not
found within 2 revolutions of the disk, the RECORDNOT -FOUND bit will be set in the status register,
and the command will be terminated. Once found,
the 1771 will issue a ORO in request of the first data
byte to be written. Once the data register is loaded,
the 1771 will issue a DRO for each byte to be
recorded, until the entire sector is written. For the 8"
drive, the user must load the data register 24
microseconds after a ORO is generated. Failure to
meet this time will cause the lost data bit to be set,
and a byte of zeros substituted and written on the
disk.

READ SECTOR
The READ SECTOR command functions in much
the same way as the WRITE SECTOR command.
The sector register must again be loaded with the
desired sector number, before the read command
can be loaded. After the 10 field has been found, the
1771 will begin generating ORa's, with the data register being loaded with each byte of the sector field.
For the 8" drive, the user must read the data register
at least 26 microseconds after the ORO is
generated. Failure to meet this time will cause the
lost data bit to be set in the status register, while the
next assembled byte will overwrite the contents of
the data register.
Both the Read and Write sector commands also

contain an "m" flag for accessing multiple sectors.
The sector register is incremented internally after
each sector is read or written to. Eventually the sector register will exceed the physical number of sectors on the track. The user can either issue the
Forced Interrupt command after the last sector, or
wait for the 1771 to interrupt out. In the latter case,
the RECORD-NOT -FOUND status bit will be set.

FLOPPY DISK INTERFACE
For the most part, the actual Floppy Disk Interface
will consist mainly of Buffer/Drivers. Most drives
manufactured today require an open collector TTL
interface, with appropriate resistor terminal networks. Figure 2 shows the interface of the 1771 to a
Shugart SA400 Drive. Aside from the data seperator,
the interface consists mainly of7438's and 7414 TTL
gates. A 9602 one-shot is used for the desired head
load delay. In this illustration, the 6800 microprocessor is used via a 6820 Peripheral Interface Adapter to control all functions of the 1771. Similarly,
other parallel port devices (such as the 8255 for 8080
systems) can be used for the interface, or the 1771
may simply be tied directly to the systems data bus
and control lines, providing TTL loading factors are
observed.

DATA SEPERATION
The internal DATA SEPERATOR of the 1771 can be
used by tying the XTDS line high, and supplying the
combined clock and data pulses on the FD data line.
In order to maintain an error rate better than 1 in 10',
and external data seperator is recommended.
Since the 1771 system clock is at 2 MHz, this allows
for a 500 ns resolution. The internal data window will
move 500 ns with respect to the incoming data bit.
On the inner tracks of the drive, the bit shift is more
severe and may occasionally cause a data or clock
bit to fall outside of this data window. Since the 1771
will perform up to 5 retries, this error rate may be
acceptable for some applications.
When the XTDS line is forced low, the 1771 will
accept seperated clock and data on the FDCLOCK
and FDDATA lines. Figure 3 illustrates the timing of
these signals. The actual FDCLOCK and FDDATA
lines may be reversed; the 1771 will determine which
line is clock and which is data when an Address
Mark is detected. This feature greatly simplifies the
design of the data seperator.
Figure 4 illustrates the Phase-Lock Loop method for
data seperation. The circuit operates at8 MHz, or32
times the frequency of a received bit cell. The
MC4024 VCO is used to supply the nominal clock
frequency. The first 74LS161 counter provides a
divide by 16 frequency and a carry to one side of the
MC4044 phase detector. The other input of the
MC4044 is tied to another 74LS161 counter which is
affected by the incoming data stream. The output of

392

the phase detector is a signal proportional to the differences of the incoming pulses. This is then fed
through a low pass filter, and to the input of the
MC4024 to adjust the output frequency. Figures 5
thru B illustrate other types of data seperators.

r '·'l
I

BITO

BIT 1

BIT 2

These employ the "Counter Seperator" techniques
and are quite different from the Phase-Lock~Loop
method. With the addition of "One-Shot" delay element or an input clock, most of\he complexityofthe
PPL circuit can be eliminated.

BIT ..

BIT 3

BIT 5

BIT6

BIT 7

HEX

FIGURE 1 FM RECORDING.

,--- ------ -------;;;.- ;--- - - - - - - . - - l
I

I
I

I
I
I

I
I
I
1
1

~--------------------------~~~~~~~

~.-------------~,~.

FIGURE 2 1771 TO SHUGART SA400 DRIVE

393

"Xm",o
EXTERNAL DATA
SEPARATION

-j
FDCLOCK

FODATA

T PWX

MISSING
CLOCK

TpWX

.Jn,-_______.J

~'-_ _ _ _ _ _ _
f---- TCX

---------'-----+-----'

~~N~SM~~X

~~~~VE TIMES ARE OOUBLED WHEN CLK

= 1 MHZ

TCX ' 3500·5000 NS

FIGURE 3 EXTERNAL DATA SEPERATOR TIMING.

f-,.s-j

-RJUL
--j2.Sf•

o5V

SOFTS

NOMINAL

RAW
DATA

SOFTS

MC4024

820U

F 6

FIGURE.. CIRCUIT PROVIDED COURTESY OF MOTOROLA AND ICOM CORPS.

394

UNSEPERA TED DATA

JLJLJL

FIGURE 5 CIRCUIT PROVIDED COURTESY OF PROCESSOR APPLICATIONS LTD.

a
UNSEPAAATED
DATA FROM
DRIVE

7474

74175

a
74175

DELAY

TOGGLE

lOAD PULSE

7<04
aDr'~'

__-o________________~

.5V

4MHZClK
(USE 2MHZ elK FOR MINI-DRIVES)

FIGURE 6

395

RAW

DATA

10,uSEC

t---------------t-----

SEP eLK

):>---+---,-------------+-... SEP DATA

L
J..
c

AAWOATA~
SEPOATA~
SEP eLK

H6·6

H6-9

FIGURE 7 CIRCUIT PROVIDED COURTESY OF ACUTEST CORP.

396

• READ DATA

- SEP eLK

-SEPDATA

551 (0)
552 (ci)
553 (0)

A2-6 (a, 1

______________________________

~r___lL

___________

FIGURE 8 CIRCUIT PROVIDED COURTESY OF SHUGART ASSOCIATES.

397

All dIagrams within this applications note are shown for illustrative purposes and may not necessarily reflect the total logicfor
Impllmentation.
InformatIOn furnished by Western Digital Corporation IS belIeved to be accurate and reliable. However, no responsibility is assumed by
Western DigItal Corporation for its use; nor any mfrlngements of patents or other rights of third parties which may result from Its use. No
license IS granted by implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corporation
reserves the fight to change said circuitry at anytime without notice

WESTERN DIGITAL
o

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

398

WESTERN DIGITAL
c

WD1691 FLOPPY SUPPORT LOGIC (F.S.L.)
o
GENERAL DESCRIPTION
The WD1691 F.S.L. has been designed to minimize the
external logic required to interface the 179X Family of Floppy
Disk Controllers to a drive. With the use of an external VCO,
the WD 1691 will generate the RCLK signal for the WD179X,
while providing an adjustment pulse (PUMP) to control the
VCO frequency. VFOE/WF de-multiplexing is also accomplished and Write Precompensation signals have been included to interface directly with the WD2143 Clock Generator.
The WD1691 is implemented in N-MOS silicon gate
technology and is available in a plastic or ceramic 20 pin
dual-in-line package.

FEATURES
.. Direct interface to the FD179X
• Eliminates external FDC Logic
.. Data Separation/RCLK GENERATION
.. Write Precompensation Signals
• VFOE/WF Demultiplexing
• Programmable Density
o 8" or 5.25" Drive Compatible
.. All inputs and outputs TTL Compatible
... Single +5V Supply

RCLK

YCO
PU

WDIN

• 1

LATE

EARLY

STB

VCO

WDOUT

DDEN

ROD

TG43

VFOElWF

VSS

WD1691

RCLK

RDD

fi
VFOE

!WF

fi
~
WG

EARLY

WDIN

LATE

WDOUT
STB

BLOCK DIAGRAM

399

co
en
III

~
o

2,3,4,19

NAME

SYMBOL

WRITE DATA
INPUT

WDIN

PHASE
2,3,1,4

iD2iii3Q104

FUNCTION

Ties directly to the FD179X WD pin.

4 Phase inputs to generate a desired Write Precompensation
delay. These signals tie directly to the WD2143 Clock
Generator.

STROBE

STB

Strobe output from the 1691. Strobe will latch at a high level
on the leading edge of WDIN and reset to a low level on the
leading edge of 04.

WRITE DATA
OUTPUT

WDOUT

Serial, pre-compensated Write data stream to be sent to the
disk drive's WD line.

WRITE GATE

Ties directly to the FD179X WG pin.

VFO ENABLE!
WRITE FAULT

VFOE/WF

Ties directly to the FD179X VFOE/WF pin.

TRACK 43

TG43

Ties directly to the FD179X TG43 pin, If Write Precompensalion is required on TRACKS 44-76.

Ground

READ DATA

ROD

Composite clock and data stream input from the drive.

READ CLOCK

RCLK

RCLK signal generated by the WD1691, to be tied to the
FD179X RCLK pin.

PUMP UP

Tri-state output that will be forced high when the WD1691
requires an increase in VCO frequency.

PUMP DOWN

Tri-state output that will be forced low when the WD1691 required a decrease in VCO frequency.

Double Density
Enable

DDEN

Double Density Select input. When Inactive (High), the VCO
frequency is internally divided by two.

Voltage
Controlled
Oscillator

VCO

A nominal 4.0MHz (8" drive) or 2.0MHz (5.25" drive) master
clock input.

17,18

EARLY
LATE

EARLY and LATE signals from the FD179X, used to determine Write Precompensation.

+ 5V ±

10% power supply

400

DEVICE DESCRIPTION

The WD1691 is divided into two sections:

When VFOE/\VF and WRITE GATE are low, the data
recovery circuit ignabled. When the ROD iine goes Active
Low, the PU or PO signals will become active. If the ROD
line has made its transition in the beginning of the RCLK
window, PU will go from a HI-Z state to a Logic I, requesting
an increase in VCO frequency. If the RoDline has made its
transition at the end of the RCLK window, PU will remain in
a HI-Z state while PO will go to a logic zero, requesting a
decrease in VCO frequency. When the leading edge of ROD
occurs in the center of the RCLI< window, both PU and PO
will remain tri-stated, indicating that no adjustment of the
VCO~ency is needed. The RC~al is a divide-by16 (DDEN=1) or a divide-by-8 (DDEN=O) of the VCO
frequency.

1) Data Recovery Circuit
2) Write precompensation Circuit

---.lhe Data ~rator or Recovery Circuit has four inputs:
DDEN, VCO, ROD, and VFOEIWF; and three outputs: PU,
Po and RCLK. The VFOEIWF input is used in conjunction
with the Write Gate signal to enable the Data recovery circuit.
When Write Gate is high, a write operation is taking place,
and the data recovery circuits are disabled, regardless of the
state on any other inputs.

VFOEIWF

ROD

PU+PD

X
1

X
X
1

HI-Z
HI-Z
HI-Z
Enable

a
a
a

a
a

The minimum Voh level on PU is specified at 2AV,
sourcing 200ua. During PUMP UP time, this output will "drift"
from a tri-state to.4V minimum. Sy tying PU and PO together,
a PUMP signal is created that will be forced low for a decrease in VCO frequency and forced high for an increase in
VCO frequency. To speed up rise times and stabilize the
output voltage, a resistor divider can be used to set the tristate level to approximately 1AV. This yields a worst case
swing of ± 1V; acceptable for most VCO chips with a linear
voltage-to-frequencv characteristic.

The Write Precompensation circuit has been designed
to be used with the WD2143-01 clock generator. When the
WD1691 is operated in a "single density only" mode, write
precompensg!!on as~eJLas the WD2143-01 is not needed.
In this case, $1,
~3, ~4, and STS should be tied together,
DO EN left open, and TG43 tied to ground.

iW,

In the double-density mode (DDEN=O), the siQ!l,als Early
and Late are used to select a phase input
11'4) on the
leading edge of WDIN. The STS line is latched high when
this occl!@, causing the WD2143-01 to start its pulse generation_ 4>2 is used as the write data -2!!Jse on nominal
(Early=Late=~), W is used for early, and ilJ3 is used for late.
resets the STS line in anticipation of
The leading edge of
the next write data pulse. When TG43=0 or DDEN=1, Precompensation is disabled and any transitions on the WDIN
line will appear on the WDout line. If write precompensation
is desired on all tracks, leave TG43 open (an internal pull-up
will force a Logic I) while DDEN=O.

(11 -

Soth PU and PO signals are affected by the width of the
RAW READ (ROD) p\!.!gl. The wider the RAW READ pulse,
the longer the PU or PO signal (depending upon the phase
relationship to RCLK) will remain active. If the RAW READ
pulse exceeds ~ (VCO = 4MHz, DDEN = 0) or 500ns.
(VCO = 4MHz, DDEN = 1), then both a PU and PO will occur
in the same window. This is undesirable and reduces the
accuracy of the external integrator or low-pass filter to convert the PUMP signals into a slow moving D.C. correction
Voltage.

Eventually, the PUMP signals will have corrected the
VCO input to exactly the same frequency multiple as the
RAW READ signal. The leading edge of the RAW READ
pulse will then occur in the exact center of the RCLK window,
and ideal condition for the FD179X internal recovery circuits.

The signals, DDEN, TG43, andl'iDlJhave internal pullup resistors and may be left open if a logic I is desired on
any of these lines.

401

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias
Voltage on any pin with respect
to Ground (vss) ...
Power Dissipation . . . . . . . . . . . . . .

-25° to 70°C

Storage Temp.-Ceramic-65°C to +150°C
Plastic-55°C to + 125°C

-0.2 to + 7V
. . . .. 1W

NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified
in the DC Electrical characteristics.

DC ELECTRICAL CHARACTERISTICS

T, = 0 to 70°C; Vee = 5.0V±10%; V,,=OV

SYMBOL

PARAMETER

MIN

Input Low Voltage

-0.2

V,H

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

High Level Output Voltage

2.4

Vee

Supply Voltage

4.5

Icc

Supply Current

TYP

MAX

+0.8

UNIT

TEST CONDITIONS

V
V

0.45

IOL=3.2MA

10H= -200ILa

5.0

5.5

100

All outputs open

AC ELECTRICAL CHARACTERISTCS

T, = 0° to 70'C; V" = 5V± 10%; Vss = OV

SYMBOL

PARAMETER

MIN

TYP

MAX

TEST CONDITIONS

MHz

ODEN=O

MHz

ODEN=l

100

200

VCO Input Frequency

Row

RDD Pulse Width

EARLY (LATE) to WOIN

100

Poo

PUMP UP/ON Time

Wpi

WDIN to WOOUT

INR

Internal Pull-up Resistor

ns.
ns.

UNIT

FIN

6.5

4.0

250

ns.

Kfi

OOEN=l

I.-

Vcc

veo

FIN

-+I

J-LJ-Ls

PINS

1 - - - - - - - - + - - - - - - 8 , 9, 11, 15

ROD

only

~ I

U-

I
1'--

Rpw

ReLK~
INTERNAL PULL-UP RESISTOR

~
......- - - -

402

Veo + 16--~""_

Wei
WDIN

n -n

Wpw

-..1 1 -

n
I

EARLY

LATE

iD2

iro
$4

STS

WDOUT
NOM

TG43
DDEN

"1"

"0"

WRITE DATA TIMING (MFM)

WDIN

WDOUT

Wpw

I
I
~I

L-_ _ _ _ __

- - - - ' I1

II
TG43
DDEN

"0"
"1"

NOM

LATE

EARLY

L - --

-11-

WRITE DATA TIMING (FM)

403

- j- - - - Wp

TYPICAL APPLICATIONS

Figure 1 illustrates the 1691 to FD1771-01 Iloppy disk controller. The RCLK signal is used to gate the RAW data pulses
which are inverted by the 74LS04 inverter. Since RCLK will
be high during data and low during clock a 74LSOB is used
to switch the proper clock or data pulse to the FDI771.

To adjust write precompensation, issue a command to
the FD179X so that write data pulses are present. This can
be done with a 'WRITE TRACK' command and the IP line
open, or a continuous 'WRITE SECTOR' operation. With a
scope on pin 4 of the WD1691, adjust the precomp pot for
the desired value. This will range from 100 to 300 ns typically.
The pulse width set on pin 4 (4)1) will be the desired precomp
delay from nominal.

Shown in Figure 2 is a Phase-Lock Loop data separator
and the support logic for a single and double-density B" drive.
The raw data (Both clock and data bits) are fed to the.
WD1691 and FDI79X. The WD1691 outputs its PU or PO
signal, which is integrated by the .33uf capacitor and 330hm
resistor to form a control voltage for the 74S124 VCO device.
The 4.0MHZ nominal output of the VCO then feeds back to
the WD1691 completing the loop. The WD2143-01 is also
used, providing write precomf1ensation when in double-density, from tracks 44-77. The DDEN line can either be controlled by a toggle switch or a logic level from the host
system.

The data separator must be adjusted with the ROD or
VFOE;WF line at a Logic I. Adjust the bias voltage potentiometer for I.4V on pin 2 of the 74S124. Then adjust the
range control to yield 4.0MHZ on pin 7 of the 74S124.

RAW
DATA

1771-01

XTDS
1691
RDD

-+__..-~

74LS08

RCLK t...::12~ _ _

26
15
DDEN

FDDATA

FDCLOCK

N.C.

FIG. 1
WD1691 to FDI771-01 INTERFACE

SUBSTITUTING VCO's

There are other VCO circuits available that may be substituted for the 74S124. The specifications required are:
1) The VCO must free run at 4.0MHz with a I.4V control
signal. The WD1691 will force this voltage 1 Volt in
either direction (i.e., .4V = decrease frequency, 2.4V
= increase frequency). 1/ a ± 15% capture range is
desired, then a 1 Volt change on the VCO input should
change the frequency by 15%. Capture range should
be limited to about ± 25%, to prevent the VCO from
breaking into oscillation and/or losing lock because of
noise spikes (causing abnormally quick adjustments of
the VCO frequency). Jitter in the VCO output frequency
may further be reduced by increasing the integration
capacitor/resistor, but this will also decrease the final
capture range and lock-up time.

2) The sink output current of the WD1691 is 3.2ma minimum. The source output current is -200ua. Therefore,
source current is the limiting factor. Insure that the input
circuitry of the VCO does not require source current in
excess of - 200ua.
Another alternative is to use a voltage follower/level
shifter circuit to match the input requirements of the VCO
chosen. A more complex filter can be used to convert the
PUMP UP/PUMP DOWN pulses to the varying DC voltage
signal required by the VCO, achieving an optimum condition
between lock-up time and high frequency rejection.

404

-i>

200 NS ± 25

r->
~

RAW DATA
FROM DRIVE

271 RAW READ
+5

I SINGLE
•. b DENSITY
. 'y DOUBLE
FD179X

-LDENSITY
+5V
+5

1Jj,"~
R2

00 ,

RNG

47K

VCD
RDD

RCLK

~
15

100K
BIAS VOLTAGE
ADJ

~
13
14

WDIN
EARLY
PU
U\TE
PD

RCLK
7

WG
WD

EARLY
LATE

TG43

VFOE

VFOE/WF
10

47K

xl 04 03 02 01

+12~""PW

WD2143-01

PRECOMP ADJ
10K
1) ALL RESISTORS '1,W ± 5%
2) SPECIFICATIONS ~
CAPTURE RANGE: ±20%
LOCK-UP TIME: 25/,58C
(ALL ONE'S PATIERN, MFM)
3) FOR 5 1/4"
8

.68/,1
68!l

.33/,1
330

VCC~ +5
19
VSS 9

FIG_ 2
8" SINGLEIDOUBLE DENSITY FLOPPY INTERFACE

-t:=:
WPRT

TO
DRIVE
11

CLK,MR!

DDEN

WD1691 WG

I 2

RANGE

F2
74LS629

-.:-

.;..

4 OM HZ
.

WDOUT
VCC
-DDEN

CPU
INTERFACE

I DIRC

I STEP

TROO

READY

FROM
Df'IVE

1691U CERAMIC PACKAGE

1691V PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation
for its use; nor any infringements of patents or other rights of third parties which may resu" from ils US8, No license is granted by implication or otherwise under
any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL
C

c'"

ION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

406

WESTERN
DIGITAL
p
c

DM1883A/B Direct Memory Access Controller
oCI)

...

FEATURES

GENERAL DESCRIPTION

The DM1BB3 Direct Memory Access Controller
(DMAC) is packaged in a 40 pin standard dual in- ::::l
line package. The chip requires a single +5 power
supply input and a single clock input. The device «
contains B CPU addressable registers, and allows
for up to 8 CPU addressable device registers if the
automatic device chip select feature is used. Byte or
word transfers can be programmed, and all memory
DMA operations are handshaked for compatibility
with a variety of bus structures. Up to 256K bytes of
memory can be accessed directly with 64K page
protection and nonexistent memory interrupt as
options. Bus and Interrupt Acknowledge signals are
internally daisy chained, and a STOP REQUEST
input prevents new requests while a current request
is active. Device accesses are not handshaked, and
a BUS HOLD feature is present for high speed
devices. Device interrupt input, end-of-block
output, and I/O read/write output pins simplify
hardware interfacing to the device and the CPU bus.
The AUTO LOAD feature allows automatic bootloading of up to 64K bytes or words into memory
starting at location zero. An B bit interrupt 10 code is
also provided.

•
o
o

•
•
•
•
o
o
o
o
o
o
o

•
o

•

AUTOMATIC DAISY CHAINING OF BUS AND
INTERRUPT ACKNOWLEDGE SIGNALS
AUTO LOAD OPTION
SINGLE +5 VDC POWER SUPPLY
B BIT BI-DIRECTIONAL DATA BUS
TRUE OR COMPLEMENT DATA BUS
B CPU ADDRESSABLE DMAC REGISTERS
B CPU ADDRESSABLE DEVICE REGISTERS
AUTOMATIC GENERATION OF DEVICE CS
DURING DMA AND CPU DEVICE ACCESSES
.256K MEMORY ADDRESSING
64K PROGRAMMABLE PAGE PROTECTION
BYTE OR WORD DMA TRANSFERS
INTERRUPT AND BUS REQUEST CAPABILITIES
END-OF-BLOCK SHUT OFF BY DMAC
TIME-OUT INTERRUPT CAPABILITY
SINGLE CLOCK INPUT
CS, RE, WE, AO-A3 ADDRESSING
STOP REQUEST INPUT TO DELAY INTERRUPT OR BUS REQUESTS
COMPATIBLE WITH OUR FLOPPY DISC
CONTROLLERS
B BIT PROGRAMMABLE INTERRUPT
IDCODE

Iii
g

IACKO

oc.

BliCi1PW

vee

<1>4

4PW

3PW

4i2

2PW

1PW

ose OUT

XTAL 1

GND

XTAL2

~
2

4i2
3

T3
¢4

PIN CONNECTIONS

WD2143-01 BLOCK DIAGRAM

419

SYMBOL

PIN NUMBER

DESCRIPTION

1,3,5,7

-01-04

2,4,6,8

01-04

Four Phase, non-overlapping outputs, These outputs are true (active
high),

GND

Ground

10,11

XTAL1
XTAL2

External XTAL connections, An external crystal tied to these pins will
cause the oscillator to oscillate at the crystal .frequency,

OSC OUT

A TTL compatable output that is a divide-by-four of the
crystal frequency,

13-16

01PW-04PW

External resistor inputs to control the individual pulse widths of each
output. These pins can be left open if 0PW is used,

0PW

External resistor input to control all phase outputs to the same pulse
widths,

Vcc

+5V ± 5% power supply input

Four phase, non-overlapping outputs, These outputs are inverted
(active low),

DEVICE OPERATION
Each of the phase outputs can be controlled individually
by typing an external resistor from 01 PW-04PW to a
+5V supply, When it is desired to have 01 through 04
outputs the same width, the 01 PW-04PW inputs
should be left open and an external resistor tied
from the !/JPW (Pin 17) input to +12V,

XTAL1 and XTAL2 can be connected directly to a
series-resonant crystal, forcing the internal oscillator to
oscillate to the crystal frequency, XTAL2 (pin 11)
may also be driven by a TTL square wave with
XTAL 1 (pin 10) left open, Each ofthe four phaseoutputs provide both true and inverted signals, capable
of driving 1 TTL load each,

420

TYPICAL APPLICATIONS

11
XTAL2

XTAL2

WD2143-01
10

WD2143-01
NC

XTAL1

TIL SQUARE WAVE OPERATION

EXTERNAL CRYSTAL OPERATION

+5
13
5K

q,1
q,2
q,3
q,4

WD2143-01 1
17

+12

q,PW

q,2
q,3
q,4

q,1

q,2

cp2

WD2143-01
15

q,3

EQUAL PULSE WIDTH OUTPUTS

q,4

cp3

_cp4

INDIVIDUAL PULSE WIDTH OUTPUTS

10K

3D
W D f - - - - - - ; ClK

EARLY

EARLY f - . - - - - - ; 10

Wii
TO
DRIVE

NOMINAL

74lS175
lATE~+-~---~ 20

179X
FD
CONTROLLER

LATE
+5

ClR
18
11
10

VCC
XTAL2

XTAL1

<1>2

WD2143-01

.10K
<1>3
17

~
GND

<1>4 I--'-----'\Mr--~-< +12
PRECOMP
ADJUST

WRITE PRECOMP FOR FLOPPY DISK

421

~~----~~~"------~~
r-

XTALl

=:.j

Ted

~TPd~
~~

\
¢2

\1...________________

-Ii f--TN1>

---I

----------------------------~~~------------------------~t-TpR

\ ---Y
TN1>=:::J
________________________________

t:=

T N¢--1

TpF

~y~Tpw~~----------

I;==TN¢
-----------------Jyl--Tpw--l'-

NOTES,
Ted MEASURED FROM 90% VoH POINTS
T pW MEASURED FROM 50% VoH POINTS

WD2143-01 TIMING DIAGRAM

SPECIFICATIONS
Absolute Maximum Ratings
Operating Temperature

0 to +70 C
0

Voltage on any pin with
respect to Ground

-0.5 to +7V

Power Dissapation

1 Watt

Storage Temperature

-55 0 to + 1250 C

Note: Maximum ratings indicate limits beyond which
permanent damage may occur. Continuous operation at
these limits is not intended and should be limited to the
DC electrical characteristics specified.

422

DC ELECTRICAL CHARACTERISTICS
Vee = +5V ;: 5% R(G!NPW) or R(G!PW)

SYMBOL

= 5K,

PARAMETER

Vol

TTL low level output

Voh

TTL high level output

Vii

XTAL in low voltage

Vih

XTAL in high voltage

Icc

Supply Current

GND = OV T A = 0° to 70° C

MIN.

MAX.

0.4
2.4
O.B

2.4

UNITS

CONDITIONS

101

= 1.6 rna.

loh

= 100 ua.

V
V

All outputs open

SWITCHING CHARACTERISTICS
Vee =5V ;: 5%, GND

OV T A = 0° to 70° C

MAJ(.

UNITS

Ted

XTALintoOSCout(t)

100

Tpd

OSCout to

100

MAX.

UNITS

SYMBOL

PARAMETER

MIN.

PARAMETER

MIN.

Tpw

Pulse Width (any output)

100

Tnct>

Non·Overlap Time

Tpr

Rise Time (any output)

Tpf

Fall Time (any output)

TFR

OSC in Frequency
External Resistor

Tpw

Pulse Width Differential

CONDITIONS

CL = 30pf
apw = 5K

CL=30pf

3
100

mHz

423

CONDITIONS

k.n

0PWor 0nPW

0PW = 5K

0920
MAX.

~mmm-4N
0014

o 021 ~r.-L --I
........I
0035
06"55

rOJOOl

L'~~~I

MAX

100"

LOO9O
110
0

0125
MIN

0140
MAX.

r---~-----;

I Q.W I
1-- 0325 --1

-,
Q.Q11

-11:L- ..J L

0021--1

WD2143L-01 CERAMIC PACKAGE

320 1
1-°
I,-MAX11

0,045
0.065

0090

0"i"i'0

0 125
MIN

~g;;g -l

WD2143M-01 PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is
completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use: nor any infringements of patents or other rights 01 third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL 13128 REDHILL AVENUE, BOX 2180
COR

'I,

NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

424

WESTERN IlIIlG§TAL
c

WD1510-00, 01
14%£@*1@9*("\

UfO/F~FO

,,5

BUFFIER REGISTER
B ! 4!Q

M @&*i

FEATURES

APPLICATIONS

w"%¥

:.:a:

• WORD LENGTH SELECTABLE: 128 OR 132

• POINT OF SALE TERMINALS

• 9 BIT WORD WIDTH

• COMPUTER-TO-PERIPHERAL BUFFER

«
:::l

o DC TO 650 KHZ (-00),1 MHz (-01)
o EMPTY AND FULL FLAGS

o CRT BUFFER MEMORY
• LINE PRINTER BUFFER

m
w

o THREE-STATE DATA LINES

• INTERRUPT STACK (LIFO MODE)

• 5-VOLT ONLY
• NO EXTERNAL CLOCKS REQUIRED
• TTL COMPATIBLE ON ALL INPUTS AND OUTPUTS
o 28 PIN PLASTIC OR CERAMIC DIP
• MASTER RESET
GENERAL DESCRIPTION
The WD1510 is an MOSILSI Memory Buffer which is organized as a 9-bit by 128 or 132 word stack. The chip has
2 bidirectional data ports and may be read from or written
into either port. Thus, the chip can function as a LIFO from
either port or it can function as a FIFO, with data flow from
either port A to port B or vice versa. The DIRECTION input
pin is used to specify the data flow direction. The WD1510
is fabricated in 5-volt only N-channel technology.
PIN DEFINITIONS
PIN
NUMBER
1

FUNCTION

SYMBOL

NAME
VSS

VSS

Ground

EMPTY

Indicates when there is no data in the buffer

EMPTY

CHIP SELECT PORT A

-CSA

128 OR 132

1281132

Used to set word length. When low word length
when high word length = 132

MASTER RESET

When pulsed will clear the buffer and set the EMPTY
pin

6,8,10,12,14,
17,19,21,23

PORT A DATA LINES

PAD-PAS

Bidirectional DATA Port for reading or writing data

7,9,11,13,15
18,20,22,24

PORT B DATA LINES

PBO-PB8

Bidirectional DATA Port for reading or writing data

Used to select Port A for either a Read or Write
operation

= 128,

Vee

+ 5 volts

DIRECTION

DIR

When low DIR specifies that Port A may be read from
and Port B may be written into. When high DIR specifies that Port A may be written into and Port B may
be read from

SYSTEM SENTINEL™
CHECKOUT

SSC

No connection (For future use)

CHIP SELECT PORT B

CSB

Used to select Port B for either a Read or Write
Operation

FULL

Ind icates that all 132 or 128 words of memory are
loaded with data

425

± .25V

PORT
A

9 BITS

PORT
B

9 BITS

WD1510

DlR---.....J
M R - -_ _--I
1281132 - - - - - - - - - '

L _ _........ EMPTY
L ___

FULL

OPERATION
The WD1510 contains a 132 x 9 buffer which may be programmed for 128 x 9 operation. Setting the 128/132 pin to a
Logic 0 enables the EMPTY and FULL lines to be activated
when 128 bytes are read or written. When the128/132 line
is set to a Logic 1 or left open, the 132 byte operation is enabled. This line contains an internal pull-up resistor of approximately 5K!l.
When the Master Reset Line (pin 5) is set to a Logic I, all
internal counters are reset and the EMPTY Flag is set. Prior
to reading or writing data, the DIRECTION Line (pin 25) must
be set to select the desired operation:
DIR

PORTA

WRITE

READ

WRITE

PORTB

To operate the device in the FIFO mode, both Ports must
be used. If the DIRECTION Line is set to a Logic I, then data

is written into Port A and read out of Port B. Reading/Writing
to the two ports can be done asynchronously.
In the LIFO mode only one port is used. For example, if
using Port A, the DIRECTION Line is set to a Logic 1 to enter
data, and is reset to a Logic 0 to read data.
Reading or writing is performed by setting the appropriate
CS (Chip Select) Line to a Logic o. After the specified hold
time has..2Eired~a may be entered or read on the rising
edge of CSA or eSB. In a Read mode, data is valid as long
as CS remains active. Both Ports return to the high impedance state when CS is returned to a Logic 1.
The EMPTY Line (Pin 2) and the FULL Line (Pin 28) are
used as status or interrupt lines to determine the status of the
buffer. When both EMPTY and FULL are at a logic 0, the
buffer contains 1 thru 127 bytes (128/132 = 0) or 1 thru 131
bytes (128/132) = 1.

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Vee with respect to V ss (Ground)
Max Voltage on any Pin with
respect to Vss
Operating Temperature
Storage Temperature
SYMBOL
III
ILO
VIH
VIL
VOH
VOL
Icc

CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input low Voltage
Output High Voltage
Output Low Voltage
Power Supply Current

Operating Characteristics (DC)
+7V

= O°C to

70°C, Vss

= OV,

Vee

+5V ± .25V

-0.5V to +7V
O°C to 70°C
- 55°C to + 125°C
MIN

TYP

MAX

UNITS

CONDITIONS

10
10

f-LA
f-LA
V
V
V
V
mA

VIN = Vee
VOUT = Vee, Vss

2.4
.7
2.4

.4
125

426

200

10 = -40f-LA
10 = 1.6 mA
All outputs open

A.C. TIMING CHARACTERISTICS
TA = O'C to 70'C, VSS = OV, Vee

+5V ± .25V, VOH

CHARACTERISTICS

!sYMBOL
TMR
TOV
TOH
TOIR
TEV
TFV
TCSL
TCSH
TCY
ToS
FMAX

Master Reset Time
Data Valid from CS
Data Hold from CS
DIR Setup Time
EMPTY Valid from CS
FULL Valid from CS
CS Pulse Width Low
CS Pulse Width High
CS Cycle Time
Data Setup Time
Data Transfer Rate

TMR
Tov
TOH
TOIR
TEV
TFV
TeSL
TCSH
TCY
TOS
FMAX

Master Reset Time
Data Valid from CS
Data Hold from CS
DIR Setup Time
EMPTY Valid from CS
FULL Valid from CS
CS Pulse Width Low
CS Pulse Width High
CS Cycle Time
Data Setup Time
Data Transfer Rate

= 2.0V,

MIN

= O.BV

VOL

WD1 51 0-00
UNITS

MAX

TYP

CONDITIONS

NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
KHZ

400
550
150
1500
550
550
600
600
1540
80
650

WD1S10-01

350
100
1000
350
350
500
500
1000
50
1

I---

CSA

CSB

I
I

-+l

DATA MUST BE

IIIIH/1 111j

DIR

-I

TeSl

I+- TDS

DATA PORT

~6L.IQ

~ TOIA

I--or

I
I

/ / / / / / / / 7 / / 7 //A

DATA PORT

!-'- T OH

'/JIII///

----l

TCSL

~TDv-I

CSB

I
I
I

-----

WRITE OPERATION

CSA

NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
MHZ

250

DATA VALID

I
Xl / / / / / /

READ OPERATION

CSA

CSB

EMPTY or FULL

TMR

~TcSL
I
I
I
I
I

=+l
~I·

I+-

TCSH

TEV
TFV

OLD VALUE
Tey

MISCTlMING

427

-I

·1

NEW VALUE:

• II

[::0:::::1
WD1510F-XX PLASTIC PACKAGE

WD1510E-XX CERAMIC PACKAGE

xx
00 650kHz, versio1

01 1.0 MHz version

This is a preliminary specification wnh tentative device parameters and may be subject to change after final product characterization is
completed.
tnformation furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for ns use; nor any infringements of patents or other rights of third parties which may resu" from no use. No
license is granted by implication or otherwise under any patent or patent rights of Western Dignal Corporation. Western Dignal Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORAr,ON

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

428

Introduction to

ADVANCED SYSTEMS DBVISDON
The Advanced Systems Division markets a complete line of microcomputer
system products. These products combine file management,
telecommunications, high level language, and microprocessor expertise into
complete computer systems.
In 1974 Western Digital developed the first 16 bit microprocessor, the LSI-11 *
for Digital Equipment Corporation, and in 1976 developed the WD16 for Alpha
Micro Corporation, both of which are still in volume production.
The Pascal MICROENGINE, announced in 1978, signalled Western Digital's
entry into the sophisticated Microcomputer Systems Marketplace. The
MICROENGINE was the first microcomputer designed exclusively to maximize
performance of Pascal high level language software programs. Pascal has
rapidly become one of the most popular computer languages.
In 1980 the Modular MICROENGINE was introduced. This product is
implemented with one function per board (processor, memory, disk controller
etc.) to maximize versatility, expandability, and maintainability. It continues the
tradition of architecture optimized to high level language execution.
The Advanced Systems Division is operating its future product strategy
around continued use of Pascal, and use of the new programming language,
Ada. Ada is a language originally defined by the US Department of Defense as
part of its Standardization program. Functionally a superset of Pascal, Ada**
extends Pascal in four major areas: error recovery with exception handling;
separately compiled packages; multi task synchronization via rendezvous; and
strongly enforced user defined data types.
Advanced System Division products wi" significantly improve programer and
user productivity in the 80's .
• LSI-11 is a trademark of Digital Equipment Corporation.
** Ada is a trademark of the U.S. Department of Defense.

429

Table of Contents

ADVANCED SYSTEMS DIVRSHON
Page
WDOO90
WD0900

Pascal MICROENGINE Brochure

433

Pascal MICROENGINE Microcomputer

437

WD9000

Pascal Microprocessor Chip Set

441

WD9810

Pascal System Software

443

Pascal Compiler

445

Modular MICROENGINE

447

ME1600

431

432

WESTERN DIGITAL
CORPORATION

=iii

21S[;dL

~ICROENGINET.M.

MICROCOMPUTER PRODUCT UNE

433

THE PASCAL MICROENGINE CONCEPT
Westem Digital's Pasca l MICROENGINp·.. ·
Product Family is the only Microcomputer specifically designed to optimize execution of modem,
high order language programs.
Thus, the Pascal MICROENGINE user enjoys
the benefits of speed and ease of use in developing
and maintaining systems in a universally recog-

nized, block structured language, plus the memory
efficiency and performance advantages normally
available only in assembly language.
The machine language of the Pascal MICROENGINE is P-code, the "ideal" Pascal intermediate language, and thus the MICROENGINE is
the ideal Pascal machine.

WD/9000

WD/900

MICROPROCESSOR CHIP SET

SINGLE BOARD COMPUTER

The WD/9000 Pascal MICROENGINE Microprocessor is a 16 bit, MOSJ1...SI chip set that executes Pascal programs at speeds five to ten times
faster than equivalent systems using conventional
architecture.
The chip set consists of five 40-pin dual-in-line
LSI components :

The Pascal MICROENGINE is also available
on a Single Board Computer, the WD/900. This implementation reduces end product design and development costs in many applications where a
standard configuration can be employed. The WD/
900 contains the following:
Pascal MICROENGINE CPU
64K Bytes of RAM Memory

ARITHMETIC CoMPONENT
contains ALU ,
micro-instruction decode, register file and paths to
control processor operation.
CoNTROL PROCESSOR
contains control circuitry, macro-instruction decode, micro-instruction
counters, and liO control logic.
THREE MICROM'S
(each 22 bits x 512) contain the high speed microcode which implements
P-code.

Two RS-232 asynchronous/synchronous ports
(110-19.2K baud-full duplex). Synchronous
or asynchronous operation, odd or even
parity, SYN stripping enabled/disabled,
character length (5 to 8 bits), and switch
selectable for baud rate
Two 8-bit parallel ports (500 KHz maximum
data rate)
Floppy disk controller with direct memory access (DMA), switch selectable for :
Single or double density 8" floppy
Single or double sided operation
1 to 4 drives
Compatable with most standard floppy
models
IBM soft sectored format
Up to 4MB floppy disk storage

MICROENGINE chip set features include 16-bit
user-defineable liO and data paths; single-and
mult-byte instruction formats ; direct addressing to
128k bytes of memory; stack architecture for reentrant and recursive programs; four-level nested interrupt structure; hardware multiply/divide (16 bit
integer) and floating point (IEEE single precision
standard) instructions; memory mapped inpuUoutput capability; and TTL-compatable three-state interface. The MICROENGINE uses +5v, - 5v, and
+ 12v power supply voltages.

A 64KB memory expansion board is also available

WD/90

PACKAGED
PASCAL COMPUTER
The desktop computer features the 16-bit
MICROENGINE processor, 32K words (64K bytes)
of RAM memory, fully-integrated floppy disk controller, two flS.232 asynchronous/synchronous ports,
and two 8-bit parallel ports all on a single 8" x 16"
board, plus a power supply, packaged in a low-profile (5V." high x 16V." x 13'12") enclosure; UCSD
Pascal Software System (Version 111.0) on floppy
diskette; and the WD/90 Pascal MICROENGINE
Reference Manual.

434

PASCAL
Pascal is a universally used structured programming language developed by Niklaus Wirth
and defined in the Pascal User Manual and Report.
The language is suited to a broad range of applications: systems programming, real-time control,
data communication, business systems, education,
and most other applications. It encourages increased programmer productivity and more reliable,
maintainable, and transportable programs. Pascal
combines the data structuring capabilities of Cobol,
the block structuring of PLII, and the expression
handling of Fortran into a concise, efficient
language.
The Pascal MICROENGINE family is built
around the UCSD Pascal compiler and System
Software-the most widely used Pascal system for
small computers. UCSD's compiler contains the
Jensen-Wirth nucleus plus additional features which
extend Pascal's capabilities. Some of these language extensions include:

P-code on the 16-bit MICROENGINE processor
provides high system throughput.
LOWER SOFTWARE DEVELOPMENT COST
as a
high-level language with strong data typing, extensive error checking, and automatic reentrancy and
recursion, Pascal increases programmer productivity.
SHORTENED DEVELOPMENT SCHEDULES
critical
software schedules are shortened.
LOWER UPDATE/MoDIFICATION CoSTS
Pascal
programs cost less to change than those programmed in alternative languages.
EFFICIENT MEMORY UTILIZATION
P-machine
efficiency means that programs written in Pascal
for the MICROENGINE family often use less memory than even assembly language programs for
other architectures.
TRANSPORTABILITY
programs written in the
widely used UCSD Pascal system may be executed
on the other Pascal'based systems.
IMPROVED RELIABILITY
since Pascal programs are simpler statements of the algorithm to be
executed, they are less likely to fail in costly field
situations.

Long integers (up to 36 characters)
Data file access
Automatic loading of program segments
from disk storage
Separate compilation and linking of Pascal
modules
1[0 and interrupt programming in Pascal
Program synchronization via SIGNAL and
WAIT ON SEMAPHORE instructions
System design engineers using the Pascal
MICROENGINE family for Pascal-based system
development realize the performance benefits of
assembly language system development and the
cost benefits of Pascal systems. These include:
HIGH PERFORMANCE

direct

execution

COMPARISON OF
DIRECT P-CODE EXECUTION TO OTHER TECHNIQUES

FIGURE 3
The Pascal MICROENGINE microprocessor does not use the approaches listed.
Instead the Pascal compiler converts programs to
P-code which the MICROENGINE microprocessor
directly executes as its native instruction set.

FIGURE 1
Most microprocessor Pascal compilers are interpretive: the Pascal compiler produces
P-code which is then decoded and executed by a
software interpreter. Interpretation of each P-code
instruction requires execution of multiple processor
instructions.

FIGURE 2
Other Pascal compilers convert Pascal source programs into the target processor's
machine language. Thus Pascal programs are force fit onto architectures not efficient for Pascal, resulting in execution of more instructions for a given function.

435

cal, the system is very efficient, has low memory
requirements, and out performs equivalent machines with conventional architecture.
In addition to an operating system the Pascal
Software System provides software tools to support
program development, debug, and execution; manipulation of files; and data and text processing.

WESTERN DIGITAL'S UCSD
PASCAL SOFTWARE SYSTEM
Western Digital's UCSD Pascal Software System is a complete software development and program execution system that runs on the "ideal" Pascal P-code machine, as defined by the University
of California at San Diego (UCSD).
This "ideal" Pascal P-code machine has been
Implemented in hardware as the Western Dig~al
Pascal MICRO ENGINE. Because Pascal programs
run directly on a stack machine designed for Pas-

Western Digital's UCSD Pascal Software System includes:
Operating System
Pascal Compiler
Multi-tasking, concurrency primitives, and
interrupts
Screen and line oriented editors
File handler
Library and Linker systems
Software debugger
Utilities
Efficient execution of Pascal programs and
minimal memory requirements
Supports up to two serial devices, one parallel device, up to four single or double
sided and single or double density drives,
and 64K bytes of memory
Can be configured for specific CRT or TTY
terminals

WESTERN DIGITAL CORPORATION
Western Digital is an industry leader in the
fields of high order languages, mass storage controllers, telecommunications subsystems, and energy management devices. We serve over 1300
customers in 23 countries through 100 sales
representatives.
In addition to Pascal Microprocessors and Mi-

WESTERN DIGITAl.

CORPORATION

crocomputers, our sophisticated products include
custom microprocessors; floppy and Winchester disk
controllers; gate arrays; X.25, SDLCtHDLC/ADCCP,
Async/Bisync and ARINC avionics communications
controllers, UARTS, and USARTS; custom industrial controllers, digital thermostats, and industrial
timers.

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550,TWX 910-595-1139
NOVEMBER,l980

436

WESTERN DIGITAL
c

Pascal MICROENGINETM Product

PASCAL MICROENGINETM
16 BIT PASCAL MICROCOMPUTER

FEATURES

DESCRIPTION

• DIRECT EXECUTION OF PASCAL P-CODE.

The PASCAL MICROENGINE is the first microcomputer
specifically designed to optimize performance of high order
languages. The machine language of the MICRO ENGINE is
Pascal P-code.

• 16 BIT STACK ORIENTED ARCHITECTURE
• UP TO 12BK BYTES OF MEMORY

Thus the user enjoys the benefits of developing and maintaining systems in a modern, universally recognized high
order language; plus the performance and memory efficiency
advantages of machine language.

• 1 TO 4 DISK DRIVES
• UP TO 4 MB DISK STORAGE

The MICROENGINE is available as a single board microcomputer with the 16 bit, stack oriented processor, 64K bytes
of memory, a floppy disk controller, two full duplex serial and
two parallel I/O ports .

• SINGLE OR DOUBLE DENSITY DISKETIES
• SINGLE OR DOUBLE SIDED DISKETIES

.. rno

FULL DUPLEX SERIAL I/O PORTS (50-19.2K
BAUD)

• rno

An expansion card is also available which provides an additional 64K bytes of memory for more user program space
and faster execution.

• INTERRUPT DRIVEN DISC AND I/O

Both the MICROENGINE and expanded MICROENGINE are
also available in a desk top cabinet with power supply.

PARALLEL I/O PORTS (500K BYTE/SEC MAX
DATA RATE)

• HARDWARE FLOATING POINT
• HARDWARE MULTIPLY/DIVIDE
• 2.5 MHZ FOUR PHASE CLOCK

437

SPECIFICATIONS

Byte Arrays

PROCESSOR

LOB
STB

Load Byte
Store Byte

Stack Architecture
Record and Array Indexing Assignment
All operations are performed on the hardware stack
MOV
SINOO .. 7
INO
INC
IXA
IXP
LOP
STP

Instructions (P-code operators)
The machine language of the PASCAL MICROENGINE'M is the Pascal P-Code operator set.

Move Words
Short Index and Load Word
Static Index and Load Word
Increment Field Pointer
Index Array
Index Packed Array
Load a Packed Field
Store into a Packed Field

All instructions are one byte long, followed by zero
to three parameters.
Logicals
Constant One Word Loads
SOLC
LOCN
LOCB
LOCI
LCA

Logical AND
Logical OR
Logical NOT
Compare Unsigned Words less than
or Equal
Compare Unsigned Words Greater than
or Equal
Bit Not

LAND
LOR
LNOT
LEUSW

Short Load Word Constant
Load Constant Nil
Load Constant Byte
Load Constant Word
Load Constant Address

GEUSW
BNOT

Local One Word Loads and Store
SLOLl .. 16
LOL
LLA
STL

Short Load Local Word
Load Local Word
Load Local Address
Store Local Word

Integers
ABI
NGI
OUP1
AOI
SBI
MPI
OVI
MODI
CHK
EOUI
NEOI
LEOI
GEOI

Global One Word Loads and Stores
SLOOI .. 16
LOO
LAO
SRO

Short Load Global Word
Load Global Word
Load Global Address
Store Global Word

Intermediate Store
LOO
LOA
STR

Load Intermediate Word
Load Intermediate Address
Store Intermediate Word

Absolute Value of Integer
Negate Integer
Copy Integer
Add Integers
Subtract Integers
Multiply Integers
Divide Integers
Modulo Integers
Check Against Subrange Bounds
Compare Integers Equal
Compare Integers Not Equal
Compare Integers less than or equal to
Compare Integers Greater than or equal

Indirect One-Word Loads and Store

Reals

STO

FLT
TNC
RNO
ABR
NGR
OUP2
AOR
SBR
MPR
OVR
EOUREAL
LEOREAL
GEOREAL

Store Indirect

Extended One Word Loads and Store
LOE
LAE
STE

Load Word Extended
Load Address Extended
Store Word Extended

Multiple Word Loads and Stores (Sets & Reals)
LOC
LOM
STM

Load Multiple Word Constant
Load Multiple Words
Store Multiple Words

438

Float top of Stack
Truncate Real
Round Real
Absolute Value of Real
Negate Real
Copy Real
Add Reals
Subtract Reals
Multiply Reals
Divide Reals
Compare Reals Equal
Compare Real Less than or Equal
Compare Real Greater than or
Equal

Sets
ADJ
SRS
INN
UNI
INT
DIF
EOUPWR
LEOPWR

Adjust Set
Build Subrange set
Set Membership
Set Union
Set Intersection
Set Difference
Set Compare Equal
Set Compare Less than or Equal
(Subset of)
Set Compare Greater than or Equal
(Superset of)

GEOPWR

GEOBYT

SERIAL 110 PORTS
Baud Rates: 50-19,200 baud
Character Size: 5-11 bits
Full Duplex
Interfaces any RS232 compatible device

PARALLEL 110 PORTS

Byte Arrays
EOUBYT
LEOBYT

Size 64K or 128K Bytes
Cycle Time: 1200 ns

Byte Array Compare Equal
Byte Array Compare Less Than or
Equal
Byte Array Compare Greater than
or Equal

8 bits In
8 bits Out
Data Rate: Up to 500 K Byteslsec.

Interfaces to Following Line Printers:
Jumps
Centronics 700,701, 737 or equivalent
Unconditional Jump
False Jump
Equal False Jump
Not Equal False Jump
Unconditional Long Jump
False Long Jump
Case Jump

UJP
FJP
EFJ
NFJ
UJPL
FJPL
XJP

FLOPPY DISK
DMA Operation
Up to 4 drives, switch selectable for
Single or dual sided, and
Single or dual density

Procedure & Function Calls & Returns
CPL
CPG
CPI
CXL
CXG
CXI
CPF
RPU
LSL

Up to 4 MB capacity
Interfaces to Following Drives: Shugart 800 and 850
series, and all compatible drives such as
REMEX 4000 seris, Oume Datatrak S, CDC 94061",9406-3, 9404-B

Call Local Procedure
Call Global Procedure
Call Intermediate Procedure
Call Local External Procedure
Call Global External Procedure
Call Intermediate External Procedure
Call Formal Procedure
Return from User Procedure
Load Static Link On To Stack

MECHANICAL
Single board computer 8" x 16"
Expansion Card 8" x 16"
Desk Top Computer 5W' H x 16W' W x 13" D
ENVIRONMENT

System Control
Operating Range 0-50 0 C
Humidity 0-95%

Signal Semaphore
Wait on Semaphore
Load Processor Register
Store Processor Register

SIGNAL
WAIT
LPR
SPR

ELECTRICAL
Power ReqUirements
Single Board Computer

Debugger
BPT

-12V
100mA

CONNECTORS

Break Point

Serial Ports:
nector

Miscellaneous
NOP
SWAP

+5V -5V +12V
2.0A .5mA 500mA

No Operation
Swap Word Top of Stack with Word
Top of Stack -1

DB-25S

25 Pin right angle con-

Parallel and Floppy Disk Ports:
right angle connector

439

DC-375

37 Pin

ORDER INFORMATION

WD900 (X) * PASCAL MICROENGINE Single Board Computer
WD90 (X) * PASCAL MICROENGINE Desk Top Computer 110V
WD95 (X) * PASCAL MICROENGINE Desk Top Computer 220 V

* (X) indicates diskette option:
a=
b=
c=
d=

8"
8"
8"
8"

Single Density Single Sided
Single Density Double Sided
Double Density Single Sided
Double Density Double Sided

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139
DECEMBER 1980

440

WESTERN DIGITAL
c

Pascal MICROENGINETM Product

;.'<'~ 'J ~~".I i

"'~,

'" ~" .

"
~

THE WD9000 CHIP SET
16 BIT Pascal MICROPROCESSOR

FEATURES

DESCRIPTION

o DIRECT EXECUTION OF PASCAL INTERMEDIATE
CODE (P-CODE)

o ASSEMBLY LANGUAGE EXECUTION EFFICIENCY

The WD9000 PASCAL MICROENGINEtm Microprocessor is
a 16 bit MOS/LSI chip set that executes programs written in
Pascal at speeds five or more times greater than equivalent
systems using conventional architectures. This is because
the MICROENGINE chip set is designed to be the ideal Pcode (Pascal Psuedo code) machine. Its machine language
is the P-code produced by the UCSD Pascal complier.

o HIGH PERFORMANCE 16 BIT MICROPROCESSOR

The Chip Set consists of five LSI components:

o HIGH LEVEL LANGUAGE PROGRAMMING DEVELOPMENT SPEED AND EASE

o STACK-BASED ARCHITECTURE FOR REENTRANT
AND RECURSIVE PROGRAMS
o EXECUTES FULL UCSD PASCAL, VERSION 111.0

Arithmetic Component - contains the arithmetic logic
unit, microinstruction decode, register file, and paths to
control processor operation.

Control Processor - contains macroinstruction decode,
portions of the control circitry, microinstruction counters,
and I/O control logic.

MICROM Components -three high-speed, 512 x 22 bit,
custom MICROMS, microcoded for direct execution of
UCSD Pascal Version 111.0 P-Code .

o PROGRAM TRANSPORTABILITY
o PROGRAM SIZE TO 128K BYTES
• 3.0 MHZ FOUR-PHASE CLOCK

The MICROENGINE Microprocessor chip set is ideal for all
applications requiring 16 bit performance, assembly language efficiency and high level language speed of program
development and ease of use.

o FOUR-LEVEL INTERRUPT STRUCTURE
o IEEE HARDWARE MULTIPLY/DIVIDE
o HARDWARE FLOATING POINT
o SINGLE AND MULTI-BYTE INSTRUCTIONS
o TTL COMPATIBLE THREE-STATE INTERFACE
• MEMORY MAPPED I/O

441

~tE''':''
·w

5V '12V

GND

CND -511

SYSTEM
CONTROL
LINES

USEOFOR

~bgE§~N~:A
PIN ASSIGNMENTS

TlON

The following are pin assignments for the Pascal MICRO.
ENGINETM MicroprocessorChipSet:
MICROM CHIP PIN ASSIGNMENTS

DATA CHIP PIN ASSIGNMENTS

SIGNAL

=~.

SIGNAL

:'::. SIGNAL

:'ri.

21 02

31 MI807

SIGNAL

1 .3

11 DALOS

2 Vaa

12 DAlO9

22 WAIT

3 DALOO

13 DAllO

23 MIB15

34=

4 DALOI

14 OALII

24 MI814

5 DAlO2

15 CAU2

25 MI813

6 DAlOJ

16 DAUJ

26 MI812

7 DAlO4

17 OAL14

27 M1811

8 DAlOS

16 CAllS

28 MI810

:~.

MiBi56

33 MI805

35 MI803

'FJTB02
MiBOf

9 DAlO6

19 Vss

'MTEi'59

38=

10 DAL07

20 1214

Mii3'08

40 1211

39 V DO

SIGNAL

:~.

SIGNAL

:~.

SIGNAL

11 MIB16

21 212

2 Vas

12 REPL.Y

22 Vee

""Mii306

3 13

13 WAIT

23 MIBt5

Mrn05

4 12

14 DOUT

24 MIB14

34 MIB04

2 V aEi
3 NC

12 MIB17

4 NC
5 NC

25 Ne

MiBO'2

MiB14

18 He

28 MI809

38 MIBOO

Mi'608

9 MtB13

19 Vss

10 MIB12

20 1214

30 MISO?

DAL
MI.
NC
CS
lC>-3

WIR

•

VDO, BB, SS, CC
lACK
SYNC

7 MIB17

17 SYNC

27 MIBt1

18 DIN

28 MIB10

38 MIBOO

BUSY
COMPUTE

39 VOD

WAIT
OOUT

WESTERN DIGITAL

34 MIS03

15 Ne

33 MI804

8 BUSY

CORPORATION

24 Ne

36 Ne

36 MIB02

Mi"BM

14 Ne

26 MIB11

35 MIB03

22 Vee
23 CS

32 tli'B05

13 M1818

27 MI810

26 MIB12

30 MtB08

SIGNAL

31 MI806

16 Ne

25 MIB13

10 1214

~Ig.

17 Ne

15 W/R

9 COMPUTE 19 Vss.

5IGN ... l

21 0'2

7 MI815

16 lACK

10 RESEl

~IS.

6 NC

6 10

5 "

MiB16

M'iBOT

39 Voo
40 1211

SIGNAL DESCRIPTIONS

:I~.

1 .3

:~. SIGNAL

1 .3

CONTROL CHIP PIN ASSIGNMENTS

SIGNAL

DIN

""Mi"861

40 1211

REPLY MEMORY
RESET

DATA/ADDRESS LINES
MICRO INSTRUCTION BUS
NO CONNECTION
CHIP SELECT
INTERRUPT LEVEL.S
WRITE/READ
CLOCK PHASES
VOLTAGE LINES
INTERRUPT ACKNOWLEDGE
110 SYNCHRONIZATION
DATA IN
INHIBIT 110 OPERATIONS
SINGLE INSTRUCTION MODE
CONTROL TO DATA CHIP INTERFACE
DATA OUT
110 ACKNOWlEDGE
MASTER RESET

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139
DECEMBER 1980

442

WESTERN
DIGITAL
p
c

Pascal MICROENGINETM Product

PASCAL SYSTEM SOFTWARE
UCSD LEVEL 111.0
COMPATIBLE TEXT PROCESSING,
SOFTWARE DEVELOPMENT,
AND PROGRAM EXECUTION SYSTEM

FEATURES

DESCRIPTION

• OPERATING SYSTEM

Western Digital's UCSD Pascal Software System is a com·
plete software development and program execution system
that runs on the "ideal" Pascal P-code machine, as defined
by the University of California at San Diego (UCSD) .

• PASCAL COMPILER
.. MULTI-TASKING, CONCURRENCY PRIMITIVES, AND
INTERRUPTS
• SCREEN AND LINE ORIENTED EDITORS
• FILE HANDLER

This "ideal" Pascal P-code machine has been implemented
in hardware as the Western Digital Pascal Microengine™.
Because Pascal programs run directly on a stack machine
designed for Pascal, the system is efficient, has low memory
requirements, and out performs equivalent machines with
conventional architecture.

• LIBRARY AND LINKER SYSTEMS
In addition to an operating system the Pascal software system provides software tools to support program development, debugging, and execution, manipulation of files, and
data and text processing.

o SOFTWARE DEBUGGER
• UTILITIES
• EFFICIENT EXECUTION OF PASCAL PROGRAMS AND
MINIMAL MEMORY REQUIREMENTS
• SUPPORTS UP TO TWO SERIAL DEVICES, ONE PARALLEL DEVICE, UP TO FOUR SINGLE OR DOUBLE
SIDED AND SINGLE OR DOUBLE DENSITY DRIVES,
AND 64K OR 128K BYTES OF MEMORY
• CAN BE CONFIGURED FOR SPECIFIC CRT OR TTY
TERMINALS

443

Pascal Complier

• make copies of text

The Pascal compiler compiles Pascal source programs into
P-code that is directly executed by the MICROENGINE. The
UCSD Pascal language contains the Niklaus Wirth nucleus
with additional features to extend its capabilities. Some of the
language extensions are:

• include any portion of the text from another file
• conveniently move through the file
• set and jump to mar1 THEN ... ELSE ...

Segment procedures provide automatic loading of program
code from disk storage. Segment procedures and memory
overlaying in the operating system allows programs to run
that would use more than the amount of memory available.

• CASE OF ...
• REPEAT ... UNTIL

Modularity

• WHILE DO ...

The unit capability allows large programs to be broken into
smaller modules to be separately compiled and linked together. It also allows frequently used subroutines to be linked
into programs so that the source of the subroutines does not
need to be included in each program that uses it. All linking
is done before the program is executed.

• FOR .- TO DO ...
• WITH DO

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139
DECEMBER, 1980

446

Makin

9 the lea(LIngea
~'=========

ge work r.
oryou

ME 1600
MODULAR MICROENGINp

WESTERN DIGITAL
CORPORATION

447

ME1600 Modular MicroEngine'M
Software. nor hardware. has
become'the key to system efficiency
in the Eighties To this end. Westem
Digital has Innovated the MicroEngine:" It's a unique c;oncept.
designed to blaze the P-code trail.
making Pascal and Ada'" eminently
accessible. In fact. It executes
these high-order. block structured
languages directly. as ItS own native
Instruction set.
Now. to optimize usability and
fleXibility. we've expanded thiS
concept to the Modular MicroEngine. It's modular in choice of
languages - Pascal or MlcroAda: "
our microprocessor-based subset
of DoD mandated Ada'" And
I['s modular In system function. for
expansion freedom and seNlce
SimpliCity.
SpeCifically. each board In the
system Implements a distinct
function. processing. storage. file
management. I/O. and user access
to the Sentlnel/24 ,. bus.
Such modularity facilitates maintenance . And It puts the system
configuration deCISions squarely
In the hands of the OEM deSigner

The Ideal P-code machine.
Our Modular Micro Engine IS
based on the universally-embraced
UCSD Pascal compiler and System
Software. The result IS Incredibly
effiCient program compilation.
Unlike conventional processors.
which must Interpret PascallnstructlOns In their own language. the
MlcroEnglne executes ItS InternalIzed Pascal P-<:ode directly: it~the
processor's native language.
ThiS "software In hardware"
approach prOVides system deSigners
With a powerful combination:
the performance and effiCiency of
assembly language programming
and the time-saving SimpliCity of
the most advanced languages.
P-code was designed to run
most effiCiently on stack-oriented
processors. such as our Micro-

Engine. So programmer efficiency
is optimized. And there's no better
vehicle for developing fluency
with Pascal and Ada.

Speedier software development-with flexlblllty_
As high level languages with
strong data typing. extensive errorchecking. and automatic reentrancy
and recursion. Pascal and Ada are
designed to produce extremely
reliable code.
And the resulting programs are
easy to live with. They're less costly
to 'update and mOdify than programs in other common languages.

MEI601
Pascal & MlcroAda

Processor
J6-bit stack oriented processor

• Software-driven architecture·
Four interrupt levels · tia rd- _ _
ware multiply and divide, with
floating point · M emorymapped I/O • Real-time clock
• DMA control logic • Powerfall detection with auto restart

• System Sentinel™ protection
for bus "time-Qut:'

ME1610
128K Byte Memory Module
16K dynamic RAMs with 350ns

cycle time · Read/write access:
610ns • 16-bit word length •
Memory refresh interleaved - with bus access for minimum
memo!), latency.
ME1620
Floppy Disk Controller
Controls up to four floppy disk
drives · DMA operation · - Supports 8" drives · Single or
double density. single or double
sided • Diskettes may be
preformatted, or formatted
under program comrol.

ME1650/ 1651
Chassis/ Power Supply
10-slot SentJnel/24 card cage

· 15 or 25 amp power supply
• Senttnel/24 bus motherboard

448

And they're fully transportable
since Pascal and Ada are such
highly standardized languages.
Because algorithmic languages
allow simpler statements of the
program to be executed. they're
less likely to fail in the field.
The Modular MicroEngine's
UCSD Pascal Software System
includes: Operating System 0 Pascal
Compiler 0 Multi-tasking concurrency primitives and interrupts 0
Screen and line-oriented editors 0
Libral}'and Linker systems 0 Software
debugger 0 File management
utilities.

COMPARISON OF DIRECT P-COD E EXECUTION TO OTHER TECHNIOUES

Most microprocessor Pascal compilers are

Other Pascal compilers convert Pascal

interpretive: the compiler produces intermediate code lMlich is decoded and
executed by software interpreter. Each

source programs into the processor's
machine language. This force-fits programs
onto architectures not efficient for Pascal.
resulting in execution of more instructions
per function .
ME1639
Genera. Purpose
Interface Controller
Interfaces custom logIC to Sentinel/24 bus
• Includes all necessal)! control logic.
Including DMA and interrupts · FaCIlitates custom interface design. llllith

P-code instruction requires multiple
processor instructions, t:tking more time

and using more memory.

open SpaC:Zded

p""","

SOURCE
f'roGAAM

COMPILER

•I

P-COOE
l~D~D

EXECUTED

•

The Modular MicroEngine takes a direct
approach. The Pascal compiler produces
P-code \Nhich the MicroEngine is able
to execute directly as its own native
instruction set

System Conftguratlons
MEl660 Subsystem
Includes: MEI601 Pascal/M1croAda
Processor · MEI61D 128 KB Dynamic
RAM Memol}' Module ' MEI620
Floppy Disk Controller ' MEI63D
Seilal/Parallel I/O Controller '
MEI609 Boot/Terminator Module .
MEI651 10-slot ChaSSIS With 25 amp
Power Supply
ME1665 System
Includes: MEI660 Subsystem. plus:
One Double Density. Double Sided
Floppy Disk Dilve
ME1670 Packaged System
Includes: MEI660 Subsystem. plus:
One additional Double Density.
Double Sided Floppy Disk Dilve
(two total); Desk Top Enclosure
ME1675 Packaged System
Includes: ME 1670 Packaged
System. plus: Centronics 737 line
Pilnter; 80 Character by 24 line
CRT Terminal

ME1630

Serla lj Parallell/ O
Controller
Four RS-232-C full duplex
I/O channels: supports
asynchronous I/O; data transmission
at SO to 19.200 baud; interrupts may be
selectively enabled for each channel
• Parallel port tor interfacing printers. pJotters,
etc.; 8-bit input/output configuration;
compatible with Centronics printers.

449

Pascal
Pascal IS a universally used
structured programming language.
With appropriate library support it
is suited to a broad range of applications: systems programming, realtime control, data communication,
business systems, education,
and most other applications. Pascal
combines the data structuring
capabilities of COBOL, the block
structunng of PLjI, and the expression handling of FORTRAN into
a conCise, effiCient language.
The modular MlcroEnglne family
IS bUilt around the UCSD Pascal
compiler and System Softwarethe most widely used Pascal system
for small computers . UCSD's compiler contains the Jensen-Wirth
nucleus plus additional features
which extend Pascal's capabilities.
Some of these language extensions
Include:
• Long Integers
(up to 36 characters)
• Data file access
• Automatic loading of program
segments from disk storage

• Separate compilation and
linking of Pascal modules
• I/O and Interrupt programming
• Pascal program synchronization
via SIGNAL and WAIT on
SEMAPHORE Instructions.

MlcroAda
Ada is a new language defined
by the US Department of Defense,
as a standard language for all new
DoD systems. It is a modular, algorithmic language with strong data
typing and is primarily intended
for real time applications.
Functionally Ada provides
all the capabilities of Pascal, with
extensions In four major areas:

Exception handling for error recovery
• Separately com"iled packages .
Multi-task synchronization . Primitives for encapsulating and implementing of special I/O interfaces.
Western Digital's MicroAda is
a subset of the full Ada language,
and is deSigned to operate on our
MicroEnglne with 128KB of
memory. The initial release of
MicroAda will support most
features of Ada packages and
separate compilation, tasks and
exceptions, but generics, representation specifications and the more
complex exception handling
features Will not be Included.
Western Digital Intends to
support the full Ada language In
upcoming products.
For more information, contact your
sales representative at:
Westem Digital Corporation
3128 Red Hili Avenue, Box 2180
Newport Beach, CA 92663
(714) 557-3550 · T\\/X 910-595-1139
MlCroAda. MlcroEngt~. ~V2-4 and Sys~m ~ ate
traclM'lar1U of lJ..h~m DIgItal Corpotaoon ~ IS a tr.Idem.1f1(
~rtment of Oe~

01 mt U.S

WESTERN DIGITAL
CORPORA

450

The Control Systems Division offers a complete spectrum of products and
services, ranging from single-chip PMOS and NMOS microcomputers for
dedicated control applications to complete boards and finished products. In
addition, the Division is charged with developing and marketing products for use
in energy conservation and environmental control, including thermostats,
furnace, heat pump, and air conditioning controls, as well as lighting and
irrigation controllers and new sensor technology which are designed to
conserve and control all forms of energy in business and residential
environments. Another major thrust of the Division is the application of
microelectronic engineering services to supplement and improve upon existing
mechanical and electromechanical controls. From components to finished
products, Control Systems offers a complete spectrum of product support.

451

Table of Contents

CONTROL SYSTEMS DIVISION
Page

4 Bit Microcomputers

455

Designing With Electronics
WD51 Irrigation Controller
WD55 Industrial Timer/Controller

460
463

WD4020 ROMless N-Channel Microcontrollers

471
487

WD4200/WD4210 Single-Chip N-Channel Microcontrollers

495

453

4 BIT
MICROCOMPUTERS
Western Digital Control Systems Division offers both
PMOS and NMOS single chip microcomputers for dedicated controller applications. Both of these families
are true microcomputers in that they have on-chip
mask ROM, RAM, I/O, and clock generation-all olthe
elements required to implement a programmable microcontroller solution for your dedicated control problem.
Worldwide, the 4-bit microcomputer market is estimated to be approximately 20 million units in 1980 with
a growth rate of approximately 30% annually. Due to
the fact that they normally have very few if any external
support circuits, their cost effectiveness makes possible a wide diversity of applications such as:

CONSUMER APPLIANCES

Microwave ovens
Washers and dryers
Garage-door openers
House heating/cooling systems
Gas/electric ranges
Dishwashers
Lawn sprinklers
Water softeners

Specialty calculators
Copy machines
Dictation equipment

COMMERCIAL APPLIANCES

Electronic cash registers
Vending machines
Gasoline pumps
Elevator controllers
Printing presses
Cookers/fryers
Electronic weighing/marking
scales
Copy equipment
Automated "ticketing" machines
Weather monitors
Ice cream machines

SECURITY SYSTEMS

Intrusion alarms
Fire alarms
Water/flood alarms
Identification systems
Personnel counters
Electronic door locks
Violent weather alarms

CONSUMER ELECTRONIC PRODUCTS

Electronic games
Telephone answering machines
TV tuning synthesizer
CB radio synthesizer
Tape deck transports
Time zone clocks
Photographic timers/controllers
Electronic toys
Telephone dialer/memory
Telephone call-diverters
Hi-fi turntables
Hi-fi system controller
7-day alarm clocks
Automated slide projectors

AUTOMOTIVE/MARINE

Anti-skid braking system
Dashboard control
Systems status monitor
Fuel consumption/MPG computer
Anti-theft systems
Marine navigational calculator

INDUSTRIAL APPLICATIONS
OFFICE MACHINES

Simple machine control
Simple process control
Special counters/timers
Molding presses
Cooking equipment

Printing calculators
Postage machines
Small printing machines

455

ESTIMATED WORLDWIDE MICROPROCESSOR SHIPMENTS
32
30
28

2'
'c

26
24
22

~
~
!!l

20
18

E
Co
:;:

I/)

III

~
1:

::J

4·Bit Single Chip

4
2
O~

1st Otr

--__

______

2nd Otr

3rd Otr

4th Qtr

1st Otr

____L -____L -____L -__

2nd Otr

3rd Otr

1st Otr
1980

1979

1978

4th Otr

Source DATAOUEST, tnc.

SUBMISSION OF MASK
ROM CODE
To submit mask ROM code for the WD4200/4210,
two items need to be received:
(1) Completed 1/0 options list (see page ) describing
the desired configured of the mask-programmable
options.
(2) The object code itself.
The object code may be in the form of a diskette
containing the XXX,TRT and XXX,LM files generated
by a COP400 PDS development system, or EPROMS
(5204, 2708, 2716, etc.), paper tape, etc. (we prefer
the diskette or EPROMS), and a hard copy printout of
the object code. Western Digital will review and dupli-

cate the media submitted and will return copies to the
customer.
Upon written confirmation as to the correctness of
the data, masks are generated and an engineering
pilot run is commenced. At the completion of the pilot
run, approximately 10 devices are submitted to the
customer for verification and approval. Upon written
verification by the customer, the remainder of the pilot
run (usually several hundred devices) are shipped as
part of a pre-production delivery, and the production
wafers are started for predetermined, scheduled
delivery.

456

MASK OPTION CONFIGURATION TABLE
FOR WD4200/4210
(Reference WD4200 Data Sheet, Pg. 13)
MASK
OPTION

SELECTED
OPTION

MASK
OPTION

COMMENT

SELECTED
OPTION

COMMENT

Ground Pin

GO 1/0 Port

CKO Pin

G1 1/0 Port

CKllnput

G2 1/0 Port

RESET Pin

G3 1/0 Port

L7 Driver

03 Output

L6 Driver

02 Output

L5 Driver

01 Output

L4 Driver

DO Output

IN 1 Input NA 4210

Function

IN21nput NA 4210

Bonding

Vee Pin

L3 Driver

Customer:

L2 Driver

WDC PIN:

L 1 Driver

Customer PIN:

LO Driver

Sllnput

SO Driver

SK Driver

INa Input NA 4210

IN3 Input NA 4210

457

PREPROGRAMMED
MICROCONTROLLERS
Control Systems Division offers severa I preprogrammed microcontrollers which were developed by
the Division to solve timing and control problems which
previously had been implemented by electromechanical systems consisting of motors, cam switches, levers, etc. or for which a large number of random-logic
IC's were required. Several more devices are being
developed; for customized versions of these standard
products, please contact the factory.

WD-51 IRRIGATION CONTROLLER
The WD-51 performs all of the timing and control
functions required by a 6-station irrigation (sprinkler)
control system for residential and commercial
applications.
The only support circuitry required is a simple power
supply, display, keyboardlswitch matrix, and triac or
other high-current solenoid driver. The device is fully
programmable for a 7-day week and each station output is programmable from 0 to 99 minutes duration. Up
to 3 complete watering cycles per 24 hour period are
available, as well as a pumplmaster valve output and
a rain-inhibit switch input.

WD-55 TIMER/CONTROLLER
The WD-55 is a general purpose timing element for
use as a dark room timer, process sequencer, appliance timer, time-delay relay, recycling timer, etc. It
may be configured for two different modes of operation: one mode utilizes a convential matrix keyboard
for data entry, in conjunction with a 4-digit LED or VF display for generating up to seven timed sequential
outputs. Another mode allows data entry through BCDencoded switches for triggered or continuous control
of 2 outputs.

WD4200/4210
These devices are fabricated using N-channel technology, and are hardware and software compatible
with National Semiconductor's COP 420/421 devices.
The WD4200 is available in a 28-pin package and features 23 110 lines. The WD4210 is a bonding option
which deletes the 4-bit IN-port and is available in a 24pin package. They both feature 1K x 8 ROM, 64 x 4
RAM, a 4.0p.s instruction cycle time, 4.5 to 6.3V operation, a 3-level subroutine stack, single-level interrupt, serial 110 plus sync, on-chip counterltimer, and
a high current 8-bit bidirectional port capable of directly driving LED displays.

WD4020
This is a ROMless version of the WD4200. It is available in a 40-pin package and has all of the 110 lines

of the WD4200 but in addition has a multiplexed address/data bus to interface with external EPROM or
PROM memory. It is hardware and software compatible with the WD4200 and thus may be used for in-circuit emulation of the mask-ROM part for hardwarel
software debugging. Also, since it requires only an offchip latch and PROM, it may be used to implement a
low cost 3-chip microcomputer for low-volume, cost
sensitive applications.

CR2272/2282
These devices are fabricated using P-channel technology and are available in a 40-pin package. The
CR2272 has 512 x 10 words of ROM, while the CR2282
features 640 x 10 words of ROM. Both have 32 x 4
words of RAM, 16 latched outputs, 2 latched inputs,
8 scan outputs, and direct LED of V-F display drive
capability.

PRODUCT/SYSTEM
DESIGN CAPABILITY
Control System's technical staff has in-depth experience in applying microcomputer technology to
consumer and industrial applications. This experience
includes:
(1) Electronic circuit design
(2) Software (programming) design
(3) System integration
(4) Complete product deSign, development, and
testing.
In addition, Western Digital's Controlled Energy Division, located in Riverside, California, has extensive
capabilities for the assembly and test of PCB's ranging
from prototype to high volume production.
A typical development cycle for a complete product
is shown in Figure 1. The initial starting point of a product hinges on the availability of a functional specification. The functional specification describes in detail
the function which the end product is supposed to perform. If this is not available, WDC has the capability
of working with the customer in developing mutually
acceptable specifications based on our experience
and the customers' wishes or ideas for a product.
Upon completion of the functional speCification, the
preliminary hardware and software phase is entered.
During this timeframe, the electronic circuit design is
performed and a prototype, usually consisting of a
handmade wire-wrapped breadboard, is produced.
During this same time, the software design is being
performed and is mated with the prototype hardware
by means of an emulator board containing the software in EPROM. This prototype is then available for
customer checkout. At this stage, changes can be
made relatively easily since the prototype can be reprogrammed and rebuilt with minimal expenditures of

458

time and effort. However, with attention given to the
initial specification development, these changes can
be minimized to a great extent.
It is important to note that the circuit design can incorporate any part the design engineer and customer
feel is best, even though that part may not be made
by Western Digital.
When the customer is satisfied with the performance
of the hardware and software, a hard tooling phase is
entered in which the program information is converted
to mask ROM single-chip microcomputers and the
hardware design is converted to a printed circuit board

assembly. At the completion of this phase usually a
field trial with these preproduction systems is performed. Hopefully, the changes required as a result of
the field trial are minimal at this time, since significant
changes can become very costly during this phase,
due to the fact that software is now in mask ROM form.
If no changes are required, a pilot run is then performed to allow WDC or other producers to smoothly
move into a volume production phase.
If you wish further information on these capabilities,
please contact the Control Systems Division to discuss
your product in detail.

CONTROL SYSTEM DIVISION

YES

CHANGES

2-4W

YES

CHANGES

FIELD TRIAL
WITH PRE·
PROD PARTS

Figure 1

459

DESIGN NEWS
Reprinted from

February 5, 1979

Designing With Electronics
One approach is to let the electronics supplier do some, of all, the work
Bill McDonough, Applications Manager, Western Digital Corp., Newport Beach, CA

How long have design engineers been talking about
integrated circuits (ICs), medium-scale integration (MSI)
and large-scale integration (LSI)? Five, maybe ten
years? Compared to gears, detents, motors, bearings,
pulleys, levers and the like, that's a relatively short time
in which to provide case histories pertinent to every
situation.
Although it's natural for engineers and designers to
wonder how to apply these electronic technologies to
their own products, there are many unanswered questions and nebulous answers floating around. Lower
cost, part-count reduction, increased efficiency, improved performance and better reliability are hinted at
in discussions of LSI application to mechanical systems. But why would a designer who's been doing his
job right, and who has a good, reliable design, be motivated to change to electronics?
It is almost anecdotal, but too often the design engineerdoesn't determine that he needs a specially designed circuit or LSI chip until his competition announces a new product using this technology. When
the need to follow suit becomes apparent, he basically
has one of two choices to make. Will he attempt to
bring electronics expertise in-house or will he seek
assistance from an outside source?
There are several things to consider if the designer
opts for the first choice. First, simply hiring bright,
young electrical engineers with microprocessor and
LSI technology backgrounds will not solve the problem.
Although these engineers probably will be the bestqualified in the company technically, most often they
are grossly unqualified to make necessary decisions
because they lack understanding of company and market needs.
Second, bringing the design work in-house requires a
system design team-electronics assembly problems
must be addressed, the design must be tested and the
reliability must be proven. Companies literally enter a
whole new business when they choose to develop their
own electronics. The large companies of this world can
afford to design, assemble, test, and prove, but many
companies cannot afford to work this way. Sometimes
company profit margins are so thin that they will remain
mechanical even if the time is right for the application
of electronics.
The design engineer does, however, have another alternative-he can have chips specially designed by an
outside firm. And this is where he runs into many unanswered questions. Where does one go to get this
type of help? _Are specially designed "subsystem chips"

available? What is included with this.custom service?
Would it be a proprietary chip? And finally, what does
it cost-not only the end-cost, but what will it cost to
find out whether LSI application is feasible for the
product?

WHERE TO GET THIS HELP
One of the primary reasons that companies are reluctant to seek outside assistance is that they simply do
not know where to turn. The semiconductor supplier
market is not clearly defined. Certainly there are the
large semiconductor suppliers who will gladly ship custom chips in 100,OOO-piece volumes. But unless the
design engineer is able to seek help from his tried-andproven industrial control suppliers, the only answer for
the low-volume buyer has been the circuit board assembler-a middleman firm specializing in custom
work.
Typically, one of these "board stuffers" assembles
functional PC boards using designs furnished by the
engineer. Some of these firms may also be able to aid
in the board deSign, but often another middleman in
the form of a consultant may be required to help the
designer decide what to stuff on the board.
There is, however, another option available to the
second-level, low-volume buyer seeking outside help.
Some semiconductor suppliers, like Western Digital,
recognizing the "hole" in the market, are now willing
to provide as little or as much assistance as required
for quantities as low as 10,000 units. Yes, the cost per
unit will be more than for the 100,000 order, but at least
now more companies are able to consider electronics.
Services such as these will open the door to a lot of
business that might otherwise be forced to remain mechanical or use some standard semiconductor product
that can't provide all the desired features.

WHAT KIND OF HELP TO EXPECT
There are four major stages the potential chip-user
goes through to arrive at his end product. Depending
on his level of electronics expertise, he can seek help
at any or all of these stages from the semiconductor
manufacturer.
Step 1: The design engineer must compile a list of
product requirements and desired features. This can
take the form of detailed specifications or just general
function specifications. Basically, what does the product have to do?
A semiconductor supplier will sit down with the de-

460

Typical development schedule for a custom circuit

~h
Task
LDGIC DESIGN
(Upsized Schem.)
RAM Address "
Controller

Control Logic

MARC H APRIL

MAY

JUNE

JULY

AUG

NOV

DEC

JAN

FEB

I
I

Layout Design
CAD Conversion

signer and help him draw up his specification, if necessary. There is normally no charge for this service
if a predetermined volume is involved.
Carried to the next logical step, a parts list can be
drawn up from the spec and a development cost estimated. The manufacturer can also estimate a competitive production price at this pOint.
By considering cost/volume trade-otis at the start, the
designer benefits from these new services right up
front. Based on a particular product volume, the designer will know whether his $100 product will now sell
for $90 or $110 with electronics. Designers can decide
fairly early whether it's the right move to make.
As a part of the initial proposal, this is a service for
which a fee is generally charged. But it may also identify unconsidered advantages: additional selling features, a better display, increase reliability, and fewer
moving parts.
It's not unlikely that the main issue will be shown to be
features, and not strictly cost. And that has to help any
product proposal's chances of success during the marketing and financial review process. The important
thing to remember is that it is not simply a sUbstitution
of electronics for mechanics. The electronics will allow
the addition of more features now, and later will make
it easier to make further modifications.
Step 2: The design engineer must select a semiconductor product to fulfill his specification. When he seeks
assistance from a semiconductor firm he has basically
three options open to him.
The progammable solution. With the semiconductor
manufacturer's help, the design engineer can determine if his application will be satisfied with a standard
manufacturer-supplied chip, or microcontroller. Functions such as timing control, temperature control, set
pOint control, special purpose computation and appliance control can often be accomplished electronically
with a standard c:hip. For example, Western Digital has
standard chips programmed to replace logic in vending
machines and the timers in sprinkling systems.

461

I-u, -g

..:

f-,

rJJ
rJJ

..:

Mr
I,,.

Masks

rJJ
rJJ

..:

CIRCUIT DESIGN
(Sized Schem.)

Debug

OCT

Check

Fab

SEPT

,.
I

f-"

I,,.

....,

I~r-

r-f'l

Depending on the design engineer's expertise, he may
elect to program the standard chip himself, or he may
have the manufacturer do it for him.
If the designer elects to do his own programming, he
can expect free application help from the semiconductor manufacturer and enough literature to tell him how
to do the job. For the chip supplier, this is the simplest
way of doing business; in this case, the designer should
be able to order for a nominal program charge.
If the supplier will be programming the chip, he will
expect a typical order to be in the 10,000-to-100,000unit range over the first year. Programming costs might
be expected to run anywhere from $7000 to $20,000,
depending on the complexity of the application. Typically, this process takes 12 weeks from spec to singlechip programmed device.
Programming costs, in the case of Western Digital, can
be kept reasonably low because complete display timing and control functions are built into the chip hardware, as opposed to being written into the program.
This design eliminates customization or program time
usually involved with the display loop and initially saves
100 to 150 instruction words.
The custom circuit approach is the second option
open to the design engineer. The programmable solution is not always feaSible, espeCially if the intended
application is complex. In this case, a manufacturer
can build a custom circuit from scratch to perform the
required functions. The typical product development
time in this case is nine months and development costs
will run approximately $50,000. The design engineer
should be considering between 50,000 and 250,000
units per year to justify this development cost.
The integrated hardware solution is the third option
available to the design engineer. Here the semiconductor manufacturer does the system design and provides a PC board with components already mounted
and tested and ready to plug into the end product. This
route will cost out anywhere from $25,000 to $100,000.
Step 3: The designer must now decide how he is going

to design and assemble his product to do the job required. Unless the design engineer has chosen the integrated hardware solution, he buys his chip, whether
standard or custom, programs it himself or has the
manufacturer program it and is then responsible for
putting that chip on a board. At this pOint, he must also
select and design a display, a keyboard and an
interface, integrate them all together and add plugs.
Step 4: The designer has to decide whether he's going
to produce the board himself or have someone else
produce it in volume. If the designer has elected to go
with a standard chip, he can seek bids for the board
production from several manufacturers or he can produce the board himself.
If the designer has commissioned a specially designed
subsystem chip, he can opt for the designing manufacturer to handle the board production, or again, he
can handle it himself.
A TYPICAL CASE
Let's take a hypothetical situation from start to finish
to illustrate how this process would take place.
XYZ Company manufactures electromechanical irrigation system controllers. Their competition suddenly
comes out with an electronic device that does a more
efficient job. XYZ's marketing people inform their president that, to stay ahead in the market, XYZ's product
will now have to offer a better resolution of the time
cycle: one-minute increments (instead of standard five
to ten minutes) and multiple cycles (previously unavailable) to compensate for terrain differences. And,
it must remain at a competitive cost.
XYZ's president promptly hands the problem to his
design team. From a marketing timetable standpoint,
we would hope the conclusion is quickly reached that
outside help will be necessary. At that pOint, contact
is made with the applications department of a semiconductor manufacturer. The applications people sit
down with the XYZ's designers, evaluate the product's
requirements and write an objective specification.
After a suitable microcontroller has been selected,

XYZ will then decide whether the software program will
be written in-house or by the semiconductor manufacturer-a service generally priced between $7000 and
$13,000. If XYZ chooses to have the supplier do the
programming, the semiconductor maker typically will
require a production commitment before taking on the
assignment.
Let's say XYZ opts have the supplier do the programming. The company then supplies the semiconductor
firm with an order for a predetermined minimum number of chips to be used over the first year. XYZ is now
committed to pay a developmental fee for programming and tooling the chip; typically a 50% deposit will
be made to the manufacturer at this point.
Four to eight weeks later, XYZ can expect a system
prototype. In effect, the manufacturer supplies the
equivalent of a three-chip solution, with the program
resident in PROM to allow modification of the program
during prototype evaluation.
Meanwhile, XYZ is designing a board to accept this
part. The three-chip system is put on the board, it is
plugged in and field testing begins. XYZ will pinpoint
problems and change features, and the manufacturer
will make the changes accordingly until XYZ feels they
have a system that works and are ready to go with it.
The manufacturer will then pick up the rest of the developmental fee and build a single-chip part. This process can take three to six weeks. Under these conditions, XYZ owns the program and the part-it is their
proprietary chip. The company has paid in the neighborhood of $7000 to $13,000 but has done its own
board work.
If XYZ did not have the capability to do the board work,
the supplier could do this also, and would supply the
board a:·t work and design to XYZ, well documented.
In this case, XYZ would not necessarily end up with a
proprietary product.
So, when the design challenge or problem-solution first
indicates you should "go electronic," talk to a semiconductor manufacturer and see how they can help
you. You may be pleasantly surprised at the very personalized treatment.

462

WESTERN
DIGITAL
p
c

WD-51 IRRIGATION CONTROLLER
o

....

Ii
::l

FEATURES

GENERAL DESCRIPTION

• CONTROLS UP TO 6 IRRIGATION STATIONS
• PUMP CONTROUMASTER VALVE OUTPUT
• USER PROGRAMMABLE FOR UP TO 3 WATERING
CYCLES DURING A 24 HOUR DAY
• USER PROGRAMMABLE RUN TIMES OF 1 TO 99 MINUTES FOR EACH STATION
• USER SELECTION OF WATERING DAYS OF 0 TO 7
DAYS PER WEEK
• TIME OF DAY AND DAY OF WEEK CONTINUOUSLY
DISPLAYED
o RAIN INHIBIT MODE
o EASY TO DESIGN IN

Preprogrammed Controller for Irrigation Applications.
The WO-51 is a single-chip controller preprogrammed to
operate a 6 station irrigation system. It is implemented
using P-channel silicon gate MOS/LSI technology and
requires minimal support circuitry. All program and data
storage are on·chip, as well as input switch matrix scan, 7
segment display decode and drive, and output control
logic.

FUNCTIONAL DESCRIPTION
The logic symbol and block diagram of the WO-51 is
shown in Figure 1.

ROM

SCAN

INPUTS

CPU

CONTROL
OUTPUTS

SCAN
OUTPUTS

FIGURE 1 BLOCK DIAGRAM

, 463

PIN DESCRIPTION
SYMBOL

PIN NO.

VSS
VDD
SegA,B,C,
D,E,F,G

STN 1,2,3,
4,5,6

Positive Supply voltage

Negative Supply voltage

2·6,39·40

--RESET

INO, 1N1, 1N2,
1N3

FUNCTION

Decoded 7-Segment Multiplexed outputs,
15 mA source.
A low-level input voltage resets internal logic and
initializes RAM data.

Scanned inputs, 1N3 is MSB

12·15

17-19, 21-23

Station Output control for solenoid drivers.

PUMP

Pump control output- a high-level output indicates
a manual or automatic cycle is in progress.

60HZ

60 HZ time base input

50HZ

50 HZ time base inpu'.

DMUX

4-digit display control output

DO-D7

31-38

Digit scan outputs, (D7=MSD. DO=LSD)

I------ T eve

I
I
,

I
I'

_ _ _-'-I

I\~,

--'I_ _ _ _--,_-+_--"'~"___
I VA~IDfO.R4~CLOC.Ot--

-0-

1
15

12~ y,.

INa VSS

AT1

~;o~~~ ~
SEGc
SEGd
SEGe
SEGf
SEGg

IN1

RT2

13 IN2

AT,

RESET

D5---()

s,;;;

-0---

OVRl

DVR2

D-

DVR3

D-

DVR4

OVR5

~
~

r
S
~T2

24 VAC

::::::=::::=::

2N3904

220

0.1

40
39

~~SS

FIGURE 5

-1

5TN2

~--~.
•

STN3

Oj1
STN4

5TN5

STNS

VDD

D1
02
o
3
D4

PUMP

33
34

Vss

r~7 ~

--vo- r--058963.
ULN

r--

r------

2800
ETC

~
DVA7

3" COM CATHODE
LEDS

WD51

Vss

+lJ.1F

STNl

COMMON

MSD

LSD

IN3

DVR6

22011

10K

ADN

-0-

0<[

J---=::J

4 7K
.

I
COMPLETE 6-STATION IRRIGATION CONl ROLLER

cnWOI--OZ

I
Vss

SEG

6
5

SEG b
SEGc
SEG d

Va CbO DdJ
0=0
= 0=0 D=D

seG e
seG f

40
39

SEG 9

WD51

Vss
ULN2004

Dp 31

ATKa

01 32

02
A2

VDD

04 35

05 36
37
06

4019

PUMP

OMUX

{>:

02 33
03

-J:-

~-VSs

I,~

10K
10K

FIGURE 6

WD51 WITH 4-DIGIT DISPLAY OPTION

I
vss

SEGa
SEG b

SEGc
SEGd
SEG e

SEG!
SEG 9

,
3

MULTIPLEXED

(

J~_~c~~_rr~~

~~..Jli

r-- ,--

WD51

DISM

"7
Y FIl
DO 31

----

·
··

01 32

~11r==c

05 36
06 31

07 3B

...
VOD

...

V,
10-50 K

FIGURE 7
WD51/VACUUM FLOURESCENT
(V-F) DISPLAY INTERFACE

469

vGG

MECHANICAL
40 Pin DIP Package available in plastic or ceramic packages.

'" C: :::0:: : : :::1
L

_2080

.MAX

040

MIN

~ J!~ ~

i't'x \jp~JilVVi18ftRfVfiVffW ~ ~
~~
-.j !1kI
IL....
~fJ
-~

035

090

055 ....
014
~r-- 021

110

WD51A CERAMIC PACKAGE

•

640

690

WD51B PLASTIC PACKAGE

SUPPORT:
Application and Design support is available from Western Digital.

ORDERING INFORMATION:
Specify upon ordering
WD51 A for 40 pin ceramic package
WD51B for 40 pin plastic package

This is a preliminary specificaUon with tentative device parameters and may be subject to change after final product characterization is
completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digrtal Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation
reserves the right to change said cirCUitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE. BOX 2180
NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

470

WESTERN DIGITAL
CORP

WI!) 55

~U'UdlUJ]stIrHa~ T~mer/CoU'Utro~~elr

FEATURES:

APPLICATIONS:

o LOW COST PREPROGRAMMED MICROCONTROLLER
o USEABLE WITH KEYBOARD OR DISCRETE
SWITCHES
o HIGH CURRENT LED OUTPUTS OR DIRECT
DRIVE OF VACUUM FLUORESCENT (V-F)
DISPLAYS
o UP TO 7 SEQUENTIAL OUTPUTS
o SYNCHRONIZED WITH 50/60 HZ TIME BASE OR
EXTERNAL OSCILLATOR
o SINGLE TIME OPTION
o CONTINUOUS OR SEMI-AUTOMATIC OPTION
o DEDICATED TIMER OPTION-WORKS WITHOUT
KEYBOARD OR DISPLAY
o RESOLUTIONS OF FROM 0.1 SEC. TO 999
HOURS WITH DIGITAL ACCURACY
o ALARM OUTPUT FOR AUDIBLE BUZZER
o RELAY AND TRIAC OUTPUTS
o AUDIBLE FEEDBACK FOR USE WITH MEMBRANE SWITCHES
o 100 MW TYPICAL POWER CONSUMPTION

o DARKROOM TIMER
o PROCESS CONTROLLER
o PROCESS SEQUENCER
o TIME DELAY RELAY
o APPLIANCE TIMERS
o DEFROST CONTROLLERS
o "DRIP" AND "MIST' IRRIGATION CONTROLLERS
o ON/OFF TIMER
o DIGITALLY CONTROLLED TIME DELAY
o TRAFFIC LIGHT SEQUENCER
o SECURITY SYSTEMS
o LIGHTING CONTROL
o INTERVAL TIMER
o RECYCLING TIMER

VSS

SEG F

SEG E

SEG G

SEG 0

SEG C

SEG B

SEG A

RESET

elK

GENERAL DESCRIPTION
The WD-55 is a versatile, self-contained digital timer/
controller/sequencer designed to replace many of the
timing and control functions currently being performed
by gears, cams, levers, and motors. It is another in a
series of "silicon software" preprogrammed microcontrollers based on the WD40 family of 4-bit microprocessors. The WD-55 may be used in conjunction with
a matrix keyboard and numeric display to implement
a programmable timer/sequencer or with suitable
"strap" options, may be used as a dedicated, standalone on/off controller. It is implemented in P-channel
Silicon Gate MOS and is available in 40 pin plastic and
ceramic DIP packages.

471

iNS

SEa5

IN3

SED6

IN2

SEQ7

IN1

TRIG

INa

TBASE

ALARM

5EQ4

OUT

SEQ3

OUT

SEQ2

VDD

SEQ1

FIGURE 1.
WD-55 PIN CONNECTION

WD-55 PIN DESCRIPTION

PIN NO.

SYMBOL

FUNCTION

One of 7 highcurrenL(20 MA source) outputs for
direct LED drive

One· of 7 high current (20 MAsource) outputs lor
direct LED drive
One of 7· high current
direCt LED drive

472

WD-55 PIN DESCRIPTION (Continued)
PIN NO.

FUNCTION

SYMBOL
SEQ5/TIM1

One of 7 sequencer outputs, active high during
preset timing interval 5

Digit output, LSD

Digit output

Digit output, MSD

SEGF

One of 7 high current (20 MA source) putputs for
direct LED drive

SEGG

One of 7 high current (20 MA source) outputs. for
direct LED drive .

FUNCTIONAL DESCRIPTION
The WD-55 is a versatile digital timing element designed to replace mechanical timing devices of the
synchronous motor. cams. and lever variety. It is a
preprogrammed mask-ROM single chip 4-bit microcontroller with different features determined by external strap options. It has essentially two distinct
modes of operation: a keyboard programmable
timer/sequencer using on-chip RAM for data storage
and a 4-digit 7-segment display for data recall, or as
an on/off timer which uses thumbwheel switches or
even diodes for data storage and recall and does not
require a display. These two different modes are
selected by the absence or presence of a diode between the D7 digit output (38) and the INO scanned
input (15). If the diode is absent, upon the occurrence
of a reset pulse at pin (8), the device enters the
keyboard programmable timer/sequencer mode. If
the diode is present, a reset forces the device into
the on/off timer mode.
In the timer/sequencer mode, the WD-55 operates
with a matrix keyboard and a 4 digit numeric display to
form a simple but flexible digital timing device for use
in applications such as a dark room timer or programmable sequencer. The configuration table shown in
Figure 1 provides the definition of keys, display digits,
and strap options.
Keyboard: The WD-55 is useable with a standard
4x4 matrix keyboard (or 3x4 with two off-board
switches) of the electromechanical or "membrane"
type; audible feedback through the alarm output is
provided for use with membrane or other switches
which have little or no tactile feel. The debounce time
is approximately 100 ms using a 60HZ timebase.

473

FIGURE 1. CONFIGURATION TABLE
PROGRAMMABLE TIMER/SEQUENCER

KEY DEFINITIONS

STRAP CONFIGURATION

ADVANCE: The key is used to access the 7 storage
locations in RAM. Each time this key is depressed,
the sequence number (digit 3) is incremented by one
and the current value of the respective sequence is
fetched and displayed in digits 00-02 (least to most
significant). If the current sequence number is 7,
depressing the advance key will rollover to sequence
#1. If the "1 sequence" strap is present (see strap
options), this key is not required.

Considerable versatility is accomplished with the
WO-55 by the use of strap options in the form of
diodes to select or delete specific functions. In the
timer/sequencer mode, the following options are
available.

SET/ CLEAR: This key enables the entry of data
into the RAM location currently being displayed by
digit 3. When depressed, it enables the "SET" mode
and clears display digits 00-02 to zero as well as the
respective memory location. Successive entry of data
with the numeric keys (0 through 9) is then allowed.
The set mode is terminated by depressing any nonnumeric key. Note that there is no need for an "enter" or "store" key since the data displayed on digits
00-02 is always automatically stored. If "SET/
CLEAR" has not been depressed prior to a numeric
key, the numeric key is ignored, preventing the accidental or unwanted entry of data.

MANUAL ON/OFF: This key acts as a push on/
push off switch to manually force the output pins
(OUT (19) and OUT (18» to toggle. This is used to
manually force an output on, such as in a darkroom
timer application where the enlarger needs to be
turned on and adjusted before proceeding with a
timed interval. These outputs will remain in their current state indefinitely until either the manual key is
depressed again or a timed interval is initiated. It has
no effect on any of the sequencer outputs, SEQ1-7.
START/STOP: This key is used to initiate or terminate a timed sequence. If a timing cycle is not being
performed, depressing this key will initiate a cycle
beginning with the sequence currently being displayed in digit 3. If a cycle is currently running, it will
terminate it, returninq the two complementary outputs
(OUT and OUT) to their normal state and incrementing
the sequence digit by 1. In fact, when a timing
sequence is currently active, this is the only key
which is scanned. This key may be paralleled with an
external start/stop or footswitch if dictated by the application.

NUMERIC KEYS (0-9): These keys are used to
enter numeric data when in the "SET" mode. Data
entry is accomplished by right to left entry; that is,
digits 0 to 2 are left-shifted by 1 digit (with the old
value of digit 2 discarded) and the most recently depressed numeric key data entered into digit zero.
There is no limit to the number of numeric keys
which are entered, but only the most recent 3 are
displayed and stored. If the "SET/CLEAR" key has
not been previously depressed, these keys are ignored.

50 HZ STRAP: The W055 uses an external time
base to accomplish its timing functions. It is optimized for use with 50 or 60 HZ AC line applications.
For operation with 60HZ, no strap is necessary. For
50HZ applications, a diode should be connected between 03(34) and IN3(12).
1 SEQ STRAP: This strap (a diode between 02(33)
and IN3(12) ) forces the device to operate as though
it had only 1 time available. At the end of the timed
sequence, the SEQ digit does not advance and the
SEQ1 data is restored to digits 0-2. When this strap
is employed, the advance key should not be used
and the sequence digit (Digit 3) is always a "1" and
hence couid be eliminated.
.1 SEC STRAP: Without this strap, the basic resolution of the 7 sequences is 1 sec. That is, intervals of
from 1 to 999 seconds are possible. With a diode (or
diode plus SPST switch for variable applications) between 07(38) and IN1(14), the minimum resolution is
decreased to .1 seconds; that is, the intervals are
now from .1 to 99.9 seconds.

"AUTOMATIC" STRAP: With a diode between
07(38) and IN2(13), the automatic mode is enabled.
In this mode, once the START key is depressed,
sequences 1 through 7 are executed without further
intervention. The cycle stops at the conclusion of
sequence 7; that is, SEQ 1 data is being displayed
and the keyboard is again being scanned. This is
useful when the WO-55 is being used as a sequencer to cycle a complete 7-event sequence.
"AUTOCONTINUOUS" STRAP: This is used in
conjunction with the "automatic" strap mentioned
previously. If a diode is connected between D7(38)
and IN3(12), the device will operate continuously
once triggered by the start/stop key. This strap must
be connected through a switch, since there is no
means of terminating the sequence once initiated.
Sequence 7 will be followed immediately by sequence 1. Depressing the start/stop key during the
cycle will only terminate the current sequence in
progress and begin execution of the next. This mode
would typically be used in process control, machine
sequencer, "moving lights" displays, etc.

INITIALIZATION
A low going pulse of sufficient duration (see Electrical
Data) on the RESET pin (8) will force an initialization
state, usually as the result of a power-turn-on reset. All 7 sequence times are set to zero and the
sequence number digit (Digit 3) is set to "1". The
complementary outputs OUT and OUT are set to logic
LOW and logic HIGH respectively, and all sequencer
outputs are logic LOW.

474

STOPWATCH/ELAPSED TIME CONTROLLER: If
a nonzero time is entered into any sequence location, the WO-55 will count that time down to zero before advancing to the next sequence. However, if the
stored data is already zero, depressing the START /
STOP key will initiate an "UP" count mode starting
from zero. The outputs (OUT and SEQ) function as
before. If the START/STOP key is activated during
this count cycle, the count will stop, the elapsed time
will be displayed, the outputs will return to their "off"
state, butthe sequence number will not advance. This
allows the W055 to act as a "stopwatch" with a cumulative time capability and as an elapsed time controller
to time and control a variable event.

S +
WD4020AE: -40 --->
WD4020B: -0 ---> +
WD4020BE: -40 --->

70"C, CERAMIC PACKAGE
+ 85"C, CERAMIC PACKAGE
70"C, PLASTIC PACKAGE
+ 85"C, PLASTIC PACKAGE

Ik::ense is granted by implication or otherwise under any patent or patent rights of Westem Digital Corporation, Western Digital Corporation
reserves the right to change said circuitry at anytime without notice.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

494

WESTERN
DIGITAL
p
c

WD4200/WD4210 Single-Chip N-Channel Microcontroilers
FEATURES

GENERAL DESCRIPTION

o Low cost
o Powerful instruction set
o 1Kx8ROM,64x4RAM
o 23110 lines (WD4200)
o True vectored interrupt, plus restart
• Three-level subroutine stack
• 4.01lS instruction time
o Single supply operation (4.5V to 6.3V)
" Internal time-base counter for real-time
processing
o Internal binary counter register with serial 1/0
capability
o General purpose and TRI-STATE® outputs
o TTL/CMOS compatible in and out
o LED direct drive outputs
o MICROBUSTM compatible
o Software/hardware compatible with other
members of WD4200 family
o Extended temperature range device available
(-40°C to +85°C)

The WD4200 and WD4210 Single-Chip N-Channel
Microcontroliers are members of the Control Oriented Processor family, fabricated using N-channel,
silicon gate MOS technology. They are complete
microcomputers containing all system timing, internal logic, ROM, RAM and I/O necessary to
implement dedicated control functions in a variety
of applications. Features include single supply
operation, a variety of output configuration options,
with an instruction set, internal architecture and I/O
scheme designed to facilitate keyboard input,
display output and BCD data manipulation. The
WD4210 is identical to the WD4200, except with 19
I/O lines instead of 23. They are an appropriate
choice for use in numerous human interface control
environments. Standard test procedures and reliable
high-density fabrication techniques provide the
medium to large volume customers with a
customized Control Oriented Processor at a low
end-product cost.

Figure 2 WD4200/4210 BLOCK DIAGRAM

,4&

495

PIN DESCRIPTION
L7-LO 8 bidirectional 1/0 ports with
TRI-STATE®
G3-GO 4 bidirectional 1/0 ports
D3-DO 4 general purpose outputs
IN3-INO 4 general purpose inputs (WD4200 only)
SI Serial input (or counter input)
SO Serial output (or general purpose
output)
SK Logic-controlled clock (or general
purpose output)
CKI System oscillator input
CKO System Oscillator output (or general
purpose input or RAM power supply)
RESET System reset input
VCC Power supply
GND Ground
FUNCTIONAL DESCRIPTION
A block diagram of the WD4200 is given on page 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit is set, it is
logic "1" (greater than 2 volts). When a bit is reset, it
is a logic "0" (less than 0.8 volts).
Program Memory
Program Memory consists of a 1,024-byte ROM. As
can be seen by an examination of WD4200/4210
instruction set. these words may be program
instructions, program data or ROM addressing data.
Because of the special characteristics associated
with the JP, JSRP, JID and LQID instructions, ROM
must often be thought of as being organized into
16 pages of 64 words each.
ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024
8-bit words contained in ROM. A new address is
loaded into the PC register during each instruction
cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next
sequential 10-bit binary count value. Three levels of
subroutine nesting are implemented by the IO-bit
subroutine save registers, SA, 58 and SC, providing a last-in, first-out (UFO) hardware subroutine
stack.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode. Control and
Skip Logic circuitry.
Data Memory
Data Memory consists of a 256-bit RAM, organized
as four data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit 8 register whose
upper two bits (Br) select one of four data registers
and lower 4 bits (8d) select one of 16 4-bit digits in

the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into
or from, or exchanged with. the A register (accumulator), it may also be loaded into or from the
Q latches or loaded from the L ports. RAM
addressing may also be performed directly by the
LDD and XAD instructions based, upon the 6-bit
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4-bit data sent directly to the D outputs.
Internal Logic
The 4-bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load
and input four bits of the 8-bit Q latch data, to input four
bits of the 8-bit L 1/0 port data and to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic
functions of the WD4200/4210, storing its results in
A. It also outputs a carry bit to the I-bit C register,
most often employed to indicate arithmetic
overflow. The C register, in conjunction with XAS
instruction and the EN register, also serves to
control the SK output. C can be outputted directly to
SK or can enable SK to be a sync clock each
instruction cycle time (see XAS instruction and EN
register description below).
Four general-purpose inputs,
IN3-INO' are
provided; IN1, IN2 and IN3 may be selected, by
a mask-programmable option, as Read Strobe,
Chip Select and Write Strobe inputs, respectively,
for use in MICROBUSTM applications.
The D register provides four general-purpose outputs
and is used as the destination register for the 4-bit con·
tents of Bd.
The G register contents are outputs to four generalpurpose bidirectional 1/0 ports. GO may be maskprogrammed as an output for MICROBUS™
applications.
The Q register is an internal, latched, a-bit register,
used to hold data loaded to or from M and A, as well
as 8-bit data from ROM. Its contents are output to
the L 1/0 ports when the L drivers are enabled under
program control (see LEI instruction). With the
MICROBUS'M option selected, Q can also be loaded
with the a-bit contents of the L 1/0 ports upon the
occurrence of a write strobe from the host CPU.
The eight L drivers, when enabled, output the
contents of latched Q data to the L 1/0 ports. Also,
the contents of L may be read directly into A and M.
As explained above, the MICROBUSTM option
allows L 1/0 port data to be latched into the Q
register. L 110 ports can be directly connected to the
segments of a multiplexed LED display (using the
LED Direct Drive output configuration option) with

496

3. With EN2 set, the L drivers are enabled to output
the data in Q to the L 1/0 ports. Resetting EN2
disables the L drivers, placing the L 1/0 ports in a
high-impedance inputstate.lfthe MICROBUSTM
option is being used, EN2 does not affect the L
drivers.

Q data being outputted to the Sa-Sg and decimal

point segments of the display.
The SIO register functions as a 4-bit serial-in/serialout shift register or as a binary counter depending on
the contents of the EN register (see EN register
description below). Its contents can be exchanged
with A, allowing it to input or output a continuous
serial data stream. SIO may also be used to provide
additional parallel 1/0 by connecting SO to external
serial-in/serial-out shift registers. For example of
additional parallel output capacity, see Application
No.2.

The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of
each bit of this register selects or deselects the particular feature associated with each bit of the EN register
(EN 3- EN ol·
1. The least significant bit of the enable register,
ENO, selectes the SIO register as either a 4-bit
shift register or a 4-bit binary counter. With ENO
set, SIO is an asynchronous binary counter,
decrementing its value by one upon each lowgoing pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles
wide. SI< outputs the value of C upon execution
of XAS and remains the same until the execution
of another XAS instruction. The SO output is
equal to the value of EN3. With ENO reset, SIO is
a serial shift register shifting left each instruction
cycle time. The data present at SI goes into the
least significant bit of SIO. SO can be enabled to
output the most significant bit of SIO each cycle
time (see 4 below). The SK output becomes a
logic-controlled clock, providing a SYNC signal
each instruction time. It will start outputting a
SYNC pulse upon the execution of an XAS
instruction with C = 1, stopping upon the execution of a subsequent XAS with C = O.

EN3, in conjunction with ENO, affects the SO
output. With ENO set (binary counter option
selected) SO will output the value loaded into
EN3. With ENO reset (serial shift register option
selected), setting EN3 enables SO as the output
of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with
the serial shift register option selected disables
SO as the shift register output: data continues to
be shifted through SIO and can be exchanged
with A via an XAS instruction but SO remains
reset to "0". The table below provides a summary
of the modes associated with EN3 and ENO.

Interrupt
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing
interrupts.
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program
counter address (PC + 1)onto the stacl<, pushing
in turn the contents of the other subroutine-save
register to the next lower level (PC+1 .-,. SA .-,. SB
.... SC). Any previous contents of SC are losl. The
program counter is set to hex address OFF (the
last word of page 3) and EN 1 is resel.
b. An interrupt will be aclmowledged only after the
following conditions are met:
1) EN1 has been set.
2) A low-going pulse ("1" to "0") of at least two
instruction cycles wide occurs on the IN1
input.
3) A currently executing instruction has been
completed.

2. With EN1 setthe IN1 input is enabled as an interrupt input. Immediately following an interrupt,
EN1 is reset to disable further interrupts.

ENABLE REGISTER MODES -

BITS EN3 AND ENO

EN3

ENO

SIO

SI< AFTER l(AS

Shift Register

Input to Shift Register

Shift Register

Input to Shift Register

Serial Out

Binary Counter Input to Binary Counter

=1, SK =SYNC
= 0, SK =0
If C =1, SI< = SYNC
If C =0, SI< =0
If C = 1, SK " 1
If C =0, SK =0
If C =1, SI< = 1
If C =0, SK =0

497

If C
If C

4) All successive transfer of control instructions
and successive LBls have been completed
(e.g., if the main program is executing a JP
instruction which transfers program control
to another JP instruction, the interrupt will not
be acknowledged until the second JP instruction has been executed.
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon the
execution of a subsequent RET instruction. For
example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry)
instruction which results in carry, the skip logic
status is saved and program control is transferred to the interrupt servicing routine at hex
address OFF. At the end of the interrupt routine,
a RET instruction is executed to "pop" the stack
and return program control to the instruction
following the original ASC. At this time, the skip
logic is enabled and skips this instruction because of the previous ASC carry. Since, as
explained above, it is the RET instruction which
enables the previously saved status of the skip
logic, subroutines should not be nested within
the interrupt servicing routine since their RET
instruction will enable any previously saved
main program skips, interfering with the orderly
execution of the interrupt routine.

relationships between the WD4200 signal lines affected
by this option are as specified for the·MICROBUSTM
interface, and are given in the AC electrical characteristics and shown in the timing diagrams (figures 11
and 12). Connection of the WD4200 to the MICROBUSTM
is shown in MICROBUSTM Option interconnect
illustration.
Initialization
The Reset Logic, internal to the WD4200/421 a will
initialize (clear) the device upon power-up if the
power supply rise time is less than 1 ms and greater
than 1 11 s. If the power supply rise time is greater
than 1 ms, the user must provide an external RC network and diode to the RESET pin as shown below.
The RESET pin is configured as a Schmitt trigger
input. If not used it should be connected to VCC.
Initialization will occur whenever a logic "0" is
applied to the RESET input, provided it stays low for
at least two instruction cycle times.
Upon initialization, the PC register is cleared to a
(ROM address 0) and the A, B, C, D, EN, and Gregisters are cleared. The SK output is enabled as a
SYNC output, providing a pulse each instruction cycle
time. Data Memory (RAM) must be cleared by the
user's program, The first instruction at address a must
be a CLRA.

d. The first instruction of the interrupt routine at
hex address OFF must be a NOP.
e. A LEI instruction can be put immediately before
the RET to re-enable interrupts.

POWER
SUPPLY

a-BIT DATA BUS

MICROBUSTM Interface

The WD4200 has an option which allows it to be
used as a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor (IlP). IN1, IN2, and IN3 general purpose
inputs become MICROBUSTM compatible readstrobe, chip-select, and write-strobe lines, respectively. IN1 becomes RD - a logic "0" on this input
will cause Q latch data to be enabled to the L ports
for input to the IlP. IN3 becomes CS - a logic "0"
on this line selects the WD4200 as the IlP peripheral
device by enabling the operation of the RD and WR
lines and allows for the selection of one of several
periopheral components. IN 3 becomes WR - a logic
"0" on this line will write bus data from the L ports to
the Q latches for input to the WD4200. Go becomes
INTR a "ready" output, reset by a write pulse from
the IlP on the WR line, providing the "hand-shaking"
capability necessary for asynchronous data transfer
between the host CPU and the WD4200.
This option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
system for8-bit parallel data transfer between MOSI
LSI CPUs and interfacing devices. (See MICROBUSTM,
National Publication.) The functioning and timing

CLOCK

Do-D7
MICRO PROCESSOR

READ STROBE

(AD)

CHIP SELECT (CS)
RITE STROBE (WAI

Figure 3

MICROBUSTM OPTION
INTERCONNECT

POWER
SUPPLY

1
RC>5

x POWER

SUPPLY RISE TIME

Figure 4 POWER-UP CLEAR CIRCUITS

498

OUT

Oscillator

put of another WD4200/4210 with CKI connected
as shown. In this configuration, the SK output
connected to CKO must provide a SYNC (instruction cycle) signal to CKO, thereby allowing
synchronous data transfer between the WDs
using only the SI and SO serial I/O pins in conjunction with the XAS instruction. Note that on
power-up SK is automatically enabled as a
SYNC output (see Functional Description, Initialization, above).

There are four basic clock oscillator configurations
available as shown below.
a. Crystal Controlled Oscillator. CKI and CKO
are connected to an external crystal. The instruction cycle time equals the crystal frequency divided
by 16 (optional by 8).
b. External Oscillator. CKI is configured as a TTL
compatible input accepting an external clock
signal. The external frequency is divided by 16
(optional by 8 or 4) to give the instruction cycle
time. CKO is now available to be used as the
RAM power supply (VR) or as a general purpose
input.

CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a general purpose input, read into bit
2 of A (accumulator) upon execution of an INIL instruction. As another option, CKO can be a RAM power
supply pin (VR), allowing its connection to be a
standby/backup power supply to maintain the integrity
of RAM data with minimum power drain when the main
supply is inoperative or shut down to conserve power.
Using either option is appropriate in applications where
the WD4200/4210 system timing configuration does
not require use of the CKO pin.

c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation
frequency divided by 4. CKO is available for nontiming functions.
d. Externally Synchronized Oscillator. Intended for
use in multi-WD systems, CKO is programmed to
function as an input connected to the SK out-

(VR OR GENERAL
PURPOSE INPUT
PIN)

EXTERNAL

CLOCK
CRYSTAL OSCILLATOR

EXTERNAL OSCILLATOR

RC CONTROLLED OSCILLATOR

WD4200f4210

WD4200/4210

so
51

EXTERNALLY SYNCHRONIZED OSCILLATOR

Crystal Oscillator
Crystal
Value

4 MHz
3.58 MHz
2.09 MHz

1K
1K
1K

RC Controlled Oscillator

Component Values
R2
C
1M
1M
1M

R (k!2)

27 pF
27 pF
56 pF

Figure 5

12
6.8
8.2
22

WD4200/4210 OSCILLATOR

499

C (pF)
100
220
300
100

Instruction
Cycle Time
in lIS
5±20%
5.3 ±23%
8 ±29%
8.6 ± 16%

1/0 Options

f. An on-chip depletion load device to Vec.

WD4200/4210 outputs have the following optional

g. A Hi-Z input which' must be driven to a "1" or "0"
by external components.

configurations, illustrated below.
a. Standard. An enhancement-mode device to ground
in conjunction with a depletion-mode device to VCC
compatible with TLL and CMOS input requirements.

The above input and output configurations share
common enhancement-mode and depletion-mode
devices. Specifically, all configurations use one or
more of six devices (numbered 1-6, respectively).
Minimum and maximum current (lOUT and VOUT)
curves are given on figure 7 for each of these devices
to allow the designer to effectively use these 110 configurations in designing a WD4200/4210 system.
The SO, SK outputs can be configured as shown in
A, B, or e. The 0 and G outputs can be configured
as shown in A or B. Note that when inputting data to
the G ports, the G outputs should be set to "1". The L
outputs can be configured as A, B, D, or E.

b. Open-Drain. An enhancement-mode device to
ground only, allowing external pull-up as required
by the user's appl ication.
c. Push-Pull. An enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Vcc.
This configuration has been provided to allow for
fast rise and fall times when driving capacitive
loads.
d. LED Direct Drive. An enhancement-mode device
to ground and to Vce, meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off under program control (see Functional Description,
EN Register), placing the outputs in a high-impedance state to provide requi(ed LED segment blanking for a multiplexed displa'y.

An important point to remember if using configuration A or D with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a small amount of current.

e. TRI-STATE® Push-Pull. An enhancement-mode
device to ground and VCC intended to meet the
requirements associated with the MICROBUS'"
option. These outputs are TRI-STATE® outputs,
allowing for connection of these outputs to a data
bus shared by other bus drivers.

WD4210
If the WD4200 is bonded as a 24-pin device, it becomes the WD4210, illustrated in figure 1, WD42001
4210 Connection Diagrams. Note that the WD4210
does not contain the four general purpose IN inputs
(IN3-INO)' Use of this option precludes, of course use
olthe IN options, interruplfeature, and the MICROBUSTM
option which uses IN1-IN3' All other options are available for the WD421O.

WD4200/4210 inputs have the following optional

configurations:

B.OPEt'-ORAIN

A. STANDARD

C. PUSH·PULL

Vee

~".
~

(A IS DEPLETION DEVICE)

D.LEO

"PUT@--!(
G. HI-Z INPUT

F. INPUT WITH LOAD

Figure 6

OUTPUT CONFIGURATIONS

500

DEPLETION LOAD OFF SOURCE CURRENT

"Eo
~

"
Eo

\~AX

~'N

VOUT (VOLTS)

VOUT (VOL TS)

DEVICE 1

DEVICE 2

PUSH-PULL SOURCE CURRENT

STANDARD OUTPUT SOURCE CURRENT

200

Vcc - 6 3V

"
.9

.s125

''""

I"V

Vee; 63V (MIN)

:kl

VCC o

VOUT (VOL T5)

63V (MAX)

I I

1 1

MAX

Vcc = 4.5V (MAX

VOUT" 2,OV

Vec = 4,5V (MIN)

~cck ~

MIN

A I
--~
.......
'-

l,-

I I

DEVICE 3

LED OUTPUT DIRECT LED DRIVE

I I
\

I I

DEVICE 2

LED OUTPUT SOURCE CURRENT

"63V
(MIN)

\ T- 1-vlcc '(~~~)
vCCI=(~~N~ ~ ..\l. I

F-- ~
VOUT (VOLTS)

(MAX)

viC

~ee = 4 5V (MIN)

Vee = 45V (MAX)

"'- ~

025

vJJ-

(MAX)

... ...
55

VOUT (VOLTS)

DEVICE 4

..
65

Vee (VOL T5)

DEVICE 4

TRI-STATEI'! OUTPUT SOURCE CURRENT
INPUT LOAD SOURCE CURRENT

-.l

.4 5V

/JCC = 63V (MAX)

(MAX

\ \
\

6.3V (MAX)

l\ \
'\ '\ -"""""'
k' K
VOUT (VOLTS)

Vec ; 45V (MAX)

~
45V (MIN)
63V (MiN)

I"'--

K
-.c...

lX
K~

1--

'/Vcc = 4,5V (MIN)

-..,.~

VOUT (VOLTS)

DEVICE 5

Figure 7

/'::.yce~63V'(MIN)

OUTPUT CHARACTERISTICS

501

DEVICE 6

WD4200/4210 INSTRUCTION SET

Table 1 is a symbol table providing internal architecture, instruction operand, and operational symbols
used in the instruction set table.

Table 2 provides the mnemonic, operand, machine
code, data flow, skip conditions, and description
associated with each instruction in the WD4200/4210
instruction set.

TABLE 1. WD4200/4210 INSTRUCTION SET TABLE SYMBOLS
Symbol

Definition

Symbol

Definition

INTERNAL ARCHITECTURE SYMBOLS

A
B
8r
8d
C

EN
G
IL

4-bit Accumulator
S-bit RAM Address Register
Upper 2 bits of 8 (register address)
Lower 4 bits of 8 (digit address)
l-bi! Carry Register
4-bitData Output Por!
4-bit Enable Register
4-bit Register to latch data forGI/O Port
Two l-bi! Latchesassociated with the IN3
orlt"oJO Inputs
4-:bit InputPor! . . ,
8.~bit TRI-STATE@)I/O"Pr!
~~bil contents of RAM Memory Pointed 10
bye Register, :.... ...i·. ',:. .',
1O-bil ROMAddr~ss Register(prograrn
. counter) .. ' <
.:.,
8-bit. Registerto latch data for~ UpPort
1~bit Subroutine, Save Regis.ter A
10:-.bit SubrOlltine. Saye Register B

.4-bit Operand Field, 0-15 binary (RAM
DigitSelect)
2-bil Operand Field,0-3 binary (RAM
Register Select)
10-bit Operand Field, 0-1023 binary
(ROM Address) .
~~bit Operand Field, 0-15 binary
(Immediate Data)
Contentand~AMlocati?naddreSsedby s
Content and· ROM locaUOna:ddressed by t

10-bitSubro~tine~ayeRegisterC
4-bit~hin RElgister .and Counter
Logi~~Controned <;Iockputp.ut

TABLE 2. WD4200/4210 INSTRUCTION SET TABLE (Nole 1)

Code'

Mac~.II\.•

La119\1age

COde (Binary)

ARITHMETIC INSTRUCTIONS

Add with Garry. Skip on
C%fy •.,.....,.....•....
"LIII" , .IAddAtoRAM

502

MlIChln. Language

Dlt,Flow

Code (Binary)

TRANSFER OF CONTROL INSTRUCTIONS

JID
JMP

111 1 1 11

I!!

010 °la9:!J
a7:0
a6:0

111

(Pages 2, 3 only)
or
11 11 a5:0
a

(all other pages)
a5:0
01

1 0/1 oa9:81

ROM (PC9:8, A, M) .....
PC7:0
a .... PC

None

Jump Indirect (Note 3)

None

Jump

a .... PC6:0

None

Jump within Page
(Note 4)

a .... PC5:0
PC + 1 .... SA ...,. SB ..... SC None
0010 ..... PC9:6
a, .... PC 5:0
PC+l .... SA ..... SB...,. SC None
a "+i.PC

MEMORY REFERENCE INSTRUCTIONS

01 Ol'.'.~lr
011

,Q'7;:4t>,flA!V1(B)
OI?:~;RIT~/ .
·RAM(at ..... A
BR~r""'Br

503

Jump to Subroutine
Page (Note 5)
Jump to Subroutine

Descrlptfon'

STII

x
XAD

r, d

1 111

OlrlO

1 ,1

Store Memory Immediate and Increment Sd

10 0 1 010 0 1 11

XDS

d
I
t.:::...:::J...;;.;...J..:::..;..:..1;..:1-'111

XIS

~:.J..!.....J.!::-!....~o~g

Exchange RAM with A,
Exclusive OR Sr with r

Brel,,-.. Sr
RAM(r,d) <+ A

None

RAM(B) .... ' A
Sc-,l-..Bd
Sr\llr-+ .Br

Bd decre- Exchange RAM with A
ments
and Decrement Bd,
past 0
Exclusive-OR br with r

RAM(B)-A
Bd + 1 -"Bd
Br \11 r -+ Bt

Bd increments
past 15

Exchange A with, RAM
pOinted to directly by r, d

Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r

or
10 0 1 110 0 1

pOI r i d
(any d)
100ni00l
1011 01

100 01100 1
TEST INSTRUCTIONS
SKC

100 1 010000!

SKE

10 0

SKGZ

10 0 ,1 110 0 1

33
33

10 0 1 1 11 0 1 01
10 1 o 011 1 1 11

Input IN inputs to A
(Note 2)

L3:0 -+ A

·SIO, C .... SI(

Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Sr and Bd are explicitly defined)
Bits are numbered Oto N where Osignifies the least significant bit (low-order, right-most bit). Forexample, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Noto 2: The ININ and INIL instructions are not available on the 24-pin WD4210 since this device does not contain the IN inputs.
Noto 3: For additional information on the operation of the XAS, JID, LaiD. INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of page
2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last
word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used
when in pages 2 or 3. JSRP may not jump to the last word in page 2.
Note 6: LSI is a single-byte instruction if d =0, 9, 10, 11, 12, 13, 14, or 15. The machine code forthe lower 4 bits equals the binary view of
the "d" data minus 1, e.g., to load the lower four bits of S (Sd) with the value 9 (10012). the lower 4 bits of the LSI instruction equal S
(10002). To load 0, the lower 4 bits of the LSI instruction should equal 5 (11112).
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in
each bit of EN corresponds with the selection of deselection of a particular function associated with each bit (see Functional Description, EN Register).

The following information is provided to assist the
user in understanding the operation of several
unique instructions and to provide notes useful to
programmers in writing WD4200/4210 programs.

nary counter. (See Functional Description, EN
Register, above), If SIO is selected as a shift register,
an XAS instruction must be performed once every 4
instruction cycles to effect a continuous data
system.

XAS Instruction

JID Instruction

XAS (Exchange A with SIO) exchanges the 4-bit
contents of the accumulator with the 4-bit contents
of the SIO register. The contents of SIO will contain
serial-in/serial-out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output, providing a logic controlled clock if SIO is selected as a
shift register or C .... SK if SIO is selected as a bi-

JID (Jump Indirect) is an indirect addressing
instruction, transferring program control to a new
ROM location pointed to indirectly by A and M. It
loads the lower 8 bits of the ROM address register PC
with the contents of ROM addressed by the 10-bit
word, PC9:B, A, M. PC9 and PC8 are not affected by
this instruction.

505

Note that JID requires two instruction cycles.

INI'L Instruction

SKT Instruction

INIL (Input IL Latches to A) inputs two latches, IL3
and ILa (see figure a ) and CKO into A. The IL3 and
ILa latches are set if a low-going pulse ("1" to "a") has
occurred on the IN3 and INO inputs since the last
INIL instruction, provided the input pulse stays low
for at least two instruction times. Execution of an INIL
inputs IL3 and ILO into A3 and AO respectively, and
resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. If
CKO is mask programmed as a general purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "a" is always placed in A 1 upon the
execution of an INIL. The general purpose inputs
IN3-INO are input to A upon the execution of an ININ
instruction (see table 2, ININ Instruction). INILis useful in recognizing pulses of short duration or pulses
which occur too often to be read conveniently by an
ININ instruction.

The SKT (Skip on Timer) instruction tests the state
of an internal10-bit time-base counter. This counter
divides the instruction cycle clock frequency by
1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the
next program instruction if the latch is not set. If the
latch has been set since the previous test, the next
program instruction is skipped and the latch is reset.
The features associated with this instruction, therefore, allow the WD4200/4210 to generate its own
time-base for real-time processing rather than relying on an external input signal.
For example, using a 2.097 MHz crystal as the timebase to the clock generator, the instruction cycle
clock frequency will be 131 kHz (crystal frequency--;16) and the binary counter output pulse frequency
will be 128 Hz. For time-of-day or similar real-time
processing, the SKT instruction can call a routine
which increments a "seconds" counter every 128
ticks.

LaiD Instruction
LQID (Load Q Indirect) loads the a-bit Q register
with the contents of ROM pointed to by the 10-bit
word PC9' PCa, A, M. LQID can be used for table
look-up or code conversion such as BCD to sevensegment. The LQID instruction "pushes" the stack
(PC + 1 -'> SA -'> SB --> SC) and replaces the
least significant 8 bits of PC as follows: A --> PC7:4,
-->
PC3:0, leaving PC9 and PC8
RAM (B)
unchanged. The ROM data pointed to by the new
address is fetched and loaded into the Q latches.
Next, the stack is "popped" (SC --> SB --> SA-->
PC). restoring the saved value of PC to continue
sequential program execution. Since LQID pushes
SB --> SC, the previous contents of SC are lost.
Also, when LQID pops the stack, the previously
pushed contents of SB are left in SC. The net result is
that the contents of SB are placed in SC (SB -'>
SC). Note that LQID takes two instruction cycle
times to execute.

I nstruction Set Notes
a.

The first word of a WD4200/4210 program
(ROM address 0) must be a CLRA (Clear A)
instruction.

Although skipped instructions are not executed, one instruction cycle time is devoted to
skipping each byte of the skipped instruction.
Thus all program paths take the same number
of cycle times whether instructions are skipped
or executed.

The ROM is organized into 16 pages of 64
words each. The Program Counter is a 10-bit
binary counter, and will count through page
boundaries. If a JP, JSRP, JID, or LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next
page. For example: a JP location in the last
word of a page will jump to a location in the next
page. Also, a LQID or JID located in the last
word of pages 2, 7,11, or 15will access data in
the next group of four pages.

WD4200

OPTION LIST
The WD4200/421 a mask-programmable options are
assigned numbers which correspond with the
WD4200 pins.

INll

Figure 8 INIL HARDWARE IMPLEMENTATION

TABLE 3 is a list of WD4200 options. When specifying
a WD4210 chip, Options 9,10, 19,20, and 29 must all
be set to zero. The options are programmed at the
same time as the ROM pattern to provide the user with
the hardware flexibility to interface to various I/O components using little or no external circuitry.

506

TABLE 3

WD4200 MASK OPTIONS

Option 1 = 0: Ground Pin - no options available
Option
= 0:
= 1:
= 2:
= 3:
=

Option
= 0:
= 1:
= 2:
= 3:
= 4:

Option 15: LO Driver
Same as Option 5

2: CKO Pin
clock generator output to crystal
pin is RAM power supply (VR input)
general purpose input, load device to VCC
multi-COP SYNC input
general purpose input, Hi-Z input
3: CKI Input
crystal input divided by 16
crystal input divided by 8
TTL external clock input divided by 16
TTL external clock input divided by B
single-pin RC controlled oscil1ator

Option 16: SI Input
Same as Option 9
Option
= 0:
= 1:
= 2:

Option 18: SK Driver
Same as Option 17
Option 19: IN!) Input
Same as Option 9

Option 4: RESET Pin
= 0: load devices to VCC
= 1: Hi-Z input
Option
= 0:
= 1:
= 2:
= 3:

17: SO Driver
Standard output (Figure 6A)
Open-Drain output (Figure 6B)
Push-Pul1 output (Figure 6e)

Option 20: IN3 Input
Same as Option 9

5: L7 Driver
Standard output (Figure 6A)
Open-Drain output (Figure 6B)
LED direct drive output (Figure 6D)
TRI-STATE®push-pul1 output (Figure 6E)

Option 21: GO I/O Port
= 0: Standard output (A)
= 1: Open-Drain output (B)
Option 22: G1 I/O Port
Same as Option 21

Option 6: L6 Driver
Same as Option 5

Option 23: G2 I/O Port
Same as Option 21

Option 7: L5 Driver
Same as Option 5

Option 24: G3 I/O Port
Same as Option 21

Option 8: L4 Driver
Same as Option 5

Option 25: 03 Output
= 0: Standard output (A)
= 1: Open-Drain output (B)

Option 9: IN1 Input
= 0: load device to VCC (Figure 6F)
= 1: Hi-Z input

Option 26: 02 Output
Same as Option 25

Option 10: IN2 Input
Same as Option 9
Option 11 = 0: VCC Pin - no options available

Option 27: 01 Output
Same as Option 25

Option 12: L3 Driver
Same as Option 5

Option 28: DO Output
Same as Option 25

Option 13: L2 Driver
Same as Option 5

Option 29: COP Function
= 0: normal operation
= 1: MICROBUS'· option

Option 14: L 1 Driver
Same as Option 5

Option 30: COP Bonding
= 0: WD4200 (28-pin device)
= 1: WD4210 (24-pin device)

TEST MODE (Non-Standard Operation)

The SO output has been configured to provide for
standard test procedures for the customprogrammed WD4200. With SO forced to logic "1",
two test modes are provided, depending upon the
value of SI:

507

a. RAM and Internal Logic Test Mode (SI = 1)
b. ROM Test Mode (SI = 0)
These special test modes should not be employed by
the user; they are intended for manufacturing test
only.

APPLICATION NO.1: WD4200 General Controller

APPLICATION NO.2

The diagram below shows an interconnect diagram
for a WD4200 used as a general controller.
Operation of the system is as follows:

Provides an interconnect diagram for a versatile
application of the WD4200 as a keyboard/display
interface to a microprocessor (/1 Pl. Generally,
operation of the WD4200 in this configuration is as
follows:

The L7-LO outputs are configured as LED
Direct Drive outputs, allowing direct connection to the segments of the display.

The D3-DO outputs are buffered by transistors
to drive the digits of the multiplexed display
and to scan the columns of the 4x4 keyboard
matrix rows.

The IN3-INO inputs are used to input the four
drives of the keyboard matrix. Reading the IN
lines in conjunction with the current value of
the D outputs allows detection, debouncing,
and decoding of anyone of the 16 keyswitches.

CKI is configured as a single-pin oscillator
input allowing system timing to be controlled
by a single pin RC network. CKO is therefore
available for use as a VR RAM power supply
pin. RAM data integrity is thereby assured
when the main power supply is shut down.

SI is selected as the input to a binary counter
input. With SIO used as a binary counter, SO
and SK may be used as general purpose
outputs.

The MICROBUS'· option has been selected.

System timing is provided by an external crystal. The time base forthe real-time (counter and
clock) modes is provided by the internal timebase counter, tested by the SKT instruction.

The SIO register is used as a serial-in/serial-out
shift register. In this configuration, however, SI
is shifted into SIO to be tested as one ofthefour
row lines tied to the keyboard matrix. SO is
used to output display segment data (loaded
into SIO with an XAS instruction) to the cascaded 74C164s (8-bit parallel out serial shift
registers). SK functions as a logic-controlled
clock, sending a SYNC signal to clock serial
data into the 74C164s.

The 16 bits of data shifted into the 74C164s are
buffered through the DS8867s (8-segment LED
drivers) to the 16 segments of the alphanumeric LED displays.

The DO-D1 outputs are decoded by the DS8664
(14-digit decoder/driver) and used to select
one of the 14digits ofthe multiplexed display as
well as to scan the 13 columns of the keyboard
matrix and the strap switch scan line (D14).

The four bidirectional G I/O ports (G3-Go) are
available for use as required by the user's
application.

33V

4-DIGIT
LED DISPLAY

WD4200

'NO
4 GENERAL 1/0

EVENT
COMPUTER
INPUT

\4-+~-"""--II'L---+"+-

IN 1
IN2

~~;SWITCH
MATRIX

'N31-+~-~--.J~-I"+-

2 GENERAL OUTPUTS

Figure 9

WD4200 KEYBOARD/DISPLAY INTERFACE

508

a. keyboard to liP (7-bit ASCII)
b. keyboard to WD4200 buffer to liP (7-bit
ASCII)
c. liP to display
d. display to liP
e. !1P to clock
f. clock to liP
g. liP to timer
h. timer to liP
i. keyboard to display
j. clock to display
k. timer to display

The G1-G lines together with SI are connected to the four rows of the keyboard matrix
and the four strap switch lines to input key or
strap switch data to the WD4200. The strap
switches can be used to select one of several of
the system modes listed below.
The LO-L7 TRI-STATE® bidirectional I/O ports
are connected to the microprocessor data bus
to allow for input or output of data to and from
the microprocessor and the WD4200.
The various operations which can be performed by the system include the following
"handshaking" and WD4200 "stand-alone"
modes:
358MHZ
XTAl

-F"

r
02
0,
0,

TO
MICROBUSu..
CONNECTOR

'NO

'ICC

"
"

06
D7

INTR

w<
cs
<0

SPARE INPUT

'cc

WD4200

'"
'"

(Vee -

PIN 14

GND

PIN 7)

{Vee -

PIN 18
PIN 9)

'NZ

ffESEf

0,
0,

GND -

TO KEI'BOARD {
CONNECTOR

SEE SEGMENT
CONFIGURATION

FOR PINOUTS DL416(4)

~~~~7r~~~~~~~~

°1· D'3
TO KEYBOARD
CONNECTOR

'cc
053664

ALPHANUMERIC DISPLAY
SEGMENT CONFIGURATION
KEYBOARD LAYOUT

, ,

AU Q

, , , '"'
I

~SPAR

p
CF

SEGMENT PIN

" "
"
0' ,
02 "
, ,
19

0
C

G2
H

""
"

, "

, ,

Ol~D==

GJ.GO L;.LO

CI~~~TS~

G).GO 03.00

\.-

________

IK \

~r-'.:':PD:':4j=;;o;;---------'--...,'\CPD:O:=t~'02':L------JVO
~
H

L7_LO SO SK

OUTPUTS

Figure 13A INPUT/OUTPUT TIMING DIAGRAM (CRYSTAL + 16 MODE)

CK'5ULI
I

'PD'~'PDO

Figure 138 SYNCHRONIZATION

Figure 13C

CKO OUTPUT TIMING

Figure 13 TIMING

I~ .575 _I
r620 .....,

WD4200F PLASTIC PACKAGE

WD4200E CERAMIC PACKAGE

Information furnished by Western Digital Corporation is believed to be accurate and reliable. Howe .... er, no responsibility is assumed by
Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western OigitalCorporation reserves the right to change said circuitry at any time witho~t notice.

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

513

GENERAL
INFORMATION

515

WESTERN
DIGITAL
p
o

CORPORATE QUALITY ASSURANCE

It is the policy of Western Digital Corporation that every
employee be committed to quality excellence in producing
products/processes which conform to acceptable requirements.

ware and software designs, certify manufacturing operations
and monitor performance/control conformance to product
specifications.
Primary responsibility for execution of the quality program
rests with functional organizations to design, produce, and
market high quality and high reliability products specified to
our customers.

The total quality program is managed and monitored by the
quality assurance organization. Quality assurance is chartered to review marketing product requirements, qualify hard-

QUALITY ASSURANCE ORGANIZATION

,:"!s..T;~N,, ,!1!i'Tl'~
CHIEF EXECUTIVE

1
CORPORATE
QUALITY
ASSURANCE

I
EVALUATION
ENGINEERING
(SYSTEMS QAl

o New Product Qualification
• Test Qualification
• Software Qualification

"SYSTEMS DESIGN CONTROL"

1,----- MFG

PRODUCT
RELIABILITY

•
•
•
•

lr----- MFG

PRODUCT
ASSURANCE

LSI Rei Qualification
Package Qualification
Burn-in/Stress Requirements
Reli8.bllity Monitor Data

•
•
•
•
•

"LSI DESIGN CONTROL"

Specification/Document ContrOl
Process Monitors
Mil 883 Visuals
100% Outgoing Test Audit
Subsidiary/Offshore QC

MATERIAL
ASSURANCE

•
•
•
•
•
•
•

Material Certification
LSI Burn-in
LSI Package Monitors
Systems Incoming QC
Vendor Quality
Failure Analysis
Calibration Control

"MANUFACTURING ASSURANCE"

517

QUALITY ASSURANCE PROGRAM HIGHLIGHTS

the same specifications as the Newport Beach operation.
All specifications are controlled at Newport Beacl1.

• All process chemicals used in the Mask/Wafer fabrication
operations are monitored by the process control section
of QA.

• All new devices and proposed process changes must
pass a thorough reliability qualification before incorporation into production.

• Document control is an integral part of quality assurance.
All specifications are issued and controlled by this activity.

• The Western Digital HI-REL "K" program is designed to
provide high reliability comparable to the requirements of
MIL-STD-883B, Method 5004-4, Class B.

• All Western Digital devices are 100% tested by manufacturing and, in addition, must pass a 1.0% AQL sample test
performed by QA.
• All devices are tested on either state-of-the-art MOS/LSI
Spartan test systems designed and built by Western Digital or on industry standard test systems such as Megatest
or Fairchild.

OUTGOING QUALITY/RELIABILITY
This brochure should answer questions brought up by various W.D.C. customers throughout the years. In the following
pages we have outlined the quality conformance and qualification tests that all devices must meet prior to delivery to
our customers.

• Receiving inspection maintains a very thorough check of
incoming material and has developed unique "use/stress
tests" (look ahead sample build acceptance) which critical
material must pass before acceptance by Western Digital.

PRODUCT STABILIZATION

• The Quality Assurance Department continuously monitors
the manufacturing operations and issues weekly process
control reports displaying detailed data and trends for the
associated areas.

W.D.C. subjects all products to 100% stabilization bake
and temperature cycling prior to final testing. The adherence
to a single high quality level device, reduces the field maintenance problems frequently found by many customers. Device Designs have built in static protection on all devices.

• The Western Digital Malaysian assembly operation uses

QUALIFICATION AND QUALITY CONFORMANCE INSPECTION
Table I. GROUP A 100% OUTGOING ELECTRICAL AUDIT
Subgroups
Subgroup 1 Subgroup 2 -

AQL

Final Electrical Test @ 25'C
Final Electrical Test @ 70'C

1.0AQL
1.0AQL

Refer to the specific device data sheet specifications for min./max. parameters, definition and limits.

Table II. GROUP 8 REL QUALIFICATION MONITOR
Test

Conditions

Method

LTPD

Subgroup 1
Physical dimensions

2016

Subgroup 2
a. Resistance to solvents

2015

3 devices
(no failures)
I device
(no failures)

b. Internal Visual and Mechanical

2014

c. Bond Strength-Aluminum WireUltrasonic

201t

Test Condition D

Subgroup 3
Solderability

2033

Soldering Temp of 260'C ±10'C. 95%
coverage, void concentration not to exceed 5% of area.

Subgroup 4
a. Lead Fatigue

2004

Test condition B2: 8 oz., #1 direction. 3
bends, 90' each.
Flourocarbon detection 10-3 atm/cc/sec.

1005

HTRB, temperature-125'C, 1,000 hrs.
Final electrical @ 25'C

b. Gross Leak
Subgroup 5
a. Steady State life Test
b. Electrical Parameters

518

Table III.
Test
group 1
Thermal Shock

Method

Conditions

LTPD

1011

Test method B: Liquid to liquid. 125'C
to - 55'C to 125'C, 15 cycles
Test condition B: air to air -55'C to
125'C, 100 cycles
Omit initial conditioning
Fluorocarbon detection 10-3 atm/cc/sec
Final electrical @ 25'C

Test condition B: 5 shock pulses, 6
orientation directions; 1,500 F
Test condition A: 20 HZ-2 KHz; 20G, X,
Y, Z orientation
Test condition E: 30 KG centrifugal
acceleration
Flourocarbon detection 10-3 atm/cc/sec

Temperature cycling

1010

Moisture resistance
Gross Leak
Electrical parameters

1004

group 2
Mechanical shock

2002

Vibration variable frequency

2007

Constant acceleration (Centrifuge)

2001

Gross Leak
Electrical parameters
group 3
Salt atmosphere (Corrosion)
Gross Leak
Visual examination
group 4
High temperature storage
Gross Leak
Electrical parameters

Group C Tests

Final electrical @ 25'C
1009

Test condition A: 24 hrs
Fluorocarbon detection 10-3 atm/cclsec
Per visual criteria of method 1009

1008

Test condition B: 125'C storage, 1,000
hours
Fluorocarbon detection 10-3 atmlcc/sec
Final electrical @ 25'C

Groups A, B, and C sampling plans are based on standard LTPD tables of MIL-M-38510.

519

Product/Process Assurance
... Quality audits and gates are located throughout the manufacturing process in order to assure a stable process and thus,
a quality product to our customers. The following manufacturing/screening/inspection flow diagram identifies the steps as they
relate to the production of Western Digital plastic and ceramic MOS/LSI packages.

STARTING MATERIAL
LID SEAL

RECEIVING INSPECTION

FINAL ASSEMBLY
INSPECTION

DESIGN AND MASK FABRICATION

100% STABILIZATION BAKE
PLASTIC 125°C, 24 HOURS
CERAMIC 150°C, 24 HOURS

MASK INSPECTION
WAFER FABRICATION

100% TEMPERATURE CYCLE
PLASTIC -55"C to +125°C, 10 cycles
CERAMIC -65°C to + 150"C, 10 cycles

WAFER IN·PROCESS AUDITS

DIAGNOSTICS

GROSS LEAK
.65% AQL

WAFER PROBE
WAFER SCRIBE/SAW AND BREAK

FINE LEAK TEST
.65%AOL

INSPECTION

CHIP BOND

SOLDER DIP LEADS

INSPECTION
INSPECTION AUDIT

LEAD INSPECTION

BASE SEAL
CUT AND FORM
WIRE BOND

CUT & FORM INSPECTION

WIRE BOND AUDIT

100% ELECTRICAL TEST

PRECAP INSPECTION

FINAL TEST AUDIT
1.0% AQL
BRAND

INSPECTION AUDIT
LIFE TEST MONITORS
PACKAGE REL MONITORS
FINAL EXTERNAL VISUAL INSPECTION
QUALIFICATIQN AND QUALITY
CONFORMANCE INSPECTION
PACK
SHIPPING AUDIT
SHIP BY CUSTOMER
SPECIFIED CARRIER

520

RELPAK PLASTIC

plastic package body. This allows for a true AuSi Eutectic die
attachment prior to the marriage with the plastic body. This
process design again eliminated the chance for ionic con-

PACKAGE SPECIFICATION

tamination upon the active circuit areas.

FEATURES
.. COST ADVANTAGES OF TOTAL ENCAPSULATED
PACKAGES.
.. RELIABILITY ADVANTAGES OF A CERAMIC PACKAGE.
D

The package structure is such that 95% of the intemal surface area is composed of metal. The possible paths for moisture penetration are confined to the parameters of the cavity,
thereby increasing the mean distance of moisture paths to
its maximum.

SUPERIOR MECHANICAL QUALITIES

.. OUTSTANDING ELECTRICAL CHARACTERISTICS.
.. CONSTRUCTION MATERIALS ELIMINATE SOURCES
OF RUST AND CORROSION.
.. ELIMINATES HOT INTERMITIANT OPEN PROBLEMS.
.. ELIMINATES DEVICE INSTABILITY DUE TO IONIC
CONTAMINATION.
.. MOISTURE PENETRATION DRAMATICALLY REDUCED.

AVAILABILITY
WDC has been supplying satisfied customers for over nine
years with this package. Because this package was developed in-house, we have a completely self-sustained production line with very little dependence on suppliers. The package was developed alongside the ceramic package, which
means eqUipment interchangeability on the assembly line.
This production versatility has enabled WDC customers to
benefit from quick turn around times.
We patented this package in 1973 and, because of its similarities to the ceramic packages, WDC has the unique distinction of possessing the only industry available plastic EProm package. With slight material changes, WDC can assemble 24 lead E-Prom devices in the Standard RELPAK
Packages for customer evaluation and use.

This package is constructed using a proprietary copper lead
frame material, which eliminates sources of rust or corrosion.
Our proprietary molding process allows WDC to mold without
the lead frame bonding surface ever making contact with the
molding material, again eliminating possible sources for ionic
contamination .
We use an Ortho Creasol Novolac Epoxy resin and a Phenolic Novolac curing agent as the base transfer molding compound. Together with our proprietary lead frame material we
have achieved a true chemical mechanical bond during the
molding process. This bond is so strong, we are able to place
a device prior to lid seal upside down on a helium leak detector and pass a 1 x 10-8 std cc/sec open face leak test.
Using standard stress acceleration factors, the projected life
expectancy of the WDC RELPAK Package is well in excess
of 100 years.
The basic RELPAK design employs a "see thru" construction. The lead frames are stamped from 10 mil thick sheets
of copper into strips of four, which are then spot Ni spot Au
plated. The quality levels of the lead frames and molding
powders are rigorously controlled by incoming Q.C. The lead
frames and molding powders are controlled by lot numbers.
Each incoming lot is individually increased by W.D.C. material assurance.
ADVANTAGES OF THE RELPAK
The most obvious is its lower cost compared to its ceramic
counterpart without any reduction in reliability-by retaining
the pre molded cavity package concept, essentially all the
problems of a total encapsulated package are avoided such
as work damage to the bonding wires during the molding
operation, concern for adverse effects from direct contact of
the molding epoxy with the die surface, and the hot intermittent open reliability problem. The use of a solid metal lead
frame coupled with the gold plated Kovar (or Alloy 42) base
to which the die is eutectically attached provide more than
adequate thermal paths for power dissipation, a primary reliability consideration.
Careful adherence to sound engineering design practices
during package development coupled with the use of a metallurgical bond at chip bond and conventional aluminum wire
bonding has resulted in a plastic cavity package which can
be subjected to the same product assurance screening operations as its ceramic counterparts without adversely afiecting the package or device parameters.

RELIABILITY AT LOW COST
Western Digital Corporation's RELPAK Plastic Package is
unique to the industry in that it contains many of the cost
advantages of the industry accepted total encapsulated
package while it also contains many of the reliability advantages of a ceramic package.
CONSTRUCTION DETAILS
The RELPAK is a cavity approach which allows the use of
aluminum wire for cost purposes, while the plastic will never
come in contact with the active circuit and wires. This eliminates the Hot Intermittant Open HIO problems associated
with industry standard plastic packages and also eliminates
device instability due to ionic contamination caused by plastic
being in direct contact with the device.
The die is attached to its metal base separately from the

521

· .. The Western Digital plastic "cavity" package is a unique package offering most of the advantages of ceramic. The quality
assurance and reliability department maintains a thorough inspection program during production of the plastic packages. An
overview of the plastic package (RELPAK) program is illustrated below.

0-0--------

0---

0
0 -

90% ALL METAL CAViTY
DOUBLE LID/DOUBLE BASE

PLASTIC

STARTING MATERIAL

RECEIVING INSPECTION

ALLOY 42 SHieLD
PLASTIC PACKAGE
COPPER LEAD FRAME

MOLDING

I-' in. GOLD PlATED OR 100 I'- In.
EVAPORATED AI PlATED TERMINALS
TIN DIPPED LEADS

MOS/LSI DIE
GOLD SILICON EUTECTIC

KOVAR OR ALLOY 42 BASE

GOLD STRIP PLATED

O.A. QUAL SAMPLES
100% INSPECTION

O.A. FINAL INSPECTION

PlASTIC BASE
STOCK ROOM

522

WESTERN
DIGITAL
p
c

HI-REL "K" TESTING PROGRAM

FEATURES

GENERAL DESCRIPTION

o GENERAL CONFORMANCE TO MIL-STD-8838,

Western Digital's Hi-Rei "K" program is designed
to provide high reliability devices for extended
temperature environments. Individual enhancements
may be selected to meet your particular
environmental needs.

METHOD 5004.4, CLASS 8
• INCLUDES:
PRECAP VISUALS
SEAL INTEGRITY
POWER CONDITIONING
ENHANCEMENT OPTIONS

INITIATE

PACKAGE

PROBED WAFERS

LOT TRAVELER

FINE LEAK
SCRIBEISAW

GROSS LEAK
BREAK/SORT

CUT/FORM LEADS

INSPECT
PRE BURN-IN

ElECTAICALS

CHIPBOND
BURN-IN
160 HRS@ 12S"C

INSPECT

FINAL TEST

WIRE BOND
LID
INSPECT

FINAL TEST
I,O~o AQL

CLEAN/BAKE/SEAL

BRAND

TEMP CYCLE
10 CYCLES
-65'!+15Q°C

MOVE TO
FINISHED GOODS

STABAKE
24 HAS 15QoC
PACK

CONSTANT
ACCELERATION
(OPTIONAL)

SHIP VIA
CUSTOMER
SPECIFIED CARRIER

HI-REL "K" PROGRAM FLOW DIAGRAM

523

MIL-STD-883B
METHOD 5004.4
CLASS B

WD HI-REL UK" TEST PROGRAM

3.1.1 Internal Visual
Method 2010.3
Test condition B

All Hi-Rei "K" devices receive 100%
inspections prior to lid seal. These inspections
together comprise criteria comparable to
Mil-Std-883, method 2010.3, test condition B.

3.1.2 Stabilization Bake
Method 1008.1
Test condition C
24 hours at 150°C

Same

3.1.3 Temperature Cycling
Method 1010.2, Test condition C
-65°C to 150°C for 10 cycles, with 10 minutes dwe",
and 5 minutes maximum transfer time

Same

3.1.4 Constant Acceleration
Method 2001.2, Test condition E. 30,000 G stress
level

Optional

3.1.5 Visual Inspection
Visual inspection for catastrophic failures after screens

3.1.6 Seal

Same

Method 1014.2

(a) Helium fine leak - Test condition A,. Bomb condition 2 hours at 60 psig. Reject limit 5xl0-8 torr
(b) Flourocarbon gross leak - Test condition C

Same
Same

524

MIL-STO-8838
METHOD 5004.4
CLASS 8

WD HI-REL uK" TEST PROGRAM

3.1.9 Interim (pre-burn-in) Electricals

Preburn-in at 25°C. Must meet requirements
of device data sheets.

Per applicable device specification

3.1.10 Burn-in Test

Method 1015.2, 160 hours@125°C

Same

3.1.13 Interim (Post burn-in) Illectricals

Final Test

Per applicable device specification

3.1.15 Final Electrical Test

(a) Static Tests
(1) 25°C
(2) Minimum and Maximum Operating
Temperatures
(b) Dynamic and Switching Tests at 25°C
(c) Functional Tests at 25°C

Same

3.1.17 Qualification or Quality Conformance

To be agreed upon

Inspection and Test Sample Selection

3.1.18 External Visual

Method 2009.2

Same

525

WESTERN DIGITAL RELIABILITY ENHANCEMENT OPTIONS

100% Temperature Testing
Level

-40" to +85"C
-55" to +125"C

Thermal, Shock (Liquid to Liquid)
Level

0" to + 100"C, 15 cycles
-55" to + 125"C
-65" to + 150"C

Extended High Temperance Storage
+ 150"C for 24 hours standard, other time/temperature
storage requirements available as required.

WESTERN DIGITAL
CORPORATION

3128 REDHILL AVENUE, BOX 2180
NEWPORT BEACH, CA 92663 (714) 557-3550,TWX 910-595-1139

526

Abbreviations and acronyms
Reprinted from Data Communications

ND
ACCT

ACF
ACK
ACM
ACU
ADCCP
ADP
AFIPS

ALU
ANSI
APL
Arinc
ARPA

Arpanet
ARQ
ASCII

ASR
ATSU
Autodin
AVD
Basic
Baudot
BCC
BCD
BDLC
BDN
BER
BERT
Bit
BiVs
BLU

Analog/digital
Ad Hoc Committee for
Competitive
Telecommunications
Advanced communications
function
Acknowledgement, positive
Association for Computing
Machinery
Automatic calling unit
Advanced data communications
control procedure
Automatic data processing
American Federation of
Information Processing
Societies
Arithmetic logic unit
American National Standards
Institute
A programming language
Aeronautical Radio Inc. (airlines
network)
Advanced Research Project
Agency (Department of
Defense)
ARPA network (Department of
Defense)
Automatic request for repetition
(IBM)
American standard code for
information interchange
(7 level)
Automatic send/receive
(teleprinters)
Association of Time-Sharing
Users
Automatic digital network
(Department of Defense)
Alternate voice/data
Beginners ali symbolic instruction
code
Teleprinter code (5 level)
Block check character
Binary coded decimal
Burroughs data link control
Beli data network (planned)
Bit error rate
bit-error-rate-test (set)
Binary digit
Bits per second
Basic link unit

BSC
BTAM
BTU
CATV
CAl
CBEMA
CBT
CBX
CCB
CCDN
CCF
CCIA
CCIS
CCITT

CCL
CCT
CCU
CDCCP

CDF
CEPT

CICS
CMOS
CPH
CPODA
CPU
Coax
Cobol
COM
Comsat
CPOL
CR
CRC
CRT

527

Binary synchronous
communications
Basic telecommunications access
method (IBM)
Basic transmission unit
Community antenna television
Computer assisted instruction
Computer Business Equipment
Manufacturers Association
Computer-based terminal
Computerized private branch
exchange
Common Carrier Bureau
Corporate consolidated data
network (IBM)
Communications control field
Computer and Communications
Industry Association
Common channel interoffice
system (AT&T)
International Consultative
Committee for Telegraphy and
Telephony
Communications control language
Coupler cut through
Communications control unit
Control Data communications
control procedure (Control Data
Corp.)
Communications-data field
Conference of European Postal
and Telecommunications
Administrations
Customer information control
system
Complementary metal oxide
semiconductor
Characters per hour
Contention priority-oriented
demand assignment (protocol)
Central processing unit
Coaxial cable
Common business·oriented
language
Computer output microfilm
Communications Satellite Corp.
Communications procedure·
oriented language
Carriage return
Cyclic redundancy checking
Cathode ray tube

CTAK
CTS
Cybernet
DA
DAA
DAL
DAP
Darpa
DASD
Dataset
Datelll

dB,db
DBMS
DBS
DCE
DCF
DCS
DDCMP

DDP
DDS
Decnet
DES
DLC
DLCF
DMA
DMEP

DNA
Domsat
DOS
DRS
DSC
DSDS
DSE
DSU
DTE
DTS
EBCDIC
ECOS

EDP
EFT

Cipher text auto key
Communications Technology
Satellite or clear to send
Control Data Corp. network
Data available
Data access arrangement
(AT&T)
Data access line
Data access protocol
Defense Advanced Research
Project Agency (See ARPA)
Direct access storage device
Synonym for modem
(see modem)
RCA Global Communications data
service in conjunction with
Telenet
Decibel
Database management system
Database service (WUI)
Data circuit-terminating equipment
Distributive computing facility
(Bank of America)
Distributed computing system
Digital Data communications
message protocol (Digital Data
Corp.)
Distributed data processing
Dataphone digital service
(AT&T)
Digital Equipment Corp. network
Data encryption standard
Data link control
Data link control field
Direct memory access
Data-network modified emulator
program (Cambridge
Telecommunications Inc.)
Digital network architecture
(Digital Equipment Corp.)
Domestic satellite service
Disk operating system
Data rate selector
Direct satellite communications
Dataphone switched digital
service (AT&T)
Distributed system environment
Data service unit
Data terminal eqUipment
Digital tandem switch
Extended binary coded decimal
interchange code (8 level)
Extended communications
operating system
(Harris Corp.)
Electronic data processing
Electronic funds transfer

EIA
EIES

EOA
EOM
EOT
EPROM
ESS
FAX
FCC
FDX
FDM
FEC
FED-STD
-1001

-1003
-1005
-1010
-1011
-1012
-1013

-1020

-1030

FF
FHD
FIPS
FIGS
FMTP
FOC
Fortran
Fox message
FSK
FX
GPO
HASP

528

Electronic Industries Association
Electronic Information Exchange
System (New Jersey Institute of
Technology)
End of address
End of message
End of text or end of transmission
Erasable programmable read only
memory
Electronic switch system
Facsimile
Federal Communications
Commission
Full-duplex transmission
Frequency-division multiplexer
Forward error correction
Federal standard
High-speed synchronous signaling
rates between data terminal
equipment and data circuitterminating equipment
Bit-oriented data link control
procedures
2.4 kbitls modems
ASCII bit sequencing for serial-bybit transmission
Character structure for serial-bybit ASCII transmission
Character structure for parallel-bybn ASCII transmission
Data terminal equipment to data
circuit-terminating equipment
synchronous signaling rates
using 4 Hz circuits
Electrical characteristics of
unbalanced voltage digital
interface circuits
Electrical characteristics of
balanced voltage digital
interface circuits
Form feed
Fixed-head disk
Federal Information Processing
Standards
Figures shift (teleprinters)
File management transaction
processor (Bank of America)
Fiber optics communications
Formula translation
Test message (The quick brown
fox jumped over the lazy dog)
Frequency-shift keying
Foreign exchange
General purpose discipline (first
IBM data link control)
Houston automatic spooli ng
priority

HDLC
HDX
HiD/LoD
HN
Hz
IBMTSS
ICA
ICST
IDCMA

IEEE
IFIPS

IMP
IMS
Infonet
Intelsat
I/O
IPL
IPN
IRe
IS
IS-646-1973

IS 1155-1973

IS 1177-1973

IS 1745-1975

IS 2110-1972

IS 2111-1972

IS 2593-1973

IS 2628-1973

High-level data link control
Half-duplex transmission
High-density/low-density tariff
Host to network
Hertz (cycles per second)
Timesharing system
(IBM network)
International Communications
Association
Institute for Computer Science
and Technology
Independent Data
Communications Manufacturers
Association
Institute of Electrical and
Electronic Engineers
International Federation of
Information Processing
Societies
Interface message processor
Information management system
(IBM)
Computer Science Corp. network
International satellite service
Input/output
Initial program load
Instant private network
International record carrier
International standard
Bit-coded character set for
information processing
interchange
Information processing-use of
longitudinal parity to detect
errors in information messages
(included in V.4 and X.4)
Information processing-character
structure for starfistop and
synchronous transmission
(included in V.4 and X.4)
Information processing-basic
mode control procedures for
data communications systems
Data communication-data
terminal and data
communication equipmentinterchange circuits.
Assignment of connector pin
numbers (being revised-DIS
2110 is being balloted)
Data communication-basic
mode control procedures-code
independent information trasfer
Connector pin allocations for use
with high-speed data terminal
equipment
Basic mode control procedures-

IS 2629-1973

IS 3309-1976

IS 4335-1977

ISO
IT
ITOM
ITS
ITU
JCL
KAK
KAU
KDS
KSR
LED
LF
LDM
LlU
LIM
LO
LRC
LSD
LSI
LTRS
Mark III
MD
MDS
Merit
MHD
MHP
MICR
MIU
MNCS
Modem
MOS
MPCC
MPL
MSI
MT
MTBF
MTS
MTIR

529

complements
Basic mode control proceduresconversational information
message transfer
Data communications-high-Ievel
data link control proceduresframe structure
Data communications-high-Ievel
data link control procedureselements of procedures
(independent numbering)
International Standards
Organization
Intelligent terminal
Intelligent time-division multiplexer
Invitation to send
International Telecommunications
Union
Job control language
Key-auto-key
Keystation adapter unit
Keyboard display station
Keyboard send/receive
Light-emitting diode
Line feed
Limited-distance modem
Line interface unit
Line interface module
Line occupancy
Longitudinal redundancy check
Line-sharing device or line signal
detector
Large-scale integrated (circuit)
Letters shift (teletypewriters)
General Electric Co. Information
Services network
Multiple dissemination
Multiple dataset system
Michigan network among three
largest universities
Moving-head disk
Message-handling processor
(Bank of America)
Magnetic ink character recognition
Multistation interface unit
Multipoint network-control system
Modulator-demodulator
Metal oxide semiconductor
Multiprotocol communications
controller
Multischedule private line
Medium-scale integrated (circuit)
Measured time
Mean time between failures
Message telecommunications
service (AT&T)
Mean time to repair

MUX

MVS
NAK
NAM
Naruc

NBS
NC
NCP
NCR-DNA
NCS
NOT
NMC
NRZ
NSP
NTPF
NYPSC
OCR
Octopus
OS
OSWS
PABX
PAD
PAM
PBX
PCM
PFEP
PIU
PU1
PMS
PMX
PSC
PSE
PROM
PRTM
PIT
PUC
QAM
QTAM
RAD
RAM
RCAC
RCD
ROC
RLSD
RJE

Multiplexer
Multiple virtual storage
Negative acknowledgement
Network access method (Control
Data Corp.)
National Association of
Regulatory Utility
Commissioners (state agencies)
National Bureau of Standards
Network connect
Network control program (IBM)
NCR Corp.-distributed network
architecture
National communications system
(Department of Defense)
Net data throughput
Network management center
Non-return to zero (waveform)
Network services protocol (Digital
Equipment Corp.)
Number of terminals per failure
New York Public Service
Commission
Optical character recognition
Control Data Corp. network
Operating system
Operating system workstation
Private automatic branch
exchange
Packet assembler/disassembler
Pulse amplitude modulation
Private branch exchange
Pulse-code modulation
Programmable front-end
processor
Path information unit
Programming language one (IBM)
Public message service (WU)
Packet multiplexer
Public Service Commission
Packet-switching exchange
Programmable read only memory
Printing response-time monitor
Postal Telegraph and Telephone
agencies (Europe)
Public Utilities Commission
Quadrature amplitude modulation
Queued telecommunications
access method (IBM)
Random access device
Random access memory
Remote computer access
communications service
Receiver-carrier detector
Remote data concentrator
Received line signal detector
Remote job entry

RMS
RO
ROM
ROTR
RPC
RPG
RPQ
RS
RS-232-C

RS-269-B

RS-334

RS-357

RS-363

RS-366

RS-404

RS-410

RS-422

RS-423

530

Root mean square
Receive only
Read only memory
Receive-only typing reperforation
Registered protective circuit
Report program generator
Request for price quotation
Recommended standard (EIA)
Interface between data terminal
equipment and data
communication equipment
employing serial binary data
interchange (August 1969)
Synchronous signaling rates for
data transmission (January
1976; identical to
ANS IX3.1-1976)
Signal quality at interface
between data processing
terminal equipment and
synchronous data
communication equipment for
serial data transmission (Also
adopted as ANSI X3.24-1967;
new revision being balloted)
Interface between facsimile
terminal equipment and voice
frequency data communication
terminal eqUipment (June 1968)
Standard for specifying signal
quality for transmitting and
receiving data processing
terminal equipment using serial
data transmission at the
interface with non-synchronous
data communication equipment
(May 1969)
Interface between data terminal
equipment and automatic
calling equipment for data
communication (August 1969)
Standard for start/stop signal
quality between data terminal
eqUipment and nonsynchronous data
communication eqUipment
(March 1973)
Standard for electrical
characteristics of Class A
closure interchange circuits
(April 1974)
Electrical characteristics of
balanced voltage digital
interface circuits (April 1975)
Electrical characteristics of
unbalanced voltage digital
interface circuits (April 1975)

RTS
RU
SCC

SCPC
SDLC
SID
SIMP
SMRT
SNA
SNAP
SNR
SOH
SaM
SP
Spool
SaD
STR
STX
SU
SVD
Swift

Sysgen
TAC
TC
TCAM
TCU
TDM
TDMA
Telex
TIMS

TIP
TMS
TMU
TNS
TSO
TTL

TTY
TUCC
TWX
Tymnet

Request to send
Request/response unit
Satellite communications
controller or specialized
common carrier
Single channel per carrier
Synchronous data link control
(IBM)
Swift (see below) interface device
Satellite information message
protocol
Single message rate timing
Systems network architecture
(IBM)
Standard network access protocol
Signal/noise ratio
Start of header
Start of message
Space character
Simultaneous peripheral operation
on line (now an accepted term)
Signal quality detector
Synchronous transmit/receive
(4 level code, IBM)
Start of text
Signaling unit
Simultaneous voice/data
Society for Worldwide Interbank
Financial Telecommunications
(banking network)
~m generation
enet access controller (Telenet
Corp.)
Terminal controller
Telecommunications access
method
Transmission control unit
Time-division multiplexer
Time-division multiple access
Teleprinter exchange service
(WU)
Transmission impairment
measuring set
(Hewlett-Packard)
Terminal interface package
Telecommunications message
switcher
Transmission message unit
Transaction network service
(AT&T)
Timesharing option
Transistor-to-transistor logic
Teletypewriter
Triangle University Computing
Center
Teletypewriter exchange service
Timeshare Inc. network

UART
USASCII

USITA
V.
V.l

V.2

V.3
V.4

V.l0 (X.26)

V.ll (X.27)

V.15
V.19

V.20

V.2l

V.22

V.22bis

V.23

531

Universal asynchronous receiver/
transmitter
United States of America
standard code for information
interchange (identical to ASCII)
United States Independent
Telephone Association
CCITT code designation
Equivalence between notation
symbols and the significant
conditions of a two-condition
code
Power levels for data
transmission over telephone
lines
International alphabet No.5
General structure of signals of
international alphabet No. 5
code for data transmission over
public telephone network
Electrical characteristics for
unbalanced double-current
interchange circuits for general
lise with integrated circuit
equipment in the field of data
cornmunications (and
provisional amendments, May
1977)
Electrical characteristics for
balanced double-current
interchange circuits for general
use with integrated circuit
equipment in the field of data
communications (and
provisional amendments, May
1977)
Use of acoustic coupling for data
transmission
Modems for parallel data
transmission using telephone
signaling frequencies
Parallel data transmission
modems standardized for
universal use in the general
switched telephone network
200-bit/s modem standardized for
use in the general switched
telephone network
Standardization of data signaling
rates for synchronous data
transmission in the general
switched telephone network
Standardization of data signaling
rates for synchronous data
transmission on leased
telephone-type circuits
600/1 .2K bit/s modem

V.24

V.25

V.26

V.26bis

V.27
V.27bis

V.27ter

V.28

V.29
V.31

V.35

V.36

V.41
V.54

VAG
VAN
VIP
VM
V+TU
VS
VSPG

standardized for use in the
general switched telephone
network
List of definitions for interchange
circuits between data terminal
equipment and data circuit
terminating equipment (and
provisional amendments, May
1977)
Automatic calling and/or
answering equipment on the
general switched telephone
network, including disabling of
echo suppressors on manually
established calls
2.4K!1.2K bitis modem
standardized for use on fourwire leased circuits
2.4K!1.2K bit/s modem
standardized for use in the
general switched telephone
network
4.8 kbitJs modem standardized for
use on leased circuits
4.8 kbitJs modem with automatic
equalizer standardized for use
on the leased circuits
4.8K!2.4K bit/s modem
standardized for use in the
general switched telephone
network
Electrical characteristics for
unbalanced double-current
interchange circuits
9.6 kbit/s modem for use on
leased circuits
Electrical characteristics for
single-current interchange
circuits controlled by contact
closure
Data transmission at 48 kbit/s
using 60-to-l08 kHz group-bitis
circuits
Modems for synchronous data
transmission using 60-to-l08
kHz group-bit/s circuits
Code independent control system
Loop test devices for modems
(and provisional amendments,
May 1977)
Value added carrier
Value added network
Visual information projection
Virtual memory
Voice plus teleprinter unit
Virtual storage
Visual storage personal

VTAM
WATS
WPM
WRU
WUI
X-off
X-on
X.
X.1
X.2
X.3

X.4

X.20

X.20bis (V.21)

X.21

X.21bis

X.24

X.25

532

computing (IBM)
Virtual telecommunications
access method (IBM)
Wide area telecommunications
service (AT&T)
Words per minute
Who-are-you? character
Western Union International
Transmitter off
Transmitter on
GCITI recommendation
designation
International user classes of
service in public data networks
International user facilities in
public data networks
Packet assembly/disassembly
facility (PAD) in a public data
network
General structure of signals of
international alphabet No. 5
code for data transmission over
public data networks
Interface between data terminal
equipment and data circuitterminating equipment for start/
stop transmission services on
public data networks
Compatible interface between
data terminal equipment and
data circun-terminating
equipment for start/stop
transmission services on public
data networks
General purpose interface
between data terminal
equipment and data circuitterminating equipment for
synchronous operation on
public data networks
Use on public data networks of
data terminal equipment which
is designed for interfaCing to
synchronous
V-series modems
List of definitions of interchange
circuits between data terminal
equipment and data circuitterminating equipment on public
data networks
Interface between data terminal
equipment and data circuitterminating equipment for
terminals operating in the
packet mode on public data
networks (and provisional
amendment, April 1977)

X.26

X.27

V.28

X.29

X.30

X.3l

X.32

X.33

Electrical characteristics for
unbalanced double-current
interchange circuits for general
use with integrated circuit
equipment in the field of data
communications (identical to
V.l0)
Electrical characteristics for
balanced double-current
interchange circuits for general
use with integrated circuit
equipment in the field of data
communications (identical to
V.ll)
DTE!DCE interface for start/stop
mode data terminal equipment
accessing the packet assembly!
disassembly facility (PAD) on a
public network situated in the
same country
Procedures for exchange of
control information and user
data between a packet-mode
DTE and a packet assembly!
disassembly facility (PAD)
Standardization of basic model
page-printing machine in
accordance with international
alphabet No.5
Characteristics, from the
transmission point of view, at
the interchange pOint between
data terminal equipment and
data cirCUit-terminating
equipment in a 200 bit's start/
stop data terminal
Answer-back units for 200 bit's
start/stop machines in
accordance with international
alphabet No.5
Standardization of an international
text for the measurement of the
margin of start/stop machines in

533

X.92

X.95
X.96
X3.l-l976
X3.l5-l976

X3.l6-l976

X3.25-l976

X3.28-l976

X3.36-l977

X3.44-l977
X3.57-l977

XTC

accordance with international
alphabet No.5
Hypothetical reference
connections for public
synchronous data networks
Network parameters in public data
networks
Call progress signals in public
data networks
Synchronous signaling rates for
data transmission
Bit sequencing of the American
national standard code for
information interchange in
serial-by-bit transmission
Character structure and character
parity sense for serial-by-bit
data communication in the
American national standard
code for information
interchange
Character structure and character
parity sense for parallel-by-bit
communication in the American
national standard code for
information interchange
Procedures for the use of
communication control
characters of American national
standard code for information
interchange in specified data
communications links
Synchronous high-speed data
signali ng rates between data
terminal equipment and data
communication equipment
Determination of the performance
of data communication systems
Message heading formats for
information interchange using
ASCII for data communication
system control
External transmit clock

PACKAGE DESCRIPTION

"J" CERAMIC PACKAGE---16 LEADS

MAX.---j

L.1~1~2~1

MAX

10015

.-t
O"O~'t
MAX.

L ~ ~;~

0 110

_
1

0050~

MAX.

~ -II:- ..J LQQ2Q
o 02'-J

r l
0300

\-------_ 0 9;>0

"K" PLASTIC PACKAGE-16 LEADS

!~:~5

~-II:- ..J
0021--1 L0035

0055

Loo90
0110

0125

0320

MAX 1

~~;~~~

MIN

"L" CERAMIC PACKAGE-18 LEADS

"M" PLASTIC PACKAGE-18 LEADS

"U" CERAMIC PACKAGE-20 LEADS

"V" PLASTIC PACKAGE-20 LEADS

"E" CERAMIC PACKAGE-28 LEADS

"F" PLASTIC PACKAGE-28 LEADS

"A" CERAMIC PACKAGE-40 LEADS

"8" PLASTIC PACKAGE-40 LEADS

534

TERMS AND CONDITIONS
1. ACCEPTANCE: Unless otherwise provided, it is agreed that sales are made on the terms, conditions and war·
ranties contained herein and that to the extent of any conflict, the same take precedence over any terms or
conditions which may apper on Buyer's order form. Seller shall not be bound by Buyer's terms and conditions
unless expressly agreed to in writing. In the absence of written acceptance of these terms, acceptance of or
payment for any of the articles covered hereby shall constitute an acceptance of these terms and conditions.
2. F.O.B. POINT: All sales are made F.O.S. point of shipment. Seller's title passes to Buyer and Seller's liability
as to delivery ceases upon making delivery of articles purchased hereunder to carrier at shipping point in
good condition; the carrier acting as Buyer's agent. All claims for damages must be filed with the carrier. Unless specific instructions from Buyer specify which method of shipment is to be used, the Seller will exercise
his own discretion.
3. DELIVERY: Shipping dates are approximate only. Seller shall not be liable for any loss or expense (conse'
quential or otherwise) incurred by Buyer if Seller fails to meet the specified delivery schedule because of un·
avoidable production or other delays. Seller may deliver the articles in installments, Seller shall not be liable
for any delay in delivery or for non-delivery, in whole or in part, caused by the occurrence of any contingency
beyond the control either of Seller or Seller's suppliers, including, by way of illustration but not limitation,
war (whether an actual declaration thereof is made or not), sabotage, insurrection, riot or other act of civil
disobedience, act of a public enemy, failure or delay in transportation, act of any government or any agency
or subdivision thereof, judicial action, labor dispute, accident, fire, explosion, flood, storm or other act of
God, shortage of labor, fuel, raw material or machinery or technical failure where Seller has exercised ordi·
nary care in the prevention thereof. If any contingency occurs, Seller may allocate production and deliveries
among Seller's customers.
4. TERMS AND METHODS OF PAYMENT' Where Seller has extended credit to Buyer, terms of payment shall be
net thirty (30) days from date of invoice. The amount of credit or terms of payment may be changed or credit
withdrawn by Seller at any time. If the articles are delivered in installments, Buyer shall pay for each install·
ment in accordance with the terms hereof. Payment shall be made for the articles without regard to whether
Buyer has made or may make any inspection of the articles. If shipments are delayed by Buyer, payments are
due from the date when Seller is prepared to make shipments. Articles held for Buyer are at Buyer's sale risk
and expense.
5. TAXES: All prices are exclusive of all federal, state and local excise, sales, use, and similar taxes. Such
taxes; when applicable to this sale or to the articles sold, will appear as separate additional items on the invoice unless Seller receives a properly executed exemption certificate from Buyer prior to shipment.
6. PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from infringement
of patents or trademarks ariSing from compliance with Buyer's designs or specifications or instructions. The
sale of products by the Seller does not convey any license, by implication, estoppel, or otherwise, under pat·
ent claims covering combinations of said products with other devices or elements. Except as otherwise pro·
vided in the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer so
far as based on a claim that any product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States, if notified promptly in writing and given authority, information
and assistance (at the Seller's expense) for the defense of same, and the Seller shall pay all damages and
costs awarded therein against the Buyer. In case said product, or any part thereof, is in such suit held to constitute infringement and the use of said product or part is enjoined, the Seller, shall at its own expense, either
procure for the Buyer the right to continue using said product or part, or replace same with non·infringing
product, or modify it so it becomes non·infringing, or remove said product and refund the purchase price and
the transportation and installation costs thereof. The foregoing states the entire liability of the Seller for pat·
ent infringement by the said products of any part thereof.
7. ASSIGNMENT: The Buyer shall not assign his order or any interest therein or any rights thereunder without
the prior written consent of Seller.
8. WARRANTY: Seller warrants articles of its manufacture against defective materials or workmanship for a
period of one year from date on which Seller delivers said articles. the liability of Seller under this warranty is
limited at Seller's option, solely to repair, replacement with equivalent articles, or an appropriate credit
adjustment not to exceed the original sales price of articles returned to the Seller provided that (a) Seller is
promptly notified in writing by Buyer upon discovery of defects, (b) the defective article is returned to Seller,
transportation charges prepaid by Buyer, and (c) Seller's examination of such article disclosed to its
satisfaction that defects were not caused by negligence, misuse, improper installtion, accident, or
unauthorized repair or alteration by the Buyer. In the case of equipment articles, this warranty does not include mechanical parts failing from normal usage nor does it cover limited life electrical components which
deteriorate with age. In the case of accessories, not manufactured by Seller, but which are furniShed with the
Seller's eqUipment, Seller'S liability is limtied to whatever warranty is extended by the manufacturers thereof
and transferable to the Buyer. This Warranty is expressed in lieu of all other Warranties, expressed or im·
plied, including the implied Warranty of fitness for a particular purpose, and of all other obligations or
liabilities on the Seller's part, and it neither assumes nor authorizes any other person to assume for the
Seller any other liabilities. This Warranty should not be confused with or construed to imply free preventative
or remedial maintenance, calibration or other service required for normal operation of the equipment ar·
ticles. These Warranty provisions do not extend the original Warranty period of any article which has either
been repaired or replaced by Seller. In no event will Seller be liable for any incidental or consequential
damages.
9. TERMINATION: Buyer may terminate this contract in whole or from time to time in part upon 60 days written
notice to Seller. In such event Buyer shall be liable for termination charges which shall include a price adjust·
ment based on the quantity of articles actually delivered, and all costs, direct and indirect, incurred and com·
mitted for this contract together with a reasonable allowance for pro'rated expenses and profits. Any termination or back off in scheduling will not be allowed on shipments scheduled for the month in which the request is made and for the month following.
10. GOVERNMENT CONTRACTS: If the articles to be furnished under this contract are to be used in the performance of a Government contract or subcontract and a Government contract number shall appear on Buyer's
purchase order, those clauses of the applicable Government procurement regulatin which are mandatorily
required by Federal Statute to be included in Government subcontracts shall be incorporated herein by
reference.
11. ORIGIN OF ARTICLES: Seller engages in off· shore production, assembly andlor processing and makes no
warranty or representation, expressed or implied, that the articles delivered hereunder are United States ar·
ticles or of U.S. origin for the purpose of any statute, law, rule, regulation or case thereunder. If Buyer ships
the articles hereunder out of the U.S. for assembly, then at Buyer's request in writing, Seller shall provide in·
formation applicable to identification of any articles not of U.S. origin.

535

WESTERN DIGITAL
SALE REPRESENTATIVES & DISTRIBUTORS
DOMESTIC. FOREIGN

STATE
ALABAMA

COMPANY

ADDRESS

PHONE

AREA MGR

MURCOTA CORP.

904 BOB WALLACE AVE.
SW HUNTSVILLE, AL 35801

(205) 539-8476

BOB GREEN

DIPLOMAT (FL)

2120 CALUMET ST.
CLEARWATER, FL 33515

(813) 443-4514

BOB GREEN

KIERULFF

3247 TECH DRIVE,
ST. PETERSBURG, FL 32337

(813) 576-1966

BOB GREEN

RM ELECTRONICS

4702 GOVERNORS DR.
HUNTSVILLE, AL 35805

(205) 852-1550

BOB GREEN

DAR-C INC.

14425 N. SCOTTSDALE #500
SCOTTSDALE, Al 85254

(602) 948-2240

JOE MADER

KIERULFF

4134 E. WOOD ST.
PHOENIX, Al 85040

(602) 243-4104

JOE MADER

ARKANSAS

WEST & ASSOC.

4300 ALPHA RD. #106
DALLAS, TX 75234

(214) 661-9400

LEN STRONG

CALIFORNIA

EL REPCO

349 1ST ST.
LOS ALTOS, CA 94022

(415) 941-4990

E. liTTLE

ANTHEM ELECTRONICS

174 COMPONENT DR.
SAN JOSE, CA 95131

(408) 946-8000

E. ZITTL£

BELL INDUSTRIES

1161 N. FAIROAKS AVE.
SUNNYVALE, CA 94086

(40B) 734-8570

E. ZITTLE

DIPLOMAT

1283F MT. VIEW
SUNNYVALE, CA 94086

(408) 734-1900

E. ZITTLE

KIERULFF

3969 E. BAYSHORE RD.
PALO ALTO, CA 94303

(415) 968-6292

E. ZITTLE

TIME ELECTRONIC
NOR CAL

1339 MOFFETT PARK DR.
SUNNYVALE, CA 94086

(408) 734-9888
(800) 672-1422

E. ZITTLE

BESTRONICS INC.

5000 OVERLAND AVE. #11
CULVER CITY, CA 90230

(213) 870-9191

JOE MADER

BESTRONICS INC.

10150 SORRENTO VALLEY RD.
#300
SAN DIEGO, CA 92121

(714) 452-5550

JOE MADER

BESTRONICS INC.

180/1 SKY PARK CIA. #L
TUSTIN, CA 92714

(714) 979-9910

JOE MADER

IMAGE ELECTRONIC

15052 REDHILL AVE, #C
IRVINE, CA 92680

(714) 730-0303

JOE MADER

KIERULFF

2585 COMMERCE WAY
LOS ANGELES, CA 90040

(213) 725-0325

JOEMAD£R

KIERULFF

8797 BALBOA AVE.
SAN DIEGO, CA 92123

(714) 278-2112

JOE MADER

KIERULFF

14101 FRANKUN AVE.
TUSTIN, CA 92680

(714) 731-5711

JOE MADER

ANTHEM ELECTRONICS

2661 DOW ST.
TUSTIN, CA 92680

(714) 730-8000

JOE MADER

ANTHEM ELECTRONICS

4125 SORRENTO VALLEY RD.
SAN DIEGO, CA 92121

(714) 279-5200

JOE MADER

ARIZONA

REPRESENTATIVE

DISTRIBUTOR

536

STATE
COLORADO

CONNECTICUT

DELAWARE

FLORIDA

GEORGIA

IDAHO

COMPANY

ADDRESS

PHONE

AREA MGR

COMPONENT SALES

5925 E. EVANS AVE. #204B
DENVER, CO 80222

(303) 759-1666

E. ZITILE

BELL INDUSTRIES

8155 W. 48TH AVE.
WHEATRIDGE, CO 80033

(303) 424-1985

E ZITTLE

DIPLOMAT

7100 BROADWAY BLDG. 6
DENVER, CO 80221

(303) 427-5544

E. ZITTLE

KIERULFF ELECT.

10890 E 47TH AVE
DENVER, CO 80239

(303) 371-6500

E. ZITTLE

COMPo REP. ASSOC.

605 WASHINGTON AVE.
N. HAVEN, CT 06473

(203) 239-9762

BOB GREEN

KIERULFF ELECT.

13 FORTUNE DR.
BILLERICA, MA 01821

(617)667-8331

BOB GREEN

TIME NEW ENG.

400 NEW BOSTON PARK
WOBURN, MA 08101

(617) 935-8080

BOB GREEN

BOND ELECTRONIC

20 FITCH ST.
E. NORWALK, CT 06855

(203) 852-1001

BOB GREEN

NEW ERA SALES

7310 RITCHIE HWY #407,
EMPIRE TOWERS
GLEN BURNIE, MD 21061

(301) 768-6666

BOB GREEN

KIERULFF ELECT.

#3 EDISON PLACE
FAIRFIELD, NJ 07006

(201) 575-6750

BOB GREEN

TIME-MID ATL

359 E. MADISON AVE.
CUFTON HTS. PA 19018

(215) 622-2500

BOB GREEN

DYNE-A-MARK

1001 N.W. 62ND ST. #107
FT. LAUDERDALE, FL 33309

(305) 771-6501
(305) 994-5031

BOB GREEN

DYNE-A-MARK

405 SOUTH AURORA
CLEARWATER, FL 33309 BOX 6117

(813) 441-4702

BOB GREEN

DYNE-A-MARK

303 E. SEMORAN BLVD. 314
ALTAMONTE SPGS. FL 32701
BOX 33 MALTLAND, FL 32751

(305) 725-4520

BOB GREEN

DIPLOMAT (FL)

50 WOODLAKE DR. W#3-A
PALM BAY, FL 32905

(305) 725-4520

BOB GREEN

DIPLOMAT (FL)

800 N. W. 62ND ST.
FT. LAUDERDALE, FL 33309

(305) 771-0440

BOB GREEN

DIPLOMAT

2120 CALUMET ST.
CLEARWATER, FL 33515

(813) 443-4514

BOB GREEN

KIERULFF ELECT.

3247 TECH. DRIVE
ST. PETERSBURG, FL 32337

(813) 576-1966

BOB GREEN

TIME ELECT.

6610 N. W. 21ST ST.
FT. LAUDERDALE, FL 33309

(305) 974-4800

BOB GREEN

MURCOTA CORP.

1106 BURKE ST.
WINSTON SALEM, NC 27101

(919) 722-9445

BOB GREEN

DIPLOMAT ELECT.

2120 CALUMET ST.
CLEARWATER, FL 33515

(813) 443-4514

BOB GREEN

KIERULFF ELECT.

3247 TECH. DRIVE
ST. PETERSBURG, FL 32337

(813) 576-1966

BOB GREEN

COMPONENTS WEST

451 s.w. 10TH #109
RENTON & TUKWILA, WA 9B1BB

(206) 271-5252

E. ZITILE

KIERULFF ELECT.

3695 W. 1987 S.
SALT LAKE CITY, UT 84104

(801) 973-6913

E. ZITTLE

537

STATE
ILLINOIS

COMPANY

ADDRESS

PHONE

AREA MGR
LEN STRONG

JANUS INC.

3166 DES PLAINES
DES PLAINES, IL 60018

(312) 298·9330

NEVCO

1715 BALTIMORE AVE.
KANSAS CITY, MO 64108

(816) 421·1751

LEN STRONG

BELLINO.

3422 W. TOUHY AVE,
CHICAGO, IL 80845

(312)982·9210

LEN STRONG

DIPLOMAT (IL)

1011 JUDSON ST.
BENSEVILLE, IL 80106

(312) 595·1000

LEN STRONG

KIERULFF ELECT,

1536 LANDMEIER
ELK GROVE VLG. IL 60007

(312) 640·0200

LEN STRONG

RM ELECTRONICS

265 S EISENHOWER LN.

(312) 932·5150

LEN STRONG

LOMBARD IL 60148

EMA

35 COMPARK RD. BOX 449
CENTERVILLE, OH 45459

(513) 433·2800

LEN STRONG

RM ELECTRONICS

5545 W. RAYMOND '11K
INDIANAPOLIS, IN 46241

(317) 247·9701

LEN STRONG

DIPLOMAT (IL)

1071 JUDSON ST,
BENSENVILLE, IL 60106

(312)595·1000

LEN STRONG

NEVCO

730 34TH ST PLACE
W. DES MOINES, IA 50265

(515) 225·9866

LEN STRONG

DEECOING.

2500 S.w. 16TH AVE.
CEDAR RAPIDS, IA 52406

(319) 525·1332

LEN STRONG

DIPLOMAT (MN)

3818 CHANDLER DR.
MINNEAPOLIS, MN 55421

(612) 788-8601

LEN STRONG

DIPLOMAT (MO)

2721 MERCONTILE DR.
ST, LOUIS, MO 63144

(314) 645·8550

LEN STRONG

NEVCO

1715 BALTIMORE AVE.
KANSAS CITY, MO 64108

(816)421-1751

LEN STRONG

COMPONENT SPEC,

7920 IE. 40TH ST.
TULSA, OK 74145

(918) 644-2820

LEN STRONG

KENTUCKY

EMA

35 COM PARK RD. BOX 449
CENTERVILLE, OH 45459

(513) 433-2800

LEN STRONG

LOUISIANA

WEST & ASSOC.

4300 ALPHA RD. # 106
DALLAS. TX 75234

(214) 661·9400

LEN STRONG

COMPONENT SPEC.

10907 SHADY TRAIL
DALLAS, TX 75220

(214)357-6511

LEN STRONG

COMPONENT TECH.

155·U NEW BOSTON ST. #172
WOBURN, MA 01801

(617) 933·5390

BOB GREEN

KIERULFF ELECT.

13 FORTUNE DR.
BILLERICA, MA 01821

(617) 657-l13:n

BOB GREEN

TIME-NEW ENG.

400 NEW BOSTON PARK
WOBURN, MA 01801

(517) 935-8080

NEW ERA SALES

7310 RITCHIE HWY. #407,
EMPIRE TOWERS
GLEN BURNIE, MD 21061

(301) 768-6666

BOB GREEN

KIERULFF ELECT.

3 EDISON PLACE
FAIRFIELD, NJ 07008

(201) 575·6750

BOB GREEN

TECHNICO

9051 RED BRANCH RD,
COLUMBIA, MD 21044

(301) 995-1995

BOB GREEN

359 E. MADISON.AVE.
CLIFTON HTS.. PA 19018

(215) 622-2500

BOB GREEN

INDIANA

IOWA

KANSAS

MAINE

MARYLAND

TIME-MI£J.A

REPRESENTATIVE

DISTRIBUTOR

538

STATE

PHONE

AREA MGR

COMPANY

ADDRESS

COMPONENT TECH.

155-U NEW BOSTON ST. #172
WOBURN. MA 01801

(617) 933-5390

BOB GREEN

DIPLOMAT ELECT.
(MA)

NE. IND. PRK-KUNIHOLM
P.O. BOX 217
HOLLISTON. MA 01746

(617) 429-4121

BOB GREEN

RC COMPONENTS

10 CORNELL PLACE
WILMINGTON. MA 01887

(617) 657-4310

BOB GREEN

KIERULFF ELECT.

13 FORTUNE OR.
BILLERICA, MA 01821

(617) 667-8331

BOB GREEN

TIME NEW ENG.

400 NEW BOSTON PARK
WOBURN, MA 01801

(617) 935-8080

BOB GREEN

GREINER ASSOC.

15324 E. JEFFERSON
GROSSE POINT, MI 48230

(313) 499-0188

LEN STRONG

DIPLOMAT ELECT.
(MI)

32708 W. 8 MILE RD.
FARMINGTON, MI 48924

(313) 477-3200

LEN STRONG

MEL FOSTER
TECH. SALES

7389 BUSH LAKE RD. BOX 35216
EDINA. MN 55435

(612) 835-2252

LEN STRONG

KIERULFF ELECT.

5289 W. 74TH ST.
EDINA. MN 55435

(612) 835-4388

LEN STRONG

DIPLOMT (MN)

3816 CHANDLER DR.
MINNEAPOLIS. MN 55421

(612) 788-8601

LEN STRONG

NEVCO

1715 BALTIMORE AVE.
KANSAS CITY. MO 64108

(816) 421-1751

LEN STRONG

NEVCO

10132 GLENFIELD TEA.
CRESTWOOD, MO 63126

(314) 843-7406

MISSISSIPPI

MURCOTA CORP.

1106 BURKE ST.
WINSTON SALEM. NC 27101

(919) 722-9445

BOB GREEN

""ONTANA

KIERULFF ELECT.

3695 W. 1987 S.

(801) 973-6913

BOB GREEN

MASSACHUSETIS

MICHIGAN

MINNESOTA

MISSOURI

LEN STRONG

SALT LAKE CITY. UT 84104

NEVADA

NEBRASKA

NEW HAMPSHIRE

EL REPCO

55 SURREY DA.
RENO. NV 89511

(702) 849-2899

E. ZITILE

BELLINO.

tl61N. FAiROAKS AVE.
SUNNYVALE. CA 94086

(408) 734-8570

E. ZITTlE

3969 E. BAYSHORE RD.
PALO ALTO, CA 94303

(415) 968-6292

E. ZITTlE

NEVCO

1715 BALTIMORE AVE.
KANSAS CITY. MO 64108

(816) 421-1751

LEN STRONG

DIPLOMAT (MO)

2721 MERCONTILE DR.
ST. LOUIS, MO 63144

(314) 645-8558

COMPONENT TECH.

155-U NEW BOSTON #172
WOBURN, MA 01801

(617) 933-5390

BOB GREEN

KIERULFF ELECT.

13 FORTUNE DR_
BILLERICA, MA 01821

(617) 935-8331

BOB GREEN

TIME NEW ENG.

400 NEW BOSTON PARK
WOBURN, MA 01801

(617) 935-8080

BOB GREEN

539

LEN STRONG

STATE
NEW JERSEY

COMPANY

ADDRESS

PHONE

AREA MGR

E.R.A.

354 VETERANS MEMORIAL HWY.
COMMACK, NY 11725

(516) 543-0510
NJ) 800-645-5500-5501

BOB GREEN

GCMASSOC.

1014 BETHLEHEM PIKE
ERDENHEIM, PA 19118

(215) 785-1830

BOB GREEN

DIPLOMAT

490 S. RIVERVIEW DR.
TOTOWA, NJ 07512

(201) 785-1830

BOB GREEN

MID ATLANTIC
ELECTRONICS

INTERSTATE INDUSTRIAL PARK
KOR-CENTER, EAST H-l
BELL MAWR, N.J, 08031

(609) 931-5303

BOB GREEN

TIME MID ATL.

359 E. MADISON AVE.
CLIFTON HTS., PA 19018

(215) 622-2500

BOB GREEN

KIERULFF ELECT.

3 EDISON PLACE
FAIRFIELD. NJ 07006

(201) 575-6750

BOB GREEN

OSSMANN
COMPo SALES

154 PICKARD BLDG.
SYRACUSE, NY 13211

(315) 455-6611

BOB GREEN

OSSMANN COMPo

280 METRO PARK
ROCHESTER, NY 1462:1

(716) 424-4460

BOB GREEN

E.RA

354 VETERANS MEMORIAL HWY.
COMMACK, NY 11725

(516) 543-0510
NJ) 80-645-5500-5501

BOB GREEN

DIPLOMAT

110 MURCUS DRIVE
MELVILLE. NY 11747

(516) 4.54-5334

BOB GREEN

KIERULFF ELECT.

3 EDISON PLACE
FAIRFIELD, NJ 07008

(201) 575-fJ750

BOB GREEN

TIME NEW ENG.

400 NEW BOSTON PARK
WOBURN. MA 01801

(617) 935-8080

BOB GREEN

ZEUS COMPONENTS

500 EXECUTIVE BLVD.
ELMSFORD. NY 10523

MURCOTA CORP.

1106 BURKE ST.
WINSTON SALEM, NC 27101

(919) 722-9445

BOB GREEN

DIPLOMAT IFL)

2120 CALUMET ST.
CLEARWATER, FL 33515

(813) 443-4514

BOB GREEN

MEL FOSTER
TECH. SALES

7389 BUSH LAKE RD,
EDINA. MN 55435

(612) 835·2252

LEN STRONG

DIPLOMAT (MN)

3816 CHANDLER DR.
MINNEAPOLIS, MN 55421

(612) 788·8601

LEN STRONG

NEW MEXICO

DAR-C INC.

14425 N. SCOTIDALE RD. #500
SCOTISDALE, AZ 85254

(602) 948-2240

JOE MADER

OHIO

EMA

35 COMPARK RD. BOX 449
CENTERVILLE, OH 45459

(513) 433-2800

LEN STRONG

EMA

337 GARFIELD RD. BOX 275
AURORA, OH 44202

(216) 562-6104

LEN STRONG

DEECOINC.

2500 S. W. 16TH AVE

(319) 365-755.1

LEN STRONG

NEW YORK

NORTH CAROLINA

NORTH & SOUTH
DAKOTA

CEDERS RAPIDS. OH 52408

OKLAHOMA

REPRESENTATIVE

IND'L PRODUCTS

35 COMPARK RD.
CENTERVILLE OH 45459

(513) 435-2086

LEN STRONG

IND'L PRODUCTS

337 GARFIELD RD.
AURORA, OH 44202

(216) 562-8113

LEN STRONG

COMPONENT SPEC.

7920 E. 40TH ST
TULSA, OK 74145

(918) 664-2820

LEN STRONG

DISTRIBUTOR

540

STATE
OREGON

COMPANY

ADDRESS

PHONE

AREAMGR
E. ZITTLE

COMPONENTS WEST

13540 N.w. MILL CREEK
PORTLAND, OR 97229

(503) 643-5588

KIERULFF ELECT.

1005 ANDOVER PK E.
TUKWILA, WA 98188

(206) 575·4420

E. ZITTLE

GCM

1014 BETHLEHEM PIKE
ERDENHEIM, PA 19/18

(215) 233-4600

BOB GREEN

EMA

35 COMPARK RD. BOX 449
CENTERVILLE, OH 45459

(513) 433-2800

BOB GREEN

KIERULFF ELECT.

3 EDISON PLACE
FAIRFIELD, NJ 07006

(201) 575-6750

B08GREEN

TIME MID ATL.

359 MADISON AVE.
CUFTON HTS. PA 19018

(215) 622·2500

808 GREEN

MACK ELECTRONIC

1014 8ETHLEHEM PIKE
ERDENHEIM, PA 19118

(215) 233·4650

808 GREEN

COMPONENT TECH.

155·U NEW BOSTON PK. #172
WOBURN, MA 01801

(617) 933·5390

BOB GREEN

TIME NEW ENG.

400 NEW 80STON PARK
W08URN, MA 01801

(617) 935·8080

BOB GREEN

MURCOTA CORP.

1106 BURKE ST.
WINSTON SALEM, NC 27101

(919) 722-9445

BOB GREEN

DIPLOMAT IFL)

2120 CALUMET ST.
CLEARWATER, FL 33515

(813) 443-4514

B08GREEN

TENNESSEE

MURCOTA CORP.

1106 BURKE ST.
WINSTON, SALEM, NC 27101

(919) 722-9445

BOB GREEN

TEXAS

DAR-C

14425 N. SCOTTSDALE #500
SCOTTSDALE, AZ 85254

(602) 948·2240

LEN STRONG

WEST ASSOC.

4300 ALPHA RD. #106
DALLAS, TX 75234

(214) 661-9400

LEN STRONG

WEST ASSOC.

9730 TOWN PARK #101
HOUSTON, TX 77036

(713) 777·4108

LEN STRONG

WEST ASSOC.

4515 MANCHACA RD. # 105
AUSTIN, TX 78745

(512) 441·6973

LEN STRONG

COMPONENT SPEC.

10907 SHADY TRAIL
DALLAS, TX 75220

(214) 357·6511

LEN STRONG

COMPONENT SPEC.

8222 JAMESTOWN RD.
AUSTIN, TX 78758

(512) 837·8922

LEN STRONG

COMPONENTS SPEC.

8181 COMMERCE PARK DR.
HOUSTON, TX 77036
SUITE 700

(713) 771·7237

LEN STRONG

QUALITY
COMPONENTS

1020 McKALLA #D
AUSTIN, TX 78758

(512) 835-0220

LEN STRONG

QUAUTY
COMPONENTS

4257 KELLWAY CIRCLE
ADDISON, TX 75001

(214) 387·4949

LEN STRONG

QUALITY
COMPONENTS

6126 WESTLINE
HOUSTON, TX 77036

(713) 772·7100

LEN STRONG

PENNSYLVANIA

RHODE ISLAND

SOUTH CAROLINA

541

STATE

COMPANY

ADDRESS

PHONE

AREA MGR

COMPONENT SALES

2520 S. STATE ST. #102
BOX 15084
SALT LAKE CITY, UT 84115

(801) 485-0363

E. ZITTLE

BELL INDUSTRIES

3639 W. 2150 SOUTH
SALT LAKE CITY, UTAH 84120

(801) 972-6969

E.ZmLE

DIPLOMAT (UT)

3007 S. W. TEMPLE
SALT LAKE CITY, UT 84115

(801) 486-4134

E. ZITTLE

DIPLOMAT

7100 BROADWAY-BLDG 6
DENVER, CO 80221 ,

(303) 427-5544

E.ZmLE

KIERULFF ELECT.

3695 W. 1987 S.
SALT LAKE CITY, UT 84104

(801) 973-6913

E. ZITTLE

VERMONT

COMPONENT TECH.

155-U NEW BOSTON PK # 172
WOBURN, MA 01801

(617) 933-5390

BOB GREEN

VIRGINIA

NEW ERA SALES

7310 RITCHIE HWY. #407
EMPIRE TOWERS
GLEN BURNIE, MD 21061

(301) 768-6666

BOB GREEN

TIME MID An.

359 E. MADISON AVE.
CLIFTON HTS. PA 19018

(215}.622-2500

BOB GREEN

COMPONENTS WEST

451 S.W. 10TH ST. #109
RENTON, WASH. 98055
BOX 58006, TUKWilA, WA 98188

(206) 271-5252

E. ZITTLE

KIERu/FF

1005 ANDOVER PK. E.
TUKWILA, WA 98188

(206) 575-4420

E. ZITTLE

NEW ERA SALES

7310 RITCHIE HWY. #407
EMPIRE TOWERS
GLEN BURNIE, MD 21601

(301 ) 768-6666

BOB GREEN

TECHNICO

9051 RED BRANCH RD.
COLUMBIA, MD 21044

(301) 995-1995

BOB GREEN

TIME MID ATL.

359 MADISON AVE.
CUFTON HTS. PA 19018

(215) 622-21;00

BOB GREEN

WEST VIRGINIA

NEW ERA SALES

7310 RITCHIE HWY. #407
EMPIRE TOWERS
GLEN BURNIE, MD 21061

(301) 768-6666

BOB GREEN

WISCONSIN

MEL FOSTER
TECH. SALES

7389 BUSH LAKE RD.
EDINA, MN 55435

(612) 835-2252

LEN STRONG

JANUS INC.

3166 DES PLAINES
DES PLAINES, IL 60018

(312) 298-9330

LEN STRONG

KIERULFFELECT.

2212 E. MOORELAND AVE.
WAUKESTA, WI 53186

(414) 78.4-8160

LEN STRONG

DIPLOMAT (MN)

3816 CHANDLER DR,
MINNEAPOLIS, MN 55421

(612) 788-8601.

LEN STRONG

DIPLOMAT (ILL)

1071 JUDSON
BENSENVILLE, IL 60106

(312) 595-1000

LEN STRONG

COMPONENT SALES

5925 E. EVANS AVE. #204B
DENVER, CO 80222

(303) 759-1666

E. ZITTLE

DIPLOMAT (UT)

3007 S.W. TEMPLE
SALT LAKE CITY, UT 84115

(801) 486-4134

E. ZITTLE

UTAH

WASHINGTON

WASHINGTON DC

WYOMING

REPRESENTATIVE

DISTRIBUTOR

542

FOREIGN REP/DIST QUICK REFERENCE BY COUNmy
COUNTRY

COMPANY

PHONE NO.

ADDRESS

TELEX NO.

AUSTRALIA

DANEVA CONTROLS

70 BAY ROAD. SANDRIGHAM 3191
VICTORIA. AUSTRALIA

(3) 598-9207

79034439

AUSTRIA

INTRACO
AF·SYSTEME GMBH

AM BRUNNER 19
D·8011 HEIMSTETTEN
POST KIRCH HElM,
WEST GERMANY

(089) 90 36191

8415216329

BELGIUM

ETS JP LEMAIRE

RAMPE GAULOISE 1A
1020 BRUXELLES
BELGIUM

479-8690

84624610

BRAZIL

EXIMEL IMPORTACAO

E EXPORTACAO LTDA
RUA AURORA 1711CJ2
SAO PAULO
BRAZIL CEP 01209

(011)222·4170
(011)223,7388

3911131298

CANADA

WEBER ELECTRONIC

105 BRISBANE ROAD
DOWNSVIEW, ONTARIO M3J 2K6

(416)663,5650

6104223048

DIST

SEMAD ELECTRONIC
OTTAWA OFFICE:

864 LADY ELLEN PLACE
OTTAWA, ONTARIO KLZ 5L5

6104921337

SEMAD ELECTRONIC
DORVAL OFFICE

620 MELOCHE AVENUE
DORVAL, QUEBEC H9P 2P4

6104921337

DENMARK

C-88

ULDVRJEN 10
DK·2970 HORSHOLM, DENMARK

02·5708·88

85537578

ENGLAND

PRONTO

466·478 CRANBROOK ROAD,
GANTS HILL, ILFORD, ESSEX.
lG26LE

01 ·599·304 1

(851)8954213

FINLAND

KOMDEL OY

VANHA FINNOONTIE 4
02270 ESPOO 27, FINLAND
BOX 32, 02271 ESPOO 27,
FINLAND

90·885001

857121926

FRANCE

TECHNOLOGY
RESOURCES

27-29 RUE DES POISSONNIERS
92200 NEUILLY·SUR·SEINE,
FRANCE

747-4717
747-7051

842610657

W.GERMANY

INTRACO
SYSTEME GMBH

AM BRUNNER 19
D·8011 HEIMSTETTEN
POST KIRCHHEI M,
WEST GERMANY

(089) 90 36 191

8415216329

DIST.

ELECTRONIC 2000
VERTRIEBS CMBM

8000 MUNCHEN 80
NEUMARKTER STRASSE 75
WEST GERMANY

(089) 43 40 61

841522561

HOLLAND

DIODE

HOLLAN D LAAN NO. 22
UTRECHT, HOLLAND

030884214

(846)47388

HONG KONG

WHITE & ALLCOCK

TOPPAN BUILDING, 6TH FLOOR
22 WESTLANDS ROAD
QUARRY BAY, HONG KONG

5·632113-8
5-644312
5-644332

78083640

INDIA

KRYONIX

KOWDAIR, TRIVANDRUM
PIMCODE: 695003, SOUTH INDIA

63805

953884307

U.S. OFFICE

MIRCO AIDS INT'L

778 BLUE SAGE DRIVE
SUNNYVALE, CALIF 94086

(408) 738-2295

543

COUNTRY

COMPANY

ADDRESS

PHONE NO,

TELEX NO,

ISRAEL

VECTRONICS LTD

69 DORDONS ST. BOX 16335
TEL AVIV, ISRAEL

(010) 23 44 24
(010) 22 64 72
(010) 24 63 12

92232396

ITALY

COMPREL S.R.L.

20092 CINSELLO B.
(MI) - V. LE ROMAGNA, ITALY

(02) 61206412

843332464

JAPAN

PANETRON
DIV. TOKOYO
ELECTRON LIMITED

38 FL. SHINJUKU NOMURA BD.
1-26-2, NISHI-SHINJUKU
SHINJUKU-KU, TOKYO 160 JAPAN

03-343-4411

781-2322220

U,S, OFFICE:

PAN ELECTRON
INCORPORATED

465 S. MATHILDA AVE
SUNNYVALE, CALIF. 94086

(408) 735-8731

346342

NEW ZEALAND

DANEVA CONTROL

70 BAY ROAD, SANDRIGHAM 3191
VICTORIA, AUSTRALIA

(03) 598-9207

79034439

NORWAY

HANS H. SCHIVE NS
ELECTRONIC
COMPONENTS

GUSTAV VIGELANDS vel 5,
BOX 250
SKOYEN OSLO 2 NORWAY

(010) 475754655

85619124

REP,OF
IRELAND

NELTRONIC LTO

JOHN F. KENNEDY ROAD NAAS
ROAD
DUBLIN 12, REP. OF IRELAND

DUBLIN 501845

8524837

SINGAPORE

TOTAL COMPUTER
SYSTEMS (S) PTE LTO.

20/237, 6TH FLOOR BLOCK 12
50, KALLANG BAHRU.
SINGAPORE 12

(786) 293-4401

78623910

SOUTH AFRICA

SOUTH CONTINENTAL
DEVICES

5TH FLOOR, RANDOVER HOUSE
DOVER ST. 960
RANDBURG, S. AFRICA

(011) 789-2400

9604-24849

SPAIN

INTERFACE S.A.

RDA SAN PEDRI 22, 30
BARCELONA, 10 SPAIN

93-456-31-51

83151508

SWEDEN

TELEIMPORT AB

BOX 5071 S 162 05
VALLINGBY, SWEDEN

VX 08-89-0435

85413033

SWITZERLAND

STOLZAG

TAFERNSTRASSE 15
5405 BADEN-DAITWIL,
SWITZERLAND

05618401 51

84554070

TAIWAN
(REP/CHINA)

TAIWAN
AUTOMATION CO.

8TH FLOOR 270 NANKING E. RD
SECTION 3, TAIPEI TAIWAN, R.O.C.

(02) 771-0940-3

78511942

NEW JERSEY

SST TRADE
& DEVELOPMENT

1101 SLOCUM AVE
RIDGEFIELD, NEW JERSEY 07657

(201) 941-3333

135197

OFFICE:

544

2445 McCABE WAY, POST OFFICE BOX 2180
IRVINE, CALIFORNIA 92714
(714) 557-3550, TWX 910-595-1139

Source Exif Data:
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1981_Western_Digital_Product_Handbook 1981 Western Digital Product Handbook

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