1981_Zilog_Microcomputer_Components_Data_Book 1981 Zilog Microcomputer Components Data Book
User Manual: 1981_Zilog_Microcomputer_Components_Data_Book
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Microcomputer
Components
Data Book
Microcomputers in Every Form
Zilog offers microcomputers in
every form: from components and
development systems to board-level
products and complete generalpurpose microcomputer systems.
This edition of the Zilog Data Book
describes Zilog components,
development systems, and microcomputer boards. You'll also find a
section on the in-depth training
courses now offered about most
Zilog products.
Zilog components, the basic
building blocks for our other
microcomputer products, include
the 8-bit Z80® Microprocessor and
its family of intelligent peripherals,
the Z8™ Family of Single-Chip
Microcomputers, and the l6-bit
Z8000™ Microprocessor and its
family of intelligent peripherals.
Zilog offers a wide variety of
development environments, ranging from the inexpensive Z8 and
Z8000 Development Modules to the
more elaborate PDS 8000 and
ZDS-l Development Systems to the
ultra-sophisticated multi-user
Z-LAB 8000 Development System.
In addition, the Z-SCAN 8000
provides in-circuit emulation for
both the Z800 land 28002
Microprocessors.
Our 280 MCB Board Family
offers a complete solution for prototype and production designs in
which you don't want to design a
microcomputer from scratch. This
iii
well-established family includes a
Z80 CPU board, several types of
memory boards, and boards for all
types of digital and analog I/O. A
complete set of card cages,
enclosures, and other accessories
makes this family easy to use.
The card at the beginning of the
data book allows you to register for
an on-going program to keep you
informed of the latest developments
at Zilog. New information will be
published as "stand-alone" data
sheets, also in this convenient
7" x 9" size. If you are interested
in receiving this information as
well as a handy binder to hold it
in, simply fill out the card and
return it to us.
Table of Contents
3
5
27
45
59
71
28449 SIO/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87
28470 DART ............................................. 89
I
Z8DDD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 103
28001/2 CPU ........................................... 105
2
Z8D Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28400 CPU.............................................
28410 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28420 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28430 CTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
284401112 SIO ..........................................
28010 2-MMU ........................................... 133
28030 2-SCC ........................................... 149
280362-CIO ............................................ 171
28038 2-FIO ............................................ 195
28060 FIFO ............................................ 227
28065 2-BEP ............................................ 229
28068 2-DCP ........................................... 231
28090 2-UPC ........................................... 233
Universal Peripherals .................................. 257
28538 FlO ................................... See 28038 2- FlO
28530 SCC ............................................. 259
28536 CIO ............................................. 281
28590 UPC ............................................. 305
3
Z8 Family ............................................. 327
2860112/3 MCU ......................................... 329
2861112/3 MCU ......................................... 347
4
28681 MCU ............................................ 365
Memory
261324K x 8 Quasi-Static RAM ........................... 371
5
Additional Information
The Zllog 2-BUS Interconnect. . . . . . . . . . . . . . . . . . . . . . .. . ... 381
Advanced Architectural Features of the 28000 CPU ........... 397
An Introduction to the 28010 MMU ........................ .411
HIgh-Reliability Microcircuits ............................ .431
6
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
7
v
Table of Contents (Continued)
zao Microcomputer Boards .............................. 443
Z80 MCB .............................................. 445
Z80 RMB ............................................... 449
Z80 AIO/AIB .......................................... 453
Z80 IOB ............................................... 457
Z80 SIB ................................................ 459
Z80PPB ................................................ 463
Z80 PMB ............................................. .465
Z80 MDC .............................................. 467
8
Zilog Development Systems .............................. 473
ZDS-1I25 ............................................... 475
ZDS-l/40 .............................................. 477
PDS 8000 . . . . . . .. . ................................... .481
Z8 Development Module .................................. 485
Z8000 Development Module ............................... 489
Z-SCAN 8000 ........................................... 493
Z80 PLZ ................................................ 497
Z8 Software Development Package ......................... 499
Z8000 Softwdre Development Package ...................... 501
Z8000 Cross-Software Package ............................ 503
9
Zilog Technical Training ................................ 507
VI
10
Z80 Family
2
Zilog Z80® Family
~
Zilog
Faster Z80B
Peripheral Controllers
March 1981
Zilog has become an industry
leader, thanks to innovation in
microcomputer concepts and
integrated design exemplified in
the Z80 Family of microcomputer
products.
At Zilog, mnovahon means using
proven, sophisticated mainframe
and minicomputer concepts and
translating them into the latest LSI
technologies. Integration means
more than designing an evergreater number of funchons onto
a single chip. Zilog integrates
technologies-LSI design
enhanced by advances in
computer-based system
architecture and system deSign
technologies.
Zilog offers miCroprocessor
solutions to computing problems:
from components and development
systems to OEM board-level
products and general-purpose
microcomputer systems.
ThiS gUide to the Z80 Family of
state-of-the-art microprocessors
and mtelligent peripheral controllers demonstrates Zilog's
continued support for the Z80
miCroprocessor and the other
members of the Z80 product
familY-d family first introduced m
1976 that continues to enjoy growing customer support while family
chips are upgraded to newer and
ever-higher standards.
The design philosophy of all
Z80 Family members IS to help
eng meers deSign microcomputer
systems with fewer components that
have more functions per chip. The
Z80 CPU offers many more features
and functions than its competitor.
The Z8400 Z80 CPU Central
Processing Unit has rapidly
established itself as the most
sophisticated, most powerful, and
most versatile 8-blt microprocessor
in the world. In addition to being
source-code compatible with the
8080A microprocessor, the Z80
offers more mstruchons than the
8080A (158 vs. 78) and numerous
other features that simplify hardware requirements and reduce programming effort while increasing
throughput. The dual-register set
of the Z80 CPU allows high-speed
context switching and more effiCient interrupt processing. Two
index registers give additional
memory-addressing fleXibility and
simplify the task of programmmg.
InterfaCing to dynamic memory is
svnplified by on-chip, programmable refresh logiC. Block moves
plus string- and bit-manipulation
mstructions reduce programming
effort, program Size, and execution
hme.
The four traditional funchons of
a microcomputer system (parallel
I/O, serial I/O, co\mting/timmg,
and direct memory access) are
easily implemented by the Z80
CPU and the following well-proven
family of Z80 peripheral devices:
Z80 PIO, Z80 SIO, Z80 DART, Z80
CTC, and Z80 DMA.
The easily programmed, dualchannel Z8420 Z80 PIO Parallel
Input/Output Controller offers two
8-bit I/O ports with individual
handshake and pattern recognihon
logiC. Both I/O ports operate in
either a byte or a bit mode. In
addition, this deVice can be programmed to generate interrupts for
various status condihons.
All common data communications protocols, asynchronous as
well as synchronous, are
remarkably well handled by the
Z8440 Z80 SIO Serial Input/Output
Controller. This dual-channel
receiver/transmitter device offers
on-chip parity and CRC generation/checking. FIFO buffering and
flag- and frame-detection generation logic are also offered.
If asynchronous-only applications are required, the costeffective Z8470 Z80 DART Dual
Asynchronous Receiver/Transmitter can be used in place of the Z80
SIO. The Z80 DART offers all Z80
SIO asynchronous features in two
channels.
Timing and event-counting functions are the forte of the Z8430 Z80
CTC Counter/Timer Controller.
The CTC provides four counters,
each with indiVidually programmable prescalers. The CTC is a
convenient source of programmable clock rates for the SIO.
With the Z8410 Z80 DMA Direct
Memory Access Controller, data
can be transferred directly
between any two ports (tYPically,
I/O and memory). The DMA transfers, searches, or search/transfers
data in Byte-by-Byte, Burst, or
Continuous modes. This deVice can
achieve an impressive 2M bits
per second data rate m the
Search mode.
3
N
00
O.
t'2 I
IG
c::::
4
18400
Z80® CPU Central
Processing Unit
~
Zilog
Product
Specification
March 1981
Features
• The instruction set contains 158 instructions.
The 78 instructions of the 8080A are
included as a subset; 8080A software compatibllity is mamtained.
may be daisy-chained to allow implementation of a priority mterrupt scheme. Little,
if any, additional logic is required for
daisy-chaining.
• SlX MHz, 4 MHz and 2.5 MHz clocks for the
Z80B, Z80A, and Z80 CPU result in rapid
instruction execution wlth consequent high
data throughput.
• Duplicate sets of both general-purpose
and flag registers are prOVided, easing
the deslgn and operahon of system software through single-context sWltching,
background-foreground programmmg, and
Single-level interrupt processing. In addltion, two 16-blt index registers facilitate
program processing of tables and arrays.
• The extensive instruction set mcludes string,
bit, byte, and word operations. Block
searches and block transfers together with
indexed and relahve addressing result m
the most powerful data handling capabilities
in the microcomputer mdustry.
• The Z80 microprocessor; and associated
family of peripheral controllers are linked
by a vectored interrupt system. This system
..
..
M1
• There are three modes of high speed interrupt processmg: 8080 compatible, non-Z80
peripheral device, and Z80 Family
penpheral wlth or without dalsy chain.
• On-chip dynamic memory refresh counter.
A,
A,
MREQ
",,-j
CONTROL
A,
lORa
RD
WR
.,
.,
RFSH
HAl.T
ONj
CONTROL
A,
A11
A,
A"
A,
A"
A,
A"
A"
eLK
A"
A12
0,
A"
0,
A"
0,
A"
+5 V
..
..
A12
ADDRESS
BUS
A,
zao
CPU
0,
0,
CPU {
BUS
CONTROL
)
DATA
BUS
2001·0210, 0211
A,
A,
A,
A,
A,
GND
0,
RFSH
Do
0,
RESET
M1
iNT
BUSREC
NMI
WAIT
HALT
Figure 1. Pin Functions
A"
A,
BUSACK
MREQ
ViR
lORa
AD
Figure 2. Pin Assignments
5
General
Description
The Z80, Z80A, and Z80B CPUs are thirdgenerahon single-chip microprocessors with
exceptional computational power. They offer
higher system throughput and more efficient
memory utilization than comparable secondand third-generation mICroprocessors. The
internal registers contam 208 bits of read/write
memory that are accessible to the programmer.
These registers include two sets of six generalpurpose registers which may be used
individually as either 8-bit registers or as
16-bit register pairs. In addition, there are two
sets of accumulator and flag registers. A group
of "Exchange" mstructions makes either set of
main or alternate registers accessible to the
programmer. The alternate set allows operation
in foreground-background mode or it may
be reserved for very fast interrupt response.
The Z80 also contams a Stack Pointer, Program Counter, two index registers, a Refresh
register (counter), and an Interrupt register.
The CPU is easy to incorporate into a system
smce it reqUires only a smgle + 5 V power
source, all output signals are fully decoded
and hmed to control standard memory or
penpheral cirCUits, and is supported by an
extensive family of peripheral controllers. The
internal block diagram (Figure 3) shows the
pnmary functions of the Z80 processors.
Subsequent text provides more detail on the
Z80 1/0 controller family, registers, instruchon
set, interrupts and daisy chaining, and CPU
timing.
+5V -...
GND ....
CLOCK ....
Figure 3. Z80 CPU Block Diagram
6
2001·0212
ZBO Microprocessor
Family
The Zilog Z80 microprocessor is the central
element of a comprehensive microprocessor
product family. This family works together in
most applications with minimum requirements
for additional logic, facilitating the design of
efficient and cost-effective microcomputerbased systems.
Zilog has desIgned five components to provide extensive support for the Z80 microprocessor. These are:
each of which has an 8-bit prescaler. Each
of the four channels may be configured to
operate in either counter or timer mode.
• The DMA (Direct Memory Access) controller provides dual port data transfer
operations and the ability to terminate data
transfer as a result of a pattern match.
• The SIO (Serial Input/Output) controller
offers two channels. It is capable of
operating in a variety of programmable
modes for both synchronous and asynchronous communication, including
Bi-Synch and SDLC.
• The PIO (Parallel Input/Output) operates in
both data-byte I/O transfer mode (with
handshaking) and in bit mode (without
handshaking). The PIO may be configured to interface with standard parallel
peripheral devices such as printers,
tape punches, and keyboards.
• The DART (Dual Asynchronous Receiver/
Transmitter) device provides low cost
asynchronous serial communication. It has
two channels and a full modem control
interface.
• The CTC (Counter/Timer Circuit) features
four programmable 8-bit counter/timers,
ZBO CPU
Registers
Figure 4 shows three groups of registers
within the Z80 CPU. The first group consists of
duplicate sets of 8-bit registers: a principal set
and an alternate set (designated by , [prime],
e.g., A'). Both sets consist of the Accumulator Register, the Flag Register, and six
general-purpose registers. Transfer of data
between these duplicate sets of registers is
accomplished by use of "Exchange" instructions. The result is faster response to interrupts
and easy, efficient implementation of such versatile programming techniques as background-
foreground data processing. The second set of
registers consists of six registers with assigned
functions. These are the I (Interrupt Register),
the R (Refresh RegIster), the IX and IY (Index
Registers), the SP (Stack Pointer), and the PC
(Program Counter). The third group consists of
two interrupt status flip-flops, plus an additional pair of flip-flops which assists in identifying the interrupt mode at any particular
time. Table I provides further information on
these registers.
ALTERNATE REGISTER SET
MAIN REGISTER SET
A
'ACCUMULATOR
F
FLAG REGISTER
A'
ACCUMULATOR
F'
FLAG REGISTER
B
GENERAL PURPOSE
C
GENERAL PURPOSE
B'
GENERAL PURPOSE
c·
GENERAL PURPOSE
D
GENERAL PURPOSE
E
GENERAL PURPOSE
D'
GENERAL PURPOSE
E'
GENERAL PURPOSE
H
GENERAL PURPOSE
L
GENERAL PURPOSE
H'
GENERAL PURPOSE
L'
GENERAL PURPOSE
- 4 - - - - 8 BITS _
_
-------168IT5-------_+
INTERRUPT
FLIP FLOPS
G
c:J
IX INDEX REGISTER
4~~ :
IV INDEX REGISTER
STATUS
INTERRUPTS DISABLED
STORES IFF1
INTERRUPTS ENABLED
DURING NMI
SERVICE
SP STACK POINTER
INTERRUPT MODE FLIP FLOPS
PC PROGRAM COUNTER
I INTERRUPT VECTOR
I
lMFa
R MEMORY REFRESH
IMFb
INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2
Figure 4. CPU Registers
2001-0213
7
zaD CPU
Registers
(Continued)
Size (Bits)
Remarks
General Purpose
8
8
8
8
8
8
8
8
Stores an 'operand or the results of an operation.
Interrupt Register
8
R
Refresh RegIster
8
PrOVIdes user-transparent dynamic memory refresh. Automabcally
incremented and placed on the address bus during each
instruction fetch cycle.
IX
IY
SP
Index RegIster
Index RegIster
Stack Pomter
16
16
16
Used for indexed addressing.
Same as IX, above.
Stores addresses or data temporanly. See Push or Pop in instruc-
PC
Program Counter
IFFI-IFF2
IMFa-IMFb
Interrupt Enable
Interrupt Mode
Register
A, A'
F, F'
B, B'
C, C'
D, D'
Accumulator
Flags
General Purpose
General Purpose
General Purpose
E, E'
General Purpose
H, H'
General Purpose
L, L'
See Instruction Set.
Can be used separately or as a 16-bit register with C.
See B, above.
Can be used separately or as a 16-bit register with E.
See D, above.
Can be used separately or as a 16-blt register with L.
See H, above.
Note: The (B,C), (D,E), and (H,L) sets are combined as follows:
B - HIgh byte C - Low byte
D - High byte E - Low byte
H - High byte L - Lo,w byte
Stores upper eight bits of memory address for vectored interrupt
processing.
tion set.
16
Fhp-Flops
Fhp-Flops
Holds address of next instrucbon.
Set or reset to mdicate interrupt status (see Figure 4).
Rellect Interrupt mode (see Figure 4).
Table 1.
Interrupts:
General
Operation
The CPU accepts two interrupt input signals:
NMI and INT. The NMI is a non-maskable
interrupt and has the highest priority. INT is a
lower priority interrupt since it requires that
interrupts be enabled in software in order to
operate. Either NMI or INT can be connected
to mulhple peripheral devices in a wired-OR
configuration.
The Z80 has a single response mode for
interrupt service for the non-maskable interrupt. The maskable interrupt, INT, has three
programmable response modes available.
These are:
• Mode a - compatible with the 8080 microprocessor.
8
zeo CPU Registers
• Mode 1 - Peripheral Interrupt service, for
use with non-g080/Z80 systems.
• Mode 2 - a vectored interrupt scheme,
usually daisy-chained, for use with Z80
Family and compatible peripheral devices.
The CPU services interrupts by sampling the
NMI and INT signals at the rising edge of the
last clock of an instruction. Further interrupt
service processing depends upon the type of
mterrupt that was detected. Details on interrupt responses are shown in the CPU Timing
Section.
Interrupts:
General
Operation
(Continued)
Non-Maskable Interrupt (NMI). The nonmaskable interrupt cannot be disabled by program control and therefore will be accepted at
at all times by the CPU. NMI is usually
reserved for servicmg only the highest Priority
type interrupts, such as that for orderly shutdown after power failure has been detected.
After recogmtion of the NMI signal (providing
BUSREQ is not active), the CPU jumps to
restart location 0066H. Normally, software
starting at thIS address contains the mterrupt
service routine.
Maskable Interrupt (lNT). Regardless of the
interrupt mode set by the user, the 280
response to a maskable mterrupt Input follows
a common timing cycle. After the interrupt has
been detected by the CPU (provided that
interrupts are enabled and BUSREQ is not
active) a special interrupt processing cycle
begins. This is a special fetch (MI) cycle in
which IORQ becomes active rather than
MREQ, as in a normal MI cycle. In addition,
thiS special MI cycle IS automatically extended
by two WAIT states, to allow for the time
required to acknowledge the interrupt request
and to place the Interrupt vector on the bus.
Mode 0 Interrupt Operation. This mode IS
compatible with the 8080 microprocessor mterrupt service procedures. The mterrupting
device places an instruction on the data bus,
which IS then acted on SIX times by the CPU.
This IS normally a Restart InstructlOn, whICh
Will initiate an unconditional jump to the
selected one of eight restart 10catlOns in page
zero of memory.
Mode 1 Interrupt Operation. Mode I operation is very similar to that for the NMI. The
prinCipal difference IS that the Mode I mterrupt has a vector address of 0038H only.
Mode 2 Interrupt Operation. ThiS mterrupt
mode has been designed to utlhze most effectively the capabillhes of the 280 microprocessor and ItS assOCiated peripheral family. The
Interrupting peripheral device ,selects the
startmg address of the mterrupt service
routme. It does thiS by placing an 8-blt
address vector on the data bus durmg the
mterrupt acknowledge cycle. The high-order
byte of the mterrupt servICe routine address IS
supphed by the I (Interrupt) regISter. ThIS flexIbility In selectmg the Interrupt servICe routine
address allows the peripheral deVICe to use
several different types of servICe routines.
These routines may be located at any available
location in memory. Since the interrupting
device supplies the low-order byte of the
2-byte vector, bit 0 (Ao) must be a zero . .
Interrupt Priority (Daisy Chaining and
Nested Interrupts). The interrupt priority of
each peripheral device is determined by its
physical location within a daisy-chain configuration. Each device in the chain has an interrupt enable input line (lEI) and an interrupt
enable output line (lEO), which is ·fed to the
next lower priOrity deVICe. The first device in
the daisy chain has its lEI input hardwared to
a High level. The first device has highest
priority, while each succeeding device has a
corresponding lower priority. This arrangement permits the CPU to select the highest
priority interrupt from several Simultaneously
interrupting peripherals.
The interrupting device disables its lEO line
to the next lower priOrity peripheral until it has
been serviced. After serviCing, ItS lEO Ime is
raised, allowing lower pnority peripherals to
demand interrupt servicing.
The 280 CPU Will nest (queue) any pending
interrupts or interrupts received while a
selected peripheral is being serviced.
Interrupt Enable/Disable Operation. Two
flip-flops, IFFI and IFF2, referred to in the
register description are used to signal the CPU
Interrupt status. Operation of the two flip-flops
is described in Table 2. For more details, refer
to the Z80 CPU Technical Manual and Z80
Assembly Language Manual.
Action
IFFI
IFF2
Comments
CPU Reset
0
0
Maskable mterrupt
!NT dIsabled
Dr InstructIon
0
0
executIon
Maskable mterrupt
INT dIsabled
instructIon
execution
Maskable mterrupt
INT enabled
EI
LD A,I mstructlon
IFF2 - Panty flag
execution
LD A,R mstructlon
IFF2 - Panty flag
executIon
Accept NMI
RETN mstructIon
execution
0
IFF2
IFF]
IFF] - IFF2
(Maskable mterrupt INT dIsabled)
IFF2 - IFF] at
complehon of an
NMI servIce
routme.
Table 2. Siale 01 Flip-Flops
9
Instruction
Set
o
o
o
o
o
The 280 microprocessor has one of the most
powerful and versatile instruction sets
available in any 8-bit microprocessor. It
includes such unique operations as a block
move for fast, efficient data transfers within
memory or between memory and 1/0. It also
allows operations on any bit in any location in
memory.
The following is a summary of the 280
instruction set and shows the assembly
language mnemonic, the operation, the flag
status, and gives comments on each instruction. The Z80 CPU Technical Manual
(03-0029-01) and Assembly Language
Programming Manual (03-0002-01) contain
significantly more details for programming
use.
The instructions are divided into the
following categories:
8-Bit
Load
Group
Calls, returns, and restarts
o
o
o
o
Immediate
Immediate extended
Modified page zero
Relative
0 Extended
o
16-bit loads
0 Register indirect
o
o
General-purpose arithmetic and CPU
control
Flags
H
P/V N
Symbolic
Operation
Indexed
0 Register
Exchanges, block transfers, and searches
Mnemonic
Jumps
A variety of addressing modes are
implemented to permit efficient and fast data
transfer between various registers, memory
locations, and input/output devices. These
addressing modes include:
o 8-bit arithmetic and logic operations
o
Bit set, reset, and test operations
o Input and output operations
o 8-bit loads
o
o
16-bit arithmetic operations
Rotates and shifts
C
Implied
Bit
Opcod.
76 543 210 Hox
No.of No.of M No.of T
Cycles Stale.
,
LD r, r'
LD r, n
r - r'
X
X
X
X
01
00
LD" (HL)
LD" (IX+d)
, - (HL)
r - (IX+d)
X
X
X
X
LD '. (IY+d)
, - (IY+d)
X
X
LD(HL), ,
LD (IX+d). ,
(HL) - ,
(JX+d) - r
x
X
X
X
LD (IY +d), ,
(IY+d) - ,
x
X
LD (HL). n
(HL) - n
X
X
lID
01
II OIl WI
01
101
-dII III 101
01
lID
-dOl lID
II 011 101
01 110
-dII III 101
01 llO
-dOD lID 110
LD (IX+d), n
(IX+d) - n
X
X
LD (IY +d), n
(IY+d) - n
X
LD A, (BC)
LD A, (DE)
LD A, (nn)
A - (BC)
A - (DE)
LD (BC), A
LD (DE), A
LD {nnl. A
"
, 110
,
,
~
000
B
-n-
.
,
,
,
,
·
Comments
Byt••
DD
7
19
FD
19
DD
7
19
FD
19
36
10
DD
36
19
FD
36
19
OA
IA
3A
7
7
13
02
12
32
7
7
13
001
010
011
100
101
III
C
D
E
H
L
A
-nII 011 101
00110110
-d-
-nX
Il III 101
00110 110
-d-
X
X
X
X
X
X
OD 001 010
00 011 010
00 III 010
(BC) - A
(DE) - A
(nn) - A
X
X
X
X
X
X
LDA, I
A- I
X
X IFF
LDA, R
A-R
X
X IFF
LDI,A
I - A
X
LDR, A
R-A
X
-nA - (nn)
.
-n-
·
OD 000 010
00 010 010
00 110 010
-n-
NOTES
10
. ·
r, r' means any of the regIsters A, B, C, D, E, H, L
IFF the content althe mterrupt enable flip-flop, (IFF)
copLed mlo the P/V flag
For an expianatlOn of Ilag notatIOn and symbols lor
mnemOnlC tables, see Symbohc Nolallon sechon
followmg tables
X
X
II 101
01 010
II 101
01 OIl
II 101
01000
II 101
01001
101
III
101
III
101
III
101
III
ED
57
ED
5F
ED
47
ED
4F
IS
2001-001
IS-Bit Load
Group
Symbolic
Operation
Mnemonic
Flags
5
Z
dd - nn
LO dd, nn
H
X
P/V N
C
Opcoda
76 543 21D Hex
X
00 ddO 001
LD IX,
nn
IX -
nn
X
X
LD lY,
nn
lY -
nn
X
· ·
11 III 101 FD
00 100 001 21
H - (nn+1)
L - (nn)
X
X
ddH - (nn+l)
X
X
LD HL, Inn)
LD dd, (nn)
-n00 101 010 2A
11 101 101 ED
01 ddl 011
ddL - Inn)
IXH - (00+ I)
LD IX, Inn)
X
IXL - Inn)
·
LD IY, Inn)
IYH - (no+ 1)
IYL - Inn)
X
X
LD Inn), HL
(no+l) - H
X
X
(nn) -
LD Inn), dd
LD (nn), IY
(nn+ 1) -
X
IYH
X
LD SP, IY
SP - IY
X
PUSH qq
ISP-2) - qqL
ISP- I) - qqH
SP-SP-2
ISP-2) - IXL
ISP- I) - IXH
SP-SP-2
ISP-2) - IYL
(SP-I) - IYH
SP-SP-2
qqH - ISP+ I)
qqL - ISP)
SP-SP+2
IXH - ISP+ I)
IXL - (SP)
SP-SP+2
IYH - (SP+ I)
IYL - (SP)
SP-SP+2
X
POP IX
FOPIY
NOTES
dd
IS
qq IS
·
X
X
SP - HL
SP - IX
POPqq
II 101 101 ED
01 ddO 011
X
(nn) - IYL
PUSH IY
-n00 100 010 22
ddL
Inn+ I) - IXH
Inn) - IXL
PUSH IX
11 III 101 FD
00 101 010 2A
14
Commont.
dd
Pair
01
10
11
DE
HL
SP
QOllC-
14
16
20
20
20
N
00
16
C
LD Inn), IX
LD SP, HL
LD SP, IX
·
Stal ••
L
(nn+ 1) - ddH
(nn) -
-n11011 101 DD
00 101 010 2A
X
Cycl••
10
-n11 011 101 DD
00 100 001 21
X
Ho.of No.ol M Ho.ol T
Byt••
·
X
X
X
· ·
·
X
X
20
-n11 Oil 101 DD
00 100 010 22
20
-nII 111 101 FD
00 100 010 22
20
11
11
11
11
11
II
-nIII 001
Oil 101
III 001
I II 101
III 001
qqO 101
F9
DD
F9
FD
F9
t"l
IV
c:::I
6
10
10
II
X
X
1I OIl 101 DD
11 100 101 E5
IS
X
X
11 III 101 FD
11 100 101 E5
IS
X
X
11 qqD 001
10
X
X
11 Oil 101 DD
11 100 001 EI
14
X
X
11 III 101 FD
11 100 001 EI
14
~
00
01
10
11
BC
DE
HL
AF
any of the register pdlrs BC, DE, HL, SP.
any of the regIster pcHrS AF, BC. DE, HL
(PAIR1H. (PAIR1L refer to high order and low order eight bits of the register pel1r respecllvely,
e g, BeL"" C, AFH "" A
Exchange.
Block
Transfer.
Block Search
Groups
EX DE, HL
EX AF, AF'
EXX
EX (SP), HL
EX (SP), IX
EX ISP), IY
LDI
LDIR
NOTE
2001-001
CI)P/V flag
DE - HL
AF - AF'
BC - BC'
DE - DE'
HL - HL'
H-ISP+I)
L - ISP)
IXH - ISP+ I)
IXL - ISP)
IYH - ISP+ I)
IYL - (SP)
X
X
X
X
X
X
II 101 Oil EB
00 001 000 08
II Oil 001 D9
X
X
II 100 Oil E3
19
X
X
X
11
II
11
11
DD
E3
FD
E3
23
X
11 101 101 ED
10 100 000 AD
16
Load (HL) mto
II 101 101 ED
10 110 000 BO
21
16
(DE), mcrement
the pomters and
decrement the byte
counter (Be)
JlBC ,,0
II BC ~O
auxlhary register
bank exchange
.
1
171_~ol
A
(HL)
I
X
0
X
P
0
11 101 101
01 101 III
ED
6F
18
Rotate dlgll left and
rlqht between
the accumulator
I
X
0
X
P
0
II 101 101
01 100 III
ED
67
18
The content of the
dnd locatIOn (HL)
upper half of
the accumulator
unaffected
BIT b, r
Z -
rb
x
X
X
X
BIT b, (HL)
Z - (HL)b
X
X
X
X
0
BIT b, (IX+d)b Z - (IX+d)b
X
X
X
X
a
BIT b, (lY+d)b Z - (IY+d)b
X
X
X
0
11
01
11
01
II
II
01
001
b
001
b
011
001
d
b
011 CB
011 CB
110
101 DD
011 CB
110
12
20
11 111 101 FD
11 001 011 CB
d 01 b 110
20
IS
r
Reg
~
001 C
010 0
011 E
100 H
101 L
III A
b
Bll Tested
000 0
001 1
010 2
011 3
100
101
lID
SET b, r
fb -
x
I
x
x
SET b, (HL)
(HL)b -
SET b, (lX+d)
(lX+d)b -
1
X
•
SET b, (lY + d)
(lY + d)b -
1
X
•
RES b, m
mb - 0
X
•
I
X
III
11 001 011 CB
IIlI
11
IIlI
11
II
-
IIlI
m
&:
T,
11
11
-
IIlI
llil
(HL),
b
001
b
011
001
d
b
III
001
d
b
011
110
101
011
110
lOl
011
110
CB
15
DO
CB
23
FD
CB
23
To form new
opcode replace
[ill of SET b, 5
WIth [QJ Flags
and hme slales for
(lX+dl.
OY +d)
SET lnstruchon
NOTES
Jump
Group
IP nn
PC - nn
IP cc, nn
If condition cc
true PC - nn,
otherWise
conhnue
JR e
PC - PC+e
X
IRC, e
11 C
= 0,
X
IP (HL)
continue
11 C = 1,
PC - PC+e
11 C = 1,
contmue
11 C = 0,
PC - PC+e
11 Z = 0
contmue
)f Z = I,
PC - PC+e
)f Z = L
conhnue
)f Z = 0,
PC - PC+e
PC - HL
IP (IX)
PC - IX
JR NC, e
IP Z, e
IR NZ, e
14
The notatIon mb mdlcates bIt b (0 10 7) or locdhon m
IS
X
X
11 000 all C3
10
X
11
010
10
X
00
00
-
OIl 000 18
1?-2 III 000 38
e-2 -
12
If condlhon not met
12
.
12
00 101 000 28
- e-2 -
X
00 IDO 000 20
- e-2 -
X
X
11 101 001
X
X
II 011 101 DO
11 101 001 E9
X
.
If condllion
IS
met.
If condltlOn not met
00 110 000 30
- e-2 -
X
cc
Condition
000 NZ n~
001 Z zero
010 NC non-carry
011 C carry
100 PO panty odd
101 PE panty even
110 P sign poslhve
III M sign negahve
If condlhon
IS
met
If ,-ondltIon not met
12
If condition
]S
met
If condlhon not met
3 .
12
11 condlhon
IS
met
E9
2001-001
Jump Group
(Continued)
Symbollc
OperatIon
Mnemonic
IP (lY)
DJNZ, e
Flags
P/V N
H
S
PC - IY
X
B - B-1
= 0,
X
·
C
X
Opcod.
16 543 210 Hu
No.ol
Byt••
No.of M No.oJ T
Cycl•• Slat..
II III 101 FD
II 101 001 E9
00 010 000 10
X
If B
Comment,
If B
= O.
- e-2 -
continue
13
If B" 0,
If B " O.
PC - PC+e
NOTES
Call and
Return Group
e representa the extemlon In the relal1ve addressing- mode.
a Is /I !l1g-ned t .... o', complement number In the fllnQe < -126, 129 >
e -2 In the opcode provides an elfectlve dddresa of pc + e as PC Is Incremented
by:2 prior 10 the IIddl\!on 01 e
CALL nn
(SP-I) - PCH
(SP-2) - PCL
X
· ·
)) 001 )01 CD
17
X
· ·
II cc 100
10
If cc
IS
false
17
If cc
IS
true.
If cc
IS
false
PC - nn
CALL ce, nn
If condition
cc is fa.lse
X
X
contInue,
otherwise same as
CALL nn
RET
PCL - (SP)
PCH - (SP+ l)
X
X
II 001 001 C9
RET cc
If condlhon
cc IS false
contmue,
otherwise
X
X
II cc 000
10
!!oil
II
RET
RETI
Return from
X
X
RETNI
Return from
non-maskable
Interrupt
X
X
RST p
(SP-I)
(SP-2)
PCH PCL -
X
· ·
mterrupt
NOTE
Input and
Output Group
- PCH
- PCL
0
X
101
001
101
000
10l
101
101
101
II
t
III
ED
4D
ED
45
14
14
II
CC 15
cc
000
001
010
011
100
101
110
III
!N A, (n)
A - (n)
X
X
IN"IC)
, - (C)
If r = 110 only the
flags Will be affected
X
X
P
!NIH
!ND
INDR
d
OOH
OSH
10H
ISH
20H
2SH
30H
38H
0
II 011 011 DB
n
II 101 101 ED
01
000
-
II
-
12
,
n to Ao - A7
Ace to AS - A15
eta Ao - A7
BtoAs - Al5
nable flip. flop (IFF) IS copied mto the P/V flag
The state of bit b of location S IS copied lOla the Z flag
Symbol
Operation
SIgn flag, S = I If the MSB of the result IS 1.
S
Zero flag, Z = I if the result of the operation IS O.
Z
Panty or overflow flag, Panty (P) and overflow
P/V
(V) share the same flag, LogIcal operations affect
this flag WIth the panty of the result whde
arithmetic operations affect thIS flag WIth the
overflow of the resulL If PIV holds panty, PIV
I If the result of the operation IS even, PIV = 0 If
result IS odd, If PIV holds overflow, PIV = I If
the result of the operatIOn produced an overflow,
Half-carry flag, H = I If the add or subtract
H
operation produced a carry mto or borrow from
bIt 4 of the accumulator.
Add/Subtract flag, N = I If the prevIOus operaN
hon was a subtract.
Hand N flags are used In coni unction WIth the
H&N
deCImal adjust instruction (DAA) to properly carrect the result Into packed BCD format followmg
addItion or subtrachon usmg operands WIth
packed BCD formaL
Carry/Lmk flag, C = I If the operatIOn produced
C
a carry from the MSB of the operand or resulL
*"
Symbol
I
0
I
X
V
P
ss
11
R
n
nn
Operation
The flag IS affected according to the result of the
operabon.
The flag IS unchanged by the operation,
The flag IS reset by the operatIOn.
The flag IS set by the operatIOn,
The flag IS a "don't care"
P/V f1dg affected according to the overflow result
of the operatIon.
PIV flag affeeled accordmg to the panty result of
the operatIOn.
Anyone of the CPU regIsters A, B, C, D, E, H, L.
Any B·blt location for all the addressmg modes
allowed for the partIcular mstructIon.
Any 16-blt locatIOn for all the addreSSing modes
allowed for that instructIOn.
Anyone of the two Index regIsters IX or IY.
Refresh counter.
B·blt value In range < 0, 255 >.
16· bIt value In range < 0, 65535 >.
2001·001
Pin
Descriptions
Ao-A1S. Address Bus (output, achve H1gh,
3-state). Ao-AI5 form a 16-b1t address bus. The
Address Bus prov1des the address for memory
data bus exchanges (up to 64K bytes) and for
1/0 device exchanges.
BUSACK. Bus Acknowledge (output, achve
Low). Bus Acknowledge md1cates to the
requeshng dev1ce that the CPU address bus,
data bus, and control slgnals MREQ, IORQ,
RD, and WR have entered their highimpedance states. The external c1rcuitry
can now control these lines.
BUSREQ. Bus Request (input, active Low).
Bus Request has a higher pnonty than NMI
and 1S always recognized at the end of the current machme cycle. BUSREQ forces the CPU
address bus, data bus, and control slgnals
MREQ, IORQ, RD, and WR to go to a h1ghimpedance state so that other dev1ces can
control these lmes. BUSREQ is normally W1reORed and reqUlres an external pullup for
these applicahons. Extended BUSREQ
penods due to extens1ve DMA operahons can
prevent the CPU from properly refreshmg
dynamic RAMs.
00-07' Data Bus (input/output, active High,
3-state). Do-D7 constitute an 8-bit bidirectional
data bus, used for data exchanges with
memory and 110.
HALT. Halt State (output, active Low). HALT
indicates that the CPU has executed a Halt
instruction and is awaiting either a nonmaskable or a maskable interrupt (with the
mask enabled) before operation can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.
INT. Interrupt Request (mput, active Low).
Interrupt Request 1S generated by I/O devices.
The CPU honors a request at the end of the
current instruction if the internal softwarecontrolled interrupt enable flip-flop (IFF) is
enabled. INT is normally wire-ORed and
requires an external pullup for these
applications.
IORQ. Input/Output Request (output, active
Low, 3-state). IORQ indicates that the lower
half of the address bus holds a valid I/O
address for an 1/0 read or wnte operation.
IORQ is also generated concurrently with Ml
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be
placed on the data bus.
MI. Machme Cycle One (output, active Low).
Ml, together with MREQ, ind1cates that the
current machme cycle is the opcode fetch
cycle of an instruction execution. Ml, together
w1th IORQ, md1cates an interrupt acknowledge
cycle.
MREQ. Memory Request (output, achve
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.
NMI. Non-Maskable Interrupt (input, active
Low). NMI has a h1gher priority than INT. NMI
is always recognized at the end of the current
instruction, independent of the
status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at
location 0066H.
RD. Memory Read (output, achve Low,
3-state). RD indicates that the CPU wants to
read data from memory or an I/O device. The
addressed 1/0 device or memory should use
th1S signal to gate data onto the CPU data bus.
RESET. Reset (input, achve Low). RESET
initiahzes the CPU as follows: 1t resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the mterrupt status
to Mode O. Durmg reset hme, the address and
data bus go to a high-impedance state, and all
control output slgnals go to the inactive state.
Note that RESET must be achve for a mmimum
of three full clock cycles before the reset
operation is complete.
RFSH. Refresh (output, achve Low). RFSH,
together w1th MREQ, indlCates that the lower
seven bits of the system's address bus can be
used as a refresh address Jo the system's
dynam1c memones.
WAIT. Wait (input, active Low). WAIT
mdicates to the CPU that the addressed memory or I/O devices are not ready for a data
transfer. The CPU conhnues to enter a Wait
state as long as th1s slgnal is active. Extended
WAIT periods can prevent the CPU from
refreshmg dynamic memory properly.
WR. Memory Wnte (output, achve Low,
3-state). WR mdlCates that the CPU data bus
holds valid data to be stored at the addressed
memory or I/O locahon.
17
CPU Timing
The Z80 CPU executes instructions by proceeding through a specific sequence of operahons:
The basIc clock period is referred to as a
T hme or cycle, and three or more T cycles
make up a machine cycle (Ml, M2 or M3 for
Instance). Machine cycles can be extended
mther by the CPU automahcally inserting one
or more Walt states or by the Insertion of one
or more Walt states by the user.
• Memory read or write
• I/O devIce read or write
• Interrupt acknowledge .'.
Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). ApproxImately one-half clock cycle later,
MREQ goes achve. The falling edge of MREQ
can be used directly as a ChIp Enable to dynamic memones. When achve, RD indICates that
the memory data can be enabled Ol;tO the CPU
T,
. data bus.
The CPU samples the WAIT input with the
rising edge of clock state T3. During clock
states T3 and T4 of an Ml cycle dynamic RAM
refresh can occur while the CPU starts
decoding and executing the Instruction. When
the Refresh Control sIgnal becomes achve,
refreshmg of dynamic memory can take place.
Tw
T,
CLOCK
AO-A15
WAIT
--!---'
--+---------4--L~)~
««
RFSH
----O/f'-----l----r"
f-@-@
;---
-------'
NOTE' Tw-Walt cycle added when necessary for slow ancllbary devices
Figure 5. Instruction Opcode Fetch
18
2005-882
CPU
Timing
(Continued)
Memory Read or Write Cycles. FIgure 6
bus is stable, so that it can be used directly as
a Chip Enable for dynamic memories. The WR
line IS active when the data bus IS stable, so
that it can be used directly as an R/W pulse to
most semiconductor memones.
shows the timing of memory read or write
cycles other than an opcode fetGh (MI) cycle.
The MREQ and RD sIgnals funchon exactly as
In the fetch cycle. In a memory write cycle,
MREQ also becomes active when the address
T,
T,
Tw
T,
CLOCK
Ao-A15
OPERA~~~:
~--J~~-----H-7'-----H-7'-----H--~-J.~-
liD
1
00- 0 7
/
______-+__________~II.-~----~~------.I~~------WR
OPER:;:~:
1
0
00- 7
--------t==========~==~D~AT~A~O~U~T=============l
Figure 6. Memory Read or Write Cycles
2005-883
19
CPU
Timing
(Continued)
Input or Output Cycles. Figure 7 shows the
hming for an 1/0 read or 1/0 write operatIon.
Durmg 1/0 operatIons, the CPU automatically
Tw'
mserts a single Walt state (Tw). ThiS extra Walt
state allows sufficient hme for an I/O port to
decode the address and the port address lines.
Tw
CLOCK
AO-A
1
ViR
WRII~~
OPERATION
NOTE. Tw*
=
OO-D7
___________
<=================~======~~~=======>
DATA OUT
One Walt cycle automatJcally Inserted by CPU.
Figure 7. Input or Output Cycles
Interrupt Request/Acknowledge Cycle. The
CPU samples the mterrupt signal with the riSing edge of the last clock cycle at the end of
any mstruction (Figure 8). When an mterrupt
is accepted, a special Ml cycle is generated.
During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. The CPU automatically adds two
Wait states to this c;ycle.
-+__,~--------------p~C--_r------_H-f.~----~--H_-J.)----
AO-A15 ____________
-+__________________________
WAIT ____________
NOTE- 1) IL = Last state of prevIOUS Instruction.
~~--~--'
2) Two Walt cycles automahcally Inserted by CPU(*),
Figure 8. Interrupt Request/Acknowledge Cycle
20
2005·884, 885
CPU
Timing
(Continued)
Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the
maskable interrupt input INT but has higher
priority and cannot be disabled under software
contro!' The subsequent timing is similar to
that of a normal memory read operation except
that data put on the bus by the memory IS
Ignored. The CPU instead executes a restart
(RST) operahon and jumps to the NMI service
routine located at address 0066H (Figure 9).
CLOCK
+/}-!-______-+-'f_ _ _ _ _t-_+____t'
AO-A1S _ _ _ _ _ _ _ _ _ _
• Although NMI 15 an asynchronous mput, to ~antee Its bemg
recogmzed on the followmg machme cycle, NMl's fallmg edge
must occur no later than the nsmg edge of the clock cycle
precedmg TLAST.
Figure 9. Non-Maskable Interrupt Request Operation
Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock period of any machine cycle (Figure
10). If BUSREQ is active, the CPU sets its
address, data, and MREQ, IORQ, RD, and WR
lines to a high-impedance state with the rising
edge of the next clock pulse. At that time, any
external devICe can take control of these lines,
usually to transfer data between memory and
1/0 devices.
"
AO-A15
"
==========j=}---1_---!!2.~----_+_{
@-
---------------+------------------~,
-®RFSH
---------------+~
-t_______"_N_CH_A_NG_'_D_ _ _ _ _ __
HALT _ _ _ _ _ _ _ _ _ _
NOTE: TL = Last state of any M cycle.
TX = An arbItrary clock cycle used by requesting device.
Figure 10. Bus Request/Acknowledge Cycle
2005·0218, 886
21
CPU
Timing
(Continued)
Halt Acknowledge Cycle. When the CPU
receives a HALT instruction, it executes NOP
states until either an INT or NMI input is
M1
..
~
I ..
received. When in the Halt state, the HALT
output is active and remains so until an interrupt is processed (Figure Il).
M1
~
~
~
~
"1 •
~
M1
~
CLOCK~
~
~
r "
HALT
Halt Instruction
Rece,ved
~------------------
HMO
NOTE: INT will also force a Halt
·See note, Figure 9.
eXlt.
Figure I!. Halt Acknowledge Cycle
Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept it. As long as RESET remains active, the
address and data buses float, and the control
outputs are inachve. Once RESET goes
inactive, two internal T cycles are consumed
before the CPU resumes normal processing
operation. RESET clears the PC register, so the
hrst opcode fetch will be to location 0000
(Figure 12).
_MI-----T,
T,
CLOCK
AO-A15-------------------------------r~~--~r----------~~------------~~~----------------
-----@~M1
FLOAT
~--------------------------+_-------------------
Do-D7
/
--------~------------~
l!R~
R~~------------Lr,7~Z~Z~/~Z~7~--~h~------------------~\----~-----
BU~~s.,,:<
- ----
. '------------
HALT
Figure 12. Reset Cycle
22
2005·887, 888
AC
Characteristics
Number Symbol
Z80 CPU
Min Max
Z80ACPU
Min Max
Z80B CPU
Min Max
Parameter
(ns)
(ns)
(ns)
(ns)
TcC
Clock Cycle Time
400'
250'
2
TwCh
Clock Pulse Width (H,gh)
180'
110'
3
4
TwCl
TfC
Clock Pulse W,dth (Low)
180
5-TrC
2000
110
(ns)
(ns)
165'
65'
2000
65
2000
Clock Fall Time
30
30
20
Clock Rise Time
30
30
110
90
6
TdCr(A)
Clock 1 to Address Valid Delay
7
TdA(MREQf)
Address Valid to MREQ
j Delay
8
TdCf(MREQf)
Clock
9
10 -
TdCr(MREQr)
Clock 1 to MREQ 1 Delay
TwMREQh - - MREQ Pulse W,dth (H,gh) - - - 170'
11
TwMREQl
MREQ Pulse W,dth (Low)
12
TdCf(MREQr)
13
TdCf(RDf)
Clock
Clock
j
j
j
to MREQ
j
145
125'
Delay
65'
TdCr(RDr)
Clock 1 to RD 1 Delay
14
15 -TsD(Cr) - - - Data Setup T,me to Clock 1- - - 50
35'
100
85
100
85
110'
360'
to MREQ 1 Delay
to RD j Delay
20
220'
70
70
65'-135'
100 .
85
70
130
95
80
100
85
35
70
30---
a
a
a
16
17
ThD(RDr)
TsWA!T(Cf)
Data Hold T,me to RD 1
18
ThWAIT(Cf) .
WAIT Hold T,me after Clock
a
a
a
19
TdCr(Mlf)
Clock 1 to Ml I Delay
130
100
80
WAIT Setup T,me to Clock I
70
j
70
60
20 -
TdCr(Mlr) - - Clock 1 to Ml 1 Delay
130
100
80
21
TdCr(RFSHf)
Clock 1 to RFSH I Delay
180
130
110
22
TdCr(RFSHr)
Clock 1 to RFSH 1 Delay
150
120
100
23
TdCf(RDr)
Clock I to RD 1 Delay
110
85
70
24
25 -
TdCr(RDf)
Clock 1 to RD I Delay
100
85
26
TsD(Cf) - - - Data Setup to Clock I durmg - - 60
M2 , M3, ~ or Ms Cycles
320'
TdA(IORQf)
Address Stable prior to IORQ I
27
TdCr(IORQf)
Clock 1 to IORQ I Delay
90
75
28
TdCf(IORQr)
Clock
to IORQ 1 Delay
110
85
29
30 -
TdD(WRf)
Data Stable pnor to WR I
31
TwWR
WR Pulse W,dth
TdCf(WRf) - - Clock
j
j
32·
TdCf(WRr)
Clock I to WR 1 Delay
TdD(WRf)
Data Stable pnor to WR I
34
35 -
TdCr(WRf)
Clock 1 to WR I Delay
36
37
38
TdWRr(D) - - Data Stable from WR 1
Clock j to HALT 1 or I
TdCf(HALT)
NMI Pulse Width
TwNMI
TsBUSREQ(Cr) BUSREQ Setup Time to Clock 1
*For clock periods other than the mmImums shown
calculate parameters usmg the expressions
followmg page.
in
In
180'
70
135'
80
100
-10'
70
-55'
65
80
120'
70
25'
220'
20'
65
80
90
360'
70
40--110'
80'
190'
to WR I Delay
33
50
60'
60
30'-260
300
300
80
80
70
80
50
50
the table,
the table on the
23
!!oil
CO
C
~
•
d
AC
Characteristics
(C~ntinued)
Number Symbol
Parameter
ThBUSREQ( Cr) BUSREQ Hold Time after Clock 1
39
40-TdCr(BUSACKf)-Clock 1 to BUSACK I Delay
TdCf(BUSACKr) Clock I to BUSACK 1 Delay
41
TdCr(Dz)
42
Clock 1 to Data Float Delay
43
TdCr(CTz)
Clock 1 to Control Outputs Float
Delay (MREQ, lORd, RD,
and WR)
TdCr(Az)
44
Clock 1 to Address Float Delay
45 46
47
48
49
50 51
52
53
Z8D CPU
Min Max
Z8DACPU
Min Max
ZSDB CPU
Min Max
(ns)
(ns)
(ns)
(ns)
0
0
120
110
90
110
110
TdCTr(A) - - - Address Stable after MREQ 1,-- 160'
IORQ 1, RD 1, and WR 1
TsRESET(Cr)
RESET to Clock 1 Setup TIme
90
ThRESET(Cr)
RESET to Clock 1 Hold TIme
TsINTf(Cr)
INT to Clock 1 Setup TIme
80
ThINTr(Cr)
INT to Clock 1 Hold TIme
TdMlf(IORQf) - Ml I to IORQ I Delay
920'
TdCf(!ORQf)
Clock I to IORQ I Delay
TdCf(!ORQr)
Clock 1 to IORQ 1 Delay
TdCf(D)
Clock I to Data Vahd Delay
(ns)
(ns)
0
100
100
90
80
90
90
80
70
90
80
35'--
80'
60
60
0
0
0
80
70
0
0
0
365*--
85
85
150
70
70
130
565*
110
100
230
·For clock perIods other than the minimums shown In the table,
calculate parameters usmg the followmg expressions Calculated
values above assumed Tre = TfC = 20 ns.
Footnotes to AC Characteristics
zao
Number Symbol
2
zaOA
ZSOB
TcC
TwCh + TwCI + TrC + TIC
TwCh + TwCI + TrC +TfC
TwCh + TwCI. + TrC + TIC
TwCh
Although stahc by deSIgn,
TwCh of greater than 200 pos
Although stahc by deSIgn,
TwCh of greater than 200 pos
Although stahc by deSIgn,
TwCh of greater than 200 pos
IS
not guaranteed
IS
not guaranteed
IS
not guaranteed
7 ' - TdA(MREQf) - TwCh + TIC - 75 - - - - TwCh + TIC - 65 - - - - TwCh + TIC - 50 - - - TwMREQh
10
TwCh + TfC - 30
TwCh + TIC - 20
TwCh + TIC - 20
II
TwMREQI
TcC - 40
TcC - 30
TcC - 30
26
TdA(IORQ!)
TcC - 80
TcC - 70
TcC - 55
29
TdD(WRf)
TcC - 210
TcC - 170
TcC - 140
3 1 - TwWR - - - TcC - 40 - - - - - - - TcC - 30
TcC - 30 - - - - - - -
33
TdD(WRf)
TwCI + TrC - 180
TwCI + TrC - 140
TwCI + TrC - 140
TwCI + TrC - 55
35
TdWRr(D)
TwCI + TrC - 80
TwCI + TrC - 70
45
TdCTr(A)
TwCI + TrC - 40
TwCI + TrC - 50
TwCI + TrC - 50
50
TdMlf(lORQf) 2TcC + TwCh + TfC - 80
2TcC + TwCh + TfC - 65
2TcC + TwCh + TIC - 50
AC Test Conditions:
VIH = 2.0 V
VIL = 0.8 V
VIHe = Vee -0.6 V
VILe = 0.45 V
24
VOH = 20V
VOL = 0.8 V
FLOAT = ±05V
Absolute
Maximum
Ratings
Storage Temperature ........ -65°e to +150 oe
Temperature
under Bias ........ Specified operatmg range
Voltages on all mputs and
outputs with respect to ground. -0.3 V to + 7 V
Power Disslpahon .................... 1.5 W
Standard
Test
Conditions
The characteristics below apply for the
following standard test condlhons, unless
otherwIse noted. All voltages are referenced to
GND (0 VJ. Posihve current flows into the
referenced pm. AvaIlable operating
temperature ranges are:
Stresses greater than those hsted under Absolute MaxI·
mum Ratmgs may cause permanent damage to the devlce.
Th,s IS a stress rating only; operation of the devIce at any
condItion above those mdICated m the operational sections
of these speClhcahons IS not Imphed. Exposure to absolute
maxImum ratmg condItions for extended perlOds may affect
devIce rehablhty.
All ac parameters assume a load capacitance
of 50 pF. Add 10 ns delay for each 50 pF
increase in load up to a maximum of 200 pF
for the data bus and 100 pF for address and
control lmes.
+5V
• ooe to +70 oe,
+4.75 V :5 Vee:5 +5.25 V
• -40 oe to +85°e,
+4.75 V :5 Vee :5 +5.25 V
• -55°e to + 125°e,
+4.5 V :5 Vee :5 +5.5 V
2.2K
IN!
GO
C
f'2
Itt
c::::
DC
Characteristics
Symbol
VILe
VIHe
VIL
VIH
VOL
VOH
Icc
ILl
ILEAK
Parameter
Clock Input Low Voltage
Clock Input HIgh Voltage
Input Low Voltage
Input HIgh Voltage
Output Low Voltage
Output HIgh Voltage
Power Supply Current
280
zaOA
280B
Input Leakage Current
3·State Output Leakage Current in Float
1 For military grade parts. ICC IS 200 rnA
2 TYPical rate for Z80A IS 90 rnA.
Capacitance
Symbol
Parameter
Clock CapaCItance
Input CapacItance
Output CapacItance
8085·0221
Min
Max
-0.3
0.45
Vee-· 6 Vee +.3
-0.3
0.8
2.0
Vee
0.4
2.4
150'
200 2
200
-10
AI5-AO. 07-00.
Min
10
10'
Unit
Test Condition
V
V
V
V
V
V
IOL= 1.8 rnA
IOH = -250 p.A
rnA
rnA
rnA
p.A
p.A
MREQ. IORQ. RD.
Max
Unit
35
5
10
pF
pF
pF
VIN = 0 to Vee
Vour = 0.4 to Vee
and
WR.
Note
Unmeasured pins
returned to ground
25
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Temp
Speed
Description
Z8400
CE
2.5 MHz
Z80 CPU (40-pm)
Z8400A
DE
4.0 MHz
Z80A CPU (40-pm)
Z8400
CM
2.5 MHz
Same as above
Z8400A
DS
4.0 MHz
Same as above
Z8400
CMB
2.5 MHz
Same as above
Z8400A
PE
4.0 MHz
Same as above
Z8400
CS
2.5 MHz
Same as above
Z8400A
PS
4.0 MHz
Same as above
Z8400
DE
2.5 MHz
Same as above
Z8400B
CE
6.0 MHz
Z80B CPU (40-pm)
Z8400
DS
2.5 MHz
Same as above
Z8400B
CM
6.0 MHz
Same as above
Z8400
PE
2.5 MHz
Same as above
Z8400B
CMB.
6.0 MHz
Same as above
Z8400
PS
2.5 MHz
Same as above
Z8400B
CS
6.0 MHz
Same as above
Z8400A
CE
4.0 MHz
Z80A CPU (40·pm)
Z8400B
DE
6.0 MHz
Same as above
Z8400A
CM
4.0 MHz
Same as above
Z8400B
DS
6.0 MHz
Same as above
Z8400A
CMB
4.0 MHz
Same as above
Z8400B
PE.
6.0 MHz
Same as above
Z8400A
CS
4.0 MHz
Same as above
Z8400B
PS
6.0 MHz
Same as above
NOTES. C = Ceramic, D = CerdlP. P = Plashc; E = -40'C to +85'C. M = -55'C to + l25'C. MB = -55'C to + l25'C With
MIL·STD·883 Class B processmg, S
26
=
O°C to + 70°C
Z8410
Z80® DMA Direct
Memory Access Controller
~
Zilog .
Product
Specification
March 1981
Features
General
DeSCription
address registers. An entire previous
sequence can be repeated automatically.
• Transfers, searches and search/transfers in
Byte-at-a-Time, Burst or Continuous modes.
Cycle length and edge timing can be programmed to match the speed of any port.
• Extensive programmability of functions.
Cp'U can read complete channel status.
• Dual port addresses (source and destination)
generated for memory-to-I/O, memoryto-memory, or I/O-to-I/O operations.
Addresses may be fixed or automatically
incremented!decremented.
• Standard Z-80 Family bus-request and
prioritized interrupt-request daisy chains
implemented without external logiC.
Sophisticated, internally modifiable interrupt vectoring.
• Next-operation loading without disturbing
current operations via buffered starting-
• Direct interfacing to system buses without
external logic.
The Z-80 DMA (Direct Memory Access) is a
powerful and versatile device for controlling
and processing transfers of data. Its bdsic
function of managing CPU-independent
transfers between two ports is augmented by
an array of features that optimize transfer
speed and control with little or no external
logic in systems using an 8- or 16-bit data bus
and a 16-bit address bus.
Transfers can be done between any two ports
(source and destination), including memory-toI/O, memory-to-memory, and I/O-to-I/O. Dual
port addresses are automatically generated for
each transaction and may be either fixed or
incrementing/decrementing. In addition, bitmaskable byte searches can be performed
either concurrently with transfers or as an
operation in itself.
..
...
..
..
I
!
A,
A,
SYSTEMl
DATA
BUS
A,
A,
SVSTI!M
ADDRISS
BUS
A,
BUS {
CONTROL
ZeGDIlA.
SYSTEM!
CONTROL
A,
A"
elK
A"
A"
A"
A"
A"
Wll
"DY
cEIWAiT
BUS
..
.
..
.5.
Do
D.
IolREU
lAO
DM"
} CONTROL
OOIPirCiE
INTI!RRUPT
} CONTROL
IiAl
0,
BUSREQ
CElWAIT
iii
A"
lEO
A"
A"
GND
elK
Figure 1. PID FUDclioDS
2032-0125, 0126
A"
A"
Figure 2. PID Ass1gDmeDts
27
General
Description
(Continued)
The Z-80 DMA contains direct interfacing to
and independent control of system buses, as
well as sophisticated bus and interrupt controls. Many programmable features, including
variable cycle timing and auto-restart,
minimize CPU software overhead. They are
especially useful in adapting this special-
purpose transfer processor to a broad variety
of memory, IIO and CPU environments.
The Z-80 DMA is an n-channel silicon-gate
depletion-load device packaged in a 40-pin
plastic or ceramic DIP. It uses a single +5 V
power supply and the standard Z-80 Family
single-phase clock.
Functional
Description
Classes of Operation. The Z-80 DMA has
three basic classes of operation:
During a search-only operation, data is read
from the so~rce port and compared byte by
byte with a DMA-internal register containing a
programmable match byte. This match byte
may optionally be masked so that only certain
bits within the match byte are compared.
Search rates up to 1.25M bytes per second can
be obtained with the 2.5 MHz Z-80 DMA or 2M
bytes per second with the 4 MHz Z-80A DMA.
In combined searches and transfers, data
is transferred between two ports while
simultaneously searching for a bit-maskable
byte match.
Data transfers or searches can be programmed to stop or interrupt under various
conditions. In addition, CPU-readable status
bits can be programmed to reflect the
condition.
Modes of Operation. The Z-80 DMA can be
programmed to operate in one of three transfer
and/or search modes:
• Transfers of data between two ports (memory
or I/O peripheral)
• Searches for a particular 8-bit maskable
byte at a single port in memory or an IIO
peripheral
• Combined transfers with simultaneous
search between two ports
Figure 4 illustrates the basic functions
served by these classes of operation.
During a transfer, the DMA assumes control
of the system address and data buses. Data is
read from one addressable port and written to
the other addressable port, byte by byte. The
ports may be programmed to be either system
main memory or peripheral IIO devices. Thus,
a block of data may be written from one
peripheral to another, from one area of main
memory to another, or from a peripheral to
main memory and vice versa.
SYSTEM
BUSES
cPU_
INT
r
A.
j..
'f
"
.....L.
-
DMA
-
INT
RDY
lEI
• Byte-at-a-Time: data operat'ons are performed one byte at a time. Between each
byte operation the system buses are released
to the CPU. The buses are requested again
for each succeeding byte operation.
• Burst: data operations continue until a
port's Ready line to the DMA goes inactive.
The DMA then stops and releases the system
buses after completing its current byte
operation.
• Continuous: data operations continue until
the end of the programmed block of data is
reached before the system buses are
released. If a port's Ready line goes inactive
before this occurs, the DMA simply pauses
until the Ready line comes active again.
Z·80DMA
SIO
JA.
lEO
iNi
I
lEI
RDY
DMA
J...
~
Figure 3. Typical Z-80 Envlroament
?R
1
2.
3.
4
5
Search memory
Transfer memory·lOomemory (optional search)
Transf.r memory·to-I/O (optional •• arch)
Search UO •
Transf.r 110·10-110 (optional •• arch)
Figure ol. Basic Functions of the Z-80 DNA
2032·0127.0128
Functional
Description
(Continued)
In all modes, once a byte of data is read mto
the DMA, the operation on the byte w!ll be
completed m an orderly fashIon, regardless of
the state of other signals (includmg a port's
Ready lme).
Due to the DMA's hIgh-speed buffered
method of reading data, operahons on one
byte are not completed unhl the next byte is
read in. ThIs means that total transfer or
search block lengths must be two or more
bytes, and that block lengths programmed into
the DMA must be one byte less than the
deSIred block length (count IS N-l where N is
the block length).
Commands and Status. The Z-80 DMA has
several wntable control registers and readable
status regIsters available to the CPU. Control
bytes can be written to the DMA whenever the
DMA is not controllmg the system buses, but
the act of wntmg a control byte to the DMA
disables the DMA unhl it IS agam enabled by a
specific command. Status bytes can also be
read at any such hme, but wntmg the Read
Status Byte command or the Imtiate Read
Sequence command disables the DMA.
Control bytes to the DMA Include those
whICh effect ImmedIate command achons such
as enable, dIsable, reset, load startmg-address
buffers, conhnue, clear counters, clear status
bIts and the like. In addihon, many modesetting control bytes can be written, includmg
mode and class of operahon, port configuration, starhng addresses, block length, address
counting rule, match and match-mask byte,
Interrupt condlhons, Interrupt vector, statusaffects-vector condlhon, pulse countmg, auto
restart, Ready-line and Walt-line rules, and
read mask.
Readable status registers Include a general
status byte reflectmg Ready-lme, end-of-block,
byte-match and mterrupt condihons, as well as
2-byte registers for the current byte count,
Port A address and Port B address.
Variable Cycle. The Z-80 DMA has the
unique feature of programmable operahoncycle length. This is valuable m tailoring the
DMA to the parhcular reqUIrements of other
system components (fast or slow) and maximizes the data-transfer rate. It also eliminates
external logic for signal condltionmg.
There are two aspects to the variable cycle
feature. FIrst, the enhre read and wnte cycles
(penods) assocIated v,:lth the source and
destinahon ports can be independently programmed as 2, 3 or 4 T-cycles long (more if
Wait cycles are used), thereby Increasmg or
2032·0129
decreasmg the speed WIth whICh all DMA
sIgnals change (FIgure 5).
Second, the four sIgnals m each port
speclhcally assocIated wIth transfers of data
(I/O Request, Memory Request, Read, and
Wnte) can each have ItS acllve trallmg edge
termmated one-half T-cycle early. ThIs adds a
further dImensIOn of flexIbIlity and speed,
allowmg such thmgs as shorter-than-normal
Read or Wnte sIgnals that go macllve before
data starts to change.
Address Generation. Two 16-blt addresses are
generated by the Z-80 DMA for every transfer
operahon, one address for the source port and
another for the destmahon port. Each address
can be eIther vanable or hxed. Variable
addresses can mcrement or decrement from
the programmed startmg address. The hxedaddress capabIlity ellmmates the need for
separate enablmg wIres to I/O ports.
Port addresses are mulhplexed onto the
system address bus, dependmg on whether the
DMA IS readmg the source port or wntmg to
the destmahon port. Two readable address
counters (2 bytes each) keep the current
address of each port.
Auto Restart. The startmg addresses of eIther
port can be reloaded automahcally at the end
of a block. ThIs ophon IS selected by the Auto
Restart control bit. The byte counter IS cleared
when the addresses are reloaded.
The Auto Restart feature relieves the CPU of
software overhead for repehhve operahons
such as CRT refresh and many others. Moreover, when the CPU has access to the buses
durmg byte-at-a-llme or burst transfers, different startmg addresses can be wntten mto
buffer regIsters durmg transfers, causmg the
Auto Restart to begm at a new locahon.
Interrupts. The Z-80 DMA can be programmed
to mterrupt the CPU on three condlhons:
• Interrupt on Ready (before requeshng bus)
• Interrupt on Match
• Interrupt on End of Block
-4-2 CYCLE
...... 3 CYCLE
1
04-4 CYCLE
!~EARLYENDING
_~.I
~.
!
FOR CONTROL SIGNALS
"I
Figure 5. Variable Cycle Length
29
Functional
Description
(Continued)
Pin
Description
30
Any of these interrupts cause an interruptpending status bit to be set, and each of them
can optionally alter the DMA's interrupt vector. Due to the buffered constraint mentioned
under "Modes of Operation," interrupts on
Match at End of Block are caused by matches
to the byte just prior to the last byte in the
block.
The DMA shares the Z-80 Family's elaborate
interrupt scheme, which provides fast interrupt service in real-time applications. In a
Z-80 CPU environment, the DMA passes its
internally modifiable 8-bit interrupt vector to
the CPU, which adds an additional eight bits
to form the memory address of the interruptroutine table. This table contains the address
of the beginning of the interrupt routine itself.
Ao-AlS. System Address Bus (output, 3-state).
Addresses generated by the DMA are sent to
both source and destination ports (main
memory or 1/0 peripherals) on these lines.
BAl. Bus Acknowledge In (input, achve Low).
Signals that the system buses have been
released for DMA control. In multiple-DMA
configurations, the BAI pm of the highest
Priority DMA IS normally connected to the Bus
Acknowledge pin of the CPU. Lower-priority
DMAs have their BAI connected to the BAO of
a higher-priOrity DMA.
BAO. Bus Acknowledge Out (output, active
Low). In a multiple-DMA configuration, this
pin signals that no other higher-priority DMA
has requested the system buses. BAI and BAO
form a daiSY cham for mulhple-DMA priority
resoluhon over bus control.
BUSREQ. Bus Request (bidirectional, active
Low, open drain). As an output, it sends
requests for control of the system address bus,
data bus and control bus to the CPU. As an
input, when multiple DMAs are strung
together in a priority daisy chain via BAI and
BAO, it senses when another DMA has
requested the buses and causes this DMA to
refrain from bus requesting until the other
DMA is finished. Because it is a bidirectional
pin, there cannot be any buffers between this
DMA and any other DMA. It can, however,
have a buffer between it and the CPU because
it is unidirectional into the CPU. A pull-up
resistor is connected to this pin.
CE/WAIT. Chip Enable and Wait (input,
active Low). Normally this functions only as a
CE line, but it can also be programmed to
serve a WAIT function. As a CE line from the
CPU, it becomes active when WR and IORQ
are active and the I/O port address on the
In this process, CPU control is transferred
directly to the interrupt routine, so that the
next instruction executed after an interrupt
acknowledge is the first instruction of the interrupt routine itself.
Pulse Generation. External devices can keep
track of how many bytes have been transferred
by using the DMA's pulse output, which provides a signal at 256-byte intervals. The interval sequence may be offset at the beginning by
1 to 255 bytes.
The Interrupt line outputs the pulse signal in
a manner that prevents misinterpretation by
the CPU as an interrupt request, since it only
appears when the Bus Request and Bus
Acknowledge lines are both active.
system address bus is the DMA's address,
thereby allowing a transfer of control or command bytes from the CPU to the DMA. As a
WAIT line from memory or 1/0 devices, after
the DMA ha~ received a bus-request acknowledge from the CPU, it causes wait states
to be inserted in the DMA's operation cycles
thereby slowing the DMA to a speed that
matches the memory or 1/0 device.
CLK. System Clock (mput). Standard Z-80
single-phase clock at 2.5 MHz (Z-80 DMA) or
4.0 MHz (Z-80A DMA). For slower system
clocks, a TTL gate with a pullup resistor may
be adequate to meet the timing and voltage
level specification. For higher-speed systems,
use a clock driver with an active pullup to
meet the VIH specification and risetime
requirements. In all cases there should be a
resistive pullup to the power supply of 10K
ohms (max) to ensure proper power when the
DMA IS reset.
Do-D-,. System Data Bus (bidirectional,
3-state). Commands from the CPU, DMA
status, and data from memory or I/O
peripherals are transferred on these lines.
lEi. Interrupt Enable In (input, active High).
This is used with lEO to form a priority daisy
chain when there is more than one interruptdriven device. A High on this line indicates
that no other device of higher priority is being
serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI is High and the
CPU is not servicing an interrupt from this
DMA. Thus, this signal blocks lower-priority
devices from interrupting while a higherpriority device is being serviced by its CPU
interrupt service routine.
Pin
Description
(Continued)
Internal
Structure
INT/PULSE. Interrupt Request (output, active
Low, open drain). This requests a CPU interrupt. The CPU acknowledges the interrupt by
pulling its IORQ output Low during an MI
cycle. It is typically connected to the INT pin
of the CPU with a pullup resistor and tied to
all other INT pins in the system. This pin can
also be used to generate periodic pulses to an
external device. It can be used this way only
when the DMA is bus master (Le., the CPU's
BUSREQ and BUSACK lines are both Low
and the CPU cannot see interrupts).
IORQ. Input/Output Request (bidirectional,
active Low, 3-state). As an input, this indicates
that the lower half of the address bus holds a
valid I/O port address for transfer of control or
status bytes from or to the CPU, respectively;
this DMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously
active. As an output, after the DMA has taken
control of the system buses, it indicates that
the 8-bit or 16-bit address bus holds a valid
port address for another I/O device involved in
a DMA transfer of data. When IORQ and MI
are both active simultaneously, an interrupt
acknowledge is indicated.
MI. Machine Cycle One (input, active Low).
Indicates that the current CPU machine cycle
is an instruction fetch. It is used by the DMA
to decode the return-from-interrupt instruction
(RET!) (ED-4D) sent by the CPU. During twobyte instruction fetches, MI is active as each
The internal structure of the Z-80 DMA
includes driver and receiver circuitry for interfacing with an 8-bit system data bus, a 16-bit
system address bus, and system control lines
(Figure 6). In a Z-80 CPU environment, the
DMA can be tied directly to the analogous pins
on the CPU (Figure 7) with no additional buffering, except for the CElWAIT line.
The DMA's internal data bus interfaces with
the system data bus and services all internal
logic and registers. Addresses generated from
this logic for Ports A and B (source and destination) of the DMA's single transfer channel
are multiplexed onto the system address bus.
opcode byte is fetched. An interrupt acknowledge is indicated when both MI and
:iORQ are active.
MREQ. Memory Request (output, active Low,
3-state). This indicates that the address bus
holds a valid address for a memory read or
write operation. After the DMA has taken control of the system buses, it indicates a DMA
transfer request from or to memory.
RD. Read (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to read status bytes from the DMA's read
registers. As an output, after the DMA has
taken control of the system buses, it indicates a
DMA-controlled read from a memory or I/O
port. address.
RDY. Ready (input, programmable active Low
or High). This is monitored by the DMA to
determine when a peripheral device associated
with a DMA port is ready for a read or write
operation. Depending on the mode of DMA
operation (Byte, Burst or Continuous), the RDY
line indirectly controls DMA activity by causing the BUSREQ line to go Low or High.
WR. Write (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to write control or command bytes to the DMA
write registers. As an output, after the DMA
has taken control of the system buses, it
indicates a DMA-controlled write to a memory
or I/O port address.
Specialized logic Circuits in the DMA are
dedicated to the various functions of external
bus interfacing, internal bus control, byte
matching, byte counting, periodic pulse
generation, CPU interrupts, bus requests, and
address generation. A set of twenty-one
writable control registers and seven readable
status registers provides the means by which
the CPU governs and monitors the activities of
these logic circuits. All registers are eight bits
wide, with double-byte information stored in
adjacent registers. The two address counters
(two bytes each) for Ports A and B are "buffered
by the two starting addresses.
SYSTEM
DATA 11--'--"'--.1\
BUS
18 BIT]
CONTROL
MUX
u-......-....-v
SYSTEM
ADDRESS
BUS
11e BIT]
\r-----../I
Figure 6. Block Diagram
2032·0130
31
I
!
Internal
Structure
(Continued)
system bus, however, may not be pre-empted.
Any DMA that gains access to the system bus
keeps the bus until it is finished.
The 21 writable control regIsters are
organized into seven base-register groups,
most of whlCh have multiple regIsters. The
base registers in each writable group contain
both control/command bits and pointer bits
that can be set to address other registers withm
the group. The seven readable status registers
have no analogous second-level regIsters.
The registers are designated as follows,
according to theIr base-register groups:
Write Registers
WRO
WRO- WR6 - Write Register groups 0
through 6 (7 base registers plus 14 assocIated registers)
RRO-RR6 - Read RegIsters 0 through 6
WR I
Writing to a register withm a write-register
group involves hrst writing to the base
regIster, with the appropriate pOinter bits set,
then writing to one or more of the other
regIsters within the group. All seven of the
readable status registers are accessed sequenhally accordmg to a programmable mask contained in one of the writable registers. The sechon entitled "Programming" explains this m
more detail.
A plpehning scheme is used for readmg data
in. The programmed block length is the
number of bytes compared to the byte counter,
which increments at the end of each cycle. In
searches, data byte comparisons wIth the
match byte are made during the read cycle of
the next byte. Matches are, therefore, discovered only after the next byte is read m.
In mulhple-DMA conhguratlons, mterruptrequest daisy chams are prioritized by the
order in which theIr IEI and lEO lmes are connected (Zilog Apphcation Note 03-0041-01, The
2-80 Family Program Interrupt Structure). The
WR3
WR2
WR4
WR5
WR6
Base regIster byte
Port A startmg address (low byte)
Port A starting address (hIgh byte)
Block length (low byte)
Block length (hIgh byte)
Base regIster byte
Port A vanable-timmg byte
Base register byte
Port B vanable-hmmg byte
Base regIster byte
Mask byte
Match byte
Base regIster byte
Port B starhng address (low byte)
Port B startmg address (hIgh byte)
lnterrupt control byte
Pulse control byte
Interrupt vector
Base register byte
Base regIster byte
Read mask
Read Registers
RRO
RRI
RR2
RR3
RR4
RR5
RR6
Status byte
Byte counter (low byte)
Byte counter (hIgh byte)
Port A address counter (low byte)
Port A address counter (hIgh byte)
Port B address counter (low byte)
Port B address counter (hIgh byte)
COMMON
iNT
BUSREQ
,-------iBUSACK
Ml
CPU
lORa
MREQ
AD
Wli
ClK
Ao-A15
00-7
FROM HIGHER PRIORITY
INTERRUPTING DEVICE
FROM
I/O
DEVICE
FROM
I/O
DEVICE
Figure 7. Multlple-DMA Interconnection to the Z-80 CPU
32
2032-0131
Programming
The Z-80 DMA has two programmable fundamental states: (l) an enabled state, m whIch
It can gain control of the system buses and
dIrect the transfer of data between ports, and
(2) a dIsabled state, m whlCh It can lmhate
nelther bus requests nor data transfers. When
the DMA IS powered up or reset by any means,
It IS automahcally placed mto the dlSabled
state. Program commands can be wntten to It
by the CPU m either state, but thIS automahcally puts the DMA m the dIsabled state,
whIch IS mamtamed unhl an enable command
IS Issued by the CPU. The CPU must program
the DMA m advance of any data search or
transfer by addressmg It as an I/O port and
sendmg a sequence of control bytes usmg an
Output mstructlOn (such as OTIR for the
Z-80 CPU).
Writing. Control or command bytes are wntten into one or more of the Write Register
groups (WRO- WR6) by first writing to the base
register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers
in a group are sequentially accessed by hrst
writing a byte to the base register containing
register-group identification and pointer bits
(l's) to one or more of that base register's
associated registers.
This IS illustrated in Figure 8b. In this
figure, the sequence in which associated
regIsters within a group can be written to is
shown by the vertical posihon of the associated
registers. For example, if a byte written to the
DMA contains the bits that identify WRO (bIts
DO, DI and D7), and also contains I's in the
bit positions that point to the associated "Port
A Starting Address (low byte)" and "Port A
Starhng Address (high byte)," then the next
two bytes written to the DMA will be stored m
these two regIsters, in that order.
Reading. The Read RegIsters (RRO-RR6) are
read by the CPU by addressmg the DMA as an
I/O port usmg an Input mstruchon (such as
INIR for the Z-80 CPU). The readable bytes
contam DMA status, byte-counter values, and
port addresses smce the last DMA reset. The
regIsters are always read m a hxed sequence
begmning with RRO and endmg wIth RR6.
However, the regIster read m thIs sequence IS
determmed by programmmg the Read Mask in
WR6. The sequence of readmg IS lmhahzed by
wntmg an Imhate Read Sequence or Set Read
Status command to WR6. After a Reset DMA,
the sequence must be lmhahzed with the
Imhate Read Sequence command or a Read
Status command. The sequence of readmg all
regIsters that are not excluded by the Read
Mask regIster must be completed before a new
Imhate Read Sequence or Read Status
command.
Fixed-Address Programming. A specIal cIrcumstance anses when programmmg a deshnahon port to have a hxed address. The load
command m WR6 only loads a fixed address to
a port selected as the source, not to a port
selected as the destmation. Therefore, a hxed
destmahon address must be loaded by temporanly declarmg It a hxed-source address
and subsequently declanng the true source as
such, thereby lmphcltly makmg the other a
destmahon.
The followmg example Illustrates the steps m
thIs procedure, assummg that transfers are to
occur from a vanable-address source (Port A)
to a fixed-address destinahon (Port B):
I. Temporanly declare Port B as source in
WRO.
2. Load Port B address m WR6.
3. Declare Port A as source m WRO.
4. Load Port A address m WR6.
5. Enable DMA m WR6.
FIgure 9 Illustrates a program to transfer
data from memory (Port A) to a penpheral
deVIce (Port B). In thIS example, the Port A
memory startmg address IS I050H and the Port
B penpheral hxed address IS 05H. Note that
the data flow IS 100lH bytes-one more than
speCIfied by the block length. The table of
DMA commands may be stored m consecuhve
memory 10catlOns and transferred to the DMA
Wlth an output mstructlOn such as the Z-80
CPU's OTIR mstruction.
Read Register 0
07
06 Do
04
01
02
D1
III
I
Read Register 2
Do
1X 1x l i i i xiii
...JI---il-LI...J1c.....J.1-L-L...J1 BYTE COUNTER (H)GH BYTE)
STATUS BYTE
LI
L - o, "'" READY
OMA OPERATION HAS OCCURRED
ACTIVE
o = INTERRUPT PENDING
0= MATCH FOUND
o "" END OF BLOCK
Read Register 3
...JI---il-LI...J1c.....J.1-L-L...J1 PORT A ADDRESS COUNTER (LOW BYTE)
LI
Read Register 4
-,I,-,I-LI-LI-LI...L...L....J1
LI
Read Register 1
L...JI-..J.I-LI-LI-L-'--..l......J1
PORT A ADDRESS COUNTER (HIGH BYTE)
Read Register 5
BYTE COUNTER {LOW BYTE)
1
....--"I---,I--..J..I--,-I--,-I--,--,--,I
PORT B ADDRESS COUNTER (LOW BYTE)
Read Register 6
....1--"I---,I--..J..I--,-I--,-I--,--,--,I
PORT B ADDRESS COUNTER (HIGH BYTE)
Figure 8a. Read Registers
2032·0132
33
Programming
(Continued)
Write Register" Group
Write Register 0 Group
01 Os 0 5 04 0 3 O2 01
10 1
1
1
1
1
I
01 Os 0 5 D. 0 3 02 01
On
1
1 BASE REGISTER BYTE
II
0
0
1
1
0
DO NOT USE
1 '" TRANSFER
0 '" SEARCH
1 '" SEARCH/TRANSFER
11 1
1
1
1
1
00
10 1"
BASE REOISTER BYTE
II
BYTE "'0
CONTINUOUS'" 0
BURST", 1
0
1
0
t
DO NOT PROGRAM""
0::: PORT B _PORT A
1:: PORT A _PORT 8
PORT A STARTING ADDRESS
(LOW BYTE)
t
PORT A STARTING ADDRESS
(HIGH BYTE}
+
L.::..L.L"-t-"-t-.L.L..L...IINTERRUPT CONTROL BYTE
BLOCK LENGTH
(Lo.W BYTE)
I I !-
+
INTERRUPT ON MATCH
1 = INTERRUPT AT END OF BLOCK
1 = PULSE GENERATED
r,-,--I,--I'-rl,--,--,--",-, PULSE CONTROL BYTE
Write Register 1 Group
0 1 06 Os 04 0 3 D2
I
10 1
1
o
0
1
~
~
!
00
11 1 0 1 0 1 BASE REGISTER BYTE
IIl
o
01
= PORT A IS MEMORY
1 = PORT A IS 110
= PORT A ADDRESS DECREMENTS
= PORT A ADDRESS INCREMENTS
I=
1
1
1
II
1
VECTOR IS AUTOMATICALLY
MODIFIED AS SHOWN
{oI I
ONLY IF "STATUS
0
,
AFFECTS VECTOR" BIT IS SET
1
PORT A VARIABLE TIMING BYTE
I I ! !:;
WR ENDS 'h CYCLE EARLY =AD ENDS 'h CYCLE EARLY", 0
MREO ENDS v, CYCLE EARLY:; 0
0
1
0
1
11 1 0 1
1
1
Do
1 0 11 1 0 1 BASE REGISTER BYTE
II I
o ::: READY ACTIVE LOW
~ READY ACTIVE HIGH
0= CEONLY
1 :: CEIW----m MULTIPLEXED
o = STOP ON END OF BLOCK
1 = AUTO RESTART ON END OF BLOCK
Write Register 2 Group
0 7 0 6 0 5 0 4 0 3 O2 0,
= INTERRUPT ON ROY
= INTERRUPT ON MATCH
"" INTERRUPT ON END OF BLOCK
:: INTERRUPT ON MATCH
AND END OF BLOCK
Write Register 5 Group
0 7 06 Os 0 4 OJ O2 0,
CYCLE LENGTH:; 4
0 1:; CYCLE LENGTH = 3
1 0:: CYCLE LENGTH = 2
1::: DO NOT USE
.
1
0= 10RO ENDS 'I> CYCLE EARLY
I INTERRUPT VECTOR
1
PORT A ADDRESS FIXED
L.....L-.L:-.L..:...L-L-L-",-,
!I
1
Do
101111101010lBASEREGISTERBVTE
I I!
o
o
0
~
~ =
t
I
Write Register 6 Group
= PORT
1'" PORT
= PORT B
= PORT B
B IS MEMORY
B IS 110
ADDRESS DECREMENTS
ADDRESS INCREMENTS
PORT B ADDRESS FIXED
LL-L-L-L-L-L-L..J PORT
1
I I
1
=
0
0
1
1 0
1
1
0= IORO
11 11 1 BASE REGISTER BYTE
I IIII
HEX COMMAND NAME
o '" C3 :: RESET
1 :: C7 '" RESET PORT A TIMING
o :: CB :: RESET PORT B TIMING
B VARIABLE TIMING BYTE
I I ! !'"
I
WR ENDS V. CYCLE EARLY""!
J!m ENDS V. CYCLE EARLY,. 0
~ ENDS VI CYCLE EARLY
0 1 0 6 0 5 O. OJ O2 0, Og
11 1
1 :: CF = LOAD
o :: 03 :: CONTINUE
CYCLE lENGTH = 4
= CYCLE LENGTH:: 3
= CYCLE lENGTH"" 2
DO NOT USE
ENOS V. CYCLE EARLY
1 = AF =
o = AS '"
o = A3 '"
1 = B7 =
DISABLE INTERRUPTS
ENABLE INTERRUPTS
RESET AND DISABLE INTERRUPTS
ENABLE AFTER RETI
1 1 = BF = READ STATUS BYTE
1" 0'" 8B = REINITIALIZE STATUS BYTE
Write Register 3 Group
0 7 06 Os 0. 0 3 O2 0,
11 1
1
1
1
0
0
1
=
A7 = INITIATE READ SEQUENCe
o
1
1
0
0
=
B3 = FORce READY
=
1 "" 87 '" ENABLE DMA
o '" 83 = DISABLE DMA
r - 0 l' 1 1 0:: SS = READ MASK FOLLOWS
LIOl 1 1 1 1 1 1 1 READ MASK 11 = ENABLE,
STOP ON MATCH
l J -I I I I I I I MASK BYTE 10 = COMPARE)
llll
1
1 0 1 0 1 BASE REOISTER BYTE
!
II
DMA ENABLE:: 1
INTERRUPT ENABLE:: 1
Do
o
!
MATCH BYTE
II
~~~~U;O~~TTEER
IIII
lJJ~g'~~~~
L-
(lOW BYTE)
A ADDRESS
(lOWBYTE)
BYTE)
PORT COUNTER
BYTE
(HIGH
PORT A ADDRESS (HIGH BYTE)
PORT B ADDRESS (lOW BYTE)
PORT B ADDRESS (HIGH BYTE)
Figure 8b. Write Registers
34
2032-0132
i
~'U
0 ..
o 0
::l1Q
gO
tl
itS
~~.
Comments
D7
De
Ds
D4
D3
D2
Dl
WRD sets DMA to receive
block length, Port A start109 address and temporanly
sets Port 8 as source
a
1
Block Length
Upper
Follows
1
Block Length
1
PortA
Upper
Address
Follows
1
PortA
a
a
Port A address (lower)
a
1
0
1
0
0
0
0
Port A address (upper)
0
0
0
1
a
0
0
0
10
0
0
0
0
0
0
0
0
00
Block length (upper)
0
0
0
1
0
0
0
0
10
WR 1 defines Port A as
memory with fixed
Incrementing address
0
0
No Timing
Follows
0
Address
Changes
1
Address
0
1
0
0
14
WR2 defines Port B as
penpheral with fixed
address
0
0
No Timing
Follows
0
0
0
28
WR4 sets mode to Burst,
sets DMA to expect Port B
address
1
1
Port B address (lower)
0
_ WR5 sets Ready active High
WR6 loads Port B address
and resets block counter *
BlOck length (lower)
WRO
sets Port A as source *
,
Lower
Follows
Lower
Address
Follows
Port
B_A
Temporary
for
Loading B
Address·
Do
HEX
1
79
Transfer, No Search
50
Increments
Memory
1
Fixed
Address
0
1
Port IS
0
0
No Interrupt
Control Byle
Follows
0
No Upper
Address
1
Port BLower
Address
Follows
0
1
C5
0
a
0
0
1
0
1
05
1
0
0
No Auto
Restart
0
No Walt
States
1
RDY
Active High
a
1
0
8A
1
1
0
0
1
1
1
1
CF
0
0
0
1
A_B
0
1
05
Burst Mode
110
0
0
No Address or Block
Length Bytes
i
IS
.'
Transfer, No Search
I
I
WR6 loads Port A address
and resets block counter
1
1
0
0
1
1
1
1
CF
WR6 enables DMA to start
operation
1
0
0
0
0
1
1
t
87
i
I
NOTE The actual number of bytes transferred IS one more than specified by the block length
*These entnes are necessary only In the case of a fixed destmatlon address
~
I
Figure 9. Sample DMA Program
nraosz
In its disabled or mactive state, the DMA is
Inactive
State Timing addressed by the CPU as an I/O perlpheral for
(DMA as CPU Wrlte and read (control and status) operations.
Peripheral)
Wrlte timmg is illustrated in FIgure 10.
Reading of the DMA's status byte, byte
counter or port address counters is illustrated
in Figure 11. These operations require less
than three T-cycles. The CEo IORQ and
RD lines are made active over two rising edges
of CLK, and data appears on the bus approximately one T-cycle after they become active.
CLK
Do-D,
-t--+--(
Figure 10. CPU-Io-DMA Wrile Cycle
Active State
Timing
(DMA as Bus
Controller)
Figure II. CPU-Io-DMA Read Cycle
inserted walt cycle between T2 and T3. If the
CE/WAIT Ime is programmed to act as a
WAIT line during the DMA's active state, it is
sampled on the falling edge of T2 for memory
transactions and the falling edge of Tw for I/O
transactions. If CE/WAIT IS Low during this
time another T-cycle is added, during which
the CE/WAIT line will again be sampled. The
duration of transactions can thus be mdefimtely extended.
Default Read and Write Cycles. By default,
and after reset, the DMA's timmg of read and
write operations is exactly the same as the Z-80
CPU's timing of read and write cycles for
memory and I/O perlpherals, wIth one exception: during a read cycle, data IS latched on
the falling edge of T3 and held on the data bus
across the boundary between read and write
cycles, through the end of the following write
cycle.
Figure 12 Illustrates the timing for memoryto-I/O port transfers and Figure 13 Illustrates
I/O-to-memory transfers. Memory-to-memory
and I/O-to-I/O transfer timmgs are simply permutations of these dIagrams.
The default tImmg uses "three T-cycles for
memory transactions and four T-cycles for I/O
transactions, which mclude one automatically
1
4 - - - MEMORY READ
T1'
I
T2
Variable Cycle and Edge Timing. The Z-80
DMA's default operation-cycle length for the
source (read) port and destination (write) port
can be independently programmed. ThIs
variable-cycle feature allows read or write
cycles consisting of two, three or four T-cycles
(more if Walt cycles are inserted), thereby
increasing or decreasing the speed of all
sIgnals generated by the DMA. In addition,
--+-1+'
I
- - - 1 / 0 WRITE
T3
T1
T2
-----1
Tw
T3
CLK
Ao-A1S
RUD
J
--tn---t-+-+---tn---t--+-t-t---I.n...-
MREQ
1
RD
WRITE l'ORQ
WR
-t---I-t-+--t---I~
'---+--+-+--1
DO-D7
CEIWAIT
MEMORY
DRIVES DATA
Tf::
\
Figure 12. Memory-lo-1I0 Transfer
36
2032-0134, 0135, 0136
Active State
Timing
(DMA as Bus
Controller)
(Continued)
••- - - - lIO READ - - - 1
T,
T2
Tw
eLK
AO-A15
mol
IX
IORQ
\
I
RD
\
r
110 DRIVES DATA
00-07
DMA DRIVES DATA BUS
'\
MREQ
W,,"
1
IX
II
ViR
CEIWAIT
-~--~--tTl\:
-r--~--
I}-
r I-+-I\- l-1
--- ---17 It --- --
--- ---
Figure 13. I/O·to·Memory Transfer
the trallmg edges of the IORQ, MREQ, RD and
WR SIgnals can be mdependently termmated
one-half cycle early. FIgure 14 illustrates this.
In the variable-cycle mode, unlike default
hming, IORQ comes active one-half cycle
before MREQ, RD and WR. CE/WAIT can be
used to extend only the 3 or 4 T-cycle variable
memory cycles and only the 4-cycle variable
I/O cycle. The CE/WAIT lme IS sampled at the
falling edge of T2 for 3- or 4-cycle memory
cycles, and at the falling edge of T3 for 4-cycle
I/O cycles.
During transfers, data is latched on the
clock edge causing the rismg edge of RD and
held through the end of the write cycle.
Bus Requests. Figure 15 illustrates the bus
request and acceptance hming. The ROY line,
which may be programmed achve HIgh or
Low, is sampled on every rising edge of CLK.
If it IS found to be achve, and if the bus IS not
in use by any other deVICe, the following rising
edge of CLK drives BUSREQ low. After receIving BUSREQ the CPU acknowledges on the
BAr input either directly or through a
multiple-DMA daisy chain. When a Low is
detected on BAI for two consecutive rising
edges of CLK, the DMA will begin transferring
data on the next rising edge of CLK.
I " I " I " I " I
eLK
"0-A1II
eLK
~=~-c=~c=
"TI"TI"T--
'ORO \
,
~.R~ ~
t
2CYCLE
. ,...L.
t
3CYCLE
'I.-r--
ROY
BUSREQ _ _ _ - - '
- - - - - - - rt---IJ--,.'
iii ______ ...J
t
4CYCLE
EARLY END EARLY END EARLY END
Figure 14. Variable·Cycie and Edge Timing
2032-0137, 0138, 0139
Figure 15. Bus Request and Acceptance
37
Active State
Timing
(DMA as Bus
Controller)
(Continued)
Bus ReleaseJlyte-at-a-Time. In Byte-at-aTime mode, BUSREQ is brought High on the
rising edge of CLK prior to the end of each
read cycle (search-only) or write cycle
(transfer. and transfer/search) as illustrated in
Figure 16. This is done regardless of the state
of RDY. There is no possibility of confusion
when a 2-80 CPU is used since the CPU
cannot begin an operation until the following
T-cycle. Most other CPUs are not bothered by
this either, although note should be taken of it.
The next bus request for the next byte will
come after both BUSREQ and BAI have
returned High.
Bus Release at End of Block. In Burst and
Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Figure 17). The last
byte in the block is transferred even If RDY
goes inactive before completion of the last byte
transfer.
Bus Release on Not Ready. In Burst mode,
when RDY goes inactive it causes BUSREQ to
go High on the next rising edge of CLK after
the completion of its current byte operation
(Figure 18). The action on BUSREQ is thus
somewhat delayed from action on the RDY
line. The DMA always completes its current
byte operation in an orderly fashion before
releasing the bus.
By contrast, ' 'B' 'U-';S'' R' 'E' 'Qr; is not released in
Continuous mode when RDY goes inactive.
eLK
Instead, the DMA idles after completing the
current byte operation, awaiting an active RDY
again.
Bus Release on Match. If the DMA is programmed to stop on match in Burst or Continuous modes, a match causes BUSREQ to go
inactive on the next DMA operation, i.e., at
the end of the next read in a search or at the
end of the following write in a transfer (Figure
19). Due to the pipelining scheme, matches
are determined while the next DMA read or
write is being performed.
The RDY line can go inactive after the
matching operation begins without affecting
this bus-release timing.
Interrupts. Timings for interrupt acknowledge
and return from interrupt are the same as timings for these in other 2-80 peripherals. Refer
to 2ilog Application Note 03-0041-01 (The Z-80
Family Program Interrupt Structure).
Interrupt on RDY (interrupt before requesting bus) does not directly affect the BUSREQ
line. Instead, the interrupt service routine
must handle this by issuing the following
commands to WR6:
I. Enable after Return From Interrupt (RETI)
Command - Hex B7
2. Enable DMA - Hex 87
3. An RETI instruction that resets the
Interrupt Under Service latch in the
2-80 DMA.
JLJ\Lfu-u--u-u--L
BUSRE.-n"
RDY
I
iiJ
- - - - - . :I,)
OMA AcnVE
_1_
OMA INACTIVE
Figure'16_ Bus Release (Byte-at-a-Time Mode)
'---.,.---f----
RDY
INACTIVE
BUSREQ
Figure 17. Bus Release at End of Block
(Burst and Continuous Modes)
""~~0f
RDY
'----0.-------
INACTIVE
BUSREQ
----------~'O-~----~
I
-
CURRENT BYTE
O,"ERATION
I
------~O)~------~I
DM'
--INACTIVE
I
BYTEn
I
-READIN--
BYTEn+l
READ IN
-+DMA
"D
INACTIVE
MATCH FOUND
ON BYTEn
Figure 18. Bus Release When Not Ready
(Burst Mode)
38
Figure 19. Bus Release on Match
(Burst and Continuous Modes)
2032·0140.0141.0142.0143
Absolute
Maximum
Ratings
Stresses greater than those hsted under Absolute MaxI-
Operatmg AmbIent
Temperature Under BIas ... As Specihed Under
"Ordermg Informahon"
Storage Temperature ........ -65 DC to + 150 DC
mum Rahngs may cause permanent damage to the devIce.
ThIs IS a stress rating only; operatIon of the device at any
condihon above those mdicated In the operahonal sechons
of these specifIcatIons IS not Imphed. Exposure to absolute
maXImum rahng condihons for extended perIods may affect
devIce rehabllity.
Voltage On Any Pm wIth
Respect to Ground ........... -0.3 V to + 7 V
Power D,ss'pahon ........
. .. 1.5 W
Standard
Test
Conditions
temperature range may be found in the ordering information section. All ac parameters
assume a load capacitance of 100 pF max.
Timing references between two output signals
assume a load difference of 50 pF max.
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
'"
• O°C to +70 D C,
+4.75V:5Vee :5 +5.25V
• -40°C to +85 D C,
+4.75 V!> Vee!> +5.25 V
-55°C to + 125 D C,
+4.5 V!> Vee!> +5.5 V
The product number for each operating
•
DC
Characteristics
-0.3
0.45
V
Vee-. 6
5.5
O.S
5.5
0.4
V
V
V
V
VILe
VIHe
Clock Input Low Voltage
Clock Input H,gh Voltage
VIL
VIH
VOL
Input Low Voltage
Input H,gh Voltage
Output Low Voltage
-0.3
2.0
VOH
Ice
Output H,gh Voltage
Power Supply Current
Z-SO DMA
Z-SOA DMA
Input Leakage Current
3-State Output Leakage Current in Float
3-State Output Leakage Current m Float
Data Bus Leakage Current m Input Mode
2.4
Vee
Capacitance
Max
Parameter
ILl
IWH
IWL
Iw
=
V
150
200
10
10
-10
±1O
rnA
rnA
p.A
p.A
p.A
p.A
IOL= 3.2rnA for BUSREQ
IOL = 2.0 rnA for all others
IOH = 250 p.A
VIN = 0 to Vee
VOUT = 2.4 to Vee
VOUT = 0.4 V
0:5 VIN :5 Vee
5 V ± 5% unless otherwise specified. over speclhed temperature range
Symbol
C
C rN
COUT
Unit Test Condition
Min
Symbol
Parameter
Clock CapacItance
Input CapacItance
Output CapacItance
Min
Max
Unit
35
5
10
pF
pF
pF
Test Condition
Unmeasured Pms
Returned to Ground
f ::::: ] MHz, over specified temperature range.
8085-0209
39
Inactive
State
AC
Characteristics
Number Symbol
TcC
2
TwCh
3
TwCl
4
TrC
5-TfC
Parameter
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
Clock Rise Time
Clock Fall Time
Th
6
Hold Time for Any Specified Setup Time
TsC(Cr)
7
IORQ. WR, CE I to Clock 1 Setup
TdDO(RDf)
8
RDI to Data Output Delay
TsWM('cr)
9
Data In to Clock 1 Setup (WR or Ml)
10 -TdCf(DO) --IORQ I to Data Out Delay (INTA Cycle)
TdRD(Dz)
11
RD 1 to Data Float Delay (output buffer
disable)
TsIEI(lORQ)
12
IEII to IORQ I Setup (INTA Cycle)
TdlEOr(lEIr)
13
lEI 1 to lEO 1 Delay
TdIEOf(lEIf)
14
lEI I to lEO I Delay
15 - TdMl(IEO) --Ml I to lEO I Delay (interrupt just prior to
Mil)
TsMlf(Cr)
16
Ml I to Clock 1 Setup
17
TsMlr(Cf)
Ml 1 to Clock I Setup
TsRD(Cr)
18
RD I to Clock 1 Setup (Ml Cycle)
TdI(lNT)
19
Interrupt Cause to INT I Delay (INT generated
only when DMA IS inachve)
20 - TdBAlr(BAOr) -BAIl to BAO 1 Delay
TdBAIf(BAOf) BAI I to BAO I Delay
21
22
TsRDY(Cr)
RDY Active to Clock t Setup
Z-80 DMA
Min Max
Z-80A DMA
Min Max
400
170
170
250
110
110
4000
ns
2000
ns
2000
ns
30
ns
30--ns-
0
145
ns
ns
380
ns
ns
160--ns-
4000
2000
2000
30
30
0
280
500
50
50
340
160
140
110
140
160
130
210
190
300
210
20
240
190
90
-10
115
500
200
200
150
100
NOTE
1 Negative mmlffium setup values mean that the hrst-mentIoned event can come after the second-mentIoned event
40
Unit
ns
ns
ns
ns
ns
ns
nb
500
ns
l50--ns150
ns
ns
Inactive
State
AC
Characteristics
CLOCK
OUTPUT
INPUT
"1"
"0"
42V
20V
20V
Dev
D8V
oev
eLK
(Contmued)
co
--~--~--~--~
IORO
Wi!
lEI
lEO
INTERRUPT
CONDITION
--------------------------~
@ACTIVE
ROY
______________________________________J
INACTIVE
NOTE
SIgnals
2032-0144
In
thIS diagram bear no relation to one another unless speclhcally noted as a numbered Item
41
Active
State
AC
Characteristics
Number Symbol
TcC
Clock
2
TwCh
Clock
3
TwCI
Clock
4
TrC
Clock
5-TfC---Clock
6
7
Z-80 DMA
Min(ns)
Max(ns)
Parameter
Cycle Time
Wldth (H'gh)
W,dth (Low)
R,se Time
Fall T,me
400
180
180
TdA
TdC(Az)
TsA(MREQ)
TsA(IRW)
Address Output Delay
Clock 1 to Address Float Delay
8
Address to MREQ j Setup (Memory Cycle)
9
Address Stable to 10RQ, RD, WR j Setup
(I/O Cycle)
*1Q--TdRW(A)-RD, WR 1 to Addr. Stable Delay
*11
TdRW(Az) RD, WR 1 to Addr. Float
12
TdCf(DO)
Clock j to Data Out Delay
*13
TdCr(Dz)
Clock 1 to Data Float Delay (Wnte Cycle)
TsDl(Cr)
14
Data In to Clock 1 Setup (Read cycle when
nsmg edge ends read)
15-TsDI(Cf)--Data In to Clock j Setup (Read cycle when
falling edge ends read)
*16
TsDO(WfM) Data Out to WR j Setup (Memory Cycle)
17
TsDO(WfI) Data Out to WR j Setup (I/O cycle)
*18
TdWr(DO) WR 1 to Data Out Delay
19
Th
Hold T,me for Any SpeClhed Setup T,me
20-TdCf(Mf)-Clock j to MREQ j Delay
21
TdCr(Mr)
Clock 1 to MREQ 1 Delay
22
TdCf(Mr)
Clock j to MREQ 1 Delay
23
TwMI
MREQ Low Pulse Width
*24
TwMh
MREQ Hlgh Pulse Width
25-TdCr(If)--Clock 1 to 10RQ j Delay
TdCr(lr)
26
Clock 1 to 10RQ 1 Delay
*27
TdCf(lr)
Clock j to 10RQ 1 Delay
TdCr(Rf)
28
Clock 1 to RD j Delay
TdCf(Rf)
29
Clock j to RD j Delay
30-TdCr(Rr)-Clock 1 to RD 1 Delay
31
TdCf(Rr)
Clock j to RD 1 Delay
32
TdCr(Wf)
Clock 1 to WR j Delay
TdCf(Wf)
33
Clock j to WR j Delay
TdCr(Wr)
34
Clock 1 to WR 1 Delay
35-TdCf(Wr)-Clock j to WR 1 Delay
36
TwWI
WR Low Pulse W,dth
TsWA(Cf)
37
WAIT to Clock j Setup
TdCr(B)
Clock 1 to BUSREQ Delay
38
TdCr(lz)
39
Clock 1 to 10RQ, MREQ, RD, WR Float
Delay
Z-80A DMA
Min(ns)
Max(ns)
250
110
110
2000
2000
30
30
145
110
30
30110
90
(2) + (5)-75
(2) + (5)-75
(1)-80
(3) + (4)-40
(3) + (4)-60
(3) + (4)-50
(3) + (4)-45
(1)-70
ISO
230
90
90
50
35
60
(1)-210
50
(1)-170
100
(3) + (4)-80
100
(3) + (4)-70
0
0
85-
100
100
100
(1)-40
85
85
(1)-30
(2) + (5)-20
(2) + (5)-30
90
75-
100
110
100
130
100
110
80
90
100
100
85
85
85
95
85-
(1)-40
85
65
80
80
80(I )-30
70
70
ISO
100
100
80
NOTES·
I Numbers
In
parentheses are other parameter-numbers
In
this table; their values should be substItuted
In
equations.
2 A.ll equations Imply DMA default (standard) hmmg
3. Data must be enabled onto data bus when RD IS actIve.
4. AsterIsk (*) before parameter number means the parameter
42
IS
2000
2000
not Illustrated m the AC TImIng Diagrams.
Active
State
AC
Characteristics
eLK
(Continued)
INPUT
1
D,-D,
OUTPUT
-----i+----i+------IH------+---t-t"" JO+----+--+-+-+--..
----~--_H-------H------+_--++J~r_--~~~-J
BUSREQ
-----------------------,~----K
NOTE
Signals m thls diagram bear no relation to one another unless specIfically noted as a numbered Item.
2032-0145
43
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Description
28410
CE
2.5 MHz
280 DMA (40-pin)
284 lOA
CE
4.0 MHz
280A DMA (40-pin)
28410
CM
2.5 MHz
Same as above
284 lOA
CM
4.0 MHz
Same as above
28410
CMB
2.5 MHz
Same as above
284 lOA
CMB
4.0 MHz
Same as above
28410
CS
2.5 MHz
Same as above
28410A
CS
4.0 MHz
Same as above
28410
DE
2.5 MHz
Same as above
28410A
DE
4.0 MHz
Same as above
28410
DS
2.5 MHz
Same as above
28410A
DS
4.0 MHz
Same as above
28410
PE
2.5 MHz
Same as above
28410A
PE
4.0 MHz
Same as above
28410
PS
'2.5 MHz
Same as above
284 lOA
PS
4.0 MHz
Same as above
NOTES. C ~ CeramIc. D ~ Cerd,p, P ~ Plashc; E
Class B processmg, S == aoe to +70°C.
44
Package/
Temp
Speed
~
-40"C to +85"C, M = -55"C to + l25"C, MB = -55"C to + l25"C wIth MIL-STD·883
00-2032·A
Z8420
Z80® PIO Parallel
Input/Output Controller
~
Product
Specification
Zilog
March 1981
Features
• Provides a direct interface between 2-80
microcomputer systems and peripheral
devices.
• Both ports have interrupt-driven handshake
for fast response.
General
Description
• Programmable interrupts on peripheral
status conditions.
• Standard 2-80 Family bus-request and
prioritized mterrupt-request daisy chains
implemented without external logic.
• Four programmable operating modes: byte
mput, byte output, byte inpuVoutput (Port A
only). and bit mpuVoutput.
• The eight Port B outputs can drive Darlmgton transistors (1.5 rnA at 1.5 V).
The 2-80 PIO Parallel 1/0 Circuit IS a programmable, dual-port devICe that provides a
TTL-compatible interface between peripheral
devices and the 2-80 CPU. The CPU configures the 2-80 PIO to interface with a wide
range of peripheral devices with no other
external logic. Typical peripheral devices that
are compatible with the 2-80 PIO include most
keyboards, paper tape readers and punches,
prmters, PROM programmers, etc.
One characteristic of the 2-80 peripheral
controllers that separates them from other
mterface controllers is that all data transfer
between the peripheral devICe and the CPU IS
accomplished under interrupt control. Thus,
the mterrupt logic of the PIO permits full use
of the efficient mterrupt capabilities of the
2-80 CPU durmg I/O transfers. All logic
necessary to implement a fully nested interrupt
structure is mcluded in the PIO.
Another feature of the PIO is the ability to
mterrupt the CPU upon occurrence of specibed status conditions m the peripheral device.
For example, the PIO can be programmed to
mterrupt if any specified peripheral alarm conditions should occur. This interrupt capability
reduces the time the processor must spend in
polling peripheral status.
PORTA
D,
D,
D,
D.
'"
Ml
eE
eiD
BIA
A,
...
As
A,
aND
A,
A,
.
A,
ASTB
PORTS
0,
lORa
.,.,
....,,
.,.,
Ro
.0
.5V
eLK
aSTB
lEI
ARDY
iNT
Do
leO
0,
BRDY
INTERRUPT {
CONTROL
lEO
Figure 1. Pin Functions
2006-0297, 0298
Figure 2. Pin AsSignments
45
General
Description
(Continued)
The Z-80 PIO interfaces to peripherals via
two independent general-purpose I/O ports,
desIgnated Port A and Port B. Each port has
eight data bIts and two handshake signals,
Ready and Strobe, which control data transfer.
The Ready output indicates to the perlpheral
that the port is ready for a data transfer.
Strobe is an input from the peripheral that
indIcates when a data transfer has occurred.
Operating Modes. The Z-80 PIO ports can be
programmed to operate in four modes: byte
output (Mode 0), byte input (Mode I), byte
input/output (Mode 2) and bit mputloutput
(Mode 3).
In Mode 0, eIther Port A or Port B can be
programmed to output data. Both ports have
output regIsters that are individually addressed
by the CPU; data can be Wrltten to eIther port
at any time. When data is written to a port, an
achve Ready output indicates to the external
device that data IS available at the associated
port and is ready for transfer to the external
devICe. After the data transfer, the external
devIce responds with an achve Strobe mput,
which generates an interrupt, If enabled.
In Mode I, either Port A or Port B can be
configured in the input mode. Each port has
an mput regISter addressed by the CPU. When
the CPU reads data from a port, the PIO sets
the Ready signal. whICh is detected by the
external devIce. The external devIce then
places data on the 1/0 lmes and strobes the
I/O port, which latches the data into the Port
Input Register, resets Ready, and triggers the
Interrupt Request, if enabled. The CPU can
read the input data at any hme, which agam
sets Ready.
Mode 2 is bldirechonal and uses Port A,
plus the interrupts and handshake signals from
both PGfts. PortB must be set to Mode 3 and
masked off. In operation, Port A IS used for
both data mput and output. Output operatIOn
IS SImIlar to Mode 0 except that data is allowed
out onto the Port A bus only when ASTB IS
Low. For mput, operahon IS SImilar to Mode I,
except that the data mput uses the Port B
handshake sIgnals and the Port B mterrupt (If
enabled).
Both ports can be used in Mode 3. In this
mode, the indIvIdual bIts are defined as eIther
input or output bits. ThIs provIdes up to eIght
separate, mdivldually defined bIts for each
port. Dunng operahon, Ready and Strobe are
46
not used. Instead, an mterrupt is generated if
the condihon of one mput changes, or if all
inputs change. The requirements for generating an mterrupt are defined during the programmmg operahon; the active level is
specIfied as either HIgh or Low, and the logic
condition is specIfied as eIther one mput active
(OR) or all mputs active (AND). For example,
if the port IS programmed for achve Low
inputs and the logic function is AND, then all
mputs at the specIfied port must go Low to
generate an mterrupt.
Data outputs are controlled by the CPU and
can be Wrltten or changed at any time.
• Individual bits can be masked off.
• The handshake sIgnals are not used in
Mode 3; Ready IS held Low, and Strobe is
disabled.
• When usmg the Z-80 PIO interrupts, the
Z-80 CPU mterrupt mode must be set to
Mode 2.
SYSTEM
BUSES
~
CPU _
T
~
V
PIO
INT~
-
INT
lEI
-
lEO
$10
iNT
lEI
-
ROY
DMA
~
'f
-V
Figure 3. PIO in a Typical ZaD Family Environment
2041-0156
Internal
Structure
The internal structure of the 2-80 PIO conSIStS of a 2-80 CPU bus interface, internal controllogic, Port A I/O logIC, Port B 110 logic,
and mterrupt control logic (FIgure 4). The
CPU bus mterface logic allows the 2-80 PIO to
interface directly to the 2-80 CPU wIth no
other external logic. The internal control logic
synchromzes the CPU data bus to the perIpheral devIce interfaces (Port A and Port B).
The two 110 ports (A and B) are virtually
Idenhcal and are used to mterface directly to
peripheral devIces.
Port Logic. Each port contains separate input
and output registers, handshake control logIc,
and the control registers shown in FIgure 5.
All data transfers between the peripheral umt
and the CPU use the data mput and output
registers. The handshake logic associated wIth
each port controls the data transfers through
the input and the output regIsters. The mode
control regISter (two bits) selects one of the
four programmable operating modes.
The control mode (Mode 3) uses the remaining registers. The input/output control regIster
specifies whICh of the eight data bIts in the
port are to be outputs and enables these bIts;
the remaming bits are mputs. The mask regIster and the mask control register control
Mode 3 interrupt condlhons. The mask regIster
specifies whICh of the bIts in the port are
achve and which are masked or mactive.
The mask control register speclhes two
condItions: first, whether the active state of
the mput bits is High or Low, and second,
whether an interrupt IS generated when any
one unmasked mput bIt IS achve (OR condItion) or if the mterrupt is generated when
all unmasked mput bits are achve (AND
condItion).
Interrupt Control Logic. The mterrupt control
logic section handles all CPU mterrupt protocol for nested-priority interrupt structures.
Any devIce's physical location m a daisy-cham
configurahon determines its priority. Two lmes
(IEI and lEO) are prOVided in each PIO to
form thIS daisy chain. The devIce closest to the
CPU has the highest priority. Withm a PIO,
Port A mterrupts have hIgher priority than
those of Port B. In the byte mput, byte output,
or bldirechonal modes, an mterrupt can be
generated whenever the peripheral requests a
new byte transfer. In the bit control mode, an
mterrupt can be generated when the peripheral status matches a programmed value. The
PIO prOVIdes for complete control of nested
interrupts. That IS, lower priority devices may
not mterrupt hIgher Priority devIces that have
not had theIr mterrupt servIce routmes completed by the CPU. HIgher Priority devIces
may mterrupt the servICmg of lower Priority
devICes.
DATA
OR CONTROL
}HANDSHAKE
PERIPHERAL
INTERFACE
DATA
OR CONTROl.
}HANDSHAKE
INTERRUPT CONTROL LINES
Figure 4. Block Diagram
2006·0316
47
N
GO
..,...
o
o
Internal
Structure
(Continued)
If the CPU (in interrupt Mode 2) accepts an
interrupt, the mterrupting device must provide
an 8-bit mterrupt vector for the CPU. This vector forms a pointer to a locahon m memory
where the address of the interrupt service
routme IS located. The 8-blt vector from the
mterrupting device forms the least signifIcant
eight bits of the mdirect pomter while the
I Register m the CPU provides the most significant eight bits of the pointer. Each port (A and
B) has an mdependent interrupt vector. The
least significant bit of the vector IS automahcally set to 0 wlthm the PIO because the
pomter must pomt to two adjacent memory
locahons for a complete 16-blt address.
Unlike the other 2-80 peripherals, the PIO
does not enable mterrupts Immediately after
programmmg. It waits until MI goes Low (e.g.,
durmg an opcode fetch). This condlhon IS
unimportant m the 2-80 environment but might
not be if another type of CPU is used.
The PIO decodes the RETI (Return From
Interrupt) mstruchon directly from the CPU
data bus so that each PIO in the system knows
at all hmes whether It IS bemg serviCed by the
CPU mterrupt service routme. No other commUnlcahon with the CPU IS required.
CPU Bus I/O Logic. The CPU bus interface
logiC interfaces the 2-80 PIO directly to the
2-80 CPU, so no external logic is necessary.
For large systems, however, address decoders
and/or buffers may be necessary.
Internal Control Logic. This logic receives the
control words for each port duhng programming and, in turn, controls the operating functions of the 2-80 PIO. The control logic synchronizes the port operations, controls the port
mode, port addressing, selects the read/write
function, and issues appropriate commands to
the ports and the interrupt logic. The 2-80 PIO
does not receive a write input from the CPU;
instead, the RD, CE, C/D and IORQ Signals
generate the write input internally.
MODE
CONTROL
REGISTER
(2 BITS)
8-BIT 110 BUS
MASK
CONTROL
REGISTER
(2 BITS)
INTERRUPT
CONTROL
LOGIC
HANDSHAKE
READY
C~~~~gL ~
}
HANDSHAKE
CONTROL
·Used In the bit mode only to .lIow generation of en
Interrupt If the Pllrlph.ralllO pins go to the specified state.
Figure 5. Typical Port I/O Block Diagram
48
2006·0317
Programming Mode O. 1. or 2. (Byte Input, Output. or
Bidirectional). Programming a port for Mode
0, I, or 2 requires two words per port. These
words are:
A Mode Control Word. Selects the port operatmg mode
(FIgure 6). ThIs word may be WrItten any time.
An Interrupt Vector. The 2-80 PIO IS deSIgned for use WIth
the Z-80 CPU m mterrupt Mode 2 (FIgure 7). When mterrupts are enabled, the PIO must provIde an mterrupt
vector.
Mode 3. (Blt Input/Output). Programmmg a
port for Mode 3 operation requires a control
word, a vector (if interrupts are enabled), and
three additional words, described as follows:
I/O Register Control. When Mode 3 IS selected, the mode
control word must be followed by another control word that
sets the I/O control regIster, whIch m turn defmes whICh
port lmes are mputs and whIch are outputs (Figure 8).
I
-r-==
IDENTiFIES MODE
CONTROL WORD
DON'T CARE
Interrupt Control Word. In Mode 3, handshake IS not
used. Interrupts are generated as a logIc funchon of the
mput sIgnal levels. The mterrupt control word sets the
lOgiC condItions and the logIc levels requIred for generatIng an mterrupt. Two logiC condItIons or functIons are
avaIlable: AND (11 all mput bItS change to the active level,
an mterrupt IS trIggered), and OR (If anyone of the mput
bIts changes to the actIve level, an mterrupt IS tnggered),
BIt D6 sets the logIC function, as shown m FIgure 9. The
actIve level of the mput bits can be set elther HIgh or Low.
The active level IS controlled by BIt D5 .
Mask Control Word. ThIs word sets the mask control
regIster, allowmg any unused bItS to be masked off. If any
bIts are to be masked, then D4 must be set. When D4 IS set,
the next word WrItten to the port must be a mask control
word (FIgure 10).
Interrupt Disable. There is one other control
word which can be used to enable or disable a
port interrupt. It can be used without changing
the rest of the interrupt control word
(Figure ll).
III
L
MODE
MODE
MODE
MODE
0
1
2
3
~~~~~=::::HO"~'
D4 = 1 MASK WORD FOLLOWS
05 = 0 ACTIVE LEVEL IS LOW
05 = 1 ACTIVE LEVEL IS HIGH
MODE SELECT
06 = 0 INTERRUPT ON OR FUNCTION
06 = 1 INTERRUPT ON AND FUNCTION
'-------- ~; : ~ :~~~::~:~ ~~::t:g·
·NOTE THE PORT IS NOT ENABLED UNTIL
THE INTERRUPT ENABLE IS FOLLOWED
BY AN ACTIVE M1
Figure 6. Mode Control Word
Figure 9. Interrupt Control Word
1~1~1~1~1~1~1~lol
L
IDENTIFIES INTERRUPT
VECTOR
L-_ _ _ _ ~~~~OS~PPLIED INTERRUPT
Figure 7. Interrupt Vector Word
MBo-MBT MASK BITS A
BIT IS MONITORED FOR AN
' - - - - - INTERRUPT IF IT IS
DEFINED AS AN INPUT AND
THE MASK BIT IS SET TO 0
Figure 10. Mask Control Word
1T
10,10,10,10.10 I 01'1'1
L
IDENTIFIES INTERRUPT
DISABLE WOAD
DON'T CARE
Dr = 0 INTERRUPT DISABLE
Dr = 1 INTERRUPT ENABLE
Figure 8. I/O Register Control Word
2006-0318,0319,0320,0321,0322.0323
Figure 11. Interrupt Disable Word
49
Pin
Description
Ao-A7. Port A Bus (bidlrechonal, 3-state).
C/O. Control Or Data Select (input,
This S-blt bus transfers data, status, or control
information between Port A of the PIa and a
peripheral device. Ao is the least significant
bit of the Port A data bus.
High = C). This pin defines the type of data
transfer to be performed between the CPU and
the PIO. A High on this pin during a CPU
write to the PIa causes the 2-S0 data bus to be
interpreted as a command for the port selected
by the B/A Select line. A Low on this pin
means that the 2-S0 data bus IS being used to
transfer data between the CPU and the PIa.
Often address bit Al from the CPU is used for
this function.
CEo Chip Enable (input, active Low). A Low
on this pin enables the PIa to accept command or data inputs from the CPU during a
write cycle or to transmit data to the CPU during a read cycle. This signal is generally
decoded from four 1/0 port numbers for Ports
A and B, data, and control.
CLK. System Clock (input). The 2-S0 PIa uses
the standard single-phase 2-S0 system clock.
AHDY. Register A Ready (output, active
High). The meaning of this signal depends on
the mode of operation selected for Port A as
follows:
Output Mode. ThIs sIgnal goes actIve to IndIcate that the
Port A output regIster has been loaded and the penpheral
data bus IS stable and ready for transfer to the penpheral
deVIce.
Input Mode. ThIs sIgnal IS active when the Port A mput
regIster IS empty and ready to accept data from the
penpheral devIce.
BIdIrechonal Mode. ThIs sIgnal IS actIve when data IS
avaIlable In the Port A output regIster for transfer to the
penpheral devIce. In thIS mode, data IS not placed on the
Port A data bus, unless ASTB IS actIve.
Control Mode. ThIs sIgnal IS dIsabled and forced to a Low
state.
ASTB. Port A Strobe Pulse From Peripheral
Device (input, achve Low). The meanmg of
this signal depends on the mode of operahon
selected for Port A as follows:
Output Mode. The posItIve edge of thIs strobe IS issued by
the perIpheral to acknowledge the receIpt of data made
avaIlable by the PIO.
Input Mode. The strobe IS Issued by the penpheral to load
data from the perIpheral mto the Port A Input regIster.
Data IS loaded mto the PIO when thIS sIgnal IS actIve.
Bidirectional Mode. When thIs sIgnal IS achve, data from
the Port A output regIster IS gated onto the Port A bIdIrec·
tIonal data bus. The posItIve edge of the strobe acknowl·
edges the receIpt of the data.
Control Mode. The strobe IS InhIbIted mternally.
Bo-B7. Port B Bus (bidirectional, 3-state). This
8-blt bus transfers data, status, or control
information between Port B and a peripheral
device. The Port B data bus can supply
1.5 rnA at 1.5 V to drive Darlmgton transistors.
Bo is the least sigmficant bit of the bus.
BfA. Port B Or A Select (input, High = B).
This pm defines which port IS accessed during
a data transfer between the CPU and the PIa.
A Low on thiS pin selects Port A; a High
selects Port B. Often address bit Ao from the
CPU is used for thiS selection function.
BHDY. Register B Ready (output, active High).
ThiS signal is similar to ARDY, except that in
the Port A bidirectional mode thiS signal is
High when the Port A input register is empty
and ready to accept data from the peripheral
deVice.
BSTB. Port B Strobe Pulse From Peripheral
Device (input, active Low). This signal is
similar to ASTB, except that m the Port A
bidirectional mode thiS signal strobes data
from the penpheral deVICe mto the Port A
mput register.
50
Do-D7. Z-80 CPU Data Bus (bidirectional,
3-state). This bus IS used to transfer all data
and commands between the 2-S0 CPU and the
2-80 PIa. Do is the least significant bit.
lEI. Interrupt Enable In (input, active High).
This signal is used to form a priority-interrupt
daisy chain when more than one interruptdriven device is being used. A High level on
this pm indicates that no other devices of
higher prIOrity are being serviced by a CPU
interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). The lEO signal is the other signal
reqUired to form a daisy chain priority scheme.
It IS High only if lEI is High and the CPU is
not servICmg an interrupt from this PIO. Thus
thiS signal blocks lower priority devices from
interrupting whtle a higher priOrity deVice IS
bemg serviced by its CPU mterrupt service
routine.
INT. Interrupt Request (output, open drain,
active Low). When INT is active the 2-80 PIa
IS requestmg an interrupt from the 2-80 CPU.
IOHQ. Input/Output Request (input from 2-S0
CPU, active Low). 10RQ is used in conjunction with B/A, ci15, CE, and RD to transfer
commands and data between the 2-S0 CPU and
the 2-80 PIa. When CE, RD, and 10RQ are
active, the port addressed by B/A transfers
data to the CPU (a read operation). Conversely, when CE and 10RQ are active but RD
is not, the port addressed by B/A is written
into from the CPU With either data or control
information, as speCified by ciD. Also, if
IORQ and MI are active simultaneously, the
CPU IS acknowledging an interrupt; the interrupting port automatically places ItS interrupt
vector on the CPU data bus if tt IS the highest
Priority device requesting an interrupt.
Pin
Description
(Continued)
MI. Machine Cycle (Input from CPU, active
Low). This signal is used as a sync pulse to
control several Internal PIO operations. When
both the Ml and RD signals are active, the
Z-80 CPU is fetching an Instruction from
memory. Conversely, when both Ml and
IORQ are active, the CPU IS acknowledging
an interrupt. In addlhon, MI has two other
functions wIthin the Z-80 PIO: It synchromzes
Timing
The folloWing timing diagrams show typical
timing in a Z-80 CPU environment. For more
precise speCifications refer to the composite
ac timing diagram.
Write Cycle. Figure 12 illustrates the
timing for programming the Z-80 PIO
or for writing data to one of its ports. No
Wait states are allowed for writing to the
PIO other than the automatically inserted
TWA. The PIO does not receive a specific write signal; it internally generates
its own from the lack of an active
RD signal.
the PIO Interrupt logic; when Ml occurs
wIthout an active RD or IORQ sIgnal, the PIO
is reset.
RD. Read Cycle Status (Input from Z-80 CPU,
active Low). If RD is achve, or an 1/0 operahon is In progress, RD IS used WIth BiA, C/O,
CE, and IORQ to transfer data from the Z-80
PIO to the Z-80 CPU.
T,
T,
T,
TWA
T,
eLK
C/D.a/i
==x
x::=
Ci
IORQ
\
DATA
X
WR·
\
"WR = RO' CE •
r-
N
CD
0
x=:
IN
•B
r-
Ctii • IORQ
Figure 12. Write Cycle Timing
Read Cycle. Figure 13 illustrates the timing
for reading the data input from an external
device to one of the Z-80 PIO ports. No Wait
states are allowed for reading the PIO other
than the automatically inserted TWA.
Output Mode (Mode 0). An output cycle
(Figure 14) is always started by the execution
of an output instruction by the CPU. The WR*
pulse from the CPU latches the data from the
CPU data bus into the selected port's output
register. The WR * pulse sets the Ready flag
after a Low-going edge of CLK, indicating
data is available. Ready stays active until the
positive edge of the. +robe line is received,
indicating that data WdS taken by the peripheral. The positive edge of the strobe pulse
generates an INT if the interrupt enable flipflop has been set and if this device has the
highest priority.
T,
T,
T,
TWA
T,
eLK
c/D.B/A
Ci
==x
x=:
\
I
I
I
IORQ
\
iiii
\
(
DATA
\
iiii"
r
OUT
I
"RO = RO' Cii • C/O, IORQ
Figure 13. Read Cycle Timing
eLK
PORT ----------'r~--~------~~----_7--OUTPUT __________J~____+_------_+------~--READY
_ _ _ _ _ _---J
"WR = RO' CE • CID • IORQ
Figure 14. Mode 0 Output Timing
2006-0324, 0325. 0326
Rl
Timing
(Continued)
Input Mode (Mode 1). When STROBE goes
Low, data is loaded into the selected port input
register (Figure 15). The next rising edge of
strobe activates INT, if Interrupt Enable is set
and this is the highest-priority requesting
device. The following falling edge of CLK
resets Ready to an inactive state, indicating
that the input register is full and cannot accept
any more data until the CPU completes a read.
When a read is complete, the positive edge of
RD sets Ready at the next Low-going transition
of CLK. At this time new data can be loaded
into the PIO.
CLK
READY
~_ -----------------4.~------~
-RD
= RD' CE •
C/D • IORQ
Figure 15. Mode I Input Timing
Bidirectional Mode (Mode 2). This is a combination of Modes 0 and 1 using all four handshake lines and the eight Port A 1/0 lines
(Figure 16). Port B must be set to the bit mode
and its inputs must be masked. The Port A
handshake lines are used for output control
and the Port B lines are used for input control.
If interrupts occur, Port A's vector will be used
during port output and Port B's will be used
during port input. Data is allowed out onto the
Port A bus only when ASTB is Low. The rising
edge of this strobe can be used to latch the
data into' the peripheral.
CLK
iiVR- - - - - - - ,
ARDY
PORT
A
DATA
BUS
-----------------------c~~~>_--------~
85TB
BRDY
-WR
= RD.
CE • C/D • IORQ
Figure 16. Mode 2 Bidirectional Timing
2006-0327. 0328
Timing
(Continued)
Bit Mode (Mode 3). The bit mode does not
utilize the handshake signals, and a normal
port write or port read can be executed at any
time. When writing, the data is latched into
the output registers with the same timing as the
output mode (Figure 17).
When reading the PIO, the data returned to
the CPU is composed of output register data
from those port data lines assigned as outputs
and input register data from those port data
lines assigned as inputs. The input register
contains data that was present immediately
prior to the falling edge of RD. An interrupt is
generated if interrupts from the port are
enabled and the data on the port data lines
satisfy the logical equation defined by the 8-bit
mask and 2-bit mask control registers. However, if Port A is programmed in bidirectional
mode, Port B does not issue an interrupt in bit
mode and must therefore be polled.
eLK
PORT
DATA BUS
X
DATA WOAD 1
t
iii
X
DATA WORD 2
X
MA~CH
DATA
\
OCCURS HERE
III
GO
/
IORG
AD
0
a
j
Do-D7
<
·Tlmmg DIagram Refers to BIt Mode Read
DATA IN
>
LOAfA WOAD 1 PLACED ON BUS
Figure 17. Mode 3 Bit Mode Timing
Interrupt Acknowledge Timing. During Ml
time, peripheral controllers are inhibited from
changing their interrupt enable status, permitting the Interrupt Enable signal to ripple
through the daisy cham. The peripheral with
IEI High and lEO Low during INTACK places
a preprogrammed 8-bit interrupt vector on the
data bus at this time (Figure 18). IEO is held
Low until a Return From Interrupt (RETI)
il1struction is executed by the CPU while IEI is
High. The 2-byte RETI instruction is decoded
internally by the PIO for this purpose.
LASTT
STATE
I
T
1
eLK
l
'ORQAND
INDICATE
,..----
An
INTERRUPT
A2..!lliQ.WLEDGE
INTACK
,.,
Figure 18. IDterrupt Acknowledge Timing
Return From Interrupt Cycle. If a 2-80 peripheral has no interrupt pending and is not
under service, then its IEO = IEI. If it has an
interrupt under service (Le., it has already
interrupted and received an interrupt acknowledge) then its IEO is always Low, inhibiting
lower priority devices from interrupting. If it
has an interrupt pending which has not yet
been acknowledged, IEO is Low unless an
"ED" is decoded as the first byte of a 2-byte
opcode (Figure 19). In this case, IEO goes
High until the next opcode byte is decoded,
whereupon it goes Low again. If the second
byte of the opcode was a "4D," then the
opcode was an RETI instruction.
After an "ED" opcode is decoded, only the
peripheral device which has interrupted and is
currently under service has its IEI High and its
IEO Low. This device is the highest-priority
device in the daisy chain that has received an
interrupt acknowledge. All other peripherals
have IEI = IEO. If the next opcode byte
decoded is "4D," this peripheral device resets
its "interrupt under service" condition.
eLK
AD
Do-D, - - - - (
,., ---- - ,r----------______ J
-1;---
liD _ _ _ _ _ _ _ _ _ _ _ _ _
Figure 19. Return From Interrupt
2006-0329, 0330, 0331
53
AC
Characteristics
CLOCK
CE
B/A.eID
RD,IORQ
00-07
------~------i_~kr--~--1_-------------------J~~~--++-----------+--------------
J
OUT
l·N ------------+-~~~----------------~~--------~---------
lEI
lEO
REAOY
IAROY OR BROY)
iTiiiiii
IASTB OR B5TB)
MODEa
MODE 1
MODE 2
MODE 3
54
2006-0332
Z-80 PlO
Min Max
Number Symbol
Parameter
Clock Cycle Time
TcC
Clock Width (High)
2
TwCh
Clock Width (Low)
3
TwCl
4
Clock Fall Time
TIC
5-TrC
Clock Rise T,me
TsCS(RI)
CE, BfA, CfD to RD,
6
IORQ I Setup Time
Any Hold Times for Specified
7
Th
Setup Time
TsRI(C)
8
RD, IORQ to Clock 1 Setup
Time
9 - TdRI(DO)-- RD, IORQ Ito Data Out Delay
TdRI(DOs)
RD, IORQ 1 to Data Out Float
10
Delay
TsDI(C)
Data In to Clock 1 Setup Time
11
TdIO(DOI)
IORQ I to Data Out Delay
12
(INTACK Cycle)
13- TsMl(Cr)-- Ml I to Clock 1 Setup Time-14
TsMl(Cf)
Ml..Lto Clock I Setup T,me
(MI Cycle)
TdMl(IEO)
MI I to lEO j Delay (Interrupt
15
Immediately Precedmg Ml j)
TsIE!(IO)
lEI to IORQ j Setup T,me
16
(INTACK Cycle)
17 - TdIEI(IEOf)- IEI j to IEO I Delay
(ns)
250
105
105
[I]
29
2000
2000
30
30
50
50
50
0
0
0
115
115
430
[6]
0
70
[2]--
300
380
160
Comment
110
70
50
50
40
CL = 50 pF
340
210
160
90
120
70
[3]
0
0
0
[8]
300
140
TdC(RDYf)
TwSTB
TsSTB(C)
28
165
65
65
[ 1]
2000
2000
20
20
(ns)
[I]
2000
2000
30
30
21
22
23
27
(ns)
(ns)
400
170
170
20 -
19
26
(ns)
(ns)
IEI 1 to lEO 1 Delay (after ED
Decode)
TeIO(C)
IORQ 1 to Clock j Setup T,me
(To Activate READY on Next
Clock Cycle)
220
TdC(RDYr)- Clock j to READY 1 Delay-- 200
25
Z-80B PlO[gJ
Min Max
190
140
100
[5,7]
100
190
130
120
[7J
[5]-CL = 50 pF
210
160
160
[5]
150
Clock j to READY 1 Delay
STROBE Pulse Width
150
STROBE 1 to Clock j Setup
T,me (To Achvate READY on
220
Next Clock Cycle)
-TdIO(PD)-- IORQ 1 to PORT DATA Stable
Delay (Mode 0)
TsPD(STB)
PORT DATA to STROBE 1
Setup T,me (Mode 1)
260
TdSTB(PD)
STROBE j to PORT DATA
Stable (Mode 2)
-TdSTB(PDr)-STROBE 1 to PORT DATA Float
Delay (Mode 2)
TdPD(INT)
PORT DATA Match to INT j
Delay (Mode 3)
TdSTB(INT)
STROBE 1 to INT I Delay
NOTES:
[11 TcC = TwCh + TwCI + TrC + TfC.
[2] Increase TdRI(DO) by 10 ns for each 50 pF Increase m load
up to 200 pF max.
[3] Increase TdIO(DOI) by 10 ns for each 50 pF, Increase In
loadmg up to 200 pF max.
[4J For Mode 2' TwSTB > TsPD(STB)
[5] Increase these values by 2 ns for each 10 pF Increase m
loadmg up to 100 pF max.
200
190
170
170
140
150
120
120
220
150
200
180
230
[5]-CL = 50 pF
[5]
[4]
[5J
160
[5]
IN
00
0
..,....
0
TdIEI(IEOr)
18
24
Z-80A PlO
Min Max
190
230
210
180
[5J
200
180
160
CL = 50 pF
540
490
490
440
430
350
[6] TsCS(RI) may be reduced. However, the hme subtracted
from TsCS(Rl) WIll be added to TdRI(DO)
[7J 2.5 TcC > (N-2)TdIEI(lEOf) + TdMI(lEO) + TsIEI(lO)
+ TTL Buffer Delay, If any.
[8] MI must be actIve for a mmlIDum of two clock cycles to
reset the PIO.
[9] 280B PIO numbers are prelImmary and subject to change.
55
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Stresses greater than those hsted under Absolute MaxImum RatIngs may cause permanent damage to the devlc8.
ThIs IS a stress ratmg only; operatIon of the device at any
condItion above those mdlcated In the operational sections
of these speclfIcatlons IS not ImplIed. Exposure to absolute
maXlmum ratmg conditIons for extended perIods may affect
device rehablllty.
Storage Temperature ........ -65°C to + 150 °C
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND (0 V). PosItive current flows into the
referenced pin. Available operating
temperature ranges are:
Ordering Information section.
All ac parameters assume a load capacitance
of 100 pF max. Timing references between two
output signals assume a load difference of
50 pF max.
+5V
81 0° to + 70°C,
+4.75 V :5 Vee :5 +5.25 V
81 -40°C to +85°C,
+4.75 V :5 Vee :5 +5.25 V
81 -55° to + 125°C,
+4.75 V :5 Vee :5 +5.5 V
The product number for each operating
temperature range may be found in the
DC
Characteristics
Symbol
VILe
VIHe
VIL
VIH
VOL
VOH
ILl
Iz
lee
IOHD
Parameter
Clock Input Low Voltage
Clock Input HIgh Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output HIgh Voltage
Input Leakage Current
3-State Output/Data Bus Input Leakage Current
Power Supply Current
Darhngton Drive Current
21'
Unit
Test Condition
-0.3 +0.45
Vee-0.6 +5.5
-0.3 +0.8
+2.0
+5.5
+0.4
+2.4
-10.0 + 10.0
-10.0 + 10.0
100.0
-1.5
3.8
V
V
V
V
V
V
p,A
p,A
rnA
rnA
IOL = 2.0 rnA
IOH = -250 p,A
O x P x T. The minimum bmer resolubon is 16 x cj> (4 Ji.S with a 4 MHz clock). The
maximum hmer interval is 256 x cj> x 256 (16.4 ms
with a 4 MHz clock). For longer intervals
bmers may be cascaded.
Interrupt Vector Programming. If the 2-80
CTC has one or more interrupts enabled, it
can supply interrupt vectors to the 2-80 CPU.
To do so, the 2-80 CTC must be pre-programmed WIth the most-sIgnificant five bIts of
the mterrupt vector. Programming consISts of
writmg a vector word to the 1/0 port corresponding to the 2-80 CTC Channel O. Note
that Do of the vector word is always zero, to
dIstingUIsh the vector from a channel control
word. Dj and D2 are not used in programming
the vector word. These bIts are supphed by
the mterrupt logIC to identify the channel
requestmg mterrupt service with a unique
mterrupt vector (FIgure 7). Channel 0 has the
hIghest priOrity.
V7-V3~
SUPPLIED
BY USER
-c
0
1
= INTERRUPT VECTOR WORD
= CONTROL WORD
CHANNEL IDENTIFIER
(AUTOMATICALLY INSERTED
BY eTC)
0 = CHANNEL 0
1 = CHANNEL 1
1 0 = CHANNEL 2
1 1 "" CHANNEL 3
o
o
Figure 7. Interrupt Vector Word
63
~
n
Pin
Description
CEo Chip Enable (input, active Low). When
enabled the CTC accepts control words, interrupt vectors, or time constant data words from
the data bus during an I/O write cycle; or
transmits the contents of the down-counter to
the CPU during an 1/0 read cycle. In most
applications this signal is decoded from the
eight least significant bits of the address bus
for any of the four 1/0 port addresses that are
mapped to the four counter-timer channels.
ClK. System Clock (input). Standard singlephase 2-80 system clock.
ClK/TRGo-ClK/TRGa. External Clock/Timer
Trigger (input, user-selectable active High or
Low). Four pins corresponding to the four 2-80
CTC channels. In counter mode, every active
edge on this pin decrements the down-counter.
In timer mode, an achve edge starts the timer.
CSO-CSI' Channel Select (inputs active High).
Two-bit binary address code selects one of the
four CTC channels for an I/O write or read
(usually connected to Ao and AI).
00-07' System Data Bus (bidirectional,
3-state). Transfers all data and commands
between the Z-80 CPU and the 2-80 CTC.
SYSTEM
BUSES
CPU _
tNT
T
--L
A
..l\
\('
"'V
PIO
> - r - - iNT
lEI. Interrupt Enable In (input, active High).
A High indicates that no other interrupting
devices of higher priority in the daisy chain
are being serviced by the 2-80 CPU.
lEO. Interrupt Enable Out (output, active
High). High only if lEI is High and the 2-80
CPU is not servicing an interrupt from any
2-80 CTC channel. lEO blocks lower priority
devices from interrupting while a higher
priority -interrupting device is being serviced.
INT. Interrupt Request (output, open drain,
active Low). Low when any 2-80 CTC channel
that has been programmed to enable interrupts
has a zero-count condition in its down-counter.
IORQ. Input/Output Request (input from CPU,
active Low). Used with CE and RD to transfer
data and channel control words between the
2-80 CPU and the 2-80 CTC. During a write
cycle, IORQ and CE are achve and RD
inactive. The 2-80 CTC does not receive a
specific write Signal; rather, it internally
generates its own from the inverse of an active
RD signal. In a read cycle, IORQ, CE and RD
are active; the contents of the down-counter
are read by the Z-80 CPU. If IORQ and MI are
both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on
the 2-80 data bus.
MI. Machine Cycle One (input from CPU,
active Low). When Ml and IORQ are active,
the 2-80 CPU is acknowledging an interrupt.
The 2-80 CTC then places an interrupt vector
on the data bus if it has highest priority, and if
a channel has requested an interrupt (INT).
RD. Read Cycle Status (input, active Low).
lEI
lEO
-
- > - - iNT
510
A.
lEi
ROY
DMA
..l\
!y-----y
Used in conjunction wIth IORQ and CE to
transfer data and channel control words
between the 2-80 CPU and the 2-80 CTC.
RESET. Reset (input active Low). Terminates
all down-counts and disables all interrupts by
resetting the interrupt bits in all control
registers; the 2C/TO and the Interrupt outputs
go inactive; lEO reflects lEI; Do-D7 go to the
high-impedance state.
ZC/TOo-ZC/T02' Zero Count/Timeout (output,
active High). Three 2C/TO pins corresponding
to Z-80 CTC channels 2 through 0 (Channel 3
has no 2C/TO pin). In both counter and timer
modes the output is an active High pulse when
the down-counter decrements to zero.
Figure S. A Typical Z-SO Environment
64
2041-0156
Read Cycle Timing. Figure 9 shows read
cycle timmg. This cycle reads the contents of a
down-counter without disturbing the count.
During clock cycle T2, the 2-80 CPU initiates a
read cycle by drlvmg the following inputs
Low: RD, IORQ, and CE. A 2-blt binary code
at mputs CS j and CSo selects the channel to
be read. MI must be High to distinguish this
cycle from an interrupt acknowledge. No addihonal Willt states are allowed.
Timing
latched into the appropriate register with the
rising edge of clock cycle TWA. No additional
wait states are allowed.
<~~
TIME
T,
T,
1
INTERNAL
TIMER
START TIMING
Figure 11. Timer Mode Timing
CLK
CSo,
CS,. CE
===x:
CHANNEL ADDRESS
x:=:
-J;----______J;-----
\~_ _ _ _ _ _
IORO
~
\~
_ --r--------------
M1
_J
I
DATA - - - - - - - - - - (
Figure 9. Read Cycle Timing
Write Cycle Timing. Figure 10 shows write
cycle hming for loading control, time constant
or vector words.
The CTC does not have a write signal mput,
so It generates one internally when the read
(RD) input is High during Tj. Durmg T2
IORQ and CE mputs are Low. MI must be
High to distmguish a write cycle from an interrupt acknowledge. A 2-bit binary code at
mputs CSj and CSo selects the channel to be
addressed, and the word being written is
placed on the Z-80 data bus. The data word is
T,
T,
CE
===><
CHANNEL ADDRESS
\
x::=
;--
Rij--;-------------_J
_ --"7"-------------M1 _./
..JX'-__'N_...JX'-_____
DATA _ _ _ _
Figure 10. Write Cycle Timing
2041·0162,0163,0164,0165
eLK/TRO
INTERNAL
COUNTER
----"'7
ZC/TO _ _ _ _- J
Figure 12. Counter Mode Timing
T,
TWA
CLK
CSo. CS,.
Timer Operation. In the timer mode, a
CLKlTRG pulse input starts the timer (Figure
II) on the second succeeding rismg edge of
CLK. The trigger pulse is asynchronous. and it
must have a minimum width. A minimum lead
hme (210 ns) is reqUIred between the active
edge of the CLK/TRG and the next rising edge
of CLK to enable the prescaler on the following clock edge. If the CLK/TRG edge occurs
closer than this, the mitiation of the timer
funchon IS delayed one clock cycle. ThIS corresponds to the startup timing discussed in the
programming section. The timer can also be
started automatically if so programmed by the
channel control word.
Counter Operation. In the counter mode, the
CLK/TRG pulse mput decrements the downcounter. The trigger is asynchronous, but the
count is synchronized wIth CLK. For the
decrement to occur on the next rising edge of
CLK, the trigger edge must precede CLK by a
minimum lead time as shown m Figure 12. If
the lead time IS less than specified, the count
is delayed by one clock cycle. The trigger
pulse must have a minimum wIdth, and the
trigger period must be at least twice the clock
period.
The ZC/TO output occurs immediately after
zero count, and follows the rising CLK edge.
65
Interrupt
Operation
The 2-80 eTC follows the 2-80 system interrupt protocol for nested priority mterrupts and
return from interrupt, wherem the mterrupt
priority of a peripheral is determined by its
location in a daisy chain. Two lines-IEI and
IEO-m the eTC connect it to the system daisy
chain. The device closest to the + 5 V supply
has the highest priority (Figure 13). For additional information on the 2-80 interrupt structure, refer to the Z-80 CPU Product Specification and the Z-80 CPU Technical Manual.
HIGHEST PRIORITY
DEVICE
LOWEST PRIORITY
DEVICE
Figure 13. Daisy-Chain Interrupt Priorities
Within the 2-80 eTC, interrupt priority is
predetermined by channel number: Channel 0
has the highest priority, and Channel 3 the
lowest. If a device or channel is being serviced
with an interrupt routine, it cannot be interrupted by a device or channel with lower
priority until service is complete. Higher
priority devices or channels may interrupt the "
servicing of lower priority devices or channels.'
A 2-80 eTC channel may be programmed to
request an interrupt every time its downcounter reaches zero. Note that the CPU must
be programmed for interrupt mode 2. Some
time after the interrupt request, the CPU sends
an interrupt acknowledge. The eTC interrupt
control logic determines the highest prIority
channel that is requesting an interrupt. Then,
if the eTC IEI input is High (indicating that It
has priority within the system daisy cham) it
places an 8-'bit mterrupt vector on the system
data bus. The high-order five bits of this vector
T,
TWA
were written to the eTC durmg the programmmg process; the next two bits are provided
by the eTC interrupt control logic as a binary
code that identifies the highest priority channel requesting an interrupt; the low-order bit
is always zero.
Interrupt Acknowledge Timing. Figure 14
shows interrupt acknowledge timing. After an
interrupt request, the 2-80 CPU sends an interrupt acknowledge (Ml and IORQ). All channels are inhibited from changing their interrupt request staJus when Ml is active-about
two clock cycles earlier than IORQ. RD is
High to distinguish this cycle from an instruction fetch.
The eTC interrupt logic determines the
highest priority channel requesting an interrupt. If the eTC interrupt enable input (IEI) IS
High, the highest priority interrupting channel
within the eTC places its interrupt vector on
the data bus when IORQ goes Low. Two wait
states (TWA) are automatically inserted at this
time to allow the daisy chain to stabihze. AddItional wait states may be added.
Return from Interrupt Timing. At the end of
an interrupt service routine the RETI (Return
From Interrupt) instruction initializes the daisy
chain enable lines for proper control of nested
priority interrupt handling. The eTC decodes
the 2-byte RETI code mternally and determmes
whether it is intended for a channel being serviced. Figure 15 shows RETI timing.
If several 2-80 peripherals are in the daISY
chain, lEI settles active (High) on the chip
currently being serviced when the opcode
ED16 is decoded. If the followmg opcode is
4D16, the peripheral being serviced IS released
and its lEO becomes active. Addihonal wait
states are allowed.
TWA
eLK
\~
_ _ _ _~I
\,-_~I
Do-D7---{
'(====
DATA
----------~~>_----
Figure 14. Interrupt Acknowledge Timing
66
ED
IEI------
______ J
I
IEO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J~
Figure IS. Return From Interrupt Timing
2041·0166,0167,0168
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respectto GND .......... -0.3 V to + 7.0 V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
Stresses greater than those lIsted under Absolute Maximum Rahngs may cause permanent damage to the devlCe.
ThIs IS a stress rating only; operahon of the device at any
condItion above those mdicated In the operatIonal sechOns
of these speclftcatIons 15 not ImplIed. Exposure to absolute
maXImum rating condihons for extended penods may affect
devIce relIabilIty.
The product number for each operating
temperature range may be found in the ordering information section.
'K
• O°C to +70°C,
+4.75 V ~ Vee ~ +5.25 V
• -40°C to +85°C,
+4.75 V ~ Vee ~ +5.25 V
• -55°C to + 125°C,
+4.5 V ~ Vee ~ +5.5 V
DC
Characteristics
Capacitance
Symbol
VILe
VIHe
VIL
lli
.5V
FROM OUTPUT
UNDER TEST
~''I ~ ~~ ~
N
00
Parameter
Min
Max
Unit
Clock Input Low Voltage
-0.3
+0.45
V
Clock Input High Voltage
Input Low Voltage
Vee-·6 Vee+· 3
-0.3
+0.8
V
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output HIgh Voltage
lee
III
Power Supply Current
+ 120
Input Leakage Current
+10
rnA
p.A
ILOH
3-State Output Leakage Current in Float
ILOL
3-State Output Leakage Current m Float
+ 10
-10
p.A
p.A
IOHD
Darlmgton Dnve Current
Symbol
Parameter
+2.0
Vee
+0.4
+2.4
-1.5
Max
Unit
CLK
Clock CapacItance
20
pF
C IN
Input CapacItance
5
pF
C OUT
Output CapacItance
10
pF
Test Condition
V
V
IOL = 2 rnA
V
IOH= 250 p.A
rnA
VIN = 0 to Vee
Your = 2.4 to Vee
Your = 0.4 V
VOH = 1.5 V
REXT = 3900
Condition
Unmeasured pms
returned to ground
TA = 25°C, f = I MHz
8085~0239
67
"~
n
AC
Character-
istics
CLOCK
n
1
~-
I=--\
eSo l CS1
-
CE
:)(
~I
-'
1--<9--
READ
-
\.
lORa
1--0--
~I
0-FI-'
\.
liD
-'
~I
I--®-4-
DATA
~
~r
--®- FI
l(
)t
CSo, CS1
1-0- kD--1
-
L
41
\.
I--- (n·2) TdIEI(IEOf) + TdMI(IEO) + TsIE!(IO)
+ TTL buffer delay If any.
{B] RESET must be active for a mlnlffiUm of 3 clock cycles.
I
NOTES.
[I I TcC = TwCh + TwCl + TrC + TIC.
[21 Increase delay by 10 ns for each 50 pF Increase In loadmg,
200 pF maximum for data hnes, and 100 pF for control hnes.
N
00
C
"
"
Ioi
[3] Increase delay by 2 ns for each 10 pF Increase In \oacimg,
100 pF maximum.
[4J Timer mode.
[5] Counter mode.
[6J RESET must be achve for a minimum of 3 clock cycles
69
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Description
28430
CE
2.5 MHz
280 CTC (28·pin)
28430A
DE
4.0 MHz
280A CTC (28·pin)
28430
CM
2.5 MHz
Same as above
28430A
DS
4.0 MHz
Same as above
28430
CMB
2.5 MHz
Same as above
28430A
PE
4.0 MHz
Same as above
28430
2.5 MHz
Same as above
28430A
PS
4.0 MHz
28430
CS
DE
2.5 MHz
Same as above
28430B
CE
6.0 MHz
Same as above
280B CTC (28·pin)
28430
DS
2.5 MHz
Same as above
28430B
CM
6.0 MHz
Same as above
28430
PE
2.5 MHz
Same as above
28430B
CMB
6.0 MHz
Same as above
28430
PS
2.5 MHz
Same as above
28430B
CS
6.0 MHz
Same as above
28430A
28430A
CE
CM
4.0 MHz
280A CTC (28·pin)
DE
Same as above
DS
6.0 MHz
6.0 MHz
Same as above
4.0 MHz
28430B
28430B
28430A
CMB
4.0 MHz
Same as above
28430B
PE
6.0 MHz
Same as above
28430A
CS
4.0 MHz
Same as above
28430B
PS
6.0 MHz
Same as above
NOTES: C
= CeramIc,
D
= Cerdlp,
P
= Plashc; E = -40°C to
aoc to + 70 C.
MIL-STD-883 Class B processmg, S =
70
Package/
Temp
Speed
+85°C, M
= -55°C to
+ 125°C, MB
= -55°C to
Same as above
+ 125°C WIth
Q
00-2022-A
Z8440
Z80® SIO Serial
Input/Output Controller
~
Zilog
Product
Specification
March 19B1
Features
• Two independent full-duplex channels, with
separate control and status lines for modems
or other devices.
• Data rates of 0 to 500K bits/second in
the xl clock mode with a 2.5 MHz clock
(Z-BO SIO), or 0 to BOOK bits/second with a
4.0 MHz clock (Z-BOA SIO).
• Asynchronous protocols: everything
necessary for complete messages in 5, 6, 7
or 8 bits/character. Includes variable stop
bits and several clock-rate multipliers;
break generation and detection; parity;
overrun and framing error detection.
General
Description
• Highly sophisticated and flexible daisychain interrupt vectoring for interrupts
without external logic.
The Z-80 SIO Serial Input/Output Controller IS a dual-channel data communication
interface with extraordmary versatility and
capability. Its basic functions as a senal-toparallel. parallel-to-serial converter/controller
can be programmed by a CPU for a broad
range of serial communication applications.
The device supports all common asynchronous and synchronous protocols, byte- or
Di~~{' .~;
BUS
-
bit-oriented, and performs all of the functions
traditionally done by UARTs, USARTs and
synchronous communication controllers combined, plus additional functions traditionally
performed by the CPU. Moreover, it does this
on two fully-independent channels, with an
exceptionally sophisticated interrupt structure
tha t allows very fast transfers.
Full mterfacing IS provided for CPU or DMA
0,
SYN'CA -
04
-os
CHANNEL A
WlFffiYA
==~:
1
• Synchronous protocols: everything
necessary for complete bit- or byte-oriented
messages in 5, 6, 7 or 8 bits/character,
mcluding IBM Bisync, SDLC, HDLC,
CCITT-X.25 and others. Automatic CRC
generation/checking, sync character and
zero insertion/deletion, abort generation/detection and flag insertion.
• Receiver data registers quadruply buffered,
transmitter registers doubly buffered.
RlSA)
iNT
elSA _
MODEM
DTRA
CONTROL
BIA
'"
~ Z·BO 510/2 DCDA -
+5V
_M1
F~~~
lORa
R~DB
_
SYNCA
_
RD
Rllee _
R~DA
T~CB
_81A
CHANNEL B
;~
fNr
DAISY {
CONTROL
-
c/o
AD
WIRDYA
_
-c/O
INTE~:':~~
0,
D.
0,
_RESET
CONTROL
D.
0,
0,
_)
lEI
DTRB
lEO
CCDa -
MODEM
CONTROL
iiXilB
A.CA
Rxca
hCA
TxCB
DTAA
DTRB
RlSA
Rlsa
elSA
else
DCOA
Deoe
CLK
RESET
1.-..,1""---'1""---'1,..--1
+5 V
OND
elK
Figure I. Z-80 SI0/2 Pin Functions
2042·0111, 0120
Figure 2. Z-80 SI0/2 Pin Assignments
71
I:c
S
General
Description
(Continued)
control. In addition to data communication, the
circuit can handle virtually all types of serial
I/O with fast (or slow) peripheral devices.
While designed primarily as a member of the
2-80 family, its versatility makes it well suited
to many other CPUs.
The 2-80 S10 is an n-channel silicon-gate
depletion-load device packaged in a 40-pin
plastic or ceramic DIP. It uses a single + 5 V
power supply and the standard 2-80 family
single-phase clock.
Pin
Description
Figures I through 6 illustrate the three pin
configurations (bonding options) available in
the S10. The constraints of a 40-pin package
make it impossible to bring out the Receive
Clock (RxC), Transmit Clock (TxC), Data Terminal Ready (DTR) and Sync (SYNC) signals
for both channels. Therefore, either Channel B
lacks a signal or two signals are bonded
together in the three bonding options offered:
CEo Chip Enable (input, active Low). A Low
• 2-80 S10/2 lacks SYNCB
• 2-80 S1011 lacks DTRB
• 2-80 S10/0 has all four signals, but TxCB
and RxCB are bonded together
The first bonding option above (SI0/2) is the
preferred version for most applications. The
pm descriptions are as follows:
BilL Channel A Or B Select (mput, High
selects Channel B). ThIs input defines whIch
channel is accessed durmg a data transfer
between the CPU and the SIO. Address bit Ao
from the CPU is often used for the selection
function.
C/D. Control Or Data Select (mput, HIgh
selects Control). This mput defines the type of
information transfer performed between the
CPU and the SIO. A HIgh at this input during
a CPU write to the SIO causes the information
on the data bus to be interpreted as a command for the channel selected by BIJL A Low
at c/lS means that the mformahon on the data
bus IS data. Address bit Aj IS often used for
this function.
-
D~
SYNCA
-
Os
WiRDYA
1
CONTROL
F~~~
CTSA, CTSB. Clear To Send (inputs, active
Low). When programmed as Auto Enables, a
Low on these inputs enables the respective
transmitter. If not programmed as Auto
Enables, these inputs may be programmed as
general-purpose inputs. Both inputs are
Schmitt-trigger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these inputs and interrupts the CPU on both
logIC level transitions. The Schmltt-tngger buffering does not guarantee a spectfied noiselevel margin.
Do-D7' System Data Bus (bidirectIOnal,
3-state). The system data bus transfers data
and commands between the CPU and the 2-80
SIO. Do is the least significant bit.
DCDA, DCDB. Data Carrier Detect (inputs,
active Low). These pms function as receiver
enables if the SIO is programmed for Auto
Enables; otherwIse they may be used as
general-purpose mput pms. Both pins are
Schmltt-tngger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these pins and interrupts the CPU on both
logIC level translhons. Schmitt-trigger buffer-
CHANNEL A
RID _ _
eTSA
DfJfJ1.
1
MODEM
CONTROL
~~:T '·80 .,011 ;~;; •
_
AD
TxOB
_
c/o
SYNCB
_
W/RDYB
TxCB
g~~~~ { -
CLK. System Clock (input) .. The SIO uses the
standard 2-80 System Clock to synchromze
internal signals. This is a single-phase clock.
RxDA_
D~;~l ~
== :
BUS
level at this input enables the S10 to accept
command or data input from the CPU during a
write cycle or to transmit data to the CPU
during a read cycle.
_
~::: - ] ~g:;:OL
:
INTERRUPT
CONTROL
CHANNEL B
DeDe -
111
+sv
GND
elK
Figure 3. Z-80 SIO!l Pin Functions
72
Figure 4_ Z-80 SIO!l Pin Assignments
2042·0111,0120
Pin
Description
(Continued)
ing does not guarantee a specific noise-level
margin.
DTRA. DTRB. Data Terminal Ready (outputs,
achve Low). These outputs follow the state programmed mto Z-80 SIO. They can also be programmed as general-purpose outputs.
In the Z-80 SIOIl bondmg ophon, DTRB is
omItted.
lEI. Interrupt Enable In (input, active High).
This sIgnal IS used with lEO to form a prionty
daISY chain when there is more than one
mterrupt-driven device. A HIgh on this line
mdicates that no other deVIce of hIgher priority IS bemg servIced by a CPU interrupt servIce routme.
lEO. Interrupt Enable Out (output, active
High). lEO is High only If lEI is High and the
CPU IS not servicing an mterrupt from thIS
S10. Thus, thIS signal blocks lower priority
deVICes from mterrupting while a higher
pnonty deVIce IS bemg serviced by ItS CPU
mterrupt servIce routme.
INT. Interrupt Request (output, open drain,
acllve Low). When the S10 IS requestmg an
mterrupt, It pulls 1NT Low.
IORQ. Input/Output Request (input from CPU,
active Low). IORQ is used in conjunction WIth
BIA, CllS, CE and RD to transfer commands
and data between the CPU and the SIO. When
CE, RD and IORQ are all active, the channel
selected by BIA transfers data to the CPU (a
read operatIOn). When CE and IORQ are
active but RD is inactive, the channel selected
by BIA IS written to by the CPU with either
data or control mformation as specified by
C/lS. If IORQ and Ml are active simultane-
D.
~;
SYNCA
--05
WIRDYA
cpu!
DATA
BUS
-
RxCA. RxCB. Receiver Clocks (inputs).
Receive data is sampled on the rising edge of
RxC. The Receive Clocks may be I, 16,32 or
64 limes the data rate in asynchronous modes.
These clocks may be driven by the Z-80 CTC
Counter Timer CircUlt for programmable baud
rate generation. Both inputs are Schmitttngger buffered (no noise level margin is
specified).
In the Z-80 SIOIO bondmg option, RxCB is
bonded together with TxCB.
RD. Read Cycle Status (input from CPU,
active Low). If RD is active, a memory or 1/0
read operallon IS m progress. RD is used with
BIA, CE and IORQ to transfer data from the
SIO to the CPU.
RxDA. RxDB. Receive Data (inputs, active
High). Serial data at TTL levels.
RESET. Reset (input, active Low). A Low
RESET disables both receIvers and transmitters, forces TxDA and TxDB marking, forces
the modem controls HIgh and disables all
mterrupts. The control registers must be
0,
==::
_1
ously, the CPU is acknowledging an interrupt
and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest
priority device requesting an interrupt.
Ml. Machine Cycle (input from Z-80 CPU,
acllve Low). When Ml is active and RD is also
active, the Z-80 CPU is fetching an instruction
from memory; when MI is active while IORQ is
active, the SIO accepts MI and IORQ as an
interrupt acknowledge if the SIO is the highest
prionty device that has interrupted the Z-80
CPU.
0,
___
CHANNEL A
0,
RTSA)
z·ao SIOIO
CE
i'Nf
c""" -
MODEM
:-: -
CONTROL
'"
_RESET
_Ml
CONTROL
F~~~
_
0,
WTR1iYA
lORD
R~DB
_ _ RO
_
SYNCA
iiifiCB _
hCA
SYNCB_
-_CJD
_BIA
WIRDYS
R~CA
hOB
WIRDYB
CHANNEL B
OTRA
RlSA
DAISY {
INTE~~~~~
CONTROL
--
ffif
;: _ )
MODEM
elSA
lEI
DTRB
CONTROL
ilCOA
lEO
peoa _
RESET
I II
+5V
GNO
elK
Figure 5. Z-80 SIO/O Pin Functions
2042-0111. 0120
Figure 6. Z-80 SIO/O Pin Assignment.
73
Pin
Description
(Continued)
rewritten after the SIO IS reset and before data
IS transmitted or receIved.
RTSA. RTSB. Request To Send (outputs,
active Low). When the RTS bIt in Write
Register 5 (Figure 14) IS set, the RTS output
goes Low. When the RTS bIt is reset in the
Asynchronous mode, the output goes HIgh
after the transmitter IS empty. In Synchronous
modes, the RTS pm strictly follows the state of
the RTS bit. Both pins can be used as generalpurpose outputs.
SYNCA. SYNCB. Synchronization (inputs/outputs, active Low). These pins can act eIther as
mputs or outputs. In the asynchronous receive
mode, they are inputs slmllar to CTS and
DCD. In this mode, the transitions on these
lines affect the siate of the Sync/Hunt status
bIts in Read Register 0 (Figure 13), but have
no other funchon. In the External Sync mode,
these Imes also act as mputs. When external
synchromzahon IS achIeved, SYNC must be
driven Low on the second rising edge of RxC
after that rising edge of RxC on which the last
bit of the sync character was rec61ved. In
other words, after the sync pattern is detected,
the external logic must walt for two full
Receive Clock cycles to activate the SYNC
input. Once SYNC IS forced Low, il should be
kept Low unhl the CPU informs the external
synchronization detect logic that synchronizahon has been lost or a new message is about to
start. Character assembly begms on the rising
edge of RxC that Immediately precedes the
fallmg edge of SYNC in the External Sync
mode.
In the internal synchromzahon mode
(Monosync and Bisync), these pins act as outputs that are active during the part of the
receive clock (RxC) cycle in which sync
characters are recognized. The sync condition
is not latched, so these outputs are active each
hme a sync pattern is recognizt;ld, regardless
of character boundaries.
In the Z-80 SIO/2 bonding option, SYNCB
is omitted.
TxCA. TxCB. Transmitter Clocks (inputs). In
asynchronous modes, the Transmitter Clocks
may be 1, 16, 32 or 64 times the data rate;
however, the clock multiplier for the transmitter and the receiver must be the same. The
Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements (no noise level margin is speCified).
Transmitter Clocks may be driven by the Z-80
CTC Counter Timer Circuit for programmable
baud rate generation.
In the Z-80 SIO/O bonding option. TxCB is
bonded together with RxCB.
TxDA. TxDB. Transmit Dafa (outputs. active
High). Serial data at TTL levels. TxD changes
from the falling edge of TxC.
-----WIRDYA. WIRDYB. Waif/Ready A, Wait/
Ready B (outputs, open drain when programmed for Wait funchon, driven High and
Low when programmed for Ready function).
These dual-purpose outputs may be programmed as Ready lines for a DMA controller
or as Wail lines that synchronize the CPU to
the S10 data rate. The reset state is open
drain.
. . . - - } SERIAL DATA
~}
CHANNEL CLOCKS
SYNC
WAIT/READY
INTERNAL
CONTROL
LOGIC
MODEM OR
OTHER CONTROLS
DATA
CPU
BUS 110
CONTROL
CHANNEL B
CONTROL
MODEM OR
OTHER CONTROLS
AND
STATUS
INTERRUPT
CONTROL - - .
LINES
INTERRUPT
CONTROL
LOGIC
CHANNEL B
-l
:=
SERIAL DATA
CHANNEL CLOCKS
SYNC
WAIT/READY
Figure 7. Block Diagram
74
2042·0106
Functional
Description
The functional capabilihes of the Z-80 S10
can be described from two different points of
view: as a data communications device, it
transmits and receives serial data in a wide
variety of data-communication protocols; as a
Z-80 family peripheral, it interacts with the
Z-80 CPU and other peripheral circuits, sharmg the data, address and control buses, as
well as being a part of the Z-80 interrupt structure. As a peripheral to other microprocessors,
the S10 offers valuable features such as nonvectored interrupts, polling and simple handshake capability.
Figure 8 illustrates the conventional devices
that the S10 replaces.
The first part of the following discussion
covers S10 data-communication capabilities;
the second part describes interactions between
the CPU and the S10.
CHANNEL
A
MICROPROCESSOR
INTERFACE
J
1
CHANNEL
B
B
MICROPROCESSOR
INTERFACE
...........
%.80
510
CHANNEL
A
.....- CHANNEL
B
Figure 8. Conventional Devices Replaced by the Z-80 SIO
Data
Communication
Capabilities
The S10 provides two independent fullduplex channels that can be programmed for
use in any common asynchronous or synchronous data-communication protocol. Figure 9
illustrates some of these protocols. The following IS a short description of them. A more
detailed explanation of these modes can be
found in the Z-80 SIO Technical Manual.
Asynchronous Modes. Transmission and
reception can be done independently on each
channel with five to eight bits per character,
plus optional even or odd parity. The transmitters can supply one, one-and-a-half or two stop
bits per character and can provide a break
output at any time. The receiver breakdetechon logic interrupts the CPU both at the
start and end of a received break. Reception is
protected from spikes by a transient spikerejechon mechanism that checks the signal
one-half a bit hme after a Low level is detected
on the receive data input (RxDA or RxDB in
Figure 5). If the Low does not persist-as in
the case of a transient-the character assembly
process is not started.
Framing errors and overrun errors are
detected and buffered together with the partial
character on whICh they occurred .. Vectored
2042·0107
interrupts allow fast servicing of error condihons using dedICated routines. Furthermore, a
built-in checking process avoids interpreting a
framing error as a new start bit: a framing
error results in the addition of one-half a bit
time to the point at which the search for the
next start bit is begun.
The S10 does not require symmetric transmit
and receive clock signals-a feature that
allows it to be used with a Z-80 CTC or many
other clock sources. The transmitter and
receiver can handle data at a rate of 1, 1/16,
1/32 or 1164 of the clock rate supplied to the
receive and transmit clock inputs.
In asynchronous modes, the SYNC pin may
be programmed as an input that can be used
for functions such as monitoring a ring
indicator.
Synchronous Modes. The S10 supports both
byte-oriented and bit-oriented synchronous
communication.
Synchronous byte-oriented protocols can be
handled m several mod!3s that allow character
synchronization with an 8-blt sync character
(Monosync), any 16-bit sync pattern (Bisync),
or with an external sync signal. Leading sync
75
Data
Communication
Capabilities
(Continued)
characters can be removed without interrupting the CPU.
Five-, six- or seven-bit sync characters are
detected with 8- or 16-bit patterns in the SIO
by overlapping the larger pattern across multiple in-coming sync characters, as shown in
Figure 10.
CRC checking for synchronous byteoriented modes is delayed by one character
time so the CPU may disable CRC checking on
specific characters. This permits implementation of protocols such as IBM Bisync.
Both CRC-16 (X 16 + XI5 + X2 + 1) and
CCITT (X16 + XI2 + X5 + 1) error checking
polynomials are supported. In all non-SDLC
modes, the CRC generator is initialized to O's;
in SDLC modes, it is initialized to I's. The SIO
can be used for interfacing to peripherals such
as hard-sectored floppy disk, but it cannot
generate or check CRC for IBM-compatible
soft-sectored disks. The SIO also provides a
feature that automatically transmits CRC data
when no other data is available for transmission. This allows very high-speed transmissions
under DMA control with no need for CPU
'
intervention at the end of a message. When
there is no data or CRC to send in synchronous modes, the transmitter inserts 8- or
16-bit sync characters regardless of the programmed character length.
The SIO supports synchronous bit-oriented
protocols such as SDLC and HDLC by performing automatic flag sending, zero insertion
and CRC generation. A special command can
be used to abort a frame in transmission. At
the end of a message the SIO automatically
transmIts the CRC and trailing flag when the
transmit buffer becomes empty. If a transmit
____---..sr.
II
MARK'NG LINE
PAPi
underrun occurs in the middle of a message,
an external/status interrupt warns the CPU of
this status change so that an abort may be
Issued. One to eight bits per character can be
sent, which allows reception of a message with
no prior information about the character structure in the information field of a frame.
The receIver automatically synchronizes on
the leading flag of a frame in SDLC or HDLC,
and provides a synchronization signal on the
SYNC pin; an interrupt can also be programmed. The receiver can be programmed to
search for frames addressed by a single byte to
only a specified user-selected address or to a
global broadcast address. In thIS mode, frames
that do not match eIther the user-selected or
broadcast address are ignored. The number of
address bytes can be extended under software
control. For transmitting data, an interrupt on
the first received character or on every
character can be selected. The receiver
automatically deletes all zeroes inserted by the
transmitter during character assembly. It also
calculates and automatically checks the CRC
to validate frame transmiSSIOn. At the end of
transmission, the status of a received frame IS
available in the status regIsters.
The SIO can be conveniently used under
DMA control to provide high-speed reception
or transmission. In reception, for example, the
SIO can interrupt the CPU when the hrst
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The SIO then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message IS
bemg received.
op
II ' LI:1=DA=T=A=1=1-"""111
DATA
DATA
II'
t MARKING LINE
ASYNCHRONOUS
SYNC
I
~:MONOSYNC
DATA
SYNC
::
::
DATA
SYNC
SIGNAL
I
t
DATA
DATA
CAe1
CRe2
DATA
CAe1
CRe2
DATA
CAel
CRe:!
CAe1
CRe:!
alSYNC
EXTERNAL SYNC
FLAG
I
ADDRESS
I
INFO~M;TION
FLAG
SDLC/HDLC/X.25
Figure 9. Some
z-ao SIO Protocols
6 BITS
~
SYN~
SYNC
DATA
DATA
DATA
DATA
~
' -_ _~v~___8~_ _
16
Figure 10.
76
2042·0108,0109
1/0 Interface
Capabilities
The SIO offers the choice of polling, interrupt (vectored or non-vectored) and blocktransfer modes to transfer data, status and control information to and from the CPU. The
block-transfer mode can also be implemented
under DMA control.
CPU is interrupted by the transmit buffer
becoming empty. (This implies that the
transmitter must have had a data character
written into it so it can become empty.) The
receiver can interrupt the CPU in one of two
ways:
Polling. Two status registers are updated at
appropriate times for each function being performed (for example, CRC error-status valid at
the end of a message). When the CPU is
operated in a polling fashion, one of the SIO's
two status registers is used to indicate whether
the SIO has some data or needs some data.
Depending on the contents of thIs register, the
CPU will either write data, read data, or just
go on. Two bits in the register indicate that a
data transfer is needed. In addition, error and
other conditions are indicated. The second
status register (special receive condihons) does
not have to be read m a polling sequence,
until a character has been received. All mterrupt modes are disabled when operatmg the
device in a polled environment.
• Interrupt on first received character
Interrupts. The SIO has an elaborate interrupt
scheme to provide fast interrupt service in
real-time applications. A control register and a
status register in Channel B contain the interrupt vector. When programmed to do so, the
SIO can modify three bits of the interrupt vector in the status register so that it points dIrectly to one of eight mterrupt service routines in
memory, thereby serVICing condItions in both
channels and ehminating most of the needs for
a status-analysis routme.
Transmit interrupts, receIve interrupts and
external/status interrupts are the main sources
of mterrupts. Each interrupt source is enabled
under program control, with Channel A having a higher priority than Channel B, and WIth
receive, transmit and external/status interrupts
priorihzed in that order within each channel.
When the transmit interrupt is enabled, the
• Interrupt on all rec81ved characters
Interrupt-on-first-received-character IS
typically used with the block-transfer mode.
Interrupt-on-all-received-characters has the
ophon of modifying the interrupt vector in the
event of a parity error. Both of these interrupt
modes WIll also interrupt under special receive
conditions on a character or message baSIS
(end-of-frame interrupt in SDLC, for example).
This means that the special-receive condition
can cause an mterrupt only if the interrupt-onfirst-recelved-character or interrupt-on-allreceIVed-characters mode IS selected. In
interrupt-on-first-recelved-character, an mterrupt can occur from special-receIVe conditions
(except parity error) after the first-receivedcharacter mterrupt (example: receive-overrun
interrupt).
The mam function of the external/status
interrupt is to mom tor the SIgnal transihons of
the Clear To Send (CTS), Data Carrier Detect
(DCD) and Synchronizahon (SYNC) pins
(Figures 1 through 6). In addition, an external/status interrupt IS also caused by a CRCsendmg condItion or by the detechon of a
break sequence (asynchronous mode) or abort
sequence (SDLC mode) in the data stream.
The mterrupt caused by the break/abort
sequence allows the SIO to mterrupt when the
break/abort sequence is detected or terminated. This feature faCIlitates the proper termination of the current message, correct
imtiahzahon of the next message, and the
accurate timing of the break/abort condihon m
external logIC.
77
N
00
c
is
I/O Interface
Capabilities
(Continued)
In a 2-80 CPU environment (Figure II), SIO
interrupt vectormg IS "automahc": the SIO
passes its mternally-modlfiable 8-bit interrupt
vector to the CPU, whIch adds an additional 8
bIts from ItS interrupt-vector (I) register to form
the memory address of the interrupt-routine
table. This table contams the address of the
begmmng of the mterrupt routme Itself. The
process entads an mdlrect transfer of CPU
control to the mterrupt routine, so that the
next mstruction executed after an mterrupt
acknowledge by the CPU is the first instruction
of the interrupt routine Itself.
SYSTEM
BUSES
DMA
CPU
INT
ROY
lEI
+5V
T
CPU/DMA Block Transfer. The SIO's blocktransfer mode accommodates both CPU block
transfers and DMA controllers (2-80 DMA or
other designs). The block-transfer mode uses
the Wait/Ready output signal, which is
selected with three bits in an internal control
register. The Walt/Ready output sIgnal can be
programmed as a WAIT Ime in the CPU blocktransfer mode or as a READY Ime m the DMA
block-transfer mode.
To a DMA controller, the SIO READY output
mdicates that the SIO IS ready to transfer data
to or from memory. To the CPU, the WAIT output mdicates that the SIO is not ready to
transfer data, thereby requestmg the CPU to
extend the 1/0 cycle.
lEi
ZCITOl
CTC
lEO
iNT
lEO
WIRDVA
WiRDYs
SID
--'---..
~
-
iNr
lEI
ROY
DMA
Figure 11. Typical Z-80 Environment
Internal
Structure
The internal structure of the deVICe mcludes
a 2-80 CPU interface, internal control and
interrupt logiC, and two full-duplex channels.
Each channel contains its own set of control
and status (write and read) registers, and control and status logic that provides the interface
to moderns or other external devices.
The registers for each channel are designated as follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The register group includes five 8-bit control
registers, two sync-character registers and two
status registers. The interrupt vector is written
into an additional 8-bit register (Write Register
2) in Channel B that may be read through
another 8-bit register (Read Register 2) in
Channel B. The bit assignment and functional
grouping of each register is configured to
simplify and organize the programming process. Table I lists the functions assigned to
each read or write register.
78
Read Register Functions
RRO
RRI
RR2
Transmit/Receive buffer status, interrupt
status and external status
Special Receive Condition status
Modified interrupt vector (Channel B only)
Write Register Functions
WRO Register pointers, CRC initialize, initialization commands for the various modes, etc.
WRI Transmit/Receive interrupt and data transfer
mode definition.
WR2 Interrupt vector (Channel B only)
WR3 Receive parameters and control
WR4 Transmit/Receive miscellaneous parameters
and modes
WR5 Transmit parameters and controls
WR6 Sync character or SDLC address field
WR7 Sync character or SDLC flag
2032·0127
Internal
Structure
(Continued)
The logic for both channels provIdes formats, synchronization and validation for data
transferred to and from the channel interface.
The modem control inputs, Clear To Send
(CTS) and Data Carner Detect (DCD), are
monitored by the external control and status
logic under program control. All external
control-and-status-logic signals are generalpurpose in nature and can be used for functions other than modem control.
Data Path. The transmit and receive data path
Illustrated for Channel A in Figure 12 is identical for both channels. The receiver has three
8-bit buffer registers in a FIFO arrangement,
m addition to the 8-blt receive shift register.
ThIs scheme creates addihonal time for the
CPU to service an mterrupt at the beginning of
a block of high-speed data. Incoming data is
routed through one of several paths (data or
CRC) depending on the selected mode
and-in asynchronous modes-the character
length.
The transmitter has an 8-bit transmit data
buffer register that is loaded from the internal
data bus, and a 20-blt transmIt shift regIster
that can be loaded from the sync-character
buffers or from the transmit data register.
Depending on the operahonal mode, outgomg
data IS routed through one of four mam paths
before it IS transmllted from the TransmIt Data
output (TxD).
N
CPU 110
oo~l"
RECEIVE
RxCA - .
s
==
TxDA
CLOCK
LOGIC
HUNT MODE (BISYNC)
r----------,
Figure 12. Transmit and Receive Data Path (Channel A)
2042-0112
79
Programming
The system program first Issues a series of
commands that imtiahze the baslC mode of
operahon and then other commands that
qualify condihons within the selected mode.
For example, the asynchronous mode,
character length, clock rate, number of stop
bits, even or odd panty might be set first; then
the interrupt mode; and finally, receiver or
transmitter enable.
Both channels contain registers that must be
programmed via the system program pnor to
operation. The channel-select input (BfA) and
the control/data input (C/lS) are the commandstructure addressing controls, and are normally controlled by the CPU address bus. Figures
15 and 16 illustrate the timmg relationshIps for
programming the wnte registers and transferring data and status.
Read Registers. The SIO contains three read
registers for Channel B and two read registers
for Channel A (RRO-RR2 in FIgure 13) that can
be read to obtain the status informahon; RR2
contains the internally-modIhable interrupt
vector and is only m the Channel B register
set. The status information mcludes error conditions, mterrupt vector and standard
communications-interface sign;Jls.
To read the contents of a selected read
register other than RRO, the system program
must first write the pomter byte to WRO in
exactly the same way as a write register operation. Then, by executing a read instruction,
the contents of the addressed read register can
be read by the CPU.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring. For
example, when the mterrupt vector mdicates
that a SpecIal Rec81ve Condition interrupt has
occurred, all the appropriate error bits can be
read from a single regIster (RRl).
Write Registers. The SIO contains eight write
WRO is a special case in that all of the baSIC
commands can be written to It with a single
byte. Reset (internal or external) imtializes the
pointer bits Do-D2 to point 10 WRO. This
implies that a channel reset must not be combined with the pointing to any register.
READ REGISTER 0
III
~I
IL..::::INTPENDING(CH
L-
R, CHARACTER AVAILABLE
A ONLY)
h~~UFFER
EMPTY
}
SYNC/HUNT
CTS
Tx UNOERRUNIEOM
BREAK/ABORT
•
READ REGISTER It
10,[0,[0,[0 [0,[0, [0, [0 1
.
"
L-ALLSENT
III
1
0
1
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
IFI ELO BITS
I FIELD BITS IN
}
IN PREVIOUS SECOND PREVIOUS
BYTe
BYTE
o
3
o
4
o
o
o
o
6
7
8
1
,
8
8
-PARITY ERR OR
L - - Rx OVEAAU N ERROR
5
•
'Residue Data
Rx Bits/Character
-CACIFRAMI NO ERROR
END OF FA AME (SOLe)
rUsed With SpeCial Receive Condition Mode
READ REGISTER 2
Figure 13. Read Register Bit Functions
registers for Channel B and seven write
registers for Channel A (WRO- WR7 m FIgure
14) that are programmed separately to configure the funchonal personality of the channels; WR2 contains the mterrupt vector for
both channels and is only m the Channel B
register set. With the exception of WRO, programmmg the wnte registers reqUlres two
bytes. The hrst byte IS to WRO and contams
three bIts (Do-D2) that pomt to the selected
register; the second byte IS the actual control
word that IS written into the regIster to configure the SIO.
80
2042·0114
Programming
(Continued)
WRITE REGISTER 0
WRITE REGISTER 4
ID,ID.IDdD.ID, ID, 10, ID, I
I~I~I~I~I~I~I~I~I
II
I I I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
1
L--PARITY ENABLE
PARITY EVEN/ODD
SYNC MODES ENABLE
1 STOP B1T/CHAAACTER
1'h STOP BITSJCHARACTER
2 STOP BITS/CHARACTER
3
4
5
6
7
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
0 NULL CODE
1 SEND ABO RT (SOLC)
0 RESET EXTI STATUS INTERRUPTS
1 CHANNEL RESET
0 ENABLE IN T ON NEXT Rx CHARACTER
1 RESET Txll NT PENDING
0 ERROR RES ET
1 RETURN FR OM INT (CH A ONLY)
SOle MODE (01111110 FlAG)
EXTERNAL SYNC MODE
Xl CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRe GENERATOR
RESET Tx UNDERRUN/EOM LATCH
WRITE REGISTER 5
WRITE REGISTER I
I~I~I~I~I~I~I~I~I
~II
I
L-EX.TINTENABLE
Tx INT ENABLE
STATUS AFFECTS VECTOR
(CH B ONLY)
~ ! ~T:~i ~~~!~:~HC:RAARtr~~ESR(PARITY
1
1
AFFECTS VECTOR) }
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)
•
I
~
o
o
0
1
1
1
0
1
I
~~iRC
IIL~~·I====SDLC/CRC.16
I
1;11.
Tx
Tx
Tx
5
7
6
B
WRITE REGISTER 2 (CHANNEL B ONLY)
WRITE REGISTER 6
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
"
V4
V5
UI
S
BITS (OR LESS)/CHARACTEA
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
DTR
~READY ON R/T
WAIT/READY FUNCTION
'----WAIT/READy ENABLE
I1I1I I L'==;!
N
GO
C
ENABLE
h. ENABLE
SEND BREAK
I1IIII ~i~~HiH 1
SYNC
SYNC
SYNC
SYNC
SYNC
llNTERRUPT
VECTOR
V6
V7
BIT
BIT
BIT
B[T
BIT
3
4
5
6
7
•
"Also SOLe Address Field
WRITE REGISTER 7
WRITE REGISTER 3
II1I
Rx
Rx
Rx
Rx
5
7
6
8
I~SYNC
L - R, ENABLE
CHARACTER LOAD INHIBIT
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
ADDRESS SEARCH MODE (SOLe)
Rx CRe ENABLE
ENTER HUNT PHASE
AUTO ENABLES
I1I1II L'=l:~!;!.l
::i .
~~~g
~~
SYNC BIT 13
SYNC BIT 14
SYNC BIT 15
"For SOLe It Musl Be
1001111110 ForFlag
Figure 14. Write Register Bit Functions
2042·0113
81
Timing
The SIO must have the same clock as the
CPU (same phase and frequency relationship,
not necessarily the same driver).
Read Cycle. The timing signals generated by
a 2-80 CPU input instruction to read a data or
status byte from the SIO are illustrated in
Figure 15.
Write Cycle. Figure 16 illustrates the timing
and data signals generated by a 2-80 CPU output instruction to write a data or control byte
into the SIO.
Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an SIO
(iNT pulled Low). the 2-80 CPU sends an
interrupt-acknowledge sequence (MI Low, and
IORQ Low a few cycles later) as in Figure 17.
The SIO contains an internal daisy-chained
interrupt structure for prioritizing nested interrupts for the various functions of its two channels, and this structure can be used within
an external user-defined daisy chain that
prioritizes several peripheral circuits.
The IEI of the highest-priority device is
terminated High. A device that has an interrupt pending or under service forces its IEO
Low. For devices with no interrupt pending or
under service, lEO = lEI.
To insure stable conditions in the daisy
chain, all interrupt status signals are prevented from changing while MI is Low. When
IORQ is Low, the highest priority interrupt
requestor (the one with lEI High) places its
interrupt vector on the data bus and sets its
T,
T,
T,
TW
Return From Interrupt Cycle. Figure 18
illustrates the return from interrupt cycle.
Normally, the 2-80 CPU issues a RET! (Return
From Interrupt) instruction at the end of an
interrupt service routine. RET! is a 2-byte
opcode (ED-4D) that resets the interruptunder-service latch in the SIO to terminate the
interrupt that has just been processed. This is
accomplished by manipulating the daisy chain
in the follOWing way.
The normal daisy-chain operation can be
used to detect a pending interrupt; however, it
cannot distinguish between an interrupt under
service and a pending unacknowledged interrupt of a higher priority. Whenever "ED" is
decoded, the daisy chain is modified by forcing High the lEO of any interrupt that has not
yet been acknowledged. Thus the daisy chain
identifies the device presently under service as
the only one with an lEI High and an lEO Low.
If the next opcode byte is "4D:' the interruptunder-service latch is reset.
The ripple time of the interrupt daisy chain
(both the High-to-Low and the Low-to-High
transitions) limits the number of devices that
can be placed in the daisy chain. Ripple time
can be improved with carry-look-ahead, or by
extending the interrupt-acknowledge cycle.
For further information about techniques for
increasing the number of daisy-chained
devices, refer to the Z-80 CPU Product
Specification.
T,
T,
T,
TW
T,
TW
T,
CLOCK
CLOCK
CE r CID, BIA
internal interrupt-under-service latch.
--~'~~--4-----~~
OR ~\.._____---I:...JI
1
'-----+-I
iii) - - - - - - - - - - - - - - -...
1----
\====:
---------~r--~I~
OR----------------~------------DATA----______________
~
lEI _ _ _ _ _ _ _ _ _
DATA
T2
Tw
T3
iii)
------------1.
VECTOR ) . . . . - - - - -
T1
.....CLOCK~
,.,~
10RQ'
:
Figure 17. Interrupt Acknowledge Cycle
Figure 15. Read Cycle
T,
1
CLOCK
1
1
1
1
iii)~----
~
1
1
Do-Dr
1
M1-----------------~I---------I
DATA ________________~~_____
lEI
)-;1-------
-------,.,---------+----------.1
.......,r-
lEO _ _ _ _ _ _ _ _ _
Figure 16. Write Cycle
82
Figure 18. Return from Interrupt Cycle
2044-008,009, OW, 011
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
As SpeCified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This IS a stress rating only; operation of the device at any
condition above those indicated in the operallonal secllons
of these specificallons IS not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliab!llly.
Test
Conditions
The characteristics below apply for the
ifollowing test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
The product number for each operating
temperature range may be found in the ordering information section_
.sv
2IK
• O°C to +70°C,
+4.75 V S Vee S +5.25 V
• -40°C to +85°C,
+4.75 V S Vee S +5.25 V
• -55°C to + 125°C,
+4.5 V S Vee S +5.5 V
DC
Symbol
I
Parameter
Min
Max
Unit
VILe
VlHe
VIL
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
-0.3
+0.45
V
V IH
VOL
VOH
Output Low Voltage
Output High Voltage
Test Condition
Charac-
teristics
Vee -0.6 +5.5
-0.3
+0.8
Input High Voltage
+2.0
V
V
+5.5
V
+0.4
V
V
p.A
p.A
p.A
rnA
+2.4
ILl
Input Leakage Current
3-State Output/Data Bus Input Leakage Current
-10
-10
+10
Iz
IL(8Y)
SYNC Pm Leakage Current
-40
+10
Icc
Power Supply Current
+10
100
IOL = 2.0 mA
IOH = -250 p.A
O<==
..JX'-_____'N_____
DATA ___________
Figure 5a. Read Cycle
Figure 5b.· Write Cycle
CLOCK
M1
...J!
~'-__________________
' . . . _...J!
AD----------------------------------lEI
=========7
\_====
7
------.1
lEI - - - -
DATA-------------------~~~------lEO
Figure 5c. Interrupt Acknowledge Cycle
94
-
_____
,---
~I
Figure 5d. Return from Interrupt Cycle
2044-008.009.010,011
Z-80 DART
To program the 2-80 DART, the system pro-
Programming gram first issues a series of commands that
initialize the basic mode and then other commands that qualify conditions within the selected mode. For example, the character length,
clock rate, number of stop bits, even or odd
parity are first set, then the Interrupt mode
and, finally, receiver or transmitter enable.
Both channels contain command registers
that must be programmed via the system program prior to operation. The Channel Select
mput (B/A) and the Control/Data input (CiD)
are the command structure addressing controls, and are normally controlled by the CPU
address bus.
Write Registers. The 2-80 DART contains six
registers (WRO-WR5) in each channel that are
programmed separately by the system program
to conflgure the funchonal personality of the
channels (Figure 4). With the exception of
WRO, programming the write registers requires
two bytes. The first byte contains three bits
(D o-D 2) that point to the selected register; the
second byte is the actual control word that is
written into the register to configure the 2-80
DART.
WRO is a special case in that all the basic
commands (CMD o-CMD2) can be accessed
with a single byte. Reset (internal or external)
initializes the pOinter bits Do-D2 to point to
WRO. This means that a register cannot be
pointed to m the same operation as a channel
reset.
Read Registers. The 2-80 DART contains
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring. For
example, when the interrupt vector indicates
that a Special Receive Condition interrupt has
occurred, all the appropriate error bits can be
read from a single register (RRI).
three registers (RRO-RR2) that can be read to
obtain the status information for each channel
(except for RR2, which applies to Channel B
only). The status information mcludes error
conditions, interrupt vector and standard
communications-interface signals.
To read the contents of a selected read
register other than RRO, the system program
must first write the pointer byte to WRO in
exactly the same way as a write register operation. Then, by executing an input instruction,
the contents of the addressed read register can
be read by the CPU.
Write Register Functions
WRO
Register pomters, Imtialization commands for
the vanous modes, etc.
WRI Transmit/Receive interrupt and data transfer
mode definition.
WR2 Interrupt vector (Channel B only)
WR3 Receive parameters and control
WR4 Transmit/Receive miscellaneous parameters
and modes
WR5 Transmit parameters and controls
Read Register Functions
RRO
RRI
RR2
Transmit/Receive buffer status, mterrupt
status and external status
SpeCial Receive Condition status
Modified interrupt vector (Channel B only)
95
N
00
0
a
•...=-
Z-80 DART
Read and Write
Registers
READ REGISTER 0
L
~l§ug
R,CHARACTERAVAILABlE
INT PENDING (CH A ONLY)
Tx BUFFER EMPTY
:~D
crs
}
NOT USED
USED WITH "EXTERNAL!
STATUS INTERRUPT"
MODE
' - - - - - - - - BREAK
READ REGISTER 2
READ REGISTER I'
I~I~I~I~I~I~I~I~I
§~
--r-
I ug ~~::)
~
LAllSENT
~NOTUSED
,
PARITY ERROR
Ax OVERRUN ERROR
EV4
FRAMING ERROR
INTERRUPT
VECTOR
V5
NOT USED
'Used With SpeCial Receive Condition Mode
V6
'--------------V7
WRITE REGISTER 0
WRITE REGISTER I
"NT'~!
I~I~I~I~I~I~I~I~I
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
T
o
o
1
o
o
o
o
0
NULL CODE
a
NOT USED
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INT ON NEXT Ax CHARACTER
REseT TxlNT PENDING
ERROR RESET
RETURN FROM INT(CHAONLY)
1
1
0
0
1
1
1
1
11
' - - - - - - - N O T USED
IN~g~s~L~TR;FCF~~~Av~~ET~SRrARITY
CONDITION
L-______ WAIT/READY ON R/T
' - - - - - - - - - WAIT/READY FUNCTION
' - - - - - - - WAIT/READY ENABLE
WRITE REGISTER 3
I~I~I~I~I~I~I~I~I
T
I ug~; )
~
Tx INT ENABLE
STATUS AFFECTS VECTOR
(CH B ONLY)
0
Ax INT DISABLE
}
1
Rx tNT ON FIRST CHARACTER
OR ON
OINT ON ALL Ax CHARACTERS (PARITY
SPECIAL
AFFECTS VECTOR)
RECEIVE
WRITE REGISTER 2 (CHANNEL B ONLY)
EV4
L EXT INT ENABLE
~
L-
0
1
2
3
4
5
L~_
~NOTUSED
LL A,ENABlE
AUTO ENABLES
Rx
Rx
Rx
Rx
INTERRUPT
VECTOR
V5
5
7
6
6
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
V6
~---------------V7
WRITE REGISTER 4
W
WRITE REGISTER 5
I~I~I~I~I~I~I~I~I
I L PARITY ENABLE
L- PARITY EVEN/ODD
o
o
0
1
0
1
1
o
o
1
1
96
1
NOT USED
1 STOP BIT/CHARACTER
1 V. STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
~
T~
' L=~~;USEO
o
0
1
0
1
Xl
X16
X32
X64
CLOCK
CLOCK
CLOCK
CLOCK
MODE
MODE
MODE
MODE
Tx ENABLE
SEND BREAK
o
NOT USED
NOT USED
1
1
0
1
0
1
Tx
Tx
Tx
Tx
5
7
6
8
BITS (OR LESS)/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
'------OTR
2044-004, 005
Absolute
Maximum
Ratings
Test
Conditions
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150 °C
The characteristics below apply for the
following test condihons, unless otherwis"
noted. All voltages are referenced to GND
(0 V). Poslhve current flows into the referenced pm. Avallable operating temperature
ranges are:
Stresses greater than those lIsted under Absolute MaxI·
mum Ratmgs may cause permanent damage to the device.
Thls IS a stress ratmg only; operahon of the devIce at any
condItion above those mdicated m the operatIonal sectIons
of these speclhcahons IS not ImplIed. Exposure to absolute
maXImum ratmg conditions for extended perIods may affect
deVice relIability.
The product number for each operating
temperature range may be found in the order109 information section.
21K
• O°Cto +70°C,
+4.75V~Vee~
+5.25V
• -40°C to +85°C,
+4.75 V ~ Vce ~ +5.25 V
• -55°C to + 125°C,
+4.5V~V(X,~ +5.5V
DC
Characteristics
Symbol
VILC
VIHC
VIL
Clock Input Low Voltage
VIH
Input HIgh Voltage
VOL
VOH
Output Low Voltage
Output HIgh Voltage
Clock Input High Voltage
Input Low Voltage
Min
Max
Unit
-0.3
+0.45
V
VCC-°. 6 +5.5
-0.3
+0.8
+2.0
Test Condition
V
V
+5.5
V
+0.4
V
V
IOL
+2.4
= 2.0 rnA
IOH = -250 p.A
IL
Input/3-State Output Leakage Current
-10
+10
p.A
0.4
RLO
0/
ROO
RH'
R'/
R'
RH'
RL'
R'
RH'
RL'
RS
RHS
RL'
R6
RH6
RL6
R7
RH7
RL7
RL'
RH'
RL'
R'I
RH'
RL'
R61
RHo
RL6
R71
RH7
RL7
ROO
ROB
RlOl
RRlO {
R11
R111
R12
R121
RR12 {
RR12 {
R13
106
RH'
R·I
R91
RlO
RRlO {
Stacks
R'/
I
RRB {
ROB
R15
RL'
RBI15
R9
R15'
RH'
R04
01
15
R14
o
R'I
RRS {
RRB {
;R14\
o/
RLl
17
RR. {
RR6 {
R14'
RLO
RHl
RR' {
RO.
RS
RHO
Rl/15
RL'
RR' {
RR' {
RO/7
RRO {
RLl
R131
SYSTEM STACK POINTER (SEG NO)
RQ12
SYSTEM STACK POINTER (OFFSET)
NORMAL STACK POINTER (OFFSET)
RQ12
R141
NORMAL STACK POINTER (SEG NO)
RR14 {
R1S'
R15
SYSTEM STACK POINTER
NORMAL STACK POINTER
Figure 2. ZBOOI General-Purpose Registers
Figure 3. ZB002 General-Purpose Registers
The 28001 and 28002 can use stacks located
anywhere in memory. Call and Return instructions as well as interrupts and traps use Implied stacks. The distmctlOn between normal
and system stacks separates system information
from the applicahon program informahon. Two
stack pointers are available: the system stack
pomter and the normal stack pomter. Because
they are part of the general-purpose regIster
group, the user can manipulate the stack
pointers wIth any mstruchon avaIlable for
register operations.
In the 28001, regIster paIr RRI4 is the
ImpiJed stack pointer. RegIster RI4 contains
the 7-blt segment number and RI5 contains the
16-bit offset. In the 28002, register RI5 is the
Implled 16-blt stack pomter.
2001·0090,0091
Refresh
Program
Status
Information
The Z8000 CPU contains a counter that
can be used to automatically refresh dynamic
memory. The refresh counter regIster consists
of a 9-bit row counter, a 6-bit rate counter and
an enable bit (Figure 4). The 9-blt row counter
can address up to 256 rows and IS incremented
by two each time the rate counter reaches
end-of-count. The rate counter determines the
time between successIve refreshes. It consists
of a programmable 6-blt modulo-n prescaler
(n = 1 to 64), driven at one-fourth the CPU
clock rate. The refresh period can be programmed from 1 to 64 JLS with a 4 MHz clock.
Refresh can be disabled by programming the
refresh enable/disable bit.
This group of status registers contains the
program counter, flags and control bits. When
an mterrupt or trap occurs, the entire group
IS saved and a new program status group is
loaded.
Figure 5 lliustrates how the program status
groups of the Z8001 and Z8002 differ. In the
non-segmented Z8002, the program status
group consists of two words: the program
counter (PC), and the flag and control word
(FCW). In the segmented Z8001, the program
status group consists of four words: a two-word
program counter, the flag and control word
and an unused word reserved for future use.
Seven bits of the first PC word designate one
of the 128 memory segments. The second word
supphes the 16-bit offset that designates a
memory location within the segment.
With the exception of the segment enable bit
in the Z8001 program status group, the flags
and control bits are the same for both CPUs.
,ow
RATE
!
I
!
Figure 4. Refresh Counter
N
GO
C
e
N
t:I
•c::
I.._'..I.'_'-1.,_'-",-'....1...1_'..I.'_'-1.,_'-,,_'....1...'_'. 1.1_'-1.,_'-",-'....1...'_'..I.'_'-1.,_'_1,-'--,1 )~~:~VED
s_".L1s_"...II_'.JII..."_'L!NV_".LI_'...II_'.JI_'-LI_'.LI_'...II_'.JII..."_'LID_'.LI_"...II_"_IL'-,I) &~~V~~
LI
I.._'..I.I----'---'~'-"_"'L.!NT_"..I.t_'-I.E~---'_L.1_'..I.'_'-1.1_'-,1'-"....1...1_"
_"-1.1_'_,,---,°II
,-______-;;:===______
---,I
..I.'
28002 Program Status Registers
PROGRAM
jCOUNTER
SEIMEN~ OFf~ET
28001 Program Status Registers
r, I
I
SEGMENT NUMBER
I
I
I
UPPER OFFSET
I
I
I
I,
I"
I
I
, , ,
I
"I
I
, ,
I
I
"I
I
"I
,
,
"1
I
"I
I
"I "1
r
UPPER POINTER
!
!
!
I"
I
"I"I
, , ,
I
I
I
"I
,1
28002 Program Status Area Pomter
28001 Program Status Area Pomter
Figure 5. ZBOOO CPU Speci,ai Registers
Interrupt
and Trap
Structure
2045·0282, 0283
The Z8000 prOVIdes a very fleXIble and
powerful mterrupt and trap structure. Interrupts are external asynchronous events requiring CPU attenhon, and are generally tnggered
by penpherals needmg servIce. Traps are synchronous events resulting from the execuhon
of certam instruchons. Both are processed m a
SImilar manner by the CPU.
The CPU supports three types of mterrupts
(non-maskable, vectored and non-vectored)
and four traps (system call, ummplemented
mstruchon, pnvlleged mstruchons and
segmentatIOn trap). The vectored and nonvectored mterrupts are maskable. Of the four
traps, the only external one IS the segmentahon trap, which IS generated by the Z8010.
The remammg traps occur when mstructlOns
hmlted to the system mode are used m the normal mode, or as a result of the System Call mstruchon, or for an unimplemented mstruchon.
The descendmg order of pnonty for traps
and mterrupts IS: mternal traps, non-maskable
mterrupt, segmentahon trap, vectored mterrupt and non-vectored mterrupt.
When an interrupt or trap occurs, the current program status IS automatically pushed on
the system stack. The program status consists
of the processor status (PC and FCW) plus a
16-blt Idenhfier. The Idenhfler contams the
reason or source of the trap or mterrupt. For
mternal traps, the Identifier IS the first word
of the trapped mstruchon. For external traps
or mterrupts, the Identifier IS the vector on the
data bus read by the CPU durmg the
mterrupt-acknowledge or trap-acknowledge
cycle.
After saving the current program status, the
new program status IS automatically loaded
from the program status area m system
memory. ThIS area is deSIgnated by the program status area pomter (PSAP).
107
28000 instructions can operate on bits, BCD
digits (4 bits), bytes (8 bits), words (16 bits),
long words (32 bits), byte strings and word
strings (up to 64 kilobytes long). Bits can be
set, reset and tested; digits are used in BCD
arithmetic operations; bytes are used for
characters or small integer values; words are
used for integer values, instructions and nonsegmented addresses; long words are used for
long integer values and segmented addresses.
All data elements except strings can reside
either in registers or memory. Strings are
stored in memory only.
The basic data element is the byte. The
number of bytes used when manipulating a
data element is either implied by the operation
or-for strings and multiple register operations - explicitly specified in the instruction.
SegmenHigh-level languages, sophisticated operattation and
ing systems, large programs and data bases,
Memory
and decreasing memory prices are all accelManagement erating the trend toward larger memory
requirements in mICrocomputer systems. The
28001 meets this reqUIrement with an eight
megabyte addressing space. This large
address space is directly accessed by the CPU
using a segmented addressing scheme and can
be managed by the 28010 Memory Management Umt.
Segmented
Addressing
In hardware, segmented addresses are contained in a regIster pair or long-word memory
location. The segment number and offset can
be manipulated separately or together by all
the available word and long-word operations.
When contained in an instruction, a
segmented address has two different representations: long offset and short offset. The long
offset occupies two words, whereas the short
offset requires only one and combines in one
word the 7-blt segment number wIth an 8-bit
offset (range 0-256). The short offset mode
allows very dense encoding of addresses and
minimizes the need for long addresses
required by direct accesssing of thIs large
address space.
Data
Types
A segmented addressing space-compared
with linear addressing - is closer to the way a
programmer uses memory because each procedure and data space resides in its own segment. The 8 megabytes of 28001 addressing
space is divldep into 128 relocatable segments
up to 64 kilobytes each. A 23-blt segmented
address uses a 7-blt segment address to point
to the segment, and a 16-bit offset to address
any locahon relative to the beginning of the
segment. The two parts of the segmented
address may be manipulated separately. The
segmented 28001 can run any code written for
the non-segmented 28002 in anyone of its
128 segments, prOVIded it is set to the nonsegmented mode.
Memory
The addresses mampulated by the programManagement mer, used by instructions and output by the
28001 are called logical addresses. The
Memory Management Umt takes the logical
addresses and transforms them into the
physical addresses reqUIred for accessing the
memory (FIgure 6). This address transformahon process is called relocahon. Segment
relocation makes user software addresses mdependent of the physical memory so the user is
freed from specifying where mformahon is
actually located in the physical memory.
The relocahon process is transparent to user
software. A translation table in the Memory
Management Umt assocIates the 7-bit segment
number WIth the base address of the physical
memory segment. The 16-bit offset is added to
the physical base address to obtain the actual
physical address. The system may dynamically
reload translation tables as tasks are created,
suspended or changed.
In addition to supporting dynamic segment
relocahon, the Memory Management Unit also
provides segment protechon and other segment management features. The protection
features prevent illegal uses of segments, such
as wrIting into a wrIte-protected zone.
Each Memory Management Unit stores 64
segment entries that consIst of the segment
108
base address, its attributes, size and status.
Segments are variable in size from 256 bytes to
64 kilobytes in increments of 256 bytes. Pairs
of Management Units support the 128 segment
numbers available for each of the six CPU
address spaces. Within an address space,
several Management Units can be used to
create multiple translation tables.
LOGICAL ADDRESS
L...----r-r--....
r;;;Er:.;;;;;-------
I MANAGMENT
I UNIT
I
I
I
I
I
I
----1
I
BASE
ADDRESS
REGISTER
FILE
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
23
24·BIT PHYSICAL ADDRESS
L ________ _
__...1
Figure 6. Logical-to-Physical Address
Transformation
2045·0284
Extended
Processing
Architecture
The Zilog Extended Processing Architecture
(EPA) provides an extremely flexible and
modular approach to expanding both the hardware and software capabilities of the Z8000
CPU. Features of the EPA include:
• Specialized instructions for external processors or software traps may be added to
CPU instruction set.
• Increases throughput of the system by using
up to four specialized external processors in
parallel with the CPU.
• Permits modular design of Z8000-based
systems.
• Provides easy management of multiple
microprocessor configurations via "single
instruction stream" communication.
• Simple interconnection between extended
processing units and Z8000 CPU requires no
additional external supporting logic.
• Supports debugging of suspect hardware
against proven software.
• Standard feature on all Zilog Z8000 CPUs.
Specific benefits include:
• EPU s can be added as the system grows and
as EPU s with speCialized functions are
developed.
• Control of EPUs is accomplished via a
"single instruction stream" in the Z8000
CPU, eliminating many significant system
software and bus contention management
obstacles that occur in other multiprocessor
(e.g., master-slave) organization schemes.
The processing power of the Zilog Z8000
16-bit microprocessor can be boosted beyond
its intrinsic capability by Extended Processing
Architecture. Simply stated, EPA allows the
Z8000 CPU to accommodate up to four Extend-.
ed Processing Units (EPUs), whIch perform
specialized functions in parallel wIth the CPU's
main instruction execution stream.
The use of extended processors to boost the
main CPU's performance capability has been
proven with large mainframe computers and
mimcomputers. In these systems, speCialized
functions such as array processing, special
input/output processing, and data communications processing are typically assigned to
extended processor hardware. These extended
processors are complex computers in their own
right.
The Zilog Extended Processing Architecture
combines the best concepts of these proven
performance boosters with the latest in highdensity MOS integrated-circuit design. The
result is an elegant expansion of design
capability-a powerful microprocessor
architecture capable of connectmg single-chip
EPUs that permits very effechve parallel
processing and makes for a smoothly integrated instruction stream from the Z8000 programmer's point of view. A typical addition to
the current Z8000 instruction set might be
Floating Point Instructions.
The Extended Processing Units connect
directly to the Z8000 BUS (Z-BUS) and continuously monitor the CPU instruction stream.
When an extended instruction is detected, the
appropnate EPU responds, obtaining or
placing data or status mformation on the
Z-BUS using the Z8000-generated control
signals and performing its function as directed.
The Z8000 CPU is responsIble for instructing
the EPU and delivering operands and data to
It. The EPU recognizes instructions mtended
for it and executes them, using data supplied
Figure 7. Typical Extended Processor Configuration
2007-001
109
Extended
Processing
Architecture
(Continued)
with the instruction and/or data within its internal registers. There are four classes of EPU
instructions:
28000 CPU.
This software trap mechanism facilitates the
design of systems for later addition of EPUs:
initially, the extended function is executed as a
trap subroutine; when the EPU is finally
attached, the trap subroutine is eliminated and
the EPA control bit is set. Application software
is unaware of the change.
Extended Processing Architecture also offers
protection against' extended instruction overlapping. Each EPU connects to the 28000 CPU
via the STOP line so that if an EPU is
requested to perform a second extended
instruction function before it has completed the
previous one, It can put the CPU into the
Stop/Refresh state until execution of the
previous extended instruction is complete.
EPA and CPU instruction execution are
shown in Figure 8. The CPU begins operation
by fetching an instruction and determining
whether it is a CPU or an EPU command. The
EPU meanwhile monitors the 2-BUS for its own
instructions. If the CPU encounters an EPU
command, it checks to see whether an EPU is
present; if not, the EPU may be simulated by
an EPU instruction trap software routine; if an
EPU IS present, the necessary data and/or
address IS placed on the 2-BUS. If the EPU is
free when the instruction and data for it
appear, the extended instruction is executed.
If the EPU is still processing a previous
instruction, It activates the CPU's STOP line to
lock the CPU off at the 2-BUS until execution
is complete. After the instruction is finished,
the EPUdeactivates the STOP line and CPU
transactions continue.
• Data transfers between main memory and
EPU registers
• Data transfers between CPU registers and
EPU registers
• EPU internal operations
• Status transfers between the EPUs and the
28000 CPU Flag and Control Word register
(FCW)
Four 28000 addressing modes may be utilized
with transfers between EPU registers and the
CPU and main memory:
• Register
• IndIrect Register
• Direct Address
• Indexed
In addihon to the hardware-implemented
capabJiihes of the Extended Processing
Architecture, there is an extended instruction
trap mechanism to permit software simulation
of EPU functIOns. A control bIt in the 28000
FCW register indicates whether actual EPUs
are present or not. If not, when an extended
instruction IS detected, the 28000 traps on the
mstruchon, so that a software "trap handler"
can emulate the desired EPU function-a very
useful development tool. The EPA software
trap routine supports the debugging of suspect
hardware against proven software. This feature
will mcrease m sIgnificance as designers
become famihar with the EPA capability of the
I
I
I
&
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
.&. DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE EXECUTION OF AN INSTRUCTION.
Figure 8. EPA and Z8000 CPU Instruction Execution
110
2007·002
Addressing
Modes
The information included in Z8000 instructions consists of the function to be performed,
the type and size of data elements to be
'manipulated and the location of the data
elements. Locations are designated by register
addresses, memory addresses or 1/0
addresses. The addressing mode of a given
instruction defines the address space it references and the method used to compute the
address itself. Addressing modes are explicitly
speCified or implied by the instruction.
Mode
Operand Addressing
In the Instruction
Register
Figure 4 illustrates the eight addressmg
modes: Register (R), Immediate OM), Indirect
Register OR), Direct Address (DA), Indexed
(X), Relative Address (RA), Base Address (BA)
and Base Indexed (BX). In general, an addressing mode explicitly specifies either
register address space or memory address
space. Program memory address space and
1/0 address space are usually implied by the
instruction.
I
REGISTER ADDRESS
In Memory
In a Register
H
OPERAND
Qperand Value
I
HI
00 '
The content of the
register
8!
...
N
C"2
Immediate'
I
Indirect
Register
.I
Direct
Address
REGISTER ADDRESS
H{~A~D~DR~E!S~S]1------...;··I[~o:PE~R~A~ND~
.1
ADDRESS
OPERAND
CI
The content of the location
whose address is in the
register
The content of the location
whose address is in the
instruction
The content of the location
whose address is the
address in the instruction.
offset by the content of
the working register
Index
Relative
Address
•
In the instruction
OPERAND
'I PC VALUE
~
r:~D~ls~PL~A~c~EM~E~N~T:J~~:::::::::~~I-O-PE-R-A-N0-'
The content of the location
whose address is the
content of the program
counter. offset by the
displacement in the
instruction
Base
Address
The content of the location
whose address is the
address in the register.
offset by the displacement
in the instruction
Base
Index
The content of the location
whose address is the
address in the register.
offset by the displacement in the register
Figure 9. Addressing Mode.
2045·0285
III
Input/
Output
A set of I/O instructions performs 8-bit or
16-bit transfers betwen the CPU and 1/0
devices. I/O devices are addressed with a
16-bit 1/0 port address. The 1/0 port address
is similar to a memory address; however, 1/0
address space is not part of the memory
address space. 1/0 port and memory addresses
coexIst on the same bus lines and they are
distinguished by the status outputs.
Two types of 1/0 instructions are available:
standard and special. Each has its own address
space. Standard 1/0 instructions include a
comprehensive set of In, Out and Block 1/0
instructions for both bytes and words. Special
I/O instructions are used for loading and
unloading the Memory Management Unit. The
status information distmguishes between standard and special I/O references.
MultiMicro-
Multi-microprocessor systems are supported
in hardware and software. A pair of CPU pins
is used in conjunction with certain instruchons
to coordinate multiple microprocessors. The
Multi-Micro Out pin issues a request for the
resource, while the Multi-Micro In pin is used
to recognize the state of the resource. Thus,
any CPU in a multiple microprocessor system
can exclude all other asynchronous CPUs from
a critical shared resource.
Multi-microprocessor systems are supported
in software by the instructions Multi-Micro
Request, Test Multi-Micro In, Set Multi-Micro
Out and Reset Multi-Micro Out. In addition,
the eight megabyte CPU address space is
beneficial in mulhple microprocessor systems
that have large memory requirements.
The Z8000 provides the following types of
instructions:
.. Bit Manipulation
Processor
Support
Instruction
Set.
Summary
.. Rotate and Shift
.. Load and Exchange
.. Block Transfer and String Manipulation
.. Arithmetic
.. Input/Output
.. Logical
.. CPU Control
.. Program Control
Load
.and
Exchange
Clock Cycles *
Mnemonics
CLR
Operands
dst
C~B
Addr.
Modes
R
IR
DA
X
EX
EXB
R,sre
R
IR
DA
X
LO
LOB
LOL
R,src
R
1M
1M
IR
DA
X
BA
BX
LO
LOB
LOL
dst,R
IR
DA
X
BA
BX
LO
LOB
dst, 1M
IR
DA
X
• NS
112
= Non-Segmented
SS
Word. Byte
N5
7
8
II
12
6
12
15
16
55
Long Word
5L
N5
Operation
5L
Clear
dst - 0
12
12
14
15
Exchange
R - src
16
16
18
19
3
7
5 (byte only)
7
9
10
12
10
10
13
14
14
5
II
8
II
12
14
14
II
14
15
17
17
II
14
15
55
12
12
14
15
15
15
17
18
= Segmented Short Offset
SL
II
12
13
17
17
Load into Register
R - sre
13
13
15
16
15
15
17
18
= Segmented Long Offset
Load into Memory (Store)
dst - R
Load Immediate into Memory
dst - 1M
Load and
Exchange
(Continued)
Clock Cycles
Mnemonics
Addr.
Modes
Word. Byte
NS
SS
SL
13
13
15
16
Long Word
NS
SS
Operation
SL
LDA
H, src
DA
X
BA
BX
12
13
15
15
LDAR
R, src
RA
15
LDK
R, src
1M
5
LDM
R, src, n
IR
DA
X
II
14
15
15
15
;7 } +3n
18
Load Multiple
R - src (n consecuhve words)
(n = 1 ... 16)
IR
DA
X
II
14
15
15
15
;7 } +3n
18
Load Multiple (Store MullIple)
dst - R (n consecullve words)
(n = 1 ... 16)
RA
14
LDM
dst,R,n
Load Address
R - source address
Load Address Relative
R - source address
Load Constant
R - n (n = 0 .. , 15)
LDR
LDRB
LDRL
R, src
LDR
LDRB
LDRL
dst,R
RA
14
17
Load Relative (Store RelalIve)
dst - R
(range -32768 ... +32767)
POP
POPL
dst,IR
R
IR
DA
X
8
12
16
16
18
19
12
19
23
23
Pop
dst - IR
Autoincrement contents of R
R
1M
IR
DA
X
9
12
13
14
14
16
17
20
21
21
PUSH
PUSHL
Arithmetic
Operands
IR, src
17
16
16
23
23
25
26
21
21
5
ADD
ADDB
ADDL
R,src
R
1M
IR
DA
X
4
7
7
9
10
R
1M
IR
DA
X
4
7
7
9
10
IR
DA
X
11
14
15
5
Decimal Adjust
4
Decrement by n
dst - ds! - n
(n = 1 ... 16)
dst, 1M
DAB
dst
R
ds!,n
R
IR
DA
X
DEC
DECB
12
13
8
14
14
15
16
10
10
12
13
8
14
14
15
16
15
15
17
18
10
10
II
13
14
CI
Add with Carry
R-R+src+carry
R
CP
CPB
•
23
24
H, src
R,sre
N
f2
Push
Autodecrement contents of R
IR - arc
ADC
ADCB
CP
CPB
CPL
i
Load Relative
R - src
(range -32768 ... +32767)
12
14
14
M
14
14
16
17
Add
R-R+src
16
16
18
19
Compare with Register
R - src
16
16
18
19
Compare with Immediate
dst - 1M
113
Arithmetic
(Continued)
Clock Cycles
Mnemonics
DlV
DIVL
Operands
R. src
Addr.
Modes
INC
INCB
dst.n
Extend Sign
Extend sign of low order half of dst
through high order half of dst
R
4
II
13
14
R
IR
R
R, src
SUB
SUBB
SUBL
R, src
AND
ANDB
R
5
R
4
7
7
9
10
1M
IR
R,src
R
1M
IR
DA
X
COM
COMB
dst
R
IR
DA
X
OR
ORB
R,src
4
7
7
9
10
7
12
15
16
DA
X
4
7
7
9
10
R
1M
IR
TCC
TCCB
cc,dst
R
5
TEST
TESTB
TESTL
dst
R
IR
DA
X
7
8
II
12
XOR
XORB
RI src
R
4
7
7
9
10
1M
IR
DA
X
114
72
DA
X
DA
X
Logical
70
70
70
71
7
12
15
16
IR
SBC
SBCB
Operation
SL
II
1M
dst
SS
II
DA
X
NEG
NEGB
Long Word
NS
R
IR
R.src
SL
Divide (signed)
Word: Rn+l - Rn.n+l + src
Rn - remainder
Long Word: Rn +2.n+3 - Rn ... n+3 + src
DA
X
MULT
MULTL
SS
744 744 744 744 744
745 746 748
746 746 749
IR
dst
.NS
107
107
107 107 107
108 109 III
109 109 112
R
1M
DA
X
EXTS
EXTSB
EXTSL
Word. Byte
14
14
72
72
282'
282'
282'
283'
284'
-
-
284' 286'
284' 287'
Multiply (signed)
Word: Rn. n + 1 - Rn+I' src
Long Word: Rn .. n+ 3 -Rn+2. n+3
'Plus seven cycles for each I In the
mulhphcand
Negate
dst - 0 - dst
16
16
18
19
Subtract with Carry..
R - R - src - carry
10
10
12
13
8
14
14
15
16
Subtract
R-R-src
16
16
18
19
AND
R-RANDsrc
10
10
12
13
Complement
dst - NOT dst
16
16
18
19
OR
R - R OR src
10
10
12
13
Test Condition Code
Set LSB 11 cc IS true
12
12
14
15
13
13
16
17
Test
dst OR 0
17
17
19
20
Exclusive OR
R - R XOR src
10
10
12
13
remaInder
Increment by n
dst - dst + n
(n; 1 ... 16)
16
17
74
75
Rn, n + 1 -
Program
Control
Clock Cycles
Mnemonics
CALL
Operands
Addr.
Modes
IR
DA
dst
Word, Byte
NS
X
CALR
dst
RA
10
DJNZ
DBJNZ
R,dst
RA
II
IRET·
NS
SS
Operation
SL
SL
18
18
15
20
21
Call Subroutine
Autodecrement SP
@ SP - PC
PC - dst
15
Call Relative
Autodecrement SP
@SP-PC
PC - PC + dst (range -4094 to +4096)
10
12
13
Long Word
SS
Decrement and Jump if Non-Zero
R - R- I
If R *- 0: PC - PC + dst (range -254 to 0)
13
Interrupt Return
PS-@SP
Automcrement SP
16
N
00
0
JP
JR
IR
IR
DA
cc,dst
cc, dst
15
7
10
X
7
7
8
RA
6
8
8
(taken)
(not taken)
S
Jump Conditional
If cc IS true: PC - dst
N
10
II
t"l
•
CI
Jump Conditional Relative
If cc IS true: PC - PC + dst
(range -256 to + 254)
RET
Bit
Manipulation
cc
10
SC
src
1M
BIT
BITB
dst,b
R
IR
DA
7
13
7
33
39
10
II
BIT
BITB
dst, R
R
10
RES
RESB
dst,b
R
IR
DA
II
II
II
13
14
System Call
Autodecrement SP
@ SP - old PS
Push mstructIon
PS - System Call PS
13
14
Test Bit Dynamic
Z flag - NOT dst b,t specIfied by
contents of R
Reset Bit Static
Reset dst bit specIfied by b
4
X
Return Conditional
If cc IS true: PC - @ SP
Automcrement SP
Test Bit Static
Z flag - NOT dst b,t specIfied by b
4
8
X
(taken)
(not taken)
14
14
16
17
RES
RESB
dst,R
R
10
Reset Bit Dynamic
Reset dst b,t specIfied by contents R
SET
SETB
dst,b
R
IR
DA
Set Bit Static
Set dst b,t specIfied by b
X
4
II
13
14
14
14
16
17
SET
SETB
dst,R
R
10
Set Bit Dynamic
Set dst b,t specIfied by contents of R
TSET
TSETB
dst
R
IR
DA
7
II
14
15
Test and Set
S flag - MSB of dst
dst - allis
X
·Pnvlieged instruction Executed
In
15
15
17
18
system mode only
115
Rotate
and
Shift
Block
Transfer
and String
Manipulation
Clock Cycles
Mnemonics
Addr.
Modes
Word. Byte
NS
SS
SL
Long Word
NS
Operation
SS' SL
R
R
6for n
7forn
=I
=2
Rotate Left
by n bits (n
dst,n
R
R
6 for n
7 for n
=I
=2
Rotate Left through Carry
by n bits (n = I, 2)
RLDB
R,src
R
9
RR
RRB
dst,n
R
R
6 for n
7forn
=I
=2
Rotate Right
by n bits (n = 1,2)
RRC
RRCB
dst.n
R
R
6forn
7 for n
=I
=2
Rotate Right through Carry
by n bils (n = I, 2)
RRDB
R.src
R
9
SDA
SDAB
SDAL
dsl,R
R
(15 + 3 n)
(15 + 3 n)
Shilt Dynamic Arithmetic
Shlfl dst left or right
by contents of R
SDL
SDLB
SDLL
dst,R
R
(15 + 3 n)
(15 + 3 n)
Shift Dynamic Logical
Shlft dst left or right
by contents of R
SLA
SLAB
SLAL
dst,n
R
(13 + 3 n)
(13 +3n)
Shift Left Arithmetic
by n bIts
SLL
SLLB
SLLL
dst,n
R
(13 + 3 n)
(13 + 3 n)
Shilt Left Logical
by n bIts
SRA
SRAB
SRAL
dst,n
R
(13 + 3 n)
(13 + 3 n)
Shift Right Arithmetic
by n bIts
SRL
S8LB
SRLL
dst,n
R
(13 + 3 n)
(13 + 3 n)
Shift Right Logical
by n bIts
CPD
CPDB
Rx, src, Ry, cc
IR
CPDR
CPDRB
Rx. src, Ry, cc
IR
CPI
RX, sre, Ry, ec
IR
CPIR
CPIRB
RX, src, Ry, Cc
IR
CPSD
CPSDB
dst, sre, R, cc
IR
RL
RLl!
dst,n
RLC
RLCB
dplB
116
Operands
Rotate Digit Left
20
(11 + 9 n)
20
(11 + 9 n)
25
= 1,2)
Rotate Digit Right
Compare and Decrement
Rx - src
Autodecrement src address
Ry - Ry - 1
Compare. Decrement and Repeat
RX - src
Autodecrement src address
Ry - Ry - 1
Repeat unll1 cc IS true or Ry = 0
Compare and Increment
RX - src
Autoincrement src address
Ry - Ry - I
Compare. Increment and Repeat
RX - src
Automcrement src address
Ry - Ry - I
Repeat until cc IS true or Ry = 0
Compare String and Decrement
dst - src
Autodecrement dst and src addresses
R - R- 1
Block Transfer
and String
Mnemonics
Manipulation
(Contmued)
Clock Cycles
Operands
CPSDR
CPSDRB
dst, src, R, cc
CPSI
CPSlB
dst. sre. R. ee
Addr.
Modes
lR
Word. Byte
NS
SS
SL
(11 + 14 n)
Long Word
NS
SS
Operation
SL
Compare String. Deer. and Repeat
dst - src
Autodecrement clst and src addresses
R - R-I
Repeat until ee IS true or R = 0
lR
25
Compare String and Increment
dst - src
Automcrement clst and src addresses
R - R-I
CPSIR
CPSIRB
LDD
LDDB
dsl, sre, R, ee
lR
dst. src, R
lR
(11 + 14n)
20
Compare String. Incr. and Repeat
dst - sre
Automcrement clst and src addresses
R- R- I
Repeat until cc 15 true or R = 0
8==...
Load and Decrement
clst -
src
N
Autodecrement clst and src addresses
R- R- I
LDDR
LDDRB
ds!, src, R
lR
(11 + 9 n)
..,c:I
C"2
Load. Decrement and Repeat
clst -
src
Autodecrement clst and src addresses
R - R-I
Repeat until R = 0
LOI
LOIB
dst, sre, R
lR
20
Load and Increment
clst -
src
Autoincrement clst and src addresses
R- R- I
LOIR
LDJRB
dst, sre, R
lR
TRDB
ds!, sre, R
lR
TRDRB
dst, sre. R
lR
(11 + 9 n)
25
(11 + 14 n)
Load. Increment and Repeat
dst - src
Automcrement clst and src addresses
R- R- I
Repeat until R = 0
Translate and Decrement
dst - sre (dst)
Autodecrement dst address
R - R-I
Translate. Decrement and Repeat
dst - src (dst)
Autodeeremen! dst address
R - R-I
Repeat until R = 0
TRIB
dst, sre, R
lR
TRIRB
dst. src, R
lR
TRTDB
src I, src2. R
lR
25
(11 + 14n)
25
Translate and Increment
dst - src (dst)
Automcrement dst address
R - R- I
Translate. Increment and Repeat
dst - src (ds!)
Automcrement clst address
R - R- I
Repeat until R = 0
Translate and Test. Decrement
RHI - src 2 (src I)
Autodecrement src 1 address
R- R - 1
117
Block Transfer
and String
Mnemomcs
Manipulation
(Continued)
Input/
Output
Clock Cycles
Operands
'Word. Byte
N5
55 ' 5L
55
Operation
5L
sre I, sre2, R
IR
TRTIB
src I, src2, R
IR
TRTlRB
sre I, sre2, R
IR
R,src
IR
DA
10
12
Input
R - sre
INDINDB-
dst,sre,R
IR
21
Input and Decrement
dst - sre
Autodeerement dst address
R - R- I
INDRINDRB-
dst,sre,R
IR
INIINIB-
dst.sre,R
IR
INIR*
INlRB*
dst,sre.R
IR
OUT*
OUTB*
dst,R
IR
DA
10
12
Output
dst - R
OUTD*
OUTDB*
dst, sre, R
IR
21
Output and Decrement
dst - sre
Autodeerement sre address
R - R-I
OTDR*
OTDRB*
dst. sre, R
IR
OUTI*
OUTIB-
dst,sre,R
IR
OTlR*
OTIRB-
dst.sre,R
IR
ININB-
In
(II + 14 n)
Long Word
N5
TRTDRB
·PrlvIleged instructIons. Executed
118
Addr.
Modes
25
(II + 14n)
(11+ IOn)
21
(II + IOn)
(11 + 10 n)
21
(II + IOn)
system mode only.
Translate and Test. Decr. and Repeat
RHI - sre 2 (sre I)
Autodeerement sre I address
R - R- I
Repeat unhl R = 0 or RHI = 0
Translate and Test. Increment
RHI - sre 2 (sre I)
Autoinerement sre I address
R - R-I
Translate and Test. Incr. and Repeat
RHI - sre 2 (sre I)
Automerement sre I address
R - R- I
Repeat unhl R = 0 or RHI = 0
Input. Decrement and Repeat
dst - sre
Autodeerement dst address
R - R- I
Repeat unhl R = 0
Input and Increment
dst - sre
Autoinerement dst address
R - R-I
Input. Increment and Repeat
dst - Bre
Automerement dst address
R - R-I
Repeat unhl R = 0
Output. Decrement and Repeat
ds! - src
Autodeerement sre address
R - R-I
Repeat until R = 0
Output and Increment
dst - sre
A utoinerement sre address
R - R- I
Output. Increment and Repeat
dst - sre
Autoinerement are address
R - R-I
Repeat unhl R = 0
Input/Output
(Continued)
Clock Cycles
Mnemonics
SIN·
SINB·
Operands
Addr.
Modes
Word. Byte
NS
R, src
DA
12
SIND·
SINDB·
dst, src, R
IR
21
SINDR·
SINDRB·
dst, src, R
SS
SL
Long Word
NS
SS
Operation
SL
Special Input
R - src
Special Input and Decrement
src
Autodecrement dst address
R - R- 1
clst -
IR
(11 + 10 n)
Special Input. Decrement and Repeat
clst -
src
Autodecrement clst address
n- R- 1
Repeat unill R = 0
SINI·
SINIB·
SINIR·
SINIRB·
SOUT·
SOUTB·
SOUTD·
SOUTDB·
dst, src, R
IR
Special Input and Increment
21
clst -
IR
dst, src. R
(11+10n)
src
N
Automcrement clst address
R - R- 1
00
C
C
Special Input. Increment and Repeat
N
dst - src
Automcrement clst address
R - R- 1
Repeat unill R = 0
dst,src
DA
12
Special Output
dst - src
dst. src. R
IR
21
Special Output and Decrement
clst -
IV
src
Autodecrement src address
R - R- 1
SOTDR·
SOTDRB·
dst. src. R
IR
SOUTI·
SOUTIB·
dst. src, R
lR
SOTIR·
SOTIRB·
dst, src, R
(11 + IOn)
Special Output. Decr. and Repeat
dst - src
Autodecrement src address
R - R- 1
Repeat untIl R = 0
Special Output and Increment
21
clst - src
Automcrement src address
R - R- 1
R
(11 + 10 n)
Special Output. Incr. and Repeat
dst - src
Automcrement src address
R - R-l
Repeat untt! R
CPU
Control
COMFLG
=
0
flags
7
Complement Flag
(Any combmatIon of C, Z. s, PIV)
DI·
mt
7
Disable Interrupt
(Any combmailon of NVI. VI)
EI·
mt
7
Enable Interrupt
(Any combmailon of NVI. VI)
HALT·
(8 + 3 n)
HALT
LDCTL·
CTLR, src
R
7
Load into Control Register
CTLR - src
LDCTL·
dst.CTLR
R
7
Load from Control Register
dst - CTLR
*Pnvileged instructlOns Executed
In
...
"e
system mode only
119
CPU
Control
(Continued)
Clock Cycles
Mnemonics
Operands
Addr.
Modes
Word, Byte
NS
SS
SL
Long Word
NS
SS
Operation
SL
LDCTLB
FLGR,src
R
7
Load into Flag Byte Register
FLGR - src
LDCTLB
ds!,FLGR
R
7
Load from Flag Byte Register
ds! - FLGR
src
IR
DA
X
12
16
17
LOPS·
20
20
16
22
23
Load Program Status
PS - src
Test Multl·Micro Bit
Set S If Mj IS Low, reset S If Mj IS High.
MBIT"
MREQ*
R
dst
(12
+ 7 n)
Multi-Micro Request
MRES·
5
Multi-Micro Reset
MSET·
5
Multi-Micro Set
NOP
No Operation
RESFLG
flag
7
Reset Flag
(Any combinatIon of C, 2, S, PlY)
SETFLG
flag
7
Set Flag
(Any combinatIon of C, 2, S, PlY)
* Prlvlleged Instructions Executed III system mode only.
Condition
Codes
Code
Flag Sellings
Meaning
CC Field
Always false
Always true
Z
NZ
C
NC
PL
MI
NE
EQ
OV
NOV
PE
PO
GE
LT
GT
LE
UGE
ULT
UGT
ULE
0000
1000
0110
1110
0111
1111
1101
0101
1110
0110
0100
1100
0100
1100
1001
0001
10lO
0010
1111
0111
1011
0011
Z
Z
C
C
S
S
Zero
Not zero
Carry
No Carry
Plus
Mmus
Not equal
Equal
Overflow
No overflow
Panty is even
Panty IS odd
Greater than or equal (signed)
Less than (signed)
Greater than (signed)
Less than or equal (signed)
UnsIgned greater than or equal
Unsigned less than
UnsIgned greater than
Unsigned less than or equal
= I
= 0
= I
0
= 0
I
2 = 0
2 = I
PlY
I
PlY
0
P/V
I
P/V
0
(S XOR PlY) = 0
(S XOR P/V) = I
12 OR (S XOR P/V)) = 0
IZ OR (S XOR PlY)) = I
C=O
C = I
I(C = 0) AND (2 = 0)) = I
(C OR 2) = I
Note that some condItIon codes have Identical flag sethngs and bmary fields
In
the Instruchon:
2 = EQ, NZ = NE, C = ULT, NC = UGE, OV = PE, NOV = PO
Status
Line
Codes
120
ST3-STO
0000
000 I
00 I 0
001 I
0100
0101
o I 10
oI I I
Definition
Internal operation
Memory refresh
1/0 reference
Special 1/0 reference (e.g., to an MMU)
Segment trap acknowledge
Non-maskable Interrupt acknowledge
Non-vectored mterrupt acknowledge
Vectored Interrupt acknowledge
Definition
ST3-STO
1000
100 I
10 I 0
101 I
I 100
I 101
I I 10
II II
Data memory request
Slack memory request
Data memory request (EPU)
Stack memory request (EPU)
Program reference, nth word
InstructIon fetch, hrst word
ExtensIon processor transfer
Reserved
Pin
ADo-ADls. Address/Data (inputs/outputs,
ClK. System Clock (input). CLK is a 5V
Description
active High, 3-state). These multiplexed
address and data lines are used both for I/O
and to address memory.
single-phase time-base input.
AS. Address Strobe (output, active Low,
3-state). The rising edge of AS indicates
addresses are valid.
BUSACK. Bus Acknowledge (output, active
Low). A Low on this line indicates the CPU has
relinquished control of the bus.
BUSREQ. Bus Request (input, active Low).
This line must be driven Low to request the
bus from the CPU.
DS. Data Strobe (output, active Low, 3-state).
This line times the data in and out of the CPU.
MREQ. Memory Request (output, active Low,
this line resets the CPU.
R/W. Read/Write (output, Low = Write,
3-state). R/W indicates that the CPU is reading
from or writing to memory or I/O.
SNo-SNs. Segment Number (outputs, active
High, 3-state). These lines provide the 7-bit
segment number used to address one of 128
segments by the Z8010 Memory Management
Unit. Output by the Z8001 only.
SEGT. Segment Trap (input, active Low). The
Memory Management Unit interrupts the CPU
with a Low on this line when the MMU detects
a segmentation trap.
3-state). A Low on this line indicates that the
address/data bus holds a memory address.
STo-ST3. Status (outputs, active High, 3-state).
MI' Mo. Multi-Micro In, Multi-Micro Out
STOP. Stop (input, active Low). This input can
(input and output, active Low). These two lines
form a resource-request daisy chain that allows
one CPU in a multi-microprocessor system to
access a shared resource.
be used to single-step instruction execution.
NMI. Non-Maskoble Interrupt (edge triggered,
input, active Low). A high-to-Iow transition on
NMI requests a non-maskable interrupt. The
NMI interrupt has the highest priority of the
three types of interrupts.
NVI. Non- Vectored Interrupt (input, active
Low). A Low on this line requests a nonvectored interrupt.
AD,
AD,
AD,
SN,
AD10
SN,
AD11
AD,
These lines specify the CPU status (see table).
VI. Vectored Interrupt (input, active Low). A
Low on this line requests a vectored interrupt.
WAIT. Wait (input, active Low). This line indicates to the CPU that the memory or I/O
device is not ready for data transfer.
B/W. Byte/Word (output, Low = Word,
3-state). This signal defines the type of memory
reference on the 16-bit address/data bus.
Nis. Normal/System Mode (output, Low =
System Mode, 3-state). Nis indicates the CPU
IS in the normal or system mode.
Reserved. Do not connect.
AD12
ADa
AD,
ADo
ADn
AD,
AD10
AD,
STOP
SN,
ADu
AD,
11,
AD,
AD12
AD,
AD 15
AD,
ADu
AD,
AD14
AD,
STOP
AD,
+5V
AD,
1IiI,
AD,
Vi
SN,
AD15
AD,
GND,
AD14
AD,
CLOCK
+5V
GND
NVI
SEGT
NMI
RESET
Me
MREQ
AS
Vi
CLOCK
RESERVED
NVI
AS
BtW
NMT
RESERVED
NIS
RESET
BIW
OS
RlW
ST,
BUSACK
ST,
WAIT
ST,
BUSREQ
ST,
ST,
SN,
ST,
BUSREQ
SN,
SN,
ST,
ST,
Figure 10. Z8001 Pin AulgDDUlnhl
2045-0286, 0287
RESET. Reset (input, active Low). A Low on
lIiIe
N/S
MREll
OS
RtW
BUSACK
WlUT
Figure 11. zaOO2 Pin Assignment.
121
I
iii
9
Z8000
CPU
Timing
Memory
Read and
Write
The Z8000 CPU executes instructions by
stepping through sequences of basic machine
cycles, such as memory read or write, 110
device read or write, interrupt acknowledge,
and internal execution. Each of these basic
cycles requires three to ten clock cycles to
execute. Instructions that require more clock
cycles to execute are broken up into several
machine cycles. Thus no machine cycle is
longer than ten clock cycles and fast response
to a Bus Request is guaranteed.
The instruction opcode is fetched by a
normal memory read operation. A memory
refresh cycle can be inserted just after the
completion of any first instruction fetch (IFl)
cycle and can also be inserted while the
folloWing instructions are being executed:
MULT, MULTL, DIV, DIVL, HALT, all Shift
instructions, all Block Move instructions, and
the Multi-Micro Request instruction (MREQ).
The following timing diagrams show the
relative timing relationships of all CPU signals
during each of the basic operations. When a
machine cycle requires additional clock cycles
for CPU internal operation, one to five clock
cycles are added. Memory and 110 read and
write, as well as interrupt acknowledge cycles,
can be extended by activating the WAIT input.
For exact timing information, refer to the composite timing diagram.
Note that the WAIT input is not synchronized
in the Z8000 and that the setup and hold times
for WAIT relative to the clock must be met. If
asynchronous WAIT signals are generated,
they must be synchronized with the CPU clock
before entering the zaOOO.
Memory read and instruction fetch cycles
are identical, except for the status information
on the STo-ST3 outputs. During a memory
read cycle, a 16-bit address is placed on the
ADo-AD15 outputs early in the first clock
period, as shown in Figure 12. (In the Z8001,
CLOCK
-
,
,
,
I
It
.I
WAIT
--
STAT.!!SE!I
r--
INSERTS WAIT STATE
(81W, NIS,
5To-5Y3)
SNo-SN,
-
SEGMENT NUMBER
'-
is
MREQ
AD
MEMORY ADDRESS
READ
')---
~
iii
READ
Riw
READ
L
/
AD
MEMORY ADDRESS
WRITE
DATA OUT
. iii
WRITE
R1W
WRITE
r
\
Figure 12. Memory Read and Write Timing
122
2045-0288
Memory
Read and
Write
(Continued)
Input/
Output
the 7-bit segment number is output on
SNo-SN6 one clock period earlier than the
16-bit address offset to compensate for the
delay in the memory management circuitry.)
A valid address is indicated by the rising
edge of Address Strobe. Status and mode
information become valid early in the memory
access cycle and remain stable throughout.
The state of the WAIT input is sampled in the
middle of the second clock cycle by the falling
edge of Clock. If WAIT is Low, an additional
clock period is added between T2 and T3.
WAIT is sampled again in the middle of this
wait cycle, and additional wait states can be
inserted. This allows interfacing slow
memories. No control outputs change during
wait states.
Although 28000 memory is word organized,
memory is addressed as bytes. All instructions
are word-aligned, using even addresses.
Within a 16-bit word, the most significant byte
(Ds-Dls) is addressed by the low-order address
(Ao = Low), and the least significant byte
(Do-D7) is addressed by the high-order
address (Ao = High).
I/O timing is similar to memory read/write
timing, except that one wait state is automatically inserted between T2 and T3 (Figure 13).
Both the segmented 28001 and the nonsegmented 28002 use 16-bit I/O addresses.
CLOCK
-
T,
T,
TWA
T,
I
I
~
I
XQ<-
WAIT
- D<
STATUSES -
(s/w,
STo·ST~
NIS
As
~ INSERT WAIT STATE
LOW
-
rLJ
HIGH
MiiEQ
AOINPUT
~
-
D<
PORr ADDRESS
G:)
'>-------
C
iii
INPUT
R/W
INPUT
ADOUTPUT
~
-U
-
D<
PORT ADDRESS
DATA OUT
iii
OUTPUT
R/WOUTPUT
r
1\
Figure 13. Input/Output Timing
2045-0289
.
123
Interrupt and
Segment
Trap Request
and
Acknowledge
The 28000 CPU recognizes three interrupt
inputs (non-maskable, vectored and nonvectored) and a segmentation trap input. Any
Hlgh-to-Low transition on the NMI input is
asynchronously edge detected and sets the
internal NMI latch. The VI, NVI and
SEGT inputs as well as the state of the internal
NMI latch are sampled at the beginning of T3
in the last machine cycle of any instruction.
In response to an interrupt or trap, the subsequent IFJ cycle IS exercised, but aborted.
The program counter is not updated, but the
system stack pOinter is decremented.
The next machine cycle is the interrupt
acknowledge cycle. This cycle has five
automatic walt states, with additional wait
1
CLOCK
states possible, as shown in Figure 14.
After the last wait state, the CPU reads the
information on ADo-ADI5 and stores it temporarily, to be saved on the stack later in the
acknowledge sequence. This word identifies
the source of the interrupt or trap. For the
non-vedtored and non-maskable interrupts, all
16 bits·can represent peripheral device status
information. For the vectored interrupt, the
low byte is the jump vector, and the high byte
can be extra user status. For the segmentation
trap, the high byte is the Memory Management
Unit identifier and the low byte is undefined.
After the acknowledge cycle, the N/S output
indicates the automatic change to system
mode.
___________
_~~I~~~~:~~_'N~:r8.n~~Nj'_'
INSTRUCTION
(ABORTED)
I.....
m·····'
IiJi..Ji.s
----------11".'>'.,. '.
AcKNOWLEOQE _ _
CYCLE
AUTOMATIC !AIT STATES
is
Vi, NVi, Hln'
......:....--
---~
INTERNAL
iiiMi
Rlii
aiii
ITo-aTs
(\-_ _ _....J)
Figure 14. Interrupt and Segment Trap Request! Acknowledge Timing
Status
Saving
Sequence
The machine cycles following the mterrupt
acknowledge or segmentation trap acknowledge cycle push the old status mformation on
the system stack in the following order: the
16-bit program counter; the 7-bit segment
number (28001 only); the flag and ,:ontrol
Bus Request
A Low on the BUSREQ input indicates to the
Acknowledge CPU that another device is requesting the
Address/Data and Control buses. The asynTiming
chronous BUSREQ input is synchronized at the
beginning of allY machine cycle (Figure 15). If
124
word; and finally the mterrupt/trap Identifier.
Subsequent machine cycles fetch the new program status from the program status area, and
then branch to the mterrupt/trap service
routine.
BUSREQ is Low, an internal synchronous
BUSREQ signal is generated, which-after completion of the current machine cycle-causes
the BUSACK output to go Low and all bus outputs to go into the high-impedance state. The
2045·0290
Bus Request! requesting device-typically a DMA-can then
Acknowledge control the bus.
(Continued)
When BUSREQ is released, it is synchronized with the rising clock edge and the
BUSACK output goes High one clock period
later, indicating that the CPU will again take
control of the bus.
--------------~~.-- ---- ---- --)---
---------tJ
M:::'·S~:---------t---)..
t-'
__ __________ _
B/W, RiW,Hli _ _ _ _ _ _ _ _ _
Figure 15. Bus Request/Acknowledge Timing
Stop
The STOP input is sampled by the last falling
clock edge immediately preceeding any IF]
cycle (Figure 16). If STOP is found Low, a
stream of memory refresh cycles is inserted
after T3, again sampling the STOP input on
each falling clock edge in the middle of the T3
states. This refresh operation does not use the
refresh prescaler or its dlvlde-by-four clock
prescaler; rather, it double-increments the
refresh counter every three clock cycles.
When STOP is found HIgh again, the next
refresh cycle IS completed, any remaming T
states of the IF] cycle are then executed and
the CPU continues its operatIon.
CLOCK
~\~~/________~\~!_________
STO-ST3
alii
X)C
~_ _ _ _'_F'_ _ _...IX. . _______
=-\,
J\~
______________________
MEMORY REFRESH
~
---------------------~"-----
/
Figure 16. Stop Timing
2045·0291, 0292
125
Internal
Operation
because bus request or refresh cycles can be
inserted at the end of any internal machine
cycle.
Although the address outputs during TI are
undefined, Address Strobe is generated to
'satisfy the requirements of future Z-BUS compatible self-refresh dynamiC memories.
Certain extended instructions, such as
Multiply and Divide, and some special instructions need additional time for the execution of
internal operations. In these cases, the CPU
goes through a sequence of internal operation
machine ·cycles, each of which is three to eight
clock cycles long (Figure 17). This allows fast
response to Bus Request and Refresh Request,
T,
T.
CLOCK
-
T.
l1.-l1.-l1.-
'---I
- =x
=x
I---
INTERNAL OPERATION
r-
UNDEFINED
HIGH
iiiiiQ,iii,RIW
alii
UNDEFINED
",i
SAME AS PREVIOUS CYCLE
I
Figure 17. Internal Operation Timing
Memory
Refresh
When the 6-bit prescaler in the refresh
counter has been decremented to zero, a
refresh cycle consisting of three T-states is
started as soon as possible (that is, after the
next IFI cycle or Internal Operation cycle).
The 9-bit refresh counter value is put on the
low-order side of the address bus (ADo-ADs);
ADg-ADIS are undefined (Figure 18). Since
the memory is word-organized, Ao is always
Low during refresh and the refresh counter is
always incremented by two, thus stepping
through 256 consecutive refresh addresses on
ADI-ADs. Unless disabled, the presettable
prescaler runs continuously and the delay in
starting a refresh cycle is therefore not
cumulative.
While the STOP input is Low, a continuous
stream of memory refresh cycles, each three
T-states long, is executed without using the
refresh prescaler.
T.--1---- ---+1--CLOCK
AD
Aiii, .iii. NIB
REFRESHADDRES5
>-------- --------
--C
l_-t____
-t__SA_M_,_AS_'"_""_o_ust-"_CL_,_ _ _-t___
Figure 18. Memory Refresh Timing
126
2045-0293. 0294
Halt
A HALT mstruction executes an unlimIted
number of 3-cycle mternal operations,
inter-spersed with memory refresh cycles
whenever requested. An mterrupt, segmentation trap or reset are the only eXIts from a
HALT instruction.
The CPU samples the VI, NVI, NMI and
SEGT inputs at the begmning of every T3
cycle. If an input is found acbve during two
consecutive samples, the subsequent IF] cycle
IS exercised, but aborted, and the normal
interrupt acknowledge cycle is started.
Reset
A Low on the RESET input causes the following results within five clock cycles (Figure 19):
periods, two consecubve memory read cycles
are executed in the system mode. In the 28001,
the first cycle reads the flag and control word
from locabon 0002, the next reads the 7-bit
program counter segment number from locabon 0004, the next reads the 16-blt PC offset
from locabon 0006, and the followmg IF] cycle
starts the program. In the 28002, the first cycle
reads the flag and control word from location
0002, the next reads the PC from location 0004
and the following IF] cycle starts the program.
• ADo-AD]5 are 3-stated
• AS, iSS,
MREQ,
BUSACK and Ma are forced High
• STo-ST3 and SNo-SN6 are forced Low
• Refresh is disabled
• R/W, B/W and Nis are not affected
When RESET has been High for three clock
\~-------------'}-----
....J7
is _ _ _ _ _ _ _ _ _ _ _ _
-JJI
MREQ _ _ _ _ _ _ _ _ _ _ _ _ _
-JJI
O' _ _ _ _ _ _ _ _ _ _ _ _ _ _
....JJI
STO-ST, _ _ _ _ _ _ _ _ _ _ _ _
BlVi
~
___________JJI
., ____________....JJI
Figure 19. Reset Timing
2045·0295
127
Composite
AC Timing
Diagram
Vi,
-W
~
51
~
1====~
~
NVI
~
MI
--®---
K=
--®-
---®--
~
~
~--®---
Ma
~
This composite timing dla·
gram does not show actual
timing sequences Refer to
this diagram only for the
detailed timing relationships
of Individual edges Use the
preceding Illustrations as an
pc::
explanation of the vanous
timing sequences
~
59
y
STOP
y
I~
-®-
-®- -®-
XC
---@--I
69l_
Timing measurements are
made at the following
voltages,
High
Low
C
C
Clock
Output
Input
Float
lC
-:l@)
(
40V
20V
20V
6V
08V
o8V
o 8V
±05V
~
)
r)
1--0--j
CLOCK
J
kD1
CD
'
H:D -
-(i)
1/
1/
HD--
® r-----@
DATA OUT
l-.---@- 1 - -
1=
I-®J
_
"-
~
:x
-&
INPUT/OUTPUT
-@-
r-------~
J
-@
I
.(
1" .. _ _
-L
(
1"" .. _ _
~
I-®-I- -®-
.. _-
~
3a
~
Jot!'
.. _-
.c
---
--®--I- ~
J
--®---
INTERRUP;J
ACKNOWLEDGE
128
rj- >--
fiJ'
-®-
I-
ST o -ST 3 ,
READIWRITE,
NORMAL/SYSTEM,
BYTE/WORD
1-
/"1
---®--
MEMORY WRITE
l>
®-
I-®-
---®-
-
"-
J)~
16
@
10
-®--/ ~ --@
i~ ~l'
f®~
r----
-
>---
~
--®--
"
/
"
DATA IN
MEMORY READ
i
>--
X
MREQ
JI+-@-
K
--@
--0--
ADO-AD15
\
t:j0
SHa-SHa
ADDRESS
------\
~
~
~I
--®-I~ ~
~------------®--
-®--I
V - f;-->--
X
1
2045-0296
ZBOOl/ZB002
Number Symbol
Parameter
Min (ns)
Max (ns)
ZBOOlAlZB002A
Min (ns)
Max (ns)
I
TcC
Clock Cycle TIme
250
2000
165
2000
2
TwCh
Clock Width (High)
105
2000
70
2000
3
TwCl
Clock WIdth (Low)
105
2000
70
2000
4
TIC
Clock Fall TIme
20
10
5 -TrC
Clock RIse T i m e - - - - - - - - - - - - - - - - - 2 0 - - - - - - - - 1 0 - 6
TdC(SNv)
Clock t to Segment Number Vahd (50 pF load)
130
110
20
10
7
TdC(SNn)
Clock t to Segment Number Not Vahd
8
TdC(Bz)
Clock t to Bus Float
65
55
9
TdC(A)
Clock t to Address Vahd
100
75
lO-TdC(Az)---Clock t to Address F l o a t - - - - - - - - - - - - - - 6 5 - - - - - - - - 5 5 - II
TdA(DR)
Address Vahd to Read Data ReqUIred Valid
455*
305*
12
TsDR(C)
Read Data to Clock 1 Setup Time
50
20
80*
40*
13
TdDS(A)
DS t to Address Achve
14
TdC(DW)
Clock t to Write Data Vahd
100
75
15- ThDR(DS)--Read Data to DS t Hold T i m e - - - - - - - - - O - - - - - - - - O - - - - - 16
TdDW(DS)
Write Data Vahd to DS t Delay
295*
195*
17
TdA(MR)
Address Vahd to MREQ 1 Delay
(55)*
(35)*
18
TdC(MR)
Clock 1 to MREQ 1 Delay
80
70
19
TwMRh
MREQ WIdth (HIgh)
210*
135*
20- TdMR(A) - - - MREQ 1 to Address Not A c h v e - - - - - - - - 7 0 * - - - - - - - 3 5 * - - - - - 21
TdDW(DSW)
Write Data Vahd to DS 1 (Write) Delay
55*
35*
22
TdMR(DR)
MREQ 1 to Read Data ReqUIred Vahd
350*
225*
23
TdC(MR)
Clock 1 MREQ t Delay
80
60
24
TdC(ASf)
Clock t to AS 1 Delay
80
60
25- TdA(AS)--- Address Vahd to AS t D e l a y - - - - - - - - - 5 5 * - - - - - - - 3 5 * - - - - - 80
26
TdC(ASr)
Clock 1 to AS t Delay
90
27
TdAS(DR)
AS t to Read Data ReqUIred Vahd
340*
215*
28
TdDS(AS)
DS t to AS 1 Delay
70*
35*
29
TwAS
AS WIdth (Low)
85*
55*
30- TdAS(A)--- AS t to Address Not Achve D e l a y - - - - - - - 6 0 * - - - - - - - 3 0 * - - - - - 31
TdAz(DSR)
Address Float to DS (Read) 1 Delay
0
0
32
TdAS(DSR)
AS t to DS (Read) 1 Delay
70*
35*
33
TdDSR(DR)
DS (Read) 1 to Read Data ReqUIred Vahd
185*
130*
34
TdC(DSr)
Clock 1 to DS t Delay
70
65
35- TdDS(DW)-- DS t to Write Data and STATUS Not V a h d - - - - 7 5 * - - - - - - - 4 5 * - - - - - 36
TdA(DSR)
Address Vahd to DS (Read) 1 Delay
180*
110*
37
TdC(DSR)
Clock t to DS (Read) 1 Delay
120
85
275*
185*
38
TwDSR
DS (Read) WIdth (Low)
39
TdC(DSW)
Clock 1 to DS (Write) 1 Delay
80
95
40- TwDSW--- DS (Write) WIdth ( L o w ) - - - - - - - - - - 1 8 5 * - - - - - - - 1 1 O * - - - - - 41
TdDSI(DR)
DS (1/0) 1 to Read Data ReqUIred Vahd
320*
200*
42
TdC(DSf)
Clock 1 to DS (1/0) 1 Delay
100
120
255*
410*
43
TwDS
DS (1/0) WIdth (Low)
690*
44
TdAS(DSA)
AS t to DS (Acknowledge) 1 Delay
1065*
45- TdC(DSA)-- Clock t to DS (Acknowledge) 1 D e l a y - - - - - - - - - 1 2 0 - - - - - - - - 8 5 - 295*
46
TdDSA(DR)
DS (Ack.) 1 to Read Data ReqUIred Delay
435*
47
TdC(S)
Clock t to Status Vahd Delay
110
85
48
TdS(AS)
Status Vahd to AS t Delay
60*
30*
49
TsR(C)
RESET to Clock t Setup Time
180
70
50- ThR(C)
RESET to Clock t Hold T l m e - - - - - - - - - O - - - - - - - 0 - - - - - 51
TwNMI
NMI WIdth (Low)
100
70
52
TsNMI(C)
NMI to Clock t Setup TIme
140
70
53
TsVI(C)
VI, NV] to Clock t Setup TIme
110
50
54
ThVI(C)
VI, NVI to Clock t Hold Time
0
0
55- TsSGT(C)-- SEGT to Clock t Setup TIme
70
55-----56
ThSGT(C)
SEGT to Clock t Hold TIme
0
0
57
TsMI(C)
MI to Clock t Setup TIme
180
110
58
ThMI(C)
MI to Clock t Hold TIme
0
0
59
TdC(MO)
Clock t to MO Delay
120
85
60- TsSTP(C)-- STOP to Clock 1 Setup TIme - - - - - - - - 1 4 0 - - - - - - - 7 0 - - - - - 61
ThSTP(C)
STOP to Clock 1 Hold TIme
0
0
62
TsW(C)
WAIT to Clock 1 Setup TIme
50
30
63
ThW(C)
WAIT to Clock 1 Hold TIme
10
10
64
TsBRQ(C)
BUSREQ to Clock t Setup TIme
90
80
65- ThBRQ(C)-- BUSREQ to Clock t Hold TIme
10
10-----66
TdC(BAKr)
Clock t to BUSACK t Delay
75
100
67
TdC(BAKf)
Clock t to BUSACK 1 Delay
75
100
*
Clock-cycle-hme-dependent characteristics See table on followmg page
129
N
00
C
C
....
N
Q
c::
ClockCycle-TimeDependent
Characteristics
Number
Symbol
Z800l/Z8002
Equation
Z800lA/Z8002A
Equation
II
TdA(DR)
2TeC + TwCh - 150 ns
2TeC + TwCh - 95 ns
13
TdDS(A)
TwCI- 25 ns
TWCI- 30 ns
16
TdDW(DS)
TeC + TwCh - 60 ns
TeC + TwCh - 40 ns
TwCh - 35 ns
TdA(MR)
TwCh - 50 ns
17
1 9 - - - TwMRh---TeC - 40 ns
TeC - 30 ns
20
TdMR(A)
TwCI- 35 ns
TwCI- 35 ns
21
TdDW(DSW)
TwCh - 50 ns
TwCh - 35 ns
22
TdMR(DR)
2TeC - 150 ns
TdA(AS)
TwCh - 50 ns
25
27---TdAS(DR)--2TeC - 160 ns
2TeC - 105 ns
TwCh - 35 ns
2TeC - 115 ns
TwCI- 35 ns
28
TdDS(AS)
TwCI- 35 ns
29
TwAS
TdAS(A)
TwCh - 20 ns
TwCh - 15 ns
TwCl- 45 ns
TwCl- 40 ns
TwCl - 35 ns
30
TdAS(DSR)
TwCl - 35 ns
32
33---TdDSR(DR)--TeC + TwCh -170 ns--TeC + TwCh - 105 n s - - - - - - - -
130
35
TdDS(DW)
TwCl - 30 ns
TwCl - 25 ns
36
TdA(DSR)
TeC - 70 ns
TeC - 55 ns
TeC + TwCh - 80 ns
38
TwDSR
TeC - 65 ns
40
TwDSW
41 ---TdDSI(DR) --2TeC - 180 ns
TeC + TwCh - 50 ns
2TeC - 130 ns
43
TwDS
2TeC - 90 ns
2TeC - 75 ns
44
TdAS(DSA)
4TeC + TwCl - 40 ns
4TeC + TwCl - 40 ns
46
48
TdDSA(DR)
2TeC + TwCh - 170 ns
TdS(AS)
TwCh - 55 ns
2TeC + TwCh - 105 ns
TwCh - 40 ns
TeC - 55 ns
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature .................. O°C to + 70°C
Storage Temperature ........ -65°C to + 150 °C
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available opercrting temperature
ranges are:
Stresses greater than those lIsted under Absolute MaxI~
mum Ratmgs may cause permanent damage to the devIce.
ThIs IS a stress ratmg only; operahon of the devIce at any
condIhon above those mdlcated m the operatIOnal sechons
of these specifIcatIons lS not Imphed. Exposure to absolute
maXImum ratmg conditIons for extended perIods may affect
devIce relIabIlIty.
temperature range may be found in the ordering information section.
+SV
• O°C to + 70°C,
+4.75 V,:; Vee':; +5.25V
•
-40°C to +85°C,
+4.75 V,:; Vee':; +5.25 V
•
-55°C to + 125°C,
+4.5 V,:; Vee':; +5.5V
All dC parameters assume a load capaCltance of 100 pF max, except for parameter 6 (50 pF max) Tlmmg references between two
output signals assume a load dlfference of 50 pF max
The product number for each operating
DC
Characteris tics
Orderin~
Information
Symbol
Parameter
Min
Max
Unit
VeH
Clock Input HIgh Voltage
Vee-O.4
Vee+ 0.3
V
DrIven by External Clock
Generator
VeL
Clock Input Low Voltage
-0.3
0.45
V
DrIven by External Clock
Generator
VIH
Input HIgh Voltage
2.0
Vee+ 0.3
V
VIH RESET
Input HIgh Voltage on RESET
pm
2.4
Vee to.3
V
VIL
Input Low Voltage
-0.3
0.8
VOH
Output HIgh Voltage
VOL
Output Low Voltage
0.4
V
IlL
Input Leakage
±IO
}'A
Input Leakage on SEGT pm
100
}'A
Output Leakage
±IO
'}'A
ICC
Vee Supply Current
300
rnA
Package/
Temp
Speed
CE
4.0 MHz
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001A
CM
CMB
CS
DE
DS
PE
PS
CE
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
6.0 MHz
Z8001A
Z8001A
Z8001A
Z8001A
Z8001A
CS
DE
DS
PE
PS
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
-100
V
IlL SEGT
Product
Number
Description
CPU (segmented,
40-pm)
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
CPU (segmented,
40-pin)
Same as above
Same as above
Same as above
Same as above
Same as above
Product
Number
IOH = -250}'A
IOL
= +2.0 rnA
0.4:5 VIN:5 +2.4 V
0.4 :5 VIN :5 + 2.4 V
Package/
Temp
Speed
Z8002
CE
4.0 MHz
Z8002
Z8002
Z8002
Z8002
Z8002
Z8002
Z8002
Z8002A
CM
CMB
CS
DE
DS
PE
PS
CE
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
6.0 MHz
Z8002A
Z8002A
Z8002A
Z8002A
Z8002A
CS
DE
DS
PE
PS
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
NOTES: C = Ceramic, D = Cercilp, P = Plasllc; E = -40°C to +85°C, M
MIL-STD-B83 Wlth Class B processmg, S = O'fC to + 70°C.
8085-0006
V
2.4
IoL
Z8001
00·2045·A
Condition
= -55°C to
+ 125°C, eM
= _55°C to
Description
CPU (nonsegmented, 40-pin)
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
CPU (nonsegmented, 40-pm)
Same as above
Same as above
Same as above
Same as above
Same as above
+ 125°C with
131
N
I
N
•c::n
-
Z8010
Z8000™Z·MMU Memory
Management Unit
~
Zilog
Product
Specification
March 1981
Features
• DynamIc segment relocation makes software
addresses mdependent of physIcal memory
addresses.
65,536 bytes can be mapped into a total
physical address space of 16M bytes; all 64
segments are randomly accessIble.
• SophIsticated memory-management features
include access validation that protects
memory areas from unauthorized or
unmtentlonal access, and a wrlte-warnmg
mdicator that predICts stack overflow.
• Multiple MMUs can support several translation tables for each 28001 address space.
• MMU archItecture supports multl-programmmg systems and vIrtual memory Implementations.
• 64 variable-sized segments from 256 to
General
Description
The 28010 Memory Management Umt (MMU)
manages the large 8M byte addressmg spaces
of the 28001 CPU. The MMU provIdes dynamIc
segment relocation as well as numerous
memory protectIOn features.
DynamIc segment relocation makes user software addresses mdependent of the physIcal
memory addresses, thereby freemg the user
from specifymg where mformatlon IS actually
ADDRESSI
DATA
I
_AD"
A23
......... AD14
A"
......... AD13
A"
........ AD12
A"
.......... ADl1
A"
..........
A0 11)
os
DMASYNC
A"
AD,
A"
........ ADs
A"
PHYSICAL
ADDRESS
A"
SN,
A"
SN,
A"
SN,
Z8010
MMU
SN,
SN,
SEGMENT
A"
A"
SN,
A"
A,
SNo
A,
SEQT
TRAP
DMAISEGMENT ----+-
DMA SYNC
Ri'ii_)
NtS
BUS TIMING
{
- - . AS
--.
5 12"""'STl
CHIP SELECT --+-
cs
+5V
~
ST3~
os
...--
Sio ....--
STATUS
N/S
R/iii
SEGT
os
sUP
AS
REseT
STo
A"
ST,
A"
ST,
A"
ST,
A"
AD,
A"
AD,
Vee
AD10
A"
ADi1
A"
eLK
A"
OND
A"
AD12
A"
AD13
A"
AD14
A"
AD15
A"
SNo
A"
A,
SN,
A,
SN,
RESERVED
SN,
SN,
SN,
SN,
GND elK RESET
Figure 1. Pin Functions
2046·051. 033
located m the physIcal memory. It also proVIdes a fleXIble, effiCIent method for supportmg multl-programmmg systems. The MMU
uses a translatIOn table to transform the 23-blt
logIcal address output from the 28001 CPU
mto a 24-blt address for the physIcal memory.
(Only logIcal memory addresses go to an MMU
for translation; I/O addresses and data, m
general. must bypass this component.)
Figure 2. Pin Assignments
133
N
GO
eo
iii
iii
c:
General
Description
(Continued)
Memory segments are variable in size from
256 bytes to 64K bytes, in increments of 256
bytes. Pairs of MMUs support the 128 segment
numbers available for the various Z8001 CPU
address spaces. Within an address space, any
number of MMUs can be used to accommodate
multiple translation tables for System and Normal operahng modes, or to support more
sophisticated memory-management systems.
MMU memory-protection features safeguard
memory areas from unauthorized or unintended access by associating special access
restrictions wIth each segment. A segment is
assigned a number of attributes when its
descriptor initially entered into the MMU.
When a memory reference is made, these
attributes are checked agamst the status information supplied by the Z8001 CPU. If a
-
SEGMENT NUMBER
OFFSETIDATA
SNG-SNe
AOa-AD15
----510·5T3
SEQT
S'iJ'P
RiW, NlS:
STATUS
INFORMATION
SEGMENT SUPPRESS PHYSICAL
TRAP
REQUEST
ADDRESS
mismatch occurs, a trap is generated and the
CPU is interrupted. The CPU can then check
the status registers of the MMU to determine
the cause.
Segments are protected by modes of permitted use, such as read only, system only,
execute only and CPU-access only. Other segment management features include a writewarning zone useful for stack operations and
status flags that record read or write accesses
to each segment.
The MMU is controlled via 22 Special IIO
instructions from the Z8001 CPU in System
mode. With these instructions, system software
can assign program segments to arbitrary
memory locations, restrict the use of segments
and monitor whether segments have been read
or written.
SEQMENT NUMBER
Slo·5T3
R/W, NlS
SEGT
OFFSEYIOATA
SliP
STATUS
SEGMENT SUPPRESS PHYSICAL
INFORMATION
TRAP
ADDRESS
REQUEST
Figure 3. The shaded areas in these block diagrams illustrate the resources used in the two modes of MMU operation. In
the Address Translation Mode shown on the left. addresses are translated automatically. In the Command Mode shown
on the right. specific registers are accessed using Special 1/0 commands.
134
2046-028
Segmented
Addressing
Memory
Protection
2046·029
A segmented addressing space-compared
with linear addressing-Is closer to the way a
programmer uses memory because each procedure and data set can reside in its own
segment.
The 8M byte Z800 I addressing spaces are
dIvided into 128 relocatable segments of up to
64K bytes each. A 23-bit segmented address
uses a 7-bit segment address to point to the
segment, and a 16-bit offset to address any
byte relative to the beginnmg of the segment.
The two parts of the segmented address may
be manipulated separately.
The MMU dIvides the physIcal memory mto
256-byte blocks. Segments consist of physically
contiguous blocks. Certain segments may be
designated so that writes into the last block
generate a warnmg trap. If such a segment is
used as a stack, thIs warning can be used to
mcrease the segment sIze and prevent a stack
overflow error.
The addresses mampulated by the programmer, used by mstructions and output by the
Z8001 are called logical addresses. The MMU
takes the logIcal addresses and transforms
them mto the physical addresses required for
accessing the memory (Figure 4). ThIs address
transformahon process is called relocatIon.
The relocahon process IS transparent to user
software. A translation table m the MMU
associates the 7-blt segment number WIth the
base address of the physical memory segment.
The 16-bit logical address offset is added to the
physical base address to obtain the actual
physIcal memory location. Because a base
address always has a low byte equal to zero,
only the high-order 16 bIts are stored in the
MMU and used m the addihon. Thus the loworder byte of the physical memory location IS
the same as the low-order byte of the logical
address offset. This low-order byte therefore
bypasses the MMU, thus reducing the number
of pins required.
Each memory segment IS aSSIgned several
attributes that are used to provIde memory
access protechon. A memory request from the
Z8001 CPU is accompanied by status mformahon that indIcates the attributes of the memory
request. The MMU compares the memory
request attributes with the segment attributes
and generates a Trap Request whenever it
detects an attribute vlOlahon. Trap Request
informs the Z800l CPU and the system control
program of the vlOlahon so that appropriate
aclton can be taken to recover. The MMU also
generates the Suppress sIgnal SUP m the
event of an access violation. Suppress can be
used by a memory system to inhIbit stores mto
the memory and thus protect the contents of
the memory from erroneous changes.
Five attributes can be associated with each
segment. When an attempted access VIOlates
anyone of the attributes assocIated with a segment, a Trap Request and a Suppress sIgnal
are generated by the MMU. These attributes
are read only, execute only, system access
only, inhibIt CPU accesses and inhibIt DMA
accesses.
Segments are speclhed by a base address
and a range of legal offsets to thIS base
address. On each access to a segment, the offset IS checked against this range to insure that
the access falls wlthm the allowed range. If an
access that lies outside the segment IS attempted, Trap Request and Suppress are generated.
Normally the legal range of offsets withm a
segment is from a to 256N + 255 bytes, where
0~N~255. However, a segment may be
specihed so that legal offsets range from 256N
to 65,535 bytes, where 0~N~255. The latter
type of segment IS useful for stacks since the
Z8001 stack mampulahon instrucltons cause
stacks to grow toward lower memory locations.
Thus when a stack grows to the limit of its
allocated segment, addItional memory can be
allocated on the correct end of the segment.
As an aid in maintaining stacks, the MMU
detects when a write IS performed to the lowest
allocated 256 bytes of these segments and
generates a Trap Request. No Suppress sIgnal
IS generated so the write IS allowed to proceed.
This write warnmg can then be used to indIcate that more memory should be allocated to
the segment.
23·BIT LOGICAL ADDRESS
6 5
BIT SNe MUST BE
EaUAL TO FLAG URS
0
15
8
1
J~~~"-----'-------1
SEQ NO
OFFSET
,---------rSEoNO.l
I ':R~ ~R~ I
r-------------~~ 0 " I
"I
TABLE OF 64
SEGMENT DESCRIPTOR
REGISTERS
o
1
o
1
o
1
1
n
".,
n+641
0
1
1
1
1
1
1
24·BIT PHYSICAL ADDRESS
Figure 4. Logical-to-Physical Address Translation
135
MMU
The MMU contains three types of registers:
Register
Segment Descriptor, Control and Status. A
Organization set of 64 Segment Descriptor Registers supplies
the information needed to map logical memory
addresses to physical memory locations. The
segment number of a logical address determmes which Segment Descriptor Register is
used in address translation. Each Descriptor
Register also contains the necessary mformahon for checking that the segment location
referenced is within the bounds of the segment
and that the type of reference is permItted. It
also indicates whether the segment has been
read or written.
In addition to the Segment Descriptor
Registers, the 28010 MMU contains' three 8-bit
control registers for programming the device
and six 8- bit status registers that record informahon in the event of an access violation.
Segment Descriptor Registers. Each of the 64
Descriptor Registers contains a l6-bit base
address field, an 8-bit limit field and an 8-bit
attribute field (Figure 5). The base address
field is subdivided into high- and low-order
bytes that are loaded one byte at a time when
the descriptor is inihalized. The limIt field contains a value N that indicates N + 1 blocks of
256 bytes have been allocated to the segment. *
The attribute field contains eight flags
(Figure 6). Five are related to protecting the
segment agamst certam types of access, one
indicates the speCIal structure of the segment,
and two encode the types of accesses that have
been made to the segment. A flag is set when
its value is 1. The following brief descriptions
indicate how these flags are used.
Read-Only (RD). When thIs flag IS set, the segment IS read
only and IS protected agaInst any WrIte access.
System-Only (SYS). When thIs flag IS set. the segment can
be accessed only In system mode, and IS protected agamst
any access In normal mode.
CPU-Inhlblt (CPUl). When thIs flag IS set, the segment IS
not accessIble to the currently executmg process, and IS
protected agamst any memory access by the CPU. The
segment }s, however, accessable under DMA.
Execute-Only (EXC). When thIs flag IS set, the segment
can be accessed only durmg an InstructIon fetch cycle, and
thus IS protected agamst any access durmg other cycles.
DMA-Inhlblt (DMAI). When thIs flag IS set, the segment
can be accessed only by the CPU, and thus IS protected
agamst any access under DMA.
Duechon and Warmng (DlRW). When thIS flag IS set, the
segment memory locahons are consIdered to be orgamzed
descendmg order and each WrIte to the segment IS
checked for access to the last 256-byte block. Such an
access generates a trap to warn of potentIal segment
overflow, but no Suppress sIgnal IS generated.
In
Changed (CHG). When thIs flag IS set, the segment has
been changed (wrItten). ThIS bIt IS set automallcally durmg
any WrIte access to thIS segment If the WrIte access does not
cause any vIOlatIon.
Referenced (REF). When thIS flag IS set, the segment has
been referenced (eIther read or wrItten). ThIS bIt IS set
automatIcally durmg any access to the segment If the
access does not cause a vIolatIon.
*In the stack mode, segment
136
SIze IS
BASE ADDRESS LIMIT ATIRIBUTE
FIELD
FIELD
FIELD
~
15
8
0
0
,
,
,
::~~ 1 ::~~
BAH2
BAL2
I
I
I
I
I
I
I
LO
11
L2
AO
A1
A2
SDR63 BAH63 BAL63
L63
A63
SDRO
SOR1
SDR2
~
Figure S. Segment Descriptor Registers
,
0
I
REF \CHG \DIRW\DMAI\ EXC \CPUI\ SYS
I I
RD
Figure 6. Attribute Field in Segment Descriptor Register
Control Registers. The three user-accessIble
8-bit control registers in the MMU direct the
functiomng of the MMU (FIgure 7). The Mode
RegISter provides a sophisticated method for
selecbvely enabling MMUs in multiple-MMU
conhguratlOns. The Segment Address Register
(SAR) selects a particular Segment Descnptor
Register to be accessed during a control
operatIOn. The DeSCriptor Selechon Counter
RegIster points to a byte wIthin the Segment
Descriptor RegIster to be accessed during a
control operation.
MODE
65
0
DSC
I
'---'-_'---'-_'---'-_'-_''-....1
DESCRIPTOR
SELECTION
COUNTER
Figure 7. Control Registers
The Mode RegIster contains a 3-bit identIfication held (ID) that dIstinguishes among
eight enabled MMUs in a mulhple-MMU conhguration. This field IS used during the segment trap acknowledge sequence (refer to the
sectIOn on Segment Trap and Acknowledge).
In addihon, the Mode Register contams five
flags.
Mulhple Segment Table (MST). ThIS flag mdlcates whether
mulhple segment tables are present m the hardware conhguratIon. When thIS flag IS set, more than one table IS
present and the Nis lme must be used to determme
whether the MMU contams the approprIate table.
Normal Mode Seleel (NMS). ThIS flag mdlcates whether
the MMU IS to translate addresses when the N/S lme IS
HIgh or Low. If the MST flag IS set, the N/S lme must
match the NMS flag for the MMU to translate segment
addresses, otherWIse the MMU Address lmes remam
3-stated.
64K-256N.
2046-030, 031
Upper Range Select (URS). ThIs flag IS used to mdlcate
MMU
whether the MMU contams the lower-numbered segment
Register
descrIptors or the higher-numbered segment descrIptors.
Organization The most slgmfIcant bIt of the segment number must match
(Continued)
the URS flag for the MMU to translate segment addresses,
otherwIse the MMU Address lmes remam 3-stated.
Translate (TRNS). ThIs flag mdlcates whether the MMU IS
to translate logIcal program addresses to physIcal memory
locatIons or IS to pass the logIcal addresses unchanged to
the memory and wIthout protectIon checkmg. In the nontranslatIOn mode, the most slgmfIcant byte of the output IS
the 7-blt segment number and the most sIgmfIcant bIt IS O.
When thIs flag IS set, the MMU performs address translahon and attrIbute checkmg.
Master Enable (MSEN). ThIs flag enables or dIsables the
MMU from performmg Its address translatIon and memory
protectIOn funchons. When thIs flag IS set, the MMU performs these tasks; when the flag IS clear the Address lmes
of the MMU remam 3·stated.
The Segment Address Register (SAR) points
to one of the 64 segment deSCriptors. Control
commands to the MMU that access segment
deSCriptors Imphcitly use this pOinter to select
one of the descriptors. This regIster has an
auto-incremenhng capablhty so that multiple
descriptors can be accessed in a block
reael/wrlte fashlOn.
The DeSCriptor SelectlOn Counter Register
holds a 2-bit counter that indIcates whICh byte
In the deSCriptor is being accessed during the
reading or writing operahon. A value of zero
In thIS counter indIcates the hIgh-order byte of
the base address field is to be accessed, one
indicates the low-order byte of the base
address, two indICates the hmlt held and three
indIcates the attribute held.
Status Registers. Six 8-blt regIsters contain
information useful in recovering from memory
access violations (FIgure 8). The Violahon
Type Register describes the condihons that
generated the trap. The VlOlahon Segment
Number and Violahon Offset RegIsters record
the most-slgmhcant 15 bits of the logIcal
address that causes a trap. The InstructlOn
Segment Number and Offset RegISters record
the most-slgmhcant 15 bits of the logICal
address of the last Instruchon fetched before
the hrst accessing vlOlahon. These two
regISters can be used in conjunction WIth
external cIrcUItry that records the low-order
offset byte. At the time of the addressing vlOlahon, the Bus Cycle Status Register records the
bus cycle status (status code, reael/wrlte mode
and normal/system mode).
The MMU generates a Trap Request for two
general reasons: eIther It detects an access
2046-032
vlOlation, such as an attempt to write Into a
read-only segment, or It detects a warmng
condihon, which IS a write Into the lowest 256
bytes of a segment with the DIRW flag set.
When a violahon or warning condlhon is
detected, the MMU generates a Trap Request
and automahcally sets the appropriate flags.
The eIght flags In the VlOlation Type RegIster
deSCribe the cause of a trap.
Read·Only VlOlahon (RDV). Set when the CPU attempts to
access a read-only segment and the R/W lIne IS Low.
System Violahon (SYSV). Set when the CPU accesses a
system-only segment and the Nis lme IS HIgh.
CPU-InhIbit Violation (CPUlV). Set when the CPU
attempts to access a segment WIth the CPU-mhlblt flag set.
Execute·Only VlOlahon (EXCV). Set when the CPU
attempts to access an execute-only segment In other than
an Instruction fetch cycle
Segment Length Violahon (SLV). Set when an offset falls
outSIde of the legal range of a segment.
Primary Write Warning (PWW). Set when an access IS
made to the lowest 256 bytes of a segment WIth the DIRW
flag set.
Secondary Wnte Warmng (SWW). Set when the CPU
pushes data mto the last 256 bytes of a system stack and
EXCV, CPUIV, SLY, SYSV, RDV or PWW IS set. Once thIS
flag IS set, subsequent WrIte warnIngs for acceSSing the
system stack do not generate a Segment Trap request.
Fatal Condition (FATL). Set when any other flag m the
VIOlatIon Type Register IS set and either a vl0lahon IS
detected or a WrIte warmng condItIon occurs In normal
mode. ThIS flag IS not set durIng a stack push In system
mode that results In a warmng condItIon. ThiS flag
mdICates a memory access error has occurred In the trap
processmg routme. Once set, no Trap Request Signals are
generated on subsequent VIolations. However, Suppress
Signals are generated on thiS and subsequent CPU viola-
hons unhl the FATL flag has been reset.
,
°
IFATL\SWW\PWW\ExcvfpUlv\ SLV !SYSV\ ADV
I ~~~~ATION
SEGMENT NUMBER
I
I
UPPER OFFSET
o
! NIS \ RIW !
CPU STATUS
I;. '- r l - - - - - - - - - - ' i
L_0....l.._,-_S...
'_GM_'...
N_T_NU...M_B...J'R,-..J...--'
UPPER OFFSET
L-~~~'~
__'~~~~
VIOLATION
SEGMENT
NUMBER
VIOLATION
OFFSET
BUS
CYCLE
STATUS
INSTRUCTION
~~~~~~T
INSTRUCTION
OFfSET
Figure 8. Status Registers
137
The 28010 MMU generates a Segment Trap
Segment
Trap and
when it detects an access vlOlatJon or a
Acknowledge write warmng condItion. In the case of an
access violatJon, the MMU also actJvates Suppress, whICh can be used to inhibit memory
writes and to flag special data to be returned
on a read access. Segment Trap remams Low
until a Trap Acknowledge signal is received. If
a CPU-generated violation occurs, Suppress is
asserted for that cycle and all subsequent CPU
instruction execuhon cycles until the end of
the mstruction. Intervening DMA cycles are
not suppressed, however, unless they generate
a violation. Violahons detected during DMA
cycles cause Suppress to be asserted during
that cycle only-no Segment Trap Requests are
ever generated durmg DMA cycles.
Segment traps to the 28001 CPU are handled sImilarly to other types of mterrupts. To
serVIce a segment trap, the CPU issues a segment trap acknowledge cycle. The acknowledge cycle IS always preceded by an instruction fetch cycle that is aborted (the MMU has
been desIgned so that thIS dummy cycle IS
Ignored). Durmg the acknowledge cycle all
enabled MMUs use the AddresslData Imes to
indIcate theIr status. An MMU that has
generated a Segment Trap Request outputs a 1
on the AID Ime assocIated wIth the number in
ItS ID held; an MMU that has not generated a
segment trap request outputs a 0 on Its
associated AID line. AID lines for whIch no
MMU IS assocIated remain 3-stated. Durmg a
segment trap acknowledge cycle, an MMU
uses AID line 8 + I if its ID field IS i.
Following the acknowledge cycle the CPU
automatically pushes the Program Status and
Program Counter onto the system stack and
loads another Program Status and Program
Counter from the Program Status Area. The
Segment Trap line is reset during the segment
trap acknowledge cycle. Suppress is not
generated during the stack push. If the store
creates a write warning condition, a Segment
Trap Request is generated and is serviced at
the end of the context swap. The SWW flag is
also set. Servicing thIS second Segment Trap
Request also creates a wnte warning condition,
but because the SWW flag is set, no Segment
Trap Request is generated. If a violahon rather
than a wnte warning occurs during the context
swap, the FATL flag is set rather than the
SWW flag. Subsequent violations cause Sup. press to be asserted but not Segment Trap
Request. Without the SWW and FATL flags,
trap processing routines that generate memory
violations would repeatedly be interrupted and
called to process the trap they created.
The CPU routme to process a trap request
should first check the FATL flag to determine
If a fatal system error has occurred. If not, the
SWW flag should be checked to determine if
more memory is required for the system stack.
Finally, the trap itself should be processed and
the ViolatJon Type RegIster reset.
Virtual
Memory
Several features of the MMU can be used m
conJunchon with external CirCUItry to support
virtual memory for the 28001. Segment Trap
Request can be used to SIgnal the CPU in the
event that a segment is not m pnmary memory.
The CPU-InhIbit Flag can be used to mdicate
whether a segment IS m the memory or in
secondary storage. The Changed and Altered
Flags in the attribute field for each segment
can aid m implementmg efhclent segment
management policies. The Status Registers can
be used m recovering from virtual memory
access faults.
Multiple
MMUs
MMU archItecture dIrectly supports two
methods for multJple MMU configurahons. The
hrst approach extends single-MMU capability
for handlmg 64 segments to a dual-MMU conhguratJon that manages the 128 dIfferent
segments the 28001 can address. ThIS scheme
uses the URS flag m the Mode RegIster m connechon wIth the hIgh-order bit of the segment
number (SN6).
The second approach uses several MMUs to
Implement mulhple translahon tables. Mulhple
tables can be used to reduce the hme reqUIred
to SWItch tasks by asslgnmg separate tables to
each task. Mulhple translahon tables for mulh-
task envIronments can use the Master Enable
Flag to enable the appropriate MMUs through
software. Multiple translatJon tables may also
be used to extend the phYSIcal memory sIze
beyond 16 megabytes by separating system
from normal memory andlor program from
data memory. The MST and NMS flags in the
Mode Register can be used m conjunction WIth
the Nis Ime to select the MMU that contams
the appropnate table. SpeCIal external circuitry that mom tors the CPU Status Imes can
mampulate the MMU Nis Ime to perform thIS
selection.
138
DMA
Operation
MMU
Commands
Direct memory access operations may occur
between Z8001 instruction cycles and can be
handled through the MMU. The MMU permits
DMA in either the System or Normal mode of
operation. For each memory access, the segment attributes are checked and if a violation
is detected, Suppress is activated. Unlike a
CPU violation that automatically causes Suppress signals to be generated on subsequent
memory accesses until the next instruction,
DMA violations generate a Suppress only on a
per memory access basis.
The DMA device should note the Suppress
signal and record sufficient information to
enable the system to recover from the access
violation. No Segment Trap Request is ever
generated during DMA, hence warning
conditions are not signaled. Trap Requests are
not issued because the CPU cannot
acknowledge such a request.
The various registers in the MMU can be
read and written using Z8001 CPU special 1/0
commands. These commands have machine
cycles that cause the Status lines to indicate an
SIO operation is m progress. During these
machine cycles the MMU enters command
mode. In this mode, the rising edge of the
Address Strobe indicates a command is present on the ADs-ADI5. If this command
indicates that data is to be written int.o one of
the MMU registers, the data is read from
ADs-AD 15 while Data Strobe is Low. If the
command indicates that data is to be read from
one of the MMU registers, the data is placed
on ADs-ADI5 while Data Strobe is Low.
There are ten commands that read or write
various fields in the Segment DeSCriptor
Register. The status of the Read/Write line
indicates whether the command is a read or a
write.
The auto-incrementing feature of the Segment Address Register (SAR) can be used to
block load segment descriptors using the
repeat forms of the Special 1/0 instructions.
The SAR is auto incremented at the end of the
field. In accessing the base field, first the
high-order byte IS selected and then the loworder byte. The command accessing the entire
Descriptor Register references the fields in the
order of base address, limit and attribute.
At the start of a DMA cycle, DMASYNC
must go Low, indicatmg to the MMU the
beginning of a DMA cycle. A Low DMASYNC
inhibits the MMU from using an indetermmate
segment number on lines SNo-SN6. When the
DMA logical"memory address is valid, the
DMASYNC line must be High on a rising edge
of Clock and the MMU then performs its
address translation and access protection functions. Upon the release of the bus at the termination of the DMA cycle the DMASYNC line
must again be High. After two clock cycles of
DMASYNC High, the MMU assumes that the
CPU has control of the bus and that subsequent memory references are CPU accesses.
The first instruction fetch occurs at least two
cycles after the CPU regains control of the
bus. During CPU cycles, DMASYNC should
always be High.
Opcode (Hex)
OS
09
OA
OB
OC
OD
OE
OF
IS
Instruction
Read/WrIte Base FIeld
Read/WrIte LImIt FIeld
Read/WrIte AttrIbute FIeld
Read/WrIte DeSCrIptor (all he Ids)
Read/WrIte Base FIeld; Increment SAR
Read/WrIte LImIt FIeld; Increment SAR
Read/WrIte AttrIbute FIeld; Increment
SAR
Read/WrIte DeSCrIptor; Increment SAR
Set All CPU-InhIbIt AttrIbute Flags
Set All DMA-Inhlblt AttrIbute Flags
16
Three commands are used to read and write
the control registers.
Opcode (Hex)
Instruction
Read/WrIte Mode RegIster
00
01
Read/Write Segment Address RegIster
20
Read/Write DeSCrIptor Selector Counter
RegIster
The Status Registers are read-only registers,
although the Violation Type Register (VTR)
can be reset. Nme mstructions access these
regISters.
Opcode (Hex)
Instruction
Read VlOlalton Type RegIster
02
Read VIOlatIOn Segment Number RegIster
03
Read Vlolalton Offset (HIgh-byte) RegIster
04
Read Bus Status RegIster
05
Read Instruchon Segment Number
06
RegIster
07
Read Instruclton Offset (HIgh-byte)
II
13
14
Reset Vlolalton Type RegIster
Reset SWW Flag In VTR
Reset FATL Flag In VTR
RegIster
139
MMU
Timing
The 28010 translates addresses and checks
for access vIOlatIOns by steppmg through
sequences of basIc clock cycles correspondmg
to the cycle structure of the 2800 I CPU. The
followmg hmmg diagrams show the relahve
hmmg relatIOnshIps of MMU sIgnals during the
basIc operahons of memory read/wnte and
MMU control commands. For exact timmg
mformatlOn, refer to the composite hmmg
diagram.
Memory Read and Write. Memory read and
mstruchon fetch cycles are Identical, except
for the status mformatlOn on the STo-ST3
mputs. Durmg a memory read cycle (FIgure 9)
the 7-blt segment number IS mput on SNo-SN6
one clock penod earl1er than the address offset; a HIgh on DMASYNC during T3 indIcates
that the segment offset data IS vahd. The most
slgniilcant eight bIts of the address offset are
placed on the ADo-AD15 mputs early m the
-T,----1
r-T'-~+-T,--t'I-'
CLOCK
I
~
I
I
I
lr----1l
Nis,
STo-ST3
DMASVNC
DON'T CARE
SEGMENT NUMBER
SNO-SNS
J
/
\
'\
PHYSICAL ADDRESS
/
/
--
OFFSET
ADe- A D15
\
HlW
140
/
(
DATA IN
)
.-.~
L
2046-034
MMU
Timing
(Contmued)
hrst clock penod. Vahd address offset data IS
Indicated by the nSIng edge of Address
Strobe. Status and mode InfOrmatlOn become
valid early m the memory access cycle and
remaIn stable throughout. The most slgmfJcant
l6-bltS of the address (physical memory locaIton) remam va ltd unltl the end of T3. Segment
Trap Request and Suppress are asserted In T2.
Segment Trap Request remaInS Low unltl Segment Trap Acknowledge IS received. Suppress
IS asserted durIng the current mach me cycle
and termmates durmg T3. Suppress IS
repeatedly asserted durmg CPU mstructl0n
execulton cycles untt! the current mstruchon
has termmated.
r-T'_~+_T,_+t++_T'-1
CLOCK
~
"
" - - - - ,-
NIS,
STo-STa
SNa-SNe
DMASVNC
<
.J \
DON'T CARE
SEGMENT NUMBER
,
j
Aa-A23
\
PHYSICAL ADDRESS
~
J
SUP
ADa-AD15
Riw
~
J
OFFSET
DATA OUT
/
\
Figure 10. Memory Write Timing
2046·198
141
MMU
Timing
(Continued)
MMU Command Cycle. During the command
cycle of the MMU (FIgure ll), commands are
placed on the Address/Data lines durmg TI.
The Status lmes mdlcate that a specIal I/O
mstruchon is m progress, and the ChIp Select
lme enables the appropnate MMU for that
command. Data to be wntten to a register m
the MMU must be vahd on the Address/Data
lines late m T2. Data read from the MMU is
i-
CLOCK
placed on the Address/Data lines late m the
TWA cycle.
Input/Output and Refresh. Input/Output and
Refresh operations are mdicated by the status
lmes STO-ST3. During these operahons, the
MMU refrains from any address translahon or
protection checkmg. The address lines AS-A23
remain 3-stated.
WA-r-
T' - + - T 2 - + - T
J
I
1
1 1
1
1
-i
1 '---1-
T3
cs
STo-ST3
-
- P-_..tr®
----------------------------,'~
.~
-----.~~I.,..
____________________________________ _
~~~-------------------------------------
~kJa)
OO·2046·A
2046·122
147
Z8030 Z8000™ Z-SCC
Serial Communications
Controller
~
Product
Specification
Zilog
March 1981
Features
• Two independent, 0 to 1M bit/second, fullduplex channels, each wlth a separate
crystal osclllator, baud rate generator, and
Dlgital Phase-Locked Loop for clock
recovery.
• Synchronous mode with internal or external
character synchronizahon on one or two
synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
• Mulh-protocol operahon under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handhng, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Asynchronous mode with five to eight blts
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detechon and generation; parity,
overrun, and frammg error detection.
General
Description
• Local Loopback and Auto Echo modes.
communications applications. The device contams a variety of new, sophishcated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications penpheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a senal-to-parallel, parallel-to-serial converter/controller. The Z-SCC can be softwareconfigured to satisfy a wide variety of serial
ADDRESS/I~
DATABUS1~
AD,
TxOA
AD,
RxOA
AD,
TAxCA
AD,
AD,
SYNCA
AD,
WIREOA
AD,
DTRIREOA
ADo
RISA
As
I~ Os
CONTROL.!=:
INTERRUPT
=:
1
} SERIAL
DATA
- - . . } CHANNEL
RT)(CA .....-- CLOCKS
TIM~~~ 1-----AND RESET
..-
elSA
CH-A
CHANNEL
CONTROLS
FOR MODEM,
DMA,QR
OTHER
TxDB
cs,
CSo
RxDS
ADo
AD,
AD,
AD,
AD,
AD,
AD,
Wi
Os
As
lEO
lEI
DeOA
R/W
AD,
CSo
+5V
cs,
WIREOA
SYNCA
RTxCA
TRJlCB
INT
RxDA
RTxCB
TRxCA
INTACK
SYNCS
WIREQB
lEI
lEO
OTR/REDS
Alsa
Z8030
elSs
Z·SCC
DeDa
CHANNEL
CONTROLS
FOR MODEM,
DMA,OR
OTHER
CH-B
A/W
INTACK
TxOA
DTRIREQA
RISA
GNO
W/REOB
SYNCe
RTxCB
AxDS
TRxeB
hOB
OTR/REDS
elSA
RTSS
DeOA
elsa
PCLK
DeDa
t t
+5V
GND PClK
Figure I. Pin Functions
2016-039. 041
Figure 2. Pin Assignment.
149
General
Description
(Continued)
The Z-SCC handles asynchronous formats,
synchronous byte-oriented protocols such as
IBM Bisync, and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
The device can generate and check CRC
codes in any Synchronous mode and can be
programmed to check data integrity in various
modes. The Z-SCC also has facilities for
modem controls in both channels. In applications where these controls are not needed,
the modem controls can be used for
general-purpose I/O.
The Z-Bus daisy-chain interrupt hierarchy
is also supported-as is standard for Zilog
peripheral components.
The Z8030 Z-SCC is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.
Pin
Description
The following section describes the pin
functions of the Z-SCC. Figures I and 2 detail
the respective pin functions and pin
assignments.
lEI. Interrupt Enab.Ie In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
ADo-AD7' Address/Data Bus (bidirectional,
active High, 3-state). These multiplexed lines
carry register addresses to the Z-SCC as well
as data or control information to and from
the Z-SCC.
AS. Address Strobe (input, active Low).
Addresses on ADo-AD7 are latched by the rising edge of this signal.
CSo. Chip Select 0 (input, active Low). This
signal is latched concurrently with the
addresses on ADo-AD7 and must be active for
the intended bus transaction to occur.
CSI. Chip Select 1 (input, active High). This
second select signal must also be active before
the intended bus transaction can occur. CSt
must remain active throughout the transaction.
CTSA. CTSB. Clear to Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables their
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The Z-SCC detects pulses on these inputs and
can interrupt the CPU on both logic level
transitions.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-tngger buffered to accommodate slow
rise-time signals. The Z-SCC detects pulses on
these pins and can interrupt the CPU on both
logic level transitions.
DS. Data Strobe (input, active Low). This
SIgnal provides timing for the transfer of data
into and out of the Z-SCC. If AS and DS coincide, this is interpreted as a reset.
DTR/REQA. DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
150
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI is High and the
CPU is not servicing a Z-SCC interrupt or the
Z-SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). lEO is connected to
the next lower priority device's IEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
Z-SCC requests an interrupt.
IN TACK. Interrupt Acknowledge (input, active
Low). This signal indICates an active Interrupt
Acknowledge cycle. During this cycle, the
Z-SCC interrupt daisy chain settles. When DS
becomes active, the Z-SCC places an interrupt
vector on the data bus (if lEI is High).
!NTACK is latched by the riSing edge of AS.
PCLK. Clock (input). This is the master Z-SCC
clock used to synchronize internal signals.
PCLK is not required to have any phase re"lationship with the master system clock, although
the frequency of this clock must be at least
90% of the CPU clock frequency for a Z8000.
PCLK is a TTL level signal.
RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
, RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, achve Low). These pins can be programmed in 'several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock of the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be I, 16,32, or 64 times the
data rate in Asynchronous modes.
RTSA. RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bIt in Write Register 5 (Figure II) is set, the
Pin
Description
(Continued)
RTS signal goes Low. When the RTS bit is
reset m the Asynchronous mode and Auto
Enable is on, the signal goes HIgh after the
transmitter is empty. In Synchronous mode or
m Asynchronous mode with Auto Enable off,
the RTS pin stnctly follows the state of the RTS
bIt. Both pins can be used as general-purpose
outputs.
(Monosync and BIsync) wIth the crystal
oscillator not selected, these pins act as outputs and are active only durmg the part of the
receIve clock cycle in which synchronous
characters are recogmzed. The synchronous
condlhon is not latched, so these outputs are
active each hme a synchronization pattern is
recognized (regardless of character boundaries). In SDLC mode, these pms act as outputs and are valid on rec81pt of a flag.
R/W. Read/Write (input). ThIS SIgnal speCIfies
whether the operation to be performed is a
read or a write.
TxDA, TxDB. Transmit Data (outputs, active
High). These output SIgnals transmit senal data
at standard TTL levels.
SYNCA, SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either
as inputs, outputs, or part of the crystal
oscillator circuit.
In the Asynchronous Receive mode (crystal
osctllator option not selected), these pms are
inputs similar to CTS and DCD. In this mode,
translhons on these Imes affect the state of the
Synchronous/Hunt status bits m Read RegIster
o (Figure 10) but have no other funchon.
In External Synchronization mode with the
crystal oscIllator not selected, these lines also
act as inputs. In this mode, SYNC must be
driven Low two receive clock cycles after
the last bit in the synchronous character IS
received. Character assembly begins on the
rismg edge of the reC81ve clock Immediately
precedmg the activahon of SYNC.
In the Internal Synchronizahon mode
Functional
Description
---
---
TRxCA, TRxCB. TransmIt/Receive Clocks
(inputs or outputs, achve Low). These pins can
be programmed in several dIfferent modes of
operahon. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the output of the DIgital Phase-Locked
Loop, the crystal oscIllator, the baud rate
generator, or the transmIt clock in the output
mode.
W/REQA, W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven HIgh or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait Imes to
synchronize the CPU to the Z-SCC data rate.
The reset state is Wait.
The funchonal capabilities of the Z-SCC
can be described from two dIfferent points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communlcahons protocols;
as a Z8000 Family peripheral, it mteracts
with the Z8000 CPU and other peripheral
circuits and IS part of the Z-Bus interrupt
structure.
following description briefly detail these
protocols.
Asynchronous Modes. Transmission and
reception can be accompltshed independently
on each channel with five to eight bits per
character, plus ophonal even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bIts per character and can
provide a break output at any hme. The
receiver break-detechon logIC mterrupts the
CPU both at the start and at the end of a
received break. Reception IS protected from
spikes by a transient spike-rejechon
mechamsm that checks the signal one-half a
Data Communkations Capabilities. The
Z-SCC provides two independent full-duplex
channels programmable for use in any common Asynchronous or Synchronous datacommunication protocol. Figure 3 and the
PARITY
STt !r
"'MA:':R:::'K,"'NG=LlN"'E:-----.,IIr-DA-TA--rI"I"':1:1=DA=T=A=1:1"'11 DATA II' <'MARKING LINE
ASYNCHRONOUS
DATA
SYNC
::
::
::
1
DATA
CRel
CRC2
DATA
CRel
CRez
DATA
CRel
CRez
CRel
CRC2
MONQSVNC
SYNC
SYNC
DATA
SIGNAL
I
+
DATA
-I
BISYNC
EXTERNAL SYNC
FLAG
I
ADDRESS
I
INFO~M:TION
FLAG
SDLCIHDLCIX.25
Figure 3. Some Z-SCC Protocols
2042·108
lSI
.
N
fIJ
n
n
Functional
Description
(Continued)
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure I). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
.
The Z-SCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of I, 1/16, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
transmission. This allows for high speed
transmissions under DMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in Synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous
characters, regardless of the programmed
character length.
The Z-SCC supports Synchronous bitoriented protocols, such as SDLC and HDLC,
by performing automatic flag sending, zero insertion, and CRC generation. A special command can be used to abort a frame in transmission. At the end of a message, the Z-SCC
automatically transmits the CRC and trailing
flag when the transmitter underruns. The
transmitter may also be programmed to send
an idle line consisting of continuous flag
characters or a steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The Z-SCC may also be
programmed to send an abort itself in case of
an underrun, relieVing the CPU of this task.
One to eight bits per character can be sent,
allowing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be
programmed to search for frames addressed by
a single byte (or four bits within a byte) of a
user-selected address or to a global broadcast
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (endof-frame) can be selected. The receiver
automatically deletes all as inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SDLC
mode, the Z-SCC must be programmed to use
the SDLC CRC polynomial, but the generator
and checker may be preset to all Is or all as.
Synchronous Modes. The Z-SCC supports both
byte-oriented and bit-oriented synchronous
communication. Synchronous byte-oriented
protocols can be handled in several modes,
allowing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync),
any 12-bit synchronization pattern (Bisync), or
with an external synchronization signal.
Leading synchronous characters can be
removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the
Z-SCC by overlapping the larger pattern
across multiple incoming synchronous
characters as shown in Figure 4.
CRC checking for Synchronous byteoriented modes is delayed by one character
time so that the CPU may disable CRC checking on speCific characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-16 (X 16 + Xl5 + X2 + I) and
CCITT (X16 + Xl2 + X5 + I) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all as. The Z-SCC also
provides a feature that automatically transmits
CRC data when no other data is available for
5 BITS
~
DATA
DATA
DATA
DATA
Figure 4. Detecting 5- or 7-Bit Synchronous Character.
152
2042-109
Functional
Description
(Continued)
The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any
Ix mode. The parity options available in Asynchronous modes are available in Synchronous
modes.
The Z-SCC can be conveniently used under
DMA control to provide high-speed reception
or transmission. In reception, for example, the
Z-SCC can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The Z-SCC then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received. The CPU may also enable the
DMA first and have the Z-SCC interrupt only
on end-of-frame. This procedure allows all
data to be transferred via the DMA.
SDLe Loop Mode. The Z-SCC supports SDLC
Loop mode in addition to normal SDLC. In an
SDLC Loop, there is a primary controller
station that manages the message traffic flow
on the loop and any number of secondary
stations. In SDLC Loop mode, the Z-SCC performs the functions of a secondary station
while a Z-SCC operating in regular SDLC
mode can act as a controller (Figure 5).
A secondary station in an SDLC Loop is
always listening to the messages being sent
around the loop, and in fact must pass these
messages to the rest of the loop by retransmitting them with a one-bit-time delay. The
secondary stahon can place its own message
on the loop only at specific times. The controller signals that secondary stations may
transmit messages by sending a special
character, called an EOP (End Of Poll),
around the loop. The EOP character is the bit
pattern 11111110. Because of zero insertion
during messages, this bit pattern is unique and
easily recogmzed.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0
before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop
and terminates the message with an EOP. Any
secondary stations further down the loop with
messages to transmit can then append their
messages to the message of the first secondary
station by the same process. Any secondary
stations without messages to send merely echo
the incoming messages and are prohibited
from placing messages on the loop (except
upon recognizing an EOP).
SDLC Loop mode is a programmable option
in the Z-SCC. NRZ, NRZI, and FM coding may
all be used in SDLC Loop mode.
Baud Rate Generator. Each channel in the
Z-SCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
hme constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded mto the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The following formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
baud rate =
2 (bme constant + 2) X (BR clock penod)
Digital Phase-Locked Loop. The Z-SCC contains a Digital Phase-Locked Loop (DPLL) to
recover clock information from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this
clock, along with the data stream, to construct
a clock for the data. This clock may then be
used as the Z-SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
Figure S. An SDLe Loop
2016-001
153
Functional
Description
(Continued)
incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the Z-SCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding The Z-SCC may be programmed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encoding, a 1 is represented by a High level
and a 0 IS represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a 0 is represented by a change in
level. In FMl (more properly, bi-phase mark)
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bl-phase space),
a transition occurs at the beginning of every
bit cell. A a is represented by an additional
transition at the center of the bit cell, and a 1
IS represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the Z-SCC can be used to
decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to 1,
the bit is a O. If the transition is 1 to 0 the
bit is a 1.
Auto Echo and Local Loopback. The Z-SCC
is capable of automatically echOing everything
it receives. This feature is useful mainly in
Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto
Echo mode, TxD is RxD. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The Z-SCC is also capable of Local Loopback. In this mode TxD is RxD, just as in Auto
Echo mode. However, in Local Loopback
m,ode, the internal transmit data is tied to the
internal receive data and RxD is ignored
(except to be echoed out via TxD). The CTS
and DCD inputs are also ignored as transmit
and receive enables. However, transitions on
these inputs can still cause interrupts. Local
Loopback works in Asynchronous, Synchronous and SDLC modes with NRZ, NRZI or
FM coding of the data stream.
1/0 Interface Capabilities. The Z-SCC offers
the choice of Polling, Interrupt (vectored or
nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the Z-SCC are automatically
updated whenever any function IS performed.
For example, end-of-frame in SDLC mode
sets a bit in one of these status registers. The
idea behind polling is for the CPU to periodically read a status register until the register
contents indicate the need for data to be
transferred. Only one register needs to be
DATA
NRZ
\
NRZI
\
/
/
\
\
FM1
FM
MANCHESTER
Figure 6. Data EDcocllDg Methocla
154
2016-002
Functional
Description
(Continued)
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. The Z-SCC interrupt scheme conforms to the Z-Bus specification. When a
Z-SCC responds to an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt
vector may be placed on the AID bus. This
vector is written in WR2 and may be read in
RR2A or RR2B (Figures 10 and 11).
To speed interrupt response time, the Z-SCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the SIX sources of Interrupts in the
Z-SCC (Transmit, Receive, and ExternaVStatus
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP). Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the Z-Bus
interrupt priority chain (Figure 7). As a Z-Bus
peripheral, the Z-SCC may request an
interrupt only when no higher priority device
is requesting one, e.g., when IEI is High. If
the device i.!!..9:uestion requests an interrupt, it
pulls down INT. The CPU then responds w,ith
INTACK, and the interrupting device places
the vector on the AID bus.
In the Z-SCC, the IP bit signals a need for
interrupt servicing. When an IP bit is I and
the IEI input is High, the INT output is pulled
Low, requesting an interrupt. In the Z-SCC, if
the IE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the Z-SCC and
Z·BUS
PERIPHERAL
lEI ADo·AD7 iNf INYACK lEO
external to the Z-SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the IEO output of the Z-SCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and ExternaVStatus. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of
three ways:
• Interrupt on First Receive Character or
Special Receive Condition.
• Interrupt on All Receive Characters or
Special Receive Condition.
• Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is one of
the following: receiver overrun, framing error
in Asynchronous mode, end-of-frame in SDLC
mode and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receive character available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First Receive Character, an interrupt can occur from Special Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
Z·BUS
PERIPHERAL
Z·BUS
PERIPHERAL
iNT
lEI ADo-AD7 iNi INYACK
lEI ADo-AD7
INYACK lEO
+5V
ADO-::~ _------~+_______
...!__I----------JL-t-J
________
nniCK~-------~
_J_ _ _ _ _ _ _ _~
Figure 7. Z-Bus Interrupt Schedule
2016·003
155
Functional
Description
(Continued)
in the baud rate generator, or by the detection
of a Break (Asynchronous mode), Abort (SDLC
mode) or EOP (SDLC Loop mode) sequence in
the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing
the Z-SCC to interrupt when the Abort or EOP
sequence is detected or terminated. This
feature facilitates the proper termination of the
current message, correct initialization of the
next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature allows
secondary stations to recognize the wishes of
the primary station to regain control of the
loop during a poll sequence.
CPU/DMA Block Transfer. Th,e Z-SCC provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Transfer mode uses the
WAIT/REQUEST output in conjunction with the
Wait/Request bits in WRl. The WAIT/
REQUEST output can be defined under soft,ware control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the Z-SCC REQUEST
output indicates that the Z-SCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the Z-SCC is not
ready to transfer data, thereby requesting that
the CPU extend the I/O cycle. The DTR/
REQUEST line allows full-duplex operation
under DMA control.
Architecture
The Z-SCC internal structure includes two
full-duplex channels, two baud rate
generators, internal control and interrupt
logic, and a bus interface to the Zilog Z-Bus.
Associated with each channel are a number of
read and write registers for mode control and
status information, as well as logic necessary to
interface to modems or other external devices
(Figure 8).
The logic for both channels provides
WAIT/REQUEST
INTERNAL
CONTROL
LOGIC
_
}
MODEM, DMA, OR
OTHER CONTROLS
ADDRESSlAA
DATA~
CPU
WL-__--'
BUS I/O
CONTROL
INTERRUPT
CONTROL
LINES
-}
MODEM, DMA, OR
OTHER CONTROLS
INTERRUPT
CONTROL
LOGIC
} SERIAL DATA
ttt
. . - } CHANNEL CLOCKS
SYNC
WAIT/REQUEST
+SVGNDPCLK
Figure 8. Block Diagram 01 Z-SCC Architecture
156
2016-040
w
2
~>
Co
aa:
S' m
c n
0 ...
m
o n
:i2
CD o..S:::
~Ql
CPU 110
BR GENERATOR
INPUT
BR GENERATOR
OUTPUT
TRANSMIT
CLOCK
R,D
DPLL
•I
OPLL OUTPUT
I
CRe RESULT
~
I
RECEIVE CLOCK
BA GENERATOR OUTPUT
DPLl OUTPUT ---~-o.l.
TRllC---~o.l
CLOCK
MUX
RTxC--r-~o.l
TRANSMIT CLOCK
DPLL CLOCK
BR GENERATOR CLOCK
SYNC
(OSCILLATOR)
(JJ
'-J
Figure 9. Data Path
l:JS-Z
Architecture
(Continued)
Programming
158
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two sync
character (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write-only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pendmg bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRI5 - Write Registers 0 through 15.
RRO-RR3, RRlO, RRI2, RRI3, RRl5 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The Z-SCC contains
only one WR2 and WR9, but they can be
accessed by either channel. All other registers
are paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Fi',l"ure 9 is identical for both
channels. The receiver has three 8-bit buffer
registers in at! FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths (data or CRC)
depending on the selected mode (the character
length in Asynchronous modes also determines
the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
The Z-SCC contains 13 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels. All of the registers
in the Z-SCC are directly addressable. How
the Z-SCC decodes the address placed on the
address/data bus at the beginning of a Read or
Write cycle is controlled by a command issued
in WROB.
bus and a 20-bit Transmit Shift register that
can be loaded either from the synchronous
character registers or from the Transmit Data
register. Dependmg on the operational mode,
outgoing data is routed through one of four
main paths before it is transmitted from the
Transmit Data output (TxD)
Read Register Functions
RRO
Transmit/Receive buffer status and External status
RRI
SpeClal Receive Condlhon status
RR2
Modlhed mterrupt vector (Channel B only)
Unmodlhed mterrupt vector (Channel A only)
Interrupt Pendmg bits (Channel A only)
RR3
RR8
Receive buffer
RRIO
Miscellaneous status
RR12
Lower byte of baud rate generator hme constant
RR13
Upper byte of baud rate generator hme constant
RRI5
External/Status mterrupt mformatlon
Write Register Functions
WRO
CRC lmhahze. lmhalizahon commands for the
vanous modes. shilt nghtlshlft left command
WRI
Transmit/Receive Interrupt and data transfer mode
defInItion
WR2
Interrupt vector (accessed through either channel)
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and
modes
WR5
Transmit parameters and controls
WR6
Sync characters or SDLC address held
WR7
Sync character or SDLC flag
WR8
Transmit buffer
WR9
Master mterrupt control and reset (accessed
through either channel)
WRIO
MIscellaneous transmItter/receiver control bits
WRII
Clock mode control
WRI2
Lower byte of baud ,rate generator hme constant
WRI3
Upper byte of baud rate generator hme constant
WRI4
Miscellaneous control bits
WR15
External/Status mterrupt control
Table 1. Read and Write Register Functions
The system program first issues a series of
commands to initialize the basic mode of
operation. This is followed by other commands
to qualify conditions within the selected mode.
For example, the Asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first.
Then the Interrupt mode would be set, and
finally, receiver or transmitter enable.
Programming Read Registers. The Z-SCC contains eight
(Continued)
read registers (actually nine, counting the
receive buffer [RR8]) in each channel. Four of
these may be read to obtain status information
(RRO, RRl, RRI0, and RRI5). Two registers
(RRI2 and RRI3) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the
Read Register 0
Interrupt Pending OP) bits (Channel A).
Figure 10 shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropnate error bits can be read from a single
register (RR 1).
Read Register 10
ID, ID, ID, ID,I D, ID, ID, IDo I
~ R,CHARACTERAVAILABLE
L
lli!~~
ZEROCQUNT
h BUFFER EMPTY
DCD
.
SYNC/HUNT
CTS
toil
Tx UNDERRUNIEOM
fI.I
n
BREAK/ABORT
n
Read Register 1
lli!~~
Read Register 12
L~ALLSENT
lli!~
RESIDUE CODe 2
RESIDUE CODE 1
RESIDUE CODE 0
PARITY ERROR
Rx OVERRUN ERROR
CRe/FRAMING ERROR
LOWER BYTE OF
TIME CONSTANT
TC,
END OF FRAME (SOLe)
Read Register 2
Read Register 13
UPPER BYTE OF
INTERRUPT VECTOR'
TIME CONSTANT
'MODIFIED IN B CHANNEL
Read Register 3
lli!~~
Read Register 15
'~ CHANNEL B EXT/STAT IP·
L
CHANNEL B Tx IP'
CHANNEL B Rx IP'
CHANNEL A EXT/STAT lP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'
o
o
~ ~::~ECOUNTIE
~
lli!~
,
SYNC/HUNT IE
eTS IE
Tx UNDERRUN/EOM IE
BREAK/ABORT IE
'ALWAYS 0 IN B CHANNEL
Figure 10. Read Register Bit Functions
2016·005
159
Programming Write Registers. The Z-SCC contains 13 write
(Continued)
registers (14 countmg WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
Write Register 0
WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits. Figure
11 shows the format of each write register.
Write Register 3
1
10,!0.1 0, I0,1 0, I0, I0, IDo I
L L!=R'ENABLE
0
0
NULL CODE
o
1
NULL CODE
1
0
SELECT SHIFT lEFT MODE'
1
1
:ELECT SHIFT RIGHT MODE'
~~
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SOle)
Rx CRe ENABLE
ENTER HUNT MODE
AUTO ENABLES
o
0
NUll CODE
o
0
1
NULL CODE
1
0
RESET EXT/STATUS INTERRUPTS
1
1
SEND ABORT
1
0
0
ENABLE INT ON NEXT Ax CHARACTER
1
0
1
RESET Tx INT PENDING
0
0
0
0
0
0
Rx 5 BITS/CHARACTER
o
1
Rx 7 BITS/CHARACTER
1
0
Rx 6 BITS/CHARACTER
1
1
Rx 8 BITS/CHARACTER
Write Register 4
1
1
0
ERROR RESET
1
1
1
RESET HIGHEST IUS
0
NUll CODE
o
1
RESET RI'; CRe CHECKER
1
0
RESET Tx CRe GENERATOR
1
1
RESET Tx UNDERRUNIEOM LATCH
~
• B CHANNEL ONLY
I L PARITY ENABLE
L
PARITY EVEN/ODD
o
o
1
1 STOP BIT/CHARACTER
1
0
1'h STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
0
SYNC MODES ENABLE
Write Register 1
10, I0.1 0, I0,1 0, I0, I0, IDol
=
~L
a
0
o
0
8 BIT SYNC CHARACTER
o
1
16 BIT SYNC CHARACTER
o
SOLC MODE (01111110 FLAG)
1
EXTERNAL SYNC MODE
EXT INT ENABLE
1
Tx INT ENABLE
o
PARITY IS SPECIAL CONDITION
Rx INT DISABLE
o
1
1
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
t
Ax INT ON FIRST CHARACTER OR SPECIAL CONDITION
0
Xl CLOCK MODE
o
1
X16 CLOCK MODE
1
0
X32 CLOCK MODE
1
1
X64 CLOCK MODE
Rx INT ON SPECIAL CONDITION ONLY
" - - - - - - WAITIDMA REQUEST ON RECEIVE/TRANSMIT
Write Register 5
' - - - - - - - WAITIOMA REQUEST FUNCTION
1~1~1~1~1~1~:~i~1
' - - - - - - - - WAITIDMA REQUEST ENABLE
I ~ :~:RC
L
~
Write Register 2
ll!;,
ENABLE
SDLC/CRC 16
Tx ENABLE
SEND BREAK
INTERRUPT VECTOR
o
o
0
Tx 5 BITS (OR LESS)/CHARACTER
1
Tx 7 BITS/CHARACTER
1
0
Tx 6 BITS/CHARACTER
1
1
Tx 8 BITS/CHARACTER
' - - - - - - - - DTR
v,
Write Register 6
I~I~I~I~I~I~I~I~I
iFFJ~l~
SYNC7
SYNC,
SYNC7
SYNC3
ADR7
ADA7
SYNCe
SYNCo
SYNCe
SYNC2
ADRe
ADR6
SYNCs
SYNCs
SYNC5
SYNC,
ADR5
AD As
SYNC4
SYNC4
SYNC4
SYNCo
ADR4
ADA4
SYNC3
SYNCs
SYNC 3
1
ADR3
SYNC2
SYNC2
SYNC2
1
ADR2
SYNC,
SYNC,
SYNC,
1
ADR,
SYNCo
SYNCo
SYNCo
1
ADRo
MONOSYNC,6 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SOLe
SOLe (ADDRESS RANGE)
Figure II. Write Register Bit Functions
160
2016·006
Programming
Write Register 7
(Contmued)
I~I~I~I~I~I~I~I~I
~Jl~
SYNC7
SYNCs
SYNC15
SYNCt!
SYNCS
SYNC,
SYNC14
SYNC,o
1
o
SYNCs
SYNC 3
SYNC I3
SYNCg
1
SYNC4
SYNC2
SYNC,2
SYNCe
1
SYNC3
SYNC!
SYNCll
SYNC7
1
SY NC2
SYNCo
SYNCtO
SYNCs
1
SYNCj
,
SYNCo
SYNCg
SYNCs
1
SYNCs
SYNC4
o
MONOSYNC,8 BITS
MONOSYNC,6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SOle
Write Register 12
Write Register 9
LOWER BYTE OF
TIME CONSTANT
o
0
NO RESET
o
1
CHANNEL RESET B
1
0
CHANNEL RESET A
1
1
FORCE HARDWARE RESET
Write Register 13
Write Register 10
10, I0, I0, I0.1 0, I0, I0, I0,1
I ~ 6 BITJilBfT SYNC
L..=
~
LOOP MODE
ABORT/FLAG ON UNDERRUN
MARK/FLAG IDLE
GO ACTIVE ON POLL
o a
NRZ
o
1
NRZI
1
0
FMl (TRANSITION'" 1)
1
1
FMO (TRANSITION = 0)
Write Register 14
' - - - - - - - - CRC PRESET 110
L
~lS
L BR GENERATOR ENABLE
Write Register 11
1
1~1~1~1~1~I~i~I~1
a
AUTO ECHO
LOCAL LOQPBACK
0
0
fl\,c OUT
o
1
TRXC
1
0
lRiC OUT = BR GENERATOR OUTPUT
0
1
1
TRxC OUT"" DPLL OUTPUT
0
TRxC
SR GENERATOR SOURCE
DfR/REQUEST FUNCTION
OUT
0
XTAL OUTPUT
= TRANSMIT CLOCK
0
0
0
,
,
oli
a
TRANSMIT CLOCK"" RTxC PIN
a
1
TRANSMIT CLOCK '" TRxC PIN
1
a
TRANSMIT CLOCK"" BR GENERATOR OUTPUT
1
1
TRANSMIT CLOCK
:=
0
,
1
0
,
,
, ,
0
0
0
,
1
,
0
0
,
NULL COMMAND
ENTER SEARCH MODE
RESET MISSING CLOCK
DISABLE DPLL
SET SOURCE"" BR GENERATOR
SET SOURCE "" RTxC
SET FM MODE
SET NRZI MODE
DPLL OUTPUT
Write Register 15
a
a
RECEIVE CLOCK
a
1
RECEIVE CLOCK""
1
a
RECEIVE CLOCK"" BR GENERATOR OUTPUT
1
1
RECEIVE CLOCK = DPLL OUTPUT
:=
RTxC PIN
lAiC
PIN
' - - - - - - - - - - - RTxC XTAUNOXTAL
Figure 11. Write Register Bit Functions (Conhnued)
2016·006
161
Timing
The Z-SCC generates internal control signals
from AS and DS that are related to PCLK.
Since PCLK has no phase relationship with
AS and DS, the circuitry generating these
internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the Z-SCC. The recovery
time required for proper operation is specified
from the rising edge of DS in the first transaction involving the Z-SCC to the falling edge of
DS in the second transaction involving the
Z-SCC. This time must be at least 6 PCLK
cycles plus 200 ns.
Read Cycle Timing. Figure 12 illustrates read
cycle timing. The address on ADa-AD7 and
the state of CSa and INTACK are latched by
the rising edge of AS. RlW must be High to
indicate a Read cycle. CSj must also be High
for the Read cycle to occur. The data bus
drivers in the Z-SCC are then enabled while
DS is Low.
I
\
7
\
)
( ____---JX
X~~=~..Jf-----<""
ADO-AD7 _ _ _..J
ADDRESS
R/W
------'
cs,
_ _ _ _...J/
DATA VALID
}--
/
c
\'--____---'rFigure 12. Read Cycle Timing
Write Cycle Timing. Figure 13 illustrates
Write cycle timing. The address on ADa-AD7
and the state of CSa and INTACK are latched
by the rising edge of AS. R/W must be Low to
indicate a Write cycle. CSj must be High for
the Write cycle to occur. DS Low strobes the
data into the Z-SCC.
I
\~----------
--IX
ADO-A D7 _ _
RJW
~,
ADDRESS
O . . . .______
C
\
C
/
c
DA_T_A_ _ _ _ _ _
------'
\'--____----..Jr-
Figure 13. Write Cycle Timing
Interrupt Acknowledge Cycle Timing.
Figure 14 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD7 and
the state of CSa and INTACK are latched by
162
the rising edge of AS. However, If INTACK is
Low, the address and CS o are ignored. The
state of the R/W and CSj are also ignored for
the duration of the Interrupt Acknowledge
2016-007,008
Timing
(Continued)
cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
IEI/IEO daisy chains settle. If there is an interrupt pending in the Z-SCC and IEI is High
when DS falls, the Acknowledge cycle was
AS
~
Cso
intended for the Z-SCC. In this case, the
Z-SCC may be programmed to respond to DS
Low by placing its interrupt vector on
ADo-AD7. It then sets the appropriate
Interrupt- Under-Service latch internally.
r------"
~
X
X
ADO-AD7 _ _ _.J
(IGNORED)
~:
(IGNORED)
>).----II_~---
~-~----------------------
...
.J}--
c=x'__V_EC_T_OR
__
Figure 14. Interrupt Acknowledge Cycle Timing
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherWIse noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those hsted under Absolute MaxImum Ratings may cause permanent damage to the device.
Thls 15 a stress ratmg only; operation of the deVIce at any
condItion above those mdicated In the operahonal sectIons
of these specIficahons IS not Imphed. Exposure to absolute
maXImum ratmg conditions for extended penods may affect
devIce rehablhty.
• +4.75 V
:$
Vee
:$
+5.25 V
• GND = 0 V
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+5V
21K
+5V
FROM OUTPUT
UNDER TEST
~
I
Figure 15. Standard Test Load
DC
Characteristics
Capacitance
Symbol
VIH
VIL
VOH
VOL
IlL
IOL
Icc
Vee =
Cvo
f
2016-009
8085-006, 001
=
SOPF
Figure 16. Open-Drain Test Load
Parameter
Min
Max
Unit
Input HIgh Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
2.0
-0.3
2.4
Vee+ 0.3
0.8
V
V
V
V
0.4
±1O.0
± 10.0
250
p.A
p.A
mA
Condition
IOH=
IOL=
0.4 $
0.4 $
-250 j.tA
+2.0 rnA
VIN $ + 2.4V
Your $ +2.4V
5 V ± 5% unless otherwlse speCIfied, over speCliJed temperature range.
Symbol
CIN
Cour
22K
Parameter
Input Capacitance
Output Capacitance
BidIrectional CapacItance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
Unmeasured Pins
Returned to Ground
1 MHz, over speclhed temperature range
163
Read and
Write
Timing
CSo
~
.~
X
(i)--j- ~
X
Ri\y
READ
~
-
,
-.
®~
~W
~
R/W
WRITE
L
f--. f-®
ADo-AD7
WRITE
)(
@-
ADo-AD7
READ
~
--:--®-
-
.....
-------x .....
(IV
l(
CDf--
®I-
~
~
"
X
K
~- ®
I-
--@-o-
"
~
~
-E
)!
--- @ ~
~
®
~
\,
W/REQ
WAIT
f-®--f
W/REQ
~
REQUEST
DTR/REQ
----®-------l
REQUEST
"
Number
Symbol
Min(ns) Max(ns)
Parameters
Notes·
I
TwAS
AS Low WIdth
70
2
TdDS(AS)
DS 1 to AS j Delay
50
3
TsCSO(AS)
CSo to AS 1 Setup Time
0
I
4
ThCSO(AS)
CSo to AS 1 Hold Time
60
I
5--TsCSl(DS)--CS 1 to DS j Setup T l m e - - - - - - - - - - - I O O - - - - - - 16
ThCSl(DS)
CS 1 to DS 1 Hold TIme
60
I
7
TsIA(AS)
INTACK to AS 1 Setup Time
0
8
ThIA(AS)
INTACK to AS 1 Hold TIme
250
9
TsRWR(DS)
R/W (Read) to DS j Setup TIme
100
10--ThRW(DS)--RlWtoDS 1 Hold TIme
60------II
TsRWW(DS)
RIW (Write) to DS j Setup Time
0
12
TdAS(DS)
AS 1 to DS j Delay
60
13
TwDSI
DS Low Width
390
14
TrC
.Valld Access Recovery Time
6TcPC
2
+200
15--TsA(AS)---Address to AS 1 Setup T i m e - - - - - - - - - - I O - - - - - - I 16
ThA(AS)
Address to AS 1 Hold Time
50
1
17
TsDW(DS)
Wnte Data to DS j Setup Time
30
18
ThDW(DS)
Wnte Data to DS 1 Hold Time
0
19
TdDS(DA)
DS j to Data Achve Delay
0
20-- TdDSr(DR)-- DS 1 to Read Data Not Valld Delay
0-------21
TdDSf(DR)
DS j to Read Data Valid Delay
255
AS 1 to Read Data Valid Delay
22
TdAS(DR)
480
NOTES:
1 Parameter does not apply to Interrupt Acknowledge
transactions.
164
2. Parameter applIes only between transactIons Involvmg the
z-see.
2016-010
y
Interrupt
Acknowledge
Timing
------,
ADO-AD7 ----------------------~----------------_rr__"[
lEI
lEO
Reset
Timing
Cycle
Timing
PCLK
Number
Symbol
Parameters
Min(ns) Max(ns)
Notes·
3
23
TdDS(DRz)
DS t to Read Data Float Delay
70
24
TdA(DR)
Address ReqUlred ValId to Read Data ValId Delay
590
25
TdDS(W)
DS I to Walt Valid Delay
240
4
26
TdDSf(REQ)
DS I to W/REQ Not ValId Delay
240
27-- TdDSr(REQ)--DS I to DTR/REQ Not Valid D e l a y - - - - - - - - - 5 T c P C - - - +300
28
TdAS(INT)
AS 1 to INT ValId Delay
500
4
29
TdAS(DSA)
AS 1 to DS I (Acknowledge) Delay
5
30
TwDSA
DS (Acknowledge) Low W,dth
475
31
TdDSA(DR)
DS I (Acknowledge) to Read Data ValId Delay
360
32--TsIEI(DSA)--IEI to DS I (Acknowledge) Setup T , m e - - - - - - 1 2 0 - - - - - - - 33
ThIEI(DSA)
lEI io DS t (Acknowledge) Hold T,me
0
34
TdIEI(IEO)
lEI to lEO Delay
120
35
TdAS(lEO)
AS t to lEO Delay
250
6
4
36
TdDSA(INT)
500
DS I (Acknowledge) to INT Inachve Delay
37--TdDS(ASQ)--DS I to AS I Delay for No R e s e t - - - - - - - - 3 0 - - - - - - - 38
TdASQ(DS)
AS t to DSI Delay for No Reset
30
7
39
TwRES
AS and DS Comcldent Low for Reset
250
40
TwPCI
PCLK Low Width
105
2000
41
TwPCh
PCLK Hlgh Width
105
2000
42--TcPC
PCLK Cycle T,me
250--4000----43
TrPC
PCLK Rise Time
20
44
TlPC
PCLK Fall T,me
20
NOTES:
3. Float delay
IS
dehned as the hme requIred for a ± a 5 V
change m the output With a maximum de load and minimum
de
load.
4 Open-dram output, measured WIth open-dram test load
5 Parameter IS system dependent For any Z-SCC In the daISY
cham, TdAS(DSA) must be greater than the sum of TdAS(IEO)
for the highest priorIty deVIce In the daiSY cham, TsIEI(DSA)
2016-011, 012, 013
for the Z-SCC, and TdIElfOEO) for each deVice separatmg
them In the daiSY cham
6. Parameter apphes only to a Z-SCC pullmg INT Low at the
begmnmg of the Interrupt Acknowledge transachon
7 Internal clrcUltry allows for the reset prOVided by the Z8 to be
recognized as a reset by the Z-SCC.
*Tlmmgs are prehmmary and subject to change
165
General
Timing
Number
Symbol
Min(ns) Max(ns)
Parameters
I
TdPC(REQ)
PCLK I to W/REQ Valid Delay
250
2
TdPC(W)
PCLK I to Walt Inactive Delay
350
3
TsRXC(PC)
RxC I to PCLK I Setup Time
4
TsRXD(RXCr)
RxD to RxC I Setup Time (XI Mode)
5 - - ThRXD(RXCr)-RxD to RxC I Hold Time (XI Mode)
6
TsRXD(RXCf)
RxD to RxC I Setup Time (XI Mode)
7
ThRXD(RXCf)
RxD to RxC I Hold Time (XI Mode)
8
TsSY(RXC)
SYNC to RxC I Setup Time
9
ThSY(RXC)
SYNC to RxC I Hold Time
50
1,4
0
I
150 - - - - - - 1 0
1,5
150
1,5
-200
10-- TsTXC(PC)--TxC I to PCLK 1 Setup Time
3TcPC
+200
0- - - - - 2 , 4 -
II
TdTXCf(TXD)
TxC I to TxD Delay (XI Mode)
300
2
12
TdTXCr(TXD)
TxC 1 to TxD Delay (XI Mode)
300
2,5
13
TdTXD(TRX)
TxD to TRxC Delay (Send Clock Echo)
1000
3
TwRTXh
RTxC High Width
14
15-- TwRTXI--- RTxC Low Width
180
TcRTX
RTxC Cycle Time
400
17
TcRTXX
Crystal Oscillator Period
250
18
TwTRXh
TRxC High Width
180
16
19
TwTRXI
20--TcTRX
180
TRxC Low Width
180
TRxC Cycle Time
400
21
TwEXT
DCD or CTS Pulse Width
200
22
TwSY
SYNC Pulse Width
200
NOTES:
1. RxC IS RTxC or TRxC, whichever IS supplymg the receIve
clock.
2. TxC IS TRxC or RTxC, whichever IS supplYing the transmlt
clock.
3. Both RTxC and SYNC have 30 pF capacItors to the ground
connected to them.
166
Notes"
4. Parameter applies only If the data rate IS one-fourth the
PCLK rate. In all other cases, no phase relationship between
RxC and PCLK or TxC and PCLK IS requIred.
5. Parameter appiles only to FM encodmg/decodmg.
*Tlmmgs are prelimmary and subject to change
General
Timing
(Continued)
PCLK
WIRE:Q
REQUEST
-==------4--1
WAIT
WIREQ
_______________
-,
~~7:::j_----------------_===---------
.
N
fI1
n
n
2016-014
167
System
Timing
iITxc,
TRxe
RECEIVE
WIRED
REQUEST
W/REQ
WAIT
SYNC
OUTPUT
RTxC, TRxe
TRANSMIT
W/REQ
REQUEST
W/REQ
WAIT
DTR/REQ
REQUEST
CTS,DCD ____________________~~~-----------------------------------------SYNC--------------------~----~~~,------------------------------------INPUT ____________________~-----A~,--__:.,....----.,._-------------------------
~
\
I - - - - - - { I O ) - - - -___] " " - - - - - - - - - - - - - - - - - - - - - - - - -
Number
Min
Max
Units
Notes·
RxC 1 to W/REQ Valid Delay
8
12
TcPC
2
RxC 1 to Walt Inachve Delay
8
4
12
TcPC
1,2
7
TcPC
2
Symbol
Parameter
I
TdRXC (REQ)
2
TdRXC(W)
3
TdRXqSY)
RxC 1 to SYNC Valid Delay
4
TdRXqINT)
RxC 1 to INT Valid Delay
6
TdTXqW)
TxC I to Wait Inachve Delay
5
8
TcPC
7
TdTXC(DRQ)
TxC I to DTR/REQ Valid Delay
4
7
TcPC
3
8
TdTXC(INT)
TxC I to !NT Valid Delay
4
+2
6
+3
TcPC
AS1
1,3
9
TdSY(!NT)
SYNC Transihon to INT Valid Delay
2
3
AS1
TdEXT(INT)
DCD or CTS Transition to INT Valid Delay
2
3
AS1
8
12
TcPC
1,2
+2
+3
AS1
5--TdTXC(REQ)-TxC I to W/REQ Vahd D e l a y - - - - - - 5 - - - 8 - - T c P C - - 3 -
10
NOTES.
1 Open-dram output, measured wIth open-dram test load.
2. RxC IS RTxC or TRxC, whIchever IS supplYing the receIve
clock.
168
3. TxC
IS
TRxC or RTxC, whIchever
IS
1,3
supplymg the transmit
clock.
*Tlmmgs are prelimmary and subject to change.
2016·015
Ordering
Information
Product
Number
Speed
Z8030A
CE
6.0 MHz
Z-SCC (40-pin)
Z8030A
CS
DE
6.0 MHz
Same as above
6.0 MHz
Same as above
6.0 MHz
Z8030A
DS
PE
6.0 MHz
Same as above
Same as above
Z8030A
PS
6.0 MHz
Same as above
Speed
Z8030
CE
4.0 MHz
Z-SCC (40-pin)
Z8030
CS
4.0 MHz
Same as above
Z8030
DE
4.0 MHz
Same as above
Z8030A
Z8030
DS
4.0 MHz
Same as above
Z8030A
Z8030
PE
4.0 MHz
Same as above
Z8030
PS
4.0 MHz
Same as above
NOTES. C:::: Ceramic, D
OO·2016-A
Package/
Temp
Product
Number
Package/
Temp
=
Description
Cercilp, P = PlastJc; E :::: _40°C to +85°C, S =
aoe to
Description
+70°C.
169
Z8036 Z8000™ Z-CIO
Counter/Timer and
Parallel I/O Unit
~
Zilog
Product
Specification
March 1981
Features
General
Description
• Two independent 8-bit, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode), "pulse
catchers," and programmable opendrain outputs.
• Flexible pattern-recognition logiC, programmable as a 16-vector interrupt controller.
• Four handshake modes, induding 3-Wire
(like the IEEE-488).
• Three independent 16-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave),
programmable as retriggerable or
nonretriggerable.
• REQUEST/WAIT signal for high-speed data
transfer.
• Easy to use since all registers are read/write
and directly addressable.
The Z8036 Z-CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most
counter/timer and parallel I/O needs
encountered in system designs. This versatile
device contains three I/O ports and three
counter/timers. Many programmable options
tailor Its configuration to specific applications.
The use of the device is simplified by making
all internal registers (command, status, and
data) readable and (except for status bits)
writable. In addition, each register is given its
own unique address so that it can be
accessed directly-no special sequential
operations are required. The Z-CIO is directly
Z-Bus compatible.
ADDRESSIDATA
BUS
j~ ~ ~
BUS TIMING {
AND RESET
CONTROL {
PA 4 .........
. . - . ADa
PAa .........
........ AD2
PA,
PA,
........ ADD
PAo ..........
~
os
=::;:
ADs
AD,
PORT A
PC, ___
}
PC
_
2
pC I ...-...
PORT C
pee . . - . .
~CSI
INTERRUPT
{ -. :ACK
- . . lEI
lEO
ADo
os
GND
Z8038
Z·CIO
AD,
RNi
.....-.. ADt
-.
---.
AD,
PA,
_)
PAs ..........
PAs ..........
PBs
PB, ......
...... )
PB5 .........
PB4 ........
PBa ........
PB 2 ........
PSI
---..
PS e
..........
PBo
Plio
PB,
PA,
PB,
PA~
PB,
PA,
PB,
PA,
PBs
PAs
PB,
Plio
PB,
PORT B
PCLK
lEI
PA,
INTACK
iNf
lEO
+5V
PCo
PC,
PC,
PC,
PCLK +5V GND
Figure I. Pin Functions
2014-0035. 0036
Figure 2. Pin Assignments
171
Pin
Description
ADo-AD7. Z-Bus Address/Data lines
(bidlrechonal/3-state). these mulhplexed
Address/Data lines are used for transfers
between the CPU and Z-CIO.
AS*. Address Strobe (input, active Low).
Addresses, INTACK, and CSo are sampled
whIle AS IS Low.
CSo and CSI. Chlp Select 0 (mput, achve
Low) and Chlp Select 1 (mput, active HIgh).
CSo and CSI must be Low and HIgh, respechvely, in order to select a deVIce. CSo is
latched by AS.
DS*. Data Strobe (mput, active Low). DS provides timing for the transfer of data mto or out
of the Z-CIO.
lEI. Interrupt Enable In (mput, achve High).
lEI is used with IEO to form an interrupt daisy
cham when there IS more than one interruptdriven deVIce. A HIgh IEI indIcates that no
other hIgher priority device has an mterrupt
under servIce or is requesting an mterrupt.
lEO. Interrupt Enable Out (output, active
HIgh). IEO is High only if IEI is HIgh and the
CPU is not servicing an interrupt from the
requesting Z-CIO or is not requesting an interrupt (Interrupt Acknowledge cycle only). IEO
is connected to the next lower Priority deVIce's
lEI input and thus inhIbits interrupts from
lower priority devices. .
Architecture
INT. Interrupt Request (output, open-drain,
active Low). This signal is pulled Low when
the Z-CIO requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates to the Z-CIO that
an Interrupt Acknowledge cycle is m progress.
INT ACK is sampled while AS is Low.
PAo-PA7. Port A 1/0 lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer_ mformation between the Z-CIO's Port
A and external devices.
PBo-PB7. Port B 1/0 lines (bidirectional,
3-state, or open-drain). These 81ght I/O lmes
transfer informahon between the Z-CIO's Port
B and external deVIces. May also be used to
provide external access to Counter/Timers
I and 2.
PCO-PC3. Port C 1/0 lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the Z-CIO's Port C.
PCLK. (input, TTL-compatible). This IS a
peripheral clock that may be, but is not
necessarily, the CPU clock. It IS used with
timers and REQUEST/WAIT logIC. Maximum
input frequency IS 4 MHz.
·When AS and DS are detected Low at the same bme (normally
an lllegal conditiOn), the Z-CIO IS reset
R/W. Read/Write (input). R/W indicates that
the CPU IS reading from (HIgh) or wrltmg to
(Low) the Z-CIO.
The Z8036 Z-CIO Counter/Timer and
Parallel I/O element (FIgure 3) consIsts of a
Z-Bus interface, three I/O ports (two generalpurpose 8-bit ports and one special-purpose
< >
INTERRUPT
CONTROL
lOGIC
INT':RUPT
CONTROL
ADDRESSI
¢=q
CON~ROL >'--__--'
Z BUS
INTERFACE
INPUTS
INTERNAL
PORT
B
CONTROL
LOGIC
~
110
Figure 3. Z·CIO Block Diagram
172
2014·001
Architecture
(Continued)
4-blt port), three 16-bit counter/hmers, an
mterrupt control logIc block, and the mternal
control logIc block. An extensIve number of
programmable options allow the user to tailor
the configuration to best suit the specihc
application.
The two general-purpose 8-blt 1/0 ports
(FIgure 4) are idenhcal, except that Port B can
be specIfied to provIde external access to
CounterlTimers 1 and 2. EIther port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the dIrection
of each bIt mdlvldually programmable. Each
port mcludes pattern-recogmtion logIc, allowmg mterrupt generation when a specIfic pattern is detected. The pattern-recognition logIc
can be programmed so the port functions like
a pnonty-mterrupt controller. Ports A and B
can also be lmked to form a 16-blt I/O port.
To control these capabiltties, both ports contam 12 registers. Three of these regIsters, the
Input, Output, and Buffer regIsters, compnse
the data path registers. Two registers, the
Mode Specihcahon and Handshake Speclhcahon regIsters, are used to dehne the mode of
the port and to specify whIch handshake, if
any, IS to be used. The reference pattern for
the pattern-recognihon logIC IS dehned via
three regIsters: the Pattern Polarity, Pattern
Transition, and Pattern Mask regIsters. The
detaIled characteristics of each bIt path (for
example, the direchon of data flow or whether
a path is mvertmg or nonmvertmg) are programmed using the Data Path Polarity, Data
DirectIOn, and SpeCial I/O Control regIsters.
The primary control and status bits are
grouped m a smgle regIster, the Command
and Status regIster, so that after the port IS imhally configured, only this regIster must be
accessed frequently. To facilttate ImitaltzatlOn,
the port logIC IS deSIgned so that regIsters
assocIated with an unreqUlred capablltty are
Ignored and do not have to be programmed.
TO COUNTER/TIMERS 1 AND 2
(PORT B ONLy)
~
INTERNAL
BUS
INPUT
BUFFERI
INVERTERS
OUTPUT
REGISTER
AND
PULSE
CATCHER
PATTERN
PORT
110
RECOGNITION
LOGIC
OUTPUT
INPUT
BUFFERt
REGISTER
INVERTERS
PORT
CONTROL
LOGIC
TO PORT C
Figure 4. Ports A and B Block Diagram
2014·002
173
Architecture
(Continued)
The function of the special-purpose 4-blt
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lmes can be used as
I/O lines or to provide external access for the
third counter/timer.
Since Port C's funchon IS dehned pnmarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The three counter/timers (Figure 6) are all
idenhcal. Each is compnsed of a l6-bit downcounter, a l6-bit Time Constant register
(whICh holds the value loaded into the downcounter), a 16-bit Current Counter register
(used to read the contents of the downcounter), and two 8-bit registers for control
and status (the Mode Specification and the
Command and Status registers).
The capabilities of the counter/timer are
numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/hmer: counter input, gate mput, trigger mput, and counter/timer output. Three different counter/hmer output duty cycles are
aVallable: pulse, one-shot, or square-wave.
The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
The mterrupt control logic provides standard
Z-Bus interrupt capabihties. There are hve
registers (Master Interrupt Control register,
three Interrupt Vector registers, and the Current Vector register) associated With the mterrupt logic. In addlhon, the ports' Command
and Status registers and the counter/timers'
Command and Status registers include bits
associated with the mterrupt logiC. Each of
these registers contains three bits for interrupt
control and status: Interrupt Pending (IP),
Interrupt Under Service (IUS), and Interrupt
Enable (IE).
TO COUNTERI
TO PORT TO PORT
A
TIMER 3
B
INPUT
BUFfERI
INVERTERS
AND
PULSE
CATCHERS
PORT
110
OUTPUT
BUFFERI
INVERTERS
PORT
CONTROL
LOGIC
)----~NTERNAL
~_____
::::J--, ~
PORT
CONTROL LINES
Figure 5. Pori C Block Diagram
174
Architecture
(Continued)
INTERNAL
BUS
CURRENT
COUNT
REGISTER
(MSB's)
CURRENT
COUNT
R~~~!S;R
I----...J
TO PORT
Figure 6. Counter/Timer Block Diagram
Functional
Description
The following describes the functions
of the ports, pattern-recognition 10glC,
counter/hmers, and interrupt 10glC.
110 Port Operations. Of the Z-CIO's three
I/O ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port Balsa
provides access for Counter/Timers 1 and 2. In
all configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUEST/WAIT line can also be provided
so that Z-CIO transfers can be synchronized
with DMAs or CPUs. Any Port C bits not used
for handshake or REQUEST/WAIT can be used
as input or output bits (indiVidually data direction programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits
remain undisturbed without first reading the
register.
port's Data Direction register speCifies the
direction of data flow for each bit. A I
speCifies an input bit, and a 0 specifies an output bit. If bits are used as 110 bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverhng.
The value returned when reading an input
bit reflects the state of the mput just prior to
the read. AI's catcher can be inserted into the
input data path by programming a 1 to the
corresponding bit position of the port's Special
I/O Control register. When a 1 is detected at
the 1's catcher input, its output is set to a 1
until it is cleared. The l' s catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be speCified as opendrain by writing a 1 to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least sigmficant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with a 1, the state of the corresponding output
bit is not changed.
Bit Port Operations. In bit port operations, the
2014·004
175
Functional
Description
(Continued)
Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The Z-CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When speCified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logiC. Port C provides the
handshake Imes as shown in Table I. Any Port
C Imes not used for handshake can be used as
sImple I/O Imes or as access lines for Counter!
Timer 3.
When Ports A and B are configured as ports
With handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
mterrupt for the first byte is serviced. Normally, the Interrupt Pendmg (IP) bit IS set and
an interrupt is generated when data is shifted
into the Input register (mput port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP IS cleared only by command.
When the Interrupt on Two Bytes (ITB) control
bIt is set to I, mterrupts are generated only
when two bytes of data are avaIlable to be read
or written. This allows a minimum of 16 bIts of
mformahon to be transferred on each mterrup!. With ITB set, the IP is not automatically
cleared until the second byte of data is read or
written.
When the Single Buffer (SB) bit is set to I,
the port acts as If It is only smgle-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a I in the Port Lmk Control (PLC) bi!. In this mode, only Port A's
Handshake SpeCification and Command and
Status registers are used. Port B must be
speCified as a bit port. When linked, only Port
Pori A/B Configuration
Ports A und B:
Blt Ports
A has pattern-match capability. Port B's
pattern-match capabihty must be disabled.
Also, when the ports are linked, Port B's Data
register must be read or written before
Port A's.
When a port is speCIfied as a port with handshake, the type of port it is (mput, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have I's catchers; therefore, those bits in the
Special I/O Control register are Ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the Z-CIO must
be acknowledged by the external device
before the next action can take place. Figure 7
shows hmmg for Interlocked Handshake. An
output port does not indIcate that new data is
available unhl the external deVICe mdicates it
IS ready for the data. SimIlarly, an input port
does not indicate that It is ready for new data
unhl the data source indicates that the preVIOUS byte of the data IS no longer available,
thereby ac~nowledgmg the input port's acceptance of the last byte. ThIS allows the Z-CIO to
interface directly to the port of a Z8 mICrocomputer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-blt deskew hmer can be inserted in the
Data Available (DAV) output for output ports.
As data IS transferred to the Buffer register,
the deskew timer IS triggered. After the
number of PCLK cycles speCified by the
deskew timer time constant plus one, DAV IS
PC3
PC2
PCI
PCO
Blt I/O
Blt I/O
Blt I/O
Blt I/O
Pori A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake) •
RFD or DAV
ACKIN
REQUEST/WAIT
or Blt I/O
Blt I/O
Pori B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)'
REQUEST/WAIT
or Blt I/O
Blt I/O
RFD or DAV
ACKIN
Port A or B: Input Port (3-W,re
Handshake)
RFD (Output)
DAV (Input)
REQUEST/WAIT
or Blt I/O
DAC (Output)
Port A or B: Output Port (3-Wlre
Handshake)
DA V (Output)
DAC (Input)
REQUEST/WAIT
or Blt I/O
RFD (Input)
Port A or B: BIdIrectIonal Port
(Interlocked or Strobed Handshake)
RFD or DAV
ACKIN
REQUEST/WAIT
or Blt I/O
IN/OUT
*Both Ports A and B can be speclhed mput or output WIth Interlocked, Strobed, or Pulsed Handshake at the same hme If neither
uses REQUEST/WAIT
Table 1. Pori C Bit Utilization
176
Functional
Description
(Continued)
allowed to go Low. The deskew hmer therefore
guarantees that the output data is valid for a
specified minimum amount of time before DA V
goes Low. Deskew hmers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data IS "strobed" into or out of
the port by the external logic. The fallIng edge
of the Acknowledge Input (ACKIN) strobes
data Into or out of the port. Figure 7 shows
timIng for the Strobed Handshake. In contrast
to the Interlocked Handshake, the sIgnal
indicatIng the port IS ready for another data
transfer operates independently of the ACKIN
input. It IS up to the external logIC to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wlre Handshake is
designed for the sltuahon In whICh one output
port IS communicating WIth many input ports
sImultaneously. It is essenhally the same as the
Interlocked Handshake, except that two signals
are used to Indicate If an Input port IS ready
for new data or If It has accepted the present
data. In the 3-Wlre Handshake (FIgure 8), the
nSIng edge of one status line indIcates that the
port IS ready for data, and the nSIng edge of
another status lIne IndICates that the data has
been accepted. With the 3-Wire Handshake,
the output hnes of many input ports can be
bussed together WIth open-drain drivers; the
INPUT HANDSHAKE
DATA
=:x
output port knows when all the ports have
accepted the data and are ready. This IS the
same handshake as is used on the IEEE-488
bus. Because thIS handshake requires three
lines, only one port (eIther A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake IS not available In the bIdirectional
mode. Because the port's direchon can be
changed under software control, however,
bldirechonal IEEE-488-type transfers can be
performed.
Pulsed Handshake. The Pulsed Handshake
(FIgure 9) is designed to interface to
mechamcal-type deVIces that require data to
be held for long periods of hme and need
relahvely wide pulses to gate the data into or
out of the device. The logIC IS the same as the
Interlocked Handshake mode, except that an
Internal counter/timer IS lInked to the handshake logic. If the port IS specifIed in the input
mode, the hmer is Inserted In the ACKIN path.
The external ACKIN Input tnggers the timer
and ItS output is used as the Intetlocked Handshake's normal ackriowledge Input. If the port
IS an output port, the hmer IS placed in the
Data AvaIlable (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output IS used as the actual DAV output. The
counter/hmer maIntaInS all of its normal
capabihhes. ThIS handshake is not avaIlable to
bidirechonal ports.
OUTPUT HANDSHAKE
X'-__________
VALID
DATA
NEXT BYTE
ACKIN
STROBED
HANDSHAKE ......,
RFD
-
--
' - _ _ _-L _ _...J '"W-~;~~~~~~~D
DATA LATCHED
IN BUFFER REGISTER
DATA SHIFTED
TO INPUT REGISTER
r--i----"''''--...-----'-. $~;~~~~~~~D
DAY
'----
I
STROBED
HANDSHAKE
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Figure 7. Interlocked and Strobed Handshakes
OUTPUT HANDSHAKE
INPUT HANDSHAKE
DATA::=:X
DAY
INPUT
VALID
X'-__________
DATA
NEXT BYTE
RFD
INPUT
RFD
DAC
OUTPUT
INPUT
DAC
DAY
OUTPUT
OUTPUT
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Figure 8. 3-Wire Handshake
2014·005, 006
177
Functional
Description
(Continued)
REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a data transfer via the Z-Bus. It is
mtended for use with a DMA-type device. The
WAIT sIgnal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUEST/WAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a handshake and a
REQUEST/WAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (lTB) control bit. When ITB is a, the
REQUEST line goes active as soon as the
Z-CIO is ready for a data transfer. If ITB IS I,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte IS available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bIdIrectional ports only. In this
case, the REQUEST line indicates the status of
the register not bemg used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line IS High when the Output
regIster is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
mterrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allowing the port to recognize patterns in all of
its configurations. The pattern can be
independently specified for each bit as I, a,
nsing edge, falling edge, or any transition.
Individual bits may be masked off. A patternmatch is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT
ACKIN'
OUTPUT PORT
Figure 9. Pulsed Handshake
178
The pattern specified in the Pattern Definition register assumes that the data path IS programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
specified. Output bits used in the patternmatch logic are internally sampled before the
invert/noninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as I/O for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the invertlnoninvert
logic) in all cases except for simple inputs with
l's catchers. In this case, the output of the I's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports specified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transItion from a no-match to a match state is
not reqUIred.
The pattern-recognition logic of bit ports
operates m two basic modes: Transparent and
Latched. When the Latch on Pattern Match
(LPM) bit is set to a (Transparent model, the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily mdicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = 1), the state of all the
port inputs at the time the interrupt was generated is latched in the input register and held
unhl IP is cleared. In all cases, the PMF indicates the state of the port at the time it is read.
If a match occurs while IP is already set, an
error condlhon eXIsts. If the Interrupt On Error
bit (lOE) is a, the match is ignored. However,
if IOE is I, after the first IP is cleared, it is
automatically set to I along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP IS cleared.
When a pattern-match IS present in the
OR-Priority Encoded Vector mode, IP is set to
I. The IP cannot be cleared until a match is no
longer present. If the interrupt vector IS
allowed to include status, the vector returned
durmg Interrupt Acknowledge indIcates the
hIghest pnority bIt matchmg its specification at
the time of the Acknowledge cycle. Bit 7 is the
highest pnority and bit a is the lowest. The bit
imhally causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the
Acknowledge cycle is imtiated, the vector is
2014·007
Functional
Description
(Continued)
frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt IS serviced, the I's
catcher can be used to hold the value.
Because a no-match to match translhon is not
required, the source of the Interrupt must be
cleared before IP is cleared or else a second
Interrupt IS generated. No error detechon IS
performed In this mode and the Interrupt On
Error bit should be set to O.
CIT I
C/T2
C/Ta
Counter/TImer Output
PB 4
PB 0
PC 0
Counter Input
PB 5
PB I
PC I
Trigger Input
PB 6
PB 2
PC 2
Gate Input
PB 7
PB 3
PC 3
Function
Table 2. Counter/Timer External Access
The flexibility of the counter/timers is
enhanced by the prOVision of up to four lines
per counter/timer (counter input, gate input,
trigger input, and counter/hmer output) for
direct external control and status. Counter/
Timer I's external I/O lines are provided by
the four most significant bits of Port B.
Counter/Timer 2's are prOVided by the four
least significant bits of Port B. Counter/Timer
3's external I/O lines are prOVided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode SpecifIcation
registers.
When external counter/timer I/O lines are to
be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lmes used for counter/hmer I/O
have the same characterIstics as simple Input
lines. They can be speCified as inverting or
nonmverting; they can be read and used with
the pattern-recognition logic. They can also
include the I's catcher input.
Counter/Timers I and 2 can be linked internally in three different ways. Counter/Timer
I's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer I
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles aVailable for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/
Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the Pattern
Match Flag (PMF). The data is compared with
the match pattern when it is shifted from the
Buffer register to the Input register (input port)
or when it is shifted from the Output register to
the Buffer register (output port). The patternmatch logic can oveuide the handshake logic
in certain situations. If the port is programmed
to Interrupt when two bytes of data are
available to be read or written, but the first
byte matches the specified pattern, the
pattern-recognition logic sets IP and generates
an mterrupt. While PMF IS set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emptied while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit IS
set, IP is set only when the data matches the
pattern. This IS useful in DMA-type applicahons when Interrupts are required only after a
block of data is transferred.
Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-blt down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode Specification register,
an 8-blt Command and Status register, and the
associated control logic that links these
registers.
PCLKl2 OR
COUNTER INPUT
TRIGGER
~
U
GATE
I
PULSE OUTPUT
ONE SHOT
OUTPUT
SQUARE WAVE
OUTPUT
FIRST HALF
I TC-1 I
TC
TC-1
/1
I
TC-2
I
1
I
6:
I
rI
--------1.f........-.-J
---.J
'-
/~
r---
--------------1.l;c---J
SQUARE WAVE - OUTPUT
-
-
-
---------ifr---,
~
SECOND HALF
Figure 10. Counter/Timer Waveforms
2014-008
179
N
n
o
Functional
Description
(Continued)
180
hmer waveforms. When the Pulse mode is
spec!f!8d, the output goes High for one clock
cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode,
the output goes High when the counter/timer IS
triggered and goes Low when the down-.
counter reaches O. When the square-wave output duty cycle IS specified, the counter/hmer
goes through two full sequences for each
cycle. The imhal trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a 1 count is
detected on the down-counter's clocking edge,
the output goes High and the hme constant
value IS reloaded. On the clocking edge, when
both the down-counter and the output are l's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode Specification register controls operahon of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count IS reached, the countdown sequence
stops. If the C/SC bit IS 1 each time the countdown counter reaches I, the next cycle causes
the hme constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new hme constant
value IS loaded.
Counter/timer operations reqUire loading the
time constant value In the Time Constant
register and imhatlng the countdown sequence
by loading the down-counter with the hme
constant value. The Time Constant register is
accessed as two 8-blt registers. The registers
are readable as well as writable, and the
access order IS irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter IS loaded In one of
three ways: by writing a 1 to the Trigger
Command Bit (TCB) of the Command and
Status register, on the rising edge of the external trigger Input, or, for Counter/Timer 2 only,
on the rising edge of Counter/Timer l's internal output if the counters are linked via the
trigger input. The TCB is write-only, and read
always returns O.
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/hmers' hardware and software gate inputs are High. If any
of the gate Inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are 1
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrlgger Enable Bit (REB) In the Mode
Speclficahon register. If REB IS 0, retriggers
are ignored and the countdown continues normally. If REB IS 1, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output
is programmed in the Square-Wave mode,
ret rigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECE] bit IS 0), the down-counter is clocked
Internally by a signal that is half the frequency
of the PCLK Input to the chip. In the Counter
mode (ECE is 1), the down-counter is
decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to 1,
and if Interrupts are enabled (IE = 1), an interrupt IS generated. If a terminal count occurs
while IP IS already set, an internal error flag is
set. As soon as IP is cleared, It is forced to a 1
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag IS set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter Via the Current Count
register or by testing the Count In Progress
(CIP) status bit In the Command and Status
register. The CIP status bit IS set when the
down-counter IS loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16-bit register, acceSSible as two
8-bit registers, whICh mirrors the contents of
the down-counler. ThiS register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a 1 to
the Read Counter Control (RCC) bit In the
counter/timer's Command and Status register.
ThiS freezes the value in the Current Count
regISter unhl a read of the least significant
byte is performed.
Interrupt Logic Operation. The interrupts
generated by the Z-CIO follow the Z-Bus
operation as described more fully in the Zilog
Z-Bus Summary. The Z-CIO has five potential
sources of interrupts: the three counter/hmers
and Ports A and B. The prionties of these
sources are fixed in the follOWing order:
Counter/Timer 3, Port A, Counter/Timer 2,
Port B, and Counter/Timer 1. Since the
counter/hmers all have equal capabilities and
Ports A and B have equal capabilihes, there is
no adverse impact from the relahve priOrities.
The Z-CIO interrupt prionty, relahve to
other components Within the system, IS determined by an Interrupt daiSy chain. Two pins,
Interrupt Enable In (IEI) and Interrupt Enable
Out (lEO), provide the Input and output
necessary to Implement the daisy chain. When
IEI IS pulled Low by a higher prlonty device,
Functional
Description
(Continued)
the Z-CIO cannot request an interrupt of the
CPU. The followmg discussion assumes that
the lEI line is High.
Each source of interrupt in the Z-CIO contams three bIts for the control and status of the
interrupt logic: an Interrupt Pending (lP)
status bit, an Interrupt Under Service (IUS)
status bIt, and an Interrupt Enable (IE) control
bIt. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (lNT) output Low, if the
associated IE is 1.
The IUS status bIt IS set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge commences. It
can also be set directly by the CPU. Its
pnmary function IS to control the mterrupt
daIsy cham. When set, it disables lower priority sources m the daisy chain, so that lower
prionty interrupt sources do not request servlcmg whIle higher prionty devIces are being
serviced.
The IE bit provIdes the CPU wIth a means of
masking off individual sources of interrupts.
When IE IS set to 1, an mterrupt IS generated
normally. When IE IS set to 0, the IP bIt IS set
when an event occurs that would normally
reqUIre service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts wIthin the Z-CIO to be
disabled without having to indIVIdually set
each IE to 0. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Cham
(DLC) bit is mcluded to allow the CPU to
modIfy the system daisy cham. When the DLC
bit is set to 1, the Z-CIO's lEO is forced Low,
independent of the state of the Z-CIO or its lEI
input, and all lower pnonty devices' interrupts
are dIsabled.
As part of the Interrupt Acknowledge cycle,
the Z-CIO IS capable of respondmg wIth an
8-blt mterrupt vector that specifIes the source
of the interrupt. The Z-CIO contams three vector regIsters: one for Port A, one for Port B,
and one shared by the three counter/timers.
The vector output IS mhibited by settmg the No
Vector (NV) control bit to 1. The vector output
can be modifIed to include status information
to pmpomt more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = 1, reading the base vector register
always mcludes status, independent of the
state of the VIS bIt. In thIS way, all the mformati on obtained by the vector, mcludmg
status, can be obtained with one addItional
instruction when VIS is set to 0. When
MIE = 0, readmg the vector regIster returns
the unmodified base vector so that it Cdn be
venfIed. Another regIster, the Current Vector
register, allows use of the Z-CIO m a polled
environment. When read, the data returned IS
the same as the mterrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector regIster IS read-only.
Programming
Programmmg the Z-CIO entaIls loading control registers with bIts to implement the desired
operatIon. Individual enable bits are prOVIded
for the various major blocks so that erroneous
operations do not occur while the part IS being
InItIalIzed. Before the ports are enabled, IPs
cannot be set, REQUEST and WAIT cannot be
asserted, and all outputs remam hIgh-Impedance. The handshake Imes are Ignored untIl
Port C is enabled. The counter/timers cannot
be triggered until their enable bits are set.
The Z-CIO is reset by forcing AS and OS
Low sImultaneously or by writing a 1 to the
Reset bIt. Once reset, the only thing that can
be done is to read and write the Reset bIt.
Writes to all other bits are ignored and all
reads return Os. In this state, all control bIts
are forced to 0. Only after clearing the Reset
bit (by writing to it) can the other command
bits be programmed.
Register Addressing. The Z-CIO allows two
schemes for register addressmg. Both schemes
use only SIX of the eIght bIts of the address/
data bus. The scheme used IS determined by
the RIght JustIfy Address (RJA) bIt m the
Master Interrupt Control regIster. When RJA
equals 0, address bus bIts and 7 are ignored,
and bIts 1 through 6 are decoded for the
regIster address (Ao from ADj). When RJA
equals 1, bIts through 5 are decoded for the
regIster address (Ao from ADo). In the following regIster descnplIons, only SIX bIts are
shown for addresses and represent address/
data bus bIts through 5 or 1 through 6,
dependmg on the state of the RJA bIt.
°
°
°
181
Registers
Master Interrupt Control Register
Address: 000000
(Read/Write)
!J
INTERRUPT~
MASTER
ENABLE (MIE)
DISABLE LOWER CHAIN (OLC)
NO VECTOR
I
~
PORT A VECTOR INCLUDES
STATUS (PA VIS)
L
Master Configuration Control Register
Address: 000001
(Read/Write)
PORTB~JJ
LRESET
ENABLE (PBE)
RIGHT JUSTIFIED ADDRESSES
o =SHIFT LEFT (Ao from AD1)
1 = RIGHT JUSTIFY (Ao from ADol
COUNTERITIMER 1
ENABLE (CT1E)
COUNTERfTlMERS VECTOR
INCLUDES STATUS (eT VIS)
COUNTERITIMER 2
ENABLE (CT2E)
PORT B VECTOR INCLUDES
STATUS (PB VIS)
PORT C AND COUNTERI
le
T
TIMER 3 ENABLE
(peE AND CT3E)
COUNTERITIMER LiNK
CONTROLS (Le)
LCl
----0
o
1
1
LCD
0
1
0
1
COUNT
CIT l's
CIT l's
CIT l's
INDEPENDENT
GATES CIT 2
TRIGGERS CIT 2
IS CIT 2's
COUNT INPUT
PORT A ENABLE (PAE)
PORT LINK CONTROL (PlC)
0= PORTS A AND B OPERATE INDEPENDENTLY
1;:: PORTS A AND B ARE LINKED
Figure II. Master Control Registers
Port Handshake Specification Registers
Addresses: 100000 Port A
101000 Port B
(ReadlWrite)
Port Mode Specification Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
1~1~1~1~1~1~1~1~1
PORTTYPE~
SELECTS (PTS)
PiS1 PTS2
o
o
1
0
1
0
1
1
BIT PORT
INPUT PORT
OUTPUT PORT
L
BIDIRECTIONAL
PMS1 PMSO
o
0
o
1
1
0
1
1
PORT
SINGLE BUFFERED
MODE (SB)
LATCH ON PATTERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (oTE)
(HANDSHAKE MODES)
HANDSHAK. E TYPE SPECIFICATION
BITS (HSn
Hsn HSTO
o 0 INTERLOCKED HANDSHAKE
o 1 STROBED HANDSHAKE
1
0 PULSED HANDSHAKE
1
1 THREE WIRE HANDSHAKE
PATTERN MODE SPECIFICATION
BITS (PMS)
INTERRUPT ON TWO
BYTES (ITB)
DISABLE PATTERN MATCH
"AND"MODE
"OR" MODE
"OR·PRIORITY ENCODED
VECTOR" MODE
L-_ _ _
J
1~1~1~1~1~1~1~1~1
DESKEW TIME SPECIFICATION
BITS
~~~~I:~~I~HE~ ~:~sC°ciNSTANT
lSB IS FORCED 1
REQUESTfWAIT SPECIFICATION BITS
IRWS)
RWS2
RWS1
INTERRUPT ON MATCH ONLY (IMO)
~ort
------c
RWSO FUNCTION
RECUEST/WAIT DISABLED
OUTPUT WAIT
INPUT WAIT
SPECIAL REQUEST
OUTPUT REQUEST
INPUT REQUEST
Command and Status Registers
Addresses: 100001 Port A
101001 Port B
(Read/Write)
INTERRUPT UNDER
SERVICE (IUS)
~J
INTERRUPT ENABLE (IE)
INTERRUPT PENDING (IP)
IUS, IE AND IP ARE
WRITTEN USING THE
FOLLOWING COMMAND:
~L
I L
,
INTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (IRF)
(READ ONLY)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLY)
EI!!!~
NULL CODE
CLEAR IP Be IUS
SET IUS
CLEAR IUS
SET IP
CLEAR IP
SET IE
CLEAR IE
INTERRUPT ERROR (ERR) _ _ _---J
(READ ONLy)
Figure 12. Port Specification Registers
182
2014-009,010
Registers
(Continued)
Data Direction Regi~l~rs
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(Read/Write)
Data Path Polarity Registers
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(Read/Write)
L-_ _ _ _ DATA DIRECTION (DO)
0= OUTPUT BIT
1 =INPUT BIT
' - - - - - DATA PATH POLARITY (DPP)
0= NON INVERTING
1 =INVERTING
Speciall!O Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(Read/Write)
I0, I0.1 0, I0.1 0, I0, I0, I0.1
L -_ _ _ _ SPECIAL INPUT/OUTPUT (SIO)
0= NORMAL INPUT OR OUTPUT
1 =OUTPUT WITH OPEN DRAIN OR
INPUT WITH "5 CATCHER
Figure 13. Bit Path Definition Registers
Port C Data Register
Address: 001111
(Read/Write)
Port Data Registers
Addresses: 001101 Port A
001110 Port B
(Read/Wnte)
4 MSBs
O=WRITING OF CORRESPONDtNG lSB ENABLED
1 = WAITING OF CORRESPONDING LSB INHIBITED
(READ RETURNS 1)
Figure 14. Port Data Registers
Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(Read/Wnte)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Port B
(Read/Write)
p~
o
o
1
1
1
PT PP
0 X
X
0
1
PATTERN SPECIFICATION
BIT MASKED OFF
ANY TRANSITION
ZERO
lONE
0 ONE'IO-ZERO TRANSITION (I)
1 ZERo·rO-ONE TRANSITION (tl
Pattern Mask Registers (PM)
Addresses: 100111 Port A
101111 Port B
(Read/Write)
Figure 15. Pallern Definition Registers
2014-011,012,013
183
Registers
(Continued)
Counter/Timer Command and Status Registers
Addresses:. 001010 Counter/TImer I
001011 Counter/Timer 2
001100 Counter/TImer 3
(Read/Parhal WrIte)
I D, I D,I D, I D,I D, I D, I D, I D,I
INTERRUPT UNDER
SERVIC~
(AEAOIWRITE)
jJ I
I
I
INTERRUPT ENA~
(REAOfWRITE)
It;lTERRUPT
PEND~
I
I
I
I
E~
COUNT IN PROGRESS (CIP)
(READ ONLy)
TRIGGER COMMAND BIT (TeB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (GCB)
(READfWRITE)
(READfWRITE)
IUS, IE, AND IP ARE WRITTEN USING
READ COUNTER CONTROL (RCG)
(READ/SET ONLY CLEARED BY READING eCR LSB)
THE FOLLOWING CODE
NULL CODE
0
0
0
CLEAR IP & IUS
0
0
1
SET IUS
0
1
0
CLEAR IUS
0
1
1
SET IP
1
0
0
CLEAR IP
1
0
1
SET IE
1
1
0
CLEAR IE
1
1
1
INTERRUPT ERROR (ERR) - - - - - '
(READ ONL.Y)
Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/TImer I
01110 I Counter/TImer 2
01111 0 Counter/Timer 3
(ReadlWrite)
10 , I D,I D, 10 ,1 D, I D, I D, I D,I
CONTINUOUS SllJ
GLE CYCLE (C/SC)
JJillj
EXTERNAL OUTPUT
ENABLE (EOE)
EXTERNAL COUNT
ENABLE (EGE)
EXTERNAL TRIGGER
ENABLE (ETE)
L
[
OUTPUT DUTY CYCLE
SELECTS (DCS)
eSC1 DCSO
~ 0- PULSE OUTPUT
o
1
1
1
0
1
ONE SHOT OUTPUT
SQUARE WAVE OUTPUT
DO NOT SPECIFY
RETRIGGER ENABLE BIT (REB)
EXTERNAL GATE ENABLE (EGE)
Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer I's MSB
010001 Counter/Timer I's LSB
010010 Counter/TImer 2's MSB
010011 Counter/Timer 2's LSB
010100 Counter/TImer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)
MOST----J
SIGNIFICANT
BYTE
"----LEAST
SIGNIFICANT
BYTE
Counter/Timer Time Constant Registers
Addresses: 010110 Counter/Timer I's MSB
010111 Counter/Timer I's LSB
011000 Counter/Timer 2' s MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/TImer 3's LSB
(Read/WrIte)
MOST - - - - - '
SIGNIFICANT
BYTE
"----LEAST
SIGNIFICANT
BYTE
Figure 16. Counter/Timer Registers
184
2014·014
Registers
Interrupt Vector Register
(Continued)
Addresses. 000010 Port A
000011 Port B
000100 Counter/Timers
Current Vector Regi
Address: a]]]]]
(Read Only)
(ReadIWnte)
' - - - - - INTERRUPT VECTOR BASED
ON HIGHEST PRIORITY
UNMASKED IP
IN NO INTERRUPT PENDING
ALL 1'5 OUTPUT
' - - - - - INTERRUPT VECTOR
PORT VECTOR STATUS
PRIORITY ENCODED VECTOR MODE
~
x
~
x
~
x
NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH
ALL OTHER MODES
03
02
D,
ORE IRF PMF
a
0
0
NORMAL
ERROR
CQUNTERfTlMER STATUS
D2 D,
(01)
o 1
1 0
1 1
CIT 3
CIT 2
CIT 1
eRROR
Figure 17. Interrupt Vector Registers
Register
Address
Summary
Main Control Register.
Address
(AD 7-ADo)
OOOOOOXX
OOOOOIXX
OOOOIOXX
OOOOIIXX
OOOlOOXX
OOOIOIXX
OOOllOXX
OOOlllXX
RegIster Name
Master Interrupt Control
Ma,ster Conhgurahon Control
Port A's Interrupt Vector
Port B's Interrupt Vector
Counter/TImer's Interrupt Vector
Port C's Data Path Polanty
Port C's Data D,rechon
Port C's SpecIal I/O Control
Counter/Timer Related Registers (Conhnued)
Address
(AD 7-ADO) Register Name
CounterlTlmer 2's Time Constant-MSBs
OIlOOOXX
Counter/Timer 2's Time Constant-LSBs
OIIOOIXX
Counter/Timer 3's Time Constant-MSBs
OllOlOXX
OllOllXX
Counter/Timer 3's Time Constant-LSBs
Counter/Timer I's Mode Speclhcahon
OIIlOOXX
Counter/Timer 2's Mode SpeClhcahon
OlllOlXX
OllllOXX
Counter/Timer 3' s Mode Speclhcahon
Oil I llXX
Current Vector
Port A Specification Register.
Most Often Accessed Registers
Address
(AD7-ADO)
OOlOOOXX
001001 XX
00 lO lOXX
OOlOIIXX
OOIlOOXX
OOIlOlXX
OOlllOXX
OOIlIlXX
RegIster Name
Port A's Command and Status
Port B's Command and Status
Counter/TImer I's Control
Counter/TImer 2'8 Control
Counter/TImer 3's Control
Port A's Data
Port B's Data
Port C's Data
Address
(AD 7-ADO)
lOOOOOXX
lOOOOIXX
lOOOlOXX
1000 II XX
lOOlOOXX
lOOlOlXX
lOOllOXX
lOOlllXX
Port B Specification Registers
Counter/Timer Related Register.
Address
(AD7-ADO)
OlOOOOXX
010001 XX
OlOOIOXX
olOO II XX
OJOlOOXX
OJOJOlXX
OlOllOXX
OlOIllXX
2014-015
RegIster Name
Counter/TImer
Counter/TImer
CounterlTlmer
CounterlTlmer
Counter/TImer
Counter/TImer
Counter/TImer
Counter/TImer
I's Current Count-MSBs
I's Current Count-LSBs
2's Current Count-MSBs
2's Current Count-LSBs
3's Current Count-MSBs
3's Current Count-LSBs
I's TIme Constant-MSBs
I's TIme Constant-LSBs
RegIster Name
Port A's Mode SpeclflCahon
Port A's Handshake SpeClhcahon
Port A's Data Path Polanty
Port A's Data Direchon
Port A's SpecIal I/O Control
Port A's Pattern Polanty
Port A's Pattern Translhon
Port A's Pattern Mask
Address
(AD 7-ADO)
lOlOOOXX
lOlOOIXX
lOJOJOXX
lO lOll XX
lOllOOXX
lOllOIXX
lOlllOXX
lOll II XX
RegIster Name
Port B's Mode Speclhcahon
Pori B's Handshake SpeClhcahon
Port B's Data Path Polanty
Port B's Data Dlrechon
Port B's SpecIal 110 Control
Port B's Pattern Polanty
Port B's Pattern Translhon
Port B's Pattern Mask
185
Timing
:4 Read Cycle.
The CPU places an address on
. ,the address/data bus, The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CS1). Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The data from the register specified is
strobed onto the address/data bus when the
CPU issues a Data Strobe (DS). If the register
indicated by the address does not exist, the
Z-CIO remains high-impedance.
cs.
Write Cycle. The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CS1). Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The CPU places the data on the
address/data bus and strobes it into the Z-CIO
register by issuing a Data Strobe (DS).
cs.
t=
RlW~
Di
ADO-AD7
==)C~~}----(~R~EA~D~D~AT~')
ADo-AD7
r-
\
~
x::=
WRITE DATA
Figure 19. Write Cycle Timing
Figure 18. Read Cycle Timing
Interrupt Acknowledge Cycle. When one of
the IP bits in the Z-CIO goes High and interrupts are enabled, the Z-CIO pulls its INT
output line Low, requesting an interrupt. The
CPU responds with an Interrupt Acknowledge
cycle. When INTACK goes Low with IP set, the
Z-CIO pulls its Interrupt Enable Out (lEO)
Low, disabling all lower priority devices on the
daisy cham. The CPU reads the Z-CIO interrupt vector by issuing a Low DS, thereby
strobing the interrupt vector onto the address/
data bus. The IUS that corresponds to the IP is
also set, which causes lEO to remain Low.
-J!
ijff _ _ _ _ _ _ _ _ _ _
lEI
lEO
ADO-AD.,
\'------\'--_....J/
==)(r'IG~NO~R~ED~------<
'INTACK
IS
decoded from ZSOOO status,
Figure 20. Interrupt Acknowledge Timing
186
2014·016.017.018
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3Vto +7.0V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those hsted under Absolute MaxImum Rahngs may cause permanent damage to the device.
This IS a stress ratmg only; operation of the device at any
condition above those indicated m the operational sechons
of these speClflcahons IS not Implied. Exposure to absolute
maximum rahng condlhons for extended perIods may affect
device relIabihty.
• +4.75 V S Vee S +5.25 V
• GND = 0 V
• TA as speCified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+SV
dr
+SV
2.2K
2.2K
FROM OUTPUT
UNDER TEST
SOPF
Figure 21. Standard Test Load
DC
Characteristics
Figure 22. Open-Drain Test Load
Parameter
Min
Max
Unit
VIH
VIL
VOH
VOL
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
2.0
Vee +0.3
-0.3
2.4
V
V
V
IlL
IOL
ICC
Input Leakage
Output Leakage
Vee Supply Current
Symbol
0.8
0.4
0.5
± 10.0
± 10.0
250
V
V
/loA
/loA
rnA
Condition
IOH = - 250 p.A
IOL = +2.0 rnA
IOL= +3.2 rnA
0.4 s VIN S +2.4 V
0.4 s VOUT
S
+2.4 V
Vee = 5 V ± 5% unless otherwise speclhed. over specIfied temperature range.
Capacitance
Symbol
CIN
COUT
CliO
Parameter
Input CapaCitance
Output Capacitance
Bidirectional CapaCitance
Min
Max
Unit
Test Condition
10
pF
pF
pF
Unmeasured Pms
Returned to Ground
15
20
f = 1 MHz, over speclhed temperature range.
8085-0209, 000 1
187
CPU
Number Symbol
Interface
Timing
Parameter
Min
Max
Units
2000
ns
TwAS
AS Low Width
70
2
TsA(AS)
Address to AS 1 Setup Time
10
ns
3
ThA(AS)
Address to AS 1 Hold Time
50
ns
4
TsA(DS)
Address to DS I Setup Time
120
5 -TsCSO(AS) -CSo to AS 1 Setup Time
ThCSO(AS)
CSo to AS 1 Hold Time
60
ns
7
TdAS(DS)
AS 1 to DS I Delay
60
ns
8
TsCSl(DS)
CS I to DS I Setup Time
100
ns
TsRWR(DS)
RIW (Read) to DS I Setup TIme
9
lO-TsRWW(DS)-RIW (Write) to DS I Setup Time
100
ns
11
TwDS
DS Low Width
390
ns
12
TsDW(DSf)
Write Data to DS I Setup Time
30
ns
13
TdDS(DRV)
DS (Read) I to Address Data Bus Driven
.0
14
TdDSf(DR)
DS I to Read Data Valid Delay
0
255
15-ThDW(DS)- Write Data to DS 1 Hold Time
Interrupt
Timing
TdDSr(DR)
iSS 1 to Read Data Not Valid Delay
17
TdDS(DRz)
DS 1 to Read Data Float Delay
18
ThRW(DS)
RIW to DS 1 Hold Time
19
ThCSl(DS)
CS I to DS 1 Hold Time
ns
0
70
AS I Delay
ns
60
ns
2
60
ns
50
ns
1000
ns
3
AS cycle
+ns
AS cycle
+ns
4
21
Trc
Vahd Access Recovery Time
22
TdPM(INT)
Pattern Match to INT Delay (BIt Port)
23
TdACK(INT)
ACKIN to INT Delay (Port wIth Handshake)
4
Counter Input to INT Delay (Counter Mode)
1 - - AS cycle - - +ns
25
TdPC(INT)
PCLK to INT Delay (TImer Mode)
26
TdAS(INT)
AS to INT Delay
27
TsIA(AS)
INTACK to AS 1 Setup Time
28
ThIA(AS)
INTACK to
AS cycle
+ns
ns
AS 1 Hold Time
TsAS(DSA)
AS 1 to DS (Acknowledge) I Setup Time
29
30-TdDSA(DR)- DS (Acknowledge) I to Read Data Valid Delay
0
ns
250
ns
350
ns
360-- ns
31
TwDSA
DS (Acknowledge) Low Width
TdAS(IEO)
AS I to lEO I Delay (INTACK Cycle)
350
ns
5
33
TdIEI(IEO)
lEI to lEO Delay
150
ns
5
34
TsIEI(DSA)
lEI to DS (Acknowledge) I Setup Time
100
ns
5
35 -
ThIEI(DSA) -
lEI to DS (Acknowledge) 1 Hold Time
100
ns
36
TdDSA(INT)
DS (Acknowledge) I to INT 1 Delay
1. Parameter does not apply to Interrupt Acknowledge transac~
hons.
2. Float delay IS measured to the hme when the output has
changed 0.5 V from steady state with mInImum fle load and
maximum de load.
3. Th,s IS the delay from 5§ I of one cia access to OS I of
another CIa access.
4. The delay IS from DAV I for 3-Wlre Input Handshake. The
delay IS from DAC I for 3-Wlre Output Handshake. One add,-
475
5
32
NOTES:
188
ns
30
16
24-TdCI(INT) -
Interrupt
Acknowledge
Timing
ns
ns---I-
0
6
20-TdDS(AS)-DS 1 to
Notes·
honal As cycle
mode.
ns
600
IS
required for ports
5. The parameters for the
deViceS 10
ns
In
the S10gle Buffered
any parhcuiar cia!!1 chal~
must meet the followmg constr.mt: the delay from AS I to DS I
must be greater than the sum of TdAS(IEO) for the hIghest
priorlly peripheral, TsIEI(DSA) for the lowest Priority
peripheral, and TdlEI(IEO) for e.ch peripheral seperatmg them
In the cham.
.. Timings are prelImmary and subject to change
CPU
Interface
Timing
CS,
NW
READ
NW
WRITE
------~~r=~+----------+~----------_ _ _ _++...J
----+I----=f-:;::-l--------l--f.--::----.,..--
ADDRESS
ADO-ADT
CIO
WRITE
CIO
READ
Interrupt
Timing
PATTERN MATCH
INPUT(S)
BIT PORT
.
PATIERN MATCHES
.
NOTE 4
COUNTER
INPUT
PCLK
is
INT
Interrupt
Acknowledge
Timing
ADO-AD7 _ _ _ _ _
.. '
®
ACKIN
If.
®
®
.
@
·
·
·
~"\
XUNDEFINED)-------
lEI
lEO
2014-019, 020, 021
189
Handshake
Timing
Number Symbol
I
TsDI(ACK)
2
ThDI(ACK)
TdACKf(RFD)
3
4
TwACKI
5-TwACKh
TdRFDr(ACK)
6
TsDO(DAV)
7
Parameter
Min
Data Input to ACKIN I Setup Time
Data Input to ACKIN I Hold TimeStrobed Handshake
ACKIN I to RFD I Delay
ACKIN Low Width-Strobed Handshake
ACKIN High Width-Strobed Handshake
a
RFD t to ACKIN I Delay
Data Out to DAV I Setup Time
TdDAVf(ACK)
DAV I to ACKIN I Delay
8
ThDO(ACK)
Data Out to ACKIN I Hold Time
9
la -TdACK(DAV) --ACKIN I to DAV t Delay
11
ThDI(RFD)
a
a
25
Data Input to RFD I Hold TimeInterlocked Handshake
TdRFDf(ACK)
NOTES: '
1. ThIS hme can be extended through the use of the deskew tuners.
*Tlmlngs are prehmlnary and subject to change.
190
Units
ns
ns
RFD I to ACKIN t DelayInterlocked Handshake
TdACKr(RFD)
13
ACKIN t (DAV I) to RFD t DelayInterlocked and 3-Wire
Handshake
TdDAVr(ACK)
DAV t to ACKIN t (RFD I)-Interlocked
14
and 3-Wire Handshake
15'-TdACK(DAV)--ACKIN t (RFD I) to DAV I Delay-'-Interlocked and 3-Wire
Handshake
TdDAVIf(DAC)
16
DAV I to DAC t Delay-Input
3-Wire Handshake
ThDI(DAC)
Data Input to DAC t Hold Time17
3-Wire Handshake
TdDACOr(DAV)
DAC t to DAV t Delay-Input
18
3-Wire Handshake
TdDAVIr(DAC)
DAV t to DAC I Delay-Input
19
3-Wire Handshake
2a-TdDAVOf(DAC)-DAV I to DAC t Delay-Output
3-Wire Handshake
21
ThDO(DAC)
Data Output to DAC t Hold Time3-Wire Handshake
TdDACIr(DAV)
DAC t to DAV t Delay-Output
22
3-Wlre Handshake
TdDAVOr(DAC)
DAV t to DAC I Delay-Output
23
3-Wire Handshake
12
Max
ns
ns
ns
ns
a
2
2
ns
ns
TcPC
TcPC
a
ns
a
ns
a
ns
a
ns
a
ns
a
ns
a
ns
a
a
ns
ns
a
ns
2
TcPC
2
TcPC
a
ns
Notes·
Strobed
Handshake
INPUT
OUTPUT
Interlocked
Handshake
DATA
OUTPUT
" ACKIN
DAY
3-Wire
Handshake
DATA
DAY
INPUT
INPUT
RFD
OUTPUT
DAC
OUTPUT
DATA
DAC
INPUT
OUTPUT
RFD
INPUT
DAY
OUTPUT
2014-022,023,024
191
Counter/
Timer
Timing
Parameter
Number Symbol
Min
Max
Unlts
ns
TePC
PCLK Cycle Time
250
4000
2
TwPCh
PCLK High Width
105
2000
ns
3
TwPCI
PCLK Low Width
105
2000
ns
20
ns
20---ns
4
TIPC
PCLK Fall Time
5-TrPC---PCLK Rise Time
6
TeCI
Counter Input Cycle Time
500
ns
7
TClh
Counter Input High Width
230
ns
8
TwCIl
Counter Input Low Width
230
Counter Input Fall Time
TfCI
9
IO-TrCI
Counter Input Rise Time
Trigger Input to PCLK I Setup Time
(Timer Mode)
ns
20
ns
20---ns
II
TsTI(PC}
12
TsTI(CI}
Trigger Input to Counter Input I Setup Time
(Counter Mode)
13
TwTI
TsGI(PC}
Trigger Input Pulse Width (High or Low)
ns
Gate Input to PCLK I Setup Time
(Timer Mode)
ns
14
Notes*
15-TsGI(CI}--Gate Input to Counter Input I Setup Time
(Counter Mode)
ns
2
ns
2
2
ns---2-
16
ThGI(PC}
Gate Input to PCLK I Hold Time (Timer Mode)
ns
2
17
ThGI(CI}
Gate Input to Counter Input I Hold Time
(Counter Mode)
ns
2
18
TdPC(CO}
PCLK to Counter Output Delay (Timer Mode)
ns
19
TdCI(CO}
Counter Input to Counter Output Delay
(Counter Mode)
ns
NOTES:
1 PCLK IS only used wlth the counter/hmers (m Timer mode), the
deskew IImers, and the REQUESTIW AIT logiC If these funchans are not used, the PCLK mput can be held Low.
2. These parameters must be met to guarantee trIgger or gate are
valid for the next counter/hmer cycle.
"'TImmgs are prelImmary and subject to change.
PCLK
PCLKI2
INTERNAL
COUNTER
INPUT
TRIGGER
INPUT
---------1'
GATE - - - - - - - " ' " ' .......----~
INPUT
COUNTER
OUTPUT
192
_ _ _ _ _ _ _...J )....._ _ _ _-'1
--------------------~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
2014-025
REQUEST/
WAIT
Timing
Number Symbol
2
Parameter
Min
Max
Units
TdDS(REQ)
DS I to REQ I Delay
ns
TdDS(WAIT)
DS I to WAIT I Delay
ns
Notes"
TdPC(REQ)
PCLK I to REQ I Delay
ns
3
TdPC(WAIT)
4
PCLK I to WAIT I Delay
ns
5--TdACK(REQ)--ACKIN I to REQ I D e l a y - - - - - - - - - - - - A S cycles--l+ PCLK cycles
+ns
TdACK(WAIT)
ACKIN I to WAIT I Delay
PCLK cycles
6
+ ns
NOTES:
1. The delay
The delay
IS
IS
from DAY I for 3-Wlre Input Handshake.
from DAC t for 3-Wue Output Handshake.
-TImings are prehmmary and subject to change.
PCLK
N
.~
ACKIH
NOTE 1
REQ
~~____________~r----Reset
Number Symbol
Min
Parameter
Timing
Max
Units
1
TdDSQ(AS)
Delay from
55
I to AS I for No Reset
40
ns
2
TdASQ(DS)
Delay from
As
I to DS I for No Reset
50
ns
3
TwRES
Minimum Width of AS and DS both Low
for Reset
250
ns
Notes"
NOTES:
1. Internal CIrCUItry allows for the reset provIded by the Z8
(00 held Low while .AS pulses) to be sufhci8nt.
RESET
INTERNAL
2014-026, 027
-TImings are prelIminary and subject to change.
r
--------------------~
193
Miscellaneous
Port Timing
Number Symbol
Parameler
Min
TrI
Any Input Rise Time
Any Input Fall Time
TfI
Twl's
I's Catcher High Width
3
4--TwPM---Pattern Match Input Valid (Bit Port)
2
Max
Units
100
100
ns
ns
ns
250
750
5
TsPMD
Data Latched on Pattern Match Setup Time
(Bit Port)
6
ThPMD
Data Latched on Pattern Match Hold Time
(Bit Port)
Noles*
0
ns
ns
1000
ns
NOTES:
1. If
the input
IS
programmed Inverhng, a Low-going pulse of the
"TImmgs are prehmmary and subject to change.
same width will be detected.
ANY INPUT
1's CATCHER
INPUT
----'I~V-
-L--
_~)--w--\I......_..:_ _
DA~:~:::: ------------x=~5~~~~~HES~-~~---------
LATCHED TO
PATTERN MATCH ___________
Ordering
Information
Package/
Speed
Temp
Product
Number
Z8036
Z8036
Z8036
CE
CS
DE
Z8036
Z8036
DS
PE
4.0
4.0
4.0
4.0
4.0
Z8036
PS
4.0 MHz
NOTES: C
=
CeramiC, D
=
Description
Z-CIO (40-pin)
MHz
MHz
MHz
MHz
MHz
Cercilp, P
Same as above
Same as above
Same as above
Same as above
=
Product
Number
Z8036A
Z8036A
Z8036A
Z8036A
Same as above
Z8036A
Z8036A
=
=
PlastIc, E
_40°C to +85°C, S
Package/
Temp
Speed
CE
CS
DE
6.0 MHz
6.0 MHz
6.0 MHz
DS
PE
PS
6.0 MHz
6.0 MHz
6.0 MHz
Description
Z-CIO (40-pin)
Same
Same
Same
Same
Same
as
as
as
as
as
above
above
above
above
above
O°C to + 70°C.
','
194
2014-028
00-2014-A
Z8038 Z8000™
Z-FIO FIFO Inputl
Output Interface Unit
Product
Specification
~
Zilog
March 1981
Z8038 Z_BUSTM Version FlO
Z8538 Universal Version FlO
Features
• 128-byte FIFO buffer provides asynchronous
bidirectional CPU/CPU or CPU/peripheral
interface, expandable to any width in byte
increments by use of multiple FIOs.
• Interlocked 2-Wire or 3-Wire Handshake
logic port mode; Z-BUS or non-Z-BUS
interface.
• Pattern-recognition logic stops DMA
transfers and/or interrupts CPU; preset byte
count can initiate variable-length DMA
transfers.
General
Description
The Z8038 FlO provides an asynchronous
128-byte FIFO buffer between two CPUs or
between a CPU and a peripheral device. This
buffer interface expands to a 16-bit or wider
data path and expands in depth to add as
many Z8060 FIFOs (and an additional FlO) as
are needed.
The FlO manages data transfers by assuming
Z-BUS, non-Z-BUS microprocessor (a generalized microprocessor interface), Interlocked
• Seven sources of vectored/non vectored
interrupt which include pattern-match,
byte count, empty or full buffer status;
a dedicated "mailbox" register with
interrupt capability provides CPU/CPU
communication.
• REQUEST/WAIT lines control high-speed
data transfers.
• All functions are software controlled via
directly addressable read/write registers.
2-Wire Handshake, and 3-Wire Handshake
operating modes. These modes interface
dissimilar CPUs or CPUs and peripherals
running under differing speeds or protocols,
allowing asynchronous data transactions and
improving I/O overhead by as much as two
orders of magnitude. Figures I and 2 show
how the signals controlling these operating
modes are mapped to the FlO pins.
+5V
Ii1l
IiTI
[Q]
[jj]
[j]
lEI
QJ
[j]
0,
Do
[Q]
[jj]
QJ
_M,
_Mo
+5 V
0,
03
0,
O.
03
0,
O.
0,
0,
0,
06
M,
0,
GNO
Mo
GND
Figure 1. Pin Functions
2020-096, 097
0,
Figure 2. Pin Assignments
195
General
Description
(Continued)
The FLO supports the Z-BUS interrupt protocols, generating seven sources of interrupts
upon any of the following events: a write to a
message register, change in data direction,
pattern match, status match, over/underflow
error, buffer full and buffer empty status. Each
interrupt source can be enabled or disabled,
and can also place an interrupt vector on the
port address/data lines.
The data transfer logic of the FLO has been
specially designed to work with DMA (Direct
Memory Access) devices for high-speed
transfers. It provides for data transfers to or
from memory each machine cycle, while the
DMA device generates memory address and
control signals. The FLO also supports the
variably sized block length, improving system
throughput when multiple variable length
messages are transferred amongst several
sources.
CPU
INTERFACE
OR
110 PORT
CPU
INTERFACE
DATA
BUS
DATA
\r--tl---i
t--"'v--;t BUS
PORT 1 SIDE : PORT 2 SIDE
Figure 3. FlO Block Diagram
Functional
Description
Operating Modes. Ports I and 2 operate in
any of twelve combinations of operating
modes, listed in Table 2. Port 1 functions in
either the Z-BUS or non-Z-BUS microprocessor
modes, while Port 2 functions in Z-BUS, nonZ-BUS, Interlocked 2-Wire Handshake, and
3-Wire Handshake modes. Table 1 describes
the signals and their corresponding pins in
each of these modes.
Control
Signal
Pins
[KJ
[i]
[£]
[Q]
~
W
@]
[ill
[j]
[j]
Z-BUS
Low Byte
Z-BUS
High Byte
REQIWT
DMASTB
DS
RIW
CS
AS
INTACK
lEO
lEI
!NT
REQIWT
DMASTB
DS
RiW
CS
AS
Aa
AI
A2
A3
The pin diagrams of the FLO are identical,
except for two pins on the Port 1 side, which
select that port's operating mode. Port 2's
operating mode is programmed by two bits in
Port l's Control register O. Table 2 describes
the combinations of operating modes; Table 3
describes the control signals mapped to pins
A-J in the five possible operating modes.
Inter locked
HS Port·
3-Wire
HS Port·
RFD/DAV
RFD/DAV
DAV/DAC
C/D
ACKIN
FULL
EMPTY
CLEAR
DATA DIR
INTACK
lEO
lEI
!NT
INa
OUTI
OE
OUT3
Non-Z-BUS
REQIWT
DACK
RD
WR
CE
DAC/RFD
EMPTY
CLEAR
DATA DIR
INa
OUT]
OE
OUT3
*2 SIde only.
Table 1. Pin Assignments
196
2020·001
Functional
Description
(Continued)
Mode
Ml
MO
Bl
0
0
0
0
BO
0
0
0
5
6
8
0
0
10
0
11
Pori I
Pori 2
Z-BUS
Z-BUS
Z-BUS
Z-BUS
Low Byte
Low Byte
Low Byte
Low Byte
Z-BUS Low Byte
Non-Z-BUS
3-Wlre Handshake
2-Wire Handshake
Z-BUS
Z-BUS
Z-BUS
Z-BUS
High
High
High
High
Z-BUS High Byte
Non-Z-BUS
3-Wire Handshake
2-WIre Handshake
Byte
Byte
Byte
Byte
Non-Z-BUS
Non-Z-BUS
Non-Z-BUS
Non-Z-BUS
Z-BUS Low Byte
Non-Z-BUS
3-WIre Handshake
2-Wlre Handshake
Table 2. Operating Modes
CHANNEL A
,,----, CHANNEL B
PORT 2
<8>
Z8002
, - - - - , PORT 3
<8>
SYSTEM
MEMORY
Z80 BUS
110
Z80
Z·FIO
.....-
}
HANDSHAKE
SIGNALS
Z·FIO
MEMORY
Z·BUS
zao BUS
Figure 4. CPU 10 CPU Configuration
2020-002, 003
Figure 5. CPU to 110 Configuration
197
Pins Common
To Both Sides
Pin
Signal.
Signal
Description
MO
21
19
40
DC power source
GND
20
DC power ground
Pin
Names
Pin Number.
Port
2
ADO- AD7
(Address/Data)
DO-D7,
11-18
REQ/WAIT
(Request/WaIt)
A
DMASTB
(DIrect Memory
Access Strobe)
B
DS
(Data Strobe)
+5 Vdc
GND
Z-BUS
High Byte
Mode
Pin
Numbers
MI
+5 Vdc
MO
Mj
Z-BUS
Low Byte
Mode
Pin
Names
Pin
Signal.
MI and MO program Port I
sIde CPU interface
Signal
Description
29-22
Multiplexed bIdirectIonal address/data Imes, Z-BUS
compatIble.
39
Output, actIve Low, REQUEST (ready) line for DMA
transfer; WAIT Ime (open-dram) output for synchronIzed CPU and FlO data transfers.
2
38
Input, active Low. Strobes DMA data to and from
the FIFO buffer.
C
3
37
Input, active Low. ProvIdes timing for data transfer to or from FlO.
R/W
(ReadlW rIte)
D
4
36
Input; actIve HIgh signals CPU read from FlO;
actIve Low signals CPU WrIte to FlO.
CS
(ChIp Select)
E
5
35
Input, active Low. Enables FlO. Latched on the
rIsing edge of AS.
AS
(Address Strobe)
F
6
34
Input, actIve Low. Addresses, CS and INTACK
sampled whIle AS Low.
INTACK
(Interrupt
Acknowledge)
G
7
33
Input, active Low. Acknowled~ an mterrupt.
lEO
(Interrupt
Enable Out)
H
Latched on the rismg edge of AS.
8
32
lEI
(Interrupt
Enable In)
9
31
INT
(Interrupt)
10
Input, actIve High. ReceIves mterrupt enable from
hlgher priority deVice lEO signal.
30
Names
Pin Numbers
Port
2
AD O-AD 7
(Address/Data)
Do-D7
11-18
REQ/WAIT
(Request/Wait)
A
DMASTB
(DIrect Memory
Access Strobe)
B
DS
(Data Strobe)
R/W
(ReadlWrIte)
Pin
Signal.
Output, active HIgh. Sends mterrupt enable to
lower priOrIty device lEI pm.
Pin
Output, open dram, actIve Low. S,gnals FlO mterrupt request to CPU.
Signal
Description
29-22
Multiplexed b,d,rectional address/data lines, Z-BUS
compatIble.
39
Output, active Low, REQUEST (ready) Ime for DMA
transfer; WAIT Ime (open-dram) output for synchronized CPU and FlO data transfers.
2
38
Input, active Low. Strobes DMA data to and from the
FIFO buffer.
C
3
37
Input, active Low. Provides tImmg for transfer of data
to or from FlO.
D
4
36
Input, actIve HIgh. SIgnals CPU read from FlO; active
Low sIgnals CPU wrIte to FlO.
E
5
35
Input, active Low. Enables FlO. Latched on the
rIsing edge of AS.
AS
(Address Strobe)
F
6
34
Input, active Low. Addresses, CS and INTACK are
sampled whIle AS IS Low.
AO
(Address BIt 0)
G
7
33
Input, actIve HIgh. W,th AI, A2, and A3, addresses
FlO mternal regIsters.
Al
(Address BIt I)
H
8
32
Input, achve High. W,th AO' A2, and A3, addresses
FlO mternal registers.
A2
(Address BIt 2)
9
31
Input, actIve HIgh. W,th AO, AI, and A3, addresses
FlO mternal registers.
A3
(Address BIt 3)
10
30
Input, actIve High. W,th AO, AI, and A2, addresses
FlO mternal registers.
es
(ChIp Select)
Table 3. Signal/Pin Descriptions
198
Non-Z-BUS
Mode
Pin
Signals
Pin
Names
Pin Numbers
Port
4
DO-D7
(Data)
Do-D7
11-18
REQ/WT
(Request/Wait)
A
DACK
(DMA Acknowledge)
B
HiS
Signal
Description
29-22
Bldlrechonal data bus.
39
Output, achve Low, REQUEST (ready) lme for DMA
transfer; WAIT lme (open-dram) output for synchronIzed CPU and FlO data transfer.
2
38
Input, achve Low. DMA acknowledge.
C
3
37
Input, achve Low. SIgnals CPU read from FlO.
WR
(Write)
D
4
36
Input, achve Low. SIgnals CPU WrIte to FlO.
CE
(ChIp Select)
E
5
35
Input, achve Low. Used to select FlO.
ciiS
F
6
34
Input, active HIgh. IdenhfIes control byte on DO-D7;
achve Low IdentifIes data byte on DO-D7.
INTACK
(Interrupt
Acknowledge)
G
7
33
Input, achve Low. Acknowledges an mterrupt.
IEO
(Interrupt
Enable Out)
H
8
32
Output, achve HIgh. Sends mterrupt enable to
lower PrIOrIty deVIce IEI pm.
IEI
(Interrupt
Enable In)
9
31
INT
(Interrupt)
10
(Read)
(Control/Data)
Port 2-1/0
Port Mode
Pin
Signals
N
...C•
10:1
Input, achve HIgh. ReceIves mterrupt enable from
hIgher PrIOrIty deVIce lEO SIgnal.
30
Output, open drain, achve Low. SIgnals FlO Interrupt
to CPU.
Pin
Names
Pin
Numbers
Signal
Description
Mode
DO-D7
29-22
2-Wlre HS<
3,Wlre HS
Bldlrechonal data bus.
RFD/DAV
(Ready for Data/Data
AvaIlable)
A
39
2,Wlre HS
3-Wlre HS
Output, RFD achve Hlgh~nals perIpherals that FlO
IS ready to receIve data. DAV actIve Low SIgnals
that FlO 15 ready to send data to peripherals.
ACKIN
(Acknowledge Input)
B
38
2-Wlre HS
Input, achve Low. SIgnals FlO that output data 15
receIved by perIpherals or that mput data 15 valId.
DAV/DAC
(Data AvaIlable/Data
Accepted)
B
38
3-Wlre HS
Input; DAV (achve Low) SIgnals that data 15 valId on
bus. DAC (achve HIgh) SIgnals that output data IS
accepted by perIpherals.
FULL
C
37
2,Wlre HS
Output, open dram, achve HIgh. SIgnals that FlO
buffer 15 full.
DAC/RFD
(Data Accepted/Ready
for Data)
C
37
3-Wlre HS
Dlrechon controlled by mternal programmmg. Both
achve HIgh. DAC (an output) SIgnals that FlO has
receIved data from perIpheral; RFD (an mput) SIgnals
that the lIsteners are ready for data.
EMPTY
D
36
2-Wlre HS
3-Wlre HS
Output, open dram, achve HIgh. SIgnals that FIFO
buffer 15 empty.
CLEAR
E
35
2-Wlre HS
3-Wlre HS
Programmable mput or output, achve Low. Clears all
data from FIFO buffer.
DATA DIR
(Data DlfectIon)
F
34
2-Wlre HS
~-Wlfe HS
Programmable mput or output. Achve HIgh SIgnals
data mput to Port 2; Low SIgnals data output from
Port 2.
INa
G
33
2-Wlfe HS
3-Wlre HS
Input lme to DO of Control RegISter 3.
OUTj
H
32
2-Wlfe HS
3-Wlre HS
Output lme from Dj of Control RegISter 3.
OE
(Output Enable)
31
2-Wlfe HS
3-Wlfe HS
Input, active Low. When Low enables bus dnvers.
When HIgh, floats bus drIvers at hIgh Impedance.
OUT3
30
2-Wlre HS
3-Wlre HS
Output lme from D3 of Control regISter 3.
DO-D7
(Data)
I
--------«--;T~O:CP~u~»)------
\J
cs
R/W
writing a 0 to it) can the other command bits
be programmed. This action is true for both
sides of the FlO when programmed as a CPU
interface.
For proper system control, when Port I is
reset, Port 2 is also reset. In addition, all Port
2's outputs are floating and all inputs are
ignored. To initiate the data transfer, Port 2
must be enabled by Port 1. The Port 2 CPU
can determine when it is enabled by reading
Control register 0, which reads "floating" data
bus if not enabled and "OIH" if enabled.
OJ
\ ______
\~_ _--J!
Figure 6. Z-BUS Read Cycle Timing
ADO-AD7
Rlw
----«
A~~rroSS H~
___DA_TA_F_R_OM_C_P_U__---J)~---
c
\
\I...-_ _....J!
Figure 7. Z-BUS Write Cycle Timing
200
2020-004, 005
CPU
Interfaces
(Continued)
registers except the FIFO buffer' are two-step
operations, described as follows (Figure 8).
First, write the address (C/lS = 1) of the register
to be accessed into the Pointer Register (State
0); second, read or write (C/l) = 1) to the
register pointed at previously (State 1). Continuous status monitoring can be performed in
State 1 by continuous Control Read operations
(C/l)= 1).
RD OR WR
Figure 8. Register Access in Non-Z-BUS Mode
IThe FIFO buffer can also be accessed by this two-step operahon.
C/D===><_ _ _ _ _ _ _C
DO_D7------------------------------~(--;TO~C;PU~>______
\~
____________~r_
\'----_......./
Figure 9. Non-Z-BUS Read Cycle Timing
C/D
x
X
-----'
)
(
DO-D7----{==~~==>___-FROM CPU
\
/
\
/
Figure 10. Non-Z-BUS Write Cycle Timing
WAIT
Operation
Interrupt
Operation
2020-006. 007. 008
When data is output by the CPU, the
REQ/WT (WAIT) pin is active (Low) only when
the FIFO buffer is full, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not full.
When data is input by the CPU, the
REQ/WT pin becomes active (Low) only when
the FIFO buffer is empty, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not empty.
The FlO supports Zilog's prioritized daisy
chain interrupt protocol for both Z-BUS and
non-Z-BUS operating modes (for more details
refer to the Zilog Z-BU$ Summary).
Each side of the FlO has seven sources of
interrupt. The priorities of these devices are
fixed in the following order (highest to lowest):
Mailbox Message, Change in Data Direction,
Pattern Match, Status Match, Overflow/
Underflow Error, Buffer Full, and Buffer
Empty. Each interrupt source has three bits
that control how it generates the interrupt.
These bits are Interrupt Pending (IP),
Interrupt Enable (IE), and Interrupt Under
Service (IUS).
In addition, each side of the FlO has an
interrupt vector and four bits controlling the
FlO interrupt logic. These bits are Vector
201
Interrupt
Operation
(Continued)
Includes Status (VIS), Master Interrupt Enable
(MIE), Disable Lower Chain (DLC), and No
Vector (NV).
A typical Interrupt Acknowledge cycle for
Z-BUS operation is shown in Figure 11 and for
non-Z-BUS operation in Figure 12. The only
difference is that in Z-BUS mode, INTACK is
latched by AS, and in non-Z-BUS mode
INTACK is not latched.
When MIE = 1, reading the vector always
includes status, independent of the state of the
ADO-AD7~
VIS bit. In this way, when VIS = 0, all information can be obtained with one additional
read, thus conserving vector space. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified.
In non-Z-BUS mode, IPs do not get set while
in State 1. Therefore, in order to minimize
interrupt latency, the FlO should be left in
State O.
(
VECTOR
>---
lEI _ _....J/
INT
/
-------~
Figure 11. Z-BUS Interrupt Acknowledge Cycle
DO-D7 - - - - - - - - - - - - {
INYACK \ \ ._ _ _ _ _ _
~-------II
\I...... _ _~I
lEI _ _ _....J/
INT
_ _ _ _ _ _- - - J/
Figure 12. Non-Z-BUS Interrupt Acknowledge Cycle
CPU to CPU
Operation
202
DMA Operation. The FlO is particularly well
suited to work with a DMA in both Z-BUS and
non-Z-BUS modes. A data transfer between the
FlO and system memory can take place during
every machine cycle on both sides of the FlO
simultaneously.
In Z-BUS mode, the DMASTB pin (DMA
Strobe) is used to read or write into the FIFO
buffer. The R/W (Read/Write) and DS (Data
Strobe) signals are ignored by the FlO;
however, the CS (Chip Select) signal is not
ignored and therefore must be kept invalid.
Figures 13 and 14 show typical timing.
In Non-Z-BUS mode, the DACK pin (DMA
Acknowledge) is used to tell the FlO that its
DMA request is granted. After DACK goes
Low, every read or write to the FlO goes into
the FIFO buffer. Figures 15 and 16 show
typical timing.
2020·009,
aI a
CPU to CPu
Operation
OATA FROM FlO TO MEMORY
(Continued)
\\-__---11
RlYi
\'--___.....IrFigure 13. Z-BUS flO to Memory Data Transaction
AJD BUS
DATA FROM MEMORY TO FlO
\'-----~;Riw
\'--_----'1
Figure 14. Z-BUS Memory to FlO Data Transaction
ADDRESSES
===><_____M_EM_O_R_Y_A_D_DR_E_S_S_O_FW__RI_TE____-J)(~_____________________
D:~~
________~~(,D:A;'TA~F;'R~O:M~F~'O~T~O~M;'E~M~O;RY~}------(~____________--J}--
MEMORY
WRITE
110
READ
OACK~~
__________________________________________________
Figure 15. Non-Z-BUS FlO to Memory Transaction
ADDRESSES
==x
MEMORY ADDRESS OF READ
DABTUAS _...:______
MEMORY~
READ
X'-_________________________
-«(-:JD~A~TA~FR~D~MC"'».--------~<~~~~~~~~~~~~~)----MEMORY TO FlO
,
~
•
/
\~.__________-J.
\I--_--JI
\'--_.....11
DACK ~\._________________________________________________
Figure 16. Non-Z-BUS Memory to FlO Dala Transaction
2020·011,012,013,014
203
CPU to CPU
Operation
(Continued)
The FlO provides a special mode to enhance
its DMA transfer capability. When data is
written into the FIFO buffer, the REQ/WT
(REQUEST) pin is active (Low) until the FIFO
buffer is full. It then goes inactive and stays
inactive until the number of bytes in the FIFO
buffer is equal to the value programmed into
the Byte Count Comparison register. Then the
REQUEST signal goes active and the sequence
starts over again (Figure 17).
When data is read from the FlO, the
REQ/WT pin (REQUEST) is inactive until the
number of bytes in the FIFO buffer is equal to
the value programmed in the Byte Count Comparison register. The REQUEST signal then
goes active and stays active until the FIFO buffer is empty. When empty, REQUEST goes
inactive and the sequence starts over again
(Figure 18).
REO
G)
ACTIVE --''-+---,------,0
INACTIVE
ACTIVE
o
CD
-'''-f---+....;;..-......
f-----I_....NUMBEA OF BYTES IN FIFO
EMPTY
INACTIVE
FULL
-+_____---,.._
o
G)
G)
....:::+-----i
.....---+=-.,----FJLl
EMPTY
NUMBER IN BYTE COUNT COMPARISON REGISTER
NUMBER IN BYTe COUNT COMPARISON REGISTER
NOTES:
I. FIFO empty.
2. REQUEST enabled, FlO requests DMA transfer.
NOTES:
I. FIFO empty.
2. CPU/DMA hIls FIFO buffer from the oppoSIte port.
3. DMA transfers data 1Oto the FLO.
4, FIFO full, REQUEST maclive.
5. The FIFO emptIes from the OppOSIte port until the number
of bytes 10 the FIFO buffer IS the same as the number programmed 10 the Byte Count Comparison regIster.
3. Number of bytes 10 FIFO buffer IS the same as the number
of bytes programmed In the Byte Count Companson register.
4 REQUEST goes achve.
5. DMA transfers data out of FIFO untillt is empty.
Figure 17. Byte Count Control: Write to FlO
Figure 18. Byte Count Control: Read from FlO
Message Registers. Two CPUs can communicate through a dedicated "mailbox" register
without involving the 128 x 8 bit FIFO buffer
(Figure 19). This mailbox approach is useful
for transferring contr;1 parameters between
the interfacing devices on either side of the
FlO without using the FIFO buffer. For
example, when Port l's CPU writes to the
Message Out register, Port 2's message IP is
set. If interrupts are enabled, Port 2's CPU is
PORT 1
MESSAGE OUT
REGISTER
ADDRESS
<
interrupted. Port 2's message IP status is
readable from the Port 1 side. When Port 2's
CPU reads the data from its Message In register, the Port 2 IP is cleared. Thus, Port l's
CPU can read when the message has been
read and can now send another message or
follow whatever protocol that is set up between
the two CPU's. The same transfer can also be
made from Port 2's CPU to Port l's CPU.
>
MESSAGE
"C"
L-_ _ _ _---'
0"
REGISTER
REGISTER
PORT 1
TO
-PORT 2
po RT
1
MESS AGE IN
REG ISTER
REGISTER
ADDRESS
"B"
1-----,
PORT 2
MESSAGE IN
REGISTER
MESSAGE
REGISTER
-
PORT 2
TO
REGISTER
ADDRESS
"8"
-
PORT 1
NOTE: Usable only for CPU/CPU mterface.
Figure 19. Message Register Operation
204
2020 015,016,017
0
CPU to CPU
Operation
(Continued)
CLEAR (Empty) FIFO Operation. The CLEAR
FIFO bit (active Low) clears the FIFO buffer of
data. Writing a 0 to this bit empties the FIFO
buffer, inactivates the REQUEST line, and
disables the handshake (if programmed). The
CLEAR bit does not affect any control or data
register. To remove the CLEAR state, write a 1
to the CLEAR bIt.
In CPU/CPU mode, under program control,
only one of the ports can empty the FIFO by
writing to its Control Register 3, bit 6. The
Port 1 CPU must program bit 7 in Control
Register 3 to determine which port controls the
CLEAR FIFO operation (0 = Port 1 control;
1 = Port 2 control).
Direction of Data Transfer Operation. The
Data Direction bit controls the direction of data
transfer in the FIFO buffer. The Data Direction
bit is defined as 0 = output from CPU and
1 = input to CPU. This bit reads correctly
when read by either port's CPU. For example,
if Port l's CPU reads a 0 (CPU output) in its
Data Direction bit, then Port 2's CPU reads a 1
(input to CPU) in its Data Direction bit.
In CPU/CPU mode, under program control,
only one of the ports can control the direction
of data transfer. The Port 1 CPU must program
bit 5 in Control Register 3 to determine which
port controls the data direction (0 = Port 1
control; 1 = Port 2 control). Figure 20 shows
FlO data transfer options.
N
• I
:3
0
(PROGRAM REGISTERS FOR OPERATING MODE,
PORT 2 CONFIGURATION, DATA TRANSFER CONTROL, ETC)
PORT 1 (CPU)
PORT 2 (CPU)
PORT 2(110)
(aMA OR INTERRUPT·
DRIVEN TRANSFERS, AS
FOR PORT 1)
TRANSFERS DATA BYTE·
AT·A·TlME UNTIL
FIFO BUFFER IS
I
I
I
Full OR Empty
t
t
EXCHANGE BYTES
VIA MESSAGE REGISTER
TERMINATES ON ANY
OF THESE CONDITIONS:
-DMA BLOCK LENGTH REGISTER
TERMINATES ON ANY
OF THESE CONDITIONS:
=0
·CPU COMPLETES BUFFER DUMP
·FIO PATTERN MATCH INTERRUPT
·BYTE COUNT DISABLES REQ
·FIO PATIERN MATCH INTERRUPT
-FlO BYTE COUNT INTERRUPT
-FlO Full I Empty INTERRUPT
I
I
l
I
"
)
//
""" '-
Y
/'
/~
\
I
Y
I
I
I
I
I
I
I
I
I
I
I
I
EXCHANGE BYTES
VIA MESSAGE REGISTERS
----.--
..... - - - -
CONTINUE OR REPROGRAM PORT REGISTERS WITH NEW BLOCKS OF CONTROL BYTES.
Figure 20. FlO Dala Transfer Options
2020·018
205
I
,
CPU to I/O
Operation
(Continued)
DATA IN,=:>(
X
1
VALID DATA
\
ACKIN
X
X
L-I
VALID DATA
RFD
Figure 21. Interlocked Handshake Timing (Input) Port 2 Side Only
DATA OUT
,=:>(__
V_A_L1_D_DA_T_A
_JX...___JX
XI.._____
VALID DATA
\1...._-J1
\1...._ _ 1
-1
Figure 22. Interlocked Handshake Timing (Output) Port 2 Side Only
_DA_T_A_~X:==X
DATA IN ==:X,-_V_A_L1_D
RFD
OUT
-..I
\ ....._ _ _.....11
\'-_----1
DAV
IN
VALID DATA
X'-_____
\....----
'----I
DAC
OUT _ _ _ _ _ _ _ _ _ _J
Figure 23. Input (Acceptor) Timing IEEE·488 HS Port: Port 2 Side Only
DATA OUT
DO"u~
===::x
VALID DATA
X'-______JX
VALID DATA
X'--____
1
\
DAC
IN _ _ _ _ _ _ _ _ _J
\I....--_ _-JI
,'-----
Figure 24. Output (Source) Timing IEEE·488 HS Port: Port 2 Side Only
2020-019,020,021,022
207
Programming
The programming of the FlO is greatly
simplified by the efficient grouping of the
various operation modes in the control
registers. Since all of the control registers are
read/write, the need for maintaining their
image in system memory is eliminated. Also,
the read/write feature of the registers aids in
system debugging.
Each side of the FlO has 16 registers. All 16
registers are used by the Port 1 side; Control
register 2 is not used on the Port 2 side. All
registers are addressable 0H through FH.
In the Z-BUS Low Byte mode, the FlO allows
two methods for register addressing under control of the Right Justify Address (RJA) bit in
Control register 0. When RJA = 0, address
bus bits 1-4 are used for register addressing
and bits 1, 5, 6, and 7 are ignored (Table 4).
When RJA = 1, bits 0-3 are used for the
register addresses, and bits 4-7 are ignored.
Control Registers. These four registers speCify
FlO operation. The Port 2 side control
NonZ-BUS
°
Interrupt Status Registers. These four
registers control and monitor the priority
interrupt functions for the FlO.
Interrupt Vector Register. This register stores
the interrupt service routine address. This vector is placed on Do-D7 when IUS is set by the
Interrupt Acknowledge signal from the CPU.
When bit 4 (Vector Includes Status) is set in
Control Register 0, the reason for the interrupt
is encoded within the vector address in bits 1,
2, and 3. If bit 5 is set in Control register 0, no
vector is output by the FlO during an Interrupt
Acknowledge cycle. However, IUS is set as
usual.
D7-D4
D3
A3
A2
Al
Ao
A~-ADs
A~-AD4
AD4
AD3
AD3
AD2
AD2
ADI
ADI
ADo
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
x
x
a
x
Z-BUS High
{ RJA=O
Z-BUS Low RJA= I
registers operate only if the Port 2 device is a
CPU. The Port 2 CPU can control interface
operations, including data direction, only
when enabled by the setting of bit in the Port
1 side of Control Register 2. A I in bit I of the
same register enables the handshake logic.
D2
DI
Do
ADo
Description
Control RegIster
a
x
x
Control RegIster I
Interrupt Status RegIster 0
x
Interrupt Status RegIster I
x
Interrupt Status RegIster 2
x
Interrupt Status RegIster 3
x
Interrupt Vector RegIster
x
Byte Count RegIster
x
Byte Count ComparIson
x
Register
Control RegIster 2·
x
Control RegIster 3
x
Message Out RegIster
x
Message In RegIster
x
Pattern Match RegIster
x
Pattern Mask RegIster
x
Data Buffer RegIster
x
a
x
a
x
x
x
a
a
a
a
x = Don't Care
"Register IS only on Port I sIde
Table 4. FlO Register Address Summary
208
x
a
a
a
a
a
x
I
x
a
x
I
I
x
a
a
a
x
x
a
x
x
Programming Byte Count Compare Register. This register
(Continued)
contains a value compared with the byte count
in the Byte Count register. If the Byte Count
Compare interrupt is enabled, an interrupt will
occur upon compare.
Message Out Register. Either CPU can place
a message in its Message Out register. If the
opposite side Message register interrupt is
enabled, the receiving side CPU will receive
an interrupt request, advising that a message
is present in its Message In register. Bit 5 in
Control Register 1 on the initiating side is set
when a message is written. It is cleared when
the message is read by the receiving CPU.
Message In Register. This register receives a
message placed in the Message Out register by
the opposite side CPU.
Pattern Match Register. This register contains
a bit pattern matched against the byte in the
Data Buffer register. When these patterns
match, a Pattern Match interrupt will be
generated, if previously enabled.
Pattern Mask Register. The Pattern Mask
register may be programmed with a bit pattern
mask that limits comparable bits in the Pattern
Match register to non-masked bits (l = mask).
Data Buffer Register. This register contains
the data to be read from or written to the
FIFO buffer.
Byte Count Register. This is a read-only
register, containing the byte count for the
FIFO buffer. The byte count is derived by subtracting the number of bytes read from the buffer from the number of bytes written into the
buffer. The count is "frozen" for an accurate
reading by setting bit 6 (Freeze Status register)
in Control Register 1. This bit is cleared when
the Byte Count register read is completed.
Z-BUS
1/----, TO
COMM.
LINE
MASTER
CPU
NOTES:
1.
2.
3.
4.
5.
Data from master CPU - Z-FIO Port 2.
Z-FIO Port 1 -DCP.
DCP -RAM.
RAM -Z-SCC.
Z-SCC - data camm. lme loop.
Figure 25. Typical Application: Node Controller
2020-033
209
Registers
Control Register 0
Address: 0000
(ReadlWrite)
Control Register 2*
Address: 100 1
(ReadlWrite)
",. 'I 'I "'i" '~ ;;,:::" '''"'"'.'
g1
1
~~
:
Z BUS CPU
Z BUS
- NpN
=
3·WIRE
HS rfcjU
"""i"""""
~
.
'THIS
}
O'S
PROQRAMS
PORT 2 MODE
::: INTERLOCKED H
F:~~1~6~ATREADS
2 SIDE
: : PORT 2 SIDE ENABLED
_ PORT 2 SIDE ENABL
BITS 2-7 NOT
ALL
MUST BE
PRO~~;~ME
E HANDSHAKE
DO
1 ::: VECTOR INCLUDE
S
1 "" NO VECTOR
5 STATUS (VIS)
1 ::: DISABLE L
.:~~~ ~~rLDYEFROM
1 =
ON INTERRUPT (NV)
INTERRUP~SW:R
NABLEO
DAISY (MIE)
CHAIN (DLC)
Control Register 3
Address: 1010
(ReadlWrite)
Control Register 1
Address: 000 1
(ReadlWrite)
0
1 ,1
0
0
1
~'Iii~'
~'I
0
D
~'I
~'
L...:=
0
,
I0,1 0 1
i l lI i
§
' I Dl1
'
PORT 2 SIDE
NOT USED
(~~UTPUT
PORT 2 SIDE
0
m1
'
lI
11
D
DL.;'::
;'
REOUEST/WAIT ENABLED
DATA
= REaUEST
1=
1 ::: START DMA
STOP DMA
1
1
= MESSAGE
O~::YTE COUNT
______
DlREC;~UTPUT LINE (PIN
30)-·
O=PORT 1 FROM CPU
1 = PORT 2 SIDE
SIDE CONTROLS
CONTROLS DATA DIRECTION
0-
TTERN MATCH
- CLEAR FIFO BUFFER
= M ESSAGE MAILBOX
AEGISTE
MAILBD
R UNDER SERV
1 = FREEZE STATUS
E (PIN 33)"
LINE (PIN 32)0.
5T BE PROGRAMMED 0)
~~~J~pTu~O c~~IT
- WAIT
1
'READ ONLY BITS
PORT 2 SIDE-INPUT LIN '
X REGISTER FULL'
,~~~~yONLY BITS
O=PORT 1 SIDE
•
ICE-
1 = PORT 2 SIDE
gg~;=OLS CLEAR
WHEN PORT 2 IS AN 110 PORT
NOT_ USED (MUS T BE PROGRAMMED
REGISTER COUNT
0)
OLS
Figure 26, Control Registers
Interrupt
Ad St a t us Register 0
dress: 0010
(ReadlWrite)
'"I'I'i" "'""t!:! ==I.OO'M"""
I
MESSAG:
I
::~ERRUPT PENDING (IP)
EARUPT EN
FOLLOWIN~R~
o
IUS, IE, AND IP
THE
MESSAGE INTERRUPT U ABLE (IE)
WRITTEN USING
NDER SERVICE (IUS)
NULL CODE
OMMAND.
'
CLEAR IP & IUS
o
SET IUS
Figure 27, Interrupt Status Registers
210
2020-023
Registers
(Continued)
Interrupt Status Register 1
Address: 00 11
(Reacl/Write)
DATA DIRECTION CHANGE INTERRUPT
UNDER SERVICE (IUS)
iJ I
I
ENABLE (IE)
I
I
L
I
DATA DIRECTION CHANGE INTERRUPT
PENDING UP)
t
,
DATA DIRECTION CHANGE INTERRUPT
IIl--L
=
1
PATTERN MATCH FlAG'
PATTERN MATCH INTERRUPT PENDING UP)
PATTERN MATCH INTERRUPT ENABLED (IE)
I
I
I
PATTERN MATCH INTERRUPT
I
I
UNDER SERVICE (IUS)
' - - - - _ NOT USED
(MUST BE PROGRAMMED 0)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND.
IUS, IE, AND IP ARE WRITTEN USING
NULL coDe
THE FOLLOWING COMMAND.
CLEAR lP & IUS
0
0
1
seT IUS
a
1
0
CLEAR IUS
0
1
1
SET IP
1
0
0
CLEAR IP
1
a
1
SET IE
1
1
a
CLEAR IE
1
1
1
o
a
0
NULL CODe
o
o
a
0
1
CLEAR IP & IUS
1
0
SET IUS
1
1
CLEAR IUS
1
a
0
SET IP
1
0
1
CLEAR IP
1
1
a
seT IE
1
1
1
CLEAR IE
*READ·QNLY BITS
Interrupt Status Register 2
Address: 0100
(Reacl/Write)
BYTE COUNT COMPARE INTERRUPT
UNDER SERVICE (IUS)
BYTE COUNT COMPARE INTERRUPT
ENABLE (IE)
BYTE COUNT COMPARE INTERRUPT
PENDING (IP)
jJ I
I
I
~~
L
L UNDERFLOW ERROR'
I
I
I
I
I
I
ERROR INTERRUPT PENDING (ID)
ERROR INTERRUPT ENABLED (IE)
I
I
ERROR INTERRUPT UNDER SERVICE (IUS)
I
I
OVERFLOW ERROR-
0
0
NULL CODE
0
1
CLEAR IP & IUS
1
0
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND.
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND.
NULL CODE
0
0
0
CLEAR IP & IUS
0
0
1
SET IUS
0
1
0
CLEAR IUS
0
1
1
o
o
o
o
1
1
CLEAR IUS
SETIP100
1
0
0
SET IP
CLEAR IP
SET IE
CLEAR IE
1
SET IUS
0
1
1
0
1
CLEAR IP
11
0
1
1
0
SET IE
1
1
1
1
1
CLEAR IE
1
·READ ONLY BITS
Interrupt Status Register 3
Address: 0101
(ReacI/W rite)
FULL INTERRUPT UNDER SERVICE (IUSI
FULL INTERRUPT ENABLE (IE)
FULL INTERRUPT PENDING (IP)
~ I
~
I
I
I
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND.
I
~
I
L BUFFER EMPTY'
~ EMPTY INTERRUPT PENDING (IP)
I
::
EMPTY INTERRUPT ENABLE (IE)
EMPTY INTERRUPT UNDER SERVICE (IUS)
BUFFER FULL·
NULL CODE
0
0
0
CLEAR IP & IUS
0
0
1
SET IUS
0
1
0
o
0
0
NULL CODE
CLEAR IUS
0
1
1
o
0
1
CLf'AR IP & IUS
SETIP100
1
0
SET IUS
1
o
o
1
1
CLEAR IUS
0
0
SET IP
1
CLEAR IP
CLEAR IP
1
0
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND·
SET IE
1
1
0
1
CLEAR IE
1
1
1
1
0
1
1
0
SET IE
,
1
1
CLEAR IE
·READ-ONLY BITS
Figure 27, Interrupt Status Registers (Contmued)
2020·024
211
Registers
(Continued)
Interrupt Vector Register
Address: 0110
(ReadIWrite)
Byte Count Register
Address: 0111
I~I~I~I~I~I~I~I~I
IIIII"
I I I I
I
REFLECTS NUMBER OF BYTES IN BUFFER
NO INTERRUPTS PENDING
Figure 28. Byte Count Register
VECTOR STATUS
1
BUFFER EMPTY
BUFFER FULL
o
o
o
OVER/UNDERFlOW ERROR
BYTE COUNT MATCH
0
0
0
1
1
0
1
1
o
0
PATTERN MATCH
1
0
1
DATA DIRECTION CHANGE
1
1
0
MAILBOX MESSAGE
1
1
1
Figure 29. Interrupt Vector Register
Pattern Match Register
Address: 1011
(ReadlWrite)
Pattern Mask Register
Address: 1110
(ReadlWrite)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
I I I I I II I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER
I II I I I I I
IF SET, BITS 0-7 MASK BITS 0·7
IN PATTERN MATCH REGISTER.
MATCH OCCURS WHEN ALL
NON·MASKED BITS AGREE.
Figure 30. Pattern Match Register
Figure 31. Pattern Mask Register
Data Buffer Register
Address: IIII
(ReadlWrite)
Byte Count Comparison Register
Address: 1000
(ReadlWrite)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
IIIII
II
I
CONTAINS THE BYTE TRANSFERRED
TO OR FROM FIFO BUFFER RAM
IIIII
II
I
CONTAINS VALUE COMPARED TO BYTE COUNT
REGISTER TO ISSUE INTERRUPTS ON MATCH
(BIT 7 ALWAYS 0)
Figure 32. Data Buffer Register
Figure 33. Byte Count Comparison Register
Message Out Register
Address: 1011
(ReadlWrite)
Message In Register
Address: 1100
(Read Only)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
I I I I I II I
212
"
I I I I "
STORES MESSAGE SENT TO MESSAGE
IN REGISTER ON OPPOSITE PORT OF Fro
STORES MESSAGE RECEIVED FROM MESSAGE
Figure 34. Message Out Register
Figure 35. Message In Register
OUT REGISTER ON OPPOSITE PORT OF CPU
2020-025,026,027,028,029,030,031, 032
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature .................
to +70 C
oac
a
Storage Temperature ........ -65 a C to + 150 a C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those hsted under Absolute MaxImum Ratmgs may cause permanent damage to the deVIce.
ThIS IS a stress rahng only; operahon of the devIce at any
condItion above those mdicated m the operahonal sechons
of these specIhcatIons IS not ImplIed. Exposure to absolute
maXImum rahng condItions for extended penods may affect
device rehablhty.
•
+4.75 V S Vee S +5.25 V
• GND = 0 V
• TA as specified in Ordering Information
+5V
+5V
FROM OUTPUT
UNDER TEST
dr
22K
IN
•
IIJ
...o
SOPF
Figure 37. Open-Drain Test Load
Figure 3S. Standard Test Load
DC
Characteristics
Symbol
Parameter
VIH
Input High Voltage
VIL
VOH
Input Low Voltage
Output High Voltage
Output Low Voltage
VOL
IlL
h
ICC
Min
Max
Unit
2.0
Vcc +0.3
0.8
V
V
V
V
V
I'A
IOH =
IOL =
IOL =
0.4 s
~
0.4 s VOUT
-0.3
2.4
0.4
0.5
± 10.0
± 10.0
250
Input Leakage
Output Leakage
Vee Supply Current
Condition
-250 ~
+2.0 mA
+3.2 mA
VIN S +2.4V
S
+2.4V
mA
Vee= 5 V ± 5% unless otherwise speclhed, over specliled temperature range.
Capacitance
Symbol
Max
Unit
CIIO
Input Capacitance
Output Capacitance
Bidirectional Capacitance
10
15
20
pF
pF
pF
tr
If
Any Input Rise Time
Any Input Fall Time
100
100
ns
ns
CIN
C OUT
Inputs
f
8085·0209. 0002
=
Parameter
Min
Test Condition
Unmeasured Pins
Returned to Ground
1 MHz, over specliIed temperature range.
213
Z-BUS CPU
Number Symbol
Interface
Timing
Parameter
Min
TwAS
AS Low Width
2
TsA(AS)
3
ThA(AS)
4
TsCSO(AS)
CS to AS I Setup Time
Units
ns
Address to AS I Setup Time
10
ns
Address to AS I Hold Time
50
ns
0
5 -ThCSO(AS) - - CS to AS I Hold Time
6
TdAS(DS)
AS I to DS I Delay
7
TsA(DS)
Address to DS I
8
TsRWR(DS)
R!W (Read) to ITs
9
TsRWW(DS)
lO-TwDS
Max
70
60
ns
ns--l-
60
ns
120
ns
I Setup Time
100
ns
RIW (Write) to DS I Setup Time
0
ns
390
ns
30
ns
DS Low Width
11
TsDW(DSf)
Write Data to DS I Setup Time
12
TdDS(DRV)
DS (Read) I to Address Data Bus Driven
13
TdDSf(DR)
DS I to Read Data Valid Delay
14
ThDW(DS)
Write Data to DS I Hold Time
0
ns
255
30
16
TdDS(DRz)
17
ThRW(DS)
r to Read Data Not Valid Delay
DS r to Read Data Float Delay
RlW to DS I Hold Time
18
TdDS(AS)
DS I to AS I Delay
19
Trc
Valid Access Recovery Time
15 -TdDSr(DR)-- DS
Alii
READ
R/W
WRITE
3. This
IS
ns
ns
0
ns
70
ns
60
ns
50
ns
1000
ns
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
transactions.
2. Float delay IS measured to the hme when the output has
changed 0.5 V from steady state wIth mInImUm ae load and
maXImum de load.
Notes
the delay from DS of one CIa access to
2
3
iSS of another
FlO access (eIther read or wrIte),
----t+-J
----+ir-----+-:--+--------+4
--------:----
ADO_AD .. ] :I:DRESS
WRITE
READ
FID
214
-----------r-~~--)l~~~~~r_---------
2020·034
Z-BUS CPU
Interrupt
Acknowledge
Timing
Number Symbol
Parameter
Min
20
TsIA(AS)
INTACK to AS t Setup Time
21
ThIA(AS)
INT ACK to AS t Hold Time
22
TdDSA(DR)
DS (Acknowledge)
23
TwDSA
DS (Acknowledge) Low Width
24-TdAS(lEO)--AS
j
to IEO
j
j
Max
250
to Read Data Valid Delay
Units
Notes
ns
0
ns
360
475
ns
ns
350-ns--4-
Delay (lNTACK Cycle)
25
TdIEl(IEO)
IEI to IEO Delay
26
TsIEl(DSA)
IEI to DS (Acknowledge)
j
Setup Time
100
ns
27
ThIEl(DSA)
IEI to DS (Acknowledge)
j
Hold Time
200
ns
28
TdDS(INT)
DS (lNTACK Cycle) to INT Delay
ns
29
TdDCST
Interrupt Daisy Chain Settle Time
ns
150
ns
4
4
4
NOTES:
4. The parameters for the deVices in any particular da~ ch~
must meet the followmg constramt: The delay from AS to DS
must be greater than the sum of TdAS(!EO) for the hIghest
ADO-AD7
priority peripheral, TsIE!(DSA) for the lowest priority
penpheral, and TdIEI(IEO) for each peripheral separating them
in the cham.
UNDEFINED
lEI
lEO
2020·035
215
Z-BUS
Number Symbol
Interrupt
Timing
Parameter
TdMW(INT)
30
Min
Max
Units
Notes
AS Cycles 5
+ns
TdDC(INT)
31
Data Direction Change to INT Delay
AS Cycles 6
+ns
TdPMW(INT)
32
AS Cycles
Pattern Match to INT Delay (Write Case)
+ns
TdPMR(INT)
Pattern Match (Read Case) to INT Delay
33
AS Cycles
+ns
34--TdSC(INT)--Status Compare to INT D e l a y - - - - - - - - - I - - A S Cycles-6+ns
TdER(INT)
35
Error to INT Delay
AS Cycles
+ns
Empty to INT Delay
TdEM(INT)
AS Cycles 6
36
+ns
Full to INT Delay
TdFL(INT)
37
AS Cycles 6
+ns
TdAS(INT)
AS to INT Delay
38
AS Cycles
+ns
NOTES'
5. Wrlte
6
IS
Message Write to INT Delay
from the other SIde of FlO.
Wflte can
be from either
SIde, dependmg on programmmg
of FlO
216
2020·036
Z-BUS
Request/Wait
Timing
Number Symbol
Parameter
Min
Max
Units
TdDS(WAIT)
DS I to WAIT I Delay
ns
2
TdDSI(WAIT)
DSI I to WAIT t Delay
ns
3
TdACK(WAIT)
ACKIN I to WAIT t Delay
ns
Notes
4-TdDS(REQ)-- DS I to REQ t D e l a y - - - - - - - - - - - - - - n s - - -
5
6
TdDMA(REQ)
DMASTB I to REQ t Delay
ns
TdDSI(REQ)
DSI t to REQ I Delay
ns
7
TdACK(REQ)
ACKIN I to REQ I Delay
ns
8-TdSU(DMA)- Data Setup Time to D M A S T B - - - - - - - 2 0 0 - - - - n s - - - -
9
TdH(DMA)
Data Hold Time to DMASTB
10
TdDMA(DR)
DMASTB I to Valid Data
11
TdDMA(DRH)
DMASTB t to Data Not Valid
12
TdDMA(DR2)
DMASTB t to Data Bus Float
30
ns
ns
o
ns
70
ns
Max
Units
NOTES:
1. The delay IS Irom DAV I lor 3· Wire Input Handshake. The
delay is from DAC t for 3·Wlre Output Handshake.
os
READIWRITE
DATA
BUFFER
BY OTHER SIDE
REGISTER
DSI
WRITE/READ
BY OTHER SIDE
DATA
BUFFER
REGISTER
INPUTI
OUTPUT
PORT
REQ
DATA
DATA
FROM
BUFFER
FlO
WRITE
TO
FlO
Z-BUS Reset
IN/OUT
REGISTER
DATA
BUFFER
REGISTER
Number Symbol
Timing
Parameter
TdDSQ(AS)
Delay from DS t to AS I for No Reset
2
TdASQ(DS)
Delay for AS t to DS I for No Reset
3
Tw(AS+DS)
Mmimum Width of AS and DS Both Low for
Reset
Min
40
ns
50
500
ns
Notes
ns
NOTES:
1. Internal ClrcuItry allows for the reset provided by the Z8
(00 held Low whIle AS pulses) to be sulhclent.
2020·037, 038
217
Non-Z-BUS
CPU Interface
Timing
Number Symbol
Min
Parameter
Max
Units
1
TsA(RD)
Address Setup to RD I
80
ns
2
TsA(WR)
Address Setup to WR I
80
ns
a
a
a
a
a
a
ns
ThA(RD)
Address Hold Time to RD 1
3
4 -ThA(WR) - - - Address Hold Time to WR f
5
TsCEI(RD)
CE Low Setup Time to RD
6
TsCEI(WR)
CE Low Setup Time to WR
ThCEI(RD)
CE Low Hold Time to RD
7
8 -ThCEI(WR) - - CE Low Hold Time to WR
ns
ns
ns
ns
ns
9
TsCEh(RD)
CE High Setup Time to RD
100
ns
10
TsCEh(WR)
CE High Setup Time to WR
100
ns
II
TwRDI
RD Low WIdth
400
ns
12 -TdRD(DRA) - - RD I to Read Data ActIve Delay
13
TdRDf(DR)
RD I to Valid Data Delay
14
TdRDr(DR)
RD 1 to Read Data Not Valid Delay
TdRD(DRz)
RD 1 to Data Bus Float
15
16-TwWRI--- WR Low Width
17
TsDW(WR)
Data Setup Time to WR
18
ThDW(WR)
Data Hold Time to WR
19
Trc
Valid Access Recovery Time
Notes
a
ns
300
ns
70
ns
ns
a
400
ns
a
a
ns
1000
ns
2
ns
3
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
3. Ih.!.s IS the delay from RD f or WR t of one FlO access to
RD I or WR I of another FlO access.
transactions.
2. Float delay Is measured to the hme the output has changed
0.5 V from steady state wIth mInImUm ae load and maxImum de load.
C/O
FI~~~~~ -----+-~,...-+~~..,.._.Jl\.,__.,_...",~*--f----
Do-D7
FlO WRITE _ _ _ _- - '
DATA VALID
Non-Z-BUS CPU Interface Timing
Non-Z-BUS Interface Timing
218
2020·039, 040
Non-Z-BUS
Interrupt
Acknowledge
Timing
Number Symbol
Units
Notes
20
TdlEI(lEO)
Parameter
lEI to lEO Delay
Min
150
Max
ns
4
21
TdI(lEO)
INTACK I to lEO I Delay
350
ns
4
22
TsIEI(RDA)
lEI Setup Time to RD (Acknowledge)
200
ns
4
23
TdRD(DR)
RD I to Vector Valid Delay
300
ns
24-TwRDl(IA)--Read Low Width (Interrupt Acknowledge)---400
ThIA(RD)
25
INTACK 1 to RD 1 Hold Time
30
ThlEI(RD)
lEI Hold Time to RD 1
26
100
ns
27
TdRD(lNT)
RD 1 to INT 1 Delay
ns
28
TdDCST
Interrupt Daisy Chain Settle Time
ns
NOTES:
4. The parameter for the devIces many parhcular dalsy chain
must meet the followmg constramt: The delay from INTACK 1
to RD I must be greater than the sum of TdINA(IEO) for the
ns
ns
4
highest pnonty penpheral, TsIEI(RD) for the lowest pnonty
perIpheral, and TdIEI(IEO) for each peripheral separatIng them
In
the chain.
N
INTACK
.:.:.
o
oo--------------t-----~I--~~~~[_~-----
DO-D1
--------------t-(~:HK:){~t)-----
lEI
lEO
INT
2020-041
219
Non-Z-BUS
Interrupt
Timing
Number Symbol
Min
Parameter
Max
Units
Notes
29
TdMW(INT)
Message Write to INT Delay
ns
5,6
30
TdDC(INT)
Data Direction Change to INT Delay
ns
5,7
31
TdPMW(INT)
Pattern Match (Write Case) to INT Delay
ns
5
32
TdPMR(INT)
Pattern Match (Read Case) to INT Delay
ns
5
ns--5,7-
33-TdSC(INT)--Status Compare to INT Delay
34
TdER(INT)
Error to INT Delay
ns
5,7
35
TdEM(INT)
Empty to INT Delay
ns
5,7
36
TdFL(INT)
Full to INT Delay
ns
5,7
37
TdSO(INT)
State 0 to INT Delay
ns
NOTES:
5. Delay number IS valId for State 0 only.
6. Wnte IS from other SIde of FlO.
MESSAGE
WRITE
WRITE
7. WrIte can be from eIther SIde, depending on programmmg of
FlO.
,
~
WR~·5
MESSAGE
REGISTER
r. .
I----®--
OUT
DATA
DIRECTION
CHANGE
WRITE
CONTROL
REGISTER J
WR,,6
/
REGISTER
PATTERN
MATCH
READ DATA
BUFFER
WR4,6
ERROR
WRITE DATA
BUFFER
Wfj'
EMPTY
WAITE DATA
REGISTER
WR,,8
BUFFER
REGISTER
FULL
ST1-STo
WRITE DATA
BUFFER
REGISTER
,
,
I---------®-----
WRITE DATA
BUFFER
REGISTER
COMPARE
,
I----@-------
RD4
REGISTER
STATUS
I----®-------
7
WiP
BUFFER
I---®-
7
I"
.
®
~
WR4,6
WR'- RD'
/
I--®----
7
.NT
220
2020-042
Non-Z-BUS
Request/Wait
Timing
Number Symbol
Parameter
1
TdRD(WT)
RD
2
TdRDl(WT)
RDI
3
TdACK(WT)
ACKIN
Min
Max
to WAIT Active
j
j
Notes
ns
to WAIT Inactive
j
Units
ns
ns
to WAIT Inactive
---4-TdRD(REQ)--RD j to REQ I n a c t i v e - - - - - - - - - - - - - - - ns
5
TdRDl(REQ)
RDI j to REQ Active
ns
6
TdACK(REQ)
ACKIN
7
TdDAC(RD)
DACK
j
j
to REQ Active
to RD
j
or WR
ns
ns
j
---8-TSU(WR)---Data Setup Time to W R - - - - - - - - - - - - - - - ns
9
Th(WR)
Data Hold Time to WR
10
TdDMA
RD I to Valid Data
11
TdDMA(DRH)
RD t to Data Not Valid
12
TdDMA(DRZ)
RD t to Data Bus Float
ns
0
70
ns
2
ns
2
ns
2
NOTES:
1. The delay IS from DAV I for 3-Wlre Input Handshake. The
delay 15 from DAC t for 3-Wue Input Handshake.
2. Only when DACK is achve.
N
•
'0:1
...
C
jjjj
READ/WRITE OF DATA
BUFFER REGISTER
RD,
WRITEJREAD OF DATA
BU':vE~T~EE~~~~: -~r---------+---J
ACKIN
INPUT/OUTPUT PORT
DATA FROM FlO
-l®
WR
~
--v-~9,.-------------------
FlO WRITE TO DATA
BUFFER REGISTER~ _ . '_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
2020-043
221
Non-Z-BUS
Reset
Timing
Number Symbol
Parameter
Min
100
100
500
L
2.
TdWR(RD)
Delay from WR I to RD I
TdRD(WR)
Delay from RD I to WR I
3.
TwRD+WR
Width of RD and WR, both Low for Reset
Max
Units
ns
ns
ns
,
'~
J
Port 2 Side
Operation
Number Symbol
Min
700
I.
TwCLR
Width of Clear to Reset FIFO
2.
TdOE(DO)
OE I to Data Bus Driven
3.
TdOE(DRZ)
OE t to Data Bus Float
CLEAR
INPUT
222...
Parameter
a
Max
Units
ns
ns
ns
~--0----Jt
2020-044, 045
FlO 2-Wire
Handshake
Timing
Number Symbol
2
Parameter
TsDl(ACK)
Data Input to ACKIN I to Setup Time
TdACKf(RFD)
ACKIN I to RFD I Delay
TdRFDr(ACK)
RFD t to ACKIN I Delay
3
4-TsDO(DAV)--Data Out to DAV I Setup Time
5
TdDAVf(ACK)
6
ThDO(ACK)
Data Out to ACKIN Hold Time
7
TdACK(DAV)
ACKIN I to DAV t Delay
DAV I to ACKIN I Delay
8-ThDI(RFD)--Data Input to RFD I Hold Time
Min
Max
Units
ns
0
ns
0
ns
25
ns
0
ns
ns
0
ns
0
ns
9
TdRFD£(ACK)
RFD I to ACKIN t Delay
0
ns
10
TdACKr(RFD)
ACKIN t (DAV t) to RFD t DelayInterlocked and 3- Wire Handshake
0
ns
11
TdDAVr(ACK)
DAV t to ACKIN t (RFD t)
0
ns
12
TdACKr(DAV)
ACKIN t to DAV I
0
ns
N
•
lit
...0
2-Wire Handshake (Port 2 Side Only) Output
2-Wire Handshake (Port 2 Side Only) Input
2020-046, 047
223
3-Wire
Handshake
Timing
Number Symbol
Parameter
Min
1
TsDI(DAV)
Data Input to DAV I Setup Time
2
TdDAVIf(RFD)
DAV I to RFD I Delay
3
TdDAVf(DAC)
DAV I to DAC 1 Delay
4-
ThDI(DAC) - - Data In to DAC 1 Hold Time
5
TdDACIr(DAV) DAC 1 to DAV 1 Delay
6
TdDAVIr(DAC)
DAV 1 to DAC I Delay
7
TdDAVIr(RFD)
DAV 1 to'RFD 1 Delay
8-TdRFDI(DAV)-RFD 1 to DAV I Delay
9
TsDO(DAC)
Max
Units
ns
0
0
ns
0
0
0
ns
0
0
Data Out to DAV I
ns
ns
ns
ns
ns
ns
TdDAVOf(RFD) DAV I to RFD I Delay
10
TdDAVOf(DAC) DAV I to DAC 1 Delay
11
12 -ThDO(DAC)-Data Out to DAC 1 Hold Time
TdDACOr(DAV) DAC 1 to DAV I Delay
13
0
0
14
TdDAVOr(DAC) DAV I to DAC I Delay
15
TdDAVOr(RFD) DAV I to RFD 1 Delay
0
0
ns
16
TdRFDO(DAV)
0
ns
RFD 1 to DAV I Delay
ns
ns
ns
ns
ns
DATA
DAY
INPUT
RFD
OUTPUT
DAC
OUTPUT _ _ _ _......:_ _
.-r
3-Wire Handshake Input
DATA
DAC
INPUT
RFD
INPUT
DAY
OUTPUT
3-Wlre Handshake Output
224
2020-049
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Temp
Speed
Description
Z8038
CE
4.0 MHz
Z-FIO (Z-BUS
compatible,
40-pin)
Z8538
CE
4.0 MHz
Z8538
Same as above
CS
DE
4.0 MHz
4.0 MHz
Z8038
Z8038
DS
4.0 MHz
4.0 MHz
Same as above
Same as above
Same as above
Z8538
Z8538
Z8538
4.0 MHz
4.0 MHz
4.0 MHz
Same as above
Same as above
Same as above
Same as above
Same as above
Z-FIO (Z-BUS
compahble,
40-pm)
Z8538
Z8538A
CS
DE
DS
PE
PS
CE
4.0 MHz
Z8038
Z8038
4.0 MHz
6.0 MHz
CS
DE
DS
PE
PS
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
Same as above
FlO (Universal,
40-pm)
Same as above
Same as above
Same as above
Same as above
Same as above
Z8038
Z8038A
Z8038A
Z8038A
Z8038A
Z8038A
Z8038A
PE
PS
CE
CS
DE
DS
PE
PS
4.0 MHz
6.0 MHz
6.0
6.0
6.0
6.0
6.0
MHz
MHz
MHz
MHz
MHz
Same
Same
Same
Same
Same
as
as
as
as
as
above
above
above
above
above
Z8538A
Z8538A
Z8538A
Z8538A
Z8538A
FlO (Universal,
40-pm)
N
...C•
IIJ
NOTES' C = CeramIC, D = CerdIp. P = Plashc, E = -40'C to +85'C, S = O'C to +70'C.
225
Z8060
Z8000™ FIFO Buffer Unit
and Z-FIO Expander
~
Zilog
Product
Brief
March 1981
Features
• Asynchronous, bidirectional hrst-in, first-out
buffer.
• Extends depth of Z-FIO without limit.
• 3-state data outputs.
• Empty and Full status pins are wire-ORed
among mulhple stages.
• 128 x 8 organization.
Description
The Z-FIFO first-in, first-out buffer unit is a
128 x 8-bit memory with bidirectional data
transfer capability and handshake logic. Its
structure is similar to that of other FIFOs that
are commonly available, such as the AM2812
and the 3351. The handshake logic used is
compatible with that of the Z8, the Z-CIO, and
Z-FIO. Z-FIFO buffers can be cascaded, end to
end, without limit, their RFD/DAV and ACKIN
signals daisy-chained, to make a FIFO array
any desired number of words deep. Two such
channels in parallel, suitably controlled, make
up a 16-bit-wide buffer array.
DATA
} BUS
}
CONTROL
COMMON {
CONTROL
+5V
GND
Figure 1. Pin Functions
TOZ·BUS
OR QENERAL
MICROPROCESSOR
TO Z·BUS
DR GENERAL
MICROPROCESSOR
Figure 2. Using FIFO. to Extend FIOs
2047-099, 101
227
Z8065
Z8000™ Z·BEP
Burst Error Processor
~
Zilog
Product
Brief
March 1981
Features
• Error detechon and correction for highspeed data transfers.
• Effechve data rates of up to20M bits/
second.
General
Description
• Three correctIOn algorithms: full-period
clock-around method, Chinese remainder
theorem method, and reciprocal polynomIal
method.
• Four selectable Industry-standard
polynomIals: IBM 56- and 48-bit, and
35- and 32-bit polynomials.
• Allows correction of error bursts of up to
12 bIts.
The Z8065 Burst Error Processor (BEP) is a
peripheral interface circUIt for serial or parallel data error detectIOn and correctlO·n. It IS
used in many apphcahons, such as high performance dIsk systems. Four dIfferent
generator polynomials are Internally encoded
to sahsfy a broad range of applicahons.
Data is entered In 8-bit (byte) parallel format, and check bits are provIded in the same
parallel format. Write data IS entered on the
fly into the BEP wh!le blocks are written to the
assocIated disk, and check bIts are extracted
following the last data byte. A Read Normal
mode extracts the error pattern and locahon
wh!le a Read HIgh Speed mode allows direct
dIvision of data by the factors of the generator
polynomIal. A DIvide mode generates output
check bits and validates data. The Compute
mode imhates a data correction process by
locating the error pattern and outputhng it for
correction.
Operating with a single + 5 V supply and a
single phase clock, the Z8065 BEP supports
data rates of up to 20M bits/second and data
streams of over 585K bIts In length. The BEP
detects all errors and allows correction of error
bursts of up to twelve bits In length from the
hrst error bIt location to the last. OutsIde of
the burst error, the probablhty of overlooking
an error is extremely small. (The expressIOn
1/[2N_1J, where N is the degree of the detechon polynomial selected, Indicates the
probability. )
1
DATA OUT-
DATJ
INPUT
• Supports data stream of up to 585K bIts.
}
POLYNOMIAL {
SELECT
}
FUNCTION {
SELECT
CHECK BITS
LOCATED ERROR
PATTERN
ERROR
ALIGNMENT EXCEPTION
READ eRROR
PATTERN
eRROR PATTERN
} PATTERN MATCH
POLYNOMIAL {
SHIFT CONTROL
+5V GND
CP
MR
Figure 1. Pin Functions
2019-001, 002
Some of the matenal herem IS used by permiSSion of Advanced Micro DevlC8s, Inc
Figure 2. Pin Assignments
229
General
Description
(Continued)
reCiprocal polynomial method is used with the
48-bit code correction.
For even more flexibility, the BEP provides
two read modes, normal and high-speed,
which determine the correction methodology if
an error is found. The normal method divides
the data stream by the expanded form of the
polynomial while the high-speed method performs parallel divisions using the factors of the
polynomial. Both methods take the same
amount of time during the read mode.
However, the high-speed method can result
in correction times differing by orders of
magnitude.
Figure 3 shows the major sections of the
28065 BEP. The Polynomial Divide Matrix is
the heart of the BEP. The Control Logic
decodes inputs to generate the Jlecessary
polynomial gating signals to the matrix. The
matrix establishes connections with the
Register Array such that a byte of data
presented on the Do-D7 inputs is suitably
divided by the selected generator polynomial.
The 28065 BEP provides four standard
polynomials, known as Fire codes, to satisfy
a broad range of applications. These polynomials include the popular IBM 56- and
48-bit versions. During a write operation, the
BEP divides the data stream by the selected
polynomial using the rules of algebra in
polynomial fields. The resulting remainder is
the check word, which is then appended to the
data stream for writing on the disc as a record.
When reading the record back, the stream of
data and check bytes is divided by the
appropriate polynomial to obtain the
syndrome.
If the syndrome is not zero, an error is
detected and indicated by the ER (Error) output. This syndrome is used to correct any
errors using a choice of two correction
methodologies, depending on the type of
polynomial selected: the "full-period clockaround" (normal method) or the "Chinese
remainder theorem" (high-speed method). This
extracts the burst error pattern and locates it
in the data stream for external correction. A
.5V
--------
STATUS LOOIC
ll
ERROR (EA)
ZERO DETECTION
RESET(fIFi) - - - - - - ,
ALIGNMENT EXCEPTION IAE)
ALIGNMENT MONITOR
CLOCK ICP) - - - - ,
ERROA PATTERN (EP)
ERROR PAnERN DETECTOR
FUNCTION
SELECT (C2-Co)
READ ERROR
PATTERN (REP)
~
____
~~
____
PATTERN MATCH (PM4 PM21
-J--~
r-...........-l---i.-,
1--_--;--'--"_"
-:-,---I\OATAOUT
107-00)
POLYNOMIAL SHIFT
CONTROL (P3-Po)
POLYNOMIAL
SELECT (S~-So)
REGISTER
ARRAY
1------:-1\. LOCATED ERROR
L_..".,...._j--II-::'--,1 PATTERN (LP3-LPoI
I
I
I
I
I
I
I
I
SELECTABLE POLYNOMIAL
I
DIVIDERS
IL ___________
.,JI
POLYNOMIAL
DIV1DE MATRIX
.---:-----:;----:----'\1
IDr-Do)'-------'---i-;tL_ _ _ _ _ _J
DATA IN
Figure 3. Block Diagram
230
2019·003
00·2019·A
Z8068
Z8000™ Z-DCP Data
Ciphering Processor
~
Zilog
Product
Brief
March 1981
Features
• Encrypts and decrypts data using the
Nahonal Bureau of Standards encryption
algorithm.
• Oata rates greater than 1M bytes/second.
General
Description
• Three ports allow separate ports for the key,
clear data, and enciphered data.
• Provides simultaneous input, output, and
encIphering.
• Key parity check.
SessIOn keys and initializahon vectors may
be entered encrypted or clear.
• Supports three standard ciphering options:
Electronic Code Book, Cipher Feedback,
and Chain Block.
II
The 28068 Oata Ciphering Processor (OCP)
contains the circUItry necessary to encrypt and
decrypt data using the National Bureau of
Standards encryphon alognthm. It is designed
to be used in a variety of environments
including dedicated controllers, communication concentrators, terminals, and peripheral
task processors in general processor systems.
The OCP provIdes a hIgh throughput rate
using CIpher Feedback, Electronic Code
Book, or Cham Block CIpher operating modes.
Separate ports are provIded for key mput,
clear data, and encIphered data to enhance
secunty.
The system communicates with the OCP
using commands entered in the master port
and through auxiliary control lmes. Once set
up, data can flow through the OCP at hIgh
speeds because input, output, and ciphering
activities are all performed concurrently.
External OMA control can easily be used to
enhance throughput m some system configurahons. This deVICe is designed to
interface directly to the 2-Bus.
GND
SP,
SP,
}
SLAVE PDRT {
CONTROL
}.~..
AUXILIARY {
CONTROL
PORT
(DATAl
w.o.,,,!
PORT
CONTROL/KEY
PARITY
+5V
SP,
AUX4
AUX1
AUXs
AUX2
AUX6
AUX3
AUXT
AFLG
SFLG
ASTB
ses
PAR
50S
elK
elK
MR/W
AS
MFLG
MDS
MP,
Mes
MP,
MP,
MP,
MP,
MP,
MP,
+5V
MP,
GND elK
Figure I. Pin Functions
2018-001,002
SP,
sP,
PORT
"U
...
(ADDRESSI
DATAl
Some of the material herem IS used by permiSSion of Advanced Micro DeVices, Inc.
Figure 2. Pin Assignments
231
General
Description
(Continued)
The Z8068 can be configured In several
ways: as a single-port system (Master Port
only). as a dual-port system (master and slave)
with either the master used for clear data and
the slave for encrypted data or vice-versa, as
an encrypting device, or as a descripting
device. Figure 3 shows the major functional
units of the DCP. The AlgorIthm Processor is
the heart of the Z8068. Processing of data with
the ciphering algorithm can be overlapped
with input and outpUt, thus maximizing data
throughput.
ClK
Figure 3. Block Diagram
232
2018·003
00·2018·A
Z8090
Z8000™ Z-UPC Univenal
Peripheral Controller
~
Zilog
Product
Specification
March 1981
Features
each with a 6-bit prescaler. Counter/Timer
TO is driven by an internal source, and
Counter/Timer Tl can be driven by mternal
or external sources. Both counter/timers are
independent of program execution.
• Complete slave microcomputer, for
distributed processing Z-Bus use.
• Unmatched power of Z8 architecture and
instruction set.
• Three programmable I/O ports, two wIth
optional 2-Wire Handshake.
• Six levels of priority mterrupts from eight
sources: six from external sources and two
from internal sources.
• Two programmable 8-bit counter/timers
General
Description
The Z8090 Universal Peripheral Controller
(Z- UPC) is an intelligent peripheral controller
for distributed processing applications (Figure
3). The Z-UPC unburdens the host processor
by assuming tasks traditionally done by the
host (or by added hardware). such as performing arithmetic, translating or formatting data,
and controlling I/O devices. Based on the Z8
Pl'
_
]
~~~
I!I
256-byte register file, accessible by both the
master CPU and Z-UPC, as allocated in the
Z- UPC program.
• 2K bytes of on-chip ROM for efficiency and
versatility.
microcomputer architecture and instruction
. set, the Z-UPC contains 2K bytes of internal
program ROM, a 256-byte register file, three
8-bit I/O ports, and two counter/timers.
The Z-UPC offers fast execution time; an
effective use of memory; and sophisticated
interrupt, I/O, and bit manipulation. Using a
powerful and extensive instruction set
P1& ...........
P3,
P15~
ADDRESS'j ......... ADa
DATA BUS
Ph
P1a ..........
. . - . AD2
P12~
~AD,
PI,
TIM~~:
CONTROL
J
AS
,-R/VI
I -----I-
DS
INTERR~:~
Z·UPC
P
P3, 3 ' _ }
P3,,,--
lEI OR P30
os
GND
WAIT
P35
----. INTACK OR P32
----+- lEI OR P30
lEO OR P3,
GND----.
Figure 1. za090 Z-UPC Pin Functions
2017·069,095
....,,
P20
•
7
P2,
P20
P3,
AD,
P"
PI,
AD,
PI,
AD,
PI,
PI,
PI,
PI,
+5V~
PCLK----.
P2,
P2,
P2,
PORT 3
P3,
:IT
3
iNT OR P3s
DS
Z8090
iNT OR
MASTER {
IEOOA P37
INTACK OR P3a
P10~
...--.. ADo
AND RESET
P3,
PORT 1
AD,
AD,
PI,
PI,
Figure 2. Za090 Z-UPC Pin Assignments
233
General
Description
(Continued)
combined with an efficient internal addressing
scheme, the Z-UPC speeds program execution
and efficiently packs program code into the
on-chip ROM.
An important feature of the Z- UPC is an
internal register file containing I/O port and
control registers accessed both by the Z- UPC
program and indirectly by its associated master CPU. This architecture results in both byte
and programming efficiency, because Z- UPC
instructions can operate directly on I/O data
without moving it to and from an accumulator.
Such a structure allows the user to allocate as
many general-purpose registers as the application requires for data buffers between the CPU
and peripheral devices. All general-purpose
registers can be used as address pOinters,
index registers, data buffers, or stack space.
The register file is logically divided into 16
groups, each consisting of 16 working
registers. A Register Pointer is used in conjunction with short format instructions,
resulting in tight, fast code and easy task
switching.
Communication between the master CPU
and the register file takes place via one group
of 19 interface registers addressed directly by
both the master CPU and the Z-UPC, or via a
block transfer mechanism. Access by the
master CPU is controlled by the Z- UPC to
allow independence between the master CPU
and Z-UPC software.
The Z-UPC has 24 pins that can be dedicated to 110 functions. Grouped logically into
HOST CPU
INTERFACE
three 8-line ports, they can be programmed in
many combinations of input or output lines,
with or WIthout handshake, and with push-pull
or open-drain outputs. Ports 1 and 2 are bitprogrammable; Port 3 has four fixed inputs
and four outputs.
To relieve software from coping with realtime counting and timing problems, the Z- UPC
has two 8-bit hardware counter/timers, each
with a fixed divide-by-four, and a 6-bit programmable prescaler. Various counting modes
may be selected.
In addition to the 40-pin standard configuration, the Z-UPC is available in four special
configurations:
• A 54-pin RAM development version with
external interface for up to 4K bytes of RAM
and 36 bytes of internal ROM permitting
down-loading from the master CPU.
• A Protopack RAM version with a socket for
up to 2K bytes of RAM, with 36 bytes of
internal ROM permitting down-loading from
the master CPU.
• A 64-pin ROM development version with
external interface for up to 4K bytes of ROM
and no internal ROM.
• A Protopack ROM version with a socket for
2K bytes of ROM and no internal ROM.
This range of versions and configurations
makes the·Z-UPC compatible with most system
peripheral device control considerations.
Z·UPC MICROCOMPUTER
PROGRAM
MEMORY
INTERFACE
ADo-AD7
2K
REGISTERS
(PART OF REGISTER
FILE)
)C
B
PORT
1
-----
110
All_
Z·BUS TO
MASTER
CPU
RP
DS
niw
Os
110
'RP
WAIT
L _____ .,
'EO
+5V GND PCLK
Figure 3. Functional Block Diagram
234
2017-0B7
Pin
Description
ADo-AD7' Z-Bus Address/Data Lines (bidirectional). These multiplexed address and data
lines are used to transfer information between
the master CPU and the slave Z-UPC.
AS. Address Strobe {input, active Low}. The
rising edge of AS initiates the beginning of a
transaction and indicates that the Address,
Status, R/W, and CS signals must be valid.
PCLK. Clock {input}. TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.
CS. Chip Select (input, active Low). A Low on
this line during the rising edge of AS enables
the Z- UPC to accept address or data information from the bus during a master CPU write
cycle or to transmit data to the bus during a
read cycle.
Functional
Description
Plo-PI7. P2o-P27. P30-P37' I/O Port Lines
(inputs/outputs, TTL-compatible). These 24
lines are divided into three 8-bit I/O ports and
may be configured in the following ways under
program control:
Plo-PI7' Port 1 (input/output-as output it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P2o-P27' Port 2 (input/output-as output, it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P30-P37' Port 3 (four inputs, four outputs).
Parallel I/O, handshake contro!, timer I/O, or
interrupt control.
R/W. Read/Write (input). This status signal
indicates that the master CPU is executing a
Read cycle if High, and a Write cycle if Low.
DS. Data Strobe {input, active Low}. OS
provides timing for data movement to the bus
master. A simultaneous Low on AS and OS
resets the Z-UPC. It is held in reset as long as
OS is Low.
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the Z- UPC register
file, this signal requests the master CPU to
wait until the Z- UPC can complete its part of
the transaction.
Address Space. On the 40-pin Z-UPC, all
address space is committed to on-chip
memory. There are 2048 bytes of maskprogrammed ROM and 256 bytes of register
file. I/O is memory-mapped to three registers
in the register file. Only the Protopack and
64-pin versions of the Z-UPC can access external program memory. See the section entitled
"Special Configurations" for complete descriptions of the Protopack and 64-pin versions.
Program Memory. Figure 4 is a map of the 2K
on-chip program ROM. Even though the architecture allows addresses from 0 to 4K, behavior of the device above program address 2047
(7FFH) is not defined. The first 12 bytes of program memory are reserved for the Z-UPC
interrupt vectors. For the Protopack and 64-pin
versions, the address space is extended to 4096
bytes. In the RAM versions, addresses OCH
through 2FH are reserved for on-chip ROM.
Register File. This 256-byte file includes three
I/O port registers (l-3H). 234 general-purpose
registers (6-EEH), and 19 control, status
and special I/O registers (OH, 4H, 5H, and
FO-FFH). The functions and mnemonics
assigned to these register address locations are
shown in Figure 5. Of the 256 Z-UPC registers,
19 can be directly accessed by the master
CPU; the others are accessed indirectly via the
block transfer mechanism.
FFH
STACK POINTER
SP
MIC
FEH
MASTER CPU INTERRUPT CONTROL
FDH
REGISTER POINTER
RP
FCH
PROGRAM CONTROL FLAGS
FLAGS
FBH
FAH
upe INTERRUPT MASK REGISTER
upe INTERRUPT REQUEST REGISTER
IRQ
F9H
upe
2"
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED AFTER
RESET
USER
ROM
..... ;-...,
,.
12
11
"
P1M
PORT 3 MODE
P3M
PORT 2 MODE
P2M
F5H
To PRESCALER
PREO
F4H
TIMERfCOUNTER 0
To
F3H
T1 PRESCALER
PREl
TIMERICOUNTER 1
T,
F1H
TIMER MODE
TMR
FOH
MASTER CPU INTERRUPT VECTOR REG
MIV
F2H
EFH
IR04 LOWER BYTE
IRQ4 UPPER BYTE
GENERAL-PURPOSE REGISTERS
IR03 LOWER BYTE
a
IR03 UPPER BYTE
5
1RQ2 LOWER BYTE
4
IRQ2 UPPER BYTE
3
IRQ1 LOWER BYTE
2
IRQ1 UPPER BYTE
2H
1
IROO LOWER BYTE
.H
IROO UPPER BYTE
Figure 4. Program Memory Map
2017·001.002
IPR
POnT 1 MODE
F7H
IR05 UPPER BYTE
a
•
IMR
IR05 LOWER BYTE
9
7
INTERRUPT PRIORITY REGISTER
FaH
FaH
1
IDENTIFIER
(Upe Side)
LOCATION
'H
5H
DATA INDIRECTION REGISTER
4H
LIMIT COUNT REGISTER
LC
3H
PORT 3
P3
PORT 2
PORT 1
DATA TRANSFER CONTROL REGISTER
P2
1H
DIND
P1
DTC
Figure 5. Register File Organization
235
Functional
Description
(Continued)
The I/O port and control registers are
included in the register file without differentiation. This allows any Z-UPC instruction to
process I/O or control information, thereby
elIminating the need for special I/O and control instructions. All general-purpose registers
can function as accumulators, address
pomters, or index registers. In instruction execution, the registers are read when they are
defmed as sources and written when defined as
destinahons.
Z- UPC instructions may access registers
directly or mdlrectly using an 8-bit address
mode or a 4-blt address mode and a Register
Pomter. For the 4-bit addressing mode, the file
is divided into 16 working register groups,
each occupying 16 contiguous locations
(Figure 6). The Register Pointer (RP) in
address location FDH addresses the starting
point of the active workmg-register group, and
the 4-bit register designator supplied by the
instruction specifies the register within the
group. Any mstruction altering the contents of
the register hIe can also alter the Register
Pointer. The Z- UPC instruction set has a
special Set Register Pointer (SRP) instruction
for initialiZing or altering the pointer contents.
Stacks. An 8-bit Stack Pointer (SP), register
R255, is used for addressing the stack,
residing withm the 234 general.-purpose
registers, address location 6H through EFH.
PUSH and POP instructions can save and
restore any register in the register file on the
stack. During CALL instructions, the Program
Counter is automatically saved on the stack.
During Z- UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the stack. The RET and IRET
mstructions pop the saved values of the Program Counter and Flag register.
o
1 1 1
o
THE 4·811 REGISTER}
POINTER PROVIDES THE
UPPER NIBBLE OF THE
REGISTER FilE ADDRESS
FOR THE 4 BIT ADDRESS
MODE
75H 01110101
0 0 0
FFH
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
9FH
90H
8FH
80H
7FH
70H
SFH
'OH
5FH
50H
4FH
40H
3FH
30H
2FH
20H
lFH
10H
OFH
Ports. The Z- UPC has 24 lines dedicated to
input and output. These are grouped into three
ports of eight lines each and can be configured under software control as inputs, outputs, or special control Signals. They can be
programmed to provide Parallel I/O with or
without handshake and timing signals. All outputs can have active pullups and pulldowns,
compatible with TTL loads. In addition, they
may be configured as open-drain outputs.
Port 1. Individual bits of Port I can be configured as input or output by programming
Port I Mode register (PIM) F8H. This port is
accessed by the Z-UPC program as general
register IH. It is written by specifying address
IH as the destination of any instruction used to
store data in the output register. The port is
read by specifying address IH as the source of
an instruction.
Port I may be placed under handshake control by programming Port 3 Mode register
(P3M) F7H. This configures Port 3 pins P33
and P34 as handshake control lines DA Vt and
RDYt for input handshake, or RDYt and DAVt
for output handshake, as determined by the
direction (input or output) assigned to bit 7 of
Port 1. The Port 3 Mode register also has a bit
that programs Port I for open-drain output.
Port 2. Individual bits of Port 2 can be configured as inputs or outputs by programming
Port 2 Mode register (P2M) F6H. This port is
accessed by the Z-UPC program as general
register 2H, and its functions and methods of
programming are the same as those of P0rt 1.
Port 3 pins P3t and P36 are the handshake
lines DAV2 and RDY2, with the direction (input
or output) determined by the state of bit 7 of
the port. The Port 3 Mode register also has a
bit used to program Port 2 for open-drain
output.
Function
DAV2IRDY2
DAVI/RDY 1
RDYIIDAVI
RDY2IDAV2
In
In
In
IRQ3
IRQ2
IRQI
CounterlTlmer { P31
P3e
In
Out
r~
P32
P30
P37
Out
In
In
Out
TIN
TOUT
INT
INTACK
lEI
lEO
P3S
Out
AS
Z-UPC Interrupt
Request'
THE LOWER NIBBLE
OF THE REGISTER FILE
Signal
In
In
Out
Out
Handshake
{ ADDRESS (0101) IS
r
Line Direction
PROVIDED BY THE
INSTRUCTION
Master CPU
Test Mode
~~!
31
P3e
{~~
1
P3J
·P30. P31. and P33 can always be used as UPC mterrupt
request mputs, regardless of the configuration
programmed.
0
Figure 6. Register Pointer Mechanism
236
Table I. Port 3 Control Functions
2017·003
Functional
Description
(Continued)
Port 3. This port can be configured as I/O or
• Nonretriggerable trigger input for the
Z-UPC internal clock divided by four.
control hnes by programming the Port 3 Mode
register. Port 3 is accessed as general register
3H. The directions of the eight data lines are
fixed. Four lines, P3a through P33, are Inputs,
and the other four, P34 through P37, are outputs. The control functions performed by Port
3 are hsted in Table 1.
• External gate input for the Z- UPC internal
clock divided by four.
Interrupts. The Z- UPC allows six interrupts
from eight different sources as follows:
• Port 3 lines P3a, P32, and P33.
• The master CPU(3}.
Counter/Timers. The Z-UPC contains two
8-bit programmable counter/timers, each
driven by an internal 6-bit programmable
prescaler.
The Tl prescaler can be driven by internal
or ext~rnal clock sources. The TO prescaler is
driven by an internal clock source. Both
counter/timers operate independently of the
processor instruction sequence to relieve the
program from time-critical operations like
event counting or elapsed-time calculation. TO
Prescaler register (PREO) F5H and Tl Prescaler register (PREI) F3H can be programmed
to divide the input frequency of the source
being counted by any number from I to 64. A
Counter register (F2H or F4H) is loaded With a
number from 1 to 256. The corresponding
counter is decremented from this number each
time the prescaler reaches end-of-count. When
the count is complete, the counter issues a
timer interrupt request; IRQ4 for TO or IRQ5
for Tl. Loading either counter with a number
(n) results In the interruption of the Z-UPC at
the nth count.
The counters can be started, stopped,
restarted to continue, or restarted from the initial value. They can be programmed to stop
upon reaching end-of-count (Single-Pass
mode) or to automatically reload the initial
value and continue counting (Modulo-n Continuous mode). The counters and pre scalers
can be read at any time without disturbing
their values or changing their counts. The
clock sources for both hmers can be defined as
anyone of the follOWing:
• The two counter/timers.
These interrupts can be masked and globally
enabled or disabled uSing Interrupt Mask
Register (IMR) FBH. Interrupt Priority Register
(IPR) F9H specifies the order of their priority.
All Z-UPC interrupts are vectored.
Table 2 lists the Z-UPC's interrupt sources,
their types, and their vector locations in program ROM. Interrupt Request IRQ6 is
dedicated to master CPU communications.
Interrupt Requests IRQI, IRQ2, and IRQ3 are
generated on the falling transitions of external
inputs P33, P31, and P3a. Interrupt Requests
IRQ4 and IRQ5 are generated upon the timeout
of the Z-UPC's two counter/timers. When an
interrupt request is granted, the Z-UPC enters
an interrupt machine cycle. This cycle disables
all subsequent Interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that Interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
The Z-UPC also supports polled systems. To
accommodate a polled structure, any or all of
the interrupt Inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Following any hardware reset operation, an
EI Instruchon must be executed to enable the
setting of any interrupt request bit in the IRQ
register. Interrupts must be disabled prior to
changing the content of either the IPR (F9H)
or the IMR (FBH). DI is the only Instruction
that should be used to globally disable
Interrupts.
• Z-UPC Internal clock (4 MHz maximum)
divided by four.
• External clock input to Counter/Timer Tl
via P31 (1 MHz maximum).
• Retriggerable tTigger input for the Z- UPC
internal clock divided by four.
Source
Name
IROo
!ROj
IR02
IR03
!R04
!ROS
EOM. XERR, LERR
DAVj, !ROj
DAV2, !R02, TIN
!R03, lEI
Ta
Tl
Vector
Location
a,1
2,3
4.5
6,7
8,9
10,11
Comments
Internal (Ra BIts a, I, 2)
External (P33) I Edge TrIggered
External (P31) I Edge TrIggered
External (P30) I Edge TrIggered
Internal
Internal
Table 2. Interrupt Types, Sources, and Vector Locations
237
Functional
Description
(Continued)
Master CPU Register File Access, There are
two ways in which the master CPU can access
the Z-UPC register file: direct access and
block access.
Direct Access. Three Z- UPC registers-the
Data Transfer Control (OH), the Master Interrupt Vector (FOH), and the Master Interrupt
Control (FEH)-are mapped directly into the
master CPU address space. The master CPU
accesses these registers via the addresses
shown in Table 3.
The master CPU also has direct access to 16
registers known as the DSC (Data, Status,
Command) registers. The DSC Registers are
numbered 0 through F (DSCO-DSCF). These
registers can be any 16 contiguous register file
registers beginning on a 16-byte boundary.
The base address of the DSC register group is
designated by the IRP (110 Register Pointer),
which is bits D4-D7 of the Data Transfer Control register (OH). Figure 7 shows how the
register address is made up of the 4-bit IRP
field, concatenated with the low order 4-bits of
the address from the master CPU.
read or written. The Data Indirection register
is incremented, al).d the Limit Count register is
Block Access. The master CPU may transmit
or receive blocks of data via address xxxiii II
(xxllllix shifted). When the master CPU
accesses this address, the Z-UPC register
pointed to by the Data Indirection register is
DTe
IRP
Z-UPC Address
Decimal
Hex
0
5
@5"
240
254
'n
n+3
n+4
ADDRESS FROM CPU
I-I~I~I~I~I~I~I-I
_lFTED
NON SHIFTED
I~I~I~I~I~I~I~I~I
REGISTER
FILE
n+5
n+6
n+7
OH
5H
@5W'
DTC
DIND
xxxllooO
xx 11 ooOx
FOH
FEH
MIV
xxxII 11 I
xxxlOOOO
xxxII 110
xxlllllx
xxlOOOOx
xxII 11 Ox
xxxOooOO
xxxOOOOI
xxOOOOOx
xxOOOOlx
DSC3
DSC4
DSC5
DSC6
xxxOOOIO
xxxOOOIl
xxxOOIOO
xxxoo 10 I
xxxOOllO
xxOOOlOx
xxOOOllx
xxOOIOOx
xxOO 10 Ix
xxoollOx
MIC
DSC7
xxxOOll1
n+B
DSCB
n+9
n+lO
DSC9
xxxOIOOO
xxxOIOOI
xxOOlllx
xxOlOOOx
xxOIOOlx
n+ 11
n+12
DSCA xxxOIOIO
DSCB xxxOlOIl
DSCC xxxOlIOO
xxOlOllx
xxOllOOx
n+13
n+14
n+ 15
DSCD xxx01101
DSCE xxxOlllO
DSCF xxxOl 11 I
xxOllOlx
xxOlllOx
xxOllllx
x = don't care
*n IS the value In the IRP x 16
• • Master CPU accesses the register address
Figure 7, DSC Register Addressing Scheme
238
Shllt
Address
No-Shllt
ldentilier Address
DSCO
DSCI
DSC2
n+1
n+2
~
----==r=f""'
decremented, for example, when the master
CPU issues a read or write to address
xxxiii II while the Data Indirection register
contains the value 33H. The operation causes
register 33H to be read or written and the Data
Indirection register to be incremented to 34H.
The Limit Count register (04H) is decremented and is used to control the number of
bytes to be transferred by master CPU block
accesses. If the master CPU attempts a read or
write to the Z-UPC after the Limit Count
register reaches 0, the access is not completed, the LERR bit (D2) of the Data Transfer
Control register is set (indic~ting a limit
error), and the LERR error causes an IROo interrupt request.
The IRP field of the Data Transfer Control
register, the Data Indirection register, and the
Limit Count register are not directly accessible
to the master CPU and therefore must be set
by the Z-UPC. This allows the Z-UPC to protect
itself from master CPU errors and frees the
master CPU from tracking the Z-UPC's internal
data layout.
In
xxO 101 Ox
Register 5
Table 3. Master CPU/Z-UPC Register Map
2017-004
Special
Configurations
There are two Protopack and two 54-pin
versions of the Z-UPC_ These versions are
identical to the 40-pin Z- UPC with the following exceptions:
• Internal ROM is totally omitted from the
54-pin development and ROM Protopack
versions_
• All but 35 bytes of internal ROM are omitted
from the 54-pin RAM and Protopack RAM
versions.
• The memory address and data lines are buffered and brought out to external pins or to
the socket on the Protopack.
• Control lines for the external memory are
also prOVided.
The 54-pin version of the Z- UPC allows the
user to prototype the system in hardware with
an actual Z- UPC device and to develop the
code intended to be mask-programmed into
the on-chip ROM of the 40-pin Z- UPC for the
production system. The 54-pin or Protopack
RAM/ROM versions of the Z- UPC are extremely versatile parts. Memory space can be
extended to 4K bytes on the 54-pin version by
using external RAM/ROM for all but 35 bytes
of the Z-UPC's memory space. This memory
can then be down-loaded from the master CPU
using a bootstrap program stored in the 35
bytes (C-2F). Figure 8 is a memory map for
the 54-pin RAM version.
54-Pin and Protopack Pin Functions. Forty of
the pins on the 54-pin and Protopack versions
have functions identical to those of the 40-pin
version. The remaining 24 pins have additional
functions described below. (Figures 9 through
11 show the 54-pin and Protopack versions' pin
functions and pin assignments.)
Ao-All' Program Memory Address Lines (output). These lines are identical in all 54-pin and
RAM versions in the Protopack. They are used
to address 4K bytes of external Z- UPC memory.
Do-D7' Program Data (input). Data is read in
from the external memory on these lines. The
RAM version also writes external memory
through this bus.
lACK. Interrupt Acknowledge (output, active
High). This signal is active whenever an internal Z-UPC interrupt cycle is in process.
ADDRESS/!
DATA
BUS
BUS{
TIMING
AND RESET
CONTROL {
INTERRUPT {
FFFH . . . - - - - - - - - - - - - ,
EXTERNAL
PROGRAM MEMORY
RAM
EXTERNAL!
DATA
~~~ f - - - - - - - - - - - - 1
EXTERNAL {
BOOTSTRAP ROM
INTERNAL
}
CONTROL
ROM
~~r----------~
PCLK
Z UPC INTERRUPT
VECTORS
EXTERNAL
)
RAM
+5V
~------------~
Figure S. Z-UPC RAM Version Memory Map
2017-005,006
Figure 9_ ZS091/ZS092 Z-UPC Pin Functions
239
Special
Configurations
(Continued)
MAS_ Memory Address Strobe (output, active
Low). This address strobe is pulsed once for
each memory fetch to interface with quasistatic RAM.
MDS. Memory Data Strobe (output, active
Low). This signal is Low during an instruction
fetch or memory write.
64
MR/W. Memory Read/Write (output RAM
versions only). This signal is High when the
Z- UPC is fetching an instruction and Low when
it is loading external memory.
SYNC. Instruction Sync (output, active Low).
This signal is Low during the clock cycle just
preceding an opcode fetch.
+SY
PCLK
+5V 1
PCLK 2
·20
."
Z8091
Z8092
."."
'"
D,
D,
D,
D.
A.
A,
A,
A3
A,
As
A,
A,
P3s100 5
36 P2s
P32iINTACK 6
35 P24
057
34 P23
RlW 8
33 P22
AS9
32 P21
10
31 P20
aND 11
30 P33
WAIT 12
29 .""
28 P17
AD7 13
AD6 14
27 P16
21
ADs 15
26 P1s
22
AD4 16
25 P14
23
2.
2.
2.
27
28
2.
3.
31
32
MRiW/lACK
AD3 17
24 P13
AD2 18
23 P12
AD1 19
22 P11
ADo 20
21 P10
D3
'SOCKET FOR 2716 EPROM (2K )( 8) OR RAM
Figure 11. Z8093/Z8094 Protopack Pin Assignments
RR
Reglster palr or workmg-reglster palr address
IRR
IndIrect regIster pair or mdirect workIng-regIster
R
Irr
Ir
cist
Reglster or workmg-reglster address
Working-reglster address only
Indirect-reglster or mdlrect workmg-reglster
address
'
Indirect workmg-reglster address only
Destmation locahon or contents
Source locahon or contents
Condltion code (see list)
cc
@
Indlrect address prehx
SP
Stack Pomter (control reglster FFH)
PC
Program Counter
FLAGS Flag reglster (control reglster FCH)
RP
Reglster Pointer (control reglster FDH)
IMR
Interrupt Mask reglster (control reglster FBH)
arc
240
37 P26
The follOWing notation is used to deSCribe the
addressing modes and instruction operations as
shown in the instruchon summary.
IR
Symbols
38 P21
P30fiEI 4
1.
20
Figure 10. Z8091/Z8092 Z-UPC Pin Assignments
Addressing
Modes
39 P3s
P371IEO 3
CS
Z·UPC
40 P31
X
DA
RA
1M
palr address
Indirect workmg-reglster palr only
Indexed address
Dlrect address
Relahve address
Immedlate
Assignment of a value is indicated by the symbol
u_". For example,
dst - dst + src
indicates that the source data IS added to the
destmahon data and the result IS stored in the
destmation location. The notation "addr{n)" is used
to refer to bit "n" of a given locatIOn. For example,
dst (7)
refers to bit 7 of the destmation operand.
2017-007,008
Flags
Control RegIster FCH contains the following six
flags:
C
Z
S
V
D
H
Condition
Codes
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Value
Cleared to zero
Set to one
Set or cleared accordmg to operallon
Unaffected
Undefmed
*
X
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Affected flags are mdicated by:
o
Meaning
C
NC
Z
NZ
Flags Set
Always true
Carry
C
No carry
C
Zero
Z
PL
EO
NE
GE
Mmus
S = a
S
1
V
No overflow
V
Equal
Not equal
Z
GT
LE
UGE
[Z OR (8 XOR V)j = a
[Z OR (8 XOR V)j = 1
C =a
C = 1
(C = a AND Z = 0)
(C OR Z) = 1
UnsIgned greater than or equal
ULT
Unsigned less than
Unsigned greater than
Unsigned less than or equal
UGT
ULE
1
a
1
a
Z =
(8 XOR V) = a
(8 XOR V) = 1
Greater than or equal
Less than
Greater than
Less than or equal
LT
= 1
Overflow
Plus
MI
1
a
Z =a
Not zero
OV
NOV
=
Never true
Instruction
Formats
ope
CCF, 01, EI, tRET, NOP,
ReF, RET, SCF
dot
ope
INC r
One-Byte Instructions
ope
MODE
dst/src
OR 111 101 dstlsrc
I
CLR, CPL, CA, DEC,
DECW, INC, INew, POP,
ope
RRC, SRA, SWAP
ope
MODe
'"
dot
PUSH, AL, RLC, RR,
Aoe, ADD, AND, CP,
LD, OR, SSC, SUB,
TeM, TM, XOR
OR
OR
1 1 1 0
1 1 1 0
d"
OR
b 1 1 01
dot
OR
OR
til 0
JP, CALL (Indirect)
dot
1 OR
11
1 1
01
ope
ope
dot
SRP
MODE
dot
VALUE
ACC, ADD, AND, CP,
LD, OR,
sec, SUB,
reM, 1M, XOR
VALUE
ope
MODE
ope
ADe, ADD, AND,
MODE
CP, OR, SBC, SUB,
d"
MODE
ope
src/dst
ope
dsl/src
srcJdst
I
ope
LD, LDE, LOEI,
LOC, LOCI
dot
ope
MODE
OR
11
1 1
01
LD
ope
JP
DA,
DA,
LD
ope
IdsllCCR~ OPC
LD
dst/src
ADDRESS
VALUE
DJNZ, JR
Two-Byte Instructions
2037-013
LD
1 1 1 0
reM, TM, XOR
dstlsrc
d"
d,'
CALL
DA,
DA,
Three-Byte Instructions
241
Opcode
Lower Nibble (Hex)
Map
o
o
2
4
5
..
m
6
!!'!.
.!
.Q
:9
7
6,5
6,5
DEC
DEC
D
E
F
10,5
R2,RI
IR2,RI
RI,!M
JRI,IM
6,5
10,5
10,5
10,5
10,5
RLC
RLC
Irz
RI
JRI
fl,IZ
R2,RI
IR2,RI
RI,IM
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IRI,!M
II,
RI
IRI
II, [2
Il,II2
R2,RI
JR2,RI
RI,IM
6,1
6,5
6,5
10,5
10,5
10,5
10,5
IP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRRI
1M
II, [2
Il,II2
R2,RI
JR2,RI
RI,IM
JR1,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
IRI,IM
RI
JRI
II, [2
Il,lu
R2,RI
JR2, RI
RI,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
JRI,!M
RI
JRI
II, [2
Il,II2
R2,RI
JR2,RI
RI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
RI
IRI
rl,IZ
n,lrz
R2,RI
JR2,RI
RI,IM
JRI,!M
10/12,1 12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH PUSH
TM
TM
TM
TM
TM
TM
II, [2
[11hz
R2,RI
IR2,RI
RI,IM
JRI,IM
°
LDE
12,
DECW DECW
JRI
6,5
6,5
RL
RL
RI
JRI
10,5
10,5
E
A
B
6,5
6,5
12110,5
12110,0
6,5
12/10,0
6,5
LD
LD
DINZ
IR
LD
IP
INC
Il,R2
[2, HI
rl,RA
cc,RA
n,IM
cc,DA
fl
C
IRI,!M
8,0
RRI
D
9
F
r--
ADC ADC ADC ADC ADC ADC
6,5
II,rIlZ
°
LDE
12,
r-r--r--r---
r-r-r--
18,0
6,1
LDEI
DI
In,Irrz
r--
18,0
6,1
LDEI
EI
12,lrn Irz,lrrl
6,5
INCW INCW
IRI
6,5
10,5
10,5
10,5
r--
10,5
CP
CP
CP
CP
CP
CP
n,rz
n,Irz
R2,RI
JR2,RI
RI,IM
IRI,IM
14,
°
RET
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
r---
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
RI
JRI
II, [2
[1, h 2
R2,RI
IR2,RI
RI,IM
IRI,!M
IRET
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LDC
LDCI
LD
RI
JRI
n,Irrz Ir 1, Irrz
II,
6,5
6,5
12,0
18,0
SRA
LDC
LDCI CALL*
RI
JRI
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
RI
IRI
II, Irz
R2,RI
IR2,RI
RI,IM
IRI,IM
6,7
6,7
6,5
10,5
LD
LD
hI, [2
R2,IRl
Iz,lrn 1I2,Inl
SWAP SWAP
"-
JRI
'V'
'"
20,0
20,0
10,5
CALL
LD
DA
IRRI
"-
I2,
16,0
r--6,5
RCF
x, R2
SRA
RI
Bytes per
Instruction
10,5
Il,112
RRI
C
10,5
6,5
JR2
B
10,5
II, [2
10,5
A
6,5
IRI
R2
9
6,5
ADD ADD ADD ADD ADD ADD
6,5
10,5
'"'"
7
RI
til
::>
6
6,5
:z;
8
5
2
x,
r-6,5
SCF
HI
r-6,5
CCF
r--6,
"V"
3
°
NOP
,.I
"-~----------~~----------,'" ~ ~
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode- A
Nibble
First
Operand
•
Pipeline
Cycles
Mnemonic
Second
Operand
Legend:
R = 8·61t Address
r = 4·Blt Address
R1 or r 1 = Dst Address
R2 or [2 = Src Address
Sequence:
Opcode, FlrSt Operand, Second Operand
Note: The blank areas are not defmed.
*2.byte Instruchon; fetch cycle appears as a 3·byte Instruction.
242
8085-002
Instruction
Summary
Instruction
and Operation
Addr Mode
dst
Brc
Opcode Flags Allected
Byte
(Hex)
CZSVDH
ADC dst,sre
dst - dst + arc + C
(Note I)
10
* a *
ADD dst,sre
(Note I)
00
a *
(Note I)
50
dst - dst + sre
AND dst,sre
dst - dst AND sre
a
DA
SP-SP-2
IRR
@SP - PC; PC - dst
D6
D4
------
CCF
EF
,..
R
IR
BO
BI
dst - NOT dst
R
IR
60
61
CP dst,sre
(Note I)
COM dst
-
- -
-
dst - DA dst
DEC dst
dst - dst - I
DECW dst
dst-dst-I
a
dst - @SP
SP - SP +
R
IR
50
51
------
R
IR
RCF
70
71
-
-
a
RET
AF
------
-
-
d
00
01
-k**--
RLCdst~
R
IR
!O
II
RR
IR
80
81
- * * *- -
lc:;r1
I~
EO
EI
RRCdst~
R
IR
CO
CI
(Note I)
3D
'
RR dst
45J
,
'
RA
-
CF
C-O
8F
------
rA
------
r~O-F
,
0
0
SBC dst,sre
•n
* I *
dst - dst - sre - C
SCF
SRA dst
------
45J~I~
- - - - -
DF
I
DO
* * * 0
C-I
DI
31
------
20
* * * * I *
Fa
FI
X
IR
TCM dst,sre
(NOT dst) AND sre
(Note I)
60
- * *
0
TM dst,sre
(Note I)
70
- * *
0
(Note I)
BO
SRP sre
1m
RP - sre
rE
r~O-F
-
* ,.. ,.. - -
R
IR
20
21
RR
IR
AO
AI
- * * *- -
BF
* * * * * *
DA
PC - dst
IRR
cD
SUB dst,sre
dst - dst - sre
(Note I)
SWAP dst ~ R
dst AND sre
------
XOR dst,sre
* * x - -
* 0 - -
dst - dst XOR sre
e~O-F
30
RA
eB
------
Note I
e~O-F
true,
These InstructIons have an IdentIcal set of addressmg
PC-PC+dst
Range: + 127, -128
r
R
1m
R
rC
r8
r9
------
modes, whIch are encoded for brevIty. The hrst opeode
nIbble IS found In the InstructIOn set table above. The
second nIbble IS expressed symbolIcally by a 0 In thIS
table, and
Its
value
IS
found
In
the followmg table to the
left of the applIcable addreSSIng mode paIr.
r~O-F
8085~OO3
- * * 0 - -
R
IR
IP ee,dst
If CC 15 true
For example, to determme the opcode of an ADC
Instruction usmg the addreSSing modes r (destmahon) and
r
X
r
Ir
R
R
R
IR
IR
X
r
Ir
r
R
IR
1m
1m
R
C7
D7
E3
F3
E4
E5
E6
E7
F5
r
Irr
Irr
C2
D2
------
Ir
clst - src
Irr
r - r + 1; rr - rr + 1
Irr
Ir
C3
D3
------
src
------
40
90
91
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) - I
clst -
FF
(Note I)
R
IR
IRET
LDCI dst,src
OR dst,sre
0I6J
dst-dst+1
LDC dst,src
------
RL dst
INC dst
LD dst,sre
clst - src
83
93
SP - SP - I; @SP - sre
AD
9F
If CC IS
Irr
Ir
PUSH sre
IMR(7) - I
IR ee,dst
Ir
Irr
dst - sre
r - r + I; rr - rr + 1
LDEI dst,sre
* * * X
EI
dst - dst +
------
40
41
*
INCW dst
82
92
R
IR
r - 1
If r
0
PC - PC + dst
Range: + 127, -128
r -
Irr
PC - @SP; SP-SP+2
Dl
IMR (7) - 0
DINZ r,dst
r
Irr
LDE dst,sre
dst - src
POP dst
-
dst - sre
DA dst
Brc
dst - dst OR sre
C - NOT C
dst - 0
Opcode Flags Allected
Byte
(Hex)
CZSVDH
dst
NOP
CALL dst
CLR dst
Addr Mode
Instruction
and Operation
Ir (source) IS 13.
Addr Mode
dst
R
R
R
IR
Brc
Ir
R
IR
1M
1M
Lower
Opeode Nibble
rn
rn
m
~
@]
rn
243
Registers
R248 PIM
Port 1 Mode Register
Z-UPC register address (Hex): F8
R247 P3M
Port 3 Mode Register
Z-UPC register address (Hex): F7
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
III ~::;::~::::~:::
LI____ ~~E~l~~g ~~Fl~I~8rpUT
1 DEFINES BIT AS INPUT
1 PORT 1 PULL·UPS ACTIVE
o P35
R246 P2M
Port 2 Mode Register
Z-UPC regIster address (Hex): F6
:::: OUTPUT
1 P35;:: INT
RESERVED
o P3S
= INPUT
1 P33 "" DAVlIRDY1
I~I~I~I~I~I~I~I~I
L._ _ _ _ _ ~ ~!~
: ~N:~R~~J
L _ _ _ _ _ _ ~ ::~ : :~tUT
P2o-P21 110 DEFINITION
L -_ _ _ _ 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
=
P34
OUTPUT
P34 = RCY1/DAV1
~~:: ~~~:~OUT)
~:; : ~~TPUT
Figure 12_ Port Mode Registers
R251lMR
Interrupt Mask Register
Z-UPC register address (Hex): FE
R250 IRQ
Interrupt Request Register
Z-UPC register address (Hex): FA
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
e~~
1
L
I
I
L IROO; MASTER CPU COMMUNICATIONS
~ IRQ1 = P33 1NPUT
~~
L'ENABLESIROO
1 ENABLES IRQ1
1 ENABLES IRQ2
1 ENABLES IR03
,
1 ENABLES IRQ4
IR02
lRQ3
= P31 INPUT
= P30 INPUT
IRQ4=To
1 ENABLES lAOS
lAOS = T1
RESERVED
RESERVED
1 ENABLES INTERRUPTS
R2491PR
Interrupt Priority Register
Z-UPC register address (Hex): F9 (Write Only)
I~I~I~I~I~I~I~I~I
I
RESERVED
~~ o '"
IRQ1, IRQ4 PRIORITY (GROUP C)
IRQ1 > IRQ4
INTERRUPT GROUP PRIORITY
RESERVED", 000
C>A>B '" 001
A>B>C '" 010
A>C>B '" 011
B>C>A '" 100
C>B>A '" 101
B>A>C '" 110
RESERVED:: 111
1 "" IRC4 > lRCl
IRCO, IRC2 PRIORITY (GROUP B)
0::: IRC2 > IRCO
1 = IRCO>IR02
lRC3, IROS PRIORITY (GROUP AJ
0 = IR05 > IR03
1 = IRC3>IROS
Figure 13_ Interrupt Control Registers
R254 MIC
Master CPU Interrupt Control Register
Z-UPC register address (Hex): FE
R240 MIV
Master CPU Interrupt Vector Register
Z-UPC register address (Hex): FO
I~I~I~I~I~I~I~I~I
LO-
~lS
I~I~I~I~I~I~I~I~I
1 END OF MESSAGE
o WAIT ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE
IL-__
VECTOR DATA (Do; LSB)
o ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN
o DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
o VECTOR OUTPUT
1 NO VECTOR OUTPUT
L _____
'-------
~ ~~S~~~T~:UCI~~:~~~~~U:~N~~~gING
~ ~N~~~~~~~UJ~DUE~Di:R~~~~ICE
'-------- ~ :~i~==~:i =~g~~;~ ~~s::c:g
Figure 14. Master CPU Interrupt Registers
244
2017-009,010,011
Registers
(Continued)
R252 FLAGS
Flag Register
Z-UPC reglster address (Hex): FC
R253 RP
Register Pointer
Z-UPC register address (Hex): FD
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
E~~
'
L
c=
LUSERFLAGF1
DON'T CARE
USER FLAG F2
HALF~CARRY
FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
R255 SP
Stack Pointer
Z-UPC register address (Hex): FF
CARRY FLAG
I~I~I~I~I~I~I~I~I
1...._ _ _ _
~Tp~:~p~~INTEA
Figure 15. Z-UPC Control Registers
RODTC
Data Transfer Control Register
Z-UPC reglster address (Hex): 00
R4LC
Limit Count Register
Z-UPC register address (Hex): 04
I~I~I~I~I~I~I~I~I
LIMIT COUNT VALUE
L-_ _ _ _ _ (RANGE 0-255 DECIMAL
OO-FF HEX)
END OF MESSAGE
NO TRANSFER ERROR
TRANSFER ERROR
(LEAR)
NO LIMIT ERROR
LIMIT ERROR
(EDX)
DISABLE DATA TRANSFER
ENABLE OATA TRANSFER
""I"'RP-')_ _ _ _ _ _ _ l
R5 D1ND
Data Indirection Register
Z-UPC register address (Hex): 05
I~I~I~I~I~I~I~I~I
I/O REGISTER POINTER
Figure 16. Master CpO-Z-UPC Data Transfer Registers
R241 TMR
Timer Mode Register
Z-UPC register address (Hex): Fl
R243 PREI
Prescaler I Register
Z-UPC reglster address (Hex): F3
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
RESERVED == 00
ToOUT
01
TourMODESj
T1 OUT = 10
INTERNAL CLOCK OUT = 11
=
~~
~
L ~~U~TS~N°o"L~
0 == NO FUNCTION
1 == LOAD To
0 ::: DISABLE To COUNT
1 == ENABLE To COUNT
l.1 ~~gg~
EXTERNT
0 == NO FUNCTION
INPUT = 00
1 = LOAD T1
TR1~~i~ :~~~~ ~ ~~
0
(NON RETRIGGERABLE)
TRIGGER INPUT", 11
(RETRIGGERABLE)
1
=
=
PASS
1 '" T1 MODULO. N
CLOCK SOURCE
EXTERNAL TIMING INPUT
(TIN) MODE
1 '" T1 INTERNAL
o '"
PRESCALER MODULO
DISABLE T1 COUNT
ENABLE T1 COUNT
(RANGE· 1-64 DECIMAL
01-00 HEX)
R244 TO
CounterlTimer 0 Register
Z-UPC reglster address (Hex): F4
R242 Tl
Counter/Timer 1 Register
Z-UPC register address (Hex): F2
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
1-___
..
~~~~~~~~-~~~~~CIMAL
T11NITIAL VALUE
' - - - - - - (RANGE: 1-256 DECIMAL
01-00 HEX)
01-00 HEX)
R245 PREO
Prescaler 0 Register
Z-UPC register address (Hex): F5
I~I~I~I~I~I~I~I~I
L ~~U~oTS~~~CE.PASS
~
1
=
To MODULO· N
RESERVED
PRESCALER MODULO
(RANGE. 1-64 DECIMAL
01-00 HEX)
Figure 17. Z-UPC Counter/Timer Registers
2017-012,013,014
245
Registers
(Continued)
Control Register
07
06
05
04
03
02
01
00
Comments
OOH
Data Transfer Control Reglster
X
X
X
X
a
a
a
a
Dlsable data transfer
from master CPU
0
0
0
Stops TO and Tl
X
0
0
Single-Pass mode
X
0
0
Single-Pass mode
External clock source
04H
Llmlt Count Reglster
Not Defined
aSH
Data Ind,recIJon Reglster
Not Defined
FOH
Interrupt Vector Register
Not Defmed
FIH
T,mer Mode
a
a
a
X
X
X
F4}j
Tl Reglster
F5H
Tl Prescaler
0
Not Defmed
F2H
TO Reglster
F3H
TO Prescaler
0
X
X
Not Defmed
X
X
X
X
X
Port 2 lines defined as
F6H
Port 2 Mode
F7H
Port 3 Mode
inputs
0
0
0
0
X
0
0
Port I, 2 open dram;
P3S = INT; P30, P31, P32,
P33 defined as mput; P34,
P36, P37 defmed as output.
Port lImes defined as
FBH
Port I Mode
mputs
Not Defmed
F9H
Interrupt Pnonty
FAH
Interrupt Request
X
X
0
0
0
0
0
0
Reset Interrupt Request
FBH
Interrupt Mask
0
X
X
X
X
X
X
X
Interrupts disabled
0
0
0
Master CPU mterrupt disabled; walt-enable when
write; lower chain enabled
FCH
Flag Reglster
Not Defmed
FDH
Not Defmed
Reglster Pomter
FEH
Master CPU Interrupt
Control Reglster
FFH
Stack Pomter
0
0
0
0
0
Not Defmed
NOTE: X means not defmed.
Table 4. Control Register Reset Conditions
246
Absolute
Maximum
Ratings
Voltages on all pins (except VBB )
with respect to GND .......... -0.5 V to + 7.0 V
Operating Ambient
Temperature .................. 0 °C to + 70°C
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
Stresses greater than those listed under Absolute Maximum Ratmgs may cause permanent damage to the device.
This IS a stress ratmg only; operatIon of the device at any
condltIon above those indicated in the operational sectIons
of these specifIcations IS not ImplIed. Exposure to absolute
maximum rating conditIons for extended periods may affect
devICe relIability.
• +4.75 V :5 VCC :5 +5.25 V
• VSS = GND = 0 V
• O°C :5 TA :5 +70°C
+5V
+5V
2.2K
Figure 18. Test Load 1
DC
Characteristics
Symbol
Figure 19. Test Load 2
Parameter
Min
Max
Unit
VCH
Clock Input High Voltage
V
Clock Input Low Voltage
2.4
-0.3
2.0
-0.3
2.4
Vcc
VCL
VIH
Input High Voltage
V IL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
-10
10L
Output Leakage
-10
Icc
Vce Supply Current
0.8
V
Vcc
V
0.8
0.4
10
10
180
Condition
V
V
IoH = -250 p.A
V
IoL= +2.0 rnA
p.A
p.A
o :S
o :S
o,::n 2
VIN :S +5.25 V
VIN :S +5.25 V
rnA
1 For AO-All and 00-07, MOS, SYNC, MAS, and MR/W/IACK on the 64-pm versions. IOH
ROR~-onnn
Notes
= 100 ~A and IOL = 1.0 rnA.
247
Master CPU
Interface
Timing
Number Symbol
Min (ns) Max (ns)
Parameter
20
1855
20
1855
105
250--2000
0
60
10
·50
TrC
Clock Rise Time
Clock High Width
2
TwCh
Clock Fall Time
3
TIC
4
TwCI
Clock Low Width
5-TpC
Clock Period
TsCS(AS)
CS to AS I Setup Time
6
ThCS(AS)
CS to AS I Hold Time
7
TsA(AS)
Address to AS I Setup Time
8
ThA(AS)
Address to AS I Hold Time
9
AS Low Width
10-TwAS
II
TdDS(DR)
DS , to Read Data Not Valid
TdDS(DRz)
12
DS I to Read Data Float Delay
AS I to DS , Delay
TdAS(DS)
13
TdDS(AS)
DS I to AS , Delay
14
15-ThDW(DS)--Write Data to DS Hold Time
TdDS(DR)
DS , to Read Data Valid Delay
16
TdAz(DS)
Address Float to DS Delay
17
DS Low Width
18
TwDS
R/W (Read) to DS , Setup Time
19
TsRWR(DS)
20-TsRWW(DS)-RlW(Wflle) to DS , Setup Time
TsDW(DSf)
Wflte Data to DS , Setup Time
21
TdAS(W)
AS , to WAIT' Valid Delay
22
23
24
ThRW(DS)
TsDR(W)
105
70
0
60
50
30
70
2095
2
1--
3
0
390
100
0
30
195
RlW to DS I Hold Time
Read Data Valid to WAIT
60
0
Number Symbol
Parameter
Interrupt
Acknowledge
INTACK to AS I Setup Time
TsIA(AS)
25
Timing
ThIA(AS)
26
!NTACK to AS I Hold Time
AS I to DS , (Acknowledge) Delay
TdAS(DSA)
27
TdDSA(DR)
DS' (Acknowledge) to Read Data Valid Delay
28
DS I (Acknowledge) Low WIdth
29
TwDSA
30-TdAS(IEO)--AS I to lEO Delay
TdlEIf(lEO)
lEI to lEO Delay
31
TslEl(DSA)
lEI to DS , (Acknowledge) Setup Time
32
DS , to INT Delay
TdDS(lNT)
33
lEI to DS I Hold Time
ThIEI(DS)
34
Min (ns) Max (ns)
Notes·
0
250
940
360
475
290
120
150
500
100
NOTES
1. Parameter does not apply to Interrupt Acknowledge
4. The hmmg characterlshcs given reference 2.0 V as HIgh and
transactions.
2. The maXImum value for TdAS(DS) does not apply to Interrupt
O.S V as Low.
5. All output ae parameters use test load 1.
Acknowledge transactions
3
248
Notes·
ThIS parameter IS dependent on the state of UPC at the hme of
master CPU access
·Timmgs are prehmmary and subject to change.
Master CPU
Interface
Timing
PCLK
Cs
RlW
(WRITE)
RJW
(READ)
----='
--------H-----....:!t-+----i--t----1~
--------:-H----
AD o-AD7
MASTE:'~I~~
_ _ _ _ _ _ _ , __
..
+....;.;;"'=_-'[~--=.:::..:...:..:.---+::::-:-------
Interrupt
Acknowledge
Timing
2017-015,016
249
Handshake
Timing
Number Symbol
RAM Version
Program
Memory
Timing
Min (ns) Max (ns)
TsDI(DA)
Data In Setup Time
ThDA(DI)
Data In Hold Time
TwDA
Data Available Width
4
TdDAL(RY)
Data Available Low to Ready
Delay Time
5
TdDAH(RY)
Data Available High to Ready
Delay Time
6
TdDO(DA)
Data Out to Data Available
Delay Time
7
TdRY(DA)
Ready to Data Available Delay Time
2
3
Reset
Timing
Parameter
Number Symbol
0
230
175
20
0
150
0
50
Parameter
0
205
Min (ns) Max (ns)
TdRDQ(WR)
Delay from DS f to AS J for No Reset
2
TdWRQ(RD)
Delay from DS f to AS J for No Reset
3
TwRES
Minimum Width of AS and DS both Low
for Reset
Number Symbol
175
1,2
1,2
2,3
1,2
2,3
2
2
Notes·
40
50
250
4
Min (ns) Max (ns)
Parameter
Notes·
Notes·
1
2
3
TwMAS
Memory Address Strobe Width
TdA(MAS)
Address Valid to Memory Address Strobe f Delay
TdMRIW
(MAS)
Memory Read/Write to Memory Address Strobe f
Delay
4
TdMDS(A)
Memory Data Strobe f to Address Change Delay
5-
TdMDS - - - Memory Data'Strobe f to Memory ReadlWrite Not --80 - - - - - : - - - - - (MRIW)
Valid Delay
6
Tw(MDS)
Memory Data Strobe Width (Write Case)
7
TdDO(MDS)
Data Out Valid to Memory Data Strobe J Delay
II
12
13
14
15
TdMAS(DI)
Memory Address Strobe J to Data In Valid Delay
ThMDS(DI)
Memory Data Strobe f to Data In Hold Time
TwSY
Instruction Sync Out Width
TdSY(MDS)
Instruction Sync Out to Memory Data Strobe Delay
TwI
Interrupt Request via Port 3 Input Width
60
30
30
5
5
5
60
160
6
30
5
TdMDS(DO)
Memory Data Strobe f to Data Out Change Delay
8
30
5
9
Tw(MDS)
MelTIory Data Strobe Width (Read Case)
230
6
IO-TdMDS(DI)- Memory Data Strobe J to Data In Valid Delay - - - - - - - - 1 6 0 - - - 7 - 280
7
0
160
200
100
NOTES:
1. Input Handshake.
2. Test Load l.
3. Output Handshake.
4. Internal reset sIgnal is 1;2 to 2 clock delays from external reset
condItIon.
S. Delay hmes are specIfIed for an mput clock frequency of
4 MHz. When operatmg at a lower frequency, the Increase In
input clock perIod must be added to the speClhed delay hme.
6. Data strobe width IS specIhed for an mput clock frequency of
4 MHz. When operating at a lower frequency, the Increase in
250
three mput clock penods must be added to the specIfIed wIdth.
Data strobe width varIes accordmg to the instructIon bemg
executed.
.
7. Address strobe and data strobe to data In valId delay hmes
represent memory system access hmes and are gIven for a
4 MHz Input frequency.
8. All timIng references assume 2.0 V for a logIC "1" and 0.8 V
for a lOgIC "0."
9. All output dC parameters use test load 2.
~TImmgs are prelimmary and subject to change.
Handshake
Timing
DATA IN
DAV
INPUT
----------------------~
I
~Jr~-pott-T---------
RDY
OUTPUT
READ
Input Handshake
DATA OUT
DATA OUT VALID
DAY
OUTPUT
I
RDY
\
\
INPUT
d
...,
C'lI
Output Handshake
Reset
Timing
RAM Version
\L ---
Program
Memory
Timing
if
~
G::>- :--
)
AO-A11
MRlW
~
X
ADDRESS VALID
r
)
(RAM VERSION
ONLy)
~
MDS
WRITE CASE
~
DO-D7
WRITE CASE
DATA VAl.1D OUT
'"
MDS
~
2017·017,018,019
®
01X
~
READ CASE
IJ
1-0-1
.
11
-00
DATA
VAllO
'~
251
Ordering
Information
Product
Number
Package/
Temp
Speed
28090
CE
4.0 MHz
2-UPC Universal
Peripheral
Controller (40-pin)
28090
CS
DE
4.0 MHz
Same as above
DS
4.0 MHz
4.0 MHz
Same as above
Same as above
28090
PE
4.0 MHz
Same as above
28090
28091
PS
QS
4.0 MHz
4.0 MHz
Same as above
28090
28090
NOTES' C == Ceramic, D = Cercilp, P
to +70°C.
252
Product
Number
Description
Package/
Temp
Speed
28092
QS
4.0 MHz
2- UPC External
RAM-based
Program Memory
(54-pin)
28093
RS
4.0 MHz
2-UPC
2715 EPROM
Program Memory
(40-pm)
28094
RS
4.0 MHz
2-UPC RAM
Program Memory
(40-pin)
2- UPC External
ROM-based
Program Memory
(54-pin)
= PlastIc,
Q == QUIP, R
=
Description
Protopack; E
= -40'Cto +85'C.M
~
-55'Cto +125'C. S
~
O'C
OO·2017-A
More to Come
The components deSCribed m
the foregoing documents exist
now or are well along in theIr
development. These components
represent the first step of an ongoing commitment to support the
Z8000 Family. The next step is a
series of specialized processors
and peripherals that includes the
Z8016 DMA Transfer Controller
and Z8052 CRT Controller.
Z80lS DMA Transfer Controller (DTC). ThIS hIgh-speed
(2M byte/sec) versahle dualchannel DMA controller matches
the power and addressing
capabIlity of the Z8000 CPUs. It
supports a variety of system
Implementations, rangmg from
dedicated smgle-DMA configurations to distributed mulhple-DMA
configurations found m multiuser, mulh-taskmg environments.
The Z8016 DTC takes full
advantage of the Z8000 memory
management scheme because It
interfaces dIrectly to the Z8010
Memory Management Umt
(MMU). Consequently, 8M bytes
of logical address range are provided for each CPU address
space. Alternatively, the Z80l6
DTC can operate mdependently
of the Z8010 MMU and directly
address up to 16M bytes of
physical address space.
The ability to self-load control
parameters from memory enables
chamed DMA operahons of different types, and prOVides a high
degree of independence from the
CPU. Memory-to-memory data
transfers, as well as the more con-
ventional data transfer between
I/O and memory, can be
executed. Data transfers can be
in the form of smgle byte, double
byte or word, and a number of
search and match operahons can
be performed on the data.
Several dIfferent interrupt
shmull can be enabled under program control. These include
interrupts on Termmal Count
(TC), End of Process (EOP), or a
number or condlhon bits in the
Channel Mode Register. The
Z80l6 DTC operates withm the
Z8000 daISy-cham vectoredpriority mterrupt scheme.
Z8052 CRT Controller
(CRTC). The Z8052 CRTC is a
broad-applicahon, raster scan
CRT controller speCifically
designed to mterface the Z8000
CPU to a variety of CRT dIsplays.
Its numerous advanced features
SUIt a wide variety of applications
mcludmg general business and
scientific data processmg, word
processing and graphICS.
Text-editing software implementation is simplified by means
of variable vertical and horizontal
split-screen capability. Double
character-cell display with verhcal adjustment of character POSItion enhances word processmg as
well as sClenhfic and mathemahcal notation. Character
Jushfication along WIth mIxing of
fonts is achIeved by external synchronization of verhcal retrace
and variable character clock frequency. TypeWriter formatted
smgle- or mulllple-line spacing
along with oversized alpha-
numerics or memory blt-mapped
displays can be generated with
variable scan lines per character
row. Simple lme drawing
capability is also made available
with the line attributes provided.
The Z8052 CRTC's programmable register archItecture allows
easy operating configuration and
mode changes under software
program control. This contrasts
favorably to the time consuming
and costly ROM programming
methods used by other CRT
controllers.
These advanced display
features are achIeved WIth the
ability to change attributes
dynamically on a real-time baSIS.
The ability to change row
attributes in real time allows
smooth scrolling. Character attributes changmg in real time allow
multiple cursors and various
underline combmations, all WIth
indIvidual blink rates. The
character attributes control normal or double character cells for
subscripted and superscripted
display as well as the line attributes used for lme drawing. This
allows intermIxing of forms and
text displays for various
applications.
DynamiC change of attributes is
achIeved by storing the data for
changmg attributes in parallel
WIth the displayed character data.
Data transfers from main memory
to the CRTC are under the control of a fleXIble DMA function
built mto the Z8052. Bus activity
is minimized by the mclUSlOn of
full two-line buffermg on the
Z8052 CRT Controller.
253
Universal Peripherals
.... ilog
Universal Peripherals
~
Zilog
Two Versions Extend
Range of Applications
March 1981
Zilog's Universal Peripheral
Components Family is more than a
group of simple I/O circuits-they
are intelligent, fully programmable
devices capable of performing
complicated tasks independently.
TheIr capabilities unburden the
master CPU, reduce bus traffic,
increase system throughput, and
greatly simplify overall system
hardware design requirements.
The peripheral components,
where needed, are produced in
two versions to increase theIr
range of application. One verSIon,
identified by the number Z80xx, is
capable of interfacing with Zilog's
multiplexed Z-BUS only or with
both the Z-BUS and conventional
mulhplexed buses. The second version, identified by the number
Z85xx, is capable of interfacing
with conventional non-multiplexed
buses.
All of the peripheral components
are extenSively programmable to
permit each to be tailored to its
own application(s). All Z-BUS per-
ipherals share common interrupt
and bus-request structures; they
can also be operated in either
a priority-interrupt or polled
environment.
Counting, timmg, and parallel
I/O transfer problems are easily
solved using the Z8036/28536 CIO
Counter/Timer and I/O Unit. ThIs
component has three 16-blt
counter/timers, three I/O ports,
and can double as a programmable
prionty-interrupt controller.
Data communications problems
are neatly handled by the Z8030/
28530 SCC Serial Communications
Controller. This device is a senal,
dual-channel, multi-protocol controller which supports all popular
communications formats. The SCC
supports virtually all serial data
transfer applications.
Interface problems with the
interconnection of major components withm an asynchronous,
parallel processor system can be
solved using the 28038 2-FIO FIFO
I/O Interface Unit. This generalpurpose interface unit provides
expandable, bIdirectional buffering between asynchronous CPU s in
a parallel processing network, or
between a CPU and peripheral circuits and/or devices. The Z-FIO
can be used with systems having
either multiplexed or nonmultiplexed buses.
General-purpose control and
data manipulation problems are
easily handled by the Z8034/Z8534
UPC Universal Peripheral Controller. The UPC is a complete
microcomputer designed for offline applications. This microcomputer executes the same fnendly,
capable instruction set as Zilog's Z8
microcomputer; it has three I/O
ports, six levels of priorityinterrupt, and 2K bytes of memory
on chip. The UPC is intended for
applicahons that requIre an intelligent peripheral controller whICh
can assume many of the tasks normally reqUIred of the master CPU.
257
Z8530 SCC Serial
Communications
Controller
~
Zilog
Product
Specification
February 1981
Features
• Two independent, 0 to 1M biVsecond, fullduplex channels, each with a separate
crystal oscillator, baud rate generator, and
Digital Phase-Locked Loop for clock
recovery.
II
Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
General
Description
The Z8530 SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use With conventional non-multiplexed buses.
The SCC functions as a serial-to-parallel,
parallel-to-serial converter/controller. The
SCC can be software-configured to satisfy a
• Synchronous mode with internal or external
character synchronization on one or two
synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
III
SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
wide variety of serial communications applications. The device contains a variety of new,
sophisticated internal functions including
on-chip baud rate generators, Digital PhaseLocked Loops, and crystal oscillators that
dramatically reduce the need for external
logic.
0,
0,
0,
D.
DATA BUS
0,
CH·A
0,
WIREOA
0,
BUS { ------.
TIMING
AND RESET
CONTROL
INTERRUPT
1=
--.
1==
CHANNEL
CONTROLS
DTRIREQA
FOR MODEM,
0,
RTSA
Rii
DMA,OR
eTSA
OTHER
WR
DeOA
AlB
TxDB
CE
RxDB
ole
iN!
TRxeB
INTACK
SYNCS
sec
D.
0,
0,
iNT
Rii
lEO
WR
lEI
AlB
INTACK
CE
+5V
AheA
R)(OA
TRxCA
CHANNEL
CONTROLS
FOR MODEM,
DTRIREQB
Z8530
0,
SYNCA
WIREQB
lEI
0,
0,
WIREQA
RTxCB
lEa
0,
0,
RTsB
else
~
DeDe
~
DMA,OR
OTHER
CH-B
TxOA
OTRIREQA
RTSA
ole
aND
W/REQe
SYNCe
RlxeB
RxOB
TAxeB
TxDB
OTRIREQB
elSA
RTse
DeOA
CTsB
PCLK
DeDB
t t
+5V
GND PClK
Figure 1. Pin Functions
20nOOl. 002
Figure 2. Pin Assignment.
259
fft
t"lI
t"lI
General
Description
(Continued)
Pin
Description
The SCC handles asynchronous formats,
Synchronous byte-oriented protocols such as
IBM Bisync, and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
The device can generate and check CRC
codes in any Synchronous mode and can be
programmed to check data integrity in various
modes. The SCC also has facilities for
modem controls in both channels. In applications where these controls are not needed,
the modem controls can be used for
general-purpose I/O.
The Z-Bus daisy-chain interrupt hierarchy is
also supported-as is standard for Zilog
peripheral components.
The Z8530 SCC is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.
The following section describes the pin
functions of the SCC. Figures 1 and 2 detail
the respective pin functions and pin
assignments.
lEO. Interrupt Enable Out (output, active
AlB. Channel A/Channel B Select (input).
This signal selects the channel in which the
read or write operation occurs.
CEo Chip Enable (input, active Low). This
signal selects the SCC for a read or write
operation.
CTSA. CTSB. Clear To Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables the
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The SCC detects pulses on these inputs and
can interrupt the CPU on both logic level
transitions.
D/C. Data/Control Select (input). This signal
defines the type of information transferred to
or from the SCC. A High means data is
transferred; a Low indicates a command.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accomodate slow
rise-time signals. The SCC detects pulses on
these pins and can interrupt the CPU on both
logic level transitions.
DD-D.,. Data Bus (bidirectional, 3-state). These
lines carry data and commands to and from
the SCC.
DTR/REQA. DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
lEI is used with IEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
260
High). lEO is High only if lEI IS High and the
CPU is not servicing an SCC interrupt or the
SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). lEO is connected to
the next lower priority device's IEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain.
active Low). This signal is activated when the
SCC requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
SCC interrupt daisy chain settles. When RD
becomes active, the SCC places an interrupt
vector on the data bus (if lEI is High).
INTACK is latched by the rising edge
of PCLK.
PCLK. Clock (input). This is the master SCC
clock used to synchronize internal signals
PCLK is a TTL level signal.
RD. Read (input, active Low). This signal indicates a read operation and when the SCC is
selected. enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus
if the SCC is the highest priority device
requesting an interrupt.
RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock for the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be 1, 16, 32, or 64 times the
data rate in Asynchronous modes.
RTSA. RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 11) is set, the
RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto
Pin
Description
(Continued)
Functional
Description
Enable is on, the signal goes High after the
transmitter is empty. In Synchronous mode or
in Asynchronous mode with Auto Enable off,
the RTS pin strictly follows the state of the RTS
bit. Both pins can be used as general·purpose
outputs.
SYNCA, SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either
as inputs, outputs, or part of the crystal
oscillator circuit. In the Asynchronous Receive
mode (crystal oscillator option not selected),
these pins are inputs similar to CTS and DCD.
In this mode, transitions on these lines affect
the state of the Synchronous/Hunt status bits in
Read Register 0 (Figure 10) but have no other
function.
In External Synchronization mode with the
crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be
driven Low two recel'ie clock cycles after the
last bIt in the synchronous character is
received. Character assembly begins on the
rising edge of the receive clock immediately
preceding the activation of SYNC.
In the Internal Synchronization mode
(Monosync and Bisync) with the crystal
oscillator not selected, these pins act as outputs and are active only dunng the part of the
receive clock cycle in whICh synchronous
characters are recognized. The synchronous
condition is not latched, so these outputs are
active each time a synchronization pattern is
recognized (regardless of character boundaries). In SDLC mode, these pins act as
outputs and are valid on receipt of a flag.
TxDA, TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.
--- --TRxCA, TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the output of the DIgital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output
mode.
Ul
is selected, this signal indicates a write
operation. The coincidence of RD and WR is
interpreted as a reset.
n
W/REQA, W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The
reset state is Wait.
The functional capabilities of the SCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data m a wide
variety of data communications protocols; as a
microprocessor peripheral, the SCC offers
valuable features such as vectored interrupts,
polling, and simple handshake capabtlity.
following description briefly detail these
protocols.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
Data Communications Capabilities. The
SCC provides two independent full-duplex
channels programmable for use in any common Asynchronous or Synchronous datacommunication protocol. Figure 3 and the
sr
WR. Write (input, active Low). When the SCC
PARITY
~r
~MA~R~KlN~G~l~'N~E--~1 rl-DA-T-A~141"~I=I=DA=T=A=I=I~'~II
DATA
II'
, MARKING LINE
ASYNCHRONOUS
DATA
SYNC
::
::
I
DATA
CRe,
CRC2
DATA
CRe,
CRC2
DATA
CRe,
CRC2
CRe,
CRC2
MONOSYNC
SYNC
DATA
SYNC
SIGNAL
I
+
DATA
BISYNC
~:
EXTERNAL SYNC
FLAG
I ADDRESS I
INFO~M:TION
FLAG
SDLCIHDLCIX.25
Figure 3. Some
2042·108
see Protocols
261
n
Functional
Description
(Continued)
mechanism that checks the signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure 1). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The SCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of I, 1116, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
Synchronous Modes. The SCC supports both
byte-oriented and bit-oriented synchronous
communication. Synchronous byte-oriented
protocols can be handled in several modes,
allowing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync).
any 12-bit synchronization pattern (Bisync), or
with an external synchronous signal. Leading
sync characters can be removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the SCC
by overlapping the larger pattern across multiple incoming synchronous characters as shown
in Figure 4.
CRC checking for Synchronous byteoriented modes is delayed by one character
time so that the CPU may disable CRC checking on speCific characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-16 (X 16 + XI5 + X2 + 1) and
CCITT (X16 + XI2 + X5 + I) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all as. The SCC also provides a feature that automatically transmits
CRC data when no other data is available for
5 BITS
~
SYN~
I
SYNC,
I
transmission. This allows for high speed
transmissions under DMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in Synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous
characters, regardless of the programmed
character length.
The SCC supports Synchronous bit-oriented
protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion,
and CRC generation. A special command can
be used to abort a frame in transmission. At
the end of a message, the SCC automatically
transmits the CRC and trailing flag when the
transmitter underruns. The transmitter may
also be programmed to send an idle line consisting of continuous flag characters or a
steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The SCC may also be
programmed to send an abort itself in case of
an underrun, relieving the CPU of this task.
One to eight bits per character can be sent,
allOWing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be
programmed to search for frames addressed by
a single byte (or four bits within a byte) of a
user-selected address or to a global broadcast
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
rec"eiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (endof-frame) can be selected. The receiver
automatically deletes all as inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SDLC
mode, the SCC must be programmed to use
the SDLC CRC polynomial, but the generator
, and checker may be preset to all Is or all as.
DATA
DATA
DATA
DATA
Figure 4. Detecting 5- or 7-Bit Synchronous Character.
262
2042·109
Functional
Description
(Continued)
The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any
Ix mode. The parity options available in Asynchronous modes are available in Synchronous
modes.
The SCC can be conveniently used under
DMA control to provide high speed reception
or transmission. In reception, for example, the
SCC can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The SCC then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received. The CPU may also enable the
DMA first and have the SCC interrupt only on
end-of-frame. This procedure allows all data to
be transferred via the DMA.
SOLe Loop Mode. The SCC supports SDLC
Loop mode in addition to normal SDLC. In an
SDLC Loop, there is a primary controller
station that manages the message traffic flow
on the loop and any number of secondary
stations. In SDLC Loop mode, the SCC performs the functions of a secondary station
while an SCC operating in regular SDLC
mode can act as a controller (Figure 5).
A secondary station in an SDLC Loop is
always listening to the messages being sent
around the loop, and in fact must pass these
messages to the rest of the loop by retransmitting them with a one-bit-time delay. The
secondary station can place its own message
on the loop only at specific times. The controller signals that secondary stations may
transmit messages by sending a special
character, called an EOP (End Of Poll),
around the loop. The EOP character is the bit
pattern 11111110. Because of zero insertion
during messages, this bit pattern is unique and
easily recognized.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0
before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop
and terminates the message with an EOP. Any
secondary stations further down the loop with
messages to transmit can then append their
messages to the message of the first secondary
station by the same process. Any secondary
stations without messages to send merely echo
the incoming messages and are prohibited
from placing messages on the loop (except
upon recognizing an EOP).
SDLC Loop mode is a programmable option
in the SCC. NRZ, NRZI, and FM coding may
all be used in SDLC Loop mode.
Baud Rate Generator. Each channel in the
SCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a l6-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receIve clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The followmg formula relates the time constant to the baud rate (the baud rate IS in
bits/second and the BR clock penod is in
seconds):
baud rate =
2 (hme constant + 2) x
(BR clock perIod)
Digital Phase-Locked Loop. The SCC contains a Digital Phase-Locked-Loop (DPLL) to
recover clock informahon from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses thIS
clock, along with the data stream, to construct
a clock for the data. ThIS clock may then be
used as the SCC receIve clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
Figure 5. An SDLe Loop
2016-001
263
Functional
Description
(Continued)
incoming data stream for edges (either I to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but wIth a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
o. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transi tion.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the SCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding. The SCC may be programmed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encoding, a 1 is represented by a High level
and a 0 is representeq by a Low level. In NRZI
encoding, a I is represented by no change in
level and a 0 is represented by a change In
level. In FMI (more properly, bi-phase mark).
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bl-phase space).
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a I
is represented by no additional transition at
the center of the bIt cell. In addition to these
four methods, the SCC can be used to decode
Manchester (bi-phase level) data by using the
DPLL in the FM mode and programming the
receiver for NRZ data. Manchester encoding
always produces a transition at the center of
the bit cell. If the transition is 0 to I, the bit is
a o. If the transition is I to 0, the bit is a 1.
Auto Echo and Local Loopback. The SCC is
capable of automatically echoing everything it
receives. This feature is useful mainly in
Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto
Echo mode, TxD is RxD. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The SCC is also capable of local loopback.
In this mode TxD is RxD, just as in Auto Echo
mode. However, in Local Loopback mode, the
internal transmit data is tied to the internal
receive data and RxD is ignored (except to be
echoed out via TxD). The CTS and DCD
inputs are also ignored as transmit and receive
enables. However, transitions on these inputs
can still cause interrupts. Local Loopback
works in Asynchronous, Synchronous and
SDLC modes with NRZ, NRZI or FM coding of
the data stream.
I/O Interface Capabilities. The SCC offers
the choice of Polling, Interrupt (vectored or
non vectored) , and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the SCC are automatically
updated whenever any function is performed.
For example, end-of-frame in SDLC mode
sets a bit in one of these status registers. The
idea behind polling is for the CPU to
periodically read a status register until the
register contents indicate the need for data to
be transferred. Only one register needs to be
DATA
NRZ
NRZI
\
\
/
I
\
\
FM1
FMO
MANCHESTER
Figure 6. Data Encoding Methoda
264
2016-002
Functional
Description
(Continued)
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. When an SCC responds to an
Interrupt Acknowledge signal (INTACK) from
the CPU, an interrupt vector may be placed on
the data bus. This vector is written in WR2 and
may be read in RR2A or RR2B (Figures 10
and 11).
To speed interrupt response time, the SCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the lE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MlE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
lE bits are write only.
The other two bits are related to the interrupt priority chain (Figure 7). As a
microprocessor peripheral, the SCC may
request an interrupt only when no higher
priority device is requesting one, e.g., when
lEI is High. If the device in question requests
an interrupt, it pulls down INT. The CPU then
responds with INTACK, and the interrupting
device places the vector on the data bus.
In the SCC, the IP bit signals a need for
interrupt servicing. When an IP bit is 1 and
the lEI input is High, the INT output is pulled
Low, requesting an interrupt. In the SCC, if
the lE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the SCC and
PERIPHERAL
lEI Do-Or
iNT
external to the SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the lEO output of the SCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
mterrupt type is enabled under program control with Channel A having hIgher priority
than Channel B, and wIth Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmIt buffer becomes
empty. (This implies that the transmitter must
have had a data character wrItten into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU m one of three
ways:
• Interrupt on First Receive Character or
Special Receive Condition.
• Interrupt on All Receive Characters or
Special Receive Condition.
• Interrupt on SpeCIal Receive ConditIOn
Only:
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is one of
the follOWing: receiver overrun, framing error
in Asynchronous mode, end-of-frame m SDLC
mode and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receIVe character available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First ReceIve Character, an interrupt can occur from Special Receive Conditions any hme after the first receive character
interrupt.
The main funchon of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins; however, an
PERIPHERAL
INTACK lEO
lEI 00-01
!NT
PERIPHERAL
INTACK lEO
+5V
DO-D7\r____________________________________________
~
INT~----------~~4_--------------~_+--------------~--+_~
~ACK~--------------4-----------------~
________________~
Figure 7. Interrupt Schedule
2023·003
265
Functional
Description
(Continued)
External/Status interrupt is also caused by a
Transmit Underrun condItion, or a zero count
in the baud rate generator, or by the detection
of a Break (Asynchronous mode). Abort (SDLC
mode) or EOP (SDLC Loop mode) sequence in
the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing
the SCC to interrupt when the Abort or EOP
sequence is detected or terminated. This
feature facilitates the proper termination of the
current message, correct initialization of the
next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature allows
secondary stations to recognize the wishes of
the primary station to regain control of the
loop during a poll sequence.
CPU/DMA Block Transfer. The SCC provides
a Block Transfer mode to accommodate CPU
block transfer functions and DMA controllers.
The Block Transfer mode uses the WAITI
REQUEST output in conjunction with the
Wait/Request bits in WRl. The WAITI
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the SCC REQUEST
output indicates that the SCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the SCC is not
ready to transfer data, thereby requesting that
the CPU extend the 1/0 cycle. The DTRI
REQUEST line allows full-duplex operation
under DMA control.
Architecture
The SCC internal structure includes two fullduplex channels, two baud rate generators,
internal control and interrupt logic, and a bus
interface to a nonmultiplexed bus. Associated
with each channel are a number of read and
write registers for mode control and status
information, as well as logic necessary to interface to modems or other external devices
(Figure 8).
The logic for both channels provides
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two synccharacter (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
. . . - } SERIAL DATA
CHANNEL A
. . - - } CHANNEL CLOCKS
---
INTERNAL
CONTROL
;;;~~~~;~/R=EQ=U=ES=T
lOGIC
DISCRETE
CONTROL
& STATUS
A
DATAy=>
:= }
MODEM, DMA, OR
OTHER CONTROLS
CPU
BUS 110
CONTROL
Y=>L-__-'
INTERRUPT
CONTROL
LINES
-}
MODEM, OMA, OR
OTHER CONTROLS
INTERRUPT
CONTROL
LOGIC
} SERIAL DATA
ttt
. - } CHANNEL CLOCKS
SYNC
WAIT/REQUEST
+5VGNDPCLK
Figure 8. Block Diagram 01
266
see Architecture
2016-040
~
0;
o~
o n
~
::!.e:
S' i'
c n
rop.S::
-
~;
CPU 110
BA GENERATOR
INPUT
BR GENERATOR
OUTPUT
TRANSMIT
CLOCK
R,D
CPLl
_I
I CAe RESULT
I
~
-----<---1.
TRx.C -----<--1
BA GENERATOR OUTPUT
DPLL OUTPUT
RECEIVE CLOCK
CLOCK
TRANSMIT CLOCK
MUX
RhC-.......---<~
DPLl CLOCK
BA GENERATOR CLOCK
SYNC
(OSCILLATOR)
tv
(J)
'-J
Figure 9. Data Path
33S
Architecture
(Continued)
write only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRI5 - Write Registers 0 through 15.
RRO-RR3, RRIO, RRI2, RRI3, RRI5 - Read
Registers 0 through 3, 10, 12, 13, IS.
Table I lists the functions assigned to each
read or write register. The SCC contains only
one WR2 and WR9, but they can be accessed
by either channel. All other registers are
paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Figure 9 is identical for both
channels. The receiver has three 8-bit buffer
regIsters in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths (data or CRC)
depending on the selected mode (the character
length in Asynchronous modes also determines
the data path).
The transmitter has an 8-bit Transmit Data
buffer regIster loaded from the internal data
bus and a 20-bit Transmit Shift register that
can be loaded either from the synchronous
character registers or from the Transmit Data
regIster. Depending on the operational mode,
outgoing data is routed through one of four
main paths before it is transmitted from the
Transmit Data output (TxD)
Programming
268
The SCC contains 13 write registers in each
channel that are programmed by the system
separately to configure the functional personality of the channels.
In the SCC, register addressing is direct for
the data registers only, which are selected by
a HIgh on the Die pin. In all other cases (with
the exception of WRO and RRO), programming
the write registers requires two write operations and reading the read registers requires
both a write and a read operation. The first
write IS to WRO and contains three bits that
pomt to the selected register. The second write
is the actual control word for the selected
register, and if the second operation is read,
Read Register Functions
RRO
RRI
RR2
TransmIt/ReceIve buffer status and External status
SpecIal ReceIve Condlhon status
ModIfIed mterrupt vector (Channel B only)
UnmodIfIed mterrupt vector (Channel A only)
RR3
Interrupt Pending bIts (Channel A only)
RR8
RRIO
RRl2
RRl3
RRl5
ReceIve buffer
MIscellaneous status
Lower byte of baud rate generator hme constant
Upper byte of baud rate generator hme constant
External/Status Interrupt mformatIon
Write Register Functions
WRO
eRe
WRI
TransmIt/ReceIve mterrupt and data transfer mode
definition
WR2
WR3
WR4
InitIalIze, InitIalIzation commands for the
various modes, Register POinters
Interrupt vector (accessed through either channel)
ReceIve parameters and control
TransmIt/ReceIve mIscellaneous parameters and
modes
WR5
TransmIt parameters and controls
WR6
Sync characters or SDLC address held
WR7
WR8
WR9
TransmIt buffer
WRIO
MIscellaneous transmItter/receIver control bIts
WRII
WRl2
WR13
WRl4
WRl5
Clock mode control
Sync
charact~r
or SDLC flag
Master mterrupt control and reset (accessed
through eIther channel)
Lower byte of baud ,rate generator hme constant
Upper byte of baud rate generator hme constant
MIscellaneous control bIts
External/Status mterrupt control
Table I. Read and Write Register Functions
the selected read register is accessed. All of
the registers in the SCC, including the data
registers, may be accessed in this fashion. The
pOinter bits are automatically cleared after the
read or write operation so that WRO (or RRO) is
addressed again.
The system program first issues a series of
commands to initialize the basic mode of
operation. This is followed by other commands
to qualify conditions within the selected mode.
For example, the Asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first.
Then the interrupt mode would be set, and
finall y, receiver or transmitter enable.
Programming Read Registers. The SCC contains eight read
(Continued)
registers (actually nine, counting the receive
buffer (RR8) in each channel). Four of these
may be read to obtain status information (RRO,
RRl, RRIO, and RRIS). Two registers (RRI2
and RRI3) may be read to learn the baud rate
generator time constant. RR2 contains either
the unmodified interrupt vector (Channel A) or
the vector modified by status information
Read Register 0
Read Register 10
~ R,CHARACTERAVAILASLE
ll!~~
L
(Channel B). RR3 contains the Interrupt Pending (IP) bits (Channel A). Figure 10 shows
the formats for each read register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a smgle
register (RRI).
ZERO COUNT
Tx BUFFER EMPTY
DCD
SYNC/HUNT
CTS
Tx UNDERRUN/EOM
ll!~~~~~:::,~~
ONE CLOCK MISSING
BREAK/ABORT
Read Register 1
Read Register 12
10 , ! 0, I 0, I 0, I 0, I 0, I 0, I 0, I
L ~ALLSENTcooe
ll!~~
~~
RESIDUE CODe 2
RESIDUE
1
RESIDUE
cooe 0
PARITY ERROR
Rx OVERRUN ERROR
CRe/FRAMING ERROR
LOWER BYTE OF
TIME CONSTANT
TC,
END OF FRAME (SDLe)
Read Register 2
Read Register 13
UPPER BYTE OF
INTERRUPT VECTOR'
TIME CONSTANT
"MODIFIED IN B CHANNEL
Read Register 3
ll!~~
L~
Read Register 15
CHANNELS EXTISTATIP'
CHANNEL B Tx IP'
CHANNEL B Ax Ip·
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP*
CHANNEL A Ax IP'
o
o
'ALWAYS 0 IN B CHANNEL
Figure 10. Read Register Bit FUDctions
2016-005
269
Programming Write Registers. The SCC contains 13 write
registers (14 counting WR8, the transmit
(Continued)
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
Write Register 0
o
Write Register 3
o
0
0
REGISTER 0
o
o
o
0
1
REGISTER 1
1
0
REGISTER 2
1
1
REGISTER 3
0
REGISTER 4
I
~~
L
LR'ENABLE
0
0
REGISTER 5
1
1
REGISTER 6
o
Rx 5 BITS/CHARACTER
1
1
1
REGISTER 7
o
1
Rx 7 BITS/CHARACTER
0
0
REGISTER 8
1
0
Rx 6 BITS/CHARACTER
0
0
1
REGISTER 9
1
1
Rx 8 BITS/CHARACTER
0
1
0
REGISTER 10
1
1
REGISTER 11
1
0
0
REGISTER 12
1
0
REGISTER 13
1
1
1
REGISTER 14
1
1
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
AUTO ENABLES
0
0
0
SYNC CHARACTER LOAD INHIBIT
ENTER HUNT MODE
1
1
)
Write Register 4
I
REGISTER 15
o
0
0
NULL CODe
o
o
o
0
1
POINT HIGH
1
1
0
RESET EXT/STAT INTERRUPTS
SEND ABORT (SOLe)
1
0
ENABLE INT ON NEXT Rx CHARACTER
1
0
1
WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits. Figure
11 shows the format of each write register.
I L
L
PARITY ENABLE
PARITY EVEN/ODD
o
0
SYNC MODES ENABLE
o
1
1 STOP BtTlCHARACTER
1
0
1 '12 STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
RESET TxlNT PENDING
o
ERROR RESET
1
RESET HIGHEST IUS
NULL CODE
o
0
8 BIT SYNC CHARACTER
o
1
16 BIT SYNC CHARACTER
o
SOLC MODE (01111110 FLAG)
1
EXTERNAL SYNC MODE
1
1
RESET Ax CRe CHECKER
1
0
RESET Tx CRe GENERATOR
1
1
RESET Tx UNDERRUN/EOM LATCH
·WITH POINT HIGH COMMAND
o
0
Xl CLOCK MODE
o
1
X16 CLOCK MODE
1
0
X32 CLOCK MODE
1
1
X64 CLOCK MODE
Write Register 1
Write Register 5
L
~
L
EXT INT ENABLE
I ~ :~:RC ENABLE
L
~
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
•
o
0
Rx tNT DISABLE
o
1
Rx tNT ON FIRST CHARACTER OR SPECIAL CONDITION
1
0
tNT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
1
Rx INT ON SPECIAL CONDITION ONLY
SDLC/CRC 16
Tx ENABLE
SEND BREAK
' - - - - - - WAIT/DMA REQUEST ON RECEIVE/TRANSMIT
' - - - - - - - WAIT/OMA REQUEST FUNCTION
' - - - - - - - - WAITIDMA REQUEST ENABLE
o
0
o
1
Tx 7 BITS/CHARACTER
1
0
Tx 6 BITS/CHARACTER
1
1
Tx 8 BITS/CHARACTER
Tx 5 BITS (OR LESS)lCHARACTER
,
' - - - - - - - - OTR
Write Register 2
Write Register 6
INTERRUPT
VECTOR
SYNC7
SYNCt
SYNC7
SYNC3
ADR7
ADR7
SYNCs
SYNCe
SYNCs
SYNC2
ADRs
AORs
SYNCs
SYNCs
SYNCs
SYNC1
ADRs
ADRs
SYNC4
SYNC4
SYNC4
SYNCo
ADR4
AOR4
SYNC3
SYNC 3
SYNC3
SYN C2
SY NC2
SYNC2
SYNCt
SYNC1
SYNC1
SYNCe
SYNCe
SYNCe
1
1
1
1
,
ADR2
,
ADRl
,
ADRe
ADR3
MONOSYNC, 8 BITS
MONOSYNC,6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC
(ADDRESS RANGE)
Figure 11. Write Register Bit Functions
270
2016·00n ?W:1·01 0
Programming
Write Register 7
(Continued)
SYNCr
SYNCs
SYNC,s
SYNC!1
o
SYNCs
SYNC 4
SYNC14
SYNCIO
1
SYNCs
SYN C3
SYNC 13
SYNCg
1
SYNC,
SYNCz
SYNC1z
SYNCs"
1
SYNC3
SYNC 1
SYNC ll
SYNC1
1
SYNCz
SYNCo
SYNClO
SYNCS
1
SYNC1
SYNCo
SYNC9
SYNCs
1
SYNCa
SYNC4
MONOSYNC, B BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
,
o
Write Register 9
Write Register 12
1~!~I~!~;~:~:~:~1
10,10.10,10.10,10, I 0, I Do 1
I~~~c
~MIE
~
~TATUS HIGHISTATUSYOW
o
0
NO RESET
o
1
CHANNEL RESET B
1
0
CHANNEL RESET A
1
1
FORCE HARDWARE RESET
~~
LOWER BYTE OF
TIME CONSTANT
Write Register 13
Write Register 10
10,I 0.1 0, I0.1 0, I0, I 0, IDol
~~
L' BiTl8lffi SYNC
UPPER BYTE OF
TIME CONSTANT
LOOP MODE
ABORTIFLAG ON UNDERRUN
MARK/FLAG IDLE
GO ACTIVE ON POLL
o
0
o
1
NRZI
1
0
FMl (TRANSITION = 1)
1
1
FMO (TRANSITION = OJ
NRZ
Write Register 14
' - - - - - - - - CRC PRESET 110
L
~~
L BR GENERATOR ENABLE
Write Register 11
1
BR GENERATOR SOURCE
DTRIREQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK
0
0
fA'" OUT = XTAL OUTPUT
0
0
0
NULL COMMAND
o
1
TAiC OUT"" TRANSMIT CLOCK
0
0
1
ENTER SEARCH MODE
1
0
TRxC OUT = BR GENERATOR OUTPUT
0
1
0
RESET MISSING CLOCK
1
1
TRxC OUT = DPLL OUTPUT
0
1
1
DISABLE DPlL
1
0
0
SET SOURCE = SR GENERATOR
SET SOURCE = RTxC
TRxC 011
1
0
1
o
0
TRANSMIT CLOCK", RTxC PIN
1
1
0
SET FM MODE
o
1
TRANSMIT CLOCK = TRxC PIN
1
1
1
SET NRZI MODE
1
0
TRANSMIT CLOCK = BR GENERATOR OUTPUT
1
1
TRANSMIT CLOCK"" DPLL OUTPUT
Write Register 15
o
0
RECEIVE CLOCK :: RTxC PIN
o
1
RECEIVE CLOCK = TAXC PIN
1
0
RECEIVE CLOCK = BR GENERATOR OUTPUT
1
1
RECEIVE CLOCK:: DPLL OUTPUT
10, I 0.1 0, I0.1 0, I0, I 0, IDo 1
L _ _ _ _ _ _ _ RTxC XTAUNO XT7il
Figure 11. Write Register Bit Functions (Contmued)
2016·006
271
Timing
The SCC generates internal control signals
from WR and RD that are related to PCLK.
Since PCLK has no phase relationship with
WR and RD, the circuitry generating these
internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the SCC. The recovery time
required for proper operation is specified from
the rising edge of WR or RD in the first trans-
action involving the SCC to the falling edge of
WR or RD in the second transaction involving
the SCC. This time must be at least 6 PCLK
cycles plus 200 ns.
Read Cycle Timing. Figure 12 illustrates
Read cycle timing. Addresses on AlB and Die
and the status on INTACK must remain stable
throughout the cycle. If CE falls after RD falls
or if it rises before RD rises, the effective RD is
shortened.
X
AlB, Die _ _- J ' -_ _ _ _
ADDRESS
VALID
~
_
_ _ _ _"
---
\'----
1
\
DO-D7
\'--____--11
------------« ......___ X
)~---DATA VALID
.J
Figure 12. Read Cycle Timing
Write Cycle Timing. Figure 13 illustrates
Write cycle timing. Addresses on AlB and Die
and the status on INTACK must remain stable
AlB,
throughout the cycle. If CE falls after WR falls
or if it rises before WR rises, the effective WR
is shortened.
X
ole _ _- J ......_ _ _ _
~ODRESS
VALID
~
_
_ _ _ _"
--
\'--1
\
\I..... _ _ _ _......JI
Do-D7
-...J»)-----
---------«'-_____
D_AT....
A_VA_L_ID_ _ _ _
Figure 13. Write Cycle Timing
Interrupt Acknowledge Cycle Timing. Figure
14 illustrates Interrupt Acknowledge cycle
timing. Between the time INTACK goes Low
and the falling edge of RD, the internal and
external lEI/lEO daisy chains settle. If there is
an interrupt pending in the SCC and IEI is
INTACK
High when RD falls, the Acknowledge cycle is
intended for the SCC. In this case, the SCC
may be programmed to respond to RD Low by
placing its interrupt vector on Do-D7 and it
then sets the appropriate Interrupt- UnderService latch internally.
\1.....------1i,I---------------...J
I~'--_ _ _--I
Do-D7
----«
------II,f-'
oJ
1..._ _ _
Figure 14. Interrupt Acknowledge Cycle Timing
272
2023-003, 004, 005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3Vto +7.0V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Stresses greater than those hsted under Absolute MaxImum Ratmgs may cause permanent damage to the devIce.
Thls 15 a stress ratmg only; operatIon of the devIce at any
condItion above those mdicated In the operahonal sections
of these specIhcahons is not Imphed. Exposure to absolute
maXImum ratmg condihons for extended penods may affect
device rehabIhty.
Storage Temperature ........ -65°C to + 150 °C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
•
+4.75 V :5 Vee :5 +5.25 V
• GND = OV
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+5 V
+5V
2.1K
FROM OUTPUT
UNDER TEST
~ 2'2K
(12
n
n
r
OPF
Figure 15. Standard Test Load
DC
Characteristics
Figure 16. Open-Drain Test Load
Parameter
Min
Max
Unit
VIH
Input HIgh Voltage
2.0
V1L
VOH
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
Vee +0.3
0.8
V
V
V
V
p.A
p.A
rnA
Symbol
VOL
IlL
1m
ICC
-0.3
2.4
0.4
± 10.0
± 10.0
250
Condition
IOH =
IOL =
0.4 ,;;
0.4 ,;;
-250 p.A
+2.0 rnA
VlN ,;; + 2.4V
VOUT ';; +2.4V
Vee = 5 V ± 5% unless otherwIse speclfIed, over specIfied temperature range.
Capacitance
Symbol
C IN
COUT
CliO
f
8085-006. 00 I
=
Parameter
Input Capacitance
Output Capacitance
BIdIrectional CapacItance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
Unmeasured Pins
Returned to Ground
1 MHz, over specIhed temperature range.
273
Read and
Write
PCLK
Timing
~~~ r-w ~.----.
AlB, ole
~
-Y--<)---l
Figure 9. Pulsed Handshake
288
The pattern specified in the Pattern Definition register assumes that the data path IS programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
specified. Output bits used in the patternmatch logic are internally sampled before the
invertlnoninvert logIc.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as 1/0 for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the invertlnoninvert
logic) in all cases except for simple inputs with
I's catchers. In this case, the output of the I's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports specified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transition from a no-match to a match state is
not required.
The pattern-recognition logic of bit ports
operates in two basic modes: transparent and
latched. When the Latch on Pattern Match
(LPM) bit is set to (Transparent mode), the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = I), the state of all the
port inputs at the time the interrupt was
generated is latched in the input register and
held until IP is cleared. In all cases, the PMF
indicates the state of the port at the time it is
read.
If a match occurs while IP is already set, an
error condition exists. If the Interrupt On Error
bit (IOE) is 0, the match is ignored. However,
If IOE is I after the first IP is cleared, it is
automatically set to I along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP is cleared.
When a pattern-match is present m the ORPriority Encoded Vector mode, IP is set to l.
The IP cannot be cleared until a match is no
longer present. If the interrupt vector IS allowed to include status, the vector returned during Interrupt Acknowledge indicates the
highest priority bit matching its specificahon at
the time of the Acknowledge cycle. Bit 7 is the
highest priority and bIt is the lowest. The bit
mltially causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the
°
°
2014007
Functional
Description
(Continued)
Acknowledge cycle is initiated, the vector is
frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the l's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection is
performed in this mode, and the Interrupt On
Error bit should be set to O.
Function
C/TJ
CIT2
C/T3
Counter/Timer Output
PB 4
PB 0
PCO
Counter Input
PB 5
PB I
PC I
Tngger Input
PB 6
PB 2
PC 2
Gate Input
PB 7
PB 3
PC 3
Table 2. Counter/Timer External Access
Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logIC
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logIC controls the PatternMatch Flag (PMF). The data IS compared wIth
the match pattern when it IS shIfted from the
Buffer register to the Input regIster (input port)
or when It IS shIfted from the Output register to
the Buffer register (output port). The pattern
match logIC can overnde the handshake logic
in certain sltuahons. If the port IS programmed
to mterrupt when two bytes of data are
avaIlable to be read or written, but the hrst
byte matches the speclhed pattern, the
pattern-recogmtion logIC sets IP and generates
an mterrupt. WhIle PMF IS set, IP cannot be
cleared by reading or wnting the data
regIsters. IP must be cleared by command.
The mput regIster IS not emptied while IP is
set, nor IS the output regIster filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bIt IS
set, IP is set only when the data matches the
pattern. ThlS IS useful m DMA-type application
when mterrupts are required only after a block
of data is transferred.
Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant regIster, a 16-bit Current Counter
register, an 8-bit Mode Specification register,
an 8-bit Command and Status register, and the
associated control logic that links these registers.
The flexibility of the counter/timers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate input,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer l's external I/O lines are prOVided by
the four most Significant bits of Port B.
Counter/Timer 2's are provided by the four
least significant bits of Port B. Counter/Timer
3's external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode SpeCification
registers.
When external counter/timer I/O lines are
to be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as Simple input
lines. They can be speCified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the l's catcher mput.
Counter/Timers 1 and 2 can be linked internally in three different ways. Counter/Timer
l's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilihes as when used separately. The
only restrichon is that when Counter/Timer 1
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles avaIlable for the
hmer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/
timer waveforms. When the Pulse mode
PCLK/2 OR
COUNTER INPUT
TRIGGER
~
GATE
I
PULSE OUTPUT
ONE-SHOT
OUTPUT
I
TC
TC-1
I
U
TC-1
;'f
I
TC-2
I
1
I
~o~
I
rI
-----~fr___J
L-
fr---,
I
-----1
L--
SQUARE WAVE
OUTPUT
r----
FIRST HALF _ _ _ _ _ _ _ _ _ _ _ _---»~
SQUARE WAVE - OUTPUT
SECOND HALF
-
-
-
---------I.fr---,
L--
Figure 10. Counter/Timer Waveforms
2014-008
289
Functional
Description
(Continued)
290
is specified, the output goes HIgh for one
clock cycle, beginning when the down-counter
leaves the count of I. In the One-Shot mode,
the output goes High when the counter/timer is
triggered and goes Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/timer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a I count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value IS reloaded. On the clocking edge, when
both the down-counter and the output are I's,
the output is pulled back Low.
The Continuou&/Single Cycle (C/SC) bit in
the Mode Specification register controls operation of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count is reached, the countdown sequence
stops. If the C/SC bit is I each time the countdown counter reaches I, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register and initiating the countdown sequence
by loading the down-counter with the time
constant value. The Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter IS loaded in one of
three ways: by writmg a I to the Trigger Command Bit (TCB) of the Command and Status
register, on the rising edge of the external
trigger input, or, for Counter/Timer 2 only, on
the rising edge of Counter/Timer l's internal
output if the counters are linked via the trigger
mput. The TCB is write-only, and read always
returns O.
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are 1
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
Specification register. If REB is 0, ret riggers
are ignored and the countdown continues normally. If REB is 1, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output
is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECE] bit is 0), the down-counter is clocked
internally by a signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is 1), the down-counter is decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to 1,
and if interrupts are enabled (IE = 1), an interrupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to 1
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(CIP) status bit in the Command and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16-bit register, accessible as two
8-bit regIsters, which mirrors the contents of
the down-counter. This register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a 1 to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.
Interrupt Logic Operation. The CIO has five
potential sources of interrupts: the three
counter/timers and Ports A and B. The
priorities of these sources are fIxed in the
following order: Counter/Timer 3, Port A,
Counter/Timer 2, Port B, and Counter/Timer
1. Since the counter/timers all have equal
capabilities and Ports A and B have equal
capabilities, there is no adverse impact from
the relahve pTlorities.
The CIO interrupt priority, relative to other
components within the system, is determined
by an interrupt daisy chain. Two pins, Interrupt Enable In (IEI) and Interrupt Enable Out
(lEO), provide the input and output necessary
to implemenf the daisy chain. When IEI is
pulled Low by a higher pTlority device, the
CIO cannot request an interrupt of the CPU.
The following discussion assumes that the IEI
line is High.
Each source of interrupt in the CIO contains
three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bIt, an Interrupt Under Service (IUS)
Functional
Description
(Continued)
status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is I.
The IUS status bit is set as a result of the
Interrupt' Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
hme the Interrupt Acknowledge commences.
It can also be set directly by the CPU. Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do neit request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off mdividual sources of interrupts.
When IE is set to I, interrupt is generated normally. When IE is set to 0, the IP bit is set
when an event occurs that would normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the CIa to be
disabled without having to individually set
each IE to O. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain
(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to I, the CIG's IEa is forced Low,
independent of the state of the CIa or its lEI
input, and all lower priority devices' interrupts
are disabled.
As part of the lriterrupt Acknowledge cycle,
the CIa is capable of responding with an 8-bit
interrupt vector that specifies the source of the
interrupt. The CIa contains three vector
registers: one for Port A, one for Port B, and
one shared by the three counter/timers. The
vector output is inhibited by setting the No
Vector (NV) control bit to I. The vector output
can be modified to include status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = I, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this way, all the information obtained by the vector, including
status, can be obtained with one additional
instruction when VIS is set to O. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the CIa in a polled environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.
Programming
The data registers within the CIa are
directly accessed by address lines Ao and Al
(Table 3). All other internal registers are
accessed by the following two-step sequence,
with the address lines specifying a control
operation. First, write the address of the target
register to an internal 6-bit Pointer Register;
then read from or write to the target register.
The Data registers can also be accessed by
this method.
An internal state machine determines if
accesses with Ao and Al equalling I are to the
Pointer Register or to an internal control
register (Figure II) . Following any control
read operation, the state machine is in State 0
(the next control access is to the Pointer
Register). This can be used to force the state
machine into a known state. Control reads in
State 0 return the contents of the last register
pointed to. Therefore, a register can be read
continuously without writing to the Pointer.
While the CIa is in State I (next control
access is to the register pointed to), many
internal operations are suspended-no IPs are
set and internal status is frozen. Therefore, to
minimize interrupt latency and to allow continuous status updates, the CIa should not be
left in State I.
The CIa is reset by forCing RD and WR Low
simultaneously (normally an illegal condition)
or by writing a I to the Reset bit. Reset
disables all functions except a read from or
write to the Reset bit; writes to all other bits
are ignored, and all reads return OIH. In this
state, all control bits are forced to 0 and may
be programmed only after clearing the Reset
bit (by writing a 0 to it).
READ
Register
o
o
0
READ OR WRITE
RESET
(REGISTER POINTED TO)
(POINTER =0)
STATE
Port C's Data RegIster
STATE
o
1
Port B's Data R~glster
o
Port A's Data RegIster
Control RegIsters
Table 3. Register Selection
2021·002
)1:)/
(REGISTECGLjRPOINTEDTO)
WAITE (TO POINTER)
NOTE:
State changes occur only when
accesses have effect
Ao =
Al
=
1. No other
Figure II. State Machlno Operation
291
Registers
Master Configuration Control Register
Address: 000001
(Read/Write)
Master Interrupt Control Register
Address: 000000
(ReacllWrite)
MASTER INTERRUPT
ENABLE (MIE)
~:J
E
L=RESET
. pORTe
ENABLE
(PSE)
JJ~
L
NOT useD (READ RETURNS 1)
DISABLE LOWER CHAIN (DLC)
NO VECTOR (NY)
COUNTERITIMEAS VECTOR
INCLUDES STATUS (eT VIS)
COUNTEAfTlMER 2
ENABLE (CT2E)
.
PORT B VECTOR INCLUDES
STATUS (PS VIS)
PORT A VECTOR INCLUDES
STATUS (PA VIS)
[
COUNTERITIMER 1
ENABLE (CT1E)
5 INDEPENDENT
GATES CIT 2
TRIGGERS CIT 2
IS CIT 2's
=
Port Handshake Specification Registers
Addresses: 100000 Port A
101000 Port B
(ReacllWrite)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
PORTTYPE~
SELECTS (PTS)
1
LCO
0
COUNT
1 CIT 1's
0 CIT 1's
1 CIT 1's
Pori Mode Specification Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
PTS1 PTS2
0
1
o
1
1
PORT LINK CONTROL (PLe)
Q=PORTS A AND 8 OPERATE INDEPENDENTlY
1 PORTS A AND B ARE LINKED
Figure 12. Master Control Registors
0
o
PORT A ENABLE (PAE)
(peE AND CT3E)
1
1
Lel
COUNT INPUT
PORT C AND COUNTER!
TIMER 3 ENABLE
o
o
COUNTERITIMER LINK
CONTROLS (LC)
BIT PORT
INPUT PORT
OUTPUT PORT
BIDIRECTIONAL
PORT
INTERRUPT ON TWO
BYTES (ITS)
L
LATCH ON PATTERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (DTE)
(HANDSHAKE MODES)
PATTERN MODE SPECIFICATION
BITS (PMS)
o
1
1
0
1
1
PMS1 PMSO
o
1
o
1
SINGLE BUFFERED
MODE (S8)
HANDSHAKE TYPE SPECIFICATION
BITS (HST)
HST1 HSTO
DISABLE PATIERN MATCH
"AND"MODE
"OR" MODE
"OR·PRIORITY ENCODED
VECTOR" MODE
' - - - - INTERRUPT ON MATCH ONLY (IMO)
J
-----c
---0- -0-'NTERLOCKED HANDSHAKE
DESKEW TIME SPECIFICATION
BITS SPECIFIES THE MSB's OF
DESKEW TIMER TIME CONSTAt-iT
LS8 IS FORCED 1.
STROBED HANDSHAKE
PULSED HANDSHAKE
THREE·WIRE HANDSHAKE
REQUESTIWAIT SPECIFICATION BITS
(RWS)
RWS2 RWS1 RWSO FUNCTION
-o~
~- REQUESTIWAIT DISABLED
o
OUTPUT WAIT
INPUT WAIT
1
SPECIAL REQUEST
1
OUTPUT REQUEST
1
INPUT REQUEST
o
Port Command and Status Registers
Addresses: 100001 Port A
101001 Port B
(ReacllWrite)
INTERRUPT UNDER
SERVICE (IUS)
~J
INTER~UPT ENABLE (IE)
INTERRUPT PENDING (IP)
JUS, IE AND IP ARE
WRITTEN USING THE
FOLLOWING COMMAND'
~
I L
L
INTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (IRF)
(READ ONLy)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLy)
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEAR IP
SET IE
CLEAR IE
INTERRUPT ERROR (ERR) _ _ _----J
(READ ONLy)
Figure 13. Port Specification Rogisters
292
2014-009, 010
Registers
(Continued)
Data Path Polarity Registers
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(ReadlWrite)
Data Direction Registers
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(ReadlWrite)
' - - - - DATA DIRECTION (DO)
O=QUTPUT BIT
1 =\NPUT BIT
' - - - - DATA PATH POLARITY (DPP)
0= NON·INVERTING
1 = INVERTING
Special 110 Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(ReadlWrite)
' - - - - SPECIAL INPUT/OUTPUT (SIC)
0= NORMAL INPUT OR OUTPUT
1 =OUTPUT WITH OPEN DRAIN OR
INPUT WITH 1's CATCHER
Figure 14. Bit Path Definition Registers
Port Data Registers
Addresses: 001101 Port A *
001110 Port B*
(ReadlWrite)
Port C Data Register
Address: 001111(Read/Write)
4 MSBs
o
~WRITING OF CORRESPONDING LSB ENABLED
1 =WR1TING OF CORRESPONDING LSB INHIB1TED
(READ RETURNS 1)
• These regIsters can be
addressed dIrectly.
Figure 15. Port Data Registers
Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(ReadlWrite)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Port B
(ReadlWrite)
~
f!!'f
PATTERN SPECIFICATION
BIT MASKED OFF
ANY TRANSITION
ZERO
ONE
ONE·TO ZERO TRANSITION (\)
ZERO-TQ·ONE TRANSITION (t)
Pattern Mask Registers (PM)
Addresses: 100111 Port A
101111 Port B
(Read/Write)
Figure 16. Pattern Definition Registers
2014-011,012,013
293
Registers
(Continued)
Counter/Timer Command and Status Registers
Addresses: 011100 Counter/Timer 1
011101 Counter/TImer 2
011110 Counter/TImer 3
(ReadlWrite)
INTERRUPT UNDER SERVICE (IUS)
(READiWRffE)
jJ
I
I
INTERRUPT ENAB.!.U!E)
(READfWRITE)
,
I
INTERRUPT PENDIw:Lt!.f)
I
I
I
E~
COUNT IN PROGRESS ICIP)
(READ ONLy)
TRIGGER COMMAND BIT (TLB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (GCB)
(REAOIWRITE)
(READIWAITE)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE
READ COUNTER CONTROL (RCe)
NULL CODE
0
0
CLEAR IP & IUS
0
0
1
seT IUS
0
1
0
CLEAR IUS
0
1
1
SET IP
1
0
0
CLEAR IP
1
0
1
(READ/SET ONlYCLEARED BY READING eeR LSB)
0
SET IE
1
1
0
CLEAR IE
1
1
1
INTERRUPT ERROR (ERR)
(READ ONLY)
Counter/Timer Mode Specification Registers
Addresses: 001010 Counter/TImer 1
001011 Counter/Timer 2
001100 Counter/TImer 3
(Read/Partial WrIte)
CONT1NUOUS S.ill
GlE CYCLE (e/SC)
JJgJJ
~XTERNAl OUTPUT
[L
OUTPUT DUTY CYCLE
SELECTS (DeS)
D~C1 D~SO PULSE OUTPUT
ENABLE (EOE)
0
1
ONE SHOT OUTPUT
EXTERNAL COUNT
ENABLE (EeE)
1
1
0
1
SQUARE·WAVE OUTPUT
DO NOT SPECIFY
EXTERNAL TRIGGER
ENABLE (ETE)
RETRIGGER ENABLE BIT (REB)
EXTERNAL GATE ENABLE (EGE)
Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer l's MSB
010001 Counter/Timer l's LSB
010010 Counter/Timer 2's MSB
010011 Counter/Timer 2's LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)
MOST - - - - - '
SIGNIFICANT
BYTE
' - - - - - LEAST
SIGNIFICANT
BYTE
Counter/Timer Time Constant Registers
Addresses: 010110 Counter/Timer l's MSB
010111 Counter/TImer l's LSB
011000 Counter/Timer 2's MSB
011001 Counter/TImer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/Timer 3's LSB
(Read/Write)
MOST--------J
SIGNIFICANT
' - - - - - LEAST
SIGNIFICANT
BYTE
BYTE
Figure 17. Counter/Timer Registers
294
2014-014
Registers
Current Vector Register
Address: 011111
(Read only)
Interrupt Vector Register
Addresses: 000010 Port A
0000 11 Port B
000100 Counter/Timers
(Read/Write)
(Continued)
' - - - - - INTERRUPT VECTOR BASED
ON HIGHEST PRIORITY
UNMASKED IP
IN NO INTERRUPT PENDING
ALL ,'s OUTPUT.
' - - - - - INTERRUPT VECTOR
PORT VECTOR STATUS
PRIORITY ENCODED VECTOR MODE:
~
~
x
~
x
NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH
ALL OTHER MODES
03
02
01
ORe IRF PMF
o
0
0
NORMAL
ERROR
COUNTERfTlMER STATUS
02
oo
01
0"
,
, ,
,
0
CIT 3
CIT 2
CIT ,
ERROR
Q
o
Figure 18. Interrupt Vector Registers
Register
Address
Summary
Main Control Registers
Address
(AD 7- AD o)
OOOOOOXX
OOOOOIXX
OOOOIOXX
OOOOIIXX
ooOIOOXX
oOolOlXX
ooollOXX
000 III XX
Register Name
Master Interrupt Control
Master ConfIgurahon Control
Port A's Interrupt Vector
Port B's Interrupt Vector
Counter/TImer's Interrupt Vector
Port C's Data Path PolaIlty
Port C's Data DlIection
Port C's SpecIal I/O Control
Counter/Timer Related Registers (Contmued)
Address
(AD 7-ADO) Register Narne
OlIOOOXX
Counter/TImer 2's TIme Constant·MSBs
01 1001 XX
Counter/TImer 2's TIme Constant-LSBs
OIIOIOXX
Counter/TImer 3's TIme Constant-MSBs
ollOllXX
Counter/TImer 3's TIme Constant-LSBs
olllooXX
Counter/TImer I's Mode SpecIfICatIon
OlllolXX
Counter/TImer 2's Mode SpecIfIcatIon
olllloXX
Counter/TImer 3's Mode SpecIfICahon
olllllXX
Current Vector
Most Often Accessed Registers
Address
(AD 7-ADO)
oolOooXX
oOloolXX
00 10 IOXX
oOIOllXX
oollOoXX
ooilO1XX
OOlllOXX
OOIIIIXX
RegIster Name
Port A's Command and Status
Port B's Command and Status
Counter/TImer 1's Control
Counter/Timer 2' s Control
Counter/TImer 3's Control
Port A's Data (can be accessed dlIectly)
Port B's Data (can be accessed directly)
Port Cs Data (can be accessed dlIectly)
Port A Specification Registers
Address
(AD 7-ADO)
100000XX
100001XX
1000lOXX
1000llXX
100100XX
100101XX
1001lOXX
10011lXX
Counter/Timer Related Registers
Address
(AD 7- ADO)
OIOOoOXX
010001 XX
01 00 IOXX
OloollXX
olOlOOXX
OlolOlXX
OIOIIOXX
OlOlllXX
2014-015
Register Name
Counter/TImer
Counter/TImer
Counter/Timer
Counter/TImer
Counter/TImer
Counter/TImer
Counter/TImer
Counter/TImer
l's Current Count-MSBs
l's Current Count-LSBs
2's Current Count-MSBs
2's Current Count-LSBs
3's Current Count-MSBs
3's Current Count-LSBs
l's TIme Constant-MSBs
I's TIme Constant-LSBs
Register Name
Port A's Mode SpecIficatIon
Port A's Handshake SpecifIcatIon
Port A's Data Path PolaIlty
Port A's Data DIrectIon
Port A's Special I/O Control
Port A's Pattern PolaIlty
Port A's Pattern Translhon
Port A's Pattern Mask
Port B Specification Registers
Address
(AD 7- ADO)
101000XX
1OlO01XX
10 10 IOXX
1010llXX
1OIlO0XX
101l0lXX
IOllloXX
1011 II XX
RegIster Name
Port B's Mode SpeCIfICatIon
Port B's Handshake Speclhcahon
Port B's Data Path PolaIlty
Port B's Data Dlrecilon
Port B's SpecIal I/O Control
Port B's Pattern PolaIlty
Port B's Pattern Translilon
Port B's Pattern Mask
295
Timing
Read Cycle. At the beginning of a read cycle,
the CPU places an address on the address bus.
Bits Ao and Al specify a CIa register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIa. When
Read (RD) goes Low, data from the specified
register is gated onto the data bus.
AO-Ai
CE
liD
Do-D7
==x
Write Cycle. At the beginning of a write
cycle, the CPU places an address on the data
bus. Bits Ao and Al specify a CIa register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIa. When
WR goes Low, data placed on the bus by the
CPU is strobed into the specified CIa register.
x:=
ADDRESS VALID
~
/
(
READ DATA
==x
(
>--
WRITE DATA
Figure 20. Write Cycle Timing
Interrupt Acknowl~e. The CIa pulls its
Interrupt Request (!NT) line Low, requesting
interrupt service from the CPU, if an Interrupt
Pending (IP) bit is set and interrupts are
enabled. The CPU responds with an Interrupt
Acknowledge cycle. When Interrupt Acknowledge (INTACK) goes true and the IP is set, the
CIa forces Interrupt Enable aut (lEa) Low,
disabling all lower priority devices in the interrupt daisy chain. If the CIa is the highest
priority device requesting service (lEI is
High). it places its interrupt vector on the data
bus and sets the Interrupt Under Service (IUS)
bit when Read (RD) goes Low.
INT ____________
lEO
I
\
Do-D7
Figure 19. Read Cycle Timing
lEI
/
WR
)--
x=
ADDRESS VALID
~
CE
I
\
Ao-Ai
)~)~------JI
I/
~f-'- - - - - f~
00- 0 7
-----------'"")f)J''---------«C~VE~C~TO~R=}Figure 21. Interrupt Acknowledge Timing
296
2021-003,004,005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operatmg Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
followmg standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the refer·
enced pm. Standard conditions are as follows:
Stresses greater than those lIsted under Absolute MaxImum RatIngs may cause permanent damage to the deVIce.
ThIs IS a stress ratmg only; operahon of the devIce at any
condItIon above those mdicated In the operational sections
of these specIfIcatIons IS not ImplIed. Exposure to absolute
maXImum ratIng condItIons for extended penods may affect
devIce relIabIlIty.
•
+4.75 V::; Vee::; +5.25 V
• GND = 0 V
• TA as specifted in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+5V
dr
+5V
22K
2.2K
FROM OUTPUT
UNDER TEST
50 PF
Figure 22. Standard Test Load
DC
Characteristics
Symbol
VIH
V1L
VOH
VOL
Parameter
Figure 23. Open-Drain Test Load
Min
Max
Unit
Input High Voltage
2.0
V
Input Low Voltage
-0.3
Vee +0.3
0.8
Output High Voltage
Output Low Voltage
2.4
0.4
0.5
V
V
Condition
V
V
p,A
IoH=
h=
IOL =
0.4 :S
0.4
IlL
IOL
Input Leakage
± 10.0
Output Leakage
± 10.0
p.A
Icc
Vee Supply Current
250
mA
:S
~
- 250 p.A
+2.0 mA
+3.2 mA
VIN :S +2.4 V
Your
:S
+2.4 V
Vee = 5 V ± 5% unless otherwlse speclfied, over specliled temperature range.
Capacitance
Symbol
C IN
C our
CliO
f
8085-0209. 000 1
=
Parameter
Input CapacItance
Output CapacItance
BidIrechonal Capacitance
Min
Max
Unit
10
pF
pF
pF
15
20
Test Condition
Unmeasured Pins
Returned to Ground
1 MHz, over specliled temperature range.
297
CPU
Interface
Timing
Interrupt
Timing
Number Symbol
31
TdPM(INT)
Pattern Match to INT Delay (Elt Port)
32
TdACK(INT)
ACKIN to INT Delay (Port with Handshake)
34
TdPC(INT)
250
105
105
100
0
200
0
200
0
80
0
80
0
0
100
0
0
100
0
390
0
0
390
0
0
1000'
actIons.
2. Float delay IS measured to the hme when the output has
changed 0.5 V With mlnlmum ae load and maXImum de load
3 Tre IS l,uS or 3 Tc~whlchever IS longer
4. The delay IS from DAV I for 3- Wlre Input Handshake
The deldY lS from DAC i for 3-Wlre Output Handshake.
Units
4000
ns
2000
ns
2000
ns
20
ns
20--ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
255
ns
ns
70
ns
ns
ns
ns
ns
TcPC
+ns
10
TcPC
+ns
2 - - TcPC
+ns
TcPC
3
+ns
PCLK to INT Delay (Timer Mode)
TsIA(RDA)
INTACK to RD ! (Acknowledge) Setup Tlme
35
RD (Acknowledge Width)
36
TwRDA
TdRDA(DR)
RD ! (Acknowledge) to Read Data Valid Delay
37
TdIA(IEO)
INTACK ! to IEO ! Delay
38
39-TdIEI(IEO)- IEI to IEO Delay
IEI to RD ! (Acknowledge) Setup Time
TsIEI(RDA)
40
ThIEI(RDA)
IEI to RD t (Acknowledge) Hold Time
41
42
TdRDA(INT) RD ! (Acknowledge) to INT t Delay
Max
Notes"
2
3
2
Counter Input to INT Delay (Counter Mode)
NOTES:
1. Parameter does not apply to Interrupt Acknowledge trans-
298
Min
I
TcPC
PCLK Cycle Time
TwPCh
PCLK Wldth (Hlgh)
2
PCLK Width (Low)
TwPCl
3
TrPC
PCLK Rlse Tlme
4
5-TfPC
PCLK Fall Time
TsIA(PC)
INTACK to PCLK 1 Setup T,me
6
ThIA(PC)
INTACK To PCLK 1 Hold Tlme
7
TsIA(RD)
INTACK to RD I Setup Tlme
8
ThIA(RD)
9
INTACK to RD 1 Hold Time
IO-TsIA(WR)-- INTACK to WR ! Setup Time
ThIA(WR)
11
INTACK to WR 1 Hold T,me
TsA(RD)
Address to RD ! Setup Time
12
ThA(RD)
13
Address to RD 1 Hold Time
TsA(WR)
Address to WR I Setup Time
14
15-ThA(WR) --Address to WR 1 Hold Time
TsCEl(RD)
CE Low to RD ! Setup T,me
16
17
TsCEh(RD)
CE High to RD ! Setup T,me
18
ThCE(RD)
CE to RD 1 Hold Time
TsCEl(WR)
CE Low to WR ! Setup T,me
19
20-TsCEh(WR)- CE Hlgh to WR ! Setup Time
ThCE(WR)
CE to WR t Hold T,me
21
22
TwRDI
RD Low Width
TdRD(DRA)
23
RD I to Read Data Active Delay
TdRDf(DR)
RD ! to Read Data Valid Delay
24
25-TdRDr(DR)- RD Ito Read Data Not Vahd Delay
TdRD(DRz)
RD t to Read Data Float Delay
26
27
TwWRl
WR Low Width
TsDW(WR)
28
Write Data to WR ! Setup Time
ThDW(WR)
29
Wnte Data to WR t Hold Tlme
30
Trc
Vahd Access Recovery Time
33- TdCI(INT) -
Interrupt
Acknowledge
Timing
Parameter
350
350
100
100
4
ns
5
ns
ns
255
ns
5
350
150--- n s - - - 5 ns
5
ns
ns
600
5 The parameters for the devices In any parhcular daisy cham
~st meet the followmg constramt' The delay from INTACK I to
RD I must be greater than the sum of TdIA{IEO) for the hIghest
pnorIty penpheral, TsIEI(RDA) for the lowest prIOrIty
penpheraL and TdIEI{IEO) for each penpheral separatmg them
m the cham
*Tlmlngs are prehmlnary and subject to change.
CPU
Interface
Timing
PCLK
Ao-A1
D~E~6
C"l
-------+--+-<
S
Do-D7
DATA VALID
WRITE _ _ _ _ _ _- '
Interrupt
Timing
PATTERN MATCH
INPUT(S)
BIT PORT
~
______
PATTERN MATCHES
~ r~'-~~~~~~~~®-'::::====:--I-------------
ACKIN
NOTE 4
32
COUNTER
INPUT _ _ _ _ _J
33
PCLK
Interrupt
Acknowledge
Timing
RD
DO-07
lEI
lED
INT
2021-006,007,008
~r------
299
Handshake
Timing
Number Symbol
2
TsDl(ACK)
ThDI(ACK)
TdACK£(RFD)
3
4
TwACKI
5-TwACKh
Parameter
Min
Data Input to ACKIN I Setup Time
Data Input to ACKIN I Hold TlmeStrobed Handshake
ACKIN I to RFD I Delay
ACKIN Low Width-Strobed Handshake
ACKIN High Width-Strobed Handshake
0
ns
ns
0
ns
ns
ns
ns
TdRFDr(ACK)
RFD I to ACKIN I Delay
0
TsDO(DAV)
Data Out to DAV I Setup Time
25
TdDAV£(ACK)
DA V I to ACKIN I Delay
8
0
ThDO(ACK)
9
Data Out to ACKIN I Hold Time
2
10-TdACK(DAV)--ACKIN I to DAV I Delay
2
ThDl(RFD)
Data Input to RFD I Hold TlmeII
0
Interlocked Handshake
TdRFDf(ACK)
12
RFD I to ACKIN I Delay0
Interlocked Handshake
TdACKr(RFD)
ACKIN I (DA V I) to RFD I Delay13
0
Interlocked and 3-Wire
Handshake
14
TdDAVr(ACK)
DAV I to ACKIN I (RFD I)-Interlocked
0
and 3-Wlre Handshake
15-TdACK(DAV)--ACKIN I (RFD I) to DAV I Delay----O
Interlocked and 3-Wlre
Handshake
16
TdDAVI£(DAC)
DAV I to DAC I Delay-Input
3-Wire Handshake
0
ThDl(DAC)
Data Input to DAC I Hold Time17
0
3-Wire Handshake
TdDACOr(DAV)
18
DAC I to DAV I Delay-Input
3-Wire Handshake
0
19
TdDAVIr(DAC)
DAV I to DAC I Delay-Input
0
3-Wlre Handshake
20- TdDAVO£(DAC)- DAV I to DAC I Delay-Output
0
3-Wlre Handshake
21
ThDO(DAC)
Data Output to DAC I Hold Time2
3-Wire Handshake
TdDACIr(DAV)
22
DAC I to DA V I Delay-Output
2
3-Wire Handshake
TdDAVOr(DAC)
23
DA V I to DAC I Delay-Output
0
3-Wire Handshake
Max
Units
6
7
ns
ns
TcPC
TcPC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TcPC
TcPC
ns
NOTES:
1. This hme can be extended through the use of the deskew hmers
300
*Tlmmgs are prehmlOary and subject to change
Notes·
Strobed
Handshake
DATA
INPUT
RFD
~~ATAVALID k'----;-_---;~--;---
-J~~r,~
---.:.~ OJJ-'-=--==
-j
OUTPUT
Interlocked
Handshake
DATA
~
-Jcl_~
INPUT
RFD
D
DATAVAUD
i<~
_______
_______1~~~3
__~~--'-}~-------
DATA
OUTPUT
3-Wire
Handshake
ACKIH
DATA
DAY
INPUT
INPUT
RFD
OUTPUT
DAC
OUTPUT
DATA
DAC
INPUT
-----1-------'1"
OUTPUT
RFD
INPUT
DAY
OUTPUT
2014-022, 023, 024
301
Counter/
Timer
Timing
Number Symbol
Parameter
Min
Max
Units
Notes·
ns
TeCI
Counter Input Cycle Time
500
2
TClh
Counter Input High Width
230
ns
3
TwCIl
Counter Input Low Width
230
ns
20
ns
Counter Input Fall Time
4
TICI
5--TrCI----Counter Input Rise T i m e - - - - - - - - - - - - - - 2 0 - - - n s - - - - - 6
TsTI(PC)
Trigger Input to PCLK I Setup Time
(Timer Mode)
ns
7
TsTI(CI)
Trigger Input to Counter Input I Setup Time
(Counter Mode)
ns
8-TwTI----Trigger Input Pulse WIdth (High or L o w ) - - - - - - - - - - - n s - - - - 9
TsGI(PC)
10
TsGI(CI)
12
ThGI(CI)
13
14
Gate Input to PCLK I Setup Time
(Timer Mode)
ns
ns
Gate Input to Counter Input I Setup Time
(Counter Mode)
II--ThGI(PC)--Gate Input to PCLK I Hold Time (Timer Mode) _ _ _ _ _ _ _ _ ns _ _ _ I _
Gate Input to Counter Input I Hold TIme
(Counter Mode)
ns
TdPC(CO)
PCLK to Counter Output Delay (Timer Mode)
ns
TdCI(CO)
Counter Input to Counter Output Delay
(Counter Mode)
ns
NOTES1. These parameters must be met to guarantee tngger or gate are
"Tlmmgs are prehmmary and subject to change.
valId for the next counter/hmer cycle.
PCLK
PCLKI2
(INTERNAL)
COUNTER
INPUT
TRIGGER
INPUT
GATE
INPUT
COUNTER
OUTPUT
302
2021-009
REQUEST/
WAIT
Number Symbol
Timing
2
Parameter
Min
Max
Units
TdRD(REQ)
RD I to REQ I Delay
ns
TdRD(WAIT)
RD I to WAIT I Delay
ns
TdWR(REQ)
WR I to REQ I Delay
3
TdWR(WAlT)
4
WR I to WAIT I Delay
5-TdPC(REQ)---PCLK I to REQ I Delay
Notes·
ns
ns
ns
6
TdPC(WAIT)
PCLK I to WAIT I Delay
7
TdACK(REQ)
ACKIN I to REQ I Delay
8
TdACK(WAIT)
ACKIN I to WAIT I Delay
ns
TcPC
+ns
TcPC
+ns
NOTES:
1. The delay
The delay
IS
IS
from DAV I for 3-Wlre Input Handshake.
from DAC t for 3-Wlre Output Handshake.
*Tlmmgs are prehmmary and subject to change.
PCLK
REQ
Reset
Timing
Number Symbol
Parameter
1
TdRD(WR)
Delay from RD I to WR I for No Reset
2
TdWR(RD)
Delay from WR I to RD I for No Reset
3
TwRES
Minimum W ldth of RD and WR both Low
for Reset
Min
Max
50
50
250
Units
Notes·
ns
ns
ns
*Tlmmgs are preliminary and subject to change
RESET
INTERNAL
2021-010,011
____________________
~r
303
Min
Miscellaneous Number Symbol
Parameter
Port
Any Input RIse Time
I
TrI
Timing
Any Input Fall TIme
TfI
2
l's Catcher High Width
Twl's
3
4--TwPM--- Pattern Match Input Valid (Bit Port)
5
TsPMD
Data Latched on' Pattern Match Setup Time
(Bit Port)
6
ThPMD
Data Latched on Pattern Match Hold Time
(Bit Port)
NOTES:
I. If the input IS programmed Invertmg, a Low·gomg pulse of the
same wIdth wIll be detected.
ANY INPUT
1'5 CATCHER
INPUT
-----'\~~t
Units
Max
100
ns
100
ns
250
ns
750
ns
0
ns
1000
ns
Notes"
*rlmmgs are prelim mary and subject to chanqe.
-~1'---:--
-----'~'-----
DA::~:: ------x='f~:HES~------
LATCHED TO
PATTERN MATCH _ _ _ _ __
Ordering
Information
Product
Number
Z8536
Z8536
Z8536
Z8536
Z8536
Z8536
Package/
Temp
Speed
Description
Product
Number
Description
CE
4.0 MHz
CIa (40-pm)
Z8536A
CE
6,0 MHz
CIa (40-pin)
CS
4.0 MHz
Same as above
Z8536A
CS
6.0 MHz
Same as above
DE
4.0 MHz
Same as above
Z8536A
DE
6.0 MHz
Same as above
DS
4.0 MHz
Same as above
Z8536A
DS
6.0 MHz
Same as above
PE
4.0 MHz
Same as above
Z8536A
PE
6.0 MHz
Same as above
PS
4.0 MHz
Same as above
Z8536A
PS
6.0 MHz
Same as above
NOTES C = Ceramic, D :::: Cerdlp, P = PlastIc, E ::::: _40°C to +85°C, S
304
Package/
Temp
Speed
= aoc to
+70°C.
2014·028
00·2021-A
Z8590
upe Universal
Peripheral Controller
~
Zilog
Product
Specilication
March 1981
Features
• Complete slave microcomputer, for
distributed processing use.
• Unmatched power of 28 architecture and
instruction set.
• Three programmable I/O ports, two with
optional 2-Wire Handshake.
• Six levels of priority interrupts from eight
sources: six from external sources and two
from internal sources.
• Two programmable 8-bit counter/timers
General
Description
The 28590 Universal Peripheral Controller
(UPC) is an intelligent peripheral controller
for distributed processing applications (Figure
3). The UPC unburdens the host processor by
assuming tasks traditionally done by the host
(or by added hardware), such as performing
arithmetic, translating or formatting data, and
controlling I/O devices. Based on the 28
DATA]
BUS
P13~
Ph ....--..
_____ DB1
Pl,
. . - . OBI)
P10 .....--.
AND RESET
---+-
~
z~;~o
P3,
cs
PORT 1
iNT OR
INTERR~:~
P3s
---+- lEI OR P30
P2'_]
P2s..-....
P26 ...--..
6
P2,
Rij
7
P2,
P2,
P20
P3,
P3,
Pl,
+5V ---+PCLK--.
P20
PORT 2
GNO---+-
Figure 1. Z8590 UPC Pin Functions
2017-068,095
P2,
INTACK OR P32
P24~
P2,
P2,
P2,
lEO OR P3T
P2,
P2,
PORT 3
P3,
---+- INTACK OR P32
3
lEI OR P30
WAIT
MASTER {
lEO OR P31
iNT OR P3s
P3'_}
P3,
P3l .......-
- - - - WR
CONTROL ( --.-...
microcomputer architecture and instruction
set, the UPC contains 2K bytes of internal program ROM, a 256-byte register file, three 8-bit
I/O ports, and two counter/timers.
The UPC offers fast execution time, an
effective use of memory, and sophisticated
interrupt, I/O, and bit manipulation. Using
a powerful and extensive instruction set
P15~
_____ DB3
NO
• 2K bytes of on-chip ROM for efficiency and
versatility.
P1a ...-....
Pl,
~DB2
( --.
• 256-byte register file, accessible by both the
master CPU and UPC, as allocated in the
UPC program.
Ph_j
~~~
TIM~~~
each with a 6-bit prescaler. Counter/Timer
TO is driven by an internal source, and
Counter/Timer Tl can be driven by internal
or external sources. Both counter/timers are
independent of program execution.
Pl,
Pl,
Pl,
Pl,
P10
Figure 2. Z8590 UPC Pin Assignments
305
General
Description
(Continued)
combined with an efficient internal
addressing scheme, the UPC speeds
program execution and efficiently packs
program code into the on-chip ROM.
An important feature of the UPC is an internal register file containing I/O port and control registers accessed both by the UPC program and indirectly by its associated master
CPU. This architecture results in both byte
and programming efficiency, because UPC
instructions can operate directly on I/O data
without moving it to and from an accumulator.
Such a structure allows the user to allocate as
many general purpose registers as the application requires for data buffers between the CPU
and peripheral devices. All general-purpose
registers can be used as address pOinters,
index registers, data buffers, or stack space.
The register file is logically divided into 16
groups, each consisting of 16 working
registers. A Register Pointer is used in conjunction with short format instructions,
resulting in tight, fast code and easy task
switching.
Communication between the master CPU
and the register file takes place via one group
of 19 interface registers addressed directly by
both the master CPU and the UPC, or via a
block transfer mechanism. Access by the
master CPU is controlled by the UPC to allow
independence between the master CPU and
UPC software.
The UPC has 24 pins that can be dedicated
to I/O functions. Grouped logically into three
HOST CPU
INTERFACE
8-line ports, they can be programmed in many
combinations of mput or output lines, with or
without handshake, and with push-pull or
open-drain outputs. Ports 1 and 2 are bitprogrammable; Port 3 has four fixed inputs
and four outputs.
To relieve software from coping with realtime counting and hming problems, the UPC
has two 8-bit hardware counter/timers, each
with a fixed divide-by-four, and a 6-bit programmable prescaler. Various counting modes
may be selected.
In addition to the 40-pin standard configuration, the UPC IS avaIlable in four special configurations:
• A 64-pin RAM development version with
external interface for up to 4K bytes of RAM
and 36 bytes of internal ROM permitting
down-loading from the master CPU.
• A Protopack RAM version with a socket for
up to 2K bytes of RAM, with 36 bytes of
internal ROM permitting down-loading from
the master CPU.
• A 64-pin ROM development version with
external interface for up to 4K bytes of ROM
and no internal ROM.
• A Protopack ROM version with a socket for
2K bytes of ROM and no internal ROM.
This range of versions and configurations
makes the UPC compatible with most system
peripheral device control considerations.
UPC MICROCOMPUTER
PORT
1
INTERFACE
DBo-OSr
110
REGISTERS
(PART OF REGISTER
FilE)
RP
TO
MASTER
CPU
PORT
2
110
IRP
REGISTER
FilE
256)(8
INT
lEO
(1/0 FUNCTION
IS OPTIONAL)
+5VGND PCLK
Figure 3. Functional Block Diagram
306
2017·087
Pin
Description
AID. Address/Data (input). A Low on this pin
defines information on the data bus as an
address. A High defines the information
as data.
CS. Chip Select (input, active Low). A Low
enables the UPC to accept address or data
information from the master CPU during a
write cycle or to transmit data to the master
CPU during a read cycle. This line is usually
generated from higher bits of the address
lines.
DBo-DB-,. Data Bus (bidirectional). This bus is
used to transfer address and data information
between the master CPU and the UPC.
PIO-PI7. P2Q-P27. P30-P:J.,. I/O Port Lines
(bidirectional. TTL compatible). These 24 lines
are divided into three 8-bit I/O ports and may
be configured in the following ways under program control:
PIo-PI7' Port 1 (inpuVoutput-as output it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P2Q-P27. Port 2 (inpuVoutput-as output, it can
Functional
Description
Address Space. On the 40-pin UPC, all
address space is committed to on-chip
memory. There are 2048 bytes of maskprogrammed ROM and 256 bytes of register
file. I/O is memory-mapped to three registers
in the register file. Only the Protopack and
64-pin versions of the UPC can access external
program memory. See the section entitled
"Special Configurations" for complete descriptions of the Protopack and 64-pin versions.
Program Memory. Figure 4 is a map of the 2K
on-chip program ROM. Even though the architecture allows addresses from 0 to 4K, behavior of the device above program address 2047
(7FFH) is not defined. The first 12 bytes of program memory are reserved for the UPC
interrupt vectors. For the Protopack and 64-pin
versions, the address space is extended to 4096
bytes. In the RAM versions, addresses OCH
20 47
LOCATION OF
FIRST BYTE OF
INSTRUCTION
USER
ROM
EXECUTED AFTER ' " ,
RESET
12
11
P30-P:J.,. Port 3 (four inputs, four outputs).
Parallel I/O, handshake control, timer I/O, or
interrupt control.
PCLK. Clock (input). TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.
RD. Read (input, active Low). A Low enables
the master CPU to read information from the
UPC. Raising the voltage on this pin above
Voo will force the UPC into test mode.
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the UPC register file,
this signal requests the master CPU to wait
until the UPC can complete its part of the
transaction.
WR. Write (input, active Low). A Low on this
pin enables the master CPU to write information to the UPC. A simultaneous Low on RD
and WR resets the UPC. It is held in reset as
long as WR is Low.
through 2FH are reserved for on-chip ROM.
Register File. This 256-byte file includes three
I/O port registers (l-3H), 234 general-purpose
registers (6-EEH), and 19 control, status and
special I/O registers (OH, 4H, 5H, and
FO-FFH). The functions and mnemonics
assigned to these register address locations
are shown in Figure 5. Of the 256 UPC
registers, 19 can be directly accessed by the
master CPU; the others are accessed indirectly
via the block transfer mechanism.
IDENTIFIER
(UPC Side)
LOCATION
FFH
STACK POINTER
SP
MIC
FEH
MASTER CPU INTERRUPT CONTROL
FDH
REGISTER POINTER
RP
FCH
PROGRAM CONTROL FLAGS
FLAGS
FBH
UPC INTERRUPT MASK REGISTER
IMR
FAH
UPC INTERRUPT REQUEST REGISTER
IRQ
F9H
UPC INTERRUPT PRIORITY REGISTER
IPR
F8H
PORT 1 MODE
P1M
F7H
F6H
PORT 3 MODE
PJM
PORT 2 MODE
P2M
FSH
F4H
To PRESCALER
PREO
TIMER/COUNTER 0
T,
FaH
T1 PRESCALER
PRE1
TIMER/COUNTER 1
T,
F1H
TIMER MODE
TMR
IROS LOWER BYTE
FOH
MASTER CPU INTERRUPT VECTOR REG
MIV
10
lAOS UPPER BYTE
EFH
9
IRQ4 LOWER BYTE
8
IRQ4 UPPER BYTE
F2H
"
7
IRC3 LOWER BYTE
6
IR03 UPPER BYTE
5
IRQ2 UPPER BYTE
IRal LOWER BYTE
2
IRQ1 UPPER BYTE
0
GENERAL-PURPOSE REGISTERS
IR02 LOWER BYTE
4
3
1
6H
SH
DATA INDIRECTION REGISTER
~
LIMIT COUNT REGISTER
IROO LOWER BYTE
3H
PORT 3
P3
IROO UPPER BYTE
2H
PORT 2
P2
Figure 4. Program Memory Map
2017·001.002
be push-pull or open-drain). Bit-programmable
Parallel I/O.
DIND
~
1H
PORT 1
P1
OH
DATA TRANSFER CONTROL REGISTER
DTC
Figure 5. Register File Organization
307
Functional
Description
(Continued)
The 1/0 port and control registers are
included in the register file without differentiation. This allows any UPC instruction to
process 1/0 or control information, thereby
eliminating the need for special I/O and control instructions. All general-purpose registers
can function as accumulators, address
pOinters, or index registers. In instruction execution, the registers are read when they are
defined as sources and written when defined as
destinahons.
UPC instructions may access registers
directly or indirectly using an 8-bit address
mode or a 4-bit address mode and a Register
Pointer. For the 4-bit addressing mode, the file
is divided into 16 working register groups,
each occupying 16 contiguous locations
(Figure 6). The Register Pointer (RP) addresses
the starting point of the active working-register
group, and the 4-bit register designator supplied by the instruction specifies the register
within the group. Any instruction altering the
contents of the register file can also alter the
Register Pointer. The UPC instruction set has a
special Set Register Pointer (SRP) instruction
for initializing or altering the pointer contents.
Stacks. An 8-bit Stack Pointer (SP), register
R255, is used for addressing the stack,
residing within the 234 general-purpose
registers, address location 6H through EFH.
PUSH and POP instructions can save and
restore any register in the register file on the
stack. During CALL instructions, the Program
Counter is automatically saved on the stack.
During UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the stack. The RET and IRET
instructions pop the saved values of the Program Counter and Flag register.
o 1 1 1
o
THE 4-BIT REGISTER}
POINTER PROVIDES THE
UPPER NIBBLE OF THE
REGISTER FILE ADDRESS
FOR THE 4-BIT ADDRESS
MODE.
75H 01110101
0 0 0
FFH
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BaH
AFH
AOH
9FH
90H
BFH
BaH
7FH
70H
6FH
60H
5FH
50H
4FH
40H
3FH
30H
2FH
20H
1FH
10H
OFH
0
Figure 6. Register Pointer Mechanism
308
Ports. The UPC has 24 lines dedicated to
input and output. These are grouped into three
ports of eight lines each and can be configured under software control as inputs, outputs, or speCial control signals. They can be
programmed to provide Parallel I/O with or
without handshake and timing signals. All outputs can have active pull ups and pulldowns,
compatible with TTL loads. In addition, they
may be configured as open-drain outputs.
Port 1. Individual bits of Port 1 can be configured as input or output by programming
Port I Mode register (PIM) F8H. This port is
accessed by the UPC program as general
register IH. It is written by specifying address
1H as the destination of any instruction used to
store data in the output register. The port is
read by speCifying address 1H as the source of
an instruction.
Port 1 may be placed under handshake control by programming Port 3 Mode register
(P3M) F7H. This configures Port 3 pins P33
and P34 as handshake control lines DA V! and
RDY! for input handshake, or RDY! and DAV!
for output handshake, as determined by the
direction (input or output) assigned to bit 7 of
Port 1. The Port 3 Mode register also has a bit
that programs Port 1 for open-drain output.
Port 2. Individual bits of Port 2 can be configured as inputs or outputs by programming
Port 2 Mode register (P2M) F6H. This port is
accessed by the UPC program as general
register 2H, and its functions and methods of
programming are the same as those of Port 1.
Port 3 pins P3! and P36 are the handshake
lines DAV2 and RDY2, with the direction (input
or output) determined by the state of bit 7 of
the port. The Port 3 Mode register also has a
bit used to program Port 2 for open-drain
output.
Function
Handshake
UPC Interrupt
Request*
{ THE LOWER NIBBLE
OF THE REGISTER FILE
ADDRESS (0101) IS
Counter/Timer
PROVIDED BY THE
INSTRUCTION
Master CPU
Test Mode
Line Direction
Signal
P3j
P33
P34
P36
!{
In
In
Out
Out
DAVj/RDYj
RDYj/DAVj
RDY2/DAV2
P30
P3j
P33
In
In
In
IRQ3
IRQ2
IRQj
{ P3j
P36
In
Out
P3s
P32
P30
P37
!
Out
In
In
Out
T7N
Tour
!NT
INTACK
lEI
lEO
P3S
Out
AID
DAV2/RDY2
*P30, P31, and P33 can always be used as UPC mterrupt
request mputs, regardless of the conhguratIon
programmed.
Table 1. Port 3 Control Functions
20j7·003
Functional
Description
(Continued)
.. Nonretriggerable trigger input for the UPC
internal clock divided by four.
Port 3. This port can be configured as I/O or
control lines by programming the Port 3 Mode
register. Port 3 is accessed as general register
3H. The directions of the eight data lines are
fixed. Four lines, P3a through P33, are inputs,
and the other four, P34 through P37, are outputs. The control functions performed by Port
3 are hsted in Table l.
.. External gate input for the UPC internal
clock divided by four.
Interrupts. The UPC allows six interrupts from
eight different sources as follows:
.. Port 3 lines P3a, P32, and P33.
Counter/Timers. The UPC contains two 8-bit
programmable counter/timers, each driven by
an internal 6-bit programmable prescaler.
The Tl prescaler can be driven by internal
or external clock sources. The TO prescaler is
driven by an internal clock source. Both
counter/timers operate independently of the
processor instruction sequence to relieve the
program from time-critical operations like
event counting or elapsed-time calculation. TO
Prescaler register (PREO) F5H and Tl Prescaler register (PREl) F3H can be programmed
to divide the input frequency of the source
being counted by any number from 1 to 64. A
counter register (F2H or F4H) is loaded with a
number from I to 256. The corresponding
counter is decremented from this number each
time the prescaler reaches end-of-coun!. When
the count is complete, the counter issues a
hmer interrupt request; IRQ4 for TO or IRQ5
for Tl. Loading either counter with a number
(n) results in the interruphon of the UPC at the
nth count.
The counters can be started, stopped,
restarted to continue, or restarted from the initial value. They can be programmed to stop
upon reaching end-of-count (Smgle-Pass
mode) or to automatically reload the initial
value and continue counting (Modulo-n Continuous mode). The counters and pre scalers
can be read at any hme without disturbing
their values or changing their counts. The
clock sources for both timers can be defined as
anyone of the following:
l1li
.. The master CPU(3).
.. The two counter/timers.
These interrupts can be masked and globally
enabled or disabled using Interrupt Mask
Register (lMR) FBH. Interrupt Priority Register
(lPR) F9H specifies the order of their priority.
All UPC interrupts are vectored.
Table 2 lists the UPC's interrupt sources,
their types, and their vector locations in program ROM. Interrupt Request IRQ6 is
dedicated to master CPU communications.
Interrupt Requests IRQI, IRQ2, and IRQ3 are
generated on the falling transitions of external
inputs P33, P31, and P3a. Interrupt Requests
IRQ4 and IRQ5 are generated upon the timeout
of the UPC's two counter/timers. When an
interrupt request is granted, the UPC enters an
interrupt machine cycle. This cycle disables all
subsequent interrupts, saves the Program
Counter and Status Flags, and branches to the
program memory vector location reserved for
that interrupt. ThiS memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
The UPC also supports polled systems. To
accommodate a polled structure, any or all of
the interrupt mputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Following any hardware reset operation, an
EI instruction must be executed to enable the
setting of any interrupt request bit m the
IRQ register. Interrupts must be disabled prior
to changing the content of either the IPR
(F9H) or the IMR (FBH). DI IS the only instruction that should be used to globally disable
interrupts .
UPC internal clock (4 MHz maximum)
divided by four.
lIII External clock input to Counter/Timer
Tl
via P31 (l MHz maximum).
.. Retriggerable trigger input for the UPC
internal clock divided by four.
Vector
Name
Source
Location
Comments
IRQo
EOM, XERR, LERR
a,1
Internal (RO BIts 0, I, 2)
IRQ)
DAV), IRQ)
2,3
External (P33) I Edge Tnggered
IRQ2
DAV2, IRQ2, TIN
External (P3)) I Edge Tnggered
IRQ3
IRQ3. IEI
4,5
6,7
IRQ4
TO
8,9
Internal
IRQ5
II
10,11
Internal
External (P30) I Edge Tnggered
Table 2. Interrupt Types. Sources. and Vector Locations
309
d
..,
n
I
Functional
Description
(Continued)
Master CPU Register File Access. There are
two ways in which the master CPU can access
the UPC register file: direct access and block
access.
Direct Access. Three UPC registers-the Data
Transfer Control (OH), the Master Interrupt
Vector (FOH), and the Master Interrupt Control
(FEH)-are mapped directly into the master
CPU address space. The master CPU accesses
these registers via the addresses shown in
Table 3.
The master CPU also has direct access to 16
registers known as the DSC (Data, Status,
Command) registers. The DSC registers are
numbered 0 through F (DSCO-DSCF). These
registers can be any 16 contiguous register file
registers beginning on a 16-byte boundary.
The base address of the DSC register group is
deSIgnated by the IRP (IIO Register Pointer),
which is bits D4-D7 of the Data Transfer Control register (OH). Figure 7 shows how the
register address is made up of the 4-bit IRP
field, concatenated with the low order 4-bits of
the address from the master CPU.
Block Access. The master CPU may transmit
·or receive blocks of data vIa address xxxIII II.
When the master CPU accesses this address,
the UPC register pointed to by the Data
Indirection register is read or written. The
Data Indirection register is incremented, and
the Limit Count .register is decremented, for
example, when the master CPU issues a read
or write to address xxxIII II while the Data
Indirection register contains the value 33H.
The operation causes register 33H to be read
or written and the Data Indirection register to
be incremented to 34H. This scheme IS well
suited to Block I/O Instructions and allows the
master CPU to efficiently read or write a block
of data to or from the UPC.
The Limit Count register (04H) is
decremented and is used to control the
number of bytes to be transferred by master
CPU block accesses. If the master CPU
attempts a read or write to the UPC after the
Limit Count register reaches 0, the access is
not completed, the LERR bit (D2) of the Data
Transfer Control register is set (indicating a
limit error), and the LERR error causes an
IRQo interrupt request.
The IRP field of the Data Transfer Control
register, the Data Indirection register, and the
Limit Count register are not directly accessible
to the master CPU and therefore must be set
by the UPC. This allows the UPC to protect
itself from master CPU errors and frees the
master CPU from tracking the UPC's internal
data layout.
UPC Address
Decimal
Hex
0
Identifier
OH
DIC
DIND
Address
xxxi 1000
S
SH
@S"
@SH"
240
FOH
MIV
xxx 10000
2S4
FEH
xxxiii II
MIC
xxxllllO
'n
DSCO
xxxOOOOO
n+1
DSCI
xxxOOOOI
n+2
DSC2
xxxOOOIO
n+3
DSC3
xxxOOOIl
n+4
DSC4
xxxOO100
ADDRESS FROM CPU
n+S
DSC5
xxxOO 10 I
I~I~I~I~I~I~I~I~I
n+6
DSC6
xxxOO11O
n+7
DSC7
xxxOOll1
n+B
DSCS
xxx01000
n+9
DSC9
xxx01001
n+ 10
DSCA
xxxOlO1O
n+ II
DSCB
xxxO 10 II
n+ 12
DSCC
xxxOllOO
n+ 13
DSCD
xxxOl101
n+ 14
DSCE
xxxOlllO
n+ IS
DSCF
xxxOll1l
DTC
IRP
~
I
[R, IR, IR, IR, IR,I R,I R, IRo I
REGISTER
FILE
x
=
don't care
*n IS the value In the IRP x 16
...... Master CPU accesses the regIster address
In
RegIster 5
Table 3. Master CPU/UPC Register Map
Figure 7. DSC Register Addressing Scheme
310
2017-004
Special
Configurations
There are two Protopack and two 64-pin versions of the UPC. These versions are identical to the 40-pin UPC with the following
exceptions:
• Internal ROM is totally omitted from the
64-pin development and ROM Protopack
versions.
64-Pin and Protopack Pin Functions. Forty of
the pins on the 64-pin and Protopack versions
have functions identical to those of the 40-pin
version. The remaining 24 pins have additional
functions described below. (Figures 9 through
II show the 64-pin and Protopack versions' pin
functions and pin assignments.)
Au-All. Program Memory Address Lines (out-
• All but 36 bytes of internal ROM are omitted
from the 64-pin RAM and Protopack RAM
versions.
put). These lines are identical in all 64-pin and
RAM versions in the Protopack. They are used
to address 4K bytes of external UPC memory.
• The memory address and data lines are buffered and brought out to external pins or to
the socket on the Protopack.
Do-l>7. Program Data (input). Data is read in
from the external memory on these lines. The
RAM version also writes external memory
through this bus.
lACK. Interrupt Acknowledge (output, active
High). This signal is active whenever an internal UPC interrupt cycle is in process.
II Control lines for the external memory are
also prOVided.
The 64-pin version of the UPC allows the
user to prototype the system in hardware with
an actual UPC device and to develop the code
intended to be mask programmed into the
on-chip ROM of the 40-pin UPC for the production system. The 64-pin or Protopack RAM
versions of the UPC are extremely versatile
parts. Memory space can be extended to 4K
bytes on the 64-pin version by using external
RAWROM for all but 36 bytes of the UPC's
memory space. This memory can then be
down-loaded from the master CPU using a
bootstrap program stored in the 36 bytes
(C-2F). Figure 8 is a memory map for the
64-pin RAM version.
1
DATJ
BUS
BUS{
TIMING
AND RESET
CONTROL {
INTERRUPT {
FFFH . . . - - - - - - - - - - - ,
EXTERNAL
RAM
PROGRAM MEMORY
EXTERNAL
DATA
1f
~~~ 1------------1
EXTERNAL {
BOOTSTRAP ROM
}
INTERNAL
ROM
}
EXTERNAL
RAM
CONTROL
~~~----------1
PCLK
Z UPC INTERRUPT
VECTORS
+5V
~------------~
Figure 8. UPC RAM Version Memory Map
2017-005,006
Figure 9. Z8591/Z8592 UPC Pin Functions
311
Special
Configurations
(Continued)
MAS. Memory Address Strobe (output, active
MR/W. Memory Read/Write (output RAM ver-
Low). This address strobe is pulsed once for
each memory fetch to interface with quasistatic RAM.
sions only). This signal is High when the UPC
is fetching art instruction and Low when it is
loading external memory.
MOS. Memory Data Strobe (output, active
SYNC. Instruction Sync (output, active Low).
Low). This signal is Low during an instruction
fetch or memory write.
This signal is Low during the clock cycle just
preceding an opcode fetch .
•3,
.3,
1
.2,
.2,
P321INTACK
.2,
os
.3,
."
.
"
13
1.
15
16
17
Z8591
40 P31
39 P36
38 P21
P3011EI 4
37 P26
P3s100 5
36 P25
P3211 NT ACK 6
35 P2.
DB,
RD7
34 P23
WR 8
33 P22
DBs
AlO 9
32 P21
CS
Z8592
upc
18
+5V 1
PCLK 2
P3rllEO 3
DB,
MAS
MAIWIIACK
10
31 P20
GND 11
30 P33
WAIT 12
29 P3 •
DBT 13
28 P11
DBs 14
27 P16
DBs 15
26 P1s
DB. 16
25 P14
083 17
24 P13
DB2 18
23 Ph
DB, 19
22 P1,
OBo 20
21 P10
0,
*SOCKET FOR 2716 EPROM (2K x 8) OR RAM
A10
Figure 10. Z8591/ZS592 UPC Pin Assignments
Addressing
Modes
Additional
Symbols
The following notation is used to describe the
addressing modes and instruction operations as
shown in the Instruction summary.
R
RegIster or working-regIster address
Workmg-reglster address only
IR
Indirect-regIster or indirect working-register
Ir
address
IndIrect working-register address only
dB!
DestinatIon location or contents
arc
Source location or contents
Condlhon code (see hst)
IndIrect address prefix
SP
Stack Pomter (control regIster FFH)
PC
Program Counter
FLAGS Flag regIster (control regIster FCH)
RP
Register Pomter (control register FDH)
Interrupt Mask register (control register FBH)
IMR
cc
@
312
Figure 11. Z8593/Z8594 UPC Protopack Pin Assignments
RR
IRR
In
X
DA
RA
1M
RegIster paIr or working~reglster pair address
Indirect regIster pair or indIrect workmg-register
pair address
IndIrect working-register paIr only
Indexed address
Direct address
Relahve address
ImmedIate
Assignment of a value is indicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
2017-007.008
Flags
Control Register FCH contains the following six
flags:
Affected flags are indicated by:
o
I
Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag
C
Z
S
V
D
H
Condition
Codes
Value
*
X
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Cleared to zero
Set to one
Set or cleared according to operatIon
Unaffected
Undefined
Flags Set
Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Mmus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
C = 1
C = a
Z
1
a
Z
S
0
I
S
V
1
V
a
I
Z
Z
0
(8 XOR V) = 0
(8 XOR V) = 1
[Z OR (8 XOR V)] = 0
[Z OR (8 XOR V)] = I
C=O
C = 1
(C = 0 AND Z = 0)
(COR Z) = 1
Never true
Instruction
Formats
ope
d't
CCF, 01, EI, IRET, NOP,
ReF, RET, SCF
ope
INC r
One-Byte Instructions
ope
MODE
dsUsrc
ope
OR
I
d"
h 1 1 01 dst/src I
CLR, CPL, OA, DEC,
DECW, INC, INeW, POP,
PUSH, Rl, RLC, RR,
RRC, SRA, SWAP
ope
Ace, ADD, AND, CP,
LD, OR, ssc, SUB,
TeM, TM, XOR
MODE
OR
OR
d"
til 0
a
d"
b 1 1 01
d,t
1 1 1
JP, CALL (Indirect)
OR
11
1 1
01
d,t
I
ope
MODE
d"
ope
SRP
OR
Ace, ADD, AND, CP,
LO, OR, SSC, SUB,
TeM, 1M, XOA
VALUE
VALUE
MODE
ope
MODE
Ace, ADD, AND,
CP, OR, SSC, SUB,
d"
TeM, TM, XOR
MODE
ope
dstlsrc
src/dst
ope
ope
L.D, L.DE, L.DEt,
MODE
LDC, LOCI
dstlsrc
LD
OR
OR
'"
d"
1 1 1
a
til 0
d"
LD
ADDRESS
ope
dstlsrc
srcldsl
d"
I ope
OR
11
1 1
01
LD
LD
ope
JP
DA,
DAc
VALUE
ope
IdstlCCR~ ope
DJNZ, JR
Two-Byte Instructions
2037-013
CALL
DA,
DAc
Three-Byte Instructions
313
Opcode
Lower Nibble (Hex)
Map
o
6,5
DEC
IRI
6,5
ADD
6,5
ADD
II, 12
6,5
RLC
RI
6,5
ADC
6,5
INC
RI
6,5
RLC
IRI
6,5
INC
IRI
B,O
JP
IRRI
6,1
SRP
1M
4
8,5
DA
HI
8,5
DA
JRI
5
10,5
POP
HI
10,5
POP
IRI
6
6,5
COM
HI
6,5
COM
IRI
10/12,1
12114,1
PUSH
IR2
II
!;
.!
.Q
:9
7
:z;
~
II
'"'"
3
6,5
DEC
RI
o
"
2
8
::>
9
A
B
C
D
PUSH
R2
10,5
INCW
RRI
10,5
INCW
JRI
6,5
CLR
RI
6,5
RRC
RI
6,5
SRA
HI
RR
HI
F
II, Ir2
10,5
ADD
R2,RI
10,5
ADD
IR2,RI
10,5
ADD
RI,IM
10,5
ADD
IRI,IM
II, I,;z
6,5
ADC
II, Ir.:z
10,5
ADC
R2,RI
10,5
ADC
IR2,RI
10,5
ADC
RI,IM
10,5
ADC
IRI,IM
6,5
SUB
6,5
SUB
II, r2
II, III
10,5
SUB
R2,RI
10,5
SUB
IR2,RI
10,5
SUB
RdM
10,5
SUB
IRdM
6,5
SBC
6,5
SBC
10,5
SBC
II, r;z
II,Il2
R2,Rl
10,5
SBC
JR2, HI
10,5
SBC
RI,IM
10,5
SBC
JRI,IM
6,5
OR
6,5
OR
II, r2
II, III
10,5
OR
R2,RI
10,5
OR
JR2,HI
10,5
OR
RI,IM
10,5
OR
JRI,IM
6,5
AND
6,5
AND
II, r2
11,Ir;z
10,5
AND
H2,RI
10,5
AND
JR2, HI
10,5
AND
RI,IM
10,5
AND
IRdM
6,5
TCM
6,5
TCM
II, 12
tI,Ir2
10,5
TCl'II
H2,RI
10,5
TCM
IR2,RI
10,5
TCM
RI,IM
TCM
IRI,IM
6,5
TM
6,5
Tl'II
fl. 12
II, Ir2
10,5
TM
R2,RI
10,5
TM
IR2,RI
10,5
Tl'II
RI,IM
10,5
TM
JRI,IM
6,5
CP
6,5
CP
II, r2
r 1, Il2
6,5
CLR
IRI
6,5
XOR
6,5
XOR
tI, 12
II, Ir2
6,5
RRC
IRI
6,5
SRA
IRI
12,0
LDC
6,5
LD
II, R2
9
A
B
6,5
LD
I2, RI
12/10,5
12/10,0
DINZ
IR
n,RA
cc,RA
C
6,5
LD
rI,IM
D
E
IP
6,5
INC
cc,DA
n
12/10,0
r 1,
12,0
LDC
I2,IIII
6,5
RR
JRI
r---
r--r---
r--r---
la,S
r--DI
6,1
EI
10,5
CP
R2,RI
10,5
CP
JR2,RI
10,5
CP
RI,IM
10,5
CP
IRI,IM
10,5
XOR
H2,RI
la,S
XOR
IR2,HI
10,5
XOR
HI,IM
10,5
XOR
IRI,IM
'V"
2
14,0
RET
r--16, a
IRET
r---
6,5
'RCF
II, X, R2
10,5
LD
R2,HI
6,5
LD
20,0
CALL
la,S
LD
JR2, HI
DA
10,5
LD
I2, X, HI
10,5
LD
HI,IM
10,5
LD
IHI,IM
r--6,5
SCF
r--6,5
CCF
r---
10,5
LD
H2,IRI
Ill, 12
./
r---
10,5
LD
20,0
CALL"
1r2, Irn IHHI
II, Ir2
r---
-
18,0
LDCI
6,5
LD
F
6,1
18,0
LDCI
Irr2 Ir 1, Irr2
6,7
6,7
SWAP SWAP
HI
JRI
\",
Bytes per
Instruction
7
12,0
10,5
10,5
IB,O
DECW DECW LDE
LDEI
RHI
IRI
r 1. Irr2 In,Iu2
6,5
6,5
12,0
18, a
RL
RL
LDE
LDEI
HI
IRI
12, lIn Ir2.Irrl
6,5
E
6
I....
'V'"
6,0
NOP
.I
\",
'----------~,----------,./ ~ ~
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode- A
Nibble
First
Operand
t
Pipeline
Cycles
Mnemonic
Socond
Operand
Legend: ,
R = 8-Blt Address
r = 4-Blt Address
RJ or II = Dst Address
R2 or f2 = Src Address
Sequence:
Opcode, FIrst Operand, Second Operand
Note: The blank areas are not dehned,
*2-byte instructIon; fetch cycle appears as a 3-byte InstructIon
314
BOB5-002
Instruction
Summary
Instruction
and Operation
Addr Mode
ADC dst,sre
dst - dst + sre + C
(Note I)
ADD dst,sre
dst - dst + sre
(Note I)
AND dst,sre
dst - dst AND sre
(Note I)
dst
src
Opcode Flags Affected
Byte - - - (Hex)
CZSVDH
ID
..
* * 0 *
o•
00
LDEI dst,sre
dst - src
50
------
CCF
C - NOT C
EF
* ... ... ... - -
POP dst
dst - @SP
SP - SP +
R
IR
BO
BI
COM dst
dst - NOT dst
R
IR
60
61
CP dst,sre
dst - sre
(Note I)
DA dst
dst - DA dst
R
IR
00
01
R
IR
RR
IR
DINZ r,dst
RA
r - r- I
tf r;< 0
PC-PC+dst
Range: + 127, -128
.
• 0
INC dst
dst-dsl+1
* X- -
- * * * --
If CC IS
true
PC - dsl
IR ee,dsl
If CC IS
DA
IRR
RA
true,
r
R
X
r
Ir
R
R
R
1M
R
X
r
Ir
r
R
IR
-
...
- -
-
...
cD
e=O-F
30
------
eB
e=O-F
------
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E5
E7
F5
------
.
------
70
71
R
IR
10
II
RR dst
lEJ 4:::::3-J I~
EO
EI
LEJ=E::j}J
R
IR
CO
CI
(Note I)
3D
'
,
,
,
0
0
[09I~
SRP sre
RP - sre
1m
(Note I)
SWAP dst ~ R
IR
·
-
DF
I
DO
DI
.·
-
•
• I
-
• 0
31
20
FO
FI
TCM dst,sre
(NOT dst) AND sre
(Note I)
50
TM dst,sre
dsl AND sre
(Note I)
70
XOR dsl,sre
dst - dst XOR sre
(Note I)
BO
.
I
X
·
·
- ·
-
• X
• 0
• 0
* 0 . . ,.
1"'"
Note I
These mstruchons have an Idenhcal set of addressmg
modes, which are encoded for brevity. The hrst opcode
mbble IS found In the Instruction set table above. The
second Olbble IS expressed symbolically by a 0 In thl~
table, dnd Its value IS found In the followmg table to the
For example, to determme the opcode of an ADC
mstructlOn usmg the addressmg modes r (destmatlon) and
Ir (source)
15
13
Addr Mode
------
Irr
Ir
C3
D3
------
dst
sre
R
R
R
IR
Ir
R
lR
1M
1M
CI
. -- X
left of the applIcable addressing mode paIr.
C2
D2
Ir
R
IR
l.l:il=ciJ
RLC dst
SUB dst,sre
dsl - dsl - sre
Irr
LDCI dst,sre
50
51
90
91
------
r
dst - sre
Irr
r - r + 1; rr - rr + 1
R
IR
SCF
C-I
1M
1M
R
Irr
------ • 0 - -
40
R
IR
SBC dst,sre
dst - dst- sre - C
IR
IR
LDC dst,sre
dsl - sre
FF
(Note I)
0~
- - - - -.-
PC - PC + dsl
Range: + 127, -128
LD dst,sre
dsl - sre
----
RL dst
rA
r=O-F
IRET
BF
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR(7) -I
IP ee,dsl
83
93
------
RRC dst
AD
Al
Irr
Ir
AF
------
RR
IR
Ir
Irr
RET
PC - @SP; SP - SP + 2
8F
R
IR
----- ...
0-- - - -
**- -
rE
r=O-F
20
21
82
92
CF
80
81
9F
Irr
RCF
C-O
SRA dst
EI
IMR (7) - I
r
Irr
PUSH sre
SP - SP-I; @SP - sre
AD
40
41
DI
IMR (7) - 0
INCW dst
dsl - dsl +
-
src
NOP
D6
D4
CLR dst
dst - 0
Opcode Flags Affecteci
Byte
(Hex)
CZSVDH
dst
r-r + I; rr - rr + 1
0
CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst
DECW dst
dst-dst-I
8085-003
LDE dst,sre
dst - src
OR dst,sre
dst - dst OR sre
DEC dst
dst-dst-I
Addr Mode
Instruction
and Operation
Lower
Opeode Nibble
§
I1J
LiJ
~
[§J
[2J
315
I
I
I
Registers
R248 PIM
Port 1 Mode Register
UPC regder address (Hex): F8
R247 P3M
Port 3 Mode Register
UPC regIster address (Hex): F7
1~1~1~1~I~i~I~I~1
l~i~I~I~I~I~I~I~1
III ~:::::::::=::::
P10-P17 110 DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
1 PORT 1 PULL UPS ACTIVE
o P35 = OUTPUT
R246 P2M
Port 2 Mode Register
UPC regIster address (Hex): F6
1 P3S = INT
RESERVED
o P3J = INPUT
1 P33 = OAV1/RDYl
I~I~I~I~I~I~I~I~I
'------~ =~:
: ~:V~R~~J
' -_ _ _ _ _ _ ~ ~~~ : :~tUT
'-------- :
~ =~~
P34 = OUTPUT
P34 = RDY1fOAVl
:~:: ~~~~~~D;0UT)
=;~
:
~~TPUT
:~~~6K
Figure 12. Port Mode Registers
R251IMR
Interrupt Mask Register
UPC regIster address (Hex): FB
R250 IRQ
Interrupt Request Register
UPC regIster address (Hex): FA
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
um~
1
L
L lRao = MASTER CPU COMMUNICATIONS
~~~
L'ENABLEslRao
L
1 ENABLES IRQ1
1 ENABLES IRQ2
1 ENABLES IA03
IRQ1 = P3 3 1NPUT
IRQ2 = P3j INPUT
IR03 = P30 INPUT
1 ENABLES IRQ4
IRQ4 '" To
1 ENABLES IROS
lAOS = T1
RESERVED
RESERVED
1 ENABLES INTERRUPTS
R249IPR
Interrupt Priority Register
UPC register address (Hex): F9 (Wnte Only)
I~I~I~I~I~I~I~I~I
"",,,0 ~
INTERRUPT GROUP PRIORITY
RESERVED
000
C>A> B "" 001
A>B>C '" 010
=
II I Y-", ""' ",,,""""" '"
o=
> IRQ1
lRao, IR02 PRIORITY (GROUP B)
0= IR02 > IROO
1 = IROO>IR02
= 011
= 100
= 101
= 110
A>C>B
B>C>A
C> B>A
B>A>C
RESERVED =
IRQl > IRQ4
1 = IRQ4
IR03, IROS PRIORITY (GROUP A)
0 = IROS > IRoa
1 = IR03>IROS
111
Figure 13. Interrupt Control Registers
R254 MIC
Master CPU Interrupt Control Register
UPC reglSter address (Hex): FE
R240 MIV
Master CPU Interrupt Vector Register
UPC register address (Hex): FO
1~1~1~1~1~1~1~1~1
lli¥llg
LO1 END OF MESSAGE
~I-
_ _ VECTOR OATA (0, = LSB)
o WAIT ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE
a
ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN
DATA TRANSFER
1 ENABLE DATA TRANSFER
o DISABLE
o VECTOR OUTPUT
1 NO VECTOR OUTPUT
'-----'-------
~ ~~s~~~Tg~UCI~~~~~~~~U:ETN~~~gING
~ ~~~~~~~~U~~DUE~Di~~~~:ICE
'--------~ :~i~==~:i =~g~~~i ~~::LL:g
Figure 14. Master CPU Interrupt Registers
316
2017·009,010,011
Registers
(Continued)
R253 RP
Register Pointer
upe register address (Hex): FD
R252 FLAGS
Flag Register
upe register address (Hex): Fe
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
E~~
'
L
LUSERFLAGF1
REGISTER POINTER
c=
:=J
DON'T CARE
(r4- r1)
USER FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
R255 SP
Stack Pointer
upe register address (Hex): FF
CARRY FLAG
I~I~I~I~I~I~I~I~I
LI_ _ _ _
STACK POINTER
(SPO-SP7)
Figure 15. UPC Control Registers
R4LC
Limit Count Register
upe register address (Hex): 04
RODTC
Data Transfer Control Register
upe register address (Hex): 00
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
(EOMI
~
(XERR)
L
0-
LIMIT COUNT VALUE
_ _ _ _ _ (RANGE: 0-255 DECIMAL
OO-FF HEX)
1 END OF MESSAGE
0 NO TRANSFER ERROR
1 TRANSFER ERROR
(LERR)
NO LIMIT ERROR
LIMIT ERROR
(EDX)
DISABLE DATA TRANSFER
ENABLE DATA TRANSFER
R5 DlND
Data Indirection Register
upe register address (Hex): 05
I~I~I~I~I~I~I~I~I
1.!!(I~RP:!.I_ _ _ _ _ _ _ 1 110 REGISTER POINTER
L I_ _ _ _ _ _
:~~~i~~)ON ADDRESS
Figure 16. Master CPU-UPC Data Transfer Registers
R243 PREI
Prescaler I Register
upe register address (Hex): F3
R241 TMR
Timer Mode Register
upe register address (Hex): Fl
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
=
=
T1 OUT = 10
INTERNAL CLOCK OUT = 11
RESERVED
00
To OUT
01
TOUTMODESj
~~
0 '" NO FUNCTION
= 00
= LOAD 11
0 = DISABLE 11 COUNT
1
TRlg:~~ :~~~~ : ~~
(NON-RETRIGGERABLEj
TRIGGER INPUT
= DISABLE To COUNT
1 = ENABLE To COUNT
0
EXTERNTA~ ~~gg~
INPUT
~
L ~~U~:s';'N°a"LEEPASS
0 '" NO FUNCTION
1 '" LOAD To
1
= 11
=
1 '" 11 MODULO. N
CLOCK SOURCE
o = EXTERNAL TIMING
INPUT
(TIN) MODE
1 :: 11 INTERNAL
PRESCAlER MODULO
ENABLE T~ COUNT
(RANGE: 1-64 DECIMAL
01-00 HEX)
(RETRIGGEAABLE)
R244 TO
CounterlTimer 0 Register
upe register address (Hex): F4
R242 Tl
Counter/Timer I Register
upe register address (Hex): F2
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
I
To INITIAL VALUE
' - - - - - (RANGE: 1-256 DECIMAL
01-00 HEX)
T11NITIAL VALUE
' - - - - - - (RANGE: 1-256 DECIMAL
01-00 HEX)
R245 PREO
Prescaler 0 Register
upe register address (Hex); F5
I~I~I~I~I~I~I~I~I
~L
COUNTMODE
o
1
= To SINGLE-PASS
= To MODULO· N
RESERVED
PRESCALER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)
Figure 17. UPC Counter/Timer Registers
2017-012,014,013
317
Registers
(Continued)
Control Register
OOH
Data Transfer Control RegIster
0,
D6
DS
D4
D3
D2
Dl
Do
Comments
X
X
X
X
0
0
0
0
DIsable data transfer
from master CPU
0
0
0
Stops TO and Tl
X
0
0
SIngle-Pass mode
X
0
0
Single-Pass mode
External clock source
Not Defined
04H
LImIt Count RegIster
05H
Not Defined
Data IndIrectIon RegIster
Not DefIned
FOH
Interrupt Vector RegIster
FIH
TImer Mode
0
0
0
X
X
X
X
X
Not DefIned
F4H
Tl RegIster
F5H
Tl Prescaler
0
Not DefIned
F2H
TO RegIster
F3H
TO Prescaler
0
X
X
X
X
X
Port 2 hnes defIned as
inputs
F6H
Port 2 Mode
F7H
Port 3 Mode
0
0
0
0
X
0
0
Port 1. 2 open draIn;
P35 = INT; P30. P3j. P32.
P33 defIned as Input; P34.
P36. P37 defIned as output.
Port I hnes defIned as
mputs
F8H
Port I Mode
Not DefIned
F9H
Interrupt Pnonty
FAH
Interrupt Request
X
X
0
0
0
0
0
0
Reset Interrupt Request
FBH
Interrupt Mask
0
X
X
X
X
X
X
X
Interrupts dIsabled
0
0
0
Master CPU mterrupt dlsabled; walt enable when
wnte; lower cham enabled
FCH
Flag RegIster
Not Defined
FDH
Not DefIned
RegIster Pomter
FEH
Master CPU Interrupt
Control RegIster
FFH
Stack POInter
0
0
0
0
0
Not DefIned
NOTE: X means not defIned
Table 4. Control Register Reset Conditions
318
Absolute
Maximum
Ratings
Voltages on all pins (except VBB)
with respect to GND .......... -0.5 V to +7.0 V
Operating Ambient
Temperature .................. 0 °C to + 70°C
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
following standard test condihons, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
Stresses greater than those lIsted under Absolute MaxImum Ratmgs may cause permanent damage to the devIce.
ThIs IS a stress ratmg only; operahon of the devIce at any
condIhon above those mdICated In the operatIonal sections
of these specIhcatIons IS not Imphed. Exposure to absolute
mdXlmum ratmg condItions for extended perIods may affect
deVIce relIabIlIty.
• +4.75 V
~
Vcc
~
+5.25 V
Vss = GND = 0 V
!II O°C ~ TA ~ +70°C
II
+5V
+5V
22K
18K
Figur'; 18. Test Load I
DC
Characteristics
Symbol
Min
Max
Unit
Vcc
0.8
V
VCH
Clock Input Hlgh Voltage
2.4
VCL
Clock Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
-0.3
VOH
Output High Voltage
VOL
Output Low Voltage
VCC
0.8
Condition
Notes
V
V
V
V
IOH = -250 p.A
0.4
V
IOL = +2.0 rnA
2.4
IlL
Input Leakage
-10
10
IoL
Output Leakage
-10
10
p.A
p.A
Icc
Vcc Supply Current
180
rnA
I
8085·006, 312
Parameter
Figure 19. Test Load 2
o :5
o :5
For AO-All and DO-D7, MDS, SYNC, MAS, and MR/W/IACK on the 64'pm versIOns. IOH
=
VIN
:5
+5.25 V
VIN
:5
+5.25 V
100 "A and 10L
= lOrnA
319
Master CPU
Interface
Timing
Number Symbol
2
Min (ns) Max (ns)
Parameter
TrC
Clock Rise Time
TwCh
Clock High Width
20
TfC
Clock Fall Time
TwCl
Clock Low Width
105
1855
250
2000
TpC
Clock Period
6-
TsAlD(WR) -
20
7
TsAlD(RD)
8
ThAlD(WR)
9
ThAlD(RD)
AID to WR I Setup Time
AID to RD I Setup TIme
AID to WR I Hold TIme
AID to RD 1 Hold TIme
10
TsCSf(WR)
CS I toWR I Setup TIme
II -
TsCSf(RD) - - CS I to RD I Setup Time
12
TsCSr(WR)
CS 1 to WR I Setup TIme
60
60
80
80
30
30
0
0
13
TsCSr(RD)
CS 1 to RD I Setup Time
14
ThCS(WR)
CS to WR I Hold TIme
0
IS
ThCS(RD)
CS to RD I Hold Time
0
0
17
Tw(WR)
WR Low Width
390
18
Tw(RD)
RD Low Width
390
19
ThWR(DI)
Data
20
TdRD(DI)
Data Valid from RD I Delay
In
to WR 1 Hold TIme
0
21- ThRD(DI) - - Data Valid to RD 1 Hold Time
0
22
TdRD(DIz)
Data Bus Float Delay from RD 1
23
TdRD(DBA)
RD I to Read Data Active Delay
24
TdWR(W)
WR I to WAIT I Delay
25
TdRD(W)
RD I to WAIT I Delay
26
TdDI(W)
Data Valid to WAIT 1 Delay
Number Symbol
Parameter
27
TsACK(RD)
INTACK I to RD I Setup TIme
28
29
TdRD(DI)
ThRD(ACK)
RD I to Vector Vahd Delay
70
0
150
150
0
Min (ns) Max (ns)
90
RD 1 to !NTACK 1 Hold TIme
0
100
33
34
TsIEl(RD)
TdACKf(lEO)
IEI to RD I Setup Time
!NTACK I to IEO I Delay
35
TdACKr(IEO)
IN TACK 1 to IEO 1 Delay
IS
dependent on the state of the UPC at the bme
of master CPU access.
2. In case where daiSY cham IS not used.
3. The tlmmg characterIstics given reference 2.0 V as HIgh and
O.B V as Low
Notes"
2
255
ThIEI(RD)
IEI to RD I Hold TIme
30
31-TwRDI--- RD (Acknowledge) Low Width
TdIEI(IEO)
IEI to IEO Delay
32
NOTES:
1 This parameter
320
1855
4
16-TsDI(WR)-- Data in to WR I Setup Time
Interrupt
Acknowledge
Transactions
105
3
5
Notes"
255
120
150
250
250
4 All output ae parameters use test load 1
*Tlmmgs are prehmmary and subject to change.
Master CPU
Interface
Timing
DBO-DB7
WAITE CASE
------+--+,1<-+-------t-"n.f----1H----------
__
DBO-DB7------~~~~fft=~~~~~~~~--11 ~~~-----
READ CASE
Interrupt
Acknowledge
Timing
~
DBo-DB7
~
~
.J
lEI
lEO
2022-015,016
VECTOR
)
...... ®I-
-----®-l~
.
I------:-@---
---{t~
i----@---.
--
K
®
321
Handshake
Number Symbol
Min (ns)
Parameter
Max (ns)
Notes·
Timing
Reset
Timing
TsDI(DA)
Data In Setup TIme
2
ThDA(DI)
Data In Hold Time
230
3
TwDA
Data Available WIdth
175
4
TdDAL(RY)
Data Available Low to Ready
Delay Time
20
0
5
TdDAH(RY)
Data Available High to Ready
Delay TIme
6
TdDO(DA)
Data Out to Data Avadable
Delay TIme
7
TdRY(DA)
Ready to Data Available Delay TIme
Number Symbol
0
1,2
2,3
150
0
1,2
2,3
50
2
0
Min (ns)
Parameter
1,2
175
TdRDQ(WR)
Delay from RD t to WR I for No Reset
40
2
TdWRQ(RD)
Delay from WR t to RD I for No Reset
50
3
TwRES
Mmlmum WIdth of WR and RD both Low
for Reset
205
2
Max (ns)
Notes·
250
4
'1/
RAM Version
,Program
Membry
timing
Number Symbol
Parameter
!
Notes·
TwMAS
Memory Address Strobe Width
60
5
TdA(MAS)
Address Vahd to Memory Address Strobe t Delay
30
5
3
TdMRIW
(MAS)
Memory ReaclJWnte to Memory Address Strobe I
Delay
30
5
4
TdMDS(A)
Memory Data Strobe t to Address Change Delay
60
5
TdMDS
(MR/W)
Memory Data Strobe I to Memory Read/Wnte Not
Valid Delay
80
6
Tw(MDS)
Memory Data Strobe Width (Wnte Case)
7
TdDO(MDS)
Data Out Vahd to Memory Data Strobe I Delay
8
TdMDS(DO)
Memory Data Strobe t to Data Out Change Delay
9
Tw(MDS)
Memory Data Strobe WIdth (Read Case)
10
TdMDS(DI)
Memory Data Strobe I to Data In Valid Delay
160
7
II
TdMAS(DI)
Memory Address Strobe I to Data In Valid Delay
280
7
160
6
30
5
30
5
230
12
ThMDS(DI)
Memory Data Strobe t to Data In Hold TIme
13
TwSY
Instruchon Sync Out WIdth
160
14
TdSY(MDS)
Instruchon Sync Out to Memory Data Strobe Delay
200
15
TwI
Interrupt Request vIa Port 3 Input WIdth
100
2 Test Load 1
3 Output Handshake
4 Internal reset signal IS V2 to 2 clock delays from external reset
condlhon.
5. Delay hmes are specIfied for an mput clock frequency of
4 MHz. When operahng at a lower frequency, the Increase In
mput clock penod must be added to the specified delay hme.
6. Data strobe wIdth IS speclhed for an Input clock frequency of
4 MHz. When operating at a lower frequency, the mcrease In
!
Max (ns)
2
NOTES
1. Input Handshake
322
Min (ns)
6
0
three mput clock perIods must be added to the specIfIed width.
Data strobe width varies according to the instructIon bemg
executed.
7. Address strobe and data strobe to data In vahd delay hmes
represent memory system access hmes and are gIven for d
4 MHz mput frequency.
All hmmg references assume 2.0 V for a lOgIC "1" and 0.8 V
for a lOgIC "0."
All output ac parameters use test load 2.
* TImmgs are prelimmary and subject to change
Handshake
Timing
X
DATA IN
DATA IN VALID
DAY
INPUT
-'0(
ROY
1
OUTPUT
K
1+v
1-0--1 ---(2Xi)-'\
1
t
PORT
READ
Input Handshake
DATA OUT
DATA OUT VALID
DAY
OUTPUT
I
ROY
\
INPUT
\
Output Handshake
Reset
Timing
RAM Version
Program
Memory
Timing
MAS
\L 1/
f-0--j
0-- I-
)
Ao-A11
ADDRESS VALID
G:r- lMRlW
)
(RAM VERSION
ONLY)
~I
I~P CDr-
MDS
WRITE CASE
M
00-07
WRITE CASE
X
DATA VALID OUT
-J,\
~
MDS
READ CASE
-®----13
2017-017,018
2014-024
2017-019
®
.
12
~
DATA
VALID
IN
323
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
28592
QS
4.0 MHz
UPC External
RAM-based
Program Memory
(54-pm)
28593
RS
4.0 MHz
UPC
2715 EPROM
Program Memory
(40-pm)
28594
RS
4.0 MHz
UPC RAM
Program Memory
(40-pin)
28590
CE
4.0 MHz
UPC (40-pin)
28590
CS
4.0 MHz
Same as above
28590
DE
4.0 MHz
Same as above
28590
DS
4.0 MHz
28590
PE
4.0 MHz
Same as above
Same as above
28590
PS
QS
4.0 MHz
Same as above
4.0 MHz
UPC External
ROM-based
Program Memory
(54-pin)
28591
NOTES C = Ceramic, D = Cercilp, P = Plastic, Q = QUIP, R
324
= Protopack; E
Package/
Temp
Speed
= -40'C to +85'C, S
= G'C to
Description
+70'C.
Z8 FaDliiy
liilog Z8™ Family
~
Zilog
The New Standard F@r
§ingle..Chip Microcompuiers
March 1981
The Z8 Family of microcomputers
offers the most sophisticated processing capabIlity available on a
single chip. As an extension of
earlier generations of microcomputers, the Z8 Family provides
standard on-chip funchons,
such as:
lID 2K or 4K bytes of ROM·
Ii!!
144 8-bit registers
III 32 lines of programmable 1/0
III Clock oscIllator
In addition, the Z8 FamIly offers
advanced on-chip features,
includmg:
III Two counter/timers
II!I
Six vectored interrupts
Ill!
UART for serial 1/0 communication
m Stack functions
m Power-down ophon
I!I
TTL compatibility
The capabIlity of the Z8 FamIly
of mICrocomputers is expandable
off-chIp to provide an addItional
62K bytes of program memory and
62K bytes of data memory for the
2K-byte ROM version. It provIdes
an addlhonal 60K bytes of program
memory and 60K bytes of data
memory for the 4K-byte ROM version. The interface to external
memory is accomphshed through
one, one and one- half, or tHO of
the 8-bit 1/0 ports, depending on
the number of address bits
required for the external funchons.
The Z-BUS protocol allows easy
mterface to external functIOns
. including Zilog's family of
peripheral chIps.
With the thlrd-generahon Z8
FamJly, Zilog IS pushmg the capability of microcomputers beyond
the first and second generahon of
computers. The Z8 Family
challenges the "mulh-chlp
soluhon" deSIgn currently
implemented by general-purpose
mIcroprocessors. DeSIgns based on
Z8-Family microcomputers offer a
mmimum chip-count configurahon
that can easJly be expanded to
meet requirements for enhancement ophons and for future
improvements.
Optimized Instruction Set. The
mstruction set of the Z8-Family
microcomputers IS ophmized for
hIgh-code denSIty and reduced
executIOn hme. This feature IS supported by a "workmg regIster
area" concept that uses short
(4-blt) register addresses. The
general-purpose registers can be
used as accumulators, as address
pomters for indirect addressing, as
index registers, or for Implementing an on-chip stack.
The 47 instruction types and SIX
addressmg modes-together wIth
the ability to operate on bits, 4-bit
BCD digits, 8-blt bytes, and 16-blt
words-offer unique programmmg
capabJllty and flexibJllty.
327
Growing Family. The Z8 Family
of microcomputers IS growmg to
meet the needs of more complex
designs. The 4K ROM verSIOn of
the Z8 microcomputer (the Z8610
series) offers all the features of the
Z8 Family, plus 4K bytes of on-chip
ROM. The increased ROM allows
the desIgner to take advantage of
the code ophmizatlOn mherent in
the Z8 mstruchon set when using
between 2K and 4K bytes of program memory.
The ROMless mIcrocomputer
provides an alternative for
designers seeking to take advantage of the on-chIp features of the
Z8601 in apphcations that reqUIre
external program memory. A
Z8681 mIcrocomputer can be used
to control a system that addresses
up to 128K bytes of off-chip
memory.
The Z8671 mICrocomputer IS a
Z8-based BASIC/debug interpreter
on a chip. The BASIC used m the
Z8671 IS a subset of Dartmouth
BASIC with the added capab!llty of
interachon between the mterpreter
and ItS envIronment through the
debug faCIlity. The BASIC/debug
interpreter resides in the 2K of onchip ROM, with all the features of
the Z8 mICrocomputer at ItS
disposal.
Expanded Applications. The Z8
Family of mIcrocomputers IS fmding its way mto increasingly
sophlshcated desIgns. In addihon
to the low-end capab!llty applications commonly used with mIcrocomputers, the Z8 FamIly of mIcrocomputers can be used effectively
m such applicahons as:
Z8
MICROCOMPUTER
SERIAL
COMMUNICATIONS
UART
Figure!. Z8-Based Intelligent Terminal
328
Computer penpheral controllers
• Smart
terminals
II
II
Dumb terminals
II
Telephone switchmg systems
II
Arcade games and mtelligent
home games
.
Process control
II
Intelligent mstrumentation
II
Automotive mechamsms
An example of how a Z8 might
be used in the design of an intelhgent termmal is shown in Figure 1.
The features of such a termmal
depend on its specific reqUIrements, but it is clear that the Z8
mICrocomputers offer unprecedented capability and flexibIlity to
the microcomputer designer.
Z8™ Family oi
Microcomputers
:£8601 " 18602 " 18603
Product
Specification
~
Zilog
March 1981
Z8601 Smgle-Ch,p MIcrocomputer wIth 2K ROM
Z8602 Development DevIce wIth Memory Interface
Z8603 Prototypmg DevIce wIth EPROM Interface
Features
III Complete mIcrocomputer, 2K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
62K bytes addressable external space each
for program and data memory.
III 144-byte register file, includmg 124
general-purpose registers, four 1/0 port
regIsters, and 16 status and control
registers.
General
Description
III
Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit programmable pres caler .
D
RegIster Pointer so that short, fast instructions can access any of nine working
register groups in 1.5 p.s.
EJ On-chIp oscillator which accepts crystal or
external clock drive.
III Average instruchon execuhon time of
2.2 p.s, maxImum of 4.25 p.s.
[J
III Vectored, priority interrupts for 110,
counterltimers, and UART.
CI Single
The 28601 microcomputer introduces a new
level of sophIstication to smgle-chip architecture. Compared to earlier single-chip microcomputers, the 28601 offers faster execution;
more efficIent use of memory; more sophishcated mterrupt, mputloutput and bit-manipulation capabillbes; and easier system expansion.
Under program control, the 28601 can be
tailored to the needs of its user. It can be con-
Low-power standby option which retains
contents of general-purpose regIsters.
+ 5 V power supply-all pins TTLcompatible.
figured as a stand-alone microcomputer wIth
2K bytes of mternal ROM, a traditional microprocessor that manages up to 124K bytes of
external memory, or a parallel-processing element m a system wIth other processors and
peripheral controllers linked by the 2-BUS. In
all conhgurations, a large number of pms
remam aVailable for I/O.
+5V
P3,
XTAL2
P3,
XTAL1
P2,
P3,
P2,
P3,
PORT 0
.-.
(NIBBLE
PROGRAMMABLE)
'0 OR A" A
PORT 1
(BYTE
PROGRAMMABLE)
10 OR AD -AD
I
I
I
I
PORT 2
(BIT PRO
GRAMMABLE)
10
P2,
RIW
P2,
ers
P2,
AS
P2,
P3,
P2,
GND
P3,
P3,
P3,
P1,
PORT 3
(FOUR INPUT,
po,
po,
po,
FOUR OUTPUT)
PD,
P1,
po,
po,
po,
po,
P1,
I
I
SERIAL AND
f'ARALU::L 1:0
AND CONTROL
Figure I. Z8GOI MCU Pin Functions
2037 ·001. 002
P2,
RESET
Figure 2. ZeGl
P1,
P1,
P1,
P1,
P1,
MCU Pin Assignments
329
Architecture
Z8601 archItecture IS characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancdlary features that are helpful in many
applicahons.
Microcomputer applications demand powerful I/O capabIlities. The Z8601 fulhlls thIs with
32 pins dedicated to input and output. These
lines are grouped mto four ports of eight lines
each and are configurable under software control to provIde timmg, status sIgnals, serial or
parallel I/O with or without handshake, and an
address/data bus for interfacmg external
memory.
Because the mulllplexed address/data bus is
merged with the I/O-oriented ports, the Z8601
can assume many dIfferent memory and I/O
conhgurations. These conhgurahons range
from a self-contained microcomputer to a
OUTPUT
INPUT
Vee
microprocessor that can address 124K bytes of
external memory.
Three basic address spaces are available to
support this wide range of configurations: program memory (internal and external), data
memory (external) and the register file (internal). The 144-byte random-access regIster file
is composed of 124 general-purpose regIsters,
four I/O port registers, and 16 control and
status regISters.
To unburden the program from coping WIth
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers WIth a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized
because one of the on-chip timers supplies the
bIt rate.
XTAL
GND
AS
MI'----!-!-\I~---'---,
UART
Uttt!!!
110
(BrT PROGRAMMABLE)
ADDRESS OR 110
(NIBBLE PROGRAMMABLE)
ADDRESSIDATA OR 1/0
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
Pin
Description
AS. Address Strobe (output, achve Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed m the high-impedance state along with
Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, achve Low). Data
Strobe IS achvated once for each external
memory transfer.
POo-po7. P1o-P17. P2o-P27. P30-P37' I/O Port
Lwes (mput/outputs, TTL-compatible). These
32 lines are dIvided mto four 8-blt I/O ports
330
that can be configured under program control
for I/O or external memory interface.
RESET. Reset (input, active Low). RESET initiahzes the Z8601. When RESET is deactivated,
program execution begins from internal program location OOOCH.
R/W. Read/Write (output). R/W is Low when
the Z8601 is wnting to external program or
data memory.
XTALI. XTAL2. Crystal], Crystal 2 (time-base
mput and output). These pins connect a seriesresonant crystal (8 MHz maximum) or an external single-phase clock (8 MHz maximum) to
the on-chIp clock oscillator and buffer.
2037·003
Address
Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 2048 bytes
consist of on-chip mask-programmed ROM. At
addresses 2048 and greater, the 28601
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The 28601 can address 62K
bytes of external data memory beginning at
locations 2048 (Figure 5). External data
memory may be mcluded WIth or separated
from the external program memory space.
OM, an optional I/O function that can be
programmed to appear on pm P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four 1/0 port registers (RO-R3), 124
general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure 6.
28601 instructions can access registers
6553Sr----------,
5535
EXTERNAL
ROM OR RAM
N
20"
2047
,llIfl1lSI
I...
ON·CHIP
ROM
Location 0I
hrstbytloI
Lnsln.lc!lon
.... cut.d
l'ci 0------------11
10
,
Inlarrup
;
V.elo
(Lower Byle
,
Interrup
Vector
(UpperSyl.J
IROS
IROS
•
IRQ4
8
IR04
7
IR03
•
IR03
5
IRQ2
410"
IRQ2
3
IROl
2
IRQ1
1
IROO
0
IROO
~g:; 1-----------.,
NOT ADDRESSABLE
IDENTIFIERS
255
STACK POINTER (BITS 7-0)
SPL
254
STACK POINTER (BITS 15-8)
SPH
253
REGISTER POINTER
RP
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REQUEST REGISTER
IRQ
24.
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
POtM
PORT 3 MODE
P3M
248
PORT 2 MODE
P2M
245
TO PRESCALER
244
TIMER/COUNTER 0
247
Figure 5. Data Memory Map
'--_-rll~_~~,:..·~,~·~,.:.·~,~,::i::...;;O:..:.O~O~;O:_=1_1:::
....- - - - - - - - -. . 240
Thaupparnibblaoitharegll'arillaaddrass
>--~rovldedbYlheregls'erpolnlarIlPeellies
thallcilveworklnglllgitiergroup
r----------.,127
PREO
TO
PRE1
243
T1 PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
SERIAL UO
SIO
240
~
w
I
Figure 4. Program Memory Map
LOCATION
-
EXTERNAL
DATA
MEMORY
T1
NOT
The lower
IMPLEMENTED
SPECIFIED WORKING·
REGISTER GROUP
127
ntbblaol
thereglstar
IIle.ddrns
-
provided by
Ihelnstrucllon
potnlsto Ihe
spaclfled
reglsler
GENERAL PURPOSE
REGISTERS
PORT 3
P3
PORT 2
P2
PORT 1
PI
PORT 0
PO
Figure 6. The Register File
2037·004.005,006.007
t - - - - - - - - - - - 1 '5
----"OPO'RiS-----
3
Figure 7. The Register Pointer
331
Address
Spaces
(Continued)
directly or indirectly with an 8-bit address
field. The 28601 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-RI27).
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second.
The Z8601 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity IS also available as an option. Eight
data bits are always transmitted, regardless of
parity selection. If parity is enabled, the eighth
bit is the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data m,ust have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error £lag. Received characters generate
the IRQ3 interrupt request.
Transmitted Data
Received Data
(No Parity)
(No Parity)
Ispispi D, ID.I D,I D.I D,I D,I D, ID,I sTI
T
I~I~I~I~I~I~I~I~I~IMI
I
LSTARTBIT
' - - - - - - - E I O H 1 DATA BITS
LSTART BIT
' - - - - - - E I O H T DATA BITS
' - - - - - - - - - - O N E STOP BIT
TWO STOP BITS
Transmitted Data
Received Data
(With Parity)
(With Parity)
1~lpl~I~I~I~I~I~I~IMI
1~1~lpl~I~I~I~I~I~I~lsij
T
I
I L_L~TARTBIT
LSTART BIT
L - - - - S E y E N DATA BITS
'------SEVEN DATA BITS
' - - - - - - - - - O O D PARITY
PARITY ERROR FLAG
' - - - - - - - - - - O N E STOP BIT
TWO STOP BITS
Figure 8. Serial Data Formals
Counter/
Timers
332
The Z8601 contains two 8-bit programmable
counter/timers (To and Tj), each driven by its
own 6-blt programmable prescaler. The Tj
prescaler can be dnven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-blt prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each pres caler drives its counter,
which decrements the value (1 to 256) that has
been loaded mto the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (TI)-IS
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reachmg zero (single-
pass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time Without
disturbing their value or count mode.
The clock source for TI is user-definable and
can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (l MHz maximum).
a trigger mput that can be retriggerable or
non-retnggerable, or as a gate input for the
internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of T I. Port 3 line P36 also
serves as a timer output (TOUT) through which
To, TI or the internal clock can be output.
2037-009
1/0 Ports
The 28601 has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to
provIde address outputs, timing, status signals,
serial 110, and parallel 110 with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 1 can be programmed as a byte 1/0
port or as an addressldata port for mterfacing
external memory. When used as an 1/0 port,
Port 1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY)
and DAV) (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the mulhplexed Address/Data mode. If
more than 256 external locations are required,
Port must output the additional lines.
Port 1 can be placed in the hIgh-impedance
state along with Port 0, AS, DS and R/W,
allowing the 28600 to share common resources
in multiprocessor and DMA applications. Data
transfers can be controlled by assIgning P33 as
a Bus Acknowledge mput and P34 as a Bus
Request output.
Port 0 can be programmed as a nibble 110
port, or as an address port for interfacing
external memory. When used as an 1/0 port,
Port may be placed under handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls DA Vo
and RDYo. Handshake signal assignment is
dictated by the 1/0 direction of the upper
nibble P04-P07.
For external memory references, Port can
provide address bits As-All (lower nibble) or
As-AJ5 (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port can be programmed independently as
1/0 while the lower nibble IS used for addressing. When Port nibbles are defined as
address bits, they can be set to the hlghimpedance state along WIth Port 1 and the control signals AS, DS and R/W.
PORT 1
(110 OR AD o-AD 7)
HANDSHAKE CONTROLS
} DAV1 AND RDY1
(P3 3 AND P34)
°
°
Figure 9a. Pori 1
°
°
°
Port 2 bits can be programmed independently as input or output. The port is
always available for 1/0 operations. In addition, Port 2 can be configured to provide
open-drain outputs.
LIke Ports and 1, Port 2 may also be
placed under handshake control. In thIs configuration, Port 3 lines P3) and P36 are used as
the handshake controls lines DA V2 and RDY 2.
The handshake signal assignment for Port 3
lines P3) and P36 is dICtated by the direction
(input or output) assigned to bIt 7 of Port 2.
__ }
Figure 9b. Pori 0
PORT 2{I/O)
°
Port 3 lines can be configured as 110 or control lines. In either case, the dIrection of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37). For serial 1/0, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt
request signals (IRQo-IRQ3); hmer input and
output signals (TIN and TOUT) and Data
Memory Select (DM).
2037·008
~~~~!~~KRED~~NTROLS
(P32 AND P3s)
HANDSHAKE CONTROLS
} DAV2 AND RDY2
(P3, AND P3 6)
Figure 9c. Pori 2
-..--
PORT 3
(110 OR CONTROl)
Figure 9d. Pori 3
333
Interrupts
The 28601 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counterl
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
All 28601 interrupts are vectored. When an
interrupt request is granted, an interrupt
machine cycle IS entered. This disables all
subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Clock
The on-chip oscillator has a high-gain,
series-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitors (C] = 15 pF) from each pin to
ground. The speCifications for the crystal are
as follows:
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input. This
necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. FIgure 10 shows
the recommended circuit for a battery back-up
supply system.
Power Down
Standby
Option
• AT cut, series resonant
• Fundamental type, 8 MHz maximum
• Series resistance, Rs :5 100 n
+5 V
0 - - - - -......--1
Z8601
J
Figure 10. Recommended Driver Circuit
for Power Down Operation
ZB602
This 64'pin development version of the
Development 40-pin mask· programmed 28601 (FIgure 11)
allows the user to prototype the system in hardDevice
ware with an actual device and to develop the
code that IS eventually mask· programmed into
the on·chip ROM of the 28601.
The 28602 is identical to the 28601 with the
follOWing exceplJons:
P3,
os
P3s
• The internal ROM has been removed.
po,
• The ROM address lines and data lines are
buffered and brought out to external pins.
• Control lines for the new memory have
been added.
Pin Description. The functions of the 28602
I/O lines, AS, DS, R/W, XTALl, XTAL2 and
RESET are identical to those of their 28601
counterparts. The functions of the remaining
24 pins are as follows:
Ao-All' Program Memory Address (outputs).
VDO
po,
po,
Z86Q2
pOs
SYNC
41
MDS
0,
Ao-A II access the first 2K bytes of program
memory. All is a reserved pin.
Figure 11. Z8602 Pin Assignments
334
2037·010,011
ZB602
00-07' Program Data (inputs). Program data
Development from the first 2K bytes of program memory is
Device
input through pins Do-D7.
(Continued)
lACK. Interrupt Acknowledge (output, active
High). lACK is driven High in response to an
interrupt during the interrupt machine cycle.
MOS. Program Memory Data Strobe (output,
active Low). MDS is Low during an instruction
fetch cycle when the first 2K bytes of program
memory are being accessed.
ZB603
Protopack
Emulator
The Z8603 MPE (Protopack) is used for
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROM less version of the standard Z8601,
housed in a pin-compatible 40-pin package
(Figure 12).
To provide pin compatibility and interchangeabIlity with the standard maskprogrammed device, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure I). The
24-pin socket is equipped with 12 ROM
SCLK. System Clock (output). SCLK is the
Internal clock output through a buffer. The
clock rate is equal to one-half the crystal
frequency.
SYNC. Instruction Sync (output, active Low).
This strobe output is forced Low during the
internal clock period preceding an opcode
fetch.
address lines, 8 ROM data lines and necessary
control lines for interface to 2716 EPROM for
the first 2K bytes of program memory.
Pin compatibility allows the user to design
the pc board for a final 40-pin maskprogrammed Z8601, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot produchon units. When the
final program is estabhshed, the user can then
switch over to the 40-pin mask-programmed
Z8601 for large volume produchon. The Protopack is also useful in small volume applications where masked ROM setup time, mask
charges, etc., are prohIbitive and program
flexibIlity is desired.
Compared to the convenhonal EPROM
versions of the Single-chip microcomputers,
the Protopack approach offers two main
advantages:
• Ease of developing various programs during
the prototyping stage. For instance, in
applications where the same hardware
configuration IS used with more than one
program, the Z8603 Protopack allows
economical program storage in separate
EPROMs (or PROMs)' whereas the use of
separate EPROM-based single-chip
mIcrocomputers is more costly .
Figure 12. The Z8603 Microcomputer Protopack Emulator
Instruction
Set
Notation
Addressing Modes. The followmg notation IS used
to describe the addressmg modes and instruction
operahons as shown m the mstruchon summary.
IRR
IndIrect regIster paIr or mdirect workmg-register
paIr address
Irr
X
IndIrect workmg-register paIr only
Indexed address
D Ireet address
RelatIve address
ImmedIate
DA
RA
1M
R
IR
2037-012
RegIster or workmg-regIster address
WorkIng-regIster address only
Ir
IndIrect-register or mdlrect workmg-register
address
IndIrect workmg-register address only
RR
RegIster paIr or workmg regIster paIr address
• Elimination of long lead time in procuring
EPROM-based microcomputers.
Symbols. The following symbols are used in
describing the mstruction set.
dst
src
cc
DestmatIon locatIon or contents
Source locatIon or contents
CondItIon code (see l,st)
@
IndIrect address prehx
SP
Stack pomter (control regIsters 254-255)
PC
Program counter
FLAGS Flag regISter (control regIster 252)
RP
RegIster pomter (control regIster 253)
IMR
Interrupt mask regIster (control regIster 251)
Assignment of a value IS indIcated by the symbol
n_". For example,
dst - dst + src
indICates that the source data IS added to the
destmahon data and the result IS stored m the
destmahon location. The notation naddr(n)" is used
to refer to b,t nn" of a gIven location. For example,
dst (7)
refers to b,t 7 of the destinahon operand.
335
Instruction
Set
Notation
(Continued)
Flags. Control Reglster R252 contains the following
SlX flags:
C
Z
S
V
D
H
Condition
Codes
Affected flags are Indicated by:
o
Value
Cleared to zero
Set to one
Set or cleared accordmg to operahon
Unaffected
Undefmed
I
'"
Carry flag
Zero flag
Slgn flag
Overflow flag
Declmal-adJust flag
Half-carry flag
X
Mnemonic
Flags Set
Meaning
Always true
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
C
NC
2
NZ
PL
I
C
C =a
2
1
a
2
S
a
S
1
V
1
V =a
2 = 1
2 = a
(S XOR V) = a
(S XOR V) = 1
[2 OR (S XOR V)j
[2 OR (S XOR V)j
C =a
C = I
(C = a AND 2 = 0)
(C OR 2) = 1
Carry
No carry
Zero
Not zero
Plus
MI
Mmus
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
UnsIgned greater than or equal
UnsIgned less than
Unslgned greater than
UnsIgned less than or equal
a
I
Never true
Instruction
Formats
OPC
CCF, 01, EI, IRET, NOP,
ReF, RET, SCf
d"
OPC
INC t
One-Byte Instructions
ope
MODE
,--,d'-'.""",,-,,,_--,
ClR, CPL, CA, DEC,
OR
11
1 1
01
dst/src
OPC
I ~~~~'~~~Rt~~~R,POP,
,----,d",",----,
OR
OR
d"
RRC, SRA, SWAP
I--"O:':PC'------11
OR
11
1 1 0
I
dsl
I
OPC
,,'
Ace, ADD, AND,
CP, OR, SBC, SUB,
'"
OR
OPC
OR
OR
d,'
reM, TM, XOR
ope
src/dst
dstlsrc
ope
src/dst
I dstlCCR~
ope
lC, LOE, LDEI,
LOC, L.OCI
11
1 1
01
MODE
dsllsrc
OPC
,
,
'"
I
Ace, ADD, AND, CP,
LD, OR, SSC, SUB,
TeM. TM, XOR
lD
, 1 0
1 1 0
d"
lD
ADDRESS
OR
dst lope
VALUE
d"
MODE
MODE
MODE
MODE
1 1 1 0
VALUE
SRP
dsl/src
1 1 1 0
JP, CALL (Indirect)
OPC
VALUE
ope
Ace, ADD, AND, CP,
LD, OR, SSC, SUB,
TeM, TM, XOR
MODE
11
1 1
01
lD
OPC
JP
DA,
DA,
LD
DJNZ, JR
OPC
DA,
DA,
Two-Byte Instructions
CAll
Three-Byte Instructions
Figure 13. Instruction Formats
336
2037-0l3
Instruction
Summary
Instruction
and Operation
Adclr Mode
, dst
src
Opcode Flags Allected
Byte
(Hex)
CZSVDH
• 0 •
ADC dst,sre
dst-dst+sre+C
(Note 1)
ADD dst,sre
(Note 1)
00
(Note I)
50
-
DA
SP-SP-2
IRR
@SP - PC; PC - dst
D6
D4
------
CCF
EF
* - - - - -
10
o•
CALL dst
.
• 0
BO
Bl
dst - NOT dst
R
IR
60
61
CP dst,sre
(Note 1)
COM dst
dst - DA dst
DEC dst
dst - dst - 1
DECW dst
dst - dst - I
0--
rA
r=O-F
R
IR
50
51
------
70
71
------
CF
o- - - - -
AF
------
90
91
. ·
R
IR
RET
.
PC - @SP; SP - SP + 2
RL dst
* • X
------
------
R
[2J~ IR
LEl=E:::ilJ
R
IR
10
11
RR dst
l[2Jlc:::3J~
EO
El
RRC dst
Liri=E3J
' , ,
R
IR
CO
Cl
(Note 1)
30
'
,
0
SBC dst,sre
dst - dst- sre - C
SCF
DF
rE
r=O-F
20
21
-
R
IR
RR
IR
AO
AI
-
*
.
·.
PC - dst
IRR
RA
true I
t:l
· .
• 1
1 - - -
IR
FO
Fl
X * * X - -
(Note 1)
60
-
TM dst, sre
dst AND sre
(Note 1)
70
-
XOR dst,sre
dst - dst XOR sre
(Note 1)
BO
SUB dst,sre
31
(Note 1)
dst - dst - sre
SWAP dst ~ R
* * - -
TCM dst,sre
(NOT dst) AND sre
BF
DA
--a:
. .
1m
cD
e=O-F
30
------
eB
e=O-F
------
• • 1
* • 0
.
• 0
* 0
Note 1
These Instructions have an Idenhcal set of addressmg
PC-PC+dst
Range: + 127, -128
modes, whlCh are encoded for brevity. The hrst opeode
r
R
1m
R
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
------
r
X
r
Ir
R
R
R
IR
IR
X
r
Ir
r
R
IR
1m
1m
R
r
Irr
Irr
C2
D2
------
Ir
dst - src
Irr
r - r + 1; rr - rr + 1
Irr
Ir
C3
D3
------
mbble
IS
found
In
the instructIon set table above. The
second mbble IS expressed symbollCally by a 0 In this
table, and ItS value IS found In the followmg table to the
left of the appheable addressIng mode pair.
For example, to determme the opeode of an ADC
Instruchon usmg the addressmg modes r (deshr:.ahon) and
Ir (source) IS 13.
Addr Mode
dst
src
R
R
R
IR
Ir
R
IR
1M
1M
...--
w
*
SRP sre
DO
Dl
~
0
20
l[2JPI~
00
N
RP - sre
- -
N
* - -
* * 0
SRA dst
------
*
.
C-l
IP ee,dst
If cc is true
0
C-O
-***--
RA
40
RCF
80
81
8F
(Note I)
SP - SP - 1; @SP- sre
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR (7) -1
8085,003
dst - @SP
SP - SP +
RR
IR
mET
LOCI dst,sre
FF
OR dst,sre
RLC dst
dst-dst+l
LDC dst,sre
dst - src
------
- * * *- -
INC dst
LD dst,sre
dst - sre
83
93
00
01
9F
If CC IS
Irr
Ir
PUSH sre
IMR (7) - 1
IR ee,dst
Ir
Irr
dst - sre
r - r + 1; rr-rr+l
LDEI dst,sre
R
IR
EI
dst - dst +
------
40
41
r - r- 1
If r '" 0
PC-PC+dst
Range: + 127, -128
INCW dst
82
92
R
IR
DI
IMR (7) - 0
DINZ r,dst
Irr
dst - dst OR sre
AO
dst - sre
DA dst
r
Irr
LDE dst,sre
POP dst
R
IR
dst - 0
src
NOP
C - NOT C
CLR dst
Opcode Flags Allected
Byte
(Hex)
CZSVDH
dst
dst - sre
dst - dst + sre
AND dst,sre
dst - dst AND sre
Addr Mode
Instruction
and Operation
Lower
Opcode Nibble
rn
rn
GJ
[]]
@]
[]
337
CI
Registers
R240 SIO
Serial I/O Register
(FOH; Reacl!Write)
R244 TO
Counter/Timer 0 Register
(F4H; ReacI!Wnte)
' - - - - - S E A I A L DATA (Do ::: lSB)
To INITIAL VALUE (WHEN WRITTEN)
' - - - - ( R A N G E 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
MODES
NOT To",
USED'"
00
i~ g~i
INTERNAL CLOCK OUT
:= ~~
R241 TMR
Timer Mode Register
(FI H; Reacl!Write)
R245 PREO
Prescaler 0 Register
(F5 H; Write Only)
~~o
~L
j
~
NO FUNCTION
1 =
'" LOAD
To
0 "" DISABLE To COUNT
1 ::: ENABLE To COUNT
11
=
(NON
o
To SINGLE PASS
1 = To MODULO N
RESERVED
0 = NO FUNCTION
'
lOAD T,
0 = DISABLE T 1 COUNT
T MODES
EXTERNAL CLOCK IN~DT
00
GATE INPUT = 01
COUNTMODE
=
=
A~~~~g~~~~~~~l :::
PRES CALER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)
1 ::: ENABLE Tl COUNT
10
TRIGGER INPUT::: 11
(RETRIGGERABLE)
R242 Tl
Counter Timer 1 Register
(F2H ; Reacl!Write)
R246 P2M
Port 2 Mode Register
(F6H; Write Only)
P2 0-P2 1 110 DEFINITION
' - - - - a DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
Tl INITIAL VALUE (WHEN WRITTEN)
' - - - - ( R A N G E 1-256 DECIMAL 01-00 HEX)
11 CURRENT VALUE (WHEN READ)
R247 P3M
Port 3 Mode Register
(F7H; Write Only)
R243 PREl
Prescaler 1 Register
(F3H; Write Only)
~L
~~
COUNTMODE
o ::: Tl SINGLE PASS
1 ::: T, MODULO·N
CLOCK SOURCE
1 ::: Tl INTERNAL
o = Tl EXTERNAL TIMING INPUT
(T,N) MODE
o1 PORT
2 PULL UPS OPEN DRAIN
PORT 2 PULL UPS ACTIVE
RESERVED
=
=
a P32
INPUT
P3S
OUTpUT
1 P32 = DAva/RDYO P3S = ROYO/DAVO
oa
P33
-=
INPUT
~6}P33
PRESCALER MODULO
(RANGE 1-64 DECIMAL
11
01-00 HEX)
= INPUT
P33 = DAVlIROY1
P34
= OUTPUT
P34 = OM
P34 = RDYlIDAVi
'-------~ ~~~ ~ 6N:V~R(6~~ ~i: ~ ~~~~~:V~UT)
'--------~ ~~~ ~ ~N:R~lL IN ~~i ~ ~~~rAULTOUT
'-________
~ ~:=:+~ g~F
Figure 14. Control Registers
338
2037-014
Registers
R252 FLAGS
Flag Register
R248 POIM
Port 0 and 1 Mode Register
(F8 H; Wnte Only)
(Continued)
...-J
po._po, MOOE:]
OUTPUT", 00
INPUT = 01
A 12 -A 15 = 1X
(FC H; ReacllWnte)
1
ll!~~
~-r
L pOo-po,= MOOE
00
OUTPUT
01 = INPUT
lX = As-A, I
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1
LUSERHAGF.
LUSER FLAG F2
STACK SELECTION
a EXTERNAL
1 = INTERNAL
=
HALF CARRY FLAG
OECIMAL AOJUST flAG
OVERFLOW FLAG
SIGN FLAG
Pl 0·P1, MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
ZERO FLAG
CARRY FLAG
10 '" ADo·AD,
11 = HIGH IMPEDANCE ADo-AD"
AS, OS, RIW, As-A", A12-A,S
IF SELECTED
R249IPR
Interrupt Priority Register
(F9 H; Wnte Only)
R253 RP
Register Pointer
(FDH; ReacllWrite)
1~1~I~i~I~I~I~I~1
I I III '"IT"""" ,~""o."
.." ..,,:J
RESERVED
C ;:> A > B
A > B ;:> C
A> C > B
B ;:> C ;:> A
c>B>A
B > A ;:> C
RESERVED
IR03, IROS PRIORITY (GROUP A)
a '" lAOS;:> IRQ3
1 = IRQ3 ;:> IROS
IROO, IRQ2 PRIORITY (GROUP B)
o = IR02 > IROO
1 = IROO > IRQ2
LOON'TeARE
= 000
'" 001
'" 010
= 011
REGISTER
POINTER
= 100
= 101
= 110
= 111
IRQ1, IRQ4 PRIORITY (GROUP C)
= IRQ1 > IRQ4
1 = IRQ4 > IRQl
a
R250 IRQ
Interrupt Request Register
R254 SPH
Stack Pointer
(FAH ; ReacllWnte)
(FEH; ReacllWnte)
10 , IDo I0, I0.1 0, I0, I0, IDo I
RESERVEOT
C='Rao
IRQ1
IRQ2
IRQ3
IR04
IROS
P32 INPUT (Do '" IROO)
P331NPUT
P3,INPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
T,
R251lMR
Interrupt Mask Register
R255 SPL
Stack Pointer
(FBH; ReacllWrite)
(FFH; ReacllWrlte)
I'
L
c=
1 ENABLES IROO-IROS
(Do '" IROO)
_ _ _ _ _ _ RESERVED
L - - - - -_ _ _ l
ENABLES INTERRUPTS
Figure 14. Control Registers
339
zaBOI
Lower Nibble (Hex)
Opcode
Map
o
o
5
e""
:
4
DEC
3
4
2
SCF
Rl
I--6,5
CCF
I--6,0
'V'
3
NOP
.I
"'---------~~~------------~ ~
2
~
3
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode-A
Nibble
Firsl
Operand
+
Pipeline
Cycles
Mnemonic
Second
Op~rand
Legend:
R = 8-Bll Address
r = 4·Blt Address
R 1 or r 1 = Dst Address
R2 or fZ = Src Address
Sequence:
Opcode, FIrst Operand, Second Operand
Nole: The blank areas are not dehned_
*2·byte lnstructlon, fetch cycle appears as a 3-byte mstruchon
340
8085-002
Absolute
Maximum
Ratings
Voltages on all pins
withrespecttoGND .......... -0.3Vto +7.0V
Operating Ambient
Temperature .................. 0 °e to + 70°C
Storage Temperature ........ -65°C to + 150 °e
Standard
Test
Conditions
Stresses greater than those lIsted under Absolute MaxI·
mum Rahngs may cause permanent damage to the device.
This 15 a stress rating only; operatIon of the device at any
conditIon above those indicated m the operational sectIons
of these speclhcatIons is not ImplIed. Exposure to absolute
maximum rating conditions for extended penods may affect
devIce relIabIlIty.
o
o
o
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
+5V
+4.75 V :5 VCC :5 +5.25 V
GND = 0 V
ooe :5 TA :5 +70 oe
+5V
+5V
21K
+5V
18K
15k
74lS04
CL~CK
15k
74lS04
--r>c>--.............-r>o--~-.-- XTAL2
I
Cl = 1SpF MAX
L _ _ _---<~_ XTAL1
r
Figure 15. Test Load I
DC
Characteristics
Figure 17. External Clock Interlace Circuit
Condition
Parameter
Min
Max
Unit
VCH
Clock Input HIgh Voltage
3.8
Vcc
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VlH
Input HIgh Voltage
2.0
Vcc
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input HIgh Voltage
3.8
VCC
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output HIgh Voltage
VOL
Output Low Voltage
IlL
Input Leakage
IOL
Output Leakage
1m
Symbol
V
IoH = -250 p.A
0.4
V
IOL
-10
10
p.A
o V:5
VIN s +5.25 V
-10
10
p.A
o Vs
VIN s +5.25 V
Reset Input Current
-50
p.A
Vcc
Icc
VCC Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
I
8085·0313,0312
Figure 16. Test Load 2
2.4
3
Vcc
For AO-All, MDS, SYNC, SCLK and lACK on the Z8612 VerSIOn, IOH
2037·015
V
~
CL = 15pF MAX
=
Notes
+2.0 rnA
=
+5.25 V, VRL
=0V
Power Down Mode
Power Down
-100
~A
and IOL
~
1.0
rnA.
341
External I/O
or Memory
Read and
Write Timing
Number
Symbol
Parameter
Min
Max
Unit
TdA(AS)
TdAS(A)
TdAS(DI)
Address Valid to Address Strobe Delay
50
Address Strobe to Address Float Delay
60
Address Strobe to Data In Valid Delay
320
3
TwAS
Address Strobe Width
80
4
5--TdA(DS)-Address Float to Data Strobe Delay--- 0 - - - - - 6a
TwDS
Data Strobe Width Read
250
TwDS
Data Strobe Width Write
160
6b
7
TdDS(DI)
Data Strobe to Data In Valid Delay
200
8
ThDS(DI)
Data In Hold Time
0
9
TdDS(A)
Data Strobe to Address Change Delay
80
lO--TdDS(AS)-Data Strobe to Address Strobe D e l a y - - 7 0 - - - - - 2
11
TdR(AS)
Read Valid to Address Strobe Delay
12
TdDS(R)
Data Strobe to Read Change Delay
13
TdDO(DS) Data Out Valid to Data Strobe Delay
14
TdDS(DO) Data Strobe to Data Out Change Delay
15--TdW(AS)-Wrlte Valid to Address Strobe Delay-16
TdDS(W)
Data Strobe to Write Change Delay
50
60
50
80
50 - - - - - 60
Notes
ns
1,2
1,2
ns
1,4
ns
1,2
ns
ns---l-1,3
ns
1,3
ns
1,4
ns
ns
1,2
ns
ns---l,2-1,2
ns
1,2
ns
1,2
ns
1,2
ns
ns---1,2-ns
1,2
NOTES:
1. Test Load 1.
2. Delay hmes gIven are for an 8 MHz crystal mput frequency. For
lower frequencIes, the change In clock perIod must be added to
4. Address Strobe and Data Strobe to Data In Valid delay hmes
represent memory system access hmes and are gIven for an 8
MHz crystal mput frequency. For lower frequencies; the change
the delay tIme.
3, Data Strobe Width
IS
In four clock periods must be added to TdAS(DI) and the
change In three clock perIods added to TdDS(DI).
All hrnmg references assume 2 a v for a logIC "I" and 0.8 V for
a lOgIC "0,"
given for an 8 MHz crystal mput fre-
quency. For lower frequenCies the change In three clock
perIods must be added to obtam the mInImUm Width. The Data
Strobe Width vanes according to the mstruchon bemg
executed.
PORT~
DM
PORT 1
=>=>-
A8~All OR A8~A15
I-
0
let
1--0--- I-®+-
Ao-AT
----(i)--
t
1-----0------
.
----G:®--
-
00-07 OUT
DO-OliN
(5)-11-
..--!--(i)-
"\
\
.
.i
}
OUT
01-
c=
c=
~~
~----------.,;k=
~
342
CD
------- IRa3
1 = IRa3 > lAOS
I I III '""""""
~DON'TCARE
RESERVED = 000
C > A >
A :> B >
A > C >
B0000,""",""
= 001
C = 010
B = all
B > C > A =
c> B>A =
B > A > C =
RESERVED",
IROO, lR02 PRIORITY (GROUP B)
o = IAQ2 > IROO
1 = IROO > IRQ2
REGISTER
POINTER
100
101
110
111
IRQ1, IRQ4 PRIORITY (GROUP C)
o = IRO' > IR04
1 ::: IR04 > lAOl
R2S0 IRQ
Interrupt Request Register
R254 SPH
Stack Pointer
(FAH; Read/Wrlte)
(FE H; Read/Wnte)
I~I~I~I~I~I~I~I~I
RESERVEO~
L:='RQO
IR01
IRQ2
lA03
IR04
IROS
=
P32 INPUT (Do
IROO)
P331NPUT
P311NPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
T,
R255 SPL
Stack Pointer
R251IMR
Interrupt Mask Register
(FFH; Read/Wrlte)
(FBH; Read/Write)
Il____
I~I~I~I~I~I~I~I~I
L
__
:=
_ ' ENABLES IROO-IROS
(00:= IROO)
L I_ _ _ _
~~*~~s~~~~~~R
lOWER
RESERVED
'---------1
ENABLES INTERRUPTS
Figure 14. Control Registers
357
Opcode
Lower Nibble (Hex)
Map
o
o
2
3
4
5
".
6
~
.
:il
:9
z
I»
'"'"
3
8
::>
9
A
C
0
E
F
9
A
B
C
o
E
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
ADD
ADD
ADD
ADD
ADD
ADD
LD
LD
DINZ
IR
LD
IP
INC
n,R2
f2, HI
q,HA
cc,RA
cc,DA
Ii
HI
JRI
fl, f2
rI,lr.:z
H.,HI
IR2,Rl
HI,IM
JRI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
IHI,!M
HI
!HI
ll, !2
fl,Il2
H.,HI
!H.,HI
HI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
fl,
Ir.:z
!HI,IM
HI
JRI
fl, l2
H.,HI
IH., HI
HI,IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
lP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
JRHI
1M
fl, [2
fl, III
RllBI
IR., HI
HI,IM
IHI,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
HI
JRI
fl, [2
n,Ir2
H.,HI
JR.,HI
HI,IM
IHI,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
HI
JRI
f1, l2
fl,
Ir2
fi.:z,Hl
JR.,HI
HI,IM
IHI,IM
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
HI
JRI
fl, [2
II,Il2
R2,Rl
IR.,HI
HI,IM
IHI,IM
6,5
6,5
10,5
10,5
10,5
10,5
PUSH PUSH
H.
JR.
10,5
10,5
DECW DECW
6,5
TM
TM
TM
TM
TM
TM
fl, [2
ll,Il.:z
H.,HI
JR.,HI
HI,IM
IHI,IM
12, a
18,0
LDE
LDEI
HHI
!HI
r 1, Irr2
Irl,Irr.:z
6,5
6,5
12,0
18,0
RL
RL
LDE
LDEI
RI
JRI
f2, lUI
112, Irr 1
10,5
10,5
6,5
6,5
INCW INCW
JRI
CP
ll, l2
CP
ll,
Ir2
[1,
1M
F
r--r--r--
r--r-r-r--
r--6, I
DI
r-6, I
EI
10,5
10,5
10,5
10,5
r--RET
CP
CP
CP
CP
H.,HI
IH.,HI
HI,IM
IHI,IM
14,0
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
r---
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
HI
JRI
ll,12
fl,If2
H.,HI
!H., HI
HI,IM
!HI,IM
IRET
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LDC
LOCI
LD
HI
IHI
r 1, Irr2
Ill,Iru
ll,
16, a
r--6,5
RCF
x, R2
f---
6,5
6,5
12,0
18,0
SRA
SRA
LDC
LOCI CALL"
HI
!HI
f2, Irrl
6,5
6,5
6,5
10,5
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
HI
JRI
II,Il2
H.,HI
JR.,HI
HI,IM
JRI,iM
6,7
6,7
6,5
10,5
r---
LD
LD
NOP
SWAP SWAP
,
Instruction
8
DEC
HI
Bytes per
7
6,5
HHI
B
6
DEC
10/12,1 12/14,1
7
5
IHI
Ir.:z,
Irll
Ill,12
'V'
2
"
20,0
10,5
CALL
LD
20,0
IHHI
,
DA
f2,
6,5
SCF
r--
x, HI
10,5
6,5
CCF
6,0
H.,IHI
'V'
.I
,
~
________
~~~
__________,J
~
~
2
Lower
Opcode
Nibble
Execution
Cycles
t
Pipeline
Cycles
Legend:
H
Upper
Opcode-A
Nibble
First
Operand
Mnemonic
Second
Operand
= 8-Blt Address
=
4-Blt Address
Ti = Dst Address
R2 or 12 = Src Address
r
RI or
Sequence:
Opcode, FIrst Operand, Second Operand
Note: The blank areas are not defmed_
*2-byte InstructIon; fetch cycle appears as a 3-byte mstructlon
358
8085-002
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature .................. 00eto +70 oe
Stresses greater than those listed under Absolute MaxI'
mum RatIngs may cause permanent damage to the devIce.
This IS a stress rating only; operatIon of the deVIce at any
conditIon above those mdlcated m the operational sections
of these specIfications IS not ImplIed. Exposure to absolute
maXImum rating condItions for extended penods may affect
devlCe rehabihty.
Storage Temperature ........ -65°C to + l500e
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flo>'ls into the reference
pin. Standard conditions are as follows:
o
o
o
+4.75 V
Vee
$
$
oce
TA
$
+70°C
$
+5V
+5V
+5V
+5.25 V
GND = 0 V
+5V
16K
2.1K
15k
74LS04
1.Sk
74LS04
J
CL = 150F MAX
'----~~- XTAL1
r
CL :: 15pF MAX
Figure 15. Test Load I
DC
Characteristics
Figure 17. External Clock Interface Circuit
Parameter
Min
Max
Unit
VeH
Clock Input HIgh Voltage
3.8
Vec
V
Dflven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input H,gh Voltage
2.0
Vce
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input H,gh Voltage
3.8
Vcc
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output HIgh Voltage
VOL
Output Low Voltage
IlL
Input Leakage
IOL
Output Leakage
1m
Symbol
Condition
V
IOH
= -250 p,A
0.4
V
IoL
=
-10
10
p,A
o Vs
VIN s +5.25 V
-10
10
p,A
o Vs
VIN s +5.25 V
Reset Input Current
-50
p,A
Vcc
lee
Vee Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
1. For
8085·0313.0304
Figure 16. Test Load 2
2037·015
2.4
AO-All. MDS. SYNC. SCLK and lACK on the
3
V
Vcc
Z8612 verSion.
IOH
~
Notes
+2.0 rnA
=
+5.25 V, VRL
=0V
Power Down Mode
Power Down
-100
~A
and
IOL
~
10
mA
359
External 1/0
or Memory
Read and
Write Timing
Number
Symbol
TdA(AS)
1
TdAS(A)
2
TdAS(Dl)
3
4
TwAS
5 - - TdA(DS) 6a
TwDS
6b
TwDS
TdDS(DI)
7
ThDS(DI)
8
Parameter
Min
Address Valid to Address Strobe Delay
Address Strobe to Address Float Delay
Address Strobe to Data In Valid Delay
50
60
Unit
Max
ns
ns
ns
ns
ns---
320
Address Str~be Width
80
Address Float to Data Strobe Delay - - - 0
250
Data Strobe Width Read
Data Strobe Width Write
160
Data Strobe to Data In Vahd Delay
Data In Hold Time
0
9 - - TdDS(A) - Data Strobe to Address Change Delay 80
10
TdDS(AS)
Data Strobe to Address Strobe Delay
70
TdR(AS)
II
Read Vahd to Address Strobe Delay
50
12
TdDS(R)
Data Strobe to Read Change Delay
60
13
TdDO(DS) Data Out Valid to Data Strobe Delay
50
14 - - TdDS(DO) - Data Strobe to Data Out Change Delay - 80
TdW(AS)
15
Write Valid to Address Strobe Delay
50
TdDS(W)
16
Data Strobe to Write Change Delay
60
Notes
1,2
1,2
1,4
1,2
1 -1,3
1,3
1,4
ns
ns
ns
ns
ns---l,2-1,2
ns
1,2
ns
1,2
ns
200
1,2
ns
ns---l,2-ns
ns
1,2
1,2
NOTES.
1 Test Load l.
4. Address Strobe and Data Strobe to Data In Valid delay hmes
represent memory system access tImes and are gIVen for an 8
MHz crystal mput frequency. For lower frequencies; the change
In four clock periods must be added to TdAS(DI) and the
change m three clock periods added to TdDS(DI)
5. All hmmg references assume 2.0 V for a logiC "I" and 0.8 V for
a logiC "0."
2. Delay hmes given are for an 8 MHz crystal mput frequency. For
lower frequencIes, the change In clock perIOd must be added to
the delay hme.
3 Data Strobe Width IS given for an 8 MHz crystal mput frequency, For lower frequencies the change
In
three clock
perlOds must be added to obtain the mmanum WIdth The Data
Strobe WIdth vanes accordmg to the mstructIon bemg
executed.
PORT~
DM
PORT 1
~
~
As-A" OR As-A,s
I•
CD
A,-A,
--0---
){
1---0---
.
~
-
Do-OriN
0,-0, OUT
I~
ll'
1------0----
OUT
~
CD-+- 1-----:---0----"\
~
}
CD I-
K=
K=
\
I
II
CD
II
~
R/W
360
2037-016
Additional
Timing
Table
Number
Parameter
Symbol
I
TpC
Input Clock Period
2
TrC, TIC
Input Clock Rise and
Fall Times
Min
Max
Unit
125
1000
ns
25
ns
Notes
3
3
37
ns
TwC
Input Clock Width
3
4 - - TdSC(AS)- System Clock Out to Address - - - - - - - - - - - - n s - - - I - - Strobe Delay Time
5
TdSY(DS)
Instruction Sync Out to Data
Strobe Delay Time
200
ns
l.2
6
TwSY
Instruchon Sync Out Width
160
ns
I, 2
TwI
Interrupt Request via
Port 3 Input Width
100
ns
7
NOTES:
1. Test ConditIons use Test Load 1 for SCLK when output through
3. From external clock generator
the Port 3 pms and Test Load 2 on the SCLK and SYNC direct
outputs on 28612.
2. Times given assume an 8 MHz crystalmput frequency. For
lower frequencies, the change In two clock penods must be
added.
4. All hmmg references assume 2.0 V for a logIC "1" and 0.8 V for
a logiC "0."
CLOCK
\----I
I
DATA IN
....---.. SAMPLED
READ CYCLE
'----------'1."
IRQ n
2037-017
t----0----r _~<'."'''o'''
_~~.~0~~-f~------------_
~
361
Handshake
Timing
'---
Number
Symbol
Parameter
Min
Max
Unit
I
TsDI(DA)
Data In Setup Time
0
ns
2
ThDA(DI)
Data In Hold Time
230
ns
3
TwDA
Data Available Width
175
4a
4b
TdDAL(RY) Data Avallable Low to Ready
Delay TIme
20
0
5a
5b
TdDAH(RY) Data Avallable HIgh to Ready
Delay Time
6
TdDO(DA)
Data Out to Data AVailable
Delay Time
7
TdRY(DA)
Ready to Data Available Delay TIme
ns
Notes
1,2
175
1,2
ns
ns---l,3--
150
0
ns
ns
50
ns
0
205
1,2
1,3
ns
NOTES;
1. Test Load 1
2. Input Handshake
3. Output Handshake
.xt
DATA IN
DATA IN VALID
I~I -----
P,
r
~
ADo-AD7
~
<8>
Aa-A1S
P,
15110
LINES
(
64'
PROGRAM
MEMORY
<8>
Z8681
PORT 3
64.
DATA
MEMORY
Y
<3>
~
PORT 3
~
<4->
P,
OM
Y
Figure 3. Z8G8l Interfacing to Memory-Mapped I/O
366
2040-003
ZSSSI
Applications
(Continued)
Z·BUS
Z BUS COMPATIBLE
PERIPHERAL CHIP
lUPC
l·CIO
FlO
A.
j..
'f
y
PRINTER
P,
P2. P3
A
ADo-AD7
~
,
P,
lSCC
CRT
OMA
Aa- A1s
r
-
za881
INT REQ
P,
OM
P,
p,lP,r-
64K
DATA
MEMORY
.'K
PROGRAM
MEMORY
RS232
DRIVER
AND
~
SERIAL OUT
Figure 4. ZSBSI Interfacing to External Memory
Ordering
Information
Product
Number
Packagel
Temp
Speed
Product
Number
Packagel
Temp
Speed
Description
28681
CE
8.0 MHz
28MCU
(ROMless, 40-pm)
28681
DS
8.0 MHz
28MCU
(ROMless, 40-pm)
28681
CS
DE
8.0 MHz
8.0 MHz
Same as above
Same as above
28681
28681
PE
PS
8.0 MHz
8.0 MHz
Same as above
Same as above
28681
NOTES C = Ceramic, D
2040·004 00-2040-A
Description
= Cercilp, P
= Plastic, E
=
_40°C to + 85°C, S =
aoc to
+ 70°C
I...
3
MelDory
il
Z6132 4Kx 8
Quasi-Static RAM
~
Zilog
Product
Specification
March 1981
Description
Features
The Zllog Z6132 is a +5 V mtelligent MOS
dynamIc RAM organized as 4096 words by
eight bits. Although it uses single-transistor
dynamic storage cells, the Z6132 effechvely
funchons as a static RAM because It performs
and controls its own refresh. ThIs eliminates
the need for external refresh cIrcuitry and
combines the convemence of a static RAM with
the high density and low power consumption
normally assocIated WIth a dynamic RAM.
The Z6132 is parhcularly suited for
mICroprocessor and minicomputer applications
where its byte-wide organization, transparent
self-refresh and smgle supply voltage reduce
the parts count and simplify the design.
The Z6132 uses high-performance depletionload double-poly n-channel SIll con-gate MOS
technology with a mixture of static and
dynamic cirCUItry that provides a small
memory cell, fast access and low power consumptIOn. The Z6132 has separate pms for
addresses and bidirechonal data I/O to provide maximum flexibility in ItS appllcation.
The CIrcUIt is packaged m an industrystandard 28-pin DIP and pin compatible with
the proposed JEDEC standard.
The Z6132 conforms with the Z-Bus specificahon used by the new generahon of Zilog
microprocessors, the ZS and Z8000.
• Byte-wide orgamzation: 4096 words by eIght
bits
• Low power consumphon: 250 mW active,
125 mW stand-by.
• Access and cycle times guaranteed over
voltage and temperature range:
• Industry-standard 2S-pin DIP with JEDECrecommended pinout
Part Number
Z6132·3
Z6132·4
Z6132·5
Z6132·6
Cycle Time
350 ns
375 ns
425 ns
450 ns
Access Time
200 ns
250 ns
300 ns
350 ns
• Automatic self-refresh scheme with slow-and
fast-cycle modes.
• On-chip substrate bias generator.
• Interfaces readily to Z8 and Z8000.
• All inputs and outputs are TTL compatible
Pin Names
BUSY
V"
A,
AC
A,
AB
A,
A,
A.
A"
A3
2B
os
A,
A"
A,
OS
..
0,
14
.5V
WE
0,
AO·All Address mputs
Data Inputs/Outputs (3'state)
Do·D 7
AC
Address Clock Input (nslng edge)
DS
Data Strobe Input (aclive Low)
WE
Wnte Enable Input (active Low)
Chip Select mput (aclive Low)
CS
BUSY
Busy output
0,
DB
0,
0,
D.
GND
0,
(actIve Low; open dram)
VBB
Vee
VSS
and Refresh Mode Control mput
Negalive Substrate Bias output
+ 5 V supply conneclion
o v :;: : Ground connectIon
11 12 13 1S 16 17 18 19
Figure 1. Logic Symbol
2028·0146, 0147
Figure 2. Pin Assignments
371
...
=
W
N
Functional
Description
The 26132 4K x 8 quasi-static RAM is organized as two separate blocks, each having two
sets of 64 rows on either side of the 128 sense
amplifiers (Figure 3). Both blocks have
separate and independent row address buffers
and decoders, but they share the column
decoder and the internal 8-bit wide data path.
The two sets of row address decoders are addressed either by the address inputs AI-A7 or
by the internal 7-bit refresh counter. The least
significant address input (AO) selects one of the
two blocks for external access. While the
selected block performs a read or write operation, the other memory block uses the refresh
counter address to refresh one row. Details of
the self-refresh mechanism are explained later.
A memory cycle starts when the rising edge
of Address Clock (AC) clocks in Chip Select
(CS), Ao, and Write Enable (WE). If the chip
is not selected (CS = High), all other inputs
are ignored for the rest of the cycle (that is,
until the next rising edge of AC). Both memory
blocks are self refreshed by the 7-bit refresh
counter. If the chip is selected (CS = Low),
the 12 address bits and the Write Enable bit
are clocked into their registers. Ao determines
which block is addressed by AI-All; the other
block is refreshed by the 7-bit refresh counter.
The Chip Select and Address inputs must be
valid only during a short hold time after the
rlsmg edge of AC. This allows address/data
multiplexing, because data I/O is controlled by
a separate control input Data Strobe (DS).
Read Cycle
A read cycle is initiated by the rising edge of
Address Clock (AC) while Chip Select (CS) is
Low and Write Enable (WE) High. A Low level
on the Data Strobe (DS) input activates the
Data outputs after a specified delay from the
riSing edge of AC as well as the falling edge of
DS, whichever comes later. During a read
operation, DS is nothing but a static Output
Enable signal.
Write Cycle
A write cycle is initiated by the riSing edge
of Address Clock (AC) while Chip Select
(CS) is Low and Write Enable (WE) is Low.
The WE input is checked again at the beginning (falling edge) of Data Strobe (DS).
If WE is still Low, this falling edge of DS edgetriggers the data on the Do-D7 inputs into the
addressed memory location. Data must be
valid only during a short hold time after the
falling edge of DS.
Write Inhibit
Cycle
After a write cycle has been initiated, the
actual write operation can still be aborted by
pulling WE High again before the falling edge
of DS. This write inhIbit cycle is a special
feature that permits starting a write cycle early
at AC time, but still allows the option of inhibiting the write operation later at DS time.
Note: Whenever a write cycle has been initiated, it must be accompanied by a High-toLow transition on the Data Strobe input.
Maximum
Cycle Time
The maximum read or write cycle time reqUIrements (15,000 and 800 ns) do not apply to
any individual cycle. They are specified to
guarantee a complete refresh in a 2 ms period.
REFRESH
ADDRESS
COUNTER
MUX
INPUT
ADDRESS
BUFFERS
ROW
DECODER
(1 OF 128)
MUX
INPUT
ADDRESS
ROW
DECODER
(1 OF 126)
MEMORY ARRAY
CLOCK
GENERATOR
BUFFERS
128 SENSE AMPLIFIERS
MEMORY ARRAY
Figure 3. Z6132 Block Diagram
372
2028·0148
Self-Refresh
Operation
The Z6132 stores data in single-transistor
dynamic cells that must be refreshed at least
every 2 ms. Each of the two memory blocks
contains 16,384 cells and requires 128 refresh
cycles to completely refresh the array.
The Z6132 operates m one of two user-
selectable self-refresh modes, each satisfying
the refresh time reqUirements. On the basis of
the available memory cycle time, the user can
decide to use eIther the Long Cycle-Time
Refresh Mode or the Short Cycle-Time Refresh
Mode.
Long CycleThis is the simplest self-refresh mode, and is
Time Refresh selected by permanently grounding the BUSY
Mode
output pin. Every memory cycle in this mode
consists of a memory operation followed by a
refresh operation on both blocks, after which
the refresh counter is incremented. Internally,
the complete cycle consists of a 4-phase sequence: I. Memory read, write, or write inhibit. 2. Precharge. 3. Refresh. 4. Precharge.
These mternal operations are automatic and
transparent to the user. When the chip is not
selected (CS = High when AC goes High), the
first two phases are omitted.
There are two important requirements: the
memory cycle time must always be longer than
the TC (Min) value specified for BUSY = Low
and there must be at least 128 Address Clocks
in any 2 ms period.
The Long Cycle-Time Refresh mode is the
one most practical for microprocessor applications, where the cycle time usually exceeds
700 ns.
ThIs IS a more sophlshcated self-refresh
Short CycleTime Refresh mode that allows operation at any cycle time
down to the specified minimum value.
Mode
The user selects this mode by pulling the
BUSY output pin High through a pull-up
resistor (typically I kfl) to Vcc. The BUSYoutputs of several Z6132 chips can be or-tied
together.
In thIs mode, the Z6132 always performs a
refresh operation on the memory block that is
not being addressed from the outside. The
refresh counter is mcremented whenever it IS
meanmgful. as explained in the following text.
tage of the inherent sequential nature of most
memory addressing.
Deselect Self-Refresh. If the chip is deselected
(CS = High when AC goes High), both blocks
are refreshed and the refresh counter is incremented after every cycle.
Odd/Even Self-Refresh. If the chip is selected
(CS = Low when AC goes High), the refresh
counter refreshes the block that is not addressed by Ao. The refresh counter is mcremented
after an even and an odd address have occured. ThIs self-refresh scheme takes advanExternal logIC can be used to select between
Mixed Cycle
Time Refresh Long and Short Cycle Time Refresh modes by
controlhng the BUSY pm as an input. The TimMode
mg DIagram (parameters 25 through 27) shows
when the mternal logic interrogates the BUSY
input.
When BUSY IS Low the cycle must be long,
both blocks are refreshed and the refresh
counter is incremented every cycle.
When BUSY is High, the cycle can be short
and the refresh operation is performed as
described under Short Cycle Time Refresh
Mode.
The external logic must guarantee proper
refresh timing. If the Z6132 received a sequence of 17 consecuhve all odd or all even
addresses while it was conhnuously selected
and BUSY was held High, the BUSY output will
go Low as described before.
A current hmitmg resIstor of - Ikfl should
2028-0150
Cycle-Count Self-Refresh. Normally the
deselect and odd/even self-refresh schemes
step through 128 refresh addresses in less than
2 ms. To guarantee proper refresh operation
even in the exceptional case when the memory
is continually selected and addressed by a
long string of all even or all odd addresses, a
built-in cycle counter activates the BUSYoutput and requests one longer memory cycle to
append a refresh operation. This internal cycle
counter is reset whenever the refresh counter
is mcremented. The cycle counter then counts
memory cycles and activates the BUSY output
when it reaches a count of 17.
BUSY is fed into the WAIT input of most
microprocessors. BUSY is a request to the CPU
for a longer memory cycle and is kept Low
until the refresh cycle has started. BUSY only
becomes active when the Z6132 has been
selected and addressed with all odd or all even
addresses for 17 consecutive Address Strobes.
be inserted if the BUSY pin is driven by TTL
logic.
External logic, as shown in FIgure 4 can
detect the fact that the memory requires a long
cycle hme and can pull the CPU WAIT input
Low.
Note that the cycle time in most microprocessor applications is so long that the simple
Long Cycle Time Refresh Mode is sufficient.
1k
REFRESH
MODE -~~Nv--,----I BUSY
CONTROL
Z6132
WAIT-------~
Figure 4. External WAIT Generation
373
N
...enw
N
AC
Electrical
Characteristics
~------------------~~
·AC ~~--........,
-0--------
~----_r-----J'
________2______~5)_--:__--t==~
1-
1--------~0~---------,1
..I
~~~-I~~.~==~-+~==
cs=t~xW~1
r=tt---:======+==+====
AO-Al1==t==x:~n=~X=~=-______I_I_==
. 0-1-
WRITE {
-l-®
t--~'--t----,.V__.fi
WE _ _
INHIBITL_~==+===~~_~
___+;::--__==:;-__________________
1\.L_ _ _ _ _ _ _ _ __
~
1------~N~----41_-----------------------------'\.~__l_--+__=__~J
BUSV{ OUTIN=====+==--~
___J:f-®-~21t=~",,=--®---=25=:r-~--=======
____
374
2028·0149
Z6132-3 7
No.
Symbol
Parameter
TC
Read or Wnte Cycle Time
Min
(ns)
Max
(ns)
Z6132-4
Min
(ns)
Max
(ns)
Z6132-5
Min
(ns)
Max
(ns)
Z6132-6
Min
(ns)
Max
(ns)
Notes
650 15000
725 15000
700 15000
750 15000
1
350
800
375
800
800
450 800
425
2
AC Width (H,gh)
TwACh
480
2
510
550
610
1
230
260
280
310
2
3
TwACI
AC Wldth (Low)
40
50
60
60
4
TdAC(DS) AC 1 to DS I
10
10
10
10
5-TdDS(AC)-DS ItaAC 1 - - - - - - 5 5 0 - - - - 580
1-610
640
250
275
310
340
2
6
TwDS
DS W,dth (Low)
120
140
160
180
7
TsCS(AC) CS Setup T,me to AC 1
0
0
0
0
8
ThCS(AS) CS Hold T,me to AC 1
40
45
50
55
9
TsA(AC)
Address Setup T,me to AC 1
0
0
0
0
lO-ThA(AC)- Address Hold T,me to AC 1 - - 4 0 - - - - -45
50
55
11
TsW(AC)
WE Setup T,me to AC 1
-10
-20
-25
-15
12
ThW(AC)
WE Hold Time to AC 1
60
70
80
80
13
TdAC(DO) AC 1 to Data Out
200
250
300
350
3
14
TdDS(DO) DS I to Data Out
70
80
90
100
3
15-TdDS(DOz)- DS 1 to Data Out Float
30--70--35--80--40--90--45-100--4-16
TdAC(DOz) AC I to Data Out Float
30
70
35
80
40
90
45
100
4
17
ThW(DS)
WE Hold Time to DS 1
60
70
80
90
3
18
TsW(AC)
WE Hold T,me to AC 1
120
130
140
150
3
19
TsDI(DS)
Data In Setup T,me to DS 1
0
0
0
0
20- ThDl(AC)- Data In Hold T,me to DS 1 - - - 45
50
60
70 - - - - 3 - 21
ThDI(AC)
Data In Hold Time to AC 1
120
130
140
150
3
22
TsWh(DS) WE H,gh Setup Time to DS I
10
10
10
10
23
TdAC(Bl)
AC I to BUSY Out I
80
90
100
110
24
TdAC(Bh) AC 1 to BUSY Out 1
400
450
500
550
5
90
100
80
110
6
3-25- ThB(DS)- BUSY In Hold Time to DS 1 - - 7 0 - - - - 80
90
100
26
ThB(AC)
BUSY In Hold Time to AC 1
150
160
170
180
3
27
TsB(AC)
BUSY In Setup T,me to AC 1
-40
-50
-60
-70
NOTES·
1 BUSY ~ Low.
2 BUSY ~ High
3 WhIchever IS later.
Whlchever
IS
earher
Selected.
Deselected
Available second half of 1981.
375
N
~
W
N
Substrate Bias The 26132 contains an on-chip negative
substrate-bias generator, which is a simple dcGenerator
to-dc converter that generates a substrate-bias
voltage of -2.5 to -3 V. This reduces parasitic
junction capacitances and thus increases circuit speed. The substrate bias output VBB
should be decoupled externally with an
==0.1 p.F ceramic capacitor to Vss (ground).
Power-Up
After applying Vee, it is necessary to wait
20 ms to charge the substrate bias decoupling
capacitor. Moreover, the 6132 requires sixteen
selected or deselected memory cycles before
proper operation is attained.
Absolute
Maximum
Ratings
Voltages on all pins (except VBB)
with respect to GND .......... -0.5 V to +7.0 V
Operating Ambient
Temperature .................. 0 °C to + 70°C
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the refer-ence
pin. Standard conditions are as follows:
DC
Electrical
Characteristics
Symbol
Min
ThIS is a stress rahng only; operation of the device at any
condition above those mdicated in the operational sections
of these speCIfIcations is not implied. Exposure to absolute
maximum rahng condihons for extended periods may affect
deVIce reliabihty.
• +4.75 V :$ Vee :$ +5.25 V
• VSS = GND = 0 V
• O°C :$ TA :$ +70°C
Max
Unit
Condition
VIH
Input High Voltage
2.2
7.0
V
VIL
Input Low Voltage
-0.5
0.8
V
VOH
Output High Voltage
V
IOH = 250 pA (except BUSY)
0.4
V
IOL
+3.5 rnA for
0.4
V
IOL
+ 5 rnA for BUSY
VOL
Capacitance
Parameter
Stresses greater than those listed under Absolute MaXI·
mum Ratings may cause permanent damage to the device.
2.4
Do-~
Output Low Voltage
IlL
Input Leakage
±IO
/-=-t-;;;,:=--t-;;;,:=--tt;:.:;=-1>I
74800
iii
--.,----==:L,r-------- ....
....-.r --t-----=:J")':4S::"_______
AC
T4L813B
~_------Cs
~:~:::::::::::::::::::::::::::::::::::::::jU
Figure 7. Z-SO Connection Diagram
The Z6132 interfaces directly with the single
chip Z8 microcomputer. Port 1 provides the
8-bit multiplexed Address/Data bus, and the
more significant address bits are prOVided by
Port O.
Figure S. ZS Connection Diagram
Ordering
Information
Product
Number
Speed
Description
26132·34096x8-Bit
QuasI-Static RAM
26132-44096x8-Bit
QuasI-Static RAM
26132·3
CS,PS,DS
200 ns
26132-4
CS,PS,DS
250 ns
NOTES C
378
Package/
Temp
CeramiC, D
Cerdlp, P
Plastic; S
Product
Number
Package/
Temp
Speed
Description
26132-5
CS,PS,DS
300 ns
26132-6
CS,PS,DS
350 ns
26132·5 4096x8·Bit
Quasi-Stalic RAM
26132-6 4096x8-Blt
Quasi-Static RAM
O·C to +70·C.
2028-0153, 0281
00-2028-A
Additional Information
~ilog
Z·BUSTM
Component Interconnect
~
Zilog
Summary
March 1981
Features
General
Description
• Mulllplexed address/data bus shared by
memory and I/O transfers.
• Direct addressmg of registers wlthm a
penpheral faclhtates I/O programmmg.
• 16 or more memory address bits; 16-blt I/O
addresses; 8 or 16 data bits.
• Bus signals allow asynchronous CPU and
penpheral clocks.
• Supports pollmg and vectored or nonvectored mterrupts.
• Daisy-cham bus-request structure supports
dlstnbuted control of the bus.
• Daisy-cham mterrupt structure services
mterrupts without a separate prlOrity
controller.
• Shared resources can be managed by a
general- purpose, dlstnbu ted resourcerequest mechamsm.
The Z-BUS is a high-speed parallel shared
bus that links components of the Z8000 Family.
It provides family members With a common
commumcatlOn mterface that supports the
following kinds of interactions:
------PRIMARy SIGNALS------
£XTENOED ADDRESS
• Data Transfer. Data can be moved between
bus controllers (such as a CPU) and memones or peripherals.
• interl'Upts. Interrupts can be generated by
STATUS>
BUS
MASTER
- - AS----+-
PERIPHERAL
--5&---..
AND MEMORY
--R/W----+-
penpherals and serviCed by CPUs over
the bus.
- - 8 M ------.
~WAIT-
_ _ RESET--+-
• Resource Control. Distributed management
of shared resources (mcluding the bus itself)
is supported by a daisy-cham priority
mechamsm.
The heart of the Z-BUS is a set of mulllplexed address/data lines and the signals that
control these lines. Multiplexing data and
addresses onto the same lines makes more efficient use of pins and facihtates expansion of
the number of data and address bits. Multiplexing also allows straightforward addressing
of a peripheral's internal registers, which
greatly slmphfies I/O programming.
A daisy-chained priority mechanism resolves
mterrupt and resource requests, thus allowmg
distributed control of the bus and elimmating
the need for separate prionty controllers. The
resource-control daisy chain allows wide
phYSiCal separation of components.
The Z-BUS is asynchronous in the sense that
peripherals do not need to be synchromzed
with the CPU clock. All timmg information is
provided by Z-BUS signals.
2031-0045
""'--CLOCK-----+-
- - - - - 8 U 8 REQUEST S I G N A L S - - - - -
-+----- BUSREQ----"
CPU
--BUSACK~
C=B:==
REQUESTER
-----IINTERRUPT S I G N A L S - - - - -
......-00-PERIPHERAL
~IEI----'
L - 1EO """-----RESOURCE REQUEST SIGNALS-----MMRQ----+-
Z·BUS
COMPONENT
"--MMST--
MULTI·MICRO
REQUEST
_4__MMAI--,
NETWORK
-----+- MMAO---.J
Figure 1. Z-BUS Signals
381
CPUs. A Z-BUS system contains one CPU, and
this CPU has default control of the bus and
typically initiates most hus transactions.
Besides generating bus transactions, it handles
interrupt and bus-control requests. The Z8001
Segmented CPU and Z8002 Non-Segmented
CPU are Z-BUS CPUs.
Peripherals. A Z-BUS peripheral is a component capable of responding to I/O transactions and generating interrupt requests. The
Z8036 Counter Input/Output Circuit (Z-CIO),
Z8038 FIFO Input/Output, Interface Unit
(Z-FIO), the Z8030 Serial Communication
Controller (Z-SCC), the Z8090 Universal
Peripheral ControlJer (Z-UPC), and the
Z8052 CRT Controller (Z-CRT) are all
Z-BUS peripherals.
Requesters. A Z-BUS requester is any component capable of requesting control of the
bus and initiating transactions on the bus. A
Z-BUS requester is usually also a peripheral.
The Z8016 DMA Transfer Controller (Z-DTC) is
a Z-BUS requester and a peripheral.
Memories. A Z-BUS memory is one that interfaces directly to the Z-BUS and is capable of
fetching and storing data in response to Z-BUS
memory transactions. The Z6132 Quasi-Static
RAM is a Z-BUS memory.
Other
Components
The Z8 Microcomputer-in its microprocessor configuration-conforms to Z-BUS
timing (which allows it to use Z-BUS
peripherals and memories), but is missing a
wait input and certain status outputs.
The Z8010 Memory Management Unit
(Z-MMUJ is a Z8000 CPU support component
that interfaces with part of the Z-BUS on the
CPU side and provides demultiplexed
addresses on the memory side.
The Z8060 First-In-First-Out Buffer (Z-FIFO)
is not a Z-BUS component; rather, it is used to
expand the buffer depth of the ,z-FIO or to
interface the I/O ports of the Z-UPC, Z-CIO,
or Z-FIO to user eqUipment.
Z-80 Family components, while not
Z-BUS compatible, are easily interfaced to
Z-BUS CPUs.
Operation
Two kinds of operations can occur on the
Z-BUS:, transactions and requests. At any given
time, one device (either the CPU or a bus
requester) has control of the Z-BUS and is
known as the bus master. A transaction is
initiated by a bus master and is responded to
by some other device on the bus. Four kinds of
transactions occur in Z-BUS systems:
at a time, and it must be initiated by the bus
master. A request, however, may be initiated by a component that does not have control of the bus. There are three kinds of
requests:
Z-BUS
Components
A Z-BUS component is one that uses Z-BUS
signals and protocols, and meets the specified
ac and dc characteristics. Most components in
the Z8000 Family are Z-BUS components. The
four categories of Z-BUS components are as
follows:
• Memory. Transfers 8 or 16 bits of data to or
from a memory location.
• I/O. Transfers 8 or 16 bits of data io or from
a peripheral.
• Interrupt Acknowledge. Acknowledges
an interrupt and transfers an identification/status vector from the interrupting
peripheral.
• Null. Does not transfer data. Typically used
for refreshing memory.
Only one transaction can proceed on the bus
382
• Interrupt. Requests the attention of the
Z-BUS CPU.
• Bus. Requests control of the Z-BUS to initiate transactions.
• Resource. Requests control of a particular
resource.
When a request is made, it is answered
according to its type: for interrupt requests an
interrupt-acknowledge transaction is initiated;
for bus and resource requests an acknowledge
signal is sent. In all cases a daisy-chain priority mechanism provides arbitration between
simultaneous requests.
Signal
Lines
be transmitted on a 16-bit bus. This signal is
not present on an 8-blt bus.
The Z-BUS consists of a set of common signal
lines that interconnect bus components (Figure
1). The signals on these lines can be grouped
into four catagories, depending on how they
are used in transactions and requests.
WAIT. (active Low). A Low on this line indicates that the responding device needs more
time to complete a transaction.
Primary Signals. These signals provide
timing, control, and data transfer for Z-BUS
transactions.
RESET. (active Low). A Low on this line resets
the CPU and bus users. Peripherals may be
reset by RESET or by holding AS and DS Low
simultaneously.
ADo-AD1S. Address/Data (active High). These
multiplexed data and address lines carry 1/0
addresses, memory addresses, and data during
Z-BUS transactions. A Z-BUS may have 8 or 16
bits of data depending on the type of CPU. In
the case of an 8-bit Z-BUS, data is transferred
on ADo-AD?
Extended Address. (active High). These
lines extend ADo-AD15 to support memory
addresses greater than 16 bits. The number of
lines and the type of address mformation
carried is dependent on the CPU.
Status. (active High). These lmes designate
the kind of transaction occurring on the bus
and certain additional information about the
transaction (such as program or data memory
access or System versus Normal Mode).
AS. Address Strobe (active Low). The rising
edge of AS indicates the beginning of ~trans
action and that the Address, Status, R/W, and
B/W signals are valid.
CS. Chip Select (active Low}~ach peripheral
or memory component has a CS line that is
decoded from the address and status lines. A
Low on this line indicates that the peripheral
or memory component is being addressed by a
transaction. The Chip Select information is
latched on the rising edge of AS.
CLOCK. This signal provides basic timing for
bus transactions. Bus masters must provide all
signals synchronouly to the clock. Peripherals
and memories do not need to be synchronized
to the clock.
Bus Request Signals. These signals make
bus requests and establish which component
should obtain control of the bus.
BUSREQ. Bus Request (active Low). This lme
is driven by all bus requesters. A Low indicates that a bus requester has or is trying to
obtain control of the bus.
DS. Data Strobe (active Low). DS provides
timing for data movement to or from the bus
master.
BUSACK. Bus Acknowledge (active Low). A
Low on this line indicates that the Z-BUS CPU
has relmquished control of the bus in response
to a bus request.
R/w' Read/Write (Low = write). This signal
determines the direction of data transfer for
memory or 1/0 transachons.
BAI, BAa. Bus Acknowledge In, Bus
Acknowledge Out (active Low). These signals
form the bus-request daisy chain.
B/W. Byte/Word (Low = word). This signal
mdicates whether a byte or word of data is to
383
Z-BUS
Connections
Signal
CPU
Requester
Peripheral
Memory
ADo-AD I5
BldlrecllonaJ2
3-state
BldlrecllonaJ2
3-state
Bldlrecllona)l
3-state
BldlreclIona!2
3-state
Extended
Address S
Output
3-state
Output
3-state
0
Input
Status
Output
3-state
Output
3-state
Input lO
0
R/W
Output
3-state
Output
3-state
Input
Input
B/Wg
Output
Output
Input3
Input
Input
Input
OutputS
Open Dram
OutputS
Open Dram
AS
Output
3-state
Output
3-state
Input
Input
DS
Output
3-state
Output
3-state
Input
Input
CS4
0
0
Input
Input
RESET
Input
Input l3
InputS
0
CLOCK14
Input
Input
InputS
InputS
BUSREQ
Input
Bldlrecllonal
Open Dram
0
0
BUSACK
Output
0
0
0
BAF
0
Input
0
0
BA07
0
Output
0
0
Input
0
Output
Open Dram
0
INTACK6
0
0
Input!!
0
IEF
0
0
Input
0
0
0
Output
0
WAIT
!NT
IE07
MMRQI2---
Output
Open Dram
MMST12
Input
MMAP,12
Input
MMA07,12
Output
1. Only ADO-AD7' unless perlpheralls 16-Blt
2. For an 8-blt bus, only ADO-AD7 are bidirectional.
Only for a 16-blt peripheral.
4. Derived signal, one for each penpheral or memory, decoded
from status and address lmes.
Ophonal~penpherals are tYPically reset by AS and i5S bemg
Low simultaneously, however, they can have a reset mput
6 Denved signal, decoded from status hnes.
7 Dalsy-cham lmes
8. Optional slgnal(s).
10 Ophonal-usually only mput on peripherals that are also
requesters
11. May be omitted If perIpheral mputs status hnes.
12. Optional signal; any component may attach to the resource
request hnes.
13. Ophonai sIgnal; a bus requestor may also be reset by AS and
D'S go1Og Low and BAI be10g HIgh sImultaneously.
14 ThIS sIgnal IS optIonallf there are no requesters on the bus.
CPU hm10g can be provIded by alternate means such as
crystal osclliator 10puts
9. For 16-bJt data bus only
Table 1. Z-BUS Component Connections to
Signal Lines. This table shows how the various
Z-BUS components attach to each signal line,
When a device is both a bus requester and a
384
peripheral, the attributes in both columns of
the table should be combined (e,g., input
combined with output and 3-state becomes
bidirectional and 3-state.J
o
No Connechon
Signal
Lines
(Continued)
Interrupt Signals. These signals are used for
mterrupt requests and for determining which
interrupting component is to respond to an
acknowledge. To support more than one type
of interrupt, the lines carrying these signals
can be replicated. (The 28000 CPU supports
three types of interrupts: non-maskable, vectored, and non-vectored.)
INT. Interrupt (active Low). ThIS signal can
be driven by any peripheral capable of generating an interrupt. A Low on INT mdicates that
an mterrupt request is bemg made.
INTACK. Interrupt Acknowledge (active
Low). This signal is decoded from the status
lmes. A Low indicates an interrupt acknowledge transachon IS in progress. This signal
is latched by the peripheral on the rising
edge of AS.
Resource Request Signals. These signals are
used for resource requests. To manage more
than one resource, the lines carrying these
signals can be replicated. (The 28000 supports
one set of resource request lines.)
MMRQ. Multi-Micro Request (active
Low). This line is driven by any deVIce that
can use the shared resource. A Low mdicates
that a request for the resource has been made
or granted.
MMST. Multi-Micro Status (active Low). This
pm allows a deVICe to observe the value of the
MMRQ lme. An mput pm other than MMRQ
facIlitates the use of lme drivers for MMRQ.
MMAI, MMAO. Multi-Micro Acknowledge In,
Multi-Micro Acknowledge Out (active
Low). These lines form the resource-request
daISY cham.
lEI, lEO. Interrupt Enable In, Interrupt Enable
Out (active High). These SIgnals form the
mterrupt daiSy cham.
Transactions
All transactions start with Address Strobe
being driven Low and then raised High by the
bus master (FIgure 2). The Status lines are
valid on the rising edge of Address Strobe and
mdicate the type of transactions bemg imhated. If the transachon requires an address,
It must also be valid on the rismg edge
of Address Strobe.
F or all transachons except null transactions
(which do nothing beyond thIS point), data IS
then transferred to or from the bus master. The
bus master uses Data Strobe to time the movement of data. For a read (R/W = HIgh), the
)O¢(
CLOCK
bus master makes ADo-ADI5 inachve before
driving Data Strobe Low so that the
addressed memory or peripheral can put its
data on the bus. The bus master samples this
data just before ralsmg Data Strobe High. For
a write (R/W = Low), the bus master puts the
data to be written on ADo-ADI5 before forcmg
Data Strobe Low.
For an 8-bit 2-BUS, data is transferred on
ADo-AD7. Address bits may remain on
ADs-ADI5 while DS is Low.
"»K
!------t.
-
I
-:1 BUS MASTER
SAMPLES
!NPUT DATA
BUS MASTER
SAMPLES WAIT
I
STo-ST3
R/W,BlW
AS
ADo-AD15
ADDRESS FROM
BUS MASTER
'\
DATA TO
BUS MASTER
\
ADO-AD15
-(
\
-
DATA FROM BUS MASTER
Figure 2. Typical Transaction Timin!]
2031·0181
385
Memory
Transactions
For a memory transaction, the Status hnes
distmguish among various address spaces,
such as program and data or system and normal, as well as indicating the type of transaction. The memory address is put on
ADo-AD15 and on the extended address lines.
For a Z-BUS with l6-bit data, the memory is
orgamzed as two banks of eight bits each
(Figure 3). One bank contains all the upper
bytes of all the addressable 16-bit words. The
other bank contams all the lower bytes. When
a single byte is written (R/W = Low,
B/W = High), only the bank indicated by
address bit Ao is enabled for writing.
For a Z-BUS with 8-bit data, the memory is
organized as one bank which contains all
bytes. This bank always inputs and outputs its
data on ADo-AD7.
i6.BIT z.SUS DATA PATH
0"
D
Ds D7
D.
Ao-A15
EXTENDED
ADDRESS
_-l:==~=L/
_________
LOWER
BANK
-'ENABLE
Figure 3. Byte/Word Memory Organization
I/O
Transactions
Null
Transactions
Interrupts
386
1/0 transactions are similar to memory
transachons wIth two important differences.
The first is that 1/0 transachons take an extra
clock cycle to allow for slow peripheral operahon. The second IS that byte data (indicated
by B/\/If High on a 16-bit bus) is always trans-
mltted on ADo-AD7, regardless of the I/O
address. (ADs-AD15 contain arbitrary data in
thIS case.) For an I/O transaction, the address
indICates a peripheral and a particular register
or function within that peripheral.
The two kinds of null transactions are distinguished by the Status lmes: internal operation and memory refresh. Both transachons
look hke a memory read transaction except
that Data Strobe remains High and no data IS
transferred.
For an internal operation transaction, the
Address lmes contam arbitrary data when
Address Strobe goes High. This transaction is
mitiated to mamtam a minimum transaction
rate when a bus master is doing a long mternal
operation (to support memories which generate
refresh cycles from Address Strobe).
For a memory refresh transaction, the
Address lines contain a refresh address when
Address Strobe goes High. ThiS transaction is
used to refresh a row of a dynamic memory.
Any memory or 1/0 transaction can be suppressed (effechvely turning it into a null transachon) by keeping Data Strobe High throughout the transaction.
A complete interrupt cycle consists of an
interrupt request followed by an interruptacknowledge transaction. The request, which
consists of INT pulled Low by a peripheral,
notihes the CPU that an mterrupt is pending.
The interrupt-acknowledge transaction, which
is Imtiated by the CPU as a result of the
request, performs two functions: it selects the
peripheral whose interrupt is to be acknowledged, and it obtams a vector that identifies
the selected device and capse of interrupt.
A peripheral can have one or more sources
of interrupt. Each interrupt source has three
bits that control how it generates interrupts.
These bits are an Interrupt Pending bit OP),
and Interrupt Enable bit (IE), and an Interrupt
Under Service bit (IUS).
A peripheral may also have one or more
vectors for identifymg the source of an interrupt during an interrupt-acknowledge transaction. Each interrupt source is associated with
one mterrupt vector and each interrupt vector
can have one or more interrupt sources assocIated with It. Each vector has a Vector Includes
Status bit (VIS) controlling ItS use.
Fmally, each peripheral has three bits for
2031-0182
Interrupts
(Continued)
controlling interrupt behavior for the whole
device. These are a Master Interrupt Enable
bit (MIE), a Disable Lower Chain bit (DLC),
and a No Vector bit (NV).
Peripherals are connected together via an
interrupt daisy chain formed with their IEI and
IEO pins (Figure 4). The interrupt sources
within a device are similarly connected into
this chain with the overall effect being a daisy
chain connecting the interrupt sources. The
daisy chain has two functions: during an
interrupt-acknowledge transaction, it determines which interrupt source is being
acknowledged; at all other times it determines
which interrupt sources can initiate an interrupt request.
Figure 5 is a state diagram for interrupt
processing for an interrupt source (assuming
its IE bit is 1). An interrupt source with an
interrupt pending (IP = 1) makes an interrupt
request (by pulling INT Low) if, and only if, It
is enabled (IE = 1, MIE = I), it does not have
an interrupt under service (IUS = 0), no
higher priority interrupt is being serVICed
(IEI = High), and no interrupt-acknowledge
transaction is in progress (as indicated by
IN TACK at the last rising edge of AS). lEO is
not pulled down by the interrupt source at this
time; IEO continues to follow IEI until an
interrupt-acknowledge transaction occurs.
Some time after INT has been pulled Low,
the CPU initiates an interrupt-acknowledge
transaction (mdicated by INTACK Low).
Between the rising edge of AS and the falling
edge of DS, the IEI/IEO daisy chain settles.
Any interrupt source with an interrupt pending
(IP = I, IE = I, MIE = 1) or under service
(IUS = I) holds its IEO line Low; all other
interrupt sources make lEO follow IEI. When
DS falls, only the highest prionty interrupt
source with a pending interrupt (IP = 1) has
its IEI input High, its IE bit set to 1, and its
IUS bit set to O. This is the interrupt source
being acknowledged, and at this point it sets
its IUS bit to 1, and, if the peripheral's NV bit
is 0, identifies Itself by placmg the vector on
ADo-AD7. If the NV bit is 1, then the peripheral's ADo - AD7 pins remain floating, thus
allowing external circuitry to supply the vector. (All mterrupts, including the Z8000's nonvectored interrupt, need a vector for identifying the source of an mterrupt.) If the vector's
VIS bit is 1, the vector Will also contain status
information further identifying the source of
the interrupt. If the VIS bit is 0, the vector
held in the peripheral will be output without
modi fica lion.
While an interrupt source has an interrupt
under service (IUS = 1), it prevents all lower
priority interrupt sources from requesting
interrupts by forcing IEO Low. When interrupt
servicing is complete, the CPU must reset the
IUS bit and, m most cases, the IP bit (by
means of an 1/0 transaclion).
INTERRUPT
VECTOR
INTERRUPT
VECTOR
II,~"
~
~
~~
,o,-Ao,
I
AS
os
fNfA'ER: '-"'T'--"i'-'T--'
lEI
HIQHE~~
PRIORI~~
Z·BUS
TT t ti
leO
INTACK
ADo-AD7
Z.BUS
CPU
Z·BUS
Z·BUS
PERIPHERAL
PERIPHERAL
T~
LOWEST
PRIORITY
lEI ADo-A01 AS
os
iN'i' i'NfAcR
I LJJl t
PERIPHERAL
lEO
~
AS
os
iNf
WAIT
STATUS
A08-AO'5
-
==ll
¢=:J
STATUS
DECODER
lEI AOo-A07
AS
os
iNT ffiTAC'K
"~gJJ )
,
lEO
+f
I
r
FROM 16·BIT PERIPHERALS
FIgure 4. Interrupt Connechons
2031·0189
387
Interrupts
ANY
(Continued)
tiNT
~
~ANY
rmmi ~. .
HIGH.
,
HIGH~
t-
lEI ...
IP
IUS
~lOW--"J
Y
r - H1GH
IIEO
INT
LOW
+
IE
lEI
~
a
IP
'm~:ri' ~
". "~
I
IP
IUS
IP
tiNT
IUS
IE
~
JUS
lOW
IE
CiEEJ
''''''Jl
~\
ANY~
~lOW ~
IP
IE
"~~,,.~ 1J
IE
LOW
IUS
'm~
c::J:II1J
HIGH
lOW
t
I "":;;+-..,1,;;;':-+;;;'"
)
)
STATE 4
ANY~
I
~,:.--------\--,
~--~-------~V
STATE 5
IP
IUS
IE
ITEEJ
.,S"TA",T"E".,..----...J
ANY
ANY
IP
IUS
IE
IP
~
IUS
IE
~
STATE 7
STATE 8
Figure 5. State Diagram for an Interrupt Source
Transition Legend
Siale Legend
fA'.- The penpheral detects an mterrupt conditIOn and sets
No mterrupts are pendmg or under serVlce for thIS
perIpheral.
t:,;' Interrupt PendIng.
rB'- All hlgher PriOrity penpherals fImsh mterrupt serVlce,
An mterrupt IS pendmg, and an mterrupt request has
been made by pulhng INT Low.
~ thus allOWIng IEI to go HIgh.
An mterrupt IS pendmg, but no mterrupt request has
been made because a hIgher pnonty penpheral has an
mterrupt under serVice, and thIS has forced lEI Low.
fC3'.An mterrupt-acknowledge transachon starts, and the
1.::;1" lEI/lEO daISY chaIn settles.
~ The mterrupt-acknowledge transactIOn termmates wlth
the peripheral selected. Interrupt Under ServIce (IUS)
IS set to I, and Interrupt PendIng (lP) mayor may not
be reset.
An mterrupt-acknowledge sequence IS In progress, and
no hIgher prIOrity perIpheral has a pendmg mterrupt.
fE'.. The mterrupt-acknowledge transdchon termmates With a
~ hIgher PriOrity deVIce havmg been selected.
If".. The Interrupt Pendmg bIt m the peripheral IS reset by
L::/ an I/O
operahon.
rG' A new mterrupt condlhon IS detected by the peripheral,
~ causmg IP to be set agam.
rH" Interrupt serVIce IS termmated for the perIpheral by
l.!:,/ resettmg IUS.
IE:> IE IS reset to zero, causmg mterrupts to be dIsabled.
IT:> IE set to one, re-enablmg mterrupts
IS
1. ThIS dIagram assumes MIE = 1 The effect of MIE = 0 IS the
same as that of sethng IE = O.
2. The DLe bIt does noi affect the states of mdividual mterrupt
sources. Its only effect 15 on the lEO output of a whole penpheral.
388
o
An mternipt-acknowledge sequence 15 m progress, but
a hIgher pnonty perIpheral has a pendmg mterrupt,
forcmg lEI Low.
The penpheral has an mterrupt under serVice, SerVice
may be temporarily suspended (mdlCated by lEI gomg
Low) If a hIgher pnonty deVIce generates an mterrupt.
ThIS IS the same as State 5 except that an mterrupt IS
also pendmg m the perIpheral.
Interrupts are disabled from thIS source because IE
o.
Interrupts are dlsabled from thIS source and lower
Priority sources because lE = 0 and IUS = 1.
3. TranSition I to state 6 or 7 can occur from any state except 3 or
4 (whIch only occur durmg mterrupt aCknowledge).
4. TransItIon J from state 6 or 7 can be to any state except 3 or 4,
dependmg on the value of lEI, IP, and IUS.
2031·0185
Interrupts
(Continued)
A peripheral's Master Interrupt Enable bit
(MIE) and Disable Lower Chain bit (DLC) can
modify the behavior of the peripheral's interrupt sources in the following way: if the MIE
bit is 0, the effect is as if every Interrupt
Enable bit (IE) in the peripheral were 0; thus
all interrupts from the peripheral are disabled.
If the DLC bit is I, the effect is to force the
peripheral's lEO output Low, thus disabling all
lower priority devices from initiating interrupt
requests.
Polling can be done by disabling interrupts
(using MIE and DLC) and by reading peripherals to detect pending interrupts. Each
Z-BUS peripheral has a single directly
addressable register that can be read to determine if there is an interrupt pending in the
device and, if so, what interrupt source
it is from.
Bus
Requests
To generate transactions on the bus, a bus
requester must gain control of the bus by
making a bus request. This is done by forcing
BUSREQ Low (Figure 6). A bus request can be
made only if BUSREQ is initially High (and has
been for two clock cycles), indicating that the
bus is controlled by the CPU and no other
device is requesting it.
After BUSREQ is pulled Low, the Z-BUS
CPU relinquishes the bus and indicates this
condition by making BUSACK Low. The Low
on BUSACK is propagated through the
BAIIBAO daisy chain (Figure 6). BAI follows
BAO for components not requesting the bus,
and any component requesting the bus holds
its BAO High, thereby locking out all lower
priority users.
A bus requester gains control of the bus
when its BAI input goes Low. When it is ready
to relinquish the bus, it stops pulling BUSREQ
Low and allows BAO to follow BAl. This permits lower priority devices that made simultaneous requests to gain control of the bus.
When all simultaneously requesting devices
have relinquished the bus, BUSREQ goes
High, returnmg control of the bus to the CPU
and allowing other devices to request it.
The protocol to be followed in making a bus
request is shown in Figure 7.
Z-BUS CPU
BUS
REQUESTORS
+5V
Figure 6. Bus Request Connections
2031·0193,0194
Figure 7. Bus Request Protocol
389
Resource
Requests
Resource requests are used to obtain control
of a resource that IS shared between several
users. The resource can be a common bus, a
common memory or any other resource. The
requestor can be any component capable of
implementing the request protocol.
Unlike the Z-BUS itself, no component has
control of a general resource by default; every
device must acquire the resource before using
it. All devices sharing the general resource
drive the MMRQ line (Figure 8). When Low,
the MMRQ line indicates that the resource is
being acquired or used by some device. The
MMST pin allows each device to observe the
state of the MMRQ line.
When MMRQ is High, a device may initiate
a resource request by pulling MMRQ Low
(Figure 9). The resulting Low on MMRQ is
propagated through the MMAI/MMAO daisy
chain. If a device IS not requestmg the
resource, its MMAO output follows its MMAI
input. Any device making a resource
request forces its MMAO output High to deny
use of the resource to lower priority devices.
A device gains control of the resource if its
MMAI input IS Low (and ItS MMAO output IS
High) after a sufficient delay to let the daisy
chain settle. If the device does not obtain the
resource after this short delay, it must stop
pulling MMRQ Low and make another request
at some later time when MMRQ is again High.
When a device that has gamed control of a
resource is finIshed, it releases the resource by
allowing MMRQ to go High.
The four unidirectional lines of the resource
request chain allow the use of line drivers,
thus facilitating connection of compone.nts
separated by some distance. In the case of the
Z8000 CPU, the four resource request lines
may be mapped into the CPU MI and MO pins
using the logic shown in Figure 10. With this
configuration, the Multi-Micro Request Instruction (MREQ) performs a resource request.
VES
+5V
MMAi 1---------1
MMST
MMRQ
1__- - - - - - - ;
f--------;
MMAO
Figure 9. Resource Request Protocol
MMAI
MMST
1---------1
MMAO
f--------;
For any resource requested, this walt hme must be less than the
minimum walt tIme plus resource usage hme of all other
requesters
MMAO
r-IP---------------~MMST
MMAI
:::: 1---------;
MMFfQ
MMAOIl
I
I
1
Mi
-----<><.
r-lP-r1-------------~MMAI
MO~----------------~
I
1
Figure S. Resource Request Connections
390
Figure 10. Bus Request Logic for ZSOOO
2031-0196.0238
Test
Conditions
The hmmg characterIstics gIven in this
document reference 2.0 V as High and 0.8 V
as Low. The following test load CIrcuIt is
assumed. The effect of larger capacItive
loadmgs can be calculated by delaying output
signal transihons by 10 ns for each addihonal
50 pF of load Up to a maximum 200 pF.
+5V DC
+5V DC
FROM OUTPUT
22K
T
22K
r
UNDERTESTl
50pF
Open-Drain Test Load
DC
Characteristics
Capacitance
The following table states the dc characterIStiCS for the input and output pms of Z-BUS
components. All voltages are relative to
ground.
Symbol
Parameter
Min
VIL
VIH
VIHRESET
Input Low Voltage
Input HIgh Voltage
Input High Voltage on RESET pIn
-0.3
2.0
2.4
VOL
VOH
IlL
IOL
Output Low Voltage
Output HIgh Voltage
Input Leakage Current
3-State Output Leakage Current In Float
The followmg table gives maximum pin
capacitance for Z-BUS components. Capacitance is specified at a frequency of I MHz
over the temperature range of the component.
Unused pms are returned to ground.
2.4
-10
-10
Symbol
CIN
COUT
CliO
Timing
Diagrams
The following diagrams and tables give the
timing for each kmd of transaction (except null
transactions). Timings are gIven separately for
bus masters and for peripherals and memories
and are intended to give the minimum hmmg
requirements whIch a Z-BUS component must
meet. An indIvidual component will have more
detailed and sometimes more stringent timing
specificahons. The dIfferences between bus
master hming and perIpheral and memory hming allow for buffer and decoding circUlt
Standard Test Load
Max
Unit
0.8
V
V
V
Vee+ 0.3
Vee to
0.3
0.4
+ 10
+10
V
V
/LA
/LA
Test Condition
N
•
D:I
IOL = 2.0mA
IOH = 250/LA
VIN = 0.4 to 2.4 V
VOUT = 0.4 to 2.4 V
Parameter
Max (pF)
Input Capacitance
Output CapacItance
BidIreclIonal CapacItance
10
15
15
delays and for signal skew. The timmg given
for memOrIes is a constraint on bus-compatible
memOrIes (lIke the Z6132 Quasi-Static RAM)
and IS not mtended to constrain memory subsystems constructed from conventional components.
Besides these timings, there is a requirement
that at least 128 transactions be imhated in any
2 ms period. This accommodates memOrIes that
generate refresh cycles from Address Strobe.
/
8085-004, 005
391
c:
rn
Bus Master
Timing
~r
~ r--®--I ., f
-----0---CLOCK
~~I-~j
2
3
CD---- -
~
STo-ST3
A/W,B/W
i0
/'~,
WAIT
SAMPLED
-f-0
r---
WAIT CYCLES
ADDEO
)[
CD----
](
~
l-w
o--
,
L;
REGISTER
CONTROL
§
AND
Q
Xl
REGISTER
FILE
;1----J\
\r-v'
ADDRESS
,--l\
REGISTER
f-
CPU
DATA
¢=;
SEGMENT NUMBER
REGISTER
~
CONTROL
UNIT
Y
II
if
CPU
CONTROL
REGISTER
ADDRESSI
DATA BUS
ADo-AD1S
rv'
-V
INTERNAL DATA BUS
1
-"
INSTRUCTION
LOOKAHEAD
lS
Figure 1. CPU Organization
:z'"
(D
ARITHMETIC
LOGIC
UNIT
ALU
CONTROL
READ/WRITE:
FLAGS
PROGRAM COUNTER OFFSET
REFRESH COUNTER
REFRESH TIMER
AND
INCREMENTER BY 2
i----
SEGMENT
ADDRESS
SNo-SN7
CPU
The Z8000 CPU also contains a number of
Organization special-purpose registers in addition to the
(Continued)
general-purpose ones. These include the Program Counter, Program Status reglsters and
RO
RRO (
17
./
oi7
All
R" (
Rsl
Rsl
A41
RRe (
RRlO
RR12
(
RR2 (
RR. (
RS [
RRG (
'1
RH'
RH'
R"
'0'
RII
R811s
RR' (
R91
( '" 1I
RRlO
Rll
RI2I
( "'/
Rul
RR12
Rul
'"
·1
./
Rsl
R" /
R1S'
RLa
"I
RL<
A91
I '"
017
R31
""'
RTI
R"
RR14
115
R2!
'0'
R111
(
11
R1
1'18115
Reo (
AO
RRO (
115
R21
R1
RR' (
the Refresh Counter. These registers are
accessible through software and provide some
of the interestmg features of Z8000 CPU
archi tecture.
N
§
RQ12
SYSTEM STACK POINTER (SEG NOI
NORMAL STACK POINTER (SEG NO)
RR14
SYSTEM STACK POINTER (OFFSET)
1"'1
R1S'
SYSTEM STACK POINTER
N
NORMAL STACK POINTER
R"
NORMAL STACK POINTER (OFFSET)
Q
Figure 3. Z8002 General Purpose Registers
Figure 2. Z8001 General Purpose Registers
c::
~
All general-purpose registers can be used as
Register
Organization accumulators, and all but one as index
registers or memory pomters. The one register
that cannot be used as an index register lS
Reglster O. Specifymg Register 0 is used as an
escape mechanism to change the address mode
from IR to 1M, from X to DA, or-with Load
mstructions-from BA to RA. This has been
done so that the two addressmg mode blts m
the mstruchon can speclfy more than four
addressing modes for the same opcode.
The Z8000 CPU reglster file can be
addressed in several groupings: as sixteen
byte reglsters (occupying the upper half of the
hIe only), as slxteen word registers, as eight
long-word reglsters, as four quadruple-word
registers, or as a mlxture of these. Instructions
elther expl!citly or lmplicltly specify the type
of register. Table 1 illustrates the correspondence between the 4-blt source and
destmation reglster he Ids in the mstruction
(Figure 4) and the location of the registers m
the register file (Flgures 2 and 3).
Word
Long
Word
Quadruple
Word
RO
RRO
ROO
Register
Designator
Byte
0000
RHO
0001
RHI
Rl
0010
RH2
R2
001 1
RH3
R3
0100
RH4
R4
0101
RH5
R5
01 10
RH6
R6
01 1 1
RH7
R7
aa
RLO
R8
100 1
RLl
R9
10 1 a
RL2
RIO
101 1
RL3
Rll
10
1 100
RL4
R12
1 101
RL5
R13
1 1 10
RL6
R14
1111
RL7
R15
R04
RR6
RR8
R08
RRI0
RR12
R012
RR14
Table I
2048·0207, 0208
DI
RR2
RR4
5.
2...
399
Register
Note that the byte regIster-addressing
Organization sequence (most sigmficant bIt distinguishes
(Continued)
between the two bytes in a word register) is
dIfferent from the memory addressing
sequence (least significant bit dishnguishes
between the two bytes in a word). Long-word
(32-bit) and quadruple-word (64-bit) regIsters
are addressed by the binary number of their
starting word registers (most significant word).
For example, RR6 is addressed by a binary 6
and occupies word registers 6 and 7.
BY~~~~ I M~DE
LO~g~O~~
MODE
REGISTER
I
MOpE
1
!
I"'wl
QPCQOE
!
!
SOURCE
!
!
QPCODE
SOURCE
!
!
!
!
!
!
DESTINATION
!
!
!
DESTINATION
!
!
!
j j
1
0
IMMEOIATE
DIRECT
~
} FOR SOURCE", 0
0
0
0
INDIRECT
~
} FOR SOURCE
'* 0
0
0
0
INDEXED
!
Figure 4. Instruction Format
System/
The Z8000 CPU can run in one of two
Normal Mode modes: System or Normal. In System Mode,
of Operation all of the instructions can be executed and all
of the CPU regIsters can be accessed. This
mode IS mtended for use by programs that perform operating system type functions. In Normal Mode, some instructions, such as I/O
mstruchons, are not all allowed, and the control registers of the CPU are inaccessIble. In
general, this mode of operation is intended for
use by application programs. This separahon
of CPU resources promotes the integrity of the
system since programs operating in Normal
Mode cannot access those aspects of the CPU
which deal wIth time-dependent or system
interface events.
Normal Mode programs that have errors can
always reproduce those errors for debugging purposes by simply re-executmg the programs with their onginal data. Programs using
facihties available only in System Mode may
have errors due to timing considerahons (e.g.,
based on the frequency of disk requests and
disk arm position) that are harder to debug
because these errors are not easily reproduced. Thus a preferred method of program
development would be to partition the task mto
that portion whIch can be performed without
recourse to resources acceSSIble only in
System Mode (which will usually be the bulk of
the task) and that portion requlflng System
Mode resources. The classIC example of this
parhhonmg comes from current mmlcomputer
and mainframe systems: the operatmg system
runs in System Mode and the mdivldual users
write their programs to run m Normal Mode.
To further support the System/Normal Mode
dichotomy, there are two copies of the stack
pomter-one for the System Mode and another
for Normal. Although the stacks are separated,
It is possible to access the normal stack
registers while in the System Mode by using
the LDCTL Instruction.
Status Lines
with 128K bytes If addihonalloglC IS used,
say, to select the lower 64K bytes for program
references and the upper 64K bytes for data
references ..
400
The Z8000 CPU outputs status information
over its four status lines (STo-ST 3) and the
System/Normal Ime (S/N). This information can
be used to extend the addressing range or to
protect accesses to certain portions of memory.
The types of status mformation and their codes
are hsted in Table 2.
Status conditions are mutually exclUSIve and
can, therefore, be encoded without penalty.
Most status defimhons are self-explanatory.
One code is reserved for future enhancements
of the Z8000 Family.
Extension of the addressing range IS accomplished m a Z8000 system by allocating
physical memory to specific usage (program
vs. data space, for example) and using external cirCUItry to monitor the status lines and
select the appropriate memory space for each
address. For example, the dIrect addressing
range of the Z8002 CPU is limited to 64K
bytes; however, a system Cdn be configured
Definition
0000
a a 01
aa 1 a
a 01 1
a 1 aa
a1a1
01 10
01 1 1
10 a a
100 1
10 1 a
101 1
1 100
1 J 01
1 1 10
1111
Internal operatIon
Memory refresh
I/O reference
SpeCIal 110 reference
Segment trap acknowledge
Non-maskable mterrupt acknowledge
Non-vectored interrupt acknowledge
Vectored mterrupt acknowledge
Data memory request
Stack memory request
Data memory request (EPU)
Stack memory request (EPU)
Instruchon space access
Instruction fetch, hrst word
ExtenSIon processor transfer
Reserved
Table 2
2048-0202
Status Lines
(Continued)
Protection of memory by access types is
accomplished similarly. The memory is diVIded
into blocks of locations and associated with
each block is a set of legal status signals. For
each access to the memory, the external circuit
checks whether the CPU status is appropriate
for the memory reference. The Z8010 Memory
Management Unit is an example of an external
memory-protection circuit, and it is discussed
later in this tutorial.
The first word in an instruction fetch has its
own dedICated status code, namely 1101. This
allows the synchronization of external circuits
to the CPU. During all subsequent fetch cycles
within the same instruction (remember, the
longest instruction requires a total of four word
fetches), the status is changed from 110 I to
1100. Load Relahve and Store Relahve also
have a status of 1100 with the data reference,
so information can be moved from program
space to data space.
Refresh
The idea of incorporating the Refresh
Counter in the CPU was pioneered by the
Z-80 CPU, which performs a refresh access in
a normally unused time slot after each opcode
fetch. The Z8000 is more straightforward (each
refresh has its own memory-access time slot of
three clock cycles), and is more versatile (the
refresh rate is programmable and capable of
being disabled altogether).
The Refresh Register contains a 9-bit Row
Counter, a 6-bit Rate Counter and an Enable
Bit (Figure 5). The row section IS output on
ADo-ADs during a refresh cycle. The Z8000
CPU uses word-organized memory, wherein Ao
is only employed to distinguish between the
lower and upper bytes within a word during
reading or writing bytes. Ao therefore plays no
role in refresh-it is always O. The Row
Counter is-at least conceptually-always
incremented by two whenever the rate counter
passes through zero. The Row Counter cycles
through 256 addresses on lines ADI-ADs,
which satisfies older and current 64- and
128-row addressing schemes, and can also be
used with 256-row refresh schemes for
64K RAMs.
The Rate Counter determines the time
between successive refreshes. It consists of a
programmable 6-bit modulo-n prescaler
(n = 1 to 64), driven at one-fourth the CPU
clock rate. The refresh period can be programmed from 1 to 64 JLS with a 4 MHz clock.
A value of zero in the counter held Indicates
the maximum hme between refreshes; a value
of n indicates that refresh IS to be performed
every 4n clock cycles. Refresh can be disabled
by programming the Refresh Enable Bit to
be zero.
A memory refresh occurs as soon as possible
after the indicated hme has elapsed. Generally, this means after the T3 clock cycle of an
instruction if an instruction execution has commenced. When the CPU does not have control
of the bus (during the bus-request/busacknowledge sequence, for example), it cannot
issue refresh commands. Instead, it has internal Circuitry to record "mIssed" refreshes;
when the CPU regains control of the bus It
immediately issues the "missed" refresh cycles.
The Z8001 and Z8002 CPU can record up to
two "mIssed" refresh cycles.
Most instructions conclude with two or three
clock cycles being devoted to internal CPU
operations. For such instruchons, the subsequent instruction-fetch machine cycle is
overlapped with the concluding operations,
thereby improving performance by two or
three clock cycles per instruction.
Examples of instruchons for which the subsequent instruction is fetched wh!le they complete are Arithmetic and Shift instructions.
Some instructions for which the overlap is
logIcally impossible are the Jump instructions
(because the following Instruchon 10catJon has
not been determined until the Instruchon completes). Some instructions for which overlap is
physically impossible are the Memory Load
instructions (because the memory is busy WIth
the current instruction and cannot service the
fetch of the succeeding instruction).
Instruction
Prefetch
(Pipelining)
2048·0203
I.
109
RATE
!
!
!
,
ROW
(
!
Figure 5. Refresh Counter
401
N
00
o
o
N
...
Q
c
DoO)
....
I:
;-
!.
Extended
Instruction
Facility
402
The Z8000 architecture has a mechanism for
extending the basic instruction set through the
use of external devices. Special opcodes have
been set aside to implement this feature. When
the CPU encounters instructions with these
opcodes in its instruction stream, it will perform any indicated address calculation and
data transfer, but otherwise treat the "extended
instruction" as being executed by the external
device. Fields have been set aside in these
extended instructions which can be interpreted
by external devices (called Extended Processing Units-EPUs) as opcodes. Thus by using
appropriate EPUs, the instruction set of the
Z8000 can be extended to include specialized
instructions.
In general, an EPU is dedicated to performing complex and time consuming tasks in
order to unburden the CPU. Typical tasks
suitable for specialized EPUs include floatingpoint arithmetic, data base search and
maintenance operations, network interfaces,
graphics support operations-a complete list
would include most areas of computing. EPUs
are generally desIgned to perform their tasks
on data resIdent in their internal registers.
Moving information into and out of the EPU's
internal registers, as well as instructing the
EPU as to what operations are to be performed, is the responsibility of the CPU.
For the Z8000 CPU, control of the EPUs
takes the following form. The Z8000 CPU
fetches instructions, calculates the
addresses of operands residing in memory,
and controls the movement of data to and
from memory. An EPU monitors this activity on
the CPU's AD lines. If the instructions fetched
by the CPU are extended instructions, all
EPUs and the CPU latch the instruction (there
may be several different EPUs controlled by
one CPU). If the mstruction is to be executed
by a particular EPU, both the CPU and the
mdicated EPU will be involved in executing
the instruction.
If the extended instruction indicates a
transfer of clata between the EPU's internal
registers and the main memory, the CPU will
calculate the memory address and generate
the appropriate timmg signals (AS, DS,
MREQ, etc.), but the data transfer itself IS
between the memory and the EPU (over the
AD lines). If a transfer of data between the
CPU and EPU is indicated, the sender places
the data on the AD lines and the receiver
reads the AD lines during the next clock
period.
If the extended instruction indicates an
internal operation to be performed by the EPU,
the EPU begins execution of that task and the
CPU is free to continue on to the next instruction. Processing then proceeds simultaneously
on both the CPU and the EPU until a second
extended instruction is encountered that is
destined for the same EPU (if more than one
EPU is in the system, all can be operating
simultaneously and independently). If an
extended instruction specifies an EPU still
executing a previous extended instruction, the
EPU can suspend instruction fetching by the
Z8000 CPU until it is ready to accept the next
extended instruction: the mechanism for this is
the STOP line, which suspends CPU activity
during the instruction fetch cycle.
There are four types of extended instructions
in the Z8000 CPU instruction repertoire: EPU
internal operations; data transfers between
memory and EPU; data transfers between EPU
and CPU; and data transfer between EPU flag
registers and CPU flag and control word. The
last type is useful when the program must
branch based on conditions determined by the
EPU. Six opcodes are dedicated to extended
instructions: OE, OF, 4E, 4F, 8E and 8F (in
hexadecimal). The action taken by the CPU
upon encountering these instructions is dependent upon an EPU control bit in the CPU's
FCW. When this bit is set, it indicates that the
system configuration includes EPUs; therefore,
the instruction is executed. If this bit is clear,
the CPU traps (extended instruction trap), so
that a trap handler in software can emulate the
desired operation.
In conclusion, the major features of this
capability are, that multiple EPUs can be
operating in parallel with the CPU, that the
five main CPU addressing modes (Register,
Immediate, Indirect Register, Direct Address,
Indexed) are available in accessing data for
the EPU; that each EPU can have more than
256 different instructions; and that data types
manipulated by extended instructions can be
up to 16 words long.
Program
Status
Information
Interrupt
and Trap
Structure
Effects of
Interrupts
on Program
Status
The Program Status Informahon consists of
the Flag And Control Word (FCW) and the
Program Counter (PC). The Z8000 CPU uses
one byte in FCW to store flags and another
byte to store control bits.
Control Bits. The control bits occupy the
upper byte in the FCW. They are loaded and
read by the LDCTL instruchon, which IS
privileged In that it can be executed only in
the System Mode. The control bits are:
Arithmetic Flags. Flags occupy the low byte
in the FCW and are loaded, read, set and
reset by the special instruction LDCTLB,
RESFLG and SETFLG. The flags are:
NVIE Non-Vectored Interrupt Enable
C
Carry
Z
Zero
S
Sign (l = negative; two's complement
notation IS used for all anthmehc on
data elements)
P/V
Even Parity or Overflow (the same bit is
shared)
D
Decimal Adjust (differentiates between
addition and subtraction)
H
Half Carry (from the low-order nibble)
VIE
Vectored Interrupt Enable
SIN System or Normal Mode
SEG Segmented Mode Enable (Z8001 only)
The SEG bit is always 0 in the Z8002 even if
the programmer attempts to set it. In the
Z800 I, a I in this bit indicates segmented
operation. A 0 in the Z8001 SEG bit forces
non-segmented operation and the CPU interprets all code as non-segmented. Thus, the
Z8001 can execute modules of user code
developed for the non-segmented Z8002.
N
00
...g
N
The Z8000 provides a powerful Interrupt and
trap structure. Interrupts are external asynchronous events requiring CPU attention, and
are generally tnggered by peripherals needing
service. Traps are synchronous events
resulting from the execution of certain instructions. Both are processed in a similar manner
by the CPU.
The CPU supports three types of interrupts
(non-maskable, vectored and non-vectored),
three internal traps (system call, unimplemented instruction, privileged instruction) and
a segmentation trap. The vectored and nonvectored interrupts are maskable.
The descending order of priority for traps
and interrupts is: internal traps, non-maskable
Interrupts, segmentahon trap, vectored interrupts and non-vectored interrupts.
The Flag and Control Word and the Program Counter are collectively called the Program Status Information-a useful grouping
because both the FCW and PC are affected by
interrupts and traps. When an interrupt or trap
occurs, the CPU automahcally SWitches to the
System Mode and saves the Program Status
plus an identifier word on the system stack.
The identifier supplies the reason for the interrupt. (The Z8002 pushes three words on the
stack; the Z8001 pushes four words.)
After the pre-interrupt or "old" Program
Status has been stored, the "new" Program
Status is automatically loaded into the FCW
and PC. This new Program Status Information
is obtained from a specified location in
memory, called the Program Status Area.
The Z8000 CPU allows the location of the
Program Status Area anywhere in the addressable memory space, although it must be
aligned to a 256-byte boundary. Because the
Status Line code is 1100 (program reference)
when the new Program Status is loaded, the
Program Status must be located in program
memory space if the memory uses this attribute
(for example, when using the 28010 Memory
Management Unit or when separate memory
modules are used for program and for data).
The Program Status Area Pointer (PSAP)
specifies the beginning of the Program Status
Area. In the 28002, the PSAP is stored in one
word, the lower byte of which is zero. The
28001, however, stores its PSAP in two words.
The first contains the segment number and the
second contains the offset, the lower byte of
which is again zero. The PSAP is loaded and
read by the LDCTL instruchon.
In the 28002, the first 14 words (28 bytes) of
the Program Status Area contain the Program
Status Information for the follOWing interrupt
conditions:
Location
{1n Bytesl
Condition
0-3
Not used (reserved for future use)
4-7
Ummplemented Instruchon has
been fetched, causing a trap
8-11
PriVileged instruchon has been
fetched in Normal Mode, causing a
trap
12-15
System Call Instruchon
16-19
Not used
20-23
Non-maskable interrupt
24-27
Non-vectored interrupt
403
"...,
d
..a
i...
-
III
Effects of
Interrupts
on Program
Status
(Contmued)
Bytes 28-29 contain the FCW that is common to all vectored interrupts. Subsequent
locations contam the vector jump table (new
PC for vectored interrupts). These locahons
are addressed in the following way: the 8-bit
vector that the interrupting device has put on
the lower byte of the Address/Data bus
(ADo-AD7) IS doubled and added to
PSAP + 30. Thus,
Vector 0 addresses PSAP + 30,
Vector I addresses PSAP + 32, and
Vector 255 addresses PSAP + 540.
In the segmented 2800 I, the hrst 28 words of
the Program Status Area (56 bytes) contam the
Program Status Information (reserved word,
FCW, segment number, offset), for the following mterrupt conditions:
Location
(In bytes)
Bytes 56-59 contain the reserved word and
FCW common to all vectored mterrupts.
Subsequent locations contain the vector jump
table (the new segment number and offset for
all vectored interrupts). These locations are
addressed in the following way: the 8-bit vector that the interrupting device has put on the
lower byte of the Address/Data bus (ADo-AD7)
is doubled and added to PSAP + 60. Thus,
Vector 0 addresses PSAP + 60,
Vector 2 addresses PSAP + 64, and
Vector 254 addresses PSAP + 568.
Care must be exercised in allocating vector
locations to interrupting devices; always use
even vectors. Thus there are effectively only
128 entries m the vector jump table. (Figure 6
illustrates the Program Status Area.)
Condition
UNIMPLEMENTED
INSTRUCTION
0-7
Not used (reserved for future use)
PRIVILEGED
INSTRUCTION
8-15
Ummplemented instruchon has
been fetched causing a trap
SYSTEM CALL
INSTRUCTION
16-23
PriVIleged instruchon has been
fetched m Normal Mode causing
a trap
24-31
32-39
System Call mstruction
Segmentahon trap (memory violahon detected by the 28010 Memory
Management Umt)
40-47
Non-maskable mterrupt
48-55
Non-vectored mterrupt
SEGMENT TRAP
{UNUSED FOR za002J
NON MASKABLE
INTERRUPT
NON VECTORED
INTERRUPT
28
30
VECTOREOINT
r- NEWPC- -
56
60
54
:========::: lVECTORED
INTERRUPT
JUMP TABLE
NEW PC
Figure 6. Program Status Area
404
2048·0204
Z8000 CPU
Memory
Features
The way a processor addresses and manages
ItS memory IS an Important aspect m both the
evaluation of the processor and the desIgn of a
computer system that uses the processor. Z8000
archItecture provIdes a consIstent memory
address notahon m combming bytes into words
and words mto long words. All three data
types are supported for operands m the Z8000
mstructlOn set. 1/0 data can be either byte- or
word-Oriented.
The Z8001 CPU provides a segmented
addressmg space WIth 23-blt addressing. The
Z8010 Memory Management Umt can mcrease
the address range of this processor. To support
a memory management system, the Z8001 processor generates Processor Status Informahon.
These sIgnals are also generated by the Z8002
CPU and-as mentioned ear her-can be used
to increase the address range of this processor
beyond its nominal 64K byte limit. It is not
necessary to use a Z8010 Memory Management
Unit WIth a Z8001. The segment number {upper
SIX bits of the address} can be used directly by
the memory system as part of the absolute
address.
These Issues are discussed in more detall in
the following sections, along with a description of the method used to encode certam
segmented addresses mto one word. A brief
comment on the use of 16K DynamIc RAMs
WIth the Z8001 concludes this group of sections
that deal with Z8000 CPU memory features.
Address
Notation
In the Z8000 CPU, memory and 1/0
addresses are always byte addresses. Words or
long words are addressed by the address of
their most slgmficant byte {FIgure 7}. Words
always start on even addresses (Ao = 0), so
both bytes of a word can be accessed sImultaneously. Long words also start on even
addresses.
WIthin a word, the upper {or more slgmficant} byte IS addressed by the lower {and
always even} address. SImilarly, wlthm a long
word, the upper {more slgmiJcant} word is
addressed by the lower address. Note that this
format differs from the PDP-II but IS idenhcal
to the IBM convenhon.
There IS good reason for choosing thIS format. Because the Z8000 CPU can operate on
32-bit long words and also on byte and word
strings, It IS Important to mamtam a continUIty
of order when words are concatenated mto
long words and strmgs. Makmg ascending
addresses proceed from the highest byte of the
hrst word to the lowest byte of the last word
mamtains this contmUlty, and allows compar-
ing and sortmg of byte and word strings.
Bit labeling withm a byte does not follow thIS
order. The least significant bit m a byte, word
or long word IS called BIt 0 and occurs m the
byte with the hIghest memory address. ThIS is
consistent WIth the convenhon where bIt n
corresponds to posItion 2 n m the conventional
bmary notation. ThIS ordermg of bIt numbers
IS also followed in the regISters.
2048·0205
LONG WORD
ADDRESSES
WORD
ADDRESSES
'''l-l
.. [ .. [
"
"
1000
1
0010
[
0100
[
01iD[
1000 [
0000
5B
0010
C2
0011
35
0100
02
0101
AB
0110
2B
0111
FF
1000
A2
1001
CONTENTS OF BYTE 0100 '" "02"
CONTENTS OF WORD 0100 '" "02AB"
CONTENTS OF LONG WORD 0100
CONTENTS OF LONG WORD 0010
N
C':I
tel
C
~
-
AO
QaDi
o
....
C
i...
I»
BYTE
ADDRESSES MEMORY
~
0000 [
N
CO
= "02AB2BFF"
= "C23502AB"
Figure 7. Memory Addressing
405
Memory
and 1/0
Addressing
Like most 16-bit microprocessors, the 28000
CPU uses a 16-bit parallel data bus between
the CPU and memory or I/O. The CPU is
capable of reading or writing a 16-bit word
with every access. Words are always addressed
with even addresses (Ao = 0). All instructions
are words or multiple words.
The 28000 CPU can, however, also read and
write 8-bit bytes, so memory and I/O addresses
are always expressed in bytes. The Byte/Word
(B/W') output indicates whether a byte or word
is addressed (High = byte). Ao distinguishes
between the upper and lower byte in memory
or I/O. The most significant byte of the word is
addressed when Ao is Low (Figure 8).
For word operations in both the read and
write modes, B/W' = Low, Ao is simply
ignored and Al-A1S address the memory or
I/O. For byte operations in the read mode,
B/W' = High, Ao is again ignored, and a
whole word (both bytes) is read, but the CPU
internally selects the appropriate byte. For
byte operations in the write mode, the CPU
outputs identical informatiop. on both the Low
(ADo-AD?) and the High (ADs-AD IS) bytes of
, the Address/Data bus. External TTL logic must
be used to enable writing in one memory byte
and disable writing in the other byte, as
defined by Ao. The replication of byte information for writes is for the current implementation
and may change for subsequent 28000 CPUs;
therefore system designs should not depend
upon this feature.
i6·BIT BUS DATA PATH
D
0,
WORD,
ADDRESS;
B'W
-011>-:---...,-...-,
" --':""'-I:»-I--f-L/
R/W
LOWER
--i:==:±=L./-----------'
BANK
ENABLE
Figure 8. Byte/Word Selection
Segmentation
406
In organizing memory, segmentation is a
powerful and useful technique because It forms
a natural way of dividing an address space into
different functional areas. A program typically
partitions its available memory into disjointed
areas for particular uses. Examples of this are
storing the procedure instructions, holding its
global variables, or serving as a buffer area
for processing large, dIsk-resident data bases.
The reqUIrements for these different areas may
differ, and the areas themselves may be
needed only part of the time.
Segmentation reflects this use of memory by
allOWing a user to employ a different segment
for each different area. A memory management system can then be employed to provide
system support, such as swapping segments
from disk to primary memory as requested (as
in overlays), or in monitoring memory accesses
and allOWing only certam types of accesses to
a particular segment. Thus, dealing with
segments is a convenient way of speCifying
portions of a large address space.
When segmentation is combined with an
address translation mechanism to provide
relocation capability, the advantages of
segmentation are enhanced. Now segments can
be of variable user-specifiable sizes and
located anywhere in memory.
The 28001 generates 23-bit logical
addresses, consisting of a 7-bit segment
number and a 16-bit offset. Thus each of its six
memory address spaces consists of 128 segments, and each segment can be up to 64K
bytes. Different routines of a program can
reside in different segments, and different data
sets can reside in different segments. The
28010 Memory Management Unit translates
these logical addresses into physical-memory
locations.
2048-0206
Long Offset
and Short
Offset
Addressing
When a segmented address IS stored in
memory or in a register, it occupies two
l6-blt words as previously descnbed for the
PC and PSAP. This is a consequence of the
large addressmg range. When a segmented
address is part of an mstruction in the DIrect
Address and Indexed Address Modes, there
are two representations: Long and Short Offset
addressmg.
In the general unrestricted case of Long Offset, the segmented address occupIes two
words, as described before. The most signihcant bit m the segment word IS a I in this case.
The Short Offset Mode squeezes the segment
number and offset into one word, saving pro-
gram sIze and execution time. Smce 23 bits
obviously don't fit into a l6-blt word, the 8
most sIgnificant bits of the offset are omItted
and implied to be zero. The most slgnihcant
bIt of the address word is made 0 to mdlcate
Short Offset Mode. Short Offset addresses are
thus hmlted to the first 256 bytes at the begmning of each segment. This may appear to be a
severe restnchon, but it IS very useful,
especIally in the Index Mode, where the mdex
register can always supply the full l6-bit range
of the offset. Short Offset saves one mstruction
word and speeds up execution by two clock
cycles m DIrect Address Mode and three clock
cycles in Indexed Mode.
Using the
Z8010 Memory Management Unit
The Z8001 CPU can be combmed with
another 48-pin LSI deVICe-the Z8010 MMUfor sophisticated memory management. The
MMU provides address translahon from the
logICal addresses generated by the Z800l CPU
to the phYSIcal addresses used by the memory.
An address translation table, contaming startmg addresses and sIze informatIOn for each of
the 64 segments, is stored m the MMU. The
translation table can be written and read by
the CPU usmg SpeCIal I/O instruchons. The
MMU thus provIdes address relocation under
software control. making software addresses
(i.e., logical addresses) mdependent of the
phYSIcal memory addresses.
But the MMU provIdes much more than
address relocahon; It also monitors and protects memory access. The MMU provides a
Trap input to the CPU and-if necessary-an
inhIbIt signal (SUP) to the memory write logic
when specihc memory-access VIOlations occur.
The MMU provides the following types of
memory protechon:
Multiple MMUs must be used when more
than 64 segments are needed. Thus, to support
the full complement of 128 segment numbers
provIded for each Z800l CPU address space,
two MMUs are reqUIred. The MMU has been
deSIgned for mulhple-chip configurations, both
to support l28-segment translation tables and
to support mulhple translation table systems.
Note that the memory management features
do not mterfere with the ability to directly
address the entire memory space. Once programmed, the MMU (or MMUs) translates and
monitors any memory address generated by
the CPU.
The MMU contains status bits that describe
the hIstory of each segment. One bit for each
segment indicates whether the segment has
been accessed; another bll indIcates whether
the segment has been written. This IS Important
for certain memory management schemes. For
example, the MMU indicates which segments
have been updated and, therefore, must be
saved on disk before the memory can be used
by another program.
When translating logical addresses to physIcal memory addresses, the MMU must do the
following: access ItS mternal 64 x 32-blt RAM,
usmg the segment number as the address, then
add the 16 bIts of RAM output to the most
sigmhcant address byte (ADs-AD15) and fmally place the result on ItS Address outputs. The
least sigmficant byte (ADo-AD7) bypasses the
MMU.
The mternal RAM access hme IS approxImately 150 ns. Throughput delay IS aVOIded by
making the segment number available early:
SNo-SN7 are output one clock period ear her
than the address mformahon on ADo-AD7.
In summary, the Z8000 CPU supports
sophlShcated memory management through
such archItectural features as the Status Lmes,
the R/W and SiN lines, Segment Trap mput
lme, and early output of segment numbers.
• Accesses outsIde the segment's alloted
memory can be prevented.
• Any segment can be declared mvahd or
non-accessable to the CPU.
• Segments can be declared Read Only.
• By desIgnating a segment as System Only,
access can be prohIbited during the Normal
Mode.
• Declarmg a segment Execute Only means It
can be accessed only dunng mstruchon
access cycles. Data or stack use IS prohIbIted.
• Any segment can be excluded from DMA
access.
• Segments can have a Dlrechon And Wnte
Warnmg attribute, whIch generates a trap
when a wnte access IS made m the last 256
bytes of ItS size. ThIS mechamsm can be
used to prevent stack overflow.
407
toil
00
C
S
N
Q
c::
~
a
2...
11/
Using 16K
Dynamic
RAMs with
the Z8DDI
28000 systems usually implement most of
their memory with 16K x I-bit dynamic RAMs
that have time-multiplexed addresses (2ilog
also manufactures thIs device-the 26116).
In 28001-based systems with MMUs, CPU
Address/Data lines AD1-AD7 supply row
addresses, MMU address outputs As-AI4 supply column addresses, and MMU outputs
A15-A23 are decoded to generate Chip Select
sIgnals that gate either RAS or CAS or both.
Gating RAS reduces power consumption
because all non-selected memories remain
m the standby mode. But this technique
reqUIres that RAS must wait for the availabihty
of the most sigmficant address bits from the
MMU. During refresh, the RAS decoder must
be changed to activate all memories
sImultaneously.
Gating CAS does not achieve lower power
consumption; however, this technique allows
the use of slower memones because RAS can
be activated as soon as the CPU address outputs are stable, without waiting for the MMU
delay. Also, there is no need to change the
CAS decoder during refresh.
Data Types
and
Instructions
The 28000 archItecture directly supports
bits, digIts, bytes, and 16- or 32-bit integers as
primitive operands in its instruction set. In
addItion, the nch set of addressing modes supports higher-level data constructs such as
arrays, lists and records. The 28000 also intro-
duces a number of powerful instructions that
extend the capabihties of microprocessors. The
remaining sections of thIs paper describe
28000 data types, addreSSing modes, and a
selection of novel instructions.
Data Types
Operands are I, 4, 8, 16,32, or 64 bits, as
specified by the instructIOn. In addition,
strings of 8- or 16-bit data can be mampulated
by single instructions. Of particular interest
are the mcreased precisions of the arithmetic
instructions. Add and Subtract instructions can
operate on 8-, 16-, or 32-bit operands; Multiply mstructions can operate on 16- or 32-bit
multiplicands; and Divide instructions can
operate on 32- or 64-bit dividends. The Shift
instructions can operate on 8-, 16-, and 32-b1t
registers.
Addressing
Modes
The nch vanety of addressing modes offered
by 28000 architecture includes: Register,
Immediate, IndIrect Register, Direct Address,
Index, Relative Address, Base Address, and
Base Index. Three are of particular interest
with respect to high-level data structures:
IndIrect Register, Base Address, and Base
Index. These modes can be used for lists,
records, and arrays, respectively.
IS useful, for example, in accessing fields
within a record whose format is fixed at compile time.
Indirect Register. In this addressing mode,
the contents of the register are used as a
memory address. This mode is needed
whenever special address arithmetic must be
performed to reference data. Essentially, the
address is calculated in a register and then
used to fetch the data. For example, this mode
IS useful when manipulating a lmked list,
where each entry contains a memory pointer to
the memory location of the next entry. Essentially, the pointer is loaded into a register and
used to access the next item on the list. When
the list Item is large or has a complex structure, the Base Address or Base Index Modes
can be used to access various components of
the Item.
Base Address. In thIS addressing mode, the
memory address contained in the regISter (the
base) is modified by a dIsplacement in the
instruction (known at compile time). This mode
408
Base Index. The memory address in this
addressmg mode IS contamed in a register (the
base) and is modified by the contents of
another register (the index). ThIS mode can be
useful m accessing the components of an
array, because the index of the component is
usually calculated during execution time-as a
function of the mdex of a DO-Loop, for
example.
Index vs. Base Address~8G02 and in
the 28001 running non-segmented, these two
addressmg modes are functionally equivalent,
because the base address and displacement
are both 16-bit values.
When the 28001 runs segmented, there is a
difference: in the Index mode, the base
address (mcluding the segment number) IS
contained in the instructIOn, in eIther Short
Offset or Long Offset notahon. The 16-blt displacement stored in a register IS then added to
the offset in the base address to calculate the
effechve address. In the Base Address Mode,
on the other hand, the l6-blt displacement is
speCIfied m the instruction and is added to the
offset of the base address that is stored in a
long-word register.
The Instruction Set
The Z8000 offers an abundant instruction set
that represents a major advance over ItS
predecessors. The Load and Exchange instructions have been expanded to support operating
system functions and conversion of existing
microprocessor programs. The usual Arithmetic mstructions can now deal with higherprecisIOn operands, and hardware Multiply
and DIvide instructions have been added. The
Bit Manipulation instruchons can access a
calculated bit position within a byte or word,
as well as speCify the posItion stahcally in the
instruction.
The Rotate and Shift mstructions are conSiderably more flexible than those in prevIOus
microprocessors. The String instructions are
useful in translating between dIfferent
character codes. Special I/O mstructions are
included to manage penpheral devices, such
as the Memory Management Umt, that do not
respond to regular I/O commands. Multipleprocessor configurations are supported by
special mstructions.
The following mstruchons exemphfy the
mnovative nature of the Z8000 mstruchon set.
A complete hst of Z8000 mstructions can be
found in the reference materials listed at the
end of thIs tutonal.
Load and Exchange Instructions.
Exchange Byte (EX) IS prachcal for converting
Z-80, 8080, 6800 and other mIcroprocessor
programs into Z8000 code, because the Z8000
uses the opposite assignment of odd/even
addresses in 16-blt words.
Load Multiple (LDM) saves n registers and IS
useful for switching tasks.
Load Relative (LDR) loads fixed values from
program space mto data space.
Arithmetic Instructions.
Add With Carry and Subtract With Carry
(ADC, SBC) are conventionally used m 8-blt
microprocessors for mulhprecislOn arithmehc
operations. These mstructions are rarely used
with the Z8000 CPU because it has 16- and
32-bit arithmehc instruchons.
Decrement By N and Increment By N (DEC,
INC) are mtended for address and pomter
manipulation, but can also be used for Quick
• Add/Subtract ImmedIate with 4-bJt mbbles.
The flag settmg IS different from Add/Subtract
instruchons-as IS conventional-m that the
Carry and DeCImal adjust flags are unaffected
by the Increment and Decrement mstructlOns
to support mulhple precIsIon anthmehc.
Decimal Adjust (DAB) automahcally generates
the proper 2-dlglt BCD result after a byte Add
or Subtract operahon, and elimmates the need
for special decimal anthmehc mstruchons.
Multiply (MULT) provides signed (two's complement) multiplication of two words, generating a long-word result; or of two long-words
generatmg a quadruple word result. No byte
multiply eXIsts because it is rarely used and,
after sign extension, can be performed by a
word multiply.
Divide (DIV) prOVIdes signed (two's complement) divisIOn of a long word by another word,
generating a word quotient and a remainder
word; or of one quadruple-word by a longword, generating a long-word quohent and
long-word remainder.
Both Mulhply and DIvide use a conformmg
regIster assignment. That is, a multiply followed by a divide on the same regIsters is
essentially a no-op. The regISter desIgnation
used in the operahon description must be even
for word operahons and must be a multiple of
four for long-word operations.
Logical Instructions.
Test Condition Code (TCC) performs the same
test as a Jump mstruchon, but affects the least
slgmhcant bit of a specihed register mstead of
changing the PC.
Program Control Instructions.
Call Relative (CALR) IS a shorter, faster versIon of Call, but WIth a hmited range.
Decrement And Jump If Non-Zero (DJNZ) is a
one-word basic looping instruction.
Jump Relative (JR) IS a shorter, faster versIOn
of Jump, but WIth a hmited range.
Bit Manipulation Instructions.
Test Bit, Reset Bit, Set Bit (BIT, RES, SET) are
available in two forms: stallc and dynamic. For
the static form, any bit (the posItion is defined
m the immediate word of the mstruchon)
located m any byte or word m any regIster or
m memory can be set, reset or tested (mverted
and routed into the Z flag).
For the dynamIC form, any bIt (the position
is defined by the content of a register that IS,
m turn, speclhed in the mstruction) located in
any byte or word m any register, but not in
memory, can be set, reset or tested.
Test And Set (TSET) IS a read/modify/write
mstruchon normally used to create operating
system locks. The most slgmficant bit of a byte
or word in a regIster or in memory is routed
mto the S flag bit and the whole byte or word
is then set to all Is. Durmg thIS mstruchon, the
processor does not relmquish the bus.
Test Multi-Micro Bit and Multi-Micro
Request/Set/Reset (MBIT, MREQ, MSET,
MRES) are used to synchronize the access by
mulhple mICroprocessors to a shared resource,
409
The Instruction Set
(Continued)
such as a common memory, bus, or I/O
devICe.
Note that the instruction MREQ (MultiMIcroprocessor Request) has nothing whatsoever in common with the MREQ (Memory
Request) output from the 28000 CPU.
Rotate and Shift Instructions.
The 28000 CPU has a complete set of shift
instructions that shIft any comb mati on of bytes
or words, right or left, anthmetically or logICally, by any meaningful number of posItions as
specified either in the mstruction (stahc) or in
a register (dynamIc).
The CPU also has a smaller repertoire of
rotate instruchons that rotates bytes or words,
either right or left, through carry or not, and
by one bIt or by two bIts.
The instructions Rotate Digit Left and Rotate
Digit RIght (RLDB, RRDB) rotate 4-blt BCD
dIgits right or left, and are used in BCD arithmetic operations.
Block Transfer and String Manipulation
Instructions.
Translate And Decrement/Increment (TRDB,
TRIB) is used for code conversion, such as
ASCII to EBCDIC. These mstructlOns translate
a byte strmg in memory by substitutmg one
string by its table-lookup eqUIvalent. TRDB
and TRIB execute one operatIOn and decrement the contents of the length register; thus
they are useful as part of loop performmg
several achons on each character.
TRIB, except they repeat automatically unhl
the contents of the length register become
zero. They are therefore useful m straightforward translation applications.
Translate And Test, Decrement/Increment
(TRTDB, TRTIB) tests a character according to
the contents of the translahon table.
Translate And Test, Decrement/Increment And
Repeat (TRTDRB, TRTIRB) scans a string of
characters. The first character is tested and,
depending on the contents of the translation
table, the process stops or skips to the next
character. Stopped characters can be used for
further processing.
1/0 and Special 1/0 Instructions.
The 28000 CPU has two complete sets of I/O
instructions: Standard I/O and Special I/O.
The only difference is the status informahon on
the STo-ST3 outputs. Standard I/O instructions
are used to communic;ate WIth 2-Bus compatible peripherals. Special I/O mstructions are
tYPIcally used for communicatmg with the
Memory Management Unit.
Both types of instructions transfer 8 or 16
bits and use a type of 16-bit addressing
analogous to the 28002 memory-addressing
scheme: For word operations, Ao IS always
zero; in byte-mput operahons, Ao IS used
mternally by the CPU to select the appropnate
byte; m byte-output operations, the byte is
duplicated m the hIgh and low bytes of the
address/data bus, and external logIc uses Ao
to enable the appropnate output device.
Translate, Decrement/Increment and Repeat
(TRDRB, TRIRB) are the same as TRDB and
Biliography
Selected Publications on the 28000 Family
Z8001lZ8002 CPU Product SpecificatlOn
(00-2045)
Z8000 PLZIASM Assembly Language
Programmmg Manual (03-3055-01)
Z8010 Z-MMU Product Specification (00-2046)
Z8000 CPU Instruction Set (03-8020-01)
410
00-2048-A
An Introduction to the
Z8010 MMU Memory
Management Unit
~
Zilog
Tutorial
Information
March 1981
Introduction
The declining cost of memory, coupled with
the increasing power of microprocessors, has
accelerated the trend in microcomputer
systems to the use of high-level languages,
sophisticated operating systems, complex programs and large data bases. The Z800l microprocessor supports these advances by offering
multiple 8M byte address spaces as well as a
rich and powerful mstruction set. The Z8010
Memory Management Uillt (MMU) supports the
Z800l processor m the efficIent and flexible
use of its large address space.
Support for managmg d large memory can
take many forms:
• Providing a logical structure to the memory
space that is largely mdependent of the
actual physIcal location of the data
• Protecting the user from madvertent
mistakes such as attempting to execute data
Motivations
for Memory
Management
The pnmary memory of a computer is one of
ItS major resources. As such, the management
of thIS resource becomes a major concern as
demands on It increase. These demands can
anse from dIfferent sources, three of which are
of mterest m the present context. The first
stems from multiple users (or multiple tasks
wIthin a dedIcated application) contendmg for
a limited amount of phYSIcal memory. The
second comes from the deSIre to mcrease the
mtegnty of the system by limiting access to
various portIOns of the memory. The fmal
source anses from issues surroundmg the
development of large, complex programs or
systems. Each of these three sources mvolves a
multifaceted group of related issues.
When multiple tasks conshtute a given
system (for example, multiple users of a system
or mulhple sub-tasks of a dedIcated appllcahon), the possibility eXIsts that not all tasks
may be in pnmary memory at the same hme.
(A task IS the achon of executing a program on
ItS data; a task may be as simple as a smgle
• Preventmg one user from unauthonzed
access to memory resources or data
'1'1
• Protectmg the operatmg system from unexpected access by the users.
c:
The Z8010 provides all these features plus
addItional features that permIt a vanety of
system hardware configurations and system
desIgns.
This paper exammes the various uses of
memory management m computer systems and
how memory management techmques generally meet these reqUIrements. The major
features of the Z8010 MMU illustrate how
memory management functions can be supported by hardware. A few examples demonstrate how thIS LSI cIrcuit can be used to
configure several different memory management systems.
procedure or as complex as a set of related
routmes.) If the popuJahon of memory-resident
tasks can vary over hme, a useful feature of a
system would be the abIlity for a task to reclde
anywhere m memory, and perhaps m several
different locatIOns durmg Its lIfehme. Such
tasks are called relocaiable, and a system m
whIch all tasks are relocatable generally offers
greater flexibIlity m respondmg to changmg
system envIronments than a system m whIch
each task must reSIde m a fixed location.
A second Issue that anses m multi-task
envIronments IS that of sharing. Separate tasks
may execute the same program on dIfferent
data, and may therefore share common code.
For example, several users complimg FORTRAN programs may WIsh to share the compiler rather than each user having a separate
copy m memory. Alternatively, several tasks
may WISh to execute different programs usmg
the same data as mput, and It may be possible
for these tasks to access the same copy of the
411
tiC
tiC
-....
~
CI
III
Motivations
for Memory
Management
(Continued)
mput. For example, a user may wIsh to print a
PASCAL program whIle It is bemg compJ!ed;
the prmt process and the compJ!er process
could access the same copy of the text file.
A thIrd issue in multi-task systems IS protectmg one task from unwanted interactions wIth
another. The classIC example of unwanted
mteractJon IS one user's unauthorized reading
of another user's data. ProhibJtmg all such
mteractJons conflicts wIth the goal of sharmg
and so thIS Issue IS usually one of selectively
prohIbiting certa in types of interactIOns. The
Issue of protectmg memory resources from
unauthorized access IS usually mcluded m the
larger set of Issues relatmg to system mtegrity.
System mtegnty takes many forms in additJon to protecting a task's data from unwanted
access. Another aspect IS preventmg user tasks
from performing operating system functJons
and thereby mterruptmg the orderly dIspatch
of these tasks. For example, most large systems
prevent a user task from dIrectly mitiating ,I/O
operatJons because thIS can dIsrupt the correct
functioning of the system.
Another aspect of separating users from
system functions relates to separatmg system
I/O transfers from user tasks, espeCIally wIth
respect to error cond!tJons. For example, an
error during a dIrect memory access, say to a
nonexlstant memory 10catJon, should not cause
an error m the program that is currently
executmg.
A fmal example of mcreasing the system
integnty IS protectmg a user task from Itself.
Obvious errors, such as trymg to execute data
or overflowmg an area set aside for a stack,
can be detected whJ!e a program is executing
and handled appropnately, provIded the
system IS gIven sufhc!8nt mformatJon.
The notion of protectmg an executmg task
from performmg certam types of actJons known
to be erroneous mtroduces a thIrd general
motJvation for memory management, namely
support for the deSIgn and correct implementation of large, complex programs and systems.
The FundaMemory management has two funcbons:
mentals of
the allocation and the protection of memory.
Memory
DynamIC relocabon of tasks during theIr
Management executJon IS accomphshed by an address
translation mechamsm. The restrictJon of
memory access IS accomplished by memory
attribute checkmg. Both operatJons occur WIth
each memory request durmg the execution of a
program and both are transparent to the user.
Address translatJon SImply means treating
the memory addresses generated by the program as logIcal addresses to be interpreted or
translated mto actual phYSICal memory locahons before dispatchmg the memory access
requests to the memory umt. Memory attribute
checkmg means that each area of memory has
assocIated WIth It mformabon as to who can
412
ProtectJng a task from Itself obViously helps in
debuggmg a large program, but there are
other system features that can aid m developing complex systems. Modern methodology for
developmg large systems dictates partJtionmg
a task mto a number of small, Simple, selfcontamed sub-tasks WIth well defmed interfaces. Each sub-task generally mteracts WIth
only a few other sub-tasks and thIS communication IS carefully controlled. ThIS methodology
promotes a systems deSIgn that can be readily
modified, but it also tends to promote the creation of a large number of nearly independent
sub-tasks and many data structures accessible
to only one or a few of these sub-tasks.
Because modern systems are increasingly
driven to support many mteracting tasks,
possibly written and compiled separately, they
must also enforce some communication protocol WIthout sacrificing efficient operatJon.
Modern memory management systems can
offer effective tools for Implementing large
systems designed usmg thIS methodology.
In summary, the major goals of memory
management systems are to:
• Provide fl,?xlble and efficIent allocation of
memory resources durmg the execution of
tasks
• Support multiple, mdependent tasks that
can share access to common resources
• Provide protectJon from unauthonzed or
unintentJonal access to data or other
memory resources
• Detect obviously mcorrect use of memory by
an executing task
• Separate users from system functJons.
Most of today's memory management systems
support these functions to some degree. The
extent of thIS support IS largely a question of
resources to be devoted to these functions and
the understood demands of the mtended
apphcatlOns for these systems.
access It and what types of access can be made
by each task. Each memory reference is
checked to msure that the task has the right to
access that 10catJon in the gIven fashion (for
example, to read the contents of the locabon or
to wnte data to that locabon).
Instead of a linear address space, more
elaborate memory management systems have a
hIerarchical structure in which the memory
conSIsts of a collection of memory areas, called
segments. Access to this structured memory
reqUIres the specJiICation of a segment and an
offset WIthin that segment. Thus,' mstead of
specifymg memory locabon 1050 m a lmear
address space, a task speciflces memory location 5 m segment number 23, for example.
The Fundamentals of
Memory
Management
(Continued)
Generally, segments can be of variable size,
within limits, and a user can specIfy the sIze of
each segment to be used. Thus one user may
have two segments of two thousand and ten
thousand words for his FORTRAN program and
data, respectively, while another user might
have three segments of three thousand, SIX
thousand and two thousand words for her
PASCAL program, data, and run-time stack. If
the hrst user called his data segment number
5, then the first word in hIs data set would be
accessed by the logical address (5,0) indICating segment 5, offset O. The memory management system translates this symbolic name
into the correct physical memory address.
Figure 1 gIves a conceptual realization of
these two users' logical program spaces. The
first user, User A, has hIS program segment
called "Segment 6" and his data segment
called "Segment 5." The second user, User E,
has her program segment called "Segment 5,"
her data segment called "Segment 12" and her
stack segment called "Segment 2." Notice that
both users have named one of theIr segments
"Segment 5," but they refer to dIfferent enhties. ThIS causes no problem smce the system
keeps the two memory areas separate. The
situation IS analogous to both users having an
mteger variable called "I" in theIr programs:
The system reahzes that these are two separate
variables stored m different memory locations.
User A's data segment, "Segment 5," IS ten
thousand words. If he references word 10,050
of Segment 5 he gets an error message from
the system indicating that he has exceeded the
allocation limit for Segment 5. Note that he
does not access word 50 of Segment 6. That is,
segments are logically distinct and unordered.
A reference to one segment cannot inadvertently result in access to another segment.
Thus, m this example, User A is prevented
from accidentally (or deliberately) accessing
hIs program as though it were part of his data
segment.
Figure 2 illustrates one way that these
segments could be arranged m the physical
memory. The dotted lines indicate the
memory-mapping function from the logical
address space of the user to the physical memory locations allocated to him.
The figure also mdicates the access attributes associated wIth each user's segments.
For example, program segments are "execute only" and data segments are "read/
write." Thus a user is prevented from executing a data segment or writing mto a
code segment.
LOGICAL ADDRESS SPACE
PHYSICAL
MEMORY
EXECUTE
ONLY
A.SEG
e
PROGRAM
READ/WRITE - - - - - ___ _
,,
,,
'\
USER A
,,
A.SEQ !i
DATA
/
,,
SEQ,a
PROGRAM
/
/
/
/
'/ 4
/ ' I,
/
/,'I"
/
I
/,
/
/1
1
I,
I
,
SEG. !;
,
,
I
/
I
/
EXECUTE/
DATA
ONLY
/ I
I
,
I
/'
,
1
I
/
f
,I
,
I, " 'II
I
/ r"
1
, , ,
I I
I I
...
I I
READ/WRITE I
,
B.SEG2 "/' ...... ,'STACK
USER B
I
'
"
''-
SEG.5
PROGRAM
5EO.12
DATA
SEG 2
STACK
Figure 1. Two User's Logical Address Space
2049·0075, 0076
Figure 2. Mapping Logical Segments to Physical Memory
413
The Fundamentals of
Memory
Management
(Continued)
Figure 3 illustrates what happens when
both users have access to the same data
set in pnmary memory, say the results of a
queshonnaire that both intend to analyze.
Each user has a logIcal name associated
with that data set to specify the segment in
which the data set IS to reside. Note that the
two users have chosen to put the data set in
different segments of their personal address
spaces. The system-mappmg funchon translates these dIfferent segment names to the
same physIcal memory locahons. Thus User
A's access to address (2, 17) references the
same physical memory location as User B's
access to address (7, 17). In the figure, note
that two of B's segments have been moved in
physical memory to create a space large
enough to hold the questionnaIre data.
Another tOPIC m memory management that IS
supported by 28001-28010 archItecture but
reqUIres addlhonal support hardware is
demand swappmg, or segmented virtual
memory, whIch means that the logical memory
EXECUTe
ONLY
A
seQ. 6
PROGRAM
READ/WRITE
',READ ONLY
"-
,,
,,
SHARED
,
SEGMENT
A SEa 2
'-
QUESTION
NAIRE
A. SEa 5
DATA
I
I
I
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"
I
'- I
)"'-
_--- I
I
"I
I
I
I
I
I
I
I
I
I
,
I
I
I
"
I
I
"
READ ONLY
EXECUTE.....
ONLY
8 SEG 7
" " QUESTION
',,~
"-
,
NA1RE
~
BSEG5
PROGRAM
"-
"
'- "-
"READ/WRITE"""
B SEG 2
STACK
\
..... '-
',
.........."'-
......
\
\
..... ,
'~ ....
\
\
\
\
\
\
\
\
\
\
\
\
\
\
......
\
\
\
'\, "
\ ....... ,~
',\
\
\
\
\
\
Figure 3. Two Users Sharing a Common Segment
414
area may not actually reside m physical
memory until a task actually tries to access it.
At the hme an access is made to a segment
mIssing from phYSIcal memory, the instruchon
execution is held m abeyance unhl the logical
memory can be brought mto the physical
memory and then the mstruchon is allowed to
proceed with the memory access. The address
translation is performed, access protection is
checked and the instruchon proceeds as if the
logical memory area had been in the physical
memory at the beginning of the instruction.
The instruchons in the 28001 must run to completion before the CPU can perform any
achon, such as responding to a missing segment trap. But WIth the conjunction of hardware and software to simulate the above funchons, a segmented virtual memory scheme can
be implemented.
A final tOPIC m memory management is
pagmg, which is another method for parhtionmg a user address space and mapping it onto
the physical memory. Paging is most effective
when demand swappmg can be supported.
Essenhally, paging dIvides the logIcal memory
mto fixed-size blocks, called pages. Like
segments, the indIvidual pages can be located
anywhere m the physical memory and a
translation mechanism maps logical addresses
to physICal memory locations. There are two
differences between paging and segmentmg a
logical memory. FIrst, pages are of fixed size
whereas segments are of various sizes. Second,
under paging, the logical memory is still
lmear, that IS, a task accesses memory using a
smgle number, rather than a paIr as m
segmentahon. The major advantage of pagmg
is in treatmg memory as blocks of flxed sizes,
whIch SImplifies allocatmg memory to users
and deCIding where to place the logical pages
in physical memory. The major dIsadvantage
of paging IS in assIgning dIfferent protection
attnbutes to different areas m a user address
space because a paged memory appears
homogeneous to the user and the operating
system. Pagmg can be combined with segmentahon to produce a memory management
system with the advantages of both paging and
segmentation. The Implementation of pagmg
for the 28001 reqUIres addihonal support hardware and may be Implemented mdependent of
the 28010.
Before proceedmg to the mechanism of
memory management, it is instruchve to revIew
how a segmented address translation
mechamsm with protection attributes achieves
the five major goals of memory management
outlmed m the prevlOUS section. The flrst goal
permits dynamIc allocahon of memory dunng
the execution of tasks; that is, a task could be
located anywhere in memory and even moved
about when its executlOn is suspended. The
address translahon mechamsm provIdes this
flexlbihty because the task deals exclUSIvely
2046-0077
The Fundamentals of
Memory
Management
(Continued)
with logICal addresses and hence IS mdependent of the addresses of the physical memory
locations it accesses. Movmg the task to different physical memory locations reqUIres that
the address mappmg function be changed to
reflect the change m memory location, but the
task's code need not be modIfied. Of course,
thIs flexibility does mcur the price of managing the varIOus system tables required to
Implement memory management.
The second goal supports sharing of common memory areas by dIfferent tasks. ThIs IS
accomphshed by mapping different logICal
areas m different tasks to the same physical
memory locations.
The thIrd provides protectIOn against certam
types of memory accesses. ThIS IS accomplished by assoclatmg accessing attributes wIth
each logical segment and checking the type of
access to see if each access IS permItted.
The fourth goal detects obvIOus execution
errors related to memory accessmg. ThIS can
be accomphshed by checking each access to a
segment to see whether the address falls within
the allocated physICal memory for that segment. It could also mclude affixmg a
read/write attribute to data to prevent a task
from trymg to execute a data segment, and
affIxing an execute-only attribute to code
segments to prevent a task from trymg to read
or wrIte data to thIS segment. AddItionally, If a
segment IS used for a stack, the system could
issue a warnmg to a task when the stack
approaches the allocated limIt of the segment.
The task could then request more memory for
the stack before the stack overflows and
creates a fatal error.
The fmal goal hsted for memory manage-
Essentially there are four Issues m impleThe Mechanics of Memory mentmg a memory management system: how
Management addresses are specIfied, how these addresses
are translated, what attributes are checked for
each access, and how the protection mechanism is implemented. Some of the major alternatives in each of these Issues are briefly
discussed here, primarily from the pomt of
view of a segmented memory.
Two approaches have traditionally been
taken for specifymg addresses m a segmented
memory. For sImplicity, only addresses m
mstruchons are dIscussed. The hrst way
puts all the addressmg information in the
mstruction itself. That is, each memory address
m an instruction con tams both the segment
name and the offset wlthm the segment. The
alternahve sets aside speCIal registers that contam some of thIS mformation, for example the
segment name or the address in physical memory where the segment resIdes.
The advantage of the latter approach hes m
the fact that fewer bIts are needed in an
instruction to specify addresses. Thus programs may be shorter. Also, because there IS
ment systems separates user functions from
system functions. For processors that dlstmguish between System mode and User mode
of operation, this goal can be accomphshed by associating a system-only attribute
with system segments so users cannot directly
access system tables and tasks.
As a final pomt, it should be noted how
segmentation can be used to support the
development and execution of large, complex
programs and systems. The concept of segmentation corresponds to the concept of partitlonmg a large system mto procedures and data
structures where each procedure and data
structure can be assocIated with a separate
segment. A task can then invoke a procedure
or sub-task or access a data structure by referring to ItS logIcal segment name. Access to
these objects can be mdlvldually restricted by
usmg the protectlon-checkmg mechanism of
the memory management system.
As a speclhc example of how segmentation
could be used m the desIgn of a large system,
consider a multi-user mteractive BASIC system
with a large data base shared by all users.
Such a system could be desIgned wIth
segments 0 through 15 reserved for system
use, segments 16 through 31 reserved for the
BASIC mterpreter and ItS mternal tables,
segments 32 through 63 allocated to user tasks
and segments 64 through 127 reserved for portions of the data base when they are m primary
memory bemg accessed by users. For this
system, segments 0 through 31 would probably
always be in memory; the other segments
would be assigned as needed and the memory
they reqUIre allocated dynamICally.
reduced traffIC between the memory and the
processor for fetchmg shorter mstructlons, a
program may execute faster.
On the other hand, these specIal regIsters
must be manipulated to access more segments
than there are registers, and thIS mampulahon
adds to the number of instruchons, the program size and the execution hme. In practice,
these can destroy the advantages described
above. If the special regIsters contam phYSICal
memory locahons, then these must be protected from user access to maintain the integrity of the system, and changmg segments
requires system calls whICh can be hme consuming If too few regIsters are supphed. The
Z8001 archItecture specifies the complete
logical address m the instruction.
Address translahon is performed by addmg
the logICal segment offset to the memory location where the segment begms. Thus, when an
address of the form (a, b) IS presented to the
translahon mechamsm, the segment name "au
IS used to determme where segment "aU
resides in memory. Assume that It resides m
locahons 10000 to 25000. Then the actual
415
The Mechan- memory location of (a, b) is memory location
ics of Memory 10000+b. The major option in implementing
Management this type of address translation is in determin(Continued)
ing the segment location in physical memory.
When special registers have been set aside to
contain the starting location of the segment
instead of putting all address information in
the instruction, the addressing mechamsm IS
similar to using the segment register as an
index register or a base register.
When logical addresses are either completely specified in the instruction or when the
special register contains the symbolic segment
name, a table must be used to translate the
logical segment name into a physical memory
location. The table may have an associative
capability, that is, the segment name is
presented to the table and the device returns
the physical memory location where the segment begins. Alternatively, the table could
have one entry for every possible segment
name. The Z8010 implementation of the
address translation table sets aside a specific
table entry for each logical segment name.
A number of attributes can be associated
with a segment and checked during each
access. One of these is the allocated length of
the segment, and each access is checked to
see if it falls within the bounds of the segment.
The Z8010 provides limit checking.
Another type of attribute deals with ownership or class of ownership: tasks are grouped
into classes and only those in certain classes
are permitted access. The simplest example is
the system versus user classification, where
tasks are either one or the other and this determines whether or not any type of access can
be made to the segment. The Z8010 has this
feature-users are prevented from accessing
system segments.
Other types of attributes that can be
associated with a segment involve modes of
accessing, for example read only, reael/write
or execute only. For these attributes, the processor must indicate the type of access to be
made, be it code fetch, read from memory,
write to memory, etc. The Z8001 indicates
when it is fetching code, reading or writing
data, or performing stack operations, and thus
the Z80 10 can offer protection for these opera-
tions. The other issue with respect to attributes
is whether they are permissive or prohibitive.
That IS, whether the attribute is in the form of
"write to this segment is permitted" or of the
form "write to this segment is prohibited." The
Z8010 adopts the approach of specifying attributes that prohibit certain types of accessing.
The final issue in the mechanics of memory
management systems is the implementation of
the protection attributes. These may be
associated either with the logical address
space or with the physical memory itself. The
IBM 360 series, for example, places the
memory protection information with the
physical memory itself. Thus the processor
generates a memory address and the memory
module checks to see if the access is permitted. The main difficulty with this approach is
in the lack of flexibility, because protection is
associated with fixed memory partitions. Also,
sharing memory is cumbersome because each
user is given a protection key to match the
memory key; thus both users must have the
same access key or a universal access key.
ASSOCiating access attributes with the logical
segment permits a versatile memory management scheme because different users can
access the same segment and have different
access attributes associated with their accessing. The Z8010 implements access attributes
using the segment mapplIig information.
Other information associated with each segment does not pertain to the protection
mechanism but can be of use to the memory
management system. This information generally relates to the history of the segment; for
example, whether a segment has been
modified while resident in primary memory. If
it has not been modified and the system
reqUires the memory for another segment, the
memory can be freed immediately; otherwise,
the updated version of the segment must be
stored in secondary memory and the primary
memory is not available until the segment has
been saved. Although not strictly necessary,
such information can improve the performance
of the memory management system. The Z8010
collects information on segment usage, and
thiS information can be used to enhance performance of systems that use this device.
The Z8001 CPU generates segmented
The Z8010
addresses conSisting of a 7-bit segment number
Memory
Management and a 16-bit segment offset address. In addi-
some detail, beginning with the translation
procedure and continuing with a deSCription of
the internal registers of the chip. The section
concludes with a deSCription of the system
commands that alter the contents of these
registers.
The Z8010 MMU has three functional states.
The first is the memory management state:
when a logical address is presented to the unit,
the MMU checks the access to Insure ItS validity and translates the logical address to a
physical memory location. The second state IS
a command state: when a speCial I/O instruc-
Unit
416
tion, the CPU generates status Signals indicating ItS current mode of operation (such as
Instruction Fetch, Data Memory Reference,
Stack Memory Reference, and Internal Operation), whether it is performing a Read or a
Write Memory Reference and whether it is In
Normal (User) or System Mode. The Z8010
Memory Management Unit uses this information to perform ItS memory management functions. This section describes the Z8010 MMU in
The Z8010
Memory
Management
Unit
(Continued)
tion IS issued to the MMU, such as reading or
writing one of ItS internal regIsters, the MMU
responds to the command as appropriate. The
thIrd state is a quiescent state: when the CPU
issues an I/O instruchon or a refresh cycle, the
MMU address lmes remam 3-stated.
The inputs to the MMU are the Address/Data
lines (AID lines), Segment Number hnes, Bus
Status and TIming Lines, and special control
lines for chip selechon and DMA. The outputs
from the MMU are Address lmes, a Segment
Trap line and a Suppress lme (Figure 4). During address translation and access protection,
logical addresses are presented to the MMU on
the Segment Number and Address/Data lines;
the MMU puts the translated physICal memory
location on ItS Address lmes and, if appropriate, activates the Segment Trap and/or Suppress lmes.
Segment Trap IS a speCIal type of synchronous interrupt for the 28001 CPU; Suppress aborts the memory access. In the command state, the MMU receIves commands on
the AID lmes; data to be read from or written
mto the MMU IS also placed on the AID lmes.
The MMU selects whICh of the three states It
WIll be m according to the status mformahon
on the Bus Status lmes durmg the Imtial clock
cycle of an mstruchon or DMA cycle. The
MMU performs address translahon during a
memory reference for eIther a regular mstruction or a DMA request. Only I/O mstructions
(eIther regular or specIal), memory refresh and
reserved bus status states cause the MMU to
cease performing memory address translahons
and enter another state.
The MMU uses the segment number to
access an mternal table of segment deSCriptor
registers, each register containmg the startmg
memory locatIOn of the segment (called the
base address), the segment's hmit (used to '
df:,ermme the range of legal address offsets)
and the types of accesses permItted to that
segment.
PhysICal memory for segments IS allocated m
blocks of 256 bytes. The eIght least significant
bIts of the base address are all zero and are
not stored m the Segment Descriptor RegIster.
Also, smce the eight low-order bIts of the segment base are always zero, the eIght low-order
bits of the segment offset need not participate
6
I
PHYSICAL
ADDRESS
Z8010
MMU
SEGMENT
TRAP
SUPPRESS
DMAISEQMENT ----.. DMASYNC
R,iN
NIS
BUS TIMING
{
_AS
~
)
5T2
STATUS
ST,
CHIP SELECT - - - .
cs
e
....
=S'
+5V GND el.K RESET DECOUPLE
in the addlllOn of the base address to the offset. Rather, they can be juxtaposed to the
result of adding the high-order byte of the offset to the most slgmficant 16 bIts of the base
address.
ThIs process IS illustrated m Figure 5. Note
that the low-order eight blls of the offset are
not used by the MMU. Figure 6 goes through
an example of mapping the logICal address
(5, 1528) to a physIcal memory locahon when
segment 5 begms at locahon 231100.
FIgure 6a illustrates the full addition to be
performed durmg address translation. The segment number 5 selects Segment DescrIptor
Register 5 m the MMU. The base address held
m this regIster contams 2311 whICh corresponds to a base address of 231100. The offset,
1528, is then added to 231100 to produce the
physICal memory location 232628. FIgure 6b
represents the same logICal procedure, but
Illustrates the actual operahon of the MMU.
Agam segment number 5 IS used to select the
base address. However, only the high-order
byte of the offset IS added to the contents of the
a
l/1"
F--_______________ I ~ ~J. ~ ~ ~ J.~ ~ ~ J~ ?:~~~~~~T
.,6 7_ - - - - - - - - - - - - - -
J.
J.
J.
J.
STARTING ADDRESS
J.
+
I..I________________--L._ _ _ _ _ _ _ _--II
PHYSICAL MEMORY LOCATION
Figure 5. Generation of the Physical Memory Location from a Logical Address
2046-0051
2049-0079
DI
Figure 4_ Z8010 MMU Pin Functions
[, _ _ _ _ _ _ _ _0_FF
...
;5_ET_ _ _ _ _ _ _ _....1 LOGICAL ADDRESS
BASE ADDRESS
~
iii
ST,
15
SEGMENT NUMBER
....--
ST,
os
417
The ZSOIO
Memory
Management
Unit
(Continued)
MMU base-address field: 15 is added to 2311
to produce the most significant 16 bits of the
physical memory location. The low-order byte
of the physical location is the same as the loworder byte of the offset.
The results of the two processes illustrated in
figures 6a and 6b are the same, but in 6a a
24-bit addition is implied whereas in 6b only a
16-bit addition is needed. Also, the low-order
eight bits of the offset are not needed by the
MMU and this reduces the number of pins
required by the MMU package.
The MMU checks memory references for two
types of trap conditions. The first type is an
access violation. This occurs when a memory
reference is performed in a mode that is not
allowed by the read-only, execute-only, CPUinhibit or system-only attribute of a segment. A
memory reference outside the allocated
memory for the segment also constitutes an
access violation.
The second type is a write warning. This
occurs when a write is made to the last 256
bytes of a special type of segment (indicated
by a special attribute flag called the Direction
And Warning Flag). These segments are
typically used for stacks and are therefore
logically organized so that successive writes
(or stack pushes) access lower-numbered
memory locations. By generating a segment
trap request when a write is performed into the
lowest-numbered 256 bytes of the memory
allocated for these segments, the MMU is
signaling that a stack is in danger of overflowIng. The operating system in serVICing this
trap can increase the memory allocated for the
segment and avoid a fatal stack overflow
condition.
The MMU generates two control signals that
can be used by the system to perform memory
management functions. Segment Trap Request
IS generated upon the first detected occur-
rance of a violation or write warning. Once
asserted, this signal remains set until a trap
acknowledge signal is received. Only when the
Fatal Flag, a special MMU control flag, is set
will a detected violation not cause a segment
trap request. This flag is set only when a
second violation is detected while a previous
trap is being processed and thus indicates that
the system software is in error.
The other control signal generated by the
MMU is Suppress. Once a violation has been
detected, this signal is asserted on that and
every succeeding memory reference for the
remainder of the instruction. In particular, I/O
and Special I/O instructions are checked for
memory access VIOlations, and once a memory
access violatIon is detected, subsequent
memory accesses cause Suppress signals to be
generated. I/O addresses, of course, bypass
the MMU and are neither translated nor
checked. Intervemng DMA cycles and memory
refresh cycles are exceptions to this rule. DurIng such cycles Suppress is not asserted unless
a violation is detected during that cycle. Only
DMA can generate a VIOlatIon; refresh can
never cause a VIOlation. Suppress can be used
by the memory system to inhibit writes, thus
protecting the memory from illegal alterations.
MMU
Internal
Registers
There are three groups of registers in the
MMU: . Segment Descriptor Registers, Control
RegIsters and Status Registers. The Segment
Descriptor Registers contain all the information
relating to the address translation and access
protection of a particular segment. The Con-
trol Registers contain information used to control the various functions of the MMU, including how to Interpret various signals generated
by the CPU. The Status Registers contain all
the information the MMU generates when It
detects an access violation.
Segment
Descriptor
Registers
Because there are 64 Segment Descriptor
RegIsters in the MMU, two MMUs are required
to handle all 128 segments that the 28001 can
mampulate dIrectly. An MMU is programmed
to handle either segments 0 through 63 or
segments 64 through 127; the particular set of
64 segments In an MMU can be changed uSing
speCIal operating system commands. Each Segment Descriptor contains three fields, a 16-bit
Base Field, an 8-bit Limit FIeld and an 8-bit
Attribute Field (Figure 7). The segment
number of a logical address determines which
segment descriptors are used in address
translation.
The Base Field speCIfies the starting location
in memory of the segment.
The Limit Field specifies the segment size in
blocks of 256 bytes. The address offset is compared against the segment limit and a size
violatIon occurs if the offset falls outside the
segment boundaries. A write warning occurs if
the destination is in the last block of a segment
being used as a stack.
418
o
b
0
0
,~
1',_,2,81
bJ~~
\
\
\
\
23
I
87
2 , 3 , 1 , 1
23
0
I ~=~J
2
3
,
'I
1
. ' , , .
+
+
23
0
12,3,2,8,2,81
8) FULL ADDITION
8
\
,
I
I
I
I
I
I
8/7 0'
I_ 2 ' 3 , 2 , 8 Ir;-;l
.L:....L..:...J
23
b) ADDITION OF HIGH ORDER
BYTES ONLY
Figure 6. Two Methods 01 Address Translation
2049-0080
Segment
Descriptor
Registers
(Continued)
BASE ADDRESS
LIMIT
BASE FIELD
LIMIT FIELD
v
ATTRIBUTE FIELD
Figure 7. A Segment Descriptor
The Attribute Field contains eight flags. Five
flags protect the segment against certain types
of access, one mdlcates a speCial orientation of
the segment, and two indicate the types of
accesses that have been made to the segment.
The following brief description explains how
these flags are used.
The Read-Only Flag (RD) indicates that the
only accesses to this segment are reads. Writes
are prohibited when this flag IS set. Thus this
flag is a write-inhibit flag; in particular, code
can be executed from a read-only segment.
This flag is useful in protecting data from
being written by unauthorized users. For
example, if one user wants to give another
access to a document that he has created, but
does not want this user to be able to modify it,
the system can set the Read-Only Flag when It
copies the file into the user's address space. If
the data is already in memory (in a read-only
mode), then this same memory area can be
made accessible to that user without another
copy of the document being required.
The System-Only Flag (SYS) indicates that
only accesses made in System Mode are to be
permitted. When this flag IS set, accesses in
the Normal Mode are prohibited. ThiS attribute
is useful in protecting system tables and tasks
from being accessed by users. For example,
system I/O routines can be left m the memory
with this flag set. and a user is unable to call
them directly. This feature is useful if a system
is designed so that users are given certain segment names and other segment names are
reserved for system use. This flag prevents
users from accessing system segments, even
though they can generate the logical
addresses.
The CPU-Inhibit Flag (CPUI) indicates that
the segment IS not to be referenced by the
CPU. When this flag IS set, CPU access to this
segment is prohibited, but DMA channels can
access the segment. ThiS flag is useful m
preventmg a program from accessing a segment whose data resides on secondary storage
and has not been brought into primary
memory. For example, a user may request the'
operating system to read a hie from disk into
segment number 19; If the operating system
returns control to the user before the file has
been read, this flag should be set in Segment
Descriptor Register 19.
The Execute-Only Flag (EXC) indicates that
the segment is to be referenced only durmg
the mstruchon fetch cycle of the processor.
When this flag is set, access to the segment
during any other cycle of an instruchon, for
example during the memory request cycle, is
2049·0081
prohibited. This flag is useful in preventing a
program from making a copy of a proprietary
program. For example, if this flag is set for a
segment con taming code that a user can
access, that code is protected from being read
and hence from being copied.
The DMA-Inhibit Flag (DMAI) indicates that
the segment is not to be referenced by a DMA
Channel. When this flag is set, only the CPU
has access to the segment. This flag is useful
in preventing a DMA device from modifying a
segment being used by an executing task. For
example, segments with valid data should have
this flag set to protect them from modification
by a DMA device.
The Direction And Warning Flag (DIRW)
indicates that memory accesses are to be
momtored and certain accesses are to be
signaled, although allowed to proceed. When
this flag is set, any write to the lowest 256
bytes of the segment generates a write warning. ThiS flag is useful for segments that are
used as stacks since the 28001 has special
stack instructions to manipulate stacks that
grow toward lower memory locations. Thus a
write warning for a stack indicates that the
stack may soon overflow its allotted memory
space and that more physical memory should
be obtained. For example, if a segment serves
as a run-time stack for a block-structured programming language such as PASCAL, memory
can be allocated to thiS segment only as a program requires during ItS execution. The alternahve in a fixed allocation environment is to
allocate as much memory for the stack as the
system expects the program to need, whether
or not it is actually used by the program.
The Changed Flag (CRG) indicates that a
write has occurred to thiS segment. This flag is
set automatically whenever a program or DMA
device writes into the segment. This flag is
useful in indicating which segments have been
modified in the case where the segment must
be written to a secondary storage deVICe.
Segments that have not been updated need not
be copied back to disk if a copy already exists.
For example, when a user task is suspended in
a multiple-user environment and his task is to
be swapped out of memory temporarily to
make room for another task, only those
segments that have been changed need to be
updated on the disk.
The Referenced Flag (REF) indicates that a
memory access has been made to a segment.
ThiS flag is set automaticaly whenever a program or DMA device accesses the segment.
This flag IS useful in indicating which segments
are active m the case that a segment must be
419
i
iE
CI
Segment
Descriptor
Registers
(Contmued)
selected to be swapped out of primary memory
to make room for another task. For example,
seldom-used operating-system tasks that usually reside m primary memory may be swapped
out to make room for users with large memory
reqUIrements. This flag IS a way of ascertaining
which segments contain seldom used tasks.
Control
Registers
Three user-accessIble 8-blt registers in the
MMU control the functionmg of the MMU
(Figure 8). The Mode RegIster provides a
sophisticated method for selectively enabling
MMUs m a multiple-MMU configuration. The
Segment Address Register (SAR) selects a particular segment deSCrIptor to be accessed by a
system routine when it is changing the
organization of primary memory. The Descriptor Selection Counter Register selects the particular byte in the Segment Descriptor Register
that is accessed.
Two flags in the Mode Register govern the
functioning of the MMU. The Master Enable
Flag (MSEN) indICates whether the device will
perform address translahon. When this flag is
set, addresses translated by the MMU are
placed on ItS Address lines; when thIS flag IS
clear, the Address lines are 3-stated. Thus,
once thIS flag IS reset, no memory request can
pass through the MMU. In a single-MMU configuration, MSEN set to zero requIres that the
CPU must have access to a special memory,
since it WIll not be able to fetch an mstruction
from the prImary memory. This flag can be set
durmg hardware reset (this IS dIscussed later).
The second flag in the mode regIster that
governs the funchonmg of the MMU IS the
Translate Flag (TRNS). This flag mdlCates
whether the MMU IS to translate the addresses
present~d to It. When the flag is set, the MMU
translates logIcal addresses to physical memory
locations and checks to see If a violation will
occur on that access. When the flag is clear,
addresses presented to the MMU are passed to
the output Address lines WIthout change, and
no protechon checking is done.
When multiple-MMUs are used m a memorymanagement system, some mechanism must be
present to select those deVICes that are to be
active durmg the memory translahon process.
More speCifIcally, If two MMUs are employed
so that all 128 segments can be used at random
by an executmg process, then some way must
exist for each of the MMUs to know which 64
Segment DeSCrIptors are located in ItS Segment
Descriptor RegIsters. The Upper Range Select
Flag (URS) mdlCates which set of 64 descriptors is stored m the MMU. When the flag is
set, the MMU contains descriptors 64 through
127; when the flag IS reset, the MMU contains
descriptors 0 through 63.
When mulhple-MMU deVICes keep separate
tables for system descriptors and user descriptors, the Mulhple Segment Table Flag (MST)
and the Normal Mode Select Flag (NMS) in the
Mode Register dlstmguish which MMUs contam system descriptors and which contain user
descriptors. When the MST flag is set, multiple
tables are present in the configuration, and
each MMU IS dedicated to one of the tables. In
this case the MMU translates addresses only
when the Nis SIgnal matches the NMS flag.
Thus, If there are two tables in the memory
management system (one for the system and
one for users). the NMS flag is set in those
MMUs containing the users' segment descriptors, and IS not set in the remainmg MMUs. All
MMUs m the system have the MST flag set to
indicate more than one table m the system.
The final piece of control informahon in the
Mode Register is a 3-bit Identification Field
(ID) that indicates a logical name for the
MMU. When a segment trap is acknowledged
by the CPU, the MMU uses this field to select
one of the AID lmes; each enabled MMU
should select a dIfferent line. If an MMU
requested a segment trap, it outputs a I on its
assigned AID line; otherwise it outputs a O.
Smce the ID fIeld IS three bIts, up to eight
MMUs can be uniquely identified. One
instruchon mIght result in multiple violations
in dIfferent MMUs, so that the segment trap
software might have to deal WIth several MMUs
to process the trap.
The other two control registers in the MMU
are the Segment Address RegIster (SAR),
which points to one of the 64 segment deSCrIptors, and the DeSCrIptor Selection Counter
Register. Commands to read or write a segment deSCrIptor use the SAR pointer to select
which descriptor IS to be accessed. This
register has an auto-incrementing capability
for accessing consecuhve descriptors m successIon WIthout having to reload the SAR. Thus
If deSCrIptors 0 through 4 are to be modifIed,
the SAR IS InItialized to 0 and then autoincremented to point to descriptors, I, 2, 3
and 4 in succession.
The Segment Descriptor Number is a 6-bit
field that con tams the address of the descriptor
WIthin the MMU. If the MMU holds segments
64 through 127 (that IS, If the URS flag IS set),
the segment named 64 is accessed when the
SAR number field is O. ThIS IS a result of the
6-bit limit of the descriptor number field. The
field indicates the 6 least-significant bits of the
logical segment descriptor number.
7
32
0
TR_N..L5_uR_sJ...1M_S_TIL...N_MS...LI_"-'D-'----'I
L.E_SE...J1_
6 5
MODE
0
ISEGMENT DESCRIPTOR NUMBER I SEGMENT
!
!
!
!
21
I
ADDRESS
!
0
I ~~~ENC:~~N
DESCRIPTOR
' - - - ' - - " " _ " - - - ' - - - ' _..._D'-~C--'
Figure 8. MMU Control Registers
420
2046·0031
Control
Registers
(Continued)
Segment DescrIptors consIst of four bytes;
the Descriptor Selection Counter indICates
which byte is bemg accessed durmg a command (commands to the MMU can read or
write only one byte at a time). A counter value
of 0 mdicates the hIgh-order byte of the base
address is bemg accessed, I indicates the loworder byte of the base address, 2 indICates the
hmit field, and 3 mdICates the attribute held.
ThIS counter is used by MMU commands that
access multiple bytes wIthin a descriptor. In
general. the counter is handled automatically
by the MMU commands. Only when a command could be interrupted-and mtervening
MMU commands issued-should this register
be saved and later restored by the mterrupting
program.
Status
Registers
Six S-blt regIsters contain mformation useful
m recovermg from memory trap conditions
(FIgure 9). The Violahon Type RegIster
describes the conditions that generated the
segment trap. The VlOlahon Segment Number
and Offset Registers con tam the segment
number and upper byte of the segment address
offset for the logical address that caused
the segment trap. The Instruchon Segment
Number and Offset RegIsters contam the segment number and uper byte of the segment
address offset for the last mstructlOn before the
segment trap was issued. The Bus Cycle Status
RegIster records the status of the bus at the
hme the trap condlhon was detected.
Only violahons caused by CPU access have
trap mformahon stored m the status registers;
DMA violahons cause Suppress to be asserted,
but the Status Registers are not altered. Thus If
a DMA VIolation occurs between a CPU vlolahon and entry to the trap servICe rouhne, the
serVICe routme shll has the CPU trap information avaIlable to process the trap. It IS the
responsiblhty of the DMA deVICe to save
enough information m the event of a vlOlahon
so that a software DMA vlOlahon service
routine can process the violation correctly.
Eight flags m the Violation Type RegIster
deSCribe the cause of the segment trap. Four
flags correspond to access protectIOn modes m
the segment deSCriptor attrIbute mode. A readonly vlOlahon sets the RDV flag, a system-only
vlOlahon sets the SYSV flag, a CPU access to a
CPU-InhIbIt segment sets the CPUIV flag, an
execute-only vlOlahon sets the EXCV flag.
Three flags correspond to addressmg vlolahon or warnmgs. The Segment Length VlOlahon Flag (SL V) IS set whenever the offset of the
logICal address falls outside the memory space
allocated to the segment. The Primary Write
Warnmg Flag (PWW) IS set whenever a write
occurs in the last 256 bytes of a segment whose
Direchon And Warnmg Flag IS set (that IS, for
segments being used as stacks where the top of
the stack is withm 256 bytes of the allocated
memory space of the segment). The Secondary
Write Warnmg Flag (SWW) is SImIlar to the
PWW flag, only it is set when the CPU is m
system mode, a stack push IS being performed
to a segment WIth a Direction And Warnmg
Flag set, and some other addressmg VIOlation
or warning has occurred (the EXCV, CPUIV,
SLY, SYSV, RDV or PWW flags have been
set). When the SWW flag IS set It indicates
that the system stack is in danger of overflowmg its allotted memory. Once the SWW flag is
set, further write warmngs are suppressed.
ThIs prevents the system from repeatedly
bemg interrupted for the same warnmg while
it is in the process of ehmmating the cause
of the warning.
The final violahon-type regIster flag to be
dIscussed is the Fatal Condlhon Flag (FATL).
ThIS flag IS set when any other flag m the
violahon type register is set and eIther a vlOlahon IS detected or a write-warning condlhon
occurs in normal mode. ThIS flag IS not set
durmg a stack push m system mode that
results m a warning condihon. ThIS flag
indICates that a memory access error has
occurred in the trap processmg rouhne. Once
thIS flag has been set, no Trap Request signals
are generated on subsequent vIOlations.
However, Suppress SIgnals are generated on
thIS and subsequent CPU violations unhl the
FATL flag has been reset.
The Bus Cycle Status RegIster con tams informahon pertaining to the status of the bus when
a trap condition is detected. This includes
CPU Status (STo-ST3). plus flags mdicatmg
whether a read or a write was being performed
and whether or not the Nls Ime was asserted.
The Violahon Segment Number and Offset
RegIsters record the hrst logical address to
cause a trap. Only the hIgh-order byte of the
offset IS saved, however, so that external support cIrcuItry IS needed to save the low-order
eIght bIts of the logical address offset. If the
trap occurred durmg the instruchon fetch
cycle, thIS mformation is the logical address of
the mstruction; otherwise it indICates the
2046-0032
7
,
I
IFATLISWWlpwwlExcvfpUlvl SLY ISYSVI ROV ~~~~ATION
7
,
I I
I ~~~~~=T
VIOLATION
1..._'--,_-,-5_EG,-.
M_EN....L~_NU_M"-~E_R--'-----'----I.
UPPER OFFSET
I
~~~~~~~~
7
VIOLATION
OFFSET
,
'I
I ~~~~~~i'ON
I----'._-'--'-----',_-'---'-----'---1.
SEGMENT NUMBER
1....
NUMBER
I
'---'----""_U'-~P_ER....L?_F_FS"-;r_'---'--___'.
INSTRUCTION
OFFSET
Figure 9. MMU Violation Information Registers
421
~
II
II
c:
....e.~
o
Status
Registers
(Continued)
logical address of a data item whICh was to be
accessed.
The Instruction Segment Number and Offset
Registers record the logical address of the last
mstructlon fetch that occurred before the trap.
Only the high-order byte of the offset is saved,
however, so external support circuitry is needed to save the low-order eight bits of the offset.
If an instruction fetch caused the trap, these
registers mdicate the logical address of the
prevIous instruction. Such mformation IS useful
If the precedmg instruction was a branch
instruction to an invalid address since-in this
case-these registers indicate which branch
instruction led to the erroneous situation. If a
data reference caused the segment trap, then
these registers indicate the logical address of
the instruction that specified the illegal access.
Stack
Segments
Segments are speCified by a base address
and a range of legal offsets to this base
address. On each access to a segment, the offset is checked agamst this range to insure that
the access falls within the allowed range. If an
access outSide the segment is attempted, a
Trap Request and a Suppress signal are
generated.
Normally the legal range of offsets Within a
segment is from 0 to 256N +255 bytes, where
O::;N ::;255. (N IS the value in the limit field of
the segment descriptor.) However, a segment
may be speCIfied so that legal offsets range
from 256N to 65,535 bytes, where 0::;N::;255.
The latter type of segment is useful for stacks
because the 28001 stack-manipulation instructions cause stacks to grow toward lower
memory locations. Thus, when a stack grows to
the limit of Its allocated segment, additional
memory can be allocated on the correct end of
the segment. As an aid in maintaining stacks,
the MMU detects when a write is performed to
the lowest allocated 256 bytes of these
segments and generates a Trap Request. No
Suppress signal is generated so the write is
allowed to proceed. This write warning can
then be used to indicate that more memory
should be allocated to the segment.
The DIRW flag indicates that a segment is to
be treated in this special way by the MMU.
When the DIRW flag is set, the range of
allowed offsets is from 256N to 65,535 bytes
and writes into the range 256N to 256N + 255
generate Segment Trap but not Suppress,
indicating a write warmng.
Segment
The 28010 MMU generates a Segment Trap
Trap and
whenever it detects an access VIOlation or a
Acknowledge write warmng condition. In the case of an
access Violation, the MMU also activates Suppress. Suppress can be used to mhlblt memory
writes and to request that special data be
returned on a read access. Segment Trap
remams Low until a Trap Acknowledge signal
is received. If a violation occurs, Suppress is
asserted for that cycle and all subsequent CPU
memory references until the end of the instruction. Intervenmg DMA cycles are not suppressed, however, unless they generate a
violation. VIOlations detected during DMA
cycles cause Suppress to be asserted during
that cycle only; no segment trap requests are
ever generated during DMA cycles. This IS
because the CPU would not be able to respond
to these traps until the conclUSIOn of the DMA
cycle.
Segment traps to the 28001 CPU are handled
Similarly to other types of mterrupts. To service a segment trap, the CPU enters a segment
trap acknowledge cycle. The acknowledge
cycle IS always preceded by an instruction
fetch cycle that IS aborted. The MMU has been
deSigned so that thiS dummy mstructlon fetch
cycle IS Ignored. Durmg the acknowledge
cycle, all enabled MMUs use the AddresslData
lmes to indicate their status. An MMU that has
generated a Segment Trap request outputs a 1
on the AID line associated with the number in
its ID field. An MMU that has not generated a
segment trap request outputs a 0 on its
assoCIated AID line. AID Imes for which no
MMU is associated remain 3-stated. During a
segment trap acknowledge cycle, an MMU
uses AID line 8 + i If the content of Its ID
field is i.
Followmg the acknowledge cycle, the CPU
automatically pushes the program status words
and program counter onto the system stack,
and loads a new program status word and program counter from the program status area.
The Segment Trap lme IS reset during the segment trap acknowledge cycle, and no Suppress
signal IS generated during the stack push. If
the store creates a write warning condltlon, a
segment trap request is generated and is serviced at the end of the context swap; the SWW
flag is also set. ServICmg thiS second Segment
Trap request also creates a write warmng condition, but-because the SWW flag IS set-no
Segment Trap request IS generated. If a violation rather than a write warning condition
occurs during the context swap, the FATL flag
is set rather than the SWW flag. In thiS case,
subsequent VIOlations cause the Suppress to be
asserted but not Trap Request. Without the
SWW and FATL flags, trap processing routines
that generate memory violations would
repeatedly be interrupted and called to pro-
422
cess the viola lions they create.
Segment
The CPU routine to process a trap request
Trap and
Acknowledge should first check the FATL flag to determine
(Contmued)
if a fatal system error has occurred. If not, the
SWW flag should be checked to determine if
more memory is required for the system stack.
Finally, the trap itself should be processed and
the violation type register reset.
Commands
to the MMU
descriptors m the MMU to have the CPUI or
DMAI flags set, respectively. These two set
commands can be useful in InilialIzmg address
translalion tables or when swapping between
tasks. For example, when swappmg between
tasks the Set All CPUI Flags command
automalically makes the previous task's
segments maccessible to the next task, unless
the system expliCItly InilialIzes the segment
attrIbute held m these segments.
As an example of using the SpeCIal Output
mstruchon SOUT to control an MMU, consider
resettmg the fatal flag of MMU #1. The MMU
command opcode for thIS is "%14" (% denotes
hexadecImal). The assembler syntax for the
SOUT instruction IS "SOUT destinalion field,
source held" so that the instruclion to reset the
fatal flag of MMU #1 IS "SOUT %1402, RO."
SpecIfymg regIster 0 In this mstruclion IS an
arbitrary choice-the content of this regIster is
placed on the AID lines during the data phase
of the SOUT instruclion, but It is ignored by
the MMU. The low-order byte of the command
(the destmalion held of the mstructIon) encodes whICh MMU IS to reset ItS fatal flag. The
convention followed In this paper is that MMU
I is speCIfIed by setting bit i in the low order
byte of the command. (Bit I set IS hex "%02.")
The rest of the MMU commands consist of
both opera lion and data. The followmg internal
regIsters can be read or WrItten: the Mode
Register, the Segment Address RegIster, the
Descnptor RegIsters and the DeSCrIptor Seleclion Counter RegIster. A Descriptor Register
can be read or WrItten as a whole, or selected
subfields can be accessed. In addItion, by
usmg the auto-mcrement feature of the Segment Address Register, successIve Descnptor
Registers can be accessed, or a selected held
withm successive DescrIptor RegIsters can be
accessed. For example, one SpeCIal I/O command m block mode could read a number of
segment attrIbute helds. This IS useful m determmg whICh segments have been modified.
As an example of usmg the Special Output
instruclion SOUT to wrIte data into an MMU,
consider wrlling the contents of RegIster 6 mto
the Mode Register of MMU #2. The opcode for
thIS command is "%00" and so the command IS
"SOUT %0004, R6." Here the high-order byte
of the deslination field contams the opcode
and the low-order byte has bIt 2 set (hexadeclmal4 if 0100 in biNary) mdICatmg
MMU #2.
When a memory management system must
read or change information in the MMU to
respond to a segment trap or to re-organlze the
physIcal memory, it can Issue control commands to the MMU. These commands fall mto
two generIC categories: resel commands and
read/write commands. Reset commands are
SImply orders to the MMU to set or clear
speclhed fields. For these commands, the
28001 SpecIal I/O output command can be
used WIth the destination field set to be the
MMU command code correspondmg to the
deSIred aclion.
Read and write commands are slightly more
complIcated because they consIst of both commands and data. Such commands to the MMU
are Issued using the 28001 SpecIal I/O mstructIons. These instructions have a source and a
destmation held. For an mput mstruclion, the
source field contams an MMU command code
and the destmalion fIeld mdlcates where m
prImary memory the data is placed. For an
output mstruction, the destmalion field contams an MMU command and the source held
mdICates where the data to be WrItten mto the
MMU reSIdes in memory.
The hIgh-order byte of the command contams the opcode for that command; the loworder byte of the command can be used to
speCIfy the parlicular MMU to be accessed.
The MMU does not receIve mformation on
ADo-AD7, so external cIrcuitry must decode
informalion on these Imes durmg the SpecIal
I/O commands and then select a parlicular
MMU. The encoding of the low-order byte IS
dependent upon the system Implementalion.
ThIs paper always uses the convenhon that
bit I speclhes MMU number i.
The reset commands to the MMU are: Reset
VIolation Type RegIster, Reset SWW Flag In
VlOlalion Type RegIster, and Reset Fatal Flag
In Vlolalion Type Register. Resetting the ViolatIon Type Register IS SImIlar to a hardware
reset in that It clears thIs register and returns
the internal control of the MMU to an initIal
state (as If no vlOlalion had occurred since
system mlhalIzalion). Resettmg the SWW flag
or the FATL flag m the VIOlation Type RegIster
clears these flags.
Two other commands are SImilar to reset
commands m that they have no data assoCIated
WIth them. These are Set All CPU-InhibIt Flags
m the segment attribute helds and Set All
DMA-Inhibit Flags m the segment attribute
fields, both of whICh cause all segment
423
Commands
to the MMU
(Continued)
Certain MMU internal registers can only be
read-there is no corresponding write instruchon. ThIs is because these registers contain
mformation relating toa detected vlOlahon and
thus It IS not necessary to be able to write into
these regIsters. These registers are the Violahon Type Register, the Violahon Segment
Number Register, the Violation Offset Register,
the Instruction Segment Number Register, the
Instruction Offset Register and the Violation
Bus Status Register. Although the Violahon
Type Register cannot be written, it should be
noted that It can be cleared and that two of its
flags can be individually cleared: the SWW
flag and the FA TL flag.
Direct
Memory
Access
DMA operations may occur between 28001
machme cycles and can be handled through
the MMU. The MMU permIts DMA in either
the System or Normal Mode of operation. For
each memory access, segment attributes are
checked and-if a vlOlahon is detected-a
Suppress sIgnal is generated. Unlike a CPU
violahon, whICh automatically causes Suppress
sIgnals to be generated on subsequent memory
accesses until the next mstruchon, DMA violations generate a Suppress only on a permemory-access basis. The DMA deVICe should
note the Suppress sIgnal and record sufficient
mformahon to enable the system to recover
from the access VIOlation. No Segment Trap
Request IS ever generated durmg DMA (hence
warning condlhons are not signaled). There
eire no trap requests because the CPU would
not acknowledge the request unhl the end of
the DMA cycle.
At the start of a DMA cycle, the DMASYNC
lme must go Low, indicating to the MMU the
beginnmg of a DMA cycle. A Low DMASYNC
inhibits the MMU from using an indeterminate
segment number on lines SNo-SN6. When the
DMA logical memory address is valId,
DMASYNC must be High on one rising edge of
Clock and the MMU then performs ItS addresstranslahon and access-protection funchons.
Upon the release of the bus at the termmation
of the DMA cycle, DMASYNC must agam be
HIgh. After two clock cycles of DMASYNC
HIgh, the MMU assumes that the CPU has control of the bus and that subsequent memory
references are CPU accesses. The first mstruction fetch occurs at least two clock cycles after
the CPU regams bus control. Dunng CPU
cycles, DMASYNC should always be HIgh.
Hardware
and
Software
Reset
The MMU can be reset by eIther hardware
or software mechamsms but note that they
have dIfferent effects. A hardware reset occurs
on the fallmg edge of the Reset mput; a software reset is performed by an MMU command.
A hardware reset clears the Mode Register,
Violation Type RegIster and DeSCriptor Selection Counter. If the ChIP Select line IS Low
whIle Reset IS Low the Master Enable Flag m
the Mode RegIster IS set to 1. All other
registers are undefmed. After reset, the AID
and A lmes are 3-stated. The SUP and SEGT
open-drain outputs are not dnven. If the
Master Enable Flag is not set durmg reset,
the MMU does not respond to subsequent
addresses on ItS AID lmes. To enable an MMU
after a hardware reset, an MMU command
must be used in conjunction WIth ChIP Select.
A software reset occurs when the Reset
Violahon Type RegIster command is issued.
This command clears the Violation Type
RegIster and returns the MMU to its mltial
state as If no violatIOns or warnings had
occurred.
Multiple-MMU 28010 MMU archItecture supports system
ConfigurconfiguratIOns that use more than one
ations
MMU. Mulhple MMU devices can be used
either to manage 128 CPU segments rather
than the 64 supported by one MMU, or to
manage mulhple translahon tables.
The 28001 CPU generates logIcal addresses that can specIfy up to 128 dIfferent segment names. Because the MMU contains
only 64 Segment DeSCriptor RegIsters, two
MMUs are needed to perform address translahon for 128 logical segments. Systems
deSIgned WIth only one MMU deVIce still
have the power and fleXIbIlIty offered by
memory management, although tasks in
such a system are restricted to manipu-
424
latmg only 64 logical segment names. These
names must eIther be 0 through 63 or 64
through 127. If the MMU m a single-MMU
confIguratIOn is set to translate segment names
m one range and the CPU generates a logical
segment name m the other range, the MMU
does not perform address translation and no
phYSIcal memory locahon IS output. In this
case, no request IS made to memory. Therefore, a smgle-MMU configurahon should have
addItIonal external logic to detect erroneous segment names and generate a Segment
Trap and Suppress signal.
The Upper Range Select flag (URS) IS
used m multIple MMU configurations to
indIcate which group of logical segment names
Multiple-MMU
Configurations
(Continued)
Examples
are to be translated by an MMU. When thIs
flag IS set, the Segment Descnptor RegIsters m
the MMU are used in translating logical
addresses in the range 64 through 127. When
the flag is clear, the range is 0 through 63.
Thus the URS flag corresponds to the most
significant bit (bIt 6) in the logIcal segment
names that the MMU translates. Because this
flag IS under program control, the range of
logical segment names can be changed durmg
execution in System Mode.
MMU architecture also supports multiple
segment translation tables. This feature is
useful when separate tables are maintamed for
different tasks. Each task has its own table and
switching between tasks reqUIres enablmg the
appropriate MMU devices. In contrast, systems
with only one translation table must eIther
restnct the logical segment names that an
mdlvldual task can use, or change the
Descriptor RegIster entries whenever tasks are
swapped. Two flags m the Mode RegIster,
together wIth the N/S SIgnal, are used in mulhpie table conhgurations.
The Mulhple Segment Table (MST) flag
mdicates whether the configuration is being
used to support multiple tables. When this flag
IS set, the MMU will compare the N/S lme
against the Normal Mode Select Flag (NMS)
before generatmg a physICal memory locahon
on ItS Address lmes. When the lme and the
flag match (both asserted or both de-asserted),
the MMU is enabled and an address translatlOn
IS performed (assuming the URS flag matches
the most sigmhcant bit m the logical segment
name). If the Nis line fails to match the state
of the NMS flag, no translated address IS
generated by the MMU. The MST flag and the
NMS flag are under program control and can
be changed in System Mode.
The sImplest multiple translation table configuration has one table for Normal Mode
access and one for System Mode access. In
such a configurahon, the Multiple Table Flag
IS set in all MMUs and the NlS line of each
MMU receIves its input from the N/S output of
the Z8001 CPU. MMUs containing descnptors
of system segments have the NMS flag clear,
and those containmg descriptors to be used in
Normal Mode have the flag set. When the
Z8001 is m System Mode, the N/S line is Low
and It matches the NMS flag m those MMUs
whose Descriptor RegIsters contam system segment informahon. Therefore, these MMUs are
used in address translation for system
references.
When the Z8001 IS m Normal Mode, the NlS
lme is High and it matches the NMS flag m
those MMUs whose Descnptor Registers contam user segment mformation. Consequently,
these MMUs are used in address translahon for
user segments. In thIs configurahon, system
segments are separated from user segments.
When the Z8001 changes from Normal to
System Mode of operation, the appropriate
translation table IS automahcally selected. A
more elaborate example of a configurahon with
mulhple translation tables is gIven m the next
sechon.
This section descnbes two Z8001-Z8010 configurations: one contains two MMUs and one
address translation table; the other contams
seven MMUs and four address translation
tables. These examples are given in sufhClent detail to Illustrate some of the major
ideas in constructing memory-management
systems around the Z8010 MMU. HIgh-level
block diagrams lliustrate some of the major
features of typical hardware conhgurations
and short programs illustrate software techmques for usmg the MMU.
The hrst example system IS the two-MMU
configuration illustrated in FIgure 10. The two
MMUs are called MMU #1 and #2, and they
are selected during a command cycle by AD]
and AD2 bemg Low, respectively. Smce a
Special I/O instruction is bemg used blt 0 must
always be zero. Thus, when a low-order byte of
a command is "%02," MMU #1 responds;
when it is "%04," MMU #2 responds; and
when It is "%06," both MMUs respond. (Note
that AD j is mverted before attachment to the
CSpm.)
The AID] lme, which controls MMU #1
through the Chip Select input, is first com-
bined with the Reset lme. This allows the
Master Enable Flag to be set upon system
mlhalizatlOn, so the logical addresses generated by the CPU are passed to the physical
memory. ThIs IS done because-upon resetthe mode regIster IS otherWIse cleared, the
Translate Flag IS clear and addresses pass
through the MMUs untranslated. The bootstrap
program can therefore reside m absolute
memory locahons in the physICal memory. If
the Reset line IS not an input to the Chip
Select lme, the Master Enable Flag would not
be set durmg system mitialization and the CPU
would not be able to address memory through
the MMUs.
Note that there IS a dIrect path from the
CPU and DMA to the system bus. This path
IS used durmg I/O and memory refresh
because the MMUs are quiescent durmg these
cycles. It IS also used for data on memory
reads and wntes. Also, note that the Suppress
line goes both to the memory, where it can be
used to protect the memory from erroneous
425
i
-I:.
~
o
Examples
(Continued)
To write this descriptor into the MMU, a
copy of the descriptor should be created in
primary memory and a Special I/O block
transfer instruction used. The SOTIRB instruction can be used for this.
This instruction has the assembler syntax
"SOTIRB destination, source, count register"
where both the destination and source are
registers. The destination register contains the
command to the MMU, the memory location
pointed to by the source register contains the
first byte of the data to be transferred, and the
Count Register contains the nu~ber of bytes to
be transferred.
The opcode to load the Descriptor Register
is "%OB". Segment Descriptor Register 65 is
Segment Descriptor Register 1 of MMU #2, so
the MMU command is "%OB04".
To specify which Segment Descriptor
Register to write, it is necessary to load the
Segment Address Register of MMU #2 with 1.
The MMU opcode to do this is "%01" and so
the command is "%0104." The segment
number (in this case 65) is a parameter to the
example routine, passed in register O. The
writes, and back to the DMA device to save
information upon the event of a DMA access
error.
Of further interest in the example, address
latches are used to buffer addresses between
the Z8001 and a demultiplexed bus. This is
required to demultiplex the address and data
onto the bus. The address latch for ADs-ADJS
may not be needed if the 1/0 device does not
use separate address and data lines.
A detailed example indicates how such a
system could be used. First, consider setting
Segment Descriptor Register 65 to point to a
read-only segment of 768 bytes starting at
memory location % 115200. The segment is to
be accessed in Normal Mode. The Descriptor
Register should be %115202 01. The first two
bytes, %1152, indicate the starting location of
the segment (note that the low-order byte of
the memory address is all zeros and is not
stored in the Descriptor Register). The third
byte, %02, indicates that three blocks of 256
bytes have been allocated to this segment. The
fourth byte, %01, indicates that only the readonly segment flag has been set.
I
,.
RESET
16
BUSACK
7
ADo-AD16
-;:z
....
•
ADa-AD15
8
ADo-AD7
~
Z BUS
l,.
""
-;z
24
BAa-BS1S
V
SNa-SN,
ZBOO1
CPU
,--
SEGT
4
STo-ST3
4
eNTl
BUSREQ
V
,.
BRQ
IiAI
-;z
ADo-AD15
7
SNa-SNe
4
STo-813
4
CNTl
ADa-AD1S
7
SNo-SNe
EOP
4
810-ST3
MMU SYNC
4
DMA
BAa-BA1S
V
8
Z8018
r-
-;:z BAo-BA,
Z8010
MMU
16
N1
CNTl
-.:z
...
BA16-BA za
SUP
AD1 ...........
~ es
RESET
SEGT
I-
RESET
DMASYNC
J--
8
ADe-AD15
7
SNo-SHe
4
STo-ST3
Z8010
4
MMU
#2
eNTL
AD,
SUP
es
SElfi'
RESET
+1-
-
DMASYNC
Figure 10. A Dual-MMU Configuration
426
2049·0084
Examples
(Continued)
BIT
JR
RO, #6
Z, OVER
!Test to see if Descriptor Register is in MMU # I!
lor MMU #2!
SOUTB
LD
%0104, RHO
'Rl, #%OB04
!Set SAR In MMU #2!
!Prepare to wnte descnptor!
JR
NEXT
OVER:
SOUTB
LD
%OlO2, RHO
Rl, #%OB02
!Set SAR in MMU #l!
!Prepare to wnte descriptor!
NEXT:
LD
SOTIRB
RO, #4
@Rl, @RR2, RO
!Load count field-4 bytes!
!Write descnptor!
descriptor to be written is another parameter to
this routine: RR2 contains the address in
memory where this information resides. The
SOUTB instruction has a simIlar syntax to the
SOTIRB instruction explained previously
except that it wntes one byte instead of a
series of bytes, and the destinahon 110 address
is In the Instruchon itself instead of in a
register specified by the instruchon.
The routine on this page initializes the Segment Descriptor. Its parameters are found In
RegIster RO, which contains the segment
number to be wntten, and in Register RR2,
which points to the descriptor information in
primary memory. RegIsters RO through R3 are
used by this routme.
Now suppose that the user tries to write into
location < < 65 > > %9328. This causes a segment trap both because of the wnte to a readonly segment and because the access exceeds
the segment limit. At the end of the Instruction
that has the illegal memory access, the CPU
acknowledges the trap. During the trap
acknowledge cycle, MMU #2 asserts ADIO
(assuming its ID field is "OlO") and this information is placed on the system stack for the
trap-handling routine.
The trap-handling routine reads the violation
information registers from the MMU. The violation type register contains "%05" indicating
both a length violation and a read-only violation. The Violation Bus Status Normal Register
contains "%28". The first mbble indICates a
write in Normal Mode was in progress and the
second nibble indICates a memory data access
cycle was In progress. The violation segment
register contains "%41" indicating segment 1
of MMU #2 caused the violation (which is segment number 65), and the violation offset
register contains "%93" indicating the highorder byte of the logical address offset. The
operating system can then issue an error
message to the user indicating a read-only
violation to segment 65. Using the program
counter that was stacked when the segment
trap was acknowledged, the system can also
indicate the next instruction that was to be
executed. Note that in this system the loworder byte of the violation offset IS lost. This
condition is corrected in the next example
system.
427
Examples
(Continued)
_--;::L
t-
BUSACK
Z8001
16
ADo-AC1s
7
SNo·SNa
CPU
r-I-+
SEGT
---
4
STo-ST3
4
CNTL
I
16
ADa AD15
8
ADa-AC1s
8
ADo-ADr
I
BUSREQ
-
I
RESET
...
j
DMA SYNC
s;t
......
Z·BU
116
BAo-BA23
t:l BA!-BA15
-;:z BAa-BAr
V
AD1-AD7
MMU
SELECT
DECODe
8
'-+
BAl
16
BUSREQ
DMA
7
~
ADo-AC1S
SNO-SN&
4
STo-ST3
4
CNlL
MMU SYNC
E5P
-;:z BAa-BAts
BUSREQ
16
7
SNo-SNa
4
510-513
4
CNTL
ADo-ACts
Z8Q10
"
CS
.
16
-;:J
BAwBA23
-SUP
SEGT
r-
RESET
SNo-SNa
8
ADa- AC1S
4
STo-ST3
7
SNo-SNa
4
CNTL
4
STo-ST3
4
CNTl
Z8010
MMU
.2
MMU SYNC
f-I-----
...
DMASYNC
7
Z80
DMA
ADs-ADts
~
RESEr
BAI
8
MMU
.......- BAD
c...
LATCH
VOFF
OMASYNC
Z8015
r- I-----
......
16}
EOP
SUP
es
SEGT
~r-rr-
r-
RESET
DMASYNC
•
ADs-ADn
7
SNo-SNa
•
•
Z8010
MMU
510-513
16
;t-t- t-
07
CNT!..
SUP
es
r-
$EGT
ReSEr
Figure 11. IS-MMU Configuration
Figure 11 gives a high-level diagram of the
second system to be discussed. This configuration contains 16 MMUs, and the AID lines
select the appropriate MMU when in Command mode. The major innovation in this
example, aside from the additional MMUs, is
the latch that retains the least significant byte
of an address offset when a violation is
detected. This latch is enabled when a segment trap is generated by an MMU and holds
the low-order byte of the address that
generates an access violation.
In addition, external decoding logic for
selecting one MMU Chip Select line is indicated. Seven MMUs is the limit in one configuration without additional decoding logic
for selecting one MMU Chip Select line. (The
reason why ADO cannot be used to control an
eighth MMU is due to the Special 1/0 input
428
convention of the CPU. When the CPU inputs
a byte of information and ADo is asserted, the
data is taken from ADo-AD7' which are not
driven by the MMU.)
Switching Tables in a lS-MMU System.
The l6-MMU configuration can support a
memory management system designed with two
MMUs permanently allocated to the operating
system and the others allocated in pairs to different user tasks. Thus, seven user tasks can
have translation tables resident in the 14-user
MMUs, and switching between active tasks
requires the appropriate MMUs to be enabled
and disabled. This selection process can be
effected by manipulating the Master Enable
(MSEN) flags in the mode registers of the
appropriate MMUs.
2049-0085
Examples
(Conhnued)
The routme performs the selective enablmg
of MMUs required by a task swap. This routine
dIsables all user MMUs (thus dIsabling the currently enabled user MMUs), then enables the
appropriate pair. (The system pair IS always
enabled.) The code selecting the new task is
passed in register RI; It contams %n, if task n
is to be dispatched.
Two pecuhanhes of thIs example are worth
noting. First, each user ID number corresponds to seven MMUs (for example, all
upper-range user MMUs). The Segment Trap
processing routine has to take this into
account. Second, the ChIp Select code IS
assumed to be as follows:
CLR
SOUT
SLA
LD
RO
%00F8,RO
RI,#I
RI,TABLE(RI)
LDA
SOUTIB
RR2,DATA
@RI,@RR2,RO
INC
SOUTIB
END:
DATA:
TABLE:
RI, #8
@RI,@RR2,RO
ADo-AD-,
System:
User 0:
User 1:
User 2:
User 6:
MMU Selected
02
04
08
10
18
20
28
30
#1 ID=O, URS=O
68
70
#15, ID=2, URS=O
#16, ID=3, URS=1
#2
#3,
#4,
#5,
#6,
#7,
#8,
ID= 1,
ID=2,
ID=3,
ID=2,
ID=3,
ID=2,
ID=3,
URS= 1
URS=O
URS= 1
URS=O
URS= 1
URS=O
URS= 1
It is also assumed that %F8 will select all
user MMUs.
!Clear RO!
!Disable all user MMUs by clearing their mode registers!
!Multiply RI by 2-the number of bytes in a memory word!
!Get the command word (opcode always %00) for user n,
URS=O!
!Get the new mode regIster bit pattern (%DA)!
!Send %DA to lower-range MMU and increment RR2 to
DATA + I!
!Command word for URS = l!
!Send %FB to upper range MMU!
BYTES(%DA, %FB) !Mode regIster bit patterns!
WORDS (%8, % 18, %28, %38, %48, %58, %68)
Program to Switch Tables
MMU
Command
Summary
Opeode
00
01
02
'03
04
05
06
07
08
09
OA
OB
00-2049·A
Operation
Reac:llWrite Mode RegIster
Reac:llWrite Segment Address
RegIster
Read VIOlatIOn Type RegIster
Read VIOlation Segment
Number
Read VlOlahon Offset (hIgh
byte)
Read Bus Cycle Status RegIster
Read InstructIOn Segment
Number
Read Instruchon Offset (high
byte)
Reac:llWrite Base Field In
Descnptor
Reac:llWrite LImIt FIeld In
Descnptor
Reac:llWrite Attribute FIeld In
Descnptor
Reac:llWrite Descnptor (all
fields)
Ope ode
OC
OD
OE
OF
10
II
12
13
14
15
16
17-IF
20
21-3F
Operation
Reac:llWnte Base FIeld And
Increment SAR
Reac:llWrite LImit FIeld And
Increment SAR
Reac:llWrite Attribute FIeld
And Increment SAR
Reac:llWnte Descnptor And
Increment SAR
Reserved
Reset VlOlahon Type RegIster
Reserved
Reset SWW Flag In VTR
Reset FATL Flag In VTR
Set All CPU-InhibIt Flags
Set All DMA-Inhlblt Flags
Reserved
Reac:llWnte Descriptor Selector
Counter RegISter
Reserved
429
Bigh-Reliability
Microcircuits
~
Zilog
Military Specification
Standards
March 1981
General
Description
Zilog offers high-reliability versions of the
entire family of Z80 and Z8000 logic circuits,
processed in accordance with the requirements
of MIL-STD-833 level B (Test Methods and Procedures for Microelectronics). In addition, the
Z80 CPU and the Z80A CPU are included as
part of MIL-M-3851O (General Specification for
Microcircuits) in 1980, with the remaining
devices scheduled for inclusion in 198!. Each
of the Zilog devices will become militaryqualified as soon as the detailed specifications
are released.
General Considerations. Zilog high-reliability
microcircuits are designed to meet the full
military temperature range of -55°C to
+ 125°C and are packaged in hermetic dualin-line packages. These packages can reliably
Test
Condition
withstand the thermal shock requirements of
MIL-STD-833, method 1011, Condition C
(-65°C to + 150°C). For industrial users, Zilog
offers an extended operating temperature
range of -40°C to +85°C. All of Zilog's highreliability microcircuits receive 1005 processing in accordance with the requirements of
MIL-STD-833 level B or C (as specified). Table
1 lists the screening tests performed on the two
levels. An X indicates that the test is performed 100% ot the time, an S indicates that
testing is done on a sample basis, and a Z indicates that the test can be done upon request.
Table 2 lists the Zilog products available with
the 100% testing process shown with X's in
Table 1.
MIL-STD-883
Method Condition
Screening Level
B
C
SEM Inspection
2018
Z
Z
Precap Visual
2010
B
X
X
X
X
1008
C
X
X
Seal and Lot LD.
Stablhzahon Bake
48 hrs.
@
150°C
Temperature Cyclmg
10 cycles
1010
C
X
X
Centnfuge
Y1 Plane
2001
E
X
X
Fme Leak
1014
A
X
X
Gross Leak
1014
C
X
X
X
X
1015
1015
Done
Done
Electncal Test
Burn·In
Fmal Electncal
RadIOgraphIc Inspechon
External V,sual
Per Ziiog Data Sheets
168 hr.
240 hr.
X
X
25°C, -55°C,
and + 125°C
1 VIew
X
Z
X
S
2012
Z
Z
2009
X
X
NOTES: S ::::: Sample testmg only, X ::::: 100% testmg, Z ::::: Optional (tested If requested),
Table 1. Tolal Lol Screening
431
:a
!::-......
CD
~
General
Description
(Continued)
Product
Speed
Mil Temp
Range
Extended
Temp Range
Planned
JAN
ZSO CPU
2.5 MHz
Yes
Yes
Early 1981
ZSOA CPU
4.0 MHz
Yes
Yes
Early 1981
ZSO PIa
2.5 MHz
Yes
Yes
Mid 1981
ZSOA PIa
4.0 MHz
Yes
Yes
MId 1981
Z80 SIO
2.5 MHz
Yes
Yes
MId 1981
ZSOA SIO
4.0 MHz
Yes
Yes
MId 1981
ZSODMA
2.5 MHz
Yes
Yes
Late 1981
ZSOA DMA
4.0 MHz
Yes
Yes
Late 1981
ZSO CTC
2.5 MHz
Yes
Yes
Late 1981
Z80A CTC
4.0 MHz
Yes
Yes
Late 1981
Z8001 CPU
4.0 MHz
Yes
Yes
Late 1981
Z8002 CPU
4.0 MHz
Yes
Yes
Late 1981
NOTE' See Ordermg InformatIon for package and temperature deslgnators.
Table 2. High-Reliability Products Available
Manufacturing and
Process
Controls
Zilog hlgh-reliabllity microcircuits are
processed and assembled in accordance with
the Zilog Product Assurance Program Plan,
which conforms to the requirements of
Appendix A of MIL-M-3851O. The following
are some of the items contained in the plan:
• A clear, concise procedure for converting a
customer specification to a Zilog internal
specification, assuring the customer that
parts received meet or exceed speCified
requirements.
• A formalized training and testing program
for all operator and inspection personnel to
ensure that each operation is performed
correctly.
• An inspection system that includes a complete Incoming Inspection Laboratory, a
Chemical Analysis Laboratory, and a
Failure Analysis Laboratory to assure that
all materials, utilities, and work-in-progress
meet Zilog reqUirements.
432
• Rigid requirements for the cleanliness of
work areas and the maintenance of a Class
100 environment at all stations where
cntical operations are performed.
• A document control system to control
changes in design, materials, and processes.
• A system for maintaming documents and
records in active files for three years and in
archive files for ten years.
• An instrument maintenance and calibration
system complying to the requirements of
MIL-C-45662 (Calibration System
Requirements) .
• A quality audit system in accordance
with MIL-Q-9858 (Quality Program
Requirements) .
OO·2027-A
Package DiDlensions
_il
Package Dimensions
~
Zilog
March 1981
Package
Summary
This table summarizes the microprocessor
components aVailable from Zilog by number of
pins and package type. Following the table are
detailed drawings for each package type. For
Pins
Package
Component
28
CeramIC, Cerdlp, Plasbc
Z6132 QuaSl·Stabc
RAM
Z8430 Z80 CTC
40
CeramIC, Cercilp, Plasbc
Z8002
ZS030
Z8036
ZS038
Z8090
ZS400
Z8410
ZS420
ZS440
ZS441
ZS442
ZS449
ZS470
ZS530
ZS536
ZS538
Z8590
Z8000 CPU
ZSOOO Z·SCC
Z8000 Z·CIO
ZSOOO FlO
Z8000 UPC
ZSO CPU
Z80 DMA
ZSO PIO
ZSO SIO/O
ZSO SIOI!
ZSO SI0/2
ZSO SI0/9
ZSO DART
SCC
CIO
FlO
UPC
further information on specific components,
see the Ordering Information sechon of each
product specification.
Pins
Package
Component
40
CeramIc. Cerdlp, Plasbc
(Conbnued)
Z8601
Z8611
ZS671
Z8681
Z8
ZS
ZS
Z8
40
Protopack
ZS093
ZS094
ZS593
ZS594
ZS603
ZS613
Z8000 Z· UPC
ZSOOO Z· UPC
UPC
UPC
ZS MCU
Z8 MCU
48
CeramIC, PlastIC
Z800 I Z8000 CPU
ZSOIO Z8000 Z·MMU
64
QUlP
Z8091
ZS092
Z8591
ZS592
Z8602
ZS612
z·
z·
MCU
MCU
MCU
MCU
Z8000 Z· UPC
ZSOOO Z· UPC
UPC
UPC
Z8 MCU
ZS MCU
435
Package
Dimensions
28
PIN 1
IDENTIFICATION
15
)
~s:: Do
f.=:======::;
t
~~~~~~~~~
14
r
1"l~
I'
'I
+007
~!-:;=~- ~I~
0008
~
1..--°.60°_1
REF
0.125
,
_
,
--.I
1_°.065
MIN
0.035
BOTH ENDS
0.060
0.020
,
1_0.110
11_°.021
0.090
---
0.015
28-Pin Ceramic Package
'~=t--'-L28~~Li~LLJJ~Li~LL~-LLi~LL~-L'
0.550
l~~~
14
~
0230
----1~~-0.056
~I_~
.1.1
MIN
0.040
±.020
~
".'00 OM --I
BOTH ENDS
~
"-!,.
-TO~~
"-!""
-f~~
28-Pin Cerdip Package
15
28
0.062
RAD
-------~4f~------00
.62°_1
-0.60
1
t 10~~0
~::~
J ___ -11- 1_ ~5t
-
-
0.100
-TYP
0.018
0.050
± ,003 TYP TYP
TYP
MIN
28-Pin Plastic Package
NOTE- Package dimensIOns are given
436
In
Inches. To convert to millImeters, mulhply by 25.4.
Package
Dimensions
r
(Continued)
PIN 1
IDENTIFICATION
21
40
~s:: r:========~
t
DI'o
~~~==~~~~~~~~
20
I
~·--------------------~~~--------------------~
0.040
~~!E~
.~i_M.
MHi
0.060
0.020
J L.,.
'" .015 BOTH ENDS
± .010 TYP
JLM"
± .003 TYP
40-Pin Ceramic Package
,!It ·
21
0.550
1~T"'T"rT'T"TTCTTT'T'T'T'T"T"T'T'TT"TT'TT~
20
1---___________________ 2.060 ________________~
MAX
I
0230
0.056
'~L~
·::l-I.-.
~ .~,..~
•
'""
::t.020
~
1.-".
'm
~I.-.".
'Ill
40-Pin Cerdip Package
437
Package
40
Dimensions
(Continued)
21
T
0555
I
'=r=i=r=n=r=r=n=n==r=r=n==n=rr=n=n=n=r=r=;=r=rr=n=n=n=n=r=J
20
-----1
~-----------------------~~~----------------
. ~!
~~----------------------------------++--------------lI~li~
0.020
h-TTTTTTTTTTTTTT-rr-rr-rr-rr-rr--rr-rr--i+..."...,,--rr--rr--,--l~IN
0.015
-
......-0.009
1 -~:~~~--------I
40-Pin Plastic Package
40
0
lJ
t_~~UDDDDDDDDDDD
[
o
1
rLD D D D DOD D D DOD
D
rn.".
MAX
,...,,...,,...,,...,,...,,...,,!:!,
MAX
PIN 1
!DENTI FICATION
-
2.020 MAX
•
~
F
I~ 0.050 ~ 020
'I
1220 MAX
-I
20
sa'----j
Ll~1't
1_0.530
MAX
0.300
MAX
0.010
----.-.-.. -±.002
TYP
I~OR~9~_1
0.04JI
~ 1--'-0050~.015 BOTH ENOS _11_~°ti~3
~
1~0100~.010TYP
TYP
_ _ 0040+.007TYP
+.---------------------lR~O~
40-Pin Prolopack Package
438
.
I ~5
~~
-.002
MIN
,
Package
r
Dimensions
(Continued)
PIN 1
IDENTIFICATION
48
25
~S:1 ~=================:
)0
~
~~~~==~~~~~~==~~~
24
0.185
0 095
~~~
I'
0.040
0.530
+
.007
'I
.AA.f~
ffi ~
0.125
MIN
0.060
0.020
!
0.050
L=.025
BOTH ENDS
-J
~
0.100
1-=.010TYP
0.018
-JL=.003TYP
48-Pin Ceramic Package
4
0.620
15,]r-z--0.600=J
4 PLACES
I /~
..,-,,~ m., (
~
0155
O~1~
_
J'L~~:':;:::;::;:::=:::::;:;:;:::::::::::~:;:::::::;:::;::;::;:;:::::::;:::;::;::;:;:::::::;=;:;:::::::~
f 00"66510o~--I- :RIJ I~~
r---
MIN.
0.060.
TYP.
Irll_0060
~
0.040
48-Pin Plastic Package
439
Package
Dimensions
(Continued)
d1025~REF.
32
0.250 t [
16r)
I---------I!;~:)---------
64-Pin Quip Package
440
Z80
Microcomputer Boards
The Problem Solvers for
Microcomputer Systems
The Z80 MCB family of bus compatible microcomputer boards features
powerful performance and application
flexibility at a low total systems cost.
For every application, from a smgleboard solution to a high-performance
board set, the MCB family provides the
right comb mati on to easily solve most
microcomputer system problems.
Performance. The powerful architecture of the Z80 Central Processmg Unit
(CPU) is at the heart of the MCB
family. The dual-register set of the Z80
CPU allows high-speed mterrupt processing, context switching and other
forms of foregroundlbackground programming. Each register set includes
an 8-bit storage register which can also
be used as three 16-bit memory
address or general-purpose registers.
Two index registers provide greater
memory addressing capability. A 16-bit
external stack pointer permits
unlimited subroutine nesting and temporary data storage. In addition, the
CPU features vectored interrupts and
supports dynamic memories requiring
periodic refresh.
Economy. Because each Z80 microcomputer board provides a large
number of funchons wlthm a convenient and compact size, Implementing an MCB family solution reqUIres
fewer boards and less space than comparable alternatives. Fewer boards
mean lower power consumphon, lowercost power supply, less heat generation
and, therefore, lower cooling costs and
greater economy m connector and
other mechanical costs. Feature for
feature, the MCB family adds up a superior soluhon with unbeatable
economy.
The Competitive Edge. The time it
takes from product conception to
market introduchon may mean the difference between success or failure.
Success is assured with the ZSO MCB
family. The boards are compatible, can
be integrated into a system quickly, are
easy to learn and use, allow the convenient addition of last minute features,
and are available off-the-shelf.
Proven Design. The MCB family has
been used in hundreds of applications
throughout the world, demonstrating
reliabihty and performance day after
day. All Zilog mICrocomputer boards
undergo extensive burn-m with both
pre and post burn-m teshng to ensure
constant performance and reliability.
Family Members. The Z80 microcomputer board family includes powerful
CPU and memory boards as well as a
variety of versatile, high-performance
I/O expansion boards. The Z80 MICrocomputer Board (MCB) is a complete
smgle-board microcomputer with its
own self-contained memory plus serial
and parallel VO ports. The ZSO
Memory and Disk Controller (MDC)
adds up to 48K bytes of system memory
and interface for up to eight floppy
disk drives. The Z80 Serial Interface
Board (SIB) prOVides four hlghperformance serial interface channels
to solve a variety of data communications problems. Analog interface is
Simplified with the Z80 Analog Input
Board (AlB) or the Analog Input/
Output (AIO) board-each provides up
to 32 mput channels and 12-bit resolution. Flexible, parallel VO is prOVided
by the Z80 Input/Output Board (lOB)
with 64 I/O hnes and a hberal amount
of "wire-wrap" area to give the user a
head start on special interface solutions. Memory expansion IS easily
handled by the Z80 RAM Memory
Board (RMB). It contains both RAM (up
to 64K bytes) and fixed memory socket
area, while the Z80 PROM Memory
Board (PMB) allows up to 32K bytes of
non-volatile memory.
Make vs Buy. The make vs buy decision impacts both strategic and
economic Issues including new product
mtroduction schedules, product
reliability, test fixture design, resource
allocation, spare parts inventory, field
maintenance and many others. These
issues all Involve hidden costs and
potential product development delays.
When all costs are considered, it is
often more economical to purchase,
rather than manufacture, microcomputer boards.
Purohasing microcomputer boards
for initial production quantities and
later switching to in-house manufacture
of these boards prOVides an effective
compromISe solution. Zilog supports
thiS approach by licensing the manufacture of its microcomputer boards.
The high front-end manufacturmg costs
can thereby be postponed unhl the
success of the product is confirmed by
market acceptance.
443
Z80®MCB
Z80 Microcomputer Board
~
Zilog
Product
Description
March 1981
• Complete. Powerful Single-Board
Solution
• 16K or 4K Bytes RAM
• Industry Standard Serial Interface
• Convenient. Flexible Parallel 110
• Low-Power 5 V Operation
• Many User Options
• Programmable baud rates
• Relocatable address paging
• Vanable 1/0 port assignments
OVERVIEW
The Z80 Microcomputer Board
(MCB) is a complete smgle-board
mIcrocomputer adaptable to a wIde
range of applications. As either a
stand-alone board or as the heart of a
system of bus-compatible boa~ds, the
MCB provIdes the essential system
functions. Built from Zilog's widelyused Z80 Central Processing Unit
(CPU) and other Z80 peripheral components, th,s board provides serial and
parallel I/O, 4K or 16K bytes of
dynamic RAM and provision for up to
4K bytes of EIP/ROM all on a compact
7.7 x 7.5 in. circuit board.
All address, data and controllmes
are fully buffered to standard TTL
levels for easy expansion with other
boards in the Z80 MCB family. The
MCB employs an on-board dc-dc converter to allow operation from a single
+ 5 V power supply; the converter circuit ge~erates the + 12 V and - 5 V
necessary for the dynamic RAM array
and - 10 V for serial commumcation
interface.
FUNCTIONAL DESCRIPTION
Central Processing Unit. The MCB is
controlled by the Z80 CPU with 158
instructions mcludmg 16-bit arithmetic,
block moves and block 1/0, bit
manipulation and versatile addressmg
modes. This powerful set of mstructions
provides programming ease and, for
convement portabIlity, contams all
8080 mstruchons as a proper subset.
The CPU has an operating frequency
of 2.457 MHz derived from a 19.6608
MHz system clock and is able to execute instructions as fast as 1.6 I'S'
The CPU has a powerful and versatile vectored interrupt capabihty
whlCh allows identification of up to 128
umque interrupt servIce subroutmes
WIthout addItional hardware. See the
Z80 CPU Product SpecifJCatlOn for
addItional mformahon.
445
Memory-RAM Array. The MCB
includes a dynamic Ramdom Access
Memory (RAM) array of either 4K or
16K bytes. A umque refresh regIster in
the CPU sends a new refresh address
to the memory array after each op code
fetch; therefore, automatic refresh is
transparent and no walt states are
imposed. This manner of memory
refresh removes all the disadvantages
of dynamic memory while still retaining
economy and speed performance.
The addressable memory space may
be located at any 4K byte boundary by
changing the position of two jumpers
on the board. Systems requiring additional fixed memory, such as the
280® PROM Memory Board (PMB) can
thereby obtain a large block of continuous address space starting at zero.
This same memory pagmg scheme
generates a RAM SELECT signal
routed to the array by a pair of connectors. Thus, external hardware may be
used to disable the memory for bank
selection. Figure 1 shows the memory
addressing for the MCB/4 and
MCB/16.
(HEX
ADDRESS)
8000
,
/
/"><,
4000
2000
-
~
--- >< ,
RAM
RAM
--- .><
1000
E/PfROM
ElP/ROM
MCB 4
MCB16
Figure 1. Memory Addressing
for MCB/4 and MCB/l6
Memory-E/P/ROM Array. The MCB
includes four 24-pin sockets that can
accommodate up to 4K bytes of nonvolatile memory. The type of memory
device to be used-Erasable Programmable Read Only Memory (EPROM),
Programmable Read Only Memory
(PROM) or Read Only Memory
(ROM)-can be selected by changing
the jumper wires. Although the MCB
dc-dc converter generates the voltages
required by PIROM arrays, it cannot
deliver sufficient current from these
outputs to drive EPROM devices. When
2708 or 2704 EPROMs are used, external supplIes must prOVide the required
voltages. This option is easily
implemented by selechng the
app'ropriate jumpers on the board.
Table 1 lists devices that can be used
in these sockets. The standard board
configuration is for the 2708.
446
Device
Number
Non-Volatile
Memory
MaS
EIPROM
Bipolar
P/ROM
2704
2708
2716
8704
8708
2316
6341
6381
82S181
82S191
Table 1. Non-Volatile Memory Devices
As with the RAM array, addressing is
deSIgned to allow the user to relocate
the EIPIROM array to any 4K byte
boundary within the address range of
the CPU. A ROM SELECT output
signal and corresponding input contacts on the edge connector allow the
user to implement shadow EIPIROM or
select an alternate PROM set.
Counter-Timer. The 280 CTC contams
four mdependent 8-bit counter channels which can be programmed by
system software for a broad range of
counting and timing applications. One
of the four channels is used as a baudrate generator for serial interface; the
additional channels can be used .to
satisfy other system requirements.
Each of the four channels may be
decremented either from an external
input in the counter mode or from a
prescaled version of the system clock.
Upon reaching zero, a pulse is
available from three of the channels
and interrupts may be generated by all
four channels if they are programmed
to do so. The device will supply an
interrupt vector indicating which channel IS causing the interrupt. The four
independent input lines are each
available on a separate position of the
edge connector. The input signal may
serve as a positive or negative trigger
for the timer mode or as the actual
event to be counted. Each output may
be used as the input or trigger to a
subsequent channel m order to achieve
long time delays.
If an external device must cause an
interrupt to indicate a status change,
one channel of the CTC can be used as
a vectored interrupt generator by programming in a time constant of I and
drivmg the input trigger with a transition signal from the external device.
Thus, when no other parallel data need
to be transferred, interrupts can occur
without using the PIO strobe Ime.
The output of channel I serves as the
transmIt and 'receive clock for the
USART, prOVIding a convenient way to
implement software programmable
baud rates. This signal is routed to the
edge connector of the board and is
returned on a separate contact. Consequently, channel I of the CTC may be
used as either the USART clock or in
the user's application, depending on
edge connector wiring. See the ZaD
CTC Product Specliication for details.
I/O Capability. The MCB provides
both parallel and serial I/O via a
Counter-Timer Circuit (CTC), Parallel
Input/Output (PIO) device and a
Umversal SynchronouslAsynchronous
Receiver/Transmitter (USART). These
devices occupy eleven locations of
port-assigned 1/0 space as shown in
Table 2. Jumper options allow relocation of the 1/0 devices within the portassigned address space.
MCB 1/0 PORT ASSIGNMENTS
FUNCTION
PORT
CTC Channel 0
D4
CTC Channel I
D5
CTC Channel 2
D6
CTC Channel 3
D7
PIa Port A Data
D8
PIa Port B Data
D9
PIa Port A Control
DA
PIa Port B Control
DB
SWItch RegIster
DD
USART Data
DE
USART Status/Control
DF
Table 2. MCB Port Assignments
Serial J/O. A serial data communicahon channel prOVides support for
either asynchronous or synchronous
data transfer with either half- or fullduplex signaling. Driver and receiver
devices are mcluded to provide RS232C compatible interface to passive
20 rnA eqUIpment simply by relocating
two jumpers and attaching the serial'
line to the approprIate locations on the
edge connector.
Although the 8251 USART IS designed for polled operations, it is possible
to utilize the mode 2 interr'upt structure
of the CPU by coupling the transmitter
ready and receiver ready lines from
the USART to the mput lines of the
parallel I/O device. The baud-rate
clock is derived from the 19.6608 MHz
crystal oscillator and channel I of the
CTC deVIce. This allows baud-rate
selection under program control as
shown in Table 3.
1030,001
BAUD
RATE
As an alternahve to the on-board
clock, user-selected Jumpers allow
independent transmlt and recelve
cloch from external sources to be
applied directly to the USART. A
single external clock operahng at tWlce
the desired frequency may be apphed
to the on-board wave-shaping fhp-f!op,
thus providing a clean, reliable clock
signal.
TIME
CONSTANT
50
96
64
44
32
24
16
75
110
150
200
300
600
1200
2400
4800
9600
19200
38400
8
4
2
Parallel I/O. The Z80 PIO contains two
mdependent 8-bit parallel I/O ports. It
can be conhgured by the CPU to
operate m any of four major
modes-mput, output, bidirechonal or
control. Data direction characteristics
I
4} Counter
2
Mode
I
Table 3. Programmable Baud Rates
lor Serial 110
r-
can be programmed indlvldually or in
byte configuration. Each byte has two
independent handshake lines for completely asynchronous data transfers
wlth any general-purpose interface. To
allow maximum flexibllity for the user,
the 16 PIO data Imes and four handshake lines are totally uncommitted.
Also, four 16-pin IC sockets may be
wired to accept any necessary loglc
device or terminator package. See the
280 PIO Product Specification for
details.
eTe 110
4K OR 16K Byre
RAM SPACE
o
TO 4K BYTE
ROM, PROM, EPROM
SPACE
BUFFERED
ADDRESS BUS
I
I
SYSTEM
BUS
"
PORT
110
OECODE
BUFFERED STATUS
~
+
SERIAL
CLOCK
DATA
Z80 CPU
DI.
SWITCH
USART
CONTROL 12
25 MHZO
ose
BUFFERED DATA BUS
PARALLEL 110
J
Z80 eTC
i-
J
Z80 PIO
B
20
SERIAL 110 (RS-232C OR 20MA CURRENT LOOP BUFFERED)
'-Z80® MCB Block Diagram
1030-002
447
SPECIFICATIONS
Processor
Zllog
zao CPU
Operating Frequency
2.5 MHz
RAM Array
MCB/4
MCBIl6
4K X 1 RAMs, tAC = 250 ns
16K x 1 RAMs, tAC = 250 ns
EIPIROM Sockels
Four 24-Pm Sockets
Serial II 0 Channels
1 Channel - RS232C or 20 rnA Current
Loop
Serial Modes
Synchronous or Asynchronous
Dala Rales
50 to 38.4K Baud
Parallel I I 0 Lines
16 Lmes wIth 4 Handshake Lmes
EIPIROM Types
E/P ROM 2704, 2708 or EqUIvalent
P/ROM 6341,6381 ,82S181 ,82S191 or
EqUIvalent
ORDERING INFORMATION
Part No.
Description
05-6009-01
MCB/4
Z80 MIcrocomputer
Board wIth 4K bytes
RAM
448
Part No.
05-6009-02
Description
MCB/16
Z80 MICrocomputer
Board with 16K bytes
RAM
Connectors
122-Pm Edge (100 mll spacmg)
Power
+ 5 V ± 5% @ 2 A (max)
(wIth 3 PROMs)
Environmental
Temperature
HumIdIty
Physical
HeIght
WIdth
Part No.
05-6009-19
o to 50°C
o to 90% noncondensmg
7.5" (191 mm)
7.7" (196 mm)
Description
MCBIl6
Z80 Microcomputer
Board with 16K bytes
RAM for use with
RIOTMoperatmg system
software
OO-I030-A
Z80®RMB
Z80 RAM Memory Board
~
Zilog
Product
Description
March 1981
• Automatic Refresh by CPU lor
Simple. Fast System Operation
• Low-Cost. High-Performance
Dynamic Memory
• 8K Bytes of E/P/ROM Sockets
Available lor Flexible Memory
Arrangement
• User-Selected Address Boundaries
• On-Board dc-dc Converter Allows
Low-Power Operation
• Compatible with All MCB Family
Microcomputer Boards
OVERVIEW
The Z80 RMB RAM Memory Board
provides system memory expansion for
the MCB family of microcomputer
boards. Containing both RAM as well
as sockets for ElP/ROM memory. the
RMB board provides a flexible means
of implementing additional system
memory. Each board contains a dc-dc
converter that generates + 12 V and
-5 V bias voltages. thereby allowing
operation from a single +5 V system
power supply.
FUNCTIONAL DESCRIPTION
Address Map. The RMB memory
address selection is completely compatible with the MCB microcomputer
board. Figure 1 shows the memory
map for the RMB/l6 and RMB/4S.
Location of the memory array may be
altered by the user. The RAM chipselect logic allows each 4K segment to
have a starting address at any of 16
boundries within the 64K of
addressable memory space. Chip
selection IS accomplished by using a
PROM decoder to select the Row
Address Strobe (RAS) signal to the
appropriate bank of devices. This
method of bank selection mimmizes
overall system power since only the
selected bank dissIpates achve power.
The address select PROM is socketed
so that it may be easily replaced by the
user for address reassignment.
PROM Sockets. The RMB contains
eight 24-pin sockets that may be used
for a variety of EIP/ROM devices.
Through selechon of appropriate
jumpers the socket area can be configured to accept the devlCe types
shown in Table 1.
449
RMB/ie
RMB/48
.. K
FFFF
48K
COOOH
characteristics of the MCB CPU allow
memory to be refreshed automahcally
and in a transparent mode. FolloWing
each op·code fetch, a new refresh
address is available on the system
aFFFH
32K
A
8000H
A
0-
16K
==x
MEMORY ACCESS ADDRESS
X'--_ _x:=
REFRESH ADDRESS
iiiRa _ _ _ _ _'\
4000H
\ ___---J!\'-_-JI
4K
RFSH _ _ _ _ _ _ _ _ _ _ _ _ _,
1000H
o
o
o
15
address bus while the op-code is being
decoded within the CPU. The CPU
does not require wait states; therefore,
there is no degradation of system performance (See Figure 2).
\'--_.....1
-RMB MEMORY
-MCBI16 MEMORY
Figure 2. Automatic Refresh Generation
Figure I. RMB Memory Map
r--
Non-Volatile
Memory
MOS
E/PROM
BIpolar
P/ROM
Device
Number
2704
2708
2716
:
RAM
OUTPUT ENABLE
I RAS
I CAS
o TO 64K BYTE
DYNAMIC RAM
MEMORY SPACE
at :NTER NAL
DATA BUS
ADDRESS BUS
16
SYSTEM
LJ
BUS
CONTROL BUS
Table I. Non-Volatile Memory Devices
DATA BUS
Chip selection is accomplished by
means of a PROM decoder, supplied
socketed and unprogrammed so that
the user has complete flexibility m Its
application. When using EPROM
devices the -5 V and + 12 V .
requirements must be supplied from a
source external to the board.
PAGE
DECODER
I AD~~~UX
8704
8708
2316
6341
6381
82S181
82S191
ADDRESS
I
•
DATABUS
BUFFER
CONTROL
•
F
DATA
BUS
BUFFER
!
ROM
_I
OUTPUT ENABLE
II
PAGE
DECODER r
AND
CHIP SELECT
I
SELECT
I
I
o TO 16K BYTE
ROM, PROM, EPROM
MEMORY SPACE
I
'--
Z80'" RMB Block Diagram
Refresh. Although dynamic RAMs are
used, the RMB does not require any
addihonal circuItry for refresh. Unique
450
1031-001
1031-002
SPECIFICATIONS
Memory Capacity
Dynamic RAM 64K
E/P/ROM
16K
Memory Size
Standard ConfiguratIons
16K or 48K RAM
Connectors
122-Pm Edge (l00 mil spacmg)
Environmental
Temperature
Humidity
Power
+5 V ±50/0 @ 1.6 A (max)
DC-DC Converter Output
+12 V @ 320 rnA (max)
-5 V @ 50 rnA (max)
Physical
Height
Width
o to 50'C
o to 90% noncondensmg
7.5" (l91 mm)
7.7" (l96 mm)
ORDERING INFORMATION
Part No.
05-6003-02
05-6003-03
OO-!031-A
Description
280 RMB/l6
16K RAM Memory Board
280 RMB/32
32K RAM Memory Board
Part No.
05-6003004
05-6003-05
Description
280 RMB/48
48K RAM Memory Board
280 RMB/64
64K RAM Memory Board
451
Z80® AIO/ AlB
Z80 Analog Input/Output
and Analog Input Boards
~
Zilog
Product
Description
March 1981
N
GO
• 12-Bit Resolution and High
Accuracy
o
...
:ao
• 16 Single-Ended or 32 Differential
Inputs for Application Flexibility
;
• Fast 45 ms Channel Conversion
• On-Board dc-dc Converter for Convenient Low-Power Operation
• Polled or Vectored Interrupt Control for Programming Convenience
• Multiple Voltage Ranges for Easy
Interface
OVERVIEW
The 280 Analog Input Board (AlB)
provides 16 differential input channels
that may be configured as 32 singleended channels. Through a combmation of user-selectable input voltage
ranges and a programmable gain
ampltfier, input signals ranging from
mIllivolts to as high as 10 V can be
converted to a 12-blt word. In order to
ensure accuracy and compatiblltty with
the other MCB family boards, a 5 V
dc-de converter IS included as a
standard feature.
The Z80 Analog Input/Output (Ala)
Board has input features Identical to
the AlB except that there are also two
12-bit DIA output channels, each with
a wide range of user-selectable output
voltages.
FUNCTIONAL DESCRIPTION
Input Ranges. The AlB and Ala contam an input multiplexer, an ampliher
whose gam may be altered from I to
1000, and an analog-to-dlgllal converter module. Five baSIC input ranges
are shown in Table 1. The bIpolar
inputs are converted mto a 12-bit value
in twos complement format; the
umpolar mputs are converted mto a
12-bit straight bmary value.
0.0
0.0
-2.500
-5.000
-10.000
to
to
to
to
to
+ 4.9988
+ 9.9975
+ 2.4988
+ 4.9975
+ 9.9951
V
V
V
V
V
Table 1. Input and Output
Voltage Ranges
453
Amplifier Gain. Amphher gain is set
to I but can be changed by a resistor
substitulIon according to the following
formula:
20 kO
R = Gain-l
Increasing the gain of the amphfier
effectively allows the input voltage
range to be scaled by the recIprocal of
the gain factor. For example, by
increasing the amphfier gain to 1000,
an input voltage range of ±2.5 V
becomes ±2.5 mY. As the gam IS
increased the settling time of the
amplifier will also increase.
Because the AIO and ArB use a hxed
timing sequence between channel
selection and the start of data conversion, the system delay time must be
lengthened, via a resistor change, to
allow for the greater settling lIme of the
amplifier at hIgher gain (see Table 2).
Amplifier
Gain
Delay Time
1'"
Resistance
kll
I
10
100
1000
20
30
40
100
13.3
14.3
19.0
47.5
equivalent Single-ended input circuit is
shown in Figure 1. The multiplexer
must be allowed to settle to ± .01 %
(approximately nine time constants) to
insure accuracy. For high source
impedance, it may be necessary to
increase the system delay time beyond
that shown in Table 2. For the differential input configuration, the multiplexer
time constant is one half of that in
Figure 1.
System Interface. The AIO and ALB
occupy 10 locations wlthm the MCB
CPU's IIO address space as shown in
Table 3. Input status, control and data
are interfaced through a PIO while the
data for the two output channels is written to a set of l2-bit output regIsters.
The location of the port assignments
may be moved anywhere within valid
IIO space of the CPU, with the restriction that both the PIO and output
registers must reside within the same
20H block of IIO addresses. These
address changes are jumper-selectable.
Data may be obtained in either a
polled or fully vectored interrupt
mode. The mode is selected entirely by
software control.
Table 2. Recommended System Delay
Time VB Amplifier Gain
Input Modes. The standard 16-channel
differential input configurahon is
recommended in areas of commonmode noise and for low-level inputs.
For input signals of 1.0 V or more, a
32-channel smgle-ended configurahon
can be jumper selected.
Output Ranges. The AIO board is
configured with two independent 12-bit
digital-to-analog convertor output
channels. Output voltage range is
selectable by the appropriate jumper
configuration. The available full scale
output ranges are shown in Table 1.
Output quantities are represented as
twos complement numbers for bipolar
ranges and as straight binary numbers
for the unipolar configuration.
Function
PIO Port A Data
PIO Port B Data
P 10 Port A Control
P 10 Port B Control
Address RegIster
(Channel Select)
Status RegIster
DACI Output (La Byte)
,DACI Output (HI Byte)
DAC2 Output (La Byte)
DAC2 Output (HI Byte)
Port
80
81
82
83
88
89
8C
8D
8E
8F
AIO
Only
Table 3. AIO/ AlB Port Assignments
ADDRESS BUS 16
CONTROL LINES
SYSTEM
USER
BUS
110
Equivalent Input Circuit. Source ,output impedance has an effect on the settling time of the multiplexer. The
formula for the lIme constant and the
DATA BUS
SOURCE
RESISTANCE
8
MULTIPLEXER
ON RESISTANCE
Rg
RON
1.8k
C,
"SOpF
C,
50pF
MULTIPLEXER TIME CONSTANT"" fRg +RON) Co
zeD AIO/AlB Block Diagram
Figure I. Input Equivalent Circuit
454
1033-01
1033-02
SPECIFICATIONS
Input Characteristics
Number of Channels
32 Smgle-ended/ 16 Differenhal
ADC Gam Ranges
O-S V, 0-10 V, ±2_SV, ±S V,
±10 V
AmplifIer Gam Ranges
I to 1000
Max Input Voltage
±26 V
Input Impedance
100 MD, IOpF OFF Channel
100 MD ON Channel
BIdS
Current
20 nA
Dlfferenhal Bias Current
10 nA
Resoluhon
12 BIts
Throughput T,me
Gam = I
4S p.s Channel
Gam = 100
1001's Channel
Accuracy
Gam=1
Gam= 1000
±0.02S% FSR
±O.lOO% FSR
Lmeanty
±1/2 LSB
Dlfferenhal Lmearlty
±1/2 LSB
QuantIzmg Error
±lI2 LSB
Temperature StabIlity
Gam = I
± 30ppm of FSR/ 'C
Gam= 1000 ±80ppm of FSR/'C
DynamIC Accuracy
Sample and Hold Aperature
30 ms
Aperature TIme Vanahon
±S ms
Dlfferenhal Ampllf,er CMR
74 db (dc to I kHz)
Crosstalk
80 db down @ I kHz for OFF
and ON Channel
Output Characteristics
Number of Channels
2
Output Voltage Ranges
O-SV,O-lOV, ±2.SV, ±SV,
±10 V
Output Current
SmA
Output Impedance
I
Resolution
12 b,ts
Output Settling T,me
10 I's (max)
Accuracy
Output Accuracy
±0.012S% FSR
Temperature Coeff,c,ent
± 30ppm of FSR/ 'C
Connectors
122-Pin Edge (l00 mIl spacing)
Power
+SV ±S% @ 1.6 A (max)
Environmental
Temperature
HumidIty
Physical
HeIght
W,dth
o to 90% noncondensing
05-6075-01
05-6075-02
OO-1033A
o
III
7.S" (191 mm)
7.7" (196 mm)
S
E
ORDERING INFORMATION
Part No.
N
00
Description
Z80 Ala
Analog Input/Output Board
Z80 AlB
Analog Input Board
455
Z80®IOB
Z80 Input/Output Board
~
Zilog
Product
Description
March 1981
N
00
..
o
• Large User Interface Area for
Application Flexibility
i
• 64 Data and 16 Handshake Lines
for Easy Interface
• Fully Vectored Interrupt Operation
Allows Convenient Program
Design
• Port Assignment May Be Altered
to Allow Several lOBs in a Single
System
• Uses Z80A PIO Devices for Full
Compatibility with Other
Members of MCB Family
OVERVIEW
The Z80A Input/Output Board (lOB)
provIdes system expanSlOn to external
dIgItal 110 devlCes. It IS fully compatible with other boards in the MCB
famlly and provIdes eIght parallel I/O
ports to augment the two contained on
the Z80 Microcomputer Board (MCB).
DesIgned for user flex,b,hty, the lOB
can tams four Z80A Parallel Input/Output (PIO) devIces, a large pre-dnlled
user mterface area, daIsy-cham mterrupt prionty logic and user-selectable
port address assIgnment.
FUNCTIONAL DESCRIPTION
The lOB contams four PIO controllers whlCh provIde 64 programmable I/O lmes. These lines may be
conhgured eIther as mdlvldual data
lines wIth independent data d,rechon
or as groups of eIght lmes for byteonented data transfer. The lOB gIves
the user a headstart on specIal mter-
face reqUlrements by provldmg a large
pre-drilled, pre-etched interface area.
The hole array is spaced on .3' and
.6' centers m a flexible arrangement
that accommodates 16-pin, 24-pin or
40-pm ICs.
Parallel Input/Output. Each Z80A
PlO deVIce IS a programmable, dualport ClrcUlt that provIdes a TTLcompahble mterface between
peripheral devlCes and the Z80 CPU.
The PIO mterfaces to penpherals vIa
two independent general-purpose I/O
ports deSIgnated Port A and Port B.
Each port has eIght data b,ts and two
handshake sIgnals, READY and
STROBE, which control data transfer.
The READY output mdlCates to the
penpheral that the port IS ready for a
data transfer; STROBE IS an mput from
the peripheral that mdlCates that the
data transfer has occurred. In add,hon,
the 8lght output lmes from Port B can
dnve Darhngton transIstors (1.5 rnA at
1.5 V).
457
Operating Modes. Each group of eight
lines is capable of being programmed
in one of four modes of operation-byte
output, byte input, byte input/output
and bit input/output.
Input Operation. The PIO device
allows fully vectored interrupt operation with a unique vector for each port.
The interrupt abll1ty of each port may
be enabled or disabled independently
of the other ports. Interrupt priority is
established by a hardware daisy-chain
arrangement. Each group of lines has a
fixed position within the priority structure; individual lines wIthin each port
are assIgned equal priority. (See the
Z80 PIO Product Specification for
details.)
Port Assignments. By jumper placement, the four PIOs can be placed in
any of eight 32-byte address ranges
allowmg the system to be easily configured and expanded.
CONTROL BUS 6
PORT AlB CONTROL
PORT B
>-____-1
Z80(~
PIO
I--_ _ _~
UNWERSAL
SYSTEM
DATA BUS
P10
!NTERFACE!
AREA
B
BUS
zeOA PIO
1'1
ADDRESS BUS B
f-,"::::'=ER"'N~AL-:C"'ON::::'='O"'L-::B::::US---I Z80~) PIO I-----~
Z80A@ lOB Block Diagram
SPECIFICATIONS
I/O Lines
64 Programmable
Operational Modes
Input, Output, BldlreclIonal, Bit Control
Handshake
8 Ready and 8 Strobe Lmes
Interrupt Vectors
8
I/O pelrt Locations
16 User· selectable wlthm 1·0£·8 Blocks
Output Voltage
HIGH 2.4 V (mm) @ 250 rnA Output
Current
LOW
0.4 V (max) @ 2.0 mA Smk
Current
Connectors
122-Pm Edge (100 mIl spacmg)
Power
+5 V ±5% @ 0.5 A (max)
'(wIthout user ICs)
Darlington Drive Current
Port B of Each PIO
3.8 mA (max) @ 1.5 V
Environmental
Input Voltage
HIGH 2.0 V (mm)
LOW 0.8 V (max)
Physical
HeIght
WIdth
Temperature
HumIdIty
o to 50'C
a to 90% noncondensmg
7.5" (191 mm)
7.7" (196 mm)
ORDERING INFORMATION
Part No.
Description
05-6006-03
Z80 lOB
Input/Output Board
458
1034-001
00-1034A
Z80®SIB
Z80 Serial Interface Board
~
Zilog
Product
Description
March 1981
• Industry Standard RS-232C
Interface
• Polled or Fully Vectored Interrupt
Control for Maximum Program
Flexibility
• Single +5 V Operation
ill Fully Compatible with Zilog's
MCZ-l Series Microcomputers and
PDS BOOOTM Product Development
System
• Error Detection for Reliable
Message Handling
• Four Powerful. Flexible Data
Channels
OVERVIEW
The Z80 SerIal Interface Board (SIB)
1S a multiple channel serIal communications interface w1th a varIety of
powerful, convement features. Four
independent channels, proVided by
8251 USART devices, allow synchronous or asychronous data transfer
w1th either half or full duplex slgnal
handlmg. All four channels have
drIvers and rece1vers for RS·232C
system mterface and one will also
accommodate a 20 rnA current-loop
interface. A dc-dc converter
generates all necessary voltages from a
single +5 V supply. An on-board
crystal oSClllator prov1des commumcahon hmmg mdependent of the system
clock.
FUNCTIONAL DESCRIPTION
The four SIB channels are capable of
mdependent operation in e1ther asynchronous or synchronous protocols.
The system program may inihate and
control e1ther mode by selectmg the
approprIate command words. Both the
transm1tter and rece1ver sechons are
double-buffered for maX1mum performance and convenience. All data
transfer status slgnals, such as TxRDY
and RxRDY, are aVallable in a readable status register or as external
slgnals so that e1ther polled operahon
459
or full interrupt control may be
selected by the user under software
control. In addihon to the normal data
transmission, each channel can
generate break sIgnals and be mdlvidually reset under software control.
Asynchronous Mode, In the asynchronous mode, the system program
controls the number of data b,ts (5, 6,
7, or 8), the number of stop b,ts (1,
1Y" or 2.) and the sense of parity protechon (even or odd) if enabled. Each
channel has a programmable baud rate
factor of 1, 16, or 64 controlling the
relationshIp between the transmItted or
received data rates and the frequency
of the baud rate reference clock. See
Figure 1 for a descrIphon of the asynchronous mode control word. Error
detection signals are avaIlable for each
channel and may be read from the
channel status register; these sIgnals
include parIty error (PE,), framing error
(FE), and receiver overrun error (OE).
Figure 2 descrIbes the channel status
register.
Baud
Rate
50
75
110
134.5
150
200
300
600
1200
2400
4800
9600
19200
38400
Synchronous Mode, In the synchronous receive mode, character synch-
ronization may be obtamed from an
external devlCe or mternally from the
receIved data stream. The nature of the
SYNC connection for each channel IS
programmed as eIther an mput when
the channel IS expectmg an external
sync signal or as an output to ldenhfy
that sync has been achIeved. In addlhan, each channel may be programmed to operate with eIther smgle
or double synchromzing characters.
6
'-I-'
5
4
l t'
3
2
1
0
Time Constant
Hex
Decimal
96
64
44
36
32
24
16
8
4
2
I
4'
2'
I'
60
40
2C
24
24
18
BAUD RATE FACTOR
ASYNC MODE, 64X
BAUD RATE FACTOR
BITS
BITS
BITS
BITS
5-16, 1-7,3-6
5-15, 1-7,3-6
5-16,2-7,3-6
5-15, 2-7, 3-6
5-16, 1-7,4-6
5-15, 1-7,4-6
5-16,2-7,4-6
5-15, 2-7, 4-6
8
4
2
4'
2'
I'
7
5
6
7
8
00 to IF
20
3F
40
5F
7F
60
80
9F
AO
BF
CO
DF
EO
FF
Table I. Baud Rate vs Time Constant
for 16 x Baud Rate Factor
'~"ffi~§:~:::"
00
01
10
11
J4 JUMPERS
10
BIT NO
11
ADDRESS RANGE
* eTC m counter mode
Timing, The transmitter and receiver
clocks for each USART channel can be
derIved from eIther the on-board
7
Interrupt Control, Each channel may
be selected to operate m eIther a
polled mode or a fully vectored mterrupt mode. The mterrupt capabIlIty for
each channel may be enabled or
d,sabled by the programmer to allow
mIxing both modes. Each channel may
be programmed to have a umque mterrupt vector for the receIver ready and
the transmitter ready sIgnals, allowmg
independent interrupt service
subroutines for each d,rechon of data
transfer. Interrupt prIorIties are assigned by the hardware on a dalsychain baSIS. The four receIver ready
sIgnals are given prIority over the four
transmItter ready signals. The channel
priorIty for each group ranges from
channel 0 havmg highest PrIOrIty to
channel 3 the lowest.
Hardware Interface, Each of the four
channels has drIvers and receIvers to
allow full industry standard RS-232C
mterface parameters to external eqUlpment. All voltages necessary for thIS
crystal oscIllator, thereby enaLlmg
opera hans to be mdependent of the
mam system clock frequency, or proVIded externally by the approprIate
Jumper selechon.
For mternal clock sIgnal generation,
mput sIgnals to two Counter/TImer C,rCUltS (CTC) can be jumper-selected to
be eIther 112 or 1132 of the crystal frequency. The outputs of the CTCs are
further diVIded by flip-flops to provIde
a 50% duty cycle to the USARTs. By
programming each channel of the thIrd
on-board CTC WIth the proper hme
constant, baud rates of 50 to 38.4K are
possIble. Table 1 shows hme constants
for varIOUS data rates when the USART
has been programmed for a baud rate
faster than 16.
PER
PER
PER
PER
6
Table 2. Port Address Range
5
4
J
2
1
0
BIT NO
.!;;-+-+-+-+-+-+-+-SYNDET
CONDITION OF NAMED SIGNALS
TxRDY
Rx ADY
' - - - - - T x EN
CHARACTER
CHARACTER
CHARACTER
CHARACTER
PE
'-------
~~:IJ.;~~~~O;ARITY
ERROR
IS DETECTED
'------ ~ ~ ~!~::~~ ~~s:JtLf
'-------- ~ ~ ~~~l~:~r::y
'--------- n ~ 1~T~:O~11ITS
00
INVALID
11
2 STOP BITS
Figure I. Channel Mode Control Word
460
THESE BITS
ARE RESET
BY BIT 4(ER)
OFTHE
COMMAND
INSTRUCTION
DE
L -_ _ _ _ _
~~!E~~f~i:~~F~l~~6 ~~¥~ :~:D
NEXT CHARACTER
'E
FRAMING ERROR (ASYNCHRONOUS
'---------
SE~O':~E~Nk ~AlID STOP BIT IS NOT
DETECTED AT THE END OF
EVERY CHARACTER
Figure 2, Channel Status Register
1036~00 1,
002
mterface are provIded by the dc-dc
converter operahng from a smgle +5 V
mput. Channel 3 IS supphed WIth an
achve 20 mA current loop mterface
whICh the user may dISable m favor of
the RS-232C mterface by selectmg the
appropnate Jumper. In addlbon to the
separate transmIt and receIve data
sIgnals, standard modem control
sIgnals such as DSR (data set ready),
DTR (data termmal ready), CTS (clear
to send), and RTS (request to send) are
provided for each channel. The sense
of each channel's mterface IS Jumperselectable so that the board may
behave as eIther a termmal devICe or a
modem devIce.
Port Selection. The SIB uhhzes port
assIgned I/O and occupIes locahons
wlthm the 1I0 port assIgnment space.
By selection of appropnate Jumpers
-
the user may place the SIB mto any
one of eIght port address ranges, each
offermg 32 avallable port addresses.
Table 2 shows the possIble address
ranges for the SIB. Each of the four
USARTs and the three CTCs may be
placed at a umque locahon wlthm the
selected range. The user selects the approp nate Jumper conhgurahon for the
locahon.
CONTROL
_I
+EXT
L
elK
~
L BUFFER
EXT elK
ADDRESS BUS
"I
DATA BUS
BUFFER
I
I
I
+
110\
ADDRESS
DECODER
IEXTl
elK
I
I
elK
SEL
JI
zao eTC
I---
110 SELECT
DATA BUS
HI
DATA BUS
BUFFER
SYSTEM
BUS
I
TxADY
t
INTERNAL
DATA BUS
!
RS232C 110
zao eTC
r-
o
~
1'1.1
~xRDY
1:11:1
110 SELECT
!
USART
RS 232C OR 20mA 110
r-
zao eTC
RxADY
N
00
1
CONTROL
J
1
t
I--~
USART
USART
1--.....
USART
r
AS 232C 110
RS232C 110
'--
zao SIB Block Diagram
1036·003
461
SPECIFICATIONS
Number of Channels
4
Synchronization Method
External or Internal Character Match
Power
Mode
Full or Half Duplex
Interface
Channels 0-3
RS232C
Channel 3
Current Loop AvaIlable
Environmental
Baud Rates
50 to 38.4K Baud
Baud Rate Reference Clock
19.6608 MHz
Connectors
122-Pin Edge (100 mll spacmg)
+5 V ±5% @ 1.5 A (max)
Temperature
HumIdIty
Physical
HeIght
WIdth
o to 50°C
o to 900/0 noncondensmg
7.5" (191 mm)
7.7" (196 mm)
ORDERING INFORMATION
Part No.
Description
05-6007-01
280 SIB
Senal Interface Board
462
OO·1036·A
Z80®pPB
PROM Programmer Board
~
Zilog
Product
Description
March 1981
N
00
o
.
."
."
III Flexibility to Program a Wide
Range 01 E/PROMs
.. Complete Programming Circuitry Generates All Required
Programming Voltages
II Zero Force Insertion Sockets lor
Reliability and Ease 01 Use
OVERVIEW
The Z80 PROM Programmer Board
(PPB) is deSIgned to be used m conjunction with the Z80 MIcrocomputer
Board (MCB) to program a variety of
MaS EIPROM or bipolar PROM
deVICes. The PPB is available in two
configural1ons, PPB and PPB/16, each
capable of programmmg a specific
type of E/PROM. All necessary programmmg voltages are generated on
the boards making them completely
compal1ble with the MCB famIly,
MCZTM mIcrocomputers or ZDS
development systems.
FUNCTIONAL DESCRIPTION
The PPB uses Z80 PIa deVICes to
mterface between the E/PROM sockets
and the system microprocessor. Singlebyte data transfers in both dlrechons
permit either reading or programming
of the selected E/PROM socket. Additional parallel IIO lines control the
mode of operahon and provIde chip
select to the deSIred socket.
Zero force insertion sockets are used
m the programming locations to provIde convenience, rehabihty and long
hfe. The programmer board extends
beyond the card cage for easy access
to programmmg sockets mounted near
the board edge. Each board contains
one 16-pm and two 24-pin sockets.
Device
MaS E/PROMs
2704
2708
BIpolar PROMs
7610
7611
7620
7621
7640
7641
Organization
512 x 8
1024 x 8
256 x 4
256 x 4
512 x 8
512 x 8
1024 x 8
1024 x 8
Table I. PPB E/PROM Devices
463
PROM Types. The PPB IS designed to
program 2704 and 2708 E/PROM
devices and HarrIs-type blpolar
devices. (See Table 1 for devICe selechon.) The PPB/16 allows programming
of 5 V 27l6-type EIPROM devIces and
Signetic-type bIpolar devICes (see
rADDRESS BUS
I/O
ADDRESS
DECODe
•
DATA BUS
SYSTEM
BUS
BUS
Organization
I
J
I
VPPSNCCB (2)
,
Z80 PIO
CONTROL
MOS
EPROM
SOCKET
PROG/CS (2)
~
Table 2).
Device
,
,
INTERNAL DATA BUS
DRIVER
I
PROG
DATA
DRIVERS
I
PROG
PULSE
PROGRAM
ADDRESS BUS
•
BC
MOS E/PROMs
2716
BIpolar PROMs
82S126
82S129
82S130
82S131
82S140
82S141
82S180
82S181
82S2708
2048 x 8
256
256
512
512
512
512
1024
1024
1024
x
x
x
x
x
x
x
x
x
I
I
1
4
4
4
4
8
8
8
8
8
BIPOLAR PROM
SOCKETS
I
zao@
PPB/l6 Block Diagram
rI/O
Table 2. PPB/l6 E/PROM Devices
MOS
ADDRESS
ADDRESS BUS 8
DECODE
EPROM
I
SOCKET
Software. Both programmer boards
are supported by the Z-PROG utihty
whICh is part of Zilog's RIOTM
operating system. Z-PROG is an easy
to use interactive program that allows
E/PROMs to be read, programmed
from disk file and duplicated, and
allows the user to select the appropriate socket by speClfymg the
E/PROM type and the word length.
Z-PROG also provides address boundary selechon for parhal E/PROM
programmmg.
DATA BUS 8
PROG/CS (2)
---
J
VPPSIVCCB (2)
Z80 PIO
SYSTEM
BUS
t
PROG
PULSE
DRIVER
INTERNAL DATA BUS
I
CONTROL
BUS
6
BC
-'---
PROGRAM
ADDRESS BUS
I
I
Z80 PIO
BIPOLAR PROM
SOCKETS
PROG
DATA
DRIVERS
I
I
'--
zao"
PPB Block Diagram
SPECIFICATIONS
E/PROM Sockets
One 16-Pm Zero Force Inserhon
Two 24-Pm Zero Force InsertIOn
E/PROM Types
24-Pm MOS
2704 (512 x 8) PPB
2708 (1024 x 8) PPB
2716 (2048 x 8) PPBIl6
24-Pm BIpolar
7640 (1024 x 8) PPB
7641 (1024 x 8) PPB
82S140 (512 x 8) PPBIl6
82S141 (512 x 8) PPBIl6
82S180 (1024 x 8) PPB/16
82S181 (1024 x 8) PPBIl6
82S2708 (1024 x 8) PPB/16
16-Pm BIpolar
7610 (256 x 4) PPB
7611 (256 x 4) PPB
7620 (512 x 8) PPB
7621 (512 x 8) PPB
82S126 (256 x 4) PPBIl6
82S129 (256 x 4) PPBIl6
82S130 (512 x 4) PPBIl6
82S131 (512 x 4) PPBIl6
Control Interlace
TTL Interface WIth MCZ Senes Data,
Address and Control SIgnals
Connectors
122-Pin Edge (100 mIl spacmg)
Power
+5 V ±5'10 @
2.5 A durmg Programmmg
1.5 A durmg Read
Environmental
Temperature
HumIdity
Physical:
HeIght
WIdth
o to 50°C
o to 90% noncondensmg
9.0 m. (229 mm)
7.7 m. (196 mr'l)
ORDERING INFORMATION
Part No.
05-6005-01
05-6079
464
Description
Z80 PPB
PROM Programming Board
Z80 PPBIl6
PROM Programmmg Board
1045·001
1045-002
00·1045-A
Z80®pMB
Z80 PROM Memory Board
~
Zilog
Product
Description
March 1981
II Flexible Application
iii Allows several types of E/P/ROMs
Ii> Vanable address selecllOn
I!II Includes Z80 PIO and CTC Devices
for I/O Expansion
III! Allows Expansion Up to 32K Bytes
of Non-volatile Memory
III! Fully Buffered for Compatibility
with All MCB Family Boards
OVERVIEW
The Z80 PROM Memory Board
(PMB), desIgned for memory expanSlOn
m systems whICh reqUIre a large
amount of hxed memory, provIdes up
to 32K bytes of hxed program or data
storage. Completely compahble wIth
the Z80 MCB, the PMB is mterchangeable wIth other memory boards
wlthm the MCB famIly.
FUNCTIONAL DESCRIPTION
Memory Array. The PMB contams 16
24-pm sockets to accommodate a vanety of E/P/ROM devIces as shown m
Table 1. FlexIbIlIty m the selechon of
the devIce type is provIded m the form
of Jumpers that may be mstalled on a
16-pm component carner. ChIp selechon logic allows each socket wlthm the
array to be conhgured to have a
UnIque address startmg on IK byte
boundanes. In addlhon, each socket
may be programmed to have eIther a
lK byte or 2K byte granulanty dependmg upon the memory devIce chosen.
Chip seleclion IS accomplIshed by a
paIr of socketed 32 X 8 PROMs.
Parallel 110. An on-board Z80 PIO
device provides addllIonal system I/O
vIa 16 status or data lInes whIch may
be configured mdlvldually or m two
groups of eIght. (See Z80 PIO Product
Speclficalion for addlhonal detaIls.)
There are two sets of Ready-Strobe
handshake Imes for each group of IIO
Imes. DrIvers for both ports are provIded for use m the output mode; termmahon resIstor sockets are avaIlable
for use m the mput mode.
Device
Number
Non-Volatile
Memory
MOS
EIPROM
BIpolar
P/ROM
2704
2708
2716
8704
8708
2316
6341
6381
82S181
82S191
Table I. Non-Volatile Memory Devices
465
Counter/Timer. An on-board 280
Counter/Timer ClfCUlt provides
expanded timing capability. The 280
CTC Includes four Independent 8-bit
counter/timers and can be programmed by system software for event counting, Interrupt and Inte-rval hmIng, and
general clock rate generahon (See ZeG
eTe Product Specifico/lOn for specific
details.)
r--
. Jc°~~~~i~U~
-I
CONTROL BUS
ADDRESS BUS
CONTROL
I 1
8.1
.I ADDRESS
DECODE
eTC 110
.
SYSTEM
BUS
Port Assignments. The chIp select
logic allows each of the two I/O
devices (CTC and PIO) to be located
withIn anyone of eight port assIgnment
blocks each containing 20H bytes for
I/O locations. Each device must occupy
four consecutive locahons withIn the
chosen block. The configuration
desired by the user IS easIly achIeved
by selecting appropnate jumpers that
reside on component carners.
INTERNAL CONTROL BUS
6
.1I
DATA BUS
o TO 32K BYTE
ROM, PROM, EPROM
MEMORY SPACE
~
DATA BUS
l
Z80 eTC
If.-
DATA BUS
BUFFER
PORT A
8
PORT AlB CONTROL
PORT B
INIOUT
INTERNAL DATA BUS
TAI·STATE
BUFFERS
L
PORT A
.
CONTROL
,
Z80 PIO
PORT B
8
'---
'---
L......
zao'"
PMB Block Diagram
SPECIFICATIONS
Memory Capacity
32K (Populated wIth 2K DeVIces)
E/P/ROM Socket Array
Number 16 (24'pm)
E/P/ROM Device Types
2708, 2716, 6381
Parallel I/O
Number of Lmes-16 (Programmable)
Operatmg Modes-Input. Output,
BIdIrectIonal, BIt Control
Handshake Lmes-Ready, Strobe
Interrupt Vectors-2 (User Program·
mabIe)
Counter. Timer
Channels
4 (8 BItS Each)
Interrupt Vectors
4 (User Programmable)
Connector
122·Pm Edge (100 mIl spacmg)
Power
+5 V ±5%
@ 0.60 A
@ 2.28 A
@ 3.40 A
@ 0.84 A
(max)
(max)
(max)
(max)
wIthout Memory
2716
6381
2708
-5 V ±5%
@ 0.96 A (max) 2708
+ 12 V ±5%
@ 1.28 A (max) 2708
DC-DC Converter Output
+12 V @ 320 mA (max)
-5 V @ 50 mA (max)
Environmental
Temperature
HumIdIty
0 to 50 'C
0 to 90% noncondensmg
Physical
HeIght 7.5" (191 mm)
Width 7.7" (196 mm)
ORDERING INFORMATION
Part No.
05-6023-01
Description
zao PMB
PROM Memory Board
466
1032·001
00·I032·A
~80®MDC
Z80 Memory and Disk
Coniroller Board
Product
Description
March 1981
III CRC Error Checking for Reliable
Data Transfer
Ea Control Signals Allow Expansion
Up to Eight Full Size. Single Density Floppy Disk Drives
D Memory Array Allows Complete.
Compact System Integration
Ell Reliable and Proven Frequency
Modulation Recording Technique
IIiIl CPU-Controlled Access Allows
Complete Software Flexibility
!iii Low-Power Operation from a
Single +5 V Supply
OVERVIEW
The Z80 Memory DIsk and Controller
(MDC) board IS a floppy dIsk controller
capable of handlmg up to eight floppy
dIsk dnves and provldmg sockets for
16K to 48K bytes of addihonal mam
system memory. A member of the MCB
famliy. the MDC IS completely compatible wIth the other mICrocomputer
boards m the series.
The MDC IS most effechvely used
wIth the MCB/16 MIcrocomputer
Board. Together these two boards compnse a complete mICrocomputer system
that mcludes 64K bytes of RAM, 4K
bytes of PROM, parallel mterface,
serial mterface, and control of up to
eight floppy dIsk dnves-on a 115 sq.
in. cIrcuit board whICh operates from a
smgle +5 V power supply.
FUNCTIONAL DESCRIPTION
Memory Array. The memory array is
implemented usmg 16K x I-bit
dynamIC RAM deVICes to provIde 16K
bytes to 48K bytes of mam system
memory. Although dynamIC RAMs are
used in the memory array, addlhonal
refresh cirCUItry IS not reqUIred due to
the umque memory refresh charactenshc of the MCB CPU. Followmg each
op-code fetch, a new refresh address IS
available on the system address bus
whlie the op-code is bemg decoded
wIthin the processor.
An on-board dc-dc converter
generates the -5 and + 12 V sIgnals
for the dynamic memory deVIces,
enabhng the MDC board to be
operated from a smgle +5 V power
supply.
467
Memory address selechon IS completely compahble with the MCB/16.
ThIs two-board combInahon provides
64K bytes of contInUOUS memory wIthIn
the address space of the MCB CPU.
For maxImum fleXIbIlIty, the RAM chip
select logic is desIgned to allow the
memory to be addressed in 4K byte
blocks that may be located anywhere
withIn the address range of the CPU.
Chip selechon IS accomplIshed USIng a
PROM decoder to select the Row
Address Strobe (RAS) sIgnal to the
appropnate bank of devIces. ThIs
address select PROM IS socketed so
that It may eaSIly be replaced by the
user for address reassIgnment.
The MDC includes a CRC used during read and wnte operahons. ThIs cIrcuit generates a l6-bit word whIch is
appended to the end of the data stream
durIng wnte operatIOns. Durmg read
operahons a l6-blt word is again computed and then compared with the
value previously written on the disk. A
CRC error condition causes an error
flag to be read Into the CPU through
the PIO Interface.
Data is recorded onto the floppy
dIskette m a serial format. Parallelto-serial and senal-to-parallel data
conversIon is performed by on-board
cIrcuitry. During the frequency
Disk Control. The dIsk control signals,
formattIng information and data
transfer are provIded by the CPU
under program control. A PIO device
is used as the interface element to
transfer dIsk control and status informahon between the CPU and the control
cIrcuitry on the disk dnve units. DIsk
status signals include READY, TRACK
0, SECTOR MARKER, WRITE PROTECT, and CRC ERROR. The control
signals are DIRECTION, STEP, four
DISK SELECT lines, READ, WRITE,
and ENABLE CRC.
r--
FORWARD/BACKWARD
LINKAGE FOR FILE
MAINTENANCE
1 BYTE
•
SECTOR ADDRESS·
100 A4A3A2A1Ao
DISK READ DATA
1 BYTE
o TO
"
•
J
48K BYTE
DYNAMIC RAM MEMORY
I
SPACE
J
I
DATA
SEPARATOR
•
BUS
DISK CONTROL
I
zeo
PIO
DISK WRITE DATA
I
I
'--
2 BYTES
TRACK ADDRESS·
0 A6AsA4A3AzA1Ao
l
J
WAIT CONTROL
PARALLEl
TO SERIAL
REGISTER
I
I
DATA
I
I
CPU CONTROL BUS
WAIT LINE
4 BYTES
•
SYSTEM
DISK STATUS
128 BYTES
Figure I. Sector Data Format
BUFFERED DATA
BUFFEREO ADDRESS
modulahon recording mode, each data
bl t recorded on the dIskette has an
assocIated clock bit recorded.
Formathng of serial data into the
disk is accomplIshed under program
control by the MCB CPU. Optional
PROM-based firmware to control up to
two Shugart 80lR Floppy Disk Drives
is available from Zilog. This lirmwave
assumes that 32 data sectors (records)
are utilized per track and 77 tracks
are utilized per disk. The lirmwave
prOVides all control functions for the
dIsk and performs all data transfer. The
sector data format is illustrated In
Figure 1.
~
CIRe
GENICHK
DATA
ENCODER
I
I-
~
Z80 MDe Block Diagram
468
1035-001. 002
SPECIFICATIONS
Disk Drive Capability
8 Smgle-Slded Dnves
Memory Capacity
48K Bytes
Power
Disk Drive Characteristics
Sector Type
Hard
Smgle DensIty
Recordmg
Sectors per Track
32
Tracks per DIsk
77
CapacIty
308K Bytes Data
Memory Configurations
16K, 32K, or 48K Bytes DynamIc RAM.
Each 4K page may have ItS startmg
address assIgned to any of 16 possIble
values.
Environmental
Data Transfer Mode
Programmed 110
Connectors
122-Pm Edge (100 mIl spacmg)
+5 V ±5% @ 1.6 A max.
Temperature
HumIdIty
Physical
HeIght
W,dth
o to 50'C
o to 90% noncondensmg
7.5" (191 mm)
7.7" (196 mm)
ORDERING INFORMATION
Part No.
Description
Part No.
05-6011-04
280 MDCIl6
16K Memory and DIsk
Controller
05-6011-03
00-103SA
Description
280 MDC/32
32K Memory and Disk
Controller
Part No.
05-6011-02
Description
280 MDC/48
48K Memory and DIsk
Controller
469
Zilog
Developmenl Systems
il
Comprehensive Development
Environments for
All Zilog Microprocessors
Innovative Design. Zllog's development system products feature ideal
environments for software development
for the za, Z80, and Z8000
microprocessors. The modularized
design approach of the Zilog development systems allows the user a chOice
of hardware and software modules to
meet current needs, while providing
the necessary upgradability for future
requirements.
Proven Components. The PDS 8000
Family and ZDS-l Family of development systems provide development
support for the za, zao, and zaooo
microprocessors. The PDS 8000 systems
are software development stations,
while the ZDS-l systems contain integrated zao emulators, whICh permit full
hardware and software debugging of
the zao target system. Each of these
systems offers variable configurahon
choices and extra card slots for additional peripherals. Ample provisions
have been made for the expansion of
memory, disk storage, PROM programming, and external mterface. And each
system is supphed With Zilog's lieldproven RIO operating system and the
necessary utilities.
The Z-LAB 8000, Zilog's newest
development system, offers multi-user
capabilities With ZEUS, a UNIX· -based
operating system With the 6MHz
Z80lOA microcomputer. The Z-LAB
8000 mcorporates 2~M bytes of reliable
Winchester disk storage, a cartridge
tape backup facility, and 256K bytes of
error-correcting memory to represent
the programmer's ideal development
system.
In addition to the standard development system configuration, several
optional modules are also available for
system enhancement.
Hardware. The Z-SCAN 8000 Emulator
provides in-Circuit emulahon for the
Z8001 or za002 16-bit microprocessors
and may be used as a stand-alone unit
or as a peripheral to a host CPU such
as the Z-LAB 8000 andlor a CRT.
The za and Z8000 Development
Modules are complete single-board
microcomputers that permit the
development of code for the za or
zaOOO. They facilitate prototyping with
large wire-wrap areas and are totally
transparent to the CRTs and host CPU
systems.
Software. To faCilitate program
development, Zilog offers the complementary PLZ apphcation languages,
PLZlSYS and PLZIASM. Similar con-
structs within the PLZ languages permit
the user to combine high-level,
machine-independent modules together
with machine-dependent modules.
PLZlSYS IS a procedure-oriented
language with a style that blends
elements of other well known
languages such as Pascal, ALGOL,
PUI and C.
PLZIASM is a structured assembly
language that provides all the
capabilities needed to manage the
mlcroprocessor resources such as
registers, memory accesses, and 1/0
operations.
This modular programming techmque enables the programmer to concentrate on program design rather than
on development system software.
The Z8000 Cross-Software Package,
running on UNIX·, enables multi-user
access for enhanced software development. The package consists of a complete set of software tools for developing zaooo programs on DEC's
PDP-1l/44, 11145, and llno systems.
The C language, including compiler
and code optimizer, protects the user's
software investment by permitting program transportabihty.
• UNIX
IS
the
trademark of Bell LaboratorIes.
473
ZDS·1/25
Development System
~
Zilog
Product
Description
March 1981
• Full Development Support for the
Z8()® Microprocessor.
• EPROM-based Monitor/Debug
Software.
• In-Circuit Emulation up to 2.5
MHz.
• Memory Mapping Allows Borrowing of System Resources before
Prototype Memory Is Available.
OVERVIEW
The ZDS-1/25 Development System is
a cost-effective development aId providing total desIgn and prototYPlng
capability for zao CPU-based systems.
This capablhty enables the user to
develop Z80 code before prototype
hardware IS bUIlt. Once prototype
hardware is available, the ZDS-1/25
system can then be used as an incircuit emulator to allow Integrahon of
software and hardware.
FUNCTIONAL DESCRIPTION
The ZDS-1/25 Development System
consIsts of two functional parts: a soft-
ware development system and an InCIrcuit emulation subsystem.
Software Development. As a software
development system, the ZDS-1/25
includes a zaO-based mIcrocomputer,
60K bytes of dynamIc RAM, an EPROM
monitor, floppy dIsk controller, senal
RS-232C console Interface and dual
Single-sIded, Single-denSIty floppy dIsk
dnves. Zilog's held-proven RIOTM
operahng system IS used to edIt. assemble and modify zao code.
WIth relocatable modules, I/O
management and general-purpose computing power, the RIO operahng
system faClhtates both the development
process and the expansIOn of system
features to meet indIVIdual user needs.
RIO's main features Include an OS
execuhve, relocahng macro assembler,
linker, text edItor and ZDOS II hie
manager.
OS Executive. The OS executive
handles 110 requests, dynamically
allocates system storage areas to active
programs on an "as needed" baSIS and
invokes programs In response to
operator commands.
g
Relocating Macro Assembler. The
relocating macro assembler permits
external symbol references, global
symbol definitions and conditional
assembly.
-...
¥J
N
Linker. The linker resolves external
references and assIgns absolute
addresses to program modules, thereby
creating executable code. The hnker
also permits overlays and produces a
memory map and a global address
table.
Text Editor. A line-oriented text editor
can handle files or programs larger
than the available memory space. All
operations within a hie are based on
character string matching to allow
quick and easy search and modificahon
of text. The capability to access other
hies during an edIt sessIon saves the
repehtive entry of commonly used
routines and enables the user to bUIld
libraries of commonly used code. Automahc backup of an existing file
prevents accidental destruction of
valuable data.
475
en
ZDOS II File Manager. The file
manager organizes, stores and
retrieves data from the floppy disk
umts. A directory provides a data
index which is accessed using a
"hierarchical linked Its!." All space on
the disk is dynamIcally allocated on an
as needed basis to prevent gaps in the
storage space. LogIcal record lengths
from 128 to 4096 bytes per record may
be used. Also, all files may be assigned
one or more attributes for protection
and privacy.
In-Circuit Emulation. Once the software development task is complete, the
ZDS-1/25 may be switched to the User
mode to function as an in-circUIt
emulator. In this mode of operation,
the system CPU becomes the emulator
CPU and, in conjunchon with the user
interface module, monitor module and
real-time trace module, provIdes full
real-time emulation up to 2.5 MHz.
In the Emulator mode, 60K bytes of
system memory, system peripheral
devices and I/O ports (with the
exception of EO Hex through EF Hex)
may be wholly or partially used by the
user target system. The development
system is connected to the user's target
system via a three-foot emulator cable
and 40-pin DIP plug.
As a standard part of the emulation
package, the ZDS-1/25 system includes
a mapper utility and EPROM-based
monitor/debug firmware allowing realtime execution, trace and debug.
FFFF
RAM SCRATCH PAD
F8FF
3K DEBUG PROM
FOOD
NON· EXISTENT
MEMORY
2FFF
MEMORY
ALLOCATED TO
USER'S SYSTEM
~
1\
r-------ADDRESSES MAI'Peo
TOZO!>t125
MEMORY
(4098 BYTES)
r-- - -- - - - -
~
1FFF
'FFF
UNDEVELOPED
~
1FFF
PROTOTYPE
MEMORY
(4098 BYTES)
OFFF
r--------
11
MEMORY
ALLOCATED TO
USER'S SYSTEM
II
1\
ADDRESSES MAPPED
TOZD$~m
~
0000
OFFF
PROM AREA
(4098 BYTES)
,
~---U-SE-R-'S--"'" 0000
DEVELOPMENT SYSTEM
ADDRESS SPACE
ADDRESS SPACE
Figure I. ZDS-1/25 Memory Mapping
Mapper Utility. The mapper uhlity
allows the nature of memory used during emulation to be described. All or
part of the memory used may be mapped to the ZDS-1/25 system memory or
target system memory. Mapping occurs
using blocks containing 256 bytes
each. Mapped memory internal to the
system may be write-protected and programmed to cause a break In emulation
in the event of illegal access. The
memory in the ZDS-l/25 must eXIst for
the associated block being mapped In
the user's prototype system.
EPROM Monitor/Debugger. The
EPROM-based momtor provides the
capabihty to control, analyze and
debug software which may reside in
either Internal system memory, external
target system memory or a combination
of the two. The monitor command
package consists of the follOWing functional groups: Execution, such as GO,
GET, SAVE and JUMP; Register/
Memory Manipulation, such as
DISPLAY, REGISTER and COMPARE;
Input/Output; and Debug, such as
BREAK, TRACE and HISTORY.
Floppy Disk Storage (Contmued)
Physical
SPECIFICATIONS
CPU
Z80 CPU
Memory
60K Bytes User Memory Space
(DynamIC RAM)
Word Size
8 BIts (J Byte)
Clock Rate
2.S MHz Crystal Controlled
Interrupts
Three modes mcludmg vectored,
nonvectored and nonmaskable
Option Card Slots
Two (2)
Floppy Disk Storage
CapacIty
300,000
bytes/drIve
Type
Smgle-slded,
smgle-denslty
hard-sectored
ORDERING
Part No.
05-6030-05
05-6030-06
476
MaxImum CapaCIty
600,000 bytes
(dual drIves)
Transler Rate
2S0K hIts/s
Average Latency
83 ros
Track-to-Track Seek
10 ros
Average Access TIme 260 ms
32 sectors/track,
PhYSIcal Sectors
77 tracks
IN-cmCUlT EMULATOR
2.S MHz
Clock Rate
Hardware
Trigger
Real-T,me Trace
Module
Emulator Cable
Break on
Address
2S6 X 36 WIde,
hIgh-speed
stallc RAM
3 It. (91 cm)
HeIght
Width
Depth
Weight
10.0
19.0
16.0
6S.0
m. (2S.4 cm)
in. (48.3 cm)
m. (40.6 cm)
lbs. (29.S kg)
Power
110 V/SO Hz @ I.S A
220 V/SO Hz @ 0.9 A
110 V/60 Hz @ 1.8 A
Environmental
Operatmg Temperature 0° to 40°C
Storage Temperature
0 ° to 85 °C
H,:,midity
20 to 80%
noncondensmg
I
INFORMATION
Description
ZDS-l/25 Development System (60 Hz)
ZDS-l/25 Development System (50 Hz)
1039-001
OO-1039-A
ZDS·1/40
Development System
~
Zilog
Product
Description
March 1981
N
ill
•
...
--I
~
\
\
. _ . w , i . l l iil
.,..
.. . . . )
• Full Development Support for the
Z80® and Z80A Microprocessors
• 64K Bytes of Memory to Support
Large Programs
• 600K Bytes Floppy Disk Storage
• In-Circuit Emulation up to 4 MHz
• Memory Mapping Allows Borrowing of System Memory Before Prototype Memory Is Built
• ZAP Package Provides Interactive.
Symbolic Debugging With
Disassembly
assist in every phase of software
development.
Included with the powerful
prototype, and mimmlze the problems
encountered m mtegratmg software
wlth hardware. Interachve debug software-the ZAP package, provlded wlth
the emulation system-allows debuggmg of the prototype, full dlsassembly
of memory data and trace mformahon,
the use of symbolic references, and the
capabllity of placing all debug commands on disk for execuhon.
OVERVIEW
The ZDS-l/40 Development System
provldes total development support for
Z80 and Z80A CPU-based system
deslgns. Thls support begms With a
complete Z80-based microcomputer
system that includes 64K bytes of RAM,
dual single-slded, smgle denslty floppy
disk dnves and system software to
microcomputer IS an In-CIrCUIt emu la-
han subsystem whiCh connects to the
user's prototype to monitor the execution of the software, control the
behavior of the miCroprocessor m the
FUNCTIONAL DESCRIPTION
The ZDS-l/40 Development System m
effect consists of two functional parts: a
software development host and an mClrcuit emulahon subsystem.
Software Development. The software
development host is a Z80-based
general-purpose mlcrocomputer with
3K bytes of EPROM, 64K bytes of
dynamlc RAM, a floppy dlsk controller,
senal RS-232C console mterface, and
two single-slded, single density floppy
disk drives.
477
I
Included with the microcomputer
system is Zilog's RIOTM Operating
System and System Uhlities. This set of
tools provIdes the user wIth the full
capability of carrying out the various
development tasks from the mputting
and assembly of source code to the
printing of listmgs and the creation of
EPROMs. The RIO operatmg system is
designed to provide the user with the
capabihty of tailoring commands and
inihalization routines to suit the needs
of the specific application. The mam
features of RIO include a PROM-based
monitor, OS executive, ZOOS II file
manager, text edItor, Z80 relocating
macro assembler and linker.
PROM-Based Monitor. 3K bytes of
nonvolatile storage provide system
primitives for communication wIth
floppy disk and console devices, and
contain the bootstrap routme for the
system.
OS Executive. The executive IS the
focus of system activIty and thus
handles 1/0 requests, dynamically
allocates system storage areas to active
programs on an "as needed" basis and
invokes programs in response to
operator commands.
ZDOS II File Manager. The file
manager organizes, stores and
retrieves data from the floppy disk
units. A directory provides an mdex for
the data, which is accessed using a
"hierarchical linked hst." All space on
the disk is dynamically allocated on an
"as needed" basis to prevent gaps in
the storage space. Logical record
lengths from 128 to 4096 bytes per
record may be used. Also, all files may
be assigned one or more attributes for
protection and privacy.
Text Editor. A line-oriented text editor
can handle files or programs larger
than the available memory space. All
operations within a file are based on
character strmg matchmg to allow
quick and easy search and modification
of text. The capability to access other
files during an edit sessIOn saves the
repetitive entry of commonly used
routines and enables the user to build
hbraries of commonly used code. Automatic backup of an existing file
prevents accidental destruction of
valuable data.
Z80 Relocating Macro Assembler. The
relocahng macro assembler prOVIdes a
qUIck way to create Z80 code in a
modular fashIOn. Its deSIgn supports
absolute or relocatable object code formats, global deflnlhons, external
references, macros and condihonal
assembly. Ophonally, a cross-reference
andlor symbol table IS hmited only by
478
available storage on the disk. All
diagnoshc messages are routed to the
system console with pertinent line
number, error and the statement Itself
so that there is no waitmg for a listmg
to locate erroneous statements.
Z80 Lmker. The Z80 Linker provides a
means to link various program modules
together and resolve communication
between global modules, described by
external references. The result is the
generation of a single, executable program with absolute addresses. The use
of the linker allows mdlvidual modules
to be built and debugged, then merged
with others wIthout performmg a complete assembly.
System Utilities. All of the software
used to drive or control the various
accessory boards available is included
with the system. There is no need to
write software to commUnicate with
prmters or PROM programmers
because It is already completed. The
source code for the uhlities is included
so that the user can supplement or
custom-tailor the software.
In-Circuit Emulation. The in-circuit
emulation subsystem enables the software developed on the microcomputer
to be debugged before the hardware
prototype is completed and even while
the prototype is nonexistent. Resourcelending capabilities enable the software
to be tested in the prototype hardware
before it is completed. After the hardware is complete, the emulation subsystem allows total integration and
testmg to occur in a real-time environment. The subsystem consists of a trigger or breakpoint module, a monitor
module, a user pod controller, a user
pod, and a Z80A emulator CPU.
Hardware trigger capability enables
searching for a specific condition while
the software is executing in real time,
and executing breaks when detected.
The detection can also be used to generate a sync pulse to trigger other
instruments, such as oscilloscopes or
logic analyzers used in the debug
process.
Monitoring Functions. The emulation
subsystem provides a means of
monitoring the interaction of the
microprocessor with the target design.
A special high-speed trace memory
records the microprocessor's bus achvity, while running the software in real
time. The contents of the memory may
then be dumped on the console after
emulation has been halted for subsequent debug. The output of the trace
memory can be dIsplayed in three
available formats. The user may quahfy
the inputs to the trace memory to select
the speCific type of bus cycle to be
recorded, such as a memory write or
an 1/0 operation.
Resource Sharing Functions. The
ZOS-I!40 system allows the user to borrow memory resources so that testmg
can begin even before the hardware is
complete.
The system prOVIdes a memory mapping mechanism, whereby the user can
describe the addressable memory
space of the microprocessor. This
memory space is divided into blocks,
each containing 1024 bytes of contiguous memory addresses. These
blocks may be described to eXIst m the
user's prototype, m the development
system memory, or not to eXIst at all.
All commands executed to examine or
modify memory are quahfied by the
mapping mechanism.
The mapping mechanism also allows
hardware write protection of any block.
Any attempted write to a wrlteprotected block will be reported as a
write violation and will terminate program execuhon without causing overwrites to the block. The nonexistent
memory feature enables the user to
declare blocks of memory nonexistent.
Any attempt to access these blocks will
immediately terminate program execution with a nonexistent memory violation message.
Emulation occurs by removing the
Z80 or Z80A mICroprocessor from the
prototype and replacing it with the
Z80A Emulator CPU of the development system. This emulator is connected to and controlled by the emulation subsystem. Monitormg and
,resource lending capabilities provided
by the emulation subsystem also
simphfy the development process.
Emulation Functions. The emulation
subsystem provides several functions
extremely useful to software and hardware designers: I) control of the microprocessor in the hardware prototype; 2)
the ability to mOnitor the bus signals of
the microprocessor and record them;
and 3) the ability to lend development
system resources to the user's hardware
prototype.
Control Function. The cable connection between the user's prototype and
the development system allows start!
stop control of the Z80A CPU Emulator.
This feature enables the user to execute
the software in a normal run mode,
single-step the software, or execute
multiple instructions. When the
emulator is idling or not running the
user's software, it generates the
necessary refresh timmg signals to
keep dynamIC memory m the prototype
alive. Control of the microprocessor
also allows the user to examine or
modify CPU registers, memory or 1/0
devices.
SPECIFICATIONS
SW HOST
CPU
Z80 CPU and ZSOA Emulator CPU
Memory
64K bytes (3K EPROM, IK statIc RAM,
60K dynamlc RAM)
Word Size
8 blts (I byte)
Clock Rate
2.5 MHz crystal-controlled
Interrupts
Three modes mcludmg vectored,
nonvedored and nonmaskable
Option Card Slots
F,ve (5)
Floppy Disk Storage
Capaclty
300,000 bytes/dnve
Type
Smgle-slded, smgle
IN-CIRCUIT EMULATOR
Clock Rate
4 MHz
Tngger
Break on address
Real-hme trace
256 X 36 blls wlde,
module
hlgh-speed statIc RAM
EmulatIon cable
6ft.
(mcludmg pod)
(1.82 m)
PHYSICAL
System
Height
Depth
Weight
Width
10.0 m.
19.0 m.
16.0 m.
35.0 lbs.
(25.4 cm) (48.3 cm) (40.6 cm) (15.9 kg)
DIsk Umt
Depth
Height
Width
Weight
10.0 m.
19.0 m.
16.0 m.
35.0 lbs.
(25.4 cm) (48.3 cm) (40.6 cm) (15.9 kg)
POWER
System
Frequency
50 Hz
50 Hz
60 Hz
DIsk Umt
Frequency
50 Hz
50 Hz
60 Hz
ENVIRONMENTAL
Operating
Voltage
110 Vac
220 Vac
110 Vac
Current
Voltage
110 Vac
220 Vac
110 Vac
Current
Storage
Relative
Humidity
20 to 80%
Temperature
Temperature
0° to 40°C
0° to 85°C
1.5 A
0.7 A
1.5 A
15 A
0.7 A
1.5 A
noncondensmg
densIty hard-sectored
600,000 bytes
(dual dnves)
260K b/s
I
MaXlTIlUID
Capacity
Transfer Rate
Average Latency
83 ms
Track-to- Track Seek
10 ms
Average Access TIme 250 ms
Physlcal Sectors
32 sectors/track,
77 tracks
ORDERING INFORMATION
Part No.
Description
05-6013-05 ZDS-1/40 Development System (60 Hz).
05-6013-06 ZDS-1/40 Development System (50 Hz).
ZILOG ANALYZER PACKAGE (ZAP)
EMULATION SOFTWARE
Product Overview. The Zilog Analyzer
Program is a sophlshcated software
module used to operate the emulahon
hardware of the ZDS-1I40 Development
System. ZAP provldes full control over
the emulation hardware for qUIck and
easy debugging of Z80- and Z80Abased deSIgns. ThIS module allows the
user to mspect the mIcroprocessor and
to mteract WIth the prototype system.
The regIsters, user or system memory,
and I/O ports may be mterrogated and
controlled. Control of program execuhon, mterrupt, and DIrect Memory
Access (DMA) achvlty IS also provIded.
These features, combmed with full symbolIc debugging and disaaembly capabIlIty, provIde powerful debugging
tools for the Z80 mIcroprocessor.
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Functional Description. The ZIlog
Analyzer Program IS a dIsk-resident
program used to control the Z80/Z80A
emulation hardware of the ZDS-1/40
Development System. It provIdes an
interface between a command source
and the emulallon hardware. Commands may therefore be supplIed from
the dIsk hIe system (command hIe),
system console deVIce or a control program. ThIS provides fleXIbIlity in hardware debuggIng as well as testing
applications.
ZAP provIdes a complete spectrum of
commands and data formats to enable
prototype hardware and software to be
qUIckly mtegrated and debugged. A
simple command syntax, using abbreviated command words, provIdes ViSIbilIty mto the Z80's registers, user
memory, system memory, user I/O
ports, and CPU status. MIcroprocessor
regIsters may be dIsplayed and altered
indiVIdually, or the complete regIster
set may be dIsplayed, Commands for
accessing user or system memory
include FILL, SET, DISPLAY, and
ALTER. A block compare command IS
also provIded for comparison of a
gIven string with memory. All memory
data may be dIsassembled to reflect the
actual source code mnemOnICS and
symbolIc references if the symbol table
for the code IS avaIlable.
Emulator Start/Stop Control. The use
of ZAP and the ZDS-1/40 emulation
hardware allows the user to control the
start up and shut down of the Z80A
Emulator CPU. Emulation is mihated
by the GO command and contmues
unlIl one of the followmg condihons
occurs:
• One of eIght different software
breakpomts IS encountered
• Hardware breakpoint compare
• Operator intervenhon (manual
break)
• Bad clock deteclIon (m target
system)
• Non-eXIstent memory access
• Write-protect VIOlation
479
The user may select single step or
multi-step executIon of the program
under test. ThIs enables the registers to
be examined after each step operation.
In multi-step mode a group of mstructions may be executed in real time.
Any group of up to 255 mstructions
may be multi-stepped before stoppmg
the emulator.
Memory Mapping. The memory mapping capabilities of the ZDS-J/40
Development System are easily manipulated by ZAP. Blocks of memory, each
contaming 1024 contiguous bytes, may
be assigned to exist in the user's
system, m the development system at
the normal address, m the development
system with a translated address, or not
to exist at all. In addItIon, these blocks
of memory may be hardware writeprotected to assist m the debugging
task and prevent accidental destruction
of data.
Disassembly CapabIlity. User memory,
system memory, and the trace memory
of the development system may be displayed in the hexadecImal or dIsassembled format. In dIsassembled format,
480
the instructions are displayed in both
hexadecimal machine code and assembly language mnemonics.
Symbolic Debugging Capability. Symbol tables for each program module
may be loaded individually, or the
entire symbol table for the program
may be loaded. The user may define
local symbols to assist in the debugging process.
Symbols are loaded into development system memory and are automatically hardware write-protected to
prevent accidental destruction. A maximum of 29K bytes of system memory
may be used for the symbol table: this
equals approximately 3000 symbols.
Since development system memory
may be shared with the user's prototype system, the maximum symbol
table size is a function of the number of
blocks allocated for use in the user's
prototype hardware.
The use of symbols in place of
numeric values in the ZAP command
syntax, teamed WIth dIsassembly,
enables the user to have an electronic
listmg of the program under test. ThIS
allows the user to concentrate on the
debugging task instead of havmg to
struggle WIth the development system
software.
Command File Capability. The Zilog
Analyzer Program is structured to
accept command input from several
sources: console, file, or program. ThIS
capabIlity is Important in the debugging process, the training process, and
even the manufacturmg test process.
In the debugging process, commonly
used commands for establIshmg the
memory map, enablmg mterrupts, and
loading program modules may be
placed in a dIsk file and executed. This
allows a series of necessary operations
to be performed with a minimum
number of keystrokes. It also msures
that the system will be mitialized the
same way, no matter how many individuals are using the system.
The same technique may be used for
training new users of the ZAP command structures. Tutorial files can be
created to execute the various system
commands and illustrate the results. An
example of this IS ZAP TUTOR, a software traimng package mcluded with
ZAP to acquamt the user with the commands and theIr use.
In a manufacturing test operation,
the user may create software which formats command parameters for ZAP and
pass these USIng a CALL to ZAP. The
ZAP software will perform the
requested operatIon and return the
results to the calling program. This
enables the user to dIagnose desIgns
using the emulatIon hardware controlled by applicahons software.
OO·W40-A
PDS 8000™
Development Systems
~
Zilog
Product
Description
March 1981
~
II SUPPORTS entire family of Zilog
microprocessors - Z8™, Z80@ , and
Z8000™.
fI2
00
C
C
C
II SPEEDS program development
with high-level. structured
assembler.
II EXTENDS system capability with
an intelligent CRT console.
II EXPANDS to allow full emulation
and debugging.
II PROVIDES either Iloppy or cartridge hard disk back-up data
storage.
FUNCTIONAL DESCRIPTION
System Hardware. The PDS 8000
Senes consists of several models of
single-user systems for the design,
development, and debug of Zllog
mlCroprocessor-based systems. The
PDS 8000 is a Z80-based microcomputer system with 64K bytes of RAM, a
disk controller, parallel prmter interface, and an mtelligent CRT console.
A vanety of configurations allows the
selection of unbundled hardware
options or a complete package of hardware, development software, and a
development module. A choice of one
of the following types of disk drives IS
available in the standard PDS 8000
configuration.
II A dual, floppy-disk drive unit with
600K bytes of hard-sectored storage
capacity.
II A cartridge disk drive with 10M
bytes storage capacity (5M bytes
removable).
Dual Floppy Disk Drive. The floppy
disk drive IS interfaced to the microcomputer via the Z80 Memory Disk
Controller (MDC), which provides the
Z80 microcomputer with all the data
formattmg required for readmg and
writing onto the floppy disks from RAM
storage. Disk read/write accuracy IS
ensured by 16-bit CRC-code circuitry.
Wait control logic synchronizes the
speed of the CPU to the disk read or
write speed by setting the CPU wait
line to an achve state until a complete
byte of data IS assembled. The MDC
employs a parallel interface to control
the disk drives and to provide status
informahon to the CPU. The MDC also
prOVides 48K bytes of dynamlC RAM
memory for programs or data storage.
Cartridge Disk Drlves. The cartridge
disk drive IS interfaced to the microcomputer via the Hard Disk Interface.
The Hard Disk Interface is an mtelligent disk control unit that provides
control for up to lour cartridge disk
drives. It consists 01 a 280 Direct
Memory Access (DMA) penpheral
device, software-delmed hie data bufler, and read/write control logic on
lour PC boards. Primary control 01
hard disk operahons is exercised by a
reSident processmg system, which
includes a Z80 microprocessor CPU,
16K bytes 01 high-speed stahc RAM,
and CPU support Clrcuitry.
The Hard Disk Interface to the host is
compnsed 01 a pair 01 Z80 Serial Input!
Output (SIO) chips and a Z80 Counter!
Timer Circuit (CTC). One SIO device
connects to the hard disk interlace bus
and the other SIO device connects to
the host system bus.
The Hard Disk Interface executes
high-speed translers of disk files
between the disk drive and system
memory With all the necessary DMA
control intelligence prOVided by the
interlace itself. The basic responslbihty
of the mlCrocomputer host IS to download the file system software to the
Hard Disk Interface memory, and to
output disk I/O requests (also perlormed under DMA control), thus
minimizing the host mlCrocomputer's
interaction with the Hard Disk
Interface.
481
An automatic bootstrap feature
allows hIe system software to be loaded
automatically. The hard dIsk processmg subsystem serves as the central
control for all hard dIsk control functions, includmg:
System Software. The PDS 8000
System provIdes all the necessary software to handle software development
tasks, from mputting source code to
prinhng hstmgs and creatmg
EPROM's.
• Processmg messages receIved
serIally from the host CPU vIa the
SIO.
RIO Operating System. The PDS 8000
• Issumg commands such as SEEK,
READ, WRITE, etc., to the selected
drives.
• Reading the status of a selected
drIve.
• ImtIalizmg DMA circuits m preparation for dISk hIe transfers.
• Servicmg mterrupts from hard dIsk
controller elements.
• Performmg varIOUS housekeepmg
tasks required by software.
Operating System Executive. The
RIO Executive maps requests of operations on logical umts to speCific devICehandling programs. Commands may be
issued to the operating system from the
system console or by an executmg program. Any number of user-defmed
commands may be added to the
system. Command sequences may be
recorded in files and executed as a
group. The Executive manages the
allocahon of memory blocks.
utilizes Zilog's field-proven RIO
Operating System for the creation,
editing, assembly, and debuggmg of
software. RIO, VersIon 2, wIth
relocatable modules and IIO management, is a general-purpose computing
system with architecture designed to
facihtate the development process. RIO
provides straIghtforward lmking to
various system rouhnes and enables
expansIOn of system features to meet
the particular needs of indIvidual user.
RIO is composed of the folloWing
elements which aid m the development
Relocating MACRO Assembler. The
Relocating MACRO Assembler offers
relocatable or absolute object code format wIth external symbol references
and global symbol dehmhons,
MACRO's and condItional assembly.
The Assembler pages the symbol table,
permitting assembly of arbitrarily large
programs in standard memory. It also
includes a dIrechve permithng additional files to be merged with the
source at assembly hme.
process:
1----1
: CJ] :
CRT
CONSOLE
I
I
FLOPPY DISK
L _ S~R~E _ -.J
zao Mea
I
OPTIONS:
•
•
•
1 _ _ _ _ _ -"I
SERIAL 110 EXPANSION
PARALLEL 110 EXPANSION
PROMIEPROM
PROGRAMMERS
I
I
I
I
L _ _ _ _ _ _ _ _ _ _ ...JI
Figure I. PDS 8000 Development System
482
1020·00 I, 002
Linker. The Lmker assigns absolute
addresses to program modules,
resolves external references, permits
overlays, and produces a load memory
map with a global address table.
Text Editor. A line-oriented Text
Editor pages work space so that files of
any size can be edited and also provides automahc file backup and access
to other disk files during editmg.
String matchmg allows for locating and
modifying lines within a file.
PROM Monitor. The PROM Momtor
bootstrap loads for easy system entry,
supports a full machme-language
debug package, and includes low-level
device handlers for system console and
disk.
ZDOS II File Manager for Floppy
Disk Configurations. The ZDOS II File
Manager allocates all disk space automatically on an "as needed" baSIS and
supports sequential access to disk hies
or direct access to any speclhc disk
address. A directory provides an mdex
for data, accessed by calling a "hierarchical hnked list." Logical record
lengths range from 128 to 4096 bytes.
The Flle Manager also assigns attributes for protection and privacy.
DFS File Manager for Cartridge Disk
Configurations. The DFS File
Manager provides features similar to
the ZDOS II File Manager. It resides in
the Hard Disk Controller to save
memory working space for user software.
Utilities. In addition to the RIO
Operating System, the PDS 8000
System includes a utilities package that
contains programs such as peripheral
drivers, Z-PROG for programming
2708 and 2716 EPROM's for the Z80,
and a memory test routine. All these
programs are modular and relocatable.
Processor-Oriented Support. To
enhance the development capability of
the PDS 8000 Series of systems, Zllog
also provides speClfic software
packages and development tools to aid
the microprocessor system designer.
Z8000 Support. For Z8000-based
system designs, the Z8000 Software
Development Package (SDP) provides
the necessary tools to aid in software
development. Utilizing PLZ, Zilog's
high-level language, the Z8000 SDP
includes a Cross Assembler, Linker,
and PROM programming utility.
For a tried and tested environment to
run Z8000 code, the Z8000 Development Module is available. Providing
support for either the Z8001 or Z8002,
the Development Module is a singleboard computer With RAM, VO and
monitor/debug firmware. The Z8000
Development Module IS a convenient
tool to evaluate Z8000 CPU performance, as well as a first-level software
debug tool for use early in the design
process.
For real-hme emulation of either the
Z8001 or Z8002, the Z-SCAN 8000
Emulator is available. Operable. both
stand-alone and with a host system,
Z-SCAN 8000 makes possible software.
and hardware integration with realtime breakpoint, momtor/debug software, mappable memory, and an interactive user interface.
Z80 Support. The Z80 Software Development Package (SDP) affords the
designer a high-level PLZ Complier, a
Cross Assembler, Linker, and Code
Generator.
Z8 Support. The Z8 Software Development Package (SDP) includes a PLZ
Cross Assembler, Linker, and PROM
programming uhlity for Z8-based
designs. The Z8 Development Module
IS a Single-board computer that provides a ready environment to evaluate
and debug Z8 code. With 2K bytes of
stahc RAM, breakpomt, and PROMbased monitor, the Z8 Development
Module can operate stand-alone with a
CRT or with a host CPU.
SPECIFICATIONS
MICROCOMPUTER
Microprocessor
Z80 CPU
Interrupts
Three modes-maskable vectored,
maskable non-vectored and nonmaskable
Memory
60K bytes of dynamIC RAM
3K bytes of EPROM
Screen Size
12-inch dlagonai, non-glare screen
Maximum Capacity
600K bytes (dual drives)
Keyboard
Standard typewriter keyboard
15 numerlC keys
5 separate cursor control keys
Track-to-Track Seek Time
10 mllhseconds
CARTRIDGE DISK DRIVE
Character Set
128 ASCII code, 32 control codes
Capacity
10M bytes/drive (SM bytes formatted
storage, 5M bytes removable)
Option Card Slots Available
Floppy dIsk conhgurallon-7
Hard dIsk conhgurallon-9
Interface
Standard-RS-232C/CCITT. V24
Auxlhary-EIA RS-232C
Data Transfer Rate
2.5M bits/second
FLOPPY DISK DRIVE
Type
Top-loadmg cartridge
Word Size
8 b,ts (I byte)
Capacity
300K bytes/drive
I/O Channels
One serial 110 port WIth EIA RS-232C
Data Transfer Rate
250K bits/second
interface
Two parallel I/O ports for prmter mterface
CRT CONSOLE
Physical Sectors
32 sectors/track, 77 tracks
Screen Format
24 lines by 80 characters
Type
Smgle-sided, single denSIty,
hard sectored
Attributes
Reversed, blmkmg and blanked helds
Average Latency
83 mllhseconds
Average Latency
12.5 mllhseconds
Access Time
60 milliseconds (maxImum)
Maximum Capacity
40M bytes (four drives)
Track-to-Track Access Time
7.S mllhseconds
Physical Sectors
12 sectors/track, 402 tracks
483
SPECIFICATIONS (Continued)
Physical (Contmued)
Power
AC
Single-Phase
Height
Width
Depth
Microcomputer
110,220VAC
(SO Hz)
SSOVA
(60 Hz)
Floppy DIsk
Dnve
9.S0"
24.lcm
4.60"
11.8cm
14.2S"
36.2cm
Floppy DIsk
Dnve
IS,230VAC
(SO Hz)
S2VA
(60 Hz)
Cartridge
Disk Dnve
8.7S"
22.2cm
19"
48.3cm
29.2S"
74.3cm
Cartridge
Disk Drive
llO,230VAC
(SO Hz)
1l0VA
(60 Hz)
start/stop,
400VA typical
Operating
Temperature
Storage
Temperature
Relative
Humidity
OO-40'C
OO-8SoC
20%-8S%
Drive
SO-SO°C
OO-8SoC
20%-80%
Cartridge
DIsk Drive
Iso-30'C
10 o_6S°C
S%-8S%
Environmental
Microcomputer
Physical
Microcomputer
Height
Width
Depth
30.00"
76.2cm
IS.60"
SS.9cm
20.20"
76.2cm
Floppy Disk
ORDERING INFORMATION
Floppy Disk-Based
Part No.
05-6102-01
06-6102-02
05-6102-04
Description
PDS 8000105 Development System (60 Hz). Includes 280 Microcomputer, 64K bytes
dynamic RAM, 3K
monitor, printer interface, editing-type video
terminal w/line-drawing
capability, dual floppy
dIsk and RIO Operating
System. (l15 VAC)
PDS 8000105 Development System (50 Hz).
Same as 05-6102-01 except 230 VAC.
PDS 8000105-1 Development System (60 Hz). Includes 280 Microcomputer, 64K bytes
dynamic RAM, 3K
monitor, printer mterface, serial interface,
dual floppy disk and
RIO Operating System.
(l15 VAC)
Floppy Disk-Based (Continued)
Part No.
Description
Cartridge Disk-Based
Part No.
Description
05-6102-03
05-6105-01
PDS 8000120 Development System. Includes
280 MICrocomputer, 64K
bytes dynamic RAM, 4K
monitor, printer interface, editing-type video
terminal w/lme drawmg
capability, 10M byte
disk subsystem, 30-inch
high enclosure, RIO
Operating System.
(l15 VAC)
PDS 8000/20 Development System. Same as
05-6105-0 I except 230
VAC.
PDS 8000/20-1 Development System (60 Hz). Includes 280 Microcomputer, 64K bytes
dynamic RAM, 4K
monitor, printer interface, 10M byte disk subsystem, 30-inch high
enclosure, RIO
Operating System. (l15
VAC)
PDS 8000120·1 Development System (50 Hz).
Same as 05-6105-04 except 230 VAC.
05-6104-01
05-6104-02
PDS 8000105-1 Development System (50 Hz).
Same as 05-6102-04 except 230 VAC.
PDS 8000/15 Development System (60 Hz). Includes 280 Microcomputer, 64K bytes
dynamic RAM, 3K
monitor, printer interface, edihng-type video
terninal w/line-drawing
capabihty, dual floppy
disk, 28000 Development
Module, 28000 SDP Software Development
Package, and RIO
Operating System.
(l15 VAC)
PDS 8000/15 Development System (50 Hz).
Same as 05-6104-01 except 230 VAC.
05-6105-02
05-6105-04
05-6105-03
484
OO·1020·A
Z8™ Development
Module
~
Zilog
Product
Description
March 1981
• Two Z8-02 Devices Offer Complete
Configuration Choice for Any
Application_
• 2048 Bytes Static RAM for Convenient Execution and Debug of
User Code_
• On-board 2716 Socket to Test User
Code in EPROM Without Additional Hardware.
• As Many as 2048 Hardware Breakpoints on Address Compare Cover
the Entire Internal ROM Space.
• Versatile Monitor Software for
Debugging, Register and Memory
Manipulation, and File Upload
and Download.
• 'Transparent' Operation Allows
Software Development Without
Disconnecting from CRT and Host.
Industry-Standard Interface Compatible with Most CRT Terminals
and Development Hosts.
• Wire-Wrap Area for Prototyping.
OVERVIEW
The 28 Development Module is a
single-board microcomputer system
specihcally designed to assIst in the
development and evaluation of hardware and software designs based on the
28 microcomputer. It allows system
prototyping in hardware with the 28-02
prototyping device, thereby developing
code that wIll eventually be mask programmed into the 28 on-chip ROM.
Two 28-02 devlCes on the Z8 Development Module prOVIde flexibility: one
serves as a controller whIle the other is
totally user-definable. All user ports on
the second Z8-02 are unconhgured and
avaIlable to suit any applicahon.
To simulate the final mask-programmed version on which user code
resides, 2048 bytes of high-speed stahc
RAM are avaIlable for executmg and
debuggmg code. An on-board EPROM
socket allows the user to subshtute
EPROM for stahc RAM. Th,s enables
the user to test PROM after software
development and debug WIthout bUllding special hardware.
The EPROM-resident monitor software offers debugging features,
regIster and memory mampulahon, as
well as a convenient means to upload
and download software between the
host and user RAM space.
The Development Module connects
to the CRT terminal and host system
vIa two on-board standard RS-232C
senal ports and IS physIcally located
between the CRT and host. A SImple
command makes the Development
Module transparent m the senal path to
allow software development WIthout
disconnecting from the CRT and host.
The Development Module can
operate stand-alone for SImple debuggmg operahons or It can mterface
dIrectly to a host development system
such as the 2110g 2DS-1 or PDS 8000™
Senes for software development and
file storage.
Twenty square inches of wIre-wrap
area with convemently located 5 V and
ground points are prOVIded near the
user 28-02 for prototypmg.
485
FUNCTIONAL DESCRIPTION
Hardware. Two Z8 mlCrocomputer
units designated the Monllor MCU and
User MCU are at the heart of the 28
Development Module. The Monitor
MCU controls operation of the User
MCU and the momtor/debug software.
The mom tor/debugger resldes m 4K
bytes of EPROM. Hardware breakpomt
logic provldes a maximum of 2048
breakpoints. Single stepping and software trace capabihties are also
avallable.
The User MCU is a 28-02 controlled
by the Monitor MCU Vla mternal
address/data and control lines brought
out to external pins. This effechvely
leaves all ports on the User MCU
unconfigured and avallable to the user.
The 2K bytes of static RAM on the
'mternal' bus are for user code that
may be executed by the User MCU.
Execuhon lS in real time at full processor speed. Both MCUs uhlize
7.4 MHz crystal oscillators, the outputs
of which are divided internally to provide 3.7 MHz clocks.
In addition to wire-wrap area, a
40-pin header (3M type 3495-1002) for
the User 28 can connect to a nbbon
cable with a 40-pm plug that may plug
into a target system. Bus dnver logic
may be added on the wire-wrap area
for basic emulation capability. Two
switches, 'Mode' and 'Reset', provlde a
means to re-enter the Monitor and
remitiahze the system, respectively.
Baud rate from 1l0·to 19200 may be
selected wlth an on-board 4-element
DIP switch.
Software. The monitor/debug program, residing in 4096 bytes of
EPROM, includes debug, input/output,
control and host interface commands.
The commands are grouped into four
major functional blocks: monitor,
debug, manipulation and file
commands.
Z8 Development Module conveniently connects to both the CRT and PDS 8000 Development System.
Monitor Commands. This group of commands controls
execution of the User MCU, monitors user interrupts and
transfers controls from the mom tor to the host system.
GO
HALT
QUIT
Causes User MCU to execute program disallowmg further debug
unhl a BREAK or HALT command
lS encountered.
Halts program execution of the
User MCU.
Debug Commands. This group of commands allows the user
to debug code by tracmg through code and setting breakpoints and Jumps to specified locations within the 'internal'
ROM space.
BREAK < ADDRESS>
Sets a breakpoint at the specihed
address.
KILL [
Allows the User MCU to jump to a
specified address anywhere withm
the internal ROM space, by changing the value of the program
counter.
NEXT [-
PROGRAM
COUNTER
RAM
ir
ir
USER
to.
y
~
-;:j
BUS
PORT
USER
MCU
nl
A
MONITOR ADDR BUS
DATA
MUX
y
AD DR
MUX
¢=>
BUS
J:1::BUS
<
>
RS232C
PORTS
QQ
TO CRT
TO HOST
Z8 Development Module Block Diagram
Manipulation Commands. The mampulahon commands
display and alter regIsters and memory. Th,s group may be
subdIvIded mto two categones: regIster manipulahon and
memory mampulahon.
MOVE < SOURCE
ADDRESS>
< DESTINATION
ADDRESS> [< n>]
Moves contents of a user memory
block from a source address to a
deshnahon address for a length
of n bytes.
Register Manipulation
COMPARE
< ADDRESS 2> [< n> ]
Compares two blocks of user
memory data, one begmning at
ADDRESS 1 and the other at
ADDRESS 2 for n bytes.
REGISTER [< REG
NUMBER>] [< NEW
REG VALUE> lJ
Allows exammahon and modlfication of the User MCU regIsters.
WORKING REGISTERS
DIsplays contents of the 16 working
regIsters of the User MCU.
PHILL < STARTING
REGISTER>
[]
Stores the sequence of DATA
BYTES mto User MCU reglSters
begmning at the STARTING
REGISTER and IS copIed as many
hmes as necessary for the
NUMBER OF REGISTERS
speclhed.
Memory Manipulation
File Commands. The FIle group enables the user to upload
and download programs to and from the host system.
LOAD
Downloads a hie to user memory
starting at the low address of the
hIe and conhnumg unhl the entire
hIe is transferred.
UPLOAD
Creates a RIO hie Image of user
memory, begmnmg at ADDRESS
1, creatmg default length records,
and imagmg memory for the
[< ENTRY ADDRESS>] speclhed number of bytes.
DISPLAY [ [< n> lJ
Allows d,splay and modlflCahon of
user memory contents for n
number of bytes.
SET < ADDRESS>
[< DATA BYTES>]
Allows a sequence of data bytes
beginmng at the ADDRESS specihed to be wntten mto user
Note: The followmg notahon IS used m the command descflphon.
memory.
< >
Enclose descnphve names for the
quanhhes to be entered, and are not
actually entered as part of the
command.
[]
Denote optional entries m the command syntax.
FILL < STARTING
ADDRESS>
[< DATA BYTES>]
1007·001
Stores the sequence of DATA
BYTES mta user memory begmnmg at the starhng ADDRESS and
is copIed as many hmes as
necessary for the LENGTH
speclhed.
Denotes liar."
487
SPECIFICATIONS
Central Processor
Momtor MCU: 28-02 (54-pm package)
User MCU: 28-02 (54-pm package)
Clock Rate: 3.7 MHz
Memory
Momtor: 4K bytes of EPROM
User: 2K bytes of statIc RAM
User: WIred socket for EPROM to
substItute for statIc RAM
Input/Output
Two RS-232C ports to CRT termmal and
host system
Baud Rate
SWitch selectable from 110 to 19200 baud
Breakpoint
2048 max., vahd for Address Compare,
apphcable to user 'mternal' memory only
Control
Mode and Reset sWltches
Power
+5V,IAA
Physical
Wire Wrap
Area
Height
Width
Depth
20 sq. in. 0.035" dia.
plated-through holes
on 3132 m. centers
1.75 m. (4.75 cm).
mcludmg standoffs
14.5 in. (35.5 cm)
1LO m. (29.9 cm)
ORDERING INFORMATION
Part No.
05-6158-01
Description
28 Development Module.
Includes one senal mterface ribbon cable and
reference manual.
Systems recommended for use with above:
Description
Prerequisites
2DS-1 Series Development Systems
Z8 Software Development Package
PDS-8000 Series Development
Systems
28 Software Development Package
488
OO-lO07-A
Z8000™
Development Module
~
Zilog
Product
Description
March 1981
• Z800l/Z8002 CPU Evaluation and
Debug Support
• 16K Words Dynamic RAM
(Expandable to 32K for User Code
Execution and Debug
• 32 Programmable I/O Lines
• EPROM Monitor and Debugger
• Transparent Operation Allows
Soltware Development without
Disconnection Irom CRT and Host
System
• RS-232C Standard Serial Interlaces
Compatible with Most CRT Terminals and Development Hosts
• Wire-wrap Area lor Prototyping
OVERVIEW
The Z8000 Development Module IS a
complete, single-board mIcrocomputer
that IS used as a tool for the evaluatIon
and debug of Z8000-based mIcroprocessor systems. The Development
Module IS used m the hrst stages of the
desIgn and development process, not
only as a tool for evaluatmg Z8000
mICroprocessor capabIlitIes, but also as
an envIronment m whIch code can be
executed and debugged.
Evaluation. The Development Module
provIdes a ready-made enVIronment m
whICh the user can execute software
umque to hIs Z8000-based applIcation,
evaluate the CPU's performance, and
then reach a realIstIc decIsIon about ItS
sUItabIlIty for a speclhc applIcatIon.
Soltware Debug. In addItIon to use as
an evaluatIon tool, the Z8000 Development Module can be used to debug
and modIfy user code. For the software
desIgner, the Development Module IS a
real Z8000 envIronment m whICh he
can execute code and carry out fairly
extensive debuggmg. For the hardware
desIgner, the Development Module IS
an example of Z8000 hardware desIgn
which provIdes specIal hooks and wlrewrap faCIlItIes to strap on addItIonal
logIc.
489
FUNCTIONAL DESCRIPTION
zaooo code developed on a software
host may be downloaded serially to the
Development Module RAM area vIa a
serial port, and executed and debugged under EPROM mom tor control.
Once the system IS connected, no further disconnechon is necessary as the
module has two serial ports (one connected to a host and the other connected to a CRT terminal). A simple
software command makes the development process transparent m the serIal
path, thereby allowing direct commUnIcahon between the host and terminal.
The serIal RS-232C mterfaces allow VIrtually any software development host
and CRT terminal to be used. For
PROM-based code testmg, the development module IS self-contamed and
can operate stand-alone with a CRT
terminal, since the host IS only
required for storage of user code
on dIsk.
A vanety of Jumper areas and
switches permit the selechon of clock
rates ranging from 2.5 to 3.9 MHz; the
use of 2708,2716, or 2732 EPROMs;
the use of 4K or 16K RAMS; serIal
interface to modem, terminal, or teletype; I/O port addressmg; and baudrate selectIon from lID to 19200 baud.
Hardware. The 28000 Development
Module is avaIlable in two verSIOns:
one supports the segmented 28001
mICroprocessor; the other supports the
non-segmented 28002 microprocessor.
Z8001 Development Module. The
28001 Development Module consIsts of
a 28001 CPU, 16K words of dynamIc
RAM (expandable to 32K words), 4K
words of EPROM mOnItor (userexpandable to 8K words), a 280A SIO
providing dual serial ports, a 280A
CTC perIpheral chIp provldmg four
counter/hmer channels, two 280A PIO
devices providing 32 programmable
I/O lines, and wIre-wrap area for prototyping hardware.
Z8002 Development Module. The
28002 Development Module consIsts of
a 28002 CPU, 16K words of dynamic
RAM (expandable to 24K words), 2K
words of EPROM monitor (userexpandable to 8K words), a 280A SIO
device providing dual serIal ports, a
280A CTC perIpheral deVIce provldmg
four counter/hmer channels, two zaOA
PIO devices providing 32 programmable I/O Imes, and wIre-wrap area
for prototyping.
490
COMMAND
INTERPRETER
DEBUGGER
Figure I. Monitor Block Diagram
Software. The monitor software
(Figure 1) contained m EPROM (4K
words for the 2800 I and 2K words for
the 28002) prOVIdes debuggmg commands, I/O control and host mterface.
It consIsts of a terminal handler, command mterpreter, debugger and
upload/download handler.
ensures command validity and passes
to other software modules in the
monitor.
Terminal Handler_ A Terminal Handler
prOVIdes interface to the console
deVIce to facilItate output to a dIsplay
or prmtIng mechanIsm and input from
a standard ASCII keyboard.
Upload/Download Handler. The
UploacJ/Download Handler provides an
Interface between the serial connection
and the host computer, the command
Interpreter and the memory resources
of the 28002 Development Module. It
formats and interprets asynchronous
data streams to and from the host and
prOVIdes error checking and recovery
for the serial Interface (see Figure 2).
Debugger. The Debugger provides a
baSIC set of debug commands to allow
the user to start and stop program execuhon, display and alter CPU
regIsters, flags or memory, and trap
instruchon sequences.
Memory Organization. Tables 1 and 2
show the memory maps for the two versions of the Development Module. The
organIzation of ROM and RAM In both
the segmented and nonsegmented
modes IS IndICated.
Command Interpreter. The Command
Interpreter scans console Inputs,
/
ADDRESS
I I I
BYTE CHECK
COUNT SUM
I
I
CHECK C
SUM
R
DATA
I I I I
I I I I
I
Figure 2. Serial Dala Formal
I047~OOI,
002
Segment 0
Segment I
Address (Hex)
Memory
Address (Hex)
Memory
Address (Hex)
Memory
0000
MOnItor
EPROM
0000
Momtor
0000
IFFF
EPROM
3FFF
ExpanslOn RAM
(User Installed)
User EPROM
(User Installed)
2000
User EPROM
(User Installed)
4000
Unused
OFFF
1000
3FFF
4000
BFFF
COOO
FFFF
Standard
RAM
Expansion RAM
(U ser Installed)
3FFFF
4000
Momtor RAM
(Scratchpad Area)
49FF
4AOO
BFFF
COOO
FFFF
Table I. Z8002 Development Module Memory Map
FFFF
Standard RAM
Expansion RAM
(User Installed)
Table 2. Z8001 Development Module Memory Map
MONITOR COMMAND SUMMARY
The followmg notation is used m the
command description:
< > Enclose descriptive names for the
quantities to be entered, and are
not actually entered as part of the
command.
[]
Denote optional entries in the command syntax.
Denotes "OR", ego WIB denotes that
either W or B may be used but not
simultaneously.
<
Prompt sign for the nonsegmented
Z8002 monitor.
Prompt sign for the segmented
Z8001 monitor.
The followmg commands apply when
the Z8001 momtor IS used. All commands hsted remam the same except
those that permIt reference to segmented addresses as follows:
=
[ < segment number>] < offset
address>
< segment number> =
"<"">"
BREAK < address>
[]
Sets and clears a breakpoint at a
gIven memory address. The option
< n> allows speclfication of the
number of occurrences, where n IS
from I to 128. The default is one.
COMPARE
Compares two blocks of memory
data beginning WIth the addresses
specihed for bytes, where n
is from I to 128. Errors are
reported on the console device.
DISPLAY < address>
[LIWIB]
Displays and modihes memory for
number of words or bytes.
The ophonal entry allows data to
be handled as bytes, words, or
long words. The default IS words.
FILL < address I >
Stores the < word> from memory
address I to and mcluding
address 2.
GO
10PORT
[WIB]
JUMP < address>
Begins program execution at the
address contained in the current
PC; execution is resumed where it
was last mterrupted. All registers
are restored prlOr to execuhon.
Allows direct communications from
the console to a selected 1/0 port.
A word (Wl or a byte (Bl may,be
read from the selected port and a
word or byte may be sent to the
selected port; default is byte.
Unconditional branch to the specified address. All registers are
restored pnor to execution.
MOVE < address I >
Moves contents of a memory block
from source address < address 1 >
to destination address
for bytes.
NEXT[ ]
Executes the next < n > machine
mstruchons. may be from
I to 128. If n is omitted, I is
assumed.
PUNCH < address I >
Punches a copy of memory from
address I to address 2 on paper
tape on the console device. Automatically turns on punch and a
null leader is created.
Upload/Download section
deSCribes the tape format used.
QUIT
Places senal channels mto transparent mode. The Z8000 Development Module must be connected to
both the Zilog host and the console
device, and the Development
Module acts as a message
switcher.
REGISTER
[ < register name> ]
Allows examinahon and modihcahon of Z8000 registers. 8-bit, 16-bit
or 32-bJt quantities may be
selected by the appropriate
register-naming conventions.
TAPE
Loads memory from paper tape vIa
the console device. The
Upload/Download sechon
describes the tape format used.
491
N
e00
e
e
1:11
l"J
~
::ce
'='
e::
PI
l"J
SPECIFICATIONS
Microprocessor
Z800 I or Z8oo2 CPU
Clock Rate: 2.5 MHZ or 3.9 MHz
Memory
ROM: 2K or 4K Words (Expandable
to 8K Words)
RAM: 16K Words (Expandable"
to 32K Words)
Input/Output
Parallel: 32 Lmes (Two Z80A·PIOs)
Serial: Dual RS·232C or RS·232C and
Current Loop (Z80A·SIO)
Power
Note
Physical
Height
The user has access to all bus signals to allow
+5 V, 3 A
+12 V, 1 A
-12 V, 0.2 A
custom system expansIOn mto the wire-wrap area
off-board.
Interrupts
Maskable Vectored (256), Maskable
Non·vectored, Non·maskable,
SegmentatIon Trap
Width
Depth
Weight
1.75 m. (4.5 em) InclUSive of
Standoffs
14.0 m. (35.6 em)
11.0 m. (27.9 em)
Approx. 30 oz. (850 gm)
ORDERING INFORMATION
Part No.
Description
05-6168-01
05-6101-01
05-6171-01
28001 Development Module
28002 Development Module
28001 Conversion KIt (converts 28002 Development Module into
28001 Development Module)
Systems recommended for use with the above:
Description
Prerequisite
2DS-l Senes Development Systems
28000 Software Development Package
PDS 8000 Senes Development
Systems
28000 Software Development Package
492
OD·1047-A
Z8000™ Emulator
Z-SCAN 8000
~
Zilog
Product
Description
March 1981
.. Provides Real Time Emulation up
to" MHz of the Z800l and Z8002
CPUs.
II Two RS-232C Serial Ports Make It
a Peripheral Usable with Most
Standard CRTs and Software
Hosts.
• Transparent Operation Permits
Direct Communication Between
CRT and Host without Physical
Disconnect.
• Shadow Monitor Removes All
Restrictions on Target System
Memory Space. Making It Fully
Available To the User.
• Highly Interactive. ScreenOriented User Interface Makes
Z-SCAN Easy To Use.
• High-Speed Mappable Memory
(no wait states) Is Available to
Simulate Target System
RAM/ROM.
OVERVIEW
The Z-SCAN 8000 Emulator 1S an inC1rcUlt emulator that has been designed
as a penpheral umt for Zllog's Z8001
and Z8002 16-b1t mlCroprocessors.
Interfacmg V1a two RS-232C Senal
ports to host and CRT termmal,
Z-SCAN 8000 can work with Zllog's
family of development hosts.
Because 1t employs a standard senal
mterface, Z-SCAN 8000 can also be
used w1th v1rtually any software host
system that runs a cross assembler or
cross complIer capable of generating
Z8000 code. Commumcahon between
the host system and Z-SCAN 8000 1S
w1th a standard senal format reqUlring
only a slmple upload and download
uhhty to operate. For PROM-based
target systems, Z-SCAN can operate
stand-alone with a CRT termmal
because the mom tor and debug software 1S EPROM-res1dent.
In keepmg w1th Zllog's des1gn
phllosophy of separahng a development system mto two 1denhhable umts
(the software host and an emulahon
penpheralL Z-SCAN 8000 hts mto
three scenanos, making 11 a h1ghly versahle umt:
II As a penpheral to Zllog's PDS 8000
and ZDS-l Senes of development
systems, Z-SCAN 8000 completes
the development support package
for the Z8001 and Z8002 microprocessors avallable from Zllog.
• As a penpheral to any development
host w1th the capabll1ty of complling
or assembling Z8000 code, Z-SCAN
8000 allows a low-cost emulahon
capab1hty wh1ch precludes substanhal remvestment m a software host
system.
• As a stand-alone m-C1rcUlt emulator
that can operate with most CRT
terminals, Z-SCAN 8000 prov1des
slmple testmg and debugging
capab1lity for PROM-based target
systems.
493
SYSTEM FEATURES
User Interface. Z-SCAN 8000 mcorporates the use of a two-dimenslOnal
screen-oriented user interface whlch
makes It easy to use. Because it is
general-purpose in nature, the user
interface does not requIre a customized
CRT terminal to operate. The only
requirements are that the CRT terminal
have screen erase, line erase, and cursor addressmg capability.
The objective of the user Interface IS
to provide a screen format with a
menu-like approach, which directs the
user through the operation of the emulator. The user IS aware at all times of
where he/she is in the debug process
because Z-SCAN 8000 provides the
CRT information about system para-
ADDRESSJDATA
BUS
COMPARE
VALUE
SEGMENT
BUS
ADDRESS/DATA
COMPARATORS
DON'T
CARE
COMPARE
VALUE
SEGMENT
COMPARATORS
STATUS
BUS
VALUE
STATUS
COMPARATORS
DON'T
DON'T
CARE
CARE
INSTRUCTION
FETCH
DETECT
COMPARE
MATCH
meters, system resources, current
execution, and error messages. When
the system is turned on, a bootstrap
routine produces a display informing
the user of the unit's configuratlOn and
requesting the user to define set-up
parameters. A menu of dISplay chOICes
shows the user the different capabIlIties
of the system:
• The Memory/I/O command display
shows the various memory and I/O
manipuiallon commands whIch
access the target system.
• The Resources display presents the
user WIth the full complement of
arguments applicable to emulation
of the target system.
• The Execution display shows all the
commands and parameters necessary to cause emulation to take
place.
At all times, executlOn of speCIfIc
Monitor commands is possible, and
information on other relevant system
parameters and resources is always displayed. ThIS highly interactive user
Interface makes it possible to use
Z-SCAN 8000 Without frequent
reference to the operating manual.
Shadow Memory. Z-SCAN 8000 IS a
smgle, CPU-based system that can be
confIgured to emulate eIther the Z8001
or Z8002 by SImply exchanging the
CPU, monitor EPROM, and the
emulator cable.
Although the system uses a Single
CPU for both mom tor and emuiallon
functions, no restrictions are placed on
the target system memory sIze. ThIS is
because the enlIre mom tor resides In
shadow memory and, therefore, does
not appear In the target system memory
space. ThIS feature also prOVIdes the
beneht of makmg future system expansIOn pOSSIble WIthout any hardware
redeSIgn.
494
COUNTER
COUNTER
BREAKPOINT
' -_ _ _ _ _ _.......... LOGIC
Figure I. Hardware Trigger Implementation
Hardware Trigger. Z-SCAN 8000
offers the capabIlIty of sethng breakpoints In three dIfferent he Ids or In a
comblnahon of these fields. These are
the Address/Data Field, the Segment
Field, and the Control/Status FIeld. A
Pass Counter can be set up to a maximum of 255 counts to allow multiple
pass triggermg. In addItion, Z-SCAN
8000 may also be set to break on
Instruchon fetches only (Single-step
execuhon), or, by uSing a Pass
Counter, may be set up to a maxImum
of 247 counts to allow triggermg on
mulhple instructlOn fetches (multi-step
executIon).
WIth these two capabIlIlles, a breakpOint argument can be set up whIch is
on ORed con dIllOn allowing for eIther
a break-on-held (or comblnahon of
fields) argument or for "n" instruction
fetches, whichever occurs hrst. ThIS
ORed sItuation IS convement when
tracing through a program In search of
a speCIfic occurrence. A pulse output,
prOVIding a trIgger pulse on breakpoint match condition IS avaIlable on
the rear panel to trigger aUXIlIary test
Instrumentation.
Mappable Memory. Z-SCAN 8000
offers a 4K work block of high-speed
static RAM. This block is available to
the user to simulate a target system
memory block which would tYPICally
be ROM. No Wait states are required
at 4 MHz. ThIS block is mappable
anywhere in the Z8001 and Z8002
address space and can be speCified to
be Normal Code, Normal Data, Normal
Stack, System Code, System Data,
System Stack, or Space Independent.
Mapping must be done on 4K word
boundaries only, and the entire block
can be write protected agamst Illegal
writes to cause system emulahon either
to break on such occurrences or continue emulation. An error message
appears on the CRT display informing
the user of an illegal write.
Software Trace. Z-SCAN 8000 offers a
software trace feature which provides
insight into target system activity and
CPU resources. In the Trace Mode, the
system displays the address of the
Instruction being executed and the
contents of the CPU regIsters (both
general-purpose and control) consecutively, covering one full screen
format.
For example, displaying the CPU
regIsters assocIated with every instruction executed Just prior to execuhng a
Break is tremendously useful to the
user during debug of target system
activity.
1041-001
SPECIFICATIONS
CPU
28001 or 28002 per conhgurahon
Clock Rate
500 kHz-4.0 MHz (external)
I/O
Two RS-232C Serlal Ports for CRT and
host
Baud Rate
Automancally selected from 50 to 19.2K
Breakpoint
Address, Data, Segment and Address,
Control, Address and Control, Data and
Control, Segment and Address and
Control, Instruction Fetch, OR combmalion of Instrucbon Fetch and any Field
Mappable Memory
4096 x 16 Stallc RAM (no Walt states at
4 MHz while operatmg off User clock)
Front Panel
Target/Momtor, Reset, and NMI toggle
sWItches
Inputs
One standard LS-TTL load plus 30 pF
Power
maXImum
110/220 Vac, 50/60 Hz sWitch selectable,
60 VA maximum
Outputs
Capable of drlvmg one standard LS-TTL
load plus 30 pF preload
Dimensions
Rear Panel Output
BNC connector for pulse output, standard
LS-TTL
Emulator Cable
12 mches
4 m. (10.2 cm) (H) x 14\!, m. (36.8 cm)
(W) x 18 m. (45.7 cm) (D)
argument
AC CHARACTERISTICS
Number
Symbol
Parameter
ZBOOI/2
Min (ns)
Max (ns)
Z-SCAN
Min (ns)
Max (ns)
1 TcC
Clock Cycle Time
250
2000
250
2000
2 TwCh
Clock Width (High)
105
2000
105
2000
3 TwCI
Clock Width (Low)
105
2000
105
2000
4 TIC
Clock Fall Time
20
20
5- TrC
Clock Rise T l m e - - - - - - - - - - - - - - - - - - - 2 0 - - - - - - - - - 2 0 - 6 TdC(SNv)
Clock 1 to Segment Number Vahd (50 pF load)
130
175
7 TdC(SNn)
Clock 1 to Segment Number Not Vahd
20
35
Clock 1 to Bus Float
65
165
8 TdC(Bz)
9 TdC(A)
Clock 1 to Address Valid
100
163
10- TdC(Az)---Clock 1 to Address Float - - - - - - - - - - - - - - - 6 5 - - - - - - - - 1 5 4 - 11
TdA(DI)
Address Valid to Data In Requued Valid
455
383
12 TsDI(C)
Data In to Clock I Setup Time
50
76
13 TdDS(A)
DS 1 to Address Achve
80
-4
14 TdC(DO)
Clock 1 to Data Out Vahd
163
100
15-ThDI(DS)---Data In to DS I Hold T l m e - - - - - - - - - - 0 - - - - - - - - 2 0 - - - - - 16 TdDO(DS)
Data Out Valid to DS 1 Delay
295
269
17 TdA(MR)
Address Valid to MREQ I Delay
55
29
18 TdC(MR)
Clock I to MREQ I Delay
80
143
MREQ Width (High)
210
193
19a TwMRh
19b-TwMRh
MREQ Width (High) Durmg Momtor O p e r a h o n - - - - - - - - - - - - 1 8 4 - - - - - 20 TdMR(A)
MREQ I to Address Not Achve
70
53
21
TdDO(DSW)
Data Out Vahd to DS I (Wnte) Delay
55
59
22 TdMR(DI)
MREQ I to Data In Required Vahd
350
287
23 TdC(MR)
Clock I MREQ 1 Delay
80
134
24-TdC(ASf)--Clock 1 to AS I D e l a y - - - - - - - - - - - - - - - - 8 0 - - - - - - - 1 3 4 25 TdA(AS)
Address Vahd to AS 1 Delay
55
29
26 TdC(ASr)
Clock I to AS 1 Delay
144
90
27 TdAS(DI)
AS I to Data In ReqUired Valid
340
277
28 TdDS(AS)
DS I to AS I Delay
70
53
29-TwAS
AS Width ( L o w ) - - - - - - - - - - - - - 7 0 - - - - - - - - 5 3 - - - - - 30 TdAS(A)
AS 1 to Address Not Achve Delay
60
43
31
TdAz(DSR)
Address Float to DS (Read) I Delay
0
-41
4
--------------------CONTINUEDONNEXTPAGE--------------------
495
AC CHARACTERISTICS
Number
Symbol
Z8001l2
Min (ns)
Max (ns)
Parameter
Z-SCAN
Min (ns)
Max (ns)
32 TdAS(DSR)
AS t to DS (Read) I Delay
70
53
DS (Read) I to Data In Required Valid
33 TdDSR(DI)
185
122
34 TdC(DSr)
Clock I to DS t Delay
65
70
35 TdDS(DO)
DS t to Data Out and STATUS Not Vahd
75
58
36-TdA(DSR)-- Address Vahd to DS (Read) I Delay - - - - - - - 1 8 0 - - - - - - - - 1 5 4 - - - - - 37 TdC(DSR)
Clock t to DS (Read) I Delay
174
120
38 TwDSR
DS (Read) Width (Low)
275
258
149
39 TdC(DSW)
Clock I to DS (Write) I Delay
95
40 TwDSW
DS (Write) Width (Low)
185
168
41-TdDSI(DI)-- DS (Input) I to Data In Required Valid------320 - - - - - - - - 2 6 6 - - - - - 174
42 TdC(DSf)
Clock I to DS (1/0) I Delay
120
43
TwDS
DS (1/0) Width (Low)
393
410
44 TdAS(DSA)
AS t to DS (Acknowledge) I Delay
1065
1048
45 TdC(DSA)
Clock t to DS (Acknowledge) I Delay
174
120
46-TdDSA(DI)--DS (Acknowledge) I to Data In Required Delay---435 - - - - - - - - 3 8 1 - - - - - 162
47 TdC(S)
Clock t to Status Valid Delay
110
48 TdS(AS)
Status Vahd to AS t Delay
60
45
RESET to Clock t Setup TIme
180
208
49 TsR(C)
50
ThR(C)
RESET to Clock t Hold Time
0
15
51-TwNMI
NMI Width ( L o w ) - - - - - - - - - - - - - 1 0 0 - - - - - - - 1 1 6 - - - - - 52 TsNMI(C)
NMI to Clock t Setup Time
140
154
53
TsVl(C)
VI, NVI to Clock t Setup TIme
110
118
54 ThVI(C)
VI, NVI to Clock t Hold TIme
0
22
55 TsSGT(C)
SEGT to Clock t Setup TIme
70
78
56-ThSGT(C)-- SEGT to Clock t Hold Time
0
22 - - - - - 57
TsMI(C)
MI to Clock t Setup Time
180
188
58 ThMI(C)
MI to Clock t Hold Time
0
22
59 TdC(MO)
Clock t to MO Delay
165
120
60 TsSTP(C)
STOP to Clock I Setup Time
140
148
61-ThSTP(C)--STOP to Clock I Hold T l m e - - - - - - - - - - O - - - - - - - - 2 2 - - - - - 62 TsWT(C)
WAlT to Clock I Setup TIme
50
78
63
ThWT(C)
WAIT to Clock I Hold TIme
10
25
64 TsBRQ(C)
BUSREQ to Clock t Setup Time
90
98
BUSREQ to Clock t Hold TIme
10
32
65 ThBRQ(C)
66-TdC(BAKr)--Clock t to BUSACK t D e l a y - - - - - - - - - - - - - 1 0 0 - - - - - - - 1 4 5 - 67 TdC(BAKf)
Clock t to BUSACK I Delay
100
145
ORDERING INFORMATION
Part No.
Description
05-0100-00
Z-SCAN 800011 Emulator
(Supports Z8001 Emulation and Control)
05-0100-01
Z-SCAN 8000/2 Emulator
(Supports Z8002 Emulation and Control)
05-0101-00
Z8001 FIeld Support KIt
(Converts Z-SCAN
8000/2 into Z-SCAN
8000/1)
05-0102-00
Z8002 FIeld Support KIt
(Converts Z-SCAN
800011 into Z-SCAN
8000/2)
Systems recommended for use with above:
Description
ZDS-I
Sene~
Prerequisites
Development Systems
PDS 8000 Series Development
Systems
496
Z8000 SDP
Z8000 SDP
OO-1041-A
Z80 PLZTM
~
Product
Description
Zilog
March 1981
• High-Level Procedure-Oriented
Language Permits Efficient
Writing of Machine-Independent
Modules and Programs.
• Structured Format for Fast and
Easy-to-Compile Programs.
• Produces Efficient Code for
Economical Memory Usage and
Processing Time.
• Simplifies Software Production
and Maintenance.
• Allows Direct or Interpretive
Execution of Program Modules.
FEATURES
Compiler. The Z80 PLZlSYS Compiler
translates source code modules mto an
intermediate stage called Z-code. The
Z-code modules may then be executed
interpretively or processed by the code
generator to produce a machme-code
object module.
Code Generator. The 280 PLZCG
Code Generator accepts a file of mtermediate Z-code generated by PLZlSYS
and produces the corresponding Z80
machine code as a relocatable object
module. This file may be lmked with
other modules to form the complete executable load module.
Interpreter. The intermediate Z-code
modules produced by the Z80 PLZlSYS
OVERVIEW
Z80 PLZ 18 a family of different programmmg languages designed to
satisfy a WIde range of microcomputer
software development requirements.
The two members of the PLZ famIly,
PLZlSYS and PLZIASM, produce object
code-compatible modules and share
common control structures and data
defimtion faCllihes. Thus, selective portions of programs may be written in the
most appropriate language for the
specific application and still maintam a
consIstent structure between modules.
PLZlSYS is a hIgh-level, procedureoriented language that is syntactically
similar to PASCAL. It provides a
medium for wnhng structured,
machine-independent programs with a
mmimum of programming effort.
PLZIASM, on the other hand, is a
structured assembly language that permils access to the low-level capabllihes
of the processor by mixing assembly
language and high-level control
structures.
Compiler can be executed mterprehvely by ZINTERP. Linking ZINTERP
with the other modules generated by
the compiler produces an executable
load module.
Although interprehve Z-code runs
more slowly than machine code, the
space savings over machme code is
usually substanhal for larger programs
where the 3K bytes of ZINTERP is a
small percentage of the entire program. By balanCing the number of
Z-code and machme code modules, the
user can maximIze the effiCIency of a
parhcular program.
PLINK resolves any external references between separately assembled
modules, so that the load module produced is relocatable. It also allows the
reordering and combining of named
sections between modules and supports
mcremental linking.
PLZ/ASM Translator. The PLZ FILTER
translates a PLZIASM source module
mto a file of the corresponding Z80
Assembler source. ThIS gIves the
Assembler the benefit of logICal data
structure, program flow control, and
modular program deSign, m addition to
ItS eXIsting features.
PLZ Linker. The PLZ Linker, PLINK,
lmks Z-code, ZINTERP and/or machme
code modules into a single relocatable
load module, allowmg the user to control the overall size and speed of the
program.
ORDERING INFORMATION
Part No.
Description
07-3301-01
280 PLZ
Object Diskette for use
with PDS 8000/05 and
PDS 8000115
07-3303-01
Z80 PLZ
Object Cartridge Disk
for use with PDS 8000120
and PDS 8000/30
07-3302-01
280 PLZ
Object DIskette for use
WIth ZDS-I Series
07-3303-02
280 PLZ
Object DIskette for Hard
DIsk Systems with
Ophonal Floppy Drives
07-3303-04
Z80 PLZ
Object Cartridge DIsk
for use with
PDS 8000120A
497
PLZ/SYS
FILTER
PLZCQ
ASM
PLINK
Figure 1.
498
zao PLZ Language Modules.
OO-1043-A
Z8 Software
Development Package
~
Product
Description
Zilog
March 1981
• Structured Assembly Language
with High-Level Constructs.
• Relocatable and Absolute Object
Code Format.
• Free Format Statements Allow
Indentation and Spacing for
Readability.
• External Symbol References.
• Global Symbol Definitions.
OVERVIEW
The Z8 Software Development
Package consists of five utility programs which aId and simplify software
development for Z8-based systems. Z8
PLZlASM, part of Zilog's PLZ famIly,
brings all the advantages of modular
programming to Z8 software development. The programmmg task can be
broken into easily managed modules,
gIving more work assignment ophons to
the engineering manager and a clearcut structure to the indIvidual programmer. The Z8 linker completes the task
by combmmg the modules and resolving any external references.
FEATURES
Assembler. The Z8 PLZIASM
Assembler translates easy-to-read, freeformat PLZI ASM source programs to
object code. Because the user may
specdy that eIther absolute or
relocatable object code be produced,
he may choose a memory locahon for
the program or leave that responslbllity
to the Lmker. The Z8 PLZI ASM
Assembler produces a hstmg hie containing both the source and assembled
code.
Z8 PLZ/ ASM allows an efhcient mIx
of powerful assembly language
mnemonics WIth hIgh-level control
structures such as IF ... THEN ..
ELSE ... FI and DO ... OD loops.
The PLZIASM programmer may map
mstructions and mformahon into the
Z8's regIster, program and data
memory spaces, and orgamze the data
space WIth such data declarahons as
RECORDS and ARRAYS. The
PLZIASM Assembler supports external
symbol references and global symbol
dehnihons and IS fully supported by
the RIOTM operatmg system.
Z-LINK. Z-LINK Imks assembled
modules mto a smgle relocatable
module and resolves any external
references among separately assembled
modules. It can also reorder and combine named sechons found in the mput
assembly language modules. Z-LINK
accepts a symbohc specihcation of
the program entry pomt m the command line and, on request, produces a
detailed link map which gIves the locahons of global references and relocated
modules and sechons. Errors m the
linking process are reported m the
ophonal Imk map and at the system
console.
IMAGER. IMAGER accepts multiple
linked-object files from the lmker and
translates them into absolute code.
IMAGER can then eIther store the
absolute code in a dIsk hIe or leave it
in system memory. Named sections
·found in the input object modules may
be reordered and loaded anywhere in
system memory.
LOAD/SEND. LOAD/SEND downloads
an absolute program hIe into the Z8
Development Module for debugging,
then sends it back to the dIsk for backup and storage.
Z-PROG. Z-PROG stores the perfected
load module in PROM.
ORDERING INFORMATION
Part No.
Description
07-0086-01
Z8 Software Development Package
Object Cartridge Disk
for Use WIth PDS
8000120A
07-3361-01
Z8 Software Development Package
Object Diskette for Use
with PDS 8000/5 and
PDS 8000/15
OO·]042·A
Part No.
07-3362-01
Description
Z8 Software Development Package
Object Diskette for Use
with ZDS-I Series
07-3363-01
Z8 Software Development Package
Object Cartridge DIsk
for Use with PDS
8000/20 and PDS
8000/30
Part No.
07-3363-02
Description
Z8 Software Development Package
Object DIskette for
Hardware Disk Systems
WIth Optional Floppy
Drives
499
N
00
!
Z8000™ Software
Development Package
~
Zilog
Product
Description
March 1981
• Structured assembly language
with high-level constructs.
• Relocatable and absolute object
code format.
• Free format statements allow
indentation and spacing lor
readability.
• External symbol references.
• Global symbol definitions.
OVERVIEW
The Z8000 Software Development
Package consists of six uhhty programs
which aid and slmphfy the development of Z8000 programs on the Z8000
Development Module. Z8000 PLZlSYS
and PLZlASM from Zllog's PLZ family
bring all the advantages of modular
programmmg to the Z8000 software
developer and ensure transportabihty
to future processors. The Z8000
LINKER, IMAGER, LOAD/SEND and
Z-PROG slmphfy the testmg and production stages of new software. Each
program faClhtates a single step
towards completmg a segmented or
nonsegmented program; together they
guarantee a smooth, 10glCal, and
manageable software development
process.
FEATURES
Assembler. The Z8000 PLZI ASM
Assembler assembles easy-to-read,
free-format PLZlASM source programs
directly to machme code. PLZlASM
allows an efhclent mix of powerful
assembly language mnemonics WIth
high-level control structures, such as
IF ... THEN ... ELSE ... FI and
DO ... OD loops. The PLZlASM programmer may map mstruchons and
mformahon mto the Z8000's program
and data memory space, and orgamze
the data space WIth such data declarahons as RECORDS and ARRAYS. The
PLZ/ ASM Assembler supports both
segmented and nonsegmented programs and IS fully supported by the
RIOTM operatmg system.
LINKER. Z-LINK Imks assembled
modules mto a smgle-load module.
Z-INTERP, Z-code, and machme code
modules may be combmed m a smgle
program to faclhtate execuhon speed
and memory conservahon, or the most
efhcient balance of the two. Z-LINK
resolves any external references
between separately assembled
modules, so that the load module produced is relocatable. It also allows the
reordermg and combmmg of named
sechons between modules. Z-LINK permits a symbohc speclhcahon of the
program entry point m the command
Ime and, on request, produces a
detalled Imk map for program
documentahon.
IMAGER. The PLZ IMAGER can
accept mulhple Imked obJect hIes from
Z-LINK and translate them mto absolutE
code. IMAGER can then either store
the absolute code m a disk hIe or leave
It m system memory. IMAGER may
load Z-INTERP and Z-code obJect hIes
and supports segmented code. Named
sechons found m the mput obJect
modules may be reordered and loaded
anywhere m system memory.
LOAD/SEND. LOAD/SEND downloads
an absolute program file into the Z8000
Development Module for debugging,
then sends it back to the disk for backup and storage.
Z-PROG. Z-PROG stores the perfected
load module in PROM.
ORDERING INFORMATION
Part No.
07-0085-01
07-3306-01
OO-I044-A
Description
Part No.
Description
Part No.
Description
Z8000 Software Development Package
Ob]8ct Cartridge Disk
for Use With PDS
8000/20A
07-3306-02
Z8000 Software Development Package
Ob]8ct DIskette for Hard
Disk Systems With
Ophonal Floppy Drives
07-3310-01
Z8000 Software Development System
ObJect Diskette for Use
With ZDS-! Senes
Z8000 Software Development Package
ObJect Cartndge Disk
for Use With PDS
8000/20
07-3309-01
Z8000 Software Development System
ObJect Diskette for Use
WIth PDS 8000/5
501
N
00
C
C
C
Ul
t::I
."
Z8000™
Cross-Software
Package
~
Zilog
Product
Description
March 1981
• Runs on the UNIX· Operating
System.
This enables multi-user access for
more effiCient software development
and provIdes tools to aid documentation production.
N
§
n
;
iii High-Level. Machine-Independent.
Systems Implementation
Language. C. Generates Efficient
ZBOOO Code.
C improves programmer productivIty. shortens product time-to-market.
and protects software investment.
PROGRAMS
AND DATA
ZBOOO
CROSS SOFTWARE
PACKAGE
II Includes C Run-Time Support
Environment for the ZBOOO
Development Module.
ThIs keeps product development on
schedule by reducing dependency
on prototype hardware.
UNIX
OPERATING SYSTEM
• C Compiler Produces ZBOOO CrossAssembler Source Code.
Assembly language listing of C programs simplifies debugging in any
target envIronment.
OVERVIEW
In today's complex mICroprocessorbased products. software development
costs typICally exceed those of hardware development. The 28000 CrossSoftware Package. running on the
UNIX operating system. reduces software development costs by imprOVing
programmer produchvity and enabling
software to be developed before prototype hardware is ready. ThIS allows
hme for thorough product testing whIle
shll meehng development schedules.
The result IS a higher quality product
dehvered on schedule.
The 28000 Cross-Software Package
(CSP) IS a complete set of software
tools for developing 28000 programs.
The package works on DIgItal Equipment Corporahon's PDP-l 1144, 11145,
and 11170 systems WIth the Seventh
Edihon of the UNIX operating system.
Programmers and related support personnel at a UNIX installahon can easily
·UNIX
15
1006·001
a trademark of Bell Laboratones.
transfer their knowledge of the UNIX
environment to the 28000 development
proJect. The result IS that programmers
become productive more qUIckly. And,
there IS a greater likelihood of the project finishing on schedule.
The C language, hke other highlevel, machine-Independent, systems
Implementation languages, Improves
programmer produchvity and protects
the software Investment made in a product by assuring program transportabihty. In addItion. C produces 28000
code which is efhclent both in terms of
execuhon hme and memory space
used. The result IS a lower cost, hIgher
performance product.
The development envIronment supported by the 28000 CSP allows for
multiple user software development on
various 28000 target systems (see hgure
below). The pass-through mode of the
28000 Development Module enables
any terminal connected to the host
system to be a hardware and software
evaluation stahon. In thIS mode, the
terminal and the host system communicate directly as If the 28000
Development Module were not present.
Thus, each terminal on a host system
can text edIt and compIle programs
and then download them Into a
development module for testing.
The pass-through mode of the development module offers a more effective
means of debugging than software
emulation because programs can be
debugged in real-time on actual hardware, without requiring any host
system resources. New 2110g emulahon
products, such as 2-SCAN 8000, wlll
continue to use the pass-through mode
to commumcate to the host system.
Thus, a single host system WIth 2110g's
development modules, emulahon products. and the 28000 CSP can support
total product development.
503
PRODUCT DESCRIPTION
The major pIeces of software m the
28000 CSP are the C compiler, C optimIzer, 28000 cross-assembler, 28000
cross-linker, upload/download program
for the 28000 Development Module,
and C run-time support environment
for the 28000 Development Module.
The 28000 C compIler IS the portable
PDP-II C compIler from the Seventh
Edition of the UNIX system modIfied to
generate 28000 code. This means that
eXIsting PDP-II C programs can be
compiled by the 28000 C compIler
and, if the programs are machmemdependent, they WIll run on a 28000
target system. The C compIler presently generates non-segmented 28000
code; segmented code will be supported later.
The C optimizer speed optimIzes the
code produced by the compiler and
outputs 28000 cross-assembler source
code. ThIs process YIelds an assembly
language lIsting of the optimIzed code.
The 28000 cross-assembler accepts
2ilog's standard mnemomcs and uses
the pseudo-operatIons familIar to UNIX
assembly language programmers. It
supports programs with combined or
separate code and data spaces. The
28000 cross-linker lInks cross-assembler
and C program modules together.
The upload/download program transfers programs and data between the
.~:. ~
CRT
~_
5iJ
1LfIl"~
28000 target system and the UNIX host
using Tektronix hex format. The C runtIme support environment prOVIdes the
necessary facilities to run sophisticated
C programs on the 28000 Development
Module. Because It mcludes routmes
for terminal and UNIX file access,
sigmficant software development can
take place usmg C and the 28000
Development Module.
The 28000 Cross-Software Package
combines with the UNIX operating
system to provide a complete development environment for 28000 software.
,i',"
_______
~ ~
~_----:- ZS_CAN8000_gjRT
CRQdl ~
tl
POPll
/
Z8000
\
UNIX, V7
zaooo csp
Z8000
~
I
9
C
1£Jf
OEVELOPMENT
DEVELOPMENTj----,
MODULE
~ R=T-~-~
MODULE
I
jI;}J)RT
Typical Z8000 Cross-Software Package Installation
ORDERING INFORMATION
Soitware (ContInued)
PREREQUISITES
Part Number
07-3341-01
All software is distrIbuted on one reel
of magnetIc tape recorded at 800 BPI.
• License for the Seventh EdItIon of
the UNIX operating system.
Description
zaooo Cross-Software Package.
includes:
Documentation
Soitware
• 28000 C compIler
• The C Programmmg Language
Manual
• One of the followmg computers from
DIgital Equipment CorporatIon:
PDP 11144
PDP 11145
PDP 11170
• 28000 C code optimIzer
• 28000 CPU Techmcal Manual
• 28000 cross-assembler
• 28000 Cross-Software Package
User's GUIde
License Requirement
• A specIal lIcense is reqUIred for
28000 Cross-Software Package
• 28000 cross-Imker
• Upload/download program
• C run-tIme support envIronment
504
1006-002
00-1006-A
Zilog Technical Training
~
Zilog
Courses for All Zilog
Components and Systems
March 1981
Time and money: precious commodities in the 1980's. There never
seems to be enough to get the job
done. At Zilog, our wide range of
innovative components and systems
helps you get the edge on your
competitors by redUCing both
system design costs and time. Now
Zilog's Training and Education
Department can help you turn the
clock back even further by saving
on those costly hours spent getting
up to speed.
Zilog offers sophishcated
microcomputer products in every
form-from microprocessor components and development systems
to OEM boards and general-
purpose microcomputer systems.
And to give you the knowledge
necessary to take full advantage of
these products, we also offer
thorough training programs geared
for the design engineer.
Zilog courses offer an informal
hands-on, mteractive approach
that takes you where you need to
be: up to speed in the qUIckest,
most effiCIent way. Each course
enhances your ability to use
individual Zilog products effectively . You get all the mformahon you
want and need.
The Zilog Traming and Educahon Department offers an exceptionally wide range of courses.
This sechon describes them in
detail.
Because enrollment is limited,
register at least five weeks before
class start date. Classes cancelled
less than 15 days before class start
date are subject to a $100 cancellation fee.
Zllog offers discounts to compames with three or more students
attending any given course.
On request, Zilog also offers onsite courses at a customer's plant.
For schedules and enrollment
mformation, call the Zilog Training
and Education Department at (408)
446-4666.
507
Microprocessors:
A General
Introduction
T
his course introduces the world of microprocessors.
In it you will learn basic microprocessor fundamentals and capabilities as well as the basics of
microcomputer-based design. Some of the topics
covered include:
V' What is a microprocessor?
V' Some fundamental concepts about microprocessors
V' Microprocessor organization
V' Instruction execution
V' Memories, central processing units, support chips
V' Microprocessor interfacing
V' Programming a microprocessor
Length: Three days
Tuition: $450
Order Number:
05·0008·00
A background in digital electronics is helpful but not
necessary.
Z8D Component
Family
This basic course on Z80 components is designed for hardware and software development personnel with a modest
background in microprocessors and assembly language
programming. This course should be taken by anyone
interested in effectively using the Z80 family of products.
Some topics covered are:
V' ZaD architecture and timing
V' ZaD assembly language programming
V' ZaD interrupt processing (interfacing
non-Zilog peripherals)
V' ZaD PIO Parallel I/O Controller
V' ZaD CTC Counter/Timer Controller
V' ZaD DMA Direct Memory Access Controller
This course offers a "hands-on" approach to learning by
doing. As each chip is covered, students measure their
progress by programming a single-board computer in
the laboratory.
A general microcomputer course or eqUivalent experience
is suggested as a course prerequisite.
508
Length: Four days
Tuition: $595
Order Number:
05·1001·0B
Z8000
Component
Family
Zilog's basic course on the Z8000 family of components is
for hardware and software development personnel who are
familiar with microprocessor system design. Anyone
interested in effectively using the Z8000 family of products
should take this course. Some of the topics covered include:
", Z8000 architecture and timing
", Z8000 assembly language programming
", Z8010 MMU Memory Management Unit
", Z-BUS peripheral interfacing
", Z8000 peripheral devices (CIO, FlO, SCC, and UPC)
", Z8000 software development tools
", Z8000 Development Module and other support products
Length: Four days
Tuition: $595
Order Number:
05-1001·09
A general microcomputer course or equivalent experience
is suggested as a course prerequisite.
Z8 Component
Family
The Z8 is Zilog's powerful single-chip, 8-bit microcomputer.
This seminar is designed for hardware and software development personnel who are familiar WIth microcomputer system
design and who are interested in learning Z8 architecture,
capabilities, and supporting systems. Some of the topics
covered are:
", Z8 architecture and timing
", Z8 assembly language programming
", Interfacing memory and peripheral devices
", Z8 software development tools
", Z8 Development Module and other supporting products
Length: Three days
Tuition: $450
Order Number:
05·1001-06
Designers interested in using the Z8034 UPC Universal Peripheral Controller should also attend this seminar, smce the
architecture of the UPC IS very similar to that of the 28.
A general microcomputer course or equivalent experience
is suggested as a course prerequisite.
509
ZDS and PDS
Operating
Systems
The needs of both the new Zilog system user and the experienced designer are met in this Z80-based systems course.
The full range of ZDS and PDS microcomputer systems
is described. Emphasis is placed on RIO, the Zilog
operating system. Some topics covered are:
J/ ZDS and PDS hardware
J/ ZaG assembler, linker, debugger, editor
J/ Advanced debugging techniques (symbolic
debugging ZBUG and NBUG)
J/ Elements of RIO-the ZDS and PDS operating system
J/ RIO structure-making system calls
J/ RIO floppy-disk driver-ZDOS
J/ Device drivers-printers, consoles
Order Number:
05·1001-02
This course provides a "hands-on" approach to learning by
dOing. As each portion of the operating system is covered in
lecture, students can measure their progress by writing their
own programs in class.
A Z80 component class or eqUivalent Z80 assembly language
experience is suggested as a course prerequisite.
MCZ-2
Systems
This Z80A-based systems course introduces the systems
user to MCZ-2 local network microcomputer systems
architecture and operation. The full range of MCZ-2 systems
is described, with emphasis placed on RIO/CP, Zilog's multitasking operating system. Some topiCS covered are:
J/ RIO/CP (Concurrent Processing) multitasking
operating system
J/ MCZ-2 System Kernel-dispatcher for
multitasking environment
J/ Logical I/O mapping
J/ RIO/CP floppy disk driver-FFS
J/ COBOL calls to assembler
J/ Z-NET philosphy and local networking concepts
A Z80 component class or equivalent Z80 assembly language
experience is suggested as a course prerequisite.
510
Length: Four days
Tuition: $595
Order Number:
05-0009-00
PLZ/SYS
Programming
The PLZ programming seminar is for programmers who
need language tools that permit methodical and wellorganized programs. PLZ, Zilog's Pascal-like language,
includes the PLZlSYS (high level, user-oriented) and
PLZlASM (a structu~ed assembly language) elements.
Some topics covered in this seminar are:
v' Program structure
v' Data types-simple and structured
v' Recursive programming
v' Pointers and linked lists
v' System 1/0 calls
v' Comparison of programming languages
v' Protocols for communicating with other languages
v' The PLZ symbolic Debugging Tool (PDT)
Length: Four days
Tuition: $595
ZDS-1/40
Development
System
This seminar describes zao emulation using the ZDS-l/40
development system. Description of the ZDS-1/40 emphasizes those aspects of the development system that affect
the emulation process. Some of the topics covered include:
v' ZDS-l/40 hardware design
v' zao system design hints to aid the emulation process
v' The Zilog Analyzer Program (ZAP)
v' The RIO Hardware Emulation Driver (RHED)
Length: One day
Tuition: $150
Order Number:
05-1001·04
Order Number:
05·1001·03
This course is recommended for designers of zao systems
where the emulation process is used as a development tool,
as well as for engineers who are directly involved in zao
emulation.
A zao component class or equivalent zao assembly language
experience is suggested as a course prerequisite.
511
Data
Communications
Concepts
This course provides the engineer with a thorough background in the terminology and operating concepts of data
communications. Some of the topics covered are:
,; Line protocols, telecommunications codes
(ASCII, EBCDIC, BCD)
,; Asynchronous and synchronous transmission
,; Error Detection, CRC and parity codes
,; Half and full duplex concepts
,; Modems; RS232C and RS449 specifications
,; Introduction to protocols-Bisync, SDLC, X.25, DDCMP
,; Introduction to networking
Length: Four days
Tuition: $595
Order Number:
05-0010-00
Zilog offers a variety of solutions to data communications
support problems. This course also offers an overview of
Zilog's SIO and SCC data communication controllers, and a
description of Zilog's ASYNC and 2780/3780 emulator.
Z8D OEM Board
Family
Component
Course
This component-level course is offered for the OEM or large
volume end user who needs to know component level
theory, maintenance, and repair techniques for the Zilog
MCB series boards. Some of the topics covered are:
,; MCB (MicroComputer Board) theory and repair
,; MDC (Memory Disc Controller) theory and repair
,; SIB (Serial Interface Board) theory and repair
,; HDC (Hard Disk Controller Boards) theory and repair
The Zilog Training and Education Department can offer a
variety of special hardware classes, each tailored to your
needs. Call Zilog's Training and Education Department at
(408) 446-4666 for further information.
512
Length: Four days
Tuition: $895
(offered on requesl)
Z8000 Architecture
Correspondence
Course
Z
ilog's generation-ahead, 16-bit Z8000 is
changing the way systems manufacturers
and designers think about microprocessing.
Now there's an easy way for you to learn everything
you need to know to stay on top of this powerful new
technology. Enroll today In Zllog's five-part, homestudy seminar on Z8000 architecture for the advanced
engineer. Learn the details of the Z8000's 16-bit
architecture, techmques of memory management,
methods of interfacing memory and peripherals, proper
handling of Interrupts and traps, and use of the Z8000's
powerful instruction set.
Length: 5 Lessons
Tuition: $39
Order Number:
05-0007-00
You study at your own pace at home. Each lesson
Includes a test consisting of ten questions which IS
individually graded and critiqued. The total cost for all
course materials and tests is $39. (On completion of
this course, every registrant gets a colorful Captain
Zilog T-shirt!) Become your company's expert on the
microprocessor technology of the future. Allow up to
SIX weeks for receipt of your first lesson.
Lesson 1
Introduces the Z8000 architecture, starting with a
description of the function of each signal pin on the
Z8001 and Z8002 processors. The Z8000 register structure
IS examined in detail, followed by a discussion of the
Z8000's eight basic operand addressing modes. Some
basic system considerations, such as initialization
requirements, are also Introduced.
Lesson 2
Concentrates on memory and peripheral interfacing.
The memory organization for a tYPical Z8000 system is
described, leading to an examination of the memory
control circUitry necessary to support the Z8000's
powerful 16-bit architecture. Hardware deSign
considerations, such as address/data bus buffering, are
included In this lesson. Basic Instruction timing IS
analyzed, with emphaSIS on memory and peripheral
access timing.
Lesson 3
Provides a detailed discussion of Interrupts, traps, and
other context switching within a Z8000 system. The
concept of program status IS introduced, and the methods
of changing program status through context switching
are analyzed. Both the hardware and software considerations necessary for proper handling of interrupts and traps
are investigated.
Lesson 4
Studies the concepts of memory and peripheral
management. Memory segmentation in Z8000 systems is
examined, Including an analYSIS of the reasons for uSing
memory segmentation as well as a discussion of possible
implementations. Peripheral management and resource
sharing In Z8000 systems are also explored.
Lesson 5
Offers an overview of the Z8000's powerful Instruction
set. After reviewing the operand addressing modes, the
instruction set IS divided into functional categories, and
the instructions in each category are described in detail.
513
514
I
I
~---------------------------------------~
Z
ilog
Training and Educahon
10460 Bubb Road, Cupertino, CA 95014
Z8000 Architecture Correspondence
Course Registration Card
Enroll me today In the 1981 Z,log ZSOOO Architecture Course (Order Number: 05-0007-00).
Enclosed IS my check or money order for $39 (no cash or purchase orders please). Make check payable to Zilog, Inc.
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r----------------------------------------
Z
il09
Trammg and Educahon
10460 Bubb Road, Cupertino, CA 95014
Z8000 Architecture Correspondence
Course Registration Card
Enroll me today In the 1981 Zilog Z8000 Architecture Course (Order Number' 05-0007-00).
Enclosed IS my check or money order for $39 (no cash or purchase orders please). Make check payable to Zilog, Inc.
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Please charge my 0 Mastercharge or 0 ViSa account: 0000000000000000
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Mail lessons to:
0
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My T-Shirt size IS:
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-Z~~ ------~l::,:0: ~=e:::~~ ::::c;:,:-Co;;-es::d.:.--~-Training and Education
10460 Bubb Road, Cupertmo, CA 95014
Course Registration Card
Enroll me today In the 1981 Zilog ZSOOO Architecture Course (Order Number: 05-0007-00).
Enclosed is my check or money order for $39 (no cash or purchase orders please). Make check payable to Zllog, Inc.
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516
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